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* cpu-m32c.c (m32c_scan): New function. Ensures that a scan for
[deliverable/binutils-gdb.git] / opcodes / i386-dis.c
CommitLineData
252b5132 1/* Print i386 instructions for GDB, the GNU debugger.
060d22b0 2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0bfee649 3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
0af1713e 4 Free Software Foundation, Inc.
252b5132 5
9b201bb5 6 This file is part of the GNU opcodes library.
20f0a1fc 7
9b201bb5 8 This library is free software; you can redistribute it and/or modify
20f0a1fc 9 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
20f0a1fc 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
20f0a1fc
NC		 17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
20f0a1fc
NC		 23
24/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
25 July 1988
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
29
30/* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
252b5132 36
252b5132 37#include "sysdep.h"
dabbade6 38#include "dis-asm.h"
252b5132 39#include "opintl.h"
0b1cf022 40#include "opcode/i386.h"
85f10a01 41#include "libiberty.h"
252b5132
RH		 42
43#include <setjmp.h>
44
26ca5450
AJ		 45static int print_insn (bfd_vma, disassemble_info *);
46static void dofloat (int);
47static void OP_ST (int, int);
48static void OP_STi (int, int);
49static int putop (const char *, int);
50static void oappend (const char *);
51static void append_seg (void);
52static void OP_indirE (int, int);
53static void print_operand_value (char *, int, bfd_vma);
c0f3af97 54static void OP_E_register (int, int);
c1e679ec 55static void OP_E_memory (int, int);
5d669648 56static void print_displacement (char *, bfd_vma);
26ca5450
AJ		 57static void OP_E (int, int);
58static void OP_G (int, int);
59static bfd_vma get64 (void);
60static bfd_signed_vma get32 (void);
61static bfd_signed_vma get32s (void);
62static int get16 (void);
63static void set_op (bfd_vma, int);
b844680a 64static void OP_Skip_MODRM (int, int);
26ca5450
AJ		 65static void OP_REG (int, int);
66static void OP_IMREG (int, int);
67static void OP_I (int, int);
68static void OP_I64 (int, int);
69static void OP_sI (int, int);
70static void OP_J (int, int);
71static void OP_SEG (int, int);
72static void OP_DIR (int, int);
73static void OP_OFF (int, int);
74static void OP_OFF64 (int, int);
75static void ptr_reg (int, int);
76static void OP_ESreg (int, int);
77static void OP_DSreg (int, int);
78static void OP_C (int, int);
79static void OP_D (int, int);
80static void OP_T (int, int);
6f74c397 81static void OP_R (int, int);
26ca5450
AJ		 82static void OP_MMX (int, int);
83static void OP_XMM (int, int);
84static void OP_EM (int, int);
85static void OP_EX (int, int);
4d9567e0
MM		 86static void OP_EMC (int,int);
87static void OP_MXC (int,int);
26ca5450
AJ		 88static void OP_MS (int, int);
89static void OP_XS (int, int);
cc0ec051 90static void OP_M (int, int);
c0f3af97
L		 91static void OP_VEX (int, int);
92static void OP_EX_Vex (int, int);
922d8de8 93static void OP_EX_VexW (int, int);
c0f3af97 94static void OP_XMM_Vex (int, int);
922d8de8 95static void OP_XMM_VexW (int, int);
c0f3af97
L		 96static void OP_REG_VexI4 (int, int);
97static void PCLMUL_Fixup (int, int);
922d8de8 98static void VEXI4_Fixup (int, int);
c0f3af97
L		 99static void VZERO_Fixup (int, int);
100static void VCMP_Fixup (int, int);
cc0ec051 101static void OP_0f07 (int, int);
b844680a
L		 102static void OP_Monitor (int, int);
103static void OP_Mwait (int, int);
46e883c5
L		 104static void NOP_Fixup1 (int, int);
105static void NOP_Fixup2 (int, int);
26ca5450 106static void OP_3DNowSuffix (int, int);
ad19981d 107static void CMP_Fixup (int, int);
26ca5450 108static void BadOp (void);
35c52694 109static void REP_Fixup (int, int);
f5804c90 110static void CMPXCHG8B_Fixup (int, int);
42903f7f 111static void XMM_Fixup (int, int);
381d071f 112static void CRC32_Fixup (int, int);
eacc9c89 113static void FXSAVE_Fixup (int, int);
f88c9eb0
SP		 114static void OP_LWPCB_E (int, int);
115static void OP_LWP_E (int, int);
116static void OP_LWP_I (int, int);
5dd85c99
SP		 117static void OP_Vex_2src_1 (int, int);
118static void OP_Vex_2src_2 (int, int);
c1e679ec 119
f1f8f695 120static void MOVBE_Fixup (int, int);
252b5132 121
6608db57 122struct dis_private {
252b5132
RH		 123 /* Points to first byte not fetched. */
124 bfd_byte *max_fetched;
0b1cf022 125 bfd_byte the_buffer[MAX_MNEM_SIZE];
252b5132 126 bfd_vma insn_start;
e396998b 127 int orig_sizeflag;
252b5132
RH		 128 jmp_buf bailout;
129};
130
cb712a9e
L		 131enum address_mode
132{
133 mode_16bit,
134 mode_32bit,
135 mode_64bit
136};
137
138enum address_mode address_mode;
52b15da3 139
5076851f
ILT		 140/* Flags for the prefixes for the current instruction. See below. */
141static int prefixes;
142
52b15da3
JH		 143/* REX prefix the current instruction. See below. */
144static int rex;
145/* Bits of REX we've already used. */
146static int rex_used;
d869730d 147/* REX bits in original REX prefix ignored. */
c0f3af97 148static int rex_ignored;
52b15da3
JH		 149/* Mark parts used in the REX prefix. When we are testing for
150 empty prefix (for 8bit register REX extension), just mask it
151 out. Otherwise test for REX bit is excuse for existence of REX
152 only in case value is nonzero. */
153#define USED_REX(value) \
154 { \
155 if (value) \
161a04f6
L		 156 { \
157 if ((rex & value)) \
158 rex_used |= (value) | REX_OPCODE; \
159 } \
52b15da3 160 else \
161a04f6 161 rex_used |= REX_OPCODE; \
52b15da3
JH		 162 }
163
7d421014
ILT		 164/* Flags for prefixes which we somehow handled when printing the
165 current instruction. */
166static int used_prefixes;
167
5076851f
ILT		 168/* Flags stored in PREFIXES. */
169#define PREFIX_REPZ 1
170#define PREFIX_REPNZ 2
171#define PREFIX_LOCK 4
172#define PREFIX_CS 8
173#define PREFIX_SS 0x10
174#define PREFIX_DS 0x20
175#define PREFIX_ES 0x40
176#define PREFIX_FS 0x80
177#define PREFIX_GS 0x100
178#define PREFIX_DATA 0x200
179#define PREFIX_ADDR 0x400
180#define PREFIX_FWAIT 0x800
181
252b5132
RH		 182/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
183 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
184 on error. */
185#define FETCH_DATA(info, addr) \
6608db57 186 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
252b5132
RH		 187 ? 1 : fetch_data ((info), (addr)))
188
189static int
26ca5450 190fetch_data (struct disassemble_info *info, bfd_byte *addr)
252b5132
RH		 191{
192 int status;
6608db57 193 struct dis_private *priv = (struct dis_private *) info->private_data;
252b5132
RH		 194 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
195
0b1cf022 196 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
272c9217
JB		 197 status = (*info->read_memory_func) (start,
198 priv->max_fetched,
199 addr - priv->max_fetched,
200 info);
201 else
202 status = -1;
252b5132
RH		 203 if (status != 0)
204 {
7d421014 205 /* If we did manage to read at least one byte, then
db6eb5be
AM		 206 print_insn_i386 will do something sensible. Otherwise, print
207 an error. We do that here because this is where we know
208 STATUS. */
7d421014 209 if (priv->max_fetched == priv->the_buffer)
5076851f 210 (*info->memory_error_func) (status, start, info);
252b5132
RH		 211 longjmp (priv->bailout, 1);
212 }
213 else
214 priv->max_fetched = addr;
215 return 1;
216}
217
ce518a5f
L		 218#define XX { NULL, 0 }
219
220#define Eb { OP_E, b_mode }
b6169b20 221#define EbS { OP_E, b_swap_mode }
ce518a5f 222#define Ev { OP_E, v_mode }
b6169b20 223#define EvS { OP_E, v_swap_mode }
ce518a5f
L		 224#define Ed { OP_E, d_mode }
225#define Edq { OP_E, dq_mode }
226#define Edqw { OP_E, dqw_mode }
42903f7f
L		 227#define Edqb { OP_E, dqb_mode }
228#define Edqd { OP_E, dqd_mode }
09335d05 229#define Eq { OP_E, q_mode }
ce518a5f
L		 230#define indirEv { OP_indirE, stack_v_mode }
231#define indirEp { OP_indirE, f_mode }
232#define stackEv { OP_E, stack_v_mode }
233#define Em { OP_E, m_mode }
234#define Ew { OP_E, w_mode }
235#define M { OP_M, 0 } /* lea, lgdt, etc. */
34b772a6 236#define Ma { OP_M, a_mode }
b844680a 237#define Mb { OP_M, b_mode }
d9a5e5e5 238#define Md { OP_M, d_mode }
f1f8f695 239#define Mo { OP_M, o_mode }
ce518a5f
L		 240#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
241#define Mq { OP_M, q_mode }
4ee52178 242#define Mx { OP_M, x_mode }
c0f3af97 243#define Mxmm { OP_M, xmm_mode }
ce518a5f
L		 244#define Gb { OP_G, b_mode }
245#define Gv { OP_G, v_mode }
246#define Gd { OP_G, d_mode }
247#define Gdq { OP_G, dq_mode }
248#define Gm { OP_G, m_mode }
249#define Gw { OP_G, w_mode }
6f74c397
L		 250#define Rd { OP_R, d_mode }
251#define Rm { OP_R, m_mode }
ce518a5f
L		 252#define Ib { OP_I, b_mode }
253#define sIb { OP_sI, b_mode } /* sign extened byte */
254#define Iv { OP_I, v_mode }
255#define Iq { OP_I, q_mode }
256#define Iv64 { OP_I64, v_mode }
257#define Iw { OP_I, w_mode }
258#define I1 { OP_I, const_1_mode }
259#define Jb { OP_J, b_mode }
260#define Jv { OP_J, v_mode }
261#define Cm { OP_C, m_mode }
262#define Dm { OP_D, m_mode }
263#define Td { OP_T, d_mode }
b844680a 264#define Skip_MODRM { OP_Skip_MODRM, 0 }
ce518a5f
L		 265
266#define RMeAX { OP_REG, eAX_reg }
267#define RMeBX { OP_REG, eBX_reg }
268#define RMeCX { OP_REG, eCX_reg }
269#define RMeDX { OP_REG, eDX_reg }
270#define RMeSP { OP_REG, eSP_reg }
271#define RMeBP { OP_REG, eBP_reg }
272#define RMeSI { OP_REG, eSI_reg }
273#define RMeDI { OP_REG, eDI_reg }
274#define RMrAX { OP_REG, rAX_reg }
275#define RMrBX { OP_REG, rBX_reg }
276#define RMrCX { OP_REG, rCX_reg }
277#define RMrDX { OP_REG, rDX_reg }
278#define RMrSP { OP_REG, rSP_reg }
279#define RMrBP { OP_REG, rBP_reg }
280#define RMrSI { OP_REG, rSI_reg }
281#define RMrDI { OP_REG, rDI_reg }
282#define RMAL { OP_REG, al_reg }
283#define RMAL { OP_REG, al_reg }
284#define RMCL { OP_REG, cl_reg }
285#define RMDL { OP_REG, dl_reg }
286#define RMBL { OP_REG, bl_reg }
287#define RMAH { OP_REG, ah_reg }
288#define RMCH { OP_REG, ch_reg }
289#define RMDH { OP_REG, dh_reg }
290#define RMBH { OP_REG, bh_reg }
291#define RMAX { OP_REG, ax_reg }
292#define RMDX { OP_REG, dx_reg }
293
294#define eAX { OP_IMREG, eAX_reg }
295#define eBX { OP_IMREG, eBX_reg }
296#define eCX { OP_IMREG, eCX_reg }
297#define eDX { OP_IMREG, eDX_reg }
298#define eSP { OP_IMREG, eSP_reg }
299#define eBP { OP_IMREG, eBP_reg }
300#define eSI { OP_IMREG, eSI_reg }
301#define eDI { OP_IMREG, eDI_reg }
302#define AL { OP_IMREG, al_reg }
303#define CL { OP_IMREG, cl_reg }
304#define DL { OP_IMREG, dl_reg }
305#define BL { OP_IMREG, bl_reg }
306#define AH { OP_IMREG, ah_reg }
307#define CH { OP_IMREG, ch_reg }
308#define DH { OP_IMREG, dh_reg }
309#define BH { OP_IMREG, bh_reg }
310#define AX { OP_IMREG, ax_reg }
311#define DX { OP_IMREG, dx_reg }
312#define zAX { OP_IMREG, z_mode_ax_reg }
313#define indirDX { OP_IMREG, indir_dx_reg }
314
315#define Sw { OP_SEG, w_mode }
316#define Sv { OP_SEG, v_mode }
317#define Ap { OP_DIR, 0 }
318#define Ob { OP_OFF64, b_mode }
319#define Ov { OP_OFF64, v_mode }
320#define Xb { OP_DSreg, eSI_reg }
321#define Xv { OP_DSreg, eSI_reg }
322#define Xz { OP_DSreg, eSI_reg }
323#define Yb { OP_ESreg, eDI_reg }
324#define Yv { OP_ESreg, eDI_reg }
325#define DSBX { OP_DSreg, eBX_reg }
326
327#define es { OP_REG, es_reg }
328#define ss { OP_REG, ss_reg }
329#define cs { OP_REG, cs_reg }
330#define ds { OP_REG, ds_reg }
331#define fs { OP_REG, fs_reg }
332#define gs { OP_REG, gs_reg }
333
334#define MX { OP_MMX, 0 }
335#define XM { OP_XMM, 0 }
c0f3af97 336#define XMM { OP_XMM, xmm_mode }
ce518a5f 337#define EM { OP_EM, v_mode }
b6169b20 338#define EMS { OP_EM, v_swap_mode }
09a2c6cf 339#define EMd { OP_EM, d_mode }
14051056 340#define EMx { OP_EM, x_mode }
8976381e 341#define EXw { OP_EX, w_mode }
09a2c6cf 342#define EXd { OP_EX, d_mode }
fa99fab2 343#define EXdS { OP_EX, d_swap_mode }
09a2c6cf 344#define EXq { OP_EX, q_mode }
b6169b20 345#define EXqS { OP_EX, q_swap_mode }
09a2c6cf 346#define EXx { OP_EX, x_mode }
b6169b20 347#define EXxS { OP_EX, x_swap_mode }
c0f3af97
L		 348#define EXxmm { OP_EX, xmm_mode }
349#define EXxmmq { OP_EX, xmmq_mode }
350#define EXymmq { OP_EX, ymmq_mode }
0bfee649 351#define EXVexWdq { OP_EX, vex_w_dq_mode }
ce518a5f
L		 352#define MS { OP_MS, v_mode }
353#define XS { OP_XS, v_mode }
09335d05 354#define EMCq { OP_EMC, q_mode }
ce518a5f 355#define MXC { OP_MXC, 0 }
ce518a5f 356#define OPSUF { OP_3DNowSuffix, 0 }
ad19981d 357#define CMP { CMP_Fixup, 0 }
42903f7f 358#define XMM0 { XMM_Fixup, 0 }
eacc9c89 359#define FXSAVE { FXSAVE_Fixup, 0 }
5dd85c99
SP		 360#define Vex_2src_1 { OP_Vex_2src_1, 0 }
361#define Vex_2src_2 { OP_Vex_2src_2, 0 }
252b5132 362
c0f3af97
L		 363#define Vex { OP_VEX, vex_mode }
364#define Vex128 { OP_VEX, vex128_mode }
365#define Vex256 { OP_VEX, vex256_mode }
922d8de8 366#define VexI4 { VEXI4_Fixup, 0}
c0f3af97 367#define EXdVex { OP_EX_Vex, d_mode }
fa99fab2 368#define EXdVexS { OP_EX_Vex, d_swap_mode }
c0f3af97 369#define EXqVex { OP_EX_Vex, q_mode }
fa99fab2 370#define EXqVexS { OP_EX_Vex, q_swap_mode }
922d8de8
DR		 371#define EXVexW { OP_EX_VexW, x_mode }
372#define EXdVexW { OP_EX_VexW, d_mode }
373#define EXqVexW { OP_EX_VexW, q_mode }
c0f3af97 374#define XMVex { OP_XMM_Vex, 0 }
922d8de8 375#define XMVexW { OP_XMM_VexW, 0 }
c0f3af97
L		 376#define XMVexI4 { OP_REG_VexI4, x_mode }
377#define PCLMUL { PCLMUL_Fixup, 0 }
378#define VZERO { VZERO_Fixup, 0 }
379#define VCMP { VCMP_Fixup, 0 }
c0f3af97 380
35c52694 381/* Used handle "rep" prefix for string instructions. */
ce518a5f
L		 382#define Xbr { REP_Fixup, eSI_reg }
383#define Xvr { REP_Fixup, eSI_reg }
384#define Ybr { REP_Fixup, eDI_reg }
385#define Yvr { REP_Fixup, eDI_reg }
386#define Yzr { REP_Fixup, eDI_reg }
387#define indirDXr { REP_Fixup, indir_dx_reg }
388#define ALr { REP_Fixup, al_reg }
389#define eAXr { REP_Fixup, eAX_reg }
390
391#define cond_jump_flag { NULL, cond_jump_mode }
392#define loop_jcxz_flag { NULL, loop_jcxz_mode }
3ffd33cf 393
252b5132 394/* bits in sizeflag */
252b5132 395#define SUFFIX_ALWAYS 4
252b5132
RH		 396#define AFLAG 2
397#define DFLAG 1
398
51e7da1b
L		 399enum
400{
401 /* byte operand */
402 b_mode = 1,
403 /* byte operand with operand swapped */
3873ba12 404 b_swap_mode,
51e7da1b 405 /* operand size depends on prefixes */
3873ba12 406 v_mode,
51e7da1b 407 /* operand size depends on prefixes with operand swapped */
3873ba12 408 v_swap_mode,
51e7da1b 409 /* word operand */
3873ba12 410 w_mode,
51e7da1b 411 /* double word operand */
3873ba12 412 d_mode,
51e7da1b 413 /* double word operand with operand swapped */
3873ba12 414 d_swap_mode,
51e7da1b 415 /* quad word operand */
3873ba12 416 q_mode,
51e7da1b 417 /* quad word operand with operand swapped */
3873ba12 418 q_swap_mode,
51e7da1b 419 /* ten-byte operand */
3873ba12 420 t_mode,
51e7da1b 421 /* 16-byte XMM or 32-byte YMM operand */
3873ba12 422 x_mode,
51e7da1b 423 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
3873ba12 424 x_swap_mode,
51e7da1b 425 /* 16-byte XMM operand */
3873ba12 426 xmm_mode,
51e7da1b 427 /* 16-byte XMM or quad word operand */
3873ba12 428 xmmq_mode,
51e7da1b 429 /* 32-byte YMM or quad word operand */
3873ba12 430 ymmq_mode,
51e7da1b 431 /* d_mode in 32bit, q_mode in 64bit mode. */
3873ba12 432 m_mode,
51e7da1b 433 /* pair of v_mode operands */
3873ba12
L		 434 a_mode,
435 cond_jump_mode,
436 loop_jcxz_mode,
51e7da1b 437 /* operand size depends on REX prefixes. */
3873ba12 438 dq_mode,
51e7da1b 439 /* registers like dq_mode, memory like w_mode. */
3873ba12 440 dqw_mode,
51e7da1b 441 /* 4- or 6-byte pointer operand */
3873ba12
L		 442 f_mode,
443 const_1_mode,
51e7da1b 444 /* v_mode for stack-related opcodes. */
3873ba12 445 stack_v_mode,
51e7da1b 446 /* non-quad operand size depends on prefixes */
3873ba12 447 z_mode,
51e7da1b 448 /* 16-byte operand */
3873ba12 449 o_mode,
51e7da1b 450 /* registers like dq_mode, memory like b_mode. */
3873ba12 451 dqb_mode,
51e7da1b 452 /* registers like dq_mode, memory like d_mode. */
3873ba12 453 dqd_mode,
51e7da1b 454 /* normal vex mode */
3873ba12 455 vex_mode,
51e7da1b 456 /* 128bit vex mode */
3873ba12 457 vex128_mode,
51e7da1b 458 /* 256bit vex mode */
3873ba12 459 vex256_mode,
51e7da1b 460 /* operand size depends on the VEX.W bit. */
3873ba12 461 vex_w_dq_mode,
d55ee72f 462
3873ba12
L		 463 es_reg,
464 cs_reg,
465 ss_reg,
466 ds_reg,
467 fs_reg,
468 gs_reg,
d55ee72f 469
3873ba12
L		 470 eAX_reg,
471 eCX_reg,
472 eDX_reg,
473 eBX_reg,
474 eSP_reg,
475 eBP_reg,
476 eSI_reg,
477 eDI_reg,
d55ee72f 478
3873ba12
L		 479 al_reg,
480 cl_reg,
481 dl_reg,
482 bl_reg,
483 ah_reg,
484 ch_reg,
485 dh_reg,
486 bh_reg,
d55ee72f 487
3873ba12
L		 488 ax_reg,
489 cx_reg,
490 dx_reg,
491 bx_reg,
492 sp_reg,
493 bp_reg,
494 si_reg,
495 di_reg,
d55ee72f 496
3873ba12
L		 497 rAX_reg,
498 rCX_reg,
499 rDX_reg,
500 rBX_reg,
501 rSP_reg,
502 rBP_reg,
503 rSI_reg,
504 rDI_reg,
d55ee72f 505
3873ba12
L		 506 z_mode_ax_reg,
507 indir_dx_reg
51e7da1b 508};
252b5132 509
51e7da1b
L		 510enum
511{
512 FLOATCODE = 1,
3873ba12
L		 513 USE_REG_TABLE,
514 USE_MOD_TABLE,
515 USE_RM_TABLE,
516 USE_PREFIX_TABLE,
517 USE_X86_64_TABLE,
518 USE_3BYTE_TABLE,
f88c9eb0 519 USE_XOP_8F_TABLE,
3873ba12
L		 520 USE_VEX_C4_TABLE,
521 USE_VEX_C5_TABLE,
9e30b8e0
L		 522 USE_VEX_LEN_TABLE,
523 USE_VEX_W_TABLE
51e7da1b 524};
6439fc28 525
1ceb70f8 526#define FLOAT NULL, { { NULL, FLOATCODE } }
4efba78c 527
4e7d34a6 528#define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
1ceb70f8
L		 529#define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
530#define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
531#define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
532#define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
4e7d34a6
L		 533#define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
534#define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
f88c9eb0 535#define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
c0f3af97
L		 536#define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
537#define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
538#define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
9e30b8e0 539#define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
1ceb70f8 540
51e7da1b
L		 541enum
542{
543 REG_80 = 0,
3873ba12
L		 544 REG_81,
545 REG_82,
546 REG_8F,
547 REG_C0,
548 REG_C1,
549 REG_C6,
550 REG_C7,
551 REG_D0,
552 REG_D1,
553 REG_D2,
554 REG_D3,
555 REG_F6,
556 REG_F7,
557 REG_FE,
558 REG_FF,
559 REG_0F00,
560 REG_0F01,
561 REG_0F0D,
562 REG_0F18,
563 REG_0F71,
564 REG_0F72,
565 REG_0F73,
566 REG_0FA6,
567 REG_0FA7,
568 REG_0FAE,
569 REG_0FBA,
570 REG_0FC7,
571 REG_VEX_71,
572 REG_VEX_72,
573 REG_VEX_73,
f88c9eb0
SP		 574 REG_VEX_AE,
575 REG_XOP_LWPCB,
576 REG_XOP_LWP
51e7da1b 577};
1ceb70f8 578
51e7da1b
L		 579enum
580{
581 MOD_8D = 0,
3873ba12
L		 582 MOD_0F01_REG_0,
583 MOD_0F01_REG_1,
584 MOD_0F01_REG_2,
585 MOD_0F01_REG_3,
586 MOD_0F01_REG_7,
587 MOD_0F12_PREFIX_0,
588 MOD_0F13,
589 MOD_0F16_PREFIX_0,
590 MOD_0F17,
591 MOD_0F18_REG_0,
592 MOD_0F18_REG_1,
593 MOD_0F18_REG_2,
594 MOD_0F18_REG_3,
595 MOD_0F20,
596 MOD_0F21,
597 MOD_0F22,
598 MOD_0F23,
599 MOD_0F24,
600 MOD_0F26,
601 MOD_0F2B_PREFIX_0,
602 MOD_0F2B_PREFIX_1,
603 MOD_0F2B_PREFIX_2,
604 MOD_0F2B_PREFIX_3,
605 MOD_0F51,
606 MOD_0F71_REG_2,
607 MOD_0F71_REG_4,
608 MOD_0F71_REG_6,
609 MOD_0F72_REG_2,
610 MOD_0F72_REG_4,
611 MOD_0F72_REG_6,
612 MOD_0F73_REG_2,
613 MOD_0F73_REG_3,
614 MOD_0F73_REG_6,
615 MOD_0F73_REG_7,
616 MOD_0FAE_REG_0,
617 MOD_0FAE_REG_1,
618 MOD_0FAE_REG_2,
619 MOD_0FAE_REG_3,
620 MOD_0FAE_REG_4,
621 MOD_0FAE_REG_5,
622 MOD_0FAE_REG_6,
623 MOD_0FAE_REG_7,
624 MOD_0FB2,
625 MOD_0FB4,
626 MOD_0FB5,
627 MOD_0FC7_REG_6,
628 MOD_0FC7_REG_7,
629 MOD_0FD7,
630 MOD_0FE7_PREFIX_2,
631 MOD_0FF0_PREFIX_3,
632 MOD_0F382A_PREFIX_2,
633 MOD_62_32BIT,
634 MOD_C4_32BIT,
635 MOD_C5_32BIT,
636 MOD_VEX_12_PREFIX_0,
637 MOD_VEX_13,
638 MOD_VEX_16_PREFIX_0,
639 MOD_VEX_17,
640 MOD_VEX_2B,
976f1fde 641 MOD_VEX_50,
3873ba12
L		 642 MOD_VEX_71_REG_2,
643 MOD_VEX_71_REG_4,
644 MOD_VEX_71_REG_6,
645 MOD_VEX_72_REG_2,
646 MOD_VEX_72_REG_4,
647 MOD_VEX_72_REG_6,
648 MOD_VEX_73_REG_2,
649 MOD_VEX_73_REG_3,
650 MOD_VEX_73_REG_6,
651 MOD_VEX_73_REG_7,
652 MOD_VEX_AE_REG_2,
653 MOD_VEX_AE_REG_3,
654 MOD_VEX_D7_PREFIX_2,
655 MOD_VEX_E7_PREFIX_2,
656 MOD_VEX_F0_PREFIX_3,
657 MOD_VEX_3818_PREFIX_2,
658 MOD_VEX_3819_PREFIX_2,
659 MOD_VEX_381A_PREFIX_2,
660 MOD_VEX_382A_PREFIX_2,
661 MOD_VEX_382C_PREFIX_2,
662 MOD_VEX_382D_PREFIX_2,
663 MOD_VEX_382E_PREFIX_2,
664 MOD_VEX_382F_PREFIX_2
51e7da1b 665};
1ceb70f8 666
51e7da1b
L		 667enum
668{
669 RM_0F01_REG_0 = 0,
3873ba12
L		 670 RM_0F01_REG_1,
671 RM_0F01_REG_2,
672 RM_0F01_REG_3,
673 RM_0F01_REG_7,
674 RM_0FAE_REG_5,
675 RM_0FAE_REG_6,
676 RM_0FAE_REG_7
51e7da1b 677};
1ceb70f8 678
51e7da1b
L		 679enum
680{
681 PREFIX_90 = 0,
3873ba12
L		 682 PREFIX_0F10,
683 PREFIX_0F11,
684 PREFIX_0F12,
685 PREFIX_0F16,
686 PREFIX_0F2A,
687 PREFIX_0F2B,
688 PREFIX_0F2C,
689 PREFIX_0F2D,
690 PREFIX_0F2E,
691 PREFIX_0F2F,
692 PREFIX_0F51,
693 PREFIX_0F52,
694 PREFIX_0F53,
695 PREFIX_0F58,
696 PREFIX_0F59,
697 PREFIX_0F5A,
698 PREFIX_0F5B,
699 PREFIX_0F5C,
700 PREFIX_0F5D,
701 PREFIX_0F5E,
702 PREFIX_0F5F,
703 PREFIX_0F60,
704 PREFIX_0F61,
705 PREFIX_0F62,
706 PREFIX_0F6C,
707 PREFIX_0F6D,
708 PREFIX_0F6F,
709 PREFIX_0F70,
710 PREFIX_0F73_REG_3,
711 PREFIX_0F73_REG_7,
712 PREFIX_0F78,
713 PREFIX_0F79,
714 PREFIX_0F7C,
715 PREFIX_0F7D,
716 PREFIX_0F7E,
717 PREFIX_0F7F,
718 PREFIX_0FB8,
719 PREFIX_0FBD,
720 PREFIX_0FC2,
721 PREFIX_0FC3,
722 PREFIX_0FC7_REG_6,
723 PREFIX_0FD0,
724 PREFIX_0FD6,
725 PREFIX_0FE6,
726 PREFIX_0FE7,
727 PREFIX_0FF0,
728 PREFIX_0FF7,
729 PREFIX_0F3810,
730 PREFIX_0F3814,
731 PREFIX_0F3815,
732 PREFIX_0F3817,
733 PREFIX_0F3820,
734 PREFIX_0F3821,
735 PREFIX_0F3822,
736 PREFIX_0F3823,
737 PREFIX_0F3824,
738 PREFIX_0F3825,
739 PREFIX_0F3828,
740 PREFIX_0F3829,
741 PREFIX_0F382A,
742 PREFIX_0F382B,
743 PREFIX_0F3830,
744 PREFIX_0F3831,
745 PREFIX_0F3832,
746 PREFIX_0F3833,
747 PREFIX_0F3834,
748 PREFIX_0F3835,
749 PREFIX_0F3837,
750 PREFIX_0F3838,
751 PREFIX_0F3839,
752 PREFIX_0F383A,
753 PREFIX_0F383B,
754 PREFIX_0F383C,
755 PREFIX_0F383D,
756 PREFIX_0F383E,
757 PREFIX_0F383F,
758 PREFIX_0F3840,
759 PREFIX_0F3841,
760 PREFIX_0F3880,
761 PREFIX_0F3881,
762 PREFIX_0F38DB,
763 PREFIX_0F38DC,
764 PREFIX_0F38DD,
765 PREFIX_0F38DE,
766 PREFIX_0F38DF,
767 PREFIX_0F38F0,
768 PREFIX_0F38F1,
769 PREFIX_0F3A08,
770 PREFIX_0F3A09,
771 PREFIX_0F3A0A,
772 PREFIX_0F3A0B,
773 PREFIX_0F3A0C,
774 PREFIX_0F3A0D,
775 PREFIX_0F3A0E,
776 PREFIX_0F3A14,
777 PREFIX_0F3A15,
778 PREFIX_0F3A16,
779 PREFIX_0F3A17,
780 PREFIX_0F3A20,
781 PREFIX_0F3A21,
782 PREFIX_0F3A22,
783 PREFIX_0F3A40,
784 PREFIX_0F3A41,
785 PREFIX_0F3A42,
786 PREFIX_0F3A44,
787 PREFIX_0F3A60,
788 PREFIX_0F3A61,
789 PREFIX_0F3A62,
790 PREFIX_0F3A63,
791 PREFIX_0F3ADF,
792 PREFIX_VEX_10,
793 PREFIX_VEX_11,
794 PREFIX_VEX_12,
795 PREFIX_VEX_16,
796 PREFIX_VEX_2A,
797 PREFIX_VEX_2C,
798 PREFIX_VEX_2D,
799 PREFIX_VEX_2E,
800 PREFIX_VEX_2F,
801 PREFIX_VEX_51,
802 PREFIX_VEX_52,
803 PREFIX_VEX_53,
804 PREFIX_VEX_58,
805 PREFIX_VEX_59,
806 PREFIX_VEX_5A,
807 PREFIX_VEX_5B,
808 PREFIX_VEX_5C,
809 PREFIX_VEX_5D,
810 PREFIX_VEX_5E,
811 PREFIX_VEX_5F,
812 PREFIX_VEX_60,
813 PREFIX_VEX_61,
814 PREFIX_VEX_62,
815 PREFIX_VEX_63,
816 PREFIX_VEX_64,
817 PREFIX_VEX_65,
818 PREFIX_VEX_66,
819 PREFIX_VEX_67,
820 PREFIX_VEX_68,
821 PREFIX_VEX_69,
822 PREFIX_VEX_6A,
823 PREFIX_VEX_6B,
824 PREFIX_VEX_6C,
825 PREFIX_VEX_6D,
826 PREFIX_VEX_6E,
827 PREFIX_VEX_6F,
828 PREFIX_VEX_70,
829 PREFIX_VEX_71_REG_2,
830 PREFIX_VEX_71_REG_4,
831 PREFIX_VEX_71_REG_6,
832 PREFIX_VEX_72_REG_2,
833 PREFIX_VEX_72_REG_4,
834 PREFIX_VEX_72_REG_6,
835 PREFIX_VEX_73_REG_2,
836 PREFIX_VEX_73_REG_3,
837 PREFIX_VEX_73_REG_6,
838 PREFIX_VEX_73_REG_7,
839 PREFIX_VEX_74,
840 PREFIX_VEX_75,
841 PREFIX_VEX_76,
842 PREFIX_VEX_77,
843 PREFIX_VEX_7C,
844 PREFIX_VEX_7D,
845 PREFIX_VEX_7E,
846 PREFIX_VEX_7F,
847 PREFIX_VEX_C2,
848 PREFIX_VEX_C4,
849 PREFIX_VEX_C5,
850 PREFIX_VEX_D0,
851 PREFIX_VEX_D1,
852 PREFIX_VEX_D2,
853 PREFIX_VEX_D3,
854 PREFIX_VEX_D4,
855 PREFIX_VEX_D5,
856 PREFIX_VEX_D6,
857 PREFIX_VEX_D7,
858 PREFIX_VEX_D8,
859 PREFIX_VEX_D9,
860 PREFIX_VEX_DA,
861 PREFIX_VEX_DB,
862 PREFIX_VEX_DC,
863 PREFIX_VEX_DD,
864 PREFIX_VEX_DE,
865 PREFIX_VEX_DF,
866 PREFIX_VEX_E0,
867 PREFIX_VEX_E1,
868 PREFIX_VEX_E2,
869 PREFIX_VEX_E3,
870 PREFIX_VEX_E4,
871 PREFIX_VEX_E5,
872 PREFIX_VEX_E6,
873 PREFIX_VEX_E7,
874 PREFIX_VEX_E8,
875 PREFIX_VEX_E9,
876 PREFIX_VEX_EA,
877 PREFIX_VEX_EB,
878 PREFIX_VEX_EC,
879 PREFIX_VEX_ED,
880 PREFIX_VEX_EE,
881 PREFIX_VEX_EF,
882 PREFIX_VEX_F0,
883 PREFIX_VEX_F1,
884 PREFIX_VEX_F2,
885 PREFIX_VEX_F3,
886 PREFIX_VEX_F4,
887 PREFIX_VEX_F5,
888 PREFIX_VEX_F6,
889 PREFIX_VEX_F7,
890 PREFIX_VEX_F8,
891 PREFIX_VEX_F9,
892 PREFIX_VEX_FA,
893 PREFIX_VEX_FB,
894 PREFIX_VEX_FC,
895 PREFIX_VEX_FD,
896 PREFIX_VEX_FE,
897 PREFIX_VEX_3800,
898 PREFIX_VEX_3801,
899 PREFIX_VEX_3802,
900 PREFIX_VEX_3803,
901 PREFIX_VEX_3804,
902 PREFIX_VEX_3805,
903 PREFIX_VEX_3806,
904 PREFIX_VEX_3807,
905 PREFIX_VEX_3808,
906 PREFIX_VEX_3809,
907 PREFIX_VEX_380A,
908 PREFIX_VEX_380B,
909 PREFIX_VEX_380C,
910 PREFIX_VEX_380D,
911 PREFIX_VEX_380E,
912 PREFIX_VEX_380F,
913 PREFIX_VEX_3817,
914 PREFIX_VEX_3818,
915 PREFIX_VEX_3819,
916 PREFIX_VEX_381A,
917 PREFIX_VEX_381C,
918 PREFIX_VEX_381D,
919 PREFIX_VEX_381E,
920 PREFIX_VEX_3820,
921 PREFIX_VEX_3821,
922 PREFIX_VEX_3822,
923 PREFIX_VEX_3823,
924 PREFIX_VEX_3824,
925 PREFIX_VEX_3825,
926 PREFIX_VEX_3828,
927 PREFIX_VEX_3829,
928 PREFIX_VEX_382A,
929 PREFIX_VEX_382B,
930 PREFIX_VEX_382C,
931 PREFIX_VEX_382D,
932 PREFIX_VEX_382E,
933 PREFIX_VEX_382F,
934 PREFIX_VEX_3830,
935 PREFIX_VEX_3831,
936 PREFIX_VEX_3832,
937 PREFIX_VEX_3833,
938 PREFIX_VEX_3834,
939 PREFIX_VEX_3835,
940 PREFIX_VEX_3837,
941 PREFIX_VEX_3838,
942 PREFIX_VEX_3839,
943 PREFIX_VEX_383A,
944 PREFIX_VEX_383B,
945 PREFIX_VEX_383C,
946 PREFIX_VEX_383D,
947 PREFIX_VEX_383E,
948 PREFIX_VEX_383F,
949 PREFIX_VEX_3840,
950 PREFIX_VEX_3841,
951 PREFIX_VEX_3896,
952 PREFIX_VEX_3897,
953 PREFIX_VEX_3898,
954 PREFIX_VEX_3899,
955 PREFIX_VEX_389A,
956 PREFIX_VEX_389B,
957 PREFIX_VEX_389C,
958 PREFIX_VEX_389D,
959 PREFIX_VEX_389E,
960 PREFIX_VEX_389F,
961 PREFIX_VEX_38A6,
962 PREFIX_VEX_38A7,
963 PREFIX_VEX_38A8,
964 PREFIX_VEX_38A9,
965 PREFIX_VEX_38AA,
966 PREFIX_VEX_38AB,
967 PREFIX_VEX_38AC,
968 PREFIX_VEX_38AD,
969 PREFIX_VEX_38AE,
970 PREFIX_VEX_38AF,
971 PREFIX_VEX_38B6,
972 PREFIX_VEX_38B7,
973 PREFIX_VEX_38B8,
974 PREFIX_VEX_38B9,
975 PREFIX_VEX_38BA,
976 PREFIX_VEX_38BB,
977 PREFIX_VEX_38BC,
978 PREFIX_VEX_38BD,
979 PREFIX_VEX_38BE,
980 PREFIX_VEX_38BF,
981 PREFIX_VEX_38DB,
982 PREFIX_VEX_38DC,
983 PREFIX_VEX_38DD,
984 PREFIX_VEX_38DE,
985 PREFIX_VEX_38DF,
986 PREFIX_VEX_3A04,
987 PREFIX_VEX_3A05,
988 PREFIX_VEX_3A06,
989 PREFIX_VEX_3A08,
990 PREFIX_VEX_3A09,
991 PREFIX_VEX_3A0A,
992 PREFIX_VEX_3A0B,
993 PREFIX_VEX_3A0C,
994 PREFIX_VEX_3A0D,
995 PREFIX_VEX_3A0E,
996 PREFIX_VEX_3A0F,
997 PREFIX_VEX_3A14,
998 PREFIX_VEX_3A15,
999 PREFIX_VEX_3A16,
1000 PREFIX_VEX_3A17,
1001 PREFIX_VEX_3A18,
1002 PREFIX_VEX_3A19,
1003 PREFIX_VEX_3A20,
1004 PREFIX_VEX_3A21,
1005 PREFIX_VEX_3A22,
1006 PREFIX_VEX_3A40,
1007 PREFIX_VEX_3A41,
1008 PREFIX_VEX_3A42,
1009 PREFIX_VEX_3A44,
1010 PREFIX_VEX_3A4A,
1011 PREFIX_VEX_3A4B,
1012 PREFIX_VEX_3A4C,
1013 PREFIX_VEX_3A5C,
1014 PREFIX_VEX_3A5D,
1015 PREFIX_VEX_3A5E,
1016 PREFIX_VEX_3A5F,
1017 PREFIX_VEX_3A60,
1018 PREFIX_VEX_3A61,
1019 PREFIX_VEX_3A62,
1020 PREFIX_VEX_3A63,
1021 PREFIX_VEX_3A68,
1022 PREFIX_VEX_3A69,
1023 PREFIX_VEX_3A6A,
1024 PREFIX_VEX_3A6B,
1025 PREFIX_VEX_3A6C,
1026 PREFIX_VEX_3A6D,
1027 PREFIX_VEX_3A6E,
1028 PREFIX_VEX_3A6F,
1029 PREFIX_VEX_3A78,
1030 PREFIX_VEX_3A79,
1031 PREFIX_VEX_3A7A,
1032 PREFIX_VEX_3A7B,
1033 PREFIX_VEX_3A7C,
1034 PREFIX_VEX_3A7D,
1035 PREFIX_VEX_3A7E,
1036 PREFIX_VEX_3A7F,
1037 PREFIX_VEX_3ADF
51e7da1b 1038};
4e7d34a6 1039
51e7da1b
L		 1040enum
1041{
1042 X86_64_06 = 0,
3873ba12
L		 1043 X86_64_07,
1044 X86_64_0D,
1045 X86_64_16,
1046 X86_64_17,
1047 X86_64_1E,
1048 X86_64_1F,
1049 X86_64_27,
1050 X86_64_2F,
1051 X86_64_37,
1052 X86_64_3F,
1053 X86_64_60,
1054 X86_64_61,
1055 X86_64_62,
1056 X86_64_63,
1057 X86_64_6D,
1058 X86_64_6F,
1059 X86_64_9A,
1060 X86_64_C4,
1061 X86_64_C5,
1062 X86_64_CE,
1063 X86_64_D4,
1064 X86_64_D5,
1065 X86_64_EA,
1066 X86_64_0F01_REG_0,
1067 X86_64_0F01_REG_1,
1068 X86_64_0F01_REG_2,
1069 X86_64_0F01_REG_3
51e7da1b 1070};
4e7d34a6 1071
51e7da1b
L		 1072enum
1073{
1074 THREE_BYTE_0F38 = 0,
3873ba12
L		 1075 THREE_BYTE_0F3A,
1076 THREE_BYTE_0F7A
51e7da1b 1077};
4e7d34a6 1078
f88c9eb0
SP		 1079enum
1080{
5dd85c99
SP		 1081 XOP_08 = 0,
1082 XOP_09,
f88c9eb0
SP		 1083 XOP_0A
1084};
1085
51e7da1b
L		 1086enum
1087{
1088 VEX_0F = 0,
3873ba12
L		 1089 VEX_0F38,
1090 VEX_0F3A
51e7da1b 1091};
c0f3af97 1092
51e7da1b
L		 1093enum
1094{
1095 VEX_LEN_10_P_1 = 0,
3873ba12
L		 1096 VEX_LEN_10_P_3,
1097 VEX_LEN_11_P_1,
1098 VEX_LEN_11_P_3,
1099 VEX_LEN_12_P_0_M_0,
1100 VEX_LEN_12_P_0_M_1,
1101 VEX_LEN_12_P_2,
1102 VEX_LEN_13_M_0,
1103 VEX_LEN_16_P_0_M_0,
1104 VEX_LEN_16_P_0_M_1,
1105 VEX_LEN_16_P_2,
1106 VEX_LEN_17_M_0,
1107 VEX_LEN_2A_P_1,
1108 VEX_LEN_2A_P_3,
1109 VEX_LEN_2C_P_1,
1110 VEX_LEN_2C_P_3,
1111 VEX_LEN_2D_P_1,
1112 VEX_LEN_2D_P_3,
1113 VEX_LEN_2E_P_0,
1114 VEX_LEN_2E_P_2,
1115 VEX_LEN_2F_P_0,
1116 VEX_LEN_2F_P_2,
1117 VEX_LEN_51_P_1,
1118 VEX_LEN_51_P_3,
1119 VEX_LEN_52_P_1,
1120 VEX_LEN_53_P_1,
1121 VEX_LEN_58_P_1,
1122 VEX_LEN_58_P_3,
1123 VEX_LEN_59_P_1,
1124 VEX_LEN_59_P_3,
1125 VEX_LEN_5A_P_1,
1126 VEX_LEN_5A_P_3,
1127 VEX_LEN_5C_P_1,
1128 VEX_LEN_5C_P_3,
1129 VEX_LEN_5D_P_1,
1130 VEX_LEN_5D_P_3,
1131 VEX_LEN_5E_P_1,
1132 VEX_LEN_5E_P_3,
1133 VEX_LEN_5F_P_1,
1134 VEX_LEN_5F_P_3,
1135 VEX_LEN_60_P_2,
1136 VEX_LEN_61_P_2,
1137 VEX_LEN_62_P_2,
1138 VEX_LEN_63_P_2,
1139 VEX_LEN_64_P_2,
1140 VEX_LEN_65_P_2,
1141 VEX_LEN_66_P_2,
1142 VEX_LEN_67_P_2,
1143 VEX_LEN_68_P_2,
1144 VEX_LEN_69_P_2,
1145 VEX_LEN_6A_P_2,
1146 VEX_LEN_6B_P_2,
1147 VEX_LEN_6C_P_2,
1148 VEX_LEN_6D_P_2,
1149 VEX_LEN_6E_P_2,
1150 VEX_LEN_70_P_1,
1151 VEX_LEN_70_P_2,
1152 VEX_LEN_70_P_3,
1153 VEX_LEN_71_R_2_P_2,
1154 VEX_LEN_71_R_4_P_2,
1155 VEX_LEN_71_R_6_P_2,
1156 VEX_LEN_72_R_2_P_2,
1157 VEX_LEN_72_R_4_P_2,
1158 VEX_LEN_72_R_6_P_2,
1159 VEX_LEN_73_R_2_P_2,
1160 VEX_LEN_73_R_3_P_2,
1161 VEX_LEN_73_R_6_P_2,
1162 VEX_LEN_73_R_7_P_2,
1163 VEX_LEN_74_P_2,
1164 VEX_LEN_75_P_2,
1165 VEX_LEN_76_P_2,
1166 VEX_LEN_7E_P_1,
1167 VEX_LEN_7E_P_2,
1168 VEX_LEN_AE_R_2_M_0,
1169 VEX_LEN_AE_R_3_M_0,
1170 VEX_LEN_C2_P_1,
1171 VEX_LEN_C2_P_3,
1172 VEX_LEN_C4_P_2,
1173 VEX_LEN_C5_P_2,
1174 VEX_LEN_D1_P_2,
1175 VEX_LEN_D2_P_2,
1176 VEX_LEN_D3_P_2,
1177 VEX_LEN_D4_P_2,
1178 VEX_LEN_D5_P_2,
1179 VEX_LEN_D6_P_2,
1180 VEX_LEN_D7_P_2_M_1,
1181 VEX_LEN_D8_P_2,
1182 VEX_LEN_D9_P_2,
1183 VEX_LEN_DA_P_2,
1184 VEX_LEN_DB_P_2,
1185 VEX_LEN_DC_P_2,
1186 VEX_LEN_DD_P_2,
1187 VEX_LEN_DE_P_2,
1188 VEX_LEN_DF_P_2,
1189 VEX_LEN_E0_P_2,
1190 VEX_LEN_E1_P_2,
1191 VEX_LEN_E2_P_2,
1192 VEX_LEN_E3_P_2,
1193 VEX_LEN_E4_P_2,
1194 VEX_LEN_E5_P_2,
1195 VEX_LEN_E8_P_2,
1196 VEX_LEN_E9_P_2,
1197 VEX_LEN_EA_P_2,
1198 VEX_LEN_EB_P_2,
1199 VEX_LEN_EC_P_2,
1200 VEX_LEN_ED_P_2,
1201 VEX_LEN_EE_P_2,
1202 VEX_LEN_EF_P_2,
1203 VEX_LEN_F1_P_2,
1204 VEX_LEN_F2_P_2,
1205 VEX_LEN_F3_P_2,
1206 VEX_LEN_F4_P_2,
1207 VEX_LEN_F5_P_2,
1208 VEX_LEN_F6_P_2,
1209 VEX_LEN_F7_P_2,
1210 VEX_LEN_F8_P_2,
1211 VEX_LEN_F9_P_2,
1212 VEX_LEN_FA_P_2,
1213 VEX_LEN_FB_P_2,
1214 VEX_LEN_FC_P_2,
1215 VEX_LEN_FD_P_2,
1216 VEX_LEN_FE_P_2,
1217 VEX_LEN_3800_P_2,
1218 VEX_LEN_3801_P_2,
1219 VEX_LEN_3802_P_2,
1220 VEX_LEN_3803_P_2,
1221 VEX_LEN_3804_P_2,
1222 VEX_LEN_3805_P_2,
1223 VEX_LEN_3806_P_2,
1224 VEX_LEN_3807_P_2,
1225 VEX_LEN_3808_P_2,
1226 VEX_LEN_3809_P_2,
1227 VEX_LEN_380A_P_2,
1228 VEX_LEN_380B_P_2,
1229 VEX_LEN_3819_P_2_M_0,
1230 VEX_LEN_381A_P_2_M_0,
1231 VEX_LEN_381C_P_2,
1232 VEX_LEN_381D_P_2,
1233 VEX_LEN_381E_P_2,
1234 VEX_LEN_3820_P_2,
1235 VEX_LEN_3821_P_2,
1236 VEX_LEN_3822_P_2,
1237 VEX_LEN_3823_P_2,
1238 VEX_LEN_3824_P_2,
1239 VEX_LEN_3825_P_2,
1240 VEX_LEN_3828_P_2,
1241 VEX_LEN_3829_P_2,
1242 VEX_LEN_382A_P_2_M_0,
1243 VEX_LEN_382B_P_2,
1244 VEX_LEN_3830_P_2,
1245 VEX_LEN_3831_P_2,
1246 VEX_LEN_3832_P_2,
1247 VEX_LEN_3833_P_2,
1248 VEX_LEN_3834_P_2,
1249 VEX_LEN_3835_P_2,
1250 VEX_LEN_3837_P_2,
1251 VEX_LEN_3838_P_2,
1252 VEX_LEN_3839_P_2,
1253 VEX_LEN_383A_P_2,
1254 VEX_LEN_383B_P_2,
1255 VEX_LEN_383C_P_2,
1256 VEX_LEN_383D_P_2,
1257 VEX_LEN_383E_P_2,
1258 VEX_LEN_383F_P_2,
1259 VEX_LEN_3840_P_2,
1260 VEX_LEN_3841_P_2,
1261 VEX_LEN_38DB_P_2,
1262 VEX_LEN_38DC_P_2,
1263 VEX_LEN_38DD_P_2,
1264 VEX_LEN_38DE_P_2,
1265 VEX_LEN_38DF_P_2,
1266 VEX_LEN_3A06_P_2,
1267 VEX_LEN_3A0A_P_2,
1268 VEX_LEN_3A0B_P_2,
1269 VEX_LEN_3A0E_P_2,
1270 VEX_LEN_3A0F_P_2,
1271 VEX_LEN_3A14_P_2,
1272 VEX_LEN_3A15_P_2,
1273 VEX_LEN_3A16_P_2,
1274 VEX_LEN_3A17_P_2,
1275 VEX_LEN_3A18_P_2,
1276 VEX_LEN_3A19_P_2,
1277 VEX_LEN_3A20_P_2,
1278 VEX_LEN_3A21_P_2,
1279 VEX_LEN_3A22_P_2,
1280 VEX_LEN_3A41_P_2,
1281 VEX_LEN_3A42_P_2,
1282 VEX_LEN_3A44_P_2,
1283 VEX_LEN_3A4C_P_2,
1284 VEX_LEN_3A60_P_2,
1285 VEX_LEN_3A61_P_2,
1286 VEX_LEN_3A62_P_2,
1287 VEX_LEN_3A63_P_2,
1288 VEX_LEN_3A6A_P_2,
1289 VEX_LEN_3A6B_P_2,
1290 VEX_LEN_3A6E_P_2,
1291 VEX_LEN_3A6F_P_2,
1292 VEX_LEN_3A7A_P_2,
1293 VEX_LEN_3A7B_P_2,
1294 VEX_LEN_3A7E_P_2,
1295 VEX_LEN_3A7F_P_2,
5dd85c99 1296 VEX_LEN_3ADF_P_2,
5dd85c99
SP		 1297 VEX_LEN_XOP_09_80,
1298 VEX_LEN_XOP_09_81
51e7da1b 1299};
c0f3af97 1300
9e30b8e0
L		 1301enum
1302{
1303 VEX_W_10_P_0 = 0,
1304 VEX_W_10_P_1,
1305 VEX_W_10_P_2,
1306 VEX_W_10_P_3,
1307 VEX_W_11_P_0,
1308 VEX_W_11_P_1,
1309 VEX_W_11_P_2,
1310 VEX_W_11_P_3,
1311 VEX_W_12_P_0_M_0,
1312 VEX_W_12_P_0_M_1,
1313 VEX_W_12_P_1,
1314 VEX_W_12_P_2,
1315 VEX_W_12_P_3,
1316 VEX_W_13_M_0,
1317 VEX_W_14,
1318 VEX_W_15,
1319 VEX_W_16_P_0_M_0,
1320 VEX_W_16_P_0_M_1,
1321 VEX_W_16_P_1,
1322 VEX_W_16_P_2,
1323 VEX_W_17_M_0,
1324 VEX_W_28,
1325 VEX_W_29,
1326 VEX_W_2B_M_0,
1327 VEX_W_2E_P_0,
1328 VEX_W_2E_P_2,
1329 VEX_W_2F_P_0,
1330 VEX_W_2F_P_2,
1331 VEX_W_50_M_0,
1332 VEX_W_51_P_0,
1333 VEX_W_51_P_1,
1334 VEX_W_51_P_2,
1335 VEX_W_51_P_3,
1336 VEX_W_52_P_0,
1337 VEX_W_52_P_1,
1338 VEX_W_53_P_0,
1339 VEX_W_53_P_1,
1340 VEX_W_58_P_0,
1341 VEX_W_58_P_1,
1342 VEX_W_58_P_2,
1343 VEX_W_58_P_3,
1344 VEX_W_59_P_0,
1345 VEX_W_59_P_1,
1346 VEX_W_59_P_2,
1347 VEX_W_59_P_3,
1348 VEX_W_5A_P_0,
1349 VEX_W_5A_P_1,
1350 VEX_W_5A_P_3,
1351 VEX_W_5B_P_0,
1352 VEX_W_5B_P_1,
1353 VEX_W_5B_P_2,
1354 VEX_W_5C_P_0,
1355 VEX_W_5C_P_1,
1356 VEX_W_5C_P_2,
1357 VEX_W_5C_P_3,
1358 VEX_W_5D_P_0,
1359 VEX_W_5D_P_1,
1360 VEX_W_5D_P_2,
1361 VEX_W_5D_P_3,
1362 VEX_W_5E_P_0,
1363 VEX_W_5E_P_1,
1364 VEX_W_5E_P_2,
1365 VEX_W_5E_P_3,
1366 VEX_W_5F_P_0,
1367 VEX_W_5F_P_1,
1368 VEX_W_5F_P_2,
1369 VEX_W_5F_P_3,
1370 VEX_W_60_P_2,
1371 VEX_W_61_P_2,
1372 VEX_W_62_P_2,
1373 VEX_W_63_P_2,
1374 VEX_W_64_P_2,
1375 VEX_W_65_P_2,
1376 VEX_W_66_P_2,
1377 VEX_W_67_P_2,
1378 VEX_W_68_P_2,
1379 VEX_W_69_P_2,
1380 VEX_W_6A_P_2,
1381 VEX_W_6B_P_2,
1382 VEX_W_6C_P_2,
1383 VEX_W_6D_P_2,
1384 VEX_W_6F_P_1,
1385 VEX_W_6F_P_2,
1386 VEX_W_70_P_1,
1387 VEX_W_70_P_2,
1388 VEX_W_70_P_3,
1389 VEX_W_71_R_2_P_2,
1390 VEX_W_71_R_4_P_2,
1391 VEX_W_71_R_6_P_2,
1392 VEX_W_72_R_2_P_2,
1393 VEX_W_72_R_4_P_2,
1394 VEX_W_72_R_6_P_2,
1395 VEX_W_73_R_2_P_2,
1396 VEX_W_73_R_3_P_2,
1397 VEX_W_73_R_6_P_2,
1398 VEX_W_73_R_7_P_2,
1399 VEX_W_74_P_2,
1400 VEX_W_75_P_2,
1401 VEX_W_76_P_2,
1402 VEX_W_77_P_0,
1403 VEX_W_7C_P_2,
1404 VEX_W_7C_P_3,
1405 VEX_W_7D_P_2,
1406 VEX_W_7D_P_3,
1407 VEX_W_7E_P_1,
1408 VEX_W_7F_P_1,
1409 VEX_W_7F_P_2,
1410 VEX_W_AE_R_2_M_0,
1411 VEX_W_AE_R_3_M_0,
1412 VEX_W_C2_P_0,
1413 VEX_W_C2_P_1,
1414 VEX_W_C2_P_2,
1415 VEX_W_C2_P_3,
1416 VEX_W_C4_P_2,
1417 VEX_W_C5_P_2,
1418 VEX_W_D0_P_2,
1419 VEX_W_D0_P_3,
1420 VEX_W_D1_P_2,
1421 VEX_W_D2_P_2,
1422 VEX_W_D3_P_2,
1423 VEX_W_D4_P_2,
1424 VEX_W_D5_P_2,
1425 VEX_W_D6_P_2,
1426 VEX_W_D7_P_2_M_1,
1427 VEX_W_D8_P_2,
1428 VEX_W_D9_P_2,
1429 VEX_W_DA_P_2,
1430 VEX_W_DB_P_2,
1431 VEX_W_DC_P_2,
1432 VEX_W_DD_P_2,
1433 VEX_W_DE_P_2,
1434 VEX_W_DF_P_2,
1435 VEX_W_E0_P_2,
1436 VEX_W_E1_P_2,
1437 VEX_W_E2_P_2,
1438 VEX_W_E3_P_2,
1439 VEX_W_E4_P_2,
1440 VEX_W_E5_P_2,
1441 VEX_W_E6_P_1,
1442 VEX_W_E6_P_2,
1443 VEX_W_E6_P_3,
1444 VEX_W_E7_P_2_M_0,
1445 VEX_W_E8_P_2,
1446 VEX_W_E9_P_2,
1447 VEX_W_EA_P_2,
1448 VEX_W_EB_P_2,
1449 VEX_W_EC_P_2,
1450 VEX_W_ED_P_2,
1451 VEX_W_EE_P_2,
1452 VEX_W_EF_P_2,
1453 VEX_W_F0_P_3_M_0,
1454 VEX_W_F1_P_2,
1455 VEX_W_F2_P_2,
1456 VEX_W_F3_P_2,
1457 VEX_W_F4_P_2,
1458 VEX_W_F5_P_2,
1459 VEX_W_F6_P_2,
1460 VEX_W_F7_P_2,
1461 VEX_W_F8_P_2,
1462 VEX_W_F9_P_2,
1463 VEX_W_FA_P_2,
1464 VEX_W_FB_P_2,
1465 VEX_W_FC_P_2,
1466 VEX_W_FD_P_2,
1467 VEX_W_FE_P_2,
1468 VEX_W_3800_P_2,
1469 VEX_W_3801_P_2,
1470 VEX_W_3802_P_2,
1471 VEX_W_3803_P_2,
1472 VEX_W_3804_P_2,
1473 VEX_W_3805_P_2,
1474 VEX_W_3806_P_2,
1475 VEX_W_3807_P_2,
1476 VEX_W_3808_P_2,
1477 VEX_W_3809_P_2,
1478 VEX_W_380A_P_2,
1479 VEX_W_380B_P_2,
1480 VEX_W_380C_P_2,
1481 VEX_W_380D_P_2,
1482 VEX_W_380E_P_2,
1483 VEX_W_380F_P_2,
1484 VEX_W_3817_P_2,
bcf2684f 1485 VEX_W_3818_P_2_M_0,
9e30b8e0
L		 1486 VEX_W_3819_P_2_M_0,
1487 VEX_W_381A_P_2_M_0,
1488 VEX_W_381C_P_2,
1489 VEX_W_381D_P_2,
1490 VEX_W_381E_P_2,
1491 VEX_W_3820_P_2,
1492 VEX_W_3821_P_2,
1493 VEX_W_3822_P_2,
1494 VEX_W_3823_P_2,
1495 VEX_W_3824_P_2,
1496 VEX_W_3825_P_2,
1497 VEX_W_3828_P_2,
1498 VEX_W_3829_P_2,
1499 VEX_W_382A_P_2_M_0,
1500 VEX_W_382B_P_2,
53aa04a0
L		 1501 VEX_W_382C_P_2_M_0,
1502 VEX_W_382D_P_2_M_0,
1503 VEX_W_382E_P_2_M_0,
1504 VEX_W_382F_P_2_M_0,
9e30b8e0
L		 1505 VEX_W_3830_P_2,
1506 VEX_W_3831_P_2,
1507 VEX_W_3832_P_2,
1508 VEX_W_3833_P_2,
1509 VEX_W_3834_P_2,
1510 VEX_W_3835_P_2,
1511 VEX_W_3837_P_2,
1512 VEX_W_3838_P_2,
1513 VEX_W_3839_P_2,
1514 VEX_W_383A_P_2,
1515 VEX_W_383B_P_2,
1516 VEX_W_383C_P_2,
1517 VEX_W_383D_P_2,
1518 VEX_W_383E_P_2,
1519 VEX_W_383F_P_2,
1520 VEX_W_3840_P_2,
1521 VEX_W_3841_P_2,
1522 VEX_W_38DB_P_2,
1523 VEX_W_38DC_P_2,
1524 VEX_W_38DD_P_2,
1525 VEX_W_38DE_P_2,
1526 VEX_W_38DF_P_2,
1527 VEX_W_3A04_P_2,
1528 VEX_W_3A05_P_2,
1529 VEX_W_3A06_P_2,
1530 VEX_W_3A08_P_2,
1531 VEX_W_3A09_P_2,
1532 VEX_W_3A0A_P_2,
1533 VEX_W_3A0B_P_2,
1534 VEX_W_3A0C_P_2,
1535 VEX_W_3A0D_P_2,
1536 VEX_W_3A0E_P_2,
1537 VEX_W_3A0F_P_2,
1538 VEX_W_3A14_P_2,
1539 VEX_W_3A15_P_2,
1540 VEX_W_3A18_P_2,
1541 VEX_W_3A19_P_2,
1542 VEX_W_3A20_P_2,
1543 VEX_W_3A21_P_2,
1544 VEX_W_3A40_P_2,
1545 VEX_W_3A41_P_2,
1546 VEX_W_3A42_P_2,
1547 VEX_W_3A44_P_2,
1548 VEX_W_3A4A_P_2,
1549 VEX_W_3A4B_P_2,
1550 VEX_W_3A4C_P_2,
1551 VEX_W_3A60_P_2,
1552 VEX_W_3A61_P_2,
1553 VEX_W_3A62_P_2,
1554 VEX_W_3A63_P_2,
1555 VEX_W_3ADF_P_2
1556};
1557
26ca5450 1558typedef void (*op_rtn) (int bytemode, int sizeflag);
252b5132
RH		 1559
1560struct dis386 {
2da11e11 1561 const char *name;
ce518a5f
L		 1562 struct
1563 {
1564 op_rtn rtn;
1565 int bytemode;
1566 } op[MAX_OPERANDS];
252b5132
RH		 1567};
1568
1569/* Upper case letters in the instruction names here are macros.
1570 'A' => print 'b' if no register operands or suffix_always is true
1571 'B' => print 'b' if suffix_always is true
9306ca4a 1572 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
98b528ac 1573 size prefix
ed7841b3 1574 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
98b528ac 1575 suffix_always is true
252b5132 1576 'E' => print 'e' if 32-bit form of jcxz
3ffd33cf 1577 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
52fd6d94 1578 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
5dd0794d 1579 'H' => print ",pt" or ",pn" branch hint
9306ca4a 1580 'I' => honor following macro letter even in Intel mode (implemented only
98b528ac 1581 for some of the macro letters)
9306ca4a 1582 'J' => print 'l'
42903f7f 1583 'K' => print 'd' or 'q' if rex prefix is present.
252b5132 1584 'L' => print 'l' if suffix_always is true
9d141669 1585 'M' => print 'r' if intel_mnemonic is false.
252b5132 1586 'N' => print 'n' if instruction has no wait "prefix"
a35ca55a 1587 'O' => print 'd' or 'o' (or 'q' in Intel mode)
52b15da3 1588 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
98b528ac
L		 1589 or suffix_always is true. print 'q' if rex prefix is present.
1590 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1591 is true
a35ca55a 1592 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
52b15da3 1593 'S' => print 'w', 'l' or 'q' if suffix_always is true
6439fc28
AM		 1594 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1595 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1a114b12 1596 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
a35ca55a 1597 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
9306ca4a 1598 'X' => print 's', 'd' depending on data16 prefix (for XMM)
8a72226a
L		 1599 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1600 suffix_always is true.
6dd5059a 1601 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
9d141669 1602 '!' => change condition from true to false or from false to true.
98b528ac
L		 1603 '%' => add 1 upper case letter to the macro.
1604
1605 2 upper case letter macros:
c0f3af97
L		 1606 "XY" => print 'x' or 'y' if no register operands or suffix_always
1607 is true.
4b06377f
L		 1608 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1609 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
98b528ac 1610 or suffix_always is true
4b06377f
L		 1611 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1612 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1613 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
52b15da3 1614
6439fc28
AM		 1615 Many of the above letters print nothing in Intel mode. See "putop"
1616 for the details.
52b15da3 1617
6439fc28 1618 Braces '{' and '}', and vertical bars '|', indicate alternative
7c52e0e8 1619 mnemonic strings for AT&T and Intel. */
252b5132 1620
6439fc28 1621static const struct dis386 dis386[] = {
252b5132 1622 /* 00 */
ce518a5f
L		 1623 { "addB", { Eb, Gb } },
1624 { "addS", { Ev, Gv } },
c7532693
L		 1625 { "addB", { Gb, EbS } },
1626 { "addS", { Gv, EvS } },
ce518a5f
L		 1627 { "addB", { AL, Ib } },
1628 { "addS", { eAX, Iv } },
4e7d34a6
L		 1629 { X86_64_TABLE (X86_64_06) },
1630 { X86_64_TABLE (X86_64_07) },
252b5132 1631 /* 08 */
ce518a5f
L		 1632 { "orB", { Eb, Gb } },
1633 { "orS", { Ev, Gv } },
c7532693
L		 1634 { "orB", { Gb, EbS } },
1635 { "orS", { Gv, EvS } },
ce518a5f
L		 1636 { "orB", { AL, Ib } },
1637 { "orS", { eAX, Iv } },
4e7d34a6 1638 { X86_64_TABLE (X86_64_0D) },
ce518a5f 1639 { "(bad)", { XX } }, /* 0x0f extended opcode escape */
252b5132 1640 /* 10 */
ce518a5f
L		 1641 { "adcB", { Eb, Gb } },
1642 { "adcS", { Ev, Gv } },
c7532693
L		 1643 { "adcB", { Gb, EbS } },
1644 { "adcS", { Gv, EvS } },
ce518a5f
L		 1645 { "adcB", { AL, Ib } },
1646 { "adcS", { eAX, Iv } },
4e7d34a6
L		 1647 { X86_64_TABLE (X86_64_16) },
1648 { X86_64_TABLE (X86_64_17) },
252b5132 1649 /* 18 */
ce518a5f
L		 1650 { "sbbB", { Eb, Gb } },
1651 { "sbbS", { Ev, Gv } },
c7532693
L		 1652 { "sbbB", { Gb, EbS } },
1653 { "sbbS", { Gv, EvS } },
ce518a5f
L		 1654 { "sbbB", { AL, Ib } },
1655 { "sbbS", { eAX, Iv } },
4e7d34a6
L		 1656 { X86_64_TABLE (X86_64_1E) },
1657 { X86_64_TABLE (X86_64_1F) },
252b5132 1658 /* 20 */
ce518a5f
L		 1659 { "andB", { Eb, Gb } },
1660 { "andS", { Ev, Gv } },
c7532693
L		 1661 { "andB", { Gb, EbS } },
1662 { "andS", { Gv, EvS } },
ce518a5f
L		 1663 { "andB", { AL, Ib } },
1664 { "andS", { eAX, Iv } },
1665 { "(bad)", { XX } }, /* SEG ES prefix */
4e7d34a6 1666 { X86_64_TABLE (X86_64_27) },
252b5132 1667 /* 28 */
ce518a5f
L		 1668 { "subB", { Eb, Gb } },
1669 { "subS", { Ev, Gv } },
c7532693
L		 1670 { "subB", { Gb, EbS } },
1671 { "subS", { Gv, EvS } },
ce518a5f
L		 1672 { "subB", { AL, Ib } },
1673 { "subS", { eAX, Iv } },
1674 { "(bad)", { XX } }, /* SEG CS prefix */
4e7d34a6 1675 { X86_64_TABLE (X86_64_2F) },
252b5132 1676 /* 30 */
ce518a5f
L		 1677 { "xorB", { Eb, Gb } },
1678 { "xorS", { Ev, Gv } },
c7532693
L		 1679 { "xorB", { Gb, EbS } },
1680 { "xorS", { Gv, EvS } },
ce518a5f
L		 1681 { "xorB", { AL, Ib } },
1682 { "xorS", { eAX, Iv } },
1683 { "(bad)", { XX } }, /* SEG SS prefix */
4e7d34a6 1684 { X86_64_TABLE (X86_64_37) },
252b5132 1685 /* 38 */
ce518a5f
L		 1686 { "cmpB", { Eb, Gb } },
1687 { "cmpS", { Ev, Gv } },
c7532693
L		 1688 { "cmpB", { Gb, EbS } },
1689 { "cmpS", { Gv, EvS } },
ce518a5f
L		 1690 { "cmpB", { AL, Ib } },
1691 { "cmpS", { eAX, Iv } },
1692 { "(bad)", { XX } }, /* SEG DS prefix */
4e7d34a6 1693 { X86_64_TABLE (X86_64_3F) },
252b5132 1694 /* 40 */
ce518a5f
L		 1695 { "inc{S|}", { RMeAX } },
1696 { "inc{S|}", { RMeCX } },
1697 { "inc{S|}", { RMeDX } },
1698 { "inc{S|}", { RMeBX } },
1699 { "inc{S|}", { RMeSP } },
1700 { "inc{S|}", { RMeBP } },
1701 { "inc{S|}", { RMeSI } },
1702 { "inc{S|}", { RMeDI } },
252b5132 1703 /* 48 */
ce518a5f
L		 1704 { "dec{S|}", { RMeAX } },
1705 { "dec{S|}", { RMeCX } },
1706 { "dec{S|}", { RMeDX } },
1707 { "dec{S|}", { RMeBX } },
1708 { "dec{S|}", { RMeSP } },
1709 { "dec{S|}", { RMeBP } },
1710 { "dec{S|}", { RMeSI } },
1711 { "dec{S|}", { RMeDI } },
252b5132 1712 /* 50 */
ce518a5f
L		 1713 { "pushV", { RMrAX } },
1714 { "pushV", { RMrCX } },
1715 { "pushV", { RMrDX } },
1716 { "pushV", { RMrBX } },
1717 { "pushV", { RMrSP } },
1718 { "pushV", { RMrBP } },
1719 { "pushV", { RMrSI } },
1720 { "pushV", { RMrDI } },
252b5132 1721 /* 58 */
ce518a5f
L		 1722 { "popV", { RMrAX } },
1723 { "popV", { RMrCX } },
1724 { "popV", { RMrDX } },
1725 { "popV", { RMrBX } },
1726 { "popV", { RMrSP } },
1727 { "popV", { RMrBP } },
1728 { "popV", { RMrSI } },
1729 { "popV", { RMrDI } },
252b5132 1730 /* 60 */
4e7d34a6
L		 1731 { X86_64_TABLE (X86_64_60) },
1732 { X86_64_TABLE (X86_64_61) },
1733 { X86_64_TABLE (X86_64_62) },
1734 { X86_64_TABLE (X86_64_63) },
ce518a5f
L		 1735 { "(bad)", { XX } }, /* seg fs */
1736 { "(bad)", { XX } }, /* seg gs */
1737 { "(bad)", { XX } }, /* op size prefix */
1738 { "(bad)", { XX } }, /* adr size prefix */
252b5132 1739 /* 68 */
ce518a5f
L		 1740 { "pushT", { Iq } },
1741 { "imulS", { Gv, Ev, Iv } },
1742 { "pushT", { sIb } },
1743 { "imulS", { Gv, Ev, sIb } },
7c52e0e8 1744 { "ins{b|}", { Ybr, indirDX } },
4e7d34a6 1745 { X86_64_TABLE (X86_64_6D) },
7c52e0e8 1746 { "outs{b|}", { indirDXr, Xb } },
4e7d34a6 1747 { X86_64_TABLE (X86_64_6F) },
252b5132 1748 /* 70 */
ce518a5f
L		 1749 { "joH", { Jb, XX, cond_jump_flag } },
1750 { "jnoH", { Jb, XX, cond_jump_flag } },
1751 { "jbH", { Jb, XX, cond_jump_flag } },
1752 { "jaeH", { Jb, XX, cond_jump_flag } },
1753 { "jeH", { Jb, XX, cond_jump_flag } },
1754 { "jneH", { Jb, XX, cond_jump_flag } },
1755 { "jbeH", { Jb, XX, cond_jump_flag } },
1756 { "jaH", { Jb, XX, cond_jump_flag } },
252b5132 1757 /* 78 */
ce518a5f
L		 1758 { "jsH", { Jb, XX, cond_jump_flag } },
1759 { "jnsH", { Jb, XX, cond_jump_flag } },
1760 { "jpH", { Jb, XX, cond_jump_flag } },
1761 { "jnpH", { Jb, XX, cond_jump_flag } },
1762 { "jlH", { Jb, XX, cond_jump_flag } },
1763 { "jgeH", { Jb, XX, cond_jump_flag } },
1764 { "jleH", { Jb, XX, cond_jump_flag } },
1765 { "jgH", { Jb, XX, cond_jump_flag } },
252b5132 1766 /* 80 */
1ceb70f8
L		 1767 { REG_TABLE (REG_80) },
1768 { REG_TABLE (REG_81) },
ce518a5f 1769 { "(bad)", { XX } },
1ceb70f8 1770 { REG_TABLE (REG_82) },
ce518a5f
L		 1771 { "testB", { Eb, Gb } },
1772 { "testS", { Ev, Gv } },
1773 { "xchgB", { Eb, Gb } },
1774 { "xchgS", { Ev, Gv } },
252b5132 1775 /* 88 */
ce518a5f
L		 1776 { "movB", { Eb, Gb } },
1777 { "movS", { Ev, Gv } },
b6169b20
L		 1778 { "movB", { Gb, EbS } },
1779 { "movS", { Gv, EvS } },
ce518a5f 1780 { "movD", { Sv, Sw } },
1ceb70f8 1781 { MOD_TABLE (MOD_8D) },
ce518a5f 1782 { "movD", { Sw, Sv } },
1ceb70f8 1783 { REG_TABLE (REG_8F) },
252b5132 1784 /* 90 */
1ceb70f8 1785 { PREFIX_TABLE (PREFIX_90) },
ce518a5f
L		 1786 { "xchgS", { RMeCX, eAX } },
1787 { "xchgS", { RMeDX, eAX } },
1788 { "xchgS", { RMeBX, eAX } },
1789 { "xchgS", { RMeSP, eAX } },
1790 { "xchgS", { RMeBP, eAX } },
1791 { "xchgS", { RMeSI, eAX } },
1792 { "xchgS", { RMeDI, eAX } },
252b5132 1793 /* 98 */
7c52e0e8
L		 1794 { "cW{t|}R", { XX } },
1795 { "cR{t|}O", { XX } },
4e7d34a6 1796 { X86_64_TABLE (X86_64_9A) },
ce518a5f
L		 1797 { "(bad)", { XX } }, /* fwait */
1798 { "pushfT", { XX } },
1799 { "popfT", { XX } },
7c52e0e8
L		 1800 { "sahf", { XX } },
1801 { "lahf", { XX } },
252b5132 1802 /* a0 */
4b06377f
L		 1803 { "mov%LB", { AL, Ob } },
1804 { "mov%LS", { eAX, Ov } },
1805 { "mov%LB", { Ob, AL } },
1806 { "mov%LS", { Ov, eAX } },
7c52e0e8
L		 1807 { "movs{b|}", { Ybr, Xb } },
1808 { "movs{R|}", { Yvr, Xv } },
1809 { "cmps{b|}", { Xb, Yb } },
1810 { "cmps{R|}", { Xv, Yv } },
252b5132 1811 /* a8 */
ce518a5f
L		 1812 { "testB", { AL, Ib } },
1813 { "testS", { eAX, Iv } },
1814 { "stosB", { Ybr, AL } },
1815 { "stosS", { Yvr, eAX } },
1816 { "lodsB", { ALr, Xb } },
1817 { "lodsS", { eAXr, Xv } },
1818 { "scasB", { AL, Yb } },
1819 { "scasS", { eAX, Yv } },
252b5132 1820 /* b0 */
ce518a5f
L		 1821 { "movB", { RMAL, Ib } },
1822 { "movB", { RMCL, Ib } },
1823 { "movB", { RMDL, Ib } },
1824 { "movB", { RMBL, Ib } },
1825 { "movB", { RMAH, Ib } },
1826 { "movB", { RMCH, Ib } },
1827 { "movB", { RMDH, Ib } },
1828 { "movB", { RMBH, Ib } },
252b5132 1829 /* b8 */
4b06377f
L		 1830 { "mov%LV", { RMeAX, Iv64 } },
1831 { "mov%LV", { RMeCX, Iv64 } },
1832 { "mov%LV", { RMeDX, Iv64 } },
1833 { "mov%LV", { RMeBX, Iv64 } },
1834 { "mov%LV", { RMeSP, Iv64 } },
1835 { "mov%LV", { RMeBP, Iv64 } },
1836 { "mov%LV", { RMeSI, Iv64 } },
1837 { "mov%LV", { RMeDI, Iv64 } },
252b5132 1838 /* c0 */
1ceb70f8
L		 1839 { REG_TABLE (REG_C0) },
1840 { REG_TABLE (REG_C1) },
ce518a5f
L		 1841 { "retT", { Iw } },
1842 { "retT", { XX } },
4e7d34a6
L		 1843 { X86_64_TABLE (X86_64_C4) },
1844 { X86_64_TABLE (X86_64_C5) },
1ceb70f8
L		 1845 { REG_TABLE (REG_C6) },
1846 { REG_TABLE (REG_C7) },
252b5132 1847 /* c8 */
ce518a5f
L		 1848 { "enterT", { Iw, Ib } },
1849 { "leaveT", { XX } },
ddab3d59
JB		 1850 { "Jret{|f}P", { Iw } },
1851 { "Jret{|f}P", { XX } },
ce518a5f
L		 1852 { "int3", { XX } },
1853 { "int", { Ib } },
4e7d34a6 1854 { X86_64_TABLE (X86_64_CE) },
ce518a5f 1855 { "iretP", { XX } },
252b5132 1856 /* d0 */
1ceb70f8
L		 1857 { REG_TABLE (REG_D0) },
1858 { REG_TABLE (REG_D1) },
1859 { REG_TABLE (REG_D2) },
1860 { REG_TABLE (REG_D3) },
4e7d34a6
L		 1861 { X86_64_TABLE (X86_64_D4) },
1862 { X86_64_TABLE (X86_64_D5) },
ce518a5f
L		 1863 { "(bad)", { XX } },
1864 { "xlat", { DSBX } },
252b5132
RH		 1865 /* d8 */
1866 { FLOAT },
1867 { FLOAT },
1868 { FLOAT },
1869 { FLOAT },
1870 { FLOAT },
1871 { FLOAT },
1872 { FLOAT },
1873 { FLOAT },
1874 /* e0 */
ce518a5f
L		 1875 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
1876 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
1877 { "loopFH", { Jb, XX, loop_jcxz_flag } },
1878 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
1879 { "inB", { AL, Ib } },
1880 { "inG", { zAX, Ib } },
1881 { "outB", { Ib, AL } },
1882 { "outG", { Ib, zAX } },
252b5132 1883 /* e8 */
ce518a5f
L		 1884 { "callT", { Jv } },
1885 { "jmpT", { Jv } },
4e7d34a6 1886 { X86_64_TABLE (X86_64_EA) },
ce518a5f
L		 1887 { "jmp", { Jb } },
1888 { "inB", { AL, indirDX } },
1889 { "inG", { zAX, indirDX } },
1890 { "outB", { indirDX, AL } },
1891 { "outG", { indirDX, zAX } },
252b5132 1892 /* f0 */
ce518a5f
L		 1893 { "(bad)", { XX } }, /* lock prefix */
1894 { "icebp", { XX } },
1895 { "(bad)", { XX } }, /* repne */
1896 { "(bad)", { XX } }, /* repz */
1897 { "hlt", { XX } },
1898 { "cmc", { XX } },
1ceb70f8
L		 1899 { REG_TABLE (REG_F6) },
1900 { REG_TABLE (REG_F7) },
252b5132 1901 /* f8 */
ce518a5f
L		 1902 { "clc", { XX } },
1903 { "stc", { XX } },
1904 { "cli", { XX } },
1905 { "sti", { XX } },
1906 { "cld", { XX } },
1907 { "std", { XX } },
1ceb70f8
L		 1908 { REG_TABLE (REG_FE) },
1909 { REG_TABLE (REG_FF) },
252b5132
RH		 1910};
1911
6439fc28 1912static const struct dis386 dis386_twobyte[] = {
252b5132 1913 /* 00 */
1ceb70f8
L		 1914 { REG_TABLE (REG_0F00 ) },
1915 { REG_TABLE (REG_0F01 ) },
ce518a5f
L		 1916 { "larS", { Gv, Ew } },
1917 { "lslS", { Gv, Ew } },
1918 { "(bad)", { XX } },
1919 { "syscall", { XX } },
1920 { "clts", { XX } },
1921 { "sysretP", { XX } },
252b5132 1922 /* 08 */
ce518a5f
L		 1923 { "invd", { XX } },
1924 { "wbinvd", { XX } },
1925 { "(bad)", { XX } },
1926 { "ud2a", { XX } },
1927 { "(bad)", { XX } },
b5b1fc4f 1928 { REG_TABLE (REG_0F0D) },
ce518a5f
L		 1929 { "femms", { XX } },
1930 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
252b5132 1931 /* 10 */
1ceb70f8
L		 1932 { PREFIX_TABLE (PREFIX_0F10) },
1933 { PREFIX_TABLE (PREFIX_0F11) },
1934 { PREFIX_TABLE (PREFIX_0F12) },
1935 { MOD_TABLE (MOD_0F13) },
f2a421c4
L		 1936 { "unpcklpX", { XM, EXx } },
1937 { "unpckhpX", { XM, EXx } },
1ceb70f8
L		 1938 { PREFIX_TABLE (PREFIX_0F16) },
1939 { MOD_TABLE (MOD_0F17) },
252b5132 1940 /* 18 */
1ceb70f8 1941 { REG_TABLE (REG_0F18) },
b5b1fc4f
L		 1942 { "nopQ", { Ev } },
1943 { "nopQ", { Ev } },
1944 { "nopQ", { Ev } },
1945 { "nopQ", { Ev } },
1946 { "nopQ", { Ev } },
1947 { "nopQ", { Ev } },
ce518a5f 1948 { "nopQ", { Ev } },
252b5132 1949 /* 20 */
1ceb70f8
L		 1950 { MOD_TABLE (MOD_0F20) },
1951 { MOD_TABLE (MOD_0F21) },
1952 { MOD_TABLE (MOD_0F22) },
1953 { MOD_TABLE (MOD_0F23) },
1954 { MOD_TABLE (MOD_0F24) },
c1e679ec 1955 { "(bad)", { XX } },
1ceb70f8 1956 { MOD_TABLE (MOD_0F26) },
ce518a5f 1957 { "(bad)", { XX } },
252b5132 1958 /* 28 */
09a2c6cf 1959 { "movapX", { XM, EXx } },
b6169b20 1960 { "movapX", { EXxS, XM } },
1ceb70f8
L		 1961 { PREFIX_TABLE (PREFIX_0F2A) },
1962 { PREFIX_TABLE (PREFIX_0F2B) },
1963 { PREFIX_TABLE (PREFIX_0F2C) },
1964 { PREFIX_TABLE (PREFIX_0F2D) },
1965 { PREFIX_TABLE (PREFIX_0F2E) },
1966 { PREFIX_TABLE (PREFIX_0F2F) },
252b5132 1967 /* 30 */
ce518a5f
L		 1968 { "wrmsr", { XX } },
1969 { "rdtsc", { XX } },
1970 { "rdmsr", { XX } },
1971 { "rdpmc", { XX } },
1972 { "sysenter", { XX } },
1973 { "sysexit", { XX } },
1974 { "(bad)", { XX } },
47dd174c 1975 { "getsec", { XX } },
252b5132 1976 /* 38 */
4e7d34a6 1977 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
ce518a5f 1978 { "(bad)", { XX } },
4e7d34a6 1979 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
ce518a5f
L		 1980 { "(bad)", { XX } },
1981 { "(bad)", { XX } },
1982 { "(bad)", { XX } },
1983 { "(bad)", { XX } },
1984 { "(bad)", { XX } },
252b5132 1985 /* 40 */
b19d5385
JB		 1986 { "cmovoS", { Gv, Ev } },
1987 { "cmovnoS", { Gv, Ev } },
1988 { "cmovbS", { Gv, Ev } },
1989 { "cmovaeS", { Gv, Ev } },
1990 { "cmoveS", { Gv, Ev } },
1991 { "cmovneS", { Gv, Ev } },
1992 { "cmovbeS", { Gv, Ev } },
1993 { "cmovaS", { Gv, Ev } },
252b5132 1994 /* 48 */
b19d5385
JB		 1995 { "cmovsS", { Gv, Ev } },
1996 { "cmovnsS", { Gv, Ev } },
1997 { "cmovpS", { Gv, Ev } },
1998 { "cmovnpS", { Gv, Ev } },
1999 { "cmovlS", { Gv, Ev } },
2000 { "cmovgeS", { Gv, Ev } },
2001 { "cmovleS", { Gv, Ev } },
2002 { "cmovgS", { Gv, Ev } },
252b5132 2003 /* 50 */
75c135a8 2004 { MOD_TABLE (MOD_0F51) },
1ceb70f8
L		 2005 { PREFIX_TABLE (PREFIX_0F51) },
2006 { PREFIX_TABLE (PREFIX_0F52) },
2007 { PREFIX_TABLE (PREFIX_0F53) },
09a2c6cf
L		 2008 { "andpX", { XM, EXx } },
2009 { "andnpX", { XM, EXx } },
2010 { "orpX", { XM, EXx } },
2011 { "xorpX", { XM, EXx } },
252b5132 2012 /* 58 */
1ceb70f8
L		 2013 { PREFIX_TABLE (PREFIX_0F58) },
2014 { PREFIX_TABLE (PREFIX_0F59) },
2015 { PREFIX_TABLE (PREFIX_0F5A) },
2016 { PREFIX_TABLE (PREFIX_0F5B) },
2017 { PREFIX_TABLE (PREFIX_0F5C) },
2018 { PREFIX_TABLE (PREFIX_0F5D) },
2019 { PREFIX_TABLE (PREFIX_0F5E) },
2020 { PREFIX_TABLE (PREFIX_0F5F) },
252b5132 2021 /* 60 */
1ceb70f8
L		 2022 { PREFIX_TABLE (PREFIX_0F60) },
2023 { PREFIX_TABLE (PREFIX_0F61) },
2024 { PREFIX_TABLE (PREFIX_0F62) },
ce518a5f
L		 2025 { "packsswb", { MX, EM } },
2026 { "pcmpgtb", { MX, EM } },
2027 { "pcmpgtw", { MX, EM } },
2028 { "pcmpgtd", { MX, EM } },
2029 { "packuswb", { MX, EM } },
252b5132 2030 /* 68 */
ce518a5f
L		 2031 { "punpckhbw", { MX, EM } },
2032 { "punpckhwd", { MX, EM } },
2033 { "punpckhdq", { MX, EM } },
2034 { "packssdw", { MX, EM } },
1ceb70f8
L		 2035 { PREFIX_TABLE (PREFIX_0F6C) },
2036 { PREFIX_TABLE (PREFIX_0F6D) },
231af070 2037 { "movK", { MX, Edq } },
1ceb70f8 2038 { PREFIX_TABLE (PREFIX_0F6F) },
252b5132 2039 /* 70 */
1ceb70f8
L		 2040 { PREFIX_TABLE (PREFIX_0F70) },
2041 { REG_TABLE (REG_0F71) },
2042 { REG_TABLE (REG_0F72) },
2043 { REG_TABLE (REG_0F73) },
ce518a5f
L		 2044 { "pcmpeqb", { MX, EM } },
2045 { "pcmpeqw", { MX, EM } },
2046 { "pcmpeqd", { MX, EM } },
2047 { "emms", { XX } },
252b5132 2048 /* 78 */
1ceb70f8
L		 2049 { PREFIX_TABLE (PREFIX_0F78) },
2050 { PREFIX_TABLE (PREFIX_0F79) },
4e7d34a6 2051 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
c1e679ec 2052 { "(bad)", { XX } },
1ceb70f8
L		 2053 { PREFIX_TABLE (PREFIX_0F7C) },
2054 { PREFIX_TABLE (PREFIX_0F7D) },
2055 { PREFIX_TABLE (PREFIX_0F7E) },
2056 { PREFIX_TABLE (PREFIX_0F7F) },
252b5132 2057 /* 80 */
ce518a5f
L		 2058 { "joH", { Jv, XX, cond_jump_flag } },
2059 { "jnoH", { Jv, XX, cond_jump_flag } },
2060 { "jbH", { Jv, XX, cond_jump_flag } },
2061 { "jaeH", { Jv, XX, cond_jump_flag } },
2062 { "jeH", { Jv, XX, cond_jump_flag } },
2063 { "jneH", { Jv, XX, cond_jump_flag } },
2064 { "jbeH", { Jv, XX, cond_jump_flag } },
2065 { "jaH", { Jv, XX, cond_jump_flag } },
252b5132 2066 /* 88 */
ce518a5f
L		 2067 { "jsH", { Jv, XX, cond_jump_flag } },
2068 { "jnsH", { Jv, XX, cond_jump_flag } },
2069 { "jpH", { Jv, XX, cond_jump_flag } },
2070 { "jnpH", { Jv, XX, cond_jump_flag } },
2071 { "jlH", { Jv, XX, cond_jump_flag } },
2072 { "jgeH", { Jv, XX, cond_jump_flag } },
2073 { "jleH", { Jv, XX, cond_jump_flag } },
2074 { "jgH", { Jv, XX, cond_jump_flag } },
252b5132 2075 /* 90 */
ce518a5f
L		 2076 { "seto", { Eb } },
2077 { "setno", { Eb } },
2078 { "setb", { Eb } },
2079 { "setae", { Eb } },
2080 { "sete", { Eb } },
2081 { "setne", { Eb } },
2082 { "setbe", { Eb } },
2083 { "seta", { Eb } },
252b5132 2084 /* 98 */
ce518a5f
L		 2085 { "sets", { Eb } },
2086 { "setns", { Eb } },
2087 { "setp", { Eb } },
2088 { "setnp", { Eb } },
2089 { "setl", { Eb } },
2090 { "setge", { Eb } },
2091 { "setle", { Eb } },
2092 { "setg", { Eb } },
252b5132 2093 /* a0 */
ce518a5f
L		 2094 { "pushT", { fs } },
2095 { "popT", { fs } },
2096 { "cpuid", { XX } },
2097 { "btS", { Ev, Gv } },
2098 { "shldS", { Ev, Gv, Ib } },
2099 { "shldS", { Ev, Gv, CL } },
1ceb70f8
L		 2100 { REG_TABLE (REG_0FA6) },
2101 { REG_TABLE (REG_0FA7) },
252b5132 2102 /* a8 */
ce518a5f
L		 2103 { "pushT", { gs } },
2104 { "popT", { gs } },
2105 { "rsm", { XX } },
2106 { "btsS", { Ev, Gv } },
2107 { "shrdS", { Ev, Gv, Ib } },
2108 { "shrdS", { Ev, Gv, CL } },
1ceb70f8 2109 { REG_TABLE (REG_0FAE) },
ce518a5f 2110 { "imulS", { Gv, Ev } },
252b5132 2111 /* b0 */
ce518a5f
L		 2112 { "cmpxchgB", { Eb, Gb } },
2113 { "cmpxchgS", { Ev, Gv } },
1ceb70f8 2114 { MOD_TABLE (MOD_0FB2) },
ce518a5f 2115 { "btrS", { Ev, Gv } },
1ceb70f8
L		 2116 { MOD_TABLE (MOD_0FB4) },
2117 { MOD_TABLE (MOD_0FB5) },
7c52e0e8
L		 2118 { "movz{bR|x}", { Gv, Eb } },
2119 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
252b5132 2120 /* b8 */
1ceb70f8 2121 { PREFIX_TABLE (PREFIX_0FB8) },
ce518a5f 2122 { "ud2b", { XX } },
1ceb70f8 2123 { REG_TABLE (REG_0FBA) },
ce518a5f
L		 2124 { "btcS", { Ev, Gv } },
2125 { "bsfS", { Gv, Ev } },
1ceb70f8 2126 { PREFIX_TABLE (PREFIX_0FBD) },
7c52e0e8
L		 2127 { "movs{bR|x}", { Gv, Eb } },
2128 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
252b5132 2129 /* c0 */
ce518a5f
L		 2130 { "xaddB", { Eb, Gb } },
2131 { "xaddS", { Ev, Gv } },
1ceb70f8 2132 { PREFIX_TABLE (PREFIX_0FC2) },
4ee52178 2133 { PREFIX_TABLE (PREFIX_0FC3) },
ce518a5f
L		 2134 { "pinsrw", { MX, Edqw, Ib } },
2135 { "pextrw", { Gdq, MS, Ib } },
09a2c6cf 2136 { "shufpX", { XM, EXx, Ib } },
1ceb70f8 2137 { REG_TABLE (REG_0FC7) },
252b5132 2138 /* c8 */
ce518a5f
L		 2139 { "bswap", { RMeAX } },
2140 { "bswap", { RMeCX } },
2141 { "bswap", { RMeDX } },
2142 { "bswap", { RMeBX } },
2143 { "bswap", { RMeSP } },
2144 { "bswap", { RMeBP } },
2145 { "bswap", { RMeSI } },
2146 { "bswap", { RMeDI } },
252b5132 2147 /* d0 */
1ceb70f8 2148 { PREFIX_TABLE (PREFIX_0FD0) },
ce518a5f
L		 2149 { "psrlw", { MX, EM } },
2150 { "psrld", { MX, EM } },
2151 { "psrlq", { MX, EM } },
2152 { "paddq", { MX, EM } },
2153 { "pmullw", { MX, EM } },
1ceb70f8 2154 { PREFIX_TABLE (PREFIX_0FD6) },
75c135a8 2155 { MOD_TABLE (MOD_0FD7) },
252b5132 2156 /* d8 */
ce518a5f
L		 2157 { "psubusb", { MX, EM } },
2158 { "psubusw", { MX, EM } },
2159 { "pminub", { MX, EM } },
2160 { "pand", { MX, EM } },
2161 { "paddusb", { MX, EM } },
2162 { "paddusw", { MX, EM } },
2163 { "pmaxub", { MX, EM } },
2164 { "pandn", { MX, EM } },
252b5132 2165 /* e0 */
ce518a5f
L		 2166 { "pavgb", { MX, EM } },
2167 { "psraw", { MX, EM } },
2168 { "psrad", { MX, EM } },
2169 { "pavgw", { MX, EM } },
2170 { "pmulhuw", { MX, EM } },
2171 { "pmulhw", { MX, EM } },
1ceb70f8
L		 2172 { PREFIX_TABLE (PREFIX_0FE6) },
2173 { PREFIX_TABLE (PREFIX_0FE7) },
252b5132 2174 /* e8 */
ce518a5f
L		 2175 { "psubsb", { MX, EM } },
2176 { "psubsw", { MX, EM } },
2177 { "pminsw", { MX, EM } },
2178 { "por", { MX, EM } },
2179 { "paddsb", { MX, EM } },
2180 { "paddsw", { MX, EM } },
2181 { "pmaxsw", { MX, EM } },
2182 { "pxor", { MX, EM } },
252b5132 2183 /* f0 */
1ceb70f8 2184 { PREFIX_TABLE (PREFIX_0FF0) },
ce518a5f
L		 2185 { "psllw", { MX, EM } },
2186 { "pslld", { MX, EM } },
2187 { "psllq", { MX, EM } },
2188 { "pmuludq", { MX, EM } },
2189 { "pmaddwd", { MX, EM } },
2190 { "psadbw", { MX, EM } },
1ceb70f8 2191 { PREFIX_TABLE (PREFIX_0FF7) },
252b5132 2192 /* f8 */
ce518a5f
L		 2193 { "psubb", { MX, EM } },
2194 { "psubw", { MX, EM } },
2195 { "psubd", { MX, EM } },
2196 { "psubq", { MX, EM } },
2197 { "paddb", { MX, EM } },
2198 { "paddw", { MX, EM } },
2199 { "paddd", { MX, EM } },
2200 { "(bad)", { XX } },
252b5132
RH		 2201};
2202
2203static const unsigned char onebyte_has_modrm[256] = {
c608c12e
AM		 2204 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2205 /* ------------------------------- */
2206 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2207 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2208 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2209 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2210 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2211 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2212 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2213 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2214 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2215 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2216 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2217 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2218 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2219 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2220 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2221 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2222 /* ------------------------------- */
2223 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
252b5132
RH		 2224};
2225
2226static const unsigned char twobyte_has_modrm[256] = {
c608c12e
AM		 2227 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2228 /* ------------------------------- */
252b5132 2229 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
b5b1fc4f 2230 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
85f10a01 2231 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
331d2d0d 2232 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
252b5132 2233 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
4bba6815
AM		 2234 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2235 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
85f10a01 2236 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
252b5132
RH		 2237 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2238 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
30d1c836 2239 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
050dfa73 2240 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
252b5132 2241 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
ca164297 2242 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
4bba6815 2243 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
ca164297 2244 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
c608c12e
AM		 2245 /* ------------------------------- */
2246 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2247};
2248
252b5132
RH		 2249static char obuf[100];
2250static char *obufp;
ea397f5b 2251static char *mnemonicendp;
252b5132
RH		 2252static char scratchbuf[100];
2253static unsigned char *start_codep;
2254static unsigned char *insn_codep;
2255static unsigned char *codep;
f16cd0d5
L		 2256static int last_lock_prefix;
2257static int last_repz_prefix;
2258static int last_repnz_prefix;
2259static int last_data_prefix;
2260static int last_addr_prefix;
2261static int last_rex_prefix;
2262static int last_seg_prefix;
2263#define MAX_CODE_LENGTH 15
2264/* We can up to 14 prefixes since the maximum instruction length is
2265 15bytes. */
2266static int all_prefixes[MAX_CODE_LENGTH - 1];
252b5132 2267static disassemble_info *the_info;
7967e09e
L		 2268static struct
2269 {
2270 int mod;
7967e09e 2271 int reg;
484c222e 2272 int rm;
7967e09e
L		 2273 }
2274modrm;
4bba6815 2275static unsigned char need_modrm;
c0f3af97
L		 2276static struct
2277 {
2278 int register_specifier;
2279 int length;
2280 int prefix;
2281 int w;
2282 }
2283vex;
2284static unsigned char need_vex;
2285static unsigned char need_vex_reg;
dae39acc 2286static unsigned char vex_w_done;
252b5132 2287
ea397f5b
L		 2288struct op
2289 {
2290 const char *name;
2291 unsigned int len;
2292 };
2293
4bba6815
AM		 2294/* If we are accessing mod/rm/reg without need_modrm set, then the
2295 values are stale. Hitting this abort likely indicates that you
2296 need to update onebyte_has_modrm or twobyte_has_modrm. */
2297#define MODRM_CHECK if (!need_modrm) abort ()
2298
d708bcba
AM		 2299static const char **names64;
2300static const char **names32;
2301static const char **names16;
2302static const char **names8;
2303static const char **names8rex;
2304static const char **names_seg;
db51cc60
L		 2305static const char *index64;
2306static const char *index32;
d708bcba
AM		 2307static const char **index16;
2308
2309static const char *intel_names64[] = {
2310 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2311 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2312};
2313static const char *intel_names32[] = {
2314 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2315 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2316};
2317static const char *intel_names16[] = {
2318 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2319 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2320};
2321static const char *intel_names8[] = {
2322 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2323};
2324static const char *intel_names8rex[] = {
2325 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2326 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2327};
2328static const char *intel_names_seg[] = {
2329 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2330};
db51cc60
L		 2331static const char *intel_index64 = "riz";
2332static const char *intel_index32 = "eiz";
d708bcba
AM		 2333static const char *intel_index16[] = {
2334 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2335};
2336
2337static const char *att_names64[] = {
2338 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
52b15da3
JH		 2339 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2340};
d708bcba
AM		 2341static const char *att_names32[] = {
2342 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
52b15da3 2343 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
252b5132 2344};
d708bcba
AM		 2345static const char *att_names16[] = {
2346 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
52b15da3 2347 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
252b5132 2348};
d708bcba
AM		 2349static const char *att_names8[] = {
2350 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
252b5132 2351};
d708bcba
AM		 2352static const char *att_names8rex[] = {
2353 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
52b15da3
JH		 2354 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2355};
d708bcba
AM		 2356static const char *att_names_seg[] = {
2357 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
252b5132 2358};
db51cc60
L		 2359static const char *att_index64 = "%riz";
2360static const char *att_index32 = "%eiz";
d708bcba
AM		 2361static const char *att_index16[] = {
2362 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
252b5132
RH		 2363};
2364
1ceb70f8
L		 2365static const struct dis386 reg_table[][8] = {
2366 /* REG_80 */
252b5132 2367 {
ce518a5f
L		 2368 { "addA", { Eb, Ib } },
2369 { "orA", { Eb, Ib } },
2370 { "adcA", { Eb, Ib } },
2371 { "sbbA", { Eb, Ib } },
2372 { "andA", { Eb, Ib } },
2373 { "subA", { Eb, Ib } },
2374 { "xorA", { Eb, Ib } },
2375 { "cmpA", { Eb, Ib } },
252b5132 2376 },
1ceb70f8 2377 /* REG_81 */
252b5132 2378 {
ce518a5f
L		 2379 { "addQ", { Ev, Iv } },
2380 { "orQ", { Ev, Iv } },
2381 { "adcQ", { Ev, Iv } },
2382 { "sbbQ", { Ev, Iv } },
2383 { "andQ", { Ev, Iv } },
2384 { "subQ", { Ev, Iv } },
2385 { "xorQ", { Ev, Iv } },
2386 { "cmpQ", { Ev, Iv } },
252b5132 2387 },
1ceb70f8 2388 /* REG_82 */
252b5132 2389 {
ce518a5f
L		 2390 { "addQ", { Ev, sIb } },
2391 { "orQ", { Ev, sIb } },
2392 { "adcQ", { Ev, sIb } },
2393 { "sbbQ", { Ev, sIb } },
2394 { "andQ", { Ev, sIb } },
2395 { "subQ", { Ev, sIb } },
2396 { "xorQ", { Ev, sIb } },
2397 { "cmpQ", { Ev, sIb } },
252b5132 2398 },
1ceb70f8 2399 /* REG_8F */
4e7d34a6
L		 2400 {
2401 { "popU", { stackEv } },
c48244a5 2402 { XOP_8F_TABLE (XOP_09) },
4e7d34a6
L		 2403 { "(bad)", { XX } },
2404 { "(bad)", { XX } },
2405 { "(bad)", { XX } },
f88c9eb0 2406 { XOP_8F_TABLE (XOP_09) },
4e7d34a6
L		 2407 { "(bad)", { XX } },
2408 { "(bad)", { XX } },
2409 },
1ceb70f8 2410 /* REG_C0 */
252b5132 2411 {
ce518a5f
L		 2412 { "rolA", { Eb, Ib } },
2413 { "rorA", { Eb, Ib } },
2414 { "rclA", { Eb, Ib } },
2415 { "rcrA", { Eb, Ib } },
2416 { "shlA", { Eb, Ib } },
2417 { "shrA", { Eb, Ib } },
2418 { "(bad)", { XX } },
2419 { "sarA", { Eb, Ib } },
252b5132 2420 },
1ceb70f8 2421 /* REG_C1 */
252b5132 2422 {
ce518a5f
L		 2423 { "rolQ", { Ev, Ib } },
2424 { "rorQ", { Ev, Ib } },
2425 { "rclQ", { Ev, Ib } },
2426 { "rcrQ", { Ev, Ib } },
2427 { "shlQ", { Ev, Ib } },
2428 { "shrQ", { Ev, Ib } },
2429 { "(bad)", { XX } },
2430 { "sarQ", { Ev, Ib } },
252b5132 2431 },
1ceb70f8 2432 /* REG_C6 */
4e7d34a6
L		 2433 {
2434 { "movA", { Eb, Ib } },
2435 { "(bad)", { XX } },
2436 { "(bad)", { XX } },
2437 { "(bad)", { XX } },
2438 { "(bad)", { XX } },
2439 { "(bad)", { XX } },
2440 { "(bad)", { XX } },
2441 { "(bad)", { XX } },
2442 },
1ceb70f8 2443 /* REG_C7 */
4e7d34a6
L		 2444 {
2445 { "movQ", { Ev, Iv } },
2446 { "(bad)", { XX } },
2447 { "(bad)", { XX } },
2448 { "(bad)", { XX } },
2449 { "(bad)", { XX } },
2450 { "(bad)", { XX } },
2451 { "(bad)", { XX } },
2452 { "(bad)", { XX } },
2453 },
1ceb70f8 2454 /* REG_D0 */
252b5132 2455 {
ce518a5f
L		 2456 { "rolA", { Eb, I1 } },
2457 { "rorA", { Eb, I1 } },
2458 { "rclA", { Eb, I1 } },
2459 { "rcrA", { Eb, I1 } },
2460 { "shlA", { Eb, I1 } },
2461 { "shrA", { Eb, I1 } },
2462 { "(bad)", { XX } },
2463 { "sarA", { Eb, I1 } },
252b5132 2464 },
1ceb70f8 2465 /* REG_D1 */
252b5132 2466 {
ce518a5f
L		 2467 { "rolQ", { Ev, I1 } },
2468 { "rorQ", { Ev, I1 } },
2469 { "rclQ", { Ev, I1 } },
2470 { "rcrQ", { Ev, I1 } },
2471 { "shlQ", { Ev, I1 } },
2472 { "shrQ", { Ev, I1 } },
2473 { "(bad)", { XX } },
2474 { "sarQ", { Ev, I1 } },
252b5132 2475 },
1ceb70f8 2476 /* REG_D2 */
252b5132 2477 {
ce518a5f
L		 2478 { "rolA", { Eb, CL } },
2479 { "rorA", { Eb, CL } },
2480 { "rclA", { Eb, CL } },
2481 { "rcrA", { Eb, CL } },
2482 { "shlA", { Eb, CL } },
2483 { "shrA", { Eb, CL } },
2484 { "(bad)", { XX } },
2485 { "sarA", { Eb, CL } },
252b5132 2486 },
1ceb70f8 2487 /* REG_D3 */
252b5132 2488 {
ce518a5f
L		 2489 { "rolQ", { Ev, CL } },
2490 { "rorQ", { Ev, CL } },
2491 { "rclQ", { Ev, CL } },
2492 { "rcrQ", { Ev, CL } },
2493 { "shlQ", { Ev, CL } },
2494 { "shrQ", { Ev, CL } },
2495 { "(bad)", { XX } },
2496 { "sarQ", { Ev, CL } },
252b5132 2497 },
1ceb70f8 2498 /* REG_F6 */
252b5132 2499 {
ce518a5f 2500 { "testA", { Eb, Ib } },
058f233b 2501 { "(bad)", { XX } },
ce518a5f
L		 2502 { "notA", { Eb } },
2503 { "negA", { Eb } },
2504 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
2505 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
2506 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
2507 { "idivA", { Eb } }, /* and idiv for consistency. */
252b5132 2508 },
1ceb70f8 2509 /* REG_F7 */
252b5132 2510 {
ce518a5f
L		 2511 { "testQ", { Ev, Iv } },
2512 { "(bad)", { XX } },
2513 { "notQ", { Ev } },
2514 { "negQ", { Ev } },
2515 { "mulQ", { Ev } }, /* Don't print the implicit register. */
2516 { "imulQ", { Ev } },
2517 { "divQ", { Ev } },
2518 { "idivQ", { Ev } },
252b5132 2519 },
1ceb70f8 2520 /* REG_FE */
252b5132 2521 {
ce518a5f
L		 2522 { "incA", { Eb } },
2523 { "decA", { Eb } },
2524 { "(bad)", { XX } },
2525 { "(bad)", { XX } },
2526 { "(bad)", { XX } },
2527 { "(bad)", { XX } },
2528 { "(bad)", { XX } },
2529 { "(bad)", { XX } },
252b5132 2530 },
1ceb70f8 2531 /* REG_FF */
252b5132 2532 {
ce518a5f
L		 2533 { "incQ", { Ev } },
2534 { "decQ", { Ev } },
2535 { "callT", { indirEv } },
2536 { "JcallT", { indirEp } },
2537 { "jmpT", { indirEv } },
2538 { "JjmpT", { indirEp } },
2539 { "pushU", { stackEv } },
2540 { "(bad)", { XX } },
252b5132 2541 },
1ceb70f8 2542 /* REG_0F00 */
252b5132 2543 {
ce518a5f
L		 2544 { "sldtD", { Sv } },
2545 { "strD", { Sv } },
2546 { "lldt", { Ew } },
2547 { "ltr", { Ew } },
2548 { "verr", { Ew } },
2549 { "verw", { Ew } },
2550 { "(bad)", { XX } },
2551 { "(bad)", { XX } },
252b5132 2552 },
1ceb70f8 2553 /* REG_0F01 */
252b5132 2554 {
1ceb70f8
L		 2555 { MOD_TABLE (MOD_0F01_REG_0) },
2556 { MOD_TABLE (MOD_0F01_REG_1) },
2557 { MOD_TABLE (MOD_0F01_REG_2) },
2558 { MOD_TABLE (MOD_0F01_REG_3) },
ce518a5f
L		 2559 { "smswD", { Sv } },
2560 { "(bad)", { XX } },
2561 { "lmsw", { Ew } },
1ceb70f8 2562 { MOD_TABLE (MOD_0F01_REG_7) },
252b5132 2563 },
b5b1fc4f 2564 /* REG_0F0D */
252b5132 2565 {
4e7d34a6
L		 2566 { "prefetch", { Eb } },
2567 { "prefetchw", { Eb } },
2568 { "(bad)", { XX } },
2569 { "(bad)", { XX } },
2570 { "(bad)", { XX } },
2571 { "(bad)", { XX } },
2572 { "(bad)", { XX } },
2573 { "(bad)", { XX } },
252b5132 2574 },
1ceb70f8 2575 /* REG_0F18 */
252b5132 2576 {
1ceb70f8
L		 2577 { MOD_TABLE (MOD_0F18_REG_0) },
2578 { MOD_TABLE (MOD_0F18_REG_1) },
2579 { MOD_TABLE (MOD_0F18_REG_2) },
2580 { MOD_TABLE (MOD_0F18_REG_3) },
ce518a5f
L		 2581 { "(bad)", { XX } },
2582 { "(bad)", { XX } },
2583 { "(bad)", { XX } },
2584 { "(bad)", { XX } },
252b5132 2585 },
1ceb70f8 2586 /* REG_0F71 */
a6bd098c 2587 {
ce518a5f
L		 2588 { "(bad)", { XX } },
2589 { "(bad)", { XX } },
1ceb70f8 2590 { MOD_TABLE (MOD_0F71_REG_2) },
ce518a5f 2591 { "(bad)", { XX } },
1ceb70f8 2592 { MOD_TABLE (MOD_0F71_REG_4) },
ce518a5f 2593 { "(bad)", { XX } },
1ceb70f8 2594 { MOD_TABLE (MOD_0F71_REG_6) },
ce518a5f 2595 { "(bad)", { XX } },
a6bd098c 2596 },
1ceb70f8 2597 /* REG_0F72 */
a6bd098c 2598 {
ce518a5f
L		 2599 { "(bad)", { XX } },
2600 { "(bad)", { XX } },
1ceb70f8 2601 { MOD_TABLE (MOD_0F72_REG_2) },
ce518a5f 2602 { "(bad)", { XX } },
1ceb70f8 2603 { MOD_TABLE (MOD_0F72_REG_4) },
ce518a5f 2604 { "(bad)", { XX } },
1ceb70f8 2605 { MOD_TABLE (MOD_0F72_REG_6) },
ce518a5f 2606 { "(bad)", { XX } },
a6bd098c 2607 },
1ceb70f8 2608 /* REG_0F73 */
252b5132 2609 {
ce518a5f
L		 2610 { "(bad)", { XX } },
2611 { "(bad)", { XX } },
1ceb70f8
L		 2612 { MOD_TABLE (MOD_0F73_REG_2) },
2613 { MOD_TABLE (MOD_0F73_REG_3) },
ce518a5f 2614 { "(bad)", { XX } },
ce518a5f 2615 { "(bad)", { XX } },
1ceb70f8
L		 2616 { MOD_TABLE (MOD_0F73_REG_6) },
2617 { MOD_TABLE (MOD_0F73_REG_7) },
252b5132 2618 },
1ceb70f8 2619 /* REG_0FA6 */
252b5132 2620 {
4e7d34a6
L		 2621 { "montmul", { { OP_0f07, 0 } } },
2622 { "xsha1", { { OP_0f07, 0 } } },
2623 { "xsha256", { { OP_0f07, 0 } } },
2624 { "(bad)", { { OP_0f07, 0 } } },
2625 { "(bad)", { { OP_0f07, 0 } } },
2626 { "(bad)", { { OP_0f07, 0 } } },
2627 { "(bad)", { { OP_0f07, 0 } } },
2628 { "(bad)", { { OP_0f07, 0 } } },
2629 },
1ceb70f8 2630 /* REG_0FA7 */
4e7d34a6
L		 2631 {
2632 { "xstore-rng", { { OP_0f07, 0 } } },
2633 { "xcrypt-ecb", { { OP_0f07, 0 } } },
2634 { "xcrypt-cbc", { { OP_0f07, 0 } } },
2635 { "xcrypt-ctr", { { OP_0f07, 0 } } },
2636 { "xcrypt-cfb", { { OP_0f07, 0 } } },
2637 { "xcrypt-ofb", { { OP_0f07, 0 } } },
2638 { "(bad)", { { OP_0f07, 0 } } },
2639 { "(bad)", { { OP_0f07, 0 } } },
2640 },
1ceb70f8 2641 /* REG_0FAE */
4e7d34a6 2642 {
1ceb70f8
L		 2643 { MOD_TABLE (MOD_0FAE_REG_0) },
2644 { MOD_TABLE (MOD_0FAE_REG_1) },
2645 { MOD_TABLE (MOD_0FAE_REG_2) },
2646 { MOD_TABLE (MOD_0FAE_REG_3) },
475a2301 2647 { MOD_TABLE (MOD_0FAE_REG_4) },
1ceb70f8
L		 2648 { MOD_TABLE (MOD_0FAE_REG_5) },
2649 { MOD_TABLE (MOD_0FAE_REG_6) },
2650 { MOD_TABLE (MOD_0FAE_REG_7) },
252b5132 2651 },
1ceb70f8 2652 /* REG_0FBA */
252b5132 2653 {
ce518a5f
L		 2654 { "(bad)", { XX } },
2655 { "(bad)", { XX } },
d8faab4e
L		 2656 { "(bad)", { XX } },
2657 { "(bad)", { XX } },
4e7d34a6
L		 2658 { "btQ", { Ev, Ib } },
2659 { "btsQ", { Ev, Ib } },
2660 { "btrQ", { Ev, Ib } },
2661 { "btcQ", { Ev, Ib } },
c608c12e 2662 },
1ceb70f8 2663 /* REG_0FC7 */
c608c12e 2664 {
b844680a 2665 { "(bad)", { XX } },
4e7d34a6 2666 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
d8faab4e 2667 { "(bad)", { XX } },
b844680a
L		 2668 { "(bad)", { XX } },
2669 { "(bad)", { XX } },
2670 { "(bad)", { XX } },
1ceb70f8
L		 2671 { MOD_TABLE (MOD_0FC7_REG_6) },
2672 { MOD_TABLE (MOD_0FC7_REG_7) },
252b5132 2673 },
c0f3af97
L		 2674 /* REG_VEX_71 */
2675 {
2676 { "(bad)", { XX } },
2677 { "(bad)", { XX } },
2678 { MOD_TABLE (MOD_VEX_71_REG_2) },
2679 { "(bad)", { XX } },
2680 { MOD_TABLE (MOD_VEX_71_REG_4) },
2681 { "(bad)", { XX } },
2682 { MOD_TABLE (MOD_VEX_71_REG_6) },
2683 { "(bad)", { XX } },
2684 },
2685 /* REG_VEX_72 */
2686 {
2687 { "(bad)", { XX } },
2688 { "(bad)", { XX } },
2689 { MOD_TABLE (MOD_VEX_72_REG_2) },
2690 { "(bad)", { XX } },
2691 { MOD_TABLE (MOD_VEX_72_REG_4) },
2692 { "(bad)", { XX } },
2693 { MOD_TABLE (MOD_VEX_72_REG_6) },
2694 { "(bad)", { XX } },
2695 },
2696 /* REG_VEX_73 */
2697 {
2698 { "(bad)", { XX } },
2699 { "(bad)", { XX } },
2700 { MOD_TABLE (MOD_VEX_73_REG_2) },
2701 { MOD_TABLE (MOD_VEX_73_REG_3) },
2702 { "(bad)", { XX } },
2703 { "(bad)", { XX } },
2704 { MOD_TABLE (MOD_VEX_73_REG_6) },
2705 { MOD_TABLE (MOD_VEX_73_REG_7) },
2706 },
2707 /* REG_VEX_AE */
2708 {
2709 { "(bad)", { XX } },
2710 { "(bad)", { XX } },
2711 { MOD_TABLE (MOD_VEX_AE_REG_2) },
2712 { MOD_TABLE (MOD_VEX_AE_REG_3) },
2713 { "(bad)", { XX } },
2714 { "(bad)", { XX } },
2715 { "(bad)", { XX } },
2716 { "(bad)", { XX } },
2717 },
f88c9eb0
SP		 2718 /* REG_XOP_LWPCB */
2719 {
2720 { "llwpcb", { { OP_LWPCB_E, 0 } } },
2721 { "slwpcb", { { OP_LWPCB_E, 0 } } },
2722 { "(bad)", { XX } },
2723 { "(bad)", { XX } },
2724 { "(bad)", { XX } },
2725 { "(bad)", { XX } },
2726 { "(bad)", { XX } },
2727 { "(bad)", { XX } },
2728 },
2729 /* REG_XOP_LWP */
2730 {
2731 { "lwpins", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2732 { "lwpval", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2733 { "(bad)", { XX } },
2734 { "(bad)", { XX } },
2735 { "(bad)", { XX } },
2736 { "(bad)", { XX } },
2737 { "(bad)", { XX } },
2738 { "(bad)", { XX } },
2739 },
4e7d34a6
L		 2740};
2741
1ceb70f8
L		 2742static const struct dis386 prefix_table[][4] = {
2743 /* PREFIX_90 */
252b5132 2744 {
4e7d34a6
L		 2745 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2746 { "pause", { XX } },
2747 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2748 { "(bad)", { XX } },
0f10071e 2749 },
4e7d34a6 2750
1ceb70f8 2751 /* PREFIX_0F10 */
cc0ec051 2752 {
4e7d34a6
L		 2753 { "movups", { XM, EXx } },
2754 { "movss", { XM, EXd } },
2755 { "movupd", { XM, EXx } },
2756 { "movsd", { XM, EXq } },
30d1c836 2757 },
4e7d34a6 2758
1ceb70f8 2759 /* PREFIX_0F11 */
30d1c836 2760 {
b6169b20 2761 { "movups", { EXxS, XM } },
fa99fab2 2762 { "movss", { EXdS, XM } },
b6169b20 2763 { "movupd", { EXxS, XM } },
fa99fab2 2764 { "movsd", { EXqS, XM } },
4e7d34a6 2765 },
252b5132 2766
1ceb70f8 2767 /* PREFIX_0F12 */
c608c12e 2768 {
1ceb70f8 2769 { MOD_TABLE (MOD_0F12_PREFIX_0) },
4e7d34a6
L		 2770 { "movsldup", { XM, EXx } },
2771 { "movlpd", { XM, EXq } },
2772 { "movddup", { XM, EXq } },
c608c12e 2773 },
4e7d34a6 2774
1ceb70f8 2775 /* PREFIX_0F16 */
c608c12e 2776 {
1ceb70f8 2777 { MOD_TABLE (MOD_0F16_PREFIX_0) },
4e7d34a6
L		 2778 { "movshdup", { XM, EXx } },
2779 { "movhpd", { XM, EXq } },
058f233b 2780 { "(bad)", { XX } },
c608c12e 2781 },
4e7d34a6 2782
1ceb70f8 2783 /* PREFIX_0F2A */
c608c12e 2784 {
09335d05 2785 { "cvtpi2ps", { XM, EMCq } },
98b528ac 2786 { "cvtsi2ss%LQ", { XM, Ev } },
09335d05 2787 { "cvtpi2pd", { XM, EMCq } },
98b528ac 2788 { "cvtsi2sd%LQ", { XM, Ev } },
c608c12e 2789 },
4e7d34a6 2790
1ceb70f8 2791 /* PREFIX_0F2B */
c608c12e 2792 {
75c135a8
L		 2793 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2794 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2795 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2796 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
c608c12e 2797 },
4e7d34a6 2798
1ceb70f8 2799 /* PREFIX_0F2C */
c608c12e 2800 {
09335d05
L		 2801 { "cvttps2pi", { MXC, EXq } },
2802 { "cvttss2siY", { Gv, EXd } },
09a2c6cf 2803 { "cvttpd2pi", { MXC, EXx } },
09335d05 2804 { "cvttsd2siY", { Gv, EXq } },
c608c12e 2805 },
4e7d34a6 2806
1ceb70f8 2807 /* PREFIX_0F2D */
c608c12e 2808 {
4e7d34a6
L		 2809 { "cvtps2pi", { MXC, EXq } },
2810 { "cvtss2siY", { Gv, EXd } },
2811 { "cvtpd2pi", { MXC, EXx } },
2812 { "cvtsd2siY", { Gv, EXq } },
c608c12e 2813 },
4e7d34a6 2814
1ceb70f8 2815 /* PREFIX_0F2E */
c608c12e 2816 {
4e7d34a6
L		 2817 { "ucomiss",{ XM, EXd } },
2818 { "(bad)", { XX } },
2819 { "ucomisd",{ XM, EXq } },
2820 { "(bad)", { XX } },
c608c12e 2821 },
4e7d34a6 2822
1ceb70f8 2823 /* PREFIX_0F2F */
c608c12e 2824 {
4e7d34a6
L		 2825 { "comiss", { XM, EXd } },
2826 { "(bad)", { XX } },
2827 { "comisd", { XM, EXq } },
2828 { "(bad)", { XX } },
c608c12e 2829 },
4e7d34a6 2830
1ceb70f8 2831 /* PREFIX_0F51 */
c608c12e 2832 {
4e7d34a6
L		 2833 { "sqrtps", { XM, EXx } },
2834 { "sqrtss", { XM, EXd } },
2835 { "sqrtpd", { XM, EXx } },
2836 { "sqrtsd", { XM, EXq } },
c608c12e 2837 },
4e7d34a6 2838
1ceb70f8 2839 /* PREFIX_0F52 */
c608c12e 2840 {
4e7d34a6
L		 2841 { "rsqrtps",{ XM, EXx } },
2842 { "rsqrtss",{ XM, EXd } },
058f233b
L		 2843 { "(bad)", { XX } },
2844 { "(bad)", { XX } },
c608c12e 2845 },
4e7d34a6 2846
1ceb70f8 2847 /* PREFIX_0F53 */
c608c12e 2848 {
4e7d34a6
L		 2849 { "rcpps", { XM, EXx } },
2850 { "rcpss", { XM, EXd } },
058f233b
L		 2851 { "(bad)", { XX } },
2852 { "(bad)", { XX } },
c608c12e 2853 },
4e7d34a6 2854
1ceb70f8 2855 /* PREFIX_0F58 */
c608c12e 2856 {
4e7d34a6
L		 2857 { "addps", { XM, EXx } },
2858 { "addss", { XM, EXd } },
2859 { "addpd", { XM, EXx } },
2860 { "addsd", { XM, EXq } },
c608c12e 2861 },
4e7d34a6 2862
1ceb70f8 2863 /* PREFIX_0F59 */
c608c12e 2864 {
4e7d34a6
L		 2865 { "mulps", { XM, EXx } },
2866 { "mulss", { XM, EXd } },
2867 { "mulpd", { XM, EXx } },
2868 { "mulsd", { XM, EXq } },
041bd2e0 2869 },
4e7d34a6 2870
1ceb70f8 2871 /* PREFIX_0F5A */
041bd2e0 2872 {
4e7d34a6
L		 2873 { "cvtps2pd", { XM, EXq } },
2874 { "cvtss2sd", { XM, EXd } },
2875 { "cvtpd2ps", { XM, EXx } },
2876 { "cvtsd2ss", { XM, EXq } },
041bd2e0 2877 },
4e7d34a6 2878
1ceb70f8 2879 /* PREFIX_0F5B */
041bd2e0 2880 {
09a2c6cf
L		 2881 { "cvtdq2ps", { XM, EXx } },
2882 { "cvttps2dq", { XM, EXx } },
2883 { "cvtps2dq", { XM, EXx } },
058f233b 2884 { "(bad)", { XX } },
041bd2e0 2885 },
4e7d34a6 2886
1ceb70f8 2887 /* PREFIX_0F5C */
041bd2e0 2888 {
4e7d34a6
L		 2889 { "subps", { XM, EXx } },
2890 { "subss", { XM, EXd } },
2891 { "subpd", { XM, EXx } },
2892 { "subsd", { XM, EXq } },
041bd2e0 2893 },
4e7d34a6 2894
1ceb70f8 2895 /* PREFIX_0F5D */
041bd2e0 2896 {
4e7d34a6
L		 2897 { "minps", { XM, EXx } },
2898 { "minss", { XM, EXd } },
2899 { "minpd", { XM, EXx } },
2900 { "minsd", { XM, EXq } },
041bd2e0 2901 },
4e7d34a6 2902
1ceb70f8 2903 /* PREFIX_0F5E */
041bd2e0 2904 {
4e7d34a6
L		 2905 { "divps", { XM, EXx } },
2906 { "divss", { XM, EXd } },
2907 { "divpd", { XM, EXx } },
2908 { "divsd", { XM, EXq } },
041bd2e0 2909 },
4e7d34a6 2910
1ceb70f8 2911 /* PREFIX_0F5F */
041bd2e0 2912 {
4e7d34a6
L		 2913 { "maxps", { XM, EXx } },
2914 { "maxss", { XM, EXd } },
2915 { "maxpd", { XM, EXx } },
2916 { "maxsd", { XM, EXq } },
041bd2e0 2917 },
4e7d34a6 2918
1ceb70f8 2919 /* PREFIX_0F60 */
041bd2e0 2920 {
4e7d34a6
L		 2921 { "punpcklbw",{ MX, EMd } },
2922 { "(bad)", { XX } },
2923 { "punpcklbw",{ MX, EMx } },
2924 { "(bad)", { XX } },
041bd2e0 2925 },
4e7d34a6 2926
1ceb70f8 2927 /* PREFIX_0F61 */
041bd2e0 2928 {
4e7d34a6
L		 2929 { "punpcklwd",{ MX, EMd } },
2930 { "(bad)", { XX } },
2931 { "punpcklwd",{ MX, EMx } },
2932 { "(bad)", { XX } },
041bd2e0 2933 },
4e7d34a6 2934
1ceb70f8 2935 /* PREFIX_0F62 */
041bd2e0 2936 {
4e7d34a6
L		 2937 { "punpckldq",{ MX, EMd } },
2938 { "(bad)", { XX } },
2939 { "punpckldq",{ MX, EMx } },
2940 { "(bad)", { XX } },
041bd2e0 2941 },
4e7d34a6 2942
1ceb70f8 2943 /* PREFIX_0F6C */
041bd2e0 2944 {
058f233b
L		 2945 { "(bad)", { XX } },
2946 { "(bad)", { XX } },
4e7d34a6 2947 { "punpcklqdq", { XM, EXx } },
058f233b 2948 { "(bad)", { XX } },
0f17484f 2949 },
4e7d34a6 2950
1ceb70f8 2951 /* PREFIX_0F6D */
0f17484f 2952 {
058f233b
L		 2953 { "(bad)", { XX } },
2954 { "(bad)", { XX } },
4e7d34a6 2955 { "punpckhqdq", { XM, EXx } },
058f233b 2956 { "(bad)", { XX } },
041bd2e0 2957 },
4e7d34a6 2958
1ceb70f8 2959 /* PREFIX_0F6F */
ca164297 2960 {
4e7d34a6
L		 2961 { "movq", { MX, EM } },
2962 { "movdqu", { XM, EXx } },
2963 { "movdqa", { XM, EXx } },
058f233b 2964 { "(bad)", { XX } },
ca164297 2965 },
4e7d34a6 2966
1ceb70f8 2967 /* PREFIX_0F70 */
4e7d34a6
L		 2968 {
2969 { "pshufw", { MX, EM, Ib } },
2970 { "pshufhw",{ XM, EXx, Ib } },
2971 { "pshufd", { XM, EXx, Ib } },
2972 { "pshuflw",{ XM, EXx, Ib } },
2973 },
2974
92fddf8e
L		 2975 /* PREFIX_0F73_REG_3 */
2976 {
2977 { "(bad)", { XX } },
2978 { "(bad)", { XX } },
2979 { "psrldq", { XS, Ib } },
2980 { "(bad)", { XX } },
2981 },
2982
2983 /* PREFIX_0F73_REG_7 */
2984 {
2985 { "(bad)", { XX } },
2986 { "(bad)", { XX } },
2987 { "pslldq", { XS, Ib } },
2988 { "(bad)", { XX } },
2989 },
2990
1ceb70f8 2991 /* PREFIX_0F78 */
4e7d34a6
L		 2992 {
2993 {"vmread", { Em, Gm } },
2994 {"(bad)", { XX } },
2995 {"extrq", { XS, Ib, Ib } },
2996 {"insertq", { XM, XS, Ib, Ib } },
2997 },
2998
1ceb70f8 2999 /* PREFIX_0F79 */
4e7d34a6
L		 3000 {
3001 {"vmwrite", { Gm, Em } },
3002 {"(bad)", { XX } },
3003 {"extrq", { XM, XS } },
3004 {"insertq", { XM, XS } },
3005 },
3006
1ceb70f8 3007 /* PREFIX_0F7C */
ca164297 3008 {
058f233b
L		 3009 { "(bad)", { XX } },
3010 { "(bad)", { XX } },
09a2c6cf
L		 3011 { "haddpd", { XM, EXx } },
3012 { "haddps", { XM, EXx } },
ca164297 3013 },
4e7d34a6 3014
1ceb70f8 3015 /* PREFIX_0F7D */
ca164297 3016 {
058f233b
L		 3017 { "(bad)", { XX } },
3018 { "(bad)", { XX } },
09a2c6cf
L		 3019 { "hsubpd", { XM, EXx } },
3020 { "hsubps", { XM, EXx } },
ca164297 3021 },
4e7d34a6 3022
1ceb70f8 3023 /* PREFIX_0F7E */
ca164297 3024 {
4e7d34a6
L		 3025 { "movK", { Edq, MX } },
3026 { "movq", { XM, EXq } },
3027 { "movK", { Edq, XM } },
058f233b 3028 { "(bad)", { XX } },
ca164297 3029 },
4e7d34a6 3030
1ceb70f8 3031 /* PREFIX_0F7F */
ca164297 3032 {
b6169b20
L		 3033 { "movq", { EMS, MX } },
3034 { "movdqu", { EXxS, XM } },
3035 { "movdqa", { EXxS, XM } },
058f233b 3036 { "(bad)", { XX } },
ca164297 3037 },
4e7d34a6 3038
1ceb70f8 3039 /* PREFIX_0FB8 */
ca164297 3040 {
4e7d34a6
L		 3041 { "(bad)", { XX } },
3042 { "popcntS", { Gv, Ev } },
3043 { "(bad)", { XX } },
3044 { "(bad)", { XX } },
ca164297 3045 },
4e7d34a6 3046
1ceb70f8 3047 /* PREFIX_0FBD */
050dfa73 3048 {
4e7d34a6
L		 3049 { "bsrS", { Gv, Ev } },
3050 { "lzcntS", { Gv, Ev } },
3051 { "bsrS", { Gv, Ev } },
3052 { "(bad)", { XX } },
050dfa73
MM		 3053 },
3054
1ceb70f8 3055 /* PREFIX_0FC2 */
050dfa73 3056 {
ad19981d
L		 3057 { "cmpps", { XM, EXx, CMP } },
3058 { "cmpss", { XM, EXd, CMP } },
3059 { "cmppd", { XM, EXx, CMP } },
3060 { "cmpsd", { XM, EXq, CMP } },
050dfa73 3061 },
246c51aa 3062
4ee52178
L		 3063 /* PREFIX_0FC3 */
3064 {
3065 { "movntiS", { Ma, Gv } },
3066 { "(bad)", { XX } },
3067 { "(bad)", { XX } },
3068 { "(bad)", { XX } },
3069 },
3070
92fddf8e
L		 3071 /* PREFIX_0FC7_REG_6 */
3072 {
3073 { "vmptrld",{ Mq } },
3074 { "vmxon", { Mq } },
3075 { "vmclear",{ Mq } },
3076 { "(bad)", { XX } },
3077 },
3078
1ceb70f8 3079 /* PREFIX_0FD0 */
050dfa73 3080 {
058f233b
L		 3081 { "(bad)", { XX } },
3082 { "(bad)", { XX } },
4e7d34a6
L		 3083 { "addsubpd", { XM, EXx } },
3084 { "addsubps", { XM, EXx } },
246c51aa 3085 },
050dfa73 3086
1ceb70f8 3087 /* PREFIX_0FD6 */
050dfa73 3088 {
058f233b 3089 { "(bad)", { XX } },
4e7d34a6 3090 { "movq2dq",{ XM, MS } },
b6169b20 3091 { "movq", { EXqS, XM } },
4e7d34a6 3092 { "movdq2q",{ MX, XS } },
050dfa73
MM		 3093 },
3094
1ceb70f8 3095 /* PREFIX_0FE6 */
7918206c 3096 {
058f233b 3097 { "(bad)", { XX } },
4e7d34a6
L		 3098 { "cvtdq2pd", { XM, EXq } },
3099 { "cvttpd2dq", { XM, EXx } },
3100 { "cvtpd2dq", { XM, EXx } },
7918206c 3101 },
8b38ad71 3102
1ceb70f8 3103 /* PREFIX_0FE7 */
8b38ad71 3104 {
4ee52178 3105 { "movntq", { Mq, MX } },
058f233b 3106 { "(bad)", { XX } },
75c135a8 3107 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
058f233b 3108 { "(bad)", { XX } },
4e7d34a6
L		 3109 },
3110
1ceb70f8 3111 /* PREFIX_0FF0 */
4e7d34a6 3112 {
058f233b
L		 3113 { "(bad)", { XX } },
3114 { "(bad)", { XX } },
3115 { "(bad)", { XX } },
1ceb70f8 3116 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4e7d34a6
L		 3117 },
3118
1ceb70f8 3119 /* PREFIX_0FF7 */
4e7d34a6
L		 3120 {
3121 { "maskmovq", { MX, MS } },
058f233b 3122 { "(bad)", { XX } },
4e7d34a6 3123 { "maskmovdqu", { XM, XS } },
058f233b 3124 { "(bad)", { XX } },
8b38ad71 3125 },
42903f7f 3126
1ceb70f8 3127 /* PREFIX_0F3810 */
42903f7f
L		 3128 {
3129 { "(bad)", { XX } },
3130 { "(bad)", { XX } },
88a94849 3131 { "pblendvb", { XM, EXx, XMM0 } },
42903f7f
L		 3132 { "(bad)", { XX } },
3133 },
3134
1ceb70f8 3135 /* PREFIX_0F3814 */
42903f7f
L		 3136 {
3137 { "(bad)", { XX } },
3138 { "(bad)", { XX } },
88a94849 3139 { "blendvps", { XM, EXx, XMM0 } },
42903f7f
L		 3140 { "(bad)", { XX } },
3141 },
3142
1ceb70f8 3143 /* PREFIX_0F3815 */
42903f7f
L		 3144 {
3145 { "(bad)", { XX } },
3146 { "(bad)", { XX } },
09a2c6cf 3147 { "blendvpd", { XM, EXx, XMM0 } },
42903f7f
L		 3148 { "(bad)", { XX } },
3149 },
3150
1ceb70f8 3151 /* PREFIX_0F3817 */
42903f7f
L		 3152 {
3153 { "(bad)", { XX } },
3154 { "(bad)", { XX } },
09a2c6cf 3155 { "ptest", { XM, EXx } },
42903f7f
L		 3156 { "(bad)", { XX } },
3157 },
3158
1ceb70f8 3159 /* PREFIX_0F3820 */
42903f7f
L		 3160 {
3161 { "(bad)", { XX } },
3162 { "(bad)", { XX } },
8976381e 3163 { "pmovsxbw", { XM, EXq } },
42903f7f
L		 3164 { "(bad)", { XX } },
3165 },
3166
1ceb70f8 3167 /* PREFIX_0F3821 */
42903f7f
L		 3168 {
3169 { "(bad)", { XX } },
3170 { "(bad)", { XX } },
8976381e 3171 { "pmovsxbd", { XM, EXd } },
42903f7f
L		 3172 { "(bad)", { XX } },
3173 },
3174
1ceb70f8 3175 /* PREFIX_0F3822 */
42903f7f
L		 3176 {
3177 { "(bad)", { XX } },
3178 { "(bad)", { XX } },
8976381e 3179 { "pmovsxbq", { XM, EXw } },
42903f7f
L		 3180 { "(bad)", { XX } },
3181 },
3182
1ceb70f8 3183 /* PREFIX_0F3823 */
42903f7f
L		 3184 {
3185 { "(bad)", { XX } },
3186 { "(bad)", { XX } },
8976381e 3187 { "pmovsxwd", { XM, EXq } },
42903f7f
L		 3188 { "(bad)", { XX } },
3189 },
3190
1ceb70f8 3191 /* PREFIX_0F3824 */
42903f7f
L		 3192 {
3193 { "(bad)", { XX } },
3194 { "(bad)", { XX } },
8976381e 3195 { "pmovsxwq", { XM, EXd } },
42903f7f
L		 3196 { "(bad)", { XX } },
3197 },
3198
1ceb70f8 3199 /* PREFIX_0F3825 */
42903f7f
L		 3200 {
3201 { "(bad)", { XX } },
3202 { "(bad)", { XX } },
8976381e 3203 { "pmovsxdq", { XM, EXq } },
42903f7f
L		 3204 { "(bad)", { XX } },
3205 },
3206
1ceb70f8 3207 /* PREFIX_0F3828 */
42903f7f
L		 3208 {
3209 { "(bad)", { XX } },
3210 { "(bad)", { XX } },
09a2c6cf 3211 { "pmuldq", { XM, EXx } },
42903f7f
L		 3212 { "(bad)", { XX } },
3213 },
3214
1ceb70f8 3215 /* PREFIX_0F3829 */
42903f7f
L		 3216 {
3217 { "(bad)", { XX } },
3218 { "(bad)", { XX } },
09a2c6cf 3219 { "pcmpeqq", { XM, EXx } },
42903f7f
L		 3220 { "(bad)", { XX } },
3221 },
3222
1ceb70f8 3223 /* PREFIX_0F382A */
42903f7f
L		 3224 {
3225 { "(bad)", { XX } },
3226 { "(bad)", { XX } },
75c135a8 3227 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
42903f7f
L		 3228 { "(bad)", { XX } },
3229 },
3230
1ceb70f8 3231 /* PREFIX_0F382B */
42903f7f
L		 3232 {
3233 { "(bad)", { XX } },
3234 { "(bad)", { XX } },
09a2c6cf 3235 { "packusdw", { XM, EXx } },
42903f7f
L		 3236 { "(bad)", { XX } },
3237 },
3238
1ceb70f8 3239 /* PREFIX_0F3830 */
42903f7f
L		 3240 {
3241 { "(bad)", { XX } },
3242 { "(bad)", { XX } },
8976381e 3243 { "pmovzxbw", { XM, EXq } },
42903f7f
L		 3244 { "(bad)", { XX } },
3245 },
3246
1ceb70f8 3247 /* PREFIX_0F3831 */
42903f7f
L		 3248 {
3249 { "(bad)", { XX } },
3250 { "(bad)", { XX } },
8976381e 3251 { "pmovzxbd", { XM, EXd } },
42903f7f
L		 3252 { "(bad)", { XX } },
3253 },
3254
1ceb70f8 3255 /* PREFIX_0F3832 */
42903f7f
L		 3256 {
3257 { "(bad)", { XX } },
3258 { "(bad)", { XX } },
8976381e 3259 { "pmovzxbq", { XM, EXw } },
42903f7f
L		 3260 { "(bad)", { XX } },
3261 },
3262
1ceb70f8 3263 /* PREFIX_0F3833 */
42903f7f
L		 3264 {
3265 { "(bad)", { XX } },
3266 { "(bad)", { XX } },
8976381e 3267 { "pmovzxwd", { XM, EXq } },
42903f7f
L		 3268 { "(bad)", { XX } },
3269 },
3270
1ceb70f8 3271 /* PREFIX_0F3834 */
42903f7f
L		 3272 {
3273 { "(bad)", { XX } },
3274 { "(bad)", { XX } },
8976381e 3275 { "pmovzxwq", { XM, EXd } },
42903f7f
L		 3276 { "(bad)", { XX } },
3277 },
3278
1ceb70f8 3279 /* PREFIX_0F3835 */
42903f7f
L		 3280 {
3281 { "(bad)", { XX } },
3282 { "(bad)", { XX } },
8976381e 3283 { "pmovzxdq", { XM, EXq } },
42903f7f
L		 3284 { "(bad)", { XX } },
3285 },
3286
1ceb70f8 3287 /* PREFIX_0F3837 */
4e7d34a6
L		 3288 {
3289 { "(bad)", { XX } },
3290 { "(bad)", { XX } },
3291 { "pcmpgtq", { XM, EXx } },
3292 { "(bad)", { XX } },
3293 },
3294
1ceb70f8 3295 /* PREFIX_0F3838 */
42903f7f
L		 3296 {
3297 { "(bad)", { XX } },
3298 { "(bad)", { XX } },
09a2c6cf 3299 { "pminsb", { XM, EXx } },
42903f7f
L		 3300 { "(bad)", { XX } },
3301 },
3302
1ceb70f8 3303 /* PREFIX_0F3839 */
42903f7f
L		 3304 {
3305 { "(bad)", { XX } },
3306 { "(bad)", { XX } },
09a2c6cf 3307 { "pminsd", { XM, EXx } },
42903f7f
L		 3308 { "(bad)", { XX } },
3309 },
3310
1ceb70f8 3311 /* PREFIX_0F383A */
42903f7f
L		 3312 {
3313 { "(bad)", { XX } },
3314 { "(bad)", { XX } },
09a2c6cf 3315 { "pminuw", { XM, EXx } },
42903f7f
L		 3316 { "(bad)", { XX } },
3317 },
3318
1ceb70f8 3319 /* PREFIX_0F383B */
42903f7f
L		 3320 {
3321 { "(bad)", { XX } },
3322 { "(bad)", { XX } },
09a2c6cf 3323 { "pminud", { XM, EXx } },
42903f7f
L		 3324 { "(bad)", { XX } },
3325 },
3326
1ceb70f8 3327 /* PREFIX_0F383C */
42903f7f
L		 3328 {
3329 { "(bad)", { XX } },
3330 { "(bad)", { XX } },
09a2c6cf 3331 { "pmaxsb", { XM, EXx } },
42903f7f
L		 3332 { "(bad)", { XX } },
3333 },
3334
1ceb70f8 3335 /* PREFIX_0F383D */
42903f7f
L		 3336 {
3337 { "(bad)", { XX } },
3338 { "(bad)", { XX } },
09a2c6cf 3339 { "pmaxsd", { XM, EXx } },
42903f7f
L		 3340 { "(bad)", { XX } },
3341 },
3342
1ceb70f8 3343 /* PREFIX_0F383E */
42903f7f
L		 3344 {
3345 { "(bad)", { XX } },
3346 { "(bad)", { XX } },
09a2c6cf 3347 { "pmaxuw", { XM, EXx } },
42903f7f
L		 3348 { "(bad)", { XX } },
3349 },
3350
1ceb70f8 3351 /* PREFIX_0F383F */
42903f7f
L		 3352 {
3353 { "(bad)", { XX } },
3354 { "(bad)", { XX } },
09a2c6cf 3355 { "pmaxud", { XM, EXx } },
42903f7f
L		 3356 { "(bad)", { XX } },
3357 },
3358
1ceb70f8 3359 /* PREFIX_0F3840 */
42903f7f
L		 3360 {
3361 { "(bad)", { XX } },
3362 { "(bad)", { XX } },
09a2c6cf 3363 { "pmulld", { XM, EXx } },
42903f7f
L		 3364 { "(bad)", { XX } },
3365 },
3366
1ceb70f8 3367 /* PREFIX_0F3841 */
42903f7f
L		 3368 {
3369 { "(bad)", { XX } },
3370 { "(bad)", { XX } },
09a2c6cf 3371 { "phminposuw", { XM, EXx } },
42903f7f
L		 3372 { "(bad)", { XX } },
3373 },
3374
f1f8f695
L		 3375 /* PREFIX_0F3880 */
3376 {
3377 { "(bad)", { XX } },
3378 { "(bad)", { XX } },
3379 { "invept", { Gm, Mo } },
3380 { "(bad)", { XX } },
3381 },
3382
3383 /* PREFIX_0F3881 */
3384 {
3385 { "(bad)", { XX } },
3386 { "(bad)", { XX } },
3387 { "invvpid", { Gm, Mo } },
3388 { "(bad)", { XX } },
3389 },
3390
c0f3af97
L		 3391 /* PREFIX_0F38DB */
3392 {
3393 { "(bad)", { XX } },
3394 { "(bad)", { XX } },
3395 { "aesimc", { XM, EXx } },
3396 { "(bad)", { XX } },
3397 },
3398
3399 /* PREFIX_0F38DC */
3400 {
3401 { "(bad)", { XX } },
3402 { "(bad)", { XX } },
3403 { "aesenc", { XM, EXx } },
3404 { "(bad)", { XX } },
3405 },
3406
3407 /* PREFIX_0F38DD */
3408 {
3409 { "(bad)", { XX } },
3410 { "(bad)", { XX } },
3411 { "aesenclast", { XM, EXx } },
3412 { "(bad)", { XX } },
3413 },
3414
3415 /* PREFIX_0F38DE */
3416 {
3417 { "(bad)", { XX } },
3418 { "(bad)", { XX } },
3419 { "aesdec", { XM, EXx } },
3420 { "(bad)", { XX } },
3421 },
3422
3423 /* PREFIX_0F38DF */
3424 {
3425 { "(bad)", { XX } },
3426 { "(bad)", { XX } },
3427 { "aesdeclast", { XM, EXx } },
3428 { "(bad)", { XX } },
3429 },
3430
1ceb70f8 3431 /* PREFIX_0F38F0 */
4e7d34a6 3432 {
f1f8f695 3433 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4e7d34a6 3434 { "(bad)", { XX } },
f1f8f695 3435 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4e7d34a6
L		 3436 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
3437 },
3438
1ceb70f8 3439 /* PREFIX_0F38F1 */
4e7d34a6 3440 {
f1f8f695 3441 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4e7d34a6 3442 { "(bad)", { XX } },
f1f8f695 3443 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4e7d34a6
L		 3444 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
3445 },
3446
1ceb70f8 3447 /* PREFIX_0F3A08 */
42903f7f
L		 3448 {
3449 { "(bad)", { XX } },
3450 { "(bad)", { XX } },
09a2c6cf 3451 { "roundps", { XM, EXx, Ib } },
42903f7f
L		 3452 { "(bad)", { XX } },
3453 },
3454
1ceb70f8 3455 /* PREFIX_0F3A09 */
42903f7f
L		 3456 {
3457 { "(bad)", { XX } },
3458 { "(bad)", { XX } },
09a2c6cf 3459 { "roundpd", { XM, EXx, Ib } },
42903f7f
L		 3460 { "(bad)", { XX } },
3461 },
3462
1ceb70f8 3463 /* PREFIX_0F3A0A */
42903f7f
L		 3464 {
3465 { "(bad)", { XX } },
3466 { "(bad)", { XX } },
09335d05 3467 { "roundss", { XM, EXd, Ib } },
42903f7f
L		 3468 { "(bad)", { XX } },
3469 },
3470
1ceb70f8 3471 /* PREFIX_0F3A0B */
42903f7f
L		 3472 {
3473 { "(bad)", { XX } },
3474 { "(bad)", { XX } },
09335d05 3475 { "roundsd", { XM, EXq, Ib } },
42903f7f
L		 3476 { "(bad)", { XX } },
3477 },
3478
1ceb70f8 3479 /* PREFIX_0F3A0C */
42903f7f
L		 3480 {
3481 { "(bad)", { XX } },
3482 { "(bad)", { XX } },
09a2c6cf 3483 { "blendps", { XM, EXx, Ib } },
42903f7f
L		 3484 { "(bad)", { XX } },
3485 },
3486
1ceb70f8 3487 /* PREFIX_0F3A0D */
42903f7f
L		 3488 {
3489 { "(bad)", { XX } },
3490 { "(bad)", { XX } },
09a2c6cf 3491 { "blendpd", { XM, EXx, Ib } },
42903f7f
L		 3492 { "(bad)", { XX } },
3493 },
3494
1ceb70f8 3495 /* PREFIX_0F3A0E */
42903f7f
L		 3496 {
3497 { "(bad)", { XX } },
3498 { "(bad)", { XX } },
09a2c6cf 3499 { "pblendw", { XM, EXx, Ib } },
42903f7f
L		 3500 { "(bad)", { XX } },
3501 },
3502
1ceb70f8 3503 /* PREFIX_0F3A14 */
42903f7f
L		 3504 {
3505 { "(bad)", { XX } },
3506 { "(bad)", { XX } },
3507 { "pextrb", { Edqb, XM, Ib } },
3508 { "(bad)", { XX } },
3509 },
3510
1ceb70f8 3511 /* PREFIX_0F3A15 */
42903f7f
L		 3512 {
3513 { "(bad)", { XX } },
3514 { "(bad)", { XX } },
3515 { "pextrw", { Edqw, XM, Ib } },
3516 { "(bad)", { XX } },
3517 },
3518
1ceb70f8 3519 /* PREFIX_0F3A16 */
42903f7f
L		 3520 {
3521 { "(bad)", { XX } },
3522 { "(bad)", { XX } },
3523 { "pextrK", { Edq, XM, Ib } },
3524 { "(bad)", { XX } },
3525 },
3526
1ceb70f8 3527 /* PREFIX_0F3A17 */
42903f7f
L		 3528 {
3529 { "(bad)", { XX } },
3530 { "(bad)", { XX } },
3531 { "extractps", { Edqd, XM, Ib } },
3532 { "(bad)", { XX } },
3533 },
3534
1ceb70f8 3535 /* PREFIX_0F3A20 */
42903f7f
L		 3536 {
3537 { "(bad)", { XX } },
3538 { "(bad)", { XX } },
3539 { "pinsrb", { XM, Edqb, Ib } },
3540 { "(bad)", { XX } },
3541 },
3542
1ceb70f8 3543 /* PREFIX_0F3A21 */
42903f7f
L		 3544 {
3545 { "(bad)", { XX } },
3546 { "(bad)", { XX } },
8976381e 3547 { "insertps", { XM, EXd, Ib } },
42903f7f
L		 3548 { "(bad)", { XX } },
3549 },
3550
1ceb70f8 3551 /* PREFIX_0F3A22 */
42903f7f
L		 3552 {
3553 { "(bad)", { XX } },
3554 { "(bad)", { XX } },
3555 { "pinsrK", { XM, Edq, Ib } },
3556 { "(bad)", { XX } },
3557 },
3558
1ceb70f8 3559 /* PREFIX_0F3A40 */
42903f7f
L		 3560 {
3561 { "(bad)", { XX } },
3562 { "(bad)", { XX } },
09a2c6cf 3563 { "dpps", { XM, EXx, Ib } },
42903f7f
L		 3564 { "(bad)", { XX } },
3565 },
3566
1ceb70f8 3567 /* PREFIX_0F3A41 */
42903f7f
L		 3568 {
3569 { "(bad)", { XX } },
3570 { "(bad)", { XX } },
09a2c6cf 3571 { "dppd", { XM, EXx, Ib } },
42903f7f
L		 3572 { "(bad)", { XX } },
3573 },
3574
1ceb70f8 3575 /* PREFIX_0F3A42 */
42903f7f
L		 3576 {
3577 { "(bad)", { XX } },
3578 { "(bad)", { XX } },
09a2c6cf 3579 { "mpsadbw", { XM, EXx, Ib } },
42903f7f
L		 3580 { "(bad)", { XX } },
3581 },
381d071f 3582
c0f3af97
L		 3583 /* PREFIX_0F3A44 */
3584 {
3585 { "(bad)", { XX } },
3586 { "(bad)", { XX } },
3587 { "pclmulqdq", { XM, EXx, PCLMUL } },
3588 { "(bad)", { XX } },
3589 },
3590
1ceb70f8 3591 /* PREFIX_0F3A60 */
381d071f
L		 3592 {
3593 { "(bad)", { XX } },
3594 { "(bad)", { XX } },
4e7d34a6 3595 { "pcmpestrm", { XM, EXx, Ib } },
381d071f
L		 3596 { "(bad)", { XX } },
3597 },
3598
1ceb70f8 3599 /* PREFIX_0F3A61 */
381d071f
L		 3600 {
3601 { "(bad)", { XX } },
3602 { "(bad)", { XX } },
4e7d34a6 3603 { "pcmpestri", { XM, EXx, Ib } },
381d071f 3604 { "(bad)", { XX } },
381d071f
L		 3605 },
3606
1ceb70f8 3607 /* PREFIX_0F3A62 */
381d071f
L		 3608 {
3609 { "(bad)", { XX } },
3610 { "(bad)", { XX } },
4e7d34a6 3611 { "pcmpistrm", { XM, EXx, Ib } },
381d071f 3612 { "(bad)", { XX } },
381d071f
L		 3613 },
3614
1ceb70f8 3615 /* PREFIX_0F3A63 */
381d071f
L		 3616 {
3617 { "(bad)", { XX } },
3618 { "(bad)", { XX } },
4e7d34a6 3619 { "pcmpistri", { XM, EXx, Ib } },
381d071f
L		 3620 { "(bad)", { XX } },
3621 },
09a2c6cf 3622
c0f3af97 3623 /* PREFIX_0F3ADF */
09a2c6cf 3624 {
c0f3af97
L		 3625 { "(bad)", { XX } },
3626 { "(bad)", { XX } },
3627 { "aeskeygenassist", { XM, EXx, Ib } },
3628 { "(bad)", { XX } },
09a2c6cf
L		 3629 },
3630
c0f3af97 3631 /* PREFIX_VEX_10 */
09a2c6cf 3632 {
9e30b8e0 3633 { VEX_W_TABLE (VEX_W_10_P_0) },
c0f3af97 3634 { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
9e30b8e0 3635 { VEX_W_TABLE (VEX_W_10_P_2) },
c0f3af97 3636 { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
09a2c6cf
L		 3637 },
3638
c0f3af97 3639 /* PREFIX_VEX_11 */
09a2c6cf 3640 {
9e30b8e0 3641 { VEX_W_TABLE (VEX_W_11_P_0) },
c0f3af97 3642 { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
9e30b8e0 3643 { VEX_W_TABLE (VEX_W_11_P_2) },
c0f3af97 3644 { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
09a2c6cf
L		 3645 },
3646
c0f3af97 3647 /* PREFIX_VEX_12 */
09a2c6cf 3648 {
c0f3af97 3649 { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
9e30b8e0 3650 { VEX_W_TABLE (VEX_W_12_P_1) },
c0f3af97 3651 { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
9e30b8e0 3652 { VEX_W_TABLE (VEX_W_12_P_3) },
09a2c6cf
L		 3653 },
3654
c0f3af97 3655 /* PREFIX_VEX_16 */
09a2c6cf 3656 {
c0f3af97 3657 { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
9e30b8e0 3658 { VEX_W_TABLE (VEX_W_16_P_1) },
c0f3af97
L		 3659 { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3660 { "(bad)", { XX } },
5f754f58 3661 },
7c52e0e8 3662
c0f3af97 3663 /* PREFIX_VEX_2A */
5f754f58 3664 {
c0f3af97
L		 3665 { "(bad)", { XX } },
3666 { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3667 { "(bad)", { XX } },
3668 { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
5f754f58 3669 },
7c52e0e8 3670
c0f3af97 3671 /* PREFIX_VEX_2C */
5f754f58 3672 {
c0f3af97
L		 3673 { "(bad)", { XX } },
3674 { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3675 { "(bad)", { XX } },
3676 { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
5f754f58 3677 },
7c52e0e8 3678
c0f3af97 3679 /* PREFIX_VEX_2D */
7c52e0e8 3680 {
c0f3af97
L		 3681 { "(bad)", { XX } },
3682 { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3683 { "(bad)", { XX } },
3684 { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
7c52e0e8
L		 3685 },
3686
c0f3af97 3687 /* PREFIX_VEX_2E */
7c52e0e8 3688 {
c0f3af97
L		 3689 { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3690 { "(bad)", { XX } },
3691 { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3692 { "(bad)", { XX } },
7c52e0e8
L		 3693 },
3694
c0f3af97 3695 /* PREFIX_VEX_2F */
7c52e0e8 3696 {
c0f3af97
L		 3697 { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3698 { "(bad)", { XX } },
3699 { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3700 { "(bad)", { XX } },
7c52e0e8
L		 3701 },
3702
c0f3af97 3703 /* PREFIX_VEX_51 */
7c52e0e8 3704 {
9e30b8e0 3705 { VEX_W_TABLE (VEX_W_51_P_0) },
c0f3af97 3706 { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
9e30b8e0 3707 { VEX_W_TABLE (VEX_W_51_P_2) },
c0f3af97 3708 { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
7c52e0e8
L		 3709 },
3710
c0f3af97 3711 /* PREFIX_VEX_52 */
7c52e0e8 3712 {
9e30b8e0 3713 { VEX_W_TABLE (VEX_W_52_P_0) },
c0f3af97
L		 3714 { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3715 { "(bad)", { XX } },
3716 { "(bad)", { XX } },
7c52e0e8
L		 3717 },
3718
c0f3af97 3719 /* PREFIX_VEX_53 */
7c52e0e8 3720 {
9e30b8e0 3721 { VEX_W_TABLE (VEX_W_53_P_0) },
c0f3af97
L		 3722 { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3723 { "(bad)", { XX } },
3724 { "(bad)", { XX } },
7c52e0e8
L		 3725 },
3726
c0f3af97 3727 /* PREFIX_VEX_58 */
7c52e0e8 3728 {
9e30b8e0 3729 { VEX_W_TABLE (VEX_W_58_P_0) },
c0f3af97 3730 { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
9e30b8e0 3731 { VEX_W_TABLE (VEX_W_58_P_2) },
c0f3af97 3732 { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
7c52e0e8
L		 3733 },
3734
c0f3af97 3735 /* PREFIX_VEX_59 */
7c52e0e8 3736 {
9e30b8e0 3737 { VEX_W_TABLE (VEX_W_59_P_0) },
c0f3af97 3738 { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
9e30b8e0 3739 { VEX_W_TABLE (VEX_W_59_P_2) },
c0f3af97 3740 { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
7c52e0e8
L		 3741 },
3742
c0f3af97 3743 /* PREFIX_VEX_5A */
7c52e0e8 3744 {
9e30b8e0 3745 { VEX_W_TABLE (VEX_W_5A_P_0) },
c0f3af97
L		 3746 { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3747 { "vcvtpd2ps%XY", { XMM, EXx } },
3748 { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
7c52e0e8
L		 3749 },
3750
c0f3af97 3751 /* PREFIX_VEX_5B */
7c52e0e8 3752 {
9e30b8e0
L		 3753 { VEX_W_TABLE (VEX_W_5B_P_0) },
3754 { VEX_W_TABLE (VEX_W_5B_P_1) },
3755 { VEX_W_TABLE (VEX_W_5B_P_2) },
c0f3af97 3756 { "(bad)", { XX } },
7c52e0e8
L		 3757 },
3758
c0f3af97 3759 /* PREFIX_VEX_5C */
7c52e0e8 3760 {
9e30b8e0 3761 { VEX_W_TABLE (VEX_W_5C_P_0) },
c0f3af97 3762 { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
9e30b8e0 3763 { VEX_W_TABLE (VEX_W_5C_P_2) },
c0f3af97 3764 { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
7c52e0e8
L		 3765 },
3766
c0f3af97 3767 /* PREFIX_VEX_5D */
7c52e0e8 3768 {
9e30b8e0 3769 { VEX_W_TABLE (VEX_W_5D_P_0) },
c0f3af97 3770 { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
9e30b8e0 3771 { VEX_W_TABLE (VEX_W_5D_P_2) },
c0f3af97 3772 { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
7c52e0e8
L		 3773 },
3774
c0f3af97 3775 /* PREFIX_VEX_5E */
7c52e0e8 3776 {
9e30b8e0 3777 { VEX_W_TABLE (VEX_W_5E_P_0) },
c0f3af97 3778 { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
9e30b8e0 3779 { VEX_W_TABLE (VEX_W_5E_P_2) },
c0f3af97 3780 { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
7c52e0e8
L		 3781 },
3782
c0f3af97 3783 /* PREFIX_VEX_5F */
7c52e0e8 3784 {
9e30b8e0 3785 { VEX_W_TABLE (VEX_W_5F_P_0) },
c0f3af97 3786 { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
9e30b8e0 3787 { VEX_W_TABLE (VEX_W_5F_P_2) },
c0f3af97 3788 { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
7c52e0e8
L		 3789 },
3790
c0f3af97 3791 /* PREFIX_VEX_60 */
7c52e0e8 3792 {
c0f3af97
L		 3793 { "(bad)", { XX } },
3794 { "(bad)", { XX } },
3795 { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3796 { "(bad)", { XX } },
7c52e0e8
L		 3797 },
3798
c0f3af97 3799 /* PREFIX_VEX_61 */
7c52e0e8 3800 {
c0f3af97
L		 3801 { "(bad)", { XX } },
3802 { "(bad)", { XX } },
3803 { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3804 { "(bad)", { XX } },
7c52e0e8
L		 3805 },
3806
c0f3af97 3807 /* PREFIX_VEX_62 */
7c52e0e8 3808 {
c0f3af97
L		 3809 { "(bad)", { XX } },
3810 { "(bad)", { XX } },
3811 { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3812 { "(bad)", { XX } },
7c52e0e8
L		 3813 },
3814
c0f3af97 3815 /* PREFIX_VEX_63 */
7c52e0e8 3816 {
c0f3af97
L		 3817 { "(bad)", { XX } },
3818 { "(bad)", { XX } },
3819 { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3820 { "(bad)", { XX } },
7c52e0e8
L		 3821 },
3822
c0f3af97 3823 /* PREFIX_VEX_64 */
7c52e0e8 3824 {
c0f3af97
L		 3825 { "(bad)", { XX } },
3826 { "(bad)", { XX } },
3827 { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3828 { "(bad)", { XX } },
7c52e0e8
L		 3829 },
3830
c0f3af97 3831 /* PREFIX_VEX_65 */
7c52e0e8 3832 {
c0f3af97
L		 3833 { "(bad)", { XX } },
3834 { "(bad)", { XX } },
3835 { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3836 { "(bad)", { XX } },
7c52e0e8
L		 3837 },
3838
c0f3af97 3839 /* PREFIX_VEX_66 */
7c52e0e8 3840 {
c0f3af97
L		 3841 { "(bad)", { XX } },
3842 { "(bad)", { XX } },
3843 { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3844 { "(bad)", { XX } },
7c52e0e8 3845 },
6439fc28 3846
c0f3af97 3847 /* PREFIX_VEX_67 */
331d2d0d 3848 {
c0f3af97
L		 3849 { "(bad)", { XX } },
3850 { "(bad)", { XX } },
3851 { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3852 { "(bad)", { XX } },
3853 },
3854
3855 /* PREFIX_VEX_68 */
3856 {
3857 { "(bad)", { XX } },
3858 { "(bad)", { XX } },
3859 { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3860 { "(bad)", { XX } },
3861 },
3862
3863 /* PREFIX_VEX_69 */
3864 {
3865 { "(bad)", { XX } },
3866 { "(bad)", { XX } },
3867 { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3868 { "(bad)", { XX } },
3869 },
3870
3871 /* PREFIX_VEX_6A */
3872 {
3873 { "(bad)", { XX } },
3874 { "(bad)", { XX } },
3875 { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3876 { "(bad)", { XX } },
3877 },
3878
3879 /* PREFIX_VEX_6B */
3880 {
3881 { "(bad)", { XX } },
3882 { "(bad)", { XX } },
3883 { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3884 { "(bad)", { XX } },
3885 },
3886
3887 /* PREFIX_VEX_6C */
3888 {
3889 { "(bad)", { XX } },
3890 { "(bad)", { XX } },
3891 { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3892 { "(bad)", { XX } },
3893 },
3894
3895 /* PREFIX_VEX_6D */
3896 {
3897 { "(bad)", { XX } },
3898 { "(bad)", { XX } },
3899 { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3900 { "(bad)", { XX } },
3901 },
3902
3903 /* PREFIX_VEX_6E */
3904 {
3905 { "(bad)", { XX } },
3906 { "(bad)", { XX } },
3907 { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3908 { "(bad)", { XX } },
3909 },
3910
3911 /* PREFIX_VEX_6F */
3912 {
3913 { "(bad)", { XX } },
9e30b8e0
L		 3914 { VEX_W_TABLE (VEX_W_6F_P_1) },
3915 { VEX_W_TABLE (VEX_W_6F_P_2) },
c0f3af97
L		 3916 { "(bad)", { XX } },
3917 },
3918
3919 /* PREFIX_VEX_70 */
3920 {
3921 { "(bad)", { XX } },
3922 { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3923 { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3924 { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3925 },
3926
3927 /* PREFIX_VEX_71_REG_2 */
3928 {
3929 { "(bad)", { XX } },
3930 { "(bad)", { XX } },
3931 { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3932 { "(bad)", { XX } },
3933 },
3934
3935 /* PREFIX_VEX_71_REG_4 */
3936 {
3937 { "(bad)", { XX } },
3938 { "(bad)", { XX } },
3939 { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3940 { "(bad)", { XX } },
3941 },
3942
3943 /* PREFIX_VEX_71_REG_6 */
3944 {
3945 { "(bad)", { XX } },
3946 { "(bad)", { XX } },
3947 { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3948 { "(bad)", { XX } },
3949 },
3950
3951 /* PREFIX_VEX_72_REG_2 */
3952 {
3953 { "(bad)", { XX } },
3954 { "(bad)", { XX } },
3955 { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3956 { "(bad)", { XX } },
3957 },
3958
3959 /* PREFIX_VEX_72_REG_4 */
3960 {
3961 { "(bad)", { XX } },
3962 { "(bad)", { XX } },
3963 { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3964 { "(bad)", { XX } },
3965 },
3966
3967 /* PREFIX_VEX_72_REG_6 */
3968 {
3969 { "(bad)", { XX } },
3970 { "(bad)", { XX } },
3971 { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3972 { "(bad)", { XX } },
3973 },
3974
3975 /* PREFIX_VEX_73_REG_2 */
3976 {
3977 { "(bad)", { XX } },
3978 { "(bad)", { XX } },
3979 { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3980 { "(bad)", { XX } },
3981 },
3982
3983 /* PREFIX_VEX_73_REG_3 */
3984 {
3985 { "(bad)", { XX } },
3986 { "(bad)", { XX } },
3987 { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3988 { "(bad)", { XX } },
3989 },
3990
3991 /* PREFIX_VEX_73_REG_6 */
3992 {
3993 { "(bad)", { XX } },
3994 { "(bad)", { XX } },
3995 { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3996 { "(bad)", { XX } },
3997 },
3998
3999 /* PREFIX_VEX_73_REG_7 */
4000 {
4001 { "(bad)", { XX } },
4002 { "(bad)", { XX } },
4003 { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
4004 { "(bad)", { XX } },
4005 },
4006
4007 /* PREFIX_VEX_74 */
4008 {
4009 { "(bad)", { XX } },
4010 { "(bad)", { XX } },
4011 { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
4012 { "(bad)", { XX } },
4013 },
4014
4015 /* PREFIX_VEX_75 */
4016 {
4017 { "(bad)", { XX } },
4018 { "(bad)", { XX } },
4019 { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
4020 { "(bad)", { XX } },
4021 },
4022
4023 /* PREFIX_VEX_76 */
4024 {
4025 { "(bad)", { XX } },
4026 { "(bad)", { XX } },
4027 { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
4028 { "(bad)", { XX } },
4029 },
4030
4031 /* PREFIX_VEX_77 */
4032 {
9e30b8e0 4033 { VEX_W_TABLE (VEX_W_77_P_0) },
c0f3af97
L		 4034 { "(bad)", { XX } },
4035 { "(bad)", { XX } },
4036 { "(bad)", { XX } },
4037 },
4038
4039 /* PREFIX_VEX_7C */
4040 {
4041 { "(bad)", { XX } },
4042 { "(bad)", { XX } },
9e30b8e0
L		 4043 { VEX_W_TABLE (VEX_W_7C_P_2) },
4044 { VEX_W_TABLE (VEX_W_7C_P_3) },
c0f3af97
L		 4045 },
4046
4047 /* PREFIX_VEX_7D */
4048 {
4049 { "(bad)", { XX } },
4050 { "(bad)", { XX } },
9e30b8e0
L		 4051 { VEX_W_TABLE (VEX_W_7D_P_2) },
4052 { VEX_W_TABLE (VEX_W_7D_P_3) },
c0f3af97
L		 4053 },
4054
4055 /* PREFIX_VEX_7E */
4056 {
4057 { "(bad)", { XX } },
4058 { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
4059 { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
4060 { "(bad)", { XX } },
4061 },
4062
4063 /* PREFIX_VEX_7F */
4064 {
4065 { "(bad)", { XX } },
9e30b8e0
L		 4066 { VEX_W_TABLE (VEX_W_7F_P_1) },
4067 { VEX_W_TABLE (VEX_W_7F_P_2) },
c0f3af97
L		 4068 { "(bad)", { XX } },
4069 },
4070
4071 /* PREFIX_VEX_C2 */
4072 {
9e30b8e0 4073 { VEX_W_TABLE (VEX_W_C2_P_0) },
c0f3af97 4074 { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
9e30b8e0 4075 { VEX_W_TABLE (VEX_W_C2_P_2) },
c0f3af97
L		 4076 { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
4077 },
4078
4079 /* PREFIX_VEX_C4 */
4080 {
4081 { "(bad)", { XX } },
4082 { "(bad)", { XX } },
4083 { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
4084 { "(bad)", { XX } },
4085 },
4086
4087 /* PREFIX_VEX_C5 */
4088 {
4089 { "(bad)", { XX } },
4090 { "(bad)", { XX } },
4091 { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
4092 { "(bad)", { XX } },
4093 },
4094
4095 /* PREFIX_VEX_D0 */
4096 {
4097 { "(bad)", { XX } },
4098 { "(bad)", { XX } },
9e30b8e0
L		 4099 { VEX_W_TABLE (VEX_W_D0_P_2) },
4100 { VEX_W_TABLE (VEX_W_D0_P_3) },
c0f3af97
L		 4101 },
4102
4103 /* PREFIX_VEX_D1 */
4104 {
4105 { "(bad)", { XX } },
4106 { "(bad)", { XX } },
4107 { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
4108 { "(bad)", { XX } },
4109 },
4110
4111 /* PREFIX_VEX_D2 */
4112 {
4113 { "(bad)", { XX } },
4114 { "(bad)", { XX } },
4115 { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
4116 { "(bad)", { XX } },
4117 },
4118
4119 /* PREFIX_VEX_D3 */
4120 {
4121 { "(bad)", { XX } },
4122 { "(bad)", { XX } },
4123 { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
4124 { "(bad)", { XX } },
4125 },
4126
4127 /* PREFIX_VEX_D4 */
4128 {
4129 { "(bad)", { XX } },
4130 { "(bad)", { XX } },
4131 { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
4132 { "(bad)", { XX } },
4133 },
4134
4135 /* PREFIX_VEX_D5 */
4136 {
4137 { "(bad)", { XX } },
4138 { "(bad)", { XX } },
4139 { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
4140 { "(bad)", { XX } },
4141 },
4142
4143 /* PREFIX_VEX_D6 */
4144 {
4145 { "(bad)", { XX } },
4146 { "(bad)", { XX } },
4147 { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
4148 { "(bad)", { XX } },
4149 },
4150
4151 /* PREFIX_VEX_D7 */
4152 {
4153 { "(bad)", { XX } },
4154 { "(bad)", { XX } },
4155 { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
4156 { "(bad)", { XX } },
4157 },
4158
4159 /* PREFIX_VEX_D8 */
4160 {
4161 { "(bad)", { XX } },
4162 { "(bad)", { XX } },
4163 { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
4164 { "(bad)", { XX } },
4165 },
4166
4167 /* PREFIX_VEX_D9 */
4168 {
4169 { "(bad)", { XX } },
4170 { "(bad)", { XX } },
4171 { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
4172 { "(bad)", { XX } },
4173 },
4174
4175 /* PREFIX_VEX_DA */
4176 {
4177 { "(bad)", { XX } },
4178 { "(bad)", { XX } },
4179 { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
4180 { "(bad)", { XX } },
4181 },
4182
4183 /* PREFIX_VEX_DB */
4184 {
4185 { "(bad)", { XX } },
4186 { "(bad)", { XX } },
4187 { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
4188 { "(bad)", { XX } },
4189 },
4190
4191 /* PREFIX_VEX_DC */
4192 {
4193 { "(bad)", { XX } },
4194 { "(bad)", { XX } },
4195 { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
4196 { "(bad)", { XX } },
4197 },
4198
4199 /* PREFIX_VEX_DD */
4200 {
4201 { "(bad)", { XX } },
4202 { "(bad)", { XX } },
4203 { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
4204 { "(bad)", { XX } },
4205 },
4206
4207 /* PREFIX_VEX_DE */
4208 {
4209 { "(bad)", { XX } },
4210 { "(bad)", { XX } },
4211 { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
4212 { "(bad)", { XX } },
4213 },
4214
4215 /* PREFIX_VEX_DF */
4216 {
4217 { "(bad)", { XX } },
4218 { "(bad)", { XX } },
4219 { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
4220 { "(bad)", { XX } },
4221 },
4222
4223 /* PREFIX_VEX_E0 */
4224 {
4225 { "(bad)", { XX } },
4226 { "(bad)", { XX } },
4227 { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
4228 { "(bad)", { XX } },
4229 },
4230
4231 /* PREFIX_VEX_E1 */
4232 {
4233 { "(bad)", { XX } },
4234 { "(bad)", { XX } },
4235 { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
4236 { "(bad)", { XX } },
4237 },
4238
4239 /* PREFIX_VEX_E2 */
4240 {
4241 { "(bad)", { XX } },
4242 { "(bad)", { XX } },
4243 { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
4244 { "(bad)", { XX } },
4245 },
4246
4247 /* PREFIX_VEX_E3 */
4248 {
4249 { "(bad)", { XX } },
4250 { "(bad)", { XX } },
4251 { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
4252 { "(bad)", { XX } },
4253 },
4254
4255 /* PREFIX_VEX_E4 */
4256 {
4257 { "(bad)", { XX } },
4258 { "(bad)", { XX } },
4259 { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
4260 { "(bad)", { XX } },
4261 },
4262
4263 /* PREFIX_VEX_E5 */
4264 {
4265 { "(bad)", { XX } },
4266 { "(bad)", { XX } },
4267 { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
4268 { "(bad)", { XX } },
4269 },
4270
4271 /* PREFIX_VEX_E6 */
4272 {
4273 { "(bad)", { XX } },
9e30b8e0
L		 4274 { VEX_W_TABLE (VEX_W_E6_P_1) },
4275 { VEX_W_TABLE (VEX_W_E6_P_2) },
4276 { VEX_W_TABLE (VEX_W_E6_P_3) },
c0f3af97
L		 4277 },
4278
4279 /* PREFIX_VEX_E7 */
4280 {
4281 { "(bad)", { XX } },
4282 { "(bad)", { XX } },
4283 { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
4284 { "(bad)", { XX } },
4285 },
4286
4287 /* PREFIX_VEX_E8 */
4288 {
4289 { "(bad)", { XX } },
4290 { "(bad)", { XX } },
4291 { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
4292 { "(bad)", { XX } },
4293 },
4294
4295 /* PREFIX_VEX_E9 */
4296 {
4297 { "(bad)", { XX } },
4298 { "(bad)", { XX } },
4299 { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
4300 { "(bad)", { XX } },
4301 },
4302
4303 /* PREFIX_VEX_EA */
4304 {
4305 { "(bad)", { XX } },
4306 { "(bad)", { XX } },
4307 { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
4308 { "(bad)", { XX } },
4309 },
4310
4311 /* PREFIX_VEX_EB */
4312 {
4313 { "(bad)", { XX } },
4314 { "(bad)", { XX } },
4315 { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
4316 { "(bad)", { XX } },
4317 },
4318
4319 /* PREFIX_VEX_EC */
4320 {
4321 { "(bad)", { XX } },
4322 { "(bad)", { XX } },
4323 { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
4324 { "(bad)", { XX } },
4325 },
4326
4327 /* PREFIX_VEX_ED */
4328 {
4329 { "(bad)", { XX } },
4330 { "(bad)", { XX } },
4331 { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4332 { "(bad)", { XX } },
4333 },
4334
4335 /* PREFIX_VEX_EE */
4336 {
4337 { "(bad)", { XX } },
4338 { "(bad)", { XX } },
4339 { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4340 { "(bad)", { XX } },
4341 },
4342
4343 /* PREFIX_VEX_EF */
4344 {
4345 { "(bad)", { XX } },
4346 { "(bad)", { XX } },
4347 { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4348 { "(bad)", { XX } },
4349 },
4350
4351 /* PREFIX_VEX_F0 */
4352 {
4353 { "(bad)", { XX } },
4354 { "(bad)", { XX } },
4355 { "(bad)", { XX } },
4356 { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4357 },
4358
4359 /* PREFIX_VEX_F1 */
4360 {
4361 { "(bad)", { XX } },
4362 { "(bad)", { XX } },
4363 { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4364 { "(bad)", { XX } },
4365 },
4366
4367 /* PREFIX_VEX_F2 */
4368 {
4369 { "(bad)", { XX } },
4370 { "(bad)", { XX } },
4371 { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4372 { "(bad)", { XX } },
4373 },
4374
4375 /* PREFIX_VEX_F3 */
4376 {
4377 { "(bad)", { XX } },
4378 { "(bad)", { XX } },
4379 { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4380 { "(bad)", { XX } },
4381 },
4382
4383 /* PREFIX_VEX_F4 */
4384 {
4385 { "(bad)", { XX } },
4386 { "(bad)", { XX } },
4387 { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4388 { "(bad)", { XX } },
4389 },
4390
4391 /* PREFIX_VEX_F5 */
4392 {
4393 { "(bad)", { XX } },
4394 { "(bad)", { XX } },
4395 { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4396 { "(bad)", { XX } },
4397 },
4398
4399 /* PREFIX_VEX_F6 */
4400 {
4401 { "(bad)", { XX } },
4402 { "(bad)", { XX } },
4403 { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4404 { "(bad)", { XX } },
4405 },
4406
4407 /* PREFIX_VEX_F7 */
4408 {
4409 { "(bad)", { XX } },
4410 { "(bad)", { XX } },
4411 { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4412 { "(bad)", { XX } },
4413 },
4414
4415 /* PREFIX_VEX_F8 */
4416 {
4417 { "(bad)", { XX } },
4418 { "(bad)", { XX } },
4419 { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4420 { "(bad)", { XX } },
4421 },
4422
4423 /* PREFIX_VEX_F9 */
4424 {
4425 { "(bad)", { XX } },
4426 { "(bad)", { XX } },
4427 { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4428 { "(bad)", { XX } },
4429 },
4430
4431 /* PREFIX_VEX_FA */
4432 {
4433 { "(bad)", { XX } },
4434 { "(bad)", { XX } },
4435 { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4436 { "(bad)", { XX } },
4437 },
4438
4439 /* PREFIX_VEX_FB */
4440 {
4441 { "(bad)", { XX } },
4442 { "(bad)", { XX } },
4443 { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4444 { "(bad)", { XX } },
4445 },
4446
4447 /* PREFIX_VEX_FC */
4448 {
4449 { "(bad)", { XX } },
4450 { "(bad)", { XX } },
4451 { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4452 { "(bad)", { XX } },
4453 },
4454
4455 /* PREFIX_VEX_FD */
4456 {
4457 { "(bad)", { XX } },
4458 { "(bad)", { XX } },
4459 { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4460 { "(bad)", { XX } },
4461 },
4462
4463 /* PREFIX_VEX_FE */
4464 {
4465 { "(bad)", { XX } },
4466 { "(bad)", { XX } },
4467 { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4468 { "(bad)", { XX } },
4469 },
4470
4471 /* PREFIX_VEX_3800 */
4472 {
4473 { "(bad)", { XX } },
4474 { "(bad)", { XX } },
4475 { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4476 { "(bad)", { XX } },
4477 },
4478
4479 /* PREFIX_VEX_3801 */
4480 {
4481 { "(bad)", { XX } },
4482 { "(bad)", { XX } },
4483 { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4484 { "(bad)", { XX } },
4485 },
4486
4487 /* PREFIX_VEX_3802 */
4488 {
4489 { "(bad)", { XX } },
4490 { "(bad)", { XX } },
4491 { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4492 { "(bad)", { XX } },
4493 },
4494
4495 /* PREFIX_VEX_3803 */
4496 {
4497 { "(bad)", { XX } },
4498 { "(bad)", { XX } },
4499 { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4500 { "(bad)", { XX } },
4501 },
4502
4503 /* PREFIX_VEX_3804 */
4504 {
4505 { "(bad)", { XX } },
4506 { "(bad)", { XX } },
4507 { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4508 { "(bad)", { XX } },
4509 },
4510
4511 /* PREFIX_VEX_3805 */
4512 {
4513 { "(bad)", { XX } },
4514 { "(bad)", { XX } },
4515 { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4516 { "(bad)", { XX } },
4517 },
4518
4519 /* PREFIX_VEX_3806 */
4520 {
4521 { "(bad)", { XX } },
4522 { "(bad)", { XX } },
4523 { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4524 { "(bad)", { XX } },
4525 },
4526
4527 /* PREFIX_VEX_3807 */
4528 {
4529 { "(bad)", { XX } },
4530 { "(bad)", { XX } },
4531 { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4532 { "(bad)", { XX } },
4533 },
4534
4535 /* PREFIX_VEX_3808 */
4536 {
4537 { "(bad)", { XX } },
4538 { "(bad)", { XX } },
4539 { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4540 { "(bad)", { XX } },
4541 },
4542
4543 /* PREFIX_VEX_3809 */
4544 {
4545 { "(bad)", { XX } },
4546 { "(bad)", { XX } },
4547 { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4548 { "(bad)", { XX } },
4549 },
4550
4551 /* PREFIX_VEX_380A */
4552 {
4553 { "(bad)", { XX } },
4554 { "(bad)", { XX } },
4555 { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4556 { "(bad)", { XX } },
4557 },
4558
4559 /* PREFIX_VEX_380B */
4560 {
4561 { "(bad)", { XX } },
4562 { "(bad)", { XX } },
4563 { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4564 { "(bad)", { XX } },
4565 },
4566
4567 /* PREFIX_VEX_380C */
4568 {
4569 { "(bad)", { XX } },
4570 { "(bad)", { XX } },
9e30b8e0 4571 { VEX_W_TABLE (VEX_W_380C_P_2) },
c0f3af97
L		 4572 { "(bad)", { XX } },
4573 },
4574
4575 /* PREFIX_VEX_380D */
4576 {
4577 { "(bad)", { XX } },
4578 { "(bad)", { XX } },
9e30b8e0 4579 { VEX_W_TABLE (VEX_W_380D_P_2) },
c0f3af97
L		 4580 { "(bad)", { XX } },
4581 },
4582
4583 /* PREFIX_VEX_380E */
4584 {
4585 { "(bad)", { XX } },
4586 { "(bad)", { XX } },
9e30b8e0 4587 { VEX_W_TABLE (VEX_W_380E_P_2) },
c0f3af97
L		 4588 { "(bad)", { XX } },
4589 },
4590
4591 /* PREFIX_VEX_380F */
4592 {
4593 { "(bad)", { XX } },
4594 { "(bad)", { XX } },
9e30b8e0 4595 { VEX_W_TABLE (VEX_W_380F_P_2) },
c0f3af97
L		 4596 { "(bad)", { XX } },
4597 },
4598
4599 /* PREFIX_VEX_3817 */
4600 {
4601 { "(bad)", { XX } },
4602 { "(bad)", { XX } },
9e30b8e0 4603 { VEX_W_TABLE (VEX_W_3817_P_2) },
c0f3af97
L		 4604 { "(bad)", { XX } },
4605 },
4606
4607 /* PREFIX_VEX_3818 */
4608 {
4609 { "(bad)", { XX } },
4610 { "(bad)", { XX } },
4611 { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4612 { "(bad)", { XX } },
4613 },
4614
4615 /* PREFIX_VEX_3819 */
4616 {
4617 { "(bad)", { XX } },
4618 { "(bad)", { XX } },
4619 { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4620 { "(bad)", { XX } },
4621 },
4622
4623 /* PREFIX_VEX_381A */
4624 {
4625 { "(bad)", { XX } },
4626 { "(bad)", { XX } },
4627 { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4628 { "(bad)", { XX } },
4629 },
4630
4631 /* PREFIX_VEX_381C */
4632 {
4633 { "(bad)", { XX } },
4634 { "(bad)", { XX } },
4635 { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4636 { "(bad)", { XX } },
4637 },
4638
4639 /* PREFIX_VEX_381D */
4640 {
4641 { "(bad)", { XX } },
4642 { "(bad)", { XX } },
4643 { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4644 { "(bad)", { XX } },
4645 },
4646
4647 /* PREFIX_VEX_381E */
4648 {
4649 { "(bad)", { XX } },
4650 { "(bad)", { XX } },
4651 { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4652 { "(bad)", { XX } },
4653 },
4654
4655 /* PREFIX_VEX_3820 */
4656 {
4657 { "(bad)", { XX } },
4658 { "(bad)", { XX } },
4659 { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4660 { "(bad)", { XX } },
4661 },
4662
4663 /* PREFIX_VEX_3821 */
4664 {
4665 { "(bad)", { XX } },
4666 { "(bad)", { XX } },
4667 { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4668 { "(bad)", { XX } },
4669 },
4670
4671 /* PREFIX_VEX_3822 */
4672 {
4673 { "(bad)", { XX } },
4674 { "(bad)", { XX } },
4675 { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4676 { "(bad)", { XX } },
4677 },
4678
4679 /* PREFIX_VEX_3823 */
4680 {
4681 { "(bad)", { XX } },
4682 { "(bad)", { XX } },
4683 { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4684 { "(bad)", { XX } },
4685 },
4686
4687 /* PREFIX_VEX_3824 */
4688 {
4689 { "(bad)", { XX } },
4690 { "(bad)", { XX } },
4691 { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4692 { "(bad)", { XX } },
4693 },
4694
4695 /* PREFIX_VEX_3825 */
4696 {
4697 { "(bad)", { XX } },
4698 { "(bad)", { XX } },
4699 { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4700 { "(bad)", { XX } },
4701 },
4702
4703 /* PREFIX_VEX_3828 */
4704 {
4705 { "(bad)", { XX } },
4706 { "(bad)", { XX } },
4707 { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4708 { "(bad)", { XX } },
4709 },
4710
4711 /* PREFIX_VEX_3829 */
4712 {
4713 { "(bad)", { XX } },
4714 { "(bad)", { XX } },
4715 { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4716 { "(bad)", { XX } },
4717 },
4718
4719 /* PREFIX_VEX_382A */
4720 {
4721 { "(bad)", { XX } },
4722 { "(bad)", { XX } },
4723 { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4724 { "(bad)", { XX } },
4725 },
4726
4727 /* PREFIX_VEX_382B */
4728 {
4729 { "(bad)", { XX } },
4730 { "(bad)", { XX } },
4731 { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4732 { "(bad)", { XX } },
4733 },
4734
4735 /* PREFIX_VEX_382C */
4736 {
4737 { "(bad)", { XX } },
4738 { "(bad)", { XX } },
4739 { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4740 { "(bad)", { XX } },
4741 },
4742
4743 /* PREFIX_VEX_382D */
4744 {
4745 { "(bad)", { XX } },
4746 { "(bad)", { XX } },
4747 { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4748 { "(bad)", { XX } },
4749 },
4750
4751 /* PREFIX_VEX_382E */
4752 {
4753 { "(bad)", { XX } },
4754 { "(bad)", { XX } },
4755 { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4756 { "(bad)", { XX } },
4757 },
4758
4759 /* PREFIX_VEX_382F */
4760 {
4761 { "(bad)", { XX } },
4762 { "(bad)", { XX } },
4763 { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4764 { "(bad)", { XX } },
4765 },
4766
4767 /* PREFIX_VEX_3830 */
4768 {
4769 { "(bad)", { XX } },
4770 { "(bad)", { XX } },
4771 { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4772 { "(bad)", { XX } },
4773 },
4774
4775 /* PREFIX_VEX_3831 */
4776 {
4777 { "(bad)", { XX } },
4778 { "(bad)", { XX } },
4779 { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4780 { "(bad)", { XX } },
4781 },
4782
4783 /* PREFIX_VEX_3832 */
4784 {
4785 { "(bad)", { XX } },
4786 { "(bad)", { XX } },
4787 { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4788 { "(bad)", { XX } },
4789 },
4790
4791 /* PREFIX_VEX_3833 */
4792 {
4793 { "(bad)", { XX } },
4794 { "(bad)", { XX } },
4795 { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4796 { "(bad)", { XX } },
4797 },
4798
4799 /* PREFIX_VEX_3834 */
4800 {
4801 { "(bad)", { XX } },
4802 { "(bad)", { XX } },
4803 { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4804 { "(bad)", { XX } },
4805 },
4806
4807 /* PREFIX_VEX_3835 */
4808 {
4809 { "(bad)", { XX } },
4810 { "(bad)", { XX } },
4811 { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4812 { "(bad)", { XX } },
4813 },
4814
4815 /* PREFIX_VEX_3837 */
4816 {
4817 { "(bad)", { XX } },
4818 { "(bad)", { XX } },
4819 { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4820 { "(bad)", { XX } },
4821 },
4822
4823 /* PREFIX_VEX_3838 */
4824 {
4825 { "(bad)", { XX } },
4826 { "(bad)", { XX } },
4827 { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4828 { "(bad)", { XX } },
4829 },
4830
4831 /* PREFIX_VEX_3839 */
4832 {
4833 { "(bad)", { XX } },
4834 { "(bad)", { XX } },
4835 { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4836 { "(bad)", { XX } },
4837 },
4838
4839 /* PREFIX_VEX_383A */
4840 {
4841 { "(bad)", { XX } },
4842 { "(bad)", { XX } },
4843 { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4844 { "(bad)", { XX } },
4845 },
4846
4847 /* PREFIX_VEX_383B */
4848 {
4849 { "(bad)", { XX } },
4850 { "(bad)", { XX } },
4851 { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4852 { "(bad)", { XX } },
4853 },
4854
4855 /* PREFIX_VEX_383C */
4856 {
4857 { "(bad)", { XX } },
4858 { "(bad)", { XX } },
4859 { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4860 { "(bad)", { XX } },
4861 },
4862
4863 /* PREFIX_VEX_383D */
4864 {
4865 { "(bad)", { XX } },
4866 { "(bad)", { XX } },
4867 { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4868 { "(bad)", { XX } },
4869 },
4870
4871 /* PREFIX_VEX_383E */
4872 {
4873 { "(bad)", { XX } },
4874 { "(bad)", { XX } },
4875 { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4876 { "(bad)", { XX } },
4877 },
4878
4879 /* PREFIX_VEX_383F */
4880 {
4881 { "(bad)", { XX } },
4882 { "(bad)", { XX } },
4883 { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4884 { "(bad)", { XX } },
4885 },
4886
4887 /* PREFIX_VEX_3840 */
4888 {
4889 { "(bad)", { XX } },
4890 { "(bad)", { XX } },
4891 { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4892 { "(bad)", { XX } },
4893 },
4894
4895 /* PREFIX_VEX_3841 */
4896 {
4897 { "(bad)", { XX } },
4898 { "(bad)", { XX } },
4899 { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4900 { "(bad)", { XX } },
4901 },
4902
0bfee649 4903 /* PREFIX_VEX_3896 */
a5ff0eb2
L		 4904 {
4905 { "(bad)", { XX } },
4906 { "(bad)", { XX } },
0bfee649 4907 { "vfmaddsub132p%XW", { XM, Vex, EXx } },
a5ff0eb2
L		 4908 { "(bad)", { XX } },
4909 },
4910
0bfee649 4911 /* PREFIX_VEX_3897 */
a5ff0eb2
L		 4912 {
4913 { "(bad)", { XX } },
4914 { "(bad)", { XX } },
0bfee649 4915 { "vfmsubadd132p%XW", { XM, Vex, EXx } },
a5ff0eb2
L		 4916 { "(bad)", { XX } },
4917 },
4918
0bfee649 4919 /* PREFIX_VEX_3898 */
a5ff0eb2
L		 4920 {
4921 { "(bad)", { XX } },
4922 { "(bad)", { XX } },
0bfee649 4923 { "vfmadd132p%XW", { XM, Vex, EXx } },
a5ff0eb2
L		 4924 { "(bad)", { XX } },
4925 },
4926
0bfee649 4927 /* PREFIX_VEX_3899 */
a5ff0eb2
L		 4928 {
4929 { "(bad)", { XX } },
4930 { "(bad)", { XX } },
0bfee649 4931 { "vfmadd132s%XW", { XM, Vex, EXVexWdq } },
a5ff0eb2
L		 4932 { "(bad)", { XX } },
4933 },
4934
0bfee649 4935 /* PREFIX_VEX_389A */
a5ff0eb2
L		 4936 {
4937 { "(bad)", { XX } },
4938 { "(bad)", { XX } },
0bfee649 4939 { "vfmsub132p%XW", { XM, Vex, EXx } },
a5ff0eb2
L		 4940 { "(bad)", { XX } },
4941 },
4942
0bfee649 4943 /* PREFIX_VEX_389B */
c0f3af97
L		 4944 {
4945 { "(bad)", { XX } },
4946 { "(bad)", { XX } },
0bfee649 4947 { "vfmsub132s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4948 { "(bad)", { XX } },
4949 },
4950
0bfee649 4951 /* PREFIX_VEX_389C */
c0f3af97
L		 4952 {
4953 { "(bad)", { XX } },
4954 { "(bad)", { XX } },
0bfee649 4955 { "vfnmadd132p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4956 { "(bad)", { XX } },
4957 },
4958
0bfee649 4959 /* PREFIX_VEX_389D */
c0f3af97
L		 4960 {
4961 { "(bad)", { XX } },
4962 { "(bad)", { XX } },
0bfee649 4963 { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4964 { "(bad)", { XX } },
4965 },
4966
0bfee649 4967 /* PREFIX_VEX_389E */
c0f3af97
L		 4968 {
4969 { "(bad)", { XX } },
4970 { "(bad)", { XX } },
0bfee649 4971 { "vfnmsub132p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4972 { "(bad)", { XX } },
4973 },
4974
0bfee649 4975 /* PREFIX_VEX_389F */
c0f3af97
L		 4976 {
4977 { "(bad)", { XX } },
4978 { "(bad)", { XX } },
0bfee649 4979 { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4980 { "(bad)", { XX } },
4981 },
4982
0bfee649 4983 /* PREFIX_VEX_38A6 */
c0f3af97
L		 4984 {
4985 { "(bad)", { XX } },
4986 { "(bad)", { XX } },
0bfee649 4987 { "vfmaddsub213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4988 { "(bad)", { XX } },
4989 },
4990
0bfee649 4991 /* PREFIX_VEX_38A7 */
c0f3af97
L		 4992 {
4993 { "(bad)", { XX } },
4994 { "(bad)", { XX } },
0bfee649 4995 { "vfmsubadd213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4996 { "(bad)", { XX } },
4997 },
4998
0bfee649 4999 /* PREFIX_VEX_38A8 */
c0f3af97
L		 5000 {
5001 { "(bad)", { XX } },
5002 { "(bad)", { XX } },
0bfee649 5003 { "vfmadd213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 5004 { "(bad)", { XX } },
5005 },
5006
0bfee649 5007 /* PREFIX_VEX_38A9 */
c0f3af97
L		 5008 {
5009 { "(bad)", { XX } },
5010 { "(bad)", { XX } },
0bfee649 5011 { "vfmadd213s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 5012 { "(bad)", { XX } },
5013 },
5014
0bfee649 5015 /* PREFIX_VEX_38AA */
c0f3af97
L		 5016 {
5017 { "(bad)", { XX } },
5018 { "(bad)", { XX } },
0bfee649 5019 { "vfmsub213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 5020 { "(bad)", { XX } },
5021 },
5022
0bfee649 5023 /* PREFIX_VEX_38AB */
c0f3af97
L		 5024 {
5025 { "(bad)", { XX } },
5026 { "(bad)", { XX } },
0bfee649 5027 { "vfmsub213s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 5028 { "(bad)", { XX } },
5029 },
5030
0bfee649 5031 /* PREFIX_VEX_38AC */
c0f3af97
L		 5032 {
5033 { "(bad)", { XX } },
5034 { "(bad)", { XX } },
0bfee649 5035 { "vfnmadd213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 5036 { "(bad)", { XX } },
5037 },
5038
0bfee649 5039 /* PREFIX_VEX_38AD */
c0f3af97
L		 5040 {
5041 { "(bad)", { XX } },
5042 { "(bad)", { XX } },
0bfee649 5043 { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 5044 { "(bad)", { XX } },
5045 },
5046
0bfee649 5047 /* PREFIX_VEX_38AE */
c0f3af97
L		 5048 {
5049 { "(bad)", { XX } },
5050 { "(bad)", { XX } },
0bfee649 5051 { "vfnmsub213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 5052 { "(bad)", { XX } },
5053 },
5054
0bfee649 5055 /* PREFIX_VEX_38AF */
c0f3af97
L		 5056 {
5057 { "(bad)", { XX } },
5058 { "(bad)", { XX } },
0bfee649 5059 { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 5060 { "(bad)", { XX } },
5061 },
5062
0bfee649 5063 /* PREFIX_VEX_38B6 */
c0f3af97
L		 5064 {
5065 { "(bad)", { XX } },
5066 { "(bad)", { XX } },
0bfee649 5067 { "vfmaddsub231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 5068 { "(bad)", { XX } },
5069 },
5070
0bfee649 5071 /* PREFIX_VEX_38B7 */
c0f3af97
L		 5072 {
5073 { "(bad)", { XX } },
5074 { "(bad)", { XX } },
0bfee649 5075 { "vfmsubadd231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 5076 { "(bad)", { XX } },
5077 },
5078
0bfee649 5079 /* PREFIX_VEX_38B8 */
c0f3af97
L		 5080 {
5081 { "(bad)", { XX } },
5082 { "(bad)", { XX } },
0bfee649 5083 { "vfmadd231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 5084 { "(bad)", { XX } },
5085 },
5086
0bfee649 5087 /* PREFIX_VEX_38B9 */
c0f3af97
L		 5088 {
5089 { "(bad)", { XX } },
5090 { "(bad)", { XX } },
0bfee649 5091 { "vfmadd231s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 5092 { "(bad)", { XX } },
5093 },
5094
0bfee649 5095 /* PREFIX_VEX_38BA */
c0f3af97
L		 5096 {
5097 { "(bad)", { XX } },
5098 { "(bad)", { XX } },
0bfee649 5099 { "vfmsub231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 5100 { "(bad)", { XX } },
5101 },
5102
0bfee649 5103 /* PREFIX_VEX_38BB */
c0f3af97
L		 5104 {
5105 { "(bad)", { XX } },
5106 { "(bad)", { XX } },
0bfee649 5107 { "vfmsub231s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 5108 { "(bad)", { XX } },
5109 },
5110
0bfee649 5111 /* PREFIX_VEX_38BC */
c0f3af97
L		 5112 {
5113 { "(bad)", { XX } },
5114 { "(bad)", { XX } },
0bfee649 5115 { "vfnmadd231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 5116 { "(bad)", { XX } },
5117 },
5118
0bfee649 5119 /* PREFIX_VEX_38BD */
c0f3af97
L		 5120 {
5121 { "(bad)", { XX } },
5122 { "(bad)", { XX } },
0bfee649 5123 { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 5124 { "(bad)", { XX } },
5125 },
5126
0bfee649 5127 /* PREFIX_VEX_38BE */
c0f3af97
L		 5128 {
5129 { "(bad)", { XX } },
5130 { "(bad)", { XX } },
0bfee649 5131 { "vfnmsub231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 5132 { "(bad)", { XX } },
5133 },
5134
0bfee649 5135 /* PREFIX_VEX_38BF */
c0f3af97
L		 5136 {
5137 { "(bad)", { XX } },
5138 { "(bad)", { XX } },
0bfee649 5139 { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 5140 { "(bad)", { XX } },
5141 },
5142
0bfee649 5143 /* PREFIX_VEX_38DB */
c0f3af97
L		 5144 {
5145 { "(bad)", { XX } },
5146 { "(bad)", { XX } },
0bfee649 5147 { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
c0f3af97
L		 5148 { "(bad)", { XX } },
5149 },
5150
0bfee649 5151 /* PREFIX_VEX_38DC */
c0f3af97
L		 5152 {
5153 { "(bad)", { XX } },
5154 { "(bad)", { XX } },
0bfee649 5155 { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
c0f3af97
L		 5156 { "(bad)", { XX } },
5157 },
5158
0bfee649 5159 /* PREFIX_VEX_38DD */
c0f3af97
L		 5160 {
5161 { "(bad)", { XX } },
5162 { "(bad)", { XX } },
0bfee649 5163 { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
c0f3af97
L		 5164 { "(bad)", { XX } },
5165 },
5166
0bfee649 5167 /* PREFIX_VEX_38DE */
c0f3af97
L		 5168 {
5169 { "(bad)", { XX } },
5170 { "(bad)", { XX } },
0bfee649 5171 { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
c0f3af97
L		 5172 { "(bad)", { XX } },
5173 },
5174
0bfee649 5175 /* PREFIX_VEX_38DF */
c0f3af97
L		 5176 {
5177 { "(bad)", { XX } },
5178 { "(bad)", { XX } },
0bfee649 5179 { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
c0f3af97
L		 5180 { "(bad)", { XX } },
5181 },
5182
0bfee649 5183 /* PREFIX_VEX_3A04 */
c0f3af97
L		 5184 {
5185 { "(bad)", { XX } },
5186 { "(bad)", { XX } },
9e30b8e0 5187 { VEX_W_TABLE (VEX_W_3A04_P_2) },
c0f3af97
L		 5188 { "(bad)", { XX } },
5189 },
5190
0bfee649 5191 /* PREFIX_VEX_3A05 */
c0f3af97
L		 5192 {
5193 { "(bad)", { XX } },
5194 { "(bad)", { XX } },
9e30b8e0 5195 { VEX_W_TABLE (VEX_W_3A05_P_2) },
c0f3af97
L		 5196 { "(bad)", { XX } },
5197 },
5198
0bfee649 5199 /* PREFIX_VEX_3A06 */
c0f3af97
L		 5200 {
5201 { "(bad)", { XX } },
5202 { "(bad)", { XX } },
0bfee649 5203 { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
c0f3af97
L		 5204 { "(bad)", { XX } },
5205 },
5206
0bfee649 5207 /* PREFIX_VEX_3A08 */
c0f3af97
L		 5208 {
5209 { "(bad)", { XX } },
5210 { "(bad)", { XX } },
9e30b8e0 5211 { VEX_W_TABLE (VEX_W_3A08_P_2) },
c0f3af97
L		 5212 { "(bad)", { XX } },
5213 },
5214
0bfee649 5215 /* PREFIX_VEX_3A09 */
c0f3af97
L		 5216 {
5217 { "(bad)", { XX } },
5218 { "(bad)", { XX } },
9e30b8e0 5219 { VEX_W_TABLE (VEX_W_3A09_P_2) },
c0f3af97
L		 5220 { "(bad)", { XX } },
5221 },
5222
0bfee649 5223 /* PREFIX_VEX_3A0A */
c0f3af97
L		 5224 {
5225 { "(bad)", { XX } },
5226 { "(bad)", { XX } },
0bfee649
L		 5227 { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
5228 { "(bad)", { XX } },
5229 },
5230
5231 /* PREFIX_VEX_3A0B */
5232 {
5233 { "(bad)", { XX } },
5234 { "(bad)", { XX } },
5235 { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
5236 { "(bad)", { XX } },
5237 },
5238
5239 /* PREFIX_VEX_3A0C */
5240 {
5241 { "(bad)", { XX } },
5242 { "(bad)", { XX } },
9e30b8e0 5243 { VEX_W_TABLE (VEX_W_3A0C_P_2) },
0bfee649
L		 5244 { "(bad)", { XX } },
5245 },
5246
5247 /* PREFIX_VEX_3A0D */
5248 {
5249 { "(bad)", { XX } },
5250 { "(bad)", { XX } },
9e30b8e0 5251 { VEX_W_TABLE (VEX_W_3A0D_P_2) },
c0f3af97
L		 5252 { "(bad)", { XX } },
5253 },
5254
0bfee649
L		 5255 /* PREFIX_VEX_3A0E */
5256 {
5257 { "(bad)", { XX } },
5258 { "(bad)", { XX } },
5259 { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
5260 { "(bad)", { XX } },
5261 },
5262
5263 /* PREFIX_VEX_3A0F */
5264 {
5265 { "(bad)", { XX } },
5266 { "(bad)", { XX } },
5267 { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
5268 { "(bad)", { XX } },
5269 },
5270
5271 /* PREFIX_VEX_3A14 */
5272 {
5273 { "(bad)", { XX } },
5274 { "(bad)", { XX } },
5275 { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
5276 { "(bad)", { XX } },
5277 },
5278
5279 /* PREFIX_VEX_3A15 */
5280 {
5281 { "(bad)", { XX } },
5282 { "(bad)", { XX } },
5283 { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
5284 { "(bad)", { XX } },
5285 },
5286
5287 /* PREFIX_VEX_3A16 */
c0f3af97
L		 5288 {
5289 { "(bad)", { XX } },
5290 { "(bad)", { XX } },
0bfee649 5291 { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
c0f3af97
L		 5292 { "(bad)", { XX } },
5293 },
5294
0bfee649 5295 /* PREFIX_VEX_3A17 */
c0f3af97
L		 5296 {
5297 { "(bad)", { XX } },
5298 { "(bad)", { XX } },
0bfee649 5299 { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
c0f3af97
L		 5300 { "(bad)", { XX } },
5301 },
5302
0bfee649 5303 /* PREFIX_VEX_3A18 */
c0f3af97
L		 5304 {
5305 { "(bad)", { XX } },
5306 { "(bad)", { XX } },
0bfee649 5307 { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
c0f3af97
L		 5308 { "(bad)", { XX } },
5309 },
5310
0bfee649 5311 /* PREFIX_VEX_3A19 */
c0f3af97
L		 5312 {
5313 { "(bad)", { XX } },
5314 { "(bad)", { XX } },
0bfee649 5315 { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
c0f3af97
L		 5316 { "(bad)", { XX } },
5317 },
5318
0bfee649 5319 /* PREFIX_VEX_3A20 */
c0f3af97
L		 5320 {
5321 { "(bad)", { XX } },
5322 { "(bad)", { XX } },
0bfee649 5323 { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
c0f3af97
L		 5324 { "(bad)", { XX } },
5325 },
5326
0bfee649 5327 /* PREFIX_VEX_3A21 */
c0f3af97
L		 5328 {
5329 { "(bad)", { XX } },
5330 { "(bad)", { XX } },
0bfee649 5331 { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
c0f3af97
L		 5332 { "(bad)", { XX } },
5333 },
5334
0bfee649
L		 5335 /* PREFIX_VEX_3A22 */
5336 {
5337 { "(bad)", { XX } },
5338 { "(bad)", { XX } },
5339 { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5340 { "(bad)", { XX } },
5341 },
5342
5343 /* PREFIX_VEX_3A40 */
c0f3af97
L		 5344 {
5345 { "(bad)", { XX } },
5346 { "(bad)", { XX } },
9e30b8e0 5347 { VEX_W_TABLE (VEX_W_3A40_P_2) },
c0f3af97
L		 5348 { "(bad)", { XX } },
5349 },
5350
0bfee649 5351 /* PREFIX_VEX_3A41 */
c0f3af97
L		 5352 {
5353 { "(bad)", { XX } },
5354 { "(bad)", { XX } },
0bfee649 5355 { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
c0f3af97
L		 5356 { "(bad)", { XX } },
5357 },
5358
0bfee649 5359 /* PREFIX_VEX_3A42 */
c0f3af97
L		 5360 {
5361 { "(bad)", { XX } },
5362 { "(bad)", { XX } },
0bfee649 5363 { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
c0f3af97
L		 5364 { "(bad)", { XX } },
5365 },
5366
ce2f5b3c
L		 5367 /* PREFIX_VEX_3A44 */
5368 {
5369 { "(bad)", { XX } },
5370 { "(bad)", { XX } },
5371 { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
5372 { "(bad)", { XX } },
5373 },
5374
0bfee649 5375 /* PREFIX_VEX_3A4A */
c0f3af97
L		 5376 {
5377 { "(bad)", { XX } },
5378 { "(bad)", { XX } },
9e30b8e0 5379 { VEX_W_TABLE (VEX_W_3A4A_P_2) },
c0f3af97
L		 5380 { "(bad)", { XX } },
5381 },
5382
0bfee649 5383 /* PREFIX_VEX_3A4B */
c0f3af97
L		 5384 {
5385 { "(bad)", { XX } },
5386 { "(bad)", { XX } },
9e30b8e0 5387 { VEX_W_TABLE (VEX_W_3A4B_P_2) },
c0f3af97
L		 5388 { "(bad)", { XX } },
5389 },
5390
0bfee649 5391 /* PREFIX_VEX_3A4C */
c0f3af97
L		 5392 {
5393 { "(bad)", { XX } },
5394 { "(bad)", { XX } },
0bfee649 5395 { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
c0f3af97
L		 5396 { "(bad)", { XX } },
5397 },
5398
922d8de8
DR		 5399 /* PREFIX_VEX_3A5C */
5400 {
5401 { "(bad)", { XX } },
5402 { "(bad)", { XX } },
206c2556 5403 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5404 { "(bad)", { XX } },
5405 },
5406
5407 /* PREFIX_VEX_3A5D */
5408 {
5409 { "(bad)", { XX } },
5410 { "(bad)", { XX } },
206c2556 5411 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5412 { "(bad)", { XX } },
5413 },
5414
5415 /* PREFIX_VEX_3A5E */
5416 {
5417 { "(bad)", { XX } },
5418 { "(bad)", { XX } },
206c2556 5419 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5420 { "(bad)", { XX } },
5421 },
5422
5423 /* PREFIX_VEX_3A5F */
5424 {
5425 { "(bad)", { XX } },
5426 { "(bad)", { XX } },
206c2556 5427 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5428 { "(bad)", { XX } },
5429 },
5430
0bfee649 5431 /* PREFIX_VEX_3A60 */
c0f3af97
L		 5432 {
5433 { "(bad)", { XX } },
5434 { "(bad)", { XX } },
0bfee649 5435 { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
c0f3af97
L		 5436 { "(bad)", { XX } },
5437 },
5438
0bfee649 5439 /* PREFIX_VEX_3A61 */
c0f3af97
L		 5440 {
5441 { "(bad)", { XX } },
5442 { "(bad)", { XX } },
0bfee649 5443 { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
c0f3af97
L		 5444 { "(bad)", { XX } },
5445 },
5446
0bfee649 5447 /* PREFIX_VEX_3A62 */
c0f3af97
L		 5448 {
5449 { "(bad)", { XX } },
5450 { "(bad)", { XX } },
0bfee649 5451 { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
c0f3af97
L		 5452 { "(bad)", { XX } },
5453 },
5454
0bfee649 5455 /* PREFIX_VEX_3A63 */
c0f3af97
L		 5456 {
5457 { "(bad)", { XX } },
5458 { "(bad)", { XX } },
0bfee649 5459 { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
c0f3af97
L		 5460 { "(bad)", { XX } },
5461 },
a5ff0eb2 5462
922d8de8
DR		 5463 /* PREFIX_VEX_3A68 */
5464 {
5465 { "(bad)", { XX } },
5466 { "(bad)", { XX } },
206c2556 5467 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5468 { "(bad)", { XX } },
5469 },
5470
5471 /* PREFIX_VEX_3A69 */
5472 {
5473 { "(bad)", { XX } },
5474 { "(bad)", { XX } },
206c2556 5475 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5476 { "(bad)", { XX } },
5477 },
5478
5479 /* PREFIX_VEX_3A6A */
5480 {
5481 { "(bad)", { XX } },
5482 { "(bad)", { XX } },
5483 { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
5484 { "(bad)", { XX } },
5485 },
5486
5487 /* PREFIX_VEX_3A6B */
5488 {
5489 { "(bad)", { XX } },
5490 { "(bad)", { XX } },
5491 { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
5492 { "(bad)", { XX } },
5493 },
5494
5495 /* PREFIX_VEX_3A6C */
5496 {
5497 { "(bad)", { XX } },
5498 { "(bad)", { XX } },
206c2556 5499 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5500 { "(bad)", { XX } },
5501 },
5502
5503 /* PREFIX_VEX_3A6D */
5504 {
5505 { "(bad)", { XX } },
5506 { "(bad)", { XX } },
206c2556 5507 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5508 { "(bad)", { XX } },
5509 },
5510
5511 /* PREFIX_VEX_3A6E */
5512 {
5513 { "(bad)", { XX } },
5514 { "(bad)", { XX } },
5515 { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
5516 { "(bad)", { XX } },
5517 },
5518
5519 /* PREFIX_VEX_3A6F */
5520 {
5521 { "(bad)", { XX } },
5522 { "(bad)", { XX } },
5523 { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
5524 { "(bad)", { XX } },
5525 },
5526
5527 /* PREFIX_VEX_3A78 */
5528 {
5529 { "(bad)", { XX } },
5530 { "(bad)", { XX } },
206c2556 5531 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5532 { "(bad)", { XX } },
5533 },
5534
5535 /* PREFIX_VEX_3A79 */
5536 {
5537 { "(bad)", { XX } },
5538 { "(bad)", { XX } },
206c2556 5539 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5540 { "(bad)", { XX } },
5541 },
5542
5543 /* PREFIX_VEX_3A7A */
5544 {
5545 { "(bad)", { XX } },
5546 { "(bad)", { XX } },
5547 { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
5548 { "(bad)", { XX } },
5549 },
5550
5551 /* PREFIX_VEX_3A7B */
5552 {
5553 { "(bad)", { XX } },
5554 { "(bad)", { XX } },
5555 { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
5556 { "(bad)", { XX } },
5557 },
5558
5559 /* PREFIX_VEX_3A7C */
5560 {
5561 { "(bad)", { XX } },
5562 { "(bad)", { XX } },
206c2556 5563 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5564 { "(bad)", { XX } },
5565 },
5566
5567 /* PREFIX_VEX_3A7D */
5568 {
5569 { "(bad)", { XX } },
5570 { "(bad)", { XX } },
206c2556 5571 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5572 { "(bad)", { XX } },
5573 },
5574
5575 /* PREFIX_VEX_3A7E */
5576 {
5577 { "(bad)", { XX } },
5578 { "(bad)", { XX } },
5579 { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5580 { "(bad)", { XX } },
5581 },
5582
5583 /* PREFIX_VEX_3A7F */
5584 {
5585 { "(bad)", { XX } },
5586 { "(bad)", { XX } },
5587 { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5588 { "(bad)", { XX } },
5589 },
5590
a5ff0eb2
L		 5591 /* PREFIX_VEX_3ADF */
5592 {
5593 { "(bad)", { XX } },
5594 { "(bad)", { XX } },
5595 { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5596 { "(bad)", { XX } },
5597 },
c0f3af97
L		 5598};
5599
5600static const struct dis386 x86_64_table[][2] = {
5601 /* X86_64_06 */
5602 {
5603 { "push{T|}", { es } },
5604 { "(bad)", { XX } },
5605 },
5606
5607 /* X86_64_07 */
5608 {
5609 { "pop{T|}", { es } },
5610 { "(bad)", { XX } },
5611 },
5612
5613 /* X86_64_0D */
5614 {
5615 { "push{T|}", { cs } },
5616 { "(bad)", { XX } },
5617 },
5618
5619 /* X86_64_16 */
5620 {
5621 { "push{T|}", { ss } },
5622 { "(bad)", { XX } },
5623 },
5624
5625 /* X86_64_17 */
5626 {
5627 { "pop{T|}", { ss } },
5628 { "(bad)", { XX } },
5629 },
5630
5631 /* X86_64_1E */
5632 {
5633 { "push{T|}", { ds } },
5634 { "(bad)", { XX } },
5635 },
5636
5637 /* X86_64_1F */
5638 {
5639 { "pop{T|}", { ds } },
5640 { "(bad)", { XX } },
5641 },
5642
5643 /* X86_64_27 */
5644 {
5645 { "daa", { XX } },
5646 { "(bad)", { XX } },
5647 },
5648
5649 /* X86_64_2F */
5650 {
5651 { "das", { XX } },
5652 { "(bad)", { XX } },
5653 },
5654
5655 /* X86_64_37 */
5656 {
5657 { "aaa", { XX } },
5658 { "(bad)", { XX } },
5659 },
5660
5661 /* X86_64_3F */
5662 {
5663 { "aas", { XX } },
5664 { "(bad)", { XX } },
5665 },
5666
5667 /* X86_64_60 */
5668 {
5669 { "pusha{P|}", { XX } },
5670 { "(bad)", { XX } },
5671 },
5672
5673 /* X86_64_61 */
5674 {
5675 { "popa{P|}", { XX } },
5676 { "(bad)", { XX } },
5677 },
5678
5679 /* X86_64_62 */
5680 {
5681 { MOD_TABLE (MOD_62_32BIT) },
5682 { "(bad)", { XX } },
5683 },
5684
5685 /* X86_64_63 */
5686 {
5687 { "arpl", { Ew, Gw } },
5688 { "movs{lq|xd}", { Gv, Ed } },
5689 },
5690
5691 /* X86_64_6D */
5692 {
5693 { "ins{R|}", { Yzr, indirDX } },
5694 { "ins{G|}", { Yzr, indirDX } },
5695 },
5696
5697 /* X86_64_6F */
5698 {
5699 { "outs{R|}", { indirDXr, Xz } },
5700 { "outs{G|}", { indirDXr, Xz } },
5701 },
5702
5703 /* X86_64_9A */
5704 {
5705 { "Jcall{T|}", { Ap } },
5706 { "(bad)", { XX } },
5707 },
5708
5709 /* X86_64_C4 */
5710 {
5711 { MOD_TABLE (MOD_C4_32BIT) },
5712 { VEX_C4_TABLE (VEX_0F) },
5713 },
5714
5715 /* X86_64_C5 */
5716 {
5717 { MOD_TABLE (MOD_C5_32BIT) },
5718 { VEX_C5_TABLE (VEX_0F) },
5719 },
5720
5721 /* X86_64_CE */
5722 {
5723 { "into", { XX } },
5724 { "(bad)", { XX } },
5725 },
5726
5727 /* X86_64_D4 */
5728 {
5729 { "aam", { sIb } },
5730 { "(bad)", { XX } },
5731 },
5732
5733 /* X86_64_D5 */
5734 {
5735 { "aad", { sIb } },
5736 { "(bad)", { XX } },
5737 },
5738
5739 /* X86_64_EA */
5740 {
5741 { "Jjmp{T|}", { Ap } },
5742 { "(bad)", { XX } },
5743 },
5744
5745 /* X86_64_0F01_REG_0 */
5746 {
5747 { "sgdt{Q|IQ}", { M } },
5748 { "sgdt", { M } },
5749 },
5750
5751 /* X86_64_0F01_REG_1 */
5752 {
5753 { "sidt{Q|IQ}", { M } },
5754 { "sidt", { M } },
5755 },
5756
5757 /* X86_64_0F01_REG_2 */
5758 {
5759 { "lgdt{Q|Q}", { M } },
5760 { "lgdt", { M } },
5761 },
5762
5763 /* X86_64_0F01_REG_3 */
5764 {
5765 { "lidt{Q|Q}", { M } },
5766 { "lidt", { M } },
5767 },
5768};
5769
5770static const struct dis386 three_byte_table[][256] = {
c1e679ec
DR		 5771
5772 /* THREE_BYTE_0F38 */
c0f3af97
L		 5773 {
5774 /* 00 */
c1e679ec
DR		 5775 { "pshufb", { MX, EM } },
5776 { "phaddw", { MX, EM } },
5777 { "phaddd", { MX, EM } },
5778 { "phaddsw", { MX, EM } },
5779 { "pmaddubsw", { MX, EM } },
5780 { "phsubw", { MX, EM } },
5781 { "phsubd", { MX, EM } },
5782 { "phsubsw", { MX, EM } },
c0f3af97 5783 /* 08 */
c1e679ec
DR		 5784 { "psignb", { MX, EM } },
5785 { "psignw", { MX, EM } },
5786 { "psignd", { MX, EM } },
5787 { "pmulhrsw", { MX, EM } },
c0f3af97
L		 5788 { "(bad)", { XX } },
5789 { "(bad)", { XX } },
5790 { "(bad)", { XX } },
5791 { "(bad)", { XX } },
f88c9eb0
SP		 5792 /* 10 */
5793 { PREFIX_TABLE (PREFIX_0F3810) },
5794 { "(bad)", { XX } },
5795 { "(bad)", { XX } },
5796 { "(bad)", { XX } },
5797 { PREFIX_TABLE (PREFIX_0F3814) },
5798 { PREFIX_TABLE (PREFIX_0F3815) },
5799 { "(bad)", { XX } },
5800 { PREFIX_TABLE (PREFIX_0F3817) },
5801 /* 18 */
5802 { "(bad)", { XX } },
5803 { "(bad)", { XX } },
5804 { "(bad)", { XX } },
5805 { "(bad)", { XX } },
5806 { "pabsb", { MX, EM } },
5807 { "pabsw", { MX, EM } },
5808 { "pabsd", { MX, EM } },
5809 { "(bad)", { XX } },
5810 /* 20 */
5811 { PREFIX_TABLE (PREFIX_0F3820) },
5812 { PREFIX_TABLE (PREFIX_0F3821) },
5813 { PREFIX_TABLE (PREFIX_0F3822) },
5814 { PREFIX_TABLE (PREFIX_0F3823) },
5815 { PREFIX_TABLE (PREFIX_0F3824) },
5816 { PREFIX_TABLE (PREFIX_0F3825) },
5817 { "(bad)", { XX } },
5818 { "(bad)", { XX } },
5819 /* 28 */
5820 { PREFIX_TABLE (PREFIX_0F3828) },
5821 { PREFIX_TABLE (PREFIX_0F3829) },
5822 { PREFIX_TABLE (PREFIX_0F382A) },
5823 { PREFIX_TABLE (PREFIX_0F382B) },
5824 { "(bad)", { XX } },
5825 { "(bad)", { XX } },
5826 { "(bad)", { XX } },
5827 { "(bad)", { XX } },
5828 /* 30 */
5829 { PREFIX_TABLE (PREFIX_0F3830) },
5830 { PREFIX_TABLE (PREFIX_0F3831) },
5831 { PREFIX_TABLE (PREFIX_0F3832) },
5832 { PREFIX_TABLE (PREFIX_0F3833) },
5833 { PREFIX_TABLE (PREFIX_0F3834) },
5834 { PREFIX_TABLE (PREFIX_0F3835) },
5835 { "(bad)", { XX } },
5836 { PREFIX_TABLE (PREFIX_0F3837) },
5837 /* 38 */
5838 { PREFIX_TABLE (PREFIX_0F3838) },
5839 { PREFIX_TABLE (PREFIX_0F3839) },
5840 { PREFIX_TABLE (PREFIX_0F383A) },
5841 { PREFIX_TABLE (PREFIX_0F383B) },
5842 { PREFIX_TABLE (PREFIX_0F383C) },
5843 { PREFIX_TABLE (PREFIX_0F383D) },
5844 { PREFIX_TABLE (PREFIX_0F383E) },
5845 { PREFIX_TABLE (PREFIX_0F383F) },
5846 /* 40 */
5847 { PREFIX_TABLE (PREFIX_0F3840) },
5848 { PREFIX_TABLE (PREFIX_0F3841) },
5849 { "(bad)", { XX } },
5850 { "(bad)", { XX } },
5851 { "(bad)", { XX } },
5852 { "(bad)", { XX } },
5853 { "(bad)", { XX } },
5854 { "(bad)", { XX } },
5855 /* 48 */
5856 { "(bad)", { XX } },
5857 { "(bad)", { XX } },
5858 { "(bad)", { XX } },
5859 { "(bad)", { XX } },
5860 { "(bad)", { XX } },
5861 { "(bad)", { XX } },
5862 { "(bad)", { XX } },
5863 { "(bad)", { XX } },
5864 /* 50 */
5865 { "(bad)", { XX } },
5866 { "(bad)", { XX } },
5867 { "(bad)", { XX } },
5868 { "(bad)", { XX } },
5869 { "(bad)", { XX } },
5870 { "(bad)", { XX } },
5871 { "(bad)", { XX } },
5872 { "(bad)", { XX } },
5873 /* 58 */
5874 { "(bad)", { XX } },
5875 { "(bad)", { XX } },
5876 { "(bad)", { XX } },
5877 { "(bad)", { XX } },
5878 { "(bad)", { XX } },
5879 { "(bad)", { XX } },
5880 { "(bad)", { XX } },
5881 { "(bad)", { XX } },
5882 /* 60 */
5883 { "(bad)", { XX } },
5884 { "(bad)", { XX } },
5885 { "(bad)", { XX } },
5886 { "(bad)", { XX } },
5887 { "(bad)", { XX } },
5888 { "(bad)", { XX } },
5889 { "(bad)", { XX } },
5890 { "(bad)", { XX } },
5891 /* 68 */
5892 { "(bad)", { XX } },
5893 { "(bad)", { XX } },
5894 { "(bad)", { XX } },
5895 { "(bad)", { XX } },
5896 { "(bad)", { XX } },
5897 { "(bad)", { XX } },
5898 { "(bad)", { XX } },
5899 { "(bad)", { XX } },
5900 /* 70 */
5901 { "(bad)", { XX } },
5902 { "(bad)", { XX } },
5903 { "(bad)", { XX } },
5904 { "(bad)", { XX } },
5905 { "(bad)", { XX } },
5906 { "(bad)", { XX } },
5907 { "(bad)", { XX } },
5908 { "(bad)", { XX } },
5909 /* 78 */
5910 { "(bad)", { XX } },
5911 { "(bad)", { XX } },
5912 { "(bad)", { XX } },
5913 { "(bad)", { XX } },
5914 { "(bad)", { XX } },
5915 { "(bad)", { XX } },
5916 { "(bad)", { XX } },
5917 { "(bad)", { XX } },
5918 /* 80 */
5919 { PREFIX_TABLE (PREFIX_0F3880) },
5920 { PREFIX_TABLE (PREFIX_0F3881) },
5921 { "(bad)", { XX } },
5922 { "(bad)", { XX } },
5923 { "(bad)", { XX } },
5924 { "(bad)", { XX } },
5925 { "(bad)", { XX } },
5926 { "(bad)", { XX } },
5927 /* 88 */
5928 { "(bad)", { XX } },
5929 { "(bad)", { XX } },
5930 { "(bad)", { XX } },
5931 { "(bad)", { XX } },
5932 { "(bad)", { XX } },
5933 { "(bad)", { XX } },
5934 { "(bad)", { XX } },
5935 { "(bad)", { XX } },
5936 /* 90 */
5937 { "(bad)", { XX } },
5938 { "(bad)", { XX } },
5939 { "(bad)", { XX } },
5940 { "(bad)", { XX } },
5941 { "(bad)", { XX } },
5942 { "(bad)", { XX } },
5943 { "(bad)", { XX } },
5944 { "(bad)", { XX } },
5945 /* 98 */
5946 { "(bad)", { XX } },
5947 { "(bad)", { XX } },
5948 { "(bad)", { XX } },
5949 { "(bad)", { XX } },
5950 { "(bad)", { XX } },
5951 { "(bad)", { XX } },
5952 { "(bad)", { XX } },
5953 { "(bad)", { XX } },
5954 /* a0 */
5955 { "(bad)", { XX } },
5956 { "(bad)", { XX } },
5957 { "(bad)", { XX } },
5958 { "(bad)", { XX } },
5959 { "(bad)", { XX } },
5960 { "(bad)", { XX } },
5961 { "(bad)", { XX } },
5962 { "(bad)", { XX } },
5963 /* a8 */
5964 { "(bad)", { XX } },
5965 { "(bad)", { XX } },
5966 { "(bad)", { XX } },
5967 { "(bad)", { XX } },
5968 { "(bad)", { XX } },
5969 { "(bad)", { XX } },
5970 { "(bad)", { XX } },
5971 { "(bad)", { XX } },
5972 /* b0 */
5973 { "(bad)", { XX } },
5974 { "(bad)", { XX } },
5975 { "(bad)", { XX } },
5976 { "(bad)", { XX } },
5977 { "(bad)", { XX } },
5978 { "(bad)", { XX } },
5979 { "(bad)", { XX } },
5980 { "(bad)", { XX } },
5981 /* b8 */
5982 { "(bad)", { XX } },
5983 { "(bad)", { XX } },
5984 { "(bad)", { XX } },
5985 { "(bad)", { XX } },
5986 { "(bad)", { XX } },
5987 { "(bad)", { XX } },
5988 { "(bad)", { XX } },
5989 { "(bad)", { XX } },
5990 /* c0 */
5991 { "(bad)", { XX } },
5992 { "(bad)", { XX } },
5993 { "(bad)", { XX } },
5994 { "(bad)", { XX } },
5995 { "(bad)", { XX } },
5996 { "(bad)", { XX } },
5997 { "(bad)", { XX } },
5998 { "(bad)", { XX } },
5999 /* c8 */
6000 { "(bad)", { XX } },
6001 { "(bad)", { XX } },
6002 { "(bad)", { XX } },
6003 { "(bad)", { XX } },
6004 { "(bad)", { XX } },
6005 { "(bad)", { XX } },
6006 { "(bad)", { XX } },
6007 { "(bad)", { XX } },
6008 /* d0 */
6009 { "(bad)", { XX } },
6010 { "(bad)", { XX } },
6011 { "(bad)", { XX } },
6012 { "(bad)", { XX } },
6013 { "(bad)", { XX } },
6014 { "(bad)", { XX } },
6015 { "(bad)", { XX } },
6016 { "(bad)", { XX } },
6017 /* d8 */
6018 { "(bad)", { XX } },
6019 { "(bad)", { XX } },
6020 { "(bad)", { XX } },
6021 { PREFIX_TABLE (PREFIX_0F38DB) },
6022 { PREFIX_TABLE (PREFIX_0F38DC) },
6023 { PREFIX_TABLE (PREFIX_0F38DD) },
6024 { PREFIX_TABLE (PREFIX_0F38DE) },
6025 { PREFIX_TABLE (PREFIX_0F38DF) },
6026 /* e0 */
6027 { "(bad)", { XX } },
6028 { "(bad)", { XX } },
6029 { "(bad)", { XX } },
6030 { "(bad)", { XX } },
6031 { "(bad)", { XX } },
6032 { "(bad)", { XX } },
6033 { "(bad)", { XX } },
6034 { "(bad)", { XX } },
6035 /* e8 */
6036 { "(bad)", { XX } },
6037 { "(bad)", { XX } },
6038 { "(bad)", { XX } },
6039 { "(bad)", { XX } },
6040 { "(bad)", { XX } },
6041 { "(bad)", { XX } },
6042 { "(bad)", { XX } },
6043 { "(bad)", { XX } },
6044 /* f0 */
6045 { PREFIX_TABLE (PREFIX_0F38F0) },
6046 { PREFIX_TABLE (PREFIX_0F38F1) },
6047 { "(bad)", { XX } },
6048 { "(bad)", { XX } },
6049 { "(bad)", { XX } },
6050 { "(bad)", { XX } },
6051 { "(bad)", { XX } },
6052 { "(bad)", { XX } },
6053 /* f8 */
6054 { "(bad)", { XX } },
6055 { "(bad)", { XX } },
6056 { "(bad)", { XX } },
6057 { "(bad)", { XX } },
6058 { "(bad)", { XX } },
6059 { "(bad)", { XX } },
6060 { "(bad)", { XX } },
6061 { "(bad)", { XX } },
6062 },
6063 /* THREE_BYTE_0F3A */
6064 {
6065 /* 00 */
6066 { "(bad)", { XX } },
6067 { "(bad)", { XX } },
6068 { "(bad)", { XX } },
6069 { "(bad)", { XX } },
6070 { "(bad)", { XX } },
6071 { "(bad)", { XX } },
6072 { "(bad)", { XX } },
6073 { "(bad)", { XX } },
6074 /* 08 */
6075 { PREFIX_TABLE (PREFIX_0F3A08) },
6076 { PREFIX_TABLE (PREFIX_0F3A09) },
6077 { PREFIX_TABLE (PREFIX_0F3A0A) },
6078 { PREFIX_TABLE (PREFIX_0F3A0B) },
6079 { PREFIX_TABLE (PREFIX_0F3A0C) },
6080 { PREFIX_TABLE (PREFIX_0F3A0D) },
6081 { PREFIX_TABLE (PREFIX_0F3A0E) },
6082 { "palignr", { MX, EM, Ib } },
6083 /* 10 */
6084 { "(bad)", { XX } },
6085 { "(bad)", { XX } },
6086 { "(bad)", { XX } },
6087 { "(bad)", { XX } },
6088 { PREFIX_TABLE (PREFIX_0F3A14) },
6089 { PREFIX_TABLE (PREFIX_0F3A15) },
6090 { PREFIX_TABLE (PREFIX_0F3A16) },
6091 { PREFIX_TABLE (PREFIX_0F3A17) },
6092 /* 18 */
6093 { "(bad)", { XX } },
6094 { "(bad)", { XX } },
6095 { "(bad)", { XX } },
6096 { "(bad)", { XX } },
6097 { "(bad)", { XX } },
6098 { "(bad)", { XX } },
6099 { "(bad)", { XX } },
6100 { "(bad)", { XX } },
6101 /* 20 */
6102 { PREFIX_TABLE (PREFIX_0F3A20) },
6103 { PREFIX_TABLE (PREFIX_0F3A21) },
6104 { PREFIX_TABLE (PREFIX_0F3A22) },
6105 { "(bad)", { XX } },
6106 { "(bad)", { XX } },
6107 { "(bad)", { XX } },
6108 { "(bad)", { XX } },
6109 { "(bad)", { XX } },
6110 /* 28 */
6111 { "(bad)", { XX } },
6112 { "(bad)", { XX } },
6113 { "(bad)", { XX } },
6114 { "(bad)", { XX } },
6115 { "(bad)", { XX } },
6116 { "(bad)", { XX } },
6117 { "(bad)", { XX } },
6118 { "(bad)", { XX } },
6119 /* 30 */
6120 { "(bad)", { XX } },
6121 { "(bad)", { XX } },
6122 { "(bad)", { XX } },
6123 { "(bad)", { XX } },
6124 { "(bad)", { XX } },
6125 { "(bad)", { XX } },
6126 { "(bad)", { XX } },
6127 { "(bad)", { XX } },
6128 /* 38 */
6129 { "(bad)", { XX } },
6130 { "(bad)", { XX } },
6131 { "(bad)", { XX } },
6132 { "(bad)", { XX } },
6133 { "(bad)", { XX } },
6134 { "(bad)", { XX } },
6135 { "(bad)", { XX } },
6136 { "(bad)", { XX } },
6137 /* 40 */
6138 { PREFIX_TABLE (PREFIX_0F3A40) },
6139 { PREFIX_TABLE (PREFIX_0F3A41) },
6140 { PREFIX_TABLE (PREFIX_0F3A42) },
6141 { "(bad)", { XX } },
6142 { PREFIX_TABLE (PREFIX_0F3A44) },
6143 { "(bad)", { XX } },
6144 { "(bad)", { XX } },
6145 { "(bad)", { XX } },
6146 /* 48 */
6147 { "(bad)", { XX } },
6148 { "(bad)", { XX } },
6149 { "(bad)", { XX } },
6150 { "(bad)", { XX } },
6151 { "(bad)", { XX } },
6152 { "(bad)", { XX } },
6153 { "(bad)", { XX } },
6154 { "(bad)", { XX } },
6155 /* 50 */
6156 { "(bad)", { XX } },
6157 { "(bad)", { XX } },
6158 { "(bad)", { XX } },
6159 { "(bad)", { XX } },
6160 { "(bad)", { XX } },
6161 { "(bad)", { XX } },
6162 { "(bad)", { XX } },
6163 { "(bad)", { XX } },
6164 /* 58 */
6165 { "(bad)", { XX } },
6166 { "(bad)", { XX } },
6167 { "(bad)", { XX } },
6168 { "(bad)", { XX } },
6169 { "(bad)", { XX } },
6170 { "(bad)", { XX } },
6171 { "(bad)", { XX } },
6172 { "(bad)", { XX } },
6173 /* 60 */
6174 { PREFIX_TABLE (PREFIX_0F3A60) },
6175 { PREFIX_TABLE (PREFIX_0F3A61) },
6176 { PREFIX_TABLE (PREFIX_0F3A62) },
6177 { PREFIX_TABLE (PREFIX_0F3A63) },
6178 { "(bad)", { XX } },
6179 { "(bad)", { XX } },
6180 { "(bad)", { XX } },
6181 { "(bad)", { XX } },
6182 /* 68 */
6183 { "(bad)", { XX } },
6184 { "(bad)", { XX } },
6185 { "(bad)", { XX } },
6186 { "(bad)", { XX } },
6187 { "(bad)", { XX } },
6188 { "(bad)", { XX } },
6189 { "(bad)", { XX } },
6190 { "(bad)", { XX } },
6191 /* 70 */
6192 { "(bad)", { XX } },
6193 { "(bad)", { XX } },
6194 { "(bad)", { XX } },
6195 { "(bad)", { XX } },
6196 { "(bad)", { XX } },
6197 { "(bad)", { XX } },
6198 { "(bad)", { XX } },
6199 { "(bad)", { XX } },
6200 /* 78 */
6201 { "(bad)", { XX } },
6202 { "(bad)", { XX } },
6203 { "(bad)", { XX } },
6204 { "(bad)", { XX } },
6205 { "(bad)", { XX } },
6206 { "(bad)", { XX } },
6207 { "(bad)", { XX } },
6208 { "(bad)", { XX } },
6209 /* 80 */
6210 { "(bad)", { XX } },
6211 { "(bad)", { XX } },
6212 { "(bad)", { XX } },
6213 { "(bad)", { XX } },
6214 { "(bad)", { XX } },
6215 { "(bad)", { XX } },
6216 { "(bad)", { XX } },
6217 { "(bad)", { XX } },
6218 /* 88 */
6219 { "(bad)", { XX } },
6220 { "(bad)", { XX } },
6221 { "(bad)", { XX } },
6222 { "(bad)", { XX } },
6223 { "(bad)", { XX } },
6224 { "(bad)", { XX } },
6225 { "(bad)", { XX } },
6226 { "(bad)", { XX } },
6227 /* 90 */
6228 { "(bad)", { XX } },
6229 { "(bad)", { XX } },
6230 { "(bad)", { XX } },
6231 { "(bad)", { XX } },
6232 { "(bad)", { XX } },
6233 { "(bad)", { XX } },
6234 { "(bad)", { XX } },
6235 { "(bad)", { XX } },
6236 /* 98 */
6237 { "(bad)", { XX } },
6238 { "(bad)", { XX } },
6239 { "(bad)", { XX } },
6240 { "(bad)", { XX } },
6241 { "(bad)", { XX } },
6242 { "(bad)", { XX } },
6243 { "(bad)", { XX } },
6244 { "(bad)", { XX } },
6245 /* a0 */
6246 { "(bad)", { XX } },
6247 { "(bad)", { XX } },
6248 { "(bad)", { XX } },
6249 { "(bad)", { XX } },
6250 { "(bad)", { XX } },
6251 { "(bad)", { XX } },
6252 { "(bad)", { XX } },
6253 { "(bad)", { XX } },
6254 /* a8 */
6255 { "(bad)", { XX } },
6256 { "(bad)", { XX } },
6257 { "(bad)", { XX } },
6258 { "(bad)", { XX } },
6259 { "(bad)", { XX } },
6260 { "(bad)", { XX } },
6261 { "(bad)", { XX } },
6262 { "(bad)", { XX } },
6263 /* b0 */
6264 { "(bad)", { XX } },
6265 { "(bad)", { XX } },
6266 { "(bad)", { XX } },
6267 { "(bad)", { XX } },
6268 { "(bad)", { XX } },
6269 { "(bad)", { XX } },
6270 { "(bad)", { XX } },
6271 { "(bad)", { XX } },
6272 /* b8 */
6273 { "(bad)", { XX } },
6274 { "(bad)", { XX } },
6275 { "(bad)", { XX } },
6276 { "(bad)", { XX } },
6277 { "(bad)", { XX } },
6278 { "(bad)", { XX } },
6279 { "(bad)", { XX } },
6280 { "(bad)", { XX } },
6281 /* c0 */
6282 { "(bad)", { XX } },
6283 { "(bad)", { XX } },
6284 { "(bad)", { XX } },
6285 { "(bad)", { XX } },
6286 { "(bad)", { XX } },
6287 { "(bad)", { XX } },
6288 { "(bad)", { XX } },
6289 { "(bad)", { XX } },
6290 /* c8 */
6291 { "(bad)", { XX } },
6292 { "(bad)", { XX } },
6293 { "(bad)", { XX } },
6294 { "(bad)", { XX } },
6295 { "(bad)", { XX } },
6296 { "(bad)", { XX } },
6297 { "(bad)", { XX } },
6298 { "(bad)", { XX } },
6299 /* d0 */
6300 { "(bad)", { XX } },
6301 { "(bad)", { XX } },
6302 { "(bad)", { XX } },
6303 { "(bad)", { XX } },
6304 { "(bad)", { XX } },
6305 { "(bad)", { XX } },
6306 { "(bad)", { XX } },
6307 { "(bad)", { XX } },
6308 /* d8 */
6309 { "(bad)", { XX } },
6310 { "(bad)", { XX } },
6311 { "(bad)", { XX } },
6312 { "(bad)", { XX } },
6313 { "(bad)", { XX } },
6314 { "(bad)", { XX } },
6315 { "(bad)", { XX } },
6316 { PREFIX_TABLE (PREFIX_0F3ADF) },
6317 /* e0 */
6318 { "(bad)", { XX } },
6319 { "(bad)", { XX } },
6320 { "(bad)", { XX } },
6321 { "(bad)", { XX } },
6322 { "(bad)", { XX } },
6323 { "(bad)", { XX } },
6324 { "(bad)", { XX } },
6325 { "(bad)", { XX } },
6326 /* e8 */
6327 { "(bad)", { XX } },
6328 { "(bad)", { XX } },
6329 { "(bad)", { XX } },
6330 { "(bad)", { XX } },
6331 { "(bad)", { XX } },
6332 { "(bad)", { XX } },
6333 { "(bad)", { XX } },
6334 { "(bad)", { XX } },
6335 /* f0 */
6336 { "(bad)", { XX } },
6337 { "(bad)", { XX } },
6338 { "(bad)", { XX } },
6339 { "(bad)", { XX } },
6340 { "(bad)", { XX } },
6341 { "(bad)", { XX } },
6342 { "(bad)", { XX } },
6343 { "(bad)", { XX } },
6344 /* f8 */
6345 { "(bad)", { XX } },
6346 { "(bad)", { XX } },
6347 { "(bad)", { XX } },
6348 { "(bad)", { XX } },
6349 { "(bad)", { XX } },
6350 { "(bad)", { XX } },
6351 { "(bad)", { XX } },
6352 { "(bad)", { XX } },
6353 },
6354
6355 /* THREE_BYTE_0F7A */
6356 {
6357 /* 00 */
6358 { "(bad)", { XX } },
6359 { "(bad)", { XX } },
6360 { "(bad)", { XX } },
6361 { "(bad)", { XX } },
6362 { "(bad)", { XX } },
6363 { "(bad)", { XX } },
6364 { "(bad)", { XX } },
6365 { "(bad)", { XX } },
6366 /* 08 */
6367 { "(bad)", { XX } },
6368 { "(bad)", { XX } },
6369 { "(bad)", { XX } },
6370 { "(bad)", { XX } },
6371 { "(bad)", { XX } },
6372 { "(bad)", { XX } },
6373 { "(bad)", { XX } },
6374 { "(bad)", { XX } },
6375 /* 10 */
6376 { "(bad)", { XX } },
6377 { "(bad)", { XX } },
6378 { "(bad)", { XX } },
6379 { "(bad)", { XX } },
6380 { "(bad)", { XX } },
6381 { "(bad)", { XX } },
6382 { "(bad)", { XX } },
6383 { "(bad)", { XX } },
6384 /* 18 */
6385 { "(bad)", { XX } },
6386 { "(bad)", { XX } },
6387 { "(bad)", { XX } },
6388 { "(bad)", { XX } },
6389 { "(bad)", { XX } },
6390 { "(bad)", { XX } },
6391 { "(bad)", { XX } },
6392 { "(bad)", { XX } },
6393 /* 20 */
6394 { "ptest", { XX } },
6395 { "(bad)", { XX } },
6396 { "(bad)", { XX } },
c0f3af97
L		 6397 { "(bad)", { XX } },
6398 { "(bad)", { XX } },
6399 { "(bad)", { XX } },
6400 { "(bad)", { XX } },
6401 { "(bad)", { XX } },
f88c9eb0 6402 /* 28 */
c0f3af97
L		 6403 { "(bad)", { XX } },
6404 { "(bad)", { XX } },
6405 { "(bad)", { XX } },
c0f3af97
L		 6406 { "(bad)", { XX } },
6407 { "(bad)", { XX } },
6408 { "(bad)", { XX } },
6409 { "(bad)", { XX } },
6410 { "(bad)", { XX } },
f88c9eb0 6411 /* 30 */
c0f3af97
L		 6412 { "(bad)", { XX } },
6413 { "(bad)", { XX } },
6414 { "(bad)", { XX } },
4e7d34a6
L		 6415 { "(bad)", { XX } },
6416 { "(bad)", { XX } },
c0f3af97 6417 { "(bad)", { XX } },
c0f3af97
L		 6418 { "(bad)", { XX } },
6419 { "(bad)", { XX } },
f88c9eb0 6420 /* 38 */
c0f3af97 6421 { "(bad)", { XX } },
4e7d34a6
L		 6422 { "(bad)", { XX } },
6423 { "(bad)", { XX } },
6424 { "(bad)", { XX } },
6425 { "(bad)", { XX } },
4e7d34a6
L		 6426 { "(bad)", { XX } },
6427 { "(bad)", { XX } },
6428 { "(bad)", { XX } },
f88c9eb0 6429 /* 40 */
4e7d34a6 6430 { "(bad)", { XX } },
f88c9eb0
SP		 6431 { "phaddbw", { XM, EXq } },
6432 { "phaddbd", { XM, EXq } },
6433 { "phaddbq", { XM, EXq } },
4e7d34a6
L		 6434 { "(bad)", { XX } },
6435 { "(bad)", { XX } },
f88c9eb0
SP		 6436 { "phaddwd", { XM, EXq } },
6437 { "phaddwq", { XM, EXq } },
6438 /* 48 */
4e7d34a6
L		 6439 { "(bad)", { XX } },
6440 { "(bad)", { XX } },
4e7d34a6 6441 { "(bad)", { XX } },
f88c9eb0 6442 { "phadddq", { XM, EXq } },
4e7d34a6
L		 6443 { "(bad)", { XX } },
6444 { "(bad)", { XX } },
6445 { "(bad)", { XX } },
6446 { "(bad)", { XX } },
f88c9eb0 6447 /* 50 */
4e7d34a6 6448 { "(bad)", { XX } },
f88c9eb0
SP		 6449 { "phaddubw", { XM, EXq } },
6450 { "phaddubd", { XM, EXq } },
6451 { "phaddubq", { XM, EXq } },
4e7d34a6
L		 6452 { "(bad)", { XX } },
6453 { "(bad)", { XX } },
f88c9eb0
SP		 6454 { "phadduwd", { XM, EXq } },
6455 { "phadduwq", { XM, EXq } },
6456 /* 58 */
4e7d34a6
L		 6457 { "(bad)", { XX } },
6458 { "(bad)", { XX } },
6459 { "(bad)", { XX } },
f88c9eb0 6460 { "phaddudq", { XM, EXq } },
4e7d34a6 6461 { "(bad)", { XX } },
c1e679ec
DR		 6462 { "(bad)", { XX } },
6463 { "(bad)", { XX } },
6464 { "(bad)", { XX } },
f88c9eb0 6465 /* 60 */
c1e679ec 6466 { "(bad)", { XX } },
f88c9eb0
SP		 6467 { "phsubbw", { XM, EXq } },
6468 { "phsubbd", { XM, EXq } },
6469 { "phsubbq", { XM, EXq } },
4e7d34a6
L		 6470 { "(bad)", { XX } },
6471 { "(bad)", { XX } },
6472 { "(bad)", { XX } },
6473 { "(bad)", { XX } },
6474 /* 68 */
6475 { "(bad)", { XX } },
6476 { "(bad)", { XX } },
6477 { "(bad)", { XX } },
6478 { "(bad)", { XX } },
6479 { "(bad)", { XX } },
6480 { "(bad)", { XX } },
6481 { "(bad)", { XX } },
6482 { "(bad)", { XX } },
85f10a01 6483 /* 70 */
4e7d34a6
L		 6484 { "(bad)", { XX } },
6485 { "(bad)", { XX } },
6486 { "(bad)", { XX } },
6487 { "(bad)", { XX } },
6488 { "(bad)", { XX } },
6489 { "(bad)", { XX } },
6490 { "(bad)", { XX } },
6491 { "(bad)", { XX } },
85f10a01 6492 /* 78 */
4e7d34a6
L		 6493 { "(bad)", { XX } },
6494 { "(bad)", { XX } },
6495 { "(bad)", { XX } },
6496 { "(bad)", { XX } },
6497 { "(bad)", { XX } },
6498 { "(bad)", { XX } },
6499 { "(bad)", { XX } },
6500 { "(bad)", { XX } },
85f10a01 6501 /* 80 */
f88c9eb0
SP		 6502 { "(bad)", { XX } },
6503 { "(bad)", { XX } },
4e7d34a6
L		 6504 { "(bad)", { XX } },
6505 { "(bad)", { XX } },
6506 { "(bad)", { XX } },
c0f3af97
L		 6507 { "(bad)", { XX } },
6508 { "(bad)", { XX } },
6509 { "(bad)", { XX } },
85f10a01 6510 /* 88 */
4e7d34a6
L		 6511 { "(bad)", { XX } },
6512 { "(bad)", { XX } },
6513 { "(bad)", { XX } },
6514 { "(bad)", { XX } },
6515 { "(bad)", { XX } },
6516 { "(bad)", { XX } },
c0f3af97
L		 6517 { "(bad)", { XX } },
6518 { "(bad)", { XX } },
85f10a01 6519 /* 90 */
4e7d34a6
L		 6520 { "(bad)", { XX } },
6521 { "(bad)", { XX } },
6522 { "(bad)", { XX } },
6523 { "(bad)", { XX } },
6524 { "(bad)", { XX } },
c0f3af97
L		 6525 { "(bad)", { XX } },
6526 { "(bad)", { XX } },
6527 { "(bad)", { XX } },
85f10a01 6528 /* 98 */
4e7d34a6
L		 6529 { "(bad)", { XX } },
6530 { "(bad)", { XX } },
6531 { "(bad)", { XX } },
6532 { "(bad)", { XX } },
6533 { "(bad)", { XX } },
6534 { "(bad)", { XX } },
c0f3af97
L		 6535 { "(bad)", { XX } },
6536 { "(bad)", { XX } },
85f10a01 6537 /* a0 */
4e7d34a6
L		 6538 { "(bad)", { XX } },
6539 { "(bad)", { XX } },
6540 { "(bad)", { XX } },
6541 { "(bad)", { XX } },
6542 { "(bad)", { XX } },
6543 { "(bad)", { XX } },
c0f3af97 6544 { "(bad)", { XX } },
4e7d34a6 6545 { "(bad)", { XX } },
85f10a01 6546 /* a8 */
4e7d34a6
L		 6547 { "(bad)", { XX } },
6548 { "(bad)", { XX } },
6549 { "(bad)", { XX } },
6550 { "(bad)", { XX } },
6551 { "(bad)", { XX } },
6552 { "(bad)", { XX } },
6553 { "(bad)", { XX } },
6554 { "(bad)", { XX } },
85f10a01 6555 /* b0 */
4e7d34a6
L		 6556 { "(bad)", { XX } },
6557 { "(bad)", { XX } },
6558 { "(bad)", { XX } },
6559 { "(bad)", { XX } },
6560 { "(bad)", { XX } },
6561 { "(bad)", { XX } },
c0f3af97 6562 { "(bad)", { XX } },
4e7d34a6 6563 { "(bad)", { XX } },
85f10a01 6564 /* b8 */
4e7d34a6
L		 6565 { "(bad)", { XX } },
6566 { "(bad)", { XX } },
6567 { "(bad)", { XX } },
6568 { "(bad)", { XX } },
6569 { "(bad)", { XX } },
6570 { "(bad)", { XX } },
6571 { "(bad)", { XX } },
6572 { "(bad)", { XX } },
85f10a01 6573 /* c0 */
4e7d34a6
L		 6574 { "(bad)", { XX } },
6575 { "(bad)", { XX } },
6576 { "(bad)", { XX } },
6577 { "(bad)", { XX } },
6578 { "(bad)", { XX } },
6579 { "(bad)", { XX } },
6580 { "(bad)", { XX } },
6581 { "(bad)", { XX } },
85f10a01 6582 /* c8 */
4e7d34a6
L		 6583 { "(bad)", { XX } },
6584 { "(bad)", { XX } },
6585 { "(bad)", { XX } },
6586 { "(bad)", { XX } },
6587 { "(bad)", { XX } },
6588 { "(bad)", { XX } },
6589 { "(bad)", { XX } },
6590 { "(bad)", { XX } },
85f10a01 6591 /* d0 */
4e7d34a6
L		 6592 { "(bad)", { XX } },
6593 { "(bad)", { XX } },
6594 { "(bad)", { XX } },
6595 { "(bad)", { XX } },
6596 { "(bad)", { XX } },
6597 { "(bad)", { XX } },
6598 { "(bad)", { XX } },
6599 { "(bad)", { XX } },
85f10a01 6600 /* d8 */
4e7d34a6
L		 6601 { "(bad)", { XX } },
6602 { "(bad)", { XX } },
6603 { "(bad)", { XX } },
f88c9eb0
SP		 6604 { "(bad)", { XX } },
6605 { "(bad)", { XX } },
6606 { "(bad)", { XX } },
6607 { "(bad)", { XX } },
6608 { "(bad)", { XX } },
85f10a01 6609 /* e0 */
4e7d34a6
L		 6610 { "(bad)", { XX } },
6611 { "(bad)", { XX } },
6612 { "(bad)", { XX } },
6613 { "(bad)", { XX } },
6614 { "(bad)", { XX } },
6615 { "(bad)", { XX } },
6616 { "(bad)", { XX } },
6617 { "(bad)", { XX } },
85f10a01 6618 /* e8 */
4e7d34a6
L		 6619 { "(bad)", { XX } },
6620 { "(bad)", { XX } },
6621 { "(bad)", { XX } },
6622 { "(bad)", { XX } },
6623 { "(bad)", { XX } },
6624 { "(bad)", { XX } },
6625 { "(bad)", { XX } },
6626 { "(bad)", { XX } },
85f10a01 6627 /* f0 */
f88c9eb0
SP		 6628 { "(bad)", { XX } },
6629 { "(bad)", { XX } },
4e7d34a6
L		 6630 { "(bad)", { XX } },
6631 { "(bad)", { XX } },
6632 { "(bad)", { XX } },
6633 { "(bad)", { XX } },
6634 { "(bad)", { XX } },
6635 { "(bad)", { XX } },
85f10a01 6636 /* f8 */
4e7d34a6
L		 6637 { "(bad)", { XX } },
6638 { "(bad)", { XX } },
6639 { "(bad)", { XX } },
6640 { "(bad)", { XX } },
6641 { "(bad)", { XX } },
6642 { "(bad)", { XX } },
6643 { "(bad)", { XX } },
6644 { "(bad)", { XX } },
85f10a01 6645 },
f88c9eb0
SP		 6646};
6647
6648static const struct dis386 xop_table[][256] = {
5dd85c99 6649 /* XOP_08 */
85f10a01
MM		 6650 {
6651 /* 00 */
4e7d34a6
L		 6652 { "(bad)", { XX } },
6653 { "(bad)", { XX } },
6654 { "(bad)", { XX } },
6655 { "(bad)", { XX } },
6656 { "(bad)", { XX } },
6657 { "(bad)", { XX } },
6658 { "(bad)", { XX } },
6659 { "(bad)", { XX } },
85f10a01 6660 /* 08 */
f88c9eb0
SP		 6661 { "(bad)", { XX } },
6662 { "(bad)", { XX } },
6663 { "(bad)", { XX } },
6664 { "(bad)", { XX } },
6665 { "(bad)", { XX } },
6666 { "(bad)", { XX } },
6667 { "(bad)", { XX } },
6668 { "(bad)", { XX } },
85f10a01 6669 /* 10 */
4e7d34a6
L		 6670 { "(bad)", { XX } },
6671 { "(bad)", { XX } },
5dd85c99 6672 { "(bad)", { XX } },
f88c9eb0
SP		 6673 { "(bad)", { XX } },
6674 { "(bad)", { XX } },
6675 { "(bad)", { XX } },
4e7d34a6
L		 6676 { "(bad)", { XX } },
6677 { "(bad)", { XX } },
85f10a01 6678 /* 18 */
4e7d34a6
L		 6679 { "(bad)", { XX } },
6680 { "(bad)", { XX } },
6681 { "(bad)", { XX } },
6682 { "(bad)", { XX } },
6683 { "(bad)", { XX } },
6684 { "(bad)", { XX } },
6685 { "(bad)", { XX } },
6686 { "(bad)", { XX } },
85f10a01 6687 /* 20 */
f88c9eb0
SP		 6688 { "(bad)", { XX } },
6689 { "(bad)", { XX } },
6690 { "(bad)", { XX } },
4e7d34a6
L		 6691 { "(bad)", { XX } },
6692 { "(bad)", { XX } },
6693 { "(bad)", { XX } },
6694 { "(bad)", { XX } },
6695 { "(bad)", { XX } },
85f10a01 6696 /* 28 */
4e7d34a6
L		 6697 { "(bad)", { XX } },
6698 { "(bad)", { XX } },
6699 { "(bad)", { XX } },
6700 { "(bad)", { XX } },
4e7d34a6
L		 6701 { "(bad)", { XX } },
6702 { "(bad)", { XX } },
6703 { "(bad)", { XX } },
6704 { "(bad)", { XX } },
c0f3af97 6705 /* 30 */
c1e679ec
DR		 6706 { "(bad)", { XX } },
6707 { "(bad)", { XX } },
4e7d34a6 6708 { "(bad)", { XX } },
4e7d34a6
L		 6709 { "(bad)", { XX } },
6710 { "(bad)", { XX } },
6711 { "(bad)", { XX } },
6712 { "(bad)", { XX } },
6713 { "(bad)", { XX } },
c0f3af97 6714 /* 38 */
4e7d34a6
L		 6715 { "(bad)", { XX } },
6716 { "(bad)", { XX } },
6717 { "(bad)", { XX } },
4e7d34a6
L		 6718 { "(bad)", { XX } },
6719 { "(bad)", { XX } },
6720 { "(bad)", { XX } },
6721 { "(bad)", { XX } },
6722 { "(bad)", { XX } },
c0f3af97 6723 /* 40 */
c1e679ec 6724 { "(bad)", { XX } },
f88c9eb0
SP		 6725 { "(bad)", { XX } },
6726 { "(bad)", { XX } },
6727 { "(bad)", { XX } },
6728 { "(bad)", { XX } },
4e7d34a6
L		 6729 { "(bad)", { XX } },
6730 { "(bad)", { XX } },
6731 { "(bad)", { XX } },
85f10a01 6732 /* 48 */
4e7d34a6
L		 6733 { "(bad)", { XX } },
6734 { "(bad)", { XX } },
6735 { "(bad)", { XX } },
c1e679ec 6736 { "(bad)", { XX } },
4e7d34a6
L		 6737 { "(bad)", { XX } },
6738 { "(bad)", { XX } },
6739 { "(bad)", { XX } },
6740 { "(bad)", { XX } },
c0f3af97 6741 /* 50 */
4e7d34a6
L		 6742 { "(bad)", { XX } },
6743 { "(bad)", { XX } },
6744 { "(bad)", { XX } },
c1e679ec
DR		 6745 { "(bad)", { XX } },
6746 { "(bad)", { XX } },
6747 { "(bad)", { XX } },
6748 { "(bad)", { XX } },
6749 { "(bad)", { XX } },
85f10a01 6750 /* 58 */
4e7d34a6
L		 6751 { "(bad)", { XX } },
6752 { "(bad)", { XX } },
6753 { "(bad)", { XX } },
4e7d34a6
L		 6754 { "(bad)", { XX } },
6755 { "(bad)", { XX } },
6756 { "(bad)", { XX } },
6757 { "(bad)", { XX } },
4e7d34a6 6758 { "(bad)", { XX } },
c1e679ec 6759 /* 60 */
f88c9eb0
SP		 6760 { "(bad)", { XX } },
6761 { "(bad)", { XX } },
6762 { "(bad)", { XX } },
6763 { "(bad)", { XX } },
4e7d34a6
L		 6764 { "(bad)", { XX } },
6765 { "(bad)", { XX } },
6766 { "(bad)", { XX } },
6767 { "(bad)", { XX } },
c0f3af97
L		 6768 /* 68 */
6769 { "(bad)", { XX } },
4e7d34a6
L		 6770 { "(bad)", { XX } },
6771 { "(bad)", { XX } },
6772 { "(bad)", { XX } },
4e7d34a6
L		 6773 { "(bad)", { XX } },
6774 { "(bad)", { XX } },
6775 { "(bad)", { XX } },
6776 { "(bad)", { XX } },
85f10a01 6777 /* 70 */
4e7d34a6
L		 6778 { "(bad)", { XX } },
6779 { "(bad)", { XX } },
6780 { "(bad)", { XX } },
6781 { "(bad)", { XX } },
6782 { "(bad)", { XX } },
6783 { "(bad)", { XX } },
6784 { "(bad)", { XX } },
6785 { "(bad)", { XX } },
85f10a01 6786 /* 78 */
4e7d34a6
L		 6787 { "(bad)", { XX } },
6788 { "(bad)", { XX } },
6789 { "(bad)", { XX } },
6790 { "(bad)", { XX } },
6791 { "(bad)", { XX } },
6792 { "(bad)", { XX } },
6793 { "(bad)", { XX } },
6794 { "(bad)", { XX } },
85f10a01 6795 /* 80 */
4e7d34a6
L		 6796 { "(bad)", { XX } },
6797 { "(bad)", { XX } },
6798 { "(bad)", { XX } },
6799 { "(bad)", { XX } },
6800 { "(bad)", { XX } },
5dd85c99
SP		 6801 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6802 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6803 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6804 /* 88 */
4e7d34a6
L		 6805 { "(bad)", { XX } },
6806 { "(bad)", { XX } },
6807 { "(bad)", { XX } },
4e7d34a6
L		 6808 { "(bad)", { XX } },
6809 { "(bad)", { XX } },
6810 { "(bad)", { XX } },
5dd85c99
SP		 6811 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6812 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6813 /* 90 */
4e7d34a6
L		 6814 { "(bad)", { XX } },
6815 { "(bad)", { XX } },
6816 { "(bad)", { XX } },
6817 { "(bad)", { XX } },
6818 { "(bad)", { XX } },
5dd85c99
SP		 6819 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6820 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6821 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6822 /* 98 */
4e7d34a6
L		 6823 { "(bad)", { XX } },
6824 { "(bad)", { XX } },
6825 { "(bad)", { XX } },
6826 { "(bad)", { XX } },
6827 { "(bad)", { XX } },
6828 { "(bad)", { XX } },
5dd85c99
SP		 6829 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6830 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6831 /* a0 */
f0ae4a24
SP		 6832 { "(bad)", { XX } },
6833 { "(bad)", { XX } },
5dd85c99
SP		 6834 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6835 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
4e7d34a6
L		 6836 { "(bad)", { XX } },
6837 { "(bad)", { XX } },
5dd85c99 6838 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
4e7d34a6 6839 { "(bad)", { XX } },
5dd85c99 6840 /* a8 */
4e7d34a6
L		 6841 { "(bad)", { XX } },
6842 { "(bad)", { XX } },
6843 { "(bad)", { XX } },
6844 { "(bad)", { XX } },
6845 { "(bad)", { XX } },
6846 { "(bad)", { XX } },
6847 { "(bad)", { XX } },
4e7d34a6 6848 { "(bad)", { XX } },
5dd85c99 6849 /* b0 */
4e7d34a6
L		 6850 { "(bad)", { XX } },
6851 { "(bad)", { XX } },
6852 { "(bad)", { XX } },
6853 { "(bad)", { XX } },
6854 { "(bad)", { XX } },
6855 { "(bad)", { XX } },
5dd85c99 6856 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
4e7d34a6 6857 { "(bad)", { XX } },
5dd85c99 6858 /* b8 */
4e7d34a6
L		 6859 { "(bad)", { XX } },
6860 { "(bad)", { XX } },
6861 { "(bad)", { XX } },
6862 { "(bad)", { XX } },
6863 { "(bad)", { XX } },
6864 { "(bad)", { XX } },
6865 { "(bad)", { XX } },
6866 { "(bad)", { XX } },
5dd85c99
SP		 6867 /* c0 */
6868 { "vprotb", { XM, Vex_2src_1, Ib } },
6869 { "vprotw", { XM, Vex_2src_1, Ib } },
6870 { "vprotd", { XM, Vex_2src_1, Ib } },
6871 { "vprotq", { XM, Vex_2src_1, Ib } },
4e7d34a6
L		 6872 { "(bad)", { XX } },
6873 { "(bad)", { XX } },
6874 { "(bad)", { XX } },
6875 { "(bad)", { XX } },
5dd85c99 6876 /* c8 */
4e7d34a6
L		 6877 { "(bad)", { XX } },
6878 { "(bad)", { XX } },
6879 { "(bad)", { XX } },
6880 { "(bad)", { XX } },
5dd85c99
SP		 6881 { "vpcomb", { XM, Vex128, EXx, Ib } },
6882 { "vpcomw", { XM, Vex128, EXx, Ib } },
6883 { "vpcomd", { XM, Vex128, EXx, Ib } },
6884 { "vpcomq", { XM, Vex128, EXx, Ib } },
6885 /* d0 */
4e7d34a6
L		 6886 { "(bad)", { XX } },
6887 { "(bad)", { XX } },
6888 { "(bad)", { XX } },
6889 { "(bad)", { XX } },
6890 { "(bad)", { XX } },
6891 { "(bad)", { XX } },
6892 { "(bad)", { XX } },
6893 { "(bad)", { XX } },
5dd85c99 6894 /* d8 */
4e7d34a6
L		 6895 { "(bad)", { XX } },
6896 { "(bad)", { XX } },
6897 { "(bad)", { XX } },
6898 { "(bad)", { XX } },
6899 { "(bad)", { XX } },
6900 { "(bad)", { XX } },
6901 { "(bad)", { XX } },
6902 { "(bad)", { XX } },
5dd85c99 6903 /* e0 */
4e7d34a6
L		 6904 { "(bad)", { XX } },
6905 { "(bad)", { XX } },
6906 { "(bad)", { XX } },
6907 { "(bad)", { XX } },
6908 { "(bad)", { XX } },
6909 { "(bad)", { XX } },
6910 { "(bad)", { XX } },
6911 { "(bad)", { XX } },
5dd85c99 6912 /* e8 */
4e7d34a6
L		 6913 { "(bad)", { XX } },
6914 { "(bad)", { XX } },
6915 { "(bad)", { XX } },
6916 { "(bad)", { XX } },
5dd85c99
SP		 6917 { "vpcomub", { XM, Vex128, EXx, Ib } },
6918 { "vpcomuw", { XM, Vex128, EXx, Ib } },
6919 { "vpcomud", { XM, Vex128, EXx, Ib } },
6920 { "vpcomuq", { XM, Vex128, EXx, Ib } },
6921 /* f0 */
4e7d34a6
L		 6922 { "(bad)", { XX } },
6923 { "(bad)", { XX } },
6924 { "(bad)", { XX } },
6925 { "(bad)", { XX } },
4e7d34a6
L		 6926 { "(bad)", { XX } },
6927 { "(bad)", { XX } },
6928 { "(bad)", { XX } },
6929 { "(bad)", { XX } },
5dd85c99
SP		 6930 /* f8 */
6931 { "(bad)", { XX } },
6932 { "(bad)", { XX } },
6933 { "(bad)", { XX } },
6934 { "(bad)", { XX } },
6935 { "(bad)", { XX } },
6936 { "(bad)", { XX } },
6937 { "(bad)", { XX } },
6938 { "(bad)", { XX } },
6939 },
6940 /* XOP_09 */
6941 {
6942 /* 00 */
6943 { "(bad)", { XX } },
6944 { "(bad)", { XX } },
6945 { "(bad)", { XX } },
6946 { "(bad)", { XX } },
6947 { "(bad)", { XX } },
6948 { "(bad)", { XX } },
6949 { "(bad)", { XX } },
6950 { "(bad)", { XX } },
6951 /* 08 */
6952 { "(bad)", { XX } },
6953 { "(bad)", { XX } },
6954 { "(bad)", { XX } },
6955 { "(bad)", { XX } },
6956 { "(bad)", { XX } },
6957 { "(bad)", { XX } },
6958 { "(bad)", { XX } },
6959 { "(bad)", { XX } },
6960 /* 10 */
6961 { "(bad)", { XX } },
6962 { "(bad)", { XX } },
6963 { REG_TABLE (REG_XOP_LWPCB) },
6964 { "(bad)", { XX } },
6965 { "(bad)", { XX } },
6966 { "(bad)", { XX } },
6967 { "(bad)", { XX } },
6968 { "(bad)", { XX } },
6969 /* 18 */
6970 { "(bad)", { XX } },
6971 { "(bad)", { XX } },
6972 { "(bad)", { XX } },
6973 { "(bad)", { XX } },
6974 { "(bad)", { XX } },
6975 { "(bad)", { XX } },
6976 { "(bad)", { XX } },
6977 { "(bad)", { XX } },
6978 /* 20 */
4e7d34a6
L		 6979 { "(bad)", { XX } },
6980 { "(bad)", { XX } },
6981 { "(bad)", { XX } },
f88c9eb0 6982 { "(bad)", { XX } },
4e7d34a6
L		 6983 { "(bad)", { XX } },
6984 { "(bad)", { XX } },
6985 { "(bad)", { XX } },
6986 { "(bad)", { XX } },
5dd85c99
SP		 6987 /* 28 */
6988 { "(bad)", { XX } },
6989 { "(bad)", { XX } },
6990 { "(bad)", { XX } },
6991 { "(bad)", { XX } },
6992 { "(bad)", { XX } },
6993 { "(bad)", { XX } },
6994 { "(bad)", { XX } },
6995 { "(bad)", { XX } },
6996 /* 30 */
6997 { "(bad)", { XX } },
6998 { "(bad)", { XX } },
6999 { "(bad)", { XX } },
7000 { "(bad)", { XX } },
7001 { "(bad)", { XX } },
7002 { "(bad)", { XX } },
7003 { "(bad)", { XX } },
7004 { "(bad)", { XX } },
7005 /* 38 */
7006 { "(bad)", { XX } },
7007 { "(bad)", { XX } },
7008 { "(bad)", { XX } },
7009 { "(bad)", { XX } },
7010 { "(bad)", { XX } },
7011 { "(bad)", { XX } },
7012 { "(bad)", { XX } },
7013 { "(bad)", { XX } },
7014 /* 40 */
7015 { "(bad)", { XX } },
7016 { "(bad)", { XX } },
7017 { "(bad)", { XX } },
7018 { "(bad)", { XX } },
7019 { "(bad)", { XX } },
7020 { "(bad)", { XX } },
7021 { "(bad)", { XX } },
7022 { "(bad)", { XX } },
7023 /* 48 */
7024 { "(bad)", { XX } },
7025 { "(bad)", { XX } },
7026 { "(bad)", { XX } },
7027 { "(bad)", { XX } },
7028 { "(bad)", { XX } },
7029 { "(bad)", { XX } },
7030 { "(bad)", { XX } },
7031 { "(bad)", { XX } },
7032 /* 50 */
7033 { "(bad)", { XX } },
7034 { "(bad)", { XX } },
7035 { "(bad)", { XX } },
7036 { "(bad)", { XX } },
7037 { "(bad)", { XX } },
7038 { "(bad)", { XX } },
7039 { "(bad)", { XX } },
7040 { "(bad)", { XX } },
7041 /* 58 */
7042 { "(bad)", { XX } },
7043 { "(bad)", { XX } },
7044 { "(bad)", { XX } },
7045 { "(bad)", { XX } },
7046 { "(bad)", { XX } },
7047 { "(bad)", { XX } },
7048 { "(bad)", { XX } },
7049 { "(bad)", { XX } },
7050 /* 60 */
7051 { "(bad)", { XX } },
7052 { "(bad)", { XX } },
7053 { "(bad)", { XX } },
7054 { "(bad)", { XX } },
7055 { "(bad)", { XX } },
7056 { "(bad)", { XX } },
7057 { "(bad)", { XX } },
7058 { "(bad)", { XX } },
7059 /* 68 */
7060 { "(bad)", { XX } },
7061 { "(bad)", { XX } },
7062 { "(bad)", { XX } },
7063 { "(bad)", { XX } },
7064 { "(bad)", { XX } },
7065 { "(bad)", { XX } },
7066 { "(bad)", { XX } },
7067 { "(bad)", { XX } },
7068 /* 70 */
7069 { "(bad)", { XX } },
7070 { "(bad)", { XX } },
7071 { "(bad)", { XX } },
7072 { "(bad)", { XX } },
7073 { "(bad)", { XX } },
7074 { "(bad)", { XX } },
7075 { "(bad)", { XX } },
7076 { "(bad)", { XX } },
7077 /* 78 */
7078 { "(bad)", { XX } },
7079 { "(bad)", { XX } },
7080 { "(bad)", { XX } },
7081 { "(bad)", { XX } },
7082 { "(bad)", { XX } },
7083 { "(bad)", { XX } },
7084 { "(bad)", { XX } },
7085 { "(bad)", { XX } },
7086 /* 80 */
7087 { VEX_LEN_TABLE (VEX_LEN_XOP_09_80) },
7088 { VEX_LEN_TABLE (VEX_LEN_XOP_09_81) },
7089 { "vfrczss", { XM, EXd } },
7090 { "vfrczsd", { XM, EXq } },
7091 { "(bad)", { XX } },
7092 { "(bad)", { XX } },
7093 { "(bad)", { XX } },
7094 { "(bad)", { XX } },
7095 /* 88 */
7096 { "(bad)", { XX } },
7097 { "(bad)", { XX } },
7098 { "(bad)", { XX } },
7099 { "(bad)", { XX } },
7100 { "(bad)", { XX } },
7101 { "(bad)", { XX } },
7102 { "(bad)", { XX } },
7103 { "(bad)", { XX } },
7104 /* 90 */
7105 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } },
7106 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } },
7107 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } },
7108 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } },
7109 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } },
7110 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } },
7111 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } },
7112 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } },
7113 /* 98 */
7114 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } },
7115 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } },
7116 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } },
7117 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } },
7118 { "(bad)", { XX } },
7119 { "(bad)", { XX } },
7120 { "(bad)", { XX } },
7121 { "(bad)", { XX } },
7122 /* a0 */
7123 { "(bad)", { XX } },
7124 { "(bad)", { XX } },
7125 { "(bad)", { XX } },
7126 { "(bad)", { XX } },
7127 { "(bad)", { XX } },
7128 { "(bad)", { XX } },
7129 { "(bad)", { XX } },
7130 { "(bad)", { XX } },
7131 /* a8 */
7132 { "(bad)", { XX } },
7133 { "(bad)", { XX } },
7134 { "(bad)", { XX } },
7135 { "(bad)", { XX } },
7136 { "(bad)", { XX } },
7137 { "(bad)", { XX } },
7138 { "(bad)", { XX } },
7139 { "(bad)", { XX } },
7140 /* b0 */
7141 { "(bad)", { XX } },
7142 { "(bad)", { XX } },
7143 { "(bad)", { XX } },
7144 { "(bad)", { XX } },
7145 { "(bad)", { XX } },
7146 { "(bad)", { XX } },
7147 { "(bad)", { XX } },
7148 { "(bad)", { XX } },
7149 /* b8 */
7150 { "(bad)", { XX } },
7151 { "(bad)", { XX } },
7152 { "(bad)", { XX } },
7153 { "(bad)", { XX } },
7154 { "(bad)", { XX } },
7155 { "(bad)", { XX } },
7156 { "(bad)", { XX } },
7157 { "(bad)", { XX } },
7158 /* c0 */
7159 { "(bad)", { XX } },
7160 { "vphaddbw", { XM, EXxmm } },
7161 { "vphaddbd", { XM, EXxmm } },
7162 { "vphaddbq", { XM, EXxmm } },
7163 { "(bad)", { XX } },
7164 { "(bad)", { XX } },
7165 { "vphaddwd", { XM, EXxmm } },
7166 { "vphaddwq", { XM, EXxmm } },
7167 /* c8 */
7168 { "(bad)", { XX } },
7169 { "(bad)", { XX } },
7170 { "(bad)", { XX } },
7171 { "vphadddq", { XM, EXxmm } },
7172 { "(bad)", { XX } },
7173 { "(bad)", { XX } },
7174 { "(bad)", { XX } },
7175 { "(bad)", { XX } },
7176 /* d0 */
7177 { "(bad)", { XX } },
7178 { "vphaddubw", { XM, EXxmm } },
7179 { "vphaddubd", { XM, EXxmm } },
7180 { "vphaddubq", { XM, EXxmm } },
7181 { "(bad)", { XX } },
7182 { "(bad)", { XX } },
7183 { "vphadduwd", { XM, EXxmm } },
7184 { "vphadduwq", { XM, EXxmm } },
7185 /* d8 */
7186 { "(bad)", { XX } },
7187 { "(bad)", { XX } },
7188 { "(bad)", { XX } },
7189 { "vphaddudq", { XM, EXxmm } },
7190 { "(bad)", { XX } },
7191 { "(bad)", { XX } },
7192 { "(bad)", { XX } },
7193 { "(bad)", { XX } },
7194 /* e0 */
7195 { "(bad)", { XX } },
7196 { "vphsubbw", { XM, EXxmm } },
7197 { "vphsubwd", { XM, EXxmm } },
7198 { "vphsubdq", { XM, EXxmm } },
4e7d34a6
L		 7199 { "(bad)", { XX } },
7200 { "(bad)", { XX } },
7201 { "(bad)", { XX } },
7202 { "(bad)", { XX } },
7203 /* e8 */
7204 { "(bad)", { XX } },
7205 { "(bad)", { XX } },
7206 { "(bad)", { XX } },
7207 { "(bad)", { XX } },
7208 { "(bad)", { XX } },
7209 { "(bad)", { XX } },
7210 { "(bad)", { XX } },
7211 { "(bad)", { XX } },
7212 /* f0 */
7213 { "(bad)", { XX } },
7214 { "(bad)", { XX } },
7215 { "(bad)", { XX } },
7216 { "(bad)", { XX } },
7217 { "(bad)", { XX } },
7218 { "(bad)", { XX } },
7219 { "(bad)", { XX } },
7220 { "(bad)", { XX } },
7221 /* f8 */
7222 { "(bad)", { XX } },
7223 { "(bad)", { XX } },
7224 { "(bad)", { XX } },
7225 { "(bad)", { XX } },
7226 { "(bad)", { XX } },
7227 { "(bad)", { XX } },
7228 { "(bad)", { XX } },
7229 { "(bad)", { XX } },
7230 },
f88c9eb0 7231 /* XOP_0A */
4e7d34a6
L		 7232 {
7233 /* 00 */
c0f3af97
L		 7234 { "(bad)", { XX } },
7235 { "(bad)", { XX } },
7236 { "(bad)", { XX } },
7237 { "(bad)", { XX } },
7238 { "(bad)", { XX } },
7239 { "(bad)", { XX } },
7240 { "(bad)", { XX } },
7241 { "(bad)", { XX } },
4e7d34a6 7242 /* 08 */
c0f3af97
L		 7243 { "(bad)", { XX } },
7244 { "(bad)", { XX } },
7245 { "(bad)", { XX } },
7246 { "(bad)", { XX } },
d5d7db8e
L		 7247 { "(bad)", { XX } },
7248 { "(bad)", { XX } },
7249 { "(bad)", { XX } },
7250 { "(bad)", { XX } },
4e7d34a6 7251 /* 10 */
d5d7db8e
L		 7252 { "(bad)", { XX } },
7253 { "(bad)", { XX } },
f88c9eb0 7254 { REG_TABLE (REG_XOP_LWP) },
d5d7db8e 7255 { "(bad)", { XX } },
c0f3af97
L		 7256 { "(bad)", { XX } },
7257 { "(bad)", { XX } },
7258 { "(bad)", { XX } },
7259 { "(bad)", { XX } },
4e7d34a6 7260 /* 18 */
d5d7db8e
L		 7261 { "(bad)", { XX } },
7262 { "(bad)", { XX } },
7263 { "(bad)", { XX } },
7264 { "(bad)", { XX } },
c0f3af97
L		 7265 { "(bad)", { XX } },
7266 { "(bad)", { XX } },
7267 { "(bad)", { XX } },
d5d7db8e 7268 { "(bad)", { XX } },
4e7d34a6 7269 /* 20 */
f88c9eb0 7270 { "(bad)", { XX } },
c0f3af97
L		 7271 { "(bad)", { XX } },
7272 { "(bad)", { XX } },
7273 { "(bad)", { XX } },
7274 { "(bad)", { XX } },
7275 { "(bad)", { XX } },
d5d7db8e
L		 7276 { "(bad)", { XX } },
7277 { "(bad)", { XX } },
4e7d34a6 7278 /* 28 */
c0f3af97
L		 7279 { "(bad)", { XX } },
7280 { "(bad)", { XX } },
7281 { "(bad)", { XX } },
7282 { "(bad)", { XX } },
d5d7db8e
L		 7283 { "(bad)", { XX } },
7284 { "(bad)", { XX } },
7285 { "(bad)", { XX } },
7286 { "(bad)", { XX } },
4e7d34a6 7287 /* 30 */
d5d7db8e 7288 { "(bad)", { XX } },
d5d7db8e
L		 7289 { "(bad)", { XX } },
7290 { "(bad)", { XX } },
7291 { "(bad)", { XX } },
7292 { "(bad)", { XX } },
7293 { "(bad)", { XX } },
7294 { "(bad)", { XX } },
c0f3af97
L		 7295 { "(bad)", { XX } },
7296 /* 38 */
7297 { "(bad)", { XX } },
7298 { "(bad)", { XX } },
7299 { "(bad)", { XX } },
7300 { "(bad)", { XX } },
d5d7db8e
L		 7301 { "(bad)", { XX } },
7302 { "(bad)", { XX } },
7303 { "(bad)", { XX } },
7304 { "(bad)", { XX } },
c0f3af97 7305 /* 40 */
c1e679ec 7306 { "(bad)", { XX } },
d5d7db8e
L		 7307 { "(bad)", { XX } },
7308 { "(bad)", { XX } },
f88c9eb0
SP		 7309 { "(bad)", { XX } },
7310 { "(bad)", { XX } },
7311 { "(bad)", { XX } },
7312 { "(bad)", { XX } },
7313 { "(bad)", { XX } },
c1e679ec 7314 /* 48 */
d5d7db8e
L		 7315 { "(bad)", { XX } },
7316 { "(bad)", { XX } },
d5d7db8e 7317 { "(bad)", { XX } },
f88c9eb0 7318 { "(bad)", { XX } },
d5d7db8e
L		 7319 { "(bad)", { XX } },
7320 { "(bad)", { XX } },
7321 { "(bad)", { XX } },
7322 { "(bad)", { XX } },
c1e679ec 7323 /* 50 */
d5d7db8e
L		 7324 { "(bad)", { XX } },
7325 { "(bad)", { XX } },
7326 { "(bad)", { XX } },
f88c9eb0
SP		 7327 { "(bad)", { XX } },
7328 { "(bad)", { XX } },
7329 { "(bad)", { XX } },
7330 { "(bad)", { XX } },
7331 { "(bad)", { XX } },
4e7d34a6 7332 /* 58 */
d5d7db8e
L		 7333 { "(bad)", { XX } },
7334 { "(bad)", { XX } },
7335 { "(bad)", { XX } },
f88c9eb0 7336 { "(bad)", { XX } },
d5d7db8e
L		 7337 { "(bad)", { XX } },
7338 { "(bad)", { XX } },
7339 { "(bad)", { XX } },
7340 { "(bad)", { XX } },
4e7d34a6 7341 /* 60 */
d5d7db8e 7342 { "(bad)", { XX } },
f88c9eb0
SP		 7343 { "(bad)", { XX } },
7344 { "(bad)", { XX } },
7345 { "(bad)", { XX } },
d5d7db8e
L		 7346 { "(bad)", { XX } },
7347 { "(bad)", { XX } },
7348 { "(bad)", { XX } },
7349 { "(bad)", { XX } },
4e7d34a6 7350 /* 68 */
d5d7db8e
L		 7351 { "(bad)", { XX } },
7352 { "(bad)", { XX } },
7353 { "(bad)", { XX } },
7354 { "(bad)", { XX } },
7355 { "(bad)", { XX } },
7356 { "(bad)", { XX } },
7357 { "(bad)", { XX } },
7358 { "(bad)", { XX } },
4e7d34a6 7359 /* 70 */
d5d7db8e
L		 7360 { "(bad)", { XX } },
7361 { "(bad)", { XX } },
7362 { "(bad)", { XX } },
7363 { "(bad)", { XX } },
7364 { "(bad)", { XX } },
7365 { "(bad)", { XX } },
7366 { "(bad)", { XX } },
7367 { "(bad)", { XX } },
4e7d34a6 7368 /* 78 */
d5d7db8e
L		 7369 { "(bad)", { XX } },
7370 { "(bad)", { XX } },
7371 { "(bad)", { XX } },
7372 { "(bad)", { XX } },
7373 { "(bad)", { XX } },
7374 { "(bad)", { XX } },
7375 { "(bad)", { XX } },
7376 { "(bad)", { XX } },
4e7d34a6 7377 /* 80 */
d5d7db8e
L		 7378 { "(bad)", { XX } },
7379 { "(bad)", { XX } },
7380 { "(bad)", { XX } },
7381 { "(bad)", { XX } },
7382 { "(bad)", { XX } },
7383 { "(bad)", { XX } },
7384 { "(bad)", { XX } },
7385 { "(bad)", { XX } },
4e7d34a6 7386 /* 88 */
d5d7db8e
L		 7387 { "(bad)", { XX } },
7388 { "(bad)", { XX } },
7389 { "(bad)", { XX } },
7390 { "(bad)", { XX } },
7391 { "(bad)", { XX } },
7392 { "(bad)", { XX } },
7393 { "(bad)", { XX } },
7394 { "(bad)", { XX } },
4e7d34a6 7395 /* 90 */
d5d7db8e
L		 7396 { "(bad)", { XX } },
7397 { "(bad)", { XX } },
7398 { "(bad)", { XX } },
7399 { "(bad)", { XX } },
7400 { "(bad)", { XX } },
7401 { "(bad)", { XX } },
7402 { "(bad)", { XX } },
7403 { "(bad)", { XX } },
4e7d34a6 7404 /* 98 */
d5d7db8e
L		 7405 { "(bad)", { XX } },
7406 { "(bad)", { XX } },
7407 { "(bad)", { XX } },
7408 { "(bad)", { XX } },
7409 { "(bad)", { XX } },
7410 { "(bad)", { XX } },
7411 { "(bad)", { XX } },
7412 { "(bad)", { XX } },
4e7d34a6 7413 /* a0 */
d5d7db8e
L		 7414 { "(bad)", { XX } },
7415 { "(bad)", { XX } },
7416 { "(bad)", { XX } },
7417 { "(bad)", { XX } },
7418 { "(bad)", { XX } },
7419 { "(bad)", { XX } },
7420 { "(bad)", { XX } },
7421 { "(bad)", { XX } },
4e7d34a6 7422 /* a8 */
d5d7db8e
L		 7423 { "(bad)", { XX } },
7424 { "(bad)", { XX } },
7425 { "(bad)", { XX } },
7426 { "(bad)", { XX } },
7427 { "(bad)", { XX } },
7428 { "(bad)", { XX } },
7429 { "(bad)", { XX } },
7430 { "(bad)", { XX } },
7431 /* b0 */
7432 { "(bad)", { XX } },
7433 { "(bad)", { XX } },
7434 { "(bad)", { XX } },
7435 { "(bad)", { XX } },
7436 { "(bad)", { XX } },
7437 { "(bad)", { XX } },
7438 { "(bad)", { XX } },
7439 { "(bad)", { XX } },
85f10a01 7440 /* b8 */
d5d7db8e
L		 7441 { "(bad)", { XX } },
7442 { "(bad)", { XX } },
7443 { "(bad)", { XX } },
7444 { "(bad)", { XX } },
7445 { "(bad)", { XX } },
7446 { "(bad)", { XX } },
7447 { "(bad)", { XX } },
7448 { "(bad)", { XX } },
85f10a01 7449 /* c0 */
d5d7db8e
L		 7450 { "(bad)", { XX } },
7451 { "(bad)", { XX } },
7452 { "(bad)", { XX } },
7453 { "(bad)", { XX } },
7454 { "(bad)", { XX } },
7455 { "(bad)", { XX } },
7456 { "(bad)", { XX } },
7457 { "(bad)", { XX } },
85f10a01 7458 /* c8 */
d5d7db8e
L		 7459 { "(bad)", { XX } },
7460 { "(bad)", { XX } },
7461 { "(bad)", { XX } },
7462 { "(bad)", { XX } },
7463 { "(bad)", { XX } },
7464 { "(bad)", { XX } },
7465 { "(bad)", { XX } },
7466 { "(bad)", { XX } },
85f10a01 7467 /* d0 */
d5d7db8e
L		 7468 { "(bad)", { XX } },
7469 { "(bad)", { XX } },
7470 { "(bad)", { XX } },
7471 { "(bad)", { XX } },
7472 { "(bad)", { XX } },
7473 { "(bad)", { XX } },
7474 { "(bad)", { XX } },
7475 { "(bad)", { XX } },
85f10a01 7476 /* d8 */
d5d7db8e
L		 7477 { "(bad)", { XX } },
7478 { "(bad)", { XX } },
7479 { "(bad)", { XX } },
7480 { "(bad)", { XX } },
7481 { "(bad)", { XX } },
7482 { "(bad)", { XX } },
7483 { "(bad)", { XX } },
7484 { "(bad)", { XX } },
85f10a01 7485 /* e0 */
d5d7db8e
L		 7486 { "(bad)", { XX } },
7487 { "(bad)", { XX } },
7488 { "(bad)", { XX } },
7489 { "(bad)", { XX } },
7490 { "(bad)", { XX } },
7491 { "(bad)", { XX } },
7492 { "(bad)", { XX } },
7493 { "(bad)", { XX } },
85f10a01 7494 /* e8 */
d5d7db8e
L		 7495 { "(bad)", { XX } },
7496 { "(bad)", { XX } },
7497 { "(bad)", { XX } },
7498 { "(bad)", { XX } },
7499 { "(bad)", { XX } },
7500 { "(bad)", { XX } },
7501 { "(bad)", { XX } },
7502 { "(bad)", { XX } },
85f10a01 7503 /* f0 */
c0f3af97
L		 7504 { "(bad)", { XX } },
7505 { "(bad)", { XX } },
d5d7db8e
L		 7506 { "(bad)", { XX } },
7507 { "(bad)", { XX } },
7508 { "(bad)", { XX } },
7509 { "(bad)", { XX } },
7510 { "(bad)", { XX } },
7511 { "(bad)", { XX } },
85f10a01 7512 /* f8 */
d5d7db8e
L		 7513 { "(bad)", { XX } },
7514 { "(bad)", { XX } },
7515 { "(bad)", { XX } },
7516 { "(bad)", { XX } },
7517 { "(bad)", { XX } },
7518 { "(bad)", { XX } },
7519 { "(bad)", { XX } },
7520 { "(bad)", { XX } },
85f10a01 7521 },
c0f3af97
L		 7522};
7523
7524static const struct dis386 vex_table[][256] = {
7525 /* VEX_0F */
85f10a01
MM		 7526 {
7527 /* 00 */
d5d7db8e
L		 7528 { "(bad)", { XX } },
7529 { "(bad)", { XX } },
7530 { "(bad)", { XX } },
7531 { "(bad)", { XX } },
7532 { "(bad)", { XX } },
7533 { "(bad)", { XX } },
7534 { "(bad)", { XX } },
7535 { "(bad)", { XX } },
85f10a01 7536 /* 08 */
d5d7db8e
L		 7537 { "(bad)", { XX } },
7538 { "(bad)", { XX } },
7539 { "(bad)", { XX } },
7540 { "(bad)", { XX } },
d5d7db8e
L		 7541 { "(bad)", { XX } },
7542 { "(bad)", { XX } },
7543 { "(bad)", { XX } },
7544 { "(bad)", { XX } },
c0f3af97
L		 7545 /* 10 */
7546 { PREFIX_TABLE (PREFIX_VEX_10) },
7547 { PREFIX_TABLE (PREFIX_VEX_11) },
7548 { PREFIX_TABLE (PREFIX_VEX_12) },
7549 { MOD_TABLE (MOD_VEX_13) },
9e30b8e0
L		 7550 { VEX_W_TABLE (VEX_W_14) },
7551 { VEX_W_TABLE (VEX_W_15) },
c0f3af97
L		 7552 { PREFIX_TABLE (PREFIX_VEX_16) },
7553 { MOD_TABLE (MOD_VEX_17) },
7554 /* 18 */
d5d7db8e
L		 7555 { "(bad)", { XX } },
7556 { "(bad)", { XX } },
7557 { "(bad)", { XX } },
d5d7db8e
L		 7558 { "(bad)", { XX } },
7559 { "(bad)", { XX } },
7560 { "(bad)", { XX } },
7561 { "(bad)", { XX } },
7562 { "(bad)", { XX } },
c0f3af97 7563 /* 20 */
d5d7db8e
L		 7564 { "(bad)", { XX } },
7565 { "(bad)", { XX } },
7566 { "(bad)", { XX } },
7567 { "(bad)", { XX } },
7568 { "(bad)", { XX } },
7569 { "(bad)", { XX } },
7570 { "(bad)", { XX } },
7571 { "(bad)", { XX } },
c0f3af97 7572 /* 28 */
9e30b8e0
L		 7573 { VEX_W_TABLE (VEX_W_28) },
7574 { VEX_W_TABLE (VEX_W_29) },
c0f3af97
L		 7575 { PREFIX_TABLE (PREFIX_VEX_2A) },
7576 { MOD_TABLE (MOD_VEX_2B) },
7577 { PREFIX_TABLE (PREFIX_VEX_2C) },
7578 { PREFIX_TABLE (PREFIX_VEX_2D) },
7579 { PREFIX_TABLE (PREFIX_VEX_2E) },
7580 { PREFIX_TABLE (PREFIX_VEX_2F) },
85f10a01 7581 /* 30 */
d5d7db8e
L		 7582 { "(bad)", { XX } },
7583 { "(bad)", { XX } },
7584 { "(bad)", { XX } },
7585 { "(bad)", { XX } },
7586 { "(bad)", { XX } },
7587 { "(bad)", { XX } },
7588 { "(bad)", { XX } },
7589 { "(bad)", { XX } },
4e7d34a6 7590 /* 38 */
d5d7db8e
L		 7591 { "(bad)", { XX } },
7592 { "(bad)", { XX } },
7593 { "(bad)", { XX } },
7594 { "(bad)", { XX } },
7595 { "(bad)", { XX } },
7596 { "(bad)", { XX } },
7597 { "(bad)", { XX } },
7598 { "(bad)", { XX } },
7599 /* 40 */
c0f3af97
L		 7600 { "(bad)", { XX } },
7601 { "(bad)", { XX } },
7602 { "(bad)", { XX } },
d5d7db8e
L		 7603 { "(bad)", { XX } },
7604 { "(bad)", { XX } },
7605 { "(bad)", { XX } },
7606 { "(bad)", { XX } },
7607 { "(bad)", { XX } },
85f10a01 7608 /* 48 */
85f10a01
MM		 7609 { "(bad)", { XX } },
7610 { "(bad)", { XX } },
7611 { "(bad)", { XX } },
7612 { "(bad)", { XX } },
7613 { "(bad)", { XX } },
7614 { "(bad)", { XX } },
7615 { "(bad)", { XX } },
7616 { "(bad)", { XX } },
d5d7db8e 7617 /* 50 */
976f1fde 7618 { MOD_TABLE (MOD_VEX_50) },
c0f3af97
L		 7619 { PREFIX_TABLE (PREFIX_VEX_51) },
7620 { PREFIX_TABLE (PREFIX_VEX_52) },
7621 { PREFIX_TABLE (PREFIX_VEX_53) },
7622 { "vandpX", { XM, Vex, EXx } },
7623 { "vandnpX", { XM, Vex, EXx } },
7624 { "vorpX", { XM, Vex, EXx } },
7625 { "vxorpX", { XM, Vex, EXx } },
7626 /* 58 */
7627 { PREFIX_TABLE (PREFIX_VEX_58) },
7628 { PREFIX_TABLE (PREFIX_VEX_59) },
7629 { PREFIX_TABLE (PREFIX_VEX_5A) },
7630 { PREFIX_TABLE (PREFIX_VEX_5B) },
7631 { PREFIX_TABLE (PREFIX_VEX_5C) },
7632 { PREFIX_TABLE (PREFIX_VEX_5D) },
7633 { PREFIX_TABLE (PREFIX_VEX_5E) },
7634 { PREFIX_TABLE (PREFIX_VEX_5F) },
7635 /* 60 */
7636 { PREFIX_TABLE (PREFIX_VEX_60) },
7637 { PREFIX_TABLE (PREFIX_VEX_61) },
7638 { PREFIX_TABLE (PREFIX_VEX_62) },
7639 { PREFIX_TABLE (PREFIX_VEX_63) },
7640 { PREFIX_TABLE (PREFIX_VEX_64) },
7641 { PREFIX_TABLE (PREFIX_VEX_65) },
7642 { PREFIX_TABLE (PREFIX_VEX_66) },
7643 { PREFIX_TABLE (PREFIX_VEX_67) },
7644 /* 68 */
7645 { PREFIX_TABLE (PREFIX_VEX_68) },
7646 { PREFIX_TABLE (PREFIX_VEX_69) },
7647 { PREFIX_TABLE (PREFIX_VEX_6A) },
7648 { PREFIX_TABLE (PREFIX_VEX_6B) },
7649 { PREFIX_TABLE (PREFIX_VEX_6C) },
7650 { PREFIX_TABLE (PREFIX_VEX_6D) },
7651 { PREFIX_TABLE (PREFIX_VEX_6E) },
7652 { PREFIX_TABLE (PREFIX_VEX_6F) },
7653 /* 70 */
7654 { PREFIX_TABLE (PREFIX_VEX_70) },
7655 { REG_TABLE (REG_VEX_71) },
7656 { REG_TABLE (REG_VEX_72) },
7657 { REG_TABLE (REG_VEX_73) },
7658 { PREFIX_TABLE (PREFIX_VEX_74) },
7659 { PREFIX_TABLE (PREFIX_VEX_75) },
7660 { PREFIX_TABLE (PREFIX_VEX_76) },
7661 { PREFIX_TABLE (PREFIX_VEX_77) },
7662 /* 78 */
85f10a01
MM		 7663 { "(bad)", { XX } },
7664 { "(bad)", { XX } },
7665 { "(bad)", { XX } },
7666 { "(bad)", { XX } },
c0f3af97
L		 7667 { PREFIX_TABLE (PREFIX_VEX_7C) },
7668 { PREFIX_TABLE (PREFIX_VEX_7D) },
7669 { PREFIX_TABLE (PREFIX_VEX_7E) },
7670 { PREFIX_TABLE (PREFIX_VEX_7F) },
7671 /* 80 */
85f10a01
MM		 7672 { "(bad)", { XX } },
7673 { "(bad)", { XX } },
7674 { "(bad)", { XX } },
7675 { "(bad)", { XX } },
85f10a01
MM		 7676 { "(bad)", { XX } },
7677 { "(bad)", { XX } },
7678 { "(bad)", { XX } },
7679 { "(bad)", { XX } },
c0f3af97 7680 /* 88 */
85f10a01
MM		 7681 { "(bad)", { XX } },
7682 { "(bad)", { XX } },
7683 { "(bad)", { XX } },
7684 { "(bad)", { XX } },
7685 { "(bad)", { XX } },
7686 { "(bad)", { XX } },
7687 { "(bad)", { XX } },
7688 { "(bad)", { XX } },
c0f3af97 7689 /* 90 */
85f10a01
MM		 7690 { "(bad)", { XX } },
7691 { "(bad)", { XX } },
7692 { "(bad)", { XX } },
7693 { "(bad)", { XX } },
7694 { "(bad)", { XX } },
7695 { "(bad)", { XX } },
7696 { "(bad)", { XX } },
85f10a01 7697 { "(bad)", { XX } },
c0f3af97 7698 /* 98 */
85f10a01
MM		 7699 { "(bad)", { XX } },
7700 { "(bad)", { XX } },
7701 { "(bad)", { XX } },
d5d7db8e
L		 7702 { "(bad)", { XX } },
7703 { "(bad)", { XX } },
7704 { "(bad)", { XX } },
7705 { "(bad)", { XX } },
7706 { "(bad)", { XX } },
c0f3af97 7707 /* a0 */
d5d7db8e
L		 7708 { "(bad)", { XX } },
7709 { "(bad)", { XX } },
7710 { "(bad)", { XX } },
7711 { "(bad)", { XX } },
7712 { "(bad)", { XX } },
7713 { "(bad)", { XX } },
7714 { "(bad)", { XX } },
7715 { "(bad)", { XX } },
c0f3af97 7716 /* a8 */
d5d7db8e
L		 7717 { "(bad)", { XX } },
7718 { "(bad)", { XX } },
7719 { "(bad)", { XX } },
7720 { "(bad)", { XX } },
7721 { "(bad)", { XX } },
7722 { "(bad)", { XX } },
c0f3af97 7723 { REG_TABLE (REG_VEX_AE) },
d5d7db8e 7724 { "(bad)", { XX } },
c0f3af97 7725 /* b0 */
d5d7db8e 7726 { "(bad)", { XX } },
d5d7db8e
L		 7727 { "(bad)", { XX } },
7728 { "(bad)", { XX } },
7729 { "(bad)", { XX } },
7730 { "(bad)", { XX } },
7731 { "(bad)", { XX } },
7732 { "(bad)", { XX } },
7733 { "(bad)", { XX } },
c0f3af97 7734 /* b8 */
d5d7db8e 7735 { "(bad)", { XX } },
d5d7db8e
L		 7736 { "(bad)", { XX } },
7737 { "(bad)", { XX } },
7738 { "(bad)", { XX } },
7739 { "(bad)", { XX } },
7740 { "(bad)", { XX } },
7741 { "(bad)", { XX } },
7742 { "(bad)", { XX } },
c0f3af97 7743 /* c0 */
d5d7db8e 7744 { "(bad)", { XX } },
d5d7db8e 7745 { "(bad)", { XX } },
c0f3af97 7746 { PREFIX_TABLE (PREFIX_VEX_C2) },
d5d7db8e 7747 { "(bad)", { XX } },
c0f3af97
L		 7748 { PREFIX_TABLE (PREFIX_VEX_C4) },
7749 { PREFIX_TABLE (PREFIX_VEX_C5) },
7750 { "vshufpX", { XM, Vex, EXx, Ib } },
d5d7db8e 7751 { "(bad)", { XX } },
c0f3af97 7752 /* c8 */
d5d7db8e
L		 7753 { "(bad)", { XX } },
7754 { "(bad)", { XX } },
7755 { "(bad)", { XX } },
7756 { "(bad)", { XX } },
7757 { "(bad)", { XX } },
d5d7db8e
L		 7758 { "(bad)", { XX } },
7759 { "(bad)", { XX } },
7760 { "(bad)", { XX } },
c0f3af97
L		 7761 /* d0 */
7762 { PREFIX_TABLE (PREFIX_VEX_D0) },
7763 { PREFIX_TABLE (PREFIX_VEX_D1) },
7764 { PREFIX_TABLE (PREFIX_VEX_D2) },
7765 { PREFIX_TABLE (PREFIX_VEX_D3) },
7766 { PREFIX_TABLE (PREFIX_VEX_D4) },
7767 { PREFIX_TABLE (PREFIX_VEX_D5) },
7768 { PREFIX_TABLE (PREFIX_VEX_D6) },
7769 { PREFIX_TABLE (PREFIX_VEX_D7) },
7770 /* d8 */
7771 { PREFIX_TABLE (PREFIX_VEX_D8) },
7772 { PREFIX_TABLE (PREFIX_VEX_D9) },
7773 { PREFIX_TABLE (PREFIX_VEX_DA) },
7774 { PREFIX_TABLE (PREFIX_VEX_DB) },
7775 { PREFIX_TABLE (PREFIX_VEX_DC) },
7776 { PREFIX_TABLE (PREFIX_VEX_DD) },
7777 { PREFIX_TABLE (PREFIX_VEX_DE) },
7778 { PREFIX_TABLE (PREFIX_VEX_DF) },
7779 /* e0 */
7780 { PREFIX_TABLE (PREFIX_VEX_E0) },
7781 { PREFIX_TABLE (PREFIX_VEX_E1) },
7782 { PREFIX_TABLE (PREFIX_VEX_E2) },
7783 { PREFIX_TABLE (PREFIX_VEX_E3) },
7784 { PREFIX_TABLE (PREFIX_VEX_E4) },
7785 { PREFIX_TABLE (PREFIX_VEX_E5) },
7786 { PREFIX_TABLE (PREFIX_VEX_E6) },
7787 { PREFIX_TABLE (PREFIX_VEX_E7) },
7788 /* e8 */
7789 { PREFIX_TABLE (PREFIX_VEX_E8) },
7790 { PREFIX_TABLE (PREFIX_VEX_E9) },
7791 { PREFIX_TABLE (PREFIX_VEX_EA) },
7792 { PREFIX_TABLE (PREFIX_VEX_EB) },
7793 { PREFIX_TABLE (PREFIX_VEX_EC) },
7794 { PREFIX_TABLE (PREFIX_VEX_ED) },
7795 { PREFIX_TABLE (PREFIX_VEX_EE) },
7796 { PREFIX_TABLE (PREFIX_VEX_EF) },
7797 /* f0 */
7798 { PREFIX_TABLE (PREFIX_VEX_F0) },
7799 { PREFIX_TABLE (PREFIX_VEX_F1) },
7800 { PREFIX_TABLE (PREFIX_VEX_F2) },
7801 { PREFIX_TABLE (PREFIX_VEX_F3) },
7802 { PREFIX_TABLE (PREFIX_VEX_F4) },
7803 { PREFIX_TABLE (PREFIX_VEX_F5) },
7804 { PREFIX_TABLE (PREFIX_VEX_F6) },
7805 { PREFIX_TABLE (PREFIX_VEX_F7) },
7806 /* f8 */
7807 { PREFIX_TABLE (PREFIX_VEX_F8) },
7808 { PREFIX_TABLE (PREFIX_VEX_F9) },
7809 { PREFIX_TABLE (PREFIX_VEX_FA) },
7810 { PREFIX_TABLE (PREFIX_VEX_FB) },
7811 { PREFIX_TABLE (PREFIX_VEX_FC) },
7812 { PREFIX_TABLE (PREFIX_VEX_FD) },
7813 { PREFIX_TABLE (PREFIX_VEX_FE) },
d5d7db8e 7814 { "(bad)", { XX } },
c0f3af97
L		 7815 },
7816 /* VEX_0F38 */
7817 {
7818 /* 00 */
7819 { PREFIX_TABLE (PREFIX_VEX_3800) },
7820 { PREFIX_TABLE (PREFIX_VEX_3801) },
7821 { PREFIX_TABLE (PREFIX_VEX_3802) },
7822 { PREFIX_TABLE (PREFIX_VEX_3803) },
7823 { PREFIX_TABLE (PREFIX_VEX_3804) },
7824 { PREFIX_TABLE (PREFIX_VEX_3805) },
7825 { PREFIX_TABLE (PREFIX_VEX_3806) },
7826 { PREFIX_TABLE (PREFIX_VEX_3807) },
7827 /* 08 */
7828 { PREFIX_TABLE (PREFIX_VEX_3808) },
7829 { PREFIX_TABLE (PREFIX_VEX_3809) },
7830 { PREFIX_TABLE (PREFIX_VEX_380A) },
7831 { PREFIX_TABLE (PREFIX_VEX_380B) },
7832 { PREFIX_TABLE (PREFIX_VEX_380C) },
7833 { PREFIX_TABLE (PREFIX_VEX_380D) },
7834 { PREFIX_TABLE (PREFIX_VEX_380E) },
7835 { PREFIX_TABLE (PREFIX_VEX_380F) },
7836 /* 10 */
d5d7db8e
L		 7837 { "(bad)", { XX } },
7838 { "(bad)", { XX } },
7839 { "(bad)", { XX } },
7840 { "(bad)", { XX } },
d5d7db8e
L		 7841 { "(bad)", { XX } },
7842 { "(bad)", { XX } },
7843 { "(bad)", { XX } },
c0f3af97
L		 7844 { PREFIX_TABLE (PREFIX_VEX_3817) },
7845 /* 18 */
7846 { PREFIX_TABLE (PREFIX_VEX_3818) },
7847 { PREFIX_TABLE (PREFIX_VEX_3819) },
7848 { PREFIX_TABLE (PREFIX_VEX_381A) },
d5d7db8e 7849 { "(bad)", { XX } },
c0f3af97
L		 7850 { PREFIX_TABLE (PREFIX_VEX_381C) },
7851 { PREFIX_TABLE (PREFIX_VEX_381D) },
7852 { PREFIX_TABLE (PREFIX_VEX_381E) },
d5d7db8e 7853 { "(bad)", { XX } },
c0f3af97
L		 7854 /* 20 */
7855 { PREFIX_TABLE (PREFIX_VEX_3820) },
7856 { PREFIX_TABLE (PREFIX_VEX_3821) },
7857 { PREFIX_TABLE (PREFIX_VEX_3822) },
7858 { PREFIX_TABLE (PREFIX_VEX_3823) },
7859 { PREFIX_TABLE (PREFIX_VEX_3824) },
7860 { PREFIX_TABLE (PREFIX_VEX_3825) },
d5d7db8e
L		 7861 { "(bad)", { XX } },
7862 { "(bad)", { XX } },
c0f3af97
L		 7863 /* 28 */
7864 { PREFIX_TABLE (PREFIX_VEX_3828) },
7865 { PREFIX_TABLE (PREFIX_VEX_3829) },
7866 { PREFIX_TABLE (PREFIX_VEX_382A) },
7867 { PREFIX_TABLE (PREFIX_VEX_382B) },
7868 { PREFIX_TABLE (PREFIX_VEX_382C) },
7869 { PREFIX_TABLE (PREFIX_VEX_382D) },
7870 { PREFIX_TABLE (PREFIX_VEX_382E) },
7871 { PREFIX_TABLE (PREFIX_VEX_382F) },
7872 /* 30 */
7873 { PREFIX_TABLE (PREFIX_VEX_3830) },
7874 { PREFIX_TABLE (PREFIX_VEX_3831) },
7875 { PREFIX_TABLE (PREFIX_VEX_3832) },
7876 { PREFIX_TABLE (PREFIX_VEX_3833) },
7877 { PREFIX_TABLE (PREFIX_VEX_3834) },
7878 { PREFIX_TABLE (PREFIX_VEX_3835) },
7879 { "(bad)", { XX } },
7880 { PREFIX_TABLE (PREFIX_VEX_3837) },
7881 /* 38 */
7882 { PREFIX_TABLE (PREFIX_VEX_3838) },
7883 { PREFIX_TABLE (PREFIX_VEX_3839) },
7884 { PREFIX_TABLE (PREFIX_VEX_383A) },
7885 { PREFIX_TABLE (PREFIX_VEX_383B) },
7886 { PREFIX_TABLE (PREFIX_VEX_383C) },
7887 { PREFIX_TABLE (PREFIX_VEX_383D) },
7888 { PREFIX_TABLE (PREFIX_VEX_383E) },
7889 { PREFIX_TABLE (PREFIX_VEX_383F) },
7890 /* 40 */
7891 { PREFIX_TABLE (PREFIX_VEX_3840) },
7892 { PREFIX_TABLE (PREFIX_VEX_3841) },
d5d7db8e 7893 { "(bad)", { XX } },
d5d7db8e
L		 7894 { "(bad)", { XX } },
7895 { "(bad)", { XX } },
7896 { "(bad)", { XX } },
7897 { "(bad)", { XX } },
7898 { "(bad)", { XX } },
c0f3af97 7899 /* 48 */
d5d7db8e
L		 7900 { "(bad)", { XX } },
7901 { "(bad)", { XX } },
7902 { "(bad)", { XX } },
d5d7db8e
L		 7903 { "(bad)", { XX } },
7904 { "(bad)", { XX } },
7905 { "(bad)", { XX } },
7906 { "(bad)", { XX } },
7907 { "(bad)", { XX } },
c0f3af97 7908 /* 50 */
d5d7db8e
L		 7909 { "(bad)", { XX } },
7910 { "(bad)", { XX } },
7911 { "(bad)", { XX } },
d5d7db8e
L		 7912 { "(bad)", { XX } },
7913 { "(bad)", { XX } },
7914 { "(bad)", { XX } },
7915 { "(bad)", { XX } },
7916 { "(bad)", { XX } },
c0f3af97 7917 /* 58 */
d5d7db8e
L		 7918 { "(bad)", { XX } },
7919 { "(bad)", { XX } },
7920 { "(bad)", { XX } },
d5d7db8e
L		 7921 { "(bad)", { XX } },
7922 { "(bad)", { XX } },
7923 { "(bad)", { XX } },
7924 { "(bad)", { XX } },
7925 { "(bad)", { XX } },
c0f3af97 7926 /* 60 */
d5d7db8e
L		 7927 { "(bad)", { XX } },
7928 { "(bad)", { XX } },
7929 { "(bad)", { XX } },
d5d7db8e
L		 7930 { "(bad)", { XX } },
7931 { "(bad)", { XX } },
7932 { "(bad)", { XX } },
7933 { "(bad)", { XX } },
7934 { "(bad)", { XX } },
c0f3af97 7935 /* 68 */
d5d7db8e
L		 7936 { "(bad)", { XX } },
7937 { "(bad)", { XX } },
7938 { "(bad)", { XX } },
d5d7db8e
L		 7939 { "(bad)", { XX } },
7940 { "(bad)", { XX } },
7941 { "(bad)", { XX } },
7942 { "(bad)", { XX } },
7943 { "(bad)", { XX } },
c0f3af97 7944 /* 70 */
d5d7db8e
L		 7945 { "(bad)", { XX } },
7946 { "(bad)", { XX } },
7947 { "(bad)", { XX } },
d5d7db8e
L		 7948 { "(bad)", { XX } },
7949 { "(bad)", { XX } },
7950 { "(bad)", { XX } },
7951 { "(bad)", { XX } },
7952 { "(bad)", { XX } },
c0f3af97 7953 /* 78 */
d5d7db8e
L		 7954 { "(bad)", { XX } },
7955 { "(bad)", { XX } },
7956 { "(bad)", { XX } },
d5d7db8e
L		 7957 { "(bad)", { XX } },
7958 { "(bad)", { XX } },
7959 { "(bad)", { XX } },
7960 { "(bad)", { XX } },
7961 { "(bad)", { XX } },
c0f3af97 7962 /* 80 */
d5d7db8e
L		 7963 { "(bad)", { XX } },
7964 { "(bad)", { XX } },
7965 { "(bad)", { XX } },
d5d7db8e
L		 7966 { "(bad)", { XX } },
7967 { "(bad)", { XX } },
7968 { "(bad)", { XX } },
7969 { "(bad)", { XX } },
7970 { "(bad)", { XX } },
c0f3af97 7971 /* 88 */
d5d7db8e
L		 7972 { "(bad)", { XX } },
7973 { "(bad)", { XX } },
7974 { "(bad)", { XX } },
d5d7db8e
L		 7975 { "(bad)", { XX } },
7976 { "(bad)", { XX } },
7977 { "(bad)", { XX } },
7978 { "(bad)", { XX } },
7979 { "(bad)", { XX } },
c0f3af97 7980 /* 90 */
d5d7db8e
L		 7981 { "(bad)", { XX } },
7982 { "(bad)", { XX } },
7983 { "(bad)", { XX } },
d5d7db8e
L		 7984 { "(bad)", { XX } },
7985 { "(bad)", { XX } },
7986 { "(bad)", { XX } },
0bfee649
L		 7987 { PREFIX_TABLE (PREFIX_VEX_3896) },
7988 { PREFIX_TABLE (PREFIX_VEX_3897) },
c0f3af97 7989 /* 98 */
0bfee649
L		 7990 { PREFIX_TABLE (PREFIX_VEX_3898) },
7991 { PREFIX_TABLE (PREFIX_VEX_3899) },
7992 { PREFIX_TABLE (PREFIX_VEX_389A) },
7993 { PREFIX_TABLE (PREFIX_VEX_389B) },
7994 { PREFIX_TABLE (PREFIX_VEX_389C) },
7995 { PREFIX_TABLE (PREFIX_VEX_389D) },
7996 { PREFIX_TABLE (PREFIX_VEX_389E) },
7997 { PREFIX_TABLE (PREFIX_VEX_389F) },
c0f3af97 7998 /* a0 */
d5d7db8e
L		 7999 { "(bad)", { XX } },
8000 { "(bad)", { XX } },
8001 { "(bad)", { XX } },
d5d7db8e
L		 8002 { "(bad)", { XX } },
8003 { "(bad)", { XX } },
8004 { "(bad)", { XX } },
0bfee649
L		 8005 { PREFIX_TABLE (PREFIX_VEX_38A6) },
8006 { PREFIX_TABLE (PREFIX_VEX_38A7) },
c0f3af97 8007 /* a8 */
0bfee649
L		 8008 { PREFIX_TABLE (PREFIX_VEX_38A8) },
8009 { PREFIX_TABLE (PREFIX_VEX_38A9) },
8010 { PREFIX_TABLE (PREFIX_VEX_38AA) },
8011 { PREFIX_TABLE (PREFIX_VEX_38AB) },
8012 { PREFIX_TABLE (PREFIX_VEX_38AC) },
8013 { PREFIX_TABLE (PREFIX_VEX_38AD) },
8014 { PREFIX_TABLE (PREFIX_VEX_38AE) },
8015 { PREFIX_TABLE (PREFIX_VEX_38AF) },
c0f3af97 8016 /* b0 */
d5d7db8e
L		 8017 { "(bad)", { XX } },
8018 { "(bad)", { XX } },
8019 { "(bad)", { XX } },
8020 { "(bad)", { XX } },
8021 { "(bad)", { XX } },
8022 { "(bad)", { XX } },
0bfee649
L		 8023 { PREFIX_TABLE (PREFIX_VEX_38B6) },
8024 { PREFIX_TABLE (PREFIX_VEX_38B7) },
c0f3af97 8025 /* b8 */
0bfee649
L		 8026 { PREFIX_TABLE (PREFIX_VEX_38B8) },
8027 { PREFIX_TABLE (PREFIX_VEX_38B9) },
8028 { PREFIX_TABLE (PREFIX_VEX_38BA) },
8029 { PREFIX_TABLE (PREFIX_VEX_38BB) },
8030 { PREFIX_TABLE (PREFIX_VEX_38BC) },
8031 { PREFIX_TABLE (PREFIX_VEX_38BD) },
8032 { PREFIX_TABLE (PREFIX_VEX_38BE) },
8033 { PREFIX_TABLE (PREFIX_VEX_38BF) },
c0f3af97 8034 /* c0 */
d5d7db8e
L		 8035 { "(bad)", { XX } },
8036 { "(bad)", { XX } },
8037 { "(bad)", { XX } },
8038 { "(bad)", { XX } },
d5d7db8e
L		 8039 { "(bad)", { XX } },
8040 { "(bad)", { XX } },
8041 { "(bad)", { XX } },
8042 { "(bad)", { XX } },
c0f3af97 8043 /* c8 */
d5d7db8e
L		 8044 { "(bad)", { XX } },
8045 { "(bad)", { XX } },
8046 { "(bad)", { XX } },
8047 { "(bad)", { XX } },
d5d7db8e 8048 { "(bad)", { XX } },
d5d7db8e
L		 8049 { "(bad)", { XX } },
8050 { "(bad)", { XX } },
d5d7db8e 8051 { "(bad)", { XX } },
c0f3af97 8052 /* d0 */
d5d7db8e
L		 8053 { "(bad)", { XX } },
8054 { "(bad)", { XX } },
d5d7db8e
L		 8055 { "(bad)", { XX } },
8056 { "(bad)", { XX } },
8057 { "(bad)", { XX } },
8058 { "(bad)", { XX } },
d5d7db8e 8059 { "(bad)", { XX } },
d5d7db8e 8060 { "(bad)", { XX } },
c0f3af97 8061 /* d8 */
d5d7db8e 8062 { "(bad)", { XX } },
d5d7db8e
L		 8063 { "(bad)", { XX } },
8064 { "(bad)", { XX } },
a5ff0eb2
L		 8065 { PREFIX_TABLE (PREFIX_VEX_38DB) },
8066 { PREFIX_TABLE (PREFIX_VEX_38DC) },
8067 { PREFIX_TABLE (PREFIX_VEX_38DD) },
8068 { PREFIX_TABLE (PREFIX_VEX_38DE) },
8069 { PREFIX_TABLE (PREFIX_VEX_38DF) },
c0f3af97 8070 /* e0 */
d5d7db8e 8071 { "(bad)", { XX } },
d5d7db8e
L		 8072 { "(bad)", { XX } },
8073 { "(bad)", { XX } },
8074 { "(bad)", { XX } },
8075 { "(bad)", { XX } },
d5d7db8e
L		 8076 { "(bad)", { XX } },
8077 { "(bad)", { XX } },
8078 { "(bad)", { XX } },
c0f3af97 8079 /* e8 */
d5d7db8e
L		 8080 { "(bad)", { XX } },
8081 { "(bad)", { XX } },
8082 { "(bad)", { XX } },
8083 { "(bad)", { XX } },
8084 { "(bad)", { XX } },
d5d7db8e
L		 8085 { "(bad)", { XX } },
8086 { "(bad)", { XX } },
8087 { "(bad)", { XX } },
c0f3af97 8088 /* f0 */
d5d7db8e
L		 8089 { "(bad)", { XX } },
8090 { "(bad)", { XX } },
8091 { "(bad)", { XX } },
8092 { "(bad)", { XX } },
8093 { "(bad)", { XX } },
d5d7db8e
L		 8094 { "(bad)", { XX } },
8095 { "(bad)", { XX } },
8096 { "(bad)", { XX } },
c0f3af97 8097 /* f8 */
d5d7db8e
L		 8098 { "(bad)", { XX } },
8099 { "(bad)", { XX } },
8100 { "(bad)", { XX } },
8101 { "(bad)", { XX } },
8102 { "(bad)", { XX } },
d5d7db8e
L		 8103 { "(bad)", { XX } },
8104 { "(bad)", { XX } },
8105 { "(bad)", { XX } },
c0f3af97
L		 8106 },
8107 /* VEX_0F3A */
8108 {
8109 /* 00 */
d5d7db8e
L		 8110 { "(bad)", { XX } },
8111 { "(bad)", { XX } },
8112 { "(bad)", { XX } },
8113 { "(bad)", { XX } },
c0f3af97
L		 8114 { PREFIX_TABLE (PREFIX_VEX_3A04) },
8115 { PREFIX_TABLE (PREFIX_VEX_3A05) },
8116 { PREFIX_TABLE (PREFIX_VEX_3A06) },
d5d7db8e 8117 { "(bad)", { XX } },
c0f3af97
L		 8118 /* 08 */
8119 { PREFIX_TABLE (PREFIX_VEX_3A08) },
8120 { PREFIX_TABLE (PREFIX_VEX_3A09) },
8121 { PREFIX_TABLE (PREFIX_VEX_3A0A) },
8122 { PREFIX_TABLE (PREFIX_VEX_3A0B) },
8123 { PREFIX_TABLE (PREFIX_VEX_3A0C) },
8124 { PREFIX_TABLE (PREFIX_VEX_3A0D) },
8125 { PREFIX_TABLE (PREFIX_VEX_3A0E) },
8126 { PREFIX_TABLE (PREFIX_VEX_3A0F) },
8127 /* 10 */
d5d7db8e
L		 8128 { "(bad)", { XX } },
8129 { "(bad)", { XX } },
8130 { "(bad)", { XX } },
8131 { "(bad)", { XX } },
c0f3af97
L		 8132 { PREFIX_TABLE (PREFIX_VEX_3A14) },
8133 { PREFIX_TABLE (PREFIX_VEX_3A15) },
8134 { PREFIX_TABLE (PREFIX_VEX_3A16) },
8135 { PREFIX_TABLE (PREFIX_VEX_3A17) },
8136 /* 18 */
8137 { PREFIX_TABLE (PREFIX_VEX_3A18) },
8138 { PREFIX_TABLE (PREFIX_VEX_3A19) },
d5d7db8e
L		 8139 { "(bad)", { XX } },
8140 { "(bad)", { XX } },
8141 { "(bad)", { XX } },
8142 { "(bad)", { XX } },
d5d7db8e
L		 8143 { "(bad)", { XX } },
8144 { "(bad)", { XX } },
c0f3af97
L		 8145 /* 20 */
8146 { PREFIX_TABLE (PREFIX_VEX_3A20) },
8147 { PREFIX_TABLE (PREFIX_VEX_3A21) },
8148 { PREFIX_TABLE (PREFIX_VEX_3A22) },
d5d7db8e
L		 8149 { "(bad)", { XX } },
8150 { "(bad)", { XX } },
8151 { "(bad)", { XX } },
8152 { "(bad)", { XX } },
8153 { "(bad)", { XX } },
c0f3af97 8154 /* 28 */
d5d7db8e 8155 { "(bad)", { XX } },
d5d7db8e
L		 8156 { "(bad)", { XX } },
8157 { "(bad)", { XX } },
8158 { "(bad)", { XX } },
8159 { "(bad)", { XX } },
8160 { "(bad)", { XX } },
8161 { "(bad)", { XX } },
8162 { "(bad)", { XX } },
c0f3af97 8163 /* 30 */
d5d7db8e 8164 { "(bad)", { XX } },
d5d7db8e
L		 8165 { "(bad)", { XX } },
8166 { "(bad)", { XX } },
8167 { "(bad)", { XX } },
8168 { "(bad)", { XX } },
8169 { "(bad)", { XX } },
8170 { "(bad)", { XX } },
8171 { "(bad)", { XX } },
c0f3af97 8172 /* 38 */
d5d7db8e 8173 { "(bad)", { XX } },
d5d7db8e
L		 8174 { "(bad)", { XX } },
8175 { "(bad)", { XX } },
8176 { "(bad)", { XX } },
8177 { "(bad)", { XX } },
8178 { "(bad)", { XX } },
8179 { "(bad)", { XX } },
8180 { "(bad)", { XX } },
c0f3af97
L		 8181 /* 40 */
8182 { PREFIX_TABLE (PREFIX_VEX_3A40) },
8183 { PREFIX_TABLE (PREFIX_VEX_3A41) },
8184 { PREFIX_TABLE (PREFIX_VEX_3A42) },
d5d7db8e 8185 { "(bad)", { XX } },
ce2f5b3c 8186 { PREFIX_TABLE (PREFIX_VEX_3A44) },
d5d7db8e
L		 8187 { "(bad)", { XX } },
8188 { "(bad)", { XX } },
8189 { "(bad)", { XX } },
c0f3af97 8190 /* 48 */
0bfee649
L		 8191 { "(bad)", { XX } },
8192 { "(bad)", { XX } },
c0f3af97
L		 8193 { PREFIX_TABLE (PREFIX_VEX_3A4A) },
8194 { PREFIX_TABLE (PREFIX_VEX_3A4B) },
8195 { PREFIX_TABLE (PREFIX_VEX_3A4C) },
d5d7db8e
L		 8196 { "(bad)", { XX } },
8197 { "(bad)", { XX } },
8198 { "(bad)", { XX } },
c0f3af97 8199 /* 50 */
d5d7db8e 8200 { "(bad)", { XX } },
d5d7db8e
L		 8201 { "(bad)", { XX } },
8202 { "(bad)", { XX } },
8203 { "(bad)", { XX } },
8204 { "(bad)", { XX } },
8205 { "(bad)", { XX } },
8206 { "(bad)", { XX } },
8207 { "(bad)", { XX } },
c0f3af97 8208 /* 58 */
d5d7db8e 8209 { "(bad)", { XX } },
d5d7db8e
L		 8210 { "(bad)", { XX } },
8211 { "(bad)", { XX } },
8212 { "(bad)", { XX } },
922d8de8
DR		 8213 { PREFIX_TABLE (PREFIX_VEX_3A5C) },
8214 { PREFIX_TABLE (PREFIX_VEX_3A5D) },
8215 { PREFIX_TABLE (PREFIX_VEX_3A5E) },
8216 { PREFIX_TABLE (PREFIX_VEX_3A5F) },
c0f3af97
L		 8217 /* 60 */
8218 { PREFIX_TABLE (PREFIX_VEX_3A60) },
8219 { PREFIX_TABLE (PREFIX_VEX_3A61) },
8220 { PREFIX_TABLE (PREFIX_VEX_3A62) },
8221 { PREFIX_TABLE (PREFIX_VEX_3A63) },
d5d7db8e
L		 8222 { "(bad)", { XX } },
8223 { "(bad)", { XX } },
8224 { "(bad)", { XX } },
8225 { "(bad)", { XX } },
c0f3af97 8226 /* 68 */
922d8de8
DR		 8227 { PREFIX_TABLE (PREFIX_VEX_3A68) },
8228 { PREFIX_TABLE (PREFIX_VEX_3A69) },
8229 { PREFIX_TABLE (PREFIX_VEX_3A6A) },
8230 { PREFIX_TABLE (PREFIX_VEX_3A6B) },
8231 { PREFIX_TABLE (PREFIX_VEX_3A6C) },
8232 { PREFIX_TABLE (PREFIX_VEX_3A6D) },
8233 { PREFIX_TABLE (PREFIX_VEX_3A6E) },
8234 { PREFIX_TABLE (PREFIX_VEX_3A6F) },
c0f3af97 8235 /* 70 */
d5d7db8e 8236 { "(bad)", { XX } },
d5d7db8e
L		 8237 { "(bad)", { XX } },
8238 { "(bad)", { XX } },
8239 { "(bad)", { XX } },
8240 { "(bad)", { XX } },
8241 { "(bad)", { XX } },
8242 { "(bad)", { XX } },
8243 { "(bad)", { XX } },
c0f3af97 8244 /* 78 */
922d8de8
DR		 8245 { PREFIX_TABLE (PREFIX_VEX_3A78) },
8246 { PREFIX_TABLE (PREFIX_VEX_3A79) },
8247 { PREFIX_TABLE (PREFIX_VEX_3A7A) },
8248 { PREFIX_TABLE (PREFIX_VEX_3A7B) },
8249 { PREFIX_TABLE (PREFIX_VEX_3A7C) },
8250 { PREFIX_TABLE (PREFIX_VEX_3A7D) },
8251 { PREFIX_TABLE (PREFIX_VEX_3A7E) },
8252 { PREFIX_TABLE (PREFIX_VEX_3A7F) },
c0f3af97 8253 /* 80 */
d5d7db8e 8254 { "(bad)", { XX } },
d5d7db8e
L		 8255 { "(bad)", { XX } },
8256 { "(bad)", { XX } },
8257 { "(bad)", { XX } },
8258 { "(bad)", { XX } },
8259 { "(bad)", { XX } },
8260 { "(bad)", { XX } },
8261 { "(bad)", { XX } },
c0f3af97 8262 /* 88 */
d5d7db8e 8263 { "(bad)", { XX } },
d5d7db8e
L		 8264 { "(bad)", { XX } },
8265 { "(bad)", { XX } },
8266 { "(bad)", { XX } },
8267 { "(bad)", { XX } },
8268 { "(bad)", { XX } },
8269 { "(bad)", { XX } },
8270 { "(bad)", { XX } },
c0f3af97 8271 /* 90 */
d5d7db8e 8272 { "(bad)", { XX } },
d5d7db8e
L		 8273 { "(bad)", { XX } },
8274 { "(bad)", { XX } },
8275 { "(bad)", { XX } },
8276 { "(bad)", { XX } },
8277 { "(bad)", { XX } },
8278 { "(bad)", { XX } },
8279 { "(bad)", { XX } },
c0f3af97 8280 /* 98 */
d5d7db8e 8281 { "(bad)", { XX } },
d5d7db8e
L		 8282 { "(bad)", { XX } },
8283 { "(bad)", { XX } },
8284 { "(bad)", { XX } },
8285 { "(bad)", { XX } },
8286 { "(bad)", { XX } },
8287 { "(bad)", { XX } },
8288 { "(bad)", { XX } },
c0f3af97 8289 /* a0 */
d5d7db8e 8290 { "(bad)", { XX } },
85f10a01
MM		 8291 { "(bad)", { XX } },
8292 { "(bad)", { XX } },
d5d7db8e
L		 8293 { "(bad)", { XX } },
8294 { "(bad)", { XX } },
8295 { "(bad)", { XX } },
8296 { "(bad)", { XX } },
8297 { "(bad)", { XX } },
c0f3af97 8298 /* a8 */
d5d7db8e 8299 { "(bad)", { XX } },
d5d7db8e
L		 8300 { "(bad)", { XX } },
8301 { "(bad)", { XX } },
8302 { "(bad)", { XX } },
8303 { "(bad)", { XX } },
8304 { "(bad)", { XX } },
8305 { "(bad)", { XX } },
8306 { "(bad)", { XX } },
c0f3af97
L		 8307 /* b0 */
8308 { "(bad)", { XX } },
8309 { "(bad)", { XX } },
8310 { "(bad)", { XX } },
8311 { "(bad)", { XX } },
8312 { "(bad)", { XX } },
8313 { "(bad)", { XX } },
8314 { "(bad)", { XX } },
8315 { "(bad)", { XX } },
8316 /* b8 */
8317 { "(bad)", { XX } },
8318 { "(bad)", { XX } },
8319 { "(bad)", { XX } },
8320 { "(bad)", { XX } },
8321 { "(bad)", { XX } },
8322 { "(bad)", { XX } },
8323 { "(bad)", { XX } },
8324 { "(bad)", { XX } },
8325 /* c0 */
8326 { "(bad)", { XX } },
8327 { "(bad)", { XX } },
8328 { "(bad)", { XX } },
8329 { "(bad)", { XX } },
8330 { "(bad)", { XX } },
8331 { "(bad)", { XX } },
8332 { "(bad)", { XX } },
8333 { "(bad)", { XX } },
8334 /* c8 */
8335 { "(bad)", { XX } },
8336 { "(bad)", { XX } },
d5d7db8e 8337 { "(bad)", { XX } },
d5d7db8e
L		 8338 { "(bad)", { XX } },
8339 { "(bad)", { XX } },
8340 { "(bad)", { XX } },
8341 { "(bad)", { XX } },
8342 { "(bad)", { XX } },
c0f3af97
L		 8343 /* d0 */
8344 { "(bad)", { XX } },
8345 { "(bad)", { XX } },
8346 { "(bad)", { XX } },
d5d7db8e
L		 8347 { "(bad)", { XX } },
8348 { "(bad)", { XX } },
8349 { "(bad)", { XX } },
c0f3af97
L		 8350 { "(bad)", { XX } },
8351 { "(bad)", { XX } },
8352 /* d8 */
8353 { "(bad)", { XX } },
d5d7db8e
L		 8354 { "(bad)", { XX } },
8355 { "(bad)", { XX } },
8356 { "(bad)", { XX } },
8357 { "(bad)", { XX } },
8358 { "(bad)", { XX } },
8359 { "(bad)", { XX } },
a5ff0eb2 8360 { PREFIX_TABLE (PREFIX_VEX_3ADF) },
c0f3af97 8361 /* e0 */
d5d7db8e 8362 { "(bad)", { XX } },
d5d7db8e
L		 8363 { "(bad)", { XX } },
8364 { "(bad)", { XX } },
8365 { "(bad)", { XX } },
8366 { "(bad)", { XX } },
8367 { "(bad)", { XX } },
8368 { "(bad)", { XX } },
8369 { "(bad)", { XX } },
c0f3af97 8370 /* e8 */
d5d7db8e 8371 { "(bad)", { XX } },
d5d7db8e
L		 8372 { "(bad)", { XX } },
8373 { "(bad)", { XX } },
8374 { "(bad)", { XX } },
8375 { "(bad)", { XX } },
8376 { "(bad)", { XX } },
8377 { "(bad)", { XX } },
8378 { "(bad)", { XX } },
c0f3af97 8379 /* f0 */
d5d7db8e 8380 { "(bad)", { XX } },
d5d7db8e
L		 8381 { "(bad)", { XX } },
8382 { "(bad)", { XX } },
8383 { "(bad)", { XX } },
8384 { "(bad)", { XX } },
8385 { "(bad)", { XX } },
8386 { "(bad)", { XX } },
8387 { "(bad)", { XX } },
c0f3af97 8388 /* f8 */
d5d7db8e 8389 { "(bad)", { XX } },
d5d7db8e
L		 8390 { "(bad)", { XX } },
8391 { "(bad)", { XX } },
8392 { "(bad)", { XX } },
8393 { "(bad)", { XX } },
8394 { "(bad)", { XX } },
8395 { "(bad)", { XX } },
8396 { "(bad)", { XX } },
c0f3af97
L		 8397 },
8398};
8399
8400static const struct dis386 vex_len_table[][2] = {
8401 /* VEX_LEN_10_P_1 */
8402 {
9e30b8e0 8403 { VEX_W_TABLE (VEX_W_10_P_1) },
d5d7db8e 8404 { "(bad)", { XX } },
c0f3af97
L		 8405 },
8406
8407 /* VEX_LEN_10_P_3 */
8408 {
9e30b8e0 8409 { VEX_W_TABLE (VEX_W_10_P_3) },
d5d7db8e 8410 { "(bad)", { XX } },
c0f3af97
L		 8411 },
8412
8413 /* VEX_LEN_11_P_1 */
8414 {
9e30b8e0 8415 { VEX_W_TABLE (VEX_W_11_P_1) },
d5d7db8e 8416 { "(bad)", { XX } },
c0f3af97
L		 8417 },
8418
8419 /* VEX_LEN_11_P_3 */
8420 {
9e30b8e0 8421 { VEX_W_TABLE (VEX_W_11_P_3) },
d5d7db8e 8422 { "(bad)", { XX } },
c0f3af97
L		 8423 },
8424
8425 /* VEX_LEN_12_P_0_M_0 */
8426 {
9e30b8e0 8427 { VEX_W_TABLE (VEX_W_12_P_0_M_0) },
d5d7db8e 8428 { "(bad)", { XX } },
c0f3af97
L		 8429 },
8430
8431 /* VEX_LEN_12_P_0_M_1 */
8432 {
9e30b8e0 8433 { VEX_W_TABLE (VEX_W_12_P_0_M_1) },
d5d7db8e 8434 { "(bad)", { XX } },
c0f3af97
L		 8435 },
8436
8437 /* VEX_LEN_12_P_2 */
8438 {
9e30b8e0 8439 { VEX_W_TABLE (VEX_W_12_P_2) },
d5d7db8e 8440 { "(bad)", { XX } },
c0f3af97
L		 8441 },
8442
8443 /* VEX_LEN_13_M_0 */
8444 {
9e30b8e0 8445 { VEX_W_TABLE (VEX_W_13_M_0) },
85f10a01 8446 { "(bad)", { XX } },
c0f3af97
L		 8447 },
8448
8449 /* VEX_LEN_16_P_0_M_0 */
8450 {
9e30b8e0 8451 { VEX_W_TABLE (VEX_W_16_P_0_M_0) },
85f10a01 8452 { "(bad)", { XX } },
c0f3af97
L		 8453 },
8454
8455 /* VEX_LEN_16_P_0_M_1 */
8456 {
9e30b8e0 8457 { VEX_W_TABLE (VEX_W_16_P_0_M_1) },
85f10a01 8458 { "(bad)", { XX } },
c0f3af97
L		 8459 },
8460
8461 /* VEX_LEN_16_P_2 */
8462 {
9e30b8e0 8463 { VEX_W_TABLE (VEX_W_16_P_2) },
85f10a01 8464 { "(bad)", { XX } },
c0f3af97
L		 8465 },
8466
8467 /* VEX_LEN_17_M_0 */
8468 {
9e30b8e0 8469 { VEX_W_TABLE (VEX_W_17_M_0) },
85f10a01 8470 { "(bad)", { XX } },
c0f3af97
L		 8471 },
8472
8473 /* VEX_LEN_2A_P_1 */
8474 {
8475 { "vcvtsi2ss%LQ", { XM, Vex128, Ev } },
d5d7db8e 8476 { "(bad)", { XX } },
c0f3af97
L		 8477 },
8478
8479 /* VEX_LEN_2A_P_3 */
8480 {
8481 { "vcvtsi2sd%LQ", { XM, Vex128, Ev } },
d5d7db8e 8482 { "(bad)", { XX } },
c0f3af97
L		 8483 },
8484
c0f3af97
L		 8485 /* VEX_LEN_2C_P_1 */
8486 {
8487 { "vcvttss2siY", { Gv, EXd } },
d5d7db8e 8488 { "(bad)", { XX } },
c0f3af97
L		 8489 },
8490
8491 /* VEX_LEN_2C_P_3 */
8492 {
8493 { "vcvttsd2siY", { Gv, EXq } },
d5d7db8e 8494 { "(bad)", { XX } },
c0f3af97
L		 8495 },
8496
8497 /* VEX_LEN_2D_P_1 */
8498 {
8499 { "vcvtss2siY", { Gv, EXd } },
85f10a01 8500 { "(bad)", { XX } },
c0f3af97
L		 8501 },
8502
8503 /* VEX_LEN_2D_P_3 */
8504 {
8505 { "vcvtsd2siY", { Gv, EXq } },
d5d7db8e 8506 { "(bad)", { XX } },
c0f3af97
L		 8507 },
8508
8509 /* VEX_LEN_2E_P_0 */
8510 {
9e30b8e0 8511 { VEX_W_TABLE (VEX_W_2E_P_0) },
d5d7db8e 8512 { "(bad)", { XX } },
c0f3af97
L		 8513 },
8514
8515 /* VEX_LEN_2E_P_2 */
8516 {
9e30b8e0 8517 { VEX_W_TABLE (VEX_W_2E_P_2) },
d5d7db8e 8518 { "(bad)", { XX } },
c0f3af97
L		 8519 },
8520
8521 /* VEX_LEN_2F_P_0 */
8522 {
9e30b8e0 8523 { VEX_W_TABLE (VEX_W_2F_P_0) },
d5d7db8e 8524 { "(bad)", { XX } },
c0f3af97
L		 8525 },
8526
8527 /* VEX_LEN_2F_P_2 */
8528 {
9e30b8e0 8529 { VEX_W_TABLE (VEX_W_2F_P_2) },
d5d7db8e 8530 { "(bad)", { XX } },
c0f3af97
L		 8531 },
8532
8533 /* VEX_LEN_51_P_1 */
8534 {
9e30b8e0 8535 { VEX_W_TABLE (VEX_W_51_P_1) },
d5d7db8e 8536 { "(bad)", { XX } },
c0f3af97
L		 8537 },
8538
8539 /* VEX_LEN_51_P_3 */
8540 {
9e30b8e0 8541 { VEX_W_TABLE (VEX_W_51_P_3) },
d5d7db8e 8542 { "(bad)", { XX } },
c0f3af97
L		 8543 },
8544
8545 /* VEX_LEN_52_P_1 */
8546 {
9e30b8e0 8547 { VEX_W_TABLE (VEX_W_52_P_1) },
d5d7db8e 8548 { "(bad)", { XX } },
c0f3af97
L		 8549 },
8550
8551 /* VEX_LEN_53_P_1 */
8552 {
9e30b8e0 8553 { VEX_W_TABLE (VEX_W_53_P_1) },
d5d7db8e 8554 { "(bad)", { XX } },
c0f3af97
L		 8555 },
8556
8557 /* VEX_LEN_58_P_1 */
8558 {
9e30b8e0 8559 { VEX_W_TABLE (VEX_W_58_P_1) },
d5d7db8e 8560 { "(bad)", { XX } },
c0f3af97
L		 8561 },
8562
8563 /* VEX_LEN_58_P_3 */
8564 {
9e30b8e0 8565 { VEX_W_TABLE (VEX_W_58_P_3) },
d5d7db8e 8566 { "(bad)", { XX } },
c0f3af97
L		 8567 },
8568
8569 /* VEX_LEN_59_P_1 */
8570 {
9e30b8e0 8571 { VEX_W_TABLE (VEX_W_59_P_1) },
d5d7db8e 8572 { "(bad)", { XX } },
c0f3af97
L		 8573 },
8574
8575 /* VEX_LEN_59_P_3 */
8576 {
9e30b8e0 8577 { VEX_W_TABLE (VEX_W_59_P_3) },
d5d7db8e 8578 { "(bad)", { XX } },
c0f3af97
L		 8579 },
8580
8581 /* VEX_LEN_5A_P_1 */
8582 {
9e30b8e0 8583 { VEX_W_TABLE (VEX_W_5A_P_1) },
d5d7db8e 8584 { "(bad)", { XX } },
c0f3af97
L		 8585 },
8586
8587 /* VEX_LEN_5A_P_3 */
8588 {
9e30b8e0 8589 { VEX_W_TABLE (VEX_W_5A_P_3) },
d5d7db8e 8590 { "(bad)", { XX } },
c0f3af97
L		 8591 },
8592
8593 /* VEX_LEN_5C_P_1 */
8594 {
9e30b8e0 8595 { VEX_W_TABLE (VEX_W_5C_P_1) },
d5d7db8e 8596 { "(bad)", { XX } },
c0f3af97
L		 8597 },
8598
8599 /* VEX_LEN_5C_P_3 */
8600 {
9e30b8e0 8601 { VEX_W_TABLE (VEX_W_5C_P_3) },
d5d7db8e 8602 { "(bad)", { XX } },
c0f3af97
L		 8603 },
8604
8605 /* VEX_LEN_5D_P_1 */
8606 {
9e30b8e0 8607 { VEX_W_TABLE (VEX_W_5D_P_1) },
d5d7db8e 8608 { "(bad)", { XX } },
c0f3af97
L		 8609 },
8610
8611 /* VEX_LEN_5D_P_3 */
8612 {
9e30b8e0 8613 { VEX_W_TABLE (VEX_W_5D_P_3) },
d5d7db8e 8614 { "(bad)", { XX } },
c0f3af97
L		 8615 },
8616
8617 /* VEX_LEN_5E_P_1 */
8618 {
9e30b8e0 8619 { VEX_W_TABLE (VEX_W_5E_P_1) },
85f10a01 8620 { "(bad)", { XX } },
c0f3af97
L		 8621 },
8622
8623 /* VEX_LEN_5E_P_3 */
8624 {
9e30b8e0 8625 { VEX_W_TABLE (VEX_W_5E_P_3) },
85f10a01 8626 { "(bad)", { XX } },
c0f3af97
L		 8627 },
8628
8629 /* VEX_LEN_5F_P_1 */
8630 {
9e30b8e0 8631 { VEX_W_TABLE (VEX_W_5F_P_1) },
85f10a01 8632 { "(bad)", { XX } },
c0f3af97
L		 8633 },
8634
8635 /* VEX_LEN_5F_P_3 */
8636 {
9e30b8e0 8637 { VEX_W_TABLE (VEX_W_5F_P_3) },
85f10a01 8638 { "(bad)", { XX } },
c0f3af97
L		 8639 },
8640
8641 /* VEX_LEN_60_P_2 */
8642 {
9e30b8e0 8643 { VEX_W_TABLE (VEX_W_60_P_2) },
d5d7db8e 8644 { "(bad)", { XX } },
c0f3af97
L		 8645 },
8646
8647 /* VEX_LEN_61_P_2 */
8648 {
9e30b8e0 8649 { VEX_W_TABLE (VEX_W_61_P_2) },
d5d7db8e 8650 { "(bad)", { XX } },
c0f3af97
L		 8651 },
8652
8653 /* VEX_LEN_62_P_2 */
8654 {
9e30b8e0 8655 { VEX_W_TABLE (VEX_W_62_P_2) },
d5d7db8e 8656 { "(bad)", { XX } },
c0f3af97
L		 8657 },
8658
8659 /* VEX_LEN_63_P_2 */
8660 {
9e30b8e0 8661 { VEX_W_TABLE (VEX_W_63_P_2) },
d5d7db8e 8662 { "(bad)", { XX } },
c0f3af97
L		 8663 },
8664
8665 /* VEX_LEN_64_P_2 */
8666 {
9e30b8e0 8667 { VEX_W_TABLE (VEX_W_64_P_2) },
d5d7db8e 8668 { "(bad)", { XX } },
c0f3af97
L		 8669 },
8670
8671 /* VEX_LEN_65_P_2 */
8672 {
9e30b8e0 8673 { VEX_W_TABLE (VEX_W_65_P_2) },
d5d7db8e 8674 { "(bad)", { XX } },
c0f3af97
L		 8675 },
8676
8677 /* VEX_LEN_66_P_2 */
8678 {
9e30b8e0 8679 { VEX_W_TABLE (VEX_W_66_P_2) },
d5d7db8e 8680 { "(bad)", { XX } },
c0f3af97
L		 8681 },
8682
8683 /* VEX_LEN_67_P_2 */
8684 {
9e30b8e0 8685 { VEX_W_TABLE (VEX_W_67_P_2) },
d5d7db8e 8686 { "(bad)", { XX } },
c0f3af97
L		 8687 },
8688
8689 /* VEX_LEN_68_P_2 */
8690 {
9e30b8e0 8691 { VEX_W_TABLE (VEX_W_68_P_2) },
d5d7db8e 8692 { "(bad)", { XX } },
c0f3af97
L		 8693 },
8694
8695 /* VEX_LEN_69_P_2 */
8696 {
9e30b8e0 8697 { VEX_W_TABLE (VEX_W_69_P_2) },
d5d7db8e 8698 { "(bad)", { XX } },
c0f3af97
L		 8699 },
8700
8701 /* VEX_LEN_6A_P_2 */
8702 {
9e30b8e0 8703 { VEX_W_TABLE (VEX_W_6A_P_2) },
d5d7db8e 8704 { "(bad)", { XX } },
c0f3af97
L		 8705 },
8706
8707 /* VEX_LEN_6B_P_2 */
8708 {
9e30b8e0 8709 { VEX_W_TABLE (VEX_W_6B_P_2) },
d5d7db8e 8710 { "(bad)", { XX } },
c0f3af97
L		 8711 },
8712
8713 /* VEX_LEN_6C_P_2 */
8714 {
9e30b8e0 8715 { VEX_W_TABLE (VEX_W_6C_P_2) },
d5d7db8e 8716 { "(bad)", { XX } },
c0f3af97
L		 8717 },
8718
8719 /* VEX_LEN_6D_P_2 */
8720 {
9e30b8e0 8721 { VEX_W_TABLE (VEX_W_6D_P_2) },
d5d7db8e 8722 { "(bad)", { XX } },
c0f3af97
L		 8723 },
8724
8725 /* VEX_LEN_6E_P_2 */
8726 {
8727 { "vmovK", { XM, Edq } },
d5d7db8e 8728 { "(bad)", { XX } },
c0f3af97
L		 8729 },
8730
8731 /* VEX_LEN_70_P_1 */
8732 {
9e30b8e0 8733 { VEX_W_TABLE (VEX_W_70_P_1) },
d5d7db8e 8734 { "(bad)", { XX } },
c0f3af97
L		 8735 },
8736
8737 /* VEX_LEN_70_P_2 */
8738 {
9e30b8e0 8739 { VEX_W_TABLE (VEX_W_70_P_2) },
d5d7db8e 8740 { "(bad)", { XX } },
c0f3af97
L		 8741 },
8742
8743 /* VEX_LEN_70_P_3 */
8744 {
9e30b8e0 8745 { VEX_W_TABLE (VEX_W_70_P_3) },
d5d7db8e 8746 { "(bad)", { XX } },
c0f3af97
L		 8747 },
8748
8749 /* VEX_LEN_71_R_2_P_2 */
8750 {
9e30b8e0 8751 { VEX_W_TABLE (VEX_W_71_R_2_P_2) },
d5d7db8e 8752 { "(bad)", { XX } },
c0f3af97
L		 8753 },
8754
8755 /* VEX_LEN_71_R_4_P_2 */
8756 {
9e30b8e0 8757 { VEX_W_TABLE (VEX_W_71_R_4_P_2) },
d5d7db8e 8758 { "(bad)", { XX } },
c0f3af97
L		 8759 },
8760
8761 /* VEX_LEN_71_R_6_P_2 */
8762 {
9e30b8e0 8763 { VEX_W_TABLE (VEX_W_71_R_6_P_2) },
d5d7db8e 8764 { "(bad)", { XX } },
c0f3af97
L		 8765 },
8766
8767 /* VEX_LEN_72_R_2_P_2 */
8768 {
9e30b8e0 8769 { VEX_W_TABLE (VEX_W_72_R_2_P_2) },
d5d7db8e 8770 { "(bad)", { XX } },
c0f3af97
L		 8771 },
8772
8773 /* VEX_LEN_72_R_4_P_2 */
8774 {
9e30b8e0 8775 { VEX_W_TABLE (VEX_W_72_R_4_P_2) },
d5d7db8e 8776 { "(bad)", { XX } },
c0f3af97
L		 8777 },
8778
8779 /* VEX_LEN_72_R_6_P_2 */
8780 {
9e30b8e0 8781 { VEX_W_TABLE (VEX_W_72_R_6_P_2) },
d5d7db8e 8782 { "(bad)", { XX } },
c0f3af97
L		 8783 },
8784
8785 /* VEX_LEN_73_R_2_P_2 */
8786 {
9e30b8e0 8787 { VEX_W_TABLE (VEX_W_73_R_2_P_2) },
d5d7db8e 8788 { "(bad)", { XX } },
c0f3af97
L		 8789 },
8790
8791 /* VEX_LEN_73_R_3_P_2 */
8792 {
9e30b8e0 8793 { VEX_W_TABLE (VEX_W_73_R_3_P_2) },
d5d7db8e 8794 { "(bad)", { XX } },
c0f3af97
L		 8795 },
8796
8797 /* VEX_LEN_73_R_6_P_2 */
8798 {
9e30b8e0 8799 { VEX_W_TABLE (VEX_W_73_R_6_P_2) },
d5d7db8e 8800 { "(bad)", { XX } },
c0f3af97
L		 8801 },
8802
8803 /* VEX_LEN_73_R_7_P_2 */
8804 {
9e30b8e0 8805 { VEX_W_TABLE (VEX_W_73_R_7_P_2) },
d5d7db8e 8806 { "(bad)", { XX } },
c0f3af97
L		 8807 },
8808
8809 /* VEX_LEN_74_P_2 */
8810 {
9e30b8e0 8811 { VEX_W_TABLE (VEX_W_74_P_2) },
d5d7db8e 8812 { "(bad)", { XX } },
c0f3af97
L		 8813 },
8814
8815 /* VEX_LEN_75_P_2 */
8816 {
9e30b8e0 8817 { VEX_W_TABLE (VEX_W_75_P_2) },
d5d7db8e 8818 { "(bad)", { XX } },
c0f3af97
L		 8819 },
8820
8821 /* VEX_LEN_76_P_2 */
8822 {
9e30b8e0 8823 { VEX_W_TABLE (VEX_W_76_P_2) },
d5d7db8e 8824 { "(bad)", { XX } },
c0f3af97
L		 8825 },
8826
8827 /* VEX_LEN_7E_P_1 */
8828 {
9e30b8e0 8829 { VEX_W_TABLE (VEX_W_7E_P_1) },
d5d7db8e 8830 { "(bad)", { XX } },
c0f3af97
L		 8831 },
8832
8833 /* VEX_LEN_7E_P_2 */
8834 {
8835 { "vmovK", { Edq, XM } },
d5d7db8e 8836 { "(bad)", { XX } },
c0f3af97
L		 8837 },
8838
9daa0d29 8839 /* VEX_LEN_AE_R_2_M_0 */
c0f3af97 8840 {
9e30b8e0 8841 { VEX_W_TABLE (VEX_W_AE_R_2_M_0) },
d5d7db8e 8842 { "(bad)", { XX } },
c0f3af97
L		 8843 },
8844
9daa0d29 8845 /* VEX_LEN_AE_R_3_M_0 */
c0f3af97 8846 {
9e30b8e0 8847 { VEX_W_TABLE (VEX_W_AE_R_3_M_0) },
d5d7db8e 8848 { "(bad)", { XX } },
c0f3af97
L		 8849 },
8850
8851 /* VEX_LEN_C2_P_1 */
8852 {
9e30b8e0 8853 { VEX_W_TABLE (VEX_W_C2_P_1) },
d5d7db8e 8854 { "(bad)", { XX } },
c0f3af97
L		 8855 },
8856
8857 /* VEX_LEN_C2_P_3 */
8858 {
9e30b8e0 8859 { VEX_W_TABLE (VEX_W_C2_P_3) },
d5d7db8e 8860 { "(bad)", { XX } },
c0f3af97
L		 8861 },
8862
8863 /* VEX_LEN_C4_P_2 */
8864 {
9e30b8e0 8865 { VEX_W_TABLE (VEX_W_C4_P_2) },
d5d7db8e 8866 { "(bad)", { XX } },
c0f3af97
L		 8867 },
8868
8869 /* VEX_LEN_C5_P_2 */
8870 {
9e30b8e0 8871 { VEX_W_TABLE (VEX_W_C5_P_2) },
d5d7db8e 8872 { "(bad)", { XX } },
c0f3af97
L		 8873 },
8874
8875 /* VEX_LEN_D1_P_2 */
8876 {
9e30b8e0 8877 { VEX_W_TABLE (VEX_W_D1_P_2) },
d5d7db8e 8878 { "(bad)", { XX } },
c0f3af97
L		 8879 },
8880
8881 /* VEX_LEN_D2_P_2 */
8882 {
9e30b8e0 8883 { VEX_W_TABLE (VEX_W_D2_P_2) },
d5d7db8e 8884 { "(bad)", { XX } },
c0f3af97
L		 8885 },
8886
8887 /* VEX_LEN_D3_P_2 */
8888 {
9e30b8e0 8889 { VEX_W_TABLE (VEX_W_D3_P_2) },
d5d7db8e 8890 { "(bad)", { XX } },
c0f3af97
L		 8891 },
8892
8893 /* VEX_LEN_D4_P_2 */
8894 {
9e30b8e0 8895 { VEX_W_TABLE (VEX_W_D4_P_2) },
d5d7db8e 8896 { "(bad)", { XX } },
c0f3af97
L		 8897 },
8898
8899 /* VEX_LEN_D5_P_2 */
8900 {
9e30b8e0 8901 { VEX_W_TABLE (VEX_W_D5_P_2) },
d5d7db8e 8902 { "(bad)", { XX } },
c0f3af97
L		 8903 },
8904
8905 /* VEX_LEN_D6_P_2 */
8906 {
9e30b8e0 8907 { VEX_W_TABLE (VEX_W_D6_P_2) },
d5d7db8e 8908 { "(bad)", { XX } },
c0f3af97
L		 8909 },
8910
8911 /* VEX_LEN_D7_P_2_M_1 */
8912 {
9e30b8e0 8913 { VEX_W_TABLE (VEX_W_D7_P_2_M_1) },
d5d7db8e 8914 { "(bad)", { XX } },
c0f3af97
L		 8915 },
8916
8917 /* VEX_LEN_D8_P_2 */
8918 {
9e30b8e0 8919 { VEX_W_TABLE (VEX_W_D8_P_2) },
d5d7db8e 8920 { "(bad)", { XX } },
c0f3af97
L		 8921 },
8922
8923 /* VEX_LEN_D9_P_2 */
8924 {
9e30b8e0 8925 { VEX_W_TABLE (VEX_W_D9_P_2) },
d5d7db8e 8926 { "(bad)", { XX } },
c0f3af97
L		 8927 },
8928
8929 /* VEX_LEN_DA_P_2 */
8930 {
9e30b8e0 8931 { VEX_W_TABLE (VEX_W_DA_P_2) },
d5d7db8e 8932 { "(bad)", { XX } },
c0f3af97
L		 8933 },
8934
8935 /* VEX_LEN_DB_P_2 */
8936 {
9e30b8e0 8937 { VEX_W_TABLE (VEX_W_DB_P_2) },
d5d7db8e 8938 { "(bad)", { XX } },
c0f3af97
L		 8939 },
8940
8941 /* VEX_LEN_DC_P_2 */
8942 {
9e30b8e0 8943 { VEX_W_TABLE (VEX_W_DC_P_2) },
d5d7db8e 8944 { "(bad)", { XX } },
c0f3af97
L		 8945 },
8946
8947 /* VEX_LEN_DD_P_2 */
8948 {
9e30b8e0 8949 { VEX_W_TABLE (VEX_W_DD_P_2) },
d5d7db8e 8950 { "(bad)", { XX } },
c0f3af97
L		 8951 },
8952
8953 /* VEX_LEN_DE_P_2 */
8954 {
9e30b8e0 8955 { VEX_W_TABLE (VEX_W_DE_P_2) },
d5d7db8e 8956 { "(bad)", { XX } },
c0f3af97
L		 8957 },
8958
8959 /* VEX_LEN_DF_P_2 */
8960 {
9e30b8e0 8961 { VEX_W_TABLE (VEX_W_DF_P_2) },
d5d7db8e 8962 { "(bad)", { XX } },
c0f3af97
L		 8963 },
8964
8965 /* VEX_LEN_E0_P_2 */
8966 {
9e30b8e0 8967 { VEX_W_TABLE (VEX_W_E0_P_2) },
d5d7db8e 8968 { "(bad)", { XX } },
c0f3af97
L		 8969 },
8970
8971 /* VEX_LEN_E1_P_2 */
8972 {
9e30b8e0 8973 { VEX_W_TABLE (VEX_W_E1_P_2) },
d5d7db8e 8974 { "(bad)", { XX } },
c0f3af97
L		 8975 },
8976
8977 /* VEX_LEN_E2_P_2 */
8978 {
9e30b8e0 8979 { VEX_W_TABLE (VEX_W_E2_P_2) },
d5d7db8e 8980 { "(bad)", { XX } },
c0f3af97
L		 8981 },
8982
8983 /* VEX_LEN_E3_P_2 */
8984 {
9e30b8e0 8985 { VEX_W_TABLE (VEX_W_E3_P_2) },
d5d7db8e 8986 { "(bad)", { XX } },
c0f3af97
L		 8987 },
8988
8989 /* VEX_LEN_E4_P_2 */
8990 {
9e30b8e0 8991 { VEX_W_TABLE (VEX_W_E4_P_2) },
d5d7db8e 8992 { "(bad)", { XX } },
c0f3af97
L		 8993 },
8994
8995 /* VEX_LEN_E5_P_2 */
8996 {
9e30b8e0 8997 { VEX_W_TABLE (VEX_W_E5_P_2) },
d5d7db8e 8998 { "(bad)", { XX } },
c0f3af97
L		 8999 },
9000
c0f3af97
L		 9001 /* VEX_LEN_E8_P_2 */
9002 {
9e30b8e0 9003 { VEX_W_TABLE (VEX_W_E8_P_2) },
d5d7db8e 9004 { "(bad)", { XX } },
c0f3af97
L		 9005 },
9006
9007 /* VEX_LEN_E9_P_2 */
9008 {
9e30b8e0 9009 { VEX_W_TABLE (VEX_W_E9_P_2) },
d5d7db8e 9010 { "(bad)", { XX } },
c0f3af97
L		 9011 },
9012
9013 /* VEX_LEN_EA_P_2 */
9014 {
9e30b8e0 9015 { VEX_W_TABLE (VEX_W_EA_P_2) },
d5d7db8e 9016 { "(bad)", { XX } },
c0f3af97
L		 9017 },
9018
9019 /* VEX_LEN_EB_P_2 */
9020 {
9e30b8e0 9021 { VEX_W_TABLE (VEX_W_EB_P_2) },
d5d7db8e 9022 { "(bad)", { XX } },
c0f3af97
L		 9023 },
9024
9025 /* VEX_LEN_EC_P_2 */
9026 {
9e30b8e0 9027 { VEX_W_TABLE (VEX_W_EC_P_2) },
d5d7db8e 9028 { "(bad)", { XX } },
c0f3af97
L		 9029 },
9030
9031 /* VEX_LEN_ED_P_2 */
9032 {
9e30b8e0 9033 { VEX_W_TABLE (VEX_W_ED_P_2) },
d5d7db8e 9034 { "(bad)", { XX } },
c0f3af97
L		 9035 },
9036
9037 /* VEX_LEN_EE_P_2 */
9038 {
9e30b8e0 9039 { VEX_W_TABLE (VEX_W_EE_P_2) },
d5d7db8e 9040 { "(bad)", { XX } },
c0f3af97
L		 9041 },
9042
9043 /* VEX_LEN_EF_P_2 */
9044 {
9e30b8e0 9045 { VEX_W_TABLE (VEX_W_EF_P_2) },
d5d7db8e 9046 { "(bad)", { XX } },
c0f3af97
L		 9047 },
9048
9049 /* VEX_LEN_F1_P_2 */
9050 {
9e30b8e0 9051 { VEX_W_TABLE (VEX_W_F1_P_2) },
d5d7db8e 9052 { "(bad)", { XX } },
c0f3af97
L		 9053 },
9054
9055 /* VEX_LEN_F2_P_2 */
9056 {
9e30b8e0 9057 { VEX_W_TABLE (VEX_W_F2_P_2) },
d5d7db8e 9058 { "(bad)", { XX } },
c0f3af97
L		 9059 },
9060
9061 /* VEX_LEN_F3_P_2 */
9062 {
9e30b8e0 9063 { VEX_W_TABLE (VEX_W_F3_P_2) },
d5d7db8e 9064 { "(bad)", { XX } },
c0f3af97
L		 9065 },
9066
9067 /* VEX_LEN_F4_P_2 */
9068 {
9e30b8e0 9069 { VEX_W_TABLE (VEX_W_F4_P_2) },
d5d7db8e 9070 { "(bad)", { XX } },
c0f3af97
L		 9071 },
9072
9073 /* VEX_LEN_F5_P_2 */
9074 {
9e30b8e0 9075 { VEX_W_TABLE (VEX_W_F5_P_2) },
d5d7db8e 9076 { "(bad)", { XX } },
c0f3af97
L		 9077 },
9078
9079 /* VEX_LEN_F6_P_2 */
9080 {
9e30b8e0 9081 { VEX_W_TABLE (VEX_W_F6_P_2) },
d5d7db8e 9082 { "(bad)", { XX } },
c0f3af97
L		 9083 },
9084
9085 /* VEX_LEN_F7_P_2 */
9086 {
9e30b8e0 9087 { VEX_W_TABLE (VEX_W_F7_P_2) },
d5d7db8e 9088 { "(bad)", { XX } },
c0f3af97
L		 9089 },
9090
9091 /* VEX_LEN_F8_P_2 */
9092 {
9e30b8e0 9093 { VEX_W_TABLE (VEX_W_F8_P_2) },
d5d7db8e 9094 { "(bad)", { XX } },
c0f3af97
L		 9095 },
9096
9097 /* VEX_LEN_F9_P_2 */
9098 {
9e30b8e0 9099 { VEX_W_TABLE (VEX_W_F9_P_2) },
d5d7db8e 9100 { "(bad)", { XX } },
c0f3af97
L		 9101 },
9102
9103 /* VEX_LEN_FA_P_2 */
9104 {
9e30b8e0 9105 { VEX_W_TABLE (VEX_W_FA_P_2) },
d5d7db8e 9106 { "(bad)", { XX } },
c0f3af97
L		 9107 },
9108
9109 /* VEX_LEN_FB_P_2 */
9110 {
9e30b8e0 9111 { VEX_W_TABLE (VEX_W_FB_P_2) },
d5d7db8e 9112 { "(bad)", { XX } },
c0f3af97
L		 9113 },
9114
9115 /* VEX_LEN_FC_P_2 */
9116 {
9e30b8e0 9117 { VEX_W_TABLE (VEX_W_FC_P_2) },
d5d7db8e 9118 { "(bad)", { XX } },
c0f3af97
L		 9119 },
9120
9121 /* VEX_LEN_FD_P_2 */
9122 {
9e30b8e0 9123 { VEX_W_TABLE (VEX_W_FD_P_2) },
d5d7db8e 9124 { "(bad)", { XX } },
c0f3af97
L		 9125 },
9126
9127 /* VEX_LEN_FE_P_2 */
9128 {
9e30b8e0 9129 { VEX_W_TABLE (VEX_W_FE_P_2) },
d5d7db8e 9130 { "(bad)", { XX } },
c0f3af97
L		 9131 },
9132
9133 /* VEX_LEN_3800_P_2 */
9134 {
9e30b8e0 9135 { VEX_W_TABLE (VEX_W_3800_P_2) },
d5d7db8e 9136 { "(bad)", { XX } },
c0f3af97
L		 9137 },
9138
9139 /* VEX_LEN_3801_P_2 */
9140 {
9e30b8e0 9141 { VEX_W_TABLE (VEX_W_3801_P_2) },
d5d7db8e 9142 { "(bad)", { XX } },
c0f3af97
L		 9143 },
9144
9145 /* VEX_LEN_3802_P_2 */
9146 {
9e30b8e0 9147 { VEX_W_TABLE (VEX_W_3802_P_2) },
d5d7db8e 9148 { "(bad)", { XX } },
c0f3af97
L		 9149 },
9150
9151 /* VEX_LEN_3803_P_2 */
9152 {
9e30b8e0 9153 { VEX_W_TABLE (VEX_W_3803_P_2) },
d5d7db8e 9154 { "(bad)", { XX } },
c0f3af97
L		 9155 },
9156
9157 /* VEX_LEN_3804_P_2 */
9158 {
9e30b8e0 9159 { VEX_W_TABLE (VEX_W_3804_P_2) },
d5d7db8e 9160 { "(bad)", { XX } },
c0f3af97
L		 9161 },
9162
9163 /* VEX_LEN_3805_P_2 */
9164 {
9e30b8e0 9165 { VEX_W_TABLE (VEX_W_3805_P_2) },
d5d7db8e 9166 { "(bad)", { XX } },
c0f3af97
L		 9167 },
9168
9169 /* VEX_LEN_3806_P_2 */
9170 {
9e30b8e0 9171 { VEX_W_TABLE (VEX_W_3806_P_2) },
d5d7db8e 9172 { "(bad)", { XX } },
c0f3af97
L		 9173 },
9174
9175 /* VEX_LEN_3807_P_2 */
9176 {
9e30b8e0 9177 { VEX_W_TABLE (VEX_W_3807_P_2) },
d5d7db8e 9178 { "(bad)", { XX } },
c0f3af97
L		 9179 },
9180
9181 /* VEX_LEN_3808_P_2 */
9182 {
9e30b8e0 9183 { VEX_W_TABLE (VEX_W_3808_P_2) },
d5d7db8e 9184 { "(bad)", { XX } },
c0f3af97
L		 9185 },
9186
9187 /* VEX_LEN_3809_P_2 */
9188 {
9e30b8e0 9189 { VEX_W_TABLE (VEX_W_3809_P_2) },
d5d7db8e 9190 { "(bad)", { XX } },
c0f3af97
L		 9191 },
9192
9193 /* VEX_LEN_380A_P_2 */
9194 {
9e30b8e0 9195 { VEX_W_TABLE (VEX_W_380A_P_2) },
d5d7db8e 9196 { "(bad)", { XX } },
c0f3af97
L		 9197 },
9198
9199 /* VEX_LEN_380B_P_2 */
9200 {
9e30b8e0 9201 { VEX_W_TABLE (VEX_W_380B_P_2) },
d5d7db8e 9202 { "(bad)", { XX } },
c0f3af97
L		 9203 },
9204
9205 /* VEX_LEN_3819_P_2_M_0 */
9206 {
d5d7db8e 9207 { "(bad)", { XX } },
9e30b8e0 9208 { VEX_W_TABLE (VEX_W_3819_P_2_M_0) },
c0f3af97
L		 9209 },
9210
9211 /* VEX_LEN_381A_P_2_M_0 */
9212 {
d5d7db8e 9213 { "(bad)", { XX } },
9e30b8e0 9214 { VEX_W_TABLE (VEX_W_381A_P_2_M_0) },
c0f3af97
L		 9215 },
9216
9217 /* VEX_LEN_381C_P_2 */
9218 {
9e30b8e0 9219 { VEX_W_TABLE (VEX_W_381C_P_2) },
d5d7db8e 9220 { "(bad)", { XX } },
c0f3af97
L		 9221 },
9222
9223 /* VEX_LEN_381D_P_2 */
9224 {
9e30b8e0 9225 { VEX_W_TABLE (VEX_W_381D_P_2) },
d5d7db8e 9226 { "(bad)", { XX } },
c0f3af97
L		 9227 },
9228
9229 /* VEX_LEN_381E_P_2 */
9230 {
9e30b8e0 9231 { VEX_W_TABLE (VEX_W_381E_P_2) },
d5d7db8e 9232 { "(bad)", { XX } },
c0f3af97
L		 9233 },
9234
9235 /* VEX_LEN_3820_P_2 */
9236 {
9e30b8e0 9237 { VEX_W_TABLE (VEX_W_3820_P_2) },
d5d7db8e 9238 { "(bad)", { XX } },
c0f3af97
L		 9239 },
9240
9241 /* VEX_LEN_3821_P_2 */
9242 {
9e30b8e0 9243 { VEX_W_TABLE (VEX_W_3821_P_2) },
d5d7db8e 9244 { "(bad)", { XX } },
c0f3af97
L		 9245 },
9246
9247 /* VEX_LEN_3822_P_2 */
9248 {
9e30b8e0 9249 { VEX_W_TABLE (VEX_W_3822_P_2) },
d5d7db8e 9250 { "(bad)", { XX } },
c0f3af97
L		 9251 },
9252
9253 /* VEX_LEN_3823_P_2 */
9254 {
9e30b8e0 9255 { VEX_W_TABLE (VEX_W_3823_P_2) },
d5d7db8e 9256 { "(bad)", { XX } },
c0f3af97
L		 9257 },
9258
9259 /* VEX_LEN_3824_P_2 */
9260 {
9e30b8e0 9261 { VEX_W_TABLE (VEX_W_3824_P_2) },
d5d7db8e 9262 { "(bad)", { XX } },
c0f3af97
L		 9263 },
9264
9265 /* VEX_LEN_3825_P_2 */
9266 {
9e30b8e0 9267 { VEX_W_TABLE (VEX_W_3825_P_2) },
d5d7db8e 9268 { "(bad)", { XX } },
c0f3af97
L		 9269 },
9270
9271 /* VEX_LEN_3828_P_2 */
9272 {
9e30b8e0 9273 { VEX_W_TABLE (VEX_W_3828_P_2) },
d5d7db8e 9274 { "(bad)", { XX } },
c0f3af97
L		 9275 },
9276
9277 /* VEX_LEN_3829_P_2 */
9278 {
9e30b8e0 9279 { VEX_W_TABLE (VEX_W_3829_P_2) },
d5d7db8e 9280 { "(bad)", { XX } },
c0f3af97
L		 9281 },
9282
9283 /* VEX_LEN_382A_P_2_M_0 */
9284 {
9e30b8e0 9285 { VEX_W_TABLE (VEX_W_382A_P_2_M_0) },
d5d7db8e 9286 { "(bad)", { XX } },
c0f3af97
L		 9287 },
9288
9289 /* VEX_LEN_382B_P_2 */
9290 {
9e30b8e0 9291 { VEX_W_TABLE (VEX_W_382B_P_2) },
d5d7db8e 9292 { "(bad)", { XX } },
c0f3af97
L		 9293 },
9294
9295 /* VEX_LEN_3830_P_2 */
9296 {
9e30b8e0 9297 { VEX_W_TABLE (VEX_W_3830_P_2) },
d5d7db8e 9298 { "(bad)", { XX } },
c0f3af97
L		 9299 },
9300
9301 /* VEX_LEN_3831_P_2 */
9302 {
9e30b8e0 9303 { VEX_W_TABLE (VEX_W_3831_P_2) },
d5d7db8e 9304 { "(bad)", { XX } },
c0f3af97
L		 9305 },
9306
9307 /* VEX_LEN_3832_P_2 */
9308 {
9e30b8e0 9309 { VEX_W_TABLE (VEX_W_3832_P_2) },
d5d7db8e 9310 { "(bad)", { XX } },
c0f3af97
L		 9311 },
9312
9313 /* VEX_LEN_3833_P_2 */
9314 {
9e30b8e0 9315 { VEX_W_TABLE (VEX_W_3833_P_2) },
d5d7db8e 9316 { "(bad)", { XX } },
c0f3af97
L		 9317 },
9318
9319 /* VEX_LEN_3834_P_2 */
9320 {
9e30b8e0 9321 { VEX_W_TABLE (VEX_W_3834_P_2) },
d5d7db8e 9322 { "(bad)", { XX } },
c0f3af97
L		 9323 },
9324
9325 /* VEX_LEN_3835_P_2 */
9326 {
9e30b8e0 9327 { VEX_W_TABLE (VEX_W_3835_P_2) },
d5d7db8e 9328 { "(bad)", { XX } },
c0f3af97
L		 9329 },
9330
9331 /* VEX_LEN_3837_P_2 */
9332 {
9e30b8e0 9333 { VEX_W_TABLE (VEX_W_3837_P_2) },
d5d7db8e 9334 { "(bad)", { XX } },
c0f3af97
L		 9335 },
9336
9337 /* VEX_LEN_3838_P_2 */
9338 {
9e30b8e0 9339 { VEX_W_TABLE (VEX_W_3838_P_2) },
d5d7db8e 9340 { "(bad)", { XX } },
c0f3af97
L		 9341 },
9342
9343 /* VEX_LEN_3839_P_2 */
9344 {
9e30b8e0 9345 { VEX_W_TABLE (VEX_W_3839_P_2) },
d5d7db8e 9346 { "(bad)", { XX } },
c0f3af97
L		 9347 },
9348
9349 /* VEX_LEN_383A_P_2 */
9350 {
9e30b8e0 9351 { VEX_W_TABLE (VEX_W_383A_P_2) },
d5d7db8e 9352 { "(bad)", { XX } },
c0f3af97
L		 9353 },
9354
9355 /* VEX_LEN_383B_P_2 */
9356 {
9e30b8e0 9357 { VEX_W_TABLE (VEX_W_383B_P_2) },
d5d7db8e 9358 { "(bad)", { XX } },
c0f3af97
L		 9359 },
9360
9361 /* VEX_LEN_383C_P_2 */
9362 {
9e30b8e0 9363 { VEX_W_TABLE (VEX_W_383C_P_2) },
d5d7db8e 9364 { "(bad)", { XX } },
c0f3af97
L		 9365 },
9366
9367 /* VEX_LEN_383D_P_2 */
9368 {
9e30b8e0 9369 { VEX_W_TABLE (VEX_W_383D_P_2) },
d5d7db8e 9370 { "(bad)", { XX } },
c0f3af97
L		 9371 },
9372
9373 /* VEX_LEN_383E_P_2 */
9374 {
9e30b8e0 9375 { VEX_W_TABLE (VEX_W_383E_P_2) },
d5d7db8e 9376 { "(bad)", { XX } },
c0f3af97
L		 9377 },
9378
9379 /* VEX_LEN_383F_P_2 */
9380 {
9e30b8e0 9381 { VEX_W_TABLE (VEX_W_383F_P_2) },
d5d7db8e 9382 { "(bad)", { XX } },
c0f3af97
L		 9383 },
9384
9385 /* VEX_LEN_3840_P_2 */
9386 {
9e30b8e0 9387 { VEX_W_TABLE (VEX_W_3840_P_2) },
d5d7db8e 9388 { "(bad)", { XX } },
c0f3af97
L		 9389 },
9390
9391 /* VEX_LEN_3841_P_2 */
9392 {
9e30b8e0 9393 { VEX_W_TABLE (VEX_W_3841_P_2) },
d5d7db8e 9394 { "(bad)", { XX } },
c0f3af97
L		 9395 },
9396
a5ff0eb2
L		 9397 /* VEX_LEN_38DB_P_2 */
9398 {
9e30b8e0 9399 { VEX_W_TABLE (VEX_W_38DB_P_2) },
a5ff0eb2
L		 9400 { "(bad)", { XX } },
9401 },
9402
9403 /* VEX_LEN_38DC_P_2 */
9404 {
9e30b8e0 9405 { VEX_W_TABLE (VEX_W_38DC_P_2) },
a5ff0eb2
L		 9406 { "(bad)", { XX } },
9407 },
9408
9409 /* VEX_LEN_38DD_P_2 */
9410 {
9e30b8e0 9411 { VEX_W_TABLE (VEX_W_38DD_P_2) },
a5ff0eb2
L		 9412 { "(bad)", { XX } },
9413 },
9414
9415 /* VEX_LEN_38DE_P_2 */
9416 {
9e30b8e0 9417 { VEX_W_TABLE (VEX_W_38DE_P_2) },
a5ff0eb2
L		 9418 { "(bad)", { XX } },
9419 },
9420
9421 /* VEX_LEN_38DF_P_2 */
9422 {
9e30b8e0 9423 { VEX_W_TABLE (VEX_W_38DF_P_2) },
a5ff0eb2
L		 9424 { "(bad)", { XX } },
9425 },
9426
c0f3af97
L		 9427 /* VEX_LEN_3A06_P_2 */
9428 {
d5d7db8e 9429 { "(bad)", { XX } },
9e30b8e0 9430 { VEX_W_TABLE (VEX_W_3A06_P_2) },
c0f3af97
L		 9431 },
9432
9433 /* VEX_LEN_3A0A_P_2 */
9434 {
9e30b8e0 9435 { VEX_W_TABLE (VEX_W_3A0A_P_2) },
d5d7db8e 9436 { "(bad)", { XX } },
c0f3af97
L		 9437 },
9438
9439 /* VEX_LEN_3A0B_P_2 */
9440 {
9e30b8e0 9441 { VEX_W_TABLE (VEX_W_3A0B_P_2) },
d5d7db8e 9442 { "(bad)", { XX } },
c0f3af97
L		 9443 },
9444
9445 /* VEX_LEN_3A0E_P_2 */
9446 {
9e30b8e0 9447 { VEX_W_TABLE (VEX_W_3A0E_P_2) },
d5d7db8e 9448 { "(bad)", { XX } },
c0f3af97
L		 9449 },
9450
9451 /* VEX_LEN_3A0F_P_2 */
9452 {
9e30b8e0 9453 { VEX_W_TABLE (VEX_W_3A0F_P_2) },
d5d7db8e 9454 { "(bad)", { XX } },
c0f3af97
L		 9455 },
9456
9457 /* VEX_LEN_3A14_P_2 */
9458 {
9e30b8e0 9459 { VEX_W_TABLE (VEX_W_3A14_P_2) },
d5d7db8e 9460 { "(bad)", { XX } },
c0f3af97
L		 9461 },
9462
9463 /* VEX_LEN_3A15_P_2 */
9464 {
9e30b8e0 9465 { VEX_W_TABLE (VEX_W_3A15_P_2) },
d5d7db8e 9466 { "(bad)", { XX } },
c0f3af97
L		 9467 },
9468
9469 /* VEX_LEN_3A16_P_2 */
9470 {
9471 { "vpextrK", { Edq, XM, Ib } },
d5d7db8e 9472 { "(bad)", { XX } },
c0f3af97
L		 9473 },
9474
9475 /* VEX_LEN_3A17_P_2 */
9476 {
9477 { "vextractps", { Edqd, XM, Ib } },
d5d7db8e 9478 { "(bad)", { XX } },
c0f3af97
L		 9479 },
9480
9481 /* VEX_LEN_3A18_P_2 */
9482 {
d5d7db8e 9483 { "(bad)", { XX } },
9e30b8e0 9484 { VEX_W_TABLE (VEX_W_3A18_P_2) },
c0f3af97
L		 9485 },
9486
9487 /* VEX_LEN_3A19_P_2 */
9488 {
d5d7db8e 9489 { "(bad)", { XX } },
9e30b8e0 9490 { VEX_W_TABLE (VEX_W_3A19_P_2) },
c0f3af97
L		 9491 },
9492
9493 /* VEX_LEN_3A20_P_2 */
9494 {
9e30b8e0 9495 { VEX_W_TABLE (VEX_W_3A20_P_2) },
d5d7db8e 9496 { "(bad)", { XX } },
c0f3af97
L		 9497 },
9498
9499 /* VEX_LEN_3A21_P_2 */
9500 {
9e30b8e0 9501 { VEX_W_TABLE (VEX_W_3A21_P_2) },
d5d7db8e 9502 { "(bad)", { XX } },
c0f3af97
L		 9503 },
9504
9505 /* VEX_LEN_3A22_P_2 */
9506 {
9507 { "vpinsrK", { XM, Vex128, Edq, Ib } },
d5d7db8e 9508 { "(bad)", { XX } },
c0f3af97
L		 9509 },
9510
9511 /* VEX_LEN_3A41_P_2 */
9512 {
9e30b8e0 9513 { VEX_W_TABLE (VEX_W_3A41_P_2) },
d5d7db8e 9514 { "(bad)", { XX } },
c0f3af97
L		 9515 },
9516
9517 /* VEX_LEN_3A42_P_2 */
9518 {
9e30b8e0 9519 { VEX_W_TABLE (VEX_W_3A42_P_2) },
d5d7db8e 9520 { "(bad)", { XX } },
c0f3af97
L		 9521 },
9522
ce2f5b3c
L		 9523 /* VEX_LEN_3A44_P_2 */
9524 {
9e30b8e0 9525 { VEX_W_TABLE (VEX_W_3A44_P_2) },
ce2f5b3c
L		 9526 { "(bad)", { XX } },
9527 },
9528
c0f3af97
L		 9529 /* VEX_LEN_3A4C_P_2 */
9530 {
9e30b8e0 9531 { VEX_W_TABLE (VEX_W_3A4C_P_2) },
d5d7db8e 9532 { "(bad)", { XX } },
c0f3af97
L		 9533 },
9534
9535 /* VEX_LEN_3A60_P_2 */
9536 {
9e30b8e0 9537 { VEX_W_TABLE (VEX_W_3A60_P_2) },
d5d7db8e 9538 { "(bad)", { XX } },
c0f3af97
L		 9539 },
9540
9541 /* VEX_LEN_3A61_P_2 */
9542 {
9e30b8e0 9543 { VEX_W_TABLE (VEX_W_3A61_P_2) },
d5d7db8e 9544 { "(bad)", { XX } },
c0f3af97
L		 9545 },
9546
9547 /* VEX_LEN_3A62_P_2 */
9548 {
9e30b8e0 9549 { VEX_W_TABLE (VEX_W_3A62_P_2) },
d5d7db8e 9550 { "(bad)", { XX } },
c0f3af97
L		 9551 },
9552
9553 /* VEX_LEN_3A63_P_2 */
9554 {
9e30b8e0 9555 { VEX_W_TABLE (VEX_W_3A63_P_2) },
d5d7db8e 9556 { "(bad)", { XX } },
c0f3af97
L		 9557 },
9558
922d8de8
DR		 9559 /* VEX_LEN_3A6A_P_2 */
9560 {
206c2556 9561 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
922d8de8
DR		 9562 { "(bad)", { XX } },
9563 },
9564
9565 /* VEX_LEN_3A6B_P_2 */
9566 {
206c2556 9567 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
922d8de8
DR		 9568 { "(bad)", { XX } },
9569 },
9570
9571 /* VEX_LEN_3A6E_P_2 */
9572 {
206c2556 9573 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
922d8de8
DR		 9574 { "(bad)", { XX } },
9575 },
9576
9577 /* VEX_LEN_3A6F_P_2 */
9578 {
206c2556 9579 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
922d8de8
DR		 9580 { "(bad)", { XX } },
9581 },
9582
9583 /* VEX_LEN_3A7A_P_2 */
9584 {
206c2556 9585 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
922d8de8
DR		 9586 { "(bad)", { XX } },
9587 },
9588
9589 /* VEX_LEN_3A7B_P_2 */
9590 {
206c2556 9591 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
922d8de8
DR		 9592 { "(bad)", { XX } },
9593 },
9594
9595 /* VEX_LEN_3A7E_P_2 */
9596 {
206c2556 9597 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
922d8de8
DR		 9598 { "(bad)", { XX } },
9599 },
9600
9601 /* VEX_LEN_3A7F_P_2 */
9602 {
206c2556 9603 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
922d8de8
DR		 9604 { "(bad)", { XX } },
9605 },
9606
a5ff0eb2
L		 9607 /* VEX_LEN_3ADF_P_2 */
9608 {
9e30b8e0 9609 { VEX_W_TABLE (VEX_W_3ADF_P_2) },
a5ff0eb2
L		 9610 { "(bad)", { XX } },
9611 },
4c807e72 9612
5dd85c99
SP		 9613 /* VEX_LEN_XOP_09_80 */
9614 {
4c807e72
L		 9615 { "vfrczps", { XM, EXxmm } },
9616 { "vfrczps", { XM, EXymmq } },
5dd85c99 9617 },
4c807e72 9618
5dd85c99
SP		 9619 /* VEX_LEN_XOP_09_81 */
9620 {
4c807e72
L		 9621 { "vfrczpd", { XM, EXxmm } },
9622 { "vfrczpd", { XM, EXymmq } },
5dd85c99 9623 },
331d2d0d
L		 9624};
9625
9e30b8e0 9626static const struct dis386 vex_w_table[][2] = {
b844680a 9627 {
9e30b8e0
L		 9628 /* VEX_W_10_P_0 */
9629 { "vmovups", { XM, EXx } },
d8faab4e
L		 9630 { "(bad)", { XX } },
9631 },
9632 {
9e30b8e0
L		 9633 /* VEX_W_10_P_1 */
9634 { "vmovss", { XMVex, Vex128, EXd } },
9635 { "(bad)", { XX } },
d8faab4e
L		 9636 },
9637 {
9e30b8e0
L		 9638 /* VEX_W_10_P_2 */
9639 { "vmovupd", { XM, EXx } },
9640 { "(bad)", { XX } },
d8faab4e
L		 9641 },
9642 {
9e30b8e0
L		 9643 /* VEX_W_10_P_3 */
9644 { "vmovsd", { XMVex, Vex128, EXq } },
9645 { "(bad)", { XX } },
d8faab4e
L		 9646 },
9647 {
9e30b8e0
L		 9648 /* VEX_W_11_P_0 */
9649 { "vmovups", { EXxS, XM } },
9650 { "(bad)", { XX } },
d8faab4e
L		 9651 },
9652 {
9e30b8e0
L		 9653 /* VEX_W_11_P_1 */
9654 { "vmovss", { EXdVexS, Vex128, XM } },
9655 { "(bad)", { XX } },
b844680a
L		 9656 },
9657 {
9e30b8e0
L		 9658 /* VEX_W_11_P_2 */
9659 { "vmovupd", { EXxS, XM } },
9660 { "(bad)", { XX } },
b844680a
L		 9661 },
9662 {
9e30b8e0
L		 9663 /* VEX_W_11_P_3 */
9664 { "vmovsd", { EXqVexS, Vex128, XM } },
d8faab4e
L		 9665 { "(bad)", { XX } },
9666 },
9667 {
9e30b8e0
L		 9668 /* VEX_W_12_P_0_M_0 */
9669 { "vmovlps", { XM, Vex128, EXq } },
9670 { "(bad)", { XX } },
b844680a
L		 9671 },
9672 {
9e30b8e0
L		 9673 /* VEX_W_12_P_0_M_1 */
9674 { "vmovhlps", { XM, Vex128, EXq } },
b844680a
L		 9675 { "(bad)", { XX } },
9676 },
9677 {
9e30b8e0
L		 9678 /* VEX_W_12_P_1 */
9679 { "vmovsldup", { XM, EXx } },
b844680a 9680 { "(bad)", { XX } },
b844680a
L		 9681 },
9682 {
9e30b8e0
L		 9683 /* VEX_W_12_P_2 */
9684 { "vmovlpd", { XM, Vex128, EXq } },
92fddf8e 9685 { "(bad)", { XX } },
b844680a
L		 9686 },
9687 {
9e30b8e0
L		 9688 /* VEX_W_12_P_3 */
9689 { "vmovddup", { XM, EXymmq } },
92fddf8e 9690 { "(bad)", { XX } },
b844680a
L		 9691 },
9692 {
9e30b8e0
L		 9693 /* VEX_W_13_M_0 */
9694 { "vmovlpX", { EXq, XM } },
b844680a 9695 { "(bad)", { XX } },
b844680a
L		 9696 },
9697 {
9e30b8e0
L		 9698 /* VEX_W_14 */
9699 { "vunpcklpX", { XM, Vex, EXx } },
92fddf8e 9700 { "(bad)", { XX } },
b844680a
L		 9701 },
9702 {
9e30b8e0
L		 9703 /* VEX_W_15 */
9704 { "vunpckhpX", { XM, Vex, EXx } },
92fddf8e 9705 { "(bad)", { XX } },
b844680a
L		 9706 },
9707 {
9e30b8e0
L		 9708 /* VEX_W_16_P_0_M_0 */
9709 { "vmovhps", { XM, Vex128, EXq } },
b844680a 9710 { "(bad)", { XX } },
9e30b8e0
L		 9711 },
9712 {
9713 /* VEX_W_16_P_0_M_1 */
9714 { "vmovlhps", { XM, Vex128, EXq } },
9715 { "(bad)", { XX } },
9716 },
9717 {
9718 /* VEX_W_16_P_1 */
9719 { "vmovshdup", { XM, EXx } },
9720 { "(bad)", { XX } },
9721 },
9722 {
9723 /* VEX_W_16_P_2 */
9724 { "vmovhpd", { XM, Vex128, EXq } },
9725 { "(bad)", { XX } },
9726 },
9727 {
9728 /* VEX_W_17_M_0 */
9729 { "vmovhpX", { EXq, XM } },
9730 { "(bad)", { XX } },
9731 },
9732 {
9733 /* VEX_W_28 */
9734 { "vmovapX", { XM, EXx } },
9735 { "(bad)", { XX } },
9736 },
9737 {
9738 /* VEX_W_29 */
9739 { "vmovapX", { EXxS, XM } },
9740 { "(bad)", { XX } },
9741 },
9742 {
9743 /* VEX_W_2B_M_0 */
9744 { "vmovntpX", { Mx, XM } },
9745 { "(bad)", { XX } },
9746 },
9747 {
9748 /* VEX_W_2E_P_0 */
9749 { "vucomiss", { XM, EXd } },
9750 { "(bad)", { XX } },
9751 },
9752 {
9753 /* VEX_W_2E_P_2 */
9754 { "vucomisd", { XM, EXq } },
9755 { "(bad)", { XX } },
9756 },
9757 {
9758 /* VEX_W_2F_P_0 */
9759 { "vcomiss", { XM, EXd } },
9760 { "(bad)", { XX } },
9761 },
9762 {
9763 /* VEX_W_2F_P_2 */
9764 { "vcomisd", { XM, EXq } },
9765 { "(bad)", { XX } },
9766 },
9767 {
9768 /* VEX_W_50_M_0 */
9769 { "vmovmskpX", { Gdq, XS } },
9770 { "(bad)", { XX } },
9771 },
9772 {
9773 /* VEX_W_51_P_0 */
9774 { "vsqrtps", { XM, EXx } },
9775 { "(bad)", { XX } },
9776 },
9777 {
9778 /* VEX_W_51_P_1 */
9779 { "vsqrtss", { XM, Vex128, EXd } },
9780 { "(bad)", { XX } },
9781 },
9782 {
9783 /* VEX_W_51_P_2 */
9784 { "vsqrtpd", { XM, EXx } },
9785 { "(bad)", { XX } },
9786 },
9787 {
9788 /* VEX_W_51_P_3 */
9789 { "vsqrtsd", { XM, Vex128, EXq } },
9790 { "(bad)", { XX } },
9791 },
9792 {
9793 /* VEX_W_52_P_0 */
9794 { "vrsqrtps", { XM, EXx } },
9795 { "(bad)", { XX } },
9796 },
9797 {
9798 /* VEX_W_52_P_1 */
9799 { "vrsqrtss", { XM, Vex128, EXd } },
9800 { "(bad)", { XX } },
9801 },
9802 {
9803 /* VEX_W_53_P_0 */
9804 { "vrcpps", { XM, EXx } },
9805 { "(bad)", { XX } },
9806 },
9807 {
9808 /* VEX_W_53_P_1 */
9809 { "vrcpss", { XM, Vex128, EXd } },
9810 { "(bad)", { XX } },
9811 },
9812 {
9813 /* VEX_W_58_P_0 */
9814 { "vaddps", { XM, Vex, EXx } },
9815 { "(bad)", { XX } },
9816 },
9817 {
9818 /* VEX_W_58_P_1 */
9819 { "vaddss", { XM, Vex128, EXd } },
9820 { "(bad)", { XX } },
9821 },
9822 {
9823 /* VEX_W_58_P_2 */
9824 { "vaddpd", { XM, Vex, EXx } },
9825 { "(bad)", { XX } },
9826 },
9827 {
9828 /* VEX_W_58_P_3 */
9829 { "vaddsd", { XM, Vex128, EXq } },
9830 { "(bad)", { XX } },
9831 },
9832 {
9833 /* VEX_W_59_P_0 */
9834 { "vmulps", { XM, Vex, EXx } },
9835 { "(bad)", { XX } },
9836 },
9837 {
9838 /* VEX_W_59_P_1 */
9839 { "vmulss", { XM, Vex128, EXd } },
9840 { "(bad)", { XX } },
9841 },
9842 {
9843 /* VEX_W_59_P_2 */
9844 { "vmulpd", { XM, Vex, EXx } },
9845 { "(bad)", { XX } },
9846 },
9847 {
9848 /* VEX_W_59_P_3 */
9849 { "vmulsd", { XM, Vex128, EXq } },
9850 { "(bad)", { XX } },
9851 },
9852 {
9853 /* VEX_W_5A_P_0 */
9854 { "vcvtps2pd", { XM, EXxmmq } },
9855 { "(bad)", { XX } },
9856 },
9857 {
9858 /* VEX_W_5A_P_1 */
9859 { "vcvtss2sd", { XM, Vex128, EXd } },
9860 { "(bad)", { XX } },
9861 },
9862 {
9863 /* VEX_W_5A_P_3 */
9864 { "vcvtsd2ss", { XM, Vex128, EXq } },
9865 { "(bad)", { XX } },
9866 },
9867 {
9868 /* VEX_W_5B_P_0 */
9869 { "vcvtdq2ps", { XM, EXx } },
9870 { "(bad)", { XX } },
9871 },
9872 {
9873 /* VEX_W_5B_P_1 */
9874 { "vcvttps2dq", { XM, EXx } },
9875 { "(bad)", { XX } },
9876 },
9877 {
9878 /* VEX_W_5B_P_2 */
9879 { "vcvtps2dq", { XM, EXx } },
9880 { "(bad)", { XX } },
9881 },
9882 {
9883 /* VEX_W_5C_P_0 */
9884 { "vsubps", { XM, Vex, EXx } },
9885 { "(bad)", { XX } },
9886 },
9887 {
9888 /* VEX_W_5C_P_1 */
9889 { "vsubss", { XM, Vex128, EXd } },
9890 { "(bad)", { XX } },
9891 },
9892 {
9893 /* VEX_W_5C_P_2 */
9894 { "vsubpd", { XM, Vex, EXx } },
9895 { "(bad)", { XX } },
9896 },
9897 {
9898 /* VEX_W_5C_P_3 */
9899 { "vsubsd", { XM, Vex128, EXq } },
9900 { "(bad)", { XX } },
9901 },
9902 {
9903 /* VEX_W_5D_P_0 */
9904 { "vminps", { XM, Vex, EXx } },
9905 { "(bad)", { XX } },
9906 },
9907 {
9908 /* VEX_W_5D_P_1 */
9909 { "vminss", { XM, Vex128, EXd } },
9910 { "(bad)", { XX } },
9911 },
9912 {
9913 /* VEX_W_5D_P_2 */
9914 { "vminpd", { XM, Vex, EXx } },
9915 { "(bad)", { XX } },
9916 },
9917 {
9918 /* VEX_W_5D_P_3 */
9919 { "vminsd", { XM, Vex128, EXq } },
9920 { "(bad)", { XX } },
9921 },
9922 {
9923 /* VEX_W_5E_P_0 */
9924 { "vdivps", { XM, Vex, EXx } },
9925 { "(bad)", { XX } },
9926 },
9927 {
9928 /* VEX_W_5E_P_1 */
9929 { "vdivss", { XM, Vex128, EXd } },
9930 { "(bad)", { XX } },
9931 },
9932 {
9933 /* VEX_W_5E_P_2 */
9934 { "vdivpd", { XM, Vex, EXx } },
9935 { "(bad)", { XX } },
9936 },
9937 {
9938 /* VEX_W_5E_P_3 */
9939 { "vdivsd", { XM, Vex128, EXq } },
9940 { "(bad)", { XX } },
9941 },
9942 {
9943 /* VEX_W_5F_P_0 */
9944 { "vmaxps", { XM, Vex, EXx } },
9945 { "(bad)", { XX } },
9946 },
9947 {
9948 /* VEX_W_5F_P_1 */
9949 { "vmaxss", { XM, Vex128, EXd } },
9950 { "(bad)", { XX } },
9951 },
9952 {
9953 /* VEX_W_5F_P_2 */
9954 { "vmaxpd", { XM, Vex, EXx } },
9955 { "(bad)", { XX } },
9956 },
9957 {
9958 /* VEX_W_5F_P_3 */
9959 { "vmaxsd", { XM, Vex128, EXq } },
9960 { "(bad)", { XX } },
9961 },
9962 {
9963 /* VEX_W_60_P_2 */
9964 { "vpunpcklbw", { XM, Vex128, EXx } },
9965 { "(bad)", { XX } },
9966 },
9967 {
9968 /* VEX_W_61_P_2 */
9969 { "vpunpcklwd", { XM, Vex128, EXx } },
9970 { "(bad)", { XX } },
9971 },
9972 {
9973 /* VEX_W_62_P_2 */
9974 { "vpunpckldq", { XM, Vex128, EXx } },
9975 { "(bad)", { XX } },
9976 },
9977 {
9978 /* VEX_W_63_P_2 */
9979 { "vpacksswb", { XM, Vex128, EXx } },
9980 { "(bad)", { XX } },
9981 },
9982 {
9983 /* VEX_W_64_P_2 */
9984 { "vpcmpgtb", { XM, Vex128, EXx } },
9985 { "(bad)", { XX } },
9986 },
9987 {
9988 /* VEX_W_65_P_2 */
9989 { "vpcmpgtw", { XM, Vex128, EXx } },
9990 { "(bad)", { XX } },
9991 },
9992 {
9993 /* VEX_W_66_P_2 */
9994 { "vpcmpgtd", { XM, Vex128, EXx } },
9995 { "(bad)", { XX } },
9996 },
9997 {
9998 /* VEX_W_67_P_2 */
9999 { "vpackuswb", { XM, Vex128, EXx } },
10000 { "(bad)", { XX } },
10001 },
10002 {
10003 /* VEX_W_68_P_2 */
10004 { "vpunpckhbw", { XM, Vex128, EXx } },
10005 { "(bad)", { XX } },
10006 },
10007 {
10008 /* VEX_W_69_P_2 */
10009 { "vpunpckhwd", { XM, Vex128, EXx } },
10010 { "(bad)", { XX } },
10011 },
10012 {
10013 /* VEX_W_6A_P_2 */
10014 { "vpunpckhdq", { XM, Vex128, EXx } },
10015 { "(bad)", { XX } },
10016 },
10017 {
10018 /* VEX_W_6B_P_2 */
10019 { "vpackssdw", { XM, Vex128, EXx } },
10020 { "(bad)", { XX } },
10021 },
10022 {
10023 /* VEX_W_6C_P_2 */
10024 { "vpunpcklqdq", { XM, Vex128, EXx } },
10025 { "(bad)", { XX } },
10026 },
10027 {
10028 /* VEX_W_6D_P_2 */
10029 { "vpunpckhqdq", { XM, Vex128, EXx } },
10030 { "(bad)", { XX } },
10031 },
10032 {
10033 /* VEX_W_6F_P_1 */
efdb52b7 10034 { "vmovdqu", { XM, EXx } },
9e30b8e0
L		 10035 { "(bad)", { XX } },
10036 },
10037 {
10038 /* VEX_W_6F_P_2 */
efdb52b7 10039 { "vmovdqa", { XM, EXx } },
9e30b8e0
L		 10040 { "(bad)", { XX } },
10041 },
10042 {
10043 /* VEX_W_70_P_1 */
10044 { "vpshufhw", { XM, EXx, Ib } },
10045 { "(bad)", { XX } },
10046 },
10047 {
10048 /* VEX_W_70_P_2 */
10049 { "vpshufd", { XM, EXx, Ib } },
10050 { "(bad)", { XX } },
10051 },
10052 {
10053 /* VEX_W_70_P_3 */
10054 { "vpshuflw", { XM, EXx, Ib } },
10055 { "(bad)", { XX } },
10056 },
10057 {
10058 /* VEX_W_71_R_2_P_2 */
10059 { "vpsrlw", { Vex128, XS, Ib } },
10060 { "(bad)", { XX } },
10061 },
10062 {
10063 /* VEX_W_71_R_4_P_2 */
10064 { "vpsraw", { Vex128, XS, Ib } },
10065 { "(bad)", { XX } },
10066 },
10067 {
10068 /* VEX_W_71_R_6_P_2 */
10069 { "vpsllw", { Vex128, XS, Ib } },
10070 { "(bad)", { XX } },
10071 },
10072 {
10073 /* VEX_W_72_R_2_P_2 */
10074 { "vpsrld", { Vex128, XS, Ib } },
10075 { "(bad)", { XX } },
10076 },
10077 {
10078 /* VEX_W_72_R_4_P_2 */
10079 { "vpsrad", { Vex128, XS, Ib } },
10080 { "(bad)", { XX } },
10081 },
10082 {
10083 /* VEX_W_72_R_6_P_2 */
10084 { "vpslld", { Vex128, XS, Ib } },
10085 { "(bad)", { XX } },
10086 },
10087 {
10088 /* VEX_W_73_R_2_P_2 */
10089 { "vpsrlq", { Vex128, XS, Ib } },
10090 { "(bad)", { XX } },
10091 },
10092 {
10093 /* VEX_W_73_R_3_P_2 */
10094 { "vpsrldq", { Vex128, XS, Ib } },
10095 { "(bad)", { XX } },
10096 },
10097 {
10098 /* VEX_W_73_R_6_P_2 */
10099 { "vpsllq", { Vex128, XS, Ib } },
10100 { "(bad)", { XX } },
10101 },
10102 {
10103 /* VEX_W_73_R_7_P_2 */
10104 { "vpslldq", { Vex128, XS, Ib } },
10105 { "(bad)", { XX } },
10106 },
10107 {
10108 /* VEX_W_74_P_2 */
10109 { "vpcmpeqb", { XM, Vex128, EXx } },
10110 { "(bad)", { XX } },
10111 },
10112 {
10113 /* VEX_W_75_P_2 */
10114 { "vpcmpeqw", { XM, Vex128, EXx } },
10115 { "(bad)", { XX } },
10116 },
10117 {
10118 /* VEX_W_76_P_2 */
10119 { "vpcmpeqd", { XM, Vex128, EXx } },
10120 { "(bad)", { XX } },
10121 },
10122 {
10123 /* VEX_W_77_P_0 */
10124 { "", { VZERO } },
10125 { "(bad)", { XX } },
10126 },
10127 {
10128 /* VEX_W_7C_P_2 */
10129 { "vhaddpd", { XM, Vex, EXx } },
10130 { "(bad)", { XX } },
10131 },
10132 {
10133 /* VEX_W_7C_P_3 */
10134 { "vhaddps", { XM, Vex, EXx } },
10135 { "(bad)", { XX } },
10136 },
10137 {
10138 /* VEX_W_7D_P_2 */
10139 { "vhsubpd", { XM, Vex, EXx } },
10140 { "(bad)", { XX } },
10141 },
10142 {
10143 /* VEX_W_7D_P_3 */
10144 { "vhsubps", { XM, Vex, EXx } },
10145 { "(bad)", { XX } },
10146 },
10147 {
10148 /* VEX_W_7E_P_1 */
10149 { "vmovq", { XM, EXq } },
10150 { "(bad)", { XX } },
10151 },
10152 {
10153 /* VEX_W_7F_P_1 */
10154 { "vmovdqu", { EXxS, XM } },
10155 { "(bad)", { XX } },
10156 },
10157 {
10158 /* VEX_W_7F_P_2 */
10159 { "vmovdqa", { EXxS, XM } },
10160 { "(bad)", { XX } },
10161 },
10162 {
10163 /* VEX_W_AE_R_2_M_0 */
10164 { "vldmxcsr", { Md } },
10165 { "(bad)", { XX } },
10166 },
10167 {
10168 /* VEX_W_AE_R_3_M_0 */
10169 { "vstmxcsr", { Md } },
10170 { "(bad)", { XX } },
10171 },
10172 {
10173 /* VEX_W_C2_P_0 */
10174 { "vcmpps", { XM, Vex, EXx, VCMP } },
10175 { "(bad)", { XX } },
10176 },
10177 {
10178 /* VEX_W_C2_P_1 */
10179 { "vcmpss", { XM, Vex128, EXd, VCMP } },
10180 { "(bad)", { XX } },
10181 },
10182 {
10183 /* VEX_W_C2_P_2 */
10184 { "vcmppd", { XM, Vex, EXx, VCMP } },
10185 { "(bad)", { XX } },
10186 },
10187 {
10188 /* VEX_W_C2_P_3 */
10189 { "vcmpsd", { XM, Vex128, EXq, VCMP } },
10190 { "(bad)", { XX } },
10191 },
10192 {
10193 /* VEX_W_C4_P_2 */
10194 { "vpinsrw", { XM, Vex128, Edqw, Ib } },
10195 { "(bad)", { XX } },
10196 },
10197 {
10198 /* VEX_W_C5_P_2 */
10199 { "vpextrw", { Gdq, XS, Ib } },
10200 { "(bad)", { XX } },
10201 },
10202 {
10203 /* VEX_W_D0_P_2 */
10204 { "vaddsubpd", { XM, Vex, EXx } },
10205 { "(bad)", { XX } },
10206 },
10207 {
10208 /* VEX_W_D0_P_3 */
10209 { "vaddsubps", { XM, Vex, EXx } },
10210 { "(bad)", { XX } },
10211 },
10212 {
10213 /* VEX_W_D1_P_2 */
10214 { "vpsrlw", { XM, Vex128, EXx } },
10215 { "(bad)", { XX } },
10216 },
10217 {
10218 /* VEX_W_D2_P_2 */
10219 { "vpsrld", { XM, Vex128, EXx } },
10220 { "(bad)", { XX } },
10221 },
10222 {
10223 /* VEX_W_D3_P_2 */
10224 { "vpsrlq", { XM, Vex128, EXx } },
10225 { "(bad)", { XX } },
10226 },
10227 {
10228 /* VEX_W_D4_P_2 */
10229 { "vpaddq", { XM, Vex128, EXx } },
10230 { "(bad)", { XX } },
10231 },
10232 {
10233 /* VEX_W_D5_P_2 */
10234 { "vpmullw", { XM, Vex128, EXx } },
10235 { "(bad)", { XX } },
10236 },
10237 {
10238 /* VEX_W_D6_P_2 */
10239 { "vmovq", { EXqS, XM } },
10240 { "(bad)", { XX } },
10241 },
10242 {
10243 /* VEX_W_D7_P_2_M_1 */
10244 { "vpmovmskb", { Gdq, XS } },
10245 { "(bad)", { XX } },
10246 },
10247 {
10248 /* VEX_W_D8_P_2 */
10249 { "vpsubusb", { XM, Vex128, EXx } },
10250 { "(bad)", { XX } },
10251 },
10252 {
10253 /* VEX_W_D9_P_2 */
10254 { "vpsubusw", { XM, Vex128, EXx } },
10255 { "(bad)", { XX } },
10256 },
10257 {
10258 /* VEX_W_DA_P_2 */
10259 { "vpminub", { XM, Vex128, EXx } },
10260 { "(bad)", { XX } },
10261 },
10262 {
10263 /* VEX_W_DB_P_2 */
10264 { "vpand", { XM, Vex128, EXx } },
10265 { "(bad)", { XX } },
10266 },
10267 {
10268 /* VEX_W_DC_P_2 */
10269 { "vpaddusb", { XM, Vex128, EXx } },
10270 { "(bad)", { XX } },
10271 },
10272 {
10273 /* VEX_W_DD_P_2 */
10274 { "vpaddusw", { XM, Vex128, EXx } },
10275 { "(bad)", { XX } },
10276 },
10277 {
10278 /* VEX_W_DE_P_2 */
10279 { "vpmaxub", { XM, Vex128, EXx } },
10280 { "(bad)", { XX } },
10281 },
10282 {
10283 /* VEX_W_DF_P_2 */
10284 { "vpandn", { XM, Vex128, EXx } },
10285 { "(bad)", { XX } },
10286 },
10287 {
10288 /* VEX_W_E0_P_2 */
10289 { "vpavgb", { XM, Vex128, EXx } },
10290 { "(bad)", { XX } },
10291 },
10292 {
10293 /* VEX_W_E1_P_2 */
10294 { "vpsraw", { XM, Vex128, EXx } },
10295 { "(bad)", { XX } },
10296 },
10297 {
10298 /* VEX_W_E2_P_2 */
10299 { "vpsrad", { XM, Vex128, EXx } },
10300 { "(bad)", { XX } },
10301 },
10302 {
10303 /* VEX_W_E3_P_2 */
10304 { "vpavgw", { XM, Vex128, EXx } },
10305 { "(bad)", { XX } },
10306 },
10307 {
10308 /* VEX_W_E4_P_2 */
10309 { "vpmulhuw", { XM, Vex128, EXx } },
10310 { "(bad)", { XX } },
10311 },
10312 {
10313 /* VEX_W_E5_P_2 */
10314 { "vpmulhw", { XM, Vex128, EXx } },
10315 { "(bad)", { XX } },
10316 },
10317 {
10318 /* VEX_W_E6_P_1 */
efdb52b7 10319 { "vcvtdq2pd", { XM, EXxmmq } },
9e30b8e0
L		 10320 { "(bad)", { XX } },
10321 },
10322 {
10323 /* VEX_W_E6_P_2 */
a179a9fd 10324 { "vcvttpd2dq%XY", { XMM, EXx } },
9e30b8e0
L		 10325 { "(bad)", { XX } },
10326 },
10327 {
10328 /* VEX_W_E6_P_3 */
a179a9fd 10329 { "vcvtpd2dq%XY", { XMM, EXx } },
9e30b8e0
L		 10330 { "(bad)", { XX } },
10331 },
10332 {
10333 /* VEX_W_E7_P_2_M_0 */
10334 { "vmovntdq", { Mx, XM } },
10335 { "(bad)", { XX } },
10336 },
10337 {
10338 /* VEX_W_E8_P_2 */
10339 { "vpsubsb", { XM, Vex128, EXx } },
10340 { "(bad)", { XX } },
10341 },
10342 {
10343 /* VEX_W_E9_P_2 */
10344 { "vpsubsw", { XM, Vex128, EXx } },
10345 { "(bad)", { XX } },
10346 },
10347 {
10348 /* VEX_W_EA_P_2 */
10349 { "vpminsw", { XM, Vex128, EXx } },
10350 { "(bad)", { XX } },
10351 },
10352 {
10353 /* VEX_W_EB_P_2 */
10354 { "vpor", { XM, Vex128, EXx } },
10355 { "(bad)", { XX } },
10356 },
10357 {
10358 /* VEX_W_EC_P_2 */
10359 { "vpaddsb", { XM, Vex128, EXx } },
10360 { "(bad)", { XX } },
10361 },
10362 {
10363 /* VEX_W_ED_P_2 */
10364 { "vpaddsw", { XM, Vex128, EXx } },
10365 { "(bad)", { XX } },
10366 },
10367 {
10368 /* VEX_W_EE_P_2 */
10369 { "vpmaxsw", { XM, Vex128, EXx } },
10370 { "(bad)", { XX } },
10371 },
10372 {
10373 /* VEX_W_EF_P_2 */
10374 { "vpxor", { XM, Vex128, EXx } },
10375 { "(bad)", { XX } },
10376 },
10377 {
10378 /* VEX_W_F0_P_3_M_0 */
10379 { "vlddqu", { XM, M } },
10380 { "(bad)", { XX } },
10381 },
10382 {
10383 /* VEX_W_F1_P_2 */
10384 { "vpsllw", { XM, Vex128, EXx } },
10385 { "(bad)", { XX } },
10386 },
10387 {
10388 /* VEX_W_F2_P_2 */
10389 { "vpslld", { XM, Vex128, EXx } },
10390 { "(bad)", { XX } },
10391 },
10392 {
10393 /* VEX_W_F3_P_2 */
10394 { "vpsllq", { XM, Vex128, EXx } },
10395 { "(bad)", { XX } },
10396 },
10397 {
10398 /* VEX_W_F4_P_2 */
10399 { "vpmuludq", { XM, Vex128, EXx } },
10400 { "(bad)", { XX } },
10401 },
10402 {
10403 /* VEX_W_F5_P_2 */
10404 { "vpmaddwd", { XM, Vex128, EXx } },
10405 { "(bad)", { XX } },
10406 },
10407 {
10408 /* VEX_W_F6_P_2 */
10409 { "vpsadbw", { XM, Vex128, EXx } },
10410 { "(bad)", { XX } },
10411 },
10412 {
10413 /* VEX_W_F7_P_2 */
10414 { "vmaskmovdqu", { XM, XS } },
10415 { "(bad)", { XX } },
10416 },
10417 {
10418 /* VEX_W_F8_P_2 */
10419 { "vpsubb", { XM, Vex128, EXx } },
10420 { "(bad)", { XX } },
10421 },
10422 {
10423 /* VEX_W_F9_P_2 */
10424 { "vpsubw", { XM, Vex128, EXx } },
10425 { "(bad)", { XX } },
10426 },
10427 {
10428 /* VEX_W_FA_P_2 */
10429 { "vpsubd", { XM, Vex128, EXx } },
10430 { "(bad)", { XX } },
10431 },
10432 {
10433 /* VEX_W_FB_P_2 */
10434 { "vpsubq", { XM, Vex128, EXx } },
10435 { "(bad)", { XX } },
10436 },
10437 {
10438 /* VEX_W_FC_P_2 */
10439 { "vpaddb", { XM, Vex128, EXx } },
10440 { "(bad)", { XX } },
10441 },
10442 {
10443 /* VEX_W_FD_P_2 */
10444 { "vpaddw", { XM, Vex128, EXx } },
10445 { "(bad)", { XX } },
10446 },
10447 {
10448 /* VEX_W_FE_P_2 */
10449 { "vpaddd", { XM, Vex128, EXx } },
10450 { "(bad)", { XX } },
10451 },
10452 {
10453 /* VEX_W_3800_P_2 */
10454 { "vpshufb", { XM, Vex128, EXx } },
10455 { "(bad)", { XX } },
10456 },
10457 {
10458 /* VEX_W_3801_P_2 */
10459 { "vphaddw", { XM, Vex128, EXx } },
10460 { "(bad)", { XX } },
10461 },
10462 {
10463 /* VEX_W_3802_P_2 */
10464 { "vphaddd", { XM, Vex128, EXx } },
10465 { "(bad)", { XX } },
10466 },
10467 {
10468 /* VEX_W_3803_P_2 */
10469 { "vphaddsw", { XM, Vex128, EXx } },
10470 { "(bad)", { XX } },
10471 },
10472 {
10473 /* VEX_W_3804_P_2 */
10474 { "vpmaddubsw", { XM, Vex128, EXx } },
10475 { "(bad)", { XX } },
10476 },
10477 {
10478 /* VEX_W_3805_P_2 */
10479 { "vphsubw", { XM, Vex128, EXx } },
10480 { "(bad)", { XX } },
10481 },
10482 {
10483 /* VEX_W_3806_P_2 */
10484 { "vphsubd", { XM, Vex128, EXx } },
10485 { "(bad)", { XX } },
10486 },
10487 {
10488 /* VEX_W_3807_P_2 */
10489 { "vphsubsw", { XM, Vex128, EXx } },
10490 { "(bad)", { XX } },
10491 },
10492 {
10493 /* VEX_W_3808_P_2 */
10494 { "vpsignb", { XM, Vex128, EXx } },
10495 { "(bad)", { XX } },
10496 },
10497 {
10498 /* VEX_W_3809_P_2 */
10499 { "vpsignw", { XM, Vex128, EXx } },
10500 { "(bad)", { XX } },
10501 },
10502 {
10503 /* VEX_W_380A_P_2 */
10504 { "vpsignd", { XM, Vex128, EXx } },
10505 { "(bad)", { XX } },
10506 },
10507 {
10508 /* VEX_W_380B_P_2 */
10509 { "vpmulhrsw", { XM, Vex128, EXx } },
10510 { "(bad)", { XX } },
10511 },
10512 {
10513 /* VEX_W_380C_P_2 */
10514 { "vpermilps", { XM, Vex, EXx } },
10515 { "(bad)", { XX } },
10516 },
10517 {
10518 /* VEX_W_380D_P_2 */
10519 { "vpermilpd", { XM, Vex, EXx } },
10520 { "(bad)", { XX } },
10521 },
10522 {
10523 /* VEX_W_380E_P_2 */
10524 { "vtestps", { XM, EXx } },
10525 { "(bad)", { XX } },
10526 },
10527 {
10528 /* VEX_W_380F_P_2 */
10529 { "vtestpd", { XM, EXx } },
10530 { "(bad)", { XX } },
10531 },
10532 {
10533 /* VEX_W_3817_P_2 */
10534 { "vptest", { XM, EXx } },
10535 { "(bad)", { XX } },
10536 },
bcf2684f
L		 10537 {
10538 /* VEX_W_3818_P_2_M_0 */
10539 { "vbroadcastss", { XM, Md } },
10540 { "(bad)", { XX } },
10541 },
9e30b8e0
L		 10542 {
10543 /* VEX_W_3819_P_2_M_0 */
10544 { "vbroadcastsd", { XM, Mq } },
10545 { "(bad)", { XX } },
10546 },
10547 {
10548 /* VEX_W_381A_P_2_M_0 */
10549 { "vbroadcastf128", { XM, Mxmm } },
10550 { "(bad)", { XX } },
10551 },
10552 {
10553 /* VEX_W_381C_P_2 */
10554 { "vpabsb", { XM, EXx } },
10555 { "(bad)", { XX } },
10556 },
10557 {
10558 /* VEX_W_381D_P_2 */
10559 { "vpabsw", { XM, EXx } },
10560 { "(bad)", { XX } },
10561 },
10562 {
10563 /* VEX_W_381E_P_2 */
10564 { "vpabsd", { XM, EXx } },
10565 { "(bad)", { XX } },
10566 },
10567 {
10568 /* VEX_W_3820_P_2 */
10569 { "vpmovsxbw", { XM, EXq } },
10570 { "(bad)", { XX } },
10571 },
10572 {
10573 /* VEX_W_3821_P_2 */
10574 { "vpmovsxbd", { XM, EXd } },
10575 { "(bad)", { XX } },
10576 },
10577 {
10578 /* VEX_W_3822_P_2 */
10579 { "vpmovsxbq", { XM, EXw } },
10580 { "(bad)", { XX } },
10581 },
10582 {
10583 /* VEX_W_3823_P_2 */
10584 { "vpmovsxwd", { XM, EXq } },
10585 { "(bad)", { XX } },
10586 },
10587 {
10588 /* VEX_W_3824_P_2 */
10589 { "vpmovsxwq", { XM, EXd } },
10590 { "(bad)", { XX } },
10591 },
10592 {
10593 /* VEX_W_3825_P_2 */
10594 { "vpmovsxdq", { XM, EXq } },
10595 { "(bad)", { XX } },
10596 },
10597 {
10598 /* VEX_W_3828_P_2 */
10599 { "vpmuldq", { XM, Vex128, EXx } },
10600 { "(bad)", { XX } },
10601 },
10602 {
10603 /* VEX_W_3829_P_2 */
10604 { "vpcmpeqq", { XM, Vex128, EXx } },
10605 { "(bad)", { XX } },
10606 },
10607 {
10608 /* VEX_W_382A_P_2_M_0 */
10609 { "vmovntdqa", { XM, Mx } },
10610 { "(bad)", { XX } },
10611 },
10612 {
10613 /* VEX_W_382B_P_2 */
10614 { "vpackusdw", { XM, Vex128, EXx } },
10615 { "(bad)", { XX } },
10616 },
53aa04a0
L		 10617 {
10618 /* VEX_W_382C_P_2_M_0 */
10619 { "vmaskmovps", { XM, Vex, Mx } },
10620 { "(bad)", { XX } },
10621 },
10622 {
10623 /* VEX_W_382D_P_2_M_0 */
10624 { "vmaskmovpd", { XM, Vex, Mx } },
10625 { "(bad)", { XX } },
10626 },
10627 {
10628 /* VEX_W_382E_P_2_M_0 */
10629 { "vmaskmovps", { Mx, Vex, XM } },
10630 { "(bad)", { XX } },
10631 },
10632 {
10633 /* VEX_W_382F_P_2_M_0 */
10634 { "vmaskmovpd", { Mx, Vex, XM } },
10635 { "(bad)", { XX } },
10636 },
9e30b8e0
L		 10637 {
10638 /* VEX_W_3830_P_2 */
10639 { "vpmovzxbw", { XM, EXq } },
10640 { "(bad)", { XX } },
10641 },
10642 {
10643 /* VEX_W_3831_P_2 */
10644 { "vpmovzxbd", { XM, EXd } },
10645 { "(bad)", { XX } },
10646 },
10647 {
10648 /* VEX_W_3832_P_2 */
10649 { "vpmovzxbq", { XM, EXw } },
10650 { "(bad)", { XX } },
10651 },
10652 {
10653 /* VEX_W_3833_P_2 */
10654 { "vpmovzxwd", { XM, EXq } },
10655 { "(bad)", { XX } },
10656 },
10657 {
10658 /* VEX_W_3834_P_2 */
10659 { "vpmovzxwq", { XM, EXd } },
10660 { "(bad)", { XX } },
10661 },
10662 {
10663 /* VEX_W_3835_P_2 */
10664 { "vpmovzxdq", { XM, EXq } },
10665 { "(bad)", { XX } },
10666 },
10667 {
10668 /* VEX_W_3837_P_2 */
10669 { "vpcmpgtq", { XM, Vex128, EXx } },
10670 { "(bad)", { XX } },
10671 },
10672 {
10673 /* VEX_W_3838_P_2 */
10674 { "vpminsb", { XM, Vex128, EXx } },
10675 { "(bad)", { XX } },
10676 },
10677 {
10678 /* VEX_W_3839_P_2 */
10679 { "vpminsd", { XM, Vex128, EXx } },
10680 { "(bad)", { XX } },
10681 },
10682 {
10683 /* VEX_W_383A_P_2 */
10684 { "vpminuw", { XM, Vex128, EXx } },
10685 { "(bad)", { XX } },
10686 },
10687 {
10688 /* VEX_W_383B_P_2 */
10689 { "vpminud", { XM, Vex128, EXx } },
10690 { "(bad)", { XX } },
10691 },
10692 {
10693 /* VEX_W_383C_P_2 */
10694 { "vpmaxsb", { XM, Vex128, EXx } },
10695 { "(bad)", { XX } },
10696 },
10697 {
10698 /* VEX_W_383D_P_2 */
10699 { "vpmaxsd", { XM, Vex128, EXx } },
10700 { "(bad)", { XX } },
10701 },
10702 {
10703 /* VEX_W_383E_P_2 */
10704 { "vpmaxuw", { XM, Vex128, EXx } },
10705 { "(bad)", { XX } },
10706 },
10707 {
10708 /* VEX_W_383F_P_2 */
10709 { "vpmaxud", { XM, Vex128, EXx } },
10710 { "(bad)", { XX } },
10711 },
10712 {
10713 /* VEX_W_3840_P_2 */
10714 { "vpmulld", { XM, Vex128, EXx } },
10715 { "(bad)", { XX } },
10716 },
10717 {
10718 /* VEX_W_3841_P_2 */
10719 { "vphminposuw", { XM, EXx } },
10720 { "(bad)", { XX } },
10721 },
10722 {
10723 /* VEX_W_38DB_P_2 */
10724 { "vaesimc", { XM, EXx } },
10725 { "(bad)", { XX } },
10726 },
10727 {
10728 /* VEX_W_38DC_P_2 */
10729 { "vaesenc", { XM, Vex128, EXx } },
10730 { "(bad)", { XX } },
10731 },
10732 {
10733 /* VEX_W_38DD_P_2 */
10734 { "vaesenclast", { XM, Vex128, EXx } },
10735 { "(bad)", { XX } },
10736 },
10737 {
10738 /* VEX_W_38DE_P_2 */
10739 { "vaesdec", { XM, Vex128, EXx } },
10740 { "(bad)", { XX } },
10741 },
10742 {
10743 /* VEX_W_38DF_P_2 */
10744 { "vaesdeclast", { XM, Vex128, EXx } },
10745 { "(bad)", { XX } },
10746 },
10747 {
10748 /* VEX_W_3A04_P_2 */
10749 { "vpermilps", { XM, EXx, Ib } },
10750 { "(bad)", { XX } },
10751 },
10752 {
10753 /* VEX_W_3A05_P_2 */
10754 { "vpermilpd", { XM, EXx, Ib } },
10755 { "(bad)", { XX } },
10756 },
10757 {
10758 /* VEX_W_3A06_P_2 */
10759 { "vperm2f128", { XM, Vex256, EXx, Ib } },
10760 { "(bad)", { XX } },
10761 },
10762 {
10763 /* VEX_W_3A08_P_2 */
10764 { "vroundps", { XM, EXx, Ib } },
10765 { "(bad)", { XX } },
10766 },
10767 {
10768 /* VEX_W_3A09_P_2 */
10769 { "vroundpd", { XM, EXx, Ib } },
10770 { "(bad)", { XX } },
10771 },
10772 {
10773 /* VEX_W_3A0A_P_2 */
10774 { "vroundss", { XM, Vex128, EXd, Ib } },
10775 { "(bad)", { XX } },
10776 },
10777 {
10778 /* VEX_W_3A0B_P_2 */
10779 { "vroundsd", { XM, Vex128, EXq, Ib } },
10780 { "(bad)", { XX } },
10781 },
10782 {
10783 /* VEX_W_3A0C_P_2 */
10784 { "vblendps", { XM, Vex, EXx, Ib } },
10785 { "(bad)", { XX } },
10786 },
10787 {
10788 /* VEX_W_3A0D_P_2 */
10789 { "vblendpd", { XM, Vex, EXx, Ib } },
10790 { "(bad)", { XX } },
10791 },
10792 {
10793 /* VEX_W_3A0E_P_2 */
10794 { "vpblendw", { XM, Vex128, EXx, Ib } },
10795 { "(bad)", { XX } },
10796 },
10797 {
10798 /* VEX_W_3A0F_P_2 */
10799 { "vpalignr", { XM, Vex128, EXx, Ib } },
10800 { "(bad)", { XX } },
10801 },
10802 {
10803 /* VEX_W_3A14_P_2 */
10804 { "vpextrb", { Edqb, XM, Ib } },
10805 { "(bad)", { XX } },
10806 },
10807 {
10808 /* VEX_W_3A15_P_2 */
10809 { "vpextrw", { Edqw, XM, Ib } },
10810 { "(bad)", { XX } },
10811 },
10812 {
10813 /* VEX_W_3A18_P_2 */
10814 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
10815 { "(bad)", { XX } },
10816 },
10817 {
10818 /* VEX_W_3A19_P_2 */
10819 { "vextractf128", { EXxmm, XM, Ib } },
10820 { "(bad)", { XX } },
10821 },
10822 {
10823 /* VEX_W_3A20_P_2 */
10824 { "vpinsrb", { XM, Vex128, Edqb, Ib } },
10825 { "(bad)", { XX } },
10826 },
10827 {
10828 /* VEX_W_3A21_P_2 */
10829 { "vinsertps", { XM, Vex128, EXd, Ib } },
10830 { "(bad)", { XX } },
10831 },
10832 {
10833 /* VEX_W_3A40_P_2 */
10834 { "vdpps", { XM, Vex, EXx, Ib } },
10835 { "(bad)", { XX } },
10836 },
10837 {
10838 /* VEX_W_3A41_P_2 */
10839 { "vdppd", { XM, Vex128, EXx, Ib } },
10840 { "(bad)", { XX } },
10841 },
10842 {
10843 /* VEX_W_3A42_P_2 */
10844 { "vmpsadbw", { XM, Vex128, EXx, Ib } },
10845 { "(bad)", { XX } },
10846 },
10847 {
10848 /* VEX_W_3A44_P_2 */
10849 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } },
10850 { "(bad)", { XX } },
10851 },
10852 {
10853 /* VEX_W_3A4A_P_2 */
10854 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
10855 { "(bad)", { XX } },
10856 },
10857 {
10858 /* VEX_W_3A4B_P_2 */
10859 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
10860 { "(bad)", { XX } },
10861 },
10862 {
10863 /* VEX_W_3A4C_P_2 */
10864 { "vpblendvb", { XM, Vex128, EXx, XMVexI4 } },
10865 { "(bad)", { XX } },
10866 },
10867 {
10868 /* VEX_W_3A60_P_2 */
10869 { "vpcmpestrm", { XM, EXx, Ib } },
10870 { "(bad)", { XX } },
10871 },
10872 {
10873 /* VEX_W_3A61_P_2 */
10874 { "vpcmpestri", { XM, EXx, Ib } },
10875 { "(bad)", { XX } },
10876 },
10877 {
10878 /* VEX_W_3A62_P_2 */
10879 { "vpcmpistrm", { XM, EXx, Ib } },
10880 { "(bad)", { XX } },
10881 },
10882 {
10883 /* VEX_W_3A63_P_2 */
10884 { "vpcmpistri", { XM, EXx, Ib } },
10885 { "(bad)", { XX } },
10886 },
10887 {
10888 /* VEX_W_3ADF_P_2 */
10889 { "vaeskeygenassist", { XM, EXx, Ib } },
10890 { "(bad)", { XX } },
10891 },
10892};
10893
10894static const struct dis386 mod_table[][2] = {
10895 {
10896 /* MOD_8D */
10897 { "leaS", { Gv, M } },
10898 { "(bad)", { XX } },
10899 },
10900 {
10901 /* MOD_0F01_REG_0 */
10902 { X86_64_TABLE (X86_64_0F01_REG_0) },
10903 { RM_TABLE (RM_0F01_REG_0) },
10904 },
10905 {
10906 /* MOD_0F01_REG_1 */
10907 { X86_64_TABLE (X86_64_0F01_REG_1) },
10908 { RM_TABLE (RM_0F01_REG_1) },
10909 },
10910 {
10911 /* MOD_0F01_REG_2 */
10912 { X86_64_TABLE (X86_64_0F01_REG_2) },
10913 { RM_TABLE (RM_0F01_REG_2) },
10914 },
10915 {
10916 /* MOD_0F01_REG_3 */
10917 { X86_64_TABLE (X86_64_0F01_REG_3) },
10918 { RM_TABLE (RM_0F01_REG_3) },
10919 },
10920 {
10921 /* MOD_0F01_REG_7 */
10922 { "invlpg", { Mb } },
10923 { RM_TABLE (RM_0F01_REG_7) },
10924 },
10925 {
10926 /* MOD_0F12_PREFIX_0 */
10927 { "movlps", { XM, EXq } },
10928 { "movhlps", { XM, EXq } },
10929 },
10930 {
10931 /* MOD_0F13 */
10932 { "movlpX", { EXq, XM } },
10933 { "(bad)", { XX } },
10934 },
10935 {
10936 /* MOD_0F16_PREFIX_0 */
10937 { "movhps", { XM, EXq } },
10938 { "movlhps", { XM, EXq } },
10939 },
10940 {
10941 /* MOD_0F17 */
10942 { "movhpX", { EXq, XM } },
10943 { "(bad)", { XX } },
10944 },
10945 {
10946 /* MOD_0F18_REG_0 */
10947 { "prefetchnta", { Mb } },
10948 { "(bad)", { XX } },
10949 },
10950 {
10951 /* MOD_0F18_REG_1 */
10952 { "prefetcht0", { Mb } },
10953 { "(bad)", { XX } },
10954 },
10955 {
10956 /* MOD_0F18_REG_2 */
10957 { "prefetcht1", { Mb } },
10958 { "(bad)", { XX } },
10959 },
10960 {
10961 /* MOD_0F18_REG_3 */
10962 { "prefetcht2", { Mb } },
10963 { "(bad)", { XX } },
10964 },
10965 {
10966 /* MOD_0F20 */
10967 { "(bad)", { XX } },
10968 { "movZ", { Rm, Cm } },
10969 },
10970 {
10971 /* MOD_0F21 */
10972 { "(bad)", { XX } },
10973 { "movZ", { Rm, Dm } },
10974 },
10975 {
10976 /* MOD_0F22 */
10977 { "(bad)", { XX } },
10978 { "movZ", { Cm, Rm } },
b844680a
L		 10979 },
10980 {
92fddf8e 10981 /* MOD_0F23 */
b844680a 10982 { "(bad)", { XX } },
92fddf8e 10983 { "movZ", { Dm, Rm } },
b844680a
L		 10984 },
10985 {
92fddf8e 10986 /* MOD_0F24 */
c1e679ec 10987 { "(bad)", { XX } },
92fddf8e 10988 { "movL", { Rd, Td } },
b844680a
L		 10989 },
10990 {
92fddf8e 10991 /* MOD_0F26 */
b844680a 10992 { "(bad)", { XX } },
92fddf8e 10993 { "movL", { Td, Rd } },
b844680a 10994 },
75c135a8
L		 10995 {
10996 /* MOD_0F2B_PREFIX_0 */
4ee52178 10997 {"movntps", { Mx, XM } },
75c135a8
L		 10998 { "(bad)", { XX } },
10999 },
11000 {
11001 /* MOD_0F2B_PREFIX_1 */
4ee52178 11002 {"movntss", { Md, XM } },
75c135a8
L		 11003 { "(bad)", { XX } },
11004 },
11005 {
11006 /* MOD_0F2B_PREFIX_2 */
4ee52178 11007 {"movntpd", { Mx, XM } },
75c135a8
L		 11008 { "(bad)", { XX } },
11009 },
11010 {
11011 /* MOD_0F2B_PREFIX_3 */
4ee52178 11012 {"movntsd", { Mq, XM } },
75c135a8
L		 11013 { "(bad)", { XX } },
11014 },
11015 {
11016 /* MOD_0F51 */
11017 { "(bad)", { XX } },
11018 { "movmskpX", { Gdq, XS } },
11019 },
b844680a 11020 {
1ceb70f8 11021 /* MOD_0F71_REG_2 */
b844680a 11022 { "(bad)", { XX } },
4e7d34a6 11023 { "psrlw", { MS, Ib } },
b844680a
L		 11024 },
11025 {
1ceb70f8 11026 /* MOD_0F71_REG_4 */
b844680a 11027 { "(bad)", { XX } },
4e7d34a6 11028 { "psraw", { MS, Ib } },
b844680a
L		 11029 },
11030 {
1ceb70f8 11031 /* MOD_0F71_REG_6 */
b844680a 11032 { "(bad)", { XX } },
4e7d34a6 11033 { "psllw", { MS, Ib } },
b844680a
L		 11034 },
11035 {
1ceb70f8 11036 /* MOD_0F72_REG_2 */
b844680a 11037 { "(bad)", { XX } },
4e7d34a6 11038 { "psrld", { MS, Ib } },
b844680a
L		 11039 },
11040 {
1ceb70f8 11041 /* MOD_0F72_REG_4 */
b844680a 11042 { "(bad)", { XX } },
4e7d34a6 11043 { "psrad", { MS, Ib } },
b844680a
L		 11044 },
11045 {
1ceb70f8 11046 /* MOD_0F72_REG_6 */
b844680a 11047 { "(bad)", { XX } },
4e7d34a6 11048 { "pslld", { MS, Ib } },
b844680a
L		 11049 },
11050 {
1ceb70f8 11051 /* MOD_0F73_REG_2 */
4e7d34a6
L		 11052 { "(bad)", { XX } },
11053 { "psrlq", { MS, Ib } },
b844680a
L		 11054 },
11055 {
1ceb70f8 11056 /* MOD_0F73_REG_3 */
b844680a 11057 { "(bad)", { XX } },
c0f3af97
L		 11058 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11059 },
11060 {
11061 /* MOD_0F73_REG_6 */
11062 { "(bad)", { XX } },
11063 { "psllq", { MS, Ib } },
11064 },
11065 {
11066 /* MOD_0F73_REG_7 */
11067 { "(bad)", { XX } },
11068 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11069 },
11070 {
11071 /* MOD_0FAE_REG_0 */
eacc9c89 11072 { "fxsave", { FXSAVE } },
c0f3af97
L		 11073 { "(bad)", { XX } },
11074 },
11075 {
11076 /* MOD_0FAE_REG_1 */
eacc9c89 11077 { "fxrstor", { FXSAVE } },
c0f3af97
L		 11078 { "(bad)", { XX } },
11079 },
11080 {
11081 /* MOD_0FAE_REG_2 */
11082 { "ldmxcsr", { Md } },
11083 { "(bad)", { XX } },
11084 },
11085 {
11086 /* MOD_0FAE_REG_3 */
11087 { "stmxcsr", { Md } },
11088 { "(bad)", { XX } },
11089 },
11090 {
11091 /* MOD_0FAE_REG_4 */
11092 { "xsave", { M } },
11093 { "(bad)", { XX } },
11094 },
11095 {
11096 /* MOD_0FAE_REG_5 */
11097 { "xrstor", { M } },
11098 { RM_TABLE (RM_0FAE_REG_5) },
11099 },
11100 {
11101 /* MOD_0FAE_REG_6 */
11102 { "xsaveopt", { M } },
11103 { RM_TABLE (RM_0FAE_REG_6) },
11104 },
11105 {
11106 /* MOD_0FAE_REG_7 */
11107 { "clflush", { Mb } },
11108 { RM_TABLE (RM_0FAE_REG_7) },
11109 },
11110 {
11111 /* MOD_0FB2 */
11112 { "lssS", { Gv, Mp } },
11113 { "(bad)", { XX } },
11114 },
11115 {
11116 /* MOD_0FB4 */
11117 { "lfsS", { Gv, Mp } },
11118 { "(bad)", { XX } },
11119 },
11120 {
11121 /* MOD_0FB5 */
11122 { "lgsS", { Gv, Mp } },
11123 { "(bad)", { XX } },
11124 },
11125 {
11126 /* MOD_0FC7_REG_6 */
11127 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11128 { "(bad)", { XX } },
11129 },
11130 {
11131 /* MOD_0FC7_REG_7 */
11132 { "vmptrst", { Mq } },
11133 { "(bad)", { XX } },
11134 },
11135 {
11136 /* MOD_0FD7 */
11137 { "(bad)", { XX } },
11138 { "pmovmskb", { Gdq, MS } },
11139 },
11140 {
11141 /* MOD_0FE7_PREFIX_2 */
11142 { "movntdq", { Mx, XM } },
11143 { "(bad)", { XX } },
11144 },
11145 {
11146 /* MOD_0FF0_PREFIX_3 */
11147 { "lddqu", { XM, M } },
11148 { "(bad)", { XX } },
11149 },
11150 {
11151 /* MOD_0F382A_PREFIX_2 */
11152 { "movntdqa", { XM, Mx } },
11153 { "(bad)", { XX } },
11154 },
11155 {
11156 /* MOD_62_32BIT */
11157 { "bound{S|}", { Gv, Ma } },
11158 { "(bad)", { XX } },
11159 },
11160 {
11161 /* MOD_C4_32BIT */
11162 { "lesS", { Gv, Mp } },
11163 { VEX_C4_TABLE (VEX_0F) },
11164 },
11165 {
11166 /* MOD_C5_32BIT */
11167 { "ldsS", { Gv, Mp } },
11168 { VEX_C5_TABLE (VEX_0F) },
11169 },
11170 {
11171 /* MOD_VEX_12_PREFIX_0 */
11172 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
11173 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
11174 },
11175 {
11176 /* MOD_VEX_13 */
11177 { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
11178 { "(bad)", { XX } },
11179 },
11180 {
11181 /* MOD_VEX_16_PREFIX_0 */
11182 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
11183 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
11184 },
11185 {
11186 /* MOD_VEX_17 */
11187 { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
11188 { "(bad)", { XX } },
11189 },
11190 {
11191 /* MOD_VEX_2B */
9e30b8e0 11192 { VEX_W_TABLE (VEX_W_2B_M_0) },
c0f3af97
L		 11193 { "(bad)", { XX } },
11194 },
11195 {
976f1fde 11196 /* MOD_VEX_50 */
c0f3af97 11197 { "(bad)", { XX } },
9e30b8e0 11198 { VEX_W_TABLE (VEX_W_50_M_0) },
c0f3af97
L		 11199 },
11200 {
11201 /* MOD_VEX_71_REG_2 */
11202 { "(bad)", { XX } },
11203 { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
b844680a
L		 11204 },
11205 {
c0f3af97 11206 /* MOD_VEX_71_REG_4 */
b844680a 11207 { "(bad)", { XX } },
c0f3af97 11208 { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
b844680a
L		 11209 },
11210 {
c0f3af97 11211 /* MOD_VEX_71_REG_6 */
b844680a 11212 { "(bad)", { XX } },
c0f3af97 11213 { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
b844680a
L		 11214 },
11215 {
c0f3af97 11216 /* MOD_VEX_72_REG_2 */
b844680a 11217 { "(bad)", { XX } },
c0f3af97 11218 { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
b844680a 11219 },
d8faab4e 11220 {
c0f3af97 11221 /* MOD_VEX_72_REG_4 */
d8faab4e 11222 { "(bad)", { XX } },
c0f3af97 11223 { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
d8faab4e
L		 11224 },
11225 {
c0f3af97 11226 /* MOD_VEX_72_REG_6 */
d8faab4e 11227 { "(bad)", { XX } },
c0f3af97 11228 { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
d8faab4e 11229 },
876d4bfa 11230 {
c0f3af97 11231 /* MOD_VEX_73_REG_2 */
876d4bfa 11232 { "(bad)", { XX } },
c0f3af97 11233 { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
876d4bfa
L		 11234 },
11235 {
c0f3af97 11236 /* MOD_VEX_73_REG_3 */
876d4bfa 11237 { "(bad)", { XX } },
c0f3af97 11238 { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
475a2301
L		 11239 },
11240 {
c0f3af97
L		 11241 /* MOD_VEX_73_REG_6 */
11242 { "(bad)", { XX } },
11243 { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
876d4bfa
L		 11244 },
11245 {
c0f3af97 11246 /* MOD_VEX_73_REG_7 */
4e7d34a6 11247 { "(bad)", { XX } },
c0f3af97 11248 { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
876d4bfa
L		 11249 },
11250 {
c0f3af97
L		 11251 /* MOD_VEX_AE_REG_2 */
11252 { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
11253 { "(bad)", { XX } },
876d4bfa 11254 },
bbedc832 11255 {
c0f3af97
L		 11256 /* MOD_VEX_AE_REG_3 */
11257 { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
4e7d34a6 11258 { "(bad)", { XX } },
bbedc832 11259 },
144c41d9 11260 {
c0f3af97 11261 /* MOD_VEX_D7_PREFIX_2 */
4e7d34a6 11262 { "(bad)", { XX } },
c0f3af97 11263 { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
144c41d9 11264 },
1afd85e3 11265 {
c0f3af97 11266 /* MOD_VEX_E7_PREFIX_2 */
9e30b8e0 11267 { VEX_W_TABLE (VEX_W_E7_P_2_M_0) },
92fddf8e 11268 { "(bad)", { XX } },
1afd85e3
L		 11269 },
11270 {
c0f3af97 11271 /* MOD_VEX_F0_PREFIX_3 */
9e30b8e0 11272 { VEX_W_TABLE (VEX_W_F0_P_3_M_0) },
92fddf8e
L		 11273 { "(bad)", { XX } },
11274 },
11275 {
c0f3af97 11276 /* MOD_VEX_3818_PREFIX_2 */
bcf2684f 11277 { VEX_W_TABLE (VEX_W_3818_P_2_M_0) },
92fddf8e 11278 { "(bad)", { XX } },
1afd85e3 11279 },
75c135a8 11280 {
c0f3af97
L		 11281 /* MOD_VEX_3819_PREFIX_2 */
11282 { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
75c135a8 11283 { "(bad)", { XX } },
75c135a8
L		 11284 },
11285 {
c0f3af97
L		 11286 /* MOD_VEX_381A_PREFIX_2 */
11287 { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
75c135a8
L		 11288 { "(bad)", { XX } },
11289 },
1afd85e3 11290 {
c0f3af97
L		 11291 /* MOD_VEX_382A_PREFIX_2 */
11292 { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
1afd85e3 11293 { "(bad)", { XX } },
1afd85e3 11294 },
75c135a8 11295 {
c0f3af97 11296 /* MOD_VEX_382C_PREFIX_2 */
53aa04a0 11297 { VEX_W_TABLE (VEX_W_382C_P_2_M_0) },
75c135a8
L		 11298 { "(bad)", { XX } },
11299 },
1afd85e3 11300 {
c0f3af97 11301 /* MOD_VEX_382D_PREFIX_2 */
53aa04a0 11302 { VEX_W_TABLE (VEX_W_382D_P_2_M_0) },
1afd85e3 11303 { "(bad)", { XX } },
1afd85e3
L		 11304 },
11305 {
c0f3af97 11306 /* MOD_VEX_382E_PREFIX_2 */
53aa04a0 11307 { VEX_W_TABLE (VEX_W_382E_P_2_M_0) },
4e7d34a6 11308 { "(bad)", { XX } },
1afd85e3
L		 11309 },
11310 {
c0f3af97 11311 /* MOD_VEX_382F_PREFIX_2 */
53aa04a0 11312 { VEX_W_TABLE (VEX_W_382F_P_2_M_0) },
1afd85e3 11313 { "(bad)", { XX } },
1afd85e3 11314 },
b844680a
L		 11315};
11316
1ceb70f8 11317static const struct dis386 rm_table[][8] = {
b844680a 11318 {
1ceb70f8 11319 /* RM_0F01_REG_0 */
b844680a
L		 11320 { "(bad)", { XX } },
11321 { "vmcall", { Skip_MODRM } },
11322 { "vmlaunch", { Skip_MODRM } },
11323 { "vmresume", { Skip_MODRM } },
11324 { "vmxoff", { Skip_MODRM } },
11325 { "(bad)", { XX } },
11326 { "(bad)", { XX } },
11327 { "(bad)", { XX } },
11328 },
11329 {
1ceb70f8 11330 /* RM_0F01_REG_1 */
b844680a
L		 11331 { "monitor", { { OP_Monitor, 0 } } },
11332 { "mwait", { { OP_Mwait, 0 } } },
11333 { "(bad)", { XX } },
11334 { "(bad)", { XX } },
11335 { "(bad)", { XX } },
11336 { "(bad)", { XX } },
11337 { "(bad)", { XX } },
11338 { "(bad)", { XX } },
11339 },
475a2301
L		 11340 {
11341 /* RM_0F01_REG_2 */
11342 { "xgetbv", { Skip_MODRM } },
11343 { "xsetbv", { Skip_MODRM } },
11344 { "(bad)", { XX } },
11345 { "(bad)", { XX } },
11346 { "(bad)", { XX } },
11347 { "(bad)", { XX } },
11348 { "(bad)", { XX } },
11349 { "(bad)", { XX } },
11350 },
b844680a 11351 {
1ceb70f8 11352 /* RM_0F01_REG_3 */
4e7d34a6
L		 11353 { "vmrun", { Skip_MODRM } },
11354 { "vmmcall", { Skip_MODRM } },
11355 { "vmload", { Skip_MODRM } },
11356 { "vmsave", { Skip_MODRM } },
11357 { "stgi", { Skip_MODRM } },
11358 { "clgi", { Skip_MODRM } },
11359 { "skinit", { Skip_MODRM } },
11360 { "invlpga", { Skip_MODRM } },
11361 },
11362 {
1ceb70f8 11363 /* RM_0F01_REG_7 */
4e7d34a6
L		 11364 { "swapgs", { Skip_MODRM } },
11365 { "rdtscp", { Skip_MODRM } },
b844680a
L		 11366 { "(bad)", { XX } },
11367 { "(bad)", { XX } },
11368 { "(bad)", { XX } },
11369 { "(bad)", { XX } },
11370 { "(bad)", { XX } },
11371 { "(bad)", { XX } },
11372 },
11373 {
1ceb70f8 11374 /* RM_0FAE_REG_5 */
4e7d34a6 11375 { "lfence", { Skip_MODRM } },
b844680a
L		 11376 { "(bad)", { XX } },
11377 { "(bad)", { XX } },
11378 { "(bad)", { XX } },
11379 { "(bad)", { XX } },
11380 { "(bad)", { XX } },
11381 { "(bad)", { XX } },
11382 { "(bad)", { XX } },
11383 },
11384 {
1ceb70f8 11385 /* RM_0FAE_REG_6 */
4e7d34a6 11386 { "mfence", { Skip_MODRM } },
b844680a
L		 11387 { "(bad)", { XX } },
11388 { "(bad)", { XX } },
11389 { "(bad)", { XX } },
11390 { "(bad)", { XX } },
11391 { "(bad)", { XX } },
11392 { "(bad)", { XX } },
11393 { "(bad)", { XX } },
11394 },
bbedc832 11395 {
1ceb70f8 11396 /* RM_0FAE_REG_7 */
4e7d34a6
L		 11397 { "sfence", { Skip_MODRM } },
11398 { "(bad)", { XX } },
bbedc832
L		 11399 { "(bad)", { XX } },
11400 { "(bad)", { XX } },
11401 { "(bad)", { XX } },
11402 { "(bad)", { XX } },
11403 { "(bad)", { XX } },
11404 { "(bad)", { XX } },
144c41d9 11405 },
b844680a
L		 11406};
11407
c608c12e
AM		 11408#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11409
f16cd0d5
L		 11410/* We use the high bit to indicate different name for the same
11411 prefix. */
11412#define ADDR16_PREFIX (0x67 | 0x100)
11413#define ADDR32_PREFIX (0x67 | 0x200)
11414#define DATA16_PREFIX (0x66 | 0x100)
11415#define DATA32_PREFIX (0x66 | 0x200)
11416#define REP_PREFIX (0xf3 | 0x100)
11417
11418static int
26ca5450 11419ckprefix (void)
252b5132 11420{
f16cd0d5 11421 int newrex, i, length;
52b15da3 11422 rex = 0;
c0f3af97 11423 rex_ignored = 0;
252b5132 11424 prefixes = 0;
7d421014 11425 used_prefixes = 0;
52b15da3 11426 rex_used = 0;
f16cd0d5
L		 11427 last_lock_prefix = -1;
11428 last_repz_prefix = -1;
11429 last_repnz_prefix = -1;
11430 last_data_prefix = -1;
11431 last_addr_prefix = -1;
11432 last_rex_prefix = -1;
11433 last_seg_prefix = -1;
f310f33d
L		 11434 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11435 all_prefixes[i] = 0;
11436 i = 0;
f16cd0d5
L		 11437 length = 0;
11438 /* The maximum instruction length is 15bytes. */
11439 while (length < MAX_CODE_LENGTH - 1)
252b5132
RH		 11440 {
11441 FETCH_DATA (the_info, codep + 1);
52b15da3 11442 newrex = 0;
252b5132
RH		 11443 switch (*codep)
11444 {
52b15da3
JH		 11445 /* REX prefixes family. */
11446 case 0x40:
11447 case 0x41:
11448 case 0x42:
11449 case 0x43:
11450 case 0x44:
11451 case 0x45:
11452 case 0x46:
11453 case 0x47:
11454 case 0x48:
11455 case 0x49:
11456 case 0x4a:
11457 case 0x4b:
11458 case 0x4c:
11459 case 0x4d:
11460 case 0x4e:
11461 case 0x4f:
f16cd0d5
L		 11462 if (address_mode == mode_64bit)
11463 newrex = *codep;
11464 else
11465 return 1;
11466 last_rex_prefix = i;
52b15da3 11467 break;
252b5132
RH		 11468 case 0xf3:
11469 prefixes |= PREFIX_REPZ;
f16cd0d5 11470 last_repz_prefix = i;
252b5132
RH		 11471 break;
11472 case 0xf2:
11473 prefixes |= PREFIX_REPNZ;
f16cd0d5 11474 last_repnz_prefix = i;
252b5132
RH		 11475 break;
11476 case 0xf0:
11477 prefixes |= PREFIX_LOCK;
f16cd0d5 11478 last_lock_prefix = i;
252b5132
RH		 11479 break;
11480 case 0x2e:
11481 prefixes |= PREFIX_CS;
f16cd0d5 11482 last_seg_prefix = i;
252b5132
RH		 11483 break;
11484 case 0x36:
11485 prefixes |= PREFIX_SS;
f16cd0d5 11486 last_seg_prefix = i;
252b5132
RH		 11487 break;
11488 case 0x3e:
11489 prefixes |= PREFIX_DS;
f16cd0d5 11490 last_seg_prefix = i;
252b5132
RH		 11491 break;
11492 case 0x26:
11493 prefixes |= PREFIX_ES;
f16cd0d5 11494 last_seg_prefix = i;
252b5132
RH		 11495 break;
11496 case 0x64:
11497 prefixes |= PREFIX_FS;
f16cd0d5 11498 last_seg_prefix = i;
252b5132
RH		 11499 break;
11500 case 0x65:
11501 prefixes |= PREFIX_GS;
f16cd0d5 11502 last_seg_prefix = i;
252b5132
RH		 11503 break;
11504 case 0x66:
11505 prefixes |= PREFIX_DATA;
f16cd0d5 11506 last_data_prefix = i;
252b5132
RH		 11507 break;
11508 case 0x67:
11509 prefixes |= PREFIX_ADDR;
f16cd0d5 11510 last_addr_prefix = i;
252b5132 11511 break;
5076851f 11512 case FWAIT_OPCODE:
252b5132
RH		 11513 /* fwait is really an instruction. If there are prefixes
11514 before the fwait, they belong to the fwait, *not* to the
11515 following instruction. */
3e7d61b2 11516 if (prefixes || rex)
252b5132
RH		 11517 {
11518 prefixes |= PREFIX_FWAIT;
11519 codep++;
f16cd0d5 11520 return 1;
252b5132
RH		 11521 }
11522 prefixes = PREFIX_FWAIT;
11523 break;
11524 default:
f16cd0d5 11525 return 1;
252b5132 11526 }
52b15da3
JH		 11527 /* Rex is ignored when followed by another prefix. */
11528 if (rex)
11529 {
3e7d61b2 11530 rex_used = rex;
f16cd0d5 11531 return 1;
52b15da3 11532 }
f16cd0d5
L		 11533 if (*codep != FWAIT_OPCODE)
11534 all_prefixes[i++] = *codep;
52b15da3 11535 rex = newrex;
252b5132 11536 codep++;
f16cd0d5
L		 11537 length++;
11538 }
11539 return 0;
11540}
11541
11542static int
11543seg_prefix (int pref)
11544{
11545 switch (pref)
11546 {
11547 case 0x2e:
11548 return PREFIX_CS;
11549 case 0x36:
11550 return PREFIX_SS;
11551 case 0x3e:
11552 return PREFIX_DS;
11553 case 0x26:
11554 return PREFIX_ES;
11555 case 0x64:
11556 return PREFIX_FS;
11557 case 0x65:
11558 return PREFIX_GS;
11559 default:
11560 return 0;
252b5132
RH		 11561 }
11562}
11563
7d421014
ILT		 11564/* Return the name of the prefix byte PREF, or NULL if PREF is not a
11565 prefix byte. */
11566
11567static const char *
26ca5450 11568prefix_name (int pref, int sizeflag)
7d421014 11569{
0003779b
L		 11570 static const char *rexes [16] =
11571 {
11572 "rex", /* 0x40 */
11573 "rex.B", /* 0x41 */
11574 "rex.X", /* 0x42 */
11575 "rex.XB", /* 0x43 */
11576 "rex.R", /* 0x44 */
11577 "rex.RB", /* 0x45 */
11578 "rex.RX", /* 0x46 */
11579 "rex.RXB", /* 0x47 */
11580 "rex.W", /* 0x48 */
11581 "rex.WB", /* 0x49 */
11582 "rex.WX", /* 0x4a */
11583 "rex.WXB", /* 0x4b */
11584 "rex.WR", /* 0x4c */
11585 "rex.WRB", /* 0x4d */
11586 "rex.WRX", /* 0x4e */
11587 "rex.WRXB", /* 0x4f */
11588 };
11589
7d421014
ILT		 11590 switch (pref)
11591 {
52b15da3
JH		 11592 /* REX prefixes family. */
11593 case 0x40:
52b15da3 11594 case 0x41:
52b15da3 11595 case 0x42:
52b15da3 11596 case 0x43:
52b15da3 11597 case 0x44:
52b15da3 11598 case 0x45:
52b15da3 11599 case 0x46:
52b15da3 11600 case 0x47:
52b15da3 11601 case 0x48:
52b15da3 11602 case 0x49:
52b15da3 11603 case 0x4a:
52b15da3 11604 case 0x4b:
52b15da3 11605 case 0x4c:
52b15da3 11606 case 0x4d:
52b15da3 11607 case 0x4e:
52b15da3 11608 case 0x4f:
0003779b 11609 return rexes [pref - 0x40];
7d421014
ILT		 11610 case 0xf3:
11611 return "repz";
11612 case 0xf2:
11613 return "repnz";
11614 case 0xf0:
11615 return "lock";
11616 case 0x2e:
11617 return "cs";
11618 case 0x36:
11619 return "ss";
11620 case 0x3e:
11621 return "ds";
11622 case 0x26:
11623 return "es";
11624 case 0x64:
11625 return "fs";
11626 case 0x65:
11627 return "gs";
11628 case 0x66:
11629 return (sizeflag & DFLAG) ? "data16" : "data32";
11630 case 0x67:
cb712a9e 11631 if (address_mode == mode_64bit)
db6eb5be 11632 return (sizeflag & AFLAG) ? "addr32" : "addr64";
c1a64871 11633 else
2888cb7a 11634 return (sizeflag & AFLAG) ? "addr16" : "addr32";
7d421014
ILT		 11635 case FWAIT_OPCODE:
11636 return "fwait";
f16cd0d5
L		 11637 case ADDR16_PREFIX:
11638 return "addr16";
11639 case ADDR32_PREFIX:
11640 return "addr32";
11641 case DATA16_PREFIX:
11642 return "data16";
11643 case DATA32_PREFIX:
11644 return "data32";
11645 case REP_PREFIX:
11646 return "rep";
7d421014
ILT		 11647 default:
11648 return NULL;
11649 }
11650}
11651
ce518a5f
L		 11652static char op_out[MAX_OPERANDS][100];
11653static int op_ad, op_index[MAX_OPERANDS];
1d9f512f 11654static int two_source_ops;
ce518a5f
L		 11655static bfd_vma op_address[MAX_OPERANDS];
11656static bfd_vma op_riprel[MAX_OPERANDS];
52b15da3 11657static bfd_vma start_pc;
ce518a5f 11658
252b5132
RH		 11659/*
11660 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11661 * (see topic "Redundant prefixes" in the "Differences from 8086"
11662 * section of the "Virtual 8086 Mode" chapter.)
11663 * 'pc' should be the address of this instruction, it will
11664 * be used to print the target address if this is a relative jump or call
11665 * The function returns the length of this instruction in bytes.
11666 */
11667
252b5132 11668static char intel_syntax;
9d141669 11669static char intel_mnemonic = !SYSV386_COMPAT;
252b5132
RH		 11670static char open_char;
11671static char close_char;
11672static char separator_char;
11673static char scale_char;
11674
e396998b
AM		 11675/* Here for backwards compatibility. When gdb stops using
11676 print_insn_i386_att and print_insn_i386_intel these functions can
11677 disappear, and print_insn_i386 be merged into print_insn. */
252b5132 11678int
26ca5450 11679print_insn_i386_att (bfd_vma pc, disassemble_info *info)
252b5132
RH		 11680{
11681 intel_syntax = 0;
e396998b
AM		 11682
11683 return print_insn (pc, info);
252b5132
RH		 11684}
11685
11686int
26ca5450 11687print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
252b5132
RH		 11688{
11689 intel_syntax = 1;
e396998b
AM		 11690
11691 return print_insn (pc, info);
252b5132
RH		 11692}
11693
e396998b 11694int
26ca5450 11695print_insn_i386 (bfd_vma pc, disassemble_info *info)
e396998b
AM		 11696{
11697 intel_syntax = -1;
11698
11699 return print_insn (pc, info);
11700}
11701
f59a29b9
L		 11702void
11703print_i386_disassembler_options (FILE *stream)
11704{
11705 fprintf (stream, _("\n\
11706The following i386/x86-64 specific disassembler options are supported for use\n\
11707with the -M switch (multiple options should be separated by commas):\n"));
11708
11709 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
11710 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
11711 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
11712 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
11713 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
9d141669
L		 11714 fprintf (stream, _(" att-mnemonic\n"
11715 " Display instruction in AT&T mnemonic\n"));
11716 fprintf (stream, _(" intel-mnemonic\n"
11717 " Display instruction in Intel mnemonic\n"));
f59a29b9
L		 11718 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
11719 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
11720 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
11721 fprintf (stream, _(" data32 Assume 32bit data size\n"));
11722 fprintf (stream, _(" data16 Assume 16bit data size\n"));
11723 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11724}
11725
b844680a
L		 11726/* Get a pointer to struct dis386 with a valid name. */
11727
11728static const struct dis386 *
8bb15339 11729get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
b844680a 11730{
91d6fa6a 11731 int vindex, vex_table_index;
b844680a
L		 11732
11733 if (dp->name != NULL)
11734 return dp;
11735
11736 switch (dp->op[0].bytemode)
11737 {
1ceb70f8
L		 11738 case USE_REG_TABLE:
11739 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11740 break;
11741
11742 case USE_MOD_TABLE:
91d6fa6a
NC		 11743 vindex = modrm.mod == 0x3 ? 1 : 0;
11744 dp = &mod_table[dp->op[1].bytemode][vindex];
1ceb70f8
L		 11745 break;
11746
11747 case USE_RM_TABLE:
11748 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
b844680a
L		 11749 break;
11750
4e7d34a6 11751 case USE_PREFIX_TABLE:
c0f3af97 11752 if (need_vex)
b844680a 11753 {
c0f3af97
L		 11754 /* The prefix in VEX is implicit. */
11755 switch (vex.prefix)
11756 {
11757 case 0:
91d6fa6a 11758 vindex = 0;
c0f3af97
L		 11759 break;
11760 case REPE_PREFIX_OPCODE:
91d6fa6a 11761 vindex = 1;
c0f3af97
L		 11762 break;
11763 case DATA_PREFIX_OPCODE:
91d6fa6a 11764 vindex = 2;
c0f3af97
L		 11765 break;
11766 case REPNE_PREFIX_OPCODE:
91d6fa6a 11767 vindex = 3;
c0f3af97
L		 11768 break;
11769 default:
11770 abort ();
11771 break;
11772 }
b844680a 11773 }
c0f3af97 11774 else
b844680a 11775 {
91d6fa6a 11776 vindex = 0;
c0f3af97
L		 11777 used_prefixes |= (prefixes & PREFIX_REPZ);
11778 if (prefixes & PREFIX_REPZ)
b844680a 11779 {
91d6fa6a 11780 vindex = 1;
f16cd0d5 11781 all_prefixes[last_repz_prefix] = 0;
b844680a
L		 11782 }
11783 else
11784 {
c0f3af97
L		 11785 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11786 PREFIX_DATA. */
11787 used_prefixes |= (prefixes & PREFIX_REPNZ);
11788 if (prefixes & PREFIX_REPNZ)
11789 {
91d6fa6a 11790 vindex = 3;
f16cd0d5 11791 all_prefixes[last_repnz_prefix] = 0;
c0f3af97
L		 11792 }
11793 else
b844680a 11794 {
c0f3af97
L		 11795 used_prefixes |= (prefixes & PREFIX_DATA);
11796 if (prefixes & PREFIX_DATA)
11797 {
91d6fa6a 11798 vindex = 2;
f16cd0d5 11799 all_prefixes[last_data_prefix] = 0;
c0f3af97 11800 }
b844680a
L		 11801 }
11802 }
11803 }
91d6fa6a 11804 dp = &prefix_table[dp->op[1].bytemode][vindex];
b844680a
L		 11805 break;
11806
4e7d34a6 11807 case USE_X86_64_TABLE:
91d6fa6a
NC		 11808 vindex = address_mode == mode_64bit ? 1 : 0;
11809 dp = &x86_64_table[dp->op[1].bytemode][vindex];
b844680a
L		 11810 break;
11811
4e7d34a6 11812 case USE_3BYTE_TABLE:
8bb15339 11813 FETCH_DATA (info, codep + 2);
91d6fa6a
NC		 11814 vindex = *codep++;
11815 dp = &three_byte_table[dp->op[1].bytemode][vindex];
8bb15339
L		 11816 modrm.mod = (*codep >> 6) & 3;
11817 modrm.reg = (*codep >> 3) & 7;
11818 modrm.rm = *codep & 7;
11819 break;
11820
c0f3af97
L		 11821 case USE_VEX_LEN_TABLE:
11822 if (!need_vex)
11823 abort ();
11824
11825 switch (vex.length)
11826 {
11827 case 128:
91d6fa6a 11828 vindex = 0;
c0f3af97
L		 11829 break;
11830 case 256:
91d6fa6a 11831 vindex = 1;
c0f3af97
L		 11832 break;
11833 default:
11834 abort ();
11835 break;
11836 }
11837
91d6fa6a 11838 dp = &vex_len_table[dp->op[1].bytemode][vindex];
c0f3af97
L		 11839 break;
11840
f88c9eb0
SP		 11841 case USE_XOP_8F_TABLE:
11842 FETCH_DATA (info, codep + 3);
11843 /* All bits in the REX prefix are ignored. */
11844 rex_ignored = rex;
11845 rex = ~(*codep >> 5) & 0x7;
11846
11847 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11848 switch ((*codep & 0x1f))
11849 {
11850 default:
11851 BadOp ();
5dd85c99
SP		 11852 case 0x8:
11853 vex_table_index = XOP_08;
11854 break;
f88c9eb0
SP		 11855 case 0x9:
11856 vex_table_index = XOP_09;
11857 break;
11858 case 0xa:
11859 vex_table_index = XOP_0A;
11860 break;
11861 }
11862 codep++;
11863 vex.w = *codep & 0x80;
11864 if (vex.w && address_mode == mode_64bit)
11865 rex |= REX_W;
11866
11867 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11868 if (address_mode != mode_64bit
11869 && vex.register_specifier > 0x7)
11870 BadOp ();
11871
11872 vex.length = (*codep & 0x4) ? 256 : 128;
11873 switch ((*codep & 0x3))
11874 {
11875 case 0:
11876 vex.prefix = 0;
11877 break;
11878 case 1:
11879 vex.prefix = DATA_PREFIX_OPCODE;
11880 break;
11881 case 2:
11882 vex.prefix = REPE_PREFIX_OPCODE;
11883 break;
11884 case 3:
11885 vex.prefix = REPNE_PREFIX_OPCODE;
11886 break;
11887 }
11888 need_vex = 1;
11889 need_vex_reg = 1;
11890 codep++;
91d6fa6a
NC		 11891 vindex = *codep++;
11892 dp = &xop_table[vex_table_index][vindex];
c48244a5
SP		 11893
11894 FETCH_DATA (info, codep + 1);
11895 modrm.mod = (*codep >> 6) & 3;
11896 modrm.reg = (*codep >> 3) & 7;
11897 modrm.rm = *codep & 7;
f88c9eb0
SP		 11898 break;
11899
c0f3af97
L		 11900 case USE_VEX_C4_TABLE:
11901 FETCH_DATA (info, codep + 3);
11902 /* All bits in the REX prefix are ignored. */
11903 rex_ignored = rex;
11904 rex = ~(*codep >> 5) & 0x7;
11905 switch ((*codep & 0x1f))
11906 {
11907 default:
11908 BadOp ();
11909 case 0x1:
f88c9eb0 11910 vex_table_index = VEX_0F;
c0f3af97
L		 11911 break;
11912 case 0x2:
f88c9eb0 11913 vex_table_index = VEX_0F38;
c0f3af97
L		 11914 break;
11915 case 0x3:
f88c9eb0 11916 vex_table_index = VEX_0F3A;
c0f3af97
L		 11917 break;
11918 }
11919 codep++;
11920 vex.w = *codep & 0x80;
11921 if (vex.w && address_mode == mode_64bit)
11922 rex |= REX_W;
11923
11924 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11925 if (address_mode != mode_64bit
11926 && vex.register_specifier > 0x7)
11927 BadOp ();
11928
11929 vex.length = (*codep & 0x4) ? 256 : 128;
11930 switch ((*codep & 0x3))
11931 {
11932 case 0:
11933 vex.prefix = 0;
11934 break;
11935 case 1:
11936 vex.prefix = DATA_PREFIX_OPCODE;
11937 break;
11938 case 2:
11939 vex.prefix = REPE_PREFIX_OPCODE;
11940 break;
11941 case 3:
11942 vex.prefix = REPNE_PREFIX_OPCODE;
11943 break;
11944 }
11945 need_vex = 1;
11946 need_vex_reg = 1;
11947 codep++;
91d6fa6a
NC		 11948 vindex = *codep++;
11949 dp = &vex_table[vex_table_index][vindex];
c0f3af97 11950 /* There is no MODRM byte for VEX [82|77]. */
91d6fa6a 11951 if (vindex != 0x77 && vindex != 0x82)
c0f3af97
L		 11952 {
11953 FETCH_DATA (info, codep + 1);
11954 modrm.mod = (*codep >> 6) & 3;
11955 modrm.reg = (*codep >> 3) & 7;
11956 modrm.rm = *codep & 7;
11957 }
11958 break;
11959
11960 case USE_VEX_C5_TABLE:
11961 FETCH_DATA (info, codep + 2);
11962 /* All bits in the REX prefix are ignored. */
11963 rex_ignored = rex;
11964 rex = (*codep & 0x80) ? 0 : REX_R;
11965
11966 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11967 if (address_mode != mode_64bit
11968 && vex.register_specifier > 0x7)
11969 BadOp ();
11970
759a05ce
L		 11971 vex.w = 0;
11972
c0f3af97
L		 11973 vex.length = (*codep & 0x4) ? 256 : 128;
11974 switch ((*codep & 0x3))
11975 {
11976 case 0:
11977 vex.prefix = 0;
11978 break;
11979 case 1:
11980 vex.prefix = DATA_PREFIX_OPCODE;
11981 break;
11982 case 2:
11983 vex.prefix = REPE_PREFIX_OPCODE;
11984 break;
11985 case 3:
11986 vex.prefix = REPNE_PREFIX_OPCODE;
11987 break;
11988 }
11989 need_vex = 1;
11990 need_vex_reg = 1;
11991 codep++;
91d6fa6a
NC		 11992 vindex = *codep++;
11993 dp = &vex_table[dp->op[1].bytemode][vindex];
c0f3af97 11994 /* There is no MODRM byte for VEX [82|77]. */
91d6fa6a 11995 if (vindex != 0x77 && vindex != 0x82)
c0f3af97
L		 11996 {
11997 FETCH_DATA (info, codep + 1);
11998 modrm.mod = (*codep >> 6) & 3;
11999 modrm.reg = (*codep >> 3) & 7;
12000 modrm.rm = *codep & 7;
12001 }
12002 break;
12003
9e30b8e0
L		 12004 case USE_VEX_W_TABLE:
12005 if (!need_vex)
12006 abort ();
12007
12008 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12009 break;
12010
b844680a 12011 default:
d34b5006 12012 abort ();
b844680a
L		 12013 }
12014
12015 if (dp->name != NULL)
12016 return dp;
12017 else
8bb15339 12018 return get_valid_dis386 (dp, info);
b844680a
L		 12019}
12020
e396998b 12021static int
26ca5450 12022print_insn (bfd_vma pc, disassemble_info *info)
252b5132 12023{
2da11e11 12024 const struct dis386 *dp;
252b5132 12025 int i;
ce518a5f 12026 char *op_txt[MAX_OPERANDS];
252b5132 12027 int needcomma;
e396998b
AM		 12028 int sizeflag;
12029 const char *p;
252b5132 12030 struct dis_private priv;
eec0f4ca 12031 unsigned char op;
f16cd0d5
L		 12032 int prefix_length;
12033 int default_prefixes;
252b5132 12034
cb712a9e 12035 if (info->mach == bfd_mach_x86_64_intel_syntax
8a9036a4
L		 12036 || info->mach == bfd_mach_x86_64
12037 || info->mach == bfd_mach_l1om
12038 || info->mach == bfd_mach_l1om_intel_syntax)
cb712a9e
L		 12039 address_mode = mode_64bit;
12040 else
12041 address_mode = mode_32bit;
52b15da3 12042
8373f971 12043 if (intel_syntax == (char) -1)
e396998b 12044 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
8a9036a4
L		 12045 || info->mach == bfd_mach_x86_64_intel_syntax
12046 || info->mach == bfd_mach_l1om_intel_syntax);
e396998b 12047
2da11e11 12048 if (info->mach == bfd_mach_i386_i386
52b15da3 12049 || info->mach == bfd_mach_x86_64
8a9036a4 12050 || info->mach == bfd_mach_l1om
52b15da3 12051 || info->mach == bfd_mach_i386_i386_intel_syntax
8a9036a4
L		 12052 || info->mach == bfd_mach_x86_64_intel_syntax
12053 || info->mach == bfd_mach_l1om_intel_syntax)
e396998b 12054 priv.orig_sizeflag = AFLAG | DFLAG;
2da11e11 12055 else if (info->mach == bfd_mach_i386_i8086)
e396998b 12056 priv.orig_sizeflag = 0;
2da11e11
AM		 12057 else
12058 abort ();
e396998b
AM		 12059
12060 for (p = info->disassembler_options; p != NULL; )
12061 {
0112cd26 12062 if (CONST_STRNEQ (p, "x86-64"))
e396998b 12063 {
cb712a9e 12064 address_mode = mode_64bit;
e396998b
AM		 12065 priv.orig_sizeflag = AFLAG | DFLAG;
12066 }
0112cd26 12067 else if (CONST_STRNEQ (p, "i386"))
e396998b 12068 {
cb712a9e 12069 address_mode = mode_32bit;
e396998b
AM		 12070 priv.orig_sizeflag = AFLAG | DFLAG;
12071 }
0112cd26 12072 else if (CONST_STRNEQ (p, "i8086"))
e396998b 12073 {
cb712a9e 12074 address_mode = mode_16bit;
e396998b
AM		 12075 priv.orig_sizeflag = 0;
12076 }
0112cd26 12077 else if (CONST_STRNEQ (p, "intel"))
e396998b
AM		 12078 {
12079 intel_syntax = 1;
9d141669
L		 12080 if (CONST_STRNEQ (p + 5, "-mnemonic"))
12081 intel_mnemonic = 1;
e396998b 12082 }
0112cd26 12083 else if (CONST_STRNEQ (p, "att"))
e396998b
AM		 12084 {
12085 intel_syntax = 0;
9d141669
L		 12086 if (CONST_STRNEQ (p + 3, "-mnemonic"))
12087 intel_mnemonic = 0;
e396998b 12088 }
0112cd26 12089 else if (CONST_STRNEQ (p, "addr"))
e396998b 12090 {
f59a29b9
L		 12091 if (address_mode == mode_64bit)
12092 {
12093 if (p[4] == '3' && p[5] == '2')
12094 priv.orig_sizeflag &= ~AFLAG;
12095 else if (p[4] == '6' && p[5] == '4')
12096 priv.orig_sizeflag |= AFLAG;
12097 }
12098 else
12099 {
12100 if (p[4] == '1' && p[5] == '6')
12101 priv.orig_sizeflag &= ~AFLAG;
12102 else if (p[4] == '3' && p[5] == '2')
12103 priv.orig_sizeflag |= AFLAG;
12104 }
e396998b 12105 }
0112cd26 12106 else if (CONST_STRNEQ (p, "data"))
e396998b
AM		 12107 {
12108 if (p[4] == '1' && p[5] == '6')
12109 priv.orig_sizeflag &= ~DFLAG;
12110 else if (p[4] == '3' && p[5] == '2')
12111 priv.orig_sizeflag |= DFLAG;
12112 }
0112cd26 12113 else if (CONST_STRNEQ (p, "suffix"))
e396998b
AM		 12114 priv.orig_sizeflag |= SUFFIX_ALWAYS;
12115
12116 p = strchr (p, ',');
12117 if (p != NULL)
12118 p++;
12119 }
12120
12121 if (intel_syntax)
12122 {
12123 names64 = intel_names64;
12124 names32 = intel_names32;
12125 names16 = intel_names16;
12126 names8 = intel_names8;
12127 names8rex = intel_names8rex;
12128 names_seg = intel_names_seg;
db51cc60
L		 12129 index64 = intel_index64;
12130 index32 = intel_index32;
e396998b
AM		 12131 index16 = intel_index16;
12132 open_char = '[';
12133 close_char = ']';
12134 separator_char = '+';
12135 scale_char = '*';
12136 }
12137 else
12138 {
12139 names64 = att_names64;
12140 names32 = att_names32;
12141 names16 = att_names16;
12142 names8 = att_names8;
12143 names8rex = att_names8rex;
12144 names_seg = att_names_seg;
db51cc60
L		 12145 index64 = att_index64;
12146 index32 = att_index32;
e396998b
AM		 12147 index16 = att_index16;
12148 open_char = '(';
12149 close_char = ')';
12150 separator_char = ',';
12151 scale_char = ',';
12152 }
2da11e11 12153
4fe53c98 12154 /* The output looks better if we put 7 bytes on a line, since that
8a9036a4
L		 12155 puts most long word instructions on a single line. Use 8 bytes
12156 for Intel L1OM. */
12157 if (info->mach == bfd_mach_l1om
12158 || info->mach == bfd_mach_l1om_intel_syntax)
12159 info->bytes_per_line = 8;
12160 else
12161 info->bytes_per_line = 7;
252b5132 12162
26ca5450 12163 info->private_data = &priv;
252b5132
RH		 12164 priv.max_fetched = priv.the_buffer;
12165 priv.insn_start = pc;
252b5132
RH		 12166
12167 obuf[0] = 0;
ce518a5f
L		 12168 for (i = 0; i < MAX_OPERANDS; ++i)
12169 {
12170 op_out[i][0] = 0;
12171 op_index[i] = -1;
12172 }
252b5132
RH		 12173
12174 the_info = info;
12175 start_pc = pc;
e396998b
AM		 12176 start_codep = priv.the_buffer;
12177 codep = priv.the_buffer;
252b5132 12178
5076851f
ILT		 12179 if (setjmp (priv.bailout) != 0)
12180 {
7d421014
ILT		 12181 const char *name;
12182
5076851f 12183 /* Getting here means we tried for data but didn't get it. That
e396998b
AM		 12184 means we have an incomplete instruction of some sort. Just
12185 print the first byte as a prefix or a .byte pseudo-op. */
12186 if (codep > priv.the_buffer)
5076851f 12187 {
e396998b 12188 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 12189 if (name != NULL)
12190 (*info->fprintf_func) (info->stream, "%s", name);
12191 else
5076851f 12192 {
7d421014
ILT		 12193 /* Just print the first byte as a .byte instruction. */
12194 (*info->fprintf_func) (info->stream, ".byte 0x%x",
e396998b 12195 (unsigned int) priv.the_buffer[0]);
5076851f 12196 }
5076851f 12197
7d421014 12198 return 1;
5076851f
ILT		 12199 }
12200
12201 return -1;
12202 }
12203
52b15da3 12204 obufp = obuf;
f16cd0d5
L		 12205 sizeflag = priv.orig_sizeflag;
12206
12207 if (!ckprefix () || rex_used)
12208 {
12209 /* Too many prefixes or unused REX prefixes. */
12210 for (i = 0;
12211 all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes);
12212 i++)
12213 (*info->fprintf_func) (info->stream, "%s",
12214 prefix_name (all_prefixes[i], sizeflag));
12215 return 1;
12216 }
252b5132
RH		 12217
12218 insn_codep = codep;
12219
12220 FETCH_DATA (info, codep + 1);
12221 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12222
3e7d61b2 12223 if (((prefixes & PREFIX_FWAIT)
f16cd0d5 12224 && ((*codep < 0xd8) || (*codep > 0xdf))))
252b5132 12225 {
f16cd0d5 12226 (*info->fprintf_func) (info->stream, "fwait");
7d421014 12227 return 1;
252b5132
RH		 12228 }
12229
eec0f4ca 12230 op = 0;
c1e679ec 12231
252b5132
RH		 12232 if (*codep == 0x0f)
12233 {
eec0f4ca 12234 unsigned char threebyte;
252b5132 12235 FETCH_DATA (info, codep + 2);
eec0f4ca
L		 12236 threebyte = *++codep;
12237 dp = &dis386_twobyte[threebyte];
252b5132 12238 need_modrm = twobyte_has_modrm[*codep];
eec0f4ca 12239 codep++;
252b5132
RH		 12240 }
12241 else
12242 {
6439fc28 12243 dp = &dis386[*codep];
252b5132 12244 need_modrm = onebyte_has_modrm[*codep];
eec0f4ca 12245 codep++;
252b5132 12246 }
246c51aa 12247
b844680a 12248 if ((prefixes & PREFIX_REPZ))
f16cd0d5 12249 used_prefixes |= PREFIX_REPZ;
b844680a 12250 if ((prefixes & PREFIX_REPNZ))
f16cd0d5 12251 used_prefixes |= PREFIX_REPNZ;
b844680a 12252 if ((prefixes & PREFIX_LOCK))
f16cd0d5 12253 used_prefixes |= PREFIX_LOCK;
c608c12e 12254
f16cd0d5 12255 default_prefixes = 0;
c608c12e
AM		 12256 if (prefixes & PREFIX_ADDR)
12257 {
12258 sizeflag ^= AFLAG;
ce518a5f 12259 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
3ffd33cf 12260 {
cb712a9e 12261 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
f16cd0d5 12262 all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
3ffd33cf 12263 else
f16cd0d5
L		 12264 all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
12265 default_prefixes |= PREFIX_ADDR;
3ffd33cf
AM		 12266 }
12267 }
12268
b844680a 12269 if ((prefixes & PREFIX_DATA))
3ffd33cf
AM		 12270 {
12271 sizeflag ^= DFLAG;
ce518a5f
L		 12272 if (dp->op[2].bytemode == cond_jump_mode
12273 && dp->op[0].bytemode == v_mode
6439fc28 12274 && !intel_syntax)
3ffd33cf
AM		 12275 {
12276 if (sizeflag & DFLAG)
f16cd0d5 12277 all_prefixes[last_data_prefix] = DATA32_PREFIX;
3ffd33cf 12278 else
f16cd0d5
L		 12279 all_prefixes[last_data_prefix] = DATA16_PREFIX;
12280 default_prefixes |= PREFIX_DATA;
12281 }
12282 else if (rex & REX_W)
12283 {
12284 /* REX_W will override PREFIX_DATA. */
12285 default_prefixes |= PREFIX_DATA;
3ffd33cf
AM		 12286 }
12287 }
12288
8bb15339 12289 if (need_modrm)
252b5132
RH		 12290 {
12291 FETCH_DATA (info, codep + 1);
7967e09e
L		 12292 modrm.mod = (*codep >> 6) & 3;
12293 modrm.reg = (*codep >> 3) & 7;
12294 modrm.rm = *codep & 7;
252b5132
RH		 12295 }
12296
55b126d4
L		 12297 need_vex = 0;
12298 need_vex_reg = 0;
12299 vex_w_done = 0;
12300
ce518a5f 12301 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
252b5132
RH		 12302 {
12303 dofloat (sizeflag);
12304 }
12305 else
12306 {
8bb15339 12307 dp = get_valid_dis386 (dp, info);
b844680a 12308 if (dp != NULL && putop (dp->name, sizeflag) == 0)
ce518a5f
L		 12309 {
12310 for (i = 0; i < MAX_OPERANDS; ++i)
12311 {
246c51aa 12312 obufp = op_out[i];
ce518a5f
L		 12313 op_ad = MAX_OPERANDS - 1 - i;
12314 if (dp->op[i].rtn)
12315 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12316 }
6439fc28 12317 }
252b5132
RH		 12318 }
12319
7d421014
ILT		 12320 /* See if any prefixes were not used. If so, print the first one
12321 separately. If we don't do this, we'll wind up printing an
12322 instruction stream which does not precisely correspond to the
12323 bytes we are disassembling. */
f16cd0d5 12324 if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
7d421014 12325 {
f16cd0d5
L		 12326 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12327 if (all_prefixes[i])
12328 {
12329 const char *name;
12330 name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
12331 if (name == NULL)
12332 name = INTERNAL_DISASSEMBLER_ERROR;
12333 (*info->fprintf_func) (info->stream, "%s", name);
12334 return 1;
12335 }
52b15da3 12336 }
7d421014 12337
d869730d 12338 /* Check if the REX prefix is used. */
2a70cca4 12339 if (rex_ignored == 0 && (rex ^ rex_used) == 0)
f16cd0d5
L		 12340 all_prefixes[last_rex_prefix] = 0;
12341
12342 /* Check if the SEG prefix used. */
12343 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12344 | PREFIX_FS | PREFIX_GS)) != 0
12345 && (used_prefixes
12346 & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
12347 all_prefixes[last_seg_prefix] = 0;
12348
12349 /* Check if the ADDR prefix used. */
12350 if ((prefixes & PREFIX_ADDR) != 0
12351 && (used_prefixes & PREFIX_ADDR) != 0)
12352 all_prefixes[last_addr_prefix] = 0;
12353
12354 /* Check if the DATA prefix used. */
12355 if ((prefixes & PREFIX_DATA) != 0
12356 && (used_prefixes & PREFIX_DATA) != 0)
12357 all_prefixes[last_data_prefix] = 0;
12358
12359 prefix_length = 0;
f310f33d 12360 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
f16cd0d5
L		 12361 if (all_prefixes[i])
12362 {
12363 const char *name;
12364 name = prefix_name (all_prefixes[i], sizeflag);
12365 if (name == NULL)
12366 abort ();
12367 prefix_length += strlen (name) + 1;
12368 (*info->fprintf_func) (info->stream, "%s ", name);
12369 }
b844680a 12370
f16cd0d5
L		 12371 /* Check maximum code length. */
12372 if ((codep - start_codep) > MAX_CODE_LENGTH)
12373 {
12374 (*info->fprintf_func) (info->stream, "(bad)");
12375 return MAX_CODE_LENGTH;
12376 }
b844680a 12377
ea397f5b 12378 obufp = mnemonicendp;
f16cd0d5 12379 for (i = strlen (obuf) + prefix_length; i < 6; i++)
252b5132
RH		 12380 oappend (" ");
12381 oappend (" ");
12382 (*info->fprintf_func) (info->stream, "%s", obuf);
12383
12384 /* The enter and bound instructions are printed with operands in the same
12385 order as the intel book; everything else is printed in reverse order. */
2da11e11 12386 if (intel_syntax || two_source_ops)
252b5132 12387 {
185b1163
L		 12388 bfd_vma riprel;
12389
ce518a5f
L		 12390 for (i = 0; i < MAX_OPERANDS; ++i)
12391 op_txt[i] = op_out[i];
246c51aa 12392
ce518a5f
L		 12393 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12394 {
12395 op_ad = op_index[i];
12396 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12397 op_index[MAX_OPERANDS - 1 - i] = op_ad;
185b1163
L		 12398 riprel = op_riprel[i];
12399 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12400 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
ce518a5f 12401 }
252b5132
RH		 12402 }
12403 else
12404 {
ce518a5f
L		 12405 for (i = 0; i < MAX_OPERANDS; ++i)
12406 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
050dfa73
MM		 12407 }
12408
ce518a5f
L		 12409 needcomma = 0;
12410 for (i = 0; i < MAX_OPERANDS; ++i)
12411 if (*op_txt[i])
12412 {
12413 if (needcomma)
12414 (*info->fprintf_func) (info->stream, ",");
12415 if (op_index[i] != -1 && !op_riprel[i])
12416 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12417 else
12418 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12419 needcomma = 1;
12420 }
050dfa73 12421
ce518a5f 12422 for (i = 0; i < MAX_OPERANDS; i++)
52b15da3
JH		 12423 if (op_index[i] != -1 && op_riprel[i])
12424 {
12425 (*info->fprintf_func) (info->stream, " # ");
12426 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
12427 + op_address[op_index[i]]), info);
185b1163 12428 break;
52b15da3 12429 }
e396998b 12430 return codep - priv.the_buffer;
252b5132
RH		 12431}
12432
6439fc28 12433static const char *float_mem[] = {
252b5132 12434 /* d8 */
7c52e0e8
L		 12435 "fadd{s|}",
12436 "fmul{s|}",
12437 "fcom{s|}",
12438 "fcomp{s|}",
12439 "fsub{s|}",
12440 "fsubr{s|}",
12441 "fdiv{s|}",
12442 "fdivr{s|}",
db6eb5be 12443 /* d9 */
7c52e0e8 12444 "fld{s|}",
252b5132 12445 "(bad)",
7c52e0e8
L		 12446 "fst{s|}",
12447 "fstp{s|}",
9306ca4a 12448 "fldenvIC",
252b5132 12449 "fldcw",
9306ca4a 12450 "fNstenvIC",
252b5132
RH		 12451 "fNstcw",
12452 /* da */
7c52e0e8
L		 12453 "fiadd{l|}",
12454 "fimul{l|}",
12455 "ficom{l|}",
12456 "ficomp{l|}",
12457 "fisub{l|}",
12458 "fisubr{l|}",
12459 "fidiv{l|}",
12460 "fidivr{l|}",
252b5132 12461 /* db */
7c52e0e8
L		 12462 "fild{l|}",
12463 "fisttp{l|}",
12464 "fist{l|}",
12465 "fistp{l|}",
252b5132 12466 "(bad)",
6439fc28 12467 "fld{t||t|}",
252b5132 12468 "(bad)",
6439fc28 12469 "fstp{t||t|}",
252b5132 12470 /* dc */
7c52e0e8
L		 12471 "fadd{l|}",
12472 "fmul{l|}",
12473 "fcom{l|}",
12474 "fcomp{l|}",
12475 "fsub{l|}",
12476 "fsubr{l|}",
12477 "fdiv{l|}",
12478 "fdivr{l|}",
252b5132 12479 /* dd */
7c52e0e8
L		 12480 "fld{l|}",
12481 "fisttp{ll|}",
12482 "fst{l||}",
12483 "fstp{l|}",
9306ca4a 12484 "frstorIC",
252b5132 12485 "(bad)",
9306ca4a 12486 "fNsaveIC",
252b5132
RH		 12487 "fNstsw",
12488 /* de */
12489 "fiadd",
12490 "fimul",
12491 "ficom",
12492 "ficomp",
12493 "fisub",
12494 "fisubr",
12495 "fidiv",
12496 "fidivr",
12497 /* df */
12498 "fild",
ca164297 12499 "fisttp",
252b5132
RH		 12500 "fist",
12501 "fistp",
12502 "fbld",
7c52e0e8 12503 "fild{ll|}",
252b5132 12504 "fbstp",
7c52e0e8 12505 "fistp{ll|}",
1d9f512f
AM		 12506};
12507
12508static const unsigned char float_mem_mode[] = {
12509 /* d8 */
12510 d_mode,
12511 d_mode,
12512 d_mode,
12513 d_mode,
12514 d_mode,
12515 d_mode,
12516 d_mode,
12517 d_mode,
12518 /* d9 */
12519 d_mode,
12520 0,
12521 d_mode,
12522 d_mode,
12523 0,
12524 w_mode,
12525 0,
12526 w_mode,
12527 /* da */
12528 d_mode,
12529 d_mode,
12530 d_mode,
12531 d_mode,
12532 d_mode,
12533 d_mode,
12534 d_mode,
12535 d_mode,
12536 /* db */
12537 d_mode,
12538 d_mode,
12539 d_mode,
12540 d_mode,
12541 0,
9306ca4a 12542 t_mode,
1d9f512f 12543 0,
9306ca4a 12544 t_mode,
1d9f512f
AM		 12545 /* dc */
12546 q_mode,
12547 q_mode,
12548 q_mode,
12549 q_mode,
12550 q_mode,
12551 q_mode,
12552 q_mode,
12553 q_mode,
12554 /* dd */
12555 q_mode,
12556 q_mode,
12557 q_mode,
12558 q_mode,
12559 0,
12560 0,
12561 0,
12562 w_mode,
12563 /* de */
12564 w_mode,
12565 w_mode,
12566 w_mode,
12567 w_mode,
12568 w_mode,
12569 w_mode,
12570 w_mode,
12571 w_mode,
12572 /* df */
12573 w_mode,
12574 w_mode,
12575 w_mode,
12576 w_mode,
9306ca4a 12577 t_mode,
1d9f512f 12578 q_mode,
9306ca4a 12579 t_mode,
1d9f512f 12580 q_mode
252b5132
RH		 12581};
12582
ce518a5f
L		 12583#define ST { OP_ST, 0 }
12584#define STi { OP_STi, 0 }
252b5132 12585
4efba78c
L		 12586#define FGRPd9_2 NULL, { { NULL, 0 } }
12587#define FGRPd9_4 NULL, { { NULL, 1 } }
12588#define FGRPd9_5 NULL, { { NULL, 2 } }
12589#define FGRPd9_6 NULL, { { NULL, 3 } }
12590#define FGRPd9_7 NULL, { { NULL, 4 } }
12591#define FGRPda_5 NULL, { { NULL, 5 } }
12592#define FGRPdb_4 NULL, { { NULL, 6 } }
12593#define FGRPde_3 NULL, { { NULL, 7 } }
12594#define FGRPdf_4 NULL, { { NULL, 8 } }
252b5132 12595
2da11e11 12596static const struct dis386 float_reg[][8] = {
252b5132
RH		 12597 /* d8 */
12598 {
ce518a5f
L		 12599 { "fadd", { ST, STi } },
12600 { "fmul", { ST, STi } },
12601 { "fcom", { STi } },
12602 { "fcomp", { STi } },
12603 { "fsub", { ST, STi } },
12604 { "fsubr", { ST, STi } },
12605 { "fdiv", { ST, STi } },
12606 { "fdivr", { ST, STi } },
252b5132
RH		 12607 },
12608 /* d9 */
12609 {
ce518a5f
L		 12610 { "fld", { STi } },
12611 { "fxch", { STi } },
252b5132 12612 { FGRPd9_2 },
ce518a5f 12613 { "(bad)", { XX } },
252b5132
RH		 12614 { FGRPd9_4 },
12615 { FGRPd9_5 },
12616 { FGRPd9_6 },
12617 { FGRPd9_7 },
12618 },
12619 /* da */
12620 {
ce518a5f
L		 12621 { "fcmovb", { ST, STi } },
12622 { "fcmove", { ST, STi } },
12623 { "fcmovbe",{ ST, STi } },
12624 { "fcmovu", { ST, STi } },
12625 { "(bad)", { XX } },
252b5132 12626 { FGRPda_5 },
ce518a5f
L		 12627 { "(bad)", { XX } },
12628 { "(bad)", { XX } },
252b5132
RH		 12629 },
12630 /* db */
12631 {
ce518a5f
L		 12632 { "fcmovnb",{ ST, STi } },
12633 { "fcmovne",{ ST, STi } },
12634 { "fcmovnbe",{ ST, STi } },
12635 { "fcmovnu",{ ST, STi } },
252b5132 12636 { FGRPdb_4 },
ce518a5f
L		 12637 { "fucomi", { ST, STi } },
12638 { "fcomi", { ST, STi } },
12639 { "(bad)", { XX } },
252b5132
RH		 12640 },
12641 /* dc */
12642 {
ce518a5f
L		 12643 { "fadd", { STi, ST } },
12644 { "fmul", { STi, ST } },
12645 { "(bad)", { XX } },
12646 { "(bad)", { XX } },
9d141669
L		 12647 { "fsub!M", { STi, ST } },
12648 { "fsubM", { STi, ST } },
12649 { "fdiv!M", { STi, ST } },
12650 { "fdivM", { STi, ST } },
252b5132
RH		 12651 },
12652 /* dd */
12653 {
ce518a5f
L		 12654 { "ffree", { STi } },
12655 { "(bad)", { XX } },
12656 { "fst", { STi } },
12657 { "fstp", { STi } },
12658 { "fucom", { STi } },
12659 { "fucomp", { STi } },
12660 { "(bad)", { XX } },
12661 { "(bad)", { XX } },
252b5132
RH		 12662 },
12663 /* de */
12664 {
ce518a5f
L		 12665 { "faddp", { STi, ST } },
12666 { "fmulp", { STi, ST } },
12667 { "(bad)", { XX } },
252b5132 12668 { FGRPde_3 },
9d141669
L		 12669 { "fsub!Mp", { STi, ST } },
12670 { "fsubMp", { STi, ST } },
12671 { "fdiv!Mp", { STi, ST } },
12672 { "fdivMp", { STi, ST } },
252b5132
RH		 12673 },
12674 /* df */
12675 {
ce518a5f
L		 12676 { "ffreep", { STi } },
12677 { "(bad)", { XX } },
12678 { "(bad)", { XX } },
12679 { "(bad)", { XX } },
252b5132 12680 { FGRPdf_4 },
ce518a5f
L		 12681 { "fucomip", { ST, STi } },
12682 { "fcomip", { ST, STi } },
12683 { "(bad)", { XX } },
252b5132
RH		 12684 },
12685};
12686
252b5132
RH		 12687static char *fgrps[][8] = {
12688 /* d9_2 0 */
12689 {
12690 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12691 },
12692
12693 /* d9_4 1 */
12694 {
12695 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12696 },
12697
12698 /* d9_5 2 */
12699 {
12700 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12701 },
12702
12703 /* d9_6 3 */
12704 {
12705 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12706 },
12707
12708 /* d9_7 4 */
12709 {
12710 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12711 },
12712
12713 /* da_5 5 */
12714 {
12715 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12716 },
12717
12718 /* db_4 6 */
12719 {
309d3373
JB		 12720 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12721 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
252b5132
RH		 12722 },
12723
12724 /* de_3 7 */
12725 {
12726 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12727 },
12728
12729 /* df_4 8 */
12730 {
12731 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12732 },
12733};
12734
b6169b20
L		 12735static void
12736swap_operand (void)
12737{
12738 mnemonicendp[0] = '.';
12739 mnemonicendp[1] = 's';
12740 mnemonicendp += 2;
12741}
12742
b844680a
L		 12743static void
12744OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12745 int sizeflag ATTRIBUTE_UNUSED)
12746{
12747 /* Skip mod/rm byte. */
12748 MODRM_CHECK;
12749 codep++;
12750}
12751
252b5132 12752static void
26ca5450 12753dofloat (int sizeflag)
252b5132 12754{
2da11e11 12755 const struct dis386 *dp;
252b5132
RH		 12756 unsigned char floatop;
12757
12758 floatop = codep[-1];
12759
7967e09e 12760 if (modrm.mod != 3)
252b5132 12761 {
7967e09e 12762 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
1d9f512f
AM		 12763
12764 putop (float_mem[fp_indx], sizeflag);
ce518a5f 12765 obufp = op_out[0];
6e50d963 12766 op_ad = 2;
1d9f512f 12767 OP_E (float_mem_mode[fp_indx], sizeflag);
252b5132
RH		 12768 return;
12769 }
6608db57 12770 /* Skip mod/rm byte. */
4bba6815 12771 MODRM_CHECK;
252b5132
RH		 12772 codep++;
12773
7967e09e 12774 dp = &float_reg[floatop - 0xd8][modrm.reg];
252b5132
RH		 12775 if (dp->name == NULL)
12776 {
7967e09e 12777 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
252b5132 12778
6608db57 12779 /* Instruction fnstsw is only one with strange arg. */
252b5132 12780 if (floatop == 0xdf && codep[-1] == 0xe0)
ce518a5f 12781 strcpy (op_out[0], names16[0]);
252b5132
RH		 12782 }
12783 else
12784 {
12785 putop (dp->name, sizeflag);
12786
ce518a5f 12787 obufp = op_out[0];
6e50d963 12788 op_ad = 2;
ce518a5f
L		 12789 if (dp->op[0].rtn)
12790 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
6e50d963 12791
ce518a5f 12792 obufp = op_out[1];
6e50d963 12793 op_ad = 1;
ce518a5f
L		 12794 if (dp->op[1].rtn)
12795 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
252b5132
RH		 12796 }
12797}
12798
252b5132 12799static void
26ca5450 12800OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 12801{
422673a9 12802 oappend ("%st" + intel_syntax);
252b5132
RH		 12803}
12804
252b5132 12805static void
26ca5450 12806OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 12807{
7967e09e 12808 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
d708bcba 12809 oappend (scratchbuf + intel_syntax);
252b5132
RH		 12810}
12811
6608db57 12812/* Capital letters in template are macros. */
6439fc28 12813static int
d3ce72d0 12814putop (const char *in_template, int sizeflag)
252b5132 12815{
2da11e11 12816 const char *p;
9306ca4a 12817 int alt = 0;
9d141669 12818 int cond = 1;
98b528ac
L		 12819 unsigned int l = 0, len = 1;
12820 char last[4];
12821
12822#define SAVE_LAST(c) \
12823 if (l < len && l < sizeof (last)) \
12824 last[l++] = c; \
12825 else \
12826 abort ();
252b5132 12827
d3ce72d0 12828 for (p = in_template; *p; p++)
252b5132
RH		 12829 {
12830 switch (*p)
12831 {
12832 default:
12833 *obufp++ = *p;
12834 break;
98b528ac
L		 12835 case '%':
12836 len++;
12837 break;
9d141669
L		 12838 case '!':
12839 cond = 0;
12840 break;
6439fc28
AM		 12841 case '{':
12842 alt = 0;
12843 if (intel_syntax)
6439fc28
AM		 12844 {
12845 while (*++p != '|')
7c52e0e8
L		 12846 if (*p == '}' || *p == '\0')
12847 abort ();
6439fc28 12848 }
9306ca4a
JB		 12849 /* Fall through. */
12850 case 'I':
12851 alt = 1;
12852 continue;
6439fc28
AM		 12853 case '|':
12854 while (*++p != '}')
12855 {
12856 if (*p == '\0')
12857 abort ();
12858 }
12859 break;
12860 case '}':
12861 break;
252b5132 12862 case 'A':
db6eb5be
AM		 12863 if (intel_syntax)
12864 break;
7967e09e 12865 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132
RH		 12866 *obufp++ = 'b';
12867 break;
12868 case 'B':
4b06377f
L		 12869 if (l == 0 && len == 1)
12870 {
12871case_B:
12872 if (intel_syntax)
12873 break;
12874 if (sizeflag & SUFFIX_ALWAYS)
12875 *obufp++ = 'b';
12876 }
12877 else
12878 {
12879 if (l != 1
12880 || len != 2
12881 || last[0] != 'L')
12882 {
12883 SAVE_LAST (*p);
12884 break;
12885 }
12886
12887 if (address_mode == mode_64bit
12888 && !(prefixes & PREFIX_ADDR))
12889 {
12890 *obufp++ = 'a';
12891 *obufp++ = 'b';
12892 *obufp++ = 's';
12893 }
12894
12895 goto case_B;
12896 }
252b5132 12897 break;
9306ca4a
JB		 12898 case 'C':
12899 if (intel_syntax && !alt)
12900 break;
12901 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12902 {
12903 if (sizeflag & DFLAG)
12904 *obufp++ = intel_syntax ? 'd' : 'l';
12905 else
12906 *obufp++ = intel_syntax ? 'w' : 's';
12907 used_prefixes |= (prefixes & PREFIX_DATA);
12908 }
12909 break;
ed7841b3
JB		 12910 case 'D':
12911 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12912 break;
161a04f6 12913 USED_REX (REX_W);
7967e09e 12914 if (modrm.mod == 3)
ed7841b3 12915 {
161a04f6 12916 if (rex & REX_W)
ed7841b3 12917 *obufp++ = 'q';
ed7841b3 12918 else
f16cd0d5
L		 12919 {
12920 if (sizeflag & DFLAG)
12921 *obufp++ = intel_syntax ? 'd' : 'l';
12922 else
12923 *obufp++ = 'w';
12924 used_prefixes |= (prefixes & PREFIX_DATA);
12925 }
ed7841b3
JB		 12926 }
12927 else
12928 *obufp++ = 'w';
12929 break;
252b5132 12930 case 'E': /* For jcxz/jecxz */
cb712a9e 12931 if (address_mode == mode_64bit)
c1a64871
JH		 12932 {
12933 if (sizeflag & AFLAG)
12934 *obufp++ = 'r';
12935 else
12936 *obufp++ = 'e';
12937 }
12938 else
12939 if (sizeflag & AFLAG)
12940 *obufp++ = 'e';
3ffd33cf
AM		 12941 used_prefixes |= (prefixes & PREFIX_ADDR);
12942 break;
12943 case 'F':
db6eb5be
AM		 12944 if (intel_syntax)
12945 break;
e396998b 12946 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
3ffd33cf
AM		 12947 {
12948 if (sizeflag & AFLAG)
cb712a9e 12949 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
3ffd33cf 12950 else
cb712a9e 12951 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
3ffd33cf
AM		 12952 used_prefixes |= (prefixes & PREFIX_ADDR);
12953 }
252b5132 12954 break;
52fd6d94
JB		 12955 case 'G':
12956 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12957 break;
161a04f6 12958 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 12959 *obufp++ = 'l';
12960 else
12961 *obufp++ = 'w';
161a04f6 12962 if (!(rex & REX_W))
52fd6d94
JB		 12963 used_prefixes |= (prefixes & PREFIX_DATA);
12964 break;
5dd0794d 12965 case 'H':
db6eb5be
AM		 12966 if (intel_syntax)
12967 break;
5dd0794d
AM		 12968 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12969 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12970 {
12971 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12972 *obufp++ = ',';
12973 *obufp++ = 'p';
12974 if (prefixes & PREFIX_DS)
12975 *obufp++ = 't';
12976 else
12977 *obufp++ = 'n';
12978 }
12979 break;
9306ca4a
JB		 12980 case 'J':
12981 if (intel_syntax)
12982 break;
12983 *obufp++ = 'l';
12984 break;
42903f7f
L		 12985 case 'K':
12986 USED_REX (REX_W);
12987 if (rex & REX_W)
12988 *obufp++ = 'q';
12989 else
12990 *obufp++ = 'd';
12991 break;
6dd5059a
L		 12992 case 'Z':
12993 if (intel_syntax)
12994 break;
12995 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12996 {
12997 *obufp++ = 'q';
12998 break;
12999 }
13000 /* Fall through. */
98b528ac 13001 goto case_L;
252b5132 13002 case 'L':
98b528ac
L		 13003 if (l != 0 || len != 1)
13004 {
13005 SAVE_LAST (*p);
13006 break;
13007 }
13008case_L:
db6eb5be
AM		 13009 if (intel_syntax)
13010 break;
252b5132
RH		 13011 if (sizeflag & SUFFIX_ALWAYS)
13012 *obufp++ = 'l';
252b5132 13013 break;
9d141669
L		 13014 case 'M':
13015 if (intel_mnemonic != cond)
13016 *obufp++ = 'r';
13017 break;
252b5132
RH		 13018 case 'N':
13019 if ((prefixes & PREFIX_FWAIT) == 0)
13020 *obufp++ = 'n';
7d421014
ILT		 13021 else
13022 used_prefixes |= PREFIX_FWAIT;
252b5132 13023 break;
52b15da3 13024 case 'O':
161a04f6
L		 13025 USED_REX (REX_W);
13026 if (rex & REX_W)
6439fc28 13027 *obufp++ = 'o';
a35ca55a
JB		 13028 else if (intel_syntax && (sizeflag & DFLAG))
13029 *obufp++ = 'q';
52b15da3
JH		 13030 else
13031 *obufp++ = 'd';
161a04f6 13032 if (!(rex & REX_W))
a35ca55a 13033 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 13034 break;
6439fc28 13035 case 'T':
db6eb5be
AM		 13036 if (intel_syntax)
13037 break;
cb712a9e 13038 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 13039 {
13040 *obufp++ = 'q';
13041 break;
13042 }
6608db57 13043 /* Fall through. */
252b5132 13044 case 'P':
db6eb5be
AM		 13045 if (intel_syntax)
13046 break;
252b5132 13047 if ((prefixes & PREFIX_DATA)
161a04f6 13048 || (rex & REX_W)
e396998b 13049 || (sizeflag & SUFFIX_ALWAYS))
252b5132 13050 {
161a04f6
L		 13051 USED_REX (REX_W);
13052 if (rex & REX_W)
52b15da3 13053 *obufp++ = 'q';
c2419411 13054 else
52b15da3
JH		 13055 {
13056 if (sizeflag & DFLAG)
13057 *obufp++ = 'l';
13058 else
13059 *obufp++ = 'w';
f16cd0d5 13060 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 13061 }
252b5132
RH		 13062 }
13063 break;
6439fc28 13064 case 'U':
db6eb5be
AM		 13065 if (intel_syntax)
13066 break;
cb712a9e 13067 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28 13068 {
7967e09e 13069 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
1a114b12 13070 *obufp++ = 'q';
6439fc28
AM		 13071 break;
13072 }
6608db57 13073 /* Fall through. */
98b528ac 13074 goto case_Q;
252b5132 13075 case 'Q':
98b528ac 13076 if (l == 0 && len == 1)
252b5132 13077 {
98b528ac
L		 13078case_Q:
13079 if (intel_syntax && !alt)
13080 break;
13081 USED_REX (REX_W);
13082 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
52b15da3 13083 {
98b528ac
L		 13084 if (rex & REX_W)
13085 *obufp++ = 'q';
52b15da3 13086 else
98b528ac
L		 13087 {
13088 if (sizeflag & DFLAG)
13089 *obufp++ = intel_syntax ? 'd' : 'l';
13090 else
13091 *obufp++ = 'w';
f16cd0d5 13092 used_prefixes |= (prefixes & PREFIX_DATA);
98b528ac 13093 }
52b15da3 13094 }
98b528ac
L		 13095 }
13096 else
13097 {
13098 if (l != 1 || len != 2 || last[0] != 'L')
13099 {
13100 SAVE_LAST (*p);
13101 break;
13102 }
13103 if (intel_syntax
13104 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13105 break;
13106 if ((rex & REX_W))
13107 {
13108 USED_REX (REX_W);
13109 *obufp++ = 'q';
13110 }
13111 else
13112 *obufp++ = 'l';
252b5132
RH		 13113 }
13114 break;
13115 case 'R':
161a04f6
L		 13116 USED_REX (REX_W);
13117 if (rex & REX_W)
a35ca55a
JB		 13118 *obufp++ = 'q';
13119 else if (sizeflag & DFLAG)
c608c12e 13120 {
a35ca55a 13121 if (intel_syntax)
c608c12e 13122 *obufp++ = 'd';
c608c12e 13123 else
a35ca55a 13124 *obufp++ = 'l';
c608c12e 13125 }
252b5132 13126 else
a35ca55a
JB		 13127 *obufp++ = 'w';
13128 if (intel_syntax && !p[1]
161a04f6 13129 && ((rex & REX_W) || (sizeflag & DFLAG)))
a35ca55a 13130 *obufp++ = 'e';
161a04f6 13131 if (!(rex & REX_W))
52b15da3 13132 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 13133 break;
1a114b12 13134 case 'V':
4b06377f 13135 if (l == 0 && len == 1)
1a114b12 13136 {
4b06377f
L		 13137 if (intel_syntax)
13138 break;
13139 if (address_mode == mode_64bit && (sizeflag & DFLAG))
13140 {
13141 if (sizeflag & SUFFIX_ALWAYS)
13142 *obufp++ = 'q';
13143 break;
13144 }
13145 }
13146 else
13147 {
13148 if (l != 1
13149 || len != 2
13150 || last[0] != 'L')
13151 {
13152 SAVE_LAST (*p);
13153 break;
13154 }
13155
13156 if (rex & REX_W)
13157 {
13158 *obufp++ = 'a';
13159 *obufp++ = 'b';
13160 *obufp++ = 's';
13161 }
1a114b12
JB		 13162 }
13163 /* Fall through. */
4b06377f 13164 goto case_S;
252b5132 13165 case 'S':
4b06377f 13166 if (l == 0 && len == 1)
252b5132 13167 {
4b06377f
L		 13168case_S:
13169 if (intel_syntax)
13170 break;
13171 if (sizeflag & SUFFIX_ALWAYS)
52b15da3 13172 {
4b06377f
L		 13173 if (rex & REX_W)
13174 *obufp++ = 'q';
52b15da3 13175 else
4b06377f
L		 13176 {
13177 if (sizeflag & DFLAG)
13178 *obufp++ = 'l';
13179 else
13180 *obufp++ = 'w';
13181 used_prefixes |= (prefixes & PREFIX_DATA);
13182 }
13183 }
13184 }
13185 else
13186 {
13187 if (l != 1
13188 || len != 2
13189 || last[0] != 'L')
13190 {
13191 SAVE_LAST (*p);
13192 break;
52b15da3 13193 }
4b06377f
L		 13194
13195 if (address_mode == mode_64bit
13196 && !(prefixes & PREFIX_ADDR))
13197 {
13198 *obufp++ = 'a';
13199 *obufp++ = 'b';
13200 *obufp++ = 's';
13201 }
13202
13203 goto case_S;
252b5132 13204 }
252b5132 13205 break;
041bd2e0 13206 case 'X':
c0f3af97
L		 13207 if (l != 0 || len != 1)
13208 {
13209 SAVE_LAST (*p);
13210 break;
13211 }
13212 if (need_vex && vex.prefix)
13213 {
13214 if (vex.prefix == DATA_PREFIX_OPCODE)
13215 *obufp++ = 'd';
13216 else
13217 *obufp++ = 's';
13218 }
041bd2e0 13219 else
f16cd0d5
L		 13220 {
13221 if (prefixes & PREFIX_DATA)
13222 *obufp++ = 'd';
13223 else
13224 *obufp++ = 's';
13225 used_prefixes |= (prefixes & PREFIX_DATA);
13226 }
041bd2e0 13227 break;
76f227a5 13228 case 'Y':
c0f3af97 13229 if (l == 0 && len == 1)
76f227a5 13230 {
c0f3af97
L		 13231 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13232 break;
13233 if (rex & REX_W)
13234 {
13235 USED_REX (REX_W);
13236 *obufp++ = 'q';
13237 }
13238 break;
13239 }
13240 else
13241 {
13242 if (l != 1 || len != 2 || last[0] != 'X')
13243 {
13244 SAVE_LAST (*p);
13245 break;
13246 }
13247 if (!need_vex)
13248 abort ();
13249 if (intel_syntax
13250 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13251 break;
13252 switch (vex.length)
13253 {
13254 case 128:
13255 *obufp++ = 'x';
13256 break;
13257 case 256:
13258 *obufp++ = 'y';
13259 break;
13260 default:
13261 abort ();
13262 }
76f227a5
JH		 13263 }
13264 break;
252b5132 13265 case 'W':
0bfee649 13266 if (l == 0 && len == 1)
a35ca55a 13267 {
0bfee649
L		 13268 /* operand size flag for cwtl, cbtw */
13269 USED_REX (REX_W);
13270 if (rex & REX_W)
13271 {
13272 if (intel_syntax)
13273 *obufp++ = 'd';
13274 else
13275 *obufp++ = 'l';
13276 }
13277 else if (sizeflag & DFLAG)
13278 *obufp++ = 'w';
a35ca55a 13279 else
0bfee649
L		 13280 *obufp++ = 'b';
13281 if (!(rex & REX_W))
13282 used_prefixes |= (prefixes & PREFIX_DATA);
a35ca55a 13283 }
252b5132 13284 else
0bfee649
L		 13285 {
13286 if (l != 1 || len != 2 || last[0] != 'X')
13287 {
13288 SAVE_LAST (*p);
13289 break;
13290 }
13291 if (!need_vex)
13292 abort ();
13293 *obufp++ = vex.w ? 'd': 's';
13294 }
252b5132
RH		 13295 break;
13296 }
9306ca4a 13297 alt = 0;
252b5132
RH		 13298 }
13299 *obufp = 0;
ea397f5b 13300 mnemonicendp = obufp;
6439fc28 13301 return 0;
252b5132
RH		 13302}
13303
13304static void
26ca5450 13305oappend (const char *s)
252b5132 13306{
ea397f5b 13307 obufp = stpcpy (obufp, s);
252b5132
RH		 13308}
13309
13310static void
26ca5450 13311append_seg (void)
252b5132
RH		 13312{
13313 if (prefixes & PREFIX_CS)
7d421014 13314 {
7d421014 13315 used_prefixes |= PREFIX_CS;
d708bcba 13316 oappend ("%cs:" + intel_syntax);
7d421014 13317 }
252b5132 13318 if (prefixes & PREFIX_DS)
7d421014 13319 {
7d421014 13320 used_prefixes |= PREFIX_DS;
d708bcba 13321 oappend ("%ds:" + intel_syntax);
7d421014 13322 }
252b5132 13323 if (prefixes & PREFIX_SS)
7d421014 13324 {
7d421014 13325 used_prefixes |= PREFIX_SS;
d708bcba 13326 oappend ("%ss:" + intel_syntax);
7d421014 13327 }
252b5132 13328 if (prefixes & PREFIX_ES)
7d421014 13329 {
7d421014 13330 used_prefixes |= PREFIX_ES;
d708bcba 13331 oappend ("%es:" + intel_syntax);
7d421014 13332 }
252b5132 13333 if (prefixes & PREFIX_FS)
7d421014 13334 {
7d421014 13335 used_prefixes |= PREFIX_FS;
d708bcba 13336 oappend ("%fs:" + intel_syntax);
7d421014 13337 }
252b5132 13338 if (prefixes & PREFIX_GS)
7d421014 13339 {
7d421014 13340 used_prefixes |= PREFIX_GS;
d708bcba 13341 oappend ("%gs:" + intel_syntax);
7d421014 13342 }
252b5132
RH		 13343}
13344
13345static void
26ca5450 13346OP_indirE (int bytemode, int sizeflag)
252b5132
RH		 13347{
13348 if (!intel_syntax)
13349 oappend ("*");
13350 OP_E (bytemode, sizeflag);
13351}
13352
52b15da3 13353static void
26ca5450 13354print_operand_value (char *buf, int hex, bfd_vma disp)
52b15da3 13355{
cb712a9e 13356 if (address_mode == mode_64bit)
52b15da3
JH		 13357 {
13358 if (hex)
13359 {
13360 char tmp[30];
13361 int i;
13362 buf[0] = '0';
13363 buf[1] = 'x';
13364 sprintf_vma (tmp, disp);
6608db57 13365 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
52b15da3
JH		 13366 strcpy (buf + 2, tmp + i);
13367 }
13368 else
13369 {
13370 bfd_signed_vma v = disp;
13371 char tmp[30];
13372 int i;
13373 if (v < 0)
13374 {
13375 *(buf++) = '-';
13376 v = -disp;
6608db57 13377 /* Check for possible overflow on 0x8000000000000000. */
52b15da3
JH		 13378 if (v < 0)
13379 {
13380 strcpy (buf, "9223372036854775808");
13381 return;
13382 }
13383 }
13384 if (!v)
13385 {
13386 strcpy (buf, "0");
13387 return;
13388 }
13389
13390 i = 0;
13391 tmp[29] = 0;
13392 while (v)
13393 {
6608db57 13394 tmp[28 - i] = (v % 10) + '0';
52b15da3
JH		 13395 v /= 10;
13396 i++;
13397 }
13398 strcpy (buf, tmp + 29 - i);
13399 }
13400 }
13401 else
13402 {
13403 if (hex)
13404 sprintf (buf, "0x%x", (unsigned int) disp);
13405 else
13406 sprintf (buf, "%d", (int) disp);
13407 }
13408}
13409
5d669648
L		 13410/* Put DISP in BUF as signed hex number. */
13411
13412static void
13413print_displacement (char *buf, bfd_vma disp)
13414{
13415 bfd_signed_vma val = disp;
13416 char tmp[30];
13417 int i, j = 0;
13418
13419 if (val < 0)
13420 {
13421 buf[j++] = '-';
13422 val = -disp;
13423
13424 /* Check for possible overflow. */
13425 if (val < 0)
13426 {
13427 switch (address_mode)
13428 {
13429 case mode_64bit:
13430 strcpy (buf + j, "0x8000000000000000");
13431 break;
13432 case mode_32bit:
13433 strcpy (buf + j, "0x80000000");
13434 break;
13435 case mode_16bit:
13436 strcpy (buf + j, "0x8000");
13437 break;
13438 }
13439 return;
13440 }
13441 }
13442
13443 buf[j++] = '0';
13444 buf[j++] = 'x';
13445
0af1713e 13446 sprintf_vma (tmp, (bfd_vma) val);
5d669648
L		 13447 for (i = 0; tmp[i] == '0'; i++)
13448 continue;
13449 if (tmp[i] == '\0')
13450 i--;
13451 strcpy (buf + j, tmp + i);
13452}
13453
3f31e633
JB		 13454static void
13455intel_operand_size (int bytemode, int sizeflag)
13456{
13457 switch (bytemode)
13458 {
13459 case b_mode:
b6169b20 13460 case b_swap_mode:
42903f7f 13461 case dqb_mode:
3f31e633
JB		 13462 oappend ("BYTE PTR ");
13463 break;
13464 case w_mode:
13465 case dqw_mode:
13466 oappend ("WORD PTR ");
13467 break;
1a114b12 13468 case stack_v_mode:
cb712a9e 13469 if (address_mode == mode_64bit && (sizeflag & DFLAG))
3f31e633
JB		 13470 {
13471 oappend ("QWORD PTR ");
3f31e633
JB		 13472 break;
13473 }
13474 /* FALLTHRU */
13475 case v_mode:
b6169b20 13476 case v_swap_mode:
3f31e633 13477 case dq_mode:
161a04f6
L		 13478 USED_REX (REX_W);
13479 if (rex & REX_W)
3f31e633 13480 oappend ("QWORD PTR ");
3f31e633 13481 else
f16cd0d5
L		 13482 {
13483 if ((sizeflag & DFLAG) || bytemode == dq_mode)
13484 oappend ("DWORD PTR ");
13485 else
13486 oappend ("WORD PTR ");
13487 used_prefixes |= (prefixes & PREFIX_DATA);
13488 }
3f31e633 13489 break;
52fd6d94 13490 case z_mode:
161a04f6 13491 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 13492 *obufp++ = 'D';
13493 oappend ("WORD PTR ");
161a04f6 13494 if (!(rex & REX_W))
52fd6d94
JB		 13495 used_prefixes |= (prefixes & PREFIX_DATA);
13496 break;
34b772a6
JB		 13497 case a_mode:
13498 if (sizeflag & DFLAG)
13499 oappend ("QWORD PTR ");
13500 else
13501 oappend ("DWORD PTR ");
13502 used_prefixes |= (prefixes & PREFIX_DATA);
13503 break;
3f31e633 13504 case d_mode:
fa99fab2 13505 case d_swap_mode:
42903f7f 13506 case dqd_mode:
3f31e633
JB		 13507 oappend ("DWORD PTR ");
13508 break;
13509 case q_mode:
b6169b20 13510 case q_swap_mode:
3f31e633
JB		 13511 oappend ("QWORD PTR ");
13512 break;
13513 case m_mode:
cb712a9e 13514 if (address_mode == mode_64bit)
3f31e633
JB		 13515 oappend ("QWORD PTR ");
13516 else
13517 oappend ("DWORD PTR ");
13518 break;
13519 case f_mode:
13520 if (sizeflag & DFLAG)
13521 oappend ("FWORD PTR ");
13522 else
13523 oappend ("DWORD PTR ");
13524 used_prefixes |= (prefixes & PREFIX_DATA);
13525 break;
13526 case t_mode:
13527 oappend ("TBYTE PTR ");
13528 break;
13529 case x_mode:
b6169b20 13530 case x_swap_mode:
c0f3af97
L		 13531 if (need_vex)
13532 {
13533 switch (vex.length)
13534 {
13535 case 128:
13536 oappend ("XMMWORD PTR ");
13537 break;
13538 case 256:
13539 oappend ("YMMWORD PTR ");
13540 break;
13541 default:
13542 abort ();
13543 }
13544 }
13545 else
13546 oappend ("XMMWORD PTR ");
13547 break;
13548 case xmm_mode:
3f31e633
JB		 13549 oappend ("XMMWORD PTR ");
13550 break;
c0f3af97
L		 13551 case xmmq_mode:
13552 if (!need_vex)
13553 abort ();
13554
13555 switch (vex.length)
13556 {
13557 case 128:
13558 oappend ("QWORD PTR ");
13559 break;
13560 case 256:
13561 oappend ("XMMWORD PTR ");
13562 break;
13563 default:
13564 abort ();
13565 }
13566 break;
13567 case ymmq_mode:
13568 if (!need_vex)
13569 abort ();
13570
13571 switch (vex.length)
13572 {
13573 case 128:
13574 oappend ("QWORD PTR ");
13575 break;
13576 case 256:
13577 oappend ("YMMWORD PTR ");
13578 break;
13579 default:
13580 abort ();
13581 }
13582 break;
fb9c77c7
L		 13583 case o_mode:
13584 oappend ("OWORD PTR ");
13585 break;
0bfee649
L		 13586 case vex_w_dq_mode:
13587 if (!need_vex)
13588 abort ();
13589
13590 if (vex.w)
13591 oappend ("QWORD PTR ");
13592 else
13593 oappend ("DWORD PTR ");
13594 break;
3f31e633
JB		 13595 default:
13596 break;
13597 }
13598}
13599
252b5132 13600static void
c0f3af97 13601OP_E_register (int bytemode, int sizeflag)
252b5132 13602{
c0f3af97
L		 13603 int reg = modrm.rm;
13604 const char **names;
252b5132 13605
c0f3af97
L		 13606 USED_REX (REX_B);
13607 if ((rex & REX_B))
13608 reg += 8;
252b5132 13609
b6169b20
L		 13610 if ((sizeflag & SUFFIX_ALWAYS)
13611 && (bytemode == b_swap_mode || bytemode == v_swap_mode))
13612 swap_operand ();
13613
c0f3af97 13614 switch (bytemode)
252b5132 13615 {
c0f3af97 13616 case b_mode:
b6169b20 13617 case b_swap_mode:
c0f3af97
L		 13618 USED_REX (0);
13619 if (rex)
13620 names = names8rex;
13621 else
13622 names = names8;
13623 break;
13624 case w_mode:
13625 names = names16;
13626 break;
13627 case d_mode:
13628 names = names32;
13629 break;
13630 case q_mode:
13631 names = names64;
13632 break;
13633 case m_mode:
13634 names = address_mode == mode_64bit ? names64 : names32;
13635 break;
13636 case stack_v_mode:
13637 if (address_mode == mode_64bit && (sizeflag & DFLAG))
252b5132 13638 {
c0f3af97 13639 names = names64;
252b5132 13640 break;
252b5132 13641 }
c0f3af97
L		 13642 bytemode = v_mode;
13643 /* FALLTHRU */
13644 case v_mode:
b6169b20 13645 case v_swap_mode:
c0f3af97
L		 13646 case dq_mode:
13647 case dqb_mode:
13648 case dqd_mode:
13649 case dqw_mode:
13650 USED_REX (REX_W);
13651 if (rex & REX_W)
13652 names = names64;
c0f3af97 13653 else
f16cd0d5
L		 13654 {
13655 if ((sizeflag & DFLAG)
13656 || (bytemode != v_mode
13657 && bytemode != v_swap_mode))
13658 names = names32;
13659 else
13660 names = names16;
13661 used_prefixes |= (prefixes & PREFIX_DATA);
13662 }
c0f3af97
L		 13663 break;
13664 case 0:
13665 return;
13666 default:
13667 oappend (INTERNAL_DISASSEMBLER_ERROR);
252b5132
RH		 13668 return;
13669 }
c0f3af97
L		 13670 oappend (names[reg]);
13671}
13672
13673static void
c1e679ec 13674OP_E_memory (int bytemode, int sizeflag)
c0f3af97
L		 13675{
13676 bfd_vma disp = 0;
13677 int add = (rex & REX_B) ? 8 : 0;
13678 int riprel = 0;
252b5132 13679
c0f3af97 13680 USED_REX (REX_B);
3f31e633
JB		 13681 if (intel_syntax)
13682 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 13683 append_seg ();
13684
5d669648 13685 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132 13686 {
5d669648
L		 13687 /* 32/64 bit address mode */
13688 int havedisp;
252b5132
RH		 13689 int havesib;
13690 int havebase;
0f7da397 13691 int haveindex;
20afcfb7 13692 int needindex;
82c18208 13693 int base, rbase;
91d6fa6a 13694 int vindex = 0;
252b5132
RH		 13695 int scale = 0;
13696
13697 havesib = 0;
13698 havebase = 1;
0f7da397 13699 haveindex = 0;
7967e09e 13700 base = modrm.rm;
252b5132
RH		 13701
13702 if (base == 4)
13703 {
13704 havesib = 1;
13705 FETCH_DATA (the_info, codep + 1);
91d6fa6a 13706 vindex = (*codep >> 3) & 7;
db51cc60 13707 scale = (*codep >> 6) & 3;
252b5132 13708 base = *codep & 7;
161a04f6
L		 13709 USED_REX (REX_X);
13710 if (rex & REX_X)
91d6fa6a
NC		 13711 vindex += 8;
13712 haveindex = vindex != 4;
252b5132
RH		 13713 codep++;
13714 }
82c18208 13715 rbase = base + add;
252b5132 13716
7967e09e 13717 switch (modrm.mod)
252b5132
RH		 13718 {
13719 case 0:
82c18208 13720 if (base == 5)
252b5132
RH		 13721 {
13722 havebase = 0;
cb712a9e 13723 if (address_mode == mode_64bit && !havesib)
52b15da3
JH		 13724 riprel = 1;
13725 disp = get32s ();
252b5132
RH		 13726 }
13727 break;
13728 case 1:
13729 FETCH_DATA (the_info, codep + 1);
13730 disp = *codep++;
13731 if ((disp & 0x80) != 0)
13732 disp -= 0x100;
13733 break;
13734 case 2:
52b15da3 13735 disp = get32s ();
252b5132
RH		 13736 break;
13737 }
13738
20afcfb7
L		 13739 /* In 32bit mode, we need index register to tell [offset] from
13740 [eiz*1 + offset]. */
13741 needindex = (havesib
13742 && !havebase
13743 && !haveindex
13744 && address_mode == mode_32bit);
13745 havedisp = (havebase
13746 || needindex
13747 || (havesib && (haveindex || scale != 0)));
5d669648 13748
252b5132 13749 if (!intel_syntax)
82c18208 13750 if (modrm.mod != 0 || base == 5)
db6eb5be 13751 {
5d669648
L		 13752 if (havedisp || riprel)
13753 print_displacement (scratchbuf, disp);
13754 else
13755 print_operand_value (scratchbuf, 1, disp);
db6eb5be 13756 oappend (scratchbuf);
52b15da3
JH		 13757 if (riprel)
13758 {
13759 set_op (disp, 1);
87767711 13760 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
52b15da3 13761 }
db6eb5be 13762 }
2da11e11 13763
87767711
JB		 13764 if (havebase || haveindex || riprel)
13765 used_prefixes |= PREFIX_ADDR;
13766
5d669648 13767 if (havedisp || (intel_syntax && riprel))
252b5132 13768 {
252b5132 13769 *obufp++ = open_char;
52b15da3 13770 if (intel_syntax && riprel)
185b1163
L		 13771 {
13772 set_op (disp, 1);
87767711 13773 oappend (sizeflag & AFLAG ? "rip" : "eip");
185b1163 13774 }
db6eb5be 13775 *obufp = '\0';
252b5132 13776 if (havebase)
cb712a9e 13777 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
82c18208 13778 ? names64[rbase] : names32[rbase]);
252b5132
RH		 13779 if (havesib)
13780 {
db51cc60
L		 13781 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
13782 print index to tell base + index from base. */
13783 if (scale != 0
20afcfb7 13784 || needindex
db51cc60
L		 13785 || haveindex
13786 || (havebase && base != ESP_REG_NUM))
252b5132 13787 {
9306ca4a 13788 if (!intel_syntax || havebase)
db6eb5be 13789 {
9306ca4a
JB		 13790 *obufp++ = separator_char;
13791 *obufp = '\0';
db6eb5be 13792 }
db51cc60
L		 13793 if (haveindex)
13794 oappend (address_mode == mode_64bit
13795 && (sizeflag & AFLAG)
91d6fa6a 13796 ? names64[vindex] : names32[vindex]);
db51cc60
L		 13797 else
13798 oappend (address_mode == mode_64bit
13799 && (sizeflag & AFLAG)
13800 ? index64 : index32);
13801
db6eb5be
AM		 13802 *obufp++ = scale_char;
13803 *obufp = '\0';
13804 sprintf (scratchbuf, "%d", 1 << scale);
13805 oappend (scratchbuf);
13806 }
252b5132 13807 }
185b1163 13808 if (intel_syntax
82c18208 13809 && (disp || modrm.mod != 0 || base == 5))
3d456fa1 13810 {
db51cc60 13811 if (!havedisp || (bfd_signed_vma) disp >= 0)
3d456fa1
JB		 13812 {
13813 *obufp++ = '+';
13814 *obufp = '\0';
13815 }
05203043 13816 else if (modrm.mod != 1 && disp != -disp)
3d456fa1
JB		 13817 {
13818 *obufp++ = '-';
13819 *obufp = '\0';
13820 disp = - (bfd_signed_vma) disp;
13821 }
13822
db51cc60
L		 13823 if (havedisp)
13824 print_displacement (scratchbuf, disp);
13825 else
13826 print_operand_value (scratchbuf, 1, disp);
3d456fa1
JB		 13827 oappend (scratchbuf);
13828 }
252b5132
RH		 13829
13830 *obufp++ = close_char;
db6eb5be 13831 *obufp = '\0';
252b5132
RH		 13832 }
13833 else if (intel_syntax)
db6eb5be 13834 {
82c18208 13835 if (modrm.mod != 0 || base == 5)
db6eb5be 13836 {
252b5132
RH		 13837 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13838 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13839 ;
13840 else
13841 {
d708bcba 13842 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 13843 oappend (":");
13844 }
52b15da3 13845 print_operand_value (scratchbuf, 1, disp);
db6eb5be
AM		 13846 oappend (scratchbuf);
13847 }
13848 }
252b5132
RH		 13849 }
13850 else
f16cd0d5
L		 13851 {
13852 /* 16 bit address mode */
13853 used_prefixes |= prefixes & PREFIX_ADDR;
7967e09e 13854 switch (modrm.mod)
252b5132
RH		 13855 {
13856 case 0:
7967e09e 13857 if (modrm.rm == 6)
252b5132
RH		 13858 {
13859 disp = get16 ();
13860 if ((disp & 0x8000) != 0)
13861 disp -= 0x10000;
13862 }
13863 break;
13864 case 1:
13865 FETCH_DATA (the_info, codep + 1);
13866 disp = *codep++;
13867 if ((disp & 0x80) != 0)
13868 disp -= 0x100;
13869 break;
13870 case 2:
13871 disp = get16 ();
13872 if ((disp & 0x8000) != 0)
13873 disp -= 0x10000;
13874 break;
13875 }
13876
13877 if (!intel_syntax)
7967e09e 13878 if (modrm.mod != 0 || modrm.rm == 6)
db6eb5be 13879 {
5d669648 13880 print_displacement (scratchbuf, disp);
db6eb5be
AM		 13881 oappend (scratchbuf);
13882 }
252b5132 13883
7967e09e 13884 if (modrm.mod != 0 || modrm.rm != 6)
252b5132
RH		 13885 {
13886 *obufp++ = open_char;
db6eb5be 13887 *obufp = '\0';
7967e09e 13888 oappend (index16[modrm.rm]);
5d669648
L		 13889 if (intel_syntax
13890 && (disp || modrm.mod != 0 || modrm.rm == 6))
3d456fa1 13891 {
5d669648 13892 if ((bfd_signed_vma) disp >= 0)
3d456fa1
JB		 13893 {
13894 *obufp++ = '+';
13895 *obufp = '\0';
13896 }
7967e09e 13897 else if (modrm.mod != 1)
3d456fa1
JB		 13898 {
13899 *obufp++ = '-';
13900 *obufp = '\0';
13901 disp = - (bfd_signed_vma) disp;
13902 }
13903
5d669648 13904 print_displacement (scratchbuf, disp);
3d456fa1
JB		 13905 oappend (scratchbuf);
13906 }
13907
db6eb5be
AM		 13908 *obufp++ = close_char;
13909 *obufp = '\0';
252b5132 13910 }
3d456fa1
JB		 13911 else if (intel_syntax)
13912 {
13913 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13914 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13915 ;
13916 else
13917 {
13918 oappend (names_seg[ds_reg - es_reg]);
13919 oappend (":");
13920 }
13921 print_operand_value (scratchbuf, 1, disp & 0xffff);
13922 oappend (scratchbuf);
13923 }
252b5132
RH		 13924 }
13925}
13926
c0f3af97 13927static void
8b3f93e7 13928OP_E (int bytemode, int sizeflag)
c0f3af97
L		 13929{
13930 /* Skip mod/rm byte. */
13931 MODRM_CHECK;
13932 codep++;
13933
13934 if (modrm.mod == 3)
13935 OP_E_register (bytemode, sizeflag);
13936 else
c1e679ec 13937 OP_E_memory (bytemode, sizeflag);
c0f3af97
L		 13938}
13939
252b5132 13940static void
26ca5450 13941OP_G (int bytemode, int sizeflag)
252b5132 13942{
52b15da3 13943 int add = 0;
161a04f6
L		 13944 USED_REX (REX_R);
13945 if (rex & REX_R)
52b15da3 13946 add += 8;
252b5132
RH		 13947 switch (bytemode)
13948 {
13949 case b_mode:
52b15da3
JH		 13950 USED_REX (0);
13951 if (rex)
7967e09e 13952 oappend (names8rex[modrm.reg + add]);
52b15da3 13953 else
7967e09e 13954 oappend (names8[modrm.reg + add]);
252b5132
RH		 13955 break;
13956 case w_mode:
7967e09e 13957 oappend (names16[modrm.reg + add]);
252b5132
RH		 13958 break;
13959 case d_mode:
7967e09e 13960 oappend (names32[modrm.reg + add]);
52b15da3
JH		 13961 break;
13962 case q_mode:
7967e09e 13963 oappend (names64[modrm.reg + add]);
252b5132
RH		 13964 break;
13965 case v_mode:
9306ca4a 13966 case dq_mode:
42903f7f
L		 13967 case dqb_mode:
13968 case dqd_mode:
9306ca4a 13969 case dqw_mode:
161a04f6
L		 13970 USED_REX (REX_W);
13971 if (rex & REX_W)
7967e09e 13972 oappend (names64[modrm.reg + add]);
252b5132 13973 else
f16cd0d5
L		 13974 {
13975 if ((sizeflag & DFLAG) || bytemode != v_mode)
13976 oappend (names32[modrm.reg + add]);
13977 else
13978 oappend (names16[modrm.reg + add]);
13979 used_prefixes |= (prefixes & PREFIX_DATA);
13980 }
252b5132 13981 break;
90700ea2 13982 case m_mode:
cb712a9e 13983 if (address_mode == mode_64bit)
7967e09e 13984 oappend (names64[modrm.reg + add]);
90700ea2 13985 else
7967e09e 13986 oappend (names32[modrm.reg + add]);
90700ea2 13987 break;
252b5132
RH		 13988 default:
13989 oappend (INTERNAL_DISASSEMBLER_ERROR);
13990 break;
13991 }
13992}
13993
52b15da3 13994static bfd_vma
26ca5450 13995get64 (void)
52b15da3 13996{
5dd0794d 13997 bfd_vma x;
52b15da3 13998#ifdef BFD64
5dd0794d
AM		 13999 unsigned int a;
14000 unsigned int b;
14001
52b15da3
JH		 14002 FETCH_DATA (the_info, codep + 8);
14003 a = *codep++ & 0xff;
14004 a |= (*codep++ & 0xff) << 8;
14005 a |= (*codep++ & 0xff) << 16;
14006 a |= (*codep++ & 0xff) << 24;
5dd0794d 14007 b = *codep++ & 0xff;
52b15da3
JH		 14008 b |= (*codep++ & 0xff) << 8;
14009 b |= (*codep++ & 0xff) << 16;
14010 b |= (*codep++ & 0xff) << 24;
14011 x = a + ((bfd_vma) b << 32);
14012#else
6608db57 14013 abort ();
5dd0794d 14014 x = 0;
52b15da3
JH		 14015#endif
14016 return x;
14017}
14018
14019static bfd_signed_vma
26ca5450 14020get32 (void)
252b5132 14021{
52b15da3 14022 bfd_signed_vma x = 0;
252b5132
RH		 14023
14024 FETCH_DATA (the_info, codep + 4);
52b15da3
JH		 14025 x = *codep++ & (bfd_signed_vma) 0xff;
14026 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14027 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14028 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14029 return x;
14030}
14031
14032static bfd_signed_vma
26ca5450 14033get32s (void)
52b15da3
JH		 14034{
14035 bfd_signed_vma x = 0;
14036
14037 FETCH_DATA (the_info, codep + 4);
14038 x = *codep++ & (bfd_signed_vma) 0xff;
14039 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14040 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14041 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14042
14043 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14044
252b5132
RH		 14045 return x;
14046}
14047
14048static int
26ca5450 14049get16 (void)
252b5132
RH		 14050{
14051 int x = 0;
14052
14053 FETCH_DATA (the_info, codep + 2);
14054 x = *codep++ & 0xff;
14055 x |= (*codep++ & 0xff) << 8;
14056 return x;
14057}
14058
14059static void
26ca5450 14060set_op (bfd_vma op, int riprel)
252b5132
RH		 14061{
14062 op_index[op_ad] = op_ad;
cb712a9e 14063 if (address_mode == mode_64bit)
7081ff04
AJ		 14064 {
14065 op_address[op_ad] = op;
14066 op_riprel[op_ad] = riprel;
14067 }
14068 else
14069 {
14070 /* Mask to get a 32-bit address. */
14071 op_address[op_ad] = op & 0xffffffff;
14072 op_riprel[op_ad] = riprel & 0xffffffff;
14073 }
252b5132
RH		 14074}
14075
14076static void
26ca5450 14077OP_REG (int code, int sizeflag)
252b5132 14078{
2da11e11 14079 const char *s;
9b60702d 14080 int add;
161a04f6
L		 14081 USED_REX (REX_B);
14082 if (rex & REX_B)
52b15da3 14083 add = 8;
9b60702d
L		 14084 else
14085 add = 0;
52b15da3
JH		 14086
14087 switch (code)
14088 {
52b15da3
JH		 14089 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14090 case sp_reg: case bp_reg: case si_reg: case di_reg:
14091 s = names16[code - ax_reg + add];
14092 break;
14093 case es_reg: case ss_reg: case cs_reg:
14094 case ds_reg: case fs_reg: case gs_reg:
14095 s = names_seg[code - es_reg + add];
14096 break;
14097 case al_reg: case ah_reg: case cl_reg: case ch_reg:
14098 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14099 USED_REX (0);
14100 if (rex)
14101 s = names8rex[code - al_reg + add];
14102 else
14103 s = names8[code - al_reg];
14104 break;
6439fc28
AM		 14105 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14106 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
cb712a9e 14107 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 14108 {
14109 s = names64[code - rAX_reg + add];
14110 break;
14111 }
14112 code += eAX_reg - rAX_reg;
6608db57 14113 /* Fall through. */
52b15da3
JH		 14114 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14115 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 14116 USED_REX (REX_W);
14117 if (rex & REX_W)
52b15da3 14118 s = names64[code - eAX_reg + add];
52b15da3 14119 else
f16cd0d5
L		 14120 {
14121 if (sizeflag & DFLAG)
14122 s = names32[code - eAX_reg + add];
14123 else
14124 s = names16[code - eAX_reg + add];
14125 used_prefixes |= (prefixes & PREFIX_DATA);
14126 }
52b15da3 14127 break;
52b15da3
JH		 14128 default:
14129 s = INTERNAL_DISASSEMBLER_ERROR;
14130 break;
14131 }
14132 oappend (s);
14133}
14134
14135static void
26ca5450 14136OP_IMREG (int code, int sizeflag)
52b15da3
JH		 14137{
14138 const char *s;
252b5132
RH		 14139
14140 switch (code)
14141 {
14142 case indir_dx_reg:
d708bcba 14143 if (intel_syntax)
52fd6d94 14144 s = "dx";
d708bcba 14145 else
db6eb5be 14146 s = "(%dx)";
252b5132
RH		 14147 break;
14148 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14149 case sp_reg: case bp_reg: case si_reg: case di_reg:
14150 s = names16[code - ax_reg];
14151 break;
14152 case es_reg: case ss_reg: case cs_reg:
14153 case ds_reg: case fs_reg: case gs_reg:
14154 s = names_seg[code - es_reg];
14155 break;
14156 case al_reg: case ah_reg: case cl_reg: case ch_reg:
14157 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
52b15da3
JH		 14158 USED_REX (0);
14159 if (rex)
14160 s = names8rex[code - al_reg];
14161 else
14162 s = names8[code - al_reg];
252b5132
RH		 14163 break;
14164 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14165 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 14166 USED_REX (REX_W);
14167 if (rex & REX_W)
52b15da3 14168 s = names64[code - eAX_reg];
252b5132 14169 else
f16cd0d5
L		 14170 {
14171 if (sizeflag & DFLAG)
14172 s = names32[code - eAX_reg];
14173 else
14174 s = names16[code - eAX_reg];
14175 used_prefixes |= (prefixes & PREFIX_DATA);
14176 }
252b5132 14177 break;
52fd6d94 14178 case z_mode_ax_reg:
161a04f6 14179 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 14180 s = *names32;
14181 else
14182 s = *names16;
161a04f6 14183 if (!(rex & REX_W))
52fd6d94
JB		 14184 used_prefixes |= (prefixes & PREFIX_DATA);
14185 break;
252b5132
RH		 14186 default:
14187 s = INTERNAL_DISASSEMBLER_ERROR;
14188 break;
14189 }
14190 oappend (s);
14191}
14192
14193static void
26ca5450 14194OP_I (int bytemode, int sizeflag)
252b5132 14195{
52b15da3
JH		 14196 bfd_signed_vma op;
14197 bfd_signed_vma mask = -1;
252b5132
RH		 14198
14199 switch (bytemode)
14200 {
14201 case b_mode:
14202 FETCH_DATA (the_info, codep + 1);
52b15da3
JH		 14203 op = *codep++;
14204 mask = 0xff;
14205 break;
14206 case q_mode:
cb712a9e 14207 if (address_mode == mode_64bit)
6439fc28
AM		 14208 {
14209 op = get32s ();
14210 break;
14211 }
6608db57 14212 /* Fall through. */
252b5132 14213 case v_mode:
161a04f6
L		 14214 USED_REX (REX_W);
14215 if (rex & REX_W)
52b15da3 14216 op = get32s ();
252b5132 14217 else
52b15da3 14218 {
f16cd0d5
L		 14219 if (sizeflag & DFLAG)
14220 {
14221 op = get32 ();
14222 mask = 0xffffffff;
14223 }
14224 else
14225 {
14226 op = get16 ();
14227 mask = 0xfffff;
14228 }
14229 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 14230 }
252b5132
RH		 14231 break;
14232 case w_mode:
52b15da3 14233 mask = 0xfffff;
252b5132
RH		 14234 op = get16 ();
14235 break;
9306ca4a
JB		 14236 case const_1_mode:
14237 if (intel_syntax)
14238 oappend ("1");
14239 return;
252b5132
RH		 14240 default:
14241 oappend (INTERNAL_DISASSEMBLER_ERROR);
14242 return;
14243 }
14244
52b15da3
JH		 14245 op &= mask;
14246 scratchbuf[0] = '$';
d708bcba
AM		 14247 print_operand_value (scratchbuf + 1, 1, op);
14248 oappend (scratchbuf + intel_syntax);
52b15da3
JH		 14249 scratchbuf[0] = '\0';
14250}
14251
14252static void
26ca5450 14253OP_I64 (int bytemode, int sizeflag)
52b15da3
JH		 14254{
14255 bfd_signed_vma op;
14256 bfd_signed_vma mask = -1;
14257
cb712a9e 14258 if (address_mode != mode_64bit)
6439fc28
AM		 14259 {
14260 OP_I (bytemode, sizeflag);
14261 return;
14262 }
14263
52b15da3
JH		 14264 switch (bytemode)
14265 {
14266 case b_mode:
14267 FETCH_DATA (the_info, codep + 1);
14268 op = *codep++;
14269 mask = 0xff;
14270 break;
14271 case v_mode:
161a04f6
L		 14272 USED_REX (REX_W);
14273 if (rex & REX_W)
52b15da3 14274 op = get64 ();
52b15da3
JH		 14275 else
14276 {
f16cd0d5
L		 14277 if (sizeflag & DFLAG)
14278 {
14279 op = get32 ();
14280 mask = 0xffffffff;
14281 }
14282 else
14283 {
14284 op = get16 ();
14285 mask = 0xfffff;
14286 }
14287 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 14288 }
52b15da3
JH		 14289 break;
14290 case w_mode:
14291 mask = 0xfffff;
14292 op = get16 ();
14293 break;
14294 default:
14295 oappend (INTERNAL_DISASSEMBLER_ERROR);
14296 return;
14297 }
14298
14299 op &= mask;
14300 scratchbuf[0] = '$';
d708bcba
AM		 14301 print_operand_value (scratchbuf + 1, 1, op);
14302 oappend (scratchbuf + intel_syntax);
252b5132
RH		 14303 scratchbuf[0] = '\0';
14304}
14305
14306static void
26ca5450 14307OP_sI (int bytemode, int sizeflag)
252b5132 14308{
52b15da3
JH		 14309 bfd_signed_vma op;
14310 bfd_signed_vma mask = -1;
252b5132
RH		 14311
14312 switch (bytemode)
14313 {
14314 case b_mode:
14315 FETCH_DATA (the_info, codep + 1);
14316 op = *codep++;
14317 if ((op & 0x80) != 0)
14318 op -= 0x100;
52b15da3 14319 mask = 0xffffffff;
252b5132
RH		 14320 break;
14321 case v_mode:
161a04f6
L		 14322 USED_REX (REX_W);
14323 if (rex & REX_W)
52b15da3 14324 op = get32s ();
252b5132
RH		 14325 else
14326 {
f16cd0d5
L		 14327 if (sizeflag & DFLAG)
14328 {
14329 op = get32s ();
14330 mask = 0xffffffff;
14331 }
14332 else
14333 {
14334 mask = 0xffffffff;
14335 op = get16 ();
14336 if ((op & 0x8000) != 0)
14337 op -= 0x10000;
14338 }
14339 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 14340 }
14341 break;
14342 case w_mode:
14343 op = get16 ();
52b15da3 14344 mask = 0xffffffff;
252b5132
RH		 14345 if ((op & 0x8000) != 0)
14346 op -= 0x10000;
14347 break;
14348 default:
14349 oappend (INTERNAL_DISASSEMBLER_ERROR);
14350 return;
14351 }
52b15da3
JH		 14352
14353 scratchbuf[0] = '$';
14354 print_operand_value (scratchbuf + 1, 1, op);
d708bcba 14355 oappend (scratchbuf + intel_syntax);
252b5132
RH		 14356}
14357
14358static void
26ca5450 14359OP_J (int bytemode, int sizeflag)
252b5132 14360{
52b15da3 14361 bfd_vma disp;
7081ff04 14362 bfd_vma mask = -1;
65ca155d 14363 bfd_vma segment = 0;
252b5132
RH		 14364
14365 switch (bytemode)
14366 {
14367 case b_mode:
14368 FETCH_DATA (the_info, codep + 1);
14369 disp = *codep++;
14370 if ((disp & 0x80) != 0)
14371 disp -= 0x100;
14372 break;
14373 case v_mode:
f16cd0d5 14374 USED_REX (REX_W);
161a04f6 14375 if ((sizeflag & DFLAG) || (rex & REX_W))
52b15da3 14376 disp = get32s ();
252b5132
RH		 14377 else
14378 {
14379 disp = get16 ();
206717e8
L		 14380 if ((disp & 0x8000) != 0)
14381 disp -= 0x10000;
65ca155d
L		 14382 /* In 16bit mode, address is wrapped around at 64k within
14383 the same segment. Otherwise, a data16 prefix on a jump
14384 instruction means that the pc is masked to 16 bits after
14385 the displacement is added! */
14386 mask = 0xffff;
14387 if ((prefixes & PREFIX_DATA) == 0)
14388 segment = ((start_pc + codep - start_codep)
14389 & ~((bfd_vma) 0xffff));
252b5132 14390 }
f16cd0d5
L		 14391 if (!(rex & REX_W))
14392 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 14393 break;
14394 default:
14395 oappend (INTERNAL_DISASSEMBLER_ERROR);
14396 return;
14397 }
65ca155d 14398 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
52b15da3
JH		 14399 set_op (disp, 0);
14400 print_operand_value (scratchbuf, 1, disp);
252b5132
RH		 14401 oappend (scratchbuf);
14402}
14403
252b5132 14404static void
ed7841b3 14405OP_SEG (int bytemode, int sizeflag)
252b5132 14406{
ed7841b3 14407 if (bytemode == w_mode)
7967e09e 14408 oappend (names_seg[modrm.reg]);
ed7841b3 14409 else
7967e09e 14410 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
252b5132
RH		 14411}
14412
14413static void
26ca5450 14414OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
252b5132
RH		 14415{
14416 int seg, offset;
14417
c608c12e 14418 if (sizeflag & DFLAG)
252b5132 14419 {
c608c12e
AM		 14420 offset = get32 ();
14421 seg = get16 ();
252b5132 14422 }
c608c12e
AM		 14423 else
14424 {
14425 offset = get16 ();
14426 seg = get16 ();
14427 }
7d421014 14428 used_prefixes |= (prefixes & PREFIX_DATA);
d708bcba 14429 if (intel_syntax)
3f31e633 14430 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
d708bcba
AM		 14431 else
14432 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
c608c12e 14433 oappend (scratchbuf);
252b5132
RH		 14434}
14435
252b5132 14436static void
3f31e633 14437OP_OFF (int bytemode, int sizeflag)
252b5132 14438{
52b15da3 14439 bfd_vma off;
252b5132 14440
3f31e633
JB		 14441 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14442 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 14443 append_seg ();
14444
cb712a9e 14445 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132
RH		 14446 off = get32 ();
14447 else
14448 off = get16 ();
14449
14450 if (intel_syntax)
14451 {
14452 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 14453 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
252b5132 14454 {
d708bcba 14455 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 14456 oappend (":");
14457 }
14458 }
52b15da3
JH		 14459 print_operand_value (scratchbuf, 1, off);
14460 oappend (scratchbuf);
14461}
6439fc28 14462
52b15da3 14463static void
3f31e633 14464OP_OFF64 (int bytemode, int sizeflag)
52b15da3
JH		 14465{
14466 bfd_vma off;
14467
539e75ad
L		 14468 if (address_mode != mode_64bit
14469 || (prefixes & PREFIX_ADDR))
6439fc28
AM		 14470 {
14471 OP_OFF (bytemode, sizeflag);
14472 return;
14473 }
14474
3f31e633
JB		 14475 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14476 intel_operand_size (bytemode, sizeflag);
52b15da3
JH		 14477 append_seg ();
14478
6608db57 14479 off = get64 ();
52b15da3
JH		 14480
14481 if (intel_syntax)
14482 {
14483 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 14484 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
52b15da3 14485 {
d708bcba 14486 oappend (names_seg[ds_reg - es_reg]);
52b15da3
JH		 14487 oappend (":");
14488 }
14489 }
14490 print_operand_value (scratchbuf, 1, off);
252b5132
RH		 14491 oappend (scratchbuf);
14492}
14493
14494static void
26ca5450 14495ptr_reg (int code, int sizeflag)
252b5132 14496{
2da11e11 14497 const char *s;
d708bcba 14498
1d9f512f 14499 *obufp++ = open_char;
20f0a1fc 14500 used_prefixes |= (prefixes & PREFIX_ADDR);
cb712a9e 14501 if (address_mode == mode_64bit)
c1a64871
JH		 14502 {
14503 if (!(sizeflag & AFLAG))
db6eb5be 14504 s = names32[code - eAX_reg];
c1a64871 14505 else
db6eb5be 14506 s = names64[code - eAX_reg];
c1a64871 14507 }
52b15da3 14508 else if (sizeflag & AFLAG)
252b5132
RH		 14509 s = names32[code - eAX_reg];
14510 else
14511 s = names16[code - eAX_reg];
14512 oappend (s);
1d9f512f
AM		 14513 *obufp++ = close_char;
14514 *obufp = 0;
252b5132
RH		 14515}
14516
14517static void
26ca5450 14518OP_ESreg (int code, int sizeflag)
252b5132 14519{
9306ca4a 14520 if (intel_syntax)
52fd6d94
JB		 14521 {
14522 switch (codep[-1])
14523 {
14524 case 0x6d: /* insw/insl */
14525 intel_operand_size (z_mode, sizeflag);
14526 break;
14527 case 0xa5: /* movsw/movsl/movsq */
14528 case 0xa7: /* cmpsw/cmpsl/cmpsq */
14529 case 0xab: /* stosw/stosl */
14530 case 0xaf: /* scasw/scasl */
14531 intel_operand_size (v_mode, sizeflag);
14532 break;
14533 default:
14534 intel_operand_size (b_mode, sizeflag);
14535 }
14536 }
d708bcba 14537 oappend ("%es:" + intel_syntax);
252b5132
RH		 14538 ptr_reg (code, sizeflag);
14539}
14540
14541static void
26ca5450 14542OP_DSreg (int code, int sizeflag)
252b5132 14543{
9306ca4a 14544 if (intel_syntax)
52fd6d94
JB		 14545 {
14546 switch (codep[-1])
14547 {
14548 case 0x6f: /* outsw/outsl */
14549 intel_operand_size (z_mode, sizeflag);
14550 break;
14551 case 0xa5: /* movsw/movsl/movsq */
14552 case 0xa7: /* cmpsw/cmpsl/cmpsq */
14553 case 0xad: /* lodsw/lodsl/lodsq */
14554 intel_operand_size (v_mode, sizeflag);
14555 break;
14556 default:
14557 intel_operand_size (b_mode, sizeflag);
14558 }
14559 }
252b5132
RH		 14560 if ((prefixes
14561 & (PREFIX_CS
14562 | PREFIX_DS
14563 | PREFIX_SS
14564 | PREFIX_ES
14565 | PREFIX_FS
14566 | PREFIX_GS)) == 0)
14567 prefixes |= PREFIX_DS;
6608db57 14568 append_seg ();
252b5132
RH		 14569 ptr_reg (code, sizeflag);
14570}
14571
252b5132 14572static void
26ca5450 14573OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 14574{
9b60702d 14575 int add;
161a04f6 14576 if (rex & REX_R)
c4a530c5 14577 {
161a04f6 14578 USED_REX (REX_R);
c4a530c5
JB		 14579 add = 8;
14580 }
cb712a9e 14581 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
c4a530c5 14582 {
f16cd0d5 14583 all_prefixes[last_lock_prefix] = 0;
c4a530c5
JB		 14584 used_prefixes |= PREFIX_LOCK;
14585 add = 8;
14586 }
9b60702d
L		 14587 else
14588 add = 0;
7967e09e 14589 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
d708bcba 14590 oappend (scratchbuf + intel_syntax);
252b5132
RH		 14591}
14592
252b5132 14593static void
26ca5450 14594OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 14595{
9b60702d 14596 int add;
161a04f6
L		 14597 USED_REX (REX_R);
14598 if (rex & REX_R)
52b15da3 14599 add = 8;
9b60702d
L		 14600 else
14601 add = 0;
d708bcba 14602 if (intel_syntax)
7967e09e 14603 sprintf (scratchbuf, "db%d", modrm.reg + add);
d708bcba 14604 else
7967e09e 14605 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
252b5132
RH		 14606 oappend (scratchbuf);
14607}
14608
252b5132 14609static void
26ca5450 14610OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 14611{
7967e09e 14612 sprintf (scratchbuf, "%%tr%d", modrm.reg);
d708bcba 14613 oappend (scratchbuf + intel_syntax);
252b5132
RH		 14614}
14615
14616static void
6f74c397 14617OP_R (int bytemode, int sizeflag)
252b5132 14618{
7967e09e 14619 if (modrm.mod == 3)
2da11e11
AM		 14620 OP_E (bytemode, sizeflag);
14621 else
6608db57 14622 BadOp ();
252b5132
RH		 14623}
14624
14625static void
26ca5450 14626OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 14627{
041bd2e0
JH		 14628 used_prefixes |= (prefixes & PREFIX_DATA);
14629 if (prefixes & PREFIX_DATA)
20f0a1fc 14630 {
9b60702d 14631 int add;
161a04f6
L		 14632 USED_REX (REX_R);
14633 if (rex & REX_R)
20f0a1fc 14634 add = 8;
9b60702d
L		 14635 else
14636 add = 0;
7967e09e 14637 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
20f0a1fc 14638 }
041bd2e0 14639 else
7967e09e 14640 sprintf (scratchbuf, "%%mm%d", modrm.reg);
d708bcba 14641 oappend (scratchbuf + intel_syntax);
252b5132
RH		 14642}
14643
c608c12e 14644static void
c0f3af97 14645OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
c608c12e 14646{
9b60702d 14647 int add;
161a04f6
L		 14648 USED_REX (REX_R);
14649 if (rex & REX_R)
041bd2e0 14650 add = 8;
9b60702d
L		 14651 else
14652 add = 0;
c0f3af97
L		 14653 if (need_vex && bytemode != xmm_mode)
14654 {
14655 switch (vex.length)
14656 {
14657 case 128:
14658 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
14659 break;
14660 case 256:
14661 sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);
14662 break;
14663 default:
14664 abort ();
14665 }
14666 }
14667 else
14668 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
d708bcba 14669 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 14670}
14671
252b5132 14672static void
26ca5450 14673OP_EM (int bytemode, int sizeflag)
252b5132 14674{
7967e09e 14675 if (modrm.mod != 3)
252b5132 14676 {
b6169b20
L		 14677 if (intel_syntax
14678 && (bytemode == v_mode || bytemode == v_swap_mode))
9306ca4a
JB		 14679 {
14680 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14681 used_prefixes |= (prefixes & PREFIX_DATA);
14682 }
252b5132
RH		 14683 OP_E (bytemode, sizeflag);
14684 return;
14685 }
14686
b6169b20
L		 14687 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
14688 swap_operand ();
14689
6608db57 14690 /* Skip mod/rm byte. */
4bba6815 14691 MODRM_CHECK;
252b5132 14692 codep++;
041bd2e0
JH		 14693 used_prefixes |= (prefixes & PREFIX_DATA);
14694 if (prefixes & PREFIX_DATA)
20f0a1fc 14695 {
9b60702d 14696 int add;
20f0a1fc 14697
161a04f6
L		 14698 USED_REX (REX_B);
14699 if (rex & REX_B)
20f0a1fc 14700 add = 8;
9b60702d
L		 14701 else
14702 add = 0;
7967e09e 14703 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
20f0a1fc 14704 }
041bd2e0 14705 else
7967e09e 14706 sprintf (scratchbuf, "%%mm%d", modrm.rm);
d708bcba 14707 oappend (scratchbuf + intel_syntax);
252b5132
RH		 14708}
14709
246c51aa
L		 14710/* cvt* are the only instructions in sse2 which have
14711 both SSE and MMX operands and also have 0x66 prefix
14712 in their opcode. 0x66 was originally used to differentiate
14713 between SSE and MMX instruction(operands). So we have to handle the
4d9567e0
MM		 14714 cvt* separately using OP_EMC and OP_MXC */
14715static void
14716OP_EMC (int bytemode, int sizeflag)
14717{
7967e09e 14718 if (modrm.mod != 3)
4d9567e0
MM		 14719 {
14720 if (intel_syntax && bytemode == v_mode)
14721 {
14722 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14723 used_prefixes |= (prefixes & PREFIX_DATA);
14724 }
14725 OP_E (bytemode, sizeflag);
14726 return;
14727 }
246c51aa 14728
4d9567e0
MM		 14729 /* Skip mod/rm byte. */
14730 MODRM_CHECK;
14731 codep++;
14732 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 14733 sprintf (scratchbuf, "%%mm%d", modrm.rm);
4d9567e0
MM		 14734 oappend (scratchbuf + intel_syntax);
14735}
14736
14737static void
14738OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14739{
14740 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 14741 sprintf (scratchbuf, "%%mm%d", modrm.reg);
4d9567e0
MM		 14742 oappend (scratchbuf + intel_syntax);
14743}
14744
c608c12e 14745static void
26ca5450 14746OP_EX (int bytemode, int sizeflag)
c608c12e 14747{
9b60702d 14748 int add;
d6f574e0
L		 14749
14750 /* Skip mod/rm byte. */
14751 MODRM_CHECK;
14752 codep++;
14753
7967e09e 14754 if (modrm.mod != 3)
c608c12e 14755 {
c1e679ec 14756 OP_E_memory (bytemode, sizeflag);
c608c12e
AM		 14757 return;
14758 }
d6f574e0 14759
161a04f6
L		 14760 USED_REX (REX_B);
14761 if (rex & REX_B)
041bd2e0 14762 add = 8;
9b60702d
L		 14763 else
14764 add = 0;
c608c12e 14765
b6169b20 14766 if ((sizeflag & SUFFIX_ALWAYS)
fa99fab2
L		 14767 && (bytemode == x_swap_mode
14768 || bytemode == d_swap_mode
14769 || bytemode == q_swap_mode))
b6169b20
L		 14770 swap_operand ();
14771
c0f3af97
L		 14772 if (need_vex
14773 && bytemode != xmm_mode
14774 && bytemode != xmmq_mode)
14775 {
14776 switch (vex.length)
14777 {
14778 case 128:
14779 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
14780 break;
14781 case 256:
14782 sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);
14783 break;
14784 default:
14785 abort ();
14786 }
14787 }
14788 else
14789 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
d708bcba 14790 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 14791}
14792
252b5132 14793static void
26ca5450 14794OP_MS (int bytemode, int sizeflag)
252b5132 14795{
7967e09e 14796 if (modrm.mod == 3)
2da11e11
AM		 14797 OP_EM (bytemode, sizeflag);
14798 else
6608db57 14799 BadOp ();
252b5132
RH		 14800}
14801
992aaec9 14802static void
26ca5450 14803OP_XS (int bytemode, int sizeflag)
992aaec9 14804{
7967e09e 14805 if (modrm.mod == 3)
992aaec9
AM		 14806 OP_EX (bytemode, sizeflag);
14807 else
6608db57 14808 BadOp ();
992aaec9
AM		 14809}
14810
cc0ec051
AM		 14811static void
14812OP_M (int bytemode, int sizeflag)
14813{
7967e09e 14814 if (modrm.mod == 3)
75413a22
L		 14815 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14816 BadOp ();
cc0ec051
AM		 14817 else
14818 OP_E (bytemode, sizeflag);
14819}
14820
14821static void
14822OP_0f07 (int bytemode, int sizeflag)
14823{
7967e09e 14824 if (modrm.mod != 3 || modrm.rm != 0)
cc0ec051
AM		 14825 BadOp ();
14826 else
14827 OP_E (bytemode, sizeflag);
14828}
14829
46e883c5 14830/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
246c51aa 14831 32bit mode and "xchg %rax,%rax" in 64bit mode. */
46e883c5 14832
cc0ec051 14833static void
46e883c5 14834NOP_Fixup1 (int bytemode, int sizeflag)
cc0ec051 14835{
8b38ad71
L		 14836 if ((prefixes & PREFIX_DATA) != 0
14837 || (rex != 0
14838 && rex != 0x48
14839 && address_mode == mode_64bit))
46e883c5
L		 14840 OP_REG (bytemode, sizeflag);
14841 else
14842 strcpy (obuf, "nop");
14843}
14844
14845static void
14846NOP_Fixup2 (int bytemode, int sizeflag)
14847{
8b38ad71
L		 14848 if ((prefixes & PREFIX_DATA) != 0
14849 || (rex != 0
14850 && rex != 0x48
14851 && address_mode == mode_64bit))
46e883c5 14852 OP_IMREG (bytemode, sizeflag);
cc0ec051
AM		 14853}
14854
84037f8c 14855static const char *const Suffix3DNow[] = {
252b5132
RH		 14856/* 00 */ NULL, NULL, NULL, NULL,
14857/* 04 */ NULL, NULL, NULL, NULL,
14858/* 08 */ NULL, NULL, NULL, NULL,
9e525108 14859/* 0C */ "pi2fw", "pi2fd", NULL, NULL,
252b5132
RH		 14860/* 10 */ NULL, NULL, NULL, NULL,
14861/* 14 */ NULL, NULL, NULL, NULL,
14862/* 18 */ NULL, NULL, NULL, NULL,
9e525108 14863/* 1C */ "pf2iw", "pf2id", NULL, NULL,
252b5132
RH		 14864/* 20 */ NULL, NULL, NULL, NULL,
14865/* 24 */ NULL, NULL, NULL, NULL,
14866/* 28 */ NULL, NULL, NULL, NULL,
14867/* 2C */ NULL, NULL, NULL, NULL,
14868/* 30 */ NULL, NULL, NULL, NULL,
14869/* 34 */ NULL, NULL, NULL, NULL,
14870/* 38 */ NULL, NULL, NULL, NULL,
14871/* 3C */ NULL, NULL, NULL, NULL,
14872/* 40 */ NULL, NULL, NULL, NULL,
14873/* 44 */ NULL, NULL, NULL, NULL,
14874/* 48 */ NULL, NULL, NULL, NULL,
14875/* 4C */ NULL, NULL, NULL, NULL,
14876/* 50 */ NULL, NULL, NULL, NULL,
14877/* 54 */ NULL, NULL, NULL, NULL,
14878/* 58 */ NULL, NULL, NULL, NULL,
14879/* 5C */ NULL, NULL, NULL, NULL,
14880/* 60 */ NULL, NULL, NULL, NULL,
14881/* 64 */ NULL, NULL, NULL, NULL,
14882/* 68 */ NULL, NULL, NULL, NULL,
14883/* 6C */ NULL, NULL, NULL, NULL,
14884/* 70 */ NULL, NULL, NULL, NULL,
14885/* 74 */ NULL, NULL, NULL, NULL,
14886/* 78 */ NULL, NULL, NULL, NULL,
14887/* 7C */ NULL, NULL, NULL, NULL,
14888/* 80 */ NULL, NULL, NULL, NULL,
14889/* 84 */ NULL, NULL, NULL, NULL,
9e525108
AM		 14890/* 88 */ NULL, NULL, "pfnacc", NULL,
14891/* 8C */ NULL, NULL, "pfpnacc", NULL,
252b5132
RH		 14892/* 90 */ "pfcmpge", NULL, NULL, NULL,
14893/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
14894/* 98 */ NULL, NULL, "pfsub", NULL,
14895/* 9C */ NULL, NULL, "pfadd", NULL,
14896/* A0 */ "pfcmpgt", NULL, NULL, NULL,
14897/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
14898/* A8 */ NULL, NULL, "pfsubr", NULL,
14899/* AC */ NULL, NULL, "pfacc", NULL,
14900/* B0 */ "pfcmpeq", NULL, NULL, NULL,
9beff690 14901/* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
9e525108 14902/* B8 */ NULL, NULL, NULL, "pswapd",
252b5132
RH		 14903/* BC */ NULL, NULL, NULL, "pavgusb",
14904/* C0 */ NULL, NULL, NULL, NULL,
14905/* C4 */ NULL, NULL, NULL, NULL,
14906/* C8 */ NULL, NULL, NULL, NULL,
14907/* CC */ NULL, NULL, NULL, NULL,
14908/* D0 */ NULL, NULL, NULL, NULL,
14909/* D4 */ NULL, NULL, NULL, NULL,
14910/* D8 */ NULL, NULL, NULL, NULL,
14911/* DC */ NULL, NULL, NULL, NULL,
14912/* E0 */ NULL, NULL, NULL, NULL,
14913/* E4 */ NULL, NULL, NULL, NULL,
14914/* E8 */ NULL, NULL, NULL, NULL,
14915/* EC */ NULL, NULL, NULL, NULL,
14916/* F0 */ NULL, NULL, NULL, NULL,
14917/* F4 */ NULL, NULL, NULL, NULL,
14918/* F8 */ NULL, NULL, NULL, NULL,
14919/* FC */ NULL, NULL, NULL, NULL,
14920};
14921
14922static void
26ca5450 14923OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132
RH		 14924{
14925 const char *mnemonic;
14926
14927 FETCH_DATA (the_info, codep + 1);
14928 /* AMD 3DNow! instructions are specified by an opcode suffix in the
14929 place where an 8-bit immediate would normally go. ie. the last
14930 byte of the instruction. */
ea397f5b 14931 obufp = mnemonicendp;
c608c12e 14932 mnemonic = Suffix3DNow[*codep++ & 0xff];
252b5132 14933 if (mnemonic)
2da11e11 14934 oappend (mnemonic);
252b5132
RH		 14935 else
14936 {
14937 /* Since a variable sized modrm/sib chunk is between the start
14938 of the opcode (0x0f0f) and the opcode suffix, we need to do
14939 all the modrm processing first, and don't know until now that
14940 we have a bad opcode. This necessitates some cleaning up. */
ce518a5f
L		 14941 op_out[0][0] = '\0';
14942 op_out[1][0] = '\0';
6608db57 14943 BadOp ();
252b5132 14944 }
ea397f5b 14945 mnemonicendp = obufp;
252b5132 14946}
c608c12e 14947
ea397f5b
L		 14948static struct op simd_cmp_op[] =
14949{
14950 { STRING_COMMA_LEN ("eq") },
14951 { STRING_COMMA_LEN ("lt") },
14952 { STRING_COMMA_LEN ("le") },
14953 { STRING_COMMA_LEN ("unord") },
14954 { STRING_COMMA_LEN ("neq") },
14955 { STRING_COMMA_LEN ("nlt") },
14956 { STRING_COMMA_LEN ("nle") },
14957 { STRING_COMMA_LEN ("ord") }
c608c12e
AM		 14958};
14959
14960static void
ad19981d 14961CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e
AM		 14962{
14963 unsigned int cmp_type;
14964
14965 FETCH_DATA (the_info, codep + 1);
14966 cmp_type = *codep++ & 0xff;
c0f3af97 14967 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
c608c12e 14968 {
ad19981d 14969 char suffix [3];
ea397f5b 14970 char *p = mnemonicendp - 2;
ad19981d
L		 14971 suffix[0] = p[0];
14972 suffix[1] = p[1];
14973 suffix[2] = '\0';
ea397f5b
L		 14974 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14975 mnemonicendp += simd_cmp_op[cmp_type].len;
c608c12e
AM		 14976 }
14977 else
14978 {
ad19981d
L		 14979 /* We have a reserved extension byte. Output it directly. */
14980 scratchbuf[0] = '$';
14981 print_operand_value (scratchbuf + 1, 1, cmp_type);
14982 oappend (scratchbuf + intel_syntax);
14983 scratchbuf[0] = '\0';
c608c12e
AM		 14984 }
14985}
14986
ca164297 14987static void
b844680a
L		 14988OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
14989 int sizeflag ATTRIBUTE_UNUSED)
14990{
14991 /* mwait %eax,%ecx */
14992 if (!intel_syntax)
14993 {
14994 const char **names = (address_mode == mode_64bit
14995 ? names64 : names32);
14996 strcpy (op_out[0], names[0]);
14997 strcpy (op_out[1], names[1]);
14998 two_source_ops = 1;
14999 }
15000 /* Skip mod/rm byte. */
15001 MODRM_CHECK;
15002 codep++;
15003}
15004
15005static void
15006OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15007 int sizeflag ATTRIBUTE_UNUSED)
ca164297 15008{
b844680a
L		 15009 /* monitor %eax,%ecx,%edx" */
15010 if (!intel_syntax)
ca164297 15011 {
b844680a 15012 const char **op1_names;
cb712a9e
L		 15013 const char **names = (address_mode == mode_64bit
15014 ? names64 : names32);
1d9f512f 15015
b844680a
L		 15016 if (!(prefixes & PREFIX_ADDR))
15017 op1_names = (address_mode == mode_16bit
15018 ? names16 : names);
ca164297
L		 15019 else
15020 {
b844680a 15021 /* Remove "addr16/addr32". */
f16cd0d5 15022 all_prefixes[last_addr_prefix] = 0;
b844680a
L		 15023 op1_names = (address_mode != mode_32bit
15024 ? names32 : names16);
15025 used_prefixes |= PREFIX_ADDR;
ca164297 15026 }
b844680a
L		 15027 strcpy (op_out[0], op1_names[0]);
15028 strcpy (op_out[1], names[1]);
15029 strcpy (op_out[2], names[2]);
15030 two_source_ops = 1;
ca164297 15031 }
b844680a
L		 15032 /* Skip mod/rm byte. */
15033 MODRM_CHECK;
15034 codep++;
30123838
JB		 15035}
15036
6608db57
KH		 15037static void
15038BadOp (void)
2da11e11 15039{
6608db57
KH		 15040 /* Throw away prefixes and 1st. opcode byte. */
15041 codep = insn_codep + 1;
2da11e11
AM		 15042 oappend ("(bad)");
15043}
4cc91dba 15044
35c52694
L		 15045static void
15046REP_Fixup (int bytemode, int sizeflag)
15047{
15048 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15049 lods and stos. */
35c52694 15050 if (prefixes & PREFIX_REPZ)
f16cd0d5 15051 all_prefixes[last_repz_prefix] = REP_PREFIX;
35c52694
L		 15052
15053 switch (bytemode)
15054 {
15055 case al_reg:
15056 case eAX_reg:
15057 case indir_dx_reg:
15058 OP_IMREG (bytemode, sizeflag);
15059 break;
15060 case eDI_reg:
15061 OP_ESreg (bytemode, sizeflag);
15062 break;
15063 case eSI_reg:
15064 OP_DSreg (bytemode, sizeflag);
15065 break;
15066 default:
15067 abort ();
15068 break;
15069 }
15070}
f5804c90
L		 15071
15072static void
15073CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15074{
161a04f6
L		 15075 USED_REX (REX_W);
15076 if (rex & REX_W)
f5804c90
L		 15077 {
15078 /* Change cmpxchg8b to cmpxchg16b. */
ea397f5b
L		 15079 char *p = mnemonicendp - 2;
15080 mnemonicendp = stpcpy (p, "16b");
fb9c77c7 15081 bytemode = o_mode;
f5804c90
L		 15082 }
15083 OP_M (bytemode, sizeflag);
15084}
42903f7f
L		 15085
15086static void
15087XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15088{
c0f3af97
L		 15089 if (need_vex)
15090 {
15091 switch (vex.length)
15092 {
15093 case 128:
15094 sprintf (scratchbuf, "%%xmm%d", reg);
15095 break;
15096 case 256:
15097 sprintf (scratchbuf, "%%ymm%d", reg);
15098 break;
15099 default:
15100 abort ();
15101 }
15102 }
15103 else
15104 sprintf (scratchbuf, "%%xmm%d", reg);
42903f7f
L		 15105 oappend (scratchbuf + intel_syntax);
15106}
381d071f
L		 15107
15108static void
15109CRC32_Fixup (int bytemode, int sizeflag)
15110{
15111 /* Add proper suffix to "crc32". */
ea397f5b 15112 char *p = mnemonicendp;
381d071f
L		 15113
15114 switch (bytemode)
15115 {
15116 case b_mode:
20592a94 15117 if (intel_syntax)
ea397f5b 15118 goto skip;
20592a94 15119
381d071f
L		 15120 *p++ = 'b';
15121 break;
15122 case v_mode:
20592a94 15123 if (intel_syntax)
ea397f5b 15124 goto skip;
20592a94 15125
381d071f
L		 15126 USED_REX (REX_W);
15127 if (rex & REX_W)
15128 *p++ = 'q';
f16cd0d5
L		 15129 else
15130 {
15131 if (sizeflag & DFLAG)
15132 *p++ = 'l';
15133 else
15134 *p++ = 'w';
15135 used_prefixes |= (prefixes & PREFIX_DATA);
15136 }
381d071f
L		 15137 break;
15138 default:
15139 oappend (INTERNAL_DISASSEMBLER_ERROR);
15140 break;
15141 }
ea397f5b 15142 mnemonicendp = p;
381d071f
L		 15143 *p = '\0';
15144
ea397f5b 15145skip:
381d071f
L		 15146 if (modrm.mod == 3)
15147 {
15148 int add;
15149
15150 /* Skip mod/rm byte. */
15151 MODRM_CHECK;
15152 codep++;
15153
15154 USED_REX (REX_B);
15155 add = (rex & REX_B) ? 8 : 0;
15156 if (bytemode == b_mode)
15157 {
15158 USED_REX (0);
15159 if (rex)
15160 oappend (names8rex[modrm.rm + add]);
15161 else
15162 oappend (names8[modrm.rm + add]);
15163 }
15164 else
15165 {
15166 USED_REX (REX_W);
15167 if (rex & REX_W)
15168 oappend (names64[modrm.rm + add]);
15169 else if ((prefixes & PREFIX_DATA))
15170 oappend (names16[modrm.rm + add]);
15171 else
15172 oappend (names32[modrm.rm + add]);
15173 }
15174 }
15175 else
9344ff29 15176 OP_E (bytemode, sizeflag);
381d071f 15177}
85f10a01 15178
eacc9c89
L		 15179static void
15180FXSAVE_Fixup (int bytemode, int sizeflag)
15181{
15182 /* Add proper suffix to "fxsave" and "fxrstor". */
15183 USED_REX (REX_W);
15184 if (rex & REX_W)
15185 {
15186 char *p = mnemonicendp;
15187 *p++ = '6';
15188 *p++ = '4';
15189 *p = '\0';
15190 mnemonicendp = p;
15191 }
15192 OP_M (bytemode, sizeflag);
15193}
15194
c0f3af97
L		 15195/* Display the destination register operand for instructions with
15196 VEX. */
15197
15198static void
15199OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15200{
15201 if (!need_vex)
15202 abort ();
15203
15204 if (!need_vex_reg)
15205 return;
15206
15207 switch (vex.length)
15208 {
15209 case 128:
15210 switch (bytemode)
15211 {
15212 case vex_mode:
15213 case vex128_mode:
15214 break;
15215 default:
15216 abort ();
15217 return;
15218 }
15219
15220 sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
15221 break;
15222 case 256:
15223 switch (bytemode)
15224 {
15225 case vex_mode:
15226 case vex256_mode:
15227 break;
15228 default:
15229 abort ();
15230 return;
15231 }
15232
15233 sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);
15234 break;
15235 default:
15236 abort ();
15237 break;
15238 }
15239 oappend (scratchbuf + intel_syntax);
15240}
15241
922d8de8
DR		 15242/* Get the VEX immediate byte without moving codep. */
15243
15244static unsigned char
ccc5981b 15245get_vex_imm8 (int sizeflag, int opnum)
922d8de8
DR		 15246{
15247 int bytes_before_imm = 0;
15248
922d8de8
DR		 15249 if (modrm.mod != 3)
15250 {
15251 /* There are SIB/displacement bytes. */
15252 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
02e647f9 15253 {
922d8de8 15254 /* 32/64 bit address mode */
02e647f9 15255 int base = modrm.rm;
922d8de8
DR		 15256
15257 /* Check SIB byte. */
02e647f9
SP		 15258 if (base == 4)
15259 {
15260 FETCH_DATA (the_info, codep + 1);
15261 base = *codep & 7;
15262 /* When decoding the third source, don't increase
15263 bytes_before_imm as this has already been incremented
15264 by one in OP_E_memory while decoding the second
15265 source operand. */
ccc5981b
SP		 15266 if (opnum == 0)
15267 bytes_before_imm++;
02e647f9
SP		 15268 }
15269
15270 /* Don't increase bytes_before_imm when decoding the third source,
15271 it has already been incremented by OP_E_memory while decoding
15272 the second source operand. */
15273 if (opnum == 0)
15274 {
15275 switch (modrm.mod)
15276 {
15277 case 0:
15278 /* When modrm.rm == 5 or modrm.rm == 4 and base in
15279 SIB == 5, there is a 4 byte displacement. */
15280 if (base != 5)
15281 /* No displacement. */
15282 break;
15283 case 2:
15284 /* 4 byte displacement. */
15285 bytes_before_imm += 4;
15286 break;
15287 case 1:
15288 /* 1 byte displacement. */
15289 bytes_before_imm++;
15290 break;
15291 }
15292 }
15293 }
922d8de8 15294 else
02e647f9
SP		 15295 {
15296 /* 16 bit address mode */
15297 /* Don't increase bytes_before_imm when decoding the third source,
15298 it has already been incremented by OP_E_memory while decoding
15299 the second source operand. */
15300 if (opnum == 0)
15301 {
15302 switch (modrm.mod)
15303 {
15304 case 0:
15305 /* When modrm.rm == 6, there is a 2 byte displacement. */
15306 if (modrm.rm != 6)
15307 /* No displacement. */
15308 break;
15309 case 2:
15310 /* 2 byte displacement. */
15311 bytes_before_imm += 2;
15312 break;
15313 case 1:
15314 /* 1 byte displacement: when decoding the third source,
15315 don't increase bytes_before_imm as this has already
15316 been incremented by one in OP_E_memory while decoding
15317 the second source operand. */
15318 if (opnum == 0)
15319 bytes_before_imm++;
ccc5981b 15320
02e647f9
SP		 15321 break;
15322 }
922d8de8
DR		 15323 }
15324 }
15325 }
15326
15327 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
15328 return codep [bytes_before_imm];
15329}
15330
15331static void
15332OP_EX_VexReg (int bytemode, int sizeflag, int reg)
15333{
15334 if (reg == -1 && modrm.mod != 3)
15335 {
15336 OP_E_memory (bytemode, sizeflag);
15337 return;
15338 }
15339 else
15340 {
15341 if (reg == -1)
15342 {
15343 reg = modrm.rm;
15344 USED_REX (REX_B);
15345 if (rex & REX_B)
15346 reg += 8;
15347 }
15348 else if (reg > 7 && address_mode != mode_64bit)
15349 BadOp ();
15350 }
15351
15352 switch (vex.length)
15353 {
15354 case 128:
15355 sprintf (scratchbuf, "%%xmm%d", reg);
15356 break;
15357 case 256:
15358 sprintf (scratchbuf, "%%ymm%d", reg);
15359 break;
15360 default:
15361 abort ();
15362 }
15363 oappend (scratchbuf + intel_syntax);
15364}
15365
5dd85c99
SP		 15366static void
15367OP_Vex_2src (int bytemode, int sizeflag)
15368{
15369 if (modrm.mod == 3)
15370 {
15371 USED_REX (REX_B);
15372 sprintf (scratchbuf, "%%xmm%d", rex & REX_B ? modrm.rm + 8 : modrm.rm);
15373 oappend (scratchbuf + intel_syntax);
15374 }
15375 else
15376 {
15377 if (intel_syntax
15378 && (bytemode == v_mode || bytemode == v_swap_mode))
15379 {
15380 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15381 used_prefixes |= (prefixes & PREFIX_DATA);
15382 }
15383 OP_E (bytemode, sizeflag);
15384 }
15385}
15386
15387static void
15388OP_Vex_2src_1 (int bytemode, int sizeflag)
15389{
15390 if (modrm.mod == 3)
15391 {
15392 /* Skip mod/rm byte. */
15393 MODRM_CHECK;
15394 codep++;
15395 }
15396
15397 if (vex.w)
15398 {
15399 sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
15400 oappend (scratchbuf + intel_syntax);
15401 }
15402 else
15403 OP_Vex_2src (bytemode, sizeflag);
15404}
15405
15406static void
15407OP_Vex_2src_2 (int bytemode, int sizeflag)
15408{
15409 if (vex.w)
15410 OP_Vex_2src (bytemode, sizeflag);
15411 else
15412 {
15413 sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
15414 oappend (scratchbuf + intel_syntax);
15415 }
15416}
15417
922d8de8
DR		 15418static void
15419OP_EX_VexW (int bytemode, int sizeflag)
15420{
15421 int reg = -1;
15422
15423 if (!vex_w_done)
15424 {
15425 vex_w_done = 1;
41effecb
SP		 15426
15427 /* Skip mod/rm byte. */
15428 MODRM_CHECK;
15429 codep++;
15430
922d8de8 15431 if (vex.w)
ccc5981b 15432 reg = get_vex_imm8 (sizeflag, 0) >> 4;
922d8de8
DR		 15433 }
15434 else
15435 {
15436 if (!vex.w)
ccc5981b 15437 reg = get_vex_imm8 (sizeflag, 1) >> 4;
922d8de8
DR		 15438 }
15439
15440 OP_EX_VexReg (bytemode, sizeflag, reg);
15441}
15442
922d8de8
DR		 15443static void
15444VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
15445 int sizeflag ATTRIBUTE_UNUSED)
15446{
15447 /* Skip the immediate byte and check for invalid bits. */
15448 FETCH_DATA (the_info, codep + 1);
15449 if (*codep++ & 0xf)
15450 BadOp ();
15451}
15452
c0f3af97
L		 15453static void
15454OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15455{
15456 int reg;
15457 FETCH_DATA (the_info, codep + 1);
15458 reg = *codep++;
15459
15460 if (bytemode != x_mode)
15461 abort ();
15462
15463 if (reg & 0xf)
15464 BadOp ();
15465
15466 reg >>= 4;
dae39acc
L		 15467 if (reg > 7 && address_mode != mode_64bit)
15468 BadOp ();
15469
c0f3af97
L		 15470 switch (vex.length)
15471 {
15472 case 128:
15473 sprintf (scratchbuf, "%%xmm%d", reg);
15474 break;
15475 case 256:
15476 sprintf (scratchbuf, "%%ymm%d", reg);
15477 break;
15478 default:
15479 abort ();
15480 }
15481 oappend (scratchbuf + intel_syntax);
15482}
15483
922d8de8
DR		 15484static void
15485OP_XMM_VexW (int bytemode, int sizeflag)
15486{
15487 /* Turn off the REX.W bit since it is used for swapping operands
15488 now. */
15489 rex &= ~REX_W;
15490 OP_XMM (bytemode, sizeflag);
15491}
15492
c0f3af97
L		 15493static void
15494OP_EX_Vex (int bytemode, int sizeflag)
15495{
15496 if (modrm.mod != 3)
15497 {
15498 if (vex.register_specifier != 0)
15499 BadOp ();
15500 need_vex_reg = 0;
15501 }
15502 OP_EX (bytemode, sizeflag);
15503}
15504
15505static void
15506OP_XMM_Vex (int bytemode, int sizeflag)
15507{
15508 if (modrm.mod != 3)
15509 {
15510 if (vex.register_specifier != 0)
15511 BadOp ();
15512 need_vex_reg = 0;
15513 }
15514 OP_XMM (bytemode, sizeflag);
15515}
15516
15517static void
15518VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15519{
15520 switch (vex.length)
15521 {
15522 case 128:
ea397f5b 15523 mnemonicendp = stpcpy (obuf, "vzeroupper");
c0f3af97
L		 15524 break;
15525 case 256:
ea397f5b 15526 mnemonicendp = stpcpy (obuf, "vzeroall");
c0f3af97
L		 15527 break;
15528 default:
15529 abort ();
15530 }
15531}
15532
ea397f5b
L		 15533static struct op vex_cmp_op[] =
15534{
15535 { STRING_COMMA_LEN ("eq") },
15536 { STRING_COMMA_LEN ("lt") },
15537 { STRING_COMMA_LEN ("le") },
15538 { STRING_COMMA_LEN ("unord") },
15539 { STRING_COMMA_LEN ("neq") },
15540 { STRING_COMMA_LEN ("nlt") },
15541 { STRING_COMMA_LEN ("nle") },
15542 { STRING_COMMA_LEN ("ord") },
15543 { STRING_COMMA_LEN ("eq_uq") },
15544 { STRING_COMMA_LEN ("nge") },
15545 { STRING_COMMA_LEN ("ngt") },
15546 { STRING_COMMA_LEN ("false") },
15547 { STRING_COMMA_LEN ("neq_oq") },
15548 { STRING_COMMA_LEN ("ge") },
15549 { STRING_COMMA_LEN ("gt") },
15550 { STRING_COMMA_LEN ("true") },
15551 { STRING_COMMA_LEN ("eq_os") },
15552 { STRING_COMMA_LEN ("lt_oq") },
15553 { STRING_COMMA_LEN ("le_oq") },
15554 { STRING_COMMA_LEN ("unord_s") },
15555 { STRING_COMMA_LEN ("neq_us") },
15556 { STRING_COMMA_LEN ("nlt_uq") },
15557 { STRING_COMMA_LEN ("nle_uq") },
15558 { STRING_COMMA_LEN ("ord_s") },
15559 { STRING_COMMA_LEN ("eq_us") },
15560 { STRING_COMMA_LEN ("nge_uq") },
15561 { STRING_COMMA_LEN ("ngt_uq") },
15562 { STRING_COMMA_LEN ("false_os") },
15563 { STRING_COMMA_LEN ("neq_os") },
15564 { STRING_COMMA_LEN ("ge_oq") },
15565 { STRING_COMMA_LEN ("gt_oq") },
15566 { STRING_COMMA_LEN ("true_us") },
c0f3af97
L		 15567};
15568
15569static void
15570VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15571{
15572 unsigned int cmp_type;
15573
15574 FETCH_DATA (the_info, codep + 1);
15575 cmp_type = *codep++ & 0xff;
15576 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
15577 {
15578 char suffix [3];
ea397f5b 15579 char *p = mnemonicendp - 2;
c0f3af97
L		 15580 suffix[0] = p[0];
15581 suffix[1] = p[1];
15582 suffix[2] = '\0';
ea397f5b
L		 15583 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
15584 mnemonicendp += vex_cmp_op[cmp_type].len;
c0f3af97
L		 15585 }
15586 else
15587 {
15588 /* We have a reserved extension byte. Output it directly. */
15589 scratchbuf[0] = '$';
15590 print_operand_value (scratchbuf + 1, 1, cmp_type);
15591 oappend (scratchbuf + intel_syntax);
15592 scratchbuf[0] = '\0';
15593 }
15594}
15595
ea397f5b
L		 15596static const struct op pclmul_op[] =
15597{
15598 { STRING_COMMA_LEN ("lql") },
15599 { STRING_COMMA_LEN ("hql") },
15600 { STRING_COMMA_LEN ("lqh") },
15601 { STRING_COMMA_LEN ("hqh") }
c0f3af97
L		 15602};
15603
15604static void
15605PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
15606 int sizeflag ATTRIBUTE_UNUSED)
15607{
15608 unsigned int pclmul_type;
15609
15610 FETCH_DATA (the_info, codep + 1);
15611 pclmul_type = *codep++ & 0xff;
15612 switch (pclmul_type)
15613 {
15614 case 0x10:
15615 pclmul_type = 2;
15616 break;
15617 case 0x11:
15618 pclmul_type = 3;
15619 break;
15620 default:
15621 break;
15622 }
15623 if (pclmul_type < ARRAY_SIZE (pclmul_op))
15624 {
15625 char suffix [4];
ea397f5b 15626 char *p = mnemonicendp - 3;
c0f3af97
L		 15627 suffix[0] = p[0];
15628 suffix[1] = p[1];
15629 suffix[2] = p[2];
15630 suffix[3] = '\0';
ea397f5b
L		 15631 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
15632 mnemonicendp += pclmul_op[pclmul_type].len;
c0f3af97
L		 15633 }
15634 else
15635 {
15636 /* We have a reserved extension byte. Output it directly. */
15637 scratchbuf[0] = '$';
15638 print_operand_value (scratchbuf + 1, 1, pclmul_type);
15639 oappend (scratchbuf + intel_syntax);
15640 scratchbuf[0] = '\0';
15641 }
15642}
15643
f1f8f695
L		 15644static void
15645MOVBE_Fixup (int bytemode, int sizeflag)
15646{
15647 /* Add proper suffix to "movbe". */
ea397f5b 15648 char *p = mnemonicendp;
f1f8f695
L		 15649
15650 switch (bytemode)
15651 {
15652 case v_mode:
15653 if (intel_syntax)
ea397f5b 15654 goto skip;
f1f8f695
L		 15655
15656 USED_REX (REX_W);
15657 if (sizeflag & SUFFIX_ALWAYS)
15658 {
15659 if (rex & REX_W)
15660 *p++ = 'q';
f1f8f695 15661 else
f16cd0d5
L		 15662 {
15663 if (sizeflag & DFLAG)
15664 *p++ = 'l';
15665 else
15666 *p++ = 'w';
15667 used_prefixes |= (prefixes & PREFIX_DATA);
15668 }
f1f8f695 15669 }
f1f8f695
L		 15670 break;
15671 default:
15672 oappend (INTERNAL_DISASSEMBLER_ERROR);
15673 break;
15674 }
ea397f5b 15675 mnemonicendp = p;
f1f8f695
L		 15676 *p = '\0';
15677
ea397f5b 15678skip:
f1f8f695
L		 15679 OP_M (bytemode, sizeflag);
15680}
f88c9eb0
SP		 15681
15682static void
15683OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15684{
15685 int reg;
15686 const char **names;
15687
15688 /* Skip mod/rm byte. */
15689 MODRM_CHECK;
15690 codep++;
15691
15692 if (vex.w)
15693 names = names64;
15694 else if (vex.length == 256)
15695 names = names32;
15696 else
15697 names = names16;
15698
15699 reg = modrm.rm;
15700 USED_REX (REX_B);
15701 if (rex & REX_B)
15702 reg += 8;
15703
15704 oappend (names[reg]);
15705}
15706
15707static void
15708OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15709{
15710 const char **names;
15711
15712 if (vex.w)
15713 names = names64;
15714 else if (vex.length == 256)
15715 names = names32;
15716 else
15717 names = names16;
15718
15719 oappend (names[vex.register_specifier]);
15720}
15721
15722static void
15723OP_LWP_I (int bytemode ATTRIBUTE_UNUSED, int sizeflag)
15724{
15725 if (vex.w || vex.length == 256)
15726 OP_I (q_mode, sizeflag);
15727 else
15728 OP_I (w_mode, sizeflag);
15729}
15730
GDB Binutils - Deliverables
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