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perf/x86/intel: Add Broadwell core support
[deliverable/linux.git] / arch / x86 / kernel / cpu / perf_event_intel.c
CommitLineData
a7e3ed1e 1/*
efc9f05d
SE		 2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
a7e3ed1e 6 */
de0428a7 7
c767a54b
JP		 8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
de0428a7
KW		 10#include <linux/stddef.h>
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/slab.h>
69c60c88 14#include <linux/export.h>
de0428a7 15
3a632cb2 16#include <asm/cpufeature.h>
de0428a7
KW		 17#include <asm/hardirq.h>
18#include <asm/apic.h>
19
20#include "perf_event.h"
a7e3ed1e 21
f22f54f4 22/*
b622d644 23 * Intel PerfMon, used on Core and later.
f22f54f4 24 */
ec75a716 25static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
f22f54f4 26{
c3b7cdf1
PE		 27 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
28 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
29 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
30 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
31 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
32 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
33 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
34 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
f22f54f4
PZ		 35};
36
5c543e3c 37static struct event_constraint intel_core_event_constraints[] __read_mostly =
f22f54f4
PZ		 38{
39 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
40 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
41 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
42 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
43 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
44 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
45 EVENT_CONSTRAINT_END
46};
47
5c543e3c 48static struct event_constraint intel_core2_event_constraints[] __read_mostly =
f22f54f4 49{
b622d644
PZ		 50 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
51 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 52 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 53 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
54 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
55 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
56 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
57 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
58 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
59 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
60 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
b622d644 61 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
f22f54f4
PZ		 62 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
63 EVENT_CONSTRAINT_END
64};
65
5c543e3c 66static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
f22f54f4 67{
b622d644
PZ		 68 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
69 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 70 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 71 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
72 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
73 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
74 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
75 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
76 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
77 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
78 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
79 EVENT_CONSTRAINT_END
80};
81
5c543e3c 82static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
a7e3ed1e 83{
53ad0447
YZ		 84 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
85 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
f20093ee 86 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 87 EVENT_EXTRA_END
88};
89
5c543e3c 90static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
f22f54f4 91{
b622d644
PZ		 92 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
93 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 94 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 95 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
96 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
97 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
d1100770 98 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
f22f54f4
PZ		 99 EVENT_CONSTRAINT_END
100};
101
5c543e3c 102static struct event_constraint intel_snb_event_constraints[] __read_mostly =
b06b3d49
LM		 103{
104 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
105 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 106 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
fd4a5aef
SE		 107 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
108 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
109 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
110 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
b06b3d49 111 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
b06b3d49
LM		 112 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
113 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
f8378f52
AK		 114 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
115 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
b06b3d49
LM		 116 EVENT_CONSTRAINT_END
117};
118
69943182
SE		 119static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
120{
121 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
122 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
123 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
124 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
125 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
126 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
6113af14 127 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
69943182
SE		 128 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
129 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
130 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
131 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
132 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
133 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
741a698f
PZ		 134 /*
135 * Errata BV98 -- MEM_*_RETIRED events can leak between counters of SMT
136 * siblings; disable these events because they can corrupt unrelated
137 * counters.
138 */
139 INTEL_EVENT_CONSTRAINT(0xd0, 0x0), /* MEM_UOPS_RETIRED.* */
140 INTEL_EVENT_CONSTRAINT(0xd1, 0x0), /* MEM_LOAD_UOPS_RETIRED.* */
141 INTEL_EVENT_CONSTRAINT(0xd2, 0x0), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
142 INTEL_EVENT_CONSTRAINT(0xd3, 0x0), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
69943182
SE		 143 EVENT_CONSTRAINT_END
144};
145
5c543e3c 146static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
a7e3ed1e 147{
53ad0447
YZ		 148 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
149 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
150 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
f20093ee 151 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 152 EVENT_EXTRA_END
153};
154
0af3ac1f
AK		 155static struct event_constraint intel_v1_event_constraints[] __read_mostly =
156{
157 EVENT_CONSTRAINT_END
158};
159
5c543e3c 160static struct event_constraint intel_gen_event_constraints[] __read_mostly =
f22f54f4 161{
b622d644
PZ		 162 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
163 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 164 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 165 EVENT_CONSTRAINT_END
166};
167
1fa64180
YZ		 168static struct event_constraint intel_slm_event_constraints[] __read_mostly =
169{
170 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
171 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
1fa64180
YZ		 172 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
173 EVENT_CONSTRAINT_END
174};
175
ee89cbc2 176static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
53ad0447
YZ		 177 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
178 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
179 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
f20093ee 180 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
f1923820
SE		 181 EVENT_EXTRA_END
182};
183
184static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
53ad0447
YZ		 185 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
186 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
187 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
f1a52789 188 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
ee89cbc2
SE		 189 EVENT_EXTRA_END
190};
191
7f2ee91f
IM		 192EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
193EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
194EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
f20093ee
SE		 195
196struct attribute *nhm_events_attrs[] = {
197 EVENT_PTR(mem_ld_nhm),
198 NULL,
199};
200
201struct attribute *snb_events_attrs[] = {
202 EVENT_PTR(mem_ld_snb),
9ad64c0f 203 EVENT_PTR(mem_st_snb),
f20093ee
SE		 204 NULL,
205};
206
3a632cb2
AK		 207static struct event_constraint intel_hsw_event_constraints[] = {
208 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
209 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
210 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
211 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.* */
212 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
213 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
214 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
215 INTEL_EVENT_CONSTRAINT(0x08a3, 0x4),
216 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
217 INTEL_EVENT_CONSTRAINT(0x0ca3, 0x4),
218 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
219 INTEL_EVENT_CONSTRAINT(0x04a3, 0xf),
220 EVENT_CONSTRAINT_END
221};
222
91f1b705
AK		 223struct event_constraint intel_bdw_event_constraints[] = {
224 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
225 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
226 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
227 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
228 INTEL_EVENT_CONSTRAINT(0xa3, 0x4), /* CYCLE_ACTIVITY.* */
229 EVENT_CONSTRAINT_END
230};
231
f22f54f4
PZ		 232static u64 intel_pmu_event_map(int hw_event)
233{
234 return intel_perfmon_event_map[hw_event];
235}
236
74e6543f
YZ		 237#define SNB_DMND_DATA_RD (1ULL << 0)
238#define SNB_DMND_RFO (1ULL << 1)
239#define SNB_DMND_IFETCH (1ULL << 2)
240#define SNB_DMND_WB (1ULL << 3)
241#define SNB_PF_DATA_RD (1ULL << 4)
242#define SNB_PF_RFO (1ULL << 5)
243#define SNB_PF_IFETCH (1ULL << 6)
244#define SNB_LLC_DATA_RD (1ULL << 7)
245#define SNB_LLC_RFO (1ULL << 8)
246#define SNB_LLC_IFETCH (1ULL << 9)
247#define SNB_BUS_LOCKS (1ULL << 10)
248#define SNB_STRM_ST (1ULL << 11)
249#define SNB_OTHER (1ULL << 15)
250#define SNB_RESP_ANY (1ULL << 16)
251#define SNB_NO_SUPP (1ULL << 17)
252#define SNB_LLC_HITM (1ULL << 18)
253#define SNB_LLC_HITE (1ULL << 19)
254#define SNB_LLC_HITS (1ULL << 20)
255#define SNB_LLC_HITF (1ULL << 21)
256#define SNB_LOCAL (1ULL << 22)
257#define SNB_REMOTE (0xffULL << 23)
258#define SNB_SNP_NONE (1ULL << 31)
259#define SNB_SNP_NOT_NEEDED (1ULL << 32)
260#define SNB_SNP_MISS (1ULL << 33)
261#define SNB_NO_FWD (1ULL << 34)
262#define SNB_SNP_FWD (1ULL << 35)
263#define SNB_HITM (1ULL << 36)
264#define SNB_NON_DRAM (1ULL << 37)
265
266#define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
267#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
268#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
269
270#define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
271 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
272 SNB_HITM)
273
274#define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
275#define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
276
277#define SNB_L3_ACCESS SNB_RESP_ANY
278#define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
279
280static __initconst const u64 snb_hw_cache_extra_regs
281 [PERF_COUNT_HW_CACHE_MAX]
282 [PERF_COUNT_HW_CACHE_OP_MAX]
283 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
284{
285 [ C(LL ) ] = {
286 [ C(OP_READ) ] = {
287 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
288 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
289 },
290 [ C(OP_WRITE) ] = {
291 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
292 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
293 },
294 [ C(OP_PREFETCH) ] = {
295 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
296 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
297 },
298 },
299 [ C(NODE) ] = {
300 [ C(OP_READ) ] = {
301 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
302 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
303 },
304 [ C(OP_WRITE) ] = {
305 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
306 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
307 },
308 [ C(OP_PREFETCH) ] = {
309 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
310 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
311 },
312 },
313};
314
b06b3d49
LM		 315static __initconst const u64 snb_hw_cache_event_ids
316 [PERF_COUNT_HW_CACHE_MAX]
317 [PERF_COUNT_HW_CACHE_OP_MAX]
318 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
319{
320 [ C(L1D) ] = {
321 [ C(OP_READ) ] = {
322 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
323 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
324 },
325 [ C(OP_WRITE) ] = {
326 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
327 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
328 },
329 [ C(OP_PREFETCH) ] = {
330 [ C(RESULT_ACCESS) ] = 0x0,
331 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
332 },
333 },
334 [ C(L1I ) ] = {
335 [ C(OP_READ) ] = {
336 [ C(RESULT_ACCESS) ] = 0x0,
337 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
338 },
339 [ C(OP_WRITE) ] = {
340 [ C(RESULT_ACCESS) ] = -1,
341 [ C(RESULT_MISS) ] = -1,
342 },
343 [ C(OP_PREFETCH) ] = {
344 [ C(RESULT_ACCESS) ] = 0x0,
345 [ C(RESULT_MISS) ] = 0x0,
346 },
347 },
348 [ C(LL ) ] = {
b06b3d49 349 [ C(OP_READ) ] = {
63b6a675 350 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
b06b3d49 351 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 352 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
353 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 354 },
355 [ C(OP_WRITE) ] = {
63b6a675 356 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
b06b3d49 357 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 358 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
359 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 360 },
361 [ C(OP_PREFETCH) ] = {
63b6a675 362 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
b06b3d49 363 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 364 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
365 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 366 },
367 },
368 [ C(DTLB) ] = {
369 [ C(OP_READ) ] = {
370 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
371 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
372 },
373 [ C(OP_WRITE) ] = {
374 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
375 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
376 },
377 [ C(OP_PREFETCH) ] = {
378 [ C(RESULT_ACCESS) ] = 0x0,
379 [ C(RESULT_MISS) ] = 0x0,
380 },
381 },
382 [ C(ITLB) ] = {
383 [ C(OP_READ) ] = {
384 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
385 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
386 },
387 [ C(OP_WRITE) ] = {
388 [ C(RESULT_ACCESS) ] = -1,
389 [ C(RESULT_MISS) ] = -1,
390 },
391 [ C(OP_PREFETCH) ] = {
392 [ C(RESULT_ACCESS) ] = -1,
393 [ C(RESULT_MISS) ] = -1,
394 },
395 },
396 [ C(BPU ) ] = {
397 [ C(OP_READ) ] = {
398 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
399 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
400 },
401 [ C(OP_WRITE) ] = {
402 [ C(RESULT_ACCESS) ] = -1,
403 [ C(RESULT_MISS) ] = -1,
404 },
405 [ C(OP_PREFETCH) ] = {
406 [ C(RESULT_ACCESS) ] = -1,
407 [ C(RESULT_MISS) ] = -1,
408 },
409 },
89d6c0b5
PZ		 410 [ C(NODE) ] = {
411 [ C(OP_READ) ] = {
74e6543f
YZ		 412 [ C(RESULT_ACCESS) ] = 0x01b7,
413 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 414 },
415 [ C(OP_WRITE) ] = {
74e6543f
YZ		 416 [ C(RESULT_ACCESS) ] = 0x01b7,
417 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 418 },
419 [ C(OP_PREFETCH) ] = {
74e6543f
YZ		 420 [ C(RESULT_ACCESS) ] = 0x01b7,
421 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 422 },
423 },
424
b06b3d49
LM		 425};
426
0f1b5ca2
AK		 427/*
428 * Notes on the events:
429 * - data reads do not include code reads (comparable to earlier tables)
430 * - data counts include speculative execution (except L1 write, dtlb, bpu)
431 * - remote node access includes remote memory, remote cache, remote mmio.
432 * - prefetches are not included in the counts because they are not
433 * reliably counted.
434 */
435
436#define HSW_DEMAND_DATA_RD BIT_ULL(0)
437#define HSW_DEMAND_RFO BIT_ULL(1)
438#define HSW_ANY_RESPONSE BIT_ULL(16)
439#define HSW_SUPPLIER_NONE BIT_ULL(17)
440#define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
441#define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
442#define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
443#define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
444#define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
445 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
446 HSW_L3_MISS_REMOTE_HOP2P)
447#define HSW_SNOOP_NONE BIT_ULL(31)
448#define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
449#define HSW_SNOOP_MISS BIT_ULL(33)
450#define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
451#define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
452#define HSW_SNOOP_HITM BIT_ULL(36)
453#define HSW_SNOOP_NON_DRAM BIT_ULL(37)
454#define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
455 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
456 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
457 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
458#define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
459#define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
460#define HSW_DEMAND_WRITE HSW_DEMAND_RFO
461#define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
462 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
463#define HSW_LLC_ACCESS HSW_ANY_RESPONSE
464
91f1b705
AK		 465#define BDW_L3_MISS_LOCAL BIT(26)
466#define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
467 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
468 HSW_L3_MISS_REMOTE_HOP2P)
469
470
0f1b5ca2
AK		 471static __initconst const u64 hsw_hw_cache_event_ids
472 [PERF_COUNT_HW_CACHE_MAX]
473 [PERF_COUNT_HW_CACHE_OP_MAX]
474 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
475{
476 [ C(L1D ) ] = {
477 [ C(OP_READ) ] = {
478 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
479 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
480 },
481 [ C(OP_WRITE) ] = {
482 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
483 [ C(RESULT_MISS) ] = 0x0,
484 },
485 [ C(OP_PREFETCH) ] = {
486 [ C(RESULT_ACCESS) ] = 0x0,
487 [ C(RESULT_MISS) ] = 0x0,
488 },
489 },
490 [ C(L1I ) ] = {
491 [ C(OP_READ) ] = {
492 [ C(RESULT_ACCESS) ] = 0x0,
493 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
494 },
495 [ C(OP_WRITE) ] = {
496 [ C(RESULT_ACCESS) ] = -1,
497 [ C(RESULT_MISS) ] = -1,
498 },
499 [ C(OP_PREFETCH) ] = {
500 [ C(RESULT_ACCESS) ] = 0x0,
501 [ C(RESULT_MISS) ] = 0x0,
502 },
503 },
504 [ C(LL ) ] = {
505 [ C(OP_READ) ] = {
506 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
507 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
508 },
509 [ C(OP_WRITE) ] = {
510 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
511 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
512 },
513 [ C(OP_PREFETCH) ] = {
514 [ C(RESULT_ACCESS) ] = 0x0,
515 [ C(RESULT_MISS) ] = 0x0,
516 },
517 },
518 [ C(DTLB) ] = {
519 [ C(OP_READ) ] = {
520 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
521 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
522 },
523 [ C(OP_WRITE) ] = {
524 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
525 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
526 },
527 [ C(OP_PREFETCH) ] = {
528 [ C(RESULT_ACCESS) ] = 0x0,
529 [ C(RESULT_MISS) ] = 0x0,
530 },
531 },
532 [ C(ITLB) ] = {
533 [ C(OP_READ) ] = {
534 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
535 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
536 },
537 [ C(OP_WRITE) ] = {
538 [ C(RESULT_ACCESS) ] = -1,
539 [ C(RESULT_MISS) ] = -1,
540 },
541 [ C(OP_PREFETCH) ] = {
542 [ C(RESULT_ACCESS) ] = -1,
543 [ C(RESULT_MISS) ] = -1,
544 },
545 },
546 [ C(BPU ) ] = {
547 [ C(OP_READ) ] = {
548 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
549 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
550 },
551 [ C(OP_WRITE) ] = {
552 [ C(RESULT_ACCESS) ] = -1,
553 [ C(RESULT_MISS) ] = -1,
554 },
555 [ C(OP_PREFETCH) ] = {
556 [ C(RESULT_ACCESS) ] = -1,
557 [ C(RESULT_MISS) ] = -1,
558 },
559 },
560 [ C(NODE) ] = {
561 [ C(OP_READ) ] = {
562 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
563 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
564 },
565 [ C(OP_WRITE) ] = {
566 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
567 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
568 },
569 [ C(OP_PREFETCH) ] = {
570 [ C(RESULT_ACCESS) ] = 0x0,
571 [ C(RESULT_MISS) ] = 0x0,
572 },
573 },
574};
575
576static __initconst const u64 hsw_hw_cache_extra_regs
577 [PERF_COUNT_HW_CACHE_MAX]
578 [PERF_COUNT_HW_CACHE_OP_MAX]
579 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
580{
581 [ C(LL ) ] = {
582 [ C(OP_READ) ] = {
583 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
584 HSW_LLC_ACCESS,
585 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
586 HSW_L3_MISS|HSW_ANY_SNOOP,
587 },
588 [ C(OP_WRITE) ] = {
589 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
590 HSW_LLC_ACCESS,
591 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
592 HSW_L3_MISS|HSW_ANY_SNOOP,
593 },
594 [ C(OP_PREFETCH) ] = {
595 [ C(RESULT_ACCESS) ] = 0x0,
596 [ C(RESULT_MISS) ] = 0x0,
597 },
598 },
599 [ C(NODE) ] = {
600 [ C(OP_READ) ] = {
601 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
602 HSW_L3_MISS_LOCAL_DRAM|
603 HSW_SNOOP_DRAM,
604 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
605 HSW_L3_MISS_REMOTE|
606 HSW_SNOOP_DRAM,
607 },
608 [ C(OP_WRITE) ] = {
609 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
610 HSW_L3_MISS_LOCAL_DRAM|
611 HSW_SNOOP_DRAM,
612 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
613 HSW_L3_MISS_REMOTE|
614 HSW_SNOOP_DRAM,
615 },
616 [ C(OP_PREFETCH) ] = {
617 [ C(RESULT_ACCESS) ] = 0x0,
618 [ C(RESULT_MISS) ] = 0x0,
619 },
620 },
621};
622
caaa8be3 623static __initconst const u64 westmere_hw_cache_event_ids
f22f54f4
PZ		 624 [PERF_COUNT_HW_CACHE_MAX]
625 [PERF_COUNT_HW_CACHE_OP_MAX]
626 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
627{
628 [ C(L1D) ] = {
629 [ C(OP_READ) ] = {
630 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
631 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
632 },
633 [ C(OP_WRITE) ] = {
634 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
635 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
636 },
637 [ C(OP_PREFETCH) ] = {
638 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
639 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
640 },
641 },
642 [ C(L1I ) ] = {
643 [ C(OP_READ) ] = {
644 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
645 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
646 },
647 [ C(OP_WRITE) ] = {
648 [ C(RESULT_ACCESS) ] = -1,
649 [ C(RESULT_MISS) ] = -1,
650 },
651 [ C(OP_PREFETCH) ] = {
652 [ C(RESULT_ACCESS) ] = 0x0,
653 [ C(RESULT_MISS) ] = 0x0,
654 },
655 },
656 [ C(LL ) ] = {
657 [ C(OP_READ) ] = {
63b6a675 658 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
e994d7d2 659 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 660 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
661 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 662 },
e994d7d2
AK		 663 /*
664 * Use RFO, not WRITEBACK, because a write miss would typically occur
665 * on RFO.
666 */
f22f54f4 667 [ C(OP_WRITE) ] = {
63b6a675
PZ		 668 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
669 [ C(RESULT_ACCESS) ] = 0x01b7,
670 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
e994d7d2 671 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 672 },
673 [ C(OP_PREFETCH) ] = {
63b6a675 674 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
e994d7d2 675 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 676 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
677 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 678 },
679 },
680 [ C(DTLB) ] = {
681 [ C(OP_READ) ] = {
682 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
683 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
684 },
685 [ C(OP_WRITE) ] = {
686 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
687 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
688 },
689 [ C(OP_PREFETCH) ] = {
690 [ C(RESULT_ACCESS) ] = 0x0,
691 [ C(RESULT_MISS) ] = 0x0,
692 },
693 },
694 [ C(ITLB) ] = {
695 [ C(OP_READ) ] = {
696 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
697 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
698 },
699 [ C(OP_WRITE) ] = {
700 [ C(RESULT_ACCESS) ] = -1,
701 [ C(RESULT_MISS) ] = -1,
702 },
703 [ C(OP_PREFETCH) ] = {
704 [ C(RESULT_ACCESS) ] = -1,
705 [ C(RESULT_MISS) ] = -1,
706 },
707 },
708 [ C(BPU ) ] = {
709 [ C(OP_READ) ] = {
710 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
711 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
712 },
713 [ C(OP_WRITE) ] = {
714 [ C(RESULT_ACCESS) ] = -1,
715 [ C(RESULT_MISS) ] = -1,
716 },
717 [ C(OP_PREFETCH) ] = {
718 [ C(RESULT_ACCESS) ] = -1,
719 [ C(RESULT_MISS) ] = -1,
720 },
721 },
89d6c0b5
PZ		 722 [ C(NODE) ] = {
723 [ C(OP_READ) ] = {
724 [ C(RESULT_ACCESS) ] = 0x01b7,
725 [ C(RESULT_MISS) ] = 0x01b7,
726 },
727 [ C(OP_WRITE) ] = {
728 [ C(RESULT_ACCESS) ] = 0x01b7,
729 [ C(RESULT_MISS) ] = 0x01b7,
730 },
731 [ C(OP_PREFETCH) ] = {
732 [ C(RESULT_ACCESS) ] = 0x01b7,
733 [ C(RESULT_MISS) ] = 0x01b7,
734 },
735 },
f22f54f4
PZ		 736};
737
e994d7d2 738/*
63b6a675
PZ		 739 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
740 * See IA32 SDM Vol 3B 30.6.1.3
e994d7d2
AK		 741 */
742
63b6a675
PZ		 743#define NHM_DMND_DATA_RD (1 << 0)
744#define NHM_DMND_RFO (1 << 1)
745#define NHM_DMND_IFETCH (1 << 2)
746#define NHM_DMND_WB (1 << 3)
747#define NHM_PF_DATA_RD (1 << 4)
748#define NHM_PF_DATA_RFO (1 << 5)
749#define NHM_PF_IFETCH (1 << 6)
750#define NHM_OFFCORE_OTHER (1 << 7)
751#define NHM_UNCORE_HIT (1 << 8)
752#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
753#define NHM_OTHER_CORE_HITM (1 << 10)
754 /* reserved */
755#define NHM_REMOTE_CACHE_FWD (1 << 12)
756#define NHM_REMOTE_DRAM (1 << 13)
757#define NHM_LOCAL_DRAM (1 << 14)
758#define NHM_NON_DRAM (1 << 15)
759
87e24f4b
PZ		 760#define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
761#define NHM_REMOTE (NHM_REMOTE_DRAM)
63b6a675
PZ		 762
763#define NHM_DMND_READ (NHM_DMND_DATA_RD)
764#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
765#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
766
767#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
87e24f4b 768#define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
63b6a675 769#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
e994d7d2
AK		 770
771static __initconst const u64 nehalem_hw_cache_extra_regs
772 [PERF_COUNT_HW_CACHE_MAX]
773 [PERF_COUNT_HW_CACHE_OP_MAX]
774 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
775{
776 [ C(LL ) ] = {
777 [ C(OP_READ) ] = {
63b6a675
PZ		 778 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
779 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
e994d7d2
AK		 780 },
781 [ C(OP_WRITE) ] = {
63b6a675
PZ		 782 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
783 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
e994d7d2
AK		 784 },
785 [ C(OP_PREFETCH) ] = {
63b6a675
PZ		 786 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
787 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
e994d7d2 788 },
89d6c0b5
PZ		 789 },
790 [ C(NODE) ] = {
791 [ C(OP_READ) ] = {
87e24f4b
PZ		 792 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
793 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
89d6c0b5
PZ		 794 },
795 [ C(OP_WRITE) ] = {
87e24f4b
PZ		 796 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
797 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
89d6c0b5
PZ		 798 },
799 [ C(OP_PREFETCH) ] = {
87e24f4b
PZ		 800 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
801 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
89d6c0b5
PZ		 802 },
803 },
e994d7d2
AK		 804};
805
caaa8be3 806static __initconst const u64 nehalem_hw_cache_event_ids
f22f54f4
PZ		 807 [PERF_COUNT_HW_CACHE_MAX]
808 [PERF_COUNT_HW_CACHE_OP_MAX]
809 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
810{
811 [ C(L1D) ] = {
812 [ C(OP_READ) ] = {
f4929bd3
PZ		 813 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
814 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
f22f54f4
PZ		 815 },
816 [ C(OP_WRITE) ] = {
f4929bd3
PZ		 817 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
818 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
f22f54f4
PZ		 819 },
820 [ C(OP_PREFETCH) ] = {
821 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
822 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
823 },
824 },
825 [ C(L1I ) ] = {
826 [ C(OP_READ) ] = {
827 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
828 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
829 },
830 [ C(OP_WRITE) ] = {
831 [ C(RESULT_ACCESS) ] = -1,
832 [ C(RESULT_MISS) ] = -1,
833 },
834 [ C(OP_PREFETCH) ] = {
835 [ C(RESULT_ACCESS) ] = 0x0,
836 [ C(RESULT_MISS) ] = 0x0,
837 },
838 },
839 [ C(LL ) ] = {
840 [ C(OP_READ) ] = {
e994d7d2
AK		 841 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
842 [ C(RESULT_ACCESS) ] = 0x01b7,
843 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
844 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 845 },
e994d7d2
AK		 846 /*
847 * Use RFO, not WRITEBACK, because a write miss would typically occur
848 * on RFO.
849 */
f22f54f4 850 [ C(OP_WRITE) ] = {
e994d7d2
AK		 851 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
852 [ C(RESULT_ACCESS) ] = 0x01b7,
853 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
854 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 855 },
856 [ C(OP_PREFETCH) ] = {
e994d7d2
AK		 857 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
858 [ C(RESULT_ACCESS) ] = 0x01b7,
859 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
860 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 861 },
862 },
863 [ C(DTLB) ] = {
864 [ C(OP_READ) ] = {
865 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
866 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
867 },
868 [ C(OP_WRITE) ] = {
869 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
870 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
871 },
872 [ C(OP_PREFETCH) ] = {
873 [ C(RESULT_ACCESS) ] = 0x0,
874 [ C(RESULT_MISS) ] = 0x0,
875 },
876 },
877 [ C(ITLB) ] = {
878 [ C(OP_READ) ] = {
879 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
880 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
881 },
882 [ C(OP_WRITE) ] = {
883 [ C(RESULT_ACCESS) ] = -1,
884 [ C(RESULT_MISS) ] = -1,
885 },
886 [ C(OP_PREFETCH) ] = {
887 [ C(RESULT_ACCESS) ] = -1,
888 [ C(RESULT_MISS) ] = -1,
889 },
890 },
891 [ C(BPU ) ] = {
892 [ C(OP_READ) ] = {
893 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
894 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
895 },
896 [ C(OP_WRITE) ] = {
897 [ C(RESULT_ACCESS) ] = -1,
898 [ C(RESULT_MISS) ] = -1,
899 },
900 [ C(OP_PREFETCH) ] = {
901 [ C(RESULT_ACCESS) ] = -1,
902 [ C(RESULT_MISS) ] = -1,
903 },
904 },
89d6c0b5
PZ		 905 [ C(NODE) ] = {
906 [ C(OP_READ) ] = {
907 [ C(RESULT_ACCESS) ] = 0x01b7,
908 [ C(RESULT_MISS) ] = 0x01b7,
909 },
910 [ C(OP_WRITE) ] = {
911 [ C(RESULT_ACCESS) ] = 0x01b7,
912 [ C(RESULT_MISS) ] = 0x01b7,
913 },
914 [ C(OP_PREFETCH) ] = {
915 [ C(RESULT_ACCESS) ] = 0x01b7,
916 [ C(RESULT_MISS) ] = 0x01b7,
917 },
918 },
f22f54f4
PZ		 919};
920
caaa8be3 921static __initconst const u64 core2_hw_cache_event_ids
f22f54f4
PZ		 922 [PERF_COUNT_HW_CACHE_MAX]
923 [PERF_COUNT_HW_CACHE_OP_MAX]
924 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
925{
926 [ C(L1D) ] = {
927 [ C(OP_READ) ] = {
928 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
929 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
930 },
931 [ C(OP_WRITE) ] = {
932 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
933 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
934 },
935 [ C(OP_PREFETCH) ] = {
936 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
937 [ C(RESULT_MISS) ] = 0,
938 },
939 },
940 [ C(L1I ) ] = {
941 [ C(OP_READ) ] = {
942 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
943 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
944 },
945 [ C(OP_WRITE) ] = {
946 [ C(RESULT_ACCESS) ] = -1,
947 [ C(RESULT_MISS) ] = -1,
948 },
949 [ C(OP_PREFETCH) ] = {
950 [ C(RESULT_ACCESS) ] = 0,
951 [ C(RESULT_MISS) ] = 0,
952 },
953 },
954 [ C(LL ) ] = {
955 [ C(OP_READ) ] = {
956 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
957 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
958 },
959 [ C(OP_WRITE) ] = {
960 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
961 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
962 },
963 [ C(OP_PREFETCH) ] = {
964 [ C(RESULT_ACCESS) ] = 0,
965 [ C(RESULT_MISS) ] = 0,
966 },
967 },
968 [ C(DTLB) ] = {
969 [ C(OP_READ) ] = {
970 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
971 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
972 },
973 [ C(OP_WRITE) ] = {
974 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
975 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
976 },
977 [ C(OP_PREFETCH) ] = {
978 [ C(RESULT_ACCESS) ] = 0,
979 [ C(RESULT_MISS) ] = 0,
980 },
981 },
982 [ C(ITLB) ] = {
983 [ C(OP_READ) ] = {
984 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
985 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
986 },
987 [ C(OP_WRITE) ] = {
988 [ C(RESULT_ACCESS) ] = -1,
989 [ C(RESULT_MISS) ] = -1,
990 },
991 [ C(OP_PREFETCH) ] = {
992 [ C(RESULT_ACCESS) ] = -1,
993 [ C(RESULT_MISS) ] = -1,
994 },
995 },
996 [ C(BPU ) ] = {
997 [ C(OP_READ) ] = {
998 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
999 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1000 },
1001 [ C(OP_WRITE) ] = {
1002 [ C(RESULT_ACCESS) ] = -1,
1003 [ C(RESULT_MISS) ] = -1,
1004 },
1005 [ C(OP_PREFETCH) ] = {
1006 [ C(RESULT_ACCESS) ] = -1,
1007 [ C(RESULT_MISS) ] = -1,
1008 },
1009 },
1010};
1011
caaa8be3 1012static __initconst const u64 atom_hw_cache_event_ids
f22f54f4
PZ		 1013 [PERF_COUNT_HW_CACHE_MAX]
1014 [PERF_COUNT_HW_CACHE_OP_MAX]
1015 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1016{
1017 [ C(L1D) ] = {
1018 [ C(OP_READ) ] = {
1019 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1020 [ C(RESULT_MISS) ] = 0,
1021 },
1022 [ C(OP_WRITE) ] = {
1023 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1024 [ C(RESULT_MISS) ] = 0,
1025 },
1026 [ C(OP_PREFETCH) ] = {
1027 [ C(RESULT_ACCESS) ] = 0x0,
1028 [ C(RESULT_MISS) ] = 0,
1029 },
1030 },
1031 [ C(L1I ) ] = {
1032 [ C(OP_READ) ] = {
1033 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1034 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1035 },
1036 [ C(OP_WRITE) ] = {
1037 [ C(RESULT_ACCESS) ] = -1,
1038 [ C(RESULT_MISS) ] = -1,
1039 },
1040 [ C(OP_PREFETCH) ] = {
1041 [ C(RESULT_ACCESS) ] = 0,
1042 [ C(RESULT_MISS) ] = 0,
1043 },
1044 },
1045 [ C(LL ) ] = {
1046 [ C(OP_READ) ] = {
1047 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1048 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1049 },
1050 [ C(OP_WRITE) ] = {
1051 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1052 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1053 },
1054 [ C(OP_PREFETCH) ] = {
1055 [ C(RESULT_ACCESS) ] = 0,
1056 [ C(RESULT_MISS) ] = 0,
1057 },
1058 },
1059 [ C(DTLB) ] = {
1060 [ C(OP_READ) ] = {
1061 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1062 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1063 },
1064 [ C(OP_WRITE) ] = {
1065 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1066 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1067 },
1068 [ C(OP_PREFETCH) ] = {
1069 [ C(RESULT_ACCESS) ] = 0,
1070 [ C(RESULT_MISS) ] = 0,
1071 },
1072 },
1073 [ C(ITLB) ] = {
1074 [ C(OP_READ) ] = {
1075 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1076 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1077 },
1078 [ C(OP_WRITE) ] = {
1079 [ C(RESULT_ACCESS) ] = -1,
1080 [ C(RESULT_MISS) ] = -1,
1081 },
1082 [ C(OP_PREFETCH) ] = {
1083 [ C(RESULT_ACCESS) ] = -1,
1084 [ C(RESULT_MISS) ] = -1,
1085 },
1086 },
1087 [ C(BPU ) ] = {
1088 [ C(OP_READ) ] = {
1089 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1090 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1091 },
1092 [ C(OP_WRITE) ] = {
1093 [ C(RESULT_ACCESS) ] = -1,
1094 [ C(RESULT_MISS) ] = -1,
1095 },
1096 [ C(OP_PREFETCH) ] = {
1097 [ C(RESULT_ACCESS) ] = -1,
1098 [ C(RESULT_MISS) ] = -1,
1099 },
1100 },
1101};
1102
1fa64180
YZ		 1103static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1104{
1105 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
06c939c1
PZ		 1106 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1107 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x768005ffffull, RSP_1),
1fa64180
YZ		 1108 EVENT_EXTRA_END
1109};
1110
1111#define SLM_DMND_READ SNB_DMND_DATA_RD
1112#define SLM_DMND_WRITE SNB_DMND_RFO
1113#define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1114
1115#define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1116#define SLM_LLC_ACCESS SNB_RESP_ANY
1117#define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1118
1119static __initconst const u64 slm_hw_cache_extra_regs
1120 [PERF_COUNT_HW_CACHE_MAX]
1121 [PERF_COUNT_HW_CACHE_OP_MAX]
1122 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1123{
1124 [ C(LL ) ] = {
1125 [ C(OP_READ) ] = {
1126 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1127 [ C(RESULT_MISS) ] = SLM_DMND_READ|SLM_LLC_MISS,
1128 },
1129 [ C(OP_WRITE) ] = {
1130 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1131 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1132 },
1133 [ C(OP_PREFETCH) ] = {
1134 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1135 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1136 },
1137 },
1138};
1139
1140static __initconst const u64 slm_hw_cache_event_ids
1141 [PERF_COUNT_HW_CACHE_MAX]
1142 [PERF_COUNT_HW_CACHE_OP_MAX]
1143 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1144{
1145 [ C(L1D) ] = {
1146 [ C(OP_READ) ] = {
1147 [ C(RESULT_ACCESS) ] = 0,
1148 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1149 },
1150 [ C(OP_WRITE) ] = {
1151 [ C(RESULT_ACCESS) ] = 0,
1152 [ C(RESULT_MISS) ] = 0,
1153 },
1154 [ C(OP_PREFETCH) ] = {
1155 [ C(RESULT_ACCESS) ] = 0,
1156 [ C(RESULT_MISS) ] = 0,
1157 },
1158 },
1159 [ C(L1I ) ] = {
1160 [ C(OP_READ) ] = {
1161 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1162 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1163 },
1164 [ C(OP_WRITE) ] = {
1165 [ C(RESULT_ACCESS) ] = -1,
1166 [ C(RESULT_MISS) ] = -1,
1167 },
1168 [ C(OP_PREFETCH) ] = {
1169 [ C(RESULT_ACCESS) ] = 0,
1170 [ C(RESULT_MISS) ] = 0,
1171 },
1172 },
1173 [ C(LL ) ] = {
1174 [ C(OP_READ) ] = {
1175 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1176 [ C(RESULT_ACCESS) ] = 0x01b7,
1177 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1178 [ C(RESULT_MISS) ] = 0x01b7,
1179 },
1180 [ C(OP_WRITE) ] = {
1181 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1182 [ C(RESULT_ACCESS) ] = 0x01b7,
1183 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1184 [ C(RESULT_MISS) ] = 0x01b7,
1185 },
1186 [ C(OP_PREFETCH) ] = {
1187 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1188 [ C(RESULT_ACCESS) ] = 0x01b7,
1189 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1190 [ C(RESULT_MISS) ] = 0x01b7,
1191 },
1192 },
1193 [ C(DTLB) ] = {
1194 [ C(OP_READ) ] = {
1195 [ C(RESULT_ACCESS) ] = 0,
1196 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1197 },
1198 [ C(OP_WRITE) ] = {
1199 [ C(RESULT_ACCESS) ] = 0,
1200 [ C(RESULT_MISS) ] = 0,
1201 },
1202 [ C(OP_PREFETCH) ] = {
1203 [ C(RESULT_ACCESS) ] = 0,
1204 [ C(RESULT_MISS) ] = 0,
1205 },
1206 },
1207 [ C(ITLB) ] = {
1208 [ C(OP_READ) ] = {
1209 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1210 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1211 },
1212 [ C(OP_WRITE) ] = {
1213 [ C(RESULT_ACCESS) ] = -1,
1214 [ C(RESULT_MISS) ] = -1,
1215 },
1216 [ C(OP_PREFETCH) ] = {
1217 [ C(RESULT_ACCESS) ] = -1,
1218 [ C(RESULT_MISS) ] = -1,
1219 },
1220 },
1221 [ C(BPU ) ] = {
1222 [ C(OP_READ) ] = {
1223 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1224 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1225 },
1226 [ C(OP_WRITE) ] = {
1227 [ C(RESULT_ACCESS) ] = -1,
1228 [ C(RESULT_MISS) ] = -1,
1229 },
1230 [ C(OP_PREFETCH) ] = {
1231 [ C(RESULT_ACCESS) ] = -1,
1232 [ C(RESULT_MISS) ] = -1,
1233 },
1234 },
1235};
1236
f22f54f4
PZ		 1237static void intel_pmu_disable_all(void)
1238{
89cbc767 1239 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4
PZ		 1240
1241 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1242
15c7ad51 1243 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
f22f54f4 1244 intel_pmu_disable_bts();
ca037701
PZ		 1245
1246 intel_pmu_pebs_disable_all();
caff2bef 1247 intel_pmu_lbr_disable_all();
f22f54f4
PZ		 1248}
1249
11164cd4 1250static void intel_pmu_enable_all(int added)
f22f54f4 1251{
89cbc767 1252 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4 1253
d329527e
PZ		 1254 intel_pmu_pebs_enable_all();
1255 intel_pmu_lbr_enable_all();
144d31e6
GN		 1256 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1257 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
f22f54f4 1258
15c7ad51 1259 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
f22f54f4 1260 struct perf_event *event =
15c7ad51 1261 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
f22f54f4
PZ		 1262
1263 if (WARN_ON_ONCE(!event))
1264 return;
1265
1266 intel_pmu_enable_bts(event->hw.config);
1267 }
1268}
1269
11164cd4
PZ		 1270/*
1271 * Workaround for:
1272 * Intel Errata AAK100 (model 26)
1273 * Intel Errata AAP53 (model 30)
40b91cd1 1274 * Intel Errata BD53 (model 44)
11164cd4 1275 *
351af072
ZY		 1276 * The official story:
1277 * These chips need to be 'reset' when adding counters by programming the
1278 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
1279 * in sequence on the same PMC or on different PMCs.
1280 *
1281 * In practise it appears some of these events do in fact count, and
1282 * we need to programm all 4 events.
11164cd4 1283 */
351af072 1284static void intel_pmu_nhm_workaround(void)
11164cd4 1285{
89cbc767 1286 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
351af072
ZY		 1287 static const unsigned long nhm_magic[4] = {
1288 0x4300B5,
1289 0x4300D2,
1290 0x4300B1,
1291 0x4300B1
1292 };
1293 struct perf_event *event;
1294 int i;
11164cd4 1295
351af072
ZY		 1296 /*
1297 * The Errata requires below steps:
1298 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
1299 * 2) Configure 4 PERFEVTSELx with the magic events and clear
1300 * the corresponding PMCx;
1301 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
1302 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
1303 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
1304 */
11164cd4 1305
351af072
ZY		 1306 /*
1307 * The real steps we choose are a little different from above.
1308 * A) To reduce MSR operations, we don't run step 1) as they
1309 * are already cleared before this function is called;
1310 * B) Call x86_perf_event_update to save PMCx before configuring
1311 * PERFEVTSELx with magic number;
1312 * C) With step 5), we do clear only when the PERFEVTSELx is
1313 * not used currently.
1314 * D) Call x86_perf_event_set_period to restore PMCx;
1315 */
11164cd4 1316
351af072
ZY		 1317 /* We always operate 4 pairs of PERF Counters */
1318 for (i = 0; i < 4; i++) {
1319 event = cpuc->events[i];
1320 if (event)
1321 x86_perf_event_update(event);
1322 }
11164cd4 1323
351af072
ZY		 1324 for (i = 0; i < 4; i++) {
1325 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
1326 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
1327 }
1328
1329 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
1330 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
11164cd4 1331
351af072
ZY		 1332 for (i = 0; i < 4; i++) {
1333 event = cpuc->events[i];
1334
1335 if (event) {
1336 x86_perf_event_set_period(event);
31fa58af 1337 __x86_pmu_enable_event(&event->hw,
351af072
ZY		 1338 ARCH_PERFMON_EVENTSEL_ENABLE);
1339 } else
1340 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
11164cd4 1341 }
351af072
ZY		 1342}
1343
1344static void intel_pmu_nhm_enable_all(int added)
1345{
1346 if (added)
1347 intel_pmu_nhm_workaround();
11164cd4
PZ		 1348 intel_pmu_enable_all(added);
1349}
1350
f22f54f4
PZ		 1351static inline u64 intel_pmu_get_status(void)
1352{
1353 u64 status;
1354
1355 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1356
1357 return status;
1358}
1359
1360static inline void intel_pmu_ack_status(u64 ack)
1361{
1362 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1363}
1364
ca037701 1365static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
f22f54f4 1366{
15c7ad51 1367 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4
PZ		 1368 u64 ctrl_val, mask;
1369
1370 mask = 0xfULL << (idx * 4);
1371
1372 rdmsrl(hwc->config_base, ctrl_val);
1373 ctrl_val &= ~mask;
7645a24c 1374 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1375}
1376
2b9e344d
PZ		 1377static inline bool event_is_checkpointed(struct perf_event *event)
1378{
1379 return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
1380}
1381
ca037701 1382static void intel_pmu_disable_event(struct perf_event *event)
f22f54f4 1383{
aff3d91a 1384 struct hw_perf_event *hwc = &event->hw;
89cbc767 1385 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
aff3d91a 1386
15c7ad51 1387 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
f22f54f4
PZ		 1388 intel_pmu_disable_bts();
1389 intel_pmu_drain_bts_buffer();
1390 return;
1391 }
1392
144d31e6
GN		 1393 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1394 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
2b9e344d 1395 cpuc->intel_cp_status &= ~(1ull << hwc->idx);
144d31e6 1396
60ce0fbd
SE		 1397 /*
1398 * must disable before any actual event
1399 * because any event may be combined with LBR
1400 */
a46a2300 1401 if (needs_branch_stack(event))
60ce0fbd
SE		 1402 intel_pmu_lbr_disable(event);
1403
f22f54f4 1404 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1405 intel_pmu_disable_fixed(hwc);
f22f54f4
PZ		 1406 return;
1407 }
1408
aff3d91a 1409 x86_pmu_disable_event(event);
ca037701 1410
ab608344 1411 if (unlikely(event->attr.precise_ip))
ef21f683 1412 intel_pmu_pebs_disable(event);
f22f54f4
PZ		 1413}
1414
ca037701 1415static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
f22f54f4 1416{
15c7ad51 1417 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4 1418 u64 ctrl_val, bits, mask;
f22f54f4
PZ		 1419
1420 /*
1421 * Enable IRQ generation (0x8),
1422 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1423 * if requested:
1424 */
1425 bits = 0x8ULL;
1426 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1427 bits |= 0x2;
1428 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1429 bits |= 0x1;
1430
1431 /*
1432 * ANY bit is supported in v3 and up
1433 */
1434 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1435 bits |= 0x4;
1436
1437 bits <<= (idx * 4);
1438 mask = 0xfULL << (idx * 4);
1439
1440 rdmsrl(hwc->config_base, ctrl_val);
1441 ctrl_val &= ~mask;
1442 ctrl_val |= bits;
7645a24c 1443 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1444}
1445
aff3d91a 1446static void intel_pmu_enable_event(struct perf_event *event)
f22f54f4 1447{
aff3d91a 1448 struct hw_perf_event *hwc = &event->hw;
89cbc767 1449 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
aff3d91a 1450
15c7ad51 1451 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
0a3aee0d 1452 if (!__this_cpu_read(cpu_hw_events.enabled))
f22f54f4
PZ		 1453 return;
1454
1455 intel_pmu_enable_bts(hwc->config);
1456 return;
1457 }
60ce0fbd
SE		 1458 /*
1459 * must enabled before any actual event
1460 * because any event may be combined with LBR
1461 */
a46a2300 1462 if (needs_branch_stack(event))
60ce0fbd 1463 intel_pmu_lbr_enable(event);
f22f54f4 1464
144d31e6
GN		 1465 if (event->attr.exclude_host)
1466 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1467 if (event->attr.exclude_guest)
1468 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1469
2b9e344d
PZ		 1470 if (unlikely(event_is_checkpointed(event)))
1471 cpuc->intel_cp_status |= (1ull << hwc->idx);
1472
f22f54f4 1473 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1474 intel_pmu_enable_fixed(hwc);
f22f54f4
PZ		 1475 return;
1476 }
1477
ab608344 1478 if (unlikely(event->attr.precise_ip))
ef21f683 1479 intel_pmu_pebs_enable(event);
ca037701 1480
31fa58af 1481 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
f22f54f4
PZ		 1482}
1483
1484/*
1485 * Save and restart an expired event. Called by NMI contexts,
1486 * so it has to be careful about preempting normal event ops:
1487 */
de0428a7 1488int intel_pmu_save_and_restart(struct perf_event *event)
f22f54f4 1489{
cc2ad4ba 1490 x86_perf_event_update(event);
2dbf0116
AK		 1491 /*
1492 * For a checkpointed counter always reset back to 0. This
1493 * avoids a situation where the counter overflows, aborts the
1494 * transaction and is then set back to shortly before the
1495 * overflow, and overflows and aborts again.
1496 */
1497 if (unlikely(event_is_checkpointed(event))) {
1498 /* No race with NMIs because the counter should not be armed */
1499 wrmsrl(event->hw.event_base, 0);
1500 local64_set(&event->hw.prev_count, 0);
1501 }
cc2ad4ba 1502 return x86_perf_event_set_period(event);
f22f54f4
PZ		 1503}
1504
1505static void intel_pmu_reset(void)
1506{
0a3aee0d 1507 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
f22f54f4
PZ		 1508 unsigned long flags;
1509 int idx;
1510
948b1bb8 1511 if (!x86_pmu.num_counters)
f22f54f4
PZ		 1512 return;
1513
1514 local_irq_save(flags);
1515
c767a54b 1516 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
f22f54f4 1517
948b1bb8 1518 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
715c85b1
PA		 1519 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1520 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
f22f54f4 1521 }
948b1bb8 1522 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
715c85b1 1523 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
948b1bb8 1524
f22f54f4
PZ		 1525 if (ds)
1526 ds->bts_index = ds->bts_buffer_base;
1527
1528 local_irq_restore(flags);
1529}
1530
1531/*
1532 * This handler is triggered by the local APIC, so the APIC IRQ handling
1533 * rules apply:
1534 */
1535static int intel_pmu_handle_irq(struct pt_regs *regs)
1536{
1537 struct perf_sample_data data;
1538 struct cpu_hw_events *cpuc;
1539 int bit, loops;
2e556b5b 1540 u64 status;
b0b2072d 1541 int handled;
f22f54f4 1542
89cbc767 1543 cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4 1544
2bce5dac 1545 /*
72db5596
AK		 1546 * No known reason to not always do late ACK,
1547 * but just in case do it opt-in.
2bce5dac 1548 */
72db5596
AK		 1549 if (!x86_pmu.late_ack)
1550 apic_write(APIC_LVTPC, APIC_DM_NMI);
3fb2b8dd 1551 intel_pmu_disable_all();
b0b2072d 1552 handled = intel_pmu_drain_bts_buffer();
f22f54f4 1553 status = intel_pmu_get_status();
a3ef2229
MM		 1554 if (!status)
1555 goto done;
f22f54f4
PZ		 1556
1557 loops = 0;
1558again:
2e556b5b 1559 intel_pmu_ack_status(status);
f22f54f4 1560 if (++loops > 100) {
ae0def05
DH		 1561 static bool warned = false;
1562 if (!warned) {
1563 WARN(1, "perfevents: irq loop stuck!\n");
1564 perf_event_print_debug();
1565 warned = true;
1566 }
f22f54f4 1567 intel_pmu_reset();
3fb2b8dd 1568 goto done;
f22f54f4
PZ		 1569 }
1570
1571 inc_irq_stat(apic_perf_irqs);
ca037701 1572
caff2bef
PZ		 1573 intel_pmu_lbr_read();
1574
b292d7a1
HD		 1575 /*
1576 * CondChgd bit 63 doesn't mean any overflow status. Ignore
1577 * and clear the bit.
1578 */
1579 if (__test_and_clear_bit(63, (unsigned long *)&status)) {
1580 if (!status)
1581 goto done;
1582 }
1583
ca037701
PZ		 1584 /*
1585 * PEBS overflow sets bit 62 in the global status register
1586 */
de725dec
PZ		 1587 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1588 handled++;
ca037701 1589 x86_pmu.drain_pebs(regs);
de725dec 1590 }
ca037701 1591
2dbf0116 1592 /*
2b9e344d
PZ		 1593 * Checkpointed counters can lead to 'spurious' PMIs because the
1594 * rollback caused by the PMI will have cleared the overflow status
1595 * bit. Therefore always force probe these counters.
2dbf0116 1596 */
2b9e344d 1597 status |= cpuc->intel_cp_status;
2dbf0116 1598
984b3f57 1599 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
f22f54f4
PZ		 1600 struct perf_event *event = cpuc->events[bit];
1601
de725dec
PZ		 1602 handled++;
1603
f22f54f4
PZ		 1604 if (!test_bit(bit, cpuc->active_mask))
1605 continue;
1606
1607 if (!intel_pmu_save_and_restart(event))
1608 continue;
1609
fd0d000b 1610 perf_sample_data_init(&data, 0, event->hw.last_period);
f22f54f4 1611
60ce0fbd
SE		 1612 if (has_branch_stack(event))
1613 data.br_stack = &cpuc->lbr_stack;
1614
a8b0ca17 1615 if (perf_event_overflow(event, &data, regs))
a4eaf7f1 1616 x86_pmu_stop(event, 0);
f22f54f4
PZ		 1617 }
1618
f22f54f4
PZ		 1619 /*
1620 * Repeat if there is more work to be done:
1621 */
1622 status = intel_pmu_get_status();
1623 if (status)
1624 goto again;
1625
3fb2b8dd 1626done:
11164cd4 1627 intel_pmu_enable_all(0);
72db5596
AK		 1628 /*
1629 * Only unmask the NMI after the overflow counters
1630 * have been reset. This avoids spurious NMIs on
1631 * Haswell CPUs.
1632 */
1633 if (x86_pmu.late_ack)
1634 apic_write(APIC_LVTPC, APIC_DM_NMI);
de725dec 1635 return handled;
f22f54f4
PZ		 1636}
1637
f22f54f4 1638static struct event_constraint *
ca037701 1639intel_bts_constraints(struct perf_event *event)
f22f54f4 1640{
ca037701
PZ		 1641 struct hw_perf_event *hwc = &event->hw;
1642 unsigned int hw_event, bts_event;
f22f54f4 1643
18a073a3
PZ		 1644 if (event->attr.freq)
1645 return NULL;
1646
ca037701
PZ		 1647 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1648 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
f22f54f4 1649
ca037701 1650 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
f22f54f4 1651 return &bts_constraint;
ca037701 1652
f22f54f4
PZ		 1653 return NULL;
1654}
1655
5a425294 1656static int intel_alt_er(int idx)
b79e8941
PZ		 1657{
1658 if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
5a425294 1659 return idx;
b79e8941 1660
5a425294
PZ		 1661 if (idx == EXTRA_REG_RSP_0)
1662 return EXTRA_REG_RSP_1;
1663
1664 if (idx == EXTRA_REG_RSP_1)
1665 return EXTRA_REG_RSP_0;
1666
1667 return idx;
1668}
1669
1670static void intel_fixup_er(struct perf_event *event, int idx)
1671{
1672 event->hw.extra_reg.idx = idx;
1673
1674 if (idx == EXTRA_REG_RSP_0) {
b79e8941 1675 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
53ad0447 1676 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
b79e8941 1677 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
5a425294
PZ		 1678 } else if (idx == EXTRA_REG_RSP_1) {
1679 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
53ad0447 1680 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
5a425294 1681 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
b79e8941 1682 }
b79e8941
PZ		 1683}
1684
efc9f05d
SE		 1685/*
1686 * manage allocation of shared extra msr for certain events
1687 *
1688 * sharing can be:
1689 * per-cpu: to be shared between the various events on a single PMU
1690 * per-core: per-cpu + shared by HT threads
1691 */
a7e3ed1e 1692static struct event_constraint *
efc9f05d 1693__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
b36817e8
SE		 1694 struct perf_event *event,
1695 struct hw_perf_event_extra *reg)
a7e3ed1e 1696{
efc9f05d 1697 struct event_constraint *c = &emptyconstraint;
a7e3ed1e 1698 struct er_account *era;
cd8a38d3 1699 unsigned long flags;
5a425294 1700 int idx = reg->idx;
a7e3ed1e 1701
5a425294
PZ		 1702 /*
1703 * reg->alloc can be set due to existing state, so for fake cpuc we
1704 * need to ignore this, otherwise we might fail to allocate proper fake
1705 * state for this extra reg constraint. Also see the comment below.
1706 */
1707 if (reg->alloc && !cpuc->is_fake)
b36817e8 1708 return NULL; /* call x86_get_event_constraint() */
a7e3ed1e 1709
b79e8941 1710again:
5a425294 1711 era = &cpuc->shared_regs->regs[idx];
cd8a38d3
SE		 1712 /*
1713 * we use spin_lock_irqsave() to avoid lockdep issues when
1714 * passing a fake cpuc
1715 */
1716 raw_spin_lock_irqsave(&era->lock, flags);
efc9f05d
SE		 1717
1718 if (!atomic_read(&era->ref) || era->config == reg->config) {
1719
5a425294
PZ		 1720 /*
1721 * If its a fake cpuc -- as per validate_{group,event}() we
1722 * shouldn't touch event state and we can avoid doing so
1723 * since both will only call get_event_constraints() once
1724 * on each event, this avoids the need for reg->alloc.
1725 *
1726 * Not doing the ER fixup will only result in era->reg being
1727 * wrong, but since we won't actually try and program hardware
1728 * this isn't a problem either.
1729 */
1730 if (!cpuc->is_fake) {
1731 if (idx != reg->idx)
1732 intel_fixup_er(event, idx);
1733
1734 /*
1735 * x86_schedule_events() can call get_event_constraints()
1736 * multiple times on events in the case of incremental
1737 * scheduling(). reg->alloc ensures we only do the ER
1738 * allocation once.
1739 */
1740 reg->alloc = 1;
1741 }
1742
efc9f05d
SE		 1743 /* lock in msr value */
1744 era->config = reg->config;
1745 era->reg = reg->reg;
1746
1747 /* one more user */
1748 atomic_inc(&era->ref);
1749
a7e3ed1e 1750 /*
b36817e8
SE		 1751 * need to call x86_get_event_constraint()
1752 * to check if associated event has constraints
a7e3ed1e 1753 */
b36817e8 1754 c = NULL;
5a425294
PZ		 1755 } else {
1756 idx = intel_alt_er(idx);
1757 if (idx != reg->idx) {
1758 raw_spin_unlock_irqrestore(&era->lock, flags);
1759 goto again;
1760 }
a7e3ed1e 1761 }
cd8a38d3 1762 raw_spin_unlock_irqrestore(&era->lock, flags);
a7e3ed1e 1763
efc9f05d
SE		 1764 return c;
1765}
1766
1767static void
1768__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1769 struct hw_perf_event_extra *reg)
1770{
1771 struct er_account *era;
1772
1773 /*
5a425294
PZ		 1774 * Only put constraint if extra reg was actually allocated. Also takes
1775 * care of event which do not use an extra shared reg.
1776 *
1777 * Also, if this is a fake cpuc we shouldn't touch any event state
1778 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
1779 * either since it'll be thrown out.
efc9f05d 1780 */
5a425294 1781 if (!reg->alloc || cpuc->is_fake)
efc9f05d
SE		 1782 return;
1783
1784 era = &cpuc->shared_regs->regs[reg->idx];
1785
1786 /* one fewer user */
1787 atomic_dec(&era->ref);
1788
1789 /* allocate again next time */
1790 reg->alloc = 0;
1791}
1792
1793static struct event_constraint *
1794intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1795 struct perf_event *event)
1796{
b36817e8
SE		 1797 struct event_constraint *c = NULL, *d;
1798 struct hw_perf_event_extra *xreg, *breg;
1799
1800 xreg = &event->hw.extra_reg;
1801 if (xreg->idx != EXTRA_REG_NONE) {
1802 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
1803 if (c == &emptyconstraint)
1804 return c;
1805 }
1806 breg = &event->hw.branch_reg;
1807 if (breg->idx != EXTRA_REG_NONE) {
1808 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
1809 if (d == &emptyconstraint) {
1810 __intel_shared_reg_put_constraints(cpuc, xreg);
1811 c = d;
1812 }
1813 }
efc9f05d 1814 return c;
a7e3ed1e
AK		 1815}
1816
de0428a7
KW		 1817struct event_constraint *
1818x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1819{
1820 struct event_constraint *c;
1821
1822 if (x86_pmu.event_constraints) {
1823 for_each_event_constraint(c, x86_pmu.event_constraints) {
9fac2cf3 1824 if ((event->hw.config & c->cmask) == c->code) {
9fac2cf3 1825 event->hw.flags |= c->flags;
de0428a7 1826 return c;
9fac2cf3 1827 }
de0428a7
KW		 1828 }
1829 }
1830
1831 return &unconstrained;
1832}
1833
f22f54f4
PZ		 1834static struct event_constraint *
1835intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1836{
1837 struct event_constraint *c;
1838
ca037701
PZ		 1839 c = intel_bts_constraints(event);
1840 if (c)
1841 return c;
1842
1843 c = intel_pebs_constraints(event);
f22f54f4
PZ		 1844 if (c)
1845 return c;
1846
efc9f05d 1847 c = intel_shared_regs_constraints(cpuc, event);
a7e3ed1e
AK		 1848 if (c)
1849 return c;
1850
f22f54f4
PZ		 1851 return x86_get_event_constraints(cpuc, event);
1852}
1853
efc9f05d
SE		 1854static void
1855intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
a7e3ed1e
AK		 1856 struct perf_event *event)
1857{
efc9f05d 1858 struct hw_perf_event_extra *reg;
a7e3ed1e 1859
efc9f05d
SE		 1860 reg = &event->hw.extra_reg;
1861 if (reg->idx != EXTRA_REG_NONE)
1862 __intel_shared_reg_put_constraints(cpuc, reg);
b36817e8
SE		 1863
1864 reg = &event->hw.branch_reg;
1865 if (reg->idx != EXTRA_REG_NONE)
1866 __intel_shared_reg_put_constraints(cpuc, reg);
efc9f05d 1867}
a7e3ed1e 1868
efc9f05d
SE		 1869static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
1870 struct perf_event *event)
1871{
1872 intel_put_shared_regs_event_constraints(cpuc, event);
a7e3ed1e
AK		 1873}
1874
0780c927 1875static void intel_pebs_aliases_core2(struct perf_event *event)
b4cdc5c2 1876{
0780c927 1877 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
7639dae0
PZ		 1878 /*
1879 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1880 * (0x003c) so that we can use it with PEBS.
1881 *
1882 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1883 * PEBS capable. However we can use INST_RETIRED.ANY_P
1884 * (0x00c0), which is a PEBS capable event, to get the same
1885 * count.
1886 *
1887 * INST_RETIRED.ANY_P counts the number of cycles that retires
1888 * CNTMASK instructions. By setting CNTMASK to a value (16)
1889 * larger than the maximum number of instructions that can be
1890 * retired per cycle (4) and then inverting the condition, we
1891 * count all cycles that retire 16 or less instructions, which
1892 * is every cycle.
1893 *
1894 * Thereby we gain a PEBS capable cycle counter.
1895 */
f9b4eeb8
PZ		 1896 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
1897
0780c927
PZ		 1898 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1899 event->hw.config = alt_config;
1900 }
1901}
1902
1903static void intel_pebs_aliases_snb(struct perf_event *event)
1904{
1905 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1906 /*
1907 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1908 * (0x003c) so that we can use it with PEBS.
1909 *
1910 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1911 * PEBS capable. However we can use UOPS_RETIRED.ALL
1912 * (0x01c2), which is a PEBS capable event, to get the same
1913 * count.
1914 *
1915 * UOPS_RETIRED.ALL counts the number of cycles that retires
1916 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
1917 * larger than the maximum number of micro-ops that can be
1918 * retired per cycle (4) and then inverting the condition, we
1919 * count all cycles that retire 16 or less micro-ops, which
1920 * is every cycle.
1921 *
1922 * Thereby we gain a PEBS capable cycle counter.
1923 */
1924 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
7639dae0
PZ		 1925
1926 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1927 event->hw.config = alt_config;
1928 }
0780c927
PZ		 1929}
1930
1931static int intel_pmu_hw_config(struct perf_event *event)
1932{
1933 int ret = x86_pmu_hw_config(event);
1934
1935 if (ret)
1936 return ret;
1937
1938 if (event->attr.precise_ip && x86_pmu.pebs_aliases)
1939 x86_pmu.pebs_aliases(event);
7639dae0 1940
a46a2300 1941 if (needs_branch_stack(event)) {
60ce0fbd
SE		 1942 ret = intel_pmu_setup_lbr_filter(event);
1943 if (ret)
1944 return ret;
1945 }
1946
b4cdc5c2
PZ		 1947 if (event->attr.type != PERF_TYPE_RAW)
1948 return 0;
1949
1950 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
1951 return 0;
1952
1953 if (x86_pmu.version < 3)
1954 return -EINVAL;
1955
1956 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
1957 return -EACCES;
1958
1959 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
1960
1961 return 0;
1962}
1963
144d31e6
GN		 1964struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
1965{
1966 if (x86_pmu.guest_get_msrs)
1967 return x86_pmu.guest_get_msrs(nr);
1968 *nr = 0;
1969 return NULL;
1970}
1971EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
1972
1973static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
1974{
89cbc767 1975 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 1976 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1977
1978 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
1979 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
1980 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
26a4f3c0
GN		 1981 /*
1982 * If PMU counter has PEBS enabled it is not enough to disable counter
1983 * on a guest entry since PEBS memory write can overshoot guest entry
1984 * and corrupt guest memory. Disabling PEBS solves the problem.
1985 */
1986 arr[1].msr = MSR_IA32_PEBS_ENABLE;
1987 arr[1].host = cpuc->pebs_enabled;
1988 arr[1].guest = 0;
144d31e6 1989
26a4f3c0 1990 *nr = 2;
144d31e6
GN		 1991 return arr;
1992}
1993
1994static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
1995{
89cbc767 1996 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 1997 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1998 int idx;
1999
2000 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2001 struct perf_event *event = cpuc->events[idx];
2002
2003 arr[idx].msr = x86_pmu_config_addr(idx);
2004 arr[idx].host = arr[idx].guest = 0;
2005
2006 if (!test_bit(idx, cpuc->active_mask))
2007 continue;
2008
2009 arr[idx].host = arr[idx].guest =
2010 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
2011
2012 if (event->attr.exclude_host)
2013 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2014 else if (event->attr.exclude_guest)
2015 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2016 }
2017
2018 *nr = x86_pmu.num_counters;
2019 return arr;
2020}
2021
2022static void core_pmu_enable_event(struct perf_event *event)
2023{
2024 if (!event->attr.exclude_host)
2025 x86_pmu_enable_event(event);
2026}
2027
2028static void core_pmu_enable_all(int added)
2029{
89cbc767 2030 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 2031 int idx;
2032
2033 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2034 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
2035
2036 if (!test_bit(idx, cpuc->active_mask) ||
2037 cpuc->events[idx]->attr.exclude_host)
2038 continue;
2039
2040 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2041 }
2042}
2043
3a632cb2
AK		 2044static int hsw_hw_config(struct perf_event *event)
2045{
2046 int ret = intel_pmu_hw_config(event);
2047
2048 if (ret)
2049 return ret;
2050 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
2051 return 0;
2052 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
2053
2054 /*
2055 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
2056 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
2057 * this combination.
2058 */
2059 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
2060 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
2061 event->attr.precise_ip > 0))
2062 return -EOPNOTSUPP;
2063
2dbf0116
AK		 2064 if (event_is_checkpointed(event)) {
2065 /*
2066 * Sampling of checkpointed events can cause situations where
2067 * the CPU constantly aborts because of a overflow, which is
2068 * then checkpointed back and ignored. Forbid checkpointing
2069 * for sampling.
2070 *
2071 * But still allow a long sampling period, so that perf stat
2072 * from KVM works.
2073 */
2074 if (event->attr.sample_period > 0 &&
2075 event->attr.sample_period < 0x7fffffff)
2076 return -EOPNOTSUPP;
2077 }
3a632cb2
AK		 2078 return 0;
2079}
2080
2081static struct event_constraint counter2_constraint =
2082 EVENT_CONSTRAINT(0, 0x4, 0);
2083
2084static struct event_constraint *
2085hsw_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
2086{
2087 struct event_constraint *c = intel_get_event_constraints(cpuc, event);
2088
2089 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
2090 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
2091 if (c->idxmsk64 & (1U << 2))
2092 return &counter2_constraint;
2093 return &emptyconstraint;
2094 }
2095
2096 return c;
2097}
2098
641cc938
JO		 2099PMU_FORMAT_ATTR(event, "config:0-7" );
2100PMU_FORMAT_ATTR(umask, "config:8-15" );
2101PMU_FORMAT_ATTR(edge, "config:18" );
2102PMU_FORMAT_ATTR(pc, "config:19" );
2103PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
2104PMU_FORMAT_ATTR(inv, "config:23" );
2105PMU_FORMAT_ATTR(cmask, "config:24-31" );
3a632cb2
AK		 2106PMU_FORMAT_ATTR(in_tx, "config:32");
2107PMU_FORMAT_ATTR(in_tx_cp, "config:33");
641cc938
JO		 2108
2109static struct attribute *intel_arch_formats_attr[] = {
2110 &format_attr_event.attr,
2111 &format_attr_umask.attr,
2112 &format_attr_edge.attr,
2113 &format_attr_pc.attr,
2114 &format_attr_inv.attr,
2115 &format_attr_cmask.attr,
2116 NULL,
2117};
2118
0bf79d44
JO		 2119ssize_t intel_event_sysfs_show(char *page, u64 config)
2120{
2121 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
2122
2123 return x86_event_sysfs_show(page, config, event);
2124}
2125
caaa8be3 2126static __initconst const struct x86_pmu core_pmu = {
f22f54f4
PZ		 2127 .name = "core",
2128 .handle_irq = x86_pmu_handle_irq,
2129 .disable_all = x86_pmu_disable_all,
144d31e6
GN		 2130 .enable_all = core_pmu_enable_all,
2131 .enable = core_pmu_enable_event,
f22f54f4 2132 .disable = x86_pmu_disable_event,
b4cdc5c2 2133 .hw_config = x86_pmu_hw_config,
a072738e 2134 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 2135 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
2136 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
2137 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 2138 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
2139 .apic = 1,
2140 /*
2141 * Intel PMCs cannot be accessed sanely above 32 bit width,
2142 * so we install an artificial 1<<31 period regardless of
2143 * the generic event period:
2144 */
2145 .max_period = (1ULL << 31) - 1,
2146 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 2147 .put_event_constraints = intel_put_event_constraints,
f22f54f4 2148 .event_constraints = intel_core_event_constraints,
144d31e6 2149 .guest_get_msrs = core_guest_get_msrs,
641cc938 2150 .format_attrs = intel_arch_formats_attr,
0bf79d44 2151 .events_sysfs_show = intel_event_sysfs_show,
f22f54f4
PZ		 2152};
2153
de0428a7 2154struct intel_shared_regs *allocate_shared_regs(int cpu)
efc9f05d
SE		 2155{
2156 struct intel_shared_regs *regs;
2157 int i;
2158
2159 regs = kzalloc_node(sizeof(struct intel_shared_regs),
2160 GFP_KERNEL, cpu_to_node(cpu));
2161 if (regs) {
2162 /*
2163 * initialize the locks to keep lockdep happy
2164 */
2165 for (i = 0; i < EXTRA_REG_MAX; i++)
2166 raw_spin_lock_init(&regs->regs[i].lock);
2167
2168 regs->core_id = -1;
2169 }
2170 return regs;
2171}
2172
a7e3ed1e
AK		 2173static int intel_pmu_cpu_prepare(int cpu)
2174{
2175 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2176
b36817e8 2177 if (!(x86_pmu.extra_regs || x86_pmu.lbr_sel_map))
69092624
LM		 2178 return NOTIFY_OK;
2179
efc9f05d
SE		 2180 cpuc->shared_regs = allocate_shared_regs(cpu);
2181 if (!cpuc->shared_regs)
a7e3ed1e
AK		 2182 return NOTIFY_BAD;
2183
a7e3ed1e
AK		 2184 return NOTIFY_OK;
2185}
2186
74846d35
PZ		 2187static void intel_pmu_cpu_starting(int cpu)
2188{
a7e3ed1e
AK		 2189 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2190 int core_id = topology_core_id(cpu);
2191 int i;
2192
69092624
LM		 2193 init_debug_store_on_cpu(cpu);
2194 /*
2195 * Deal with CPUs that don't clear their LBRs on power-up.
2196 */
2197 intel_pmu_lbr_reset();
2198
b36817e8
SE		 2199 cpuc->lbr_sel = NULL;
2200
2201 if (!cpuc->shared_regs)
69092624
LM		 2202 return;
2203
b36817e8
SE		 2204 if (!(x86_pmu.er_flags & ERF_NO_HT_SHARING)) {
2205 for_each_cpu(i, topology_thread_cpumask(cpu)) {
2206 struct intel_shared_regs *pc;
a7e3ed1e 2207
b36817e8
SE		 2208 pc = per_cpu(cpu_hw_events, i).shared_regs;
2209 if (pc && pc->core_id == core_id) {
2210 cpuc->kfree_on_online = cpuc->shared_regs;
2211 cpuc->shared_regs = pc;
2212 break;
2213 }
a7e3ed1e 2214 }
b36817e8
SE		 2215 cpuc->shared_regs->core_id = core_id;
2216 cpuc->shared_regs->refcnt++;
a7e3ed1e
AK		 2217 }
2218
b36817e8
SE		 2219 if (x86_pmu.lbr_sel_map)
2220 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
74846d35
PZ		 2221}
2222
2223static void intel_pmu_cpu_dying(int cpu)
2224{
a7e3ed1e 2225 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
efc9f05d 2226 struct intel_shared_regs *pc;
a7e3ed1e 2227
efc9f05d 2228 pc = cpuc->shared_regs;
a7e3ed1e
AK		 2229 if (pc) {
2230 if (pc->core_id == -1 || --pc->refcnt == 0)
2231 kfree(pc);
efc9f05d 2232 cpuc->shared_regs = NULL;
a7e3ed1e
AK		 2233 }
2234
74846d35
PZ		 2235 fini_debug_store_on_cpu(cpu);
2236}
2237
641cc938
JO		 2238PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
2239
a63fcab4
SE		 2240PMU_FORMAT_ATTR(ldlat, "config1:0-15");
2241
641cc938
JO		 2242static struct attribute *intel_arch3_formats_attr[] = {
2243 &format_attr_event.attr,
2244 &format_attr_umask.attr,
2245 &format_attr_edge.attr,
2246 &format_attr_pc.attr,
2247 &format_attr_any.attr,
2248 &format_attr_inv.attr,
2249 &format_attr_cmask.attr,
3a632cb2
AK		 2250 &format_attr_in_tx.attr,
2251 &format_attr_in_tx_cp.attr,
641cc938
JO		 2252
2253 &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
a63fcab4 2254 &format_attr_ldlat.attr, /* PEBS load latency */
641cc938
JO		 2255 NULL,
2256};
2257
caaa8be3 2258static __initconst const struct x86_pmu intel_pmu = {
f22f54f4
PZ		 2259 .name = "Intel",
2260 .handle_irq = intel_pmu_handle_irq,
2261 .disable_all = intel_pmu_disable_all,
2262 .enable_all = intel_pmu_enable_all,
2263 .enable = intel_pmu_enable_event,
2264 .disable = intel_pmu_disable_event,
b4cdc5c2 2265 .hw_config = intel_pmu_hw_config,
a072738e 2266 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 2267 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
2268 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
2269 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 2270 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
2271 .apic = 1,
2272 /*
2273 * Intel PMCs cannot be accessed sanely above 32 bit width,
2274 * so we install an artificial 1<<31 period regardless of
2275 * the generic event period:
2276 */
2277 .max_period = (1ULL << 31) - 1,
3f6da390 2278 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 2279 .put_event_constraints = intel_put_event_constraints,
0780c927 2280 .pebs_aliases = intel_pebs_aliases_core2,
3f6da390 2281
641cc938 2282 .format_attrs = intel_arch3_formats_attr,
0bf79d44 2283 .events_sysfs_show = intel_event_sysfs_show,
641cc938 2284
a7e3ed1e 2285 .cpu_prepare = intel_pmu_cpu_prepare,
74846d35
PZ		 2286 .cpu_starting = intel_pmu_cpu_starting,
2287 .cpu_dying = intel_pmu_cpu_dying,
144d31e6 2288 .guest_get_msrs = intel_guest_get_msrs,
2a0ad3b3 2289 .sched_task = intel_pmu_lbr_sched_task,
f22f54f4
PZ		 2290};
2291
c1d6f42f 2292static __init void intel_clovertown_quirk(void)
3c44780b
PZ		 2293{
2294 /*
2295 * PEBS is unreliable due to:
2296 *
2297 * AJ67 - PEBS may experience CPL leaks
2298 * AJ68 - PEBS PMI may be delayed by one event
2299 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
2300 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
2301 *
2302 * AJ67 could be worked around by restricting the OS/USR flags.
2303 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
2304 *
2305 * AJ106 could possibly be worked around by not allowing LBR
2306 * usage from PEBS, including the fixup.
2307 * AJ68 could possibly be worked around by always programming
ec75a716 2308 * a pebs_event_reset[0] value and coping with the lost events.
3c44780b
PZ		 2309 *
2310 * But taken together it might just make sense to not enable PEBS on
2311 * these chips.
2312 */
c767a54b 2313 pr_warn("PEBS disabled due to CPU errata\n");
3c44780b
PZ		 2314 x86_pmu.pebs = 0;
2315 x86_pmu.pebs_constraints = NULL;
2316}
2317
c93dc84c
PZ		 2318static int intel_snb_pebs_broken(int cpu)
2319{
2320 u32 rev = UINT_MAX; /* default to broken for unknown models */
2321
2322 switch (cpu_data(cpu).x86_model) {
2323 case 42: /* SNB */
2324 rev = 0x28;
2325 break;
2326
2327 case 45: /* SNB-EP */
2328 switch (cpu_data(cpu).x86_mask) {
2329 case 6: rev = 0x618; break;
2330 case 7: rev = 0x70c; break;
2331 }
2332 }
2333
2334 return (cpu_data(cpu).microcode < rev);
2335}
2336
2337static void intel_snb_check_microcode(void)
2338{
2339 int pebs_broken = 0;
2340 int cpu;
2341
2342 get_online_cpus();
2343 for_each_online_cpu(cpu) {
2344 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
2345 break;
2346 }
2347 put_online_cpus();
2348
2349 if (pebs_broken == x86_pmu.pebs_broken)
2350 return;
2351
2352 /*
2353 * Serialized by the microcode lock..
2354 */
2355 if (x86_pmu.pebs_broken) {
2356 pr_info("PEBS enabled due to microcode update\n");
2357 x86_pmu.pebs_broken = 0;
2358 } else {
2359 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
2360 x86_pmu.pebs_broken = 1;
2361 }
2362}
2363
338b522c
KL		 2364/*
2365 * Under certain circumstances, access certain MSR may cause #GP.
2366 * The function tests if the input MSR can be safely accessed.
2367 */
2368static bool check_msr(unsigned long msr, u64 mask)
2369{
2370 u64 val_old, val_new, val_tmp;
2371
2372 /*
2373 * Read the current value, change it and read it back to see if it
2374 * matches, this is needed to detect certain hardware emulators
2375 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
2376 */
2377 if (rdmsrl_safe(msr, &val_old))
2378 return false;
2379
2380 /*
2381 * Only change the bits which can be updated by wrmsrl.
2382 */
2383 val_tmp = val_old ^ mask;
2384 if (wrmsrl_safe(msr, val_tmp) ||
2385 rdmsrl_safe(msr, &val_new))
2386 return false;
2387
2388 if (val_new != val_tmp)
2389 return false;
2390
2391 /* Here it's sure that the MSR can be safely accessed.
2392 * Restore the old value and return.
2393 */
2394 wrmsrl(msr, val_old);
2395
2396 return true;
2397}
2398
c1d6f42f 2399static __init void intel_sandybridge_quirk(void)
6a600a8b 2400{
c93dc84c
PZ		 2401 x86_pmu.check_microcode = intel_snb_check_microcode;
2402 intel_snb_check_microcode();
6a600a8b
PZ		 2403}
2404
c1d6f42f
PZ		 2405static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
2406 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
2407 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
2408 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
2409 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
2410 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
2411 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
2412 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
ffb871bc
GN		 2413};
2414
c1d6f42f
PZ		 2415static __init void intel_arch_events_quirk(void)
2416{
2417 int bit;
2418
2419 /* disable event that reported as not presend by cpuid */
2420 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
2421 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
c767a54b
JP		 2422 pr_warn("CPUID marked event: \'%s\' unavailable\n",
2423 intel_arch_events_map[bit].name);
c1d6f42f
PZ		 2424 }
2425}
2426
2427static __init void intel_nehalem_quirk(void)
2428{
2429 union cpuid10_ebx ebx;
2430
2431 ebx.full = x86_pmu.events_maskl;
2432 if (ebx.split.no_branch_misses_retired) {
2433 /*
2434 * Erratum AAJ80 detected, we work it around by using
2435 * the BR_MISP_EXEC.ANY event. This will over-count
2436 * branch-misses, but it's still much better than the
2437 * architectural event which is often completely bogus:
2438 */
2439 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
2440 ebx.split.no_branch_misses_retired = 0;
2441 x86_pmu.events_maskl = ebx.full;
c767a54b 2442 pr_info("CPU erratum AAJ80 worked around\n");
c1d6f42f
PZ		 2443 }
2444}
2445
7f2ee91f
IM		 2446EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
2447EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
f9134f36 2448
4b2c4f1f 2449/* Haswell special events */
7f2ee91f
IM		 2450EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
2451EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
2452EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
2453EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
2454EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
2455EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
2456EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
2457EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
2458EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
2459EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
2460EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
2461EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
4b2c4f1f 2462
f9134f36 2463static struct attribute *hsw_events_attrs[] = {
4b2c4f1f
AK		 2464 EVENT_PTR(tx_start),
2465 EVENT_PTR(tx_commit),
2466 EVENT_PTR(tx_abort),
2467 EVENT_PTR(tx_capacity),
2468 EVENT_PTR(tx_conflict),
2469 EVENT_PTR(el_start),
2470 EVENT_PTR(el_commit),
2471 EVENT_PTR(el_abort),
2472 EVENT_PTR(el_capacity),
2473 EVENT_PTR(el_conflict),
2474 EVENT_PTR(cycles_t),
2475 EVENT_PTR(cycles_ct),
f9134f36
AK		 2476 EVENT_PTR(mem_ld_hsw),
2477 EVENT_PTR(mem_st_hsw),
2478 NULL
2479};
2480
de0428a7 2481__init int intel_pmu_init(void)
f22f54f4
PZ		 2482{
2483 union cpuid10_edx edx;
2484 union cpuid10_eax eax;
ffb871bc 2485 union cpuid10_ebx ebx;
a1eac7ac 2486 struct event_constraint *c;
f22f54f4 2487 unsigned int unused;
338b522c
KL		 2488 struct extra_reg *er;
2489 int version, i;
f22f54f4
PZ		 2490
2491 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
a072738e
CG		 2492 switch (boot_cpu_data.x86) {
2493 case 0x6:
2494 return p6_pmu_init();
e717bf4e
VW		 2495 case 0xb:
2496 return knc_pmu_init();
a072738e
CG		 2497 case 0xf:
2498 return p4_pmu_init();
2499 }
f22f54f4 2500 return -ENODEV;
f22f54f4
PZ		 2501 }
2502
2503 /*
2504 * Check whether the Architectural PerfMon supports
2505 * Branch Misses Retired hw_event or not.
2506 */
ffb871bc
GN		 2507 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
2508 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
f22f54f4
PZ		 2509 return -ENODEV;
2510
2511 version = eax.split.version_id;
2512 if (version < 2)
2513 x86_pmu = core_pmu;
2514 else
2515 x86_pmu = intel_pmu;
2516
2517 x86_pmu.version = version;
948b1bb8
RR		 2518 x86_pmu.num_counters = eax.split.num_counters;
2519 x86_pmu.cntval_bits = eax.split.bit_width;
2520 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
f22f54f4 2521
c1d6f42f
PZ		 2522 x86_pmu.events_maskl = ebx.full;
2523 x86_pmu.events_mask_len = eax.split.mask_length;
2524
70ab7003
AK		 2525 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
2526
f22f54f4
PZ		 2527 /*
2528 * Quirk: v2 perfmon does not report fixed-purpose events, so
2529 * assume at least 3 events:
2530 */
2531 if (version > 1)
948b1bb8 2532 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
f22f54f4 2533
c9b08884 2534 if (boot_cpu_has(X86_FEATURE_PDCM)) {
8db909a7
PZ		 2535 u64 capabilities;
2536
2537 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
2538 x86_pmu.intel_cap.capabilities = capabilities;
2539 }
2540
ca037701
PZ		 2541 intel_ds_init();
2542
c1d6f42f
PZ		 2543 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
2544
f22f54f4
PZ		 2545 /*
2546 * Install the hw-cache-events table:
2547 */
2548 switch (boot_cpu_data.x86_model) {
0f7c29ce 2549 case 14: /* 65nm Core "Yonah" */
f22f54f4
PZ		 2550 pr_cont("Core events, ");
2551 break;
2552
0f7c29ce 2553 case 15: /* 65nm Core2 "Merom" */
c1d6f42f 2554 x86_add_quirk(intel_clovertown_quirk);
0f7c29ce
PZ		 2555 case 22: /* 65nm Core2 "Merom-L" */
2556 case 23: /* 45nm Core2 "Penryn" */
2557 case 29: /* 45nm Core2 "Dunnington (MP) */
f22f54f4
PZ		 2558 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
2559 sizeof(hw_cache_event_ids));
2560
caff2bef
PZ		 2561 intel_pmu_lbr_init_core();
2562
f22f54f4 2563 x86_pmu.event_constraints = intel_core2_event_constraints;
17e31629 2564 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
f22f54f4
PZ		 2565 pr_cont("Core2 events, ");
2566 break;
2567
0f7c29ce
PZ		 2568 case 30: /* 45nm Nehalem */
2569 case 26: /* 45nm Nehalem-EP */
2570 case 46: /* 45nm Nehalem-EX */
f22f54f4
PZ		 2571 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
2572 sizeof(hw_cache_event_ids));
e994d7d2
AK		 2573 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2574 sizeof(hw_cache_extra_regs));
f22f54f4 2575
caff2bef
PZ		 2576 intel_pmu_lbr_init_nhm();
2577
f22f54f4 2578 x86_pmu.event_constraints = intel_nehalem_event_constraints;
17e31629 2579 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
11164cd4 2580 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
a7e3ed1e 2581 x86_pmu.extra_regs = intel_nehalem_extra_regs;
ec75a716 2582
f20093ee
SE		 2583 x86_pmu.cpu_events = nhm_events_attrs;
2584
91fc4cc0 2585 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 2586 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2587 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
91fc4cc0 2588 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 2589 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2590 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
94403f88 2591
c1d6f42f 2592 x86_add_quirk(intel_nehalem_quirk);
ec75a716 2593
11164cd4 2594 pr_cont("Nehalem events, ");
f22f54f4 2595 break;
caff2bef 2596
0f7c29ce
PZ		 2597 case 28: /* 45nm Atom "Pineview" */
2598 case 38: /* 45nm Atom "Lincroft" */
2599 case 39: /* 32nm Atom "Penwell" */
2600 case 53: /* 32nm Atom "Cloverview" */
2601 case 54: /* 32nm Atom "Cedarview" */
f22f54f4
PZ		 2602 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
2603 sizeof(hw_cache_event_ids));
2604
caff2bef
PZ		 2605 intel_pmu_lbr_init_atom();
2606
f22f54f4 2607 x86_pmu.event_constraints = intel_gen_event_constraints;
17e31629 2608 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
f22f54f4
PZ		 2609 pr_cont("Atom events, ");
2610 break;
2611
0f7c29ce 2612 case 55: /* 22nm Atom "Silvermont" */
ef454cae 2613 case 76: /* 14nm Atom "Airmont" */
0f7c29ce 2614 case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
1fa64180
YZ		 2615 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
2616 sizeof(hw_cache_event_ids));
2617 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
2618 sizeof(hw_cache_extra_regs));
2619
2620 intel_pmu_lbr_init_atom();
2621
2622 x86_pmu.event_constraints = intel_slm_event_constraints;
2623 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
2624 x86_pmu.extra_regs = intel_slm_extra_regs;
2625 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2626 pr_cont("Silvermont events, ");
2627 break;
2628
0f7c29ce
PZ		 2629 case 37: /* 32nm Westmere */
2630 case 44: /* 32nm Westmere-EP */
2631 case 47: /* 32nm Westmere-EX */
f22f54f4
PZ		 2632 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
2633 sizeof(hw_cache_event_ids));
e994d7d2
AK		 2634 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2635 sizeof(hw_cache_extra_regs));
f22f54f4 2636
caff2bef
PZ		 2637 intel_pmu_lbr_init_nhm();
2638
f22f54f4 2639 x86_pmu.event_constraints = intel_westmere_event_constraints;
40b91cd1 2640 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
17e31629 2641 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
a7e3ed1e 2642 x86_pmu.extra_regs = intel_westmere_extra_regs;
b79e8941 2643 x86_pmu.er_flags |= ERF_HAS_RSP_1;
30112039 2644
f20093ee
SE		 2645 x86_pmu.cpu_events = nhm_events_attrs;
2646
30112039 2647 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 2648 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2649 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
30112039 2650 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 2651 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2652 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
30112039 2653
f22f54f4
PZ		 2654 pr_cont("Westmere events, ");
2655 break;
b622d644 2656
0f7c29ce
PZ		 2657 case 42: /* 32nm SandyBridge */
2658 case 45: /* 32nm SandyBridge-E/EN/EP */
47a8863d 2659 x86_add_quirk(intel_sandybridge_quirk);
b06b3d49
LM		 2660 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2661 sizeof(hw_cache_event_ids));
74e6543f
YZ		 2662 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2663 sizeof(hw_cache_extra_regs));
b06b3d49 2664
c5cc2cd9 2665 intel_pmu_lbr_init_snb();
b06b3d49
LM		 2666
2667 x86_pmu.event_constraints = intel_snb_event_constraints;
de0428a7 2668 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
0780c927 2669 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
f1923820
SE		 2670 if (boot_cpu_data.x86_model == 45)
2671 x86_pmu.extra_regs = intel_snbep_extra_regs;
2672 else
2673 x86_pmu.extra_regs = intel_snb_extra_regs;
ee89cbc2 2674 /* all extra regs are per-cpu when HT is on */
b79e8941
PZ		 2675 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2676 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
e04d1b23 2677
f20093ee
SE		 2678 x86_pmu.cpu_events = snb_events_attrs;
2679
e04d1b23 2680 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
f9b4eeb8
PZ		 2681 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2682 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 2683 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
f9b4eeb8
PZ		 2684 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2685 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 2686
b06b3d49
LM		 2687 pr_cont("SandyBridge events, ");
2688 break;
0f7c29ce
PZ		 2689
2690 case 58: /* 22nm IvyBridge */
2691 case 62: /* 22nm IvyBridge-EP/EX */
20a36e39
SE		 2692 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2693 sizeof(hw_cache_event_ids));
1996388e
VW		 2694 /* dTLB-load-misses on IVB is different than SNB */
2695 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
2696
20a36e39
SE		 2697 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2698 sizeof(hw_cache_extra_regs));
2699
2700 intel_pmu_lbr_init_snb();
2701
69943182 2702 x86_pmu.event_constraints = intel_ivb_event_constraints;
20a36e39
SE		 2703 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
2704 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
f1923820
SE		 2705 if (boot_cpu_data.x86_model == 62)
2706 x86_pmu.extra_regs = intel_snbep_extra_regs;
2707 else
2708 x86_pmu.extra_regs = intel_snb_extra_regs;
20a36e39
SE		 2709 /* all extra regs are per-cpu when HT is on */
2710 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2711 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2712
f20093ee
SE		 2713 x86_pmu.cpu_events = snb_events_attrs;
2714
20a36e39
SE		 2715 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
2716 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2717 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2718
2719 pr_cont("IvyBridge events, ");
2720 break;
2721
b06b3d49 2722
d86c8eaf
AK		 2723 case 60: /* 22nm Haswell Core */
2724 case 63: /* 22nm Haswell Server */
2725 case 69: /* 22nm Haswell ULT */
2726 case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
72db5596 2727 x86_pmu.late_ack = true;
0f1b5ca2
AK		 2728 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
2729 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3a632cb2 2730
e9d7f7cd 2731 intel_pmu_lbr_init_hsw();
3a632cb2
AK		 2732
2733 x86_pmu.event_constraints = intel_hsw_event_constraints;
3044318f 2734 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
36bbb2f2 2735 x86_pmu.extra_regs = intel_snbep_extra_regs;
3044318f 2736 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3a632cb2
AK		 2737 /* all extra regs are per-cpu when HT is on */
2738 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2739 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2740
2741 x86_pmu.hw_config = hsw_hw_config;
2742 x86_pmu.get_event_constraints = hsw_get_event_constraints;
f9134f36 2743 x86_pmu.cpu_events = hsw_events_attrs;
b7af41a1 2744 x86_pmu.lbr_double_abort = true;
3a632cb2
AK		 2745 pr_cont("Haswell events, ");
2746 break;
2747
91f1b705
AK		 2748 case 61: /* 14nm Broadwell Core-M */
2749 case 86: /* 14nm Broadwell Xeon D */
2750 x86_pmu.late_ack = true;
2751 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
2752 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
2753
2754 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
2755 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
2756 BDW_L3_MISS|HSW_SNOOP_DRAM;
2757 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
2758 HSW_SNOOP_DRAM;
2759 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
2760 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
2761 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
2762 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
2763
2764 intel_pmu_lbr_init_snb();
2765
2766 x86_pmu.event_constraints = intel_bdw_event_constraints;
2767 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
2768 x86_pmu.extra_regs = intel_snbep_extra_regs;
2769 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
2770 /* all extra regs are per-cpu when HT is on */
2771 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2772 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2773
2774 x86_pmu.hw_config = hsw_hw_config;
2775 x86_pmu.get_event_constraints = hsw_get_event_constraints;
2776 x86_pmu.cpu_events = hsw_events_attrs;
2777 pr_cont("Broadwell events, ");
2778 break;
2779
f22f54f4 2780 default:
0af3ac1f
AK		 2781 switch (x86_pmu.version) {
2782 case 1:
2783 x86_pmu.event_constraints = intel_v1_event_constraints;
2784 pr_cont("generic architected perfmon v1, ");
2785 break;
2786 default:
2787 /*
2788 * default constraints for v2 and up
2789 */
2790 x86_pmu.event_constraints = intel_gen_event_constraints;
2791 pr_cont("generic architected perfmon, ");
2792 break;
2793 }
f22f54f4 2794 }
ffb871bc 2795
a1eac7ac
RR		 2796 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
2797 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
2798 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
2799 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
2800 }
2801 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
2802
2803 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
2804 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
2805 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
2806 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
2807 }
2808
2809 x86_pmu.intel_ctrl |=
2810 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
2811
2812 if (x86_pmu.event_constraints) {
2813 /*
2814 * event on fixed counter2 (REF_CYCLES) only works on this
2815 * counter, so do not extend mask to generic counters
2816 */
2817 for_each_event_constraint(c, x86_pmu.event_constraints) {
3a632cb2 2818 if (c->cmask != FIXED_EVENT_FLAGS
a1eac7ac
RR		 2819 || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) {
2820 continue;
2821 }
2822
2823 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
2824 c->weight += x86_pmu.num_counters;
2825 }
2826 }
2827
338b522c
KL		 2828 /*
2829 * Access LBR MSR may cause #GP under certain circumstances.
2830 * E.g. KVM doesn't support LBR MSR
2831 * Check all LBT MSR here.
2832 * Disable LBR access if any LBR MSRs can not be accessed.
2833 */
2834 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
2835 x86_pmu.lbr_nr = 0;
2836 for (i = 0; i < x86_pmu.lbr_nr; i++) {
2837 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
2838 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
2839 x86_pmu.lbr_nr = 0;
2840 }
2841
2842 /*
2843 * Access extra MSR may cause #GP under certain circumstances.
2844 * E.g. KVM doesn't support offcore event
2845 * Check all extra_regs here.
2846 */
2847 if (x86_pmu.extra_regs) {
2848 for (er = x86_pmu.extra_regs; er->msr; er++) {
2849 er->extra_msr_access = check_msr(er->msr, 0x1ffUL);
2850 /* Disable LBR select mapping */
2851 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
2852 x86_pmu.lbr_sel_map = NULL;
2853 }
2854 }
2855
069e0c3c
AK		 2856 /* Support full width counters using alternative MSR range */
2857 if (x86_pmu.intel_cap.full_width_write) {
2858 x86_pmu.max_period = x86_pmu.cntval_mask;
2859 x86_pmu.perfctr = MSR_IA32_PMC0;
2860 pr_cont("full-width counters, ");
2861 }
2862
f22f54f4
PZ		 2863 return 0;
2864}
Linux kernel - Deliverables
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