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KVM: convert io_bus to SRCU
[deliverable/linux.git] / arch / x86 / kvm / mmu.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 *
11 * Authors:
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
14 *
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
17 *
18 */
e495606d 19
1d737c8a 20#include "mmu.h"
6de4f3ad 21#include "kvm_cache_regs.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732
AK		 24#include <linux/types.h>
25#include <linux/string.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
28#include <linux/module.h>
448353ca 29#include <linux/swap.h>
05da4558 30#include <linux/hugetlb.h>
2f333bcb 31#include <linux/compiler.h>
bc6678a3 32#include <linux/srcu.h>
6aa8b732 33
e495606d
AK		 34#include <asm/page.h>
35#include <asm/cmpxchg.h>
4e542370 36#include <asm/io.h>
13673a90 37#include <asm/vmx.h>
6aa8b732 38
18552672
JR		 39/*
40 * When setting this variable to true it enables Two-Dimensional-Paging
41 * where the hardware walks 2 page tables:
42 * 1. the guest-virtual to guest-physical
43 * 2. while doing 1. it walks guest-physical to host-physical
44 * If the hardware supports that we don't need to do shadow paging.
45 */
2f333bcb 46bool tdp_enabled = false;
18552672 47
37a7d8b0
AK		 48#undef MMU_DEBUG
49
50#undef AUDIT
51
52#ifdef AUDIT
53static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg);
54#else
55static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {}
56#endif
57
58#ifdef MMU_DEBUG
59
60#define pgprintk(x...) do { if (dbg) printk(x); } while (0)
61#define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
62
63#else
64
65#define pgprintk(x...) do { } while (0)
66#define rmap_printk(x...) do { } while (0)
67
68#endif
69
70#if defined(MMU_DEBUG) || defined(AUDIT)
6ada8cca
AK		 71static int dbg = 0;
72module_param(dbg, bool, 0644);
37a7d8b0 73#endif
6aa8b732 74
582801a9
MT		 75static int oos_shadow = 1;
76module_param(oos_shadow, bool, 0644);
77
d6c69ee9
YD		 78#ifndef MMU_DEBUG
79#define ASSERT(x) do { } while (0)
80#else
6aa8b732
AK		 81#define ASSERT(x) \
82 if (!(x)) { \
83 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
84 __FILE__, __LINE__, #x); \
85 }
d6c69ee9 86#endif
6aa8b732 87
6aa8b732
AK		 88#define PT_FIRST_AVAIL_BITS_SHIFT 9
89#define PT64_SECOND_AVAIL_BITS_SHIFT 52
90
6aa8b732
AK		 91#define VALID_PAGE(x) ((x) != INVALID_PAGE)
92
93#define PT64_LEVEL_BITS 9
94
95#define PT64_LEVEL_SHIFT(level) \
d77c26fc 96 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
6aa8b732
AK		 97
98#define PT64_LEVEL_MASK(level) \
99 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
100
101#define PT64_INDEX(address, level)\
102 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
103
104
105#define PT32_LEVEL_BITS 10
106
107#define PT32_LEVEL_SHIFT(level) \
d77c26fc 108 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
6aa8b732
AK		 109
110#define PT32_LEVEL_MASK(level) \
111 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
e04da980
JR		 112#define PT32_LVL_OFFSET_MASK(level) \
113 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
114 * PT32_LEVEL_BITS))) - 1))
6aa8b732
AK		 115
116#define PT32_INDEX(address, level)\
117 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
118
119
27aba766 120#define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
6aa8b732
AK		 121#define PT64_DIR_BASE_ADDR_MASK \
122 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
e04da980
JR		 123#define PT64_LVL_ADDR_MASK(level) \
124 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
125 * PT64_LEVEL_BITS))) - 1))
126#define PT64_LVL_OFFSET_MASK(level) \
127 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
128 * PT64_LEVEL_BITS))) - 1))
6aa8b732
AK		 129
130#define PT32_BASE_ADDR_MASK PAGE_MASK
131#define PT32_DIR_BASE_ADDR_MASK \
132 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
e04da980
JR		 133#define PT32_LVL_ADDR_MASK(level) \
134 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
135 * PT32_LEVEL_BITS))) - 1))
6aa8b732 136
79539cec
AK		 137#define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
138 | PT64_NX_MASK)
6aa8b732
AK		 139
140#define PFERR_PRESENT_MASK (1U << 0)
141#define PFERR_WRITE_MASK (1U << 1)
142#define PFERR_USER_MASK (1U << 2)
82725b20 143#define PFERR_RSVD_MASK (1U << 3)
73b1087e 144#define PFERR_FETCH_MASK (1U << 4)
6aa8b732 145
e04da980 146#define PT_PDPE_LEVEL 3
6aa8b732
AK		 147#define PT_DIRECTORY_LEVEL 2
148#define PT_PAGE_TABLE_LEVEL 1
149
cd4a4e53
AK		 150#define RMAP_EXT 4
151
fe135d2c
AK		 152#define ACC_EXEC_MASK 1
153#define ACC_WRITE_MASK PT_WRITABLE_MASK
154#define ACC_USER_MASK PT_USER_MASK
155#define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
156
07420171
AK		 157#define CREATE_TRACE_POINTS
158#include "mmutrace.h"
159
1403283a
IE		 160#define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
161
135f8c2b
AK		 162#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
163
cd4a4e53 164struct kvm_rmap_desc {
d555c333 165 u64 *sptes[RMAP_EXT];
cd4a4e53
AK		 166 struct kvm_rmap_desc *more;
167};
168
2d11123a
AK		 169struct kvm_shadow_walk_iterator {
170 u64 addr;
171 hpa_t shadow_addr;
172 int level;
173 u64 *sptep;
174 unsigned index;
175};
176
177#define for_each_shadow_entry(_vcpu, _addr, _walker) \
178 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
179 shadow_walk_okay(&(_walker)); \
180 shadow_walk_next(&(_walker)))
181
182
4731d4c7
MT		 183struct kvm_unsync_walk {
184 int (*entry) (struct kvm_mmu_page *sp, struct kvm_unsync_walk *walk);
185};
186
ad8cfbe3
MT		 187typedef int (*mmu_parent_walk_fn) (struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp);
188
b5a33a75
AK		 189static struct kmem_cache *pte_chain_cache;
190static struct kmem_cache *rmap_desc_cache;
d3d25b04 191static struct kmem_cache *mmu_page_header_cache;
b5a33a75 192
c7addb90
AK		 193static u64 __read_mostly shadow_trap_nonpresent_pte;
194static u64 __read_mostly shadow_notrap_nonpresent_pte;
7b52345e
SY		 195static u64 __read_mostly shadow_base_present_pte;
196static u64 __read_mostly shadow_nx_mask;
197static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
198static u64 __read_mostly shadow_user_mask;
199static u64 __read_mostly shadow_accessed_mask;
200static u64 __read_mostly shadow_dirty_mask;
c7addb90 201
82725b20
DE		 202static inline u64 rsvd_bits(int s, int e)
203{
204 return ((1ULL << (e - s + 1)) - 1) << s;
205}
206
c7addb90
AK		 207void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
208{
209 shadow_trap_nonpresent_pte = trap_pte;
210 shadow_notrap_nonpresent_pte = notrap_pte;
211}
212EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
213
7b52345e
SY		 214void kvm_mmu_set_base_ptes(u64 base_pte)
215{
216 shadow_base_present_pte = base_pte;
217}
218EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes);
219
220void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
4b12f0de 221 u64 dirty_mask, u64 nx_mask, u64 x_mask)
7b52345e
SY		 222{
223 shadow_user_mask = user_mask;
224 shadow_accessed_mask = accessed_mask;
225 shadow_dirty_mask = dirty_mask;
226 shadow_nx_mask = nx_mask;
227 shadow_x_mask = x_mask;
228}
229EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
230
6aa8b732
AK		 231static int is_write_protection(struct kvm_vcpu *vcpu)
232{
ad312c7c 233 return vcpu->arch.cr0 & X86_CR0_WP;
6aa8b732
AK		 234}
235
236static int is_cpuid_PSE36(void)
237{
238 return 1;
239}
240
73b1087e
AK		 241static int is_nx(struct kvm_vcpu *vcpu)
242{
ad312c7c 243 return vcpu->arch.shadow_efer & EFER_NX;
73b1087e
AK		 244}
245
c7addb90
AK		 246static int is_shadow_present_pte(u64 pte)
247{
c7addb90
AK		 248 return pte != shadow_trap_nonpresent_pte
249 && pte != shadow_notrap_nonpresent_pte;
250}
251
05da4558
MT		 252static int is_large_pte(u64 pte)
253{
254 return pte & PT_PAGE_SIZE_MASK;
255}
256
6aa8b732
AK		 257static int is_writeble_pte(unsigned long pte)
258{
259 return pte & PT_WRITABLE_MASK;
260}
261
43a3795a 262static int is_dirty_gpte(unsigned long pte)
e3c5e7ec 263{
439e218a 264 return pte & PT_DIRTY_MASK;
e3c5e7ec
AK		 265}
266
43a3795a 267static int is_rmap_spte(u64 pte)
cd4a4e53 268{
4b1a80fa 269 return is_shadow_present_pte(pte);
cd4a4e53
AK		 270}
271
776e6633
MT		 272static int is_last_spte(u64 pte, int level)
273{
274 if (level == PT_PAGE_TABLE_LEVEL)
275 return 1;
852e3c19 276 if (is_large_pte(pte))
776e6633
MT		 277 return 1;
278 return 0;
279}
280
35149e21 281static pfn_t spte_to_pfn(u64 pte)
0b49ea86 282{
35149e21 283 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
0b49ea86
AK		 284}
285
da928521
AK		 286static gfn_t pse36_gfn_delta(u32 gpte)
287{
288 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
289
290 return (gpte & PT32_DIR_PSE36_MASK) << shift;
291}
292
d555c333 293static void __set_spte(u64 *sptep, u64 spte)
e663ee64
AK		 294{
295#ifdef CONFIG_X86_64
296 set_64bit((unsigned long *)sptep, spte);
297#else
298 set_64bit((unsigned long long *)sptep, spte);
299#endif
300}
301
e2dec939 302static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
2e3e5882 303 struct kmem_cache *base_cache, int min)
714b93da
AK		 304{
305 void *obj;
306
307 if (cache->nobjs >= min)
e2dec939 308 return 0;
714b93da 309 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 310 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
714b93da 311 if (!obj)
e2dec939 312 return -ENOMEM;
714b93da
AK		 313 cache->objects[cache->nobjs++] = obj;
314 }
e2dec939 315 return 0;
714b93da
AK		 316}
317
318static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc)
319{
320 while (mc->nobjs)
321 kfree(mc->objects[--mc->nobjs]);
322}
323
c1158e63 324static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
2e3e5882 325 int min)
c1158e63
AK		 326{
327 struct page *page;
328
329 if (cache->nobjs >= min)
330 return 0;
331 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 332 page = alloc_page(GFP_KERNEL);
c1158e63
AK		 333 if (!page)
334 return -ENOMEM;
335 set_page_private(page, 0);
336 cache->objects[cache->nobjs++] = page_address(page);
337 }
338 return 0;
339}
340
341static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
342{
343 while (mc->nobjs)
c4d198d5 344 free_page((unsigned long)mc->objects[--mc->nobjs]);
c1158e63
AK		 345}
346
2e3e5882 347static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
714b93da 348{
e2dec939
AK		 349 int r;
350
ad312c7c 351 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache,
2e3e5882 352 pte_chain_cache, 4);
e2dec939
AK		 353 if (r)
354 goto out;
ad312c7c 355 r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache,
c41ef344 356 rmap_desc_cache, 4);
d3d25b04
AK		 357 if (r)
358 goto out;
ad312c7c 359 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
d3d25b04
AK		 360 if (r)
361 goto out;
ad312c7c 362 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
2e3e5882 363 mmu_page_header_cache, 4);
e2dec939
AK		 364out:
365 return r;
714b93da
AK		 366}
367
368static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
369{
ad312c7c
ZX		 370 mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache);
371 mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache);
372 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
373 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
714b93da
AK		 374}
375
376static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
377 size_t size)
378{
379 void *p;
380
381 BUG_ON(!mc->nobjs);
382 p = mc->objects[--mc->nobjs];
714b93da
AK		 383 return p;
384}
385
714b93da
AK		 386static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
387{
ad312c7c 388 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache,
714b93da
AK		 389 sizeof(struct kvm_pte_chain));
390}
391
90cb0529 392static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
714b93da 393{
90cb0529 394 kfree(pc);
714b93da
AK		 395}
396
397static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
398{
ad312c7c 399 return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache,
714b93da
AK		 400 sizeof(struct kvm_rmap_desc));
401}
402
90cb0529 403static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
714b93da 404{
90cb0529 405 kfree(rd);
714b93da
AK		 406}
407
05da4558
MT		 408/*
409 * Return the pointer to the largepage write count for a given
410 * gfn, handling slots that are not large page aligned.
411 */
d25797b2
JR		 412static int *slot_largepage_idx(gfn_t gfn,
413 struct kvm_memory_slot *slot,
414 int level)
05da4558
MT		 415{
416 unsigned long idx;
417
d25797b2
JR		 418 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
419 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
420 return &slot->lpage_info[level - 2][idx].write_count;
05da4558
MT		 421}
422
423static void account_shadowed(struct kvm *kvm, gfn_t gfn)
424{
d25797b2 425 struct kvm_memory_slot *slot;
05da4558 426 int *write_count;
d25797b2 427 int i;
05da4558 428
2843099f 429 gfn = unalias_gfn(kvm, gfn);
d25797b2
JR		 430
431 slot = gfn_to_memslot_unaliased(kvm, gfn);
432 for (i = PT_DIRECTORY_LEVEL;
433 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
434 write_count = slot_largepage_idx(gfn, slot, i);
435 *write_count += 1;
436 }
05da4558
MT		 437}
438
439static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
440{
d25797b2 441 struct kvm_memory_slot *slot;
05da4558 442 int *write_count;
d25797b2 443 int i;
05da4558 444
2843099f 445 gfn = unalias_gfn(kvm, gfn);
d25797b2
JR		 446 for (i = PT_DIRECTORY_LEVEL;
447 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
448 slot = gfn_to_memslot_unaliased(kvm, gfn);
449 write_count = slot_largepage_idx(gfn, slot, i);
450 *write_count -= 1;
451 WARN_ON(*write_count < 0);
452 }
05da4558
MT		 453}
454
d25797b2
JR		 455static int has_wrprotected_page(struct kvm *kvm,
456 gfn_t gfn,
457 int level)
05da4558 458{
2843099f 459 struct kvm_memory_slot *slot;
05da4558
MT		 460 int *largepage_idx;
461
2843099f
IE		 462 gfn = unalias_gfn(kvm, gfn);
463 slot = gfn_to_memslot_unaliased(kvm, gfn);
05da4558 464 if (slot) {
d25797b2 465 largepage_idx = slot_largepage_idx(gfn, slot, level);
05da4558
MT		 466 return *largepage_idx;
467 }
468
469 return 1;
470}
471
d25797b2 472static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
05da4558 473{
d25797b2 474 unsigned long page_size = PAGE_SIZE;
05da4558
MT		 475 struct vm_area_struct *vma;
476 unsigned long addr;
d25797b2 477 int i, ret = 0;
05da4558
MT		 478
479 addr = gfn_to_hva(kvm, gfn);
480 if (kvm_is_error_hva(addr))
82b7005f 481 return PT_PAGE_TABLE_LEVEL;
05da4558 482
4c2155ce 483 down_read(&current->mm->mmap_sem);
05da4558 484 vma = find_vma(current->mm, addr);
d25797b2
JR		 485 if (!vma)
486 goto out;
487
488 page_size = vma_kernel_pagesize(vma);
489
490out:
4c2155ce 491 up_read(&current->mm->mmap_sem);
05da4558 492
d25797b2
JR		 493 for (i = PT_PAGE_TABLE_LEVEL;
494 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
495 if (page_size >= KVM_HPAGE_SIZE(i))
496 ret = i;
497 else
498 break;
499 }
500
4c2155ce 501 return ret;
05da4558
MT		 502}
503
d25797b2 504static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
05da4558
MT		 505{
506 struct kvm_memory_slot *slot;
d25797b2
JR		 507 int host_level;
508 int level = PT_PAGE_TABLE_LEVEL;
05da4558
MT		 509
510 slot = gfn_to_memslot(vcpu->kvm, large_gfn);
511 if (slot && slot->dirty_bitmap)
d25797b2 512 return PT_PAGE_TABLE_LEVEL;
05da4558 513
d25797b2
JR		 514 host_level = host_mapping_level(vcpu->kvm, large_gfn);
515
516 if (host_level == PT_PAGE_TABLE_LEVEL)
517 return host_level;
518
82b7005f 519 for (level = PT_DIRECTORY_LEVEL; level <= host_level; ++level)
d25797b2
JR		 520 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
521 break;
d25797b2
JR		 522
523 return level - 1;
05da4558
MT		 524}
525
290fc38d
IE		 526/*
527 * Take gfn and return the reverse mapping to it.
528 * Note: gfn must be unaliased before this function get called
529 */
530
44ad9944 531static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
290fc38d
IE		 532{
533 struct kvm_memory_slot *slot;
05da4558 534 unsigned long idx;
290fc38d
IE		 535
536 slot = gfn_to_memslot(kvm, gfn);
44ad9944 537 if (likely(level == PT_PAGE_TABLE_LEVEL))
05da4558
MT		 538 return &slot->rmap[gfn - slot->base_gfn];
539
44ad9944
JR		 540 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
541 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
05da4558 542
44ad9944 543 return &slot->lpage_info[level - 2][idx].rmap_pde;
290fc38d
IE		 544}
545
cd4a4e53
AK		 546/*
547 * Reverse mapping data structures:
548 *
290fc38d
IE		 549 * If rmapp bit zero is zero, then rmapp point to the shadw page table entry
550 * that points to page_address(page).
cd4a4e53 551 *
290fc38d
IE		 552 * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc
553 * containing more mappings.
53a27b39
MT		 554 *
555 * Returns the number of rmap entries before the spte was added or zero if
556 * the spte was not added.
557 *
cd4a4e53 558 */
44ad9944 559static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
cd4a4e53 560{
4db35314 561 struct kvm_mmu_page *sp;
cd4a4e53 562 struct kvm_rmap_desc *desc;
290fc38d 563 unsigned long *rmapp;
53a27b39 564 int i, count = 0;
cd4a4e53 565
43a3795a 566 if (!is_rmap_spte(*spte))
53a27b39 567 return count;
290fc38d 568 gfn = unalias_gfn(vcpu->kvm, gfn);
4db35314
AK		 569 sp = page_header(__pa(spte));
570 sp->gfns[spte - sp->spt] = gfn;
44ad9944 571 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
290fc38d 572 if (!*rmapp) {
cd4a4e53 573 rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
290fc38d
IE		 574 *rmapp = (unsigned long)spte;
575 } else if (!(*rmapp & 1)) {
cd4a4e53 576 rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
714b93da 577 desc = mmu_alloc_rmap_desc(vcpu);
d555c333
AK		 578 desc->sptes[0] = (u64 *)*rmapp;
579 desc->sptes[1] = spte;
290fc38d 580 *rmapp = (unsigned long)desc | 1;
cd4a4e53
AK		 581 } else {
582 rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
290fc38d 583 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
d555c333 584 while (desc->sptes[RMAP_EXT-1] && desc->more) {
cd4a4e53 585 desc = desc->more;
53a27b39
MT		 586 count += RMAP_EXT;
587 }
d555c333 588 if (desc->sptes[RMAP_EXT-1]) {
714b93da 589 desc->more = mmu_alloc_rmap_desc(vcpu);
cd4a4e53
AK		 590 desc = desc->more;
591 }
d555c333 592 for (i = 0; desc->sptes[i]; ++i)
cd4a4e53 593 ;
d555c333 594 desc->sptes[i] = spte;
cd4a4e53 595 }
53a27b39 596 return count;
cd4a4e53
AK		 597}
598
290fc38d 599static void rmap_desc_remove_entry(unsigned long *rmapp,
cd4a4e53
AK		 600 struct kvm_rmap_desc *desc,
601 int i,
602 struct kvm_rmap_desc *prev_desc)
603{
604 int j;
605
d555c333 606 for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j)
cd4a4e53 607 ;
d555c333
AK		 608 desc->sptes[i] = desc->sptes[j];
609 desc->sptes[j] = NULL;
cd4a4e53
AK		 610 if (j != 0)
611 return;
612 if (!prev_desc && !desc->more)
d555c333 613 *rmapp = (unsigned long)desc->sptes[0];
cd4a4e53
AK		 614 else
615 if (prev_desc)
616 prev_desc->more = desc->more;
617 else
290fc38d 618 *rmapp = (unsigned long)desc->more | 1;
90cb0529 619 mmu_free_rmap_desc(desc);
cd4a4e53
AK		 620}
621
290fc38d 622static void rmap_remove(struct kvm *kvm, u64 *spte)
cd4a4e53 623{
cd4a4e53
AK		 624 struct kvm_rmap_desc *desc;
625 struct kvm_rmap_desc *prev_desc;
4db35314 626 struct kvm_mmu_page *sp;
35149e21 627 pfn_t pfn;
290fc38d 628 unsigned long *rmapp;
cd4a4e53
AK		 629 int i;
630
43a3795a 631 if (!is_rmap_spte(*spte))
cd4a4e53 632 return;
4db35314 633 sp = page_header(__pa(spte));
35149e21 634 pfn = spte_to_pfn(*spte);
7b52345e 635 if (*spte & shadow_accessed_mask)
35149e21 636 kvm_set_pfn_accessed(pfn);
b4231d61 637 if (is_writeble_pte(*spte))
acb66dd0 638 kvm_set_pfn_dirty(pfn);
44ad9944 639 rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt], sp->role.level);
290fc38d 640 if (!*rmapp) {
cd4a4e53
AK		 641 printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
642 BUG();
290fc38d 643 } else if (!(*rmapp & 1)) {
cd4a4e53 644 rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte);
290fc38d 645 if ((u64 *)*rmapp != spte) {
cd4a4e53
AK		 646 printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n",
647 spte, *spte);
648 BUG();
649 }
290fc38d 650 *rmapp = 0;
cd4a4e53
AK		 651 } else {
652 rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte);
290fc38d 653 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
cd4a4e53
AK		 654 prev_desc = NULL;
655 while (desc) {
d555c333
AK		 656 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i)
657 if (desc->sptes[i] == spte) {
290fc38d 658 rmap_desc_remove_entry(rmapp,
714b93da 659 desc, i,
cd4a4e53
AK		 660 prev_desc);
661 return;
662 }
663 prev_desc = desc;
664 desc = desc->more;
665 }
186a3e52 666 pr_err("rmap_remove: %p %llx many->many\n", spte, *spte);
cd4a4e53
AK		 667 BUG();
668 }
669}
670
98348e95 671static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
374cbac0 672{
374cbac0 673 struct kvm_rmap_desc *desc;
98348e95
IE		 674 struct kvm_rmap_desc *prev_desc;
675 u64 *prev_spte;
676 int i;
677
678 if (!*rmapp)
679 return NULL;
680 else if (!(*rmapp & 1)) {
681 if (!spte)
682 return (u64 *)*rmapp;
683 return NULL;
684 }
685 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
686 prev_desc = NULL;
687 prev_spte = NULL;
688 while (desc) {
d555c333 689 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) {
98348e95 690 if (prev_spte == spte)
d555c333
AK		 691 return desc->sptes[i];
692 prev_spte = desc->sptes[i];
98348e95
IE		 693 }
694 desc = desc->more;
695 }
696 return NULL;
697}
698
b1a36821 699static int rmap_write_protect(struct kvm *kvm, u64 gfn)
98348e95 700{
290fc38d 701 unsigned long *rmapp;
374cbac0 702 u64 *spte;
44ad9944 703 int i, write_protected = 0;
374cbac0 704
4a4c9924 705 gfn = unalias_gfn(kvm, gfn);
44ad9944 706 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
374cbac0 707
98348e95
IE		 708 spte = rmap_next(kvm, rmapp, NULL);
709 while (spte) {
374cbac0 710 BUG_ON(!spte);
374cbac0 711 BUG_ON(!(*spte & PT_PRESENT_MASK));
374cbac0 712 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
caa5b8a5 713 if (is_writeble_pte(*spte)) {
d555c333 714 __set_spte(spte, *spte & ~PT_WRITABLE_MASK);
caa5b8a5
ED		 715 write_protected = 1;
716 }
9647c14c 717 spte = rmap_next(kvm, rmapp, spte);
374cbac0 718 }
855149aa 719 if (write_protected) {
35149e21 720 pfn_t pfn;
855149aa
IE		 721
722 spte = rmap_next(kvm, rmapp, NULL);
35149e21
AL		 723 pfn = spte_to_pfn(*spte);
724 kvm_set_pfn_dirty(pfn);
855149aa
IE		 725 }
726
05da4558 727 /* check for huge page mappings */
44ad9944
JR		 728 for (i = PT_DIRECTORY_LEVEL;
729 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
730 rmapp = gfn_to_rmap(kvm, gfn, i);
731 spte = rmap_next(kvm, rmapp, NULL);
732 while (spte) {
733 BUG_ON(!spte);
734 BUG_ON(!(*spte & PT_PRESENT_MASK));
735 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
736 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
737 if (is_writeble_pte(*spte)) {
738 rmap_remove(kvm, spte);
739 --kvm->stat.lpages;
740 __set_spte(spte, shadow_trap_nonpresent_pte);
741 spte = NULL;
742 write_protected = 1;
743 }
744 spte = rmap_next(kvm, rmapp, spte);
05da4558 745 }
05da4558
MT		 746 }
747
b1a36821 748 return write_protected;
374cbac0
AK		 749}
750
8a8365c5
FD		 751static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
752 unsigned long data)
e930bffe
AA		 753{
754 u64 *spte;
755 int need_tlb_flush = 0;
756
757 while ((spte = rmap_next(kvm, rmapp, NULL))) {
758 BUG_ON(!(*spte & PT_PRESENT_MASK));
759 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
760 rmap_remove(kvm, spte);
d555c333 761 __set_spte(spte, shadow_trap_nonpresent_pte);
e930bffe
AA		 762 need_tlb_flush = 1;
763 }
764 return need_tlb_flush;
765}
766
8a8365c5
FD		 767static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
768 unsigned long data)
3da0dd43
IE		 769{
770 int need_flush = 0;
771 u64 *spte, new_spte;
772 pte_t *ptep = (pte_t *)data;
773 pfn_t new_pfn;
774
775 WARN_ON(pte_huge(*ptep));
776 new_pfn = pte_pfn(*ptep);
777 spte = rmap_next(kvm, rmapp, NULL);
778 while (spte) {
779 BUG_ON(!is_shadow_present_pte(*spte));
780 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
781 need_flush = 1;
782 if (pte_write(*ptep)) {
783 rmap_remove(kvm, spte);
784 __set_spte(spte, shadow_trap_nonpresent_pte);
785 spte = rmap_next(kvm, rmapp, NULL);
786 } else {
787 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
788 new_spte |= (u64)new_pfn << PAGE_SHIFT;
789
790 new_spte &= ~PT_WRITABLE_MASK;
791 new_spte &= ~SPTE_HOST_WRITEABLE;
792 if (is_writeble_pte(*spte))
793 kvm_set_pfn_dirty(spte_to_pfn(*spte));
794 __set_spte(spte, new_spte);
795 spte = rmap_next(kvm, rmapp, spte);
796 }
797 }
798 if (need_flush)
799 kvm_flush_remote_tlbs(kvm);
800
801 return 0;
802}
803
8a8365c5
FD		 804static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
805 unsigned long data,
3da0dd43 806 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
8a8365c5 807 unsigned long data))
e930bffe 808{
852e3c19 809 int i, j;
e930bffe 810 int retval = 0;
bc6678a3
MT		 811 struct kvm_memslots *slots;
812
813 slots = rcu_dereference(kvm->memslots);
e930bffe 814
46a26bf5
MT		 815 for (i = 0; i < slots->nmemslots; i++) {
816 struct kvm_memory_slot *memslot = &slots->memslots[i];
e930bffe
AA		 817 unsigned long start = memslot->userspace_addr;
818 unsigned long end;
819
e930bffe
AA		 820 end = start + (memslot->npages << PAGE_SHIFT);
821 if (hva >= start && hva < end) {
822 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
852e3c19 823
3da0dd43
IE		 824 retval |= handler(kvm, &memslot->rmap[gfn_offset],
825 data);
852e3c19
JR		 826
827 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
828 int idx = gfn_offset;
829 idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j);
830 retval |= handler(kvm,
3da0dd43
IE		 831 &memslot->lpage_info[j][idx].rmap_pde,
832 data);
852e3c19 833 }
e930bffe
AA		 834 }
835 }
836
837 return retval;
838}
839
840int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
841{
3da0dd43
IE		 842 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
843}
844
845void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
846{
8a8365c5 847 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
e930bffe
AA		 848}
849
8a8365c5
FD		 850static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
851 unsigned long data)
e930bffe
AA		 852{
853 u64 *spte;
854 int young = 0;
855
534e38b4
SY		 856 /* always return old for EPT */
857 if (!shadow_accessed_mask)
858 return 0;
859
e930bffe
AA		 860 spte = rmap_next(kvm, rmapp, NULL);
861 while (spte) {
862 int _young;
863 u64 _spte = *spte;
864 BUG_ON(!(_spte & PT_PRESENT_MASK));
865 _young = _spte & PT_ACCESSED_MASK;
866 if (_young) {
867 young = 1;
868 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
869 }
870 spte = rmap_next(kvm, rmapp, spte);
871 }
872 return young;
873}
874
53a27b39
MT		 875#define RMAP_RECYCLE_THRESHOLD 1000
876
852e3c19 877static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
53a27b39
MT		 878{
879 unsigned long *rmapp;
852e3c19
JR		 880 struct kvm_mmu_page *sp;
881
882 sp = page_header(__pa(spte));
53a27b39
MT		 883
884 gfn = unalias_gfn(vcpu->kvm, gfn);
852e3c19 885 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
53a27b39 886
3da0dd43 887 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
53a27b39
MT		 888 kvm_flush_remote_tlbs(vcpu->kvm);
889}
890
e930bffe
AA		 891int kvm_age_hva(struct kvm *kvm, unsigned long hva)
892{
3da0dd43 893 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
e930bffe
AA		 894}
895
d6c69ee9 896#ifdef MMU_DEBUG
47ad8e68 897static int is_empty_shadow_page(u64 *spt)
6aa8b732 898{
139bdb2d
AK		 899 u64 *pos;
900 u64 *end;
901
47ad8e68 902 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
3c915510 903 if (is_shadow_present_pte(*pos)) {
b8688d51 904 printk(KERN_ERR "%s: %p %llx\n", __func__,
139bdb2d 905 pos, *pos);
6aa8b732 906 return 0;
139bdb2d 907 }
6aa8b732
AK		 908 return 1;
909}
d6c69ee9 910#endif
6aa8b732 911
4db35314 912static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
260746c0 913{
4db35314
AK		 914 ASSERT(is_empty_shadow_page(sp->spt));
915 list_del(&sp->link);
916 __free_page(virt_to_page(sp->spt));
917 __free_page(virt_to_page(sp->gfns));
918 kfree(sp);
f05e70ac 919 ++kvm->arch.n_free_mmu_pages;
260746c0
AK		 920}
921
cea0f0e7
AK		 922static unsigned kvm_page_table_hashfn(gfn_t gfn)
923{
1ae0a13d 924 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
cea0f0e7
AK		 925}
926
25c0de2c
AK		 927static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
928 u64 *parent_pte)
6aa8b732 929{
4db35314 930 struct kvm_mmu_page *sp;
6aa8b732 931
ad312c7c
ZX		 932 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp);
933 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
934 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
4db35314 935 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
f05e70ac 936 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
6cffe8ca 937 INIT_LIST_HEAD(&sp->oos_link);
291f26bc 938 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
4db35314
AK		 939 sp->multimapped = 0;
940 sp->parent_pte = parent_pte;
f05e70ac 941 --vcpu->kvm->arch.n_free_mmu_pages;
4db35314 942 return sp;
6aa8b732
AK		 943}
944
714b93da 945static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
4db35314 946 struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7
AK		 947{
948 struct kvm_pte_chain *pte_chain;
949 struct hlist_node *node;
950 int i;
951
952 if (!parent_pte)
953 return;
4db35314
AK		 954 if (!sp->multimapped) {
955 u64 *old = sp->parent_pte;
cea0f0e7
AK		 956
957 if (!old) {
4db35314 958 sp->parent_pte = parent_pte;
cea0f0e7
AK		 959 return;
960 }
4db35314 961 sp->multimapped = 1;
714b93da 962 pte_chain = mmu_alloc_pte_chain(vcpu);
4db35314
AK		 963 INIT_HLIST_HEAD(&sp->parent_ptes);
964 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 965 pte_chain->parent_ptes[0] = old;
966 }
4db35314 967 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) {
cea0f0e7
AK		 968 if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1])
969 continue;
970 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i)
971 if (!pte_chain->parent_ptes[i]) {
972 pte_chain->parent_ptes[i] = parent_pte;
973 return;
974 }
975 }
714b93da 976 pte_chain = mmu_alloc_pte_chain(vcpu);
cea0f0e7 977 BUG_ON(!pte_chain);
4db35314 978 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 979 pte_chain->parent_ptes[0] = parent_pte;
980}
981
4db35314 982static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
cea0f0e7
AK		 983 u64 *parent_pte)
984{
985 struct kvm_pte_chain *pte_chain;
986 struct hlist_node *node;
987 int i;
988
4db35314
AK		 989 if (!sp->multimapped) {
990 BUG_ON(sp->parent_pte != parent_pte);
991 sp->parent_pte = NULL;
cea0f0e7
AK		 992 return;
993 }
4db35314 994 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
cea0f0e7
AK		 995 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
996 if (!pte_chain->parent_ptes[i])
997 break;
998 if (pte_chain->parent_ptes[i] != parent_pte)
999 continue;
697fe2e2
AK		 1000 while (i + 1 < NR_PTE_CHAIN_ENTRIES
1001 && pte_chain->parent_ptes[i + 1]) {
cea0f0e7
AK		 1002 pte_chain->parent_ptes[i]
1003 = pte_chain->parent_ptes[i + 1];
1004 ++i;
1005 }
1006 pte_chain->parent_ptes[i] = NULL;
697fe2e2
AK		 1007 if (i == 0) {
1008 hlist_del(&pte_chain->link);
90cb0529 1009 mmu_free_pte_chain(pte_chain);
4db35314
AK		 1010 if (hlist_empty(&sp->parent_ptes)) {
1011 sp->multimapped = 0;
1012 sp->parent_pte = NULL;
697fe2e2
AK		 1013 }
1014 }
cea0f0e7
AK		 1015 return;
1016 }
1017 BUG();
1018}
1019
ad8cfbe3
MT		 1020
1021static void mmu_parent_walk(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1022 mmu_parent_walk_fn fn)
1023{
1024 struct kvm_pte_chain *pte_chain;
1025 struct hlist_node *node;
1026 struct kvm_mmu_page *parent_sp;
1027 int i;
1028
1029 if (!sp->multimapped && sp->parent_pte) {
1030 parent_sp = page_header(__pa(sp->parent_pte));
1031 fn(vcpu, parent_sp);
1032 mmu_parent_walk(vcpu, parent_sp, fn);
1033 return;
1034 }
1035 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1036 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1037 if (!pte_chain->parent_ptes[i])
1038 break;
1039 parent_sp = page_header(__pa(pte_chain->parent_ptes[i]));
1040 fn(vcpu, parent_sp);
1041 mmu_parent_walk(vcpu, parent_sp, fn);
1042 }
1043}
1044
0074ff63
MT		 1045static void kvm_mmu_update_unsync_bitmap(u64 *spte)
1046{
1047 unsigned int index;
1048 struct kvm_mmu_page *sp = page_header(__pa(spte));
1049
1050 index = spte - sp->spt;
60c8aec6
MT		 1051 if (!__test_and_set_bit(index, sp->unsync_child_bitmap))
1052 sp->unsync_children++;
1053 WARN_ON(!sp->unsync_children);
0074ff63
MT		 1054}
1055
1056static void kvm_mmu_update_parents_unsync(struct kvm_mmu_page *sp)
1057{
1058 struct kvm_pte_chain *pte_chain;
1059 struct hlist_node *node;
1060 int i;
1061
1062 if (!sp->parent_pte)
1063 return;
1064
1065 if (!sp->multimapped) {
1066 kvm_mmu_update_unsync_bitmap(sp->parent_pte);
1067 return;
1068 }
1069
1070 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1071 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1072 if (!pte_chain->parent_ptes[i])
1073 break;
1074 kvm_mmu_update_unsync_bitmap(pte_chain->parent_ptes[i]);
1075 }
1076}
1077
1078static int unsync_walk_fn(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1079{
0074ff63
MT		 1080 kvm_mmu_update_parents_unsync(sp);
1081 return 1;
1082}
1083
1084static void kvm_mmu_mark_parents_unsync(struct kvm_vcpu *vcpu,
1085 struct kvm_mmu_page *sp)
1086{
1087 mmu_parent_walk(vcpu, sp, unsync_walk_fn);
1088 kvm_mmu_update_parents_unsync(sp);
1089}
1090
d761a501
AK		 1091static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
1092 struct kvm_mmu_page *sp)
1093{
1094 int i;
1095
1096 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1097 sp->spt[i] = shadow_trap_nonpresent_pte;
1098}
1099
e8bc217a
MT		 1100static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1101 struct kvm_mmu_page *sp)
1102{
1103 return 1;
1104}
1105
a7052897
MT		 1106static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1107{
1108}
1109
60c8aec6
MT		 1110#define KVM_PAGE_ARRAY_NR 16
1111
1112struct kvm_mmu_pages {
1113 struct mmu_page_and_offset {
1114 struct kvm_mmu_page *sp;
1115 unsigned int idx;
1116 } page[KVM_PAGE_ARRAY_NR];
1117 unsigned int nr;
1118};
1119
0074ff63
MT		 1120#define for_each_unsync_children(bitmap, idx) \
1121 for (idx = find_first_bit(bitmap, 512); \
1122 idx < 512; \
1123 idx = find_next_bit(bitmap, 512, idx+1))
1124
cded19f3
HE		 1125static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1126 int idx)
4731d4c7 1127{
60c8aec6 1128 int i;
4731d4c7 1129
60c8aec6
MT		 1130 if (sp->unsync)
1131 for (i=0; i < pvec->nr; i++)
1132 if (pvec->page[i].sp == sp)
1133 return 0;
1134
1135 pvec->page[pvec->nr].sp = sp;
1136 pvec->page[pvec->nr].idx = idx;
1137 pvec->nr++;
1138 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1139}
1140
1141static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1142 struct kvm_mmu_pages *pvec)
1143{
1144 int i, ret, nr_unsync_leaf = 0;
4731d4c7 1145
0074ff63 1146 for_each_unsync_children(sp->unsync_child_bitmap, i) {
4731d4c7
MT		 1147 u64 ent = sp->spt[i];
1148
87917239 1149 if (is_shadow_present_pte(ent) && !is_large_pte(ent)) {
4731d4c7
MT		 1150 struct kvm_mmu_page *child;
1151 child = page_header(ent & PT64_BASE_ADDR_MASK);
1152
1153 if (child->unsync_children) {
60c8aec6
MT		 1154 if (mmu_pages_add(pvec, child, i))
1155 return -ENOSPC;
1156
1157 ret = __mmu_unsync_walk(child, pvec);
1158 if (!ret)
1159 __clear_bit(i, sp->unsync_child_bitmap);
1160 else if (ret > 0)
1161 nr_unsync_leaf += ret;
1162 else
4731d4c7
MT		 1163 return ret;
1164 }
1165
1166 if (child->unsync) {
60c8aec6
MT		 1167 nr_unsync_leaf++;
1168 if (mmu_pages_add(pvec, child, i))
1169 return -ENOSPC;
4731d4c7
MT		 1170 }
1171 }
1172 }
1173
0074ff63 1174 if (find_first_bit(sp->unsync_child_bitmap, 512) == 512)
4731d4c7
MT		 1175 sp->unsync_children = 0;
1176
60c8aec6
MT		 1177 return nr_unsync_leaf;
1178}
1179
1180static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1181 struct kvm_mmu_pages *pvec)
1182{
1183 if (!sp->unsync_children)
1184 return 0;
1185
1186 mmu_pages_add(pvec, sp, 0);
1187 return __mmu_unsync_walk(sp, pvec);
4731d4c7
MT		 1188}
1189
4db35314 1190static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm *kvm, gfn_t gfn)
cea0f0e7
AK		 1191{
1192 unsigned index;
1193 struct hlist_head *bucket;
4db35314 1194 struct kvm_mmu_page *sp;
cea0f0e7
AK		 1195 struct hlist_node *node;
1196
b8688d51 1197 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
1ae0a13d 1198 index = kvm_page_table_hashfn(gfn);
f05e70ac 1199 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1200 hlist_for_each_entry(sp, node, bucket, hash_link)
f6e2c02b 1201 if (sp->gfn == gfn && !sp->role.direct
2e53d63a 1202 && !sp->role.invalid) {
cea0f0e7 1203 pgprintk("%s: found role %x\n",
b8688d51 1204 __func__, sp->role.word);
4db35314 1205 return sp;
cea0f0e7
AK		 1206 }
1207 return NULL;
1208}
1209
4731d4c7
MT		 1210static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1211{
1212 WARN_ON(!sp->unsync);
1213 sp->unsync = 0;
1214 --kvm->stat.mmu_unsync;
1215}
1216
1217static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp);
1218
1219static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1220{
1221 if (sp->role.glevels != vcpu->arch.mmu.root_level) {
1222 kvm_mmu_zap_page(vcpu->kvm, sp);
1223 return 1;
1224 }
1225
f691fe1d 1226 trace_kvm_mmu_sync_page(sp);
b1a36821
MT		 1227 if (rmap_write_protect(vcpu->kvm, sp->gfn))
1228 kvm_flush_remote_tlbs(vcpu->kvm);
0c0f40bd 1229 kvm_unlink_unsync_page(vcpu->kvm, sp);
4731d4c7
MT		 1230 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1231 kvm_mmu_zap_page(vcpu->kvm, sp);
1232 return 1;
1233 }
1234
1235 kvm_mmu_flush_tlb(vcpu);
4731d4c7
MT		 1236 return 0;
1237}
1238
60c8aec6
MT		 1239struct mmu_page_path {
1240 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1241 unsigned int idx[PT64_ROOT_LEVEL-1];
4731d4c7
MT		 1242};
1243
60c8aec6
MT		 1244#define for_each_sp(pvec, sp, parents, i) \
1245 for (i = mmu_pages_next(&pvec, &parents, -1), \
1246 sp = pvec.page[i].sp; \
1247 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1248 i = mmu_pages_next(&pvec, &parents, i))
1249
cded19f3
HE		 1250static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1251 struct mmu_page_path *parents,
1252 int i)
60c8aec6
MT		 1253{
1254 int n;
1255
1256 for (n = i+1; n < pvec->nr; n++) {
1257 struct kvm_mmu_page *sp = pvec->page[n].sp;
1258
1259 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1260 parents->idx[0] = pvec->page[n].idx;
1261 return n;
1262 }
1263
1264 parents->parent[sp->role.level-2] = sp;
1265 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1266 }
1267
1268 return n;
1269}
1270
cded19f3 1271static void mmu_pages_clear_parents(struct mmu_page_path *parents)
4731d4c7 1272{
60c8aec6
MT		 1273 struct kvm_mmu_page *sp;
1274 unsigned int level = 0;
1275
1276 do {
1277 unsigned int idx = parents->idx[level];
4731d4c7 1278
60c8aec6
MT		 1279 sp = parents->parent[level];
1280 if (!sp)
1281 return;
1282
1283 --sp->unsync_children;
1284 WARN_ON((int)sp->unsync_children < 0);
1285 __clear_bit(idx, sp->unsync_child_bitmap);
1286 level++;
1287 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
4731d4c7
MT		 1288}
1289
60c8aec6
MT		 1290static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1291 struct mmu_page_path *parents,
1292 struct kvm_mmu_pages *pvec)
4731d4c7 1293{
60c8aec6
MT		 1294 parents->parent[parent->role.level-1] = NULL;
1295 pvec->nr = 0;
1296}
4731d4c7 1297
60c8aec6
MT		 1298static void mmu_sync_children(struct kvm_vcpu *vcpu,
1299 struct kvm_mmu_page *parent)
1300{
1301 int i;
1302 struct kvm_mmu_page *sp;
1303 struct mmu_page_path parents;
1304 struct kvm_mmu_pages pages;
1305
1306 kvm_mmu_pages_init(parent, &parents, &pages);
1307 while (mmu_unsync_walk(parent, &pages)) {
b1a36821
MT		 1308 int protected = 0;
1309
1310 for_each_sp(pages, sp, parents, i)
1311 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1312
1313 if (protected)
1314 kvm_flush_remote_tlbs(vcpu->kvm);
1315
60c8aec6
MT		 1316 for_each_sp(pages, sp, parents, i) {
1317 kvm_sync_page(vcpu, sp);
1318 mmu_pages_clear_parents(&parents);
1319 }
4731d4c7 1320 cond_resched_lock(&vcpu->kvm->mmu_lock);
60c8aec6
MT		 1321 kvm_mmu_pages_init(parent, &parents, &pages);
1322 }
4731d4c7
MT		 1323}
1324
cea0f0e7
AK		 1325static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1326 gfn_t gfn,
1327 gva_t gaddr,
1328 unsigned level,
f6e2c02b 1329 int direct,
41074d07 1330 unsigned access,
f7d9c7b7 1331 u64 *parent_pte)
cea0f0e7
AK		 1332{
1333 union kvm_mmu_page_role role;
1334 unsigned index;
1335 unsigned quadrant;
1336 struct hlist_head *bucket;
4db35314 1337 struct kvm_mmu_page *sp;
4731d4c7 1338 struct hlist_node *node, *tmp;
cea0f0e7 1339
a770f6f2 1340 role = vcpu->arch.mmu.base_role;
cea0f0e7 1341 role.level = level;
f6e2c02b 1342 role.direct = direct;
41074d07 1343 role.access = access;
ad312c7c 1344 if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
cea0f0e7
AK		 1345 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1346 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1347 role.quadrant = quadrant;
1348 }
1ae0a13d 1349 index = kvm_page_table_hashfn(gfn);
f05e70ac 1350 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4731d4c7
MT		 1351 hlist_for_each_entry_safe(sp, node, tmp, bucket, hash_link)
1352 if (sp->gfn == gfn) {
1353 if (sp->unsync)
1354 if (kvm_sync_page(vcpu, sp))
1355 continue;
1356
1357 if (sp->role.word != role.word)
1358 continue;
1359
4db35314 1360 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
0074ff63
MT		 1361 if (sp->unsync_children) {
1362 set_bit(KVM_REQ_MMU_SYNC, &vcpu->requests);
1363 kvm_mmu_mark_parents_unsync(vcpu, sp);
1364 }
f691fe1d 1365 trace_kvm_mmu_get_page(sp, false);
4db35314 1366 return sp;
cea0f0e7 1367 }
dfc5aa00 1368 ++vcpu->kvm->stat.mmu_cache_miss;
4db35314
AK		 1369 sp = kvm_mmu_alloc_page(vcpu, parent_pte);
1370 if (!sp)
1371 return sp;
4db35314
AK		 1372 sp->gfn = gfn;
1373 sp->role = role;
1374 hlist_add_head(&sp->hash_link, bucket);
f6e2c02b 1375 if (!direct) {
b1a36821
MT		 1376 if (rmap_write_protect(vcpu->kvm, gfn))
1377 kvm_flush_remote_tlbs(vcpu->kvm);
4731d4c7
MT		 1378 account_shadowed(vcpu->kvm, gfn);
1379 }
131d8279
AK		 1380 if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
1381 vcpu->arch.mmu.prefetch_page(vcpu, sp);
1382 else
1383 nonpaging_prefetch_page(vcpu, sp);
f691fe1d 1384 trace_kvm_mmu_get_page(sp, true);
4db35314 1385 return sp;
cea0f0e7
AK		 1386}
1387
2d11123a
AK		 1388static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1389 struct kvm_vcpu *vcpu, u64 addr)
1390{
1391 iterator->addr = addr;
1392 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1393 iterator->level = vcpu->arch.mmu.shadow_root_level;
1394 if (iterator->level == PT32E_ROOT_LEVEL) {
1395 iterator->shadow_addr
1396 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1397 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1398 --iterator->level;
1399 if (!iterator->shadow_addr)
1400 iterator->level = 0;
1401 }
1402}
1403
1404static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1405{
1406 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1407 return false;
4d88954d
MT		 1408
1409 if (iterator->level == PT_PAGE_TABLE_LEVEL)
1410 if (is_large_pte(*iterator->sptep))
1411 return false;
1412
2d11123a
AK		 1413 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1414 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1415 return true;
1416}
1417
1418static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1419{
1420 iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK;
1421 --iterator->level;
1422}
1423
90cb0529 1424static void kvm_mmu_page_unlink_children(struct kvm *kvm,
4db35314 1425 struct kvm_mmu_page *sp)
a436036b 1426{
697fe2e2
AK		 1427 unsigned i;
1428 u64 *pt;
1429 u64 ent;
1430
4db35314 1431 pt = sp->spt;
697fe2e2 1432
697fe2e2
AK		 1433 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1434 ent = pt[i];
1435
05da4558 1436 if (is_shadow_present_pte(ent)) {
776e6633 1437 if (!is_last_spte(ent, sp->role.level)) {
05da4558
MT		 1438 ent &= PT64_BASE_ADDR_MASK;
1439 mmu_page_remove_parent_pte(page_header(ent),
1440 &pt[i]);
1441 } else {
776e6633
MT		 1442 if (is_large_pte(ent))
1443 --kvm->stat.lpages;
05da4558
MT		 1444 rmap_remove(kvm, &pt[i]);
1445 }
1446 }
c7addb90 1447 pt[i] = shadow_trap_nonpresent_pte;
697fe2e2 1448 }
a436036b
AK		 1449}
1450
4db35314 1451static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7 1452{
4db35314 1453 mmu_page_remove_parent_pte(sp, parent_pte);
a436036b
AK		 1454}
1455
12b7d28f
AK		 1456static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1457{
1458 int i;
988a2cae 1459 struct kvm_vcpu *vcpu;
12b7d28f 1460
988a2cae
GN		 1461 kvm_for_each_vcpu(i, vcpu, kvm)
1462 vcpu->arch.last_pte_updated = NULL;
12b7d28f
AK		 1463}
1464
31aa2b44 1465static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
a436036b
AK		 1466{
1467 u64 *parent_pte;
1468
4db35314
AK		 1469 while (sp->multimapped || sp->parent_pte) {
1470 if (!sp->multimapped)
1471 parent_pte = sp->parent_pte;
a436036b
AK		 1472 else {
1473 struct kvm_pte_chain *chain;
1474
4db35314 1475 chain = container_of(sp->parent_ptes.first,
a436036b
AK		 1476 struct kvm_pte_chain, link);
1477 parent_pte = chain->parent_ptes[0];
1478 }
697fe2e2 1479 BUG_ON(!parent_pte);
4db35314 1480 kvm_mmu_put_page(sp, parent_pte);
d555c333 1481 __set_spte(parent_pte, shadow_trap_nonpresent_pte);
a436036b 1482 }
31aa2b44
AK		 1483}
1484
60c8aec6
MT		 1485static int mmu_zap_unsync_children(struct kvm *kvm,
1486 struct kvm_mmu_page *parent)
4731d4c7 1487{
60c8aec6
MT		 1488 int i, zapped = 0;
1489 struct mmu_page_path parents;
1490 struct kvm_mmu_pages pages;
4731d4c7 1491
60c8aec6 1492 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
4731d4c7 1493 return 0;
60c8aec6
MT		 1494
1495 kvm_mmu_pages_init(parent, &parents, &pages);
1496 while (mmu_unsync_walk(parent, &pages)) {
1497 struct kvm_mmu_page *sp;
1498
1499 for_each_sp(pages, sp, parents, i) {
1500 kvm_mmu_zap_page(kvm, sp);
1501 mmu_pages_clear_parents(&parents);
1502 }
1503 zapped += pages.nr;
1504 kvm_mmu_pages_init(parent, &parents, &pages);
1505 }
1506
1507 return zapped;
4731d4c7
MT		 1508}
1509
07385413 1510static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp)
31aa2b44 1511{
4731d4c7 1512 int ret;
f691fe1d
AK		 1513
1514 trace_kvm_mmu_zap_page(sp);
31aa2b44 1515 ++kvm->stat.mmu_shadow_zapped;
4731d4c7 1516 ret = mmu_zap_unsync_children(kvm, sp);
4db35314 1517 kvm_mmu_page_unlink_children(kvm, sp);
31aa2b44 1518 kvm_mmu_unlink_parents(kvm, sp);
5b5c6a5a 1519 kvm_flush_remote_tlbs(kvm);
f6e2c02b 1520 if (!sp->role.invalid && !sp->role.direct)
5b5c6a5a 1521 unaccount_shadowed(kvm, sp->gfn);
4731d4c7
MT		 1522 if (sp->unsync)
1523 kvm_unlink_unsync_page(kvm, sp);
4db35314
AK		 1524 if (!sp->root_count) {
1525 hlist_del(&sp->hash_link);
1526 kvm_mmu_free_page(kvm, sp);
2e53d63a 1527 } else {
2e53d63a 1528 sp->role.invalid = 1;
5b5c6a5a 1529 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2e53d63a
MT		 1530 kvm_reload_remote_mmus(kvm);
1531 }
12b7d28f 1532 kvm_mmu_reset_last_pte_updated(kvm);
4731d4c7 1533 return ret;
a436036b
AK		 1534}
1535
82ce2c96
IE		 1536/*
1537 * Changing the number of mmu pages allocated to the vm
1538 * Note: if kvm_nr_mmu_pages is too small, you will get dead lock
1539 */
1540void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
1541{
025dbbf3
MT		 1542 int used_pages;
1543
1544 used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages;
1545 used_pages = max(0, used_pages);
1546
82ce2c96
IE		 1547 /*
1548 * If we set the number of mmu pages to be smaller be than the
1549 * number of actived pages , we must to free some mmu pages before we
1550 * change the value
1551 */
1552
025dbbf3
MT		 1553 if (used_pages > kvm_nr_mmu_pages) {
1554 while (used_pages > kvm_nr_mmu_pages) {
82ce2c96
IE		 1555 struct kvm_mmu_page *page;
1556
f05e70ac 1557 page = container_of(kvm->arch.active_mmu_pages.prev,
82ce2c96
IE		 1558 struct kvm_mmu_page, link);
1559 kvm_mmu_zap_page(kvm, page);
025dbbf3 1560 used_pages--;
82ce2c96 1561 }
f05e70ac 1562 kvm->arch.n_free_mmu_pages = 0;
82ce2c96
IE		 1563 }
1564 else
f05e70ac
ZX		 1565 kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages
1566 - kvm->arch.n_alloc_mmu_pages;
82ce2c96 1567
f05e70ac 1568 kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages;
82ce2c96
IE		 1569}
1570
f67a46f4 1571static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
a436036b
AK		 1572{
1573 unsigned index;
1574 struct hlist_head *bucket;
4db35314 1575 struct kvm_mmu_page *sp;
a436036b
AK		 1576 struct hlist_node *node, *n;
1577 int r;
1578
b8688d51 1579 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
a436036b 1580 r = 0;
1ae0a13d 1581 index = kvm_page_table_hashfn(gfn);
f05e70ac 1582 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1583 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link)
f6e2c02b 1584 if (sp->gfn == gfn && !sp->role.direct) {
b8688d51 1585 pgprintk("%s: gfn %lx role %x\n", __func__, gfn,
4db35314 1586 sp->role.word);
a436036b 1587 r = 1;
07385413
MT		 1588 if (kvm_mmu_zap_page(kvm, sp))
1589 n = bucket->first;
a436036b
AK		 1590 }
1591 return r;
cea0f0e7
AK		 1592}
1593
f67a46f4 1594static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
97a0a01e 1595{
4677a3b6
AK		 1596 unsigned index;
1597 struct hlist_head *bucket;
4db35314 1598 struct kvm_mmu_page *sp;
4677a3b6 1599 struct hlist_node *node, *nn;
97a0a01e 1600
4677a3b6
AK		 1601 index = kvm_page_table_hashfn(gfn);
1602 bucket = &kvm->arch.mmu_page_hash[index];
1603 hlist_for_each_entry_safe(sp, node, nn, bucket, hash_link) {
f6e2c02b 1604 if (sp->gfn == gfn && !sp->role.direct
4677a3b6
AK		 1605 && !sp->role.invalid) {
1606 pgprintk("%s: zap %lx %x\n",
1607 __func__, gfn, sp->role.word);
1608 kvm_mmu_zap_page(kvm, sp);
1609 }
97a0a01e
AK		 1610 }
1611}
1612
38c335f1 1613static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
6aa8b732 1614{
bc6678a3 1615 int slot = memslot_id(kvm, gfn);
4db35314 1616 struct kvm_mmu_page *sp = page_header(__pa(pte));
6aa8b732 1617
291f26bc 1618 __set_bit(slot, sp->slot_bitmap);
6aa8b732
AK		 1619}
1620
6844dec6
MT		 1621static void mmu_convert_notrap(struct kvm_mmu_page *sp)
1622{
1623 int i;
1624 u64 *pt = sp->spt;
1625
1626 if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte)
1627 return;
1628
1629 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1630 if (pt[i] == shadow_notrap_nonpresent_pte)
d555c333 1631 __set_spte(&pt[i], shadow_trap_nonpresent_pte);
6844dec6
MT		 1632 }
1633}
1634
039576c0
AK		 1635struct page *gva_to_page(struct kvm_vcpu *vcpu, gva_t gva)
1636{
72dc67a6
IE		 1637 struct page *page;
1638
ad312c7c 1639 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva);
039576c0
AK		 1640
1641 if (gpa == UNMAPPED_GVA)
1642 return NULL;
72dc67a6 1643
72dc67a6 1644 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6
IE		 1645
1646 return page;
039576c0
AK		 1647}
1648
74be52e3
SY		 1649/*
1650 * The function is based on mtrr_type_lookup() in
1651 * arch/x86/kernel/cpu/mtrr/generic.c
1652 */
1653static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1654 u64 start, u64 end)
1655{
1656 int i;
1657 u64 base, mask;
1658 u8 prev_match, curr_match;
1659 int num_var_ranges = KVM_NR_VAR_MTRR;
1660
1661 if (!mtrr_state->enabled)
1662 return 0xFF;
1663
1664 /* Make end inclusive end, instead of exclusive */
1665 end--;
1666
1667 /* Look in fixed ranges. Just return the type as per start */
1668 if (mtrr_state->have_fixed && (start < 0x100000)) {
1669 int idx;
1670
1671 if (start < 0x80000) {
1672 idx = 0;
1673 idx += (start >> 16);
1674 return mtrr_state->fixed_ranges[idx];
1675 } else if (start < 0xC0000) {
1676 idx = 1 * 8;
1677 idx += ((start - 0x80000) >> 14);
1678 return mtrr_state->fixed_ranges[idx];
1679 } else if (start < 0x1000000) {
1680 idx = 3 * 8;
1681 idx += ((start - 0xC0000) >> 12);
1682 return mtrr_state->fixed_ranges[idx];
1683 }
1684 }
1685
1686 /*
1687 * Look in variable ranges
1688 * Look of multiple ranges matching this address and pick type
1689 * as per MTRR precedence
1690 */
1691 if (!(mtrr_state->enabled & 2))
1692 return mtrr_state->def_type;
1693
1694 prev_match = 0xFF;
1695 for (i = 0; i < num_var_ranges; ++i) {
1696 unsigned short start_state, end_state;
1697
1698 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
1699 continue;
1700
1701 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
1702 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
1703 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
1704 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
1705
1706 start_state = ((start & mask) == (base & mask));
1707 end_state = ((end & mask) == (base & mask));
1708 if (start_state != end_state)
1709 return 0xFE;
1710
1711 if ((start & mask) != (base & mask))
1712 continue;
1713
1714 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
1715 if (prev_match == 0xFF) {
1716 prev_match = curr_match;
1717 continue;
1718 }
1719
1720 if (prev_match == MTRR_TYPE_UNCACHABLE ||
1721 curr_match == MTRR_TYPE_UNCACHABLE)
1722 return MTRR_TYPE_UNCACHABLE;
1723
1724 if ((prev_match == MTRR_TYPE_WRBACK &&
1725 curr_match == MTRR_TYPE_WRTHROUGH) ||
1726 (prev_match == MTRR_TYPE_WRTHROUGH &&
1727 curr_match == MTRR_TYPE_WRBACK)) {
1728 prev_match = MTRR_TYPE_WRTHROUGH;
1729 curr_match = MTRR_TYPE_WRTHROUGH;
1730 }
1731
1732 if (prev_match != curr_match)
1733 return MTRR_TYPE_UNCACHABLE;
1734 }
1735
1736 if (prev_match != 0xFF)
1737 return prev_match;
1738
1739 return mtrr_state->def_type;
1740}
1741
4b12f0de 1742u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
74be52e3
SY		 1743{
1744 u8 mtrr;
1745
1746 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
1747 (gfn << PAGE_SHIFT) + PAGE_SIZE);
1748 if (mtrr == 0xfe || mtrr == 0xff)
1749 mtrr = MTRR_TYPE_WRBACK;
1750 return mtrr;
1751}
4b12f0de 1752EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
74be52e3 1753
4731d4c7
MT		 1754static int kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1755{
1756 unsigned index;
1757 struct hlist_head *bucket;
1758 struct kvm_mmu_page *s;
1759 struct hlist_node *node, *n;
1760
f691fe1d 1761 trace_kvm_mmu_unsync_page(sp);
4731d4c7
MT		 1762 index = kvm_page_table_hashfn(sp->gfn);
1763 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
1764 /* don't unsync if pagetable is shadowed with multiple roles */
1765 hlist_for_each_entry_safe(s, node, n, bucket, hash_link) {
f6e2c02b 1766 if (s->gfn != sp->gfn || s->role.direct)
4731d4c7
MT		 1767 continue;
1768 if (s->role.word != sp->role.word)
1769 return 1;
1770 }
4731d4c7
MT		 1771 ++vcpu->kvm->stat.mmu_unsync;
1772 sp->unsync = 1;
6cffe8ca 1773
c2d0ee46 1774 kvm_mmu_mark_parents_unsync(vcpu, sp);
6cffe8ca 1775
4731d4c7
MT		 1776 mmu_convert_notrap(sp);
1777 return 0;
1778}
1779
1780static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
1781 bool can_unsync)
1782{
1783 struct kvm_mmu_page *shadow;
1784
1785 shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
1786 if (shadow) {
1787 if (shadow->role.level != PT_PAGE_TABLE_LEVEL)
1788 return 1;
1789 if (shadow->unsync)
1790 return 0;
582801a9 1791 if (can_unsync && oos_shadow)
4731d4c7
MT		 1792 return kvm_unsync_page(vcpu, shadow);
1793 return 1;
1794 }
1795 return 0;
1796}
1797
d555c333 1798static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd 1799 unsigned pte_access, int user_fault,
852e3c19 1800 int write_fault, int dirty, int level,
c2d0ee46 1801 gfn_t gfn, pfn_t pfn, bool speculative,
1403283a 1802 bool can_unsync, bool reset_host_protection)
1c4f1fd6
AK		 1803{
1804 u64 spte;
1e73f9dd 1805 int ret = 0;
64d4d521 1806
1c4f1fd6
AK		 1807 /*
1808 * We don't set the accessed bit, since we sometimes want to see
1809 * whether the guest actually used the pte (in order to detect
1810 * demand paging).
1811 */
7b52345e 1812 spte = shadow_base_present_pte | shadow_dirty_mask;
947da538 1813 if (!speculative)
3201b5d9 1814 spte |= shadow_accessed_mask;
1c4f1fd6
AK		 1815 if (!dirty)
1816 pte_access &= ~ACC_WRITE_MASK;
7b52345e
SY		 1817 if (pte_access & ACC_EXEC_MASK)
1818 spte |= shadow_x_mask;
1819 else
1820 spte |= shadow_nx_mask;
1c4f1fd6 1821 if (pte_access & ACC_USER_MASK)
7b52345e 1822 spte |= shadow_user_mask;
852e3c19 1823 if (level > PT_PAGE_TABLE_LEVEL)
05da4558 1824 spte |= PT_PAGE_SIZE_MASK;
4b12f0de
SY		 1825 if (tdp_enabled)
1826 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
1827 kvm_is_mmio_pfn(pfn));
1c4f1fd6 1828
1403283a
IE		 1829 if (reset_host_protection)
1830 spte |= SPTE_HOST_WRITEABLE;
1831
35149e21 1832 spte |= (u64)pfn << PAGE_SHIFT;
1c4f1fd6
AK		 1833
1834 if ((pte_access & ACC_WRITE_MASK)
1835 || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
1c4f1fd6 1836
852e3c19
JR		 1837 if (level > PT_PAGE_TABLE_LEVEL &&
1838 has_wrprotected_page(vcpu->kvm, gfn, level)) {
38187c83
MT		 1839 ret = 1;
1840 spte = shadow_trap_nonpresent_pte;
1841 goto set_pte;
1842 }
1843
1c4f1fd6 1844 spte |= PT_WRITABLE_MASK;
1c4f1fd6 1845
ecc5589f
MT		 1846 /*
1847 * Optimization: for pte sync, if spte was writable the hash
1848 * lookup is unnecessary (and expensive). Write protection
1849 * is responsibility of mmu_get_page / kvm_sync_page.
1850 * Same reasoning can be applied to dirty page accounting.
1851 */
d555c333 1852 if (!can_unsync && is_writeble_pte(*sptep))
ecc5589f
MT		 1853 goto set_pte;
1854
4731d4c7 1855 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
1c4f1fd6 1856 pgprintk("%s: found shadow page for %lx, marking ro\n",
b8688d51 1857 __func__, gfn);
1e73f9dd 1858 ret = 1;
1c4f1fd6 1859 pte_access &= ~ACC_WRITE_MASK;
a378b4e6 1860 if (is_writeble_pte(spte))
1c4f1fd6 1861 spte &= ~PT_WRITABLE_MASK;
1c4f1fd6
AK		 1862 }
1863 }
1864
1c4f1fd6
AK		 1865 if (pte_access & ACC_WRITE_MASK)
1866 mark_page_dirty(vcpu->kvm, gfn);
1867
38187c83 1868set_pte:
d555c333 1869 __set_spte(sptep, spte);
1e73f9dd
MT		 1870 return ret;
1871}
1872
d555c333 1873static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd
MT		 1874 unsigned pt_access, unsigned pte_access,
1875 int user_fault, int write_fault, int dirty,
852e3c19 1876 int *ptwrite, int level, gfn_t gfn,
1403283a
IE		 1877 pfn_t pfn, bool speculative,
1878 bool reset_host_protection)
1e73f9dd
MT		 1879{
1880 int was_rmapped = 0;
d555c333 1881 int was_writeble = is_writeble_pte(*sptep);
53a27b39 1882 int rmap_count;
1e73f9dd
MT		 1883
1884 pgprintk("%s: spte %llx access %x write_fault %d"
1885 " user_fault %d gfn %lx\n",
d555c333 1886 __func__, *sptep, pt_access,
1e73f9dd
MT		 1887 write_fault, user_fault, gfn);
1888
d555c333 1889 if (is_rmap_spte(*sptep)) {
1e73f9dd
MT		 1890 /*
1891 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
1892 * the parent of the now unreachable PTE.
1893 */
852e3c19
JR		 1894 if (level > PT_PAGE_TABLE_LEVEL &&
1895 !is_large_pte(*sptep)) {
1e73f9dd 1896 struct kvm_mmu_page *child;
d555c333 1897 u64 pte = *sptep;
1e73f9dd
MT		 1898
1899 child = page_header(pte & PT64_BASE_ADDR_MASK);
d555c333
AK		 1900 mmu_page_remove_parent_pte(child, sptep);
1901 } else if (pfn != spte_to_pfn(*sptep)) {
1e73f9dd 1902 pgprintk("hfn old %lx new %lx\n",
d555c333
AK		 1903 spte_to_pfn(*sptep), pfn);
1904 rmap_remove(vcpu->kvm, sptep);
6bed6b9e
JR		 1905 } else
1906 was_rmapped = 1;
1e73f9dd 1907 }
852e3c19 1908
d555c333 1909 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
1403283a
IE		 1910 dirty, level, gfn, pfn, speculative, true,
1911 reset_host_protection)) {
1e73f9dd
MT		 1912 if (write_fault)
1913 *ptwrite = 1;
a378b4e6
MT		 1914 kvm_x86_ops->tlb_flush(vcpu);
1915 }
1e73f9dd 1916
d555c333 1917 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
1e73f9dd 1918 pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n",
d555c333 1919 is_large_pte(*sptep)? "2MB" : "4kB",
a205bc19
JR		 1920 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
1921 *sptep, sptep);
d555c333 1922 if (!was_rmapped && is_large_pte(*sptep))
05da4558
MT		 1923 ++vcpu->kvm->stat.lpages;
1924
d555c333 1925 page_header_update_slot(vcpu->kvm, sptep, gfn);
1c4f1fd6 1926 if (!was_rmapped) {
44ad9944 1927 rmap_count = rmap_add(vcpu, sptep, gfn);
acb66dd0 1928 kvm_release_pfn_clean(pfn);
53a27b39 1929 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
852e3c19 1930 rmap_recycle(vcpu, sptep, gfn);
75e68e60
IE		 1931 } else {
1932 if (was_writeble)
35149e21 1933 kvm_release_pfn_dirty(pfn);
75e68e60 1934 else
35149e21 1935 kvm_release_pfn_clean(pfn);
1c4f1fd6 1936 }
1b7fcd32 1937 if (speculative) {
d555c333 1938 vcpu->arch.last_pte_updated = sptep;
1b7fcd32
AK		 1939 vcpu->arch.last_pte_gfn = gfn;
1940 }
1c4f1fd6
AK		 1941}
1942
6aa8b732
AK		 1943static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
1944{
1945}
1946
9f652d21 1947static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
852e3c19 1948 int level, gfn_t gfn, pfn_t pfn)
140754bc 1949{
9f652d21 1950 struct kvm_shadow_walk_iterator iterator;
140754bc 1951 struct kvm_mmu_page *sp;
9f652d21 1952 int pt_write = 0;
140754bc 1953 gfn_t pseudo_gfn;
6aa8b732 1954
9f652d21 1955 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
852e3c19 1956 if (iterator.level == level) {
9f652d21
AK		 1957 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL,
1958 0, write, 1, &pt_write,
1403283a 1959 level, gfn, pfn, false, true);
9f652d21
AK		 1960 ++vcpu->stat.pf_fixed;
1961 break;
6aa8b732
AK		 1962 }
1963
9f652d21
AK		 1964 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
1965 pseudo_gfn = (iterator.addr & PT64_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
1966 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
1967 iterator.level - 1,
1968 1, ACC_ALL, iterator.sptep);
1969 if (!sp) {
1970 pgprintk("nonpaging_map: ENOMEM\n");
1971 kvm_release_pfn_clean(pfn);
1972 return -ENOMEM;
1973 }
140754bc 1974
d555c333
AK		 1975 __set_spte(iterator.sptep,
1976 __pa(sp->spt)
1977 | PT_PRESENT_MASK | PT_WRITABLE_MASK
1978 | shadow_user_mask | shadow_x_mask);
9f652d21
AK		 1979 }
1980 }
1981 return pt_write;
6aa8b732
AK		 1982}
1983
10589a46
MT		 1984static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
1985{
1986 int r;
852e3c19 1987 int level;
35149e21 1988 pfn_t pfn;
e930bffe 1989 unsigned long mmu_seq;
aaee2c94 1990
852e3c19
JR		 1991 level = mapping_level(vcpu, gfn);
1992
1993 /*
1994 * This path builds a PAE pagetable - so we can map 2mb pages at
1995 * maximum. Therefore check if the level is larger than that.
1996 */
1997 if (level > PT_DIRECTORY_LEVEL)
1998 level = PT_DIRECTORY_LEVEL;
1999
2000 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
05da4558 2001
e930bffe 2002 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2003 smp_rmb();
35149e21 2004 pfn = gfn_to_pfn(vcpu->kvm, gfn);
aaee2c94 2005
d196e343 2006 /* mmio */
35149e21
AL		 2007 if (is_error_pfn(pfn)) {
2008 kvm_release_pfn_clean(pfn);
d196e343
AK		 2009 return 1;
2010 }
2011
aaee2c94 2012 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2013 if (mmu_notifier_retry(vcpu, mmu_seq))
2014 goto out_unlock;
eb787d10 2015 kvm_mmu_free_some_pages(vcpu);
852e3c19 2016 r = __direct_map(vcpu, v, write, level, gfn, pfn);
aaee2c94
MT		 2017 spin_unlock(&vcpu->kvm->mmu_lock);
2018
aaee2c94 2019
10589a46 2020 return r;
e930bffe
AA		 2021
2022out_unlock:
2023 spin_unlock(&vcpu->kvm->mmu_lock);
2024 kvm_release_pfn_clean(pfn);
2025 return 0;
10589a46
MT		 2026}
2027
2028
17ac10ad
AK		 2029static void mmu_free_roots(struct kvm_vcpu *vcpu)
2030{
2031 int i;
4db35314 2032 struct kvm_mmu_page *sp;
17ac10ad 2033
ad312c7c 2034 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
7b53aa56 2035 return;
aaee2c94 2036 spin_lock(&vcpu->kvm->mmu_lock);
ad312c7c
ZX		 2037 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2038 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad 2039
4db35314
AK		 2040 sp = page_header(root);
2041 --sp->root_count;
2e53d63a
MT		 2042 if (!sp->root_count && sp->role.invalid)
2043 kvm_mmu_zap_page(vcpu->kvm, sp);
ad312c7c 2044 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
aaee2c94 2045 spin_unlock(&vcpu->kvm->mmu_lock);
17ac10ad
AK		 2046 return;
2047 }
17ac10ad 2048 for (i = 0; i < 4; ++i) {
ad312c7c 2049 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad 2050
417726a3 2051 if (root) {
417726a3 2052 root &= PT64_BASE_ADDR_MASK;
4db35314
AK		 2053 sp = page_header(root);
2054 --sp->root_count;
2e53d63a
MT		 2055 if (!sp->root_count && sp->role.invalid)
2056 kvm_mmu_zap_page(vcpu->kvm, sp);
417726a3 2057 }
ad312c7c 2058 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2059 }
aaee2c94 2060 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2061 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
17ac10ad
AK		 2062}
2063
8986ecc0
MT		 2064static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2065{
2066 int ret = 0;
2067
2068 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2069 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2070 ret = 1;
2071 }
2072
2073 return ret;
2074}
2075
2076static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
17ac10ad
AK		 2077{
2078 int i;
cea0f0e7 2079 gfn_t root_gfn;
4db35314 2080 struct kvm_mmu_page *sp;
f6e2c02b 2081 int direct = 0;
6de4f3ad 2082 u64 pdptr;
3bb65a22 2083
ad312c7c 2084 root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT;
17ac10ad 2085
ad312c7c
ZX		 2086 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2087 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad
AK		 2088
2089 ASSERT(!VALID_PAGE(root));
fb72d167 2090 if (tdp_enabled)
f6e2c02b 2091 direct = 1;
8986ecc0
MT		 2092 if (mmu_check_root(vcpu, root_gfn))
2093 return 1;
4db35314 2094 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
f6e2c02b 2095 PT64_ROOT_LEVEL, direct,
fb72d167 2096 ACC_ALL, NULL);
4db35314
AK		 2097 root = __pa(sp->spt);
2098 ++sp->root_count;
ad312c7c 2099 vcpu->arch.mmu.root_hpa = root;
8986ecc0 2100 return 0;
17ac10ad 2101 }
f6e2c02b 2102 direct = !is_paging(vcpu);
fb72d167 2103 if (tdp_enabled)
f6e2c02b 2104 direct = 1;
17ac10ad 2105 for (i = 0; i < 4; ++i) {
ad312c7c 2106 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad
AK		 2107
2108 ASSERT(!VALID_PAGE(root));
ad312c7c 2109 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
6de4f3ad 2110 pdptr = kvm_pdptr_read(vcpu, i);
43a3795a 2111 if (!is_present_gpte(pdptr)) {
ad312c7c 2112 vcpu->arch.mmu.pae_root[i] = 0;
417726a3
AK		 2113 continue;
2114 }
6de4f3ad 2115 root_gfn = pdptr >> PAGE_SHIFT;
ad312c7c 2116 } else if (vcpu->arch.mmu.root_level == 0)
cea0f0e7 2117 root_gfn = 0;
8986ecc0
MT		 2118 if (mmu_check_root(vcpu, root_gfn))
2119 return 1;
4db35314 2120 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
f6e2c02b 2121 PT32_ROOT_LEVEL, direct,
f7d9c7b7 2122 ACC_ALL, NULL);
4db35314
AK		 2123 root = __pa(sp->spt);
2124 ++sp->root_count;
ad312c7c 2125 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
17ac10ad 2126 }
ad312c7c 2127 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
8986ecc0 2128 return 0;
17ac10ad
AK		 2129}
2130
0ba73cda
MT		 2131static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2132{
2133 int i;
2134 struct kvm_mmu_page *sp;
2135
2136 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2137 return;
2138 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2139 hpa_t root = vcpu->arch.mmu.root_hpa;
2140 sp = page_header(root);
2141 mmu_sync_children(vcpu, sp);
2142 return;
2143 }
2144 for (i = 0; i < 4; ++i) {
2145 hpa_t root = vcpu->arch.mmu.pae_root[i];
2146
8986ecc0 2147 if (root && VALID_PAGE(root)) {
0ba73cda
MT		 2148 root &= PT64_BASE_ADDR_MASK;
2149 sp = page_header(root);
2150 mmu_sync_children(vcpu, sp);
2151 }
2152 }
2153}
2154
2155void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2156{
2157 spin_lock(&vcpu->kvm->mmu_lock);
2158 mmu_sync_roots(vcpu);
6cffe8ca 2159 spin_unlock(&vcpu->kvm->mmu_lock);
0ba73cda
MT		 2160}
2161
6aa8b732
AK		 2162static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr)
2163{
2164 return vaddr;
2165}
2166
2167static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3f3e7124 2168 u32 error_code)
6aa8b732 2169{
e833240f 2170 gfn_t gfn;
e2dec939 2171 int r;
6aa8b732 2172
b8688d51 2173 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
e2dec939
AK		 2174 r = mmu_topup_memory_caches(vcpu);
2175 if (r)
2176 return r;
714b93da 2177
6aa8b732 2178 ASSERT(vcpu);
ad312c7c 2179 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2180
e833240f 2181 gfn = gva >> PAGE_SHIFT;
6aa8b732 2182
e833240f
AK		 2183 return nonpaging_map(vcpu, gva & PAGE_MASK,
2184 error_code & PFERR_WRITE_MASK, gfn);
6aa8b732
AK		 2185}
2186
fb72d167
JR		 2187static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
2188 u32 error_code)
2189{
35149e21 2190 pfn_t pfn;
fb72d167 2191 int r;
852e3c19 2192 int level;
05da4558 2193 gfn_t gfn = gpa >> PAGE_SHIFT;
e930bffe 2194 unsigned long mmu_seq;
fb72d167
JR		 2195
2196 ASSERT(vcpu);
2197 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2198
2199 r = mmu_topup_memory_caches(vcpu);
2200 if (r)
2201 return r;
2202
852e3c19
JR		 2203 level = mapping_level(vcpu, gfn);
2204
2205 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2206
e930bffe 2207 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2208 smp_rmb();
35149e21 2209 pfn = gfn_to_pfn(vcpu->kvm, gfn);
35149e21
AL		 2210 if (is_error_pfn(pfn)) {
2211 kvm_release_pfn_clean(pfn);
fb72d167
JR		 2212 return 1;
2213 }
2214 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2215 if (mmu_notifier_retry(vcpu, mmu_seq))
2216 goto out_unlock;
fb72d167
JR		 2217 kvm_mmu_free_some_pages(vcpu);
2218 r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
852e3c19 2219 level, gfn, pfn);
fb72d167 2220 spin_unlock(&vcpu->kvm->mmu_lock);
fb72d167
JR		 2221
2222 return r;
e930bffe
AA		 2223
2224out_unlock:
2225 spin_unlock(&vcpu->kvm->mmu_lock);
2226 kvm_release_pfn_clean(pfn);
2227 return 0;
fb72d167
JR		 2228}
2229
6aa8b732
AK		 2230static void nonpaging_free(struct kvm_vcpu *vcpu)
2231{
17ac10ad 2232 mmu_free_roots(vcpu);
6aa8b732
AK		 2233}
2234
2235static int nonpaging_init_context(struct kvm_vcpu *vcpu)
2236{
ad312c7c 2237 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2238
2239 context->new_cr3 = nonpaging_new_cr3;
2240 context->page_fault = nonpaging_page_fault;
6aa8b732
AK		 2241 context->gva_to_gpa = nonpaging_gva_to_gpa;
2242 context->free = nonpaging_free;
c7addb90 2243 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2244 context->sync_page = nonpaging_sync_page;
a7052897 2245 context->invlpg = nonpaging_invlpg;
cea0f0e7 2246 context->root_level = 0;
6aa8b732 2247 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2248 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2249 return 0;
2250}
2251
d835dfec 2252void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
6aa8b732 2253{
1165f5fe 2254 ++vcpu->stat.tlb_flush;
cbdd1bea 2255 kvm_x86_ops->tlb_flush(vcpu);
6aa8b732
AK		 2256}
2257
2258static void paging_new_cr3(struct kvm_vcpu *vcpu)
2259{
b8688d51 2260 pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3);
cea0f0e7 2261 mmu_free_roots(vcpu);
6aa8b732
AK		 2262}
2263
6aa8b732
AK		 2264static void inject_page_fault(struct kvm_vcpu *vcpu,
2265 u64 addr,
2266 u32 err_code)
2267{
c3c91fee 2268 kvm_inject_page_fault(vcpu, addr, err_code);
6aa8b732
AK		 2269}
2270
6aa8b732
AK		 2271static void paging_free(struct kvm_vcpu *vcpu)
2272{
2273 nonpaging_free(vcpu);
2274}
2275
82725b20
DE		 2276static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level)
2277{
2278 int bit7;
2279
2280 bit7 = (gpte >> 7) & 1;
2281 return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0;
2282}
2283
6aa8b732
AK		 2284#define PTTYPE 64
2285#include "paging_tmpl.h"
2286#undef PTTYPE
2287
2288#define PTTYPE 32
2289#include "paging_tmpl.h"
2290#undef PTTYPE
2291
82725b20
DE		 2292static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level)
2293{
2294 struct kvm_mmu *context = &vcpu->arch.mmu;
2295 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2296 u64 exb_bit_rsvd = 0;
2297
2298 if (!is_nx(vcpu))
2299 exb_bit_rsvd = rsvd_bits(63, 63);
2300 switch (level) {
2301 case PT32_ROOT_LEVEL:
2302 /* no rsvd bits for 2 level 4K page table entries */
2303 context->rsvd_bits_mask[0][1] = 0;
2304 context->rsvd_bits_mask[0][0] = 0;
2305 if (is_cpuid_PSE36())
2306 /* 36bits PSE 4MB page */
2307 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
2308 else
2309 /* 32 bits PSE 4MB page */
2310 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
29a4b933 2311 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE		 2312 break;
2313 case PT32E_ROOT_LEVEL:
20c466b5
DE		 2314 context->rsvd_bits_mask[0][2] =
2315 rsvd_bits(maxphyaddr, 63) |
2316 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
82725b20 2317 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2318 rsvd_bits(maxphyaddr, 62); /* PDE */
82725b20
DE		 2319 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2320 rsvd_bits(maxphyaddr, 62); /* PTE */
2321 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2322 rsvd_bits(maxphyaddr, 62) |
2323 rsvd_bits(13, 20); /* large page */
29a4b933 2324 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE		 2325 break;
2326 case PT64_ROOT_LEVEL:
2327 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
2328 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2329 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
2330 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2331 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2332 rsvd_bits(maxphyaddr, 51);
82725b20
DE		 2333 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2334 rsvd_bits(maxphyaddr, 51);
2335 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
e04da980
JR		 2336 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
2337 rsvd_bits(maxphyaddr, 51) |
2338 rsvd_bits(13, 29);
82725b20 2339 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4c26b4cd
SY		 2340 rsvd_bits(maxphyaddr, 51) |
2341 rsvd_bits(13, 20); /* large page */
29a4b933 2342 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE		 2343 break;
2344 }
2345}
2346
17ac10ad 2347static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level)
6aa8b732 2348{
ad312c7c 2349 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2350
2351 ASSERT(is_pae(vcpu));
2352 context->new_cr3 = paging_new_cr3;
2353 context->page_fault = paging64_page_fault;
6aa8b732 2354 context->gva_to_gpa = paging64_gva_to_gpa;
c7addb90 2355 context->prefetch_page = paging64_prefetch_page;
e8bc217a 2356 context->sync_page = paging64_sync_page;
a7052897 2357 context->invlpg = paging64_invlpg;
6aa8b732 2358 context->free = paging_free;
17ac10ad
AK		 2359 context->root_level = level;
2360 context->shadow_root_level = level;
17c3ba9d 2361 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2362 return 0;
2363}
2364
17ac10ad
AK		 2365static int paging64_init_context(struct kvm_vcpu *vcpu)
2366{
82725b20 2367 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
17ac10ad
AK		 2368 return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL);
2369}
2370
6aa8b732
AK		 2371static int paging32_init_context(struct kvm_vcpu *vcpu)
2372{
ad312c7c 2373 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732 2374
82725b20 2375 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
6aa8b732
AK		 2376 context->new_cr3 = paging_new_cr3;
2377 context->page_fault = paging32_page_fault;
6aa8b732
AK		 2378 context->gva_to_gpa = paging32_gva_to_gpa;
2379 context->free = paging_free;
c7addb90 2380 context->prefetch_page = paging32_prefetch_page;
e8bc217a 2381 context->sync_page = paging32_sync_page;
a7052897 2382 context->invlpg = paging32_invlpg;
6aa8b732
AK		 2383 context->root_level = PT32_ROOT_LEVEL;
2384 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2385 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2386 return 0;
2387}
2388
2389static int paging32E_init_context(struct kvm_vcpu *vcpu)
2390{
82725b20 2391 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
17ac10ad 2392 return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL);
6aa8b732
AK		 2393}
2394
fb72d167
JR		 2395static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
2396{
2397 struct kvm_mmu *context = &vcpu->arch.mmu;
2398
2399 context->new_cr3 = nonpaging_new_cr3;
2400 context->page_fault = tdp_page_fault;
2401 context->free = nonpaging_free;
2402 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2403 context->sync_page = nonpaging_sync_page;
a7052897 2404 context->invlpg = nonpaging_invlpg;
67253af5 2405 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
fb72d167
JR		 2406 context->root_hpa = INVALID_PAGE;
2407
2408 if (!is_paging(vcpu)) {
2409 context->gva_to_gpa = nonpaging_gva_to_gpa;
2410 context->root_level = 0;
2411 } else if (is_long_mode(vcpu)) {
82725b20 2412 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
fb72d167
JR		 2413 context->gva_to_gpa = paging64_gva_to_gpa;
2414 context->root_level = PT64_ROOT_LEVEL;
2415 } else if (is_pae(vcpu)) {
82725b20 2416 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
fb72d167
JR		 2417 context->gva_to_gpa = paging64_gva_to_gpa;
2418 context->root_level = PT32E_ROOT_LEVEL;
2419 } else {
82725b20 2420 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
fb72d167
JR		 2421 context->gva_to_gpa = paging32_gva_to_gpa;
2422 context->root_level = PT32_ROOT_LEVEL;
2423 }
2424
2425 return 0;
2426}
2427
2428static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
6aa8b732 2429{
a770f6f2
AK		 2430 int r;
2431
6aa8b732 2432 ASSERT(vcpu);
ad312c7c 2433 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732
AK		 2434
2435 if (!is_paging(vcpu))
a770f6f2 2436 r = nonpaging_init_context(vcpu);
a9058ecd 2437 else if (is_long_mode(vcpu))
a770f6f2 2438 r = paging64_init_context(vcpu);
6aa8b732 2439 else if (is_pae(vcpu))
a770f6f2 2440 r = paging32E_init_context(vcpu);
6aa8b732 2441 else
a770f6f2
AK		 2442 r = paging32_init_context(vcpu);
2443
2444 vcpu->arch.mmu.base_role.glevels = vcpu->arch.mmu.root_level;
2445
2446 return r;
6aa8b732
AK		 2447}
2448
fb72d167
JR		 2449static int init_kvm_mmu(struct kvm_vcpu *vcpu)
2450{
35149e21
AL		 2451 vcpu->arch.update_pte.pfn = bad_pfn;
2452
fb72d167
JR		 2453 if (tdp_enabled)
2454 return init_kvm_tdp_mmu(vcpu);
2455 else
2456 return init_kvm_softmmu(vcpu);
2457}
2458
6aa8b732
AK		 2459static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
2460{
2461 ASSERT(vcpu);
ad312c7c
ZX		 2462 if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
2463 vcpu->arch.mmu.free(vcpu);
2464 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
6aa8b732
AK		 2465 }
2466}
2467
2468int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
17c3ba9d
AK		 2469{
2470 destroy_kvm_mmu(vcpu);
2471 return init_kvm_mmu(vcpu);
2472}
8668a3c4 2473EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
17c3ba9d
AK		 2474
2475int kvm_mmu_load(struct kvm_vcpu *vcpu)
6aa8b732 2476{
714b93da
AK		 2477 int r;
2478
e2dec939 2479 r = mmu_topup_memory_caches(vcpu);
17c3ba9d
AK		 2480 if (r)
2481 goto out;
aaee2c94 2482 spin_lock(&vcpu->kvm->mmu_lock);
eb787d10 2483 kvm_mmu_free_some_pages(vcpu);
8986ecc0 2484 r = mmu_alloc_roots(vcpu);
0ba73cda 2485 mmu_sync_roots(vcpu);
aaee2c94 2486 spin_unlock(&vcpu->kvm->mmu_lock);
8986ecc0
MT		 2487 if (r)
2488 goto out;
3662cb1c 2489 /* set_cr3() should ensure TLB has been flushed */
ad312c7c 2490 kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
714b93da
AK		 2491out:
2492 return r;
6aa8b732 2493}
17c3ba9d
AK		 2494EXPORT_SYMBOL_GPL(kvm_mmu_load);
2495
2496void kvm_mmu_unload(struct kvm_vcpu *vcpu)
2497{
2498 mmu_free_roots(vcpu);
2499}
6aa8b732 2500
09072daf 2501static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
4db35314 2502 struct kvm_mmu_page *sp,
ac1b714e
AK		 2503 u64 *spte)
2504{
2505 u64 pte;
2506 struct kvm_mmu_page *child;
2507
2508 pte = *spte;
c7addb90 2509 if (is_shadow_present_pte(pte)) {
776e6633 2510 if (is_last_spte(pte, sp->role.level))
290fc38d 2511 rmap_remove(vcpu->kvm, spte);
ac1b714e
AK		 2512 else {
2513 child = page_header(pte & PT64_BASE_ADDR_MASK);
90cb0529 2514 mmu_page_remove_parent_pte(child, spte);
ac1b714e
AK		 2515 }
2516 }
d555c333 2517 __set_spte(spte, shadow_trap_nonpresent_pte);
05da4558
MT		 2518 if (is_large_pte(pte))
2519 --vcpu->kvm->stat.lpages;
ac1b714e
AK		 2520}
2521
0028425f 2522static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4db35314 2523 struct kvm_mmu_page *sp,
0028425f 2524 u64 *spte,
489f1d65 2525 const void *new)
0028425f 2526{
30945387 2527 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
7e4e4056
JR		 2528 ++vcpu->kvm->stat.mmu_pde_zapped;
2529 return;
30945387 2530 }
0028425f 2531
4cee5764 2532 ++vcpu->kvm->stat.mmu_pte_updated;
4db35314 2533 if (sp->role.glevels == PT32_ROOT_LEVEL)
489f1d65 2534 paging32_update_pte(vcpu, sp, spte, new);
0028425f 2535 else
489f1d65 2536 paging64_update_pte(vcpu, sp, spte, new);
0028425f
AK		 2537}
2538
79539cec
AK		 2539static bool need_remote_flush(u64 old, u64 new)
2540{
2541 if (!is_shadow_present_pte(old))
2542 return false;
2543 if (!is_shadow_present_pte(new))
2544 return true;
2545 if ((old ^ new) & PT64_BASE_ADDR_MASK)
2546 return true;
2547 old ^= PT64_NX_MASK;
2548 new ^= PT64_NX_MASK;
2549 return (old & ~new & PT64_PERM_MASK) != 0;
2550}
2551
2552static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, u64 old, u64 new)
2553{
2554 if (need_remote_flush(old, new))
2555 kvm_flush_remote_tlbs(vcpu->kvm);
2556 else
2557 kvm_mmu_flush_tlb(vcpu);
2558}
2559
12b7d28f
AK		 2560static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
2561{
ad312c7c 2562 u64 *spte = vcpu->arch.last_pte_updated;
12b7d28f 2563
7b52345e 2564 return !!(spte && (*spte & shadow_accessed_mask));
12b7d28f
AK		 2565}
2566
d7824fff
AK		 2567static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
2568 const u8 *new, int bytes)
2569{
2570 gfn_t gfn;
2571 int r;
2572 u64 gpte = 0;
35149e21 2573 pfn_t pfn;
d7824fff
AK		 2574
2575 if (bytes != 4 && bytes != 8)
2576 return;
2577
2578 /*
2579 * Assume that the pte write on a page table of the same type
2580 * as the current vcpu paging mode. This is nearly always true
2581 * (might be false while changing modes). Note it is verified later
2582 * by update_pte().
2583 */
2584 if (is_pae(vcpu)) {
2585 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
2586 if ((bytes == 4) && (gpa % 4 == 0)) {
2587 r = kvm_read_guest(vcpu->kvm, gpa & ~(u64)7, &gpte, 8);
2588 if (r)
2589 return;
2590 memcpy((void *)&gpte + (gpa % 8), new, 4);
2591 } else if ((bytes == 8) && (gpa % 8 == 0)) {
2592 memcpy((void *)&gpte, new, 8);
2593 }
2594 } else {
2595 if ((bytes == 4) && (gpa % 4 == 0))
2596 memcpy((void *)&gpte, new, 4);
2597 }
43a3795a 2598 if (!is_present_gpte(gpte))
d7824fff
AK		 2599 return;
2600 gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
72dc67a6 2601
e930bffe 2602 vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2603 smp_rmb();
35149e21 2604 pfn = gfn_to_pfn(vcpu->kvm, gfn);
72dc67a6 2605
35149e21
AL		 2606 if (is_error_pfn(pfn)) {
2607 kvm_release_pfn_clean(pfn);
d196e343
AK		 2608 return;
2609 }
d7824fff 2610 vcpu->arch.update_pte.gfn = gfn;
35149e21 2611 vcpu->arch.update_pte.pfn = pfn;
d7824fff
AK		 2612}
2613
1b7fcd32
AK		 2614static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
2615{
2616 u64 *spte = vcpu->arch.last_pte_updated;
2617
2618 if (spte
2619 && vcpu->arch.last_pte_gfn == gfn
2620 && shadow_accessed_mask
2621 && !(*spte & shadow_accessed_mask)
2622 && is_shadow_present_pte(*spte))
2623 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
2624}
2625
09072daf 2626void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
ad218f85
MT		 2627 const u8 *new, int bytes,
2628 bool guest_initiated)
da4a00f0 2629{
9b7a0325 2630 gfn_t gfn = gpa >> PAGE_SHIFT;
4db35314 2631 struct kvm_mmu_page *sp;
0e7bc4b9 2632 struct hlist_node *node, *n;
9b7a0325
AK		 2633 struct hlist_head *bucket;
2634 unsigned index;
489f1d65 2635 u64 entry, gentry;
9b7a0325 2636 u64 *spte;
9b7a0325 2637 unsigned offset = offset_in_page(gpa);
0e7bc4b9 2638 unsigned pte_size;
9b7a0325 2639 unsigned page_offset;
0e7bc4b9 2640 unsigned misaligned;
fce0657f 2641 unsigned quadrant;
9b7a0325 2642 int level;
86a5ba02 2643 int flooded = 0;
ac1b714e 2644 int npte;
489f1d65 2645 int r;
9b7a0325 2646
b8688d51 2647 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
d7824fff 2648 mmu_guess_page_from_pte_write(vcpu, gpa, new, bytes);
aaee2c94 2649 spin_lock(&vcpu->kvm->mmu_lock);
1b7fcd32 2650 kvm_mmu_access_page(vcpu, gfn);
eb787d10 2651 kvm_mmu_free_some_pages(vcpu);
4cee5764 2652 ++vcpu->kvm->stat.mmu_pte_write;
c7addb90 2653 kvm_mmu_audit(vcpu, "pre pte write");
ad218f85
MT		 2654 if (guest_initiated) {
2655 if (gfn == vcpu->arch.last_pt_write_gfn
2656 && !last_updated_pte_accessed(vcpu)) {
2657 ++vcpu->arch.last_pt_write_count;
2658 if (vcpu->arch.last_pt_write_count >= 3)
2659 flooded = 1;
2660 } else {
2661 vcpu->arch.last_pt_write_gfn = gfn;
2662 vcpu->arch.last_pt_write_count = 1;
2663 vcpu->arch.last_pte_updated = NULL;
2664 }
86a5ba02 2665 }
1ae0a13d 2666 index = kvm_page_table_hashfn(gfn);
f05e70ac 2667 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4db35314 2668 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) {
f6e2c02b 2669 if (sp->gfn != gfn || sp->role.direct || sp->role.invalid)
9b7a0325 2670 continue;
4db35314 2671 pte_size = sp->role.glevels == PT32_ROOT_LEVEL ? 4 : 8;
0e7bc4b9 2672 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
e925c5ba 2673 misaligned |= bytes < 4;
86a5ba02 2674 if (misaligned || flooded) {
0e7bc4b9
AK		 2675 /*
2676 * Misaligned accesses are too much trouble to fix
2677 * up; also, they usually indicate a page is not used
2678 * as a page table.
86a5ba02
AK		 2679 *
2680 * If we're seeing too many writes to a page,
2681 * it may no longer be a page table, or we may be
2682 * forking, in which case it is better to unmap the
2683 * page.
0e7bc4b9
AK		 2684 */
2685 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4db35314 2686 gpa, bytes, sp->role.word);
07385413
MT		 2687 if (kvm_mmu_zap_page(vcpu->kvm, sp))
2688 n = bucket->first;
4cee5764 2689 ++vcpu->kvm->stat.mmu_flooded;
0e7bc4b9
AK		 2690 continue;
2691 }
9b7a0325 2692 page_offset = offset;
4db35314 2693 level = sp->role.level;
ac1b714e 2694 npte = 1;
4db35314 2695 if (sp->role.glevels == PT32_ROOT_LEVEL) {
ac1b714e
AK		 2696 page_offset <<= 1; /* 32->64 */
2697 /*
2698 * A 32-bit pde maps 4MB while the shadow pdes map
2699 * only 2MB. So we need to double the offset again
2700 * and zap two pdes instead of one.
2701 */
2702 if (level == PT32_ROOT_LEVEL) {
6b8d0f9b 2703 page_offset &= ~7; /* kill rounding error */
ac1b714e
AK		 2704 page_offset <<= 1;
2705 npte = 2;
2706 }
fce0657f 2707 quadrant = page_offset >> PAGE_SHIFT;
9b7a0325 2708 page_offset &= ~PAGE_MASK;
4db35314 2709 if (quadrant != sp->role.quadrant)
fce0657f 2710 continue;
9b7a0325 2711 }
4db35314 2712 spte = &sp->spt[page_offset / sizeof(*spte)];
489f1d65
DE		 2713 if ((gpa & (pte_size - 1)) || (bytes < pte_size)) {
2714 gentry = 0;
2715 r = kvm_read_guest_atomic(vcpu->kvm,
2716 gpa & ~(u64)(pte_size - 1),
2717 &gentry, pte_size);
2718 new = (const void *)&gentry;
2719 if (r < 0)
2720 new = NULL;
2721 }
ac1b714e 2722 while (npte--) {
79539cec 2723 entry = *spte;
4db35314 2724 mmu_pte_write_zap_pte(vcpu, sp, spte);
489f1d65
DE		 2725 if (new)
2726 mmu_pte_write_new_pte(vcpu, sp, spte, new);
79539cec 2727 mmu_pte_write_flush_tlb(vcpu, entry, *spte);
ac1b714e 2728 ++spte;
9b7a0325 2729 }
9b7a0325 2730 }
c7addb90 2731 kvm_mmu_audit(vcpu, "post pte write");
aaee2c94 2732 spin_unlock(&vcpu->kvm->mmu_lock);
35149e21
AL		 2733 if (!is_error_pfn(vcpu->arch.update_pte.pfn)) {
2734 kvm_release_pfn_clean(vcpu->arch.update_pte.pfn);
2735 vcpu->arch.update_pte.pfn = bad_pfn;
d7824fff 2736 }
da4a00f0
AK		 2737}
2738
a436036b
AK		 2739int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2740{
10589a46
MT		 2741 gpa_t gpa;
2742 int r;
a436036b 2743
60f24784
AK		 2744 if (tdp_enabled)
2745 return 0;
2746
10589a46 2747 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva);
10589a46 2748
aaee2c94 2749 spin_lock(&vcpu->kvm->mmu_lock);
10589a46 2750 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
aaee2c94 2751 spin_unlock(&vcpu->kvm->mmu_lock);
10589a46 2752 return r;
a436036b 2753}
577bdc49 2754EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
a436036b 2755
22d95b12 2756void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
ebeace86 2757{
3b80fffe
IE		 2758 while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES &&
2759 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
4db35314 2760 struct kvm_mmu_page *sp;
ebeace86 2761
f05e70ac 2762 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
4db35314
AK		 2763 struct kvm_mmu_page, link);
2764 kvm_mmu_zap_page(vcpu->kvm, sp);
4cee5764 2765 ++vcpu->kvm->stat.mmu_recycled;
ebeace86
AK		 2766 }
2767}
ebeace86 2768
3067714c
AK		 2769int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
2770{
2771 int r;
2772 enum emulation_result er;
2773
ad312c7c 2774 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code);
3067714c
AK		 2775 if (r < 0)
2776 goto out;
2777
2778 if (!r) {
2779 r = 1;
2780 goto out;
2781 }
2782
b733bfb5
AK		 2783 r = mmu_topup_memory_caches(vcpu);
2784 if (r)
2785 goto out;
2786
851ba692 2787 er = emulate_instruction(vcpu, cr2, error_code, 0);
3067714c
AK		 2788
2789 switch (er) {
2790 case EMULATE_DONE:
2791 return 1;
2792 case EMULATE_DO_MMIO:
2793 ++vcpu->stat.mmio_exits;
2794 return 0;
2795 case EMULATE_FAIL:
3f5d18a9
AK		 2796 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2797 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
a9c7399d 2798 vcpu->run->internal.ndata = 0;
3f5d18a9 2799 return 0;
3067714c
AK		 2800 default:
2801 BUG();
2802 }
2803out:
3067714c
AK		 2804 return r;
2805}
2806EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
2807
a7052897
MT		 2808void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
2809{
a7052897 2810 vcpu->arch.mmu.invlpg(vcpu, gva);
a7052897
MT		 2811 kvm_mmu_flush_tlb(vcpu);
2812 ++vcpu->stat.invlpg;
2813}
2814EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
2815
18552672
JR		 2816void kvm_enable_tdp(void)
2817{
2818 tdp_enabled = true;
2819}
2820EXPORT_SYMBOL_GPL(kvm_enable_tdp);
2821
5f4cb662
JR		 2822void kvm_disable_tdp(void)
2823{
2824 tdp_enabled = false;
2825}
2826EXPORT_SYMBOL_GPL(kvm_disable_tdp);
2827
6aa8b732
AK		 2828static void free_mmu_pages(struct kvm_vcpu *vcpu)
2829{
ad312c7c 2830 free_page((unsigned long)vcpu->arch.mmu.pae_root);
6aa8b732
AK		 2831}
2832
2833static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
2834{
17ac10ad 2835 struct page *page;
6aa8b732
AK		 2836 int i;
2837
2838 ASSERT(vcpu);
2839
17ac10ad
AK		 2840 /*
2841 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
2842 * Therefore we need to allocate shadow page tables in the first
2843 * 4GB of memory, which happens to fit the DMA32 zone.
2844 */
2845 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
2846 if (!page)
2847 goto error_1;
ad312c7c 2848 vcpu->arch.mmu.pae_root = page_address(page);
17ac10ad 2849 for (i = 0; i < 4; ++i)
ad312c7c 2850 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2851
6aa8b732
AK		 2852 return 0;
2853
2854error_1:
2855 free_mmu_pages(vcpu);
2856 return -ENOMEM;
2857}
2858
8018c27b 2859int kvm_mmu_create(struct kvm_vcpu *vcpu)
6aa8b732 2860{
6aa8b732 2861 ASSERT(vcpu);
ad312c7c 2862 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2863
8018c27b
IM		 2864 return alloc_mmu_pages(vcpu);
2865}
6aa8b732 2866
8018c27b
IM		 2867int kvm_mmu_setup(struct kvm_vcpu *vcpu)
2868{
2869 ASSERT(vcpu);
ad312c7c 2870 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2c264957 2871
8018c27b 2872 return init_kvm_mmu(vcpu);
6aa8b732
AK		 2873}
2874
2875void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
2876{
2877 ASSERT(vcpu);
2878
2879 destroy_kvm_mmu(vcpu);
2880 free_mmu_pages(vcpu);
714b93da 2881 mmu_free_memory_caches(vcpu);
6aa8b732
AK		 2882}
2883
90cb0529 2884void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
6aa8b732 2885{
4db35314 2886 struct kvm_mmu_page *sp;
6aa8b732 2887
f05e70ac 2888 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
6aa8b732
AK		 2889 int i;
2890 u64 *pt;
2891
291f26bc 2892 if (!test_bit(slot, sp->slot_bitmap))
6aa8b732
AK		 2893 continue;
2894
4db35314 2895 pt = sp->spt;
6aa8b732
AK		 2896 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2897 /* avoid RMW */
9647c14c 2898 if (pt[i] & PT_WRITABLE_MASK)
6aa8b732 2899 pt[i] &= ~PT_WRITABLE_MASK;
6aa8b732 2900 }
171d595d 2901 kvm_flush_remote_tlbs(kvm);
6aa8b732 2902}
37a7d8b0 2903
90cb0529 2904void kvm_mmu_zap_all(struct kvm *kvm)
e0fa826f 2905{
4db35314 2906 struct kvm_mmu_page *sp, *node;
e0fa826f 2907
aaee2c94 2908 spin_lock(&kvm->mmu_lock);
f05e70ac 2909 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
07385413
MT		 2910 if (kvm_mmu_zap_page(kvm, sp))
2911 node = container_of(kvm->arch.active_mmu_pages.next,
2912 struct kvm_mmu_page, link);
aaee2c94 2913 spin_unlock(&kvm->mmu_lock);
e0fa826f 2914
90cb0529 2915 kvm_flush_remote_tlbs(kvm);
e0fa826f
DL		 2916}
2917
8b2cf73c 2918static void kvm_mmu_remove_one_alloc_mmu_page(struct kvm *kvm)
3ee16c81
IE		 2919{
2920 struct kvm_mmu_page *page;
2921
2922 page = container_of(kvm->arch.active_mmu_pages.prev,
2923 struct kvm_mmu_page, link);
2924 kvm_mmu_zap_page(kvm, page);
2925}
2926
2927static int mmu_shrink(int nr_to_scan, gfp_t gfp_mask)
2928{
2929 struct kvm *kvm;
2930 struct kvm *kvm_freed = NULL;
2931 int cache_count = 0;
2932
2933 spin_lock(&kvm_lock);
2934
2935 list_for_each_entry(kvm, &vm_list, vm_list) {
2936 int npages;
2937
5a4c9288
MT		 2938 if (!down_read_trylock(&kvm->slots_lock))
2939 continue;
3ee16c81
IE		 2940 spin_lock(&kvm->mmu_lock);
2941 npages = kvm->arch.n_alloc_mmu_pages -
2942 kvm->arch.n_free_mmu_pages;
2943 cache_count += npages;
2944 if (!kvm_freed && nr_to_scan > 0 && npages > 0) {
2945 kvm_mmu_remove_one_alloc_mmu_page(kvm);
2946 cache_count--;
2947 kvm_freed = kvm;
2948 }
2949 nr_to_scan--;
2950
2951 spin_unlock(&kvm->mmu_lock);
5a4c9288 2952 up_read(&kvm->slots_lock);
3ee16c81
IE		 2953 }
2954 if (kvm_freed)
2955 list_move_tail(&kvm_freed->vm_list, &vm_list);
2956
2957 spin_unlock(&kvm_lock);
2958
2959 return cache_count;
2960}
2961
2962static struct shrinker mmu_shrinker = {
2963 .shrink = mmu_shrink,
2964 .seeks = DEFAULT_SEEKS * 10,
2965};
2966
2ddfd20e 2967static void mmu_destroy_caches(void)
b5a33a75
AK		 2968{
2969 if (pte_chain_cache)
2970 kmem_cache_destroy(pte_chain_cache);
2971 if (rmap_desc_cache)
2972 kmem_cache_destroy(rmap_desc_cache);
d3d25b04
AK		 2973 if (mmu_page_header_cache)
2974 kmem_cache_destroy(mmu_page_header_cache);
b5a33a75
AK		 2975}
2976
3ee16c81
IE		 2977void kvm_mmu_module_exit(void)
2978{
2979 mmu_destroy_caches();
2980 unregister_shrinker(&mmu_shrinker);
2981}
2982
b5a33a75
AK		 2983int kvm_mmu_module_init(void)
2984{
2985 pte_chain_cache = kmem_cache_create("kvm_pte_chain",
2986 sizeof(struct kvm_pte_chain),
20c2df83 2987 0, 0, NULL);
b5a33a75
AK		 2988 if (!pte_chain_cache)
2989 goto nomem;
2990 rmap_desc_cache = kmem_cache_create("kvm_rmap_desc",
2991 sizeof(struct kvm_rmap_desc),
20c2df83 2992 0, 0, NULL);
b5a33a75
AK		 2993 if (!rmap_desc_cache)
2994 goto nomem;
2995
d3d25b04
AK		 2996 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
2997 sizeof(struct kvm_mmu_page),
20c2df83 2998 0, 0, NULL);
d3d25b04
AK		 2999 if (!mmu_page_header_cache)
3000 goto nomem;
3001
3ee16c81
IE		 3002 register_shrinker(&mmu_shrinker);
3003
b5a33a75
AK		 3004 return 0;
3005
3006nomem:
3ee16c81 3007 mmu_destroy_caches();
b5a33a75
AK		 3008 return -ENOMEM;
3009}
3010
3ad82a7e
ZX		 3011/*
3012 * Caculate mmu pages needed for kvm.
3013 */
3014unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3015{
3016 int i;
3017 unsigned int nr_mmu_pages;
3018 unsigned int nr_pages = 0;
bc6678a3 3019 struct kvm_memslots *slots;
3ad82a7e 3020
bc6678a3
MT		 3021 slots = rcu_dereference(kvm->memslots);
3022 for (i = 0; i < slots->nmemslots; i++)
3023 nr_pages += slots->memslots[i].npages;
3ad82a7e
ZX		 3024
3025 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3026 nr_mmu_pages = max(nr_mmu_pages,
3027 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3028
3029 return nr_mmu_pages;
3030}
3031
2f333bcb
MT		 3032static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3033 unsigned len)
3034{
3035 if (len > buffer->len)
3036 return NULL;
3037 return buffer->ptr;
3038}
3039
3040static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3041 unsigned len)
3042{
3043 void *ret;
3044
3045 ret = pv_mmu_peek_buffer(buffer, len);
3046 if (!ret)
3047 return ret;
3048 buffer->ptr += len;
3049 buffer->len -= len;
3050 buffer->processed += len;
3051 return ret;
3052}
3053
3054static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3055 gpa_t addr, gpa_t value)
3056{
3057 int bytes = 8;
3058 int r;
3059
3060 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3061 bytes = 4;
3062
3063 r = mmu_topup_memory_caches(vcpu);
3064 if (r)
3065 return r;
3066
3200f405 3067 if (!emulator_write_phys(vcpu, addr, &value, bytes))
2f333bcb
MT		 3068 return -EFAULT;
3069
3070 return 1;
3071}
3072
3073static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3074{
a8cd0244 3075 kvm_set_cr3(vcpu, vcpu->arch.cr3);
2f333bcb
MT		 3076 return 1;
3077}
3078
3079static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
3080{
3081 spin_lock(&vcpu->kvm->mmu_lock);
3082 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
3083 spin_unlock(&vcpu->kvm->mmu_lock);
3084 return 1;
3085}
3086
3087static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
3088 struct kvm_pv_mmu_op_buffer *buffer)
3089{
3090 struct kvm_mmu_op_header *header;
3091
3092 header = pv_mmu_peek_buffer(buffer, sizeof *header);
3093 if (!header)
3094 return 0;
3095 switch (header->op) {
3096 case KVM_MMU_OP_WRITE_PTE: {
3097 struct kvm_mmu_op_write_pte *wpte;
3098
3099 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
3100 if (!wpte)
3101 return 0;
3102 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
3103 wpte->pte_val);
3104 }
3105 case KVM_MMU_OP_FLUSH_TLB: {
3106 struct kvm_mmu_op_flush_tlb *ftlb;
3107
3108 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
3109 if (!ftlb)
3110 return 0;
3111 return kvm_pv_mmu_flush_tlb(vcpu);
3112 }
3113 case KVM_MMU_OP_RELEASE_PT: {
3114 struct kvm_mmu_op_release_pt *rpt;
3115
3116 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
3117 if (!rpt)
3118 return 0;
3119 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
3120 }
3121 default: return 0;
3122 }
3123}
3124
3125int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
3126 gpa_t addr, unsigned long *ret)
3127{
3128 int r;
6ad18fba 3129 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
2f333bcb 3130
6ad18fba
DH		 3131 buffer->ptr = buffer->buf;
3132 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
3133 buffer->processed = 0;
2f333bcb 3134
6ad18fba 3135 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
2f333bcb
MT		 3136 if (r)
3137 goto out;
3138
6ad18fba
DH		 3139 while (buffer->len) {
3140 r = kvm_pv_mmu_op_one(vcpu, buffer);
2f333bcb
MT		 3141 if (r < 0)
3142 goto out;
3143 if (r == 0)
3144 break;
3145 }
3146
3147 r = 1;
3148out:
6ad18fba 3149 *ret = buffer->processed;
2f333bcb
MT		 3150 return r;
3151}
3152
94d8b056
MT		 3153int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3154{
3155 struct kvm_shadow_walk_iterator iterator;
3156 int nr_sptes = 0;
3157
3158 spin_lock(&vcpu->kvm->mmu_lock);
3159 for_each_shadow_entry(vcpu, addr, iterator) {
3160 sptes[iterator.level-1] = *iterator.sptep;
3161 nr_sptes++;
3162 if (!is_shadow_present_pte(*iterator.sptep))
3163 break;
3164 }
3165 spin_unlock(&vcpu->kvm->mmu_lock);
3166
3167 return nr_sptes;
3168}
3169EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
3170
37a7d8b0
AK		 3171#ifdef AUDIT
3172
3173static const char *audit_msg;
3174
3175static gva_t canonicalize(gva_t gva)
3176{
3177#ifdef CONFIG_X86_64
3178 gva = (long long)(gva << 16) >> 16;
3179#endif
3180 return gva;
3181}
3182
08a3732b
MT		 3183
3184typedef void (*inspect_spte_fn) (struct kvm *kvm, struct kvm_mmu_page *sp,
3185 u64 *sptep);
3186
3187static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp,
3188 inspect_spte_fn fn)
3189{
3190 int i;
3191
3192 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3193 u64 ent = sp->spt[i];
3194
3195 if (is_shadow_present_pte(ent)) {
2920d728 3196 if (!is_last_spte(ent, sp->role.level)) {
08a3732b
MT		 3197 struct kvm_mmu_page *child;
3198 child = page_header(ent & PT64_BASE_ADDR_MASK);
3199 __mmu_spte_walk(kvm, child, fn);
2920d728 3200 } else
08a3732b
MT		 3201 fn(kvm, sp, &sp->spt[i]);
3202 }
3203 }
3204}
3205
3206static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn)
3207{
3208 int i;
3209 struct kvm_mmu_page *sp;
3210
3211 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3212 return;
3213 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3214 hpa_t root = vcpu->arch.mmu.root_hpa;
3215 sp = page_header(root);
3216 __mmu_spte_walk(vcpu->kvm, sp, fn);
3217 return;
3218 }
3219 for (i = 0; i < 4; ++i) {
3220 hpa_t root = vcpu->arch.mmu.pae_root[i];
3221
3222 if (root && VALID_PAGE(root)) {
3223 root &= PT64_BASE_ADDR_MASK;
3224 sp = page_header(root);
3225 __mmu_spte_walk(vcpu->kvm, sp, fn);
3226 }
3227 }
3228 return;
3229}
3230
37a7d8b0
AK		 3231static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte,
3232 gva_t va, int level)
3233{
3234 u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK);
3235 int i;
3236 gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1));
3237
3238 for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) {
3239 u64 ent = pt[i];
3240
c7addb90 3241 if (ent == shadow_trap_nonpresent_pte)
37a7d8b0
AK		 3242 continue;
3243
3244 va = canonicalize(va);
2920d728
MT		 3245 if (is_shadow_present_pte(ent) && !is_last_spte(ent, level))
3246 audit_mappings_page(vcpu, ent, va, level - 1);
3247 else {
ad312c7c 3248 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, va);
34382539
JK		 3249 gfn_t gfn = gpa >> PAGE_SHIFT;
3250 pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn);
3251 hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT;
37a7d8b0 3252
2aaf65e8
MT		 3253 if (is_error_pfn(pfn)) {
3254 kvm_release_pfn_clean(pfn);
3255 continue;
3256 }
3257
c7addb90 3258 if (is_shadow_present_pte(ent)
37a7d8b0 3259 && (ent & PT64_BASE_ADDR_MASK) != hpa)
c7addb90
AK		 3260 printk(KERN_ERR "xx audit error: (%s) levels %d"
3261 " gva %lx gpa %llx hpa %llx ent %llx %d\n",
ad312c7c 3262 audit_msg, vcpu->arch.mmu.root_level,
d77c26fc
MD		 3263 va, gpa, hpa, ent,
3264 is_shadow_present_pte(ent));
c7addb90
AK		 3265 else if (ent == shadow_notrap_nonpresent_pte
3266 && !is_error_hpa(hpa))
3267 printk(KERN_ERR "audit: (%s) notrap shadow,"
3268 " valid guest gva %lx\n", audit_msg, va);
35149e21 3269 kvm_release_pfn_clean(pfn);
c7addb90 3270
37a7d8b0
AK		 3271 }
3272 }
3273}
3274
3275static void audit_mappings(struct kvm_vcpu *vcpu)
3276{
1ea252af 3277 unsigned i;
37a7d8b0 3278
ad312c7c
ZX		 3279 if (vcpu->arch.mmu.root_level == 4)
3280 audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4);
37a7d8b0
AK		 3281 else
3282 for (i = 0; i < 4; ++i)
ad312c7c 3283 if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK)
37a7d8b0 3284 audit_mappings_page(vcpu,
ad312c7c 3285 vcpu->arch.mmu.pae_root[i],
37a7d8b0
AK		 3286 i << 30,
3287 2);
3288}
3289
3290static int count_rmaps(struct kvm_vcpu *vcpu)
3291{
3292 int nmaps = 0;
bc6678a3 3293 int i, j, k, idx;
37a7d8b0 3294
bc6678a3
MT		 3295 idx = srcu_read_lock(&kvm->srcu);
3296 slots = rcu_dereference(kvm->memslots);
37a7d8b0 3297 for (i = 0; i < KVM_MEMORY_SLOTS; ++i) {
bc6678a3 3298 struct kvm_memory_slot *m = &slots->memslots[i];
37a7d8b0
AK		 3299 struct kvm_rmap_desc *d;
3300
3301 for (j = 0; j < m->npages; ++j) {
290fc38d 3302 unsigned long *rmapp = &m->rmap[j];
37a7d8b0 3303
290fc38d 3304 if (!*rmapp)
37a7d8b0 3305 continue;
290fc38d 3306 if (!(*rmapp & 1)) {
37a7d8b0
AK		 3307 ++nmaps;
3308 continue;
3309 }
290fc38d 3310 d = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
37a7d8b0
AK		 3311 while (d) {
3312 for (k = 0; k < RMAP_EXT; ++k)
d555c333 3313 if (d->sptes[k])
37a7d8b0
AK		 3314 ++nmaps;
3315 else
3316 break;
3317 d = d->more;
3318 }
3319 }
3320 }
bc6678a3 3321 srcu_read_unlock(&kvm->srcu, idx);
37a7d8b0
AK		 3322 return nmaps;
3323}
3324
08a3732b
MT		 3325void inspect_spte_has_rmap(struct kvm *kvm, struct kvm_mmu_page *sp, u64 *sptep)
3326{
3327 unsigned long *rmapp;
3328 struct kvm_mmu_page *rev_sp;
3329 gfn_t gfn;
3330
3331 if (*sptep & PT_WRITABLE_MASK) {
3332 rev_sp = page_header(__pa(sptep));
3333 gfn = rev_sp->gfns[sptep - rev_sp->spt];
3334
3335 if (!gfn_to_memslot(kvm, gfn)) {
3336 if (!printk_ratelimit())
3337 return;
3338 printk(KERN_ERR "%s: no memslot for gfn %ld\n",
3339 audit_msg, gfn);
3340 printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n",
3341 audit_msg, sptep - rev_sp->spt,
3342 rev_sp->gfn);
3343 dump_stack();
3344 return;
3345 }
3346
2920d728
MT		 3347 rmapp = gfn_to_rmap(kvm, rev_sp->gfns[sptep - rev_sp->spt],
3348 is_large_pte(*sptep));
08a3732b
MT		 3349 if (!*rmapp) {
3350 if (!printk_ratelimit())
3351 return;
3352 printk(KERN_ERR "%s: no rmap for writable spte %llx\n",
3353 audit_msg, *sptep);
3354 dump_stack();
3355 }
3356 }
3357
3358}
3359
3360void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu)
3361{
3362 mmu_spte_walk(vcpu, inspect_spte_has_rmap);
3363}
3364
3365static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu)
37a7d8b0 3366{
4db35314 3367 struct kvm_mmu_page *sp;
37a7d8b0
AK		 3368 int i;
3369
f05e70ac 3370 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
4db35314 3371 u64 *pt = sp->spt;
37a7d8b0 3372
4db35314 3373 if (sp->role.level != PT_PAGE_TABLE_LEVEL)
37a7d8b0
AK		 3374 continue;
3375
3376 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3377 u64 ent = pt[i];
3378
3379 if (!(ent & PT_PRESENT_MASK))
3380 continue;
3381 if (!(ent & PT_WRITABLE_MASK))
3382 continue;
08a3732b 3383 inspect_spte_has_rmap(vcpu->kvm, sp, &pt[i]);
37a7d8b0
AK		 3384 }
3385 }
08a3732b 3386 return;
37a7d8b0
AK		 3387}
3388
3389static void audit_rmap(struct kvm_vcpu *vcpu)
3390{
08a3732b
MT		 3391 check_writable_mappings_rmap(vcpu);
3392 count_rmaps(vcpu);
37a7d8b0
AK		 3393}
3394
3395static void audit_write_protection(struct kvm_vcpu *vcpu)
3396{
4db35314 3397 struct kvm_mmu_page *sp;
290fc38d
IE		 3398 struct kvm_memory_slot *slot;
3399 unsigned long *rmapp;
e58b0f9e 3400 u64 *spte;
290fc38d 3401 gfn_t gfn;
37a7d8b0 3402
f05e70ac 3403 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
f6e2c02b 3404 if (sp->role.direct)
37a7d8b0 3405 continue;
e58b0f9e
MT		 3406 if (sp->unsync)
3407 continue;
37a7d8b0 3408
4db35314 3409 gfn = unalias_gfn(vcpu->kvm, sp->gfn);
2843099f 3410 slot = gfn_to_memslot_unaliased(vcpu->kvm, sp->gfn);
290fc38d 3411 rmapp = &slot->rmap[gfn - slot->base_gfn];
e58b0f9e
MT		 3412
3413 spte = rmap_next(vcpu->kvm, rmapp, NULL);
3414 while (spte) {
3415 if (*spte & PT_WRITABLE_MASK)
3416 printk(KERN_ERR "%s: (%s) shadow page has "
3417 "writable mappings: gfn %lx role %x\n",
b8688d51 3418 __func__, audit_msg, sp->gfn,
4db35314 3419 sp->role.word);
e58b0f9e
MT		 3420 spte = rmap_next(vcpu->kvm, rmapp, spte);
3421 }
37a7d8b0
AK		 3422 }
3423}
3424
3425static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg)
3426{
3427 int olddbg = dbg;
3428
3429 dbg = 0;
3430 audit_msg = msg;
3431 audit_rmap(vcpu);
3432 audit_write_protection(vcpu);
2aaf65e8
MT		 3433 if (strcmp("pre pte write", audit_msg) != 0)
3434 audit_mappings(vcpu);
08a3732b 3435 audit_writable_sptes_have_rmaps(vcpu);
37a7d8b0
AK		 3436 dbg = olddbg;
3437}
3438
3439#endif
Linux kernel - Deliverables
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