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drm/i915: Call drm helpers when duplicating crtc and plane states
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34};
35
45244b87
ED		 36/* HDMI/DVI modes ignore everything but the last 2 items. So we share
37 * them for both DP and FDI transports, allowing those ports to
38 * automatically adapt to HDMI connections as well
39 */
10122051
JN		 40static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
41 { 0x00FFFFFF, 0x0006000E },
42 { 0x00D75FFF, 0x0005000A },
43 { 0x00C30FFF, 0x00040006 },
44 { 0x80AAAFFF, 0x000B0000 },
45 { 0x00FFFFFF, 0x0005000A },
46 { 0x00D75FFF, 0x000C0004 },
47 { 0x80C30FFF, 0x000B0000 },
48 { 0x00FFFFFF, 0x00040006 },
49 { 0x80D75FFF, 0x000B0000 },
45244b87
ED		 50};
51
10122051
JN		 52static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
53 { 0x00FFFFFF, 0x0007000E },
54 { 0x00D75FFF, 0x000F000A },
55 { 0x00C30FFF, 0x00060006 },
56 { 0x00AAAFFF, 0x001E0000 },
57 { 0x00FFFFFF, 0x000F000A },
58 { 0x00D75FFF, 0x00160004 },
59 { 0x00C30FFF, 0x001E0000 },
60 { 0x00FFFFFF, 0x00060006 },
61 { 0x00D75FFF, 0x001E0000 },
6acab15a
PZ		 62};
63
10122051
JN		 64static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
65 /* Idx NT mV d T mV d db */
66 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */
67 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */
68 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */
69 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */
70 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */
71 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */
72 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */
73 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */
74 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */
75 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */
76 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */
77 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */
45244b87
ED		 78};
79
10122051
JN		 80static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
81 { 0x00FFFFFF, 0x00000012 },
82 { 0x00EBAFFF, 0x00020011 },
83 { 0x00C71FFF, 0x0006000F },
84 { 0x00AAAFFF, 0x000E000A },
85 { 0x00FFFFFF, 0x00020011 },
86 { 0x00DB6FFF, 0x0005000F },
87 { 0x00BEEFFF, 0x000A000C },
88 { 0x00FFFFFF, 0x0005000F },
89 { 0x00DB6FFF, 0x000A000C },
300644c7
PZ		 90};
91
10122051
JN		 92static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
93 { 0x00FFFFFF, 0x0007000E },
94 { 0x00D75FFF, 0x000E000A },
95 { 0x00BEFFFF, 0x00140006 },
96 { 0x80B2CFFF, 0x001B0002 },
97 { 0x00FFFFFF, 0x000E000A },
17b523ba 98 { 0x00DB6FFF, 0x00160005 },
6805b2a7 99 { 0x80C71FFF, 0x001A0002 },
10122051
JN		 100 { 0x00F7DFFF, 0x00180004 },
101 { 0x80D75FFF, 0x001B0002 },
e58623cb
AR		 102};
103
10122051
JN		 104static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
105 { 0x00FFFFFF, 0x0001000E },
106 { 0x00D75FFF, 0x0004000A },
107 { 0x00C30FFF, 0x00070006 },
108 { 0x00AAAFFF, 0x000C0000 },
109 { 0x00FFFFFF, 0x0004000A },
110 { 0x00D75FFF, 0x00090004 },
111 { 0x00C30FFF, 0x000C0000 },
112 { 0x00FFFFFF, 0x00070006 },
113 { 0x00D75FFF, 0x000C0000 },
e58623cb
AR		 114};
115
10122051
JN		 116static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
117 /* Idx NT mV d T mV df db */
118 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */
119 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */
120 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */
121 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */
122 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */
123 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */
124 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */
125 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */
126 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */
127 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */
a26aa8ba
DL		 128};
129
7f88e3af 130static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
6c930688
DL		 131 { 0x00000018, 0x000000a2 },
132 { 0x00004014, 0x0000009B },
7f88e3af 133 { 0x00006012, 0x00000088 },
6c930688
DL		 134 { 0x00008010, 0x00000087 },
135 { 0x00000018, 0x0000009B },
7f88e3af 136 { 0x00004014, 0x00000088 },
6c930688 137 { 0x00006012, 0x00000087 },
7f88e3af 138 { 0x00000018, 0x00000088 },
6c930688 139 { 0x00004014, 0x00000087 },
7f88e3af
DL		 140};
141
7ad14a29
SJ		 142/* eDP 1.4 low vswing translation parameters */
143static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
144 { 0x00000018, 0x000000a8 },
145 { 0x00002016, 0x000000ab },
146 { 0x00006012, 0x000000a2 },
147 { 0x00008010, 0x00000088 },
148 { 0x00000018, 0x000000ab },
149 { 0x00004014, 0x000000a2 },
150 { 0x00006012, 0x000000a6 },
151 { 0x00000018, 0x000000a2 },
152 { 0x00005013, 0x0000009c },
153 { 0x00000018, 0x00000088 },
154};
155
156
7f88e3af 157static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
b7192a56
SJ		 158 { 0x00000018, 0x000000ac },
159 { 0x00005012, 0x0000009d },
160 { 0x00007011, 0x00000088 },
161 { 0x00000018, 0x000000a1 },
162 { 0x00000018, 0x00000098 },
163 { 0x00004013, 0x00000088 },
164 { 0x00006012, 0x00000087 },
165 { 0x00000018, 0x000000df },
166 { 0x00003015, 0x00000087 },
167 { 0x00003015, 0x000000c7 },
168 { 0x00000018, 0x000000c7 },
7f88e3af
DL		 169};
170
96fb9f9b
VK		 171struct bxt_ddi_buf_trans {
172 u32 margin; /* swing value */
173 u32 scale; /* scale value */
174 u32 enable; /* scale enable */
175 u32 deemphasis;
176 bool default_index; /* true if the entry represents default value */
177};
178
179/* BSpec does not define separate vswing/pre-emphasis values for eDP.
180 * Using DP values for eDP as well.
181 */
182static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
183 /* Idx NT mV diff db */
184 { 52, 0, 0, 128, true }, /* 0: 400 0 */
185 { 78, 0, 0, 85, false }, /* 1: 400 3.5 */
186 { 104, 0, 0, 64, false }, /* 2: 400 6 */
187 { 154, 0, 0, 43, false }, /* 3: 400 9.5 */
188 { 77, 0, 0, 128, false }, /* 4: 600 0 */
189 { 116, 0, 0, 85, false }, /* 5: 600 3.5 */
190 { 154, 0, 0, 64, false }, /* 6: 600 6 */
191 { 102, 0, 0, 128, false }, /* 7: 800 0 */
192 { 154, 0, 0, 85, false }, /* 8: 800 3.5 */
193 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
194};
195
196/* BSpec has 2 recommended values - entries 0 and 8.
197 * Using the entry with higher vswing.
198 */
199static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
200 /* Idx NT mV diff db */
201 { 52, 0, 0, 128, false }, /* 0: 400 0 */
202 { 52, 0, 0, 85, false }, /* 1: 400 3.5 */
203 { 52, 0, 0, 64, false }, /* 2: 400 6 */
204 { 42, 0, 0, 43, false }, /* 3: 400 9.5 */
205 { 77, 0, 0, 128, false }, /* 4: 600 0 */
206 { 77, 0, 0, 85, false }, /* 5: 600 3.5 */
207 { 77, 0, 0, 64, false }, /* 6: 600 6 */
208 { 102, 0, 0, 128, false }, /* 7: 800 0 */
209 { 102, 0, 0, 85, false }, /* 8: 800 3.5 */
210 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
211};
212
a1e6ad66
ID		 213static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
214 struct intel_digital_port **dig_port,
215 enum port *port)
fc914639 216{
0bdee30e 217 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 218 int type = intel_encoder->type;
219
0e32b39c 220 if (type == INTEL_OUTPUT_DP_MST) {
a1e6ad66
ID		 221 *dig_port = enc_to_mst(encoder)->primary;
222 *port = (*dig_port)->port;
0e32b39c 223 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 224 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
a1e6ad66
ID		 225 *dig_port = enc_to_dig_port(encoder);
226 *port = (*dig_port)->port;
fc914639 227 } else if (type == INTEL_OUTPUT_ANALOG) {
a1e6ad66
ID		 228 *dig_port = NULL;
229 *port = PORT_E;
fc914639
PZ		 230 } else {
231 DRM_ERROR("Invalid DDI encoder type %d\n", type);
232 BUG();
233 }
234}
235
a1e6ad66
ID		 236enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
237{
238 struct intel_digital_port *dig_port;
239 enum port port;
240
241 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
242
243 return port;
244}
245
ce3b7e9b
DL		 246static bool
247intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
248{
249 return intel_dig_port->hdmi.hdmi_reg;
250}
251
e58623cb
AR		 252/*
253 * Starting with Haswell, DDI port buffers must be programmed with correct
254 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 255 * but the HDMI/DVI fields are shared among those. So we program the DDI
256 * in either FDI or DP modes only, as HDMI connections will work with both
257 * of those
258 */
faa0cdbe
ID		 259static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
260 bool supports_hdmi)
45244b87
ED		 261{
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 u32 reg;
7ff44670 264 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
7ad14a29 265 size;
6acab15a 266 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
10122051
JN		 267 const struct ddi_buf_trans *ddi_translations_fdi;
268 const struct ddi_buf_trans *ddi_translations_dp;
269 const struct ddi_buf_trans *ddi_translations_edp;
270 const struct ddi_buf_trans *ddi_translations_hdmi;
271 const struct ddi_buf_trans *ddi_translations;
e58623cb 272
96fb9f9b 273 if (IS_BROXTON(dev)) {
faa0cdbe 274 if (!supports_hdmi)
96fb9f9b
VK		 275 return;
276
277 /* Vswing programming for HDMI */
278 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
279 INTEL_OUTPUT_HDMI);
280 return;
281 } else if (IS_SKYLAKE(dev)) {
7f88e3af
DL		 282 ddi_translations_fdi = NULL;
283 ddi_translations_dp = skl_ddi_translations_dp;
7ad14a29 284 n_dp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
9e458034 285 if (dev_priv->edp_low_vswing) {
7ad14a29
SJ		 286 ddi_translations_edp = skl_ddi_translations_edp;
287 n_edp_entries = ARRAY_SIZE(skl_ddi_translations_edp);
288 } else {
289 ddi_translations_edp = skl_ddi_translations_dp;
290 n_edp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
291 }
292
7f88e3af
DL		 293 ddi_translations_hdmi = skl_ddi_translations_hdmi;
294 n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
b7192a56 295 hdmi_default_entry = 7;
7f88e3af 296 } else if (IS_BROADWELL(dev)) {
e58623cb
AR		 297 ddi_translations_fdi = bdw_ddi_translations_fdi;
298 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 299 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 300 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 301 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
302 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 303 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 304 hdmi_default_entry = 7;
e58623cb
AR		 305 } else if (IS_HASWELL(dev)) {
306 ddi_translations_fdi = hsw_ddi_translations_fdi;
307 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 308 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 309 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 310 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 311 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
7ff44670 312 hdmi_default_entry = 6;
e58623cb
AR		 313 } else {
314 WARN(1, "ddi translation table missing\n");
300644c7 315 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 316 ddi_translations_fdi = bdw_ddi_translations_fdi;
317 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 318 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 319 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
320 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 321 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 322 hdmi_default_entry = 7;
e58623cb
AR		 323 }
324
300644c7
PZ		 325 switch (port) {
326 case PORT_A:
327 ddi_translations = ddi_translations_edp;
7ad14a29 328 size = n_edp_entries;
300644c7
PZ		 329 break;
330 case PORT_B:
331 case PORT_C:
300644c7 332 ddi_translations = ddi_translations_dp;
7ad14a29 333 size = n_dp_entries;
300644c7 334 break;
77d8d009 335 case PORT_D:
7ad14a29 336 if (intel_dp_is_edp(dev, PORT_D)) {
77d8d009 337 ddi_translations = ddi_translations_edp;
7ad14a29
SJ		 338 size = n_edp_entries;
339 } else {
77d8d009 340 ddi_translations = ddi_translations_dp;
7ad14a29
SJ		 341 size = n_dp_entries;
342 }
77d8d009 343 break;
300644c7 344 case PORT_E:
7f88e3af
DL		 345 if (ddi_translations_fdi)
346 ddi_translations = ddi_translations_fdi;
347 else
348 ddi_translations = ddi_translations_dp;
7ad14a29 349 size = n_dp_entries;
300644c7
PZ		 350 break;
351 default:
352 BUG();
353 }
45244b87 354
7ad14a29 355 for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) {
10122051
JN		 356 I915_WRITE(reg, ddi_translations[i].trans1);
357 reg += 4;
358 I915_WRITE(reg, ddi_translations[i].trans2);
45244b87
ED		 359 reg += 4;
360 }
ce4dd49e 361
faa0cdbe 362 if (!supports_hdmi)
ce3b7e9b
DL		 363 return;
364
ce4dd49e
DL		 365 /* Choose a good default if VBT is badly populated */
366 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
367 hdmi_level >= n_hdmi_entries)
7ff44670 368 hdmi_level = hdmi_default_entry;
ce4dd49e 369
6acab15a 370 /* Entry 9 is for HDMI: */
10122051
JN		 371 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
372 reg += 4;
373 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
374 reg += 4;
45244b87
ED		 375}
376
377/* Program DDI buffers translations for DP. By default, program ports A-D in DP
378 * mode and port E for FDI.
379 */
380void intel_prepare_ddi(struct drm_device *dev)
381{
faa0cdbe 382 struct intel_encoder *intel_encoder;
b403745c 383 bool visited[I915_MAX_PORTS] = { 0, };
45244b87 384
0d536cb4
PZ		 385 if (!HAS_DDI(dev))
386 return;
45244b87 387
faa0cdbe
ID		 388 for_each_intel_encoder(dev, intel_encoder) {
389 struct intel_digital_port *intel_dig_port;
390 enum port port;
391 bool supports_hdmi;
392
393 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
394
395 if (visited[port])
b403745c
DL		 396 continue;
397
faa0cdbe
ID		 398 supports_hdmi = intel_dig_port &&
399 intel_dig_port_supports_hdmi(intel_dig_port);
400
401 intel_prepare_ddi_buffers(dev, port, supports_hdmi);
402 visited[port] = true;
b403745c 403 }
45244b87 404}
c82e4d26 405
248138b5
PZ		 406static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
407 enum port port)
408{
409 uint32_t reg = DDI_BUF_CTL(port);
410 int i;
411
3449ca85 412 for (i = 0; i < 16; i++) {
248138b5
PZ		 413 udelay(1);
414 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
415 return;
416 }
417 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
418}
c82e4d26
ED		 419
420/* Starting with Haswell, different DDI ports can work in FDI mode for
421 * connection to the PCH-located connectors. For this, it is necessary to train
422 * both the DDI port and PCH receiver for the desired DDI buffer settings.
423 *
424 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
425 * please note that when FDI mode is active on DDI E, it shares 2 lines with
426 * DDI A (which is used for eDP)
427 */
428
429void hsw_fdi_link_train(struct drm_crtc *crtc)
430{
431 struct drm_device *dev = crtc->dev;
432 struct drm_i915_private *dev_priv = dev->dev_private;
433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 434 u32 temp, i, rx_ctl_val;
c82e4d26 435
04945641
PZ		 436 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
437 * mode set "sequence for CRT port" document:
438 * - TP1 to TP2 time with the default value
439 * - FDI delay to 90h
8693a824
DL		 440 *
441 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641
PZ		 442 */
443 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
444 FDI_RX_PWRDN_LANE0_VAL(2) |
445 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
446
447 /* Enable the PCH Receiver FDI PLL */
3e68320e 448 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 449 FDI_RX_PLL_ENABLE |
6e3c9717 450 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
04945641
PZ		 451 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
452 POSTING_READ(_FDI_RXA_CTL);
453 udelay(220);
454
455 /* Switch from Rawclk to PCDclk */
456 rx_ctl_val |= FDI_PCDCLK;
457 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
458
459 /* Configure Port Clock Select */
6e3c9717
ACO		 460 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
461 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 462
463 /* Start the training iterating through available voltages and emphasis,
464 * testing each value twice. */
10122051 465 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 466 /* Configure DP_TP_CTL with auto-training */
467 I915_WRITE(DP_TP_CTL(PORT_E),
468 DP_TP_CTL_FDI_AUTOTRAIN |
469 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
470 DP_TP_CTL_LINK_TRAIN_PAT1 |
471 DP_TP_CTL_ENABLE);
472
876a8cdf
DL		 473 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
474 * DDI E does not support port reversal, the functionality is
475 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
476 * port reversal bit */
c82e4d26 477 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 478 DDI_BUF_CTL_ENABLE |
6e3c9717 479 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 480 DDI_BUF_TRANS_SELECT(i / 2));
04945641 481 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 482
483 udelay(600);
484
04945641
PZ		 485 /* Program PCH FDI Receiver TU */
486 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
487
488 /* Enable PCH FDI Receiver with auto-training */
489 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
490 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
491 POSTING_READ(_FDI_RXA_CTL);
492
493 /* Wait for FDI receiver lane calibration */
494 udelay(30);
495
496 /* Unset FDI_RX_MISC pwrdn lanes */
497 temp = I915_READ(_FDI_RXA_MISC);
498 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
499 I915_WRITE(_FDI_RXA_MISC, temp);
500 POSTING_READ(_FDI_RXA_MISC);
501
502 /* Wait for FDI auto training time */
503 udelay(5);
c82e4d26
ED		 504
505 temp = I915_READ(DP_TP_STATUS(PORT_E));
506 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 507 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 508
509 /* Enable normal pixel sending for FDI */
510 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 511 DP_TP_CTL_FDI_AUTOTRAIN |
512 DP_TP_CTL_LINK_TRAIN_NORMAL |
513 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
514 DP_TP_CTL_ENABLE);
c82e4d26 515
04945641 516 return;
c82e4d26 517 }
04945641 518
248138b5
PZ		 519 temp = I915_READ(DDI_BUF_CTL(PORT_E));
520 temp &= ~DDI_BUF_CTL_ENABLE;
521 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
522 POSTING_READ(DDI_BUF_CTL(PORT_E));
523
04945641 524 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 525 temp = I915_READ(DP_TP_CTL(PORT_E));
526 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
527 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
528 I915_WRITE(DP_TP_CTL(PORT_E), temp);
529 POSTING_READ(DP_TP_CTL(PORT_E));
530
531 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 532
533 rx_ctl_val &= ~FDI_RX_ENABLE;
534 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
248138b5 535 POSTING_READ(_FDI_RXA_CTL);
04945641
PZ		 536
537 /* Reset FDI_RX_MISC pwrdn lanes */
538 temp = I915_READ(_FDI_RXA_MISC);
539 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
540 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
541 I915_WRITE(_FDI_RXA_MISC, temp);
248138b5 542 POSTING_READ(_FDI_RXA_MISC);
c82e4d26
ED		 543 }
544
04945641 545 DRM_ERROR("FDI link training failed!\n");
c82e4d26 546}
0e72a5b5 547
44905a27
DA		 548void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
549{
550 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
551 struct intel_digital_port *intel_dig_port =
552 enc_to_dig_port(&encoder->base);
553
554 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 555 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
44905a27
DA		 556 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
557
558}
559
8d9ddbcb
PZ		 560static struct intel_encoder *
561intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
562{
563 struct drm_device *dev = crtc->dev;
564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
565 struct intel_encoder *intel_encoder, *ret = NULL;
566 int num_encoders = 0;
567
568 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
569 ret = intel_encoder;
570 num_encoders++;
571 }
572
573 if (num_encoders != 1)
84f44ce7
VS		 574 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
575 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 576
577 BUG_ON(ret == NULL);
578 return ret;
579}
580
bcddf610 581struct intel_encoder *
3165c074 582intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 583{
3165c074
ACO		 584 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
585 struct intel_encoder *ret = NULL;
586 struct drm_atomic_state *state;
d0737e1d 587 int num_encoders = 0;
3165c074 588 int i;
d0737e1d 589
3165c074
ACO		 590 state = crtc_state->base.state;
591
592 for (i = 0; i < state->num_connector; i++) {
593 if (!state->connectors[i] ||
594 state->connector_states[i]->crtc != crtc_state->base.crtc)
595 continue;
596
597 ret = to_intel_encoder(state->connector_states[i]->best_encoder);
598 num_encoders++;
d0737e1d
ACO		 599 }
600
601 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
602 pipe_name(crtc->pipe));
603
604 BUG_ON(ret == NULL);
605 return ret;
606}
607
1c0b85c5 608#define LC_FREQ 2700
27893390 609#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
1c0b85c5
DL		 610
611#define P_MIN 2
612#define P_MAX 64
613#define P_INC 2
614
615/* Constraints for PLL good behavior */
616#define REF_MIN 48
617#define REF_MAX 400
618#define VCO_MIN 2400
619#define VCO_MAX 4800
620
27893390
DL		 621#define abs_diff(a, b) ({ \
622 typeof(a) __a = (a); \
623 typeof(b) __b = (b); \
624 (void) (&__a == &__b); \
625 __a > __b ? (__a - __b) : (__b - __a); })
1c0b85c5
DL		 626
627struct wrpll_rnp {
628 unsigned p, n2, r2;
629};
630
631static unsigned wrpll_get_budget_for_freq(int clock)
6441ab5f 632{
1c0b85c5
DL		 633 unsigned budget;
634
635 switch (clock) {
636 case 25175000:
637 case 25200000:
638 case 27000000:
639 case 27027000:
640 case 37762500:
641 case 37800000:
642 case 40500000:
643 case 40541000:
644 case 54000000:
645 case 54054000:
646 case 59341000:
647 case 59400000:
648 case 72000000:
649 case 74176000:
650 case 74250000:
651 case 81000000:
652 case 81081000:
653 case 89012000:
654 case 89100000:
655 case 108000000:
656 case 108108000:
657 case 111264000:
658 case 111375000:
659 case 148352000:
660 case 148500000:
661 case 162000000:
662 case 162162000:
663 case 222525000:
664 case 222750000:
665 case 296703000:
666 case 297000000:
667 budget = 0;
668 break;
669 case 233500000:
670 case 245250000:
671 case 247750000:
672 case 253250000:
673 case 298000000:
674 budget = 1500;
675 break;
676 case 169128000:
677 case 169500000:
678 case 179500000:
679 case 202000000:
680 budget = 2000;
681 break;
682 case 256250000:
683 case 262500000:
684 case 270000000:
685 case 272500000:
686 case 273750000:
687 case 280750000:
688 case 281250000:
689 case 286000000:
690 case 291750000:
691 budget = 4000;
692 break;
693 case 267250000:
694 case 268500000:
695 budget = 5000;
696 break;
697 default:
698 budget = 1000;
699 break;
700 }
6441ab5f 701
1c0b85c5
DL		 702 return budget;
703}
704
705static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
706 unsigned r2, unsigned n2, unsigned p,
707 struct wrpll_rnp *best)
708{
709 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 710
1c0b85c5
DL		 711 /* No best (r,n,p) yet */
712 if (best->p == 0) {
713 best->p = p;
714 best->n2 = n2;
715 best->r2 = r2;
716 return;
717 }
6441ab5f 718
1c0b85c5
DL		 719 /*
720 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
721 * freq2k.
722 *
723 * delta = 1e6 *
724 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
725 * freq2k;
726 *
727 * and we would like delta <= budget.
728 *
729 * If the discrepancy is above the PPM-based budget, always prefer to
730 * improve upon the previous solution. However, if you're within the
731 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
732 */
733 a = freq2k * budget * p * r2;
734 b = freq2k * budget * best->p * best->r2;
27893390
DL		 735 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
736 diff_best = abs_diff(freq2k * best->p * best->r2,
737 LC_FREQ_2K * best->n2);
1c0b85c5
DL		 738 c = 1000000 * diff;
739 d = 1000000 * diff_best;
740
741 if (a < c && b < d) {
742 /* If both are above the budget, pick the closer */
743 if (best->p * best->r2 * diff < p * r2 * diff_best) {
744 best->p = p;
745 best->n2 = n2;
746 best->r2 = r2;
747 }
748 } else if (a >= c && b < d) {
749 /* If A is below the threshold but B is above it? Update. */
750 best->p = p;
751 best->n2 = n2;
752 best->r2 = r2;
753 } else if (a >= c && b >= d) {
754 /* Both are below the limit, so pick the higher n2/(r2*r2) */
755 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
756 best->p = p;
757 best->n2 = n2;
758 best->r2 = r2;
759 }
760 }
761 /* Otherwise a < c && b >= d, do nothing */
762}
763
11578553
JB		 764static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
765 int reg)
766{
767 int refclk = LC_FREQ;
768 int n, p, r;
769 u32 wrpll;
770
771 wrpll = I915_READ(reg);
114fe488
DV		 772 switch (wrpll & WRPLL_PLL_REF_MASK) {
773 case WRPLL_PLL_SSC:
774 case WRPLL_PLL_NON_SSC:
11578553
JB		 775 /*
776 * We could calculate spread here, but our checking
777 * code only cares about 5% accuracy, and spread is a max of
778 * 0.5% downspread.
779 */
780 refclk = 135;
781 break;
114fe488 782 case WRPLL_PLL_LCPLL:
11578553
JB		 783 refclk = LC_FREQ;
784 break;
785 default:
786 WARN(1, "bad wrpll refclk\n");
787 return 0;
788 }
789
790 r = wrpll & WRPLL_DIVIDER_REF_MASK;
791 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
792 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
793
20f0ec16
JB		 794 /* Convert to KHz, p & r have a fixed point portion */
795 return (refclk * n * 100) / (p * r);
11578553
JB		 796}
797
540e732c
S		 798static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
799 uint32_t dpll)
800{
801 uint32_t cfgcr1_reg, cfgcr2_reg;
802 uint32_t cfgcr1_val, cfgcr2_val;
803 uint32_t p0, p1, p2, dco_freq;
804
805 cfgcr1_reg = GET_CFG_CR1_REG(dpll);
806 cfgcr2_reg = GET_CFG_CR2_REG(dpll);
807
808 cfgcr1_val = I915_READ(cfgcr1_reg);
809 cfgcr2_val = I915_READ(cfgcr2_reg);
810
811 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
812 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
813
814 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
815 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
816 else
817 p1 = 1;
818
819
820 switch (p0) {
821 case DPLL_CFGCR2_PDIV_1:
822 p0 = 1;
823 break;
824 case DPLL_CFGCR2_PDIV_2:
825 p0 = 2;
826 break;
827 case DPLL_CFGCR2_PDIV_3:
828 p0 = 3;
829 break;
830 case DPLL_CFGCR2_PDIV_7:
831 p0 = 7;
832 break;
833 }
834
835 switch (p2) {
836 case DPLL_CFGCR2_KDIV_5:
837 p2 = 5;
838 break;
839 case DPLL_CFGCR2_KDIV_2:
840 p2 = 2;
841 break;
842 case DPLL_CFGCR2_KDIV_3:
843 p2 = 3;
844 break;
845 case DPLL_CFGCR2_KDIV_1:
846 p2 = 1;
847 break;
848 }
849
850 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
851
852 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
853 1000) / 0x8000;
854
855 return dco_freq / (p0 * p1 * p2 * 5);
856}
857
858
859static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 860 struct intel_crtc_state *pipe_config)
540e732c
S		 861{
862 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 863 int link_clock = 0;
864 uint32_t dpll_ctl1, dpll;
865
134ffa44 866 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 867
868 dpll_ctl1 = I915_READ(DPLL_CTRL1);
869
870 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
871 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
872 } else {
71cd8423
DL		 873 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
874 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 875
876 switch (link_clock) {
71cd8423 877 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 878 link_clock = 81000;
879 break;
71cd8423 880 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 881 link_clock = 108000;
882 break;
71cd8423 883 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 884 link_clock = 135000;
885 break;
71cd8423 886 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 887 link_clock = 162000;
888 break;
71cd8423 889 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 890 link_clock = 216000;
891 break;
71cd8423 892 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 893 link_clock = 270000;
894 break;
895 default:
896 WARN(1, "Unsupported link rate\n");
897 break;
898 }
899 link_clock *= 2;
900 }
901
902 pipe_config->port_clock = link_clock;
903
904 if (pipe_config->has_dp_encoder)
2d112de7 905 pipe_config->base.adjusted_mode.crtc_clock =
540e732c
S		 906 intel_dotclock_calculate(pipe_config->port_clock,
907 &pipe_config->dp_m_n);
908 else
2d112de7 909 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
540e732c
S		 910}
911
3d51278a 912static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 913 struct intel_crtc_state *pipe_config)
11578553
JB		 914{
915 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 916 int link_clock = 0;
917 u32 val, pll;
918
26804afd 919 val = pipe_config->ddi_pll_sel;
11578553
JB		 920 switch (val & PORT_CLK_SEL_MASK) {
921 case PORT_CLK_SEL_LCPLL_810:
922 link_clock = 81000;
923 break;
924 case PORT_CLK_SEL_LCPLL_1350:
925 link_clock = 135000;
926 break;
927 case PORT_CLK_SEL_LCPLL_2700:
928 link_clock = 270000;
929 break;
930 case PORT_CLK_SEL_WRPLL1:
931 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
932 break;
933 case PORT_CLK_SEL_WRPLL2:
934 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
935 break;
936 case PORT_CLK_SEL_SPLL:
937 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
938 if (pll == SPLL_PLL_FREQ_810MHz)
939 link_clock = 81000;
940 else if (pll == SPLL_PLL_FREQ_1350MHz)
941 link_clock = 135000;
942 else if (pll == SPLL_PLL_FREQ_2700MHz)
943 link_clock = 270000;
944 else {
945 WARN(1, "bad spll freq\n");
946 return;
947 }
948 break;
949 default:
950 WARN(1, "bad port clock sel\n");
951 return;
952 }
953
954 pipe_config->port_clock = link_clock * 2;
955
956 if (pipe_config->has_pch_encoder)
2d112de7 957 pipe_config->base.adjusted_mode.crtc_clock =
11578553
JB		 958 intel_dotclock_calculate(pipe_config->port_clock,
959 &pipe_config->fdi_m_n);
960 else if (pipe_config->has_dp_encoder)
2d112de7 961 pipe_config->base.adjusted_mode.crtc_clock =
11578553
JB		 962 intel_dotclock_calculate(pipe_config->port_clock,
963 &pipe_config->dp_m_n);
964 else
2d112de7 965 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
11578553
JB		 966}
967
977bb38d
S		 968static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
969 enum intel_dpll_id dpll)
970{
971 /* FIXME formula not available in bspec */
972 return 0;
973}
974
975static void bxt_ddi_clock_get(struct intel_encoder *encoder,
976 struct intel_crtc_state *pipe_config)
977{
978 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
979 enum port port = intel_ddi_get_encoder_port(encoder);
980 uint32_t dpll = port;
981
982 pipe_config->port_clock =
983 bxt_calc_pll_link(dev_priv, dpll);
984
985 if (pipe_config->has_dp_encoder)
986 pipe_config->base.adjusted_mode.crtc_clock =
987 intel_dotclock_calculate(pipe_config->port_clock,
988 &pipe_config->dp_m_n);
989 else
990 pipe_config->base.adjusted_mode.crtc_clock =
991 pipe_config->port_clock;
992}
993
3d51278a 994void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 995 struct intel_crtc_state *pipe_config)
3d51278a 996{
22606a18
DL		 997 struct drm_device *dev = encoder->base.dev;
998
999 if (INTEL_INFO(dev)->gen <= 8)
1000 hsw_ddi_clock_get(encoder, pipe_config);
977bb38d 1001 else if (IS_SKYLAKE(dev))
22606a18 1002 skl_ddi_clock_get(encoder, pipe_config);
977bb38d
S		 1003 else if (IS_BROXTON(dev))
1004 bxt_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1005}
1006
1c0b85c5 1007static void
d664c0ce
DL		 1008hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1009 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1c0b85c5
DL		 1010{
1011 uint64_t freq2k;
1012 unsigned p, n2, r2;
1013 struct wrpll_rnp best = { 0, 0, 0 };
1014 unsigned budget;
1015
1016 freq2k = clock / 100;
1017
1018 budget = wrpll_get_budget_for_freq(clock);
1019
1020 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1021 * and directly pass the LC PLL to it. */
1022 if (freq2k == 5400000) {
1023 *n2_out = 2;
1024 *p_out = 1;
1025 *r2_out = 2;
1026 return;
1027 }
1028
1029 /*
1030 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1031 * the WR PLL.
1032 *
1033 * We want R so that REF_MIN <= Ref <= REF_MAX.
1034 * Injecting R2 = 2 * R gives:
1035 * REF_MAX * r2 > LC_FREQ * 2 and
1036 * REF_MIN * r2 < LC_FREQ * 2
1037 *
1038 * Which means the desired boundaries for r2 are:
1039 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1040 *
1041 */
1042 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1043 r2 <= LC_FREQ * 2 / REF_MIN;
1044 r2++) {
1045
1046 /*
1047 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1048 *
1049 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1050 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1051 * VCO_MAX * r2 > n2 * LC_FREQ and
1052 * VCO_MIN * r2 < n2 * LC_FREQ)
1053 *
1054 * Which means the desired boundaries for n2 are:
1055 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1056 */
1057 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1058 n2 <= VCO_MAX * r2 / LC_FREQ;
1059 n2++) {
1060
1061 for (p = P_MIN; p <= P_MAX; p += P_INC)
1062 wrpll_update_rnp(freq2k, budget,
1063 r2, n2, p, &best);
1064 }
1065 }
6441ab5f 1066
1c0b85c5
DL		 1067 *n2_out = best.n2;
1068 *p_out = best.p;
1069 *r2_out = best.r2;
6441ab5f
PZ		 1070}
1071
0220ab6e 1072static bool
d664c0ce 1073hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1074 struct intel_crtc_state *crtc_state,
d664c0ce
DL		 1075 struct intel_encoder *intel_encoder,
1076 int clock)
6441ab5f 1077{
d664c0ce 1078 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
e0b01be4 1079 struct intel_shared_dpll *pll;
716c2e55 1080 uint32_t val;
1c0b85c5 1081 unsigned p, n2, r2;
6441ab5f 1082
d664c0ce 1083 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
0694001b 1084
114fe488 1085 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
0694001b
PZ		 1086 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1087 WRPLL_DIVIDER_POST(p);
1088
190f68c5 1089 crtc_state->dpll_hw_state.wrpll = val;
6441ab5f 1090
190f68c5 1091 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
716c2e55
DV		 1092 if (pll == NULL) {
1093 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1094 pipe_name(intel_crtc->pipe));
1095 return false;
0694001b 1096 }
d452c5b6 1097
190f68c5 1098 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
6441ab5f
PZ		 1099 }
1100
6441ab5f
PZ		 1101 return true;
1102}
1103
82d35437
S		 1104struct skl_wrpll_params {
1105 uint32_t dco_fraction;
1106 uint32_t dco_integer;
1107 uint32_t qdiv_ratio;
1108 uint32_t qdiv_mode;
1109 uint32_t kdiv;
1110 uint32_t pdiv;
1111 uint32_t central_freq;
1112};
1113
1114static void
1115skl_ddi_calculate_wrpll(int clock /* in Hz */,
1116 struct skl_wrpll_params *wrpll_params)
1117{
1118 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
21318cce
DL		 1119 uint64_t dco_central_freq[3] = {8400000000ULL,
1120 9000000000ULL,
1121 9600000000ULL};
82d35437
S		 1122 uint32_t min_dco_deviation = 400;
1123 uint32_t min_dco_index = 3;
1124 uint32_t P0[4] = {1, 2, 3, 7};
1125 uint32_t P2[4] = {1, 2, 3, 5};
1126 bool found = false;
1127 uint32_t candidate_p = 0;
1128 uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0};
1129 uint32_t candidate_p2[3] = {0};
1130 uint32_t dco_central_freq_deviation[3];
1131 uint32_t i, P1, k, dco_count;
1132 bool retry_with_odd = false;
1133 uint64_t dco_freq;
1134
1135 /* Determine P0, P1 or P2 */
1136 for (dco_count = 0; dco_count < 3; dco_count++) {
1137 found = false;
1138 candidate_p =
1139 div64_u64(dco_central_freq[dco_count], afe_clock);
1140 if (retry_with_odd == false)
1141 candidate_p = (candidate_p % 2 == 0 ?
1142 candidate_p : candidate_p + 1);
1143
1144 for (P1 = 1; P1 < candidate_p; P1++) {
1145 for (i = 0; i < 4; i++) {
1146 if (!(P0[i] != 1 || P1 == 1))
1147 continue;
1148
1149 for (k = 0; k < 4; k++) {
1150 if (P1 != 1 && P2[k] != 2)
1151 continue;
1152
1153 if (candidate_p == P0[i] * P1 * P2[k]) {
1154 /* Found possible P0, P1, P2 */
1155 found = true;
1156 candidate_p0[dco_count] = P0[i];
1157 candidate_p1[dco_count] = P1;
1158 candidate_p2[dco_count] = P2[k];
1159 goto found;
1160 }
1161
1162 }
1163 }
1164 }
1165
1166found:
1167 if (found) {
1168 dco_central_freq_deviation[dco_count] =
1169 div64_u64(10000 *
1170 abs_diff((candidate_p * afe_clock),
1171 dco_central_freq[dco_count]),
1172 dco_central_freq[dco_count]);
1173
1174 if (dco_central_freq_deviation[dco_count] <
1175 min_dco_deviation) {
1176 min_dco_deviation =
1177 dco_central_freq_deviation[dco_count];
1178 min_dco_index = dco_count;
1179 }
1180 }
1181
1182 if (min_dco_index > 2 && dco_count == 2) {
1183 retry_with_odd = true;
1184 dco_count = 0;
1185 }
1186 }
1187
1188 if (min_dco_index > 2) {
1189 WARN(1, "No valid values found for the given pixel clock\n");
1190 } else {
1191 wrpll_params->central_freq = dco_central_freq[min_dco_index];
1192
1193 switch (dco_central_freq[min_dco_index]) {
21318cce 1194 case 9600000000ULL:
82d35437
S		 1195 wrpll_params->central_freq = 0;
1196 break;
21318cce 1197 case 9000000000ULL:
82d35437
S		 1198 wrpll_params->central_freq = 1;
1199 break;
21318cce 1200 case 8400000000ULL:
82d35437
S		 1201 wrpll_params->central_freq = 3;
1202 }
1203
1204 switch (candidate_p0[min_dco_index]) {
1205 case 1:
1206 wrpll_params->pdiv = 0;
1207 break;
1208 case 2:
1209 wrpll_params->pdiv = 1;
1210 break;
1211 case 3:
1212 wrpll_params->pdiv = 2;
1213 break;
1214 case 7:
1215 wrpll_params->pdiv = 4;
1216 break;
1217 default:
1218 WARN(1, "Incorrect PDiv\n");
1219 }
1220
1221 switch (candidate_p2[min_dco_index]) {
1222 case 5:
1223 wrpll_params->kdiv = 0;
1224 break;
1225 case 2:
1226 wrpll_params->kdiv = 1;
1227 break;
1228 case 3:
1229 wrpll_params->kdiv = 2;
1230 break;
1231 case 1:
1232 wrpll_params->kdiv = 3;
1233 break;
1234 default:
1235 WARN(1, "Incorrect KDiv\n");
1236 }
1237
1238 wrpll_params->qdiv_ratio = candidate_p1[min_dco_index];
1239 wrpll_params->qdiv_mode =
1240 (wrpll_params->qdiv_ratio == 1) ? 0 : 1;
1241
1242 dco_freq = candidate_p0[min_dco_index] *
1243 candidate_p1[min_dco_index] *
1244 candidate_p2[min_dco_index] * afe_clock;
1245
1246 /*
1247 * Intermediate values are in Hz.
1248 * Divide by MHz to match bsepc
1249 */
1250 wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1)));
1251 wrpll_params->dco_fraction =
1252 div_u64(((div_u64(dco_freq, 24) -
1253 wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1));
1254
1255 }
1256}
1257
1258
1259static bool
1260skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1261 struct intel_crtc_state *crtc_state,
82d35437
S		 1262 struct intel_encoder *intel_encoder,
1263 int clock)
1264{
1265 struct intel_shared_dpll *pll;
1266 uint32_t ctrl1, cfgcr1, cfgcr2;
1267
1268 /*
1269 * See comment in intel_dpll_hw_state to understand why we always use 0
1270 * as the DPLL id in this function.
1271 */
1272
1273 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1274
1275 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1276 struct skl_wrpll_params wrpll_params = { 0, };
1277
1278 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1279
1280 skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params);
1281
1282 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1283 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1284 wrpll_params.dco_integer;
1285
1286 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1287 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1288 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1289 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1290 wrpll_params.central_freq;
1291 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1292 struct drm_encoder *encoder = &intel_encoder->base;
1293 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1294
1295 switch (intel_dp->link_bw) {
1296 case DP_LINK_BW_1_62:
71cd8423 1297 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
82d35437
S		 1298 break;
1299 case DP_LINK_BW_2_7:
71cd8423 1300 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
82d35437
S		 1301 break;
1302 case DP_LINK_BW_5_4:
71cd8423 1303 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
82d35437
S		 1304 break;
1305 }
1306
1307 cfgcr1 = cfgcr2 = 0;
1308 } else /* eDP */
1309 return true;
1310
190f68c5
ACO		 1311 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1312 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1313 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
82d35437 1314
190f68c5 1315 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
82d35437
S		 1316 if (pll == NULL) {
1317 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1318 pipe_name(intel_crtc->pipe));
1319 return false;
1320 }
1321
1322 /* shared DPLL id 0 is DPLL 1 */
190f68c5 1323 crtc_state->ddi_pll_sel = pll->id + 1;
82d35437
S		 1324
1325 return true;
1326}
0220ab6e 1327
d683f3bc
S		 1328/* bxt clock parameters */
1329struct bxt_clk_div {
1330 uint32_t p1;
1331 uint32_t p2;
1332 uint32_t m2_int;
1333 uint32_t m2_frac;
1334 bool m2_frac_en;
1335 uint32_t n;
1336 uint32_t prop_coef;
1337 uint32_t int_coef;
1338 uint32_t gain_ctl;
1339 uint32_t targ_cnt;
1340 uint32_t lanestagger;
1341};
1342
1343/* pre-calculated values for DP linkrates */
1344static struct bxt_clk_div bxt_dp_clk_val[7] = {
1345 /* 162 */ {4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
1346 /* 270 */ {4, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0xd},
1347 /* 540 */ {2, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0x18},
1348 /* 216 */ {3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
1349 /* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
1350 /* 324 */ {4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
1351 /* 432 */ {3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
1352};
1353
1354static bool
1355bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1356 struct intel_crtc_state *crtc_state,
1357 struct intel_encoder *intel_encoder,
1358 int clock)
1359{
1360 struct intel_shared_dpll *pll;
1361 struct bxt_clk_div clk_div = {0};
1362
1363 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1364 intel_clock_t best_clock;
1365
1366 /* Calculate HDMI div */
1367 /*
1368 * FIXME: tie the following calculation into
1369 * i9xx_crtc_compute_clock
1370 */
1371 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1372 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1373 clock, pipe_name(intel_crtc->pipe));
1374 return false;
1375 }
1376
1377 clk_div.p1 = best_clock.p1;
1378 clk_div.p2 = best_clock.p2;
1379 WARN_ON(best_clock.m1 != 2);
1380 clk_div.n = best_clock.n;
1381 clk_div.m2_int = best_clock.m2 >> 22;
1382 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1383 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1384
1385 /* FIXME: set coef, gain, targcnt based on freq band */
1386 clk_div.prop_coef = 5;
1387 clk_div.int_coef = 11;
1388 clk_div.gain_ctl = 2;
1389 clk_div.targ_cnt = 9;
1390 if (clock > 270000)
1391 clk_div.lanestagger = 0x18;
1392 else if (clock > 135000)
1393 clk_div.lanestagger = 0x0d;
1394 else if (clock > 67000)
1395 clk_div.lanestagger = 0x07;
1396 else if (clock > 33000)
1397 clk_div.lanestagger = 0x04;
1398 else
1399 clk_div.lanestagger = 0x02;
1400 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1401 intel_encoder->type == INTEL_OUTPUT_EDP) {
1402 struct drm_encoder *encoder = &intel_encoder->base;
1403 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1404
1405 switch (intel_dp->link_bw) {
1406 case DP_LINK_BW_1_62:
1407 clk_div = bxt_dp_clk_val[0];
1408 break;
1409 case DP_LINK_BW_2_7:
1410 clk_div = bxt_dp_clk_val[1];
1411 break;
1412 case DP_LINK_BW_5_4:
1413 clk_div = bxt_dp_clk_val[2];
1414 break;
1415 default:
1416 clk_div = bxt_dp_clk_val[0];
1417 DRM_ERROR("Unknown link rate\n");
1418 }
1419 }
1420
1421 crtc_state->dpll_hw_state.ebb0 =
1422 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1423 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1424 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1425 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1426
1427 if (clk_div.m2_frac_en)
1428 crtc_state->dpll_hw_state.pll3 =
1429 PORT_PLL_M2_FRAC_ENABLE;
1430
1431 crtc_state->dpll_hw_state.pll6 =
1432 clk_div.prop_coef | PORT_PLL_INT_COEFF(clk_div.int_coef);
1433 crtc_state->dpll_hw_state.pll6 |=
1434 PORT_PLL_GAIN_CTL(clk_div.gain_ctl);
1435
1436 crtc_state->dpll_hw_state.pll8 = clk_div.targ_cnt;
1437
1438 crtc_state->dpll_hw_state.pcsdw12 =
1439 LANESTAGGER_STRAP_OVRD | clk_div.lanestagger;
1440
1441 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1442 if (pll == NULL) {
1443 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1444 pipe_name(intel_crtc->pipe));
1445 return false;
1446 }
1447
1448 /* shared DPLL id 0 is DPLL A */
1449 crtc_state->ddi_pll_sel = pll->id;
1450
1451 return true;
1452}
1453
0220ab6e
DL		 1454/*
1455 * Tries to find a *shared* PLL for the CRTC and store it in
1456 * intel_crtc->ddi_pll_sel.
1457 *
1458 * For private DPLLs, compute_config() should do the selection for us. This
1459 * function should be folded into compute_config() eventually.
1460 */
190f68c5
ACO		 1461bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1462 struct intel_crtc_state *crtc_state)
0220ab6e 1463{
82d35437 1464 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d 1465 struct intel_encoder *intel_encoder =
3165c074 1466 intel_ddi_get_crtc_new_encoder(crtc_state);
190f68c5 1467 int clock = crtc_state->port_clock;
0220ab6e 1468
82d35437 1469 if (IS_SKYLAKE(dev))
190f68c5
ACO		 1470 return skl_ddi_pll_select(intel_crtc, crtc_state,
1471 intel_encoder, clock);
d683f3bc
S		 1472 else if (IS_BROXTON(dev))
1473 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1474 intel_encoder, clock);
82d35437 1475 else
190f68c5
ACO		 1476 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1477 intel_encoder, clock);
0220ab6e
DL		 1478}
1479
dae84799
PZ		 1480void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1481{
1482 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1483 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1484 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1485 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1486 int type = intel_encoder->type;
1487 uint32_t temp;
1488
0e32b39c 1489 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1490 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1491 switch (intel_crtc->config->pipe_bpp) {
dae84799 1492 case 18:
c9809791 1493 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1494 break;
1495 case 24:
c9809791 1496 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1497 break;
1498 case 30:
c9809791 1499 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1500 break;
1501 case 36:
c9809791 1502 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1503 break;
1504 default:
4e53c2e0 1505 BUG();
dae84799 1506 }
c9809791 1507 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1508 }
1509}
1510
0e32b39c
DA		 1511void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1512{
1513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1514 struct drm_device *dev = crtc->dev;
1515 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1516 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1517 uint32_t temp;
1518 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1519 if (state == true)
1520 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1521 else
1522 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1523 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1524}
1525
8228c251 1526void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1527{
1528 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1529 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1530 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1531 struct drm_device *dev = crtc->dev;
1532 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1533 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1534 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1535 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1536 int type = intel_encoder->type;
8d9ddbcb
PZ		 1537 uint32_t temp;
1538
ad80a810
PZ		 1539 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1540 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1541 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1542
6e3c9717 1543 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1544 case 18:
ad80a810 1545 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1546 break;
1547 case 24:
ad80a810 1548 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1549 break;
1550 case 30:
ad80a810 1551 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1552 break;
1553 case 36:
ad80a810 1554 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1555 break;
1556 default:
4e53c2e0 1557 BUG();
dfcef252 1558 }
72662e10 1559
6e3c9717 1560 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1561 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1562 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1563 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1564
e6f0bfc4
PZ		 1565 if (cpu_transcoder == TRANSCODER_EDP) {
1566 switch (pipe) {
1567 case PIPE_A:
c7670b10
PZ		 1568 /* On Haswell, can only use the always-on power well for
1569 * eDP when not using the panel fitter, and when not
1570 * using motion blur mitigation (which we don't
1571 * support). */
fabf6e51 1572 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1573 (intel_crtc->config->pch_pfit.enabled ||
1574 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1575 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1576 else
1577 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1578 break;
1579 case PIPE_B:
1580 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1581 break;
1582 case PIPE_C:
1583 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1584 break;
1585 default:
1586 BUG();
1587 break;
1588 }
1589 }
1590
7739c33b 1591 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1592 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1593 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1594 else
ad80a810 1595 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1596
7739c33b 1597 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1598 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1599 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b
PZ		 1600
1601 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1602 type == INTEL_OUTPUT_EDP) {
1603 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1604
0e32b39c
DA		 1605 if (intel_dp->is_mst) {
1606 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1607 } else
1608 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1609
1610 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1611 } else if (type == INTEL_OUTPUT_DP_MST) {
1612 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1613
1614 if (intel_dp->is_mst) {
1615 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1616 } else
1617 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1618
17aa6be9 1619 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
8d9ddbcb 1620 } else {
84f44ce7
VS		 1621 WARN(1, "Invalid encoder type %d for pipe %c\n",
1622 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1623 }
1624
ad80a810 1625 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1626}
72662e10 1627
ad80a810
PZ		 1628void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1629 enum transcoder cpu_transcoder)
8d9ddbcb 1630{
ad80a810 1631 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1632 uint32_t val = I915_READ(reg);
1633
0e32b39c 1634 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1635 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1636 I915_WRITE(reg, val);
72662e10
ED		 1637}
1638
bcbc889b
PZ		 1639bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1640{
1641 struct drm_device *dev = intel_connector->base.dev;
1642 struct drm_i915_private *dev_priv = dev->dev_private;
1643 struct intel_encoder *intel_encoder = intel_connector->encoder;
1644 int type = intel_connector->base.connector_type;
1645 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1646 enum pipe pipe = 0;
1647 enum transcoder cpu_transcoder;
882244a3 1648 enum intel_display_power_domain power_domain;
bcbc889b
PZ		 1649 uint32_t tmp;
1650
882244a3 1651 power_domain = intel_display_port_power_domain(intel_encoder);
f458ebbc 1652 if (!intel_display_power_is_enabled(dev_priv, power_domain))
882244a3
PZ		 1653 return false;
1654
bcbc889b
PZ		 1655 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1656 return false;
1657
1658 if (port == PORT_A)
1659 cpu_transcoder = TRANSCODER_EDP;
1660 else
1a240d4d 1661 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1662
1663 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1664
1665 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1666 case TRANS_DDI_MODE_SELECT_HDMI:
1667 case TRANS_DDI_MODE_SELECT_DVI:
1668 return (type == DRM_MODE_CONNECTOR_HDMIA);
1669
1670 case TRANS_DDI_MODE_SELECT_DP_SST:
1671 if (type == DRM_MODE_CONNECTOR_eDP)
1672 return true;
bcbc889b 1673 return (type == DRM_MODE_CONNECTOR_DisplayPort);
0e32b39c
DA		 1674 case TRANS_DDI_MODE_SELECT_DP_MST:
1675 /* if the transcoder is in MST state then
1676 * connector isn't connected */
1677 return false;
bcbc889b
PZ		 1678
1679 case TRANS_DDI_MODE_SELECT_FDI:
1680 return (type == DRM_MODE_CONNECTOR_VGA);
1681
1682 default:
1683 return false;
1684 }
1685}
1686
85234cdc
DV		 1687bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1688 enum pipe *pipe)
1689{
1690 struct drm_device *dev = encoder->base.dev;
1691 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1692 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 1693 enum intel_display_power_domain power_domain;
85234cdc
DV		 1694 u32 tmp;
1695 int i;
1696
6d129bea 1697 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1698 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1699 return false;
1700
fe43d3f5 1701 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1702
1703 if (!(tmp & DDI_BUF_CTL_ENABLE))
1704 return false;
1705
ad80a810
PZ		 1706 if (port == PORT_A) {
1707 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1708
ad80a810
PZ		 1709 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1710 case TRANS_DDI_EDP_INPUT_A_ON:
1711 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1712 *pipe = PIPE_A;
1713 break;
1714 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1715 *pipe = PIPE_B;
1716 break;
1717 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1718 *pipe = PIPE_C;
1719 break;
1720 }
1721
1722 return true;
1723 } else {
1724 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1725 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1726
1727 if ((tmp & TRANS_DDI_PORT_MASK)
1728 == TRANS_DDI_SELECT_PORT(port)) {
0e32b39c
DA		 1729 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1730 return false;
1731
ad80a810
PZ		 1732 *pipe = i;
1733 return true;
1734 }
85234cdc
DV		 1735 }
1736 }
1737
84f44ce7 1738 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 1739
22f9fe50 1740 return false;
85234cdc
DV		 1741}
1742
fc914639
PZ		 1743void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1744{
1745 struct drm_crtc *crtc = &intel_crtc->base;
1746 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1747 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1748 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 1749 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1750
bb523fc0
PZ		 1751 if (cpu_transcoder != TRANSCODER_EDP)
1752 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1753 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1754}
1755
1756void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1757{
1758 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6e3c9717 1759 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1760
bb523fc0
PZ		 1761 if (cpu_transcoder != TRANSCODER_EDP)
1762 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1763 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1764}
1765
96fb9f9b
VK		 1766void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
1767 enum port port, int type)
1768{
1769 struct drm_i915_private *dev_priv = dev->dev_private;
1770 const struct bxt_ddi_buf_trans *ddi_translations;
1771 u32 n_entries, i;
1772 uint32_t val;
1773
1774 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1775 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1776 ddi_translations = bxt_ddi_translations_dp;
1777 } else if (type == INTEL_OUTPUT_HDMI) {
1778 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1779 ddi_translations = bxt_ddi_translations_hdmi;
1780 } else {
1781 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1782 type);
1783 return;
1784 }
1785
1786 /* Check if default value has to be used */
1787 if (level >= n_entries ||
1788 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1789 for (i = 0; i < n_entries; i++) {
1790 if (ddi_translations[i].default_index) {
1791 level = i;
1792 break;
1793 }
1794 }
1795 }
1796
1797 /*
1798 * While we write to the group register to program all lanes at once we
1799 * can read only lane registers and we pick lanes 0/1 for that.
1800 */
1801 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1802 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
1803 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1804
1805 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
1806 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
1807 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
1808 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
1809 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
1810
1811 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
1812 val &= ~UNIQE_TRANGE_EN_METHOD;
1813 if (ddi_translations[level].enable)
1814 val |= UNIQE_TRANGE_EN_METHOD;
1815 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
1816
1817 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
1818 val &= ~DE_EMPHASIS;
1819 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
1820 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
1821
1822 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1823 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
1824 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1825}
1826
00c09d70 1827static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 1828{
c19b0669 1829 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 1830 struct drm_device *dev = encoder->dev;
1831 struct drm_i915_private *dev_priv = dev->dev_private;
30cf6db8 1832 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6441ab5f 1833 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1834 int type = intel_encoder->type;
96fb9f9b 1835 int hdmi_level;
6441ab5f 1836
82a4d9c0
PZ		 1837 if (type == INTEL_OUTPUT_EDP) {
1838 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4be73780 1839 intel_edp_panel_on(intel_dp);
82a4d9c0 1840 }
6441ab5f 1841
efa80add 1842 if (IS_SKYLAKE(dev)) {
6e3c9717 1843 uint32_t dpll = crtc->config->ddi_pll_sel;
efa80add
S		 1844 uint32_t val;
1845
5416d871
DL		 1846 /*
1847 * DPLL0 is used for eDP and is the only "private" DPLL (as
1848 * opposed to shared) on SKL
1849 */
1850 if (type == INTEL_OUTPUT_EDP) {
1851 WARN_ON(dpll != SKL_DPLL0);
1852
1853 val = I915_READ(DPLL_CTRL1);
1854
1855 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
1856 DPLL_CTRL1_SSC(dpll) |
71cd8423 1857 DPLL_CTRL1_LINK_RATE_MASK(dpll));
6e3c9717 1858 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
5416d871
DL		 1859
1860 I915_WRITE(DPLL_CTRL1, val);
1861 POSTING_READ(DPLL_CTRL1);
1862 }
1863
1864 /* DDI -> PLL mapping */
efa80add
S		 1865 val = I915_READ(DPLL_CTRL2);
1866
1867 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1868 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1869 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1870 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1871
1872 I915_WRITE(DPLL_CTRL2, val);
5416d871 1873
1ab23380 1874 } else if (INTEL_INFO(dev)->gen < 9) {
6e3c9717
ACO		 1875 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
1876 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
efa80add 1877 }
c19b0669 1878
82a4d9c0 1879 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 1880 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 1881
44905a27 1882 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 1883
1884 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1885 intel_dp_start_link_train(intel_dp);
1886 intel_dp_complete_link_train(intel_dp);
23f08d83 1887 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
3ab9c637 1888 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 1889 } else if (type == INTEL_OUTPUT_HDMI) {
1890 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1891
96fb9f9b
VK		 1892 if (IS_BROXTON(dev)) {
1893 hdmi_level = dev_priv->vbt.
1894 ddi_port_info[port].hdmi_level_shift;
1895 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
1896 INTEL_OUTPUT_HDMI);
1897 }
30cf6db8 1898 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 1899 crtc->config->has_hdmi_sink,
1900 &crtc->config->base.adjusted_mode);
c19b0669 1901 }
6441ab5f
PZ		 1902}
1903
00c09d70 1904static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 1905{
1906 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 1907 struct drm_device *dev = encoder->dev;
1908 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 1909 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1910 int type = intel_encoder->type;
2886e93f 1911 uint32_t val;
a836bdf9 1912 bool wait = false;
2886e93f
PZ		 1913
1914 val = I915_READ(DDI_BUF_CTL(port));
1915 if (val & DDI_BUF_CTL_ENABLE) {
1916 val &= ~DDI_BUF_CTL_ENABLE;
1917 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 1918 wait = true;
2886e93f 1919 }
6441ab5f 1920
a836bdf9
PZ		 1921 val = I915_READ(DP_TP_CTL(port));
1922 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1923 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1924 I915_WRITE(DP_TP_CTL(port), val);
1925
1926 if (wait)
1927 intel_wait_ddi_buf_idle(dev_priv, port);
1928
76bb80ed 1929 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 1930 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 1931 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 1932 intel_edp_panel_vdd_on(intel_dp);
4be73780 1933 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 1934 }
1935
efa80add
S		 1936 if (IS_SKYLAKE(dev))
1937 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1938 DPLL_CTRL2_DDI_CLK_OFF(port)));
1ab23380 1939 else if (INTEL_INFO(dev)->gen < 9)
efa80add 1940 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 1941}
1942
00c09d70 1943static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 1944{
6547fef8 1945 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1946 struct drm_crtc *crtc = encoder->crtc;
1947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 1948 struct drm_device *dev = encoder->dev;
72662e10 1949 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 1950 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1951 int type = intel_encoder->type;
72662e10 1952
6547fef8 1953 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 1954 struct intel_digital_port *intel_dig_port =
1955 enc_to_dig_port(encoder);
1956
6547fef8
PZ		 1957 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1958 * are ignored so nothing special needs to be done besides
1959 * enabling the port.
1960 */
876a8cdf 1961 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 1962 intel_dig_port->saved_port_bits |
1963 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 1964 } else if (type == INTEL_OUTPUT_EDP) {
1965 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1966
23f08d83 1967 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 1968 intel_dp_stop_link_train(intel_dp);
1969
4be73780 1970 intel_edp_backlight_on(intel_dp);
0bc12bcb 1971 intel_psr_enable(intel_dp);
c395578e 1972 intel_edp_drrs_enable(intel_dp);
6547fef8 1973 }
7b9f35a6 1974
6e3c9717 1975 if (intel_crtc->config->has_audio) {
d45a0bf5 1976 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 1977 intel_audio_codec_enable(intel_encoder);
7b9f35a6 1978 }
5ab432ef
DV		 1979}
1980
00c09d70 1981static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 1982{
d6c50ff8 1983 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1984 struct drm_crtc *crtc = encoder->crtc;
1985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 1986 int type = intel_encoder->type;
7b9f35a6
WX		 1987 struct drm_device *dev = encoder->dev;
1988 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 1989
6e3c9717 1990 if (intel_crtc->config->has_audio) {
69bfe1a9 1991 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 1992 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1993 }
2831d842 1994
d6c50ff8
PZ		 1995 if (type == INTEL_OUTPUT_EDP) {
1996 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1997
c395578e 1998 intel_edp_drrs_disable(intel_dp);
0bc12bcb 1999 intel_psr_disable(intel_dp);
4be73780 2000 intel_edp_backlight_off(intel_dp);
d6c50ff8 2001 }
72662e10 2002}
79f689aa 2003
e0b01be4
DV		 2004static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
2005 struct intel_shared_dpll *pll)
2006{
3e369b76 2007 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
e0b01be4
DV		 2008 POSTING_READ(WRPLL_CTL(pll->id));
2009 udelay(20);
2010}
2011
12030431
DV		 2012static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
2013 struct intel_shared_dpll *pll)
2014{
2015 uint32_t val;
2016
2017 val = I915_READ(WRPLL_CTL(pll->id));
12030431
DV		 2018 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2019 POSTING_READ(WRPLL_CTL(pll->id));
2020}
2021
d452c5b6
DV		 2022static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2023 struct intel_shared_dpll *pll,
2024 struct intel_dpll_hw_state *hw_state)
2025{
2026 uint32_t val;
2027
f458ebbc 2028 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
d452c5b6
DV		 2029 return false;
2030
2031 val = I915_READ(WRPLL_CTL(pll->id));
2032 hw_state->wrpll = val;
2033
2034 return val & WRPLL_PLL_ENABLE;
2035}
2036
ca1381b5 2037static const char * const hsw_ddi_pll_names[] = {
9cd86933
DV		 2038 "WRPLL 1",
2039 "WRPLL 2",
2040};
2041
143b307c 2042static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
79f689aa 2043{
9cd86933
DV		 2044 int i;
2045
716c2e55 2046 dev_priv->num_shared_dpll = 2;
9cd86933 2047
716c2e55 2048 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9cd86933
DV		 2049 dev_priv->shared_dplls[i].id = i;
2050 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
12030431 2051 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
e0b01be4 2052 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
d452c5b6
DV		 2053 dev_priv->shared_dplls[i].get_hw_state =
2054 hsw_ddi_pll_get_hw_state;
9cd86933 2055 }
143b307c
DL		 2056}
2057
d1a2dc78
S		 2058static const char * const skl_ddi_pll_names[] = {
2059 "DPLL 1",
2060 "DPLL 2",
2061 "DPLL 3",
2062};
2063
2064struct skl_dpll_regs {
2065 u32 ctl, cfgcr1, cfgcr2;
2066};
2067
2068/* this array is indexed by the *shared* pll id */
2069static const struct skl_dpll_regs skl_dpll_regs[3] = {
2070 {
2071 /* DPLL 1 */
2072 .ctl = LCPLL2_CTL,
2073 .cfgcr1 = DPLL1_CFGCR1,
2074 .cfgcr2 = DPLL1_CFGCR2,
2075 },
2076 {
2077 /* DPLL 2 */
2078 .ctl = WRPLL_CTL1,
2079 .cfgcr1 = DPLL2_CFGCR1,
2080 .cfgcr2 = DPLL2_CFGCR2,
2081 },
2082 {
2083 /* DPLL 3 */
2084 .ctl = WRPLL_CTL2,
2085 .cfgcr1 = DPLL3_CFGCR1,
2086 .cfgcr2 = DPLL3_CFGCR2,
2087 },
2088};
2089
2090static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2091 struct intel_shared_dpll *pll)
2092{
2093 uint32_t val;
2094 unsigned int dpll;
2095 const struct skl_dpll_regs *regs = skl_dpll_regs;
2096
2097 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2098 dpll = pll->id + 1;
2099
2100 val = I915_READ(DPLL_CTRL1);
2101
2102 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
71cd8423 2103 DPLL_CTRL1_LINK_RATE_MASK(dpll));
d1a2dc78
S		 2104 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2105
2106 I915_WRITE(DPLL_CTRL1, val);
2107 POSTING_READ(DPLL_CTRL1);
2108
2109 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2110 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2111 POSTING_READ(regs[pll->id].cfgcr1);
2112 POSTING_READ(regs[pll->id].cfgcr2);
2113
2114 /* the enable bit is always bit 31 */
2115 I915_WRITE(regs[pll->id].ctl,
2116 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2117
2118 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2119 DRM_ERROR("DPLL %d not locked\n", dpll);
2120}
2121
2122static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2123 struct intel_shared_dpll *pll)
2124{
2125 const struct skl_dpll_regs *regs = skl_dpll_regs;
2126
2127 /* the enable bit is always bit 31 */
2128 I915_WRITE(regs[pll->id].ctl,
2129 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2130 POSTING_READ(regs[pll->id].ctl);
2131}
2132
2133static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2134 struct intel_shared_dpll *pll,
2135 struct intel_dpll_hw_state *hw_state)
2136{
2137 uint32_t val;
2138 unsigned int dpll;
2139 const struct skl_dpll_regs *regs = skl_dpll_regs;
2140
2141 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2142 return false;
2143
2144 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2145 dpll = pll->id + 1;
2146
2147 val = I915_READ(regs[pll->id].ctl);
2148 if (!(val & LCPLL_PLL_ENABLE))
2149 return false;
2150
2151 val = I915_READ(DPLL_CTRL1);
2152 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2153
2154 /* avoid reading back stale values if HDMI mode is not enabled */
2155 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2156 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2157 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2158 }
2159
2160 return true;
2161}
2162
2163static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2164{
2165 int i;
2166
2167 dev_priv->num_shared_dpll = 3;
2168
2169 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2170 dev_priv->shared_dplls[i].id = i;
2171 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2172 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2173 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2174 dev_priv->shared_dplls[i].get_hw_state =
2175 skl_ddi_pll_get_hw_state;
2176 }
2177}
2178
5c6706e5
VK		 2179static void broxton_phy_init(struct drm_i915_private *dev_priv,
2180 enum dpio_phy phy)
2181{
2182 enum port port;
2183 uint32_t val;
2184
2185 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2186 val |= GT_DISPLAY_POWER_ON(phy);
2187 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2188
2189 /* Considering 10ms timeout until BSpec is updated */
2190 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2191 DRM_ERROR("timeout during PHY%d power on\n", phy);
2192
2193 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2194 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2195 int lane;
2196
2197 for (lane = 0; lane < 4; lane++) {
2198 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2199 /*
2200 * Note that on CHV this flag is called UPAR, but has
2201 * the same function.
2202 */
2203 val &= ~LATENCY_OPTIM;
2204 if (lane != 1)
2205 val |= LATENCY_OPTIM;
2206
2207 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2208 }
2209 }
2210
2211 /* Program PLL Rcomp code offset */
2212 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2213 val &= ~IREF0RC_OFFSET_MASK;
2214 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2215 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2216
2217 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2218 val &= ~IREF1RC_OFFSET_MASK;
2219 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2220 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2221
2222 /* Program power gating */
2223 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2224 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2225 SUS_CLK_CONFIG;
2226 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2227
2228 if (phy == DPIO_PHY0) {
2229 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2230 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2231 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2232 }
2233
2234 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2235 val &= ~OCL2_LDOFUSE_PWR_DIS;
2236 /*
2237 * On PHY1 disable power on the second channel, since no port is
2238 * connected there. On PHY0 both channels have a port, so leave it
2239 * enabled.
2240 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2241 * power down the second channel on PHY0 as well.
2242 */
2243 if (phy == DPIO_PHY1)
2244 val |= OCL2_LDOFUSE_PWR_DIS;
2245 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2246
2247 if (phy == DPIO_PHY0) {
2248 uint32_t grc_code;
2249 /*
2250 * PHY0 isn't connected to an RCOMP resistor so copy over
2251 * the corresponding calibrated value from PHY1, and disable
2252 * the automatic calibration on PHY0.
2253 */
2254 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2255 10))
2256 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2257
2258 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2259 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2260 grc_code = val << GRC_CODE_FAST_SHIFT |
2261 val << GRC_CODE_SLOW_SHIFT |
2262 val;
2263 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2264
2265 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2266 val |= GRC_DIS | GRC_RDY_OVRD;
2267 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2268 }
2269
2270 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2271 val |= COMMON_RESET_DIS;
2272 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2273}
2274
2275void broxton_ddi_phy_init(struct drm_device *dev)
2276{
2277 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2278 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2279 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2280}
2281
2282static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2283 enum dpio_phy phy)
2284{
2285 uint32_t val;
2286
2287 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2288 val &= ~COMMON_RESET_DIS;
2289 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2290}
2291
2292void broxton_ddi_phy_uninit(struct drm_device *dev)
2293{
2294 struct drm_i915_private *dev_priv = dev->dev_private;
2295
2296 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2297 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2298
2299 /* FIXME: do this in broxton_phy_uninit per phy */
2300 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2301}
2302
dfb82408
S		 2303static const char * const bxt_ddi_pll_names[] = {
2304 "PORT PLL A",
2305 "PORT PLL B",
2306 "PORT PLL C",
2307};
2308
2309static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2310 struct intel_shared_dpll *pll)
2311{
2312 uint32_t temp;
2313 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2314
2315 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2316 temp &= ~PORT_PLL_REF_SEL;
2317 /* Non-SSC reference */
2318 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2319
2320 /* Disable 10 bit clock */
2321 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2322 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2323 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2324
2325 /* Write P1 & P2 */
2326 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2327 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2328 temp |= pll->config.hw_state.ebb0;
2329 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2330
2331 /* Write M2 integer */
2332 temp = I915_READ(BXT_PORT_PLL(port, 0));
2333 temp &= ~PORT_PLL_M2_MASK;
2334 temp |= pll->config.hw_state.pll0;
2335 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2336
2337 /* Write N */
2338 temp = I915_READ(BXT_PORT_PLL(port, 1));
2339 temp &= ~PORT_PLL_N_MASK;
2340 temp |= pll->config.hw_state.pll1;
2341 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2342
2343 /* Write M2 fraction */
2344 temp = I915_READ(BXT_PORT_PLL(port, 2));
2345 temp &= ~PORT_PLL_M2_FRAC_MASK;
2346 temp |= pll->config.hw_state.pll2;
2347 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2348
2349 /* Write M2 fraction enable */
2350 temp = I915_READ(BXT_PORT_PLL(port, 3));
2351 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2352 temp |= pll->config.hw_state.pll3;
2353 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2354
2355 /* Write coeff */
2356 temp = I915_READ(BXT_PORT_PLL(port, 6));
2357 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2358 temp &= ~PORT_PLL_INT_COEFF_MASK;
2359 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2360 temp |= pll->config.hw_state.pll6;
2361 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2362
2363 /* Write calibration val */
2364 temp = I915_READ(BXT_PORT_PLL(port, 8));
2365 temp &= ~PORT_PLL_TARGET_CNT_MASK;
2366 temp |= pll->config.hw_state.pll8;
2367 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2368
2369 /*
2370 * FIXME: program PORT_PLL_9/i_lockthresh according to the latest
2371 * specification update.
2372 */
2373
2374 /* Recalibrate with new settings */
2375 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2376 temp |= PORT_PLL_RECALIBRATE;
2377 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2378 /* Enable 10 bit clock */
2379 temp |= PORT_PLL_10BIT_CLK_ENABLE;
2380 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2381
2382 /* Enable PLL */
2383 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2384 temp |= PORT_PLL_ENABLE;
2385 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2386 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2387
2388 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2389 PORT_PLL_LOCK), 200))
2390 DRM_ERROR("PLL %d not locked\n", port);
2391
2392 /*
2393 * While we write to the group register to program all lanes at once we
2394 * can read only lane registers and we pick lanes 0/1 for that.
2395 */
2396 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2397 temp &= ~LANE_STAGGER_MASK;
2398 temp &= ~LANESTAGGER_STRAP_OVRD;
2399 temp |= pll->config.hw_state.pcsdw12;
2400 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2401}
2402
2403static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2404 struct intel_shared_dpll *pll)
2405{
2406 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2407 uint32_t temp;
2408
2409 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2410 temp &= ~PORT_PLL_ENABLE;
2411 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2412 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2413}
2414
2415static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2416 struct intel_shared_dpll *pll,
2417 struct intel_dpll_hw_state *hw_state)
2418{
2419 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2420 uint32_t val;
2421
2422 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2423 return false;
2424
2425 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2426 if (!(val & PORT_PLL_ENABLE))
2427 return false;
2428
2429 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
2430 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
2431 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
2432 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
2433 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
2434 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
2435 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
2436 /*
2437 * While we write to the group register to program all lanes at once we
2438 * can read only lane registers. We configure all lanes the same way, so
2439 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2440 */
2441 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2442 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port) != hw_state->pcsdw12))
2443 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2444 hw_state->pcsdw12,
2445 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
2446
2447 return true;
2448}
2449
2450static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2451{
2452 int i;
2453
2454 dev_priv->num_shared_dpll = 3;
2455
2456 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2457 dev_priv->shared_dplls[i].id = i;
2458 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2459 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2460 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2461 dev_priv->shared_dplls[i].get_hw_state =
2462 bxt_ddi_pll_get_hw_state;
2463 }
2464}
2465
143b307c
DL		 2466void intel_ddi_pll_init(struct drm_device *dev)
2467{
2468 struct drm_i915_private *dev_priv = dev->dev_private;
2469 uint32_t val = I915_READ(LCPLL_CTL);
2470
d1a2dc78
S		 2471 if (IS_SKYLAKE(dev))
2472 skl_shared_dplls_init(dev_priv);
dfb82408
S		 2473 else if (IS_BROXTON(dev))
2474 bxt_shared_dplls_init(dev_priv);
d1a2dc78
S		 2475 else
2476 hsw_shared_dplls_init(dev_priv);
79f689aa 2477
b2b877ff 2478 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1652d19e 2479 dev_priv->display.get_display_clock_speed(dev));
79f689aa 2480
121643c2
S		 2481 if (IS_SKYLAKE(dev)) {
2482 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
2483 DRM_ERROR("LCPLL1 is disabled\n");
f8437dd1
VK		 2484 } else if (IS_BROXTON(dev)) {
2485 broxton_init_cdclk(dev);
5c6706e5 2486 broxton_ddi_phy_init(dev);
121643c2
S		 2487 } else {
2488 /*
2489 * The LCPLL register should be turned on by the BIOS. For now
2490 * let's just check its state and print errors in case
2491 * something is wrong. Don't even try to turn it on.
2492 */
2493
2494 if (val & LCPLL_CD_SOURCE_FCLK)
2495 DRM_ERROR("CDCLK source is not LCPLL\n");
79f689aa 2496
121643c2
S		 2497 if (val & LCPLL_PLL_DISABLE)
2498 DRM_ERROR("LCPLL is disabled\n");
2499 }
79f689aa 2500}
c19b0669
PZ		 2501
2502void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
2503{
174edf1f
PZ		 2504 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2505 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 2506 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 2507 enum port port = intel_dig_port->port;
c19b0669 2508 uint32_t val;
f3e227df 2509 bool wait = false;
c19b0669
PZ		 2510
2511 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2512 val = I915_READ(DDI_BUF_CTL(port));
2513 if (val & DDI_BUF_CTL_ENABLE) {
2514 val &= ~DDI_BUF_CTL_ENABLE;
2515 I915_WRITE(DDI_BUF_CTL(port), val);
2516 wait = true;
2517 }
2518
2519 val = I915_READ(DP_TP_CTL(port));
2520 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2521 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2522 I915_WRITE(DP_TP_CTL(port), val);
2523 POSTING_READ(DP_TP_CTL(port));
2524
2525 if (wait)
2526 intel_wait_ddi_buf_idle(dev_priv, port);
2527 }
2528
0e32b39c 2529 val = DP_TP_CTL_ENABLE |
c19b0669 2530 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 2531 if (intel_dp->is_mst)
2532 val |= DP_TP_CTL_MODE_MST;
2533 else {
2534 val |= DP_TP_CTL_MODE_SST;
2535 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2536 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2537 }
c19b0669
PZ		 2538 I915_WRITE(DP_TP_CTL(port), val);
2539 POSTING_READ(DP_TP_CTL(port));
2540
2541 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2542 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2543 POSTING_READ(DDI_BUF_CTL(port));
2544
2545 udelay(600);
2546}
00c09d70 2547
1ad960f2
PZ		 2548void intel_ddi_fdi_disable(struct drm_crtc *crtc)
2549{
2550 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2551 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2552 uint32_t val;
2553
2554 intel_ddi_post_disable(intel_encoder);
2555
2556 val = I915_READ(_FDI_RXA_CTL);
2557 val &= ~FDI_RX_ENABLE;
2558 I915_WRITE(_FDI_RXA_CTL, val);
2559
2560 val = I915_READ(_FDI_RXA_MISC);
2561 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2562 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2563 I915_WRITE(_FDI_RXA_MISC, val);
2564
2565 val = I915_READ(_FDI_RXA_CTL);
2566 val &= ~FDI_PCDCLK;
2567 I915_WRITE(_FDI_RXA_CTL, val);
2568
2569 val = I915_READ(_FDI_RXA_CTL);
2570 val &= ~FDI_RX_PLL_ENABLE;
2571 I915_WRITE(_FDI_RXA_CTL, val);
2572}
2573
00c09d70
PZ		 2574static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
2575{
0e32b39c
DA		 2576 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base);
2577 int type = intel_dig_port->base.type;
2578
2579 if (type != INTEL_OUTPUT_DISPLAYPORT &&
2580 type != INTEL_OUTPUT_EDP &&
2581 type != INTEL_OUTPUT_UNKNOWN) {
2582 return;
2583 }
00c09d70 2584
0e32b39c 2585 intel_dp_hot_plug(intel_encoder);
00c09d70
PZ		 2586}
2587
6801c18c 2588void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 2589 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2590{
2591 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
2592 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 2593 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 2594 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 2595 u32 temp, flags = 0;
2596
2597 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2598 if (temp & TRANS_DDI_PHSYNC)
2599 flags |= DRM_MODE_FLAG_PHSYNC;
2600 else
2601 flags |= DRM_MODE_FLAG_NHSYNC;
2602 if (temp & TRANS_DDI_PVSYNC)
2603 flags |= DRM_MODE_FLAG_PVSYNC;
2604 else
2605 flags |= DRM_MODE_FLAG_NVSYNC;
2606
2d112de7 2607 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 2608
2609 switch (temp & TRANS_DDI_BPC_MASK) {
2610 case TRANS_DDI_BPC_6:
2611 pipe_config->pipe_bpp = 18;
2612 break;
2613 case TRANS_DDI_BPC_8:
2614 pipe_config->pipe_bpp = 24;
2615 break;
2616 case TRANS_DDI_BPC_10:
2617 pipe_config->pipe_bpp = 30;
2618 break;
2619 case TRANS_DDI_BPC_12:
2620 pipe_config->pipe_bpp = 36;
2621 break;
2622 default:
2623 break;
2624 }
eb14cb74
VS		 2625
2626 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2627 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 2628 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 2629 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2630
2631 if (intel_hdmi->infoframe_enabled(&encoder->base))
2632 pipe_config->has_infoframe = true;
cbc572a9 2633 break;
eb14cb74
VS		 2634 case TRANS_DDI_MODE_SELECT_DVI:
2635 case TRANS_DDI_MODE_SELECT_FDI:
2636 break;
2637 case TRANS_DDI_MODE_SELECT_DP_SST:
2638 case TRANS_DDI_MODE_SELECT_DP_MST:
2639 pipe_config->has_dp_encoder = true;
2640 intel_dp_get_m_n(intel_crtc, pipe_config);
2641 break;
2642 default:
2643 break;
2644 }
10214420 2645
f458ebbc 2646 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
a60551b1 2647 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6 2648 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
a60551b1
PZ		 2649 pipe_config->has_audio = true;
2650 }
9ed109a7 2651
10214420
DV		 2652 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
2653 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2654 /*
2655 * This is a big fat ugly hack.
2656 *
2657 * Some machines in UEFI boot mode provide us a VBT that has 18
2658 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2659 * unknown we fail to light up. Yet the same BIOS boots up with
2660 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2661 * max, not what it tells us to use.
2662 *
2663 * Note: This will still be broken if the eDP panel is not lit
2664 * up by the BIOS, and thus we can't get the mode at module
2665 * load.
2666 */
2667 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2668 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2669 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2670 }
11578553 2671
22606a18 2672 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 2673}
2674
00c09d70
PZ		 2675static void intel_ddi_destroy(struct drm_encoder *encoder)
2676{
2677 /* HDMI has nothing special to destroy, so we can go with this. */
2678 intel_dp_encoder_destroy(encoder);
2679}
2680
5bfe2ac0 2681static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 2682 struct intel_crtc_state *pipe_config)
00c09d70 2683{
5bfe2ac0 2684 int type = encoder->type;
eccb140b 2685 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 2686
5bfe2ac0 2687 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 2688
eccb140b
DV		 2689 if (port == PORT_A)
2690 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2691
00c09d70 2692 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 2693 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 2694 else
5bfe2ac0 2695 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 2696}
2697
2698static const struct drm_encoder_funcs intel_ddi_funcs = {
2699 .destroy = intel_ddi_destroy,
2700};
2701
4a28ae58
PZ		 2702static struct intel_connector *
2703intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2704{
2705 struct intel_connector *connector;
2706 enum port port = intel_dig_port->port;
2707
9bdbd0b9 2708 connector = intel_connector_alloc();
4a28ae58
PZ		 2709 if (!connector)
2710 return NULL;
2711
2712 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2713 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2714 kfree(connector);
2715 return NULL;
2716 }
2717
2718 return connector;
2719}
2720
2721static struct intel_connector *
2722intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2723{
2724 struct intel_connector *connector;
2725 enum port port = intel_dig_port->port;
2726
9bdbd0b9 2727 connector = intel_connector_alloc();
4a28ae58
PZ		 2728 if (!connector)
2729 return NULL;
2730
2731 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2732 intel_hdmi_init_connector(intel_dig_port, connector);
2733
2734 return connector;
2735}
2736
00c09d70
PZ		 2737void intel_ddi_init(struct drm_device *dev, enum port port)
2738{
876a8cdf 2739 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 2740 struct intel_digital_port *intel_dig_port;
2741 struct intel_encoder *intel_encoder;
2742 struct drm_encoder *encoder;
311a2094
PZ		 2743 bool init_hdmi, init_dp;
2744
2745 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2746 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2747 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2748 if (!init_dp && !init_hdmi) {
f68d697e 2749 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
311a2094
PZ		 2750 port_name(port));
2751 init_hdmi = true;
2752 init_dp = true;
2753 }
00c09d70 2754
b14c5679 2755 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 2756 if (!intel_dig_port)
2757 return;
2758
00c09d70
PZ		 2759 intel_encoder = &intel_dig_port->base;
2760 encoder = &intel_encoder->base;
2761
2762 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
2763 DRM_MODE_ENCODER_TMDS);
00c09d70 2764
5bfe2ac0 2765 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 2766 intel_encoder->enable = intel_enable_ddi;
2767 intel_encoder->pre_enable = intel_ddi_pre_enable;
2768 intel_encoder->disable = intel_disable_ddi;
2769 intel_encoder->post_disable = intel_ddi_post_disable;
2770 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 2771 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 2772
2773 intel_dig_port->port = port;
bcf53de4
SM		 2774 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2775 (DDI_BUF_PORT_REVERSAL |
2776 DDI_A_4_LANES);
00c09d70
PZ		 2777
2778 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 2779 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 2780 intel_encoder->cloneable = 0;
00c09d70
PZ		 2781 intel_encoder->hot_plug = intel_ddi_hot_plug;
2782
f68d697e
CW		 2783 if (init_dp) {
2784 if (!intel_ddi_init_dp_connector(intel_dig_port))
2785 goto err;
13cf5504 2786
f68d697e
CW		 2787 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2788 dev_priv->hpd_irq_port[port] = intel_dig_port;
2789 }
21a8e6a4 2790
311a2094
PZ		 2791 /* In theory we don't need the encoder->type check, but leave it just in
2792 * case we have some really bad VBTs... */
f68d697e
CW		 2793 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2794 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2795 goto err;
21a8e6a4 2796 }
f68d697e
CW		 2797
2798 return;
2799
2800err:
2801 drm_encoder_cleanup(encoder);
2802 kfree(intel_dig_port);
00c09d70 2803}
Linux kernel - Deliverables
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