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drm/i915: remove duplicate register defines
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 114static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 116
0e32b39c 117int
ea5b213a 118intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 119{
7183dc29 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
d4eead50 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
d4eead50 134 break;
a4fc5ed6 135 default:
d4eead50
ID		 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
a4fc5ed6
KP		 138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
eeb6324d
PZ		 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c19de8eb 189static enum drm_mode_status
a4fc5ed6
KP		 190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
df0e9248 193 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 198
dd06f90e
JN		 199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 201 return MODE_PANEL;
202
dd06f90e 203 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 204 return MODE_PANEL;
03afc4a2
DV		 205
206 target_clock = fixed_mode->clock;
7de56f43
ZY		 207 }
208
36008365 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 210 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
c4867936 216 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
0af78a2b
DV		 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
a4fc5ed6
KP		 224 return MODE_OK;
225}
226
227static uint32_t
228pack_aux(uint8_t *src, int src_bytes)
229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
fb0f8fbf
KP		 250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
9473c8f4
VP		 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
fb0f8fbf
KP		 261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
bf13e81b
JN		 284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
293static enum pipe
294vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
295{
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
298 struct drm_device *dev = intel_dig_port->base.base.dev;
299 struct drm_i915_private *dev_priv = dev->dev_private;
300 enum port port = intel_dig_port->port;
301 enum pipe pipe;
302
303 /* modeset should have pipe */
304 if (crtc)
305 return to_intel_crtc(crtc)->pipe;
306
307 /* init time, try to find a pipe with this port selected */
308 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
309 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
310 PANEL_PORT_SELECT_MASK;
311 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
312 return pipe;
313 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
314 return pipe;
315 }
316
317 /* shrug */
318 return PIPE_A;
319}
320
321static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
322{
323 struct drm_device *dev = intel_dp_to_dev(intel_dp);
324
325 if (HAS_PCH_SPLIT(dev))
326 return PCH_PP_CONTROL;
327 else
328 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
329}
330
331static u32 _pp_stat_reg(struct intel_dp *intel_dp)
332{
333 struct drm_device *dev = intel_dp_to_dev(intel_dp);
334
335 if (HAS_PCH_SPLIT(dev))
336 return PCH_PP_STATUS;
337 else
338 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
339}
340
01527b31
CT		 341/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
342 This function only applicable when panel PM state is not to be tracked */
343static int edp_notify_handler(struct notifier_block *this, unsigned long code,
344 void *unused)
345{
346 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
347 edp_notifier);
348 struct drm_device *dev = intel_dp_to_dev(intel_dp);
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 u32 pp_div;
351 u32 pp_ctrl_reg, pp_div_reg;
352 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
353
354 if (!is_edp(intel_dp) || code != SYS_RESTART)
355 return 0;
356
357 if (IS_VALLEYVIEW(dev)) {
358 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
359 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
360 pp_div = I915_READ(pp_div_reg);
361 pp_div &= PP_REFERENCE_DIVIDER_MASK;
362
363 /* 0x1F write to PP_DIV_REG sets max cycle delay */
364 I915_WRITE(pp_div_reg, pp_div | 0x1F);
365 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
366 msleep(intel_dp->panel_power_cycle_delay);
367 }
368
369 return 0;
370}
371
4be73780 372static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 373{
30add22d 374 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 375 struct drm_i915_private *dev_priv = dev->dev_private;
376
bf13e81b 377 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 378}
379
4be73780 380static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 381{
30add22d 382 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 383 struct drm_i915_private *dev_priv = dev->dev_private;
bb4932c4
ID		 384 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
385 struct intel_encoder *intel_encoder = &intel_dig_port->base;
386 enum intel_display_power_domain power_domain;
ebf33b18 387
bb4932c4
ID		 388 power_domain = intel_display_port_power_domain(intel_encoder);
389 return intel_display_power_enabled(dev_priv, power_domain) &&
efbc20ab 390 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 391}
392
9b984dae
KP		 393static void
394intel_dp_check_edp(struct intel_dp *intel_dp)
395{
30add22d 396 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 397 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 398
9b984dae
KP		 399 if (!is_edp(intel_dp))
400 return;
453c5420 401
4be73780 402 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 403 WARN(1, "eDP powered off while attempting aux channel communication.\n");
404 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 405 I915_READ(_pp_stat_reg(intel_dp)),
406 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 407 }
408}
409
9ee32fea
DV		 410static uint32_t
411intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
412{
413 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
414 struct drm_device *dev = intel_dig_port->base.base.dev;
415 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 416 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 417 uint32_t status;
418 bool done;
419
ef04f00d 420#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 421 if (has_aux_irq)
b18ac466 422 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 423 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 424 else
425 done = wait_for_atomic(C, 10) == 0;
426 if (!done)
427 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
428 has_aux_irq);
429#undef C
430
431 return status;
432}
433
ec5b01dd 434static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 435{
174edf1f
PZ		 436 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
437 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 438
ec5b01dd
DL		 439 /*
440 * The clock divider is based off the hrawclk, and would like to run at
441 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 442 */
ec5b01dd
DL		 443 return index ? 0 : intel_hrawclk(dev) / 2;
444}
445
446static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
447{
448 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
449 struct drm_device *dev = intel_dig_port->base.base.dev;
450
451 if (index)
452 return 0;
453
454 if (intel_dig_port->port == PORT_A) {
455 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 456 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 457 else
b84a1cf8 458 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 459 } else {
460 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
461 }
462}
463
464static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
465{
466 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
467 struct drm_device *dev = intel_dig_port->base.base.dev;
468 struct drm_i915_private *dev_priv = dev->dev_private;
469
470 if (intel_dig_port->port == PORT_A) {
471 if (index)
472 return 0;
473 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 474 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
475 /* Workaround for non-ULT HSW */
bc86625a
CW		 476 switch (index) {
477 case 0: return 63;
478 case 1: return 72;
479 default: return 0;
480 }
ec5b01dd 481 } else {
bc86625a 482 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 483 }
b84a1cf8
RV		 484}
485
ec5b01dd
DL		 486static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
487{
488 return index ? 0 : 100;
489}
490
5ed12a19
DL		 491static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
492 bool has_aux_irq,
493 int send_bytes,
494 uint32_t aux_clock_divider)
495{
496 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
497 struct drm_device *dev = intel_dig_port->base.base.dev;
498 uint32_t precharge, timeout;
499
500 if (IS_GEN6(dev))
501 precharge = 3;
502 else
503 precharge = 5;
504
505 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
506 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
507 else
508 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
509
510 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 511 DP_AUX_CH_CTL_DONE |
5ed12a19 512 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 513 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 514 timeout |
788d4433 515 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 516 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
517 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 518 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 519}
520
b84a1cf8
RV		 521static int
522intel_dp_aux_ch(struct intel_dp *intel_dp,
523 uint8_t *send, int send_bytes,
524 uint8_t *recv, int recv_size)
525{
526 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
527 struct drm_device *dev = intel_dig_port->base.base.dev;
528 struct drm_i915_private *dev_priv = dev->dev_private;
529 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
530 uint32_t ch_data = ch_ctl + 4;
bc86625a 531 uint32_t aux_clock_divider;
b84a1cf8
RV		 532 int i, ret, recv_bytes;
533 uint32_t status;
5ed12a19 534 int try, clock = 0;
4e6b788c 535 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 536 bool vdd;
537
538 vdd = _edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 539
540 /* dp aux is extremely sensitive to irq latency, hence request the
541 * lowest possible wakeup latency and so prevent the cpu from going into
542 * deep sleep states.
543 */
544 pm_qos_update_request(&dev_priv->pm_qos, 0);
545
546 intel_dp_check_edp(intel_dp);
5eb08b69 547
c67a470b
PZ		 548 intel_aux_display_runtime_get(dev_priv);
549
11bee43e
JB		 550 /* Try to wait for any previous AUX channel activity */
551 for (try = 0; try < 3; try++) {
ef04f00d 552 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 553 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
554 break;
555 msleep(1);
556 }
557
558 if (try == 3) {
559 WARN(1, "dp_aux_ch not started status 0x%08x\n",
560 I915_READ(ch_ctl));
9ee32fea
DV		 561 ret = -EBUSY;
562 goto out;
4f7f7b7e
CW		 563 }
564
46a5ae9f
PZ		 565 /* Only 5 data registers! */
566 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
567 ret = -E2BIG;
568 goto out;
569 }
570
ec5b01dd 571 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 572 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
573 has_aux_irq,
574 send_bytes,
575 aux_clock_divider);
5ed12a19 576
bc86625a
CW		 577 /* Must try at least 3 times according to DP spec */
578 for (try = 0; try < 5; try++) {
579 /* Load the send data into the aux channel data registers */
580 for (i = 0; i < send_bytes; i += 4)
581 I915_WRITE(ch_data + i,
582 pack_aux(send + i, send_bytes - i));
583
584 /* Send the command and wait for it to complete */
5ed12a19 585 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 586
587 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
588
589 /* Clear done status and any errors */
590 I915_WRITE(ch_ctl,
591 status |
592 DP_AUX_CH_CTL_DONE |
593 DP_AUX_CH_CTL_TIME_OUT_ERROR |
594 DP_AUX_CH_CTL_RECEIVE_ERROR);
595
596 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
597 DP_AUX_CH_CTL_RECEIVE_ERROR))
598 continue;
599 if (status & DP_AUX_CH_CTL_DONE)
600 break;
601 }
4f7f7b7e 602 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 603 break;
604 }
605
a4fc5ed6 606 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 607 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 608 ret = -EBUSY;
609 goto out;
a4fc5ed6
KP		 610 }
611
612 /* Check for timeout or receive error.
613 * Timeouts occur when the sink is not connected
614 */
a5b3da54 615 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 616 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 617 ret = -EIO;
618 goto out;
a5b3da54 619 }
1ae8c0a5
KP		 620
621 /* Timeouts occur when the device isn't connected, so they're
622 * "normal" -- don't fill the kernel log with these */
a5b3da54 623 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 624 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 625 ret = -ETIMEDOUT;
626 goto out;
a4fc5ed6
KP		 627 }
628
629 /* Unload any bytes sent back from the other side */
630 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
631 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 632 if (recv_bytes > recv_size)
633 recv_bytes = recv_size;
0206e353 634
4f7f7b7e
CW		 635 for (i = 0; i < recv_bytes; i += 4)
636 unpack_aux(I915_READ(ch_data + i),
637 recv + i, recv_bytes - i);
a4fc5ed6 638
9ee32fea
DV		 639 ret = recv_bytes;
640out:
641 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 642 intel_aux_display_runtime_put(dev_priv);
9ee32fea 643
884f19e9
JN		 644 if (vdd)
645 edp_panel_vdd_off(intel_dp, false);
646
9ee32fea 647 return ret;
a4fc5ed6
KP		 648}
649
a6c8aff0
JN		 650#define BARE_ADDRESS_SIZE 3
651#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 652static ssize_t
653intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 654{
9d1a1031
JN		 655 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
656 uint8_t txbuf[20], rxbuf[20];
657 size_t txsize, rxsize;
a4fc5ed6 658 int ret;
a4fc5ed6 659
9d1a1031
JN		 660 txbuf[0] = msg->request << 4;
661 txbuf[1] = msg->address >> 8;
662 txbuf[2] = msg->address & 0xff;
663 txbuf[3] = msg->size - 1;
46a5ae9f 664
9d1a1031
JN		 665 switch (msg->request & ~DP_AUX_I2C_MOT) {
666 case DP_AUX_NATIVE_WRITE:
667 case DP_AUX_I2C_WRITE:
a6c8aff0 668 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 669 rxsize = 1;
f51a44b9 670
9d1a1031
JN		 671 if (WARN_ON(txsize > 20))
672 return -E2BIG;
a4fc5ed6 673
9d1a1031 674 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 675
9d1a1031
JN		 676 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
677 if (ret > 0) {
678 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 679
9d1a1031
JN		 680 /* Return payload size. */
681 ret = msg->size;
682 }
683 break;
46a5ae9f 684
9d1a1031
JN		 685 case DP_AUX_NATIVE_READ:
686 case DP_AUX_I2C_READ:
a6c8aff0 687 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 688 rxsize = msg->size + 1;
a4fc5ed6 689
9d1a1031
JN		 690 if (WARN_ON(rxsize > 20))
691 return -E2BIG;
a4fc5ed6 692
9d1a1031
JN		 693 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
694 if (ret > 0) {
695 msg->reply = rxbuf[0] >> 4;
696 /*
697 * Assume happy day, and copy the data. The caller is
698 * expected to check msg->reply before touching it.
699 *
700 * Return payload size.
701 */
702 ret--;
703 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 704 }
9d1a1031
JN		 705 break;
706
707 default:
708 ret = -EINVAL;
709 break;
a4fc5ed6 710 }
f51a44b9 711
9d1a1031 712 return ret;
a4fc5ed6
KP		 713}
714
9d1a1031
JN		 715static void
716intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
717{
718 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 719 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
720 enum port port = intel_dig_port->port;
0b99836f 721 const char *name = NULL;
ab2c0672
DA		 722 int ret;
723
33ad6626
JN		 724 switch (port) {
725 case PORT_A:
726 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 727 name = "DPDDC-A";
ab2c0672 728 break;
33ad6626
JN		 729 case PORT_B:
730 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 731 name = "DPDDC-B";
ab2c0672 732 break;
33ad6626
JN		 733 case PORT_C:
734 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 735 name = "DPDDC-C";
ab2c0672 736 break;
33ad6626
JN		 737 case PORT_D:
738 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 739 name = "DPDDC-D";
33ad6626
JN		 740 break;
741 default:
742 BUG();
ab2c0672
DA		 743 }
744
33ad6626
JN		 745 if (!HAS_DDI(dev))
746 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 747
0b99836f 748 intel_dp->aux.name = name;
9d1a1031
JN		 749 intel_dp->aux.dev = dev->dev;
750 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 751
0b99836f
JN		 752 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
753 connector->base.kdev->kobj.name);
8316f337 754
4f71d0cb 755 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 756 if (ret < 0) {
4f71d0cb 757 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 758 name, ret);
759 return;
ab2c0672 760 }
8a5e6aeb 761
0b99836f
JN		 762 ret = sysfs_create_link(&connector->base.kdev->kobj,
763 &intel_dp->aux.ddc.dev.kobj,
764 intel_dp->aux.ddc.dev.kobj.name);
765 if (ret < 0) {
766 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 767 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 768 }
a4fc5ed6
KP		 769}
770
80f65de3
ID		 771static void
772intel_dp_connector_unregister(struct intel_connector *intel_connector)
773{
774 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
775
0e32b39c
DA		 776 if (!intel_connector->mst_port)
777 sysfs_remove_link(&intel_connector->base.kdev->kobj,
778 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 779 intel_connector_unregister(intel_connector);
780}
781
0e50338c
DV		 782static void
783hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
784{
785 switch (link_bw) {
786 case DP_LINK_BW_1_62:
787 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
788 break;
789 case DP_LINK_BW_2_7:
790 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
791 break;
792 case DP_LINK_BW_5_4:
793 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
794 break;
795 }
796}
797
c6bb3538
DV		 798static void
799intel_dp_set_clock(struct intel_encoder *encoder,
800 struct intel_crtc_config *pipe_config, int link_bw)
801{
802 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 803 const struct dp_link_dpll *divisor = NULL;
804 int i, count = 0;
c6bb3538
DV		 805
806 if (IS_G4X(dev)) {
9dd4ffdf
CML		 807 divisor = gen4_dpll;
808 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 809 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 810 divisor = pch_dpll;
811 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 812 } else if (IS_CHERRYVIEW(dev)) {
813 divisor = chv_dpll;
814 count = ARRAY_SIZE(chv_dpll);
c6bb3538 815 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 816 divisor = vlv_dpll;
817 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 818 }
9dd4ffdf
CML		 819
820 if (divisor && count) {
821 for (i = 0; i < count; i++) {
822 if (link_bw == divisor[i].link_bw) {
823 pipe_config->dpll = divisor[i].dpll;
824 pipe_config->clock_set = true;
825 break;
826 }
827 }
c6bb3538
DV		 828 }
829}
830
00c09d70 831bool
5bfe2ac0
DV		 832intel_dp_compute_config(struct intel_encoder *encoder,
833 struct intel_crtc_config *pipe_config)
a4fc5ed6 834{
5bfe2ac0 835 struct drm_device *dev = encoder->base.dev;
36008365 836 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 837 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 838 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 839 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 840 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 841 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 842 int lane_count, clock;
56071a20 843 int min_lane_count = 1;
eeb6324d 844 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 845 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 846 int min_clock = 0;
06ea66b6 847 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 848 int bpp, mode_rate;
06ea66b6 849 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 850 int link_avail, link_clock;
a4fc5ed6 851
bc7d38a4 852 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 853 pipe_config->has_pch_encoder = true;
854
03afc4a2 855 pipe_config->has_dp_encoder = true;
f769cd24 856 pipe_config->has_drrs = false;
9ed109a7 857 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 858
dd06f90e
JN		 859 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
860 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
861 adjusted_mode);
2dd24552
JB		 862 if (!HAS_PCH_SPLIT(dev))
863 intel_gmch_panel_fitting(intel_crtc, pipe_config,
864 intel_connector->panel.fitting_mode);
865 else
b074cec8
JB		 866 intel_pch_panel_fitting(intel_crtc, pipe_config,
867 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 868 }
869
cb1793ce 870 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 871 return false;
872
083f9560
DV		 873 DRM_DEBUG_KMS("DP link computation with max lane count %i "
874 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 875 max_lane_count, bws[max_clock],
876 adjusted_mode->crtc_clock);
083f9560 877
36008365
DV		 878 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
879 * bpc in between. */
3e7ca985 880 bpp = pipe_config->pipe_bpp;
56071a20
JN		 881 if (is_edp(intel_dp)) {
882 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
883 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
884 dev_priv->vbt.edp_bpp);
885 bpp = dev_priv->vbt.edp_bpp;
886 }
887
f4cdbc21
JN		 888 if (IS_BROADWELL(dev)) {
889 /* Yes, it's an ugly hack. */
890 min_lane_count = max_lane_count;
891 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
892 min_lane_count);
893 } else if (dev_priv->vbt.edp_lanes) {
56071a20
JN		 894 min_lane_count = min(dev_priv->vbt.edp_lanes,
895 max_lane_count);
896 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
897 min_lane_count);
898 }
899
900 if (dev_priv->vbt.edp_rate) {
901 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
902 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
903 bws[min_clock]);
904 }
7984211e 905 }
657445fe 906
36008365 907 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 908 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
909 bpp);
36008365 910
c6930992
DA		 911 for (clock = min_clock; clock <= max_clock; clock++) {
912 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 913 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
914 link_avail = intel_dp_max_data_rate(link_clock,
915 lane_count);
916
917 if (mode_rate <= link_avail) {
918 goto found;
919 }
920 }
921 }
922 }
c4867936 923
36008365 924 return false;
3685a8f3 925
36008365 926found:
55bc60db
VS		 927 if (intel_dp->color_range_auto) {
928 /*
929 * See:
930 * CEA-861-E - 5.1 Default Encoding Parameters
931 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
932 */
18316c8c 933 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 934 intel_dp->color_range = DP_COLOR_RANGE_16_235;
935 else
936 intel_dp->color_range = 0;
937 }
938
3685a8f3 939 if (intel_dp->color_range)
50f3b016 940 pipe_config->limited_color_range = true;
a4fc5ed6 941
36008365
DV		 942 intel_dp->link_bw = bws[clock];
943 intel_dp->lane_count = lane_count;
657445fe 944 pipe_config->pipe_bpp = bpp;
ff9a6750 945 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 946
36008365
DV		 947 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
948 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 949 pipe_config->port_clock, bpp);
36008365
DV		 950 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
951 mode_rate, link_avail);
a4fc5ed6 952
03afc4a2 953 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 954 adjusted_mode->crtc_clock,
955 pipe_config->port_clock,
03afc4a2 956 &pipe_config->dp_m_n);
9d1a455b 957
439d7ac0
PB		 958 if (intel_connector->panel.downclock_mode != NULL &&
959 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 960 pipe_config->has_drrs = true;
439d7ac0
PB		 961 intel_link_compute_m_n(bpp, lane_count,
962 intel_connector->panel.downclock_mode->clock,
963 pipe_config->port_clock,
964 &pipe_config->dp_m2_n2);
965 }
966
ea155f32 967 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 968 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
969 else
970 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 971
03afc4a2 972 return true;
a4fc5ed6
KP		 973}
974
7c62a164 975static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 976{
7c62a164
DV		 977 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
978 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
979 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 980 struct drm_i915_private *dev_priv = dev->dev_private;
981 u32 dpa_ctl;
982
ff9a6750 983 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 984 dpa_ctl = I915_READ(DP_A);
985 dpa_ctl &= ~DP_PLL_FREQ_MASK;
986
ff9a6750 987 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 988 /* For a long time we've carried around a ILK-DevA w/a for the
989 * 160MHz clock. If we're really unlucky, it's still required.
990 */
991 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 992 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 993 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 994 } else {
995 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 996 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 997 }
1ce17038 998
ea9b6006
DV		 999 I915_WRITE(DP_A, dpa_ctl);
1000
1001 POSTING_READ(DP_A);
1002 udelay(500);
1003}
1004
8ac33ed3 1005static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1006{
b934223d 1007 struct drm_device *dev = encoder->base.dev;
417e822d 1008 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1009 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1010 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1011 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1012 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1013
417e822d 1014 /*
1a2eb460 1015 * There are four kinds of DP registers:
417e822d
KP		 1016 *
1017 * IBX PCH
1a2eb460
KP		 1018 * SNB CPU
1019 * IVB CPU
417e822d
KP		 1020 * CPT PCH
1021 *
1022 * IBX PCH and CPU are the same for almost everything,
1023 * except that the CPU DP PLL is configured in this
1024 * register
1025 *
1026 * CPT PCH is quite different, having many bits moved
1027 * to the TRANS_DP_CTL register instead. That
1028 * configuration happens (oddly) in ironlake_pch_enable
1029 */
9c9e7927 1030
417e822d
KP		 1031 /* Preserve the BIOS-computed detected bit. This is
1032 * supposed to be read-only.
1033 */
1034 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1035
417e822d 1036 /* Handle DP bits in common between all three register formats */
417e822d 1037 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1038 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1039
9ed109a7 1040 if (crtc->config.has_audio) {
e0dac65e 1041 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1042 pipe_name(crtc->pipe));
ea5b213a 1043 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1044 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1045 }
247d89f6 1046
417e822d 1047 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1048
bc7d38a4 1049 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1050 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1051 intel_dp->DP |= DP_SYNC_HS_HIGH;
1052 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1053 intel_dp->DP |= DP_SYNC_VS_HIGH;
1054 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1055
6aba5b6c 1056 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1057 intel_dp->DP |= DP_ENHANCED_FRAMING;
1058
7c62a164 1059 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1060 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1061 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1062 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1063
1064 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1065 intel_dp->DP |= DP_SYNC_HS_HIGH;
1066 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1067 intel_dp->DP |= DP_SYNC_VS_HIGH;
1068 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1069
6aba5b6c 1070 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1071 intel_dp->DP |= DP_ENHANCED_FRAMING;
1072
44f37d1f
CML		 1073 if (!IS_CHERRYVIEW(dev)) {
1074 if (crtc->pipe == 1)
1075 intel_dp->DP |= DP_PIPEB_SELECT;
1076 } else {
1077 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1078 }
417e822d
KP		 1079 } else {
1080 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1081 }
a4fc5ed6
KP		 1082}
1083
ffd6749d
PZ		 1084#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1085#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1086
1a5ef5b7
PZ		 1087#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1088#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1089
ffd6749d
PZ		 1090#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1091#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1092
4be73780 1093static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1094 u32 mask,
1095 u32 value)
bd943159 1096{
30add22d 1097 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1098 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1099 u32 pp_stat_reg, pp_ctrl_reg;
1100
bf13e81b
JN		 1101 pp_stat_reg = _pp_stat_reg(intel_dp);
1102 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1103
99ea7127 1104 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1105 mask, value,
1106 I915_READ(pp_stat_reg),
1107 I915_READ(pp_ctrl_reg));
32ce697c 1108
453c5420 1109 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1110 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1111 I915_READ(pp_stat_reg),
1112 I915_READ(pp_ctrl_reg));
32ce697c 1113 }
54c136d4
CW		 1114
1115 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1116}
32ce697c 1117
4be73780 1118static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1119{
1120 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1121 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1122}
1123
4be73780 1124static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1125{
1126 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1127 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1128}
1129
4be73780 1130static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1131{
1132 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1133
1134 /* When we disable the VDD override bit last we have to do the manual
1135 * wait. */
1136 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1137 intel_dp->panel_power_cycle_delay);
1138
4be73780 1139 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1140}
1141
4be73780 1142static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1143{
1144 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1145 intel_dp->backlight_on_delay);
1146}
1147
4be73780 1148static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1149{
1150 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1151 intel_dp->backlight_off_delay);
1152}
99ea7127 1153
832dd3c1
KP		 1154/* Read the current pp_control value, unlocking the register if it
1155 * is locked
1156 */
1157
453c5420 1158static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1159{
453c5420
JB		 1160 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1161 struct drm_i915_private *dev_priv = dev->dev_private;
1162 u32 control;
832dd3c1 1163
bf13e81b 1164 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1165 control &= ~PANEL_UNLOCK_MASK;
1166 control |= PANEL_UNLOCK_REGS;
1167 return control;
bd943159
KP		 1168}
1169
adddaaf4 1170static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1171{
30add22d 1172 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1173 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1174 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1175 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1176 enum intel_display_power_domain power_domain;
5d613501 1177 u32 pp;
453c5420 1178 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1179 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1180
97af61f5 1181 if (!is_edp(intel_dp))
adddaaf4 1182 return false;
bd943159
KP		 1183
1184 intel_dp->want_panel_vdd = true;
99ea7127 1185
4be73780 1186 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1187 return need_to_disable;
b0665d57 1188
4e6e1a54
ID		 1189 power_domain = intel_display_port_power_domain(intel_encoder);
1190 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1191
b0665d57 1192 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1193
4be73780
DV		 1194 if (!edp_have_panel_power(intel_dp))
1195 wait_panel_power_cycle(intel_dp);
99ea7127 1196
453c5420 1197 pp = ironlake_get_pp_control(intel_dp);
5d613501 1198 pp |= EDP_FORCE_VDD;
ebf33b18 1199
bf13e81b
JN		 1200 pp_stat_reg = _pp_stat_reg(intel_dp);
1201 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1202
1203 I915_WRITE(pp_ctrl_reg, pp);
1204 POSTING_READ(pp_ctrl_reg);
1205 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1206 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1207 /*
1208 * If the panel wasn't on, delay before accessing aux channel
1209 */
4be73780 1210 if (!edp_have_panel_power(intel_dp)) {
bd943159 1211 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1212 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1213 }
adddaaf4
JN		 1214
1215 return need_to_disable;
1216}
1217
b80d6c78 1218void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4
JN		 1219{
1220 if (is_edp(intel_dp)) {
1221 bool vdd = _edp_panel_vdd_on(intel_dp);
1222
1223 WARN(!vdd, "eDP VDD already requested on\n");
1224 }
5d613501
JB		 1225}
1226
4be73780 1227static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1228{
30add22d 1229 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1230 struct drm_i915_private *dev_priv = dev->dev_private;
1231 u32 pp;
453c5420 1232 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1233
51fd371b 1234 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
a0e99e68 1235
4be73780 1236 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
4e6e1a54
ID		 1237 struct intel_digital_port *intel_dig_port =
1238 dp_to_dig_port(intel_dp);
1239 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1240 enum intel_display_power_domain power_domain;
1241
b0665d57
PZ		 1242 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1243
453c5420 1244 pp = ironlake_get_pp_control(intel_dp);
bd943159 1245 pp &= ~EDP_FORCE_VDD;
bd943159 1246
9f08ef59
PZ		 1247 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1248 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1249
1250 I915_WRITE(pp_ctrl_reg, pp);
1251 POSTING_READ(pp_ctrl_reg);
99ea7127 1252
453c5420
JB		 1253 /* Make sure sequencer is idle before allowing subsequent activity */
1254 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1255 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1256
1257 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1258 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1259
4e6e1a54
ID		 1260 power_domain = intel_display_port_power_domain(intel_encoder);
1261 intel_display_power_put(dev_priv, power_domain);
bd943159
KP		 1262 }
1263}
5d613501 1264
4be73780 1265static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1266{
1267 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1268 struct intel_dp, panel_vdd_work);
30add22d 1269 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1270
51fd371b 1271 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 1272 edp_panel_vdd_off_sync(intel_dp);
51fd371b 1273 drm_modeset_unlock(&dev->mode_config.connection_mutex);
bd943159
KP		 1274}
1275
aba86890
ID		 1276static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1277{
1278 unsigned long delay;
1279
1280 /*
1281 * Queue the timer to fire a long time from now (relative to the power
1282 * down delay) to keep the panel power up across a sequence of
1283 * operations.
1284 */
1285 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1286 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1287}
1288
4be73780 1289static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1290{
97af61f5
KP		 1291 if (!is_edp(intel_dp))
1292 return;
5d613501 1293
bd943159 1294 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1295
bd943159
KP		 1296 intel_dp->want_panel_vdd = false;
1297
aba86890 1298 if (sync)
4be73780 1299 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1300 else
1301 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1302}
1303
4be73780 1304void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1305{
30add22d 1306 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1307 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1308 u32 pp;
453c5420 1309 u32 pp_ctrl_reg;
9934c132 1310
97af61f5 1311 if (!is_edp(intel_dp))
bd943159 1312 return;
99ea7127
KP		 1313
1314 DRM_DEBUG_KMS("Turn eDP power on\n");
1315
4be73780 1316 if (edp_have_panel_power(intel_dp)) {
99ea7127 1317 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1318 return;
99ea7127 1319 }
9934c132 1320
4be73780 1321 wait_panel_power_cycle(intel_dp);
37c6c9b0 1322
bf13e81b 1323 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1324 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1325 if (IS_GEN5(dev)) {
1326 /* ILK workaround: disable reset around power sequence */
1327 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1328 I915_WRITE(pp_ctrl_reg, pp);
1329 POSTING_READ(pp_ctrl_reg);
05ce1a49 1330 }
37c6c9b0 1331
1c0ae80a 1332 pp |= POWER_TARGET_ON;
99ea7127
KP		 1333 if (!IS_GEN5(dev))
1334 pp |= PANEL_POWER_RESET;
1335
453c5420
JB		 1336 I915_WRITE(pp_ctrl_reg, pp);
1337 POSTING_READ(pp_ctrl_reg);
9934c132 1338
4be73780 1339 wait_panel_on(intel_dp);
dce56b3c 1340 intel_dp->last_power_on = jiffies;
9934c132 1341
05ce1a49
KP		 1342 if (IS_GEN5(dev)) {
1343 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1344 I915_WRITE(pp_ctrl_reg, pp);
1345 POSTING_READ(pp_ctrl_reg);
05ce1a49 1346 }
9934c132
JB		 1347}
1348
4be73780 1349void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1350{
4e6e1a54
ID		 1351 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1352 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1353 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1354 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1355 enum intel_display_power_domain power_domain;
99ea7127 1356 u32 pp;
453c5420 1357 u32 pp_ctrl_reg;
9934c132 1358
97af61f5
KP		 1359 if (!is_edp(intel_dp))
1360 return;
37c6c9b0 1361
99ea7127 1362 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1363
24f3e092
JN		 1364 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1365
453c5420 1366 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1367 /* We need to switch off panel power _and_ force vdd, for otherwise some
1368 * panels get very unhappy and cease to work. */
b3064154
PJ		 1369 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1370 EDP_BLC_ENABLE);
453c5420 1371
bf13e81b 1372 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1373
849e39f5
PZ		 1374 intel_dp->want_panel_vdd = false;
1375
453c5420
JB		 1376 I915_WRITE(pp_ctrl_reg, pp);
1377 POSTING_READ(pp_ctrl_reg);
9934c132 1378
dce56b3c 1379 intel_dp->last_power_cycle = jiffies;
4be73780 1380 wait_panel_off(intel_dp);
849e39f5
PZ		 1381
1382 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1383 power_domain = intel_display_port_power_domain(intel_encoder);
1384 intel_display_power_put(dev_priv, power_domain);
9934c132
JB		 1385}
1386
4be73780 1387void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1388{
da63a9f2
PZ		 1389 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1390 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1391 struct drm_i915_private *dev_priv = dev->dev_private;
1392 u32 pp;
453c5420 1393 u32 pp_ctrl_reg;
32f9d658 1394
f01eca2e
KP		 1395 if (!is_edp(intel_dp))
1396 return;
1397
28c97730 1398 DRM_DEBUG_KMS("\n");
f7d2323c
JB		 1399
1400 intel_panel_enable_backlight(intel_dp->attached_connector);
1401
01cb9ea6
JB		 1402 /*
1403 * If we enable the backlight right away following a panel power
1404 * on, we may see slight flicker as the panel syncs with the eDP
1405 * link. So delay a bit to make sure the image is solid before
1406 * allowing it to appear.
1407 */
4be73780 1408 wait_backlight_on(intel_dp);
453c5420 1409 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1410 pp |= EDP_BLC_ENABLE;
453c5420 1411
bf13e81b 1412 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1413
1414 I915_WRITE(pp_ctrl_reg, pp);
1415 POSTING_READ(pp_ctrl_reg);
32f9d658
ZW		 1416}
1417
4be73780 1418void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1419{
30add22d 1420 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1421 struct drm_i915_private *dev_priv = dev->dev_private;
1422 u32 pp;
453c5420 1423 u32 pp_ctrl_reg;
32f9d658 1424
f01eca2e
KP		 1425 if (!is_edp(intel_dp))
1426 return;
1427
28c97730 1428 DRM_DEBUG_KMS("\n");
453c5420 1429 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1430 pp &= ~EDP_BLC_ENABLE;
453c5420 1431
bf13e81b 1432 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1433
1434 I915_WRITE(pp_ctrl_reg, pp);
1435 POSTING_READ(pp_ctrl_reg);
dce56b3c 1436 intel_dp->last_backlight_off = jiffies;
f7d2323c
JB		 1437
1438 edp_wait_backlight_off(intel_dp);
1439
1440 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1441}
a4fc5ed6 1442
2bd2ad64 1443static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1444{
da63a9f2
PZ		 1445 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1446 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1447 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1448 struct drm_i915_private *dev_priv = dev->dev_private;
1449 u32 dpa_ctl;
1450
2bd2ad64
DV		 1451 assert_pipe_disabled(dev_priv,
1452 to_intel_crtc(crtc)->pipe);
1453
d240f20f
JB		 1454 DRM_DEBUG_KMS("\n");
1455 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1456 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1457 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1458
1459 /* We don't adjust intel_dp->DP while tearing down the link, to
1460 * facilitate link retraining (e.g. after hotplug). Hence clear all
1461 * enable bits here to ensure that we don't enable too much. */
1462 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1463 intel_dp->DP |= DP_PLL_ENABLE;
1464 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1465 POSTING_READ(DP_A);
1466 udelay(200);
d240f20f
JB		 1467}
1468
2bd2ad64 1469static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1470{
da63a9f2
PZ		 1471 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1472 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1473 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1474 struct drm_i915_private *dev_priv = dev->dev_private;
1475 u32 dpa_ctl;
1476
2bd2ad64
DV		 1477 assert_pipe_disabled(dev_priv,
1478 to_intel_crtc(crtc)->pipe);
1479
d240f20f 1480 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1481 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1482 "dp pll off, should be on\n");
1483 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1484
1485 /* We can't rely on the value tracked for the DP register in
1486 * intel_dp->DP because link_down must not change that (otherwise link
1487 * re-training will fail. */
298b0b39 1488 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1489 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1490 POSTING_READ(DP_A);
d240f20f
JB		 1491 udelay(200);
1492}
1493
c7ad3810 1494/* If the sink supports it, try to set the power state appropriately */
c19b0669 1495void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1496{
1497 int ret, i;
1498
1499 /* Should have a valid DPCD by this point */
1500 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1501 return;
1502
1503 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1504 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1505 DP_SET_POWER_D3);
c7ad3810
JB		 1506 if (ret != 1)
1507 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1508 } else {
1509 /*
1510 * When turning on, we need to retry for 1ms to give the sink
1511 * time to wake up.
1512 */
1513 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1514 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1515 DP_SET_POWER_D0);
c7ad3810
JB		 1516 if (ret == 1)
1517 break;
1518 msleep(1);
1519 }
1520 }
1521}
1522
19d8fe15
DV		 1523static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1524 enum pipe *pipe)
d240f20f 1525{
19d8fe15 1526 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1527 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1528 struct drm_device *dev = encoder->base.dev;
1529 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1530 enum intel_display_power_domain power_domain;
1531 u32 tmp;
1532
1533 power_domain = intel_display_port_power_domain(encoder);
1534 if (!intel_display_power_enabled(dev_priv, power_domain))
1535 return false;
1536
1537 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1538
1539 if (!(tmp & DP_PORT_EN))
1540 return false;
1541
bc7d38a4 1542 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1543 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1544 } else if (IS_CHERRYVIEW(dev)) {
1545 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1546 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1547 *pipe = PORT_TO_PIPE(tmp);
1548 } else {
1549 u32 trans_sel;
1550 u32 trans_dp;
1551 int i;
1552
1553 switch (intel_dp->output_reg) {
1554 case PCH_DP_B:
1555 trans_sel = TRANS_DP_PORT_SEL_B;
1556 break;
1557 case PCH_DP_C:
1558 trans_sel = TRANS_DP_PORT_SEL_C;
1559 break;
1560 case PCH_DP_D:
1561 trans_sel = TRANS_DP_PORT_SEL_D;
1562 break;
1563 default:
1564 return true;
1565 }
1566
1567 for_each_pipe(i) {
1568 trans_dp = I915_READ(TRANS_DP_CTL(i));
1569 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1570 *pipe = i;
1571 return true;
1572 }
1573 }
19d8fe15 1574
4a0833ec
DV		 1575 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1576 intel_dp->output_reg);
1577 }
d240f20f 1578
19d8fe15
DV		 1579 return true;
1580}
d240f20f 1581
045ac3b5
JB		 1582static void intel_dp_get_config(struct intel_encoder *encoder,
1583 struct intel_crtc_config *pipe_config)
1584{
1585 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1586 u32 tmp, flags = 0;
63000ef6
XZ		 1587 struct drm_device *dev = encoder->base.dev;
1588 struct drm_i915_private *dev_priv = dev->dev_private;
1589 enum port port = dp_to_dig_port(intel_dp)->port;
1590 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1591 int dotclock;
045ac3b5 1592
9ed109a7
DV		 1593 tmp = I915_READ(intel_dp->output_reg);
1594 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1595 pipe_config->has_audio = true;
1596
63000ef6 1597 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1598 if (tmp & DP_SYNC_HS_HIGH)
1599 flags |= DRM_MODE_FLAG_PHSYNC;
1600 else
1601 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1602
63000ef6
XZ		 1603 if (tmp & DP_SYNC_VS_HIGH)
1604 flags |= DRM_MODE_FLAG_PVSYNC;
1605 else
1606 flags |= DRM_MODE_FLAG_NVSYNC;
1607 } else {
1608 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1609 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1610 flags |= DRM_MODE_FLAG_PHSYNC;
1611 else
1612 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1613
63000ef6
XZ		 1614 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1615 flags |= DRM_MODE_FLAG_PVSYNC;
1616 else
1617 flags |= DRM_MODE_FLAG_NVSYNC;
1618 }
045ac3b5
JB		 1619
1620 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1621
eb14cb74
VS		 1622 pipe_config->has_dp_encoder = true;
1623
1624 intel_dp_get_m_n(crtc, pipe_config);
1625
18442d08 1626 if (port == PORT_A) {
f1f644dc
JB		 1627 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1628 pipe_config->port_clock = 162000;
1629 else
1630 pipe_config->port_clock = 270000;
1631 }
18442d08
VS		 1632
1633 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1634 &pipe_config->dp_m_n);
1635
1636 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1637 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1638
241bfc38 1639 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1640
c6cd2ee2
JN		 1641 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1642 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1643 /*
1644 * This is a big fat ugly hack.
1645 *
1646 * Some machines in UEFI boot mode provide us a VBT that has 18
1647 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1648 * unknown we fail to light up. Yet the same BIOS boots up with
1649 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1650 * max, not what it tells us to use.
1651 *
1652 * Note: This will still be broken if the eDP panel is not lit
1653 * up by the BIOS, and thus we can't get the mode at module
1654 * load.
1655 */
1656 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1657 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1658 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1659 }
045ac3b5
JB		 1660}
1661
34eb7579 1662static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1663{
34eb7579 1664 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1665}
1666
2b28bb1b
RV		 1667static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1668{
1669 struct drm_i915_private *dev_priv = dev->dev_private;
1670
18b5992c 1671 if (!HAS_PSR(dev))
2b28bb1b
RV		 1672 return false;
1673
18b5992c 1674 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1675}
1676
1677static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1678 struct edp_vsc_psr *vsc_psr)
1679{
1680 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1681 struct drm_device *dev = dig_port->base.base.dev;
1682 struct drm_i915_private *dev_priv = dev->dev_private;
1683 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1684 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1685 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1686 uint32_t *data = (uint32_t *) vsc_psr;
1687 unsigned int i;
1688
1689 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1690 the video DIP being updated before program video DIP data buffer
1691 registers for DIP being updated. */
1692 I915_WRITE(ctl_reg, 0);
1693 POSTING_READ(ctl_reg);
1694
1695 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1696 if (i < sizeof(struct edp_vsc_psr))
1697 I915_WRITE(data_reg + i, *data++);
1698 else
1699 I915_WRITE(data_reg + i, 0);
1700 }
1701
1702 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1703 POSTING_READ(ctl_reg);
1704}
1705
1706static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1707{
1708 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1709 struct drm_i915_private *dev_priv = dev->dev_private;
1710 struct edp_vsc_psr psr_vsc;
1711
2b28bb1b
RV		 1712 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1713 memset(&psr_vsc, 0, sizeof(psr_vsc));
1714 psr_vsc.sdp_header.HB0 = 0;
1715 psr_vsc.sdp_header.HB1 = 0x7;
1716 psr_vsc.sdp_header.HB2 = 0x2;
1717 psr_vsc.sdp_header.HB3 = 0x8;
1718 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1719
1720 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1721 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1722 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1723}
1724
1725static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1726{
0e0ae652
RV		 1727 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1728 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 1729 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1730 uint32_t aux_clock_divider;
2b28bb1b
RV		 1731 int precharge = 0x3;
1732 int msg_size = 5; /* Header(4) + Message(1) */
0e0ae652 1733 bool only_standby = false;
2b28bb1b 1734
ec5b01dd
DL		 1735 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1736
0e0ae652
RV		 1737 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1738 only_standby = true;
1739
2b28bb1b 1740 /* Enable PSR in sink */
0e0ae652 1741 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 1742 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1743 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1744 else
9d1a1031
JN		 1745 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1746 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1747
1748 /* Setup AUX registers */
18b5992c
BW		 1749 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1750 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1751 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1752 DP_AUX_CH_CTL_TIME_OUT_400us |
1753 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1754 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1755 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1756}
1757
1758static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1759{
0e0ae652
RV		 1760 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1761 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 1762 struct drm_i915_private *dev_priv = dev->dev_private;
1763 uint32_t max_sleep_time = 0x1f;
1764 uint32_t idle_frames = 1;
1765 uint32_t val = 0x0;
ed8546ac 1766 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 1767 bool only_standby = false;
1768
1769 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1770 only_standby = true;
2b28bb1b 1771
0e0ae652 1772 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 1773 val |= EDP_PSR_LINK_STANDBY;
1774 val |= EDP_PSR_TP2_TP3_TIME_0us;
1775 val |= EDP_PSR_TP1_TIME_0us;
1776 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 1777 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 1778 } else
1779 val |= EDP_PSR_LINK_DISABLE;
1780
18b5992c 1781 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1782 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1783 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1784 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1785 EDP_PSR_ENABLE);
1786}
1787
3f51e471
RV		 1788static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1789{
1790 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1791 struct drm_device *dev = dig_port->base.base.dev;
1792 struct drm_i915_private *dev_priv = dev->dev_private;
1793 struct drm_crtc *crtc = dig_port->base.base.crtc;
1794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 1795
f0355c4a 1796 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 1797 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1798 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
1799
a031d709
RV		 1800 dev_priv->psr.source_ok = false;
1801
9ca15301 1802 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 1803 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1804 return false;
1805 }
1806
d330a953 1807 if (!i915.enable_psr) {
105b7c11 1808 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1809 return false;
1810 }
1811
4c8c7000
RV		 1812 /* Below limitations aren't valid for Broadwell */
1813 if (IS_BROADWELL(dev))
1814 goto out;
1815
3f51e471
RV		 1816 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1817 S3D_ENABLE) {
1818 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1819 return false;
1820 }
1821
ca73b4f0 1822 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1823 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1824 return false;
1825 }
1826
4c8c7000 1827 out:
a031d709 1828 dev_priv->psr.source_ok = true;
3f51e471
RV		 1829 return true;
1830}
1831
3d739d92 1832static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 1833{
7c8f8a70
RV		 1834 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1835 struct drm_device *dev = intel_dig_port->base.base.dev;
1836 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 1837
3638379c
DV		 1838 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1839 WARN_ON(dev_priv->psr.active);
f0355c4a 1840 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 1841
2b28bb1b
RV		 1842 /* Enable PSR on the panel */
1843 intel_edp_psr_enable_sink(intel_dp);
1844
1845 /* Enable PSR on the host */
1846 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 1847
7c8f8a70 1848 dev_priv->psr.active = true;
2b28bb1b
RV		 1849}
1850
3d739d92
RV		 1851void intel_edp_psr_enable(struct intel_dp *intel_dp)
1852{
1853 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 1854 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 1855
4704c573
RV		 1856 if (!HAS_PSR(dev)) {
1857 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1858 return;
1859 }
1860
34eb7579
RV		 1861 if (!is_edp_psr(intel_dp)) {
1862 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1863 return;
1864 }
1865
f0355c4a 1866 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 1867 if (dev_priv->psr.enabled) {
1868 DRM_DEBUG_KMS("PSR already in use\n");
f0355c4a 1869 mutex_unlock(&dev_priv->psr.lock);
109fc2ad
DV		 1870 return;
1871 }
1872
9ca15301
DV		 1873 dev_priv->psr.busy_frontbuffer_bits = 0;
1874
16487254
RV		 1875 /* Setup PSR once */
1876 intel_edp_psr_setup(intel_dp);
1877
7c8f8a70 1878 if (intel_edp_psr_match_conditions(intel_dp))
9ca15301 1879 dev_priv->psr.enabled = intel_dp;
f0355c4a 1880 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 1881}
1882
2b28bb1b
RV		 1883void intel_edp_psr_disable(struct intel_dp *intel_dp)
1884{
1885 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1886 struct drm_i915_private *dev_priv = dev->dev_private;
1887
f0355c4a
DV		 1888 mutex_lock(&dev_priv->psr.lock);
1889 if (!dev_priv->psr.enabled) {
1890 mutex_unlock(&dev_priv->psr.lock);
1891 return;
1892 }
1893
3638379c
DV		 1894 if (dev_priv->psr.active) {
1895 I915_WRITE(EDP_PSR_CTL(dev),
1896 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1897
1898 /* Wait till PSR is idle */
1899 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1900 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1901 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 1902
3638379c
DV		 1903 dev_priv->psr.active = false;
1904 } else {
1905 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1906 }
7c8f8a70 1907
2807cf69 1908 dev_priv->psr.enabled = NULL;
f0355c4a 1909 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 1910
1911 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 1912}
1913
f02a326e 1914static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 1915{
1916 struct drm_i915_private *dev_priv =
1917 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 1918 struct intel_dp *intel_dp = dev_priv->psr.enabled;
1919
f0355c4a
DV		 1920 mutex_lock(&dev_priv->psr.lock);
1921 intel_dp = dev_priv->psr.enabled;
1922
2807cf69 1923 if (!intel_dp)
f0355c4a 1924 goto unlock;
2807cf69 1925
9ca15301
DV		 1926 /*
1927 * The delayed work can race with an invalidate hence we need to
1928 * recheck. Since psr_flush first clears this and then reschedules we
1929 * won't ever miss a flush when bailing out here.
1930 */
1931 if (dev_priv->psr.busy_frontbuffer_bits)
1932 goto unlock;
1933
1934 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 1935unlock:
1936 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 1937}
1938
9ca15301 1939static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 1940{
1941 struct drm_i915_private *dev_priv = dev->dev_private;
1942
3638379c
DV		 1943 if (dev_priv->psr.active) {
1944 u32 val = I915_READ(EDP_PSR_CTL(dev));
1945
1946 WARN_ON(!(val & EDP_PSR_ENABLE));
1947
1948 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
1949
1950 dev_priv->psr.active = false;
1951 }
7c8f8a70 1952
9ca15301
DV		 1953}
1954
1955void intel_edp_psr_invalidate(struct drm_device *dev,
1956 unsigned frontbuffer_bits)
1957{
1958 struct drm_i915_private *dev_priv = dev->dev_private;
1959 struct drm_crtc *crtc;
1960 enum pipe pipe;
1961
9ca15301
DV		 1962 mutex_lock(&dev_priv->psr.lock);
1963 if (!dev_priv->psr.enabled) {
1964 mutex_unlock(&dev_priv->psr.lock);
1965 return;
1966 }
1967
1968 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
1969 pipe = to_intel_crtc(crtc)->pipe;
1970
1971 intel_edp_psr_do_exit(dev);
1972
1973 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
1974
1975 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
1976 mutex_unlock(&dev_priv->psr.lock);
1977}
1978
1979void intel_edp_psr_flush(struct drm_device *dev,
1980 unsigned frontbuffer_bits)
1981{
1982 struct drm_i915_private *dev_priv = dev->dev_private;
1983 struct drm_crtc *crtc;
1984 enum pipe pipe;
1985
9ca15301
DV		 1986 mutex_lock(&dev_priv->psr.lock);
1987 if (!dev_priv->psr.enabled) {
1988 mutex_unlock(&dev_priv->psr.lock);
1989 return;
1990 }
1991
1992 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
1993 pipe = to_intel_crtc(crtc)->pipe;
1994 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
1995
1996 /*
1997 * On Haswell sprite plane updates don't result in a psr invalidating
1998 * signal in the hardware. Which means we need to manually fake this in
1999 * software for all flushes, not just when we've seen a preceding
2000 * invalidation through frontbuffer rendering.
2001 */
2002 if (IS_HASWELL(dev) &&
2003 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2004 intel_edp_psr_do_exit(dev);
2005
2006 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2007 schedule_delayed_work(&dev_priv->psr.work,
2008 msecs_to_jiffies(100));
f0355c4a 2009 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2010}
2011
2012void intel_edp_psr_init(struct drm_device *dev)
2013{
2014 struct drm_i915_private *dev_priv = dev->dev_private;
2015
7c8f8a70 2016 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2017 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2018}
2019
e8cb4558 2020static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2021{
e8cb4558 2022 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 2023 enum port port = dp_to_dig_port(intel_dp)->port;
2024 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2025
2026 /* Make sure the panel is off before trying to change the mode. But also
2027 * ensure that we have vdd while we switch off the panel. */
24f3e092 2028 intel_edp_panel_vdd_on(intel_dp);
4be73780 2029 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2030 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2031 intel_edp_panel_off(intel_dp);
3739850b
DV		 2032
2033 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 2034 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 2035 intel_dp_link_down(intel_dp);
d240f20f
JB		 2036}
2037
49277c31 2038static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2039{
2bd2ad64 2040 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2041 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2042
49277c31
VS		 2043 if (port != PORT_A)
2044 return;
2045
2046 intel_dp_link_down(intel_dp);
2047 ironlake_edp_pll_off(intel_dp);
2048}
2049
2050static void vlv_post_disable_dp(struct intel_encoder *encoder)
2051{
2052 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2053
2054 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2055}
2056
580d3811
VS		 2057static void chv_post_disable_dp(struct intel_encoder *encoder)
2058{
2059 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2060 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2061 struct drm_device *dev = encoder->base.dev;
2062 struct drm_i915_private *dev_priv = dev->dev_private;
2063 struct intel_crtc *intel_crtc =
2064 to_intel_crtc(encoder->base.crtc);
2065 enum dpio_channel ch = vlv_dport_to_channel(dport);
2066 enum pipe pipe = intel_crtc->pipe;
2067 u32 val;
2068
2069 intel_dp_link_down(intel_dp);
2070
2071 mutex_lock(&dev_priv->dpio_lock);
2072
2073 /* Propagate soft reset to data lane reset */
97fd4d5c 2074 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2075 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2076 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2077
97fd4d5c
VS		 2078 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2079 val |= CHV_PCS_REQ_SOFTRESET_EN;
2080 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2081
2082 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2083 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2084 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2085
2086 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2087 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2088 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2089
2090 mutex_unlock(&dev_priv->dpio_lock);
2091}
2092
e8cb4558 2093static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2094{
e8cb4558
DV		 2095 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2096 struct drm_device *dev = encoder->base.dev;
2097 struct drm_i915_private *dev_priv = dev->dev_private;
2098 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2099
0c33d8d7
DV		 2100 if (WARN_ON(dp_reg & DP_PORT_EN))
2101 return;
5d613501 2102
24f3e092 2103 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 2104 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2105 intel_dp_start_link_train(intel_dp);
4be73780
DV		 2106 intel_edp_panel_on(intel_dp);
2107 edp_panel_vdd_off(intel_dp, true);
33a34e4e 2108 intel_dp_complete_link_train(intel_dp);
3ab9c637 2109 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2110}
89b667f8 2111
ecff4f3b
JN		 2112static void g4x_enable_dp(struct intel_encoder *encoder)
2113{
828f5c6e
JN		 2114 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2115
ecff4f3b 2116 intel_enable_dp(encoder);
4be73780 2117 intel_edp_backlight_on(intel_dp);
ab1f90f9 2118}
89b667f8 2119
ab1f90f9
JN		 2120static void vlv_enable_dp(struct intel_encoder *encoder)
2121{
828f5c6e
JN		 2122 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2123
4be73780 2124 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2125}
2126
ecff4f3b 2127static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2128{
2129 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2130 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2131
8ac33ed3
DV		 2132 intel_dp_prepare(encoder);
2133
d41f1efb
DV		 2134 /* Only ilk+ has port A */
2135 if (dport->port == PORT_A) {
2136 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2137 ironlake_edp_pll_on(intel_dp);
d41f1efb 2138 }
ab1f90f9
JN		 2139}
2140
2141static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2142{
2bd2ad64 2143 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2144 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2145 struct drm_device *dev = encoder->base.dev;
89b667f8 2146 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2147 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2148 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 2149 int pipe = intel_crtc->pipe;
bf13e81b 2150 struct edp_power_seq power_seq;
ab1f90f9 2151 u32 val;
a4fc5ed6 2152
ab1f90f9 2153 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2154
ab3c759a 2155 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2156 val = 0;
2157 if (pipe)
2158 val |= (1<<21);
2159 else
2160 val &= ~(1<<21);
2161 val |= 0x001000c4;
ab3c759a
CML		 2162 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2163 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2164 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2165
ab1f90f9
JN		 2166 mutex_unlock(&dev_priv->dpio_lock);
2167
2cac613b
ID		 2168 if (is_edp(intel_dp)) {
2169 /* init power sequencer on this pipe and port */
2170 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2171 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2172 &power_seq);
2173 }
bf13e81b 2174
ab1f90f9
JN		 2175 intel_enable_dp(encoder);
2176
e4607fcf 2177 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2178}
2179
ecff4f3b 2180static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2181{
2182 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2183 struct drm_device *dev = encoder->base.dev;
2184 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2185 struct intel_crtc *intel_crtc =
2186 to_intel_crtc(encoder->base.crtc);
e4607fcf 2187 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2188 int pipe = intel_crtc->pipe;
89b667f8 2189
8ac33ed3
DV		 2190 intel_dp_prepare(encoder);
2191
89b667f8 2192 /* Program Tx lane resets to default */
0980a60f 2193 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2194 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2195 DPIO_PCS_TX_LANE2_RESET |
2196 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2197 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2198 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2199 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2200 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2201 DPIO_PCS_CLK_SOFT_RESET);
2202
2203 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2204 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2205 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2206 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2207 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2208}
2209
e4a1d846
CML		 2210static void chv_pre_enable_dp(struct intel_encoder *encoder)
2211{
2212 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2213 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2214 struct drm_device *dev = encoder->base.dev;
2215 struct drm_i915_private *dev_priv = dev->dev_private;
2216 struct edp_power_seq power_seq;
2217 struct intel_crtc *intel_crtc =
2218 to_intel_crtc(encoder->base.crtc);
2219 enum dpio_channel ch = vlv_dport_to_channel(dport);
2220 int pipe = intel_crtc->pipe;
2221 int data, i;
949c1d43 2222 u32 val;
e4a1d846 2223
e4a1d846 2224 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2225
2226 /* Deassert soft data lane reset*/
97fd4d5c 2227 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2228 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2229 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2230
2231 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2232 val |= CHV_PCS_REQ_SOFTRESET_EN;
2233 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2234
2235 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2236 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2237 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2238
97fd4d5c 2239 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2240 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2241 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2242
2243 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2244 for (i = 0; i < 4; i++) {
2245 /* Set the latency optimal bit */
2246 data = (i == 1) ? 0x0 : 0x6;
2247 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2248 data << DPIO_FRC_LATENCY_SHFIT);
2249
2250 /* Set the upar bit */
2251 data = (i == 1) ? 0x0 : 0x1;
2252 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2253 data << DPIO_UPAR_SHIFT);
2254 }
2255
2256 /* Data lane stagger programming */
2257 /* FIXME: Fix up value only after power analysis */
2258
2259 mutex_unlock(&dev_priv->dpio_lock);
2260
2261 if (is_edp(intel_dp)) {
2262 /* init power sequencer on this pipe and port */
2263 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2264 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2265 &power_seq);
2266 }
2267
2268 intel_enable_dp(encoder);
2269
2270 vlv_wait_port_ready(dev_priv, dport);
2271}
2272
9197c88b
VS		 2273static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2274{
2275 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2276 struct drm_device *dev = encoder->base.dev;
2277 struct drm_i915_private *dev_priv = dev->dev_private;
2278 struct intel_crtc *intel_crtc =
2279 to_intel_crtc(encoder->base.crtc);
2280 enum dpio_channel ch = vlv_dport_to_channel(dport);
2281 enum pipe pipe = intel_crtc->pipe;
2282 u32 val;
2283
625695f8
VS		 2284 intel_dp_prepare(encoder);
2285
9197c88b
VS		 2286 mutex_lock(&dev_priv->dpio_lock);
2287
b9e5ac3c
VS		 2288 /* program left/right clock distribution */
2289 if (pipe != PIPE_B) {
2290 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2291 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2292 if (ch == DPIO_CH0)
2293 val |= CHV_BUFLEFTENA1_FORCE;
2294 if (ch == DPIO_CH1)
2295 val |= CHV_BUFRIGHTENA1_FORCE;
2296 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2297 } else {
2298 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2299 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2300 if (ch == DPIO_CH0)
2301 val |= CHV_BUFLEFTENA2_FORCE;
2302 if (ch == DPIO_CH1)
2303 val |= CHV_BUFRIGHTENA2_FORCE;
2304 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2305 }
2306
9197c88b
VS		 2307 /* program clock channel usage */
2308 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2309 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2310 if (pipe != PIPE_B)
2311 val &= ~CHV_PCS_USEDCLKCHANNEL;
2312 else
2313 val |= CHV_PCS_USEDCLKCHANNEL;
2314 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2315
2316 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2317 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2318 if (pipe != PIPE_B)
2319 val &= ~CHV_PCS_USEDCLKCHANNEL;
2320 else
2321 val |= CHV_PCS_USEDCLKCHANNEL;
2322 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2323
2324 /*
2325 * This a a bit weird since generally CL
2326 * matches the pipe, but here we need to
2327 * pick the CL based on the port.
2328 */
2329 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2330 if (pipe != PIPE_B)
2331 val &= ~CHV_CMN_USEDCLKCHANNEL;
2332 else
2333 val |= CHV_CMN_USEDCLKCHANNEL;
2334 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2335
2336 mutex_unlock(&dev_priv->dpio_lock);
2337}
2338
a4fc5ed6 2339/*
df0c237d
JB		 2340 * Native read with retry for link status and receiver capability reads for
2341 * cases where the sink may still be asleep.
9d1a1031
JN		 2342 *
2343 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2344 * supposed to retry 3 times per the spec.
a4fc5ed6 2345 */
9d1a1031
JN		 2346static ssize_t
2347intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2348 void *buffer, size_t size)
a4fc5ed6 2349{
9d1a1031
JN		 2350 ssize_t ret;
2351 int i;
61da5fab 2352
61da5fab 2353 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2354 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2355 if (ret == size)
2356 return ret;
61da5fab
JB		 2357 msleep(1);
2358 }
a4fc5ed6 2359
9d1a1031 2360 return ret;
a4fc5ed6
KP		 2361}
2362
2363/*
2364 * Fetch AUX CH registers 0x202 - 0x207 which contain
2365 * link status information
2366 */
2367static bool
93f62dad 2368intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2369{
9d1a1031
JN		 2370 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2371 DP_LANE0_1_STATUS,
2372 link_status,
2373 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2374}
2375
1100244e 2376/* These are source-specific values. */
a4fc5ed6 2377static uint8_t
1a2eb460 2378intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2379{
30add22d 2380 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2381 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2382
9576c27f 2383 if (IS_VALLEYVIEW(dev))
e2fa6fba 2384 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2385 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2386 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2387 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2388 return DP_TRAIN_VOLTAGE_SWING_1200;
2389 else
2390 return DP_TRAIN_VOLTAGE_SWING_800;
2391}
2392
2393static uint8_t
2394intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2395{
30add22d 2396 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2397 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2398
9576c27f 2399 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722
PZ		 2400 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2401 case DP_TRAIN_VOLTAGE_SWING_400:
2402 return DP_TRAIN_PRE_EMPHASIS_9_5;
2403 case DP_TRAIN_VOLTAGE_SWING_600:
2404 return DP_TRAIN_PRE_EMPHASIS_6;
2405 case DP_TRAIN_VOLTAGE_SWING_800:
2406 return DP_TRAIN_PRE_EMPHASIS_3_5;
2407 case DP_TRAIN_VOLTAGE_SWING_1200:
2408 default:
2409 return DP_TRAIN_PRE_EMPHASIS_0;
2410 }
e2fa6fba
P		 2411 } else if (IS_VALLEYVIEW(dev)) {
2412 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2413 case DP_TRAIN_VOLTAGE_SWING_400:
2414 return DP_TRAIN_PRE_EMPHASIS_9_5;
2415 case DP_TRAIN_VOLTAGE_SWING_600:
2416 return DP_TRAIN_PRE_EMPHASIS_6;
2417 case DP_TRAIN_VOLTAGE_SWING_800:
2418 return DP_TRAIN_PRE_EMPHASIS_3_5;
2419 case DP_TRAIN_VOLTAGE_SWING_1200:
2420 default:
2421 return DP_TRAIN_PRE_EMPHASIS_0;
2422 }
bc7d38a4 2423 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2424 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2425 case DP_TRAIN_VOLTAGE_SWING_400:
2426 return DP_TRAIN_PRE_EMPHASIS_6;
2427 case DP_TRAIN_VOLTAGE_SWING_600:
2428 case DP_TRAIN_VOLTAGE_SWING_800:
2429 return DP_TRAIN_PRE_EMPHASIS_3_5;
2430 default:
2431 return DP_TRAIN_PRE_EMPHASIS_0;
2432 }
2433 } else {
2434 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2435 case DP_TRAIN_VOLTAGE_SWING_400:
2436 return DP_TRAIN_PRE_EMPHASIS_6;
2437 case DP_TRAIN_VOLTAGE_SWING_600:
2438 return DP_TRAIN_PRE_EMPHASIS_6;
2439 case DP_TRAIN_VOLTAGE_SWING_800:
2440 return DP_TRAIN_PRE_EMPHASIS_3_5;
2441 case DP_TRAIN_VOLTAGE_SWING_1200:
2442 default:
2443 return DP_TRAIN_PRE_EMPHASIS_0;
2444 }
a4fc5ed6
KP		 2445 }
2446}
2447
e2fa6fba
P		 2448static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2449{
2450 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2451 struct drm_i915_private *dev_priv = dev->dev_private;
2452 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2453 struct intel_crtc *intel_crtc =
2454 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2455 unsigned long demph_reg_value, preemph_reg_value,
2456 uniqtranscale_reg_value;
2457 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2458 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2459 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2460
2461 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2462 case DP_TRAIN_PRE_EMPHASIS_0:
2463 preemph_reg_value = 0x0004000;
2464 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2465 case DP_TRAIN_VOLTAGE_SWING_400:
2466 demph_reg_value = 0x2B405555;
2467 uniqtranscale_reg_value = 0x552AB83A;
2468 break;
2469 case DP_TRAIN_VOLTAGE_SWING_600:
2470 demph_reg_value = 0x2B404040;
2471 uniqtranscale_reg_value = 0x5548B83A;
2472 break;
2473 case DP_TRAIN_VOLTAGE_SWING_800:
2474 demph_reg_value = 0x2B245555;
2475 uniqtranscale_reg_value = 0x5560B83A;
2476 break;
2477 case DP_TRAIN_VOLTAGE_SWING_1200:
2478 demph_reg_value = 0x2B405555;
2479 uniqtranscale_reg_value = 0x5598DA3A;
2480 break;
2481 default:
2482 return 0;
2483 }
2484 break;
2485 case DP_TRAIN_PRE_EMPHASIS_3_5:
2486 preemph_reg_value = 0x0002000;
2487 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2488 case DP_TRAIN_VOLTAGE_SWING_400:
2489 demph_reg_value = 0x2B404040;
2490 uniqtranscale_reg_value = 0x5552B83A;
2491 break;
2492 case DP_TRAIN_VOLTAGE_SWING_600:
2493 demph_reg_value = 0x2B404848;
2494 uniqtranscale_reg_value = 0x5580B83A;
2495 break;
2496 case DP_TRAIN_VOLTAGE_SWING_800:
2497 demph_reg_value = 0x2B404040;
2498 uniqtranscale_reg_value = 0x55ADDA3A;
2499 break;
2500 default:
2501 return 0;
2502 }
2503 break;
2504 case DP_TRAIN_PRE_EMPHASIS_6:
2505 preemph_reg_value = 0x0000000;
2506 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2507 case DP_TRAIN_VOLTAGE_SWING_400:
2508 demph_reg_value = 0x2B305555;
2509 uniqtranscale_reg_value = 0x5570B83A;
2510 break;
2511 case DP_TRAIN_VOLTAGE_SWING_600:
2512 demph_reg_value = 0x2B2B4040;
2513 uniqtranscale_reg_value = 0x55ADDA3A;
2514 break;
2515 default:
2516 return 0;
2517 }
2518 break;
2519 case DP_TRAIN_PRE_EMPHASIS_9_5:
2520 preemph_reg_value = 0x0006000;
2521 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2522 case DP_TRAIN_VOLTAGE_SWING_400:
2523 demph_reg_value = 0x1B405555;
2524 uniqtranscale_reg_value = 0x55ADDA3A;
2525 break;
2526 default:
2527 return 0;
2528 }
2529 break;
2530 default:
2531 return 0;
2532 }
2533
0980a60f 2534 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2535 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2536 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2537 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2538 uniqtranscale_reg_value);
ab3c759a
CML		 2539 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2540 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2541 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2542 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2543 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2544
2545 return 0;
2546}
2547
e4a1d846
CML		 2548static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2549{
2550 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2551 struct drm_i915_private *dev_priv = dev->dev_private;
2552 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2553 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2554 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2555 uint8_t train_set = intel_dp->train_set[0];
2556 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2557 enum pipe pipe = intel_crtc->pipe;
2558 int i;
e4a1d846
CML		 2559
2560 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2561 case DP_TRAIN_PRE_EMPHASIS_0:
2562 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2563 case DP_TRAIN_VOLTAGE_SWING_400:
2564 deemph_reg_value = 128;
2565 margin_reg_value = 52;
2566 break;
2567 case DP_TRAIN_VOLTAGE_SWING_600:
2568 deemph_reg_value = 128;
2569 margin_reg_value = 77;
2570 break;
2571 case DP_TRAIN_VOLTAGE_SWING_800:
2572 deemph_reg_value = 128;
2573 margin_reg_value = 102;
2574 break;
2575 case DP_TRAIN_VOLTAGE_SWING_1200:
2576 deemph_reg_value = 128;
2577 margin_reg_value = 154;
2578 /* FIXME extra to set for 1200 */
2579 break;
2580 default:
2581 return 0;
2582 }
2583 break;
2584 case DP_TRAIN_PRE_EMPHASIS_3_5:
2585 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2586 case DP_TRAIN_VOLTAGE_SWING_400:
2587 deemph_reg_value = 85;
2588 margin_reg_value = 78;
2589 break;
2590 case DP_TRAIN_VOLTAGE_SWING_600:
2591 deemph_reg_value = 85;
2592 margin_reg_value = 116;
2593 break;
2594 case DP_TRAIN_VOLTAGE_SWING_800:
2595 deemph_reg_value = 85;
2596 margin_reg_value = 154;
2597 break;
2598 default:
2599 return 0;
2600 }
2601 break;
2602 case DP_TRAIN_PRE_EMPHASIS_6:
2603 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2604 case DP_TRAIN_VOLTAGE_SWING_400:
2605 deemph_reg_value = 64;
2606 margin_reg_value = 104;
2607 break;
2608 case DP_TRAIN_VOLTAGE_SWING_600:
2609 deemph_reg_value = 64;
2610 margin_reg_value = 154;
2611 break;
2612 default:
2613 return 0;
2614 }
2615 break;
2616 case DP_TRAIN_PRE_EMPHASIS_9_5:
2617 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2618 case DP_TRAIN_VOLTAGE_SWING_400:
2619 deemph_reg_value = 43;
2620 margin_reg_value = 154;
2621 break;
2622 default:
2623 return 0;
2624 }
2625 break;
2626 default:
2627 return 0;
2628 }
2629
2630 mutex_lock(&dev_priv->dpio_lock);
2631
2632 /* Clear calc init */
1966e59e
VS		 2633 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2634 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2635 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2636
2637 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2638 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2639 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2640
2641 /* Program swing deemph */
f72df8db
VS		 2642 for (i = 0; i < 4; i++) {
2643 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2644 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2645 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2646 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2647 }
e4a1d846
CML		 2648
2649 /* Program swing margin */
f72df8db
VS		 2650 for (i = 0; i < 4; i++) {
2651 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 2652 val &= ~DPIO_SWING_MARGIN000_MASK;
2653 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 2654 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2655 }
e4a1d846
CML		 2656
2657 /* Disable unique transition scale */
f72df8db
VS		 2658 for (i = 0; i < 4; i++) {
2659 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2660 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2661 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2662 }
e4a1d846
CML		 2663
2664 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2665 == DP_TRAIN_PRE_EMPHASIS_0) &&
2666 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2667 == DP_TRAIN_VOLTAGE_SWING_1200)) {
2668
2669 /*
2670 * The document said it needs to set bit 27 for ch0 and bit 26
2671 * for ch1. Might be a typo in the doc.
2672 * For now, for this unique transition scale selection, set bit
2673 * 27 for ch0 and ch1.
2674 */
f72df8db
VS		 2675 for (i = 0; i < 4; i++) {
2676 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2677 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2678 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2679 }
e4a1d846 2680
f72df8db
VS		 2681 for (i = 0; i < 4; i++) {
2682 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2683 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2684 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2685 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2686 }
e4a1d846
CML		 2687 }
2688
2689 /* Start swing calculation */
1966e59e
VS		 2690 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2691 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2692 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2693
2694 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2695 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2696 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2697
2698 /* LRC Bypass */
2699 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2700 val |= DPIO_LRC_BYPASS;
2701 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2702
2703 mutex_unlock(&dev_priv->dpio_lock);
2704
2705 return 0;
2706}
2707
a4fc5ed6 2708static void
0301b3ac
JN		 2709intel_get_adjust_train(struct intel_dp *intel_dp,
2710 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2711{
2712 uint8_t v = 0;
2713 uint8_t p = 0;
2714 int lane;
1a2eb460
KP		 2715 uint8_t voltage_max;
2716 uint8_t preemph_max;
a4fc5ed6 2717
33a34e4e 2718 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2719 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2720 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2721
2722 if (this_v > v)
2723 v = this_v;
2724 if (this_p > p)
2725 p = this_p;
2726 }
2727
1a2eb460 2728 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2729 if (v >= voltage_max)
2730 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2731
1a2eb460
KP		 2732 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2733 if (p >= preemph_max)
2734 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2735
2736 for (lane = 0; lane < 4; lane++)
33a34e4e 2737 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2738}
2739
2740static uint32_t
f0a3424e 2741intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2742{
3cf2efb1 2743 uint32_t signal_levels = 0;
a4fc5ed6 2744
3cf2efb1 2745 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2746 case DP_TRAIN_VOLTAGE_SWING_400:
2747 default:
2748 signal_levels |= DP_VOLTAGE_0_4;
2749 break;
2750 case DP_TRAIN_VOLTAGE_SWING_600:
2751 signal_levels |= DP_VOLTAGE_0_6;
2752 break;
2753 case DP_TRAIN_VOLTAGE_SWING_800:
2754 signal_levels |= DP_VOLTAGE_0_8;
2755 break;
2756 case DP_TRAIN_VOLTAGE_SWING_1200:
2757 signal_levels |= DP_VOLTAGE_1_2;
2758 break;
2759 }
3cf2efb1 2760 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2761 case DP_TRAIN_PRE_EMPHASIS_0:
2762 default:
2763 signal_levels |= DP_PRE_EMPHASIS_0;
2764 break;
2765 case DP_TRAIN_PRE_EMPHASIS_3_5:
2766 signal_levels |= DP_PRE_EMPHASIS_3_5;
2767 break;
2768 case DP_TRAIN_PRE_EMPHASIS_6:
2769 signal_levels |= DP_PRE_EMPHASIS_6;
2770 break;
2771 case DP_TRAIN_PRE_EMPHASIS_9_5:
2772 signal_levels |= DP_PRE_EMPHASIS_9_5;
2773 break;
2774 }
2775 return signal_levels;
2776}
2777
e3421a18
ZW		 2778/* Gen6's DP voltage swing and pre-emphasis control */
2779static uint32_t
2780intel_gen6_edp_signal_levels(uint8_t train_set)
2781{
3c5a62b5
YL		 2782 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2783 DP_TRAIN_PRE_EMPHASIS_MASK);
2784 switch (signal_levels) {
e3421a18 2785 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2786 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2787 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2788 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2789 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2790 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2791 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2792 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2793 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2794 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2795 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2796 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2797 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2798 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2799 default:
3c5a62b5
YL		 2800 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2801 "0x%x\n", signal_levels);
2802 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2803 }
2804}
2805
1a2eb460
KP		 2806/* Gen7's DP voltage swing and pre-emphasis control */
2807static uint32_t
2808intel_gen7_edp_signal_levels(uint8_t train_set)
2809{
2810 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2811 DP_TRAIN_PRE_EMPHASIS_MASK);
2812 switch (signal_levels) {
2813 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2814 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2815 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2816 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2817 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2818 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2819
2820 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2821 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2822 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2823 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2824
2825 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2826 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2827 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2828 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2829
2830 default:
2831 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2832 "0x%x\n", signal_levels);
2833 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2834 }
2835}
2836
d6c0d722
PZ		 2837/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2838static uint32_t
f0a3424e 2839intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2840{
d6c0d722
PZ		 2841 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2842 DP_TRAIN_PRE_EMPHASIS_MASK);
2843 switch (signal_levels) {
2844 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2845 return DDI_BUF_EMP_400MV_0DB_HSW;
2846 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2847 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2848 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2849 return DDI_BUF_EMP_400MV_6DB_HSW;
2850 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2851 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2852
d6c0d722
PZ		 2853 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2854 return DDI_BUF_EMP_600MV_0DB_HSW;
2855 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2856 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2857 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2858 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2859
d6c0d722
PZ		 2860 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2861 return DDI_BUF_EMP_800MV_0DB_HSW;
2862 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2863 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2864 default:
2865 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2866 "0x%x\n", signal_levels);
2867 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2868 }
a4fc5ed6
KP		 2869}
2870
f0a3424e
PZ		 2871/* Properly updates "DP" with the correct signal levels. */
2872static void
2873intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2874{
2875 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2876 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2877 struct drm_device *dev = intel_dig_port->base.base.dev;
2878 uint32_t signal_levels, mask;
2879 uint8_t train_set = intel_dp->train_set[0];
2880
9576c27f 2881 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
f0a3424e
PZ		 2882 signal_levels = intel_hsw_signal_levels(train_set);
2883 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 2884 } else if (IS_CHERRYVIEW(dev)) {
2885 signal_levels = intel_chv_signal_levels(intel_dp);
2886 mask = 0;
e2fa6fba
P		 2887 } else if (IS_VALLEYVIEW(dev)) {
2888 signal_levels = intel_vlv_signal_levels(intel_dp);
2889 mask = 0;
bc7d38a4 2890 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2891 signal_levels = intel_gen7_edp_signal_levels(train_set);
2892 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2893 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2894 signal_levels = intel_gen6_edp_signal_levels(train_set);
2895 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2896 } else {
2897 signal_levels = intel_gen4_signal_levels(train_set);
2898 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2899 }
2900
2901 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2902
2903 *DP = (*DP & ~mask) | signal_levels;
2904}
2905
a4fc5ed6 2906static bool
ea5b213a 2907intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2908 uint32_t *DP,
58e10eb9 2909 uint8_t dp_train_pat)
a4fc5ed6 2910{
174edf1f
PZ		 2911 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2912 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2913 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2914 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2915 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2916 int ret, len;
a4fc5ed6 2917
22b8bf17 2918 if (HAS_DDI(dev)) {
3ab9c637 2919 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2920
2921 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2922 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2923 else
2924 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2925
2926 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2927 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2928 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2929 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2930
2931 break;
2932 case DP_TRAINING_PATTERN_1:
2933 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2934 break;
2935 case DP_TRAINING_PATTERN_2:
2936 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2937 break;
2938 case DP_TRAINING_PATTERN_3:
2939 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2940 break;
2941 }
174edf1f 2942 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2943
bc7d38a4 2944 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2945 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2946
2947 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2948 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2949 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2950 break;
2951 case DP_TRAINING_PATTERN_1:
70aff66c 2952 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2953 break;
2954 case DP_TRAINING_PATTERN_2:
70aff66c 2955 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2956 break;
2957 case DP_TRAINING_PATTERN_3:
2958 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2959 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2960 break;
2961 }
2962
2963 } else {
aad3d14d
VS		 2964 if (IS_CHERRYVIEW(dev))
2965 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2966 else
2967 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2968
2969 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2970 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2971 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2972 break;
2973 case DP_TRAINING_PATTERN_1:
70aff66c 2974 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2975 break;
2976 case DP_TRAINING_PATTERN_2:
70aff66c 2977 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2978 break;
2979 case DP_TRAINING_PATTERN_3:
aad3d14d
VS		 2980 if (IS_CHERRYVIEW(dev)) {
2981 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2982 } else {
2983 DRM_ERROR("DP training pattern 3 not supported\n");
2984 *DP |= DP_LINK_TRAIN_PAT_2;
2985 }
47ea7542
PZ		 2986 break;
2987 }
2988 }
2989
70aff66c 2990 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2991 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2992
2cdfe6c8
JN		 2993 buf[0] = dp_train_pat;
2994 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2995 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2996 /* don't write DP_TRAINING_LANEx_SET on disable */
2997 len = 1;
2998 } else {
2999 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3000 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3001 len = intel_dp->lane_count + 1;
47ea7542 3002 }
a4fc5ed6 3003
9d1a1031
JN		 3004 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3005 buf, len);
2cdfe6c8
JN		 3006
3007 return ret == len;
a4fc5ed6
KP		 3008}
3009
70aff66c
JN		 3010static bool
3011intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3012 uint8_t dp_train_pat)
3013{
953d22e8 3014 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3015 intel_dp_set_signal_levels(intel_dp, DP);
3016 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3017}
3018
3019static bool
3020intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3021 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3022{
3023 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3024 struct drm_device *dev = intel_dig_port->base.base.dev;
3025 struct drm_i915_private *dev_priv = dev->dev_private;
3026 int ret;
3027
3028 intel_get_adjust_train(intel_dp, link_status);
3029 intel_dp_set_signal_levels(intel_dp, DP);
3030
3031 I915_WRITE(intel_dp->output_reg, *DP);
3032 POSTING_READ(intel_dp->output_reg);
3033
9d1a1031
JN		 3034 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3035 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3036
3037 return ret == intel_dp->lane_count;
3038}
3039
3ab9c637
ID		 3040static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3041{
3042 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3043 struct drm_device *dev = intel_dig_port->base.base.dev;
3044 struct drm_i915_private *dev_priv = dev->dev_private;
3045 enum port port = intel_dig_port->port;
3046 uint32_t val;
3047
3048 if (!HAS_DDI(dev))
3049 return;
3050
3051 val = I915_READ(DP_TP_CTL(port));
3052 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3053 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3054 I915_WRITE(DP_TP_CTL(port), val);
3055
3056 /*
3057 * On PORT_A we can have only eDP in SST mode. There the only reason
3058 * we need to set idle transmission mode is to work around a HW issue
3059 * where we enable the pipe while not in idle link-training mode.
3060 * In this case there is requirement to wait for a minimum number of
3061 * idle patterns to be sent.
3062 */
3063 if (port == PORT_A)
3064 return;
3065
3066 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3067 1))
3068 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3069}
3070
33a34e4e 3071/* Enable corresponding port and start training pattern 1 */
c19b0669 3072void
33a34e4e 3073intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3074{
da63a9f2 3075 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3076 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3077 int i;
3078 uint8_t voltage;
cdb0e95b 3079 int voltage_tries, loop_tries;
ea5b213a 3080 uint32_t DP = intel_dp->DP;
6aba5b6c 3081 uint8_t link_config[2];
a4fc5ed6 3082
affa9354 3083 if (HAS_DDI(dev))
c19b0669
PZ		 3084 intel_ddi_prepare_link_retrain(encoder);
3085
3cf2efb1 3086 /* Write the link configuration data */
6aba5b6c
JN		 3087 link_config[0] = intel_dp->link_bw;
3088 link_config[1] = intel_dp->lane_count;
3089 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3090 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3091 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3092
3093 link_config[0] = 0;
3094 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3095 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3096
3097 DP |= DP_PORT_EN;
1a2eb460 3098
70aff66c
JN		 3099 /* clock recovery */
3100 if (!intel_dp_reset_link_train(intel_dp, &DP,
3101 DP_TRAINING_PATTERN_1 |
3102 DP_LINK_SCRAMBLING_DISABLE)) {
3103 DRM_ERROR("failed to enable link training\n");
3104 return;
3105 }
3106
a4fc5ed6 3107 voltage = 0xff;
cdb0e95b
KP		 3108 voltage_tries = 0;
3109 loop_tries = 0;
a4fc5ed6 3110 for (;;) {
70aff66c 3111 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3112
a7c9655f 3113 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3114 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3115 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3116 break;
93f62dad 3117 }
a4fc5ed6 3118
01916270 3119 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3120 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3121 break;
3122 }
3123
3124 /* Check to see if we've tried the max voltage */
3125 for (i = 0; i < intel_dp->lane_count; i++)
3126 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3127 break;
3b4f819d 3128 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3129 ++loop_tries;
3130 if (loop_tries == 5) {
3def84b3 3131 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3132 break;
3133 }
70aff66c
JN		 3134 intel_dp_reset_link_train(intel_dp, &DP,
3135 DP_TRAINING_PATTERN_1 |
3136 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3137 voltage_tries = 0;
3138 continue;
3139 }
a4fc5ed6 3140
3cf2efb1 3141 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3142 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3143 ++voltage_tries;
b06fbda3 3144 if (voltage_tries == 5) {
3def84b3 3145 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3146 break;
3147 }
3148 } else
3149 voltage_tries = 0;
3150 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3151
70aff66c
JN		 3152 /* Update training set as requested by target */
3153 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3154 DRM_ERROR("failed to update link training\n");
3155 break;
3156 }
a4fc5ed6
KP		 3157 }
3158
33a34e4e
JB		 3159 intel_dp->DP = DP;
3160}
3161
c19b0669 3162void
33a34e4e
JB		 3163intel_dp_complete_link_train(struct intel_dp *intel_dp)
3164{
33a34e4e 3165 bool channel_eq = false;
37f80975 3166 int tries, cr_tries;
33a34e4e 3167 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3168 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3169
3170 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3171 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3172 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3173
a4fc5ed6 3174 /* channel equalization */
70aff66c 3175 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3176 training_pattern |
70aff66c
JN		 3177 DP_LINK_SCRAMBLING_DISABLE)) {
3178 DRM_ERROR("failed to start channel equalization\n");
3179 return;
3180 }
3181
a4fc5ed6 3182 tries = 0;
37f80975 3183 cr_tries = 0;
a4fc5ed6
KP		 3184 channel_eq = false;
3185 for (;;) {
70aff66c 3186 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3187
37f80975
JB		 3188 if (cr_tries > 5) {
3189 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3190 break;
3191 }
3192
a7c9655f 3193 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3194 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3195 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3196 break;
70aff66c 3197 }
a4fc5ed6 3198
37f80975 3199 /* Make sure clock is still ok */
01916270 3200 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3201 intel_dp_start_link_train(intel_dp);
70aff66c 3202 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3203 training_pattern |
70aff66c 3204 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3205 cr_tries++;
3206 continue;
3207 }
3208
1ffdff13 3209 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3210 channel_eq = true;
3211 break;
3212 }
a4fc5ed6 3213
37f80975
JB		 3214 /* Try 5 times, then try clock recovery if that fails */
3215 if (tries > 5) {
3216 intel_dp_link_down(intel_dp);
3217 intel_dp_start_link_train(intel_dp);
70aff66c 3218 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3219 training_pattern |
70aff66c 3220 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3221 tries = 0;
3222 cr_tries++;
3223 continue;
3224 }
a4fc5ed6 3225
70aff66c
JN		 3226 /* Update training set as requested by target */
3227 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3228 DRM_ERROR("failed to update link training\n");
3229 break;
3230 }
3cf2efb1 3231 ++tries;
869184a6 3232 }
3cf2efb1 3233
3ab9c637
ID		 3234 intel_dp_set_idle_link_train(intel_dp);
3235
3236 intel_dp->DP = DP;
3237
d6c0d722 3238 if (channel_eq)
07f42258 3239 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3240
3ab9c637
ID		 3241}
3242
3243void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3244{
70aff66c 3245 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3246 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3247}
3248
3249static void
ea5b213a 3250intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3251{
da63a9f2 3252 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3253 enum port port = intel_dig_port->port;
da63a9f2 3254 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3255 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3256 struct intel_crtc *intel_crtc =
3257 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3258 uint32_t DP = intel_dp->DP;
a4fc5ed6 3259
bc76e320 3260 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3261 return;
3262
0c33d8d7 3263 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3264 return;
3265
28c97730 3266 DRM_DEBUG_KMS("\n");
32f9d658 3267
bc7d38a4 3268 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3269 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3270 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3271 } else {
aad3d14d
VS		 3272 if (IS_CHERRYVIEW(dev))
3273 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3274 else
3275 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3276 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3277 }
fe255d00 3278 POSTING_READ(intel_dp->output_reg);
5eb08b69 3279
493a7081 3280 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3281 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3282 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3283
5bddd17f
EA		 3284 /* Hardware workaround: leaving our transcoder select
3285 * set to transcoder B while it's off will prevent the
3286 * corresponding HDMI output on transcoder A.
3287 *
3288 * Combine this with another hardware workaround:
3289 * transcoder select bit can only be cleared while the
3290 * port is enabled.
3291 */
3292 DP &= ~DP_PIPEB_SELECT;
3293 I915_WRITE(intel_dp->output_reg, DP);
3294
3295 /* Changes to enable or select take place the vblank
3296 * after being written.
3297 */
ff50afe9
DV		 3298 if (WARN_ON(crtc == NULL)) {
3299 /* We should never try to disable a port without a crtc
3300 * attached. For paranoia keep the code around for a
3301 * bit. */
31acbcc4
CW		 3302 POSTING_READ(intel_dp->output_reg);
3303 msleep(50);
3304 } else
ab527efc 3305 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3306 }
3307
832afda6 3308 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3309 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3310 POSTING_READ(intel_dp->output_reg);
f01eca2e 3311 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3312}
3313
26d61aad
KP		 3314static bool
3315intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3316{
a031d709
RV		 3317 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3318 struct drm_device *dev = dig_port->base.base.dev;
3319 struct drm_i915_private *dev_priv = dev->dev_private;
3320
577c7a50
DL		 3321 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3322
9d1a1031
JN		 3323 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3324 sizeof(intel_dp->dpcd)) < 0)
edb39244 3325 return false; /* aux transfer failed */
92fd8fd1 3326
577c7a50
DL		 3327 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3328 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3329 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3330
edb39244
AJ		 3331 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3332 return false; /* DPCD not present */
3333
2293bb5c
SK		 3334 /* Check if the panel supports PSR */
3335 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3336 if (is_edp(intel_dp)) {
9d1a1031
JN		 3337 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3338 intel_dp->psr_dpcd,
3339 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3340 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3341 dev_priv->psr.sink_support = true;
50003939 3342 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3343 }
50003939
JN		 3344 }
3345
06ea66b6
TP		 3346 /* Training Pattern 3 support */
3347 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3348 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3349 intel_dp->use_tps3 = true;
3350 DRM_DEBUG_KMS("Displayport TPS3 supported");
3351 } else
3352 intel_dp->use_tps3 = false;
3353
edb39244
AJ		 3354 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3355 DP_DWN_STRM_PORT_PRESENT))
3356 return true; /* native DP sink */
3357
3358 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3359 return true; /* no per-port downstream info */
3360
9d1a1031
JN		 3361 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3362 intel_dp->downstream_ports,
3363 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3364 return false; /* downstream port status fetch failed */
3365
3366 return true;
92fd8fd1
KP		 3367}
3368
0d198328
AJ		 3369static void
3370intel_dp_probe_oui(struct intel_dp *intel_dp)
3371{
3372 u8 buf[3];
3373
3374 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3375 return;
3376
24f3e092 3377 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3378
9d1a1031 3379 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3380 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3381 buf[0], buf[1], buf[2]);
3382
9d1a1031 3383 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3384 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3385 buf[0], buf[1], buf[2]);
351cfc34 3386
4be73780 3387 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3388}
3389
0e32b39c
DA		 3390static bool
3391intel_dp_probe_mst(struct intel_dp *intel_dp)
3392{
3393 u8 buf[1];
3394
3395 if (!intel_dp->can_mst)
3396 return false;
3397
3398 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3399 return false;
3400
3401 _edp_panel_vdd_on(intel_dp);
3402 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3403 if (buf[0] & DP_MST_CAP) {
3404 DRM_DEBUG_KMS("Sink is MST capable\n");
3405 intel_dp->is_mst = true;
3406 } else {
3407 DRM_DEBUG_KMS("Sink is not MST capable\n");
3408 intel_dp->is_mst = false;
3409 }
3410 }
3411 edp_panel_vdd_off(intel_dp, false);
3412
3413 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3414 return intel_dp->is_mst;
3415}
3416
d2e216d0
RV		 3417int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3418{
3419 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3420 struct drm_device *dev = intel_dig_port->base.base.dev;
3421 struct intel_crtc *intel_crtc =
3422 to_intel_crtc(intel_dig_port->base.base.crtc);
3423 u8 buf[1];
3424
9d1a1031 3425 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3426 return -EAGAIN;
3427
3428 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3429 return -ENOTTY;
3430
9d1a1031
JN		 3431 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3432 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3433 return -EAGAIN;
3434
3435 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3436 intel_wait_for_vblank(dev, intel_crtc->pipe);
3437 intel_wait_for_vblank(dev, intel_crtc->pipe);
3438
9d1a1031 3439 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3440 return -EAGAIN;
3441
9d1a1031 3442 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3443 return 0;
3444}
3445
a60f0e38
JB		 3446static bool
3447intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3448{
9d1a1031
JN		 3449 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3450 DP_DEVICE_SERVICE_IRQ_VECTOR,
3451 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3452}
3453
0e32b39c
DA		 3454static bool
3455intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3456{
3457 int ret;
3458
3459 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3460 DP_SINK_COUNT_ESI,
3461 sink_irq_vector, 14);
3462 if (ret != 14)
3463 return false;
3464
3465 return true;
3466}
3467
a60f0e38
JB		 3468static void
3469intel_dp_handle_test_request(struct intel_dp *intel_dp)
3470{
3471 /* NAK by default */
9d1a1031 3472 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3473}
3474
0e32b39c
DA		 3475static int
3476intel_dp_check_mst_status(struct intel_dp *intel_dp)
3477{
3478 bool bret;
3479
3480 if (intel_dp->is_mst) {
3481 u8 esi[16] = { 0 };
3482 int ret = 0;
3483 int retry;
3484 bool handled;
3485 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3486go_again:
3487 if (bret == true) {
3488
3489 /* check link status - esi[10] = 0x200c */
3490 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3491 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3492 intel_dp_start_link_train(intel_dp);
3493 intel_dp_complete_link_train(intel_dp);
3494 intel_dp_stop_link_train(intel_dp);
3495 }
3496
3497 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3498 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3499
3500 if (handled) {
3501 for (retry = 0; retry < 3; retry++) {
3502 int wret;
3503 wret = drm_dp_dpcd_write(&intel_dp->aux,
3504 DP_SINK_COUNT_ESI+1,
3505 &esi[1], 3);
3506 if (wret == 3) {
3507 break;
3508 }
3509 }
3510
3511 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3512 if (bret == true) {
3513 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3514 goto go_again;
3515 }
3516 } else
3517 ret = 0;
3518
3519 return ret;
3520 } else {
3521 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3522 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3523 intel_dp->is_mst = false;
3524 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3525 /* send a hotplug event */
3526 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3527 }
3528 }
3529 return -EINVAL;
3530}
3531
a4fc5ed6
KP		 3532/*
3533 * According to DP spec
3534 * 5.1.2:
3535 * 1. Read DPCD
3536 * 2. Configure link according to Receiver Capabilities
3537 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3538 * 4. Check link status on receipt of hot-plug interrupt
3539 */
00c09d70 3540void
ea5b213a 3541intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3542{
da63a9f2 3543 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3544 u8 sink_irq_vector;
93f62dad 3545 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3546
6e9f798d 3547 /* FIXME: This access isn't protected by any locks. */
da63a9f2 3548 if (!intel_encoder->connectors_active)
d2b996ac 3549 return;
59cd09e1 3550
da63a9f2 3551 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3552 return;
3553
92fd8fd1 3554 /* Try to read receiver status if the link appears to be up */
93f62dad 3555 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3556 return;
3557 }
3558
92fd8fd1 3559 /* Now read the DPCD to see if it's actually running */
26d61aad 3560 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3561 return;
3562 }
3563
a60f0e38
JB		 3564 /* Try to read the source of the interrupt */
3565 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3566 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3567 /* Clear interrupt source */
9d1a1031
JN		 3568 drm_dp_dpcd_writeb(&intel_dp->aux,
3569 DP_DEVICE_SERVICE_IRQ_VECTOR,
3570 sink_irq_vector);
a60f0e38
JB		 3571
3572 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3573 intel_dp_handle_test_request(intel_dp);
3574 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3575 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3576 }
3577
1ffdff13 3578 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3579 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3580 intel_encoder->base.name);
33a34e4e
JB		 3581 intel_dp_start_link_train(intel_dp);
3582 intel_dp_complete_link_train(intel_dp);
3ab9c637 3583 intel_dp_stop_link_train(intel_dp);
33a34e4e 3584 }
a4fc5ed6 3585}
a4fc5ed6 3586
caf9ab24 3587/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3588static enum drm_connector_status
26d61aad 3589intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3590{
caf9ab24 3591 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3592 uint8_t type;
3593
3594 if (!intel_dp_get_dpcd(intel_dp))
3595 return connector_status_disconnected;
3596
3597 /* if there's no downstream port, we're done */
3598 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3599 return connector_status_connected;
caf9ab24
AJ		 3600
3601 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3602 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3603 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3604 uint8_t reg;
9d1a1031
JN		 3605
3606 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3607 &reg, 1) < 0)
caf9ab24 3608 return connector_status_unknown;
9d1a1031 3609
23235177
AJ		 3610 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3611 : connector_status_disconnected;
caf9ab24
AJ		 3612 }
3613
3614 /* If no HPD, poke DDC gently */
0b99836f 3615 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3616 return connector_status_connected;
caf9ab24
AJ		 3617
3618 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3619 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3620 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3621 if (type == DP_DS_PORT_TYPE_VGA ||
3622 type == DP_DS_PORT_TYPE_NON_EDID)
3623 return connector_status_unknown;
3624 } else {
3625 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3626 DP_DWN_STRM_PORT_TYPE_MASK;
3627 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3628 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3629 return connector_status_unknown;
3630 }
caf9ab24
AJ		 3631
3632 /* Anything else is out of spec, warn and ignore */
3633 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3634 return connector_status_disconnected;
71ba9000
AJ		 3635}
3636
5eb08b69 3637static enum drm_connector_status
a9756bb5 3638ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3639{
30add22d 3640 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3641 struct drm_i915_private *dev_priv = dev->dev_private;
3642 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3643 enum drm_connector_status status;
3644
fe16d949
CW		 3645 /* Can't disconnect eDP, but you can close the lid... */
3646 if (is_edp(intel_dp)) {
30add22d 3647 status = intel_panel_detect(dev);
fe16d949
CW		 3648 if (status == connector_status_unknown)
3649 status = connector_status_connected;
3650 return status;
3651 }
01cb9ea6 3652
1b469639
DL		 3653 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3654 return connector_status_disconnected;
3655
26d61aad 3656 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3657}
3658
a4fc5ed6 3659static enum drm_connector_status
a9756bb5 3660g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3661{
30add22d 3662 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3663 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3664 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3665 uint32_t bit;
5eb08b69 3666
35aad75f
JB		 3667 /* Can't disconnect eDP, but you can close the lid... */
3668 if (is_edp(intel_dp)) {
3669 enum drm_connector_status status;
3670
3671 status = intel_panel_detect(dev);
3672 if (status == connector_status_unknown)
3673 status = connector_status_connected;
3674 return status;
3675 }
3676
232a6ee9
TP		 3677 if (IS_VALLEYVIEW(dev)) {
3678 switch (intel_dig_port->port) {
3679 case PORT_B:
3680 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3681 break;
3682 case PORT_C:
3683 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3684 break;
3685 case PORT_D:
3686 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3687 break;
3688 default:
3689 return connector_status_unknown;
3690 }
3691 } else {
3692 switch (intel_dig_port->port) {
3693 case PORT_B:
3694 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3695 break;
3696 case PORT_C:
3697 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3698 break;
3699 case PORT_D:
3700 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3701 break;
3702 default:
3703 return connector_status_unknown;
3704 }
a4fc5ed6
KP		 3705 }
3706
10f76a38 3707 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3708 return connector_status_disconnected;
3709
26d61aad 3710 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3711}
3712
8c241fef
KP		 3713static struct edid *
3714intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3715{
9cd300e0 3716 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3717
9cd300e0
JN		 3718 /* use cached edid if we have one */
3719 if (intel_connector->edid) {
9cd300e0
JN		 3720 /* invalid edid */
3721 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3722 return NULL;
3723
55e9edeb 3724 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3725 }
8c241fef 3726
9cd300e0 3727 return drm_get_edid(connector, adapter);
8c241fef
KP		 3728}
3729
3730static int
3731intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3732{
9cd300e0 3733 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3734
9cd300e0
JN		 3735 /* use cached edid if we have one */
3736 if (intel_connector->edid) {
3737 /* invalid edid */
3738 if (IS_ERR(intel_connector->edid))
3739 return 0;
3740
3741 return intel_connector_update_modes(connector,
3742 intel_connector->edid);
d6f24d0f
JB		 3743 }
3744
9cd300e0 3745 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3746}
3747
a9756bb5
ZW		 3748static enum drm_connector_status
3749intel_dp_detect(struct drm_connector *connector, bool force)
3750{
3751 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3752 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3753 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3754 struct drm_device *dev = connector->dev;
c8c8fb33 3755 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3756 enum drm_connector_status status;
671dedd2 3757 enum intel_display_power_domain power_domain;
a9756bb5 3758 struct edid *edid = NULL;
0e32b39c 3759 bool ret;
a9756bb5 3760
671dedd2
ID		 3761 power_domain = intel_display_port_power_domain(intel_encoder);
3762 intel_display_power_get(dev_priv, power_domain);
3763
164c8598 3764 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 3765 connector->base.id, connector->name);
164c8598 3766
0e32b39c
DA		 3767 if (intel_dp->is_mst) {
3768 /* MST devices are disconnected from a monitor POV */
3769 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3770 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3771 status = connector_status_disconnected;
3772 goto out;
3773 }
3774
a9756bb5
ZW		 3775 intel_dp->has_audio = false;
3776
3777 if (HAS_PCH_SPLIT(dev))
3778 status = ironlake_dp_detect(intel_dp);
3779 else
3780 status = g4x_dp_detect(intel_dp);
1b9be9d0 3781
a9756bb5 3782 if (status != connector_status_connected)
c8c8fb33 3783 goto out;
a9756bb5 3784
0d198328
AJ		 3785 intel_dp_probe_oui(intel_dp);
3786
0e32b39c
DA		 3787 ret = intel_dp_probe_mst(intel_dp);
3788 if (ret) {
3789 /* if we are in MST mode then this connector
3790 won't appear connected or have anything with EDID on it */
3791 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3792 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3793 status = connector_status_disconnected;
3794 goto out;
3795 }
3796
c3e5f67b
DV		 3797 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3798 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3799 } else {
0b99836f 3800 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3801 if (edid) {
3802 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3803 kfree(edid);
3804 }
a9756bb5
ZW		 3805 }
3806
d63885da
PZ		 3807 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3808 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3809 status = connector_status_connected;
3810
3811out:
671dedd2 3812 intel_display_power_put(dev_priv, power_domain);
c8c8fb33 3813 return status;
a4fc5ed6
KP		 3814}
3815
3816static int intel_dp_get_modes(struct drm_connector *connector)
3817{
df0e9248 3818 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3819 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3820 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3821 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3822 struct drm_device *dev = connector->dev;
671dedd2
ID		 3823 struct drm_i915_private *dev_priv = dev->dev_private;
3824 enum intel_display_power_domain power_domain;
32f9d658 3825 int ret;
a4fc5ed6
KP		 3826
3827 /* We should parse the EDID data and find out if it has an audio sink
3828 */
3829
671dedd2
ID		 3830 power_domain = intel_display_port_power_domain(intel_encoder);
3831 intel_display_power_get(dev_priv, power_domain);
3832
0b99836f 3833 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3834 intel_display_power_put(dev_priv, power_domain);
f8779fda 3835 if (ret)
32f9d658
ZW		 3836 return ret;
3837
f8779fda 3838 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3839 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3840 struct drm_display_mode *mode;
dd06f90e
JN		 3841 mode = drm_mode_duplicate(dev,
3842 intel_connector->panel.fixed_mode);
f8779fda 3843 if (mode) {
32f9d658
ZW		 3844 drm_mode_probed_add(connector, mode);
3845 return 1;
3846 }
3847 }
3848 return 0;
a4fc5ed6
KP		 3849}
3850
1aad7ac0
CW		 3851static bool
3852intel_dp_detect_audio(struct drm_connector *connector)
3853{
3854 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3855 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3856 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3857 struct drm_device *dev = connector->dev;
3858 struct drm_i915_private *dev_priv = dev->dev_private;
3859 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3860 struct edid *edid;
3861 bool has_audio = false;
3862
671dedd2
ID		 3863 power_domain = intel_display_port_power_domain(intel_encoder);
3864 intel_display_power_get(dev_priv, power_domain);
3865
0b99836f 3866 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3867 if (edid) {
3868 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3869 kfree(edid);
3870 }
3871
671dedd2
ID		 3872 intel_display_power_put(dev_priv, power_domain);
3873
1aad7ac0
CW		 3874 return has_audio;
3875}
3876
f684960e
CW		 3877static int
3878intel_dp_set_property(struct drm_connector *connector,
3879 struct drm_property *property,
3880 uint64_t val)
3881{
e953fd7b 3882 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3883 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3884 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3885 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3886 int ret;
3887
662595df 3888 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3889 if (ret)
3890 return ret;
3891
3f43c48d 3892 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3893 int i = val;
3894 bool has_audio;
3895
3896 if (i == intel_dp->force_audio)
f684960e
CW		 3897 return 0;
3898
1aad7ac0 3899 intel_dp->force_audio = i;
f684960e 3900
c3e5f67b 3901 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3902 has_audio = intel_dp_detect_audio(connector);
3903 else
c3e5f67b 3904 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3905
3906 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3907 return 0;
3908
1aad7ac0 3909 intel_dp->has_audio = has_audio;
f684960e
CW		 3910 goto done;
3911 }
3912
e953fd7b 3913 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3914 bool old_auto = intel_dp->color_range_auto;
3915 uint32_t old_range = intel_dp->color_range;
3916
55bc60db
VS		 3917 switch (val) {
3918 case INTEL_BROADCAST_RGB_AUTO:
3919 intel_dp->color_range_auto = true;
3920 break;
3921 case INTEL_BROADCAST_RGB_FULL:
3922 intel_dp->color_range_auto = false;
3923 intel_dp->color_range = 0;
3924 break;
3925 case INTEL_BROADCAST_RGB_LIMITED:
3926 intel_dp->color_range_auto = false;
3927 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3928 break;
3929 default:
3930 return -EINVAL;
3931 }
ae4edb80
DV		 3932
3933 if (old_auto == intel_dp->color_range_auto &&
3934 old_range == intel_dp->color_range)
3935 return 0;
3936
e953fd7b
CW		 3937 goto done;
3938 }
3939
53b41837
YN		 3940 if (is_edp(intel_dp) &&
3941 property == connector->dev->mode_config.scaling_mode_property) {
3942 if (val == DRM_MODE_SCALE_NONE) {
3943 DRM_DEBUG_KMS("no scaling not supported\n");
3944 return -EINVAL;
3945 }
3946
3947 if (intel_connector->panel.fitting_mode == val) {
3948 /* the eDP scaling property is not changed */
3949 return 0;
3950 }
3951 intel_connector->panel.fitting_mode = val;
3952
3953 goto done;
3954 }
3955
f684960e
CW		 3956 return -EINVAL;
3957
3958done:
c0c36b94
CW		 3959 if (intel_encoder->base.crtc)
3960 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3961
3962 return 0;
3963}
3964
a4fc5ed6 3965static void
73845adf 3966intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3967{
1d508706 3968 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3969
9cd300e0
JN		 3970 if (!IS_ERR_OR_NULL(intel_connector->edid))
3971 kfree(intel_connector->edid);
3972
acd8db10
PZ		 3973 /* Can't call is_edp() since the encoder may have been destroyed
3974 * already. */
3975 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3976 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3977
a4fc5ed6 3978 drm_connector_cleanup(connector);
55f78c43 3979 kfree(connector);
a4fc5ed6
KP		 3980}
3981
00c09d70 3982void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3983{
da63a9f2
PZ		 3984 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3985 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3986 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 3987
4f71d0cb 3988 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 3989 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 3990 drm_encoder_cleanup(encoder);
bd943159
KP		 3991 if (is_edp(intel_dp)) {
3992 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 3993 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 3994 edp_panel_vdd_off_sync(intel_dp);
51fd371b 3995 drm_modeset_unlock(&dev->mode_config.connection_mutex);
01527b31
CT		 3996 if (intel_dp->edp_notifier.notifier_call) {
3997 unregister_reboot_notifier(&intel_dp->edp_notifier);
3998 intel_dp->edp_notifier.notifier_call = NULL;
3999 }
bd943159 4000 }
da63a9f2 4001 kfree(intel_dig_port);
24d05927
DV		 4002}
4003
6d93c0c4
ID		 4004static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4005{
4006 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4007}
4008
a4fc5ed6 4009static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4010 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 4011 .detect = intel_dp_detect,
4012 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4013 .set_property = intel_dp_set_property,
73845adf 4014 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4015};
4016
4017static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4018 .get_modes = intel_dp_get_modes,
4019 .mode_valid = intel_dp_mode_valid,
df0e9248 4020 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4021};
4022
a4fc5ed6 4023static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4024 .reset = intel_dp_encoder_reset,
24d05927 4025 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4026};
4027
0e32b39c 4028void
21d40d37 4029intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4030{
0e32b39c 4031 return;
c8110e52 4032}
6207937d 4033
13cf5504
DA		 4034bool
4035intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4036{
4037 struct intel_dp *intel_dp = &intel_dig_port->dp;
0e32b39c
DA		 4038 struct drm_device *dev = intel_dig_port->base.base.dev;
4039 struct drm_i915_private *dev_priv = dev->dev_private;
4040 int ret;
4041 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4042 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4043
0e32b39c
DA		 4044 DRM_DEBUG_KMS("got hpd irq on port %d - %s\n", intel_dig_port->port,
4045 long_hpd ? "long" : "short");
13cf5504 4046
0e32b39c
DA		 4047 if (long_hpd) {
4048 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4049 goto mst_fail;
4050
4051 if (!intel_dp_get_dpcd(intel_dp)) {
4052 goto mst_fail;
4053 }
4054
4055 intel_dp_probe_oui(intel_dp);
4056
4057 if (!intel_dp_probe_mst(intel_dp))
4058 goto mst_fail;
4059
4060 } else {
4061 if (intel_dp->is_mst) {
4062 ret = intel_dp_check_mst_status(intel_dp);
4063 if (ret == -EINVAL)
4064 goto mst_fail;
4065 }
4066
4067 if (!intel_dp->is_mst) {
4068 /*
4069 * we'll check the link status via the normal hot plug path later -
4070 * but for short hpds we should check it now
4071 */
4072 intel_dp_check_link_status(intel_dp);
4073 }
4074 }
13cf5504 4075 return false;
0e32b39c
DA		 4076mst_fail:
4077 /* if we were in MST mode, and device is not there get out of MST mode */
4078 if (intel_dp->is_mst) {
4079 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4080 intel_dp->is_mst = false;
4081 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4082 }
4083 return true;
13cf5504
DA		 4084}
4085
e3421a18
ZW		 4086/* Return which DP Port should be selected for Transcoder DP control */
4087int
0206e353 4088intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4089{
4090 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4091 struct intel_encoder *intel_encoder;
4092 struct intel_dp *intel_dp;
e3421a18 4093
fa90ecef
PZ		 4094 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4095 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4096
fa90ecef
PZ		 4097 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4098 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4099 return intel_dp->output_reg;
e3421a18 4100 }
ea5b213a 4101
e3421a18
ZW		 4102 return -1;
4103}
4104
36e83a18 4105/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4106bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4107{
4108 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4109 union child_device_config *p_child;
36e83a18 4110 int i;
5d8a7752
VS		 4111 static const short port_mapping[] = {
4112 [PORT_B] = PORT_IDPB,
4113 [PORT_C] = PORT_IDPC,
4114 [PORT_D] = PORT_IDPD,
4115 };
36e83a18 4116
3b32a35b
VS		 4117 if (port == PORT_A)
4118 return true;
4119
41aa3448 4120 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4121 return false;
4122
41aa3448
RV		 4123 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4124 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4125
5d8a7752 4126 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4127 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4128 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4129 return true;
4130 }
4131 return false;
4132}
4133
0e32b39c 4134void
f684960e
CW		 4135intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4136{
53b41837
YN		 4137 struct intel_connector *intel_connector = to_intel_connector(connector);
4138
3f43c48d 4139 intel_attach_force_audio_property(connector);
e953fd7b 4140 intel_attach_broadcast_rgb_property(connector);
55bc60db 4141 intel_dp->color_range_auto = true;
53b41837
YN		 4142
4143 if (is_edp(intel_dp)) {
4144 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4145 drm_object_attach_property(
4146 &connector->base,
53b41837 4147 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4148 DRM_MODE_SCALE_ASPECT);
4149 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4150 }
f684960e
CW		 4151}
4152
dada1a9f
ID		 4153static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4154{
4155 intel_dp->last_power_cycle = jiffies;
4156 intel_dp->last_power_on = jiffies;
4157 intel_dp->last_backlight_off = jiffies;
4158}
4159
67a54566
DV		 4160static void
4161intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 4162 struct intel_dp *intel_dp,
4163 struct edp_power_seq *out)
67a54566
DV		 4164{
4165 struct drm_i915_private *dev_priv = dev->dev_private;
4166 struct edp_power_seq cur, vbt, spec, final;
4167 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4168 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 4169
4170 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4171 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4172 pp_on_reg = PCH_PP_ON_DELAYS;
4173 pp_off_reg = PCH_PP_OFF_DELAYS;
4174 pp_div_reg = PCH_PP_DIVISOR;
4175 } else {
bf13e81b
JN		 4176 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4177
4178 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4179 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4180 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4181 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4182 }
67a54566
DV		 4183
4184 /* Workaround: Need to write PP_CONTROL with the unlock key as
4185 * the very first thing. */
453c5420 4186 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4187 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4188
453c5420
JB		 4189 pp_on = I915_READ(pp_on_reg);
4190 pp_off = I915_READ(pp_off_reg);
4191 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4192
4193 /* Pull timing values out of registers */
4194 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4195 PANEL_POWER_UP_DELAY_SHIFT;
4196
4197 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4198 PANEL_LIGHT_ON_DELAY_SHIFT;
4199
4200 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4201 PANEL_LIGHT_OFF_DELAY_SHIFT;
4202
4203 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4204 PANEL_POWER_DOWN_DELAY_SHIFT;
4205
4206 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4207 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4208
4209 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4210 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4211
41aa3448 4212 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4213
4214 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4215 * our hw here, which are all in 100usec. */
4216 spec.t1_t3 = 210 * 10;
4217 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4218 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4219 spec.t10 = 500 * 10;
4220 /* This one is special and actually in units of 100ms, but zero
4221 * based in the hw (so we need to add 100 ms). But the sw vbt
4222 * table multiplies it with 1000 to make it in units of 100usec,
4223 * too. */
4224 spec.t11_t12 = (510 + 100) * 10;
4225
4226 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4227 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4228
4229 /* Use the max of the register settings and vbt. If both are
4230 * unset, fall back to the spec limits. */
4231#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4232 spec.field : \
4233 max(cur.field, vbt.field))
4234 assign_final(t1_t3);
4235 assign_final(t8);
4236 assign_final(t9);
4237 assign_final(t10);
4238 assign_final(t11_t12);
4239#undef assign_final
4240
4241#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4242 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4243 intel_dp->backlight_on_delay = get_delay(t8);
4244 intel_dp->backlight_off_delay = get_delay(t9);
4245 intel_dp->panel_power_down_delay = get_delay(t10);
4246 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4247#undef get_delay
4248
f30d26e4
JN		 4249 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4250 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4251 intel_dp->panel_power_cycle_delay);
4252
4253 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4254 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4255
4256 if (out)
4257 *out = final;
4258}
4259
4260static void
4261intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4262 struct intel_dp *intel_dp,
4263 struct edp_power_seq *seq)
4264{
4265 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4266 u32 pp_on, pp_off, pp_div, port_sel = 0;
4267 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4268 int pp_on_reg, pp_off_reg, pp_div_reg;
4269
4270 if (HAS_PCH_SPLIT(dev)) {
4271 pp_on_reg = PCH_PP_ON_DELAYS;
4272 pp_off_reg = PCH_PP_OFF_DELAYS;
4273 pp_div_reg = PCH_PP_DIVISOR;
4274 } else {
bf13e81b
JN		 4275 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4276
4277 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4278 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4279 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4280 }
4281
b2f19d1a
PZ		 4282 /*
4283 * And finally store the new values in the power sequencer. The
4284 * backlight delays are set to 1 because we do manual waits on them. For
4285 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4286 * we'll end up waiting for the backlight off delay twice: once when we
4287 * do the manual sleep, and once when we disable the panel and wait for
4288 * the PP_STATUS bit to become zero.
4289 */
f30d26e4 4290 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4291 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4292 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4293 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4294 /* Compute the divisor for the pp clock, simply match the Bspec
4295 * formula. */
453c5420 4296 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4297 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4298 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4299
4300 /* Haswell doesn't have any port selection bits for the panel
4301 * power sequencer any more. */
bc7d38a4 4302 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 4303 if (dp_to_dig_port(intel_dp)->port == PORT_B)
4304 port_sel = PANEL_PORT_SELECT_DPB_VLV;
4305 else
4306 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 4307 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4308 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 4309 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4310 else
a24c144c 4311 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4312 }
4313
453c5420
JB		 4314 pp_on |= port_sel;
4315
4316 I915_WRITE(pp_on_reg, pp_on);
4317 I915_WRITE(pp_off_reg, pp_off);
4318 I915_WRITE(pp_div_reg, pp_div);
67a54566 4319
67a54566 4320 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4321 I915_READ(pp_on_reg),
4322 I915_READ(pp_off_reg),
4323 I915_READ(pp_div_reg));
f684960e
CW		 4324}
4325
439d7ac0
PB		 4326void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4327{
4328 struct drm_i915_private *dev_priv = dev->dev_private;
4329 struct intel_encoder *encoder;
4330 struct intel_dp *intel_dp = NULL;
4331 struct intel_crtc_config *config = NULL;
4332 struct intel_crtc *intel_crtc = NULL;
4333 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4334 u32 reg, val;
4335 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4336
4337 if (refresh_rate <= 0) {
4338 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4339 return;
4340 }
4341
4342 if (intel_connector == NULL) {
4343 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4344 return;
4345 }
4346
1fcc9d1c
DV		 4347 /*
4348 * FIXME: This needs proper synchronization with psr state. But really
4349 * hard to tell without seeing the user of this function of this code.
4350 * Check locking and ordering once that lands.
4351 */
439d7ac0
PB		 4352 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4353 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4354 return;
4355 }
4356
4357 encoder = intel_attached_encoder(&intel_connector->base);
4358 intel_dp = enc_to_intel_dp(&encoder->base);
4359 intel_crtc = encoder->new_crtc;
4360
4361 if (!intel_crtc) {
4362 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4363 return;
4364 }
4365
4366 config = &intel_crtc->config;
4367
4368 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4369 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4370 return;
4371 }
4372
4373 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4374 index = DRRS_LOW_RR;
4375
4376 if (index == intel_dp->drrs_state.refresh_rate_type) {
4377 DRM_DEBUG_KMS(
4378 "DRRS requested for previously set RR...ignoring\n");
4379 return;
4380 }
4381
4382 if (!intel_crtc->active) {
4383 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4384 return;
4385 }
4386
4387 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4388 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4389 val = I915_READ(reg);
4390 if (index > DRRS_HIGH_RR) {
4391 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4392 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4393 } else {
4394 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4395 }
4396 I915_WRITE(reg, val);
4397 }
4398
4399 /*
4400 * mutex taken to ensure that there is no race between differnt
4401 * drrs calls trying to update refresh rate. This scenario may occur
4402 * in future when idleness detection based DRRS in kernel and
4403 * possible calls from user space to set differnt RR are made.
4404 */
4405
4406 mutex_lock(&intel_dp->drrs_state.mutex);
4407
4408 intel_dp->drrs_state.refresh_rate_type = index;
4409
4410 mutex_unlock(&intel_dp->drrs_state.mutex);
4411
4412 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4413}
4414
4f9db5b5
PB		 4415static struct drm_display_mode *
4416intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4417 struct intel_connector *intel_connector,
4418 struct drm_display_mode *fixed_mode)
4419{
4420 struct drm_connector *connector = &intel_connector->base;
4421 struct intel_dp *intel_dp = &intel_dig_port->dp;
4422 struct drm_device *dev = intel_dig_port->base.base.dev;
4423 struct drm_i915_private *dev_priv = dev->dev_private;
4424 struct drm_display_mode *downclock_mode = NULL;
4425
4426 if (INTEL_INFO(dev)->gen <= 6) {
4427 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4428 return NULL;
4429 }
4430
4431 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4432 DRM_INFO("VBT doesn't support DRRS\n");
4433 return NULL;
4434 }
4435
4436 downclock_mode = intel_find_panel_downclock
4437 (dev, fixed_mode, connector);
4438
4439 if (!downclock_mode) {
4440 DRM_INFO("DRRS not supported\n");
4441 return NULL;
4442 }
4443
439d7ac0
PB		 4444 dev_priv->drrs.connector = intel_connector;
4445
4446 mutex_init(&intel_dp->drrs_state.mutex);
4447
4f9db5b5
PB		 4448 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4449
4450 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4451 DRM_INFO("seamless DRRS supported for eDP panel.\n");
4452 return downclock_mode;
4453}
4454
aba86890
ID		 4455void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4456{
4457 struct drm_device *dev = intel_encoder->base.dev;
4458 struct drm_i915_private *dev_priv = dev->dev_private;
4459 struct intel_dp *intel_dp;
4460 enum intel_display_power_domain power_domain;
4461
4462 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4463 return;
4464
4465 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4466 if (!edp_have_panel_vdd(intel_dp))
4467 return;
4468 /*
4469 * The VDD bit needs a power domain reference, so if the bit is
4470 * already enabled when we boot or resume, grab this reference and
4471 * schedule a vdd off, so we don't hold on to the reference
4472 * indefinitely.
4473 */
4474 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4475 power_domain = intel_display_port_power_domain(intel_encoder);
4476 intel_display_power_get(dev_priv, power_domain);
4477
4478 edp_panel_vdd_schedule_off(intel_dp);
4479}
4480
ed92f0b2 4481static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4482 struct intel_connector *intel_connector,
4483 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4484{
4485 struct drm_connector *connector = &intel_connector->base;
4486 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4487 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4488 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4489 struct drm_i915_private *dev_priv = dev->dev_private;
4490 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4491 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4492 bool has_dpcd;
4493 struct drm_display_mode *scan;
4494 struct edid *edid;
4495
4f9db5b5
PB		 4496 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4497
ed92f0b2
PZ		 4498 if (!is_edp(intel_dp))
4499 return true;
4500
aba86890 4501 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 4502
ed92f0b2 4503 /* Cache DPCD and EDID for edp. */
24f3e092 4504 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4505 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 4506 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4507
4508 if (has_dpcd) {
4509 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4510 dev_priv->no_aux_handshake =
4511 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4512 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4513 } else {
4514 /* if this fails, presume the device is a ghost */
4515 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4516 return false;
4517 }
4518
4519 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 4520 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 4521
060c8778 4522 mutex_lock(&dev->mode_config.mutex);
0b99836f 4523 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4524 if (edid) {
4525 if (drm_add_edid_modes(connector, edid)) {
4526 drm_mode_connector_update_edid_property(connector,
4527 edid);
4528 drm_edid_to_eld(connector, edid);
4529 } else {
4530 kfree(edid);
4531 edid = ERR_PTR(-EINVAL);
4532 }
4533 } else {
4534 edid = ERR_PTR(-ENOENT);
4535 }
4536 intel_connector->edid = edid;
4537
4538 /* prefer fixed mode from EDID if available */
4539 list_for_each_entry(scan, &connector->probed_modes, head) {
4540 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4541 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4542 downclock_mode = intel_dp_drrs_init(
4543 intel_dig_port,
4544 intel_connector, fixed_mode);
ed92f0b2
PZ		 4545 break;
4546 }
4547 }
4548
4549 /* fallback to VBT if available for eDP */
4550 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4551 fixed_mode = drm_mode_duplicate(dev,
4552 dev_priv->vbt.lfp_lvds_vbt_mode);
4553 if (fixed_mode)
4554 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4555 }
060c8778 4556 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4557
01527b31
CT		 4558 if (IS_VALLEYVIEW(dev)) {
4559 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4560 register_reboot_notifier(&intel_dp->edp_notifier);
4561 }
4562
4f9db5b5 4563 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
ed92f0b2
PZ		 4564 intel_panel_setup_backlight(connector);
4565
4566 return true;
4567}
4568
16c25533 4569bool
f0fec3f2
PZ		 4570intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4571 struct intel_connector *intel_connector)
a4fc5ed6 4572{
f0fec3f2
PZ		 4573 struct drm_connector *connector = &intel_connector->base;
4574 struct intel_dp *intel_dp = &intel_dig_port->dp;
4575 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4576 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4577 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4578 enum port port = intel_dig_port->port;
0095e6dc 4579 struct edp_power_seq power_seq = { 0 };
0b99836f 4580 int type;
a4fc5ed6 4581
ec5b01dd
DL		 4582 /* intel_dp vfuncs */
4583 if (IS_VALLEYVIEW(dev))
4584 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4585 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4586 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4587 else if (HAS_PCH_SPLIT(dev))
4588 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4589 else
4590 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4591
153b1100
DL		 4592 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4593
0767935e
DV		 4594 /* Preserve the current hw state. */
4595 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 4596 intel_dp->attached_connector = intel_connector;
3d3dc149 4597
3b32a35b 4598 if (intel_dp_is_edp(dev, port))
b329530c 4599 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 4600 else
4601 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 4602
f7d24902
ID		 4603 /*
4604 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4605 * for DP the encoder type can be set by the caller to
4606 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4607 */
4608 if (type == DRM_MODE_CONNECTOR_eDP)
4609 intel_encoder->type = INTEL_OUTPUT_EDP;
4610
e7281eab
ID		 4611 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4612 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4613 port_name(port));
4614
b329530c 4615 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 4616 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4617
a4fc5ed6
KP		 4618 connector->interlace_allowed = true;
4619 connector->doublescan_allowed = 0;
4620
f0fec3f2 4621 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 4622 edp_panel_vdd_work);
a4fc5ed6 4623
df0e9248 4624 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 4625 drm_connector_register(connector);
a4fc5ed6 4626
affa9354 4627 if (HAS_DDI(dev))
bcbc889b
PZ		 4628 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4629 else
4630 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 4631 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 4632
0b99836f 4633 /* Set up the hotplug pin. */
ab9d7c30
PZ		 4634 switch (port) {
4635 case PORT_A:
1d843f9d 4636 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 4637 break;
4638 case PORT_B:
1d843f9d 4639 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 4640 break;
4641 case PORT_C:
1d843f9d 4642 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 4643 break;
4644 case PORT_D:
1d843f9d 4645 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 4646 break;
4647 default:
ad1c0b19 4648 BUG();
5eb08b69
ZW		 4649 }
4650
dada1a9f
ID		 4651 if (is_edp(intel_dp)) {
4652 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 4653 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 4654 }
0095e6dc 4655
9d1a1031 4656 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 4657
0e32b39c
DA		 4658 /* init MST on ports that can support it */
4659 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4660 if (port == PORT_B || port == PORT_C || port == PORT_D) {
4661 intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id);
4662 }
4663 }
4664
0095e6dc 4665 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 4666 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 4667 if (is_edp(intel_dp)) {
4668 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 4669 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 4670 edp_panel_vdd_off_sync(intel_dp);
51fd371b 4671 drm_modeset_unlock(&dev->mode_config.connection_mutex);
15b1d171 4672 }
34ea3d38 4673 drm_connector_unregister(connector);
b2f246a8 4674 drm_connector_cleanup(connector);
16c25533 4675 return false;
b2f246a8 4676 }
32f9d658 4677
f684960e
CW		 4678 intel_dp_add_properties(intel_dp, connector);
4679
a4fc5ed6
KP		 4680 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4681 * 0xd. Failure to do so will result in spurious interrupts being
4682 * generated on the port when a cable is not attached.
4683 */
4684 if (IS_G4X(dev) && !IS_GM45(dev)) {
4685 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4686 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4687 }
16c25533
PZ		 4688
4689 return true;
a4fc5ed6 4690}
f0fec3f2
PZ		 4691
4692void
4693intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4694{
13cf5504 4695 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 4696 struct intel_digital_port *intel_dig_port;
4697 struct intel_encoder *intel_encoder;
4698 struct drm_encoder *encoder;
4699 struct intel_connector *intel_connector;
4700
b14c5679 4701 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 4702 if (!intel_dig_port)
4703 return;
4704
b14c5679 4705 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 4706 if (!intel_connector) {
4707 kfree(intel_dig_port);
4708 return;
4709 }
4710
4711 intel_encoder = &intel_dig_port->base;
4712 encoder = &intel_encoder->base;
4713
4714 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4715 DRM_MODE_ENCODER_TMDS);
4716
5bfe2ac0 4717 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 4718 intel_encoder->disable = intel_disable_dp;
00c09d70 4719 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 4720 intel_encoder->get_config = intel_dp_get_config;
e4a1d846 4721 if (IS_CHERRYVIEW(dev)) {
9197c88b 4722 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 4723 intel_encoder->pre_enable = chv_pre_enable_dp;
4724 intel_encoder->enable = vlv_enable_dp;
580d3811 4725 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 4726 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 4727 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 4728 intel_encoder->pre_enable = vlv_pre_enable_dp;
4729 intel_encoder->enable = vlv_enable_dp;
49277c31 4730 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 4731 } else {
ecff4f3b
JN		 4732 intel_encoder->pre_enable = g4x_pre_enable_dp;
4733 intel_encoder->enable = g4x_enable_dp;
49277c31 4734 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 4735 }
f0fec3f2 4736
174edf1f 4737 intel_dig_port->port = port;
f0fec3f2
PZ		 4738 intel_dig_port->dp.output_reg = output_reg;
4739
00c09d70 4740 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 4741 if (IS_CHERRYVIEW(dev)) {
4742 if (port == PORT_D)
4743 intel_encoder->crtc_mask = 1 << 2;
4744 else
4745 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4746 } else {
4747 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4748 }
bc079e8b 4749 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 4750 intel_encoder->hot_plug = intel_dp_hot_plug;
4751
13cf5504
DA		 4752 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4753 dev_priv->hpd_irq_port[port] = intel_dig_port;
4754
15b1d171
PZ		 4755 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4756 drm_encoder_cleanup(encoder);
4757 kfree(intel_dig_port);
b2f246a8 4758 kfree(intel_connector);
15b1d171 4759 }
f0fec3f2 4760}
0e32b39c
DA		 4761
4762void intel_dp_mst_suspend(struct drm_device *dev)
4763{
4764 struct drm_i915_private *dev_priv = dev->dev_private;
4765 int i;
4766
4767 /* disable MST */
4768 for (i = 0; i < I915_MAX_PORTS; i++) {
4769 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4770 if (!intel_dig_port)
4771 continue;
4772
4773 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4774 if (!intel_dig_port->dp.can_mst)
4775 continue;
4776 if (intel_dig_port->dp.is_mst)
4777 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
4778 }
4779 }
4780}
4781
4782void intel_dp_mst_resume(struct drm_device *dev)
4783{
4784 struct drm_i915_private *dev_priv = dev->dev_private;
4785 int i;
4786
4787 for (i = 0; i < I915_MAX_PORTS; i++) {
4788 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4789 if (!intel_dig_port)
4790 continue;
4791 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4792 int ret;
4793
4794 if (!intel_dig_port->dp.can_mst)
4795 continue;
4796
4797 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
4798 if (ret != 0) {
4799 intel_dp_check_mst_status(&intel_dig_port->dp);
4800 }
4801 }
4802 }
4803}
Linux kernel - Deliverables
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