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drm/i915: Parametrize PANEL_PORT_SELECT_VLV
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 114static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 116
0e32b39c 117int
ea5b213a 118intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 119{
7183dc29 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
d4eead50 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
d4eead50 134 break;
a4fc5ed6 135 default:
d4eead50
ID		 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
a4fc5ed6
KP		 138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
eeb6324d
PZ		 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c19de8eb 189static enum drm_mode_status
a4fc5ed6
KP		 190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
df0e9248 193 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 198
dd06f90e
JN		 199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 201 return MODE_PANEL;
202
dd06f90e 203 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 204 return MODE_PANEL;
03afc4a2
DV		 205
206 target_clock = fixed_mode->clock;
7de56f43
ZY		 207 }
208
36008365 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 210 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
c4867936 216 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
0af78a2b
DV		 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
a4fc5ed6
KP		 224 return MODE_OK;
225}
226
227static uint32_t
228pack_aux(uint8_t *src, int src_bytes)
229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
fb0f8fbf
KP		 250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
9473c8f4
VP		 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
fb0f8fbf
KP		 261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
bf13e81b
JN		 284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
293static enum pipe
294vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
295{
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
298 struct drm_device *dev = intel_dig_port->base.base.dev;
299 struct drm_i915_private *dev_priv = dev->dev_private;
300 enum port port = intel_dig_port->port;
301 enum pipe pipe;
302
303 /* modeset should have pipe */
304 if (crtc)
305 return to_intel_crtc(crtc)->pipe;
306
307 /* init time, try to find a pipe with this port selected */
308 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
309 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
310 PANEL_PORT_SELECT_MASK;
ad933b56 311 if (port_sel == PANEL_PORT_SELECT_VLV(port))
bf13e81b
JN		 312 return pipe;
313 }
314
315 /* shrug */
316 return PIPE_A;
317}
318
319static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
320{
321 struct drm_device *dev = intel_dp_to_dev(intel_dp);
322
323 if (HAS_PCH_SPLIT(dev))
324 return PCH_PP_CONTROL;
325 else
326 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
327}
328
329static u32 _pp_stat_reg(struct intel_dp *intel_dp)
330{
331 struct drm_device *dev = intel_dp_to_dev(intel_dp);
332
333 if (HAS_PCH_SPLIT(dev))
334 return PCH_PP_STATUS;
335 else
336 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
337}
338
01527b31
CT		 339/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
340 This function only applicable when panel PM state is not to be tracked */
341static int edp_notify_handler(struct notifier_block *this, unsigned long code,
342 void *unused)
343{
344 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
345 edp_notifier);
346 struct drm_device *dev = intel_dp_to_dev(intel_dp);
347 struct drm_i915_private *dev_priv = dev->dev_private;
348 u32 pp_div;
349 u32 pp_ctrl_reg, pp_div_reg;
350 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
351
352 if (!is_edp(intel_dp) || code != SYS_RESTART)
353 return 0;
354
355 if (IS_VALLEYVIEW(dev)) {
356 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
357 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
358 pp_div = I915_READ(pp_div_reg);
359 pp_div &= PP_REFERENCE_DIVIDER_MASK;
360
361 /* 0x1F write to PP_DIV_REG sets max cycle delay */
362 I915_WRITE(pp_div_reg, pp_div | 0x1F);
363 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
364 msleep(intel_dp->panel_power_cycle_delay);
365 }
366
367 return 0;
368}
369
4be73780 370static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 371{
30add22d 372 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 373 struct drm_i915_private *dev_priv = dev->dev_private;
374
bf13e81b 375 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 376}
377
4be73780 378static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 379{
30add22d 380 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 381 struct drm_i915_private *dev_priv = dev->dev_private;
bb4932c4
ID		 382 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
383 struct intel_encoder *intel_encoder = &intel_dig_port->base;
384 enum intel_display_power_domain power_domain;
ebf33b18 385
bb4932c4
ID		 386 power_domain = intel_display_port_power_domain(intel_encoder);
387 return intel_display_power_enabled(dev_priv, power_domain) &&
efbc20ab 388 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 389}
390
9b984dae
KP		 391static void
392intel_dp_check_edp(struct intel_dp *intel_dp)
393{
30add22d 394 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 395 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 396
9b984dae
KP		 397 if (!is_edp(intel_dp))
398 return;
453c5420 399
4be73780 400 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 401 WARN(1, "eDP powered off while attempting aux channel communication.\n");
402 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 403 I915_READ(_pp_stat_reg(intel_dp)),
404 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 405 }
406}
407
9ee32fea
DV		 408static uint32_t
409intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
410{
411 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
412 struct drm_device *dev = intel_dig_port->base.base.dev;
413 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 414 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 415 uint32_t status;
416 bool done;
417
ef04f00d 418#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 419 if (has_aux_irq)
b18ac466 420 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 421 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 422 else
423 done = wait_for_atomic(C, 10) == 0;
424 if (!done)
425 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
426 has_aux_irq);
427#undef C
428
429 return status;
430}
431
ec5b01dd 432static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 433{
174edf1f
PZ		 434 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
435 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 436
ec5b01dd
DL		 437 /*
438 * The clock divider is based off the hrawclk, and would like to run at
439 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 440 */
ec5b01dd
DL		 441 return index ? 0 : intel_hrawclk(dev) / 2;
442}
443
444static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
445{
446 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
447 struct drm_device *dev = intel_dig_port->base.base.dev;
448
449 if (index)
450 return 0;
451
452 if (intel_dig_port->port == PORT_A) {
453 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 454 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 455 else
b84a1cf8 456 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 457 } else {
458 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
459 }
460}
461
462static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
463{
464 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
465 struct drm_device *dev = intel_dig_port->base.base.dev;
466 struct drm_i915_private *dev_priv = dev->dev_private;
467
468 if (intel_dig_port->port == PORT_A) {
469 if (index)
470 return 0;
471 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 472 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
473 /* Workaround for non-ULT HSW */
bc86625a
CW		 474 switch (index) {
475 case 0: return 63;
476 case 1: return 72;
477 default: return 0;
478 }
ec5b01dd 479 } else {
bc86625a 480 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 481 }
b84a1cf8
RV		 482}
483
ec5b01dd
DL		 484static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
485{
486 return index ? 0 : 100;
487}
488
5ed12a19
DL		 489static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
490 bool has_aux_irq,
491 int send_bytes,
492 uint32_t aux_clock_divider)
493{
494 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
495 struct drm_device *dev = intel_dig_port->base.base.dev;
496 uint32_t precharge, timeout;
497
498 if (IS_GEN6(dev))
499 precharge = 3;
500 else
501 precharge = 5;
502
503 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
504 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
505 else
506 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
507
508 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 509 DP_AUX_CH_CTL_DONE |
5ed12a19 510 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 511 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 512 timeout |
788d4433 513 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 514 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
515 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 516 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 517}
518
b84a1cf8
RV		 519static int
520intel_dp_aux_ch(struct intel_dp *intel_dp,
521 uint8_t *send, int send_bytes,
522 uint8_t *recv, int recv_size)
523{
524 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
525 struct drm_device *dev = intel_dig_port->base.base.dev;
526 struct drm_i915_private *dev_priv = dev->dev_private;
527 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
528 uint32_t ch_data = ch_ctl + 4;
bc86625a 529 uint32_t aux_clock_divider;
b84a1cf8
RV		 530 int i, ret, recv_bytes;
531 uint32_t status;
5ed12a19 532 int try, clock = 0;
4e6b788c 533 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 534 bool vdd;
535
536 vdd = _edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 537
538 /* dp aux is extremely sensitive to irq latency, hence request the
539 * lowest possible wakeup latency and so prevent the cpu from going into
540 * deep sleep states.
541 */
542 pm_qos_update_request(&dev_priv->pm_qos, 0);
543
544 intel_dp_check_edp(intel_dp);
5eb08b69 545
c67a470b
PZ		 546 intel_aux_display_runtime_get(dev_priv);
547
11bee43e
JB		 548 /* Try to wait for any previous AUX channel activity */
549 for (try = 0; try < 3; try++) {
ef04f00d 550 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 551 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
552 break;
553 msleep(1);
554 }
555
556 if (try == 3) {
557 WARN(1, "dp_aux_ch not started status 0x%08x\n",
558 I915_READ(ch_ctl));
9ee32fea
DV		 559 ret = -EBUSY;
560 goto out;
4f7f7b7e
CW		 561 }
562
46a5ae9f
PZ		 563 /* Only 5 data registers! */
564 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
565 ret = -E2BIG;
566 goto out;
567 }
568
ec5b01dd 569 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 570 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
571 has_aux_irq,
572 send_bytes,
573 aux_clock_divider);
5ed12a19 574
bc86625a
CW		 575 /* Must try at least 3 times according to DP spec */
576 for (try = 0; try < 5; try++) {
577 /* Load the send data into the aux channel data registers */
578 for (i = 0; i < send_bytes; i += 4)
579 I915_WRITE(ch_data + i,
580 pack_aux(send + i, send_bytes - i));
581
582 /* Send the command and wait for it to complete */
5ed12a19 583 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 584
585 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
586
587 /* Clear done status and any errors */
588 I915_WRITE(ch_ctl,
589 status |
590 DP_AUX_CH_CTL_DONE |
591 DP_AUX_CH_CTL_TIME_OUT_ERROR |
592 DP_AUX_CH_CTL_RECEIVE_ERROR);
593
594 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
595 DP_AUX_CH_CTL_RECEIVE_ERROR))
596 continue;
597 if (status & DP_AUX_CH_CTL_DONE)
598 break;
599 }
4f7f7b7e 600 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 601 break;
602 }
603
a4fc5ed6 604 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 605 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 606 ret = -EBUSY;
607 goto out;
a4fc5ed6
KP		 608 }
609
610 /* Check for timeout or receive error.
611 * Timeouts occur when the sink is not connected
612 */
a5b3da54 613 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 614 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 615 ret = -EIO;
616 goto out;
a5b3da54 617 }
1ae8c0a5
KP		 618
619 /* Timeouts occur when the device isn't connected, so they're
620 * "normal" -- don't fill the kernel log with these */
a5b3da54 621 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 622 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 623 ret = -ETIMEDOUT;
624 goto out;
a4fc5ed6
KP		 625 }
626
627 /* Unload any bytes sent back from the other side */
628 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
629 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 630 if (recv_bytes > recv_size)
631 recv_bytes = recv_size;
0206e353 632
4f7f7b7e
CW		 633 for (i = 0; i < recv_bytes; i += 4)
634 unpack_aux(I915_READ(ch_data + i),
635 recv + i, recv_bytes - i);
a4fc5ed6 636
9ee32fea
DV		 637 ret = recv_bytes;
638out:
639 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 640 intel_aux_display_runtime_put(dev_priv);
9ee32fea 641
884f19e9
JN		 642 if (vdd)
643 edp_panel_vdd_off(intel_dp, false);
644
9ee32fea 645 return ret;
a4fc5ed6
KP		 646}
647
a6c8aff0
JN		 648#define BARE_ADDRESS_SIZE 3
649#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 650static ssize_t
651intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 652{
9d1a1031
JN		 653 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
654 uint8_t txbuf[20], rxbuf[20];
655 size_t txsize, rxsize;
a4fc5ed6 656 int ret;
a4fc5ed6 657
9d1a1031
JN		 658 txbuf[0] = msg->request << 4;
659 txbuf[1] = msg->address >> 8;
660 txbuf[2] = msg->address & 0xff;
661 txbuf[3] = msg->size - 1;
46a5ae9f 662
9d1a1031
JN		 663 switch (msg->request & ~DP_AUX_I2C_MOT) {
664 case DP_AUX_NATIVE_WRITE:
665 case DP_AUX_I2C_WRITE:
a6c8aff0 666 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 667 rxsize = 1;
f51a44b9 668
9d1a1031
JN		 669 if (WARN_ON(txsize > 20))
670 return -E2BIG;
a4fc5ed6 671
9d1a1031 672 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 673
9d1a1031
JN		 674 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
675 if (ret > 0) {
676 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 677
9d1a1031
JN		 678 /* Return payload size. */
679 ret = msg->size;
680 }
681 break;
46a5ae9f 682
9d1a1031
JN		 683 case DP_AUX_NATIVE_READ:
684 case DP_AUX_I2C_READ:
a6c8aff0 685 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 686 rxsize = msg->size + 1;
a4fc5ed6 687
9d1a1031
JN		 688 if (WARN_ON(rxsize > 20))
689 return -E2BIG;
a4fc5ed6 690
9d1a1031
JN		 691 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
692 if (ret > 0) {
693 msg->reply = rxbuf[0] >> 4;
694 /*
695 * Assume happy day, and copy the data. The caller is
696 * expected to check msg->reply before touching it.
697 *
698 * Return payload size.
699 */
700 ret--;
701 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 702 }
9d1a1031
JN		 703 break;
704
705 default:
706 ret = -EINVAL;
707 break;
a4fc5ed6 708 }
f51a44b9 709
9d1a1031 710 return ret;
a4fc5ed6
KP		 711}
712
9d1a1031
JN		 713static void
714intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
715{
716 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 717 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
718 enum port port = intel_dig_port->port;
0b99836f 719 const char *name = NULL;
ab2c0672
DA		 720 int ret;
721
33ad6626
JN		 722 switch (port) {
723 case PORT_A:
724 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 725 name = "DPDDC-A";
ab2c0672 726 break;
33ad6626
JN		 727 case PORT_B:
728 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 729 name = "DPDDC-B";
ab2c0672 730 break;
33ad6626
JN		 731 case PORT_C:
732 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 733 name = "DPDDC-C";
ab2c0672 734 break;
33ad6626
JN		 735 case PORT_D:
736 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 737 name = "DPDDC-D";
33ad6626
JN		 738 break;
739 default:
740 BUG();
ab2c0672
DA		 741 }
742
33ad6626
JN		 743 if (!HAS_DDI(dev))
744 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 745
0b99836f 746 intel_dp->aux.name = name;
9d1a1031
JN		 747 intel_dp->aux.dev = dev->dev;
748 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 749
0b99836f
JN		 750 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
751 connector->base.kdev->kobj.name);
8316f337 752
4f71d0cb 753 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 754 if (ret < 0) {
4f71d0cb 755 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 756 name, ret);
757 return;
ab2c0672 758 }
8a5e6aeb 759
0b99836f
JN		 760 ret = sysfs_create_link(&connector->base.kdev->kobj,
761 &intel_dp->aux.ddc.dev.kobj,
762 intel_dp->aux.ddc.dev.kobj.name);
763 if (ret < 0) {
764 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 765 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 766 }
a4fc5ed6
KP		 767}
768
80f65de3
ID		 769static void
770intel_dp_connector_unregister(struct intel_connector *intel_connector)
771{
772 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
773
0e32b39c
DA		 774 if (!intel_connector->mst_port)
775 sysfs_remove_link(&intel_connector->base.kdev->kobj,
776 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 777 intel_connector_unregister(intel_connector);
778}
779
0e50338c
DV		 780static void
781hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
782{
783 switch (link_bw) {
784 case DP_LINK_BW_1_62:
785 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
786 break;
787 case DP_LINK_BW_2_7:
788 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
789 break;
790 case DP_LINK_BW_5_4:
791 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
792 break;
793 }
794}
795
c6bb3538
DV		 796static void
797intel_dp_set_clock(struct intel_encoder *encoder,
798 struct intel_crtc_config *pipe_config, int link_bw)
799{
800 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 801 const struct dp_link_dpll *divisor = NULL;
802 int i, count = 0;
c6bb3538
DV		 803
804 if (IS_G4X(dev)) {
9dd4ffdf
CML		 805 divisor = gen4_dpll;
806 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 807 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 808 divisor = pch_dpll;
809 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 810 } else if (IS_CHERRYVIEW(dev)) {
811 divisor = chv_dpll;
812 count = ARRAY_SIZE(chv_dpll);
c6bb3538 813 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 814 divisor = vlv_dpll;
815 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 816 }
9dd4ffdf
CML		 817
818 if (divisor && count) {
819 for (i = 0; i < count; i++) {
820 if (link_bw == divisor[i].link_bw) {
821 pipe_config->dpll = divisor[i].dpll;
822 pipe_config->clock_set = true;
823 break;
824 }
825 }
c6bb3538
DV		 826 }
827}
828
00c09d70 829bool
5bfe2ac0
DV		 830intel_dp_compute_config(struct intel_encoder *encoder,
831 struct intel_crtc_config *pipe_config)
a4fc5ed6 832{
5bfe2ac0 833 struct drm_device *dev = encoder->base.dev;
36008365 834 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 835 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 836 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 837 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 838 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 839 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 840 int lane_count, clock;
56071a20 841 int min_lane_count = 1;
eeb6324d 842 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 843 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 844 int min_clock = 0;
06ea66b6 845 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 846 int bpp, mode_rate;
06ea66b6 847 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 848 int link_avail, link_clock;
a4fc5ed6 849
bc7d38a4 850 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 851 pipe_config->has_pch_encoder = true;
852
03afc4a2 853 pipe_config->has_dp_encoder = true;
f769cd24 854 pipe_config->has_drrs = false;
9ed109a7 855 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 856
dd06f90e
JN		 857 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
858 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
859 adjusted_mode);
2dd24552
JB		 860 if (!HAS_PCH_SPLIT(dev))
861 intel_gmch_panel_fitting(intel_crtc, pipe_config,
862 intel_connector->panel.fitting_mode);
863 else
b074cec8
JB		 864 intel_pch_panel_fitting(intel_crtc, pipe_config,
865 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 866 }
867
cb1793ce 868 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 869 return false;
870
083f9560
DV		 871 DRM_DEBUG_KMS("DP link computation with max lane count %i "
872 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 873 max_lane_count, bws[max_clock],
874 adjusted_mode->crtc_clock);
083f9560 875
36008365
DV		 876 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
877 * bpc in between. */
3e7ca985 878 bpp = pipe_config->pipe_bpp;
56071a20
JN		 879 if (is_edp(intel_dp)) {
880 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
881 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
882 dev_priv->vbt.edp_bpp);
883 bpp = dev_priv->vbt.edp_bpp;
884 }
885
f4cdbc21
JN		 886 if (IS_BROADWELL(dev)) {
887 /* Yes, it's an ugly hack. */
888 min_lane_count = max_lane_count;
889 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
890 min_lane_count);
891 } else if (dev_priv->vbt.edp_lanes) {
56071a20
JN		 892 min_lane_count = min(dev_priv->vbt.edp_lanes,
893 max_lane_count);
894 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
895 min_lane_count);
896 }
897
898 if (dev_priv->vbt.edp_rate) {
899 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
900 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
901 bws[min_clock]);
902 }
7984211e 903 }
657445fe 904
36008365 905 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 906 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
907 bpp);
36008365 908
c6930992
DA		 909 for (clock = min_clock; clock <= max_clock; clock++) {
910 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 911 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
912 link_avail = intel_dp_max_data_rate(link_clock,
913 lane_count);
914
915 if (mode_rate <= link_avail) {
916 goto found;
917 }
918 }
919 }
920 }
c4867936 921
36008365 922 return false;
3685a8f3 923
36008365 924found:
55bc60db
VS		 925 if (intel_dp->color_range_auto) {
926 /*
927 * See:
928 * CEA-861-E - 5.1 Default Encoding Parameters
929 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
930 */
18316c8c 931 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 932 intel_dp->color_range = DP_COLOR_RANGE_16_235;
933 else
934 intel_dp->color_range = 0;
935 }
936
3685a8f3 937 if (intel_dp->color_range)
50f3b016 938 pipe_config->limited_color_range = true;
a4fc5ed6 939
36008365
DV		 940 intel_dp->link_bw = bws[clock];
941 intel_dp->lane_count = lane_count;
657445fe 942 pipe_config->pipe_bpp = bpp;
ff9a6750 943 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 944
36008365
DV		 945 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
946 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 947 pipe_config->port_clock, bpp);
36008365
DV		 948 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
949 mode_rate, link_avail);
a4fc5ed6 950
03afc4a2 951 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 952 adjusted_mode->crtc_clock,
953 pipe_config->port_clock,
03afc4a2 954 &pipe_config->dp_m_n);
9d1a455b 955
439d7ac0
PB		 956 if (intel_connector->panel.downclock_mode != NULL &&
957 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 958 pipe_config->has_drrs = true;
439d7ac0
PB		 959 intel_link_compute_m_n(bpp, lane_count,
960 intel_connector->panel.downclock_mode->clock,
961 pipe_config->port_clock,
962 &pipe_config->dp_m2_n2);
963 }
964
ea155f32 965 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 966 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
967 else
968 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 969
03afc4a2 970 return true;
a4fc5ed6
KP		 971}
972
7c62a164 973static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 974{
7c62a164
DV		 975 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
976 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
977 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 978 struct drm_i915_private *dev_priv = dev->dev_private;
979 u32 dpa_ctl;
980
ff9a6750 981 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 982 dpa_ctl = I915_READ(DP_A);
983 dpa_ctl &= ~DP_PLL_FREQ_MASK;
984
ff9a6750 985 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 986 /* For a long time we've carried around a ILK-DevA w/a for the
987 * 160MHz clock. If we're really unlucky, it's still required.
988 */
989 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 990 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 991 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 992 } else {
993 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 994 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 995 }
1ce17038 996
ea9b6006
DV		 997 I915_WRITE(DP_A, dpa_ctl);
998
999 POSTING_READ(DP_A);
1000 udelay(500);
1001}
1002
8ac33ed3 1003static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1004{
b934223d 1005 struct drm_device *dev = encoder->base.dev;
417e822d 1006 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1007 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1008 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1009 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1010 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1011
417e822d 1012 /*
1a2eb460 1013 * There are four kinds of DP registers:
417e822d
KP		 1014 *
1015 * IBX PCH
1a2eb460
KP		 1016 * SNB CPU
1017 * IVB CPU
417e822d
KP		 1018 * CPT PCH
1019 *
1020 * IBX PCH and CPU are the same for almost everything,
1021 * except that the CPU DP PLL is configured in this
1022 * register
1023 *
1024 * CPT PCH is quite different, having many bits moved
1025 * to the TRANS_DP_CTL register instead. That
1026 * configuration happens (oddly) in ironlake_pch_enable
1027 */
9c9e7927 1028
417e822d
KP		 1029 /* Preserve the BIOS-computed detected bit. This is
1030 * supposed to be read-only.
1031 */
1032 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1033
417e822d 1034 /* Handle DP bits in common between all three register formats */
417e822d 1035 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1036 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1037
9ed109a7 1038 if (crtc->config.has_audio) {
e0dac65e 1039 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1040 pipe_name(crtc->pipe));
ea5b213a 1041 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1042 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1043 }
247d89f6 1044
417e822d 1045 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1046
bc7d38a4 1047 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1048 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1049 intel_dp->DP |= DP_SYNC_HS_HIGH;
1050 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1051 intel_dp->DP |= DP_SYNC_VS_HIGH;
1052 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1053
6aba5b6c 1054 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1055 intel_dp->DP |= DP_ENHANCED_FRAMING;
1056
7c62a164 1057 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1058 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1059 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1060 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1061
1062 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1063 intel_dp->DP |= DP_SYNC_HS_HIGH;
1064 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1065 intel_dp->DP |= DP_SYNC_VS_HIGH;
1066 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1067
6aba5b6c 1068 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1069 intel_dp->DP |= DP_ENHANCED_FRAMING;
1070
44f37d1f
CML		 1071 if (!IS_CHERRYVIEW(dev)) {
1072 if (crtc->pipe == 1)
1073 intel_dp->DP |= DP_PIPEB_SELECT;
1074 } else {
1075 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1076 }
417e822d
KP		 1077 } else {
1078 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1079 }
a4fc5ed6
KP		 1080}
1081
ffd6749d
PZ		 1082#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1083#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1084
1a5ef5b7
PZ		 1085#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1086#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1087
ffd6749d
PZ		 1088#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1089#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1090
4be73780 1091static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1092 u32 mask,
1093 u32 value)
bd943159 1094{
30add22d 1095 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1096 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1097 u32 pp_stat_reg, pp_ctrl_reg;
1098
bf13e81b
JN		 1099 pp_stat_reg = _pp_stat_reg(intel_dp);
1100 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1101
99ea7127 1102 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1103 mask, value,
1104 I915_READ(pp_stat_reg),
1105 I915_READ(pp_ctrl_reg));
32ce697c 1106
453c5420 1107 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1108 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1109 I915_READ(pp_stat_reg),
1110 I915_READ(pp_ctrl_reg));
32ce697c 1111 }
54c136d4
CW		 1112
1113 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1114}
32ce697c 1115
4be73780 1116static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1117{
1118 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1119 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1120}
1121
4be73780 1122static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1123{
1124 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1125 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1126}
1127
4be73780 1128static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1129{
1130 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1131
1132 /* When we disable the VDD override bit last we have to do the manual
1133 * wait. */
1134 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1135 intel_dp->panel_power_cycle_delay);
1136
4be73780 1137 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1138}
1139
4be73780 1140static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1141{
1142 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1143 intel_dp->backlight_on_delay);
1144}
1145
4be73780 1146static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1147{
1148 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1149 intel_dp->backlight_off_delay);
1150}
99ea7127 1151
832dd3c1
KP		 1152/* Read the current pp_control value, unlocking the register if it
1153 * is locked
1154 */
1155
453c5420 1156static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1157{
453c5420
JB		 1158 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1159 struct drm_i915_private *dev_priv = dev->dev_private;
1160 u32 control;
832dd3c1 1161
bf13e81b 1162 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1163 control &= ~PANEL_UNLOCK_MASK;
1164 control |= PANEL_UNLOCK_REGS;
1165 return control;
bd943159
KP		 1166}
1167
adddaaf4 1168static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1169{
30add22d 1170 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1171 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1172 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1173 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1174 enum intel_display_power_domain power_domain;
5d613501 1175 u32 pp;
453c5420 1176 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1177 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1178
97af61f5 1179 if (!is_edp(intel_dp))
adddaaf4 1180 return false;
bd943159
KP		 1181
1182 intel_dp->want_panel_vdd = true;
99ea7127 1183
4be73780 1184 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1185 return need_to_disable;
b0665d57 1186
4e6e1a54
ID		 1187 power_domain = intel_display_port_power_domain(intel_encoder);
1188 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1189
b0665d57 1190 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1191
4be73780
DV		 1192 if (!edp_have_panel_power(intel_dp))
1193 wait_panel_power_cycle(intel_dp);
99ea7127 1194
453c5420 1195 pp = ironlake_get_pp_control(intel_dp);
5d613501 1196 pp |= EDP_FORCE_VDD;
ebf33b18 1197
bf13e81b
JN		 1198 pp_stat_reg = _pp_stat_reg(intel_dp);
1199 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1200
1201 I915_WRITE(pp_ctrl_reg, pp);
1202 POSTING_READ(pp_ctrl_reg);
1203 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1204 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1205 /*
1206 * If the panel wasn't on, delay before accessing aux channel
1207 */
4be73780 1208 if (!edp_have_panel_power(intel_dp)) {
bd943159 1209 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1210 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1211 }
adddaaf4
JN		 1212
1213 return need_to_disable;
1214}
1215
b80d6c78 1216void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4
JN		 1217{
1218 if (is_edp(intel_dp)) {
1219 bool vdd = _edp_panel_vdd_on(intel_dp);
1220
1221 WARN(!vdd, "eDP VDD already requested on\n");
1222 }
5d613501
JB		 1223}
1224
4be73780 1225static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1226{
30add22d 1227 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1228 struct drm_i915_private *dev_priv = dev->dev_private;
1229 u32 pp;
453c5420 1230 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1231
51fd371b 1232 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
a0e99e68 1233
4be73780 1234 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
4e6e1a54
ID		 1235 struct intel_digital_port *intel_dig_port =
1236 dp_to_dig_port(intel_dp);
1237 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1238 enum intel_display_power_domain power_domain;
1239
b0665d57
PZ		 1240 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1241
453c5420 1242 pp = ironlake_get_pp_control(intel_dp);
bd943159 1243 pp &= ~EDP_FORCE_VDD;
bd943159 1244
9f08ef59
PZ		 1245 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1246 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1247
1248 I915_WRITE(pp_ctrl_reg, pp);
1249 POSTING_READ(pp_ctrl_reg);
99ea7127 1250
453c5420
JB		 1251 /* Make sure sequencer is idle before allowing subsequent activity */
1252 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1253 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1254
1255 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1256 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1257
4e6e1a54
ID		 1258 power_domain = intel_display_port_power_domain(intel_encoder);
1259 intel_display_power_put(dev_priv, power_domain);
bd943159
KP		 1260 }
1261}
5d613501 1262
4be73780 1263static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1264{
1265 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1266 struct intel_dp, panel_vdd_work);
30add22d 1267 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1268
51fd371b 1269 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 1270 edp_panel_vdd_off_sync(intel_dp);
51fd371b 1271 drm_modeset_unlock(&dev->mode_config.connection_mutex);
bd943159
KP		 1272}
1273
aba86890
ID		 1274static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1275{
1276 unsigned long delay;
1277
1278 /*
1279 * Queue the timer to fire a long time from now (relative to the power
1280 * down delay) to keep the panel power up across a sequence of
1281 * operations.
1282 */
1283 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1284 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1285}
1286
4be73780 1287static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1288{
97af61f5
KP		 1289 if (!is_edp(intel_dp))
1290 return;
5d613501 1291
bd943159 1292 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1293
bd943159
KP		 1294 intel_dp->want_panel_vdd = false;
1295
aba86890 1296 if (sync)
4be73780 1297 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1298 else
1299 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1300}
1301
4be73780 1302void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1303{
30add22d 1304 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1305 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1306 u32 pp;
453c5420 1307 u32 pp_ctrl_reg;
9934c132 1308
97af61f5 1309 if (!is_edp(intel_dp))
bd943159 1310 return;
99ea7127
KP		 1311
1312 DRM_DEBUG_KMS("Turn eDP power on\n");
1313
4be73780 1314 if (edp_have_panel_power(intel_dp)) {
99ea7127 1315 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1316 return;
99ea7127 1317 }
9934c132 1318
4be73780 1319 wait_panel_power_cycle(intel_dp);
37c6c9b0 1320
bf13e81b 1321 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1322 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1323 if (IS_GEN5(dev)) {
1324 /* ILK workaround: disable reset around power sequence */
1325 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1326 I915_WRITE(pp_ctrl_reg, pp);
1327 POSTING_READ(pp_ctrl_reg);
05ce1a49 1328 }
37c6c9b0 1329
1c0ae80a 1330 pp |= POWER_TARGET_ON;
99ea7127
KP		 1331 if (!IS_GEN5(dev))
1332 pp |= PANEL_POWER_RESET;
1333
453c5420
JB		 1334 I915_WRITE(pp_ctrl_reg, pp);
1335 POSTING_READ(pp_ctrl_reg);
9934c132 1336
4be73780 1337 wait_panel_on(intel_dp);
dce56b3c 1338 intel_dp->last_power_on = jiffies;
9934c132 1339
05ce1a49
KP		 1340 if (IS_GEN5(dev)) {
1341 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1342 I915_WRITE(pp_ctrl_reg, pp);
1343 POSTING_READ(pp_ctrl_reg);
05ce1a49 1344 }
9934c132
JB		 1345}
1346
4be73780 1347void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1348{
4e6e1a54
ID		 1349 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1350 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1351 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1352 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1353 enum intel_display_power_domain power_domain;
99ea7127 1354 u32 pp;
453c5420 1355 u32 pp_ctrl_reg;
9934c132 1356
97af61f5
KP		 1357 if (!is_edp(intel_dp))
1358 return;
37c6c9b0 1359
99ea7127 1360 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1361
24f3e092
JN		 1362 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1363
453c5420 1364 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1365 /* We need to switch off panel power _and_ force vdd, for otherwise some
1366 * panels get very unhappy and cease to work. */
b3064154
PJ		 1367 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1368 EDP_BLC_ENABLE);
453c5420 1369
bf13e81b 1370 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1371
849e39f5
PZ		 1372 intel_dp->want_panel_vdd = false;
1373
453c5420
JB		 1374 I915_WRITE(pp_ctrl_reg, pp);
1375 POSTING_READ(pp_ctrl_reg);
9934c132 1376
dce56b3c 1377 intel_dp->last_power_cycle = jiffies;
4be73780 1378 wait_panel_off(intel_dp);
849e39f5
PZ		 1379
1380 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1381 power_domain = intel_display_port_power_domain(intel_encoder);
1382 intel_display_power_put(dev_priv, power_domain);
9934c132
JB		 1383}
1384
1250d107
JN		 1385/* Enable backlight in the panel power control. */
1386static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1387{
da63a9f2
PZ		 1388 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1389 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1390 struct drm_i915_private *dev_priv = dev->dev_private;
1391 u32 pp;
453c5420 1392 u32 pp_ctrl_reg;
32f9d658 1393
01cb9ea6
JB		 1394 /*
1395 * If we enable the backlight right away following a panel power
1396 * on, we may see slight flicker as the panel syncs with the eDP
1397 * link. So delay a bit to make sure the image is solid before
1398 * allowing it to appear.
1399 */
4be73780 1400 wait_backlight_on(intel_dp);
453c5420 1401 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1402 pp |= EDP_BLC_ENABLE;
453c5420 1403
bf13e81b 1404 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1405
1406 I915_WRITE(pp_ctrl_reg, pp);
1407 POSTING_READ(pp_ctrl_reg);
32f9d658
ZW		 1408}
1409
1250d107
JN		 1410/* Enable backlight PWM and backlight PP control. */
1411void intel_edp_backlight_on(struct intel_dp *intel_dp)
1412{
1413 if (!is_edp(intel_dp))
1414 return;
1415
1416 DRM_DEBUG_KMS("\n");
1417
1418 intel_panel_enable_backlight(intel_dp->attached_connector);
1419 _intel_edp_backlight_on(intel_dp);
1420}
1421
1422/* Disable backlight in the panel power control. */
1423static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1424{
30add22d 1425 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1426 struct drm_i915_private *dev_priv = dev->dev_private;
1427 u32 pp;
453c5420 1428 u32 pp_ctrl_reg;
32f9d658 1429
453c5420 1430 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1431 pp &= ~EDP_BLC_ENABLE;
453c5420 1432
bf13e81b 1433 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1434
1435 I915_WRITE(pp_ctrl_reg, pp);
1436 POSTING_READ(pp_ctrl_reg);
dce56b3c 1437 intel_dp->last_backlight_off = jiffies;
f7d2323c
JB		 1438
1439 edp_wait_backlight_off(intel_dp);
1250d107
JN		 1440}
1441
1442/* Disable backlight PP control and backlight PWM. */
1443void intel_edp_backlight_off(struct intel_dp *intel_dp)
1444{
1445 if (!is_edp(intel_dp))
1446 return;
1447
1448 DRM_DEBUG_KMS("\n");
f7d2323c 1449
1250d107 1450 _intel_edp_backlight_off(intel_dp);
f7d2323c 1451 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1452}
a4fc5ed6 1453
73580fb7
JN		 1454/*
1455 * Hook for controlling the panel power control backlight through the bl_power
1456 * sysfs attribute. Take care to handle multiple calls.
1457 */
1458static void intel_edp_backlight_power(struct intel_connector *connector,
1459 bool enable)
1460{
1461 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
1462 bool is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1463
1464 if (is_enabled == enable)
1465 return;
1466
1467 DRM_DEBUG_KMS("\n");
1468
1469 if (enable)
1470 _intel_edp_backlight_on(intel_dp);
1471 else
1472 _intel_edp_backlight_off(intel_dp);
1473}
1474
2bd2ad64 1475static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1476{
da63a9f2
PZ		 1477 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1478 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1479 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1480 struct drm_i915_private *dev_priv = dev->dev_private;
1481 u32 dpa_ctl;
1482
2bd2ad64
DV		 1483 assert_pipe_disabled(dev_priv,
1484 to_intel_crtc(crtc)->pipe);
1485
d240f20f
JB		 1486 DRM_DEBUG_KMS("\n");
1487 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1488 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1489 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1490
1491 /* We don't adjust intel_dp->DP while tearing down the link, to
1492 * facilitate link retraining (e.g. after hotplug). Hence clear all
1493 * enable bits here to ensure that we don't enable too much. */
1494 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1495 intel_dp->DP |= DP_PLL_ENABLE;
1496 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1497 POSTING_READ(DP_A);
1498 udelay(200);
d240f20f
JB		 1499}
1500
2bd2ad64 1501static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1502{
da63a9f2
PZ		 1503 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1504 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1505 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1506 struct drm_i915_private *dev_priv = dev->dev_private;
1507 u32 dpa_ctl;
1508
2bd2ad64
DV		 1509 assert_pipe_disabled(dev_priv,
1510 to_intel_crtc(crtc)->pipe);
1511
d240f20f 1512 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1513 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1514 "dp pll off, should be on\n");
1515 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1516
1517 /* We can't rely on the value tracked for the DP register in
1518 * intel_dp->DP because link_down must not change that (otherwise link
1519 * re-training will fail. */
298b0b39 1520 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1521 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1522 POSTING_READ(DP_A);
d240f20f
JB		 1523 udelay(200);
1524}
1525
c7ad3810 1526/* If the sink supports it, try to set the power state appropriately */
c19b0669 1527void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1528{
1529 int ret, i;
1530
1531 /* Should have a valid DPCD by this point */
1532 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1533 return;
1534
1535 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1536 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1537 DP_SET_POWER_D3);
c7ad3810
JB		 1538 if (ret != 1)
1539 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1540 } else {
1541 /*
1542 * When turning on, we need to retry for 1ms to give the sink
1543 * time to wake up.
1544 */
1545 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1546 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1547 DP_SET_POWER_D0);
c7ad3810
JB		 1548 if (ret == 1)
1549 break;
1550 msleep(1);
1551 }
1552 }
1553}
1554
19d8fe15
DV		 1555static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1556 enum pipe *pipe)
d240f20f 1557{
19d8fe15 1558 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1559 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1560 struct drm_device *dev = encoder->base.dev;
1561 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1562 enum intel_display_power_domain power_domain;
1563 u32 tmp;
1564
1565 power_domain = intel_display_port_power_domain(encoder);
1566 if (!intel_display_power_enabled(dev_priv, power_domain))
1567 return false;
1568
1569 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1570
1571 if (!(tmp & DP_PORT_EN))
1572 return false;
1573
bc7d38a4 1574 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1575 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1576 } else if (IS_CHERRYVIEW(dev)) {
1577 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1578 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1579 *pipe = PORT_TO_PIPE(tmp);
1580 } else {
1581 u32 trans_sel;
1582 u32 trans_dp;
1583 int i;
1584
1585 switch (intel_dp->output_reg) {
1586 case PCH_DP_B:
1587 trans_sel = TRANS_DP_PORT_SEL_B;
1588 break;
1589 case PCH_DP_C:
1590 trans_sel = TRANS_DP_PORT_SEL_C;
1591 break;
1592 case PCH_DP_D:
1593 trans_sel = TRANS_DP_PORT_SEL_D;
1594 break;
1595 default:
1596 return true;
1597 }
1598
055e393f 1599 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1600 trans_dp = I915_READ(TRANS_DP_CTL(i));
1601 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1602 *pipe = i;
1603 return true;
1604 }
1605 }
19d8fe15 1606
4a0833ec
DV		 1607 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1608 intel_dp->output_reg);
1609 }
d240f20f 1610
19d8fe15
DV		 1611 return true;
1612}
d240f20f 1613
045ac3b5
JB		 1614static void intel_dp_get_config(struct intel_encoder *encoder,
1615 struct intel_crtc_config *pipe_config)
1616{
1617 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1618 u32 tmp, flags = 0;
63000ef6
XZ		 1619 struct drm_device *dev = encoder->base.dev;
1620 struct drm_i915_private *dev_priv = dev->dev_private;
1621 enum port port = dp_to_dig_port(intel_dp)->port;
1622 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1623 int dotclock;
045ac3b5 1624
9ed109a7
DV		 1625 tmp = I915_READ(intel_dp->output_reg);
1626 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1627 pipe_config->has_audio = true;
1628
63000ef6 1629 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1630 if (tmp & DP_SYNC_HS_HIGH)
1631 flags |= DRM_MODE_FLAG_PHSYNC;
1632 else
1633 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1634
63000ef6
XZ		 1635 if (tmp & DP_SYNC_VS_HIGH)
1636 flags |= DRM_MODE_FLAG_PVSYNC;
1637 else
1638 flags |= DRM_MODE_FLAG_NVSYNC;
1639 } else {
1640 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1641 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1642 flags |= DRM_MODE_FLAG_PHSYNC;
1643 else
1644 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1645
63000ef6
XZ		 1646 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1647 flags |= DRM_MODE_FLAG_PVSYNC;
1648 else
1649 flags |= DRM_MODE_FLAG_NVSYNC;
1650 }
045ac3b5
JB		 1651
1652 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1653
eb14cb74
VS		 1654 pipe_config->has_dp_encoder = true;
1655
1656 intel_dp_get_m_n(crtc, pipe_config);
1657
18442d08 1658 if (port == PORT_A) {
f1f644dc
JB		 1659 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1660 pipe_config->port_clock = 162000;
1661 else
1662 pipe_config->port_clock = 270000;
1663 }
18442d08
VS		 1664
1665 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1666 &pipe_config->dp_m_n);
1667
1668 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1669 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1670
241bfc38 1671 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1672
c6cd2ee2
JN		 1673 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1674 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1675 /*
1676 * This is a big fat ugly hack.
1677 *
1678 * Some machines in UEFI boot mode provide us a VBT that has 18
1679 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1680 * unknown we fail to light up. Yet the same BIOS boots up with
1681 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1682 * max, not what it tells us to use.
1683 *
1684 * Note: This will still be broken if the eDP panel is not lit
1685 * up by the BIOS, and thus we can't get the mode at module
1686 * load.
1687 */
1688 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1689 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1690 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1691 }
045ac3b5
JB		 1692}
1693
34eb7579 1694static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1695{
34eb7579 1696 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1697}
1698
2b28bb1b
RV		 1699static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1700{
1701 struct drm_i915_private *dev_priv = dev->dev_private;
1702
18b5992c 1703 if (!HAS_PSR(dev))
2b28bb1b
RV		 1704 return false;
1705
18b5992c 1706 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1707}
1708
1709static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1710 struct edp_vsc_psr *vsc_psr)
1711{
1712 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1713 struct drm_device *dev = dig_port->base.base.dev;
1714 struct drm_i915_private *dev_priv = dev->dev_private;
1715 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1716 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1717 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1718 uint32_t *data = (uint32_t *) vsc_psr;
1719 unsigned int i;
1720
1721 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1722 the video DIP being updated before program video DIP data buffer
1723 registers for DIP being updated. */
1724 I915_WRITE(ctl_reg, 0);
1725 POSTING_READ(ctl_reg);
1726
1727 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1728 if (i < sizeof(struct edp_vsc_psr))
1729 I915_WRITE(data_reg + i, *data++);
1730 else
1731 I915_WRITE(data_reg + i, 0);
1732 }
1733
1734 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1735 POSTING_READ(ctl_reg);
1736}
1737
1738static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1739{
1740 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1741 struct drm_i915_private *dev_priv = dev->dev_private;
1742 struct edp_vsc_psr psr_vsc;
1743
2b28bb1b
RV		 1744 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1745 memset(&psr_vsc, 0, sizeof(psr_vsc));
1746 psr_vsc.sdp_header.HB0 = 0;
1747 psr_vsc.sdp_header.HB1 = 0x7;
1748 psr_vsc.sdp_header.HB2 = 0x2;
1749 psr_vsc.sdp_header.HB3 = 0x8;
1750 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1751
1752 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1753 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1754 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1755}
1756
1757static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1758{
0e0ae652
RV		 1759 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1760 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 1761 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1762 uint32_t aux_clock_divider;
2b28bb1b
RV		 1763 int precharge = 0x3;
1764 int msg_size = 5; /* Header(4) + Message(1) */
0e0ae652 1765 bool only_standby = false;
2b28bb1b 1766
ec5b01dd
DL		 1767 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1768
0e0ae652
RV		 1769 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1770 only_standby = true;
1771
2b28bb1b 1772 /* Enable PSR in sink */
0e0ae652 1773 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 1774 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1775 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1776 else
9d1a1031
JN		 1777 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1778 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1779
1780 /* Setup AUX registers */
18b5992c
BW		 1781 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1782 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1783 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1784 DP_AUX_CH_CTL_TIME_OUT_400us |
1785 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1786 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1787 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1788}
1789
1790static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1791{
0e0ae652
RV		 1792 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1793 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 1794 struct drm_i915_private *dev_priv = dev->dev_private;
1795 uint32_t max_sleep_time = 0x1f;
1796 uint32_t idle_frames = 1;
1797 uint32_t val = 0x0;
ed8546ac 1798 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 1799 bool only_standby = false;
1800
1801 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1802 only_standby = true;
2b28bb1b 1803
0e0ae652 1804 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 1805 val |= EDP_PSR_LINK_STANDBY;
1806 val |= EDP_PSR_TP2_TP3_TIME_0us;
1807 val |= EDP_PSR_TP1_TIME_0us;
1808 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 1809 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 1810 } else
1811 val |= EDP_PSR_LINK_DISABLE;
1812
18b5992c 1813 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1814 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1815 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1816 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1817 EDP_PSR_ENABLE);
1818}
1819
3f51e471
RV		 1820static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1821{
1822 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1823 struct drm_device *dev = dig_port->base.base.dev;
1824 struct drm_i915_private *dev_priv = dev->dev_private;
1825 struct drm_crtc *crtc = dig_port->base.base.crtc;
1826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 1827
f0355c4a 1828 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 1829 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1830 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
1831
a031d709
RV		 1832 dev_priv->psr.source_ok = false;
1833
9ca15301 1834 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 1835 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1836 return false;
1837 }
1838
d330a953 1839 if (!i915.enable_psr) {
105b7c11 1840 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1841 return false;
1842 }
1843
4c8c7000
RV		 1844 /* Below limitations aren't valid for Broadwell */
1845 if (IS_BROADWELL(dev))
1846 goto out;
1847
3f51e471
RV		 1848 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1849 S3D_ENABLE) {
1850 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1851 return false;
1852 }
1853
ca73b4f0 1854 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1855 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1856 return false;
1857 }
1858
4c8c7000 1859 out:
a031d709 1860 dev_priv->psr.source_ok = true;
3f51e471
RV		 1861 return true;
1862}
1863
3d739d92 1864static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 1865{
7c8f8a70
RV		 1866 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1867 struct drm_device *dev = intel_dig_port->base.base.dev;
1868 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 1869
3638379c
DV		 1870 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1871 WARN_ON(dev_priv->psr.active);
f0355c4a 1872 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 1873
2b28bb1b
RV		 1874 /* Enable PSR on the panel */
1875 intel_edp_psr_enable_sink(intel_dp);
1876
1877 /* Enable PSR on the host */
1878 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 1879
7c8f8a70 1880 dev_priv->psr.active = true;
2b28bb1b
RV		 1881}
1882
3d739d92
RV		 1883void intel_edp_psr_enable(struct intel_dp *intel_dp)
1884{
1885 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 1886 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 1887
4704c573
RV		 1888 if (!HAS_PSR(dev)) {
1889 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1890 return;
1891 }
1892
34eb7579
RV		 1893 if (!is_edp_psr(intel_dp)) {
1894 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1895 return;
1896 }
1897
f0355c4a 1898 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 1899 if (dev_priv->psr.enabled) {
1900 DRM_DEBUG_KMS("PSR already in use\n");
f0355c4a 1901 mutex_unlock(&dev_priv->psr.lock);
109fc2ad
DV		 1902 return;
1903 }
1904
9ca15301
DV		 1905 dev_priv->psr.busy_frontbuffer_bits = 0;
1906
16487254
RV		 1907 /* Setup PSR once */
1908 intel_edp_psr_setup(intel_dp);
1909
7c8f8a70 1910 if (intel_edp_psr_match_conditions(intel_dp))
9ca15301 1911 dev_priv->psr.enabled = intel_dp;
f0355c4a 1912 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 1913}
1914
2b28bb1b
RV		 1915void intel_edp_psr_disable(struct intel_dp *intel_dp)
1916{
1917 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1918 struct drm_i915_private *dev_priv = dev->dev_private;
1919
f0355c4a
DV		 1920 mutex_lock(&dev_priv->psr.lock);
1921 if (!dev_priv->psr.enabled) {
1922 mutex_unlock(&dev_priv->psr.lock);
1923 return;
1924 }
1925
3638379c
DV		 1926 if (dev_priv->psr.active) {
1927 I915_WRITE(EDP_PSR_CTL(dev),
1928 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1929
1930 /* Wait till PSR is idle */
1931 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1932 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1933 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 1934
3638379c
DV		 1935 dev_priv->psr.active = false;
1936 } else {
1937 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1938 }
7c8f8a70 1939
2807cf69 1940 dev_priv->psr.enabled = NULL;
f0355c4a 1941 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 1942
1943 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 1944}
1945
f02a326e 1946static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 1947{
1948 struct drm_i915_private *dev_priv =
1949 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 1950 struct intel_dp *intel_dp = dev_priv->psr.enabled;
1951
f0355c4a
DV		 1952 mutex_lock(&dev_priv->psr.lock);
1953 intel_dp = dev_priv->psr.enabled;
1954
2807cf69 1955 if (!intel_dp)
f0355c4a 1956 goto unlock;
2807cf69 1957
9ca15301
DV		 1958 /*
1959 * The delayed work can race with an invalidate hence we need to
1960 * recheck. Since psr_flush first clears this and then reschedules we
1961 * won't ever miss a flush when bailing out here.
1962 */
1963 if (dev_priv->psr.busy_frontbuffer_bits)
1964 goto unlock;
1965
1966 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 1967unlock:
1968 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 1969}
1970
9ca15301 1971static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 1972{
1973 struct drm_i915_private *dev_priv = dev->dev_private;
1974
3638379c
DV		 1975 if (dev_priv->psr.active) {
1976 u32 val = I915_READ(EDP_PSR_CTL(dev));
1977
1978 WARN_ON(!(val & EDP_PSR_ENABLE));
1979
1980 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
1981
1982 dev_priv->psr.active = false;
1983 }
7c8f8a70 1984
9ca15301
DV		 1985}
1986
1987void intel_edp_psr_invalidate(struct drm_device *dev,
1988 unsigned frontbuffer_bits)
1989{
1990 struct drm_i915_private *dev_priv = dev->dev_private;
1991 struct drm_crtc *crtc;
1992 enum pipe pipe;
1993
9ca15301
DV		 1994 mutex_lock(&dev_priv->psr.lock);
1995 if (!dev_priv->psr.enabled) {
1996 mutex_unlock(&dev_priv->psr.lock);
1997 return;
1998 }
1999
2000 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2001 pipe = to_intel_crtc(crtc)->pipe;
2002
2003 intel_edp_psr_do_exit(dev);
2004
2005 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2006
2007 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2008 mutex_unlock(&dev_priv->psr.lock);
2009}
2010
2011void intel_edp_psr_flush(struct drm_device *dev,
2012 unsigned frontbuffer_bits)
2013{
2014 struct drm_i915_private *dev_priv = dev->dev_private;
2015 struct drm_crtc *crtc;
2016 enum pipe pipe;
2017
9ca15301
DV		 2018 mutex_lock(&dev_priv->psr.lock);
2019 if (!dev_priv->psr.enabled) {
2020 mutex_unlock(&dev_priv->psr.lock);
2021 return;
2022 }
2023
2024 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2025 pipe = to_intel_crtc(crtc)->pipe;
2026 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2027
2028 /*
2029 * On Haswell sprite plane updates don't result in a psr invalidating
2030 * signal in the hardware. Which means we need to manually fake this in
2031 * software for all flushes, not just when we've seen a preceding
2032 * invalidation through frontbuffer rendering.
2033 */
2034 if (IS_HASWELL(dev) &&
2035 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2036 intel_edp_psr_do_exit(dev);
2037
2038 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2039 schedule_delayed_work(&dev_priv->psr.work,
2040 msecs_to_jiffies(100));
f0355c4a 2041 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2042}
2043
2044void intel_edp_psr_init(struct drm_device *dev)
2045{
2046 struct drm_i915_private *dev_priv = dev->dev_private;
2047
7c8f8a70 2048 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2049 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2050}
2051
e8cb4558 2052static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2053{
e8cb4558 2054 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 2055 enum port port = dp_to_dig_port(intel_dp)->port;
2056 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2057
2058 /* Make sure the panel is off before trying to change the mode. But also
2059 * ensure that we have vdd while we switch off the panel. */
24f3e092 2060 intel_edp_panel_vdd_on(intel_dp);
4be73780 2061 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2062 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2063 intel_edp_panel_off(intel_dp);
3739850b
DV		 2064
2065 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 2066 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 2067 intel_dp_link_down(intel_dp);
d240f20f
JB		 2068}
2069
49277c31 2070static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2071{
2bd2ad64 2072 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2073 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2074
49277c31
VS		 2075 if (port != PORT_A)
2076 return;
2077
2078 intel_dp_link_down(intel_dp);
2079 ironlake_edp_pll_off(intel_dp);
2080}
2081
2082static void vlv_post_disable_dp(struct intel_encoder *encoder)
2083{
2084 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2085
2086 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2087}
2088
580d3811
VS		 2089static void chv_post_disable_dp(struct intel_encoder *encoder)
2090{
2091 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2092 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2093 struct drm_device *dev = encoder->base.dev;
2094 struct drm_i915_private *dev_priv = dev->dev_private;
2095 struct intel_crtc *intel_crtc =
2096 to_intel_crtc(encoder->base.crtc);
2097 enum dpio_channel ch = vlv_dport_to_channel(dport);
2098 enum pipe pipe = intel_crtc->pipe;
2099 u32 val;
2100
2101 intel_dp_link_down(intel_dp);
2102
2103 mutex_lock(&dev_priv->dpio_lock);
2104
2105 /* Propagate soft reset to data lane reset */
97fd4d5c 2106 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2107 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2108 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2109
97fd4d5c
VS		 2110 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2111 val |= CHV_PCS_REQ_SOFTRESET_EN;
2112 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2113
2114 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2115 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2116 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2117
2118 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2119 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2120 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2121
2122 mutex_unlock(&dev_priv->dpio_lock);
2123}
2124
e8cb4558 2125static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2126{
e8cb4558
DV		 2127 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2128 struct drm_device *dev = encoder->base.dev;
2129 struct drm_i915_private *dev_priv = dev->dev_private;
2130 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2131
0c33d8d7
DV		 2132 if (WARN_ON(dp_reg & DP_PORT_EN))
2133 return;
5d613501 2134
24f3e092 2135 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 2136 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2137 intel_dp_start_link_train(intel_dp);
4be73780
DV		 2138 intel_edp_panel_on(intel_dp);
2139 edp_panel_vdd_off(intel_dp, true);
33a34e4e 2140 intel_dp_complete_link_train(intel_dp);
3ab9c637 2141 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2142}
89b667f8 2143
ecff4f3b
JN		 2144static void g4x_enable_dp(struct intel_encoder *encoder)
2145{
828f5c6e
JN		 2146 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2147
ecff4f3b 2148 intel_enable_dp(encoder);
4be73780 2149 intel_edp_backlight_on(intel_dp);
ab1f90f9 2150}
89b667f8 2151
ab1f90f9
JN		 2152static void vlv_enable_dp(struct intel_encoder *encoder)
2153{
828f5c6e
JN		 2154 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2155
4be73780 2156 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2157}
2158
ecff4f3b 2159static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2160{
2161 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2162 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2163
8ac33ed3
DV		 2164 intel_dp_prepare(encoder);
2165
d41f1efb
DV		 2166 /* Only ilk+ has port A */
2167 if (dport->port == PORT_A) {
2168 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2169 ironlake_edp_pll_on(intel_dp);
d41f1efb 2170 }
ab1f90f9
JN		 2171}
2172
2173static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2174{
2bd2ad64 2175 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2176 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2177 struct drm_device *dev = encoder->base.dev;
89b667f8 2178 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2179 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2180 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 2181 int pipe = intel_crtc->pipe;
bf13e81b 2182 struct edp_power_seq power_seq;
ab1f90f9 2183 u32 val;
a4fc5ed6 2184
ab1f90f9 2185 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2186
ab3c759a 2187 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2188 val = 0;
2189 if (pipe)
2190 val |= (1<<21);
2191 else
2192 val &= ~(1<<21);
2193 val |= 0x001000c4;
ab3c759a
CML		 2194 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2195 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2196 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2197
ab1f90f9
JN		 2198 mutex_unlock(&dev_priv->dpio_lock);
2199
2cac613b
ID		 2200 if (is_edp(intel_dp)) {
2201 /* init power sequencer on this pipe and port */
2202 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2203 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2204 &power_seq);
2205 }
bf13e81b 2206
ab1f90f9
JN		 2207 intel_enable_dp(encoder);
2208
e4607fcf 2209 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2210}
2211
ecff4f3b 2212static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2213{
2214 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2215 struct drm_device *dev = encoder->base.dev;
2216 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2217 struct intel_crtc *intel_crtc =
2218 to_intel_crtc(encoder->base.crtc);
e4607fcf 2219 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2220 int pipe = intel_crtc->pipe;
89b667f8 2221
8ac33ed3
DV		 2222 intel_dp_prepare(encoder);
2223
89b667f8 2224 /* Program Tx lane resets to default */
0980a60f 2225 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2226 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2227 DPIO_PCS_TX_LANE2_RESET |
2228 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2229 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2230 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2231 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2232 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2233 DPIO_PCS_CLK_SOFT_RESET);
2234
2235 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2236 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2237 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2238 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2239 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2240}
2241
e4a1d846
CML		 2242static void chv_pre_enable_dp(struct intel_encoder *encoder)
2243{
2244 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2245 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2246 struct drm_device *dev = encoder->base.dev;
2247 struct drm_i915_private *dev_priv = dev->dev_private;
2248 struct edp_power_seq power_seq;
2249 struct intel_crtc *intel_crtc =
2250 to_intel_crtc(encoder->base.crtc);
2251 enum dpio_channel ch = vlv_dport_to_channel(dport);
2252 int pipe = intel_crtc->pipe;
2253 int data, i;
949c1d43 2254 u32 val;
e4a1d846 2255
e4a1d846 2256 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2257
2258 /* Deassert soft data lane reset*/
97fd4d5c 2259 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2260 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2261 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2262
2263 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2264 val |= CHV_PCS_REQ_SOFTRESET_EN;
2265 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2266
2267 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2268 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2269 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2270
97fd4d5c 2271 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2272 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2273 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2274
2275 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2276 for (i = 0; i < 4; i++) {
2277 /* Set the latency optimal bit */
2278 data = (i == 1) ? 0x0 : 0x6;
2279 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2280 data << DPIO_FRC_LATENCY_SHFIT);
2281
2282 /* Set the upar bit */
2283 data = (i == 1) ? 0x0 : 0x1;
2284 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2285 data << DPIO_UPAR_SHIFT);
2286 }
2287
2288 /* Data lane stagger programming */
2289 /* FIXME: Fix up value only after power analysis */
2290
2291 mutex_unlock(&dev_priv->dpio_lock);
2292
2293 if (is_edp(intel_dp)) {
2294 /* init power sequencer on this pipe and port */
2295 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2296 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2297 &power_seq);
2298 }
2299
2300 intel_enable_dp(encoder);
2301
2302 vlv_wait_port_ready(dev_priv, dport);
2303}
2304
9197c88b
VS		 2305static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2306{
2307 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2308 struct drm_device *dev = encoder->base.dev;
2309 struct drm_i915_private *dev_priv = dev->dev_private;
2310 struct intel_crtc *intel_crtc =
2311 to_intel_crtc(encoder->base.crtc);
2312 enum dpio_channel ch = vlv_dport_to_channel(dport);
2313 enum pipe pipe = intel_crtc->pipe;
2314 u32 val;
2315
625695f8
VS		 2316 intel_dp_prepare(encoder);
2317
9197c88b
VS		 2318 mutex_lock(&dev_priv->dpio_lock);
2319
b9e5ac3c
VS		 2320 /* program left/right clock distribution */
2321 if (pipe != PIPE_B) {
2322 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2323 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2324 if (ch == DPIO_CH0)
2325 val |= CHV_BUFLEFTENA1_FORCE;
2326 if (ch == DPIO_CH1)
2327 val |= CHV_BUFRIGHTENA1_FORCE;
2328 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2329 } else {
2330 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2331 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2332 if (ch == DPIO_CH0)
2333 val |= CHV_BUFLEFTENA2_FORCE;
2334 if (ch == DPIO_CH1)
2335 val |= CHV_BUFRIGHTENA2_FORCE;
2336 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2337 }
2338
9197c88b
VS		 2339 /* program clock channel usage */
2340 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2341 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2342 if (pipe != PIPE_B)
2343 val &= ~CHV_PCS_USEDCLKCHANNEL;
2344 else
2345 val |= CHV_PCS_USEDCLKCHANNEL;
2346 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2347
2348 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2349 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2350 if (pipe != PIPE_B)
2351 val &= ~CHV_PCS_USEDCLKCHANNEL;
2352 else
2353 val |= CHV_PCS_USEDCLKCHANNEL;
2354 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2355
2356 /*
2357 * This a a bit weird since generally CL
2358 * matches the pipe, but here we need to
2359 * pick the CL based on the port.
2360 */
2361 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2362 if (pipe != PIPE_B)
2363 val &= ~CHV_CMN_USEDCLKCHANNEL;
2364 else
2365 val |= CHV_CMN_USEDCLKCHANNEL;
2366 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2367
2368 mutex_unlock(&dev_priv->dpio_lock);
2369}
2370
a4fc5ed6 2371/*
df0c237d
JB		 2372 * Native read with retry for link status and receiver capability reads for
2373 * cases where the sink may still be asleep.
9d1a1031
JN		 2374 *
2375 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2376 * supposed to retry 3 times per the spec.
a4fc5ed6 2377 */
9d1a1031
JN		 2378static ssize_t
2379intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2380 void *buffer, size_t size)
a4fc5ed6 2381{
9d1a1031
JN		 2382 ssize_t ret;
2383 int i;
61da5fab 2384
61da5fab 2385 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2386 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2387 if (ret == size)
2388 return ret;
61da5fab
JB		 2389 msleep(1);
2390 }
a4fc5ed6 2391
9d1a1031 2392 return ret;
a4fc5ed6
KP		 2393}
2394
2395/*
2396 * Fetch AUX CH registers 0x202 - 0x207 which contain
2397 * link status information
2398 */
2399static bool
93f62dad 2400intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2401{
9d1a1031
JN		 2402 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2403 DP_LANE0_1_STATUS,
2404 link_status,
2405 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2406}
2407
1100244e 2408/* These are source-specific values. */
a4fc5ed6 2409static uint8_t
1a2eb460 2410intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2411{
30add22d 2412 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2413 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2414
9576c27f 2415 if (IS_VALLEYVIEW(dev))
e2fa6fba 2416 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2417 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2418 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2419 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2420 return DP_TRAIN_VOLTAGE_SWING_1200;
2421 else
2422 return DP_TRAIN_VOLTAGE_SWING_800;
2423}
2424
2425static uint8_t
2426intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2427{
30add22d 2428 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2429 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2430
9576c27f 2431 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722
PZ		 2432 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2433 case DP_TRAIN_VOLTAGE_SWING_400:
2434 return DP_TRAIN_PRE_EMPHASIS_9_5;
2435 case DP_TRAIN_VOLTAGE_SWING_600:
2436 return DP_TRAIN_PRE_EMPHASIS_6;
2437 case DP_TRAIN_VOLTAGE_SWING_800:
2438 return DP_TRAIN_PRE_EMPHASIS_3_5;
2439 case DP_TRAIN_VOLTAGE_SWING_1200:
2440 default:
2441 return DP_TRAIN_PRE_EMPHASIS_0;
2442 }
e2fa6fba
P		 2443 } else if (IS_VALLEYVIEW(dev)) {
2444 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2445 case DP_TRAIN_VOLTAGE_SWING_400:
2446 return DP_TRAIN_PRE_EMPHASIS_9_5;
2447 case DP_TRAIN_VOLTAGE_SWING_600:
2448 return DP_TRAIN_PRE_EMPHASIS_6;
2449 case DP_TRAIN_VOLTAGE_SWING_800:
2450 return DP_TRAIN_PRE_EMPHASIS_3_5;
2451 case DP_TRAIN_VOLTAGE_SWING_1200:
2452 default:
2453 return DP_TRAIN_PRE_EMPHASIS_0;
2454 }
bc7d38a4 2455 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2456 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2457 case DP_TRAIN_VOLTAGE_SWING_400:
2458 return DP_TRAIN_PRE_EMPHASIS_6;
2459 case DP_TRAIN_VOLTAGE_SWING_600:
2460 case DP_TRAIN_VOLTAGE_SWING_800:
2461 return DP_TRAIN_PRE_EMPHASIS_3_5;
2462 default:
2463 return DP_TRAIN_PRE_EMPHASIS_0;
2464 }
2465 } else {
2466 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2467 case DP_TRAIN_VOLTAGE_SWING_400:
2468 return DP_TRAIN_PRE_EMPHASIS_6;
2469 case DP_TRAIN_VOLTAGE_SWING_600:
2470 return DP_TRAIN_PRE_EMPHASIS_6;
2471 case DP_TRAIN_VOLTAGE_SWING_800:
2472 return DP_TRAIN_PRE_EMPHASIS_3_5;
2473 case DP_TRAIN_VOLTAGE_SWING_1200:
2474 default:
2475 return DP_TRAIN_PRE_EMPHASIS_0;
2476 }
a4fc5ed6
KP		 2477 }
2478}
2479
e2fa6fba
P		 2480static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2481{
2482 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2483 struct drm_i915_private *dev_priv = dev->dev_private;
2484 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2485 struct intel_crtc *intel_crtc =
2486 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2487 unsigned long demph_reg_value, preemph_reg_value,
2488 uniqtranscale_reg_value;
2489 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2490 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2491 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2492
2493 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2494 case DP_TRAIN_PRE_EMPHASIS_0:
2495 preemph_reg_value = 0x0004000;
2496 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2497 case DP_TRAIN_VOLTAGE_SWING_400:
2498 demph_reg_value = 0x2B405555;
2499 uniqtranscale_reg_value = 0x552AB83A;
2500 break;
2501 case DP_TRAIN_VOLTAGE_SWING_600:
2502 demph_reg_value = 0x2B404040;
2503 uniqtranscale_reg_value = 0x5548B83A;
2504 break;
2505 case DP_TRAIN_VOLTAGE_SWING_800:
2506 demph_reg_value = 0x2B245555;
2507 uniqtranscale_reg_value = 0x5560B83A;
2508 break;
2509 case DP_TRAIN_VOLTAGE_SWING_1200:
2510 demph_reg_value = 0x2B405555;
2511 uniqtranscale_reg_value = 0x5598DA3A;
2512 break;
2513 default:
2514 return 0;
2515 }
2516 break;
2517 case DP_TRAIN_PRE_EMPHASIS_3_5:
2518 preemph_reg_value = 0x0002000;
2519 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2520 case DP_TRAIN_VOLTAGE_SWING_400:
2521 demph_reg_value = 0x2B404040;
2522 uniqtranscale_reg_value = 0x5552B83A;
2523 break;
2524 case DP_TRAIN_VOLTAGE_SWING_600:
2525 demph_reg_value = 0x2B404848;
2526 uniqtranscale_reg_value = 0x5580B83A;
2527 break;
2528 case DP_TRAIN_VOLTAGE_SWING_800:
2529 demph_reg_value = 0x2B404040;
2530 uniqtranscale_reg_value = 0x55ADDA3A;
2531 break;
2532 default:
2533 return 0;
2534 }
2535 break;
2536 case DP_TRAIN_PRE_EMPHASIS_6:
2537 preemph_reg_value = 0x0000000;
2538 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2539 case DP_TRAIN_VOLTAGE_SWING_400:
2540 demph_reg_value = 0x2B305555;
2541 uniqtranscale_reg_value = 0x5570B83A;
2542 break;
2543 case DP_TRAIN_VOLTAGE_SWING_600:
2544 demph_reg_value = 0x2B2B4040;
2545 uniqtranscale_reg_value = 0x55ADDA3A;
2546 break;
2547 default:
2548 return 0;
2549 }
2550 break;
2551 case DP_TRAIN_PRE_EMPHASIS_9_5:
2552 preemph_reg_value = 0x0006000;
2553 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2554 case DP_TRAIN_VOLTAGE_SWING_400:
2555 demph_reg_value = 0x1B405555;
2556 uniqtranscale_reg_value = 0x55ADDA3A;
2557 break;
2558 default:
2559 return 0;
2560 }
2561 break;
2562 default:
2563 return 0;
2564 }
2565
0980a60f 2566 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2567 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2568 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2569 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2570 uniqtranscale_reg_value);
ab3c759a
CML		 2571 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2572 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2573 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2574 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2575 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2576
2577 return 0;
2578}
2579
e4a1d846
CML		 2580static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2581{
2582 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2583 struct drm_i915_private *dev_priv = dev->dev_private;
2584 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2585 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2586 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2587 uint8_t train_set = intel_dp->train_set[0];
2588 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2589 enum pipe pipe = intel_crtc->pipe;
2590 int i;
e4a1d846
CML		 2591
2592 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2593 case DP_TRAIN_PRE_EMPHASIS_0:
2594 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2595 case DP_TRAIN_VOLTAGE_SWING_400:
2596 deemph_reg_value = 128;
2597 margin_reg_value = 52;
2598 break;
2599 case DP_TRAIN_VOLTAGE_SWING_600:
2600 deemph_reg_value = 128;
2601 margin_reg_value = 77;
2602 break;
2603 case DP_TRAIN_VOLTAGE_SWING_800:
2604 deemph_reg_value = 128;
2605 margin_reg_value = 102;
2606 break;
2607 case DP_TRAIN_VOLTAGE_SWING_1200:
2608 deemph_reg_value = 128;
2609 margin_reg_value = 154;
2610 /* FIXME extra to set for 1200 */
2611 break;
2612 default:
2613 return 0;
2614 }
2615 break;
2616 case DP_TRAIN_PRE_EMPHASIS_3_5:
2617 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2618 case DP_TRAIN_VOLTAGE_SWING_400:
2619 deemph_reg_value = 85;
2620 margin_reg_value = 78;
2621 break;
2622 case DP_TRAIN_VOLTAGE_SWING_600:
2623 deemph_reg_value = 85;
2624 margin_reg_value = 116;
2625 break;
2626 case DP_TRAIN_VOLTAGE_SWING_800:
2627 deemph_reg_value = 85;
2628 margin_reg_value = 154;
2629 break;
2630 default:
2631 return 0;
2632 }
2633 break;
2634 case DP_TRAIN_PRE_EMPHASIS_6:
2635 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2636 case DP_TRAIN_VOLTAGE_SWING_400:
2637 deemph_reg_value = 64;
2638 margin_reg_value = 104;
2639 break;
2640 case DP_TRAIN_VOLTAGE_SWING_600:
2641 deemph_reg_value = 64;
2642 margin_reg_value = 154;
2643 break;
2644 default:
2645 return 0;
2646 }
2647 break;
2648 case DP_TRAIN_PRE_EMPHASIS_9_5:
2649 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2650 case DP_TRAIN_VOLTAGE_SWING_400:
2651 deemph_reg_value = 43;
2652 margin_reg_value = 154;
2653 break;
2654 default:
2655 return 0;
2656 }
2657 break;
2658 default:
2659 return 0;
2660 }
2661
2662 mutex_lock(&dev_priv->dpio_lock);
2663
2664 /* Clear calc init */
1966e59e
VS		 2665 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2666 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2667 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2668
2669 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2670 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2671 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2672
2673 /* Program swing deemph */
f72df8db
VS		 2674 for (i = 0; i < 4; i++) {
2675 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2676 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2677 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2678 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2679 }
e4a1d846
CML		 2680
2681 /* Program swing margin */
f72df8db
VS		 2682 for (i = 0; i < 4; i++) {
2683 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 2684 val &= ~DPIO_SWING_MARGIN000_MASK;
2685 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 2686 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2687 }
e4a1d846
CML		 2688
2689 /* Disable unique transition scale */
f72df8db
VS		 2690 for (i = 0; i < 4; i++) {
2691 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2692 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2693 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2694 }
e4a1d846
CML		 2695
2696 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2697 == DP_TRAIN_PRE_EMPHASIS_0) &&
2698 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2699 == DP_TRAIN_VOLTAGE_SWING_1200)) {
2700
2701 /*
2702 * The document said it needs to set bit 27 for ch0 and bit 26
2703 * for ch1. Might be a typo in the doc.
2704 * For now, for this unique transition scale selection, set bit
2705 * 27 for ch0 and ch1.
2706 */
f72df8db
VS		 2707 for (i = 0; i < 4; i++) {
2708 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2709 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2710 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2711 }
e4a1d846 2712
f72df8db
VS		 2713 for (i = 0; i < 4; i++) {
2714 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2715 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2716 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2717 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2718 }
e4a1d846
CML		 2719 }
2720
2721 /* Start swing calculation */
1966e59e
VS		 2722 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2723 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2724 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2725
2726 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2727 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2728 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2729
2730 /* LRC Bypass */
2731 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2732 val |= DPIO_LRC_BYPASS;
2733 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2734
2735 mutex_unlock(&dev_priv->dpio_lock);
2736
2737 return 0;
2738}
2739
a4fc5ed6 2740static void
0301b3ac
JN		 2741intel_get_adjust_train(struct intel_dp *intel_dp,
2742 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2743{
2744 uint8_t v = 0;
2745 uint8_t p = 0;
2746 int lane;
1a2eb460
KP		 2747 uint8_t voltage_max;
2748 uint8_t preemph_max;
a4fc5ed6 2749
33a34e4e 2750 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2751 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2752 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2753
2754 if (this_v > v)
2755 v = this_v;
2756 if (this_p > p)
2757 p = this_p;
2758 }
2759
1a2eb460 2760 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2761 if (v >= voltage_max)
2762 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2763
1a2eb460
KP		 2764 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2765 if (p >= preemph_max)
2766 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2767
2768 for (lane = 0; lane < 4; lane++)
33a34e4e 2769 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2770}
2771
2772static uint32_t
f0a3424e 2773intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2774{
3cf2efb1 2775 uint32_t signal_levels = 0;
a4fc5ed6 2776
3cf2efb1 2777 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2778 case DP_TRAIN_VOLTAGE_SWING_400:
2779 default:
2780 signal_levels |= DP_VOLTAGE_0_4;
2781 break;
2782 case DP_TRAIN_VOLTAGE_SWING_600:
2783 signal_levels |= DP_VOLTAGE_0_6;
2784 break;
2785 case DP_TRAIN_VOLTAGE_SWING_800:
2786 signal_levels |= DP_VOLTAGE_0_8;
2787 break;
2788 case DP_TRAIN_VOLTAGE_SWING_1200:
2789 signal_levels |= DP_VOLTAGE_1_2;
2790 break;
2791 }
3cf2efb1 2792 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2793 case DP_TRAIN_PRE_EMPHASIS_0:
2794 default:
2795 signal_levels |= DP_PRE_EMPHASIS_0;
2796 break;
2797 case DP_TRAIN_PRE_EMPHASIS_3_5:
2798 signal_levels |= DP_PRE_EMPHASIS_3_5;
2799 break;
2800 case DP_TRAIN_PRE_EMPHASIS_6:
2801 signal_levels |= DP_PRE_EMPHASIS_6;
2802 break;
2803 case DP_TRAIN_PRE_EMPHASIS_9_5:
2804 signal_levels |= DP_PRE_EMPHASIS_9_5;
2805 break;
2806 }
2807 return signal_levels;
2808}
2809
e3421a18
ZW		 2810/* Gen6's DP voltage swing and pre-emphasis control */
2811static uint32_t
2812intel_gen6_edp_signal_levels(uint8_t train_set)
2813{
3c5a62b5
YL		 2814 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2815 DP_TRAIN_PRE_EMPHASIS_MASK);
2816 switch (signal_levels) {
e3421a18 2817 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2818 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2819 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2820 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2821 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2822 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2823 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2824 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2825 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2826 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2827 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2828 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2829 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2830 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2831 default:
3c5a62b5
YL		 2832 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2833 "0x%x\n", signal_levels);
2834 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2835 }
2836}
2837
1a2eb460
KP		 2838/* Gen7's DP voltage swing and pre-emphasis control */
2839static uint32_t
2840intel_gen7_edp_signal_levels(uint8_t train_set)
2841{
2842 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2843 DP_TRAIN_PRE_EMPHASIS_MASK);
2844 switch (signal_levels) {
2845 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2846 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2847 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2848 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2849 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2850 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2851
2852 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2853 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2854 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2855 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2856
2857 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2858 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2859 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2860 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2861
2862 default:
2863 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2864 "0x%x\n", signal_levels);
2865 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2866 }
2867}
2868
d6c0d722
PZ		 2869/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2870static uint32_t
f0a3424e 2871intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2872{
d6c0d722
PZ		 2873 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2874 DP_TRAIN_PRE_EMPHASIS_MASK);
2875 switch (signal_levels) {
2876 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2877 return DDI_BUF_EMP_400MV_0DB_HSW;
2878 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2879 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2880 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2881 return DDI_BUF_EMP_400MV_6DB_HSW;
2882 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2883 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2884
d6c0d722
PZ		 2885 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2886 return DDI_BUF_EMP_600MV_0DB_HSW;
2887 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2888 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2889 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2890 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2891
d6c0d722
PZ		 2892 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2893 return DDI_BUF_EMP_800MV_0DB_HSW;
2894 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2895 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2896 default:
2897 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2898 "0x%x\n", signal_levels);
2899 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2900 }
a4fc5ed6
KP		 2901}
2902
f0a3424e
PZ		 2903/* Properly updates "DP" with the correct signal levels. */
2904static void
2905intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2906{
2907 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2908 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2909 struct drm_device *dev = intel_dig_port->base.base.dev;
2910 uint32_t signal_levels, mask;
2911 uint8_t train_set = intel_dp->train_set[0];
2912
9576c27f 2913 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
f0a3424e
PZ		 2914 signal_levels = intel_hsw_signal_levels(train_set);
2915 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 2916 } else if (IS_CHERRYVIEW(dev)) {
2917 signal_levels = intel_chv_signal_levels(intel_dp);
2918 mask = 0;
e2fa6fba
P		 2919 } else if (IS_VALLEYVIEW(dev)) {
2920 signal_levels = intel_vlv_signal_levels(intel_dp);
2921 mask = 0;
bc7d38a4 2922 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2923 signal_levels = intel_gen7_edp_signal_levels(train_set);
2924 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2925 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2926 signal_levels = intel_gen6_edp_signal_levels(train_set);
2927 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2928 } else {
2929 signal_levels = intel_gen4_signal_levels(train_set);
2930 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2931 }
2932
2933 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2934
2935 *DP = (*DP & ~mask) | signal_levels;
2936}
2937
a4fc5ed6 2938static bool
ea5b213a 2939intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2940 uint32_t *DP,
58e10eb9 2941 uint8_t dp_train_pat)
a4fc5ed6 2942{
174edf1f
PZ		 2943 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2944 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2945 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2946 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2947 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2948 int ret, len;
a4fc5ed6 2949
22b8bf17 2950 if (HAS_DDI(dev)) {
3ab9c637 2951 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2952
2953 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2954 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2955 else
2956 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2957
2958 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2959 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2960 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2961 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2962
2963 break;
2964 case DP_TRAINING_PATTERN_1:
2965 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2966 break;
2967 case DP_TRAINING_PATTERN_2:
2968 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2969 break;
2970 case DP_TRAINING_PATTERN_3:
2971 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2972 break;
2973 }
174edf1f 2974 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2975
bc7d38a4 2976 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2977 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2978
2979 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2980 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2981 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2982 break;
2983 case DP_TRAINING_PATTERN_1:
70aff66c 2984 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2985 break;
2986 case DP_TRAINING_PATTERN_2:
70aff66c 2987 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2988 break;
2989 case DP_TRAINING_PATTERN_3:
2990 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2991 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2992 break;
2993 }
2994
2995 } else {
aad3d14d
VS		 2996 if (IS_CHERRYVIEW(dev))
2997 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2998 else
2999 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 3000
3001 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3002 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 3003 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 3004 break;
3005 case DP_TRAINING_PATTERN_1:
70aff66c 3006 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 3007 break;
3008 case DP_TRAINING_PATTERN_2:
70aff66c 3009 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 3010 break;
3011 case DP_TRAINING_PATTERN_3:
aad3d14d
VS		 3012 if (IS_CHERRYVIEW(dev)) {
3013 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
3014 } else {
3015 DRM_ERROR("DP training pattern 3 not supported\n");
3016 *DP |= DP_LINK_TRAIN_PAT_2;
3017 }
47ea7542
PZ		 3018 break;
3019 }
3020 }
3021
70aff66c 3022 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3023 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3024
2cdfe6c8
JN		 3025 buf[0] = dp_train_pat;
3026 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3027 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3028 /* don't write DP_TRAINING_LANEx_SET on disable */
3029 len = 1;
3030 } else {
3031 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3032 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3033 len = intel_dp->lane_count + 1;
47ea7542 3034 }
a4fc5ed6 3035
9d1a1031
JN		 3036 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3037 buf, len);
2cdfe6c8
JN		 3038
3039 return ret == len;
a4fc5ed6
KP		 3040}
3041
70aff66c
JN		 3042static bool
3043intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3044 uint8_t dp_train_pat)
3045{
953d22e8 3046 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3047 intel_dp_set_signal_levels(intel_dp, DP);
3048 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3049}
3050
3051static bool
3052intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3053 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3054{
3055 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3056 struct drm_device *dev = intel_dig_port->base.base.dev;
3057 struct drm_i915_private *dev_priv = dev->dev_private;
3058 int ret;
3059
3060 intel_get_adjust_train(intel_dp, link_status);
3061 intel_dp_set_signal_levels(intel_dp, DP);
3062
3063 I915_WRITE(intel_dp->output_reg, *DP);
3064 POSTING_READ(intel_dp->output_reg);
3065
9d1a1031
JN		 3066 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3067 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3068
3069 return ret == intel_dp->lane_count;
3070}
3071
3ab9c637
ID		 3072static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3073{
3074 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3075 struct drm_device *dev = intel_dig_port->base.base.dev;
3076 struct drm_i915_private *dev_priv = dev->dev_private;
3077 enum port port = intel_dig_port->port;
3078 uint32_t val;
3079
3080 if (!HAS_DDI(dev))
3081 return;
3082
3083 val = I915_READ(DP_TP_CTL(port));
3084 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3085 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3086 I915_WRITE(DP_TP_CTL(port), val);
3087
3088 /*
3089 * On PORT_A we can have only eDP in SST mode. There the only reason
3090 * we need to set idle transmission mode is to work around a HW issue
3091 * where we enable the pipe while not in idle link-training mode.
3092 * In this case there is requirement to wait for a minimum number of
3093 * idle patterns to be sent.
3094 */
3095 if (port == PORT_A)
3096 return;
3097
3098 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3099 1))
3100 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3101}
3102
33a34e4e 3103/* Enable corresponding port and start training pattern 1 */
c19b0669 3104void
33a34e4e 3105intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3106{
da63a9f2 3107 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3108 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3109 int i;
3110 uint8_t voltage;
cdb0e95b 3111 int voltage_tries, loop_tries;
ea5b213a 3112 uint32_t DP = intel_dp->DP;
6aba5b6c 3113 uint8_t link_config[2];
a4fc5ed6 3114
affa9354 3115 if (HAS_DDI(dev))
c19b0669
PZ		 3116 intel_ddi_prepare_link_retrain(encoder);
3117
3cf2efb1 3118 /* Write the link configuration data */
6aba5b6c
JN		 3119 link_config[0] = intel_dp->link_bw;
3120 link_config[1] = intel_dp->lane_count;
3121 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3122 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3123 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3124
3125 link_config[0] = 0;
3126 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3127 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3128
3129 DP |= DP_PORT_EN;
1a2eb460 3130
70aff66c
JN		 3131 /* clock recovery */
3132 if (!intel_dp_reset_link_train(intel_dp, &DP,
3133 DP_TRAINING_PATTERN_1 |
3134 DP_LINK_SCRAMBLING_DISABLE)) {
3135 DRM_ERROR("failed to enable link training\n");
3136 return;
3137 }
3138
a4fc5ed6 3139 voltage = 0xff;
cdb0e95b
KP		 3140 voltage_tries = 0;
3141 loop_tries = 0;
a4fc5ed6 3142 for (;;) {
70aff66c 3143 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3144
a7c9655f 3145 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3146 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3147 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3148 break;
93f62dad 3149 }
a4fc5ed6 3150
01916270 3151 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3152 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3153 break;
3154 }
3155
3156 /* Check to see if we've tried the max voltage */
3157 for (i = 0; i < intel_dp->lane_count; i++)
3158 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3159 break;
3b4f819d 3160 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3161 ++loop_tries;
3162 if (loop_tries == 5) {
3def84b3 3163 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3164 break;
3165 }
70aff66c
JN		 3166 intel_dp_reset_link_train(intel_dp, &DP,
3167 DP_TRAINING_PATTERN_1 |
3168 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3169 voltage_tries = 0;
3170 continue;
3171 }
a4fc5ed6 3172
3cf2efb1 3173 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3174 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3175 ++voltage_tries;
b06fbda3 3176 if (voltage_tries == 5) {
3def84b3 3177 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3178 break;
3179 }
3180 } else
3181 voltage_tries = 0;
3182 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3183
70aff66c
JN		 3184 /* Update training set as requested by target */
3185 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3186 DRM_ERROR("failed to update link training\n");
3187 break;
3188 }
a4fc5ed6
KP		 3189 }
3190
33a34e4e
JB		 3191 intel_dp->DP = DP;
3192}
3193
c19b0669 3194void
33a34e4e
JB		 3195intel_dp_complete_link_train(struct intel_dp *intel_dp)
3196{
33a34e4e 3197 bool channel_eq = false;
37f80975 3198 int tries, cr_tries;
33a34e4e 3199 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3200 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3201
3202 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3203 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3204 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3205
a4fc5ed6 3206 /* channel equalization */
70aff66c 3207 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3208 training_pattern |
70aff66c
JN		 3209 DP_LINK_SCRAMBLING_DISABLE)) {
3210 DRM_ERROR("failed to start channel equalization\n");
3211 return;
3212 }
3213
a4fc5ed6 3214 tries = 0;
37f80975 3215 cr_tries = 0;
a4fc5ed6
KP		 3216 channel_eq = false;
3217 for (;;) {
70aff66c 3218 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3219
37f80975
JB		 3220 if (cr_tries > 5) {
3221 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3222 break;
3223 }
3224
a7c9655f 3225 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3226 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3227 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3228 break;
70aff66c 3229 }
a4fc5ed6 3230
37f80975 3231 /* Make sure clock is still ok */
01916270 3232 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3233 intel_dp_start_link_train(intel_dp);
70aff66c 3234 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3235 training_pattern |
70aff66c 3236 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3237 cr_tries++;
3238 continue;
3239 }
3240
1ffdff13 3241 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3242 channel_eq = true;
3243 break;
3244 }
a4fc5ed6 3245
37f80975
JB		 3246 /* Try 5 times, then try clock recovery if that fails */
3247 if (tries > 5) {
3248 intel_dp_link_down(intel_dp);
3249 intel_dp_start_link_train(intel_dp);
70aff66c 3250 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3251 training_pattern |
70aff66c 3252 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3253 tries = 0;
3254 cr_tries++;
3255 continue;
3256 }
a4fc5ed6 3257
70aff66c
JN		 3258 /* Update training set as requested by target */
3259 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3260 DRM_ERROR("failed to update link training\n");
3261 break;
3262 }
3cf2efb1 3263 ++tries;
869184a6 3264 }
3cf2efb1 3265
3ab9c637
ID		 3266 intel_dp_set_idle_link_train(intel_dp);
3267
3268 intel_dp->DP = DP;
3269
d6c0d722 3270 if (channel_eq)
07f42258 3271 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3272
3ab9c637
ID		 3273}
3274
3275void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3276{
70aff66c 3277 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3278 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3279}
3280
3281static void
ea5b213a 3282intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3283{
da63a9f2 3284 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3285 enum port port = intel_dig_port->port;
da63a9f2 3286 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3287 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3288 struct intel_crtc *intel_crtc =
3289 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3290 uint32_t DP = intel_dp->DP;
a4fc5ed6 3291
bc76e320 3292 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3293 return;
3294
0c33d8d7 3295 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3296 return;
3297
28c97730 3298 DRM_DEBUG_KMS("\n");
32f9d658 3299
bc7d38a4 3300 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3301 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3302 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3303 } else {
aad3d14d
VS		 3304 if (IS_CHERRYVIEW(dev))
3305 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3306 else
3307 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3308 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3309 }
fe255d00 3310 POSTING_READ(intel_dp->output_reg);
5eb08b69 3311
493a7081 3312 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3313 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3314 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3315
5bddd17f
EA		 3316 /* Hardware workaround: leaving our transcoder select
3317 * set to transcoder B while it's off will prevent the
3318 * corresponding HDMI output on transcoder A.
3319 *
3320 * Combine this with another hardware workaround:
3321 * transcoder select bit can only be cleared while the
3322 * port is enabled.
3323 */
3324 DP &= ~DP_PIPEB_SELECT;
3325 I915_WRITE(intel_dp->output_reg, DP);
3326
3327 /* Changes to enable or select take place the vblank
3328 * after being written.
3329 */
ff50afe9
DV		 3330 if (WARN_ON(crtc == NULL)) {
3331 /* We should never try to disable a port without a crtc
3332 * attached. For paranoia keep the code around for a
3333 * bit. */
31acbcc4
CW		 3334 POSTING_READ(intel_dp->output_reg);
3335 msleep(50);
3336 } else
ab527efc 3337 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3338 }
3339
832afda6 3340 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3341 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3342 POSTING_READ(intel_dp->output_reg);
f01eca2e 3343 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3344}
3345
26d61aad
KP		 3346static bool
3347intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3348{
a031d709
RV		 3349 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3350 struct drm_device *dev = dig_port->base.base.dev;
3351 struct drm_i915_private *dev_priv = dev->dev_private;
3352
577c7a50
DL		 3353 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3354
9d1a1031
JN		 3355 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3356 sizeof(intel_dp->dpcd)) < 0)
edb39244 3357 return false; /* aux transfer failed */
92fd8fd1 3358
577c7a50
DL		 3359 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3360 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3361 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3362
edb39244
AJ		 3363 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3364 return false; /* DPCD not present */
3365
2293bb5c
SK		 3366 /* Check if the panel supports PSR */
3367 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3368 if (is_edp(intel_dp)) {
9d1a1031
JN		 3369 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3370 intel_dp->psr_dpcd,
3371 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3372 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3373 dev_priv->psr.sink_support = true;
50003939 3374 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3375 }
50003939
JN		 3376 }
3377
06ea66b6
TP		 3378 /* Training Pattern 3 support */
3379 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3380 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3381 intel_dp->use_tps3 = true;
3382 DRM_DEBUG_KMS("Displayport TPS3 supported");
3383 } else
3384 intel_dp->use_tps3 = false;
3385
edb39244
AJ		 3386 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3387 DP_DWN_STRM_PORT_PRESENT))
3388 return true; /* native DP sink */
3389
3390 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3391 return true; /* no per-port downstream info */
3392
9d1a1031
JN		 3393 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3394 intel_dp->downstream_ports,
3395 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3396 return false; /* downstream port status fetch failed */
3397
3398 return true;
92fd8fd1
KP		 3399}
3400
0d198328
AJ		 3401static void
3402intel_dp_probe_oui(struct intel_dp *intel_dp)
3403{
3404 u8 buf[3];
3405
3406 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3407 return;
3408
24f3e092 3409 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3410
9d1a1031 3411 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3412 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3413 buf[0], buf[1], buf[2]);
3414
9d1a1031 3415 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3416 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3417 buf[0], buf[1], buf[2]);
351cfc34 3418
4be73780 3419 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3420}
3421
0e32b39c
DA		 3422static bool
3423intel_dp_probe_mst(struct intel_dp *intel_dp)
3424{
3425 u8 buf[1];
3426
3427 if (!intel_dp->can_mst)
3428 return false;
3429
3430 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3431 return false;
3432
3433 _edp_panel_vdd_on(intel_dp);
3434 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3435 if (buf[0] & DP_MST_CAP) {
3436 DRM_DEBUG_KMS("Sink is MST capable\n");
3437 intel_dp->is_mst = true;
3438 } else {
3439 DRM_DEBUG_KMS("Sink is not MST capable\n");
3440 intel_dp->is_mst = false;
3441 }
3442 }
3443 edp_panel_vdd_off(intel_dp, false);
3444
3445 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3446 return intel_dp->is_mst;
3447}
3448
d2e216d0
RV		 3449int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3450{
3451 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3452 struct drm_device *dev = intel_dig_port->base.base.dev;
3453 struct intel_crtc *intel_crtc =
3454 to_intel_crtc(intel_dig_port->base.base.crtc);
3455 u8 buf[1];
3456
9d1a1031 3457 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3458 return -EAGAIN;
3459
3460 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3461 return -ENOTTY;
3462
9d1a1031
JN		 3463 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3464 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3465 return -EAGAIN;
3466
3467 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3468 intel_wait_for_vblank(dev, intel_crtc->pipe);
3469 intel_wait_for_vblank(dev, intel_crtc->pipe);
3470
9d1a1031 3471 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3472 return -EAGAIN;
3473
9d1a1031 3474 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3475 return 0;
3476}
3477
a60f0e38
JB		 3478static bool
3479intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3480{
9d1a1031
JN		 3481 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3482 DP_DEVICE_SERVICE_IRQ_VECTOR,
3483 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3484}
3485
0e32b39c
DA		 3486static bool
3487intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3488{
3489 int ret;
3490
3491 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3492 DP_SINK_COUNT_ESI,
3493 sink_irq_vector, 14);
3494 if (ret != 14)
3495 return false;
3496
3497 return true;
3498}
3499
a60f0e38
JB		 3500static void
3501intel_dp_handle_test_request(struct intel_dp *intel_dp)
3502{
3503 /* NAK by default */
9d1a1031 3504 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3505}
3506
0e32b39c
DA		 3507static int
3508intel_dp_check_mst_status(struct intel_dp *intel_dp)
3509{
3510 bool bret;
3511
3512 if (intel_dp->is_mst) {
3513 u8 esi[16] = { 0 };
3514 int ret = 0;
3515 int retry;
3516 bool handled;
3517 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3518go_again:
3519 if (bret == true) {
3520
3521 /* check link status - esi[10] = 0x200c */
3522 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3523 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3524 intel_dp_start_link_train(intel_dp);
3525 intel_dp_complete_link_train(intel_dp);
3526 intel_dp_stop_link_train(intel_dp);
3527 }
3528
3529 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3530 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3531
3532 if (handled) {
3533 for (retry = 0; retry < 3; retry++) {
3534 int wret;
3535 wret = drm_dp_dpcd_write(&intel_dp->aux,
3536 DP_SINK_COUNT_ESI+1,
3537 &esi[1], 3);
3538 if (wret == 3) {
3539 break;
3540 }
3541 }
3542
3543 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3544 if (bret == true) {
3545 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3546 goto go_again;
3547 }
3548 } else
3549 ret = 0;
3550
3551 return ret;
3552 } else {
3553 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3554 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3555 intel_dp->is_mst = false;
3556 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3557 /* send a hotplug event */
3558 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3559 }
3560 }
3561 return -EINVAL;
3562}
3563
a4fc5ed6
KP		 3564/*
3565 * According to DP spec
3566 * 5.1.2:
3567 * 1. Read DPCD
3568 * 2. Configure link according to Receiver Capabilities
3569 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3570 * 4. Check link status on receipt of hot-plug interrupt
3571 */
00c09d70 3572void
ea5b213a 3573intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3574{
5b215bcf 3575 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3576 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3577 u8 sink_irq_vector;
93f62dad 3578 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3579
5b215bcf
DA		 3580 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3581
da63a9f2 3582 if (!intel_encoder->connectors_active)
d2b996ac 3583 return;
59cd09e1 3584
da63a9f2 3585 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3586 return;
3587
1a125d8a
ID		 3588 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3589 return;
3590
92fd8fd1 3591 /* Try to read receiver status if the link appears to be up */
93f62dad 3592 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3593 return;
3594 }
3595
92fd8fd1 3596 /* Now read the DPCD to see if it's actually running */
26d61aad 3597 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3598 return;
3599 }
3600
a60f0e38
JB		 3601 /* Try to read the source of the interrupt */
3602 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3603 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3604 /* Clear interrupt source */
9d1a1031
JN		 3605 drm_dp_dpcd_writeb(&intel_dp->aux,
3606 DP_DEVICE_SERVICE_IRQ_VECTOR,
3607 sink_irq_vector);
a60f0e38
JB		 3608
3609 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3610 intel_dp_handle_test_request(intel_dp);
3611 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3612 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3613 }
3614
1ffdff13 3615 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3616 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3617 intel_encoder->base.name);
33a34e4e
JB		 3618 intel_dp_start_link_train(intel_dp);
3619 intel_dp_complete_link_train(intel_dp);
3ab9c637 3620 intel_dp_stop_link_train(intel_dp);
33a34e4e 3621 }
a4fc5ed6 3622}
a4fc5ed6 3623
caf9ab24 3624/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3625static enum drm_connector_status
26d61aad 3626intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3627{
caf9ab24 3628 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3629 uint8_t type;
3630
3631 if (!intel_dp_get_dpcd(intel_dp))
3632 return connector_status_disconnected;
3633
3634 /* if there's no downstream port, we're done */
3635 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3636 return connector_status_connected;
caf9ab24
AJ		 3637
3638 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3639 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3640 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3641 uint8_t reg;
9d1a1031
JN		 3642
3643 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3644 &reg, 1) < 0)
caf9ab24 3645 return connector_status_unknown;
9d1a1031 3646
23235177
AJ		 3647 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3648 : connector_status_disconnected;
caf9ab24
AJ		 3649 }
3650
3651 /* If no HPD, poke DDC gently */
0b99836f 3652 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3653 return connector_status_connected;
caf9ab24
AJ		 3654
3655 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3656 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3657 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3658 if (type == DP_DS_PORT_TYPE_VGA ||
3659 type == DP_DS_PORT_TYPE_NON_EDID)
3660 return connector_status_unknown;
3661 } else {
3662 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3663 DP_DWN_STRM_PORT_TYPE_MASK;
3664 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3665 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3666 return connector_status_unknown;
3667 }
caf9ab24
AJ		 3668
3669 /* Anything else is out of spec, warn and ignore */
3670 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3671 return connector_status_disconnected;
71ba9000
AJ		 3672}
3673
5eb08b69 3674static enum drm_connector_status
a9756bb5 3675ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3676{
30add22d 3677 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3678 struct drm_i915_private *dev_priv = dev->dev_private;
3679 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3680 enum drm_connector_status status;
3681
fe16d949
CW		 3682 /* Can't disconnect eDP, but you can close the lid... */
3683 if (is_edp(intel_dp)) {
30add22d 3684 status = intel_panel_detect(dev);
fe16d949
CW		 3685 if (status == connector_status_unknown)
3686 status = connector_status_connected;
3687 return status;
3688 }
01cb9ea6 3689
1b469639
DL		 3690 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3691 return connector_status_disconnected;
3692
26d61aad 3693 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3694}
3695
a4fc5ed6 3696static enum drm_connector_status
a9756bb5 3697g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3698{
30add22d 3699 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3700 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3701 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3702 uint32_t bit;
5eb08b69 3703
35aad75f
JB		 3704 /* Can't disconnect eDP, but you can close the lid... */
3705 if (is_edp(intel_dp)) {
3706 enum drm_connector_status status;
3707
3708 status = intel_panel_detect(dev);
3709 if (status == connector_status_unknown)
3710 status = connector_status_connected;
3711 return status;
3712 }
3713
232a6ee9
TP		 3714 if (IS_VALLEYVIEW(dev)) {
3715 switch (intel_dig_port->port) {
3716 case PORT_B:
3717 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3718 break;
3719 case PORT_C:
3720 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3721 break;
3722 case PORT_D:
3723 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3724 break;
3725 default:
3726 return connector_status_unknown;
3727 }
3728 } else {
3729 switch (intel_dig_port->port) {
3730 case PORT_B:
3731 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3732 break;
3733 case PORT_C:
3734 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3735 break;
3736 case PORT_D:
3737 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3738 break;
3739 default:
3740 return connector_status_unknown;
3741 }
a4fc5ed6
KP		 3742 }
3743
10f76a38 3744 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3745 return connector_status_disconnected;
3746
26d61aad 3747 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3748}
3749
8c241fef
KP		 3750static struct edid *
3751intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3752{
9cd300e0 3753 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3754
9cd300e0
JN		 3755 /* use cached edid if we have one */
3756 if (intel_connector->edid) {
9cd300e0
JN		 3757 /* invalid edid */
3758 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3759 return NULL;
3760
55e9edeb 3761 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3762 }
8c241fef 3763
9cd300e0 3764 return drm_get_edid(connector, adapter);
8c241fef
KP		 3765}
3766
3767static int
3768intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3769{
9cd300e0 3770 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3771
9cd300e0
JN		 3772 /* use cached edid if we have one */
3773 if (intel_connector->edid) {
3774 /* invalid edid */
3775 if (IS_ERR(intel_connector->edid))
3776 return 0;
3777
3778 return intel_connector_update_modes(connector,
3779 intel_connector->edid);
d6f24d0f
JB		 3780 }
3781
9cd300e0 3782 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3783}
3784
a9756bb5
ZW		 3785static enum drm_connector_status
3786intel_dp_detect(struct drm_connector *connector, bool force)
3787{
3788 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3789 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3790 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3791 struct drm_device *dev = connector->dev;
c8c8fb33 3792 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3793 enum drm_connector_status status;
671dedd2 3794 enum intel_display_power_domain power_domain;
a9756bb5 3795 struct edid *edid = NULL;
0e32b39c 3796 bool ret;
a9756bb5 3797
671dedd2
ID		 3798 power_domain = intel_display_port_power_domain(intel_encoder);
3799 intel_display_power_get(dev_priv, power_domain);
3800
164c8598 3801 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 3802 connector->base.id, connector->name);
164c8598 3803
0e32b39c
DA		 3804 if (intel_dp->is_mst) {
3805 /* MST devices are disconnected from a monitor POV */
3806 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3807 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3808 status = connector_status_disconnected;
3809 goto out;
3810 }
3811
a9756bb5
ZW		 3812 intel_dp->has_audio = false;
3813
3814 if (HAS_PCH_SPLIT(dev))
3815 status = ironlake_dp_detect(intel_dp);
3816 else
3817 status = g4x_dp_detect(intel_dp);
1b9be9d0 3818
a9756bb5 3819 if (status != connector_status_connected)
c8c8fb33 3820 goto out;
a9756bb5 3821
0d198328
AJ		 3822 intel_dp_probe_oui(intel_dp);
3823
0e32b39c
DA		 3824 ret = intel_dp_probe_mst(intel_dp);
3825 if (ret) {
3826 /* if we are in MST mode then this connector
3827 won't appear connected or have anything with EDID on it */
3828 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3829 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3830 status = connector_status_disconnected;
3831 goto out;
3832 }
3833
c3e5f67b
DV		 3834 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3835 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3836 } else {
0b99836f 3837 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3838 if (edid) {
3839 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3840 kfree(edid);
3841 }
a9756bb5
ZW		 3842 }
3843
d63885da
PZ		 3844 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3845 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3846 status = connector_status_connected;
3847
3848out:
671dedd2 3849 intel_display_power_put(dev_priv, power_domain);
c8c8fb33 3850 return status;
a4fc5ed6
KP		 3851}
3852
3853static int intel_dp_get_modes(struct drm_connector *connector)
3854{
df0e9248 3855 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3856 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3857 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3858 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3859 struct drm_device *dev = connector->dev;
671dedd2
ID		 3860 struct drm_i915_private *dev_priv = dev->dev_private;
3861 enum intel_display_power_domain power_domain;
32f9d658 3862 int ret;
a4fc5ed6
KP		 3863
3864 /* We should parse the EDID data and find out if it has an audio sink
3865 */
3866
671dedd2
ID		 3867 power_domain = intel_display_port_power_domain(intel_encoder);
3868 intel_display_power_get(dev_priv, power_domain);
3869
0b99836f 3870 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3871 intel_display_power_put(dev_priv, power_domain);
f8779fda 3872 if (ret)
32f9d658
ZW		 3873 return ret;
3874
f8779fda 3875 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3876 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3877 struct drm_display_mode *mode;
dd06f90e
JN		 3878 mode = drm_mode_duplicate(dev,
3879 intel_connector->panel.fixed_mode);
f8779fda 3880 if (mode) {
32f9d658
ZW		 3881 drm_mode_probed_add(connector, mode);
3882 return 1;
3883 }
3884 }
3885 return 0;
a4fc5ed6
KP		 3886}
3887
1aad7ac0
CW		 3888static bool
3889intel_dp_detect_audio(struct drm_connector *connector)
3890{
3891 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3892 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3893 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3894 struct drm_device *dev = connector->dev;
3895 struct drm_i915_private *dev_priv = dev->dev_private;
3896 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3897 struct edid *edid;
3898 bool has_audio = false;
3899
671dedd2
ID		 3900 power_domain = intel_display_port_power_domain(intel_encoder);
3901 intel_display_power_get(dev_priv, power_domain);
3902
0b99836f 3903 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3904 if (edid) {
3905 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3906 kfree(edid);
3907 }
3908
671dedd2
ID		 3909 intel_display_power_put(dev_priv, power_domain);
3910
1aad7ac0
CW		 3911 return has_audio;
3912}
3913
f684960e
CW		 3914static int
3915intel_dp_set_property(struct drm_connector *connector,
3916 struct drm_property *property,
3917 uint64_t val)
3918{
e953fd7b 3919 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3920 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3921 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3922 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3923 int ret;
3924
662595df 3925 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3926 if (ret)
3927 return ret;
3928
3f43c48d 3929 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3930 int i = val;
3931 bool has_audio;
3932
3933 if (i == intel_dp->force_audio)
f684960e
CW		 3934 return 0;
3935
1aad7ac0 3936 intel_dp->force_audio = i;
f684960e 3937
c3e5f67b 3938 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3939 has_audio = intel_dp_detect_audio(connector);
3940 else
c3e5f67b 3941 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3942
3943 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3944 return 0;
3945
1aad7ac0 3946 intel_dp->has_audio = has_audio;
f684960e
CW		 3947 goto done;
3948 }
3949
e953fd7b 3950 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3951 bool old_auto = intel_dp->color_range_auto;
3952 uint32_t old_range = intel_dp->color_range;
3953
55bc60db
VS		 3954 switch (val) {
3955 case INTEL_BROADCAST_RGB_AUTO:
3956 intel_dp->color_range_auto = true;
3957 break;
3958 case INTEL_BROADCAST_RGB_FULL:
3959 intel_dp->color_range_auto = false;
3960 intel_dp->color_range = 0;
3961 break;
3962 case INTEL_BROADCAST_RGB_LIMITED:
3963 intel_dp->color_range_auto = false;
3964 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3965 break;
3966 default:
3967 return -EINVAL;
3968 }
ae4edb80
DV		 3969
3970 if (old_auto == intel_dp->color_range_auto &&
3971 old_range == intel_dp->color_range)
3972 return 0;
3973
e953fd7b
CW		 3974 goto done;
3975 }
3976
53b41837
YN		 3977 if (is_edp(intel_dp) &&
3978 property == connector->dev->mode_config.scaling_mode_property) {
3979 if (val == DRM_MODE_SCALE_NONE) {
3980 DRM_DEBUG_KMS("no scaling not supported\n");
3981 return -EINVAL;
3982 }
3983
3984 if (intel_connector->panel.fitting_mode == val) {
3985 /* the eDP scaling property is not changed */
3986 return 0;
3987 }
3988 intel_connector->panel.fitting_mode = val;
3989
3990 goto done;
3991 }
3992
f684960e
CW		 3993 return -EINVAL;
3994
3995done:
c0c36b94
CW		 3996 if (intel_encoder->base.crtc)
3997 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3998
3999 return 0;
4000}
4001
a4fc5ed6 4002static void
73845adf 4003intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4004{
1d508706 4005 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4006
9cd300e0
JN		 4007 if (!IS_ERR_OR_NULL(intel_connector->edid))
4008 kfree(intel_connector->edid);
4009
acd8db10
PZ		 4010 /* Can't call is_edp() since the encoder may have been destroyed
4011 * already. */
4012 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4013 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4014
a4fc5ed6 4015 drm_connector_cleanup(connector);
55f78c43 4016 kfree(connector);
a4fc5ed6
KP		 4017}
4018
00c09d70 4019void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4020{
da63a9f2
PZ		 4021 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4022 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 4023 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 4024
4f71d0cb 4025 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4026 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4027 drm_encoder_cleanup(encoder);
bd943159
KP		 4028 if (is_edp(intel_dp)) {
4029 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 4030 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 4031 edp_panel_vdd_off_sync(intel_dp);
51fd371b 4032 drm_modeset_unlock(&dev->mode_config.connection_mutex);
01527b31
CT		 4033 if (intel_dp->edp_notifier.notifier_call) {
4034 unregister_reboot_notifier(&intel_dp->edp_notifier);
4035 intel_dp->edp_notifier.notifier_call = NULL;
4036 }
bd943159 4037 }
da63a9f2 4038 kfree(intel_dig_port);
24d05927
DV		 4039}
4040
07f9cd0b
ID		 4041static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4042{
4043 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4044
4045 if (!is_edp(intel_dp))
4046 return;
4047
4048 edp_panel_vdd_off_sync(intel_dp);
4049}
4050
6d93c0c4
ID		 4051static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4052{
4053 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4054}
4055
a4fc5ed6 4056static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4057 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 4058 .detect = intel_dp_detect,
4059 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4060 .set_property = intel_dp_set_property,
73845adf 4061 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4062};
4063
4064static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4065 .get_modes = intel_dp_get_modes,
4066 .mode_valid = intel_dp_mode_valid,
df0e9248 4067 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4068};
4069
a4fc5ed6 4070static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4071 .reset = intel_dp_encoder_reset,
24d05927 4072 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4073};
4074
0e32b39c 4075void
21d40d37 4076intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4077{
0e32b39c 4078 return;
c8110e52 4079}
6207937d 4080
13cf5504
DA		 4081bool
4082intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4083{
4084 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4085 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4086 struct drm_device *dev = intel_dig_port->base.base.dev;
4087 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4088 enum intel_display_power_domain power_domain;
4089 bool ret = true;
4090
0e32b39c
DA		 4091 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4092 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4093
26fbb774
VS		 4094 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4095 port_name(intel_dig_port->port),
0e32b39c 4096 long_hpd ? "long" : "short");
13cf5504 4097
1c767b33
ID		 4098 power_domain = intel_display_port_power_domain(intel_encoder);
4099 intel_display_power_get(dev_priv, power_domain);
4100
0e32b39c
DA		 4101 if (long_hpd) {
4102 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4103 goto mst_fail;
4104
4105 if (!intel_dp_get_dpcd(intel_dp)) {
4106 goto mst_fail;
4107 }
4108
4109 intel_dp_probe_oui(intel_dp);
4110
4111 if (!intel_dp_probe_mst(intel_dp))
4112 goto mst_fail;
4113
4114 } else {
4115 if (intel_dp->is_mst) {
1c767b33 4116 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4117 goto mst_fail;
4118 }
4119
4120 if (!intel_dp->is_mst) {
4121 /*
4122 * we'll check the link status via the normal hot plug path later -
4123 * but for short hpds we should check it now
4124 */
5b215bcf 4125 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4126 intel_dp_check_link_status(intel_dp);
5b215bcf 4127 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4128 }
4129 }
1c767b33
ID		 4130 ret = false;
4131 goto put_power;
0e32b39c
DA		 4132mst_fail:
4133 /* if we were in MST mode, and device is not there get out of MST mode */
4134 if (intel_dp->is_mst) {
4135 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4136 intel_dp->is_mst = false;
4137 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4138 }
1c767b33
ID		 4139put_power:
4140 intel_display_power_put(dev_priv, power_domain);
4141
4142 return ret;
13cf5504
DA		 4143}
4144
e3421a18
ZW		 4145/* Return which DP Port should be selected for Transcoder DP control */
4146int
0206e353 4147intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4148{
4149 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4150 struct intel_encoder *intel_encoder;
4151 struct intel_dp *intel_dp;
e3421a18 4152
fa90ecef
PZ		 4153 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4154 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4155
fa90ecef
PZ		 4156 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4157 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4158 return intel_dp->output_reg;
e3421a18 4159 }
ea5b213a 4160
e3421a18
ZW		 4161 return -1;
4162}
4163
36e83a18 4164/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4165bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4166{
4167 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4168 union child_device_config *p_child;
36e83a18 4169 int i;
5d8a7752
VS		 4170 static const short port_mapping[] = {
4171 [PORT_B] = PORT_IDPB,
4172 [PORT_C] = PORT_IDPC,
4173 [PORT_D] = PORT_IDPD,
4174 };
36e83a18 4175
3b32a35b
VS		 4176 if (port == PORT_A)
4177 return true;
4178
41aa3448 4179 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4180 return false;
4181
41aa3448
RV		 4182 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4183 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4184
5d8a7752 4185 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4186 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4187 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4188 return true;
4189 }
4190 return false;
4191}
4192
0e32b39c 4193void
f684960e
CW		 4194intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4195{
53b41837
YN		 4196 struct intel_connector *intel_connector = to_intel_connector(connector);
4197
3f43c48d 4198 intel_attach_force_audio_property(connector);
e953fd7b 4199 intel_attach_broadcast_rgb_property(connector);
55bc60db 4200 intel_dp->color_range_auto = true;
53b41837
YN		 4201
4202 if (is_edp(intel_dp)) {
4203 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4204 drm_object_attach_property(
4205 &connector->base,
53b41837 4206 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4207 DRM_MODE_SCALE_ASPECT);
4208 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4209 }
f684960e
CW		 4210}
4211
dada1a9f
ID		 4212static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4213{
4214 intel_dp->last_power_cycle = jiffies;
4215 intel_dp->last_power_on = jiffies;
4216 intel_dp->last_backlight_off = jiffies;
4217}
4218
67a54566
DV		 4219static void
4220intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 4221 struct intel_dp *intel_dp,
4222 struct edp_power_seq *out)
67a54566
DV		 4223{
4224 struct drm_i915_private *dev_priv = dev->dev_private;
4225 struct edp_power_seq cur, vbt, spec, final;
4226 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4227 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 4228
4229 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4230 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4231 pp_on_reg = PCH_PP_ON_DELAYS;
4232 pp_off_reg = PCH_PP_OFF_DELAYS;
4233 pp_div_reg = PCH_PP_DIVISOR;
4234 } else {
bf13e81b
JN		 4235 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4236
4237 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4238 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4239 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4240 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4241 }
67a54566
DV		 4242
4243 /* Workaround: Need to write PP_CONTROL with the unlock key as
4244 * the very first thing. */
453c5420 4245 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4246 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4247
453c5420
JB		 4248 pp_on = I915_READ(pp_on_reg);
4249 pp_off = I915_READ(pp_off_reg);
4250 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4251
4252 /* Pull timing values out of registers */
4253 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4254 PANEL_POWER_UP_DELAY_SHIFT;
4255
4256 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4257 PANEL_LIGHT_ON_DELAY_SHIFT;
4258
4259 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4260 PANEL_LIGHT_OFF_DELAY_SHIFT;
4261
4262 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4263 PANEL_POWER_DOWN_DELAY_SHIFT;
4264
4265 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4266 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4267
4268 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4269 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4270
41aa3448 4271 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4272
4273 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4274 * our hw here, which are all in 100usec. */
4275 spec.t1_t3 = 210 * 10;
4276 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4277 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4278 spec.t10 = 500 * 10;
4279 /* This one is special and actually in units of 100ms, but zero
4280 * based in the hw (so we need to add 100 ms). But the sw vbt
4281 * table multiplies it with 1000 to make it in units of 100usec,
4282 * too. */
4283 spec.t11_t12 = (510 + 100) * 10;
4284
4285 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4286 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4287
4288 /* Use the max of the register settings and vbt. If both are
4289 * unset, fall back to the spec limits. */
4290#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4291 spec.field : \
4292 max(cur.field, vbt.field))
4293 assign_final(t1_t3);
4294 assign_final(t8);
4295 assign_final(t9);
4296 assign_final(t10);
4297 assign_final(t11_t12);
4298#undef assign_final
4299
4300#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4301 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4302 intel_dp->backlight_on_delay = get_delay(t8);
4303 intel_dp->backlight_off_delay = get_delay(t9);
4304 intel_dp->panel_power_down_delay = get_delay(t10);
4305 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4306#undef get_delay
4307
f30d26e4
JN		 4308 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4309 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4310 intel_dp->panel_power_cycle_delay);
4311
4312 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4313 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4314
4315 if (out)
4316 *out = final;
4317}
4318
4319static void
4320intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4321 struct intel_dp *intel_dp,
4322 struct edp_power_seq *seq)
4323{
4324 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4325 u32 pp_on, pp_off, pp_div, port_sel = 0;
4326 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4327 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4328 enum port port = dp_to_dig_port(intel_dp)->port;
453c5420
JB		 4329
4330 if (HAS_PCH_SPLIT(dev)) {
4331 pp_on_reg = PCH_PP_ON_DELAYS;
4332 pp_off_reg = PCH_PP_OFF_DELAYS;
4333 pp_div_reg = PCH_PP_DIVISOR;
4334 } else {
bf13e81b
JN		 4335 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4336
4337 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4338 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4339 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4340 }
4341
b2f19d1a
PZ		 4342 /*
4343 * And finally store the new values in the power sequencer. The
4344 * backlight delays are set to 1 because we do manual waits on them. For
4345 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4346 * we'll end up waiting for the backlight off delay twice: once when we
4347 * do the manual sleep, and once when we disable the panel and wait for
4348 * the PP_STATUS bit to become zero.
4349 */
f30d26e4 4350 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4351 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4352 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4353 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4354 /* Compute the divisor for the pp clock, simply match the Bspec
4355 * formula. */
453c5420 4356 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4357 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4358 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4359
4360 /* Haswell doesn't have any port selection bits for the panel
4361 * power sequencer any more. */
bc7d38a4 4362 if (IS_VALLEYVIEW(dev)) {
ad933b56 4363 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4364 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4365 if (port == PORT_A)
a24c144c 4366 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4367 else
a24c144c 4368 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4369 }
4370
453c5420
JB		 4371 pp_on |= port_sel;
4372
4373 I915_WRITE(pp_on_reg, pp_on);
4374 I915_WRITE(pp_off_reg, pp_off);
4375 I915_WRITE(pp_div_reg, pp_div);
67a54566 4376
67a54566 4377 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4378 I915_READ(pp_on_reg),
4379 I915_READ(pp_off_reg),
4380 I915_READ(pp_div_reg));
f684960e
CW		 4381}
4382
439d7ac0
PB		 4383void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4384{
4385 struct drm_i915_private *dev_priv = dev->dev_private;
4386 struct intel_encoder *encoder;
4387 struct intel_dp *intel_dp = NULL;
4388 struct intel_crtc_config *config = NULL;
4389 struct intel_crtc *intel_crtc = NULL;
4390 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4391 u32 reg, val;
4392 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4393
4394 if (refresh_rate <= 0) {
4395 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4396 return;
4397 }
4398
4399 if (intel_connector == NULL) {
4400 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4401 return;
4402 }
4403
1fcc9d1c
DV		 4404 /*
4405 * FIXME: This needs proper synchronization with psr state. But really
4406 * hard to tell without seeing the user of this function of this code.
4407 * Check locking and ordering once that lands.
4408 */
439d7ac0
PB		 4409 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4410 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4411 return;
4412 }
4413
4414 encoder = intel_attached_encoder(&intel_connector->base);
4415 intel_dp = enc_to_intel_dp(&encoder->base);
4416 intel_crtc = encoder->new_crtc;
4417
4418 if (!intel_crtc) {
4419 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4420 return;
4421 }
4422
4423 config = &intel_crtc->config;
4424
4425 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4426 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4427 return;
4428 }
4429
4430 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4431 index = DRRS_LOW_RR;
4432
4433 if (index == intel_dp->drrs_state.refresh_rate_type) {
4434 DRM_DEBUG_KMS(
4435 "DRRS requested for previously set RR...ignoring\n");
4436 return;
4437 }
4438
4439 if (!intel_crtc->active) {
4440 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4441 return;
4442 }
4443
4444 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4445 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4446 val = I915_READ(reg);
4447 if (index > DRRS_HIGH_RR) {
4448 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4449 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4450 } else {
4451 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4452 }
4453 I915_WRITE(reg, val);
4454 }
4455
4456 /*
4457 * mutex taken to ensure that there is no race between differnt
4458 * drrs calls trying to update refresh rate. This scenario may occur
4459 * in future when idleness detection based DRRS in kernel and
4460 * possible calls from user space to set differnt RR are made.
4461 */
4462
4463 mutex_lock(&intel_dp->drrs_state.mutex);
4464
4465 intel_dp->drrs_state.refresh_rate_type = index;
4466
4467 mutex_unlock(&intel_dp->drrs_state.mutex);
4468
4469 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4470}
4471
4f9db5b5
PB		 4472static struct drm_display_mode *
4473intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4474 struct intel_connector *intel_connector,
4475 struct drm_display_mode *fixed_mode)
4476{
4477 struct drm_connector *connector = &intel_connector->base;
4478 struct intel_dp *intel_dp = &intel_dig_port->dp;
4479 struct drm_device *dev = intel_dig_port->base.base.dev;
4480 struct drm_i915_private *dev_priv = dev->dev_private;
4481 struct drm_display_mode *downclock_mode = NULL;
4482
4483 if (INTEL_INFO(dev)->gen <= 6) {
4484 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4485 return NULL;
4486 }
4487
4488 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 4489 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 4490 return NULL;
4491 }
4492
4493 downclock_mode = intel_find_panel_downclock
4494 (dev, fixed_mode, connector);
4495
4496 if (!downclock_mode) {
4079b8d1 4497 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 4498 return NULL;
4499 }
4500
439d7ac0
PB		 4501 dev_priv->drrs.connector = intel_connector;
4502
4503 mutex_init(&intel_dp->drrs_state.mutex);
4504
4f9db5b5
PB		 4505 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4506
4507 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 4508 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 4509 return downclock_mode;
4510}
4511
aba86890
ID		 4512void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4513{
4514 struct drm_device *dev = intel_encoder->base.dev;
4515 struct drm_i915_private *dev_priv = dev->dev_private;
4516 struct intel_dp *intel_dp;
4517 enum intel_display_power_domain power_domain;
4518
4519 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4520 return;
4521
4522 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4523 if (!edp_have_panel_vdd(intel_dp))
4524 return;
4525 /*
4526 * The VDD bit needs a power domain reference, so if the bit is
4527 * already enabled when we boot or resume, grab this reference and
4528 * schedule a vdd off, so we don't hold on to the reference
4529 * indefinitely.
4530 */
4531 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4532 power_domain = intel_display_port_power_domain(intel_encoder);
4533 intel_display_power_get(dev_priv, power_domain);
4534
4535 edp_panel_vdd_schedule_off(intel_dp);
4536}
4537
ed92f0b2 4538static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4539 struct intel_connector *intel_connector,
4540 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4541{
4542 struct drm_connector *connector = &intel_connector->base;
4543 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4544 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4545 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4546 struct drm_i915_private *dev_priv = dev->dev_private;
4547 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4548 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4549 bool has_dpcd;
4550 struct drm_display_mode *scan;
4551 struct edid *edid;
4552
4f9db5b5
PB		 4553 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4554
ed92f0b2
PZ		 4555 if (!is_edp(intel_dp))
4556 return true;
4557
aba86890 4558 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 4559
ed92f0b2 4560 /* Cache DPCD and EDID for edp. */
24f3e092 4561 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4562 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 4563 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4564
4565 if (has_dpcd) {
4566 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4567 dev_priv->no_aux_handshake =
4568 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4569 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4570 } else {
4571 /* if this fails, presume the device is a ghost */
4572 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4573 return false;
4574 }
4575
4576 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 4577 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 4578
060c8778 4579 mutex_lock(&dev->mode_config.mutex);
0b99836f 4580 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4581 if (edid) {
4582 if (drm_add_edid_modes(connector, edid)) {
4583 drm_mode_connector_update_edid_property(connector,
4584 edid);
4585 drm_edid_to_eld(connector, edid);
4586 } else {
4587 kfree(edid);
4588 edid = ERR_PTR(-EINVAL);
4589 }
4590 } else {
4591 edid = ERR_PTR(-ENOENT);
4592 }
4593 intel_connector->edid = edid;
4594
4595 /* prefer fixed mode from EDID if available */
4596 list_for_each_entry(scan, &connector->probed_modes, head) {
4597 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4598 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4599 downclock_mode = intel_dp_drrs_init(
4600 intel_dig_port,
4601 intel_connector, fixed_mode);
ed92f0b2
PZ		 4602 break;
4603 }
4604 }
4605
4606 /* fallback to VBT if available for eDP */
4607 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4608 fixed_mode = drm_mode_duplicate(dev,
4609 dev_priv->vbt.lfp_lvds_vbt_mode);
4610 if (fixed_mode)
4611 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4612 }
060c8778 4613 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4614
01527b31
CT		 4615 if (IS_VALLEYVIEW(dev)) {
4616 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4617 register_reboot_notifier(&intel_dp->edp_notifier);
4618 }
4619
4f9db5b5 4620 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 4621 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 4622 intel_panel_setup_backlight(connector);
4623
4624 return true;
4625}
4626
16c25533 4627bool
f0fec3f2
PZ		 4628intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4629 struct intel_connector *intel_connector)
a4fc5ed6 4630{
f0fec3f2
PZ		 4631 struct drm_connector *connector = &intel_connector->base;
4632 struct intel_dp *intel_dp = &intel_dig_port->dp;
4633 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4634 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4635 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4636 enum port port = intel_dig_port->port;
0095e6dc 4637 struct edp_power_seq power_seq = { 0 };
0b99836f 4638 int type;
a4fc5ed6 4639
ec5b01dd
DL		 4640 /* intel_dp vfuncs */
4641 if (IS_VALLEYVIEW(dev))
4642 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4643 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4644 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4645 else if (HAS_PCH_SPLIT(dev))
4646 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4647 else
4648 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4649
153b1100
DL		 4650 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4651
0767935e
DV		 4652 /* Preserve the current hw state. */
4653 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 4654 intel_dp->attached_connector = intel_connector;
3d3dc149 4655
3b32a35b 4656 if (intel_dp_is_edp(dev, port))
b329530c 4657 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 4658 else
4659 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 4660
f7d24902
ID		 4661 /*
4662 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4663 * for DP the encoder type can be set by the caller to
4664 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4665 */
4666 if (type == DRM_MODE_CONNECTOR_eDP)
4667 intel_encoder->type = INTEL_OUTPUT_EDP;
4668
e7281eab
ID		 4669 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4670 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4671 port_name(port));
4672
b329530c 4673 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 4674 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4675
a4fc5ed6
KP		 4676 connector->interlace_allowed = true;
4677 connector->doublescan_allowed = 0;
4678
f0fec3f2 4679 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 4680 edp_panel_vdd_work);
a4fc5ed6 4681
df0e9248 4682 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 4683 drm_connector_register(connector);
a4fc5ed6 4684
affa9354 4685 if (HAS_DDI(dev))
bcbc889b
PZ		 4686 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4687 else
4688 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 4689 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 4690
0b99836f 4691 /* Set up the hotplug pin. */
ab9d7c30
PZ		 4692 switch (port) {
4693 case PORT_A:
1d843f9d 4694 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 4695 break;
4696 case PORT_B:
1d843f9d 4697 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 4698 break;
4699 case PORT_C:
1d843f9d 4700 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 4701 break;
4702 case PORT_D:
1d843f9d 4703 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 4704 break;
4705 default:
ad1c0b19 4706 BUG();
5eb08b69
ZW		 4707 }
4708
dada1a9f
ID		 4709 if (is_edp(intel_dp)) {
4710 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 4711 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 4712 }
0095e6dc 4713
9d1a1031 4714 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 4715
0e32b39c
DA		 4716 /* init MST on ports that can support it */
4717 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4718 if (port == PORT_B || port == PORT_C || port == PORT_D) {
4719 intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id);
4720 }
4721 }
4722
0095e6dc 4723 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 4724 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 4725 if (is_edp(intel_dp)) {
4726 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 4727 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 4728 edp_panel_vdd_off_sync(intel_dp);
51fd371b 4729 drm_modeset_unlock(&dev->mode_config.connection_mutex);
15b1d171 4730 }
34ea3d38 4731 drm_connector_unregister(connector);
b2f246a8 4732 drm_connector_cleanup(connector);
16c25533 4733 return false;
b2f246a8 4734 }
32f9d658 4735
f684960e
CW		 4736 intel_dp_add_properties(intel_dp, connector);
4737
a4fc5ed6
KP		 4738 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4739 * 0xd. Failure to do so will result in spurious interrupts being
4740 * generated on the port when a cable is not attached.
4741 */
4742 if (IS_G4X(dev) && !IS_GM45(dev)) {
4743 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4744 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4745 }
16c25533
PZ		 4746
4747 return true;
a4fc5ed6 4748}
f0fec3f2
PZ		 4749
4750void
4751intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4752{
13cf5504 4753 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 4754 struct intel_digital_port *intel_dig_port;
4755 struct intel_encoder *intel_encoder;
4756 struct drm_encoder *encoder;
4757 struct intel_connector *intel_connector;
4758
b14c5679 4759 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 4760 if (!intel_dig_port)
4761 return;
4762
b14c5679 4763 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 4764 if (!intel_connector) {
4765 kfree(intel_dig_port);
4766 return;
4767 }
4768
4769 intel_encoder = &intel_dig_port->base;
4770 encoder = &intel_encoder->base;
4771
4772 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4773 DRM_MODE_ENCODER_TMDS);
4774
5bfe2ac0 4775 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 4776 intel_encoder->disable = intel_disable_dp;
00c09d70 4777 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 4778 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 4779 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 4780 if (IS_CHERRYVIEW(dev)) {
9197c88b 4781 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 4782 intel_encoder->pre_enable = chv_pre_enable_dp;
4783 intel_encoder->enable = vlv_enable_dp;
580d3811 4784 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 4785 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 4786 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 4787 intel_encoder->pre_enable = vlv_pre_enable_dp;
4788 intel_encoder->enable = vlv_enable_dp;
49277c31 4789 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 4790 } else {
ecff4f3b
JN		 4791 intel_encoder->pre_enable = g4x_pre_enable_dp;
4792 intel_encoder->enable = g4x_enable_dp;
49277c31 4793 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 4794 }
f0fec3f2 4795
174edf1f 4796 intel_dig_port->port = port;
f0fec3f2
PZ		 4797 intel_dig_port->dp.output_reg = output_reg;
4798
00c09d70 4799 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 4800 if (IS_CHERRYVIEW(dev)) {
4801 if (port == PORT_D)
4802 intel_encoder->crtc_mask = 1 << 2;
4803 else
4804 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4805 } else {
4806 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4807 }
bc079e8b 4808 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 4809 intel_encoder->hot_plug = intel_dp_hot_plug;
4810
13cf5504
DA		 4811 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4812 dev_priv->hpd_irq_port[port] = intel_dig_port;
4813
15b1d171
PZ		 4814 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4815 drm_encoder_cleanup(encoder);
4816 kfree(intel_dig_port);
b2f246a8 4817 kfree(intel_connector);
15b1d171 4818 }
f0fec3f2 4819}
0e32b39c
DA		 4820
4821void intel_dp_mst_suspend(struct drm_device *dev)
4822{
4823 struct drm_i915_private *dev_priv = dev->dev_private;
4824 int i;
4825
4826 /* disable MST */
4827 for (i = 0; i < I915_MAX_PORTS; i++) {
4828 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4829 if (!intel_dig_port)
4830 continue;
4831
4832 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4833 if (!intel_dig_port->dp.can_mst)
4834 continue;
4835 if (intel_dig_port->dp.is_mst)
4836 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
4837 }
4838 }
4839}
4840
4841void intel_dp_mst_resume(struct drm_device *dev)
4842{
4843 struct drm_i915_private *dev_priv = dev->dev_private;
4844 int i;
4845
4846 for (i = 0; i < I915_MAX_PORTS; i++) {
4847 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4848 if (!intel_dig_port)
4849 continue;
4850 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4851 int ret;
4852
4853 if (!intel_dig_port->dp.can_mst)
4854 continue;
4855
4856 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
4857 if (ret != 0) {
4858 intel_dp_check_mst_status(&intel_dig_port->dp);
4859 }
4860 }
4861 }
4862}
Linux kernel - Deliverables
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