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drm/i915: Limit the watermark to at least 8 entries on gen2/3
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 116
0e32b39c 117int
ea5b213a 118intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 119{
7183dc29 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
d4eead50 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
d4eead50 134 break;
a4fc5ed6 135 default:
d4eead50
ID		 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
a4fc5ed6
KP		 138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
eeb6324d
PZ		 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c19de8eb 189static enum drm_mode_status
a4fc5ed6
KP		 190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
df0e9248 193 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 198
dd06f90e
JN		 199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 201 return MODE_PANEL;
202
dd06f90e 203 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 204 return MODE_PANEL;
03afc4a2
DV		 205
206 target_clock = fixed_mode->clock;
7de56f43
ZY		 207 }
208
36008365 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 210 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
c4867936 216 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
0af78a2b
DV		 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
a4fc5ed6
KP		 224 return MODE_OK;
225}
226
227static uint32_t
228pack_aux(uint8_t *src, int src_bytes)
229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
fb0f8fbf
KP		 250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
9473c8f4
VP		 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
fb0f8fbf
KP		 261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
bf13e81b
JN		 284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
773538e8
VS		 293static void pps_lock(struct intel_dp *intel_dp)
294{
295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
296 struct intel_encoder *encoder = &intel_dig_port->base;
297 struct drm_device *dev = encoder->base.dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
299 enum intel_display_power_domain power_domain;
300
301 /*
302 * See vlv_power_sequencer_reset() why we need
303 * a power domain reference here.
304 */
305 power_domain = intel_display_port_power_domain(encoder);
306 intel_display_power_get(dev_priv, power_domain);
307
308 mutex_lock(&dev_priv->pps_mutex);
309}
310
311static void pps_unlock(struct intel_dp *intel_dp)
312{
313 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
314 struct intel_encoder *encoder = &intel_dig_port->base;
315 struct drm_device *dev = encoder->base.dev;
316 struct drm_i915_private *dev_priv = dev->dev_private;
317 enum intel_display_power_domain power_domain;
318
319 mutex_unlock(&dev_priv->pps_mutex);
320
321 power_domain = intel_display_port_power_domain(encoder);
322 intel_display_power_put(dev_priv, power_domain);
323}
324
bf13e81b
JN		 325static enum pipe
326vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
327{
328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 329 struct drm_device *dev = intel_dig_port->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 331 struct intel_encoder *encoder;
332 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
333 struct edp_power_seq power_seq;
bf13e81b 334
e39b999a
VS		 335 lockdep_assert_held(&dev_priv->pps_mutex);
336
a4a5d2f8
VS		 337 if (intel_dp->pps_pipe != INVALID_PIPE)
338 return intel_dp->pps_pipe;
339
340 /*
341 * We don't have power sequencer currently.
342 * Pick one that's not used by other ports.
343 */
344 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
345 base.head) {
346 struct intel_dp *tmp;
347
348 if (encoder->type != INTEL_OUTPUT_EDP)
349 continue;
350
351 tmp = enc_to_intel_dp(&encoder->base);
352
353 if (tmp->pps_pipe != INVALID_PIPE)
354 pipes &= ~(1 << tmp->pps_pipe);
355 }
356
357 /*
358 * Didn't find one. This should not happen since there
359 * are two power sequencers and up to two eDP ports.
360 */
361 if (WARN_ON(pipes == 0))
362 return PIPE_A;
363
364 intel_dp->pps_pipe = ffs(pipes) - 1;
365
366 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
367 pipe_name(intel_dp->pps_pipe),
368 port_name(intel_dig_port->port));
369
370 /* init power sequencer on this pipe and port */
371 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
372 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
373 &power_seq);
374
375 return intel_dp->pps_pipe;
376}
377
6491ab27
VS		 378typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
379 enum pipe pipe);
380
381static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
382 enum pipe pipe)
383{
384 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
385}
386
387static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
388 enum pipe pipe)
389{
390 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
391}
392
393static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
394 enum pipe pipe)
395{
396 return true;
397}
bf13e81b 398
a4a5d2f8 399static enum pipe
6491ab27
VS		 400vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
401 enum port port,
402 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 403{
404 enum pipe pipe;
bf13e81b 405
bf13e81b
JN		 406 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
407 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
408 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 409
410 if (port_sel != PANEL_PORT_SELECT_VLV(port))
411 continue;
412
6491ab27
VS		 413 if (!pipe_check(dev_priv, pipe))
414 continue;
415
a4a5d2f8 416 return pipe;
bf13e81b
JN		 417 }
418
a4a5d2f8
VS		 419 return INVALID_PIPE;
420}
421
422static void
423vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
424{
425 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
426 struct drm_device *dev = intel_dig_port->base.base.dev;
427 struct drm_i915_private *dev_priv = dev->dev_private;
428 struct edp_power_seq power_seq;
429 enum port port = intel_dig_port->port;
430
431 lockdep_assert_held(&dev_priv->pps_mutex);
432
433 /* try to find a pipe with this port selected */
6491ab27
VS		 434 /* first pick one where the panel is on */
435 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
436 vlv_pipe_has_pp_on);
437 /* didn't find one? pick one where vdd is on */
438 if (intel_dp->pps_pipe == INVALID_PIPE)
439 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
440 vlv_pipe_has_vdd_on);
441 /* didn't find one? pick one with just the correct port */
442 if (intel_dp->pps_pipe == INVALID_PIPE)
443 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
444 vlv_pipe_any);
a4a5d2f8
VS		 445
446 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
447 if (intel_dp->pps_pipe == INVALID_PIPE) {
448 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
449 port_name(port));
450 return;
bf13e81b
JN		 451 }
452
a4a5d2f8
VS		 453 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
454 port_name(port), pipe_name(intel_dp->pps_pipe));
455
456 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
457 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
458 &power_seq);
bf13e81b
JN		 459}
460
773538e8
VS		 461void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
462{
463 struct drm_device *dev = dev_priv->dev;
464 struct intel_encoder *encoder;
465
466 if (WARN_ON(!IS_VALLEYVIEW(dev)))
467 return;
468
469 /*
470 * We can't grab pps_mutex here due to deadlock with power_domain
471 * mutex when power_domain functions are called while holding pps_mutex.
472 * That also means that in order to use pps_pipe the code needs to
473 * hold both a power domain reference and pps_mutex, and the power domain
474 * reference get/put must be done while _not_ holding pps_mutex.
475 * pps_{lock,unlock}() do these steps in the correct order, so one
476 * should use them always.
477 */
478
479 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
480 struct intel_dp *intel_dp;
481
482 if (encoder->type != INTEL_OUTPUT_EDP)
483 continue;
484
485 intel_dp = enc_to_intel_dp(&encoder->base);
486 intel_dp->pps_pipe = INVALID_PIPE;
487 }
bf13e81b
JN		 488}
489
490static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
491{
492 struct drm_device *dev = intel_dp_to_dev(intel_dp);
493
494 if (HAS_PCH_SPLIT(dev))
495 return PCH_PP_CONTROL;
496 else
497 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
498}
499
500static u32 _pp_stat_reg(struct intel_dp *intel_dp)
501{
502 struct drm_device *dev = intel_dp_to_dev(intel_dp);
503
504 if (HAS_PCH_SPLIT(dev))
505 return PCH_PP_STATUS;
506 else
507 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
508}
509
01527b31
CT		 510/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
511 This function only applicable when panel PM state is not to be tracked */
512static int edp_notify_handler(struct notifier_block *this, unsigned long code,
513 void *unused)
514{
515 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
516 edp_notifier);
517 struct drm_device *dev = intel_dp_to_dev(intel_dp);
518 struct drm_i915_private *dev_priv = dev->dev_private;
519 u32 pp_div;
520 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 521
522 if (!is_edp(intel_dp) || code != SYS_RESTART)
523 return 0;
524
773538e8 525 pps_lock(intel_dp);
e39b999a 526
01527b31 527 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 528 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
529
01527b31
CT		 530 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
531 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
532 pp_div = I915_READ(pp_div_reg);
533 pp_div &= PP_REFERENCE_DIVIDER_MASK;
534
535 /* 0x1F write to PP_DIV_REG sets max cycle delay */
536 I915_WRITE(pp_div_reg, pp_div | 0x1F);
537 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
538 msleep(intel_dp->panel_power_cycle_delay);
539 }
540
773538e8 541 pps_unlock(intel_dp);
e39b999a 542
01527b31
CT		 543 return 0;
544}
545
4be73780 546static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 547{
30add22d 548 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 549 struct drm_i915_private *dev_priv = dev->dev_private;
550
e39b999a
VS		 551 lockdep_assert_held(&dev_priv->pps_mutex);
552
bf13e81b 553 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 554}
555
4be73780 556static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 557{
30add22d 558 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 559 struct drm_i915_private *dev_priv = dev->dev_private;
560
e39b999a
VS		 561 lockdep_assert_held(&dev_priv->pps_mutex);
562
773538e8 563 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 564}
565
9b984dae
KP		 566static void
567intel_dp_check_edp(struct intel_dp *intel_dp)
568{
30add22d 569 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 570 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 571
9b984dae
KP		 572 if (!is_edp(intel_dp))
573 return;
453c5420 574
4be73780 575 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 576 WARN(1, "eDP powered off while attempting aux channel communication.\n");
577 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 578 I915_READ(_pp_stat_reg(intel_dp)),
579 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 580 }
581}
582
9ee32fea
DV		 583static uint32_t
584intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
585{
586 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
587 struct drm_device *dev = intel_dig_port->base.base.dev;
588 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 589 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 590 uint32_t status;
591 bool done;
592
ef04f00d 593#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 594 if (has_aux_irq)
b18ac466 595 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 596 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 597 else
598 done = wait_for_atomic(C, 10) == 0;
599 if (!done)
600 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
601 has_aux_irq);
602#undef C
603
604 return status;
605}
606
ec5b01dd 607static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 608{
174edf1f
PZ		 609 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
610 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 611
ec5b01dd
DL		 612 /*
613 * The clock divider is based off the hrawclk, and would like to run at
614 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 615 */
ec5b01dd
DL		 616 return index ? 0 : intel_hrawclk(dev) / 2;
617}
618
619static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
620{
621 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
622 struct drm_device *dev = intel_dig_port->base.base.dev;
623
624 if (index)
625 return 0;
626
627 if (intel_dig_port->port == PORT_A) {
628 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 629 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 630 else
b84a1cf8 631 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 632 } else {
633 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
634 }
635}
636
637static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
638{
639 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
640 struct drm_device *dev = intel_dig_port->base.base.dev;
641 struct drm_i915_private *dev_priv = dev->dev_private;
642
643 if (intel_dig_port->port == PORT_A) {
644 if (index)
645 return 0;
646 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 647 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
648 /* Workaround for non-ULT HSW */
bc86625a
CW		 649 switch (index) {
650 case 0: return 63;
651 case 1: return 72;
652 default: return 0;
653 }
ec5b01dd 654 } else {
bc86625a 655 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 656 }
b84a1cf8
RV		 657}
658
ec5b01dd
DL		 659static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
660{
661 return index ? 0 : 100;
662}
663
5ed12a19
DL		 664static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
665 bool has_aux_irq,
666 int send_bytes,
667 uint32_t aux_clock_divider)
668{
669 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
670 struct drm_device *dev = intel_dig_port->base.base.dev;
671 uint32_t precharge, timeout;
672
673 if (IS_GEN6(dev))
674 precharge = 3;
675 else
676 precharge = 5;
677
678 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
679 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
680 else
681 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
682
683 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 684 DP_AUX_CH_CTL_DONE |
5ed12a19 685 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 686 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 687 timeout |
788d4433 688 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 689 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
690 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 691 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 692}
693
b84a1cf8
RV		 694static int
695intel_dp_aux_ch(struct intel_dp *intel_dp,
696 uint8_t *send, int send_bytes,
697 uint8_t *recv, int recv_size)
698{
699 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
700 struct drm_device *dev = intel_dig_port->base.base.dev;
701 struct drm_i915_private *dev_priv = dev->dev_private;
702 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
703 uint32_t ch_data = ch_ctl + 4;
bc86625a 704 uint32_t aux_clock_divider;
b84a1cf8
RV		 705 int i, ret, recv_bytes;
706 uint32_t status;
5ed12a19 707 int try, clock = 0;
4e6b788c 708 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 709 bool vdd;
710
773538e8 711 pps_lock(intel_dp);
e39b999a 712
72c3500a
VS		 713 /*
714 * We will be called with VDD already enabled for dpcd/edid/oui reads.
715 * In such cases we want to leave VDD enabled and it's up to upper layers
716 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
717 * ourselves.
718 */
1e0560e0 719 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 720
721 /* dp aux is extremely sensitive to irq latency, hence request the
722 * lowest possible wakeup latency and so prevent the cpu from going into
723 * deep sleep states.
724 */
725 pm_qos_update_request(&dev_priv->pm_qos, 0);
726
727 intel_dp_check_edp(intel_dp);
5eb08b69 728
c67a470b
PZ		 729 intel_aux_display_runtime_get(dev_priv);
730
11bee43e
JB		 731 /* Try to wait for any previous AUX channel activity */
732 for (try = 0; try < 3; try++) {
ef04f00d 733 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 734 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
735 break;
736 msleep(1);
737 }
738
739 if (try == 3) {
740 WARN(1, "dp_aux_ch not started status 0x%08x\n",
741 I915_READ(ch_ctl));
9ee32fea
DV		 742 ret = -EBUSY;
743 goto out;
4f7f7b7e
CW		 744 }
745
46a5ae9f
PZ		 746 /* Only 5 data registers! */
747 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
748 ret = -E2BIG;
749 goto out;
750 }
751
ec5b01dd 752 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 753 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
754 has_aux_irq,
755 send_bytes,
756 aux_clock_divider);
5ed12a19 757
bc86625a
CW		 758 /* Must try at least 3 times according to DP spec */
759 for (try = 0; try < 5; try++) {
760 /* Load the send data into the aux channel data registers */
761 for (i = 0; i < send_bytes; i += 4)
762 I915_WRITE(ch_data + i,
763 pack_aux(send + i, send_bytes - i));
764
765 /* Send the command and wait for it to complete */
5ed12a19 766 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 767
768 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
769
770 /* Clear done status and any errors */
771 I915_WRITE(ch_ctl,
772 status |
773 DP_AUX_CH_CTL_DONE |
774 DP_AUX_CH_CTL_TIME_OUT_ERROR |
775 DP_AUX_CH_CTL_RECEIVE_ERROR);
776
777 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
778 DP_AUX_CH_CTL_RECEIVE_ERROR))
779 continue;
780 if (status & DP_AUX_CH_CTL_DONE)
781 break;
782 }
4f7f7b7e 783 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 784 break;
785 }
786
a4fc5ed6 787 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 788 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 789 ret = -EBUSY;
790 goto out;
a4fc5ed6
KP		 791 }
792
793 /* Check for timeout or receive error.
794 * Timeouts occur when the sink is not connected
795 */
a5b3da54 796 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 797 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 798 ret = -EIO;
799 goto out;
a5b3da54 800 }
1ae8c0a5
KP		 801
802 /* Timeouts occur when the device isn't connected, so they're
803 * "normal" -- don't fill the kernel log with these */
a5b3da54 804 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 805 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 806 ret = -ETIMEDOUT;
807 goto out;
a4fc5ed6
KP		 808 }
809
810 /* Unload any bytes sent back from the other side */
811 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
812 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 813 if (recv_bytes > recv_size)
814 recv_bytes = recv_size;
0206e353 815
4f7f7b7e
CW		 816 for (i = 0; i < recv_bytes; i += 4)
817 unpack_aux(I915_READ(ch_data + i),
818 recv + i, recv_bytes - i);
a4fc5ed6 819
9ee32fea
DV		 820 ret = recv_bytes;
821out:
822 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 823 intel_aux_display_runtime_put(dev_priv);
9ee32fea 824
884f19e9
JN		 825 if (vdd)
826 edp_panel_vdd_off(intel_dp, false);
827
773538e8 828 pps_unlock(intel_dp);
e39b999a 829
9ee32fea 830 return ret;
a4fc5ed6
KP		 831}
832
a6c8aff0
JN		 833#define BARE_ADDRESS_SIZE 3
834#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 835static ssize_t
836intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 837{
9d1a1031
JN		 838 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
839 uint8_t txbuf[20], rxbuf[20];
840 size_t txsize, rxsize;
a4fc5ed6 841 int ret;
a4fc5ed6 842
9d1a1031
JN		 843 txbuf[0] = msg->request << 4;
844 txbuf[1] = msg->address >> 8;
845 txbuf[2] = msg->address & 0xff;
846 txbuf[3] = msg->size - 1;
46a5ae9f 847
9d1a1031
JN		 848 switch (msg->request & ~DP_AUX_I2C_MOT) {
849 case DP_AUX_NATIVE_WRITE:
850 case DP_AUX_I2C_WRITE:
a6c8aff0 851 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 852 rxsize = 1;
f51a44b9 853
9d1a1031
JN		 854 if (WARN_ON(txsize > 20))
855 return -E2BIG;
a4fc5ed6 856
9d1a1031 857 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 858
9d1a1031
JN		 859 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
860 if (ret > 0) {
861 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 862
9d1a1031
JN		 863 /* Return payload size. */
864 ret = msg->size;
865 }
866 break;
46a5ae9f 867
9d1a1031
JN		 868 case DP_AUX_NATIVE_READ:
869 case DP_AUX_I2C_READ:
a6c8aff0 870 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 871 rxsize = msg->size + 1;
a4fc5ed6 872
9d1a1031
JN		 873 if (WARN_ON(rxsize > 20))
874 return -E2BIG;
a4fc5ed6 875
9d1a1031
JN		 876 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
877 if (ret > 0) {
878 msg->reply = rxbuf[0] >> 4;
879 /*
880 * Assume happy day, and copy the data. The caller is
881 * expected to check msg->reply before touching it.
882 *
883 * Return payload size.
884 */
885 ret--;
886 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 887 }
9d1a1031
JN		 888 break;
889
890 default:
891 ret = -EINVAL;
892 break;
a4fc5ed6 893 }
f51a44b9 894
9d1a1031 895 return ret;
a4fc5ed6
KP		 896}
897
9d1a1031
JN		 898static void
899intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
900{
901 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 902 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
903 enum port port = intel_dig_port->port;
0b99836f 904 const char *name = NULL;
ab2c0672
DA		 905 int ret;
906
33ad6626
JN		 907 switch (port) {
908 case PORT_A:
909 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 910 name = "DPDDC-A";
ab2c0672 911 break;
33ad6626
JN		 912 case PORT_B:
913 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 914 name = "DPDDC-B";
ab2c0672 915 break;
33ad6626
JN		 916 case PORT_C:
917 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 918 name = "DPDDC-C";
ab2c0672 919 break;
33ad6626
JN		 920 case PORT_D:
921 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 922 name = "DPDDC-D";
33ad6626
JN		 923 break;
924 default:
925 BUG();
ab2c0672
DA		 926 }
927
33ad6626
JN		 928 if (!HAS_DDI(dev))
929 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 930
0b99836f 931 intel_dp->aux.name = name;
9d1a1031
JN		 932 intel_dp->aux.dev = dev->dev;
933 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 934
0b99836f
JN		 935 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
936 connector->base.kdev->kobj.name);
8316f337 937
4f71d0cb 938 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 939 if (ret < 0) {
4f71d0cb 940 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 941 name, ret);
942 return;
ab2c0672 943 }
8a5e6aeb 944
0b99836f
JN		 945 ret = sysfs_create_link(&connector->base.kdev->kobj,
946 &intel_dp->aux.ddc.dev.kobj,
947 intel_dp->aux.ddc.dev.kobj.name);
948 if (ret < 0) {
949 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 950 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 951 }
a4fc5ed6
KP		 952}
953
80f65de3
ID		 954static void
955intel_dp_connector_unregister(struct intel_connector *intel_connector)
956{
957 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
958
0e32b39c
DA		 959 if (!intel_connector->mst_port)
960 sysfs_remove_link(&intel_connector->base.kdev->kobj,
961 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 962 intel_connector_unregister(intel_connector);
963}
964
0e50338c
DV		 965static void
966hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
967{
968 switch (link_bw) {
969 case DP_LINK_BW_1_62:
970 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
971 break;
972 case DP_LINK_BW_2_7:
973 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
974 break;
975 case DP_LINK_BW_5_4:
976 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
977 break;
978 }
979}
980
c6bb3538
DV		 981static void
982intel_dp_set_clock(struct intel_encoder *encoder,
983 struct intel_crtc_config *pipe_config, int link_bw)
984{
985 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 986 const struct dp_link_dpll *divisor = NULL;
987 int i, count = 0;
c6bb3538
DV		 988
989 if (IS_G4X(dev)) {
9dd4ffdf
CML		 990 divisor = gen4_dpll;
991 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 992 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 993 divisor = pch_dpll;
994 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 995 } else if (IS_CHERRYVIEW(dev)) {
996 divisor = chv_dpll;
997 count = ARRAY_SIZE(chv_dpll);
c6bb3538 998 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 999 divisor = vlv_dpll;
1000 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1001 }
9dd4ffdf
CML		 1002
1003 if (divisor && count) {
1004 for (i = 0; i < count; i++) {
1005 if (link_bw == divisor[i].link_bw) {
1006 pipe_config->dpll = divisor[i].dpll;
1007 pipe_config->clock_set = true;
1008 break;
1009 }
1010 }
c6bb3538
DV		 1011 }
1012}
1013
00c09d70 1014bool
5bfe2ac0
DV		 1015intel_dp_compute_config(struct intel_encoder *encoder,
1016 struct intel_crtc_config *pipe_config)
a4fc5ed6 1017{
5bfe2ac0 1018 struct drm_device *dev = encoder->base.dev;
36008365 1019 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 1020 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 1021 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1022 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1023 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1024 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1025 int lane_count, clock;
56071a20 1026 int min_lane_count = 1;
eeb6324d 1027 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1028 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1029 int min_clock = 0;
06ea66b6 1030 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1031 int bpp, mode_rate;
06ea66b6 1032 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1033 int link_avail, link_clock;
a4fc5ed6 1034
bc7d38a4 1035 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1036 pipe_config->has_pch_encoder = true;
1037
03afc4a2 1038 pipe_config->has_dp_encoder = true;
f769cd24 1039 pipe_config->has_drrs = false;
9ed109a7 1040 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1041
dd06f90e
JN		 1042 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1043 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1044 adjusted_mode);
2dd24552
JB		 1045 if (!HAS_PCH_SPLIT(dev))
1046 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1047 intel_connector->panel.fitting_mode);
1048 else
b074cec8
JB		 1049 intel_pch_panel_fitting(intel_crtc, pipe_config,
1050 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1051 }
1052
cb1793ce 1053 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1054 return false;
1055
083f9560
DV		 1056 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1057 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1058 max_lane_count, bws[max_clock],
1059 adjusted_mode->crtc_clock);
083f9560 1060
36008365
DV		 1061 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1062 * bpc in between. */
3e7ca985 1063 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1064 if (is_edp(intel_dp)) {
1065 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1066 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1067 dev_priv->vbt.edp_bpp);
1068 bpp = dev_priv->vbt.edp_bpp;
1069 }
1070
f4cdbc21
JN		 1071 if (IS_BROADWELL(dev)) {
1072 /* Yes, it's an ugly hack. */
1073 min_lane_count = max_lane_count;
1074 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
1075 min_lane_count);
1076 } else if (dev_priv->vbt.edp_lanes) {
56071a20
JN		 1077 min_lane_count = min(dev_priv->vbt.edp_lanes,
1078 max_lane_count);
1079 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
1080 min_lane_count);
1081 }
1082
1083 if (dev_priv->vbt.edp_rate) {
1084 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
1085 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
1086 bws[min_clock]);
1087 }
7984211e 1088 }
657445fe 1089
36008365 1090 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1091 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1092 bpp);
36008365 1093
c6930992
DA		 1094 for (clock = min_clock; clock <= max_clock; clock++) {
1095 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1096 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1097 link_avail = intel_dp_max_data_rate(link_clock,
1098 lane_count);
1099
1100 if (mode_rate <= link_avail) {
1101 goto found;
1102 }
1103 }
1104 }
1105 }
c4867936 1106
36008365 1107 return false;
3685a8f3 1108
36008365 1109found:
55bc60db
VS		 1110 if (intel_dp->color_range_auto) {
1111 /*
1112 * See:
1113 * CEA-861-E - 5.1 Default Encoding Parameters
1114 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1115 */
18316c8c 1116 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1117 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1118 else
1119 intel_dp->color_range = 0;
1120 }
1121
3685a8f3 1122 if (intel_dp->color_range)
50f3b016 1123 pipe_config->limited_color_range = true;
a4fc5ed6 1124
36008365
DV		 1125 intel_dp->link_bw = bws[clock];
1126 intel_dp->lane_count = lane_count;
657445fe 1127 pipe_config->pipe_bpp = bpp;
ff9a6750 1128 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1129
36008365
DV		 1130 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1131 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1132 pipe_config->port_clock, bpp);
36008365
DV		 1133 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1134 mode_rate, link_avail);
a4fc5ed6 1135
03afc4a2 1136 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1137 adjusted_mode->crtc_clock,
1138 pipe_config->port_clock,
03afc4a2 1139 &pipe_config->dp_m_n);
9d1a455b 1140
439d7ac0
PB		 1141 if (intel_connector->panel.downclock_mode != NULL &&
1142 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1143 pipe_config->has_drrs = true;
439d7ac0
PB		 1144 intel_link_compute_m_n(bpp, lane_count,
1145 intel_connector->panel.downclock_mode->clock,
1146 pipe_config->port_clock,
1147 &pipe_config->dp_m2_n2);
1148 }
1149
ea155f32 1150 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1151 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1152 else
1153 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1154
03afc4a2 1155 return true;
a4fc5ed6
KP		 1156}
1157
7c62a164 1158static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1159{
7c62a164
DV		 1160 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1161 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1162 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1163 struct drm_i915_private *dev_priv = dev->dev_private;
1164 u32 dpa_ctl;
1165
ff9a6750 1166 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 1167 dpa_ctl = I915_READ(DP_A);
1168 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1169
ff9a6750 1170 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1171 /* For a long time we've carried around a ILK-DevA w/a for the
1172 * 160MHz clock. If we're really unlucky, it's still required.
1173 */
1174 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1175 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1176 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1177 } else {
1178 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1179 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1180 }
1ce17038 1181
ea9b6006
DV		 1182 I915_WRITE(DP_A, dpa_ctl);
1183
1184 POSTING_READ(DP_A);
1185 udelay(500);
1186}
1187
8ac33ed3 1188static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1189{
b934223d 1190 struct drm_device *dev = encoder->base.dev;
417e822d 1191 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1192 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1193 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1194 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1195 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1196
417e822d 1197 /*
1a2eb460 1198 * There are four kinds of DP registers:
417e822d
KP		 1199 *
1200 * IBX PCH
1a2eb460
KP		 1201 * SNB CPU
1202 * IVB CPU
417e822d
KP		 1203 * CPT PCH
1204 *
1205 * IBX PCH and CPU are the same for almost everything,
1206 * except that the CPU DP PLL is configured in this
1207 * register
1208 *
1209 * CPT PCH is quite different, having many bits moved
1210 * to the TRANS_DP_CTL register instead. That
1211 * configuration happens (oddly) in ironlake_pch_enable
1212 */
9c9e7927 1213
417e822d
KP		 1214 /* Preserve the BIOS-computed detected bit. This is
1215 * supposed to be read-only.
1216 */
1217 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1218
417e822d 1219 /* Handle DP bits in common between all three register formats */
417e822d 1220 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1221 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1222
9ed109a7 1223 if (crtc->config.has_audio) {
e0dac65e 1224 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1225 pipe_name(crtc->pipe));
ea5b213a 1226 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1227 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1228 }
247d89f6 1229
417e822d 1230 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1231
bc7d38a4 1232 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1233 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1234 intel_dp->DP |= DP_SYNC_HS_HIGH;
1235 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1236 intel_dp->DP |= DP_SYNC_VS_HIGH;
1237 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1238
6aba5b6c 1239 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1240 intel_dp->DP |= DP_ENHANCED_FRAMING;
1241
7c62a164 1242 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1243 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1244 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1245 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1246
1247 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1248 intel_dp->DP |= DP_SYNC_HS_HIGH;
1249 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1250 intel_dp->DP |= DP_SYNC_VS_HIGH;
1251 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1252
6aba5b6c 1253 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1254 intel_dp->DP |= DP_ENHANCED_FRAMING;
1255
44f37d1f
CML		 1256 if (!IS_CHERRYVIEW(dev)) {
1257 if (crtc->pipe == 1)
1258 intel_dp->DP |= DP_PIPEB_SELECT;
1259 } else {
1260 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1261 }
417e822d
KP		 1262 } else {
1263 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1264 }
a4fc5ed6
KP		 1265}
1266
ffd6749d
PZ		 1267#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1268#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1269
1a5ef5b7
PZ		 1270#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1271#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1272
ffd6749d
PZ		 1273#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1274#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1275
4be73780 1276static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1277 u32 mask,
1278 u32 value)
bd943159 1279{
30add22d 1280 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1281 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1282 u32 pp_stat_reg, pp_ctrl_reg;
1283
e39b999a
VS		 1284 lockdep_assert_held(&dev_priv->pps_mutex);
1285
bf13e81b
JN		 1286 pp_stat_reg = _pp_stat_reg(intel_dp);
1287 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1288
99ea7127 1289 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1290 mask, value,
1291 I915_READ(pp_stat_reg),
1292 I915_READ(pp_ctrl_reg));
32ce697c 1293
453c5420 1294 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1295 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1296 I915_READ(pp_stat_reg),
1297 I915_READ(pp_ctrl_reg));
32ce697c 1298 }
54c136d4
CW		 1299
1300 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1301}
32ce697c 1302
4be73780 1303static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1304{
1305 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1306 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1307}
1308
4be73780 1309static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1310{
1311 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1312 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1313}
1314
4be73780 1315static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1316{
1317 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1318
1319 /* When we disable the VDD override bit last we have to do the manual
1320 * wait. */
1321 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1322 intel_dp->panel_power_cycle_delay);
1323
4be73780 1324 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1325}
1326
4be73780 1327static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1328{
1329 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1330 intel_dp->backlight_on_delay);
1331}
1332
4be73780 1333static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1334{
1335 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1336 intel_dp->backlight_off_delay);
1337}
99ea7127 1338
832dd3c1
KP		 1339/* Read the current pp_control value, unlocking the register if it
1340 * is locked
1341 */
1342
453c5420 1343static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1344{
453c5420
JB		 1345 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1346 struct drm_i915_private *dev_priv = dev->dev_private;
1347 u32 control;
832dd3c1 1348
e39b999a
VS		 1349 lockdep_assert_held(&dev_priv->pps_mutex);
1350
bf13e81b 1351 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1352 control &= ~PANEL_UNLOCK_MASK;
1353 control |= PANEL_UNLOCK_REGS;
1354 return control;
bd943159
KP		 1355}
1356
951468f3
VS		 1357/*
1358 * Must be paired with edp_panel_vdd_off().
1359 * Must hold pps_mutex around the whole on/off sequence.
1360 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1361 */
1e0560e0 1362static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1363{
30add22d 1364 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1365 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1366 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1367 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1368 enum intel_display_power_domain power_domain;
5d613501 1369 u32 pp;
453c5420 1370 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1371 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1372
e39b999a
VS		 1373 lockdep_assert_held(&dev_priv->pps_mutex);
1374
97af61f5 1375 if (!is_edp(intel_dp))
adddaaf4 1376 return false;
bd943159
KP		 1377
1378 intel_dp->want_panel_vdd = true;
99ea7127 1379
4be73780 1380 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1381 return need_to_disable;
b0665d57 1382
4e6e1a54
ID		 1383 power_domain = intel_display_port_power_domain(intel_encoder);
1384 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1385
b0665d57 1386 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1387
4be73780
DV		 1388 if (!edp_have_panel_power(intel_dp))
1389 wait_panel_power_cycle(intel_dp);
99ea7127 1390
453c5420 1391 pp = ironlake_get_pp_control(intel_dp);
5d613501 1392 pp |= EDP_FORCE_VDD;
ebf33b18 1393
bf13e81b
JN		 1394 pp_stat_reg = _pp_stat_reg(intel_dp);
1395 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1396
1397 I915_WRITE(pp_ctrl_reg, pp);
1398 POSTING_READ(pp_ctrl_reg);
1399 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1400 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1401 /*
1402 * If the panel wasn't on, delay before accessing aux channel
1403 */
4be73780 1404 if (!edp_have_panel_power(intel_dp)) {
bd943159 1405 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1406 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1407 }
adddaaf4
JN		 1408
1409 return need_to_disable;
1410}
1411
951468f3
VS		 1412/*
1413 * Must be paired with intel_edp_panel_vdd_off() or
1414 * intel_edp_panel_off().
1415 * Nested calls to these functions are not allowed since
1416 * we drop the lock. Caller must use some higher level
1417 * locking to prevent nested calls from other threads.
1418 */
b80d6c78 1419void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1420{
c695b6b6 1421 bool vdd;
adddaaf4 1422
c695b6b6
VS		 1423 if (!is_edp(intel_dp))
1424 return;
1425
773538e8 1426 pps_lock(intel_dp);
c695b6b6 1427 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1428 pps_unlock(intel_dp);
c695b6b6
VS		 1429
1430 WARN(!vdd, "eDP VDD already requested on\n");
5d613501
JB		 1431}
1432
4be73780 1433static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1434{
30add22d 1435 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1436 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1437 struct intel_digital_port *intel_dig_port =
1438 dp_to_dig_port(intel_dp);
1439 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1440 enum intel_display_power_domain power_domain;
5d613501 1441 u32 pp;
453c5420 1442 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1443
e39b999a 1444 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1445
15e899a0 1446 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1447
15e899a0 1448 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1449 return;
b0665d57 1450
be2c9196 1451 DRM_DEBUG_KMS("Turning eDP VDD off\n");
bd943159 1452
be2c9196
VS		 1453 pp = ironlake_get_pp_control(intel_dp);
1454 pp &= ~EDP_FORCE_VDD;
453c5420 1455
be2c9196
VS		 1456 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1457 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420 1458
be2c9196
VS		 1459 I915_WRITE(pp_ctrl_reg, pp);
1460 POSTING_READ(pp_ctrl_reg);
99ea7127 1461
be2c9196
VS		 1462 /* Make sure sequencer is idle before allowing subsequent activity */
1463 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1464 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c 1465
be2c9196
VS		 1466 if ((pp & POWER_TARGET_ON) == 0)
1467 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1468
be2c9196
VS		 1469 power_domain = intel_display_port_power_domain(intel_encoder);
1470 intel_display_power_put(dev_priv, power_domain);
bd943159 1471}
5d613501 1472
4be73780 1473static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1474{
1475 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1476 struct intel_dp, panel_vdd_work);
bd943159 1477
773538e8 1478 pps_lock(intel_dp);
15e899a0
VS		 1479 if (!intel_dp->want_panel_vdd)
1480 edp_panel_vdd_off_sync(intel_dp);
773538e8 1481 pps_unlock(intel_dp);
bd943159
KP		 1482}
1483
aba86890
ID		 1484static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1485{
1486 unsigned long delay;
1487
1488 /*
1489 * Queue the timer to fire a long time from now (relative to the power
1490 * down delay) to keep the panel power up across a sequence of
1491 * operations.
1492 */
1493 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1494 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1495}
1496
951468f3
VS		 1497/*
1498 * Must be paired with edp_panel_vdd_on().
1499 * Must hold pps_mutex around the whole on/off sequence.
1500 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1501 */
4be73780 1502static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1503{
e39b999a
VS		 1504 struct drm_i915_private *dev_priv =
1505 intel_dp_to_dev(intel_dp)->dev_private;
1506
1507 lockdep_assert_held(&dev_priv->pps_mutex);
1508
97af61f5
KP		 1509 if (!is_edp(intel_dp))
1510 return;
5d613501 1511
bd943159 1512 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1513
bd943159
KP		 1514 intel_dp->want_panel_vdd = false;
1515
aba86890 1516 if (sync)
4be73780 1517 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1518 else
1519 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1520}
1521
951468f3
VS		 1522/*
1523 * Must be paired with intel_edp_panel_vdd_on().
1524 * Nested calls to these functions are not allowed since
1525 * we drop the lock. Caller must use some higher level
1526 * locking to prevent nested calls from other threads.
1527 */
1e0560e0
VS		 1528static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1529{
e39b999a
VS		 1530 if (!is_edp(intel_dp))
1531 return;
1532
773538e8 1533 pps_lock(intel_dp);
1e0560e0 1534 edp_panel_vdd_off(intel_dp, sync);
773538e8 1535 pps_unlock(intel_dp);
1e0560e0
VS		 1536}
1537
4be73780 1538void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1539{
30add22d 1540 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1541 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1542 u32 pp;
453c5420 1543 u32 pp_ctrl_reg;
9934c132 1544
97af61f5 1545 if (!is_edp(intel_dp))
bd943159 1546 return;
99ea7127
KP		 1547
1548 DRM_DEBUG_KMS("Turn eDP power on\n");
1549
773538e8 1550 pps_lock(intel_dp);
e39b999a 1551
4be73780 1552 if (edp_have_panel_power(intel_dp)) {
99ea7127 1553 DRM_DEBUG_KMS("eDP power already on\n");
e39b999a 1554 goto out;
99ea7127 1555 }
9934c132 1556
4be73780 1557 wait_panel_power_cycle(intel_dp);
37c6c9b0 1558
bf13e81b 1559 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1560 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1561 if (IS_GEN5(dev)) {
1562 /* ILK workaround: disable reset around power sequence */
1563 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1564 I915_WRITE(pp_ctrl_reg, pp);
1565 POSTING_READ(pp_ctrl_reg);
05ce1a49 1566 }
37c6c9b0 1567
1c0ae80a 1568 pp |= POWER_TARGET_ON;
99ea7127
KP		 1569 if (!IS_GEN5(dev))
1570 pp |= PANEL_POWER_RESET;
1571
453c5420
JB		 1572 I915_WRITE(pp_ctrl_reg, pp);
1573 POSTING_READ(pp_ctrl_reg);
9934c132 1574
4be73780 1575 wait_panel_on(intel_dp);
dce56b3c 1576 intel_dp->last_power_on = jiffies;
9934c132 1577
05ce1a49
KP		 1578 if (IS_GEN5(dev)) {
1579 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1580 I915_WRITE(pp_ctrl_reg, pp);
1581 POSTING_READ(pp_ctrl_reg);
05ce1a49 1582 }
e39b999a
VS		 1583
1584 out:
773538e8 1585 pps_unlock(intel_dp);
9934c132
JB		 1586}
1587
4be73780 1588void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1589{
4e6e1a54
ID		 1590 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1591 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1592 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1593 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1594 enum intel_display_power_domain power_domain;
99ea7127 1595 u32 pp;
453c5420 1596 u32 pp_ctrl_reg;
9934c132 1597
97af61f5
KP		 1598 if (!is_edp(intel_dp))
1599 return;
37c6c9b0 1600
99ea7127 1601 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1602
773538e8 1603 pps_lock(intel_dp);
e39b999a 1604
24f3e092
JN		 1605 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1606
453c5420 1607 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1608 /* We need to switch off panel power _and_ force vdd, for otherwise some
1609 * panels get very unhappy and cease to work. */
b3064154
PJ		 1610 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1611 EDP_BLC_ENABLE);
453c5420 1612
bf13e81b 1613 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1614
849e39f5
PZ		 1615 intel_dp->want_panel_vdd = false;
1616
453c5420
JB		 1617 I915_WRITE(pp_ctrl_reg, pp);
1618 POSTING_READ(pp_ctrl_reg);
9934c132 1619
dce56b3c 1620 intel_dp->last_power_cycle = jiffies;
4be73780 1621 wait_panel_off(intel_dp);
849e39f5
PZ		 1622
1623 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1624 power_domain = intel_display_port_power_domain(intel_encoder);
1625 intel_display_power_put(dev_priv, power_domain);
e39b999a 1626
773538e8 1627 pps_unlock(intel_dp);
9934c132
JB		 1628}
1629
1250d107
JN		 1630/* Enable backlight in the panel power control. */
1631static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1632{
da63a9f2
PZ		 1633 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1634 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1635 struct drm_i915_private *dev_priv = dev->dev_private;
1636 u32 pp;
453c5420 1637 u32 pp_ctrl_reg;
32f9d658 1638
01cb9ea6
JB		 1639 /*
1640 * If we enable the backlight right away following a panel power
1641 * on, we may see slight flicker as the panel syncs with the eDP
1642 * link. So delay a bit to make sure the image is solid before
1643 * allowing it to appear.
1644 */
4be73780 1645 wait_backlight_on(intel_dp);
e39b999a 1646
773538e8 1647 pps_lock(intel_dp);
e39b999a 1648
453c5420 1649 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1650 pp |= EDP_BLC_ENABLE;
453c5420 1651
bf13e81b 1652 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1653
1654 I915_WRITE(pp_ctrl_reg, pp);
1655 POSTING_READ(pp_ctrl_reg);
e39b999a 1656
773538e8 1657 pps_unlock(intel_dp);
32f9d658
ZW		 1658}
1659
1250d107
JN		 1660/* Enable backlight PWM and backlight PP control. */
1661void intel_edp_backlight_on(struct intel_dp *intel_dp)
1662{
1663 if (!is_edp(intel_dp))
1664 return;
1665
1666 DRM_DEBUG_KMS("\n");
1667
1668 intel_panel_enable_backlight(intel_dp->attached_connector);
1669 _intel_edp_backlight_on(intel_dp);
1670}
1671
1672/* Disable backlight in the panel power control. */
1673static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1674{
30add22d 1675 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1676 struct drm_i915_private *dev_priv = dev->dev_private;
1677 u32 pp;
453c5420 1678 u32 pp_ctrl_reg;
32f9d658 1679
f01eca2e
KP		 1680 if (!is_edp(intel_dp))
1681 return;
1682
773538e8 1683 pps_lock(intel_dp);
e39b999a 1684
453c5420 1685 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1686 pp &= ~EDP_BLC_ENABLE;
453c5420 1687
bf13e81b 1688 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1689
1690 I915_WRITE(pp_ctrl_reg, pp);
1691 POSTING_READ(pp_ctrl_reg);
f7d2323c 1692
773538e8 1693 pps_unlock(intel_dp);
e39b999a
VS		 1694
1695 intel_dp->last_backlight_off = jiffies;
f7d2323c 1696 edp_wait_backlight_off(intel_dp);
1250d107 1697}
f7d2323c 1698
1250d107
JN		 1699/* Disable backlight PP control and backlight PWM. */
1700void intel_edp_backlight_off(struct intel_dp *intel_dp)
1701{
1702 if (!is_edp(intel_dp))
1703 return;
1704
1705 DRM_DEBUG_KMS("\n");
f7d2323c 1706
1250d107 1707 _intel_edp_backlight_off(intel_dp);
f7d2323c 1708 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1709}
a4fc5ed6 1710
73580fb7
JN		 1711/*
1712 * Hook for controlling the panel power control backlight through the bl_power
1713 * sysfs attribute. Take care to handle multiple calls.
1714 */
1715static void intel_edp_backlight_power(struct intel_connector *connector,
1716 bool enable)
1717{
1718 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1719 bool is_enabled;
1720
773538e8 1721 pps_lock(intel_dp);
e39b999a 1722 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1723 pps_unlock(intel_dp);
73580fb7
JN		 1724
1725 if (is_enabled == enable)
1726 return;
1727
23ba9373
JN		 1728 DRM_DEBUG_KMS("panel power control backlight %s\n",
1729 enable ? "enable" : "disable");
73580fb7
JN		 1730
1731 if (enable)
1732 _intel_edp_backlight_on(intel_dp);
1733 else
1734 _intel_edp_backlight_off(intel_dp);
1735}
1736
2bd2ad64 1737static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1738{
da63a9f2
PZ		 1739 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1740 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1741 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1742 struct drm_i915_private *dev_priv = dev->dev_private;
1743 u32 dpa_ctl;
1744
2bd2ad64
DV		 1745 assert_pipe_disabled(dev_priv,
1746 to_intel_crtc(crtc)->pipe);
1747
d240f20f
JB		 1748 DRM_DEBUG_KMS("\n");
1749 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1750 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1751 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1752
1753 /* We don't adjust intel_dp->DP while tearing down the link, to
1754 * facilitate link retraining (e.g. after hotplug). Hence clear all
1755 * enable bits here to ensure that we don't enable too much. */
1756 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1757 intel_dp->DP |= DP_PLL_ENABLE;
1758 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1759 POSTING_READ(DP_A);
1760 udelay(200);
d240f20f
JB		 1761}
1762
2bd2ad64 1763static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1764{
da63a9f2
PZ		 1765 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1766 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1767 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1768 struct drm_i915_private *dev_priv = dev->dev_private;
1769 u32 dpa_ctl;
1770
2bd2ad64
DV		 1771 assert_pipe_disabled(dev_priv,
1772 to_intel_crtc(crtc)->pipe);
1773
d240f20f 1774 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1775 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1776 "dp pll off, should be on\n");
1777 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1778
1779 /* We can't rely on the value tracked for the DP register in
1780 * intel_dp->DP because link_down must not change that (otherwise link
1781 * re-training will fail. */
298b0b39 1782 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1783 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1784 POSTING_READ(DP_A);
d240f20f
JB		 1785 udelay(200);
1786}
1787
c7ad3810 1788/* If the sink supports it, try to set the power state appropriately */
c19b0669 1789void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1790{
1791 int ret, i;
1792
1793 /* Should have a valid DPCD by this point */
1794 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1795 return;
1796
1797 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1798 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1799 DP_SET_POWER_D3);
c7ad3810
JB		 1800 } else {
1801 /*
1802 * When turning on, we need to retry for 1ms to give the sink
1803 * time to wake up.
1804 */
1805 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1806 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1807 DP_SET_POWER_D0);
c7ad3810
JB		 1808 if (ret == 1)
1809 break;
1810 msleep(1);
1811 }
1812 }
f9cac721
JN		 1813
1814 if (ret != 1)
1815 DRM_DEBUG_KMS("failed to %s sink power state\n",
1816 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1817}
1818
19d8fe15
DV		 1819static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1820 enum pipe *pipe)
d240f20f 1821{
19d8fe15 1822 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1823 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1824 struct drm_device *dev = encoder->base.dev;
1825 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1826 enum intel_display_power_domain power_domain;
1827 u32 tmp;
1828
1829 power_domain = intel_display_port_power_domain(encoder);
1830 if (!intel_display_power_enabled(dev_priv, power_domain))
1831 return false;
1832
1833 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1834
1835 if (!(tmp & DP_PORT_EN))
1836 return false;
1837
bc7d38a4 1838 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1839 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1840 } else if (IS_CHERRYVIEW(dev)) {
1841 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1842 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1843 *pipe = PORT_TO_PIPE(tmp);
1844 } else {
1845 u32 trans_sel;
1846 u32 trans_dp;
1847 int i;
1848
1849 switch (intel_dp->output_reg) {
1850 case PCH_DP_B:
1851 trans_sel = TRANS_DP_PORT_SEL_B;
1852 break;
1853 case PCH_DP_C:
1854 trans_sel = TRANS_DP_PORT_SEL_C;
1855 break;
1856 case PCH_DP_D:
1857 trans_sel = TRANS_DP_PORT_SEL_D;
1858 break;
1859 default:
1860 return true;
1861 }
1862
055e393f 1863 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1864 trans_dp = I915_READ(TRANS_DP_CTL(i));
1865 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1866 *pipe = i;
1867 return true;
1868 }
1869 }
19d8fe15 1870
4a0833ec
DV		 1871 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1872 intel_dp->output_reg);
1873 }
d240f20f 1874
19d8fe15
DV		 1875 return true;
1876}
d240f20f 1877
045ac3b5
JB		 1878static void intel_dp_get_config(struct intel_encoder *encoder,
1879 struct intel_crtc_config *pipe_config)
1880{
1881 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1882 u32 tmp, flags = 0;
63000ef6
XZ		 1883 struct drm_device *dev = encoder->base.dev;
1884 struct drm_i915_private *dev_priv = dev->dev_private;
1885 enum port port = dp_to_dig_port(intel_dp)->port;
1886 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1887 int dotclock;
045ac3b5 1888
9ed109a7
DV		 1889 tmp = I915_READ(intel_dp->output_reg);
1890 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1891 pipe_config->has_audio = true;
1892
63000ef6 1893 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1894 if (tmp & DP_SYNC_HS_HIGH)
1895 flags |= DRM_MODE_FLAG_PHSYNC;
1896 else
1897 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1898
63000ef6
XZ		 1899 if (tmp & DP_SYNC_VS_HIGH)
1900 flags |= DRM_MODE_FLAG_PVSYNC;
1901 else
1902 flags |= DRM_MODE_FLAG_NVSYNC;
1903 } else {
1904 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1905 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1906 flags |= DRM_MODE_FLAG_PHSYNC;
1907 else
1908 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1909
63000ef6
XZ		 1910 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1911 flags |= DRM_MODE_FLAG_PVSYNC;
1912 else
1913 flags |= DRM_MODE_FLAG_NVSYNC;
1914 }
045ac3b5
JB		 1915
1916 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1917
eb14cb74
VS		 1918 pipe_config->has_dp_encoder = true;
1919
1920 intel_dp_get_m_n(crtc, pipe_config);
1921
18442d08 1922 if (port == PORT_A) {
f1f644dc
JB		 1923 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1924 pipe_config->port_clock = 162000;
1925 else
1926 pipe_config->port_clock = 270000;
1927 }
18442d08
VS		 1928
1929 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1930 &pipe_config->dp_m_n);
1931
1932 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1933 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1934
241bfc38 1935 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1936
c6cd2ee2
JN		 1937 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1938 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1939 /*
1940 * This is a big fat ugly hack.
1941 *
1942 * Some machines in UEFI boot mode provide us a VBT that has 18
1943 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1944 * unknown we fail to light up. Yet the same BIOS boots up with
1945 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1946 * max, not what it tells us to use.
1947 *
1948 * Note: This will still be broken if the eDP panel is not lit
1949 * up by the BIOS, and thus we can't get the mode at module
1950 * load.
1951 */
1952 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1953 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1954 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1955 }
045ac3b5
JB		 1956}
1957
34eb7579 1958static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1959{
34eb7579 1960 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1961}
1962
2b28bb1b
RV		 1963static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1964{
1965 struct drm_i915_private *dev_priv = dev->dev_private;
1966
18b5992c 1967 if (!HAS_PSR(dev))
2b28bb1b
RV		 1968 return false;
1969
18b5992c 1970 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1971}
1972
1973static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1974 struct edp_vsc_psr *vsc_psr)
1975{
1976 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1977 struct drm_device *dev = dig_port->base.base.dev;
1978 struct drm_i915_private *dev_priv = dev->dev_private;
1979 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1980 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1981 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1982 uint32_t *data = (uint32_t *) vsc_psr;
1983 unsigned int i;
1984
1985 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1986 the video DIP being updated before program video DIP data buffer
1987 registers for DIP being updated. */
1988 I915_WRITE(ctl_reg, 0);
1989 POSTING_READ(ctl_reg);
1990
1991 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1992 if (i < sizeof(struct edp_vsc_psr))
1993 I915_WRITE(data_reg + i, *data++);
1994 else
1995 I915_WRITE(data_reg + i, 0);
1996 }
1997
1998 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1999 POSTING_READ(ctl_reg);
2000}
2001
2002static void intel_edp_psr_setup(struct intel_dp *intel_dp)
2003{
2004 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2005 struct drm_i915_private *dev_priv = dev->dev_private;
2006 struct edp_vsc_psr psr_vsc;
2007
2b28bb1b
RV		 2008 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2009 memset(&psr_vsc, 0, sizeof(psr_vsc));
2010 psr_vsc.sdp_header.HB0 = 0;
2011 psr_vsc.sdp_header.HB1 = 0x7;
2012 psr_vsc.sdp_header.HB2 = 0x2;
2013 psr_vsc.sdp_header.HB3 = 0x8;
2014 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
2015
2016 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 2017 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 2018 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 2019}
2020
2021static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
2022{
0e0ae652
RV		 2023 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2024 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 2025 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 2026 uint32_t aux_clock_divider;
2b28bb1b
RV		 2027 int precharge = 0x3;
2028 int msg_size = 5; /* Header(4) + Message(1) */
0e0ae652 2029 bool only_standby = false;
2b28bb1b 2030
ec5b01dd
DL		 2031 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2032
0e0ae652
RV		 2033 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2034 only_standby = true;
2035
2b28bb1b 2036 /* Enable PSR in sink */
0e0ae652 2037 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 2038 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2039 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 2040 else
9d1a1031
JN		 2041 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2042 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 2043
2044 /* Setup AUX registers */
18b5992c
BW		 2045 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
2046 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
2047 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 2048 DP_AUX_CH_CTL_TIME_OUT_400us |
2049 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
2050 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
2051 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
2052}
2053
2054static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2055{
0e0ae652
RV		 2056 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2057 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 2058 struct drm_i915_private *dev_priv = dev->dev_private;
2059 uint32_t max_sleep_time = 0x1f;
2060 uint32_t idle_frames = 1;
2061 uint32_t val = 0x0;
ed8546ac 2062 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 2063 bool only_standby = false;
2064
2065 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2066 only_standby = true;
2b28bb1b 2067
0e0ae652 2068 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 2069 val |= EDP_PSR_LINK_STANDBY;
2070 val |= EDP_PSR_TP2_TP3_TIME_0us;
2071 val |= EDP_PSR_TP1_TIME_0us;
2072 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 2073 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 2074 } else
2075 val |= EDP_PSR_LINK_DISABLE;
2076
18b5992c 2077 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 2078 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 2079 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2080 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2081 EDP_PSR_ENABLE);
2082}
2083
3f51e471
RV		 2084static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2085{
2086 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2087 struct drm_device *dev = dig_port->base.base.dev;
2088 struct drm_i915_private *dev_priv = dev->dev_private;
2089 struct drm_crtc *crtc = dig_port->base.base.crtc;
2090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 2091
f0355c4a 2092 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 2093 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2094 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2095
a031d709
RV		 2096 dev_priv->psr.source_ok = false;
2097
9ca15301 2098 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 2099 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 2100 return false;
2101 }
2102
d330a953 2103 if (!i915.enable_psr) {
105b7c11 2104 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 2105 return false;
2106 }
2107
4c8c7000
RV		 2108 /* Below limitations aren't valid for Broadwell */
2109 if (IS_BROADWELL(dev))
2110 goto out;
2111
3f51e471
RV		 2112 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2113 S3D_ENABLE) {
2114 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 2115 return false;
2116 }
2117
ca73b4f0 2118 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 2119 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 2120 return false;
2121 }
2122
4c8c7000 2123 out:
a031d709 2124 dev_priv->psr.source_ok = true;
3f51e471
RV		 2125 return true;
2126}
2127
3d739d92 2128static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 2129{
7c8f8a70
RV		 2130 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2131 struct drm_device *dev = intel_dig_port->base.base.dev;
2132 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 2133
3638379c
DV		 2134 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2135 WARN_ON(dev_priv->psr.active);
f0355c4a 2136 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 2137
2b28bb1b
RV		 2138 /* Enable PSR on the panel */
2139 intel_edp_psr_enable_sink(intel_dp);
2140
2141 /* Enable PSR on the host */
2142 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 2143
7c8f8a70 2144 dev_priv->psr.active = true;
2b28bb1b
RV		 2145}
2146
3d739d92
RV		 2147void intel_edp_psr_enable(struct intel_dp *intel_dp)
2148{
2149 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 2150 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 2151
4704c573
RV		 2152 if (!HAS_PSR(dev)) {
2153 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2154 return;
2155 }
2156
34eb7579
RV		 2157 if (!is_edp_psr(intel_dp)) {
2158 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2159 return;
2160 }
2161
f0355c4a 2162 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 2163 if (dev_priv->psr.enabled) {
2164 DRM_DEBUG_KMS("PSR already in use\n");
f0355c4a 2165 mutex_unlock(&dev_priv->psr.lock);
109fc2ad
DV		 2166 return;
2167 }
2168
9ca15301
DV		 2169 dev_priv->psr.busy_frontbuffer_bits = 0;
2170
16487254
RV		 2171 /* Setup PSR once */
2172 intel_edp_psr_setup(intel_dp);
2173
7c8f8a70 2174 if (intel_edp_psr_match_conditions(intel_dp))
9ca15301 2175 dev_priv->psr.enabled = intel_dp;
f0355c4a 2176 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2177}
2178
2b28bb1b
RV		 2179void intel_edp_psr_disable(struct intel_dp *intel_dp)
2180{
2181 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2182 struct drm_i915_private *dev_priv = dev->dev_private;
2183
f0355c4a
DV		 2184 mutex_lock(&dev_priv->psr.lock);
2185 if (!dev_priv->psr.enabled) {
2186 mutex_unlock(&dev_priv->psr.lock);
2187 return;
2188 }
2189
3638379c
DV		 2190 if (dev_priv->psr.active) {
2191 I915_WRITE(EDP_PSR_CTL(dev),
2192 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2193
2194 /* Wait till PSR is idle */
2195 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2196 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2197 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 2198
3638379c
DV		 2199 dev_priv->psr.active = false;
2200 } else {
2201 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2202 }
7c8f8a70 2203
2807cf69 2204 dev_priv->psr.enabled = NULL;
f0355c4a 2205 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 2206
2207 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 2208}
2209
f02a326e 2210static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 2211{
2212 struct drm_i915_private *dev_priv =
2213 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 2214 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2215
f0355c4a
DV		 2216 mutex_lock(&dev_priv->psr.lock);
2217 intel_dp = dev_priv->psr.enabled;
2218
2807cf69 2219 if (!intel_dp)
f0355c4a 2220 goto unlock;
2807cf69 2221
9ca15301
DV		 2222 /*
2223 * The delayed work can race with an invalidate hence we need to
2224 * recheck. Since psr_flush first clears this and then reschedules we
2225 * won't ever miss a flush when bailing out here.
2226 */
2227 if (dev_priv->psr.busy_frontbuffer_bits)
2228 goto unlock;
2229
2230 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 2231unlock:
2232 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2233}
2234
9ca15301 2235static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 2236{
2237 struct drm_i915_private *dev_priv = dev->dev_private;
2238
3638379c
DV		 2239 if (dev_priv->psr.active) {
2240 u32 val = I915_READ(EDP_PSR_CTL(dev));
2241
2242 WARN_ON(!(val & EDP_PSR_ENABLE));
2243
2244 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2245
2246 dev_priv->psr.active = false;
2247 }
7c8f8a70 2248
9ca15301
DV		 2249}
2250
2251void intel_edp_psr_invalidate(struct drm_device *dev,
2252 unsigned frontbuffer_bits)
2253{
2254 struct drm_i915_private *dev_priv = dev->dev_private;
2255 struct drm_crtc *crtc;
2256 enum pipe pipe;
2257
9ca15301
DV		 2258 mutex_lock(&dev_priv->psr.lock);
2259 if (!dev_priv->psr.enabled) {
2260 mutex_unlock(&dev_priv->psr.lock);
2261 return;
2262 }
2263
2264 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2265 pipe = to_intel_crtc(crtc)->pipe;
2266
2267 intel_edp_psr_do_exit(dev);
2268
2269 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2270
2271 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2272 mutex_unlock(&dev_priv->psr.lock);
2273}
2274
2275void intel_edp_psr_flush(struct drm_device *dev,
2276 unsigned frontbuffer_bits)
2277{
2278 struct drm_i915_private *dev_priv = dev->dev_private;
2279 struct drm_crtc *crtc;
2280 enum pipe pipe;
2281
9ca15301
DV		 2282 mutex_lock(&dev_priv->psr.lock);
2283 if (!dev_priv->psr.enabled) {
2284 mutex_unlock(&dev_priv->psr.lock);
2285 return;
2286 }
2287
2288 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2289 pipe = to_intel_crtc(crtc)->pipe;
2290 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2291
2292 /*
2293 * On Haswell sprite plane updates don't result in a psr invalidating
2294 * signal in the hardware. Which means we need to manually fake this in
2295 * software for all flushes, not just when we've seen a preceding
2296 * invalidation through frontbuffer rendering.
2297 */
2298 if (IS_HASWELL(dev) &&
2299 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2300 intel_edp_psr_do_exit(dev);
2301
2302 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2303 schedule_delayed_work(&dev_priv->psr.work,
2304 msecs_to_jiffies(100));
f0355c4a 2305 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2306}
2307
2308void intel_edp_psr_init(struct drm_device *dev)
2309{
2310 struct drm_i915_private *dev_priv = dev->dev_private;
2311
7c8f8a70 2312 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2313 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2314}
2315
e8cb4558 2316static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2317{
e8cb4558 2318 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2319 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2320
2321 /* Make sure the panel is off before trying to change the mode. But also
2322 * ensure that we have vdd while we switch off the panel. */
24f3e092 2323 intel_edp_panel_vdd_on(intel_dp);
4be73780 2324 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2325 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2326 intel_edp_panel_off(intel_dp);
3739850b 2327
08aff3fe
VS		 2328 /* disable the port before the pipe on g4x */
2329 if (INTEL_INFO(dev)->gen < 5)
3739850b 2330 intel_dp_link_down(intel_dp);
d240f20f
JB		 2331}
2332
08aff3fe 2333static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2334{
2bd2ad64 2335 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2336 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2337
49277c31 2338 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2339 if (port == PORT_A)
2340 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2341}
2342
2343static void vlv_post_disable_dp(struct intel_encoder *encoder)
2344{
2345 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2346
2347 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2348}
2349
580d3811
VS		 2350static void chv_post_disable_dp(struct intel_encoder *encoder)
2351{
2352 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2353 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2354 struct drm_device *dev = encoder->base.dev;
2355 struct drm_i915_private *dev_priv = dev->dev_private;
2356 struct intel_crtc *intel_crtc =
2357 to_intel_crtc(encoder->base.crtc);
2358 enum dpio_channel ch = vlv_dport_to_channel(dport);
2359 enum pipe pipe = intel_crtc->pipe;
2360 u32 val;
2361
2362 intel_dp_link_down(intel_dp);
2363
2364 mutex_lock(&dev_priv->dpio_lock);
2365
2366 /* Propagate soft reset to data lane reset */
97fd4d5c 2367 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2368 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2369 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2370
97fd4d5c
VS		 2371 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2372 val |= CHV_PCS_REQ_SOFTRESET_EN;
2373 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2374
2375 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2376 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2377 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2378
2379 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2380 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2381 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2382
2383 mutex_unlock(&dev_priv->dpio_lock);
2384}
2385
7b13b58a
VS		 2386static void
2387_intel_dp_set_link_train(struct intel_dp *intel_dp,
2388 uint32_t *DP,
2389 uint8_t dp_train_pat)
2390{
2391 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2392 struct drm_device *dev = intel_dig_port->base.base.dev;
2393 struct drm_i915_private *dev_priv = dev->dev_private;
2394 enum port port = intel_dig_port->port;
2395
2396 if (HAS_DDI(dev)) {
2397 uint32_t temp = I915_READ(DP_TP_CTL(port));
2398
2399 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2400 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2401 else
2402 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2403
2404 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2405 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2406 case DP_TRAINING_PATTERN_DISABLE:
2407 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2408
2409 break;
2410 case DP_TRAINING_PATTERN_1:
2411 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2412 break;
2413 case DP_TRAINING_PATTERN_2:
2414 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2415 break;
2416 case DP_TRAINING_PATTERN_3:
2417 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2418 break;
2419 }
2420 I915_WRITE(DP_TP_CTL(port), temp);
2421
2422 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2423 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2424
2425 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2426 case DP_TRAINING_PATTERN_DISABLE:
2427 *DP |= DP_LINK_TRAIN_OFF_CPT;
2428 break;
2429 case DP_TRAINING_PATTERN_1:
2430 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2431 break;
2432 case DP_TRAINING_PATTERN_2:
2433 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2434 break;
2435 case DP_TRAINING_PATTERN_3:
2436 DRM_ERROR("DP training pattern 3 not supported\n");
2437 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2438 break;
2439 }
2440
2441 } else {
2442 if (IS_CHERRYVIEW(dev))
2443 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2444 else
2445 *DP &= ~DP_LINK_TRAIN_MASK;
2446
2447 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2448 case DP_TRAINING_PATTERN_DISABLE:
2449 *DP |= DP_LINK_TRAIN_OFF;
2450 break;
2451 case DP_TRAINING_PATTERN_1:
2452 *DP |= DP_LINK_TRAIN_PAT_1;
2453 break;
2454 case DP_TRAINING_PATTERN_2:
2455 *DP |= DP_LINK_TRAIN_PAT_2;
2456 break;
2457 case DP_TRAINING_PATTERN_3:
2458 if (IS_CHERRYVIEW(dev)) {
2459 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2460 } else {
2461 DRM_ERROR("DP training pattern 3 not supported\n");
2462 *DP |= DP_LINK_TRAIN_PAT_2;
2463 }
2464 break;
2465 }
2466 }
2467}
2468
2469static void intel_dp_enable_port(struct intel_dp *intel_dp)
2470{
2471 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2472 struct drm_i915_private *dev_priv = dev->dev_private;
2473
2474 intel_dp->DP |= DP_PORT_EN;
2475
2476 /* enable with pattern 1 (as per spec) */
2477 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2478 DP_TRAINING_PATTERN_1);
2479
2480 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2481 POSTING_READ(intel_dp->output_reg);
2482}
2483
e8cb4558 2484static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2485{
e8cb4558
DV		 2486 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2487 struct drm_device *dev = encoder->base.dev;
2488 struct drm_i915_private *dev_priv = dev->dev_private;
2489 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2490
0c33d8d7
DV		 2491 if (WARN_ON(dp_reg & DP_PORT_EN))
2492 return;
5d613501 2493
7b13b58a 2494 intel_dp_enable_port(intel_dp);
24f3e092 2495 intel_edp_panel_vdd_on(intel_dp);
4be73780 2496 intel_edp_panel_on(intel_dp);
1e0560e0 2497 intel_edp_panel_vdd_off(intel_dp, true);
f01eca2e 2498 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2499 intel_dp_start_link_train(intel_dp);
33a34e4e 2500 intel_dp_complete_link_train(intel_dp);
3ab9c637 2501 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2502}
89b667f8 2503
ecff4f3b
JN		 2504static void g4x_enable_dp(struct intel_encoder *encoder)
2505{
828f5c6e
JN		 2506 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2507
ecff4f3b 2508 intel_enable_dp(encoder);
4be73780 2509 intel_edp_backlight_on(intel_dp);
ab1f90f9 2510}
89b667f8 2511
ab1f90f9
JN		 2512static void vlv_enable_dp(struct intel_encoder *encoder)
2513{
828f5c6e
JN		 2514 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2515
4be73780 2516 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2517}
2518
ecff4f3b 2519static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2520{
2521 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2522 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2523
8ac33ed3
DV		 2524 intel_dp_prepare(encoder);
2525
d41f1efb
DV		 2526 /* Only ilk+ has port A */
2527 if (dport->port == PORT_A) {
2528 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2529 ironlake_edp_pll_on(intel_dp);
d41f1efb 2530 }
ab1f90f9
JN		 2531}
2532
a4a5d2f8
VS		 2533static void vlv_steal_power_sequencer(struct drm_device *dev,
2534 enum pipe pipe)
2535{
2536 struct drm_i915_private *dev_priv = dev->dev_private;
2537 struct intel_encoder *encoder;
2538
2539 lockdep_assert_held(&dev_priv->pps_mutex);
2540
2541 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2542 base.head) {
2543 struct intel_dp *intel_dp;
773538e8 2544 enum port port;
a4a5d2f8
VS		 2545
2546 if (encoder->type != INTEL_OUTPUT_EDP)
2547 continue;
2548
2549 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2550 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2551
2552 if (intel_dp->pps_pipe != pipe)
2553 continue;
2554
2555 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2556 pipe_name(pipe), port_name(port));
a4a5d2f8
VS		 2557
2558 /* make sure vdd is off before we steal it */
2559 edp_panel_vdd_off_sync(intel_dp);
2560
2561 intel_dp->pps_pipe = INVALID_PIPE;
2562 }
2563}
2564
2565static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2566{
2567 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2568 struct intel_encoder *encoder = &intel_dig_port->base;
2569 struct drm_device *dev = encoder->base.dev;
2570 struct drm_i915_private *dev_priv = dev->dev_private;
2571 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2572 struct edp_power_seq power_seq;
2573
2574 lockdep_assert_held(&dev_priv->pps_mutex);
2575
2576 if (intel_dp->pps_pipe == crtc->pipe)
2577 return;
2578
2579 /*
2580 * If another power sequencer was being used on this
2581 * port previously make sure to turn off vdd there while
2582 * we still have control of it.
2583 */
2584 if (intel_dp->pps_pipe != INVALID_PIPE)
2585 edp_panel_vdd_off_sync(intel_dp);
2586
2587 /*
2588 * We may be stealing the power
2589 * sequencer from another port.
2590 */
2591 vlv_steal_power_sequencer(dev, crtc->pipe);
2592
2593 /* now it's all ours */
2594 intel_dp->pps_pipe = crtc->pipe;
2595
2596 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2597 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2598
2599 /* init power sequencer on this pipe and port */
2600 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2601 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2602 &power_seq);
2603}
2604
ab1f90f9 2605static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2606{
2bd2ad64 2607 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2608 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2609 struct drm_device *dev = encoder->base.dev;
89b667f8 2610 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2611 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2612 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2613 int pipe = intel_crtc->pipe;
2614 u32 val;
a4fc5ed6 2615
ab1f90f9 2616 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2617
ab3c759a 2618 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2619 val = 0;
2620 if (pipe)
2621 val |= (1<<21);
2622 else
2623 val &= ~(1<<21);
2624 val |= 0x001000c4;
ab3c759a
CML		 2625 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2626 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2627 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2628
ab1f90f9
JN		 2629 mutex_unlock(&dev_priv->dpio_lock);
2630
2cac613b 2631 if (is_edp(intel_dp)) {
773538e8 2632 pps_lock(intel_dp);
a4a5d2f8 2633 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2634 pps_unlock(intel_dp);
2cac613b 2635 }
bf13e81b 2636
ab1f90f9
JN		 2637 intel_enable_dp(encoder);
2638
e4607fcf 2639 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2640}
2641
ecff4f3b 2642static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2643{
2644 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2645 struct drm_device *dev = encoder->base.dev;
2646 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2647 struct intel_crtc *intel_crtc =
2648 to_intel_crtc(encoder->base.crtc);
e4607fcf 2649 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2650 int pipe = intel_crtc->pipe;
89b667f8 2651
8ac33ed3
DV		 2652 intel_dp_prepare(encoder);
2653
89b667f8 2654 /* Program Tx lane resets to default */
0980a60f 2655 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2656 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2657 DPIO_PCS_TX_LANE2_RESET |
2658 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2659 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2660 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2661 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2662 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2663 DPIO_PCS_CLK_SOFT_RESET);
2664
2665 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2666 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2667 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2668 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2669 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2670}
2671
e4a1d846
CML		 2672static void chv_pre_enable_dp(struct intel_encoder *encoder)
2673{
2674 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2675 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2676 struct drm_device *dev = encoder->base.dev;
2677 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2678 struct intel_crtc *intel_crtc =
2679 to_intel_crtc(encoder->base.crtc);
2680 enum dpio_channel ch = vlv_dport_to_channel(dport);
2681 int pipe = intel_crtc->pipe;
2682 int data, i;
949c1d43 2683 u32 val;
e4a1d846 2684
e4a1d846 2685 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2686
2687 /* Deassert soft data lane reset*/
97fd4d5c 2688 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2689 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2690 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2691
2692 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2693 val |= CHV_PCS_REQ_SOFTRESET_EN;
2694 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2695
2696 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2697 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2698 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2699
97fd4d5c 2700 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2701 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2702 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2703
2704 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2705 for (i = 0; i < 4; i++) {
2706 /* Set the latency optimal bit */
2707 data = (i == 1) ? 0x0 : 0x6;
2708 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2709 data << DPIO_FRC_LATENCY_SHFIT);
2710
2711 /* Set the upar bit */
2712 data = (i == 1) ? 0x0 : 0x1;
2713 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2714 data << DPIO_UPAR_SHIFT);
2715 }
2716
2717 /* Data lane stagger programming */
2718 /* FIXME: Fix up value only after power analysis */
2719
2720 mutex_unlock(&dev_priv->dpio_lock);
2721
2722 if (is_edp(intel_dp)) {
773538e8 2723 pps_lock(intel_dp);
a4a5d2f8 2724 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2725 pps_unlock(intel_dp);
e4a1d846
CML		 2726 }
2727
2728 intel_enable_dp(encoder);
2729
2730 vlv_wait_port_ready(dev_priv, dport);
2731}
2732
9197c88b
VS		 2733static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2734{
2735 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2736 struct drm_device *dev = encoder->base.dev;
2737 struct drm_i915_private *dev_priv = dev->dev_private;
2738 struct intel_crtc *intel_crtc =
2739 to_intel_crtc(encoder->base.crtc);
2740 enum dpio_channel ch = vlv_dport_to_channel(dport);
2741 enum pipe pipe = intel_crtc->pipe;
2742 u32 val;
2743
625695f8
VS		 2744 intel_dp_prepare(encoder);
2745
9197c88b
VS		 2746 mutex_lock(&dev_priv->dpio_lock);
2747
b9e5ac3c
VS		 2748 /* program left/right clock distribution */
2749 if (pipe != PIPE_B) {
2750 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2751 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2752 if (ch == DPIO_CH0)
2753 val |= CHV_BUFLEFTENA1_FORCE;
2754 if (ch == DPIO_CH1)
2755 val |= CHV_BUFRIGHTENA1_FORCE;
2756 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2757 } else {
2758 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2759 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2760 if (ch == DPIO_CH0)
2761 val |= CHV_BUFLEFTENA2_FORCE;
2762 if (ch == DPIO_CH1)
2763 val |= CHV_BUFRIGHTENA2_FORCE;
2764 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2765 }
2766
9197c88b
VS		 2767 /* program clock channel usage */
2768 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2769 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2770 if (pipe != PIPE_B)
2771 val &= ~CHV_PCS_USEDCLKCHANNEL;
2772 else
2773 val |= CHV_PCS_USEDCLKCHANNEL;
2774 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2775
2776 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2777 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2778 if (pipe != PIPE_B)
2779 val &= ~CHV_PCS_USEDCLKCHANNEL;
2780 else
2781 val |= CHV_PCS_USEDCLKCHANNEL;
2782 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2783
2784 /*
2785 * This a a bit weird since generally CL
2786 * matches the pipe, but here we need to
2787 * pick the CL based on the port.
2788 */
2789 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2790 if (pipe != PIPE_B)
2791 val &= ~CHV_CMN_USEDCLKCHANNEL;
2792 else
2793 val |= CHV_CMN_USEDCLKCHANNEL;
2794 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2795
2796 mutex_unlock(&dev_priv->dpio_lock);
2797}
2798
a4fc5ed6 2799/*
df0c237d
JB		 2800 * Native read with retry for link status and receiver capability reads for
2801 * cases where the sink may still be asleep.
9d1a1031
JN		 2802 *
2803 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2804 * supposed to retry 3 times per the spec.
a4fc5ed6 2805 */
9d1a1031
JN		 2806static ssize_t
2807intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2808 void *buffer, size_t size)
a4fc5ed6 2809{
9d1a1031
JN		 2810 ssize_t ret;
2811 int i;
61da5fab 2812
61da5fab 2813 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2814 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2815 if (ret == size)
2816 return ret;
61da5fab
JB		 2817 msleep(1);
2818 }
a4fc5ed6 2819
9d1a1031 2820 return ret;
a4fc5ed6
KP		 2821}
2822
2823/*
2824 * Fetch AUX CH registers 0x202 - 0x207 which contain
2825 * link status information
2826 */
2827static bool
93f62dad 2828intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2829{
9d1a1031
JN		 2830 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2831 DP_LANE0_1_STATUS,
2832 link_status,
2833 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2834}
2835
1100244e 2836/* These are source-specific values. */
a4fc5ed6 2837static uint8_t
1a2eb460 2838intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2839{
30add22d 2840 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2841 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2842
9576c27f 2843 if (IS_VALLEYVIEW(dev))
bd60018a 2844 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2845 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2846 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2847 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2848 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2849 else
bd60018a 2850 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2851}
2852
2853static uint8_t
2854intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2855{
30add22d 2856 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2857 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2858
9576c27f 2859 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2860 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2861 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2862 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2863 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2864 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2865 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2866 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2867 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2868 default:
bd60018a 2869 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2870 }
e2fa6fba
P		 2871 } else if (IS_VALLEYVIEW(dev)) {
2872 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2873 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2874 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2875 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2876 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2877 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2878 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2879 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2880 default:
bd60018a 2881 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2882 }
bc7d38a4 2883 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2884 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2885 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2886 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2887 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2888 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2889 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2890 default:
bd60018a 2891 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2892 }
2893 } else {
2894 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2895 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2896 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2897 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2898 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2899 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2900 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2901 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2902 default:
bd60018a 2903 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2904 }
a4fc5ed6
KP		 2905 }
2906}
2907
e2fa6fba
P		 2908static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2909{
2910 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2911 struct drm_i915_private *dev_priv = dev->dev_private;
2912 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2913 struct intel_crtc *intel_crtc =
2914 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2915 unsigned long demph_reg_value, preemph_reg_value,
2916 uniqtranscale_reg_value;
2917 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2918 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2919 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2920
2921 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2922 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2923 preemph_reg_value = 0x0004000;
2924 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2925 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2926 demph_reg_value = 0x2B405555;
2927 uniqtranscale_reg_value = 0x552AB83A;
2928 break;
bd60018a 2929 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2930 demph_reg_value = 0x2B404040;
2931 uniqtranscale_reg_value = 0x5548B83A;
2932 break;
bd60018a 2933 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2934 demph_reg_value = 0x2B245555;
2935 uniqtranscale_reg_value = 0x5560B83A;
2936 break;
bd60018a 2937 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 2938 demph_reg_value = 0x2B405555;
2939 uniqtranscale_reg_value = 0x5598DA3A;
2940 break;
2941 default:
2942 return 0;
2943 }
2944 break;
bd60018a 2945 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 2946 preemph_reg_value = 0x0002000;
2947 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2948 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2949 demph_reg_value = 0x2B404040;
2950 uniqtranscale_reg_value = 0x5552B83A;
2951 break;
bd60018a 2952 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2953 demph_reg_value = 0x2B404848;
2954 uniqtranscale_reg_value = 0x5580B83A;
2955 break;
bd60018a 2956 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2957 demph_reg_value = 0x2B404040;
2958 uniqtranscale_reg_value = 0x55ADDA3A;
2959 break;
2960 default:
2961 return 0;
2962 }
2963 break;
bd60018a 2964 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 2965 preemph_reg_value = 0x0000000;
2966 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2967 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2968 demph_reg_value = 0x2B305555;
2969 uniqtranscale_reg_value = 0x5570B83A;
2970 break;
bd60018a 2971 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2972 demph_reg_value = 0x2B2B4040;
2973 uniqtranscale_reg_value = 0x55ADDA3A;
2974 break;
2975 default:
2976 return 0;
2977 }
2978 break;
bd60018a 2979 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 2980 preemph_reg_value = 0x0006000;
2981 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2982 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2983 demph_reg_value = 0x1B405555;
2984 uniqtranscale_reg_value = 0x55ADDA3A;
2985 break;
2986 default:
2987 return 0;
2988 }
2989 break;
2990 default:
2991 return 0;
2992 }
2993
0980a60f 2994 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2995 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2996 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2997 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2998 uniqtranscale_reg_value);
ab3c759a
CML		 2999 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3000 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3001 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3002 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 3003 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 3004
3005 return 0;
3006}
3007
e4a1d846
CML		 3008static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3009{
3010 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3011 struct drm_i915_private *dev_priv = dev->dev_private;
3012 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3013 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3014 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3015 uint8_t train_set = intel_dp->train_set[0];
3016 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3017 enum pipe pipe = intel_crtc->pipe;
3018 int i;
e4a1d846
CML		 3019
3020 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3021 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3022 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3023 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3024 deemph_reg_value = 128;
3025 margin_reg_value = 52;
3026 break;
bd60018a 3027 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3028 deemph_reg_value = 128;
3029 margin_reg_value = 77;
3030 break;
bd60018a 3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3032 deemph_reg_value = 128;
3033 margin_reg_value = 102;
3034 break;
bd60018a 3035 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3036 deemph_reg_value = 128;
3037 margin_reg_value = 154;
3038 /* FIXME extra to set for 1200 */
3039 break;
3040 default:
3041 return 0;
3042 }
3043 break;
bd60018a 3044 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3045 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3047 deemph_reg_value = 85;
3048 margin_reg_value = 78;
3049 break;
bd60018a 3050 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3051 deemph_reg_value = 85;
3052 margin_reg_value = 116;
3053 break;
bd60018a 3054 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3055 deemph_reg_value = 85;
3056 margin_reg_value = 154;
3057 break;
3058 default:
3059 return 0;
3060 }
3061 break;
bd60018a 3062 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3063 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3064 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3065 deemph_reg_value = 64;
3066 margin_reg_value = 104;
3067 break;
bd60018a 3068 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3069 deemph_reg_value = 64;
3070 margin_reg_value = 154;
3071 break;
3072 default:
3073 return 0;
3074 }
3075 break;
bd60018a 3076 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3077 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3078 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3079 deemph_reg_value = 43;
3080 margin_reg_value = 154;
3081 break;
3082 default:
3083 return 0;
3084 }
3085 break;
3086 default:
3087 return 0;
3088 }
3089
3090 mutex_lock(&dev_priv->dpio_lock);
3091
3092 /* Clear calc init */
1966e59e
VS		 3093 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3094 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3095 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3096
3097 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3098 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3099 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3100
3101 /* Program swing deemph */
f72df8db
VS		 3102 for (i = 0; i < 4; i++) {
3103 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3104 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3105 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3106 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3107 }
e4a1d846
CML		 3108
3109 /* Program swing margin */
f72df8db
VS		 3110 for (i = 0; i < 4; i++) {
3111 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3112 val &= ~DPIO_SWING_MARGIN000_MASK;
3113 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3114 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3115 }
e4a1d846
CML		 3116
3117 /* Disable unique transition scale */
f72df8db
VS		 3118 for (i = 0; i < 4; i++) {
3119 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3120 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3121 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3122 }
e4a1d846
CML		 3123
3124 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3125 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3126 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3127 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3128
3129 /*
3130 * The document said it needs to set bit 27 for ch0 and bit 26
3131 * for ch1. Might be a typo in the doc.
3132 * For now, for this unique transition scale selection, set bit
3133 * 27 for ch0 and ch1.
3134 */
f72df8db
VS		 3135 for (i = 0; i < 4; i++) {
3136 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3137 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3138 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3139 }
e4a1d846 3140
f72df8db
VS		 3141 for (i = 0; i < 4; i++) {
3142 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3143 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3144 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3145 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3146 }
e4a1d846
CML		 3147 }
3148
3149 /* Start swing calculation */
1966e59e
VS		 3150 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3151 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3152 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3153
3154 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3155 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3156 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3157
3158 /* LRC Bypass */
3159 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3160 val |= DPIO_LRC_BYPASS;
3161 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3162
3163 mutex_unlock(&dev_priv->dpio_lock);
3164
3165 return 0;
3166}
3167
a4fc5ed6 3168static void
0301b3ac
JN		 3169intel_get_adjust_train(struct intel_dp *intel_dp,
3170 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3171{
3172 uint8_t v = 0;
3173 uint8_t p = 0;
3174 int lane;
1a2eb460
KP		 3175 uint8_t voltage_max;
3176 uint8_t preemph_max;
a4fc5ed6 3177
33a34e4e 3178 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3179 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3180 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3181
3182 if (this_v > v)
3183 v = this_v;
3184 if (this_p > p)
3185 p = this_p;
3186 }
3187
1a2eb460 3188 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3189 if (v >= voltage_max)
3190 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3191
1a2eb460
KP		 3192 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3193 if (p >= preemph_max)
3194 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3195
3196 for (lane = 0; lane < 4; lane++)
33a34e4e 3197 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3198}
3199
3200static uint32_t
f0a3424e 3201intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3202{
3cf2efb1 3203 uint32_t signal_levels = 0;
a4fc5ed6 3204
3cf2efb1 3205 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3206 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3207 default:
3208 signal_levels |= DP_VOLTAGE_0_4;
3209 break;
bd60018a 3210 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3211 signal_levels |= DP_VOLTAGE_0_6;
3212 break;
bd60018a 3213 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3214 signal_levels |= DP_VOLTAGE_0_8;
3215 break;
bd60018a 3216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3217 signal_levels |= DP_VOLTAGE_1_2;
3218 break;
3219 }
3cf2efb1 3220 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3221 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3222 default:
3223 signal_levels |= DP_PRE_EMPHASIS_0;
3224 break;
bd60018a 3225 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3226 signal_levels |= DP_PRE_EMPHASIS_3_5;
3227 break;
bd60018a 3228 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3229 signal_levels |= DP_PRE_EMPHASIS_6;
3230 break;
bd60018a 3231 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3232 signal_levels |= DP_PRE_EMPHASIS_9_5;
3233 break;
3234 }
3235 return signal_levels;
3236}
3237
e3421a18
ZW		 3238/* Gen6's DP voltage swing and pre-emphasis control */
3239static uint32_t
3240intel_gen6_edp_signal_levels(uint8_t train_set)
3241{
3c5a62b5
YL		 3242 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3243 DP_TRAIN_PRE_EMPHASIS_MASK);
3244 switch (signal_levels) {
bd60018a
SJ		 3245 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3246 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3247 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3248 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3249 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3250 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3251 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3252 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3253 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3254 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3255 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3256 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3257 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3258 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3259 default:
3c5a62b5
YL		 3260 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3261 "0x%x\n", signal_levels);
3262 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3263 }
3264}
3265
1a2eb460
KP		 3266/* Gen7's DP voltage swing and pre-emphasis control */
3267static uint32_t
3268intel_gen7_edp_signal_levels(uint8_t train_set)
3269{
3270 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3271 DP_TRAIN_PRE_EMPHASIS_MASK);
3272 switch (signal_levels) {
bd60018a 3273 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3274 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3275 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3276 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3277 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3278 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3279
bd60018a 3280 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3281 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3282 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3283 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3284
bd60018a 3285 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3286 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3287 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3288 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3289
3290 default:
3291 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3292 "0x%x\n", signal_levels);
3293 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3294 }
3295}
3296
d6c0d722
PZ		 3297/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3298static uint32_t
f0a3424e 3299intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3300{
d6c0d722
PZ		 3301 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3302 DP_TRAIN_PRE_EMPHASIS_MASK);
3303 switch (signal_levels) {
bd60018a 3304 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3305 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3306 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3307 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3308 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3309 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3310 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3311 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3312
bd60018a 3313 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3314 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3315 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3316 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3317 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3318 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3319
bd60018a 3320 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3321 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3322 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3323 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 3324 default:
3325 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3326 "0x%x\n", signal_levels);
c5fe6a06 3327 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3328 }
a4fc5ed6
KP		 3329}
3330
f0a3424e
PZ		 3331/* Properly updates "DP" with the correct signal levels. */
3332static void
3333intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3334{
3335 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3336 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3337 struct drm_device *dev = intel_dig_port->base.base.dev;
3338 uint32_t signal_levels, mask;
3339 uint8_t train_set = intel_dp->train_set[0];
3340
9576c27f 3341 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
f0a3424e
PZ		 3342 signal_levels = intel_hsw_signal_levels(train_set);
3343 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3344 } else if (IS_CHERRYVIEW(dev)) {
3345 signal_levels = intel_chv_signal_levels(intel_dp);
3346 mask = 0;
e2fa6fba
P		 3347 } else if (IS_VALLEYVIEW(dev)) {
3348 signal_levels = intel_vlv_signal_levels(intel_dp);
3349 mask = 0;
bc7d38a4 3350 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3351 signal_levels = intel_gen7_edp_signal_levels(train_set);
3352 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3353 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3354 signal_levels = intel_gen6_edp_signal_levels(train_set);
3355 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3356 } else {
3357 signal_levels = intel_gen4_signal_levels(train_set);
3358 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3359 }
3360
3361 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3362
3363 *DP = (*DP & ~mask) | signal_levels;
3364}
3365
a4fc5ed6 3366static bool
ea5b213a 3367intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3368 uint32_t *DP,
58e10eb9 3369 uint8_t dp_train_pat)
a4fc5ed6 3370{
174edf1f
PZ		 3371 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3372 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3373 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3374 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3375 int ret, len;
a4fc5ed6 3376
7b13b58a 3377 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3378
70aff66c 3379 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3380 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3381
2cdfe6c8
JN		 3382 buf[0] = dp_train_pat;
3383 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3384 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3385 /* don't write DP_TRAINING_LANEx_SET on disable */
3386 len = 1;
3387 } else {
3388 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3389 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3390 len = intel_dp->lane_count + 1;
47ea7542 3391 }
a4fc5ed6 3392
9d1a1031
JN		 3393 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3394 buf, len);
2cdfe6c8
JN		 3395
3396 return ret == len;
a4fc5ed6
KP		 3397}
3398
70aff66c
JN		 3399static bool
3400intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3401 uint8_t dp_train_pat)
3402{
953d22e8 3403 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3404 intel_dp_set_signal_levels(intel_dp, DP);
3405 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3406}
3407
3408static bool
3409intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3410 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3411{
3412 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3413 struct drm_device *dev = intel_dig_port->base.base.dev;
3414 struct drm_i915_private *dev_priv = dev->dev_private;
3415 int ret;
3416
3417 intel_get_adjust_train(intel_dp, link_status);
3418 intel_dp_set_signal_levels(intel_dp, DP);
3419
3420 I915_WRITE(intel_dp->output_reg, *DP);
3421 POSTING_READ(intel_dp->output_reg);
3422
9d1a1031
JN		 3423 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3424 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3425
3426 return ret == intel_dp->lane_count;
3427}
3428
3ab9c637
ID		 3429static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3430{
3431 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3432 struct drm_device *dev = intel_dig_port->base.base.dev;
3433 struct drm_i915_private *dev_priv = dev->dev_private;
3434 enum port port = intel_dig_port->port;
3435 uint32_t val;
3436
3437 if (!HAS_DDI(dev))
3438 return;
3439
3440 val = I915_READ(DP_TP_CTL(port));
3441 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3442 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3443 I915_WRITE(DP_TP_CTL(port), val);
3444
3445 /*
3446 * On PORT_A we can have only eDP in SST mode. There the only reason
3447 * we need to set idle transmission mode is to work around a HW issue
3448 * where we enable the pipe while not in idle link-training mode.
3449 * In this case there is requirement to wait for a minimum number of
3450 * idle patterns to be sent.
3451 */
3452 if (port == PORT_A)
3453 return;
3454
3455 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3456 1))
3457 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3458}
3459
33a34e4e 3460/* Enable corresponding port and start training pattern 1 */
c19b0669 3461void
33a34e4e 3462intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3463{
da63a9f2 3464 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3465 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3466 int i;
3467 uint8_t voltage;
cdb0e95b 3468 int voltage_tries, loop_tries;
ea5b213a 3469 uint32_t DP = intel_dp->DP;
6aba5b6c 3470 uint8_t link_config[2];
a4fc5ed6 3471
affa9354 3472 if (HAS_DDI(dev))
c19b0669
PZ		 3473 intel_ddi_prepare_link_retrain(encoder);
3474
3cf2efb1 3475 /* Write the link configuration data */
6aba5b6c
JN		 3476 link_config[0] = intel_dp->link_bw;
3477 link_config[1] = intel_dp->lane_count;
3478 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3479 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3480 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3481
3482 link_config[0] = 0;
3483 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3484 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3485
3486 DP |= DP_PORT_EN;
1a2eb460 3487
70aff66c
JN		 3488 /* clock recovery */
3489 if (!intel_dp_reset_link_train(intel_dp, &DP,
3490 DP_TRAINING_PATTERN_1 |
3491 DP_LINK_SCRAMBLING_DISABLE)) {
3492 DRM_ERROR("failed to enable link training\n");
3493 return;
3494 }
3495
a4fc5ed6 3496 voltage = 0xff;
cdb0e95b
KP		 3497 voltage_tries = 0;
3498 loop_tries = 0;
a4fc5ed6 3499 for (;;) {
70aff66c 3500 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3501
a7c9655f 3502 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3503 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3504 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3505 break;
93f62dad 3506 }
a4fc5ed6 3507
01916270 3508 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3509 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3510 break;
3511 }
3512
3513 /* Check to see if we've tried the max voltage */
3514 for (i = 0; i < intel_dp->lane_count; i++)
3515 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3516 break;
3b4f819d 3517 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3518 ++loop_tries;
3519 if (loop_tries == 5) {
3def84b3 3520 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3521 break;
3522 }
70aff66c
JN		 3523 intel_dp_reset_link_train(intel_dp, &DP,
3524 DP_TRAINING_PATTERN_1 |
3525 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3526 voltage_tries = 0;
3527 continue;
3528 }
a4fc5ed6 3529
3cf2efb1 3530 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3531 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3532 ++voltage_tries;
b06fbda3 3533 if (voltage_tries == 5) {
3def84b3 3534 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3535 break;
3536 }
3537 } else
3538 voltage_tries = 0;
3539 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3540
70aff66c
JN		 3541 /* Update training set as requested by target */
3542 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3543 DRM_ERROR("failed to update link training\n");
3544 break;
3545 }
a4fc5ed6
KP		 3546 }
3547
33a34e4e
JB		 3548 intel_dp->DP = DP;
3549}
3550
c19b0669 3551void
33a34e4e
JB		 3552intel_dp_complete_link_train(struct intel_dp *intel_dp)
3553{
33a34e4e 3554 bool channel_eq = false;
37f80975 3555 int tries, cr_tries;
33a34e4e 3556 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3557 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3558
3559 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3560 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3561 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3562
a4fc5ed6 3563 /* channel equalization */
70aff66c 3564 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3565 training_pattern |
70aff66c
JN		 3566 DP_LINK_SCRAMBLING_DISABLE)) {
3567 DRM_ERROR("failed to start channel equalization\n");
3568 return;
3569 }
3570
a4fc5ed6 3571 tries = 0;
37f80975 3572 cr_tries = 0;
a4fc5ed6
KP		 3573 channel_eq = false;
3574 for (;;) {
70aff66c 3575 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3576
37f80975
JB		 3577 if (cr_tries > 5) {
3578 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3579 break;
3580 }
3581
a7c9655f 3582 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3583 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3584 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3585 break;
70aff66c 3586 }
a4fc5ed6 3587
37f80975 3588 /* Make sure clock is still ok */
01916270 3589 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3590 intel_dp_start_link_train(intel_dp);
70aff66c 3591 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3592 training_pattern |
70aff66c 3593 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3594 cr_tries++;
3595 continue;
3596 }
3597
1ffdff13 3598 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3599 channel_eq = true;
3600 break;
3601 }
a4fc5ed6 3602
37f80975
JB		 3603 /* Try 5 times, then try clock recovery if that fails */
3604 if (tries > 5) {
3605 intel_dp_link_down(intel_dp);
3606 intel_dp_start_link_train(intel_dp);
70aff66c 3607 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3608 training_pattern |
70aff66c 3609 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3610 tries = 0;
3611 cr_tries++;
3612 continue;
3613 }
a4fc5ed6 3614
70aff66c
JN		 3615 /* Update training set as requested by target */
3616 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3617 DRM_ERROR("failed to update link training\n");
3618 break;
3619 }
3cf2efb1 3620 ++tries;
869184a6 3621 }
3cf2efb1 3622
3ab9c637
ID		 3623 intel_dp_set_idle_link_train(intel_dp);
3624
3625 intel_dp->DP = DP;
3626
d6c0d722 3627 if (channel_eq)
07f42258 3628 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3629
3ab9c637
ID		 3630}
3631
3632void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3633{
70aff66c 3634 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3635 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3636}
3637
3638static void
ea5b213a 3639intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3640{
da63a9f2 3641 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3642 enum port port = intel_dig_port->port;
da63a9f2 3643 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3644 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3645 struct intel_crtc *intel_crtc =
3646 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3647 uint32_t DP = intel_dp->DP;
a4fc5ed6 3648
bc76e320 3649 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3650 return;
3651
0c33d8d7 3652 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3653 return;
3654
28c97730 3655 DRM_DEBUG_KMS("\n");
32f9d658 3656
bc7d38a4 3657 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3658 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3659 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3660 } else {
aad3d14d
VS		 3661 if (IS_CHERRYVIEW(dev))
3662 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3663 else
3664 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3665 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3666 }
fe255d00 3667 POSTING_READ(intel_dp->output_reg);
5eb08b69 3668
493a7081 3669 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3670 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3671 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3672
5bddd17f
EA		 3673 /* Hardware workaround: leaving our transcoder select
3674 * set to transcoder B while it's off will prevent the
3675 * corresponding HDMI output on transcoder A.
3676 *
3677 * Combine this with another hardware workaround:
3678 * transcoder select bit can only be cleared while the
3679 * port is enabled.
3680 */
3681 DP &= ~DP_PIPEB_SELECT;
3682 I915_WRITE(intel_dp->output_reg, DP);
3683
3684 /* Changes to enable or select take place the vblank
3685 * after being written.
3686 */
ff50afe9
DV		 3687 if (WARN_ON(crtc == NULL)) {
3688 /* We should never try to disable a port without a crtc
3689 * attached. For paranoia keep the code around for a
3690 * bit. */
31acbcc4
CW		 3691 POSTING_READ(intel_dp->output_reg);
3692 msleep(50);
3693 } else
ab527efc 3694 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3695 }
3696
832afda6 3697 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3698 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3699 POSTING_READ(intel_dp->output_reg);
f01eca2e 3700 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3701}
3702
26d61aad
KP		 3703static bool
3704intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3705{
a031d709
RV		 3706 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3707 struct drm_device *dev = dig_port->base.base.dev;
3708 struct drm_i915_private *dev_priv = dev->dev_private;
3709
9d1a1031
JN		 3710 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3711 sizeof(intel_dp->dpcd)) < 0)
edb39244 3712 return false; /* aux transfer failed */
92fd8fd1 3713
a8e98153 3714 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3715
edb39244
AJ		 3716 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3717 return false; /* DPCD not present */
3718
2293bb5c
SK		 3719 /* Check if the panel supports PSR */
3720 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3721 if (is_edp(intel_dp)) {
9d1a1031
JN		 3722 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3723 intel_dp->psr_dpcd,
3724 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3725 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3726 dev_priv->psr.sink_support = true;
50003939 3727 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3728 }
50003939
JN		 3729 }
3730
06ea66b6
TP		 3731 /* Training Pattern 3 support */
3732 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3733 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3734 intel_dp->use_tps3 = true;
3735 DRM_DEBUG_KMS("Displayport TPS3 supported");
3736 } else
3737 intel_dp->use_tps3 = false;
3738
edb39244
AJ		 3739 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3740 DP_DWN_STRM_PORT_PRESENT))
3741 return true; /* native DP sink */
3742
3743 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3744 return true; /* no per-port downstream info */
3745
9d1a1031
JN		 3746 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3747 intel_dp->downstream_ports,
3748 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3749 return false; /* downstream port status fetch failed */
3750
3751 return true;
92fd8fd1
KP		 3752}
3753
0d198328
AJ		 3754static void
3755intel_dp_probe_oui(struct intel_dp *intel_dp)
3756{
3757 u8 buf[3];
3758
3759 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3760 return;
3761
24f3e092 3762 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3763
9d1a1031 3764 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3765 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3766 buf[0], buf[1], buf[2]);
3767
9d1a1031 3768 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3769 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3770 buf[0], buf[1], buf[2]);
351cfc34 3771
1e0560e0 3772 intel_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3773}
3774
0e32b39c
DA		 3775static bool
3776intel_dp_probe_mst(struct intel_dp *intel_dp)
3777{
3778 u8 buf[1];
3779
3780 if (!intel_dp->can_mst)
3781 return false;
3782
3783 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3784 return false;
3785
d337a341 3786 intel_edp_panel_vdd_on(intel_dp);
0e32b39c
DA		 3787 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3788 if (buf[0] & DP_MST_CAP) {
3789 DRM_DEBUG_KMS("Sink is MST capable\n");
3790 intel_dp->is_mst = true;
3791 } else {
3792 DRM_DEBUG_KMS("Sink is not MST capable\n");
3793 intel_dp->is_mst = false;
3794 }
3795 }
1e0560e0 3796 intel_edp_panel_vdd_off(intel_dp, false);
0e32b39c
DA		 3797
3798 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3799 return intel_dp->is_mst;
3800}
3801
d2e216d0
RV		 3802int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3803{
3804 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3805 struct drm_device *dev = intel_dig_port->base.base.dev;
3806 struct intel_crtc *intel_crtc =
3807 to_intel_crtc(intel_dig_port->base.base.crtc);
3808 u8 buf[1];
3809
9d1a1031 3810 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3811 return -EAGAIN;
3812
3813 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3814 return -ENOTTY;
3815
9d1a1031
JN		 3816 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3817 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3818 return -EAGAIN;
3819
3820 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3821 intel_wait_for_vblank(dev, intel_crtc->pipe);
3822 intel_wait_for_vblank(dev, intel_crtc->pipe);
3823
9d1a1031 3824 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3825 return -EAGAIN;
3826
9d1a1031 3827 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3828 return 0;
3829}
3830
a60f0e38
JB		 3831static bool
3832intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3833{
9d1a1031
JN		 3834 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3835 DP_DEVICE_SERVICE_IRQ_VECTOR,
3836 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3837}
3838
0e32b39c
DA		 3839static bool
3840intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3841{
3842 int ret;
3843
3844 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3845 DP_SINK_COUNT_ESI,
3846 sink_irq_vector, 14);
3847 if (ret != 14)
3848 return false;
3849
3850 return true;
3851}
3852
a60f0e38
JB		 3853static void
3854intel_dp_handle_test_request(struct intel_dp *intel_dp)
3855{
3856 /* NAK by default */
9d1a1031 3857 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3858}
3859
0e32b39c
DA		 3860static int
3861intel_dp_check_mst_status(struct intel_dp *intel_dp)
3862{
3863 bool bret;
3864
3865 if (intel_dp->is_mst) {
3866 u8 esi[16] = { 0 };
3867 int ret = 0;
3868 int retry;
3869 bool handled;
3870 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3871go_again:
3872 if (bret == true) {
3873
3874 /* check link status - esi[10] = 0x200c */
3875 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3876 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3877 intel_dp_start_link_train(intel_dp);
3878 intel_dp_complete_link_train(intel_dp);
3879 intel_dp_stop_link_train(intel_dp);
3880 }
3881
3882 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3883 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3884
3885 if (handled) {
3886 for (retry = 0; retry < 3; retry++) {
3887 int wret;
3888 wret = drm_dp_dpcd_write(&intel_dp->aux,
3889 DP_SINK_COUNT_ESI+1,
3890 &esi[1], 3);
3891 if (wret == 3) {
3892 break;
3893 }
3894 }
3895
3896 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3897 if (bret == true) {
3898 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3899 goto go_again;
3900 }
3901 } else
3902 ret = 0;
3903
3904 return ret;
3905 } else {
3906 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3907 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3908 intel_dp->is_mst = false;
3909 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3910 /* send a hotplug event */
3911 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3912 }
3913 }
3914 return -EINVAL;
3915}
3916
a4fc5ed6
KP		 3917/*
3918 * According to DP spec
3919 * 5.1.2:
3920 * 1. Read DPCD
3921 * 2. Configure link according to Receiver Capabilities
3922 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3923 * 4. Check link status on receipt of hot-plug interrupt
3924 */
00c09d70 3925void
ea5b213a 3926intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3927{
5b215bcf 3928 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3929 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3930 u8 sink_irq_vector;
93f62dad 3931 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3932
5b215bcf
DA		 3933 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3934
da63a9f2 3935 if (!intel_encoder->connectors_active)
d2b996ac 3936 return;
59cd09e1 3937
da63a9f2 3938 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3939 return;
3940
1a125d8a
ID		 3941 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3942 return;
3943
92fd8fd1 3944 /* Try to read receiver status if the link appears to be up */
93f62dad 3945 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3946 return;
3947 }
3948
92fd8fd1 3949 /* Now read the DPCD to see if it's actually running */
26d61aad 3950 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3951 return;
3952 }
3953
a60f0e38
JB		 3954 /* Try to read the source of the interrupt */
3955 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3956 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3957 /* Clear interrupt source */
9d1a1031
JN		 3958 drm_dp_dpcd_writeb(&intel_dp->aux,
3959 DP_DEVICE_SERVICE_IRQ_VECTOR,
3960 sink_irq_vector);
a60f0e38
JB		 3961
3962 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3963 intel_dp_handle_test_request(intel_dp);
3964 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3965 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3966 }
3967
1ffdff13 3968 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3969 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3970 intel_encoder->base.name);
33a34e4e
JB		 3971 intel_dp_start_link_train(intel_dp);
3972 intel_dp_complete_link_train(intel_dp);
3ab9c637 3973 intel_dp_stop_link_train(intel_dp);
33a34e4e 3974 }
a4fc5ed6 3975}
a4fc5ed6 3976
caf9ab24 3977/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3978static enum drm_connector_status
26d61aad 3979intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3980{
caf9ab24 3981 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3982 uint8_t type;
3983
3984 if (!intel_dp_get_dpcd(intel_dp))
3985 return connector_status_disconnected;
3986
3987 /* if there's no downstream port, we're done */
3988 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3989 return connector_status_connected;
caf9ab24
AJ		 3990
3991 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3992 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3993 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3994 uint8_t reg;
9d1a1031
JN		 3995
3996 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3997 &reg, 1) < 0)
caf9ab24 3998 return connector_status_unknown;
9d1a1031 3999
23235177
AJ		 4000 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4001 : connector_status_disconnected;
caf9ab24
AJ		 4002 }
4003
4004 /* If no HPD, poke DDC gently */
0b99836f 4005 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4006 return connector_status_connected;
caf9ab24
AJ		 4007
4008 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4009 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4010 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4011 if (type == DP_DS_PORT_TYPE_VGA ||
4012 type == DP_DS_PORT_TYPE_NON_EDID)
4013 return connector_status_unknown;
4014 } else {
4015 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4016 DP_DWN_STRM_PORT_TYPE_MASK;
4017 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4018 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4019 return connector_status_unknown;
4020 }
caf9ab24
AJ		 4021
4022 /* Anything else is out of spec, warn and ignore */
4023 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4024 return connector_status_disconnected;
71ba9000
AJ		 4025}
4026
d410b56d
CW		 4027static enum drm_connector_status
4028edp_detect(struct intel_dp *intel_dp)
4029{
4030 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4031 enum drm_connector_status status;
4032
4033 status = intel_panel_detect(dev);
4034 if (status == connector_status_unknown)
4035 status = connector_status_connected;
4036
4037 return status;
4038}
4039
5eb08b69 4040static enum drm_connector_status
a9756bb5 4041ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4042{
30add22d 4043 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4044 struct drm_i915_private *dev_priv = dev->dev_private;
4045 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4046
1b469639
DL		 4047 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4048 return connector_status_disconnected;
4049
26d61aad 4050 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4051}
4052
2a592bec
DA		 4053static int g4x_digital_port_connected(struct drm_device *dev,
4054 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4055{
a4fc5ed6 4056 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4057 uint32_t bit;
5eb08b69 4058
232a6ee9
TP		 4059 if (IS_VALLEYVIEW(dev)) {
4060 switch (intel_dig_port->port) {
4061 case PORT_B:
4062 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4063 break;
4064 case PORT_C:
4065 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4066 break;
4067 case PORT_D:
4068 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4069 break;
4070 default:
2a592bec 4071 return -EINVAL;
232a6ee9
TP		 4072 }
4073 } else {
4074 switch (intel_dig_port->port) {
4075 case PORT_B:
4076 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4077 break;
4078 case PORT_C:
4079 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4080 break;
4081 case PORT_D:
4082 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4083 break;
4084 default:
2a592bec 4085 return -EINVAL;
232a6ee9 4086 }
a4fc5ed6
KP		 4087 }
4088
10f76a38 4089 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4090 return 0;
4091 return 1;
4092}
4093
4094static enum drm_connector_status
4095g4x_dp_detect(struct intel_dp *intel_dp)
4096{
4097 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4098 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4099 int ret;
4100
4101 /* Can't disconnect eDP, but you can close the lid... */
4102 if (is_edp(intel_dp)) {
4103 enum drm_connector_status status;
4104
4105 status = intel_panel_detect(dev);
4106 if (status == connector_status_unknown)
4107 status = connector_status_connected;
4108 return status;
4109 }
4110
4111 ret = g4x_digital_port_connected(dev, intel_dig_port);
4112 if (ret == -EINVAL)
4113 return connector_status_unknown;
4114 else if (ret == 0)
a4fc5ed6
KP		 4115 return connector_status_disconnected;
4116
26d61aad 4117 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4118}
4119
8c241fef 4120static struct edid *
beb60608 4121intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4122{
beb60608 4123 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4124
9cd300e0
JN		 4125 /* use cached edid if we have one */
4126 if (intel_connector->edid) {
9cd300e0
JN		 4127 /* invalid edid */
4128 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4129 return NULL;
4130
55e9edeb 4131 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4132 } else
4133 return drm_get_edid(&intel_connector->base,
4134 &intel_dp->aux.ddc);
4135}
8c241fef 4136
beb60608
CW		 4137static void
4138intel_dp_set_edid(struct intel_dp *intel_dp)
4139{
4140 struct intel_connector *intel_connector = intel_dp->attached_connector;
4141 struct edid *edid;
8c241fef 4142
beb60608
CW		 4143 edid = intel_dp_get_edid(intel_dp);
4144 intel_connector->detect_edid = edid;
4145
4146 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4147 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4148 else
4149 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4150}
4151
beb60608
CW		 4152static void
4153intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4154{
beb60608 4155 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4156
beb60608
CW		 4157 kfree(intel_connector->detect_edid);
4158 intel_connector->detect_edid = NULL;
9cd300e0 4159
beb60608
CW		 4160 intel_dp->has_audio = false;
4161}
d6f24d0f 4162
beb60608
CW		 4163static enum intel_display_power_domain
4164intel_dp_power_get(struct intel_dp *dp)
4165{
4166 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4167 enum intel_display_power_domain power_domain;
4168
4169 power_domain = intel_display_port_power_domain(encoder);
4170 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4171
4172 return power_domain;
4173}
d6f24d0f 4174
beb60608
CW		 4175static void
4176intel_dp_power_put(struct intel_dp *dp,
4177 enum intel_display_power_domain power_domain)
4178{
4179 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4180 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4181}
4182
a9756bb5
ZW		 4183static enum drm_connector_status
4184intel_dp_detect(struct drm_connector *connector, bool force)
4185{
4186 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4187 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4188 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4189 struct drm_device *dev = connector->dev;
a9756bb5 4190 enum drm_connector_status status;
671dedd2 4191 enum intel_display_power_domain power_domain;
0e32b39c 4192 bool ret;
a9756bb5 4193
164c8598 4194 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4195 connector->base.id, connector->name);
beb60608 4196 intel_dp_unset_edid(intel_dp);
164c8598 4197
0e32b39c
DA		 4198 if (intel_dp->is_mst) {
4199 /* MST devices are disconnected from a monitor POV */
4200 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4201 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4202 return connector_status_disconnected;
0e32b39c
DA		 4203 }
4204
beb60608 4205 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4206
d410b56d
CW		 4207 /* Can't disconnect eDP, but you can close the lid... */
4208 if (is_edp(intel_dp))
4209 status = edp_detect(intel_dp);
4210 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4211 status = ironlake_dp_detect(intel_dp);
4212 else
4213 status = g4x_dp_detect(intel_dp);
4214 if (status != connector_status_connected)
c8c8fb33 4215 goto out;
a9756bb5 4216
0d198328
AJ		 4217 intel_dp_probe_oui(intel_dp);
4218
0e32b39c
DA		 4219 ret = intel_dp_probe_mst(intel_dp);
4220 if (ret) {
4221 /* if we are in MST mode then this connector
4222 won't appear connected or have anything with EDID on it */
4223 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4224 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4225 status = connector_status_disconnected;
4226 goto out;
4227 }
4228
beb60608 4229 intel_dp_set_edid(intel_dp);
a9756bb5 4230
d63885da
PZ		 4231 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4232 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4233 status = connector_status_connected;
4234
4235out:
beb60608 4236 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4237 return status;
a4fc5ed6
KP		 4238}
4239
beb60608
CW		 4240static void
4241intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4242{
df0e9248 4243 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4244 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4245 enum intel_display_power_domain power_domain;
a4fc5ed6 4246
beb60608
CW		 4247 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4248 connector->base.id, connector->name);
4249 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4250
beb60608
CW		 4251 if (connector->status != connector_status_connected)
4252 return;
671dedd2 4253
beb60608
CW		 4254 power_domain = intel_dp_power_get(intel_dp);
4255
4256 intel_dp_set_edid(intel_dp);
4257
4258 intel_dp_power_put(intel_dp, power_domain);
4259
4260 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4261 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4262}
4263
4264static int intel_dp_get_modes(struct drm_connector *connector)
4265{
4266 struct intel_connector *intel_connector = to_intel_connector(connector);
4267 struct edid *edid;
4268
4269 edid = intel_connector->detect_edid;
4270 if (edid) {
4271 int ret = intel_connector_update_modes(connector, edid);
4272 if (ret)
4273 return ret;
4274 }
32f9d658 4275
f8779fda 4276 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4277 if (is_edp(intel_attached_dp(connector)) &&
4278 intel_connector->panel.fixed_mode) {
f8779fda 4279 struct drm_display_mode *mode;
beb60608
CW		 4280
4281 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4282 intel_connector->panel.fixed_mode);
f8779fda 4283 if (mode) {
32f9d658
ZW		 4284 drm_mode_probed_add(connector, mode);
4285 return 1;
4286 }
4287 }
beb60608 4288
32f9d658 4289 return 0;
a4fc5ed6
KP		 4290}
4291
1aad7ac0
CW		 4292static bool
4293intel_dp_detect_audio(struct drm_connector *connector)
4294{
1aad7ac0 4295 bool has_audio = false;
beb60608 4296 struct edid *edid;
1aad7ac0 4297
beb60608
CW		 4298 edid = to_intel_connector(connector)->detect_edid;
4299 if (edid)
1aad7ac0 4300 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4301
1aad7ac0
CW		 4302 return has_audio;
4303}
4304
f684960e
CW		 4305static int
4306intel_dp_set_property(struct drm_connector *connector,
4307 struct drm_property *property,
4308 uint64_t val)
4309{
e953fd7b 4310 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4311 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4312 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4313 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4314 int ret;
4315
662595df 4316 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4317 if (ret)
4318 return ret;
4319
3f43c48d 4320 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4321 int i = val;
4322 bool has_audio;
4323
4324 if (i == intel_dp->force_audio)
f684960e
CW		 4325 return 0;
4326
1aad7ac0 4327 intel_dp->force_audio = i;
f684960e 4328
c3e5f67b 4329 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4330 has_audio = intel_dp_detect_audio(connector);
4331 else
c3e5f67b 4332 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4333
4334 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4335 return 0;
4336
1aad7ac0 4337 intel_dp->has_audio = has_audio;
f684960e
CW		 4338 goto done;
4339 }
4340
e953fd7b 4341 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4342 bool old_auto = intel_dp->color_range_auto;
4343 uint32_t old_range = intel_dp->color_range;
4344
55bc60db
VS		 4345 switch (val) {
4346 case INTEL_BROADCAST_RGB_AUTO:
4347 intel_dp->color_range_auto = true;
4348 break;
4349 case INTEL_BROADCAST_RGB_FULL:
4350 intel_dp->color_range_auto = false;
4351 intel_dp->color_range = 0;
4352 break;
4353 case INTEL_BROADCAST_RGB_LIMITED:
4354 intel_dp->color_range_auto = false;
4355 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4356 break;
4357 default:
4358 return -EINVAL;
4359 }
ae4edb80
DV		 4360
4361 if (old_auto == intel_dp->color_range_auto &&
4362 old_range == intel_dp->color_range)
4363 return 0;
4364
e953fd7b
CW		 4365 goto done;
4366 }
4367
53b41837
YN		 4368 if (is_edp(intel_dp) &&
4369 property == connector->dev->mode_config.scaling_mode_property) {
4370 if (val == DRM_MODE_SCALE_NONE) {
4371 DRM_DEBUG_KMS("no scaling not supported\n");
4372 return -EINVAL;
4373 }
4374
4375 if (intel_connector->panel.fitting_mode == val) {
4376 /* the eDP scaling property is not changed */
4377 return 0;
4378 }
4379 intel_connector->panel.fitting_mode = val;
4380
4381 goto done;
4382 }
4383
f684960e
CW		 4384 return -EINVAL;
4385
4386done:
c0c36b94
CW		 4387 if (intel_encoder->base.crtc)
4388 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4389
4390 return 0;
4391}
4392
a4fc5ed6 4393static void
73845adf 4394intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4395{
1d508706 4396 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4397
beb60608
CW		 4398 intel_dp_unset_edid(intel_attached_dp(connector));
4399
9cd300e0
JN		 4400 if (!IS_ERR_OR_NULL(intel_connector->edid))
4401 kfree(intel_connector->edid);
4402
acd8db10
PZ		 4403 /* Can't call is_edp() since the encoder may have been destroyed
4404 * already. */
4405 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4406 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4407
a4fc5ed6 4408 drm_connector_cleanup(connector);
55f78c43 4409 kfree(connector);
a4fc5ed6
KP		 4410}
4411
00c09d70 4412void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4413{
da63a9f2
PZ		 4414 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4415 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4416
4f71d0cb 4417 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4418 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4419 drm_encoder_cleanup(encoder);
bd943159
KP		 4420 if (is_edp(intel_dp)) {
4421 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4422 /*
4423 * vdd might still be enabled do to the delayed vdd off.
4424 * Make sure vdd is actually turned off here.
4425 */
773538e8 4426 pps_lock(intel_dp);
4be73780 4427 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4428 pps_unlock(intel_dp);
4429
01527b31
CT		 4430 if (intel_dp->edp_notifier.notifier_call) {
4431 unregister_reboot_notifier(&intel_dp->edp_notifier);
4432 intel_dp->edp_notifier.notifier_call = NULL;
4433 }
bd943159 4434 }
da63a9f2 4435 kfree(intel_dig_port);
24d05927
DV		 4436}
4437
07f9cd0b
ID		 4438static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4439{
4440 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4441
4442 if (!is_edp(intel_dp))
4443 return;
4444
951468f3
VS		 4445 /*
4446 * vdd might still be enabled do to the delayed vdd off.
4447 * Make sure vdd is actually turned off here.
4448 */
773538e8 4449 pps_lock(intel_dp);
07f9cd0b 4450 edp_panel_vdd_off_sync(intel_dp);
773538e8 4451 pps_unlock(intel_dp);
07f9cd0b
ID		 4452}
4453
6d93c0c4
ID		 4454static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4455{
4456 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4457}
4458
a4fc5ed6 4459static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4460 .dpms = intel_connector_dpms,
a4fc5ed6 4461 .detect = intel_dp_detect,
beb60608 4462 .force = intel_dp_force,
a4fc5ed6 4463 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4464 .set_property = intel_dp_set_property,
73845adf 4465 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4466};
4467
4468static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4469 .get_modes = intel_dp_get_modes,
4470 .mode_valid = intel_dp_mode_valid,
df0e9248 4471 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4472};
4473
a4fc5ed6 4474static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4475 .reset = intel_dp_encoder_reset,
24d05927 4476 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4477};
4478
0e32b39c 4479void
21d40d37 4480intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4481{
0e32b39c 4482 return;
c8110e52 4483}
6207937d 4484
13cf5504
DA		 4485bool
4486intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4487{
4488 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4489 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4490 struct drm_device *dev = intel_dig_port->base.base.dev;
4491 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4492 enum intel_display_power_domain power_domain;
4493 bool ret = true;
4494
0e32b39c
DA		 4495 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4496 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4497
26fbb774
VS		 4498 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4499 port_name(intel_dig_port->port),
0e32b39c 4500 long_hpd ? "long" : "short");
13cf5504 4501
1c767b33
ID		 4502 power_domain = intel_display_port_power_domain(intel_encoder);
4503 intel_display_power_get(dev_priv, power_domain);
4504
0e32b39c 4505 if (long_hpd) {
2a592bec
DA		 4506
4507 if (HAS_PCH_SPLIT(dev)) {
4508 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4509 goto mst_fail;
4510 } else {
4511 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4512 goto mst_fail;
4513 }
0e32b39c
DA		 4514
4515 if (!intel_dp_get_dpcd(intel_dp)) {
4516 goto mst_fail;
4517 }
4518
4519 intel_dp_probe_oui(intel_dp);
4520
4521 if (!intel_dp_probe_mst(intel_dp))
4522 goto mst_fail;
4523
4524 } else {
4525 if (intel_dp->is_mst) {
1c767b33 4526 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4527 goto mst_fail;
4528 }
4529
4530 if (!intel_dp->is_mst) {
4531 /*
4532 * we'll check the link status via the normal hot plug path later -
4533 * but for short hpds we should check it now
4534 */
5b215bcf 4535 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4536 intel_dp_check_link_status(intel_dp);
5b215bcf 4537 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4538 }
4539 }
1c767b33
ID		 4540 ret = false;
4541 goto put_power;
0e32b39c
DA		 4542mst_fail:
4543 /* if we were in MST mode, and device is not there get out of MST mode */
4544 if (intel_dp->is_mst) {
4545 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4546 intel_dp->is_mst = false;
4547 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4548 }
1c767b33
ID		 4549put_power:
4550 intel_display_power_put(dev_priv, power_domain);
4551
4552 return ret;
13cf5504
DA		 4553}
4554
e3421a18
ZW		 4555/* Return which DP Port should be selected for Transcoder DP control */
4556int
0206e353 4557intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4558{
4559 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4560 struct intel_encoder *intel_encoder;
4561 struct intel_dp *intel_dp;
e3421a18 4562
fa90ecef
PZ		 4563 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4564 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4565
fa90ecef
PZ		 4566 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4567 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4568 return intel_dp->output_reg;
e3421a18 4569 }
ea5b213a 4570
e3421a18
ZW		 4571 return -1;
4572}
4573
36e83a18 4574/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4575bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4576{
4577 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4578 union child_device_config *p_child;
36e83a18 4579 int i;
5d8a7752
VS		 4580 static const short port_mapping[] = {
4581 [PORT_B] = PORT_IDPB,
4582 [PORT_C] = PORT_IDPC,
4583 [PORT_D] = PORT_IDPD,
4584 };
36e83a18 4585
3b32a35b
VS		 4586 if (port == PORT_A)
4587 return true;
4588
41aa3448 4589 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4590 return false;
4591
41aa3448
RV		 4592 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4593 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4594
5d8a7752 4595 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4596 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4597 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4598 return true;
4599 }
4600 return false;
4601}
4602
0e32b39c 4603void
f684960e
CW		 4604intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4605{
53b41837
YN		 4606 struct intel_connector *intel_connector = to_intel_connector(connector);
4607
3f43c48d 4608 intel_attach_force_audio_property(connector);
e953fd7b 4609 intel_attach_broadcast_rgb_property(connector);
55bc60db 4610 intel_dp->color_range_auto = true;
53b41837
YN		 4611
4612 if (is_edp(intel_dp)) {
4613 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4614 drm_object_attach_property(
4615 &connector->base,
53b41837 4616 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4617 DRM_MODE_SCALE_ASPECT);
4618 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4619 }
f684960e
CW		 4620}
4621
dada1a9f
ID		 4622static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4623{
4624 intel_dp->last_power_cycle = jiffies;
4625 intel_dp->last_power_on = jiffies;
4626 intel_dp->last_backlight_off = jiffies;
4627}
4628
67a54566
DV		 4629static void
4630intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 4631 struct intel_dp *intel_dp,
4632 struct edp_power_seq *out)
67a54566
DV		 4633{
4634 struct drm_i915_private *dev_priv = dev->dev_private;
4635 struct edp_power_seq cur, vbt, spec, final;
4636 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4637 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4638
e39b999a
VS		 4639 lockdep_assert_held(&dev_priv->pps_mutex);
4640
453c5420 4641 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4642 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4643 pp_on_reg = PCH_PP_ON_DELAYS;
4644 pp_off_reg = PCH_PP_OFF_DELAYS;
4645 pp_div_reg = PCH_PP_DIVISOR;
4646 } else {
bf13e81b
JN		 4647 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4648
4649 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4650 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4651 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4652 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4653 }
67a54566
DV		 4654
4655 /* Workaround: Need to write PP_CONTROL with the unlock key as
4656 * the very first thing. */
453c5420 4657 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4658 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4659
453c5420
JB		 4660 pp_on = I915_READ(pp_on_reg);
4661 pp_off = I915_READ(pp_off_reg);
4662 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4663
4664 /* Pull timing values out of registers */
4665 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4666 PANEL_POWER_UP_DELAY_SHIFT;
4667
4668 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4669 PANEL_LIGHT_ON_DELAY_SHIFT;
4670
4671 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4672 PANEL_LIGHT_OFF_DELAY_SHIFT;
4673
4674 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4675 PANEL_POWER_DOWN_DELAY_SHIFT;
4676
4677 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4678 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4679
4680 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4681 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4682
41aa3448 4683 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4684
4685 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4686 * our hw here, which are all in 100usec. */
4687 spec.t1_t3 = 210 * 10;
4688 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4689 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4690 spec.t10 = 500 * 10;
4691 /* This one is special and actually in units of 100ms, but zero
4692 * based in the hw (so we need to add 100 ms). But the sw vbt
4693 * table multiplies it with 1000 to make it in units of 100usec,
4694 * too. */
4695 spec.t11_t12 = (510 + 100) * 10;
4696
4697 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4698 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4699
4700 /* Use the max of the register settings and vbt. If both are
4701 * unset, fall back to the spec limits. */
4702#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4703 spec.field : \
4704 max(cur.field, vbt.field))
4705 assign_final(t1_t3);
4706 assign_final(t8);
4707 assign_final(t9);
4708 assign_final(t10);
4709 assign_final(t11_t12);
4710#undef assign_final
4711
4712#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4713 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4714 intel_dp->backlight_on_delay = get_delay(t8);
4715 intel_dp->backlight_off_delay = get_delay(t9);
4716 intel_dp->panel_power_down_delay = get_delay(t10);
4717 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4718#undef get_delay
4719
f30d26e4
JN		 4720 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4721 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4722 intel_dp->panel_power_cycle_delay);
4723
4724 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4725 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4726
4727 if (out)
4728 *out = final;
4729}
4730
4731static void
4732intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4733 struct intel_dp *intel_dp,
4734 struct edp_power_seq *seq)
4735{
4736 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4737 u32 pp_on, pp_off, pp_div, port_sel = 0;
4738 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4739 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4740 enum port port = dp_to_dig_port(intel_dp)->port;
453c5420 4741
e39b999a 4742 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 4743
4744 if (HAS_PCH_SPLIT(dev)) {
4745 pp_on_reg = PCH_PP_ON_DELAYS;
4746 pp_off_reg = PCH_PP_OFF_DELAYS;
4747 pp_div_reg = PCH_PP_DIVISOR;
4748 } else {
bf13e81b
JN		 4749 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4750
4751 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4752 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4753 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4754 }
4755
b2f19d1a
PZ		 4756 /*
4757 * And finally store the new values in the power sequencer. The
4758 * backlight delays are set to 1 because we do manual waits on them. For
4759 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4760 * we'll end up waiting for the backlight off delay twice: once when we
4761 * do the manual sleep, and once when we disable the panel and wait for
4762 * the PP_STATUS bit to become zero.
4763 */
f30d26e4 4764 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4765 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4766 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4767 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4768 /* Compute the divisor for the pp clock, simply match the Bspec
4769 * formula. */
453c5420 4770 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4771 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4772 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4773
4774 /* Haswell doesn't have any port selection bits for the panel
4775 * power sequencer any more. */
bc7d38a4 4776 if (IS_VALLEYVIEW(dev)) {
ad933b56 4777 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4778 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4779 if (port == PORT_A)
a24c144c 4780 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4781 else
a24c144c 4782 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4783 }
4784
453c5420
JB		 4785 pp_on |= port_sel;
4786
4787 I915_WRITE(pp_on_reg, pp_on);
4788 I915_WRITE(pp_off_reg, pp_off);
4789 I915_WRITE(pp_div_reg, pp_div);
67a54566 4790
67a54566 4791 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4792 I915_READ(pp_on_reg),
4793 I915_READ(pp_off_reg),
4794 I915_READ(pp_div_reg));
f684960e
CW		 4795}
4796
439d7ac0
PB		 4797void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4798{
4799 struct drm_i915_private *dev_priv = dev->dev_private;
4800 struct intel_encoder *encoder;
4801 struct intel_dp *intel_dp = NULL;
4802 struct intel_crtc_config *config = NULL;
4803 struct intel_crtc *intel_crtc = NULL;
4804 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4805 u32 reg, val;
4806 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4807
4808 if (refresh_rate <= 0) {
4809 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4810 return;
4811 }
4812
4813 if (intel_connector == NULL) {
4814 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4815 return;
4816 }
4817
1fcc9d1c
DV		 4818 /*
4819 * FIXME: This needs proper synchronization with psr state. But really
4820 * hard to tell without seeing the user of this function of this code.
4821 * Check locking and ordering once that lands.
4822 */
439d7ac0
PB		 4823 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4824 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4825 return;
4826 }
4827
4828 encoder = intel_attached_encoder(&intel_connector->base);
4829 intel_dp = enc_to_intel_dp(&encoder->base);
4830 intel_crtc = encoder->new_crtc;
4831
4832 if (!intel_crtc) {
4833 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4834 return;
4835 }
4836
4837 config = &intel_crtc->config;
4838
4839 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4840 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4841 return;
4842 }
4843
4844 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4845 index = DRRS_LOW_RR;
4846
4847 if (index == intel_dp->drrs_state.refresh_rate_type) {
4848 DRM_DEBUG_KMS(
4849 "DRRS requested for previously set RR...ignoring\n");
4850 return;
4851 }
4852
4853 if (!intel_crtc->active) {
4854 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4855 return;
4856 }
4857
4858 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4859 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4860 val = I915_READ(reg);
4861 if (index > DRRS_HIGH_RR) {
4862 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4863 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4864 } else {
4865 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4866 }
4867 I915_WRITE(reg, val);
4868 }
4869
4870 /*
4871 * mutex taken to ensure that there is no race between differnt
4872 * drrs calls trying to update refresh rate. This scenario may occur
4873 * in future when idleness detection based DRRS in kernel and
4874 * possible calls from user space to set differnt RR are made.
4875 */
4876
4877 mutex_lock(&intel_dp->drrs_state.mutex);
4878
4879 intel_dp->drrs_state.refresh_rate_type = index;
4880
4881 mutex_unlock(&intel_dp->drrs_state.mutex);
4882
4883 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4884}
4885
4f9db5b5
PB		 4886static struct drm_display_mode *
4887intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4888 struct intel_connector *intel_connector,
4889 struct drm_display_mode *fixed_mode)
4890{
4891 struct drm_connector *connector = &intel_connector->base;
4892 struct intel_dp *intel_dp = &intel_dig_port->dp;
4893 struct drm_device *dev = intel_dig_port->base.base.dev;
4894 struct drm_i915_private *dev_priv = dev->dev_private;
4895 struct drm_display_mode *downclock_mode = NULL;
4896
4897 if (INTEL_INFO(dev)->gen <= 6) {
4898 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4899 return NULL;
4900 }
4901
4902 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 4903 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 4904 return NULL;
4905 }
4906
4907 downclock_mode = intel_find_panel_downclock
4908 (dev, fixed_mode, connector);
4909
4910 if (!downclock_mode) {
4079b8d1 4911 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 4912 return NULL;
4913 }
4914
439d7ac0
PB		 4915 dev_priv->drrs.connector = intel_connector;
4916
4917 mutex_init(&intel_dp->drrs_state.mutex);
4918
4f9db5b5
PB		 4919 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4920
4921 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 4922 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 4923 return downclock_mode;
4924}
4925
aba86890
ID		 4926void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4927{
4928 struct drm_device *dev = intel_encoder->base.dev;
4929 struct drm_i915_private *dev_priv = dev->dev_private;
4930 struct intel_dp *intel_dp;
4931 enum intel_display_power_domain power_domain;
4932
4933 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4934 return;
4935
4936 intel_dp = enc_to_intel_dp(&intel_encoder->base);
773538e8
VS		 4937
4938 pps_lock(intel_dp);
4939
aba86890 4940 if (!edp_have_panel_vdd(intel_dp))
e39b999a 4941 goto out;
aba86890
ID		 4942 /*
4943 * The VDD bit needs a power domain reference, so if the bit is
4944 * already enabled when we boot or resume, grab this reference and
4945 * schedule a vdd off, so we don't hold on to the reference
4946 * indefinitely.
4947 */
4948 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4949 power_domain = intel_display_port_power_domain(intel_encoder);
4950 intel_display_power_get(dev_priv, power_domain);
4951
4952 edp_panel_vdd_schedule_off(intel_dp);
e39b999a 4953 out:
773538e8 4954 pps_unlock(intel_dp);
aba86890
ID		 4955}
4956
ed92f0b2 4957static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4958 struct intel_connector *intel_connector,
4959 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4960{
4961 struct drm_connector *connector = &intel_connector->base;
4962 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4963 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4964 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4965 struct drm_i915_private *dev_priv = dev->dev_private;
4966 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4967 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4968 bool has_dpcd;
4969 struct drm_display_mode *scan;
4970 struct edid *edid;
4971
4f9db5b5
PB		 4972 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4973
ed92f0b2
PZ		 4974 if (!is_edp(intel_dp))
4975 return true;
4976
aba86890 4977 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 4978
ed92f0b2 4979 /* Cache DPCD and EDID for edp. */
24f3e092 4980 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4981 has_dpcd = intel_dp_get_dpcd(intel_dp);
1e0560e0 4982 intel_edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4983
4984 if (has_dpcd) {
4985 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4986 dev_priv->no_aux_handshake =
4987 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4988 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4989 } else {
4990 /* if this fails, presume the device is a ghost */
4991 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4992 return false;
4993 }
4994
4995 /* We now know it's not a ghost, init power sequence regs. */
773538e8 4996 pps_lock(intel_dp);
0095e6dc 4997 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
773538e8 4998 pps_unlock(intel_dp);
ed92f0b2 4999
060c8778 5000 mutex_lock(&dev->mode_config.mutex);
0b99836f 5001 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5002 if (edid) {
5003 if (drm_add_edid_modes(connector, edid)) {
5004 drm_mode_connector_update_edid_property(connector,
5005 edid);
5006 drm_edid_to_eld(connector, edid);
5007 } else {
5008 kfree(edid);
5009 edid = ERR_PTR(-EINVAL);
5010 }
5011 } else {
5012 edid = ERR_PTR(-ENOENT);
5013 }
5014 intel_connector->edid = edid;
5015
5016 /* prefer fixed mode from EDID if available */
5017 list_for_each_entry(scan, &connector->probed_modes, head) {
5018 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5019 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 5020 downclock_mode = intel_dp_drrs_init(
5021 intel_dig_port,
5022 intel_connector, fixed_mode);
ed92f0b2
PZ		 5023 break;
5024 }
5025 }
5026
5027 /* fallback to VBT if available for eDP */
5028 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5029 fixed_mode = drm_mode_duplicate(dev,
5030 dev_priv->vbt.lfp_lvds_vbt_mode);
5031 if (fixed_mode)
5032 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5033 }
060c8778 5034 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5035
01527b31
CT		 5036 if (IS_VALLEYVIEW(dev)) {
5037 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5038 register_reboot_notifier(&intel_dp->edp_notifier);
5039 }
5040
4f9db5b5 5041 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5042 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 5043 intel_panel_setup_backlight(connector);
5044
5045 return true;
5046}
5047
16c25533 5048bool
f0fec3f2
PZ		 5049intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5050 struct intel_connector *intel_connector)
a4fc5ed6 5051{
f0fec3f2
PZ		 5052 struct drm_connector *connector = &intel_connector->base;
5053 struct intel_dp *intel_dp = &intel_dig_port->dp;
5054 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5055 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5056 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5057 enum port port = intel_dig_port->port;
0095e6dc 5058 struct edp_power_seq power_seq = { 0 };
0b99836f 5059 int type;
a4fc5ed6 5060
a4a5d2f8
VS		 5061 intel_dp->pps_pipe = INVALID_PIPE;
5062
ec5b01dd
DL		 5063 /* intel_dp vfuncs */
5064 if (IS_VALLEYVIEW(dev))
5065 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5066 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5067 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5068 else if (HAS_PCH_SPLIT(dev))
5069 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5070 else
5071 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5072
153b1100
DL		 5073 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5074
0767935e
DV		 5075 /* Preserve the current hw state. */
5076 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5077 intel_dp->attached_connector = intel_connector;
3d3dc149 5078
3b32a35b 5079 if (intel_dp_is_edp(dev, port))
b329530c 5080 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5081 else
5082 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5083
f7d24902
ID		 5084 /*
5085 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5086 * for DP the encoder type can be set by the caller to
5087 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5088 */
5089 if (type == DRM_MODE_CONNECTOR_eDP)
5090 intel_encoder->type = INTEL_OUTPUT_EDP;
5091
e7281eab
ID		 5092 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5093 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5094 port_name(port));
5095
b329530c 5096 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5097 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5098
a4fc5ed6
KP		 5099 connector->interlace_allowed = true;
5100 connector->doublescan_allowed = 0;
5101
f0fec3f2 5102 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5103 edp_panel_vdd_work);
a4fc5ed6 5104
df0e9248 5105 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5106 drm_connector_register(connector);
a4fc5ed6 5107
affa9354 5108 if (HAS_DDI(dev))
bcbc889b
PZ		 5109 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5110 else
5111 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5112 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5113
0b99836f 5114 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5115 switch (port) {
5116 case PORT_A:
1d843f9d 5117 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5118 break;
5119 case PORT_B:
1d843f9d 5120 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5121 break;
5122 case PORT_C:
1d843f9d 5123 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5124 break;
5125 case PORT_D:
1d843f9d 5126 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5127 break;
5128 default:
ad1c0b19 5129 BUG();
5eb08b69
ZW		 5130 }
5131
dada1a9f 5132 if (is_edp(intel_dp)) {
773538e8 5133 pps_lock(intel_dp);
a4a5d2f8
VS		 5134 if (IS_VALLEYVIEW(dev)) {
5135 vlv_initial_power_sequencer_setup(intel_dp);
5136 } else {
5137 intel_dp_init_panel_power_timestamps(intel_dp);
5138 intel_dp_init_panel_power_sequencer(dev, intel_dp,
5139 &power_seq);
5140 }
773538e8 5141 pps_unlock(intel_dp);
dada1a9f 5142 }
0095e6dc 5143
9d1a1031 5144 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5145
0e32b39c
DA		 5146 /* init MST on ports that can support it */
5147 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5148 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5149 intel_dp_mst_encoder_init(intel_dig_port,
5150 intel_connector->base.base.id);
0e32b39c
DA		 5151 }
5152 }
5153
0095e6dc 5154 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 5155 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5156 if (is_edp(intel_dp)) {
5157 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5158 /*
5159 * vdd might still be enabled do to the delayed vdd off.
5160 * Make sure vdd is actually turned off here.
5161 */
773538e8 5162 pps_lock(intel_dp);
4be73780 5163 edp_panel_vdd_off_sync(intel_dp);
773538e8 5164 pps_unlock(intel_dp);
15b1d171 5165 }
34ea3d38 5166 drm_connector_unregister(connector);
b2f246a8 5167 drm_connector_cleanup(connector);
16c25533 5168 return false;
b2f246a8 5169 }
32f9d658 5170
f684960e
CW		 5171 intel_dp_add_properties(intel_dp, connector);
5172
a4fc5ed6
KP		 5173 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5174 * 0xd. Failure to do so will result in spurious interrupts being
5175 * generated on the port when a cable is not attached.
5176 */
5177 if (IS_G4X(dev) && !IS_GM45(dev)) {
5178 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5179 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5180 }
16c25533
PZ		 5181
5182 return true;
a4fc5ed6 5183}
f0fec3f2
PZ		 5184
5185void
5186intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5187{
13cf5504 5188 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5189 struct intel_digital_port *intel_dig_port;
5190 struct intel_encoder *intel_encoder;
5191 struct drm_encoder *encoder;
5192 struct intel_connector *intel_connector;
5193
b14c5679 5194 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5195 if (!intel_dig_port)
5196 return;
5197
b14c5679 5198 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5199 if (!intel_connector) {
5200 kfree(intel_dig_port);
5201 return;
5202 }
5203
5204 intel_encoder = &intel_dig_port->base;
5205 encoder = &intel_encoder->base;
5206
5207 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5208 DRM_MODE_ENCODER_TMDS);
5209
5bfe2ac0 5210 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5211 intel_encoder->disable = intel_disable_dp;
00c09d70 5212 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5213 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5214 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5215 if (IS_CHERRYVIEW(dev)) {
9197c88b 5216 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5217 intel_encoder->pre_enable = chv_pre_enable_dp;
5218 intel_encoder->enable = vlv_enable_dp;
580d3811 5219 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5220 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5221 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5222 intel_encoder->pre_enable = vlv_pre_enable_dp;
5223 intel_encoder->enable = vlv_enable_dp;
49277c31 5224 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5225 } else {
ecff4f3b
JN		 5226 intel_encoder->pre_enable = g4x_pre_enable_dp;
5227 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5228 if (INTEL_INFO(dev)->gen >= 5)
5229 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5230 }
f0fec3f2 5231
174edf1f 5232 intel_dig_port->port = port;
f0fec3f2
PZ		 5233 intel_dig_port->dp.output_reg = output_reg;
5234
00c09d70 5235 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5236 if (IS_CHERRYVIEW(dev)) {
5237 if (port == PORT_D)
5238 intel_encoder->crtc_mask = 1 << 2;
5239 else
5240 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5241 } else {
5242 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5243 }
bc079e8b 5244 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5245 intel_encoder->hot_plug = intel_dp_hot_plug;
5246
13cf5504
DA		 5247 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5248 dev_priv->hpd_irq_port[port] = intel_dig_port;
5249
15b1d171
PZ		 5250 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5251 drm_encoder_cleanup(encoder);
5252 kfree(intel_dig_port);
b2f246a8 5253 kfree(intel_connector);
15b1d171 5254 }
f0fec3f2 5255}
0e32b39c
DA		 5256
5257void intel_dp_mst_suspend(struct drm_device *dev)
5258{
5259 struct drm_i915_private *dev_priv = dev->dev_private;
5260 int i;
5261
5262 /* disable MST */
5263 for (i = 0; i < I915_MAX_PORTS; i++) {
5264 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5265 if (!intel_dig_port)
5266 continue;
5267
5268 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5269 if (!intel_dig_port->dp.can_mst)
5270 continue;
5271 if (intel_dig_port->dp.is_mst)
5272 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5273 }
5274 }
5275}
5276
5277void intel_dp_mst_resume(struct drm_device *dev)
5278{
5279 struct drm_i915_private *dev_priv = dev->dev_private;
5280 int i;
5281
5282 for (i = 0; i < I915_MAX_PORTS; i++) {
5283 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5284 if (!intel_dig_port)
5285 continue;
5286 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5287 int ret;
5288
5289 if (!intel_dig_port->dp.can_mst)
5290 continue;
5291
5292 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5293 if (ret != 0) {
5294 intel_dp_check_mst_status(&intel_dig_port->dp);
5295 }
5296 }
5297 }
5298}
Linux kernel - Deliverables
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