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* breakpoint.c (insert_bp_location): Add newline to note.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
67a4f2b7 3 2000, 2001, 2002, 2003, 2004, 2005, 2006
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
d182319b 83static void signed_cons PARAMS ((int));
29b0f896
AM		 84static char *output_invalid PARAMS ((int c));
85static int i386_operand PARAMS ((char *operand_string));
86static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
87static const reg_entry *parse_register PARAMS ((char *reg_string,
88 char **end_op));
89static char *parse_insn PARAMS ((char *, char *));
90static char *parse_operands PARAMS ((char *, const char *));
91static void swap_operands PARAMS ((void));
050dfa73 92static void swap_imm_operands PARAMS ((void));
29b0f896
AM		 93static void optimize_imm PARAMS ((void));
94static void optimize_disp PARAMS ((void));
95static int match_template PARAMS ((void));
96static int check_string PARAMS ((void));
97static int process_suffix PARAMS ((void));
98static int check_byte_reg PARAMS ((void));
99static int check_long_reg PARAMS ((void));
100static int check_qword_reg PARAMS ((void));
101static int check_word_reg PARAMS ((void));
102static int finalize_imm PARAMS ((void));
103static int process_operands PARAMS ((void));
104static const seg_entry *build_modrm_byte PARAMS ((void));
105static void output_insn PARAMS ((void));
106static void output_branch PARAMS ((void));
107static void output_jump PARAMS ((void));
108static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 109static void output_imm PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
111static void output_disp PARAMS ((fragS *insn_start_frag,
112 offsetT insn_start_off));
29b0f896
AM		 113#ifndef I386COFF
114static void s_bss PARAMS ((int));
252b5132 115#endif
17d4e2a2
L		 116#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
117static void handle_large_common (int small ATTRIBUTE_UNUSED);
118#endif
252b5132 119
a847613f 120static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 121
252b5132 122/* 'md_assemble ()' gathers together information and puts it into a
47926f60 123 i386_insn. */
252b5132 124
520dc8e8
AM		 125union i386_op
126 {
127 expressionS *disps;
128 expressionS *imms;
129 const reg_entry *regs;
130 };
131
252b5132
RH		 132struct _i386_insn
133 {
47926f60 134 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 135 template tm;
136
137 /* SUFFIX holds the instruction mnemonic suffix if given.
138 (e.g. 'l' for 'movl') */
139 char suffix;
140
47926f60 141 /* OPERANDS gives the number of given operands. */
252b5132
RH		 142 unsigned int operands;
143
144 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
145 of given register, displacement, memory operands and immediate
47926f60 146 operands. */
252b5132
RH		 147 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
148
149 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 150 use OP[i] for the corresponding operand. */
252b5132
RH		 151 unsigned int types[MAX_OPERANDS];
152
520dc8e8
AM		 153 /* Displacement expression, immediate expression, or register for each
154 operand. */
155 union i386_op op[MAX_OPERANDS];
252b5132 156
3e73aa7c
JH		 157 /* Flags for operands. */
158 unsigned int flags[MAX_OPERANDS];
159#define Operand_PCrel 1
160
252b5132 161 /* Relocation type for operand */
f86103b7 162 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 163
252b5132
RH		 164 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
165 the base index byte below. */
166 const reg_entry *base_reg;
167 const reg_entry *index_reg;
168 unsigned int log2_scale_factor;
169
170 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 171 explicit segment overrides are given. */
ce8a8b2f 172 const seg_entry *seg[2];
252b5132
RH		 173
174 /* PREFIX holds all the given prefix opcodes (usually null).
175 PREFIXES is the number of prefix opcodes. */
176 unsigned int prefixes;
177 unsigned char prefix[MAX_PREFIXES];
178
179 /* RM and SIB are the modrm byte and the sib byte where the
180 addressing modes of this insn are encoded. */
181
182 modrm_byte rm;
3e73aa7c 183 rex_byte rex;
252b5132
RH		 184 sib_byte sib;
185 };
186
187typedef struct _i386_insn i386_insn;
188
189/* List of chars besides those in app.c:symbol_chars that can start an
190 operand. Used to prevent the scrubber eating vital white-space. */
32137342 191const char extra_symbol_chars[] = "*%-(["
252b5132 192#ifdef LEX_AT
32137342
NC		 193 "@"
194#endif
195#ifdef LEX_QM
196 "?"
252b5132 197#endif
32137342 198 ;
252b5132 199
29b0f896
AM		 200#if (defined (TE_I386AIX) \
201 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 202 && !defined (TE_GNU) \
29b0f896 203 && !defined (TE_LINUX) \
32137342 204 && !defined (TE_NETWARE) \
29b0f896
AM		 205 && !defined (TE_FreeBSD) \
206 && !defined (TE_NetBSD)))
252b5132 207/* This array holds the chars that always start a comment. If the
b3b91714
AM		 208 pre-processor is disabled, these aren't very useful. The option
209 --divide will remove '/' from this list. */
210const char *i386_comment_chars = "#/";
211#define SVR4_COMMENT_CHARS 1
252b5132 212#define PREFIX_SEPARATOR '\\'
252b5132 213
b3b91714
AM		 214#else
215const char *i386_comment_chars = "#";
216#define PREFIX_SEPARATOR '/'
217#endif
218
252b5132
RH		 219/* This array holds the chars that only start a comment at the beginning of
220 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 221 .line and .file directives will appear in the pre-processed output.
222 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 223 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 224 #NO_APP at the beginning of its output.
225 Also note that comments started like this one will always work if
252b5132 226 '/' isn't otherwise defined. */
b3b91714 227const char line_comment_chars[] = "#/";
252b5132 228
63a0b638 229const char line_separator_chars[] = ";";
252b5132 230
ce8a8b2f
AM		 231/* Chars that can be used to separate mant from exp in floating point
232 nums. */
252b5132
RH		 233const char EXP_CHARS[] = "eE";
234
ce8a8b2f
AM		 235/* Chars that mean this number is a floating point constant
236 As in 0f12.456
237 or 0d1.2345e12. */
252b5132
RH		 238const char FLT_CHARS[] = "fFdDxX";
239
ce8a8b2f 240/* Tables for lexical analysis. */
252b5132
RH		 241static char mnemonic_chars[256];
242static char register_chars[256];
243static char operand_chars[256];
244static char identifier_chars[256];
245static char digit_chars[256];
246
ce8a8b2f 247/* Lexical macros. */
252b5132
RH		 248#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
249#define is_operand_char(x) (operand_chars[(unsigned char) x])
250#define is_register_char(x) (register_chars[(unsigned char) x])
251#define is_space_char(x) ((x) == ' ')
252#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
253#define is_digit_char(x) (digit_chars[(unsigned char) x])
254
0234cb7c 255/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 256static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
257
258/* md_assemble() always leaves the strings it's passed unaltered. To
259 effect this we maintain a stack of saved characters that we've smashed
260 with '\0's (indicating end of strings for various sub-fields of the
47926f60 261 assembler instruction). */
252b5132 262static char save_stack[32];
ce8a8b2f 263static char *save_stack_p;
252b5132
RH		 264#define END_STRING_AND_SAVE(s) \
265 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
266#define RESTORE_END_STRING(s) \
267 do { *(s) = *--save_stack_p; } while (0)
268
47926f60 269/* The instruction we're assembling. */
252b5132
RH		 270static i386_insn i;
271
272/* Possible templates for current insn. */
273static const templates *current_templates;
274
47926f60 275/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 276static expressionS disp_expressions[2], im_expressions[2];
277
47926f60
KH		 278/* Current operand we are working on. */
279static int this_operand;
252b5132 280
3e73aa7c
JH		 281/* We support four different modes. FLAG_CODE variable is used to distinguish
282 these. */
283
284enum flag_code {
285 CODE_32BIT,
286 CODE_16BIT,
287 CODE_64BIT };
f3c180ae 288#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 289
290static enum flag_code flag_code;
4fa24527 291static unsigned int object_64bit;
3e73aa7c
JH		 292static int use_rela_relocations = 0;
293
294/* The names used to print error messages. */
b77a7acd 295static const char *flag_code_names[] =
3e73aa7c
JH		 296 {
297 "32",
298 "16",
299 "64"
300 };
252b5132 301
47926f60
KH		 302/* 1 for intel syntax,
303 0 if att syntax. */
304static int intel_syntax = 0;
252b5132 305
47926f60
KH		 306/* 1 if register prefix % not required. */
307static int allow_naked_reg = 0;
252b5132 308
47926f60
KH		 309/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
310 leave, push, and pop instructions so that gcc has the same stack
311 frame as in 32 bit mode. */
312static char stackop_size = '\0';
eecb386c 313
12b55ccc
L		 314/* Non-zero to optimize code alignment. */
315int optimize_align_code = 1;
316
47926f60
KH		 317/* Non-zero to quieten some warnings. */
318static int quiet_warnings = 0;
a38cf1db 319
47926f60
KH		 320/* CPU name. */
321static const char *cpu_arch_name = NULL;
5c6af06e 322static const char *cpu_sub_arch_name = NULL;
a38cf1db 323
47926f60 324/* CPU feature flags. */
29b0f896 325static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 326
ccc9c027
L		 327/* If we have selected a cpu we are generating instructions for. */
328static int cpu_arch_tune_set = 0;
329
9103f4f4
L		 330/* Cpu we are generating instructions for. */
331static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
332
333/* CPU feature flags of cpu we are generating instructions for. */
334static unsigned int cpu_arch_tune_flags = 0;
335
ccc9c027
L		 336/* CPU instruction set architecture used. */
337static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
338
9103f4f4
L		 339/* CPU feature flags of instruction set architecture used. */
340static unsigned int cpu_arch_isa_flags = 0;
341
fddf5b5b
AM		 342/* If set, conditional jumps are not automatically promoted to handle
343 larger than a byte offset. */
344static unsigned int no_cond_jump_promotion = 0;
345
29b0f896 346/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 347static symbolS *GOT_symbol;
29b0f896 348
a4447b93
RH		 349/* The dwarf2 return column, adjusted for 32 or 64 bit. */
350unsigned int x86_dwarf2_return_column;
351
352/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
353int x86_cie_data_alignment;
354
252b5132 355/* Interface to relax_segment.
fddf5b5b
AM		 356 There are 3 major relax states for 386 jump insns because the
357 different types of jumps add different sizes to frags when we're
358 figuring out what sort of jump to choose to reach a given label. */
252b5132 359
47926f60 360/* Types. */
93c2a809
AM		 361#define UNCOND_JUMP 0
362#define COND_JUMP 1
363#define COND_JUMP86 2
fddf5b5b 364
47926f60 365/* Sizes. */
252b5132
RH		 366#define CODE16 1
367#define SMALL 0
29b0f896 368#define SMALL16 (SMALL | CODE16)
252b5132 369#define BIG 2
29b0f896 370#define BIG16 (BIG | CODE16)
252b5132
RH		 371
372#ifndef INLINE
373#ifdef __GNUC__
374#define INLINE __inline__
375#else
376#define INLINE
377#endif
378#endif
379
fddf5b5b
AM		 380#define ENCODE_RELAX_STATE(type, size) \
381 ((relax_substateT) (((type) << 2) | (size)))
382#define TYPE_FROM_RELAX_STATE(s) \
383 ((s) >> 2)
384#define DISP_SIZE_FROM_RELAX_STATE(s) \
385 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 386
387/* This table is used by relax_frag to promote short jumps to long
388 ones where necessary. SMALL (short) jumps may be promoted to BIG
389 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
390 don't allow a short jump in a 32 bit code segment to be promoted to
391 a 16 bit offset jump because it's slower (requires data size
392 prefix), and doesn't work, unless the destination is in the bottom
393 64k of the code segment (The top 16 bits of eip are zeroed). */
394
395const relax_typeS md_relax_table[] =
396{
24eab124
AM		 397 /* The fields are:
398 1) most positive reach of this state,
399 2) most negative reach of this state,
93c2a809 400 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 401 4) which index into the table to try if we can't fit into this one. */
252b5132 402
fddf5b5b 403 /* UNCOND_JUMP states. */
93c2a809
AM		 404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
406 /* dword jmp adds 4 bytes to frag:
407 0 extra opcode bytes, 4 displacement bytes. */
252b5132 408 {0, 0, 4, 0},
93c2a809
AM		 409 /* word jmp adds 2 byte2 to frag:
410 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 411 {0, 0, 2, 0},
412
93c2a809
AM		 413 /* COND_JUMP states. */
414 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
415 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
416 /* dword conditionals adds 5 bytes to frag:
417 1 extra opcode byte, 4 displacement bytes. */
418 {0, 0, 5, 0},
fddf5b5b 419 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 420 1 extra opcode byte, 2 displacement bytes. */
421 {0, 0, 3, 0},
422
423 /* COND_JUMP86 states. */
424 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
425 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
426 /* dword conditionals adds 5 bytes to frag:
427 1 extra opcode byte, 4 displacement bytes. */
428 {0, 0, 5, 0},
429 /* word conditionals add 4 bytes to frag:
430 1 displacement byte and a 3 byte long branch insn. */
431 {0, 0, 4, 0}
252b5132
RH		 432};
433
9103f4f4
L		 434static const arch_entry cpu_arch[] =
435{
436 {"generic32", PROCESSOR_GENERIC32,
d32cad65 437 Cpu186|Cpu286|Cpu386},
9103f4f4 438 {"generic64", PROCESSOR_GENERIC64,
d32cad65 439 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 440 |CpuMMX2|CpuSSE|CpuSSE2},
441 {"i8086", PROCESSOR_UNKNOWN,
d32cad65 442 0},
9103f4f4 443 {"i186", PROCESSOR_UNKNOWN,
d32cad65 444 Cpu186},
9103f4f4 445 {"i286", PROCESSOR_UNKNOWN,
d32cad65 446 Cpu186|Cpu286},
9103f4f4 447 {"i386", PROCESSOR_GENERIC32,
d32cad65 448 Cpu186|Cpu286|Cpu386},
9103f4f4 449 {"i486", PROCESSOR_I486,
d32cad65 450 Cpu186|Cpu286|Cpu386|Cpu486},
9103f4f4 451 {"i586", PROCESSOR_PENTIUM,
d32cad65 452 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 453 {"i686", PROCESSOR_PENTIUMPRO,
d32cad65 454 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 455 {"pentium", PROCESSOR_PENTIUM,
d32cad65 456 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 457 {"pentiumpro",PROCESSOR_PENTIUMPRO,
d32cad65 458 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 459 {"pentiumii", PROCESSOR_PENTIUMPRO,
d32cad65 460 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
9103f4f4 461 {"pentiumiii",PROCESSOR_PENTIUMPRO,
d32cad65 462 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
9103f4f4 463 {"pentium4", PROCESSOR_PENTIUM4,
d32cad65 464 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 465 |CpuMMX2|CpuSSE|CpuSSE2},
466 {"prescott", PROCESSOR_NOCONA,
d32cad65 467 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 468 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
469 {"nocona", PROCESSOR_NOCONA,
d32cad65 470 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 471 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 472 {"yonah", PROCESSOR_CORE,
d32cad65 473 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 474 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 475 {"core", PROCESSOR_CORE,
d32cad65 476 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
ef05d495
L		 477 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
478 {"merom", PROCESSOR_CORE2,
479 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
480 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
481 {"core2", PROCESSOR_CORE2,
482 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
483 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4 484 {"k6", PROCESSOR_K6,
d32cad65 485 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
9103f4f4 486 {"k6_2", PROCESSOR_K6,
d32cad65 487 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
9103f4f4 488 {"athlon", PROCESSOR_ATHLON,
d32cad65 489 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 490 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
491 {"sledgehammer", PROCESSOR_K8,
d32cad65 492 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 493 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
494 {"opteron", PROCESSOR_K8,
d32cad65 495 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 496 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
497 {"k8", PROCESSOR_K8,
d32cad65 498 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4 499 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
050dfa73 500 {"amdfam10", PROCESSOR_AMDFAM10,
d32cad65
L		 501 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
502 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
503 |CpuABM},
9103f4f4
L		 504 {".mmx", PROCESSOR_UNKNOWN,
505 CpuMMX},
506 {".sse", PROCESSOR_UNKNOWN,
507 CpuMMX|CpuMMX2|CpuSSE},
508 {".sse2", PROCESSOR_UNKNOWN,
509 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
510 {".sse3", PROCESSOR_UNKNOWN,
511 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495
L		 512 {".ssse3", PROCESSOR_UNKNOWN,
513 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4
L		 514 {".3dnow", PROCESSOR_UNKNOWN,
515 CpuMMX|Cpu3dnow},
516 {".3dnowa", PROCESSOR_UNKNOWN,
517 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
518 {".padlock", PROCESSOR_UNKNOWN,
519 CpuPadLock},
520 {".pacifica", PROCESSOR_UNKNOWN,
521 CpuSVME},
522 {".svme", PROCESSOR_UNKNOWN,
050dfa73
MM		 523 CpuSVME},
524 {".sse4a", PROCESSOR_UNKNOWN,
525 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
526 {".abm", PROCESSOR_UNKNOWN,
527 CpuABM}
e413e4e9
AM		 528};
529
29b0f896
AM		 530const pseudo_typeS md_pseudo_table[] =
531{
532#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
533 {"align", s_align_bytes, 0},
534#else
535 {"align", s_align_ptwo, 0},
536#endif
537 {"arch", set_cpu_arch, 0},
538#ifndef I386COFF
539 {"bss", s_bss, 0},
540#endif
541 {"ffloat", float_cons, 'f'},
542 {"dfloat", float_cons, 'd'},
543 {"tfloat", float_cons, 'x'},
544 {"value", cons, 2},
d182319b 545 {"slong", signed_cons, 4},
29b0f896
AM		 546 {"noopt", s_ignore, 0},
547 {"optim", s_ignore, 0},
548 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
549 {"code16", set_code_flag, CODE_16BIT},
550 {"code32", set_code_flag, CODE_32BIT},
551 {"code64", set_code_flag, CODE_64BIT},
552 {"intel_syntax", set_intel_syntax, 1},
553 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 554#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
555 {"largecomm", handle_large_common, 0},
07a53e5c
RH		 556#else
557 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
558 {"loc", dwarf2_directive_loc, 0},
559 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 560#endif
6482c264
NC		 561#ifdef TE_PE
562 {"secrel32", pe_directive_secrel, 0},
563#endif
29b0f896
AM		 564 {0, 0, 0}
565};
566
567/* For interface with expression (). */
568extern char *input_line_pointer;
569
570/* Hash table for instruction mnemonic lookup. */
571static struct hash_control *op_hash;
572
573/* Hash table for register lookup. */
574static struct hash_control *reg_hash;
575\f
252b5132
RH		 576void
577i386_align_code (fragP, count)
578 fragS *fragP;
579 int count;
580{
ce8a8b2f
AM		 581 /* Various efficient no-op patterns for aligning code labels.
582 Note: Don't try to assemble the instructions in the comments.
583 0L and 0w are not legal. */
252b5132
RH		 584 static const char f32_1[] =
585 {0x90}; /* nop */
586 static const char f32_2[] =
ccc9c027 587 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 588 static const char f32_3[] =
589 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
590 static const char f32_4[] =
591 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
592 static const char f32_5[] =
593 {0x90, /* nop */
594 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
595 static const char f32_6[] =
596 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
597 static const char f32_7[] =
598 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
599 static const char f32_8[] =
600 {0x90, /* nop */
601 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
602 static const char f32_9[] =
603 {0x89,0xf6, /* movl %esi,%esi */
604 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
605 static const char f32_10[] =
606 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
607 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
608 static const char f32_11[] =
609 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
610 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
611 static const char f32_12[] =
612 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
613 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
614 static const char f32_13[] =
615 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
616 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
617 static const char f32_14[] =
618 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
619 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
620 static const char f32_15[] =
621 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
622 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 623 static const char f16_3[] =
624 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 625 static const char f16_4[] =
626 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
627 static const char f16_5[] =
628 {0x90, /* nop */
629 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
630 static const char f16_6[] =
631 {0x89,0xf6, /* mov %si,%si */
632 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
633 static const char f16_7[] =
634 {0x8d,0x74,0x00, /* lea 0(%si),%si */
635 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
636 static const char f16_8[] =
637 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
638 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
639 static const char *const f32_patt[] = {
640 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
641 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
642 };
643 static const char *const f16_patt[] = {
c3332e24 644 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 645 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
646 };
ccc9c027
L		 647 /* nopl (%[re]ax) */
648 static const char alt_3[] =
649 {0x0f,0x1f,0x00};
650 /* nopl 0(%[re]ax) */
651 static const char alt_4[] =
652 {0x0f,0x1f,0x40,0x00};
653 /* nopl 0(%[re]ax,%[re]ax,1) */
654 static const char alt_5[] =
655 {0x0f,0x1f,0x44,0x00,0x00};
656 /* nopw 0(%[re]ax,%[re]ax,1) */
657 static const char alt_6[] =
658 {0x66,0x0f,0x1f,0x44,0x00,0x00};
659 /* nopl 0L(%[re]ax) */
660 static const char alt_7[] =
661 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
662 /* nopl 0L(%[re]ax,%[re]ax,1) */
663 static const char alt_8[] =
664 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
665 /* nopw 0L(%[re]ax,%[re]ax,1) */
666 static const char alt_9[] =
667 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
668 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
669 static const char alt_10[] =
670 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
671 /* data16
672 nopw %cs:0L(%[re]ax,%[re]ax,1) */
673 static const char alt_long_11[] =
674 {0x66,
675 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
676 /* data16
677 data16
678 nopw %cs:0L(%[re]ax,%[re]ax,1) */
679 static const char alt_long_12[] =
680 {0x66,
681 0x66,
682 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
683 /* data16
684 data16
685 data16
686 nopw %cs:0L(%[re]ax,%[re]ax,1) */
687 static const char alt_long_13[] =
688 {0x66,
689 0x66,
690 0x66,
691 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
692 /* data16
693 data16
694 data16
695 data16
696 nopw %cs:0L(%[re]ax,%[re]ax,1) */
697 static const char alt_long_14[] =
698 {0x66,
699 0x66,
700 0x66,
701 0x66,
702 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
703 /* data16
704 data16
705 data16
706 data16
707 data16
708 nopw %cs:0L(%[re]ax,%[re]ax,1) */
709 static const char alt_long_15[] =
710 {0x66,
711 0x66,
712 0x66,
713 0x66,
714 0x66,
715 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
716 /* nopl 0(%[re]ax,%[re]ax,1)
717 nopw 0(%[re]ax,%[re]ax,1) */
718 static const char alt_short_11[] =
719 {0x0f,0x1f,0x44,0x00,0x00,
720 0x66,0x0f,0x1f,0x44,0x00,0x00};
721 /* nopw 0(%[re]ax,%[re]ax,1)
722 nopw 0(%[re]ax,%[re]ax,1) */
723 static const char alt_short_12[] =
724 {0x66,0x0f,0x1f,0x44,0x00,0x00,
725 0x66,0x0f,0x1f,0x44,0x00,0x00};
726 /* nopw 0(%[re]ax,%[re]ax,1)
727 nopl 0L(%[re]ax) */
728 static const char alt_short_13[] =
729 {0x66,0x0f,0x1f,0x44,0x00,0x00,
730 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
731 /* nopl 0L(%[re]ax)
732 nopl 0L(%[re]ax) */
733 static const char alt_short_14[] =
734 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
735 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
736 /* nopl 0L(%[re]ax)
737 nopl 0L(%[re]ax,%[re]ax,1) */
738 static const char alt_short_15[] =
739 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
740 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
741 static const char *const alt_short_patt[] = {
742 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
743 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
744 alt_short_14, alt_short_15
745 };
746 static const char *const alt_long_patt[] = {
747 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
748 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
749 alt_long_14, alt_long_15
750 };
252b5132 751
33fef721
JH		 752 if (count <= 0 || count > 15)
753 return;
3e73aa7c 754
ccc9c027
L		 755 /* We need to decide which NOP sequence to use for 32bit and
756 64bit. When -mtune= is used:
757
758 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
759 f32_patt will be used.
050dfa73 760 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with 0x66 prefix will be used.
ef05d495 761 3. For PROCESSOR_CORE2, alt_long_patt will be used.
ccc9c027 762 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
ef05d495 763 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
ccc9c027
L		 764 and PROCESSOR_GENERIC64, alt_short_patt will be used.
765
766 When -mtune= isn't used, alt_short_patt will be used if
767 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
768
769 When -march= or .arch is used, we can't use anything beyond
770 cpu_arch_isa_flags. */
771
772 if (flag_code == CODE_16BIT)
773 {
774 memcpy (fragP->fr_literal + fragP->fr_fix,
775 f16_patt[count - 1], count);
776 if (count > 8)
777 /* Adjust jump offset. */
778 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
779 }
780 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
252b5132 781 {
33fef721
JH		 782 int i;
783 int nnops = (count + 3) / 4;
784 int len = count / nnops;
785 int remains = count - nnops * len;
786 int pos = 0;
787
ccc9c027
L		 788 /* The recommended way to pad 64bit code is to use NOPs preceded
789 by maximally four 0x66 prefixes. Balance the size of nops. */
33fef721 790 for (i = 0; i < remains; i++)
252b5132 791 {
33fef721
JH		 792 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
793 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
794 pos += len + 1;
795 }
796 for (; i < nnops; i++)
797 {
798 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
799 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
800 pos += len;
252b5132 801 }
252b5132 802 }
33fef721 803 else
ccc9c027
L		 804 {
805 const char *const *patt = NULL;
806
807 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
808 {
809 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
810 switch (cpu_arch_tune)
811 {
812 case PROCESSOR_UNKNOWN:
813 /* We use cpu_arch_isa_flags to check if we SHOULD
814 optimize for Cpu686. */
815 if ((cpu_arch_isa_flags & Cpu686) != 0)
816 patt = alt_short_patt;
817 else
818 patt = f32_patt;
819 break;
ef05d495 820 case PROCESSOR_CORE2:
ccc9c027
L		 821 patt = alt_long_patt;
822 break;
823 case PROCESSOR_PENTIUMPRO:
824 case PROCESSOR_PENTIUM4:
825 case PROCESSOR_NOCONA:
ef05d495 826 case PROCESSOR_CORE:
ccc9c027
L		 827 case PROCESSOR_K6:
828 case PROCESSOR_ATHLON:
829 case PROCESSOR_K8:
830 case PROCESSOR_GENERIC64:
050dfa73 831 case PROCESSOR_AMDFAM10:
ccc9c027
L		 832 patt = alt_short_patt;
833 break;
834 case PROCESSOR_I486:
835 case PROCESSOR_PENTIUM:
836 case PROCESSOR_GENERIC32:
837 patt = f32_patt;
838 break;
839 }
840 }
841 else
842 {
843 switch (cpu_arch_tune)
844 {
845 case PROCESSOR_UNKNOWN:
846 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
847 PROCESSOR_UNKNOWN. */
848 abort ();
849 break;
850
851 case PROCESSOR_I486:
852 case PROCESSOR_PENTIUM:
853 case PROCESSOR_PENTIUMPRO:
854 case PROCESSOR_PENTIUM4:
855 case PROCESSOR_NOCONA:
ef05d495 856 case PROCESSOR_CORE:
ccc9c027
L		 857 case PROCESSOR_K6:
858 case PROCESSOR_ATHLON:
859 case PROCESSOR_K8:
050dfa73 860 case PROCESSOR_AMDFAM10:
ccc9c027
L		 861 case PROCESSOR_GENERIC32:
862 /* We use cpu_arch_isa_flags to check if we CAN optimize
863 for Cpu686. */
864 if ((cpu_arch_isa_flags & Cpu686) != 0)
865 patt = alt_short_patt;
866 else
867 patt = f32_patt;
868 break;
ef05d495 869 case PROCESSOR_CORE2:
ccc9c027
L		 870 if ((cpu_arch_isa_flags & Cpu686) != 0)
871 patt = alt_long_patt;
872 else
873 patt = f32_patt;
874 break;
875 case PROCESSOR_GENERIC64:
876 patt = alt_short_patt;
877 break;
878 }
879 }
880
33fef721 881 memcpy (fragP->fr_literal + fragP->fr_fix,
ccc9c027
L		 882 patt[count - 1], count);
883 }
33fef721 884 fragP->fr_var = count;
252b5132
RH		 885}
886
252b5132
RH		 887static INLINE unsigned int
888mode_from_disp_size (t)
889 unsigned int t;
890{
3e73aa7c 891 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 892}
893
894static INLINE int
895fits_in_signed_byte (num)
847f7ad4 896 offsetT num;
252b5132
RH		 897{
898 return (num >= -128) && (num <= 127);
47926f60 899}
252b5132
RH		 900
901static INLINE int
902fits_in_unsigned_byte (num)
847f7ad4 903 offsetT num;
252b5132
RH		 904{
905 return (num & 0xff) == num;
47926f60 906}
252b5132
RH		 907
908static INLINE int
909fits_in_unsigned_word (num)
847f7ad4 910 offsetT num;
252b5132
RH		 911{
912 return (num & 0xffff) == num;
47926f60 913}
252b5132
RH		 914
915static INLINE int
916fits_in_signed_word (num)
847f7ad4 917 offsetT num;
252b5132
RH		 918{
919 return (-32768 <= num) && (num <= 32767);
47926f60 920}
3e73aa7c
JH		 921static INLINE int
922fits_in_signed_long (num)
923 offsetT num ATTRIBUTE_UNUSED;
924{
925#ifndef BFD64
926 return 1;
927#else
928 return (!(((offsetT) -1 << 31) & num)
929 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
930#endif
931} /* fits_in_signed_long() */
932static INLINE int
933fits_in_unsigned_long (num)
934 offsetT num ATTRIBUTE_UNUSED;
935{
936#ifndef BFD64
937 return 1;
938#else
939 return (num & (((offsetT) 2 << 31) - 1)) == num;
940#endif
941} /* fits_in_unsigned_long() */
252b5132
RH		 942
943static int
944smallest_imm_type (num)
847f7ad4 945 offsetT num;
252b5132 946{
d32cad65 947 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 948 {
949 /* This code is disabled on the 486 because all the Imm1 forms
950 in the opcode table are slower on the i486. They're the
951 versions with the implicitly specified single-position
952 displacement, which has another syntax if you really want to
953 use that form. */
954 if (num == 1)
3e73aa7c 955 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 956 }
252b5132 957 return (fits_in_signed_byte (num)
3e73aa7c 958 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 959 : fits_in_unsigned_byte (num)
3e73aa7c 960 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 961 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 962 ? (Imm16 | Imm32 | Imm32S | Imm64)
963 : fits_in_signed_long (num)
964 ? (Imm32 | Imm32S | Imm64)
965 : fits_in_unsigned_long (num)
966 ? (Imm32 | Imm64)
967 : Imm64);
47926f60 968}
252b5132 969
847f7ad4
AM		 970static offsetT
971offset_in_range (val, size)
972 offsetT val;
973 int size;
974{
508866be 975 addressT mask;
ba2adb93 976
847f7ad4
AM		 977 switch (size)
978 {
508866be
L		 979 case 1: mask = ((addressT) 1 << 8) - 1; break;
980 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 981 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 982#ifdef BFD64
983 case 8: mask = ((addressT) 2 << 63) - 1; break;
984#endif
47926f60 985 default: abort ();
847f7ad4
AM		 986 }
987
ba2adb93 988 /* If BFD64, sign extend val. */
3e73aa7c
JH		 989 if (!use_rela_relocations)
990 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
991 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 992
47926f60 993 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 994 {
995 char buf1[40], buf2[40];
996
997 sprint_value (buf1, val);
998 sprint_value (buf2, val & mask);
999 as_warn (_("%s shortened to %s"), buf1, buf2);
1000 }
1001 return val & mask;
1002}
1003
252b5132
RH		 1004/* Returns 0 if attempting to add a prefix where one from the same
1005 class already exists, 1 if non rep/repne added, 2 if rep/repne
1006 added. */
1007static int
1008add_prefix (prefix)
1009 unsigned int prefix;
1010{
1011 int ret = 1;
b1905489 1012 unsigned int q;
252b5132 1013
29b0f896
AM		 1014 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1015 && flag_code == CODE_64BIT)
b1905489
JB		 1016 {
1017 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
1018 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
1019 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
1020 ret = 0;
1021 q = REX_PREFIX;
1022 }
3e73aa7c 1023 else
b1905489
JB		 1024 {
1025 switch (prefix)
1026 {
1027 default:
1028 abort ();
1029
1030 case CS_PREFIX_OPCODE:
1031 case DS_PREFIX_OPCODE:
1032 case ES_PREFIX_OPCODE:
1033 case FS_PREFIX_OPCODE:
1034 case GS_PREFIX_OPCODE:
1035 case SS_PREFIX_OPCODE:
1036 q = SEG_PREFIX;
1037 break;
1038
1039 case REPNE_PREFIX_OPCODE:
1040 case REPE_PREFIX_OPCODE:
1041 ret = 2;
1042 /* fall thru */
1043 case LOCK_PREFIX_OPCODE:
1044 q = LOCKREP_PREFIX;
1045 break;
1046
1047 case FWAIT_OPCODE:
1048 q = WAIT_PREFIX;
1049 break;
1050
1051 case ADDR_PREFIX_OPCODE:
1052 q = ADDR_PREFIX;
1053 break;
1054
1055 case DATA_PREFIX_OPCODE:
1056 q = DATA_PREFIX;
1057 break;
1058 }
1059 if (i.prefix[q] != 0)
1060 ret = 0;
1061 }
252b5132 1062
b1905489 1063 if (ret)
252b5132 1064 {
b1905489
JB		 1065 if (!i.prefix[q])
1066 ++i.prefixes;
1067 i.prefix[q] |= prefix;
252b5132 1068 }
b1905489
JB		 1069 else
1070 as_bad (_("same type of prefix used twice"));
252b5132 1071
252b5132
RH		 1072 return ret;
1073}
1074
1075static void
3e73aa7c 1076set_code_flag (value)
e5cb08ac 1077 int value;
eecb386c 1078{
3e73aa7c
JH		 1079 flag_code = value;
1080 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1081 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1082 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1083 {
1084 as_bad (_("64bit mode not supported on this CPU."));
1085 }
1086 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1087 {
1088 as_bad (_("32bit mode not supported on this CPU."));
1089 }
eecb386c
AM		 1090 stackop_size = '\0';
1091}
1092
1093static void
3e73aa7c
JH		 1094set_16bit_gcc_code_flag (new_code_flag)
1095 int new_code_flag;
252b5132 1096{
3e73aa7c
JH		 1097 flag_code = new_code_flag;
1098 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1099 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 1100 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1101}
1102
1103static void
1104set_intel_syntax (syntax_flag)
eecb386c 1105 int syntax_flag;
252b5132
RH		 1106{
1107 /* Find out if register prefixing is specified. */
1108 int ask_naked_reg = 0;
1109
1110 SKIP_WHITESPACE ();
29b0f896 1111 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1112 {
1113 char *string = input_line_pointer;
1114 int e = get_symbol_end ();
1115
47926f60 1116 if (strcmp (string, "prefix") == 0)
252b5132 1117 ask_naked_reg = 1;
47926f60 1118 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1119 ask_naked_reg = -1;
1120 else
d0b47220 1121 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1122 *input_line_pointer = e;
1123 }
1124 demand_empty_rest_of_line ();
c3332e24 1125
252b5132
RH		 1126 intel_syntax = syntax_flag;
1127
1128 if (ask_naked_reg == 0)
f86103b7
AM		 1129 allow_naked_reg = (intel_syntax
1130 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1131 else
1132 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 1133
1134 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1135 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 1136}
1137
e413e4e9
AM		 1138static void
1139set_cpu_arch (dummy)
47926f60 1140 int dummy ATTRIBUTE_UNUSED;
e413e4e9 1141{
47926f60 1142 SKIP_WHITESPACE ();
e413e4e9 1143
29b0f896 1144 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1145 {
1146 char *string = input_line_pointer;
1147 int e = get_symbol_end ();
9103f4f4 1148 unsigned int i;
e413e4e9 1149
9103f4f4 1150 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1151 {
1152 if (strcmp (string, cpu_arch[i].name) == 0)
1153 {
5c6af06e
JB		 1154 if (*string != '.')
1155 {
1156 cpu_arch_name = cpu_arch[i].name;
1157 cpu_sub_arch_name = NULL;
1158 cpu_arch_flags = (cpu_arch[i].flags
1159 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
ccc9c027 1160 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1161 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1162 if (!cpu_arch_tune_set)
1163 {
1164 cpu_arch_tune = cpu_arch_isa;
1165 cpu_arch_tune_flags = cpu_arch_isa_flags;
1166 }
5c6af06e
JB		 1167 break;
1168 }
1169 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1170 {
1171 cpu_sub_arch_name = cpu_arch[i].name;
1172 cpu_arch_flags |= cpu_arch[i].flags;
1173 }
1174 *input_line_pointer = e;
1175 demand_empty_rest_of_line ();
1176 return;
e413e4e9
AM		 1177 }
1178 }
9103f4f4 1179 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1180 as_bad (_("no such architecture: `%s'"), string);
1181
1182 *input_line_pointer = e;
1183 }
1184 else
1185 as_bad (_("missing cpu architecture"));
1186
fddf5b5b
AM		 1187 no_cond_jump_promotion = 0;
1188 if (*input_line_pointer == ','
29b0f896 1189 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1190 {
1191 char *string = ++input_line_pointer;
1192 int e = get_symbol_end ();
1193
1194 if (strcmp (string, "nojumps") == 0)
1195 no_cond_jump_promotion = 1;
1196 else if (strcmp (string, "jumps") == 0)
1197 ;
1198 else
1199 as_bad (_("no such architecture modifier: `%s'"), string);
1200
1201 *input_line_pointer = e;
1202 }
1203
e413e4e9
AM		 1204 demand_empty_rest_of_line ();
1205}
1206
b9d79e03
JH		 1207unsigned long
1208i386_mach ()
1209{
1210 if (!strcmp (default_arch, "x86_64"))
1211 return bfd_mach_x86_64;
1212 else if (!strcmp (default_arch, "i386"))
1213 return bfd_mach_i386_i386;
1214 else
1215 as_fatal (_("Unknown architecture"));
1216}
b9d79e03 1217\f
252b5132
RH		 1218void
1219md_begin ()
1220{
1221 const char *hash_err;
1222
47926f60 1223 /* Initialize op_hash hash table. */
252b5132
RH		 1224 op_hash = hash_new ();
1225
1226 {
29b0f896
AM		 1227 const template *optab;
1228 templates *core_optab;
252b5132 1229
47926f60
KH		 1230 /* Setup for loop. */
1231 optab = i386_optab;
252b5132
RH		 1232 core_optab = (templates *) xmalloc (sizeof (templates));
1233 core_optab->start = optab;
1234
1235 while (1)
1236 {
1237 ++optab;
1238 if (optab->name == NULL
1239 || strcmp (optab->name, (optab - 1)->name) != 0)
1240 {
1241 /* different name --> ship out current template list;
47926f60 1242 add to hash table; & begin anew. */
252b5132
RH		 1243 core_optab->end = optab;
1244 hash_err = hash_insert (op_hash,
1245 (optab - 1)->name,
1246 (PTR) core_optab);
1247 if (hash_err)
1248 {
252b5132
RH		 1249 as_fatal (_("Internal Error: Can't hash %s: %s"),
1250 (optab - 1)->name,
1251 hash_err);
1252 }
1253 if (optab->name == NULL)
1254 break;
1255 core_optab = (templates *) xmalloc (sizeof (templates));
1256 core_optab->start = optab;
1257 }
1258 }
1259 }
1260
47926f60 1261 /* Initialize reg_hash hash table. */
252b5132
RH		 1262 reg_hash = hash_new ();
1263 {
29b0f896 1264 const reg_entry *regtab;
252b5132
RH		 1265
1266 for (regtab = i386_regtab;
1267 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
1268 regtab++)
1269 {
1270 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1271 if (hash_err)
3e73aa7c
JH		 1272 as_fatal (_("Internal Error: Can't hash %s: %s"),
1273 regtab->reg_name,
1274 hash_err);
252b5132
RH		 1275 }
1276 }
1277
47926f60 1278 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1279 {
29b0f896
AM		 1280 int c;
1281 char *p;
252b5132
RH		 1282
1283 for (c = 0; c < 256; c++)
1284 {
3882b010 1285 if (ISDIGIT (c))
252b5132
RH		 1286 {
1287 digit_chars[c] = c;
1288 mnemonic_chars[c] = c;
1289 register_chars[c] = c;
1290 operand_chars[c] = c;
1291 }
3882b010 1292 else if (ISLOWER (c))
252b5132
RH		 1293 {
1294 mnemonic_chars[c] = c;
1295 register_chars[c] = c;
1296 operand_chars[c] = c;
1297 }
3882b010 1298 else if (ISUPPER (c))
252b5132 1299 {
3882b010 1300 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1301 register_chars[c] = mnemonic_chars[c];
1302 operand_chars[c] = c;
1303 }
1304
3882b010 1305 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1306 identifier_chars[c] = c;
1307 else if (c >= 128)
1308 {
1309 identifier_chars[c] = c;
1310 operand_chars[c] = c;
1311 }
1312 }
1313
1314#ifdef LEX_AT
1315 identifier_chars['@'] = '@';
32137342
NC		 1316#endif
1317#ifdef LEX_QM
1318 identifier_chars['?'] = '?';
1319 operand_chars['?'] = '?';
252b5132 1320#endif
252b5132 1321 digit_chars['-'] = '-';
791fe849 1322 mnemonic_chars['-'] = '-';
252b5132
RH		 1323 identifier_chars['_'] = '_';
1324 identifier_chars['.'] = '.';
1325
1326 for (p = operand_special_chars; *p != '\0'; p++)
1327 operand_chars[(unsigned char) *p] = *p;
1328 }
1329
1330#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1331 if (IS_ELF)
252b5132
RH		 1332 {
1333 record_alignment (text_section, 2);
1334 record_alignment (data_section, 2);
1335 record_alignment (bss_section, 2);
1336 }
1337#endif
a4447b93
RH		 1338
1339 if (flag_code == CODE_64BIT)
1340 {
1341 x86_dwarf2_return_column = 16;
1342 x86_cie_data_alignment = -8;
1343 }
1344 else
1345 {
1346 x86_dwarf2_return_column = 8;
1347 x86_cie_data_alignment = -4;
1348 }
252b5132
RH		 1349}
1350
1351void
1352i386_print_statistics (file)
1353 FILE *file;
1354{
1355 hash_print_statistics (file, "i386 opcode", op_hash);
1356 hash_print_statistics (file, "i386 register", reg_hash);
1357}
1358\f
252b5132
RH		 1359#ifdef DEBUG386
1360
ce8a8b2f 1361/* Debugging routines for md_assemble. */
252b5132
RH		 1362static void pi PARAMS ((char *, i386_insn *));
1363static void pte PARAMS ((template *));
1364static void pt PARAMS ((unsigned int));
1365static void pe PARAMS ((expressionS *));
1366static void ps PARAMS ((symbolS *));
1367
1368static void
1369pi (line, x)
1370 char *line;
1371 i386_insn *x;
1372{
09f131f2 1373 unsigned int i;
252b5132
RH		 1374
1375 fprintf (stdout, "%s: template ", line);
1376 pte (&x->tm);
09f131f2
JH		 1377 fprintf (stdout, " address: base %s index %s scale %x\n",
1378 x->base_reg ? x->base_reg->reg_name : "none",
1379 x->index_reg ? x->index_reg->reg_name : "none",
1380 x->log2_scale_factor);
1381 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1382 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1383 fprintf (stdout, " sib: base %x index %x scale %x\n",
1384 x->sib.base, x->sib.index, x->sib.scale);
1385 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1386 (x->rex & REX_MODE64) != 0,
1387 (x->rex & REX_EXTX) != 0,
1388 (x->rex & REX_EXTY) != 0,
1389 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1390 for (i = 0; i < x->operands; i++)
1391 {
1392 fprintf (stdout, " #%d: ", i + 1);
1393 pt (x->types[i]);
1394 fprintf (stdout, "\n");
1395 if (x->types[i]
3f4438ab 1396 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1397 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1398 if (x->types[i] & Imm)
520dc8e8 1399 pe (x->op[i].imms);
252b5132 1400 if (x->types[i] & Disp)
520dc8e8 1401 pe (x->op[i].disps);
252b5132
RH		 1402 }
1403}
1404
1405static void
1406pte (t)
1407 template *t;
1408{
09f131f2 1409 unsigned int i;
252b5132 1410 fprintf (stdout, " %d operands ", t->operands);
47926f60 1411 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1412 if (t->extension_opcode != None)
1413 fprintf (stdout, "ext %x ", t->extension_opcode);
1414 if (t->opcode_modifier & D)
1415 fprintf (stdout, "D");
1416 if (t->opcode_modifier & W)
1417 fprintf (stdout, "W");
1418 fprintf (stdout, "\n");
1419 for (i = 0; i < t->operands; i++)
1420 {
1421 fprintf (stdout, " #%d type ", i + 1);
1422 pt (t->operand_types[i]);
1423 fprintf (stdout, "\n");
1424 }
1425}
1426
1427static void
1428pe (e)
1429 expressionS *e;
1430{
24eab124 1431 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1432 fprintf (stdout, " add_number %ld (%lx)\n",
1433 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1434 if (e->X_add_symbol)
1435 {
1436 fprintf (stdout, " add_symbol ");
1437 ps (e->X_add_symbol);
1438 fprintf (stdout, "\n");
1439 }
1440 if (e->X_op_symbol)
1441 {
1442 fprintf (stdout, " op_symbol ");
1443 ps (e->X_op_symbol);
1444 fprintf (stdout, "\n");
1445 }
1446}
1447
1448static void
1449ps (s)
1450 symbolS *s;
1451{
1452 fprintf (stdout, "%s type %s%s",
1453 S_GET_NAME (s),
1454 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1455 segment_name (S_GET_SEGMENT (s)));
1456}
1457
7b81dfbb 1458static struct type_name
252b5132
RH		 1459 {
1460 unsigned int mask;
1461 char *tname;
1462 }
7b81dfbb 1463const type_names[] =
252b5132
RH		 1464{
1465 { Reg8, "r8" },
1466 { Reg16, "r16" },
1467 { Reg32, "r32" },
09f131f2 1468 { Reg64, "r64" },
252b5132
RH		 1469 { Imm8, "i8" },
1470 { Imm8S, "i8s" },
1471 { Imm16, "i16" },
1472 { Imm32, "i32" },
09f131f2
JH		 1473 { Imm32S, "i32s" },
1474 { Imm64, "i64" },
252b5132
RH		 1475 { Imm1, "i1" },
1476 { BaseIndex, "BaseIndex" },
1477 { Disp8, "d8" },
1478 { Disp16, "d16" },
1479 { Disp32, "d32" },
09f131f2
JH		 1480 { Disp32S, "d32s" },
1481 { Disp64, "d64" },
252b5132
RH		 1482 { InOutPortReg, "InOutPortReg" },
1483 { ShiftCount, "ShiftCount" },
1484 { Control, "control reg" },
1485 { Test, "test reg" },
1486 { Debug, "debug reg" },
1487 { FloatReg, "FReg" },
1488 { FloatAcc, "FAcc" },
1489 { SReg2, "SReg2" },
1490 { SReg3, "SReg3" },
1491 { Acc, "Acc" },
1492 { JumpAbsolute, "Jump Absolute" },
1493 { RegMMX, "rMMX" },
3f4438ab 1494 { RegXMM, "rXMM" },
252b5132
RH		 1495 { EsSeg, "es" },
1496 { 0, "" }
1497};
1498
1499static void
1500pt (t)
1501 unsigned int t;
1502{
29b0f896 1503 const struct type_name *ty;
252b5132 1504
09f131f2
JH		 1505 for (ty = type_names; ty->mask; ty++)
1506 if (t & ty->mask)
1507 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1508 fflush (stdout);
1509}
1510
1511#endif /* DEBUG386 */
1512\f
252b5132 1513static bfd_reloc_code_real_type
3956db08 1514reloc (unsigned int size,
64e74474
AM		 1515 int pcrel,
1516 int sign,
1517 bfd_reloc_code_real_type other)
252b5132 1518{
47926f60 1519 if (other != NO_RELOC)
3956db08
JB		 1520 {
1521 reloc_howto_type *reloc;
1522
1523 if (size == 8)
1524 switch (other)
1525 {
64e74474
AM		 1526 case BFD_RELOC_X86_64_GOT32:
1527 return BFD_RELOC_X86_64_GOT64;
1528 break;
1529 case BFD_RELOC_X86_64_PLTOFF64:
1530 return BFD_RELOC_X86_64_PLTOFF64;
1531 break;
1532 case BFD_RELOC_X86_64_GOTPC32:
1533 other = BFD_RELOC_X86_64_GOTPC64;
1534 break;
1535 case BFD_RELOC_X86_64_GOTPCREL:
1536 other = BFD_RELOC_X86_64_GOTPCREL64;
1537 break;
1538 case BFD_RELOC_X86_64_TPOFF32:
1539 other = BFD_RELOC_X86_64_TPOFF64;
1540 break;
1541 case BFD_RELOC_X86_64_DTPOFF32:
1542 other = BFD_RELOC_X86_64_DTPOFF64;
1543 break;
1544 default:
1545 break;
3956db08 1546 }
e05278af
JB		 1547
1548 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1549 if (size == 4 && flag_code != CODE_64BIT)
1550 sign = -1;
1551
3956db08
JB		 1552 reloc = bfd_reloc_type_lookup (stdoutput, other);
1553 if (!reloc)
1554 as_bad (_("unknown relocation (%u)"), other);
1555 else if (size != bfd_get_reloc_size (reloc))
1556 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1557 bfd_get_reloc_size (reloc),
1558 size);
1559 else if (pcrel && !reloc->pc_relative)
1560 as_bad (_("non-pc-relative relocation for pc-relative field"));
1561 else if ((reloc->complain_on_overflow == complain_overflow_signed
1562 && !sign)
1563 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1564 && sign > 0))
3956db08
JB		 1565 as_bad (_("relocated field and relocation type differ in signedness"));
1566 else
1567 return other;
1568 return NO_RELOC;
1569 }
252b5132
RH		 1570
1571 if (pcrel)
1572 {
3e73aa7c 1573 if (!sign)
3956db08 1574 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1575 switch (size)
1576 {
1577 case 1: return BFD_RELOC_8_PCREL;
1578 case 2: return BFD_RELOC_16_PCREL;
1579 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1580 case 8: return BFD_RELOC_64_PCREL;
252b5132 1581 }
3956db08 1582 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1583 }
1584 else
1585 {
3956db08 1586 if (sign > 0)
e5cb08ac 1587 switch (size)
3e73aa7c
JH		 1588 {
1589 case 4: return BFD_RELOC_X86_64_32S;
1590 }
1591 else
1592 switch (size)
1593 {
1594 case 1: return BFD_RELOC_8;
1595 case 2: return BFD_RELOC_16;
1596 case 4: return BFD_RELOC_32;
1597 case 8: return BFD_RELOC_64;
1598 }
3956db08
JB		 1599 as_bad (_("cannot do %s %u byte relocation"),
1600 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1601 }
1602
bfb32b52 1603 abort ();
252b5132
RH		 1604 return BFD_RELOC_NONE;
1605}
1606
47926f60
KH		 1607/* Here we decide which fixups can be adjusted to make them relative to
1608 the beginning of the section instead of the symbol. Basically we need
1609 to make sure that the dynamic relocations are done correctly, so in
1610 some cases we force the original symbol to be used. */
1611
252b5132 1612int
c0c949c7 1613tc_i386_fix_adjustable (fixP)
31312f95 1614 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1615{
6d249963 1616#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1617 if (!IS_ELF)
31312f95
AM		 1618 return 1;
1619
a161fe53
AM		 1620 /* Don't adjust pc-relative references to merge sections in 64-bit
1621 mode. */
1622 if (use_rela_relocations
1623 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1624 && fixP->fx_pcrel)
252b5132 1625 return 0;
31312f95 1626
8d01d9a9
AJ		 1627 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1628 and changed later by validate_fix. */
1629 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1630 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1631 return 0;
1632
ce8a8b2f 1633 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1634 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1635 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1636 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1637 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1638 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1639 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1640 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1641 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1642 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1643 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1644 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1645 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1646 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1647 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1648 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1649 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1650 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1651 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1652 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1653 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1654 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1655 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1656 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1657 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1658 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1659 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1660 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1661 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1662 return 0;
31312f95 1663#endif
252b5132
RH		 1664 return 1;
1665}
252b5132 1666
29b0f896 1667static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1668
1669static int
252b5132 1670intel_float_operand (mnemonic)
29b0f896 1671 const char *mnemonic;
252b5132 1672{
9306ca4a
JB		 1673 /* Note that the value returned is meaningful only for opcodes with (memory)
1674 operands, hence the code here is free to improperly handle opcodes that
1675 have no operands (for better performance and smaller code). */
1676
1677 if (mnemonic[0] != 'f')
1678 return 0; /* non-math */
1679
1680 switch (mnemonic[1])
1681 {
1682 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1683 the fs segment override prefix not currently handled because no
1684 call path can make opcodes without operands get here */
1685 case 'i':
1686 return 2 /* integer op */;
1687 case 'l':
1688 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1689 return 3; /* fldcw/fldenv */
1690 break;
1691 case 'n':
1692 if (mnemonic[2] != 'o' /* fnop */)
1693 return 3; /* non-waiting control op */
1694 break;
1695 case 'r':
1696 if (mnemonic[2] == 's')
1697 return 3; /* frstor/frstpm */
1698 break;
1699 case 's':
1700 if (mnemonic[2] == 'a')
1701 return 3; /* fsave */
1702 if (mnemonic[2] == 't')
1703 {
1704 switch (mnemonic[3])
1705 {
1706 case 'c': /* fstcw */
1707 case 'd': /* fstdw */
1708 case 'e': /* fstenv */
1709 case 's': /* fsts[gw] */
1710 return 3;
1711 }
1712 }
1713 break;
1714 case 'x':
1715 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1716 return 0; /* fxsave/fxrstor are not really math ops */
1717 break;
1718 }
252b5132 1719
9306ca4a 1720 return 1;
252b5132
RH		 1721}
1722
1723/* This is the guts of the machine-dependent assembler. LINE points to a
1724 machine dependent instruction. This function is supposed to emit
1725 the frags/bytes it assembles to. */
1726
1727void
1728md_assemble (line)
1729 char *line;
1730{
252b5132 1731 int j;
252b5132
RH		 1732 char mnemonic[MAX_MNEM_SIZE];
1733
47926f60 1734 /* Initialize globals. */
252b5132
RH		 1735 memset (&i, '\0', sizeof (i));
1736 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1737 i.reloc[j] = NO_RELOC;
252b5132
RH		 1738 memset (disp_expressions, '\0', sizeof (disp_expressions));
1739 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1740 save_stack_p = save_stack;
252b5132
RH		 1741
1742 /* First parse an instruction mnemonic & call i386_operand for the operands.
1743 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1744 start of a (possibly prefixed) mnemonic. */
252b5132 1745
29b0f896
AM		 1746 line = parse_insn (line, mnemonic);
1747 if (line == NULL)
1748 return;
252b5132 1749
29b0f896
AM		 1750 line = parse_operands (line, mnemonic);
1751 if (line == NULL)
1752 return;
252b5132 1753
050dfa73
MM		 1754 /* The order of the immediates should be reversed
1755 for 2 immediates extrq and insertq instructions */
1756 if ((i.imm_operands == 2) &&
1757 ((strcmp (mnemonic, "extrq") == 0)
1758 || (strcmp (mnemonic, "insertq") == 0)))
1759 {
1760 swap_imm_operands ();
1761 /* "extrq" and insertq" are the only two instructions whose operands
1762 have to be reversed even though they have two immediate operands.
1763 */
1764 if (intel_syntax)
1765 swap_operands ();
1766 }
1767
29b0f896
AM		 1768 /* Now we've parsed the mnemonic into a set of templates, and have the
1769 operands at hand. */
1770
1771 /* All intel opcodes have reversed operands except for "bound" and
1772 "enter". We also don't reverse intersegment "jmp" and "call"
1773 instructions with 2 immediate operands so that the immediate segment
050dfa73 1774 precedes the offset, as it does when in AT&T mode. */
29b0f896
AM		 1775 if (intel_syntax && i.operands > 1
1776 && (strcmp (mnemonic, "bound") != 0)
30123838 1777 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1778 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1779 swap_operands ();
1780
1781 if (i.imm_operands)
1782 optimize_imm ();
1783
b300c311
L		 1784 /* Don't optimize displacement for movabs since it only takes 64bit
1785 displacement. */
1786 if (i.disp_operands
1787 && (flag_code != CODE_64BIT
1788 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1789 optimize_disp ();
1790
1791 /* Next, we find a template that matches the given insn,
1792 making sure the overlap of the given operands types is consistent
1793 with the template operand types. */
252b5132 1794
29b0f896
AM		 1795 if (!match_template ())
1796 return;
252b5132 1797
cd61ebfe
AM		 1798 if (intel_syntax)
1799 {
1800 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1801 if (SYSV386_COMPAT
1802 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1803 i.tm.base_opcode ^= FloatR;
1804
1805 /* Zap movzx and movsx suffix. The suffix may have been set from
1806 "word ptr" or "byte ptr" on the source operand, but we'll use
1807 the suffix later to choose the destination register. */
1808 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1809 {
1810 if (i.reg_operands < 2
1811 && !i.suffix
1812 && (~i.tm.opcode_modifier
1813 & (No_bSuf
1814 | No_wSuf
1815 | No_lSuf
1816 | No_sSuf
1817 | No_xSuf
1818 | No_qSuf)))
1819 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1820
1821 i.suffix = 0;
1822 }
cd61ebfe 1823 }
24eab124 1824
29b0f896
AM		 1825 if (i.tm.opcode_modifier & FWait)
1826 if (!add_prefix (FWAIT_OPCODE))
1827 return;
252b5132 1828
29b0f896
AM		 1829 /* Check string instruction segment overrides. */
1830 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1831 {
1832 if (!check_string ())
5dd0794d 1833 return;
29b0f896 1834 }
5dd0794d 1835
29b0f896
AM		 1836 if (!process_suffix ())
1837 return;
e413e4e9 1838
29b0f896
AM		 1839 /* Make still unresolved immediate matches conform to size of immediate
1840 given in i.suffix. */
1841 if (!finalize_imm ())
1842 return;
252b5132 1843
29b0f896
AM		 1844 if (i.types[0] & Imm1)
1845 i.imm_operands = 0; /* kludge for shift insns. */
1846 if (i.types[0] & ImplicitRegister)
1847 i.reg_operands--;
1848 if (i.types[1] & ImplicitRegister)
1849 i.reg_operands--;
1850 if (i.types[2] & ImplicitRegister)
1851 i.reg_operands--;
252b5132 1852
29b0f896
AM		 1853 if (i.tm.opcode_modifier & ImmExt)
1854 {
02fc3089
L		 1855 expressionS *exp;
1856
b7d9ef37 1857 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
ca164297 1858 {
b7d9ef37 1859 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 1860 operands with an opcode suffix which is coded in the same
1861 place as an 8-bit immediate field would be. Here we check
1862 those operands and remove them afterwards. */
1863 unsigned int x;
1864
a4622f40 1865 for (x = 0; x < i.operands; x++)
ca164297
L		 1866 if (i.op[x].regs->reg_num != x)
1867 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
64e74474 1868 i.op[x].regs->reg_name, x + 1, i.tm.name);
ca164297
L		 1869 i.operands = 0;
1870 }
1871
29b0f896
AM		 1872 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1873 opcode suffix which is coded in the same place as an 8-bit
1874 immediate field would be. Here we fake an 8-bit immediate
1875 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1876
29b0f896 1877 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1878
29b0f896
AM		 1879 exp = &im_expressions[i.imm_operands++];
1880 i.op[i.operands].imms = exp;
1881 i.types[i.operands++] = Imm8;
1882 exp->X_op = O_constant;
1883 exp->X_add_number = i.tm.extension_opcode;
1884 i.tm.extension_opcode = None;
1885 }
252b5132 1886
29b0f896
AM		 1887 /* For insns with operands there are more diddles to do to the opcode. */
1888 if (i.operands)
1889 {
1890 if (!process_operands ())
1891 return;
1892 }
1893 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1894 {
1895 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1896 as_warn (_("translating to `%sp'"), i.tm.name);
1897 }
252b5132 1898
29b0f896
AM		 1899 /* Handle conversion of 'int $3' --> special int3 insn. */
1900 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1901 {
1902 i.tm.base_opcode = INT3_OPCODE;
1903 i.imm_operands = 0;
1904 }
252b5132 1905
29b0f896
AM		 1906 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1907 && i.op[0].disps->X_op == O_constant)
1908 {
1909 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1910 the absolute address given by the constant. Since ix86 jumps and
1911 calls are pc relative, we need to generate a reloc. */
1912 i.op[0].disps->X_add_symbol = &abs_symbol;
1913 i.op[0].disps->X_op = O_symbol;
1914 }
252b5132 1915
29b0f896
AM		 1916 if ((i.tm.opcode_modifier & Rex64) != 0)
1917 i.rex |= REX_MODE64;
252b5132 1918
29b0f896
AM		 1919 /* For 8 bit registers we need an empty rex prefix. Also if the
1920 instruction already has a prefix, we need to convert old
1921 registers to new ones. */
773f551c 1922
29b0f896
AM		 1923 if (((i.types[0] & Reg8) != 0
1924 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1925 || ((i.types[1] & Reg8) != 0
1926 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1927 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1928 && i.rex != 0))
1929 {
1930 int x;
726c5dcd 1931
29b0f896
AM		 1932 i.rex |= REX_OPCODE;
1933 for (x = 0; x < 2; x++)
1934 {
1935 /* Look for 8 bit operand that uses old registers. */
1936 if ((i.types[x] & Reg8) != 0
1937 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1938 {
29b0f896
AM		 1939 /* In case it is "hi" register, give up. */
1940 if (i.op[x].regs->reg_num > 3)
0477af35 1941 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1942 i.op[x].regs->reg_name);
773f551c 1943
29b0f896
AM		 1944 /* Otherwise it is equivalent to the extended register.
1945 Since the encoding doesn't change this is merely
1946 cosmetic cleanup for debug output. */
1947
1948 i.op[x].regs = i.op[x].regs + 8;
773f551c 1949 }
29b0f896
AM		 1950 }
1951 }
773f551c 1952
29b0f896
AM		 1953 if (i.rex != 0)
1954 add_prefix (REX_OPCODE | i.rex);
1955
1956 /* We are ready to output the insn. */
1957 output_insn ();
1958}
1959
1960static char *
1961parse_insn (line, mnemonic)
1962 char *line;
1963 char *mnemonic;
1964{
1965 char *l = line;
1966 char *token_start = l;
1967 char *mnem_p;
5c6af06e
JB		 1968 int supported;
1969 const template *t;
29b0f896
AM		 1970
1971 /* Non-zero if we found a prefix only acceptable with string insns. */
1972 const char *expecting_string_instruction = NULL;
45288df1 1973
29b0f896
AM		 1974 while (1)
1975 {
1976 mnem_p = mnemonic;
1977 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1978 {
1979 mnem_p++;
1980 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1981 {
29b0f896
AM		 1982 as_bad (_("no such instruction: `%s'"), token_start);
1983 return NULL;
1984 }
1985 l++;
1986 }
1987 if (!is_space_char (*l)
1988 && *l != END_OF_INSN
e44823cf
JB		 1989 && (intel_syntax
1990 || (*l != PREFIX_SEPARATOR
1991 && *l != ',')))
29b0f896
AM		 1992 {
1993 as_bad (_("invalid character %s in mnemonic"),
1994 output_invalid (*l));
1995 return NULL;
1996 }
1997 if (token_start == l)
1998 {
e44823cf 1999 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2000 as_bad (_("expecting prefix; got nothing"));
2001 else
2002 as_bad (_("expecting mnemonic; got nothing"));
2003 return NULL;
2004 }
45288df1 2005
29b0f896
AM		 2006 /* Look up instruction (or prefix) via hash table. */
2007 current_templates = hash_find (op_hash, mnemonic);
47926f60 2008
29b0f896
AM		 2009 if (*l != END_OF_INSN
2010 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2011 && current_templates
2012 && (current_templates->start->opcode_modifier & IsPrefix))
2013 {
2dd88dca
JB		 2014 if (current_templates->start->cpu_flags
2015 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
2016 {
2017 as_bad ((flag_code != CODE_64BIT
2018 ? _("`%s' is only supported in 64-bit mode")
2019 : _("`%s' is not supported in 64-bit mode")),
2020 current_templates->start->name);
2021 return NULL;
2022 }
29b0f896
AM		 2023 /* If we are in 16-bit mode, do not allow addr16 or data16.
2024 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2025 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
2026 && flag_code != CODE_64BIT
2027 && (((current_templates->start->opcode_modifier & Size32) != 0)
2028 ^ (flag_code == CODE_16BIT)))
2029 {
2030 as_bad (_("redundant %s prefix"),
2031 current_templates->start->name);
2032 return NULL;
45288df1 2033 }
29b0f896
AM		 2034 /* Add prefix, checking for repeated prefixes. */
2035 switch (add_prefix (current_templates->start->base_opcode))
2036 {
2037 case 0:
2038 return NULL;
2039 case 2:
2040 expecting_string_instruction = current_templates->start->name;
2041 break;
2042 }
2043 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2044 token_start = ++l;
2045 }
2046 else
2047 break;
2048 }
45288df1 2049
29b0f896
AM		 2050 if (!current_templates)
2051 {
2052 /* See if we can get a match by trimming off a suffix. */
2053 switch (mnem_p[-1])
2054 {
2055 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2056 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2057 i.suffix = SHORT_MNEM_SUFFIX;
2058 else
29b0f896
AM		 2059 case BYTE_MNEM_SUFFIX:
2060 case QWORD_MNEM_SUFFIX:
2061 i.suffix = mnem_p[-1];
2062 mnem_p[-1] = '\0';
2063 current_templates = hash_find (op_hash, mnemonic);
2064 break;
2065 case SHORT_MNEM_SUFFIX:
2066 case LONG_MNEM_SUFFIX:
2067 if (!intel_syntax)
2068 {
2069 i.suffix = mnem_p[-1];
2070 mnem_p[-1] = '\0';
2071 current_templates = hash_find (op_hash, mnemonic);
2072 }
2073 break;
252b5132 2074
29b0f896
AM		 2075 /* Intel Syntax. */
2076 case 'd':
2077 if (intel_syntax)
2078 {
9306ca4a 2079 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2080 i.suffix = SHORT_MNEM_SUFFIX;
2081 else
2082 i.suffix = LONG_MNEM_SUFFIX;
2083 mnem_p[-1] = '\0';
2084 current_templates = hash_find (op_hash, mnemonic);
2085 }
2086 break;
2087 }
2088 if (!current_templates)
2089 {
2090 as_bad (_("no such instruction: `%s'"), token_start);
2091 return NULL;
2092 }
2093 }
252b5132 2094
29b0f896
AM		 2095 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2096 {
2097 /* Check for a branch hint. We allow ",pt" and ",pn" for
2098 predict taken and predict not taken respectively.
2099 I'm not sure that branch hints actually do anything on loop
2100 and jcxz insns (JumpByte) for current Pentium4 chips. They
2101 may work in the future and it doesn't hurt to accept them
2102 now. */
2103 if (l[0] == ',' && l[1] == 'p')
2104 {
2105 if (l[2] == 't')
2106 {
2107 if (!add_prefix (DS_PREFIX_OPCODE))
2108 return NULL;
2109 l += 3;
2110 }
2111 else if (l[2] == 'n')
2112 {
2113 if (!add_prefix (CS_PREFIX_OPCODE))
2114 return NULL;
2115 l += 3;
2116 }
2117 }
2118 }
2119 /* Any other comma loses. */
2120 if (*l == ',')
2121 {
2122 as_bad (_("invalid character %s in mnemonic"),
2123 output_invalid (*l));
2124 return NULL;
2125 }
252b5132 2126
29b0f896 2127 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2128 supported = 0;
2129 for (t = current_templates->start; t < current_templates->end; ++t)
2130 {
2131 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2132 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 2133 supported |= 1;
5c6af06e 2134 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 2135 supported |= 2;
5c6af06e
JB		 2136 }
2137 if (!(supported & 2))
2138 {
2139 as_bad (flag_code == CODE_64BIT
2140 ? _("`%s' is not supported in 64-bit mode")
2141 : _("`%s' is only supported in 64-bit mode"),
2142 current_templates->start->name);
2143 return NULL;
2144 }
2145 if (!(supported & 1))
29b0f896 2146 {
5c6af06e
JB		 2147 as_warn (_("`%s' is not supported on `%s%s'"),
2148 current_templates->start->name,
2149 cpu_arch_name,
2150 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 2151 }
2152 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2153 {
2154 as_warn (_("use .code16 to ensure correct addressing mode"));
2155 }
252b5132 2156
29b0f896 2157 /* Check for rep/repne without a string instruction. */
f41bbced 2158 if (expecting_string_instruction)
29b0f896 2159 {
f41bbced
JB		 2160 static templates override;
2161
2162 for (t = current_templates->start; t < current_templates->end; ++t)
2163 if (t->opcode_modifier & IsString)
2164 break;
2165 if (t >= current_templates->end)
2166 {
2167 as_bad (_("expecting string instruction after `%s'"),
64e74474 2168 expecting_string_instruction);
f41bbced
JB		 2169 return NULL;
2170 }
2171 for (override.start = t; t < current_templates->end; ++t)
2172 if (!(t->opcode_modifier & IsString))
2173 break;
2174 override.end = t;
2175 current_templates = &override;
29b0f896 2176 }
252b5132 2177
29b0f896
AM		 2178 return l;
2179}
252b5132 2180
29b0f896
AM		 2181static char *
2182parse_operands (l, mnemonic)
2183 char *l;
2184 const char *mnemonic;
2185{
2186 char *token_start;
3138f287 2187
29b0f896
AM		 2188 /* 1 if operand is pending after ','. */
2189 unsigned int expecting_operand = 0;
252b5132 2190
29b0f896
AM		 2191 /* Non-zero if operand parens not balanced. */
2192 unsigned int paren_not_balanced;
2193
2194 while (*l != END_OF_INSN)
2195 {
2196 /* Skip optional white space before operand. */
2197 if (is_space_char (*l))
2198 ++l;
2199 if (!is_operand_char (*l) && *l != END_OF_INSN)
2200 {
2201 as_bad (_("invalid character %s before operand %d"),
2202 output_invalid (*l),
2203 i.operands + 1);
2204 return NULL;
2205 }
2206 token_start = l; /* after white space */
2207 paren_not_balanced = 0;
2208 while (paren_not_balanced || *l != ',')
2209 {
2210 if (*l == END_OF_INSN)
2211 {
2212 if (paren_not_balanced)
2213 {
2214 if (!intel_syntax)
2215 as_bad (_("unbalanced parenthesis in operand %d."),
2216 i.operands + 1);
2217 else
2218 as_bad (_("unbalanced brackets in operand %d."),
2219 i.operands + 1);
2220 return NULL;
2221 }
2222 else
2223 break; /* we are done */
2224 }
2225 else if (!is_operand_char (*l) && !is_space_char (*l))
2226 {
2227 as_bad (_("invalid character %s in operand %d"),
2228 output_invalid (*l),
2229 i.operands + 1);
2230 return NULL;
2231 }
2232 if (!intel_syntax)
2233 {
2234 if (*l == '(')
2235 ++paren_not_balanced;
2236 if (*l == ')')
2237 --paren_not_balanced;
2238 }
2239 else
2240 {
2241 if (*l == '[')
2242 ++paren_not_balanced;
2243 if (*l == ']')
2244 --paren_not_balanced;
2245 }
2246 l++;
2247 }
2248 if (l != token_start)
2249 { /* Yes, we've read in another operand. */
2250 unsigned int operand_ok;
2251 this_operand = i.operands++;
2252 if (i.operands > MAX_OPERANDS)
2253 {
2254 as_bad (_("spurious operands; (%d operands/instruction max)"),
2255 MAX_OPERANDS);
2256 return NULL;
2257 }
2258 /* Now parse operand adding info to 'i' as we go along. */
2259 END_STRING_AND_SAVE (l);
2260
2261 if (intel_syntax)
2262 operand_ok =
2263 i386_intel_operand (token_start,
2264 intel_float_operand (mnemonic));
2265 else
2266 operand_ok = i386_operand (token_start);
2267
2268 RESTORE_END_STRING (l);
2269 if (!operand_ok)
2270 return NULL;
2271 }
2272 else
2273 {
2274 if (expecting_operand)
2275 {
2276 expecting_operand_after_comma:
2277 as_bad (_("expecting operand after ','; got nothing"));
2278 return NULL;
2279 }
2280 if (*l == ',')
2281 {
2282 as_bad (_("expecting operand before ','; got nothing"));
2283 return NULL;
2284 }
2285 }
7f3f1ea2 2286
29b0f896
AM		 2287 /* Now *l must be either ',' or END_OF_INSN. */
2288 if (*l == ',')
2289 {
2290 if (*++l == END_OF_INSN)
2291 {
2292 /* Just skip it, if it's \n complain. */
2293 goto expecting_operand_after_comma;
2294 }
2295 expecting_operand = 1;
2296 }
2297 }
2298 return l;
2299}
7f3f1ea2 2300
050dfa73
MM		 2301static void
2302swap_imm_operands ()
2303{
2304 union i386_op temp_op;
2305 unsigned int temp_type;
2306 enum bfd_reloc_code_real temp_reloc;
2307 int xchg1 = 0;
2308 int xchg2 = 1;
2309
2310 temp_type = i.types[xchg2];
2311 i.types[xchg2] = i.types[xchg1];
2312 i.types[xchg1] = temp_type;
2313 temp_op = i.op[xchg2];
2314 i.op[xchg2] = i.op[xchg1];
2315 i.op[xchg1] = temp_op;
2316 temp_reloc = i.reloc[xchg2];
2317 i.reloc[xchg2] = i.reloc[xchg1];
2318 i.reloc[xchg1] = temp_reloc;
2319}
2320
2321
29b0f896
AM		 2322static void
2323swap_operands ()
2324{
2325 union i386_op temp_op;
2326 unsigned int temp_type;
f86103b7 2327 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 2328 int xchg1 = 0;
2329 int xchg2 = 0;
252b5132 2330
050dfa73
MM		 2331 if (i.operands == 4)
2332 /* There will be two exchanges in a 4 operand instruction.
2333 First exchange is the done inside this block.(1st and 4rth operand)
2334 The next exchange is done outside this block.(2nd and 3rd operand) */
2335 {
2336 xchg1 = 0;
2337 xchg2 = 3;
2338 temp_type = i.types[xchg2];
2339 i.types[xchg2] = i.types[xchg1];
2340 i.types[xchg1] = temp_type;
2341 temp_op = i.op[xchg2];
2342 i.op[xchg2] = i.op[xchg1];
2343 i.op[xchg1] = temp_op;
2344 temp_reloc = i.reloc[xchg2];
2345 i.reloc[xchg2] = i.reloc[xchg1];
2346 i.reloc[xchg1] = temp_reloc;
2347 xchg1 = 1;
2348 xchg2 = 2;
2349 }
2350
29b0f896
AM		 2351 if (i.operands == 2)
2352 {
2353 xchg1 = 0;
2354 xchg2 = 1;
2355 }
2356 else if (i.operands == 3)
2357 {
2358 xchg1 = 0;
2359 xchg2 = 2;
2360 }
2361 temp_type = i.types[xchg2];
2362 i.types[xchg2] = i.types[xchg1];
2363 i.types[xchg1] = temp_type;
2364 temp_op = i.op[xchg2];
2365 i.op[xchg2] = i.op[xchg1];
2366 i.op[xchg1] = temp_op;
2367 temp_reloc = i.reloc[xchg2];
2368 i.reloc[xchg2] = i.reloc[xchg1];
2369 i.reloc[xchg1] = temp_reloc;
2370
2371 if (i.mem_operands == 2)
2372 {
2373 const seg_entry *temp_seg;
2374 temp_seg = i.seg[0];
2375 i.seg[0] = i.seg[1];
2376 i.seg[1] = temp_seg;
2377 }
2378}
252b5132 2379
29b0f896
AM		 2380/* Try to ensure constant immediates are represented in the smallest
2381 opcode possible. */
2382static void
2383optimize_imm ()
2384{
2385 char guess_suffix = 0;
2386 int op;
252b5132 2387
29b0f896
AM		 2388 if (i.suffix)
2389 guess_suffix = i.suffix;
2390 else if (i.reg_operands)
2391 {
2392 /* Figure out a suffix from the last register operand specified.
2393 We can't do this properly yet, ie. excluding InOutPortReg,
2394 but the following works for instructions with immediates.
2395 In any case, we can't set i.suffix yet. */
2396 for (op = i.operands; --op >= 0;)
2397 if (i.types[op] & Reg)
252b5132 2398 {
29b0f896
AM		 2399 if (i.types[op] & Reg8)
2400 guess_suffix = BYTE_MNEM_SUFFIX;
2401 else if (i.types[op] & Reg16)
2402 guess_suffix = WORD_MNEM_SUFFIX;
2403 else if (i.types[op] & Reg32)
2404 guess_suffix = LONG_MNEM_SUFFIX;
2405 else if (i.types[op] & Reg64)
2406 guess_suffix = QWORD_MNEM_SUFFIX;
2407 break;
252b5132 2408 }
29b0f896
AM		 2409 }
2410 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2411 guess_suffix = WORD_MNEM_SUFFIX;
2412
2413 for (op = i.operands; --op >= 0;)
2414 if (i.types[op] & Imm)
2415 {
2416 switch (i.op[op].imms->X_op)
252b5132 2417 {
29b0f896
AM		 2418 case O_constant:
2419 /* If a suffix is given, this operand may be shortened. */
2420 switch (guess_suffix)
252b5132 2421 {
29b0f896
AM		 2422 case LONG_MNEM_SUFFIX:
2423 i.types[op] |= Imm32 | Imm64;
2424 break;
2425 case WORD_MNEM_SUFFIX:
2426 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2427 break;
2428 case BYTE_MNEM_SUFFIX:
2429 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2430 break;
252b5132 2431 }
252b5132 2432
29b0f896
AM		 2433 /* If this operand is at most 16 bits, convert it
2434 to a signed 16 bit number before trying to see
2435 whether it will fit in an even smaller size.
2436 This allows a 16-bit operand such as $0xffe0 to
2437 be recognised as within Imm8S range. */
2438 if ((i.types[op] & Imm16)
2439 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2440 {
29b0f896
AM		 2441 i.op[op].imms->X_add_number =
2442 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2443 }
2444 if ((i.types[op] & Imm32)
2445 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2446 == 0))
2447 {
2448 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2449 ^ ((offsetT) 1 << 31))
2450 - ((offsetT) 1 << 31));
2451 }
2452 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2453
29b0f896
AM		 2454 /* We must avoid matching of Imm32 templates when 64bit
2455 only immediate is available. */
2456 if (guess_suffix == QWORD_MNEM_SUFFIX)
2457 i.types[op] &= ~Imm32;
2458 break;
252b5132 2459
29b0f896
AM		 2460 case O_absent:
2461 case O_register:
2462 abort ();
2463
2464 /* Symbols and expressions. */
2465 default:
9cd96992
JB		 2466 /* Convert symbolic operand to proper sizes for matching, but don't
2467 prevent matching a set of insns that only supports sizes other
2468 than those matching the insn suffix. */
2469 {
2470 unsigned int mask, allowed = 0;
2471 const template *t;
2472
2473 for (t = current_templates->start; t < current_templates->end; ++t)
2474 allowed |= t->operand_types[op];
2475 switch (guess_suffix)
2476 {
2477 case QWORD_MNEM_SUFFIX:
2478 mask = Imm64 | Imm32S;
2479 break;
2480 case LONG_MNEM_SUFFIX:
2481 mask = Imm32;
2482 break;
2483 case WORD_MNEM_SUFFIX:
2484 mask = Imm16;
2485 break;
2486 case BYTE_MNEM_SUFFIX:
2487 mask = Imm8;
2488 break;
2489 default:
2490 mask = 0;
2491 break;
2492 }
64e74474
AM		 2493 if (mask & allowed)
2494 i.types[op] &= mask;
9cd96992 2495 }
29b0f896 2496 break;
252b5132 2497 }
29b0f896
AM		 2498 }
2499}
47926f60 2500
29b0f896
AM		 2501/* Try to use the smallest displacement type too. */
2502static void
2503optimize_disp ()
2504{
2505 int op;
3e73aa7c 2506
29b0f896 2507 for (op = i.operands; --op >= 0;)
b300c311 2508 if (i.types[op] & Disp)
252b5132 2509 {
b300c311 2510 if (i.op[op].disps->X_op == O_constant)
252b5132 2511 {
b300c311 2512 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2513
b300c311
L		 2514 if ((i.types[op] & Disp16)
2515 && (disp & ~(offsetT) 0xffff) == 0)
2516 {
2517 /* If this operand is at most 16 bits, convert
2518 to a signed 16 bit number and don't use 64bit
2519 displacement. */
2520 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2521 i.types[op] &= ~Disp64;
2522 }
2523 if ((i.types[op] & Disp32)
2524 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2525 {
2526 /* If this operand is at most 32 bits, convert
2527 to a signed 32 bit number and don't use 64bit
2528 displacement. */
2529 disp &= (((offsetT) 2 << 31) - 1);
2530 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2531 i.types[op] &= ~Disp64;
2532 }
2533 if (!disp && (i.types[op] & BaseIndex))
2534 {
2535 i.types[op] &= ~Disp;
2536 i.op[op].disps = 0;
2537 i.disp_operands--;
2538 }
2539 else if (flag_code == CODE_64BIT)
2540 {
2541 if (fits_in_signed_long (disp))
28a9d8f5
L		 2542 {
2543 i.types[op] &= ~Disp64;
2544 i.types[op] |= Disp32S;
2545 }
b300c311
L		 2546 if (fits_in_unsigned_long (disp))
2547 i.types[op] |= Disp32;
2548 }
2549 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2550 && fits_in_signed_byte (disp))
2551 i.types[op] |= Disp8;
252b5132 2552 }
67a4f2b7
AO		 2553 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2554 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2555 {
2556 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2557 i.op[op].disps, 0, i.reloc[op]);
2558 i.types[op] &= ~Disp;
2559 }
2560 else
b300c311
L		 2561 /* We only support 64bit displacement on constants. */
2562 i.types[op] &= ~Disp64;
252b5132 2563 }
29b0f896
AM		 2564}
2565
2566static int
2567match_template ()
2568{
2569 /* Points to template once we've found it. */
2570 const template *t;
f48ff2ae 2571 unsigned int overlap0, overlap1, overlap2, overlap3;
29b0f896
AM		 2572 unsigned int found_reverse_match;
2573 int suffix_check;
f48ff2ae 2574 unsigned int operand_types [MAX_OPERANDS];
539e75ad 2575 int addr_prefix_disp;
a5c311ca 2576 unsigned int j;
29b0f896 2577
f48ff2ae
L		 2578#if MAX_OPERANDS != 4
2579# error "MAX_OPERANDS must be 4."
2580#endif
2581
29b0f896
AM		 2582#define MATCH(overlap, given, template) \
2583 ((overlap & ~JumpAbsolute) \
2584 && (((given) & (BaseIndex | JumpAbsolute)) \
2585 == ((overlap) & (BaseIndex | JumpAbsolute))))
2586
2587 /* If given types r0 and r1 are registers they must be of the same type
2588 unless the expected operand type register overlap is null.
2589 Note that Acc in a template matches every size of reg. */
2590#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2591 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2592 || ((g0) & Reg) == ((g1) & Reg) \
2593 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2594
2595 overlap0 = 0;
2596 overlap1 = 0;
2597 overlap2 = 0;
f48ff2ae 2598 overlap3 = 0;
29b0f896 2599 found_reverse_match = 0;
a5c311ca
L		 2600 for (j = 0; j < MAX_OPERANDS; j++)
2601 operand_types [j] = 0;
539e75ad 2602 addr_prefix_disp = -1;
29b0f896
AM		 2603 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2604 ? No_bSuf
2605 : (i.suffix == WORD_MNEM_SUFFIX
2606 ? No_wSuf
2607 : (i.suffix == SHORT_MNEM_SUFFIX
2608 ? No_sSuf
2609 : (i.suffix == LONG_MNEM_SUFFIX
2610 ? No_lSuf
2611 : (i.suffix == QWORD_MNEM_SUFFIX
2612 ? No_qSuf
2613 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2614 ? No_xSuf : 0))))));
2615
45aa61fe 2616 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2617 {
539e75ad
L		 2618 addr_prefix_disp = -1;
2619
29b0f896
AM		 2620 /* Must have right number of operands. */
2621 if (i.operands != t->operands)
2622 continue;
2623
2624 /* Check the suffix, except for some instructions in intel mode. */
2625 if ((t->opcode_modifier & suffix_check)
2626 && !(intel_syntax
9306ca4a 2627 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2628 continue;
2629
a5c311ca
L		 2630 for (j = 0; j < MAX_OPERANDS; j++)
2631 operand_types [j] = t->operand_types [j];
539e75ad 2632
45aa61fe
AM		 2633 /* In general, don't allow 64-bit operands in 32-bit mode. */
2634 if (i.suffix == QWORD_MNEM_SUFFIX
2635 && flag_code != CODE_64BIT
2636 && (intel_syntax
2637 ? (!(t->opcode_modifier & IgnoreSize)
2638 && !intel_float_operand (t->name))
2639 : intel_float_operand (t->name) != 2)
539e75ad
L		 2640 && (!(operand_types[0] & (RegMMX | RegXMM))
2641 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
45aa61fe
AM		 2642 && (t->base_opcode != 0x0fc7
2643 || t->extension_opcode != 1 /* cmpxchg8b */))
2644 continue;
2645
29b0f896
AM		 2646 /* Do not verify operands when there are none. */
2647 else if (!t->operands)
2648 {
2649 if (t->cpu_flags & ~cpu_arch_flags)
2650 continue;
2651 /* We've found a match; break out of loop. */
2652 break;
2653 }
252b5132 2654
539e75ad
L		 2655 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2656 into Disp32/Disp16/Disp32 operand. */
2657 if (i.prefix[ADDR_PREFIX] != 0)
2658 {
a5c311ca 2659 unsigned int DispOn = 0, DispOff = 0;
539e75ad
L		 2660
2661 switch (flag_code)
2662 {
2663 case CODE_16BIT:
2664 DispOn = Disp32;
2665 DispOff = Disp16;
2666 break;
2667 case CODE_32BIT:
2668 DispOn = Disp16;
2669 DispOff = Disp32;
2670 break;
2671 case CODE_64BIT:
2672 DispOn = Disp32;
2673 DispOff = Disp64;
2674 break;
2675 }
2676
f48ff2ae 2677 for (j = 0; j < MAX_OPERANDS; j++)
539e75ad
L		 2678 {
2679 /* There should be only one Disp operand. */
2680 if ((operand_types[j] & DispOff))
2681 {
2682 addr_prefix_disp = j;
2683 operand_types[j] |= DispOn;
2684 operand_types[j] &= ~DispOff;
2685 break;
2686 }
2687 }
2688 }
2689
2690 overlap0 = i.types[0] & operand_types[0];
29b0f896
AM		 2691 switch (t->operands)
2692 {
2693 case 1:
539e75ad 2694 if (!MATCH (overlap0, i.types[0], operand_types[0]))
29b0f896
AM		 2695 continue;
2696 break;
2697 case 2:
2698 case 3:
f48ff2ae 2699 case 4:
539e75ad
L		 2700 overlap1 = i.types[1] & operand_types[1];
2701 if (!MATCH (overlap0, i.types[0], operand_types[0])
2702 || !MATCH (overlap1, i.types[1], operand_types[1])
cb712a9e 2703 /* monitor in SSE3 is a very special case. The first
708587a4 2704 register and the second register may have different
cb712a9e
L		 2705 sizes. */
2706 || !((t->base_opcode == 0x0f01
2707 && t->extension_opcode == 0xc8)
2708 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2709 operand_types[0],
cb712a9e 2710 overlap1, i.types[1],
539e75ad 2711 operand_types[1])))
29b0f896
AM		 2712 {
2713 /* Check if other direction is valid ... */
2714 if ((t->opcode_modifier & (D | FloatD)) == 0)
2715 continue;
2716
2717 /* Try reversing direction of operands. */
539e75ad
L		 2718 overlap0 = i.types[0] & operand_types[1];
2719 overlap1 = i.types[1] & operand_types[0];
2720 if (!MATCH (overlap0, i.types[0], operand_types[1])
2721 || !MATCH (overlap1, i.types[1], operand_types[0])
29b0f896 2722 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2723 operand_types[1],
29b0f896 2724 overlap1, i.types[1],
539e75ad 2725 operand_types[0]))
29b0f896
AM		 2726 {
2727 /* Does not match either direction. */
2728 continue;
2729 }
2730 /* found_reverse_match holds which of D or FloatDR
2731 we've found. */
2732 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2733 }
f48ff2ae 2734 else
29b0f896 2735 {
f48ff2ae 2736 /* Found a forward 2 operand match here. */
d1cbb4db
L		 2737 switch (t->operands)
2738 {
2739 case 4:
2740 overlap3 = i.types[3] & operand_types[3];
2741 case 3:
2742 overlap2 = i.types[2] & operand_types[2];
2743 break;
2744 }
29b0f896 2745
f48ff2ae
L		 2746 switch (t->operands)
2747 {
2748 case 4:
2749 if (!MATCH (overlap3, i.types[3], operand_types[3])
2750 || !CONSISTENT_REGISTER_MATCH (overlap2,
2751 i.types[2],
2752 operand_types[2],
2753 overlap3,
2754 i.types[3],
2755 operand_types[3]))
2756 continue;
2757 case 3:
2758 /* Here we make use of the fact that there are no
2759 reverse match 3 operand instructions, and all 3
2760 operand instructions only need to be checked for
2761 register consistency between operands 2 and 3. */
2762 if (!MATCH (overlap2, i.types[2], operand_types[2])
2763 || !CONSISTENT_REGISTER_MATCH (overlap1,
2764 i.types[1],
2765 operand_types[1],
2766 overlap2,
2767 i.types[2],
2768 operand_types[2]))
2769 continue;
2770 break;
2771 }
29b0f896 2772 }
f48ff2ae 2773 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 2774 slip through to break. */
2775 }
2776 if (t->cpu_flags & ~cpu_arch_flags)
2777 {
2778 found_reverse_match = 0;
2779 continue;
2780 }
2781 /* We've found a match; break out of loop. */
2782 break;
2783 }
2784
2785 if (t == current_templates->end)
2786 {
2787 /* We found no match. */
2788 as_bad (_("suffix or operands invalid for `%s'"),
2789 current_templates->start->name);
2790 return 0;
2791 }
252b5132 2792
29b0f896
AM		 2793 if (!quiet_warnings)
2794 {
2795 if (!intel_syntax
2796 && ((i.types[0] & JumpAbsolute)
539e75ad 2797 != (operand_types[0] & JumpAbsolute)))
29b0f896
AM		 2798 {
2799 as_warn (_("indirect %s without `*'"), t->name);
2800 }
2801
2802 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2803 == (IsPrefix | IgnoreSize))
2804 {
2805 /* Warn them that a data or address size prefix doesn't
2806 affect assembly of the next line of code. */
2807 as_warn (_("stand-alone `%s' prefix"), t->name);
2808 }
2809 }
2810
2811 /* Copy the template we found. */
2812 i.tm = *t;
539e75ad
L		 2813
2814 if (addr_prefix_disp != -1)
2815 i.tm.operand_types[addr_prefix_disp]
2816 = operand_types[addr_prefix_disp];
2817
29b0f896
AM		 2818 if (found_reverse_match)
2819 {
2820 /* If we found a reverse match we must alter the opcode
2821 direction bit. found_reverse_match holds bits to change
2822 (different for int & float insns). */
2823
2824 i.tm.base_opcode ^= found_reverse_match;
2825
539e75ad
L		 2826 i.tm.operand_types[0] = operand_types[1];
2827 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 2828 }
2829
2830 return 1;
2831}
2832
2833static int
2834check_string ()
2835{
2836 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2837 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2838 {
2839 if (i.seg[0] != NULL && i.seg[0] != &es)
2840 {
2841 as_bad (_("`%s' operand %d must use `%%es' segment"),
2842 i.tm.name,
2843 mem_op + 1);
2844 return 0;
2845 }
2846 /* There's only ever one segment override allowed per instruction.
2847 This instruction possibly has a legal segment override on the
2848 second operand, so copy the segment to where non-string
2849 instructions store it, allowing common code. */
2850 i.seg[0] = i.seg[1];
2851 }
2852 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2853 {
2854 if (i.seg[1] != NULL && i.seg[1] != &es)
2855 {
2856 as_bad (_("`%s' operand %d must use `%%es' segment"),
2857 i.tm.name,
2858 mem_op + 2);
2859 return 0;
2860 }
2861 }
2862 return 1;
2863}
2864
2865static int
543613e9 2866process_suffix (void)
29b0f896
AM		 2867{
2868 /* If matched instruction specifies an explicit instruction mnemonic
2869 suffix, use it. */
2870 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2871 {
2872 if (i.tm.opcode_modifier & Size16)
2873 i.suffix = WORD_MNEM_SUFFIX;
2874 else if (i.tm.opcode_modifier & Size64)
2875 i.suffix = QWORD_MNEM_SUFFIX;
2876 else
2877 i.suffix = LONG_MNEM_SUFFIX;
2878 }
2879 else if (i.reg_operands)
2880 {
2881 /* If there's no instruction mnemonic suffix we try to invent one
2882 based on register operands. */
2883 if (!i.suffix)
2884 {
2885 /* We take i.suffix from the last register operand specified,
2886 Destination register type is more significant than source
2887 register type. */
2888 int op;
543613e9 2889
29b0f896
AM		 2890 for (op = i.operands; --op >= 0;)
2891 if ((i.types[op] & Reg)
2892 && !(i.tm.operand_types[op] & InOutPortReg))
2893 {
2894 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2895 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2896 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2897 LONG_MNEM_SUFFIX);
2898 break;
2899 }
2900 }
2901 else if (i.suffix == BYTE_MNEM_SUFFIX)
2902 {
2903 if (!check_byte_reg ())
2904 return 0;
2905 }
2906 else if (i.suffix == LONG_MNEM_SUFFIX)
2907 {
2908 if (!check_long_reg ())
2909 return 0;
2910 }
2911 else if (i.suffix == QWORD_MNEM_SUFFIX)
2912 {
2913 if (!check_qword_reg ())
2914 return 0;
2915 }
2916 else if (i.suffix == WORD_MNEM_SUFFIX)
2917 {
2918 if (!check_word_reg ())
2919 return 0;
2920 }
2921 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2922 /* Do nothing if the instruction is going to ignore the prefix. */
2923 ;
2924 else
2925 abort ();
2926 }
9306ca4a
JB		 2927 else if ((i.tm.opcode_modifier & DefaultSize)
2928 && !i.suffix
2929 /* exclude fldenv/frstor/fsave/fstenv */
2930 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2931 {
2932 i.suffix = stackop_size;
2933 }
9306ca4a
JB		 2934 else if (intel_syntax
2935 && !i.suffix
2936 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2937 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2938 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2939 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2940 {
2941 switch (flag_code)
2942 {
2943 case CODE_64BIT:
2944 if (!(i.tm.opcode_modifier & No_qSuf))
2945 {
2946 i.suffix = QWORD_MNEM_SUFFIX;
2947 break;
2948 }
2949 case CODE_32BIT:
2950 if (!(i.tm.opcode_modifier & No_lSuf))
2951 i.suffix = LONG_MNEM_SUFFIX;
2952 break;
2953 case CODE_16BIT:
2954 if (!(i.tm.opcode_modifier & No_wSuf))
2955 i.suffix = WORD_MNEM_SUFFIX;
2956 break;
2957 }
2958 }
252b5132 2959
9306ca4a 2960 if (!i.suffix)
29b0f896 2961 {
9306ca4a
JB		 2962 if (!intel_syntax)
2963 {
2964 if (i.tm.opcode_modifier & W)
2965 {
2966 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2967 return 0;
2968 }
2969 }
2970 else
2971 {
64e74474
AM		 2972 unsigned int suffixes = (~i.tm.opcode_modifier
2973 & (No_bSuf
2974 | No_wSuf
2975 | No_lSuf
2976 | No_sSuf
2977 | No_xSuf
2978 | No_qSuf));
9306ca4a
JB		 2979
2980 if ((i.tm.opcode_modifier & W)
2981 || ((suffixes & (suffixes - 1))
2982 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2983 {
2984 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2985 return 0;
2986 }
2987 }
29b0f896 2988 }
252b5132 2989
9306ca4a
JB		 2990 /* Change the opcode based on the operand size given by i.suffix;
2991 We don't need to change things for byte insns. */
2992
29b0f896
AM		 2993 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2994 {
2995 /* It's not a byte, select word/dword operation. */
2996 if (i.tm.opcode_modifier & W)
2997 {
2998 if (i.tm.opcode_modifier & ShortForm)
2999 i.tm.base_opcode |= 8;
3000 else
3001 i.tm.base_opcode |= 1;
3002 }
0f3f3d8b 3003
29b0f896
AM		 3004 /* Now select between word & dword operations via the operand
3005 size prefix, except for instructions that will ignore this
3006 prefix anyway. */
cb712a9e
L		 3007 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
3008 {
3009 /* monitor in SSE3 is a very special case. The default size
3010 of AX is the size of mode. The address size override
3011 prefix will change the size of AX. */
3012 if (i.op->regs[0].reg_type &
3013 (flag_code == CODE_32BIT ? Reg16 : Reg32))
3014 if (!add_prefix (ADDR_PREFIX_OPCODE))
3015 return 0;
3016 }
3017 else if (i.suffix != QWORD_MNEM_SUFFIX
3018 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
3019 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
3020 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3021 || (flag_code == CODE_64BIT
3022 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 3023 {
3024 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3025
29b0f896
AM		 3026 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
3027 prefix = ADDR_PREFIX_OPCODE;
252b5132 3028
29b0f896
AM		 3029 if (!add_prefix (prefix))
3030 return 0;
24eab124 3031 }
252b5132 3032
29b0f896
AM		 3033 /* Set mode64 for an operand. */
3034 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3035 && flag_code == CODE_64BIT
29b0f896 3036 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L		 3037 {
3038 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3039 need rex64. */
3040 if (i.operands != 2
3041 || i.types [0] != (Acc | Reg64)
3042 || i.types [1] != (Acc | Reg64)
3043 || strcmp (i.tm.name, "xchg") != 0)
3044 i.rex |= REX_MODE64;
3045 }
3e73aa7c 3046
29b0f896
AM		 3047 /* Size floating point instruction. */
3048 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 3049 if (i.tm.opcode_modifier & FloatMF)
3050 i.tm.base_opcode ^= 4;
29b0f896 3051 }
7ecd2f8b 3052
29b0f896
AM		 3053 return 1;
3054}
3e73aa7c 3055
29b0f896 3056static int
543613e9 3057check_byte_reg (void)
29b0f896
AM		 3058{
3059 int op;
543613e9 3060
29b0f896
AM		 3061 for (op = i.operands; --op >= 0;)
3062 {
3063 /* If this is an eight bit register, it's OK. If it's the 16 or
3064 32 bit version of an eight bit register, we will just use the
3065 low portion, and that's OK too. */
3066 if (i.types[op] & Reg8)
3067 continue;
3068
3069 /* movzx and movsx should not generate this warning. */
3070 if (intel_syntax
3071 && (i.tm.base_opcode == 0xfb7
3072 || i.tm.base_opcode == 0xfb6
3073 || i.tm.base_opcode == 0x63
3074 || i.tm.base_opcode == 0xfbe
3075 || i.tm.base_opcode == 0xfbf))
3076 continue;
3077
65ec77d2 3078 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3079 {
3080 /* Prohibit these changes in the 64bit mode, since the
3081 lowering is more complicated. */
3082 if (flag_code == CODE_64BIT
3083 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3084 {
0f3f3d8b 3085 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3086 i.op[op].regs->reg_name,
3087 i.suffix);
3088 return 0;
3089 }
3090#if REGISTER_WARNINGS
3091 if (!quiet_warnings
3092 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3093 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3094 (i.op[op].regs + (i.types[op] & Reg16
3095 ? REGNAM_AL - REGNAM_AX
3096 : REGNAM_AL - REGNAM_EAX))->reg_name,
3097 i.op[op].regs->reg_name,
3098 i.suffix);
3099#endif
3100 continue;
3101 }
3102 /* Any other register is bad. */
3103 if (i.types[op] & (Reg | RegMMX | RegXMM
3104 | SReg2 | SReg3
3105 | Control | Debug | Test
3106 | FloatReg | FloatAcc))
3107 {
3108 as_bad (_("`%%%s' not allowed with `%s%c'"),
3109 i.op[op].regs->reg_name,
3110 i.tm.name,
3111 i.suffix);
3112 return 0;
3113 }
3114 }
3115 return 1;
3116}
3117
3118static int
3119check_long_reg ()
3120{
3121 int op;
3122
3123 for (op = i.operands; --op >= 0;)
3124 /* Reject eight bit registers, except where the template requires
3125 them. (eg. movzb) */
3126 if ((i.types[op] & Reg8) != 0
3127 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3128 {
3129 as_bad (_("`%%%s' not allowed with `%s%c'"),
3130 i.op[op].regs->reg_name,
3131 i.tm.name,
3132 i.suffix);
3133 return 0;
3134 }
3135 /* Warn if the e prefix on a general reg is missing. */
3136 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3137 && (i.types[op] & Reg16) != 0
3138 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3139 {
3140 /* Prohibit these changes in the 64bit mode, since the
3141 lowering is more complicated. */
3142 if (flag_code == CODE_64BIT)
252b5132 3143 {
0f3f3d8b 3144 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3145 i.op[op].regs->reg_name,
3146 i.suffix);
3147 return 0;
252b5132 3148 }
29b0f896
AM		 3149#if REGISTER_WARNINGS
3150 else
3151 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3152 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3153 i.op[op].regs->reg_name,
3154 i.suffix);
3155#endif
252b5132 3156 }
29b0f896
AM		 3157 /* Warn if the r prefix on a general reg is missing. */
3158 else if ((i.types[op] & Reg64) != 0
3159 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 3160 {
0f3f3d8b 3161 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3162 i.op[op].regs->reg_name,
3163 i.suffix);
3164 return 0;
3165 }
3166 return 1;
3167}
252b5132 3168
29b0f896
AM		 3169static int
3170check_qword_reg ()
3171{
3172 int op;
252b5132 3173
29b0f896
AM		 3174 for (op = i.operands; --op >= 0; )
3175 /* Reject eight bit registers, except where the template requires
3176 them. (eg. movzb) */
3177 if ((i.types[op] & Reg8) != 0
3178 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3179 {
3180 as_bad (_("`%%%s' not allowed with `%s%c'"),
3181 i.op[op].regs->reg_name,
3182 i.tm.name,
3183 i.suffix);
3184 return 0;
3185 }
3186 /* Warn if the e prefix on a general reg is missing. */
3187 else if (((i.types[op] & Reg16) != 0
3188 || (i.types[op] & Reg32) != 0)
3189 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3190 {
3191 /* Prohibit these changes in the 64bit mode, since the
3192 lowering is more complicated. */
0f3f3d8b 3193 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3194 i.op[op].regs->reg_name,
3195 i.suffix);
3196 return 0;
252b5132 3197 }
29b0f896
AM		 3198 return 1;
3199}
252b5132 3200
29b0f896
AM		 3201static int
3202check_word_reg ()
3203{
3204 int op;
3205 for (op = i.operands; --op >= 0;)
3206 /* Reject eight bit registers, except where the template requires
3207 them. (eg. movzb) */
3208 if ((i.types[op] & Reg8) != 0
3209 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3210 {
3211 as_bad (_("`%%%s' not allowed with `%s%c'"),
3212 i.op[op].regs->reg_name,
3213 i.tm.name,
3214 i.suffix);
3215 return 0;
3216 }
3217 /* Warn if the e prefix on a general reg is present. */
3218 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3219 && (i.types[op] & Reg32) != 0
3220 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 3221 {
29b0f896
AM		 3222 /* Prohibit these changes in the 64bit mode, since the
3223 lowering is more complicated. */
3224 if (flag_code == CODE_64BIT)
252b5132 3225 {
0f3f3d8b 3226 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3227 i.op[op].regs->reg_name,
3228 i.suffix);
3229 return 0;
252b5132 3230 }
29b0f896
AM		 3231 else
3232#if REGISTER_WARNINGS
3233 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3234 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3235 i.op[op].regs->reg_name,
3236 i.suffix);
3237#endif
3238 }
3239 return 1;
3240}
252b5132 3241
29b0f896
AM		 3242static int
3243finalize_imm ()
3244{
3245 unsigned int overlap0, overlap1, overlap2;
3246
3247 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 3248 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 3249 && overlap0 != Imm8 && overlap0 != Imm8S
3250 && overlap0 != Imm16 && overlap0 != Imm32S
3251 && overlap0 != Imm32 && overlap0 != Imm64)
3252 {
3253 if (i.suffix)
3254 {
3255 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3256 ? Imm8 | Imm8S
3257 : (i.suffix == WORD_MNEM_SUFFIX
3258 ? Imm16
3259 : (i.suffix == QWORD_MNEM_SUFFIX
3260 ? Imm64 | Imm32S
3261 : Imm32)));
3262 }
3263 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3264 || overlap0 == (Imm16 | Imm32)
3265 || overlap0 == (Imm16 | Imm32S))
3266 {
3267 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3268 ? Imm16 : Imm32S);
3269 }
3270 if (overlap0 != Imm8 && overlap0 != Imm8S
3271 && overlap0 != Imm16 && overlap0 != Imm32S
3272 && overlap0 != Imm32 && overlap0 != Imm64)
3273 {
3274 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
3275 return 0;
3276 }
3277 }
3278 i.types[0] = overlap0;
3279
3280 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 3281 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 3282 && overlap1 != Imm8 && overlap1 != Imm8S
3283 && overlap1 != Imm16 && overlap1 != Imm32S
3284 && overlap1 != Imm32 && overlap1 != Imm64)
3285 {
3286 if (i.suffix)
3287 {
3288 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3289 ? Imm8 | Imm8S
3290 : (i.suffix == WORD_MNEM_SUFFIX
3291 ? Imm16
3292 : (i.suffix == QWORD_MNEM_SUFFIX
3293 ? Imm64 | Imm32S
3294 : Imm32)));
3295 }
3296 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3297 || overlap1 == (Imm16 | Imm32)
3298 || overlap1 == (Imm16 | Imm32S))
3299 {
3300 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3301 ? Imm16 : Imm32S);
3302 }
3303 if (overlap1 != Imm8 && overlap1 != Imm8S
3304 && overlap1 != Imm16 && overlap1 != Imm32S
3305 && overlap1 != Imm32 && overlap1 != Imm64)
3306 {
3307 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
3308 return 0;
3309 }
3310 }
3311 i.types[1] = overlap1;
3312
3313 overlap2 = i.types[2] & i.tm.operand_types[2];
3314 assert ((overlap2 & Imm) == 0);
3315 i.types[2] = overlap2;
3316
3317 return 1;
3318}
3319
3320static int
3321process_operands ()
3322{
3323 /* Default segment register this instruction will use for memory
3324 accesses. 0 means unknown. This is only for optimizing out
3325 unnecessary segment overrides. */
3326 const seg_entry *default_seg = 0;
3327
3328 /* The imul $imm, %reg instruction is converted into
3329 imul $imm, %reg, %reg, and the clr %reg instruction
3330 is converted into xor %reg, %reg. */
3331 if (i.tm.opcode_modifier & regKludge)
3332 {
3333 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3334 /* Pretend we saw the extra register operand. */
3335 assert (i.op[first_reg_op + 1].regs == 0);
3336 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3337 i.types[first_reg_op + 1] = i.types[first_reg_op];
3338 i.reg_operands = 2;
3339 }
3340
3341 if (i.tm.opcode_modifier & ShortForm)
3342 {
3343 /* The register or float register operand is in operand 0 or 1. */
3344 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3345 /* Register goes in low 3 bits of opcode. */
3346 i.tm.base_opcode |= i.op[op].regs->reg_num;
3347 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3348 i.rex |= REX_EXTZ;
3349 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
3350 {
3351 /* Warn about some common errors, but press on regardless.
3352 The first case can be generated by gcc (<= 2.8.1). */
3353 if (i.operands == 2)
3354 {
3355 /* Reversed arguments on faddp, fsubp, etc. */
3356 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3357 i.op[1].regs->reg_name,
3358 i.op[0].regs->reg_name);
3359 }
3360 else
3361 {
3362 /* Extraneous `l' suffix on fp insn. */
3363 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3364 i.op[0].regs->reg_name);
3365 }
3366 }
3367 }
3368 else if (i.tm.opcode_modifier & Modrm)
3369 {
3370 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3371 must be put into the modrm byte). Now, we make the modrm and
3372 index base bytes based on all the info we've collected. */
29b0f896
AM		 3373
3374 default_seg = build_modrm_byte ();
3375 }
3376 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
3377 {
3378 if (i.tm.base_opcode == POP_SEG_SHORT
3379 && i.op[0].regs->reg_num == 1)
3380 {
3381 as_bad (_("you can't `pop %%cs'"));
3382 return 0;
3383 }
3384 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3385 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3386 i.rex |= REX_EXTZ;
3387 }
3388 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
3389 {
3390 default_seg = &ds;
3391 }
3392 else if ((i.tm.opcode_modifier & IsString) != 0)
3393 {
3394 /* For the string instructions that allow a segment override
3395 on one of their operands, the default segment is ds. */
3396 default_seg = &ds;
3397 }
3398
30123838
JB		 3399 if ((i.tm.base_opcode == 0x8d /* lea */
3400 || (i.tm.cpu_flags & CpuSVME))
3401 && i.seg[0] && !quiet_warnings)
3402 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3403
3404 /* If a segment was explicitly specified, and the specified segment
3405 is not the default, use an opcode prefix to select it. If we
3406 never figured out what the default segment is, then default_seg
3407 will be zero at this point, and the specified segment prefix will
3408 always be used. */
29b0f896
AM		 3409 if ((i.seg[0]) && (i.seg[0] != default_seg))
3410 {
3411 if (!add_prefix (i.seg[0]->seg_prefix))
3412 return 0;
3413 }
3414 return 1;
3415}
3416
3417static const seg_entry *
3418build_modrm_byte ()
3419{
3420 const seg_entry *default_seg = 0;
3421
3422 /* i.reg_operands MUST be the number of real register operands;
3423 implicit registers do not count. */
3424 if (i.reg_operands == 2)
3425 {
3426 unsigned int source, dest;
3427 source = ((i.types[0]
3428 & (Reg | RegMMX | RegXMM
3429 | SReg2 | SReg3
3430 | Control | Debug | Test))
3431 ? 0 : 1);
050dfa73 3432
fc225355
L		 3433 /* In 4 operands instructions with 2 immediate operands, the first
3434 two are immediate bytes and hence source operand will be in the
3435 next byte after the immediates */
050dfa73 3436 if ((i.operands == 4)&&(i.imm_operands=2)) source++;
29b0f896
AM		 3437 dest = source + 1;
3438
3439 i.rm.mode = 3;
3440 /* One of the register operands will be encoded in the i.tm.reg
3441 field, the other in the combined i.tm.mode and i.tm.regmem
3442 fields. If no form of this instruction supports a memory
3443 destination operand, then we assume the source operand may
3444 sometimes be a memory operand and so we need to store the
3445 destination in the i.rm.reg field. */
3446 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3447 {
3448 i.rm.reg = i.op[dest].regs->reg_num;
3449 i.rm.regmem = i.op[source].regs->reg_num;
3450 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3451 i.rex |= REX_EXTX;
3452 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3453 i.rex |= REX_EXTZ;
3454 }
3455 else
3456 {
3457 i.rm.reg = i.op[source].regs->reg_num;
3458 i.rm.regmem = i.op[dest].regs->reg_num;
3459 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3460 i.rex |= REX_EXTZ;
3461 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3462 i.rex |= REX_EXTX;
3463 }
c4a530c5
JB		 3464 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3465 {
3466 if (!((i.types[0] | i.types[1]) & Control))
3467 abort ();
3468 i.rex &= ~(REX_EXTX | REX_EXTZ);
3469 add_prefix (LOCK_PREFIX_OPCODE);
3470 }
29b0f896
AM		 3471 }
3472 else
3473 { /* If it's not 2 reg operands... */
3474 if (i.mem_operands)
3475 {
3476 unsigned int fake_zero_displacement = 0;
3477 unsigned int op = ((i.types[0] & AnyMem)
3478 ? 0
3479 : (i.types[1] & AnyMem) ? 1 : 2);
3480
3481 default_seg = &ds;
3482
3483 if (i.base_reg == 0)
3484 {
3485 i.rm.mode = 0;
3486 if (!i.disp_operands)
3487 fake_zero_displacement = 1;
3488 if (i.index_reg == 0)
3489 {
3490 /* Operand is just <disp> */
20f0a1fc 3491 if (flag_code == CODE_64BIT)
29b0f896
AM		 3492 {
3493 /* 64bit mode overwrites the 32bit absolute
3494 addressing by RIP relative addressing and
3495 absolute addressing is encoded by one of the
3496 redundant SIB forms. */
3497 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3498 i.sib.base = NO_BASE_REGISTER;
3499 i.sib.index = NO_INDEX_REGISTER;
fc225355
L		 3500 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3501 ? Disp32S : Disp32);
20f0a1fc 3502 }
fc225355
L		 3503 else if ((flag_code == CODE_16BIT)
3504 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 3505 {
3506 i.rm.regmem = NO_BASE_REGISTER_16;
3507 i.types[op] = Disp16;
3508 }
3509 else
3510 {
3511 i.rm.regmem = NO_BASE_REGISTER;
3512 i.types[op] = Disp32;
29b0f896
AM		 3513 }
3514 }
3515 else /* !i.base_reg && i.index_reg */
3516 {
3517 i.sib.index = i.index_reg->reg_num;
3518 i.sib.base = NO_BASE_REGISTER;
3519 i.sib.scale = i.log2_scale_factor;
3520 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3521 i.types[op] &= ~Disp;
3522 if (flag_code != CODE_64BIT)
3523 i.types[op] |= Disp32; /* Must be 32 bit */
3524 else
3525 i.types[op] |= Disp32S;
3526 if ((i.index_reg->reg_flags & RegRex) != 0)
3527 i.rex |= REX_EXTY;
3528 }
3529 }
3530 /* RIP addressing for 64bit mode. */
3531 else if (i.base_reg->reg_type == BaseIndex)
3532 {
3533 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3534 i.types[op] &= ~ Disp;
29b0f896 3535 i.types[op] |= Disp32S;
71903a11 3536 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 3537 if (! i.disp_operands)
3538 fake_zero_displacement = 1;
29b0f896
AM		 3539 }
3540 else if (i.base_reg->reg_type & Reg16)
3541 {
3542 switch (i.base_reg->reg_num)
3543 {
3544 case 3: /* (%bx) */
3545 if (i.index_reg == 0)
3546 i.rm.regmem = 7;
3547 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3548 i.rm.regmem = i.index_reg->reg_num - 6;
3549 break;
3550 case 5: /* (%bp) */
3551 default_seg = &ss;
3552 if (i.index_reg == 0)
3553 {
3554 i.rm.regmem = 6;
3555 if ((i.types[op] & Disp) == 0)
3556 {
3557 /* fake (%bp) into 0(%bp) */
3558 i.types[op] |= Disp8;
252b5132 3559 fake_zero_displacement = 1;
29b0f896
AM		 3560 }
3561 }
3562 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3563 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3564 break;
3565 default: /* (%si) -> 4 or (%di) -> 5 */
3566 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3567 }
3568 i.rm.mode = mode_from_disp_size (i.types[op]);
3569 }
3570 else /* i.base_reg and 32/64 bit mode */
3571 {
3572 if (flag_code == CODE_64BIT
3573 && (i.types[op] & Disp))
fc225355
L		 3574 i.types[op] = ((i.types[op] & Disp8)
3575 | (i.prefix[ADDR_PREFIX] == 0
3576 ? Disp32S : Disp32));
20f0a1fc 3577
29b0f896
AM		 3578 i.rm.regmem = i.base_reg->reg_num;
3579 if ((i.base_reg->reg_flags & RegRex) != 0)
3580 i.rex |= REX_EXTZ;
3581 i.sib.base = i.base_reg->reg_num;
3582 /* x86-64 ignores REX prefix bit here to avoid decoder
3583 complications. */
3584 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3585 {
3586 default_seg = &ss;
3587 if (i.disp_operands == 0)
3588 {
3589 fake_zero_displacement = 1;
3590 i.types[op] |= Disp8;
3591 }
3592 }
3593 else if (i.base_reg->reg_num == ESP_REG_NUM)
3594 {
3595 default_seg = &ss;
3596 }
3597 i.sib.scale = i.log2_scale_factor;
3598 if (i.index_reg == 0)
3599 {
3600 /* <disp>(%esp) becomes two byte modrm with no index
3601 register. We've already stored the code for esp
3602 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3603 Any base register besides %esp will not use the
3604 extra modrm byte. */
3605 i.sib.index = NO_INDEX_REGISTER;
3606#if !SCALE1_WHEN_NO_INDEX
3607 /* Another case where we force the second modrm byte. */
3608 if (i.log2_scale_factor)
3609 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3610#endif
29b0f896
AM		 3611 }
3612 else
3613 {
3614 i.sib.index = i.index_reg->reg_num;
3615 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3616 if ((i.index_reg->reg_flags & RegRex) != 0)
3617 i.rex |= REX_EXTY;
3618 }
67a4f2b7
AO		 3619
3620 if (i.disp_operands
3621 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3622 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3623 i.rm.mode = 0;
3624 else
3625 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3626 }
252b5132 3627
29b0f896
AM		 3628 if (fake_zero_displacement)
3629 {
3630 /* Fakes a zero displacement assuming that i.types[op]
3631 holds the correct displacement size. */
3632 expressionS *exp;
3633
3634 assert (i.op[op].disps == 0);
3635 exp = &disp_expressions[i.disp_operands++];
3636 i.op[op].disps = exp;
3637 exp->X_op = O_constant;
3638 exp->X_add_number = 0;
3639 exp->X_add_symbol = (symbolS *) 0;
3640 exp->X_op_symbol = (symbolS *) 0;
3641 }
3642 }
252b5132 3643
29b0f896
AM		 3644 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3645 (if any) based on i.tm.extension_opcode. Again, we must be
3646 careful to make sure that segment/control/debug/test/MMX
3647 registers are coded into the i.rm.reg field. */
3648 if (i.reg_operands)
3649 {
3650 unsigned int op =
3651 ((i.types[0]
3652 & (Reg | RegMMX | RegXMM
3653 | SReg2 | SReg3
3654 | Control | Debug | Test))
3655 ? 0
3656 : ((i.types[1]
3657 & (Reg | RegMMX | RegXMM
3658 | SReg2 | SReg3
3659 | Control | Debug | Test))
3660 ? 1
3661 : 2));
3662 /* If there is an extension opcode to put here, the register
3663 number must be put into the regmem field. */
3664 if (i.tm.extension_opcode != None)
3665 {
3666 i.rm.regmem = i.op[op].regs->reg_num;
3667 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3668 i.rex |= REX_EXTZ;
3669 }
3670 else
3671 {
3672 i.rm.reg = i.op[op].regs->reg_num;
3673 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3674 i.rex |= REX_EXTX;
3675 }
252b5132 3676
29b0f896
AM		 3677 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3678 must set it to 3 to indicate this is a register operand
3679 in the regmem field. */
3680 if (!i.mem_operands)
3681 i.rm.mode = 3;
3682 }
252b5132 3683
29b0f896
AM		 3684 /* Fill in i.rm.reg field with extension opcode (if any). */
3685 if (i.tm.extension_opcode != None)
3686 i.rm.reg = i.tm.extension_opcode;
3687 }
3688 return default_seg;
3689}
252b5132 3690
29b0f896
AM		 3691static void
3692output_branch ()
3693{
3694 char *p;
3695 int code16;
3696 int prefix;
3697 relax_substateT subtype;
3698 symbolS *sym;
3699 offsetT off;
3700
3701 code16 = 0;
3702 if (flag_code == CODE_16BIT)
3703 code16 = CODE16;
3704
3705 prefix = 0;
3706 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3707 {
29b0f896
AM		 3708 prefix = 1;
3709 i.prefixes -= 1;
3710 code16 ^= CODE16;
252b5132 3711 }
29b0f896
AM		 3712 /* Pentium4 branch hints. */
3713 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3714 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3715 {
29b0f896
AM		 3716 prefix++;
3717 i.prefixes--;
3718 }
3719 if (i.prefix[REX_PREFIX] != 0)
3720 {
3721 prefix++;
3722 i.prefixes--;
2f66722d
AM		 3723 }
3724
29b0f896
AM		 3725 if (i.prefixes != 0 && !intel_syntax)
3726 as_warn (_("skipping prefixes on this instruction"));
3727
3728 /* It's always a symbol; End frag & setup for relax.
3729 Make sure there is enough room in this frag for the largest
3730 instruction we may generate in md_convert_frag. This is 2
3731 bytes for the opcode and room for the prefix and largest
3732 displacement. */
3733 frag_grow (prefix + 2 + 4);
3734 /* Prefix and 1 opcode byte go in fr_fix. */
3735 p = frag_more (prefix + 1);
3736 if (i.prefix[DATA_PREFIX] != 0)
3737 *p++ = DATA_PREFIX_OPCODE;
3738 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3739 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3740 *p++ = i.prefix[SEG_PREFIX];
3741 if (i.prefix[REX_PREFIX] != 0)
3742 *p++ = i.prefix[REX_PREFIX];
3743 *p = i.tm.base_opcode;
3744
3745 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3746 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3747 else if ((cpu_arch_flags & Cpu386) != 0)
3748 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3749 else
3750 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3751 subtype |= code16;
3e73aa7c 3752
29b0f896
AM		 3753 sym = i.op[0].disps->X_add_symbol;
3754 off = i.op[0].disps->X_add_number;
3e73aa7c 3755
29b0f896
AM		 3756 if (i.op[0].disps->X_op != O_constant
3757 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3758 {
29b0f896
AM		 3759 /* Handle complex expressions. */
3760 sym = make_expr_symbol (i.op[0].disps);
3761 off = 0;
3762 }
3e73aa7c 3763
29b0f896
AM		 3764 /* 1 possible extra opcode + 4 byte displacement go in var part.
3765 Pass reloc in fr_var. */
3766 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3767}
3e73aa7c 3768
29b0f896
AM		 3769static void
3770output_jump ()
3771{
3772 char *p;
3773 int size;
3e02c1cc 3774 fixS *fixP;
29b0f896
AM		 3775
3776 if (i.tm.opcode_modifier & JumpByte)
3777 {
3778 /* This is a loop or jecxz type instruction. */
3779 size = 1;
3780 if (i.prefix[ADDR_PREFIX] != 0)
3781 {
3782 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3783 i.prefixes -= 1;
3784 }
3785 /* Pentium4 branch hints. */
3786 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3787 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3788 {
3789 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3790 i.prefixes--;
3e73aa7c
JH		 3791 }
3792 }
29b0f896
AM		 3793 else
3794 {
3795 int code16;
3e73aa7c 3796
29b0f896
AM		 3797 code16 = 0;
3798 if (flag_code == CODE_16BIT)
3799 code16 = CODE16;
3e73aa7c 3800
29b0f896
AM		 3801 if (i.prefix[DATA_PREFIX] != 0)
3802 {
3803 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3804 i.prefixes -= 1;
3805 code16 ^= CODE16;
3806 }
252b5132 3807
29b0f896
AM		 3808 size = 4;
3809 if (code16)
3810 size = 2;
3811 }
9fcc94b6 3812
29b0f896
AM		 3813 if (i.prefix[REX_PREFIX] != 0)
3814 {
3815 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3816 i.prefixes -= 1;
3817 }
252b5132 3818
29b0f896
AM		 3819 if (i.prefixes != 0 && !intel_syntax)
3820 as_warn (_("skipping prefixes on this instruction"));
e0890092 3821
29b0f896
AM		 3822 p = frag_more (1 + size);
3823 *p++ = i.tm.base_opcode;
e0890092 3824
3e02c1cc
AM		 3825 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3826 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3827
3828 /* All jumps handled here are signed, but don't use a signed limit
3829 check for 32 and 16 bit jumps as we want to allow wrap around at
3830 4G and 64k respectively. */
3831 if (size == 1)
3832 fixP->fx_signed = 1;
29b0f896 3833}
e0890092 3834
29b0f896
AM		 3835static void
3836output_interseg_jump ()
3837{
3838 char *p;
3839 int size;
3840 int prefix;
3841 int code16;
252b5132 3842
29b0f896
AM		 3843 code16 = 0;
3844 if (flag_code == CODE_16BIT)
3845 code16 = CODE16;
a217f122 3846
29b0f896
AM		 3847 prefix = 0;
3848 if (i.prefix[DATA_PREFIX] != 0)
3849 {
3850 prefix = 1;
3851 i.prefixes -= 1;
3852 code16 ^= CODE16;
3853 }
3854 if (i.prefix[REX_PREFIX] != 0)
3855 {
3856 prefix++;
3857 i.prefixes -= 1;
3858 }
252b5132 3859
29b0f896
AM		 3860 size = 4;
3861 if (code16)
3862 size = 2;
252b5132 3863
29b0f896
AM		 3864 if (i.prefixes != 0 && !intel_syntax)
3865 as_warn (_("skipping prefixes on this instruction"));
252b5132 3866
29b0f896
AM		 3867 /* 1 opcode; 2 segment; offset */
3868 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3869
29b0f896
AM		 3870 if (i.prefix[DATA_PREFIX] != 0)
3871 *p++ = DATA_PREFIX_OPCODE;
252b5132 3872
29b0f896
AM		 3873 if (i.prefix[REX_PREFIX] != 0)
3874 *p++ = i.prefix[REX_PREFIX];
252b5132 3875
29b0f896
AM		 3876 *p++ = i.tm.base_opcode;
3877 if (i.op[1].imms->X_op == O_constant)
3878 {
3879 offsetT n = i.op[1].imms->X_add_number;
252b5132 3880
29b0f896
AM		 3881 if (size == 2
3882 && !fits_in_unsigned_word (n)
3883 && !fits_in_signed_word (n))
3884 {
3885 as_bad (_("16-bit jump out of range"));
3886 return;
3887 }
3888 md_number_to_chars (p, n, size);
3889 }
3890 else
3891 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3892 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3893 if (i.op[0].imms->X_op != O_constant)
3894 as_bad (_("can't handle non absolute segment in `%s'"),
3895 i.tm.name);
3896 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3897}
a217f122 3898
29b0f896
AM		 3899static void
3900output_insn ()
3901{
2bbd9c25
JJ		 3902 fragS *insn_start_frag;
3903 offsetT insn_start_off;
3904
29b0f896
AM		 3905 /* Tie dwarf2 debug info to the address at the start of the insn.
3906 We can't do this after the insn has been output as the current
3907 frag may have been closed off. eg. by frag_var. */
3908 dwarf2_emit_insn (0);
3909
2bbd9c25
JJ		 3910 insn_start_frag = frag_now;
3911 insn_start_off = frag_now_fix ();
3912
29b0f896
AM		 3913 /* Output jumps. */
3914 if (i.tm.opcode_modifier & Jump)
3915 output_branch ();
3916 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3917 output_jump ();
3918 else if (i.tm.opcode_modifier & JumpInterSegment)
3919 output_interseg_jump ();
3920 else
3921 {
3922 /* Output normal instructions here. */
3923 char *p;
3924 unsigned char *q;
331d2d0d 3925 unsigned int prefix;
252b5132 3926
ef05d495
L		 3927 /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
3928 Streaming SIMD extensions 3 Instructions have 3 bytes. We may
3929 use one more higher byte to specify a prefix the instruction
3930 requires. */
3931 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
bc4bd9ab 3932 {
331d2d0d
L		 3933 if (i.tm.base_opcode & 0xff000000)
3934 {
3935 prefix = (i.tm.base_opcode >> 24) & 0xff;
3936 goto check_prefix;
3937 }
3938 }
3939 else if ((i.tm.base_opcode & 0xff0000) != 0)
3940 {
3941 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 3942 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3943 {
64e74474 3944 check_prefix:
bc4bd9ab
MK		 3945 if (prefix != REPE_PREFIX_OPCODE
3946 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3947 add_prefix (prefix);
3948 }
3949 else
331d2d0d 3950 add_prefix (prefix);
0f10071e 3951 }
252b5132 3952
29b0f896
AM		 3953 /* The prefix bytes. */
3954 for (q = i.prefix;
3955 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3956 q++)
3957 {
3958 if (*q)
3959 {
3960 p = frag_more (1);
3961 md_number_to_chars (p, (valueT) *q, 1);
3962 }
3963 }
252b5132 3964
29b0f896
AM		 3965 /* Now the opcode; be careful about word order here! */
3966 if (fits_in_unsigned_byte (i.tm.base_opcode))
3967 {
3968 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3969 }
3970 else
3971 {
ef05d495 3972 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
331d2d0d
L		 3973 {
3974 p = frag_more (3);
3975 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3976 }
3977 else
3978 p = frag_more (2);
0f10071e 3979
29b0f896
AM		 3980 /* Put out high byte first: can't use md_number_to_chars! */
3981 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3982 *p = i.tm.base_opcode & 0xff;
3983 }
3e73aa7c 3984
29b0f896
AM		 3985 /* Now the modrm byte and sib byte (if present). */
3986 if (i.tm.opcode_modifier & Modrm)
3987 {
3988 p = frag_more (1);
3989 md_number_to_chars (p,
3990 (valueT) (i.rm.regmem << 0
3991 | i.rm.reg << 3
3992 | i.rm.mode << 6),
3993 1);
3994 /* If i.rm.regmem == ESP (4)
3995 && i.rm.mode != (Register mode)
3996 && not 16 bit
3997 ==> need second modrm byte. */
3998 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3999 && i.rm.mode != 3
4000 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
4001 {
4002 p = frag_more (1);
4003 md_number_to_chars (p,
4004 (valueT) (i.sib.base << 0
4005 | i.sib.index << 3
4006 | i.sib.scale << 6),
4007 1);
4008 }
4009 }
3e73aa7c 4010
29b0f896 4011 if (i.disp_operands)
2bbd9c25 4012 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 4013
29b0f896 4014 if (i.imm_operands)
2bbd9c25 4015 output_imm (insn_start_frag, insn_start_off);
29b0f896 4016 }
252b5132 4017
29b0f896
AM		 4018#ifdef DEBUG386
4019 if (flag_debug)
4020 {
7b81dfbb 4021 pi ("" /*line*/, &i);
29b0f896
AM		 4022 }
4023#endif /* DEBUG386 */
4024}
252b5132 4025
29b0f896 4026static void
64e74474 4027output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4028{
4029 char *p;
4030 unsigned int n;
252b5132 4031
29b0f896
AM		 4032 for (n = 0; n < i.operands; n++)
4033 {
4034 if (i.types[n] & Disp)
4035 {
4036 if (i.op[n].disps->X_op == O_constant)
4037 {
4038 int size;
4039 offsetT val;
252b5132 4040
29b0f896
AM		 4041 size = 4;
4042 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4043 {
4044 size = 2;
4045 if (i.types[n] & Disp8)
4046 size = 1;
4047 if (i.types[n] & Disp64)
4048 size = 8;
4049 }
4050 val = offset_in_range (i.op[n].disps->X_add_number,
4051 size);
4052 p = frag_more (size);
4053 md_number_to_chars (p, val, size);
4054 }
4055 else
4056 {
f86103b7 4057 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4058 int size = 4;
4059 int sign = 0;
4060 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4061
4062 /* The PC relative address is computed relative
4063 to the instruction boundary, so in case immediate
4064 fields follows, we need to adjust the value. */
4065 if (pcrel && i.imm_operands)
4066 {
4067 int imm_size = 4;
4068 unsigned int n1;
252b5132 4069
29b0f896
AM		 4070 for (n1 = 0; n1 < i.operands; n1++)
4071 if (i.types[n1] & Imm)
252b5132 4072 {
29b0f896 4073 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 4074 {
29b0f896
AM		 4075 imm_size = 2;
4076 if (i.types[n1] & (Imm8 | Imm8S))
4077 imm_size = 1;
4078 if (i.types[n1] & Imm64)
4079 imm_size = 8;
252b5132 4080 }
29b0f896 4081 break;
252b5132 4082 }
29b0f896
AM		 4083 /* We should find the immediate. */
4084 if (n1 == i.operands)
4085 abort ();
4086 i.op[n].disps->X_add_number -= imm_size;
4087 }
520dc8e8 4088
29b0f896
AM		 4089 if (i.types[n] & Disp32S)
4090 sign = 1;
3e73aa7c 4091
29b0f896
AM		 4092 if (i.types[n] & (Disp16 | Disp64))
4093 {
4094 size = 2;
4095 if (i.types[n] & Disp64)
4096 size = 8;
4097 }
520dc8e8 4098
29b0f896 4099 p = frag_more (size);
2bbd9c25 4100 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4101 if (GOT_symbol
2bbd9c25 4102 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4103 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4104 || reloc_type == BFD_RELOC_X86_64_32S
4105 || (reloc_type == BFD_RELOC_64
4106 && object_64bit))
d6ab8113
JB		 4107 && (i.op[n].disps->X_op == O_symbol
4108 || (i.op[n].disps->X_op == O_add
4109 && ((symbol_get_value_expression
4110 (i.op[n].disps->X_op_symbol)->X_op)
4111 == O_subtract))))
4112 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4113 {
4114 offsetT add;
4115
4116 if (insn_start_frag == frag_now)
4117 add = (p - frag_now->fr_literal) - insn_start_off;
4118 else
4119 {
4120 fragS *fr;
4121
4122 add = insn_start_frag->fr_fix - insn_start_off;
4123 for (fr = insn_start_frag->fr_next;
4124 fr && fr != frag_now; fr = fr->fr_next)
4125 add += fr->fr_fix;
4126 add += p - frag_now->fr_literal;
4127 }
4128
4fa24527 4129 if (!object_64bit)
7b81dfbb
AJ		 4130 {
4131 reloc_type = BFD_RELOC_386_GOTPC;
4132 i.op[n].imms->X_add_number += add;
4133 }
4134 else if (reloc_type == BFD_RELOC_64)
4135 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4136 else
7b81dfbb
AJ		 4137 /* Don't do the adjustment for x86-64, as there
4138 the pcrel addressing is relative to the _next_
4139 insn, and that is taken care of in other code. */
d6ab8113 4140 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4141 }
062cd5e7 4142 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4143 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4144 }
4145 }
4146 }
4147}
252b5132 4148
29b0f896 4149static void
64e74474 4150output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4151{
4152 char *p;
4153 unsigned int n;
252b5132 4154
29b0f896
AM		 4155 for (n = 0; n < i.operands; n++)
4156 {
4157 if (i.types[n] & Imm)
4158 {
4159 if (i.op[n].imms->X_op == O_constant)
4160 {
4161 int size;
4162 offsetT val;
b4cac588 4163
29b0f896
AM		 4164 size = 4;
4165 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4166 {
4167 size = 2;
4168 if (i.types[n] & (Imm8 | Imm8S))
4169 size = 1;
4170 else if (i.types[n] & Imm64)
4171 size = 8;
4172 }
4173 val = offset_in_range (i.op[n].imms->X_add_number,
4174 size);
4175 p = frag_more (size);
4176 md_number_to_chars (p, val, size);
4177 }
4178 else
4179 {
4180 /* Not absolute_section.
4181 Need a 32-bit fixup (don't support 8bit
4182 non-absolute imms). Try to support other
4183 sizes ... */
f86103b7 4184 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4185 int size = 4;
4186 int sign = 0;
4187
4188 if ((i.types[n] & (Imm32S))
a7d61044
JB		 4189 && (i.suffix == QWORD_MNEM_SUFFIX
4190 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 4191 sign = 1;
4192 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4193 {
4194 size = 2;
4195 if (i.types[n] & (Imm8 | Imm8S))
4196 size = 1;
4197 if (i.types[n] & Imm64)
4198 size = 8;
4199 }
520dc8e8 4200
29b0f896
AM		 4201 p = frag_more (size);
4202 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4203
2bbd9c25
JJ		 4204 /* This is tough to explain. We end up with this one if we
4205 * have operands that look like
4206 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4207 * obtain the absolute address of the GOT, and it is strongly
4208 * preferable from a performance point of view to avoid using
4209 * a runtime relocation for this. The actual sequence of
4210 * instructions often look something like:
4211 *
4212 * call .L66
4213 * .L66:
4214 * popl %ebx
4215 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4216 *
4217 * The call and pop essentially return the absolute address
4218 * of the label .L66 and store it in %ebx. The linker itself
4219 * will ultimately change the first operand of the addl so
4220 * that %ebx points to the GOT, but to keep things simple, the
4221 * .o file must have this operand set so that it generates not
4222 * the absolute address of .L66, but the absolute address of
4223 * itself. This allows the linker itself simply treat a GOTPC
4224 * relocation as asking for a pcrel offset to the GOT to be
4225 * added in, and the addend of the relocation is stored in the
4226 * operand field for the instruction itself.
4227 *
4228 * Our job here is to fix the operand so that it would add
4229 * the correct offset so that %ebx would point to itself. The
4230 * thing that is tricky is that .-.L66 will point to the
4231 * beginning of the instruction, so we need to further modify
4232 * the operand so that it will point to itself. There are
4233 * other cases where you have something like:
4234 *
4235 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4236 *
4237 * and here no correction would be required. Internally in
4238 * the assembler we treat operands of this form as not being
4239 * pcrel since the '.' is explicitly mentioned, and I wonder
4240 * whether it would simplify matters to do it this way. Who
4241 * knows. In earlier versions of the PIC patches, the
4242 * pcrel_adjust field was used to store the correction, but
4243 * since the expression is not pcrel, I felt it would be
4244 * confusing to do it this way. */
4245
d6ab8113 4246 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4247 || reloc_type == BFD_RELOC_X86_64_32S
4248 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4249 && GOT_symbol
4250 && GOT_symbol == i.op[n].imms->X_add_symbol
4251 && (i.op[n].imms->X_op == O_symbol
4252 || (i.op[n].imms->X_op == O_add
4253 && ((symbol_get_value_expression
4254 (i.op[n].imms->X_op_symbol)->X_op)
4255 == O_subtract))))
4256 {
2bbd9c25
JJ		 4257 offsetT add;
4258
4259 if (insn_start_frag == frag_now)
4260 add = (p - frag_now->fr_literal) - insn_start_off;
4261 else
4262 {
4263 fragS *fr;
4264
4265 add = insn_start_frag->fr_fix - insn_start_off;
4266 for (fr = insn_start_frag->fr_next;
4267 fr && fr != frag_now; fr = fr->fr_next)
4268 add += fr->fr_fix;
4269 add += p - frag_now->fr_literal;
4270 }
4271
4fa24527 4272 if (!object_64bit)
d6ab8113 4273 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4274 else if (size == 4)
d6ab8113 4275 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4276 else if (size == 8)
4277 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4278 i.op[n].imms->X_add_number += add;
29b0f896 4279 }
29b0f896
AM		 4280 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4281 i.op[n].imms, 0, reloc_type);
4282 }
4283 }
4284 }
252b5132
RH		 4285}
4286\f
d182319b
JB		 4287/* x86_cons_fix_new is called via the expression parsing code when a
4288 reloc is needed. We use this hook to get the correct .got reloc. */
4289static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4290static int cons_sign = -1;
4291
4292void
4293x86_cons_fix_new (fragS *frag,
64e74474
AM		 4294 unsigned int off,
4295 unsigned int len,
4296 expressionS *exp)
d182319b
JB		 4297{
4298 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4299
4300 got_reloc = NO_RELOC;
4301
4302#ifdef TE_PE
4303 if (exp->X_op == O_secrel)
4304 {
4305 exp->X_op = O_symbol;
4306 r = BFD_RELOC_32_SECREL;
4307 }
4308#endif
4309
4310 fix_new_exp (frag, off, len, exp, 0, r);
4311}
4312
718ddfc0
JB		 4313#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4314# define lex_got(reloc, adjust, types) NULL
4315#else
f3c180ae
AM		 4316/* Parse operands of the form
4317 <symbol>@GOTOFF+<nnn>
4318 and similar .plt or .got references.
4319
4320 If we find one, set up the correct relocation in RELOC and copy the
4321 input string, minus the `@GOTOFF' into a malloc'd buffer for
4322 parsing by the calling routine. Return this buffer, and if ADJUST
4323 is non-null set it to the length of the string we removed from the
4324 input line. Otherwise return NULL. */
4325static char *
3956db08 4326lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 4327 int *adjust,
4328 unsigned int *types)
f3c180ae 4329{
7b81dfbb
AJ		 4330 /* Some of the relocations depend on the size of what field is to
4331 be relocated. But in our callers i386_immediate and i386_displacement
4332 we don't yet know the operand size (this will be set by insn
4333 matching). Hence we record the word32 relocation here,
4334 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4335 static const struct {
4336 const char *str;
4fa24527 4337 const enum bfd_reloc_code_real rel[2];
3956db08 4338 const unsigned int types64;
f3c180ae 4339 } gotrel[] = {
7b81dfbb 4340 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
4fa24527 4341 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
7b81dfbb 4342 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
4fa24527
JB		 4343 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
4344 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
4345 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
4346 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
4347 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
4348 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
4349 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4350 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
4351 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4352 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
4353 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
7b81dfbb 4354 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 },
67a4f2b7
AO		 4355 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
4356 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 4357 };
4358 char *cp;
4359 unsigned int j;
4360
718ddfc0
JB		 4361 if (!IS_ELF)
4362 return NULL;
4363
f3c180ae
AM		 4364 for (cp = input_line_pointer; *cp != '@'; cp++)
4365 if (is_end_of_line[(unsigned char) *cp])
4366 return NULL;
4367
4368 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4369 {
4370 int len;
4371
4372 len = strlen (gotrel[j].str);
28f81592 4373 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4374 {
4fa24527 4375 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4376 {
28f81592
AM		 4377 int first, second;
4378 char *tmpbuf, *past_reloc;
f3c180ae 4379
4fa24527 4380 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 4381 if (adjust)
4382 *adjust = len;
f3c180ae 4383
3956db08
JB		 4384 if (types)
4385 {
4386 if (flag_code != CODE_64BIT)
4387 *types = Imm32|Disp32;
4388 else
4389 *types = gotrel[j].types64;
4390 }
4391
f3c180ae
AM		 4392 if (GOT_symbol == NULL)
4393 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4394
4395 /* Replace the relocation token with ' ', so that
4396 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 4397
4398 /* The length of the first part of our input line. */
f3c180ae 4399 first = cp - input_line_pointer;
28f81592
AM		 4400
4401 /* The second part goes from after the reloc token until
4402 (and including) an end_of_line char. Don't use strlen
4403 here as the end_of_line char may not be a NUL. */
4404 past_reloc = cp + 1 + len;
4405 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4406 ;
4407 second = cp - past_reloc;
4408
4409 /* Allocate and copy string. The trailing NUL shouldn't
4410 be necessary, but be safe. */
4411 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 4412 memcpy (tmpbuf, input_line_pointer, first);
4413 tmpbuf[first] = ' ';
28f81592
AM		 4414 memcpy (tmpbuf + first + 1, past_reloc, second);
4415 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 4416 return tmpbuf;
4417 }
4418
4fa24527
JB		 4419 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4420 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 4421 return NULL;
4422 }
4423 }
4424
4425 /* Might be a symbol version string. Don't as_bad here. */
4426 return NULL;
4427}
4428
f3c180ae
AM		 4429void
4430x86_cons (exp, size)
4431 expressionS *exp;
4432 int size;
4433{
4fa24527 4434 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 4435 {
4436 /* Handle @GOTOFF and the like in an expression. */
4437 char *save;
4438 char *gotfree_input_line;
4439 int adjust;
4440
4441 save = input_line_pointer;
3956db08 4442 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4443 if (gotfree_input_line)
4444 input_line_pointer = gotfree_input_line;
4445
4446 expression (exp);
4447
4448 if (gotfree_input_line)
4449 {
4450 /* expression () has merrily parsed up to the end of line,
4451 or a comma - in the wrong buffer. Transfer how far
4452 input_line_pointer has moved to the right buffer. */
4453 input_line_pointer = (save
4454 + (input_line_pointer - gotfree_input_line)
4455 + adjust);
4456 free (gotfree_input_line);
4457 }
4458 }
4459 else
4460 expression (exp);
4461}
4462#endif
4463
d182319b 4464static void signed_cons (int size)
6482c264 4465{
d182319b
JB		 4466 if (flag_code == CODE_64BIT)
4467 cons_sign = 1;
4468 cons (size);
4469 cons_sign = -1;
6482c264
NC		 4470}
4471
d182319b 4472#ifdef TE_PE
6482c264
NC		 4473static void
4474pe_directive_secrel (dummy)
4475 int dummy ATTRIBUTE_UNUSED;
4476{
4477 expressionS exp;
4478
4479 do
4480 {
4481 expression (&exp);
4482 if (exp.X_op == O_symbol)
4483 exp.X_op = O_secrel;
4484
4485 emit_expr (&exp, 4);
4486 }
4487 while (*input_line_pointer++ == ',');
4488
4489 input_line_pointer--;
4490 demand_empty_rest_of_line ();
4491}
6482c264
NC		 4492#endif
4493
252b5132
RH		 4494static int i386_immediate PARAMS ((char *));
4495
4496static int
4497i386_immediate (imm_start)
4498 char *imm_start;
4499{
4500 char *save_input_line_pointer;
f3c180ae 4501 char *gotfree_input_line;
252b5132 4502 segT exp_seg = 0;
47926f60 4503 expressionS *exp;
3956db08 4504 unsigned int types = ~0U;
252b5132
RH		 4505
4506 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4507 {
d0b47220 4508 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 4509 return 0;
4510 }
4511
4512 exp = &im_expressions[i.imm_operands++];
520dc8e8 4513 i.op[this_operand].imms = exp;
252b5132
RH		 4514
4515 if (is_space_char (*imm_start))
4516 ++imm_start;
4517
4518 save_input_line_pointer = input_line_pointer;
4519 input_line_pointer = imm_start;
4520
3956db08 4521 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4522 if (gotfree_input_line)
4523 input_line_pointer = gotfree_input_line;
252b5132
RH		 4524
4525 exp_seg = expression (exp);
4526
83183c0c 4527 SKIP_WHITESPACE ();
252b5132 4528 if (*input_line_pointer)
f3c180ae 4529 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4530
4531 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4532 if (gotfree_input_line)
4533 free (gotfree_input_line);
252b5132 4534
2daf4fd8 4535 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4536 {
47926f60 4537 /* Missing or bad expr becomes absolute 0. */
d0b47220 4538 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4539 imm_start);
252b5132
RH		 4540 exp->X_op = O_constant;
4541 exp->X_add_number = 0;
4542 exp->X_add_symbol = (symbolS *) 0;
4543 exp->X_op_symbol = (symbolS *) 0;
252b5132 4544 }
3e73aa7c 4545 else if (exp->X_op == O_constant)
252b5132 4546 {
47926f60 4547 /* Size it properly later. */
3e73aa7c
JH		 4548 i.types[this_operand] |= Imm64;
4549 /* If BFD64, sign extend val. */
4550 if (!use_rela_relocations)
4551 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4552 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4553 }
4c63da97 4554#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4555 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4556 && exp_seg != absolute_section
47926f60 4557 && exp_seg != text_section
24eab124
AM		 4558 && exp_seg != data_section
4559 && exp_seg != bss_section
4560 && exp_seg != undefined_section
f86103b7 4561 && !bfd_is_com_section (exp_seg))
252b5132 4562 {
d0b47220 4563 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4564 return 0;
4565 }
4566#endif
bb8f5920
L		 4567 else if (!intel_syntax && exp->X_op == O_register)
4568 {
4569 as_bad (_("illegal immediate register operand %s"), imm_start);
4570 return 0;
4571 }
252b5132
RH		 4572 else
4573 {
4574 /* This is an address. The size of the address will be
24eab124 4575 determined later, depending on destination register,
3e73aa7c
JH		 4576 suffix, or the default for the section. */
4577 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4578 i.types[this_operand] &= types;
252b5132
RH		 4579 }
4580
4581 return 1;
4582}
4583
551c1ca1 4584static char *i386_scale PARAMS ((char *));
252b5132 4585
551c1ca1 4586static char *
252b5132
RH		 4587i386_scale (scale)
4588 char *scale;
4589{
551c1ca1
AM		 4590 offsetT val;
4591 char *save = input_line_pointer;
252b5132 4592
551c1ca1
AM		 4593 input_line_pointer = scale;
4594 val = get_absolute_expression ();
4595
4596 switch (val)
252b5132 4597 {
551c1ca1 4598 case 1:
252b5132
RH		 4599 i.log2_scale_factor = 0;
4600 break;
551c1ca1 4601 case 2:
252b5132
RH		 4602 i.log2_scale_factor = 1;
4603 break;
551c1ca1 4604 case 4:
252b5132
RH		 4605 i.log2_scale_factor = 2;
4606 break;
551c1ca1 4607 case 8:
252b5132
RH		 4608 i.log2_scale_factor = 3;
4609 break;
4610 default:
a724f0f4
JB		 4611 {
4612 char sep = *input_line_pointer;
4613
4614 *input_line_pointer = '\0';
4615 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4616 scale);
4617 *input_line_pointer = sep;
4618 input_line_pointer = save;
4619 return NULL;
4620 }
252b5132 4621 }
29b0f896 4622 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4623 {
4624 as_warn (_("scale factor of %d without an index register"),
24eab124 4625 1 << i.log2_scale_factor);
252b5132
RH		 4626#if SCALE1_WHEN_NO_INDEX
4627 i.log2_scale_factor = 0;
4628#endif
4629 }
551c1ca1
AM		 4630 scale = input_line_pointer;
4631 input_line_pointer = save;
4632 return scale;
252b5132
RH		 4633}
4634
4635static int i386_displacement PARAMS ((char *, char *));
4636
4637static int
4638i386_displacement (disp_start, disp_end)
4639 char *disp_start;
4640 char *disp_end;
4641{
29b0f896 4642 expressionS *exp;
252b5132
RH		 4643 segT exp_seg = 0;
4644 char *save_input_line_pointer;
f3c180ae 4645 char *gotfree_input_line;
e05278af 4646 int bigdisp, override;
3956db08 4647 unsigned int types = Disp;
252b5132 4648
e05278af
JB		 4649 if ((i.types[this_operand] & JumpAbsolute)
4650 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4651 {
4652 bigdisp = Disp32;
4653 override = (i.prefix[ADDR_PREFIX] != 0);
4654 }
4655 else
4656 {
4657 /* For PC-relative branches, the width of the displacement
4658 is dependent upon data size, not address size. */
4659 bigdisp = 0;
4660 override = (i.prefix[DATA_PREFIX] != 0);
4661 }
3e73aa7c 4662 if (flag_code == CODE_64BIT)
7ecd2f8b 4663 {
e05278af 4664 if (!bigdisp)
64e74474
AM		 4665 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4666 ? Disp16
4667 : Disp32S | Disp32);
e05278af 4668 else if (!override)
3956db08 4669 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4670 }
e05278af
JB		 4671 else
4672 {
4673 if (!bigdisp)
4674 {
4675 if (!override)
4676 override = (i.suffix == (flag_code != CODE_16BIT
4677 ? WORD_MNEM_SUFFIX
4678 : LONG_MNEM_SUFFIX));
4679 bigdisp = Disp32;
4680 }
4681 if ((flag_code == CODE_16BIT) ^ override)
4682 bigdisp = Disp16;
4683 }
252b5132
RH		 4684 i.types[this_operand] |= bigdisp;
4685
4686 exp = &disp_expressions[i.disp_operands];
520dc8e8 4687 i.op[this_operand].disps = exp;
252b5132
RH		 4688 i.disp_operands++;
4689 save_input_line_pointer = input_line_pointer;
4690 input_line_pointer = disp_start;
4691 END_STRING_AND_SAVE (disp_end);
4692
4693#ifndef GCC_ASM_O_HACK
4694#define GCC_ASM_O_HACK 0
4695#endif
4696#if GCC_ASM_O_HACK
4697 END_STRING_AND_SAVE (disp_end + 1);
4698 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4699 && displacement_string_end[-1] == '+')
252b5132
RH		 4700 {
4701 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4702 constraint within gcc asm statements.
4703 For instance:
4704
4705 #define _set_tssldt_desc(n,addr,limit,type) \
4706 __asm__ __volatile__ ( \
4707 "movw %w2,%0\n\t" \
4708 "movw %w1,2+%0\n\t" \
4709 "rorl $16,%1\n\t" \
4710 "movb %b1,4+%0\n\t" \
4711 "movb %4,5+%0\n\t" \
4712 "movb $0,6+%0\n\t" \
4713 "movb %h1,7+%0\n\t" \
4714 "rorl $16,%1" \
4715 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4716
4717 This works great except that the output assembler ends
4718 up looking a bit weird if it turns out that there is
4719 no offset. You end up producing code that looks like:
4720
4721 #APP
4722 movw $235,(%eax)
4723 movw %dx,2+(%eax)
4724 rorl $16,%edx
4725 movb %dl,4+(%eax)
4726 movb $137,5+(%eax)
4727 movb $0,6+(%eax)
4728 movb %dh,7+(%eax)
4729 rorl $16,%edx
4730 #NO_APP
4731
47926f60 4732 So here we provide the missing zero. */
24eab124
AM		 4733
4734 *displacement_string_end = '0';
252b5132
RH		 4735 }
4736#endif
3956db08 4737 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4738 if (gotfree_input_line)
4739 input_line_pointer = gotfree_input_line;
252b5132 4740
24eab124 4741 exp_seg = expression (exp);
252b5132 4742
636c26b0
AM		 4743 SKIP_WHITESPACE ();
4744 if (*input_line_pointer)
4745 as_bad (_("junk `%s' after expression"), input_line_pointer);
4746#if GCC_ASM_O_HACK
4747 RESTORE_END_STRING (disp_end + 1);
4748#endif
4749 RESTORE_END_STRING (disp_end);
4750 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4751 if (gotfree_input_line)
4752 free (gotfree_input_line);
636c26b0 4753
24eab124
AM		 4754 /* We do this to make sure that the section symbol is in
4755 the symbol table. We will ultimately change the relocation
47926f60 4756 to be relative to the beginning of the section. */
1ae12ab7 4757 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4758 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4759 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4760 {
636c26b0
AM		 4761 if (exp->X_op != O_symbol)
4762 {
4763 as_bad (_("bad expression used with @%s"),
4764 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4765 ? "GOTPCREL"
4766 : "GOTOFF"));
4767 return 0;
4768 }
4769
e5cb08ac 4770 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4771 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4772 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4773 exp->X_op = O_subtract;
4774 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4775 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4776 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4777 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4778 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4779 else
29b0f896 4780 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4781 }
252b5132 4782
2daf4fd8
AM		 4783 if (exp->X_op == O_absent || exp->X_op == O_big)
4784 {
47926f60 4785 /* Missing or bad expr becomes absolute 0. */
d0b47220 4786 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4787 disp_start);
4788 exp->X_op = O_constant;
4789 exp->X_add_number = 0;
4790 exp->X_add_symbol = (symbolS *) 0;
4791 exp->X_op_symbol = (symbolS *) 0;
4792 }
4793
4c63da97 4794#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4795 if (exp->X_op != O_constant
45288df1 4796 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4797 && exp_seg != absolute_section
45288df1
AM		 4798 && exp_seg != text_section
4799 && exp_seg != data_section
4800 && exp_seg != bss_section
31312f95 4801 && exp_seg != undefined_section
f86103b7 4802 && !bfd_is_com_section (exp_seg))
24eab124 4803 {
d0b47220 4804 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4805 return 0;
4806 }
252b5132 4807#endif
3956db08
JB		 4808
4809 if (!(i.types[this_operand] & ~Disp))
4810 i.types[this_operand] &= types;
4811
252b5132
RH		 4812 return 1;
4813}
4814
e5cb08ac 4815static int i386_index_check PARAMS ((const char *));
252b5132 4816
eecb386c 4817/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4818 Return 1 on success, 0 on a failure. */
4819
252b5132 4820static int
eecb386c
AM		 4821i386_index_check (operand_string)
4822 const char *operand_string;
252b5132 4823{
3e73aa7c 4824 int ok;
24eab124 4825#if INFER_ADDR_PREFIX
eecb386c
AM		 4826 int fudged = 0;
4827
24eab124
AM		 4828 tryprefix:
4829#endif
3e73aa7c 4830 ok = 1;
30123838
JB		 4831 if ((current_templates->start->cpu_flags & CpuSVME)
4832 && current_templates->end[-1].operand_types[0] == AnyMem)
4833 {
4834 /* Memory operands of SVME insns are special in that they only allow
4835 rAX as their memory address and ignore any segment override. */
4836 unsigned RegXX;
4837
4838 /* SKINIT is even more restrictive: it always requires EAX. */
4839 if (strcmp (current_templates->start->name, "skinit") == 0)
4840 RegXX = Reg32;
4841 else if (flag_code == CODE_64BIT)
4842 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4843 else
64e74474
AM		 4844 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4845 ? Reg16
4846 : Reg32);
30123838
JB		 4847 if (!i.base_reg
4848 || !(i.base_reg->reg_type & Acc)
4849 || !(i.base_reg->reg_type & RegXX)
4850 || i.index_reg
4851 || (i.types[0] & Disp))
4852 ok = 0;
4853 }
4854 else if (flag_code == CODE_64BIT)
64e74474
AM		 4855 {
4856 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4857
4858 if ((i.base_reg
4859 && ((i.base_reg->reg_type & RegXX) == 0)
4860 && (i.base_reg->reg_type != BaseIndex
4861 || i.index_reg))
4862 || (i.index_reg
4863 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4864 != (RegXX | BaseIndex))))
4865 ok = 0;
3e73aa7c
JH		 4866 }
4867 else
4868 {
4869 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4870 {
4871 /* 16bit checks. */
4872 if ((i.base_reg
29b0f896
AM		 4873 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4874 != (Reg16 | BaseIndex)))
3e73aa7c 4875 || (i.index_reg
29b0f896
AM		 4876 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4877 != (Reg16 | BaseIndex))
4878 || !(i.base_reg
4879 && i.base_reg->reg_num < 6
4880 && i.index_reg->reg_num >= 6
4881 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4882 ok = 0;
4883 }
4884 else
e5cb08ac 4885 {
3e73aa7c
JH		 4886 /* 32bit checks. */
4887 if ((i.base_reg
4888 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4889 || (i.index_reg
29b0f896
AM		 4890 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4891 != (Reg32 | BaseIndex))))
e5cb08ac 4892 ok = 0;
3e73aa7c
JH		 4893 }
4894 }
4895 if (!ok)
24eab124
AM		 4896 {
4897#if INFER_ADDR_PREFIX
20f0a1fc 4898 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4899 {
4900 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4901 i.prefixes += 1;
b23bac36
AM		 4902 /* Change the size of any displacement too. At most one of
4903 Disp16 or Disp32 is set.
4904 FIXME. There doesn't seem to be any real need for separate
4905 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4906 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4907 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 4908 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4909 fudged = 1;
24eab124
AM		 4910 goto tryprefix;
4911 }
eecb386c
AM		 4912 if (fudged)
4913 as_bad (_("`%s' is not a valid base/index expression"),
4914 operand_string);
4915 else
c388dee8 4916#endif
eecb386c
AM		 4917 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4918 operand_string,
3e73aa7c 4919 flag_code_names[flag_code]);
24eab124 4920 }
20f0a1fc 4921 return ok;
24eab124 4922}
252b5132 4923
252b5132 4924/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4925 on error. */
252b5132 4926
252b5132
RH		 4927static int
4928i386_operand (operand_string)
4929 char *operand_string;
4930{
af6bdddf
AM		 4931 const reg_entry *r;
4932 char *end_op;
24eab124 4933 char *op_string = operand_string;
252b5132 4934
24eab124 4935 if (is_space_char (*op_string))
252b5132
RH		 4936 ++op_string;
4937
24eab124 4938 /* We check for an absolute prefix (differentiating,
47926f60 4939 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4940 if (*op_string == ABSOLUTE_PREFIX)
4941 {
4942 ++op_string;
4943 if (is_space_char (*op_string))
4944 ++op_string;
4945 i.types[this_operand] |= JumpAbsolute;
4946 }
252b5132 4947
47926f60 4948 /* Check if operand is a register. */
4d1bb795 4949 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 4950 {
24eab124
AM		 4951 /* Check for a segment override by searching for ':' after a
4952 segment register. */
4953 op_string = end_op;
4954 if (is_space_char (*op_string))
4955 ++op_string;
4956 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4957 {
4958 switch (r->reg_num)
4959 {
4960 case 0:
4961 i.seg[i.mem_operands] = &es;
4962 break;
4963 case 1:
4964 i.seg[i.mem_operands] = &cs;
4965 break;
4966 case 2:
4967 i.seg[i.mem_operands] = &ss;
4968 break;
4969 case 3:
4970 i.seg[i.mem_operands] = &ds;
4971 break;
4972 case 4:
4973 i.seg[i.mem_operands] = &fs;
4974 break;
4975 case 5:
4976 i.seg[i.mem_operands] = &gs;
4977 break;
4978 }
252b5132 4979
24eab124 4980 /* Skip the ':' and whitespace. */
252b5132
RH		 4981 ++op_string;
4982 if (is_space_char (*op_string))
24eab124 4983 ++op_string;
252b5132 4984
24eab124
AM		 4985 if (!is_digit_char (*op_string)
4986 && !is_identifier_char (*op_string)
4987 && *op_string != '('
4988 && *op_string != ABSOLUTE_PREFIX)
4989 {
4990 as_bad (_("bad memory operand `%s'"), op_string);
4991 return 0;
4992 }
47926f60 4993 /* Handle case of %es:*foo. */
24eab124
AM		 4994 if (*op_string == ABSOLUTE_PREFIX)
4995 {
4996 ++op_string;
4997 if (is_space_char (*op_string))
4998 ++op_string;
4999 i.types[this_operand] |= JumpAbsolute;
5000 }
5001 goto do_memory_reference;
5002 }
5003 if (*op_string)
5004 {
d0b47220 5005 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 5006 return 0;
5007 }
5008 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 5009 i.op[this_operand].regs = r;
24eab124
AM		 5010 i.reg_operands++;
5011 }
af6bdddf
AM		 5012 else if (*op_string == REGISTER_PREFIX)
5013 {
5014 as_bad (_("bad register name `%s'"), op_string);
5015 return 0;
5016 }
24eab124 5017 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 5018 {
24eab124
AM		 5019 ++op_string;
5020 if (i.types[this_operand] & JumpAbsolute)
5021 {
d0b47220 5022 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 5023 return 0;
5024 }
5025 if (!i386_immediate (op_string))
5026 return 0;
5027 }
5028 else if (is_digit_char (*op_string)
5029 || is_identifier_char (*op_string)
e5cb08ac 5030 || *op_string == '(')
24eab124 5031 {
47926f60 5032 /* This is a memory reference of some sort. */
af6bdddf 5033 char *base_string;
252b5132 5034
47926f60 5035 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 5036 char *displacement_string_start;
5037 char *displacement_string_end;
252b5132 5038
24eab124 5039 do_memory_reference:
24eab124
AM		 5040 if ((i.mem_operands == 1
5041 && (current_templates->start->opcode_modifier & IsString) == 0)
5042 || i.mem_operands == 2)
5043 {
5044 as_bad (_("too many memory references for `%s'"),
5045 current_templates->start->name);
5046 return 0;
5047 }
252b5132 5048
24eab124
AM		 5049 /* Check for base index form. We detect the base index form by
5050 looking for an ')' at the end of the operand, searching
5051 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5052 after the '('. */
af6bdddf 5053 base_string = op_string + strlen (op_string);
c3332e24 5054
af6bdddf
AM		 5055 --base_string;
5056 if (is_space_char (*base_string))
5057 --base_string;
252b5132 5058
47926f60 5059 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 5060 displacement_string_start = op_string;
5061 displacement_string_end = base_string + 1;
252b5132 5062
24eab124
AM		 5063 if (*base_string == ')')
5064 {
af6bdddf 5065 char *temp_string;
24eab124
AM		 5066 unsigned int parens_balanced = 1;
5067 /* We've already checked that the number of left & right ()'s are
47926f60 5068 equal, so this loop will not be infinite. */
24eab124
AM		 5069 do
5070 {
5071 base_string--;
5072 if (*base_string == ')')
5073 parens_balanced++;
5074 if (*base_string == '(')
5075 parens_balanced--;
5076 }
5077 while (parens_balanced);
c3332e24 5078
af6bdddf 5079 temp_string = base_string;
c3332e24 5080
24eab124 5081 /* Skip past '(' and whitespace. */
252b5132
RH		 5082 ++base_string;
5083 if (is_space_char (*base_string))
24eab124 5084 ++base_string;
252b5132 5085
af6bdddf 5086 if (*base_string == ','
4d1bb795 5087 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 5088 {
af6bdddf 5089 displacement_string_end = temp_string;
252b5132 5090
af6bdddf 5091 i.types[this_operand] |= BaseIndex;
252b5132 5092
af6bdddf 5093 if (i.base_reg)
24eab124 5094 {
24eab124
AM		 5095 base_string = end_op;
5096 if (is_space_char (*base_string))
5097 ++base_string;
af6bdddf
AM		 5098 }
5099
5100 /* There may be an index reg or scale factor here. */
5101 if (*base_string == ',')
5102 {
5103 ++base_string;
5104 if (is_space_char (*base_string))
5105 ++base_string;
5106
4d1bb795 5107 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 5108 {
af6bdddf 5109 base_string = end_op;
24eab124
AM		 5110 if (is_space_char (*base_string))
5111 ++base_string;
af6bdddf
AM		 5112 if (*base_string == ',')
5113 {
5114 ++base_string;
5115 if (is_space_char (*base_string))
5116 ++base_string;
5117 }
e5cb08ac 5118 else if (*base_string != ')')
af6bdddf
AM		 5119 {
5120 as_bad (_("expecting `,' or `)' after index register in `%s'"),
5121 operand_string);
5122 return 0;
5123 }
24eab124 5124 }
af6bdddf 5125 else if (*base_string == REGISTER_PREFIX)
24eab124 5126 {
af6bdddf 5127 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5128 return 0;
5129 }
252b5132 5130
47926f60 5131 /* Check for scale factor. */
551c1ca1 5132 if (*base_string != ')')
af6bdddf 5133 {
551c1ca1
AM		 5134 char *end_scale = i386_scale (base_string);
5135
5136 if (!end_scale)
af6bdddf 5137 return 0;
24eab124 5138
551c1ca1 5139 base_string = end_scale;
af6bdddf
AM		 5140 if (is_space_char (*base_string))
5141 ++base_string;
5142 if (*base_string != ')')
5143 {
5144 as_bad (_("expecting `)' after scale factor in `%s'"),
5145 operand_string);
5146 return 0;
5147 }
5148 }
5149 else if (!i.index_reg)
24eab124 5150 {
af6bdddf
AM		 5151 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
5152 *base_string);
24eab124
AM		 5153 return 0;
5154 }
5155 }
af6bdddf 5156 else if (*base_string != ')')
24eab124 5157 {
af6bdddf
AM		 5158 as_bad (_("expecting `,' or `)' after base register in `%s'"),
5159 operand_string);
24eab124
AM		 5160 return 0;
5161 }
c3332e24 5162 }
af6bdddf 5163 else if (*base_string == REGISTER_PREFIX)
c3332e24 5164 {
af6bdddf 5165 as_bad (_("bad register name `%s'"), base_string);
24eab124 5166 return 0;
c3332e24 5167 }
24eab124
AM		 5168 }
5169
5170 /* If there's an expression beginning the operand, parse it,
5171 assuming displacement_string_start and
5172 displacement_string_end are meaningful. */
5173 if (displacement_string_start != displacement_string_end)
5174 {
5175 if (!i386_displacement (displacement_string_start,
5176 displacement_string_end))
5177 return 0;
5178 }
5179
5180 /* Special case for (%dx) while doing input/output op. */
5181 if (i.base_reg
5182 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5183 && i.index_reg == 0
5184 && i.log2_scale_factor == 0
5185 && i.seg[i.mem_operands] == 0
5186 && (i.types[this_operand] & Disp) == 0)
5187 {
5188 i.types[this_operand] = InOutPortReg;
5189 return 1;
5190 }
5191
eecb386c
AM		 5192 if (i386_index_check (operand_string) == 0)
5193 return 0;
24eab124
AM		 5194 i.mem_operands++;
5195 }
5196 else
ce8a8b2f
AM		 5197 {
5198 /* It's not a memory operand; argh! */
24eab124
AM		 5199 as_bad (_("invalid char %s beginning operand %d `%s'"),
5200 output_invalid (*op_string),
5201 this_operand + 1,
5202 op_string);
5203 return 0;
5204 }
47926f60 5205 return 1; /* Normal return. */
252b5132
RH		 5206}
5207\f
ee7fcc42
AM		 5208/* md_estimate_size_before_relax()
5209
5210 Called just before relax() for rs_machine_dependent frags. The x86
5211 assembler uses these frags to handle variable size jump
5212 instructions.
5213
5214 Any symbol that is now undefined will not become defined.
5215 Return the correct fr_subtype in the frag.
5216 Return the initial "guess for variable size of frag" to caller.
5217 The guess is actually the growth beyond the fixed part. Whatever
5218 we do to grow the fixed or variable part contributes to our
5219 returned value. */
5220
252b5132
RH		 5221int
5222md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5223 fragS *fragP;
5224 segT segment;
252b5132 5225{
252b5132 5226 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5227 check for un-relaxable symbols. On an ELF system, we can't relax
5228 an externally visible symbol, because it may be overridden by a
5229 shared library. */
5230 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5231#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5232 || (IS_ELF
31312f95
AM		 5233 && (S_IS_EXTERNAL (fragP->fr_symbol)
5234 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5235#endif
5236 )
252b5132 5237 {
b98ef147
AM		 5238 /* Symbol is undefined in this segment, or we need to keep a
5239 reloc so that weak symbols can be overridden. */
5240 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5241 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5242 unsigned char *opcode;
5243 int old_fr_fix;
f6af82bd 5244
ee7fcc42
AM		 5245 if (fragP->fr_var != NO_RELOC)
5246 reloc_type = fragP->fr_var;
b98ef147 5247 else if (size == 2)
f6af82bd
AM		 5248 reloc_type = BFD_RELOC_16_PCREL;
5249 else
5250 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5251
ee7fcc42
AM		 5252 old_fr_fix = fragP->fr_fix;
5253 opcode = (unsigned char *) fragP->fr_opcode;
5254
fddf5b5b 5255 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5256 {
fddf5b5b
AM		 5257 case UNCOND_JUMP:
5258 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5259 opcode[0] = 0xe9;
252b5132 5260 fragP->fr_fix += size;
062cd5e7
AS		 5261 fix_new (fragP, old_fr_fix, size,
5262 fragP->fr_symbol,
5263 fragP->fr_offset, 1,
5264 reloc_type);
252b5132
RH		 5265 break;
5266
fddf5b5b 5267 case COND_JUMP86:
412167cb
AM		 5268 if (size == 2
5269 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5270 {
5271 /* Negate the condition, and branch past an
5272 unconditional jump. */
5273 opcode[0] ^= 1;
5274 opcode[1] = 3;
5275 /* Insert an unconditional jump. */
5276 opcode[2] = 0xe9;
5277 /* We added two extra opcode bytes, and have a two byte
5278 offset. */
5279 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5280 fix_new (fragP, old_fr_fix + 2, 2,
5281 fragP->fr_symbol,
5282 fragP->fr_offset, 1,
5283 reloc_type);
fddf5b5b
AM		 5284 break;
5285 }
5286 /* Fall through. */
5287
5288 case COND_JUMP:
412167cb
AM		 5289 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5290 {
3e02c1cc
AM		 5291 fixS *fixP;
5292
412167cb 5293 fragP->fr_fix += 1;
3e02c1cc
AM		 5294 fixP = fix_new (fragP, old_fr_fix, 1,
5295 fragP->fr_symbol,
5296 fragP->fr_offset, 1,
5297 BFD_RELOC_8_PCREL);
5298 fixP->fx_signed = 1;
412167cb
AM		 5299 break;
5300 }
93c2a809 5301
24eab124 5302 /* This changes the byte-displacement jump 0x7N
fddf5b5b 5303 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 5304 opcode[1] = opcode[0] + 0x10;
f6af82bd 5305 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 5306 /* We've added an opcode byte. */
5307 fragP->fr_fix += 1 + size;
062cd5e7
AS		 5308 fix_new (fragP, old_fr_fix + 1, size,
5309 fragP->fr_symbol,
5310 fragP->fr_offset, 1,
5311 reloc_type);
252b5132 5312 break;
fddf5b5b
AM		 5313
5314 default:
5315 BAD_CASE (fragP->fr_subtype);
5316 break;
252b5132
RH		 5317 }
5318 frag_wane (fragP);
ee7fcc42 5319 return fragP->fr_fix - old_fr_fix;
252b5132 5320 }
93c2a809 5321
93c2a809
AM		 5322 /* Guess size depending on current relax state. Initially the relax
5323 state will correspond to a short jump and we return 1, because
5324 the variable part of the frag (the branch offset) is one byte
5325 long. However, we can relax a section more than once and in that
5326 case we must either set fr_subtype back to the unrelaxed state,
5327 or return the value for the appropriate branch. */
5328 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 5329}
5330
47926f60
KH		 5331/* Called after relax() is finished.
5332
5333 In: Address of frag.
5334 fr_type == rs_machine_dependent.
5335 fr_subtype is what the address relaxed to.
5336
5337 Out: Any fixSs and constants are set up.
5338 Caller will turn frag into a ".space 0". */
5339
252b5132
RH		 5340void
5341md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 5342 bfd *abfd ATTRIBUTE_UNUSED;
5343 segT sec ATTRIBUTE_UNUSED;
29b0f896 5344 fragS *fragP;
252b5132 5345{
29b0f896 5346 unsigned char *opcode;
252b5132 5347 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 5348 offsetT target_address;
5349 offsetT opcode_address;
252b5132 5350 unsigned int extension = 0;
847f7ad4 5351 offsetT displacement_from_opcode_start;
252b5132
RH		 5352
5353 opcode = (unsigned char *) fragP->fr_opcode;
5354
47926f60 5355 /* Address we want to reach in file space. */
252b5132 5356 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 5357
47926f60 5358 /* Address opcode resides at in file space. */
252b5132
RH		 5359 opcode_address = fragP->fr_address + fragP->fr_fix;
5360
47926f60 5361 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 5362 displacement_from_opcode_start = target_address - opcode_address;
5363
fddf5b5b 5364 if ((fragP->fr_subtype & BIG) == 0)
252b5132 5365 {
47926f60
KH		 5366 /* Don't have to change opcode. */
5367 extension = 1; /* 1 opcode + 1 displacement */
252b5132 5368 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 5369 }
5370 else
5371 {
5372 if (no_cond_jump_promotion
5373 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
5374 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 5375
fddf5b5b
AM		 5376 switch (fragP->fr_subtype)
5377 {
5378 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5379 extension = 4; /* 1 opcode + 4 displacement */
5380 opcode[0] = 0xe9;
5381 where_to_put_displacement = &opcode[1];
5382 break;
252b5132 5383
fddf5b5b
AM		 5384 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5385 extension = 2; /* 1 opcode + 2 displacement */
5386 opcode[0] = 0xe9;
5387 where_to_put_displacement = &opcode[1];
5388 break;
252b5132 5389
fddf5b5b
AM		 5390 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5391 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5392 extension = 5; /* 2 opcode + 4 displacement */
5393 opcode[1] = opcode[0] + 0x10;
5394 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5395 where_to_put_displacement = &opcode[2];
5396 break;
252b5132 5397
fddf5b5b
AM		 5398 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5399 extension = 3; /* 2 opcode + 2 displacement */
5400 opcode[1] = opcode[0] + 0x10;
5401 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5402 where_to_put_displacement = &opcode[2];
5403 break;
252b5132 5404
fddf5b5b
AM		 5405 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5406 extension = 4;
5407 opcode[0] ^= 1;
5408 opcode[1] = 3;
5409 opcode[2] = 0xe9;
5410 where_to_put_displacement = &opcode[3];
5411 break;
5412
5413 default:
5414 BAD_CASE (fragP->fr_subtype);
5415 break;
5416 }
252b5132 5417 }
fddf5b5b 5418
7b81dfbb
AJ		 5419 /* If size if less then four we are sure that the operand fits,
5420 but if it's 4, then it could be that the displacement is larger
5421 then -/+ 2GB. */
5422 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5423 && object_64bit
5424 && ((addressT) (displacement_from_opcode_start - extension
5425 + ((addressT) 1 << 31))
5426 > (((addressT) 2 << 31) - 1)))
5427 {
5428 as_bad_where (fragP->fr_file, fragP->fr_line,
5429 _("jump target out of range"));
5430 /* Make us emit 0. */
5431 displacement_from_opcode_start = extension;
5432 }
47926f60 5433 /* Now put displacement after opcode. */
252b5132
RH		 5434 md_number_to_chars ((char *) where_to_put_displacement,
5435 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5436 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5437 fragP->fr_fix += extension;
5438}
5439\f
47926f60
KH		 5440/* Size of byte displacement jmp. */
5441int md_short_jump_size = 2;
5442
5443/* Size of dword displacement jmp. */
5444int md_long_jump_size = 5;
252b5132 5445
252b5132
RH		 5446void
5447md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5448 char *ptr;
5449 addressT from_addr, to_addr;
ab9da554
ILT		 5450 fragS *frag ATTRIBUTE_UNUSED;
5451 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5452{
847f7ad4 5453 offsetT offset;
252b5132
RH		 5454
5455 offset = to_addr - (from_addr + 2);
47926f60
KH		 5456 /* Opcode for byte-disp jump. */
5457 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5458 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5459}
5460
5461void
5462md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5463 char *ptr;
5464 addressT from_addr, to_addr;
a38cf1db
AM		 5465 fragS *frag ATTRIBUTE_UNUSED;
5466 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5467{
847f7ad4 5468 offsetT offset;
252b5132 5469
a38cf1db
AM		 5470 offset = to_addr - (from_addr + 5);
5471 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5472 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5473}
5474\f
5475/* Apply a fixup (fixS) to segment data, once it has been determined
5476 by our caller that we have all the info we need to fix it up.
5477
5478 On the 386, immediates, displacements, and data pointers are all in
5479 the same (little-endian) format, so we don't need to care about which
5480 we are handling. */
5481
94f592af 5482void
55cf6793 5483md_apply_fix (fixP, valP, seg)
47926f60
KH		 5484 /* The fix we're to put in. */
5485 fixS *fixP;
47926f60 5486 /* Pointer to the value of the bits. */
c6682705 5487 valueT *valP;
47926f60
KH		 5488 /* Segment fix is from. */
5489 segT seg ATTRIBUTE_UNUSED;
252b5132 5490{
94f592af 5491 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5492 valueT value = *valP;
252b5132 5493
f86103b7 5494#if !defined (TE_Mach)
93382f6d
AM		 5495 if (fixP->fx_pcrel)
5496 {
5497 switch (fixP->fx_r_type)
5498 {
5865bb77
ILT		 5499 default:
5500 break;
5501
d6ab8113
JB		 5502 case BFD_RELOC_64:
5503 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5504 break;
93382f6d 5505 case BFD_RELOC_32:
ae8887b5 5506 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5507 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5508 break;
5509 case BFD_RELOC_16:
5510 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5511 break;
5512 case BFD_RELOC_8:
5513 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5514 break;
5515 }
5516 }
252b5132 5517
a161fe53 5518 if (fixP->fx_addsy != NULL
31312f95 5519 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5520 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5521 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5522 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5523 && !use_rela_relocations)
252b5132 5524 {
31312f95
AM		 5525 /* This is a hack. There should be a better way to handle this.
5526 This covers for the fact that bfd_install_relocation will
5527 subtract the current location (for partial_inplace, PC relative
5528 relocations); see more below. */
252b5132 5529#ifndef OBJ_AOUT
718ddfc0 5530 if (IS_ELF
252b5132
RH		 5531#ifdef TE_PE
5532 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5533#endif
5534 )
5535 value += fixP->fx_where + fixP->fx_frag->fr_address;
5536#endif
5537#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5538 if (IS_ELF)
252b5132 5539 {
6539b54b 5540 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5541
6539b54b 5542 if ((sym_seg == seg
2f66722d 5543 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5544 && sym_seg != absolute_section))
ae6063d4 5545 && !generic_force_reloc (fixP))
2f66722d
AM		 5546 {
5547 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5548 bfd_install_relocation subtracts them out again. I think
5549 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5550 it. FIXME. */
5551 value += fixP->fx_where + fixP->fx_frag->fr_address;
5552 }
252b5132
RH		 5553 }
5554#endif
5555#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5556 /* For some reason, the PE format does not store a
5557 section address offset for a PC relative symbol. */
5558 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5559 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5560 value += md_pcrel_from (fixP);
5561#endif
5562 }
5563
5564 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5565 and we must not disappoint it. */
252b5132 5566#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5567 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5568 switch (fixP->fx_r_type)
5569 {
5570 case BFD_RELOC_386_PLT32:
3e73aa7c 5571 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5572 /* Make the jump instruction point to the address of the operand. At
5573 runtime we merely add the offset to the actual PLT entry. */
5574 value = -4;
5575 break;
31312f95 5576
13ae64f3
JJ		 5577 case BFD_RELOC_386_TLS_GD:
5578 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5579 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5580 case BFD_RELOC_386_TLS_IE:
5581 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5582 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5583 case BFD_RELOC_X86_64_TLSGD:
5584 case BFD_RELOC_X86_64_TLSLD:
5585 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5586 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5587 value = 0; /* Fully resolved at runtime. No addend. */
5588 /* Fallthrough */
5589 case BFD_RELOC_386_TLS_LE:
5590 case BFD_RELOC_386_TLS_LDO_32:
5591 case BFD_RELOC_386_TLS_LE_32:
5592 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5593 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5594 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5595 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5596 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5597 break;
5598
67a4f2b7
AO		 5599 case BFD_RELOC_386_TLS_DESC_CALL:
5600 case BFD_RELOC_X86_64_TLSDESC_CALL:
5601 value = 0; /* Fully resolved at runtime. No addend. */
5602 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5603 fixP->fx_done = 0;
5604 return;
5605
00f7efb6
JJ		 5606 case BFD_RELOC_386_GOT32:
5607 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5608 value = 0; /* Fully resolved at runtime. No addend. */
5609 break;
47926f60
KH		 5610
5611 case BFD_RELOC_VTABLE_INHERIT:
5612 case BFD_RELOC_VTABLE_ENTRY:
5613 fixP->fx_done = 0;
94f592af 5614 return;
47926f60
KH		 5615
5616 default:
5617 break;
5618 }
5619#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5620 *valP = value;
f86103b7 5621#endif /* !defined (TE_Mach) */
3e73aa7c 5622
3e73aa7c 5623 /* Are we finished with this relocation now? */
c6682705 5624 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5625 fixP->fx_done = 1;
5626 else if (use_rela_relocations)
5627 {
5628 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5629 /* Remember value for tc_gen_reloc. */
5630 fixP->fx_addnumber = value;
3e73aa7c
JH		 5631 value = 0;
5632 }
f86103b7 5633
94f592af 5634 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5635}
252b5132 5636\f
252b5132
RH		 5637#define MAX_LITTLENUMS 6
5638
47926f60
KH		 5639/* Turn the string pointed to by litP into a floating point constant
5640 of type TYPE, and emit the appropriate bytes. The number of
5641 LITTLENUMS emitted is stored in *SIZEP. An error message is
5642 returned, or NULL on OK. */
5643
252b5132
RH		 5644char *
5645md_atof (type, litP, sizeP)
2ab9b79e 5646 int type;
252b5132
RH		 5647 char *litP;
5648 int *sizeP;
5649{
5650 int prec;
5651 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5652 LITTLENUM_TYPE *wordP;
5653 char *t;
5654
5655 switch (type)
5656 {
5657 case 'f':
5658 case 'F':
5659 prec = 2;
5660 break;
5661
5662 case 'd':
5663 case 'D':
5664 prec = 4;
5665 break;
5666
5667 case 'x':
5668 case 'X':
5669 prec = 5;
5670 break;
5671
5672 default:
5673 *sizeP = 0;
5674 return _("Bad call to md_atof ()");
5675 }
5676 t = atof_ieee (input_line_pointer, type, words);
5677 if (t)
5678 input_line_pointer = t;
5679
5680 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5681 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5682 the bigendian 386. */
5683 for (wordP = words + prec - 1; prec--;)
5684 {
5685 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5686 litP += sizeof (LITTLENUM_TYPE);
5687 }
5688 return 0;
5689}
5690\f
2d545b82 5691static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5692
252b5132
RH		 5693static char *
5694output_invalid (c)
5695 int c;
5696{
3882b010 5697 if (ISPRINT (c))
f9f21a03
L		 5698 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5699 "'%c'", c);
252b5132 5700 else
f9f21a03 5701 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5702 "(0x%x)", (unsigned char) c);
252b5132
RH		 5703 return output_invalid_buf;
5704}
5705
af6bdddf 5706/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5707
5708static const reg_entry *
4d1bb795 5709parse_real_register (char *reg_string, char **end_op)
252b5132 5710{
af6bdddf
AM		 5711 char *s = reg_string;
5712 char *p;
252b5132
RH		 5713 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5714 const reg_entry *r;
5715
5716 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5717 if (*s == REGISTER_PREFIX)
5718 ++s;
5719
5720 if (is_space_char (*s))
5721 ++s;
5722
5723 p = reg_name_given;
af6bdddf 5724 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5725 {
5726 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5727 return (const reg_entry *) NULL;
5728 s++;
252b5132
RH		 5729 }
5730
6588847e
DN		 5731 /* For naked regs, make sure that we are not dealing with an identifier.
5732 This prevents confusing an identifier like `eax_var' with register
5733 `eax'. */
5734 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5735 return (const reg_entry *) NULL;
5736
af6bdddf 5737 *end_op = s;
252b5132
RH		 5738
5739 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5740
5f47d35b 5741 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5742 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5743 {
5f47d35b
AM		 5744 if (is_space_char (*s))
5745 ++s;
5746 if (*s == '(')
5747 {
af6bdddf 5748 ++s;
5f47d35b
AM		 5749 if (is_space_char (*s))
5750 ++s;
5751 if (*s >= '0' && *s <= '7')
5752 {
5753 r = &i386_float_regtab[*s - '0'];
af6bdddf 5754 ++s;
5f47d35b
AM		 5755 if (is_space_char (*s))
5756 ++s;
5757 if (*s == ')')
5758 {
5759 *end_op = s + 1;
5760 return r;
5761 }
5f47d35b 5762 }
47926f60 5763 /* We have "%st(" then garbage. */
5f47d35b
AM		 5764 return (const reg_entry *) NULL;
5765 }
5766 }
5767
1ae00879 5768 if (r != NULL
20f0a1fc 5769 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5770 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5771 && flag_code != CODE_64BIT)
20f0a1fc 5772 return (const reg_entry *) NULL;
1ae00879 5773
252b5132
RH		 5774 return r;
5775}
4d1bb795
JB		 5776
5777/* REG_STRING starts *before* REGISTER_PREFIX. */
5778
5779static const reg_entry *
5780parse_register (char *reg_string, char **end_op)
5781{
5782 const reg_entry *r;
5783
5784 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5785 r = parse_real_register (reg_string, end_op);
5786 else
5787 r = NULL;
5788 if (!r)
5789 {
5790 char *save = input_line_pointer;
5791 char c;
5792 symbolS *symbolP;
5793
5794 input_line_pointer = reg_string;
5795 c = get_symbol_end ();
5796 symbolP = symbol_find (reg_string);
5797 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5798 {
5799 const expressionS *e = symbol_get_value_expression (symbolP);
5800
5801 know (e->X_op == O_register);
5802 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5803 r = i386_regtab + e->X_add_number;
5804 *end_op = input_line_pointer;
5805 }
5806 *input_line_pointer = c;
5807 input_line_pointer = save;
5808 }
5809 return r;
5810}
5811
5812int
5813i386_parse_name (char *name, expressionS *e, char *nextcharP)
5814{
5815 const reg_entry *r;
5816 char *end = input_line_pointer;
5817
5818 *end = *nextcharP;
5819 r = parse_register (name, &input_line_pointer);
5820 if (r && end <= input_line_pointer)
5821 {
5822 *nextcharP = *input_line_pointer;
5823 *input_line_pointer = 0;
5824 e->X_op = O_register;
5825 e->X_add_number = r - i386_regtab;
5826 return 1;
5827 }
5828 input_line_pointer = end;
5829 *end = 0;
5830 return 0;
5831}
5832
5833void
5834md_operand (expressionS *e)
5835{
5836 if (*input_line_pointer == REGISTER_PREFIX)
5837 {
5838 char *end;
5839 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5840
5841 if (r)
5842 {
5843 e->X_op = O_register;
5844 e->X_add_number = r - i386_regtab;
5845 input_line_pointer = end;
5846 }
5847 }
5848}
5849
252b5132 5850\f
4cc782b5 5851#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5852const char *md_shortopts = "kVQ:sqn";
252b5132 5853#else
12b55ccc 5854const char *md_shortopts = "qn";
252b5132 5855#endif
6e0b89ee 5856
3e73aa7c 5857#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5858#define OPTION_64 (OPTION_MD_BASE + 1)
5859#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 5860#define OPTION_MARCH (OPTION_MD_BASE + 3)
5861#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 5862
99ad8390
NC		 5863struct option md_longopts[] =
5864{
3e73aa7c 5865 {"32", no_argument, NULL, OPTION_32},
99ad8390 5866#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 5867 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5868#endif
b3b91714 5869 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 5870 {"march", required_argument, NULL, OPTION_MARCH},
5871 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 5872 {NULL, no_argument, NULL, 0}
5873};
5874size_t md_longopts_size = sizeof (md_longopts);
5875
5876int
9103f4f4 5877md_parse_option (int c, char *arg)
252b5132 5878{
9103f4f4
L		 5879 unsigned int i;
5880
252b5132
RH		 5881 switch (c)
5882 {
12b55ccc
L		 5883 case 'n':
5884 optimize_align_code = 0;
5885 break;
5886
a38cf1db
AM		 5887 case 'q':
5888 quiet_warnings = 1;
252b5132
RH		 5889 break;
5890
5891#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5892 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5893 should be emitted or not. FIXME: Not implemented. */
5894 case 'Q':
252b5132
RH		 5895 break;
5896
5897 /* -V: SVR4 argument to print version ID. */
5898 case 'V':
5899 print_version_id ();
5900 break;
5901
a38cf1db
AM		 5902 /* -k: Ignore for FreeBSD compatibility. */
5903 case 'k':
252b5132 5904 break;
4cc782b5
ILT		 5905
5906 case 's':
5907 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5908 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5909 break;
99ad8390
NC		 5910#endif
5911#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 5912 case OPTION_64:
5913 {
5914 const char **list, **l;
5915
3e73aa7c
JH		 5916 list = bfd_target_list ();
5917 for (l = list; *l != NULL; l++)
8620418b 5918 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 5919 || strcmp (*l, "coff-x86-64") == 0
5920 || strcmp (*l, "pe-x86-64") == 0
5921 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 5922 {
5923 default_arch = "x86_64";
5924 break;
5925 }
3e73aa7c 5926 if (*l == NULL)
6e0b89ee 5927 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5928 free (list);
5929 }
5930 break;
5931#endif
252b5132 5932
6e0b89ee
AM		 5933 case OPTION_32:
5934 default_arch = "i386";
5935 break;
5936
b3b91714
AM		 5937 case OPTION_DIVIDE:
5938#ifdef SVR4_COMMENT_CHARS
5939 {
5940 char *n, *t;
5941 const char *s;
5942
5943 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5944 t = n;
5945 for (s = i386_comment_chars; *s != '\0'; s++)
5946 if (*s != '/')
5947 *t++ = *s;
5948 *t = '\0';
5949 i386_comment_chars = n;
5950 }
5951#endif
5952 break;
5953
9103f4f4
L		 5954 case OPTION_MARCH:
5955 if (*arg == '.')
5956 as_fatal (_("Invalid -march= option: `%s'"), arg);
5957 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5958 {
5959 if (strcmp (arg, cpu_arch [i].name) == 0)
5960 {
ccc9c027 5961 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 5962 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 5963 if (!cpu_arch_tune_set)
5964 {
5965 cpu_arch_tune = cpu_arch_isa;
5966 cpu_arch_tune_flags = cpu_arch_isa_flags;
5967 }
9103f4f4
L		 5968 break;
5969 }
5970 }
5971 if (i >= ARRAY_SIZE (cpu_arch))
5972 as_fatal (_("Invalid -march= option: `%s'"), arg);
5973 break;
5974
5975 case OPTION_MTUNE:
5976 if (*arg == '.')
5977 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5978 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5979 {
5980 if (strcmp (arg, cpu_arch [i].name) == 0)
5981 {
ccc9c027 5982 cpu_arch_tune_set = 1;
9103f4f4
L		 5983 cpu_arch_tune = cpu_arch [i].type;
5984 cpu_arch_tune_flags = cpu_arch[i].flags;
5985 break;
5986 }
5987 }
5988 if (i >= ARRAY_SIZE (cpu_arch))
5989 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5990 break;
5991
252b5132
RH		 5992 default:
5993 return 0;
5994 }
5995 return 1;
5996}
5997
5998void
5999md_show_usage (stream)
6000 FILE *stream;
6001{
4cc782b5
ILT		 6002#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6003 fprintf (stream, _("\
a38cf1db
AM		 6004 -Q ignored\n\
6005 -V print assembler version number\n\
b3b91714
AM		 6006 -k ignored\n"));
6007#endif
6008 fprintf (stream, _("\
12b55ccc 6009 -n Do not optimize code alignment\n\
b3b91714
AM		 6010 -q quieten some warnings\n"));
6011#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6012 fprintf (stream, _("\
a38cf1db 6013 -s ignored\n"));
b3b91714
AM		 6014#endif
6015#ifdef SVR4_COMMENT_CHARS
6016 fprintf (stream, _("\
6017 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 6018#else
6019 fprintf (stream, _("\
b3b91714 6020 --divide ignored\n"));
4cc782b5 6021#endif
9103f4f4
L		 6022 fprintf (stream, _("\
6023 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6024 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
ef05d495 6025 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 6026
252b5132
RH		 6027}
6028
99ad8390
NC		 6029#if defined(TE_PEP)
6030const char *
6031x86_64_target_format (void)
6032{
6033 if (strcmp (default_arch, "x86_64") == 0)
6034 {
6035 set_code_flag (CODE_64BIT);
6036 return COFF_TARGET_FORMAT;
6037 }
6038 else if (strcmp (default_arch, "i386") == 0)
6039 {
6040 set_code_flag (CODE_32BIT);
6041 return "coff-i386";
6042 }
6043
6044 as_fatal (_("Unknown architecture"));
6045 return NULL;
6046}
6047#endif
6048
3e73aa7c
JH		 6049#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6050 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 6051
6052/* Pick the target format to use. */
6053
47926f60 6054const char *
252b5132
RH		 6055i386_target_format ()
6056{
3e73aa7c 6057 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 6058 {
6059 set_code_flag (CODE_64BIT);
6060 if (cpu_arch_isa_flags == 0)
d32cad65 6061 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
9103f4f4
L		 6062 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6063 |CpuSSE|CpuSSE2;
ccc9c027 6064 if (cpu_arch_tune_flags == 0)
d32cad65 6065 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
ccc9c027
L		 6066 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6067 |CpuSSE|CpuSSE2;
9103f4f4 6068 }
3e73aa7c 6069 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 6070 {
6071 set_code_flag (CODE_32BIT);
6072 if (cpu_arch_isa_flags == 0)
d32cad65 6073 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
ccc9c027 6074 if (cpu_arch_tune_flags == 0)
d32cad65 6075 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
9103f4f4 6076 }
3e73aa7c
JH		 6077 else
6078 as_fatal (_("Unknown architecture"));
252b5132
RH		 6079 switch (OUTPUT_FLAVOR)
6080 {
4c63da97
AM		 6081#ifdef OBJ_MAYBE_AOUT
6082 case bfd_target_aout_flavour:
47926f60 6083 return AOUT_TARGET_FORMAT;
4c63da97
AM		 6084#endif
6085#ifdef OBJ_MAYBE_COFF
252b5132
RH		 6086 case bfd_target_coff_flavour:
6087 return "coff-i386";
4c63da97 6088#endif
3e73aa7c 6089#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 6090 case bfd_target_elf_flavour:
3e73aa7c 6091 {
e5cb08ac 6092 if (flag_code == CODE_64BIT)
4fa24527
JB		 6093 {
6094 object_64bit = 1;
6095 use_rela_relocations = 1;
6096 }
9d7cbccd 6097 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6098 }
4c63da97 6099#endif
252b5132
RH		 6100 default:
6101 abort ();
6102 return NULL;
6103 }
6104}
6105
47926f60 6106#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 6107
6108#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6109void i386_elf_emit_arch_note ()
6110{
718ddfc0 6111 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 6112 {
6113 char *p;
6114 asection *seg = now_seg;
6115 subsegT subseg = now_subseg;
6116 Elf_Internal_Note i_note;
6117 Elf_External_Note e_note;
6118 asection *note_secp;
6119 int len;
6120
6121 /* Create the .note section. */
6122 note_secp = subseg_new (".note", 0);
6123 bfd_set_section_flags (stdoutput,
6124 note_secp,
6125 SEC_HAS_CONTENTS | SEC_READONLY);
6126
6127 /* Process the arch string. */
6128 len = strlen (cpu_arch_name);
6129
6130 i_note.namesz = len + 1;
6131 i_note.descsz = 0;
6132 i_note.type = NT_ARCH;
6133 p = frag_more (sizeof (e_note.namesz));
6134 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6135 p = frag_more (sizeof (e_note.descsz));
6136 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6137 p = frag_more (sizeof (e_note.type));
6138 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6139 p = frag_more (len + 1);
6140 strcpy (p, cpu_arch_name);
6141
6142 frag_align (2, 0, 0);
6143
6144 subseg_set (seg, subseg);
6145 }
6146}
6147#endif
252b5132 6148\f
252b5132
RH		 6149symbolS *
6150md_undefined_symbol (name)
6151 char *name;
6152{
18dc2407
ILT		 6153 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6154 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6155 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6156 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6157 {
6158 if (!GOT_symbol)
6159 {
6160 if (symbol_find (name))
6161 as_bad (_("GOT already in symbol table"));
6162 GOT_symbol = symbol_new (name, undefined_section,
6163 (valueT) 0, &zero_address_frag);
6164 };
6165 return GOT_symbol;
6166 }
252b5132
RH		 6167 return 0;
6168}
6169
6170/* Round up a section size to the appropriate boundary. */
47926f60 6171
252b5132
RH		 6172valueT
6173md_section_align (segment, size)
ab9da554 6174 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6175 valueT size;
6176{
4c63da97
AM		 6177#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6178 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6179 {
6180 /* For a.out, force the section size to be aligned. If we don't do
6181 this, BFD will align it for us, but it will not write out the
6182 final bytes of the section. This may be a bug in BFD, but it is
6183 easier to fix it here since that is how the other a.out targets
6184 work. */
6185 int align;
6186
6187 align = bfd_get_section_alignment (stdoutput, segment);
6188 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6189 }
252b5132
RH		 6190#endif
6191
6192 return size;
6193}
6194
6195/* On the i386, PC-relative offsets are relative to the start of the
6196 next instruction. That is, the address of the offset, plus its
6197 size, since the offset is always the last part of the insn. */
6198
6199long
6200md_pcrel_from (fixP)
6201 fixS *fixP;
6202{
6203 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6204}
6205
6206#ifndef I386COFF
6207
6208static void
6209s_bss (ignore)
ab9da554 6210 int ignore ATTRIBUTE_UNUSED;
252b5132 6211{
29b0f896 6212 int temp;
252b5132 6213
8a75718c
JB		 6214#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6215 if (IS_ELF)
6216 obj_elf_section_change_hook ();
6217#endif
252b5132
RH		 6218 temp = get_absolute_expression ();
6219 subseg_set (bss_section, (subsegT) temp);
6220 demand_empty_rest_of_line ();
6221}
6222
6223#endif
6224
252b5132
RH		 6225void
6226i386_validate_fix (fixp)
6227 fixS *fixp;
6228{
6229 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6230 {
23df1078
JH		 6231 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6232 {
4fa24527 6233 if (!object_64bit)
23df1078
JH		 6234 abort ();
6235 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6236 }
6237 else
6238 {
4fa24527 6239 if (!object_64bit)
d6ab8113
JB		 6240 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6241 else
6242 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6243 }
252b5132
RH		 6244 fixp->fx_subsy = 0;
6245 }
6246}
6247
252b5132
RH		 6248arelent *
6249tc_gen_reloc (section, fixp)
ab9da554 6250 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6251 fixS *fixp;
6252{
6253 arelent *rel;
6254 bfd_reloc_code_real_type code;
6255
6256 switch (fixp->fx_r_type)
6257 {
3e73aa7c
JH		 6258 case BFD_RELOC_X86_64_PLT32:
6259 case BFD_RELOC_X86_64_GOT32:
6260 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6261 case BFD_RELOC_386_PLT32:
6262 case BFD_RELOC_386_GOT32:
6263 case BFD_RELOC_386_GOTOFF:
6264 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 6265 case BFD_RELOC_386_TLS_GD:
6266 case BFD_RELOC_386_TLS_LDM:
6267 case BFD_RELOC_386_TLS_LDO_32:
6268 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6269 case BFD_RELOC_386_TLS_IE:
6270 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 6271 case BFD_RELOC_386_TLS_LE_32:
6272 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 6273 case BFD_RELOC_386_TLS_GOTDESC:
6274 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 6275 case BFD_RELOC_X86_64_TLSGD:
6276 case BFD_RELOC_X86_64_TLSLD:
6277 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6278 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 6279 case BFD_RELOC_X86_64_GOTTPOFF:
6280 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 6281 case BFD_RELOC_X86_64_TPOFF64:
6282 case BFD_RELOC_X86_64_GOTOFF64:
6283 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 6284 case BFD_RELOC_X86_64_GOT64:
6285 case BFD_RELOC_X86_64_GOTPCREL64:
6286 case BFD_RELOC_X86_64_GOTPC64:
6287 case BFD_RELOC_X86_64_GOTPLT64:
6288 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 6289 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6290 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 6291 case BFD_RELOC_RVA:
6292 case BFD_RELOC_VTABLE_ENTRY:
6293 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 6294#ifdef TE_PE
6295 case BFD_RELOC_32_SECREL:
6296#endif
252b5132
RH		 6297 code = fixp->fx_r_type;
6298 break;
dbbaec26
L		 6299 case BFD_RELOC_X86_64_32S:
6300 if (!fixp->fx_pcrel)
6301 {
6302 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6303 code = fixp->fx_r_type;
6304 break;
6305 }
252b5132 6306 default:
93382f6d 6307 if (fixp->fx_pcrel)
252b5132 6308 {
93382f6d
AM		 6309 switch (fixp->fx_size)
6310 {
6311 default:
b091f402
AM		 6312 as_bad_where (fixp->fx_file, fixp->fx_line,
6313 _("can not do %d byte pc-relative relocation"),
6314 fixp->fx_size);
93382f6d
AM		 6315 code = BFD_RELOC_32_PCREL;
6316 break;
6317 case 1: code = BFD_RELOC_8_PCREL; break;
6318 case 2: code = BFD_RELOC_16_PCREL; break;
6319 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 6320#ifdef BFD64
6321 case 8: code = BFD_RELOC_64_PCREL; break;
6322#endif
93382f6d
AM		 6323 }
6324 }
6325 else
6326 {
6327 switch (fixp->fx_size)
6328 {
6329 default:
b091f402
AM		 6330 as_bad_where (fixp->fx_file, fixp->fx_line,
6331 _("can not do %d byte relocation"),
6332 fixp->fx_size);
93382f6d
AM		 6333 code = BFD_RELOC_32;
6334 break;
6335 case 1: code = BFD_RELOC_8; break;
6336 case 2: code = BFD_RELOC_16; break;
6337 case 4: code = BFD_RELOC_32; break;
937149dd 6338#ifdef BFD64
3e73aa7c 6339 case 8: code = BFD_RELOC_64; break;
937149dd 6340#endif
93382f6d 6341 }
252b5132
RH		 6342 }
6343 break;
6344 }
252b5132 6345
d182319b
JB		 6346 if ((code == BFD_RELOC_32
6347 || code == BFD_RELOC_32_PCREL
6348 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 6349 && GOT_symbol
6350 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 6351 {
4fa24527 6352 if (!object_64bit)
d6ab8113
JB		 6353 code = BFD_RELOC_386_GOTPC;
6354 else
6355 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 6356 }
7b81dfbb
AJ		 6357 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6358 && GOT_symbol
6359 && fixp->fx_addsy == GOT_symbol)
6360 {
6361 code = BFD_RELOC_X86_64_GOTPC64;
6362 }
252b5132
RH		 6363
6364 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 6365 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6366 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 6367
6368 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 6369
3e73aa7c
JH		 6370 if (!use_rela_relocations)
6371 {
6372 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6373 vtable entry to be used in the relocation's section offset. */
6374 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6375 rel->address = fixp->fx_offset;
252b5132 6376
c6682705 6377 rel->addend = 0;
3e73aa7c
JH		 6378 }
6379 /* Use the rela in 64bit mode. */
252b5132 6380 else
3e73aa7c 6381 {
062cd5e7
AS		 6382 if (!fixp->fx_pcrel)
6383 rel->addend = fixp->fx_offset;
6384 else
6385 switch (code)
6386 {
6387 case BFD_RELOC_X86_64_PLT32:
6388 case BFD_RELOC_X86_64_GOT32:
6389 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 6390 case BFD_RELOC_X86_64_TLSGD:
6391 case BFD_RELOC_X86_64_TLSLD:
6392 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 6393 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6394 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 6395 rel->addend = fixp->fx_offset - fixp->fx_size;
6396 break;
6397 default:
6398 rel->addend = (section->vma
6399 - fixp->fx_size
6400 + fixp->fx_addnumber
6401 + md_pcrel_from (fixp));
6402 break;
6403 }
3e73aa7c
JH		 6404 }
6405
252b5132
RH		 6406 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6407 if (rel->howto == NULL)
6408 {
6409 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 6410 _("cannot represent relocation type %s"),
252b5132
RH		 6411 bfd_get_reloc_code_name (code));
6412 /* Set howto to a garbage value so that we can keep going. */
6413 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6414 assert (rel->howto != NULL);
6415 }
6416
6417 return rel;
6418}
6419
64a0c779
DN		 6420\f
6421/* Parse operands using Intel syntax. This implements a recursive descent
6422 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6423 Programmer's Guide.
6424
6425 FIXME: We do not recognize the full operand grammar defined in the MASM
6426 documentation. In particular, all the structure/union and
6427 high-level macro operands are missing.
6428
6429 Uppercase words are terminals, lower case words are non-terminals.
6430 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6431 bars '|' denote choices. Most grammar productions are implemented in
6432 functions called 'intel_<production>'.
6433
6434 Initial production is 'expr'.
6435
9306ca4a 6436 addOp + | -
64a0c779
DN		 6437
6438 alpha [a-zA-Z]
6439
9306ca4a
JB		 6440 binOp & | AND | \| | OR | ^ | XOR
6441
64a0c779
DN		 6442 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6443
6444 constant digits [[ radixOverride ]]
6445
9306ca4a 6446 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 6447
6448 digits decdigit
b77a7acd
AJ		 6449 | digits decdigit
6450 | digits hexdigit
64a0c779
DN		 6451
6452 decdigit [0-9]
6453
9306ca4a
JB		 6454 e04 e04 addOp e05
6455 | e05
6456
6457 e05 e05 binOp e06
b77a7acd 6458 | e06
64a0c779
DN		 6459
6460 e06 e06 mulOp e09
b77a7acd 6461 | e09
64a0c779
DN		 6462
6463 e09 OFFSET e10
a724f0f4
JB		 6464 | SHORT e10
6465 | + e10
6466 | - e10
9306ca4a
JB		 6467 | ~ e10
6468 | NOT e10
64a0c779
DN		 6469 | e09 PTR e10
6470 | e09 : e10
6471 | e10
6472
6473 e10 e10 [ expr ]
b77a7acd 6474 | e11
64a0c779
DN		 6475
6476 e11 ( expr )
b77a7acd 6477 | [ expr ]
64a0c779
DN		 6478 | constant
6479 | dataType
6480 | id
6481 | $
6482 | register
6483
a724f0f4 6484 => expr expr cmpOp e04
9306ca4a 6485 | e04
64a0c779
DN		 6486
6487 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 6488 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 6489
6490 hexdigit a | b | c | d | e | f
b77a7acd 6491 | A | B | C | D | E | F
64a0c779
DN		 6492
6493 id alpha
b77a7acd 6494 | id alpha
64a0c779
DN		 6495 | id decdigit
6496
9306ca4a 6497 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 6498
6499 quote " | '
6500
6501 register specialRegister
b77a7acd 6502 | gpRegister
64a0c779
DN		 6503 | byteRegister
6504
6505 segmentRegister CS | DS | ES | FS | GS | SS
6506
9306ca4a 6507 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 6508 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 6509 | TR3 | TR4 | TR5 | TR6 | TR7
6510
64a0c779
DN		 6511 We simplify the grammar in obvious places (e.g., register parsing is
6512 done by calling parse_register) and eliminate immediate left recursion
6513 to implement a recursive-descent parser.
6514
a724f0f4
JB		 6515 expr e04 expr'
6516
6517 expr' cmpOp e04 expr'
6518 | Empty
9306ca4a
JB		 6519
6520 e04 e05 e04'
6521
6522 e04' addOp e05 e04'
6523 | Empty
64a0c779
DN		 6524
6525 e05 e06 e05'
6526
9306ca4a 6527 e05' binOp e06 e05'
b77a7acd 6528 | Empty
64a0c779
DN		 6529
6530 e06 e09 e06'
6531
6532 e06' mulOp e09 e06'
b77a7acd 6533 | Empty
64a0c779
DN		 6534
6535 e09 OFFSET e10 e09'
a724f0f4
JB		 6536 | SHORT e10'
6537 | + e10'
6538 | - e10'
6539 | ~ e10'
6540 | NOT e10'
b77a7acd 6541 | e10 e09'
64a0c779
DN		 6542
6543 e09' PTR e10 e09'
b77a7acd 6544 | : e10 e09'
64a0c779
DN		 6545 | Empty
6546
6547 e10 e11 e10'
6548
6549 e10' [ expr ] e10'
b77a7acd 6550 | Empty
64a0c779
DN		 6551
6552 e11 ( expr )
b77a7acd 6553 | [ expr ]
64a0c779
DN		 6554 | BYTE
6555 | WORD
6556 | DWORD
9306ca4a 6557 | FWORD
64a0c779 6558 | QWORD
9306ca4a
JB		 6559 | TBYTE
6560 | OWORD
6561 | XMMWORD
64a0c779
DN		 6562 | .
6563 | $
6564 | register
6565 | id
6566 | constant */
6567
6568/* Parsing structure for the intel syntax parser. Used to implement the
6569 semantic actions for the operand grammar. */
6570struct intel_parser_s
6571 {
6572 char *op_string; /* The string being parsed. */
6573 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6574 int op_modifier; /* Operand modifier. */
64a0c779 6575 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 6576 int in_offset; /* >=1 if parsing operand of offset. */
6577 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6578 const reg_entry *reg; /* Last register reference found. */
6579 char *disp; /* Displacement string being built. */
a724f0f4 6580 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6581 };
6582
6583static struct intel_parser_s intel_parser;
6584
6585/* Token structure for parsing intel syntax. */
6586struct intel_token
6587 {
6588 int code; /* Token code. */
6589 const reg_entry *reg; /* Register entry for register tokens. */
6590 char *str; /* String representation. */
6591 };
6592
6593static struct intel_token cur_token, prev_token;
6594
50705ef4
AM		 6595/* Token codes for the intel parser. Since T_SHORT is already used
6596 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6597#define T_NIL -1
6598#define T_CONST 1
6599#define T_REG 2
6600#define T_BYTE 3
6601#define T_WORD 4
9306ca4a
JB		 6602#define T_DWORD 5
6603#define T_FWORD 6
6604#define T_QWORD 7
6605#define T_TBYTE 8
6606#define T_XMMWORD 9
50705ef4 6607#undef T_SHORT
9306ca4a
JB		 6608#define T_SHORT 10
6609#define T_OFFSET 11
6610#define T_PTR 12
6611#define T_ID 13
6612#define T_SHL 14
6613#define T_SHR 15
64a0c779
DN		 6614
6615/* Prototypes for intel parser functions. */
6616static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 6617static void intel_get_token PARAMS ((void));
6618static void intel_putback_token PARAMS ((void));
6619static int intel_expr PARAMS ((void));
9306ca4a 6620static int intel_e04 PARAMS ((void));
cce0cbdc 6621static int intel_e05 PARAMS ((void));
cce0cbdc 6622static int intel_e06 PARAMS ((void));
cce0cbdc 6623static int intel_e09 PARAMS ((void));
a724f0f4 6624static int intel_bracket_expr PARAMS ((void));
cce0cbdc 6625static int intel_e10 PARAMS ((void));
cce0cbdc 6626static int intel_e11 PARAMS ((void));
64a0c779 6627
64a0c779
DN		 6628static int
6629i386_intel_operand (operand_string, got_a_float)
6630 char *operand_string;
6631 int got_a_float;
6632{
6633 int ret;
6634 char *p;
6635
a724f0f4
JB		 6636 p = intel_parser.op_string = xstrdup (operand_string);
6637 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6638
6639 for (;;)
64a0c779 6640 {
a724f0f4
JB		 6641 /* Initialize token holders. */
6642 cur_token.code = prev_token.code = T_NIL;
6643 cur_token.reg = prev_token.reg = NULL;
6644 cur_token.str = prev_token.str = NULL;
6645
6646 /* Initialize parser structure. */
6647 intel_parser.got_a_float = got_a_float;
6648 intel_parser.op_modifier = 0;
6649 intel_parser.is_mem = 0;
6650 intel_parser.in_offset = 0;
6651 intel_parser.in_bracket = 0;
6652 intel_parser.reg = NULL;
6653 intel_parser.disp[0] = '\0';
6654 intel_parser.next_operand = NULL;
6655
6656 /* Read the first token and start the parser. */
6657 intel_get_token ();
6658 ret = intel_expr ();
6659
6660 if (!ret)
6661 break;
6662
9306ca4a
JB		 6663 if (cur_token.code != T_NIL)
6664 {
6665 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6666 current_templates->start->name, cur_token.str);
6667 ret = 0;
6668 }
64a0c779
DN		 6669 /* If we found a memory reference, hand it over to i386_displacement
6670 to fill in the rest of the operand fields. */
9306ca4a 6671 else if (intel_parser.is_mem)
64a0c779
DN		 6672 {
6673 if ((i.mem_operands == 1
6674 && (current_templates->start->opcode_modifier & IsString) == 0)
6675 || i.mem_operands == 2)
6676 {
6677 as_bad (_("too many memory references for '%s'"),
6678 current_templates->start->name);
6679 ret = 0;
6680 }
6681 else
6682 {
6683 char *s = intel_parser.disp;
6684 i.mem_operands++;
6685
a724f0f4
JB		 6686 if (!quiet_warnings && intel_parser.is_mem < 0)
6687 /* See the comments in intel_bracket_expr. */
6688 as_warn (_("Treating `%s' as memory reference"), operand_string);
6689
64a0c779
DN		 6690 /* Add the displacement expression. */
6691 if (*s != '\0')
a4622f40
AM		 6692 ret = i386_displacement (s, s + strlen (s));
6693 if (ret)
a724f0f4
JB		 6694 {
6695 /* Swap base and index in 16-bit memory operands like
6696 [si+bx]. Since i386_index_check is also used in AT&T
6697 mode we have to do that here. */
6698 if (i.base_reg
6699 && i.index_reg
6700 && (i.base_reg->reg_type & Reg16)
6701 && (i.index_reg->reg_type & Reg16)
6702 && i.base_reg->reg_num >= 6
6703 && i.index_reg->reg_num < 6)
6704 {
6705 const reg_entry *base = i.index_reg;
6706
6707 i.index_reg = i.base_reg;
6708 i.base_reg = base;
6709 }
6710 ret = i386_index_check (operand_string);
6711 }
64a0c779
DN		 6712 }
6713 }
6714
6715 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6716 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6717 || intel_parser.reg == NULL)
6718 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6719
6720 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6721 ret = 0;
6722 if (!ret || !intel_parser.next_operand)
6723 break;
6724 intel_parser.op_string = intel_parser.next_operand;
6725 this_operand = i.operands++;
64a0c779
DN		 6726 }
6727
6728 free (p);
6729 free (intel_parser.disp);
6730
6731 return ret;
6732}
6733
a724f0f4
JB		 6734#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6735
6736/* expr e04 expr'
6737
6738 expr' cmpOp e04 expr'
6739 | Empty */
64a0c779
DN		 6740static int
6741intel_expr ()
6742{
a724f0f4
JB		 6743 /* XXX Implement the comparison operators. */
6744 return intel_e04 ();
9306ca4a
JB		 6745}
6746
a724f0f4 6747/* e04 e05 e04'
9306ca4a 6748
a724f0f4 6749 e04' addOp e05 e04'
9306ca4a
JB		 6750 | Empty */
6751static int
6752intel_e04 ()
6753{
a724f0f4 6754 int nregs = -1;
9306ca4a 6755
a724f0f4 6756 for (;;)
9306ca4a 6757 {
a724f0f4
JB		 6758 if (!intel_e05())
6759 return 0;
9306ca4a 6760
a724f0f4
JB		 6761 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6762 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6763
a724f0f4
JB		 6764 if (cur_token.code == '+')
6765 nregs = -1;
6766 else if (cur_token.code == '-')
6767 nregs = NUM_ADDRESS_REGS;
6768 else
6769 return 1;
64a0c779 6770
a724f0f4
JB		 6771 strcat (intel_parser.disp, cur_token.str);
6772 intel_match_token (cur_token.code);
6773 }
64a0c779
DN		 6774}
6775
64a0c779
DN		 6776/* e05 e06 e05'
6777
9306ca4a 6778 e05' binOp e06 e05'
64a0c779
DN		 6779 | Empty */
6780static int
6781intel_e05 ()
6782{
a724f0f4 6783 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6784
a724f0f4 6785 for (;;)
64a0c779 6786 {
a724f0f4
JB		 6787 if (!intel_e06())
6788 return 0;
6789
6790 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6791 {
6792 char str[2];
6793
6794 str[0] = cur_token.code;
6795 str[1] = 0;
6796 strcat (intel_parser.disp, str);
6797 }
6798 else
6799 break;
9306ca4a 6800
64a0c779
DN		 6801 intel_match_token (cur_token.code);
6802
a724f0f4
JB		 6803 if (nregs < 0)
6804 nregs = ~nregs;
64a0c779 6805 }
a724f0f4
JB		 6806 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6807 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6808 return 1;
4a1805b1 6809}
64a0c779
DN		 6810
6811/* e06 e09 e06'
6812
6813 e06' mulOp e09 e06'
b77a7acd 6814 | Empty */
64a0c779
DN		 6815static int
6816intel_e06 ()
6817{
a724f0f4 6818 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6819
a724f0f4 6820 for (;;)
64a0c779 6821 {
a724f0f4
JB		 6822 if (!intel_e09())
6823 return 0;
9306ca4a 6824
a724f0f4
JB		 6825 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6826 {
6827 char str[2];
9306ca4a 6828
a724f0f4
JB		 6829 str[0] = cur_token.code;
6830 str[1] = 0;
6831 strcat (intel_parser.disp, str);
6832 }
6833 else if (cur_token.code == T_SHL)
6834 strcat (intel_parser.disp, "<<");
6835 else if (cur_token.code == T_SHR)
6836 strcat (intel_parser.disp, ">>");
6837 else
6838 break;
9306ca4a 6839
64e74474 6840 intel_match_token (cur_token.code);
64a0c779 6841
a724f0f4
JB		 6842 if (nregs < 0)
6843 nregs = ~nregs;
64a0c779 6844 }
a724f0f4
JB		 6845 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6846 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6847 return 1;
64a0c779
DN		 6848}
6849
a724f0f4
JB		 6850/* e09 OFFSET e09
6851 | SHORT e09
6852 | + e09
6853 | - e09
6854 | ~ e09
6855 | NOT e09
9306ca4a
JB		 6856 | e10 e09'
6857
64a0c779 6858 e09' PTR e10 e09'
b77a7acd 6859 | : e10 e09'
64a0c779
DN		 6860 | Empty */
6861static int
6862intel_e09 ()
6863{
a724f0f4
JB		 6864 int nregs = ~NUM_ADDRESS_REGS;
6865 int in_offset = 0;
6866
6867 for (;;)
64a0c779 6868 {
a724f0f4
JB		 6869 /* Don't consume constants here. */
6870 if (cur_token.code == '+' || cur_token.code == '-')
6871 {
6872 /* Need to look one token ahead - if the next token
6873 is a constant, the current token is its sign. */
6874 int next_code;
6875
6876 intel_match_token (cur_token.code);
6877 next_code = cur_token.code;
6878 intel_putback_token ();
6879 if (next_code == T_CONST)
6880 break;
6881 }
6882
6883 /* e09 OFFSET e09 */
6884 if (cur_token.code == T_OFFSET)
6885 {
6886 if (!in_offset++)
6887 ++intel_parser.in_offset;
6888 }
6889
6890 /* e09 SHORT e09 */
6891 else if (cur_token.code == T_SHORT)
6892 intel_parser.op_modifier |= 1 << T_SHORT;
6893
6894 /* e09 + e09 */
6895 else if (cur_token.code == '+')
6896 strcat (intel_parser.disp, "+");
6897
6898 /* e09 - e09
6899 | ~ e09
6900 | NOT e09 */
6901 else if (cur_token.code == '-' || cur_token.code == '~')
6902 {
6903 char str[2];
64a0c779 6904
a724f0f4
JB		 6905 if (nregs < 0)
6906 nregs = ~nregs;
6907 str[0] = cur_token.code;
6908 str[1] = 0;
6909 strcat (intel_parser.disp, str);
6910 }
6911
6912 /* e09 e10 e09' */
6913 else
6914 break;
6915
6916 intel_match_token (cur_token.code);
64a0c779
DN		 6917 }
6918
a724f0f4 6919 for (;;)
9306ca4a 6920 {
a724f0f4
JB		 6921 if (!intel_e10 ())
6922 return 0;
9306ca4a 6923
a724f0f4
JB		 6924 /* e09' PTR e10 e09' */
6925 if (cur_token.code == T_PTR)
6926 {
6927 char suffix;
9306ca4a 6928
a724f0f4
JB		 6929 if (prev_token.code == T_BYTE)
6930 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6931
a724f0f4
JB		 6932 else if (prev_token.code == T_WORD)
6933 {
6934 if (current_templates->start->name[0] == 'l'
6935 && current_templates->start->name[2] == 's'
6936 && current_templates->start->name[3] == 0)
6937 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6938 else if (intel_parser.got_a_float == 2) /* "fi..." */
6939 suffix = SHORT_MNEM_SUFFIX;
6940 else
6941 suffix = WORD_MNEM_SUFFIX;
6942 }
64a0c779 6943
a724f0f4
JB		 6944 else if (prev_token.code == T_DWORD)
6945 {
6946 if (current_templates->start->name[0] == 'l'
6947 && current_templates->start->name[2] == 's'
6948 && current_templates->start->name[3] == 0)
6949 suffix = WORD_MNEM_SUFFIX;
6950 else if (flag_code == CODE_16BIT
6951 && (current_templates->start->opcode_modifier
435acd52 6952 & (Jump | JumpDword)))
a724f0f4
JB		 6953 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6954 else if (intel_parser.got_a_float == 1) /* "f..." */
6955 suffix = SHORT_MNEM_SUFFIX;
6956 else
6957 suffix = LONG_MNEM_SUFFIX;
6958 }
9306ca4a 6959
a724f0f4
JB		 6960 else if (prev_token.code == T_FWORD)
6961 {
6962 if (current_templates->start->name[0] == 'l'
6963 && current_templates->start->name[2] == 's'
6964 && current_templates->start->name[3] == 0)
6965 suffix = LONG_MNEM_SUFFIX;
6966 else if (!intel_parser.got_a_float)
6967 {
6968 if (flag_code == CODE_16BIT)
6969 add_prefix (DATA_PREFIX_OPCODE);
6970 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6971 }
6972 else
6973 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6974 }
64a0c779 6975
a724f0f4
JB		 6976 else if (prev_token.code == T_QWORD)
6977 {
6978 if (intel_parser.got_a_float == 1) /* "f..." */
6979 suffix = LONG_MNEM_SUFFIX;
6980 else
6981 suffix = QWORD_MNEM_SUFFIX;
6982 }
64a0c779 6983
a724f0f4
JB		 6984 else if (prev_token.code == T_TBYTE)
6985 {
6986 if (intel_parser.got_a_float == 1)
6987 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6988 else
6989 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6990 }
9306ca4a 6991
a724f0f4 6992 else if (prev_token.code == T_XMMWORD)
9306ca4a 6993 {
a724f0f4
JB		 6994 /* XXX ignored for now, but accepted since gcc uses it */
6995 suffix = 0;
9306ca4a 6996 }
64a0c779 6997
f16b83df 6998 else
a724f0f4
JB		 6999 {
7000 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
7001 return 0;
7002 }
7003
435acd52
JB		 7004 /* Operands for jump/call using 'ptr' notation denote absolute
7005 addresses. */
7006 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7007 i.types[this_operand] |= JumpAbsolute;
7008
a724f0f4
JB		 7009 if (current_templates->start->base_opcode == 0x8d /* lea */)
7010 ;
7011 else if (!i.suffix)
7012 i.suffix = suffix;
7013 else if (i.suffix != suffix)
7014 {
7015 as_bad (_("Conflicting operand modifiers"));
7016 return 0;
7017 }
64a0c779 7018
9306ca4a
JB		 7019 }
7020
a724f0f4
JB		 7021 /* e09' : e10 e09' */
7022 else if (cur_token.code == ':')
9306ca4a 7023 {
a724f0f4
JB		 7024 if (prev_token.code != T_REG)
7025 {
7026 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7027 segment/group identifier (which we don't have), using comma
7028 as the operand separator there is even less consistent, since
7029 there all branches only have a single operand. */
7030 if (this_operand != 0
7031 || intel_parser.in_offset
7032 || intel_parser.in_bracket
7033 || (!(current_templates->start->opcode_modifier
7034 & (Jump|JumpDword|JumpInterSegment))
7035 && !(current_templates->start->operand_types[0]
7036 & JumpAbsolute)))
7037 return intel_match_token (T_NIL);
7038 /* Remember the start of the 2nd operand and terminate 1st
7039 operand here.
7040 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7041 another expression), but it gets at least the simplest case
7042 (a plain number or symbol on the left side) right. */
7043 intel_parser.next_operand = intel_parser.op_string;
7044 *--intel_parser.op_string = '\0';
7045 return intel_match_token (':');
7046 }
9306ca4a 7047 }
64a0c779 7048
a724f0f4 7049 /* e09' Empty */
64a0c779 7050 else
a724f0f4 7051 break;
64a0c779 7052
a724f0f4
JB		 7053 intel_match_token (cur_token.code);
7054
7055 }
7056
7057 if (in_offset)
7058 {
7059 --intel_parser.in_offset;
7060 if (nregs < 0)
7061 nregs = ~nregs;
7062 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 7063 {
a724f0f4 7064 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 7065 return 0;
7066 }
a724f0f4
JB		 7067 intel_parser.op_modifier |= 1 << T_OFFSET;
7068 }
9306ca4a 7069
a724f0f4
JB		 7070 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7071 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7072 return 1;
7073}
64a0c779 7074
a724f0f4
JB		 7075static int
7076intel_bracket_expr ()
7077{
7078 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7079 const char *start = intel_parser.op_string;
7080 int len;
7081
7082 if (i.op[this_operand].regs)
7083 return intel_match_token (T_NIL);
7084
7085 intel_match_token ('[');
7086
7087 /* Mark as a memory operand only if it's not already known to be an
7088 offset expression. If it's an offset expression, we need to keep
7089 the brace in. */
7090 if (!intel_parser.in_offset)
7091 {
7092 ++intel_parser.in_bracket;
435acd52
JB		 7093
7094 /* Operands for jump/call inside brackets denote absolute addresses. */
7095 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7096 i.types[this_operand] |= JumpAbsolute;
7097
a724f0f4
JB		 7098 /* Unfortunately gas always diverged from MASM in a respect that can't
7099 be easily fixed without risking to break code sequences likely to be
7100 encountered (the testsuite even check for this): MASM doesn't consider
7101 an expression inside brackets unconditionally as a memory reference.
7102 When that is e.g. a constant, an offset expression, or the sum of the
7103 two, this is still taken as a constant load. gas, however, always
7104 treated these as memory references. As a compromise, we'll try to make
7105 offset expressions inside brackets work the MASM way (since that's
7106 less likely to be found in real world code), but make constants alone
7107 continue to work the traditional gas way. In either case, issue a
7108 warning. */
7109 intel_parser.op_modifier &= ~was_offset;
64a0c779 7110 }
a724f0f4 7111 else
64e74474 7112 strcat (intel_parser.disp, "[");
a724f0f4
JB		 7113
7114 /* Add a '+' to the displacement string if necessary. */
7115 if (*intel_parser.disp != '\0'
7116 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7117 strcat (intel_parser.disp, "+");
64a0c779 7118
a724f0f4
JB		 7119 if (intel_expr ()
7120 && (len = intel_parser.op_string - start - 1,
7121 intel_match_token (']')))
64a0c779 7122 {
a724f0f4
JB		 7123 /* Preserve brackets when the operand is an offset expression. */
7124 if (intel_parser.in_offset)
7125 strcat (intel_parser.disp, "]");
7126 else
7127 {
7128 --intel_parser.in_bracket;
7129 if (i.base_reg || i.index_reg)
7130 intel_parser.is_mem = 1;
7131 if (!intel_parser.is_mem)
7132 {
7133 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7134 /* Defer the warning until all of the operand was parsed. */
7135 intel_parser.is_mem = -1;
7136 else if (!quiet_warnings)
7137 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
7138 }
7139 }
7140 intel_parser.op_modifier |= was_offset;
64a0c779 7141
a724f0f4 7142 return 1;
64a0c779 7143 }
a724f0f4 7144 return 0;
64a0c779
DN		 7145}
7146
7147/* e10 e11 e10'
7148
7149 e10' [ expr ] e10'
b77a7acd 7150 | Empty */
64a0c779
DN		 7151static int
7152intel_e10 ()
7153{
a724f0f4
JB		 7154 if (!intel_e11 ())
7155 return 0;
64a0c779 7156
a724f0f4 7157 while (cur_token.code == '[')
64a0c779 7158 {
a724f0f4 7159 if (!intel_bracket_expr ())
21d6c4af 7160 return 0;
64a0c779
DN		 7161 }
7162
a724f0f4 7163 return 1;
64a0c779
DN		 7164}
7165
64a0c779 7166/* e11 ( expr )
b77a7acd 7167 | [ expr ]
64a0c779
DN		 7168 | BYTE
7169 | WORD
7170 | DWORD
9306ca4a 7171 | FWORD
64a0c779 7172 | QWORD
9306ca4a
JB		 7173 | TBYTE
7174 | OWORD
7175 | XMMWORD
4a1805b1 7176 | $
64a0c779
DN		 7177 | .
7178 | register
7179 | id
7180 | constant */
7181static int
7182intel_e11 ()
7183{
a724f0f4 7184 switch (cur_token.code)
64a0c779 7185 {
a724f0f4
JB		 7186 /* e11 ( expr ) */
7187 case '(':
64a0c779
DN		 7188 intel_match_token ('(');
7189 strcat (intel_parser.disp, "(");
7190
7191 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7192 {
7193 strcat (intel_parser.disp, ")");
7194 return 1;
7195 }
a724f0f4 7196 return 0;
4a1805b1 7197
a724f0f4
JB		 7198 /* e11 [ expr ] */
7199 case '[':
a724f0f4 7200 return intel_bracket_expr ();
64a0c779 7201
a724f0f4
JB		 7202 /* e11 $
7203 | . */
7204 case '.':
64a0c779
DN		 7205 strcat (intel_parser.disp, cur_token.str);
7206 intel_match_token (cur_token.code);
21d6c4af
DN		 7207
7208 /* Mark as a memory operand only if it's not already known to be an
7209 offset expression. */
a724f0f4 7210 if (!intel_parser.in_offset)
21d6c4af 7211 intel_parser.is_mem = 1;
64a0c779
DN		 7212
7213 return 1;
64a0c779 7214
a724f0f4
JB		 7215 /* e11 register */
7216 case T_REG:
7217 {
7218 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7219
a724f0f4 7220 intel_match_token (T_REG);
64a0c779 7221
a724f0f4
JB		 7222 /* Check for segment change. */
7223 if (cur_token.code == ':')
7224 {
7225 if (!(reg->reg_type & (SReg2 | SReg3)))
7226 {
7227 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
7228 return 0;
7229 }
7230 else if (i.seg[i.mem_operands])
7231 as_warn (_("Extra segment override ignored"));
7232 else
7233 {
7234 if (!intel_parser.in_offset)
7235 intel_parser.is_mem = 1;
7236 switch (reg->reg_num)
7237 {
7238 case 0:
7239 i.seg[i.mem_operands] = &es;
7240 break;
7241 case 1:
7242 i.seg[i.mem_operands] = &cs;
7243 break;
7244 case 2:
7245 i.seg[i.mem_operands] = &ss;
7246 break;
7247 case 3:
7248 i.seg[i.mem_operands] = &ds;
7249 break;
7250 case 4:
7251 i.seg[i.mem_operands] = &fs;
7252 break;
7253 case 5:
7254 i.seg[i.mem_operands] = &gs;
7255 break;
7256 }
7257 }
7258 }
64a0c779 7259
a724f0f4
JB		 7260 /* Not a segment register. Check for register scaling. */
7261 else if (cur_token.code == '*')
7262 {
7263 if (!intel_parser.in_bracket)
7264 {
7265 as_bad (_("Register scaling only allowed in memory operands"));
7266 return 0;
7267 }
64a0c779 7268
a724f0f4
JB		 7269 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7270 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7271 else if (i.index_reg)
7272 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 7273
a724f0f4
JB		 7274 /* What follows must be a valid scale. */
7275 intel_match_token ('*');
7276 i.index_reg = reg;
7277 i.types[this_operand] |= BaseIndex;
64a0c779 7278
a724f0f4
JB		 7279 /* Set the scale after setting the register (otherwise,
7280 i386_scale will complain) */
7281 if (cur_token.code == '+' || cur_token.code == '-')
7282 {
7283 char *str, sign = cur_token.code;
7284 intel_match_token (cur_token.code);
7285 if (cur_token.code != T_CONST)
7286 {
7287 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7288 cur_token.str);
7289 return 0;
7290 }
7291 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7292 strcpy (str + 1, cur_token.str);
7293 *str = sign;
7294 if (!i386_scale (str))
7295 return 0;
7296 free (str);
7297 }
7298 else if (!i386_scale (cur_token.str))
64a0c779 7299 return 0;
a724f0f4
JB		 7300 intel_match_token (cur_token.code);
7301 }
64a0c779 7302
a724f0f4
JB		 7303 /* No scaling. If this is a memory operand, the register is either a
7304 base register (first occurrence) or an index register (second
7305 occurrence). */
7b0441f6 7306 else if (intel_parser.in_bracket)
a724f0f4 7307 {
64a0c779 7308
a724f0f4
JB		 7309 if (!i.base_reg)
7310 i.base_reg = reg;
7311 else if (!i.index_reg)
7312 i.index_reg = reg;
7313 else
7314 {
7315 as_bad (_("Too many register references in memory operand"));
7316 return 0;
7317 }
64a0c779 7318
a724f0f4
JB		 7319 i.types[this_operand] |= BaseIndex;
7320 }
4a1805b1 7321
4d1bb795
JB		 7322 /* It's neither base nor index. */
7323 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 7324 {
7325 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7326 i.op[this_operand].regs = reg;
7327 i.reg_operands++;
7328 }
7329 else
7330 {
7331 as_bad (_("Invalid use of register"));
7332 return 0;
7333 }
64a0c779 7334
a724f0f4
JB		 7335 /* Since registers are not part of the displacement string (except
7336 when we're parsing offset operands), we may need to remove any
7337 preceding '+' from the displacement string. */
7338 if (*intel_parser.disp != '\0'
7339 && !intel_parser.in_offset)
7340 {
7341 char *s = intel_parser.disp;
7342 s += strlen (s) - 1;
7343 if (*s == '+')
7344 *s = '\0';
7345 }
4a1805b1 7346
a724f0f4
JB		 7347 return 1;
7348 }
7349
7350 /* e11 BYTE
7351 | WORD
7352 | DWORD
7353 | FWORD
7354 | QWORD
7355 | TBYTE
7356 | OWORD
7357 | XMMWORD */
7358 case T_BYTE:
7359 case T_WORD:
7360 case T_DWORD:
7361 case T_FWORD:
7362 case T_QWORD:
7363 case T_TBYTE:
7364 case T_XMMWORD:
7365 intel_match_token (cur_token.code);
64a0c779 7366
a724f0f4
JB		 7367 if (cur_token.code == T_PTR)
7368 return 1;
7369
7370 /* It must have been an identifier. */
7371 intel_putback_token ();
7372 cur_token.code = T_ID;
7373 /* FALLTHRU */
7374
7375 /* e11 id
7376 | constant */
7377 case T_ID:
7378 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 7379 {
7380 symbolS *symbolP;
7381
a724f0f4
JB		 7382 /* The identifier represents a memory reference only if it's not
7383 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 7384 symbolP = symbol_find(cur_token.str);
7385 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7386 intel_parser.is_mem = 1;
7387 }
a724f0f4 7388 /* FALLTHRU */
64a0c779 7389
a724f0f4
JB		 7390 case T_CONST:
7391 case '-':
7392 case '+':
7393 {
7394 char *save_str, sign = 0;
64a0c779 7395
a724f0f4
JB		 7396 /* Allow constants that start with `+' or `-'. */
7397 if (cur_token.code == '-' || cur_token.code == '+')
7398 {
7399 sign = cur_token.code;
7400 intel_match_token (cur_token.code);
7401 if (cur_token.code != T_CONST)
7402 {
7403 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7404 cur_token.str);
7405 return 0;
7406 }
7407 }
64a0c779 7408
a724f0f4
JB		 7409 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7410 strcpy (save_str + !!sign, cur_token.str);
7411 if (sign)
7412 *save_str = sign;
64a0c779 7413
a724f0f4
JB		 7414 /* Get the next token to check for register scaling. */
7415 intel_match_token (cur_token.code);
64a0c779 7416
a724f0f4
JB		 7417 /* Check if this constant is a scaling factor for an index register. */
7418 if (cur_token.code == '*')
7419 {
7420 if (intel_match_token ('*') && cur_token.code == T_REG)
7421 {
7422 const reg_entry *reg = cur_token.reg;
7423
7424 if (!intel_parser.in_bracket)
7425 {
7426 as_bad (_("Register scaling only allowed in memory operands"));
7427 return 0;
7428 }
7429
7430 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
7431 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7432 else if (i.index_reg)
7433 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7434
7435 /* The constant is followed by `* reg', so it must be
7436 a valid scale. */
7437 i.index_reg = reg;
7438 i.types[this_operand] |= BaseIndex;
7439
7440 /* Set the scale after setting the register (otherwise,
7441 i386_scale will complain) */
7442 if (!i386_scale (save_str))
64a0c779 7443 return 0;
a724f0f4
JB		 7444 intel_match_token (T_REG);
7445
7446 /* Since registers are not part of the displacement
7447 string, we may need to remove any preceding '+' from
7448 the displacement string. */
7449 if (*intel_parser.disp != '\0')
7450 {
7451 char *s = intel_parser.disp;
7452 s += strlen (s) - 1;
7453 if (*s == '+')
7454 *s = '\0';
7455 }
7456
7457 free (save_str);
7458
7459 return 1;
7460 }
64a0c779 7461
a724f0f4
JB		 7462 /* The constant was not used for register scaling. Since we have
7463 already consumed the token following `*' we now need to put it
7464 back in the stream. */
64a0c779 7465 intel_putback_token ();
a724f0f4 7466 }
64a0c779 7467
a724f0f4
JB		 7468 /* Add the constant to the displacement string. */
7469 strcat (intel_parser.disp, save_str);
7470 free (save_str);
64a0c779 7471
a724f0f4
JB		 7472 return 1;
7473 }
64a0c779
DN		 7474 }
7475
64a0c779
DN		 7476 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7477 return 0;
7478}
7479
64a0c779
DN		 7480/* Match the given token against cur_token. If they match, read the next
7481 token from the operand string. */
7482static int
7483intel_match_token (code)
e5cb08ac 7484 int code;
64a0c779
DN		 7485{
7486 if (cur_token.code == code)
7487 {
7488 intel_get_token ();
7489 return 1;
7490 }
7491 else
7492 {
0477af35 7493 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 7494 return 0;
7495 }
7496}
7497
64a0c779
DN		 7498/* Read a new token from intel_parser.op_string and store it in cur_token. */
7499static void
7500intel_get_token ()
7501{
7502 char *end_op;
7503 const reg_entry *reg;
7504 struct intel_token new_token;
7505
7506 new_token.code = T_NIL;
7507 new_token.reg = NULL;
7508 new_token.str = NULL;
7509
4a1805b1 7510 /* Free the memory allocated to the previous token and move
64a0c779
DN		 7511 cur_token to prev_token. */
7512 if (prev_token.str)
7513 free (prev_token.str);
7514
7515 prev_token = cur_token;
7516
7517 /* Skip whitespace. */
7518 while (is_space_char (*intel_parser.op_string))
7519 intel_parser.op_string++;
7520
7521 /* Return an empty token if we find nothing else on the line. */
7522 if (*intel_parser.op_string == '\0')
7523 {
7524 cur_token = new_token;
7525 return;
7526 }
7527
7528 /* The new token cannot be larger than the remainder of the operand
7529 string. */
a724f0f4 7530 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7531 new_token.str[0] = '\0';
7532
7533 if (strchr ("0123456789", *intel_parser.op_string))
7534 {
7535 char *p = new_token.str;
7536 char *q = intel_parser.op_string;
7537 new_token.code = T_CONST;
7538
7539 /* Allow any kind of identifier char to encompass floating point and
7540 hexadecimal numbers. */
7541 while (is_identifier_char (*q))
7542 *p++ = *q++;
7543 *p = '\0';
7544
7545 /* Recognize special symbol names [0-9][bf]. */
7546 if (strlen (intel_parser.op_string) == 2
4a1805b1 7547 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7548 || intel_parser.op_string[1] == 'f'))
7549 new_token.code = T_ID;
7550 }
7551
4d1bb795 7552 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7553 {
4d1bb795
JB		 7554 size_t len = end_op - intel_parser.op_string;
7555
64a0c779
DN		 7556 new_token.code = T_REG;
7557 new_token.reg = reg;
7558
4d1bb795
JB		 7559 memcpy (new_token.str, intel_parser.op_string, len);
7560 new_token.str[len] = '\0';
64a0c779
DN		 7561 }
7562
7563 else if (is_identifier_char (*intel_parser.op_string))
7564 {
7565 char *p = new_token.str;
7566 char *q = intel_parser.op_string;
7567
7568 /* A '.' or '$' followed by an identifier char is an identifier.
7569 Otherwise, it's operator '.' followed by an expression. */
7570 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7571 {
9306ca4a
JB		 7572 new_token.code = '.';
7573 new_token.str[0] = '.';
64a0c779
DN		 7574 new_token.str[1] = '\0';
7575 }
7576 else
7577 {
7578 while (is_identifier_char (*q) || *q == '@')
7579 *p++ = *q++;
7580 *p = '\0';
7581
9306ca4a
JB		 7582 if (strcasecmp (new_token.str, "NOT") == 0)
7583 new_token.code = '~';
7584
7585 else if (strcasecmp (new_token.str, "MOD") == 0)
7586 new_token.code = '%';
7587
7588 else if (strcasecmp (new_token.str, "AND") == 0)
7589 new_token.code = '&';
7590
7591 else if (strcasecmp (new_token.str, "OR") == 0)
7592 new_token.code = '|';
7593
7594 else if (strcasecmp (new_token.str, "XOR") == 0)
7595 new_token.code = '^';
7596
7597 else if (strcasecmp (new_token.str, "SHL") == 0)
7598 new_token.code = T_SHL;
7599
7600 else if (strcasecmp (new_token.str, "SHR") == 0)
7601 new_token.code = T_SHR;
7602
7603 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7604 new_token.code = T_BYTE;
7605
7606 else if (strcasecmp (new_token.str, "WORD") == 0)
7607 new_token.code = T_WORD;
7608
7609 else if (strcasecmp (new_token.str, "DWORD") == 0)
7610 new_token.code = T_DWORD;
7611
9306ca4a
JB		 7612 else if (strcasecmp (new_token.str, "FWORD") == 0)
7613 new_token.code = T_FWORD;
7614
64a0c779
DN		 7615 else if (strcasecmp (new_token.str, "QWORD") == 0)
7616 new_token.code = T_QWORD;
7617
9306ca4a
JB		 7618 else if (strcasecmp (new_token.str, "TBYTE") == 0
7619 /* XXX remove (gcc still uses it) */
7620 || strcasecmp (new_token.str, "XWORD") == 0)
7621 new_token.code = T_TBYTE;
7622
7623 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7624 || strcasecmp (new_token.str, "OWORD") == 0)
7625 new_token.code = T_XMMWORD;
64a0c779
DN		 7626
7627 else if (strcasecmp (new_token.str, "PTR") == 0)
7628 new_token.code = T_PTR;
7629
7630 else if (strcasecmp (new_token.str, "SHORT") == 0)
7631 new_token.code = T_SHORT;
7632
7633 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7634 {
7635 new_token.code = T_OFFSET;
7636
7637 /* ??? This is not mentioned in the MASM grammar but gcc
7638 makes use of it with -mintel-syntax. OFFSET may be
7639 followed by FLAT: */
7640 if (strncasecmp (q, " FLAT:", 6) == 0)
7641 strcat (new_token.str, " FLAT:");
7642 }
7643
7644 /* ??? This is not mentioned in the MASM grammar. */
7645 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7646 {
7647 new_token.code = T_OFFSET;
7648 if (*q == ':')
7649 strcat (new_token.str, ":");
7650 else
7651 as_bad (_("`:' expected"));
7652 }
64a0c779
DN		 7653
7654 else
7655 new_token.code = T_ID;
7656 }
7657 }
7658
9306ca4a
JB		 7659 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7660 {
7661 new_token.code = *intel_parser.op_string;
7662 new_token.str[0] = *intel_parser.op_string;
7663 new_token.str[1] = '\0';
7664 }
7665
7666 else if (strchr ("<>", *intel_parser.op_string)
7667 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7668 {
7669 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7670 new_token.str[0] = *intel_parser.op_string;
7671 new_token.str[1] = *intel_parser.op_string;
7672 new_token.str[2] = '\0';
7673 }
7674
64a0c779 7675 else
0477af35 7676 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7677
7678 intel_parser.op_string += strlen (new_token.str);
7679 cur_token = new_token;
7680}
7681
64a0c779
DN		 7682/* Put cur_token back into the token stream and make cur_token point to
7683 prev_token. */
7684static void
7685intel_putback_token ()
7686{
a724f0f4
JB		 7687 if (cur_token.code != T_NIL)
7688 {
7689 intel_parser.op_string -= strlen (cur_token.str);
7690 free (cur_token.str);
7691 }
64a0c779 7692 cur_token = prev_token;
4a1805b1 7693
64a0c779
DN		 7694 /* Forget prev_token. */
7695 prev_token.code = T_NIL;
7696 prev_token.reg = NULL;
7697 prev_token.str = NULL;
7698}
54cfded0 7699
a4447b93 7700int
1df69f4f 7701tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 7702{
7703 unsigned int regnum;
7704 unsigned int regnames_count;
089dfecd 7705 static const char *const regnames_32[] =
54cfded0 7706 {
a4447b93
RH		 7707 "eax", "ecx", "edx", "ebx",
7708 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7709 "eip", "eflags", NULL,
7710 "st0", "st1", "st2", "st3",
7711 "st4", "st5", "st6", "st7",
7712 NULL, NULL,
7713 "xmm0", "xmm1", "xmm2", "xmm3",
7714 "xmm4", "xmm5", "xmm6", "xmm7",
7715 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7716 "mm4", "mm5", "mm6", "mm7",
7717 "fcw", "fsw", "mxcsr",
7718 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7719 "tr", "ldtr"
54cfded0 7720 };
089dfecd 7721 static const char *const regnames_64[] =
54cfded0 7722 {
089dfecd
JB		 7723 "rax", "rdx", "rcx", "rbx",
7724 "rsi", "rdi", "rbp", "rsp",
7725 "r8", "r9", "r10", "r11",
54cfded0 7726 "r12", "r13", "r14", "r15",
089dfecd
JB		 7727 "rip",
7728 "xmm0", "xmm1", "xmm2", "xmm3",
7729 "xmm4", "xmm5", "xmm6", "xmm7",
7730 "xmm8", "xmm9", "xmm10", "xmm11",
7731 "xmm12", "xmm13", "xmm14", "xmm15",
7732 "st0", "st1", "st2", "st3",
7733 "st4", "st5", "st6", "st7",
7734 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7735 "mm4", "mm5", "mm6", "mm7",
7736 "rflags",
7737 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7738 "fs.base", "gs.base", NULL, NULL,
7739 "tr", "ldtr",
7740 "mxcsr", "fcw", "fsw"
54cfded0 7741 };
089dfecd 7742 const char *const *regnames;
54cfded0
AM		 7743
7744 if (flag_code == CODE_64BIT)
7745 {
7746 regnames = regnames_64;
0cea6190 7747 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7748 }
7749 else
7750 {
7751 regnames = regnames_32;
0cea6190 7752 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7753 }
7754
7755 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7756 if (regnames[regnum] != NULL
7757 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7758 return regnum;
7759
54cfded0
AM		 7760 return -1;
7761}
7762
7763void
7764tc_x86_frame_initial_instructions (void)
7765{
a4447b93
RH		 7766 static unsigned int sp_regno;
7767
7768 if (!sp_regno)
7769 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7770 ? "rsp" : "esp");
7771
7772 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7773 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7774}
d2b2c203
DJ		 7775
7776int
7777i386_elf_section_type (const char *str, size_t len)
7778{
7779 if (flag_code == CODE_64BIT
7780 && len == sizeof ("unwind") - 1
7781 && strncmp (str, "unwind", 6) == 0)
7782 return SHT_X86_64_UNWIND;
7783
7784 return -1;
7785}
bb41ade5
AM		 7786
7787#ifdef TE_PE
7788void
7789tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7790{
7791 expressionS expr;
7792
7793 expr.X_op = O_secrel;
7794 expr.X_add_symbol = symbol;
7795 expr.X_add_number = 0;
7796 emit_expr (&expr, size);
7797}
7798#endif
3b22753a
L		 7799
7800#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7801/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7802
7803int
7804x86_64_section_letter (int letter, char **ptr_msg)
7805{
7806 if (flag_code == CODE_64BIT)
7807 {
7808 if (letter == 'l')
7809 return SHF_X86_64_LARGE;
7810
7811 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7812 }
3b22753a 7813 else
64e74474 7814 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7815 return -1;
7816}
7817
7818int
7819x86_64_section_word (char *str, size_t len)
7820{
8620418b 7821 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 7822 return SHF_X86_64_LARGE;
7823
7824 return -1;
7825}
7826
7827static void
7828handle_large_common (int small ATTRIBUTE_UNUSED)
7829{
7830 if (flag_code != CODE_64BIT)
7831 {
7832 s_comm_internal (0, elf_common_parse);
7833 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7834 }
7835 else
7836 {
7837 static segT lbss_section;
7838 asection *saved_com_section_ptr = elf_com_section_ptr;
7839 asection *saved_bss_section = bss_section;
7840
7841 if (lbss_section == NULL)
7842 {
7843 flagword applicable;
7844 segT seg = now_seg;
7845 subsegT subseg = now_subseg;
7846
7847 /* The .lbss section is for local .largecomm symbols. */
7848 lbss_section = subseg_new (".lbss", 0);
7849 applicable = bfd_applicable_section_flags (stdoutput);
7850 bfd_set_section_flags (stdoutput, lbss_section,
7851 applicable & SEC_ALLOC);
7852 seg_info (lbss_section)->bss = 1;
7853
7854 subseg_set (seg, subseg);
7855 }
7856
7857 elf_com_section_ptr = &_bfd_elf_large_com_section;
7858 bss_section = lbss_section;
7859
7860 s_comm_internal (0, elf_common_parse);
7861
7862 elf_com_section_ptr = saved_com_section_ptr;
7863 bss_section = saved_bss_section;
7864 }
7865}
7866#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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