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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0bfee649 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 LOCKREP_PREFIX. */
63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
67#define LOCKREP_PREFIX 4
68#define REX_PREFIX 5 /* must come last. */
69#define MAX_PREFIXES 6 /* max prefixes per opcode */
70
71/* we define the syntax here (modulo base,index,scale syntax) */
72#define REGISTER_PREFIX '%'
73#define IMMEDIATE_PREFIX '$'
74#define ABSOLUTE_PREFIX '*'
75
76/* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78#define WORD_MNEM_SUFFIX 'w'
79#define BYTE_MNEM_SUFFIX 'b'
80#define SHORT_MNEM_SUFFIX 's'
81#define LONG_MNEM_SUFFIX 'l'
82#define QWORD_MNEM_SUFFIX 'q'
83#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 84#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 85/* Intel Syntax. Use a non-ascii letter since since it never appears
86 in instructions. */
87#define LONG_DOUBLE_MNEM_SUFFIX '\1'
88
89#define END_OF_INSN '\0'
90
91/*
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
96 END.
97 */
98typedef struct
99{
d3ce72d0
NC		 100 const insn_template *start;
101 const insn_template *end;
6305a203
L		 102}
103templates;
104
105/* 386 operand encoding bytes: see 386 book for details of this. */
106typedef struct
107{
108 unsigned int regmem; /* codes register or memory operand */
109 unsigned int reg; /* codes register operand (or extended opcode) */
110 unsigned int mode; /* how to interpret regmem & reg */
111}
112modrm_byte;
113
114/* x86-64 extension prefix. */
115typedef int rex_byte;
116
6305a203
L		 117/* 386 opcode byte to code indirect addressing. */
118typedef struct
119{
120 unsigned base;
121 unsigned index;
122 unsigned scale;
123}
124sib_byte;
125
6305a203
L		 126/* x86 arch names, types and features */
127typedef struct
128{
129 const char *name; /* arch name */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132}
133arch_entry;
134
e3bb37b5
L		 135static void set_code_flag (int);
136static void set_16bit_gcc_code_flag (int);
137static void set_intel_syntax (int);
1efbbeb4 138static void set_intel_mnemonic (int);
db51cc60 139static void set_allow_index_reg (int);
cb19c032 140static void set_sse_check (int);
e3bb37b5 141static void set_cpu_arch (int);
6482c264 142#ifdef TE_PE
e3bb37b5 143static void pe_directive_secrel (int);
6482c264 144#endif
e3bb37b5
L		 145static void signed_cons (int);
146static char *output_invalid (int c);
ee86248c
JB		 147static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
148 const char *);
149static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
150 const char *);
a7619375 151static int i386_att_operand (char *);
e3bb37b5 152static int i386_intel_operand (char *, int);
ee86248c
JB		 153static int i386_intel_simplify (expressionS *);
154static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 155static const reg_entry *parse_register (char *, char **);
156static char *parse_insn (char *, char *);
157static char *parse_operands (char *, const char *);
158static void swap_operands (void);
4d456e3d 159static void swap_2_operands (int, int);
e3bb37b5
L		 160static void optimize_imm (void);
161static void optimize_disp (void);
d3ce72d0 162static const insn_template *match_template (void);
e3bb37b5
L		 163static int check_string (void);
164static int process_suffix (void);
165static int check_byte_reg (void);
166static int check_long_reg (void);
167static int check_qword_reg (void);
168static int check_word_reg (void);
169static int finalize_imm (void);
170static int process_operands (void);
171static const seg_entry *build_modrm_byte (void);
172static void output_insn (void);
173static void output_imm (fragS *, offsetT);
174static void output_disp (fragS *, offsetT);
29b0f896 175#ifndef I386COFF
e3bb37b5 176static void s_bss (int);
252b5132 177#endif
17d4e2a2
L		 178#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
179static void handle_large_common (int small ATTRIBUTE_UNUSED);
180#endif
252b5132 181
a847613f 182static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 183
c0f3af97
L		 184/* VEX prefix. */
185typedef struct
186{
187 /* VEX prefix is either 2 byte or 3 byte. */
188 unsigned char bytes[3];
189 unsigned int length;
190 /* Destination or source register specifier. */
191 const reg_entry *register_specifier;
192} vex_prefix;
193
252b5132 194/* 'md_assemble ()' gathers together information and puts it into a
47926f60 195 i386_insn. */
252b5132 196
520dc8e8
AM		 197union i386_op
198 {
199 expressionS *disps;
200 expressionS *imms;
201 const reg_entry *regs;
202 };
203
252b5132
RH		 204struct _i386_insn
205 {
47926f60 206 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 207 insn_template tm;
252b5132 208
7d5e4556
L		 209 /* SUFFIX holds the instruction size suffix for byte, word, dword
210 or qword, if given. */
252b5132
RH		 211 char suffix;
212
47926f60 213 /* OPERANDS gives the number of given operands. */
252b5132
RH		 214 unsigned int operands;
215
216 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
217 of given register, displacement, memory operands and immediate
47926f60 218 operands. */
252b5132
RH		 219 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
220
221 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 222 use OP[i] for the corresponding operand. */
40fb9820 223 i386_operand_type types[MAX_OPERANDS];
252b5132 224
520dc8e8
AM		 225 /* Displacement expression, immediate expression, or register for each
226 operand. */
227 union i386_op op[MAX_OPERANDS];
252b5132 228
3e73aa7c
JH		 229 /* Flags for operands. */
230 unsigned int flags[MAX_OPERANDS];
231#define Operand_PCrel 1
232
252b5132 233 /* Relocation type for operand */
f86103b7 234 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 235
252b5132
RH		 236 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
237 the base index byte below. */
238 const reg_entry *base_reg;
239 const reg_entry *index_reg;
240 unsigned int log2_scale_factor;
241
242 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 243 explicit segment overrides are given. */
ce8a8b2f 244 const seg_entry *seg[2];
252b5132
RH		 245
246 /* PREFIX holds all the given prefix opcodes (usually null).
247 PREFIXES is the number of prefix opcodes. */
248 unsigned int prefixes;
249 unsigned char prefix[MAX_PREFIXES];
250
251 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 252 addressing modes of this insn are encoded. */
252b5132 253 modrm_byte rm;
3e73aa7c 254 rex_byte rex;
252b5132 255 sib_byte sib;
c0f3af97 256 vex_prefix vex;
b6169b20
L		 257
258 /* Swap operand in encoding. */
259 unsigned int swap_operand : 1;
252b5132
RH		 260 };
261
262typedef struct _i386_insn i386_insn;
263
264/* List of chars besides those in app.c:symbol_chars that can start an
265 operand. Used to prevent the scrubber eating vital white-space. */
32137342 266const char extra_symbol_chars[] = "*%-(["
252b5132 267#ifdef LEX_AT
32137342
NC		 268 "@"
269#endif
270#ifdef LEX_QM
271 "?"
252b5132 272#endif
32137342 273 ;
252b5132 274
29b0f896
AM		 275#if (defined (TE_I386AIX) \
276 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 277 && !defined (TE_GNU) \
29b0f896 278 && !defined (TE_LINUX) \
32137342 279 && !defined (TE_NETWARE) \
29b0f896
AM		 280 && !defined (TE_FreeBSD) \
281 && !defined (TE_NetBSD)))
252b5132 282/* This array holds the chars that always start a comment. If the
b3b91714
AM		 283 pre-processor is disabled, these aren't very useful. The option
284 --divide will remove '/' from this list. */
285const char *i386_comment_chars = "#/";
286#define SVR4_COMMENT_CHARS 1
252b5132 287#define PREFIX_SEPARATOR '\\'
252b5132 288
b3b91714
AM		 289#else
290const char *i386_comment_chars = "#";
291#define PREFIX_SEPARATOR '/'
292#endif
293
252b5132
RH		 294/* This array holds the chars that only start a comment at the beginning of
295 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 296 .line and .file directives will appear in the pre-processed output.
297 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 298 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 299 #NO_APP at the beginning of its output.
300 Also note that comments started like this one will always work if
252b5132 301 '/' isn't otherwise defined. */
b3b91714 302const char line_comment_chars[] = "#/";
252b5132 303
63a0b638 304const char line_separator_chars[] = ";";
252b5132 305
ce8a8b2f
AM		 306/* Chars that can be used to separate mant from exp in floating point
307 nums. */
252b5132
RH		 308const char EXP_CHARS[] = "eE";
309
ce8a8b2f
AM		 310/* Chars that mean this number is a floating point constant
311 As in 0f12.456
312 or 0d1.2345e12. */
252b5132
RH		 313const char FLT_CHARS[] = "fFdDxX";
314
ce8a8b2f 315/* Tables for lexical analysis. */
252b5132
RH		 316static char mnemonic_chars[256];
317static char register_chars[256];
318static char operand_chars[256];
319static char identifier_chars[256];
320static char digit_chars[256];
321
ce8a8b2f 322/* Lexical macros. */
252b5132
RH		 323#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
324#define is_operand_char(x) (operand_chars[(unsigned char) x])
325#define is_register_char(x) (register_chars[(unsigned char) x])
326#define is_space_char(x) ((x) == ' ')
327#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
328#define is_digit_char(x) (digit_chars[(unsigned char) x])
329
0234cb7c 330/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 331static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
332
333/* md_assemble() always leaves the strings it's passed unaltered. To
334 effect this we maintain a stack of saved characters that we've smashed
335 with '\0's (indicating end of strings for various sub-fields of the
47926f60 336 assembler instruction). */
252b5132 337static char save_stack[32];
ce8a8b2f 338static char *save_stack_p;
252b5132
RH		 339#define END_STRING_AND_SAVE(s) \
340 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
341#define RESTORE_END_STRING(s) \
342 do { *(s) = *--save_stack_p; } while (0)
343
47926f60 344/* The instruction we're assembling. */
252b5132
RH		 345static i386_insn i;
346
347/* Possible templates for current insn. */
348static const templates *current_templates;
349
31b2323c
L		 350/* Per instruction expressionS buffers: max displacements & immediates. */
351static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
352static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 353
47926f60 354/* Current operand we are working on. */
ee86248c 355static int this_operand = -1;
252b5132 356
3e73aa7c
JH		 357/* We support four different modes. FLAG_CODE variable is used to distinguish
358 these. */
359
360enum flag_code {
361 CODE_32BIT,
362 CODE_16BIT,
363 CODE_64BIT };
364
365static enum flag_code flag_code;
4fa24527 366static unsigned int object_64bit;
3e73aa7c
JH		 367static int use_rela_relocations = 0;
368
369/* The names used to print error messages. */
b77a7acd 370static const char *flag_code_names[] =
3e73aa7c
JH		 371 {
372 "32",
373 "16",
374 "64"
375 };
252b5132 376
47926f60
KH		 377/* 1 for intel syntax,
378 0 if att syntax. */
379static int intel_syntax = 0;
252b5132 380
1efbbeb4
L		 381/* 1 for intel mnemonic,
382 0 if att mnemonic. */
383static int intel_mnemonic = !SYSV386_COMPAT;
384
5209009a 385/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 386static int old_gcc = OLDGCC_COMPAT;
387
a60de03c
JB		 388/* 1 if pseudo registers are permitted. */
389static int allow_pseudo_reg = 0;
390
47926f60
KH		 391/* 1 if register prefix % not required. */
392static int allow_naked_reg = 0;
252b5132 393
ba104c83 394/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 395static int allow_index_reg = 0;
396
daf50ae7
L		 397static enum
398 {
399 sse_check_none = 0,
400 sse_check_warning,
401 sse_check_error
402 }
403sse_check;
404
2ca3ace5
L		 405/* Register prefix used for error message. */
406static const char *register_prefix = "%";
407
47926f60
KH		 408/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
409 leave, push, and pop instructions so that gcc has the same stack
410 frame as in 32 bit mode. */
411static char stackop_size = '\0';
eecb386c 412
12b55ccc
L		 413/* Non-zero to optimize code alignment. */
414int optimize_align_code = 1;
415
47926f60
KH		 416/* Non-zero to quieten some warnings. */
417static int quiet_warnings = 0;
a38cf1db 418
47926f60
KH		 419/* CPU name. */
420static const char *cpu_arch_name = NULL;
6305a203 421static char *cpu_sub_arch_name = NULL;
a38cf1db 422
47926f60 423/* CPU feature flags. */
40fb9820
L		 424static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
425
ccc9c027
L		 426/* If we have selected a cpu we are generating instructions for. */
427static int cpu_arch_tune_set = 0;
428
9103f4f4 429/* Cpu we are generating instructions for. */
fbf3f584 430enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 431
432/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 433static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 434
ccc9c027 435/* CPU instruction set architecture used. */
fbf3f584 436enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 437
9103f4f4 438/* CPU feature flags of instruction set architecture used. */
fbf3f584 439i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 440
fddf5b5b
AM		 441/* If set, conditional jumps are not automatically promoted to handle
442 larger than a byte offset. */
443static unsigned int no_cond_jump_promotion = 0;
444
c0f3af97
L		 445/* Encode SSE instructions with VEX prefix. */
446static unsigned int sse2avx;
447
29b0f896 448/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 449static symbolS *GOT_symbol;
29b0f896 450
a4447b93
RH		 451/* The dwarf2 return column, adjusted for 32 or 64 bit. */
452unsigned int x86_dwarf2_return_column;
453
454/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
455int x86_cie_data_alignment;
456
252b5132 457/* Interface to relax_segment.
fddf5b5b
AM		 458 There are 3 major relax states for 386 jump insns because the
459 different types of jumps add different sizes to frags when we're
460 figuring out what sort of jump to choose to reach a given label. */
252b5132 461
47926f60 462/* Types. */
93c2a809
AM		 463#define UNCOND_JUMP 0
464#define COND_JUMP 1
465#define COND_JUMP86 2
fddf5b5b 466
47926f60 467/* Sizes. */
252b5132
RH		 468#define CODE16 1
469#define SMALL 0
29b0f896 470#define SMALL16 (SMALL | CODE16)
252b5132 471#define BIG 2
29b0f896 472#define BIG16 (BIG | CODE16)
252b5132
RH		 473
474#ifndef INLINE
475#ifdef __GNUC__
476#define INLINE __inline__
477#else
478#define INLINE
479#endif
480#endif
481
fddf5b5b
AM		 482#define ENCODE_RELAX_STATE(type, size) \
483 ((relax_substateT) (((type) << 2) | (size)))
484#define TYPE_FROM_RELAX_STATE(s) \
485 ((s) >> 2)
486#define DISP_SIZE_FROM_RELAX_STATE(s) \
487 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 488
489/* This table is used by relax_frag to promote short jumps to long
490 ones where necessary. SMALL (short) jumps may be promoted to BIG
491 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
492 don't allow a short jump in a 32 bit code segment to be promoted to
493 a 16 bit offset jump because it's slower (requires data size
494 prefix), and doesn't work, unless the destination is in the bottom
495 64k of the code segment (The top 16 bits of eip are zeroed). */
496
497const relax_typeS md_relax_table[] =
498{
24eab124
AM		 499 /* The fields are:
500 1) most positive reach of this state,
501 2) most negative reach of this state,
93c2a809 502 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 503 4) which index into the table to try if we can't fit into this one. */
252b5132 504
fddf5b5b 505 /* UNCOND_JUMP states. */
93c2a809
AM		 506 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
507 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
508 /* dword jmp adds 4 bytes to frag:
509 0 extra opcode bytes, 4 displacement bytes. */
252b5132 510 {0, 0, 4, 0},
93c2a809
AM		 511 /* word jmp adds 2 byte2 to frag:
512 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 513 {0, 0, 2, 0},
514
93c2a809
AM		 515 /* COND_JUMP states. */
516 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
518 /* dword conditionals adds 5 bytes to frag:
519 1 extra opcode byte, 4 displacement bytes. */
520 {0, 0, 5, 0},
fddf5b5b 521 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 522 1 extra opcode byte, 2 displacement bytes. */
523 {0, 0, 3, 0},
524
525 /* COND_JUMP86 states. */
526 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
528 /* dword conditionals adds 5 bytes to frag:
529 1 extra opcode byte, 4 displacement bytes. */
530 {0, 0, 5, 0},
531 /* word conditionals add 4 bytes to frag:
532 1 displacement byte and a 3 byte long branch insn. */
533 {0, 0, 4, 0}
252b5132
RH		 534};
535
9103f4f4
L		 536static const arch_entry cpu_arch[] =
537{
6305a203
L		 538 { "generic32", PROCESSOR_GENERIC32,
539 CPU_GENERIC32_FLAGS },
540 { "generic64", PROCESSOR_GENERIC64,
541 CPU_GENERIC64_FLAGS },
542 { "i8086", PROCESSOR_UNKNOWN,
543 CPU_NONE_FLAGS },
544 { "i186", PROCESSOR_UNKNOWN,
545 CPU_I186_FLAGS },
546 { "i286", PROCESSOR_UNKNOWN,
547 CPU_I286_FLAGS },
548 { "i386", PROCESSOR_I386,
549 CPU_I386_FLAGS },
550 { "i486", PROCESSOR_I486,
551 CPU_I486_FLAGS },
552 { "i586", PROCESSOR_PENTIUM,
553 CPU_I586_FLAGS },
554 { "i686", PROCESSOR_PENTIUMPRO,
555 CPU_I686_FLAGS },
556 { "pentium", PROCESSOR_PENTIUM,
557 CPU_I586_FLAGS },
558 { "pentiumpro", PROCESSOR_PENTIUMPRO,
559 CPU_I686_FLAGS },
560 { "pentiumii", PROCESSOR_PENTIUMPRO,
561 CPU_P2_FLAGS },
562 { "pentiumiii",PROCESSOR_PENTIUMPRO,
563 CPU_P3_FLAGS },
564 { "pentium4", PROCESSOR_PENTIUM4,
565 CPU_P4_FLAGS },
566 { "prescott", PROCESSOR_NOCONA,
567 CPU_CORE_FLAGS },
568 { "nocona", PROCESSOR_NOCONA,
569 CPU_NOCONA_FLAGS },
570 { "yonah", PROCESSOR_CORE,
571 CPU_CORE_FLAGS },
572 { "core", PROCESSOR_CORE,
573 CPU_CORE_FLAGS },
574 { "merom", PROCESSOR_CORE2,
575 CPU_CORE2_FLAGS },
576 { "core2", PROCESSOR_CORE2,
577 CPU_CORE2_FLAGS },
bd5295b2
L		 578 { "corei7", PROCESSOR_COREI7,
579 CPU_COREI7_FLAGS },
3632d14b 580 { "l1om", PROCESSOR_L1OM,
8a9036a4 581 CPU_L1OM_FLAGS },
6305a203
L		 582 { "k6", PROCESSOR_K6,
583 CPU_K6_FLAGS },
584 { "k6_2", PROCESSOR_K6,
585 CPU_K6_2_FLAGS },
586 { "athlon", PROCESSOR_ATHLON,
587 CPU_ATHLON_FLAGS },
588 { "sledgehammer", PROCESSOR_K8,
589 CPU_K8_FLAGS },
590 { "opteron", PROCESSOR_K8,
591 CPU_K8_FLAGS },
592 { "k8", PROCESSOR_K8,
593 CPU_K8_FLAGS },
594 { "amdfam10", PROCESSOR_AMDFAM10,
595 CPU_AMDFAM10_FLAGS },
309d3373
JB		 596 { ".8087", PROCESSOR_UNKNOWN,
597 CPU_8087_FLAGS },
598 { ".287", PROCESSOR_UNKNOWN,
599 CPU_287_FLAGS },
600 { ".387", PROCESSOR_UNKNOWN,
601 CPU_387_FLAGS },
602 { ".no87", PROCESSOR_UNKNOWN,
603 CPU_ANY87_FLAGS },
6305a203
L		 604 { ".mmx", PROCESSOR_UNKNOWN,
605 CPU_MMX_FLAGS },
309d3373
JB		 606 { ".nommx", PROCESSOR_UNKNOWN,
607 CPU_3DNOWA_FLAGS },
6305a203
L		 608 { ".sse", PROCESSOR_UNKNOWN,
609 CPU_SSE_FLAGS },
610 { ".sse2", PROCESSOR_UNKNOWN,
611 CPU_SSE2_FLAGS },
612 { ".sse3", PROCESSOR_UNKNOWN,
613 CPU_SSE3_FLAGS },
614 { ".ssse3", PROCESSOR_UNKNOWN,
615 CPU_SSSE3_FLAGS },
616 { ".sse4.1", PROCESSOR_UNKNOWN,
617 CPU_SSE4_1_FLAGS },
618 { ".sse4.2", PROCESSOR_UNKNOWN,
619 CPU_SSE4_2_FLAGS },
620 { ".sse4", PROCESSOR_UNKNOWN,
621 CPU_SSE4_2_FLAGS },
309d3373
JB		 622 { ".nosse", PROCESSOR_UNKNOWN,
623 CPU_ANY_SSE_FLAGS },
c0f3af97
L		 624 { ".avx", PROCESSOR_UNKNOWN,
625 CPU_AVX_FLAGS },
309d3373
JB		 626 { ".noavx", PROCESSOR_UNKNOWN,
627 CPU_ANY_AVX_FLAGS },
6305a203
L		 628 { ".vmx", PROCESSOR_UNKNOWN,
629 CPU_VMX_FLAGS },
630 { ".smx", PROCESSOR_UNKNOWN,
631 CPU_SMX_FLAGS },
f03fe4c1
L		 632 { ".xsave", PROCESSOR_UNKNOWN,
633 CPU_XSAVE_FLAGS },
c0f3af97
L		 634 { ".aes", PROCESSOR_UNKNOWN,
635 CPU_AES_FLAGS },
594ab6a3
L		 636 { ".pclmul", PROCESSOR_UNKNOWN,
637 CPU_PCLMUL_FLAGS },
c0f3af97 638 { ".clmul", PROCESSOR_UNKNOWN,
594ab6a3 639 CPU_PCLMUL_FLAGS },
c0f3af97
L		 640 { ".fma", PROCESSOR_UNKNOWN,
641 CPU_FMA_FLAGS },
922d8de8
DR		 642 { ".fma4", PROCESSOR_UNKNOWN,
643 CPU_FMA4_FLAGS },
f1f8f695
L		 644 { ".movbe", PROCESSOR_UNKNOWN,
645 CPU_MOVBE_FLAGS },
646 { ".ept", PROCESSOR_UNKNOWN,
647 CPU_EPT_FLAGS },
bd5295b2
L		 648 { ".clflush", PROCESSOR_UNKNOWN,
649 CPU_CLFLUSH_FLAGS },
650 { ".syscall", PROCESSOR_UNKNOWN,
651 CPU_SYSCALL_FLAGS },
1b7f3fb0
L		 652 { ".rdtscp", PROCESSOR_UNKNOWN,
653 CPU_RDTSCP_FLAGS },
6305a203
L		 654 { ".3dnow", PROCESSOR_UNKNOWN,
655 CPU_3DNOW_FLAGS },
656 { ".3dnowa", PROCESSOR_UNKNOWN,
657 CPU_3DNOWA_FLAGS },
658 { ".padlock", PROCESSOR_UNKNOWN,
659 CPU_PADLOCK_FLAGS },
660 { ".pacifica", PROCESSOR_UNKNOWN,
661 CPU_SVME_FLAGS },
662 { ".svme", PROCESSOR_UNKNOWN,
663 CPU_SVME_FLAGS },
664 { ".sse4a", PROCESSOR_UNKNOWN,
665 CPU_SSE4A_FLAGS },
666 { ".abm", PROCESSOR_UNKNOWN,
667 CPU_ABM_FLAGS },
e413e4e9
AM		 668};
669
704209c0 670#ifdef I386COFF
a6c24e68
NC		 671/* Like s_lcomm_internal in gas/read.c but the alignment string
672 is allowed to be optional. */
673
674static symbolS *
675pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
676{
677 addressT align = 0;
678
679 SKIP_WHITESPACE ();
680
7ab9ffdd 681 if (needs_align
a6c24e68
NC		 682 && *input_line_pointer == ',')
683 {
684 align = parse_align (needs_align - 1);
7ab9ffdd 685
a6c24e68
NC		 686 if (align == (addressT) -1)
687 return NULL;
688 }
689 else
690 {
691 if (size >= 8)
692 align = 3;
693 else if (size >= 4)
694 align = 2;
695 else if (size >= 2)
696 align = 1;
697 else
698 align = 0;
699 }
700
701 bss_alloc (symbolP, size, align);
702 return symbolP;
703}
704
704209c0 705static void
a6c24e68
NC		 706pe_lcomm (int needs_align)
707{
708 s_comm_internal (needs_align * 2, pe_lcomm_internal);
709}
704209c0 710#endif
a6c24e68 711
29b0f896
AM		 712const pseudo_typeS md_pseudo_table[] =
713{
714#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
715 {"align", s_align_bytes, 0},
716#else
717 {"align", s_align_ptwo, 0},
718#endif
719 {"arch", set_cpu_arch, 0},
720#ifndef I386COFF
721 {"bss", s_bss, 0},
a6c24e68
NC		 722#else
723 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 724#endif
725 {"ffloat", float_cons, 'f'},
726 {"dfloat", float_cons, 'd'},
727 {"tfloat", float_cons, 'x'},
728 {"value", cons, 2},
d182319b 729 {"slong", signed_cons, 4},
29b0f896
AM		 730 {"noopt", s_ignore, 0},
731 {"optim", s_ignore, 0},
732 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
733 {"code16", set_code_flag, CODE_16BIT},
734 {"code32", set_code_flag, CODE_32BIT},
735 {"code64", set_code_flag, CODE_64BIT},
736 {"intel_syntax", set_intel_syntax, 1},
737 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 738 {"intel_mnemonic", set_intel_mnemonic, 1},
739 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 740 {"allow_index_reg", set_allow_index_reg, 1},
741 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 742 {"sse_check", set_sse_check, 0},
3b22753a
L		 743#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
744 {"largecomm", handle_large_common, 0},
07a53e5c 745#else
e3bb37b5 746 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 747 {"loc", dwarf2_directive_loc, 0},
748 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 749#endif
6482c264
NC		 750#ifdef TE_PE
751 {"secrel32", pe_directive_secrel, 0},
752#endif
29b0f896
AM		 753 {0, 0, 0}
754};
755
756/* For interface with expression (). */
757extern char *input_line_pointer;
758
759/* Hash table for instruction mnemonic lookup. */
760static struct hash_control *op_hash;
761
762/* Hash table for register lookup. */
763static struct hash_control *reg_hash;
764\f
252b5132 765void
e3bb37b5 766i386_align_code (fragS *fragP, int count)
252b5132 767{
ce8a8b2f
AM		 768 /* Various efficient no-op patterns for aligning code labels.
769 Note: Don't try to assemble the instructions in the comments.
770 0L and 0w are not legal. */
252b5132
RH		 771 static const char f32_1[] =
772 {0x90}; /* nop */
773 static const char f32_2[] =
ccc9c027 774 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 775 static const char f32_3[] =
776 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
777 static const char f32_4[] =
778 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
779 static const char f32_5[] =
780 {0x90, /* nop */
781 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
782 static const char f32_6[] =
783 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
784 static const char f32_7[] =
785 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
786 static const char f32_8[] =
787 {0x90, /* nop */
788 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
789 static const char f32_9[] =
790 {0x89,0xf6, /* movl %esi,%esi */
791 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
792 static const char f32_10[] =
793 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
794 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
795 static const char f32_11[] =
796 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
797 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
798 static const char f32_12[] =
799 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
800 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
801 static const char f32_13[] =
802 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
803 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
804 static const char f32_14[] =
805 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
806 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 807 static const char f16_3[] =
808 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 809 static const char f16_4[] =
810 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
811 static const char f16_5[] =
812 {0x90, /* nop */
813 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
814 static const char f16_6[] =
815 {0x89,0xf6, /* mov %si,%si */
816 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
817 static const char f16_7[] =
818 {0x8d,0x74,0x00, /* lea 0(%si),%si */
819 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
820 static const char f16_8[] =
821 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
822 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 823 static const char jump_31[] =
824 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
825 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
826 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
827 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 828 static const char *const f32_patt[] = {
829 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 830 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 831 };
832 static const char *const f16_patt[] = {
76bc74dc 833 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 834 };
ccc9c027
L		 835 /* nopl (%[re]ax) */
836 static const char alt_3[] =
837 {0x0f,0x1f,0x00};
838 /* nopl 0(%[re]ax) */
839 static const char alt_4[] =
840 {0x0f,0x1f,0x40,0x00};
841 /* nopl 0(%[re]ax,%[re]ax,1) */
842 static const char alt_5[] =
843 {0x0f,0x1f,0x44,0x00,0x00};
844 /* nopw 0(%[re]ax,%[re]ax,1) */
845 static const char alt_6[] =
846 {0x66,0x0f,0x1f,0x44,0x00,0x00};
847 /* nopl 0L(%[re]ax) */
848 static const char alt_7[] =
849 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
850 /* nopl 0L(%[re]ax,%[re]ax,1) */
851 static const char alt_8[] =
852 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
853 /* nopw 0L(%[re]ax,%[re]ax,1) */
854 static const char alt_9[] =
855 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
856 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
857 static const char alt_10[] =
858 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
859 /* data16
860 nopw %cs:0L(%[re]ax,%[re]ax,1) */
861 static const char alt_long_11[] =
862 {0x66,
863 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
864 /* data16
865 data16
866 nopw %cs:0L(%[re]ax,%[re]ax,1) */
867 static const char alt_long_12[] =
868 {0x66,
869 0x66,
870 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
871 /* data16
872 data16
873 data16
874 nopw %cs:0L(%[re]ax,%[re]ax,1) */
875 static const char alt_long_13[] =
876 {0x66,
877 0x66,
878 0x66,
879 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
880 /* data16
881 data16
882 data16
883 data16
884 nopw %cs:0L(%[re]ax,%[re]ax,1) */
885 static const char alt_long_14[] =
886 {0x66,
887 0x66,
888 0x66,
889 0x66,
890 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
891 /* data16
892 data16
893 data16
894 data16
895 data16
896 nopw %cs:0L(%[re]ax,%[re]ax,1) */
897 static const char alt_long_15[] =
898 {0x66,
899 0x66,
900 0x66,
901 0x66,
902 0x66,
903 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
904 /* nopl 0(%[re]ax,%[re]ax,1)
905 nopw 0(%[re]ax,%[re]ax,1) */
906 static const char alt_short_11[] =
907 {0x0f,0x1f,0x44,0x00,0x00,
908 0x66,0x0f,0x1f,0x44,0x00,0x00};
909 /* nopw 0(%[re]ax,%[re]ax,1)
910 nopw 0(%[re]ax,%[re]ax,1) */
911 static const char alt_short_12[] =
912 {0x66,0x0f,0x1f,0x44,0x00,0x00,
913 0x66,0x0f,0x1f,0x44,0x00,0x00};
914 /* nopw 0(%[re]ax,%[re]ax,1)
915 nopl 0L(%[re]ax) */
916 static const char alt_short_13[] =
917 {0x66,0x0f,0x1f,0x44,0x00,0x00,
918 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
919 /* nopl 0L(%[re]ax)
920 nopl 0L(%[re]ax) */
921 static const char alt_short_14[] =
922 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
923 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
924 /* nopl 0L(%[re]ax)
925 nopl 0L(%[re]ax,%[re]ax,1) */
926 static const char alt_short_15[] =
927 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
928 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
929 static const char *const alt_short_patt[] = {
930 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
931 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
932 alt_short_14, alt_short_15
933 };
934 static const char *const alt_long_patt[] = {
935 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
936 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
937 alt_long_14, alt_long_15
938 };
252b5132 939
76bc74dc
L		 940 /* Only align for at least a positive non-zero boundary. */
941 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 942 return;
3e73aa7c 943
ccc9c027
L		 944 /* We need to decide which NOP sequence to use for 32bit and
945 64bit. When -mtune= is used:
4eed87de 946
76bc74dc
L		 947 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
948 PROCESSOR_GENERIC32, f32_patt will be used.
949 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 950 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
951 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc
L		 952 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
953 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 954
76bc74dc
L		 955 When -mtune= isn't used, alt_long_patt will be used if
956 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
957 be used.
ccc9c027
L		 958
959 When -march= or .arch is used, we can't use anything beyond
960 cpu_arch_isa_flags. */
961
962 if (flag_code == CODE_16BIT)
963 {
ccc9c027 964 if (count > 8)
33fef721 965 {
76bc74dc
L		 966 memcpy (fragP->fr_literal + fragP->fr_fix,
967 jump_31, count);
968 /* Adjust jump offset. */
969 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 970 }
76bc74dc
L		 971 else
972 memcpy (fragP->fr_literal + fragP->fr_fix,
973 f16_patt[count - 1], count);
252b5132 974 }
33fef721 975 else
ccc9c027
L		 976 {
977 const char *const *patt = NULL;
978
fbf3f584 979 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 980 {
981 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
982 switch (cpu_arch_tune)
983 {
984 case PROCESSOR_UNKNOWN:
985 /* We use cpu_arch_isa_flags to check if we SHOULD
986 optimize for Cpu686. */
fbf3f584 987 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
76bc74dc 988 patt = alt_long_patt;
ccc9c027
L		 989 else
990 patt = f32_patt;
991 break;
ccc9c027
L		 992 case PROCESSOR_PENTIUMPRO:
993 case PROCESSOR_PENTIUM4:
994 case PROCESSOR_NOCONA:
ef05d495 995 case PROCESSOR_CORE:
76bc74dc 996 case PROCESSOR_CORE2:
bd5295b2 997 case PROCESSOR_COREI7:
3632d14b 998 case PROCESSOR_L1OM:
76bc74dc
L		 999 case PROCESSOR_GENERIC64:
1000 patt = alt_long_patt;
1001 break;
ccc9c027
L		 1002 case PROCESSOR_K6:
1003 case PROCESSOR_ATHLON:
1004 case PROCESSOR_K8:
4eed87de 1005 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1006 patt = alt_short_patt;
1007 break;
76bc74dc 1008 case PROCESSOR_I386:
ccc9c027
L		 1009 case PROCESSOR_I486:
1010 case PROCESSOR_PENTIUM:
1011 case PROCESSOR_GENERIC32:
1012 patt = f32_patt;
1013 break;
4eed87de 1014 }
ccc9c027
L		 1015 }
1016 else
1017 {
fbf3f584 1018 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1019 {
1020 case PROCESSOR_UNKNOWN:
e6a14101 1021 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1022 PROCESSOR_UNKNOWN. */
1023 abort ();
1024 break;
1025
76bc74dc 1026 case PROCESSOR_I386:
ccc9c027
L		 1027 case PROCESSOR_I486:
1028 case PROCESSOR_PENTIUM:
ccc9c027
L		 1029 case PROCESSOR_K6:
1030 case PROCESSOR_ATHLON:
1031 case PROCESSOR_K8:
4eed87de 1032 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1033 case PROCESSOR_GENERIC32:
1034 /* We use cpu_arch_isa_flags to check if we CAN optimize
1035 for Cpu686. */
fbf3f584 1036 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1037 patt = alt_short_patt;
1038 else
1039 patt = f32_patt;
1040 break;
76bc74dc
L		 1041 case PROCESSOR_PENTIUMPRO:
1042 case PROCESSOR_PENTIUM4:
1043 case PROCESSOR_NOCONA:
1044 case PROCESSOR_CORE:
ef05d495 1045 case PROCESSOR_CORE2:
bd5295b2 1046 case PROCESSOR_COREI7:
3632d14b 1047 case PROCESSOR_L1OM:
fbf3f584 1048 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1049 patt = alt_long_patt;
1050 else
1051 patt = f32_patt;
1052 break;
1053 case PROCESSOR_GENERIC64:
76bc74dc 1054 patt = alt_long_patt;
ccc9c027 1055 break;
4eed87de 1056 }
ccc9c027
L		 1057 }
1058
76bc74dc
L		 1059 if (patt == f32_patt)
1060 {
1061 /* If the padding is less than 15 bytes, we use the normal
1062 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1063 its offset. */
1064 int limit;
1065
1066 /* For 64bit, the limit is 3 bytes. */
1067 if (flag_code == CODE_64BIT
1068 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1069 limit = 3;
1070 else
1071 limit = 15;
1072 if (count < limit)
76bc74dc
L		 1073 memcpy (fragP->fr_literal + fragP->fr_fix,
1074 patt[count - 1], count);
1075 else
1076 {
1077 memcpy (fragP->fr_literal + fragP->fr_fix,
1078 jump_31, count);
1079 /* Adjust jump offset. */
1080 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1081 }
1082 }
1083 else
1084 {
1085 /* Maximum length of an instruction is 15 byte. If the
1086 padding is greater than 15 bytes and we don't use jump,
1087 we have to break it into smaller pieces. */
1088 int padding = count;
1089 while (padding > 15)
1090 {
1091 padding -= 15;
1092 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1093 patt [14], 15);
1094 }
1095
1096 if (padding)
1097 memcpy (fragP->fr_literal + fragP->fr_fix,
1098 patt [padding - 1], padding);
1099 }
ccc9c027 1100 }
33fef721 1101 fragP->fr_var = count;
252b5132
RH		 1102}
1103
c6fb90c8 1104static INLINE int
0dfbf9d7 1105operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1106{
0dfbf9d7 1107 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1108 {
1109 case 3:
0dfbf9d7 1110 if (x->array[2])
c6fb90c8
L		 1111 return 0;
1112 case 2:
0dfbf9d7 1113 if (x->array[1])
c6fb90c8
L		 1114 return 0;
1115 case 1:
0dfbf9d7 1116 return !x->array[0];
c6fb90c8
L		 1117 default:
1118 abort ();
1119 }
40fb9820
L		 1120}
1121
c6fb90c8 1122static INLINE void
0dfbf9d7 1123operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1124{
0dfbf9d7 1125 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1126 {
1127 case 3:
0dfbf9d7 1128 x->array[2] = v;
c6fb90c8 1129 case 2:
0dfbf9d7 1130 x->array[1] = v;
c6fb90c8 1131 case 1:
0dfbf9d7 1132 x->array[0] = v;
c6fb90c8
L		 1133 break;
1134 default:
1135 abort ();
1136 }
1137}
40fb9820 1138
c6fb90c8 1139static INLINE int
0dfbf9d7
L		 1140operand_type_equal (const union i386_operand_type *x,
1141 const union i386_operand_type *y)
c6fb90c8 1142{
0dfbf9d7 1143 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1144 {
1145 case 3:
0dfbf9d7 1146 if (x->array[2] != y->array[2])
c6fb90c8
L		 1147 return 0;
1148 case 2:
0dfbf9d7 1149 if (x->array[1] != y->array[1])
c6fb90c8
L		 1150 return 0;
1151 case 1:
0dfbf9d7 1152 return x->array[0] == y->array[0];
c6fb90c8
L		 1153 break;
1154 default:
1155 abort ();
1156 }
1157}
40fb9820 1158
0dfbf9d7
L		 1159static INLINE int
1160cpu_flags_all_zero (const union i386_cpu_flags *x)
1161{
1162 switch (ARRAY_SIZE(x->array))
1163 {
1164 case 3:
1165 if (x->array[2])
1166 return 0;
1167 case 2:
1168 if (x->array[1])
1169 return 0;
1170 case 1:
1171 return !x->array[0];
1172 default:
1173 abort ();
1174 }
1175}
1176
1177static INLINE void
1178cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1179{
1180 switch (ARRAY_SIZE(x->array))
1181 {
1182 case 3:
1183 x->array[2] = v;
1184 case 2:
1185 x->array[1] = v;
1186 case 1:
1187 x->array[0] = v;
1188 break;
1189 default:
1190 abort ();
1191 }
1192}
1193
1194static INLINE int
1195cpu_flags_equal (const union i386_cpu_flags *x,
1196 const union i386_cpu_flags *y)
1197{
1198 switch (ARRAY_SIZE(x->array))
1199 {
1200 case 3:
1201 if (x->array[2] != y->array[2])
1202 return 0;
1203 case 2:
1204 if (x->array[1] != y->array[1])
1205 return 0;
1206 case 1:
1207 return x->array[0] == y->array[0];
1208 break;
1209 default:
1210 abort ();
1211 }
1212}
c6fb90c8
L		 1213
1214static INLINE int
1215cpu_flags_check_cpu64 (i386_cpu_flags f)
1216{
1217 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1218 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1219}
1220
c6fb90c8
L		 1221static INLINE i386_cpu_flags
1222cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1223{
c6fb90c8
L		 1224 switch (ARRAY_SIZE (x.array))
1225 {
1226 case 3:
1227 x.array [2] &= y.array [2];
1228 case 2:
1229 x.array [1] &= y.array [1];
1230 case 1:
1231 x.array [0] &= y.array [0];
1232 break;
1233 default:
1234 abort ();
1235 }
1236 return x;
1237}
40fb9820 1238
c6fb90c8
L		 1239static INLINE i386_cpu_flags
1240cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1241{
c6fb90c8 1242 switch (ARRAY_SIZE (x.array))
40fb9820 1243 {
c6fb90c8
L		 1244 case 3:
1245 x.array [2] |= y.array [2];
1246 case 2:
1247 x.array [1] |= y.array [1];
1248 case 1:
1249 x.array [0] |= y.array [0];
40fb9820
L		 1250 break;
1251 default:
1252 abort ();
1253 }
40fb9820
L		 1254 return x;
1255}
1256
309d3373
JB		 1257static INLINE i386_cpu_flags
1258cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1259{
1260 switch (ARRAY_SIZE (x.array))
1261 {
1262 case 3:
1263 x.array [2] &= ~y.array [2];
1264 case 2:
1265 x.array [1] &= ~y.array [1];
1266 case 1:
1267 x.array [0] &= ~y.array [0];
1268 break;
1269 default:
1270 abort ();
1271 }
1272 return x;
1273}
1274
c0f3af97
L		 1275#define CPU_FLAGS_ARCH_MATCH 0x1
1276#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1277#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1278#define CPU_FLAGS_PCLMUL_MATCH 0x8
1279#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1280
a5ff0eb2 1281#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1282 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1283 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1284#define CPU_FLAGS_PERFECT_MATCH \
1285 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1286
1287/* Return CPU flags match bits. */
3629bb00 1288
40fb9820 1289static int
d3ce72d0 1290cpu_flags_match (const insn_template *t)
40fb9820 1291{
c0f3af97
L		 1292 i386_cpu_flags x = t->cpu_flags;
1293 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1294
1295 x.bitfield.cpu64 = 0;
1296 x.bitfield.cpuno64 = 0;
1297
0dfbf9d7 1298 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1299 {
1300 /* This instruction is available on all archs. */
1301 match |= CPU_FLAGS_32BIT_MATCH;
1302 }
3629bb00
L		 1303 else
1304 {
c0f3af97 1305 /* This instruction is available only on some archs. */
3629bb00
L		 1306 i386_cpu_flags cpu = cpu_arch_flags;
1307
1308 cpu.bitfield.cpu64 = 0;
1309 cpu.bitfield.cpuno64 = 0;
1310 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1311 if (!cpu_flags_all_zero (&cpu))
1312 {
a5ff0eb2
L		 1313 if (x.bitfield.cpuavx)
1314 {
ce2f5b3c 1315 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1316 if (cpu.bitfield.cpuavx)
1317 {
1318 /* Check SSE2AVX. */
1319 if (!t->opcode_modifier.sse2avx|| sse2avx)
1320 {
1321 match |= (CPU_FLAGS_ARCH_MATCH
1322 | CPU_FLAGS_AVX_MATCH);
1323 /* Check AES. */
1324 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1325 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1326 /* Check PCLMUL. */
1327 if (!x.bitfield.cpupclmul
1328 || cpu.bitfield.cpupclmul)
1329 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1330 }
1331 }
1332 else
1333 match |= CPU_FLAGS_ARCH_MATCH;
1334 }
1335 else
c0f3af97
L		 1336 match |= CPU_FLAGS_32BIT_MATCH;
1337 }
3629bb00 1338 }
c0f3af97 1339 return match;
40fb9820
L		 1340}
1341
c6fb90c8
L		 1342static INLINE i386_operand_type
1343operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1344{
c6fb90c8
L		 1345 switch (ARRAY_SIZE (x.array))
1346 {
1347 case 3:
1348 x.array [2] &= y.array [2];
1349 case 2:
1350 x.array [1] &= y.array [1];
1351 case 1:
1352 x.array [0] &= y.array [0];
1353 break;
1354 default:
1355 abort ();
1356 }
1357 return x;
40fb9820
L		 1358}
1359
c6fb90c8
L		 1360static INLINE i386_operand_type
1361operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1362{
c6fb90c8 1363 switch (ARRAY_SIZE (x.array))
40fb9820 1364 {
c6fb90c8
L		 1365 case 3:
1366 x.array [2] |= y.array [2];
1367 case 2:
1368 x.array [1] |= y.array [1];
1369 case 1:
1370 x.array [0] |= y.array [0];
40fb9820
L		 1371 break;
1372 default:
1373 abort ();
1374 }
c6fb90c8
L		 1375 return x;
1376}
40fb9820 1377
c6fb90c8
L		 1378static INLINE i386_operand_type
1379operand_type_xor (i386_operand_type x, i386_operand_type y)
1380{
1381 switch (ARRAY_SIZE (x.array))
1382 {
1383 case 3:
1384 x.array [2] ^= y.array [2];
1385 case 2:
1386 x.array [1] ^= y.array [1];
1387 case 1:
1388 x.array [0] ^= y.array [0];
1389 break;
1390 default:
1391 abort ();
1392 }
40fb9820
L		 1393 return x;
1394}
1395
1396static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1397static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1398static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1399static const i386_operand_type inoutportreg
1400 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1401static const i386_operand_type reg16_inoutportreg
1402 = OPERAND_TYPE_REG16_INOUTPORTREG;
1403static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1404static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1405static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1406static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1407static const i386_operand_type anydisp
1408 = OPERAND_TYPE_ANYDISP;
40fb9820 1409static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1410static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1411static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1412static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1413static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1414static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1415static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1416static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1417static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1418static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1419static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1420
1421enum operand_type
1422{
1423 reg,
40fb9820
L		 1424 imm,
1425 disp,
1426 anymem
1427};
1428
c6fb90c8 1429static INLINE int
40fb9820
L		 1430operand_type_check (i386_operand_type t, enum operand_type c)
1431{
1432 switch (c)
1433 {
1434 case reg:
1435 return (t.bitfield.reg8
1436 || t.bitfield.reg16
1437 || t.bitfield.reg32
1438 || t.bitfield.reg64);
1439
40fb9820
L		 1440 case imm:
1441 return (t.bitfield.imm8
1442 || t.bitfield.imm8s
1443 || t.bitfield.imm16
1444 || t.bitfield.imm32
1445 || t.bitfield.imm32s
1446 || t.bitfield.imm64);
1447
1448 case disp:
1449 return (t.bitfield.disp8
1450 || t.bitfield.disp16
1451 || t.bitfield.disp32
1452 || t.bitfield.disp32s
1453 || t.bitfield.disp64);
1454
1455 case anymem:
1456 return (t.bitfield.disp8
1457 || t.bitfield.disp16
1458 || t.bitfield.disp32
1459 || t.bitfield.disp32s
1460 || t.bitfield.disp64
1461 || t.bitfield.baseindex);
1462
1463 default:
1464 abort ();
1465 }
2cfe26b6
AM		 1466
1467 return 0;
40fb9820
L		 1468}
1469
5c07affc
L		 1470/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1471 operand J for instruction template T. */
1472
1473static INLINE int
d3ce72d0 1474match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1475{
1476 return !((i.types[j].bitfield.byte
1477 && !t->operand_types[j].bitfield.byte)
1478 || (i.types[j].bitfield.word
1479 && !t->operand_types[j].bitfield.word)
1480 || (i.types[j].bitfield.dword
1481 && !t->operand_types[j].bitfield.dword)
1482 || (i.types[j].bitfield.qword
1483 && !t->operand_types[j].bitfield.qword));
1484}
1485
1486/* Return 1 if there is no conflict in any size on operand J for
1487 instruction template T. */
1488
1489static INLINE int
d3ce72d0 1490match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1491{
1492 return (match_reg_size (t, j)
1493 && !((i.types[j].bitfield.unspecified
1494 && !t->operand_types[j].bitfield.unspecified)
1495 || (i.types[j].bitfield.fword
1496 && !t->operand_types[j].bitfield.fword)
1497 || (i.types[j].bitfield.tbyte
1498 && !t->operand_types[j].bitfield.tbyte)
1499 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1500 && !t->operand_types[j].bitfield.xmmword)
1501 || (i.types[j].bitfield.ymmword
1502 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1503}
1504
1505/* Return 1 if there is no size conflict on any operands for
1506 instruction template T. */
1507
1508static INLINE int
d3ce72d0 1509operand_size_match (const insn_template *t)
5c07affc
L		 1510{
1511 unsigned int j;
1512 int match = 1;
1513
1514 /* Don't check jump instructions. */
1515 if (t->opcode_modifier.jump
1516 || t->opcode_modifier.jumpbyte
1517 || t->opcode_modifier.jumpdword
1518 || t->opcode_modifier.jumpintersegment)
1519 return match;
1520
1521 /* Check memory and accumulator operand size. */
1522 for (j = 0; j < i.operands; j++)
1523 {
1524 if (t->operand_types[j].bitfield.anysize)
1525 continue;
1526
1527 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1528 {
1529 match = 0;
1530 break;
1531 }
1532
1533 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1534 {
1535 match = 0;
1536 break;
1537 }
1538 }
1539
1540 if (match
1541 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1542 return match;
1543
1544 /* Check reverse. */
9c2799c2 1545 gas_assert (i.operands == 2);
5c07affc
L		 1546
1547 match = 1;
1548 for (j = 0; j < 2; j++)
1549 {
1550 if (t->operand_types[j].bitfield.acc
1551 && !match_reg_size (t, j ? 0 : 1))
1552 {
1553 match = 0;
1554 break;
1555 }
1556
1557 if (i.types[j].bitfield.mem
1558 && !match_mem_size (t, j ? 0 : 1))
1559 {
1560 match = 0;
1561 break;
1562 }
1563 }
1564
1565 return match;
1566}
1567
c6fb90c8 1568static INLINE int
40fb9820
L		 1569operand_type_match (i386_operand_type overlap,
1570 i386_operand_type given)
1571{
1572 i386_operand_type temp = overlap;
1573
1574 temp.bitfield.jumpabsolute = 0;
7d5e4556 1575 temp.bitfield.unspecified = 0;
5c07affc
L		 1576 temp.bitfield.byte = 0;
1577 temp.bitfield.word = 0;
1578 temp.bitfield.dword = 0;
1579 temp.bitfield.fword = 0;
1580 temp.bitfield.qword = 0;
1581 temp.bitfield.tbyte = 0;
1582 temp.bitfield.xmmword = 0;
c0f3af97 1583 temp.bitfield.ymmword = 0;
0dfbf9d7 1584 if (operand_type_all_zero (&temp))
40fb9820
L		 1585 return 0;
1586
1587 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1588 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1589}
1590
7d5e4556 1591/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1592 unless the expected operand type register overlap is null.
1593 Note that Acc in a template matches every size of reg. */
1594
c6fb90c8 1595static INLINE int
40fb9820
L		 1596operand_type_register_match (i386_operand_type m0,
1597 i386_operand_type g0,
1598 i386_operand_type t0,
1599 i386_operand_type m1,
1600 i386_operand_type g1,
1601 i386_operand_type t1)
1602{
1603 if (!operand_type_check (g0, reg))
1604 return 1;
1605
1606 if (!operand_type_check (g1, reg))
1607 return 1;
1608
1609 if (g0.bitfield.reg8 == g1.bitfield.reg8
1610 && g0.bitfield.reg16 == g1.bitfield.reg16
1611 && g0.bitfield.reg32 == g1.bitfield.reg32
1612 && g0.bitfield.reg64 == g1.bitfield.reg64)
1613 return 1;
1614
1615 if (m0.bitfield.acc)
1616 {
1617 t0.bitfield.reg8 = 1;
1618 t0.bitfield.reg16 = 1;
1619 t0.bitfield.reg32 = 1;
1620 t0.bitfield.reg64 = 1;
1621 }
1622
1623 if (m1.bitfield.acc)
1624 {
1625 t1.bitfield.reg8 = 1;
1626 t1.bitfield.reg16 = 1;
1627 t1.bitfield.reg32 = 1;
1628 t1.bitfield.reg64 = 1;
1629 }
1630
1631 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1632 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1633 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1634 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1635}
1636
252b5132 1637static INLINE unsigned int
40fb9820 1638mode_from_disp_size (i386_operand_type t)
252b5132 1639{
40fb9820
L		 1640 if (t.bitfield.disp8)
1641 return 1;
1642 else if (t.bitfield.disp16
1643 || t.bitfield.disp32
1644 || t.bitfield.disp32s)
1645 return 2;
1646 else
1647 return 0;
252b5132
RH		 1648}
1649
1650static INLINE int
e3bb37b5 1651fits_in_signed_byte (offsetT num)
252b5132
RH		 1652{
1653 return (num >= -128) && (num <= 127);
47926f60 1654}
252b5132
RH		 1655
1656static INLINE int
e3bb37b5 1657fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1658{
1659 return (num & 0xff) == num;
47926f60 1660}
252b5132
RH		 1661
1662static INLINE int
e3bb37b5 1663fits_in_unsigned_word (offsetT num)
252b5132
RH		 1664{
1665 return (num & 0xffff) == num;
47926f60 1666}
252b5132
RH		 1667
1668static INLINE int
e3bb37b5 1669fits_in_signed_word (offsetT num)
252b5132
RH		 1670{
1671 return (-32768 <= num) && (num <= 32767);
47926f60 1672}
2a962e6d 1673
3e73aa7c 1674static INLINE int
e3bb37b5 1675fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1676{
1677#ifndef BFD64
1678 return 1;
1679#else
1680 return (!(((offsetT) -1 << 31) & num)
1681 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1682#endif
1683} /* fits_in_signed_long() */
2a962e6d 1684
3e73aa7c 1685static INLINE int
e3bb37b5 1686fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1687{
1688#ifndef BFD64
1689 return 1;
1690#else
1691 return (num & (((offsetT) 2 << 31) - 1)) == num;
1692#endif
1693} /* fits_in_unsigned_long() */
252b5132 1694
40fb9820 1695static i386_operand_type
e3bb37b5 1696smallest_imm_type (offsetT num)
252b5132 1697{
40fb9820 1698 i386_operand_type t;
7ab9ffdd 1699
0dfbf9d7 1700 operand_type_set (&t, 0);
40fb9820
L		 1701 t.bitfield.imm64 = 1;
1702
1703 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1704 {
1705 /* This code is disabled on the 486 because all the Imm1 forms
1706 in the opcode table are slower on the i486. They're the
1707 versions with the implicitly specified single-position
1708 displacement, which has another syntax if you really want to
1709 use that form. */
40fb9820
L		 1710 t.bitfield.imm1 = 1;
1711 t.bitfield.imm8 = 1;
1712 t.bitfield.imm8s = 1;
1713 t.bitfield.imm16 = 1;
1714 t.bitfield.imm32 = 1;
1715 t.bitfield.imm32s = 1;
1716 }
1717 else if (fits_in_signed_byte (num))
1718 {
1719 t.bitfield.imm8 = 1;
1720 t.bitfield.imm8s = 1;
1721 t.bitfield.imm16 = 1;
1722 t.bitfield.imm32 = 1;
1723 t.bitfield.imm32s = 1;
1724 }
1725 else if (fits_in_unsigned_byte (num))
1726 {
1727 t.bitfield.imm8 = 1;
1728 t.bitfield.imm16 = 1;
1729 t.bitfield.imm32 = 1;
1730 t.bitfield.imm32s = 1;
1731 }
1732 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1733 {
1734 t.bitfield.imm16 = 1;
1735 t.bitfield.imm32 = 1;
1736 t.bitfield.imm32s = 1;
1737 }
1738 else if (fits_in_signed_long (num))
1739 {
1740 t.bitfield.imm32 = 1;
1741 t.bitfield.imm32s = 1;
1742 }
1743 else if (fits_in_unsigned_long (num))
1744 t.bitfield.imm32 = 1;
1745
1746 return t;
47926f60 1747}
252b5132 1748
847f7ad4 1749static offsetT
e3bb37b5 1750offset_in_range (offsetT val, int size)
847f7ad4 1751{
508866be 1752 addressT mask;
ba2adb93 1753
847f7ad4
AM		 1754 switch (size)
1755 {
508866be
L		 1756 case 1: mask = ((addressT) 1 << 8) - 1; break;
1757 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1758 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1759#ifdef BFD64
1760 case 8: mask = ((addressT) 2 << 63) - 1; break;
1761#endif
47926f60 1762 default: abort ();
847f7ad4
AM		 1763 }
1764
9de868bf
L		 1765#ifdef BFD64
1766 /* If BFD64, sign extend val for 32bit address mode. */
1767 if (flag_code != CODE_64BIT
1768 || i.prefix[ADDR_PREFIX])
1769#endif
3e73aa7c
JH		 1770 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1771 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1772
47926f60 1773 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1774 {
1775 char buf1[40], buf2[40];
1776
1777 sprint_value (buf1, val);
1778 sprint_value (buf2, val & mask);
1779 as_warn (_("%s shortened to %s"), buf1, buf2);
1780 }
1781 return val & mask;
1782}
1783
252b5132
RH		 1784/* Returns 0 if attempting to add a prefix where one from the same
1785 class already exists, 1 if non rep/repne added, 2 if rep/repne
1786 added. */
1787static int
e3bb37b5 1788add_prefix (unsigned int prefix)
252b5132
RH		 1789{
1790 int ret = 1;
b1905489 1791 unsigned int q;
252b5132 1792
29b0f896
AM		 1793 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1794 && flag_code == CODE_64BIT)
b1905489 1795 {
161a04f6
L		 1796 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1797 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1798 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1799 ret = 0;
1800 q = REX_PREFIX;
1801 }
3e73aa7c 1802 else
b1905489
JB		 1803 {
1804 switch (prefix)
1805 {
1806 default:
1807 abort ();
1808
1809 case CS_PREFIX_OPCODE:
1810 case DS_PREFIX_OPCODE:
1811 case ES_PREFIX_OPCODE:
1812 case FS_PREFIX_OPCODE:
1813 case GS_PREFIX_OPCODE:
1814 case SS_PREFIX_OPCODE:
1815 q = SEG_PREFIX;
1816 break;
1817
1818 case REPNE_PREFIX_OPCODE:
1819 case REPE_PREFIX_OPCODE:
1820 ret = 2;
1821 /* fall thru */
1822 case LOCK_PREFIX_OPCODE:
1823 q = LOCKREP_PREFIX;
1824 break;
1825
1826 case FWAIT_OPCODE:
1827 q = WAIT_PREFIX;
1828 break;
1829
1830 case ADDR_PREFIX_OPCODE:
1831 q = ADDR_PREFIX;
1832 break;
1833
1834 case DATA_PREFIX_OPCODE:
1835 q = DATA_PREFIX;
1836 break;
1837 }
1838 if (i.prefix[q] != 0)
1839 ret = 0;
1840 }
252b5132 1841
b1905489 1842 if (ret)
252b5132 1843 {
b1905489
JB		 1844 if (!i.prefix[q])
1845 ++i.prefixes;
1846 i.prefix[q] |= prefix;
252b5132 1847 }
b1905489
JB		 1848 else
1849 as_bad (_("same type of prefix used twice"));
252b5132 1850
252b5132
RH		 1851 return ret;
1852}
1853
1854static void
e3bb37b5 1855set_code_flag (int value)
eecb386c 1856{
1e9cc1c2 1857 flag_code = (enum flag_code) value;
40fb9820
L		 1858 if (flag_code == CODE_64BIT)
1859 {
1860 cpu_arch_flags.bitfield.cpu64 = 1;
1861 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1862 }
1863 else
1864 {
1865 cpu_arch_flags.bitfield.cpu64 = 0;
1866 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1867 }
1868 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1869 {
1870 as_bad (_("64bit mode not supported on this CPU."));
1871 }
40fb9820 1872 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1873 {
1874 as_bad (_("32bit mode not supported on this CPU."));
1875 }
eecb386c
AM		 1876 stackop_size = '\0';
1877}
1878
1879static void
e3bb37b5 1880set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1881{
1e9cc1c2 1882 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 1883 if (flag_code != CODE_16BIT)
1884 abort ();
1885 cpu_arch_flags.bitfield.cpu64 = 0;
1886 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1887 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1888}
1889
1890static void
e3bb37b5 1891set_intel_syntax (int syntax_flag)
252b5132
RH		 1892{
1893 /* Find out if register prefixing is specified. */
1894 int ask_naked_reg = 0;
1895
1896 SKIP_WHITESPACE ();
29b0f896 1897 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1898 {
1899 char *string = input_line_pointer;
1900 int e = get_symbol_end ();
1901
47926f60 1902 if (strcmp (string, "prefix") == 0)
252b5132 1903 ask_naked_reg = 1;
47926f60 1904 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1905 ask_naked_reg = -1;
1906 else
d0b47220 1907 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1908 *input_line_pointer = e;
1909 }
1910 demand_empty_rest_of_line ();
c3332e24 1911
252b5132
RH		 1912 intel_syntax = syntax_flag;
1913
1914 if (ask_naked_reg == 0)
f86103b7
AM		 1915 allow_naked_reg = (intel_syntax
1916 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1917 else
1918 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1919
ee86248c 1920 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 1921
e4a3b5a4 1922 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1923 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1924 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1925}
1926
1efbbeb4
L		 1927static void
1928set_intel_mnemonic (int mnemonic_flag)
1929{
e1d4d893 1930 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1931}
1932
db51cc60
L		 1933static void
1934set_allow_index_reg (int flag)
1935{
1936 allow_index_reg = flag;
1937}
1938
cb19c032
L		 1939static void
1940set_sse_check (int dummy ATTRIBUTE_UNUSED)
1941{
1942 SKIP_WHITESPACE ();
1943
1944 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1945 {
1946 char *string = input_line_pointer;
1947 int e = get_symbol_end ();
1948
1949 if (strcmp (string, "none") == 0)
1950 sse_check = sse_check_none;
1951 else if (strcmp (string, "warning") == 0)
1952 sse_check = sse_check_warning;
1953 else if (strcmp (string, "error") == 0)
1954 sse_check = sse_check_error;
1955 else
1956 as_bad (_("bad argument to sse_check directive."));
1957 *input_line_pointer = e;
1958 }
1959 else
1960 as_bad (_("missing argument for sse_check directive"));
1961
1962 demand_empty_rest_of_line ();
1963}
1964
8a9036a4
L		 1965static void
1966check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 1967 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 1968{
1969#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1970 static const char *arch;
1971
1972 /* Intel LIOM is only supported on ELF. */
1973 if (!IS_ELF)
1974 return;
1975
1976 if (!arch)
1977 {
1978 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
1979 use default_arch. */
1980 arch = cpu_arch_name;
1981 if (!arch)
1982 arch = default_arch;
1983 }
1984
3632d14b 1985 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 1986 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 1987 || new_flag.bitfield.cpul1om)
8a9036a4
L		 1988 return;
1989
1990 as_bad (_("`%s' is not supported on `%s'"), name, arch);
1991#endif
1992}
1993
e413e4e9 1994static void
e3bb37b5 1995set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1996{
47926f60 1997 SKIP_WHITESPACE ();
e413e4e9 1998
29b0f896 1999 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2000 {
2001 char *string = input_line_pointer;
2002 int e = get_symbol_end ();
9103f4f4 2003 unsigned int i;
40fb9820 2004 i386_cpu_flags flags;
e413e4e9 2005
9103f4f4 2006 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 2007 {
2008 if (strcmp (string, cpu_arch[i].name) == 0)
2009 {
8a9036a4
L		 2010 check_cpu_arch_compatible (string, cpu_arch[i].flags);
2011
5c6af06e
JB		 2012 if (*string != '.')
2013 {
2014 cpu_arch_name = cpu_arch[i].name;
2015 cpu_sub_arch_name = NULL;
40fb9820
L		 2016 cpu_arch_flags = cpu_arch[i].flags;
2017 if (flag_code == CODE_64BIT)
2018 {
2019 cpu_arch_flags.bitfield.cpu64 = 1;
2020 cpu_arch_flags.bitfield.cpuno64 = 0;
2021 }
2022 else
2023 {
2024 cpu_arch_flags.bitfield.cpu64 = 0;
2025 cpu_arch_flags.bitfield.cpuno64 = 1;
2026 }
ccc9c027 2027 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 2028 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 2029 if (!cpu_arch_tune_set)
2030 {
2031 cpu_arch_tune = cpu_arch_isa;
2032 cpu_arch_tune_flags = cpu_arch_isa_flags;
2033 }
5c6af06e
JB		 2034 break;
2035 }
40fb9820 2036
309d3373
JB		 2037 if (strncmp (string + 1, "no", 2))
2038 flags = cpu_flags_or (cpu_arch_flags,
2039 cpu_arch[i].flags);
2040 else
2041 flags = cpu_flags_and_not (cpu_arch_flags,
2042 cpu_arch[i].flags);
0dfbf9d7 2043 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2044 {
6305a203
L		 2045 if (cpu_sub_arch_name)
2046 {
2047 char *name = cpu_sub_arch_name;
2048 cpu_sub_arch_name = concat (name,
2049 cpu_arch[i].name,
1bf57e9f 2050 (const char *) NULL);
6305a203
L		 2051 free (name);
2052 }
2053 else
2054 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 2055 cpu_arch_flags = flags;
5c6af06e
JB		 2056 }
2057 *input_line_pointer = e;
2058 demand_empty_rest_of_line ();
2059 return;
e413e4e9
AM		 2060 }
2061 }
9103f4f4 2062 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2063 as_bad (_("no such architecture: `%s'"), string);
2064
2065 *input_line_pointer = e;
2066 }
2067 else
2068 as_bad (_("missing cpu architecture"));
2069
fddf5b5b
AM		 2070 no_cond_jump_promotion = 0;
2071 if (*input_line_pointer == ','
29b0f896 2072 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2073 {
2074 char *string = ++input_line_pointer;
2075 int e = get_symbol_end ();
2076
2077 if (strcmp (string, "nojumps") == 0)
2078 no_cond_jump_promotion = 1;
2079 else if (strcmp (string, "jumps") == 0)
2080 ;
2081 else
2082 as_bad (_("no such architecture modifier: `%s'"), string);
2083
2084 *input_line_pointer = e;
2085 }
2086
e413e4e9
AM		 2087 demand_empty_rest_of_line ();
2088}
2089
8a9036a4
L		 2090enum bfd_architecture
2091i386_arch (void)
2092{
3632d14b 2093 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2094 {
2095 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2096 || flag_code != CODE_64BIT)
2097 as_fatal (_("Intel L1OM is 64bit ELF only"));
2098 return bfd_arch_l1om;
2099 }
2100 else
2101 return bfd_arch_i386;
2102}
2103
b9d79e03
JH		 2104unsigned long
2105i386_mach ()
2106{
2107 if (!strcmp (default_arch, "x86_64"))
8a9036a4 2108 {
3632d14b 2109 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2110 {
2111 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2112 as_fatal (_("Intel L1OM is 64bit ELF only"));
2113 return bfd_mach_l1om;
2114 }
2115 else
2116 return bfd_mach_x86_64;
2117 }
b9d79e03
JH		 2118 else if (!strcmp (default_arch, "i386"))
2119 return bfd_mach_i386_i386;
2120 else
2121 as_fatal (_("Unknown architecture"));
2122}
b9d79e03 2123\f
252b5132
RH		 2124void
2125md_begin ()
2126{
2127 const char *hash_err;
2128
47926f60 2129 /* Initialize op_hash hash table. */
252b5132
RH		 2130 op_hash = hash_new ();
2131
2132 {
d3ce72d0 2133 const insn_template *optab;
29b0f896 2134 templates *core_optab;
252b5132 2135
47926f60
KH		 2136 /* Setup for loop. */
2137 optab = i386_optab;
252b5132
RH		 2138 core_optab = (templates *) xmalloc (sizeof (templates));
2139 core_optab->start = optab;
2140
2141 while (1)
2142 {
2143 ++optab;
2144 if (optab->name == NULL
2145 || strcmp (optab->name, (optab - 1)->name) != 0)
2146 {
2147 /* different name --> ship out current template list;
47926f60 2148 add to hash table; & begin anew. */
252b5132
RH		 2149 core_optab->end = optab;
2150 hash_err = hash_insert (op_hash,
2151 (optab - 1)->name,
5a49b8ac 2152 (void *) core_optab);
252b5132
RH		 2153 if (hash_err)
2154 {
252b5132
RH		 2155 as_fatal (_("Internal Error: Can't hash %s: %s"),
2156 (optab - 1)->name,
2157 hash_err);
2158 }
2159 if (optab->name == NULL)
2160 break;
2161 core_optab = (templates *) xmalloc (sizeof (templates));
2162 core_optab->start = optab;
2163 }
2164 }
2165 }
2166
47926f60 2167 /* Initialize reg_hash hash table. */
252b5132
RH		 2168 reg_hash = hash_new ();
2169 {
29b0f896 2170 const reg_entry *regtab;
c3fe08fa 2171 unsigned int regtab_size = i386_regtab_size;
252b5132 2172
c3fe08fa 2173 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2174 {
5a49b8ac 2175 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2176 if (hash_err)
3e73aa7c
JH		 2177 as_fatal (_("Internal Error: Can't hash %s: %s"),
2178 regtab->reg_name,
2179 hash_err);
252b5132
RH		 2180 }
2181 }
2182
47926f60 2183 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2184 {
29b0f896
AM		 2185 int c;
2186 char *p;
252b5132
RH		 2187
2188 for (c = 0; c < 256; c++)
2189 {
3882b010 2190 if (ISDIGIT (c))
252b5132
RH		 2191 {
2192 digit_chars[c] = c;
2193 mnemonic_chars[c] = c;
2194 register_chars[c] = c;
2195 operand_chars[c] = c;
2196 }
3882b010 2197 else if (ISLOWER (c))
252b5132
RH		 2198 {
2199 mnemonic_chars[c] = c;
2200 register_chars[c] = c;
2201 operand_chars[c] = c;
2202 }
3882b010 2203 else if (ISUPPER (c))
252b5132 2204 {
3882b010 2205 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2206 register_chars[c] = mnemonic_chars[c];
2207 operand_chars[c] = c;
2208 }
2209
3882b010 2210 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2211 identifier_chars[c] = c;
2212 else if (c >= 128)
2213 {
2214 identifier_chars[c] = c;
2215 operand_chars[c] = c;
2216 }
2217 }
2218
2219#ifdef LEX_AT
2220 identifier_chars['@'] = '@';
32137342
NC		 2221#endif
2222#ifdef LEX_QM
2223 identifier_chars['?'] = '?';
2224 operand_chars['?'] = '?';
252b5132 2225#endif
252b5132 2226 digit_chars['-'] = '-';
c0f3af97 2227 mnemonic_chars['_'] = '_';
791fe849 2228 mnemonic_chars['-'] = '-';
0003779b 2229 mnemonic_chars['.'] = '.';
252b5132
RH		 2230 identifier_chars['_'] = '_';
2231 identifier_chars['.'] = '.';
2232
2233 for (p = operand_special_chars; *p != '\0'; p++)
2234 operand_chars[(unsigned char) *p] = *p;
2235 }
2236
2237#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2238 if (IS_ELF)
252b5132
RH		 2239 {
2240 record_alignment (text_section, 2);
2241 record_alignment (data_section, 2);
2242 record_alignment (bss_section, 2);
2243 }
2244#endif
a4447b93
RH		 2245
2246 if (flag_code == CODE_64BIT)
2247 {
2248 x86_dwarf2_return_column = 16;
2249 x86_cie_data_alignment = -8;
2250 }
2251 else
2252 {
2253 x86_dwarf2_return_column = 8;
2254 x86_cie_data_alignment = -4;
2255 }
252b5132
RH		 2256}
2257
2258void
e3bb37b5 2259i386_print_statistics (FILE *file)
252b5132
RH		 2260{
2261 hash_print_statistics (file, "i386 opcode", op_hash);
2262 hash_print_statistics (file, "i386 register", reg_hash);
2263}
2264\f
252b5132
RH		 2265#ifdef DEBUG386
2266
ce8a8b2f 2267/* Debugging routines for md_assemble. */
d3ce72d0 2268static void pte (insn_template *);
40fb9820 2269static void pt (i386_operand_type);
e3bb37b5
L		 2270static void pe (expressionS *);
2271static void ps (symbolS *);
252b5132
RH		 2272
2273static void
e3bb37b5 2274pi (char *line, i386_insn *x)
252b5132 2275{
09f131f2 2276 unsigned int i;
252b5132
RH		 2277
2278 fprintf (stdout, "%s: template ", line);
2279 pte (&x->tm);
09f131f2
JH		 2280 fprintf (stdout, " address: base %s index %s scale %x\n",
2281 x->base_reg ? x->base_reg->reg_name : "none",
2282 x->index_reg ? x->index_reg->reg_name : "none",
2283 x->log2_scale_factor);
2284 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2285 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2286 fprintf (stdout, " sib: base %x index %x scale %x\n",
2287 x->sib.base, x->sib.index, x->sib.scale);
2288 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2289 (x->rex & REX_W) != 0,
2290 (x->rex & REX_R) != 0,
2291 (x->rex & REX_X) != 0,
2292 (x->rex & REX_B) != 0);
252b5132
RH		 2293 for (i = 0; i < x->operands; i++)
2294 {
2295 fprintf (stdout, " #%d: ", i + 1);
2296 pt (x->types[i]);
2297 fprintf (stdout, "\n");
40fb9820
L		 2298 if (x->types[i].bitfield.reg8
2299 || x->types[i].bitfield.reg16
2300 || x->types[i].bitfield.reg32
2301 || x->types[i].bitfield.reg64
2302 || x->types[i].bitfield.regmmx
2303 || x->types[i].bitfield.regxmm
c0f3af97 2304 || x->types[i].bitfield.regymm
40fb9820
L		 2305 || x->types[i].bitfield.sreg2
2306 || x->types[i].bitfield.sreg3
2307 || x->types[i].bitfield.control
2308 || x->types[i].bitfield.debug
2309 || x->types[i].bitfield.test)
520dc8e8 2310 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2311 if (operand_type_check (x->types[i], imm))
520dc8e8 2312 pe (x->op[i].imms);
40fb9820 2313 if (operand_type_check (x->types[i], disp))
520dc8e8 2314 pe (x->op[i].disps);
252b5132
RH		 2315 }
2316}
2317
2318static void
d3ce72d0 2319pte (insn_template *t)
252b5132 2320{
09f131f2 2321 unsigned int i;
252b5132 2322 fprintf (stdout, " %d operands ", t->operands);
47926f60 2323 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2324 if (t->extension_opcode != None)
2325 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2326 if (t->opcode_modifier.d)
252b5132 2327 fprintf (stdout, "D");
40fb9820 2328 if (t->opcode_modifier.w)
252b5132
RH		 2329 fprintf (stdout, "W");
2330 fprintf (stdout, "\n");
2331 for (i = 0; i < t->operands; i++)
2332 {
2333 fprintf (stdout, " #%d type ", i + 1);
2334 pt (t->operand_types[i]);
2335 fprintf (stdout, "\n");
2336 }
2337}
2338
2339static void
e3bb37b5 2340pe (expressionS *e)
252b5132 2341{
24eab124 2342 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2343 fprintf (stdout, " add_number %ld (%lx)\n",
2344 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2345 if (e->X_add_symbol)
2346 {
2347 fprintf (stdout, " add_symbol ");
2348 ps (e->X_add_symbol);
2349 fprintf (stdout, "\n");
2350 }
2351 if (e->X_op_symbol)
2352 {
2353 fprintf (stdout, " op_symbol ");
2354 ps (e->X_op_symbol);
2355 fprintf (stdout, "\n");
2356 }
2357}
2358
2359static void
e3bb37b5 2360ps (symbolS *s)
252b5132
RH		 2361{
2362 fprintf (stdout, "%s type %s%s",
2363 S_GET_NAME (s),
2364 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2365 segment_name (S_GET_SEGMENT (s)));
2366}
2367
7b81dfbb 2368static struct type_name
252b5132 2369 {
40fb9820
L		 2370 i386_operand_type mask;
2371 const char *name;
252b5132 2372 }
7b81dfbb 2373const type_names[] =
252b5132 2374{
40fb9820
L		 2375 { OPERAND_TYPE_REG8, "r8" },
2376 { OPERAND_TYPE_REG16, "r16" },
2377 { OPERAND_TYPE_REG32, "r32" },
2378 { OPERAND_TYPE_REG64, "r64" },
2379 { OPERAND_TYPE_IMM8, "i8" },
2380 { OPERAND_TYPE_IMM8, "i8s" },
2381 { OPERAND_TYPE_IMM16, "i16" },
2382 { OPERAND_TYPE_IMM32, "i32" },
2383 { OPERAND_TYPE_IMM32S, "i32s" },
2384 { OPERAND_TYPE_IMM64, "i64" },
2385 { OPERAND_TYPE_IMM1, "i1" },
2386 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2387 { OPERAND_TYPE_DISP8, "d8" },
2388 { OPERAND_TYPE_DISP16, "d16" },
2389 { OPERAND_TYPE_DISP32, "d32" },
2390 { OPERAND_TYPE_DISP32S, "d32s" },
2391 { OPERAND_TYPE_DISP64, "d64" },
2392 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2393 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2394 { OPERAND_TYPE_CONTROL, "control reg" },
2395 { OPERAND_TYPE_TEST, "test reg" },
2396 { OPERAND_TYPE_DEBUG, "debug reg" },
2397 { OPERAND_TYPE_FLOATREG, "FReg" },
2398 { OPERAND_TYPE_FLOATACC, "FAcc" },
2399 { OPERAND_TYPE_SREG2, "SReg2" },
2400 { OPERAND_TYPE_SREG3, "SReg3" },
2401 { OPERAND_TYPE_ACC, "Acc" },
2402 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2403 { OPERAND_TYPE_REGMMX, "rMMX" },
2404 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2405 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2406 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2407};
2408
2409static void
40fb9820 2410pt (i386_operand_type t)
252b5132 2411{
40fb9820 2412 unsigned int j;
c6fb90c8 2413 i386_operand_type a;
252b5132 2414
40fb9820 2415 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2416 {
2417 a = operand_type_and (t, type_names[j].mask);
0349dc08 2418 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2419 fprintf (stdout, "%s, ", type_names[j].name);
2420 }
252b5132
RH		 2421 fflush (stdout);
2422}
2423
2424#endif /* DEBUG386 */
2425\f
252b5132 2426static bfd_reloc_code_real_type
3956db08 2427reloc (unsigned int size,
64e74474
AM		 2428 int pcrel,
2429 int sign,
2430 bfd_reloc_code_real_type other)
252b5132 2431{
47926f60 2432 if (other != NO_RELOC)
3956db08
JB		 2433 {
2434 reloc_howto_type *reloc;
2435
2436 if (size == 8)
2437 switch (other)
2438 {
64e74474
AM		 2439 case BFD_RELOC_X86_64_GOT32:
2440 return BFD_RELOC_X86_64_GOT64;
2441 break;
2442 case BFD_RELOC_X86_64_PLTOFF64:
2443 return BFD_RELOC_X86_64_PLTOFF64;
2444 break;
2445 case BFD_RELOC_X86_64_GOTPC32:
2446 other = BFD_RELOC_X86_64_GOTPC64;
2447 break;
2448 case BFD_RELOC_X86_64_GOTPCREL:
2449 other = BFD_RELOC_X86_64_GOTPCREL64;
2450 break;
2451 case BFD_RELOC_X86_64_TPOFF32:
2452 other = BFD_RELOC_X86_64_TPOFF64;
2453 break;
2454 case BFD_RELOC_X86_64_DTPOFF32:
2455 other = BFD_RELOC_X86_64_DTPOFF64;
2456 break;
2457 default:
2458 break;
3956db08 2459 }
e05278af
JB		 2460
2461 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2462 if (size == 4 && flag_code != CODE_64BIT)
2463 sign = -1;
2464
3956db08
JB		 2465 reloc = bfd_reloc_type_lookup (stdoutput, other);
2466 if (!reloc)
2467 as_bad (_("unknown relocation (%u)"), other);
2468 else if (size != bfd_get_reloc_size (reloc))
2469 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2470 bfd_get_reloc_size (reloc),
2471 size);
2472 else if (pcrel && !reloc->pc_relative)
2473 as_bad (_("non-pc-relative relocation for pc-relative field"));
2474 else if ((reloc->complain_on_overflow == complain_overflow_signed
2475 && !sign)
2476 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2477 && sign > 0))
3956db08
JB		 2478 as_bad (_("relocated field and relocation type differ in signedness"));
2479 else
2480 return other;
2481 return NO_RELOC;
2482 }
252b5132
RH		 2483
2484 if (pcrel)
2485 {
3e73aa7c 2486 if (!sign)
3956db08 2487 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2488 switch (size)
2489 {
2490 case 1: return BFD_RELOC_8_PCREL;
2491 case 2: return BFD_RELOC_16_PCREL;
2492 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2493 case 8: return BFD_RELOC_64_PCREL;
252b5132 2494 }
3956db08 2495 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2496 }
2497 else
2498 {
3956db08 2499 if (sign > 0)
e5cb08ac 2500 switch (size)
3e73aa7c
JH		 2501 {
2502 case 4: return BFD_RELOC_X86_64_32S;
2503 }
2504 else
2505 switch (size)
2506 {
2507 case 1: return BFD_RELOC_8;
2508 case 2: return BFD_RELOC_16;
2509 case 4: return BFD_RELOC_32;
2510 case 8: return BFD_RELOC_64;
2511 }
3956db08
JB		 2512 as_bad (_("cannot do %s %u byte relocation"),
2513 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2514 }
2515
0cc9e1d3 2516 return NO_RELOC;
252b5132
RH		 2517}
2518
47926f60
KH		 2519/* Here we decide which fixups can be adjusted to make them relative to
2520 the beginning of the section instead of the symbol. Basically we need
2521 to make sure that the dynamic relocations are done correctly, so in
2522 some cases we force the original symbol to be used. */
2523
252b5132 2524int
e3bb37b5 2525tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2526{
6d249963 2527#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2528 if (!IS_ELF)
31312f95
AM		 2529 return 1;
2530
a161fe53
AM		 2531 /* Don't adjust pc-relative references to merge sections in 64-bit
2532 mode. */
2533 if (use_rela_relocations
2534 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2535 && fixP->fx_pcrel)
252b5132 2536 return 0;
31312f95 2537
8d01d9a9
AJ		 2538 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2539 and changed later by validate_fix. */
2540 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2541 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2542 return 0;
2543
ce8a8b2f 2544 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2545 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2546 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2547 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2548 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2549 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2550 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2551 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2552 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2553 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2554 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2555 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2556 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2557 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2558 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2559 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2560 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2561 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2562 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2563 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2564 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2565 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2566 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2567 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2568 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2569 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2570 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2571 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2572 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2573 return 0;
31312f95 2574#endif
252b5132
RH		 2575 return 1;
2576}
252b5132 2577
b4cac588 2578static int
e3bb37b5 2579intel_float_operand (const char *mnemonic)
252b5132 2580{
9306ca4a
JB		 2581 /* Note that the value returned is meaningful only for opcodes with (memory)
2582 operands, hence the code here is free to improperly handle opcodes that
2583 have no operands (for better performance and smaller code). */
2584
2585 if (mnemonic[0] != 'f')
2586 return 0; /* non-math */
2587
2588 switch (mnemonic[1])
2589 {
2590 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2591 the fs segment override prefix not currently handled because no
2592 call path can make opcodes without operands get here */
2593 case 'i':
2594 return 2 /* integer op */;
2595 case 'l':
2596 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2597 return 3; /* fldcw/fldenv */
2598 break;
2599 case 'n':
2600 if (mnemonic[2] != 'o' /* fnop */)
2601 return 3; /* non-waiting control op */
2602 break;
2603 case 'r':
2604 if (mnemonic[2] == 's')
2605 return 3; /* frstor/frstpm */
2606 break;
2607 case 's':
2608 if (mnemonic[2] == 'a')
2609 return 3; /* fsave */
2610 if (mnemonic[2] == 't')
2611 {
2612 switch (mnemonic[3])
2613 {
2614 case 'c': /* fstcw */
2615 case 'd': /* fstdw */
2616 case 'e': /* fstenv */
2617 case 's': /* fsts[gw] */
2618 return 3;
2619 }
2620 }
2621 break;
2622 case 'x':
2623 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2624 return 0; /* fxsave/fxrstor are not really math ops */
2625 break;
2626 }
252b5132 2627
9306ca4a 2628 return 1;
252b5132
RH		 2629}
2630
c0f3af97
L		 2631/* Build the VEX prefix. */
2632
2633static void
d3ce72d0 2634build_vex_prefix (const insn_template *t)
c0f3af97
L		 2635{
2636 unsigned int register_specifier;
2637 unsigned int implied_prefix;
2638 unsigned int vector_length;
2639
2640 /* Check register specifier. */
2641 if (i.vex.register_specifier)
2642 {
2643 register_specifier = i.vex.register_specifier->reg_num;
2644 if ((i.vex.register_specifier->reg_flags & RegRex))
2645 register_specifier += 8;
2646 register_specifier = ~register_specifier & 0xf;
2647 }
2648 else
2649 register_specifier = 0xf;
2650
fa99fab2
L		 2651 /* Use 2-byte VEX prefix by swappping destination and source
2652 operand. */
2653 if (!i.swap_operand
2654 && i.operands == i.reg_operands
2655 && i.tm.opcode_modifier.vex0f
2656 && i.tm.opcode_modifier.s
2657 && i.rex == REX_B)
2658 {
2659 unsigned int xchg = i.operands - 1;
2660 union i386_op temp_op;
2661 i386_operand_type temp_type;
2662
2663 temp_type = i.types[xchg];
2664 i.types[xchg] = i.types[0];
2665 i.types[0] = temp_type;
2666 temp_op = i.op[xchg];
2667 i.op[xchg] = i.op[0];
2668 i.op[0] = temp_op;
2669
9c2799c2 2670 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2671
2672 i.rex = REX_R;
2673 xchg = i.rm.regmem;
2674 i.rm.regmem = i.rm.reg;
2675 i.rm.reg = xchg;
2676
2677 /* Use the next insn. */
2678 i.tm = t[1];
2679 }
2680
c0f3af97
L		 2681 vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0;
2682
2683 switch ((i.tm.base_opcode >> 8) & 0xff)
2684 {
2685 case 0:
2686 implied_prefix = 0;
2687 break;
2688 case DATA_PREFIX_OPCODE:
2689 implied_prefix = 1;
2690 break;
2691 case REPE_PREFIX_OPCODE:
2692 implied_prefix = 2;
2693 break;
2694 case REPNE_PREFIX_OPCODE:
2695 implied_prefix = 3;
2696 break;
2697 default:
2698 abort ();
2699 }
2700
2701 /* Use 2-byte VEX prefix if possible. */
2702 if (i.tm.opcode_modifier.vex0f
2703 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2704 {
2705 /* 2-byte VEX prefix. */
2706 unsigned int r;
2707
2708 i.vex.length = 2;
2709 i.vex.bytes[0] = 0xc5;
2710
2711 /* Check the REX.R bit. */
2712 r = (i.rex & REX_R) ? 0 : 1;
2713 i.vex.bytes[1] = (r << 7
2714 | register_specifier << 3
2715 | vector_length << 2
2716 | implied_prefix);
2717 }
2718 else
2719 {
2720 /* 3-byte VEX prefix. */
2721 unsigned int m, w;
2722
2723 if (i.tm.opcode_modifier.vex0f)
2724 m = 0x1;
2725 else if (i.tm.opcode_modifier.vex0f38)
2726 m = 0x2;
2727 else if (i.tm.opcode_modifier.vex0f3a)
2728 m = 0x3;
2729 else
2730 abort ();
2731
2732 i.vex.length = 3;
2733 i.vex.bytes[0] = 0xc4;
2734
2735 /* The high 3 bits of the second VEX byte are 1's compliment
2736 of RXB bits from REX. */
2737 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2738
2739 /* Check the REX.W bit. */
2740 w = (i.rex & REX_W) ? 1 : 0;
2741 if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1)
2742 {
2743 if (w)
2744 abort ();
2745
2746 if (i.tm.opcode_modifier.vexw1)
2747 w = 1;
2748 }
2749
2750 i.vex.bytes[2] = (w << 7
2751 | register_specifier << 3
2752 | vector_length << 2
2753 | implied_prefix);
2754 }
2755}
2756
65da13b5
L		 2757static void
2758process_immext (void)
2759{
2760 expressionS *exp;
2761
2762 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2763 {
1fed0ba1
L		 2764 /* SSE3 Instructions have the fixed operands with an opcode
2765 suffix which is coded in the same place as an 8-bit immediate
2766 field would be. Here we check those operands and remove them
2767 afterwards. */
65da13b5
L		 2768 unsigned int x;
2769
2770 for (x = 0; x < i.operands; x++)
2771 if (i.op[x].regs->reg_num != x)
2772 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2773 register_prefix, i.op[x].regs->reg_name, x + 1,
2774 i.tm.name);
2775
2776 i.operands = 0;
65da13b5
L		 2777 }
2778
c0f3af97 2779 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2780 which is coded in the same place as an 8-bit immediate field
2781 would be. Here we fake an 8-bit immediate operand from the
2782 opcode suffix stored in tm.extension_opcode.
2783
c1e679ec 2784 AVX instructions also use this encoding, for some of
c0f3af97 2785 3 argument instructions. */
65da13b5 2786
9c2799c2 2787 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2788 && (i.operands <= 2
2789 || (i.tm.opcode_modifier.vex
2790 && i.operands <= 4)));
65da13b5
L		 2791
2792 exp = &im_expressions[i.imm_operands++];
2793 i.op[i.operands].imms = exp;
2794 i.types[i.operands] = imm8;
2795 i.operands++;
2796 exp->X_op = O_constant;
2797 exp->X_add_number = i.tm.extension_opcode;
2798 i.tm.extension_opcode = None;
2799}
2800
252b5132
RH		 2801/* This is the guts of the machine-dependent assembler. LINE points to a
2802 machine dependent instruction. This function is supposed to emit
2803 the frags/bytes it assembles to. */
2804
2805void
65da13b5 2806md_assemble (char *line)
252b5132 2807{
40fb9820 2808 unsigned int j;
252b5132 2809 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 2810 const insn_template *t;
252b5132 2811
47926f60 2812 /* Initialize globals. */
252b5132
RH		 2813 memset (&i, '\0', sizeof (i));
2814 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2815 i.reloc[j] = NO_RELOC;
252b5132
RH		 2816 memset (disp_expressions, '\0', sizeof (disp_expressions));
2817 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2818 save_stack_p = save_stack;
252b5132
RH		 2819
2820 /* First parse an instruction mnemonic & call i386_operand for the operands.
2821 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2822 start of a (possibly prefixed) mnemonic. */
252b5132 2823
29b0f896
AM		 2824 line = parse_insn (line, mnemonic);
2825 if (line == NULL)
2826 return;
252b5132 2827
29b0f896 2828 line = parse_operands (line, mnemonic);
ee86248c 2829 this_operand = -1;
29b0f896
AM		 2830 if (line == NULL)
2831 return;
252b5132 2832
29b0f896
AM		 2833 /* Now we've parsed the mnemonic into a set of templates, and have the
2834 operands at hand. */
2835
2836 /* All intel opcodes have reversed operands except for "bound" and
2837 "enter". We also don't reverse intersegment "jmp" and "call"
2838 instructions with 2 immediate operands so that the immediate segment
050dfa73 2839 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2840 if (intel_syntax
2841 && i.operands > 1
29b0f896 2842 && (strcmp (mnemonic, "bound") != 0)
30123838 2843 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2844 && !(operand_type_check (i.types[0], imm)
2845 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2846 swap_operands ();
2847
ec56d5c0
JB		 2848 /* The order of the immediates should be reversed
2849 for 2 immediates extrq and insertq instructions */
2850 if (i.imm_operands == 2
2851 && (strcmp (mnemonic, "extrq") == 0
2852 || strcmp (mnemonic, "insertq") == 0))
2853 swap_2_operands (0, 1);
2854
29b0f896
AM		 2855 if (i.imm_operands)
2856 optimize_imm ();
2857
b300c311
L		 2858 /* Don't optimize displacement for movabs since it only takes 64bit
2859 displacement. */
2860 if (i.disp_operands
2861 && (flag_code != CODE_64BIT
2862 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2863 optimize_disp ();
2864
2865 /* Next, we find a template that matches the given insn,
2866 making sure the overlap of the given operands types is consistent
2867 with the template operand types. */
252b5132 2868
fa99fab2 2869 if (!(t = match_template ()))
29b0f896 2870 return;
252b5132 2871
daf50ae7 2872 if (sse_check != sse_check_none
81f8a913 2873 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2874 && (i.tm.cpu_flags.bitfield.cpusse
2875 || i.tm.cpu_flags.bitfield.cpusse2
2876 || i.tm.cpu_flags.bitfield.cpusse3
2877 || i.tm.cpu_flags.bitfield.cpussse3
2878 || i.tm.cpu_flags.bitfield.cpusse4_1
2879 || i.tm.cpu_flags.bitfield.cpusse4_2))
2880 {
2881 (sse_check == sse_check_warning
2882 ? as_warn
2883 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2884 }
2885
321fd21e
L		 2886 /* Zap movzx and movsx suffix. The suffix has been set from
2887 "word ptr" or "byte ptr" on the source operand in Intel syntax
2888 or extracted from mnemonic in AT&T syntax. But we'll use
2889 the destination register to choose the suffix for encoding. */
2890 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2891 {
321fd21e
L		 2892 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2893 there is no suffix, the default will be byte extension. */
2894 if (i.reg_operands != 2
2895 && !i.suffix
7ab9ffdd 2896 && intel_syntax)
321fd21e
L		 2897 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2898
2899 i.suffix = 0;
cd61ebfe 2900 }
24eab124 2901
40fb9820 2902 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2903 if (!add_prefix (FWAIT_OPCODE))
2904 return;
252b5132 2905
29b0f896 2906 /* Check string instruction segment overrides. */
40fb9820 2907 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2908 {
2909 if (!check_string ())
5dd0794d 2910 return;
fc0763e6 2911 i.disp_operands = 0;
29b0f896 2912 }
5dd0794d 2913
29b0f896
AM		 2914 if (!process_suffix ())
2915 return;
e413e4e9 2916
bc0844ae
L		 2917 /* Update operand types. */
2918 for (j = 0; j < i.operands; j++)
2919 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
2920
29b0f896
AM		 2921 /* Make still unresolved immediate matches conform to size of immediate
2922 given in i.suffix. */
2923 if (!finalize_imm ())
2924 return;
252b5132 2925
40fb9820 2926 if (i.types[0].bitfield.imm1)
29b0f896 2927 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2928
9afe6eb8
L		 2929 /* We only need to check those implicit registers for instructions
2930 with 3 operands or less. */
2931 if (i.operands <= 3)
2932 for (j = 0; j < i.operands; j++)
2933 if (i.types[j].bitfield.inoutportreg
2934 || i.types[j].bitfield.shiftcount
2935 || i.types[j].bitfield.acc
2936 || i.types[j].bitfield.floatacc)
2937 i.reg_operands--;
40fb9820 2938
c0f3af97
L		 2939 /* ImmExt should be processed after SSE2AVX. */
2940 if (!i.tm.opcode_modifier.sse2avx
2941 && i.tm.opcode_modifier.immext)
65da13b5 2942 process_immext ();
252b5132 2943
29b0f896
AM		 2944 /* For insns with operands there are more diddles to do to the opcode. */
2945 if (i.operands)
2946 {
2947 if (!process_operands ())
2948 return;
2949 }
40fb9820 2950 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2951 {
2952 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2953 as_warn (_("translating to `%sp'"), i.tm.name);
2954 }
252b5132 2955
c0f3af97 2956 if (i.tm.opcode_modifier.vex)
fa99fab2 2957 build_vex_prefix (t);
c0f3af97 2958
29b0f896
AM		 2959 /* Handle conversion of 'int $3' --> special int3 insn. */
2960 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2961 {
2962 i.tm.base_opcode = INT3_OPCODE;
2963 i.imm_operands = 0;
2964 }
252b5132 2965
40fb9820
L		 2966 if ((i.tm.opcode_modifier.jump
2967 || i.tm.opcode_modifier.jumpbyte
2968 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2969 && i.op[0].disps->X_op == O_constant)
2970 {
2971 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2972 the absolute address given by the constant. Since ix86 jumps and
2973 calls are pc relative, we need to generate a reloc. */
2974 i.op[0].disps->X_add_symbol = &abs_symbol;
2975 i.op[0].disps->X_op = O_symbol;
2976 }
252b5132 2977
40fb9820 2978 if (i.tm.opcode_modifier.rex64)
161a04f6 2979 i.rex |= REX_W;
252b5132 2980
29b0f896
AM		 2981 /* For 8 bit registers we need an empty rex prefix. Also if the
2982 instruction already has a prefix, we need to convert old
2983 registers to new ones. */
773f551c 2984
40fb9820 2985 if ((i.types[0].bitfield.reg8
29b0f896 2986 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2987 || (i.types[1].bitfield.reg8
29b0f896 2988 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2989 || ((i.types[0].bitfield.reg8
2990 || i.types[1].bitfield.reg8)
29b0f896
AM		 2991 && i.rex != 0))
2992 {
2993 int x;
726c5dcd 2994
29b0f896
AM		 2995 i.rex |= REX_OPCODE;
2996 for (x = 0; x < 2; x++)
2997 {
2998 /* Look for 8 bit operand that uses old registers. */
40fb9820 2999 if (i.types[x].bitfield.reg8
29b0f896 3000 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3001 {
29b0f896
AM		 3002 /* In case it is "hi" register, give up. */
3003 if (i.op[x].regs->reg_num > 3)
a540244d 3004 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3005 "instruction requiring REX prefix."),
a540244d 3006 register_prefix, i.op[x].regs->reg_name);
773f551c 3007
29b0f896
AM		 3008 /* Otherwise it is equivalent to the extended register.
3009 Since the encoding doesn't change this is merely
3010 cosmetic cleanup for debug output. */
3011
3012 i.op[x].regs = i.op[x].regs + 8;
773f551c 3013 }
29b0f896
AM		 3014 }
3015 }
773f551c 3016
7ab9ffdd 3017 if (i.rex != 0)
29b0f896
AM		 3018 add_prefix (REX_OPCODE | i.rex);
3019
3020 /* We are ready to output the insn. */
3021 output_insn ();
3022}
3023
3024static char *
e3bb37b5 3025parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3026{
3027 char *l = line;
3028 char *token_start = l;
3029 char *mnem_p;
5c6af06e 3030 int supported;
d3ce72d0 3031 const insn_template *t;
b6169b20 3032 char *dot_p = NULL;
29b0f896
AM		 3033
3034 /* Non-zero if we found a prefix only acceptable with string insns. */
3035 const char *expecting_string_instruction = NULL;
45288df1 3036
29b0f896
AM		 3037 while (1)
3038 {
3039 mnem_p = mnemonic;
3040 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3041 {
b6169b20
L		 3042 if (*mnem_p == '.')
3043 dot_p = mnem_p;
29b0f896
AM		 3044 mnem_p++;
3045 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3046 {
29b0f896
AM		 3047 as_bad (_("no such instruction: `%s'"), token_start);
3048 return NULL;
3049 }
3050 l++;
3051 }
3052 if (!is_space_char (*l)
3053 && *l != END_OF_INSN
e44823cf
JB		 3054 && (intel_syntax
3055 || (*l != PREFIX_SEPARATOR
3056 && *l != ',')))
29b0f896
AM		 3057 {
3058 as_bad (_("invalid character %s in mnemonic"),
3059 output_invalid (*l));
3060 return NULL;
3061 }
3062 if (token_start == l)
3063 {
e44823cf 3064 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3065 as_bad (_("expecting prefix; got nothing"));
3066 else
3067 as_bad (_("expecting mnemonic; got nothing"));
3068 return NULL;
3069 }
45288df1 3070
29b0f896 3071 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3072 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3073
29b0f896
AM		 3074 if (*l != END_OF_INSN
3075 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3076 && current_templates
40fb9820 3077 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3078 {
c6fb90c8 3079 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3080 {
3081 as_bad ((flag_code != CODE_64BIT
3082 ? _("`%s' is only supported in 64-bit mode")
3083 : _("`%s' is not supported in 64-bit mode")),
3084 current_templates->start->name);
3085 return NULL;
3086 }
29b0f896
AM		 3087 /* If we are in 16-bit mode, do not allow addr16 or data16.
3088 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3089 if ((current_templates->start->opcode_modifier.size16
3090 || current_templates->start->opcode_modifier.size32)
29b0f896 3091 && flag_code != CODE_64BIT
40fb9820 3092 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3093 ^ (flag_code == CODE_16BIT)))
3094 {
3095 as_bad (_("redundant %s prefix"),
3096 current_templates->start->name);
3097 return NULL;
45288df1 3098 }
29b0f896
AM		 3099 /* Add prefix, checking for repeated prefixes. */
3100 switch (add_prefix (current_templates->start->base_opcode))
3101 {
3102 case 0:
3103 return NULL;
3104 case 2:
3105 expecting_string_instruction = current_templates->start->name;
3106 break;
3107 }
3108 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3109 token_start = ++l;
3110 }
3111 else
3112 break;
3113 }
45288df1 3114
30a55f88 3115 if (!current_templates)
b6169b20 3116 {
30a55f88
L		 3117 /* Check if we should swap operand in encoding. */
3118 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3119 i.swap_operand = 1;
3120 else
3121 goto check_suffix;
3122 mnem_p = dot_p;
3123 *dot_p = '\0';
d3ce72d0 3124 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3125 }
3126
29b0f896
AM		 3127 if (!current_templates)
3128 {
b6169b20 3129check_suffix:
29b0f896
AM		 3130 /* See if we can get a match by trimming off a suffix. */
3131 switch (mnem_p[-1])
3132 {
3133 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3134 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3135 i.suffix = SHORT_MNEM_SUFFIX;
3136 else
29b0f896
AM		 3137 case BYTE_MNEM_SUFFIX:
3138 case QWORD_MNEM_SUFFIX:
3139 i.suffix = mnem_p[-1];
3140 mnem_p[-1] = '\0';
d3ce72d0
NC		 3141 current_templates = (const templates *) hash_find (op_hash,
3142 mnemonic);
29b0f896
AM		 3143 break;
3144 case SHORT_MNEM_SUFFIX:
3145 case LONG_MNEM_SUFFIX:
3146 if (!intel_syntax)
3147 {
3148 i.suffix = mnem_p[-1];
3149 mnem_p[-1] = '\0';
d3ce72d0
NC		 3150 current_templates = (const templates *) hash_find (op_hash,
3151 mnemonic);
29b0f896
AM		 3152 }
3153 break;
252b5132 3154
29b0f896
AM		 3155 /* Intel Syntax. */
3156 case 'd':
3157 if (intel_syntax)
3158 {
9306ca4a 3159 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3160 i.suffix = SHORT_MNEM_SUFFIX;
3161 else
3162 i.suffix = LONG_MNEM_SUFFIX;
3163 mnem_p[-1] = '\0';
d3ce72d0
NC		 3164 current_templates = (const templates *) hash_find (op_hash,
3165 mnemonic);
29b0f896
AM		 3166 }
3167 break;
3168 }
3169 if (!current_templates)
3170 {
3171 as_bad (_("no such instruction: `%s'"), token_start);
3172 return NULL;
3173 }
3174 }
252b5132 3175
40fb9820
L		 3176 if (current_templates->start->opcode_modifier.jump
3177 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3178 {
3179 /* Check for a branch hint. We allow ",pt" and ",pn" for
3180 predict taken and predict not taken respectively.
3181 I'm not sure that branch hints actually do anything on loop
3182 and jcxz insns (JumpByte) for current Pentium4 chips. They
3183 may work in the future and it doesn't hurt to accept them
3184 now. */
3185 if (l[0] == ',' && l[1] == 'p')
3186 {
3187 if (l[2] == 't')
3188 {
3189 if (!add_prefix (DS_PREFIX_OPCODE))
3190 return NULL;
3191 l += 3;
3192 }
3193 else if (l[2] == 'n')
3194 {
3195 if (!add_prefix (CS_PREFIX_OPCODE))
3196 return NULL;
3197 l += 3;
3198 }
3199 }
3200 }
3201 /* Any other comma loses. */
3202 if (*l == ',')
3203 {
3204 as_bad (_("invalid character %s in mnemonic"),
3205 output_invalid (*l));
3206 return NULL;
3207 }
252b5132 3208
29b0f896 3209 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3210 supported = 0;
3211 for (t = current_templates->start; t < current_templates->end; ++t)
3212 {
c0f3af97
L		 3213 supported |= cpu_flags_match (t);
3214 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3215 goto skip;
5c6af06e 3216 }
3629bb00 3217
c0f3af97 3218 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3219 {
3220 as_bad (flag_code == CODE_64BIT
3221 ? _("`%s' is not supported in 64-bit mode")
3222 : _("`%s' is only supported in 64-bit mode"),
3223 current_templates->start->name);
3224 return NULL;
3225 }
c0f3af97 3226 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3227 {
3629bb00 3228 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3229 current_templates->start->name,
41aacd83 3230 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3231 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3232 return NULL;
29b0f896 3233 }
3629bb00
L		 3234
3235skip:
3236 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3237 && (flag_code != CODE_16BIT))
29b0f896
AM		 3238 {
3239 as_warn (_("use .code16 to ensure correct addressing mode"));
3240 }
252b5132 3241
29b0f896 3242 /* Check for rep/repne without a string instruction. */
f41bbced 3243 if (expecting_string_instruction)
29b0f896 3244 {
f41bbced
JB		 3245 static templates override;
3246
3247 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3248 if (t->opcode_modifier.isstring)
f41bbced
JB		 3249 break;
3250 if (t >= current_templates->end)
3251 {
3252 as_bad (_("expecting string instruction after `%s'"),
64e74474 3253 expecting_string_instruction);
f41bbced
JB		 3254 return NULL;
3255 }
3256 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3257 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3258 break;
3259 override.end = t;
3260 current_templates = &override;
29b0f896 3261 }
252b5132 3262
29b0f896
AM		 3263 return l;
3264}
252b5132 3265
29b0f896 3266static char *
e3bb37b5 3267parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3268{
3269 char *token_start;
3138f287 3270
29b0f896
AM		 3271 /* 1 if operand is pending after ','. */
3272 unsigned int expecting_operand = 0;
252b5132 3273
29b0f896
AM		 3274 /* Non-zero if operand parens not balanced. */
3275 unsigned int paren_not_balanced;
3276
3277 while (*l != END_OF_INSN)
3278 {
3279 /* Skip optional white space before operand. */
3280 if (is_space_char (*l))
3281 ++l;
3282 if (!is_operand_char (*l) && *l != END_OF_INSN)
3283 {
3284 as_bad (_("invalid character %s before operand %d"),
3285 output_invalid (*l),
3286 i.operands + 1);
3287 return NULL;
3288 }
3289 token_start = l; /* after white space */
3290 paren_not_balanced = 0;
3291 while (paren_not_balanced || *l != ',')
3292 {
3293 if (*l == END_OF_INSN)
3294 {
3295 if (paren_not_balanced)
3296 {
3297 if (!intel_syntax)
3298 as_bad (_("unbalanced parenthesis in operand %d."),
3299 i.operands + 1);
3300 else
3301 as_bad (_("unbalanced brackets in operand %d."),
3302 i.operands + 1);
3303 return NULL;
3304 }
3305 else
3306 break; /* we are done */
3307 }
3308 else if (!is_operand_char (*l) && !is_space_char (*l))
3309 {
3310 as_bad (_("invalid character %s in operand %d"),
3311 output_invalid (*l),
3312 i.operands + 1);
3313 return NULL;
3314 }
3315 if (!intel_syntax)
3316 {
3317 if (*l == '(')
3318 ++paren_not_balanced;
3319 if (*l == ')')
3320 --paren_not_balanced;
3321 }
3322 else
3323 {
3324 if (*l == '[')
3325 ++paren_not_balanced;
3326 if (*l == ']')
3327 --paren_not_balanced;
3328 }
3329 l++;
3330 }
3331 if (l != token_start)
3332 { /* Yes, we've read in another operand. */
3333 unsigned int operand_ok;
3334 this_operand = i.operands++;
7d5e4556 3335 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3336 if (i.operands > MAX_OPERANDS)
3337 {
3338 as_bad (_("spurious operands; (%d operands/instruction max)"),
3339 MAX_OPERANDS);
3340 return NULL;
3341 }
3342 /* Now parse operand adding info to 'i' as we go along. */
3343 END_STRING_AND_SAVE (l);
3344
3345 if (intel_syntax)
3346 operand_ok =
3347 i386_intel_operand (token_start,
3348 intel_float_operand (mnemonic));
3349 else
a7619375 3350 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3351
3352 RESTORE_END_STRING (l);
3353 if (!operand_ok)
3354 return NULL;
3355 }
3356 else
3357 {
3358 if (expecting_operand)
3359 {
3360 expecting_operand_after_comma:
3361 as_bad (_("expecting operand after ','; got nothing"));
3362 return NULL;
3363 }
3364 if (*l == ',')
3365 {
3366 as_bad (_("expecting operand before ','; got nothing"));
3367 return NULL;
3368 }
3369 }
7f3f1ea2 3370
29b0f896
AM		 3371 /* Now *l must be either ',' or END_OF_INSN. */
3372 if (*l == ',')
3373 {
3374 if (*++l == END_OF_INSN)
3375 {
3376 /* Just skip it, if it's \n complain. */
3377 goto expecting_operand_after_comma;
3378 }
3379 expecting_operand = 1;
3380 }
3381 }
3382 return l;
3383}
7f3f1ea2 3384
050dfa73 3385static void
4d456e3d 3386swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3387{
3388 union i386_op temp_op;
40fb9820 3389 i386_operand_type temp_type;
050dfa73 3390 enum bfd_reloc_code_real temp_reloc;
4eed87de 3391
050dfa73
MM		 3392 temp_type = i.types[xchg2];
3393 i.types[xchg2] = i.types[xchg1];
3394 i.types[xchg1] = temp_type;
3395 temp_op = i.op[xchg2];
3396 i.op[xchg2] = i.op[xchg1];
3397 i.op[xchg1] = temp_op;
3398 temp_reloc = i.reloc[xchg2];
3399 i.reloc[xchg2] = i.reloc[xchg1];
3400 i.reloc[xchg1] = temp_reloc;
3401}
3402
29b0f896 3403static void
e3bb37b5 3404swap_operands (void)
29b0f896 3405{
b7c61d9a 3406 switch (i.operands)
050dfa73 3407 {
c0f3af97 3408 case 5:
b7c61d9a 3409 case 4:
4d456e3d 3410 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3411 case 3:
3412 case 2:
4d456e3d 3413 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3414 break;
3415 default:
3416 abort ();
29b0f896 3417 }
29b0f896
AM		 3418
3419 if (i.mem_operands == 2)
3420 {
3421 const seg_entry *temp_seg;
3422 temp_seg = i.seg[0];
3423 i.seg[0] = i.seg[1];
3424 i.seg[1] = temp_seg;
3425 }
3426}
252b5132 3427
29b0f896
AM		 3428/* Try to ensure constant immediates are represented in the smallest
3429 opcode possible. */
3430static void
e3bb37b5 3431optimize_imm (void)
29b0f896
AM		 3432{
3433 char guess_suffix = 0;
3434 int op;
252b5132 3435
29b0f896
AM		 3436 if (i.suffix)
3437 guess_suffix = i.suffix;
3438 else if (i.reg_operands)
3439 {
3440 /* Figure out a suffix from the last register operand specified.
3441 We can't do this properly yet, ie. excluding InOutPortReg,
3442 but the following works for instructions with immediates.
3443 In any case, we can't set i.suffix yet. */
3444 for (op = i.operands; --op >= 0;)
40fb9820 3445 if (i.types[op].bitfield.reg8)
7ab9ffdd 3446 {
40fb9820
L		 3447 guess_suffix = BYTE_MNEM_SUFFIX;
3448 break;
3449 }
3450 else if (i.types[op].bitfield.reg16)
252b5132 3451 {
40fb9820
L		 3452 guess_suffix = WORD_MNEM_SUFFIX;
3453 break;
3454 }
3455 else if (i.types[op].bitfield.reg32)
3456 {
3457 guess_suffix = LONG_MNEM_SUFFIX;
3458 break;
3459 }
3460 else if (i.types[op].bitfield.reg64)
3461 {
3462 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3463 break;
252b5132 3464 }
29b0f896
AM		 3465 }
3466 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3467 guess_suffix = WORD_MNEM_SUFFIX;
3468
3469 for (op = i.operands; --op >= 0;)
40fb9820 3470 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3471 {
3472 switch (i.op[op].imms->X_op)
252b5132 3473 {
29b0f896
AM		 3474 case O_constant:
3475 /* If a suffix is given, this operand may be shortened. */
3476 switch (guess_suffix)
252b5132 3477 {
29b0f896 3478 case LONG_MNEM_SUFFIX:
40fb9820
L		 3479 i.types[op].bitfield.imm32 = 1;
3480 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3481 break;
3482 case WORD_MNEM_SUFFIX:
40fb9820
L		 3483 i.types[op].bitfield.imm16 = 1;
3484 i.types[op].bitfield.imm32 = 1;
3485 i.types[op].bitfield.imm32s = 1;
3486 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3487 break;
3488 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3489 i.types[op].bitfield.imm8 = 1;
3490 i.types[op].bitfield.imm8s = 1;
3491 i.types[op].bitfield.imm16 = 1;
3492 i.types[op].bitfield.imm32 = 1;
3493 i.types[op].bitfield.imm32s = 1;
3494 i.types[op].bitfield.imm64 = 1;
29b0f896 3495 break;
252b5132 3496 }
252b5132 3497
29b0f896
AM		 3498 /* If this operand is at most 16 bits, convert it
3499 to a signed 16 bit number before trying to see
3500 whether it will fit in an even smaller size.
3501 This allows a 16-bit operand such as $0xffe0 to
3502 be recognised as within Imm8S range. */
40fb9820 3503 if ((i.types[op].bitfield.imm16)
29b0f896 3504 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3505 {
29b0f896
AM		 3506 i.op[op].imms->X_add_number =
3507 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3508 }
40fb9820 3509 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3510 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3511 == 0))
3512 {
3513 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3514 ^ ((offsetT) 1 << 31))
3515 - ((offsetT) 1 << 31));
3516 }
40fb9820 3517 i.types[op]
c6fb90c8
L		 3518 = operand_type_or (i.types[op],
3519 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3520
29b0f896
AM		 3521 /* We must avoid matching of Imm32 templates when 64bit
3522 only immediate is available. */
3523 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3524 i.types[op].bitfield.imm32 = 0;
29b0f896 3525 break;
252b5132 3526
29b0f896
AM		 3527 case O_absent:
3528 case O_register:
3529 abort ();
3530
3531 /* Symbols and expressions. */
3532 default:
9cd96992
JB		 3533 /* Convert symbolic operand to proper sizes for matching, but don't
3534 prevent matching a set of insns that only supports sizes other
3535 than those matching the insn suffix. */
3536 {
40fb9820 3537 i386_operand_type mask, allowed;
d3ce72d0 3538 const insn_template *t;
9cd96992 3539
0dfbf9d7
L		 3540 operand_type_set (&mask, 0);
3541 operand_type_set (&allowed, 0);
40fb9820 3542
4eed87de
AM		 3543 for (t = current_templates->start;
3544 t < current_templates->end;
3545 ++t)
c6fb90c8
L		 3546 allowed = operand_type_or (allowed,
3547 t->operand_types[op]);
9cd96992
JB		 3548 switch (guess_suffix)
3549 {
3550 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3551 mask.bitfield.imm64 = 1;
3552 mask.bitfield.imm32s = 1;
9cd96992
JB		 3553 break;
3554 case LONG_MNEM_SUFFIX:
40fb9820 3555 mask.bitfield.imm32 = 1;
9cd96992
JB		 3556 break;
3557 case WORD_MNEM_SUFFIX:
40fb9820 3558 mask.bitfield.imm16 = 1;
9cd96992
JB		 3559 break;
3560 case BYTE_MNEM_SUFFIX:
40fb9820 3561 mask.bitfield.imm8 = 1;
9cd96992
JB		 3562 break;
3563 default:
9cd96992
JB		 3564 break;
3565 }
c6fb90c8 3566 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3567 if (!operand_type_all_zero (&allowed))
c6fb90c8 3568 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3569 }
29b0f896 3570 break;
252b5132 3571 }
29b0f896
AM		 3572 }
3573}
47926f60 3574
29b0f896
AM		 3575/* Try to use the smallest displacement type too. */
3576static void
e3bb37b5 3577optimize_disp (void)
29b0f896
AM		 3578{
3579 int op;
3e73aa7c 3580
29b0f896 3581 for (op = i.operands; --op >= 0;)
40fb9820 3582 if (operand_type_check (i.types[op], disp))
252b5132 3583 {
b300c311 3584 if (i.op[op].disps->X_op == O_constant)
252b5132 3585 {
b300c311 3586 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3587
40fb9820 3588 if (i.types[op].bitfield.disp16
b300c311
L		 3589 && (disp & ~(offsetT) 0xffff) == 0)
3590 {
3591 /* If this operand is at most 16 bits, convert
3592 to a signed 16 bit number and don't use 64bit
3593 displacement. */
3594 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3595 i.types[op].bitfield.disp64 = 0;
b300c311 3596 }
40fb9820 3597 if (i.types[op].bitfield.disp32
b300c311
L		 3598 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3599 {
3600 /* If this operand is at most 32 bits, convert
3601 to a signed 32 bit number and don't use 64bit
3602 displacement. */
3603 disp &= (((offsetT) 2 << 31) - 1);
3604 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3605 i.types[op].bitfield.disp64 = 0;
b300c311 3606 }
40fb9820 3607 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3608 {
40fb9820
L		 3609 i.types[op].bitfield.disp8 = 0;
3610 i.types[op].bitfield.disp16 = 0;
3611 i.types[op].bitfield.disp32 = 0;
3612 i.types[op].bitfield.disp32s = 0;
3613 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3614 i.op[op].disps = 0;
3615 i.disp_operands--;
3616 }
3617 else if (flag_code == CODE_64BIT)
3618 {
3619 if (fits_in_signed_long (disp))
28a9d8f5 3620 {
40fb9820
L		 3621 i.types[op].bitfield.disp64 = 0;
3622 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3623 }
0e1147d9
L		 3624 if (i.prefix[ADDR_PREFIX]
3625 && fits_in_unsigned_long (disp))
40fb9820 3626 i.types[op].bitfield.disp32 = 1;
b300c311 3627 }
40fb9820
L		 3628 if ((i.types[op].bitfield.disp32
3629 || i.types[op].bitfield.disp32s
3630 || i.types[op].bitfield.disp16)
b300c311 3631 && fits_in_signed_byte (disp))
40fb9820 3632 i.types[op].bitfield.disp8 = 1;
252b5132 3633 }
67a4f2b7
AO		 3634 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3635 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3636 {
3637 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3638 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3639 i.types[op].bitfield.disp8 = 0;
3640 i.types[op].bitfield.disp16 = 0;
3641 i.types[op].bitfield.disp32 = 0;
3642 i.types[op].bitfield.disp32s = 0;
3643 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3644 }
3645 else
b300c311 3646 /* We only support 64bit displacement on constants. */
40fb9820 3647 i.types[op].bitfield.disp64 = 0;
252b5132 3648 }
29b0f896
AM		 3649}
3650
d3ce72d0 3651static const insn_template *
e3bb37b5 3652match_template (void)
29b0f896
AM		 3653{
3654 /* Points to template once we've found it. */
d3ce72d0 3655 const insn_template *t;
40fb9820 3656 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3657 i386_operand_type overlap4;
29b0f896 3658 unsigned int found_reverse_match;
40fb9820
L		 3659 i386_opcode_modifier suffix_check;
3660 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3661 int addr_prefix_disp;
a5c311ca 3662 unsigned int j;
3629bb00 3663 unsigned int found_cpu_match;
45664ddb 3664 unsigned int check_register;
29b0f896 3665
c0f3af97
L		 3666#if MAX_OPERANDS != 5
3667# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3668#endif
3669
29b0f896 3670 found_reverse_match = 0;
539e75ad 3671 addr_prefix_disp = -1;
40fb9820
L		 3672
3673 memset (&suffix_check, 0, sizeof (suffix_check));
3674 if (i.suffix == BYTE_MNEM_SUFFIX)
3675 suffix_check.no_bsuf = 1;
3676 else if (i.suffix == WORD_MNEM_SUFFIX)
3677 suffix_check.no_wsuf = 1;
3678 else if (i.suffix == SHORT_MNEM_SUFFIX)
3679 suffix_check.no_ssuf = 1;
3680 else if (i.suffix == LONG_MNEM_SUFFIX)
3681 suffix_check.no_lsuf = 1;
3682 else if (i.suffix == QWORD_MNEM_SUFFIX)
3683 suffix_check.no_qsuf = 1;
3684 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3685 suffix_check.no_ldsuf = 1;
29b0f896 3686
45aa61fe 3687 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3688 {
539e75ad
L		 3689 addr_prefix_disp = -1;
3690
29b0f896
AM		 3691 /* Must have right number of operands. */
3692 if (i.operands != t->operands)
3693 continue;
3694
50aecf8c 3695 /* Check processor support. */
c0f3af97
L		 3696 found_cpu_match = (cpu_flags_match (t)
3697 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3698 if (!found_cpu_match)
3699 continue;
3700
e1d4d893
L		 3701 /* Check old gcc support. */
3702 if (!old_gcc && t->opcode_modifier.oldgcc)
3703 continue;
3704
3705 /* Check AT&T mnemonic. */
3706 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3707 continue;
3708
5c07affc
L		 3709 /* Check AT&T syntax Intel syntax. */
3710 if ((intel_syntax && t->opcode_modifier.attsyntax)
3711 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3712 continue;
3713
20592a94 3714 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3715 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3716 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3717 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3718 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3719 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3720 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3721 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3722 continue;
3723
5c07affc 3724 if (!operand_size_match (t))
7d5e4556 3725 continue;
539e75ad 3726
5c07affc
L		 3727 for (j = 0; j < MAX_OPERANDS; j++)
3728 operand_types[j] = t->operand_types[j];
3729
45aa61fe
AM		 3730 /* In general, don't allow 64-bit operands in 32-bit mode. */
3731 if (i.suffix == QWORD_MNEM_SUFFIX
3732 && flag_code != CODE_64BIT
3733 && (intel_syntax
40fb9820 3734 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3735 && !intel_float_operand (t->name))
3736 : intel_float_operand (t->name) != 2)
40fb9820 3737 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3738 && !operand_types[0].bitfield.regxmm
3739 && !operand_types[0].bitfield.regymm)
40fb9820 3740 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3741 && !!operand_types[t->operands > 1].bitfield.regxmm
3742 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3743 && (t->base_opcode != 0x0fc7
3744 || t->extension_opcode != 1 /* cmpxchg8b */))
3745 continue;
3746
192dc9c6
JB		 3747 /* In general, don't allow 32-bit operands on pre-386. */
3748 else if (i.suffix == LONG_MNEM_SUFFIX
3749 && !cpu_arch_flags.bitfield.cpui386
3750 && (intel_syntax
3751 ? (!t->opcode_modifier.ignoresize
3752 && !intel_float_operand (t->name))
3753 : intel_float_operand (t->name) != 2)
3754 && ((!operand_types[0].bitfield.regmmx
3755 && !operand_types[0].bitfield.regxmm)
3756 || (!operand_types[t->operands > 1].bitfield.regmmx
3757 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3758 continue;
3759
29b0f896 3760 /* Do not verify operands when there are none. */
50aecf8c 3761 else
29b0f896 3762 {
c6fb90c8 3763 if (!t->operands)
2dbab7d5
L		 3764 /* We've found a match; break out of loop. */
3765 break;
29b0f896 3766 }
252b5132 3767
539e75ad
L		 3768 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3769 into Disp32/Disp16/Disp32 operand. */
3770 if (i.prefix[ADDR_PREFIX] != 0)
3771 {
40fb9820 3772 /* There should be only one Disp operand. */
539e75ad
L		 3773 switch (flag_code)
3774 {
3775 case CODE_16BIT:
40fb9820
L		 3776 for (j = 0; j < MAX_OPERANDS; j++)
3777 {
3778 if (operand_types[j].bitfield.disp16)
3779 {
3780 addr_prefix_disp = j;
3781 operand_types[j].bitfield.disp32 = 1;
3782 operand_types[j].bitfield.disp16 = 0;
3783 break;
3784 }
3785 }
539e75ad
L		 3786 break;
3787 case CODE_32BIT:
40fb9820
L		 3788 for (j = 0; j < MAX_OPERANDS; j++)
3789 {
3790 if (operand_types[j].bitfield.disp32)
3791 {
3792 addr_prefix_disp = j;
3793 operand_types[j].bitfield.disp32 = 0;
3794 operand_types[j].bitfield.disp16 = 1;
3795 break;
3796 }
3797 }
539e75ad
L		 3798 break;
3799 case CODE_64BIT:
40fb9820
L		 3800 for (j = 0; j < MAX_OPERANDS; j++)
3801 {
3802 if (operand_types[j].bitfield.disp64)
3803 {
3804 addr_prefix_disp = j;
3805 operand_types[j].bitfield.disp64 = 0;
3806 operand_types[j].bitfield.disp32 = 1;
3807 break;
3808 }
3809 }
539e75ad
L		 3810 break;
3811 }
539e75ad
L		 3812 }
3813
45664ddb
L		 3814 /* We check register size only if size of operands can be
3815 encoded the canonical way. */
3816 check_register = t->opcode_modifier.w;
c6fb90c8 3817 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3818 switch (t->operands)
3819 {
3820 case 1:
40fb9820 3821 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3822 continue;
3823 break;
3824 case 2:
8b38ad71
L		 3825 /* xchg %eax, %eax is a special case. It is an aliase for nop
3826 only in 32bit mode and we can use opcode 0x90. In 64bit
3827 mode, we can't use 0x90 for xchg %eax, %eax since it should
3828 zero-extend %eax to %rax. */
3829 if (flag_code == CODE_64BIT
3830 && t->base_opcode == 0x90
0dfbf9d7
L		 3831 && operand_type_equal (&i.types [0], &acc32)
3832 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3833 continue;
b6169b20
L		 3834 if (i.swap_operand)
3835 {
3836 /* If we swap operand in encoding, we either match
3837 the next one or reverse direction of operands. */
3838 if (t->opcode_modifier.s)
3839 continue;
3840 else if (t->opcode_modifier.d)
3841 goto check_reverse;
3842 }
3843
29b0f896 3844 case 3:
fa99fab2
L		 3845 /* If we swap operand in encoding, we match the next one. */
3846 if (i.swap_operand && t->opcode_modifier.s)
3847 continue;
f48ff2ae 3848 case 4:
c0f3af97 3849 case 5:
c6fb90c8 3850 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3851 if (!operand_type_match (overlap0, i.types[0])
3852 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3853 || (check_register
3854 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3855 operand_types[0],
3856 overlap1, i.types[1],
3857 operand_types[1])))
29b0f896
AM		 3858 {
3859 /* Check if other direction is valid ... */
40fb9820 3860 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3861 continue;
3862
b6169b20 3863check_reverse:
29b0f896 3864 /* Try reversing direction of operands. */
c6fb90c8
L		 3865 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3866 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3867 if (!operand_type_match (overlap0, i.types[0])
3868 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3869 || (check_register
3870 && !operand_type_register_match (overlap0,
3871 i.types[0],
3872 operand_types[1],
3873 overlap1,
3874 i.types[1],
3875 operand_types[0])))
29b0f896
AM		 3876 {
3877 /* Does not match either direction. */
3878 continue;
3879 }
3880 /* found_reverse_match holds which of D or FloatDR
3881 we've found. */
40fb9820 3882 if (t->opcode_modifier.d)
8a2ed489 3883 found_reverse_match = Opcode_D;
40fb9820 3884 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3885 found_reverse_match = Opcode_FloatD;
3886 else
3887 found_reverse_match = 0;
40fb9820 3888 if (t->opcode_modifier.floatr)
8a2ed489 3889 found_reverse_match |= Opcode_FloatR;
29b0f896 3890 }
f48ff2ae 3891 else
29b0f896 3892 {
f48ff2ae 3893 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3894 switch (t->operands)
3895 {
c0f3af97
L		 3896 case 5:
3897 overlap4 = operand_type_and (i.types[4],
3898 operand_types[4]);
d1cbb4db 3899 case 4:
c6fb90c8
L		 3900 overlap3 = operand_type_and (i.types[3],
3901 operand_types[3]);
d1cbb4db 3902 case 3:
c6fb90c8
L		 3903 overlap2 = operand_type_and (i.types[2],
3904 operand_types[2]);
d1cbb4db
L		 3905 break;
3906 }
29b0f896 3907
f48ff2ae
L		 3908 switch (t->operands)
3909 {
c0f3af97
L		 3910 case 5:
3911 if (!operand_type_match (overlap4, i.types[4])
3912 || !operand_type_register_match (overlap3,
3913 i.types[3],
3914 operand_types[3],
3915 overlap4,
3916 i.types[4],
3917 operand_types[4]))
3918 continue;
f48ff2ae 3919 case 4:
40fb9820 3920 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3921 || (check_register
3922 && !operand_type_register_match (overlap2,
3923 i.types[2],
3924 operand_types[2],
3925 overlap3,
3926 i.types[3],
3927 operand_types[3])))
f48ff2ae
L		 3928 continue;
3929 case 3:
3930 /* Here we make use of the fact that there are no
3931 reverse match 3 operand instructions, and all 3
3932 operand instructions only need to be checked for
3933 register consistency between operands 2 and 3. */
40fb9820 3934 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3935 || (check_register
3936 && !operand_type_register_match (overlap1,
3937 i.types[1],
3938 operand_types[1],
3939 overlap2,
3940 i.types[2],
3941 operand_types[2])))
f48ff2ae
L		 3942 continue;
3943 break;
3944 }
29b0f896 3945 }
f48ff2ae 3946 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3947 slip through to break. */
3948 }
3629bb00 3949 if (!found_cpu_match)
29b0f896
AM		 3950 {
3951 found_reverse_match = 0;
3952 continue;
3953 }
c0f3af97 3954
29b0f896
AM		 3955 /* We've found a match; break out of loop. */
3956 break;
3957 }
3958
3959 if (t == current_templates->end)
3960 {
3961 /* We found no match. */
95f283e8
L		 3962 if (intel_syntax)
3963 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3964 current_templates->start->name);
3965 else
3966 as_bad (_("suffix or operands invalid for `%s'"),
3967 current_templates->start->name);
fa99fab2 3968 return NULL;
29b0f896 3969 }
252b5132 3970
29b0f896
AM		 3971 if (!quiet_warnings)
3972 {
3973 if (!intel_syntax
40fb9820
L		 3974 && (i.types[0].bitfield.jumpabsolute
3975 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3976 {
3977 as_warn (_("indirect %s without `*'"), t->name);
3978 }
3979
40fb9820
L		 3980 if (t->opcode_modifier.isprefix
3981 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3982 {
3983 /* Warn them that a data or address size prefix doesn't
3984 affect assembly of the next line of code. */
3985 as_warn (_("stand-alone `%s' prefix"), t->name);
3986 }
3987 }
3988
3989 /* Copy the template we found. */
3990 i.tm = *t;
539e75ad
L		 3991
3992 if (addr_prefix_disp != -1)
3993 i.tm.operand_types[addr_prefix_disp]
3994 = operand_types[addr_prefix_disp];
3995
29b0f896
AM		 3996 if (found_reverse_match)
3997 {
3998 /* If we found a reverse match we must alter the opcode
3999 direction bit. found_reverse_match holds bits to change
4000 (different for int & float insns). */
4001
4002 i.tm.base_opcode ^= found_reverse_match;
4003
539e75ad
L		 4004 i.tm.operand_types[0] = operand_types[1];
4005 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4006 }
4007
fa99fab2 4008 return t;
29b0f896
AM		 4009}
4010
4011static int
e3bb37b5 4012check_string (void)
29b0f896 4013{
40fb9820
L		 4014 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4015 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4016 {
4017 if (i.seg[0] != NULL && i.seg[0] != &es)
4018 {
a87af027 4019 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4020 i.tm.name,
a87af027
JB		 4021 mem_op + 1,
4022 register_prefix);
29b0f896
AM		 4023 return 0;
4024 }
4025 /* There's only ever one segment override allowed per instruction.
4026 This instruction possibly has a legal segment override on the
4027 second operand, so copy the segment to where non-string
4028 instructions store it, allowing common code. */
4029 i.seg[0] = i.seg[1];
4030 }
40fb9820 4031 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4032 {
4033 if (i.seg[1] != NULL && i.seg[1] != &es)
4034 {
a87af027 4035 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4036 i.tm.name,
a87af027
JB		 4037 mem_op + 2,
4038 register_prefix);
29b0f896
AM		 4039 return 0;
4040 }
4041 }
4042 return 1;
4043}
4044
4045static int
543613e9 4046process_suffix (void)
29b0f896
AM		 4047{
4048 /* If matched instruction specifies an explicit instruction mnemonic
4049 suffix, use it. */
40fb9820
L		 4050 if (i.tm.opcode_modifier.size16)
4051 i.suffix = WORD_MNEM_SUFFIX;
4052 else if (i.tm.opcode_modifier.size32)
4053 i.suffix = LONG_MNEM_SUFFIX;
4054 else if (i.tm.opcode_modifier.size64)
4055 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4056 else if (i.reg_operands)
4057 {
4058 /* If there's no instruction mnemonic suffix we try to invent one
4059 based on register operands. */
4060 if (!i.suffix)
4061 {
4062 /* We take i.suffix from the last register operand specified,
4063 Destination register type is more significant than source
381d071f
L		 4064 register type. crc32 in SSE4.2 prefers source register
4065 type. */
4066 if (i.tm.base_opcode == 0xf20f38f1)
4067 {
40fb9820
L		 4068 if (i.types[0].bitfield.reg16)
4069 i.suffix = WORD_MNEM_SUFFIX;
4070 else if (i.types[0].bitfield.reg32)
4071 i.suffix = LONG_MNEM_SUFFIX;
4072 else if (i.types[0].bitfield.reg64)
4073 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4074 }
9344ff29 4075 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4076 {
40fb9820 4077 if (i.types[0].bitfield.reg8)
20592a94
L		 4078 i.suffix = BYTE_MNEM_SUFFIX;
4079 }
381d071f
L		 4080
4081 if (!i.suffix)
4082 {
4083 int op;
4084
20592a94
L		 4085 if (i.tm.base_opcode == 0xf20f38f1
4086 || i.tm.base_opcode == 0xf20f38f0)
4087 {
4088 /* We have to know the operand size for crc32. */
4089 as_bad (_("ambiguous memory operand size for `%s`"),
4090 i.tm.name);
4091 return 0;
4092 }
4093
381d071f 4094 for (op = i.operands; --op >= 0;)
40fb9820 4095 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4096 {
40fb9820
L		 4097 if (i.types[op].bitfield.reg8)
4098 {
4099 i.suffix = BYTE_MNEM_SUFFIX;
4100 break;
4101 }
4102 else if (i.types[op].bitfield.reg16)
4103 {
4104 i.suffix = WORD_MNEM_SUFFIX;
4105 break;
4106 }
4107 else if (i.types[op].bitfield.reg32)
4108 {
4109 i.suffix = LONG_MNEM_SUFFIX;
4110 break;
4111 }
4112 else if (i.types[op].bitfield.reg64)
4113 {
4114 i.suffix = QWORD_MNEM_SUFFIX;
4115 break;
4116 }
381d071f
L		 4117 }
4118 }
29b0f896
AM		 4119 }
4120 else if (i.suffix == BYTE_MNEM_SUFFIX)
4121 {
4122 if (!check_byte_reg ())
4123 return 0;
4124 }
4125 else if (i.suffix == LONG_MNEM_SUFFIX)
4126 {
4127 if (!check_long_reg ())
4128 return 0;
4129 }
4130 else if (i.suffix == QWORD_MNEM_SUFFIX)
4131 {
955e1e6a
L		 4132 if (intel_syntax
4133 && i.tm.opcode_modifier.ignoresize
4134 && i.tm.opcode_modifier.no_qsuf)
4135 i.suffix = 0;
4136 else if (!check_qword_reg ())
29b0f896
AM		 4137 return 0;
4138 }
4139 else if (i.suffix == WORD_MNEM_SUFFIX)
4140 {
4141 if (!check_word_reg ())
4142 return 0;
4143 }
c0f3af97
L		 4144 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4145 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4146 {
c0f3af97 4147 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4148 should check if it is a valid suffix. */
4149 }
40fb9820 4150 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4151 /* Do nothing if the instruction is going to ignore the prefix. */
4152 ;
4153 else
4154 abort ();
4155 }
40fb9820 4156 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4157 && !i.suffix
4158 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4159 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4160 {
4161 i.suffix = stackop_size;
4162 }
9306ca4a
JB		 4163 else if (intel_syntax
4164 && !i.suffix
40fb9820
L		 4165 && (i.tm.operand_types[0].bitfield.jumpabsolute
4166 || i.tm.opcode_modifier.jumpbyte
4167 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4168 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4169 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4170 {
4171 switch (flag_code)
4172 {
4173 case CODE_64BIT:
40fb9820 4174 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4175 {
4176 i.suffix = QWORD_MNEM_SUFFIX;
4177 break;
4178 }
4179 case CODE_32BIT:
40fb9820 4180 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4181 i.suffix = LONG_MNEM_SUFFIX;
4182 break;
4183 case CODE_16BIT:
40fb9820 4184 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4185 i.suffix = WORD_MNEM_SUFFIX;
4186 break;
4187 }
4188 }
252b5132 4189
9306ca4a 4190 if (!i.suffix)
29b0f896 4191 {
9306ca4a
JB		 4192 if (!intel_syntax)
4193 {
40fb9820 4194 if (i.tm.opcode_modifier.w)
9306ca4a 4195 {
4eed87de
AM		 4196 as_bad (_("no instruction mnemonic suffix given and "
4197 "no register operands; can't size instruction"));
9306ca4a
JB		 4198 return 0;
4199 }
4200 }
4201 else
4202 {
40fb9820 4203 unsigned int suffixes;
7ab9ffdd 4204
40fb9820
L		 4205 suffixes = !i.tm.opcode_modifier.no_bsuf;
4206 if (!i.tm.opcode_modifier.no_wsuf)
4207 suffixes |= 1 << 1;
4208 if (!i.tm.opcode_modifier.no_lsuf)
4209 suffixes |= 1 << 2;
fc4adea1 4210 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4211 suffixes |= 1 << 3;
4212 if (!i.tm.opcode_modifier.no_ssuf)
4213 suffixes |= 1 << 4;
4214 if (!i.tm.opcode_modifier.no_qsuf)
4215 suffixes |= 1 << 5;
4216
4217 /* There are more than suffix matches. */
4218 if (i.tm.opcode_modifier.w
9306ca4a 4219 || ((suffixes & (suffixes - 1))
40fb9820
L		 4220 && !i.tm.opcode_modifier.defaultsize
4221 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4222 {
4223 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4224 return 0;
4225 }
4226 }
29b0f896 4227 }
252b5132 4228
9306ca4a
JB		 4229 /* Change the opcode based on the operand size given by i.suffix;
4230 We don't need to change things for byte insns. */
4231
582d5edd
L		 4232 if (i.suffix
4233 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4234 && i.suffix != XMMWORD_MNEM_SUFFIX
4235 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4236 {
4237 /* It's not a byte, select word/dword operation. */
40fb9820 4238 if (i.tm.opcode_modifier.w)
29b0f896 4239 {
40fb9820 4240 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4241 i.tm.base_opcode |= 8;
4242 else
4243 i.tm.base_opcode |= 1;
4244 }
0f3f3d8b 4245
29b0f896
AM		 4246 /* Now select between word & dword operations via the operand
4247 size prefix, except for instructions that will ignore this
4248 prefix anyway. */
ca61edf2 4249 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4250 {
ca61edf2
L		 4251 /* The address size override prefix changes the size of the
4252 first operand. */
40fb9820
L		 4253 if ((flag_code == CODE_32BIT
4254 && i.op->regs[0].reg_type.bitfield.reg16)
4255 || (flag_code != CODE_32BIT
4256 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4257 if (!add_prefix (ADDR_PREFIX_OPCODE))
4258 return 0;
4259 }
4260 else if (i.suffix != QWORD_MNEM_SUFFIX
4261 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4262 && !i.tm.opcode_modifier.ignoresize
4263 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4264 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4265 || (flag_code == CODE_64BIT
40fb9820 4266 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4267 {
4268 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4269
40fb9820 4270 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4271 prefix = ADDR_PREFIX_OPCODE;
252b5132 4272
29b0f896
AM		 4273 if (!add_prefix (prefix))
4274 return 0;
24eab124 4275 }
252b5132 4276
29b0f896
AM		 4277 /* Set mode64 for an operand. */
4278 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4279 && flag_code == CODE_64BIT
40fb9820 4280 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4281 {
4282 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4283 need rex64. cmpxchg8b is also a special case. */
4284 if (! (i.operands == 2
4285 && i.tm.base_opcode == 0x90
4286 && i.tm.extension_opcode == None
0dfbf9d7
L		 4287 && operand_type_equal (&i.types [0], &acc64)
4288 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4289 && ! (i.operands == 1
4290 && i.tm.base_opcode == 0xfc7
4291 && i.tm.extension_opcode == 1
40fb9820
L		 4292 && !operand_type_check (i.types [0], reg)
4293 && operand_type_check (i.types [0], anymem)))
f6bee062 4294 i.rex |= REX_W;
46e883c5 4295 }
3e73aa7c 4296
29b0f896
AM		 4297 /* Size floating point instruction. */
4298 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4299 if (i.tm.opcode_modifier.floatmf)
543613e9 4300 i.tm.base_opcode ^= 4;
29b0f896 4301 }
7ecd2f8b 4302
29b0f896
AM		 4303 return 1;
4304}
3e73aa7c 4305
29b0f896 4306static int
543613e9 4307check_byte_reg (void)
29b0f896
AM		 4308{
4309 int op;
543613e9 4310
29b0f896
AM		 4311 for (op = i.operands; --op >= 0;)
4312 {
4313 /* If this is an eight bit register, it's OK. If it's the 16 or
4314 32 bit version of an eight bit register, we will just use the
4315 low portion, and that's OK too. */
40fb9820 4316 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4317 continue;
4318
ca61edf2
L		 4319 /* Don't generate this warning if not needed. */
4320 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 4321 continue;
4322
9344ff29
L		 4323 /* crc32 doesn't generate this warning. */
4324 if (i.tm.base_opcode == 0xf20f38f0)
4325 continue;
4326
40fb9820
L		 4327 if ((i.types[op].bitfield.reg16
4328 || i.types[op].bitfield.reg32
4329 || i.types[op].bitfield.reg64)
4330 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4331 {
4332 /* Prohibit these changes in the 64bit mode, since the
4333 lowering is more complicated. */
4334 if (flag_code == CODE_64BIT
40fb9820 4335 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4336 {
2ca3ace5
L		 4337 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4338 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4339 i.suffix);
4340 return 0;
4341 }
4342#if REGISTER_WARNINGS
4343 if (!quiet_warnings
40fb9820 4344 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4345 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4346 register_prefix,
40fb9820 4347 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4348 ? REGNAM_AL - REGNAM_AX
4349 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4350 register_prefix,
29b0f896
AM		 4351 i.op[op].regs->reg_name,
4352 i.suffix);
4353#endif
4354 continue;
4355 }
4356 /* Any other register is bad. */
40fb9820
L		 4357 if (i.types[op].bitfield.reg16
4358 || i.types[op].bitfield.reg32
4359 || i.types[op].bitfield.reg64
4360 || i.types[op].bitfield.regmmx
4361 || i.types[op].bitfield.regxmm
c0f3af97 4362 || i.types[op].bitfield.regymm
40fb9820
L		 4363 || i.types[op].bitfield.sreg2
4364 || i.types[op].bitfield.sreg3
4365 || i.types[op].bitfield.control
4366 || i.types[op].bitfield.debug
4367 || i.types[op].bitfield.test
4368 || i.types[op].bitfield.floatreg
4369 || i.types[op].bitfield.floatacc)
29b0f896 4370 {
a540244d
L		 4371 as_bad (_("`%s%s' not allowed with `%s%c'"),
4372 register_prefix,
29b0f896
AM		 4373 i.op[op].regs->reg_name,
4374 i.tm.name,
4375 i.suffix);
4376 return 0;
4377 }
4378 }
4379 return 1;
4380}
4381
4382static int
e3bb37b5 4383check_long_reg (void)
29b0f896
AM		 4384{
4385 int op;
4386
4387 for (op = i.operands; --op >= 0;)
4388 /* Reject eight bit registers, except where the template requires
4389 them. (eg. movzb) */
40fb9820
L		 4390 if (i.types[op].bitfield.reg8
4391 && (i.tm.operand_types[op].bitfield.reg16
4392 || i.tm.operand_types[op].bitfield.reg32
4393 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4394 {
a540244d
L		 4395 as_bad (_("`%s%s' not allowed with `%s%c'"),
4396 register_prefix,
29b0f896
AM		 4397 i.op[op].regs->reg_name,
4398 i.tm.name,
4399 i.suffix);
4400 return 0;
4401 }
4402 /* Warn if the e prefix on a general reg is missing. */
4403 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4404 && i.types[op].bitfield.reg16
4405 && (i.tm.operand_types[op].bitfield.reg32
4406 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4407 {
4408 /* Prohibit these changes in the 64bit mode, since the
4409 lowering is more complicated. */
4410 if (flag_code == CODE_64BIT)
252b5132 4411 {
2ca3ace5
L		 4412 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4413 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4414 i.suffix);
4415 return 0;
252b5132 4416 }
29b0f896
AM		 4417#if REGISTER_WARNINGS
4418 else
a540244d
L		 4419 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4420 register_prefix,
29b0f896 4421 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4422 register_prefix,
29b0f896
AM		 4423 i.op[op].regs->reg_name,
4424 i.suffix);
4425#endif
252b5132 4426 }
29b0f896 4427 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4428 else if (i.types[op].bitfield.reg64
4429 && (i.tm.operand_types[op].bitfield.reg32
4430 || i.tm.operand_types[op].bitfield.acc))
252b5132 4431 {
34828aad 4432 if (intel_syntax
ca61edf2 4433 && i.tm.opcode_modifier.toqword
40fb9820 4434 && !i.types[0].bitfield.regxmm)
34828aad 4435 {
ca61edf2 4436 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4437 i.suffix = QWORD_MNEM_SUFFIX;
4438 }
4439 else
4440 {
4441 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4442 register_prefix, i.op[op].regs->reg_name,
4443 i.suffix);
4444 return 0;
4445 }
29b0f896
AM		 4446 }
4447 return 1;
4448}
252b5132 4449
29b0f896 4450static int
e3bb37b5 4451check_qword_reg (void)
29b0f896
AM		 4452{
4453 int op;
252b5132 4454
29b0f896
AM		 4455 for (op = i.operands; --op >= 0; )
4456 /* Reject eight bit registers, except where the template requires
4457 them. (eg. movzb) */
40fb9820
L		 4458 if (i.types[op].bitfield.reg8
4459 && (i.tm.operand_types[op].bitfield.reg16
4460 || i.tm.operand_types[op].bitfield.reg32
4461 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4462 {
a540244d
L		 4463 as_bad (_("`%s%s' not allowed with `%s%c'"),
4464 register_prefix,
29b0f896
AM		 4465 i.op[op].regs->reg_name,
4466 i.tm.name,
4467 i.suffix);
4468 return 0;
4469 }
4470 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4471 else if ((i.types[op].bitfield.reg16
4472 || i.types[op].bitfield.reg32)
4473 && (i.tm.operand_types[op].bitfield.reg32
4474 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4475 {
4476 /* Prohibit these changes in the 64bit mode, since the
4477 lowering is more complicated. */
34828aad 4478 if (intel_syntax
ca61edf2 4479 && i.tm.opcode_modifier.todword
40fb9820 4480 && !i.types[0].bitfield.regxmm)
34828aad 4481 {
ca61edf2 4482 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4483 i.suffix = LONG_MNEM_SUFFIX;
4484 }
4485 else
4486 {
4487 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4488 register_prefix, i.op[op].regs->reg_name,
4489 i.suffix);
4490 return 0;
4491 }
252b5132 4492 }
29b0f896
AM		 4493 return 1;
4494}
252b5132 4495
29b0f896 4496static int
e3bb37b5 4497check_word_reg (void)
29b0f896
AM		 4498{
4499 int op;
4500 for (op = i.operands; --op >= 0;)
4501 /* Reject eight bit registers, except where the template requires
4502 them. (eg. movzb) */
40fb9820
L		 4503 if (i.types[op].bitfield.reg8
4504 && (i.tm.operand_types[op].bitfield.reg16
4505 || i.tm.operand_types[op].bitfield.reg32
4506 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4507 {
a540244d
L		 4508 as_bad (_("`%s%s' not allowed with `%s%c'"),
4509 register_prefix,
29b0f896
AM		 4510 i.op[op].regs->reg_name,
4511 i.tm.name,
4512 i.suffix);
4513 return 0;
4514 }
4515 /* Warn if the e prefix on a general reg is present. */
4516 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4517 && i.types[op].bitfield.reg32
4518 && (i.tm.operand_types[op].bitfield.reg16
4519 || i.tm.operand_types[op].bitfield.acc))
252b5132 4520 {
29b0f896
AM		 4521 /* Prohibit these changes in the 64bit mode, since the
4522 lowering is more complicated. */
4523 if (flag_code == CODE_64BIT)
252b5132 4524 {
2ca3ace5
L		 4525 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4526 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4527 i.suffix);
4528 return 0;
252b5132 4529 }
29b0f896
AM		 4530 else
4531#if REGISTER_WARNINGS
a540244d
L		 4532 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4533 register_prefix,
29b0f896 4534 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4535 register_prefix,
29b0f896
AM		 4536 i.op[op].regs->reg_name,
4537 i.suffix);
4538#endif
4539 }
4540 return 1;
4541}
252b5132 4542
29b0f896 4543static int
40fb9820 4544update_imm (unsigned int j)
29b0f896 4545{
bc0844ae 4546 i386_operand_type overlap = i.types[j];
40fb9820
L		 4547 if ((overlap.bitfield.imm8
4548 || overlap.bitfield.imm8s
4549 || overlap.bitfield.imm16
4550 || overlap.bitfield.imm32
4551 || overlap.bitfield.imm32s
4552 || overlap.bitfield.imm64)
0dfbf9d7
L		 4553 && !operand_type_equal (&overlap, &imm8)
4554 && !operand_type_equal (&overlap, &imm8s)
4555 && !operand_type_equal (&overlap, &imm16)
4556 && !operand_type_equal (&overlap, &imm32)
4557 && !operand_type_equal (&overlap, &imm32s)
4558 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4559 {
4560 if (i.suffix)
4561 {
40fb9820
L		 4562 i386_operand_type temp;
4563
0dfbf9d7 4564 operand_type_set (&temp, 0);
7ab9ffdd 4565 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4566 {
4567 temp.bitfield.imm8 = overlap.bitfield.imm8;
4568 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4569 }
4570 else if (i.suffix == WORD_MNEM_SUFFIX)
4571 temp.bitfield.imm16 = overlap.bitfield.imm16;
4572 else if (i.suffix == QWORD_MNEM_SUFFIX)
4573 {
4574 temp.bitfield.imm64 = overlap.bitfield.imm64;
4575 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4576 }
4577 else
4578 temp.bitfield.imm32 = overlap.bitfield.imm32;
4579 overlap = temp;
29b0f896 4580 }
0dfbf9d7
L		 4581 else if (operand_type_equal (&overlap, &imm16_32_32s)
4582 || operand_type_equal (&overlap, &imm16_32)
4583 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4584 {
40fb9820 4585 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4586 overlap = imm16;
40fb9820 4587 else
65da13b5 4588 overlap = imm32s;
29b0f896 4589 }
0dfbf9d7
L		 4590 if (!operand_type_equal (&overlap, &imm8)
4591 && !operand_type_equal (&overlap, &imm8s)
4592 && !operand_type_equal (&overlap, &imm16)
4593 && !operand_type_equal (&overlap, &imm32)
4594 && !operand_type_equal (&overlap, &imm32s)
4595 && !operand_type_equal (&overlap, &imm64))
29b0f896 4596 {
4eed87de
AM		 4597 as_bad (_("no instruction mnemonic suffix given; "
4598 "can't determine immediate size"));
29b0f896
AM		 4599 return 0;
4600 }
4601 }
40fb9820 4602 i.types[j] = overlap;
29b0f896 4603
40fb9820
L		 4604 return 1;
4605}
4606
4607static int
4608finalize_imm (void)
4609{
bc0844ae 4610 unsigned int j, n;
29b0f896 4611
bc0844ae
L		 4612 /* Update the first 2 immediate operands. */
4613 n = i.operands > 2 ? 2 : i.operands;
4614 if (n)
4615 {
4616 for (j = 0; j < n; j++)
4617 if (update_imm (j) == 0)
4618 return 0;
40fb9820 4619
bc0844ae
L		 4620 /* The 3rd operand can't be immediate operand. */
4621 gas_assert (operand_type_check (i.types[2], imm) == 0);
4622 }
29b0f896
AM		 4623
4624 return 1;
4625}
4626
c0f3af97
L		 4627static int
4628bad_implicit_operand (int xmm)
4629{
4630 const char *reg = xmm ? "xmm0" : "ymm0";
4631 if (intel_syntax)
4632 as_bad (_("the last operand of `%s' must be `%s%s'"),
4633 i.tm.name, register_prefix, reg);
4634 else
4635 as_bad (_("the first operand of `%s' must be `%s%s'"),
4636 i.tm.name, register_prefix, reg);
4637 return 0;
4638}
4639
29b0f896 4640static int
e3bb37b5 4641process_operands (void)
29b0f896
AM		 4642{
4643 /* Default segment register this instruction will use for memory
4644 accesses. 0 means unknown. This is only for optimizing out
4645 unnecessary segment overrides. */
4646 const seg_entry *default_seg = 0;
4647
c0f3af97
L		 4648 if (i.tm.opcode_modifier.sse2avx
4649 && (i.tm.opcode_modifier.vexnds
4650 || i.tm.opcode_modifier.vexndd))
29b0f896 4651 {
c0f3af97
L		 4652 unsigned int dup = i.operands;
4653 unsigned int dest = dup - 1;
9fcfb3d7
L		 4654 unsigned int j;
4655
c0f3af97 4656 /* The destination must be an xmm register. */
9c2799c2 4657 gas_assert (i.reg_operands
7ab9ffdd
L		 4658 && MAX_OPERANDS > dup
4659 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4660
4661 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4662 {
c0f3af97 4663 /* The first operand is implicit and must be xmm0. */
9c2799c2 4664 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4665 if (i.op[0].regs->reg_num != 0)
4666 return bad_implicit_operand (1);
4667
4668 if (i.tm.opcode_modifier.vex3sources)
4669 {
4670 /* Keep xmm0 for instructions with VEX prefix and 3
4671 sources. */
4672 goto duplicate;
4673 }
e2ec9d29 4674 else
c0f3af97
L		 4675 {
4676 /* We remove the first xmm0 and keep the number of
4677 operands unchanged, which in fact duplicates the
4678 destination. */
4679 for (j = 1; j < i.operands; j++)
4680 {
4681 i.op[j - 1] = i.op[j];
4682 i.types[j - 1] = i.types[j];
4683 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4684 }
4685 }
4686 }
4687 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 4688 {
9c2799c2 4689 gas_assert ((MAX_OPERANDS - 1) > dup
7ab9ffdd 4690 && i.tm.opcode_modifier.vex3sources);
c0f3af97
L		 4691
4692 /* Add the implicit xmm0 for instructions with VEX prefix
4693 and 3 sources. */
4694 for (j = i.operands; j > 0; j--)
4695 {
4696 i.op[j] = i.op[j - 1];
4697 i.types[j] = i.types[j - 1];
4698 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4699 }
4700 i.op[0].regs
4701 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 4702 i.types[0] = regxmm;
c0f3af97
L		 4703 i.tm.operand_types[0] = regxmm;
4704
4705 i.operands += 2;
4706 i.reg_operands += 2;
4707 i.tm.operands += 2;
4708
4709 dup++;
4710 dest++;
4711 i.op[dup] = i.op[dest];
4712 i.types[dup] = i.types[dest];
4713 i.tm.operand_types[dup] = i.tm.operand_types[dest];
e2ec9d29 4714 }
c0f3af97
L		 4715 else
4716 {
4717duplicate:
4718 i.operands++;
4719 i.reg_operands++;
4720 i.tm.operands++;
4721
4722 i.op[dup] = i.op[dest];
4723 i.types[dup] = i.types[dest];
4724 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4725 }
4726
4727 if (i.tm.opcode_modifier.immext)
4728 process_immext ();
4729 }
4730 else if (i.tm.opcode_modifier.firstxmm0)
4731 {
4732 unsigned int j;
4733
4734 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 4735 gas_assert (i.reg_operands
7ab9ffdd
L		 4736 && (operand_type_equal (&i.types[0], &regxmm)
4737 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 4738 if (i.op[0].regs->reg_num != 0)
4739 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4740
4741 for (j = 1; j < i.operands; j++)
4742 {
4743 i.op[j - 1] = i.op[j];
4744 i.types[j - 1] = i.types[j];
4745
4746 /* We need to adjust fields in i.tm since they are used by
4747 build_modrm_byte. */
4748 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4749 }
4750
e2ec9d29
L		 4751 i.operands--;
4752 i.reg_operands--;
e2ec9d29
L		 4753 i.tm.operands--;
4754 }
4755 else if (i.tm.opcode_modifier.regkludge)
4756 {
4757 /* The imul $imm, %reg instruction is converted into
4758 imul $imm, %reg, %reg, and the clr %reg instruction
4759 is converted into xor %reg, %reg. */
4760
4761 unsigned int first_reg_op;
4762
4763 if (operand_type_check (i.types[0], reg))
4764 first_reg_op = 0;
4765 else
4766 first_reg_op = 1;
4767 /* Pretend we saw the extra register operand. */
9c2799c2 4768 gas_assert (i.reg_operands == 1
7ab9ffdd 4769 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 4770 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4771 i.types[first_reg_op + 1] = i.types[first_reg_op];
4772 i.operands++;
4773 i.reg_operands++;
29b0f896
AM		 4774 }
4775
40fb9820 4776 if (i.tm.opcode_modifier.shortform)
29b0f896 4777 {
40fb9820
L		 4778 if (i.types[0].bitfield.sreg2
4779 || i.types[0].bitfield.sreg3)
29b0f896 4780 {
4eed87de
AM		 4781 if (i.tm.base_opcode == POP_SEG_SHORT
4782 && i.op[0].regs->reg_num == 1)
29b0f896 4783 {
a87af027 4784 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 4785 return 0;
29b0f896 4786 }
4eed87de
AM		 4787 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4788 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4789 i.rex |= REX_B;
4eed87de
AM		 4790 }
4791 else
4792 {
7ab9ffdd 4793 /* The register or float register operand is in operand
85f10a01 4794 0 or 1. */
40fb9820 4795 unsigned int op;
7ab9ffdd
L		 4796
4797 if (i.types[0].bitfield.floatreg
4798 || operand_type_check (i.types[0], reg))
4799 op = 0;
4800 else
4801 op = 1;
4eed87de
AM		 4802 /* Register goes in low 3 bits of opcode. */
4803 i.tm.base_opcode |= i.op[op].regs->reg_num;
4804 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4805 i.rex |= REX_B;
40fb9820 4806 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4807 {
4eed87de
AM		 4808 /* Warn about some common errors, but press on regardless.
4809 The first case can be generated by gcc (<= 2.8.1). */
4810 if (i.operands == 2)
4811 {
4812 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 4813 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 4814 register_prefix, i.op[!intel_syntax].regs->reg_name,
4815 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 4816 }
4817 else
4818 {
4819 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4820 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4821 register_prefix, i.op[0].regs->reg_name);
4eed87de 4822 }
29b0f896
AM		 4823 }
4824 }
4825 }
40fb9820 4826 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4827 {
4828 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4829 must be put into the modrm byte). Now, we make the modrm and
4830 index base bytes based on all the info we've collected. */
29b0f896
AM		 4831
4832 default_seg = build_modrm_byte ();
4833 }
8a2ed489 4834 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4835 {
4836 default_seg = &ds;
4837 }
40fb9820 4838 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4839 {
4840 /* For the string instructions that allow a segment override
4841 on one of their operands, the default segment is ds. */
4842 default_seg = &ds;
4843 }
4844
75178d9d
L		 4845 if (i.tm.base_opcode == 0x8d /* lea */
4846 && i.seg[0]
4847 && !quiet_warnings)
30123838 4848 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4849
4850 /* If a segment was explicitly specified, and the specified segment
4851 is not the default, use an opcode prefix to select it. If we
4852 never figured out what the default segment is, then default_seg
4853 will be zero at this point, and the specified segment prefix will
4854 always be used. */
29b0f896
AM		 4855 if ((i.seg[0]) && (i.seg[0] != default_seg))
4856 {
4857 if (!add_prefix (i.seg[0]->seg_prefix))
4858 return 0;
4859 }
4860 return 1;
4861}
4862
4863static const seg_entry *
e3bb37b5 4864build_modrm_byte (void)
29b0f896
AM		 4865{
4866 const seg_entry *default_seg = 0;
c0f3af97 4867 unsigned int source, dest;
7ab9ffdd 4868 int vex_3_sources;
c0f3af97
L		 4869
4870 /* The first operand of instructions with VEX prefix and 3 sources
4871 must be VEX_Imm4. */
4872 vex_3_sources = i.tm.opcode_modifier.vex3sources;
4873 if (vex_3_sources)
4874 {
4875 unsigned int nds, reg;
4876
922d8de8
DR		 4877 if (i.tm.opcode_modifier.veximmext
4878 && i.tm.opcode_modifier.immext)
4879 {
4880 dest = i.operands - 2;
4881 gas_assert (dest == 3);
4882 }
4883 else
0bfee649 4884 dest = i.operands - 1;
c0f3af97 4885 nds = dest - 1;
922d8de8
DR		 4886
4887 /* This instruction must have 4 register operands
4888 or 3 register operands plus 1 memory operand.
4889 It must have VexNDS and VexImmExt. */
4890 gas_assert ((i.reg_operands == 4
7ab9ffdd
L		 4891 || (i.reg_operands == 3 && i.mem_operands == 1))
4892 && i.tm.opcode_modifier.vexnds
4893 && i.tm.opcode_modifier.veximmext
922d8de8
DR		 4894 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
4895 || operand_type_equal (&i.tm.operand_types[dest], &regymm)));
c0f3af97 4896
0bfee649
L		 4897 /* Generate an 8bit immediate operand to encode the register
4898 operand. */
4899 expressionS *exp = &im_expressions[i.imm_operands++];
4900 i.op[i.operands].imms = exp;
4901 i.types[i.operands] = imm8;
4902 i.operands++;
922d8de8
DR		 4903 /* If VexW1 is set, the first operand is the source and
4904 the second operand is encoded in the immediate operand. */
4905 if (i.tm.opcode_modifier.vexw1)
4906 {
4907 source = 0;
4908 reg = 1;
4909 }
4910 else
4911 {
4912 source = 1;
4913 reg = 0;
4914 }
4915 /* FMA4 swaps REG and NDS. */
4916 if (i.tm.cpu_flags.bitfield.cpufma4)
4917 {
4918 unsigned int tmp;
4919 tmp = reg;
4920 reg = nds;
4921 nds = tmp;
4922 }
4923 gas_assert ((operand_type_equal (&i.tm.operand_types[reg], &regxmm)
4924 || operand_type_equal (&i.tm.operand_types[reg],
4925 &regymm))
4926 && (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
4927 || operand_type_equal (&i.tm.operand_types[nds],
4928 &regymm)));
0bfee649
L		 4929 exp->X_op = O_constant;
4930 exp->X_add_number
922d8de8
DR		 4931 = ((i.op[reg].regs->reg_num
4932 + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
dae39acc 4933 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 4934 }
4935 else
4936 source = dest = 0;
29b0f896
AM		 4937
4938 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 4939 implicit registers do not count. If there are 3 register
4940 operands, it must be a instruction with VexNDS. For a
4941 instruction with VexNDD, the destination register is encoded
4942 in VEX prefix. If there are 4 register operands, it must be
4943 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 4944 if (i.mem_operands == 0
4945 && ((i.reg_operands == 2
4946 && !i.tm.opcode_modifier.vexndd)
4947 || (i.reg_operands == 3
4948 && i.tm.opcode_modifier.vexnds)
4949 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 4950 {
cab737b9
L		 4951 switch (i.operands)
4952 {
4953 case 2:
4954 source = 0;
4955 break;
4956 case 3:
c81128dc
L		 4957 /* When there are 3 operands, one of them may be immediate,
4958 which may be the first or the last operand. Otherwise,
c0f3af97
L		 4959 the first operand must be shift count register (cl) or it
4960 is an instruction with VexNDS. */
9c2799c2 4961 gas_assert (i.imm_operands == 1
7ab9ffdd
L		 4962 || (i.imm_operands == 0
4963 && (i.tm.opcode_modifier.vexnds
4964 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 4965 if (operand_type_check (i.types[0], imm)
4966 || i.types[0].bitfield.shiftcount)
4967 source = 1;
4968 else
4969 source = 0;
cab737b9
L		 4970 break;
4971 case 4:
368d64cc
L		 4972 /* When there are 4 operands, the first two must be 8bit
4973 immediate operands. The source operand will be the 3rd
c0f3af97
L		 4974 one.
4975
4976 For instructions with VexNDS, if the first operand
4977 an imm8, the source operand is the 2nd one. If the last
4978 operand is imm8, the source operand is the first one. */
9c2799c2 4979 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 4980 && i.types[0].bitfield.imm8
4981 && i.types[1].bitfield.imm8)
4982 || (i.tm.opcode_modifier.vexnds
4983 && i.imm_operands == 1
4984 && (i.types[0].bitfield.imm8
4985 || i.types[i.operands - 1].bitfield.imm8)));
c0f3af97
L		 4986 if (i.tm.opcode_modifier.vexnds)
4987 {
4988 if (i.types[0].bitfield.imm8)
4989 source = 1;
4990 else
4991 source = 0;
4992 }
4993 else
4994 source = 2;
4995 break;
4996 case 5:
cab737b9
L		 4997 break;
4998 default:
4999 abort ();
5000 }
5001
c0f3af97
L		 5002 if (!vex_3_sources)
5003 {
5004 dest = source + 1;
5005
5006 if (i.tm.opcode_modifier.vexnds)
5007 {
5008 /* For instructions with VexNDS, the register-only
5009 source operand must be XMM or YMM register. It is
fa99fab2
L		 5010 encoded in VEX prefix. We need to clear RegMem bit
5011 before calling operand_type_equal. */
5012 i386_operand_type op = i.tm.operand_types[dest];
5013 op.bitfield.regmem = 0;
c0f3af97 5014 if ((dest + 1) >= i.operands
fa99fab2
L		 5015 || (!operand_type_equal (&op, &regxmm)
5016 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 5017 abort ();
5018 i.vex.register_specifier = i.op[dest].regs;
5019 dest++;
5020 }
5021 }
29b0f896
AM		 5022
5023 i.rm.mode = 3;
5024 /* One of the register operands will be encoded in the i.tm.reg
5025 field, the other in the combined i.tm.mode and i.tm.regmem
5026 fields. If no form of this instruction supports a memory
5027 destination operand, then we assume the source operand may
5028 sometimes be a memory operand and so we need to store the
5029 destination in the i.rm.reg field. */
40fb9820
L		 5030 if (!i.tm.operand_types[dest].bitfield.regmem
5031 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5032 {
5033 i.rm.reg = i.op[dest].regs->reg_num;
5034 i.rm.regmem = i.op[source].regs->reg_num;
5035 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5036 i.rex |= REX_R;
29b0f896 5037 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5038 i.rex |= REX_B;
29b0f896
AM		 5039 }
5040 else
5041 {
5042 i.rm.reg = i.op[source].regs->reg_num;
5043 i.rm.regmem = i.op[dest].regs->reg_num;
5044 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5045 i.rex |= REX_B;
29b0f896 5046 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5047 i.rex |= REX_R;
29b0f896 5048 }
161a04f6 5049 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5050 {
40fb9820
L		 5051 if (!i.types[0].bitfield.control
5052 && !i.types[1].bitfield.control)
c4a530c5 5053 abort ();
161a04f6 5054 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5055 add_prefix (LOCK_PREFIX_OPCODE);
5056 }
29b0f896
AM		 5057 }
5058 else
5059 { /* If it's not 2 reg operands... */
c0f3af97
L		 5060 unsigned int mem;
5061
29b0f896
AM		 5062 if (i.mem_operands)
5063 {
5064 unsigned int fake_zero_displacement = 0;
99018f42 5065 unsigned int op;
4eed87de 5066
7ab9ffdd
L		 5067 for (op = 0; op < i.operands; op++)
5068 if (operand_type_check (i.types[op], anymem))
5069 break;
7ab9ffdd 5070 gas_assert (op < i.operands);
29b0f896
AM		 5071
5072 default_seg = &ds;
5073
5074 if (i.base_reg == 0)
5075 {
5076 i.rm.mode = 0;
5077 if (!i.disp_operands)
5078 fake_zero_displacement = 1;
5079 if (i.index_reg == 0)
5080 {
5081 /* Operand is just <disp> */
20f0a1fc 5082 if (flag_code == CODE_64BIT)
29b0f896
AM		 5083 {
5084 /* 64bit mode overwrites the 32bit absolute
5085 addressing by RIP relative addressing and
5086 absolute addressing is encoded by one of the
5087 redundant SIB forms. */
5088 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5089 i.sib.base = NO_BASE_REGISTER;
5090 i.sib.index = NO_INDEX_REGISTER;
fc225355 5091 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5092 ? disp32s : disp32);
20f0a1fc 5093 }
fc225355
L		 5094 else if ((flag_code == CODE_16BIT)
5095 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5096 {
5097 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5098 i.types[op] = disp16;
20f0a1fc
NC		 5099 }
5100 else
5101 {
5102 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5103 i.types[op] = disp32;
29b0f896
AM		 5104 }
5105 }
5106 else /* !i.base_reg && i.index_reg */
5107 {
db51cc60
L		 5108 if (i.index_reg->reg_num == RegEiz
5109 || i.index_reg->reg_num == RegRiz)
5110 i.sib.index = NO_INDEX_REGISTER;
5111 else
5112 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5113 i.sib.base = NO_BASE_REGISTER;
5114 i.sib.scale = i.log2_scale_factor;
5115 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5116 i.types[op].bitfield.disp8 = 0;
5117 i.types[op].bitfield.disp16 = 0;
5118 i.types[op].bitfield.disp64 = 0;
29b0f896 5119 if (flag_code != CODE_64BIT)
40fb9820
L		 5120 {
5121 /* Must be 32 bit */
5122 i.types[op].bitfield.disp32 = 1;
5123 i.types[op].bitfield.disp32s = 0;
5124 }
29b0f896 5125 else
40fb9820
L		 5126 {
5127 i.types[op].bitfield.disp32 = 0;
5128 i.types[op].bitfield.disp32s = 1;
5129 }
29b0f896 5130 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5131 i.rex |= REX_X;
29b0f896
AM		 5132 }
5133 }
5134 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5135 else if (i.base_reg->reg_num == RegRip ||
5136 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5137 {
5138 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5139 i.types[op].bitfield.disp8 = 0;
5140 i.types[op].bitfield.disp16 = 0;
5141 i.types[op].bitfield.disp32 = 0;
5142 i.types[op].bitfield.disp32s = 1;
5143 i.types[op].bitfield.disp64 = 0;
71903a11 5144 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5145 if (! i.disp_operands)
5146 fake_zero_displacement = 1;
29b0f896 5147 }
40fb9820 5148 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5149 {
5150 switch (i.base_reg->reg_num)
5151 {
5152 case 3: /* (%bx) */
5153 if (i.index_reg == 0)
5154 i.rm.regmem = 7;
5155 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5156 i.rm.regmem = i.index_reg->reg_num - 6;
5157 break;
5158 case 5: /* (%bp) */
5159 default_seg = &ss;
5160 if (i.index_reg == 0)
5161 {
5162 i.rm.regmem = 6;
40fb9820 5163 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5164 {
5165 /* fake (%bp) into 0(%bp) */
40fb9820 5166 i.types[op].bitfield.disp8 = 1;
252b5132 5167 fake_zero_displacement = 1;
29b0f896
AM		 5168 }
5169 }
5170 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5171 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5172 break;
5173 default: /* (%si) -> 4 or (%di) -> 5 */
5174 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5175 }
5176 i.rm.mode = mode_from_disp_size (i.types[op]);
5177 }
5178 else /* i.base_reg and 32/64 bit mode */
5179 {
5180 if (flag_code == CODE_64BIT
40fb9820
L		 5181 && operand_type_check (i.types[op], disp))
5182 {
5183 i386_operand_type temp;
0dfbf9d7 5184 operand_type_set (&temp, 0);
40fb9820
L		 5185 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5186 i.types[op] = temp;
5187 if (i.prefix[ADDR_PREFIX] == 0)
5188 i.types[op].bitfield.disp32s = 1;
5189 else
5190 i.types[op].bitfield.disp32 = 1;
5191 }
20f0a1fc 5192
29b0f896
AM		 5193 i.rm.regmem = i.base_reg->reg_num;
5194 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5195 i.rex |= REX_B;
29b0f896
AM		 5196 i.sib.base = i.base_reg->reg_num;
5197 /* x86-64 ignores REX prefix bit here to avoid decoder
5198 complications. */
5199 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5200 {
5201 default_seg = &ss;
5202 if (i.disp_operands == 0)
5203 {
5204 fake_zero_displacement = 1;
40fb9820 5205 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5206 }
5207 }
5208 else if (i.base_reg->reg_num == ESP_REG_NUM)
5209 {
5210 default_seg = &ss;
5211 }
5212 i.sib.scale = i.log2_scale_factor;
5213 if (i.index_reg == 0)
5214 {
5215 /* <disp>(%esp) becomes two byte modrm with no index
5216 register. We've already stored the code for esp
5217 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5218 Any base register besides %esp will not use the
5219 extra modrm byte. */
5220 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5221 }
5222 else
5223 {
db51cc60
L		 5224 if (i.index_reg->reg_num == RegEiz
5225 || i.index_reg->reg_num == RegRiz)
5226 i.sib.index = NO_INDEX_REGISTER;
5227 else
5228 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5229 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5230 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5231 i.rex |= REX_X;
29b0f896 5232 }
67a4f2b7
AO		 5233
5234 if (i.disp_operands
5235 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5236 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5237 i.rm.mode = 0;
5238 else
5239 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5240 }
252b5132 5241
29b0f896
AM		 5242 if (fake_zero_displacement)
5243 {
5244 /* Fakes a zero displacement assuming that i.types[op]
5245 holds the correct displacement size. */
5246 expressionS *exp;
5247
9c2799c2 5248 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5249 exp = &disp_expressions[i.disp_operands++];
5250 i.op[op].disps = exp;
5251 exp->X_op = O_constant;
5252 exp->X_add_number = 0;
5253 exp->X_add_symbol = (symbolS *) 0;
5254 exp->X_op_symbol = (symbolS *) 0;
5255 }
c0f3af97
L		 5256
5257 mem = op;
29b0f896 5258 }
c0f3af97
L		 5259 else
5260 mem = ~0;
252b5132 5261
29b0f896
AM		 5262 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5263 (if any) based on i.tm.extension_opcode. Again, we must be
5264 careful to make sure that segment/control/debug/test/MMX
5265 registers are coded into the i.rm.reg field. */
5266 if (i.reg_operands)
5267 {
99018f42 5268 unsigned int op;
7ab9ffdd
L		 5269 unsigned int vex_reg = ~0;
5270
5271 for (op = 0; op < i.operands; op++)
5272 if (i.types[op].bitfield.reg8
5273 || i.types[op].bitfield.reg16
5274 || i.types[op].bitfield.reg32
5275 || i.types[op].bitfield.reg64
5276 || i.types[op].bitfield.regmmx
5277 || i.types[op].bitfield.regxmm
5278 || i.types[op].bitfield.regymm
5279 || i.types[op].bitfield.sreg2
5280 || i.types[op].bitfield.sreg3
5281 || i.types[op].bitfield.control
5282 || i.types[op].bitfield.debug
5283 || i.types[op].bitfield.test)
5284 break;
c0209578 5285
7ab9ffdd
L		 5286 if (vex_3_sources)
5287 op = dest;
5288 else if (i.tm.opcode_modifier.vexnds)
5289 {
5290 /* For instructions with VexNDS, the register-only
5291 source operand is encoded in VEX prefix. */
5292 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5293
7ab9ffdd 5294 if (op > mem)
c0f3af97 5295 {
7ab9ffdd
L		 5296 vex_reg = op++;
5297 gas_assert (op < i.operands);
c0f3af97
L		 5298 }
5299 else
c0f3af97 5300 {
7ab9ffdd
L		 5301 vex_reg = op + 1;
5302 gas_assert (vex_reg < i.operands);
c0f3af97 5303 }
7ab9ffdd
L		 5304 }
5305 else if (i.tm.opcode_modifier.vexndd)
5306 {
5307 /* For instructions with VexNDD, there should be
5308 no memory operand and the register destination
5309 is encoded in VEX prefix. */
5310 gas_assert (i.mem_operands == 0
5311 && (op + 2) == i.operands);
5312 vex_reg = op + 1;
5313 }
5314 else
5315 gas_assert (op < i.operands);
99018f42 5316
7ab9ffdd
L		 5317 if (vex_reg != (unsigned int) ~0)
5318 {
5319 gas_assert (i.reg_operands == 2);
5320
5321 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
5322 & regxmm)
5323 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5324 &regymm))
5325 abort ();
5326 i.vex.register_specifier = i.op[vex_reg].regs;
5327 }
5328
5329 /* If there is an extension opcode to put here, the
5330 register number must be put into the regmem field. */
5331 if (i.tm.extension_opcode != None)
5332 {
5333 i.rm.regmem = i.op[op].regs->reg_num;
5334 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5335 i.rex |= REX_B;
5336 }
5337 else
5338 {
5339 i.rm.reg = i.op[op].regs->reg_num;
5340 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5341 i.rex |= REX_R;
5342 }
252b5132 5343
29b0f896
AM		 5344 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5345 must set it to 3 to indicate this is a register operand
5346 in the regmem field. */
5347 if (!i.mem_operands)
5348 i.rm.mode = 3;
5349 }
252b5132 5350
29b0f896 5351 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5352 if (i.tm.extension_opcode != None)
29b0f896
AM		 5353 i.rm.reg = i.tm.extension_opcode;
5354 }
5355 return default_seg;
5356}
252b5132 5357
29b0f896 5358static void
e3bb37b5 5359output_branch (void)
29b0f896
AM		 5360{
5361 char *p;
5362 int code16;
5363 int prefix;
5364 relax_substateT subtype;
5365 symbolS *sym;
5366 offsetT off;
5367
5368 code16 = 0;
5369 if (flag_code == CODE_16BIT)
5370 code16 = CODE16;
5371
5372 prefix = 0;
5373 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5374 {
29b0f896
AM		 5375 prefix = 1;
5376 i.prefixes -= 1;
5377 code16 ^= CODE16;
252b5132 5378 }
29b0f896
AM		 5379 /* Pentium4 branch hints. */
5380 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5381 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5382 {
29b0f896
AM		 5383 prefix++;
5384 i.prefixes--;
5385 }
5386 if (i.prefix[REX_PREFIX] != 0)
5387 {
5388 prefix++;
5389 i.prefixes--;
2f66722d
AM		 5390 }
5391
29b0f896
AM		 5392 if (i.prefixes != 0 && !intel_syntax)
5393 as_warn (_("skipping prefixes on this instruction"));
5394
5395 /* It's always a symbol; End frag & setup for relax.
5396 Make sure there is enough room in this frag for the largest
5397 instruction we may generate in md_convert_frag. This is 2
5398 bytes for the opcode and room for the prefix and largest
5399 displacement. */
5400 frag_grow (prefix + 2 + 4);
5401 /* Prefix and 1 opcode byte go in fr_fix. */
5402 p = frag_more (prefix + 1);
5403 if (i.prefix[DATA_PREFIX] != 0)
5404 *p++ = DATA_PREFIX_OPCODE;
5405 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5406 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5407 *p++ = i.prefix[SEG_PREFIX];
5408 if (i.prefix[REX_PREFIX] != 0)
5409 *p++ = i.prefix[REX_PREFIX];
5410 *p = i.tm.base_opcode;
5411
5412 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5413 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5414 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5415 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5416 else
5417 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5418 subtype |= code16;
3e73aa7c 5419
29b0f896
AM		 5420 sym = i.op[0].disps->X_add_symbol;
5421 off = i.op[0].disps->X_add_number;
3e73aa7c 5422
29b0f896
AM		 5423 if (i.op[0].disps->X_op != O_constant
5424 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5425 {
29b0f896
AM		 5426 /* Handle complex expressions. */
5427 sym = make_expr_symbol (i.op[0].disps);
5428 off = 0;
5429 }
3e73aa7c 5430
29b0f896
AM		 5431 /* 1 possible extra opcode + 4 byte displacement go in var part.
5432 Pass reloc in fr_var. */
5433 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5434}
3e73aa7c 5435
29b0f896 5436static void
e3bb37b5 5437output_jump (void)
29b0f896
AM		 5438{
5439 char *p;
5440 int size;
3e02c1cc 5441 fixS *fixP;
29b0f896 5442
40fb9820 5443 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5444 {
5445 /* This is a loop or jecxz type instruction. */
5446 size = 1;
5447 if (i.prefix[ADDR_PREFIX] != 0)
5448 {
5449 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5450 i.prefixes -= 1;
5451 }
5452 /* Pentium4 branch hints. */
5453 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5454 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5455 {
5456 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5457 i.prefixes--;
3e73aa7c
JH		 5458 }
5459 }
29b0f896
AM		 5460 else
5461 {
5462 int code16;
3e73aa7c 5463
29b0f896
AM		 5464 code16 = 0;
5465 if (flag_code == CODE_16BIT)
5466 code16 = CODE16;
3e73aa7c 5467
29b0f896
AM		 5468 if (i.prefix[DATA_PREFIX] != 0)
5469 {
5470 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5471 i.prefixes -= 1;
5472 code16 ^= CODE16;
5473 }
252b5132 5474
29b0f896
AM		 5475 size = 4;
5476 if (code16)
5477 size = 2;
5478 }
9fcc94b6 5479
29b0f896
AM		 5480 if (i.prefix[REX_PREFIX] != 0)
5481 {
5482 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5483 i.prefixes -= 1;
5484 }
252b5132 5485
29b0f896
AM		 5486 if (i.prefixes != 0 && !intel_syntax)
5487 as_warn (_("skipping prefixes on this instruction"));
e0890092 5488
29b0f896
AM		 5489 p = frag_more (1 + size);
5490 *p++ = i.tm.base_opcode;
e0890092 5491
3e02c1cc
AM		 5492 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5493 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5494
5495 /* All jumps handled here are signed, but don't use a signed limit
5496 check for 32 and 16 bit jumps as we want to allow wrap around at
5497 4G and 64k respectively. */
5498 if (size == 1)
5499 fixP->fx_signed = 1;
29b0f896 5500}
e0890092 5501
29b0f896 5502static void
e3bb37b5 5503output_interseg_jump (void)
29b0f896
AM		 5504{
5505 char *p;
5506 int size;
5507 int prefix;
5508 int code16;
252b5132 5509
29b0f896
AM		 5510 code16 = 0;
5511 if (flag_code == CODE_16BIT)
5512 code16 = CODE16;
a217f122 5513
29b0f896
AM		 5514 prefix = 0;
5515 if (i.prefix[DATA_PREFIX] != 0)
5516 {
5517 prefix = 1;
5518 i.prefixes -= 1;
5519 code16 ^= CODE16;
5520 }
5521 if (i.prefix[REX_PREFIX] != 0)
5522 {
5523 prefix++;
5524 i.prefixes -= 1;
5525 }
252b5132 5526
29b0f896
AM		 5527 size = 4;
5528 if (code16)
5529 size = 2;
252b5132 5530
29b0f896
AM		 5531 if (i.prefixes != 0 && !intel_syntax)
5532 as_warn (_("skipping prefixes on this instruction"));
252b5132 5533
29b0f896
AM		 5534 /* 1 opcode; 2 segment; offset */
5535 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5536
29b0f896
AM		 5537 if (i.prefix[DATA_PREFIX] != 0)
5538 *p++ = DATA_PREFIX_OPCODE;
252b5132 5539
29b0f896
AM		 5540 if (i.prefix[REX_PREFIX] != 0)
5541 *p++ = i.prefix[REX_PREFIX];
252b5132 5542
29b0f896
AM		 5543 *p++ = i.tm.base_opcode;
5544 if (i.op[1].imms->X_op == O_constant)
5545 {
5546 offsetT n = i.op[1].imms->X_add_number;
252b5132 5547
29b0f896
AM		 5548 if (size == 2
5549 && !fits_in_unsigned_word (n)
5550 && !fits_in_signed_word (n))
5551 {
5552 as_bad (_("16-bit jump out of range"));
5553 return;
5554 }
5555 md_number_to_chars (p, n, size);
5556 }
5557 else
5558 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5559 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5560 if (i.op[0].imms->X_op != O_constant)
5561 as_bad (_("can't handle non absolute segment in `%s'"),
5562 i.tm.name);
5563 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5564}
a217f122 5565
29b0f896 5566static void
e3bb37b5 5567output_insn (void)
29b0f896 5568{
2bbd9c25
JJ		 5569 fragS *insn_start_frag;
5570 offsetT insn_start_off;
5571
29b0f896
AM		 5572 /* Tie dwarf2 debug info to the address at the start of the insn.
5573 We can't do this after the insn has been output as the current
5574 frag may have been closed off. eg. by frag_var. */
5575 dwarf2_emit_insn (0);
5576
2bbd9c25
JJ		 5577 insn_start_frag = frag_now;
5578 insn_start_off = frag_now_fix ();
5579
29b0f896 5580 /* Output jumps. */
40fb9820 5581 if (i.tm.opcode_modifier.jump)
29b0f896 5582 output_branch ();
40fb9820
L		 5583 else if (i.tm.opcode_modifier.jumpbyte
5584 || i.tm.opcode_modifier.jumpdword)
29b0f896 5585 output_jump ();
40fb9820 5586 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5587 output_interseg_jump ();
5588 else
5589 {
5590 /* Output normal instructions here. */
5591 char *p;
5592 unsigned char *q;
47465058 5593 unsigned int j;
331d2d0d 5594 unsigned int prefix;
4dffcebc 5595
c0f3af97
L		 5596 /* Since the VEX prefix contains the implicit prefix, we don't
5597 need the explicit prefix. */
5598 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5599 {
c0f3af97 5600 switch (i.tm.opcode_length)
bc4bd9ab 5601 {
c0f3af97
L		 5602 case 3:
5603 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5604 {
c0f3af97
L		 5605 prefix = (i.tm.base_opcode >> 24) & 0xff;
5606 goto check_prefix;
5607 }
5608 break;
5609 case 2:
5610 if ((i.tm.base_opcode & 0xff0000) != 0)
5611 {
5612 prefix = (i.tm.base_opcode >> 16) & 0xff;
5613 if (i.tm.cpu_flags.bitfield.cpupadlock)
5614 {
4dffcebc 5615check_prefix:
c0f3af97
L		 5616 if (prefix != REPE_PREFIX_OPCODE
5617 || (i.prefix[LOCKREP_PREFIX]
5618 != REPE_PREFIX_OPCODE))
5619 add_prefix (prefix);
5620 }
5621 else
4dffcebc
L		 5622 add_prefix (prefix);
5623 }
c0f3af97
L		 5624 break;
5625 case 1:
5626 break;
5627 default:
5628 abort ();
bc4bd9ab 5629 }
c0f3af97
L		 5630
5631 /* The prefix bytes. */
5632 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5633 if (*q)
5634 FRAG_APPEND_1_CHAR (*q);
0f10071e 5635 }
252b5132 5636
c0f3af97
L		 5637 if (i.tm.opcode_modifier.vex)
5638 {
5639 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5640 if (*q)
5641 switch (j)
5642 {
5643 case REX_PREFIX:
5644 /* REX byte is encoded in VEX prefix. */
5645 break;
5646 case SEG_PREFIX:
5647 case ADDR_PREFIX:
5648 FRAG_APPEND_1_CHAR (*q);
5649 break;
5650 default:
5651 /* There should be no other prefixes for instructions
5652 with VEX prefix. */
5653 abort ();
5654 }
5655
5656 /* Now the VEX prefix. */
5657 p = frag_more (i.vex.length);
5658 for (j = 0; j < i.vex.length; j++)
5659 p[j] = i.vex.bytes[j];
5660 }
252b5132 5661
29b0f896 5662 /* Now the opcode; be careful about word order here! */
4dffcebc 5663 if (i.tm.opcode_length == 1)
29b0f896
AM		 5664 {
5665 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5666 }
5667 else
5668 {
4dffcebc 5669 switch (i.tm.opcode_length)
331d2d0d 5670 {
4dffcebc 5671 case 3:
331d2d0d
L		 5672 p = frag_more (3);
5673 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5674 break;
5675 case 2:
5676 p = frag_more (2);
5677 break;
5678 default:
5679 abort ();
5680 break;
331d2d0d 5681 }
0f10071e 5682
29b0f896
AM		 5683 /* Put out high byte first: can't use md_number_to_chars! */
5684 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5685 *p = i.tm.base_opcode & 0xff;
5686 }
3e73aa7c 5687
29b0f896 5688 /* Now the modrm byte and sib byte (if present). */
40fb9820 5689 if (i.tm.opcode_modifier.modrm)
29b0f896 5690 {
4a3523fa
L		 5691 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5692 | i.rm.reg << 3
5693 | i.rm.mode << 6));
29b0f896
AM		 5694 /* If i.rm.regmem == ESP (4)
5695 && i.rm.mode != (Register mode)
5696 && not 16 bit
5697 ==> need second modrm byte. */
5698 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5699 && i.rm.mode != 3
40fb9820 5700 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5701 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5702 | i.sib.index << 3
5703 | i.sib.scale << 6));
29b0f896 5704 }
3e73aa7c 5705
29b0f896 5706 if (i.disp_operands)
2bbd9c25 5707 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5708
29b0f896 5709 if (i.imm_operands)
2bbd9c25 5710 output_imm (insn_start_frag, insn_start_off);
29b0f896 5711 }
252b5132 5712
29b0f896
AM		 5713#ifdef DEBUG386
5714 if (flag_debug)
5715 {
7b81dfbb 5716 pi ("" /*line*/, &i);
29b0f896
AM		 5717 }
5718#endif /* DEBUG386 */
5719}
252b5132 5720
e205caa7
L		 5721/* Return the size of the displacement operand N. */
5722
5723static int
5724disp_size (unsigned int n)
5725{
5726 int size = 4;
40fb9820
L		 5727 if (i.types[n].bitfield.disp64)
5728 size = 8;
5729 else if (i.types[n].bitfield.disp8)
5730 size = 1;
5731 else if (i.types[n].bitfield.disp16)
5732 size = 2;
e205caa7
L		 5733 return size;
5734}
5735
5736/* Return the size of the immediate operand N. */
5737
5738static int
5739imm_size (unsigned int n)
5740{
5741 int size = 4;
40fb9820
L		 5742 if (i.types[n].bitfield.imm64)
5743 size = 8;
5744 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5745 size = 1;
5746 else if (i.types[n].bitfield.imm16)
5747 size = 2;
e205caa7
L		 5748 return size;
5749}
5750
29b0f896 5751static void
64e74474 5752output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5753{
5754 char *p;
5755 unsigned int n;
252b5132 5756
29b0f896
AM		 5757 for (n = 0; n < i.operands; n++)
5758 {
40fb9820 5759 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5760 {
5761 if (i.op[n].disps->X_op == O_constant)
5762 {
e205caa7 5763 int size = disp_size (n);
29b0f896 5764 offsetT val;
252b5132 5765
29b0f896
AM		 5766 val = offset_in_range (i.op[n].disps->X_add_number,
5767 size);
5768 p = frag_more (size);
5769 md_number_to_chars (p, val, size);
5770 }
5771 else
5772 {
f86103b7 5773 enum bfd_reloc_code_real reloc_type;
e205caa7 5774 int size = disp_size (n);
40fb9820 5775 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5776 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5777
e205caa7 5778 /* We can't have 8 bit displacement here. */
9c2799c2 5779 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 5780
29b0f896
AM		 5781 /* The PC relative address is computed relative
5782 to the instruction boundary, so in case immediate
5783 fields follows, we need to adjust the value. */
5784 if (pcrel && i.imm_operands)
5785 {
29b0f896 5786 unsigned int n1;
e205caa7 5787 int sz = 0;
252b5132 5788
29b0f896 5789 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5790 if (operand_type_check (i.types[n1], imm))
252b5132 5791 {
e205caa7
L		 5792 /* Only one immediate is allowed for PC
5793 relative address. */
9c2799c2 5794 gas_assert (sz == 0);
e205caa7
L		 5795 sz = imm_size (n1);
5796 i.op[n].disps->X_add_number -= sz;
252b5132 5797 }
29b0f896 5798 /* We should find the immediate. */
9c2799c2 5799 gas_assert (sz != 0);
29b0f896 5800 }
520dc8e8 5801
29b0f896 5802 p = frag_more (size);
2bbd9c25 5803 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5804 if (GOT_symbol
2bbd9c25 5805 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5806 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5807 || reloc_type == BFD_RELOC_X86_64_32S
5808 || (reloc_type == BFD_RELOC_64
5809 && object_64bit))
d6ab8113
JB		 5810 && (i.op[n].disps->X_op == O_symbol
5811 || (i.op[n].disps->X_op == O_add
5812 && ((symbol_get_value_expression
5813 (i.op[n].disps->X_op_symbol)->X_op)
5814 == O_subtract))))
5815 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5816 {
5817 offsetT add;
5818
5819 if (insn_start_frag == frag_now)
5820 add = (p - frag_now->fr_literal) - insn_start_off;
5821 else
5822 {
5823 fragS *fr;
5824
5825 add = insn_start_frag->fr_fix - insn_start_off;
5826 for (fr = insn_start_frag->fr_next;
5827 fr && fr != frag_now; fr = fr->fr_next)
5828 add += fr->fr_fix;
5829 add += p - frag_now->fr_literal;
5830 }
5831
4fa24527 5832 if (!object_64bit)
7b81dfbb
AJ		 5833 {
5834 reloc_type = BFD_RELOC_386_GOTPC;
5835 i.op[n].imms->X_add_number += add;
5836 }
5837 else if (reloc_type == BFD_RELOC_64)
5838 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5839 else
7b81dfbb
AJ		 5840 /* Don't do the adjustment for x86-64, as there
5841 the pcrel addressing is relative to the _next_
5842 insn, and that is taken care of in other code. */
d6ab8113 5843 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5844 }
062cd5e7 5845 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5846 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5847 }
5848 }
5849 }
5850}
252b5132 5851
29b0f896 5852static void
64e74474 5853output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5854{
5855 char *p;
5856 unsigned int n;
252b5132 5857
29b0f896
AM		 5858 for (n = 0; n < i.operands; n++)
5859 {
40fb9820 5860 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5861 {
5862 if (i.op[n].imms->X_op == O_constant)
5863 {
e205caa7 5864 int size = imm_size (n);
29b0f896 5865 offsetT val;
b4cac588 5866
29b0f896
AM		 5867 val = offset_in_range (i.op[n].imms->X_add_number,
5868 size);
5869 p = frag_more (size);
5870 md_number_to_chars (p, val, size);
5871 }
5872 else
5873 {
5874 /* Not absolute_section.
5875 Need a 32-bit fixup (don't support 8bit
5876 non-absolute imms). Try to support other
5877 sizes ... */
f86103b7 5878 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5879 int size = imm_size (n);
5880 int sign;
29b0f896 5881
40fb9820 5882 if (i.types[n].bitfield.imm32s
a7d61044 5883 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5884 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5885 sign = 1;
e205caa7
L		 5886 else
5887 sign = 0;
520dc8e8 5888
29b0f896
AM		 5889 p = frag_more (size);
5890 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5891
2bbd9c25
JJ		 5892 /* This is tough to explain. We end up with this one if we
5893 * have operands that look like
5894 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5895 * obtain the absolute address of the GOT, and it is strongly
5896 * preferable from a performance point of view to avoid using
5897 * a runtime relocation for this. The actual sequence of
5898 * instructions often look something like:
5899 *
5900 * call .L66
5901 * .L66:
5902 * popl %ebx
5903 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5904 *
5905 * The call and pop essentially return the absolute address
5906 * of the label .L66 and store it in %ebx. The linker itself
5907 * will ultimately change the first operand of the addl so
5908 * that %ebx points to the GOT, but to keep things simple, the
5909 * .o file must have this operand set so that it generates not
5910 * the absolute address of .L66, but the absolute address of
5911 * itself. This allows the linker itself simply treat a GOTPC
5912 * relocation as asking for a pcrel offset to the GOT to be
5913 * added in, and the addend of the relocation is stored in the
5914 * operand field for the instruction itself.
5915 *
5916 * Our job here is to fix the operand so that it would add
5917 * the correct offset so that %ebx would point to itself. The
5918 * thing that is tricky is that .-.L66 will point to the
5919 * beginning of the instruction, so we need to further modify
5920 * the operand so that it will point to itself. There are
5921 * other cases where you have something like:
5922 *
5923 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5924 *
5925 * and here no correction would be required. Internally in
5926 * the assembler we treat operands of this form as not being
5927 * pcrel since the '.' is explicitly mentioned, and I wonder
5928 * whether it would simplify matters to do it this way. Who
5929 * knows. In earlier versions of the PIC patches, the
5930 * pcrel_adjust field was used to store the correction, but
5931 * since the expression is not pcrel, I felt it would be
5932 * confusing to do it this way. */
5933
d6ab8113 5934 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5935 || reloc_type == BFD_RELOC_X86_64_32S
5936 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 5937 && GOT_symbol
5938 && GOT_symbol == i.op[n].imms->X_add_symbol
5939 && (i.op[n].imms->X_op == O_symbol
5940 || (i.op[n].imms->X_op == O_add
5941 && ((symbol_get_value_expression
5942 (i.op[n].imms->X_op_symbol)->X_op)
5943 == O_subtract))))
5944 {
2bbd9c25
JJ		 5945 offsetT add;
5946
5947 if (insn_start_frag == frag_now)
5948 add = (p - frag_now->fr_literal) - insn_start_off;
5949 else
5950 {
5951 fragS *fr;
5952
5953 add = insn_start_frag->fr_fix - insn_start_off;
5954 for (fr = insn_start_frag->fr_next;
5955 fr && fr != frag_now; fr = fr->fr_next)
5956 add += fr->fr_fix;
5957 add += p - frag_now->fr_literal;
5958 }
5959
4fa24527 5960 if (!object_64bit)
d6ab8113 5961 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 5962 else if (size == 4)
d6ab8113 5963 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 5964 else if (size == 8)
5965 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 5966 i.op[n].imms->X_add_number += add;
29b0f896 5967 }
29b0f896
AM		 5968 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5969 i.op[n].imms, 0, reloc_type);
5970 }
5971 }
5972 }
252b5132
RH		 5973}
5974\f
d182319b
JB		 5975/* x86_cons_fix_new is called via the expression parsing code when a
5976 reloc is needed. We use this hook to get the correct .got reloc. */
5977static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5978static int cons_sign = -1;
5979
5980void
e3bb37b5 5981x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 5982 expressionS *exp)
d182319b
JB		 5983{
5984 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5985
5986 got_reloc = NO_RELOC;
5987
5988#ifdef TE_PE
5989 if (exp->X_op == O_secrel)
5990 {
5991 exp->X_op = O_symbol;
5992 r = BFD_RELOC_32_SECREL;
5993 }
5994#endif
5995
5996 fix_new_exp (frag, off, len, exp, 0, r);
5997}
5998
718ddfc0
JB		 5999#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6000# define lex_got(reloc, adjust, types) NULL
6001#else
f3c180ae
AM		 6002/* Parse operands of the form
6003 <symbol>@GOTOFF+<nnn>
6004 and similar .plt or .got references.
6005
6006 If we find one, set up the correct relocation in RELOC and copy the
6007 input string, minus the `@GOTOFF' into a malloc'd buffer for
6008 parsing by the calling routine. Return this buffer, and if ADJUST
6009 is non-null set it to the length of the string we removed from the
6010 input line. Otherwise return NULL. */
6011static char *
3956db08 6012lex_got (enum bfd_reloc_code_real *reloc,
64e74474 6013 int *adjust,
40fb9820 6014 i386_operand_type *types)
f3c180ae 6015{
7b81dfbb
AJ		 6016 /* Some of the relocations depend on the size of what field is to
6017 be relocated. But in our callers i386_immediate and i386_displacement
6018 we don't yet know the operand size (this will be set by insn
6019 matching). Hence we record the word32 relocation here,
6020 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6021 static const struct {
6022 const char *str;
4fa24527 6023 const enum bfd_reloc_code_real rel[2];
40fb9820 6024 const i386_operand_type types64;
f3c180ae 6025 } gotrel[] = {
1e9cc1c2 6026 { "PLTOFF", { _dummy_first_bfd_reloc_code_real,
4eed87de 6027 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6028 OPERAND_TYPE_IMM64 },
4eed87de
AM		 6029 { "PLT", { BFD_RELOC_386_PLT32,
6030 BFD_RELOC_X86_64_PLT32 },
40fb9820 6031 OPERAND_TYPE_IMM32_32S_DISP32 },
1e9cc1c2 6032 { "GOTPLT", { _dummy_first_bfd_reloc_code_real,
4eed87de 6033 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6034 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6035 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
6036 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6037 OPERAND_TYPE_IMM64_DISP64 },
1e9cc1c2 6038 { "GOTPCREL", { _dummy_first_bfd_reloc_code_real,
4eed87de 6039 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6040 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6041 { "TLSGD", { BFD_RELOC_386_TLS_GD,
6042 BFD_RELOC_X86_64_TLSGD },
40fb9820 6043 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de 6044 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
1e9cc1c2 6045 _dummy_first_bfd_reloc_code_real },
40fb9820 6046 OPERAND_TYPE_NONE },
1e9cc1c2 6047 { "TLSLD", { _dummy_first_bfd_reloc_code_real,
4eed87de 6048 BFD_RELOC_X86_64_TLSLD },
40fb9820 6049 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6050 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
6051 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6052 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6053 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
6054 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6055 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de 6056 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
1e9cc1c2 6057 _dummy_first_bfd_reloc_code_real },
40fb9820 6058 OPERAND_TYPE_NONE },
4eed87de
AM		 6059 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
6060 BFD_RELOC_X86_64_DTPOFF32 },
7ab9ffdd 6061
40fb9820 6062 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de 6063 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
1e9cc1c2 6064 _dummy_first_bfd_reloc_code_real },
40fb9820 6065 OPERAND_TYPE_NONE },
4eed87de 6066 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
1e9cc1c2 6067 _dummy_first_bfd_reloc_code_real },
40fb9820 6068 OPERAND_TYPE_NONE },
4eed87de
AM		 6069 { "GOT", { BFD_RELOC_386_GOT32,
6070 BFD_RELOC_X86_64_GOT32 },
40fb9820 6071 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 6072 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
6073 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6074 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6075 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
6076 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6077 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6078 };
6079 char *cp;
6080 unsigned int j;
6081
718ddfc0
JB		 6082 if (!IS_ELF)
6083 return NULL;
6084
f3c180ae 6085 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6086 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6087 return NULL;
6088
47465058 6089 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 6090 {
6091 int len;
6092
6093 len = strlen (gotrel[j].str);
28f81592 6094 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6095 {
4fa24527 6096 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6097 {
28f81592
AM		 6098 int first, second;
6099 char *tmpbuf, *past_reloc;
f3c180ae 6100
4fa24527 6101 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 6102 if (adjust)
6103 *adjust = len;
f3c180ae 6104
3956db08
JB		 6105 if (types)
6106 {
6107 if (flag_code != CODE_64BIT)
40fb9820
L		 6108 {
6109 types->bitfield.imm32 = 1;
6110 types->bitfield.disp32 = 1;
6111 }
3956db08
JB		 6112 else
6113 *types = gotrel[j].types64;
6114 }
6115
f3c180ae
AM		 6116 if (GOT_symbol == NULL)
6117 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6118
28f81592 6119 /* The length of the first part of our input line. */
f3c180ae 6120 first = cp - input_line_pointer;
28f81592
AM		 6121
6122 /* The second part goes from after the reloc token until
67c11a9b 6123 (and including) an end_of_line char or comma. */
28f81592 6124 past_reloc = cp + 1 + len;
67c11a9b
AM		 6125 cp = past_reloc;
6126 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6127 ++cp;
6128 second = cp + 1 - past_reloc;
28f81592
AM		 6129
6130 /* Allocate and copy string. The trailing NUL shouldn't
6131 be necessary, but be safe. */
1e9cc1c2 6132 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6133 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6134 if (second != 0 && *past_reloc != ' ')
6135 /* Replace the relocation token with ' ', so that
6136 errors like foo@GOTOFF1 will be detected. */
6137 tmpbuf[first++] = ' ';
6138 memcpy (tmpbuf + first, past_reloc, second);
6139 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6140 return tmpbuf;
6141 }
6142
4fa24527
JB		 6143 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6144 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6145 return NULL;
6146 }
6147 }
6148
6149 /* Might be a symbol version string. Don't as_bad here. */
6150 return NULL;
6151}
6152
f3c180ae 6153void
e3bb37b5 6154x86_cons (expressionS *exp, int size)
f3c180ae 6155{
ee86248c
JB		 6156 intel_syntax = -intel_syntax;
6157
4fa24527 6158 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6159 {
6160 /* Handle @GOTOFF and the like in an expression. */
6161 char *save;
6162 char *gotfree_input_line;
6163 int adjust;
6164
6165 save = input_line_pointer;
3956db08 6166 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6167 if (gotfree_input_line)
6168 input_line_pointer = gotfree_input_line;
6169
6170 expression (exp);
6171
6172 if (gotfree_input_line)
6173 {
6174 /* expression () has merrily parsed up to the end of line,
6175 or a comma - in the wrong buffer. Transfer how far
6176 input_line_pointer has moved to the right buffer. */
6177 input_line_pointer = (save
6178 + (input_line_pointer - gotfree_input_line)
6179 + adjust);
6180 free (gotfree_input_line);
3992d3b7
AM		 6181 if (exp->X_op == O_constant
6182 || exp->X_op == O_absent
6183 || exp->X_op == O_illegal
6184 || exp->X_op == O_register
6185 || exp->X_op == O_big)
6186 {
6187 char c = *input_line_pointer;
6188 *input_line_pointer = 0;
6189 as_bad (_("missing or invalid expression `%s'"), save);
6190 *input_line_pointer = c;
6191 }
f3c180ae
AM		 6192 }
6193 }
6194 else
6195 expression (exp);
ee86248c
JB		 6196
6197 intel_syntax = -intel_syntax;
6198
6199 if (intel_syntax)
6200 i386_intel_simplify (exp);
f3c180ae
AM		 6201}
6202#endif
6203
d182319b 6204static void signed_cons (int size)
6482c264 6205{
d182319b
JB		 6206 if (flag_code == CODE_64BIT)
6207 cons_sign = 1;
6208 cons (size);
6209 cons_sign = -1;
6482c264
NC		 6210}
6211
d182319b 6212#ifdef TE_PE
6482c264
NC		 6213static void
6214pe_directive_secrel (dummy)
6215 int dummy ATTRIBUTE_UNUSED;
6216{
6217 expressionS exp;
6218
6219 do
6220 {
6221 expression (&exp);
6222 if (exp.X_op == O_symbol)
6223 exp.X_op = O_secrel;
6224
6225 emit_expr (&exp, 4);
6226 }
6227 while (*input_line_pointer++ == ',');
6228
6229 input_line_pointer--;
6230 demand_empty_rest_of_line ();
6231}
6482c264
NC		 6232#endif
6233
252b5132 6234static int
70e41ade 6235i386_immediate (char *imm_start)
252b5132
RH		 6236{
6237 char *save_input_line_pointer;
f3c180ae 6238 char *gotfree_input_line;
252b5132 6239 segT exp_seg = 0;
47926f60 6240 expressionS *exp;
40fb9820
L		 6241 i386_operand_type types;
6242
0dfbf9d7 6243 operand_type_set (&types, ~0);
252b5132
RH		 6244
6245 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6246 {
31b2323c
L		 6247 as_bad (_("at most %d immediate operands are allowed"),
6248 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6249 return 0;
6250 }
6251
6252 exp = &im_expressions[i.imm_operands++];
520dc8e8 6253 i.op[this_operand].imms = exp;
252b5132
RH		 6254
6255 if (is_space_char (*imm_start))
6256 ++imm_start;
6257
6258 save_input_line_pointer = input_line_pointer;
6259 input_line_pointer = imm_start;
6260
3956db08 6261 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6262 if (gotfree_input_line)
6263 input_line_pointer = gotfree_input_line;
252b5132
RH		 6264
6265 exp_seg = expression (exp);
6266
83183c0c 6267 SKIP_WHITESPACE ();
252b5132 6268 if (*input_line_pointer)
f3c180ae 6269 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6270
6271 input_line_pointer = save_input_line_pointer;
f3c180ae 6272 if (gotfree_input_line)
ee86248c
JB		 6273 {
6274 free (gotfree_input_line);
6275
6276 if (exp->X_op == O_constant || exp->X_op == O_register)
6277 exp->X_op = O_illegal;
6278 }
6279
6280 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6281}
252b5132 6282
ee86248c
JB		 6283static int
6284i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6285 i386_operand_type types, const char *imm_start)
6286{
6287 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6288 {
3992d3b7 6289 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 6290 imm_start);
3992d3b7 6291 return 0;
252b5132 6292 }
3e73aa7c 6293 else if (exp->X_op == O_constant)
252b5132 6294 {
47926f60 6295 /* Size it properly later. */
40fb9820 6296 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6297 /* If BFD64, sign extend val. */
4eed87de
AM		 6298 if (!use_rela_relocations
6299 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6300 exp->X_add_number
6301 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6302 }
4c63da97 6303#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6304 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6305 && exp_seg != absolute_section
47926f60 6306 && exp_seg != text_section
24eab124
AM		 6307 && exp_seg != data_section
6308 && exp_seg != bss_section
6309 && exp_seg != undefined_section
f86103b7 6310 && !bfd_is_com_section (exp_seg))
252b5132 6311 {
d0b47220 6312 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6313 return 0;
6314 }
6315#endif
bb8f5920
L		 6316 else if (!intel_syntax && exp->X_op == O_register)
6317 {
6318 as_bad (_("illegal immediate register operand %s"), imm_start);
6319 return 0;
6320 }
252b5132
RH		 6321 else
6322 {
6323 /* This is an address. The size of the address will be
24eab124 6324 determined later, depending on destination register,
3e73aa7c 6325 suffix, or the default for the section. */
40fb9820
L		 6326 i.types[this_operand].bitfield.imm8 = 1;
6327 i.types[this_operand].bitfield.imm16 = 1;
6328 i.types[this_operand].bitfield.imm32 = 1;
6329 i.types[this_operand].bitfield.imm32s = 1;
6330 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6331 i.types[this_operand] = operand_type_and (i.types[this_operand],
6332 types);
252b5132
RH		 6333 }
6334
6335 return 1;
6336}
6337
551c1ca1 6338static char *
e3bb37b5 6339i386_scale (char *scale)
252b5132 6340{
551c1ca1
AM		 6341 offsetT val;
6342 char *save = input_line_pointer;
252b5132 6343
551c1ca1
AM		 6344 input_line_pointer = scale;
6345 val = get_absolute_expression ();
6346
6347 switch (val)
252b5132 6348 {
551c1ca1 6349 case 1:
252b5132
RH		 6350 i.log2_scale_factor = 0;
6351 break;
551c1ca1 6352 case 2:
252b5132
RH		 6353 i.log2_scale_factor = 1;
6354 break;
551c1ca1 6355 case 4:
252b5132
RH		 6356 i.log2_scale_factor = 2;
6357 break;
551c1ca1 6358 case 8:
252b5132
RH		 6359 i.log2_scale_factor = 3;
6360 break;
6361 default:
a724f0f4
JB		 6362 {
6363 char sep = *input_line_pointer;
6364
6365 *input_line_pointer = '\0';
6366 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6367 scale);
6368 *input_line_pointer = sep;
6369 input_line_pointer = save;
6370 return NULL;
6371 }
252b5132 6372 }
29b0f896 6373 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6374 {
6375 as_warn (_("scale factor of %d without an index register"),
24eab124 6376 1 << i.log2_scale_factor);
252b5132 6377 i.log2_scale_factor = 0;
252b5132 6378 }
551c1ca1
AM		 6379 scale = input_line_pointer;
6380 input_line_pointer = save;
6381 return scale;
252b5132
RH		 6382}
6383
252b5132 6384static int
e3bb37b5 6385i386_displacement (char *disp_start, char *disp_end)
252b5132 6386{
29b0f896 6387 expressionS *exp;
252b5132
RH		 6388 segT exp_seg = 0;
6389 char *save_input_line_pointer;
f3c180ae 6390 char *gotfree_input_line;
40fb9820
L		 6391 int override;
6392 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6393 int ret;
252b5132 6394
31b2323c
L		 6395 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6396 {
6397 as_bad (_("at most %d displacement operands are allowed"),
6398 MAX_MEMORY_OPERANDS);
6399 return 0;
6400 }
6401
0dfbf9d7 6402 operand_type_set (&bigdisp, 0);
40fb9820
L		 6403 if ((i.types[this_operand].bitfield.jumpabsolute)
6404 || (!current_templates->start->opcode_modifier.jump
6405 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6406 {
40fb9820 6407 bigdisp.bitfield.disp32 = 1;
e05278af 6408 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6409 if (flag_code == CODE_64BIT)
6410 {
6411 if (!override)
6412 {
6413 bigdisp.bitfield.disp32s = 1;
6414 bigdisp.bitfield.disp64 = 1;
6415 }
6416 }
6417 else if ((flag_code == CODE_16BIT) ^ override)
6418 {
6419 bigdisp.bitfield.disp32 = 0;
6420 bigdisp.bitfield.disp16 = 1;
6421 }
e05278af
JB		 6422 }
6423 else
6424 {
6425 /* For PC-relative branches, the width of the displacement
6426 is dependent upon data size, not address size. */
e05278af 6427 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6428 if (flag_code == CODE_64BIT)
6429 {
6430 if (override || i.suffix == WORD_MNEM_SUFFIX)
6431 bigdisp.bitfield.disp16 = 1;
6432 else
6433 {
6434 bigdisp.bitfield.disp32 = 1;
6435 bigdisp.bitfield.disp32s = 1;
6436 }
6437 }
6438 else
e05278af
JB		 6439 {
6440 if (!override)
6441 override = (i.suffix == (flag_code != CODE_16BIT
6442 ? WORD_MNEM_SUFFIX
6443 : LONG_MNEM_SUFFIX));
40fb9820
L		 6444 bigdisp.bitfield.disp32 = 1;
6445 if ((flag_code == CODE_16BIT) ^ override)
6446 {
6447 bigdisp.bitfield.disp32 = 0;
6448 bigdisp.bitfield.disp16 = 1;
6449 }
e05278af 6450 }
e05278af 6451 }
c6fb90c8
L		 6452 i.types[this_operand] = operand_type_or (i.types[this_operand],
6453 bigdisp);
252b5132
RH		 6454
6455 exp = &disp_expressions[i.disp_operands];
520dc8e8 6456 i.op[this_operand].disps = exp;
252b5132
RH		 6457 i.disp_operands++;
6458 save_input_line_pointer = input_line_pointer;
6459 input_line_pointer = disp_start;
6460 END_STRING_AND_SAVE (disp_end);
6461
6462#ifndef GCC_ASM_O_HACK
6463#define GCC_ASM_O_HACK 0
6464#endif
6465#if GCC_ASM_O_HACK
6466 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6467 if (i.types[this_operand].bitfield.baseIndex
24eab124 6468 && displacement_string_end[-1] == '+')
252b5132
RH		 6469 {
6470 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6471 constraint within gcc asm statements.
6472 For instance:
6473
6474 #define _set_tssldt_desc(n,addr,limit,type) \
6475 __asm__ __volatile__ ( \
6476 "movw %w2,%0\n\t" \
6477 "movw %w1,2+%0\n\t" \
6478 "rorl $16,%1\n\t" \
6479 "movb %b1,4+%0\n\t" \
6480 "movb %4,5+%0\n\t" \
6481 "movb $0,6+%0\n\t" \
6482 "movb %h1,7+%0\n\t" \
6483 "rorl $16,%1" \
6484 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6485
6486 This works great except that the output assembler ends
6487 up looking a bit weird if it turns out that there is
6488 no offset. You end up producing code that looks like:
6489
6490 #APP
6491 movw $235,(%eax)
6492 movw %dx,2+(%eax)
6493 rorl $16,%edx
6494 movb %dl,4+(%eax)
6495 movb $137,5+(%eax)
6496 movb $0,6+(%eax)
6497 movb %dh,7+(%eax)
6498 rorl $16,%edx
6499 #NO_APP
6500
47926f60 6501 So here we provide the missing zero. */
24eab124
AM		 6502
6503 *displacement_string_end = '0';
252b5132
RH		 6504 }
6505#endif
3956db08 6506 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6507 if (gotfree_input_line)
6508 input_line_pointer = gotfree_input_line;
252b5132 6509
24eab124 6510 exp_seg = expression (exp);
252b5132 6511
636c26b0
AM		 6512 SKIP_WHITESPACE ();
6513 if (*input_line_pointer)
6514 as_bad (_("junk `%s' after expression"), input_line_pointer);
6515#if GCC_ASM_O_HACK
6516 RESTORE_END_STRING (disp_end + 1);
6517#endif
636c26b0 6518 input_line_pointer = save_input_line_pointer;
636c26b0 6519 if (gotfree_input_line)
ee86248c
JB		 6520 {
6521 free (gotfree_input_line);
6522
6523 if (exp->X_op == O_constant || exp->X_op == O_register)
6524 exp->X_op = O_illegal;
6525 }
6526
6527 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6528
6529 RESTORE_END_STRING (disp_end);
6530
6531 return ret;
6532}
6533
6534static int
6535i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6536 i386_operand_type types, const char *disp_start)
6537{
6538 i386_operand_type bigdisp;
6539 int ret = 1;
636c26b0 6540
24eab124
AM		 6541 /* We do this to make sure that the section symbol is in
6542 the symbol table. We will ultimately change the relocation
47926f60 6543 to be relative to the beginning of the section. */
1ae12ab7 6544 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6545 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6546 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6547 {
636c26b0 6548 if (exp->X_op != O_symbol)
3992d3b7 6549 goto inv_disp;
636c26b0 6550
e5cb08ac 6551 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6552 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6553 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6554 exp->X_op = O_subtract;
6555 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6556 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6557 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6558 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6559 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6560 else
29b0f896 6561 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6562 }
252b5132 6563
3992d3b7
AM		 6564 else if (exp->X_op == O_absent
6565 || exp->X_op == O_illegal
ee86248c 6566 || exp->X_op == O_big)
2daf4fd8 6567 {
3992d3b7
AM		 6568 inv_disp:
6569 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6570 disp_start);
3992d3b7 6571 ret = 0;
2daf4fd8
AM		 6572 }
6573
0e1147d9
L		 6574 else if (flag_code == CODE_64BIT
6575 && !i.prefix[ADDR_PREFIX]
6576 && exp->X_op == O_constant)
6577 {
6578 /* Since displacement is signed extended to 64bit, don't allow
6579 disp32 and turn off disp32s if they are out of range. */
6580 i.types[this_operand].bitfield.disp32 = 0;
6581 if (!fits_in_signed_long (exp->X_add_number))
6582 {
6583 i.types[this_operand].bitfield.disp32s = 0;
6584 if (i.types[this_operand].bitfield.baseindex)
6585 {
6586 as_bad (_("0x%lx out range of signed 32bit displacement"),
6587 (long) exp->X_add_number);
6588 ret = 0;
6589 }
6590 }
6591 }
6592
4c63da97 6593#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6594 else if (exp->X_op != O_constant
6595 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6596 && exp_seg != absolute_section
6597 && exp_seg != text_section
6598 && exp_seg != data_section
6599 && exp_seg != bss_section
6600 && exp_seg != undefined_section
6601 && !bfd_is_com_section (exp_seg))
24eab124 6602 {
d0b47220 6603 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6604 ret = 0;
24eab124 6605 }
252b5132 6606#endif
3956db08 6607
40fb9820
L		 6608 /* Check if this is a displacement only operand. */
6609 bigdisp = i.types[this_operand];
6610 bigdisp.bitfield.disp8 = 0;
6611 bigdisp.bitfield.disp16 = 0;
6612 bigdisp.bitfield.disp32 = 0;
6613 bigdisp.bitfield.disp32s = 0;
6614 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6615 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6616 i.types[this_operand] = operand_type_and (i.types[this_operand],
6617 types);
3956db08 6618
3992d3b7 6619 return ret;
252b5132
RH		 6620}
6621
eecb386c 6622/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6623 Return 1 on success, 0 on a failure. */
6624
252b5132 6625static int
e3bb37b5 6626i386_index_check (const char *operand_string)
252b5132 6627{
3e73aa7c 6628 int ok;
fc0763e6 6629 const char *kind = "base/index";
24eab124 6630#if INFER_ADDR_PREFIX
eecb386c
AM		 6631 int fudged = 0;
6632
24eab124
AM		 6633 tryprefix:
6634#endif
3e73aa7c 6635 ok = 1;
fc0763e6
JB		 6636 if (current_templates->start->opcode_modifier.isstring
6637 && !current_templates->start->opcode_modifier.immext
6638 && (current_templates->end[-1].opcode_modifier.isstring
6639 || i.mem_operands))
6640 {
6641 /* Memory operands of string insns are special in that they only allow
6642 a single register (rDI, rSI, or rBX) as their memory address. */
6643 unsigned int expected;
6644
6645 kind = "string address";
6646
6647 if (current_templates->start->opcode_modifier.w)
6648 {
6649 i386_operand_type type = current_templates->end[-1].operand_types[0];
6650
6651 if (!type.bitfield.baseindex
6652 || ((!i.mem_operands != !intel_syntax)
6653 && current_templates->end[-1].operand_types[1]
6654 .bitfield.baseindex))
6655 type = current_templates->end[-1].operand_types[1];
6656 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6657 }
6658 else
6659 expected = 3 /* rBX */;
6660
6661 if (!i.base_reg || i.index_reg
6662 || operand_type_check (i.types[this_operand], disp))
6663 ok = -1;
6664 else if (!(flag_code == CODE_64BIT
6665 ? i.prefix[ADDR_PREFIX]
6666 ? i.base_reg->reg_type.bitfield.reg32
6667 : i.base_reg->reg_type.bitfield.reg64
6668 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6669 ? i.base_reg->reg_type.bitfield.reg32
6670 : i.base_reg->reg_type.bitfield.reg16))
6671 ok = 0;
6672 else if (i.base_reg->reg_num != expected)
6673 ok = -1;
6674
6675 if (ok < 0)
6676 {
6677 unsigned int j;
6678
6679 for (j = 0; j < i386_regtab_size; ++j)
6680 if ((flag_code == CODE_64BIT
6681 ? i.prefix[ADDR_PREFIX]
6682 ? i386_regtab[j].reg_type.bitfield.reg32
6683 : i386_regtab[j].reg_type.bitfield.reg64
6684 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6685 ? i386_regtab[j].reg_type.bitfield.reg32
6686 : i386_regtab[j].reg_type.bitfield.reg16)
6687 && i386_regtab[j].reg_num == expected)
6688 break;
9c2799c2 6689 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 6690 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6691 operand_string,
6692 intel_syntax ? '[' : '(',
6693 register_prefix,
6694 i386_regtab[j].reg_name,
6695 intel_syntax ? ']' : ')');
6696 ok = 1;
6697 }
6698 }
6699 else if (flag_code == CODE_64BIT)
64e74474 6700 {
64e74474 6701 if ((i.base_reg
40fb9820
L		 6702 && ((i.prefix[ADDR_PREFIX] == 0
6703 && !i.base_reg->reg_type.bitfield.reg64)
6704 || (i.prefix[ADDR_PREFIX]
6705 && !i.base_reg->reg_type.bitfield.reg32))
6706 && (i.index_reg
9a04903e
JB		 6707 || i.base_reg->reg_num !=
6708 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6709 || (i.index_reg
40fb9820
L		 6710 && (!i.index_reg->reg_type.bitfield.baseindex
6711 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6712 && i.index_reg->reg_num != RegRiz
6713 && !i.index_reg->reg_type.bitfield.reg64
6714 )
40fb9820 6715 || (i.prefix[ADDR_PREFIX]
db51cc60 6716 && i.index_reg->reg_num != RegEiz
40fb9820 6717 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6718 ok = 0;
3e73aa7c
JH		 6719 }
6720 else
6721 {
6722 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6723 {
6724 /* 16bit checks. */
6725 if ((i.base_reg
40fb9820
L		 6726 && (!i.base_reg->reg_type.bitfield.reg16
6727 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6728 || (i.index_reg
40fb9820
L		 6729 && (!i.index_reg->reg_type.bitfield.reg16
6730 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6731 || !(i.base_reg
6732 && i.base_reg->reg_num < 6
6733 && i.index_reg->reg_num >= 6
6734 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6735 ok = 0;
6736 }
6737 else
e5cb08ac 6738 {
3e73aa7c
JH		 6739 /* 32bit checks. */
6740 if ((i.base_reg
40fb9820 6741 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6742 || (i.index_reg
db51cc60
L		 6743 && ((!i.index_reg->reg_type.bitfield.reg32
6744 && i.index_reg->reg_num != RegEiz)
40fb9820 6745 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6746 ok = 0;
3e73aa7c
JH		 6747 }
6748 }
6749 if (!ok)
24eab124
AM		 6750 {
6751#if INFER_ADDR_PREFIX
fc0763e6 6752 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 6753 {
6754 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6755 i.prefixes += 1;
b23bac36
AM		 6756 /* Change the size of any displacement too. At most one of
6757 Disp16 or Disp32 is set.
6758 FIXME. There doesn't seem to be any real need for separate
6759 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6760 Removing them would probably clean up the code quite a lot. */
4eed87de 6761 if (flag_code != CODE_64BIT
40fb9820
L		 6762 && (i.types[this_operand].bitfield.disp16
6763 || i.types[this_operand].bitfield.disp32))
6764 i.types[this_operand]
c6fb90c8 6765 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6766 fudged = 1;
24eab124
AM		 6767 goto tryprefix;
6768 }
eecb386c 6769 if (fudged)
fc0763e6
JB		 6770 as_bad (_("`%s' is not a valid %s expression"),
6771 operand_string,
6772 kind);
eecb386c 6773 else
c388dee8 6774#endif
fc0763e6 6775 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 6776 operand_string,
fc0763e6
JB		 6777 flag_code_names[i.prefix[ADDR_PREFIX]
6778 ? flag_code == CODE_32BIT
6779 ? CODE_16BIT
6780 : CODE_32BIT
6781 : flag_code],
6782 kind);
24eab124 6783 }
20f0a1fc 6784 return ok;
24eab124 6785}
252b5132 6786
fc0763e6 6787/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 6788 on error. */
252b5132 6789
252b5132 6790static int
a7619375 6791i386_att_operand (char *operand_string)
252b5132 6792{
af6bdddf
AM		 6793 const reg_entry *r;
6794 char *end_op;
24eab124 6795 char *op_string = operand_string;
252b5132 6796
24eab124 6797 if (is_space_char (*op_string))
252b5132
RH		 6798 ++op_string;
6799
24eab124 6800 /* We check for an absolute prefix (differentiating,
47926f60 6801 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6802 if (*op_string == ABSOLUTE_PREFIX)
6803 {
6804 ++op_string;
6805 if (is_space_char (*op_string))
6806 ++op_string;
40fb9820 6807 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6808 }
252b5132 6809
47926f60 6810 /* Check if operand is a register. */
4d1bb795 6811 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6812 {
40fb9820
L		 6813 i386_operand_type temp;
6814
24eab124
AM		 6815 /* Check for a segment override by searching for ':' after a
6816 segment register. */
6817 op_string = end_op;
6818 if (is_space_char (*op_string))
6819 ++op_string;
40fb9820
L		 6820 if (*op_string == ':'
6821 && (r->reg_type.bitfield.sreg2
6822 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6823 {
6824 switch (r->reg_num)
6825 {
6826 case 0:
6827 i.seg[i.mem_operands] = &es;
6828 break;
6829 case 1:
6830 i.seg[i.mem_operands] = &cs;
6831 break;
6832 case 2:
6833 i.seg[i.mem_operands] = &ss;
6834 break;
6835 case 3:
6836 i.seg[i.mem_operands] = &ds;
6837 break;
6838 case 4:
6839 i.seg[i.mem_operands] = &fs;
6840 break;
6841 case 5:
6842 i.seg[i.mem_operands] = &gs;
6843 break;
6844 }
252b5132 6845
24eab124 6846 /* Skip the ':' and whitespace. */
252b5132
RH		 6847 ++op_string;
6848 if (is_space_char (*op_string))
24eab124 6849 ++op_string;
252b5132 6850
24eab124
AM		 6851 if (!is_digit_char (*op_string)
6852 && !is_identifier_char (*op_string)
6853 && *op_string != '('
6854 && *op_string != ABSOLUTE_PREFIX)
6855 {
6856 as_bad (_("bad memory operand `%s'"), op_string);
6857 return 0;
6858 }
47926f60 6859 /* Handle case of %es:*foo. */
24eab124
AM		 6860 if (*op_string == ABSOLUTE_PREFIX)
6861 {
6862 ++op_string;
6863 if (is_space_char (*op_string))
6864 ++op_string;
40fb9820 6865 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6866 }
6867 goto do_memory_reference;
6868 }
6869 if (*op_string)
6870 {
d0b47220 6871 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6872 return 0;
6873 }
40fb9820
L		 6874 temp = r->reg_type;
6875 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6876 i.types[this_operand] = operand_type_or (i.types[this_operand],
6877 temp);
7d5e4556 6878 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 6879 i.op[this_operand].regs = r;
24eab124
AM		 6880 i.reg_operands++;
6881 }
af6bdddf
AM		 6882 else if (*op_string == REGISTER_PREFIX)
6883 {
6884 as_bad (_("bad register name `%s'"), op_string);
6885 return 0;
6886 }
24eab124 6887 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6888 {
24eab124 6889 ++op_string;
40fb9820 6890 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6891 {
d0b47220 6892 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6893 return 0;
6894 }
6895 if (!i386_immediate (op_string))
6896 return 0;
6897 }
6898 else if (is_digit_char (*op_string)
6899 || is_identifier_char (*op_string)
e5cb08ac 6900 || *op_string == '(')
24eab124 6901 {
47926f60 6902 /* This is a memory reference of some sort. */
af6bdddf 6903 char *base_string;
252b5132 6904
47926f60 6905 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 6906 char *displacement_string_start;
6907 char *displacement_string_end;
252b5132 6908
24eab124 6909 do_memory_reference:
24eab124 6910 if ((i.mem_operands == 1
40fb9820 6911 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 6912 || i.mem_operands == 2)
6913 {
6914 as_bad (_("too many memory references for `%s'"),
6915 current_templates->start->name);
6916 return 0;
6917 }
252b5132 6918
24eab124
AM		 6919 /* Check for base index form. We detect the base index form by
6920 looking for an ')' at the end of the operand, searching
6921 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6922 after the '('. */
af6bdddf 6923 base_string = op_string + strlen (op_string);
c3332e24 6924
af6bdddf
AM		 6925 --base_string;
6926 if (is_space_char (*base_string))
6927 --base_string;
252b5132 6928
47926f60 6929 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 6930 displacement_string_start = op_string;
6931 displacement_string_end = base_string + 1;
252b5132 6932
24eab124
AM		 6933 if (*base_string == ')')
6934 {
af6bdddf 6935 char *temp_string;
24eab124
AM		 6936 unsigned int parens_balanced = 1;
6937 /* We've already checked that the number of left & right ()'s are
47926f60 6938 equal, so this loop will not be infinite. */
24eab124
AM		 6939 do
6940 {
6941 base_string--;
6942 if (*base_string == ')')
6943 parens_balanced++;
6944 if (*base_string == '(')
6945 parens_balanced--;
6946 }
6947 while (parens_balanced);
c3332e24 6948
af6bdddf 6949 temp_string = base_string;
c3332e24 6950
24eab124 6951 /* Skip past '(' and whitespace. */
252b5132
RH		 6952 ++base_string;
6953 if (is_space_char (*base_string))
24eab124 6954 ++base_string;
252b5132 6955
af6bdddf 6956 if (*base_string == ','
4eed87de
AM		 6957 || ((i.base_reg = parse_register (base_string, &end_op))
6958 != NULL))
252b5132 6959 {
af6bdddf 6960 displacement_string_end = temp_string;
252b5132 6961
40fb9820 6962 i.types[this_operand].bitfield.baseindex = 1;
252b5132 6963
af6bdddf 6964 if (i.base_reg)
24eab124 6965 {
24eab124
AM		 6966 base_string = end_op;
6967 if (is_space_char (*base_string))
6968 ++base_string;
af6bdddf
AM		 6969 }
6970
6971 /* There may be an index reg or scale factor here. */
6972 if (*base_string == ',')
6973 {
6974 ++base_string;
6975 if (is_space_char (*base_string))
6976 ++base_string;
6977
4eed87de
AM		 6978 if ((i.index_reg = parse_register (base_string, &end_op))
6979 != NULL)
24eab124 6980 {
af6bdddf 6981 base_string = end_op;
24eab124
AM		 6982 if (is_space_char (*base_string))
6983 ++base_string;
af6bdddf
AM		 6984 if (*base_string == ',')
6985 {
6986 ++base_string;
6987 if (is_space_char (*base_string))
6988 ++base_string;
6989 }
e5cb08ac 6990 else if (*base_string != ')')
af6bdddf 6991 {
4eed87de
AM		 6992 as_bad (_("expecting `,' or `)' "
6993 "after index register in `%s'"),
af6bdddf
AM		 6994 operand_string);
6995 return 0;
6996 }
24eab124 6997 }
af6bdddf 6998 else if (*base_string == REGISTER_PREFIX)
24eab124 6999 {
af6bdddf 7000 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7001 return 0;
7002 }
252b5132 7003
47926f60 7004 /* Check for scale factor. */
551c1ca1 7005 if (*base_string != ')')
af6bdddf 7006 {
551c1ca1
AM		 7007 char *end_scale = i386_scale (base_string);
7008
7009 if (!end_scale)
af6bdddf 7010 return 0;
24eab124 7011
551c1ca1 7012 base_string = end_scale;
af6bdddf
AM		 7013 if (is_space_char (*base_string))
7014 ++base_string;
7015 if (*base_string != ')')
7016 {
4eed87de
AM		 7017 as_bad (_("expecting `)' "
7018 "after scale factor in `%s'"),
af6bdddf
AM		 7019 operand_string);
7020 return 0;
7021 }
7022 }
7023 else if (!i.index_reg)
24eab124 7024 {
4eed87de
AM		 7025 as_bad (_("expecting index register or scale factor "
7026 "after `,'; got '%c'"),
af6bdddf 7027 *base_string);
24eab124
AM		 7028 return 0;
7029 }
7030 }
af6bdddf 7031 else if (*base_string != ')')
24eab124 7032 {
4eed87de
AM		 7033 as_bad (_("expecting `,' or `)' "
7034 "after base register in `%s'"),
af6bdddf 7035 operand_string);
24eab124
AM		 7036 return 0;
7037 }
c3332e24 7038 }
af6bdddf 7039 else if (*base_string == REGISTER_PREFIX)
c3332e24 7040 {
af6bdddf 7041 as_bad (_("bad register name `%s'"), base_string);
24eab124 7042 return 0;
c3332e24 7043 }
24eab124
AM		 7044 }
7045
7046 /* If there's an expression beginning the operand, parse it,
7047 assuming displacement_string_start and
7048 displacement_string_end are meaningful. */
7049 if (displacement_string_start != displacement_string_end)
7050 {
7051 if (!i386_displacement (displacement_string_start,
7052 displacement_string_end))
7053 return 0;
7054 }
7055
7056 /* Special case for (%dx) while doing input/output op. */
7057 if (i.base_reg
0dfbf9d7
L		 7058 && operand_type_equal (&i.base_reg->reg_type,
7059 &reg16_inoutportreg)
24eab124
AM		 7060 && i.index_reg == 0
7061 && i.log2_scale_factor == 0
7062 && i.seg[i.mem_operands] == 0
40fb9820 7063 && !operand_type_check (i.types[this_operand], disp))
24eab124 7064 {
65da13b5 7065 i.types[this_operand] = inoutportreg;
24eab124
AM		 7066 return 1;
7067 }
7068
eecb386c
AM		 7069 if (i386_index_check (operand_string) == 0)
7070 return 0;
5c07affc 7071 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7072 i.mem_operands++;
7073 }
7074 else
ce8a8b2f
AM		 7075 {
7076 /* It's not a memory operand; argh! */
24eab124
AM		 7077 as_bad (_("invalid char %s beginning operand %d `%s'"),
7078 output_invalid (*op_string),
7079 this_operand + 1,
7080 op_string);
7081 return 0;
7082 }
47926f60 7083 return 1; /* Normal return. */
252b5132
RH		 7084}
7085\f
ee7fcc42
AM		 7086/* md_estimate_size_before_relax()
7087
7088 Called just before relax() for rs_machine_dependent frags. The x86
7089 assembler uses these frags to handle variable size jump
7090 instructions.
7091
7092 Any symbol that is now undefined will not become defined.
7093 Return the correct fr_subtype in the frag.
7094 Return the initial "guess for variable size of frag" to caller.
7095 The guess is actually the growth beyond the fixed part. Whatever
7096 we do to grow the fixed or variable part contributes to our
7097 returned value. */
7098
252b5132
RH		 7099int
7100md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7101 fragS *fragP;
7102 segT segment;
252b5132 7103{
252b5132 7104 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7105 check for un-relaxable symbols. On an ELF system, we can't relax
7106 an externally visible symbol, because it may be overridden by a
7107 shared library. */
7108 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7109#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7110 || (IS_ELF
31312f95 7111 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7112 || S_IS_WEAK (fragP->fr_symbol)
7113 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7114 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7115#endif
7116#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7117 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7118 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7119#endif
7120 )
252b5132 7121 {
b98ef147
AM		 7122 /* Symbol is undefined in this segment, or we need to keep a
7123 reloc so that weak symbols can be overridden. */
7124 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7125 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7126 unsigned char *opcode;
7127 int old_fr_fix;
f6af82bd 7128
ee7fcc42 7129 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7130 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7131 else if (size == 2)
f6af82bd
AM		 7132 reloc_type = BFD_RELOC_16_PCREL;
7133 else
7134 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7135
ee7fcc42
AM		 7136 old_fr_fix = fragP->fr_fix;
7137 opcode = (unsigned char *) fragP->fr_opcode;
7138
fddf5b5b 7139 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7140 {
fddf5b5b
AM		 7141 case UNCOND_JUMP:
7142 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7143 opcode[0] = 0xe9;
252b5132 7144 fragP->fr_fix += size;
062cd5e7
AS		 7145 fix_new (fragP, old_fr_fix, size,
7146 fragP->fr_symbol,
7147 fragP->fr_offset, 1,
7148 reloc_type);
252b5132
RH		 7149 break;
7150
fddf5b5b 7151 case COND_JUMP86:
412167cb
AM		 7152 if (size == 2
7153 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7154 {
7155 /* Negate the condition, and branch past an
7156 unconditional jump. */
7157 opcode[0] ^= 1;
7158 opcode[1] = 3;
7159 /* Insert an unconditional jump. */
7160 opcode[2] = 0xe9;
7161 /* We added two extra opcode bytes, and have a two byte
7162 offset. */
7163 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7164 fix_new (fragP, old_fr_fix + 2, 2,
7165 fragP->fr_symbol,
7166 fragP->fr_offset, 1,
7167 reloc_type);
fddf5b5b
AM		 7168 break;
7169 }
7170 /* Fall through. */
7171
7172 case COND_JUMP:
412167cb
AM		 7173 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7174 {
3e02c1cc
AM		 7175 fixS *fixP;
7176
412167cb 7177 fragP->fr_fix += 1;
3e02c1cc
AM		 7178 fixP = fix_new (fragP, old_fr_fix, 1,
7179 fragP->fr_symbol,
7180 fragP->fr_offset, 1,
7181 BFD_RELOC_8_PCREL);
7182 fixP->fx_signed = 1;
412167cb
AM		 7183 break;
7184 }
93c2a809 7185
24eab124 7186 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7187 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7188 opcode[1] = opcode[0] + 0x10;
f6af82bd 7189 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7190 /* We've added an opcode byte. */
7191 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7192 fix_new (fragP, old_fr_fix + 1, size,
7193 fragP->fr_symbol,
7194 fragP->fr_offset, 1,
7195 reloc_type);
252b5132 7196 break;
fddf5b5b
AM		 7197
7198 default:
7199 BAD_CASE (fragP->fr_subtype);
7200 break;
252b5132
RH		 7201 }
7202 frag_wane (fragP);
ee7fcc42 7203 return fragP->fr_fix - old_fr_fix;
252b5132 7204 }
93c2a809 7205
93c2a809
AM		 7206 /* Guess size depending on current relax state. Initially the relax
7207 state will correspond to a short jump and we return 1, because
7208 the variable part of the frag (the branch offset) is one byte
7209 long. However, we can relax a section more than once and in that
7210 case we must either set fr_subtype back to the unrelaxed state,
7211 or return the value for the appropriate branch. */
7212 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7213}
7214
47926f60
KH		 7215/* Called after relax() is finished.
7216
7217 In: Address of frag.
7218 fr_type == rs_machine_dependent.
7219 fr_subtype is what the address relaxed to.
7220
7221 Out: Any fixSs and constants are set up.
7222 Caller will turn frag into a ".space 0". */
7223
252b5132
RH		 7224void
7225md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7226 bfd *abfd ATTRIBUTE_UNUSED;
7227 segT sec ATTRIBUTE_UNUSED;
29b0f896 7228 fragS *fragP;
252b5132 7229{
29b0f896 7230 unsigned char *opcode;
252b5132 7231 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7232 offsetT target_address;
7233 offsetT opcode_address;
252b5132 7234 unsigned int extension = 0;
847f7ad4 7235 offsetT displacement_from_opcode_start;
252b5132
RH		 7236
7237 opcode = (unsigned char *) fragP->fr_opcode;
7238
47926f60 7239 /* Address we want to reach in file space. */
252b5132 7240 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7241
47926f60 7242 /* Address opcode resides at in file space. */
252b5132
RH		 7243 opcode_address = fragP->fr_address + fragP->fr_fix;
7244
47926f60 7245 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7246 displacement_from_opcode_start = target_address - opcode_address;
7247
fddf5b5b 7248 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7249 {
47926f60
KH		 7250 /* Don't have to change opcode. */
7251 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7252 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7253 }
7254 else
7255 {
7256 if (no_cond_jump_promotion
7257 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7258 as_warn_where (fragP->fr_file, fragP->fr_line,
7259 _("long jump required"));
252b5132 7260
fddf5b5b
AM		 7261 switch (fragP->fr_subtype)
7262 {
7263 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7264 extension = 4; /* 1 opcode + 4 displacement */
7265 opcode[0] = 0xe9;
7266 where_to_put_displacement = &opcode[1];
7267 break;
252b5132 7268
fddf5b5b
AM		 7269 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7270 extension = 2; /* 1 opcode + 2 displacement */
7271 opcode[0] = 0xe9;
7272 where_to_put_displacement = &opcode[1];
7273 break;
252b5132 7274
fddf5b5b
AM		 7275 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7276 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7277 extension = 5; /* 2 opcode + 4 displacement */
7278 opcode[1] = opcode[0] + 0x10;
7279 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7280 where_to_put_displacement = &opcode[2];
7281 break;
252b5132 7282
fddf5b5b
AM		 7283 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7284 extension = 3; /* 2 opcode + 2 displacement */
7285 opcode[1] = opcode[0] + 0x10;
7286 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7287 where_to_put_displacement = &opcode[2];
7288 break;
252b5132 7289
fddf5b5b
AM		 7290 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7291 extension = 4;
7292 opcode[0] ^= 1;
7293 opcode[1] = 3;
7294 opcode[2] = 0xe9;
7295 where_to_put_displacement = &opcode[3];
7296 break;
7297
7298 default:
7299 BAD_CASE (fragP->fr_subtype);
7300 break;
7301 }
252b5132 7302 }
fddf5b5b 7303
7b81dfbb
AJ		 7304 /* If size if less then four we are sure that the operand fits,
7305 but if it's 4, then it could be that the displacement is larger
7306 then -/+ 2GB. */
7307 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7308 && object_64bit
7309 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7310 + ((addressT) 1 << 31))
7311 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7312 {
7313 as_bad_where (fragP->fr_file, fragP->fr_line,
7314 _("jump target out of range"));
7315 /* Make us emit 0. */
7316 displacement_from_opcode_start = extension;
7317 }
47926f60 7318 /* Now put displacement after opcode. */
252b5132
RH		 7319 md_number_to_chars ((char *) where_to_put_displacement,
7320 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7321 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7322 fragP->fr_fix += extension;
7323}
7324\f
252b5132
RH		 7325/* Apply a fixup (fixS) to segment data, once it has been determined
7326 by our caller that we have all the info we need to fix it up.
7327
7328 On the 386, immediates, displacements, and data pointers are all in
7329 the same (little-endian) format, so we don't need to care about which
7330 we are handling. */
7331
94f592af 7332void
55cf6793 7333md_apply_fix (fixP, valP, seg)
47926f60
KH		 7334 /* The fix we're to put in. */
7335 fixS *fixP;
47926f60 7336 /* Pointer to the value of the bits. */
c6682705 7337 valueT *valP;
47926f60
KH		 7338 /* Segment fix is from. */
7339 segT seg ATTRIBUTE_UNUSED;
252b5132 7340{
94f592af 7341 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7342 valueT value = *valP;
252b5132 7343
f86103b7 7344#if !defined (TE_Mach)
93382f6d
AM		 7345 if (fixP->fx_pcrel)
7346 {
7347 switch (fixP->fx_r_type)
7348 {
5865bb77
ILT		 7349 default:
7350 break;
7351
d6ab8113
JB		 7352 case BFD_RELOC_64:
7353 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7354 break;
93382f6d 7355 case BFD_RELOC_32:
ae8887b5 7356 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7357 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7358 break;
7359 case BFD_RELOC_16:
7360 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7361 break;
7362 case BFD_RELOC_8:
7363 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7364 break;
7365 }
7366 }
252b5132 7367
a161fe53 7368 if (fixP->fx_addsy != NULL
31312f95 7369 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7370 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7371 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7372 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7373 && !use_rela_relocations)
252b5132 7374 {
31312f95
AM		 7375 /* This is a hack. There should be a better way to handle this.
7376 This covers for the fact that bfd_install_relocation will
7377 subtract the current location (for partial_inplace, PC relative
7378 relocations); see more below. */
252b5132 7379#ifndef OBJ_AOUT
718ddfc0 7380 if (IS_ELF
252b5132
RH		 7381#ifdef TE_PE
7382 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7383#endif
7384 )
7385 value += fixP->fx_where + fixP->fx_frag->fr_address;
7386#endif
7387#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7388 if (IS_ELF)
252b5132 7389 {
6539b54b 7390 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7391
6539b54b 7392 if ((sym_seg == seg
2f66722d 7393 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7394 && sym_seg != absolute_section))
af65af87 7395 && !generic_force_reloc (fixP))
2f66722d
AM		 7396 {
7397 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7398 bfd_install_relocation subtracts them out again. I think
7399 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7400 it. FIXME. */
7401 value += fixP->fx_where + fixP->fx_frag->fr_address;
7402 }
252b5132
RH		 7403 }
7404#endif
7405#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7406 /* For some reason, the PE format does not store a
7407 section address offset for a PC relative symbol. */
7408 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7409 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7410 value += md_pcrel_from (fixP);
7411#endif
7412 }
fbeb56a4
DK		 7413#if defined (OBJ_COFF) && defined (TE_PE)
7414 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7415 {
7416 value -= S_GET_VALUE (fixP->fx_addsy);
7417 }
7418#endif
252b5132
RH		 7419
7420 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7421 and we must not disappoint it. */
252b5132 7422#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7423 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7424 switch (fixP->fx_r_type)
7425 {
7426 case BFD_RELOC_386_PLT32:
3e73aa7c 7427 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7428 /* Make the jump instruction point to the address of the operand. At
7429 runtime we merely add the offset to the actual PLT entry. */
7430 value = -4;
7431 break;
31312f95 7432
13ae64f3
JJ		 7433 case BFD_RELOC_386_TLS_GD:
7434 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7435 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7436 case BFD_RELOC_386_TLS_IE:
7437 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7438 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7439 case BFD_RELOC_X86_64_TLSGD:
7440 case BFD_RELOC_X86_64_TLSLD:
7441 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7442 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7443 value = 0; /* Fully resolved at runtime. No addend. */
7444 /* Fallthrough */
7445 case BFD_RELOC_386_TLS_LE:
7446 case BFD_RELOC_386_TLS_LDO_32:
7447 case BFD_RELOC_386_TLS_LE_32:
7448 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7449 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7450 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7451 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7452 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7453 break;
7454
67a4f2b7
AO		 7455 case BFD_RELOC_386_TLS_DESC_CALL:
7456 case BFD_RELOC_X86_64_TLSDESC_CALL:
7457 value = 0; /* Fully resolved at runtime. No addend. */
7458 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7459 fixP->fx_done = 0;
7460 return;
7461
00f7efb6
JJ		 7462 case BFD_RELOC_386_GOT32:
7463 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7464 value = 0; /* Fully resolved at runtime. No addend. */
7465 break;
47926f60
KH		 7466
7467 case BFD_RELOC_VTABLE_INHERIT:
7468 case BFD_RELOC_VTABLE_ENTRY:
7469 fixP->fx_done = 0;
94f592af 7470 return;
47926f60
KH		 7471
7472 default:
7473 break;
7474 }
7475#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7476 *valP = value;
f86103b7 7477#endif /* !defined (TE_Mach) */
3e73aa7c 7478
3e73aa7c 7479 /* Are we finished with this relocation now? */
c6682705 7480 if (fixP->fx_addsy == NULL)
3e73aa7c 7481 fixP->fx_done = 1;
fbeb56a4
DK		 7482#if defined (OBJ_COFF) && defined (TE_PE)
7483 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7484 {
7485 fixP->fx_done = 0;
7486 /* Remember value for tc_gen_reloc. */
7487 fixP->fx_addnumber = value;
7488 /* Clear out the frag for now. */
7489 value = 0;
7490 }
7491#endif
3e73aa7c
JH		 7492 else if (use_rela_relocations)
7493 {
7494 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7495 /* Remember value for tc_gen_reloc. */
7496 fixP->fx_addnumber = value;
3e73aa7c
JH		 7497 value = 0;
7498 }
f86103b7 7499
94f592af 7500 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7501}
252b5132 7502\f
252b5132 7503char *
499ac353 7504md_atof (int type, char *litP, int *sizeP)
252b5132 7505{
499ac353
NC		 7506 /* This outputs the LITTLENUMs in REVERSE order;
7507 in accord with the bigendian 386. */
7508 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7509}
7510\f
2d545b82 7511static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7512
252b5132 7513static char *
e3bb37b5 7514output_invalid (int c)
252b5132 7515{
3882b010 7516 if (ISPRINT (c))
f9f21a03
L		 7517 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7518 "'%c'", c);
252b5132 7519 else
f9f21a03 7520 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7521 "(0x%x)", (unsigned char) c);
252b5132
RH		 7522 return output_invalid_buf;
7523}
7524
af6bdddf 7525/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7526
7527static const reg_entry *
4d1bb795 7528parse_real_register (char *reg_string, char **end_op)
252b5132 7529{
af6bdddf
AM		 7530 char *s = reg_string;
7531 char *p;
252b5132
RH		 7532 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7533 const reg_entry *r;
7534
7535 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7536 if (*s == REGISTER_PREFIX)
7537 ++s;
7538
7539 if (is_space_char (*s))
7540 ++s;
7541
7542 p = reg_name_given;
af6bdddf 7543 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7544 {
7545 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7546 return (const reg_entry *) NULL;
7547 s++;
252b5132
RH		 7548 }
7549
6588847e
DN		 7550 /* For naked regs, make sure that we are not dealing with an identifier.
7551 This prevents confusing an identifier like `eax_var' with register
7552 `eax'. */
7553 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7554 return (const reg_entry *) NULL;
7555
af6bdddf 7556 *end_op = s;
252b5132
RH		 7557
7558 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7559
5f47d35b 7560 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7561 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7562 {
5f47d35b
AM		 7563 if (is_space_char (*s))
7564 ++s;
7565 if (*s == '(')
7566 {
af6bdddf 7567 ++s;
5f47d35b
AM		 7568 if (is_space_char (*s))
7569 ++s;
7570 if (*s >= '0' && *s <= '7')
7571 {
db557034 7572 int fpr = *s - '0';
af6bdddf 7573 ++s;
5f47d35b
AM		 7574 if (is_space_char (*s))
7575 ++s;
7576 if (*s == ')')
7577 {
7578 *end_op = s + 1;
1e9cc1c2 7579 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 7580 know (r);
7581 return r + fpr;
5f47d35b 7582 }
5f47d35b 7583 }
47926f60 7584 /* We have "%st(" then garbage. */
5f47d35b
AM		 7585 return (const reg_entry *) NULL;
7586 }
7587 }
7588
a60de03c
JB		 7589 if (r == NULL || allow_pseudo_reg)
7590 return r;
7591
0dfbf9d7 7592 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7593 return (const reg_entry *) NULL;
7594
192dc9c6
JB		 7595 if ((r->reg_type.bitfield.reg32
7596 || r->reg_type.bitfield.sreg3
7597 || r->reg_type.bitfield.control
7598 || r->reg_type.bitfield.debug
7599 || r->reg_type.bitfield.test)
7600 && !cpu_arch_flags.bitfield.cpui386)
7601 return (const reg_entry *) NULL;
7602
309d3373
JB		 7603 if (r->reg_type.bitfield.floatreg
7604 && !cpu_arch_flags.bitfield.cpu8087
7605 && !cpu_arch_flags.bitfield.cpu287
7606 && !cpu_arch_flags.bitfield.cpu387)
7607 return (const reg_entry *) NULL;
7608
192dc9c6
JB		 7609 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7610 return (const reg_entry *) NULL;
7611
7612 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7613 return (const reg_entry *) NULL;
7614
40f12533
L		 7615 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7616 return (const reg_entry *) NULL;
7617
db51cc60 7618 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7619 if (!allow_index_reg
db51cc60
L		 7620 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7621 return (const reg_entry *) NULL;
7622
a60de03c
JB		 7623 if (((r->reg_flags & (RegRex64 | RegRex))
7624 || r->reg_type.bitfield.reg64)
40fb9820 7625 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7626 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7627 && flag_code != CODE_64BIT)
20f0a1fc 7628 return (const reg_entry *) NULL;
1ae00879 7629
b7240065
JB		 7630 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7631 return (const reg_entry *) NULL;
7632
252b5132
RH		 7633 return r;
7634}
4d1bb795
JB		 7635
7636/* REG_STRING starts *before* REGISTER_PREFIX. */
7637
7638static const reg_entry *
7639parse_register (char *reg_string, char **end_op)
7640{
7641 const reg_entry *r;
7642
7643 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7644 r = parse_real_register (reg_string, end_op);
7645 else
7646 r = NULL;
7647 if (!r)
7648 {
7649 char *save = input_line_pointer;
7650 char c;
7651 symbolS *symbolP;
7652
7653 input_line_pointer = reg_string;
7654 c = get_symbol_end ();
7655 symbolP = symbol_find (reg_string);
7656 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7657 {
7658 const expressionS *e = symbol_get_value_expression (symbolP);
7659
7660 know (e->X_op == O_register);
4eed87de 7661 know (e->X_add_number >= 0
c3fe08fa 7662 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7663 r = i386_regtab + e->X_add_number;
7664 *end_op = input_line_pointer;
7665 }
7666 *input_line_pointer = c;
7667 input_line_pointer = save;
7668 }
7669 return r;
7670}
7671
7672int
7673i386_parse_name (char *name, expressionS *e, char *nextcharP)
7674{
7675 const reg_entry *r;
7676 char *end = input_line_pointer;
7677
7678 *end = *nextcharP;
7679 r = parse_register (name, &input_line_pointer);
7680 if (r && end <= input_line_pointer)
7681 {
7682 *nextcharP = *input_line_pointer;
7683 *input_line_pointer = 0;
7684 e->X_op = O_register;
7685 e->X_add_number = r - i386_regtab;
7686 return 1;
7687 }
7688 input_line_pointer = end;
7689 *end = 0;
ee86248c 7690 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 7691}
7692
7693void
7694md_operand (expressionS *e)
7695{
ee86248c
JB		 7696 char *end;
7697 const reg_entry *r;
4d1bb795 7698
ee86248c
JB		 7699 switch (*input_line_pointer)
7700 {
7701 case REGISTER_PREFIX:
7702 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 7703 if (r)
7704 {
7705 e->X_op = O_register;
7706 e->X_add_number = r - i386_regtab;
7707 input_line_pointer = end;
7708 }
ee86248c
JB		 7709 break;
7710
7711 case '[':
9c2799c2 7712 gas_assert (intel_syntax);
ee86248c
JB		 7713 end = input_line_pointer++;
7714 expression (e);
7715 if (*input_line_pointer == ']')
7716 {
7717 ++input_line_pointer;
7718 e->X_op_symbol = make_expr_symbol (e);
7719 e->X_add_symbol = NULL;
7720 e->X_add_number = 0;
7721 e->X_op = O_index;
7722 }
7723 else
7724 {
7725 e->X_op = O_absent;
7726 input_line_pointer = end;
7727 }
7728 break;
4d1bb795
JB		 7729 }
7730}
7731
252b5132 7732\f
4cc782b5 7733#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7734const char *md_shortopts = "kVQ:sqn";
252b5132 7735#else
12b55ccc 7736const char *md_shortopts = "qn";
252b5132 7737#endif
6e0b89ee 7738
3e73aa7c 7739#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7740#define OPTION_64 (OPTION_MD_BASE + 1)
7741#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7742#define OPTION_MARCH (OPTION_MD_BASE + 3)
7743#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7744#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7745#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7746#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7747#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7748#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 7749#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 7750#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
b3b91714 7751
99ad8390
NC		 7752struct option md_longopts[] =
7753{
3e73aa7c 7754 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 7755#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7756 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 7757 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7758#endif
b3b91714 7759 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7760 {"march", required_argument, NULL, OPTION_MARCH},
7761 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7762 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7763 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7764 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7765 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7766 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 7767 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 7768 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
252b5132
RH		 7769 {NULL, no_argument, NULL, 0}
7770};
7771size_t md_longopts_size = sizeof (md_longopts);
7772
7773int
9103f4f4 7774md_parse_option (int c, char *arg)
252b5132 7775{
9103f4f4 7776 unsigned int i;
6305a203 7777 char *arch, *next;
9103f4f4 7778
252b5132
RH		 7779 switch (c)
7780 {
12b55ccc
L		 7781 case 'n':
7782 optimize_align_code = 0;
7783 break;
7784
a38cf1db
AM		 7785 case 'q':
7786 quiet_warnings = 1;
252b5132
RH		 7787 break;
7788
7789#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7790 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7791 should be emitted or not. FIXME: Not implemented. */
7792 case 'Q':
252b5132
RH		 7793 break;
7794
7795 /* -V: SVR4 argument to print version ID. */
7796 case 'V':
7797 print_version_id ();
7798 break;
7799
a38cf1db
AM		 7800 /* -k: Ignore for FreeBSD compatibility. */
7801 case 'k':
252b5132 7802 break;
4cc782b5
ILT		 7803
7804 case 's':
7805 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7806 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7807 break;
99ad8390 7808#endif
321098a5
L		 7809#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7810 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 7811 case OPTION_64:
7812 {
7813 const char **list, **l;
7814
3e73aa7c
JH		 7815 list = bfd_target_list ();
7816 for (l = list; *l != NULL; l++)
8620418b 7817 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7818 || strcmp (*l, "coff-x86-64") == 0
7819 || strcmp (*l, "pe-x86-64") == 0
7820 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7821 {
7822 default_arch = "x86_64";
7823 break;
7824 }
3e73aa7c 7825 if (*l == NULL)
6e0b89ee 7826 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7827 free (list);
7828 }
7829 break;
7830#endif
252b5132 7831
6e0b89ee
AM		 7832 case OPTION_32:
7833 default_arch = "i386";
7834 break;
7835
b3b91714
AM		 7836 case OPTION_DIVIDE:
7837#ifdef SVR4_COMMENT_CHARS
7838 {
7839 char *n, *t;
7840 const char *s;
7841
7842 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7843 t = n;
7844 for (s = i386_comment_chars; *s != '\0'; s++)
7845 if (*s != '/')
7846 *t++ = *s;
7847 *t = '\0';
7848 i386_comment_chars = n;
7849 }
7850#endif
7851 break;
7852
9103f4f4 7853 case OPTION_MARCH:
6305a203
L		 7854 arch = xstrdup (arg);
7855 do
9103f4f4 7856 {
6305a203
L		 7857 if (*arch == '.')
7858 as_fatal (_("Invalid -march= option: `%s'"), arg);
7859 next = strchr (arch, '+');
7860 if (next)
7861 *next++ = '\0';
7862 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 7863 {
6305a203 7864 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 7865 {
6305a203
L		 7866 /* Processor. */
7867 cpu_arch_name = cpu_arch[i].name;
7868 cpu_sub_arch_name = NULL;
7869 cpu_arch_flags = cpu_arch[i].flags;
7870 cpu_arch_isa = cpu_arch[i].type;
7871 cpu_arch_isa_flags = cpu_arch[i].flags;
7872 if (!cpu_arch_tune_set)
7873 {
7874 cpu_arch_tune = cpu_arch_isa;
7875 cpu_arch_tune_flags = cpu_arch_isa_flags;
7876 }
7877 break;
7878 }
7879 else if (*cpu_arch [i].name == '.'
7880 && strcmp (arch, cpu_arch [i].name + 1) == 0)
7881 {
7882 /* ISA entension. */
7883 i386_cpu_flags flags;
309d3373
JB		 7884
7885 if (strncmp (arch, "no", 2))
7886 flags = cpu_flags_or (cpu_arch_flags,
7887 cpu_arch[i].flags);
7888 else
7889 flags = cpu_flags_and_not (cpu_arch_flags,
7890 cpu_arch[i].flags);
0dfbf9d7 7891 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 7892 {
7893 if (cpu_sub_arch_name)
7894 {
7895 char *name = cpu_sub_arch_name;
7896 cpu_sub_arch_name = concat (name,
7897 cpu_arch[i].name,
1bf57e9f 7898 (const char *) NULL);
6305a203
L		 7899 free (name);
7900 }
7901 else
7902 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
7903 cpu_arch_flags = flags;
7904 }
7905 break;
ccc9c027 7906 }
9103f4f4 7907 }
6305a203
L		 7908
7909 if (i >= ARRAY_SIZE (cpu_arch))
7910 as_fatal (_("Invalid -march= option: `%s'"), arg);
7911
7912 arch = next;
9103f4f4 7913 }
6305a203 7914 while (next != NULL );
9103f4f4
L		 7915 break;
7916
7917 case OPTION_MTUNE:
7918 if (*arg == '.')
7919 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7920 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7921 {
7922 if (strcmp (arg, cpu_arch [i].name) == 0)
7923 {
ccc9c027 7924 cpu_arch_tune_set = 1;
9103f4f4
L		 7925 cpu_arch_tune = cpu_arch [i].type;
7926 cpu_arch_tune_flags = cpu_arch[i].flags;
7927 break;
7928 }
7929 }
7930 if (i >= ARRAY_SIZE (cpu_arch))
7931 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7932 break;
7933
1efbbeb4
L		 7934 case OPTION_MMNEMONIC:
7935 if (strcasecmp (arg, "att") == 0)
7936 intel_mnemonic = 0;
7937 else if (strcasecmp (arg, "intel") == 0)
7938 intel_mnemonic = 1;
7939 else
7940 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7941 break;
7942
7943 case OPTION_MSYNTAX:
7944 if (strcasecmp (arg, "att") == 0)
7945 intel_syntax = 0;
7946 else if (strcasecmp (arg, "intel") == 0)
7947 intel_syntax = 1;
7948 else
7949 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7950 break;
7951
7952 case OPTION_MINDEX_REG:
7953 allow_index_reg = 1;
7954 break;
7955
7956 case OPTION_MNAKED_REG:
7957 allow_naked_reg = 1;
7958 break;
7959
7960 case OPTION_MOLD_GCC:
7961 old_gcc = 1;
1efbbeb4
L		 7962 break;
7963
c0f3af97
L		 7964 case OPTION_MSSE2AVX:
7965 sse2avx = 1;
7966 break;
7967
daf50ae7
L		 7968 case OPTION_MSSE_CHECK:
7969 if (strcasecmp (arg, "error") == 0)
7970 sse_check = sse_check_error;
7971 else if (strcasecmp (arg, "warning") == 0)
7972 sse_check = sse_check_warning;
7973 else if (strcasecmp (arg, "none") == 0)
7974 sse_check = sse_check_none;
7975 else
7976 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
7977 break;
7978
252b5132
RH		 7979 default:
7980 return 0;
7981 }
7982 return 1;
7983}
7984
7985void
7986md_show_usage (stream)
7987 FILE *stream;
7988{
4cc782b5
ILT		 7989#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7990 fprintf (stream, _("\
a38cf1db
AM		 7991 -Q ignored\n\
7992 -V print assembler version number\n\
b3b91714
AM		 7993 -k ignored\n"));
7994#endif
7995 fprintf (stream, _("\
12b55ccc 7996 -n Do not optimize code alignment\n\
b3b91714
AM		 7997 -q quieten some warnings\n"));
7998#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7999 fprintf (stream, _("\
a38cf1db 8000 -s ignored\n"));
b3b91714 8001#endif
321098a5
L		 8002#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8003 || defined (TE_PE) || defined (TE_PEP))
751d281c
L		 8004 fprintf (stream, _("\
8005 --32/--64 generate 32bit/64bit code\n"));
8006#endif
b3b91714
AM		 8007#ifdef SVR4_COMMENT_CHARS
8008 fprintf (stream, _("\
8009 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8010#else
8011 fprintf (stream, _("\
b3b91714 8012 --divide ignored\n"));
4cc782b5 8013#endif
9103f4f4 8014 fprintf (stream, _("\
6305a203
L		 8015 -march=CPU[,+EXTENSION...]\n\
8016 generate code for CPU and EXTENSION, CPU is one of:\n\
2cb4f3d5
L		 8017 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8018 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8a9036a4
L		 8019 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8020 amdfam10, generic32, generic64\n\
599121aa 8021 EXTENSION is combination of:\n\
309d3373
JB		 8022 8087, 287, 387, no87, mmx, nommx, sse, sse2, sse3,\n\
8023 ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\
8024 vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
bd5295b2 8025 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
922d8de8 8026 svme, abm, padlock, fma4\n"));
6305a203 8027 fprintf (stream, _("\
2cb4f3d5
L		 8028 -mtune=CPU optimize for CPU, CPU is one of:\n\
8029 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8030 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8a9036a4
L		 8031 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8032 amdfam10, generic32, generic64\n"));
ba104c83 8033 fprintf (stream, _("\
c0f3af97
L		 8034 -msse2avx encode SSE instructions with VEX prefix\n"));
8035 fprintf (stream, _("\
daf50ae7
L		 8036 -msse-check=[none|error|warning]\n\
8037 check SSE instructions\n"));
8038 fprintf (stream, _("\
ba104c83
L		 8039 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8040 fprintf (stream, _("\
8041 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8042 fprintf (stream, _("\
8043 -mindex-reg support pseudo index registers\n"));
8044 fprintf (stream, _("\
8045 -mnaked-reg don't require `%%' prefix for registers\n"));
8046 fprintf (stream, _("\
8047 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8048}
8049
3e73aa7c 8050#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8051 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8052 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8053
8054/* Pick the target format to use. */
8055
47926f60 8056const char *
e3bb37b5 8057i386_target_format (void)
252b5132 8058{
3e73aa7c 8059 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 8060 {
8061 set_code_flag (CODE_64BIT);
0dfbf9d7 8062 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8063 {
8064 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8065 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8066 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8067 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8068 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8069 cpu_arch_isa_flags.bitfield.cpui686 = 1;
bd5295b2 8070 cpu_arch_isa_flags.bitfield.cpuclflush = 1;
40fb9820 8071 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 8072 cpu_arch_isa_flags.bitfield.cpusse = 1;
8073 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
711eedef 8074 cpu_arch_isa_flags.bitfield.cpulm = 1;
40fb9820 8075 }
0dfbf9d7 8076 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8077 {
8078 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8079 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8080 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8081 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8082 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8083 cpu_arch_tune_flags.bitfield.cpui686 = 1;
bd5295b2 8084 cpu_arch_tune_flags.bitfield.cpuclflush = 1;
40fb9820 8085 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 8086 cpu_arch_tune_flags.bitfield.cpusse = 1;
8087 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8088 }
9103f4f4 8089 }
3e73aa7c 8090 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 8091 {
8092 set_code_flag (CODE_32BIT);
0dfbf9d7 8093 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8094 {
8095 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8096 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8097 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8098 }
0dfbf9d7 8099 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8100 {
8101 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8102 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8103 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8104 }
9103f4f4 8105 }
3e73aa7c
JH		 8106 else
8107 as_fatal (_("Unknown architecture"));
252b5132
RH		 8108 switch (OUTPUT_FLAVOR)
8109 {
9384f2ff 8110#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8111 case bfd_target_aout_flavour:
47926f60 8112 return AOUT_TARGET_FORMAT;
4c63da97 8113#endif
9384f2ff
AM		 8114#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8115# if defined (TE_PE) || defined (TE_PEP)
8116 case bfd_target_coff_flavour:
8117 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8118# elif defined (TE_GO32)
0561d57c
JK		 8119 case bfd_target_coff_flavour:
8120 return "coff-go32";
9384f2ff 8121# else
252b5132
RH		 8122 case bfd_target_coff_flavour:
8123 return "coff-i386";
9384f2ff 8124# endif
4c63da97 8125#endif
3e73aa7c 8126#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8127 case bfd_target_elf_flavour:
3e73aa7c 8128 {
e5cb08ac 8129 if (flag_code == CODE_64BIT)
4fa24527
JB		 8130 {
8131 object_64bit = 1;
8132 use_rela_relocations = 1;
8133 }
3632d14b 8134 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 8135 {
8136 if (flag_code != CODE_64BIT)
8137 as_fatal (_("Intel L1OM is 64bit only"));
8138 return ELF_TARGET_L1OM_FORMAT;
8139 }
8140 else
8141 return (flag_code == CODE_64BIT
8142 ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT);
3e73aa7c 8143 }
e57f8c65
TG		 8144#endif
8145#if defined (OBJ_MACH_O)
8146 case bfd_target_mach_o_flavour:
8147 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 8148#endif
252b5132
RH		 8149 default:
8150 abort ();
8151 return NULL;
8152 }
8153}
8154
47926f60 8155#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8156
8157#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8158void
8159i386_elf_emit_arch_note (void)
a847613f 8160{
718ddfc0 8161 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8162 {
8163 char *p;
8164 asection *seg = now_seg;
8165 subsegT subseg = now_subseg;
8166 Elf_Internal_Note i_note;
8167 Elf_External_Note e_note;
8168 asection *note_secp;
8169 int len;
8170
8171 /* Create the .note section. */
8172 note_secp = subseg_new (".note", 0);
8173 bfd_set_section_flags (stdoutput,
8174 note_secp,
8175 SEC_HAS_CONTENTS | SEC_READONLY);
8176
8177 /* Process the arch string. */
8178 len = strlen (cpu_arch_name);
8179
8180 i_note.namesz = len + 1;
8181 i_note.descsz = 0;
8182 i_note.type = NT_ARCH;
8183 p = frag_more (sizeof (e_note.namesz));
8184 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8185 p = frag_more (sizeof (e_note.descsz));
8186 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8187 p = frag_more (sizeof (e_note.type));
8188 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8189 p = frag_more (len + 1);
8190 strcpy (p, cpu_arch_name);
8191
8192 frag_align (2, 0, 0);
8193
8194 subseg_set (seg, subseg);
8195 }
8196}
8197#endif
252b5132 8198\f
252b5132
RH		 8199symbolS *
8200md_undefined_symbol (name)
8201 char *name;
8202{
18dc2407
ILT		 8203 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8204 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8205 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8206 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8207 {
8208 if (!GOT_symbol)
8209 {
8210 if (symbol_find (name))
8211 as_bad (_("GOT already in symbol table"));
8212 GOT_symbol = symbol_new (name, undefined_section,
8213 (valueT) 0, &zero_address_frag);
8214 };
8215 return GOT_symbol;
8216 }
252b5132
RH		 8217 return 0;
8218}
8219
8220/* Round up a section size to the appropriate boundary. */
47926f60 8221
252b5132
RH		 8222valueT
8223md_section_align (segment, size)
ab9da554 8224 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8225 valueT size;
8226{
4c63da97
AM		 8227#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8228 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8229 {
8230 /* For a.out, force the section size to be aligned. If we don't do
8231 this, BFD will align it for us, but it will not write out the
8232 final bytes of the section. This may be a bug in BFD, but it is
8233 easier to fix it here since that is how the other a.out targets
8234 work. */
8235 int align;
8236
8237 align = bfd_get_section_alignment (stdoutput, segment);
8238 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8239 }
252b5132
RH		 8240#endif
8241
8242 return size;
8243}
8244
8245/* On the i386, PC-relative offsets are relative to the start of the
8246 next instruction. That is, the address of the offset, plus its
8247 size, since the offset is always the last part of the insn. */
8248
8249long
e3bb37b5 8250md_pcrel_from (fixS *fixP)
252b5132
RH		 8251{
8252 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8253}
8254
8255#ifndef I386COFF
8256
8257static void
e3bb37b5 8258s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8259{
29b0f896 8260 int temp;
252b5132 8261
8a75718c
JB		 8262#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8263 if (IS_ELF)
8264 obj_elf_section_change_hook ();
8265#endif
252b5132
RH		 8266 temp = get_absolute_expression ();
8267 subseg_set (bss_section, (subsegT) temp);
8268 demand_empty_rest_of_line ();
8269}
8270
8271#endif
8272
252b5132 8273void
e3bb37b5 8274i386_validate_fix (fixS *fixp)
252b5132
RH		 8275{
8276 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8277 {
23df1078
JH		 8278 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8279 {
4fa24527 8280 if (!object_64bit)
23df1078
JH		 8281 abort ();
8282 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8283 }
8284 else
8285 {
4fa24527 8286 if (!object_64bit)
d6ab8113
JB		 8287 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8288 else
8289 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8290 }
252b5132
RH		 8291 fixp->fx_subsy = 0;
8292 }
8293}
8294
252b5132
RH		 8295arelent *
8296tc_gen_reloc (section, fixp)
ab9da554 8297 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8298 fixS *fixp;
8299{
8300 arelent *rel;
8301 bfd_reloc_code_real_type code;
8302
8303 switch (fixp->fx_r_type)
8304 {
3e73aa7c
JH		 8305 case BFD_RELOC_X86_64_PLT32:
8306 case BFD_RELOC_X86_64_GOT32:
8307 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8308 case BFD_RELOC_386_PLT32:
8309 case BFD_RELOC_386_GOT32:
8310 case BFD_RELOC_386_GOTOFF:
8311 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8312 case BFD_RELOC_386_TLS_GD:
8313 case BFD_RELOC_386_TLS_LDM:
8314 case BFD_RELOC_386_TLS_LDO_32:
8315 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8316 case BFD_RELOC_386_TLS_IE:
8317 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8318 case BFD_RELOC_386_TLS_LE_32:
8319 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8320 case BFD_RELOC_386_TLS_GOTDESC:
8321 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8322 case BFD_RELOC_X86_64_TLSGD:
8323 case BFD_RELOC_X86_64_TLSLD:
8324 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8325 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8326 case BFD_RELOC_X86_64_GOTTPOFF:
8327 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8328 case BFD_RELOC_X86_64_TPOFF64:
8329 case BFD_RELOC_X86_64_GOTOFF64:
8330 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8331 case BFD_RELOC_X86_64_GOT64:
8332 case BFD_RELOC_X86_64_GOTPCREL64:
8333 case BFD_RELOC_X86_64_GOTPC64:
8334 case BFD_RELOC_X86_64_GOTPLT64:
8335 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8336 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8337 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8338 case BFD_RELOC_RVA:
8339 case BFD_RELOC_VTABLE_ENTRY:
8340 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8341#ifdef TE_PE
8342 case BFD_RELOC_32_SECREL:
8343#endif
252b5132
RH		 8344 code = fixp->fx_r_type;
8345 break;
dbbaec26
L		 8346 case BFD_RELOC_X86_64_32S:
8347 if (!fixp->fx_pcrel)
8348 {
8349 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8350 code = fixp->fx_r_type;
8351 break;
8352 }
252b5132 8353 default:
93382f6d 8354 if (fixp->fx_pcrel)
252b5132 8355 {
93382f6d
AM		 8356 switch (fixp->fx_size)
8357 {
8358 default:
b091f402
AM		 8359 as_bad_where (fixp->fx_file, fixp->fx_line,
8360 _("can not do %d byte pc-relative relocation"),
8361 fixp->fx_size);
93382f6d
AM		 8362 code = BFD_RELOC_32_PCREL;
8363 break;
8364 case 1: code = BFD_RELOC_8_PCREL; break;
8365 case 2: code = BFD_RELOC_16_PCREL; break;
8366 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8367#ifdef BFD64
8368 case 8: code = BFD_RELOC_64_PCREL; break;
8369#endif
93382f6d
AM		 8370 }
8371 }
8372 else
8373 {
8374 switch (fixp->fx_size)
8375 {
8376 default:
b091f402
AM		 8377 as_bad_where (fixp->fx_file, fixp->fx_line,
8378 _("can not do %d byte relocation"),
8379 fixp->fx_size);
93382f6d
AM		 8380 code = BFD_RELOC_32;
8381 break;
8382 case 1: code = BFD_RELOC_8; break;
8383 case 2: code = BFD_RELOC_16; break;
8384 case 4: code = BFD_RELOC_32; break;
937149dd 8385#ifdef BFD64
3e73aa7c 8386 case 8: code = BFD_RELOC_64; break;
937149dd 8387#endif
93382f6d 8388 }
252b5132
RH		 8389 }
8390 break;
8391 }
252b5132 8392
d182319b
JB		 8393 if ((code == BFD_RELOC_32
8394 || code == BFD_RELOC_32_PCREL
8395 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8396 && GOT_symbol
8397 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8398 {
4fa24527 8399 if (!object_64bit)
d6ab8113
JB		 8400 code = BFD_RELOC_386_GOTPC;
8401 else
8402 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8403 }
7b81dfbb
AJ		 8404 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8405 && GOT_symbol
8406 && fixp->fx_addsy == GOT_symbol)
8407 {
8408 code = BFD_RELOC_X86_64_GOTPC64;
8409 }
252b5132
RH		 8410
8411 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8412 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8413 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8414
8415 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8416
3e73aa7c
JH		 8417 if (!use_rela_relocations)
8418 {
8419 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8420 vtable entry to be used in the relocation's section offset. */
8421 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8422 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8423#if defined (OBJ_COFF) && defined (TE_PE)
8424 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8425 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8426 else
8427#endif
c6682705 8428 rel->addend = 0;
3e73aa7c
JH		 8429 }
8430 /* Use the rela in 64bit mode. */
252b5132 8431 else
3e73aa7c 8432 {
062cd5e7
AS		 8433 if (!fixp->fx_pcrel)
8434 rel->addend = fixp->fx_offset;
8435 else
8436 switch (code)
8437 {
8438 case BFD_RELOC_X86_64_PLT32:
8439 case BFD_RELOC_X86_64_GOT32:
8440 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8441 case BFD_RELOC_X86_64_TLSGD:
8442 case BFD_RELOC_X86_64_TLSLD:
8443 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8444 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8445 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8446 rel->addend = fixp->fx_offset - fixp->fx_size;
8447 break;
8448 default:
8449 rel->addend = (section->vma
8450 - fixp->fx_size
8451 + fixp->fx_addnumber
8452 + md_pcrel_from (fixp));
8453 break;
8454 }
3e73aa7c
JH		 8455 }
8456
252b5132
RH		 8457 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8458 if (rel->howto == NULL)
8459 {
8460 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8461 _("cannot represent relocation type %s"),
252b5132
RH		 8462 bfd_get_reloc_code_name (code));
8463 /* Set howto to a garbage value so that we can keep going. */
8464 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 8465 gas_assert (rel->howto != NULL);
252b5132
RH		 8466 }
8467
8468 return rel;
8469}
8470
ee86248c 8471#include "tc-i386-intel.c"
54cfded0 8472
a60de03c
JB		 8473void
8474tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 8475{
a60de03c
JB		 8476 int saved_naked_reg;
8477 char saved_register_dot;
54cfded0 8478
a60de03c
JB		 8479 saved_naked_reg = allow_naked_reg;
8480 allow_naked_reg = 1;
8481 saved_register_dot = register_chars['.'];
8482 register_chars['.'] = '.';
8483 allow_pseudo_reg = 1;
8484 expression_and_evaluate (exp);
8485 allow_pseudo_reg = 0;
8486 register_chars['.'] = saved_register_dot;
8487 allow_naked_reg = saved_naked_reg;
8488
8489 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 8490 {
a60de03c
JB		 8491 if ((addressT) exp->X_add_number < i386_regtab_size)
8492 {
8493 exp->X_op = O_constant;
8494 exp->X_add_number = i386_regtab[exp->X_add_number]
8495 .dw2_regnum[flag_code >> 1];
8496 }
8497 else
8498 exp->X_op = O_illegal;
54cfded0 8499 }
54cfded0
AM		 8500}
8501
8502void
8503tc_x86_frame_initial_instructions (void)
8504{
a60de03c
JB		 8505 static unsigned int sp_regno[2];
8506
8507 if (!sp_regno[flag_code >> 1])
8508 {
8509 char *saved_input = input_line_pointer;
8510 char sp[][4] = {"esp", "rsp"};
8511 expressionS exp;
a4447b93 8512
a60de03c
JB		 8513 input_line_pointer = sp[flag_code >> 1];
8514 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 8515 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 8516 sp_regno[flag_code >> 1] = exp.X_add_number;
8517 input_line_pointer = saved_input;
8518 }
a4447b93 8519
a60de03c 8520 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 8521 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8522}
d2b2c203
DJ		 8523
8524int
8525i386_elf_section_type (const char *str, size_t len)
8526{
8527 if (flag_code == CODE_64BIT
8528 && len == sizeof ("unwind") - 1
8529 && strncmp (str, "unwind", 6) == 0)
8530 return SHT_X86_64_UNWIND;
8531
8532 return -1;
8533}
bb41ade5 8534
ad5fec3b
EB		 8535#ifdef TE_SOLARIS
8536void
8537i386_solaris_fix_up_eh_frame (segT sec)
8538{
8539 if (flag_code == CODE_64BIT)
8540 elf_section_type (sec) = SHT_X86_64_UNWIND;
8541}
8542#endif
8543
bb41ade5
AM		 8544#ifdef TE_PE
8545void
8546tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8547{
8548 expressionS expr;
8549
8550 expr.X_op = O_secrel;
8551 expr.X_add_symbol = symbol;
8552 expr.X_add_number = 0;
8553 emit_expr (&expr, size);
8554}
8555#endif
3b22753a
L		 8556
8557#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8558/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8559
01e1a5bc 8560bfd_vma
3b22753a
L		 8561x86_64_section_letter (int letter, char **ptr_msg)
8562{
8563 if (flag_code == CODE_64BIT)
8564 {
8565 if (letter == 'l')
8566 return SHF_X86_64_LARGE;
8567
8568 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8569 }
3b22753a 8570 else
64e74474 8571 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8572 return -1;
8573}
8574
01e1a5bc 8575bfd_vma
3b22753a
L		 8576x86_64_section_word (char *str, size_t len)
8577{
8620418b 8578 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8579 return SHF_X86_64_LARGE;
8580
8581 return -1;
8582}
8583
8584static void
8585handle_large_common (int small ATTRIBUTE_UNUSED)
8586{
8587 if (flag_code != CODE_64BIT)
8588 {
8589 s_comm_internal (0, elf_common_parse);
8590 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8591 }
8592 else
8593 {
8594 static segT lbss_section;
8595 asection *saved_com_section_ptr = elf_com_section_ptr;
8596 asection *saved_bss_section = bss_section;
8597
8598 if (lbss_section == NULL)
8599 {
8600 flagword applicable;
8601 segT seg = now_seg;
8602 subsegT subseg = now_subseg;
8603
8604 /* The .lbss section is for local .largecomm symbols. */
8605 lbss_section = subseg_new (".lbss", 0);
8606 applicable = bfd_applicable_section_flags (stdoutput);
8607 bfd_set_section_flags (stdoutput, lbss_section,
8608 applicable & SEC_ALLOC);
8609 seg_info (lbss_section)->bss = 1;
8610
8611 subseg_set (seg, subseg);
8612 }
8613
8614 elf_com_section_ptr = &_bfd_elf_large_com_section;
8615 bss_section = lbss_section;
8616
8617 s_comm_internal (0, elf_common_parse);
8618
8619 elf_com_section_ptr = saved_com_section_ptr;
8620 bss_section = saved_bss_section;
8621 }
8622}
8623#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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