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* infrun.c (handle_inferior_event): Don't call
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
67a4f2b7 3 2000, 2001, 2002, 2003, 2004, 2005, 2006
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
d182319b 83static void signed_cons PARAMS ((int));
29b0f896
AM		 84static char *output_invalid PARAMS ((int c));
85static int i386_operand PARAMS ((char *operand_string));
86static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
87static const reg_entry *parse_register PARAMS ((char *reg_string,
88 char **end_op));
89static char *parse_insn PARAMS ((char *, char *));
90static char *parse_operands PARAMS ((char *, const char *));
91static void swap_operands PARAMS ((void));
050dfa73 92static void swap_imm_operands PARAMS ((void));
29b0f896
AM		 93static void optimize_imm PARAMS ((void));
94static void optimize_disp PARAMS ((void));
95static int match_template PARAMS ((void));
96static int check_string PARAMS ((void));
97static int process_suffix PARAMS ((void));
98static int check_byte_reg PARAMS ((void));
99static int check_long_reg PARAMS ((void));
100static int check_qword_reg PARAMS ((void));
101static int check_word_reg PARAMS ((void));
102static int finalize_imm PARAMS ((void));
103static int process_operands PARAMS ((void));
104static const seg_entry *build_modrm_byte PARAMS ((void));
105static void output_insn PARAMS ((void));
106static void output_branch PARAMS ((void));
107static void output_jump PARAMS ((void));
108static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 109static void output_imm PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
111static void output_disp PARAMS ((fragS *insn_start_frag,
112 offsetT insn_start_off));
29b0f896
AM		 113#ifndef I386COFF
114static void s_bss PARAMS ((int));
252b5132 115#endif
17d4e2a2
L		 116#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
117static void handle_large_common (int small ATTRIBUTE_UNUSED);
118#endif
252b5132 119
a847613f 120static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 121
252b5132 122/* 'md_assemble ()' gathers together information and puts it into a
47926f60 123 i386_insn. */
252b5132 124
520dc8e8
AM		 125union i386_op
126 {
127 expressionS *disps;
128 expressionS *imms;
129 const reg_entry *regs;
130 };
131
252b5132
RH		 132struct _i386_insn
133 {
47926f60 134 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 135 template tm;
136
137 /* SUFFIX holds the instruction mnemonic suffix if given.
138 (e.g. 'l' for 'movl') */
139 char suffix;
140
47926f60 141 /* OPERANDS gives the number of given operands. */
252b5132
RH		 142 unsigned int operands;
143
144 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
145 of given register, displacement, memory operands and immediate
47926f60 146 operands. */
252b5132
RH		 147 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
148
149 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 150 use OP[i] for the corresponding operand. */
252b5132
RH		 151 unsigned int types[MAX_OPERANDS];
152
520dc8e8
AM		 153 /* Displacement expression, immediate expression, or register for each
154 operand. */
155 union i386_op op[MAX_OPERANDS];
252b5132 156
3e73aa7c
JH		 157 /* Flags for operands. */
158 unsigned int flags[MAX_OPERANDS];
159#define Operand_PCrel 1
160
252b5132 161 /* Relocation type for operand */
f86103b7 162 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 163
252b5132
RH		 164 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
165 the base index byte below. */
166 const reg_entry *base_reg;
167 const reg_entry *index_reg;
168 unsigned int log2_scale_factor;
169
170 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 171 explicit segment overrides are given. */
ce8a8b2f 172 const seg_entry *seg[2];
252b5132
RH		 173
174 /* PREFIX holds all the given prefix opcodes (usually null).
175 PREFIXES is the number of prefix opcodes. */
176 unsigned int prefixes;
177 unsigned char prefix[MAX_PREFIXES];
178
179 /* RM and SIB are the modrm byte and the sib byte where the
180 addressing modes of this insn are encoded. */
181
182 modrm_byte rm;
3e73aa7c 183 rex_byte rex;
252b5132
RH		 184 sib_byte sib;
185 };
186
187typedef struct _i386_insn i386_insn;
188
189/* List of chars besides those in app.c:symbol_chars that can start an
190 operand. Used to prevent the scrubber eating vital white-space. */
32137342 191const char extra_symbol_chars[] = "*%-(["
252b5132 192#ifdef LEX_AT
32137342
NC		 193 "@"
194#endif
195#ifdef LEX_QM
196 "?"
252b5132 197#endif
32137342 198 ;
252b5132 199
29b0f896
AM		 200#if (defined (TE_I386AIX) \
201 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 202 && !defined (TE_GNU) \
29b0f896 203 && !defined (TE_LINUX) \
32137342 204 && !defined (TE_NETWARE) \
29b0f896
AM		 205 && !defined (TE_FreeBSD) \
206 && !defined (TE_NetBSD)))
252b5132 207/* This array holds the chars that always start a comment. If the
b3b91714
AM		 208 pre-processor is disabled, these aren't very useful. The option
209 --divide will remove '/' from this list. */
210const char *i386_comment_chars = "#/";
211#define SVR4_COMMENT_CHARS 1
252b5132 212#define PREFIX_SEPARATOR '\\'
252b5132 213
b3b91714
AM		 214#else
215const char *i386_comment_chars = "#";
216#define PREFIX_SEPARATOR '/'
217#endif
218
252b5132
RH		 219/* This array holds the chars that only start a comment at the beginning of
220 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 221 .line and .file directives will appear in the pre-processed output.
222 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 223 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 224 #NO_APP at the beginning of its output.
225 Also note that comments started like this one will always work if
252b5132 226 '/' isn't otherwise defined. */
b3b91714 227const char line_comment_chars[] = "#/";
252b5132 228
63a0b638 229const char line_separator_chars[] = ";";
252b5132 230
ce8a8b2f
AM		 231/* Chars that can be used to separate mant from exp in floating point
232 nums. */
252b5132
RH		 233const char EXP_CHARS[] = "eE";
234
ce8a8b2f
AM		 235/* Chars that mean this number is a floating point constant
236 As in 0f12.456
237 or 0d1.2345e12. */
252b5132
RH		 238const char FLT_CHARS[] = "fFdDxX";
239
ce8a8b2f 240/* Tables for lexical analysis. */
252b5132
RH		 241static char mnemonic_chars[256];
242static char register_chars[256];
243static char operand_chars[256];
244static char identifier_chars[256];
245static char digit_chars[256];
246
ce8a8b2f 247/* Lexical macros. */
252b5132
RH		 248#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
249#define is_operand_char(x) (operand_chars[(unsigned char) x])
250#define is_register_char(x) (register_chars[(unsigned char) x])
251#define is_space_char(x) ((x) == ' ')
252#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
253#define is_digit_char(x) (digit_chars[(unsigned char) x])
254
0234cb7c 255/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 256static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
257
258/* md_assemble() always leaves the strings it's passed unaltered. To
259 effect this we maintain a stack of saved characters that we've smashed
260 with '\0's (indicating end of strings for various sub-fields of the
47926f60 261 assembler instruction). */
252b5132 262static char save_stack[32];
ce8a8b2f 263static char *save_stack_p;
252b5132
RH		 264#define END_STRING_AND_SAVE(s) \
265 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
266#define RESTORE_END_STRING(s) \
267 do { *(s) = *--save_stack_p; } while (0)
268
47926f60 269/* The instruction we're assembling. */
252b5132
RH		 270static i386_insn i;
271
272/* Possible templates for current insn. */
273static const templates *current_templates;
274
31b2323c
L		 275/* Per instruction expressionS buffers: max displacements & immediates. */
276static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
277static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 278
47926f60
KH		 279/* Current operand we are working on. */
280static int this_operand;
252b5132 281
3e73aa7c
JH		 282/* We support four different modes. FLAG_CODE variable is used to distinguish
283 these. */
284
285enum flag_code {
286 CODE_32BIT,
287 CODE_16BIT,
288 CODE_64BIT };
f3c180ae 289#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 290
291static enum flag_code flag_code;
4fa24527 292static unsigned int object_64bit;
3e73aa7c
JH		 293static int use_rela_relocations = 0;
294
295/* The names used to print error messages. */
b77a7acd 296static const char *flag_code_names[] =
3e73aa7c
JH		 297 {
298 "32",
299 "16",
300 "64"
301 };
252b5132 302
47926f60
KH		 303/* 1 for intel syntax,
304 0 if att syntax. */
305static int intel_syntax = 0;
252b5132 306
47926f60
KH		 307/* 1 if register prefix % not required. */
308static int allow_naked_reg = 0;
252b5132 309
47926f60
KH		 310/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
311 leave, push, and pop instructions so that gcc has the same stack
312 frame as in 32 bit mode. */
313static char stackop_size = '\0';
eecb386c 314
12b55ccc
L		 315/* Non-zero to optimize code alignment. */
316int optimize_align_code = 1;
317
47926f60
KH		 318/* Non-zero to quieten some warnings. */
319static int quiet_warnings = 0;
a38cf1db 320
47926f60
KH		 321/* CPU name. */
322static const char *cpu_arch_name = NULL;
5c6af06e 323static const char *cpu_sub_arch_name = NULL;
a38cf1db 324
47926f60 325/* CPU feature flags. */
29b0f896 326static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 327
ccc9c027
L		 328/* If we have selected a cpu we are generating instructions for. */
329static int cpu_arch_tune_set = 0;
330
9103f4f4
L		 331/* Cpu we are generating instructions for. */
332static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
333
334/* CPU feature flags of cpu we are generating instructions for. */
335static unsigned int cpu_arch_tune_flags = 0;
336
ccc9c027
L		 337/* CPU instruction set architecture used. */
338static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
339
9103f4f4
L		 340/* CPU feature flags of instruction set architecture used. */
341static unsigned int cpu_arch_isa_flags = 0;
342
fddf5b5b
AM		 343/* If set, conditional jumps are not automatically promoted to handle
344 larger than a byte offset. */
345static unsigned int no_cond_jump_promotion = 0;
346
29b0f896 347/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 348static symbolS *GOT_symbol;
29b0f896 349
a4447b93
RH		 350/* The dwarf2 return column, adjusted for 32 or 64 bit. */
351unsigned int x86_dwarf2_return_column;
352
353/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
354int x86_cie_data_alignment;
355
252b5132 356/* Interface to relax_segment.
fddf5b5b
AM		 357 There are 3 major relax states for 386 jump insns because the
358 different types of jumps add different sizes to frags when we're
359 figuring out what sort of jump to choose to reach a given label. */
252b5132 360
47926f60 361/* Types. */
93c2a809
AM		 362#define UNCOND_JUMP 0
363#define COND_JUMP 1
364#define COND_JUMP86 2
fddf5b5b 365
47926f60 366/* Sizes. */
252b5132
RH		 367#define CODE16 1
368#define SMALL 0
29b0f896 369#define SMALL16 (SMALL | CODE16)
252b5132 370#define BIG 2
29b0f896 371#define BIG16 (BIG | CODE16)
252b5132
RH		 372
373#ifndef INLINE
374#ifdef __GNUC__
375#define INLINE __inline__
376#else
377#define INLINE
378#endif
379#endif
380
fddf5b5b
AM		 381#define ENCODE_RELAX_STATE(type, size) \
382 ((relax_substateT) (((type) << 2) | (size)))
383#define TYPE_FROM_RELAX_STATE(s) \
384 ((s) >> 2)
385#define DISP_SIZE_FROM_RELAX_STATE(s) \
386 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 387
388/* This table is used by relax_frag to promote short jumps to long
389 ones where necessary. SMALL (short) jumps may be promoted to BIG
390 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
391 don't allow a short jump in a 32 bit code segment to be promoted to
392 a 16 bit offset jump because it's slower (requires data size
393 prefix), and doesn't work, unless the destination is in the bottom
394 64k of the code segment (The top 16 bits of eip are zeroed). */
395
396const relax_typeS md_relax_table[] =
397{
24eab124
AM		 398 /* The fields are:
399 1) most positive reach of this state,
400 2) most negative reach of this state,
93c2a809 401 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 402 4) which index into the table to try if we can't fit into this one. */
252b5132 403
fddf5b5b 404 /* UNCOND_JUMP states. */
93c2a809
AM		 405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
406 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
407 /* dword jmp adds 4 bytes to frag:
408 0 extra opcode bytes, 4 displacement bytes. */
252b5132 409 {0, 0, 4, 0},
93c2a809
AM		 410 /* word jmp adds 2 byte2 to frag:
411 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 412 {0, 0, 2, 0},
413
93c2a809
AM		 414 /* COND_JUMP states. */
415 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
416 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
417 /* dword conditionals adds 5 bytes to frag:
418 1 extra opcode byte, 4 displacement bytes. */
419 {0, 0, 5, 0},
fddf5b5b 420 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 421 1 extra opcode byte, 2 displacement bytes. */
422 {0, 0, 3, 0},
423
424 /* COND_JUMP86 states. */
425 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
426 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
427 /* dword conditionals adds 5 bytes to frag:
428 1 extra opcode byte, 4 displacement bytes. */
429 {0, 0, 5, 0},
430 /* word conditionals add 4 bytes to frag:
431 1 displacement byte and a 3 byte long branch insn. */
432 {0, 0, 4, 0}
252b5132
RH		 433};
434
9103f4f4
L		 435static const arch_entry cpu_arch[] =
436{
437 {"generic32", PROCESSOR_GENERIC32,
d32cad65 438 Cpu186|Cpu286|Cpu386},
9103f4f4 439 {"generic64", PROCESSOR_GENERIC64,
d32cad65 440 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 441 |CpuMMX2|CpuSSE|CpuSSE2},
442 {"i8086", PROCESSOR_UNKNOWN,
d32cad65 443 0},
9103f4f4 444 {"i186", PROCESSOR_UNKNOWN,
d32cad65 445 Cpu186},
9103f4f4 446 {"i286", PROCESSOR_UNKNOWN,
d32cad65 447 Cpu186|Cpu286},
9103f4f4 448 {"i386", PROCESSOR_GENERIC32,
d32cad65 449 Cpu186|Cpu286|Cpu386},
9103f4f4 450 {"i486", PROCESSOR_I486,
d32cad65 451 Cpu186|Cpu286|Cpu386|Cpu486},
9103f4f4 452 {"i586", PROCESSOR_PENTIUM,
d32cad65 453 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 454 {"i686", PROCESSOR_PENTIUMPRO,
d32cad65 455 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 456 {"pentium", PROCESSOR_PENTIUM,
d32cad65 457 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 458 {"pentiumpro",PROCESSOR_PENTIUMPRO,
d32cad65 459 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 460 {"pentiumii", PROCESSOR_PENTIUMPRO,
d32cad65 461 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
9103f4f4 462 {"pentiumiii",PROCESSOR_PENTIUMPRO,
d32cad65 463 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
9103f4f4 464 {"pentium4", PROCESSOR_PENTIUM4,
d32cad65 465 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 466 |CpuMMX2|CpuSSE|CpuSSE2},
467 {"prescott", PROCESSOR_NOCONA,
d32cad65 468 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 469 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
470 {"nocona", PROCESSOR_NOCONA,
d32cad65 471 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 472 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 473 {"yonah", PROCESSOR_CORE,
d32cad65 474 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 475 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 476 {"core", PROCESSOR_CORE,
d32cad65 477 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
ef05d495
L		 478 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
479 {"merom", PROCESSOR_CORE2,
480 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
481 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
482 {"core2", PROCESSOR_CORE2,
483 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
484 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4 485 {"k6", PROCESSOR_K6,
d32cad65 486 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
9103f4f4 487 {"k6_2", PROCESSOR_K6,
d32cad65 488 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
9103f4f4 489 {"athlon", PROCESSOR_ATHLON,
d32cad65 490 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 491 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
492 {"sledgehammer", PROCESSOR_K8,
d32cad65 493 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 494 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
495 {"opteron", PROCESSOR_K8,
d32cad65 496 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 497 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
498 {"k8", PROCESSOR_K8,
d32cad65 499 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4 500 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
050dfa73 501 {"amdfam10", PROCESSOR_AMDFAM10,
d32cad65
L		 502 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
503 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
504 |CpuABM},
9103f4f4
L		 505 {".mmx", PROCESSOR_UNKNOWN,
506 CpuMMX},
507 {".sse", PROCESSOR_UNKNOWN,
508 CpuMMX|CpuMMX2|CpuSSE},
509 {".sse2", PROCESSOR_UNKNOWN,
510 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
511 {".sse3", PROCESSOR_UNKNOWN,
512 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495
L		 513 {".ssse3", PROCESSOR_UNKNOWN,
514 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4
L		 515 {".3dnow", PROCESSOR_UNKNOWN,
516 CpuMMX|Cpu3dnow},
517 {".3dnowa", PROCESSOR_UNKNOWN,
518 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
519 {".padlock", PROCESSOR_UNKNOWN,
520 CpuPadLock},
521 {".pacifica", PROCESSOR_UNKNOWN,
522 CpuSVME},
523 {".svme", PROCESSOR_UNKNOWN,
050dfa73
MM		 524 CpuSVME},
525 {".sse4a", PROCESSOR_UNKNOWN,
526 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
527 {".abm", PROCESSOR_UNKNOWN,
528 CpuABM}
e413e4e9
AM		 529};
530
29b0f896
AM		 531const pseudo_typeS md_pseudo_table[] =
532{
533#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
534 {"align", s_align_bytes, 0},
535#else
536 {"align", s_align_ptwo, 0},
537#endif
538 {"arch", set_cpu_arch, 0},
539#ifndef I386COFF
540 {"bss", s_bss, 0},
541#endif
542 {"ffloat", float_cons, 'f'},
543 {"dfloat", float_cons, 'd'},
544 {"tfloat", float_cons, 'x'},
545 {"value", cons, 2},
d182319b 546 {"slong", signed_cons, 4},
29b0f896
AM		 547 {"noopt", s_ignore, 0},
548 {"optim", s_ignore, 0},
549 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
550 {"code16", set_code_flag, CODE_16BIT},
551 {"code32", set_code_flag, CODE_32BIT},
552 {"code64", set_code_flag, CODE_64BIT},
553 {"intel_syntax", set_intel_syntax, 1},
554 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 555#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
556 {"largecomm", handle_large_common, 0},
07a53e5c
RH		 557#else
558 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
559 {"loc", dwarf2_directive_loc, 0},
560 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 561#endif
6482c264
NC		 562#ifdef TE_PE
563 {"secrel32", pe_directive_secrel, 0},
564#endif
29b0f896
AM		 565 {0, 0, 0}
566};
567
568/* For interface with expression (). */
569extern char *input_line_pointer;
570
571/* Hash table for instruction mnemonic lookup. */
572static struct hash_control *op_hash;
573
574/* Hash table for register lookup. */
575static struct hash_control *reg_hash;
576\f
252b5132
RH		 577void
578i386_align_code (fragP, count)
579 fragS *fragP;
580 int count;
581{
ce8a8b2f
AM		 582 /* Various efficient no-op patterns for aligning code labels.
583 Note: Don't try to assemble the instructions in the comments.
584 0L and 0w are not legal. */
252b5132
RH		 585 static const char f32_1[] =
586 {0x90}; /* nop */
587 static const char f32_2[] =
ccc9c027 588 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 589 static const char f32_3[] =
590 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
591 static const char f32_4[] =
592 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
593 static const char f32_5[] =
594 {0x90, /* nop */
595 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
596 static const char f32_6[] =
597 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
598 static const char f32_7[] =
599 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
600 static const char f32_8[] =
601 {0x90, /* nop */
602 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
603 static const char f32_9[] =
604 {0x89,0xf6, /* movl %esi,%esi */
605 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
606 static const char f32_10[] =
607 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
608 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
609 static const char f32_11[] =
610 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
611 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
612 static const char f32_12[] =
613 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
614 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
615 static const char f32_13[] =
616 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
617 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
618 static const char f32_14[] =
619 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
620 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
621 static const char f32_15[] =
622 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
623 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 624 static const char f16_3[] =
625 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 626 static const char f16_4[] =
627 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
628 static const char f16_5[] =
629 {0x90, /* nop */
630 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
631 static const char f16_6[] =
632 {0x89,0xf6, /* mov %si,%si */
633 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
634 static const char f16_7[] =
635 {0x8d,0x74,0x00, /* lea 0(%si),%si */
636 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
637 static const char f16_8[] =
638 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
639 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
640 static const char *const f32_patt[] = {
641 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
642 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
643 };
644 static const char *const f16_patt[] = {
c3332e24 645 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 646 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
647 };
ccc9c027
L		 648 /* nopl (%[re]ax) */
649 static const char alt_3[] =
650 {0x0f,0x1f,0x00};
651 /* nopl 0(%[re]ax) */
652 static const char alt_4[] =
653 {0x0f,0x1f,0x40,0x00};
654 /* nopl 0(%[re]ax,%[re]ax,1) */
655 static const char alt_5[] =
656 {0x0f,0x1f,0x44,0x00,0x00};
657 /* nopw 0(%[re]ax,%[re]ax,1) */
658 static const char alt_6[] =
659 {0x66,0x0f,0x1f,0x44,0x00,0x00};
660 /* nopl 0L(%[re]ax) */
661 static const char alt_7[] =
662 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
663 /* nopl 0L(%[re]ax,%[re]ax,1) */
664 static const char alt_8[] =
665 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
666 /* nopw 0L(%[re]ax,%[re]ax,1) */
667 static const char alt_9[] =
668 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
669 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
670 static const char alt_10[] =
671 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
672 /* data16
673 nopw %cs:0L(%[re]ax,%[re]ax,1) */
674 static const char alt_long_11[] =
675 {0x66,
676 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
677 /* data16
678 data16
679 nopw %cs:0L(%[re]ax,%[re]ax,1) */
680 static const char alt_long_12[] =
681 {0x66,
682 0x66,
683 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
684 /* data16
685 data16
686 data16
687 nopw %cs:0L(%[re]ax,%[re]ax,1) */
688 static const char alt_long_13[] =
689 {0x66,
690 0x66,
691 0x66,
692 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
693 /* data16
694 data16
695 data16
696 data16
697 nopw %cs:0L(%[re]ax,%[re]ax,1) */
698 static const char alt_long_14[] =
699 {0x66,
700 0x66,
701 0x66,
702 0x66,
703 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
704 /* data16
705 data16
706 data16
707 data16
708 data16
709 nopw %cs:0L(%[re]ax,%[re]ax,1) */
710 static const char alt_long_15[] =
711 {0x66,
712 0x66,
713 0x66,
714 0x66,
715 0x66,
716 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
717 /* nopl 0(%[re]ax,%[re]ax,1)
718 nopw 0(%[re]ax,%[re]ax,1) */
719 static const char alt_short_11[] =
720 {0x0f,0x1f,0x44,0x00,0x00,
721 0x66,0x0f,0x1f,0x44,0x00,0x00};
722 /* nopw 0(%[re]ax,%[re]ax,1)
723 nopw 0(%[re]ax,%[re]ax,1) */
724 static const char alt_short_12[] =
725 {0x66,0x0f,0x1f,0x44,0x00,0x00,
726 0x66,0x0f,0x1f,0x44,0x00,0x00};
727 /* nopw 0(%[re]ax,%[re]ax,1)
728 nopl 0L(%[re]ax) */
729 static const char alt_short_13[] =
730 {0x66,0x0f,0x1f,0x44,0x00,0x00,
731 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
732 /* nopl 0L(%[re]ax)
733 nopl 0L(%[re]ax) */
734 static const char alt_short_14[] =
735 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
736 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
737 /* nopl 0L(%[re]ax)
738 nopl 0L(%[re]ax,%[re]ax,1) */
739 static const char alt_short_15[] =
740 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
741 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
742 static const char *const alt_short_patt[] = {
743 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
744 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
745 alt_short_14, alt_short_15
746 };
747 static const char *const alt_long_patt[] = {
748 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
749 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
750 alt_long_14, alt_long_15
751 };
252b5132 752
33fef721
JH		 753 if (count <= 0 || count > 15)
754 return;
3e73aa7c 755
ccc9c027
L		 756 /* We need to decide which NOP sequence to use for 32bit and
757 64bit. When -mtune= is used:
758
759 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
760 f32_patt will be used.
050dfa73 761 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with 0x66 prefix will be used.
ef05d495 762 3. For PROCESSOR_CORE2, alt_long_patt will be used.
ccc9c027 763 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
ef05d495 764 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
ccc9c027
L		 765 and PROCESSOR_GENERIC64, alt_short_patt will be used.
766
767 When -mtune= isn't used, alt_short_patt will be used if
768 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
769
770 When -march= or .arch is used, we can't use anything beyond
771 cpu_arch_isa_flags. */
772
773 if (flag_code == CODE_16BIT)
774 {
775 memcpy (fragP->fr_literal + fragP->fr_fix,
776 f16_patt[count - 1], count);
777 if (count > 8)
778 /* Adjust jump offset. */
779 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
780 }
781 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
252b5132 782 {
33fef721
JH		 783 int i;
784 int nnops = (count + 3) / 4;
785 int len = count / nnops;
786 int remains = count - nnops * len;
787 int pos = 0;
788
ccc9c027
L		 789 /* The recommended way to pad 64bit code is to use NOPs preceded
790 by maximally four 0x66 prefixes. Balance the size of nops. */
33fef721 791 for (i = 0; i < remains; i++)
252b5132 792 {
33fef721
JH		 793 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
794 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
795 pos += len + 1;
796 }
797 for (; i < nnops; i++)
798 {
799 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
800 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
801 pos += len;
252b5132 802 }
252b5132 803 }
33fef721 804 else
ccc9c027
L		 805 {
806 const char *const *patt = NULL;
807
808 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
809 {
810 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
811 switch (cpu_arch_tune)
812 {
813 case PROCESSOR_UNKNOWN:
814 /* We use cpu_arch_isa_flags to check if we SHOULD
815 optimize for Cpu686. */
816 if ((cpu_arch_isa_flags & Cpu686) != 0)
817 patt = alt_short_patt;
818 else
819 patt = f32_patt;
820 break;
ef05d495 821 case PROCESSOR_CORE2:
ccc9c027
L		 822 patt = alt_long_patt;
823 break;
824 case PROCESSOR_PENTIUMPRO:
825 case PROCESSOR_PENTIUM4:
826 case PROCESSOR_NOCONA:
ef05d495 827 case PROCESSOR_CORE:
ccc9c027
L		 828 case PROCESSOR_K6:
829 case PROCESSOR_ATHLON:
830 case PROCESSOR_K8:
831 case PROCESSOR_GENERIC64:
050dfa73 832 case PROCESSOR_AMDFAM10:
ccc9c027
L		 833 patt = alt_short_patt;
834 break;
835 case PROCESSOR_I486:
836 case PROCESSOR_PENTIUM:
837 case PROCESSOR_GENERIC32:
838 patt = f32_patt;
839 break;
840 }
841 }
842 else
843 {
844 switch (cpu_arch_tune)
845 {
846 case PROCESSOR_UNKNOWN:
847 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
848 PROCESSOR_UNKNOWN. */
849 abort ();
850 break;
851
852 case PROCESSOR_I486:
853 case PROCESSOR_PENTIUM:
854 case PROCESSOR_PENTIUMPRO:
855 case PROCESSOR_PENTIUM4:
856 case PROCESSOR_NOCONA:
ef05d495 857 case PROCESSOR_CORE:
ccc9c027
L		 858 case PROCESSOR_K6:
859 case PROCESSOR_ATHLON:
860 case PROCESSOR_K8:
050dfa73 861 case PROCESSOR_AMDFAM10:
ccc9c027
L		 862 case PROCESSOR_GENERIC32:
863 /* We use cpu_arch_isa_flags to check if we CAN optimize
864 for Cpu686. */
865 if ((cpu_arch_isa_flags & Cpu686) != 0)
866 patt = alt_short_patt;
867 else
868 patt = f32_patt;
869 break;
ef05d495 870 case PROCESSOR_CORE2:
ccc9c027
L		 871 if ((cpu_arch_isa_flags & Cpu686) != 0)
872 patt = alt_long_patt;
873 else
874 patt = f32_patt;
875 break;
876 case PROCESSOR_GENERIC64:
877 patt = alt_short_patt;
878 break;
879 }
880 }
881
33fef721 882 memcpy (fragP->fr_literal + fragP->fr_fix,
ccc9c027
L		 883 patt[count - 1], count);
884 }
33fef721 885 fragP->fr_var = count;
252b5132
RH		 886}
887
252b5132
RH		 888static INLINE unsigned int
889mode_from_disp_size (t)
890 unsigned int t;
891{
3e73aa7c 892 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 893}
894
895static INLINE int
896fits_in_signed_byte (num)
847f7ad4 897 offsetT num;
252b5132
RH		 898{
899 return (num >= -128) && (num <= 127);
47926f60 900}
252b5132
RH		 901
902static INLINE int
903fits_in_unsigned_byte (num)
847f7ad4 904 offsetT num;
252b5132
RH		 905{
906 return (num & 0xff) == num;
47926f60 907}
252b5132
RH		 908
909static INLINE int
910fits_in_unsigned_word (num)
847f7ad4 911 offsetT num;
252b5132
RH		 912{
913 return (num & 0xffff) == num;
47926f60 914}
252b5132
RH		 915
916static INLINE int
917fits_in_signed_word (num)
847f7ad4 918 offsetT num;
252b5132
RH		 919{
920 return (-32768 <= num) && (num <= 32767);
47926f60 921}
2a962e6d 922
3e73aa7c
JH		 923static INLINE int
924fits_in_signed_long (num)
925 offsetT num ATTRIBUTE_UNUSED;
926{
927#ifndef BFD64
928 return 1;
929#else
930 return (!(((offsetT) -1 << 31) & num)
931 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
932#endif
933} /* fits_in_signed_long() */
2a962e6d 934
3e73aa7c
JH		 935static INLINE int
936fits_in_unsigned_long (num)
937 offsetT num ATTRIBUTE_UNUSED;
938{
939#ifndef BFD64
940 return 1;
941#else
942 return (num & (((offsetT) 2 << 31) - 1)) == num;
943#endif
944} /* fits_in_unsigned_long() */
252b5132
RH		 945
946static int
947smallest_imm_type (num)
847f7ad4 948 offsetT num;
252b5132 949{
d32cad65 950 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 951 {
952 /* This code is disabled on the 486 because all the Imm1 forms
953 in the opcode table are slower on the i486. They're the
954 versions with the implicitly specified single-position
955 displacement, which has another syntax if you really want to
956 use that form. */
957 if (num == 1)
3e73aa7c 958 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 959 }
252b5132 960 return (fits_in_signed_byte (num)
3e73aa7c 961 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 962 : fits_in_unsigned_byte (num)
3e73aa7c 963 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 964 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 965 ? (Imm16 | Imm32 | Imm32S | Imm64)
966 : fits_in_signed_long (num)
967 ? (Imm32 | Imm32S | Imm64)
968 : fits_in_unsigned_long (num)
969 ? (Imm32 | Imm64)
970 : Imm64);
47926f60 971}
252b5132 972
847f7ad4
AM		 973static offsetT
974offset_in_range (val, size)
975 offsetT val;
976 int size;
977{
508866be 978 addressT mask;
ba2adb93 979
847f7ad4
AM		 980 switch (size)
981 {
508866be
L		 982 case 1: mask = ((addressT) 1 << 8) - 1; break;
983 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 984 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 985#ifdef BFD64
986 case 8: mask = ((addressT) 2 << 63) - 1; break;
987#endif
47926f60 988 default: abort ();
847f7ad4
AM		 989 }
990
ba2adb93 991 /* If BFD64, sign extend val. */
3e73aa7c
JH		 992 if (!use_rela_relocations)
993 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
994 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 995
47926f60 996 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 997 {
998 char buf1[40], buf2[40];
999
1000 sprint_value (buf1, val);
1001 sprint_value (buf2, val & mask);
1002 as_warn (_("%s shortened to %s"), buf1, buf2);
1003 }
1004 return val & mask;
1005}
1006
252b5132
RH		 1007/* Returns 0 if attempting to add a prefix where one from the same
1008 class already exists, 1 if non rep/repne added, 2 if rep/repne
1009 added. */
1010static int
1011add_prefix (prefix)
1012 unsigned int prefix;
1013{
1014 int ret = 1;
b1905489 1015 unsigned int q;
252b5132 1016
29b0f896
AM		 1017 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1018 && flag_code == CODE_64BIT)
b1905489
JB		 1019 {
1020 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
1021 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
1022 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
1023 ret = 0;
1024 q = REX_PREFIX;
1025 }
3e73aa7c 1026 else
b1905489
JB		 1027 {
1028 switch (prefix)
1029 {
1030 default:
1031 abort ();
1032
1033 case CS_PREFIX_OPCODE:
1034 case DS_PREFIX_OPCODE:
1035 case ES_PREFIX_OPCODE:
1036 case FS_PREFIX_OPCODE:
1037 case GS_PREFIX_OPCODE:
1038 case SS_PREFIX_OPCODE:
1039 q = SEG_PREFIX;
1040 break;
1041
1042 case REPNE_PREFIX_OPCODE:
1043 case REPE_PREFIX_OPCODE:
1044 ret = 2;
1045 /* fall thru */
1046 case LOCK_PREFIX_OPCODE:
1047 q = LOCKREP_PREFIX;
1048 break;
1049
1050 case FWAIT_OPCODE:
1051 q = WAIT_PREFIX;
1052 break;
1053
1054 case ADDR_PREFIX_OPCODE:
1055 q = ADDR_PREFIX;
1056 break;
1057
1058 case DATA_PREFIX_OPCODE:
1059 q = DATA_PREFIX;
1060 break;
1061 }
1062 if (i.prefix[q] != 0)
1063 ret = 0;
1064 }
252b5132 1065
b1905489 1066 if (ret)
252b5132 1067 {
b1905489
JB		 1068 if (!i.prefix[q])
1069 ++i.prefixes;
1070 i.prefix[q] |= prefix;
252b5132 1071 }
b1905489
JB		 1072 else
1073 as_bad (_("same type of prefix used twice"));
252b5132 1074
252b5132
RH		 1075 return ret;
1076}
1077
1078static void
3e73aa7c 1079set_code_flag (value)
e5cb08ac 1080 int value;
eecb386c 1081{
3e73aa7c
JH		 1082 flag_code = value;
1083 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1084 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1085 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1086 {
1087 as_bad (_("64bit mode not supported on this CPU."));
1088 }
1089 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1090 {
1091 as_bad (_("32bit mode not supported on this CPU."));
1092 }
eecb386c
AM		 1093 stackop_size = '\0';
1094}
1095
1096static void
3e73aa7c
JH		 1097set_16bit_gcc_code_flag (new_code_flag)
1098 int new_code_flag;
252b5132 1099{
3e73aa7c
JH		 1100 flag_code = new_code_flag;
1101 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1102 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 1103 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1104}
1105
1106static void
1107set_intel_syntax (syntax_flag)
eecb386c 1108 int syntax_flag;
252b5132
RH		 1109{
1110 /* Find out if register prefixing is specified. */
1111 int ask_naked_reg = 0;
1112
1113 SKIP_WHITESPACE ();
29b0f896 1114 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1115 {
1116 char *string = input_line_pointer;
1117 int e = get_symbol_end ();
1118
47926f60 1119 if (strcmp (string, "prefix") == 0)
252b5132 1120 ask_naked_reg = 1;
47926f60 1121 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1122 ask_naked_reg = -1;
1123 else
d0b47220 1124 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1125 *input_line_pointer = e;
1126 }
1127 demand_empty_rest_of_line ();
c3332e24 1128
252b5132
RH		 1129 intel_syntax = syntax_flag;
1130
1131 if (ask_naked_reg == 0)
f86103b7
AM		 1132 allow_naked_reg = (intel_syntax
1133 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1134 else
1135 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 1136
1137 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1138 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 1139}
1140
e413e4e9
AM		 1141static void
1142set_cpu_arch (dummy)
47926f60 1143 int dummy ATTRIBUTE_UNUSED;
e413e4e9 1144{
47926f60 1145 SKIP_WHITESPACE ();
e413e4e9 1146
29b0f896 1147 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1148 {
1149 char *string = input_line_pointer;
1150 int e = get_symbol_end ();
9103f4f4 1151 unsigned int i;
e413e4e9 1152
9103f4f4 1153 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1154 {
1155 if (strcmp (string, cpu_arch[i].name) == 0)
1156 {
5c6af06e
JB		 1157 if (*string != '.')
1158 {
1159 cpu_arch_name = cpu_arch[i].name;
1160 cpu_sub_arch_name = NULL;
1161 cpu_arch_flags = (cpu_arch[i].flags
1162 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
ccc9c027 1163 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1164 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1165 if (!cpu_arch_tune_set)
1166 {
1167 cpu_arch_tune = cpu_arch_isa;
1168 cpu_arch_tune_flags = cpu_arch_isa_flags;
1169 }
5c6af06e
JB		 1170 break;
1171 }
1172 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1173 {
1174 cpu_sub_arch_name = cpu_arch[i].name;
1175 cpu_arch_flags |= cpu_arch[i].flags;
1176 }
1177 *input_line_pointer = e;
1178 demand_empty_rest_of_line ();
1179 return;
e413e4e9
AM		 1180 }
1181 }
9103f4f4 1182 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1183 as_bad (_("no such architecture: `%s'"), string);
1184
1185 *input_line_pointer = e;
1186 }
1187 else
1188 as_bad (_("missing cpu architecture"));
1189
fddf5b5b
AM		 1190 no_cond_jump_promotion = 0;
1191 if (*input_line_pointer == ','
29b0f896 1192 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1193 {
1194 char *string = ++input_line_pointer;
1195 int e = get_symbol_end ();
1196
1197 if (strcmp (string, "nojumps") == 0)
1198 no_cond_jump_promotion = 1;
1199 else if (strcmp (string, "jumps") == 0)
1200 ;
1201 else
1202 as_bad (_("no such architecture modifier: `%s'"), string);
1203
1204 *input_line_pointer = e;
1205 }
1206
e413e4e9
AM		 1207 demand_empty_rest_of_line ();
1208}
1209
b9d79e03
JH		 1210unsigned long
1211i386_mach ()
1212{
1213 if (!strcmp (default_arch, "x86_64"))
1214 return bfd_mach_x86_64;
1215 else if (!strcmp (default_arch, "i386"))
1216 return bfd_mach_i386_i386;
1217 else
1218 as_fatal (_("Unknown architecture"));
1219}
b9d79e03 1220\f
252b5132
RH		 1221void
1222md_begin ()
1223{
1224 const char *hash_err;
1225
47926f60 1226 /* Initialize op_hash hash table. */
252b5132
RH		 1227 op_hash = hash_new ();
1228
1229 {
29b0f896
AM		 1230 const template *optab;
1231 templates *core_optab;
252b5132 1232
47926f60
KH		 1233 /* Setup for loop. */
1234 optab = i386_optab;
252b5132
RH		 1235 core_optab = (templates *) xmalloc (sizeof (templates));
1236 core_optab->start = optab;
1237
1238 while (1)
1239 {
1240 ++optab;
1241 if (optab->name == NULL
1242 || strcmp (optab->name, (optab - 1)->name) != 0)
1243 {
1244 /* different name --> ship out current template list;
47926f60 1245 add to hash table; & begin anew. */
252b5132
RH		 1246 core_optab->end = optab;
1247 hash_err = hash_insert (op_hash,
1248 (optab - 1)->name,
1249 (PTR) core_optab);
1250 if (hash_err)
1251 {
252b5132
RH		 1252 as_fatal (_("Internal Error: Can't hash %s: %s"),
1253 (optab - 1)->name,
1254 hash_err);
1255 }
1256 if (optab->name == NULL)
1257 break;
1258 core_optab = (templates *) xmalloc (sizeof (templates));
1259 core_optab->start = optab;
1260 }
1261 }
1262 }
1263
47926f60 1264 /* Initialize reg_hash hash table. */
252b5132
RH		 1265 reg_hash = hash_new ();
1266 {
29b0f896 1267 const reg_entry *regtab;
252b5132
RH		 1268
1269 for (regtab = i386_regtab;
1270 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
1271 regtab++)
1272 {
1273 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1274 if (hash_err)
3e73aa7c
JH		 1275 as_fatal (_("Internal Error: Can't hash %s: %s"),
1276 regtab->reg_name,
1277 hash_err);
252b5132
RH		 1278 }
1279 }
1280
47926f60 1281 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1282 {
29b0f896
AM		 1283 int c;
1284 char *p;
252b5132
RH		 1285
1286 for (c = 0; c < 256; c++)
1287 {
3882b010 1288 if (ISDIGIT (c))
252b5132
RH		 1289 {
1290 digit_chars[c] = c;
1291 mnemonic_chars[c] = c;
1292 register_chars[c] = c;
1293 operand_chars[c] = c;
1294 }
3882b010 1295 else if (ISLOWER (c))
252b5132
RH		 1296 {
1297 mnemonic_chars[c] = c;
1298 register_chars[c] = c;
1299 operand_chars[c] = c;
1300 }
3882b010 1301 else if (ISUPPER (c))
252b5132 1302 {
3882b010 1303 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1304 register_chars[c] = mnemonic_chars[c];
1305 operand_chars[c] = c;
1306 }
1307
3882b010 1308 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1309 identifier_chars[c] = c;
1310 else if (c >= 128)
1311 {
1312 identifier_chars[c] = c;
1313 operand_chars[c] = c;
1314 }
1315 }
1316
1317#ifdef LEX_AT
1318 identifier_chars['@'] = '@';
32137342
NC		 1319#endif
1320#ifdef LEX_QM
1321 identifier_chars['?'] = '?';
1322 operand_chars['?'] = '?';
252b5132 1323#endif
252b5132 1324 digit_chars['-'] = '-';
791fe849 1325 mnemonic_chars['-'] = '-';
252b5132
RH		 1326 identifier_chars['_'] = '_';
1327 identifier_chars['.'] = '.';
1328
1329 for (p = operand_special_chars; *p != '\0'; p++)
1330 operand_chars[(unsigned char) *p] = *p;
1331 }
1332
1333#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1334 if (IS_ELF)
252b5132
RH		 1335 {
1336 record_alignment (text_section, 2);
1337 record_alignment (data_section, 2);
1338 record_alignment (bss_section, 2);
1339 }
1340#endif
a4447b93
RH		 1341
1342 if (flag_code == CODE_64BIT)
1343 {
1344 x86_dwarf2_return_column = 16;
1345 x86_cie_data_alignment = -8;
1346 }
1347 else
1348 {
1349 x86_dwarf2_return_column = 8;
1350 x86_cie_data_alignment = -4;
1351 }
252b5132
RH		 1352}
1353
1354void
1355i386_print_statistics (file)
1356 FILE *file;
1357{
1358 hash_print_statistics (file, "i386 opcode", op_hash);
1359 hash_print_statistics (file, "i386 register", reg_hash);
1360}
1361\f
252b5132
RH		 1362#ifdef DEBUG386
1363
ce8a8b2f 1364/* Debugging routines for md_assemble. */
252b5132
RH		 1365static void pi PARAMS ((char *, i386_insn *));
1366static void pte PARAMS ((template *));
1367static void pt PARAMS ((unsigned int));
1368static void pe PARAMS ((expressionS *));
1369static void ps PARAMS ((symbolS *));
1370
1371static void
1372pi (line, x)
1373 char *line;
1374 i386_insn *x;
1375{
09f131f2 1376 unsigned int i;
252b5132
RH		 1377
1378 fprintf (stdout, "%s: template ", line);
1379 pte (&x->tm);
09f131f2
JH		 1380 fprintf (stdout, " address: base %s index %s scale %x\n",
1381 x->base_reg ? x->base_reg->reg_name : "none",
1382 x->index_reg ? x->index_reg->reg_name : "none",
1383 x->log2_scale_factor);
1384 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1385 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1386 fprintf (stdout, " sib: base %x index %x scale %x\n",
1387 x->sib.base, x->sib.index, x->sib.scale);
1388 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1389 (x->rex & REX_MODE64) != 0,
1390 (x->rex & REX_EXTX) != 0,
1391 (x->rex & REX_EXTY) != 0,
1392 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1393 for (i = 0; i < x->operands; i++)
1394 {
1395 fprintf (stdout, " #%d: ", i + 1);
1396 pt (x->types[i]);
1397 fprintf (stdout, "\n");
1398 if (x->types[i]
3f4438ab 1399 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1400 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1401 if (x->types[i] & Imm)
520dc8e8 1402 pe (x->op[i].imms);
252b5132 1403 if (x->types[i] & Disp)
520dc8e8 1404 pe (x->op[i].disps);
252b5132
RH		 1405 }
1406}
1407
1408static void
1409pte (t)
1410 template *t;
1411{
09f131f2 1412 unsigned int i;
252b5132 1413 fprintf (stdout, " %d operands ", t->operands);
47926f60 1414 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1415 if (t->extension_opcode != None)
1416 fprintf (stdout, "ext %x ", t->extension_opcode);
1417 if (t->opcode_modifier & D)
1418 fprintf (stdout, "D");
1419 if (t->opcode_modifier & W)
1420 fprintf (stdout, "W");
1421 fprintf (stdout, "\n");
1422 for (i = 0; i < t->operands; i++)
1423 {
1424 fprintf (stdout, " #%d type ", i + 1);
1425 pt (t->operand_types[i]);
1426 fprintf (stdout, "\n");
1427 }
1428}
1429
1430static void
1431pe (e)
1432 expressionS *e;
1433{
24eab124 1434 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1435 fprintf (stdout, " add_number %ld (%lx)\n",
1436 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1437 if (e->X_add_symbol)
1438 {
1439 fprintf (stdout, " add_symbol ");
1440 ps (e->X_add_symbol);
1441 fprintf (stdout, "\n");
1442 }
1443 if (e->X_op_symbol)
1444 {
1445 fprintf (stdout, " op_symbol ");
1446 ps (e->X_op_symbol);
1447 fprintf (stdout, "\n");
1448 }
1449}
1450
1451static void
1452ps (s)
1453 symbolS *s;
1454{
1455 fprintf (stdout, "%s type %s%s",
1456 S_GET_NAME (s),
1457 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1458 segment_name (S_GET_SEGMENT (s)));
1459}
1460
7b81dfbb 1461static struct type_name
252b5132
RH		 1462 {
1463 unsigned int mask;
1464 char *tname;
1465 }
7b81dfbb 1466const type_names[] =
252b5132
RH		 1467{
1468 { Reg8, "r8" },
1469 { Reg16, "r16" },
1470 { Reg32, "r32" },
09f131f2 1471 { Reg64, "r64" },
252b5132
RH		 1472 { Imm8, "i8" },
1473 { Imm8S, "i8s" },
1474 { Imm16, "i16" },
1475 { Imm32, "i32" },
09f131f2
JH		 1476 { Imm32S, "i32s" },
1477 { Imm64, "i64" },
252b5132
RH		 1478 { Imm1, "i1" },
1479 { BaseIndex, "BaseIndex" },
1480 { Disp8, "d8" },
1481 { Disp16, "d16" },
1482 { Disp32, "d32" },
09f131f2
JH		 1483 { Disp32S, "d32s" },
1484 { Disp64, "d64" },
252b5132
RH		 1485 { InOutPortReg, "InOutPortReg" },
1486 { ShiftCount, "ShiftCount" },
1487 { Control, "control reg" },
1488 { Test, "test reg" },
1489 { Debug, "debug reg" },
1490 { FloatReg, "FReg" },
1491 { FloatAcc, "FAcc" },
1492 { SReg2, "SReg2" },
1493 { SReg3, "SReg3" },
1494 { Acc, "Acc" },
1495 { JumpAbsolute, "Jump Absolute" },
1496 { RegMMX, "rMMX" },
3f4438ab 1497 { RegXMM, "rXMM" },
252b5132
RH		 1498 { EsSeg, "es" },
1499 { 0, "" }
1500};
1501
1502static void
1503pt (t)
1504 unsigned int t;
1505{
29b0f896 1506 const struct type_name *ty;
252b5132 1507
09f131f2
JH		 1508 for (ty = type_names; ty->mask; ty++)
1509 if (t & ty->mask)
1510 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1511 fflush (stdout);
1512}
1513
1514#endif /* DEBUG386 */
1515\f
252b5132 1516static bfd_reloc_code_real_type
3956db08 1517reloc (unsigned int size,
64e74474
AM		 1518 int pcrel,
1519 int sign,
1520 bfd_reloc_code_real_type other)
252b5132 1521{
47926f60 1522 if (other != NO_RELOC)
3956db08
JB		 1523 {
1524 reloc_howto_type *reloc;
1525
1526 if (size == 8)
1527 switch (other)
1528 {
64e74474
AM		 1529 case BFD_RELOC_X86_64_GOT32:
1530 return BFD_RELOC_X86_64_GOT64;
1531 break;
1532 case BFD_RELOC_X86_64_PLTOFF64:
1533 return BFD_RELOC_X86_64_PLTOFF64;
1534 break;
1535 case BFD_RELOC_X86_64_GOTPC32:
1536 other = BFD_RELOC_X86_64_GOTPC64;
1537 break;
1538 case BFD_RELOC_X86_64_GOTPCREL:
1539 other = BFD_RELOC_X86_64_GOTPCREL64;
1540 break;
1541 case BFD_RELOC_X86_64_TPOFF32:
1542 other = BFD_RELOC_X86_64_TPOFF64;
1543 break;
1544 case BFD_RELOC_X86_64_DTPOFF32:
1545 other = BFD_RELOC_X86_64_DTPOFF64;
1546 break;
1547 default:
1548 break;
3956db08 1549 }
e05278af
JB		 1550
1551 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1552 if (size == 4 && flag_code != CODE_64BIT)
1553 sign = -1;
1554
3956db08
JB		 1555 reloc = bfd_reloc_type_lookup (stdoutput, other);
1556 if (!reloc)
1557 as_bad (_("unknown relocation (%u)"), other);
1558 else if (size != bfd_get_reloc_size (reloc))
1559 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1560 bfd_get_reloc_size (reloc),
1561 size);
1562 else if (pcrel && !reloc->pc_relative)
1563 as_bad (_("non-pc-relative relocation for pc-relative field"));
1564 else if ((reloc->complain_on_overflow == complain_overflow_signed
1565 && !sign)
1566 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1567 && sign > 0))
3956db08
JB		 1568 as_bad (_("relocated field and relocation type differ in signedness"));
1569 else
1570 return other;
1571 return NO_RELOC;
1572 }
252b5132
RH		 1573
1574 if (pcrel)
1575 {
3e73aa7c 1576 if (!sign)
3956db08 1577 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1578 switch (size)
1579 {
1580 case 1: return BFD_RELOC_8_PCREL;
1581 case 2: return BFD_RELOC_16_PCREL;
1582 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1583 case 8: return BFD_RELOC_64_PCREL;
252b5132 1584 }
3956db08 1585 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1586 }
1587 else
1588 {
3956db08 1589 if (sign > 0)
e5cb08ac 1590 switch (size)
3e73aa7c
JH		 1591 {
1592 case 4: return BFD_RELOC_X86_64_32S;
1593 }
1594 else
1595 switch (size)
1596 {
1597 case 1: return BFD_RELOC_8;
1598 case 2: return BFD_RELOC_16;
1599 case 4: return BFD_RELOC_32;
1600 case 8: return BFD_RELOC_64;
1601 }
3956db08
JB		 1602 as_bad (_("cannot do %s %u byte relocation"),
1603 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1604 }
1605
bfb32b52 1606 abort ();
252b5132
RH		 1607 return BFD_RELOC_NONE;
1608}
1609
47926f60
KH		 1610/* Here we decide which fixups can be adjusted to make them relative to
1611 the beginning of the section instead of the symbol. Basically we need
1612 to make sure that the dynamic relocations are done correctly, so in
1613 some cases we force the original symbol to be used. */
1614
252b5132 1615int
c0c949c7 1616tc_i386_fix_adjustable (fixP)
31312f95 1617 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1618{
6d249963 1619#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1620 if (!IS_ELF)
31312f95
AM		 1621 return 1;
1622
a161fe53
AM		 1623 /* Don't adjust pc-relative references to merge sections in 64-bit
1624 mode. */
1625 if (use_rela_relocations
1626 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1627 && fixP->fx_pcrel)
252b5132 1628 return 0;
31312f95 1629
8d01d9a9
AJ		 1630 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1631 and changed later by validate_fix. */
1632 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1633 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1634 return 0;
1635
ce8a8b2f 1636 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1637 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1638 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1639 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1640 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1641 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1642 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1643 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1644 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1645 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1646 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1647 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1648 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1649 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1650 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1651 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1652 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1653 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1654 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1655 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1656 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1657 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1658 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1659 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1660 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1661 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1662 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1663 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1664 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1665 return 0;
31312f95 1666#endif
252b5132
RH		 1667 return 1;
1668}
252b5132 1669
29b0f896 1670static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1671
1672static int
252b5132 1673intel_float_operand (mnemonic)
29b0f896 1674 const char *mnemonic;
252b5132 1675{
9306ca4a
JB		 1676 /* Note that the value returned is meaningful only for opcodes with (memory)
1677 operands, hence the code here is free to improperly handle opcodes that
1678 have no operands (for better performance and smaller code). */
1679
1680 if (mnemonic[0] != 'f')
1681 return 0; /* non-math */
1682
1683 switch (mnemonic[1])
1684 {
1685 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1686 the fs segment override prefix not currently handled because no
1687 call path can make opcodes without operands get here */
1688 case 'i':
1689 return 2 /* integer op */;
1690 case 'l':
1691 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1692 return 3; /* fldcw/fldenv */
1693 break;
1694 case 'n':
1695 if (mnemonic[2] != 'o' /* fnop */)
1696 return 3; /* non-waiting control op */
1697 break;
1698 case 'r':
1699 if (mnemonic[2] == 's')
1700 return 3; /* frstor/frstpm */
1701 break;
1702 case 's':
1703 if (mnemonic[2] == 'a')
1704 return 3; /* fsave */
1705 if (mnemonic[2] == 't')
1706 {
1707 switch (mnemonic[3])
1708 {
1709 case 'c': /* fstcw */
1710 case 'd': /* fstdw */
1711 case 'e': /* fstenv */
1712 case 's': /* fsts[gw] */
1713 return 3;
1714 }
1715 }
1716 break;
1717 case 'x':
1718 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1719 return 0; /* fxsave/fxrstor are not really math ops */
1720 break;
1721 }
252b5132 1722
9306ca4a 1723 return 1;
252b5132
RH		 1724}
1725
1726/* This is the guts of the machine-dependent assembler. LINE points to a
1727 machine dependent instruction. This function is supposed to emit
1728 the frags/bytes it assembles to. */
1729
1730void
1731md_assemble (line)
1732 char *line;
1733{
252b5132 1734 int j;
252b5132
RH		 1735 char mnemonic[MAX_MNEM_SIZE];
1736
47926f60 1737 /* Initialize globals. */
252b5132
RH		 1738 memset (&i, '\0', sizeof (i));
1739 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1740 i.reloc[j] = NO_RELOC;
252b5132
RH		 1741 memset (disp_expressions, '\0', sizeof (disp_expressions));
1742 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1743 save_stack_p = save_stack;
252b5132
RH		 1744
1745 /* First parse an instruction mnemonic & call i386_operand for the operands.
1746 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1747 start of a (possibly prefixed) mnemonic. */
252b5132 1748
29b0f896
AM		 1749 line = parse_insn (line, mnemonic);
1750 if (line == NULL)
1751 return;
252b5132 1752
29b0f896
AM		 1753 line = parse_operands (line, mnemonic);
1754 if (line == NULL)
1755 return;
252b5132 1756
050dfa73
MM		 1757 /* The order of the immediates should be reversed
1758 for 2 immediates extrq and insertq instructions */
1759 if ((i.imm_operands == 2) &&
1760 ((strcmp (mnemonic, "extrq") == 0)
1761 || (strcmp (mnemonic, "insertq") == 0)))
1762 {
1763 swap_imm_operands ();
1764 /* "extrq" and insertq" are the only two instructions whose operands
1765 have to be reversed even though they have two immediate operands.
1766 */
1767 if (intel_syntax)
1768 swap_operands ();
1769 }
1770
29b0f896
AM		 1771 /* Now we've parsed the mnemonic into a set of templates, and have the
1772 operands at hand. */
1773
1774 /* All intel opcodes have reversed operands except for "bound" and
1775 "enter". We also don't reverse intersegment "jmp" and "call"
1776 instructions with 2 immediate operands so that the immediate segment
050dfa73 1777 precedes the offset, as it does when in AT&T mode. */
29b0f896
AM		 1778 if (intel_syntax && i.operands > 1
1779 && (strcmp (mnemonic, "bound") != 0)
30123838 1780 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1781 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1782 swap_operands ();
1783
1784 if (i.imm_operands)
1785 optimize_imm ();
1786
b300c311
L		 1787 /* Don't optimize displacement for movabs since it only takes 64bit
1788 displacement. */
1789 if (i.disp_operands
1790 && (flag_code != CODE_64BIT
1791 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1792 optimize_disp ();
1793
1794 /* Next, we find a template that matches the given insn,
1795 making sure the overlap of the given operands types is consistent
1796 with the template operand types. */
252b5132 1797
29b0f896
AM		 1798 if (!match_template ())
1799 return;
252b5132 1800
cd61ebfe
AM		 1801 if (intel_syntax)
1802 {
1803 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1804 if (SYSV386_COMPAT
1805 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1806 i.tm.base_opcode ^= FloatR;
1807
1808 /* Zap movzx and movsx suffix. The suffix may have been set from
1809 "word ptr" or "byte ptr" on the source operand, but we'll use
1810 the suffix later to choose the destination register. */
1811 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1812 {
1813 if (i.reg_operands < 2
1814 && !i.suffix
1815 && (~i.tm.opcode_modifier
1816 & (No_bSuf
1817 | No_wSuf
1818 | No_lSuf
1819 | No_sSuf
1820 | No_xSuf
1821 | No_qSuf)))
1822 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1823
1824 i.suffix = 0;
1825 }
cd61ebfe 1826 }
24eab124 1827
29b0f896
AM		 1828 if (i.tm.opcode_modifier & FWait)
1829 if (!add_prefix (FWAIT_OPCODE))
1830 return;
252b5132 1831
29b0f896
AM		 1832 /* Check string instruction segment overrides. */
1833 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1834 {
1835 if (!check_string ())
5dd0794d 1836 return;
29b0f896 1837 }
5dd0794d 1838
29b0f896
AM		 1839 if (!process_suffix ())
1840 return;
e413e4e9 1841
29b0f896
AM		 1842 /* Make still unresolved immediate matches conform to size of immediate
1843 given in i.suffix. */
1844 if (!finalize_imm ())
1845 return;
252b5132 1846
29b0f896
AM		 1847 if (i.types[0] & Imm1)
1848 i.imm_operands = 0; /* kludge for shift insns. */
1849 if (i.types[0] & ImplicitRegister)
1850 i.reg_operands--;
1851 if (i.types[1] & ImplicitRegister)
1852 i.reg_operands--;
1853 if (i.types[2] & ImplicitRegister)
1854 i.reg_operands--;
252b5132 1855
29b0f896
AM		 1856 if (i.tm.opcode_modifier & ImmExt)
1857 {
02fc3089
L		 1858 expressionS *exp;
1859
b7d9ef37 1860 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
ca164297 1861 {
b7d9ef37 1862 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 1863 operands with an opcode suffix which is coded in the same
1864 place as an 8-bit immediate field would be. Here we check
1865 those operands and remove them afterwards. */
1866 unsigned int x;
1867
a4622f40 1868 for (x = 0; x < i.operands; x++)
ca164297
L		 1869 if (i.op[x].regs->reg_num != x)
1870 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
64e74474 1871 i.op[x].regs->reg_name, x + 1, i.tm.name);
ca164297
L		 1872 i.operands = 0;
1873 }
1874
29b0f896
AM		 1875 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1876 opcode suffix which is coded in the same place as an 8-bit
1877 immediate field would be. Here we fake an 8-bit immediate
1878 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1879
29b0f896 1880 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1881
29b0f896
AM		 1882 exp = &im_expressions[i.imm_operands++];
1883 i.op[i.operands].imms = exp;
1884 i.types[i.operands++] = Imm8;
1885 exp->X_op = O_constant;
1886 exp->X_add_number = i.tm.extension_opcode;
1887 i.tm.extension_opcode = None;
1888 }
252b5132 1889
29b0f896
AM		 1890 /* For insns with operands there are more diddles to do to the opcode. */
1891 if (i.operands)
1892 {
1893 if (!process_operands ())
1894 return;
1895 }
1896 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1897 {
1898 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1899 as_warn (_("translating to `%sp'"), i.tm.name);
1900 }
252b5132 1901
29b0f896
AM		 1902 /* Handle conversion of 'int $3' --> special int3 insn. */
1903 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1904 {
1905 i.tm.base_opcode = INT3_OPCODE;
1906 i.imm_operands = 0;
1907 }
252b5132 1908
29b0f896
AM		 1909 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1910 && i.op[0].disps->X_op == O_constant)
1911 {
1912 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1913 the absolute address given by the constant. Since ix86 jumps and
1914 calls are pc relative, we need to generate a reloc. */
1915 i.op[0].disps->X_add_symbol = &abs_symbol;
1916 i.op[0].disps->X_op = O_symbol;
1917 }
252b5132 1918
29b0f896
AM		 1919 if ((i.tm.opcode_modifier & Rex64) != 0)
1920 i.rex |= REX_MODE64;
252b5132 1921
29b0f896
AM		 1922 /* For 8 bit registers we need an empty rex prefix. Also if the
1923 instruction already has a prefix, we need to convert old
1924 registers to new ones. */
773f551c 1925
29b0f896
AM		 1926 if (((i.types[0] & Reg8) != 0
1927 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1928 || ((i.types[1] & Reg8) != 0
1929 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1930 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1931 && i.rex != 0))
1932 {
1933 int x;
726c5dcd 1934
29b0f896
AM		 1935 i.rex |= REX_OPCODE;
1936 for (x = 0; x < 2; x++)
1937 {
1938 /* Look for 8 bit operand that uses old registers. */
1939 if ((i.types[x] & Reg8) != 0
1940 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1941 {
29b0f896
AM		 1942 /* In case it is "hi" register, give up. */
1943 if (i.op[x].regs->reg_num > 3)
0477af35 1944 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1945 i.op[x].regs->reg_name);
773f551c 1946
29b0f896
AM		 1947 /* Otherwise it is equivalent to the extended register.
1948 Since the encoding doesn't change this is merely
1949 cosmetic cleanup for debug output. */
1950
1951 i.op[x].regs = i.op[x].regs + 8;
773f551c 1952 }
29b0f896
AM		 1953 }
1954 }
773f551c 1955
29b0f896
AM		 1956 if (i.rex != 0)
1957 add_prefix (REX_OPCODE | i.rex);
1958
1959 /* We are ready to output the insn. */
1960 output_insn ();
1961}
1962
1963static char *
1964parse_insn (line, mnemonic)
1965 char *line;
1966 char *mnemonic;
1967{
1968 char *l = line;
1969 char *token_start = l;
1970 char *mnem_p;
5c6af06e
JB		 1971 int supported;
1972 const template *t;
29b0f896
AM		 1973
1974 /* Non-zero if we found a prefix only acceptable with string insns. */
1975 const char *expecting_string_instruction = NULL;
45288df1 1976
29b0f896
AM		 1977 while (1)
1978 {
1979 mnem_p = mnemonic;
1980 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1981 {
1982 mnem_p++;
1983 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1984 {
29b0f896
AM		 1985 as_bad (_("no such instruction: `%s'"), token_start);
1986 return NULL;
1987 }
1988 l++;
1989 }
1990 if (!is_space_char (*l)
1991 && *l != END_OF_INSN
e44823cf
JB		 1992 && (intel_syntax
1993 || (*l != PREFIX_SEPARATOR
1994 && *l != ',')))
29b0f896
AM		 1995 {
1996 as_bad (_("invalid character %s in mnemonic"),
1997 output_invalid (*l));
1998 return NULL;
1999 }
2000 if (token_start == l)
2001 {
e44823cf 2002 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2003 as_bad (_("expecting prefix; got nothing"));
2004 else
2005 as_bad (_("expecting mnemonic; got nothing"));
2006 return NULL;
2007 }
45288df1 2008
29b0f896
AM		 2009 /* Look up instruction (or prefix) via hash table. */
2010 current_templates = hash_find (op_hash, mnemonic);
47926f60 2011
29b0f896
AM		 2012 if (*l != END_OF_INSN
2013 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2014 && current_templates
2015 && (current_templates->start->opcode_modifier & IsPrefix))
2016 {
2dd88dca
JB		 2017 if (current_templates->start->cpu_flags
2018 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
2019 {
2020 as_bad ((flag_code != CODE_64BIT
2021 ? _("`%s' is only supported in 64-bit mode")
2022 : _("`%s' is not supported in 64-bit mode")),
2023 current_templates->start->name);
2024 return NULL;
2025 }
29b0f896
AM		 2026 /* If we are in 16-bit mode, do not allow addr16 or data16.
2027 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2028 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
2029 && flag_code != CODE_64BIT
2030 && (((current_templates->start->opcode_modifier & Size32) != 0)
2031 ^ (flag_code == CODE_16BIT)))
2032 {
2033 as_bad (_("redundant %s prefix"),
2034 current_templates->start->name);
2035 return NULL;
45288df1 2036 }
29b0f896
AM		 2037 /* Add prefix, checking for repeated prefixes. */
2038 switch (add_prefix (current_templates->start->base_opcode))
2039 {
2040 case 0:
2041 return NULL;
2042 case 2:
2043 expecting_string_instruction = current_templates->start->name;
2044 break;
2045 }
2046 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2047 token_start = ++l;
2048 }
2049 else
2050 break;
2051 }
45288df1 2052
29b0f896
AM		 2053 if (!current_templates)
2054 {
2055 /* See if we can get a match by trimming off a suffix. */
2056 switch (mnem_p[-1])
2057 {
2058 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2059 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2060 i.suffix = SHORT_MNEM_SUFFIX;
2061 else
29b0f896
AM		 2062 case BYTE_MNEM_SUFFIX:
2063 case QWORD_MNEM_SUFFIX:
2064 i.suffix = mnem_p[-1];
2065 mnem_p[-1] = '\0';
2066 current_templates = hash_find (op_hash, mnemonic);
2067 break;
2068 case SHORT_MNEM_SUFFIX:
2069 case LONG_MNEM_SUFFIX:
2070 if (!intel_syntax)
2071 {
2072 i.suffix = mnem_p[-1];
2073 mnem_p[-1] = '\0';
2074 current_templates = hash_find (op_hash, mnemonic);
2075 }
2076 break;
252b5132 2077
29b0f896
AM		 2078 /* Intel Syntax. */
2079 case 'd':
2080 if (intel_syntax)
2081 {
9306ca4a 2082 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2083 i.suffix = SHORT_MNEM_SUFFIX;
2084 else
2085 i.suffix = LONG_MNEM_SUFFIX;
2086 mnem_p[-1] = '\0';
2087 current_templates = hash_find (op_hash, mnemonic);
2088 }
2089 break;
2090 }
2091 if (!current_templates)
2092 {
2093 as_bad (_("no such instruction: `%s'"), token_start);
2094 return NULL;
2095 }
2096 }
252b5132 2097
29b0f896
AM		 2098 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2099 {
2100 /* Check for a branch hint. We allow ",pt" and ",pn" for
2101 predict taken and predict not taken respectively.
2102 I'm not sure that branch hints actually do anything on loop
2103 and jcxz insns (JumpByte) for current Pentium4 chips. They
2104 may work in the future and it doesn't hurt to accept them
2105 now. */
2106 if (l[0] == ',' && l[1] == 'p')
2107 {
2108 if (l[2] == 't')
2109 {
2110 if (!add_prefix (DS_PREFIX_OPCODE))
2111 return NULL;
2112 l += 3;
2113 }
2114 else if (l[2] == 'n')
2115 {
2116 if (!add_prefix (CS_PREFIX_OPCODE))
2117 return NULL;
2118 l += 3;
2119 }
2120 }
2121 }
2122 /* Any other comma loses. */
2123 if (*l == ',')
2124 {
2125 as_bad (_("invalid character %s in mnemonic"),
2126 output_invalid (*l));
2127 return NULL;
2128 }
252b5132 2129
29b0f896 2130 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2131 supported = 0;
2132 for (t = current_templates->start; t < current_templates->end; ++t)
2133 {
2134 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2135 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 2136 supported |= 1;
5c6af06e 2137 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 2138 supported |= 2;
5c6af06e
JB		 2139 }
2140 if (!(supported & 2))
2141 {
2142 as_bad (flag_code == CODE_64BIT
2143 ? _("`%s' is not supported in 64-bit mode")
2144 : _("`%s' is only supported in 64-bit mode"),
2145 current_templates->start->name);
2146 return NULL;
2147 }
2148 if (!(supported & 1))
29b0f896 2149 {
5c6af06e
JB		 2150 as_warn (_("`%s' is not supported on `%s%s'"),
2151 current_templates->start->name,
2152 cpu_arch_name,
2153 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 2154 }
2155 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2156 {
2157 as_warn (_("use .code16 to ensure correct addressing mode"));
2158 }
252b5132 2159
29b0f896 2160 /* Check for rep/repne without a string instruction. */
f41bbced 2161 if (expecting_string_instruction)
29b0f896 2162 {
f41bbced
JB		 2163 static templates override;
2164
2165 for (t = current_templates->start; t < current_templates->end; ++t)
2166 if (t->opcode_modifier & IsString)
2167 break;
2168 if (t >= current_templates->end)
2169 {
2170 as_bad (_("expecting string instruction after `%s'"),
64e74474 2171 expecting_string_instruction);
f41bbced
JB		 2172 return NULL;
2173 }
2174 for (override.start = t; t < current_templates->end; ++t)
2175 if (!(t->opcode_modifier & IsString))
2176 break;
2177 override.end = t;
2178 current_templates = &override;
29b0f896 2179 }
252b5132 2180
29b0f896
AM		 2181 return l;
2182}
252b5132 2183
29b0f896
AM		 2184static char *
2185parse_operands (l, mnemonic)
2186 char *l;
2187 const char *mnemonic;
2188{
2189 char *token_start;
3138f287 2190
29b0f896
AM		 2191 /* 1 if operand is pending after ','. */
2192 unsigned int expecting_operand = 0;
252b5132 2193
29b0f896
AM		 2194 /* Non-zero if operand parens not balanced. */
2195 unsigned int paren_not_balanced;
2196
2197 while (*l != END_OF_INSN)
2198 {
2199 /* Skip optional white space before operand. */
2200 if (is_space_char (*l))
2201 ++l;
2202 if (!is_operand_char (*l) && *l != END_OF_INSN)
2203 {
2204 as_bad (_("invalid character %s before operand %d"),
2205 output_invalid (*l),
2206 i.operands + 1);
2207 return NULL;
2208 }
2209 token_start = l; /* after white space */
2210 paren_not_balanced = 0;
2211 while (paren_not_balanced || *l != ',')
2212 {
2213 if (*l == END_OF_INSN)
2214 {
2215 if (paren_not_balanced)
2216 {
2217 if (!intel_syntax)
2218 as_bad (_("unbalanced parenthesis in operand %d."),
2219 i.operands + 1);
2220 else
2221 as_bad (_("unbalanced brackets in operand %d."),
2222 i.operands + 1);
2223 return NULL;
2224 }
2225 else
2226 break; /* we are done */
2227 }
2228 else if (!is_operand_char (*l) && !is_space_char (*l))
2229 {
2230 as_bad (_("invalid character %s in operand %d"),
2231 output_invalid (*l),
2232 i.operands + 1);
2233 return NULL;
2234 }
2235 if (!intel_syntax)
2236 {
2237 if (*l == '(')
2238 ++paren_not_balanced;
2239 if (*l == ')')
2240 --paren_not_balanced;
2241 }
2242 else
2243 {
2244 if (*l == '[')
2245 ++paren_not_balanced;
2246 if (*l == ']')
2247 --paren_not_balanced;
2248 }
2249 l++;
2250 }
2251 if (l != token_start)
2252 { /* Yes, we've read in another operand. */
2253 unsigned int operand_ok;
2254 this_operand = i.operands++;
2255 if (i.operands > MAX_OPERANDS)
2256 {
2257 as_bad (_("spurious operands; (%d operands/instruction max)"),
2258 MAX_OPERANDS);
2259 return NULL;
2260 }
2261 /* Now parse operand adding info to 'i' as we go along. */
2262 END_STRING_AND_SAVE (l);
2263
2264 if (intel_syntax)
2265 operand_ok =
2266 i386_intel_operand (token_start,
2267 intel_float_operand (mnemonic));
2268 else
2269 operand_ok = i386_operand (token_start);
2270
2271 RESTORE_END_STRING (l);
2272 if (!operand_ok)
2273 return NULL;
2274 }
2275 else
2276 {
2277 if (expecting_operand)
2278 {
2279 expecting_operand_after_comma:
2280 as_bad (_("expecting operand after ','; got nothing"));
2281 return NULL;
2282 }
2283 if (*l == ',')
2284 {
2285 as_bad (_("expecting operand before ','; got nothing"));
2286 return NULL;
2287 }
2288 }
7f3f1ea2 2289
29b0f896
AM		 2290 /* Now *l must be either ',' or END_OF_INSN. */
2291 if (*l == ',')
2292 {
2293 if (*++l == END_OF_INSN)
2294 {
2295 /* Just skip it, if it's \n complain. */
2296 goto expecting_operand_after_comma;
2297 }
2298 expecting_operand = 1;
2299 }
2300 }
2301 return l;
2302}
7f3f1ea2 2303
050dfa73
MM		 2304static void
2305swap_imm_operands ()
2306{
2307 union i386_op temp_op;
2308 unsigned int temp_type;
2309 enum bfd_reloc_code_real temp_reloc;
2310 int xchg1 = 0;
2311 int xchg2 = 1;
2312
2313 temp_type = i.types[xchg2];
2314 i.types[xchg2] = i.types[xchg1];
2315 i.types[xchg1] = temp_type;
2316 temp_op = i.op[xchg2];
2317 i.op[xchg2] = i.op[xchg1];
2318 i.op[xchg1] = temp_op;
2319 temp_reloc = i.reloc[xchg2];
2320 i.reloc[xchg2] = i.reloc[xchg1];
2321 i.reloc[xchg1] = temp_reloc;
2322}
2323
2324
29b0f896
AM		 2325static void
2326swap_operands ()
2327{
2328 union i386_op temp_op;
2329 unsigned int temp_type;
f86103b7 2330 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 2331 int xchg1 = 0;
2332 int xchg2 = 0;
252b5132 2333
050dfa73
MM		 2334 if (i.operands == 4)
2335 /* There will be two exchanges in a 4 operand instruction.
2336 First exchange is the done inside this block.(1st and 4rth operand)
2337 The next exchange is done outside this block.(2nd and 3rd operand) */
2338 {
2339 xchg1 = 0;
2340 xchg2 = 3;
2341 temp_type = i.types[xchg2];
2342 i.types[xchg2] = i.types[xchg1];
2343 i.types[xchg1] = temp_type;
2344 temp_op = i.op[xchg2];
2345 i.op[xchg2] = i.op[xchg1];
2346 i.op[xchg1] = temp_op;
2347 temp_reloc = i.reloc[xchg2];
2348 i.reloc[xchg2] = i.reloc[xchg1];
2349 i.reloc[xchg1] = temp_reloc;
2350 xchg1 = 1;
2351 xchg2 = 2;
2352 }
2353
29b0f896
AM		 2354 if (i.operands == 2)
2355 {
2356 xchg1 = 0;
2357 xchg2 = 1;
2358 }
2359 else if (i.operands == 3)
2360 {
2361 xchg1 = 0;
2362 xchg2 = 2;
2363 }
2364 temp_type = i.types[xchg2];
2365 i.types[xchg2] = i.types[xchg1];
2366 i.types[xchg1] = temp_type;
2367 temp_op = i.op[xchg2];
2368 i.op[xchg2] = i.op[xchg1];
2369 i.op[xchg1] = temp_op;
2370 temp_reloc = i.reloc[xchg2];
2371 i.reloc[xchg2] = i.reloc[xchg1];
2372 i.reloc[xchg1] = temp_reloc;
2373
2374 if (i.mem_operands == 2)
2375 {
2376 const seg_entry *temp_seg;
2377 temp_seg = i.seg[0];
2378 i.seg[0] = i.seg[1];
2379 i.seg[1] = temp_seg;
2380 }
2381}
252b5132 2382
29b0f896
AM		 2383/* Try to ensure constant immediates are represented in the smallest
2384 opcode possible. */
2385static void
2386optimize_imm ()
2387{
2388 char guess_suffix = 0;
2389 int op;
252b5132 2390
29b0f896
AM		 2391 if (i.suffix)
2392 guess_suffix = i.suffix;
2393 else if (i.reg_operands)
2394 {
2395 /* Figure out a suffix from the last register operand specified.
2396 We can't do this properly yet, ie. excluding InOutPortReg,
2397 but the following works for instructions with immediates.
2398 In any case, we can't set i.suffix yet. */
2399 for (op = i.operands; --op >= 0;)
2400 if (i.types[op] & Reg)
252b5132 2401 {
29b0f896
AM		 2402 if (i.types[op] & Reg8)
2403 guess_suffix = BYTE_MNEM_SUFFIX;
2404 else if (i.types[op] & Reg16)
2405 guess_suffix = WORD_MNEM_SUFFIX;
2406 else if (i.types[op] & Reg32)
2407 guess_suffix = LONG_MNEM_SUFFIX;
2408 else if (i.types[op] & Reg64)
2409 guess_suffix = QWORD_MNEM_SUFFIX;
2410 break;
252b5132 2411 }
29b0f896
AM		 2412 }
2413 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2414 guess_suffix = WORD_MNEM_SUFFIX;
2415
2416 for (op = i.operands; --op >= 0;)
2417 if (i.types[op] & Imm)
2418 {
2419 switch (i.op[op].imms->X_op)
252b5132 2420 {
29b0f896
AM		 2421 case O_constant:
2422 /* If a suffix is given, this operand may be shortened. */
2423 switch (guess_suffix)
252b5132 2424 {
29b0f896
AM		 2425 case LONG_MNEM_SUFFIX:
2426 i.types[op] |= Imm32 | Imm64;
2427 break;
2428 case WORD_MNEM_SUFFIX:
2429 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2430 break;
2431 case BYTE_MNEM_SUFFIX:
2432 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2433 break;
252b5132 2434 }
252b5132 2435
29b0f896
AM		 2436 /* If this operand is at most 16 bits, convert it
2437 to a signed 16 bit number before trying to see
2438 whether it will fit in an even smaller size.
2439 This allows a 16-bit operand such as $0xffe0 to
2440 be recognised as within Imm8S range. */
2441 if ((i.types[op] & Imm16)
2442 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2443 {
29b0f896
AM		 2444 i.op[op].imms->X_add_number =
2445 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2446 }
2447 if ((i.types[op] & Imm32)
2448 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2449 == 0))
2450 {
2451 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2452 ^ ((offsetT) 1 << 31))
2453 - ((offsetT) 1 << 31));
2454 }
2455 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2456
29b0f896
AM		 2457 /* We must avoid matching of Imm32 templates when 64bit
2458 only immediate is available. */
2459 if (guess_suffix == QWORD_MNEM_SUFFIX)
2460 i.types[op] &= ~Imm32;
2461 break;
252b5132 2462
29b0f896
AM		 2463 case O_absent:
2464 case O_register:
2465 abort ();
2466
2467 /* Symbols and expressions. */
2468 default:
9cd96992
JB		 2469 /* Convert symbolic operand to proper sizes for matching, but don't
2470 prevent matching a set of insns that only supports sizes other
2471 than those matching the insn suffix. */
2472 {
2473 unsigned int mask, allowed = 0;
2474 const template *t;
2475
2476 for (t = current_templates->start; t < current_templates->end; ++t)
2477 allowed |= t->operand_types[op];
2478 switch (guess_suffix)
2479 {
2480 case QWORD_MNEM_SUFFIX:
2481 mask = Imm64 | Imm32S;
2482 break;
2483 case LONG_MNEM_SUFFIX:
2484 mask = Imm32;
2485 break;
2486 case WORD_MNEM_SUFFIX:
2487 mask = Imm16;
2488 break;
2489 case BYTE_MNEM_SUFFIX:
2490 mask = Imm8;
2491 break;
2492 default:
2493 mask = 0;
2494 break;
2495 }
64e74474
AM		 2496 if (mask & allowed)
2497 i.types[op] &= mask;
9cd96992 2498 }
29b0f896 2499 break;
252b5132 2500 }
29b0f896
AM		 2501 }
2502}
47926f60 2503
29b0f896
AM		 2504/* Try to use the smallest displacement type too. */
2505static void
2506optimize_disp ()
2507{
2508 int op;
3e73aa7c 2509
29b0f896 2510 for (op = i.operands; --op >= 0;)
b300c311 2511 if (i.types[op] & Disp)
252b5132 2512 {
b300c311 2513 if (i.op[op].disps->X_op == O_constant)
252b5132 2514 {
b300c311 2515 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2516
b300c311
L		 2517 if ((i.types[op] & Disp16)
2518 && (disp & ~(offsetT) 0xffff) == 0)
2519 {
2520 /* If this operand is at most 16 bits, convert
2521 to a signed 16 bit number and don't use 64bit
2522 displacement. */
2523 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2524 i.types[op] &= ~Disp64;
2525 }
2526 if ((i.types[op] & Disp32)
2527 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2528 {
2529 /* If this operand is at most 32 bits, convert
2530 to a signed 32 bit number and don't use 64bit
2531 displacement. */
2532 disp &= (((offsetT) 2 << 31) - 1);
2533 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2534 i.types[op] &= ~Disp64;
2535 }
2536 if (!disp && (i.types[op] & BaseIndex))
2537 {
2538 i.types[op] &= ~Disp;
2539 i.op[op].disps = 0;
2540 i.disp_operands--;
2541 }
2542 else if (flag_code == CODE_64BIT)
2543 {
2544 if (fits_in_signed_long (disp))
28a9d8f5
L		 2545 {
2546 i.types[op] &= ~Disp64;
2547 i.types[op] |= Disp32S;
2548 }
b300c311
L		 2549 if (fits_in_unsigned_long (disp))
2550 i.types[op] |= Disp32;
2551 }
2552 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2553 && fits_in_signed_byte (disp))
2554 i.types[op] |= Disp8;
252b5132 2555 }
67a4f2b7
AO		 2556 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2557 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2558 {
2559 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2560 i.op[op].disps, 0, i.reloc[op]);
2561 i.types[op] &= ~Disp;
2562 }
2563 else
b300c311
L		 2564 /* We only support 64bit displacement on constants. */
2565 i.types[op] &= ~Disp64;
252b5132 2566 }
29b0f896
AM		 2567}
2568
2569static int
2570match_template ()
2571{
2572 /* Points to template once we've found it. */
2573 const template *t;
f48ff2ae 2574 unsigned int overlap0, overlap1, overlap2, overlap3;
29b0f896
AM		 2575 unsigned int found_reverse_match;
2576 int suffix_check;
f48ff2ae 2577 unsigned int operand_types [MAX_OPERANDS];
539e75ad 2578 int addr_prefix_disp;
a5c311ca 2579 unsigned int j;
29b0f896 2580
f48ff2ae
L		 2581#if MAX_OPERANDS != 4
2582# error "MAX_OPERANDS must be 4."
2583#endif
2584
29b0f896
AM		 2585#define MATCH(overlap, given, template) \
2586 ((overlap & ~JumpAbsolute) \
2587 && (((given) & (BaseIndex | JumpAbsolute)) \
2588 == ((overlap) & (BaseIndex | JumpAbsolute))))
2589
2590 /* If given types r0 and r1 are registers they must be of the same type
2591 unless the expected operand type register overlap is null.
2592 Note that Acc in a template matches every size of reg. */
2593#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2594 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2595 || ((g0) & Reg) == ((g1) & Reg) \
2596 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2597
2598 overlap0 = 0;
2599 overlap1 = 0;
2600 overlap2 = 0;
f48ff2ae 2601 overlap3 = 0;
29b0f896 2602 found_reverse_match = 0;
a5c311ca
L		 2603 for (j = 0; j < MAX_OPERANDS; j++)
2604 operand_types [j] = 0;
539e75ad 2605 addr_prefix_disp = -1;
29b0f896
AM		 2606 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2607 ? No_bSuf
2608 : (i.suffix == WORD_MNEM_SUFFIX
2609 ? No_wSuf
2610 : (i.suffix == SHORT_MNEM_SUFFIX
2611 ? No_sSuf
2612 : (i.suffix == LONG_MNEM_SUFFIX
2613 ? No_lSuf
2614 : (i.suffix == QWORD_MNEM_SUFFIX
2615 ? No_qSuf
2616 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2617 ? No_xSuf : 0))))));
2618
45aa61fe 2619 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2620 {
539e75ad
L		 2621 addr_prefix_disp = -1;
2622
29b0f896
AM		 2623 /* Must have right number of operands. */
2624 if (i.operands != t->operands)
2625 continue;
2626
2627 /* Check the suffix, except for some instructions in intel mode. */
2628 if ((t->opcode_modifier & suffix_check)
2629 && !(intel_syntax
9306ca4a 2630 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2631 continue;
2632
a5c311ca
L		 2633 for (j = 0; j < MAX_OPERANDS; j++)
2634 operand_types [j] = t->operand_types [j];
539e75ad 2635
45aa61fe
AM		 2636 /* In general, don't allow 64-bit operands in 32-bit mode. */
2637 if (i.suffix == QWORD_MNEM_SUFFIX
2638 && flag_code != CODE_64BIT
2639 && (intel_syntax
2640 ? (!(t->opcode_modifier & IgnoreSize)
2641 && !intel_float_operand (t->name))
2642 : intel_float_operand (t->name) != 2)
539e75ad
L		 2643 && (!(operand_types[0] & (RegMMX | RegXMM))
2644 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
45aa61fe
AM		 2645 && (t->base_opcode != 0x0fc7
2646 || t->extension_opcode != 1 /* cmpxchg8b */))
2647 continue;
2648
29b0f896
AM		 2649 /* Do not verify operands when there are none. */
2650 else if (!t->operands)
2651 {
2652 if (t->cpu_flags & ~cpu_arch_flags)
2653 continue;
2654 /* We've found a match; break out of loop. */
2655 break;
2656 }
252b5132 2657
539e75ad
L		 2658 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2659 into Disp32/Disp16/Disp32 operand. */
2660 if (i.prefix[ADDR_PREFIX] != 0)
2661 {
a5c311ca 2662 unsigned int DispOn = 0, DispOff = 0;
539e75ad
L		 2663
2664 switch (flag_code)
2665 {
2666 case CODE_16BIT:
2667 DispOn = Disp32;
2668 DispOff = Disp16;
2669 break;
2670 case CODE_32BIT:
2671 DispOn = Disp16;
2672 DispOff = Disp32;
2673 break;
2674 case CODE_64BIT:
2675 DispOn = Disp32;
2676 DispOff = Disp64;
2677 break;
2678 }
2679
f48ff2ae 2680 for (j = 0; j < MAX_OPERANDS; j++)
539e75ad
L		 2681 {
2682 /* There should be only one Disp operand. */
2683 if ((operand_types[j] & DispOff))
2684 {
2685 addr_prefix_disp = j;
2686 operand_types[j] |= DispOn;
2687 operand_types[j] &= ~DispOff;
2688 break;
2689 }
2690 }
2691 }
2692
2693 overlap0 = i.types[0] & operand_types[0];
29b0f896
AM		 2694 switch (t->operands)
2695 {
2696 case 1:
539e75ad 2697 if (!MATCH (overlap0, i.types[0], operand_types[0]))
29b0f896
AM		 2698 continue;
2699 break;
2700 case 2:
2701 case 3:
f48ff2ae 2702 case 4:
539e75ad
L		 2703 overlap1 = i.types[1] & operand_types[1];
2704 if (!MATCH (overlap0, i.types[0], operand_types[0])
2705 || !MATCH (overlap1, i.types[1], operand_types[1])
cb712a9e 2706 /* monitor in SSE3 is a very special case. The first
708587a4 2707 register and the second register may have different
cb712a9e
L		 2708 sizes. */
2709 || !((t->base_opcode == 0x0f01
2710 && t->extension_opcode == 0xc8)
2711 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2712 operand_types[0],
cb712a9e 2713 overlap1, i.types[1],
539e75ad 2714 operand_types[1])))
29b0f896
AM		 2715 {
2716 /* Check if other direction is valid ... */
2717 if ((t->opcode_modifier & (D | FloatD)) == 0)
2718 continue;
2719
2720 /* Try reversing direction of operands. */
539e75ad
L		 2721 overlap0 = i.types[0] & operand_types[1];
2722 overlap1 = i.types[1] & operand_types[0];
2723 if (!MATCH (overlap0, i.types[0], operand_types[1])
2724 || !MATCH (overlap1, i.types[1], operand_types[0])
29b0f896 2725 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2726 operand_types[1],
29b0f896 2727 overlap1, i.types[1],
539e75ad 2728 operand_types[0]))
29b0f896
AM		 2729 {
2730 /* Does not match either direction. */
2731 continue;
2732 }
2733 /* found_reverse_match holds which of D or FloatDR
2734 we've found. */
2735 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2736 }
f48ff2ae 2737 else
29b0f896 2738 {
f48ff2ae 2739 /* Found a forward 2 operand match here. */
d1cbb4db
L		 2740 switch (t->operands)
2741 {
2742 case 4:
2743 overlap3 = i.types[3] & operand_types[3];
2744 case 3:
2745 overlap2 = i.types[2] & operand_types[2];
2746 break;
2747 }
29b0f896 2748
f48ff2ae
L		 2749 switch (t->operands)
2750 {
2751 case 4:
2752 if (!MATCH (overlap3, i.types[3], operand_types[3])
2753 || !CONSISTENT_REGISTER_MATCH (overlap2,
2754 i.types[2],
2755 operand_types[2],
2756 overlap3,
2757 i.types[3],
2758 operand_types[3]))
2759 continue;
2760 case 3:
2761 /* Here we make use of the fact that there are no
2762 reverse match 3 operand instructions, and all 3
2763 operand instructions only need to be checked for
2764 register consistency between operands 2 and 3. */
2765 if (!MATCH (overlap2, i.types[2], operand_types[2])
2766 || !CONSISTENT_REGISTER_MATCH (overlap1,
2767 i.types[1],
2768 operand_types[1],
2769 overlap2,
2770 i.types[2],
2771 operand_types[2]))
2772 continue;
2773 break;
2774 }
29b0f896 2775 }
f48ff2ae 2776 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 2777 slip through to break. */
2778 }
2779 if (t->cpu_flags & ~cpu_arch_flags)
2780 {
2781 found_reverse_match = 0;
2782 continue;
2783 }
2784 /* We've found a match; break out of loop. */
2785 break;
2786 }
2787
2788 if (t == current_templates->end)
2789 {
2790 /* We found no match. */
2791 as_bad (_("suffix or operands invalid for `%s'"),
2792 current_templates->start->name);
2793 return 0;
2794 }
252b5132 2795
29b0f896
AM		 2796 if (!quiet_warnings)
2797 {
2798 if (!intel_syntax
2799 && ((i.types[0] & JumpAbsolute)
539e75ad 2800 != (operand_types[0] & JumpAbsolute)))
29b0f896
AM		 2801 {
2802 as_warn (_("indirect %s without `*'"), t->name);
2803 }
2804
2805 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2806 == (IsPrefix | IgnoreSize))
2807 {
2808 /* Warn them that a data or address size prefix doesn't
2809 affect assembly of the next line of code. */
2810 as_warn (_("stand-alone `%s' prefix"), t->name);
2811 }
2812 }
2813
2814 /* Copy the template we found. */
2815 i.tm = *t;
539e75ad
L		 2816
2817 if (addr_prefix_disp != -1)
2818 i.tm.operand_types[addr_prefix_disp]
2819 = operand_types[addr_prefix_disp];
2820
29b0f896
AM		 2821 if (found_reverse_match)
2822 {
2823 /* If we found a reverse match we must alter the opcode
2824 direction bit. found_reverse_match holds bits to change
2825 (different for int & float insns). */
2826
2827 i.tm.base_opcode ^= found_reverse_match;
2828
539e75ad
L		 2829 i.tm.operand_types[0] = operand_types[1];
2830 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 2831 }
2832
2833 return 1;
2834}
2835
2836static int
2837check_string ()
2838{
2839 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2840 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2841 {
2842 if (i.seg[0] != NULL && i.seg[0] != &es)
2843 {
2844 as_bad (_("`%s' operand %d must use `%%es' segment"),
2845 i.tm.name,
2846 mem_op + 1);
2847 return 0;
2848 }
2849 /* There's only ever one segment override allowed per instruction.
2850 This instruction possibly has a legal segment override on the
2851 second operand, so copy the segment to where non-string
2852 instructions store it, allowing common code. */
2853 i.seg[0] = i.seg[1];
2854 }
2855 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2856 {
2857 if (i.seg[1] != NULL && i.seg[1] != &es)
2858 {
2859 as_bad (_("`%s' operand %d must use `%%es' segment"),
2860 i.tm.name,
2861 mem_op + 2);
2862 return 0;
2863 }
2864 }
2865 return 1;
2866}
2867
2868static int
543613e9 2869process_suffix (void)
29b0f896
AM		 2870{
2871 /* If matched instruction specifies an explicit instruction mnemonic
2872 suffix, use it. */
2873 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2874 {
2875 if (i.tm.opcode_modifier & Size16)
2876 i.suffix = WORD_MNEM_SUFFIX;
2877 else if (i.tm.opcode_modifier & Size64)
2878 i.suffix = QWORD_MNEM_SUFFIX;
2879 else
2880 i.suffix = LONG_MNEM_SUFFIX;
2881 }
2882 else if (i.reg_operands)
2883 {
2884 /* If there's no instruction mnemonic suffix we try to invent one
2885 based on register operands. */
2886 if (!i.suffix)
2887 {
2888 /* We take i.suffix from the last register operand specified,
2889 Destination register type is more significant than source
2890 register type. */
2891 int op;
543613e9 2892
29b0f896
AM		 2893 for (op = i.operands; --op >= 0;)
2894 if ((i.types[op] & Reg)
2895 && !(i.tm.operand_types[op] & InOutPortReg))
2896 {
2897 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2898 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2899 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2900 LONG_MNEM_SUFFIX);
2901 break;
2902 }
2903 }
2904 else if (i.suffix == BYTE_MNEM_SUFFIX)
2905 {
2906 if (!check_byte_reg ())
2907 return 0;
2908 }
2909 else if (i.suffix == LONG_MNEM_SUFFIX)
2910 {
2911 if (!check_long_reg ())
2912 return 0;
2913 }
2914 else if (i.suffix == QWORD_MNEM_SUFFIX)
2915 {
2916 if (!check_qword_reg ())
2917 return 0;
2918 }
2919 else if (i.suffix == WORD_MNEM_SUFFIX)
2920 {
2921 if (!check_word_reg ())
2922 return 0;
2923 }
2924 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2925 /* Do nothing if the instruction is going to ignore the prefix. */
2926 ;
2927 else
2928 abort ();
2929 }
9306ca4a
JB		 2930 else if ((i.tm.opcode_modifier & DefaultSize)
2931 && !i.suffix
2932 /* exclude fldenv/frstor/fsave/fstenv */
2933 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2934 {
2935 i.suffix = stackop_size;
2936 }
9306ca4a
JB		 2937 else if (intel_syntax
2938 && !i.suffix
2939 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2940 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2941 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2942 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2943 {
2944 switch (flag_code)
2945 {
2946 case CODE_64BIT:
2947 if (!(i.tm.opcode_modifier & No_qSuf))
2948 {
2949 i.suffix = QWORD_MNEM_SUFFIX;
2950 break;
2951 }
2952 case CODE_32BIT:
2953 if (!(i.tm.opcode_modifier & No_lSuf))
2954 i.suffix = LONG_MNEM_SUFFIX;
2955 break;
2956 case CODE_16BIT:
2957 if (!(i.tm.opcode_modifier & No_wSuf))
2958 i.suffix = WORD_MNEM_SUFFIX;
2959 break;
2960 }
2961 }
252b5132 2962
9306ca4a 2963 if (!i.suffix)
29b0f896 2964 {
9306ca4a
JB		 2965 if (!intel_syntax)
2966 {
2967 if (i.tm.opcode_modifier & W)
2968 {
2969 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2970 return 0;
2971 }
2972 }
2973 else
2974 {
64e74474
AM		 2975 unsigned int suffixes = (~i.tm.opcode_modifier
2976 & (No_bSuf
2977 | No_wSuf
2978 | No_lSuf
2979 | No_sSuf
2980 | No_xSuf
2981 | No_qSuf));
9306ca4a
JB		 2982
2983 if ((i.tm.opcode_modifier & W)
2984 || ((suffixes & (suffixes - 1))
2985 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2986 {
2987 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2988 return 0;
2989 }
2990 }
29b0f896 2991 }
252b5132 2992
9306ca4a
JB		 2993 /* Change the opcode based on the operand size given by i.suffix;
2994 We don't need to change things for byte insns. */
2995
29b0f896
AM		 2996 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2997 {
2998 /* It's not a byte, select word/dword operation. */
2999 if (i.tm.opcode_modifier & W)
3000 {
3001 if (i.tm.opcode_modifier & ShortForm)
3002 i.tm.base_opcode |= 8;
3003 else
3004 i.tm.base_opcode |= 1;
3005 }
0f3f3d8b 3006
29b0f896
AM		 3007 /* Now select between word & dword operations via the operand
3008 size prefix, except for instructions that will ignore this
3009 prefix anyway. */
cb712a9e
L		 3010 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
3011 {
3012 /* monitor in SSE3 is a very special case. The default size
3013 of AX is the size of mode. The address size override
3014 prefix will change the size of AX. */
3015 if (i.op->regs[0].reg_type &
3016 (flag_code == CODE_32BIT ? Reg16 : Reg32))
3017 if (!add_prefix (ADDR_PREFIX_OPCODE))
3018 return 0;
3019 }
3020 else if (i.suffix != QWORD_MNEM_SUFFIX
3021 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
3022 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
3023 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3024 || (flag_code == CODE_64BIT
3025 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 3026 {
3027 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3028
29b0f896
AM		 3029 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
3030 prefix = ADDR_PREFIX_OPCODE;
252b5132 3031
29b0f896
AM		 3032 if (!add_prefix (prefix))
3033 return 0;
24eab124 3034 }
252b5132 3035
29b0f896
AM		 3036 /* Set mode64 for an operand. */
3037 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3038 && flag_code == CODE_64BIT
29b0f896 3039 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L		 3040 {
3041 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3042 need rex64. */
3043 if (i.operands != 2
3044 || i.types [0] != (Acc | Reg64)
3045 || i.types [1] != (Acc | Reg64)
3046 || strcmp (i.tm.name, "xchg") != 0)
3047 i.rex |= REX_MODE64;
3048 }
3e73aa7c 3049
29b0f896
AM		 3050 /* Size floating point instruction. */
3051 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 3052 if (i.tm.opcode_modifier & FloatMF)
3053 i.tm.base_opcode ^= 4;
29b0f896 3054 }
7ecd2f8b 3055
29b0f896
AM		 3056 return 1;
3057}
3e73aa7c 3058
29b0f896 3059static int
543613e9 3060check_byte_reg (void)
29b0f896
AM		 3061{
3062 int op;
543613e9 3063
29b0f896
AM		 3064 for (op = i.operands; --op >= 0;)
3065 {
3066 /* If this is an eight bit register, it's OK. If it's the 16 or
3067 32 bit version of an eight bit register, we will just use the
3068 low portion, and that's OK too. */
3069 if (i.types[op] & Reg8)
3070 continue;
3071
3072 /* movzx and movsx should not generate this warning. */
3073 if (intel_syntax
3074 && (i.tm.base_opcode == 0xfb7
3075 || i.tm.base_opcode == 0xfb6
3076 || i.tm.base_opcode == 0x63
3077 || i.tm.base_opcode == 0xfbe
3078 || i.tm.base_opcode == 0xfbf))
3079 continue;
3080
65ec77d2 3081 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3082 {
3083 /* Prohibit these changes in the 64bit mode, since the
3084 lowering is more complicated. */
3085 if (flag_code == CODE_64BIT
3086 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3087 {
0f3f3d8b 3088 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3089 i.op[op].regs->reg_name,
3090 i.suffix);
3091 return 0;
3092 }
3093#if REGISTER_WARNINGS
3094 if (!quiet_warnings
3095 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3096 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3097 (i.op[op].regs + (i.types[op] & Reg16
3098 ? REGNAM_AL - REGNAM_AX
3099 : REGNAM_AL - REGNAM_EAX))->reg_name,
3100 i.op[op].regs->reg_name,
3101 i.suffix);
3102#endif
3103 continue;
3104 }
3105 /* Any other register is bad. */
3106 if (i.types[op] & (Reg | RegMMX | RegXMM
3107 | SReg2 | SReg3
3108 | Control | Debug | Test
3109 | FloatReg | FloatAcc))
3110 {
3111 as_bad (_("`%%%s' not allowed with `%s%c'"),
3112 i.op[op].regs->reg_name,
3113 i.tm.name,
3114 i.suffix);
3115 return 0;
3116 }
3117 }
3118 return 1;
3119}
3120
3121static int
3122check_long_reg ()
3123{
3124 int op;
3125
3126 for (op = i.operands; --op >= 0;)
3127 /* Reject eight bit registers, except where the template requires
3128 them. (eg. movzb) */
3129 if ((i.types[op] & Reg8) != 0
3130 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3131 {
3132 as_bad (_("`%%%s' not allowed with `%s%c'"),
3133 i.op[op].regs->reg_name,
3134 i.tm.name,
3135 i.suffix);
3136 return 0;
3137 }
3138 /* Warn if the e prefix on a general reg is missing. */
3139 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3140 && (i.types[op] & Reg16) != 0
3141 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3142 {
3143 /* Prohibit these changes in the 64bit mode, since the
3144 lowering is more complicated. */
3145 if (flag_code == CODE_64BIT)
252b5132 3146 {
0f3f3d8b 3147 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3148 i.op[op].regs->reg_name,
3149 i.suffix);
3150 return 0;
252b5132 3151 }
29b0f896
AM		 3152#if REGISTER_WARNINGS
3153 else
3154 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3155 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3156 i.op[op].regs->reg_name,
3157 i.suffix);
3158#endif
252b5132 3159 }
29b0f896
AM		 3160 /* Warn if the r prefix on a general reg is missing. */
3161 else if ((i.types[op] & Reg64) != 0
3162 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 3163 {
0f3f3d8b 3164 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3165 i.op[op].regs->reg_name,
3166 i.suffix);
3167 return 0;
3168 }
3169 return 1;
3170}
252b5132 3171
29b0f896
AM		 3172static int
3173check_qword_reg ()
3174{
3175 int op;
252b5132 3176
29b0f896
AM		 3177 for (op = i.operands; --op >= 0; )
3178 /* Reject eight bit registers, except where the template requires
3179 them. (eg. movzb) */
3180 if ((i.types[op] & Reg8) != 0
3181 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3182 {
3183 as_bad (_("`%%%s' not allowed with `%s%c'"),
3184 i.op[op].regs->reg_name,
3185 i.tm.name,
3186 i.suffix);
3187 return 0;
3188 }
3189 /* Warn if the e prefix on a general reg is missing. */
3190 else if (((i.types[op] & Reg16) != 0
3191 || (i.types[op] & Reg32) != 0)
3192 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3193 {
3194 /* Prohibit these changes in the 64bit mode, since the
3195 lowering is more complicated. */
0f3f3d8b 3196 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3197 i.op[op].regs->reg_name,
3198 i.suffix);
3199 return 0;
252b5132 3200 }
29b0f896
AM		 3201 return 1;
3202}
252b5132 3203
29b0f896
AM		 3204static int
3205check_word_reg ()
3206{
3207 int op;
3208 for (op = i.operands; --op >= 0;)
3209 /* Reject eight bit registers, except where the template requires
3210 them. (eg. movzb) */
3211 if ((i.types[op] & Reg8) != 0
3212 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3213 {
3214 as_bad (_("`%%%s' not allowed with `%s%c'"),
3215 i.op[op].regs->reg_name,
3216 i.tm.name,
3217 i.suffix);
3218 return 0;
3219 }
3220 /* Warn if the e prefix on a general reg is present. */
3221 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3222 && (i.types[op] & Reg32) != 0
3223 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 3224 {
29b0f896
AM		 3225 /* Prohibit these changes in the 64bit mode, since the
3226 lowering is more complicated. */
3227 if (flag_code == CODE_64BIT)
252b5132 3228 {
0f3f3d8b 3229 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3230 i.op[op].regs->reg_name,
3231 i.suffix);
3232 return 0;
252b5132 3233 }
29b0f896
AM		 3234 else
3235#if REGISTER_WARNINGS
3236 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3237 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3238 i.op[op].regs->reg_name,
3239 i.suffix);
3240#endif
3241 }
3242 return 1;
3243}
252b5132 3244
29b0f896
AM		 3245static int
3246finalize_imm ()
3247{
3248 unsigned int overlap0, overlap1, overlap2;
3249
3250 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 3251 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 3252 && overlap0 != Imm8 && overlap0 != Imm8S
3253 && overlap0 != Imm16 && overlap0 != Imm32S
3254 && overlap0 != Imm32 && overlap0 != Imm64)
3255 {
3256 if (i.suffix)
3257 {
3258 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3259 ? Imm8 | Imm8S
3260 : (i.suffix == WORD_MNEM_SUFFIX
3261 ? Imm16
3262 : (i.suffix == QWORD_MNEM_SUFFIX
3263 ? Imm64 | Imm32S
3264 : Imm32)));
3265 }
3266 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3267 || overlap0 == (Imm16 | Imm32)
3268 || overlap0 == (Imm16 | Imm32S))
3269 {
3270 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3271 ? Imm16 : Imm32S);
3272 }
3273 if (overlap0 != Imm8 && overlap0 != Imm8S
3274 && overlap0 != Imm16 && overlap0 != Imm32S
3275 && overlap0 != Imm32 && overlap0 != Imm64)
3276 {
3277 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
3278 return 0;
3279 }
3280 }
3281 i.types[0] = overlap0;
3282
3283 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 3284 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 3285 && overlap1 != Imm8 && overlap1 != Imm8S
3286 && overlap1 != Imm16 && overlap1 != Imm32S
3287 && overlap1 != Imm32 && overlap1 != Imm64)
3288 {
3289 if (i.suffix)
3290 {
3291 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3292 ? Imm8 | Imm8S
3293 : (i.suffix == WORD_MNEM_SUFFIX
3294 ? Imm16
3295 : (i.suffix == QWORD_MNEM_SUFFIX
3296 ? Imm64 | Imm32S
3297 : Imm32)));
3298 }
3299 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3300 || overlap1 == (Imm16 | Imm32)
3301 || overlap1 == (Imm16 | Imm32S))
3302 {
3303 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3304 ? Imm16 : Imm32S);
3305 }
3306 if (overlap1 != Imm8 && overlap1 != Imm8S
3307 && overlap1 != Imm16 && overlap1 != Imm32S
3308 && overlap1 != Imm32 && overlap1 != Imm64)
3309 {
3310 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
3311 return 0;
3312 }
3313 }
3314 i.types[1] = overlap1;
3315
3316 overlap2 = i.types[2] & i.tm.operand_types[2];
3317 assert ((overlap2 & Imm) == 0);
3318 i.types[2] = overlap2;
3319
3320 return 1;
3321}
3322
3323static int
3324process_operands ()
3325{
3326 /* Default segment register this instruction will use for memory
3327 accesses. 0 means unknown. This is only for optimizing out
3328 unnecessary segment overrides. */
3329 const seg_entry *default_seg = 0;
3330
3331 /* The imul $imm, %reg instruction is converted into
3332 imul $imm, %reg, %reg, and the clr %reg instruction
3333 is converted into xor %reg, %reg. */
3334 if (i.tm.opcode_modifier & regKludge)
3335 {
3336 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3337 /* Pretend we saw the extra register operand. */
cab737b9
L		 3338 assert (i.reg_operands == 1
3339 && i.op[first_reg_op + 1].regs == 0);
29b0f896
AM		 3340 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3341 i.types[first_reg_op + 1] = i.types[first_reg_op];
cab737b9
L		 3342 i.operands++;
3343 i.reg_operands++;
29b0f896
AM		 3344 }
3345
3346 if (i.tm.opcode_modifier & ShortForm)
3347 {
3348 /* The register or float register operand is in operand 0 or 1. */
3349 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3350 /* Register goes in low 3 bits of opcode. */
3351 i.tm.base_opcode |= i.op[op].regs->reg_num;
3352 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3353 i.rex |= REX_EXTZ;
3354 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
3355 {
3356 /* Warn about some common errors, but press on regardless.
3357 The first case can be generated by gcc (<= 2.8.1). */
3358 if (i.operands == 2)
3359 {
3360 /* Reversed arguments on faddp, fsubp, etc. */
3361 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3362 i.op[1].regs->reg_name,
3363 i.op[0].regs->reg_name);
3364 }
3365 else
3366 {
3367 /* Extraneous `l' suffix on fp insn. */
3368 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3369 i.op[0].regs->reg_name);
3370 }
3371 }
3372 }
3373 else if (i.tm.opcode_modifier & Modrm)
3374 {
3375 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3376 must be put into the modrm byte). Now, we make the modrm and
3377 index base bytes based on all the info we've collected. */
29b0f896
AM		 3378
3379 default_seg = build_modrm_byte ();
3380 }
3381 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
3382 {
3383 if (i.tm.base_opcode == POP_SEG_SHORT
3384 && i.op[0].regs->reg_num == 1)
3385 {
3386 as_bad (_("you can't `pop %%cs'"));
3387 return 0;
3388 }
3389 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3390 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3391 i.rex |= REX_EXTZ;
3392 }
3393 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
3394 {
3395 default_seg = &ds;
3396 }
3397 else if ((i.tm.opcode_modifier & IsString) != 0)
3398 {
3399 /* For the string instructions that allow a segment override
3400 on one of their operands, the default segment is ds. */
3401 default_seg = &ds;
3402 }
3403
30123838
JB		 3404 if ((i.tm.base_opcode == 0x8d /* lea */
3405 || (i.tm.cpu_flags & CpuSVME))
3406 && i.seg[0] && !quiet_warnings)
3407 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3408
3409 /* If a segment was explicitly specified, and the specified segment
3410 is not the default, use an opcode prefix to select it. If we
3411 never figured out what the default segment is, then default_seg
3412 will be zero at this point, and the specified segment prefix will
3413 always be used. */
29b0f896
AM		 3414 if ((i.seg[0]) && (i.seg[0] != default_seg))
3415 {
3416 if (!add_prefix (i.seg[0]->seg_prefix))
3417 return 0;
3418 }
3419 return 1;
3420}
3421
3422static const seg_entry *
3423build_modrm_byte ()
3424{
3425 const seg_entry *default_seg = 0;
3426
3427 /* i.reg_operands MUST be the number of real register operands;
3428 implicit registers do not count. */
3429 if (i.reg_operands == 2)
3430 {
3431 unsigned int source, dest;
cab737b9
L		 3432
3433 switch (i.operands)
3434 {
3435 case 2:
3436 source = 0;
3437 break;
3438 case 3:
c81128dc
L		 3439 /* When there are 3 operands, one of them may be immediate,
3440 which may be the first or the last operand. Otherwise,
3441 the first operand must be shift count register (cl). */
3442 assert (i.imm_operands == 1
3443 || (i.imm_operands == 0
3444 && (i.types[0] & ShiftCount)));
3445 source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0;
cab737b9
L		 3446 break;
3447 case 4:
3448 /* When there are 4 operands, the first two must be immediate
3449 operands. The source operand will be the 3rd one. */
3450 assert (i.imm_operands == 2
3451 && (i.types[0] & Imm)
3452 && (i.types[1] & Imm));
3453 source = 2;
3454 break;
3455 default:
3456 abort ();
3457 }
3458
29b0f896
AM		 3459 dest = source + 1;
3460
3461 i.rm.mode = 3;
3462 /* One of the register operands will be encoded in the i.tm.reg
3463 field, the other in the combined i.tm.mode and i.tm.regmem
3464 fields. If no form of this instruction supports a memory
3465 destination operand, then we assume the source operand may
3466 sometimes be a memory operand and so we need to store the
3467 destination in the i.rm.reg field. */
3468 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3469 {
3470 i.rm.reg = i.op[dest].regs->reg_num;
3471 i.rm.regmem = i.op[source].regs->reg_num;
3472 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3473 i.rex |= REX_EXTX;
3474 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3475 i.rex |= REX_EXTZ;
3476 }
3477 else
3478 {
3479 i.rm.reg = i.op[source].regs->reg_num;
3480 i.rm.regmem = i.op[dest].regs->reg_num;
3481 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3482 i.rex |= REX_EXTZ;
3483 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3484 i.rex |= REX_EXTX;
3485 }
c4a530c5
JB		 3486 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3487 {
3488 if (!((i.types[0] | i.types[1]) & Control))
3489 abort ();
3490 i.rex &= ~(REX_EXTX | REX_EXTZ);
3491 add_prefix (LOCK_PREFIX_OPCODE);
3492 }
29b0f896
AM		 3493 }
3494 else
3495 { /* If it's not 2 reg operands... */
3496 if (i.mem_operands)
3497 {
3498 unsigned int fake_zero_displacement = 0;
3499 unsigned int op = ((i.types[0] & AnyMem)
3500 ? 0
3501 : (i.types[1] & AnyMem) ? 1 : 2);
3502
3503 default_seg = &ds;
3504
3505 if (i.base_reg == 0)
3506 {
3507 i.rm.mode = 0;
3508 if (!i.disp_operands)
3509 fake_zero_displacement = 1;
3510 if (i.index_reg == 0)
3511 {
3512 /* Operand is just <disp> */
20f0a1fc 3513 if (flag_code == CODE_64BIT)
29b0f896
AM		 3514 {
3515 /* 64bit mode overwrites the 32bit absolute
3516 addressing by RIP relative addressing and
3517 absolute addressing is encoded by one of the
3518 redundant SIB forms. */
3519 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3520 i.sib.base = NO_BASE_REGISTER;
3521 i.sib.index = NO_INDEX_REGISTER;
fc225355
L		 3522 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3523 ? Disp32S : Disp32);
20f0a1fc 3524 }
fc225355
L		 3525 else if ((flag_code == CODE_16BIT)
3526 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 3527 {
3528 i.rm.regmem = NO_BASE_REGISTER_16;
3529 i.types[op] = Disp16;
3530 }
3531 else
3532 {
3533 i.rm.regmem = NO_BASE_REGISTER;
3534 i.types[op] = Disp32;
29b0f896
AM		 3535 }
3536 }
3537 else /* !i.base_reg && i.index_reg */
3538 {
3539 i.sib.index = i.index_reg->reg_num;
3540 i.sib.base = NO_BASE_REGISTER;
3541 i.sib.scale = i.log2_scale_factor;
3542 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3543 i.types[op] &= ~Disp;
3544 if (flag_code != CODE_64BIT)
3545 i.types[op] |= Disp32; /* Must be 32 bit */
3546 else
3547 i.types[op] |= Disp32S;
3548 if ((i.index_reg->reg_flags & RegRex) != 0)
3549 i.rex |= REX_EXTY;
3550 }
3551 }
3552 /* RIP addressing for 64bit mode. */
3553 else if (i.base_reg->reg_type == BaseIndex)
3554 {
3555 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3556 i.types[op] &= ~ Disp;
29b0f896 3557 i.types[op] |= Disp32S;
71903a11 3558 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 3559 if (! i.disp_operands)
3560 fake_zero_displacement = 1;
29b0f896
AM		 3561 }
3562 else if (i.base_reg->reg_type & Reg16)
3563 {
3564 switch (i.base_reg->reg_num)
3565 {
3566 case 3: /* (%bx) */
3567 if (i.index_reg == 0)
3568 i.rm.regmem = 7;
3569 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3570 i.rm.regmem = i.index_reg->reg_num - 6;
3571 break;
3572 case 5: /* (%bp) */
3573 default_seg = &ss;
3574 if (i.index_reg == 0)
3575 {
3576 i.rm.regmem = 6;
3577 if ((i.types[op] & Disp) == 0)
3578 {
3579 /* fake (%bp) into 0(%bp) */
3580 i.types[op] |= Disp8;
252b5132 3581 fake_zero_displacement = 1;
29b0f896
AM		 3582 }
3583 }
3584 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3585 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3586 break;
3587 default: /* (%si) -> 4 or (%di) -> 5 */
3588 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3589 }
3590 i.rm.mode = mode_from_disp_size (i.types[op]);
3591 }
3592 else /* i.base_reg and 32/64 bit mode */
3593 {
3594 if (flag_code == CODE_64BIT
3595 && (i.types[op] & Disp))
fc225355
L		 3596 i.types[op] = ((i.types[op] & Disp8)
3597 | (i.prefix[ADDR_PREFIX] == 0
3598 ? Disp32S : Disp32));
20f0a1fc 3599
29b0f896
AM		 3600 i.rm.regmem = i.base_reg->reg_num;
3601 if ((i.base_reg->reg_flags & RegRex) != 0)
3602 i.rex |= REX_EXTZ;
3603 i.sib.base = i.base_reg->reg_num;
3604 /* x86-64 ignores REX prefix bit here to avoid decoder
3605 complications. */
3606 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3607 {
3608 default_seg = &ss;
3609 if (i.disp_operands == 0)
3610 {
3611 fake_zero_displacement = 1;
3612 i.types[op] |= Disp8;
3613 }
3614 }
3615 else if (i.base_reg->reg_num == ESP_REG_NUM)
3616 {
3617 default_seg = &ss;
3618 }
3619 i.sib.scale = i.log2_scale_factor;
3620 if (i.index_reg == 0)
3621 {
3622 /* <disp>(%esp) becomes two byte modrm with no index
3623 register. We've already stored the code for esp
3624 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3625 Any base register besides %esp will not use the
3626 extra modrm byte. */
3627 i.sib.index = NO_INDEX_REGISTER;
3628#if !SCALE1_WHEN_NO_INDEX
3629 /* Another case where we force the second modrm byte. */
3630 if (i.log2_scale_factor)
3631 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3632#endif
29b0f896
AM		 3633 }
3634 else
3635 {
3636 i.sib.index = i.index_reg->reg_num;
3637 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3638 if ((i.index_reg->reg_flags & RegRex) != 0)
3639 i.rex |= REX_EXTY;
3640 }
67a4f2b7
AO		 3641
3642 if (i.disp_operands
3643 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3644 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3645 i.rm.mode = 0;
3646 else
3647 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3648 }
252b5132 3649
29b0f896
AM		 3650 if (fake_zero_displacement)
3651 {
3652 /* Fakes a zero displacement assuming that i.types[op]
3653 holds the correct displacement size. */
3654 expressionS *exp;
3655
3656 assert (i.op[op].disps == 0);
3657 exp = &disp_expressions[i.disp_operands++];
3658 i.op[op].disps = exp;
3659 exp->X_op = O_constant;
3660 exp->X_add_number = 0;
3661 exp->X_add_symbol = (symbolS *) 0;
3662 exp->X_op_symbol = (symbolS *) 0;
3663 }
3664 }
252b5132 3665
29b0f896
AM		 3666 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3667 (if any) based on i.tm.extension_opcode. Again, we must be
3668 careful to make sure that segment/control/debug/test/MMX
3669 registers are coded into the i.rm.reg field. */
3670 if (i.reg_operands)
3671 {
3672 unsigned int op =
3673 ((i.types[0]
3674 & (Reg | RegMMX | RegXMM
3675 | SReg2 | SReg3
3676 | Control | Debug | Test))
3677 ? 0
3678 : ((i.types[1]
3679 & (Reg | RegMMX | RegXMM
3680 | SReg2 | SReg3
3681 | Control | Debug | Test))
3682 ? 1
3683 : 2));
3684 /* If there is an extension opcode to put here, the register
3685 number must be put into the regmem field. */
3686 if (i.tm.extension_opcode != None)
3687 {
3688 i.rm.regmem = i.op[op].regs->reg_num;
3689 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3690 i.rex |= REX_EXTZ;
3691 }
3692 else
3693 {
3694 i.rm.reg = i.op[op].regs->reg_num;
3695 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3696 i.rex |= REX_EXTX;
3697 }
252b5132 3698
29b0f896
AM		 3699 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3700 must set it to 3 to indicate this is a register operand
3701 in the regmem field. */
3702 if (!i.mem_operands)
3703 i.rm.mode = 3;
3704 }
252b5132 3705
29b0f896
AM		 3706 /* Fill in i.rm.reg field with extension opcode (if any). */
3707 if (i.tm.extension_opcode != None)
3708 i.rm.reg = i.tm.extension_opcode;
3709 }
3710 return default_seg;
3711}
252b5132 3712
29b0f896
AM		 3713static void
3714output_branch ()
3715{
3716 char *p;
3717 int code16;
3718 int prefix;
3719 relax_substateT subtype;
3720 symbolS *sym;
3721 offsetT off;
3722
3723 code16 = 0;
3724 if (flag_code == CODE_16BIT)
3725 code16 = CODE16;
3726
3727 prefix = 0;
3728 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3729 {
29b0f896
AM		 3730 prefix = 1;
3731 i.prefixes -= 1;
3732 code16 ^= CODE16;
252b5132 3733 }
29b0f896
AM		 3734 /* Pentium4 branch hints. */
3735 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3736 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3737 {
29b0f896
AM		 3738 prefix++;
3739 i.prefixes--;
3740 }
3741 if (i.prefix[REX_PREFIX] != 0)
3742 {
3743 prefix++;
3744 i.prefixes--;
2f66722d
AM		 3745 }
3746
29b0f896
AM		 3747 if (i.prefixes != 0 && !intel_syntax)
3748 as_warn (_("skipping prefixes on this instruction"));
3749
3750 /* It's always a symbol; End frag & setup for relax.
3751 Make sure there is enough room in this frag for the largest
3752 instruction we may generate in md_convert_frag. This is 2
3753 bytes for the opcode and room for the prefix and largest
3754 displacement. */
3755 frag_grow (prefix + 2 + 4);
3756 /* Prefix and 1 opcode byte go in fr_fix. */
3757 p = frag_more (prefix + 1);
3758 if (i.prefix[DATA_PREFIX] != 0)
3759 *p++ = DATA_PREFIX_OPCODE;
3760 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3761 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3762 *p++ = i.prefix[SEG_PREFIX];
3763 if (i.prefix[REX_PREFIX] != 0)
3764 *p++ = i.prefix[REX_PREFIX];
3765 *p = i.tm.base_opcode;
3766
3767 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3768 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3769 else if ((cpu_arch_flags & Cpu386) != 0)
3770 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3771 else
3772 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3773 subtype |= code16;
3e73aa7c 3774
29b0f896
AM		 3775 sym = i.op[0].disps->X_add_symbol;
3776 off = i.op[0].disps->X_add_number;
3e73aa7c 3777
29b0f896
AM		 3778 if (i.op[0].disps->X_op != O_constant
3779 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3780 {
29b0f896
AM		 3781 /* Handle complex expressions. */
3782 sym = make_expr_symbol (i.op[0].disps);
3783 off = 0;
3784 }
3e73aa7c 3785
29b0f896
AM		 3786 /* 1 possible extra opcode + 4 byte displacement go in var part.
3787 Pass reloc in fr_var. */
3788 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3789}
3e73aa7c 3790
29b0f896
AM		 3791static void
3792output_jump ()
3793{
3794 char *p;
3795 int size;
3e02c1cc 3796 fixS *fixP;
29b0f896
AM		 3797
3798 if (i.tm.opcode_modifier & JumpByte)
3799 {
3800 /* This is a loop or jecxz type instruction. */
3801 size = 1;
3802 if (i.prefix[ADDR_PREFIX] != 0)
3803 {
3804 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3805 i.prefixes -= 1;
3806 }
3807 /* Pentium4 branch hints. */
3808 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3809 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3810 {
3811 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3812 i.prefixes--;
3e73aa7c
JH		 3813 }
3814 }
29b0f896
AM		 3815 else
3816 {
3817 int code16;
3e73aa7c 3818
29b0f896
AM		 3819 code16 = 0;
3820 if (flag_code == CODE_16BIT)
3821 code16 = CODE16;
3e73aa7c 3822
29b0f896
AM		 3823 if (i.prefix[DATA_PREFIX] != 0)
3824 {
3825 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3826 i.prefixes -= 1;
3827 code16 ^= CODE16;
3828 }
252b5132 3829
29b0f896
AM		 3830 size = 4;
3831 if (code16)
3832 size = 2;
3833 }
9fcc94b6 3834
29b0f896
AM		 3835 if (i.prefix[REX_PREFIX] != 0)
3836 {
3837 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3838 i.prefixes -= 1;
3839 }
252b5132 3840
29b0f896
AM		 3841 if (i.prefixes != 0 && !intel_syntax)
3842 as_warn (_("skipping prefixes on this instruction"));
e0890092 3843
29b0f896
AM		 3844 p = frag_more (1 + size);
3845 *p++ = i.tm.base_opcode;
e0890092 3846
3e02c1cc
AM		 3847 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3848 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3849
3850 /* All jumps handled here are signed, but don't use a signed limit
3851 check for 32 and 16 bit jumps as we want to allow wrap around at
3852 4G and 64k respectively. */
3853 if (size == 1)
3854 fixP->fx_signed = 1;
29b0f896 3855}
e0890092 3856
29b0f896
AM		 3857static void
3858output_interseg_jump ()
3859{
3860 char *p;
3861 int size;
3862 int prefix;
3863 int code16;
252b5132 3864
29b0f896
AM		 3865 code16 = 0;
3866 if (flag_code == CODE_16BIT)
3867 code16 = CODE16;
a217f122 3868
29b0f896
AM		 3869 prefix = 0;
3870 if (i.prefix[DATA_PREFIX] != 0)
3871 {
3872 prefix = 1;
3873 i.prefixes -= 1;
3874 code16 ^= CODE16;
3875 }
3876 if (i.prefix[REX_PREFIX] != 0)
3877 {
3878 prefix++;
3879 i.prefixes -= 1;
3880 }
252b5132 3881
29b0f896
AM		 3882 size = 4;
3883 if (code16)
3884 size = 2;
252b5132 3885
29b0f896
AM		 3886 if (i.prefixes != 0 && !intel_syntax)
3887 as_warn (_("skipping prefixes on this instruction"));
252b5132 3888
29b0f896
AM		 3889 /* 1 opcode; 2 segment; offset */
3890 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3891
29b0f896
AM		 3892 if (i.prefix[DATA_PREFIX] != 0)
3893 *p++ = DATA_PREFIX_OPCODE;
252b5132 3894
29b0f896
AM		 3895 if (i.prefix[REX_PREFIX] != 0)
3896 *p++ = i.prefix[REX_PREFIX];
252b5132 3897
29b0f896
AM		 3898 *p++ = i.tm.base_opcode;
3899 if (i.op[1].imms->X_op == O_constant)
3900 {
3901 offsetT n = i.op[1].imms->X_add_number;
252b5132 3902
29b0f896
AM		 3903 if (size == 2
3904 && !fits_in_unsigned_word (n)
3905 && !fits_in_signed_word (n))
3906 {
3907 as_bad (_("16-bit jump out of range"));
3908 return;
3909 }
3910 md_number_to_chars (p, n, size);
3911 }
3912 else
3913 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3914 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3915 if (i.op[0].imms->X_op != O_constant)
3916 as_bad (_("can't handle non absolute segment in `%s'"),
3917 i.tm.name);
3918 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3919}
a217f122 3920
29b0f896
AM		 3921static void
3922output_insn ()
3923{
2bbd9c25
JJ		 3924 fragS *insn_start_frag;
3925 offsetT insn_start_off;
3926
29b0f896
AM		 3927 /* Tie dwarf2 debug info to the address at the start of the insn.
3928 We can't do this after the insn has been output as the current
3929 frag may have been closed off. eg. by frag_var. */
3930 dwarf2_emit_insn (0);
3931
2bbd9c25
JJ		 3932 insn_start_frag = frag_now;
3933 insn_start_off = frag_now_fix ();
3934
29b0f896
AM		 3935 /* Output jumps. */
3936 if (i.tm.opcode_modifier & Jump)
3937 output_branch ();
3938 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3939 output_jump ();
3940 else if (i.tm.opcode_modifier & JumpInterSegment)
3941 output_interseg_jump ();
3942 else
3943 {
3944 /* Output normal instructions here. */
3945 char *p;
3946 unsigned char *q;
331d2d0d 3947 unsigned int prefix;
252b5132 3948
ef05d495
L		 3949 /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
3950 Streaming SIMD extensions 3 Instructions have 3 bytes. We may
3951 use one more higher byte to specify a prefix the instruction
3952 requires. */
3953 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
bc4bd9ab 3954 {
331d2d0d
L		 3955 if (i.tm.base_opcode & 0xff000000)
3956 {
3957 prefix = (i.tm.base_opcode >> 24) & 0xff;
3958 goto check_prefix;
3959 }
3960 }
3961 else if ((i.tm.base_opcode & 0xff0000) != 0)
3962 {
3963 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 3964 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3965 {
64e74474 3966 check_prefix:
bc4bd9ab
MK		 3967 if (prefix != REPE_PREFIX_OPCODE
3968 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3969 add_prefix (prefix);
3970 }
3971 else
331d2d0d 3972 add_prefix (prefix);
0f10071e 3973 }
252b5132 3974
29b0f896
AM		 3975 /* The prefix bytes. */
3976 for (q = i.prefix;
3977 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3978 q++)
3979 {
3980 if (*q)
3981 {
3982 p = frag_more (1);
3983 md_number_to_chars (p, (valueT) *q, 1);
3984 }
3985 }
252b5132 3986
29b0f896
AM		 3987 /* Now the opcode; be careful about word order here! */
3988 if (fits_in_unsigned_byte (i.tm.base_opcode))
3989 {
3990 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3991 }
3992 else
3993 {
ef05d495 3994 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
331d2d0d
L		 3995 {
3996 p = frag_more (3);
3997 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3998 }
3999 else
4000 p = frag_more (2);
0f10071e 4001
29b0f896
AM		 4002 /* Put out high byte first: can't use md_number_to_chars! */
4003 *p++ = (i.tm.base_opcode >> 8) & 0xff;
4004 *p = i.tm.base_opcode & 0xff;
4005 }
3e73aa7c 4006
29b0f896
AM		 4007 /* Now the modrm byte and sib byte (if present). */
4008 if (i.tm.opcode_modifier & Modrm)
4009 {
4010 p = frag_more (1);
4011 md_number_to_chars (p,
4012 (valueT) (i.rm.regmem << 0
4013 | i.rm.reg << 3
4014 | i.rm.mode << 6),
4015 1);
4016 /* If i.rm.regmem == ESP (4)
4017 && i.rm.mode != (Register mode)
4018 && not 16 bit
4019 ==> need second modrm byte. */
4020 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
4021 && i.rm.mode != 3
4022 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
4023 {
4024 p = frag_more (1);
4025 md_number_to_chars (p,
4026 (valueT) (i.sib.base << 0
4027 | i.sib.index << 3
4028 | i.sib.scale << 6),
4029 1);
4030 }
4031 }
3e73aa7c 4032
29b0f896 4033 if (i.disp_operands)
2bbd9c25 4034 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 4035
29b0f896 4036 if (i.imm_operands)
2bbd9c25 4037 output_imm (insn_start_frag, insn_start_off);
29b0f896 4038 }
252b5132 4039
29b0f896
AM		 4040#ifdef DEBUG386
4041 if (flag_debug)
4042 {
7b81dfbb 4043 pi ("" /*line*/, &i);
29b0f896
AM		 4044 }
4045#endif /* DEBUG386 */
4046}
252b5132 4047
29b0f896 4048static void
64e74474 4049output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4050{
4051 char *p;
4052 unsigned int n;
252b5132 4053
29b0f896
AM		 4054 for (n = 0; n < i.operands; n++)
4055 {
4056 if (i.types[n] & Disp)
4057 {
4058 if (i.op[n].disps->X_op == O_constant)
4059 {
4060 int size;
4061 offsetT val;
252b5132 4062
29b0f896
AM		 4063 size = 4;
4064 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4065 {
4066 size = 2;
4067 if (i.types[n] & Disp8)
4068 size = 1;
4069 if (i.types[n] & Disp64)
4070 size = 8;
4071 }
4072 val = offset_in_range (i.op[n].disps->X_add_number,
4073 size);
4074 p = frag_more (size);
4075 md_number_to_chars (p, val, size);
4076 }
4077 else
4078 {
f86103b7 4079 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4080 int size = 4;
4081 int sign = 0;
4082 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4083
4084 /* The PC relative address is computed relative
4085 to the instruction boundary, so in case immediate
4086 fields follows, we need to adjust the value. */
4087 if (pcrel && i.imm_operands)
4088 {
4089 int imm_size = 4;
4090 unsigned int n1;
252b5132 4091
29b0f896
AM		 4092 for (n1 = 0; n1 < i.operands; n1++)
4093 if (i.types[n1] & Imm)
252b5132 4094 {
29b0f896 4095 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 4096 {
29b0f896
AM		 4097 imm_size = 2;
4098 if (i.types[n1] & (Imm8 | Imm8S))
4099 imm_size = 1;
4100 if (i.types[n1] & Imm64)
4101 imm_size = 8;
252b5132 4102 }
29b0f896 4103 break;
252b5132 4104 }
29b0f896
AM		 4105 /* We should find the immediate. */
4106 if (n1 == i.operands)
4107 abort ();
4108 i.op[n].disps->X_add_number -= imm_size;
4109 }
520dc8e8 4110
29b0f896
AM		 4111 if (i.types[n] & Disp32S)
4112 sign = 1;
3e73aa7c 4113
29b0f896
AM		 4114 if (i.types[n] & (Disp16 | Disp64))
4115 {
4116 size = 2;
4117 if (i.types[n] & Disp64)
4118 size = 8;
4119 }
520dc8e8 4120
29b0f896 4121 p = frag_more (size);
2bbd9c25 4122 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4123 if (GOT_symbol
2bbd9c25 4124 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4125 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4126 || reloc_type == BFD_RELOC_X86_64_32S
4127 || (reloc_type == BFD_RELOC_64
4128 && object_64bit))
d6ab8113
JB		 4129 && (i.op[n].disps->X_op == O_symbol
4130 || (i.op[n].disps->X_op == O_add
4131 && ((symbol_get_value_expression
4132 (i.op[n].disps->X_op_symbol)->X_op)
4133 == O_subtract))))
4134 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4135 {
4136 offsetT add;
4137
4138 if (insn_start_frag == frag_now)
4139 add = (p - frag_now->fr_literal) - insn_start_off;
4140 else
4141 {
4142 fragS *fr;
4143
4144 add = insn_start_frag->fr_fix - insn_start_off;
4145 for (fr = insn_start_frag->fr_next;
4146 fr && fr != frag_now; fr = fr->fr_next)
4147 add += fr->fr_fix;
4148 add += p - frag_now->fr_literal;
4149 }
4150
4fa24527 4151 if (!object_64bit)
7b81dfbb
AJ		 4152 {
4153 reloc_type = BFD_RELOC_386_GOTPC;
4154 i.op[n].imms->X_add_number += add;
4155 }
4156 else if (reloc_type == BFD_RELOC_64)
4157 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4158 else
7b81dfbb
AJ		 4159 /* Don't do the adjustment for x86-64, as there
4160 the pcrel addressing is relative to the _next_
4161 insn, and that is taken care of in other code. */
d6ab8113 4162 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4163 }
062cd5e7 4164 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4165 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4166 }
4167 }
4168 }
4169}
252b5132 4170
29b0f896 4171static void
64e74474 4172output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4173{
4174 char *p;
4175 unsigned int n;
252b5132 4176
29b0f896
AM		 4177 for (n = 0; n < i.operands; n++)
4178 {
4179 if (i.types[n] & Imm)
4180 {
4181 if (i.op[n].imms->X_op == O_constant)
4182 {
4183 int size;
4184 offsetT val;
b4cac588 4185
29b0f896
AM		 4186 size = 4;
4187 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4188 {
4189 size = 2;
4190 if (i.types[n] & (Imm8 | Imm8S))
4191 size = 1;
4192 else if (i.types[n] & Imm64)
4193 size = 8;
4194 }
4195 val = offset_in_range (i.op[n].imms->X_add_number,
4196 size);
4197 p = frag_more (size);
4198 md_number_to_chars (p, val, size);
4199 }
4200 else
4201 {
4202 /* Not absolute_section.
4203 Need a 32-bit fixup (don't support 8bit
4204 non-absolute imms). Try to support other
4205 sizes ... */
f86103b7 4206 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4207 int size = 4;
4208 int sign = 0;
4209
4210 if ((i.types[n] & (Imm32S))
a7d61044
JB		 4211 && (i.suffix == QWORD_MNEM_SUFFIX
4212 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 4213 sign = 1;
4214 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4215 {
4216 size = 2;
4217 if (i.types[n] & (Imm8 | Imm8S))
4218 size = 1;
4219 if (i.types[n] & Imm64)
4220 size = 8;
4221 }
520dc8e8 4222
29b0f896
AM		 4223 p = frag_more (size);
4224 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4225
2bbd9c25
JJ		 4226 /* This is tough to explain. We end up with this one if we
4227 * have operands that look like
4228 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4229 * obtain the absolute address of the GOT, and it is strongly
4230 * preferable from a performance point of view to avoid using
4231 * a runtime relocation for this. The actual sequence of
4232 * instructions often look something like:
4233 *
4234 * call .L66
4235 * .L66:
4236 * popl %ebx
4237 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4238 *
4239 * The call and pop essentially return the absolute address
4240 * of the label .L66 and store it in %ebx. The linker itself
4241 * will ultimately change the first operand of the addl so
4242 * that %ebx points to the GOT, but to keep things simple, the
4243 * .o file must have this operand set so that it generates not
4244 * the absolute address of .L66, but the absolute address of
4245 * itself. This allows the linker itself simply treat a GOTPC
4246 * relocation as asking for a pcrel offset to the GOT to be
4247 * added in, and the addend of the relocation is stored in the
4248 * operand field for the instruction itself.
4249 *
4250 * Our job here is to fix the operand so that it would add
4251 * the correct offset so that %ebx would point to itself. The
4252 * thing that is tricky is that .-.L66 will point to the
4253 * beginning of the instruction, so we need to further modify
4254 * the operand so that it will point to itself. There are
4255 * other cases where you have something like:
4256 *
4257 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4258 *
4259 * and here no correction would be required. Internally in
4260 * the assembler we treat operands of this form as not being
4261 * pcrel since the '.' is explicitly mentioned, and I wonder
4262 * whether it would simplify matters to do it this way. Who
4263 * knows. In earlier versions of the PIC patches, the
4264 * pcrel_adjust field was used to store the correction, but
4265 * since the expression is not pcrel, I felt it would be
4266 * confusing to do it this way. */
4267
d6ab8113 4268 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4269 || reloc_type == BFD_RELOC_X86_64_32S
4270 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4271 && GOT_symbol
4272 && GOT_symbol == i.op[n].imms->X_add_symbol
4273 && (i.op[n].imms->X_op == O_symbol
4274 || (i.op[n].imms->X_op == O_add
4275 && ((symbol_get_value_expression
4276 (i.op[n].imms->X_op_symbol)->X_op)
4277 == O_subtract))))
4278 {
2bbd9c25
JJ		 4279 offsetT add;
4280
4281 if (insn_start_frag == frag_now)
4282 add = (p - frag_now->fr_literal) - insn_start_off;
4283 else
4284 {
4285 fragS *fr;
4286
4287 add = insn_start_frag->fr_fix - insn_start_off;
4288 for (fr = insn_start_frag->fr_next;
4289 fr && fr != frag_now; fr = fr->fr_next)
4290 add += fr->fr_fix;
4291 add += p - frag_now->fr_literal;
4292 }
4293
4fa24527 4294 if (!object_64bit)
d6ab8113 4295 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4296 else if (size == 4)
d6ab8113 4297 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4298 else if (size == 8)
4299 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4300 i.op[n].imms->X_add_number += add;
29b0f896 4301 }
29b0f896
AM		 4302 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4303 i.op[n].imms, 0, reloc_type);
4304 }
4305 }
4306 }
252b5132
RH		 4307}
4308\f
d182319b
JB		 4309/* x86_cons_fix_new is called via the expression parsing code when a
4310 reloc is needed. We use this hook to get the correct .got reloc. */
4311static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4312static int cons_sign = -1;
4313
4314void
4315x86_cons_fix_new (fragS *frag,
64e74474
AM		 4316 unsigned int off,
4317 unsigned int len,
4318 expressionS *exp)
d182319b
JB		 4319{
4320 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4321
4322 got_reloc = NO_RELOC;
4323
4324#ifdef TE_PE
4325 if (exp->X_op == O_secrel)
4326 {
4327 exp->X_op = O_symbol;
4328 r = BFD_RELOC_32_SECREL;
4329 }
4330#endif
4331
4332 fix_new_exp (frag, off, len, exp, 0, r);
4333}
4334
718ddfc0
JB		 4335#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4336# define lex_got(reloc, adjust, types) NULL
4337#else
f3c180ae
AM		 4338/* Parse operands of the form
4339 <symbol>@GOTOFF+<nnn>
4340 and similar .plt or .got references.
4341
4342 If we find one, set up the correct relocation in RELOC and copy the
4343 input string, minus the `@GOTOFF' into a malloc'd buffer for
4344 parsing by the calling routine. Return this buffer, and if ADJUST
4345 is non-null set it to the length of the string we removed from the
4346 input line. Otherwise return NULL. */
4347static char *
3956db08 4348lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 4349 int *adjust,
4350 unsigned int *types)
f3c180ae 4351{
7b81dfbb
AJ		 4352 /* Some of the relocations depend on the size of what field is to
4353 be relocated. But in our callers i386_immediate and i386_displacement
4354 we don't yet know the operand size (this will be set by insn
4355 matching). Hence we record the word32 relocation here,
4356 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4357 static const struct {
4358 const char *str;
4fa24527 4359 const enum bfd_reloc_code_real rel[2];
3956db08 4360 const unsigned int types64;
f3c180ae 4361 } gotrel[] = {
7b81dfbb 4362 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
4fa24527 4363 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
7b81dfbb 4364 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
4fa24527
JB		 4365 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
4366 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
4367 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
4368 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
4369 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
4370 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
4371 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4372 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
4373 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4374 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
4375 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
7b81dfbb 4376 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 },
67a4f2b7
AO		 4377 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
4378 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 4379 };
4380 char *cp;
4381 unsigned int j;
4382
718ddfc0
JB		 4383 if (!IS_ELF)
4384 return NULL;
4385
f3c180ae
AM		 4386 for (cp = input_line_pointer; *cp != '@'; cp++)
4387 if (is_end_of_line[(unsigned char) *cp])
4388 return NULL;
4389
4390 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4391 {
4392 int len;
4393
4394 len = strlen (gotrel[j].str);
28f81592 4395 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4396 {
4fa24527 4397 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4398 {
28f81592
AM		 4399 int first, second;
4400 char *tmpbuf, *past_reloc;
f3c180ae 4401
4fa24527 4402 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 4403 if (adjust)
4404 *adjust = len;
f3c180ae 4405
3956db08
JB		 4406 if (types)
4407 {
4408 if (flag_code != CODE_64BIT)
4409 *types = Imm32|Disp32;
4410 else
4411 *types = gotrel[j].types64;
4412 }
4413
f3c180ae
AM		 4414 if (GOT_symbol == NULL)
4415 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4416
4417 /* Replace the relocation token with ' ', so that
4418 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 4419
4420 /* The length of the first part of our input line. */
f3c180ae 4421 first = cp - input_line_pointer;
28f81592
AM		 4422
4423 /* The second part goes from after the reloc token until
4424 (and including) an end_of_line char. Don't use strlen
4425 here as the end_of_line char may not be a NUL. */
4426 past_reloc = cp + 1 + len;
4427 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4428 ;
4429 second = cp - past_reloc;
4430
4431 /* Allocate and copy string. The trailing NUL shouldn't
4432 be necessary, but be safe. */
4433 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 4434 memcpy (tmpbuf, input_line_pointer, first);
4435 tmpbuf[first] = ' ';
28f81592
AM		 4436 memcpy (tmpbuf + first + 1, past_reloc, second);
4437 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 4438 return tmpbuf;
4439 }
4440
4fa24527
JB		 4441 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4442 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 4443 return NULL;
4444 }
4445 }
4446
4447 /* Might be a symbol version string. Don't as_bad here. */
4448 return NULL;
4449}
4450
f3c180ae
AM		 4451void
4452x86_cons (exp, size)
4453 expressionS *exp;
4454 int size;
4455{
4fa24527 4456 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 4457 {
4458 /* Handle @GOTOFF and the like in an expression. */
4459 char *save;
4460 char *gotfree_input_line;
4461 int adjust;
4462
4463 save = input_line_pointer;
3956db08 4464 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4465 if (gotfree_input_line)
4466 input_line_pointer = gotfree_input_line;
4467
4468 expression (exp);
4469
4470 if (gotfree_input_line)
4471 {
4472 /* expression () has merrily parsed up to the end of line,
4473 or a comma - in the wrong buffer. Transfer how far
4474 input_line_pointer has moved to the right buffer. */
4475 input_line_pointer = (save
4476 + (input_line_pointer - gotfree_input_line)
4477 + adjust);
4478 free (gotfree_input_line);
4479 }
4480 }
4481 else
4482 expression (exp);
4483}
4484#endif
4485
d182319b 4486static void signed_cons (int size)
6482c264 4487{
d182319b
JB		 4488 if (flag_code == CODE_64BIT)
4489 cons_sign = 1;
4490 cons (size);
4491 cons_sign = -1;
6482c264
NC		 4492}
4493
d182319b 4494#ifdef TE_PE
6482c264
NC		 4495static void
4496pe_directive_secrel (dummy)
4497 int dummy ATTRIBUTE_UNUSED;
4498{
4499 expressionS exp;
4500
4501 do
4502 {
4503 expression (&exp);
4504 if (exp.X_op == O_symbol)
4505 exp.X_op = O_secrel;
4506
4507 emit_expr (&exp, 4);
4508 }
4509 while (*input_line_pointer++ == ',');
4510
4511 input_line_pointer--;
4512 demand_empty_rest_of_line ();
4513}
6482c264
NC		 4514#endif
4515
252b5132 4516static int
70e41ade 4517i386_immediate (char *imm_start)
252b5132
RH		 4518{
4519 char *save_input_line_pointer;
f3c180ae 4520 char *gotfree_input_line;
252b5132 4521 segT exp_seg = 0;
47926f60 4522 expressionS *exp;
3956db08 4523 unsigned int types = ~0U;
252b5132
RH		 4524
4525 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4526 {
31b2323c
L		 4527 as_bad (_("at most %d immediate operands are allowed"),
4528 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 4529 return 0;
4530 }
4531
4532 exp = &im_expressions[i.imm_operands++];
520dc8e8 4533 i.op[this_operand].imms = exp;
252b5132
RH		 4534
4535 if (is_space_char (*imm_start))
4536 ++imm_start;
4537
4538 save_input_line_pointer = input_line_pointer;
4539 input_line_pointer = imm_start;
4540
3956db08 4541 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4542 if (gotfree_input_line)
4543 input_line_pointer = gotfree_input_line;
252b5132
RH		 4544
4545 exp_seg = expression (exp);
4546
83183c0c 4547 SKIP_WHITESPACE ();
252b5132 4548 if (*input_line_pointer)
f3c180ae 4549 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4550
4551 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4552 if (gotfree_input_line)
4553 free (gotfree_input_line);
252b5132 4554
2daf4fd8 4555 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4556 {
47926f60 4557 /* Missing or bad expr becomes absolute 0. */
d0b47220 4558 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4559 imm_start);
252b5132
RH		 4560 exp->X_op = O_constant;
4561 exp->X_add_number = 0;
4562 exp->X_add_symbol = (symbolS *) 0;
4563 exp->X_op_symbol = (symbolS *) 0;
252b5132 4564 }
3e73aa7c 4565 else if (exp->X_op == O_constant)
252b5132 4566 {
47926f60 4567 /* Size it properly later. */
3e73aa7c
JH		 4568 i.types[this_operand] |= Imm64;
4569 /* If BFD64, sign extend val. */
4570 if (!use_rela_relocations)
4571 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4572 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4573 }
4c63da97 4574#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4575 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4576 && exp_seg != absolute_section
47926f60 4577 && exp_seg != text_section
24eab124
AM		 4578 && exp_seg != data_section
4579 && exp_seg != bss_section
4580 && exp_seg != undefined_section
f86103b7 4581 && !bfd_is_com_section (exp_seg))
252b5132 4582 {
d0b47220 4583 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4584 return 0;
4585 }
4586#endif
bb8f5920
L		 4587 else if (!intel_syntax && exp->X_op == O_register)
4588 {
4589 as_bad (_("illegal immediate register operand %s"), imm_start);
4590 return 0;
4591 }
252b5132
RH		 4592 else
4593 {
4594 /* This is an address. The size of the address will be
24eab124 4595 determined later, depending on destination register,
3e73aa7c
JH		 4596 suffix, or the default for the section. */
4597 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4598 i.types[this_operand] &= types;
252b5132
RH		 4599 }
4600
4601 return 1;
4602}
4603
551c1ca1 4604static char *i386_scale PARAMS ((char *));
252b5132 4605
551c1ca1 4606static char *
252b5132
RH		 4607i386_scale (scale)
4608 char *scale;
4609{
551c1ca1
AM		 4610 offsetT val;
4611 char *save = input_line_pointer;
252b5132 4612
551c1ca1
AM		 4613 input_line_pointer = scale;
4614 val = get_absolute_expression ();
4615
4616 switch (val)
252b5132 4617 {
551c1ca1 4618 case 1:
252b5132
RH		 4619 i.log2_scale_factor = 0;
4620 break;
551c1ca1 4621 case 2:
252b5132
RH		 4622 i.log2_scale_factor = 1;
4623 break;
551c1ca1 4624 case 4:
252b5132
RH		 4625 i.log2_scale_factor = 2;
4626 break;
551c1ca1 4627 case 8:
252b5132
RH		 4628 i.log2_scale_factor = 3;
4629 break;
4630 default:
a724f0f4
JB		 4631 {
4632 char sep = *input_line_pointer;
4633
4634 *input_line_pointer = '\0';
4635 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4636 scale);
4637 *input_line_pointer = sep;
4638 input_line_pointer = save;
4639 return NULL;
4640 }
252b5132 4641 }
29b0f896 4642 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4643 {
4644 as_warn (_("scale factor of %d without an index register"),
24eab124 4645 1 << i.log2_scale_factor);
252b5132
RH		 4646#if SCALE1_WHEN_NO_INDEX
4647 i.log2_scale_factor = 0;
4648#endif
4649 }
551c1ca1
AM		 4650 scale = input_line_pointer;
4651 input_line_pointer = save;
4652 return scale;
252b5132
RH		 4653}
4654
4655static int i386_displacement PARAMS ((char *, char *));
4656
4657static int
4658i386_displacement (disp_start, disp_end)
4659 char *disp_start;
4660 char *disp_end;
4661{
29b0f896 4662 expressionS *exp;
252b5132
RH		 4663 segT exp_seg = 0;
4664 char *save_input_line_pointer;
f3c180ae 4665 char *gotfree_input_line;
e05278af 4666 int bigdisp, override;
3956db08 4667 unsigned int types = Disp;
252b5132 4668
31b2323c
L		 4669 if (i.disp_operands == MAX_MEMORY_OPERANDS)
4670 {
4671 as_bad (_("at most %d displacement operands are allowed"),
4672 MAX_MEMORY_OPERANDS);
4673 return 0;
4674 }
4675
e05278af
JB		 4676 if ((i.types[this_operand] & JumpAbsolute)
4677 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4678 {
4679 bigdisp = Disp32;
4680 override = (i.prefix[ADDR_PREFIX] != 0);
4681 }
4682 else
4683 {
4684 /* For PC-relative branches, the width of the displacement
4685 is dependent upon data size, not address size. */
4686 bigdisp = 0;
4687 override = (i.prefix[DATA_PREFIX] != 0);
4688 }
3e73aa7c 4689 if (flag_code == CODE_64BIT)
7ecd2f8b 4690 {
e05278af 4691 if (!bigdisp)
64e74474
AM		 4692 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4693 ? Disp16
4694 : Disp32S | Disp32);
e05278af 4695 else if (!override)
3956db08 4696 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4697 }
e05278af
JB		 4698 else
4699 {
4700 if (!bigdisp)
4701 {
4702 if (!override)
4703 override = (i.suffix == (flag_code != CODE_16BIT
4704 ? WORD_MNEM_SUFFIX
4705 : LONG_MNEM_SUFFIX));
4706 bigdisp = Disp32;
4707 }
4708 if ((flag_code == CODE_16BIT) ^ override)
4709 bigdisp = Disp16;
4710 }
252b5132
RH		 4711 i.types[this_operand] |= bigdisp;
4712
4713 exp = &disp_expressions[i.disp_operands];
520dc8e8 4714 i.op[this_operand].disps = exp;
252b5132
RH		 4715 i.disp_operands++;
4716 save_input_line_pointer = input_line_pointer;
4717 input_line_pointer = disp_start;
4718 END_STRING_AND_SAVE (disp_end);
4719
4720#ifndef GCC_ASM_O_HACK
4721#define GCC_ASM_O_HACK 0
4722#endif
4723#if GCC_ASM_O_HACK
4724 END_STRING_AND_SAVE (disp_end + 1);
4725 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4726 && displacement_string_end[-1] == '+')
252b5132
RH		 4727 {
4728 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4729 constraint within gcc asm statements.
4730 For instance:
4731
4732 #define _set_tssldt_desc(n,addr,limit,type) \
4733 __asm__ __volatile__ ( \
4734 "movw %w2,%0\n\t" \
4735 "movw %w1,2+%0\n\t" \
4736 "rorl $16,%1\n\t" \
4737 "movb %b1,4+%0\n\t" \
4738 "movb %4,5+%0\n\t" \
4739 "movb $0,6+%0\n\t" \
4740 "movb %h1,7+%0\n\t" \
4741 "rorl $16,%1" \
4742 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4743
4744 This works great except that the output assembler ends
4745 up looking a bit weird if it turns out that there is
4746 no offset. You end up producing code that looks like:
4747
4748 #APP
4749 movw $235,(%eax)
4750 movw %dx,2+(%eax)
4751 rorl $16,%edx
4752 movb %dl,4+(%eax)
4753 movb $137,5+(%eax)
4754 movb $0,6+(%eax)
4755 movb %dh,7+(%eax)
4756 rorl $16,%edx
4757 #NO_APP
4758
47926f60 4759 So here we provide the missing zero. */
24eab124
AM		 4760
4761 *displacement_string_end = '0';
252b5132
RH		 4762 }
4763#endif
3956db08 4764 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4765 if (gotfree_input_line)
4766 input_line_pointer = gotfree_input_line;
252b5132 4767
24eab124 4768 exp_seg = expression (exp);
252b5132 4769
636c26b0
AM		 4770 SKIP_WHITESPACE ();
4771 if (*input_line_pointer)
4772 as_bad (_("junk `%s' after expression"), input_line_pointer);
4773#if GCC_ASM_O_HACK
4774 RESTORE_END_STRING (disp_end + 1);
4775#endif
4776 RESTORE_END_STRING (disp_end);
4777 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4778 if (gotfree_input_line)
4779 free (gotfree_input_line);
636c26b0 4780
24eab124
AM		 4781 /* We do this to make sure that the section symbol is in
4782 the symbol table. We will ultimately change the relocation
47926f60 4783 to be relative to the beginning of the section. */
1ae12ab7 4784 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4785 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4786 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4787 {
636c26b0
AM		 4788 if (exp->X_op != O_symbol)
4789 {
4790 as_bad (_("bad expression used with @%s"),
4791 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4792 ? "GOTPCREL"
4793 : "GOTOFF"));
4794 return 0;
4795 }
4796
e5cb08ac 4797 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4798 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4799 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4800 exp->X_op = O_subtract;
4801 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4802 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4803 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4804 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4805 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4806 else
29b0f896 4807 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4808 }
252b5132 4809
2daf4fd8
AM		 4810 if (exp->X_op == O_absent || exp->X_op == O_big)
4811 {
47926f60 4812 /* Missing or bad expr becomes absolute 0. */
d0b47220 4813 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4814 disp_start);
4815 exp->X_op = O_constant;
4816 exp->X_add_number = 0;
4817 exp->X_add_symbol = (symbolS *) 0;
4818 exp->X_op_symbol = (symbolS *) 0;
4819 }
4820
4c63da97 4821#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4822 if (exp->X_op != O_constant
45288df1 4823 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4824 && exp_seg != absolute_section
45288df1
AM		 4825 && exp_seg != text_section
4826 && exp_seg != data_section
4827 && exp_seg != bss_section
31312f95 4828 && exp_seg != undefined_section
f86103b7 4829 && !bfd_is_com_section (exp_seg))
24eab124 4830 {
d0b47220 4831 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4832 return 0;
4833 }
252b5132 4834#endif
3956db08
JB		 4835
4836 if (!(i.types[this_operand] & ~Disp))
4837 i.types[this_operand] &= types;
4838
252b5132
RH		 4839 return 1;
4840}
4841
e5cb08ac 4842static int i386_index_check PARAMS ((const char *));
252b5132 4843
eecb386c 4844/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4845 Return 1 on success, 0 on a failure. */
4846
252b5132 4847static int
eecb386c
AM		 4848i386_index_check (operand_string)
4849 const char *operand_string;
252b5132 4850{
3e73aa7c 4851 int ok;
24eab124 4852#if INFER_ADDR_PREFIX
eecb386c
AM		 4853 int fudged = 0;
4854
24eab124
AM		 4855 tryprefix:
4856#endif
3e73aa7c 4857 ok = 1;
30123838
JB		 4858 if ((current_templates->start->cpu_flags & CpuSVME)
4859 && current_templates->end[-1].operand_types[0] == AnyMem)
4860 {
4861 /* Memory operands of SVME insns are special in that they only allow
4862 rAX as their memory address and ignore any segment override. */
4863 unsigned RegXX;
4864
4865 /* SKINIT is even more restrictive: it always requires EAX. */
4866 if (strcmp (current_templates->start->name, "skinit") == 0)
4867 RegXX = Reg32;
4868 else if (flag_code == CODE_64BIT)
4869 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4870 else
64e74474
AM		 4871 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4872 ? Reg16
4873 : Reg32);
30123838
JB		 4874 if (!i.base_reg
4875 || !(i.base_reg->reg_type & Acc)
4876 || !(i.base_reg->reg_type & RegXX)
4877 || i.index_reg
4878 || (i.types[0] & Disp))
4879 ok = 0;
4880 }
4881 else if (flag_code == CODE_64BIT)
64e74474
AM		 4882 {
4883 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4884
4885 if ((i.base_reg
4886 && ((i.base_reg->reg_type & RegXX) == 0)
4887 && (i.base_reg->reg_type != BaseIndex
4888 || i.index_reg))
4889 || (i.index_reg
4890 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4891 != (RegXX | BaseIndex))))
4892 ok = 0;
3e73aa7c
JH		 4893 }
4894 else
4895 {
4896 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4897 {
4898 /* 16bit checks. */
4899 if ((i.base_reg
29b0f896
AM		 4900 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4901 != (Reg16 | BaseIndex)))
3e73aa7c 4902 || (i.index_reg
29b0f896
AM		 4903 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4904 != (Reg16 | BaseIndex))
4905 || !(i.base_reg
4906 && i.base_reg->reg_num < 6
4907 && i.index_reg->reg_num >= 6
4908 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4909 ok = 0;
4910 }
4911 else
e5cb08ac 4912 {
3e73aa7c
JH		 4913 /* 32bit checks. */
4914 if ((i.base_reg
4915 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4916 || (i.index_reg
29b0f896
AM		 4917 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4918 != (Reg32 | BaseIndex))))
e5cb08ac 4919 ok = 0;
3e73aa7c
JH		 4920 }
4921 }
4922 if (!ok)
24eab124
AM		 4923 {
4924#if INFER_ADDR_PREFIX
20f0a1fc 4925 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4926 {
4927 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4928 i.prefixes += 1;
b23bac36
AM		 4929 /* Change the size of any displacement too. At most one of
4930 Disp16 or Disp32 is set.
4931 FIXME. There doesn't seem to be any real need for separate
4932 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4933 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4934 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 4935 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4936 fudged = 1;
24eab124
AM		 4937 goto tryprefix;
4938 }
eecb386c
AM		 4939 if (fudged)
4940 as_bad (_("`%s' is not a valid base/index expression"),
4941 operand_string);
4942 else
c388dee8 4943#endif
eecb386c
AM		 4944 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4945 operand_string,
3e73aa7c 4946 flag_code_names[flag_code]);
24eab124 4947 }
20f0a1fc 4948 return ok;
24eab124 4949}
252b5132 4950
252b5132 4951/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4952 on error. */
252b5132 4953
252b5132
RH		 4954static int
4955i386_operand (operand_string)
4956 char *operand_string;
4957{
af6bdddf
AM		 4958 const reg_entry *r;
4959 char *end_op;
24eab124 4960 char *op_string = operand_string;
252b5132 4961
24eab124 4962 if (is_space_char (*op_string))
252b5132
RH		 4963 ++op_string;
4964
24eab124 4965 /* We check for an absolute prefix (differentiating,
47926f60 4966 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4967 if (*op_string == ABSOLUTE_PREFIX)
4968 {
4969 ++op_string;
4970 if (is_space_char (*op_string))
4971 ++op_string;
4972 i.types[this_operand] |= JumpAbsolute;
4973 }
252b5132 4974
47926f60 4975 /* Check if operand is a register. */
4d1bb795 4976 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 4977 {
24eab124
AM		 4978 /* Check for a segment override by searching for ':' after a
4979 segment register. */
4980 op_string = end_op;
4981 if (is_space_char (*op_string))
4982 ++op_string;
4983 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4984 {
4985 switch (r->reg_num)
4986 {
4987 case 0:
4988 i.seg[i.mem_operands] = &es;
4989 break;
4990 case 1:
4991 i.seg[i.mem_operands] = &cs;
4992 break;
4993 case 2:
4994 i.seg[i.mem_operands] = &ss;
4995 break;
4996 case 3:
4997 i.seg[i.mem_operands] = &ds;
4998 break;
4999 case 4:
5000 i.seg[i.mem_operands] = &fs;
5001 break;
5002 case 5:
5003 i.seg[i.mem_operands] = &gs;
5004 break;
5005 }
252b5132 5006
24eab124 5007 /* Skip the ':' and whitespace. */
252b5132
RH		 5008 ++op_string;
5009 if (is_space_char (*op_string))
24eab124 5010 ++op_string;
252b5132 5011
24eab124
AM		 5012 if (!is_digit_char (*op_string)
5013 && !is_identifier_char (*op_string)
5014 && *op_string != '('
5015 && *op_string != ABSOLUTE_PREFIX)
5016 {
5017 as_bad (_("bad memory operand `%s'"), op_string);
5018 return 0;
5019 }
47926f60 5020 /* Handle case of %es:*foo. */
24eab124
AM		 5021 if (*op_string == ABSOLUTE_PREFIX)
5022 {
5023 ++op_string;
5024 if (is_space_char (*op_string))
5025 ++op_string;
5026 i.types[this_operand] |= JumpAbsolute;
5027 }
5028 goto do_memory_reference;
5029 }
5030 if (*op_string)
5031 {
d0b47220 5032 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 5033 return 0;
5034 }
5035 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 5036 i.op[this_operand].regs = r;
24eab124
AM		 5037 i.reg_operands++;
5038 }
af6bdddf
AM		 5039 else if (*op_string == REGISTER_PREFIX)
5040 {
5041 as_bad (_("bad register name `%s'"), op_string);
5042 return 0;
5043 }
24eab124 5044 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 5045 {
24eab124
AM		 5046 ++op_string;
5047 if (i.types[this_operand] & JumpAbsolute)
5048 {
d0b47220 5049 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 5050 return 0;
5051 }
5052 if (!i386_immediate (op_string))
5053 return 0;
5054 }
5055 else if (is_digit_char (*op_string)
5056 || is_identifier_char (*op_string)
e5cb08ac 5057 || *op_string == '(')
24eab124 5058 {
47926f60 5059 /* This is a memory reference of some sort. */
af6bdddf 5060 char *base_string;
252b5132 5061
47926f60 5062 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 5063 char *displacement_string_start;
5064 char *displacement_string_end;
252b5132 5065
24eab124 5066 do_memory_reference:
24eab124
AM		 5067 if ((i.mem_operands == 1
5068 && (current_templates->start->opcode_modifier & IsString) == 0)
5069 || i.mem_operands == 2)
5070 {
5071 as_bad (_("too many memory references for `%s'"),
5072 current_templates->start->name);
5073 return 0;
5074 }
252b5132 5075
24eab124
AM		 5076 /* Check for base index form. We detect the base index form by
5077 looking for an ')' at the end of the operand, searching
5078 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5079 after the '('. */
af6bdddf 5080 base_string = op_string + strlen (op_string);
c3332e24 5081
af6bdddf
AM		 5082 --base_string;
5083 if (is_space_char (*base_string))
5084 --base_string;
252b5132 5085
47926f60 5086 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 5087 displacement_string_start = op_string;
5088 displacement_string_end = base_string + 1;
252b5132 5089
24eab124
AM		 5090 if (*base_string == ')')
5091 {
af6bdddf 5092 char *temp_string;
24eab124
AM		 5093 unsigned int parens_balanced = 1;
5094 /* We've already checked that the number of left & right ()'s are
47926f60 5095 equal, so this loop will not be infinite. */
24eab124
AM		 5096 do
5097 {
5098 base_string--;
5099 if (*base_string == ')')
5100 parens_balanced++;
5101 if (*base_string == '(')
5102 parens_balanced--;
5103 }
5104 while (parens_balanced);
c3332e24 5105
af6bdddf 5106 temp_string = base_string;
c3332e24 5107
24eab124 5108 /* Skip past '(' and whitespace. */
252b5132
RH		 5109 ++base_string;
5110 if (is_space_char (*base_string))
24eab124 5111 ++base_string;
252b5132 5112
af6bdddf 5113 if (*base_string == ','
4d1bb795 5114 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 5115 {
af6bdddf 5116 displacement_string_end = temp_string;
252b5132 5117
af6bdddf 5118 i.types[this_operand] |= BaseIndex;
252b5132 5119
af6bdddf 5120 if (i.base_reg)
24eab124 5121 {
24eab124
AM		 5122 base_string = end_op;
5123 if (is_space_char (*base_string))
5124 ++base_string;
af6bdddf
AM		 5125 }
5126
5127 /* There may be an index reg or scale factor here. */
5128 if (*base_string == ',')
5129 {
5130 ++base_string;
5131 if (is_space_char (*base_string))
5132 ++base_string;
5133
4d1bb795 5134 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 5135 {
af6bdddf 5136 base_string = end_op;
24eab124
AM		 5137 if (is_space_char (*base_string))
5138 ++base_string;
af6bdddf
AM		 5139 if (*base_string == ',')
5140 {
5141 ++base_string;
5142 if (is_space_char (*base_string))
5143 ++base_string;
5144 }
e5cb08ac 5145 else if (*base_string != ')')
af6bdddf
AM		 5146 {
5147 as_bad (_("expecting `,' or `)' after index register in `%s'"),
5148 operand_string);
5149 return 0;
5150 }
24eab124 5151 }
af6bdddf 5152 else if (*base_string == REGISTER_PREFIX)
24eab124 5153 {
af6bdddf 5154 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5155 return 0;
5156 }
252b5132 5157
47926f60 5158 /* Check for scale factor. */
551c1ca1 5159 if (*base_string != ')')
af6bdddf 5160 {
551c1ca1
AM		 5161 char *end_scale = i386_scale (base_string);
5162
5163 if (!end_scale)
af6bdddf 5164 return 0;
24eab124 5165
551c1ca1 5166 base_string = end_scale;
af6bdddf
AM		 5167 if (is_space_char (*base_string))
5168 ++base_string;
5169 if (*base_string != ')')
5170 {
5171 as_bad (_("expecting `)' after scale factor in `%s'"),
5172 operand_string);
5173 return 0;
5174 }
5175 }
5176 else if (!i.index_reg)
24eab124 5177 {
af6bdddf
AM		 5178 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
5179 *base_string);
24eab124
AM		 5180 return 0;
5181 }
5182 }
af6bdddf 5183 else if (*base_string != ')')
24eab124 5184 {
af6bdddf
AM		 5185 as_bad (_("expecting `,' or `)' after base register in `%s'"),
5186 operand_string);
24eab124
AM		 5187 return 0;
5188 }
c3332e24 5189 }
af6bdddf 5190 else if (*base_string == REGISTER_PREFIX)
c3332e24 5191 {
af6bdddf 5192 as_bad (_("bad register name `%s'"), base_string);
24eab124 5193 return 0;
c3332e24 5194 }
24eab124
AM		 5195 }
5196
5197 /* If there's an expression beginning the operand, parse it,
5198 assuming displacement_string_start and
5199 displacement_string_end are meaningful. */
5200 if (displacement_string_start != displacement_string_end)
5201 {
5202 if (!i386_displacement (displacement_string_start,
5203 displacement_string_end))
5204 return 0;
5205 }
5206
5207 /* Special case for (%dx) while doing input/output op. */
5208 if (i.base_reg
5209 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5210 && i.index_reg == 0
5211 && i.log2_scale_factor == 0
5212 && i.seg[i.mem_operands] == 0
5213 && (i.types[this_operand] & Disp) == 0)
5214 {
5215 i.types[this_operand] = InOutPortReg;
5216 return 1;
5217 }
5218
eecb386c
AM		 5219 if (i386_index_check (operand_string) == 0)
5220 return 0;
24eab124
AM		 5221 i.mem_operands++;
5222 }
5223 else
ce8a8b2f
AM		 5224 {
5225 /* It's not a memory operand; argh! */
24eab124
AM		 5226 as_bad (_("invalid char %s beginning operand %d `%s'"),
5227 output_invalid (*op_string),
5228 this_operand + 1,
5229 op_string);
5230 return 0;
5231 }
47926f60 5232 return 1; /* Normal return. */
252b5132
RH		 5233}
5234\f
ee7fcc42
AM		 5235/* md_estimate_size_before_relax()
5236
5237 Called just before relax() for rs_machine_dependent frags. The x86
5238 assembler uses these frags to handle variable size jump
5239 instructions.
5240
5241 Any symbol that is now undefined will not become defined.
5242 Return the correct fr_subtype in the frag.
5243 Return the initial "guess for variable size of frag" to caller.
5244 The guess is actually the growth beyond the fixed part. Whatever
5245 we do to grow the fixed or variable part contributes to our
5246 returned value. */
5247
252b5132
RH		 5248int
5249md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5250 fragS *fragP;
5251 segT segment;
252b5132 5252{
252b5132 5253 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5254 check for un-relaxable symbols. On an ELF system, we can't relax
5255 an externally visible symbol, because it may be overridden by a
5256 shared library. */
5257 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5258#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5259 || (IS_ELF
31312f95
AM		 5260 && (S_IS_EXTERNAL (fragP->fr_symbol)
5261 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5262#endif
5263 )
252b5132 5264 {
b98ef147
AM		 5265 /* Symbol is undefined in this segment, or we need to keep a
5266 reloc so that weak symbols can be overridden. */
5267 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5268 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5269 unsigned char *opcode;
5270 int old_fr_fix;
f6af82bd 5271
ee7fcc42
AM		 5272 if (fragP->fr_var != NO_RELOC)
5273 reloc_type = fragP->fr_var;
b98ef147 5274 else if (size == 2)
f6af82bd
AM		 5275 reloc_type = BFD_RELOC_16_PCREL;
5276 else
5277 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5278
ee7fcc42
AM		 5279 old_fr_fix = fragP->fr_fix;
5280 opcode = (unsigned char *) fragP->fr_opcode;
5281
fddf5b5b 5282 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5283 {
fddf5b5b
AM		 5284 case UNCOND_JUMP:
5285 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5286 opcode[0] = 0xe9;
252b5132 5287 fragP->fr_fix += size;
062cd5e7
AS		 5288 fix_new (fragP, old_fr_fix, size,
5289 fragP->fr_symbol,
5290 fragP->fr_offset, 1,
5291 reloc_type);
252b5132
RH		 5292 break;
5293
fddf5b5b 5294 case COND_JUMP86:
412167cb
AM		 5295 if (size == 2
5296 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5297 {
5298 /* Negate the condition, and branch past an
5299 unconditional jump. */
5300 opcode[0] ^= 1;
5301 opcode[1] = 3;
5302 /* Insert an unconditional jump. */
5303 opcode[2] = 0xe9;
5304 /* We added two extra opcode bytes, and have a two byte
5305 offset. */
5306 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5307 fix_new (fragP, old_fr_fix + 2, 2,
5308 fragP->fr_symbol,
5309 fragP->fr_offset, 1,
5310 reloc_type);
fddf5b5b
AM		 5311 break;
5312 }
5313 /* Fall through. */
5314
5315 case COND_JUMP:
412167cb
AM		 5316 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5317 {
3e02c1cc
AM		 5318 fixS *fixP;
5319
412167cb 5320 fragP->fr_fix += 1;
3e02c1cc
AM		 5321 fixP = fix_new (fragP, old_fr_fix, 1,
5322 fragP->fr_symbol,
5323 fragP->fr_offset, 1,
5324 BFD_RELOC_8_PCREL);
5325 fixP->fx_signed = 1;
412167cb
AM		 5326 break;
5327 }
93c2a809 5328
24eab124 5329 /* This changes the byte-displacement jump 0x7N
fddf5b5b 5330 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 5331 opcode[1] = opcode[0] + 0x10;
f6af82bd 5332 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 5333 /* We've added an opcode byte. */
5334 fragP->fr_fix += 1 + size;
062cd5e7
AS		 5335 fix_new (fragP, old_fr_fix + 1, size,
5336 fragP->fr_symbol,
5337 fragP->fr_offset, 1,
5338 reloc_type);
252b5132 5339 break;
fddf5b5b
AM		 5340
5341 default:
5342 BAD_CASE (fragP->fr_subtype);
5343 break;
252b5132
RH		 5344 }
5345 frag_wane (fragP);
ee7fcc42 5346 return fragP->fr_fix - old_fr_fix;
252b5132 5347 }
93c2a809 5348
93c2a809
AM		 5349 /* Guess size depending on current relax state. Initially the relax
5350 state will correspond to a short jump and we return 1, because
5351 the variable part of the frag (the branch offset) is one byte
5352 long. However, we can relax a section more than once and in that
5353 case we must either set fr_subtype back to the unrelaxed state,
5354 or return the value for the appropriate branch. */
5355 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 5356}
5357
47926f60
KH		 5358/* Called after relax() is finished.
5359
5360 In: Address of frag.
5361 fr_type == rs_machine_dependent.
5362 fr_subtype is what the address relaxed to.
5363
5364 Out: Any fixSs and constants are set up.
5365 Caller will turn frag into a ".space 0". */
5366
252b5132
RH		 5367void
5368md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 5369 bfd *abfd ATTRIBUTE_UNUSED;
5370 segT sec ATTRIBUTE_UNUSED;
29b0f896 5371 fragS *fragP;
252b5132 5372{
29b0f896 5373 unsigned char *opcode;
252b5132 5374 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 5375 offsetT target_address;
5376 offsetT opcode_address;
252b5132 5377 unsigned int extension = 0;
847f7ad4 5378 offsetT displacement_from_opcode_start;
252b5132
RH		 5379
5380 opcode = (unsigned char *) fragP->fr_opcode;
5381
47926f60 5382 /* Address we want to reach in file space. */
252b5132 5383 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 5384
47926f60 5385 /* Address opcode resides at in file space. */
252b5132
RH		 5386 opcode_address = fragP->fr_address + fragP->fr_fix;
5387
47926f60 5388 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 5389 displacement_from_opcode_start = target_address - opcode_address;
5390
fddf5b5b 5391 if ((fragP->fr_subtype & BIG) == 0)
252b5132 5392 {
47926f60
KH		 5393 /* Don't have to change opcode. */
5394 extension = 1; /* 1 opcode + 1 displacement */
252b5132 5395 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 5396 }
5397 else
5398 {
5399 if (no_cond_jump_promotion
5400 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
5401 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 5402
fddf5b5b
AM		 5403 switch (fragP->fr_subtype)
5404 {
5405 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5406 extension = 4; /* 1 opcode + 4 displacement */
5407 opcode[0] = 0xe9;
5408 where_to_put_displacement = &opcode[1];
5409 break;
252b5132 5410
fddf5b5b
AM		 5411 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5412 extension = 2; /* 1 opcode + 2 displacement */
5413 opcode[0] = 0xe9;
5414 where_to_put_displacement = &opcode[1];
5415 break;
252b5132 5416
fddf5b5b
AM		 5417 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5418 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5419 extension = 5; /* 2 opcode + 4 displacement */
5420 opcode[1] = opcode[0] + 0x10;
5421 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5422 where_to_put_displacement = &opcode[2];
5423 break;
252b5132 5424
fddf5b5b
AM		 5425 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5426 extension = 3; /* 2 opcode + 2 displacement */
5427 opcode[1] = opcode[0] + 0x10;
5428 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5429 where_to_put_displacement = &opcode[2];
5430 break;
252b5132 5431
fddf5b5b
AM		 5432 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5433 extension = 4;
5434 opcode[0] ^= 1;
5435 opcode[1] = 3;
5436 opcode[2] = 0xe9;
5437 where_to_put_displacement = &opcode[3];
5438 break;
5439
5440 default:
5441 BAD_CASE (fragP->fr_subtype);
5442 break;
5443 }
252b5132 5444 }
fddf5b5b 5445
7b81dfbb
AJ		 5446 /* If size if less then four we are sure that the operand fits,
5447 but if it's 4, then it could be that the displacement is larger
5448 then -/+ 2GB. */
5449 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5450 && object_64bit
5451 && ((addressT) (displacement_from_opcode_start - extension
5452 + ((addressT) 1 << 31))
5453 > (((addressT) 2 << 31) - 1)))
5454 {
5455 as_bad_where (fragP->fr_file, fragP->fr_line,
5456 _("jump target out of range"));
5457 /* Make us emit 0. */
5458 displacement_from_opcode_start = extension;
5459 }
47926f60 5460 /* Now put displacement after opcode. */
252b5132
RH		 5461 md_number_to_chars ((char *) where_to_put_displacement,
5462 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5463 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5464 fragP->fr_fix += extension;
5465}
5466\f
47926f60
KH		 5467/* Size of byte displacement jmp. */
5468int md_short_jump_size = 2;
5469
5470/* Size of dword displacement jmp. */
5471int md_long_jump_size = 5;
252b5132 5472
252b5132
RH		 5473void
5474md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5475 char *ptr;
5476 addressT from_addr, to_addr;
ab9da554
ILT		 5477 fragS *frag ATTRIBUTE_UNUSED;
5478 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5479{
847f7ad4 5480 offsetT offset;
252b5132
RH		 5481
5482 offset = to_addr - (from_addr + 2);
47926f60
KH		 5483 /* Opcode for byte-disp jump. */
5484 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5485 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5486}
5487
5488void
5489md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5490 char *ptr;
5491 addressT from_addr, to_addr;
a38cf1db
AM		 5492 fragS *frag ATTRIBUTE_UNUSED;
5493 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5494{
847f7ad4 5495 offsetT offset;
252b5132 5496
a38cf1db
AM		 5497 offset = to_addr - (from_addr + 5);
5498 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5499 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5500}
5501\f
5502/* Apply a fixup (fixS) to segment data, once it has been determined
5503 by our caller that we have all the info we need to fix it up.
5504
5505 On the 386, immediates, displacements, and data pointers are all in
5506 the same (little-endian) format, so we don't need to care about which
5507 we are handling. */
5508
94f592af 5509void
55cf6793 5510md_apply_fix (fixP, valP, seg)
47926f60
KH		 5511 /* The fix we're to put in. */
5512 fixS *fixP;
47926f60 5513 /* Pointer to the value of the bits. */
c6682705 5514 valueT *valP;
47926f60
KH		 5515 /* Segment fix is from. */
5516 segT seg ATTRIBUTE_UNUSED;
252b5132 5517{
94f592af 5518 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5519 valueT value = *valP;
252b5132 5520
f86103b7 5521#if !defined (TE_Mach)
93382f6d
AM		 5522 if (fixP->fx_pcrel)
5523 {
5524 switch (fixP->fx_r_type)
5525 {
5865bb77
ILT		 5526 default:
5527 break;
5528
d6ab8113
JB		 5529 case BFD_RELOC_64:
5530 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5531 break;
93382f6d 5532 case BFD_RELOC_32:
ae8887b5 5533 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5534 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5535 break;
5536 case BFD_RELOC_16:
5537 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5538 break;
5539 case BFD_RELOC_8:
5540 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5541 break;
5542 }
5543 }
252b5132 5544
a161fe53 5545 if (fixP->fx_addsy != NULL
31312f95 5546 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5547 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5548 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5549 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5550 && !use_rela_relocations)
252b5132 5551 {
31312f95
AM		 5552 /* This is a hack. There should be a better way to handle this.
5553 This covers for the fact that bfd_install_relocation will
5554 subtract the current location (for partial_inplace, PC relative
5555 relocations); see more below. */
252b5132 5556#ifndef OBJ_AOUT
718ddfc0 5557 if (IS_ELF
252b5132
RH		 5558#ifdef TE_PE
5559 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5560#endif
5561 )
5562 value += fixP->fx_where + fixP->fx_frag->fr_address;
5563#endif
5564#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5565 if (IS_ELF)
252b5132 5566 {
6539b54b 5567 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5568
6539b54b 5569 if ((sym_seg == seg
2f66722d 5570 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5571 && sym_seg != absolute_section))
ae6063d4 5572 && !generic_force_reloc (fixP))
2f66722d
AM		 5573 {
5574 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5575 bfd_install_relocation subtracts them out again. I think
5576 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5577 it. FIXME. */
5578 value += fixP->fx_where + fixP->fx_frag->fr_address;
5579 }
252b5132
RH		 5580 }
5581#endif
5582#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5583 /* For some reason, the PE format does not store a
5584 section address offset for a PC relative symbol. */
5585 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5586 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5587 value += md_pcrel_from (fixP);
5588#endif
5589 }
5590
5591 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5592 and we must not disappoint it. */
252b5132 5593#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5594 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5595 switch (fixP->fx_r_type)
5596 {
5597 case BFD_RELOC_386_PLT32:
3e73aa7c 5598 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5599 /* Make the jump instruction point to the address of the operand. At
5600 runtime we merely add the offset to the actual PLT entry. */
5601 value = -4;
5602 break;
31312f95 5603
13ae64f3
JJ		 5604 case BFD_RELOC_386_TLS_GD:
5605 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5606 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5607 case BFD_RELOC_386_TLS_IE:
5608 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5609 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5610 case BFD_RELOC_X86_64_TLSGD:
5611 case BFD_RELOC_X86_64_TLSLD:
5612 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5613 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5614 value = 0; /* Fully resolved at runtime. No addend. */
5615 /* Fallthrough */
5616 case BFD_RELOC_386_TLS_LE:
5617 case BFD_RELOC_386_TLS_LDO_32:
5618 case BFD_RELOC_386_TLS_LE_32:
5619 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5620 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5621 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5622 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5623 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5624 break;
5625
67a4f2b7
AO		 5626 case BFD_RELOC_386_TLS_DESC_CALL:
5627 case BFD_RELOC_X86_64_TLSDESC_CALL:
5628 value = 0; /* Fully resolved at runtime. No addend. */
5629 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5630 fixP->fx_done = 0;
5631 return;
5632
00f7efb6
JJ		 5633 case BFD_RELOC_386_GOT32:
5634 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5635 value = 0; /* Fully resolved at runtime. No addend. */
5636 break;
47926f60
KH		 5637
5638 case BFD_RELOC_VTABLE_INHERIT:
5639 case BFD_RELOC_VTABLE_ENTRY:
5640 fixP->fx_done = 0;
94f592af 5641 return;
47926f60
KH		 5642
5643 default:
5644 break;
5645 }
5646#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5647 *valP = value;
f86103b7 5648#endif /* !defined (TE_Mach) */
3e73aa7c 5649
3e73aa7c 5650 /* Are we finished with this relocation now? */
c6682705 5651 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5652 fixP->fx_done = 1;
5653 else if (use_rela_relocations)
5654 {
5655 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5656 /* Remember value for tc_gen_reloc. */
5657 fixP->fx_addnumber = value;
3e73aa7c
JH		 5658 value = 0;
5659 }
f86103b7 5660
94f592af 5661 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5662}
252b5132 5663\f
252b5132
RH		 5664#define MAX_LITTLENUMS 6
5665
47926f60
KH		 5666/* Turn the string pointed to by litP into a floating point constant
5667 of type TYPE, and emit the appropriate bytes. The number of
5668 LITTLENUMS emitted is stored in *SIZEP. An error message is
5669 returned, or NULL on OK. */
5670
252b5132
RH		 5671char *
5672md_atof (type, litP, sizeP)
2ab9b79e 5673 int type;
252b5132
RH		 5674 char *litP;
5675 int *sizeP;
5676{
5677 int prec;
5678 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5679 LITTLENUM_TYPE *wordP;
5680 char *t;
5681
5682 switch (type)
5683 {
5684 case 'f':
5685 case 'F':
5686 prec = 2;
5687 break;
5688
5689 case 'd':
5690 case 'D':
5691 prec = 4;
5692 break;
5693
5694 case 'x':
5695 case 'X':
5696 prec = 5;
5697 break;
5698
5699 default:
5700 *sizeP = 0;
5701 return _("Bad call to md_atof ()");
5702 }
5703 t = atof_ieee (input_line_pointer, type, words);
5704 if (t)
5705 input_line_pointer = t;
5706
5707 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5708 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5709 the bigendian 386. */
5710 for (wordP = words + prec - 1; prec--;)
5711 {
5712 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5713 litP += sizeof (LITTLENUM_TYPE);
5714 }
5715 return 0;
5716}
5717\f
2d545b82 5718static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5719
252b5132
RH		 5720static char *
5721output_invalid (c)
5722 int c;
5723{
3882b010 5724 if (ISPRINT (c))
f9f21a03
L		 5725 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5726 "'%c'", c);
252b5132 5727 else
f9f21a03 5728 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5729 "(0x%x)", (unsigned char) c);
252b5132
RH		 5730 return output_invalid_buf;
5731}
5732
af6bdddf 5733/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5734
5735static const reg_entry *
4d1bb795 5736parse_real_register (char *reg_string, char **end_op)
252b5132 5737{
af6bdddf
AM		 5738 char *s = reg_string;
5739 char *p;
252b5132
RH		 5740 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5741 const reg_entry *r;
5742
5743 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5744 if (*s == REGISTER_PREFIX)
5745 ++s;
5746
5747 if (is_space_char (*s))
5748 ++s;
5749
5750 p = reg_name_given;
af6bdddf 5751 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5752 {
5753 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5754 return (const reg_entry *) NULL;
5755 s++;
252b5132
RH		 5756 }
5757
6588847e
DN		 5758 /* For naked regs, make sure that we are not dealing with an identifier.
5759 This prevents confusing an identifier like `eax_var' with register
5760 `eax'. */
5761 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5762 return (const reg_entry *) NULL;
5763
af6bdddf 5764 *end_op = s;
252b5132
RH		 5765
5766 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5767
5f47d35b 5768 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5769 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5770 {
5f47d35b
AM		 5771 if (is_space_char (*s))
5772 ++s;
5773 if (*s == '(')
5774 {
af6bdddf 5775 ++s;
5f47d35b
AM		 5776 if (is_space_char (*s))
5777 ++s;
5778 if (*s >= '0' && *s <= '7')
5779 {
5780 r = &i386_float_regtab[*s - '0'];
af6bdddf 5781 ++s;
5f47d35b
AM		 5782 if (is_space_char (*s))
5783 ++s;
5784 if (*s == ')')
5785 {
5786 *end_op = s + 1;
5787 return r;
5788 }
5f47d35b 5789 }
47926f60 5790 /* We have "%st(" then garbage. */
5f47d35b
AM		 5791 return (const reg_entry *) NULL;
5792 }
5793 }
5794
1ae00879 5795 if (r != NULL
20f0a1fc 5796 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5797 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5798 && flag_code != CODE_64BIT)
20f0a1fc 5799 return (const reg_entry *) NULL;
1ae00879 5800
252b5132
RH		 5801 return r;
5802}
4d1bb795
JB		 5803
5804/* REG_STRING starts *before* REGISTER_PREFIX. */
5805
5806static const reg_entry *
5807parse_register (char *reg_string, char **end_op)
5808{
5809 const reg_entry *r;
5810
5811 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5812 r = parse_real_register (reg_string, end_op);
5813 else
5814 r = NULL;
5815 if (!r)
5816 {
5817 char *save = input_line_pointer;
5818 char c;
5819 symbolS *symbolP;
5820
5821 input_line_pointer = reg_string;
5822 c = get_symbol_end ();
5823 symbolP = symbol_find (reg_string);
5824 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5825 {
5826 const expressionS *e = symbol_get_value_expression (symbolP);
5827
5828 know (e->X_op == O_register);
5829 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5830 r = i386_regtab + e->X_add_number;
5831 *end_op = input_line_pointer;
5832 }
5833 *input_line_pointer = c;
5834 input_line_pointer = save;
5835 }
5836 return r;
5837}
5838
5839int
5840i386_parse_name (char *name, expressionS *e, char *nextcharP)
5841{
5842 const reg_entry *r;
5843 char *end = input_line_pointer;
5844
5845 *end = *nextcharP;
5846 r = parse_register (name, &input_line_pointer);
5847 if (r && end <= input_line_pointer)
5848 {
5849 *nextcharP = *input_line_pointer;
5850 *input_line_pointer = 0;
5851 e->X_op = O_register;
5852 e->X_add_number = r - i386_regtab;
5853 return 1;
5854 }
5855 input_line_pointer = end;
5856 *end = 0;
5857 return 0;
5858}
5859
5860void
5861md_operand (expressionS *e)
5862{
5863 if (*input_line_pointer == REGISTER_PREFIX)
5864 {
5865 char *end;
5866 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5867
5868 if (r)
5869 {
5870 e->X_op = O_register;
5871 e->X_add_number = r - i386_regtab;
5872 input_line_pointer = end;
5873 }
5874 }
5875}
5876
252b5132 5877\f
4cc782b5 5878#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5879const char *md_shortopts = "kVQ:sqn";
252b5132 5880#else
12b55ccc 5881const char *md_shortopts = "qn";
252b5132 5882#endif
6e0b89ee 5883
3e73aa7c 5884#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5885#define OPTION_64 (OPTION_MD_BASE + 1)
5886#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 5887#define OPTION_MARCH (OPTION_MD_BASE + 3)
5888#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 5889
99ad8390
NC		 5890struct option md_longopts[] =
5891{
3e73aa7c 5892 {"32", no_argument, NULL, OPTION_32},
99ad8390 5893#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 5894 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5895#endif
b3b91714 5896 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 5897 {"march", required_argument, NULL, OPTION_MARCH},
5898 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 5899 {NULL, no_argument, NULL, 0}
5900};
5901size_t md_longopts_size = sizeof (md_longopts);
5902
5903int
9103f4f4 5904md_parse_option (int c, char *arg)
252b5132 5905{
9103f4f4
L		 5906 unsigned int i;
5907
252b5132
RH		 5908 switch (c)
5909 {
12b55ccc
L		 5910 case 'n':
5911 optimize_align_code = 0;
5912 break;
5913
a38cf1db
AM		 5914 case 'q':
5915 quiet_warnings = 1;
252b5132
RH		 5916 break;
5917
5918#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5919 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5920 should be emitted or not. FIXME: Not implemented. */
5921 case 'Q':
252b5132
RH		 5922 break;
5923
5924 /* -V: SVR4 argument to print version ID. */
5925 case 'V':
5926 print_version_id ();
5927 break;
5928
a38cf1db
AM		 5929 /* -k: Ignore for FreeBSD compatibility. */
5930 case 'k':
252b5132 5931 break;
4cc782b5
ILT		 5932
5933 case 's':
5934 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5935 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5936 break;
99ad8390
NC		 5937#endif
5938#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 5939 case OPTION_64:
5940 {
5941 const char **list, **l;
5942
3e73aa7c
JH		 5943 list = bfd_target_list ();
5944 for (l = list; *l != NULL; l++)
8620418b 5945 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 5946 || strcmp (*l, "coff-x86-64") == 0
5947 || strcmp (*l, "pe-x86-64") == 0
5948 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 5949 {
5950 default_arch = "x86_64";
5951 break;
5952 }
3e73aa7c 5953 if (*l == NULL)
6e0b89ee 5954 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5955 free (list);
5956 }
5957 break;
5958#endif
252b5132 5959
6e0b89ee
AM		 5960 case OPTION_32:
5961 default_arch = "i386";
5962 break;
5963
b3b91714
AM		 5964 case OPTION_DIVIDE:
5965#ifdef SVR4_COMMENT_CHARS
5966 {
5967 char *n, *t;
5968 const char *s;
5969
5970 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5971 t = n;
5972 for (s = i386_comment_chars; *s != '\0'; s++)
5973 if (*s != '/')
5974 *t++ = *s;
5975 *t = '\0';
5976 i386_comment_chars = n;
5977 }
5978#endif
5979 break;
5980
9103f4f4
L		 5981 case OPTION_MARCH:
5982 if (*arg == '.')
5983 as_fatal (_("Invalid -march= option: `%s'"), arg);
5984 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5985 {
5986 if (strcmp (arg, cpu_arch [i].name) == 0)
5987 {
ccc9c027 5988 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 5989 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 5990 if (!cpu_arch_tune_set)
5991 {
5992 cpu_arch_tune = cpu_arch_isa;
5993 cpu_arch_tune_flags = cpu_arch_isa_flags;
5994 }
9103f4f4
L		 5995 break;
5996 }
5997 }
5998 if (i >= ARRAY_SIZE (cpu_arch))
5999 as_fatal (_("Invalid -march= option: `%s'"), arg);
6000 break;
6001
6002 case OPTION_MTUNE:
6003 if (*arg == '.')
6004 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6005 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
6006 {
6007 if (strcmp (arg, cpu_arch [i].name) == 0)
6008 {
ccc9c027 6009 cpu_arch_tune_set = 1;
9103f4f4
L		 6010 cpu_arch_tune = cpu_arch [i].type;
6011 cpu_arch_tune_flags = cpu_arch[i].flags;
6012 break;
6013 }
6014 }
6015 if (i >= ARRAY_SIZE (cpu_arch))
6016 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6017 break;
6018
252b5132
RH		 6019 default:
6020 return 0;
6021 }
6022 return 1;
6023}
6024
6025void
6026md_show_usage (stream)
6027 FILE *stream;
6028{
4cc782b5
ILT		 6029#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6030 fprintf (stream, _("\
a38cf1db
AM		 6031 -Q ignored\n\
6032 -V print assembler version number\n\
b3b91714
AM		 6033 -k ignored\n"));
6034#endif
6035 fprintf (stream, _("\
12b55ccc 6036 -n Do not optimize code alignment\n\
b3b91714
AM		 6037 -q quieten some warnings\n"));
6038#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6039 fprintf (stream, _("\
a38cf1db 6040 -s ignored\n"));
b3b91714
AM		 6041#endif
6042#ifdef SVR4_COMMENT_CHARS
6043 fprintf (stream, _("\
6044 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 6045#else
6046 fprintf (stream, _("\
b3b91714 6047 --divide ignored\n"));
4cc782b5 6048#endif
9103f4f4
L		 6049 fprintf (stream, _("\
6050 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6051 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
ef05d495 6052 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 6053
252b5132
RH		 6054}
6055
99ad8390
NC		 6056#if defined(TE_PEP)
6057const char *
6058x86_64_target_format (void)
6059{
6060 if (strcmp (default_arch, "x86_64") == 0)
6061 {
6062 set_code_flag (CODE_64BIT);
6063 return COFF_TARGET_FORMAT;
6064 }
6065 else if (strcmp (default_arch, "i386") == 0)
6066 {
6067 set_code_flag (CODE_32BIT);
6068 return "coff-i386";
6069 }
6070
6071 as_fatal (_("Unknown architecture"));
6072 return NULL;
6073}
6074#endif
6075
3e73aa7c
JH		 6076#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6077 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 6078
6079/* Pick the target format to use. */
6080
47926f60 6081const char *
252b5132
RH		 6082i386_target_format ()
6083{
3e73aa7c 6084 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 6085 {
6086 set_code_flag (CODE_64BIT);
6087 if (cpu_arch_isa_flags == 0)
d32cad65 6088 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
9103f4f4
L		 6089 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6090 |CpuSSE|CpuSSE2;
ccc9c027 6091 if (cpu_arch_tune_flags == 0)
d32cad65 6092 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
ccc9c027
L		 6093 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6094 |CpuSSE|CpuSSE2;
9103f4f4 6095 }
3e73aa7c 6096 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 6097 {
6098 set_code_flag (CODE_32BIT);
6099 if (cpu_arch_isa_flags == 0)
d32cad65 6100 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
ccc9c027 6101 if (cpu_arch_tune_flags == 0)
d32cad65 6102 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
9103f4f4 6103 }
3e73aa7c
JH		 6104 else
6105 as_fatal (_("Unknown architecture"));
252b5132
RH		 6106 switch (OUTPUT_FLAVOR)
6107 {
4c63da97
AM		 6108#ifdef OBJ_MAYBE_AOUT
6109 case bfd_target_aout_flavour:
47926f60 6110 return AOUT_TARGET_FORMAT;
4c63da97
AM		 6111#endif
6112#ifdef OBJ_MAYBE_COFF
252b5132
RH		 6113 case bfd_target_coff_flavour:
6114 return "coff-i386";
4c63da97 6115#endif
3e73aa7c 6116#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 6117 case bfd_target_elf_flavour:
3e73aa7c 6118 {
e5cb08ac 6119 if (flag_code == CODE_64BIT)
4fa24527
JB		 6120 {
6121 object_64bit = 1;
6122 use_rela_relocations = 1;
6123 }
9d7cbccd 6124 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6125 }
4c63da97 6126#endif
252b5132
RH		 6127 default:
6128 abort ();
6129 return NULL;
6130 }
6131}
6132
47926f60 6133#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 6134
6135#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6136void i386_elf_emit_arch_note ()
6137{
718ddfc0 6138 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 6139 {
6140 char *p;
6141 asection *seg = now_seg;
6142 subsegT subseg = now_subseg;
6143 Elf_Internal_Note i_note;
6144 Elf_External_Note e_note;
6145 asection *note_secp;
6146 int len;
6147
6148 /* Create the .note section. */
6149 note_secp = subseg_new (".note", 0);
6150 bfd_set_section_flags (stdoutput,
6151 note_secp,
6152 SEC_HAS_CONTENTS | SEC_READONLY);
6153
6154 /* Process the arch string. */
6155 len = strlen (cpu_arch_name);
6156
6157 i_note.namesz = len + 1;
6158 i_note.descsz = 0;
6159 i_note.type = NT_ARCH;
6160 p = frag_more (sizeof (e_note.namesz));
6161 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6162 p = frag_more (sizeof (e_note.descsz));
6163 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6164 p = frag_more (sizeof (e_note.type));
6165 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6166 p = frag_more (len + 1);
6167 strcpy (p, cpu_arch_name);
6168
6169 frag_align (2, 0, 0);
6170
6171 subseg_set (seg, subseg);
6172 }
6173}
6174#endif
252b5132 6175\f
252b5132
RH		 6176symbolS *
6177md_undefined_symbol (name)
6178 char *name;
6179{
18dc2407
ILT		 6180 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6181 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6182 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6183 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6184 {
6185 if (!GOT_symbol)
6186 {
6187 if (symbol_find (name))
6188 as_bad (_("GOT already in symbol table"));
6189 GOT_symbol = symbol_new (name, undefined_section,
6190 (valueT) 0, &zero_address_frag);
6191 };
6192 return GOT_symbol;
6193 }
252b5132
RH		 6194 return 0;
6195}
6196
6197/* Round up a section size to the appropriate boundary. */
47926f60 6198
252b5132
RH		 6199valueT
6200md_section_align (segment, size)
ab9da554 6201 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6202 valueT size;
6203{
4c63da97
AM		 6204#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6205 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6206 {
6207 /* For a.out, force the section size to be aligned. If we don't do
6208 this, BFD will align it for us, but it will not write out the
6209 final bytes of the section. This may be a bug in BFD, but it is
6210 easier to fix it here since that is how the other a.out targets
6211 work. */
6212 int align;
6213
6214 align = bfd_get_section_alignment (stdoutput, segment);
6215 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6216 }
252b5132
RH		 6217#endif
6218
6219 return size;
6220}
6221
6222/* On the i386, PC-relative offsets are relative to the start of the
6223 next instruction. That is, the address of the offset, plus its
6224 size, since the offset is always the last part of the insn. */
6225
6226long
6227md_pcrel_from (fixP)
6228 fixS *fixP;
6229{
6230 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6231}
6232
6233#ifndef I386COFF
6234
6235static void
6236s_bss (ignore)
ab9da554 6237 int ignore ATTRIBUTE_UNUSED;
252b5132 6238{
29b0f896 6239 int temp;
252b5132 6240
8a75718c
JB		 6241#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6242 if (IS_ELF)
6243 obj_elf_section_change_hook ();
6244#endif
252b5132
RH		 6245 temp = get_absolute_expression ();
6246 subseg_set (bss_section, (subsegT) temp);
6247 demand_empty_rest_of_line ();
6248}
6249
6250#endif
6251
252b5132
RH		 6252void
6253i386_validate_fix (fixp)
6254 fixS *fixp;
6255{
6256 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6257 {
23df1078
JH		 6258 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6259 {
4fa24527 6260 if (!object_64bit)
23df1078
JH		 6261 abort ();
6262 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6263 }
6264 else
6265 {
4fa24527 6266 if (!object_64bit)
d6ab8113
JB		 6267 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6268 else
6269 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6270 }
252b5132
RH		 6271 fixp->fx_subsy = 0;
6272 }
6273}
6274
252b5132
RH		 6275arelent *
6276tc_gen_reloc (section, fixp)
ab9da554 6277 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6278 fixS *fixp;
6279{
6280 arelent *rel;
6281 bfd_reloc_code_real_type code;
6282
6283 switch (fixp->fx_r_type)
6284 {
3e73aa7c
JH		 6285 case BFD_RELOC_X86_64_PLT32:
6286 case BFD_RELOC_X86_64_GOT32:
6287 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6288 case BFD_RELOC_386_PLT32:
6289 case BFD_RELOC_386_GOT32:
6290 case BFD_RELOC_386_GOTOFF:
6291 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 6292 case BFD_RELOC_386_TLS_GD:
6293 case BFD_RELOC_386_TLS_LDM:
6294 case BFD_RELOC_386_TLS_LDO_32:
6295 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6296 case BFD_RELOC_386_TLS_IE:
6297 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 6298 case BFD_RELOC_386_TLS_LE_32:
6299 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 6300 case BFD_RELOC_386_TLS_GOTDESC:
6301 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 6302 case BFD_RELOC_X86_64_TLSGD:
6303 case BFD_RELOC_X86_64_TLSLD:
6304 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6305 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 6306 case BFD_RELOC_X86_64_GOTTPOFF:
6307 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 6308 case BFD_RELOC_X86_64_TPOFF64:
6309 case BFD_RELOC_X86_64_GOTOFF64:
6310 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 6311 case BFD_RELOC_X86_64_GOT64:
6312 case BFD_RELOC_X86_64_GOTPCREL64:
6313 case BFD_RELOC_X86_64_GOTPC64:
6314 case BFD_RELOC_X86_64_GOTPLT64:
6315 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 6316 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6317 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 6318 case BFD_RELOC_RVA:
6319 case BFD_RELOC_VTABLE_ENTRY:
6320 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 6321#ifdef TE_PE
6322 case BFD_RELOC_32_SECREL:
6323#endif
252b5132
RH		 6324 code = fixp->fx_r_type;
6325 break;
dbbaec26
L		 6326 case BFD_RELOC_X86_64_32S:
6327 if (!fixp->fx_pcrel)
6328 {
6329 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6330 code = fixp->fx_r_type;
6331 break;
6332 }
252b5132 6333 default:
93382f6d 6334 if (fixp->fx_pcrel)
252b5132 6335 {
93382f6d
AM		 6336 switch (fixp->fx_size)
6337 {
6338 default:
b091f402
AM		 6339 as_bad_where (fixp->fx_file, fixp->fx_line,
6340 _("can not do %d byte pc-relative relocation"),
6341 fixp->fx_size);
93382f6d
AM		 6342 code = BFD_RELOC_32_PCREL;
6343 break;
6344 case 1: code = BFD_RELOC_8_PCREL; break;
6345 case 2: code = BFD_RELOC_16_PCREL; break;
6346 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 6347#ifdef BFD64
6348 case 8: code = BFD_RELOC_64_PCREL; break;
6349#endif
93382f6d
AM		 6350 }
6351 }
6352 else
6353 {
6354 switch (fixp->fx_size)
6355 {
6356 default:
b091f402
AM		 6357 as_bad_where (fixp->fx_file, fixp->fx_line,
6358 _("can not do %d byte relocation"),
6359 fixp->fx_size);
93382f6d
AM		 6360 code = BFD_RELOC_32;
6361 break;
6362 case 1: code = BFD_RELOC_8; break;
6363 case 2: code = BFD_RELOC_16; break;
6364 case 4: code = BFD_RELOC_32; break;
937149dd 6365#ifdef BFD64
3e73aa7c 6366 case 8: code = BFD_RELOC_64; break;
937149dd 6367#endif
93382f6d 6368 }
252b5132
RH		 6369 }
6370 break;
6371 }
252b5132 6372
d182319b
JB		 6373 if ((code == BFD_RELOC_32
6374 || code == BFD_RELOC_32_PCREL
6375 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 6376 && GOT_symbol
6377 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 6378 {
4fa24527 6379 if (!object_64bit)
d6ab8113
JB		 6380 code = BFD_RELOC_386_GOTPC;
6381 else
6382 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 6383 }
7b81dfbb
AJ		 6384 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6385 && GOT_symbol
6386 && fixp->fx_addsy == GOT_symbol)
6387 {
6388 code = BFD_RELOC_X86_64_GOTPC64;
6389 }
252b5132
RH		 6390
6391 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 6392 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6393 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 6394
6395 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 6396
3e73aa7c
JH		 6397 if (!use_rela_relocations)
6398 {
6399 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6400 vtable entry to be used in the relocation's section offset. */
6401 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6402 rel->address = fixp->fx_offset;
252b5132 6403
c6682705 6404 rel->addend = 0;
3e73aa7c
JH		 6405 }
6406 /* Use the rela in 64bit mode. */
252b5132 6407 else
3e73aa7c 6408 {
062cd5e7
AS		 6409 if (!fixp->fx_pcrel)
6410 rel->addend = fixp->fx_offset;
6411 else
6412 switch (code)
6413 {
6414 case BFD_RELOC_X86_64_PLT32:
6415 case BFD_RELOC_X86_64_GOT32:
6416 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 6417 case BFD_RELOC_X86_64_TLSGD:
6418 case BFD_RELOC_X86_64_TLSLD:
6419 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 6420 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6421 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 6422 rel->addend = fixp->fx_offset - fixp->fx_size;
6423 break;
6424 default:
6425 rel->addend = (section->vma
6426 - fixp->fx_size
6427 + fixp->fx_addnumber
6428 + md_pcrel_from (fixp));
6429 break;
6430 }
3e73aa7c
JH		 6431 }
6432
252b5132
RH		 6433 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6434 if (rel->howto == NULL)
6435 {
6436 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 6437 _("cannot represent relocation type %s"),
252b5132
RH		 6438 bfd_get_reloc_code_name (code));
6439 /* Set howto to a garbage value so that we can keep going. */
6440 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6441 assert (rel->howto != NULL);
6442 }
6443
6444 return rel;
6445}
6446
64a0c779
DN		 6447\f
6448/* Parse operands using Intel syntax. This implements a recursive descent
6449 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6450 Programmer's Guide.
6451
6452 FIXME: We do not recognize the full operand grammar defined in the MASM
6453 documentation. In particular, all the structure/union and
6454 high-level macro operands are missing.
6455
6456 Uppercase words are terminals, lower case words are non-terminals.
6457 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6458 bars '|' denote choices. Most grammar productions are implemented in
6459 functions called 'intel_<production>'.
6460
6461 Initial production is 'expr'.
6462
9306ca4a 6463 addOp + | -
64a0c779
DN		 6464
6465 alpha [a-zA-Z]
6466
9306ca4a
JB		 6467 binOp & | AND | \| | OR | ^ | XOR
6468
64a0c779
DN		 6469 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6470
6471 constant digits [[ radixOverride ]]
6472
9306ca4a 6473 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 6474
6475 digits decdigit
b77a7acd
AJ		 6476 | digits decdigit
6477 | digits hexdigit
64a0c779
DN		 6478
6479 decdigit [0-9]
6480
9306ca4a
JB		 6481 e04 e04 addOp e05
6482 | e05
6483
6484 e05 e05 binOp e06
b77a7acd 6485 | e06
64a0c779
DN		 6486
6487 e06 e06 mulOp e09
b77a7acd 6488 | e09
64a0c779
DN		 6489
6490 e09 OFFSET e10
a724f0f4
JB		 6491 | SHORT e10
6492 | + e10
6493 | - e10
9306ca4a
JB		 6494 | ~ e10
6495 | NOT e10
64a0c779
DN		 6496 | e09 PTR e10
6497 | e09 : e10
6498 | e10
6499
6500 e10 e10 [ expr ]
b77a7acd 6501 | e11
64a0c779
DN		 6502
6503 e11 ( expr )
b77a7acd 6504 | [ expr ]
64a0c779
DN		 6505 | constant
6506 | dataType
6507 | id
6508 | $
6509 | register
6510
a724f0f4 6511 => expr expr cmpOp e04
9306ca4a 6512 | e04
64a0c779
DN		 6513
6514 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 6515 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 6516
6517 hexdigit a | b | c | d | e | f
b77a7acd 6518 | A | B | C | D | E | F
64a0c779
DN		 6519
6520 id alpha
b77a7acd 6521 | id alpha
64a0c779
DN		 6522 | id decdigit
6523
9306ca4a 6524 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 6525
6526 quote " | '
6527
6528 register specialRegister
b77a7acd 6529 | gpRegister
64a0c779
DN		 6530 | byteRegister
6531
6532 segmentRegister CS | DS | ES | FS | GS | SS
6533
9306ca4a 6534 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 6535 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 6536 | TR3 | TR4 | TR5 | TR6 | TR7
6537
64a0c779
DN		 6538 We simplify the grammar in obvious places (e.g., register parsing is
6539 done by calling parse_register) and eliminate immediate left recursion
6540 to implement a recursive-descent parser.
6541
a724f0f4
JB		 6542 expr e04 expr'
6543
6544 expr' cmpOp e04 expr'
6545 | Empty
9306ca4a
JB		 6546
6547 e04 e05 e04'
6548
6549 e04' addOp e05 e04'
6550 | Empty
64a0c779
DN		 6551
6552 e05 e06 e05'
6553
9306ca4a 6554 e05' binOp e06 e05'
b77a7acd 6555 | Empty
64a0c779
DN		 6556
6557 e06 e09 e06'
6558
6559 e06' mulOp e09 e06'
b77a7acd 6560 | Empty
64a0c779
DN		 6561
6562 e09 OFFSET e10 e09'
a724f0f4
JB		 6563 | SHORT e10'
6564 | + e10'
6565 | - e10'
6566 | ~ e10'
6567 | NOT e10'
b77a7acd 6568 | e10 e09'
64a0c779
DN		 6569
6570 e09' PTR e10 e09'
b77a7acd 6571 | : e10 e09'
64a0c779
DN		 6572 | Empty
6573
6574 e10 e11 e10'
6575
6576 e10' [ expr ] e10'
b77a7acd 6577 | Empty
64a0c779
DN		 6578
6579 e11 ( expr )
b77a7acd 6580 | [ expr ]
64a0c779
DN		 6581 | BYTE
6582 | WORD
6583 | DWORD
9306ca4a 6584 | FWORD
64a0c779 6585 | QWORD
9306ca4a
JB		 6586 | TBYTE
6587 | OWORD
6588 | XMMWORD
64a0c779
DN		 6589 | .
6590 | $
6591 | register
6592 | id
6593 | constant */
6594
6595/* Parsing structure for the intel syntax parser. Used to implement the
6596 semantic actions for the operand grammar. */
6597struct intel_parser_s
6598 {
6599 char *op_string; /* The string being parsed. */
6600 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6601 int op_modifier; /* Operand modifier. */
64a0c779 6602 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 6603 int in_offset; /* >=1 if parsing operand of offset. */
6604 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6605 const reg_entry *reg; /* Last register reference found. */
6606 char *disp; /* Displacement string being built. */
a724f0f4 6607 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6608 };
6609
6610static struct intel_parser_s intel_parser;
6611
6612/* Token structure for parsing intel syntax. */
6613struct intel_token
6614 {
6615 int code; /* Token code. */
6616 const reg_entry *reg; /* Register entry for register tokens. */
6617 char *str; /* String representation. */
6618 };
6619
6620static struct intel_token cur_token, prev_token;
6621
50705ef4
AM		 6622/* Token codes for the intel parser. Since T_SHORT is already used
6623 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6624#define T_NIL -1
6625#define T_CONST 1
6626#define T_REG 2
6627#define T_BYTE 3
6628#define T_WORD 4
9306ca4a
JB		 6629#define T_DWORD 5
6630#define T_FWORD 6
6631#define T_QWORD 7
6632#define T_TBYTE 8
6633#define T_XMMWORD 9
50705ef4 6634#undef T_SHORT
9306ca4a
JB		 6635#define T_SHORT 10
6636#define T_OFFSET 11
6637#define T_PTR 12
6638#define T_ID 13
6639#define T_SHL 14
6640#define T_SHR 15
64a0c779
DN		 6641
6642/* Prototypes for intel parser functions. */
6643static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 6644static void intel_get_token PARAMS ((void));
6645static void intel_putback_token PARAMS ((void));
6646static int intel_expr PARAMS ((void));
9306ca4a 6647static int intel_e04 PARAMS ((void));
cce0cbdc 6648static int intel_e05 PARAMS ((void));
cce0cbdc 6649static int intel_e06 PARAMS ((void));
cce0cbdc 6650static int intel_e09 PARAMS ((void));
a724f0f4 6651static int intel_bracket_expr PARAMS ((void));
cce0cbdc 6652static int intel_e10 PARAMS ((void));
cce0cbdc 6653static int intel_e11 PARAMS ((void));
64a0c779 6654
64a0c779
DN		 6655static int
6656i386_intel_operand (operand_string, got_a_float)
6657 char *operand_string;
6658 int got_a_float;
6659{
6660 int ret;
6661 char *p;
6662
a724f0f4
JB		 6663 p = intel_parser.op_string = xstrdup (operand_string);
6664 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6665
6666 for (;;)
64a0c779 6667 {
a724f0f4
JB		 6668 /* Initialize token holders. */
6669 cur_token.code = prev_token.code = T_NIL;
6670 cur_token.reg = prev_token.reg = NULL;
6671 cur_token.str = prev_token.str = NULL;
6672
6673 /* Initialize parser structure. */
6674 intel_parser.got_a_float = got_a_float;
6675 intel_parser.op_modifier = 0;
6676 intel_parser.is_mem = 0;
6677 intel_parser.in_offset = 0;
6678 intel_parser.in_bracket = 0;
6679 intel_parser.reg = NULL;
6680 intel_parser.disp[0] = '\0';
6681 intel_parser.next_operand = NULL;
6682
6683 /* Read the first token and start the parser. */
6684 intel_get_token ();
6685 ret = intel_expr ();
6686
6687 if (!ret)
6688 break;
6689
9306ca4a
JB		 6690 if (cur_token.code != T_NIL)
6691 {
6692 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6693 current_templates->start->name, cur_token.str);
6694 ret = 0;
6695 }
64a0c779
DN		 6696 /* If we found a memory reference, hand it over to i386_displacement
6697 to fill in the rest of the operand fields. */
9306ca4a 6698 else if (intel_parser.is_mem)
64a0c779
DN		 6699 {
6700 if ((i.mem_operands == 1
6701 && (current_templates->start->opcode_modifier & IsString) == 0)
6702 || i.mem_operands == 2)
6703 {
6704 as_bad (_("too many memory references for '%s'"),
6705 current_templates->start->name);
6706 ret = 0;
6707 }
6708 else
6709 {
6710 char *s = intel_parser.disp;
6711 i.mem_operands++;
6712
a724f0f4
JB		 6713 if (!quiet_warnings && intel_parser.is_mem < 0)
6714 /* See the comments in intel_bracket_expr. */
6715 as_warn (_("Treating `%s' as memory reference"), operand_string);
6716
64a0c779
DN		 6717 /* Add the displacement expression. */
6718 if (*s != '\0')
a4622f40
AM		 6719 ret = i386_displacement (s, s + strlen (s));
6720 if (ret)
a724f0f4
JB		 6721 {
6722 /* Swap base and index in 16-bit memory operands like
6723 [si+bx]. Since i386_index_check is also used in AT&T
6724 mode we have to do that here. */
6725 if (i.base_reg
6726 && i.index_reg
6727 && (i.base_reg->reg_type & Reg16)
6728 && (i.index_reg->reg_type & Reg16)
6729 && i.base_reg->reg_num >= 6
6730 && i.index_reg->reg_num < 6)
6731 {
6732 const reg_entry *base = i.index_reg;
6733
6734 i.index_reg = i.base_reg;
6735 i.base_reg = base;
6736 }
6737 ret = i386_index_check (operand_string);
6738 }
64a0c779
DN		 6739 }
6740 }
6741
6742 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6743 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6744 || intel_parser.reg == NULL)
6745 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6746
6747 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6748 ret = 0;
6749 if (!ret || !intel_parser.next_operand)
6750 break;
6751 intel_parser.op_string = intel_parser.next_operand;
6752 this_operand = i.operands++;
64a0c779
DN		 6753 }
6754
6755 free (p);
6756 free (intel_parser.disp);
6757
6758 return ret;
6759}
6760
a724f0f4
JB		 6761#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6762
6763/* expr e04 expr'
6764
6765 expr' cmpOp e04 expr'
6766 | Empty */
64a0c779
DN		 6767static int
6768intel_expr ()
6769{
a724f0f4
JB		 6770 /* XXX Implement the comparison operators. */
6771 return intel_e04 ();
9306ca4a
JB		 6772}
6773
a724f0f4 6774/* e04 e05 e04'
9306ca4a 6775
a724f0f4 6776 e04' addOp e05 e04'
9306ca4a
JB		 6777 | Empty */
6778static int
6779intel_e04 ()
6780{
a724f0f4 6781 int nregs = -1;
9306ca4a 6782
a724f0f4 6783 for (;;)
9306ca4a 6784 {
a724f0f4
JB		 6785 if (!intel_e05())
6786 return 0;
9306ca4a 6787
a724f0f4
JB		 6788 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6789 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6790
a724f0f4
JB		 6791 if (cur_token.code == '+')
6792 nregs = -1;
6793 else if (cur_token.code == '-')
6794 nregs = NUM_ADDRESS_REGS;
6795 else
6796 return 1;
64a0c779 6797
a724f0f4
JB		 6798 strcat (intel_parser.disp, cur_token.str);
6799 intel_match_token (cur_token.code);
6800 }
64a0c779
DN		 6801}
6802
64a0c779
DN		 6803/* e05 e06 e05'
6804
9306ca4a 6805 e05' binOp e06 e05'
64a0c779
DN		 6806 | Empty */
6807static int
6808intel_e05 ()
6809{
a724f0f4 6810 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6811
a724f0f4 6812 for (;;)
64a0c779 6813 {
a724f0f4
JB		 6814 if (!intel_e06())
6815 return 0;
6816
6817 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6818 {
6819 char str[2];
6820
6821 str[0] = cur_token.code;
6822 str[1] = 0;
6823 strcat (intel_parser.disp, str);
6824 }
6825 else
6826 break;
9306ca4a 6827
64a0c779
DN		 6828 intel_match_token (cur_token.code);
6829
a724f0f4
JB		 6830 if (nregs < 0)
6831 nregs = ~nregs;
64a0c779 6832 }
a724f0f4
JB		 6833 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6834 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6835 return 1;
4a1805b1 6836}
64a0c779
DN		 6837
6838/* e06 e09 e06'
6839
6840 e06' mulOp e09 e06'
b77a7acd 6841 | Empty */
64a0c779
DN		 6842static int
6843intel_e06 ()
6844{
a724f0f4 6845 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6846
a724f0f4 6847 for (;;)
64a0c779 6848 {
a724f0f4
JB		 6849 if (!intel_e09())
6850 return 0;
9306ca4a 6851
a724f0f4
JB		 6852 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6853 {
6854 char str[2];
9306ca4a 6855
a724f0f4
JB		 6856 str[0] = cur_token.code;
6857 str[1] = 0;
6858 strcat (intel_parser.disp, str);
6859 }
6860 else if (cur_token.code == T_SHL)
6861 strcat (intel_parser.disp, "<<");
6862 else if (cur_token.code == T_SHR)
6863 strcat (intel_parser.disp, ">>");
6864 else
6865 break;
9306ca4a 6866
64e74474 6867 intel_match_token (cur_token.code);
64a0c779 6868
a724f0f4
JB		 6869 if (nregs < 0)
6870 nregs = ~nregs;
64a0c779 6871 }
a724f0f4
JB		 6872 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6873 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6874 return 1;
64a0c779
DN		 6875}
6876
a724f0f4
JB		 6877/* e09 OFFSET e09
6878 | SHORT e09
6879 | + e09
6880 | - e09
6881 | ~ e09
6882 | NOT e09
9306ca4a
JB		 6883 | e10 e09'
6884
64a0c779 6885 e09' PTR e10 e09'
b77a7acd 6886 | : e10 e09'
64a0c779
DN		 6887 | Empty */
6888static int
6889intel_e09 ()
6890{
a724f0f4
JB		 6891 int nregs = ~NUM_ADDRESS_REGS;
6892 int in_offset = 0;
6893
6894 for (;;)
64a0c779 6895 {
a724f0f4
JB		 6896 /* Don't consume constants here. */
6897 if (cur_token.code == '+' || cur_token.code == '-')
6898 {
6899 /* Need to look one token ahead - if the next token
6900 is a constant, the current token is its sign. */
6901 int next_code;
6902
6903 intel_match_token (cur_token.code);
6904 next_code = cur_token.code;
6905 intel_putback_token ();
6906 if (next_code == T_CONST)
6907 break;
6908 }
6909
6910 /* e09 OFFSET e09 */
6911 if (cur_token.code == T_OFFSET)
6912 {
6913 if (!in_offset++)
6914 ++intel_parser.in_offset;
6915 }
6916
6917 /* e09 SHORT e09 */
6918 else if (cur_token.code == T_SHORT)
6919 intel_parser.op_modifier |= 1 << T_SHORT;
6920
6921 /* e09 + e09 */
6922 else if (cur_token.code == '+')
6923 strcat (intel_parser.disp, "+");
6924
6925 /* e09 - e09
6926 | ~ e09
6927 | NOT e09 */
6928 else if (cur_token.code == '-' || cur_token.code == '~')
6929 {
6930 char str[2];
64a0c779 6931
a724f0f4
JB		 6932 if (nregs < 0)
6933 nregs = ~nregs;
6934 str[0] = cur_token.code;
6935 str[1] = 0;
6936 strcat (intel_parser.disp, str);
6937 }
6938
6939 /* e09 e10 e09' */
6940 else
6941 break;
6942
6943 intel_match_token (cur_token.code);
64a0c779
DN		 6944 }
6945
a724f0f4 6946 for (;;)
9306ca4a 6947 {
a724f0f4
JB		 6948 if (!intel_e10 ())
6949 return 0;
9306ca4a 6950
a724f0f4
JB		 6951 /* e09' PTR e10 e09' */
6952 if (cur_token.code == T_PTR)
6953 {
6954 char suffix;
9306ca4a 6955
a724f0f4
JB		 6956 if (prev_token.code == T_BYTE)
6957 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6958
a724f0f4
JB		 6959 else if (prev_token.code == T_WORD)
6960 {
6961 if (current_templates->start->name[0] == 'l'
6962 && current_templates->start->name[2] == 's'
6963 && current_templates->start->name[3] == 0)
6964 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6965 else if (intel_parser.got_a_float == 2) /* "fi..." */
6966 suffix = SHORT_MNEM_SUFFIX;
6967 else
6968 suffix = WORD_MNEM_SUFFIX;
6969 }
64a0c779 6970
a724f0f4
JB		 6971 else if (prev_token.code == T_DWORD)
6972 {
6973 if (current_templates->start->name[0] == 'l'
6974 && current_templates->start->name[2] == 's'
6975 && current_templates->start->name[3] == 0)
6976 suffix = WORD_MNEM_SUFFIX;
6977 else if (flag_code == CODE_16BIT
6978 && (current_templates->start->opcode_modifier
435acd52 6979 & (Jump | JumpDword)))
a724f0f4
JB		 6980 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6981 else if (intel_parser.got_a_float == 1) /* "f..." */
6982 suffix = SHORT_MNEM_SUFFIX;
6983 else
6984 suffix = LONG_MNEM_SUFFIX;
6985 }
9306ca4a 6986
a724f0f4
JB		 6987 else if (prev_token.code == T_FWORD)
6988 {
6989 if (current_templates->start->name[0] == 'l'
6990 && current_templates->start->name[2] == 's'
6991 && current_templates->start->name[3] == 0)
6992 suffix = LONG_MNEM_SUFFIX;
6993 else if (!intel_parser.got_a_float)
6994 {
6995 if (flag_code == CODE_16BIT)
6996 add_prefix (DATA_PREFIX_OPCODE);
6997 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6998 }
6999 else
7000 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7001 }
64a0c779 7002
a724f0f4
JB		 7003 else if (prev_token.code == T_QWORD)
7004 {
7005 if (intel_parser.got_a_float == 1) /* "f..." */
7006 suffix = LONG_MNEM_SUFFIX;
7007 else
7008 suffix = QWORD_MNEM_SUFFIX;
7009 }
64a0c779 7010
a724f0f4
JB		 7011 else if (prev_token.code == T_TBYTE)
7012 {
7013 if (intel_parser.got_a_float == 1)
7014 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7015 else
7016 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7017 }
9306ca4a 7018
a724f0f4 7019 else if (prev_token.code == T_XMMWORD)
9306ca4a 7020 {
a724f0f4
JB		 7021 /* XXX ignored for now, but accepted since gcc uses it */
7022 suffix = 0;
9306ca4a 7023 }
64a0c779 7024
f16b83df 7025 else
a724f0f4
JB		 7026 {
7027 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
7028 return 0;
7029 }
7030
435acd52
JB		 7031 /* Operands for jump/call using 'ptr' notation denote absolute
7032 addresses. */
7033 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7034 i.types[this_operand] |= JumpAbsolute;
7035
a724f0f4
JB		 7036 if (current_templates->start->base_opcode == 0x8d /* lea */)
7037 ;
7038 else if (!i.suffix)
7039 i.suffix = suffix;
7040 else if (i.suffix != suffix)
7041 {
7042 as_bad (_("Conflicting operand modifiers"));
7043 return 0;
7044 }
64a0c779 7045
9306ca4a
JB		 7046 }
7047
a724f0f4
JB		 7048 /* e09' : e10 e09' */
7049 else if (cur_token.code == ':')
9306ca4a 7050 {
a724f0f4
JB		 7051 if (prev_token.code != T_REG)
7052 {
7053 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7054 segment/group identifier (which we don't have), using comma
7055 as the operand separator there is even less consistent, since
7056 there all branches only have a single operand. */
7057 if (this_operand != 0
7058 || intel_parser.in_offset
7059 || intel_parser.in_bracket
7060 || (!(current_templates->start->opcode_modifier
7061 & (Jump|JumpDword|JumpInterSegment))
7062 && !(current_templates->start->operand_types[0]
7063 & JumpAbsolute)))
7064 return intel_match_token (T_NIL);
7065 /* Remember the start of the 2nd operand and terminate 1st
7066 operand here.
7067 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7068 another expression), but it gets at least the simplest case
7069 (a plain number or symbol on the left side) right. */
7070 intel_parser.next_operand = intel_parser.op_string;
7071 *--intel_parser.op_string = '\0';
7072 return intel_match_token (':');
7073 }
9306ca4a 7074 }
64a0c779 7075
a724f0f4 7076 /* e09' Empty */
64a0c779 7077 else
a724f0f4 7078 break;
64a0c779 7079
a724f0f4
JB		 7080 intel_match_token (cur_token.code);
7081
7082 }
7083
7084 if (in_offset)
7085 {
7086 --intel_parser.in_offset;
7087 if (nregs < 0)
7088 nregs = ~nregs;
7089 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 7090 {
a724f0f4 7091 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 7092 return 0;
7093 }
a724f0f4
JB		 7094 intel_parser.op_modifier |= 1 << T_OFFSET;
7095 }
9306ca4a 7096
a724f0f4
JB		 7097 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7098 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7099 return 1;
7100}
64a0c779 7101
a724f0f4
JB		 7102static int
7103intel_bracket_expr ()
7104{
7105 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7106 const char *start = intel_parser.op_string;
7107 int len;
7108
7109 if (i.op[this_operand].regs)
7110 return intel_match_token (T_NIL);
7111
7112 intel_match_token ('[');
7113
7114 /* Mark as a memory operand only if it's not already known to be an
7115 offset expression. If it's an offset expression, we need to keep
7116 the brace in. */
7117 if (!intel_parser.in_offset)
7118 {
7119 ++intel_parser.in_bracket;
435acd52
JB		 7120
7121 /* Operands for jump/call inside brackets denote absolute addresses. */
7122 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7123 i.types[this_operand] |= JumpAbsolute;
7124
a724f0f4
JB		 7125 /* Unfortunately gas always diverged from MASM in a respect that can't
7126 be easily fixed without risking to break code sequences likely to be
7127 encountered (the testsuite even check for this): MASM doesn't consider
7128 an expression inside brackets unconditionally as a memory reference.
7129 When that is e.g. a constant, an offset expression, or the sum of the
7130 two, this is still taken as a constant load. gas, however, always
7131 treated these as memory references. As a compromise, we'll try to make
7132 offset expressions inside brackets work the MASM way (since that's
7133 less likely to be found in real world code), but make constants alone
7134 continue to work the traditional gas way. In either case, issue a
7135 warning. */
7136 intel_parser.op_modifier &= ~was_offset;
64a0c779 7137 }
a724f0f4 7138 else
64e74474 7139 strcat (intel_parser.disp, "[");
a724f0f4
JB		 7140
7141 /* Add a '+' to the displacement string if necessary. */
7142 if (*intel_parser.disp != '\0'
7143 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7144 strcat (intel_parser.disp, "+");
64a0c779 7145
a724f0f4
JB		 7146 if (intel_expr ()
7147 && (len = intel_parser.op_string - start - 1,
7148 intel_match_token (']')))
64a0c779 7149 {
a724f0f4
JB		 7150 /* Preserve brackets when the operand is an offset expression. */
7151 if (intel_parser.in_offset)
7152 strcat (intel_parser.disp, "]");
7153 else
7154 {
7155 --intel_parser.in_bracket;
7156 if (i.base_reg || i.index_reg)
7157 intel_parser.is_mem = 1;
7158 if (!intel_parser.is_mem)
7159 {
7160 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7161 /* Defer the warning until all of the operand was parsed. */
7162 intel_parser.is_mem = -1;
7163 else if (!quiet_warnings)
7164 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
7165 }
7166 }
7167 intel_parser.op_modifier |= was_offset;
64a0c779 7168
a724f0f4 7169 return 1;
64a0c779 7170 }
a724f0f4 7171 return 0;
64a0c779
DN		 7172}
7173
7174/* e10 e11 e10'
7175
7176 e10' [ expr ] e10'
b77a7acd 7177 | Empty */
64a0c779
DN		 7178static int
7179intel_e10 ()
7180{
a724f0f4
JB		 7181 if (!intel_e11 ())
7182 return 0;
64a0c779 7183
a724f0f4 7184 while (cur_token.code == '[')
64a0c779 7185 {
a724f0f4 7186 if (!intel_bracket_expr ())
21d6c4af 7187 return 0;
64a0c779
DN		 7188 }
7189
a724f0f4 7190 return 1;
64a0c779
DN		 7191}
7192
64a0c779 7193/* e11 ( expr )
b77a7acd 7194 | [ expr ]
64a0c779
DN		 7195 | BYTE
7196 | WORD
7197 | DWORD
9306ca4a 7198 | FWORD
64a0c779 7199 | QWORD
9306ca4a
JB		 7200 | TBYTE
7201 | OWORD
7202 | XMMWORD
4a1805b1 7203 | $
64a0c779
DN		 7204 | .
7205 | register
7206 | id
7207 | constant */
7208static int
7209intel_e11 ()
7210{
a724f0f4 7211 switch (cur_token.code)
64a0c779 7212 {
a724f0f4
JB		 7213 /* e11 ( expr ) */
7214 case '(':
64a0c779
DN		 7215 intel_match_token ('(');
7216 strcat (intel_parser.disp, "(");
7217
7218 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7219 {
7220 strcat (intel_parser.disp, ")");
7221 return 1;
7222 }
a724f0f4 7223 return 0;
4a1805b1 7224
a724f0f4
JB		 7225 /* e11 [ expr ] */
7226 case '[':
a724f0f4 7227 return intel_bracket_expr ();
64a0c779 7228
a724f0f4
JB		 7229 /* e11 $
7230 | . */
7231 case '.':
64a0c779
DN		 7232 strcat (intel_parser.disp, cur_token.str);
7233 intel_match_token (cur_token.code);
21d6c4af
DN		 7234
7235 /* Mark as a memory operand only if it's not already known to be an
7236 offset expression. */
a724f0f4 7237 if (!intel_parser.in_offset)
21d6c4af 7238 intel_parser.is_mem = 1;
64a0c779
DN		 7239
7240 return 1;
64a0c779 7241
a724f0f4
JB		 7242 /* e11 register */
7243 case T_REG:
7244 {
7245 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7246
a724f0f4 7247 intel_match_token (T_REG);
64a0c779 7248
a724f0f4
JB		 7249 /* Check for segment change. */
7250 if (cur_token.code == ':')
7251 {
7252 if (!(reg->reg_type & (SReg2 | SReg3)))
7253 {
7254 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
7255 return 0;
7256 }
7257 else if (i.seg[i.mem_operands])
7258 as_warn (_("Extra segment override ignored"));
7259 else
7260 {
7261 if (!intel_parser.in_offset)
7262 intel_parser.is_mem = 1;
7263 switch (reg->reg_num)
7264 {
7265 case 0:
7266 i.seg[i.mem_operands] = &es;
7267 break;
7268 case 1:
7269 i.seg[i.mem_operands] = &cs;
7270 break;
7271 case 2:
7272 i.seg[i.mem_operands] = &ss;
7273 break;
7274 case 3:
7275 i.seg[i.mem_operands] = &ds;
7276 break;
7277 case 4:
7278 i.seg[i.mem_operands] = &fs;
7279 break;
7280 case 5:
7281 i.seg[i.mem_operands] = &gs;
7282 break;
7283 }
7284 }
7285 }
64a0c779 7286
a724f0f4
JB		 7287 /* Not a segment register. Check for register scaling. */
7288 else if (cur_token.code == '*')
7289 {
7290 if (!intel_parser.in_bracket)
7291 {
7292 as_bad (_("Register scaling only allowed in memory operands"));
7293 return 0;
7294 }
64a0c779 7295
a724f0f4
JB		 7296 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7297 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7298 else if (i.index_reg)
7299 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 7300
a724f0f4
JB		 7301 /* What follows must be a valid scale. */
7302 intel_match_token ('*');
7303 i.index_reg = reg;
7304 i.types[this_operand] |= BaseIndex;
64a0c779 7305
a724f0f4
JB		 7306 /* Set the scale after setting the register (otherwise,
7307 i386_scale will complain) */
7308 if (cur_token.code == '+' || cur_token.code == '-')
7309 {
7310 char *str, sign = cur_token.code;
7311 intel_match_token (cur_token.code);
7312 if (cur_token.code != T_CONST)
7313 {
7314 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7315 cur_token.str);
7316 return 0;
7317 }
7318 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7319 strcpy (str + 1, cur_token.str);
7320 *str = sign;
7321 if (!i386_scale (str))
7322 return 0;
7323 free (str);
7324 }
7325 else if (!i386_scale (cur_token.str))
64a0c779 7326 return 0;
a724f0f4
JB		 7327 intel_match_token (cur_token.code);
7328 }
64a0c779 7329
a724f0f4
JB		 7330 /* No scaling. If this is a memory operand, the register is either a
7331 base register (first occurrence) or an index register (second
7332 occurrence). */
7b0441f6 7333 else if (intel_parser.in_bracket)
a724f0f4 7334 {
64a0c779 7335
a724f0f4
JB		 7336 if (!i.base_reg)
7337 i.base_reg = reg;
7338 else if (!i.index_reg)
7339 i.index_reg = reg;
7340 else
7341 {
7342 as_bad (_("Too many register references in memory operand"));
7343 return 0;
7344 }
64a0c779 7345
a724f0f4
JB		 7346 i.types[this_operand] |= BaseIndex;
7347 }
4a1805b1 7348
4d1bb795
JB		 7349 /* It's neither base nor index. */
7350 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 7351 {
7352 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7353 i.op[this_operand].regs = reg;
7354 i.reg_operands++;
7355 }
7356 else
7357 {
7358 as_bad (_("Invalid use of register"));
7359 return 0;
7360 }
64a0c779 7361
a724f0f4
JB		 7362 /* Since registers are not part of the displacement string (except
7363 when we're parsing offset operands), we may need to remove any
7364 preceding '+' from the displacement string. */
7365 if (*intel_parser.disp != '\0'
7366 && !intel_parser.in_offset)
7367 {
7368 char *s = intel_parser.disp;
7369 s += strlen (s) - 1;
7370 if (*s == '+')
7371 *s = '\0';
7372 }
4a1805b1 7373
a724f0f4
JB		 7374 return 1;
7375 }
7376
7377 /* e11 BYTE
7378 | WORD
7379 | DWORD
7380 | FWORD
7381 | QWORD
7382 | TBYTE
7383 | OWORD
7384 | XMMWORD */
7385 case T_BYTE:
7386 case T_WORD:
7387 case T_DWORD:
7388 case T_FWORD:
7389 case T_QWORD:
7390 case T_TBYTE:
7391 case T_XMMWORD:
7392 intel_match_token (cur_token.code);
64a0c779 7393
a724f0f4
JB		 7394 if (cur_token.code == T_PTR)
7395 return 1;
7396
7397 /* It must have been an identifier. */
7398 intel_putback_token ();
7399 cur_token.code = T_ID;
7400 /* FALLTHRU */
7401
7402 /* e11 id
7403 | constant */
7404 case T_ID:
7405 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 7406 {
7407 symbolS *symbolP;
7408
a724f0f4
JB		 7409 /* The identifier represents a memory reference only if it's not
7410 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 7411 symbolP = symbol_find(cur_token.str);
7412 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7413 intel_parser.is_mem = 1;
7414 }
a724f0f4 7415 /* FALLTHRU */
64a0c779 7416
a724f0f4
JB		 7417 case T_CONST:
7418 case '-':
7419 case '+':
7420 {
7421 char *save_str, sign = 0;
64a0c779 7422
a724f0f4
JB		 7423 /* Allow constants that start with `+' or `-'. */
7424 if (cur_token.code == '-' || cur_token.code == '+')
7425 {
7426 sign = cur_token.code;
7427 intel_match_token (cur_token.code);
7428 if (cur_token.code != T_CONST)
7429 {
7430 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7431 cur_token.str);
7432 return 0;
7433 }
7434 }
64a0c779 7435
a724f0f4
JB		 7436 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7437 strcpy (save_str + !!sign, cur_token.str);
7438 if (sign)
7439 *save_str = sign;
64a0c779 7440
a724f0f4
JB		 7441 /* Get the next token to check for register scaling. */
7442 intel_match_token (cur_token.code);
64a0c779 7443
a724f0f4
JB		 7444 /* Check if this constant is a scaling factor for an index register. */
7445 if (cur_token.code == '*')
7446 {
7447 if (intel_match_token ('*') && cur_token.code == T_REG)
7448 {
7449 const reg_entry *reg = cur_token.reg;
7450
7451 if (!intel_parser.in_bracket)
7452 {
7453 as_bad (_("Register scaling only allowed in memory operands"));
7454 return 0;
7455 }
7456
7457 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
7458 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7459 else if (i.index_reg)
7460 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7461
7462 /* The constant is followed by `* reg', so it must be
7463 a valid scale. */
7464 i.index_reg = reg;
7465 i.types[this_operand] |= BaseIndex;
7466
7467 /* Set the scale after setting the register (otherwise,
7468 i386_scale will complain) */
7469 if (!i386_scale (save_str))
64a0c779 7470 return 0;
a724f0f4
JB		 7471 intel_match_token (T_REG);
7472
7473 /* Since registers are not part of the displacement
7474 string, we may need to remove any preceding '+' from
7475 the displacement string. */
7476 if (*intel_parser.disp != '\0')
7477 {
7478 char *s = intel_parser.disp;
7479 s += strlen (s) - 1;
7480 if (*s == '+')
7481 *s = '\0';
7482 }
7483
7484 free (save_str);
7485
7486 return 1;
7487 }
64a0c779 7488
a724f0f4
JB		 7489 /* The constant was not used for register scaling. Since we have
7490 already consumed the token following `*' we now need to put it
7491 back in the stream. */
64a0c779 7492 intel_putback_token ();
a724f0f4 7493 }
64a0c779 7494
a724f0f4
JB		 7495 /* Add the constant to the displacement string. */
7496 strcat (intel_parser.disp, save_str);
7497 free (save_str);
64a0c779 7498
a724f0f4
JB		 7499 return 1;
7500 }
64a0c779
DN		 7501 }
7502
64a0c779
DN		 7503 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7504 return 0;
7505}
7506
64a0c779
DN		 7507/* Match the given token against cur_token. If they match, read the next
7508 token from the operand string. */
7509static int
7510intel_match_token (code)
e5cb08ac 7511 int code;
64a0c779
DN		 7512{
7513 if (cur_token.code == code)
7514 {
7515 intel_get_token ();
7516 return 1;
7517 }
7518 else
7519 {
0477af35 7520 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 7521 return 0;
7522 }
7523}
7524
64a0c779
DN		 7525/* Read a new token from intel_parser.op_string and store it in cur_token. */
7526static void
7527intel_get_token ()
7528{
7529 char *end_op;
7530 const reg_entry *reg;
7531 struct intel_token new_token;
7532
7533 new_token.code = T_NIL;
7534 new_token.reg = NULL;
7535 new_token.str = NULL;
7536
4a1805b1 7537 /* Free the memory allocated to the previous token and move
64a0c779
DN		 7538 cur_token to prev_token. */
7539 if (prev_token.str)
7540 free (prev_token.str);
7541
7542 prev_token = cur_token;
7543
7544 /* Skip whitespace. */
7545 while (is_space_char (*intel_parser.op_string))
7546 intel_parser.op_string++;
7547
7548 /* Return an empty token if we find nothing else on the line. */
7549 if (*intel_parser.op_string == '\0')
7550 {
7551 cur_token = new_token;
7552 return;
7553 }
7554
7555 /* The new token cannot be larger than the remainder of the operand
7556 string. */
a724f0f4 7557 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7558 new_token.str[0] = '\0';
7559
7560 if (strchr ("0123456789", *intel_parser.op_string))
7561 {
7562 char *p = new_token.str;
7563 char *q = intel_parser.op_string;
7564 new_token.code = T_CONST;
7565
7566 /* Allow any kind of identifier char to encompass floating point and
7567 hexadecimal numbers. */
7568 while (is_identifier_char (*q))
7569 *p++ = *q++;
7570 *p = '\0';
7571
7572 /* Recognize special symbol names [0-9][bf]. */
7573 if (strlen (intel_parser.op_string) == 2
4a1805b1 7574 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7575 || intel_parser.op_string[1] == 'f'))
7576 new_token.code = T_ID;
7577 }
7578
4d1bb795 7579 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7580 {
4d1bb795
JB		 7581 size_t len = end_op - intel_parser.op_string;
7582
64a0c779
DN		 7583 new_token.code = T_REG;
7584 new_token.reg = reg;
7585
4d1bb795
JB		 7586 memcpy (new_token.str, intel_parser.op_string, len);
7587 new_token.str[len] = '\0';
64a0c779
DN		 7588 }
7589
7590 else if (is_identifier_char (*intel_parser.op_string))
7591 {
7592 char *p = new_token.str;
7593 char *q = intel_parser.op_string;
7594
7595 /* A '.' or '$' followed by an identifier char is an identifier.
7596 Otherwise, it's operator '.' followed by an expression. */
7597 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7598 {
9306ca4a
JB		 7599 new_token.code = '.';
7600 new_token.str[0] = '.';
64a0c779
DN		 7601 new_token.str[1] = '\0';
7602 }
7603 else
7604 {
7605 while (is_identifier_char (*q) || *q == '@')
7606 *p++ = *q++;
7607 *p = '\0';
7608
9306ca4a
JB		 7609 if (strcasecmp (new_token.str, "NOT") == 0)
7610 new_token.code = '~';
7611
7612 else if (strcasecmp (new_token.str, "MOD") == 0)
7613 new_token.code = '%';
7614
7615 else if (strcasecmp (new_token.str, "AND") == 0)
7616 new_token.code = '&';
7617
7618 else if (strcasecmp (new_token.str, "OR") == 0)
7619 new_token.code = '|';
7620
7621 else if (strcasecmp (new_token.str, "XOR") == 0)
7622 new_token.code = '^';
7623
7624 else if (strcasecmp (new_token.str, "SHL") == 0)
7625 new_token.code = T_SHL;
7626
7627 else if (strcasecmp (new_token.str, "SHR") == 0)
7628 new_token.code = T_SHR;
7629
7630 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7631 new_token.code = T_BYTE;
7632
7633 else if (strcasecmp (new_token.str, "WORD") == 0)
7634 new_token.code = T_WORD;
7635
7636 else if (strcasecmp (new_token.str, "DWORD") == 0)
7637 new_token.code = T_DWORD;
7638
9306ca4a
JB		 7639 else if (strcasecmp (new_token.str, "FWORD") == 0)
7640 new_token.code = T_FWORD;
7641
64a0c779
DN		 7642 else if (strcasecmp (new_token.str, "QWORD") == 0)
7643 new_token.code = T_QWORD;
7644
9306ca4a
JB		 7645 else if (strcasecmp (new_token.str, "TBYTE") == 0
7646 /* XXX remove (gcc still uses it) */
7647 || strcasecmp (new_token.str, "XWORD") == 0)
7648 new_token.code = T_TBYTE;
7649
7650 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7651 || strcasecmp (new_token.str, "OWORD") == 0)
7652 new_token.code = T_XMMWORD;
64a0c779
DN		 7653
7654 else if (strcasecmp (new_token.str, "PTR") == 0)
7655 new_token.code = T_PTR;
7656
7657 else if (strcasecmp (new_token.str, "SHORT") == 0)
7658 new_token.code = T_SHORT;
7659
7660 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7661 {
7662 new_token.code = T_OFFSET;
7663
7664 /* ??? This is not mentioned in the MASM grammar but gcc
7665 makes use of it with -mintel-syntax. OFFSET may be
7666 followed by FLAT: */
7667 if (strncasecmp (q, " FLAT:", 6) == 0)
7668 strcat (new_token.str, " FLAT:");
7669 }
7670
7671 /* ??? This is not mentioned in the MASM grammar. */
7672 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7673 {
7674 new_token.code = T_OFFSET;
7675 if (*q == ':')
7676 strcat (new_token.str, ":");
7677 else
7678 as_bad (_("`:' expected"));
7679 }
64a0c779
DN		 7680
7681 else
7682 new_token.code = T_ID;
7683 }
7684 }
7685
9306ca4a
JB		 7686 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7687 {
7688 new_token.code = *intel_parser.op_string;
7689 new_token.str[0] = *intel_parser.op_string;
7690 new_token.str[1] = '\0';
7691 }
7692
7693 else if (strchr ("<>", *intel_parser.op_string)
7694 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7695 {
7696 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7697 new_token.str[0] = *intel_parser.op_string;
7698 new_token.str[1] = *intel_parser.op_string;
7699 new_token.str[2] = '\0';
7700 }
7701
64a0c779 7702 else
0477af35 7703 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7704
7705 intel_parser.op_string += strlen (new_token.str);
7706 cur_token = new_token;
7707}
7708
64a0c779
DN		 7709/* Put cur_token back into the token stream and make cur_token point to
7710 prev_token. */
7711static void
7712intel_putback_token ()
7713{
a724f0f4
JB		 7714 if (cur_token.code != T_NIL)
7715 {
7716 intel_parser.op_string -= strlen (cur_token.str);
7717 free (cur_token.str);
7718 }
64a0c779 7719 cur_token = prev_token;
4a1805b1 7720
64a0c779
DN		 7721 /* Forget prev_token. */
7722 prev_token.code = T_NIL;
7723 prev_token.reg = NULL;
7724 prev_token.str = NULL;
7725}
54cfded0 7726
a4447b93 7727int
1df69f4f 7728tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 7729{
7730 unsigned int regnum;
7731 unsigned int regnames_count;
089dfecd 7732 static const char *const regnames_32[] =
54cfded0 7733 {
a4447b93
RH		 7734 "eax", "ecx", "edx", "ebx",
7735 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7736 "eip", "eflags", NULL,
7737 "st0", "st1", "st2", "st3",
7738 "st4", "st5", "st6", "st7",
7739 NULL, NULL,
7740 "xmm0", "xmm1", "xmm2", "xmm3",
7741 "xmm4", "xmm5", "xmm6", "xmm7",
7742 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7743 "mm4", "mm5", "mm6", "mm7",
7744 "fcw", "fsw", "mxcsr",
7745 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7746 "tr", "ldtr"
54cfded0 7747 };
089dfecd 7748 static const char *const regnames_64[] =
54cfded0 7749 {
089dfecd
JB		 7750 "rax", "rdx", "rcx", "rbx",
7751 "rsi", "rdi", "rbp", "rsp",
7752 "r8", "r9", "r10", "r11",
54cfded0 7753 "r12", "r13", "r14", "r15",
089dfecd
JB		 7754 "rip",
7755 "xmm0", "xmm1", "xmm2", "xmm3",
7756 "xmm4", "xmm5", "xmm6", "xmm7",
7757 "xmm8", "xmm9", "xmm10", "xmm11",
7758 "xmm12", "xmm13", "xmm14", "xmm15",
7759 "st0", "st1", "st2", "st3",
7760 "st4", "st5", "st6", "st7",
7761 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7762 "mm4", "mm5", "mm6", "mm7",
7763 "rflags",
7764 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7765 "fs.base", "gs.base", NULL, NULL,
7766 "tr", "ldtr",
7767 "mxcsr", "fcw", "fsw"
54cfded0 7768 };
089dfecd 7769 const char *const *regnames;
54cfded0
AM		 7770
7771 if (flag_code == CODE_64BIT)
7772 {
7773 regnames = regnames_64;
0cea6190 7774 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7775 }
7776 else
7777 {
7778 regnames = regnames_32;
0cea6190 7779 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7780 }
7781
7782 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7783 if (regnames[regnum] != NULL
7784 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7785 return regnum;
7786
54cfded0
AM		 7787 return -1;
7788}
7789
7790void
7791tc_x86_frame_initial_instructions (void)
7792{
a4447b93
RH		 7793 static unsigned int sp_regno;
7794
7795 if (!sp_regno)
7796 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7797 ? "rsp" : "esp");
7798
7799 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7800 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7801}
d2b2c203
DJ		 7802
7803int
7804i386_elf_section_type (const char *str, size_t len)
7805{
7806 if (flag_code == CODE_64BIT
7807 && len == sizeof ("unwind") - 1
7808 && strncmp (str, "unwind", 6) == 0)
7809 return SHT_X86_64_UNWIND;
7810
7811 return -1;
7812}
bb41ade5
AM		 7813
7814#ifdef TE_PE
7815void
7816tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7817{
7818 expressionS expr;
7819
7820 expr.X_op = O_secrel;
7821 expr.X_add_symbol = symbol;
7822 expr.X_add_number = 0;
7823 emit_expr (&expr, size);
7824}
7825#endif
3b22753a
L		 7826
7827#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7828/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7829
7830int
7831x86_64_section_letter (int letter, char **ptr_msg)
7832{
7833 if (flag_code == CODE_64BIT)
7834 {
7835 if (letter == 'l')
7836 return SHF_X86_64_LARGE;
7837
7838 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7839 }
3b22753a 7840 else
64e74474 7841 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7842 return -1;
7843}
7844
7845int
7846x86_64_section_word (char *str, size_t len)
7847{
8620418b 7848 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 7849 return SHF_X86_64_LARGE;
7850
7851 return -1;
7852}
7853
7854static void
7855handle_large_common (int small ATTRIBUTE_UNUSED)
7856{
7857 if (flag_code != CODE_64BIT)
7858 {
7859 s_comm_internal (0, elf_common_parse);
7860 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7861 }
7862 else
7863 {
7864 static segT lbss_section;
7865 asection *saved_com_section_ptr = elf_com_section_ptr;
7866 asection *saved_bss_section = bss_section;
7867
7868 if (lbss_section == NULL)
7869 {
7870 flagword applicable;
7871 segT seg = now_seg;
7872 subsegT subseg = now_subseg;
7873
7874 /* The .lbss section is for local .largecomm symbols. */
7875 lbss_section = subseg_new (".lbss", 0);
7876 applicable = bfd_applicable_section_flags (stdoutput);
7877 bfd_set_section_flags (stdoutput, lbss_section,
7878 applicable & SEC_ALLOC);
7879 seg_info (lbss_section)->bss = 1;
7880
7881 subseg_set (seg, subseg);
7882 }
7883
7884 elf_com_section_ptr = &_bfd_elf_large_com_section;
7885 bss_section = lbss_section;
7886
7887 s_comm_internal (0, elf_common_parse);
7888
7889 elf_com_section_ptr = saved_com_section_ptr;
7890 bss_section = saved_bss_section;
7891 }
7892}
7893#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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