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* interp.c (options enum): Add OPTION_INFO_MEMORY.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4dc85607 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
252b5132 36
252b5132
RH		 37#ifndef REGISTER_WARNINGS
38#define REGISTER_WARNINGS 1
39#endif
40
c3332e24 41#ifndef INFER_ADDR_PREFIX
eecb386c 42#define INFER_ADDR_PREFIX 1
c3332e24
AM		 43#endif
44
252b5132
RH		 45#ifndef SCALE1_WHEN_NO_INDEX
46/* Specifying a scale factor besides 1 when there is no index is
47 futile. eg. `mov (%ebx,2),%al' does exactly the same as
48 `mov (%ebx),%al'. To slavishly follow what the programmer
49 specified, set SCALE1_WHEN_NO_INDEX to 0. */
50#define SCALE1_WHEN_NO_INDEX 1
51#endif
52
29b0f896
AM		 53#ifndef DEFAULT_ARCH
54#define DEFAULT_ARCH "i386"
246fcdee 55#endif
252b5132 56
edde18a5
AM		 57#ifndef INLINE
58#if __GNUC__ >= 2
59#define INLINE __inline__
60#else
61#define INLINE
62#endif
63#endif
64
e3bb37b5
L		 65static void set_code_flag (int);
66static void set_16bit_gcc_code_flag (int);
67static void set_intel_syntax (int);
68static void set_cpu_arch (int);
6482c264 69#ifdef TE_PE
e3bb37b5 70static void pe_directive_secrel (int);
6482c264 71#endif
e3bb37b5
L		 72static void signed_cons (int);
73static char *output_invalid (int c);
74static int i386_operand (char *);
75static int i386_intel_operand (char *, int);
76static const reg_entry *parse_register (char *, char **);
77static char *parse_insn (char *, char *);
78static char *parse_operands (char *, const char *);
79static void swap_operands (void);
4d456e3d 80static void swap_2_operands (int, int);
e3bb37b5
L		 81static void optimize_imm (void);
82static void optimize_disp (void);
83static int match_template (void);
84static int check_string (void);
85static int process_suffix (void);
86static int check_byte_reg (void);
87static int check_long_reg (void);
88static int check_qword_reg (void);
89static int check_word_reg (void);
90static int finalize_imm (void);
91static int process_operands (void);
92static const seg_entry *build_modrm_byte (void);
93static void output_insn (void);
94static void output_imm (fragS *, offsetT);
95static void output_disp (fragS *, offsetT);
29b0f896 96#ifndef I386COFF
e3bb37b5 97static void s_bss (int);
252b5132 98#endif
17d4e2a2
L		 99#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
100static void handle_large_common (int small ATTRIBUTE_UNUSED);
101#endif
252b5132 102
a847613f 103static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 104
252b5132 105/* 'md_assemble ()' gathers together information and puts it into a
47926f60 106 i386_insn. */
252b5132 107
520dc8e8
AM		 108union i386_op
109 {
110 expressionS *disps;
111 expressionS *imms;
112 const reg_entry *regs;
113 };
114
252b5132
RH		 115struct _i386_insn
116 {
47926f60 117 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 118 template tm;
119
120 /* SUFFIX holds the instruction mnemonic suffix if given.
121 (e.g. 'l' for 'movl') */
122 char suffix;
123
47926f60 124 /* OPERANDS gives the number of given operands. */
252b5132
RH		 125 unsigned int operands;
126
127 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
128 of given register, displacement, memory operands and immediate
47926f60 129 operands. */
252b5132
RH		 130 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
131
132 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 133 use OP[i] for the corresponding operand. */
252b5132
RH		 134 unsigned int types[MAX_OPERANDS];
135
520dc8e8
AM		 136 /* Displacement expression, immediate expression, or register for each
137 operand. */
138 union i386_op op[MAX_OPERANDS];
252b5132 139
3e73aa7c
JH		 140 /* Flags for operands. */
141 unsigned int flags[MAX_OPERANDS];
142#define Operand_PCrel 1
143
252b5132 144 /* Relocation type for operand */
f86103b7 145 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 146
252b5132
RH		 147 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
148 the base index byte below. */
149 const reg_entry *base_reg;
150 const reg_entry *index_reg;
151 unsigned int log2_scale_factor;
152
153 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 154 explicit segment overrides are given. */
ce8a8b2f 155 const seg_entry *seg[2];
252b5132
RH		 156
157 /* PREFIX holds all the given prefix opcodes (usually null).
158 PREFIXES is the number of prefix opcodes. */
159 unsigned int prefixes;
160 unsigned char prefix[MAX_PREFIXES];
161
162 /* RM and SIB are the modrm byte and the sib byte where the
163 addressing modes of this insn are encoded. */
164
165 modrm_byte rm;
3e73aa7c 166 rex_byte rex;
252b5132
RH		 167 sib_byte sib;
168 };
169
170typedef struct _i386_insn i386_insn;
171
172/* List of chars besides those in app.c:symbol_chars that can start an
173 operand. Used to prevent the scrubber eating vital white-space. */
32137342 174const char extra_symbol_chars[] = "*%-(["
252b5132 175#ifdef LEX_AT
32137342
NC		 176 "@"
177#endif
178#ifdef LEX_QM
179 "?"
252b5132 180#endif
32137342 181 ;
252b5132 182
29b0f896
AM		 183#if (defined (TE_I386AIX) \
184 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 185 && !defined (TE_GNU) \
29b0f896 186 && !defined (TE_LINUX) \
32137342 187 && !defined (TE_NETWARE) \
29b0f896
AM		 188 && !defined (TE_FreeBSD) \
189 && !defined (TE_NetBSD)))
252b5132 190/* This array holds the chars that always start a comment. If the
b3b91714
AM		 191 pre-processor is disabled, these aren't very useful. The option
192 --divide will remove '/' from this list. */
193const char *i386_comment_chars = "#/";
194#define SVR4_COMMENT_CHARS 1
252b5132 195#define PREFIX_SEPARATOR '\\'
252b5132 196
b3b91714
AM		 197#else
198const char *i386_comment_chars = "#";
199#define PREFIX_SEPARATOR '/'
200#endif
201
252b5132
RH		 202/* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 204 .line and .file directives will appear in the pre-processed output.
205 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 206 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 207 #NO_APP at the beginning of its output.
208 Also note that comments started like this one will always work if
252b5132 209 '/' isn't otherwise defined. */
b3b91714 210const char line_comment_chars[] = "#/";
252b5132 211
63a0b638 212const char line_separator_chars[] = ";";
252b5132 213
ce8a8b2f
AM		 214/* Chars that can be used to separate mant from exp in floating point
215 nums. */
252b5132
RH		 216const char EXP_CHARS[] = "eE";
217
ce8a8b2f
AM		 218/* Chars that mean this number is a floating point constant
219 As in 0f12.456
220 or 0d1.2345e12. */
252b5132
RH		 221const char FLT_CHARS[] = "fFdDxX";
222
ce8a8b2f 223/* Tables for lexical analysis. */
252b5132
RH		 224static char mnemonic_chars[256];
225static char register_chars[256];
226static char operand_chars[256];
227static char identifier_chars[256];
228static char digit_chars[256];
229
ce8a8b2f 230/* Lexical macros. */
252b5132
RH		 231#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
232#define is_operand_char(x) (operand_chars[(unsigned char) x])
233#define is_register_char(x) (register_chars[(unsigned char) x])
234#define is_space_char(x) ((x) == ' ')
235#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
236#define is_digit_char(x) (digit_chars[(unsigned char) x])
237
0234cb7c 238/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 239static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
240
241/* md_assemble() always leaves the strings it's passed unaltered. To
242 effect this we maintain a stack of saved characters that we've smashed
243 with '\0's (indicating end of strings for various sub-fields of the
47926f60 244 assembler instruction). */
252b5132 245static char save_stack[32];
ce8a8b2f 246static char *save_stack_p;
252b5132
RH		 247#define END_STRING_AND_SAVE(s) \
248 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
249#define RESTORE_END_STRING(s) \
250 do { *(s) = *--save_stack_p; } while (0)
251
47926f60 252/* The instruction we're assembling. */
252b5132
RH		 253static i386_insn i;
254
255/* Possible templates for current insn. */
256static const templates *current_templates;
257
31b2323c
L		 258/* Per instruction expressionS buffers: max displacements & immediates. */
259static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
260static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 261
47926f60
KH		 262/* Current operand we are working on. */
263static int this_operand;
252b5132 264
3e73aa7c
JH		 265/* We support four different modes. FLAG_CODE variable is used to distinguish
266 these. */
267
268enum flag_code {
269 CODE_32BIT,
270 CODE_16BIT,
271 CODE_64BIT };
f3c180ae 272#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 273
274static enum flag_code flag_code;
4fa24527 275static unsigned int object_64bit;
3e73aa7c
JH		 276static int use_rela_relocations = 0;
277
278/* The names used to print error messages. */
b77a7acd 279static const char *flag_code_names[] =
3e73aa7c
JH		 280 {
281 "32",
282 "16",
283 "64"
284 };
252b5132 285
47926f60
KH		 286/* 1 for intel syntax,
287 0 if att syntax. */
288static int intel_syntax = 0;
252b5132 289
47926f60
KH		 290/* 1 if register prefix % not required. */
291static int allow_naked_reg = 0;
252b5132 292
2ca3ace5
L		 293/* Register prefix used for error message. */
294static const char *register_prefix = "%";
295
47926f60
KH		 296/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
297 leave, push, and pop instructions so that gcc has the same stack
298 frame as in 32 bit mode. */
299static char stackop_size = '\0';
eecb386c 300
12b55ccc
L		 301/* Non-zero to optimize code alignment. */
302int optimize_align_code = 1;
303
47926f60
KH		 304/* Non-zero to quieten some warnings. */
305static int quiet_warnings = 0;
a38cf1db 306
47926f60
KH		 307/* CPU name. */
308static const char *cpu_arch_name = NULL;
5c6af06e 309static const char *cpu_sub_arch_name = NULL;
a38cf1db 310
47926f60 311/* CPU feature flags. */
29b0f896 312static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 313
ccc9c027
L		 314/* If we have selected a cpu we are generating instructions for. */
315static int cpu_arch_tune_set = 0;
316
9103f4f4
L		 317/* Cpu we are generating instructions for. */
318static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
319
320/* CPU feature flags of cpu we are generating instructions for. */
321static unsigned int cpu_arch_tune_flags = 0;
322
ccc9c027
L		 323/* CPU instruction set architecture used. */
324static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
325
9103f4f4
L		 326/* CPU feature flags of instruction set architecture used. */
327static unsigned int cpu_arch_isa_flags = 0;
328
fddf5b5b
AM		 329/* If set, conditional jumps are not automatically promoted to handle
330 larger than a byte offset. */
331static unsigned int no_cond_jump_promotion = 0;
332
29b0f896 333/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 334static symbolS *GOT_symbol;
29b0f896 335
a4447b93
RH		 336/* The dwarf2 return column, adjusted for 32 or 64 bit. */
337unsigned int x86_dwarf2_return_column;
338
339/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
340int x86_cie_data_alignment;
341
252b5132 342/* Interface to relax_segment.
fddf5b5b
AM		 343 There are 3 major relax states for 386 jump insns because the
344 different types of jumps add different sizes to frags when we're
345 figuring out what sort of jump to choose to reach a given label. */
252b5132 346
47926f60 347/* Types. */
93c2a809
AM		 348#define UNCOND_JUMP 0
349#define COND_JUMP 1
350#define COND_JUMP86 2
fddf5b5b 351
47926f60 352/* Sizes. */
252b5132
RH		 353#define CODE16 1
354#define SMALL 0
29b0f896 355#define SMALL16 (SMALL | CODE16)
252b5132 356#define BIG 2
29b0f896 357#define BIG16 (BIG | CODE16)
252b5132
RH		 358
359#ifndef INLINE
360#ifdef __GNUC__
361#define INLINE __inline__
362#else
363#define INLINE
364#endif
365#endif
366
fddf5b5b
AM		 367#define ENCODE_RELAX_STATE(type, size) \
368 ((relax_substateT) (((type) << 2) | (size)))
369#define TYPE_FROM_RELAX_STATE(s) \
370 ((s) >> 2)
371#define DISP_SIZE_FROM_RELAX_STATE(s) \
372 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 373
374/* This table is used by relax_frag to promote short jumps to long
375 ones where necessary. SMALL (short) jumps may be promoted to BIG
376 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
377 don't allow a short jump in a 32 bit code segment to be promoted to
378 a 16 bit offset jump because it's slower (requires data size
379 prefix), and doesn't work, unless the destination is in the bottom
380 64k of the code segment (The top 16 bits of eip are zeroed). */
381
382const relax_typeS md_relax_table[] =
383{
24eab124
AM		 384 /* The fields are:
385 1) most positive reach of this state,
386 2) most negative reach of this state,
93c2a809 387 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 388 4) which index into the table to try if we can't fit into this one. */
252b5132 389
fddf5b5b 390 /* UNCOND_JUMP states. */
93c2a809
AM		 391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
393 /* dword jmp adds 4 bytes to frag:
394 0 extra opcode bytes, 4 displacement bytes. */
252b5132 395 {0, 0, 4, 0},
93c2a809
AM		 396 /* word jmp adds 2 byte2 to frag:
397 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 398 {0, 0, 2, 0},
399
93c2a809
AM		 400 /* COND_JUMP states. */
401 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
403 /* dword conditionals adds 5 bytes to frag:
404 1 extra opcode byte, 4 displacement bytes. */
405 {0, 0, 5, 0},
fddf5b5b 406 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 407 1 extra opcode byte, 2 displacement bytes. */
408 {0, 0, 3, 0},
409
410 /* COND_JUMP86 states. */
411 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
413 /* dword conditionals adds 5 bytes to frag:
414 1 extra opcode byte, 4 displacement bytes. */
415 {0, 0, 5, 0},
416 /* word conditionals add 4 bytes to frag:
417 1 displacement byte and a 3 byte long branch insn. */
418 {0, 0, 4, 0}
252b5132
RH		 419};
420
9103f4f4
L		 421static const arch_entry cpu_arch[] =
422{
423 {"generic32", PROCESSOR_GENERIC32,
d32cad65 424 Cpu186|Cpu286|Cpu386},
9103f4f4 425 {"generic64", PROCESSOR_GENERIC64,
d32cad65 426 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 427 |CpuMMX2|CpuSSE|CpuSSE2},
428 {"i8086", PROCESSOR_UNKNOWN,
d32cad65 429 0},
9103f4f4 430 {"i186", PROCESSOR_UNKNOWN,
d32cad65 431 Cpu186},
9103f4f4 432 {"i286", PROCESSOR_UNKNOWN,
d32cad65 433 Cpu186|Cpu286},
76bc74dc 434 {"i386", PROCESSOR_I386,
d32cad65 435 Cpu186|Cpu286|Cpu386},
9103f4f4 436 {"i486", PROCESSOR_I486,
d32cad65 437 Cpu186|Cpu286|Cpu386|Cpu486},
9103f4f4 438 {"i586", PROCESSOR_PENTIUM,
d32cad65 439 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 440 {"i686", PROCESSOR_PENTIUMPRO,
d32cad65 441 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 442 {"pentium", PROCESSOR_PENTIUM,
d32cad65 443 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 444 {"pentiumpro",PROCESSOR_PENTIUMPRO,
d32cad65 445 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 446 {"pentiumii", PROCESSOR_PENTIUMPRO,
d32cad65 447 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
9103f4f4 448 {"pentiumiii",PROCESSOR_PENTIUMPRO,
d32cad65 449 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
9103f4f4 450 {"pentium4", PROCESSOR_PENTIUM4,
d32cad65 451 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 452 |CpuMMX2|CpuSSE|CpuSSE2},
453 {"prescott", PROCESSOR_NOCONA,
d32cad65 454 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 455 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
456 {"nocona", PROCESSOR_NOCONA,
d32cad65 457 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 458 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 459 {"yonah", PROCESSOR_CORE,
d32cad65 460 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 461 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 462 {"core", PROCESSOR_CORE,
d32cad65 463 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
ef05d495
L		 464 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
465 {"merom", PROCESSOR_CORE2,
466 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
467 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
468 {"core2", PROCESSOR_CORE2,
469 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
470 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4 471 {"k6", PROCESSOR_K6,
d32cad65 472 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
9103f4f4 473 {"k6_2", PROCESSOR_K6,
d32cad65 474 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
9103f4f4 475 {"athlon", PROCESSOR_ATHLON,
d32cad65 476 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 477 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
478 {"sledgehammer", PROCESSOR_K8,
d32cad65 479 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 480 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
481 {"opteron", PROCESSOR_K8,
d32cad65 482 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 483 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
484 {"k8", PROCESSOR_K8,
d32cad65 485 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4 486 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
050dfa73 487 {"amdfam10", PROCESSOR_AMDFAM10,
d32cad65
L		 488 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
489 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
490 |CpuABM},
9103f4f4
L		 491 {".mmx", PROCESSOR_UNKNOWN,
492 CpuMMX},
493 {".sse", PROCESSOR_UNKNOWN,
494 CpuMMX|CpuMMX2|CpuSSE},
495 {".sse2", PROCESSOR_UNKNOWN,
496 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
497 {".sse3", PROCESSOR_UNKNOWN,
498 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495
L		 499 {".ssse3", PROCESSOR_UNKNOWN,
500 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
42903f7f
L		 501 {".sse4.1", PROCESSOR_UNKNOWN,
502 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1},
381d071f
L		 503 {".sse4.2", PROCESSOR_UNKNOWN,
504 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4},
505 {".sse4", PROCESSOR_UNKNOWN,
506 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4},
9103f4f4
L		 507 {".3dnow", PROCESSOR_UNKNOWN,
508 CpuMMX|Cpu3dnow},
509 {".3dnowa", PROCESSOR_UNKNOWN,
510 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
511 {".padlock", PROCESSOR_UNKNOWN,
512 CpuPadLock},
513 {".pacifica", PROCESSOR_UNKNOWN,
514 CpuSVME},
515 {".svme", PROCESSOR_UNKNOWN,
050dfa73
MM		 516 CpuSVME},
517 {".sse4a", PROCESSOR_UNKNOWN,
518 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
519 {".abm", PROCESSOR_UNKNOWN,
520 CpuABM}
e413e4e9
AM		 521};
522
29b0f896
AM		 523const pseudo_typeS md_pseudo_table[] =
524{
525#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
526 {"align", s_align_bytes, 0},
527#else
528 {"align", s_align_ptwo, 0},
529#endif
530 {"arch", set_cpu_arch, 0},
531#ifndef I386COFF
532 {"bss", s_bss, 0},
533#endif
534 {"ffloat", float_cons, 'f'},
535 {"dfloat", float_cons, 'd'},
536 {"tfloat", float_cons, 'x'},
537 {"value", cons, 2},
d182319b 538 {"slong", signed_cons, 4},
29b0f896
AM		 539 {"noopt", s_ignore, 0},
540 {"optim", s_ignore, 0},
541 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
542 {"code16", set_code_flag, CODE_16BIT},
543 {"code32", set_code_flag, CODE_32BIT},
544 {"code64", set_code_flag, CODE_64BIT},
545 {"intel_syntax", set_intel_syntax, 1},
546 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 547#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
548 {"largecomm", handle_large_common, 0},
07a53e5c 549#else
e3bb37b5 550 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 551 {"loc", dwarf2_directive_loc, 0},
552 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 553#endif
6482c264
NC		 554#ifdef TE_PE
555 {"secrel32", pe_directive_secrel, 0},
556#endif
29b0f896
AM		 557 {0, 0, 0}
558};
559
560/* For interface with expression (). */
561extern char *input_line_pointer;
562
563/* Hash table for instruction mnemonic lookup. */
564static struct hash_control *op_hash;
565
566/* Hash table for register lookup. */
567static struct hash_control *reg_hash;
568\f
252b5132 569void
e3bb37b5 570i386_align_code (fragS *fragP, int count)
252b5132 571{
ce8a8b2f
AM		 572 /* Various efficient no-op patterns for aligning code labels.
573 Note: Don't try to assemble the instructions in the comments.
574 0L and 0w are not legal. */
252b5132
RH		 575 static const char f32_1[] =
576 {0x90}; /* nop */
577 static const char f32_2[] =
ccc9c027 578 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 579 static const char f32_3[] =
580 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
581 static const char f32_4[] =
582 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
583 static const char f32_5[] =
584 {0x90, /* nop */
585 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
586 static const char f32_6[] =
587 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
588 static const char f32_7[] =
589 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
590 static const char f32_8[] =
591 {0x90, /* nop */
592 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
593 static const char f32_9[] =
594 {0x89,0xf6, /* movl %esi,%esi */
595 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
596 static const char f32_10[] =
597 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
598 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
599 static const char f32_11[] =
600 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
601 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
602 static const char f32_12[] =
603 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
604 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
605 static const char f32_13[] =
606 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
607 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
608 static const char f32_14[] =
609 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
610 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 611 static const char f16_3[] =
612 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 613 static const char f16_4[] =
614 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
615 static const char f16_5[] =
616 {0x90, /* nop */
617 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
618 static const char f16_6[] =
619 {0x89,0xf6, /* mov %si,%si */
620 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
621 static const char f16_7[] =
622 {0x8d,0x74,0x00, /* lea 0(%si),%si */
623 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
624 static const char f16_8[] =
625 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
626 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 627 static const char jump_31[] =
628 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
629 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
630 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
631 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 632 static const char *const f32_patt[] = {
633 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 634 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 635 };
636 static const char *const f16_patt[] = {
76bc74dc 637 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 638 };
ccc9c027
L		 639 /* nopl (%[re]ax) */
640 static const char alt_3[] =
641 {0x0f,0x1f,0x00};
642 /* nopl 0(%[re]ax) */
643 static const char alt_4[] =
644 {0x0f,0x1f,0x40,0x00};
645 /* nopl 0(%[re]ax,%[re]ax,1) */
646 static const char alt_5[] =
647 {0x0f,0x1f,0x44,0x00,0x00};
648 /* nopw 0(%[re]ax,%[re]ax,1) */
649 static const char alt_6[] =
650 {0x66,0x0f,0x1f,0x44,0x00,0x00};
651 /* nopl 0L(%[re]ax) */
652 static const char alt_7[] =
653 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
654 /* nopl 0L(%[re]ax,%[re]ax,1) */
655 static const char alt_8[] =
656 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
657 /* nopw 0L(%[re]ax,%[re]ax,1) */
658 static const char alt_9[] =
659 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
660 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
661 static const char alt_10[] =
662 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
663 /* data16
664 nopw %cs:0L(%[re]ax,%[re]ax,1) */
665 static const char alt_long_11[] =
666 {0x66,
667 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
668 /* data16
669 data16
670 nopw %cs:0L(%[re]ax,%[re]ax,1) */
671 static const char alt_long_12[] =
672 {0x66,
673 0x66,
674 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
675 /* data16
676 data16
677 data16
678 nopw %cs:0L(%[re]ax,%[re]ax,1) */
679 static const char alt_long_13[] =
680 {0x66,
681 0x66,
682 0x66,
683 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
684 /* data16
685 data16
686 data16
687 data16
688 nopw %cs:0L(%[re]ax,%[re]ax,1) */
689 static const char alt_long_14[] =
690 {0x66,
691 0x66,
692 0x66,
693 0x66,
694 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
695 /* data16
696 data16
697 data16
698 data16
699 data16
700 nopw %cs:0L(%[re]ax,%[re]ax,1) */
701 static const char alt_long_15[] =
702 {0x66,
703 0x66,
704 0x66,
705 0x66,
706 0x66,
707 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
708 /* nopl 0(%[re]ax,%[re]ax,1)
709 nopw 0(%[re]ax,%[re]ax,1) */
710 static const char alt_short_11[] =
711 {0x0f,0x1f,0x44,0x00,0x00,
712 0x66,0x0f,0x1f,0x44,0x00,0x00};
713 /* nopw 0(%[re]ax,%[re]ax,1)
714 nopw 0(%[re]ax,%[re]ax,1) */
715 static const char alt_short_12[] =
716 {0x66,0x0f,0x1f,0x44,0x00,0x00,
717 0x66,0x0f,0x1f,0x44,0x00,0x00};
718 /* nopw 0(%[re]ax,%[re]ax,1)
719 nopl 0L(%[re]ax) */
720 static const char alt_short_13[] =
721 {0x66,0x0f,0x1f,0x44,0x00,0x00,
722 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
723 /* nopl 0L(%[re]ax)
724 nopl 0L(%[re]ax) */
725 static const char alt_short_14[] =
726 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
727 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
728 /* nopl 0L(%[re]ax)
729 nopl 0L(%[re]ax,%[re]ax,1) */
730 static const char alt_short_15[] =
731 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
732 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
733 static const char *const alt_short_patt[] = {
734 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
735 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
736 alt_short_14, alt_short_15
737 };
738 static const char *const alt_long_patt[] = {
739 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
740 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
741 alt_long_14, alt_long_15
742 };
252b5132 743
76bc74dc
L		 744 /* Only align for at least a positive non-zero boundary. */
745 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 746 return;
3e73aa7c 747
ccc9c027
L		 748 /* We need to decide which NOP sequence to use for 32bit and
749 64bit. When -mtune= is used:
4eed87de 750
76bc74dc
L		 751 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
752 PROCESSOR_GENERIC32, f32_patt will be used.
753 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
754 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
755 alt_long_patt will be used.
756 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
757 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 758
76bc74dc
L		 759 When -mtune= isn't used, alt_long_patt will be used if
760 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
761 be used.
ccc9c027
L		 762
763 When -march= or .arch is used, we can't use anything beyond
764 cpu_arch_isa_flags. */
765
766 if (flag_code == CODE_16BIT)
767 {
ccc9c027 768 if (count > 8)
33fef721 769 {
76bc74dc
L		 770 memcpy (fragP->fr_literal + fragP->fr_fix,
771 jump_31, count);
772 /* Adjust jump offset. */
773 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 774 }
76bc74dc
L		 775 else
776 memcpy (fragP->fr_literal + fragP->fr_fix,
777 f16_patt[count - 1], count);
252b5132 778 }
33fef721 779 else
ccc9c027
L		 780 {
781 const char *const *patt = NULL;
782
783 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
784 {
785 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
786 switch (cpu_arch_tune)
787 {
788 case PROCESSOR_UNKNOWN:
789 /* We use cpu_arch_isa_flags to check if we SHOULD
790 optimize for Cpu686. */
791 if ((cpu_arch_isa_flags & Cpu686) != 0)
76bc74dc 792 patt = alt_long_patt;
ccc9c027
L		 793 else
794 patt = f32_patt;
795 break;
ccc9c027
L		 796 case PROCESSOR_PENTIUMPRO:
797 case PROCESSOR_PENTIUM4:
798 case PROCESSOR_NOCONA:
ef05d495 799 case PROCESSOR_CORE:
76bc74dc
L		 800 case PROCESSOR_CORE2:
801 case PROCESSOR_GENERIC64:
802 patt = alt_long_patt;
803 break;
ccc9c027
L		 804 case PROCESSOR_K6:
805 case PROCESSOR_ATHLON:
806 case PROCESSOR_K8:
4eed87de 807 case PROCESSOR_AMDFAM10:
ccc9c027
L		 808 patt = alt_short_patt;
809 break;
76bc74dc 810 case PROCESSOR_I386:
ccc9c027
L		 811 case PROCESSOR_I486:
812 case PROCESSOR_PENTIUM:
813 case PROCESSOR_GENERIC32:
814 patt = f32_patt;
815 break;
4eed87de 816 }
ccc9c027
L		 817 }
818 else
819 {
820 switch (cpu_arch_tune)
821 {
822 case PROCESSOR_UNKNOWN:
823 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
824 PROCESSOR_UNKNOWN. */
825 abort ();
826 break;
827
76bc74dc 828 case PROCESSOR_I386:
ccc9c027
L		 829 case PROCESSOR_I486:
830 case PROCESSOR_PENTIUM:
ccc9c027
L		 831 case PROCESSOR_K6:
832 case PROCESSOR_ATHLON:
833 case PROCESSOR_K8:
4eed87de 834 case PROCESSOR_AMDFAM10:
ccc9c027
L		 835 case PROCESSOR_GENERIC32:
836 /* We use cpu_arch_isa_flags to check if we CAN optimize
837 for Cpu686. */
838 if ((cpu_arch_isa_flags & Cpu686) != 0)
839 patt = alt_short_patt;
840 else
841 patt = f32_patt;
842 break;
76bc74dc
L		 843 case PROCESSOR_PENTIUMPRO:
844 case PROCESSOR_PENTIUM4:
845 case PROCESSOR_NOCONA:
846 case PROCESSOR_CORE:
ef05d495 847 case PROCESSOR_CORE2:
ccc9c027
L		 848 if ((cpu_arch_isa_flags & Cpu686) != 0)
849 patt = alt_long_patt;
850 else
851 patt = f32_patt;
852 break;
853 case PROCESSOR_GENERIC64:
76bc74dc 854 patt = alt_long_patt;
ccc9c027 855 break;
4eed87de 856 }
ccc9c027
L		 857 }
858
76bc74dc
L		 859 if (patt == f32_patt)
860 {
861 /* If the padding is less than 15 bytes, we use the normal
862 ones. Otherwise, we use a jump instruction and adjust
863 its offset. */
864 if (count < 15)
865 memcpy (fragP->fr_literal + fragP->fr_fix,
866 patt[count - 1], count);
867 else
868 {
869 memcpy (fragP->fr_literal + fragP->fr_fix,
870 jump_31, count);
871 /* Adjust jump offset. */
872 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
873 }
874 }
875 else
876 {
877 /* Maximum length of an instruction is 15 byte. If the
878 padding is greater than 15 bytes and we don't use jump,
879 we have to break it into smaller pieces. */
880 int padding = count;
881 while (padding > 15)
882 {
883 padding -= 15;
884 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
885 patt [14], 15);
886 }
887
888 if (padding)
889 memcpy (fragP->fr_literal + fragP->fr_fix,
890 patt [padding - 1], padding);
891 }
ccc9c027 892 }
33fef721 893 fragP->fr_var = count;
252b5132
RH		 894}
895
252b5132 896static INLINE unsigned int
e3bb37b5 897mode_from_disp_size (unsigned int t)
252b5132 898{
3e73aa7c 899 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 900}
901
902static INLINE int
e3bb37b5 903fits_in_signed_byte (offsetT num)
252b5132
RH		 904{
905 return (num >= -128) && (num <= 127);
47926f60 906}
252b5132
RH		 907
908static INLINE int
e3bb37b5 909fits_in_unsigned_byte (offsetT num)
252b5132
RH		 910{
911 return (num & 0xff) == num;
47926f60 912}
252b5132
RH		 913
914static INLINE int
e3bb37b5 915fits_in_unsigned_word (offsetT num)
252b5132
RH		 916{
917 return (num & 0xffff) == num;
47926f60 918}
252b5132
RH		 919
920static INLINE int
e3bb37b5 921fits_in_signed_word (offsetT num)
252b5132
RH		 922{
923 return (-32768 <= num) && (num <= 32767);
47926f60 924}
2a962e6d 925
3e73aa7c 926static INLINE int
e3bb37b5 927fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 928{
929#ifndef BFD64
930 return 1;
931#else
932 return (!(((offsetT) -1 << 31) & num)
933 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
934#endif
935} /* fits_in_signed_long() */
2a962e6d 936
3e73aa7c 937static INLINE int
e3bb37b5 938fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 939{
940#ifndef BFD64
941 return 1;
942#else
943 return (num & (((offsetT) 2 << 31) - 1)) == num;
944#endif
945} /* fits_in_unsigned_long() */
252b5132 946
1509aa9a 947static unsigned int
e3bb37b5 948smallest_imm_type (offsetT num)
252b5132 949{
d32cad65 950 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 951 {
952 /* This code is disabled on the 486 because all the Imm1 forms
953 in the opcode table are slower on the i486. They're the
954 versions with the implicitly specified single-position
955 displacement, which has another syntax if you really want to
956 use that form. */
957 if (num == 1)
3e73aa7c 958 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 959 }
252b5132 960 return (fits_in_signed_byte (num)
3e73aa7c 961 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 962 : fits_in_unsigned_byte (num)
3e73aa7c 963 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 964 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 965 ? (Imm16 | Imm32 | Imm32S | Imm64)
966 : fits_in_signed_long (num)
967 ? (Imm32 | Imm32S | Imm64)
968 : fits_in_unsigned_long (num)
969 ? (Imm32 | Imm64)
970 : Imm64);
47926f60 971}
252b5132 972
847f7ad4 973static offsetT
e3bb37b5 974offset_in_range (offsetT val, int size)
847f7ad4 975{
508866be 976 addressT mask;
ba2adb93 977
847f7ad4
AM		 978 switch (size)
979 {
508866be
L		 980 case 1: mask = ((addressT) 1 << 8) - 1; break;
981 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 982 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 983#ifdef BFD64
984 case 8: mask = ((addressT) 2 << 63) - 1; break;
985#endif
47926f60 986 default: abort ();
847f7ad4
AM		 987 }
988
ba2adb93 989 /* If BFD64, sign extend val. */
3e73aa7c
JH		 990 if (!use_rela_relocations)
991 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
992 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 993
47926f60 994 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 995 {
996 char buf1[40], buf2[40];
997
998 sprint_value (buf1, val);
999 sprint_value (buf2, val & mask);
1000 as_warn (_("%s shortened to %s"), buf1, buf2);
1001 }
1002 return val & mask;
1003}
1004
252b5132
RH		 1005/* Returns 0 if attempting to add a prefix where one from the same
1006 class already exists, 1 if non rep/repne added, 2 if rep/repne
1007 added. */
1008static int
e3bb37b5 1009add_prefix (unsigned int prefix)
252b5132
RH		 1010{
1011 int ret = 1;
b1905489 1012 unsigned int q;
252b5132 1013
29b0f896
AM		 1014 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1015 && flag_code == CODE_64BIT)
b1905489 1016 {
161a04f6
L		 1017 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1018 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1019 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1020 ret = 0;
1021 q = REX_PREFIX;
1022 }
3e73aa7c 1023 else
b1905489
JB		 1024 {
1025 switch (prefix)
1026 {
1027 default:
1028 abort ();
1029
1030 case CS_PREFIX_OPCODE:
1031 case DS_PREFIX_OPCODE:
1032 case ES_PREFIX_OPCODE:
1033 case FS_PREFIX_OPCODE:
1034 case GS_PREFIX_OPCODE:
1035 case SS_PREFIX_OPCODE:
1036 q = SEG_PREFIX;
1037 break;
1038
1039 case REPNE_PREFIX_OPCODE:
1040 case REPE_PREFIX_OPCODE:
1041 ret = 2;
1042 /* fall thru */
1043 case LOCK_PREFIX_OPCODE:
1044 q = LOCKREP_PREFIX;
1045 break;
1046
1047 case FWAIT_OPCODE:
1048 q = WAIT_PREFIX;
1049 break;
1050
1051 case ADDR_PREFIX_OPCODE:
1052 q = ADDR_PREFIX;
1053 break;
1054
1055 case DATA_PREFIX_OPCODE:
1056 q = DATA_PREFIX;
1057 break;
1058 }
1059 if (i.prefix[q] != 0)
1060 ret = 0;
1061 }
252b5132 1062
b1905489 1063 if (ret)
252b5132 1064 {
b1905489
JB		 1065 if (!i.prefix[q])
1066 ++i.prefixes;
1067 i.prefix[q] |= prefix;
252b5132 1068 }
b1905489
JB		 1069 else
1070 as_bad (_("same type of prefix used twice"));
252b5132 1071
252b5132
RH		 1072 return ret;
1073}
1074
1075static void
e3bb37b5 1076set_code_flag (int value)
eecb386c 1077{
3e73aa7c
JH		 1078 flag_code = value;
1079 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1080 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1081 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1082 {
1083 as_bad (_("64bit mode not supported on this CPU."));
1084 }
1085 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1086 {
1087 as_bad (_("32bit mode not supported on this CPU."));
1088 }
eecb386c
AM		 1089 stackop_size = '\0';
1090}
1091
1092static void
e3bb37b5 1093set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1094{
3e73aa7c
JH		 1095 flag_code = new_code_flag;
1096 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1097 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 1098 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1099}
1100
1101static void
e3bb37b5 1102set_intel_syntax (int syntax_flag)
252b5132
RH		 1103{
1104 /* Find out if register prefixing is specified. */
1105 int ask_naked_reg = 0;
1106
1107 SKIP_WHITESPACE ();
29b0f896 1108 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1109 {
1110 char *string = input_line_pointer;
1111 int e = get_symbol_end ();
1112
47926f60 1113 if (strcmp (string, "prefix") == 0)
252b5132 1114 ask_naked_reg = 1;
47926f60 1115 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1116 ask_naked_reg = -1;
1117 else
d0b47220 1118 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1119 *input_line_pointer = e;
1120 }
1121 demand_empty_rest_of_line ();
c3332e24 1122
252b5132
RH		 1123 intel_syntax = syntax_flag;
1124
1125 if (ask_naked_reg == 0)
f86103b7
AM		 1126 allow_naked_reg = (intel_syntax
1127 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1128 else
1129 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1130
e4a3b5a4 1131 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1132 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1133 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1134}
1135
e413e4e9 1136static void
e3bb37b5 1137set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1138{
47926f60 1139 SKIP_WHITESPACE ();
e413e4e9 1140
29b0f896 1141 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1142 {
1143 char *string = input_line_pointer;
1144 int e = get_symbol_end ();
9103f4f4 1145 unsigned int i;
e413e4e9 1146
9103f4f4 1147 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1148 {
1149 if (strcmp (string, cpu_arch[i].name) == 0)
1150 {
5c6af06e
JB		 1151 if (*string != '.')
1152 {
1153 cpu_arch_name = cpu_arch[i].name;
1154 cpu_sub_arch_name = NULL;
1155 cpu_arch_flags = (cpu_arch[i].flags
4eed87de
AM		 1156 | (flag_code == CODE_64BIT
1157 ? Cpu64 : CpuNo64));
ccc9c027 1158 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1159 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1160 if (!cpu_arch_tune_set)
1161 {
1162 cpu_arch_tune = cpu_arch_isa;
1163 cpu_arch_tune_flags = cpu_arch_isa_flags;
1164 }
5c6af06e
JB		 1165 break;
1166 }
1167 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1168 {
1169 cpu_sub_arch_name = cpu_arch[i].name;
1170 cpu_arch_flags |= cpu_arch[i].flags;
1171 }
1172 *input_line_pointer = e;
1173 demand_empty_rest_of_line ();
1174 return;
e413e4e9
AM		 1175 }
1176 }
9103f4f4 1177 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1178 as_bad (_("no such architecture: `%s'"), string);
1179
1180 *input_line_pointer = e;
1181 }
1182 else
1183 as_bad (_("missing cpu architecture"));
1184
fddf5b5b
AM		 1185 no_cond_jump_promotion = 0;
1186 if (*input_line_pointer == ','
29b0f896 1187 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1188 {
1189 char *string = ++input_line_pointer;
1190 int e = get_symbol_end ();
1191
1192 if (strcmp (string, "nojumps") == 0)
1193 no_cond_jump_promotion = 1;
1194 else if (strcmp (string, "jumps") == 0)
1195 ;
1196 else
1197 as_bad (_("no such architecture modifier: `%s'"), string);
1198
1199 *input_line_pointer = e;
1200 }
1201
e413e4e9
AM		 1202 demand_empty_rest_of_line ();
1203}
1204
b9d79e03
JH		 1205unsigned long
1206i386_mach ()
1207{
1208 if (!strcmp (default_arch, "x86_64"))
1209 return bfd_mach_x86_64;
1210 else if (!strcmp (default_arch, "i386"))
1211 return bfd_mach_i386_i386;
1212 else
1213 as_fatal (_("Unknown architecture"));
1214}
b9d79e03 1215\f
252b5132
RH		 1216void
1217md_begin ()
1218{
1219 const char *hash_err;
1220
47926f60 1221 /* Initialize op_hash hash table. */
252b5132
RH		 1222 op_hash = hash_new ();
1223
1224 {
29b0f896
AM		 1225 const template *optab;
1226 templates *core_optab;
252b5132 1227
47926f60
KH		 1228 /* Setup for loop. */
1229 optab = i386_optab;
252b5132
RH		 1230 core_optab = (templates *) xmalloc (sizeof (templates));
1231 core_optab->start = optab;
1232
1233 while (1)
1234 {
1235 ++optab;
1236 if (optab->name == NULL
1237 || strcmp (optab->name, (optab - 1)->name) != 0)
1238 {
1239 /* different name --> ship out current template list;
47926f60 1240 add to hash table; & begin anew. */
252b5132
RH		 1241 core_optab->end = optab;
1242 hash_err = hash_insert (op_hash,
1243 (optab - 1)->name,
1244 (PTR) core_optab);
1245 if (hash_err)
1246 {
252b5132
RH		 1247 as_fatal (_("Internal Error: Can't hash %s: %s"),
1248 (optab - 1)->name,
1249 hash_err);
1250 }
1251 if (optab->name == NULL)
1252 break;
1253 core_optab = (templates *) xmalloc (sizeof (templates));
1254 core_optab->start = optab;
1255 }
1256 }
1257 }
1258
47926f60 1259 /* Initialize reg_hash hash table. */
252b5132
RH		 1260 reg_hash = hash_new ();
1261 {
29b0f896 1262 const reg_entry *regtab;
c3fe08fa 1263 unsigned int regtab_size = i386_regtab_size;
252b5132 1264
c3fe08fa 1265 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1266 {
1267 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1268 if (hash_err)
3e73aa7c
JH		 1269 as_fatal (_("Internal Error: Can't hash %s: %s"),
1270 regtab->reg_name,
1271 hash_err);
252b5132
RH		 1272 }
1273 }
1274
47926f60 1275 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1276 {
29b0f896
AM		 1277 int c;
1278 char *p;
252b5132
RH		 1279
1280 for (c = 0; c < 256; c++)
1281 {
3882b010 1282 if (ISDIGIT (c))
252b5132
RH		 1283 {
1284 digit_chars[c] = c;
1285 mnemonic_chars[c] = c;
1286 register_chars[c] = c;
1287 operand_chars[c] = c;
1288 }
3882b010 1289 else if (ISLOWER (c))
252b5132
RH		 1290 {
1291 mnemonic_chars[c] = c;
1292 register_chars[c] = c;
1293 operand_chars[c] = c;
1294 }
3882b010 1295 else if (ISUPPER (c))
252b5132 1296 {
3882b010 1297 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1298 register_chars[c] = mnemonic_chars[c];
1299 operand_chars[c] = c;
1300 }
1301
3882b010 1302 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1303 identifier_chars[c] = c;
1304 else if (c >= 128)
1305 {
1306 identifier_chars[c] = c;
1307 operand_chars[c] = c;
1308 }
1309 }
1310
1311#ifdef LEX_AT
1312 identifier_chars['@'] = '@';
32137342
NC		 1313#endif
1314#ifdef LEX_QM
1315 identifier_chars['?'] = '?';
1316 operand_chars['?'] = '?';
252b5132 1317#endif
252b5132 1318 digit_chars['-'] = '-';
791fe849 1319 mnemonic_chars['-'] = '-';
0003779b 1320 mnemonic_chars['.'] = '.';
252b5132
RH		 1321 identifier_chars['_'] = '_';
1322 identifier_chars['.'] = '.';
1323
1324 for (p = operand_special_chars; *p != '\0'; p++)
1325 operand_chars[(unsigned char) *p] = *p;
1326 }
1327
1328#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1329 if (IS_ELF)
252b5132
RH		 1330 {
1331 record_alignment (text_section, 2);
1332 record_alignment (data_section, 2);
1333 record_alignment (bss_section, 2);
1334 }
1335#endif
a4447b93
RH		 1336
1337 if (flag_code == CODE_64BIT)
1338 {
1339 x86_dwarf2_return_column = 16;
1340 x86_cie_data_alignment = -8;
1341 }
1342 else
1343 {
1344 x86_dwarf2_return_column = 8;
1345 x86_cie_data_alignment = -4;
1346 }
252b5132
RH		 1347}
1348
1349void
e3bb37b5 1350i386_print_statistics (FILE *file)
252b5132
RH		 1351{
1352 hash_print_statistics (file, "i386 opcode", op_hash);
1353 hash_print_statistics (file, "i386 register", reg_hash);
1354}
1355\f
252b5132
RH		 1356#ifdef DEBUG386
1357
ce8a8b2f 1358/* Debugging routines for md_assemble. */
e3bb37b5
L		 1359static void pte (template *);
1360static void pt (unsigned int);
1361static void pe (expressionS *);
1362static void ps (symbolS *);
252b5132
RH		 1363
1364static void
e3bb37b5 1365pi (char *line, i386_insn *x)
252b5132 1366{
09f131f2 1367 unsigned int i;
252b5132
RH		 1368
1369 fprintf (stdout, "%s: template ", line);
1370 pte (&x->tm);
09f131f2
JH		 1371 fprintf (stdout, " address: base %s index %s scale %x\n",
1372 x->base_reg ? x->base_reg->reg_name : "none",
1373 x->index_reg ? x->index_reg->reg_name : "none",
1374 x->log2_scale_factor);
1375 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1376 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1377 fprintf (stdout, " sib: base %x index %x scale %x\n",
1378 x->sib.base, x->sib.index, x->sib.scale);
1379 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 1380 (x->rex & REX_W) != 0,
1381 (x->rex & REX_R) != 0,
1382 (x->rex & REX_X) != 0,
1383 (x->rex & REX_B) != 0);
252b5132
RH		 1384 for (i = 0; i < x->operands; i++)
1385 {
1386 fprintf (stdout, " #%d: ", i + 1);
1387 pt (x->types[i]);
1388 fprintf (stdout, "\n");
1389 if (x->types[i]
3f4438ab 1390 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1391 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1392 if (x->types[i] & Imm)
520dc8e8 1393 pe (x->op[i].imms);
252b5132 1394 if (x->types[i] & Disp)
520dc8e8 1395 pe (x->op[i].disps);
252b5132
RH		 1396 }
1397}
1398
1399static void
e3bb37b5 1400pte (template *t)
252b5132 1401{
09f131f2 1402 unsigned int i;
252b5132 1403 fprintf (stdout, " %d operands ", t->operands);
47926f60 1404 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1405 if (t->extension_opcode != None)
1406 fprintf (stdout, "ext %x ", t->extension_opcode);
1407 if (t->opcode_modifier & D)
1408 fprintf (stdout, "D");
1409 if (t->opcode_modifier & W)
1410 fprintf (stdout, "W");
1411 fprintf (stdout, "\n");
1412 for (i = 0; i < t->operands; i++)
1413 {
1414 fprintf (stdout, " #%d type ", i + 1);
1415 pt (t->operand_types[i]);
1416 fprintf (stdout, "\n");
1417 }
1418}
1419
1420static void
e3bb37b5 1421pe (expressionS *e)
252b5132 1422{
24eab124 1423 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1424 fprintf (stdout, " add_number %ld (%lx)\n",
1425 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1426 if (e->X_add_symbol)
1427 {
1428 fprintf (stdout, " add_symbol ");
1429 ps (e->X_add_symbol);
1430 fprintf (stdout, "\n");
1431 }
1432 if (e->X_op_symbol)
1433 {
1434 fprintf (stdout, " op_symbol ");
1435 ps (e->X_op_symbol);
1436 fprintf (stdout, "\n");
1437 }
1438}
1439
1440static void
e3bb37b5 1441ps (symbolS *s)
252b5132
RH		 1442{
1443 fprintf (stdout, "%s type %s%s",
1444 S_GET_NAME (s),
1445 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1446 segment_name (S_GET_SEGMENT (s)));
1447}
1448
7b81dfbb 1449static struct type_name
252b5132
RH		 1450 {
1451 unsigned int mask;
1452 char *tname;
1453 }
7b81dfbb 1454const type_names[] =
252b5132
RH		 1455{
1456 { Reg8, "r8" },
1457 { Reg16, "r16" },
1458 { Reg32, "r32" },
09f131f2 1459 { Reg64, "r64" },
252b5132
RH		 1460 { Imm8, "i8" },
1461 { Imm8S, "i8s" },
1462 { Imm16, "i16" },
1463 { Imm32, "i32" },
09f131f2
JH		 1464 { Imm32S, "i32s" },
1465 { Imm64, "i64" },
252b5132
RH		 1466 { Imm1, "i1" },
1467 { BaseIndex, "BaseIndex" },
1468 { Disp8, "d8" },
1469 { Disp16, "d16" },
1470 { Disp32, "d32" },
09f131f2
JH		 1471 { Disp32S, "d32s" },
1472 { Disp64, "d64" },
252b5132
RH		 1473 { InOutPortReg, "InOutPortReg" },
1474 { ShiftCount, "ShiftCount" },
1475 { Control, "control reg" },
1476 { Test, "test reg" },
1477 { Debug, "debug reg" },
1478 { FloatReg, "FReg" },
1479 { FloatAcc, "FAcc" },
1480 { SReg2, "SReg2" },
1481 { SReg3, "SReg3" },
1482 { Acc, "Acc" },
1483 { JumpAbsolute, "Jump Absolute" },
1484 { RegMMX, "rMMX" },
3f4438ab 1485 { RegXMM, "rXMM" },
252b5132
RH		 1486 { EsSeg, "es" },
1487 { 0, "" }
1488};
1489
1490static void
1491pt (t)
1492 unsigned int t;
1493{
29b0f896 1494 const struct type_name *ty;
252b5132 1495
09f131f2
JH		 1496 for (ty = type_names; ty->mask; ty++)
1497 if (t & ty->mask)
1498 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1499 fflush (stdout);
1500}
1501
1502#endif /* DEBUG386 */
1503\f
252b5132 1504static bfd_reloc_code_real_type
3956db08 1505reloc (unsigned int size,
64e74474
AM		 1506 int pcrel,
1507 int sign,
1508 bfd_reloc_code_real_type other)
252b5132 1509{
47926f60 1510 if (other != NO_RELOC)
3956db08
JB		 1511 {
1512 reloc_howto_type *reloc;
1513
1514 if (size == 8)
1515 switch (other)
1516 {
64e74474
AM		 1517 case BFD_RELOC_X86_64_GOT32:
1518 return BFD_RELOC_X86_64_GOT64;
1519 break;
1520 case BFD_RELOC_X86_64_PLTOFF64:
1521 return BFD_RELOC_X86_64_PLTOFF64;
1522 break;
1523 case BFD_RELOC_X86_64_GOTPC32:
1524 other = BFD_RELOC_X86_64_GOTPC64;
1525 break;
1526 case BFD_RELOC_X86_64_GOTPCREL:
1527 other = BFD_RELOC_X86_64_GOTPCREL64;
1528 break;
1529 case BFD_RELOC_X86_64_TPOFF32:
1530 other = BFD_RELOC_X86_64_TPOFF64;
1531 break;
1532 case BFD_RELOC_X86_64_DTPOFF32:
1533 other = BFD_RELOC_X86_64_DTPOFF64;
1534 break;
1535 default:
1536 break;
3956db08 1537 }
e05278af
JB		 1538
1539 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1540 if (size == 4 && flag_code != CODE_64BIT)
1541 sign = -1;
1542
3956db08
JB		 1543 reloc = bfd_reloc_type_lookup (stdoutput, other);
1544 if (!reloc)
1545 as_bad (_("unknown relocation (%u)"), other);
1546 else if (size != bfd_get_reloc_size (reloc))
1547 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1548 bfd_get_reloc_size (reloc),
1549 size);
1550 else if (pcrel && !reloc->pc_relative)
1551 as_bad (_("non-pc-relative relocation for pc-relative field"));
1552 else if ((reloc->complain_on_overflow == complain_overflow_signed
1553 && !sign)
1554 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1555 && sign > 0))
3956db08
JB		 1556 as_bad (_("relocated field and relocation type differ in signedness"));
1557 else
1558 return other;
1559 return NO_RELOC;
1560 }
252b5132
RH		 1561
1562 if (pcrel)
1563 {
3e73aa7c 1564 if (!sign)
3956db08 1565 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1566 switch (size)
1567 {
1568 case 1: return BFD_RELOC_8_PCREL;
1569 case 2: return BFD_RELOC_16_PCREL;
1570 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1571 case 8: return BFD_RELOC_64_PCREL;
252b5132 1572 }
3956db08 1573 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1574 }
1575 else
1576 {
3956db08 1577 if (sign > 0)
e5cb08ac 1578 switch (size)
3e73aa7c
JH		 1579 {
1580 case 4: return BFD_RELOC_X86_64_32S;
1581 }
1582 else
1583 switch (size)
1584 {
1585 case 1: return BFD_RELOC_8;
1586 case 2: return BFD_RELOC_16;
1587 case 4: return BFD_RELOC_32;
1588 case 8: return BFD_RELOC_64;
1589 }
3956db08
JB		 1590 as_bad (_("cannot do %s %u byte relocation"),
1591 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1592 }
1593
bfb32b52 1594 abort ();
252b5132
RH		 1595 return BFD_RELOC_NONE;
1596}
1597
47926f60
KH		 1598/* Here we decide which fixups can be adjusted to make them relative to
1599 the beginning of the section instead of the symbol. Basically we need
1600 to make sure that the dynamic relocations are done correctly, so in
1601 some cases we force the original symbol to be used. */
1602
252b5132 1603int
e3bb37b5 1604tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 1605{
6d249963 1606#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1607 if (!IS_ELF)
31312f95
AM		 1608 return 1;
1609
a161fe53
AM		 1610 /* Don't adjust pc-relative references to merge sections in 64-bit
1611 mode. */
1612 if (use_rela_relocations
1613 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1614 && fixP->fx_pcrel)
252b5132 1615 return 0;
31312f95 1616
8d01d9a9
AJ		 1617 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1618 and changed later by validate_fix. */
1619 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1620 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1621 return 0;
1622
ce8a8b2f 1623 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1624 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1625 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1626 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1627 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1628 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1629 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1630 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1631 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1632 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1633 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1634 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1635 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1636 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1637 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1638 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1639 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1640 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1641 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1642 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1643 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1644 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1645 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1646 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1647 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1648 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1649 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1650 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1651 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1652 return 0;
31312f95 1653#endif
252b5132
RH		 1654 return 1;
1655}
252b5132 1656
b4cac588 1657static int
e3bb37b5 1658intel_float_operand (const char *mnemonic)
252b5132 1659{
9306ca4a
JB		 1660 /* Note that the value returned is meaningful only for opcodes with (memory)
1661 operands, hence the code here is free to improperly handle opcodes that
1662 have no operands (for better performance and smaller code). */
1663
1664 if (mnemonic[0] != 'f')
1665 return 0; /* non-math */
1666
1667 switch (mnemonic[1])
1668 {
1669 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1670 the fs segment override prefix not currently handled because no
1671 call path can make opcodes without operands get here */
1672 case 'i':
1673 return 2 /* integer op */;
1674 case 'l':
1675 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1676 return 3; /* fldcw/fldenv */
1677 break;
1678 case 'n':
1679 if (mnemonic[2] != 'o' /* fnop */)
1680 return 3; /* non-waiting control op */
1681 break;
1682 case 'r':
1683 if (mnemonic[2] == 's')
1684 return 3; /* frstor/frstpm */
1685 break;
1686 case 's':
1687 if (mnemonic[2] == 'a')
1688 return 3; /* fsave */
1689 if (mnemonic[2] == 't')
1690 {
1691 switch (mnemonic[3])
1692 {
1693 case 'c': /* fstcw */
1694 case 'd': /* fstdw */
1695 case 'e': /* fstenv */
1696 case 's': /* fsts[gw] */
1697 return 3;
1698 }
1699 }
1700 break;
1701 case 'x':
1702 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1703 return 0; /* fxsave/fxrstor are not really math ops */
1704 break;
1705 }
252b5132 1706
9306ca4a 1707 return 1;
252b5132
RH		 1708}
1709
1710/* This is the guts of the machine-dependent assembler. LINE points to a
1711 machine dependent instruction. This function is supposed to emit
1712 the frags/bytes it assembles to. */
1713
1714void
1715md_assemble (line)
1716 char *line;
1717{
252b5132 1718 int j;
252b5132
RH		 1719 char mnemonic[MAX_MNEM_SIZE];
1720
47926f60 1721 /* Initialize globals. */
252b5132
RH		 1722 memset (&i, '\0', sizeof (i));
1723 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1724 i.reloc[j] = NO_RELOC;
252b5132
RH		 1725 memset (disp_expressions, '\0', sizeof (disp_expressions));
1726 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1727 save_stack_p = save_stack;
252b5132
RH		 1728
1729 /* First parse an instruction mnemonic & call i386_operand for the operands.
1730 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1731 start of a (possibly prefixed) mnemonic. */
252b5132 1732
29b0f896
AM		 1733 line = parse_insn (line, mnemonic);
1734 if (line == NULL)
1735 return;
252b5132 1736
29b0f896
AM		 1737 line = parse_operands (line, mnemonic);
1738 if (line == NULL)
1739 return;
252b5132 1740
4eed87de 1741 /* The order of the immediates should be reversed
050dfa73 1742 for 2 immediates extrq and insertq instructions */
4d456e3d
L		 1743 if ((i.imm_operands == 2)
1744 && ((strcmp (mnemonic, "extrq") == 0)
1745 || (strcmp (mnemonic, "insertq") == 0)))
050dfa73 1746 {
4eed87de
AM		 1747 swap_2_operands (0, 1);
1748 /* "extrq" and insertq" are the only two instructions whose operands
050dfa73
MM		 1749 have to be reversed even though they have two immediate operands.
1750 */
1751 if (intel_syntax)
1752 swap_operands ();
1753 }
1754
29b0f896
AM		 1755 /* Now we've parsed the mnemonic into a set of templates, and have the
1756 operands at hand. */
1757
1758 /* All intel opcodes have reversed operands except for "bound" and
1759 "enter". We also don't reverse intersegment "jmp" and "call"
1760 instructions with 2 immediate operands so that the immediate segment
050dfa73 1761 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 1762 if (intel_syntax
1763 && i.operands > 1
29b0f896 1764 && (strcmp (mnemonic, "bound") != 0)
30123838 1765 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1766 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1767 swap_operands ();
1768
1769 if (i.imm_operands)
1770 optimize_imm ();
1771
b300c311
L		 1772 /* Don't optimize displacement for movabs since it only takes 64bit
1773 displacement. */
1774 if (i.disp_operands
1775 && (flag_code != CODE_64BIT
1776 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1777 optimize_disp ();
1778
1779 /* Next, we find a template that matches the given insn,
1780 making sure the overlap of the given operands types is consistent
1781 with the template operand types. */
252b5132 1782
29b0f896
AM		 1783 if (!match_template ())
1784 return;
252b5132 1785
cd61ebfe
AM		 1786 if (intel_syntax)
1787 {
1788 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1789 if (SYSV386_COMPAT
1790 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
8a2ed489 1791 i.tm.base_opcode ^= Opcode_FloatR;
cd61ebfe
AM		 1792
1793 /* Zap movzx and movsx suffix. The suffix may have been set from
1794 "word ptr" or "byte ptr" on the source operand, but we'll use
1795 the suffix later to choose the destination register. */
1796 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1797 {
1798 if (i.reg_operands < 2
1799 && !i.suffix
1800 && (~i.tm.opcode_modifier
1801 & (No_bSuf
1802 | No_wSuf
1803 | No_lSuf
1804 | No_sSuf
1805 | No_xSuf
1806 | No_qSuf)))
1807 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1808
1809 i.suffix = 0;
1810 }
cd61ebfe 1811 }
24eab124 1812
29b0f896
AM		 1813 if (i.tm.opcode_modifier & FWait)
1814 if (!add_prefix (FWAIT_OPCODE))
1815 return;
252b5132 1816
29b0f896
AM		 1817 /* Check string instruction segment overrides. */
1818 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1819 {
1820 if (!check_string ())
5dd0794d 1821 return;
29b0f896 1822 }
5dd0794d 1823
29b0f896
AM		 1824 if (!process_suffix ())
1825 return;
e413e4e9 1826
29b0f896
AM		 1827 /* Make still unresolved immediate matches conform to size of immediate
1828 given in i.suffix. */
1829 if (!finalize_imm ())
1830 return;
252b5132 1831
29b0f896
AM		 1832 if (i.types[0] & Imm1)
1833 i.imm_operands = 0; /* kludge for shift insns. */
1834 if (i.types[0] & ImplicitRegister)
1835 i.reg_operands--;
1836 if (i.types[1] & ImplicitRegister)
1837 i.reg_operands--;
1838 if (i.types[2] & ImplicitRegister)
1839 i.reg_operands--;
252b5132 1840
29b0f896
AM		 1841 if (i.tm.opcode_modifier & ImmExt)
1842 {
02fc3089
L		 1843 expressionS *exp;
1844
b7d9ef37 1845 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
ca164297 1846 {
b7d9ef37 1847 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 1848 operands with an opcode suffix which is coded in the same
1849 place as an 8-bit immediate field would be. Here we check
1850 those operands and remove them afterwards. */
1851 unsigned int x;
1852
a4622f40 1853 for (x = 0; x < i.operands; x++)
ca164297 1854 if (i.op[x].regs->reg_num != x)
a540244d
L		 1855 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1856 register_prefix,
1857 i.op[x].regs->reg_name,
1858 x + 1,
1859 i.tm.name);
ca164297
L		 1860 i.operands = 0;
1861 }
1862
29b0f896
AM		 1863 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1864 opcode suffix which is coded in the same place as an 8-bit
1865 immediate field would be. Here we fake an 8-bit immediate
1866 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1867
29b0f896 1868 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1869
29b0f896
AM		 1870 exp = &im_expressions[i.imm_operands++];
1871 i.op[i.operands].imms = exp;
1872 i.types[i.operands++] = Imm8;
1873 exp->X_op = O_constant;
1874 exp->X_add_number = i.tm.extension_opcode;
1875 i.tm.extension_opcode = None;
1876 }
252b5132 1877
29b0f896
AM		 1878 /* For insns with operands there are more diddles to do to the opcode. */
1879 if (i.operands)
1880 {
1881 if (!process_operands ())
1882 return;
1883 }
1884 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1885 {
1886 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1887 as_warn (_("translating to `%sp'"), i.tm.name);
1888 }
252b5132 1889
29b0f896
AM		 1890 /* Handle conversion of 'int $3' --> special int3 insn. */
1891 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1892 {
1893 i.tm.base_opcode = INT3_OPCODE;
1894 i.imm_operands = 0;
1895 }
252b5132 1896
29b0f896
AM		 1897 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1898 && i.op[0].disps->X_op == O_constant)
1899 {
1900 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1901 the absolute address given by the constant. Since ix86 jumps and
1902 calls are pc relative, we need to generate a reloc. */
1903 i.op[0].disps->X_add_symbol = &abs_symbol;
1904 i.op[0].disps->X_op = O_symbol;
1905 }
252b5132 1906
29b0f896 1907 if ((i.tm.opcode_modifier & Rex64) != 0)
161a04f6 1908 i.rex |= REX_W;
252b5132 1909
29b0f896
AM		 1910 /* For 8 bit registers we need an empty rex prefix. Also if the
1911 instruction already has a prefix, we need to convert old
1912 registers to new ones. */
773f551c 1913
29b0f896
AM		 1914 if (((i.types[0] & Reg8) != 0
1915 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1916 || ((i.types[1] & Reg8) != 0
1917 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1918 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1919 && i.rex != 0))
1920 {
1921 int x;
726c5dcd 1922
29b0f896
AM		 1923 i.rex |= REX_OPCODE;
1924 for (x = 0; x < 2; x++)
1925 {
1926 /* Look for 8 bit operand that uses old registers. */
1927 if ((i.types[x] & Reg8) != 0
1928 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1929 {
29b0f896
AM		 1930 /* In case it is "hi" register, give up. */
1931 if (i.op[x].regs->reg_num > 3)
a540244d 1932 as_bad (_("can't encode register '%s%s' in an "
4eed87de 1933 "instruction requiring REX prefix."),
a540244d 1934 register_prefix, i.op[x].regs->reg_name);
773f551c 1935
29b0f896
AM		 1936 /* Otherwise it is equivalent to the extended register.
1937 Since the encoding doesn't change this is merely
1938 cosmetic cleanup for debug output. */
1939
1940 i.op[x].regs = i.op[x].regs + 8;
773f551c 1941 }
29b0f896
AM		 1942 }
1943 }
773f551c 1944
29b0f896
AM		 1945 if (i.rex != 0)
1946 add_prefix (REX_OPCODE | i.rex);
1947
1948 /* We are ready to output the insn. */
1949 output_insn ();
1950}
1951
1952static char *
e3bb37b5 1953parse_insn (char *line, char *mnemonic)
29b0f896
AM		 1954{
1955 char *l = line;
1956 char *token_start = l;
1957 char *mnem_p;
5c6af06e
JB		 1958 int supported;
1959 const template *t;
29b0f896
AM		 1960
1961 /* Non-zero if we found a prefix only acceptable with string insns. */
1962 const char *expecting_string_instruction = NULL;
45288df1 1963
29b0f896
AM		 1964 while (1)
1965 {
1966 mnem_p = mnemonic;
1967 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1968 {
1969 mnem_p++;
1970 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1971 {
29b0f896
AM		 1972 as_bad (_("no such instruction: `%s'"), token_start);
1973 return NULL;
1974 }
1975 l++;
1976 }
1977 if (!is_space_char (*l)
1978 && *l != END_OF_INSN
e44823cf
JB		 1979 && (intel_syntax
1980 || (*l != PREFIX_SEPARATOR
1981 && *l != ',')))
29b0f896
AM		 1982 {
1983 as_bad (_("invalid character %s in mnemonic"),
1984 output_invalid (*l));
1985 return NULL;
1986 }
1987 if (token_start == l)
1988 {
e44823cf 1989 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1990 as_bad (_("expecting prefix; got nothing"));
1991 else
1992 as_bad (_("expecting mnemonic; got nothing"));
1993 return NULL;
1994 }
45288df1 1995
29b0f896
AM		 1996 /* Look up instruction (or prefix) via hash table. */
1997 current_templates = hash_find (op_hash, mnemonic);
47926f60 1998
29b0f896
AM		 1999 if (*l != END_OF_INSN
2000 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2001 && current_templates
2002 && (current_templates->start->opcode_modifier & IsPrefix))
2003 {
2dd88dca
JB		 2004 if (current_templates->start->cpu_flags
2005 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
2006 {
2007 as_bad ((flag_code != CODE_64BIT
2008 ? _("`%s' is only supported in 64-bit mode")
2009 : _("`%s' is not supported in 64-bit mode")),
2010 current_templates->start->name);
2011 return NULL;
2012 }
29b0f896
AM		 2013 /* If we are in 16-bit mode, do not allow addr16 or data16.
2014 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2015 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
2016 && flag_code != CODE_64BIT
2017 && (((current_templates->start->opcode_modifier & Size32) != 0)
2018 ^ (flag_code == CODE_16BIT)))
2019 {
2020 as_bad (_("redundant %s prefix"),
2021 current_templates->start->name);
2022 return NULL;
45288df1 2023 }
29b0f896
AM		 2024 /* Add prefix, checking for repeated prefixes. */
2025 switch (add_prefix (current_templates->start->base_opcode))
2026 {
2027 case 0:
2028 return NULL;
2029 case 2:
2030 expecting_string_instruction = current_templates->start->name;
2031 break;
2032 }
2033 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2034 token_start = ++l;
2035 }
2036 else
2037 break;
2038 }
45288df1 2039
29b0f896
AM		 2040 if (!current_templates)
2041 {
2042 /* See if we can get a match by trimming off a suffix. */
2043 switch (mnem_p[-1])
2044 {
2045 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2046 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2047 i.suffix = SHORT_MNEM_SUFFIX;
2048 else
29b0f896
AM		 2049 case BYTE_MNEM_SUFFIX:
2050 case QWORD_MNEM_SUFFIX:
2051 i.suffix = mnem_p[-1];
2052 mnem_p[-1] = '\0';
2053 current_templates = hash_find (op_hash, mnemonic);
2054 break;
2055 case SHORT_MNEM_SUFFIX:
2056 case LONG_MNEM_SUFFIX:
2057 if (!intel_syntax)
2058 {
2059 i.suffix = mnem_p[-1];
2060 mnem_p[-1] = '\0';
2061 current_templates = hash_find (op_hash, mnemonic);
2062 }
2063 break;
252b5132 2064
29b0f896
AM		 2065 /* Intel Syntax. */
2066 case 'd':
2067 if (intel_syntax)
2068 {
9306ca4a 2069 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2070 i.suffix = SHORT_MNEM_SUFFIX;
2071 else
2072 i.suffix = LONG_MNEM_SUFFIX;
2073 mnem_p[-1] = '\0';
2074 current_templates = hash_find (op_hash, mnemonic);
2075 }
2076 break;
2077 }
2078 if (!current_templates)
2079 {
2080 as_bad (_("no such instruction: `%s'"), token_start);
2081 return NULL;
2082 }
2083 }
252b5132 2084
29b0f896
AM		 2085 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2086 {
2087 /* Check for a branch hint. We allow ",pt" and ",pn" for
2088 predict taken and predict not taken respectively.
2089 I'm not sure that branch hints actually do anything on loop
2090 and jcxz insns (JumpByte) for current Pentium4 chips. They
2091 may work in the future and it doesn't hurt to accept them
2092 now. */
2093 if (l[0] == ',' && l[1] == 'p')
2094 {
2095 if (l[2] == 't')
2096 {
2097 if (!add_prefix (DS_PREFIX_OPCODE))
2098 return NULL;
2099 l += 3;
2100 }
2101 else if (l[2] == 'n')
2102 {
2103 if (!add_prefix (CS_PREFIX_OPCODE))
2104 return NULL;
2105 l += 3;
2106 }
2107 }
2108 }
2109 /* Any other comma loses. */
2110 if (*l == ',')
2111 {
2112 as_bad (_("invalid character %s in mnemonic"),
2113 output_invalid (*l));
2114 return NULL;
2115 }
252b5132 2116
29b0f896 2117 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2118 supported = 0;
2119 for (t = current_templates->start; t < current_templates->end; ++t)
2120 {
2121 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2122 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 2123 supported |= 1;
5c6af06e 2124 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 2125 supported |= 2;
5c6af06e
JB		 2126 }
2127 if (!(supported & 2))
2128 {
2129 as_bad (flag_code == CODE_64BIT
2130 ? _("`%s' is not supported in 64-bit mode")
2131 : _("`%s' is only supported in 64-bit mode"),
2132 current_templates->start->name);
2133 return NULL;
2134 }
2135 if (!(supported & 1))
29b0f896 2136 {
5c6af06e
JB		 2137 as_warn (_("`%s' is not supported on `%s%s'"),
2138 current_templates->start->name,
2139 cpu_arch_name,
2140 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 2141 }
2142 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2143 {
2144 as_warn (_("use .code16 to ensure correct addressing mode"));
2145 }
252b5132 2146
29b0f896 2147 /* Check for rep/repne without a string instruction. */
f41bbced 2148 if (expecting_string_instruction)
29b0f896 2149 {
f41bbced
JB		 2150 static templates override;
2151
2152 for (t = current_templates->start; t < current_templates->end; ++t)
2153 if (t->opcode_modifier & IsString)
2154 break;
2155 if (t >= current_templates->end)
2156 {
2157 as_bad (_("expecting string instruction after `%s'"),
64e74474 2158 expecting_string_instruction);
f41bbced
JB		 2159 return NULL;
2160 }
2161 for (override.start = t; t < current_templates->end; ++t)
2162 if (!(t->opcode_modifier & IsString))
2163 break;
2164 override.end = t;
2165 current_templates = &override;
29b0f896 2166 }
252b5132 2167
29b0f896
AM		 2168 return l;
2169}
252b5132 2170
29b0f896 2171static char *
e3bb37b5 2172parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2173{
2174 char *token_start;
3138f287 2175
29b0f896
AM		 2176 /* 1 if operand is pending after ','. */
2177 unsigned int expecting_operand = 0;
252b5132 2178
29b0f896
AM		 2179 /* Non-zero if operand parens not balanced. */
2180 unsigned int paren_not_balanced;
2181
2182 while (*l != END_OF_INSN)
2183 {
2184 /* Skip optional white space before operand. */
2185 if (is_space_char (*l))
2186 ++l;
2187 if (!is_operand_char (*l) && *l != END_OF_INSN)
2188 {
2189 as_bad (_("invalid character %s before operand %d"),
2190 output_invalid (*l),
2191 i.operands + 1);
2192 return NULL;
2193 }
2194 token_start = l; /* after white space */
2195 paren_not_balanced = 0;
2196 while (paren_not_balanced || *l != ',')
2197 {
2198 if (*l == END_OF_INSN)
2199 {
2200 if (paren_not_balanced)
2201 {
2202 if (!intel_syntax)
2203 as_bad (_("unbalanced parenthesis in operand %d."),
2204 i.operands + 1);
2205 else
2206 as_bad (_("unbalanced brackets in operand %d."),
2207 i.operands + 1);
2208 return NULL;
2209 }
2210 else
2211 break; /* we are done */
2212 }
2213 else if (!is_operand_char (*l) && !is_space_char (*l))
2214 {
2215 as_bad (_("invalid character %s in operand %d"),
2216 output_invalid (*l),
2217 i.operands + 1);
2218 return NULL;
2219 }
2220 if (!intel_syntax)
2221 {
2222 if (*l == '(')
2223 ++paren_not_balanced;
2224 if (*l == ')')
2225 --paren_not_balanced;
2226 }
2227 else
2228 {
2229 if (*l == '[')
2230 ++paren_not_balanced;
2231 if (*l == ']')
2232 --paren_not_balanced;
2233 }
2234 l++;
2235 }
2236 if (l != token_start)
2237 { /* Yes, we've read in another operand. */
2238 unsigned int operand_ok;
2239 this_operand = i.operands++;
2240 if (i.operands > MAX_OPERANDS)
2241 {
2242 as_bad (_("spurious operands; (%d operands/instruction max)"),
2243 MAX_OPERANDS);
2244 return NULL;
2245 }
2246 /* Now parse operand adding info to 'i' as we go along. */
2247 END_STRING_AND_SAVE (l);
2248
2249 if (intel_syntax)
2250 operand_ok =
2251 i386_intel_operand (token_start,
2252 intel_float_operand (mnemonic));
2253 else
2254 operand_ok = i386_operand (token_start);
2255
2256 RESTORE_END_STRING (l);
2257 if (!operand_ok)
2258 return NULL;
2259 }
2260 else
2261 {
2262 if (expecting_operand)
2263 {
2264 expecting_operand_after_comma:
2265 as_bad (_("expecting operand after ','; got nothing"));
2266 return NULL;
2267 }
2268 if (*l == ',')
2269 {
2270 as_bad (_("expecting operand before ','; got nothing"));
2271 return NULL;
2272 }
2273 }
7f3f1ea2 2274
29b0f896
AM		 2275 /* Now *l must be either ',' or END_OF_INSN. */
2276 if (*l == ',')
2277 {
2278 if (*++l == END_OF_INSN)
2279 {
2280 /* Just skip it, if it's \n complain. */
2281 goto expecting_operand_after_comma;
2282 }
2283 expecting_operand = 1;
2284 }
2285 }
2286 return l;
2287}
7f3f1ea2 2288
050dfa73 2289static void
4d456e3d 2290swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2291{
2292 union i386_op temp_op;
2293 unsigned int temp_type;
2294 enum bfd_reloc_code_real temp_reloc;
4eed87de 2295
050dfa73
MM		 2296 temp_type = i.types[xchg2];
2297 i.types[xchg2] = i.types[xchg1];
2298 i.types[xchg1] = temp_type;
2299 temp_op = i.op[xchg2];
2300 i.op[xchg2] = i.op[xchg1];
2301 i.op[xchg1] = temp_op;
2302 temp_reloc = i.reloc[xchg2];
2303 i.reloc[xchg2] = i.reloc[xchg1];
2304 i.reloc[xchg1] = temp_reloc;
2305}
2306
29b0f896 2307static void
e3bb37b5 2308swap_operands (void)
29b0f896 2309{
b7c61d9a 2310 switch (i.operands)
050dfa73 2311 {
b7c61d9a 2312 case 4:
4d456e3d 2313 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2314 case 3:
2315 case 2:
4d456e3d 2316 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2317 break;
2318 default:
2319 abort ();
29b0f896 2320 }
29b0f896
AM		 2321
2322 if (i.mem_operands == 2)
2323 {
2324 const seg_entry *temp_seg;
2325 temp_seg = i.seg[0];
2326 i.seg[0] = i.seg[1];
2327 i.seg[1] = temp_seg;
2328 }
2329}
252b5132 2330
29b0f896
AM		 2331/* Try to ensure constant immediates are represented in the smallest
2332 opcode possible. */
2333static void
e3bb37b5 2334optimize_imm (void)
29b0f896
AM		 2335{
2336 char guess_suffix = 0;
2337 int op;
252b5132 2338
29b0f896
AM		 2339 if (i.suffix)
2340 guess_suffix = i.suffix;
2341 else if (i.reg_operands)
2342 {
2343 /* Figure out a suffix from the last register operand specified.
2344 We can't do this properly yet, ie. excluding InOutPortReg,
2345 but the following works for instructions with immediates.
2346 In any case, we can't set i.suffix yet. */
2347 for (op = i.operands; --op >= 0;)
2348 if (i.types[op] & Reg)
252b5132 2349 {
29b0f896
AM		 2350 if (i.types[op] & Reg8)
2351 guess_suffix = BYTE_MNEM_SUFFIX;
2352 else if (i.types[op] & Reg16)
2353 guess_suffix = WORD_MNEM_SUFFIX;
2354 else if (i.types[op] & Reg32)
2355 guess_suffix = LONG_MNEM_SUFFIX;
2356 else if (i.types[op] & Reg64)
2357 guess_suffix = QWORD_MNEM_SUFFIX;
2358 break;
252b5132 2359 }
29b0f896
AM		 2360 }
2361 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2362 guess_suffix = WORD_MNEM_SUFFIX;
2363
2364 for (op = i.operands; --op >= 0;)
2365 if (i.types[op] & Imm)
2366 {
2367 switch (i.op[op].imms->X_op)
252b5132 2368 {
29b0f896
AM		 2369 case O_constant:
2370 /* If a suffix is given, this operand may be shortened. */
2371 switch (guess_suffix)
252b5132 2372 {
29b0f896
AM		 2373 case LONG_MNEM_SUFFIX:
2374 i.types[op] |= Imm32 | Imm64;
2375 break;
2376 case WORD_MNEM_SUFFIX:
2377 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2378 break;
2379 case BYTE_MNEM_SUFFIX:
2380 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2381 break;
252b5132 2382 }
252b5132 2383
29b0f896
AM		 2384 /* If this operand is at most 16 bits, convert it
2385 to a signed 16 bit number before trying to see
2386 whether it will fit in an even smaller size.
2387 This allows a 16-bit operand such as $0xffe0 to
2388 be recognised as within Imm8S range. */
2389 if ((i.types[op] & Imm16)
2390 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2391 {
29b0f896
AM		 2392 i.op[op].imms->X_add_number =
2393 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2394 }
2395 if ((i.types[op] & Imm32)
2396 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2397 == 0))
2398 {
2399 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2400 ^ ((offsetT) 1 << 31))
2401 - ((offsetT) 1 << 31));
2402 }
2403 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2404
29b0f896
AM		 2405 /* We must avoid matching of Imm32 templates when 64bit
2406 only immediate is available. */
2407 if (guess_suffix == QWORD_MNEM_SUFFIX)
2408 i.types[op] &= ~Imm32;
2409 break;
252b5132 2410
29b0f896
AM		 2411 case O_absent:
2412 case O_register:
2413 abort ();
2414
2415 /* Symbols and expressions. */
2416 default:
9cd96992
JB		 2417 /* Convert symbolic operand to proper sizes for matching, but don't
2418 prevent matching a set of insns that only supports sizes other
2419 than those matching the insn suffix. */
2420 {
2421 unsigned int mask, allowed = 0;
2422 const template *t;
2423
4eed87de
AM		 2424 for (t = current_templates->start;
2425 t < current_templates->end;
2426 ++t)
2427 allowed |= t->operand_types[op];
9cd96992
JB		 2428 switch (guess_suffix)
2429 {
2430 case QWORD_MNEM_SUFFIX:
2431 mask = Imm64 | Imm32S;
2432 break;
2433 case LONG_MNEM_SUFFIX:
2434 mask = Imm32;
2435 break;
2436 case WORD_MNEM_SUFFIX:
2437 mask = Imm16;
2438 break;
2439 case BYTE_MNEM_SUFFIX:
2440 mask = Imm8;
2441 break;
2442 default:
2443 mask = 0;
2444 break;
2445 }
64e74474
AM		 2446 if (mask & allowed)
2447 i.types[op] &= mask;
9cd96992 2448 }
29b0f896 2449 break;
252b5132 2450 }
29b0f896
AM		 2451 }
2452}
47926f60 2453
29b0f896
AM		 2454/* Try to use the smallest displacement type too. */
2455static void
e3bb37b5 2456optimize_disp (void)
29b0f896
AM		 2457{
2458 int op;
3e73aa7c 2459
29b0f896 2460 for (op = i.operands; --op >= 0;)
b300c311 2461 if (i.types[op] & Disp)
252b5132 2462 {
b300c311 2463 if (i.op[op].disps->X_op == O_constant)
252b5132 2464 {
b300c311 2465 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2466
b300c311
L		 2467 if ((i.types[op] & Disp16)
2468 && (disp & ~(offsetT) 0xffff) == 0)
2469 {
2470 /* If this operand is at most 16 bits, convert
2471 to a signed 16 bit number and don't use 64bit
2472 displacement. */
2473 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2474 i.types[op] &= ~Disp64;
2475 }
2476 if ((i.types[op] & Disp32)
2477 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2478 {
2479 /* If this operand is at most 32 bits, convert
2480 to a signed 32 bit number and don't use 64bit
2481 displacement. */
2482 disp &= (((offsetT) 2 << 31) - 1);
2483 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2484 i.types[op] &= ~Disp64;
2485 }
2486 if (!disp && (i.types[op] & BaseIndex))
2487 {
2488 i.types[op] &= ~Disp;
2489 i.op[op].disps = 0;
2490 i.disp_operands--;
2491 }
2492 else if (flag_code == CODE_64BIT)
2493 {
2494 if (fits_in_signed_long (disp))
28a9d8f5
L		 2495 {
2496 i.types[op] &= ~Disp64;
2497 i.types[op] |= Disp32S;
2498 }
b300c311
L		 2499 if (fits_in_unsigned_long (disp))
2500 i.types[op] |= Disp32;
2501 }
2502 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2503 && fits_in_signed_byte (disp))
2504 i.types[op] |= Disp8;
252b5132 2505 }
67a4f2b7
AO		 2506 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2507 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2508 {
2509 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2510 i.op[op].disps, 0, i.reloc[op]);
2511 i.types[op] &= ~Disp;
2512 }
2513 else
b300c311
L		 2514 /* We only support 64bit displacement on constants. */
2515 i.types[op] &= ~Disp64;
252b5132 2516 }
29b0f896
AM		 2517}
2518
2519static int
e3bb37b5 2520match_template (void)
29b0f896
AM		 2521{
2522 /* Points to template once we've found it. */
2523 const template *t;
f48ff2ae 2524 unsigned int overlap0, overlap1, overlap2, overlap3;
29b0f896
AM		 2525 unsigned int found_reverse_match;
2526 int suffix_check;
f48ff2ae 2527 unsigned int operand_types [MAX_OPERANDS];
539e75ad 2528 int addr_prefix_disp;
a5c311ca 2529 unsigned int j;
29b0f896 2530
f48ff2ae
L		 2531#if MAX_OPERANDS != 4
2532# error "MAX_OPERANDS must be 4."
2533#endif
2534
29b0f896
AM		 2535#define MATCH(overlap, given, template) \
2536 ((overlap & ~JumpAbsolute) \
2537 && (((given) & (BaseIndex | JumpAbsolute)) \
2538 == ((overlap) & (BaseIndex | JumpAbsolute))))
2539
2540 /* If given types r0 and r1 are registers they must be of the same type
2541 unless the expected operand type register overlap is null.
2542 Note that Acc in a template matches every size of reg. */
2543#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2544 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2545 || ((g0) & Reg) == ((g1) & Reg) \
2546 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2547
2548 overlap0 = 0;
2549 overlap1 = 0;
2550 overlap2 = 0;
f48ff2ae 2551 overlap3 = 0;
29b0f896 2552 found_reverse_match = 0;
a5c311ca
L		 2553 for (j = 0; j < MAX_OPERANDS; j++)
2554 operand_types [j] = 0;
539e75ad 2555 addr_prefix_disp = -1;
29b0f896
AM		 2556 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2557 ? No_bSuf
2558 : (i.suffix == WORD_MNEM_SUFFIX
2559 ? No_wSuf
2560 : (i.suffix == SHORT_MNEM_SUFFIX
2561 ? No_sSuf
2562 : (i.suffix == LONG_MNEM_SUFFIX
2563 ? No_lSuf
2564 : (i.suffix == QWORD_MNEM_SUFFIX
2565 ? No_qSuf
2566 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2567 ? No_xSuf : 0))))));
2568
45aa61fe 2569 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2570 {
539e75ad
L		 2571 addr_prefix_disp = -1;
2572
29b0f896
AM		 2573 /* Must have right number of operands. */
2574 if (i.operands != t->operands)
2575 continue;
2576
20592a94 2577 /* Check the suffix, except for some instructions in intel mode. */
29b0f896
AM		 2578 if ((t->opcode_modifier & suffix_check)
2579 && !(intel_syntax
9306ca4a 2580 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2581 continue;
2582
a5c311ca
L		 2583 for (j = 0; j < MAX_OPERANDS; j++)
2584 operand_types [j] = t->operand_types [j];
539e75ad 2585
45aa61fe
AM		 2586 /* In general, don't allow 64-bit operands in 32-bit mode. */
2587 if (i.suffix == QWORD_MNEM_SUFFIX
2588 && flag_code != CODE_64BIT
2589 && (intel_syntax
2590 ? (!(t->opcode_modifier & IgnoreSize)
2591 && !intel_float_operand (t->name))
2592 : intel_float_operand (t->name) != 2)
539e75ad
L		 2593 && (!(operand_types[0] & (RegMMX | RegXMM))
2594 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
45aa61fe
AM		 2595 && (t->base_opcode != 0x0fc7
2596 || t->extension_opcode != 1 /* cmpxchg8b */))
2597 continue;
2598
29b0f896
AM		 2599 /* Do not verify operands when there are none. */
2600 else if (!t->operands)
2601 {
2602 if (t->cpu_flags & ~cpu_arch_flags)
2603 continue;
2604 /* We've found a match; break out of loop. */
2605 break;
2606 }
252b5132 2607
539e75ad
L		 2608 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2609 into Disp32/Disp16/Disp32 operand. */
2610 if (i.prefix[ADDR_PREFIX] != 0)
2611 {
a5c311ca 2612 unsigned int DispOn = 0, DispOff = 0;
539e75ad
L		 2613
2614 switch (flag_code)
2615 {
2616 case CODE_16BIT:
2617 DispOn = Disp32;
2618 DispOff = Disp16;
2619 break;
2620 case CODE_32BIT:
2621 DispOn = Disp16;
2622 DispOff = Disp32;
2623 break;
2624 case CODE_64BIT:
2625 DispOn = Disp32;
2626 DispOff = Disp64;
2627 break;
2628 }
2629
f48ff2ae 2630 for (j = 0; j < MAX_OPERANDS; j++)
539e75ad
L		 2631 {
2632 /* There should be only one Disp operand. */
2633 if ((operand_types[j] & DispOff))
2634 {
2635 addr_prefix_disp = j;
2636 operand_types[j] |= DispOn;
2637 operand_types[j] &= ~DispOff;
2638 break;
2639 }
2640 }
2641 }
2642
2643 overlap0 = i.types[0] & operand_types[0];
29b0f896
AM		 2644 switch (t->operands)
2645 {
2646 case 1:
539e75ad 2647 if (!MATCH (overlap0, i.types[0], operand_types[0]))
29b0f896
AM		 2648 continue;
2649 break;
2650 case 2:
8b38ad71
L		 2651 /* xchg %eax, %eax is a special case. It is an aliase for nop
2652 only in 32bit mode and we can use opcode 0x90. In 64bit
2653 mode, we can't use 0x90 for xchg %eax, %eax since it should
2654 zero-extend %eax to %rax. */
2655 if (flag_code == CODE_64BIT
2656 && t->base_opcode == 0x90
2657 && i.types [0] == (Acc | Reg32)
2658 && i.types [1] == (Acc | Reg32))
2659 continue;
29b0f896 2660 case 3:
f48ff2ae 2661 case 4:
539e75ad
L		 2662 overlap1 = i.types[1] & operand_types[1];
2663 if (!MATCH (overlap0, i.types[0], operand_types[0])
2664 || !MATCH (overlap1, i.types[1], operand_types[1])
cb712a9e 2665 /* monitor in SSE3 is a very special case. The first
708587a4 2666 register and the second register may have different
381d071f 2667 sizes. The same applies to crc32 in SSE4.2. */
cb712a9e
L		 2668 || !((t->base_opcode == 0x0f01
2669 && t->extension_opcode == 0xc8)
381d071f 2670 || t->base_opcode == 0xf20f38f1
cb712a9e 2671 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2672 operand_types[0],
cb712a9e 2673 overlap1, i.types[1],
539e75ad 2674 operand_types[1])))
29b0f896
AM		 2675 {
2676 /* Check if other direction is valid ... */
2677 if ((t->opcode_modifier & (D | FloatD)) == 0)
2678 continue;
2679
2680 /* Try reversing direction of operands. */
539e75ad
L		 2681 overlap0 = i.types[0] & operand_types[1];
2682 overlap1 = i.types[1] & operand_types[0];
2683 if (!MATCH (overlap0, i.types[0], operand_types[1])
2684 || !MATCH (overlap1, i.types[1], operand_types[0])
29b0f896 2685 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2686 operand_types[1],
29b0f896 2687 overlap1, i.types[1],
539e75ad 2688 operand_types[0]))
29b0f896
AM		 2689 {
2690 /* Does not match either direction. */
2691 continue;
2692 }
2693 /* found_reverse_match holds which of D or FloatDR
2694 we've found. */
8a2ed489
L		 2695 if ((t->opcode_modifier & D))
2696 found_reverse_match = Opcode_D;
2697 else if ((t->opcode_modifier & FloatD))
2698 found_reverse_match = Opcode_FloatD;
2699 else
2700 found_reverse_match = 0;
2701 if ((t->opcode_modifier & FloatR))
2702 found_reverse_match |= Opcode_FloatR;
29b0f896 2703 }
f48ff2ae 2704 else
29b0f896 2705 {
f48ff2ae 2706 /* Found a forward 2 operand match here. */
d1cbb4db
L		 2707 switch (t->operands)
2708 {
2709 case 4:
2710 overlap3 = i.types[3] & operand_types[3];
2711 case 3:
2712 overlap2 = i.types[2] & operand_types[2];
2713 break;
2714 }
29b0f896 2715
f48ff2ae
L		 2716 switch (t->operands)
2717 {
2718 case 4:
2719 if (!MATCH (overlap3, i.types[3], operand_types[3])
2720 || !CONSISTENT_REGISTER_MATCH (overlap2,
2721 i.types[2],
2722 operand_types[2],
2723 overlap3,
2724 i.types[3],
2725 operand_types[3]))
2726 continue;
2727 case 3:
2728 /* Here we make use of the fact that there are no
2729 reverse match 3 operand instructions, and all 3
2730 operand instructions only need to be checked for
2731 register consistency between operands 2 and 3. */
2732 if (!MATCH (overlap2, i.types[2], operand_types[2])
2733 || !CONSISTENT_REGISTER_MATCH (overlap1,
2734 i.types[1],
2735 operand_types[1],
2736 overlap2,
2737 i.types[2],
2738 operand_types[2]))
2739 continue;
2740 break;
2741 }
29b0f896 2742 }
f48ff2ae 2743 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 2744 slip through to break. */
2745 }
2746 if (t->cpu_flags & ~cpu_arch_flags)
2747 {
2748 found_reverse_match = 0;
2749 continue;
2750 }
2751 /* We've found a match; break out of loop. */
2752 break;
2753 }
2754
2755 if (t == current_templates->end)
2756 {
2757 /* We found no match. */
2758 as_bad (_("suffix or operands invalid for `%s'"),
2759 current_templates->start->name);
2760 return 0;
2761 }
252b5132 2762
29b0f896
AM		 2763 if (!quiet_warnings)
2764 {
2765 if (!intel_syntax
2766 && ((i.types[0] & JumpAbsolute)
539e75ad 2767 != (operand_types[0] & JumpAbsolute)))
29b0f896
AM		 2768 {
2769 as_warn (_("indirect %s without `*'"), t->name);
2770 }
2771
2772 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2773 == (IsPrefix | IgnoreSize))
2774 {
2775 /* Warn them that a data or address size prefix doesn't
2776 affect assembly of the next line of code. */
2777 as_warn (_("stand-alone `%s' prefix"), t->name);
2778 }
2779 }
2780
2781 /* Copy the template we found. */
2782 i.tm = *t;
539e75ad
L		 2783
2784 if (addr_prefix_disp != -1)
2785 i.tm.operand_types[addr_prefix_disp]
2786 = operand_types[addr_prefix_disp];
2787
29b0f896
AM		 2788 if (found_reverse_match)
2789 {
2790 /* If we found a reverse match we must alter the opcode
2791 direction bit. found_reverse_match holds bits to change
2792 (different for int & float insns). */
2793
2794 i.tm.base_opcode ^= found_reverse_match;
2795
539e75ad
L		 2796 i.tm.operand_types[0] = operand_types[1];
2797 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 2798 }
2799
2800 return 1;
2801}
2802
2803static int
e3bb37b5 2804check_string (void)
29b0f896
AM		 2805{
2806 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2807 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2808 {
2809 if (i.seg[0] != NULL && i.seg[0] != &es)
2810 {
2811 as_bad (_("`%s' operand %d must use `%%es' segment"),
2812 i.tm.name,
2813 mem_op + 1);
2814 return 0;
2815 }
2816 /* There's only ever one segment override allowed per instruction.
2817 This instruction possibly has a legal segment override on the
2818 second operand, so copy the segment to where non-string
2819 instructions store it, allowing common code. */
2820 i.seg[0] = i.seg[1];
2821 }
2822 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2823 {
2824 if (i.seg[1] != NULL && i.seg[1] != &es)
2825 {
2826 as_bad (_("`%s' operand %d must use `%%es' segment"),
2827 i.tm.name,
2828 mem_op + 2);
2829 return 0;
2830 }
2831 }
2832 return 1;
2833}
2834
2835static int
543613e9 2836process_suffix (void)
29b0f896
AM		 2837{
2838 /* If matched instruction specifies an explicit instruction mnemonic
2839 suffix, use it. */
2840 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2841 {
2842 if (i.tm.opcode_modifier & Size16)
2843 i.suffix = WORD_MNEM_SUFFIX;
2844 else if (i.tm.opcode_modifier & Size64)
2845 i.suffix = QWORD_MNEM_SUFFIX;
2846 else
2847 i.suffix = LONG_MNEM_SUFFIX;
2848 }
2849 else if (i.reg_operands)
2850 {
2851 /* If there's no instruction mnemonic suffix we try to invent one
2852 based on register operands. */
2853 if (!i.suffix)
2854 {
2855 /* We take i.suffix from the last register operand specified,
2856 Destination register type is more significant than source
381d071f
L		 2857 register type. crc32 in SSE4.2 prefers source register
2858 type. */
2859 if (i.tm.base_opcode == 0xf20f38f1)
2860 {
2861 if ((i.types[0] & Reg))
2862 i.suffix = ((i.types[0] & Reg16) ? WORD_MNEM_SUFFIX :
29b0f896 2863 LONG_MNEM_SUFFIX);
381d071f 2864 }
9344ff29 2865 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94
L		 2866 {
2867 if ((i.types[0] & Reg8))
2868 i.suffix = BYTE_MNEM_SUFFIX;
2869 }
381d071f
L		 2870
2871 if (!i.suffix)
2872 {
2873 int op;
2874
20592a94
L		 2875 if (i.tm.base_opcode == 0xf20f38f1
2876 || i.tm.base_opcode == 0xf20f38f0)
2877 {
2878 /* We have to know the operand size for crc32. */
2879 as_bad (_("ambiguous memory operand size for `%s`"),
2880 i.tm.name);
2881 return 0;
2882 }
2883
381d071f
L		 2884 for (op = i.operands; --op >= 0;)
2885 if ((i.types[op] & Reg)
2886 && !(i.tm.operand_types[op] & InOutPortReg))
2887 {
2888 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2889 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2890 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2891 LONG_MNEM_SUFFIX);
2892 break;
2893 }
2894 }
29b0f896
AM		 2895 }
2896 else if (i.suffix == BYTE_MNEM_SUFFIX)
2897 {
2898 if (!check_byte_reg ())
2899 return 0;
2900 }
2901 else if (i.suffix == LONG_MNEM_SUFFIX)
2902 {
2903 if (!check_long_reg ())
2904 return 0;
2905 }
2906 else if (i.suffix == QWORD_MNEM_SUFFIX)
2907 {
2908 if (!check_qword_reg ())
2909 return 0;
2910 }
2911 else if (i.suffix == WORD_MNEM_SUFFIX)
2912 {
2913 if (!check_word_reg ())
2914 return 0;
2915 }
2916 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2917 /* Do nothing if the instruction is going to ignore the prefix. */
2918 ;
2919 else
2920 abort ();
2921 }
9306ca4a
JB		 2922 else if ((i.tm.opcode_modifier & DefaultSize)
2923 && !i.suffix
2924 /* exclude fldenv/frstor/fsave/fstenv */
2925 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2926 {
2927 i.suffix = stackop_size;
2928 }
9306ca4a
JB		 2929 else if (intel_syntax
2930 && !i.suffix
2931 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2932 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2933 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2934 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2935 {
2936 switch (flag_code)
2937 {
2938 case CODE_64BIT:
2939 if (!(i.tm.opcode_modifier & No_qSuf))
2940 {
2941 i.suffix = QWORD_MNEM_SUFFIX;
2942 break;
2943 }
2944 case CODE_32BIT:
2945 if (!(i.tm.opcode_modifier & No_lSuf))
2946 i.suffix = LONG_MNEM_SUFFIX;
2947 break;
2948 case CODE_16BIT:
2949 if (!(i.tm.opcode_modifier & No_wSuf))
2950 i.suffix = WORD_MNEM_SUFFIX;
2951 break;
2952 }
2953 }
252b5132 2954
9306ca4a 2955 if (!i.suffix)
29b0f896 2956 {
9306ca4a
JB		 2957 if (!intel_syntax)
2958 {
2959 if (i.tm.opcode_modifier & W)
2960 {
4eed87de
AM		 2961 as_bad (_("no instruction mnemonic suffix given and "
2962 "no register operands; can't size instruction"));
9306ca4a
JB		 2963 return 0;
2964 }
2965 }
2966 else
2967 {
64e74474
AM		 2968 unsigned int suffixes = (~i.tm.opcode_modifier
2969 & (No_bSuf
2970 | No_wSuf
2971 | No_lSuf
2972 | No_sSuf
2973 | No_xSuf
2974 | No_qSuf));
9306ca4a
JB		 2975
2976 if ((i.tm.opcode_modifier & W)
2977 || ((suffixes & (suffixes - 1))
2978 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2979 {
2980 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2981 return 0;
2982 }
2983 }
29b0f896 2984 }
252b5132 2985
9306ca4a
JB		 2986 /* Change the opcode based on the operand size given by i.suffix;
2987 We don't need to change things for byte insns. */
2988
29b0f896
AM		 2989 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2990 {
2991 /* It's not a byte, select word/dword operation. */
2992 if (i.tm.opcode_modifier & W)
2993 {
2994 if (i.tm.opcode_modifier & ShortForm)
2995 i.tm.base_opcode |= 8;
2996 else
2997 i.tm.base_opcode |= 1;
2998 }
0f3f3d8b 2999
29b0f896
AM		 3000 /* Now select between word & dword operations via the operand
3001 size prefix, except for instructions that will ignore this
3002 prefix anyway. */
cb712a9e
L		 3003 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
3004 {
3005 /* monitor in SSE3 is a very special case. The default size
3006 of AX is the size of mode. The address size override
3007 prefix will change the size of AX. */
3008 if (i.op->regs[0].reg_type &
3009 (flag_code == CODE_32BIT ? Reg16 : Reg32))
3010 if (!add_prefix (ADDR_PREFIX_OPCODE))
3011 return 0;
3012 }
3013 else if (i.suffix != QWORD_MNEM_SUFFIX
3014 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
3015 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
3016 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3017 || (flag_code == CODE_64BIT
3018 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 3019 {
3020 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3021
29b0f896
AM		 3022 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
3023 prefix = ADDR_PREFIX_OPCODE;
252b5132 3024
29b0f896
AM		 3025 if (!add_prefix (prefix))
3026 return 0;
24eab124 3027 }
252b5132 3028
29b0f896
AM		 3029 /* Set mode64 for an operand. */
3030 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3031 && flag_code == CODE_64BIT
29b0f896 3032 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L		 3033 {
3034 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 3035 need rex64. cmpxchg8b is also a special case. */
3036 if (! (i.operands == 2
3037 && i.tm.base_opcode == 0x90
3038 && i.tm.extension_opcode == None
3039 && i.types [0] == (Acc | Reg64)
3040 && i.types [1] == (Acc | Reg64))
3041 && ! (i.operands == 1
3042 && i.tm.base_opcode == 0xfc7
3043 && i.tm.extension_opcode == 1
3044 && (i.types [0] & Reg) == 0
3045 && (i.types [0] & AnyMem) != 0))
f6bee062 3046 i.rex |= REX_W;
46e883c5 3047 }
3e73aa7c 3048
29b0f896
AM		 3049 /* Size floating point instruction. */
3050 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 3051 if (i.tm.opcode_modifier & FloatMF)
3052 i.tm.base_opcode ^= 4;
29b0f896 3053 }
7ecd2f8b 3054
29b0f896
AM		 3055 return 1;
3056}
3e73aa7c 3057
29b0f896 3058static int
543613e9 3059check_byte_reg (void)
29b0f896
AM		 3060{
3061 int op;
543613e9 3062
29b0f896
AM		 3063 for (op = i.operands; --op >= 0;)
3064 {
3065 /* If this is an eight bit register, it's OK. If it's the 16 or
3066 32 bit version of an eight bit register, we will just use the
3067 low portion, and that's OK too. */
3068 if (i.types[op] & Reg8)
3069 continue;
3070
c3ad16c0
L		 3071 /* movzx, movsx, pextrb and pinsrb should not generate this
3072 warning. */
29b0f896
AM		 3073 if (intel_syntax
3074 && (i.tm.base_opcode == 0xfb7
3075 || i.tm.base_opcode == 0xfb6
3076 || i.tm.base_opcode == 0x63
3077 || i.tm.base_opcode == 0xfbe
c3ad16c0
L		 3078 || i.tm.base_opcode == 0xfbf
3079 || i.tm.base_opcode == 0x660f3a14
3080 || i.tm.base_opcode == 0x660f3a20))
29b0f896
AM		 3081 continue;
3082
9344ff29
L		 3083 /* crc32 doesn't generate this warning. */
3084 if (i.tm.base_opcode == 0xf20f38f0)
3085 continue;
3086
65ec77d2 3087 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3088 {
3089 /* Prohibit these changes in the 64bit mode, since the
3090 lowering is more complicated. */
3091 if (flag_code == CODE_64BIT
3092 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3093 {
2ca3ace5
L		 3094 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3095 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3096 i.suffix);
3097 return 0;
3098 }
3099#if REGISTER_WARNINGS
3100 if (!quiet_warnings
3101 && (i.tm.operand_types[op] & InOutPortReg) == 0)
a540244d
L		 3102 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3103 register_prefix,
29b0f896
AM		 3104 (i.op[op].regs + (i.types[op] & Reg16
3105 ? REGNAM_AL - REGNAM_AX
3106 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3107 register_prefix,
29b0f896
AM		 3108 i.op[op].regs->reg_name,
3109 i.suffix);
3110#endif
3111 continue;
3112 }
3113 /* Any other register is bad. */
3114 if (i.types[op] & (Reg | RegMMX | RegXMM
3115 | SReg2 | SReg3
3116 | Control | Debug | Test
3117 | FloatReg | FloatAcc))
3118 {
a540244d
L		 3119 as_bad (_("`%s%s' not allowed with `%s%c'"),
3120 register_prefix,
29b0f896
AM		 3121 i.op[op].regs->reg_name,
3122 i.tm.name,
3123 i.suffix);
3124 return 0;
3125 }
3126 }
3127 return 1;
3128}
3129
3130static int
e3bb37b5 3131check_long_reg (void)
29b0f896
AM		 3132{
3133 int op;
3134
3135 for (op = i.operands; --op >= 0;)
3136 /* Reject eight bit registers, except where the template requires
3137 them. (eg. movzb) */
3138 if ((i.types[op] & Reg8) != 0
3139 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3140 {
a540244d
L		 3141 as_bad (_("`%s%s' not allowed with `%s%c'"),
3142 register_prefix,
29b0f896
AM		 3143 i.op[op].regs->reg_name,
3144 i.tm.name,
3145 i.suffix);
3146 return 0;
3147 }
3148 /* Warn if the e prefix on a general reg is missing. */
3149 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3150 && (i.types[op] & Reg16) != 0
3151 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3152 {
3153 /* Prohibit these changes in the 64bit mode, since the
3154 lowering is more complicated. */
3155 if (flag_code == CODE_64BIT)
252b5132 3156 {
2ca3ace5
L		 3157 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3158 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3159 i.suffix);
3160 return 0;
252b5132 3161 }
29b0f896
AM		 3162#if REGISTER_WARNINGS
3163 else
a540244d
L		 3164 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3165 register_prefix,
29b0f896 3166 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3167 register_prefix,
29b0f896
AM		 3168 i.op[op].regs->reg_name,
3169 i.suffix);
3170#endif
252b5132 3171 }
29b0f896
AM		 3172 /* Warn if the r prefix on a general reg is missing. */
3173 else if ((i.types[op] & Reg64) != 0
3174 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 3175 {
34828aad
L		 3176 if (intel_syntax
3177 && i.tm.base_opcode == 0xf30f2d
3178 && (i.types[0] & RegXMM) == 0)
3179 {
3180 /* cvtss2si converts DWORD memory to Reg64. We want
3181 REX byte. */
3182 i.suffix = QWORD_MNEM_SUFFIX;
3183 }
3184 else
3185 {
3186 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3187 register_prefix, i.op[op].regs->reg_name,
3188 i.suffix);
3189 return 0;
3190 }
29b0f896
AM		 3191 }
3192 return 1;
3193}
252b5132 3194
29b0f896 3195static int
e3bb37b5 3196check_qword_reg (void)
29b0f896
AM		 3197{
3198 int op;
252b5132 3199
29b0f896
AM		 3200 for (op = i.operands; --op >= 0; )
3201 /* Reject eight bit registers, except where the template requires
3202 them. (eg. movzb) */
3203 if ((i.types[op] & Reg8) != 0
3204 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3205 {
a540244d
L		 3206 as_bad (_("`%s%s' not allowed with `%s%c'"),
3207 register_prefix,
29b0f896
AM		 3208 i.op[op].regs->reg_name,
3209 i.tm.name,
3210 i.suffix);
3211 return 0;
3212 }
3213 /* Warn if the e prefix on a general reg is missing. */
34828aad 3214 else if ((i.types[op] & (Reg16 | Reg32)) != 0
29b0f896
AM		 3215 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3216 {
3217 /* Prohibit these changes in the 64bit mode, since the
3218 lowering is more complicated. */
34828aad
L		 3219 if (intel_syntax
3220 && i.tm.base_opcode == 0xf20f2d
3221 && (i.types[0] & RegXMM) == 0)
3222 {
3223 /* cvtsd2si converts QWORD memory to Reg32. We don't want
3224 REX byte. */
3225 i.suffix = LONG_MNEM_SUFFIX;
3226 }
3227 else
3228 {
3229 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3230 register_prefix, i.op[op].regs->reg_name,
3231 i.suffix);
3232 return 0;
3233 }
252b5132 3234 }
29b0f896
AM		 3235 return 1;
3236}
252b5132 3237
29b0f896 3238static int
e3bb37b5 3239check_word_reg (void)
29b0f896
AM		 3240{
3241 int op;
3242 for (op = i.operands; --op >= 0;)
3243 /* Reject eight bit registers, except where the template requires
3244 them. (eg. movzb) */
3245 if ((i.types[op] & Reg8) != 0
3246 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3247 {
a540244d
L		 3248 as_bad (_("`%s%s' not allowed with `%s%c'"),
3249 register_prefix,
29b0f896
AM		 3250 i.op[op].regs->reg_name,
3251 i.tm.name,
3252 i.suffix);
3253 return 0;
3254 }
3255 /* Warn if the e prefix on a general reg is present. */
3256 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3257 && (i.types[op] & Reg32) != 0
3258 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 3259 {
29b0f896
AM		 3260 /* Prohibit these changes in the 64bit mode, since the
3261 lowering is more complicated. */
3262 if (flag_code == CODE_64BIT)
252b5132 3263 {
2ca3ace5
L		 3264 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3265 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3266 i.suffix);
3267 return 0;
252b5132 3268 }
29b0f896
AM		 3269 else
3270#if REGISTER_WARNINGS
a540244d
L		 3271 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3272 register_prefix,
29b0f896 3273 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 3274 register_prefix,
29b0f896
AM		 3275 i.op[op].regs->reg_name,
3276 i.suffix);
3277#endif
3278 }
3279 return 1;
3280}
252b5132 3281
29b0f896 3282static int
e3bb37b5 3283finalize_imm (void)
29b0f896
AM		 3284{
3285 unsigned int overlap0, overlap1, overlap2;
3286
3287 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 3288 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 3289 && overlap0 != Imm8 && overlap0 != Imm8S
3290 && overlap0 != Imm16 && overlap0 != Imm32S
3291 && overlap0 != Imm32 && overlap0 != Imm64)
3292 {
3293 if (i.suffix)
3294 {
3295 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3296 ? Imm8 | Imm8S
3297 : (i.suffix == WORD_MNEM_SUFFIX
3298 ? Imm16
3299 : (i.suffix == QWORD_MNEM_SUFFIX
3300 ? Imm64 | Imm32S
3301 : Imm32)));
3302 }
3303 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3304 || overlap0 == (Imm16 | Imm32)
3305 || overlap0 == (Imm16 | Imm32S))
3306 {
3307 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3308 ? Imm16 : Imm32S);
3309 }
3310 if (overlap0 != Imm8 && overlap0 != Imm8S
3311 && overlap0 != Imm16 && overlap0 != Imm32S
3312 && overlap0 != Imm32 && overlap0 != Imm64)
3313 {
4eed87de
AM		 3314 as_bad (_("no instruction mnemonic suffix given; "
3315 "can't determine immediate size"));
29b0f896
AM		 3316 return 0;
3317 }
3318 }
3319 i.types[0] = overlap0;
3320
3321 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 3322 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 3323 && overlap1 != Imm8 && overlap1 != Imm8S
3324 && overlap1 != Imm16 && overlap1 != Imm32S
3325 && overlap1 != Imm32 && overlap1 != Imm64)
3326 {
3327 if (i.suffix)
3328 {
3329 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3330 ? Imm8 | Imm8S
3331 : (i.suffix == WORD_MNEM_SUFFIX
3332 ? Imm16
3333 : (i.suffix == QWORD_MNEM_SUFFIX
3334 ? Imm64 | Imm32S
3335 : Imm32)));
3336 }
3337 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3338 || overlap1 == (Imm16 | Imm32)
3339 || overlap1 == (Imm16 | Imm32S))
3340 {
3341 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3342 ? Imm16 : Imm32S);
3343 }
3344 if (overlap1 != Imm8 && overlap1 != Imm8S
3345 && overlap1 != Imm16 && overlap1 != Imm32S
3346 && overlap1 != Imm32 && overlap1 != Imm64)
3347 {
4eed87de
AM		 3348 as_bad (_("no instruction mnemonic suffix given; "
3349 "can't determine immediate size %x %c"),
3350 overlap1, i.suffix);
29b0f896
AM		 3351 return 0;
3352 }
3353 }
3354 i.types[1] = overlap1;
3355
3356 overlap2 = i.types[2] & i.tm.operand_types[2];
3357 assert ((overlap2 & Imm) == 0);
3358 i.types[2] = overlap2;
3359
3360 return 1;
3361}
3362
3363static int
e3bb37b5 3364process_operands (void)
29b0f896
AM		 3365{
3366 /* Default segment register this instruction will use for memory
3367 accesses. 0 means unknown. This is only for optimizing out
3368 unnecessary segment overrides. */
3369 const seg_entry *default_seg = 0;
3370
3371 /* The imul $imm, %reg instruction is converted into
3372 imul $imm, %reg, %reg, and the clr %reg instruction
3373 is converted into xor %reg, %reg. */
5f15756d 3374 if (i.tm.opcode_modifier & RegKludge)
29b0f896 3375 {
42903f7f
L		 3376 if ((i.tm.cpu_flags & CpuSSE4_1))
3377 {
3378 /* The first operand in instruction blendvpd, blendvps and
3379 pblendvb in SSE4.1 is implicit and must be xmm0. */
3380 assert (i.operands == 3
3381 && i.reg_operands >= 2
3382 && i.types[0] == RegXMM);
3383 if (i.op[0].regs->reg_num != 0)
3384 {
3385 if (intel_syntax)
3386 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
3387 i.tm.name, register_prefix);
3388 else
3389 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
3390 i.tm.name, register_prefix);
3391 return 0;
3392 }
3393 i.op[0] = i.op[1];
3394 i.op[1] = i.op[2];
3395 i.types[0] = i.types[1];
3396 i.types[1] = i.types[2];
3397 i.operands--;
3398 i.reg_operands--;
3399
3400 /* We need to adjust fields in i.tm since they are used by
3401 build_modrm_byte. */
3402 i.tm.operand_types [0] = i.tm.operand_types [1];
3403 i.tm.operand_types [1] = i.tm.operand_types [2];
3404 i.tm.operands--;
3405 }
3406 else
3407 {
3408 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3409 /* Pretend we saw the extra register operand. */
3410 assert (i.reg_operands == 1
3411 && i.op[first_reg_op + 1].regs == 0);
3412 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3413 i.types[first_reg_op + 1] = i.types[first_reg_op];
3414 i.operands++;
3415 i.reg_operands++;
3416 }
29b0f896
AM		 3417 }
3418
3419 if (i.tm.opcode_modifier & ShortForm)
3420 {
4eed87de 3421 if (i.types[0] & (SReg2 | SReg3))
29b0f896 3422 {
4eed87de
AM		 3423 if (i.tm.base_opcode == POP_SEG_SHORT
3424 && i.op[0].regs->reg_num == 1)
29b0f896 3425 {
4eed87de
AM		 3426 as_bad (_("you can't `pop %%cs'"));
3427 return 0;
29b0f896 3428 }
4eed87de
AM		 3429 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3430 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 3431 i.rex |= REX_B;
4eed87de
AM		 3432 }
3433 else
3434 {
3435 /* The register or float register operand is in operand 0 or 1. */
3436 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3437 /* Register goes in low 3 bits of opcode. */
3438 i.tm.base_opcode |= i.op[op].regs->reg_num;
3439 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3440 i.rex |= REX_B;
4eed87de 3441 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
29b0f896 3442 {
4eed87de
AM		 3443 /* Warn about some common errors, but press on regardless.
3444 The first case can be generated by gcc (<= 2.8.1). */
3445 if (i.operands == 2)
3446 {
3447 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 3448 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
3449 register_prefix, i.op[1].regs->reg_name,
3450 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 3451 }
3452 else
3453 {
3454 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 3455 as_warn (_("translating to `%s %s%s'"), i.tm.name,
3456 register_prefix, i.op[0].regs->reg_name);
4eed87de 3457 }
29b0f896
AM		 3458 }
3459 }
3460 }
3461 else if (i.tm.opcode_modifier & Modrm)
3462 {
3463 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3464 must be put into the modrm byte). Now, we make the modrm and
3465 index base bytes based on all the info we've collected. */
29b0f896
AM		 3466
3467 default_seg = build_modrm_byte ();
3468 }
8a2ed489 3469 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 3470 {
3471 default_seg = &ds;
3472 }
3473 else if ((i.tm.opcode_modifier & IsString) != 0)
3474 {
3475 /* For the string instructions that allow a segment override
3476 on one of their operands, the default segment is ds. */
3477 default_seg = &ds;
3478 }
3479
30123838
JB		 3480 if ((i.tm.base_opcode == 0x8d /* lea */
3481 || (i.tm.cpu_flags & CpuSVME))
3482 && i.seg[0] && !quiet_warnings)
3483 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3484
3485 /* If a segment was explicitly specified, and the specified segment
3486 is not the default, use an opcode prefix to select it. If we
3487 never figured out what the default segment is, then default_seg
3488 will be zero at this point, and the specified segment prefix will
3489 always be used. */
29b0f896
AM		 3490 if ((i.seg[0]) && (i.seg[0] != default_seg))
3491 {
3492 if (!add_prefix (i.seg[0]->seg_prefix))
3493 return 0;
3494 }
3495 return 1;
3496}
3497
3498static const seg_entry *
e3bb37b5 3499build_modrm_byte (void)
29b0f896
AM		 3500{
3501 const seg_entry *default_seg = 0;
3502
3503 /* i.reg_operands MUST be the number of real register operands;
3504 implicit registers do not count. */
3505 if (i.reg_operands == 2)
3506 {
3507 unsigned int source, dest;
cab737b9
L		 3508
3509 switch (i.operands)
3510 {
3511 case 2:
3512 source = 0;
3513 break;
3514 case 3:
c81128dc
L		 3515 /* When there are 3 operands, one of them may be immediate,
3516 which may be the first or the last operand. Otherwise,
3517 the first operand must be shift count register (cl). */
3518 assert (i.imm_operands == 1
3519 || (i.imm_operands == 0
3520 && (i.types[0] & ShiftCount)));
3521 source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0;
cab737b9
L		 3522 break;
3523 case 4:
3524 /* When there are 4 operands, the first two must be immediate
3525 operands. The source operand will be the 3rd one. */
3526 assert (i.imm_operands == 2
3527 && (i.types[0] & Imm)
3528 && (i.types[1] & Imm));
3529 source = 2;
3530 break;
3531 default:
3532 abort ();
3533 }
3534
29b0f896
AM		 3535 dest = source + 1;
3536
3537 i.rm.mode = 3;
3538 /* One of the register operands will be encoded in the i.tm.reg
3539 field, the other in the combined i.tm.mode and i.tm.regmem
3540 fields. If no form of this instruction supports a memory
3541 destination operand, then we assume the source operand may
3542 sometimes be a memory operand and so we need to store the
3543 destination in the i.rm.reg field. */
e72cf3ec 3544 if ((i.tm.operand_types[dest] & (AnyMem | RegMem)) == 0)
29b0f896
AM		 3545 {
3546 i.rm.reg = i.op[dest].regs->reg_num;
3547 i.rm.regmem = i.op[source].regs->reg_num;
3548 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 3549 i.rex |= REX_R;
29b0f896 3550 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 3551 i.rex |= REX_B;
29b0f896
AM		 3552 }
3553 else
3554 {
3555 i.rm.reg = i.op[source].regs->reg_num;
3556 i.rm.regmem = i.op[dest].regs->reg_num;
3557 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 3558 i.rex |= REX_B;
29b0f896 3559 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 3560 i.rex |= REX_R;
29b0f896 3561 }
161a04f6 3562 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5
JB		 3563 {
3564 if (!((i.types[0] | i.types[1]) & Control))
3565 abort ();
161a04f6 3566 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 3567 add_prefix (LOCK_PREFIX_OPCODE);
3568 }
29b0f896
AM		 3569 }
3570 else
3571 { /* If it's not 2 reg operands... */
3572 if (i.mem_operands)
3573 {
3574 unsigned int fake_zero_displacement = 0;
99018f42 3575 unsigned int op;
4eed87de 3576
99018f42
L		 3577 for (op = 0; op < i.operands; op++)
3578 if ((i.types[op] & AnyMem))
3579 break;
3580 assert (op < i.operands);
29b0f896
AM		 3581
3582 default_seg = &ds;
3583
3584 if (i.base_reg == 0)
3585 {
3586 i.rm.mode = 0;
3587 if (!i.disp_operands)
3588 fake_zero_displacement = 1;
3589 if (i.index_reg == 0)
3590 {
3591 /* Operand is just <disp> */
20f0a1fc 3592 if (flag_code == CODE_64BIT)
29b0f896
AM		 3593 {
3594 /* 64bit mode overwrites the 32bit absolute
3595 addressing by RIP relative addressing and
3596 absolute addressing is encoded by one of the
3597 redundant SIB forms. */
3598 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3599 i.sib.base = NO_BASE_REGISTER;
3600 i.sib.index = NO_INDEX_REGISTER;
fc225355
L		 3601 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3602 ? Disp32S : Disp32);
20f0a1fc 3603 }
fc225355
L		 3604 else if ((flag_code == CODE_16BIT)
3605 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 3606 {
3607 i.rm.regmem = NO_BASE_REGISTER_16;
3608 i.types[op] = Disp16;
3609 }
3610 else
3611 {
3612 i.rm.regmem = NO_BASE_REGISTER;
3613 i.types[op] = Disp32;
29b0f896
AM		 3614 }
3615 }
3616 else /* !i.base_reg && i.index_reg */
3617 {
3618 i.sib.index = i.index_reg->reg_num;
3619 i.sib.base = NO_BASE_REGISTER;
3620 i.sib.scale = i.log2_scale_factor;
3621 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3622 i.types[op] &= ~Disp;
3623 if (flag_code != CODE_64BIT)
3624 i.types[op] |= Disp32; /* Must be 32 bit */
3625 else
3626 i.types[op] |= Disp32S;
3627 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 3628 i.rex |= REX_X;
29b0f896
AM		 3629 }
3630 }
3631 /* RIP addressing for 64bit mode. */
3632 else if (i.base_reg->reg_type == BaseIndex)
3633 {
3634 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3635 i.types[op] &= ~ Disp;
29b0f896 3636 i.types[op] |= Disp32S;
71903a11 3637 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 3638 if (! i.disp_operands)
3639 fake_zero_displacement = 1;
29b0f896
AM		 3640 }
3641 else if (i.base_reg->reg_type & Reg16)
3642 {
3643 switch (i.base_reg->reg_num)
3644 {
3645 case 3: /* (%bx) */
3646 if (i.index_reg == 0)
3647 i.rm.regmem = 7;
3648 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3649 i.rm.regmem = i.index_reg->reg_num - 6;
3650 break;
3651 case 5: /* (%bp) */
3652 default_seg = &ss;
3653 if (i.index_reg == 0)
3654 {
3655 i.rm.regmem = 6;
3656 if ((i.types[op] & Disp) == 0)
3657 {
3658 /* fake (%bp) into 0(%bp) */
3659 i.types[op] |= Disp8;
252b5132 3660 fake_zero_displacement = 1;
29b0f896
AM		 3661 }
3662 }
3663 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3664 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3665 break;
3666 default: /* (%si) -> 4 or (%di) -> 5 */
3667 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3668 }
3669 i.rm.mode = mode_from_disp_size (i.types[op]);
3670 }
3671 else /* i.base_reg and 32/64 bit mode */
3672 {
3673 if (flag_code == CODE_64BIT
3674 && (i.types[op] & Disp))
fc225355
L		 3675 i.types[op] = ((i.types[op] & Disp8)
3676 | (i.prefix[ADDR_PREFIX] == 0
3677 ? Disp32S : Disp32));
20f0a1fc 3678
29b0f896
AM		 3679 i.rm.regmem = i.base_reg->reg_num;
3680 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 3681 i.rex |= REX_B;
29b0f896
AM		 3682 i.sib.base = i.base_reg->reg_num;
3683 /* x86-64 ignores REX prefix bit here to avoid decoder
3684 complications. */
3685 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3686 {
3687 default_seg = &ss;
3688 if (i.disp_operands == 0)
3689 {
3690 fake_zero_displacement = 1;
3691 i.types[op] |= Disp8;
3692 }
3693 }
3694 else if (i.base_reg->reg_num == ESP_REG_NUM)
3695 {
3696 default_seg = &ss;
3697 }
3698 i.sib.scale = i.log2_scale_factor;
3699 if (i.index_reg == 0)
3700 {
3701 /* <disp>(%esp) becomes two byte modrm with no index
3702 register. We've already stored the code for esp
3703 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3704 Any base register besides %esp will not use the
3705 extra modrm byte. */
3706 i.sib.index = NO_INDEX_REGISTER;
3707#if !SCALE1_WHEN_NO_INDEX
3708 /* Another case where we force the second modrm byte. */
3709 if (i.log2_scale_factor)
3710 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3711#endif
29b0f896
AM		 3712 }
3713 else
3714 {
3715 i.sib.index = i.index_reg->reg_num;
3716 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3717 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 3718 i.rex |= REX_X;
29b0f896 3719 }
67a4f2b7
AO		 3720
3721 if (i.disp_operands
3722 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3723 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3724 i.rm.mode = 0;
3725 else
3726 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3727 }
252b5132 3728
29b0f896
AM		 3729 if (fake_zero_displacement)
3730 {
3731 /* Fakes a zero displacement assuming that i.types[op]
3732 holds the correct displacement size. */
3733 expressionS *exp;
3734
3735 assert (i.op[op].disps == 0);
3736 exp = &disp_expressions[i.disp_operands++];
3737 i.op[op].disps = exp;
3738 exp->X_op = O_constant;
3739 exp->X_add_number = 0;
3740 exp->X_add_symbol = (symbolS *) 0;
3741 exp->X_op_symbol = (symbolS *) 0;
3742 }
3743 }
252b5132 3744
29b0f896
AM		 3745 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3746 (if any) based on i.tm.extension_opcode. Again, we must be
3747 careful to make sure that segment/control/debug/test/MMX
3748 registers are coded into the i.rm.reg field. */
3749 if (i.reg_operands)
3750 {
99018f42
L		 3751 unsigned int op;
3752
3753 for (op = 0; op < i.operands; op++)
3754 if ((i.types[op] & (Reg | RegMMX | RegXMM
3755 | SReg2 | SReg3
3756 | Control | Debug | Test)))
3757 break;
3758 assert (op < i.operands);
3759
29b0f896
AM		 3760 /* If there is an extension opcode to put here, the register
3761 number must be put into the regmem field. */
3762 if (i.tm.extension_opcode != None)
3763 {
3764 i.rm.regmem = i.op[op].regs->reg_num;
3765 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3766 i.rex |= REX_B;
29b0f896
AM		 3767 }
3768 else
3769 {
3770 i.rm.reg = i.op[op].regs->reg_num;
3771 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3772 i.rex |= REX_R;
29b0f896 3773 }
252b5132 3774
29b0f896
AM		 3775 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3776 must set it to 3 to indicate this is a register operand
3777 in the regmem field. */
3778 if (!i.mem_operands)
3779 i.rm.mode = 3;
3780 }
252b5132 3781
29b0f896
AM		 3782 /* Fill in i.rm.reg field with extension opcode (if any). */
3783 if (i.tm.extension_opcode != None)
3784 i.rm.reg = i.tm.extension_opcode;
3785 }
3786 return default_seg;
3787}
252b5132 3788
29b0f896 3789static void
e3bb37b5 3790output_branch (void)
29b0f896
AM		 3791{
3792 char *p;
3793 int code16;
3794 int prefix;
3795 relax_substateT subtype;
3796 symbolS *sym;
3797 offsetT off;
3798
3799 code16 = 0;
3800 if (flag_code == CODE_16BIT)
3801 code16 = CODE16;
3802
3803 prefix = 0;
3804 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3805 {
29b0f896
AM		 3806 prefix = 1;
3807 i.prefixes -= 1;
3808 code16 ^= CODE16;
252b5132 3809 }
29b0f896
AM		 3810 /* Pentium4 branch hints. */
3811 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3812 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3813 {
29b0f896
AM		 3814 prefix++;
3815 i.prefixes--;
3816 }
3817 if (i.prefix[REX_PREFIX] != 0)
3818 {
3819 prefix++;
3820 i.prefixes--;
2f66722d
AM		 3821 }
3822
29b0f896
AM		 3823 if (i.prefixes != 0 && !intel_syntax)
3824 as_warn (_("skipping prefixes on this instruction"));
3825
3826 /* It's always a symbol; End frag & setup for relax.
3827 Make sure there is enough room in this frag for the largest
3828 instruction we may generate in md_convert_frag. This is 2
3829 bytes for the opcode and room for the prefix and largest
3830 displacement. */
3831 frag_grow (prefix + 2 + 4);
3832 /* Prefix and 1 opcode byte go in fr_fix. */
3833 p = frag_more (prefix + 1);
3834 if (i.prefix[DATA_PREFIX] != 0)
3835 *p++ = DATA_PREFIX_OPCODE;
3836 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3837 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3838 *p++ = i.prefix[SEG_PREFIX];
3839 if (i.prefix[REX_PREFIX] != 0)
3840 *p++ = i.prefix[REX_PREFIX];
3841 *p = i.tm.base_opcode;
3842
3843 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3844 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3845 else if ((cpu_arch_flags & Cpu386) != 0)
3846 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3847 else
3848 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3849 subtype |= code16;
3e73aa7c 3850
29b0f896
AM		 3851 sym = i.op[0].disps->X_add_symbol;
3852 off = i.op[0].disps->X_add_number;
3e73aa7c 3853
29b0f896
AM		 3854 if (i.op[0].disps->X_op != O_constant
3855 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3856 {
29b0f896
AM		 3857 /* Handle complex expressions. */
3858 sym = make_expr_symbol (i.op[0].disps);
3859 off = 0;
3860 }
3e73aa7c 3861
29b0f896
AM		 3862 /* 1 possible extra opcode + 4 byte displacement go in var part.
3863 Pass reloc in fr_var. */
3864 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3865}
3e73aa7c 3866
29b0f896 3867static void
e3bb37b5 3868output_jump (void)
29b0f896
AM		 3869{
3870 char *p;
3871 int size;
3e02c1cc 3872 fixS *fixP;
29b0f896
AM		 3873
3874 if (i.tm.opcode_modifier & JumpByte)
3875 {
3876 /* This is a loop or jecxz type instruction. */
3877 size = 1;
3878 if (i.prefix[ADDR_PREFIX] != 0)
3879 {
3880 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3881 i.prefixes -= 1;
3882 }
3883 /* Pentium4 branch hints. */
3884 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3885 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3886 {
3887 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3888 i.prefixes--;
3e73aa7c
JH		 3889 }
3890 }
29b0f896
AM		 3891 else
3892 {
3893 int code16;
3e73aa7c 3894
29b0f896
AM		 3895 code16 = 0;
3896 if (flag_code == CODE_16BIT)
3897 code16 = CODE16;
3e73aa7c 3898
29b0f896
AM		 3899 if (i.prefix[DATA_PREFIX] != 0)
3900 {
3901 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3902 i.prefixes -= 1;
3903 code16 ^= CODE16;
3904 }
252b5132 3905
29b0f896
AM		 3906 size = 4;
3907 if (code16)
3908 size = 2;
3909 }
9fcc94b6 3910
29b0f896
AM		 3911 if (i.prefix[REX_PREFIX] != 0)
3912 {
3913 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3914 i.prefixes -= 1;
3915 }
252b5132 3916
29b0f896
AM		 3917 if (i.prefixes != 0 && !intel_syntax)
3918 as_warn (_("skipping prefixes on this instruction"));
e0890092 3919
29b0f896
AM		 3920 p = frag_more (1 + size);
3921 *p++ = i.tm.base_opcode;
e0890092 3922
3e02c1cc
AM		 3923 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3924 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3925
3926 /* All jumps handled here are signed, but don't use a signed limit
3927 check for 32 and 16 bit jumps as we want to allow wrap around at
3928 4G and 64k respectively. */
3929 if (size == 1)
3930 fixP->fx_signed = 1;
29b0f896 3931}
e0890092 3932
29b0f896 3933static void
e3bb37b5 3934output_interseg_jump (void)
29b0f896
AM		 3935{
3936 char *p;
3937 int size;
3938 int prefix;
3939 int code16;
252b5132 3940
29b0f896
AM		 3941 code16 = 0;
3942 if (flag_code == CODE_16BIT)
3943 code16 = CODE16;
a217f122 3944
29b0f896
AM		 3945 prefix = 0;
3946 if (i.prefix[DATA_PREFIX] != 0)
3947 {
3948 prefix = 1;
3949 i.prefixes -= 1;
3950 code16 ^= CODE16;
3951 }
3952 if (i.prefix[REX_PREFIX] != 0)
3953 {
3954 prefix++;
3955 i.prefixes -= 1;
3956 }
252b5132 3957
29b0f896
AM		 3958 size = 4;
3959 if (code16)
3960 size = 2;
252b5132 3961
29b0f896
AM		 3962 if (i.prefixes != 0 && !intel_syntax)
3963 as_warn (_("skipping prefixes on this instruction"));
252b5132 3964
29b0f896
AM		 3965 /* 1 opcode; 2 segment; offset */
3966 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3967
29b0f896
AM		 3968 if (i.prefix[DATA_PREFIX] != 0)
3969 *p++ = DATA_PREFIX_OPCODE;
252b5132 3970
29b0f896
AM		 3971 if (i.prefix[REX_PREFIX] != 0)
3972 *p++ = i.prefix[REX_PREFIX];
252b5132 3973
29b0f896
AM		 3974 *p++ = i.tm.base_opcode;
3975 if (i.op[1].imms->X_op == O_constant)
3976 {
3977 offsetT n = i.op[1].imms->X_add_number;
252b5132 3978
29b0f896
AM		 3979 if (size == 2
3980 && !fits_in_unsigned_word (n)
3981 && !fits_in_signed_word (n))
3982 {
3983 as_bad (_("16-bit jump out of range"));
3984 return;
3985 }
3986 md_number_to_chars (p, n, size);
3987 }
3988 else
3989 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3990 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3991 if (i.op[0].imms->X_op != O_constant)
3992 as_bad (_("can't handle non absolute segment in `%s'"),
3993 i.tm.name);
3994 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3995}
a217f122 3996
29b0f896 3997static void
e3bb37b5 3998output_insn (void)
29b0f896 3999{
2bbd9c25
JJ		 4000 fragS *insn_start_frag;
4001 offsetT insn_start_off;
4002
29b0f896
AM		 4003 /* Tie dwarf2 debug info to the address at the start of the insn.
4004 We can't do this after the insn has been output as the current
4005 frag may have been closed off. eg. by frag_var. */
4006 dwarf2_emit_insn (0);
4007
2bbd9c25
JJ		 4008 insn_start_frag = frag_now;
4009 insn_start_off = frag_now_fix ();
4010
29b0f896
AM		 4011 /* Output jumps. */
4012 if (i.tm.opcode_modifier & Jump)
4013 output_branch ();
4014 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
4015 output_jump ();
4016 else if (i.tm.opcode_modifier & JumpInterSegment)
4017 output_interseg_jump ();
4018 else
4019 {
4020 /* Output normal instructions here. */
4021 char *p;
4022 unsigned char *q;
331d2d0d 4023 unsigned int prefix;
252b5132 4024
42903f7f 4025 /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and
381d071f
L		 4026 SSE4 instructions have 3 bytes. We may use one more higher
4027 byte to specify a prefix the instruction requires. Exclude
4028 instructions which are in both SSE4 and ABM. */
4029 if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4)) != 0
4030 && (i.tm.cpu_flags & CpuABM) == 0)
bc4bd9ab 4031 {
331d2d0d
L		 4032 if (i.tm.base_opcode & 0xff000000)
4033 {
4034 prefix = (i.tm.base_opcode >> 24) & 0xff;
4035 goto check_prefix;
4036 }
4037 }
4038 else if ((i.tm.base_opcode & 0xff0000) != 0)
4039 {
4040 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 4041 if ((i.tm.cpu_flags & CpuPadLock) != 0)
4042 {
64e74474 4043 check_prefix:
bc4bd9ab
MK		 4044 if (prefix != REPE_PREFIX_OPCODE
4045 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
4046 add_prefix (prefix);
4047 }
4048 else
331d2d0d 4049 add_prefix (prefix);
0f10071e 4050 }
252b5132 4051
29b0f896
AM		 4052 /* The prefix bytes. */
4053 for (q = i.prefix;
4054 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
4055 q++)
4056 {
4057 if (*q)
4058 {
4059 p = frag_more (1);
4060 md_number_to_chars (p, (valueT) *q, 1);
4061 }
4062 }
252b5132 4063
29b0f896
AM		 4064 /* Now the opcode; be careful about word order here! */
4065 if (fits_in_unsigned_byte (i.tm.base_opcode))
4066 {
4067 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
4068 }
4069 else
4070 {
381d071f
L		 4071 if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4)) != 0
4072 && (i.tm.cpu_flags & CpuABM) == 0)
331d2d0d
L		 4073 {
4074 p = frag_more (3);
4075 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4076 }
4077 else
4078 p = frag_more (2);
0f10071e 4079
29b0f896
AM		 4080 /* Put out high byte first: can't use md_number_to_chars! */
4081 *p++ = (i.tm.base_opcode >> 8) & 0xff;
4082 *p = i.tm.base_opcode & 0xff;
4083 }
3e73aa7c 4084
29b0f896
AM		 4085 /* Now the modrm byte and sib byte (if present). */
4086 if (i.tm.opcode_modifier & Modrm)
4087 {
4088 p = frag_more (1);
4089 md_number_to_chars (p,
4090 (valueT) (i.rm.regmem << 0
4091 | i.rm.reg << 3
4092 | i.rm.mode << 6),
4093 1);
4094 /* If i.rm.regmem == ESP (4)
4095 && i.rm.mode != (Register mode)
4096 && not 16 bit
4097 ==> need second modrm byte. */
4098 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
4099 && i.rm.mode != 3
4100 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
4101 {
4102 p = frag_more (1);
4103 md_number_to_chars (p,
4104 (valueT) (i.sib.base << 0
4105 | i.sib.index << 3
4106 | i.sib.scale << 6),
4107 1);
4108 }
4109 }
3e73aa7c 4110
29b0f896 4111 if (i.disp_operands)
2bbd9c25 4112 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 4113
29b0f896 4114 if (i.imm_operands)
2bbd9c25 4115 output_imm (insn_start_frag, insn_start_off);
29b0f896 4116 }
252b5132 4117
29b0f896
AM		 4118#ifdef DEBUG386
4119 if (flag_debug)
4120 {
7b81dfbb 4121 pi ("" /*line*/, &i);
29b0f896
AM		 4122 }
4123#endif /* DEBUG386 */
4124}
252b5132 4125
e205caa7
L		 4126/* Return the size of the displacement operand N. */
4127
4128static int
4129disp_size (unsigned int n)
4130{
4131 int size = 4;
4132 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4133 {
4134 size = 2;
4135 if (i.types[n] & Disp8)
4136 size = 1;
4137 if (i.types[n] & Disp64)
4138 size = 8;
4139 }
4140 return size;
4141}
4142
4143/* Return the size of the immediate operand N. */
4144
4145static int
4146imm_size (unsigned int n)
4147{
4148 int size = 4;
4149 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4150 {
4151 size = 2;
4152 if (i.types[n] & (Imm8 | Imm8S))
4153 size = 1;
4154 if (i.types[n] & Imm64)
4155 size = 8;
4156 }
4157 return size;
4158}
4159
29b0f896 4160static void
64e74474 4161output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4162{
4163 char *p;
4164 unsigned int n;
252b5132 4165
29b0f896
AM		 4166 for (n = 0; n < i.operands; n++)
4167 {
4168 if (i.types[n] & Disp)
4169 {
4170 if (i.op[n].disps->X_op == O_constant)
4171 {
e205caa7 4172 int size = disp_size (n);
29b0f896 4173 offsetT val;
252b5132 4174
29b0f896
AM		 4175 val = offset_in_range (i.op[n].disps->X_add_number,
4176 size);
4177 p = frag_more (size);
4178 md_number_to_chars (p, val, size);
4179 }
4180 else
4181 {
f86103b7 4182 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 4183 int size = disp_size (n);
4184 int sign = (i.types[n] & Disp32S) != 0;
29b0f896
AM		 4185 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4186
e205caa7
L		 4187 /* We can't have 8 bit displacement here. */
4188 assert ((i.types[n] & Disp8) == 0);
4189
29b0f896
AM		 4190 /* The PC relative address is computed relative
4191 to the instruction boundary, so in case immediate
4192 fields follows, we need to adjust the value. */
4193 if (pcrel && i.imm_operands)
4194 {
29b0f896 4195 unsigned int n1;
e205caa7 4196 int sz = 0;
252b5132 4197
29b0f896
AM		 4198 for (n1 = 0; n1 < i.operands; n1++)
4199 if (i.types[n1] & Imm)
252b5132 4200 {
e205caa7
L		 4201 /* Only one immediate is allowed for PC
4202 relative address. */
4203 assert (sz == 0);
4204 sz = imm_size (n1);
4205 i.op[n].disps->X_add_number -= sz;
252b5132 4206 }
29b0f896 4207 /* We should find the immediate. */
e205caa7 4208 assert (sz != 0);
29b0f896 4209 }
520dc8e8 4210
29b0f896 4211 p = frag_more (size);
2bbd9c25 4212 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4213 if (GOT_symbol
2bbd9c25 4214 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4215 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4216 || reloc_type == BFD_RELOC_X86_64_32S
4217 || (reloc_type == BFD_RELOC_64
4218 && object_64bit))
d6ab8113
JB		 4219 && (i.op[n].disps->X_op == O_symbol
4220 || (i.op[n].disps->X_op == O_add
4221 && ((symbol_get_value_expression
4222 (i.op[n].disps->X_op_symbol)->X_op)
4223 == O_subtract))))
4224 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4225 {
4226 offsetT add;
4227
4228 if (insn_start_frag == frag_now)
4229 add = (p - frag_now->fr_literal) - insn_start_off;
4230 else
4231 {
4232 fragS *fr;
4233
4234 add = insn_start_frag->fr_fix - insn_start_off;
4235 for (fr = insn_start_frag->fr_next;
4236 fr && fr != frag_now; fr = fr->fr_next)
4237 add += fr->fr_fix;
4238 add += p - frag_now->fr_literal;
4239 }
4240
4fa24527 4241 if (!object_64bit)
7b81dfbb
AJ		 4242 {
4243 reloc_type = BFD_RELOC_386_GOTPC;
4244 i.op[n].imms->X_add_number += add;
4245 }
4246 else if (reloc_type == BFD_RELOC_64)
4247 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4248 else
7b81dfbb
AJ		 4249 /* Don't do the adjustment for x86-64, as there
4250 the pcrel addressing is relative to the _next_
4251 insn, and that is taken care of in other code. */
d6ab8113 4252 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4253 }
062cd5e7 4254 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4255 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4256 }
4257 }
4258 }
4259}
252b5132 4260
29b0f896 4261static void
64e74474 4262output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4263{
4264 char *p;
4265 unsigned int n;
252b5132 4266
29b0f896
AM		 4267 for (n = 0; n < i.operands; n++)
4268 {
4269 if (i.types[n] & Imm)
4270 {
4271 if (i.op[n].imms->X_op == O_constant)
4272 {
e205caa7 4273 int size = imm_size (n);
29b0f896 4274 offsetT val;
b4cac588 4275
29b0f896
AM		 4276 val = offset_in_range (i.op[n].imms->X_add_number,
4277 size);
4278 p = frag_more (size);
4279 md_number_to_chars (p, val, size);
4280 }
4281 else
4282 {
4283 /* Not absolute_section.
4284 Need a 32-bit fixup (don't support 8bit
4285 non-absolute imms). Try to support other
4286 sizes ... */
f86103b7 4287 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 4288 int size = imm_size (n);
4289 int sign;
29b0f896
AM		 4290
4291 if ((i.types[n] & (Imm32S))
a7d61044
JB		 4292 && (i.suffix == QWORD_MNEM_SUFFIX
4293 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896 4294 sign = 1;
e205caa7
L		 4295 else
4296 sign = 0;
520dc8e8 4297
29b0f896
AM		 4298 p = frag_more (size);
4299 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4300
2bbd9c25
JJ		 4301 /* This is tough to explain. We end up with this one if we
4302 * have operands that look like
4303 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4304 * obtain the absolute address of the GOT, and it is strongly
4305 * preferable from a performance point of view to avoid using
4306 * a runtime relocation for this. The actual sequence of
4307 * instructions often look something like:
4308 *
4309 * call .L66
4310 * .L66:
4311 * popl %ebx
4312 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4313 *
4314 * The call and pop essentially return the absolute address
4315 * of the label .L66 and store it in %ebx. The linker itself
4316 * will ultimately change the first operand of the addl so
4317 * that %ebx points to the GOT, but to keep things simple, the
4318 * .o file must have this operand set so that it generates not
4319 * the absolute address of .L66, but the absolute address of
4320 * itself. This allows the linker itself simply treat a GOTPC
4321 * relocation as asking for a pcrel offset to the GOT to be
4322 * added in, and the addend of the relocation is stored in the
4323 * operand field for the instruction itself.
4324 *
4325 * Our job here is to fix the operand so that it would add
4326 * the correct offset so that %ebx would point to itself. The
4327 * thing that is tricky is that .-.L66 will point to the
4328 * beginning of the instruction, so we need to further modify
4329 * the operand so that it will point to itself. There are
4330 * other cases where you have something like:
4331 *
4332 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4333 *
4334 * and here no correction would be required. Internally in
4335 * the assembler we treat operands of this form as not being
4336 * pcrel since the '.' is explicitly mentioned, and I wonder
4337 * whether it would simplify matters to do it this way. Who
4338 * knows. In earlier versions of the PIC patches, the
4339 * pcrel_adjust field was used to store the correction, but
4340 * since the expression is not pcrel, I felt it would be
4341 * confusing to do it this way. */
4342
d6ab8113 4343 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4344 || reloc_type == BFD_RELOC_X86_64_32S
4345 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4346 && GOT_symbol
4347 && GOT_symbol == i.op[n].imms->X_add_symbol
4348 && (i.op[n].imms->X_op == O_symbol
4349 || (i.op[n].imms->X_op == O_add
4350 && ((symbol_get_value_expression
4351 (i.op[n].imms->X_op_symbol)->X_op)
4352 == O_subtract))))
4353 {
2bbd9c25
JJ		 4354 offsetT add;
4355
4356 if (insn_start_frag == frag_now)
4357 add = (p - frag_now->fr_literal) - insn_start_off;
4358 else
4359 {
4360 fragS *fr;
4361
4362 add = insn_start_frag->fr_fix - insn_start_off;
4363 for (fr = insn_start_frag->fr_next;
4364 fr && fr != frag_now; fr = fr->fr_next)
4365 add += fr->fr_fix;
4366 add += p - frag_now->fr_literal;
4367 }
4368
4fa24527 4369 if (!object_64bit)
d6ab8113 4370 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4371 else if (size == 4)
d6ab8113 4372 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4373 else if (size == 8)
4374 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4375 i.op[n].imms->X_add_number += add;
29b0f896 4376 }
29b0f896
AM		 4377 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4378 i.op[n].imms, 0, reloc_type);
4379 }
4380 }
4381 }
252b5132
RH		 4382}
4383\f
d182319b
JB		 4384/* x86_cons_fix_new is called via the expression parsing code when a
4385 reloc is needed. We use this hook to get the correct .got reloc. */
4386static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4387static int cons_sign = -1;
4388
4389void
e3bb37b5 4390x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 4391 expressionS *exp)
d182319b
JB		 4392{
4393 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4394
4395 got_reloc = NO_RELOC;
4396
4397#ifdef TE_PE
4398 if (exp->X_op == O_secrel)
4399 {
4400 exp->X_op = O_symbol;
4401 r = BFD_RELOC_32_SECREL;
4402 }
4403#endif
4404
4405 fix_new_exp (frag, off, len, exp, 0, r);
4406}
4407
718ddfc0
JB		 4408#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4409# define lex_got(reloc, adjust, types) NULL
4410#else
f3c180ae
AM		 4411/* Parse operands of the form
4412 <symbol>@GOTOFF+<nnn>
4413 and similar .plt or .got references.
4414
4415 If we find one, set up the correct relocation in RELOC and copy the
4416 input string, minus the `@GOTOFF' into a malloc'd buffer for
4417 parsing by the calling routine. Return this buffer, and if ADJUST
4418 is non-null set it to the length of the string we removed from the
4419 input line. Otherwise return NULL. */
4420static char *
3956db08 4421lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 4422 int *adjust,
4423 unsigned int *types)
f3c180ae 4424{
7b81dfbb
AJ		 4425 /* Some of the relocations depend on the size of what field is to
4426 be relocated. But in our callers i386_immediate and i386_displacement
4427 we don't yet know the operand size (this will be set by insn
4428 matching). Hence we record the word32 relocation here,
4429 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4430 static const struct {
4431 const char *str;
4fa24527 4432 const enum bfd_reloc_code_real rel[2];
3956db08 4433 const unsigned int types64;
f3c180ae 4434 } gotrel[] = {
4eed87de
AM		 4435 { "PLTOFF", { 0,
4436 BFD_RELOC_X86_64_PLTOFF64 },
4437 Imm64 },
4438 { "PLT", { BFD_RELOC_386_PLT32,
4439 BFD_RELOC_X86_64_PLT32 },
4440 Imm32 | Imm32S | Disp32 },
4441 { "GOTPLT", { 0,
4442 BFD_RELOC_X86_64_GOTPLT64 },
4443 Imm64 | Disp64 },
4444 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
4445 BFD_RELOC_X86_64_GOTOFF64 },
4446 Imm64 | Disp64 },
4447 { "GOTPCREL", { 0,
4448 BFD_RELOC_X86_64_GOTPCREL },
4449 Imm32 | Imm32S | Disp32 },
4450 { "TLSGD", { BFD_RELOC_386_TLS_GD,
4451 BFD_RELOC_X86_64_TLSGD },
4452 Imm32 | Imm32S | Disp32 },
4453 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
4454 0 },
4455 0 },
4456 { "TLSLD", { 0,
4457 BFD_RELOC_X86_64_TLSLD },
4458 Imm32 | Imm32S | Disp32 },
4459 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
4460 BFD_RELOC_X86_64_GOTTPOFF },
4461 Imm32 | Imm32S | Disp32 },
4462 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
4463 BFD_RELOC_X86_64_TPOFF32 },
4464 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4465 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
4466 0 },
4467 0 },
4468 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
4469 BFD_RELOC_X86_64_DTPOFF32 },
4470 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4471 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
4472 0 },
4473 0 },
4474 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
4475 0 },
4476 0 },
4477 { "GOT", { BFD_RELOC_386_GOT32,
4478 BFD_RELOC_X86_64_GOT32 },
4479 Imm32 | Imm32S | Disp32 | Imm64 },
4480 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
4481 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
4482 Imm32 | Imm32S | Disp32 },
4483 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
4484 BFD_RELOC_X86_64_TLSDESC_CALL },
4485 Imm32 | Imm32S | Disp32 }
f3c180ae
AM		 4486 };
4487 char *cp;
4488 unsigned int j;
4489
718ddfc0
JB		 4490 if (!IS_ELF)
4491 return NULL;
4492
f3c180ae 4493 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 4494 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 4495 return NULL;
4496
4497 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4498 {
4499 int len;
4500
4501 len = strlen (gotrel[j].str);
28f81592 4502 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4503 {
4fa24527 4504 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4505 {
28f81592
AM		 4506 int first, second;
4507 char *tmpbuf, *past_reloc;
f3c180ae 4508
4fa24527 4509 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 4510 if (adjust)
4511 *adjust = len;
f3c180ae 4512
3956db08
JB		 4513 if (types)
4514 {
4515 if (flag_code != CODE_64BIT)
4eed87de 4516 *types = Imm32 | Disp32;
3956db08
JB		 4517 else
4518 *types = gotrel[j].types64;
4519 }
4520
f3c180ae
AM		 4521 if (GOT_symbol == NULL)
4522 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4523
28f81592 4524 /* The length of the first part of our input line. */
f3c180ae 4525 first = cp - input_line_pointer;
28f81592
AM		 4526
4527 /* The second part goes from after the reloc token until
67c11a9b 4528 (and including) an end_of_line char or comma. */
28f81592 4529 past_reloc = cp + 1 + len;
67c11a9b
AM		 4530 cp = past_reloc;
4531 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
4532 ++cp;
4533 second = cp + 1 - past_reloc;
28f81592
AM		 4534
4535 /* Allocate and copy string. The trailing NUL shouldn't
4536 be necessary, but be safe. */
4537 tmpbuf = xmalloc (first + second + 2);
f3c180ae 4538 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 4539 if (second != 0 && *past_reloc != ' ')
4540 /* Replace the relocation token with ' ', so that
4541 errors like foo@GOTOFF1 will be detected. */
4542 tmpbuf[first++] = ' ';
4543 memcpy (tmpbuf + first, past_reloc, second);
4544 tmpbuf[first + second] = '\0';
f3c180ae
AM		 4545 return tmpbuf;
4546 }
4547
4fa24527
JB		 4548 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4549 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 4550 return NULL;
4551 }
4552 }
4553
4554 /* Might be a symbol version string. Don't as_bad here. */
4555 return NULL;
4556}
4557
f3c180ae 4558void
e3bb37b5 4559x86_cons (expressionS *exp, int size)
f3c180ae 4560{
4fa24527 4561 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 4562 {
4563 /* Handle @GOTOFF and the like in an expression. */
4564 char *save;
4565 char *gotfree_input_line;
4566 int adjust;
4567
4568 save = input_line_pointer;
3956db08 4569 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4570 if (gotfree_input_line)
4571 input_line_pointer = gotfree_input_line;
4572
4573 expression (exp);
4574
4575 if (gotfree_input_line)
4576 {
4577 /* expression () has merrily parsed up to the end of line,
4578 or a comma - in the wrong buffer. Transfer how far
4579 input_line_pointer has moved to the right buffer. */
4580 input_line_pointer = (save
4581 + (input_line_pointer - gotfree_input_line)
4582 + adjust);
4583 free (gotfree_input_line);
3992d3b7
AM		 4584 if (exp->X_op == O_constant
4585 || exp->X_op == O_absent
4586 || exp->X_op == O_illegal
4587 || exp->X_op == O_register
4588 || exp->X_op == O_big)
4589 {
4590 char c = *input_line_pointer;
4591 *input_line_pointer = 0;
4592 as_bad (_("missing or invalid expression `%s'"), save);
4593 *input_line_pointer = c;
4594 }
f3c180ae
AM		 4595 }
4596 }
4597 else
4598 expression (exp);
4599}
4600#endif
4601
d182319b 4602static void signed_cons (int size)
6482c264 4603{
d182319b
JB		 4604 if (flag_code == CODE_64BIT)
4605 cons_sign = 1;
4606 cons (size);
4607 cons_sign = -1;
6482c264
NC		 4608}
4609
d182319b 4610#ifdef TE_PE
6482c264
NC		 4611static void
4612pe_directive_secrel (dummy)
4613 int dummy ATTRIBUTE_UNUSED;
4614{
4615 expressionS exp;
4616
4617 do
4618 {
4619 expression (&exp);
4620 if (exp.X_op == O_symbol)
4621 exp.X_op = O_secrel;
4622
4623 emit_expr (&exp, 4);
4624 }
4625 while (*input_line_pointer++ == ',');
4626
4627 input_line_pointer--;
4628 demand_empty_rest_of_line ();
4629}
6482c264
NC		 4630#endif
4631
252b5132 4632static int
70e41ade 4633i386_immediate (char *imm_start)
252b5132
RH		 4634{
4635 char *save_input_line_pointer;
f3c180ae 4636 char *gotfree_input_line;
252b5132 4637 segT exp_seg = 0;
47926f60 4638 expressionS *exp;
3956db08 4639 unsigned int types = ~0U;
252b5132
RH		 4640
4641 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4642 {
31b2323c
L		 4643 as_bad (_("at most %d immediate operands are allowed"),
4644 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 4645 return 0;
4646 }
4647
4648 exp = &im_expressions[i.imm_operands++];
520dc8e8 4649 i.op[this_operand].imms = exp;
252b5132
RH		 4650
4651 if (is_space_char (*imm_start))
4652 ++imm_start;
4653
4654 save_input_line_pointer = input_line_pointer;
4655 input_line_pointer = imm_start;
4656
3956db08 4657 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4658 if (gotfree_input_line)
4659 input_line_pointer = gotfree_input_line;
252b5132
RH		 4660
4661 exp_seg = expression (exp);
4662
83183c0c 4663 SKIP_WHITESPACE ();
252b5132 4664 if (*input_line_pointer)
f3c180ae 4665 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4666
4667 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4668 if (gotfree_input_line)
4669 free (gotfree_input_line);
252b5132 4670
3992d3b7
AM		 4671 if (exp->X_op == O_absent
4672 || exp->X_op == O_illegal
4673 || exp->X_op == O_big
4674 || (gotfree_input_line
4675 && (exp->X_op == O_constant
4676 || exp->X_op == O_register)))
252b5132 4677 {
3992d3b7 4678 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 4679 imm_start);
3992d3b7 4680 return 0;
252b5132 4681 }
3e73aa7c 4682 else if (exp->X_op == O_constant)
252b5132 4683 {
47926f60 4684 /* Size it properly later. */
3e73aa7c
JH		 4685 i.types[this_operand] |= Imm64;
4686 /* If BFD64, sign extend val. */
4eed87de
AM		 4687 if (!use_rela_relocations
4688 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4689 exp->X_add_number
4690 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4691 }
4c63da97 4692#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4693 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4694 && exp_seg != absolute_section
47926f60 4695 && exp_seg != text_section
24eab124
AM		 4696 && exp_seg != data_section
4697 && exp_seg != bss_section
4698 && exp_seg != undefined_section
f86103b7 4699 && !bfd_is_com_section (exp_seg))
252b5132 4700 {
d0b47220 4701 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4702 return 0;
4703 }
4704#endif
bb8f5920
L		 4705 else if (!intel_syntax && exp->X_op == O_register)
4706 {
4707 as_bad (_("illegal immediate register operand %s"), imm_start);
4708 return 0;
4709 }
252b5132
RH		 4710 else
4711 {
4712 /* This is an address. The size of the address will be
24eab124 4713 determined later, depending on destination register,
3e73aa7c
JH		 4714 suffix, or the default for the section. */
4715 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4716 i.types[this_operand] &= types;
252b5132
RH		 4717 }
4718
4719 return 1;
4720}
4721
551c1ca1 4722static char *
e3bb37b5 4723i386_scale (char *scale)
252b5132 4724{
551c1ca1
AM		 4725 offsetT val;
4726 char *save = input_line_pointer;
252b5132 4727
551c1ca1
AM		 4728 input_line_pointer = scale;
4729 val = get_absolute_expression ();
4730
4731 switch (val)
252b5132 4732 {
551c1ca1 4733 case 1:
252b5132
RH		 4734 i.log2_scale_factor = 0;
4735 break;
551c1ca1 4736 case 2:
252b5132
RH		 4737 i.log2_scale_factor = 1;
4738 break;
551c1ca1 4739 case 4:
252b5132
RH		 4740 i.log2_scale_factor = 2;
4741 break;
551c1ca1 4742 case 8:
252b5132
RH		 4743 i.log2_scale_factor = 3;
4744 break;
4745 default:
a724f0f4
JB		 4746 {
4747 char sep = *input_line_pointer;
4748
4749 *input_line_pointer = '\0';
4750 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4751 scale);
4752 *input_line_pointer = sep;
4753 input_line_pointer = save;
4754 return NULL;
4755 }
252b5132 4756 }
29b0f896 4757 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4758 {
4759 as_warn (_("scale factor of %d without an index register"),
24eab124 4760 1 << i.log2_scale_factor);
252b5132
RH		 4761#if SCALE1_WHEN_NO_INDEX
4762 i.log2_scale_factor = 0;
4763#endif
4764 }
551c1ca1
AM		 4765 scale = input_line_pointer;
4766 input_line_pointer = save;
4767 return scale;
252b5132
RH		 4768}
4769
252b5132 4770static int
e3bb37b5 4771i386_displacement (char *disp_start, char *disp_end)
252b5132 4772{
29b0f896 4773 expressionS *exp;
252b5132
RH		 4774 segT exp_seg = 0;
4775 char *save_input_line_pointer;
f3c180ae 4776 char *gotfree_input_line;
e05278af 4777 int bigdisp, override;
3956db08 4778 unsigned int types = Disp;
3992d3b7 4779 int ret;
252b5132 4780
31b2323c
L		 4781 if (i.disp_operands == MAX_MEMORY_OPERANDS)
4782 {
4783 as_bad (_("at most %d displacement operands are allowed"),
4784 MAX_MEMORY_OPERANDS);
4785 return 0;
4786 }
4787
e05278af
JB		 4788 if ((i.types[this_operand] & JumpAbsolute)
4789 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4790 {
4791 bigdisp = Disp32;
4792 override = (i.prefix[ADDR_PREFIX] != 0);
4793 }
4794 else
4795 {
4796 /* For PC-relative branches, the width of the displacement
4797 is dependent upon data size, not address size. */
4798 bigdisp = 0;
4799 override = (i.prefix[DATA_PREFIX] != 0);
4800 }
3e73aa7c 4801 if (flag_code == CODE_64BIT)
7ecd2f8b 4802 {
e05278af 4803 if (!bigdisp)
64e74474
AM		 4804 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4805 ? Disp16
4806 : Disp32S | Disp32);
e05278af 4807 else if (!override)
3956db08 4808 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4809 }
e05278af
JB		 4810 else
4811 {
4812 if (!bigdisp)
4813 {
4814 if (!override)
4815 override = (i.suffix == (flag_code != CODE_16BIT
4816 ? WORD_MNEM_SUFFIX
4817 : LONG_MNEM_SUFFIX));
4818 bigdisp = Disp32;
4819 }
4820 if ((flag_code == CODE_16BIT) ^ override)
4821 bigdisp = Disp16;
4822 }
252b5132
RH		 4823 i.types[this_operand] |= bigdisp;
4824
4825 exp = &disp_expressions[i.disp_operands];
520dc8e8 4826 i.op[this_operand].disps = exp;
252b5132
RH		 4827 i.disp_operands++;
4828 save_input_line_pointer = input_line_pointer;
4829 input_line_pointer = disp_start;
4830 END_STRING_AND_SAVE (disp_end);
4831
4832#ifndef GCC_ASM_O_HACK
4833#define GCC_ASM_O_HACK 0
4834#endif
4835#if GCC_ASM_O_HACK
4836 END_STRING_AND_SAVE (disp_end + 1);
4837 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4838 && displacement_string_end[-1] == '+')
252b5132
RH		 4839 {
4840 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4841 constraint within gcc asm statements.
4842 For instance:
4843
4844 #define _set_tssldt_desc(n,addr,limit,type) \
4845 __asm__ __volatile__ ( \
4846 "movw %w2,%0\n\t" \
4847 "movw %w1,2+%0\n\t" \
4848 "rorl $16,%1\n\t" \
4849 "movb %b1,4+%0\n\t" \
4850 "movb %4,5+%0\n\t" \
4851 "movb $0,6+%0\n\t" \
4852 "movb %h1,7+%0\n\t" \
4853 "rorl $16,%1" \
4854 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4855
4856 This works great except that the output assembler ends
4857 up looking a bit weird if it turns out that there is
4858 no offset. You end up producing code that looks like:
4859
4860 #APP
4861 movw $235,(%eax)
4862 movw %dx,2+(%eax)
4863 rorl $16,%edx
4864 movb %dl,4+(%eax)
4865 movb $137,5+(%eax)
4866 movb $0,6+(%eax)
4867 movb %dh,7+(%eax)
4868 rorl $16,%edx
4869 #NO_APP
4870
47926f60 4871 So here we provide the missing zero. */
24eab124
AM		 4872
4873 *displacement_string_end = '0';
252b5132
RH		 4874 }
4875#endif
3956db08 4876 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4877 if (gotfree_input_line)
4878 input_line_pointer = gotfree_input_line;
252b5132 4879
24eab124 4880 exp_seg = expression (exp);
252b5132 4881
636c26b0
AM		 4882 SKIP_WHITESPACE ();
4883 if (*input_line_pointer)
4884 as_bad (_("junk `%s' after expression"), input_line_pointer);
4885#if GCC_ASM_O_HACK
4886 RESTORE_END_STRING (disp_end + 1);
4887#endif
636c26b0 4888 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4889 if (gotfree_input_line)
4890 free (gotfree_input_line);
3992d3b7 4891 ret = 1;
636c26b0 4892
24eab124
AM		 4893 /* We do this to make sure that the section symbol is in
4894 the symbol table. We will ultimately change the relocation
47926f60 4895 to be relative to the beginning of the section. */
1ae12ab7 4896 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4897 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4898 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4899 {
636c26b0 4900 if (exp->X_op != O_symbol)
3992d3b7 4901 goto inv_disp;
636c26b0 4902
e5cb08ac 4903 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4904 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4905 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4906 exp->X_op = O_subtract;
4907 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4908 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4909 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4910 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4911 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4912 else
29b0f896 4913 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4914 }
252b5132 4915
3992d3b7
AM		 4916 else if (exp->X_op == O_absent
4917 || exp->X_op == O_illegal
4918 || exp->X_op == O_big
4919 || (gotfree_input_line
4920 && (exp->X_op == O_constant
4921 || exp->X_op == O_register)))
2daf4fd8 4922 {
3992d3b7
AM		 4923 inv_disp:
4924 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 4925 disp_start);
3992d3b7 4926 ret = 0;
2daf4fd8
AM		 4927 }
4928
4c63da97 4929#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 4930 else if (exp->X_op != O_constant
4931 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4932 && exp_seg != absolute_section
4933 && exp_seg != text_section
4934 && exp_seg != data_section
4935 && exp_seg != bss_section
4936 && exp_seg != undefined_section
4937 && !bfd_is_com_section (exp_seg))
24eab124 4938 {
d0b47220 4939 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 4940 ret = 0;
24eab124 4941 }
252b5132 4942#endif
3956db08 4943
3992d3b7
AM		 4944 RESTORE_END_STRING (disp_end);
4945
3956db08
JB		 4946 if (!(i.types[this_operand] & ~Disp))
4947 i.types[this_operand] &= types;
4948
3992d3b7 4949 return ret;
252b5132
RH		 4950}
4951
eecb386c 4952/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4953 Return 1 on success, 0 on a failure. */
4954
252b5132 4955static int
e3bb37b5 4956i386_index_check (const char *operand_string)
252b5132 4957{
3e73aa7c 4958 int ok;
24eab124 4959#if INFER_ADDR_PREFIX
eecb386c
AM		 4960 int fudged = 0;
4961
24eab124
AM		 4962 tryprefix:
4963#endif
3e73aa7c 4964 ok = 1;
30123838
JB		 4965 if ((current_templates->start->cpu_flags & CpuSVME)
4966 && current_templates->end[-1].operand_types[0] == AnyMem)
4967 {
4968 /* Memory operands of SVME insns are special in that they only allow
4969 rAX as their memory address and ignore any segment override. */
4970 unsigned RegXX;
4971
4972 /* SKINIT is even more restrictive: it always requires EAX. */
4973 if (strcmp (current_templates->start->name, "skinit") == 0)
4974 RegXX = Reg32;
4975 else if (flag_code == CODE_64BIT)
4976 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4977 else
64e74474
AM		 4978 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4979 ? Reg16
4980 : Reg32);
30123838
JB		 4981 if (!i.base_reg
4982 || !(i.base_reg->reg_type & Acc)
4983 || !(i.base_reg->reg_type & RegXX)
4984 || i.index_reg
4985 || (i.types[0] & Disp))
4986 ok = 0;
4987 }
4988 else if (flag_code == CODE_64BIT)
64e74474
AM		 4989 {
4990 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4991
4992 if ((i.base_reg
4993 && ((i.base_reg->reg_type & RegXX) == 0)
4994 && (i.base_reg->reg_type != BaseIndex
4995 || i.index_reg))
4996 || (i.index_reg
4997 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4998 != (RegXX | BaseIndex))))
4999 ok = 0;
3e73aa7c
JH		 5000 }
5001 else
5002 {
5003 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
5004 {
5005 /* 16bit checks. */
5006 if ((i.base_reg
29b0f896
AM		 5007 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
5008 != (Reg16 | BaseIndex)))
3e73aa7c 5009 || (i.index_reg
29b0f896
AM		 5010 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
5011 != (Reg16 | BaseIndex))
5012 || !(i.base_reg
5013 && i.base_reg->reg_num < 6
5014 && i.index_reg->reg_num >= 6
5015 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 5016 ok = 0;
5017 }
5018 else
e5cb08ac 5019 {
3e73aa7c
JH		 5020 /* 32bit checks. */
5021 if ((i.base_reg
5022 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
5023 || (i.index_reg
29b0f896
AM		 5024 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
5025 != (Reg32 | BaseIndex))))
e5cb08ac 5026 ok = 0;
3e73aa7c
JH		 5027 }
5028 }
5029 if (!ok)
24eab124
AM		 5030 {
5031#if INFER_ADDR_PREFIX
20f0a1fc 5032 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 5033 {
5034 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
5035 i.prefixes += 1;
b23bac36
AM		 5036 /* Change the size of any displacement too. At most one of
5037 Disp16 or Disp32 is set.
5038 FIXME. There doesn't seem to be any real need for separate
5039 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 5040 Removing them would probably clean up the code quite a lot. */
4eed87de
AM		 5041 if (flag_code != CODE_64BIT
5042 && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 5043 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 5044 fudged = 1;
24eab124
AM		 5045 goto tryprefix;
5046 }
eecb386c
AM		 5047 if (fudged)
5048 as_bad (_("`%s' is not a valid base/index expression"),
5049 operand_string);
5050 else
c388dee8 5051#endif
eecb386c
AM		 5052 as_bad (_("`%s' is not a valid %s bit base/index expression"),
5053 operand_string,
3e73aa7c 5054 flag_code_names[flag_code]);
24eab124 5055 }
20f0a1fc 5056 return ok;
24eab124 5057}
252b5132 5058
252b5132 5059/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 5060 on error. */
252b5132 5061
252b5132 5062static int
e3bb37b5 5063i386_operand (char *operand_string)
252b5132 5064{
af6bdddf
AM		 5065 const reg_entry *r;
5066 char *end_op;
24eab124 5067 char *op_string = operand_string;
252b5132 5068
24eab124 5069 if (is_space_char (*op_string))
252b5132
RH		 5070 ++op_string;
5071
24eab124 5072 /* We check for an absolute prefix (differentiating,
47926f60 5073 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 5074 if (*op_string == ABSOLUTE_PREFIX)
5075 {
5076 ++op_string;
5077 if (is_space_char (*op_string))
5078 ++op_string;
5079 i.types[this_operand] |= JumpAbsolute;
5080 }
252b5132 5081
47926f60 5082 /* Check if operand is a register. */
4d1bb795 5083 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 5084 {
24eab124
AM		 5085 /* Check for a segment override by searching for ':' after a
5086 segment register. */
5087 op_string = end_op;
5088 if (is_space_char (*op_string))
5089 ++op_string;
5090 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
5091 {
5092 switch (r->reg_num)
5093 {
5094 case 0:
5095 i.seg[i.mem_operands] = &es;
5096 break;
5097 case 1:
5098 i.seg[i.mem_operands] = &cs;
5099 break;
5100 case 2:
5101 i.seg[i.mem_operands] = &ss;
5102 break;
5103 case 3:
5104 i.seg[i.mem_operands] = &ds;
5105 break;
5106 case 4:
5107 i.seg[i.mem_operands] = &fs;
5108 break;
5109 case 5:
5110 i.seg[i.mem_operands] = &gs;
5111 break;
5112 }
252b5132 5113
24eab124 5114 /* Skip the ':' and whitespace. */
252b5132
RH		 5115 ++op_string;
5116 if (is_space_char (*op_string))
24eab124 5117 ++op_string;
252b5132 5118
24eab124
AM		 5119 if (!is_digit_char (*op_string)
5120 && !is_identifier_char (*op_string)
5121 && *op_string != '('
5122 && *op_string != ABSOLUTE_PREFIX)
5123 {
5124 as_bad (_("bad memory operand `%s'"), op_string);
5125 return 0;
5126 }
47926f60 5127 /* Handle case of %es:*foo. */
24eab124
AM		 5128 if (*op_string == ABSOLUTE_PREFIX)
5129 {
5130 ++op_string;
5131 if (is_space_char (*op_string))
5132 ++op_string;
5133 i.types[this_operand] |= JumpAbsolute;
5134 }
5135 goto do_memory_reference;
5136 }
5137 if (*op_string)
5138 {
d0b47220 5139 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 5140 return 0;
5141 }
5142 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 5143 i.op[this_operand].regs = r;
24eab124
AM		 5144 i.reg_operands++;
5145 }
af6bdddf
AM		 5146 else if (*op_string == REGISTER_PREFIX)
5147 {
5148 as_bad (_("bad register name `%s'"), op_string);
5149 return 0;
5150 }
24eab124 5151 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 5152 {
24eab124
AM		 5153 ++op_string;
5154 if (i.types[this_operand] & JumpAbsolute)
5155 {
d0b47220 5156 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 5157 return 0;
5158 }
5159 if (!i386_immediate (op_string))
5160 return 0;
5161 }
5162 else if (is_digit_char (*op_string)
5163 || is_identifier_char (*op_string)
e5cb08ac 5164 || *op_string == '(')
24eab124 5165 {
47926f60 5166 /* This is a memory reference of some sort. */
af6bdddf 5167 char *base_string;
252b5132 5168
47926f60 5169 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 5170 char *displacement_string_start;
5171 char *displacement_string_end;
252b5132 5172
24eab124 5173 do_memory_reference:
24eab124
AM		 5174 if ((i.mem_operands == 1
5175 && (current_templates->start->opcode_modifier & IsString) == 0)
5176 || i.mem_operands == 2)
5177 {
5178 as_bad (_("too many memory references for `%s'"),
5179 current_templates->start->name);
5180 return 0;
5181 }
252b5132 5182
24eab124
AM		 5183 /* Check for base index form. We detect the base index form by
5184 looking for an ')' at the end of the operand, searching
5185 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5186 after the '('. */
af6bdddf 5187 base_string = op_string + strlen (op_string);
c3332e24 5188
af6bdddf
AM		 5189 --base_string;
5190 if (is_space_char (*base_string))
5191 --base_string;
252b5132 5192
47926f60 5193 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 5194 displacement_string_start = op_string;
5195 displacement_string_end = base_string + 1;
252b5132 5196
24eab124
AM		 5197 if (*base_string == ')')
5198 {
af6bdddf 5199 char *temp_string;
24eab124
AM		 5200 unsigned int parens_balanced = 1;
5201 /* We've already checked that the number of left & right ()'s are
47926f60 5202 equal, so this loop will not be infinite. */
24eab124
AM		 5203 do
5204 {
5205 base_string--;
5206 if (*base_string == ')')
5207 parens_balanced++;
5208 if (*base_string == '(')
5209 parens_balanced--;
5210 }
5211 while (parens_balanced);
c3332e24 5212
af6bdddf 5213 temp_string = base_string;
c3332e24 5214
24eab124 5215 /* Skip past '(' and whitespace. */
252b5132
RH		 5216 ++base_string;
5217 if (is_space_char (*base_string))
24eab124 5218 ++base_string;
252b5132 5219
af6bdddf 5220 if (*base_string == ','
4eed87de
AM		 5221 || ((i.base_reg = parse_register (base_string, &end_op))
5222 != NULL))
252b5132 5223 {
af6bdddf 5224 displacement_string_end = temp_string;
252b5132 5225
af6bdddf 5226 i.types[this_operand] |= BaseIndex;
252b5132 5227
af6bdddf 5228 if (i.base_reg)
24eab124 5229 {
24eab124
AM		 5230 base_string = end_op;
5231 if (is_space_char (*base_string))
5232 ++base_string;
af6bdddf
AM		 5233 }
5234
5235 /* There may be an index reg or scale factor here. */
5236 if (*base_string == ',')
5237 {
5238 ++base_string;
5239 if (is_space_char (*base_string))
5240 ++base_string;
5241
4eed87de
AM		 5242 if ((i.index_reg = parse_register (base_string, &end_op))
5243 != NULL)
24eab124 5244 {
af6bdddf 5245 base_string = end_op;
24eab124
AM		 5246 if (is_space_char (*base_string))
5247 ++base_string;
af6bdddf
AM		 5248 if (*base_string == ',')
5249 {
5250 ++base_string;
5251 if (is_space_char (*base_string))
5252 ++base_string;
5253 }
e5cb08ac 5254 else if (*base_string != ')')
af6bdddf 5255 {
4eed87de
AM		 5256 as_bad (_("expecting `,' or `)' "
5257 "after index register in `%s'"),
af6bdddf
AM		 5258 operand_string);
5259 return 0;
5260 }
24eab124 5261 }
af6bdddf 5262 else if (*base_string == REGISTER_PREFIX)
24eab124 5263 {
af6bdddf 5264 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5265 return 0;
5266 }
252b5132 5267
47926f60 5268 /* Check for scale factor. */
551c1ca1 5269 if (*base_string != ')')
af6bdddf 5270 {
551c1ca1
AM		 5271 char *end_scale = i386_scale (base_string);
5272
5273 if (!end_scale)
af6bdddf 5274 return 0;
24eab124 5275
551c1ca1 5276 base_string = end_scale;
af6bdddf
AM		 5277 if (is_space_char (*base_string))
5278 ++base_string;
5279 if (*base_string != ')')
5280 {
4eed87de
AM		 5281 as_bad (_("expecting `)' "
5282 "after scale factor in `%s'"),
af6bdddf
AM		 5283 operand_string);
5284 return 0;
5285 }
5286 }
5287 else if (!i.index_reg)
24eab124 5288 {
4eed87de
AM		 5289 as_bad (_("expecting index register or scale factor "
5290 "after `,'; got '%c'"),
af6bdddf 5291 *base_string);
24eab124
AM		 5292 return 0;
5293 }
5294 }
af6bdddf 5295 else if (*base_string != ')')
24eab124 5296 {
4eed87de
AM		 5297 as_bad (_("expecting `,' or `)' "
5298 "after base register in `%s'"),
af6bdddf 5299 operand_string);
24eab124
AM		 5300 return 0;
5301 }
c3332e24 5302 }
af6bdddf 5303 else if (*base_string == REGISTER_PREFIX)
c3332e24 5304 {
af6bdddf 5305 as_bad (_("bad register name `%s'"), base_string);
24eab124 5306 return 0;
c3332e24 5307 }
24eab124
AM		 5308 }
5309
5310 /* If there's an expression beginning the operand, parse it,
5311 assuming displacement_string_start and
5312 displacement_string_end are meaningful. */
5313 if (displacement_string_start != displacement_string_end)
5314 {
5315 if (!i386_displacement (displacement_string_start,
5316 displacement_string_end))
5317 return 0;
5318 }
5319
5320 /* Special case for (%dx) while doing input/output op. */
5321 if (i.base_reg
5322 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5323 && i.index_reg == 0
5324 && i.log2_scale_factor == 0
5325 && i.seg[i.mem_operands] == 0
5326 && (i.types[this_operand] & Disp) == 0)
5327 {
5328 i.types[this_operand] = InOutPortReg;
5329 return 1;
5330 }
5331
eecb386c
AM		 5332 if (i386_index_check (operand_string) == 0)
5333 return 0;
24eab124
AM		 5334 i.mem_operands++;
5335 }
5336 else
ce8a8b2f
AM		 5337 {
5338 /* It's not a memory operand; argh! */
24eab124
AM		 5339 as_bad (_("invalid char %s beginning operand %d `%s'"),
5340 output_invalid (*op_string),
5341 this_operand + 1,
5342 op_string);
5343 return 0;
5344 }
47926f60 5345 return 1; /* Normal return. */
252b5132
RH		 5346}
5347\f
ee7fcc42
AM		 5348/* md_estimate_size_before_relax()
5349
5350 Called just before relax() for rs_machine_dependent frags. The x86
5351 assembler uses these frags to handle variable size jump
5352 instructions.
5353
5354 Any symbol that is now undefined will not become defined.
5355 Return the correct fr_subtype in the frag.
5356 Return the initial "guess for variable size of frag" to caller.
5357 The guess is actually the growth beyond the fixed part. Whatever
5358 we do to grow the fixed or variable part contributes to our
5359 returned value. */
5360
252b5132
RH		 5361int
5362md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5363 fragS *fragP;
5364 segT segment;
252b5132 5365{
252b5132 5366 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5367 check for un-relaxable symbols. On an ELF system, we can't relax
5368 an externally visible symbol, because it may be overridden by a
5369 shared library. */
5370 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5371#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5372 || (IS_ELF
31312f95
AM		 5373 && (S_IS_EXTERNAL (fragP->fr_symbol)
5374 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5375#endif
5376 )
252b5132 5377 {
b98ef147
AM		 5378 /* Symbol is undefined in this segment, or we need to keep a
5379 reloc so that weak symbols can be overridden. */
5380 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5381 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5382 unsigned char *opcode;
5383 int old_fr_fix;
f6af82bd 5384
ee7fcc42
AM		 5385 if (fragP->fr_var != NO_RELOC)
5386 reloc_type = fragP->fr_var;
b98ef147 5387 else if (size == 2)
f6af82bd
AM		 5388 reloc_type = BFD_RELOC_16_PCREL;
5389 else
5390 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5391
ee7fcc42
AM		 5392 old_fr_fix = fragP->fr_fix;
5393 opcode = (unsigned char *) fragP->fr_opcode;
5394
fddf5b5b 5395 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5396 {
fddf5b5b
AM		 5397 case UNCOND_JUMP:
5398 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5399 opcode[0] = 0xe9;
252b5132 5400 fragP->fr_fix += size;
062cd5e7
AS		 5401 fix_new (fragP, old_fr_fix, size,
5402 fragP->fr_symbol,
5403 fragP->fr_offset, 1,
5404 reloc_type);
252b5132
RH		 5405 break;
5406
fddf5b5b 5407 case COND_JUMP86:
412167cb
AM		 5408 if (size == 2
5409 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5410 {
5411 /* Negate the condition, and branch past an
5412 unconditional jump. */
5413 opcode[0] ^= 1;
5414 opcode[1] = 3;
5415 /* Insert an unconditional jump. */
5416 opcode[2] = 0xe9;
5417 /* We added two extra opcode bytes, and have a two byte
5418 offset. */
5419 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5420 fix_new (fragP, old_fr_fix + 2, 2,
5421 fragP->fr_symbol,
5422 fragP->fr_offset, 1,
5423 reloc_type);
fddf5b5b
AM		 5424 break;
5425 }
5426 /* Fall through. */
5427
5428 case COND_JUMP:
412167cb
AM		 5429 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5430 {
3e02c1cc
AM		 5431 fixS *fixP;
5432
412167cb 5433 fragP->fr_fix += 1;
3e02c1cc
AM		 5434 fixP = fix_new (fragP, old_fr_fix, 1,
5435 fragP->fr_symbol,
5436 fragP->fr_offset, 1,
5437 BFD_RELOC_8_PCREL);
5438 fixP->fx_signed = 1;
412167cb
AM		 5439 break;
5440 }
93c2a809 5441
24eab124 5442 /* This changes the byte-displacement jump 0x7N
fddf5b5b 5443 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 5444 opcode[1] = opcode[0] + 0x10;
f6af82bd 5445 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 5446 /* We've added an opcode byte. */
5447 fragP->fr_fix += 1 + size;
062cd5e7
AS		 5448 fix_new (fragP, old_fr_fix + 1, size,
5449 fragP->fr_symbol,
5450 fragP->fr_offset, 1,
5451 reloc_type);
252b5132 5452 break;
fddf5b5b
AM		 5453
5454 default:
5455 BAD_CASE (fragP->fr_subtype);
5456 break;
252b5132
RH		 5457 }
5458 frag_wane (fragP);
ee7fcc42 5459 return fragP->fr_fix - old_fr_fix;
252b5132 5460 }
93c2a809 5461
93c2a809
AM		 5462 /* Guess size depending on current relax state. Initially the relax
5463 state will correspond to a short jump and we return 1, because
5464 the variable part of the frag (the branch offset) is one byte
5465 long. However, we can relax a section more than once and in that
5466 case we must either set fr_subtype back to the unrelaxed state,
5467 or return the value for the appropriate branch. */
5468 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 5469}
5470
47926f60
KH		 5471/* Called after relax() is finished.
5472
5473 In: Address of frag.
5474 fr_type == rs_machine_dependent.
5475 fr_subtype is what the address relaxed to.
5476
5477 Out: Any fixSs and constants are set up.
5478 Caller will turn frag into a ".space 0". */
5479
252b5132
RH		 5480void
5481md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 5482 bfd *abfd ATTRIBUTE_UNUSED;
5483 segT sec ATTRIBUTE_UNUSED;
29b0f896 5484 fragS *fragP;
252b5132 5485{
29b0f896 5486 unsigned char *opcode;
252b5132 5487 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 5488 offsetT target_address;
5489 offsetT opcode_address;
252b5132 5490 unsigned int extension = 0;
847f7ad4 5491 offsetT displacement_from_opcode_start;
252b5132
RH		 5492
5493 opcode = (unsigned char *) fragP->fr_opcode;
5494
47926f60 5495 /* Address we want to reach in file space. */
252b5132 5496 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 5497
47926f60 5498 /* Address opcode resides at in file space. */
252b5132
RH		 5499 opcode_address = fragP->fr_address + fragP->fr_fix;
5500
47926f60 5501 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 5502 displacement_from_opcode_start = target_address - opcode_address;
5503
fddf5b5b 5504 if ((fragP->fr_subtype & BIG) == 0)
252b5132 5505 {
47926f60
KH		 5506 /* Don't have to change opcode. */
5507 extension = 1; /* 1 opcode + 1 displacement */
252b5132 5508 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 5509 }
5510 else
5511 {
5512 if (no_cond_jump_promotion
5513 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 5514 as_warn_where (fragP->fr_file, fragP->fr_line,
5515 _("long jump required"));
252b5132 5516
fddf5b5b
AM		 5517 switch (fragP->fr_subtype)
5518 {
5519 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5520 extension = 4; /* 1 opcode + 4 displacement */
5521 opcode[0] = 0xe9;
5522 where_to_put_displacement = &opcode[1];
5523 break;
252b5132 5524
fddf5b5b
AM		 5525 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5526 extension = 2; /* 1 opcode + 2 displacement */
5527 opcode[0] = 0xe9;
5528 where_to_put_displacement = &opcode[1];
5529 break;
252b5132 5530
fddf5b5b
AM		 5531 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5532 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5533 extension = 5; /* 2 opcode + 4 displacement */
5534 opcode[1] = opcode[0] + 0x10;
5535 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5536 where_to_put_displacement = &opcode[2];
5537 break;
252b5132 5538
fddf5b5b
AM		 5539 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5540 extension = 3; /* 2 opcode + 2 displacement */
5541 opcode[1] = opcode[0] + 0x10;
5542 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5543 where_to_put_displacement = &opcode[2];
5544 break;
252b5132 5545
fddf5b5b
AM		 5546 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5547 extension = 4;
5548 opcode[0] ^= 1;
5549 opcode[1] = 3;
5550 opcode[2] = 0xe9;
5551 where_to_put_displacement = &opcode[3];
5552 break;
5553
5554 default:
5555 BAD_CASE (fragP->fr_subtype);
5556 break;
5557 }
252b5132 5558 }
fddf5b5b 5559
7b81dfbb
AJ		 5560 /* If size if less then four we are sure that the operand fits,
5561 but if it's 4, then it could be that the displacement is larger
5562 then -/+ 2GB. */
5563 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5564 && object_64bit
5565 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 5566 + ((addressT) 1 << 31))
5567 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 5568 {
5569 as_bad_where (fragP->fr_file, fragP->fr_line,
5570 _("jump target out of range"));
5571 /* Make us emit 0. */
5572 displacement_from_opcode_start = extension;
5573 }
47926f60 5574 /* Now put displacement after opcode. */
252b5132
RH		 5575 md_number_to_chars ((char *) where_to_put_displacement,
5576 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5577 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5578 fragP->fr_fix += extension;
5579}
5580\f
47926f60
KH		 5581/* Size of byte displacement jmp. */
5582int md_short_jump_size = 2;
5583
5584/* Size of dword displacement jmp. */
5585int md_long_jump_size = 5;
252b5132 5586
252b5132
RH		 5587void
5588md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5589 char *ptr;
5590 addressT from_addr, to_addr;
ab9da554
ILT		 5591 fragS *frag ATTRIBUTE_UNUSED;
5592 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5593{
847f7ad4 5594 offsetT offset;
252b5132
RH		 5595
5596 offset = to_addr - (from_addr + 2);
47926f60
KH		 5597 /* Opcode for byte-disp jump. */
5598 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5599 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5600}
5601
5602void
5603md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5604 char *ptr;
5605 addressT from_addr, to_addr;
a38cf1db
AM		 5606 fragS *frag ATTRIBUTE_UNUSED;
5607 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5608{
847f7ad4 5609 offsetT offset;
252b5132 5610
a38cf1db
AM		 5611 offset = to_addr - (from_addr + 5);
5612 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5613 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5614}
5615\f
5616/* Apply a fixup (fixS) to segment data, once it has been determined
5617 by our caller that we have all the info we need to fix it up.
5618
5619 On the 386, immediates, displacements, and data pointers are all in
5620 the same (little-endian) format, so we don't need to care about which
5621 we are handling. */
5622
94f592af 5623void
55cf6793 5624md_apply_fix (fixP, valP, seg)
47926f60
KH		 5625 /* The fix we're to put in. */
5626 fixS *fixP;
47926f60 5627 /* Pointer to the value of the bits. */
c6682705 5628 valueT *valP;
47926f60
KH		 5629 /* Segment fix is from. */
5630 segT seg ATTRIBUTE_UNUSED;
252b5132 5631{
94f592af 5632 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5633 valueT value = *valP;
252b5132 5634
f86103b7 5635#if !defined (TE_Mach)
93382f6d
AM		 5636 if (fixP->fx_pcrel)
5637 {
5638 switch (fixP->fx_r_type)
5639 {
5865bb77
ILT		 5640 default:
5641 break;
5642
d6ab8113
JB		 5643 case BFD_RELOC_64:
5644 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5645 break;
93382f6d 5646 case BFD_RELOC_32:
ae8887b5 5647 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5648 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5649 break;
5650 case BFD_RELOC_16:
5651 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5652 break;
5653 case BFD_RELOC_8:
5654 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5655 break;
5656 }
5657 }
252b5132 5658
a161fe53 5659 if (fixP->fx_addsy != NULL
31312f95 5660 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5661 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5662 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5663 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5664 && !use_rela_relocations)
252b5132 5665 {
31312f95
AM		 5666 /* This is a hack. There should be a better way to handle this.
5667 This covers for the fact that bfd_install_relocation will
5668 subtract the current location (for partial_inplace, PC relative
5669 relocations); see more below. */
252b5132 5670#ifndef OBJ_AOUT
718ddfc0 5671 if (IS_ELF
252b5132
RH		 5672#ifdef TE_PE
5673 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5674#endif
5675 )
5676 value += fixP->fx_where + fixP->fx_frag->fr_address;
5677#endif
5678#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5679 if (IS_ELF)
252b5132 5680 {
6539b54b 5681 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5682
6539b54b 5683 if ((sym_seg == seg
2f66722d 5684 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5685 && sym_seg != absolute_section))
ae6063d4 5686 && !generic_force_reloc (fixP))
2f66722d
AM		 5687 {
5688 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5689 bfd_install_relocation subtracts them out again. I think
5690 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5691 it. FIXME. */
5692 value += fixP->fx_where + fixP->fx_frag->fr_address;
5693 }
252b5132
RH		 5694 }
5695#endif
5696#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5697 /* For some reason, the PE format does not store a
5698 section address offset for a PC relative symbol. */
5699 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5700 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5701 value += md_pcrel_from (fixP);
5702#endif
5703 }
5704
5705 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5706 and we must not disappoint it. */
252b5132 5707#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5708 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5709 switch (fixP->fx_r_type)
5710 {
5711 case BFD_RELOC_386_PLT32:
3e73aa7c 5712 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5713 /* Make the jump instruction point to the address of the operand. At
5714 runtime we merely add the offset to the actual PLT entry. */
5715 value = -4;
5716 break;
31312f95 5717
13ae64f3
JJ		 5718 case BFD_RELOC_386_TLS_GD:
5719 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5720 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5721 case BFD_RELOC_386_TLS_IE:
5722 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5723 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5724 case BFD_RELOC_X86_64_TLSGD:
5725 case BFD_RELOC_X86_64_TLSLD:
5726 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5727 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5728 value = 0; /* Fully resolved at runtime. No addend. */
5729 /* Fallthrough */
5730 case BFD_RELOC_386_TLS_LE:
5731 case BFD_RELOC_386_TLS_LDO_32:
5732 case BFD_RELOC_386_TLS_LE_32:
5733 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5734 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5735 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5736 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5737 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5738 break;
5739
67a4f2b7
AO		 5740 case BFD_RELOC_386_TLS_DESC_CALL:
5741 case BFD_RELOC_X86_64_TLSDESC_CALL:
5742 value = 0; /* Fully resolved at runtime. No addend. */
5743 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5744 fixP->fx_done = 0;
5745 return;
5746
00f7efb6
JJ		 5747 case BFD_RELOC_386_GOT32:
5748 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5749 value = 0; /* Fully resolved at runtime. No addend. */
5750 break;
47926f60
KH		 5751
5752 case BFD_RELOC_VTABLE_INHERIT:
5753 case BFD_RELOC_VTABLE_ENTRY:
5754 fixP->fx_done = 0;
94f592af 5755 return;
47926f60
KH		 5756
5757 default:
5758 break;
5759 }
5760#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5761 *valP = value;
f86103b7 5762#endif /* !defined (TE_Mach) */
3e73aa7c 5763
3e73aa7c 5764 /* Are we finished with this relocation now? */
c6682705 5765 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5766 fixP->fx_done = 1;
5767 else if (use_rela_relocations)
5768 {
5769 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5770 /* Remember value for tc_gen_reloc. */
5771 fixP->fx_addnumber = value;
3e73aa7c
JH		 5772 value = 0;
5773 }
f86103b7 5774
94f592af 5775 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5776}
252b5132 5777\f
252b5132
RH		 5778#define MAX_LITTLENUMS 6
5779
47926f60
KH		 5780/* Turn the string pointed to by litP into a floating point constant
5781 of type TYPE, and emit the appropriate bytes. The number of
5782 LITTLENUMS emitted is stored in *SIZEP. An error message is
5783 returned, or NULL on OK. */
5784
252b5132
RH		 5785char *
5786md_atof (type, litP, sizeP)
2ab9b79e 5787 int type;
252b5132
RH		 5788 char *litP;
5789 int *sizeP;
5790{
5791 int prec;
5792 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5793 LITTLENUM_TYPE *wordP;
5794 char *t;
5795
5796 switch (type)
5797 {
5798 case 'f':
5799 case 'F':
5800 prec = 2;
5801 break;
5802
5803 case 'd':
5804 case 'D':
5805 prec = 4;
5806 break;
5807
5808 case 'x':
5809 case 'X':
5810 prec = 5;
5811 break;
5812
5813 default:
5814 *sizeP = 0;
5815 return _("Bad call to md_atof ()");
5816 }
5817 t = atof_ieee (input_line_pointer, type, words);
5818 if (t)
5819 input_line_pointer = t;
5820
5821 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5822 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5823 the bigendian 386. */
5824 for (wordP = words + prec - 1; prec--;)
5825 {
5826 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5827 litP += sizeof (LITTLENUM_TYPE);
5828 }
5829 return 0;
5830}
5831\f
2d545b82 5832static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5833
252b5132 5834static char *
e3bb37b5 5835output_invalid (int c)
252b5132 5836{
3882b010 5837 if (ISPRINT (c))
f9f21a03
L		 5838 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5839 "'%c'", c);
252b5132 5840 else
f9f21a03 5841 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5842 "(0x%x)", (unsigned char) c);
252b5132
RH		 5843 return output_invalid_buf;
5844}
5845
af6bdddf 5846/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5847
5848static const reg_entry *
4d1bb795 5849parse_real_register (char *reg_string, char **end_op)
252b5132 5850{
af6bdddf
AM		 5851 char *s = reg_string;
5852 char *p;
252b5132
RH		 5853 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5854 const reg_entry *r;
5855
5856 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5857 if (*s == REGISTER_PREFIX)
5858 ++s;
5859
5860 if (is_space_char (*s))
5861 ++s;
5862
5863 p = reg_name_given;
af6bdddf 5864 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5865 {
5866 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5867 return (const reg_entry *) NULL;
5868 s++;
252b5132
RH		 5869 }
5870
6588847e
DN		 5871 /* For naked regs, make sure that we are not dealing with an identifier.
5872 This prevents confusing an identifier like `eax_var' with register
5873 `eax'. */
5874 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5875 return (const reg_entry *) NULL;
5876
af6bdddf 5877 *end_op = s;
252b5132
RH		 5878
5879 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5880
5f47d35b 5881 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5882 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5883 {
5f47d35b
AM		 5884 if (is_space_char (*s))
5885 ++s;
5886 if (*s == '(')
5887 {
af6bdddf 5888 ++s;
5f47d35b
AM		 5889 if (is_space_char (*s))
5890 ++s;
5891 if (*s >= '0' && *s <= '7')
5892 {
db557034 5893 int fpr = *s - '0';
af6bdddf 5894 ++s;
5f47d35b
AM		 5895 if (is_space_char (*s))
5896 ++s;
5897 if (*s == ')')
5898 {
5899 *end_op = s + 1;
db557034
AM		 5900 r = hash_find (reg_hash, "st(0)");
5901 know (r);
5902 return r + fpr;
5f47d35b 5903 }
5f47d35b 5904 }
47926f60 5905 /* We have "%st(" then garbage. */
5f47d35b
AM		 5906 return (const reg_entry *) NULL;
5907 }
5908 }
5909
1ae00879 5910 if (r != NULL
20f0a1fc 5911 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5912 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5913 && flag_code != CODE_64BIT)
20f0a1fc 5914 return (const reg_entry *) NULL;
1ae00879 5915
252b5132
RH		 5916 return r;
5917}
4d1bb795
JB		 5918
5919/* REG_STRING starts *before* REGISTER_PREFIX. */
5920
5921static const reg_entry *
5922parse_register (char *reg_string, char **end_op)
5923{
5924 const reg_entry *r;
5925
5926 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5927 r = parse_real_register (reg_string, end_op);
5928 else
5929 r = NULL;
5930 if (!r)
5931 {
5932 char *save = input_line_pointer;
5933 char c;
5934 symbolS *symbolP;
5935
5936 input_line_pointer = reg_string;
5937 c = get_symbol_end ();
5938 symbolP = symbol_find (reg_string);
5939 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5940 {
5941 const expressionS *e = symbol_get_value_expression (symbolP);
5942
5943 know (e->X_op == O_register);
4eed87de 5944 know (e->X_add_number >= 0
c3fe08fa 5945 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 5946 r = i386_regtab + e->X_add_number;
5947 *end_op = input_line_pointer;
5948 }
5949 *input_line_pointer = c;
5950 input_line_pointer = save;
5951 }
5952 return r;
5953}
5954
5955int
5956i386_parse_name (char *name, expressionS *e, char *nextcharP)
5957{
5958 const reg_entry *r;
5959 char *end = input_line_pointer;
5960
5961 *end = *nextcharP;
5962 r = parse_register (name, &input_line_pointer);
5963 if (r && end <= input_line_pointer)
5964 {
5965 *nextcharP = *input_line_pointer;
5966 *input_line_pointer = 0;
5967 e->X_op = O_register;
5968 e->X_add_number = r - i386_regtab;
5969 return 1;
5970 }
5971 input_line_pointer = end;
5972 *end = 0;
5973 return 0;
5974}
5975
5976void
5977md_operand (expressionS *e)
5978{
5979 if (*input_line_pointer == REGISTER_PREFIX)
5980 {
5981 char *end;
5982 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5983
5984 if (r)
5985 {
5986 e->X_op = O_register;
5987 e->X_add_number = r - i386_regtab;
5988 input_line_pointer = end;
5989 }
5990 }
5991}
5992
252b5132 5993\f
4cc782b5 5994#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5995const char *md_shortopts = "kVQ:sqn";
252b5132 5996#else
12b55ccc 5997const char *md_shortopts = "qn";
252b5132 5998#endif
6e0b89ee 5999
3e73aa7c 6000#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 6001#define OPTION_64 (OPTION_MD_BASE + 1)
6002#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 6003#define OPTION_MARCH (OPTION_MD_BASE + 3)
6004#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 6005
99ad8390
NC		 6006struct option md_longopts[] =
6007{
3e73aa7c 6008 {"32", no_argument, NULL, OPTION_32},
99ad8390 6009#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 6010 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 6011#endif
b3b91714 6012 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 6013 {"march", required_argument, NULL, OPTION_MARCH},
6014 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 6015 {NULL, no_argument, NULL, 0}
6016};
6017size_t md_longopts_size = sizeof (md_longopts);
6018
6019int
9103f4f4 6020md_parse_option (int c, char *arg)
252b5132 6021{
9103f4f4
L		 6022 unsigned int i;
6023
252b5132
RH		 6024 switch (c)
6025 {
12b55ccc
L		 6026 case 'n':
6027 optimize_align_code = 0;
6028 break;
6029
a38cf1db
AM		 6030 case 'q':
6031 quiet_warnings = 1;
252b5132
RH		 6032 break;
6033
6034#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 6035 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6036 should be emitted or not. FIXME: Not implemented. */
6037 case 'Q':
252b5132
RH		 6038 break;
6039
6040 /* -V: SVR4 argument to print version ID. */
6041 case 'V':
6042 print_version_id ();
6043 break;
6044
a38cf1db
AM		 6045 /* -k: Ignore for FreeBSD compatibility. */
6046 case 'k':
252b5132 6047 break;
4cc782b5
ILT		 6048
6049 case 's':
6050 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 6051 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 6052 break;
99ad8390
NC		 6053#endif
6054#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 6055 case OPTION_64:
6056 {
6057 const char **list, **l;
6058
3e73aa7c
JH		 6059 list = bfd_target_list ();
6060 for (l = list; *l != NULL; l++)
8620418b 6061 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 6062 || strcmp (*l, "coff-x86-64") == 0
6063 || strcmp (*l, "pe-x86-64") == 0
6064 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 6065 {
6066 default_arch = "x86_64";
6067 break;
6068 }
3e73aa7c 6069 if (*l == NULL)
6e0b89ee 6070 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 6071 free (list);
6072 }
6073 break;
6074#endif
252b5132 6075
6e0b89ee
AM		 6076 case OPTION_32:
6077 default_arch = "i386";
6078 break;
6079
b3b91714
AM		 6080 case OPTION_DIVIDE:
6081#ifdef SVR4_COMMENT_CHARS
6082 {
6083 char *n, *t;
6084 const char *s;
6085
6086 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
6087 t = n;
6088 for (s = i386_comment_chars; *s != '\0'; s++)
6089 if (*s != '/')
6090 *t++ = *s;
6091 *t = '\0';
6092 i386_comment_chars = n;
6093 }
6094#endif
6095 break;
6096
9103f4f4
L		 6097 case OPTION_MARCH:
6098 if (*arg == '.')
6099 as_fatal (_("Invalid -march= option: `%s'"), arg);
6100 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
6101 {
6102 if (strcmp (arg, cpu_arch [i].name) == 0)
6103 {
ccc9c027 6104 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 6105 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 6106 if (!cpu_arch_tune_set)
6107 {
6108 cpu_arch_tune = cpu_arch_isa;
6109 cpu_arch_tune_flags = cpu_arch_isa_flags;
6110 }
9103f4f4
L		 6111 break;
6112 }
6113 }
6114 if (i >= ARRAY_SIZE (cpu_arch))
6115 as_fatal (_("Invalid -march= option: `%s'"), arg);
6116 break;
6117
6118 case OPTION_MTUNE:
6119 if (*arg == '.')
6120 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6121 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
6122 {
6123 if (strcmp (arg, cpu_arch [i].name) == 0)
6124 {
ccc9c027 6125 cpu_arch_tune_set = 1;
9103f4f4
L		 6126 cpu_arch_tune = cpu_arch [i].type;
6127 cpu_arch_tune_flags = cpu_arch[i].flags;
6128 break;
6129 }
6130 }
6131 if (i >= ARRAY_SIZE (cpu_arch))
6132 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6133 break;
6134
252b5132
RH		 6135 default:
6136 return 0;
6137 }
6138 return 1;
6139}
6140
6141void
6142md_show_usage (stream)
6143 FILE *stream;
6144{
4cc782b5
ILT		 6145#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6146 fprintf (stream, _("\
a38cf1db
AM		 6147 -Q ignored\n\
6148 -V print assembler version number\n\
b3b91714
AM		 6149 -k ignored\n"));
6150#endif
6151 fprintf (stream, _("\
12b55ccc 6152 -n Do not optimize code alignment\n\
b3b91714
AM		 6153 -q quieten some warnings\n"));
6154#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6155 fprintf (stream, _("\
a38cf1db 6156 -s ignored\n"));
b3b91714 6157#endif
751d281c
L		 6158#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6159 fprintf (stream, _("\
6160 --32/--64 generate 32bit/64bit code\n"));
6161#endif
b3b91714
AM		 6162#ifdef SVR4_COMMENT_CHARS
6163 fprintf (stream, _("\
6164 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 6165#else
6166 fprintf (stream, _("\
b3b91714 6167 --divide ignored\n"));
4cc782b5 6168#endif
9103f4f4
L		 6169 fprintf (stream, _("\
6170 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6171 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 6172 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 6173
252b5132
RH		 6174}
6175
3e73aa7c 6176#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 6177 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 6178
6179/* Pick the target format to use. */
6180
47926f60 6181const char *
e3bb37b5 6182i386_target_format (void)
252b5132 6183{
3e73aa7c 6184 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 6185 {
6186 set_code_flag (CODE_64BIT);
6187 if (cpu_arch_isa_flags == 0)
d32cad65 6188 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
9103f4f4
L		 6189 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6190 |CpuSSE|CpuSSE2;
ccc9c027 6191 if (cpu_arch_tune_flags == 0)
d32cad65 6192 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
ccc9c027
L		 6193 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6194 |CpuSSE|CpuSSE2;
9103f4f4 6195 }
3e73aa7c 6196 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 6197 {
6198 set_code_flag (CODE_32BIT);
6199 if (cpu_arch_isa_flags == 0)
d32cad65 6200 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
ccc9c027 6201 if (cpu_arch_tune_flags == 0)
d32cad65 6202 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
9103f4f4 6203 }
3e73aa7c
JH		 6204 else
6205 as_fatal (_("Unknown architecture"));
252b5132
RH		 6206 switch (OUTPUT_FLAVOR)
6207 {
872ce6ff
L		 6208#ifdef TE_PEP
6209 case bfd_target_coff_flavour:
6210 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
6211 break;
6212#endif
4c63da97
AM		 6213#ifdef OBJ_MAYBE_AOUT
6214 case bfd_target_aout_flavour:
47926f60 6215 return AOUT_TARGET_FORMAT;
4c63da97
AM		 6216#endif
6217#ifdef OBJ_MAYBE_COFF
252b5132
RH		 6218 case bfd_target_coff_flavour:
6219 return "coff-i386";
4c63da97 6220#endif
3e73aa7c 6221#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 6222 case bfd_target_elf_flavour:
3e73aa7c 6223 {
e5cb08ac 6224 if (flag_code == CODE_64BIT)
4fa24527
JB		 6225 {
6226 object_64bit = 1;
6227 use_rela_relocations = 1;
6228 }
9d7cbccd 6229 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6230 }
4c63da97 6231#endif
252b5132
RH		 6232 default:
6233 abort ();
6234 return NULL;
6235 }
6236}
6237
47926f60 6238#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 6239
6240#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 6241void
6242i386_elf_emit_arch_note (void)
a847613f 6243{
718ddfc0 6244 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 6245 {
6246 char *p;
6247 asection *seg = now_seg;
6248 subsegT subseg = now_subseg;
6249 Elf_Internal_Note i_note;
6250 Elf_External_Note e_note;
6251 asection *note_secp;
6252 int len;
6253
6254 /* Create the .note section. */
6255 note_secp = subseg_new (".note", 0);
6256 bfd_set_section_flags (stdoutput,
6257 note_secp,
6258 SEC_HAS_CONTENTS | SEC_READONLY);
6259
6260 /* Process the arch string. */
6261 len = strlen (cpu_arch_name);
6262
6263 i_note.namesz = len + 1;
6264 i_note.descsz = 0;
6265 i_note.type = NT_ARCH;
6266 p = frag_more (sizeof (e_note.namesz));
6267 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6268 p = frag_more (sizeof (e_note.descsz));
6269 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6270 p = frag_more (sizeof (e_note.type));
6271 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6272 p = frag_more (len + 1);
6273 strcpy (p, cpu_arch_name);
6274
6275 frag_align (2, 0, 0);
6276
6277 subseg_set (seg, subseg);
6278 }
6279}
6280#endif
252b5132 6281\f
252b5132
RH		 6282symbolS *
6283md_undefined_symbol (name)
6284 char *name;
6285{
18dc2407
ILT		 6286 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6287 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6288 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6289 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6290 {
6291 if (!GOT_symbol)
6292 {
6293 if (symbol_find (name))
6294 as_bad (_("GOT already in symbol table"));
6295 GOT_symbol = symbol_new (name, undefined_section,
6296 (valueT) 0, &zero_address_frag);
6297 };
6298 return GOT_symbol;
6299 }
252b5132
RH		 6300 return 0;
6301}
6302
6303/* Round up a section size to the appropriate boundary. */
47926f60 6304
252b5132
RH		 6305valueT
6306md_section_align (segment, size)
ab9da554 6307 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6308 valueT size;
6309{
4c63da97
AM		 6310#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6311 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6312 {
6313 /* For a.out, force the section size to be aligned. If we don't do
6314 this, BFD will align it for us, but it will not write out the
6315 final bytes of the section. This may be a bug in BFD, but it is
6316 easier to fix it here since that is how the other a.out targets
6317 work. */
6318 int align;
6319
6320 align = bfd_get_section_alignment (stdoutput, segment);
6321 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6322 }
252b5132
RH		 6323#endif
6324
6325 return size;
6326}
6327
6328/* On the i386, PC-relative offsets are relative to the start of the
6329 next instruction. That is, the address of the offset, plus its
6330 size, since the offset is always the last part of the insn. */
6331
6332long
e3bb37b5 6333md_pcrel_from (fixS *fixP)
252b5132
RH		 6334{
6335 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6336}
6337
6338#ifndef I386COFF
6339
6340static void
e3bb37b5 6341s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 6342{
29b0f896 6343 int temp;
252b5132 6344
8a75718c
JB		 6345#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6346 if (IS_ELF)
6347 obj_elf_section_change_hook ();
6348#endif
252b5132
RH		 6349 temp = get_absolute_expression ();
6350 subseg_set (bss_section, (subsegT) temp);
6351 demand_empty_rest_of_line ();
6352}
6353
6354#endif
6355
252b5132 6356void
e3bb37b5 6357i386_validate_fix (fixS *fixp)
252b5132
RH		 6358{
6359 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6360 {
23df1078
JH		 6361 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6362 {
4fa24527 6363 if (!object_64bit)
23df1078
JH		 6364 abort ();
6365 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6366 }
6367 else
6368 {
4fa24527 6369 if (!object_64bit)
d6ab8113
JB		 6370 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6371 else
6372 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6373 }
252b5132
RH		 6374 fixp->fx_subsy = 0;
6375 }
6376}
6377
252b5132
RH		 6378arelent *
6379tc_gen_reloc (section, fixp)
ab9da554 6380 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6381 fixS *fixp;
6382{
6383 arelent *rel;
6384 bfd_reloc_code_real_type code;
6385
6386 switch (fixp->fx_r_type)
6387 {
3e73aa7c
JH		 6388 case BFD_RELOC_X86_64_PLT32:
6389 case BFD_RELOC_X86_64_GOT32:
6390 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6391 case BFD_RELOC_386_PLT32:
6392 case BFD_RELOC_386_GOT32:
6393 case BFD_RELOC_386_GOTOFF:
6394 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 6395 case BFD_RELOC_386_TLS_GD:
6396 case BFD_RELOC_386_TLS_LDM:
6397 case BFD_RELOC_386_TLS_LDO_32:
6398 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6399 case BFD_RELOC_386_TLS_IE:
6400 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 6401 case BFD_RELOC_386_TLS_LE_32:
6402 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 6403 case BFD_RELOC_386_TLS_GOTDESC:
6404 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 6405 case BFD_RELOC_X86_64_TLSGD:
6406 case BFD_RELOC_X86_64_TLSLD:
6407 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6408 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 6409 case BFD_RELOC_X86_64_GOTTPOFF:
6410 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 6411 case BFD_RELOC_X86_64_TPOFF64:
6412 case BFD_RELOC_X86_64_GOTOFF64:
6413 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 6414 case BFD_RELOC_X86_64_GOT64:
6415 case BFD_RELOC_X86_64_GOTPCREL64:
6416 case BFD_RELOC_X86_64_GOTPC64:
6417 case BFD_RELOC_X86_64_GOTPLT64:
6418 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 6419 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6420 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 6421 case BFD_RELOC_RVA:
6422 case BFD_RELOC_VTABLE_ENTRY:
6423 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 6424#ifdef TE_PE
6425 case BFD_RELOC_32_SECREL:
6426#endif
252b5132
RH		 6427 code = fixp->fx_r_type;
6428 break;
dbbaec26
L		 6429 case BFD_RELOC_X86_64_32S:
6430 if (!fixp->fx_pcrel)
6431 {
6432 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6433 code = fixp->fx_r_type;
6434 break;
6435 }
252b5132 6436 default:
93382f6d 6437 if (fixp->fx_pcrel)
252b5132 6438 {
93382f6d
AM		 6439 switch (fixp->fx_size)
6440 {
6441 default:
b091f402
AM		 6442 as_bad_where (fixp->fx_file, fixp->fx_line,
6443 _("can not do %d byte pc-relative relocation"),
6444 fixp->fx_size);
93382f6d
AM		 6445 code = BFD_RELOC_32_PCREL;
6446 break;
6447 case 1: code = BFD_RELOC_8_PCREL; break;
6448 case 2: code = BFD_RELOC_16_PCREL; break;
6449 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 6450#ifdef BFD64
6451 case 8: code = BFD_RELOC_64_PCREL; break;
6452#endif
93382f6d
AM		 6453 }
6454 }
6455 else
6456 {
6457 switch (fixp->fx_size)
6458 {
6459 default:
b091f402
AM		 6460 as_bad_where (fixp->fx_file, fixp->fx_line,
6461 _("can not do %d byte relocation"),
6462 fixp->fx_size);
93382f6d
AM		 6463 code = BFD_RELOC_32;
6464 break;
6465 case 1: code = BFD_RELOC_8; break;
6466 case 2: code = BFD_RELOC_16; break;
6467 case 4: code = BFD_RELOC_32; break;
937149dd 6468#ifdef BFD64
3e73aa7c 6469 case 8: code = BFD_RELOC_64; break;
937149dd 6470#endif
93382f6d 6471 }
252b5132
RH		 6472 }
6473 break;
6474 }
252b5132 6475
d182319b
JB		 6476 if ((code == BFD_RELOC_32
6477 || code == BFD_RELOC_32_PCREL
6478 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 6479 && GOT_symbol
6480 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 6481 {
4fa24527 6482 if (!object_64bit)
d6ab8113
JB		 6483 code = BFD_RELOC_386_GOTPC;
6484 else
6485 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 6486 }
7b81dfbb
AJ		 6487 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6488 && GOT_symbol
6489 && fixp->fx_addsy == GOT_symbol)
6490 {
6491 code = BFD_RELOC_X86_64_GOTPC64;
6492 }
252b5132
RH		 6493
6494 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 6495 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6496 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 6497
6498 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 6499
3e73aa7c
JH		 6500 if (!use_rela_relocations)
6501 {
6502 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6503 vtable entry to be used in the relocation's section offset. */
6504 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6505 rel->address = fixp->fx_offset;
252b5132 6506
c6682705 6507 rel->addend = 0;
3e73aa7c
JH		 6508 }
6509 /* Use the rela in 64bit mode. */
252b5132 6510 else
3e73aa7c 6511 {
062cd5e7
AS		 6512 if (!fixp->fx_pcrel)
6513 rel->addend = fixp->fx_offset;
6514 else
6515 switch (code)
6516 {
6517 case BFD_RELOC_X86_64_PLT32:
6518 case BFD_RELOC_X86_64_GOT32:
6519 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 6520 case BFD_RELOC_X86_64_TLSGD:
6521 case BFD_RELOC_X86_64_TLSLD:
6522 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 6523 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6524 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 6525 rel->addend = fixp->fx_offset - fixp->fx_size;
6526 break;
6527 default:
6528 rel->addend = (section->vma
6529 - fixp->fx_size
6530 + fixp->fx_addnumber
6531 + md_pcrel_from (fixp));
6532 break;
6533 }
3e73aa7c
JH		 6534 }
6535
252b5132
RH		 6536 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6537 if (rel->howto == NULL)
6538 {
6539 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 6540 _("cannot represent relocation type %s"),
252b5132
RH		 6541 bfd_get_reloc_code_name (code));
6542 /* Set howto to a garbage value so that we can keep going. */
6543 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6544 assert (rel->howto != NULL);
6545 }
6546
6547 return rel;
6548}
6549
64a0c779
DN		 6550\f
6551/* Parse operands using Intel syntax. This implements a recursive descent
6552 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6553 Programmer's Guide.
6554
6555 FIXME: We do not recognize the full operand grammar defined in the MASM
6556 documentation. In particular, all the structure/union and
6557 high-level macro operands are missing.
6558
6559 Uppercase words are terminals, lower case words are non-terminals.
6560 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6561 bars '|' denote choices. Most grammar productions are implemented in
6562 functions called 'intel_<production>'.
6563
6564 Initial production is 'expr'.
6565
9306ca4a 6566 addOp + | -
64a0c779
DN		 6567
6568 alpha [a-zA-Z]
6569
9306ca4a
JB		 6570 binOp & | AND | \| | OR | ^ | XOR
6571
64a0c779
DN		 6572 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6573
6574 constant digits [[ radixOverride ]]
6575
9306ca4a 6576 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 6577
6578 digits decdigit
b77a7acd
AJ		 6579 | digits decdigit
6580 | digits hexdigit
64a0c779
DN		 6581
6582 decdigit [0-9]
6583
9306ca4a
JB		 6584 e04 e04 addOp e05
6585 | e05
6586
6587 e05 e05 binOp e06
b77a7acd 6588 | e06
64a0c779
DN		 6589
6590 e06 e06 mulOp e09
b77a7acd 6591 | e09
64a0c779
DN		 6592
6593 e09 OFFSET e10
a724f0f4
JB		 6594 | SHORT e10
6595 | + e10
6596 | - e10
9306ca4a
JB		 6597 | ~ e10
6598 | NOT e10
64a0c779
DN		 6599 | e09 PTR e10
6600 | e09 : e10
6601 | e10
6602
6603 e10 e10 [ expr ]
b77a7acd 6604 | e11
64a0c779
DN		 6605
6606 e11 ( expr )
b77a7acd 6607 | [ expr ]
64a0c779
DN		 6608 | constant
6609 | dataType
6610 | id
6611 | $
6612 | register
6613
a724f0f4 6614 => expr expr cmpOp e04
9306ca4a 6615 | e04
64a0c779
DN		 6616
6617 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 6618 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 6619
6620 hexdigit a | b | c | d | e | f
b77a7acd 6621 | A | B | C | D | E | F
64a0c779
DN		 6622
6623 id alpha
b77a7acd 6624 | id alpha
64a0c779
DN		 6625 | id decdigit
6626
9306ca4a 6627 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 6628
6629 quote " | '
6630
6631 register specialRegister
b77a7acd 6632 | gpRegister
64a0c779
DN		 6633 | byteRegister
6634
6635 segmentRegister CS | DS | ES | FS | GS | SS
6636
9306ca4a 6637 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 6638 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 6639 | TR3 | TR4 | TR5 | TR6 | TR7
6640
64a0c779
DN		 6641 We simplify the grammar in obvious places (e.g., register parsing is
6642 done by calling parse_register) and eliminate immediate left recursion
6643 to implement a recursive-descent parser.
6644
a724f0f4
JB		 6645 expr e04 expr'
6646
6647 expr' cmpOp e04 expr'
6648 | Empty
9306ca4a
JB		 6649
6650 e04 e05 e04'
6651
6652 e04' addOp e05 e04'
6653 | Empty
64a0c779
DN		 6654
6655 e05 e06 e05'
6656
9306ca4a 6657 e05' binOp e06 e05'
b77a7acd 6658 | Empty
64a0c779
DN		 6659
6660 e06 e09 e06'
6661
6662 e06' mulOp e09 e06'
b77a7acd 6663 | Empty
64a0c779
DN		 6664
6665 e09 OFFSET e10 e09'
a724f0f4
JB		 6666 | SHORT e10'
6667 | + e10'
6668 | - e10'
6669 | ~ e10'
6670 | NOT e10'
b77a7acd 6671 | e10 e09'
64a0c779
DN		 6672
6673 e09' PTR e10 e09'
b77a7acd 6674 | : e10 e09'
64a0c779
DN		 6675 | Empty
6676
6677 e10 e11 e10'
6678
6679 e10' [ expr ] e10'
b77a7acd 6680 | Empty
64a0c779
DN		 6681
6682 e11 ( expr )
b77a7acd 6683 | [ expr ]
64a0c779
DN		 6684 | BYTE
6685 | WORD
6686 | DWORD
9306ca4a 6687 | FWORD
64a0c779 6688 | QWORD
9306ca4a
JB		 6689 | TBYTE
6690 | OWORD
6691 | XMMWORD
64a0c779
DN		 6692 | .
6693 | $
6694 | register
6695 | id
6696 | constant */
6697
6698/* Parsing structure for the intel syntax parser. Used to implement the
6699 semantic actions for the operand grammar. */
6700struct intel_parser_s
6701 {
6702 char *op_string; /* The string being parsed. */
6703 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6704 int op_modifier; /* Operand modifier. */
64a0c779 6705 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 6706 int in_offset; /* >=1 if parsing operand of offset. */
6707 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6708 const reg_entry *reg; /* Last register reference found. */
6709 char *disp; /* Displacement string being built. */
a724f0f4 6710 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6711 };
6712
6713static struct intel_parser_s intel_parser;
6714
6715/* Token structure for parsing intel syntax. */
6716struct intel_token
6717 {
6718 int code; /* Token code. */
6719 const reg_entry *reg; /* Register entry for register tokens. */
6720 char *str; /* String representation. */
6721 };
6722
6723static struct intel_token cur_token, prev_token;
6724
50705ef4
AM		 6725/* Token codes for the intel parser. Since T_SHORT is already used
6726 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6727#define T_NIL -1
6728#define T_CONST 1
6729#define T_REG 2
6730#define T_BYTE 3
6731#define T_WORD 4
9306ca4a
JB		 6732#define T_DWORD 5
6733#define T_FWORD 6
6734#define T_QWORD 7
6735#define T_TBYTE 8
6736#define T_XMMWORD 9
50705ef4 6737#undef T_SHORT
9306ca4a
JB		 6738#define T_SHORT 10
6739#define T_OFFSET 11
6740#define T_PTR 12
6741#define T_ID 13
6742#define T_SHL 14
6743#define T_SHR 15
64a0c779
DN		 6744
6745/* Prototypes for intel parser functions. */
e3bb37b5
L		 6746static int intel_match_token (int);
6747static void intel_putback_token (void);
6748static void intel_get_token (void);
6749static int intel_expr (void);
6750static int intel_e04 (void);
6751static int intel_e05 (void);
6752static int intel_e06 (void);
6753static int intel_e09 (void);
6754static int intel_e10 (void);
6755static int intel_e11 (void);
64a0c779 6756
64a0c779 6757static int
e3bb37b5 6758i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 6759{
6760 int ret;
6761 char *p;
6762
a724f0f4
JB		 6763 p = intel_parser.op_string = xstrdup (operand_string);
6764 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6765
6766 for (;;)
64a0c779 6767 {
a724f0f4
JB		 6768 /* Initialize token holders. */
6769 cur_token.code = prev_token.code = T_NIL;
6770 cur_token.reg = prev_token.reg = NULL;
6771 cur_token.str = prev_token.str = NULL;
6772
6773 /* Initialize parser structure. */
6774 intel_parser.got_a_float = got_a_float;
6775 intel_parser.op_modifier = 0;
6776 intel_parser.is_mem = 0;
6777 intel_parser.in_offset = 0;
6778 intel_parser.in_bracket = 0;
6779 intel_parser.reg = NULL;
6780 intel_parser.disp[0] = '\0';
6781 intel_parser.next_operand = NULL;
6782
6783 /* Read the first token and start the parser. */
6784 intel_get_token ();
6785 ret = intel_expr ();
6786
6787 if (!ret)
6788 break;
6789
9306ca4a
JB		 6790 if (cur_token.code != T_NIL)
6791 {
6792 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6793 current_templates->start->name, cur_token.str);
6794 ret = 0;
6795 }
64a0c779
DN		 6796 /* If we found a memory reference, hand it over to i386_displacement
6797 to fill in the rest of the operand fields. */
9306ca4a 6798 else if (intel_parser.is_mem)
64a0c779
DN		 6799 {
6800 if ((i.mem_operands == 1
6801 && (current_templates->start->opcode_modifier & IsString) == 0)
6802 || i.mem_operands == 2)
6803 {
6804 as_bad (_("too many memory references for '%s'"),
6805 current_templates->start->name);
6806 ret = 0;
6807 }
6808 else
6809 {
6810 char *s = intel_parser.disp;
6811 i.mem_operands++;
6812
a724f0f4
JB		 6813 if (!quiet_warnings && intel_parser.is_mem < 0)
6814 /* See the comments in intel_bracket_expr. */
6815 as_warn (_("Treating `%s' as memory reference"), operand_string);
6816
64a0c779
DN		 6817 /* Add the displacement expression. */
6818 if (*s != '\0')
a4622f40
AM		 6819 ret = i386_displacement (s, s + strlen (s));
6820 if (ret)
a724f0f4
JB		 6821 {
6822 /* Swap base and index in 16-bit memory operands like
6823 [si+bx]. Since i386_index_check is also used in AT&T
6824 mode we have to do that here. */
6825 if (i.base_reg
6826 && i.index_reg
6827 && (i.base_reg->reg_type & Reg16)
6828 && (i.index_reg->reg_type & Reg16)
6829 && i.base_reg->reg_num >= 6
6830 && i.index_reg->reg_num < 6)
6831 {
6832 const reg_entry *base = i.index_reg;
6833
6834 i.index_reg = i.base_reg;
6835 i.base_reg = base;
6836 }
6837 ret = i386_index_check (operand_string);
6838 }
64a0c779
DN		 6839 }
6840 }
6841
6842 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6843 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6844 || intel_parser.reg == NULL)
6845 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6846
6847 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 6848 ret = 0;
a724f0f4
JB		 6849 if (!ret || !intel_parser.next_operand)
6850 break;
6851 intel_parser.op_string = intel_parser.next_operand;
6852 this_operand = i.operands++;
64a0c779
DN		 6853 }
6854
6855 free (p);
6856 free (intel_parser.disp);
6857
6858 return ret;
6859}
6860
a724f0f4
JB		 6861#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6862
6863/* expr e04 expr'
6864
6865 expr' cmpOp e04 expr'
6866 | Empty */
64a0c779 6867static int
e3bb37b5 6868intel_expr (void)
64a0c779 6869{
a724f0f4
JB		 6870 /* XXX Implement the comparison operators. */
6871 return intel_e04 ();
9306ca4a
JB		 6872}
6873
a724f0f4 6874/* e04 e05 e04'
9306ca4a 6875
a724f0f4 6876 e04' addOp e05 e04'
9306ca4a
JB		 6877 | Empty */
6878static int
e3bb37b5 6879intel_e04 (void)
9306ca4a 6880{
a724f0f4 6881 int nregs = -1;
9306ca4a 6882
a724f0f4 6883 for (;;)
9306ca4a 6884 {
a724f0f4
JB		 6885 if (!intel_e05())
6886 return 0;
9306ca4a 6887
a724f0f4
JB		 6888 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6889 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6890
a724f0f4
JB		 6891 if (cur_token.code == '+')
6892 nregs = -1;
6893 else if (cur_token.code == '-')
6894 nregs = NUM_ADDRESS_REGS;
6895 else
6896 return 1;
64a0c779 6897
a724f0f4
JB		 6898 strcat (intel_parser.disp, cur_token.str);
6899 intel_match_token (cur_token.code);
6900 }
64a0c779
DN		 6901}
6902
64a0c779
DN		 6903/* e05 e06 e05'
6904
9306ca4a 6905 e05' binOp e06 e05'
64a0c779
DN		 6906 | Empty */
6907static int
e3bb37b5 6908intel_e05 (void)
64a0c779 6909{
a724f0f4 6910 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6911
a724f0f4 6912 for (;;)
64a0c779 6913 {
a724f0f4
JB		 6914 if (!intel_e06())
6915 return 0;
6916
4eed87de
AM		 6917 if (cur_token.code == '&'
6918 || cur_token.code == '|'
6919 || cur_token.code == '^')
a724f0f4
JB		 6920 {
6921 char str[2];
6922
6923 str[0] = cur_token.code;
6924 str[1] = 0;
6925 strcat (intel_parser.disp, str);
6926 }
6927 else
6928 break;
9306ca4a 6929
64a0c779
DN		 6930 intel_match_token (cur_token.code);
6931
a724f0f4
JB		 6932 if (nregs < 0)
6933 nregs = ~nregs;
64a0c779 6934 }
a724f0f4
JB		 6935 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6936 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6937 return 1;
4a1805b1 6938}
64a0c779
DN		 6939
6940/* e06 e09 e06'
6941
6942 e06' mulOp e09 e06'
b77a7acd 6943 | Empty */
64a0c779 6944static int
e3bb37b5 6945intel_e06 (void)
64a0c779 6946{
a724f0f4 6947 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6948
a724f0f4 6949 for (;;)
64a0c779 6950 {
a724f0f4
JB		 6951 if (!intel_e09())
6952 return 0;
9306ca4a 6953
4eed87de
AM		 6954 if (cur_token.code == '*'
6955 || cur_token.code == '/'
6956 || cur_token.code == '%')
a724f0f4
JB		 6957 {
6958 char str[2];
9306ca4a 6959
a724f0f4
JB		 6960 str[0] = cur_token.code;
6961 str[1] = 0;
6962 strcat (intel_parser.disp, str);
6963 }
6964 else if (cur_token.code == T_SHL)
6965 strcat (intel_parser.disp, "<<");
6966 else if (cur_token.code == T_SHR)
6967 strcat (intel_parser.disp, ">>");
6968 else
6969 break;
9306ca4a 6970
64e74474 6971 intel_match_token (cur_token.code);
64a0c779 6972
a724f0f4
JB		 6973 if (nregs < 0)
6974 nregs = ~nregs;
64a0c779 6975 }
a724f0f4
JB		 6976 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6977 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6978 return 1;
64a0c779
DN		 6979}
6980
a724f0f4
JB		 6981/* e09 OFFSET e09
6982 | SHORT e09
6983 | + e09
6984 | - e09
6985 | ~ e09
6986 | NOT e09
9306ca4a
JB		 6987 | e10 e09'
6988
64a0c779 6989 e09' PTR e10 e09'
b77a7acd 6990 | : e10 e09'
64a0c779
DN		 6991 | Empty */
6992static int
e3bb37b5 6993intel_e09 (void)
64a0c779 6994{
a724f0f4
JB		 6995 int nregs = ~NUM_ADDRESS_REGS;
6996 int in_offset = 0;
6997
6998 for (;;)
64a0c779 6999 {
a724f0f4
JB		 7000 /* Don't consume constants here. */
7001 if (cur_token.code == '+' || cur_token.code == '-')
7002 {
7003 /* Need to look one token ahead - if the next token
7004 is a constant, the current token is its sign. */
7005 int next_code;
7006
7007 intel_match_token (cur_token.code);
7008 next_code = cur_token.code;
7009 intel_putback_token ();
7010 if (next_code == T_CONST)
7011 break;
7012 }
7013
7014 /* e09 OFFSET e09 */
7015 if (cur_token.code == T_OFFSET)
7016 {
7017 if (!in_offset++)
7018 ++intel_parser.in_offset;
7019 }
7020
7021 /* e09 SHORT e09 */
7022 else if (cur_token.code == T_SHORT)
7023 intel_parser.op_modifier |= 1 << T_SHORT;
7024
7025 /* e09 + e09 */
7026 else if (cur_token.code == '+')
7027 strcat (intel_parser.disp, "+");
7028
7029 /* e09 - e09
7030 | ~ e09
7031 | NOT e09 */
7032 else if (cur_token.code == '-' || cur_token.code == '~')
7033 {
7034 char str[2];
64a0c779 7035
a724f0f4
JB		 7036 if (nregs < 0)
7037 nregs = ~nregs;
7038 str[0] = cur_token.code;
7039 str[1] = 0;
7040 strcat (intel_parser.disp, str);
7041 }
7042
7043 /* e09 e10 e09' */
7044 else
7045 break;
7046
7047 intel_match_token (cur_token.code);
64a0c779
DN		 7048 }
7049
a724f0f4 7050 for (;;)
9306ca4a 7051 {
a724f0f4
JB		 7052 if (!intel_e10 ())
7053 return 0;
9306ca4a 7054
a724f0f4
JB		 7055 /* e09' PTR e10 e09' */
7056 if (cur_token.code == T_PTR)
7057 {
7058 char suffix;
9306ca4a 7059
a724f0f4
JB		 7060 if (prev_token.code == T_BYTE)
7061 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 7062
a724f0f4
JB		 7063 else if (prev_token.code == T_WORD)
7064 {
7065 if (current_templates->start->name[0] == 'l'
7066 && current_templates->start->name[2] == 's'
7067 && current_templates->start->name[3] == 0)
7068 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7069 else if (intel_parser.got_a_float == 2) /* "fi..." */
7070 suffix = SHORT_MNEM_SUFFIX;
7071 else
7072 suffix = WORD_MNEM_SUFFIX;
7073 }
64a0c779 7074
a724f0f4
JB		 7075 else if (prev_token.code == T_DWORD)
7076 {
7077 if (current_templates->start->name[0] == 'l'
7078 && current_templates->start->name[2] == 's'
7079 && current_templates->start->name[3] == 0)
7080 suffix = WORD_MNEM_SUFFIX;
7081 else if (flag_code == CODE_16BIT
7082 && (current_templates->start->opcode_modifier
435acd52 7083 & (Jump | JumpDword)))
a724f0f4
JB		 7084 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7085 else if (intel_parser.got_a_float == 1) /* "f..." */
7086 suffix = SHORT_MNEM_SUFFIX;
7087 else
7088 suffix = LONG_MNEM_SUFFIX;
7089 }
9306ca4a 7090
a724f0f4
JB		 7091 else if (prev_token.code == T_FWORD)
7092 {
7093 if (current_templates->start->name[0] == 'l'
7094 && current_templates->start->name[2] == 's'
7095 && current_templates->start->name[3] == 0)
7096 suffix = LONG_MNEM_SUFFIX;
7097 else if (!intel_parser.got_a_float)
7098 {
7099 if (flag_code == CODE_16BIT)
7100 add_prefix (DATA_PREFIX_OPCODE);
7101 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7102 }
7103 else
7104 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7105 }
64a0c779 7106
a724f0f4
JB		 7107 else if (prev_token.code == T_QWORD)
7108 {
7109 if (intel_parser.got_a_float == 1) /* "f..." */
7110 suffix = LONG_MNEM_SUFFIX;
7111 else
7112 suffix = QWORD_MNEM_SUFFIX;
7113 }
64a0c779 7114
a724f0f4
JB		 7115 else if (prev_token.code == T_TBYTE)
7116 {
7117 if (intel_parser.got_a_float == 1)
7118 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7119 else
7120 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7121 }
9306ca4a 7122
a724f0f4 7123 else if (prev_token.code == T_XMMWORD)
9306ca4a 7124 {
a724f0f4
JB		 7125 /* XXX ignored for now, but accepted since gcc uses it */
7126 suffix = 0;
9306ca4a 7127 }
64a0c779 7128
f16b83df 7129 else
a724f0f4
JB		 7130 {
7131 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
7132 return 0;
7133 }
7134
435acd52
JB		 7135 /* Operands for jump/call using 'ptr' notation denote absolute
7136 addresses. */
7137 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7138 i.types[this_operand] |= JumpAbsolute;
7139
a724f0f4
JB		 7140 if (current_templates->start->base_opcode == 0x8d /* lea */)
7141 ;
7142 else if (!i.suffix)
7143 i.suffix = suffix;
7144 else if (i.suffix != suffix)
7145 {
7146 as_bad (_("Conflicting operand modifiers"));
7147 return 0;
7148 }
64a0c779 7149
9306ca4a
JB		 7150 }
7151
a724f0f4
JB		 7152 /* e09' : e10 e09' */
7153 else if (cur_token.code == ':')
9306ca4a 7154 {
a724f0f4
JB		 7155 if (prev_token.code != T_REG)
7156 {
7157 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7158 segment/group identifier (which we don't have), using comma
7159 as the operand separator there is even less consistent, since
7160 there all branches only have a single operand. */
7161 if (this_operand != 0
7162 || intel_parser.in_offset
7163 || intel_parser.in_bracket
7164 || (!(current_templates->start->opcode_modifier
7165 & (Jump|JumpDword|JumpInterSegment))
7166 && !(current_templates->start->operand_types[0]
7167 & JumpAbsolute)))
7168 return intel_match_token (T_NIL);
7169 /* Remember the start of the 2nd operand and terminate 1st
7170 operand here.
7171 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7172 another expression), but it gets at least the simplest case
7173 (a plain number or symbol on the left side) right. */
7174 intel_parser.next_operand = intel_parser.op_string;
7175 *--intel_parser.op_string = '\0';
7176 return intel_match_token (':');
7177 }
9306ca4a 7178 }
64a0c779 7179
a724f0f4 7180 /* e09' Empty */
64a0c779 7181 else
a724f0f4 7182 break;
64a0c779 7183
a724f0f4
JB		 7184 intel_match_token (cur_token.code);
7185
7186 }
7187
7188 if (in_offset)
7189 {
7190 --intel_parser.in_offset;
7191 if (nregs < 0)
7192 nregs = ~nregs;
7193 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 7194 {
a724f0f4 7195 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 7196 return 0;
7197 }
a724f0f4
JB		 7198 intel_parser.op_modifier |= 1 << T_OFFSET;
7199 }
9306ca4a 7200
a724f0f4
JB		 7201 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7202 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7203 return 1;
7204}
64a0c779 7205
a724f0f4 7206static int
e3bb37b5 7207intel_bracket_expr (void)
a724f0f4
JB		 7208{
7209 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7210 const char *start = intel_parser.op_string;
7211 int len;
7212
7213 if (i.op[this_operand].regs)
7214 return intel_match_token (T_NIL);
7215
7216 intel_match_token ('[');
7217
7218 /* Mark as a memory operand only if it's not already known to be an
7219 offset expression. If it's an offset expression, we need to keep
7220 the brace in. */
7221 if (!intel_parser.in_offset)
7222 {
7223 ++intel_parser.in_bracket;
435acd52
JB		 7224
7225 /* Operands for jump/call inside brackets denote absolute addresses. */
7226 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7227 i.types[this_operand] |= JumpAbsolute;
7228
a724f0f4
JB		 7229 /* Unfortunately gas always diverged from MASM in a respect that can't
7230 be easily fixed without risking to break code sequences likely to be
7231 encountered (the testsuite even check for this): MASM doesn't consider
7232 an expression inside brackets unconditionally as a memory reference.
7233 When that is e.g. a constant, an offset expression, or the sum of the
7234 two, this is still taken as a constant load. gas, however, always
7235 treated these as memory references. As a compromise, we'll try to make
7236 offset expressions inside brackets work the MASM way (since that's
7237 less likely to be found in real world code), but make constants alone
7238 continue to work the traditional gas way. In either case, issue a
7239 warning. */
7240 intel_parser.op_modifier &= ~was_offset;
64a0c779 7241 }
a724f0f4 7242 else
64e74474 7243 strcat (intel_parser.disp, "[");
a724f0f4
JB		 7244
7245 /* Add a '+' to the displacement string if necessary. */
7246 if (*intel_parser.disp != '\0'
7247 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7248 strcat (intel_parser.disp, "+");
64a0c779 7249
a724f0f4
JB		 7250 if (intel_expr ()
7251 && (len = intel_parser.op_string - start - 1,
7252 intel_match_token (']')))
64a0c779 7253 {
a724f0f4
JB		 7254 /* Preserve brackets when the operand is an offset expression. */
7255 if (intel_parser.in_offset)
7256 strcat (intel_parser.disp, "]");
7257 else
7258 {
7259 --intel_parser.in_bracket;
7260 if (i.base_reg || i.index_reg)
7261 intel_parser.is_mem = 1;
7262 if (!intel_parser.is_mem)
7263 {
7264 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7265 /* Defer the warning until all of the operand was parsed. */
7266 intel_parser.is_mem = -1;
7267 else if (!quiet_warnings)
4eed87de
AM		 7268 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
7269 len, start, len, start);
a724f0f4
JB		 7270 }
7271 }
7272 intel_parser.op_modifier |= was_offset;
64a0c779 7273
a724f0f4 7274 return 1;
64a0c779 7275 }
a724f0f4 7276 return 0;
64a0c779
DN		 7277}
7278
7279/* e10 e11 e10'
7280
7281 e10' [ expr ] e10'
b77a7acd 7282 | Empty */
64a0c779 7283static int
e3bb37b5 7284intel_e10 (void)
64a0c779 7285{
a724f0f4
JB		 7286 if (!intel_e11 ())
7287 return 0;
64a0c779 7288
a724f0f4 7289 while (cur_token.code == '[')
64a0c779 7290 {
a724f0f4 7291 if (!intel_bracket_expr ())
21d6c4af 7292 return 0;
64a0c779
DN		 7293 }
7294
a724f0f4 7295 return 1;
64a0c779
DN		 7296}
7297
64a0c779 7298/* e11 ( expr )
b77a7acd 7299 | [ expr ]
64a0c779
DN		 7300 | BYTE
7301 | WORD
7302 | DWORD
9306ca4a 7303 | FWORD
64a0c779 7304 | QWORD
9306ca4a
JB		 7305 | TBYTE
7306 | OWORD
7307 | XMMWORD
4a1805b1 7308 | $
64a0c779
DN		 7309 | .
7310 | register
7311 | id
7312 | constant */
7313static int
e3bb37b5 7314intel_e11 (void)
64a0c779 7315{
a724f0f4 7316 switch (cur_token.code)
64a0c779 7317 {
a724f0f4
JB		 7318 /* e11 ( expr ) */
7319 case '(':
64a0c779
DN		 7320 intel_match_token ('(');
7321 strcat (intel_parser.disp, "(");
7322
7323 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7324 {
7325 strcat (intel_parser.disp, ")");
7326 return 1;
7327 }
a724f0f4 7328 return 0;
4a1805b1 7329
a724f0f4
JB		 7330 /* e11 [ expr ] */
7331 case '[':
a724f0f4 7332 return intel_bracket_expr ();
64a0c779 7333
a724f0f4
JB		 7334 /* e11 $
7335 | . */
7336 case '.':
64a0c779
DN		 7337 strcat (intel_parser.disp, cur_token.str);
7338 intel_match_token (cur_token.code);
21d6c4af
DN		 7339
7340 /* Mark as a memory operand only if it's not already known to be an
7341 offset expression. */
a724f0f4 7342 if (!intel_parser.in_offset)
21d6c4af 7343 intel_parser.is_mem = 1;
64a0c779
DN		 7344
7345 return 1;
64a0c779 7346
a724f0f4
JB		 7347 /* e11 register */
7348 case T_REG:
7349 {
7350 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7351
a724f0f4 7352 intel_match_token (T_REG);
64a0c779 7353
a724f0f4
JB		 7354 /* Check for segment change. */
7355 if (cur_token.code == ':')
7356 {
7357 if (!(reg->reg_type & (SReg2 | SReg3)))
7358 {
4eed87de
AM		 7359 as_bad (_("`%s' is not a valid segment register"),
7360 reg->reg_name);
a724f0f4
JB		 7361 return 0;
7362 }
7363 else if (i.seg[i.mem_operands])
7364 as_warn (_("Extra segment override ignored"));
7365 else
7366 {
7367 if (!intel_parser.in_offset)
7368 intel_parser.is_mem = 1;
7369 switch (reg->reg_num)
7370 {
7371 case 0:
7372 i.seg[i.mem_operands] = &es;
7373 break;
7374 case 1:
7375 i.seg[i.mem_operands] = &cs;
7376 break;
7377 case 2:
7378 i.seg[i.mem_operands] = &ss;
7379 break;
7380 case 3:
7381 i.seg[i.mem_operands] = &ds;
7382 break;
7383 case 4:
7384 i.seg[i.mem_operands] = &fs;
7385 break;
7386 case 5:
7387 i.seg[i.mem_operands] = &gs;
7388 break;
7389 }
7390 }
7391 }
64a0c779 7392
a724f0f4
JB		 7393 /* Not a segment register. Check for register scaling. */
7394 else if (cur_token.code == '*')
7395 {
7396 if (!intel_parser.in_bracket)
7397 {
7398 as_bad (_("Register scaling only allowed in memory operands"));
7399 return 0;
7400 }
64a0c779 7401
a724f0f4
JB		 7402 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7403 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7404 else if (i.index_reg)
7405 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 7406
a724f0f4
JB		 7407 /* What follows must be a valid scale. */
7408 intel_match_token ('*');
7409 i.index_reg = reg;
7410 i.types[this_operand] |= BaseIndex;
64a0c779 7411
a724f0f4
JB		 7412 /* Set the scale after setting the register (otherwise,
7413 i386_scale will complain) */
7414 if (cur_token.code == '+' || cur_token.code == '-')
7415 {
7416 char *str, sign = cur_token.code;
7417 intel_match_token (cur_token.code);
7418 if (cur_token.code != T_CONST)
7419 {
7420 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7421 cur_token.str);
7422 return 0;
7423 }
7424 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7425 strcpy (str + 1, cur_token.str);
7426 *str = sign;
7427 if (!i386_scale (str))
7428 return 0;
7429 free (str);
7430 }
7431 else if (!i386_scale (cur_token.str))
64a0c779 7432 return 0;
a724f0f4
JB		 7433 intel_match_token (cur_token.code);
7434 }
64a0c779 7435
a724f0f4
JB		 7436 /* No scaling. If this is a memory operand, the register is either a
7437 base register (first occurrence) or an index register (second
7438 occurrence). */
7b0441f6 7439 else if (intel_parser.in_bracket)
a724f0f4 7440 {
64a0c779 7441
a724f0f4
JB		 7442 if (!i.base_reg)
7443 i.base_reg = reg;
7444 else if (!i.index_reg)
7445 i.index_reg = reg;
7446 else
7447 {
7448 as_bad (_("Too many register references in memory operand"));
7449 return 0;
7450 }
64a0c779 7451
a724f0f4
JB		 7452 i.types[this_operand] |= BaseIndex;
7453 }
4a1805b1 7454
4d1bb795
JB		 7455 /* It's neither base nor index. */
7456 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 7457 {
7458 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7459 i.op[this_operand].regs = reg;
7460 i.reg_operands++;
7461 }
7462 else
7463 {
7464 as_bad (_("Invalid use of register"));
7465 return 0;
7466 }
64a0c779 7467
a724f0f4
JB		 7468 /* Since registers are not part of the displacement string (except
7469 when we're parsing offset operands), we may need to remove any
7470 preceding '+' from the displacement string. */
7471 if (*intel_parser.disp != '\0'
7472 && !intel_parser.in_offset)
7473 {
7474 char *s = intel_parser.disp;
7475 s += strlen (s) - 1;
7476 if (*s == '+')
7477 *s = '\0';
7478 }
4a1805b1 7479
a724f0f4
JB		 7480 return 1;
7481 }
7482
7483 /* e11 BYTE
7484 | WORD
7485 | DWORD
7486 | FWORD
7487 | QWORD
7488 | TBYTE
7489 | OWORD
7490 | XMMWORD */
7491 case T_BYTE:
7492 case T_WORD:
7493 case T_DWORD:
7494 case T_FWORD:
7495 case T_QWORD:
7496 case T_TBYTE:
7497 case T_XMMWORD:
7498 intel_match_token (cur_token.code);
64a0c779 7499
a724f0f4
JB		 7500 if (cur_token.code == T_PTR)
7501 return 1;
7502
7503 /* It must have been an identifier. */
7504 intel_putback_token ();
7505 cur_token.code = T_ID;
7506 /* FALLTHRU */
7507
7508 /* e11 id
7509 | constant */
7510 case T_ID:
7511 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 7512 {
7513 symbolS *symbolP;
7514
a724f0f4
JB		 7515 /* The identifier represents a memory reference only if it's not
7516 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 7517 symbolP = symbol_find(cur_token.str);
7518 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7519 intel_parser.is_mem = 1;
7520 }
a724f0f4 7521 /* FALLTHRU */
64a0c779 7522
a724f0f4
JB		 7523 case T_CONST:
7524 case '-':
7525 case '+':
7526 {
7527 char *save_str, sign = 0;
64a0c779 7528
a724f0f4
JB		 7529 /* Allow constants that start with `+' or `-'. */
7530 if (cur_token.code == '-' || cur_token.code == '+')
7531 {
7532 sign = cur_token.code;
7533 intel_match_token (cur_token.code);
7534 if (cur_token.code != T_CONST)
7535 {
7536 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7537 cur_token.str);
7538 return 0;
7539 }
7540 }
64a0c779 7541
a724f0f4
JB		 7542 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7543 strcpy (save_str + !!sign, cur_token.str);
7544 if (sign)
7545 *save_str = sign;
64a0c779 7546
a724f0f4
JB		 7547 /* Get the next token to check for register scaling. */
7548 intel_match_token (cur_token.code);
64a0c779 7549
4eed87de
AM		 7550 /* Check if this constant is a scaling factor for an
7551 index register. */
a724f0f4
JB		 7552 if (cur_token.code == '*')
7553 {
7554 if (intel_match_token ('*') && cur_token.code == T_REG)
7555 {
7556 const reg_entry *reg = cur_token.reg;
7557
7558 if (!intel_parser.in_bracket)
7559 {
4eed87de
AM		 7560 as_bad (_("Register scaling only allowed "
7561 "in memory operands"));
a724f0f4
JB		 7562 return 0;
7563 }
7564
4eed87de
AM		 7565 /* Disallow things like [1*si].
7566 sp and esp are invalid as index. */
7567 if (reg->reg_type & Reg16)
7568 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 7569 else if (i.index_reg)
4eed87de 7570 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 7571
7572 /* The constant is followed by `* reg', so it must be
7573 a valid scale. */
7574 i.index_reg = reg;
7575 i.types[this_operand] |= BaseIndex;
7576
7577 /* Set the scale after setting the register (otherwise,
7578 i386_scale will complain) */
7579 if (!i386_scale (save_str))
64a0c779 7580 return 0;
a724f0f4
JB		 7581 intel_match_token (T_REG);
7582
7583 /* Since registers are not part of the displacement
7584 string, we may need to remove any preceding '+' from
7585 the displacement string. */
7586 if (*intel_parser.disp != '\0')
7587 {
7588 char *s = intel_parser.disp;
7589 s += strlen (s) - 1;
7590 if (*s == '+')
7591 *s = '\0';
7592 }
7593
7594 free (save_str);
7595
7596 return 1;
7597 }
64a0c779 7598
a724f0f4
JB		 7599 /* The constant was not used for register scaling. Since we have
7600 already consumed the token following `*' we now need to put it
7601 back in the stream. */
64a0c779 7602 intel_putback_token ();
a724f0f4 7603 }
64a0c779 7604
a724f0f4
JB		 7605 /* Add the constant to the displacement string. */
7606 strcat (intel_parser.disp, save_str);
7607 free (save_str);
64a0c779 7608
a724f0f4
JB		 7609 return 1;
7610 }
64a0c779
DN		 7611 }
7612
64a0c779
DN		 7613 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7614 return 0;
7615}
7616
64a0c779
DN		 7617/* Match the given token against cur_token. If they match, read the next
7618 token from the operand string. */
7619static int
e3bb37b5 7620intel_match_token (int code)
64a0c779
DN		 7621{
7622 if (cur_token.code == code)
7623 {
7624 intel_get_token ();
7625 return 1;
7626 }
7627 else
7628 {
0477af35 7629 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 7630 return 0;
7631 }
7632}
7633
64a0c779
DN		 7634/* Read a new token from intel_parser.op_string and store it in cur_token. */
7635static void
e3bb37b5 7636intel_get_token (void)
64a0c779
DN		 7637{
7638 char *end_op;
7639 const reg_entry *reg;
7640 struct intel_token new_token;
7641
7642 new_token.code = T_NIL;
7643 new_token.reg = NULL;
7644 new_token.str = NULL;
7645
4a1805b1 7646 /* Free the memory allocated to the previous token and move
64a0c779
DN		 7647 cur_token to prev_token. */
7648 if (prev_token.str)
7649 free (prev_token.str);
7650
7651 prev_token = cur_token;
7652
7653 /* Skip whitespace. */
7654 while (is_space_char (*intel_parser.op_string))
7655 intel_parser.op_string++;
7656
7657 /* Return an empty token if we find nothing else on the line. */
7658 if (*intel_parser.op_string == '\0')
7659 {
7660 cur_token = new_token;
7661 return;
7662 }
7663
7664 /* The new token cannot be larger than the remainder of the operand
7665 string. */
a724f0f4 7666 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7667 new_token.str[0] = '\0';
7668
7669 if (strchr ("0123456789", *intel_parser.op_string))
7670 {
7671 char *p = new_token.str;
7672 char *q = intel_parser.op_string;
7673 new_token.code = T_CONST;
7674
7675 /* Allow any kind of identifier char to encompass floating point and
7676 hexadecimal numbers. */
7677 while (is_identifier_char (*q))
7678 *p++ = *q++;
7679 *p = '\0';
7680
7681 /* Recognize special symbol names [0-9][bf]. */
7682 if (strlen (intel_parser.op_string) == 2
4a1805b1 7683 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7684 || intel_parser.op_string[1] == 'f'))
7685 new_token.code = T_ID;
7686 }
7687
4d1bb795 7688 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7689 {
4d1bb795
JB		 7690 size_t len = end_op - intel_parser.op_string;
7691
64a0c779
DN		 7692 new_token.code = T_REG;
7693 new_token.reg = reg;
7694
4d1bb795
JB		 7695 memcpy (new_token.str, intel_parser.op_string, len);
7696 new_token.str[len] = '\0';
64a0c779
DN		 7697 }
7698
7699 else if (is_identifier_char (*intel_parser.op_string))
7700 {
7701 char *p = new_token.str;
7702 char *q = intel_parser.op_string;
7703
7704 /* A '.' or '$' followed by an identifier char is an identifier.
7705 Otherwise, it's operator '.' followed by an expression. */
7706 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7707 {
9306ca4a
JB		 7708 new_token.code = '.';
7709 new_token.str[0] = '.';
64a0c779
DN		 7710 new_token.str[1] = '\0';
7711 }
7712 else
7713 {
7714 while (is_identifier_char (*q) || *q == '@')
7715 *p++ = *q++;
7716 *p = '\0';
7717
9306ca4a
JB		 7718 if (strcasecmp (new_token.str, "NOT") == 0)
7719 new_token.code = '~';
7720
7721 else if (strcasecmp (new_token.str, "MOD") == 0)
7722 new_token.code = '%';
7723
7724 else if (strcasecmp (new_token.str, "AND") == 0)
7725 new_token.code = '&';
7726
7727 else if (strcasecmp (new_token.str, "OR") == 0)
7728 new_token.code = '|';
7729
7730 else if (strcasecmp (new_token.str, "XOR") == 0)
7731 new_token.code = '^';
7732
7733 else if (strcasecmp (new_token.str, "SHL") == 0)
7734 new_token.code = T_SHL;
7735
7736 else if (strcasecmp (new_token.str, "SHR") == 0)
7737 new_token.code = T_SHR;
7738
7739 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7740 new_token.code = T_BYTE;
7741
7742 else if (strcasecmp (new_token.str, "WORD") == 0)
7743 new_token.code = T_WORD;
7744
7745 else if (strcasecmp (new_token.str, "DWORD") == 0)
7746 new_token.code = T_DWORD;
7747
9306ca4a
JB		 7748 else if (strcasecmp (new_token.str, "FWORD") == 0)
7749 new_token.code = T_FWORD;
7750
64a0c779
DN		 7751 else if (strcasecmp (new_token.str, "QWORD") == 0)
7752 new_token.code = T_QWORD;
7753
9306ca4a
JB		 7754 else if (strcasecmp (new_token.str, "TBYTE") == 0
7755 /* XXX remove (gcc still uses it) */
7756 || strcasecmp (new_token.str, "XWORD") == 0)
7757 new_token.code = T_TBYTE;
7758
7759 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7760 || strcasecmp (new_token.str, "OWORD") == 0)
7761 new_token.code = T_XMMWORD;
64a0c779
DN		 7762
7763 else if (strcasecmp (new_token.str, "PTR") == 0)
7764 new_token.code = T_PTR;
7765
7766 else if (strcasecmp (new_token.str, "SHORT") == 0)
7767 new_token.code = T_SHORT;
7768
7769 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7770 {
7771 new_token.code = T_OFFSET;
7772
7773 /* ??? This is not mentioned in the MASM grammar but gcc
7774 makes use of it with -mintel-syntax. OFFSET may be
7775 followed by FLAT: */
7776 if (strncasecmp (q, " FLAT:", 6) == 0)
7777 strcat (new_token.str, " FLAT:");
7778 }
7779
7780 /* ??? This is not mentioned in the MASM grammar. */
7781 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7782 {
7783 new_token.code = T_OFFSET;
7784 if (*q == ':')
7785 strcat (new_token.str, ":");
7786 else
7787 as_bad (_("`:' expected"));
7788 }
64a0c779
DN		 7789
7790 else
7791 new_token.code = T_ID;
7792 }
7793 }
7794
9306ca4a
JB		 7795 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7796 {
7797 new_token.code = *intel_parser.op_string;
7798 new_token.str[0] = *intel_parser.op_string;
7799 new_token.str[1] = '\0';
7800 }
7801
7802 else if (strchr ("<>", *intel_parser.op_string)
7803 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7804 {
7805 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7806 new_token.str[0] = *intel_parser.op_string;
7807 new_token.str[1] = *intel_parser.op_string;
7808 new_token.str[2] = '\0';
7809 }
7810
64a0c779 7811 else
0477af35 7812 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7813
7814 intel_parser.op_string += strlen (new_token.str);
7815 cur_token = new_token;
7816}
7817
64a0c779
DN		 7818/* Put cur_token back into the token stream and make cur_token point to
7819 prev_token. */
7820static void
e3bb37b5 7821intel_putback_token (void)
64a0c779 7822{
a724f0f4
JB		 7823 if (cur_token.code != T_NIL)
7824 {
7825 intel_parser.op_string -= strlen (cur_token.str);
7826 free (cur_token.str);
7827 }
64a0c779 7828 cur_token = prev_token;
4a1805b1 7829
64a0c779
DN		 7830 /* Forget prev_token. */
7831 prev_token.code = T_NIL;
7832 prev_token.reg = NULL;
7833 prev_token.str = NULL;
7834}
54cfded0 7835
a4447b93 7836int
1df69f4f 7837tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 7838{
7839 unsigned int regnum;
7840 unsigned int regnames_count;
089dfecd 7841 static const char *const regnames_32[] =
54cfded0 7842 {
a4447b93
RH		 7843 "eax", "ecx", "edx", "ebx",
7844 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7845 "eip", "eflags", NULL,
7846 "st0", "st1", "st2", "st3",
7847 "st4", "st5", "st6", "st7",
7848 NULL, NULL,
7849 "xmm0", "xmm1", "xmm2", "xmm3",
7850 "xmm4", "xmm5", "xmm6", "xmm7",
7851 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7852 "mm4", "mm5", "mm6", "mm7",
7853 "fcw", "fsw", "mxcsr",
7854 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7855 "tr", "ldtr"
54cfded0 7856 };
089dfecd 7857 static const char *const regnames_64[] =
54cfded0 7858 {
089dfecd
JB		 7859 "rax", "rdx", "rcx", "rbx",
7860 "rsi", "rdi", "rbp", "rsp",
7861 "r8", "r9", "r10", "r11",
54cfded0 7862 "r12", "r13", "r14", "r15",
089dfecd
JB		 7863 "rip",
7864 "xmm0", "xmm1", "xmm2", "xmm3",
7865 "xmm4", "xmm5", "xmm6", "xmm7",
7866 "xmm8", "xmm9", "xmm10", "xmm11",
7867 "xmm12", "xmm13", "xmm14", "xmm15",
7868 "st0", "st1", "st2", "st3",
7869 "st4", "st5", "st6", "st7",
7870 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7871 "mm4", "mm5", "mm6", "mm7",
7872 "rflags",
7873 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7874 "fs.base", "gs.base", NULL, NULL,
7875 "tr", "ldtr",
7876 "mxcsr", "fcw", "fsw"
54cfded0 7877 };
089dfecd 7878 const char *const *regnames;
54cfded0
AM		 7879
7880 if (flag_code == CODE_64BIT)
7881 {
7882 regnames = regnames_64;
0cea6190 7883 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7884 }
7885 else
7886 {
7887 regnames = regnames_32;
0cea6190 7888 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7889 }
7890
7891 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7892 if (regnames[regnum] != NULL
7893 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7894 return regnum;
7895
54cfded0
AM		 7896 return -1;
7897}
7898
7899void
7900tc_x86_frame_initial_instructions (void)
7901{
a4447b93
RH		 7902 static unsigned int sp_regno;
7903
7904 if (!sp_regno)
7905 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7906 ? "rsp" : "esp");
7907
7908 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7909 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7910}
d2b2c203
DJ		 7911
7912int
7913i386_elf_section_type (const char *str, size_t len)
7914{
7915 if (flag_code == CODE_64BIT
7916 && len == sizeof ("unwind") - 1
7917 && strncmp (str, "unwind", 6) == 0)
7918 return SHT_X86_64_UNWIND;
7919
7920 return -1;
7921}
bb41ade5
AM		 7922
7923#ifdef TE_PE
7924void
7925tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7926{
7927 expressionS expr;
7928
7929 expr.X_op = O_secrel;
7930 expr.X_add_symbol = symbol;
7931 expr.X_add_number = 0;
7932 emit_expr (&expr, size);
7933}
7934#endif
3b22753a
L		 7935
7936#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7937/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7938
7939int
7940x86_64_section_letter (int letter, char **ptr_msg)
7941{
7942 if (flag_code == CODE_64BIT)
7943 {
7944 if (letter == 'l')
7945 return SHF_X86_64_LARGE;
7946
7947 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7948 }
3b22753a 7949 else
64e74474 7950 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7951 return -1;
7952}
7953
7954int
7955x86_64_section_word (char *str, size_t len)
7956{
8620418b 7957 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 7958 return SHF_X86_64_LARGE;
7959
7960 return -1;
7961}
7962
7963static void
7964handle_large_common (int small ATTRIBUTE_UNUSED)
7965{
7966 if (flag_code != CODE_64BIT)
7967 {
7968 s_comm_internal (0, elf_common_parse);
7969 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7970 }
7971 else
7972 {
7973 static segT lbss_section;
7974 asection *saved_com_section_ptr = elf_com_section_ptr;
7975 asection *saved_bss_section = bss_section;
7976
7977 if (lbss_section == NULL)
7978 {
7979 flagword applicable;
7980 segT seg = now_seg;
7981 subsegT subseg = now_subseg;
7982
7983 /* The .lbss section is for local .largecomm symbols. */
7984 lbss_section = subseg_new (".lbss", 0);
7985 applicable = bfd_applicable_section_flags (stdoutput);
7986 bfd_set_section_flags (stdoutput, lbss_section,
7987 applicable & SEC_ALLOC);
7988 seg_info (lbss_section)->bss = 1;
7989
7990 subseg_set (seg, subseg);
7991 }
7992
7993 elf_com_section_ptr = &_bfd_elf_large_com_section;
7994 bss_section = lbss_section;
7995
7996 s_comm_internal (0, elf_common_parse);
7997
7998 elf_com_section_ptr = saved_com_section_ptr;
7999 bss_section = saved_bss_section;
8000 }
8001}
8002#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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