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2007-09-08 H.J. Lu <hongjiu.lu@intel.com>
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4dc85607 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
e3bb37b5
L		 66static void set_code_flag (int);
67static void set_16bit_gcc_code_flag (int);
68static void set_intel_syntax (int);
69static void set_cpu_arch (int);
6482c264 70#ifdef TE_PE
e3bb37b5 71static void pe_directive_secrel (int);
6482c264 72#endif
e3bb37b5
L		 73static void signed_cons (int);
74static char *output_invalid (int c);
75static int i386_operand (char *);
76static int i386_intel_operand (char *, int);
77static const reg_entry *parse_register (char *, char **);
78static char *parse_insn (char *, char *);
79static char *parse_operands (char *, const char *);
80static void swap_operands (void);
4d456e3d 81static void swap_2_operands (int, int);
e3bb37b5
L		 82static void optimize_imm (void);
83static void optimize_disp (void);
84static int match_template (void);
85static int check_string (void);
86static int process_suffix (void);
87static int check_byte_reg (void);
88static int check_long_reg (void);
89static int check_qword_reg (void);
90static int check_word_reg (void);
91static int finalize_imm (void);
92static int process_operands (void);
93static const seg_entry *build_modrm_byte (void);
94static void output_insn (void);
95static void output_imm (fragS *, offsetT);
96static void output_disp (fragS *, offsetT);
29b0f896 97#ifndef I386COFF
e3bb37b5 98static void s_bss (int);
252b5132 99#endif
17d4e2a2
L		 100#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
101static void handle_large_common (int small ATTRIBUTE_UNUSED);
102#endif
252b5132 103
a847613f 104static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 105
252b5132 106/* 'md_assemble ()' gathers together information and puts it into a
47926f60 107 i386_insn. */
252b5132 108
520dc8e8
AM		 109union i386_op
110 {
111 expressionS *disps;
112 expressionS *imms;
113 const reg_entry *regs;
114 };
115
252b5132
RH		 116struct _i386_insn
117 {
47926f60 118 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 119 template tm;
120
121 /* SUFFIX holds the instruction mnemonic suffix if given.
122 (e.g. 'l' for 'movl') */
123 char suffix;
124
47926f60 125 /* OPERANDS gives the number of given operands. */
252b5132
RH		 126 unsigned int operands;
127
128 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
129 of given register, displacement, memory operands and immediate
47926f60 130 operands. */
252b5132
RH		 131 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
132
133 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 134 use OP[i] for the corresponding operand. */
40fb9820 135 i386_operand_type types[MAX_OPERANDS];
252b5132 136
520dc8e8
AM		 137 /* Displacement expression, immediate expression, or register for each
138 operand. */
139 union i386_op op[MAX_OPERANDS];
252b5132 140
3e73aa7c
JH		 141 /* Flags for operands. */
142 unsigned int flags[MAX_OPERANDS];
143#define Operand_PCrel 1
144
252b5132 145 /* Relocation type for operand */
f86103b7 146 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 147
252b5132
RH		 148 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
149 the base index byte below. */
150 const reg_entry *base_reg;
151 const reg_entry *index_reg;
152 unsigned int log2_scale_factor;
153
154 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 155 explicit segment overrides are given. */
ce8a8b2f 156 const seg_entry *seg[2];
252b5132
RH		 157
158 /* PREFIX holds all the given prefix opcodes (usually null).
159 PREFIXES is the number of prefix opcodes. */
160 unsigned int prefixes;
161 unsigned char prefix[MAX_PREFIXES];
162
163 /* RM and SIB are the modrm byte and the sib byte where the
164 addressing modes of this insn are encoded. */
165
166 modrm_byte rm;
3e73aa7c 167 rex_byte rex;
252b5132
RH		 168 sib_byte sib;
169 };
170
171typedef struct _i386_insn i386_insn;
172
173/* List of chars besides those in app.c:symbol_chars that can start an
174 operand. Used to prevent the scrubber eating vital white-space. */
32137342 175const char extra_symbol_chars[] = "*%-(["
252b5132 176#ifdef LEX_AT
32137342
NC		 177 "@"
178#endif
179#ifdef LEX_QM
180 "?"
252b5132 181#endif
32137342 182 ;
252b5132 183
29b0f896
AM		 184#if (defined (TE_I386AIX) \
185 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 186 && !defined (TE_GNU) \
29b0f896 187 && !defined (TE_LINUX) \
32137342 188 && !defined (TE_NETWARE) \
29b0f896
AM		 189 && !defined (TE_FreeBSD) \
190 && !defined (TE_NetBSD)))
252b5132 191/* This array holds the chars that always start a comment. If the
b3b91714
AM		 192 pre-processor is disabled, these aren't very useful. The option
193 --divide will remove '/' from this list. */
194const char *i386_comment_chars = "#/";
195#define SVR4_COMMENT_CHARS 1
252b5132 196#define PREFIX_SEPARATOR '\\'
252b5132 197
b3b91714
AM		 198#else
199const char *i386_comment_chars = "#";
200#define PREFIX_SEPARATOR '/'
201#endif
202
252b5132
RH		 203/* This array holds the chars that only start a comment at the beginning of
204 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 205 .line and .file directives will appear in the pre-processed output.
206 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 207 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 208 #NO_APP at the beginning of its output.
209 Also note that comments started like this one will always work if
252b5132 210 '/' isn't otherwise defined. */
b3b91714 211const char line_comment_chars[] = "#/";
252b5132 212
63a0b638 213const char line_separator_chars[] = ";";
252b5132 214
ce8a8b2f
AM		 215/* Chars that can be used to separate mant from exp in floating point
216 nums. */
252b5132
RH		 217const char EXP_CHARS[] = "eE";
218
ce8a8b2f
AM		 219/* Chars that mean this number is a floating point constant
220 As in 0f12.456
221 or 0d1.2345e12. */
252b5132
RH		 222const char FLT_CHARS[] = "fFdDxX";
223
ce8a8b2f 224/* Tables for lexical analysis. */
252b5132
RH		 225static char mnemonic_chars[256];
226static char register_chars[256];
227static char operand_chars[256];
228static char identifier_chars[256];
229static char digit_chars[256];
230
ce8a8b2f 231/* Lexical macros. */
252b5132
RH		 232#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
233#define is_operand_char(x) (operand_chars[(unsigned char) x])
234#define is_register_char(x) (register_chars[(unsigned char) x])
235#define is_space_char(x) ((x) == ' ')
236#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
237#define is_digit_char(x) (digit_chars[(unsigned char) x])
238
0234cb7c 239/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 240static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
241
242/* md_assemble() always leaves the strings it's passed unaltered. To
243 effect this we maintain a stack of saved characters that we've smashed
244 with '\0's (indicating end of strings for various sub-fields of the
47926f60 245 assembler instruction). */
252b5132 246static char save_stack[32];
ce8a8b2f 247static char *save_stack_p;
252b5132
RH		 248#define END_STRING_AND_SAVE(s) \
249 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
250#define RESTORE_END_STRING(s) \
251 do { *(s) = *--save_stack_p; } while (0)
252
47926f60 253/* The instruction we're assembling. */
252b5132
RH		 254static i386_insn i;
255
256/* Possible templates for current insn. */
257static const templates *current_templates;
258
31b2323c
L		 259/* Per instruction expressionS buffers: max displacements & immediates. */
260static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
261static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 262
47926f60
KH		 263/* Current operand we are working on. */
264static int this_operand;
252b5132 265
3e73aa7c
JH		 266/* We support four different modes. FLAG_CODE variable is used to distinguish
267 these. */
268
269enum flag_code {
270 CODE_32BIT,
271 CODE_16BIT,
272 CODE_64BIT };
f3c180ae 273#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 274
275static enum flag_code flag_code;
4fa24527 276static unsigned int object_64bit;
3e73aa7c
JH		 277static int use_rela_relocations = 0;
278
279/* The names used to print error messages. */
b77a7acd 280static const char *flag_code_names[] =
3e73aa7c
JH		 281 {
282 "32",
283 "16",
284 "64"
285 };
252b5132 286
47926f60
KH		 287/* 1 for intel syntax,
288 0 if att syntax. */
289static int intel_syntax = 0;
252b5132 290
47926f60
KH		 291/* 1 if register prefix % not required. */
292static int allow_naked_reg = 0;
252b5132 293
2ca3ace5
L		 294/* Register prefix used for error message. */
295static const char *register_prefix = "%";
296
47926f60
KH		 297/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
298 leave, push, and pop instructions so that gcc has the same stack
299 frame as in 32 bit mode. */
300static char stackop_size = '\0';
eecb386c 301
12b55ccc
L		 302/* Non-zero to optimize code alignment. */
303int optimize_align_code = 1;
304
47926f60
KH		 305/* Non-zero to quieten some warnings. */
306static int quiet_warnings = 0;
a38cf1db 307
47926f60
KH		 308/* CPU name. */
309static const char *cpu_arch_name = NULL;
5c6af06e 310static const char *cpu_sub_arch_name = NULL;
a38cf1db 311
47926f60 312/* CPU feature flags. */
40fb9820
L		 313static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
314
315/* Bitwise NOT of cpu_arch_flags. */
316static i386_cpu_flags cpu_arch_flags_not;
a38cf1db 317
ccc9c027
L		 318/* If we have selected a cpu we are generating instructions for. */
319static int cpu_arch_tune_set = 0;
320
9103f4f4
L		 321/* Cpu we are generating instructions for. */
322static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
323
324/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 325static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 326
ccc9c027
L		 327/* CPU instruction set architecture used. */
328static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
329
9103f4f4 330/* CPU feature flags of instruction set architecture used. */
40fb9820 331static i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 332
fddf5b5b
AM		 333/* If set, conditional jumps are not automatically promoted to handle
334 larger than a byte offset. */
335static unsigned int no_cond_jump_promotion = 0;
336
29b0f896 337/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 338static symbolS *GOT_symbol;
29b0f896 339
a4447b93
RH		 340/* The dwarf2 return column, adjusted for 32 or 64 bit. */
341unsigned int x86_dwarf2_return_column;
342
343/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
344int x86_cie_data_alignment;
345
252b5132 346/* Interface to relax_segment.
fddf5b5b
AM		 347 There are 3 major relax states for 386 jump insns because the
348 different types of jumps add different sizes to frags when we're
349 figuring out what sort of jump to choose to reach a given label. */
252b5132 350
47926f60 351/* Types. */
93c2a809
AM		 352#define UNCOND_JUMP 0
353#define COND_JUMP 1
354#define COND_JUMP86 2
fddf5b5b 355
47926f60 356/* Sizes. */
252b5132
RH		 357#define CODE16 1
358#define SMALL 0
29b0f896 359#define SMALL16 (SMALL | CODE16)
252b5132 360#define BIG 2
29b0f896 361#define BIG16 (BIG | CODE16)
252b5132
RH		 362
363#ifndef INLINE
364#ifdef __GNUC__
365#define INLINE __inline__
366#else
367#define INLINE
368#endif
369#endif
370
fddf5b5b
AM		 371#define ENCODE_RELAX_STATE(type, size) \
372 ((relax_substateT) (((type) << 2) | (size)))
373#define TYPE_FROM_RELAX_STATE(s) \
374 ((s) >> 2)
375#define DISP_SIZE_FROM_RELAX_STATE(s) \
376 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 377
378/* This table is used by relax_frag to promote short jumps to long
379 ones where necessary. SMALL (short) jumps may be promoted to BIG
380 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
381 don't allow a short jump in a 32 bit code segment to be promoted to
382 a 16 bit offset jump because it's slower (requires data size
383 prefix), and doesn't work, unless the destination is in the bottom
384 64k of the code segment (The top 16 bits of eip are zeroed). */
385
386const relax_typeS md_relax_table[] =
387{
24eab124
AM		 388 /* The fields are:
389 1) most positive reach of this state,
390 2) most negative reach of this state,
93c2a809 391 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 392 4) which index into the table to try if we can't fit into this one. */
252b5132 393
fddf5b5b 394 /* UNCOND_JUMP states. */
93c2a809
AM		 395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
396 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
397 /* dword jmp adds 4 bytes to frag:
398 0 extra opcode bytes, 4 displacement bytes. */
252b5132 399 {0, 0, 4, 0},
93c2a809
AM		 400 /* word jmp adds 2 byte2 to frag:
401 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 402 {0, 0, 2, 0},
403
93c2a809
AM		 404 /* COND_JUMP states. */
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
406 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
407 /* dword conditionals adds 5 bytes to frag:
408 1 extra opcode byte, 4 displacement bytes. */
409 {0, 0, 5, 0},
fddf5b5b 410 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 411 1 extra opcode byte, 2 displacement bytes. */
412 {0, 0, 3, 0},
413
414 /* COND_JUMP86 states. */
415 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
416 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
417 /* dword conditionals adds 5 bytes to frag:
418 1 extra opcode byte, 4 displacement bytes. */
419 {0, 0, 5, 0},
420 /* word conditionals add 4 bytes to frag:
421 1 displacement byte and a 3 byte long branch insn. */
422 {0, 0, 4, 0}
252b5132
RH		 423};
424
9103f4f4
L		 425static const arch_entry cpu_arch[] =
426{
427 {"generic32", PROCESSOR_GENERIC32,
40fb9820 428 CPU_GENERIC32_FLAGS },
9103f4f4 429 {"generic64", PROCESSOR_GENERIC64,
40fb9820 430 CPU_GENERIC64_FLAGS },
9103f4f4 431 {"i8086", PROCESSOR_UNKNOWN,
40fb9820 432 CPU_NONE_FLAGS },
9103f4f4 433 {"i186", PROCESSOR_UNKNOWN,
40fb9820 434 CPU_I186_FLAGS },
9103f4f4 435 {"i286", PROCESSOR_UNKNOWN,
40fb9820 436 CPU_I286_FLAGS },
76bc74dc 437 {"i386", PROCESSOR_I386,
40fb9820 438 CPU_I386_FLAGS },
9103f4f4 439 {"i486", PROCESSOR_I486,
40fb9820 440 CPU_I486_FLAGS },
9103f4f4 441 {"i586", PROCESSOR_PENTIUM,
40fb9820 442 CPU_I586_FLAGS },
9103f4f4 443 {"i686", PROCESSOR_PENTIUMPRO,
40fb9820 444 CPU_I686_FLAGS },
9103f4f4 445 {"pentium", PROCESSOR_PENTIUM,
40fb9820 446 CPU_I586_FLAGS },
9103f4f4 447 {"pentiumpro",PROCESSOR_PENTIUMPRO,
40fb9820 448 CPU_I686_FLAGS },
9103f4f4 449 {"pentiumii", PROCESSOR_PENTIUMPRO,
40fb9820 450 CPU_P2_FLAGS },
9103f4f4 451 {"pentiumiii",PROCESSOR_PENTIUMPRO,
40fb9820 452 CPU_P3_FLAGS },
9103f4f4 453 {"pentium4", PROCESSOR_PENTIUM4,
40fb9820 454 CPU_P4_FLAGS },
9103f4f4 455 {"prescott", PROCESSOR_NOCONA,
40fb9820 456 CPU_CORE_FLAGS },
9103f4f4 457 {"nocona", PROCESSOR_NOCONA,
40fb9820 458 CPU_NOCONA_FLAGS },
ef05d495 459 {"yonah", PROCESSOR_CORE,
40fb9820 460 CPU_CORE_FLAGS },
ef05d495 461 {"core", PROCESSOR_CORE,
40fb9820 462 CPU_CORE_FLAGS },
ef05d495 463 {"merom", PROCESSOR_CORE2,
40fb9820 464 CPU_CORE2_FLAGS },
ef05d495 465 {"core2", PROCESSOR_CORE2,
40fb9820 466 CPU_CORE2_FLAGS },
9103f4f4 467 {"k6", PROCESSOR_K6,
40fb9820 468 CPU_K6_FLAGS },
9103f4f4 469 {"k6_2", PROCESSOR_K6,
40fb9820 470 CPU_K6_2_FLAGS },
9103f4f4 471 {"athlon", PROCESSOR_ATHLON,
40fb9820 472 CPU_ATHLON_FLAGS },
9103f4f4 473 {"sledgehammer", PROCESSOR_K8,
40fb9820 474 CPU_K8_FLAGS },
9103f4f4 475 {"opteron", PROCESSOR_K8,
40fb9820 476 CPU_K8_FLAGS },
9103f4f4 477 {"k8", PROCESSOR_K8,
40fb9820 478 CPU_K8_FLAGS },
050dfa73 479 {"amdfam10", PROCESSOR_AMDFAM10,
40fb9820 480 CPU_AMDFAM10_FLAGS },
9103f4f4 481 {".mmx", PROCESSOR_UNKNOWN,
40fb9820 482 CPU_MMX_FLAGS },
9103f4f4 483 {".sse", PROCESSOR_UNKNOWN,
40fb9820 484 CPU_SSE_FLAGS },
9103f4f4 485 {".sse2", PROCESSOR_UNKNOWN,
40fb9820 486 CPU_SSE2_FLAGS },
9103f4f4 487 {".sse3", PROCESSOR_UNKNOWN,
40fb9820 488 CPU_SSE3_FLAGS },
ef05d495 489 {".ssse3", PROCESSOR_UNKNOWN,
40fb9820 490 CPU_SSSE3_FLAGS },
42903f7f 491 {".sse4.1", PROCESSOR_UNKNOWN,
40fb9820 492 CPU_SSE4_1_FLAGS },
381d071f 493 {".sse4.2", PROCESSOR_UNKNOWN,
40fb9820 494 CPU_SSE4_2_FLAGS },
381d071f 495 {".sse4", PROCESSOR_UNKNOWN,
40fb9820 496 CPU_SSE4_2_FLAGS },
9103f4f4 497 {".3dnow", PROCESSOR_UNKNOWN,
40fb9820 498 CPU_3DNOW_FLAGS },
9103f4f4 499 {".3dnowa", PROCESSOR_UNKNOWN,
40fb9820 500 CPU_3DNOWA_FLAGS },
9103f4f4 501 {".padlock", PROCESSOR_UNKNOWN,
40fb9820 502 CPU_PADLOCK_FLAGS },
9103f4f4 503 {".pacifica", PROCESSOR_UNKNOWN,
40fb9820 504 CPU_SVME_FLAGS },
9103f4f4 505 {".svme", PROCESSOR_UNKNOWN,
40fb9820 506 CPU_SVME_FLAGS },
050dfa73 507 {".sse4a", PROCESSOR_UNKNOWN,
40fb9820 508 CPU_SSE4A_FLAGS },
050dfa73 509 {".abm", PROCESSOR_UNKNOWN,
40fb9820 510 CPU_ABM_FLAGS },
e413e4e9
AM		 511};
512
29b0f896
AM		 513const pseudo_typeS md_pseudo_table[] =
514{
515#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
516 {"align", s_align_bytes, 0},
517#else
518 {"align", s_align_ptwo, 0},
519#endif
520 {"arch", set_cpu_arch, 0},
521#ifndef I386COFF
522 {"bss", s_bss, 0},
523#endif
524 {"ffloat", float_cons, 'f'},
525 {"dfloat", float_cons, 'd'},
526 {"tfloat", float_cons, 'x'},
527 {"value", cons, 2},
d182319b 528 {"slong", signed_cons, 4},
29b0f896
AM		 529 {"noopt", s_ignore, 0},
530 {"optim", s_ignore, 0},
531 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
532 {"code16", set_code_flag, CODE_16BIT},
533 {"code32", set_code_flag, CODE_32BIT},
534 {"code64", set_code_flag, CODE_64BIT},
535 {"intel_syntax", set_intel_syntax, 1},
536 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 537#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
538 {"largecomm", handle_large_common, 0},
07a53e5c 539#else
e3bb37b5 540 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 541 {"loc", dwarf2_directive_loc, 0},
542 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 543#endif
6482c264
NC		 544#ifdef TE_PE
545 {"secrel32", pe_directive_secrel, 0},
546#endif
29b0f896
AM		 547 {0, 0, 0}
548};
549
550/* For interface with expression (). */
551extern char *input_line_pointer;
552
553/* Hash table for instruction mnemonic lookup. */
554static struct hash_control *op_hash;
555
556/* Hash table for register lookup. */
557static struct hash_control *reg_hash;
558\f
252b5132 559void
e3bb37b5 560i386_align_code (fragS *fragP, int count)
252b5132 561{
ce8a8b2f
AM		 562 /* Various efficient no-op patterns for aligning code labels.
563 Note: Don't try to assemble the instructions in the comments.
564 0L and 0w are not legal. */
252b5132
RH		 565 static const char f32_1[] =
566 {0x90}; /* nop */
567 static const char f32_2[] =
ccc9c027 568 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 569 static const char f32_3[] =
570 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
571 static const char f32_4[] =
572 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
573 static const char f32_5[] =
574 {0x90, /* nop */
575 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
576 static const char f32_6[] =
577 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
578 static const char f32_7[] =
579 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
580 static const char f32_8[] =
581 {0x90, /* nop */
582 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
583 static const char f32_9[] =
584 {0x89,0xf6, /* movl %esi,%esi */
585 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
586 static const char f32_10[] =
587 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
588 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
589 static const char f32_11[] =
590 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
591 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
592 static const char f32_12[] =
593 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
594 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
595 static const char f32_13[] =
596 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
597 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
598 static const char f32_14[] =
599 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
600 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 601 static const char f16_3[] =
602 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 603 static const char f16_4[] =
604 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
605 static const char f16_5[] =
606 {0x90, /* nop */
607 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
608 static const char f16_6[] =
609 {0x89,0xf6, /* mov %si,%si */
610 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
611 static const char f16_7[] =
612 {0x8d,0x74,0x00, /* lea 0(%si),%si */
613 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
614 static const char f16_8[] =
615 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
616 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 617 static const char jump_31[] =
618 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
619 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
620 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
621 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 622 static const char *const f32_patt[] = {
623 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 624 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 625 };
626 static const char *const f16_patt[] = {
76bc74dc 627 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 628 };
ccc9c027
L		 629 /* nopl (%[re]ax) */
630 static const char alt_3[] =
631 {0x0f,0x1f,0x00};
632 /* nopl 0(%[re]ax) */
633 static const char alt_4[] =
634 {0x0f,0x1f,0x40,0x00};
635 /* nopl 0(%[re]ax,%[re]ax,1) */
636 static const char alt_5[] =
637 {0x0f,0x1f,0x44,0x00,0x00};
638 /* nopw 0(%[re]ax,%[re]ax,1) */
639 static const char alt_6[] =
640 {0x66,0x0f,0x1f,0x44,0x00,0x00};
641 /* nopl 0L(%[re]ax) */
642 static const char alt_7[] =
643 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
644 /* nopl 0L(%[re]ax,%[re]ax,1) */
645 static const char alt_8[] =
646 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
647 /* nopw 0L(%[re]ax,%[re]ax,1) */
648 static const char alt_9[] =
649 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
650 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
651 static const char alt_10[] =
652 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
653 /* data16
654 nopw %cs:0L(%[re]ax,%[re]ax,1) */
655 static const char alt_long_11[] =
656 {0x66,
657 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
658 /* data16
659 data16
660 nopw %cs:0L(%[re]ax,%[re]ax,1) */
661 static const char alt_long_12[] =
662 {0x66,
663 0x66,
664 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
665 /* data16
666 data16
667 data16
668 nopw %cs:0L(%[re]ax,%[re]ax,1) */
669 static const char alt_long_13[] =
670 {0x66,
671 0x66,
672 0x66,
673 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
674 /* data16
675 data16
676 data16
677 data16
678 nopw %cs:0L(%[re]ax,%[re]ax,1) */
679 static const char alt_long_14[] =
680 {0x66,
681 0x66,
682 0x66,
683 0x66,
684 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
685 /* data16
686 data16
687 data16
688 data16
689 data16
690 nopw %cs:0L(%[re]ax,%[re]ax,1) */
691 static const char alt_long_15[] =
692 {0x66,
693 0x66,
694 0x66,
695 0x66,
696 0x66,
697 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
698 /* nopl 0(%[re]ax,%[re]ax,1)
699 nopw 0(%[re]ax,%[re]ax,1) */
700 static const char alt_short_11[] =
701 {0x0f,0x1f,0x44,0x00,0x00,
702 0x66,0x0f,0x1f,0x44,0x00,0x00};
703 /* nopw 0(%[re]ax,%[re]ax,1)
704 nopw 0(%[re]ax,%[re]ax,1) */
705 static const char alt_short_12[] =
706 {0x66,0x0f,0x1f,0x44,0x00,0x00,
707 0x66,0x0f,0x1f,0x44,0x00,0x00};
708 /* nopw 0(%[re]ax,%[re]ax,1)
709 nopl 0L(%[re]ax) */
710 static const char alt_short_13[] =
711 {0x66,0x0f,0x1f,0x44,0x00,0x00,
712 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
713 /* nopl 0L(%[re]ax)
714 nopl 0L(%[re]ax) */
715 static const char alt_short_14[] =
716 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
717 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
718 /* nopl 0L(%[re]ax)
719 nopl 0L(%[re]ax,%[re]ax,1) */
720 static const char alt_short_15[] =
721 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
722 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
723 static const char *const alt_short_patt[] = {
724 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
725 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
726 alt_short_14, alt_short_15
727 };
728 static const char *const alt_long_patt[] = {
729 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
730 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
731 alt_long_14, alt_long_15
732 };
252b5132 733
76bc74dc
L		 734 /* Only align for at least a positive non-zero boundary. */
735 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 736 return;
3e73aa7c 737
ccc9c027
L		 738 /* We need to decide which NOP sequence to use for 32bit and
739 64bit. When -mtune= is used:
4eed87de 740
76bc74dc
L		 741 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
742 PROCESSOR_GENERIC32, f32_patt will be used.
743 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
744 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
745 alt_long_patt will be used.
746 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
747 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 748
76bc74dc
L		 749 When -mtune= isn't used, alt_long_patt will be used if
750 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
751 be used.
ccc9c027
L		 752
753 When -march= or .arch is used, we can't use anything beyond
754 cpu_arch_isa_flags. */
755
756 if (flag_code == CODE_16BIT)
757 {
ccc9c027 758 if (count > 8)
33fef721 759 {
76bc74dc
L		 760 memcpy (fragP->fr_literal + fragP->fr_fix,
761 jump_31, count);
762 /* Adjust jump offset. */
763 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 764 }
76bc74dc
L		 765 else
766 memcpy (fragP->fr_literal + fragP->fr_fix,
767 f16_patt[count - 1], count);
252b5132 768 }
33fef721 769 else
ccc9c027
L		 770 {
771 const char *const *patt = NULL;
772
773 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
774 {
775 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
776 switch (cpu_arch_tune)
777 {
778 case PROCESSOR_UNKNOWN:
779 /* We use cpu_arch_isa_flags to check if we SHOULD
780 optimize for Cpu686. */
40fb9820 781 if (cpu_arch_isa_flags.bitfield.cpui686)
76bc74dc 782 patt = alt_long_patt;
ccc9c027
L		 783 else
784 patt = f32_patt;
785 break;
ccc9c027
L		 786 case PROCESSOR_PENTIUMPRO:
787 case PROCESSOR_PENTIUM4:
788 case PROCESSOR_NOCONA:
ef05d495 789 case PROCESSOR_CORE:
76bc74dc
L		 790 case PROCESSOR_CORE2:
791 case PROCESSOR_GENERIC64:
792 patt = alt_long_patt;
793 break;
ccc9c027
L		 794 case PROCESSOR_K6:
795 case PROCESSOR_ATHLON:
796 case PROCESSOR_K8:
4eed87de 797 case PROCESSOR_AMDFAM10:
ccc9c027
L		 798 patt = alt_short_patt;
799 break;
76bc74dc 800 case PROCESSOR_I386:
ccc9c027
L		 801 case PROCESSOR_I486:
802 case PROCESSOR_PENTIUM:
803 case PROCESSOR_GENERIC32:
804 patt = f32_patt;
805 break;
4eed87de 806 }
ccc9c027
L		 807 }
808 else
809 {
810 switch (cpu_arch_tune)
811 {
812 case PROCESSOR_UNKNOWN:
813 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
814 PROCESSOR_UNKNOWN. */
815 abort ();
816 break;
817
76bc74dc 818 case PROCESSOR_I386:
ccc9c027
L		 819 case PROCESSOR_I486:
820 case PROCESSOR_PENTIUM:
ccc9c027
L		 821 case PROCESSOR_K6:
822 case PROCESSOR_ATHLON:
823 case PROCESSOR_K8:
4eed87de 824 case PROCESSOR_AMDFAM10:
ccc9c027
L		 825 case PROCESSOR_GENERIC32:
826 /* We use cpu_arch_isa_flags to check if we CAN optimize
827 for Cpu686. */
40fb9820 828 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 829 patt = alt_short_patt;
830 else
831 patt = f32_patt;
832 break;
76bc74dc
L		 833 case PROCESSOR_PENTIUMPRO:
834 case PROCESSOR_PENTIUM4:
835 case PROCESSOR_NOCONA:
836 case PROCESSOR_CORE:
ef05d495 837 case PROCESSOR_CORE2:
40fb9820 838 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 839 patt = alt_long_patt;
840 else
841 patt = f32_patt;
842 break;
843 case PROCESSOR_GENERIC64:
76bc74dc 844 patt = alt_long_patt;
ccc9c027 845 break;
4eed87de 846 }
ccc9c027
L		 847 }
848
76bc74dc
L		 849 if (patt == f32_patt)
850 {
851 /* If the padding is less than 15 bytes, we use the normal
852 ones. Otherwise, we use a jump instruction and adjust
853 its offset. */
854 if (count < 15)
855 memcpy (fragP->fr_literal + fragP->fr_fix,
856 patt[count - 1], count);
857 else
858 {
859 memcpy (fragP->fr_literal + fragP->fr_fix,
860 jump_31, count);
861 /* Adjust jump offset. */
862 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
863 }
864 }
865 else
866 {
867 /* Maximum length of an instruction is 15 byte. If the
868 padding is greater than 15 bytes and we don't use jump,
869 we have to break it into smaller pieces. */
870 int padding = count;
871 while (padding > 15)
872 {
873 padding -= 15;
874 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
875 patt [14], 15);
876 }
877
878 if (padding)
879 memcpy (fragP->fr_literal + fragP->fr_fix,
880 patt [padding - 1], padding);
881 }
ccc9c027 882 }
33fef721 883 fragP->fr_var = count;
252b5132
RH		 884}
885
40fb9820
L		 886static int
887cpu_flags_check_x64 (i386_cpu_flags f)
888{
889 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
890 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
891}
892
893static int
894cpu_flags_all_zero (i386_cpu_flags f)
895{
896 unsigned int j;
897
898 for (j = 0; j < ARRAY_SIZE (f.array); j++)
899 if (f.array [j])
900 return 0;
901
902 return 1;
903}
904
905static i386_cpu_flags
906cpu_flags_not (i386_cpu_flags x)
907{
908 unsigned int j;
909
910 for (j = 0; j < ARRAY_SIZE (x.array); j++)
911 x.array [j] = ~x.array [j];
912
913#ifdef CpuUnused
914 x.bitfield.unused = 0;
915#endif
916
917 return x;
918}
919
920enum i386_array_biop
921{
922 and,
923 or,
924 xor
925};
926
927static i386_cpu_flags
928cpu_flags_biop (i386_cpu_flags x, i386_cpu_flags y,
929 enum i386_array_biop op)
930{
931 unsigned int j;
932
933 switch (op)
934 {
935 case and:
936 for (j = 0; j < ARRAY_SIZE (x.array); j++)
937 x.array [j] &= y.array [j];
938 break;
939 case or:
940 for (j = 0; j < ARRAY_SIZE (x.array); j++)
941 x.array [j] |= y.array [j];
942 break;
943 case xor:
944 for (j = 0; j < ARRAY_SIZE (x.array); j++)
945 x.array [j] ^= y.array [j];
946 break;
947 default:
948 abort ();
949 }
950
951 return x;
952}
953
954static int
955cpu_flags_match (i386_cpu_flags x)
956{
957 i386_cpu_flags not = cpu_arch_flags_not;
958
959 not.bitfield.cpu64 = 1;
960 not.bitfield.cpuno64 = 1;
961
962 x.bitfield.cpu64 = 0;
963 x.bitfield.cpuno64 = 0;
964
965 return cpu_flags_all_zero (cpu_flags_biop (x, not, and));
966}
967
968static int
969operand_type_all_zero (i386_operand_type t)
970{
971 unsigned int j;
972
973 for (j = 0; j < ARRAY_SIZE (t.array); j++)
974 if (t.array [j])
975 return 0;
976
977 return 1;
978}
979
980static i386_operand_type
981operand_type_biop (i386_operand_type x, i386_operand_type y,
982 enum i386_array_biop op)
983{
984 unsigned int j;
985
986 switch (op)
987 {
988 case and:
989 for (j = 0; j < ARRAY_SIZE (x.array); j++)
990 x.array [j] &= y.array [j];
991 break;
992 case or:
993 for (j = 0; j < ARRAY_SIZE (x.array); j++)
994 x.array [j] |= y.array [j];
995 break;
996 case xor:
997 for (j = 0; j < ARRAY_SIZE (x.array); j++)
998 x.array [j] ^= y.array [j];
999 break;
1000 default:
1001 abort ();
1002 }
1003
1004 return x;
1005}
1006
1007static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1008static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1009static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1010static const i386_operand_type reg16_inoutportreg
1011 = OPERAND_TYPE_REG16_INOUTPORTREG;
1012static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1013static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1014static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1015static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1016static const i386_operand_type anydisp
1017 = OPERAND_TYPE_ANYDISP;
1018static const i386_operand_type baseindex = OPERAND_TYPE_BASEINDEX;
1019static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1020static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1021static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1022static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1023static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1024static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1025static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1026static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1027static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1028static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1029
1030enum operand_type
1031{
1032 reg,
1033 implicitregister,
1034 imm,
1035 disp,
1036 anymem
1037};
1038
1039static int
1040operand_type_check (i386_operand_type t, enum operand_type c)
1041{
1042 switch (c)
1043 {
1044 case reg:
1045 return (t.bitfield.reg8
1046 || t.bitfield.reg16
1047 || t.bitfield.reg32
1048 || t.bitfield.reg64);
1049
1050 case implicitregister:
1051 return (t.bitfield.inoutportreg
1052 || t.bitfield.shiftcount
1053 || t.bitfield.acc
1054 || t.bitfield.floatacc);
1055
1056 case imm:
1057 return (t.bitfield.imm8
1058 || t.bitfield.imm8s
1059 || t.bitfield.imm16
1060 || t.bitfield.imm32
1061 || t.bitfield.imm32s
1062 || t.bitfield.imm64);
1063
1064 case disp:
1065 return (t.bitfield.disp8
1066 || t.bitfield.disp16
1067 || t.bitfield.disp32
1068 || t.bitfield.disp32s
1069 || t.bitfield.disp64);
1070
1071 case anymem:
1072 return (t.bitfield.disp8
1073 || t.bitfield.disp16
1074 || t.bitfield.disp32
1075 || t.bitfield.disp32s
1076 || t.bitfield.disp64
1077 || t.bitfield.baseindex);
1078
1079 default:
1080 abort ();
1081 }
1082}
1083
1084static int
1085operand_type_match (i386_operand_type overlap,
1086 i386_operand_type given)
1087{
1088 i386_operand_type temp = overlap;
1089
1090 temp.bitfield.jumpabsolute = 0;
1091 if (operand_type_all_zero (temp))
1092 return 0;
1093
1094 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1095 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1096}
1097
1098/* If given types r0 and r1 are registers they must be of the same type
1099 unless the expected operand type register overlap is null.
1100 Note that Acc in a template matches every size of reg. */
1101
1102static int
1103operand_type_register_match (i386_operand_type m0,
1104 i386_operand_type g0,
1105 i386_operand_type t0,
1106 i386_operand_type m1,
1107 i386_operand_type g1,
1108 i386_operand_type t1)
1109{
1110 if (!operand_type_check (g0, reg))
1111 return 1;
1112
1113 if (!operand_type_check (g1, reg))
1114 return 1;
1115
1116 if (g0.bitfield.reg8 == g1.bitfield.reg8
1117 && g0.bitfield.reg16 == g1.bitfield.reg16
1118 && g0.bitfield.reg32 == g1.bitfield.reg32
1119 && g0.bitfield.reg64 == g1.bitfield.reg64)
1120 return 1;
1121
1122 if (m0.bitfield.acc)
1123 {
1124 t0.bitfield.reg8 = 1;
1125 t0.bitfield.reg16 = 1;
1126 t0.bitfield.reg32 = 1;
1127 t0.bitfield.reg64 = 1;
1128 }
1129
1130 if (m1.bitfield.acc)
1131 {
1132 t1.bitfield.reg8 = 1;
1133 t1.bitfield.reg16 = 1;
1134 t1.bitfield.reg32 = 1;
1135 t1.bitfield.reg64 = 1;
1136 }
1137
1138 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1139 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1140 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1141 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1142}
1143
252b5132 1144static INLINE unsigned int
40fb9820 1145mode_from_disp_size (i386_operand_type t)
252b5132 1146{
40fb9820
L		 1147 if (t.bitfield.disp8)
1148 return 1;
1149 else if (t.bitfield.disp16
1150 || t.bitfield.disp32
1151 || t.bitfield.disp32s)
1152 return 2;
1153 else
1154 return 0;
252b5132
RH		 1155}
1156
1157static INLINE int
e3bb37b5 1158fits_in_signed_byte (offsetT num)
252b5132
RH		 1159{
1160 return (num >= -128) && (num <= 127);
47926f60 1161}
252b5132
RH		 1162
1163static INLINE int
e3bb37b5 1164fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1165{
1166 return (num & 0xff) == num;
47926f60 1167}
252b5132
RH		 1168
1169static INLINE int
e3bb37b5 1170fits_in_unsigned_word (offsetT num)
252b5132
RH		 1171{
1172 return (num & 0xffff) == num;
47926f60 1173}
252b5132
RH		 1174
1175static INLINE int
e3bb37b5 1176fits_in_signed_word (offsetT num)
252b5132
RH		 1177{
1178 return (-32768 <= num) && (num <= 32767);
47926f60 1179}
2a962e6d 1180
3e73aa7c 1181static INLINE int
e3bb37b5 1182fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1183{
1184#ifndef BFD64
1185 return 1;
1186#else
1187 return (!(((offsetT) -1 << 31) & num)
1188 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1189#endif
1190} /* fits_in_signed_long() */
2a962e6d 1191
3e73aa7c 1192static INLINE int
e3bb37b5 1193fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1194{
1195#ifndef BFD64
1196 return 1;
1197#else
1198 return (num & (((offsetT) 2 << 31) - 1)) == num;
1199#endif
1200} /* fits_in_unsigned_long() */
252b5132 1201
40fb9820 1202static i386_operand_type
e3bb37b5 1203smallest_imm_type (offsetT num)
252b5132 1204{
40fb9820
L		 1205 i386_operand_type t;
1206
1207 memset (&t, 0, sizeof (t));
1208 t.bitfield.imm64 = 1;
1209
1210 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1211 {
1212 /* This code is disabled on the 486 because all the Imm1 forms
1213 in the opcode table are slower on the i486. They're the
1214 versions with the implicitly specified single-position
1215 displacement, which has another syntax if you really want to
1216 use that form. */
40fb9820
L		 1217 t.bitfield.imm1 = 1;
1218 t.bitfield.imm8 = 1;
1219 t.bitfield.imm8s = 1;
1220 t.bitfield.imm16 = 1;
1221 t.bitfield.imm32 = 1;
1222 t.bitfield.imm32s = 1;
1223 }
1224 else if (fits_in_signed_byte (num))
1225 {
1226 t.bitfield.imm8 = 1;
1227 t.bitfield.imm8s = 1;
1228 t.bitfield.imm16 = 1;
1229 t.bitfield.imm32 = 1;
1230 t.bitfield.imm32s = 1;
1231 }
1232 else if (fits_in_unsigned_byte (num))
1233 {
1234 t.bitfield.imm8 = 1;
1235 t.bitfield.imm16 = 1;
1236 t.bitfield.imm32 = 1;
1237 t.bitfield.imm32s = 1;
1238 }
1239 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1240 {
1241 t.bitfield.imm16 = 1;
1242 t.bitfield.imm32 = 1;
1243 t.bitfield.imm32s = 1;
1244 }
1245 else if (fits_in_signed_long (num))
1246 {
1247 t.bitfield.imm32 = 1;
1248 t.bitfield.imm32s = 1;
1249 }
1250 else if (fits_in_unsigned_long (num))
1251 t.bitfield.imm32 = 1;
1252
1253 return t;
47926f60 1254}
252b5132 1255
847f7ad4 1256static offsetT
e3bb37b5 1257offset_in_range (offsetT val, int size)
847f7ad4 1258{
508866be 1259 addressT mask;
ba2adb93 1260
847f7ad4
AM		 1261 switch (size)
1262 {
508866be
L		 1263 case 1: mask = ((addressT) 1 << 8) - 1; break;
1264 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1265 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1266#ifdef BFD64
1267 case 8: mask = ((addressT) 2 << 63) - 1; break;
1268#endif
47926f60 1269 default: abort ();
847f7ad4
AM		 1270 }
1271
ba2adb93 1272 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1273 if (!use_rela_relocations)
1274 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1275 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1276
47926f60 1277 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1278 {
1279 char buf1[40], buf2[40];
1280
1281 sprint_value (buf1, val);
1282 sprint_value (buf2, val & mask);
1283 as_warn (_("%s shortened to %s"), buf1, buf2);
1284 }
1285 return val & mask;
1286}
1287
252b5132
RH		 1288/* Returns 0 if attempting to add a prefix where one from the same
1289 class already exists, 1 if non rep/repne added, 2 if rep/repne
1290 added. */
1291static int
e3bb37b5 1292add_prefix (unsigned int prefix)
252b5132
RH		 1293{
1294 int ret = 1;
b1905489 1295 unsigned int q;
252b5132 1296
29b0f896
AM		 1297 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1298 && flag_code == CODE_64BIT)
b1905489 1299 {
161a04f6
L		 1300 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1301 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1302 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1303 ret = 0;
1304 q = REX_PREFIX;
1305 }
3e73aa7c 1306 else
b1905489
JB		 1307 {
1308 switch (prefix)
1309 {
1310 default:
1311 abort ();
1312
1313 case CS_PREFIX_OPCODE:
1314 case DS_PREFIX_OPCODE:
1315 case ES_PREFIX_OPCODE:
1316 case FS_PREFIX_OPCODE:
1317 case GS_PREFIX_OPCODE:
1318 case SS_PREFIX_OPCODE:
1319 q = SEG_PREFIX;
1320 break;
1321
1322 case REPNE_PREFIX_OPCODE:
1323 case REPE_PREFIX_OPCODE:
1324 ret = 2;
1325 /* fall thru */
1326 case LOCK_PREFIX_OPCODE:
1327 q = LOCKREP_PREFIX;
1328 break;
1329
1330 case FWAIT_OPCODE:
1331 q = WAIT_PREFIX;
1332 break;
1333
1334 case ADDR_PREFIX_OPCODE:
1335 q = ADDR_PREFIX;
1336 break;
1337
1338 case DATA_PREFIX_OPCODE:
1339 q = DATA_PREFIX;
1340 break;
1341 }
1342 if (i.prefix[q] != 0)
1343 ret = 0;
1344 }
252b5132 1345
b1905489 1346 if (ret)
252b5132 1347 {
b1905489
JB		 1348 if (!i.prefix[q])
1349 ++i.prefixes;
1350 i.prefix[q] |= prefix;
252b5132 1351 }
b1905489
JB		 1352 else
1353 as_bad (_("same type of prefix used twice"));
252b5132 1354
252b5132
RH		 1355 return ret;
1356}
1357
1358static void
e3bb37b5 1359set_code_flag (int value)
eecb386c 1360{
3e73aa7c 1361 flag_code = value;
40fb9820
L		 1362 if (flag_code == CODE_64BIT)
1363 {
1364 cpu_arch_flags.bitfield.cpu64 = 1;
1365 cpu_arch_flags.bitfield.cpuno64 = 0;
1366 cpu_arch_flags_not.bitfield.cpu64 = 0;
1367 cpu_arch_flags_not.bitfield.cpuno64 = 1;
1368 }
1369 else
1370 {
1371 cpu_arch_flags.bitfield.cpu64 = 0;
1372 cpu_arch_flags.bitfield.cpuno64 = 1;
1373 cpu_arch_flags_not.bitfield.cpu64 = 1;
1374 cpu_arch_flags_not.bitfield.cpuno64 = 0;
1375 }
1376 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1377 {
1378 as_bad (_("64bit mode not supported on this CPU."));
1379 }
40fb9820 1380 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1381 {
1382 as_bad (_("32bit mode not supported on this CPU."));
1383 }
eecb386c
AM		 1384 stackop_size = '\0';
1385}
1386
1387static void
e3bb37b5 1388set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1389{
3e73aa7c 1390 flag_code = new_code_flag;
40fb9820
L		 1391 if (flag_code != CODE_16BIT)
1392 abort ();
1393 cpu_arch_flags.bitfield.cpu64 = 0;
1394 cpu_arch_flags.bitfield.cpuno64 = 1;
1395 cpu_arch_flags_not.bitfield.cpu64 = 1;
1396 cpu_arch_flags_not.bitfield.cpuno64 = 0;
9306ca4a 1397 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1398}
1399
1400static void
e3bb37b5 1401set_intel_syntax (int syntax_flag)
252b5132
RH		 1402{
1403 /* Find out if register prefixing is specified. */
1404 int ask_naked_reg = 0;
1405
1406 SKIP_WHITESPACE ();
29b0f896 1407 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1408 {
1409 char *string = input_line_pointer;
1410 int e = get_symbol_end ();
1411
47926f60 1412 if (strcmp (string, "prefix") == 0)
252b5132 1413 ask_naked_reg = 1;
47926f60 1414 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1415 ask_naked_reg = -1;
1416 else
d0b47220 1417 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1418 *input_line_pointer = e;
1419 }
1420 demand_empty_rest_of_line ();
c3332e24 1421
252b5132
RH		 1422 intel_syntax = syntax_flag;
1423
1424 if (ask_naked_reg == 0)
f86103b7
AM		 1425 allow_naked_reg = (intel_syntax
1426 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1427 else
1428 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1429
e4a3b5a4 1430 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1431 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1432 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1433}
1434
e413e4e9 1435static void
e3bb37b5 1436set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1437{
47926f60 1438 SKIP_WHITESPACE ();
e413e4e9 1439
29b0f896 1440 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1441 {
1442 char *string = input_line_pointer;
1443 int e = get_symbol_end ();
9103f4f4 1444 unsigned int i;
40fb9820 1445 i386_cpu_flags flags;
e413e4e9 1446
9103f4f4 1447 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1448 {
1449 if (strcmp (string, cpu_arch[i].name) == 0)
1450 {
5c6af06e
JB		 1451 if (*string != '.')
1452 {
1453 cpu_arch_name = cpu_arch[i].name;
1454 cpu_sub_arch_name = NULL;
40fb9820
L		 1455 cpu_arch_flags = cpu_arch[i].flags;
1456 if (flag_code == CODE_64BIT)
1457 {
1458 cpu_arch_flags.bitfield.cpu64 = 1;
1459 cpu_arch_flags.bitfield.cpuno64 = 0;
1460 }
1461 else
1462 {
1463 cpu_arch_flags.bitfield.cpu64 = 0;
1464 cpu_arch_flags.bitfield.cpuno64 = 1;
1465 }
1466 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
ccc9c027 1467 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1468 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1469 if (!cpu_arch_tune_set)
1470 {
1471 cpu_arch_tune = cpu_arch_isa;
1472 cpu_arch_tune_flags = cpu_arch_isa_flags;
1473 }
5c6af06e
JB		 1474 break;
1475 }
40fb9820
L		 1476
1477 flags = cpu_flags_biop (cpu_arch_flags,
1478 cpu_arch[i].flags, or);
1479 if (memcmp (&flags, &cpu_arch_flags, sizeof (flags)))
5c6af06e
JB		 1480 {
1481 cpu_sub_arch_name = cpu_arch[i].name;
40fb9820
L		 1482 cpu_arch_flags = flags;
1483 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
5c6af06e
JB		 1484 }
1485 *input_line_pointer = e;
1486 demand_empty_rest_of_line ();
1487 return;
e413e4e9
AM		 1488 }
1489 }
9103f4f4 1490 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1491 as_bad (_("no such architecture: `%s'"), string);
1492
1493 *input_line_pointer = e;
1494 }
1495 else
1496 as_bad (_("missing cpu architecture"));
1497
fddf5b5b
AM		 1498 no_cond_jump_promotion = 0;
1499 if (*input_line_pointer == ','
29b0f896 1500 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1501 {
1502 char *string = ++input_line_pointer;
1503 int e = get_symbol_end ();
1504
1505 if (strcmp (string, "nojumps") == 0)
1506 no_cond_jump_promotion = 1;
1507 else if (strcmp (string, "jumps") == 0)
1508 ;
1509 else
1510 as_bad (_("no such architecture modifier: `%s'"), string);
1511
1512 *input_line_pointer = e;
1513 }
1514
e413e4e9
AM		 1515 demand_empty_rest_of_line ();
1516}
1517
b9d79e03
JH		 1518unsigned long
1519i386_mach ()
1520{
1521 if (!strcmp (default_arch, "x86_64"))
1522 return bfd_mach_x86_64;
1523 else if (!strcmp (default_arch, "i386"))
1524 return bfd_mach_i386_i386;
1525 else
1526 as_fatal (_("Unknown architecture"));
1527}
b9d79e03 1528\f
252b5132
RH		 1529void
1530md_begin ()
1531{
1532 const char *hash_err;
1533
40fb9820
L		 1534 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
1535
47926f60 1536 /* Initialize op_hash hash table. */
252b5132
RH		 1537 op_hash = hash_new ();
1538
1539 {
29b0f896
AM		 1540 const template *optab;
1541 templates *core_optab;
252b5132 1542
47926f60
KH		 1543 /* Setup for loop. */
1544 optab = i386_optab;
252b5132
RH		 1545 core_optab = (templates *) xmalloc (sizeof (templates));
1546 core_optab->start = optab;
1547
1548 while (1)
1549 {
1550 ++optab;
1551 if (optab->name == NULL
1552 || strcmp (optab->name, (optab - 1)->name) != 0)
1553 {
1554 /* different name --> ship out current template list;
47926f60 1555 add to hash table; & begin anew. */
252b5132
RH		 1556 core_optab->end = optab;
1557 hash_err = hash_insert (op_hash,
1558 (optab - 1)->name,
1559 (PTR) core_optab);
1560 if (hash_err)
1561 {
252b5132
RH		 1562 as_fatal (_("Internal Error: Can't hash %s: %s"),
1563 (optab - 1)->name,
1564 hash_err);
1565 }
1566 if (optab->name == NULL)
1567 break;
1568 core_optab = (templates *) xmalloc (sizeof (templates));
1569 core_optab->start = optab;
1570 }
1571 }
1572 }
1573
47926f60 1574 /* Initialize reg_hash hash table. */
252b5132
RH		 1575 reg_hash = hash_new ();
1576 {
29b0f896 1577 const reg_entry *regtab;
c3fe08fa 1578 unsigned int regtab_size = i386_regtab_size;
252b5132 1579
c3fe08fa 1580 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1581 {
1582 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1583 if (hash_err)
3e73aa7c
JH		 1584 as_fatal (_("Internal Error: Can't hash %s: %s"),
1585 regtab->reg_name,
1586 hash_err);
252b5132
RH		 1587 }
1588 }
1589
47926f60 1590 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1591 {
29b0f896
AM		 1592 int c;
1593 char *p;
252b5132
RH		 1594
1595 for (c = 0; c < 256; c++)
1596 {
3882b010 1597 if (ISDIGIT (c))
252b5132
RH		 1598 {
1599 digit_chars[c] = c;
1600 mnemonic_chars[c] = c;
1601 register_chars[c] = c;
1602 operand_chars[c] = c;
1603 }
3882b010 1604 else if (ISLOWER (c))
252b5132
RH		 1605 {
1606 mnemonic_chars[c] = c;
1607 register_chars[c] = c;
1608 operand_chars[c] = c;
1609 }
3882b010 1610 else if (ISUPPER (c))
252b5132 1611 {
3882b010 1612 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1613 register_chars[c] = mnemonic_chars[c];
1614 operand_chars[c] = c;
1615 }
1616
3882b010 1617 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1618 identifier_chars[c] = c;
1619 else if (c >= 128)
1620 {
1621 identifier_chars[c] = c;
1622 operand_chars[c] = c;
1623 }
1624 }
1625
1626#ifdef LEX_AT
1627 identifier_chars['@'] = '@';
32137342
NC		 1628#endif
1629#ifdef LEX_QM
1630 identifier_chars['?'] = '?';
1631 operand_chars['?'] = '?';
252b5132 1632#endif
252b5132 1633 digit_chars['-'] = '-';
791fe849 1634 mnemonic_chars['-'] = '-';
0003779b 1635 mnemonic_chars['.'] = '.';
252b5132
RH		 1636 identifier_chars['_'] = '_';
1637 identifier_chars['.'] = '.';
1638
1639 for (p = operand_special_chars; *p != '\0'; p++)
1640 operand_chars[(unsigned char) *p] = *p;
1641 }
1642
1643#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1644 if (IS_ELF)
252b5132
RH		 1645 {
1646 record_alignment (text_section, 2);
1647 record_alignment (data_section, 2);
1648 record_alignment (bss_section, 2);
1649 }
1650#endif
a4447b93
RH		 1651
1652 if (flag_code == CODE_64BIT)
1653 {
1654 x86_dwarf2_return_column = 16;
1655 x86_cie_data_alignment = -8;
1656 }
1657 else
1658 {
1659 x86_dwarf2_return_column = 8;
1660 x86_cie_data_alignment = -4;
1661 }
252b5132
RH		 1662}
1663
1664void
e3bb37b5 1665i386_print_statistics (FILE *file)
252b5132
RH		 1666{
1667 hash_print_statistics (file, "i386 opcode", op_hash);
1668 hash_print_statistics (file, "i386 register", reg_hash);
1669}
1670\f
252b5132
RH		 1671#ifdef DEBUG386
1672
ce8a8b2f 1673/* Debugging routines for md_assemble. */
e3bb37b5 1674static void pte (template *);
40fb9820 1675static void pt (i386_operand_type);
e3bb37b5
L		 1676static void pe (expressionS *);
1677static void ps (symbolS *);
252b5132
RH		 1678
1679static void
e3bb37b5 1680pi (char *line, i386_insn *x)
252b5132 1681{
09f131f2 1682 unsigned int i;
252b5132
RH		 1683
1684 fprintf (stdout, "%s: template ", line);
1685 pte (&x->tm);
09f131f2
JH		 1686 fprintf (stdout, " address: base %s index %s scale %x\n",
1687 x->base_reg ? x->base_reg->reg_name : "none",
1688 x->index_reg ? x->index_reg->reg_name : "none",
1689 x->log2_scale_factor);
1690 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1691 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1692 fprintf (stdout, " sib: base %x index %x scale %x\n",
1693 x->sib.base, x->sib.index, x->sib.scale);
1694 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 1695 (x->rex & REX_W) != 0,
1696 (x->rex & REX_R) != 0,
1697 (x->rex & REX_X) != 0,
1698 (x->rex & REX_B) != 0);
252b5132
RH		 1699 for (i = 0; i < x->operands; i++)
1700 {
1701 fprintf (stdout, " #%d: ", i + 1);
1702 pt (x->types[i]);
1703 fprintf (stdout, "\n");
40fb9820
L		 1704 if (x->types[i].bitfield.reg8
1705 || x->types[i].bitfield.reg16
1706 || x->types[i].bitfield.reg32
1707 || x->types[i].bitfield.reg64
1708 || x->types[i].bitfield.regmmx
1709 || x->types[i].bitfield.regxmm
1710 || x->types[i].bitfield.sreg2
1711 || x->types[i].bitfield.sreg3
1712 || x->types[i].bitfield.control
1713 || x->types[i].bitfield.debug
1714 || x->types[i].bitfield.test)
520dc8e8 1715 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 1716 if (operand_type_check (x->types[i], imm))
520dc8e8 1717 pe (x->op[i].imms);
40fb9820 1718 if (operand_type_check (x->types[i], disp))
520dc8e8 1719 pe (x->op[i].disps);
252b5132
RH		 1720 }
1721}
1722
1723static void
e3bb37b5 1724pte (template *t)
252b5132 1725{
09f131f2 1726 unsigned int i;
252b5132 1727 fprintf (stdout, " %d operands ", t->operands);
47926f60 1728 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1729 if (t->extension_opcode != None)
1730 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 1731 if (t->opcode_modifier.d)
252b5132 1732 fprintf (stdout, "D");
40fb9820 1733 if (t->opcode_modifier.w)
252b5132
RH		 1734 fprintf (stdout, "W");
1735 fprintf (stdout, "\n");
1736 for (i = 0; i < t->operands; i++)
1737 {
1738 fprintf (stdout, " #%d type ", i + 1);
1739 pt (t->operand_types[i]);
1740 fprintf (stdout, "\n");
1741 }
1742}
1743
1744static void
e3bb37b5 1745pe (expressionS *e)
252b5132 1746{
24eab124 1747 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1748 fprintf (stdout, " add_number %ld (%lx)\n",
1749 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1750 if (e->X_add_symbol)
1751 {
1752 fprintf (stdout, " add_symbol ");
1753 ps (e->X_add_symbol);
1754 fprintf (stdout, "\n");
1755 }
1756 if (e->X_op_symbol)
1757 {
1758 fprintf (stdout, " op_symbol ");
1759 ps (e->X_op_symbol);
1760 fprintf (stdout, "\n");
1761 }
1762}
1763
1764static void
e3bb37b5 1765ps (symbolS *s)
252b5132
RH		 1766{
1767 fprintf (stdout, "%s type %s%s",
1768 S_GET_NAME (s),
1769 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1770 segment_name (S_GET_SEGMENT (s)));
1771}
1772
7b81dfbb 1773static struct type_name
252b5132 1774 {
40fb9820
L		 1775 i386_operand_type mask;
1776 const char *name;
252b5132 1777 }
7b81dfbb 1778const type_names[] =
252b5132 1779{
40fb9820
L		 1780 { OPERAND_TYPE_REG8, "r8" },
1781 { OPERAND_TYPE_REG16, "r16" },
1782 { OPERAND_TYPE_REG32, "r32" },
1783 { OPERAND_TYPE_REG64, "r64" },
1784 { OPERAND_TYPE_IMM8, "i8" },
1785 { OPERAND_TYPE_IMM8, "i8s" },
1786 { OPERAND_TYPE_IMM16, "i16" },
1787 { OPERAND_TYPE_IMM32, "i32" },
1788 { OPERAND_TYPE_IMM32S, "i32s" },
1789 { OPERAND_TYPE_IMM64, "i64" },
1790 { OPERAND_TYPE_IMM1, "i1" },
1791 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
1792 { OPERAND_TYPE_DISP8, "d8" },
1793 { OPERAND_TYPE_DISP16, "d16" },
1794 { OPERAND_TYPE_DISP32, "d32" },
1795 { OPERAND_TYPE_DISP32S, "d32s" },
1796 { OPERAND_TYPE_DISP64, "d64" },
1797 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
1798 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
1799 { OPERAND_TYPE_CONTROL, "control reg" },
1800 { OPERAND_TYPE_TEST, "test reg" },
1801 { OPERAND_TYPE_DEBUG, "debug reg" },
1802 { OPERAND_TYPE_FLOATREG, "FReg" },
1803 { OPERAND_TYPE_FLOATACC, "FAcc" },
1804 { OPERAND_TYPE_SREG2, "SReg2" },
1805 { OPERAND_TYPE_SREG3, "SReg3" },
1806 { OPERAND_TYPE_ACC, "Acc" },
1807 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
1808 { OPERAND_TYPE_REGMMX, "rMMX" },
1809 { OPERAND_TYPE_REGXMM, "rXMM" },
1810 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 1811};
1812
1813static void
40fb9820 1814pt (i386_operand_type t)
252b5132 1815{
40fb9820 1816 unsigned int j;
252b5132 1817
40fb9820
L		 1818 for (j = 0; j < ARRAY_SIZE (type_names); j++)
1819 if (!operand_type_all_zero (operand_type_biop (t,
1820 type_names[j].mask,
1821 and)))
1822 fprintf (stdout, "%s, ", type_names[j].name);
252b5132
RH		 1823 fflush (stdout);
1824}
1825
1826#endif /* DEBUG386 */
1827\f
252b5132 1828static bfd_reloc_code_real_type
3956db08 1829reloc (unsigned int size,
64e74474
AM		 1830 int pcrel,
1831 int sign,
1832 bfd_reloc_code_real_type other)
252b5132 1833{
47926f60 1834 if (other != NO_RELOC)
3956db08
JB		 1835 {
1836 reloc_howto_type *reloc;
1837
1838 if (size == 8)
1839 switch (other)
1840 {
64e74474
AM		 1841 case BFD_RELOC_X86_64_GOT32:
1842 return BFD_RELOC_X86_64_GOT64;
1843 break;
1844 case BFD_RELOC_X86_64_PLTOFF64:
1845 return BFD_RELOC_X86_64_PLTOFF64;
1846 break;
1847 case BFD_RELOC_X86_64_GOTPC32:
1848 other = BFD_RELOC_X86_64_GOTPC64;
1849 break;
1850 case BFD_RELOC_X86_64_GOTPCREL:
1851 other = BFD_RELOC_X86_64_GOTPCREL64;
1852 break;
1853 case BFD_RELOC_X86_64_TPOFF32:
1854 other = BFD_RELOC_X86_64_TPOFF64;
1855 break;
1856 case BFD_RELOC_X86_64_DTPOFF32:
1857 other = BFD_RELOC_X86_64_DTPOFF64;
1858 break;
1859 default:
1860 break;
3956db08 1861 }
e05278af
JB		 1862
1863 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1864 if (size == 4 && flag_code != CODE_64BIT)
1865 sign = -1;
1866
3956db08
JB		 1867 reloc = bfd_reloc_type_lookup (stdoutput, other);
1868 if (!reloc)
1869 as_bad (_("unknown relocation (%u)"), other);
1870 else if (size != bfd_get_reloc_size (reloc))
1871 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1872 bfd_get_reloc_size (reloc),
1873 size);
1874 else if (pcrel && !reloc->pc_relative)
1875 as_bad (_("non-pc-relative relocation for pc-relative field"));
1876 else if ((reloc->complain_on_overflow == complain_overflow_signed
1877 && !sign)
1878 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1879 && sign > 0))
3956db08
JB		 1880 as_bad (_("relocated field and relocation type differ in signedness"));
1881 else
1882 return other;
1883 return NO_RELOC;
1884 }
252b5132
RH		 1885
1886 if (pcrel)
1887 {
3e73aa7c 1888 if (!sign)
3956db08 1889 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1890 switch (size)
1891 {
1892 case 1: return BFD_RELOC_8_PCREL;
1893 case 2: return BFD_RELOC_16_PCREL;
1894 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1895 case 8: return BFD_RELOC_64_PCREL;
252b5132 1896 }
3956db08 1897 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1898 }
1899 else
1900 {
3956db08 1901 if (sign > 0)
e5cb08ac 1902 switch (size)
3e73aa7c
JH		 1903 {
1904 case 4: return BFD_RELOC_X86_64_32S;
1905 }
1906 else
1907 switch (size)
1908 {
1909 case 1: return BFD_RELOC_8;
1910 case 2: return BFD_RELOC_16;
1911 case 4: return BFD_RELOC_32;
1912 case 8: return BFD_RELOC_64;
1913 }
3956db08
JB		 1914 as_bad (_("cannot do %s %u byte relocation"),
1915 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1916 }
1917
bfb32b52 1918 abort ();
252b5132
RH		 1919 return BFD_RELOC_NONE;
1920}
1921
47926f60
KH		 1922/* Here we decide which fixups can be adjusted to make them relative to
1923 the beginning of the section instead of the symbol. Basically we need
1924 to make sure that the dynamic relocations are done correctly, so in
1925 some cases we force the original symbol to be used. */
1926
252b5132 1927int
e3bb37b5 1928tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 1929{
6d249963 1930#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1931 if (!IS_ELF)
31312f95
AM		 1932 return 1;
1933
a161fe53
AM		 1934 /* Don't adjust pc-relative references to merge sections in 64-bit
1935 mode. */
1936 if (use_rela_relocations
1937 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1938 && fixP->fx_pcrel)
252b5132 1939 return 0;
31312f95 1940
8d01d9a9
AJ		 1941 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1942 and changed later by validate_fix. */
1943 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1944 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1945 return 0;
1946
ce8a8b2f 1947 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1948 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1949 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1950 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1951 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1952 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1953 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1954 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1955 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1956 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1957 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1958 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1959 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1960 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1961 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1962 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1963 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1964 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1965 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1966 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1967 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1968 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1969 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1970 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1971 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1972 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1973 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1974 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1975 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1976 return 0;
31312f95 1977#endif
252b5132
RH		 1978 return 1;
1979}
252b5132 1980
b4cac588 1981static int
e3bb37b5 1982intel_float_operand (const char *mnemonic)
252b5132 1983{
9306ca4a
JB		 1984 /* Note that the value returned is meaningful only for opcodes with (memory)
1985 operands, hence the code here is free to improperly handle opcodes that
1986 have no operands (for better performance and smaller code). */
1987
1988 if (mnemonic[0] != 'f')
1989 return 0; /* non-math */
1990
1991 switch (mnemonic[1])
1992 {
1993 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1994 the fs segment override prefix not currently handled because no
1995 call path can make opcodes without operands get here */
1996 case 'i':
1997 return 2 /* integer op */;
1998 case 'l':
1999 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2000 return 3; /* fldcw/fldenv */
2001 break;
2002 case 'n':
2003 if (mnemonic[2] != 'o' /* fnop */)
2004 return 3; /* non-waiting control op */
2005 break;
2006 case 'r':
2007 if (mnemonic[2] == 's')
2008 return 3; /* frstor/frstpm */
2009 break;
2010 case 's':
2011 if (mnemonic[2] == 'a')
2012 return 3; /* fsave */
2013 if (mnemonic[2] == 't')
2014 {
2015 switch (mnemonic[3])
2016 {
2017 case 'c': /* fstcw */
2018 case 'd': /* fstdw */
2019 case 'e': /* fstenv */
2020 case 's': /* fsts[gw] */
2021 return 3;
2022 }
2023 }
2024 break;
2025 case 'x':
2026 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2027 return 0; /* fxsave/fxrstor are not really math ops */
2028 break;
2029 }
252b5132 2030
9306ca4a 2031 return 1;
252b5132
RH		 2032}
2033
2034/* This is the guts of the machine-dependent assembler. LINE points to a
2035 machine dependent instruction. This function is supposed to emit
2036 the frags/bytes it assembles to. */
2037
2038void
2039md_assemble (line)
2040 char *line;
2041{
40fb9820 2042 unsigned int j;
252b5132
RH		 2043 char mnemonic[MAX_MNEM_SIZE];
2044
47926f60 2045 /* Initialize globals. */
252b5132
RH		 2046 memset (&i, '\0', sizeof (i));
2047 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2048 i.reloc[j] = NO_RELOC;
252b5132
RH		 2049 memset (disp_expressions, '\0', sizeof (disp_expressions));
2050 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2051 save_stack_p = save_stack;
252b5132
RH		 2052
2053 /* First parse an instruction mnemonic & call i386_operand for the operands.
2054 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2055 start of a (possibly prefixed) mnemonic. */
252b5132 2056
29b0f896
AM		 2057 line = parse_insn (line, mnemonic);
2058 if (line == NULL)
2059 return;
252b5132 2060
29b0f896
AM		 2061 line = parse_operands (line, mnemonic);
2062 if (line == NULL)
2063 return;
252b5132 2064
4eed87de 2065 /* The order of the immediates should be reversed
050dfa73 2066 for 2 immediates extrq and insertq instructions */
4d456e3d
L		 2067 if ((i.imm_operands == 2)
2068 && ((strcmp (mnemonic, "extrq") == 0)
2069 || (strcmp (mnemonic, "insertq") == 0)))
050dfa73 2070 {
4eed87de
AM		 2071 swap_2_operands (0, 1);
2072 /* "extrq" and insertq" are the only two instructions whose operands
050dfa73
MM		 2073 have to be reversed even though they have two immediate operands.
2074 */
2075 if (intel_syntax)
2076 swap_operands ();
2077 }
2078
29b0f896
AM		 2079 /* Now we've parsed the mnemonic into a set of templates, and have the
2080 operands at hand. */
2081
2082 /* All intel opcodes have reversed operands except for "bound" and
2083 "enter". We also don't reverse intersegment "jmp" and "call"
2084 instructions with 2 immediate operands so that the immediate segment
050dfa73 2085 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2086 if (intel_syntax
2087 && i.operands > 1
29b0f896 2088 && (strcmp (mnemonic, "bound") != 0)
30123838 2089 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2090 && !(operand_type_check (i.types[0], imm)
2091 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2092 swap_operands ();
2093
2094 if (i.imm_operands)
2095 optimize_imm ();
2096
b300c311
L		 2097 /* Don't optimize displacement for movabs since it only takes 64bit
2098 displacement. */
2099 if (i.disp_operands
2100 && (flag_code != CODE_64BIT
2101 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2102 optimize_disp ();
2103
2104 /* Next, we find a template that matches the given insn,
2105 making sure the overlap of the given operands types is consistent
2106 with the template operand types. */
252b5132 2107
29b0f896
AM		 2108 if (!match_template ())
2109 return;
252b5132 2110
cd61ebfe
AM		 2111 if (intel_syntax)
2112 {
2113 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
2114 if (SYSV386_COMPAT
2115 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
8a2ed489 2116 i.tm.base_opcode ^= Opcode_FloatR;
cd61ebfe
AM		 2117
2118 /* Zap movzx and movsx suffix. The suffix may have been set from
2119 "word ptr" or "byte ptr" on the source operand, but we'll use
2120 the suffix later to choose the destination register. */
2121 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 2122 {
2123 if (i.reg_operands < 2
2124 && !i.suffix
40fb9820
L		 2125 && (!i.tm.opcode_modifier.no_bsuf
2126 || !i.tm.opcode_modifier.no_wsuf
2127 || !i.tm.opcode_modifier.no_lsuf
2128 || !i.tm.opcode_modifier.no_ssuf
2129 || !i.tm.opcode_modifier.no_xsuf
2130 || !i.tm.opcode_modifier.no_qsuf))
9306ca4a
JB		 2131 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2132
2133 i.suffix = 0;
2134 }
cd61ebfe 2135 }
24eab124 2136
40fb9820 2137 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2138 if (!add_prefix (FWAIT_OPCODE))
2139 return;
252b5132 2140
29b0f896 2141 /* Check string instruction segment overrides. */
40fb9820 2142 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2143 {
2144 if (!check_string ())
5dd0794d 2145 return;
29b0f896 2146 }
5dd0794d 2147
29b0f896
AM		 2148 if (!process_suffix ())
2149 return;
e413e4e9 2150
29b0f896
AM		 2151 /* Make still unresolved immediate matches conform to size of immediate
2152 given in i.suffix. */
2153 if (!finalize_imm ())
2154 return;
252b5132 2155
40fb9820 2156 if (i.types[0].bitfield.imm1)
29b0f896 2157 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2158
40fb9820
L		 2159 for (j = 0; j < 3; j++)
2160 if (operand_type_check (i.types[j], implicitregister))
2161 i.reg_operands--;
2162
2163 if (i.tm.opcode_modifier.immext)
29b0f896 2164 {
02fc3089
L		 2165 expressionS *exp;
2166
40fb9820 2167 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
ca164297 2168 {
b7d9ef37 2169 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 2170 operands with an opcode suffix which is coded in the same
2171 place as an 8-bit immediate field would be. Here we check
2172 those operands and remove them afterwards. */
2173 unsigned int x;
2174
a4622f40 2175 for (x = 0; x < i.operands; x++)
ca164297 2176 if (i.op[x].regs->reg_num != x)
a540244d
L		 2177 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2178 register_prefix,
2179 i.op[x].regs->reg_name,
2180 x + 1,
2181 i.tm.name);
ca164297
L		 2182 i.operands = 0;
2183 }
2184
29b0f896
AM		 2185 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2186 opcode suffix which is coded in the same place as an 8-bit
2187 immediate field would be. Here we fake an 8-bit immediate
2188 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 2189
29b0f896 2190 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 2191
29b0f896
AM		 2192 exp = &im_expressions[i.imm_operands++];
2193 i.op[i.operands].imms = exp;
40fb9820
L		 2194 memset (&i.types[i.operands], 0, sizeof (i.types[i.operands]));
2195 i.types[i.operands].bitfield.imm8 = 1;
2196 i.operands++;
29b0f896
AM		 2197 exp->X_op = O_constant;
2198 exp->X_add_number = i.tm.extension_opcode;
2199 i.tm.extension_opcode = None;
2200 }
252b5132 2201
29b0f896
AM		 2202 /* For insns with operands there are more diddles to do to the opcode. */
2203 if (i.operands)
2204 {
2205 if (!process_operands ())
2206 return;
2207 }
40fb9820 2208 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2209 {
2210 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2211 as_warn (_("translating to `%sp'"), i.tm.name);
2212 }
252b5132 2213
29b0f896
AM		 2214 /* Handle conversion of 'int $3' --> special int3 insn. */
2215 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2216 {
2217 i.tm.base_opcode = INT3_OPCODE;
2218 i.imm_operands = 0;
2219 }
252b5132 2220
40fb9820
L		 2221 if ((i.tm.opcode_modifier.jump
2222 || i.tm.opcode_modifier.jumpbyte
2223 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2224 && i.op[0].disps->X_op == O_constant)
2225 {
2226 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2227 the absolute address given by the constant. Since ix86 jumps and
2228 calls are pc relative, we need to generate a reloc. */
2229 i.op[0].disps->X_add_symbol = &abs_symbol;
2230 i.op[0].disps->X_op = O_symbol;
2231 }
252b5132 2232
40fb9820 2233 if (i.tm.opcode_modifier.rex64)
161a04f6 2234 i.rex |= REX_W;
252b5132 2235
29b0f896
AM		 2236 /* For 8 bit registers we need an empty rex prefix. Also if the
2237 instruction already has a prefix, we need to convert old
2238 registers to new ones. */
773f551c 2239
40fb9820 2240 if ((i.types[0].bitfield.reg8
29b0f896 2241 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2242 || (i.types[1].bitfield.reg8
29b0f896 2243 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2244 || ((i.types[0].bitfield.reg8
2245 || i.types[1].bitfield.reg8)
29b0f896
AM		 2246 && i.rex != 0))
2247 {
2248 int x;
726c5dcd 2249
29b0f896
AM		 2250 i.rex |= REX_OPCODE;
2251 for (x = 0; x < 2; x++)
2252 {
2253 /* Look for 8 bit operand that uses old registers. */
40fb9820 2254 if (i.types[x].bitfield.reg8
29b0f896 2255 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2256 {
29b0f896
AM		 2257 /* In case it is "hi" register, give up. */
2258 if (i.op[x].regs->reg_num > 3)
a540244d 2259 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2260 "instruction requiring REX prefix."),
a540244d 2261 register_prefix, i.op[x].regs->reg_name);
773f551c 2262
29b0f896
AM		 2263 /* Otherwise it is equivalent to the extended register.
2264 Since the encoding doesn't change this is merely
2265 cosmetic cleanup for debug output. */
2266
2267 i.op[x].regs = i.op[x].regs + 8;
773f551c 2268 }
29b0f896
AM		 2269 }
2270 }
773f551c 2271
29b0f896
AM		 2272 if (i.rex != 0)
2273 add_prefix (REX_OPCODE | i.rex);
2274
2275 /* We are ready to output the insn. */
2276 output_insn ();
2277}
2278
2279static char *
e3bb37b5 2280parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2281{
2282 char *l = line;
2283 char *token_start = l;
2284 char *mnem_p;
5c6af06e
JB		 2285 int supported;
2286 const template *t;
29b0f896
AM		 2287
2288 /* Non-zero if we found a prefix only acceptable with string insns. */
2289 const char *expecting_string_instruction = NULL;
45288df1 2290
29b0f896
AM		 2291 while (1)
2292 {
2293 mnem_p = mnemonic;
2294 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2295 {
2296 mnem_p++;
2297 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2298 {
29b0f896
AM		 2299 as_bad (_("no such instruction: `%s'"), token_start);
2300 return NULL;
2301 }
2302 l++;
2303 }
2304 if (!is_space_char (*l)
2305 && *l != END_OF_INSN
e44823cf
JB		 2306 && (intel_syntax
2307 || (*l != PREFIX_SEPARATOR
2308 && *l != ',')))
29b0f896
AM		 2309 {
2310 as_bad (_("invalid character %s in mnemonic"),
2311 output_invalid (*l));
2312 return NULL;
2313 }
2314 if (token_start == l)
2315 {
e44823cf 2316 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2317 as_bad (_("expecting prefix; got nothing"));
2318 else
2319 as_bad (_("expecting mnemonic; got nothing"));
2320 return NULL;
2321 }
45288df1 2322
29b0f896
AM		 2323 /* Look up instruction (or prefix) via hash table. */
2324 current_templates = hash_find (op_hash, mnemonic);
47926f60 2325
29b0f896
AM		 2326 if (*l != END_OF_INSN
2327 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2328 && current_templates
40fb9820 2329 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2330 {
40fb9820 2331 if (!cpu_flags_check_x64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2332 {
2333 as_bad ((flag_code != CODE_64BIT
2334 ? _("`%s' is only supported in 64-bit mode")
2335 : _("`%s' is not supported in 64-bit mode")),
2336 current_templates->start->name);
2337 return NULL;
2338 }
29b0f896
AM		 2339 /* If we are in 16-bit mode, do not allow addr16 or data16.
2340 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2341 if ((current_templates->start->opcode_modifier.size16
2342 || current_templates->start->opcode_modifier.size32)
29b0f896 2343 && flag_code != CODE_64BIT
40fb9820 2344 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2345 ^ (flag_code == CODE_16BIT)))
2346 {
2347 as_bad (_("redundant %s prefix"),
2348 current_templates->start->name);
2349 return NULL;
45288df1 2350 }
29b0f896
AM		 2351 /* Add prefix, checking for repeated prefixes. */
2352 switch (add_prefix (current_templates->start->base_opcode))
2353 {
2354 case 0:
2355 return NULL;
2356 case 2:
2357 expecting_string_instruction = current_templates->start->name;
2358 break;
2359 }
2360 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2361 token_start = ++l;
2362 }
2363 else
2364 break;
2365 }
45288df1 2366
29b0f896
AM		 2367 if (!current_templates)
2368 {
2369 /* See if we can get a match by trimming off a suffix. */
2370 switch (mnem_p[-1])
2371 {
2372 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2373 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2374 i.suffix = SHORT_MNEM_SUFFIX;
2375 else
29b0f896
AM		 2376 case BYTE_MNEM_SUFFIX:
2377 case QWORD_MNEM_SUFFIX:
2378 i.suffix = mnem_p[-1];
2379 mnem_p[-1] = '\0';
2380 current_templates = hash_find (op_hash, mnemonic);
2381 break;
2382 case SHORT_MNEM_SUFFIX:
2383 case LONG_MNEM_SUFFIX:
2384 if (!intel_syntax)
2385 {
2386 i.suffix = mnem_p[-1];
2387 mnem_p[-1] = '\0';
2388 current_templates = hash_find (op_hash, mnemonic);
2389 }
2390 break;
252b5132 2391
29b0f896
AM		 2392 /* Intel Syntax. */
2393 case 'd':
2394 if (intel_syntax)
2395 {
9306ca4a 2396 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2397 i.suffix = SHORT_MNEM_SUFFIX;
2398 else
2399 i.suffix = LONG_MNEM_SUFFIX;
2400 mnem_p[-1] = '\0';
2401 current_templates = hash_find (op_hash, mnemonic);
2402 }
2403 break;
2404 }
2405 if (!current_templates)
2406 {
2407 as_bad (_("no such instruction: `%s'"), token_start);
2408 return NULL;
2409 }
2410 }
252b5132 2411
40fb9820
L		 2412 if (current_templates->start->opcode_modifier.jump
2413 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 2414 {
2415 /* Check for a branch hint. We allow ",pt" and ",pn" for
2416 predict taken and predict not taken respectively.
2417 I'm not sure that branch hints actually do anything on loop
2418 and jcxz insns (JumpByte) for current Pentium4 chips. They
2419 may work in the future and it doesn't hurt to accept them
2420 now. */
2421 if (l[0] == ',' && l[1] == 'p')
2422 {
2423 if (l[2] == 't')
2424 {
2425 if (!add_prefix (DS_PREFIX_OPCODE))
2426 return NULL;
2427 l += 3;
2428 }
2429 else if (l[2] == 'n')
2430 {
2431 if (!add_prefix (CS_PREFIX_OPCODE))
2432 return NULL;
2433 l += 3;
2434 }
2435 }
2436 }
2437 /* Any other comma loses. */
2438 if (*l == ',')
2439 {
2440 as_bad (_("invalid character %s in mnemonic"),
2441 output_invalid (*l));
2442 return NULL;
2443 }
252b5132 2444
29b0f896 2445 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2446 supported = 0;
2447 for (t = current_templates->start; t < current_templates->end; ++t)
2448 {
40fb9820 2449 if (cpu_flags_match (t->cpu_flags))
64e74474 2450 supported |= 1;
40fb9820 2451 if (cpu_flags_check_x64 (t->cpu_flags))
64e74474 2452 supported |= 2;
5c6af06e
JB		 2453 }
2454 if (!(supported & 2))
2455 {
2456 as_bad (flag_code == CODE_64BIT
2457 ? _("`%s' is not supported in 64-bit mode")
2458 : _("`%s' is only supported in 64-bit mode"),
2459 current_templates->start->name);
2460 return NULL;
2461 }
2462 if (!(supported & 1))
29b0f896 2463 {
5c6af06e
JB		 2464 as_warn (_("`%s' is not supported on `%s%s'"),
2465 current_templates->start->name,
2466 cpu_arch_name,
2467 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896 2468 }
40fb9820
L		 2469 else if (!cpu_arch_flags.bitfield.cpui386
2470 && (flag_code != CODE_16BIT))
29b0f896
AM		 2471 {
2472 as_warn (_("use .code16 to ensure correct addressing mode"));
2473 }
252b5132 2474
29b0f896 2475 /* Check for rep/repne without a string instruction. */
f41bbced 2476 if (expecting_string_instruction)
29b0f896 2477 {
f41bbced
JB		 2478 static templates override;
2479
2480 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 2481 if (t->opcode_modifier.isstring)
f41bbced
JB		 2482 break;
2483 if (t >= current_templates->end)
2484 {
2485 as_bad (_("expecting string instruction after `%s'"),
64e74474 2486 expecting_string_instruction);
f41bbced
JB		 2487 return NULL;
2488 }
2489 for (override.start = t; t < current_templates->end; ++t)
40fb9820 2490 if (!t->opcode_modifier.isstring)
f41bbced
JB		 2491 break;
2492 override.end = t;
2493 current_templates = &override;
29b0f896 2494 }
252b5132 2495
29b0f896
AM		 2496 return l;
2497}
252b5132 2498
29b0f896 2499static char *
e3bb37b5 2500parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2501{
2502 char *token_start;
3138f287 2503
29b0f896
AM		 2504 /* 1 if operand is pending after ','. */
2505 unsigned int expecting_operand = 0;
252b5132 2506
29b0f896
AM		 2507 /* Non-zero if operand parens not balanced. */
2508 unsigned int paren_not_balanced;
2509
2510 while (*l != END_OF_INSN)
2511 {
2512 /* Skip optional white space before operand. */
2513 if (is_space_char (*l))
2514 ++l;
2515 if (!is_operand_char (*l) && *l != END_OF_INSN)
2516 {
2517 as_bad (_("invalid character %s before operand %d"),
2518 output_invalid (*l),
2519 i.operands + 1);
2520 return NULL;
2521 }
2522 token_start = l; /* after white space */
2523 paren_not_balanced = 0;
2524 while (paren_not_balanced || *l != ',')
2525 {
2526 if (*l == END_OF_INSN)
2527 {
2528 if (paren_not_balanced)
2529 {
2530 if (!intel_syntax)
2531 as_bad (_("unbalanced parenthesis in operand %d."),
2532 i.operands + 1);
2533 else
2534 as_bad (_("unbalanced brackets in operand %d."),
2535 i.operands + 1);
2536 return NULL;
2537 }
2538 else
2539 break; /* we are done */
2540 }
2541 else if (!is_operand_char (*l) && !is_space_char (*l))
2542 {
2543 as_bad (_("invalid character %s in operand %d"),
2544 output_invalid (*l),
2545 i.operands + 1);
2546 return NULL;
2547 }
2548 if (!intel_syntax)
2549 {
2550 if (*l == '(')
2551 ++paren_not_balanced;
2552 if (*l == ')')
2553 --paren_not_balanced;
2554 }
2555 else
2556 {
2557 if (*l == '[')
2558 ++paren_not_balanced;
2559 if (*l == ']')
2560 --paren_not_balanced;
2561 }
2562 l++;
2563 }
2564 if (l != token_start)
2565 { /* Yes, we've read in another operand. */
2566 unsigned int operand_ok;
2567 this_operand = i.operands++;
2568 if (i.operands > MAX_OPERANDS)
2569 {
2570 as_bad (_("spurious operands; (%d operands/instruction max)"),
2571 MAX_OPERANDS);
2572 return NULL;
2573 }
2574 /* Now parse operand adding info to 'i' as we go along. */
2575 END_STRING_AND_SAVE (l);
2576
2577 if (intel_syntax)
2578 operand_ok =
2579 i386_intel_operand (token_start,
2580 intel_float_operand (mnemonic));
2581 else
2582 operand_ok = i386_operand (token_start);
2583
2584 RESTORE_END_STRING (l);
2585 if (!operand_ok)
2586 return NULL;
2587 }
2588 else
2589 {
2590 if (expecting_operand)
2591 {
2592 expecting_operand_after_comma:
2593 as_bad (_("expecting operand after ','; got nothing"));
2594 return NULL;
2595 }
2596 if (*l == ',')
2597 {
2598 as_bad (_("expecting operand before ','; got nothing"));
2599 return NULL;
2600 }
2601 }
7f3f1ea2 2602
29b0f896
AM		 2603 /* Now *l must be either ',' or END_OF_INSN. */
2604 if (*l == ',')
2605 {
2606 if (*++l == END_OF_INSN)
2607 {
2608 /* Just skip it, if it's \n complain. */
2609 goto expecting_operand_after_comma;
2610 }
2611 expecting_operand = 1;
2612 }
2613 }
2614 return l;
2615}
7f3f1ea2 2616
050dfa73 2617static void
4d456e3d 2618swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2619{
2620 union i386_op temp_op;
40fb9820 2621 i386_operand_type temp_type;
050dfa73 2622 enum bfd_reloc_code_real temp_reloc;
4eed87de 2623
050dfa73
MM		 2624 temp_type = i.types[xchg2];
2625 i.types[xchg2] = i.types[xchg1];
2626 i.types[xchg1] = temp_type;
2627 temp_op = i.op[xchg2];
2628 i.op[xchg2] = i.op[xchg1];
2629 i.op[xchg1] = temp_op;
2630 temp_reloc = i.reloc[xchg2];
2631 i.reloc[xchg2] = i.reloc[xchg1];
2632 i.reloc[xchg1] = temp_reloc;
2633}
2634
29b0f896 2635static void
e3bb37b5 2636swap_operands (void)
29b0f896 2637{
b7c61d9a 2638 switch (i.operands)
050dfa73 2639 {
b7c61d9a 2640 case 4:
4d456e3d 2641 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2642 case 3:
2643 case 2:
4d456e3d 2644 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2645 break;
2646 default:
2647 abort ();
29b0f896 2648 }
29b0f896
AM		 2649
2650 if (i.mem_operands == 2)
2651 {
2652 const seg_entry *temp_seg;
2653 temp_seg = i.seg[0];
2654 i.seg[0] = i.seg[1];
2655 i.seg[1] = temp_seg;
2656 }
2657}
252b5132 2658
29b0f896
AM		 2659/* Try to ensure constant immediates are represented in the smallest
2660 opcode possible. */
2661static void
e3bb37b5 2662optimize_imm (void)
29b0f896
AM		 2663{
2664 char guess_suffix = 0;
2665 int op;
252b5132 2666
29b0f896
AM		 2667 if (i.suffix)
2668 guess_suffix = i.suffix;
2669 else if (i.reg_operands)
2670 {
2671 /* Figure out a suffix from the last register operand specified.
2672 We can't do this properly yet, ie. excluding InOutPortReg,
2673 but the following works for instructions with immediates.
2674 In any case, we can't set i.suffix yet. */
2675 for (op = i.operands; --op >= 0;)
40fb9820
L		 2676 if (i.types[op].bitfield.reg8)
2677 {
2678 guess_suffix = BYTE_MNEM_SUFFIX;
2679 break;
2680 }
2681 else if (i.types[op].bitfield.reg16)
252b5132 2682 {
40fb9820
L		 2683 guess_suffix = WORD_MNEM_SUFFIX;
2684 break;
2685 }
2686 else if (i.types[op].bitfield.reg32)
2687 {
2688 guess_suffix = LONG_MNEM_SUFFIX;
2689 break;
2690 }
2691 else if (i.types[op].bitfield.reg64)
2692 {
2693 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 2694 break;
252b5132 2695 }
29b0f896
AM		 2696 }
2697 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2698 guess_suffix = WORD_MNEM_SUFFIX;
2699
2700 for (op = i.operands; --op >= 0;)
40fb9820 2701 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 2702 {
2703 switch (i.op[op].imms->X_op)
252b5132 2704 {
29b0f896
AM		 2705 case O_constant:
2706 /* If a suffix is given, this operand may be shortened. */
2707 switch (guess_suffix)
252b5132 2708 {
29b0f896 2709 case LONG_MNEM_SUFFIX:
40fb9820
L		 2710 i.types[op].bitfield.imm32 = 1;
2711 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2712 break;
2713 case WORD_MNEM_SUFFIX:
40fb9820
L		 2714 i.types[op].bitfield.imm16 = 1;
2715 i.types[op].bitfield.imm32 = 1;
2716 i.types[op].bitfield.imm32s = 1;
2717 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2718 break;
2719 case BYTE_MNEM_SUFFIX:
40fb9820
L		 2720 i.types[op].bitfield.imm8 = 1;
2721 i.types[op].bitfield.imm8s = 1;
2722 i.types[op].bitfield.imm16 = 1;
2723 i.types[op].bitfield.imm32 = 1;
2724 i.types[op].bitfield.imm32s = 1;
2725 i.types[op].bitfield.imm64 = 1;
29b0f896 2726 break;
252b5132 2727 }
252b5132 2728
29b0f896
AM		 2729 /* If this operand is at most 16 bits, convert it
2730 to a signed 16 bit number before trying to see
2731 whether it will fit in an even smaller size.
2732 This allows a 16-bit operand such as $0xffe0 to
2733 be recognised as within Imm8S range. */
40fb9820 2734 if ((i.types[op].bitfield.imm16)
29b0f896 2735 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2736 {
29b0f896
AM		 2737 i.op[op].imms->X_add_number =
2738 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2739 }
40fb9820 2740 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 2741 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2742 == 0))
2743 {
2744 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2745 ^ ((offsetT) 1 << 31))
2746 - ((offsetT) 1 << 31));
2747 }
40fb9820
L		 2748 i.types[op]
2749 = operand_type_biop (i.types[op],
2750 smallest_imm_type (i.op[op].imms->X_add_number),
2751 or);
252b5132 2752
29b0f896
AM		 2753 /* We must avoid matching of Imm32 templates when 64bit
2754 only immediate is available. */
2755 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 2756 i.types[op].bitfield.imm32 = 0;
29b0f896 2757 break;
252b5132 2758
29b0f896
AM		 2759 case O_absent:
2760 case O_register:
2761 abort ();
2762
2763 /* Symbols and expressions. */
2764 default:
9cd96992
JB		 2765 /* Convert symbolic operand to proper sizes for matching, but don't
2766 prevent matching a set of insns that only supports sizes other
2767 than those matching the insn suffix. */
2768 {
40fb9820 2769 i386_operand_type mask, allowed;
9cd96992
JB		 2770 const template *t;
2771
40fb9820
L		 2772 memset (&mask, 0, sizeof (mask));
2773 memset (&allowed, 0, sizeof (allowed));
2774
4eed87de
AM		 2775 for (t = current_templates->start;
2776 t < current_templates->end;
2777 ++t)
40fb9820
L		 2778 allowed = operand_type_biop (allowed,
2779 t->operand_types[op], or);
9cd96992
JB		 2780 switch (guess_suffix)
2781 {
2782 case QWORD_MNEM_SUFFIX:
40fb9820
L		 2783 mask.bitfield.imm64 = 1;
2784 mask.bitfield.imm32s = 1;
9cd96992
JB		 2785 break;
2786 case LONG_MNEM_SUFFIX:
40fb9820 2787 mask.bitfield.imm32 = 1;
9cd96992
JB		 2788 break;
2789 case WORD_MNEM_SUFFIX:
40fb9820 2790 mask.bitfield.imm16 = 1;
9cd96992
JB		 2791 break;
2792 case BYTE_MNEM_SUFFIX:
40fb9820 2793 mask.bitfield.imm8 = 1;
9cd96992
JB		 2794 break;
2795 default:
9cd96992
JB		 2796 break;
2797 }
40fb9820
L		 2798 if (!operand_type_all_zero (operand_type_biop (mask,
2799 allowed,
2800 and)))
2801 i.types[op] = operand_type_biop (i.types[op],
2802 mask, and);
9cd96992 2803 }
29b0f896 2804 break;
252b5132 2805 }
29b0f896
AM		 2806 }
2807}
47926f60 2808
29b0f896
AM		 2809/* Try to use the smallest displacement type too. */
2810static void
e3bb37b5 2811optimize_disp (void)
29b0f896
AM		 2812{
2813 int op;
3e73aa7c 2814
29b0f896 2815 for (op = i.operands; --op >= 0;)
40fb9820 2816 if (operand_type_check (i.types[op], disp))
252b5132 2817 {
b300c311 2818 if (i.op[op].disps->X_op == O_constant)
252b5132 2819 {
b300c311 2820 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2821
40fb9820 2822 if (i.types[op].bitfield.disp16
b300c311
L		 2823 && (disp & ~(offsetT) 0xffff) == 0)
2824 {
2825 /* If this operand is at most 16 bits, convert
2826 to a signed 16 bit number and don't use 64bit
2827 displacement. */
2828 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 2829 i.types[op].bitfield.disp64 = 0;
b300c311 2830 }
40fb9820 2831 if (i.types[op].bitfield.disp32
b300c311
L		 2832 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2833 {
2834 /* If this operand is at most 32 bits, convert
2835 to a signed 32 bit number and don't use 64bit
2836 displacement. */
2837 disp &= (((offsetT) 2 << 31) - 1);
2838 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 2839 i.types[op].bitfield.disp64 = 0;
b300c311 2840 }
40fb9820 2841 if (!disp && i.types[op].bitfield.baseindex)
b300c311 2842 {
40fb9820
L		 2843 i.types[op].bitfield.disp8 = 0;
2844 i.types[op].bitfield.disp16 = 0;
2845 i.types[op].bitfield.disp32 = 0;
2846 i.types[op].bitfield.disp32s = 0;
2847 i.types[op].bitfield.disp64 = 0;
b300c311
L		 2848 i.op[op].disps = 0;
2849 i.disp_operands--;
2850 }
2851 else if (flag_code == CODE_64BIT)
2852 {
2853 if (fits_in_signed_long (disp))
28a9d8f5 2854 {
40fb9820
L		 2855 i.types[op].bitfield.disp64 = 0;
2856 i.types[op].bitfield.disp32s = 1;
28a9d8f5 2857 }
b300c311 2858 if (fits_in_unsigned_long (disp))
40fb9820 2859 i.types[op].bitfield.disp32 = 1;
b300c311 2860 }
40fb9820
L		 2861 if ((i.types[op].bitfield.disp32
2862 || i.types[op].bitfield.disp32s
2863 || i.types[op].bitfield.disp16)
b300c311 2864 && fits_in_signed_byte (disp))
40fb9820 2865 i.types[op].bitfield.disp8 = 1;
252b5132 2866 }
67a4f2b7
AO		 2867 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2868 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2869 {
2870 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2871 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 2872 i.types[op].bitfield.disp8 = 0;
2873 i.types[op].bitfield.disp16 = 0;
2874 i.types[op].bitfield.disp32 = 0;
2875 i.types[op].bitfield.disp32s = 0;
2876 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 2877 }
2878 else
b300c311 2879 /* We only support 64bit displacement on constants. */
40fb9820 2880 i.types[op].bitfield.disp64 = 0;
252b5132 2881 }
29b0f896
AM		 2882}
2883
2884static int
e3bb37b5 2885match_template (void)
29b0f896
AM		 2886{
2887 /* Points to template once we've found it. */
2888 const template *t;
40fb9820 2889 i386_operand_type overlap0, overlap1, overlap2, overlap3;
29b0f896 2890 unsigned int found_reverse_match;
40fb9820
L		 2891 i386_opcode_modifier suffix_check;
2892 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 2893 int addr_prefix_disp;
a5c311ca 2894 unsigned int j;
29b0f896 2895
f48ff2ae
L		 2896#if MAX_OPERANDS != 4
2897# error "MAX_OPERANDS must be 4."
2898#endif
2899
29b0f896 2900 found_reverse_match = 0;
539e75ad 2901 addr_prefix_disp = -1;
40fb9820
L		 2902
2903 memset (&suffix_check, 0, sizeof (suffix_check));
2904 if (i.suffix == BYTE_MNEM_SUFFIX)
2905 suffix_check.no_bsuf = 1;
2906 else if (i.suffix == WORD_MNEM_SUFFIX)
2907 suffix_check.no_wsuf = 1;
2908 else if (i.suffix == SHORT_MNEM_SUFFIX)
2909 suffix_check.no_ssuf = 1;
2910 else if (i.suffix == LONG_MNEM_SUFFIX)
2911 suffix_check.no_lsuf = 1;
2912 else if (i.suffix == QWORD_MNEM_SUFFIX)
2913 suffix_check.no_qsuf = 1;
2914 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
2915 suffix_check.no_xsuf = 1;
29b0f896 2916
45aa61fe 2917 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2918 {
539e75ad
L		 2919 addr_prefix_disp = -1;
2920
29b0f896
AM		 2921 /* Must have right number of operands. */
2922 if (i.operands != t->operands)
2923 continue;
2924
20592a94 2925 /* Check the suffix, except for some instructions in intel mode. */
40fb9820
L		 2926 if (((t->opcode_modifier.no_bsuf & suffix_check.no_bsuf)
2927 || (t->opcode_modifier.no_wsuf & suffix_check.no_wsuf)
2928 || (t->opcode_modifier.no_lsuf & suffix_check.no_lsuf)
2929 || (t->opcode_modifier.no_ssuf & suffix_check.no_ssuf)
2930 || (t->opcode_modifier.no_qsuf & suffix_check.no_qsuf)
2931 || (t->opcode_modifier.no_xsuf & suffix_check.no_xsuf))
2932 && !(intel_syntax && t->opcode_modifier.ignoresize))
29b0f896
AM		 2933 continue;
2934
a5c311ca
L		 2935 for (j = 0; j < MAX_OPERANDS; j++)
2936 operand_types [j] = t->operand_types [j];
539e75ad 2937
45aa61fe
AM		 2938 /* In general, don't allow 64-bit operands in 32-bit mode. */
2939 if (i.suffix == QWORD_MNEM_SUFFIX
2940 && flag_code != CODE_64BIT
2941 && (intel_syntax
40fb9820 2942 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 2943 && !intel_float_operand (t->name))
2944 : intel_float_operand (t->name) != 2)
40fb9820
L		 2945 && ((!operand_types[0].bitfield.regmmx
2946 && !operand_types[0].bitfield.regxmm)
2947 || (!operand_types[t->operands > 1].bitfield.regmmx
2948 && !!operand_types[t->operands > 1].bitfield.regxmm))
45aa61fe
AM		 2949 && (t->base_opcode != 0x0fc7
2950 || t->extension_opcode != 1 /* cmpxchg8b */))
2951 continue;
2952
29b0f896
AM		 2953 /* Do not verify operands when there are none. */
2954 else if (!t->operands)
2955 {
40fb9820
L		 2956 if (!cpu_flags_all_zero (cpu_flags_biop (t->cpu_flags,
2957 cpu_arch_flags_not,
2958 and)))
29b0f896
AM		 2959 continue;
2960 /* We've found a match; break out of loop. */
2961 break;
2962 }
252b5132 2963
539e75ad
L		 2964 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2965 into Disp32/Disp16/Disp32 operand. */
2966 if (i.prefix[ADDR_PREFIX] != 0)
2967 {
40fb9820 2968 /* There should be only one Disp operand. */
539e75ad
L		 2969 switch (flag_code)
2970 {
2971 case CODE_16BIT:
40fb9820
L		 2972 for (j = 0; j < MAX_OPERANDS; j++)
2973 {
2974 if (operand_types[j].bitfield.disp16)
2975 {
2976 addr_prefix_disp = j;
2977 operand_types[j].bitfield.disp32 = 1;
2978 operand_types[j].bitfield.disp16 = 0;
2979 break;
2980 }
2981 }
539e75ad
L		 2982 break;
2983 case CODE_32BIT:
40fb9820
L		 2984 for (j = 0; j < MAX_OPERANDS; j++)
2985 {
2986 if (operand_types[j].bitfield.disp32)
2987 {
2988 addr_prefix_disp = j;
2989 operand_types[j].bitfield.disp32 = 0;
2990 operand_types[j].bitfield.disp16 = 1;
2991 break;
2992 }
2993 }
539e75ad
L		 2994 break;
2995 case CODE_64BIT:
40fb9820
L		 2996 for (j = 0; j < MAX_OPERANDS; j++)
2997 {
2998 if (operand_types[j].bitfield.disp64)
2999 {
3000 addr_prefix_disp = j;
3001 operand_types[j].bitfield.disp64 = 0;
3002 operand_types[j].bitfield.disp32 = 1;
3003 break;
3004 }
3005 }
539e75ad
L		 3006 break;
3007 }
539e75ad
L		 3008 }
3009
40fb9820
L		 3010 overlap0 = operand_type_biop (i.types[0], operand_types[0],
3011 and);
29b0f896
AM		 3012 switch (t->operands)
3013 {
3014 case 1:
40fb9820 3015 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3016 continue;
3017 break;
3018 case 2:
8b38ad71
L		 3019 /* xchg %eax, %eax is a special case. It is an aliase for nop
3020 only in 32bit mode and we can use opcode 0x90. In 64bit
3021 mode, we can't use 0x90 for xchg %eax, %eax since it should
3022 zero-extend %eax to %rax. */
3023 if (flag_code == CODE_64BIT
3024 && t->base_opcode == 0x90
40fb9820
L		 3025 && memcmp (&i.types [0], &acc32, sizeof (acc32)) == 0
3026 && memcmp (&i.types [1], &acc32, sizeof (acc32)) == 0)
8b38ad71 3027 continue;
29b0f896 3028 case 3:
f48ff2ae 3029 case 4:
40fb9820
L		 3030 overlap1 = operand_type_biop (i.types[1], operand_types[1],
3031 and);
3032 if (!operand_type_match (overlap0, i.types[0])
3033 || !operand_type_match (overlap1, i.types[1])
cb712a9e 3034 /* monitor in SSE3 is a very special case. The first
708587a4 3035 register and the second register may have different
26186d74
L		 3036 sizes. The same applies to crc32 in SSE4.2. It is
3037 also true for invlpga, vmload, vmrun and vmsave in
3038 SVME. */
cb712a9e 3039 || !((t->base_opcode == 0x0f01
26186d74
L		 3040 && (t->extension_opcode == 0xc8
3041 || t->extension_opcode == 0xd8
3042 || t->extension_opcode == 0xda
3043 || t->extension_opcode == 0xdb
3044 || t->extension_opcode == 0xdf))
381d071f 3045 || t->base_opcode == 0xf20f38f1
40fb9820
L		 3046 || operand_type_register_match (overlap0, i.types[0],
3047 operand_types[0],
3048 overlap1, i.types[1],
3049 operand_types[1])))
29b0f896
AM		 3050 {
3051 /* Check if other direction is valid ... */
40fb9820 3052 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3053 continue;
3054
3055 /* Try reversing direction of operands. */
40fb9820
L		 3056 overlap0 = operand_type_biop (i.types[0], operand_types[1],
3057 and);
3058 overlap1 = operand_type_biop (i.types[1], operand_types[0],
3059 and);
3060 if (!operand_type_match (overlap0, i.types[0])
3061 || !operand_type_match (overlap1, i.types[1])
3062 || !operand_type_register_match (overlap0, i.types[0],
3063 operand_types[1],
3064 overlap1, i.types[1],
3065 operand_types[0]))
29b0f896
AM		 3066 {
3067 /* Does not match either direction. */
3068 continue;
3069 }
3070 /* found_reverse_match holds which of D or FloatDR
3071 we've found. */
40fb9820 3072 if (t->opcode_modifier.d)
8a2ed489 3073 found_reverse_match = Opcode_D;
40fb9820 3074 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3075 found_reverse_match = Opcode_FloatD;
3076 else
3077 found_reverse_match = 0;
40fb9820 3078 if (t->opcode_modifier.floatr)
8a2ed489 3079 found_reverse_match |= Opcode_FloatR;
29b0f896 3080 }
f48ff2ae 3081 else
29b0f896 3082 {
f48ff2ae 3083 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3084 switch (t->operands)
3085 {
3086 case 4:
40fb9820
L		 3087 overlap3 = operand_type_biop (i.types[3],
3088 operand_types[3], and);
d1cbb4db 3089 case 3:
40fb9820
L		 3090 overlap2 = operand_type_biop (i.types[2],
3091 operand_types[2], and);
d1cbb4db
L		 3092 break;
3093 }
29b0f896 3094
f48ff2ae
L		 3095 switch (t->operands)
3096 {
3097 case 4:
40fb9820
L		 3098 if (!operand_type_match (overlap3, i.types[3])
3099 || !operand_type_register_match (overlap2,
3100 i.types[2],
3101 operand_types[2],
3102 overlap3,
3103 i.types[3],
3104 operand_types[3]))
f48ff2ae
L		 3105 continue;
3106 case 3:
3107 /* Here we make use of the fact that there are no
3108 reverse match 3 operand instructions, and all 3
3109 operand instructions only need to be checked for
3110 register consistency between operands 2 and 3. */
40fb9820
L		 3111 if (!operand_type_match (overlap2, i.types[2])
3112 || !operand_type_register_match (overlap1,
3113 i.types[1],
3114 operand_types[1],
3115 overlap2,
3116 i.types[2],
3117 operand_types[2]))
f48ff2ae
L		 3118 continue;
3119 break;
3120 }
29b0f896 3121 }
f48ff2ae 3122 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3123 slip through to break. */
3124 }
40fb9820
L		 3125 if (!cpu_flags_all_zero (cpu_flags_biop (t->cpu_flags,
3126 cpu_arch_flags_not,
3127 and)))
29b0f896
AM		 3128 {
3129 found_reverse_match = 0;
3130 continue;
3131 }
3132 /* We've found a match; break out of loop. */
3133 break;
3134 }
3135
3136 if (t == current_templates->end)
3137 {
3138 /* We found no match. */
3139 as_bad (_("suffix or operands invalid for `%s'"),
3140 current_templates->start->name);
3141 return 0;
3142 }
252b5132 3143
29b0f896
AM		 3144 if (!quiet_warnings)
3145 {
3146 if (!intel_syntax
40fb9820
L		 3147 && (i.types[0].bitfield.jumpabsolute
3148 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3149 {
3150 as_warn (_("indirect %s without `*'"), t->name);
3151 }
3152
40fb9820
L		 3153 if (t->opcode_modifier.isprefix
3154 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3155 {
3156 /* Warn them that a data or address size prefix doesn't
3157 affect assembly of the next line of code. */
3158 as_warn (_("stand-alone `%s' prefix"), t->name);
3159 }
3160 }
3161
3162 /* Copy the template we found. */
3163 i.tm = *t;
539e75ad
L		 3164
3165 if (addr_prefix_disp != -1)
3166 i.tm.operand_types[addr_prefix_disp]
3167 = operand_types[addr_prefix_disp];
3168
29b0f896
AM		 3169 if (found_reverse_match)
3170 {
3171 /* If we found a reverse match we must alter the opcode
3172 direction bit. found_reverse_match holds bits to change
3173 (different for int & float insns). */
3174
3175 i.tm.base_opcode ^= found_reverse_match;
3176
539e75ad
L		 3177 i.tm.operand_types[0] = operand_types[1];
3178 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3179 }
3180
3181 return 1;
3182}
3183
3184static int
e3bb37b5 3185check_string (void)
29b0f896 3186{
40fb9820
L		 3187 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3188 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3189 {
3190 if (i.seg[0] != NULL && i.seg[0] != &es)
3191 {
3192 as_bad (_("`%s' operand %d must use `%%es' segment"),
3193 i.tm.name,
3194 mem_op + 1);
3195 return 0;
3196 }
3197 /* There's only ever one segment override allowed per instruction.
3198 This instruction possibly has a legal segment override on the
3199 second operand, so copy the segment to where non-string
3200 instructions store it, allowing common code. */
3201 i.seg[0] = i.seg[1];
3202 }
40fb9820 3203 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3204 {
3205 if (i.seg[1] != NULL && i.seg[1] != &es)
3206 {
3207 as_bad (_("`%s' operand %d must use `%%es' segment"),
3208 i.tm.name,
3209 mem_op + 2);
3210 return 0;
3211 }
3212 }
3213 return 1;
3214}
3215
3216static int
543613e9 3217process_suffix (void)
29b0f896
AM		 3218{
3219 /* If matched instruction specifies an explicit instruction mnemonic
3220 suffix, use it. */
40fb9820
L		 3221 if (i.tm.opcode_modifier.size16)
3222 i.suffix = WORD_MNEM_SUFFIX;
3223 else if (i.tm.opcode_modifier.size32)
3224 i.suffix = LONG_MNEM_SUFFIX;
3225 else if (i.tm.opcode_modifier.size64)
3226 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3227 else if (i.reg_operands)
3228 {
3229 /* If there's no instruction mnemonic suffix we try to invent one
3230 based on register operands. */
3231 if (!i.suffix)
3232 {
3233 /* We take i.suffix from the last register operand specified,
3234 Destination register type is more significant than source
381d071f
L		 3235 register type. crc32 in SSE4.2 prefers source register
3236 type. */
3237 if (i.tm.base_opcode == 0xf20f38f1)
3238 {
40fb9820
L		 3239 if (i.types[0].bitfield.reg16)
3240 i.suffix = WORD_MNEM_SUFFIX;
3241 else if (i.types[0].bitfield.reg32)
3242 i.suffix = LONG_MNEM_SUFFIX;
3243 else if (i.types[0].bitfield.reg64)
3244 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3245 }
9344ff29 3246 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3247 {
40fb9820 3248 if (i.types[0].bitfield.reg8)
20592a94
L		 3249 i.suffix = BYTE_MNEM_SUFFIX;
3250 }
381d071f
L		 3251
3252 if (!i.suffix)
3253 {
3254 int op;
3255
20592a94
L		 3256 if (i.tm.base_opcode == 0xf20f38f1
3257 || i.tm.base_opcode == 0xf20f38f0)
3258 {
3259 /* We have to know the operand size for crc32. */
3260 as_bad (_("ambiguous memory operand size for `%s`"),
3261 i.tm.name);
3262 return 0;
3263 }
3264
381d071f 3265 for (op = i.operands; --op >= 0;)
40fb9820 3266 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3267 {
40fb9820
L		 3268 if (i.types[op].bitfield.reg8)
3269 {
3270 i.suffix = BYTE_MNEM_SUFFIX;
3271 break;
3272 }
3273 else if (i.types[op].bitfield.reg16)
3274 {
3275 i.suffix = WORD_MNEM_SUFFIX;
3276 break;
3277 }
3278 else if (i.types[op].bitfield.reg32)
3279 {
3280 i.suffix = LONG_MNEM_SUFFIX;
3281 break;
3282 }
3283 else if (i.types[op].bitfield.reg64)
3284 {
3285 i.suffix = QWORD_MNEM_SUFFIX;
3286 break;
3287 }
381d071f
L		 3288 }
3289 }
29b0f896
AM		 3290 }
3291 else if (i.suffix == BYTE_MNEM_SUFFIX)
3292 {
3293 if (!check_byte_reg ())
3294 return 0;
3295 }
3296 else if (i.suffix == LONG_MNEM_SUFFIX)
3297 {
3298 if (!check_long_reg ())
3299 return 0;
3300 }
3301 else if (i.suffix == QWORD_MNEM_SUFFIX)
3302 {
3303 if (!check_qword_reg ())
3304 return 0;
3305 }
3306 else if (i.suffix == WORD_MNEM_SUFFIX)
3307 {
3308 if (!check_word_reg ())
3309 return 0;
3310 }
40fb9820 3311 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 3312 /* Do nothing if the instruction is going to ignore the prefix. */
3313 ;
3314 else
3315 abort ();
3316 }
40fb9820 3317 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 3318 && !i.suffix
3319 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 3320 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 3321 {
3322 i.suffix = stackop_size;
3323 }
9306ca4a
JB		 3324 else if (intel_syntax
3325 && !i.suffix
40fb9820
L		 3326 && (i.tm.operand_types[0].bitfield.jumpabsolute
3327 || i.tm.opcode_modifier.jumpbyte
3328 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 3329 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3330 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 3331 {
3332 switch (flag_code)
3333 {
3334 case CODE_64BIT:
40fb9820 3335 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 3336 {
3337 i.suffix = QWORD_MNEM_SUFFIX;
3338 break;
3339 }
3340 case CODE_32BIT:
40fb9820 3341 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 3342 i.suffix = LONG_MNEM_SUFFIX;
3343 break;
3344 case CODE_16BIT:
40fb9820 3345 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 3346 i.suffix = WORD_MNEM_SUFFIX;
3347 break;
3348 }
3349 }
252b5132 3350
9306ca4a 3351 if (!i.suffix)
29b0f896 3352 {
9306ca4a
JB		 3353 if (!intel_syntax)
3354 {
40fb9820 3355 if (i.tm.opcode_modifier.w)
9306ca4a 3356 {
4eed87de
AM		 3357 as_bad (_("no instruction mnemonic suffix given and "
3358 "no register operands; can't size instruction"));
9306ca4a
JB		 3359 return 0;
3360 }
3361 }
3362 else
3363 {
40fb9820
L		 3364 unsigned int suffixes;
3365
3366 suffixes = !i.tm.opcode_modifier.no_bsuf;
3367 if (!i.tm.opcode_modifier.no_wsuf)
3368 suffixes |= 1 << 1;
3369 if (!i.tm.opcode_modifier.no_lsuf)
3370 suffixes |= 1 << 2;
3371 if (!i.tm.opcode_modifier.no_lsuf)
3372 suffixes |= 1 << 3;
3373 if (!i.tm.opcode_modifier.no_ssuf)
3374 suffixes |= 1 << 4;
3375 if (!i.tm.opcode_modifier.no_qsuf)
3376 suffixes |= 1 << 5;
3377
3378 /* There are more than suffix matches. */
3379 if (i.tm.opcode_modifier.w
9306ca4a 3380 || ((suffixes & (suffixes - 1))
40fb9820
L		 3381 && !i.tm.opcode_modifier.defaultsize
3382 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 3383 {
3384 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3385 return 0;
3386 }
3387 }
29b0f896 3388 }
252b5132 3389
9306ca4a
JB		 3390 /* Change the opcode based on the operand size given by i.suffix;
3391 We don't need to change things for byte insns. */
3392
29b0f896
AM		 3393 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
3394 {
3395 /* It's not a byte, select word/dword operation. */
40fb9820 3396 if (i.tm.opcode_modifier.w)
29b0f896 3397 {
40fb9820 3398 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 3399 i.tm.base_opcode |= 8;
3400 else
3401 i.tm.base_opcode |= 1;
3402 }
0f3f3d8b 3403
29b0f896
AM		 3404 /* Now select between word & dword operations via the operand
3405 size prefix, except for instructions that will ignore this
3406 prefix anyway. */
26186d74
L		 3407 if (i.tm.base_opcode == 0x0f01
3408 && (i.tm.extension_opcode == 0xc8
3409 || i.tm.extension_opcode == 0xd8
3410 || i.tm.extension_opcode == 0xda
3411 || i.tm.extension_opcode == 0xdb
3412 || i.tm.extension_opcode == 0xdf))
cb712a9e
L		 3413 {
3414 /* monitor in SSE3 is a very special case. The default size
3415 of AX is the size of mode. The address size override
26186d74
L		 3416 prefix will change the size of AX. It is also true for
3417 invlpga, vmload, vmrun and vmsave in SVME. */
40fb9820
L		 3418 if ((flag_code == CODE_32BIT
3419 && i.op->regs[0].reg_type.bitfield.reg16)
3420 || (flag_code != CODE_32BIT
3421 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 3422 if (!add_prefix (ADDR_PREFIX_OPCODE))
3423 return 0;
3424 }
3425 else if (i.suffix != QWORD_MNEM_SUFFIX
3426 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 3427 && !i.tm.opcode_modifier.ignoresize
3428 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 3429 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3430 || (flag_code == CODE_64BIT
40fb9820 3431 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 3432 {
3433 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3434
40fb9820 3435 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 3436 prefix = ADDR_PREFIX_OPCODE;
252b5132 3437
29b0f896
AM		 3438 if (!add_prefix (prefix))
3439 return 0;
24eab124 3440 }
252b5132 3441
29b0f896
AM		 3442 /* Set mode64 for an operand. */
3443 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3444 && flag_code == CODE_64BIT
40fb9820 3445 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 3446 {
3447 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 3448 need rex64. cmpxchg8b is also a special case. */
3449 if (! (i.operands == 2
3450 && i.tm.base_opcode == 0x90
3451 && i.tm.extension_opcode == None
40fb9820
L		 3452 && memcmp (&i.types [0], &acc64, sizeof (acc64)) == 0
3453 && memcmp (&i.types [1], &acc64, sizeof (acc64)) == 0)
d9a5e5e5
L		 3454 && ! (i.operands == 1
3455 && i.tm.base_opcode == 0xfc7
3456 && i.tm.extension_opcode == 1
40fb9820
L		 3457 && !operand_type_check (i.types [0], reg)
3458 && operand_type_check (i.types [0], anymem)))
f6bee062 3459 i.rex |= REX_W;
46e883c5 3460 }
3e73aa7c 3461
29b0f896
AM		 3462 /* Size floating point instruction. */
3463 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 3464 if (i.tm.opcode_modifier.floatmf)
543613e9 3465 i.tm.base_opcode ^= 4;
29b0f896 3466 }
7ecd2f8b 3467
29b0f896
AM		 3468 return 1;
3469}
3e73aa7c 3470
29b0f896 3471static int
543613e9 3472check_byte_reg (void)
29b0f896
AM		 3473{
3474 int op;
543613e9 3475
29b0f896
AM		 3476 for (op = i.operands; --op >= 0;)
3477 {
3478 /* If this is an eight bit register, it's OK. If it's the 16 or
3479 32 bit version of an eight bit register, we will just use the
3480 low portion, and that's OK too. */
40fb9820 3481 if (i.types[op].bitfield.reg8)
29b0f896
AM		 3482 continue;
3483
c3ad16c0
L		 3484 /* movzx, movsx, pextrb and pinsrb should not generate this
3485 warning. */
29b0f896
AM		 3486 if (intel_syntax
3487 && (i.tm.base_opcode == 0xfb7
3488 || i.tm.base_opcode == 0xfb6
3489 || i.tm.base_opcode == 0x63
3490 || i.tm.base_opcode == 0xfbe
c3ad16c0
L		 3491 || i.tm.base_opcode == 0xfbf
3492 || i.tm.base_opcode == 0x660f3a14
3493 || i.tm.base_opcode == 0x660f3a20))
29b0f896
AM		 3494 continue;
3495
9344ff29
L		 3496 /* crc32 doesn't generate this warning. */
3497 if (i.tm.base_opcode == 0xf20f38f0)
3498 continue;
3499
40fb9820
L		 3500 if ((i.types[op].bitfield.reg16
3501 || i.types[op].bitfield.reg32
3502 || i.types[op].bitfield.reg64)
3503 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3504 {
3505 /* Prohibit these changes in the 64bit mode, since the
3506 lowering is more complicated. */
3507 if (flag_code == CODE_64BIT
40fb9820 3508 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 3509 {
2ca3ace5
L		 3510 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3511 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3512 i.suffix);
3513 return 0;
3514 }
3515#if REGISTER_WARNINGS
3516 if (!quiet_warnings
40fb9820 3517 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 3518 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3519 register_prefix,
40fb9820 3520 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 3521 ? REGNAM_AL - REGNAM_AX
3522 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3523 register_prefix,
29b0f896
AM		 3524 i.op[op].regs->reg_name,
3525 i.suffix);
3526#endif
3527 continue;
3528 }
3529 /* Any other register is bad. */
40fb9820
L		 3530 if (i.types[op].bitfield.reg16
3531 || i.types[op].bitfield.reg32
3532 || i.types[op].bitfield.reg64
3533 || i.types[op].bitfield.regmmx
3534 || i.types[op].bitfield.regxmm
3535 || i.types[op].bitfield.sreg2
3536 || i.types[op].bitfield.sreg3
3537 || i.types[op].bitfield.control
3538 || i.types[op].bitfield.debug
3539 || i.types[op].bitfield.test
3540 || i.types[op].bitfield.floatreg
3541 || i.types[op].bitfield.floatacc)
29b0f896 3542 {
a540244d
L		 3543 as_bad (_("`%s%s' not allowed with `%s%c'"),
3544 register_prefix,
29b0f896
AM		 3545 i.op[op].regs->reg_name,
3546 i.tm.name,
3547 i.suffix);
3548 return 0;
3549 }
3550 }
3551 return 1;
3552}
3553
3554static int
e3bb37b5 3555check_long_reg (void)
29b0f896
AM		 3556{
3557 int op;
3558
3559 for (op = i.operands; --op >= 0;)
3560 /* Reject eight bit registers, except where the template requires
3561 them. (eg. movzb) */
40fb9820
L		 3562 if (i.types[op].bitfield.reg8
3563 && (i.tm.operand_types[op].bitfield.reg16
3564 || i.tm.operand_types[op].bitfield.reg32
3565 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3566 {
a540244d
L		 3567 as_bad (_("`%s%s' not allowed with `%s%c'"),
3568 register_prefix,
29b0f896
AM		 3569 i.op[op].regs->reg_name,
3570 i.tm.name,
3571 i.suffix);
3572 return 0;
3573 }
3574 /* Warn if the e prefix on a general reg is missing. */
3575 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3576 && i.types[op].bitfield.reg16
3577 && (i.tm.operand_types[op].bitfield.reg32
3578 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3579 {
3580 /* Prohibit these changes in the 64bit mode, since the
3581 lowering is more complicated. */
3582 if (flag_code == CODE_64BIT)
252b5132 3583 {
2ca3ace5
L		 3584 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3585 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3586 i.suffix);
3587 return 0;
252b5132 3588 }
29b0f896
AM		 3589#if REGISTER_WARNINGS
3590 else
a540244d
L		 3591 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3592 register_prefix,
29b0f896 3593 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3594 register_prefix,
29b0f896
AM		 3595 i.op[op].regs->reg_name,
3596 i.suffix);
3597#endif
252b5132 3598 }
29b0f896 3599 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 3600 else if (i.types[op].bitfield.reg64
3601 && (i.tm.operand_types[op].bitfield.reg32
3602 || i.tm.operand_types[op].bitfield.acc))
252b5132 3603 {
34828aad
L		 3604 if (intel_syntax
3605 && i.tm.base_opcode == 0xf30f2d
40fb9820 3606 && !i.types[0].bitfield.regxmm)
34828aad
L		 3607 {
3608 /* cvtss2si converts DWORD memory to Reg64. We want
3609 REX byte. */
3610 i.suffix = QWORD_MNEM_SUFFIX;
3611 }
3612 else
3613 {
3614 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3615 register_prefix, i.op[op].regs->reg_name,
3616 i.suffix);
3617 return 0;
3618 }
29b0f896
AM		 3619 }
3620 return 1;
3621}
252b5132 3622
29b0f896 3623static int
e3bb37b5 3624check_qword_reg (void)
29b0f896
AM		 3625{
3626 int op;
252b5132 3627
29b0f896
AM		 3628 for (op = i.operands; --op >= 0; )
3629 /* Reject eight bit registers, except where the template requires
3630 them. (eg. movzb) */
40fb9820
L		 3631 if (i.types[op].bitfield.reg8
3632 && (i.tm.operand_types[op].bitfield.reg16
3633 || i.tm.operand_types[op].bitfield.reg32
3634 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3635 {
a540244d
L		 3636 as_bad (_("`%s%s' not allowed with `%s%c'"),
3637 register_prefix,
29b0f896
AM		 3638 i.op[op].regs->reg_name,
3639 i.tm.name,
3640 i.suffix);
3641 return 0;
3642 }
3643 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 3644 else if ((i.types[op].bitfield.reg16
3645 || i.types[op].bitfield.reg32)
3646 && (i.tm.operand_types[op].bitfield.reg32
3647 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3648 {
3649 /* Prohibit these changes in the 64bit mode, since the
3650 lowering is more complicated. */
34828aad
L		 3651 if (intel_syntax
3652 && i.tm.base_opcode == 0xf20f2d
40fb9820 3653 && !i.types[0].bitfield.regxmm)
34828aad
L		 3654 {
3655 /* cvtsd2si converts QWORD memory to Reg32. We don't want
3656 REX byte. */
3657 i.suffix = LONG_MNEM_SUFFIX;
3658 }
3659 else
3660 {
3661 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3662 register_prefix, i.op[op].regs->reg_name,
3663 i.suffix);
3664 return 0;
3665 }
252b5132 3666 }
29b0f896
AM		 3667 return 1;
3668}
252b5132 3669
29b0f896 3670static int
e3bb37b5 3671check_word_reg (void)
29b0f896
AM		 3672{
3673 int op;
3674 for (op = i.operands; --op >= 0;)
3675 /* Reject eight bit registers, except where the template requires
3676 them. (eg. movzb) */
40fb9820
L		 3677 if (i.types[op].bitfield.reg8
3678 && (i.tm.operand_types[op].bitfield.reg16
3679 || i.tm.operand_types[op].bitfield.reg32
3680 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3681 {
a540244d
L		 3682 as_bad (_("`%s%s' not allowed with `%s%c'"),
3683 register_prefix,
29b0f896
AM		 3684 i.op[op].regs->reg_name,
3685 i.tm.name,
3686 i.suffix);
3687 return 0;
3688 }
3689 /* Warn if the e prefix on a general reg is present. */
3690 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3691 && i.types[op].bitfield.reg32
3692 && (i.tm.operand_types[op].bitfield.reg16
3693 || i.tm.operand_types[op].bitfield.acc))
252b5132 3694 {
29b0f896
AM		 3695 /* Prohibit these changes in the 64bit mode, since the
3696 lowering is more complicated. */
3697 if (flag_code == CODE_64BIT)
252b5132 3698 {
2ca3ace5
L		 3699 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3700 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3701 i.suffix);
3702 return 0;
252b5132 3703 }
29b0f896
AM		 3704 else
3705#if REGISTER_WARNINGS
a540244d
L		 3706 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3707 register_prefix,
29b0f896 3708 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 3709 register_prefix,
29b0f896
AM		 3710 i.op[op].regs->reg_name,
3711 i.suffix);
3712#endif
3713 }
3714 return 1;
3715}
252b5132 3716
29b0f896 3717static int
40fb9820 3718update_imm (unsigned int j)
29b0f896 3719{
40fb9820
L		 3720 i386_operand_type overlap;
3721
3722 overlap = operand_type_biop (i.types[j], i.tm.operand_types[j],
3723 and);
3724 if ((overlap.bitfield.imm8
3725 || overlap.bitfield.imm8s
3726 || overlap.bitfield.imm16
3727 || overlap.bitfield.imm32
3728 || overlap.bitfield.imm32s
3729 || overlap.bitfield.imm64)
3730 && memcmp (&overlap, &imm8, sizeof (overlap))
3731 && memcmp (&overlap, &imm8s, sizeof (overlap))
3732 && memcmp (&overlap, &imm16, sizeof (overlap))
3733 && memcmp (&overlap, &imm32, sizeof (overlap))
3734 && memcmp (&overlap, &imm32s, sizeof (overlap))
3735 && memcmp (&overlap, &imm64, sizeof (overlap)))
29b0f896
AM		 3736 {
3737 if (i.suffix)
3738 {
40fb9820
L		 3739 i386_operand_type temp;
3740
3741 memset (&temp, 0, sizeof (temp));
3742 if (i.suffix == BYTE_MNEM_SUFFIX)
3743 {
3744 temp.bitfield.imm8 = overlap.bitfield.imm8;
3745 temp.bitfield.imm8s = overlap.bitfield.imm8s;
3746 }
3747 else if (i.suffix == WORD_MNEM_SUFFIX)
3748 temp.bitfield.imm16 = overlap.bitfield.imm16;
3749 else if (i.suffix == QWORD_MNEM_SUFFIX)
3750 {
3751 temp.bitfield.imm64 = overlap.bitfield.imm64;
3752 temp.bitfield.imm32s = overlap.bitfield.imm32s;
3753 }
3754 else
3755 temp.bitfield.imm32 = overlap.bitfield.imm32;
3756 overlap = temp;
29b0f896 3757 }
40fb9820
L		 3758 else if (memcmp (&overlap, &imm16_32_32s, sizeof (overlap)) == 0
3759 || memcmp (&overlap, &imm16_32, sizeof (overlap)) == 0
3760 || memcmp (&overlap, &imm16_32s, sizeof (overlap)) == 0)
29b0f896 3761 {
40fb9820
L		 3762 memset (&overlap, 0, sizeof (overlap));
3763 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3764 overlap.bitfield.imm16 = 1;
3765 else
3766 overlap.bitfield.imm32s = 1;
29b0f896 3767 }
40fb9820
L		 3768 if (memcmp (&overlap, &imm8, sizeof (overlap))
3769 && memcmp (&overlap, &imm8s, sizeof (overlap))
3770 && memcmp (&overlap, &imm16, sizeof (overlap))
3771 && memcmp (&overlap, &imm32, sizeof (overlap))
3772 && memcmp (&overlap, &imm32s, sizeof (overlap))
3773 && memcmp (&overlap, &imm64, sizeof (overlap)))
29b0f896 3774 {
4eed87de
AM		 3775 as_bad (_("no instruction mnemonic suffix given; "
3776 "can't determine immediate size"));
29b0f896
AM		 3777 return 0;
3778 }
3779 }
40fb9820 3780 i.types[j] = overlap;
29b0f896 3781
40fb9820
L		 3782 return 1;
3783}
3784
3785static int
3786finalize_imm (void)
3787{
3788 unsigned int j;
29b0f896 3789
40fb9820
L		 3790 for (j = 0; j < 2; j++)
3791 if (update_imm (j) == 0)
3792 return 0;
3793
3794 i.types[2] = operand_type_biop (i.types[2], i.tm.operand_types[2],
3795 and);
3796 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 3797
3798 return 1;
3799}
3800
3801static int
e3bb37b5 3802process_operands (void)
29b0f896
AM		 3803{
3804 /* Default segment register this instruction will use for memory
3805 accesses. 0 means unknown. This is only for optimizing out
3806 unnecessary segment overrides. */
3807 const seg_entry *default_seg = 0;
3808
3809 /* The imul $imm, %reg instruction is converted into
3810 imul $imm, %reg, %reg, and the clr %reg instruction
3811 is converted into xor %reg, %reg. */
40fb9820 3812 if (i.tm.opcode_modifier.regkludge)
29b0f896 3813 {
40fb9820 3814 if (i.tm.cpu_flags.bitfield.cpusse4_1)
42903f7f
L		 3815 {
3816 /* The first operand in instruction blendvpd, blendvps and
3817 pblendvb in SSE4.1 is implicit and must be xmm0. */
3818 assert (i.operands == 3
3819 && i.reg_operands >= 2
40fb9820 3820 && memcmp (&i.types[0], &regxmm, sizeof (regxmm)) == 0);
42903f7f
L		 3821 if (i.op[0].regs->reg_num != 0)
3822 {
3823 if (intel_syntax)
3824 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
3825 i.tm.name, register_prefix);
3826 else
3827 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
3828 i.tm.name, register_prefix);
3829 return 0;
3830 }
3831 i.op[0] = i.op[1];
3832 i.op[1] = i.op[2];
3833 i.types[0] = i.types[1];
3834 i.types[1] = i.types[2];
3835 i.operands--;
3836 i.reg_operands--;
3837
3838 /* We need to adjust fields in i.tm since they are used by
3839 build_modrm_byte. */
3840 i.tm.operand_types [0] = i.tm.operand_types [1];
3841 i.tm.operand_types [1] = i.tm.operand_types [2];
3842 i.tm.operands--;
3843 }
3844 else
3845 {
40fb9820
L		 3846 unsigned int first_reg_op;
3847
3848 if (operand_type_check (i.types[0], reg))
3849 first_reg_op = 0;
3850 else
3851 first_reg_op = 1;
42903f7f
L		 3852 /* Pretend we saw the extra register operand. */
3853 assert (i.reg_operands == 1
3854 && i.op[first_reg_op + 1].regs == 0);
3855 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3856 i.types[first_reg_op + 1] = i.types[first_reg_op];
3857 i.operands++;
3858 i.reg_operands++;
3859 }
29b0f896
AM		 3860 }
3861
40fb9820 3862 if (i.tm.opcode_modifier.shortform)
29b0f896 3863 {
40fb9820
L		 3864 if (i.types[0].bitfield.sreg2
3865 || i.types[0].bitfield.sreg3)
29b0f896 3866 {
4eed87de
AM		 3867 if (i.tm.base_opcode == POP_SEG_SHORT
3868 && i.op[0].regs->reg_num == 1)
29b0f896 3869 {
4eed87de
AM		 3870 as_bad (_("you can't `pop %%cs'"));
3871 return 0;
29b0f896 3872 }
4eed87de
AM		 3873 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3874 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 3875 i.rex |= REX_B;
4eed87de
AM		 3876 }
3877 else
3878 {
3879 /* The register or float register operand is in operand 0 or 1. */
40fb9820
L		 3880 unsigned int op;
3881
3882 if (i.types[0].bitfield.floatreg
3883 || operand_type_check (i.types[0], reg))
3884 op = 0;
3885 else
3886 op = 1;
4eed87de
AM		 3887 /* Register goes in low 3 bits of opcode. */
3888 i.tm.base_opcode |= i.op[op].regs->reg_num;
3889 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3890 i.rex |= REX_B;
40fb9820 3891 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 3892 {
4eed87de
AM		 3893 /* Warn about some common errors, but press on regardless.
3894 The first case can be generated by gcc (<= 2.8.1). */
3895 if (i.operands == 2)
3896 {
3897 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 3898 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
3899 register_prefix, i.op[1].regs->reg_name,
3900 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 3901 }
3902 else
3903 {
3904 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 3905 as_warn (_("translating to `%s %s%s'"), i.tm.name,
3906 register_prefix, i.op[0].regs->reg_name);
4eed87de 3907 }
29b0f896
AM		 3908 }
3909 }
3910 }
40fb9820 3911 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 3912 {
3913 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3914 must be put into the modrm byte). Now, we make the modrm and
3915 index base bytes based on all the info we've collected. */
29b0f896
AM		 3916
3917 default_seg = build_modrm_byte ();
3918 }
8a2ed489 3919 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 3920 {
3921 default_seg = &ds;
3922 }
40fb9820 3923 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 3924 {
3925 /* For the string instructions that allow a segment override
3926 on one of their operands, the default segment is ds. */
3927 default_seg = &ds;
3928 }
3929
75178d9d
L		 3930 if (i.tm.base_opcode == 0x8d /* lea */
3931 && i.seg[0]
3932 && !quiet_warnings)
30123838 3933 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3934
3935 /* If a segment was explicitly specified, and the specified segment
3936 is not the default, use an opcode prefix to select it. If we
3937 never figured out what the default segment is, then default_seg
3938 will be zero at this point, and the specified segment prefix will
3939 always be used. */
29b0f896
AM		 3940 if ((i.seg[0]) && (i.seg[0] != default_seg))
3941 {
3942 if (!add_prefix (i.seg[0]->seg_prefix))
3943 return 0;
3944 }
3945 return 1;
3946}
3947
3948static const seg_entry *
e3bb37b5 3949build_modrm_byte (void)
29b0f896
AM		 3950{
3951 const seg_entry *default_seg = 0;
3952
3953 /* i.reg_operands MUST be the number of real register operands;
3954 implicit registers do not count. */
3955 if (i.reg_operands == 2)
3956 {
3957 unsigned int source, dest;
cab737b9
L		 3958
3959 switch (i.operands)
3960 {
3961 case 2:
3962 source = 0;
3963 break;
3964 case 3:
c81128dc
L		 3965 /* When there are 3 operands, one of them may be immediate,
3966 which may be the first or the last operand. Otherwise,
3967 the first operand must be shift count register (cl). */
3968 assert (i.imm_operands == 1
3969 || (i.imm_operands == 0
40fb9820
L		 3970 && i.types[0].bitfield.shiftcount));
3971 if (operand_type_check (i.types[0], imm)
3972 || i.types[0].bitfield.shiftcount)
3973 source = 1;
3974 else
3975 source = 0;
cab737b9
L		 3976 break;
3977 case 4:
3978 /* When there are 4 operands, the first two must be immediate
3979 operands. The source operand will be the 3rd one. */
3980 assert (i.imm_operands == 2
40fb9820
L		 3981 && operand_type_check (i.types[0], imm)
3982 && operand_type_check (i.types[1], imm));
cab737b9
L		 3983 source = 2;
3984 break;
3985 default:
3986 abort ();
3987 }
3988
29b0f896
AM		 3989 dest = source + 1;
3990
3991 i.rm.mode = 3;
3992 /* One of the register operands will be encoded in the i.tm.reg
3993 field, the other in the combined i.tm.mode and i.tm.regmem
3994 fields. If no form of this instruction supports a memory
3995 destination operand, then we assume the source operand may
3996 sometimes be a memory operand and so we need to store the
3997 destination in the i.rm.reg field. */
40fb9820
L		 3998 if (!i.tm.operand_types[dest].bitfield.regmem
3999 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 4000 {
4001 i.rm.reg = i.op[dest].regs->reg_num;
4002 i.rm.regmem = i.op[source].regs->reg_num;
4003 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4004 i.rex |= REX_R;
29b0f896 4005 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4006 i.rex |= REX_B;
29b0f896
AM		 4007 }
4008 else
4009 {
4010 i.rm.reg = i.op[source].regs->reg_num;
4011 i.rm.regmem = i.op[dest].regs->reg_num;
4012 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4013 i.rex |= REX_B;
29b0f896 4014 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4015 i.rex |= REX_R;
29b0f896 4016 }
161a04f6 4017 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 4018 {
40fb9820
L		 4019 if (!i.types[0].bitfield.control
4020 && !i.types[1].bitfield.control)
c4a530c5 4021 abort ();
161a04f6 4022 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 4023 add_prefix (LOCK_PREFIX_OPCODE);
4024 }
29b0f896
AM		 4025 }
4026 else
4027 { /* If it's not 2 reg operands... */
4028 if (i.mem_operands)
4029 {
4030 unsigned int fake_zero_displacement = 0;
99018f42 4031 unsigned int op;
4eed87de 4032
99018f42 4033 for (op = 0; op < i.operands; op++)
40fb9820 4034 if (operand_type_check (i.types[op], anymem))
99018f42
L		 4035 break;
4036 assert (op < i.operands);
29b0f896
AM		 4037
4038 default_seg = &ds;
4039
4040 if (i.base_reg == 0)
4041 {
4042 i.rm.mode = 0;
4043 if (!i.disp_operands)
4044 fake_zero_displacement = 1;
4045 if (i.index_reg == 0)
4046 {
4047 /* Operand is just <disp> */
20f0a1fc 4048 if (flag_code == CODE_64BIT)
29b0f896
AM		 4049 {
4050 /* 64bit mode overwrites the 32bit absolute
4051 addressing by RIP relative addressing and
4052 absolute addressing is encoded by one of the
4053 redundant SIB forms. */
4054 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4055 i.sib.base = NO_BASE_REGISTER;
4056 i.sib.index = NO_INDEX_REGISTER;
fc225355 4057 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 4058 ? disp32s : disp32);
20f0a1fc 4059 }
fc225355
L		 4060 else if ((flag_code == CODE_16BIT)
4061 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 4062 {
4063 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 4064 i.types[op] = disp16;
20f0a1fc
NC		 4065 }
4066 else
4067 {
4068 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 4069 i.types[op] = disp32;
29b0f896
AM		 4070 }
4071 }
4072 else /* !i.base_reg && i.index_reg */
4073 {
4074 i.sib.index = i.index_reg->reg_num;
4075 i.sib.base = NO_BASE_REGISTER;
4076 i.sib.scale = i.log2_scale_factor;
4077 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 4078 i.types[op].bitfield.disp8 = 0;
4079 i.types[op].bitfield.disp16 = 0;
4080 i.types[op].bitfield.disp64 = 0;
29b0f896 4081 if (flag_code != CODE_64BIT)
40fb9820
L		 4082 {
4083 /* Must be 32 bit */
4084 i.types[op].bitfield.disp32 = 1;
4085 i.types[op].bitfield.disp32s = 0;
4086 }
29b0f896 4087 else
40fb9820
L		 4088 {
4089 i.types[op].bitfield.disp32 = 0;
4090 i.types[op].bitfield.disp32s = 1;
4091 }
29b0f896 4092 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4093 i.rex |= REX_X;
29b0f896
AM		 4094 }
4095 }
4096 /* RIP addressing for 64bit mode. */
40fb9820
L		 4097 else if (memcmp (&i.base_reg->reg_type, &baseindex,
4098 sizeof (baseindex)) == 0)
29b0f896
AM		 4099 {
4100 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 4101 i.types[op].bitfield.disp8 = 0;
4102 i.types[op].bitfield.disp16 = 0;
4103 i.types[op].bitfield.disp32 = 0;
4104 i.types[op].bitfield.disp32s = 1;
4105 i.types[op].bitfield.disp64 = 0;
71903a11 4106 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 4107 if (! i.disp_operands)
4108 fake_zero_displacement = 1;
29b0f896 4109 }
40fb9820 4110 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 4111 {
4112 switch (i.base_reg->reg_num)
4113 {
4114 case 3: /* (%bx) */
4115 if (i.index_reg == 0)
4116 i.rm.regmem = 7;
4117 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4118 i.rm.regmem = i.index_reg->reg_num - 6;
4119 break;
4120 case 5: /* (%bp) */
4121 default_seg = &ss;
4122 if (i.index_reg == 0)
4123 {
4124 i.rm.regmem = 6;
40fb9820 4125 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 4126 {
4127 /* fake (%bp) into 0(%bp) */
40fb9820 4128 i.types[op].bitfield.disp8 = 1;
252b5132 4129 fake_zero_displacement = 1;
29b0f896
AM		 4130 }
4131 }
4132 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4133 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4134 break;
4135 default: /* (%si) -> 4 or (%di) -> 5 */
4136 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4137 }
4138 i.rm.mode = mode_from_disp_size (i.types[op]);
4139 }
4140 else /* i.base_reg and 32/64 bit mode */
4141 {
4142 if (flag_code == CODE_64BIT
40fb9820
L		 4143 && operand_type_check (i.types[op], disp))
4144 {
4145 i386_operand_type temp;
4146
4147 memset (&temp, 0, sizeof (temp));
4148 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4149 i.types[op] = temp;
4150 if (i.prefix[ADDR_PREFIX] == 0)
4151 i.types[op].bitfield.disp32s = 1;
4152 else
4153 i.types[op].bitfield.disp32 = 1;
4154 }
20f0a1fc 4155
29b0f896
AM		 4156 i.rm.regmem = i.base_reg->reg_num;
4157 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 4158 i.rex |= REX_B;
29b0f896
AM		 4159 i.sib.base = i.base_reg->reg_num;
4160 /* x86-64 ignores REX prefix bit here to avoid decoder
4161 complications. */
4162 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4163 {
4164 default_seg = &ss;
4165 if (i.disp_operands == 0)
4166 {
4167 fake_zero_displacement = 1;
40fb9820 4168 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 4169 }
4170 }
4171 else if (i.base_reg->reg_num == ESP_REG_NUM)
4172 {
4173 default_seg = &ss;
4174 }
4175 i.sib.scale = i.log2_scale_factor;
4176 if (i.index_reg == 0)
4177 {
4178 /* <disp>(%esp) becomes two byte modrm with no index
4179 register. We've already stored the code for esp
4180 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4181 Any base register besides %esp will not use the
4182 extra modrm byte. */
4183 i.sib.index = NO_INDEX_REGISTER;
4184#if !SCALE1_WHEN_NO_INDEX
4185 /* Another case where we force the second modrm byte. */
4186 if (i.log2_scale_factor)
4187 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 4188#endif
29b0f896
AM		 4189 }
4190 else
4191 {
4192 i.sib.index = i.index_reg->reg_num;
4193 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4194 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4195 i.rex |= REX_X;
29b0f896 4196 }
67a4f2b7
AO		 4197
4198 if (i.disp_operands
4199 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4200 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4201 i.rm.mode = 0;
4202 else
4203 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 4204 }
252b5132 4205
29b0f896
AM		 4206 if (fake_zero_displacement)
4207 {
4208 /* Fakes a zero displacement assuming that i.types[op]
4209 holds the correct displacement size. */
4210 expressionS *exp;
4211
4212 assert (i.op[op].disps == 0);
4213 exp = &disp_expressions[i.disp_operands++];
4214 i.op[op].disps = exp;
4215 exp->X_op = O_constant;
4216 exp->X_add_number = 0;
4217 exp->X_add_symbol = (symbolS *) 0;
4218 exp->X_op_symbol = (symbolS *) 0;
4219 }
4220 }
252b5132 4221
29b0f896
AM		 4222 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4223 (if any) based on i.tm.extension_opcode. Again, we must be
4224 careful to make sure that segment/control/debug/test/MMX
4225 registers are coded into the i.rm.reg field. */
4226 if (i.reg_operands)
4227 {
99018f42
L		 4228 unsigned int op;
4229
4230 for (op = 0; op < i.operands; op++)
40fb9820
L		 4231 if (i.types[op].bitfield.reg8
4232 || i.types[op].bitfield.reg16
4233 || i.types[op].bitfield.reg32
4234 || i.types[op].bitfield.reg64
4235 || i.types[op].bitfield.regmmx
4236 || i.types[op].bitfield.regxmm
4237 || i.types[op].bitfield.sreg2
4238 || i.types[op].bitfield.sreg3
4239 || i.types[op].bitfield.control
4240 || i.types[op].bitfield.debug
4241 || i.types[op].bitfield.test)
99018f42
L		 4242 break;
4243 assert (op < i.operands);
4244
29b0f896
AM		 4245 /* If there is an extension opcode to put here, the register
4246 number must be put into the regmem field. */
4247 if (i.tm.extension_opcode != None)
4248 {
4249 i.rm.regmem = i.op[op].regs->reg_num;
4250 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4251 i.rex |= REX_B;
29b0f896
AM		 4252 }
4253 else
4254 {
4255 i.rm.reg = i.op[op].regs->reg_num;
4256 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4257 i.rex |= REX_R;
29b0f896 4258 }
252b5132 4259
29b0f896
AM		 4260 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4261 must set it to 3 to indicate this is a register operand
4262 in the regmem field. */
4263 if (!i.mem_operands)
4264 i.rm.mode = 3;
4265 }
252b5132 4266
29b0f896
AM		 4267 /* Fill in i.rm.reg field with extension opcode (if any). */
4268 if (i.tm.extension_opcode != None)
4269 i.rm.reg = i.tm.extension_opcode;
4270 }
4271 return default_seg;
4272}
252b5132 4273
29b0f896 4274static void
e3bb37b5 4275output_branch (void)
29b0f896
AM		 4276{
4277 char *p;
4278 int code16;
4279 int prefix;
4280 relax_substateT subtype;
4281 symbolS *sym;
4282 offsetT off;
4283
4284 code16 = 0;
4285 if (flag_code == CODE_16BIT)
4286 code16 = CODE16;
4287
4288 prefix = 0;
4289 if (i.prefix[DATA_PREFIX] != 0)
252b5132 4290 {
29b0f896
AM		 4291 prefix = 1;
4292 i.prefixes -= 1;
4293 code16 ^= CODE16;
252b5132 4294 }
29b0f896
AM		 4295 /* Pentium4 branch hints. */
4296 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4297 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 4298 {
29b0f896
AM		 4299 prefix++;
4300 i.prefixes--;
4301 }
4302 if (i.prefix[REX_PREFIX] != 0)
4303 {
4304 prefix++;
4305 i.prefixes--;
2f66722d
AM		 4306 }
4307
29b0f896
AM		 4308 if (i.prefixes != 0 && !intel_syntax)
4309 as_warn (_("skipping prefixes on this instruction"));
4310
4311 /* It's always a symbol; End frag & setup for relax.
4312 Make sure there is enough room in this frag for the largest
4313 instruction we may generate in md_convert_frag. This is 2
4314 bytes for the opcode and room for the prefix and largest
4315 displacement. */
4316 frag_grow (prefix + 2 + 4);
4317 /* Prefix and 1 opcode byte go in fr_fix. */
4318 p = frag_more (prefix + 1);
4319 if (i.prefix[DATA_PREFIX] != 0)
4320 *p++ = DATA_PREFIX_OPCODE;
4321 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
4322 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
4323 *p++ = i.prefix[SEG_PREFIX];
4324 if (i.prefix[REX_PREFIX] != 0)
4325 *p++ = i.prefix[REX_PREFIX];
4326 *p = i.tm.base_opcode;
4327
4328 if ((unsigned char) *p == JUMP_PC_RELATIVE)
4329 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 4330 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 4331 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
4332 else
4333 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
4334 subtype |= code16;
3e73aa7c 4335
29b0f896
AM		 4336 sym = i.op[0].disps->X_add_symbol;
4337 off = i.op[0].disps->X_add_number;
3e73aa7c 4338
29b0f896
AM		 4339 if (i.op[0].disps->X_op != O_constant
4340 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 4341 {
29b0f896
AM		 4342 /* Handle complex expressions. */
4343 sym = make_expr_symbol (i.op[0].disps);
4344 off = 0;
4345 }
3e73aa7c 4346
29b0f896
AM		 4347 /* 1 possible extra opcode + 4 byte displacement go in var part.
4348 Pass reloc in fr_var. */
4349 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
4350}
3e73aa7c 4351
29b0f896 4352static void
e3bb37b5 4353output_jump (void)
29b0f896
AM		 4354{
4355 char *p;
4356 int size;
3e02c1cc 4357 fixS *fixP;
29b0f896 4358
40fb9820 4359 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 4360 {
4361 /* This is a loop or jecxz type instruction. */
4362 size = 1;
4363 if (i.prefix[ADDR_PREFIX] != 0)
4364 {
4365 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
4366 i.prefixes -= 1;
4367 }
4368 /* Pentium4 branch hints. */
4369 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4370 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4371 {
4372 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
4373 i.prefixes--;
3e73aa7c
JH		 4374 }
4375 }
29b0f896
AM		 4376 else
4377 {
4378 int code16;
3e73aa7c 4379
29b0f896
AM		 4380 code16 = 0;
4381 if (flag_code == CODE_16BIT)
4382 code16 = CODE16;
3e73aa7c 4383
29b0f896
AM		 4384 if (i.prefix[DATA_PREFIX] != 0)
4385 {
4386 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
4387 i.prefixes -= 1;
4388 code16 ^= CODE16;
4389 }
252b5132 4390
29b0f896
AM		 4391 size = 4;
4392 if (code16)
4393 size = 2;
4394 }
9fcc94b6 4395
29b0f896
AM		 4396 if (i.prefix[REX_PREFIX] != 0)
4397 {
4398 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
4399 i.prefixes -= 1;
4400 }
252b5132 4401
29b0f896
AM		 4402 if (i.prefixes != 0 && !intel_syntax)
4403 as_warn (_("skipping prefixes on this instruction"));
e0890092 4404
29b0f896
AM		 4405 p = frag_more (1 + size);
4406 *p++ = i.tm.base_opcode;
e0890092 4407
3e02c1cc
AM		 4408 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4409 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
4410
4411 /* All jumps handled here are signed, but don't use a signed limit
4412 check for 32 and 16 bit jumps as we want to allow wrap around at
4413 4G and 64k respectively. */
4414 if (size == 1)
4415 fixP->fx_signed = 1;
29b0f896 4416}
e0890092 4417
29b0f896 4418static void
e3bb37b5 4419output_interseg_jump (void)
29b0f896
AM		 4420{
4421 char *p;
4422 int size;
4423 int prefix;
4424 int code16;
252b5132 4425
29b0f896
AM		 4426 code16 = 0;
4427 if (flag_code == CODE_16BIT)
4428 code16 = CODE16;
a217f122 4429
29b0f896
AM		 4430 prefix = 0;
4431 if (i.prefix[DATA_PREFIX] != 0)
4432 {
4433 prefix = 1;
4434 i.prefixes -= 1;
4435 code16 ^= CODE16;
4436 }
4437 if (i.prefix[REX_PREFIX] != 0)
4438 {
4439 prefix++;
4440 i.prefixes -= 1;
4441 }
252b5132 4442
29b0f896
AM		 4443 size = 4;
4444 if (code16)
4445 size = 2;
252b5132 4446
29b0f896
AM		 4447 if (i.prefixes != 0 && !intel_syntax)
4448 as_warn (_("skipping prefixes on this instruction"));
252b5132 4449
29b0f896
AM		 4450 /* 1 opcode; 2 segment; offset */
4451 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 4452
29b0f896
AM		 4453 if (i.prefix[DATA_PREFIX] != 0)
4454 *p++ = DATA_PREFIX_OPCODE;
252b5132 4455
29b0f896
AM		 4456 if (i.prefix[REX_PREFIX] != 0)
4457 *p++ = i.prefix[REX_PREFIX];
252b5132 4458
29b0f896
AM		 4459 *p++ = i.tm.base_opcode;
4460 if (i.op[1].imms->X_op == O_constant)
4461 {
4462 offsetT n = i.op[1].imms->X_add_number;
252b5132 4463
29b0f896
AM		 4464 if (size == 2
4465 && !fits_in_unsigned_word (n)
4466 && !fits_in_signed_word (n))
4467 {
4468 as_bad (_("16-bit jump out of range"));
4469 return;
4470 }
4471 md_number_to_chars (p, n, size);
4472 }
4473 else
4474 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4475 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
4476 if (i.op[0].imms->X_op != O_constant)
4477 as_bad (_("can't handle non absolute segment in `%s'"),
4478 i.tm.name);
4479 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
4480}
a217f122 4481
29b0f896 4482static void
e3bb37b5 4483output_insn (void)
29b0f896 4484{
2bbd9c25
JJ		 4485 fragS *insn_start_frag;
4486 offsetT insn_start_off;
4487
29b0f896
AM		 4488 /* Tie dwarf2 debug info to the address at the start of the insn.
4489 We can't do this after the insn has been output as the current
4490 frag may have been closed off. eg. by frag_var. */
4491 dwarf2_emit_insn (0);
4492
2bbd9c25
JJ		 4493 insn_start_frag = frag_now;
4494 insn_start_off = frag_now_fix ();
4495
29b0f896 4496 /* Output jumps. */
40fb9820 4497 if (i.tm.opcode_modifier.jump)
29b0f896 4498 output_branch ();
40fb9820
L		 4499 else if (i.tm.opcode_modifier.jumpbyte
4500 || i.tm.opcode_modifier.jumpdword)
29b0f896 4501 output_jump ();
40fb9820 4502 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 4503 output_interseg_jump ();
4504 else
4505 {
4506 /* Output normal instructions here. */
4507 char *p;
4508 unsigned char *q;
331d2d0d 4509 unsigned int prefix;
40fb9820 4510 int opc_3b;
252b5132 4511
42903f7f 4512 /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and
381d071f
L		 4513 SSE4 instructions have 3 bytes. We may use one more higher
4514 byte to specify a prefix the instruction requires. Exclude
4515 instructions which are in both SSE4 and ABM. */
40fb9820
L		 4516 opc_3b = ((i.tm.cpu_flags.bitfield.cpussse3
4517 || i.tm.cpu_flags.bitfield.cpusse4_1
4518 || i.tm.cpu_flags.bitfield.cpusse4_2)
4519 && !i.tm.cpu_flags.bitfield.cpuabm);
4520 if (opc_3b)
bc4bd9ab 4521 {
331d2d0d
L		 4522 if (i.tm.base_opcode & 0xff000000)
4523 {
4524 prefix = (i.tm.base_opcode >> 24) & 0xff;
4525 goto check_prefix;
4526 }
4527 }
4528 else if ((i.tm.base_opcode & 0xff0000) != 0)
4529 {
4530 prefix = (i.tm.base_opcode >> 16) & 0xff;
40fb9820 4531 if (i.tm.cpu_flags.bitfield.cpupadlock)
bc4bd9ab 4532 {
64e74474 4533 check_prefix:
bc4bd9ab
MK		 4534 if (prefix != REPE_PREFIX_OPCODE
4535 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
4536 add_prefix (prefix);
4537 }
4538 else
331d2d0d 4539 add_prefix (prefix);
0f10071e 4540 }
252b5132 4541
29b0f896
AM		 4542 /* The prefix bytes. */
4543 for (q = i.prefix;
4544 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
4545 q++)
4546 {
4547 if (*q)
4548 {
4549 p = frag_more (1);
4550 md_number_to_chars (p, (valueT) *q, 1);
4551 }
4552 }
252b5132 4553
29b0f896
AM		 4554 /* Now the opcode; be careful about word order here! */
4555 if (fits_in_unsigned_byte (i.tm.base_opcode))
4556 {
4557 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
4558 }
4559 else
4560 {
40fb9820 4561 if (opc_3b)
331d2d0d
L		 4562 {
4563 p = frag_more (3);
4564 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4565 }
4566 else
4567 p = frag_more (2);
0f10071e 4568
29b0f896
AM		 4569 /* Put out high byte first: can't use md_number_to_chars! */
4570 *p++ = (i.tm.base_opcode >> 8) & 0xff;
4571 *p = i.tm.base_opcode & 0xff;
4572 }
3e73aa7c 4573
29b0f896 4574 /* Now the modrm byte and sib byte (if present). */
40fb9820 4575 if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4576 {
4577 p = frag_more (1);
4578 md_number_to_chars (p,
4579 (valueT) (i.rm.regmem << 0
4580 | i.rm.reg << 3
4581 | i.rm.mode << 6),
4582 1);
4583 /* If i.rm.regmem == ESP (4)
4584 && i.rm.mode != (Register mode)
4585 && not 16 bit
4586 ==> need second modrm byte. */
4587 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
4588 && i.rm.mode != 3
40fb9820 4589 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
29b0f896
AM		 4590 {
4591 p = frag_more (1);
4592 md_number_to_chars (p,
4593 (valueT) (i.sib.base << 0
4594 | i.sib.index << 3
4595 | i.sib.scale << 6),
4596 1);
4597 }
4598 }
3e73aa7c 4599
29b0f896 4600 if (i.disp_operands)
2bbd9c25 4601 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 4602
29b0f896 4603 if (i.imm_operands)
2bbd9c25 4604 output_imm (insn_start_frag, insn_start_off);
29b0f896 4605 }
252b5132 4606
29b0f896
AM		 4607#ifdef DEBUG386
4608 if (flag_debug)
4609 {
7b81dfbb 4610 pi ("" /*line*/, &i);
29b0f896
AM		 4611 }
4612#endif /* DEBUG386 */
4613}
252b5132 4614
e205caa7
L		 4615/* Return the size of the displacement operand N. */
4616
4617static int
4618disp_size (unsigned int n)
4619{
4620 int size = 4;
40fb9820
L		 4621 if (i.types[n].bitfield.disp64)
4622 size = 8;
4623 else if (i.types[n].bitfield.disp8)
4624 size = 1;
4625 else if (i.types[n].bitfield.disp16)
4626 size = 2;
e205caa7
L		 4627 return size;
4628}
4629
4630/* Return the size of the immediate operand N. */
4631
4632static int
4633imm_size (unsigned int n)
4634{
4635 int size = 4;
40fb9820
L		 4636 if (i.types[n].bitfield.imm64)
4637 size = 8;
4638 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
4639 size = 1;
4640 else if (i.types[n].bitfield.imm16)
4641 size = 2;
e205caa7
L		 4642 return size;
4643}
4644
29b0f896 4645static void
64e74474 4646output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4647{
4648 char *p;
4649 unsigned int n;
252b5132 4650
29b0f896
AM		 4651 for (n = 0; n < i.operands; n++)
4652 {
40fb9820 4653 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 4654 {
4655 if (i.op[n].disps->X_op == O_constant)
4656 {
e205caa7 4657 int size = disp_size (n);
29b0f896 4658 offsetT val;
252b5132 4659
29b0f896
AM		 4660 val = offset_in_range (i.op[n].disps->X_add_number,
4661 size);
4662 p = frag_more (size);
4663 md_number_to_chars (p, val, size);
4664 }
4665 else
4666 {
f86103b7 4667 enum bfd_reloc_code_real reloc_type;
e205caa7 4668 int size = disp_size (n);
40fb9820 4669 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 4670 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4671
e205caa7 4672 /* We can't have 8 bit displacement here. */
40fb9820 4673 assert (!i.types[n].bitfield.disp8);
e205caa7 4674
29b0f896
AM		 4675 /* The PC relative address is computed relative
4676 to the instruction boundary, so in case immediate
4677 fields follows, we need to adjust the value. */
4678 if (pcrel && i.imm_operands)
4679 {
29b0f896 4680 unsigned int n1;
e205caa7 4681 int sz = 0;
252b5132 4682
29b0f896 4683 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 4684 if (operand_type_check (i.types[n1], imm))
252b5132 4685 {
e205caa7
L		 4686 /* Only one immediate is allowed for PC
4687 relative address. */
4688 assert (sz == 0);
4689 sz = imm_size (n1);
4690 i.op[n].disps->X_add_number -= sz;
252b5132 4691 }
29b0f896 4692 /* We should find the immediate. */
e205caa7 4693 assert (sz != 0);
29b0f896 4694 }
520dc8e8 4695
29b0f896 4696 p = frag_more (size);
2bbd9c25 4697 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4698 if (GOT_symbol
2bbd9c25 4699 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4700 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4701 || reloc_type == BFD_RELOC_X86_64_32S
4702 || (reloc_type == BFD_RELOC_64
4703 && object_64bit))
d6ab8113
JB		 4704 && (i.op[n].disps->X_op == O_symbol
4705 || (i.op[n].disps->X_op == O_add
4706 && ((symbol_get_value_expression
4707 (i.op[n].disps->X_op_symbol)->X_op)
4708 == O_subtract))))
4709 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4710 {
4711 offsetT add;
4712
4713 if (insn_start_frag == frag_now)
4714 add = (p - frag_now->fr_literal) - insn_start_off;
4715 else
4716 {
4717 fragS *fr;
4718
4719 add = insn_start_frag->fr_fix - insn_start_off;
4720 for (fr = insn_start_frag->fr_next;
4721 fr && fr != frag_now; fr = fr->fr_next)
4722 add += fr->fr_fix;
4723 add += p - frag_now->fr_literal;
4724 }
4725
4fa24527 4726 if (!object_64bit)
7b81dfbb
AJ		 4727 {
4728 reloc_type = BFD_RELOC_386_GOTPC;
4729 i.op[n].imms->X_add_number += add;
4730 }
4731 else if (reloc_type == BFD_RELOC_64)
4732 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4733 else
7b81dfbb
AJ		 4734 /* Don't do the adjustment for x86-64, as there
4735 the pcrel addressing is relative to the _next_
4736 insn, and that is taken care of in other code. */
d6ab8113 4737 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4738 }
062cd5e7 4739 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4740 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4741 }
4742 }
4743 }
4744}
252b5132 4745
29b0f896 4746static void
64e74474 4747output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4748{
4749 char *p;
4750 unsigned int n;
252b5132 4751
29b0f896
AM		 4752 for (n = 0; n < i.operands; n++)
4753 {
40fb9820 4754 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 4755 {
4756 if (i.op[n].imms->X_op == O_constant)
4757 {
e205caa7 4758 int size = imm_size (n);
29b0f896 4759 offsetT val;
b4cac588 4760
29b0f896
AM		 4761 val = offset_in_range (i.op[n].imms->X_add_number,
4762 size);
4763 p = frag_more (size);
4764 md_number_to_chars (p, val, size);
4765 }
4766 else
4767 {
4768 /* Not absolute_section.
4769 Need a 32-bit fixup (don't support 8bit
4770 non-absolute imms). Try to support other
4771 sizes ... */
f86103b7 4772 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 4773 int size = imm_size (n);
4774 int sign;
29b0f896 4775
40fb9820 4776 if (i.types[n].bitfield.imm32s
a7d61044 4777 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 4778 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 4779 sign = 1;
e205caa7
L		 4780 else
4781 sign = 0;
520dc8e8 4782
29b0f896
AM		 4783 p = frag_more (size);
4784 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4785
2bbd9c25
JJ		 4786 /* This is tough to explain. We end up with this one if we
4787 * have operands that look like
4788 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4789 * obtain the absolute address of the GOT, and it is strongly
4790 * preferable from a performance point of view to avoid using
4791 * a runtime relocation for this. The actual sequence of
4792 * instructions often look something like:
4793 *
4794 * call .L66
4795 * .L66:
4796 * popl %ebx
4797 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4798 *
4799 * The call and pop essentially return the absolute address
4800 * of the label .L66 and store it in %ebx. The linker itself
4801 * will ultimately change the first operand of the addl so
4802 * that %ebx points to the GOT, but to keep things simple, the
4803 * .o file must have this operand set so that it generates not
4804 * the absolute address of .L66, but the absolute address of
4805 * itself. This allows the linker itself simply treat a GOTPC
4806 * relocation as asking for a pcrel offset to the GOT to be
4807 * added in, and the addend of the relocation is stored in the
4808 * operand field for the instruction itself.
4809 *
4810 * Our job here is to fix the operand so that it would add
4811 * the correct offset so that %ebx would point to itself. The
4812 * thing that is tricky is that .-.L66 will point to the
4813 * beginning of the instruction, so we need to further modify
4814 * the operand so that it will point to itself. There are
4815 * other cases where you have something like:
4816 *
4817 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4818 *
4819 * and here no correction would be required. Internally in
4820 * the assembler we treat operands of this form as not being
4821 * pcrel since the '.' is explicitly mentioned, and I wonder
4822 * whether it would simplify matters to do it this way. Who
4823 * knows. In earlier versions of the PIC patches, the
4824 * pcrel_adjust field was used to store the correction, but
4825 * since the expression is not pcrel, I felt it would be
4826 * confusing to do it this way. */
4827
d6ab8113 4828 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4829 || reloc_type == BFD_RELOC_X86_64_32S
4830 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4831 && GOT_symbol
4832 && GOT_symbol == i.op[n].imms->X_add_symbol
4833 && (i.op[n].imms->X_op == O_symbol
4834 || (i.op[n].imms->X_op == O_add
4835 && ((symbol_get_value_expression
4836 (i.op[n].imms->X_op_symbol)->X_op)
4837 == O_subtract))))
4838 {
2bbd9c25
JJ		 4839 offsetT add;
4840
4841 if (insn_start_frag == frag_now)
4842 add = (p - frag_now->fr_literal) - insn_start_off;
4843 else
4844 {
4845 fragS *fr;
4846
4847 add = insn_start_frag->fr_fix - insn_start_off;
4848 for (fr = insn_start_frag->fr_next;
4849 fr && fr != frag_now; fr = fr->fr_next)
4850 add += fr->fr_fix;
4851 add += p - frag_now->fr_literal;
4852 }
4853
4fa24527 4854 if (!object_64bit)
d6ab8113 4855 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4856 else if (size == 4)
d6ab8113 4857 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4858 else if (size == 8)
4859 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4860 i.op[n].imms->X_add_number += add;
29b0f896 4861 }
29b0f896
AM		 4862 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4863 i.op[n].imms, 0, reloc_type);
4864 }
4865 }
4866 }
252b5132
RH		 4867}
4868\f
d182319b
JB		 4869/* x86_cons_fix_new is called via the expression parsing code when a
4870 reloc is needed. We use this hook to get the correct .got reloc. */
4871static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4872static int cons_sign = -1;
4873
4874void
e3bb37b5 4875x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 4876 expressionS *exp)
d182319b
JB		 4877{
4878 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4879
4880 got_reloc = NO_RELOC;
4881
4882#ifdef TE_PE
4883 if (exp->X_op == O_secrel)
4884 {
4885 exp->X_op = O_symbol;
4886 r = BFD_RELOC_32_SECREL;
4887 }
4888#endif
4889
4890 fix_new_exp (frag, off, len, exp, 0, r);
4891}
4892
718ddfc0
JB		 4893#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4894# define lex_got(reloc, adjust, types) NULL
4895#else
f3c180ae
AM		 4896/* Parse operands of the form
4897 <symbol>@GOTOFF+<nnn>
4898 and similar .plt or .got references.
4899
4900 If we find one, set up the correct relocation in RELOC and copy the
4901 input string, minus the `@GOTOFF' into a malloc'd buffer for
4902 parsing by the calling routine. Return this buffer, and if ADJUST
4903 is non-null set it to the length of the string we removed from the
4904 input line. Otherwise return NULL. */
4905static char *
3956db08 4906lex_got (enum bfd_reloc_code_real *reloc,
64e74474 4907 int *adjust,
40fb9820 4908 i386_operand_type *types)
f3c180ae 4909{
7b81dfbb
AJ		 4910 /* Some of the relocations depend on the size of what field is to
4911 be relocated. But in our callers i386_immediate and i386_displacement
4912 we don't yet know the operand size (this will be set by insn
4913 matching). Hence we record the word32 relocation here,
4914 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4915 static const struct {
4916 const char *str;
4fa24527 4917 const enum bfd_reloc_code_real rel[2];
40fb9820 4918 const i386_operand_type types64;
f3c180ae 4919 } gotrel[] = {
4eed87de
AM		 4920 { "PLTOFF", { 0,
4921 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 4922 OPERAND_TYPE_IMM64 },
4eed87de
AM		 4923 { "PLT", { BFD_RELOC_386_PLT32,
4924 BFD_RELOC_X86_64_PLT32 },
40fb9820 4925 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 4926 { "GOTPLT", { 0,
4927 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 4928 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 4929 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
4930 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 4931 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 4932 { "GOTPCREL", { 0,
4933 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 4934 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 4935 { "TLSGD", { BFD_RELOC_386_TLS_GD,
4936 BFD_RELOC_X86_64_TLSGD },
40fb9820 4937 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 4938 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
4939 0 },
40fb9820 4940 OPERAND_TYPE_NONE },
4eed87de
AM		 4941 { "TLSLD", { 0,
4942 BFD_RELOC_X86_64_TLSLD },
40fb9820 4943 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 4944 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
4945 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 4946 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 4947 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
4948 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 4949 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 4950 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
4951 0 },
40fb9820 4952 OPERAND_TYPE_NONE },
4eed87de
AM		 4953 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
4954 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 4955
4956 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 4957 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
4958 0 },
40fb9820 4959 OPERAND_TYPE_NONE },
4eed87de
AM		 4960 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
4961 0 },
40fb9820 4962 OPERAND_TYPE_NONE },
4eed87de
AM		 4963 { "GOT", { BFD_RELOC_386_GOT32,
4964 BFD_RELOC_X86_64_GOT32 },
40fb9820 4965 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 4966 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
4967 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 4968 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 4969 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
4970 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 4971 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 4972 };
4973 char *cp;
4974 unsigned int j;
4975
718ddfc0
JB		 4976 if (!IS_ELF)
4977 return NULL;
4978
f3c180ae 4979 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 4980 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 4981 return NULL;
4982
4983 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4984 {
4985 int len;
4986
4987 len = strlen (gotrel[j].str);
28f81592 4988 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4989 {
4fa24527 4990 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4991 {
28f81592
AM		 4992 int first, second;
4993 char *tmpbuf, *past_reloc;
f3c180ae 4994
4fa24527 4995 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 4996 if (adjust)
4997 *adjust = len;
f3c180ae 4998
3956db08
JB		 4999 if (types)
5000 {
5001 if (flag_code != CODE_64BIT)
40fb9820
L		 5002 {
5003 types->bitfield.imm32 = 1;
5004 types->bitfield.disp32 = 1;
5005 }
3956db08
JB		 5006 else
5007 *types = gotrel[j].types64;
5008 }
5009
f3c180ae
AM		 5010 if (GOT_symbol == NULL)
5011 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5012
28f81592 5013 /* The length of the first part of our input line. */
f3c180ae 5014 first = cp - input_line_pointer;
28f81592
AM		 5015
5016 /* The second part goes from after the reloc token until
67c11a9b 5017 (and including) an end_of_line char or comma. */
28f81592 5018 past_reloc = cp + 1 + len;
67c11a9b
AM		 5019 cp = past_reloc;
5020 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5021 ++cp;
5022 second = cp + 1 - past_reloc;
28f81592
AM		 5023
5024 /* Allocate and copy string. The trailing NUL shouldn't
5025 be necessary, but be safe. */
5026 tmpbuf = xmalloc (first + second + 2);
f3c180ae 5027 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 5028 if (second != 0 && *past_reloc != ' ')
5029 /* Replace the relocation token with ' ', so that
5030 errors like foo@GOTOFF1 will be detected. */
5031 tmpbuf[first++] = ' ';
5032 memcpy (tmpbuf + first, past_reloc, second);
5033 tmpbuf[first + second] = '\0';
f3c180ae
AM		 5034 return tmpbuf;
5035 }
5036
4fa24527
JB		 5037 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5038 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 5039 return NULL;
5040 }
5041 }
5042
5043 /* Might be a symbol version string. Don't as_bad here. */
5044 return NULL;
5045}
5046
f3c180ae 5047void
e3bb37b5 5048x86_cons (expressionS *exp, int size)
f3c180ae 5049{
4fa24527 5050 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 5051 {
5052 /* Handle @GOTOFF and the like in an expression. */
5053 char *save;
5054 char *gotfree_input_line;
5055 int adjust;
5056
5057 save = input_line_pointer;
3956db08 5058 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 5059 if (gotfree_input_line)
5060 input_line_pointer = gotfree_input_line;
5061
5062 expression (exp);
5063
5064 if (gotfree_input_line)
5065 {
5066 /* expression () has merrily parsed up to the end of line,
5067 or a comma - in the wrong buffer. Transfer how far
5068 input_line_pointer has moved to the right buffer. */
5069 input_line_pointer = (save
5070 + (input_line_pointer - gotfree_input_line)
5071 + adjust);
5072 free (gotfree_input_line);
3992d3b7
AM		 5073 if (exp->X_op == O_constant
5074 || exp->X_op == O_absent
5075 || exp->X_op == O_illegal
5076 || exp->X_op == O_register
5077 || exp->X_op == O_big)
5078 {
5079 char c = *input_line_pointer;
5080 *input_line_pointer = 0;
5081 as_bad (_("missing or invalid expression `%s'"), save);
5082 *input_line_pointer = c;
5083 }
f3c180ae
AM		 5084 }
5085 }
5086 else
5087 expression (exp);
5088}
5089#endif
5090
d182319b 5091static void signed_cons (int size)
6482c264 5092{
d182319b
JB		 5093 if (flag_code == CODE_64BIT)
5094 cons_sign = 1;
5095 cons (size);
5096 cons_sign = -1;
6482c264
NC		 5097}
5098
d182319b 5099#ifdef TE_PE
6482c264
NC		 5100static void
5101pe_directive_secrel (dummy)
5102 int dummy ATTRIBUTE_UNUSED;
5103{
5104 expressionS exp;
5105
5106 do
5107 {
5108 expression (&exp);
5109 if (exp.X_op == O_symbol)
5110 exp.X_op = O_secrel;
5111
5112 emit_expr (&exp, 4);
5113 }
5114 while (*input_line_pointer++ == ',');
5115
5116 input_line_pointer--;
5117 demand_empty_rest_of_line ();
5118}
6482c264
NC		 5119#endif
5120
252b5132 5121static int
70e41ade 5122i386_immediate (char *imm_start)
252b5132
RH		 5123{
5124 char *save_input_line_pointer;
f3c180ae 5125 char *gotfree_input_line;
252b5132 5126 segT exp_seg = 0;
47926f60 5127 expressionS *exp;
40fb9820
L		 5128 i386_operand_type types;
5129
5130 memset (&types, ~0, sizeof (types));
252b5132
RH		 5131
5132 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5133 {
31b2323c
L		 5134 as_bad (_("at most %d immediate operands are allowed"),
5135 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 5136 return 0;
5137 }
5138
5139 exp = &im_expressions[i.imm_operands++];
520dc8e8 5140 i.op[this_operand].imms = exp;
252b5132
RH		 5141
5142 if (is_space_char (*imm_start))
5143 ++imm_start;
5144
5145 save_input_line_pointer = input_line_pointer;
5146 input_line_pointer = imm_start;
5147
3956db08 5148 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5149 if (gotfree_input_line)
5150 input_line_pointer = gotfree_input_line;
252b5132
RH		 5151
5152 exp_seg = expression (exp);
5153
83183c0c 5154 SKIP_WHITESPACE ();
252b5132 5155 if (*input_line_pointer)
f3c180ae 5156 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 5157
5158 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 5159 if (gotfree_input_line)
5160 free (gotfree_input_line);
252b5132 5161
3992d3b7
AM		 5162 if (exp->X_op == O_absent
5163 || exp->X_op == O_illegal
5164 || exp->X_op == O_big
5165 || (gotfree_input_line
5166 && (exp->X_op == O_constant
5167 || exp->X_op == O_register)))
252b5132 5168 {
3992d3b7 5169 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 5170 imm_start);
3992d3b7 5171 return 0;
252b5132 5172 }
3e73aa7c 5173 else if (exp->X_op == O_constant)
252b5132 5174 {
47926f60 5175 /* Size it properly later. */
40fb9820 5176 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 5177 /* If BFD64, sign extend val. */
4eed87de
AM		 5178 if (!use_rela_relocations
5179 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5180 exp->X_add_number
5181 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 5182 }
4c63da97 5183#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 5184 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 5185 && exp_seg != absolute_section
47926f60 5186 && exp_seg != text_section
24eab124
AM		 5187 && exp_seg != data_section
5188 && exp_seg != bss_section
5189 && exp_seg != undefined_section
f86103b7 5190 && !bfd_is_com_section (exp_seg))
252b5132 5191 {
d0b47220 5192 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 5193 return 0;
5194 }
5195#endif
bb8f5920
L		 5196 else if (!intel_syntax && exp->X_op == O_register)
5197 {
5198 as_bad (_("illegal immediate register operand %s"), imm_start);
5199 return 0;
5200 }
252b5132
RH		 5201 else
5202 {
5203 /* This is an address. The size of the address will be
24eab124 5204 determined later, depending on destination register,
3e73aa7c 5205 suffix, or the default for the section. */
40fb9820
L		 5206 i.types[this_operand].bitfield.imm8 = 1;
5207 i.types[this_operand].bitfield.imm16 = 1;
5208 i.types[this_operand].bitfield.imm32 = 1;
5209 i.types[this_operand].bitfield.imm32s = 1;
5210 i.types[this_operand].bitfield.imm64 = 1;
5211 i.types[this_operand] = operand_type_biop (i.types[this_operand],
5212 types, and);
252b5132
RH		 5213 }
5214
5215 return 1;
5216}
5217
551c1ca1 5218static char *
e3bb37b5 5219i386_scale (char *scale)
252b5132 5220{
551c1ca1
AM		 5221 offsetT val;
5222 char *save = input_line_pointer;
252b5132 5223
551c1ca1
AM		 5224 input_line_pointer = scale;
5225 val = get_absolute_expression ();
5226
5227 switch (val)
252b5132 5228 {
551c1ca1 5229 case 1:
252b5132
RH		 5230 i.log2_scale_factor = 0;
5231 break;
551c1ca1 5232 case 2:
252b5132
RH		 5233 i.log2_scale_factor = 1;
5234 break;
551c1ca1 5235 case 4:
252b5132
RH		 5236 i.log2_scale_factor = 2;
5237 break;
551c1ca1 5238 case 8:
252b5132
RH		 5239 i.log2_scale_factor = 3;
5240 break;
5241 default:
a724f0f4
JB		 5242 {
5243 char sep = *input_line_pointer;
5244
5245 *input_line_pointer = '\0';
5246 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5247 scale);
5248 *input_line_pointer = sep;
5249 input_line_pointer = save;
5250 return NULL;
5251 }
252b5132 5252 }
29b0f896 5253 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 5254 {
5255 as_warn (_("scale factor of %d without an index register"),
24eab124 5256 1 << i.log2_scale_factor);
252b5132
RH		 5257#if SCALE1_WHEN_NO_INDEX
5258 i.log2_scale_factor = 0;
5259#endif
5260 }
551c1ca1
AM		 5261 scale = input_line_pointer;
5262 input_line_pointer = save;
5263 return scale;
252b5132
RH		 5264}
5265
252b5132 5266static int
e3bb37b5 5267i386_displacement (char *disp_start, char *disp_end)
252b5132 5268{
29b0f896 5269 expressionS *exp;
252b5132
RH		 5270 segT exp_seg = 0;
5271 char *save_input_line_pointer;
f3c180ae 5272 char *gotfree_input_line;
40fb9820
L		 5273 int override;
5274 i386_operand_type bigdisp, types = anydisp;
3992d3b7 5275 int ret;
252b5132 5276
31b2323c
L		 5277 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5278 {
5279 as_bad (_("at most %d displacement operands are allowed"),
5280 MAX_MEMORY_OPERANDS);
5281 return 0;
5282 }
5283
40fb9820
L		 5284 memset (&bigdisp, 0, sizeof (bigdisp));
5285 if ((i.types[this_operand].bitfield.jumpabsolute)
5286 || (!current_templates->start->opcode_modifier.jump
5287 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 5288 {
40fb9820 5289 bigdisp.bitfield.disp32 = 1;
e05278af 5290 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 5291 if (flag_code == CODE_64BIT)
5292 {
5293 if (!override)
5294 {
5295 bigdisp.bitfield.disp32s = 1;
5296 bigdisp.bitfield.disp64 = 1;
5297 }
5298 }
5299 else if ((flag_code == CODE_16BIT) ^ override)
5300 {
5301 bigdisp.bitfield.disp32 = 0;
5302 bigdisp.bitfield.disp16 = 1;
5303 }
e05278af
JB		 5304 }
5305 else
5306 {
5307 /* For PC-relative branches, the width of the displacement
5308 is dependent upon data size, not address size. */
e05278af 5309 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 5310 if (flag_code == CODE_64BIT)
5311 {
5312 if (override || i.suffix == WORD_MNEM_SUFFIX)
5313 bigdisp.bitfield.disp16 = 1;
5314 else
5315 {
5316 bigdisp.bitfield.disp32 = 1;
5317 bigdisp.bitfield.disp32s = 1;
5318 }
5319 }
5320 else
e05278af
JB		 5321 {
5322 if (!override)
5323 override = (i.suffix == (flag_code != CODE_16BIT
5324 ? WORD_MNEM_SUFFIX
5325 : LONG_MNEM_SUFFIX));
40fb9820
L		 5326 bigdisp.bitfield.disp32 = 1;
5327 if ((flag_code == CODE_16BIT) ^ override)
5328 {
5329 bigdisp.bitfield.disp32 = 0;
5330 bigdisp.bitfield.disp16 = 1;
5331 }
e05278af 5332 }
e05278af 5333 }
40fb9820
L		 5334 i.types[this_operand] = operand_type_biop (i.types[this_operand],
5335 bigdisp, or);
252b5132
RH		 5336
5337 exp = &disp_expressions[i.disp_operands];
520dc8e8 5338 i.op[this_operand].disps = exp;
252b5132
RH		 5339 i.disp_operands++;
5340 save_input_line_pointer = input_line_pointer;
5341 input_line_pointer = disp_start;
5342 END_STRING_AND_SAVE (disp_end);
5343
5344#ifndef GCC_ASM_O_HACK
5345#define GCC_ASM_O_HACK 0
5346#endif
5347#if GCC_ASM_O_HACK
5348 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 5349 if (i.types[this_operand].bitfield.baseIndex
24eab124 5350 && displacement_string_end[-1] == '+')
252b5132
RH		 5351 {
5352 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 5353 constraint within gcc asm statements.
5354 For instance:
5355
5356 #define _set_tssldt_desc(n,addr,limit,type) \
5357 __asm__ __volatile__ ( \
5358 "movw %w2,%0\n\t" \
5359 "movw %w1,2+%0\n\t" \
5360 "rorl $16,%1\n\t" \
5361 "movb %b1,4+%0\n\t" \
5362 "movb %4,5+%0\n\t" \
5363 "movb $0,6+%0\n\t" \
5364 "movb %h1,7+%0\n\t" \
5365 "rorl $16,%1" \
5366 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5367
5368 This works great except that the output assembler ends
5369 up looking a bit weird if it turns out that there is
5370 no offset. You end up producing code that looks like:
5371
5372 #APP
5373 movw $235,(%eax)
5374 movw %dx,2+(%eax)
5375 rorl $16,%edx
5376 movb %dl,4+(%eax)
5377 movb $137,5+(%eax)
5378 movb $0,6+(%eax)
5379 movb %dh,7+(%eax)
5380 rorl $16,%edx
5381 #NO_APP
5382
47926f60 5383 So here we provide the missing zero. */
24eab124
AM		 5384
5385 *displacement_string_end = '0';
252b5132
RH		 5386 }
5387#endif
3956db08 5388 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5389 if (gotfree_input_line)
5390 input_line_pointer = gotfree_input_line;
252b5132 5391
24eab124 5392 exp_seg = expression (exp);
252b5132 5393
636c26b0
AM		 5394 SKIP_WHITESPACE ();
5395 if (*input_line_pointer)
5396 as_bad (_("junk `%s' after expression"), input_line_pointer);
5397#if GCC_ASM_O_HACK
5398 RESTORE_END_STRING (disp_end + 1);
5399#endif
636c26b0 5400 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 5401 if (gotfree_input_line)
5402 free (gotfree_input_line);
3992d3b7 5403 ret = 1;
636c26b0 5404
24eab124
AM		 5405 /* We do this to make sure that the section symbol is in
5406 the symbol table. We will ultimately change the relocation
47926f60 5407 to be relative to the beginning of the section. */
1ae12ab7 5408 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 5409 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
5410 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 5411 {
636c26b0 5412 if (exp->X_op != O_symbol)
3992d3b7 5413 goto inv_disp;
636c26b0 5414
e5cb08ac 5415 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 5416 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
5417 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 5418 exp->X_op = O_subtract;
5419 exp->X_op_symbol = GOT_symbol;
1ae12ab7 5420 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 5421 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 5422 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5423 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 5424 else
29b0f896 5425 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 5426 }
252b5132 5427
3992d3b7
AM		 5428 else if (exp->X_op == O_absent
5429 || exp->X_op == O_illegal
5430 || exp->X_op == O_big
5431 || (gotfree_input_line
5432 && (exp->X_op == O_constant
5433 || exp->X_op == O_register)))
2daf4fd8 5434 {
3992d3b7
AM		 5435 inv_disp:
5436 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 5437 disp_start);
3992d3b7 5438 ret = 0;
2daf4fd8
AM		 5439 }
5440
4c63da97 5441#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 5442 else if (exp->X_op != O_constant
5443 && OUTPUT_FLAVOR == bfd_target_aout_flavour
5444 && exp_seg != absolute_section
5445 && exp_seg != text_section
5446 && exp_seg != data_section
5447 && exp_seg != bss_section
5448 && exp_seg != undefined_section
5449 && !bfd_is_com_section (exp_seg))
24eab124 5450 {
d0b47220 5451 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 5452 ret = 0;
24eab124 5453 }
252b5132 5454#endif
3956db08 5455
3992d3b7
AM		 5456 RESTORE_END_STRING (disp_end);
5457
40fb9820
L		 5458 /* Check if this is a displacement only operand. */
5459 bigdisp = i.types[this_operand];
5460 bigdisp.bitfield.disp8 = 0;
5461 bigdisp.bitfield.disp16 = 0;
5462 bigdisp.bitfield.disp32 = 0;
5463 bigdisp.bitfield.disp32s = 0;
5464 bigdisp.bitfield.disp64 = 0;
5465 if (operand_type_all_zero (bigdisp))
5466 i.types[this_operand] = operand_type_biop (i.types[this_operand],
5467 types, and);
3956db08 5468
3992d3b7 5469 return ret;
252b5132
RH		 5470}
5471
eecb386c 5472/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 5473 Return 1 on success, 0 on a failure. */
5474
252b5132 5475static int
e3bb37b5 5476i386_index_check (const char *operand_string)
252b5132 5477{
3e73aa7c 5478 int ok;
24eab124 5479#if INFER_ADDR_PREFIX
eecb386c
AM		 5480 int fudged = 0;
5481
24eab124
AM		 5482 tryprefix:
5483#endif
3e73aa7c 5484 ok = 1;
75178d9d 5485 if (flag_code == CODE_64BIT)
64e74474 5486 {
64e74474 5487 if ((i.base_reg
40fb9820
L		 5488 && ((i.prefix[ADDR_PREFIX] == 0
5489 && !i.base_reg->reg_type.bitfield.reg64)
5490 || (i.prefix[ADDR_PREFIX]
5491 && !i.base_reg->reg_type.bitfield.reg32))
5492 && (i.index_reg
5493 || memcmp (&i.base_reg->reg_type, &baseindex,
5494 sizeof (baseindex))))
64e74474 5495 || (i.index_reg
40fb9820
L		 5496 && (!i.index_reg->reg_type.bitfield.baseindex
5497 || (i.prefix[ADDR_PREFIX] == 0
5498 && !i.index_reg->reg_type.bitfield.reg64)
5499 || (i.prefix[ADDR_PREFIX]
5500 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 5501 ok = 0;
3e73aa7c
JH		 5502 }
5503 else
5504 {
5505 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
5506 {
5507 /* 16bit checks. */
5508 if ((i.base_reg
40fb9820
L		 5509 && (!i.base_reg->reg_type.bitfield.reg16
5510 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 5511 || (i.index_reg
40fb9820
L		 5512 && (!i.index_reg->reg_type.bitfield.reg16
5513 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 5514 || !(i.base_reg
5515 && i.base_reg->reg_num < 6
5516 && i.index_reg->reg_num >= 6
5517 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 5518 ok = 0;
5519 }
5520 else
e5cb08ac 5521 {
3e73aa7c
JH		 5522 /* 32bit checks. */
5523 if ((i.base_reg
40fb9820 5524 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 5525 || (i.index_reg
40fb9820
L		 5526 && (!i.index_reg->reg_type.bitfield.reg32
5527 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 5528 ok = 0;
3e73aa7c
JH		 5529 }
5530 }
5531 if (!ok)
24eab124
AM		 5532 {
5533#if INFER_ADDR_PREFIX
20f0a1fc 5534 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 5535 {
5536 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
5537 i.prefixes += 1;
b23bac36
AM		 5538 /* Change the size of any displacement too. At most one of
5539 Disp16 or Disp32 is set.
5540 FIXME. There doesn't seem to be any real need for separate
5541 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 5542 Removing them would probably clean up the code quite a lot. */
4eed87de 5543 if (flag_code != CODE_64BIT
40fb9820
L		 5544 && (i.types[this_operand].bitfield.disp16
5545 || i.types[this_operand].bitfield.disp32))
5546 i.types[this_operand]
5547 = operand_type_biop (i.types[this_operand], disp16_32,
5548 xor);
eecb386c 5549 fudged = 1;
24eab124
AM		 5550 goto tryprefix;
5551 }
eecb386c
AM		 5552 if (fudged)
5553 as_bad (_("`%s' is not a valid base/index expression"),
5554 operand_string);
5555 else
c388dee8 5556#endif
eecb386c
AM		 5557 as_bad (_("`%s' is not a valid %s bit base/index expression"),
5558 operand_string,
3e73aa7c 5559 flag_code_names[flag_code]);
24eab124 5560 }
20f0a1fc 5561 return ok;
24eab124 5562}
252b5132 5563
252b5132 5564/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 5565 on error. */
252b5132 5566
252b5132 5567static int
e3bb37b5 5568i386_operand (char *operand_string)
252b5132 5569{
af6bdddf
AM		 5570 const reg_entry *r;
5571 char *end_op;
24eab124 5572 char *op_string = operand_string;
252b5132 5573
24eab124 5574 if (is_space_char (*op_string))
252b5132
RH		 5575 ++op_string;
5576
24eab124 5577 /* We check for an absolute prefix (differentiating,
47926f60 5578 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 5579 if (*op_string == ABSOLUTE_PREFIX)
5580 {
5581 ++op_string;
5582 if (is_space_char (*op_string))
5583 ++op_string;
40fb9820 5584 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 5585 }
252b5132 5586
47926f60 5587 /* Check if operand is a register. */
4d1bb795 5588 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 5589 {
40fb9820
L		 5590 i386_operand_type temp;
5591
24eab124
AM		 5592 /* Check for a segment override by searching for ':' after a
5593 segment register. */
5594 op_string = end_op;
5595 if (is_space_char (*op_string))
5596 ++op_string;
40fb9820
L		 5597 if (*op_string == ':'
5598 && (r->reg_type.bitfield.sreg2
5599 || r->reg_type.bitfield.sreg3))
24eab124
AM		 5600 {
5601 switch (r->reg_num)
5602 {
5603 case 0:
5604 i.seg[i.mem_operands] = &es;
5605 break;
5606 case 1:
5607 i.seg[i.mem_operands] = &cs;
5608 break;
5609 case 2:
5610 i.seg[i.mem_operands] = &ss;
5611 break;
5612 case 3:
5613 i.seg[i.mem_operands] = &ds;
5614 break;
5615 case 4:
5616 i.seg[i.mem_operands] = &fs;
5617 break;
5618 case 5:
5619 i.seg[i.mem_operands] = &gs;
5620 break;
5621 }
252b5132 5622
24eab124 5623 /* Skip the ':' and whitespace. */
252b5132
RH		 5624 ++op_string;
5625 if (is_space_char (*op_string))
24eab124 5626 ++op_string;
252b5132 5627
24eab124
AM		 5628 if (!is_digit_char (*op_string)
5629 && !is_identifier_char (*op_string)
5630 && *op_string != '('
5631 && *op_string != ABSOLUTE_PREFIX)
5632 {
5633 as_bad (_("bad memory operand `%s'"), op_string);
5634 return 0;
5635 }
47926f60 5636 /* Handle case of %es:*foo. */
24eab124
AM		 5637 if (*op_string == ABSOLUTE_PREFIX)
5638 {
5639 ++op_string;
5640 if (is_space_char (*op_string))
5641 ++op_string;
40fb9820 5642 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 5643 }
5644 goto do_memory_reference;
5645 }
5646 if (*op_string)
5647 {
d0b47220 5648 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 5649 return 0;
5650 }
40fb9820
L		 5651 temp = r->reg_type;
5652 temp.bitfield.baseindex = 0;
5653 i.types[this_operand] = operand_type_biop (i.types[this_operand],
5654 temp, or);
520dc8e8 5655 i.op[this_operand].regs = r;
24eab124
AM		 5656 i.reg_operands++;
5657 }
af6bdddf
AM		 5658 else if (*op_string == REGISTER_PREFIX)
5659 {
5660 as_bad (_("bad register name `%s'"), op_string);
5661 return 0;
5662 }
24eab124 5663 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 5664 {
24eab124 5665 ++op_string;
40fb9820 5666 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 5667 {
d0b47220 5668 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 5669 return 0;
5670 }
5671 if (!i386_immediate (op_string))
5672 return 0;
5673 }
5674 else if (is_digit_char (*op_string)
5675 || is_identifier_char (*op_string)
e5cb08ac 5676 || *op_string == '(')
24eab124 5677 {
47926f60 5678 /* This is a memory reference of some sort. */
af6bdddf 5679 char *base_string;
252b5132 5680
47926f60 5681 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 5682 char *displacement_string_start;
5683 char *displacement_string_end;
252b5132 5684
24eab124 5685 do_memory_reference:
24eab124 5686 if ((i.mem_operands == 1
40fb9820 5687 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 5688 || i.mem_operands == 2)
5689 {
5690 as_bad (_("too many memory references for `%s'"),
5691 current_templates->start->name);
5692 return 0;
5693 }
252b5132 5694
24eab124
AM		 5695 /* Check for base index form. We detect the base index form by
5696 looking for an ')' at the end of the operand, searching
5697 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5698 after the '('. */
af6bdddf 5699 base_string = op_string + strlen (op_string);
c3332e24 5700
af6bdddf
AM		 5701 --base_string;
5702 if (is_space_char (*base_string))
5703 --base_string;
252b5132 5704
47926f60 5705 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 5706 displacement_string_start = op_string;
5707 displacement_string_end = base_string + 1;
252b5132 5708
24eab124
AM		 5709 if (*base_string == ')')
5710 {
af6bdddf 5711 char *temp_string;
24eab124
AM		 5712 unsigned int parens_balanced = 1;
5713 /* We've already checked that the number of left & right ()'s are
47926f60 5714 equal, so this loop will not be infinite. */
24eab124
AM		 5715 do
5716 {
5717 base_string--;
5718 if (*base_string == ')')
5719 parens_balanced++;
5720 if (*base_string == '(')
5721 parens_balanced--;
5722 }
5723 while (parens_balanced);
c3332e24 5724
af6bdddf 5725 temp_string = base_string;
c3332e24 5726
24eab124 5727 /* Skip past '(' and whitespace. */
252b5132
RH		 5728 ++base_string;
5729 if (is_space_char (*base_string))
24eab124 5730 ++base_string;
252b5132 5731
af6bdddf 5732 if (*base_string == ','
4eed87de
AM		 5733 || ((i.base_reg = parse_register (base_string, &end_op))
5734 != NULL))
252b5132 5735 {
af6bdddf 5736 displacement_string_end = temp_string;
252b5132 5737
40fb9820 5738 i.types[this_operand].bitfield.baseindex = 1;
252b5132 5739
af6bdddf 5740 if (i.base_reg)
24eab124 5741 {
24eab124
AM		 5742 base_string = end_op;
5743 if (is_space_char (*base_string))
5744 ++base_string;
af6bdddf
AM		 5745 }
5746
5747 /* There may be an index reg or scale factor here. */
5748 if (*base_string == ',')
5749 {
5750 ++base_string;
5751 if (is_space_char (*base_string))
5752 ++base_string;
5753
4eed87de
AM		 5754 if ((i.index_reg = parse_register (base_string, &end_op))
5755 != NULL)
24eab124 5756 {
af6bdddf 5757 base_string = end_op;
24eab124
AM		 5758 if (is_space_char (*base_string))
5759 ++base_string;
af6bdddf
AM		 5760 if (*base_string == ',')
5761 {
5762 ++base_string;
5763 if (is_space_char (*base_string))
5764 ++base_string;
5765 }
e5cb08ac 5766 else if (*base_string != ')')
af6bdddf 5767 {
4eed87de
AM		 5768 as_bad (_("expecting `,' or `)' "
5769 "after index register in `%s'"),
af6bdddf
AM		 5770 operand_string);
5771 return 0;
5772 }
24eab124 5773 }
af6bdddf 5774 else if (*base_string == REGISTER_PREFIX)
24eab124 5775 {
af6bdddf 5776 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5777 return 0;
5778 }
252b5132 5779
47926f60 5780 /* Check for scale factor. */
551c1ca1 5781 if (*base_string != ')')
af6bdddf 5782 {
551c1ca1
AM		 5783 char *end_scale = i386_scale (base_string);
5784
5785 if (!end_scale)
af6bdddf 5786 return 0;
24eab124 5787
551c1ca1 5788 base_string = end_scale;
af6bdddf
AM		 5789 if (is_space_char (*base_string))
5790 ++base_string;
5791 if (*base_string != ')')
5792 {
4eed87de
AM		 5793 as_bad (_("expecting `)' "
5794 "after scale factor in `%s'"),
af6bdddf
AM		 5795 operand_string);
5796 return 0;
5797 }
5798 }
5799 else if (!i.index_reg)
24eab124 5800 {
4eed87de
AM		 5801 as_bad (_("expecting index register or scale factor "
5802 "after `,'; got '%c'"),
af6bdddf 5803 *base_string);
24eab124
AM		 5804 return 0;
5805 }
5806 }
af6bdddf 5807 else if (*base_string != ')')
24eab124 5808 {
4eed87de
AM		 5809 as_bad (_("expecting `,' or `)' "
5810 "after base register in `%s'"),
af6bdddf 5811 operand_string);
24eab124
AM		 5812 return 0;
5813 }
c3332e24 5814 }
af6bdddf 5815 else if (*base_string == REGISTER_PREFIX)
c3332e24 5816 {
af6bdddf 5817 as_bad (_("bad register name `%s'"), base_string);
24eab124 5818 return 0;
c3332e24 5819 }
24eab124
AM		 5820 }
5821
5822 /* If there's an expression beginning the operand, parse it,
5823 assuming displacement_string_start and
5824 displacement_string_end are meaningful. */
5825 if (displacement_string_start != displacement_string_end)
5826 {
5827 if (!i386_displacement (displacement_string_start,
5828 displacement_string_end))
5829 return 0;
5830 }
5831
5832 /* Special case for (%dx) while doing input/output op. */
5833 if (i.base_reg
40fb9820
L		 5834 && memcmp (&i.base_reg->reg_type, &reg16_inoutportreg,
5835 sizeof (reg16_inoutportreg)) == 0
24eab124
AM		 5836 && i.index_reg == 0
5837 && i.log2_scale_factor == 0
5838 && i.seg[i.mem_operands] == 0
40fb9820 5839 && !operand_type_check (i.types[this_operand], disp))
24eab124 5840 {
40fb9820
L		 5841 memset (&i.types[this_operand], 0,
5842 sizeof (i.types[this_operand]));
5843 i.types[this_operand].bitfield.inoutportreg = 1;
24eab124
AM		 5844 return 1;
5845 }
5846
eecb386c
AM		 5847 if (i386_index_check (operand_string) == 0)
5848 return 0;
24eab124
AM		 5849 i.mem_operands++;
5850 }
5851 else
ce8a8b2f
AM		 5852 {
5853 /* It's not a memory operand; argh! */
24eab124
AM		 5854 as_bad (_("invalid char %s beginning operand %d `%s'"),
5855 output_invalid (*op_string),
5856 this_operand + 1,
5857 op_string);
5858 return 0;
5859 }
47926f60 5860 return 1; /* Normal return. */
252b5132
RH		 5861}
5862\f
ee7fcc42
AM		 5863/* md_estimate_size_before_relax()
5864
5865 Called just before relax() for rs_machine_dependent frags. The x86
5866 assembler uses these frags to handle variable size jump
5867 instructions.
5868
5869 Any symbol that is now undefined will not become defined.
5870 Return the correct fr_subtype in the frag.
5871 Return the initial "guess for variable size of frag" to caller.
5872 The guess is actually the growth beyond the fixed part. Whatever
5873 we do to grow the fixed or variable part contributes to our
5874 returned value. */
5875
252b5132
RH		 5876int
5877md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5878 fragS *fragP;
5879 segT segment;
252b5132 5880{
252b5132 5881 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5882 check for un-relaxable symbols. On an ELF system, we can't relax
5883 an externally visible symbol, because it may be overridden by a
5884 shared library. */
5885 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5886#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5887 || (IS_ELF
31312f95
AM		 5888 && (S_IS_EXTERNAL (fragP->fr_symbol)
5889 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5890#endif
5891 )
252b5132 5892 {
b98ef147
AM		 5893 /* Symbol is undefined in this segment, or we need to keep a
5894 reloc so that weak symbols can be overridden. */
5895 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5896 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5897 unsigned char *opcode;
5898 int old_fr_fix;
f6af82bd 5899
ee7fcc42
AM		 5900 if (fragP->fr_var != NO_RELOC)
5901 reloc_type = fragP->fr_var;
b98ef147 5902 else if (size == 2)
f6af82bd
AM		 5903 reloc_type = BFD_RELOC_16_PCREL;
5904 else
5905 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5906
ee7fcc42
AM		 5907 old_fr_fix = fragP->fr_fix;
5908 opcode = (unsigned char *) fragP->fr_opcode;
5909
fddf5b5b 5910 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5911 {
fddf5b5b
AM		 5912 case UNCOND_JUMP:
5913 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5914 opcode[0] = 0xe9;
252b5132 5915 fragP->fr_fix += size;
062cd5e7
AS		 5916 fix_new (fragP, old_fr_fix, size,
5917 fragP->fr_symbol,
5918 fragP->fr_offset, 1,
5919 reloc_type);
252b5132
RH		 5920 break;
5921
fddf5b5b 5922 case COND_JUMP86:
412167cb
AM		 5923 if (size == 2
5924 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5925 {
5926 /* Negate the condition, and branch past an
5927 unconditional jump. */
5928 opcode[0] ^= 1;
5929 opcode[1] = 3;
5930 /* Insert an unconditional jump. */
5931 opcode[2] = 0xe9;
5932 /* We added two extra opcode bytes, and have a two byte
5933 offset. */
5934 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5935 fix_new (fragP, old_fr_fix + 2, 2,
5936 fragP->fr_symbol,
5937 fragP->fr_offset, 1,
5938 reloc_type);
fddf5b5b
AM		 5939 break;
5940 }
5941 /* Fall through. */
5942
5943 case COND_JUMP:
412167cb
AM		 5944 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5945 {
3e02c1cc
AM		 5946 fixS *fixP;
5947
412167cb 5948 fragP->fr_fix += 1;
3e02c1cc
AM		 5949 fixP = fix_new (fragP, old_fr_fix, 1,
5950 fragP->fr_symbol,
5951 fragP->fr_offset, 1,
5952 BFD_RELOC_8_PCREL);
5953 fixP->fx_signed = 1;
412167cb
AM		 5954 break;
5955 }
93c2a809 5956
24eab124 5957 /* This changes the byte-displacement jump 0x7N
fddf5b5b 5958 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 5959 opcode[1] = opcode[0] + 0x10;
f6af82bd 5960 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 5961 /* We've added an opcode byte. */
5962 fragP->fr_fix += 1 + size;
062cd5e7
AS		 5963 fix_new (fragP, old_fr_fix + 1, size,
5964 fragP->fr_symbol,
5965 fragP->fr_offset, 1,
5966 reloc_type);
252b5132 5967 break;
fddf5b5b
AM		 5968
5969 default:
5970 BAD_CASE (fragP->fr_subtype);
5971 break;
252b5132
RH		 5972 }
5973 frag_wane (fragP);
ee7fcc42 5974 return fragP->fr_fix - old_fr_fix;
252b5132 5975 }
93c2a809 5976
93c2a809
AM		 5977 /* Guess size depending on current relax state. Initially the relax
5978 state will correspond to a short jump and we return 1, because
5979 the variable part of the frag (the branch offset) is one byte
5980 long. However, we can relax a section more than once and in that
5981 case we must either set fr_subtype back to the unrelaxed state,
5982 or return the value for the appropriate branch. */
5983 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 5984}
5985
47926f60
KH		 5986/* Called after relax() is finished.
5987
5988 In: Address of frag.
5989 fr_type == rs_machine_dependent.
5990 fr_subtype is what the address relaxed to.
5991
5992 Out: Any fixSs and constants are set up.
5993 Caller will turn frag into a ".space 0". */
5994
252b5132
RH		 5995void
5996md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 5997 bfd *abfd ATTRIBUTE_UNUSED;
5998 segT sec ATTRIBUTE_UNUSED;
29b0f896 5999 fragS *fragP;
252b5132 6000{
29b0f896 6001 unsigned char *opcode;
252b5132 6002 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 6003 offsetT target_address;
6004 offsetT opcode_address;
252b5132 6005 unsigned int extension = 0;
847f7ad4 6006 offsetT displacement_from_opcode_start;
252b5132
RH		 6007
6008 opcode = (unsigned char *) fragP->fr_opcode;
6009
47926f60 6010 /* Address we want to reach in file space. */
252b5132 6011 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 6012
47926f60 6013 /* Address opcode resides at in file space. */
252b5132
RH		 6014 opcode_address = fragP->fr_address + fragP->fr_fix;
6015
47926f60 6016 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 6017 displacement_from_opcode_start = target_address - opcode_address;
6018
fddf5b5b 6019 if ((fragP->fr_subtype & BIG) == 0)
252b5132 6020 {
47926f60
KH		 6021 /* Don't have to change opcode. */
6022 extension = 1; /* 1 opcode + 1 displacement */
252b5132 6023 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 6024 }
6025 else
6026 {
6027 if (no_cond_jump_promotion
6028 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 6029 as_warn_where (fragP->fr_file, fragP->fr_line,
6030 _("long jump required"));
252b5132 6031
fddf5b5b
AM		 6032 switch (fragP->fr_subtype)
6033 {
6034 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6035 extension = 4; /* 1 opcode + 4 displacement */
6036 opcode[0] = 0xe9;
6037 where_to_put_displacement = &opcode[1];
6038 break;
252b5132 6039
fddf5b5b
AM		 6040 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6041 extension = 2; /* 1 opcode + 2 displacement */
6042 opcode[0] = 0xe9;
6043 where_to_put_displacement = &opcode[1];
6044 break;
252b5132 6045
fddf5b5b
AM		 6046 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6047 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6048 extension = 5; /* 2 opcode + 4 displacement */
6049 opcode[1] = opcode[0] + 0x10;
6050 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6051 where_to_put_displacement = &opcode[2];
6052 break;
252b5132 6053
fddf5b5b
AM		 6054 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6055 extension = 3; /* 2 opcode + 2 displacement */
6056 opcode[1] = opcode[0] + 0x10;
6057 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6058 where_to_put_displacement = &opcode[2];
6059 break;
252b5132 6060
fddf5b5b
AM		 6061 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6062 extension = 4;
6063 opcode[0] ^= 1;
6064 opcode[1] = 3;
6065 opcode[2] = 0xe9;
6066 where_to_put_displacement = &opcode[3];
6067 break;
6068
6069 default:
6070 BAD_CASE (fragP->fr_subtype);
6071 break;
6072 }
252b5132 6073 }
fddf5b5b 6074
7b81dfbb
AJ		 6075 /* If size if less then four we are sure that the operand fits,
6076 but if it's 4, then it could be that the displacement is larger
6077 then -/+ 2GB. */
6078 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6079 && object_64bit
6080 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 6081 + ((addressT) 1 << 31))
6082 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 6083 {
6084 as_bad_where (fragP->fr_file, fragP->fr_line,
6085 _("jump target out of range"));
6086 /* Make us emit 0. */
6087 displacement_from_opcode_start = extension;
6088 }
47926f60 6089 /* Now put displacement after opcode. */
252b5132
RH		 6090 md_number_to_chars ((char *) where_to_put_displacement,
6091 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 6092 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 6093 fragP->fr_fix += extension;
6094}
6095\f
47926f60
KH		 6096/* Size of byte displacement jmp. */
6097int md_short_jump_size = 2;
6098
6099/* Size of dword displacement jmp. */
6100int md_long_jump_size = 5;
252b5132 6101
252b5132
RH		 6102void
6103md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
6104 char *ptr;
6105 addressT from_addr, to_addr;
ab9da554
ILT		 6106 fragS *frag ATTRIBUTE_UNUSED;
6107 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 6108{
847f7ad4 6109 offsetT offset;
252b5132
RH		 6110
6111 offset = to_addr - (from_addr + 2);
47926f60
KH		 6112 /* Opcode for byte-disp jump. */
6113 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 6114 md_number_to_chars (ptr + 1, (valueT) offset, 1);
6115}
6116
6117void
6118md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
6119 char *ptr;
6120 addressT from_addr, to_addr;
a38cf1db
AM		 6121 fragS *frag ATTRIBUTE_UNUSED;
6122 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 6123{
847f7ad4 6124 offsetT offset;
252b5132 6125
a38cf1db
AM		 6126 offset = to_addr - (from_addr + 5);
6127 md_number_to_chars (ptr, (valueT) 0xe9, 1);
6128 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 6129}
6130\f
6131/* Apply a fixup (fixS) to segment data, once it has been determined
6132 by our caller that we have all the info we need to fix it up.
6133
6134 On the 386, immediates, displacements, and data pointers are all in
6135 the same (little-endian) format, so we don't need to care about which
6136 we are handling. */
6137
94f592af 6138void
55cf6793 6139md_apply_fix (fixP, valP, seg)
47926f60
KH		 6140 /* The fix we're to put in. */
6141 fixS *fixP;
47926f60 6142 /* Pointer to the value of the bits. */
c6682705 6143 valueT *valP;
47926f60
KH		 6144 /* Segment fix is from. */
6145 segT seg ATTRIBUTE_UNUSED;
252b5132 6146{
94f592af 6147 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 6148 valueT value = *valP;
252b5132 6149
f86103b7 6150#if !defined (TE_Mach)
93382f6d
AM		 6151 if (fixP->fx_pcrel)
6152 {
6153 switch (fixP->fx_r_type)
6154 {
5865bb77
ILT		 6155 default:
6156 break;
6157
d6ab8113
JB		 6158 case BFD_RELOC_64:
6159 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6160 break;
93382f6d 6161 case BFD_RELOC_32:
ae8887b5 6162 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 6163 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6164 break;
6165 case BFD_RELOC_16:
6166 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6167 break;
6168 case BFD_RELOC_8:
6169 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6170 break;
6171 }
6172 }
252b5132 6173
a161fe53 6174 if (fixP->fx_addsy != NULL
31312f95 6175 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 6176 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 6177 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6178 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6179 && !use_rela_relocations)
252b5132 6180 {
31312f95
AM		 6181 /* This is a hack. There should be a better way to handle this.
6182 This covers for the fact that bfd_install_relocation will
6183 subtract the current location (for partial_inplace, PC relative
6184 relocations); see more below. */
252b5132 6185#ifndef OBJ_AOUT
718ddfc0 6186 if (IS_ELF
252b5132
RH		 6187#ifdef TE_PE
6188 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6189#endif
6190 )
6191 value += fixP->fx_where + fixP->fx_frag->fr_address;
6192#endif
6193#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6194 if (IS_ELF)
252b5132 6195 {
6539b54b 6196 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 6197
6539b54b 6198 if ((sym_seg == seg
2f66722d 6199 || (symbol_section_p (fixP->fx_addsy)
6539b54b 6200 && sym_seg != absolute_section))
ae6063d4 6201 && !generic_force_reloc (fixP))
2f66722d
AM		 6202 {
6203 /* Yes, we add the values in twice. This is because
6539b54b
AM		 6204 bfd_install_relocation subtracts them out again. I think
6205 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 6206 it. FIXME. */
6207 value += fixP->fx_where + fixP->fx_frag->fr_address;
6208 }
252b5132
RH		 6209 }
6210#endif
6211#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 6212 /* For some reason, the PE format does not store a
6213 section address offset for a PC relative symbol. */
6214 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 6215 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 6216 value += md_pcrel_from (fixP);
6217#endif
6218 }
6219
6220 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 6221 and we must not disappoint it. */
252b5132 6222#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6223 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 6224 switch (fixP->fx_r_type)
6225 {
6226 case BFD_RELOC_386_PLT32:
3e73aa7c 6227 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 6228 /* Make the jump instruction point to the address of the operand. At
6229 runtime we merely add the offset to the actual PLT entry. */
6230 value = -4;
6231 break;
31312f95 6232
13ae64f3
JJ		 6233 case BFD_RELOC_386_TLS_GD:
6234 case BFD_RELOC_386_TLS_LDM:
13ae64f3 6235 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6236 case BFD_RELOC_386_TLS_IE:
6237 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 6238 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 6239 case BFD_RELOC_X86_64_TLSGD:
6240 case BFD_RELOC_X86_64_TLSLD:
6241 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 6242 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 6243 value = 0; /* Fully resolved at runtime. No addend. */
6244 /* Fallthrough */
6245 case BFD_RELOC_386_TLS_LE:
6246 case BFD_RELOC_386_TLS_LDO_32:
6247 case BFD_RELOC_386_TLS_LE_32:
6248 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6249 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 6250 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 6251 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 6252 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6253 break;
6254
67a4f2b7
AO		 6255 case BFD_RELOC_386_TLS_DESC_CALL:
6256 case BFD_RELOC_X86_64_TLSDESC_CALL:
6257 value = 0; /* Fully resolved at runtime. No addend. */
6258 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6259 fixP->fx_done = 0;
6260 return;
6261
00f7efb6
JJ		 6262 case BFD_RELOC_386_GOT32:
6263 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 6264 value = 0; /* Fully resolved at runtime. No addend. */
6265 break;
47926f60
KH		 6266
6267 case BFD_RELOC_VTABLE_INHERIT:
6268 case BFD_RELOC_VTABLE_ENTRY:
6269 fixP->fx_done = 0;
94f592af 6270 return;
47926f60
KH		 6271
6272 default:
6273 break;
6274 }
6275#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 6276 *valP = value;
f86103b7 6277#endif /* !defined (TE_Mach) */
3e73aa7c 6278
3e73aa7c 6279 /* Are we finished with this relocation now? */
c6682705 6280 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 6281 fixP->fx_done = 1;
6282 else if (use_rela_relocations)
6283 {
6284 fixP->fx_no_overflow = 1;
062cd5e7
AS		 6285 /* Remember value for tc_gen_reloc. */
6286 fixP->fx_addnumber = value;
3e73aa7c
JH		 6287 value = 0;
6288 }
f86103b7 6289
94f592af 6290 md_number_to_chars (p, value, fixP->fx_size);
252b5132 6291}
252b5132 6292\f
252b5132
RH		 6293#define MAX_LITTLENUMS 6
6294
47926f60
KH		 6295/* Turn the string pointed to by litP into a floating point constant
6296 of type TYPE, and emit the appropriate bytes. The number of
6297 LITTLENUMS emitted is stored in *SIZEP. An error message is
6298 returned, or NULL on OK. */
6299
252b5132
RH		 6300char *
6301md_atof (type, litP, sizeP)
2ab9b79e 6302 int type;
252b5132
RH		 6303 char *litP;
6304 int *sizeP;
6305{
6306 int prec;
6307 LITTLENUM_TYPE words[MAX_LITTLENUMS];
6308 LITTLENUM_TYPE *wordP;
6309 char *t;
6310
6311 switch (type)
6312 {
6313 case 'f':
6314 case 'F':
6315 prec = 2;
6316 break;
6317
6318 case 'd':
6319 case 'D':
6320 prec = 4;
6321 break;
6322
6323 case 'x':
6324 case 'X':
6325 prec = 5;
6326 break;
6327
6328 default:
6329 *sizeP = 0;
6330 return _("Bad call to md_atof ()");
6331 }
6332 t = atof_ieee (input_line_pointer, type, words);
6333 if (t)
6334 input_line_pointer = t;
6335
6336 *sizeP = prec * sizeof (LITTLENUM_TYPE);
6337 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
6338 the bigendian 386. */
6339 for (wordP = words + prec - 1; prec--;)
6340 {
6341 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
6342 litP += sizeof (LITTLENUM_TYPE);
6343 }
6344 return 0;
6345}
6346\f
2d545b82 6347static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 6348
252b5132 6349static char *
e3bb37b5 6350output_invalid (int c)
252b5132 6351{
3882b010 6352 if (ISPRINT (c))
f9f21a03
L		 6353 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6354 "'%c'", c);
252b5132 6355 else
f9f21a03 6356 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 6357 "(0x%x)", (unsigned char) c);
252b5132
RH		 6358 return output_invalid_buf;
6359}
6360
af6bdddf 6361/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 6362
6363static const reg_entry *
4d1bb795 6364parse_real_register (char *reg_string, char **end_op)
252b5132 6365{
af6bdddf
AM		 6366 char *s = reg_string;
6367 char *p;
252b5132
RH		 6368 char reg_name_given[MAX_REG_NAME_SIZE + 1];
6369 const reg_entry *r;
6370
6371 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6372 if (*s == REGISTER_PREFIX)
6373 ++s;
6374
6375 if (is_space_char (*s))
6376 ++s;
6377
6378 p = reg_name_given;
af6bdddf 6379 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 6380 {
6381 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 6382 return (const reg_entry *) NULL;
6383 s++;
252b5132
RH		 6384 }
6385
6588847e
DN		 6386 /* For naked regs, make sure that we are not dealing with an identifier.
6387 This prevents confusing an identifier like `eax_var' with register
6388 `eax'. */
6389 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
6390 return (const reg_entry *) NULL;
6391
af6bdddf 6392 *end_op = s;
252b5132
RH		 6393
6394 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
6395
5f47d35b 6396 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 6397 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 6398 {
5f47d35b
AM		 6399 if (is_space_char (*s))
6400 ++s;
6401 if (*s == '(')
6402 {
af6bdddf 6403 ++s;
5f47d35b
AM		 6404 if (is_space_char (*s))
6405 ++s;
6406 if (*s >= '0' && *s <= '7')
6407 {
db557034 6408 int fpr = *s - '0';
af6bdddf 6409 ++s;
5f47d35b
AM		 6410 if (is_space_char (*s))
6411 ++s;
6412 if (*s == ')')
6413 {
6414 *end_op = s + 1;
db557034
AM		 6415 r = hash_find (reg_hash, "st(0)");
6416 know (r);
6417 return r + fpr;
5f47d35b 6418 }
5f47d35b 6419 }
47926f60 6420 /* We have "%st(" then garbage. */
5f47d35b
AM		 6421 return (const reg_entry *) NULL;
6422 }
6423 }
6424
1ae00879 6425 if (r != NULL
d946b91f 6426 && ((r->reg_flags & (RegRex64 | RegRex))
40fb9820
L		 6427 || r->reg_type.bitfield.reg64)
6428 && (!cpu_arch_flags.bitfield.cpulm
6429 || memcmp (&r->reg_type, &control, sizeof (control)))
1ae00879 6430 && flag_code != CODE_64BIT)
20f0a1fc 6431 return (const reg_entry *) NULL;
1ae00879 6432
252b5132
RH		 6433 return r;
6434}
4d1bb795
JB		 6435
6436/* REG_STRING starts *before* REGISTER_PREFIX. */
6437
6438static const reg_entry *
6439parse_register (char *reg_string, char **end_op)
6440{
6441 const reg_entry *r;
6442
6443 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
6444 r = parse_real_register (reg_string, end_op);
6445 else
6446 r = NULL;
6447 if (!r)
6448 {
6449 char *save = input_line_pointer;
6450 char c;
6451 symbolS *symbolP;
6452
6453 input_line_pointer = reg_string;
6454 c = get_symbol_end ();
6455 symbolP = symbol_find (reg_string);
6456 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
6457 {
6458 const expressionS *e = symbol_get_value_expression (symbolP);
6459
6460 know (e->X_op == O_register);
4eed87de 6461 know (e->X_add_number >= 0
c3fe08fa 6462 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 6463 r = i386_regtab + e->X_add_number;
6464 *end_op = input_line_pointer;
6465 }
6466 *input_line_pointer = c;
6467 input_line_pointer = save;
6468 }
6469 return r;
6470}
6471
6472int
6473i386_parse_name (char *name, expressionS *e, char *nextcharP)
6474{
6475 const reg_entry *r;
6476 char *end = input_line_pointer;
6477
6478 *end = *nextcharP;
6479 r = parse_register (name, &input_line_pointer);
6480 if (r && end <= input_line_pointer)
6481 {
6482 *nextcharP = *input_line_pointer;
6483 *input_line_pointer = 0;
6484 e->X_op = O_register;
6485 e->X_add_number = r - i386_regtab;
6486 return 1;
6487 }
6488 input_line_pointer = end;
6489 *end = 0;
6490 return 0;
6491}
6492
6493void
6494md_operand (expressionS *e)
6495{
6496 if (*input_line_pointer == REGISTER_PREFIX)
6497 {
6498 char *end;
6499 const reg_entry *r = parse_real_register (input_line_pointer, &end);
6500
6501 if (r)
6502 {
6503 e->X_op = O_register;
6504 e->X_add_number = r - i386_regtab;
6505 input_line_pointer = end;
6506 }
6507 }
6508}
6509
252b5132 6510\f
4cc782b5 6511#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 6512const char *md_shortopts = "kVQ:sqn";
252b5132 6513#else
12b55ccc 6514const char *md_shortopts = "qn";
252b5132 6515#endif
6e0b89ee 6516
3e73aa7c 6517#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 6518#define OPTION_64 (OPTION_MD_BASE + 1)
6519#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 6520#define OPTION_MARCH (OPTION_MD_BASE + 3)
6521#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 6522
99ad8390
NC		 6523struct option md_longopts[] =
6524{
3e73aa7c 6525 {"32", no_argument, NULL, OPTION_32},
99ad8390 6526#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 6527 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 6528#endif
b3b91714 6529 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 6530 {"march", required_argument, NULL, OPTION_MARCH},
6531 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 6532 {NULL, no_argument, NULL, 0}
6533};
6534size_t md_longopts_size = sizeof (md_longopts);
6535
6536int
9103f4f4 6537md_parse_option (int c, char *arg)
252b5132 6538{
9103f4f4
L		 6539 unsigned int i;
6540
252b5132
RH		 6541 switch (c)
6542 {
12b55ccc
L		 6543 case 'n':
6544 optimize_align_code = 0;
6545 break;
6546
a38cf1db
AM		 6547 case 'q':
6548 quiet_warnings = 1;
252b5132
RH		 6549 break;
6550
6551#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 6552 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6553 should be emitted or not. FIXME: Not implemented. */
6554 case 'Q':
252b5132
RH		 6555 break;
6556
6557 /* -V: SVR4 argument to print version ID. */
6558 case 'V':
6559 print_version_id ();
6560 break;
6561
a38cf1db
AM		 6562 /* -k: Ignore for FreeBSD compatibility. */
6563 case 'k':
252b5132 6564 break;
4cc782b5
ILT		 6565
6566 case 's':
6567 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 6568 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 6569 break;
99ad8390
NC		 6570#endif
6571#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 6572 case OPTION_64:
6573 {
6574 const char **list, **l;
6575
3e73aa7c
JH		 6576 list = bfd_target_list ();
6577 for (l = list; *l != NULL; l++)
8620418b 6578 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 6579 || strcmp (*l, "coff-x86-64") == 0
6580 || strcmp (*l, "pe-x86-64") == 0
6581 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 6582 {
6583 default_arch = "x86_64";
6584 break;
6585 }
3e73aa7c 6586 if (*l == NULL)
6e0b89ee 6587 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 6588 free (list);
6589 }
6590 break;
6591#endif
252b5132 6592
6e0b89ee
AM		 6593 case OPTION_32:
6594 default_arch = "i386";
6595 break;
6596
b3b91714
AM		 6597 case OPTION_DIVIDE:
6598#ifdef SVR4_COMMENT_CHARS
6599 {
6600 char *n, *t;
6601 const char *s;
6602
6603 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
6604 t = n;
6605 for (s = i386_comment_chars; *s != '\0'; s++)
6606 if (*s != '/')
6607 *t++ = *s;
6608 *t = '\0';
6609 i386_comment_chars = n;
6610 }
6611#endif
6612 break;
6613
9103f4f4
L		 6614 case OPTION_MARCH:
6615 if (*arg == '.')
6616 as_fatal (_("Invalid -march= option: `%s'"), arg);
6617 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
6618 {
6619 if (strcmp (arg, cpu_arch [i].name) == 0)
6620 {
ccc9c027 6621 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 6622 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 6623 if (!cpu_arch_tune_set)
6624 {
6625 cpu_arch_tune = cpu_arch_isa;
6626 cpu_arch_tune_flags = cpu_arch_isa_flags;
6627 }
9103f4f4
L		 6628 break;
6629 }
6630 }
6631 if (i >= ARRAY_SIZE (cpu_arch))
6632 as_fatal (_("Invalid -march= option: `%s'"), arg);
6633 break;
6634
6635 case OPTION_MTUNE:
6636 if (*arg == '.')
6637 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6638 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
6639 {
6640 if (strcmp (arg, cpu_arch [i].name) == 0)
6641 {
ccc9c027 6642 cpu_arch_tune_set = 1;
9103f4f4
L		 6643 cpu_arch_tune = cpu_arch [i].type;
6644 cpu_arch_tune_flags = cpu_arch[i].flags;
6645 break;
6646 }
6647 }
6648 if (i >= ARRAY_SIZE (cpu_arch))
6649 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6650 break;
6651
252b5132
RH		 6652 default:
6653 return 0;
6654 }
6655 return 1;
6656}
6657
6658void
6659md_show_usage (stream)
6660 FILE *stream;
6661{
4cc782b5
ILT		 6662#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6663 fprintf (stream, _("\
a38cf1db
AM		 6664 -Q ignored\n\
6665 -V print assembler version number\n\
b3b91714
AM		 6666 -k ignored\n"));
6667#endif
6668 fprintf (stream, _("\
12b55ccc 6669 -n Do not optimize code alignment\n\
b3b91714
AM		 6670 -q quieten some warnings\n"));
6671#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6672 fprintf (stream, _("\
a38cf1db 6673 -s ignored\n"));
b3b91714 6674#endif
751d281c
L		 6675#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6676 fprintf (stream, _("\
6677 --32/--64 generate 32bit/64bit code\n"));
6678#endif
b3b91714
AM		 6679#ifdef SVR4_COMMENT_CHARS
6680 fprintf (stream, _("\
6681 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 6682#else
6683 fprintf (stream, _("\
b3b91714 6684 --divide ignored\n"));
4cc782b5 6685#endif
9103f4f4
L		 6686 fprintf (stream, _("\
6687 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6688 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 6689 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 6690
252b5132
RH		 6691}
6692
3e73aa7c 6693#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 6694 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 6695
6696/* Pick the target format to use. */
6697
47926f60 6698const char *
e3bb37b5 6699i386_target_format (void)
252b5132 6700{
3e73aa7c 6701 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 6702 {
6703 set_code_flag (CODE_64BIT);
40fb9820
L		 6704 if (cpu_flags_all_zero (cpu_arch_isa_flags))
6705 {
6706 cpu_arch_isa_flags.bitfield.cpui186 = 1;
6707 cpu_arch_isa_flags.bitfield.cpui286 = 1;
6708 cpu_arch_isa_flags.bitfield.cpui386 = 1;
6709 cpu_arch_isa_flags.bitfield.cpui486 = 1;
6710 cpu_arch_isa_flags.bitfield.cpui586 = 1;
6711 cpu_arch_isa_flags.bitfield.cpui686 = 1;
6712 cpu_arch_isa_flags.bitfield.cpup4 = 1;
6713 cpu_arch_isa_flags.bitfield.cpummx= 1;
6714 cpu_arch_isa_flags.bitfield.cpummx2 = 1;
6715 cpu_arch_isa_flags.bitfield.cpusse = 1;
6716 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
6717 }
6718 if (cpu_flags_all_zero (cpu_arch_tune_flags))
6719 {
6720 cpu_arch_tune_flags.bitfield.cpui186 = 1;
6721 cpu_arch_tune_flags.bitfield.cpui286 = 1;
6722 cpu_arch_tune_flags.bitfield.cpui386 = 1;
6723 cpu_arch_tune_flags.bitfield.cpui486 = 1;
6724 cpu_arch_tune_flags.bitfield.cpui586 = 1;
6725 cpu_arch_tune_flags.bitfield.cpui686 = 1;
6726 cpu_arch_tune_flags.bitfield.cpup4 = 1;
6727 cpu_arch_tune_flags.bitfield.cpummx= 1;
6728 cpu_arch_tune_flags.bitfield.cpummx2 = 1;
6729 cpu_arch_tune_flags.bitfield.cpusse = 1;
6730 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
6731 }
9103f4f4 6732 }
3e73aa7c 6733 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 6734 {
6735 set_code_flag (CODE_32BIT);
40fb9820
L		 6736 if (cpu_flags_all_zero (cpu_arch_isa_flags))
6737 {
6738 cpu_arch_isa_flags.bitfield.cpui186 = 1;
6739 cpu_arch_isa_flags.bitfield.cpui286 = 1;
6740 cpu_arch_isa_flags.bitfield.cpui386 = 1;
6741 }
6742 if (cpu_flags_all_zero (cpu_arch_tune_flags))
6743 {
6744 cpu_arch_tune_flags.bitfield.cpui186 = 1;
6745 cpu_arch_tune_flags.bitfield.cpui286 = 1;
6746 cpu_arch_tune_flags.bitfield.cpui386 = 1;
6747 }
9103f4f4 6748 }
3e73aa7c
JH		 6749 else
6750 as_fatal (_("Unknown architecture"));
252b5132
RH		 6751 switch (OUTPUT_FLAVOR)
6752 {
872ce6ff
L		 6753#ifdef TE_PEP
6754 case bfd_target_coff_flavour:
6755 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
6756 break;
6757#endif
4c63da97
AM		 6758#ifdef OBJ_MAYBE_AOUT
6759 case bfd_target_aout_flavour:
47926f60 6760 return AOUT_TARGET_FORMAT;
4c63da97
AM		 6761#endif
6762#ifdef OBJ_MAYBE_COFF
252b5132
RH		 6763 case bfd_target_coff_flavour:
6764 return "coff-i386";
4c63da97 6765#endif
3e73aa7c 6766#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 6767 case bfd_target_elf_flavour:
3e73aa7c 6768 {
e5cb08ac 6769 if (flag_code == CODE_64BIT)
4fa24527
JB		 6770 {
6771 object_64bit = 1;
6772 use_rela_relocations = 1;
6773 }
9d7cbccd 6774 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6775 }
4c63da97 6776#endif
252b5132
RH		 6777 default:
6778 abort ();
6779 return NULL;
6780 }
6781}
6782
47926f60 6783#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 6784
6785#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 6786void
6787i386_elf_emit_arch_note (void)
a847613f 6788{
718ddfc0 6789 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 6790 {
6791 char *p;
6792 asection *seg = now_seg;
6793 subsegT subseg = now_subseg;
6794 Elf_Internal_Note i_note;
6795 Elf_External_Note e_note;
6796 asection *note_secp;
6797 int len;
6798
6799 /* Create the .note section. */
6800 note_secp = subseg_new (".note", 0);
6801 bfd_set_section_flags (stdoutput,
6802 note_secp,
6803 SEC_HAS_CONTENTS | SEC_READONLY);
6804
6805 /* Process the arch string. */
6806 len = strlen (cpu_arch_name);
6807
6808 i_note.namesz = len + 1;
6809 i_note.descsz = 0;
6810 i_note.type = NT_ARCH;
6811 p = frag_more (sizeof (e_note.namesz));
6812 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6813 p = frag_more (sizeof (e_note.descsz));
6814 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6815 p = frag_more (sizeof (e_note.type));
6816 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6817 p = frag_more (len + 1);
6818 strcpy (p, cpu_arch_name);
6819
6820 frag_align (2, 0, 0);
6821
6822 subseg_set (seg, subseg);
6823 }
6824}
6825#endif
252b5132 6826\f
252b5132
RH		 6827symbolS *
6828md_undefined_symbol (name)
6829 char *name;
6830{
18dc2407
ILT		 6831 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6832 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6833 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6834 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6835 {
6836 if (!GOT_symbol)
6837 {
6838 if (symbol_find (name))
6839 as_bad (_("GOT already in symbol table"));
6840 GOT_symbol = symbol_new (name, undefined_section,
6841 (valueT) 0, &zero_address_frag);
6842 };
6843 return GOT_symbol;
6844 }
252b5132
RH		 6845 return 0;
6846}
6847
6848/* Round up a section size to the appropriate boundary. */
47926f60 6849
252b5132
RH		 6850valueT
6851md_section_align (segment, size)
ab9da554 6852 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6853 valueT size;
6854{
4c63da97
AM		 6855#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6856 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6857 {
6858 /* For a.out, force the section size to be aligned. If we don't do
6859 this, BFD will align it for us, but it will not write out the
6860 final bytes of the section. This may be a bug in BFD, but it is
6861 easier to fix it here since that is how the other a.out targets
6862 work. */
6863 int align;
6864
6865 align = bfd_get_section_alignment (stdoutput, segment);
6866 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6867 }
252b5132
RH		 6868#endif
6869
6870 return size;
6871}
6872
6873/* On the i386, PC-relative offsets are relative to the start of the
6874 next instruction. That is, the address of the offset, plus its
6875 size, since the offset is always the last part of the insn. */
6876
6877long
e3bb37b5 6878md_pcrel_from (fixS *fixP)
252b5132
RH		 6879{
6880 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6881}
6882
6883#ifndef I386COFF
6884
6885static void
e3bb37b5 6886s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 6887{
29b0f896 6888 int temp;
252b5132 6889
8a75718c
JB		 6890#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6891 if (IS_ELF)
6892 obj_elf_section_change_hook ();
6893#endif
252b5132
RH		 6894 temp = get_absolute_expression ();
6895 subseg_set (bss_section, (subsegT) temp);
6896 demand_empty_rest_of_line ();
6897}
6898
6899#endif
6900
252b5132 6901void
e3bb37b5 6902i386_validate_fix (fixS *fixp)
252b5132
RH		 6903{
6904 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6905 {
23df1078
JH		 6906 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6907 {
4fa24527 6908 if (!object_64bit)
23df1078
JH		 6909 abort ();
6910 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6911 }
6912 else
6913 {
4fa24527 6914 if (!object_64bit)
d6ab8113
JB		 6915 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6916 else
6917 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6918 }
252b5132
RH		 6919 fixp->fx_subsy = 0;
6920 }
6921}
6922
252b5132
RH		 6923arelent *
6924tc_gen_reloc (section, fixp)
ab9da554 6925 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6926 fixS *fixp;
6927{
6928 arelent *rel;
6929 bfd_reloc_code_real_type code;
6930
6931 switch (fixp->fx_r_type)
6932 {
3e73aa7c
JH		 6933 case BFD_RELOC_X86_64_PLT32:
6934 case BFD_RELOC_X86_64_GOT32:
6935 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6936 case BFD_RELOC_386_PLT32:
6937 case BFD_RELOC_386_GOT32:
6938 case BFD_RELOC_386_GOTOFF:
6939 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 6940 case BFD_RELOC_386_TLS_GD:
6941 case BFD_RELOC_386_TLS_LDM:
6942 case BFD_RELOC_386_TLS_LDO_32:
6943 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6944 case BFD_RELOC_386_TLS_IE:
6945 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 6946 case BFD_RELOC_386_TLS_LE_32:
6947 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 6948 case BFD_RELOC_386_TLS_GOTDESC:
6949 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 6950 case BFD_RELOC_X86_64_TLSGD:
6951 case BFD_RELOC_X86_64_TLSLD:
6952 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6953 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 6954 case BFD_RELOC_X86_64_GOTTPOFF:
6955 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 6956 case BFD_RELOC_X86_64_TPOFF64:
6957 case BFD_RELOC_X86_64_GOTOFF64:
6958 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 6959 case BFD_RELOC_X86_64_GOT64:
6960 case BFD_RELOC_X86_64_GOTPCREL64:
6961 case BFD_RELOC_X86_64_GOTPC64:
6962 case BFD_RELOC_X86_64_GOTPLT64:
6963 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 6964 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6965 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 6966 case BFD_RELOC_RVA:
6967 case BFD_RELOC_VTABLE_ENTRY:
6968 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 6969#ifdef TE_PE
6970 case BFD_RELOC_32_SECREL:
6971#endif
252b5132
RH		 6972 code = fixp->fx_r_type;
6973 break;
dbbaec26
L		 6974 case BFD_RELOC_X86_64_32S:
6975 if (!fixp->fx_pcrel)
6976 {
6977 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6978 code = fixp->fx_r_type;
6979 break;
6980 }
252b5132 6981 default:
93382f6d 6982 if (fixp->fx_pcrel)
252b5132 6983 {
93382f6d
AM		 6984 switch (fixp->fx_size)
6985 {
6986 default:
b091f402
AM		 6987 as_bad_where (fixp->fx_file, fixp->fx_line,
6988 _("can not do %d byte pc-relative relocation"),
6989 fixp->fx_size);
93382f6d
AM		 6990 code = BFD_RELOC_32_PCREL;
6991 break;
6992 case 1: code = BFD_RELOC_8_PCREL; break;
6993 case 2: code = BFD_RELOC_16_PCREL; break;
6994 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 6995#ifdef BFD64
6996 case 8: code = BFD_RELOC_64_PCREL; break;
6997#endif
93382f6d
AM		 6998 }
6999 }
7000 else
7001 {
7002 switch (fixp->fx_size)
7003 {
7004 default:
b091f402
AM		 7005 as_bad_where (fixp->fx_file, fixp->fx_line,
7006 _("can not do %d byte relocation"),
7007 fixp->fx_size);
93382f6d
AM		 7008 code = BFD_RELOC_32;
7009 break;
7010 case 1: code = BFD_RELOC_8; break;
7011 case 2: code = BFD_RELOC_16; break;
7012 case 4: code = BFD_RELOC_32; break;
937149dd 7013#ifdef BFD64
3e73aa7c 7014 case 8: code = BFD_RELOC_64; break;
937149dd 7015#endif
93382f6d 7016 }
252b5132
RH		 7017 }
7018 break;
7019 }
252b5132 7020
d182319b
JB		 7021 if ((code == BFD_RELOC_32
7022 || code == BFD_RELOC_32_PCREL
7023 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 7024 && GOT_symbol
7025 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 7026 {
4fa24527 7027 if (!object_64bit)
d6ab8113
JB		 7028 code = BFD_RELOC_386_GOTPC;
7029 else
7030 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 7031 }
7b81dfbb
AJ		 7032 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7033 && GOT_symbol
7034 && fixp->fx_addsy == GOT_symbol)
7035 {
7036 code = BFD_RELOC_X86_64_GOTPC64;
7037 }
252b5132
RH		 7038
7039 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 7040 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7041 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 7042
7043 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 7044
3e73aa7c
JH		 7045 if (!use_rela_relocations)
7046 {
7047 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7048 vtable entry to be used in the relocation's section offset. */
7049 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7050 rel->address = fixp->fx_offset;
252b5132 7051
c6682705 7052 rel->addend = 0;
3e73aa7c
JH		 7053 }
7054 /* Use the rela in 64bit mode. */
252b5132 7055 else
3e73aa7c 7056 {
062cd5e7
AS		 7057 if (!fixp->fx_pcrel)
7058 rel->addend = fixp->fx_offset;
7059 else
7060 switch (code)
7061 {
7062 case BFD_RELOC_X86_64_PLT32:
7063 case BFD_RELOC_X86_64_GOT32:
7064 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 7065 case BFD_RELOC_X86_64_TLSGD:
7066 case BFD_RELOC_X86_64_TLSLD:
7067 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 7068 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7069 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 7070 rel->addend = fixp->fx_offset - fixp->fx_size;
7071 break;
7072 default:
7073 rel->addend = (section->vma
7074 - fixp->fx_size
7075 + fixp->fx_addnumber
7076 + md_pcrel_from (fixp));
7077 break;
7078 }
3e73aa7c
JH		 7079 }
7080
252b5132
RH		 7081 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7082 if (rel->howto == NULL)
7083 {
7084 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 7085 _("cannot represent relocation type %s"),
252b5132
RH		 7086 bfd_get_reloc_code_name (code));
7087 /* Set howto to a garbage value so that we can keep going. */
7088 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7089 assert (rel->howto != NULL);
7090 }
7091
7092 return rel;
7093}
7094
64a0c779
DN		 7095\f
7096/* Parse operands using Intel syntax. This implements a recursive descent
7097 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7098 Programmer's Guide.
7099
7100 FIXME: We do not recognize the full operand grammar defined in the MASM
7101 documentation. In particular, all the structure/union and
7102 high-level macro operands are missing.
7103
7104 Uppercase words are terminals, lower case words are non-terminals.
7105 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7106 bars '|' denote choices. Most grammar productions are implemented in
7107 functions called 'intel_<production>'.
7108
7109 Initial production is 'expr'.
7110
9306ca4a 7111 addOp + | -
64a0c779
DN		 7112
7113 alpha [a-zA-Z]
7114
9306ca4a
JB		 7115 binOp & | AND | \| | OR | ^ | XOR
7116
64a0c779
DN		 7117 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7118
7119 constant digits [[ radixOverride ]]
7120
9306ca4a 7121 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 7122
7123 digits decdigit
b77a7acd
AJ		 7124 | digits decdigit
7125 | digits hexdigit
64a0c779
DN		 7126
7127 decdigit [0-9]
7128
9306ca4a
JB		 7129 e04 e04 addOp e05
7130 | e05
7131
7132 e05 e05 binOp e06
b77a7acd 7133 | e06
64a0c779
DN		 7134
7135 e06 e06 mulOp e09
b77a7acd 7136 | e09
64a0c779
DN		 7137
7138 e09 OFFSET e10
a724f0f4
JB		 7139 | SHORT e10
7140 | + e10
7141 | - e10
9306ca4a
JB		 7142 | ~ e10
7143 | NOT e10
64a0c779
DN		 7144 | e09 PTR e10
7145 | e09 : e10
7146 | e10
7147
7148 e10 e10 [ expr ]
b77a7acd 7149 | e11
64a0c779
DN		 7150
7151 e11 ( expr )
b77a7acd 7152 | [ expr ]
64a0c779
DN		 7153 | constant
7154 | dataType
7155 | id
7156 | $
7157 | register
7158
a724f0f4 7159 => expr expr cmpOp e04
9306ca4a 7160 | e04
64a0c779
DN		 7161
7162 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 7163 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 7164
7165 hexdigit a | b | c | d | e | f
b77a7acd 7166 | A | B | C | D | E | F
64a0c779
DN		 7167
7168 id alpha
b77a7acd 7169 | id alpha
64a0c779
DN		 7170 | id decdigit
7171
9306ca4a 7172 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 7173
7174 quote " | '
7175
7176 register specialRegister
b77a7acd 7177 | gpRegister
64a0c779
DN		 7178 | byteRegister
7179
7180 segmentRegister CS | DS | ES | FS | GS | SS
7181
9306ca4a 7182 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 7183 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 7184 | TR3 | TR4 | TR5 | TR6 | TR7
7185
64a0c779
DN		 7186 We simplify the grammar in obvious places (e.g., register parsing is
7187 done by calling parse_register) and eliminate immediate left recursion
7188 to implement a recursive-descent parser.
7189
a724f0f4
JB		 7190 expr e04 expr'
7191
7192 expr' cmpOp e04 expr'
7193 | Empty
9306ca4a
JB		 7194
7195 e04 e05 e04'
7196
7197 e04' addOp e05 e04'
7198 | Empty
64a0c779
DN		 7199
7200 e05 e06 e05'
7201
9306ca4a 7202 e05' binOp e06 e05'
b77a7acd 7203 | Empty
64a0c779
DN		 7204
7205 e06 e09 e06'
7206
7207 e06' mulOp e09 e06'
b77a7acd 7208 | Empty
64a0c779
DN		 7209
7210 e09 OFFSET e10 e09'
a724f0f4
JB		 7211 | SHORT e10'
7212 | + e10'
7213 | - e10'
7214 | ~ e10'
7215 | NOT e10'
b77a7acd 7216 | e10 e09'
64a0c779
DN		 7217
7218 e09' PTR e10 e09'
b77a7acd 7219 | : e10 e09'
64a0c779
DN		 7220 | Empty
7221
7222 e10 e11 e10'
7223
7224 e10' [ expr ] e10'
b77a7acd 7225 | Empty
64a0c779
DN		 7226
7227 e11 ( expr )
b77a7acd 7228 | [ expr ]
64a0c779
DN		 7229 | BYTE
7230 | WORD
7231 | DWORD
9306ca4a 7232 | FWORD
64a0c779 7233 | QWORD
9306ca4a
JB		 7234 | TBYTE
7235 | OWORD
7236 | XMMWORD
64a0c779
DN		 7237 | .
7238 | $
7239 | register
7240 | id
7241 | constant */
7242
7243/* Parsing structure for the intel syntax parser. Used to implement the
7244 semantic actions for the operand grammar. */
7245struct intel_parser_s
7246 {
7247 char *op_string; /* The string being parsed. */
7248 int got_a_float; /* Whether the operand is a float. */
4a1805b1 7249 int op_modifier; /* Operand modifier. */
64a0c779 7250 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 7251 int in_offset; /* >=1 if parsing operand of offset. */
7252 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 7253 const reg_entry *reg; /* Last register reference found. */
7254 char *disp; /* Displacement string being built. */
a724f0f4 7255 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 7256 };
7257
7258static struct intel_parser_s intel_parser;
7259
7260/* Token structure for parsing intel syntax. */
7261struct intel_token
7262 {
7263 int code; /* Token code. */
7264 const reg_entry *reg; /* Register entry for register tokens. */
7265 char *str; /* String representation. */
7266 };
7267
7268static struct intel_token cur_token, prev_token;
7269
50705ef4
AM		 7270/* Token codes for the intel parser. Since T_SHORT is already used
7271 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 7272#define T_NIL -1
7273#define T_CONST 1
7274#define T_REG 2
7275#define T_BYTE 3
7276#define T_WORD 4
9306ca4a
JB		 7277#define T_DWORD 5
7278#define T_FWORD 6
7279#define T_QWORD 7
7280#define T_TBYTE 8
7281#define T_XMMWORD 9
50705ef4 7282#undef T_SHORT
9306ca4a
JB		 7283#define T_SHORT 10
7284#define T_OFFSET 11
7285#define T_PTR 12
7286#define T_ID 13
7287#define T_SHL 14
7288#define T_SHR 15
64a0c779
DN		 7289
7290/* Prototypes for intel parser functions. */
e3bb37b5
L		 7291static int intel_match_token (int);
7292static void intel_putback_token (void);
7293static void intel_get_token (void);
7294static int intel_expr (void);
7295static int intel_e04 (void);
7296static int intel_e05 (void);
7297static int intel_e06 (void);
7298static int intel_e09 (void);
7299static int intel_e10 (void);
7300static int intel_e11 (void);
64a0c779 7301
64a0c779 7302static int
e3bb37b5 7303i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 7304{
7305 int ret;
7306 char *p;
7307
a724f0f4
JB		 7308 p = intel_parser.op_string = xstrdup (operand_string);
7309 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
7310
7311 for (;;)
64a0c779 7312 {
a724f0f4
JB		 7313 /* Initialize token holders. */
7314 cur_token.code = prev_token.code = T_NIL;
7315 cur_token.reg = prev_token.reg = NULL;
7316 cur_token.str = prev_token.str = NULL;
7317
7318 /* Initialize parser structure. */
7319 intel_parser.got_a_float = got_a_float;
7320 intel_parser.op_modifier = 0;
7321 intel_parser.is_mem = 0;
7322 intel_parser.in_offset = 0;
7323 intel_parser.in_bracket = 0;
7324 intel_parser.reg = NULL;
7325 intel_parser.disp[0] = '\0';
7326 intel_parser.next_operand = NULL;
7327
7328 /* Read the first token and start the parser. */
7329 intel_get_token ();
7330 ret = intel_expr ();
7331
7332 if (!ret)
7333 break;
7334
9306ca4a
JB		 7335 if (cur_token.code != T_NIL)
7336 {
7337 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7338 current_templates->start->name, cur_token.str);
7339 ret = 0;
7340 }
64a0c779
DN		 7341 /* If we found a memory reference, hand it over to i386_displacement
7342 to fill in the rest of the operand fields. */
9306ca4a 7343 else if (intel_parser.is_mem)
64a0c779
DN		 7344 {
7345 if ((i.mem_operands == 1
40fb9820 7346 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 7347 || i.mem_operands == 2)
7348 {
7349 as_bad (_("too many memory references for '%s'"),
7350 current_templates->start->name);
7351 ret = 0;
7352 }
7353 else
7354 {
7355 char *s = intel_parser.disp;
7356 i.mem_operands++;
7357
a724f0f4
JB		 7358 if (!quiet_warnings && intel_parser.is_mem < 0)
7359 /* See the comments in intel_bracket_expr. */
7360 as_warn (_("Treating `%s' as memory reference"), operand_string);
7361
64a0c779
DN		 7362 /* Add the displacement expression. */
7363 if (*s != '\0')
a4622f40
AM		 7364 ret = i386_displacement (s, s + strlen (s));
7365 if (ret)
a724f0f4
JB		 7366 {
7367 /* Swap base and index in 16-bit memory operands like
7368 [si+bx]. Since i386_index_check is also used in AT&T
7369 mode we have to do that here. */
7370 if (i.base_reg
7371 && i.index_reg
40fb9820
L		 7372 && i.base_reg->reg_type.bitfield.reg16
7373 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 7374 && i.base_reg->reg_num >= 6
7375 && i.index_reg->reg_num < 6)
7376 {
7377 const reg_entry *base = i.index_reg;
7378
7379 i.index_reg = i.base_reg;
7380 i.base_reg = base;
7381 }
7382 ret = i386_index_check (operand_string);
7383 }
64a0c779
DN		 7384 }
7385 }
7386
7387 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 7388 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 7389 || intel_parser.reg == NULL)
7390 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 7391
7392 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 7393 ret = 0;
a724f0f4
JB		 7394 if (!ret || !intel_parser.next_operand)
7395 break;
7396 intel_parser.op_string = intel_parser.next_operand;
7397 this_operand = i.operands++;
64a0c779
DN		 7398 }
7399
7400 free (p);
7401 free (intel_parser.disp);
7402
7403 return ret;
7404}
7405
a724f0f4
JB		 7406#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7407
7408/* expr e04 expr'
7409
7410 expr' cmpOp e04 expr'
7411 | Empty */
64a0c779 7412static int
e3bb37b5 7413intel_expr (void)
64a0c779 7414{
a724f0f4
JB		 7415 /* XXX Implement the comparison operators. */
7416 return intel_e04 ();
9306ca4a
JB		 7417}
7418
a724f0f4 7419/* e04 e05 e04'
9306ca4a 7420
a724f0f4 7421 e04' addOp e05 e04'
9306ca4a
JB		 7422 | Empty */
7423static int
e3bb37b5 7424intel_e04 (void)
9306ca4a 7425{
a724f0f4 7426 int nregs = -1;
9306ca4a 7427
a724f0f4 7428 for (;;)
9306ca4a 7429 {
a724f0f4
JB		 7430 if (!intel_e05())
7431 return 0;
9306ca4a 7432
a724f0f4
JB		 7433 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7434 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 7435
a724f0f4
JB		 7436 if (cur_token.code == '+')
7437 nregs = -1;
7438 else if (cur_token.code == '-')
7439 nregs = NUM_ADDRESS_REGS;
7440 else
7441 return 1;
64a0c779 7442
a724f0f4
JB		 7443 strcat (intel_parser.disp, cur_token.str);
7444 intel_match_token (cur_token.code);
7445 }
64a0c779
DN		 7446}
7447
64a0c779
DN		 7448/* e05 e06 e05'
7449
9306ca4a 7450 e05' binOp e06 e05'
64a0c779
DN		 7451 | Empty */
7452static int
e3bb37b5 7453intel_e05 (void)
64a0c779 7454{
a724f0f4 7455 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 7456
a724f0f4 7457 for (;;)
64a0c779 7458 {
a724f0f4
JB		 7459 if (!intel_e06())
7460 return 0;
7461
4eed87de
AM		 7462 if (cur_token.code == '&'
7463 || cur_token.code == '|'
7464 || cur_token.code == '^')
a724f0f4
JB		 7465 {
7466 char str[2];
7467
7468 str[0] = cur_token.code;
7469 str[1] = 0;
7470 strcat (intel_parser.disp, str);
7471 }
7472 else
7473 break;
9306ca4a 7474
64a0c779
DN		 7475 intel_match_token (cur_token.code);
7476
a724f0f4
JB		 7477 if (nregs < 0)
7478 nregs = ~nregs;
64a0c779 7479 }
a724f0f4
JB		 7480 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7481 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
7482 return 1;
4a1805b1 7483}
64a0c779
DN		 7484
7485/* e06 e09 e06'
7486
7487 e06' mulOp e09 e06'
b77a7acd 7488 | Empty */
64a0c779 7489static int
e3bb37b5 7490intel_e06 (void)
64a0c779 7491{
a724f0f4 7492 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 7493
a724f0f4 7494 for (;;)
64a0c779 7495 {
a724f0f4
JB		 7496 if (!intel_e09())
7497 return 0;
9306ca4a 7498
4eed87de
AM		 7499 if (cur_token.code == '*'
7500 || cur_token.code == '/'
7501 || cur_token.code == '%')
a724f0f4
JB		 7502 {
7503 char str[2];
9306ca4a 7504
a724f0f4
JB		 7505 str[0] = cur_token.code;
7506 str[1] = 0;
7507 strcat (intel_parser.disp, str);
7508 }
7509 else if (cur_token.code == T_SHL)
7510 strcat (intel_parser.disp, "<<");
7511 else if (cur_token.code == T_SHR)
7512 strcat (intel_parser.disp, ">>");
7513 else
7514 break;
9306ca4a 7515
64e74474 7516 intel_match_token (cur_token.code);
64a0c779 7517
a724f0f4
JB		 7518 if (nregs < 0)
7519 nregs = ~nregs;
64a0c779 7520 }
a724f0f4
JB		 7521 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7522 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
7523 return 1;
64a0c779
DN		 7524}
7525
a724f0f4
JB		 7526/* e09 OFFSET e09
7527 | SHORT e09
7528 | + e09
7529 | - e09
7530 | ~ e09
7531 | NOT e09
9306ca4a
JB		 7532 | e10 e09'
7533
64a0c779 7534 e09' PTR e10 e09'
b77a7acd 7535 | : e10 e09'
64a0c779
DN		 7536 | Empty */
7537static int
e3bb37b5 7538intel_e09 (void)
64a0c779 7539{
a724f0f4
JB		 7540 int nregs = ~NUM_ADDRESS_REGS;
7541 int in_offset = 0;
7542
7543 for (;;)
64a0c779 7544 {
a724f0f4
JB		 7545 /* Don't consume constants here. */
7546 if (cur_token.code == '+' || cur_token.code == '-')
7547 {
7548 /* Need to look one token ahead - if the next token
7549 is a constant, the current token is its sign. */
7550 int next_code;
7551
7552 intel_match_token (cur_token.code);
7553 next_code = cur_token.code;
7554 intel_putback_token ();
7555 if (next_code == T_CONST)
7556 break;
7557 }
7558
7559 /* e09 OFFSET e09 */
7560 if (cur_token.code == T_OFFSET)
7561 {
7562 if (!in_offset++)
7563 ++intel_parser.in_offset;
7564 }
7565
7566 /* e09 SHORT e09 */
7567 else if (cur_token.code == T_SHORT)
7568 intel_parser.op_modifier |= 1 << T_SHORT;
7569
7570 /* e09 + e09 */
7571 else if (cur_token.code == '+')
7572 strcat (intel_parser.disp, "+");
7573
7574 /* e09 - e09
7575 | ~ e09
7576 | NOT e09 */
7577 else if (cur_token.code == '-' || cur_token.code == '~')
7578 {
7579 char str[2];
64a0c779 7580
a724f0f4
JB		 7581 if (nregs < 0)
7582 nregs = ~nregs;
7583 str[0] = cur_token.code;
7584 str[1] = 0;
7585 strcat (intel_parser.disp, str);
7586 }
7587
7588 /* e09 e10 e09' */
7589 else
7590 break;
7591
7592 intel_match_token (cur_token.code);
64a0c779
DN		 7593 }
7594
a724f0f4 7595 for (;;)
9306ca4a 7596 {
a724f0f4
JB		 7597 if (!intel_e10 ())
7598 return 0;
9306ca4a 7599
a724f0f4
JB		 7600 /* e09' PTR e10 e09' */
7601 if (cur_token.code == T_PTR)
7602 {
7603 char suffix;
9306ca4a 7604
a724f0f4
JB		 7605 if (prev_token.code == T_BYTE)
7606 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 7607
a724f0f4
JB		 7608 else if (prev_token.code == T_WORD)
7609 {
7610 if (current_templates->start->name[0] == 'l'
7611 && current_templates->start->name[2] == 's'
7612 && current_templates->start->name[3] == 0)
7613 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7614 else if (intel_parser.got_a_float == 2) /* "fi..." */
7615 suffix = SHORT_MNEM_SUFFIX;
7616 else
7617 suffix = WORD_MNEM_SUFFIX;
7618 }
64a0c779 7619
a724f0f4
JB		 7620 else if (prev_token.code == T_DWORD)
7621 {
7622 if (current_templates->start->name[0] == 'l'
7623 && current_templates->start->name[2] == 's'
7624 && current_templates->start->name[3] == 0)
7625 suffix = WORD_MNEM_SUFFIX;
7626 else if (flag_code == CODE_16BIT
40fb9820
L		 7627 && (current_templates->start->opcode_modifier.jump
7628 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 7629 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7630 else if (intel_parser.got_a_float == 1) /* "f..." */
7631 suffix = SHORT_MNEM_SUFFIX;
7632 else
7633 suffix = LONG_MNEM_SUFFIX;
7634 }
9306ca4a 7635
a724f0f4
JB		 7636 else if (prev_token.code == T_FWORD)
7637 {
7638 if (current_templates->start->name[0] == 'l'
7639 && current_templates->start->name[2] == 's'
7640 && current_templates->start->name[3] == 0)
7641 suffix = LONG_MNEM_SUFFIX;
7642 else if (!intel_parser.got_a_float)
7643 {
7644 if (flag_code == CODE_16BIT)
7645 add_prefix (DATA_PREFIX_OPCODE);
7646 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7647 }
7648 else
7649 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7650 }
64a0c779 7651
a724f0f4
JB		 7652 else if (prev_token.code == T_QWORD)
7653 {
7654 if (intel_parser.got_a_float == 1) /* "f..." */
7655 suffix = LONG_MNEM_SUFFIX;
7656 else
7657 suffix = QWORD_MNEM_SUFFIX;
7658 }
64a0c779 7659
a724f0f4
JB		 7660 else if (prev_token.code == T_TBYTE)
7661 {
7662 if (intel_parser.got_a_float == 1)
7663 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7664 else
7665 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7666 }
9306ca4a 7667
a724f0f4 7668 else if (prev_token.code == T_XMMWORD)
9306ca4a 7669 {
a724f0f4
JB		 7670 /* XXX ignored for now, but accepted since gcc uses it */
7671 suffix = 0;
9306ca4a 7672 }
64a0c779 7673
f16b83df 7674 else
a724f0f4
JB		 7675 {
7676 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
7677 return 0;
7678 }
7679
435acd52
JB		 7680 /* Operands for jump/call using 'ptr' notation denote absolute
7681 addresses. */
40fb9820
L		 7682 if (current_templates->start->opcode_modifier.jump
7683 || current_templates->start->opcode_modifier.jumpdword)
7684 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 7685
a724f0f4
JB		 7686 if (current_templates->start->base_opcode == 0x8d /* lea */)
7687 ;
7688 else if (!i.suffix)
7689 i.suffix = suffix;
7690 else if (i.suffix != suffix)
7691 {
7692 as_bad (_("Conflicting operand modifiers"));
7693 return 0;
7694 }
64a0c779 7695
9306ca4a
JB		 7696 }
7697
a724f0f4
JB		 7698 /* e09' : e10 e09' */
7699 else if (cur_token.code == ':')
9306ca4a 7700 {
a724f0f4
JB		 7701 if (prev_token.code != T_REG)
7702 {
7703 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7704 segment/group identifier (which we don't have), using comma
7705 as the operand separator there is even less consistent, since
7706 there all branches only have a single operand. */
7707 if (this_operand != 0
7708 || intel_parser.in_offset
7709 || intel_parser.in_bracket
40fb9820
L		 7710 || (!current_templates->start->opcode_modifier.jump
7711 && !current_templates->start->opcode_modifier.jumpdword
7712 && !current_templates->start->opcode_modifier.jumpintersegment
7713 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 7714 return intel_match_token (T_NIL);
7715 /* Remember the start of the 2nd operand and terminate 1st
7716 operand here.
7717 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7718 another expression), but it gets at least the simplest case
7719 (a plain number or symbol on the left side) right. */
7720 intel_parser.next_operand = intel_parser.op_string;
7721 *--intel_parser.op_string = '\0';
7722 return intel_match_token (':');
7723 }
9306ca4a 7724 }
64a0c779 7725
a724f0f4 7726 /* e09' Empty */
64a0c779 7727 else
a724f0f4 7728 break;
64a0c779 7729
a724f0f4
JB		 7730 intel_match_token (cur_token.code);
7731
7732 }
7733
7734 if (in_offset)
7735 {
7736 --intel_parser.in_offset;
7737 if (nregs < 0)
7738 nregs = ~nregs;
7739 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 7740 {
a724f0f4 7741 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 7742 return 0;
7743 }
a724f0f4
JB		 7744 intel_parser.op_modifier |= 1 << T_OFFSET;
7745 }
9306ca4a 7746
a724f0f4
JB		 7747 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7748 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7749 return 1;
7750}
64a0c779 7751
a724f0f4 7752static int
e3bb37b5 7753intel_bracket_expr (void)
a724f0f4
JB		 7754{
7755 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7756 const char *start = intel_parser.op_string;
7757 int len;
7758
7759 if (i.op[this_operand].regs)
7760 return intel_match_token (T_NIL);
7761
7762 intel_match_token ('[');
7763
7764 /* Mark as a memory operand only if it's not already known to be an
7765 offset expression. If it's an offset expression, we need to keep
7766 the brace in. */
7767 if (!intel_parser.in_offset)
7768 {
7769 ++intel_parser.in_bracket;
435acd52
JB		 7770
7771 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 7772 if (current_templates->start->opcode_modifier.jump
7773 || current_templates->start->opcode_modifier.jumpdword)
7774 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 7775
a724f0f4
JB		 7776 /* Unfortunately gas always diverged from MASM in a respect that can't
7777 be easily fixed without risking to break code sequences likely to be
7778 encountered (the testsuite even check for this): MASM doesn't consider
7779 an expression inside brackets unconditionally as a memory reference.
7780 When that is e.g. a constant, an offset expression, or the sum of the
7781 two, this is still taken as a constant load. gas, however, always
7782 treated these as memory references. As a compromise, we'll try to make
7783 offset expressions inside brackets work the MASM way (since that's
7784 less likely to be found in real world code), but make constants alone
7785 continue to work the traditional gas way. In either case, issue a
7786 warning. */
7787 intel_parser.op_modifier &= ~was_offset;
64a0c779 7788 }
a724f0f4 7789 else
64e74474 7790 strcat (intel_parser.disp, "[");
a724f0f4
JB		 7791
7792 /* Add a '+' to the displacement string if necessary. */
7793 if (*intel_parser.disp != '\0'
7794 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7795 strcat (intel_parser.disp, "+");
64a0c779 7796
a724f0f4
JB		 7797 if (intel_expr ()
7798 && (len = intel_parser.op_string - start - 1,
7799 intel_match_token (']')))
64a0c779 7800 {
a724f0f4
JB		 7801 /* Preserve brackets when the operand is an offset expression. */
7802 if (intel_parser.in_offset)
7803 strcat (intel_parser.disp, "]");
7804 else
7805 {
7806 --intel_parser.in_bracket;
7807 if (i.base_reg || i.index_reg)
7808 intel_parser.is_mem = 1;
7809 if (!intel_parser.is_mem)
7810 {
7811 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7812 /* Defer the warning until all of the operand was parsed. */
7813 intel_parser.is_mem = -1;
7814 else if (!quiet_warnings)
4eed87de
AM		 7815 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
7816 len, start, len, start);
a724f0f4
JB		 7817 }
7818 }
7819 intel_parser.op_modifier |= was_offset;
64a0c779 7820
a724f0f4 7821 return 1;
64a0c779 7822 }
a724f0f4 7823 return 0;
64a0c779
DN		 7824}
7825
7826/* e10 e11 e10'
7827
7828 e10' [ expr ] e10'
b77a7acd 7829 | Empty */
64a0c779 7830static int
e3bb37b5 7831intel_e10 (void)
64a0c779 7832{
a724f0f4
JB		 7833 if (!intel_e11 ())
7834 return 0;
64a0c779 7835
a724f0f4 7836 while (cur_token.code == '[')
64a0c779 7837 {
a724f0f4 7838 if (!intel_bracket_expr ())
21d6c4af 7839 return 0;
64a0c779
DN		 7840 }
7841
a724f0f4 7842 return 1;
64a0c779
DN		 7843}
7844
64a0c779 7845/* e11 ( expr )
b77a7acd 7846 | [ expr ]
64a0c779
DN		 7847 | BYTE
7848 | WORD
7849 | DWORD
9306ca4a 7850 | FWORD
64a0c779 7851 | QWORD
9306ca4a
JB		 7852 | TBYTE
7853 | OWORD
7854 | XMMWORD
4a1805b1 7855 | $
64a0c779
DN		 7856 | .
7857 | register
7858 | id
7859 | constant */
7860static int
e3bb37b5 7861intel_e11 (void)
64a0c779 7862{
a724f0f4 7863 switch (cur_token.code)
64a0c779 7864 {
a724f0f4
JB		 7865 /* e11 ( expr ) */
7866 case '(':
64a0c779
DN		 7867 intel_match_token ('(');
7868 strcat (intel_parser.disp, "(");
7869
7870 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7871 {
7872 strcat (intel_parser.disp, ")");
7873 return 1;
7874 }
a724f0f4 7875 return 0;
4a1805b1 7876
a724f0f4
JB		 7877 /* e11 [ expr ] */
7878 case '[':
a724f0f4 7879 return intel_bracket_expr ();
64a0c779 7880
a724f0f4
JB		 7881 /* e11 $
7882 | . */
7883 case '.':
64a0c779
DN		 7884 strcat (intel_parser.disp, cur_token.str);
7885 intel_match_token (cur_token.code);
21d6c4af
DN		 7886
7887 /* Mark as a memory operand only if it's not already known to be an
7888 offset expression. */
a724f0f4 7889 if (!intel_parser.in_offset)
21d6c4af 7890 intel_parser.is_mem = 1;
64a0c779
DN		 7891
7892 return 1;
64a0c779 7893
a724f0f4
JB		 7894 /* e11 register */
7895 case T_REG:
7896 {
7897 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7898
a724f0f4 7899 intel_match_token (T_REG);
64a0c779 7900
a724f0f4
JB		 7901 /* Check for segment change. */
7902 if (cur_token.code == ':')
7903 {
40fb9820
L		 7904 if (!reg->reg_type.bitfield.sreg2
7905 && !reg->reg_type.bitfield.sreg3)
a724f0f4 7906 {
4eed87de
AM		 7907 as_bad (_("`%s' is not a valid segment register"),
7908 reg->reg_name);
a724f0f4
JB		 7909 return 0;
7910 }
7911 else if (i.seg[i.mem_operands])
7912 as_warn (_("Extra segment override ignored"));
7913 else
7914 {
7915 if (!intel_parser.in_offset)
7916 intel_parser.is_mem = 1;
7917 switch (reg->reg_num)
7918 {
7919 case 0:
7920 i.seg[i.mem_operands] = &es;
7921 break;
7922 case 1:
7923 i.seg[i.mem_operands] = &cs;
7924 break;
7925 case 2:
7926 i.seg[i.mem_operands] = &ss;
7927 break;
7928 case 3:
7929 i.seg[i.mem_operands] = &ds;
7930 break;
7931 case 4:
7932 i.seg[i.mem_operands] = &fs;
7933 break;
7934 case 5:
7935 i.seg[i.mem_operands] = &gs;
7936 break;
7937 }
7938 }
7939 }
64a0c779 7940
a724f0f4
JB		 7941 /* Not a segment register. Check for register scaling. */
7942 else if (cur_token.code == '*')
7943 {
7944 if (!intel_parser.in_bracket)
7945 {
7946 as_bad (_("Register scaling only allowed in memory operands"));
7947 return 0;
7948 }
64a0c779 7949
40fb9820 7950 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 7951 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7952 else if (i.index_reg)
7953 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 7954
a724f0f4
JB		 7955 /* What follows must be a valid scale. */
7956 intel_match_token ('*');
7957 i.index_reg = reg;
40fb9820 7958 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 7959
a724f0f4
JB		 7960 /* Set the scale after setting the register (otherwise,
7961 i386_scale will complain) */
7962 if (cur_token.code == '+' || cur_token.code == '-')
7963 {
7964 char *str, sign = cur_token.code;
7965 intel_match_token (cur_token.code);
7966 if (cur_token.code != T_CONST)
7967 {
7968 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7969 cur_token.str);
7970 return 0;
7971 }
7972 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7973 strcpy (str + 1, cur_token.str);
7974 *str = sign;
7975 if (!i386_scale (str))
7976 return 0;
7977 free (str);
7978 }
7979 else if (!i386_scale (cur_token.str))
64a0c779 7980 return 0;
a724f0f4
JB		 7981 intel_match_token (cur_token.code);
7982 }
64a0c779 7983
a724f0f4
JB		 7984 /* No scaling. If this is a memory operand, the register is either a
7985 base register (first occurrence) or an index register (second
7986 occurrence). */
7b0441f6 7987 else if (intel_parser.in_bracket)
a724f0f4 7988 {
64a0c779 7989
a724f0f4
JB		 7990 if (!i.base_reg)
7991 i.base_reg = reg;
7992 else if (!i.index_reg)
7993 i.index_reg = reg;
7994 else
7995 {
7996 as_bad (_("Too many register references in memory operand"));
7997 return 0;
7998 }
64a0c779 7999
40fb9820 8000 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 8001 }
4a1805b1 8002
4d1bb795
JB		 8003 /* It's neither base nor index. */
8004 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 8005 {
40fb9820
L		 8006 i386_operand_type temp = reg->reg_type;
8007 temp.bitfield.baseindex = 0;
8008 i.types[this_operand] = operand_type_biop (i.types[this_operand],
8009 temp, or);
a724f0f4
JB		 8010 i.op[this_operand].regs = reg;
8011 i.reg_operands++;
8012 }
8013 else
8014 {
8015 as_bad (_("Invalid use of register"));
8016 return 0;
8017 }
64a0c779 8018
a724f0f4
JB		 8019 /* Since registers are not part of the displacement string (except
8020 when we're parsing offset operands), we may need to remove any
8021 preceding '+' from the displacement string. */
8022 if (*intel_parser.disp != '\0'
8023 && !intel_parser.in_offset)
8024 {
8025 char *s = intel_parser.disp;
8026 s += strlen (s) - 1;
8027 if (*s == '+')
8028 *s = '\0';
8029 }
4a1805b1 8030
a724f0f4
JB		 8031 return 1;
8032 }
8033
8034 /* e11 BYTE
8035 | WORD
8036 | DWORD
8037 | FWORD
8038 | QWORD
8039 | TBYTE
8040 | OWORD
8041 | XMMWORD */
8042 case T_BYTE:
8043 case T_WORD:
8044 case T_DWORD:
8045 case T_FWORD:
8046 case T_QWORD:
8047 case T_TBYTE:
8048 case T_XMMWORD:
8049 intel_match_token (cur_token.code);
64a0c779 8050
a724f0f4
JB		 8051 if (cur_token.code == T_PTR)
8052 return 1;
8053
8054 /* It must have been an identifier. */
8055 intel_putback_token ();
8056 cur_token.code = T_ID;
8057 /* FALLTHRU */
8058
8059 /* e11 id
8060 | constant */
8061 case T_ID:
8062 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 8063 {
8064 symbolS *symbolP;
8065
a724f0f4
JB		 8066 /* The identifier represents a memory reference only if it's not
8067 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 8068 symbolP = symbol_find(cur_token.str);
8069 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8070 intel_parser.is_mem = 1;
8071 }
a724f0f4 8072 /* FALLTHRU */
64a0c779 8073
a724f0f4
JB		 8074 case T_CONST:
8075 case '-':
8076 case '+':
8077 {
8078 char *save_str, sign = 0;
64a0c779 8079
a724f0f4
JB		 8080 /* Allow constants that start with `+' or `-'. */
8081 if (cur_token.code == '-' || cur_token.code == '+')
8082 {
8083 sign = cur_token.code;
8084 intel_match_token (cur_token.code);
8085 if (cur_token.code != T_CONST)
8086 {
8087 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8088 cur_token.str);
8089 return 0;
8090 }
8091 }
64a0c779 8092
a724f0f4
JB		 8093 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8094 strcpy (save_str + !!sign, cur_token.str);
8095 if (sign)
8096 *save_str = sign;
64a0c779 8097
a724f0f4
JB		 8098 /* Get the next token to check for register scaling. */
8099 intel_match_token (cur_token.code);
64a0c779 8100
4eed87de
AM		 8101 /* Check if this constant is a scaling factor for an
8102 index register. */
a724f0f4
JB		 8103 if (cur_token.code == '*')
8104 {
8105 if (intel_match_token ('*') && cur_token.code == T_REG)
8106 {
8107 const reg_entry *reg = cur_token.reg;
8108
8109 if (!intel_parser.in_bracket)
8110 {
4eed87de
AM		 8111 as_bad (_("Register scaling only allowed "
8112 "in memory operands"));
a724f0f4
JB		 8113 return 0;
8114 }
8115
4eed87de
AM		 8116 /* Disallow things like [1*si].
8117 sp and esp are invalid as index. */
40fb9820 8118 if (reg->reg_type.bitfield.reg16)
4eed87de 8119 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 8120 else if (i.index_reg)
4eed87de 8121 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 8122
8123 /* The constant is followed by `* reg', so it must be
8124 a valid scale. */
8125 i.index_reg = reg;
40fb9820 8126 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 8127
8128 /* Set the scale after setting the register (otherwise,
8129 i386_scale will complain) */
8130 if (!i386_scale (save_str))
64a0c779 8131 return 0;
a724f0f4
JB		 8132 intel_match_token (T_REG);
8133
8134 /* Since registers are not part of the displacement
8135 string, we may need to remove any preceding '+' from
8136 the displacement string. */
8137 if (*intel_parser.disp != '\0')
8138 {
8139 char *s = intel_parser.disp;
8140 s += strlen (s) - 1;
8141 if (*s == '+')
8142 *s = '\0';
8143 }
8144
8145 free (save_str);
8146
8147 return 1;
8148 }
64a0c779 8149
a724f0f4
JB		 8150 /* The constant was not used for register scaling. Since we have
8151 already consumed the token following `*' we now need to put it
8152 back in the stream. */
64a0c779 8153 intel_putback_token ();
a724f0f4 8154 }
64a0c779 8155
a724f0f4
JB		 8156 /* Add the constant to the displacement string. */
8157 strcat (intel_parser.disp, save_str);
8158 free (save_str);
64a0c779 8159
a724f0f4
JB		 8160 return 1;
8161 }
64a0c779
DN		 8162 }
8163
64a0c779
DN		 8164 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8165 return 0;
8166}
8167
64a0c779
DN		 8168/* Match the given token against cur_token. If they match, read the next
8169 token from the operand string. */
8170static int
e3bb37b5 8171intel_match_token (int code)
64a0c779
DN		 8172{
8173 if (cur_token.code == code)
8174 {
8175 intel_get_token ();
8176 return 1;
8177 }
8178 else
8179 {
0477af35 8180 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 8181 return 0;
8182 }
8183}
8184
64a0c779
DN		 8185/* Read a new token from intel_parser.op_string and store it in cur_token. */
8186static void
e3bb37b5 8187intel_get_token (void)
64a0c779
DN		 8188{
8189 char *end_op;
8190 const reg_entry *reg;
8191 struct intel_token new_token;
8192
8193 new_token.code = T_NIL;
8194 new_token.reg = NULL;
8195 new_token.str = NULL;
8196
4a1805b1 8197 /* Free the memory allocated to the previous token and move
64a0c779
DN		 8198 cur_token to prev_token. */
8199 if (prev_token.str)
8200 free (prev_token.str);
8201
8202 prev_token = cur_token;
8203
8204 /* Skip whitespace. */
8205 while (is_space_char (*intel_parser.op_string))
8206 intel_parser.op_string++;
8207
8208 /* Return an empty token if we find nothing else on the line. */
8209 if (*intel_parser.op_string == '\0')
8210 {
8211 cur_token = new_token;
8212 return;
8213 }
8214
8215 /* The new token cannot be larger than the remainder of the operand
8216 string. */
a724f0f4 8217 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 8218 new_token.str[0] = '\0';
8219
8220 if (strchr ("0123456789", *intel_parser.op_string))
8221 {
8222 char *p = new_token.str;
8223 char *q = intel_parser.op_string;
8224 new_token.code = T_CONST;
8225
8226 /* Allow any kind of identifier char to encompass floating point and
8227 hexadecimal numbers. */
8228 while (is_identifier_char (*q))
8229 *p++ = *q++;
8230 *p = '\0';
8231
8232 /* Recognize special symbol names [0-9][bf]. */
8233 if (strlen (intel_parser.op_string) == 2
4a1805b1 8234 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 8235 || intel_parser.op_string[1] == 'f'))
8236 new_token.code = T_ID;
8237 }
8238
4d1bb795 8239 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 8240 {
4d1bb795
JB		 8241 size_t len = end_op - intel_parser.op_string;
8242
64a0c779
DN		 8243 new_token.code = T_REG;
8244 new_token.reg = reg;
8245
4d1bb795
JB		 8246 memcpy (new_token.str, intel_parser.op_string, len);
8247 new_token.str[len] = '\0';
64a0c779
DN		 8248 }
8249
8250 else if (is_identifier_char (*intel_parser.op_string))
8251 {
8252 char *p = new_token.str;
8253 char *q = intel_parser.op_string;
8254
8255 /* A '.' or '$' followed by an identifier char is an identifier.
8256 Otherwise, it's operator '.' followed by an expression. */
8257 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
8258 {
9306ca4a
JB		 8259 new_token.code = '.';
8260 new_token.str[0] = '.';
64a0c779
DN		 8261 new_token.str[1] = '\0';
8262 }
8263 else
8264 {
8265 while (is_identifier_char (*q) || *q == '@')
8266 *p++ = *q++;
8267 *p = '\0';
8268
9306ca4a
JB		 8269 if (strcasecmp (new_token.str, "NOT") == 0)
8270 new_token.code = '~';
8271
8272 else if (strcasecmp (new_token.str, "MOD") == 0)
8273 new_token.code = '%';
8274
8275 else if (strcasecmp (new_token.str, "AND") == 0)
8276 new_token.code = '&';
8277
8278 else if (strcasecmp (new_token.str, "OR") == 0)
8279 new_token.code = '|';
8280
8281 else if (strcasecmp (new_token.str, "XOR") == 0)
8282 new_token.code = '^';
8283
8284 else if (strcasecmp (new_token.str, "SHL") == 0)
8285 new_token.code = T_SHL;
8286
8287 else if (strcasecmp (new_token.str, "SHR") == 0)
8288 new_token.code = T_SHR;
8289
8290 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 8291 new_token.code = T_BYTE;
8292
8293 else if (strcasecmp (new_token.str, "WORD") == 0)
8294 new_token.code = T_WORD;
8295
8296 else if (strcasecmp (new_token.str, "DWORD") == 0)
8297 new_token.code = T_DWORD;
8298
9306ca4a
JB		 8299 else if (strcasecmp (new_token.str, "FWORD") == 0)
8300 new_token.code = T_FWORD;
8301
64a0c779
DN		 8302 else if (strcasecmp (new_token.str, "QWORD") == 0)
8303 new_token.code = T_QWORD;
8304
9306ca4a
JB		 8305 else if (strcasecmp (new_token.str, "TBYTE") == 0
8306 /* XXX remove (gcc still uses it) */
8307 || strcasecmp (new_token.str, "XWORD") == 0)
8308 new_token.code = T_TBYTE;
8309
8310 else if (strcasecmp (new_token.str, "XMMWORD") == 0
8311 || strcasecmp (new_token.str, "OWORD") == 0)
8312 new_token.code = T_XMMWORD;
64a0c779
DN		 8313
8314 else if (strcasecmp (new_token.str, "PTR") == 0)
8315 new_token.code = T_PTR;
8316
8317 else if (strcasecmp (new_token.str, "SHORT") == 0)
8318 new_token.code = T_SHORT;
8319
8320 else if (strcasecmp (new_token.str, "OFFSET") == 0)
8321 {
8322 new_token.code = T_OFFSET;
8323
8324 /* ??? This is not mentioned in the MASM grammar but gcc
8325 makes use of it with -mintel-syntax. OFFSET may be
8326 followed by FLAT: */
8327 if (strncasecmp (q, " FLAT:", 6) == 0)
8328 strcat (new_token.str, " FLAT:");
8329 }
8330
8331 /* ??? This is not mentioned in the MASM grammar. */
8332 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 8333 {
8334 new_token.code = T_OFFSET;
8335 if (*q == ':')
8336 strcat (new_token.str, ":");
8337 else
8338 as_bad (_("`:' expected"));
8339 }
64a0c779
DN		 8340
8341 else
8342 new_token.code = T_ID;
8343 }
8344 }
8345
9306ca4a
JB		 8346 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
8347 {
8348 new_token.code = *intel_parser.op_string;
8349 new_token.str[0] = *intel_parser.op_string;
8350 new_token.str[1] = '\0';
8351 }
8352
8353 else if (strchr ("<>", *intel_parser.op_string)
8354 && *intel_parser.op_string == *(intel_parser.op_string + 1))
8355 {
8356 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
8357 new_token.str[0] = *intel_parser.op_string;
8358 new_token.str[1] = *intel_parser.op_string;
8359 new_token.str[2] = '\0';
8360 }
8361
64a0c779 8362 else
0477af35 8363 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 8364
8365 intel_parser.op_string += strlen (new_token.str);
8366 cur_token = new_token;
8367}
8368
64a0c779
DN		 8369/* Put cur_token back into the token stream and make cur_token point to
8370 prev_token. */
8371static void
e3bb37b5 8372intel_putback_token (void)
64a0c779 8373{
a724f0f4
JB		 8374 if (cur_token.code != T_NIL)
8375 {
8376 intel_parser.op_string -= strlen (cur_token.str);
8377 free (cur_token.str);
8378 }
64a0c779 8379 cur_token = prev_token;
4a1805b1 8380
64a0c779
DN		 8381 /* Forget prev_token. */
8382 prev_token.code = T_NIL;
8383 prev_token.reg = NULL;
8384 prev_token.str = NULL;
8385}
54cfded0 8386
a4447b93 8387int
1df69f4f 8388tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 8389{
8390 unsigned int regnum;
8391 unsigned int regnames_count;
089dfecd 8392 static const char *const regnames_32[] =
54cfded0 8393 {
a4447b93
RH		 8394 "eax", "ecx", "edx", "ebx",
8395 "esp", "ebp", "esi", "edi",
089dfecd
JB		 8396 "eip", "eflags", NULL,
8397 "st0", "st1", "st2", "st3",
8398 "st4", "st5", "st6", "st7",
8399 NULL, NULL,
8400 "xmm0", "xmm1", "xmm2", "xmm3",
8401 "xmm4", "xmm5", "xmm6", "xmm7",
8402 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8403 "mm4", "mm5", "mm6", "mm7",
8404 "fcw", "fsw", "mxcsr",
8405 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8406 "tr", "ldtr"
54cfded0 8407 };
089dfecd 8408 static const char *const regnames_64[] =
54cfded0 8409 {
089dfecd
JB		 8410 "rax", "rdx", "rcx", "rbx",
8411 "rsi", "rdi", "rbp", "rsp",
8412 "r8", "r9", "r10", "r11",
54cfded0 8413 "r12", "r13", "r14", "r15",
089dfecd
JB		 8414 "rip",
8415 "xmm0", "xmm1", "xmm2", "xmm3",
8416 "xmm4", "xmm5", "xmm6", "xmm7",
8417 "xmm8", "xmm9", "xmm10", "xmm11",
8418 "xmm12", "xmm13", "xmm14", "xmm15",
8419 "st0", "st1", "st2", "st3",
8420 "st4", "st5", "st6", "st7",
8421 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8422 "mm4", "mm5", "mm6", "mm7",
8423 "rflags",
8424 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8425 "fs.base", "gs.base", NULL, NULL,
8426 "tr", "ldtr",
8427 "mxcsr", "fcw", "fsw"
54cfded0 8428 };
089dfecd 8429 const char *const *regnames;
54cfded0
AM		 8430
8431 if (flag_code == CODE_64BIT)
8432 {
8433 regnames = regnames_64;
0cea6190 8434 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 8435 }
8436 else
8437 {
8438 regnames = regnames_32;
0cea6190 8439 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 8440 }
8441
8442 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 8443 if (regnames[regnum] != NULL
8444 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 8445 return regnum;
8446
54cfded0
AM		 8447 return -1;
8448}
8449
8450void
8451tc_x86_frame_initial_instructions (void)
8452{
a4447b93
RH		 8453 static unsigned int sp_regno;
8454
8455 if (!sp_regno)
8456 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
8457 ? "rsp" : "esp");
8458
8459 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
8460 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8461}
d2b2c203
DJ		 8462
8463int
8464i386_elf_section_type (const char *str, size_t len)
8465{
8466 if (flag_code == CODE_64BIT
8467 && len == sizeof ("unwind") - 1
8468 && strncmp (str, "unwind", 6) == 0)
8469 return SHT_X86_64_UNWIND;
8470
8471 return -1;
8472}
bb41ade5
AM		 8473
8474#ifdef TE_PE
8475void
8476tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8477{
8478 expressionS expr;
8479
8480 expr.X_op = O_secrel;
8481 expr.X_add_symbol = symbol;
8482 expr.X_add_number = 0;
8483 emit_expr (&expr, size);
8484}
8485#endif
3b22753a
L		 8486
8487#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8488/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8489
8490int
8491x86_64_section_letter (int letter, char **ptr_msg)
8492{
8493 if (flag_code == CODE_64BIT)
8494 {
8495 if (letter == 'l')
8496 return SHF_X86_64_LARGE;
8497
8498 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8499 }
3b22753a 8500 else
64e74474 8501 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8502 return -1;
8503}
8504
8505int
8506x86_64_section_word (char *str, size_t len)
8507{
8620418b 8508 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8509 return SHF_X86_64_LARGE;
8510
8511 return -1;
8512}
8513
8514static void
8515handle_large_common (int small ATTRIBUTE_UNUSED)
8516{
8517 if (flag_code != CODE_64BIT)
8518 {
8519 s_comm_internal (0, elf_common_parse);
8520 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8521 }
8522 else
8523 {
8524 static segT lbss_section;
8525 asection *saved_com_section_ptr = elf_com_section_ptr;
8526 asection *saved_bss_section = bss_section;
8527
8528 if (lbss_section == NULL)
8529 {
8530 flagword applicable;
8531 segT seg = now_seg;
8532 subsegT subseg = now_subseg;
8533
8534 /* The .lbss section is for local .largecomm symbols. */
8535 lbss_section = subseg_new (".lbss", 0);
8536 applicable = bfd_applicable_section_flags (stdoutput);
8537 bfd_set_section_flags (stdoutput, lbss_section,
8538 applicable & SEC_ALLOC);
8539 seg_info (lbss_section)->bss = 1;
8540
8541 subseg_set (seg, subseg);
8542 }
8543
8544 elf_com_section_ptr = &_bfd_elf_large_com_section;
8545 bss_section = lbss_section;
8546
8547 s_comm_internal (0, elf_common_parse);
8548
8549 elf_com_section_ptr = saved_com_section_ptr;
8550 bss_section = saved_bss_section;
8551 }
8552}
8553#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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