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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5dd15031 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 LOCKREP_PREFIX. */
63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
67#define LOCKREP_PREFIX 4
68#define REX_PREFIX 5 /* must come last. */
69#define MAX_PREFIXES 6 /* max prefixes per opcode */
70
71/* we define the syntax here (modulo base,index,scale syntax) */
72#define REGISTER_PREFIX '%'
73#define IMMEDIATE_PREFIX '$'
74#define ABSOLUTE_PREFIX '*'
75
76/* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78#define WORD_MNEM_SUFFIX 'w'
79#define BYTE_MNEM_SUFFIX 'b'
80#define SHORT_MNEM_SUFFIX 's'
81#define LONG_MNEM_SUFFIX 'l'
82#define QWORD_MNEM_SUFFIX 'q'
83#define XMMWORD_MNEM_SUFFIX 'x'
84/* Intel Syntax. Use a non-ascii letter since since it never appears
85 in instructions. */
86#define LONG_DOUBLE_MNEM_SUFFIX '\1'
87
88#define END_OF_INSN '\0'
89
90/*
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
95 END.
96 */
97typedef struct
98{
99 const template *start;
100 const template *end;
101}
102templates;
103
104/* 386 operand encoding bytes: see 386 book for details of this. */
105typedef struct
106{
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
110}
111modrm_byte;
112
113/* x86-64 extension prefix. */
114typedef int rex_byte;
115
116/* The SSE5 instructions have a two bit instruction modifier (OC) that
117 is stored in two separate bytes in the instruction. Pick apart OC
118 into the 2 separate bits for instruction. */
119#define DREX_OC0(x) (((x) & 1) != 0)
120#define DREX_OC1(x) (((x) & 2) != 0)
121
122#define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
123#define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
124
125/* OC mappings */
126#define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
127#define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
128#define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
129#define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
130
131#define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
132#define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
133
134/* Information needed to create the DREX byte in SSE5 instructions. */
135typedef struct
136{
137 unsigned int reg; /* register */
138 unsigned int rex; /* REX flags */
139 unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
140 unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
141} drex_byte;
142
143/* 386 opcode byte to code indirect addressing. */
144typedef struct
145{
146 unsigned base;
147 unsigned index;
148 unsigned scale;
149}
150sib_byte;
151
152enum processor_type
153{
154 PROCESSOR_UNKNOWN,
155 PROCESSOR_I386,
156 PROCESSOR_I486,
157 PROCESSOR_PENTIUM,
158 PROCESSOR_PENTIUMPRO,
159 PROCESSOR_PENTIUM4,
160 PROCESSOR_NOCONA,
161 PROCESSOR_CORE,
162 PROCESSOR_CORE2,
163 PROCESSOR_K6,
164 PROCESSOR_ATHLON,
165 PROCESSOR_K8,
166 PROCESSOR_GENERIC32,
167 PROCESSOR_GENERIC64,
168 PROCESSOR_AMDFAM10
169};
170
171/* x86 arch names, types and features */
172typedef struct
173{
174 const char *name; /* arch name */
175 enum processor_type type; /* arch type */
176 i386_cpu_flags flags; /* cpu feature flags */
177}
178arch_entry;
179
e3bb37b5
L		 180static void set_code_flag (int);
181static void set_16bit_gcc_code_flag (int);
182static void set_intel_syntax (int);
1efbbeb4 183static void set_intel_mnemonic (int);
db51cc60 184static void set_allow_index_reg (int);
e3bb37b5 185static void set_cpu_arch (int);
6482c264 186#ifdef TE_PE
e3bb37b5 187static void pe_directive_secrel (int);
6482c264 188#endif
e3bb37b5
L		 189static void signed_cons (int);
190static char *output_invalid (int c);
a7619375 191static int i386_att_operand (char *);
e3bb37b5
L		 192static int i386_intel_operand (char *, int);
193static const reg_entry *parse_register (char *, char **);
194static char *parse_insn (char *, char *);
195static char *parse_operands (char *, const char *);
196static void swap_operands (void);
4d456e3d 197static void swap_2_operands (int, int);
e3bb37b5
L		 198static void optimize_imm (void);
199static void optimize_disp (void);
200static int match_template (void);
201static int check_string (void);
202static int process_suffix (void);
203static int check_byte_reg (void);
204static int check_long_reg (void);
205static int check_qword_reg (void);
206static int check_word_reg (void);
207static int finalize_imm (void);
85f10a01 208static void process_drex (void);
e3bb37b5
L		 209static int process_operands (void);
210static const seg_entry *build_modrm_byte (void);
211static void output_insn (void);
212static void output_imm (fragS *, offsetT);
213static void output_disp (fragS *, offsetT);
29b0f896 214#ifndef I386COFF
e3bb37b5 215static void s_bss (int);
252b5132 216#endif
17d4e2a2
L		 217#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
218static void handle_large_common (int small ATTRIBUTE_UNUSED);
219#endif
252b5132 220
a847613f 221static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 222
252b5132 223/* 'md_assemble ()' gathers together information and puts it into a
47926f60 224 i386_insn. */
252b5132 225
520dc8e8
AM		 226union i386_op
227 {
228 expressionS *disps;
229 expressionS *imms;
230 const reg_entry *regs;
231 };
232
252b5132
RH		 233struct _i386_insn
234 {
47926f60 235 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 236 template tm;
237
7d5e4556
L		 238 /* SUFFIX holds the instruction size suffix for byte, word, dword
239 or qword, if given. */
252b5132
RH		 240 char suffix;
241
47926f60 242 /* OPERANDS gives the number of given operands. */
252b5132
RH		 243 unsigned int operands;
244
245 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
246 of given register, displacement, memory operands and immediate
47926f60 247 operands. */
252b5132
RH		 248 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
249
250 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 251 use OP[i] for the corresponding operand. */
40fb9820 252 i386_operand_type types[MAX_OPERANDS];
252b5132 253
520dc8e8
AM		 254 /* Displacement expression, immediate expression, or register for each
255 operand. */
256 union i386_op op[MAX_OPERANDS];
252b5132 257
3e73aa7c
JH		 258 /* Flags for operands. */
259 unsigned int flags[MAX_OPERANDS];
260#define Operand_PCrel 1
261
252b5132 262 /* Relocation type for operand */
f86103b7 263 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 264
252b5132
RH		 265 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
266 the base index byte below. */
267 const reg_entry *base_reg;
268 const reg_entry *index_reg;
269 unsigned int log2_scale_factor;
270
271 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 272 explicit segment overrides are given. */
ce8a8b2f 273 const seg_entry *seg[2];
252b5132
RH		 274
275 /* PREFIX holds all the given prefix opcodes (usually null).
276 PREFIXES is the number of prefix opcodes. */
277 unsigned int prefixes;
278 unsigned char prefix[MAX_PREFIXES];
279
280 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 281 addressing modes of this insn are encoded. DREX is the byte
282 added by the SSE5 instructions. */
252b5132
RH		 283
284 modrm_byte rm;
3e73aa7c 285 rex_byte rex;
252b5132 286 sib_byte sib;
85f10a01 287 drex_byte drex;
252b5132
RH		 288 };
289
290typedef struct _i386_insn i386_insn;
291
292/* List of chars besides those in app.c:symbol_chars that can start an
293 operand. Used to prevent the scrubber eating vital white-space. */
32137342 294const char extra_symbol_chars[] = "*%-(["
252b5132 295#ifdef LEX_AT
32137342
NC		 296 "@"
297#endif
298#ifdef LEX_QM
299 "?"
252b5132 300#endif
32137342 301 ;
252b5132 302
29b0f896
AM		 303#if (defined (TE_I386AIX) \
304 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 305 && !defined (TE_GNU) \
29b0f896 306 && !defined (TE_LINUX) \
32137342 307 && !defined (TE_NETWARE) \
29b0f896
AM		 308 && !defined (TE_FreeBSD) \
309 && !defined (TE_NetBSD)))
252b5132 310/* This array holds the chars that always start a comment. If the
b3b91714
AM		 311 pre-processor is disabled, these aren't very useful. The option
312 --divide will remove '/' from this list. */
313const char *i386_comment_chars = "#/";
314#define SVR4_COMMENT_CHARS 1
252b5132 315#define PREFIX_SEPARATOR '\\'
252b5132 316
b3b91714
AM		 317#else
318const char *i386_comment_chars = "#";
319#define PREFIX_SEPARATOR '/'
320#endif
321
252b5132
RH		 322/* This array holds the chars that only start a comment at the beginning of
323 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 324 .line and .file directives will appear in the pre-processed output.
325 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 326 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 327 #NO_APP at the beginning of its output.
328 Also note that comments started like this one will always work if
252b5132 329 '/' isn't otherwise defined. */
b3b91714 330const char line_comment_chars[] = "#/";
252b5132 331
63a0b638 332const char line_separator_chars[] = ";";
252b5132 333
ce8a8b2f
AM		 334/* Chars that can be used to separate mant from exp in floating point
335 nums. */
252b5132
RH		 336const char EXP_CHARS[] = "eE";
337
ce8a8b2f
AM		 338/* Chars that mean this number is a floating point constant
339 As in 0f12.456
340 or 0d1.2345e12. */
252b5132
RH		 341const char FLT_CHARS[] = "fFdDxX";
342
ce8a8b2f 343/* Tables for lexical analysis. */
252b5132
RH		 344static char mnemonic_chars[256];
345static char register_chars[256];
346static char operand_chars[256];
347static char identifier_chars[256];
348static char digit_chars[256];
349
ce8a8b2f 350/* Lexical macros. */
252b5132
RH		 351#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
352#define is_operand_char(x) (operand_chars[(unsigned char) x])
353#define is_register_char(x) (register_chars[(unsigned char) x])
354#define is_space_char(x) ((x) == ' ')
355#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
356#define is_digit_char(x) (digit_chars[(unsigned char) x])
357
0234cb7c 358/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 359static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
360
361/* md_assemble() always leaves the strings it's passed unaltered. To
362 effect this we maintain a stack of saved characters that we've smashed
363 with '\0's (indicating end of strings for various sub-fields of the
47926f60 364 assembler instruction). */
252b5132 365static char save_stack[32];
ce8a8b2f 366static char *save_stack_p;
252b5132
RH		 367#define END_STRING_AND_SAVE(s) \
368 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
369#define RESTORE_END_STRING(s) \
370 do { *(s) = *--save_stack_p; } while (0)
371
47926f60 372/* The instruction we're assembling. */
252b5132
RH		 373static i386_insn i;
374
375/* Possible templates for current insn. */
376static const templates *current_templates;
377
31b2323c
L		 378/* Per instruction expressionS buffers: max displacements & immediates. */
379static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
380static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 381
47926f60
KH		 382/* Current operand we are working on. */
383static int this_operand;
252b5132 384
3e73aa7c
JH		 385/* We support four different modes. FLAG_CODE variable is used to distinguish
386 these. */
387
388enum flag_code {
389 CODE_32BIT,
390 CODE_16BIT,
391 CODE_64BIT };
392
393static enum flag_code flag_code;
4fa24527 394static unsigned int object_64bit;
3e73aa7c
JH		 395static int use_rela_relocations = 0;
396
397/* The names used to print error messages. */
b77a7acd 398static const char *flag_code_names[] =
3e73aa7c
JH		 399 {
400 "32",
401 "16",
402 "64"
403 };
252b5132 404
47926f60
KH		 405/* 1 for intel syntax,
406 0 if att syntax. */
407static int intel_syntax = 0;
252b5132 408
1efbbeb4
L		 409/* 1 for intel mnemonic,
410 0 if att mnemonic. */
411static int intel_mnemonic = !SYSV386_COMPAT;
412
5209009a 413/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 414static int old_gcc = OLDGCC_COMPAT;
415
a60de03c
JB		 416/* 1 if pseudo registers are permitted. */
417static int allow_pseudo_reg = 0;
418
47926f60
KH		 419/* 1 if register prefix % not required. */
420static int allow_naked_reg = 0;
252b5132 421
ba104c83 422/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 423static int allow_index_reg = 0;
424
2ca3ace5
L		 425/* Register prefix used for error message. */
426static const char *register_prefix = "%";
427
47926f60
KH		 428/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
429 leave, push, and pop instructions so that gcc has the same stack
430 frame as in 32 bit mode. */
431static char stackop_size = '\0';
eecb386c 432
12b55ccc
L		 433/* Non-zero to optimize code alignment. */
434int optimize_align_code = 1;
435
47926f60
KH		 436/* Non-zero to quieten some warnings. */
437static int quiet_warnings = 0;
a38cf1db 438
47926f60
KH		 439/* CPU name. */
440static const char *cpu_arch_name = NULL;
6305a203 441static char *cpu_sub_arch_name = NULL;
a38cf1db 442
47926f60 443/* CPU feature flags. */
40fb9820
L		 444static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
445
ccc9c027
L		 446/* If we have selected a cpu we are generating instructions for. */
447static int cpu_arch_tune_set = 0;
448
9103f4f4
L		 449/* Cpu we are generating instructions for. */
450static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
451
452/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 453static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 454
ccc9c027
L		 455/* CPU instruction set architecture used. */
456static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
457
9103f4f4 458/* CPU feature flags of instruction set architecture used. */
40fb9820 459static i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 460
fddf5b5b
AM		 461/* If set, conditional jumps are not automatically promoted to handle
462 larger than a byte offset. */
463static unsigned int no_cond_jump_promotion = 0;
464
29b0f896 465/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 466static symbolS *GOT_symbol;
29b0f896 467
a4447b93
RH		 468/* The dwarf2 return column, adjusted for 32 or 64 bit. */
469unsigned int x86_dwarf2_return_column;
470
471/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
472int x86_cie_data_alignment;
473
252b5132 474/* Interface to relax_segment.
fddf5b5b
AM		 475 There are 3 major relax states for 386 jump insns because the
476 different types of jumps add different sizes to frags when we're
477 figuring out what sort of jump to choose to reach a given label. */
252b5132 478
47926f60 479/* Types. */
93c2a809
AM		 480#define UNCOND_JUMP 0
481#define COND_JUMP 1
482#define COND_JUMP86 2
fddf5b5b 483
47926f60 484/* Sizes. */
252b5132
RH		 485#define CODE16 1
486#define SMALL 0
29b0f896 487#define SMALL16 (SMALL | CODE16)
252b5132 488#define BIG 2
29b0f896 489#define BIG16 (BIG | CODE16)
252b5132
RH		 490
491#ifndef INLINE
492#ifdef __GNUC__
493#define INLINE __inline__
494#else
495#define INLINE
496#endif
497#endif
498
fddf5b5b
AM		 499#define ENCODE_RELAX_STATE(type, size) \
500 ((relax_substateT) (((type) << 2) | (size)))
501#define TYPE_FROM_RELAX_STATE(s) \
502 ((s) >> 2)
503#define DISP_SIZE_FROM_RELAX_STATE(s) \
504 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 505
506/* This table is used by relax_frag to promote short jumps to long
507 ones where necessary. SMALL (short) jumps may be promoted to BIG
508 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
509 don't allow a short jump in a 32 bit code segment to be promoted to
510 a 16 bit offset jump because it's slower (requires data size
511 prefix), and doesn't work, unless the destination is in the bottom
512 64k of the code segment (The top 16 bits of eip are zeroed). */
513
514const relax_typeS md_relax_table[] =
515{
24eab124
AM		 516 /* The fields are:
517 1) most positive reach of this state,
518 2) most negative reach of this state,
93c2a809 519 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 520 4) which index into the table to try if we can't fit into this one. */
252b5132 521
fddf5b5b 522 /* UNCOND_JUMP states. */
93c2a809
AM		 523 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
524 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
525 /* dword jmp adds 4 bytes to frag:
526 0 extra opcode bytes, 4 displacement bytes. */
252b5132 527 {0, 0, 4, 0},
93c2a809
AM		 528 /* word jmp adds 2 byte2 to frag:
529 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 530 {0, 0, 2, 0},
531
93c2a809
AM		 532 /* COND_JUMP states. */
533 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
534 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
535 /* dword conditionals adds 5 bytes to frag:
536 1 extra opcode byte, 4 displacement bytes. */
537 {0, 0, 5, 0},
fddf5b5b 538 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 539 1 extra opcode byte, 2 displacement bytes. */
540 {0, 0, 3, 0},
541
542 /* COND_JUMP86 states. */
543 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
544 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
545 /* dword conditionals adds 5 bytes to frag:
546 1 extra opcode byte, 4 displacement bytes. */
547 {0, 0, 5, 0},
548 /* word conditionals add 4 bytes to frag:
549 1 displacement byte and a 3 byte long branch insn. */
550 {0, 0, 4, 0}
252b5132
RH		 551};
552
9103f4f4
L		 553static const arch_entry cpu_arch[] =
554{
6305a203
L		 555 { "generic32", PROCESSOR_GENERIC32,
556 CPU_GENERIC32_FLAGS },
557 { "generic64", PROCESSOR_GENERIC64,
558 CPU_GENERIC64_FLAGS },
559 { "i8086", PROCESSOR_UNKNOWN,
560 CPU_NONE_FLAGS },
561 { "i186", PROCESSOR_UNKNOWN,
562 CPU_I186_FLAGS },
563 { "i286", PROCESSOR_UNKNOWN,
564 CPU_I286_FLAGS },
565 { "i386", PROCESSOR_I386,
566 CPU_I386_FLAGS },
567 { "i486", PROCESSOR_I486,
568 CPU_I486_FLAGS },
569 { "i586", PROCESSOR_PENTIUM,
570 CPU_I586_FLAGS },
571 { "i686", PROCESSOR_PENTIUMPRO,
572 CPU_I686_FLAGS },
573 { "pentium", PROCESSOR_PENTIUM,
574 CPU_I586_FLAGS },
575 { "pentiumpro", PROCESSOR_PENTIUMPRO,
576 CPU_I686_FLAGS },
577 { "pentiumii", PROCESSOR_PENTIUMPRO,
578 CPU_P2_FLAGS },
579 { "pentiumiii",PROCESSOR_PENTIUMPRO,
580 CPU_P3_FLAGS },
581 { "pentium4", PROCESSOR_PENTIUM4,
582 CPU_P4_FLAGS },
583 { "prescott", PROCESSOR_NOCONA,
584 CPU_CORE_FLAGS },
585 { "nocona", PROCESSOR_NOCONA,
586 CPU_NOCONA_FLAGS },
587 { "yonah", PROCESSOR_CORE,
588 CPU_CORE_FLAGS },
589 { "core", PROCESSOR_CORE,
590 CPU_CORE_FLAGS },
591 { "merom", PROCESSOR_CORE2,
592 CPU_CORE2_FLAGS },
593 { "core2", PROCESSOR_CORE2,
594 CPU_CORE2_FLAGS },
595 { "k6", PROCESSOR_K6,
596 CPU_K6_FLAGS },
597 { "k6_2", PROCESSOR_K6,
598 CPU_K6_2_FLAGS },
599 { "athlon", PROCESSOR_ATHLON,
600 CPU_ATHLON_FLAGS },
601 { "sledgehammer", PROCESSOR_K8,
602 CPU_K8_FLAGS },
603 { "opteron", PROCESSOR_K8,
604 CPU_K8_FLAGS },
605 { "k8", PROCESSOR_K8,
606 CPU_K8_FLAGS },
607 { "amdfam10", PROCESSOR_AMDFAM10,
608 CPU_AMDFAM10_FLAGS },
609 { ".mmx", PROCESSOR_UNKNOWN,
610 CPU_MMX_FLAGS },
611 { ".sse", PROCESSOR_UNKNOWN,
612 CPU_SSE_FLAGS },
613 { ".sse2", PROCESSOR_UNKNOWN,
614 CPU_SSE2_FLAGS },
615 { ".sse3", PROCESSOR_UNKNOWN,
616 CPU_SSE3_FLAGS },
617 { ".ssse3", PROCESSOR_UNKNOWN,
618 CPU_SSSE3_FLAGS },
619 { ".sse4.1", PROCESSOR_UNKNOWN,
620 CPU_SSE4_1_FLAGS },
621 { ".sse4.2", PROCESSOR_UNKNOWN,
622 CPU_SSE4_2_FLAGS },
623 { ".sse4", PROCESSOR_UNKNOWN,
624 CPU_SSE4_2_FLAGS },
625 { ".vmx", PROCESSOR_UNKNOWN,
626 CPU_VMX_FLAGS },
627 { ".smx", PROCESSOR_UNKNOWN,
628 CPU_SMX_FLAGS },
f03fe4c1
L		 629 { ".xsave", PROCESSOR_UNKNOWN,
630 CPU_XSAVE_FLAGS },
6305a203
L		 631 { ".3dnow", PROCESSOR_UNKNOWN,
632 CPU_3DNOW_FLAGS },
633 { ".3dnowa", PROCESSOR_UNKNOWN,
634 CPU_3DNOWA_FLAGS },
635 { ".padlock", PROCESSOR_UNKNOWN,
636 CPU_PADLOCK_FLAGS },
637 { ".pacifica", PROCESSOR_UNKNOWN,
638 CPU_SVME_FLAGS },
639 { ".svme", PROCESSOR_UNKNOWN,
640 CPU_SVME_FLAGS },
641 { ".sse4a", PROCESSOR_UNKNOWN,
642 CPU_SSE4A_FLAGS },
643 { ".abm", PROCESSOR_UNKNOWN,
644 CPU_ABM_FLAGS },
645 { ".sse5", PROCESSOR_UNKNOWN,
646 CPU_SSE5_FLAGS },
e413e4e9
AM		 647};
648
29b0f896
AM		 649const pseudo_typeS md_pseudo_table[] =
650{
651#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
652 {"align", s_align_bytes, 0},
653#else
654 {"align", s_align_ptwo, 0},
655#endif
656 {"arch", set_cpu_arch, 0},
657#ifndef I386COFF
658 {"bss", s_bss, 0},
659#endif
660 {"ffloat", float_cons, 'f'},
661 {"dfloat", float_cons, 'd'},
662 {"tfloat", float_cons, 'x'},
663 {"value", cons, 2},
d182319b 664 {"slong", signed_cons, 4},
29b0f896
AM		 665 {"noopt", s_ignore, 0},
666 {"optim", s_ignore, 0},
667 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
668 {"code16", set_code_flag, CODE_16BIT},
669 {"code32", set_code_flag, CODE_32BIT},
670 {"code64", set_code_flag, CODE_64BIT},
671 {"intel_syntax", set_intel_syntax, 1},
672 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 673 {"intel_mnemonic", set_intel_mnemonic, 1},
674 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 675 {"allow_index_reg", set_allow_index_reg, 1},
676 {"disallow_index_reg", set_allow_index_reg, 0},
3b22753a
L		 677#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
678 {"largecomm", handle_large_common, 0},
07a53e5c 679#else
e3bb37b5 680 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 681 {"loc", dwarf2_directive_loc, 0},
682 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 683#endif
6482c264
NC		 684#ifdef TE_PE
685 {"secrel32", pe_directive_secrel, 0},
686#endif
29b0f896
AM		 687 {0, 0, 0}
688};
689
690/* For interface with expression (). */
691extern char *input_line_pointer;
692
693/* Hash table for instruction mnemonic lookup. */
694static struct hash_control *op_hash;
695
696/* Hash table for register lookup. */
697static struct hash_control *reg_hash;
698\f
252b5132 699void
e3bb37b5 700i386_align_code (fragS *fragP, int count)
252b5132 701{
ce8a8b2f
AM		 702 /* Various efficient no-op patterns for aligning code labels.
703 Note: Don't try to assemble the instructions in the comments.
704 0L and 0w are not legal. */
252b5132
RH		 705 static const char f32_1[] =
706 {0x90}; /* nop */
707 static const char f32_2[] =
ccc9c027 708 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 709 static const char f32_3[] =
710 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
711 static const char f32_4[] =
712 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
713 static const char f32_5[] =
714 {0x90, /* nop */
715 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
716 static const char f32_6[] =
717 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
718 static const char f32_7[] =
719 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
720 static const char f32_8[] =
721 {0x90, /* nop */
722 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
723 static const char f32_9[] =
724 {0x89,0xf6, /* movl %esi,%esi */
725 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
726 static const char f32_10[] =
727 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
728 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
729 static const char f32_11[] =
730 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
731 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
732 static const char f32_12[] =
733 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
734 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
735 static const char f32_13[] =
736 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
737 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
738 static const char f32_14[] =
739 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
740 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 741 static const char f16_3[] =
742 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 743 static const char f16_4[] =
744 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
745 static const char f16_5[] =
746 {0x90, /* nop */
747 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
748 static const char f16_6[] =
749 {0x89,0xf6, /* mov %si,%si */
750 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
751 static const char f16_7[] =
752 {0x8d,0x74,0x00, /* lea 0(%si),%si */
753 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
754 static const char f16_8[] =
755 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
756 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 757 static const char jump_31[] =
758 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
759 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
760 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
761 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 762 static const char *const f32_patt[] = {
763 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 764 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 765 };
766 static const char *const f16_patt[] = {
76bc74dc 767 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 768 };
ccc9c027
L		 769 /* nopl (%[re]ax) */
770 static const char alt_3[] =
771 {0x0f,0x1f,0x00};
772 /* nopl 0(%[re]ax) */
773 static const char alt_4[] =
774 {0x0f,0x1f,0x40,0x00};
775 /* nopl 0(%[re]ax,%[re]ax,1) */
776 static const char alt_5[] =
777 {0x0f,0x1f,0x44,0x00,0x00};
778 /* nopw 0(%[re]ax,%[re]ax,1) */
779 static const char alt_6[] =
780 {0x66,0x0f,0x1f,0x44,0x00,0x00};
781 /* nopl 0L(%[re]ax) */
782 static const char alt_7[] =
783 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
784 /* nopl 0L(%[re]ax,%[re]ax,1) */
785 static const char alt_8[] =
786 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
787 /* nopw 0L(%[re]ax,%[re]ax,1) */
788 static const char alt_9[] =
789 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
790 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
791 static const char alt_10[] =
792 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
793 /* data16
794 nopw %cs:0L(%[re]ax,%[re]ax,1) */
795 static const char alt_long_11[] =
796 {0x66,
797 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
798 /* data16
799 data16
800 nopw %cs:0L(%[re]ax,%[re]ax,1) */
801 static const char alt_long_12[] =
802 {0x66,
803 0x66,
804 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
805 /* data16
806 data16
807 data16
808 nopw %cs:0L(%[re]ax,%[re]ax,1) */
809 static const char alt_long_13[] =
810 {0x66,
811 0x66,
812 0x66,
813 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
814 /* data16
815 data16
816 data16
817 data16
818 nopw %cs:0L(%[re]ax,%[re]ax,1) */
819 static const char alt_long_14[] =
820 {0x66,
821 0x66,
822 0x66,
823 0x66,
824 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
825 /* data16
826 data16
827 data16
828 data16
829 data16
830 nopw %cs:0L(%[re]ax,%[re]ax,1) */
831 static const char alt_long_15[] =
832 {0x66,
833 0x66,
834 0x66,
835 0x66,
836 0x66,
837 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
838 /* nopl 0(%[re]ax,%[re]ax,1)
839 nopw 0(%[re]ax,%[re]ax,1) */
840 static const char alt_short_11[] =
841 {0x0f,0x1f,0x44,0x00,0x00,
842 0x66,0x0f,0x1f,0x44,0x00,0x00};
843 /* nopw 0(%[re]ax,%[re]ax,1)
844 nopw 0(%[re]ax,%[re]ax,1) */
845 static const char alt_short_12[] =
846 {0x66,0x0f,0x1f,0x44,0x00,0x00,
847 0x66,0x0f,0x1f,0x44,0x00,0x00};
848 /* nopw 0(%[re]ax,%[re]ax,1)
849 nopl 0L(%[re]ax) */
850 static const char alt_short_13[] =
851 {0x66,0x0f,0x1f,0x44,0x00,0x00,
852 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
853 /* nopl 0L(%[re]ax)
854 nopl 0L(%[re]ax) */
855 static const char alt_short_14[] =
856 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
857 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
858 /* nopl 0L(%[re]ax)
859 nopl 0L(%[re]ax,%[re]ax,1) */
860 static const char alt_short_15[] =
861 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
862 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
863 static const char *const alt_short_patt[] = {
864 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
865 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
866 alt_short_14, alt_short_15
867 };
868 static const char *const alt_long_patt[] = {
869 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
870 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
871 alt_long_14, alt_long_15
872 };
252b5132 873
76bc74dc
L		 874 /* Only align for at least a positive non-zero boundary. */
875 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 876 return;
3e73aa7c 877
ccc9c027
L		 878 /* We need to decide which NOP sequence to use for 32bit and
879 64bit. When -mtune= is used:
4eed87de 880
76bc74dc
L		 881 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
882 PROCESSOR_GENERIC32, f32_patt will be used.
883 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
884 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
885 alt_long_patt will be used.
886 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
887 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 888
76bc74dc
L		 889 When -mtune= isn't used, alt_long_patt will be used if
890 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
891 be used.
ccc9c027
L		 892
893 When -march= or .arch is used, we can't use anything beyond
894 cpu_arch_isa_flags. */
895
896 if (flag_code == CODE_16BIT)
897 {
ccc9c027 898 if (count > 8)
33fef721 899 {
76bc74dc
L		 900 memcpy (fragP->fr_literal + fragP->fr_fix,
901 jump_31, count);
902 /* Adjust jump offset. */
903 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 904 }
76bc74dc
L		 905 else
906 memcpy (fragP->fr_literal + fragP->fr_fix,
907 f16_patt[count - 1], count);
252b5132 908 }
33fef721 909 else
ccc9c027
L		 910 {
911 const char *const *patt = NULL;
912
913 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
914 {
915 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
916 switch (cpu_arch_tune)
917 {
918 case PROCESSOR_UNKNOWN:
919 /* We use cpu_arch_isa_flags to check if we SHOULD
920 optimize for Cpu686. */
40fb9820 921 if (cpu_arch_isa_flags.bitfield.cpui686)
76bc74dc 922 patt = alt_long_patt;
ccc9c027
L		 923 else
924 patt = f32_patt;
925 break;
ccc9c027
L		 926 case PROCESSOR_PENTIUMPRO:
927 case PROCESSOR_PENTIUM4:
928 case PROCESSOR_NOCONA:
ef05d495 929 case PROCESSOR_CORE:
76bc74dc
L		 930 case PROCESSOR_CORE2:
931 case PROCESSOR_GENERIC64:
932 patt = alt_long_patt;
933 break;
ccc9c027
L		 934 case PROCESSOR_K6:
935 case PROCESSOR_ATHLON:
936 case PROCESSOR_K8:
4eed87de 937 case PROCESSOR_AMDFAM10:
ccc9c027
L		 938 patt = alt_short_patt;
939 break;
76bc74dc 940 case PROCESSOR_I386:
ccc9c027
L		 941 case PROCESSOR_I486:
942 case PROCESSOR_PENTIUM:
943 case PROCESSOR_GENERIC32:
944 patt = f32_patt;
945 break;
4eed87de 946 }
ccc9c027
L		 947 }
948 else
949 {
950 switch (cpu_arch_tune)
951 {
952 case PROCESSOR_UNKNOWN:
953 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
954 PROCESSOR_UNKNOWN. */
955 abort ();
956 break;
957
76bc74dc 958 case PROCESSOR_I386:
ccc9c027
L		 959 case PROCESSOR_I486:
960 case PROCESSOR_PENTIUM:
ccc9c027
L		 961 case PROCESSOR_K6:
962 case PROCESSOR_ATHLON:
963 case PROCESSOR_K8:
4eed87de 964 case PROCESSOR_AMDFAM10:
ccc9c027
L		 965 case PROCESSOR_GENERIC32:
966 /* We use cpu_arch_isa_flags to check if we CAN optimize
967 for Cpu686. */
40fb9820 968 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 969 patt = alt_short_patt;
970 else
971 patt = f32_patt;
972 break;
76bc74dc
L		 973 case PROCESSOR_PENTIUMPRO:
974 case PROCESSOR_PENTIUM4:
975 case PROCESSOR_NOCONA:
976 case PROCESSOR_CORE:
ef05d495 977 case PROCESSOR_CORE2:
40fb9820 978 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 979 patt = alt_long_patt;
980 else
981 patt = f32_patt;
982 break;
983 case PROCESSOR_GENERIC64:
76bc74dc 984 patt = alt_long_patt;
ccc9c027 985 break;
4eed87de 986 }
ccc9c027
L		 987 }
988
76bc74dc
L		 989 if (patt == f32_patt)
990 {
991 /* If the padding is less than 15 bytes, we use the normal
992 ones. Otherwise, we use a jump instruction and adjust
993 its offset. */
994 if (count < 15)
995 memcpy (fragP->fr_literal + fragP->fr_fix,
996 patt[count - 1], count);
997 else
998 {
999 memcpy (fragP->fr_literal + fragP->fr_fix,
1000 jump_31, count);
1001 /* Adjust jump offset. */
1002 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1003 }
1004 }
1005 else
1006 {
1007 /* Maximum length of an instruction is 15 byte. If the
1008 padding is greater than 15 bytes and we don't use jump,
1009 we have to break it into smaller pieces. */
1010 int padding = count;
1011 while (padding > 15)
1012 {
1013 padding -= 15;
1014 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1015 patt [14], 15);
1016 }
1017
1018 if (padding)
1019 memcpy (fragP->fr_literal + fragP->fr_fix,
1020 patt [padding - 1], padding);
1021 }
ccc9c027 1022 }
33fef721 1023 fragP->fr_var = count;
252b5132
RH		 1024}
1025
c6fb90c8
L		 1026static INLINE int
1027uints_all_zero (const unsigned int *x, unsigned int size)
40fb9820 1028{
c6fb90c8
L		 1029 switch (size)
1030 {
1031 case 3:
1032 if (x[2])
1033 return 0;
1034 case 2:
1035 if (x[1])
1036 return 0;
1037 case 1:
1038 return !x[0];
1039 default:
1040 abort ();
1041 }
40fb9820
L		 1042}
1043
c6fb90c8
L		 1044static INLINE void
1045uints_set (unsigned int *x, unsigned int v, unsigned int size)
40fb9820 1046{
c6fb90c8
L		 1047 switch (size)
1048 {
1049 case 3:
1050 x[2] = v;
1051 case 2:
1052 x[1] = v;
1053 case 1:
1054 x[0] = v;
1055 break;
1056 default:
1057 abort ();
1058 }
1059}
40fb9820 1060
c6fb90c8
L		 1061static INLINE int
1062uints_equal (const unsigned int *x, const unsigned int *y,
1063 unsigned int size)
1064{
1065 switch (size)
1066 {
1067 case 3:
1068 if (x[2] != y [2])
1069 return 0;
1070 case 2:
1071 if (x[1] != y [1])
1072 return 0;
1073 case 1:
1074 return x[0] == y [0];
1075 break;
1076 default:
1077 abort ();
1078 }
1079}
40fb9820 1080
c6fb90c8
L		 1081#define UINTS_ALL_ZERO(x) \
1082 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
1083#define UINTS_SET(x, v) \
1084 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
1085#define UINTS_CLEAR(x) \
1086 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
1087#define UINTS_EQUAL(x, y) \
1088 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
1089
1090static INLINE int
1091cpu_flags_check_cpu64 (i386_cpu_flags f)
1092{
1093 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1094 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1095}
1096
c6fb90c8
L		 1097static INLINE i386_cpu_flags
1098cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1099{
c6fb90c8
L		 1100 switch (ARRAY_SIZE (x.array))
1101 {
1102 case 3:
1103 x.array [2] &= y.array [2];
1104 case 2:
1105 x.array [1] &= y.array [1];
1106 case 1:
1107 x.array [0] &= y.array [0];
1108 break;
1109 default:
1110 abort ();
1111 }
1112 return x;
1113}
40fb9820 1114
c6fb90c8
L		 1115static INLINE i386_cpu_flags
1116cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1117{
c6fb90c8 1118 switch (ARRAY_SIZE (x.array))
40fb9820 1119 {
c6fb90c8
L		 1120 case 3:
1121 x.array [2] |= y.array [2];
1122 case 2:
1123 x.array [1] |= y.array [1];
1124 case 1:
1125 x.array [0] |= y.array [0];
40fb9820
L		 1126 break;
1127 default:
1128 abort ();
1129 }
40fb9820
L		 1130 return x;
1131}
1132
3629bb00
L		 1133/* Return 3 if there is a perfect match, 2 if compatible with 64bit,
1134 1 if compatible with arch, 0 if there is no match. */
1135
40fb9820
L		 1136static int
1137cpu_flags_match (i386_cpu_flags x)
1138{
3629bb00 1139 int overlap = cpu_flags_check_cpu64 (x) ? 2 : 0;
40fb9820
L		 1140
1141 x.bitfield.cpu64 = 0;
1142 x.bitfield.cpuno64 = 0;
1143
3629bb00
L		 1144 if (UINTS_ALL_ZERO (x))
1145 overlap |= 1;
1146 else
1147 {
1148 i386_cpu_flags cpu = cpu_arch_flags;
1149
1150 cpu.bitfield.cpu64 = 0;
1151 cpu.bitfield.cpuno64 = 0;
1152 cpu = cpu_flags_and (x, cpu);
1153 overlap |= UINTS_ALL_ZERO (cpu) ? 0 : 1;
1154 }
1155 return overlap;
40fb9820
L		 1156}
1157
c6fb90c8
L		 1158static INLINE i386_operand_type
1159operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1160{
c6fb90c8
L		 1161 switch (ARRAY_SIZE (x.array))
1162 {
1163 case 3:
1164 x.array [2] &= y.array [2];
1165 case 2:
1166 x.array [1] &= y.array [1];
1167 case 1:
1168 x.array [0] &= y.array [0];
1169 break;
1170 default:
1171 abort ();
1172 }
1173 return x;
40fb9820
L		 1174}
1175
c6fb90c8
L		 1176static INLINE i386_operand_type
1177operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1178{
c6fb90c8 1179 switch (ARRAY_SIZE (x.array))
40fb9820 1180 {
c6fb90c8
L		 1181 case 3:
1182 x.array [2] |= y.array [2];
1183 case 2:
1184 x.array [1] |= y.array [1];
1185 case 1:
1186 x.array [0] |= y.array [0];
40fb9820
L		 1187 break;
1188 default:
1189 abort ();
1190 }
c6fb90c8
L		 1191 return x;
1192}
40fb9820 1193
c6fb90c8
L		 1194static INLINE i386_operand_type
1195operand_type_xor (i386_operand_type x, i386_operand_type y)
1196{
1197 switch (ARRAY_SIZE (x.array))
1198 {
1199 case 3:
1200 x.array [2] ^= y.array [2];
1201 case 2:
1202 x.array [1] ^= y.array [1];
1203 case 1:
1204 x.array [0] ^= y.array [0];
1205 break;
1206 default:
1207 abort ();
1208 }
40fb9820
L		 1209 return x;
1210}
1211
1212static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1213static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1214static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1215static const i386_operand_type reg16_inoutportreg
1216 = OPERAND_TYPE_REG16_INOUTPORTREG;
1217static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1218static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1219static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1220static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1221static const i386_operand_type anydisp
1222 = OPERAND_TYPE_ANYDISP;
40fb9820
L		 1223static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1224static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1225static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1226static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1227static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1228static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1229static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1230static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1231static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1232static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1233
1234enum operand_type
1235{
1236 reg,
40fb9820
L		 1237 imm,
1238 disp,
1239 anymem
1240};
1241
c6fb90c8 1242static INLINE int
40fb9820
L		 1243operand_type_check (i386_operand_type t, enum operand_type c)
1244{
1245 switch (c)
1246 {
1247 case reg:
1248 return (t.bitfield.reg8
1249 || t.bitfield.reg16
1250 || t.bitfield.reg32
1251 || t.bitfield.reg64);
1252
40fb9820
L		 1253 case imm:
1254 return (t.bitfield.imm8
1255 || t.bitfield.imm8s
1256 || t.bitfield.imm16
1257 || t.bitfield.imm32
1258 || t.bitfield.imm32s
1259 || t.bitfield.imm64);
1260
1261 case disp:
1262 return (t.bitfield.disp8
1263 || t.bitfield.disp16
1264 || t.bitfield.disp32
1265 || t.bitfield.disp32s
1266 || t.bitfield.disp64);
1267
1268 case anymem:
1269 return (t.bitfield.disp8
1270 || t.bitfield.disp16
1271 || t.bitfield.disp32
1272 || t.bitfield.disp32s
1273 || t.bitfield.disp64
1274 || t.bitfield.baseindex);
1275
1276 default:
1277 abort ();
1278 }
1279}
1280
5c07affc
L		 1281/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1282 operand J for instruction template T. */
1283
1284static INLINE int
1285match_reg_size (const template *t, unsigned int j)
1286{
1287 return !((i.types[j].bitfield.byte
1288 && !t->operand_types[j].bitfield.byte)
1289 || (i.types[j].bitfield.word
1290 && !t->operand_types[j].bitfield.word)
1291 || (i.types[j].bitfield.dword
1292 && !t->operand_types[j].bitfield.dword)
1293 || (i.types[j].bitfield.qword
1294 && !t->operand_types[j].bitfield.qword));
1295}
1296
1297/* Return 1 if there is no conflict in any size on operand J for
1298 instruction template T. */
1299
1300static INLINE int
1301match_mem_size (const template *t, unsigned int j)
1302{
1303 return (match_reg_size (t, j)
1304 && !((i.types[j].bitfield.unspecified
1305 && !t->operand_types[j].bitfield.unspecified)
1306 || (i.types[j].bitfield.fword
1307 && !t->operand_types[j].bitfield.fword)
1308 || (i.types[j].bitfield.tbyte
1309 && !t->operand_types[j].bitfield.tbyte)
1310 || (i.types[j].bitfield.xmmword
1311 && !t->operand_types[j].bitfield.xmmword)));
1312}
1313
1314/* Return 1 if there is no size conflict on any operands for
1315 instruction template T. */
1316
1317static INLINE int
1318operand_size_match (const template *t)
1319{
1320 unsigned int j;
1321 int match = 1;
1322
1323 /* Don't check jump instructions. */
1324 if (t->opcode_modifier.jump
1325 || t->opcode_modifier.jumpbyte
1326 || t->opcode_modifier.jumpdword
1327 || t->opcode_modifier.jumpintersegment)
1328 return match;
1329
1330 /* Check memory and accumulator operand size. */
1331 for (j = 0; j < i.operands; j++)
1332 {
1333 if (t->operand_types[j].bitfield.anysize)
1334 continue;
1335
1336 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1337 {
1338 match = 0;
1339 break;
1340 }
1341
1342 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1343 {
1344 match = 0;
1345 break;
1346 }
1347 }
1348
1349 if (match
1350 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1351 return match;
1352
1353 /* Check reverse. */
1354 assert (i.operands == 2);
1355
1356 match = 1;
1357 for (j = 0; j < 2; j++)
1358 {
1359 if (t->operand_types[j].bitfield.acc
1360 && !match_reg_size (t, j ? 0 : 1))
1361 {
1362 match = 0;
1363 break;
1364 }
1365
1366 if (i.types[j].bitfield.mem
1367 && !match_mem_size (t, j ? 0 : 1))
1368 {
1369 match = 0;
1370 break;
1371 }
1372 }
1373
1374 return match;
1375}
1376
c6fb90c8 1377static INLINE int
40fb9820
L		 1378operand_type_match (i386_operand_type overlap,
1379 i386_operand_type given)
1380{
1381 i386_operand_type temp = overlap;
1382
1383 temp.bitfield.jumpabsolute = 0;
7d5e4556 1384 temp.bitfield.unspecified = 0;
5c07affc
L		 1385 temp.bitfield.byte = 0;
1386 temp.bitfield.word = 0;
1387 temp.bitfield.dword = 0;
1388 temp.bitfield.fword = 0;
1389 temp.bitfield.qword = 0;
1390 temp.bitfield.tbyte = 0;
1391 temp.bitfield.xmmword = 0;
c6fb90c8 1392 if (UINTS_ALL_ZERO (temp))
40fb9820
L		 1393 return 0;
1394
1395 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1396 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1397}
1398
7d5e4556 1399/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1400 unless the expected operand type register overlap is null.
1401 Note that Acc in a template matches every size of reg. */
1402
c6fb90c8 1403static INLINE int
40fb9820
L		 1404operand_type_register_match (i386_operand_type m0,
1405 i386_operand_type g0,
1406 i386_operand_type t0,
1407 i386_operand_type m1,
1408 i386_operand_type g1,
1409 i386_operand_type t1)
1410{
1411 if (!operand_type_check (g0, reg))
1412 return 1;
1413
1414 if (!operand_type_check (g1, reg))
1415 return 1;
1416
1417 if (g0.bitfield.reg8 == g1.bitfield.reg8
1418 && g0.bitfield.reg16 == g1.bitfield.reg16
1419 && g0.bitfield.reg32 == g1.bitfield.reg32
1420 && g0.bitfield.reg64 == g1.bitfield.reg64)
1421 return 1;
1422
1423 if (m0.bitfield.acc)
1424 {
1425 t0.bitfield.reg8 = 1;
1426 t0.bitfield.reg16 = 1;
1427 t0.bitfield.reg32 = 1;
1428 t0.bitfield.reg64 = 1;
1429 }
1430
1431 if (m1.bitfield.acc)
1432 {
1433 t1.bitfield.reg8 = 1;
1434 t1.bitfield.reg16 = 1;
1435 t1.bitfield.reg32 = 1;
1436 t1.bitfield.reg64 = 1;
1437 }
1438
1439 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1440 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1441 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1442 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1443}
1444
252b5132 1445static INLINE unsigned int
40fb9820 1446mode_from_disp_size (i386_operand_type t)
252b5132 1447{
40fb9820
L		 1448 if (t.bitfield.disp8)
1449 return 1;
1450 else if (t.bitfield.disp16
1451 || t.bitfield.disp32
1452 || t.bitfield.disp32s)
1453 return 2;
1454 else
1455 return 0;
252b5132
RH		 1456}
1457
1458static INLINE int
e3bb37b5 1459fits_in_signed_byte (offsetT num)
252b5132
RH		 1460{
1461 return (num >= -128) && (num <= 127);
47926f60 1462}
252b5132
RH		 1463
1464static INLINE int
e3bb37b5 1465fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1466{
1467 return (num & 0xff) == num;
47926f60 1468}
252b5132
RH		 1469
1470static INLINE int
e3bb37b5 1471fits_in_unsigned_word (offsetT num)
252b5132
RH		 1472{
1473 return (num & 0xffff) == num;
47926f60 1474}
252b5132
RH		 1475
1476static INLINE int
e3bb37b5 1477fits_in_signed_word (offsetT num)
252b5132
RH		 1478{
1479 return (-32768 <= num) && (num <= 32767);
47926f60 1480}
2a962e6d 1481
3e73aa7c 1482static INLINE int
e3bb37b5 1483fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1484{
1485#ifndef BFD64
1486 return 1;
1487#else
1488 return (!(((offsetT) -1 << 31) & num)
1489 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1490#endif
1491} /* fits_in_signed_long() */
2a962e6d 1492
3e73aa7c 1493static INLINE int
e3bb37b5 1494fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1495{
1496#ifndef BFD64
1497 return 1;
1498#else
1499 return (num & (((offsetT) 2 << 31) - 1)) == num;
1500#endif
1501} /* fits_in_unsigned_long() */
252b5132 1502
40fb9820 1503static i386_operand_type
e3bb37b5 1504smallest_imm_type (offsetT num)
252b5132 1505{
40fb9820
L		 1506 i386_operand_type t;
1507
c6fb90c8 1508 UINTS_CLEAR (t);
40fb9820
L		 1509 t.bitfield.imm64 = 1;
1510
1511 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1512 {
1513 /* This code is disabled on the 486 because all the Imm1 forms
1514 in the opcode table are slower on the i486. They're the
1515 versions with the implicitly specified single-position
1516 displacement, which has another syntax if you really want to
1517 use that form. */
40fb9820
L		 1518 t.bitfield.imm1 = 1;
1519 t.bitfield.imm8 = 1;
1520 t.bitfield.imm8s = 1;
1521 t.bitfield.imm16 = 1;
1522 t.bitfield.imm32 = 1;
1523 t.bitfield.imm32s = 1;
1524 }
1525 else if (fits_in_signed_byte (num))
1526 {
1527 t.bitfield.imm8 = 1;
1528 t.bitfield.imm8s = 1;
1529 t.bitfield.imm16 = 1;
1530 t.bitfield.imm32 = 1;
1531 t.bitfield.imm32s = 1;
1532 }
1533 else if (fits_in_unsigned_byte (num))
1534 {
1535 t.bitfield.imm8 = 1;
1536 t.bitfield.imm16 = 1;
1537 t.bitfield.imm32 = 1;
1538 t.bitfield.imm32s = 1;
1539 }
1540 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1541 {
1542 t.bitfield.imm16 = 1;
1543 t.bitfield.imm32 = 1;
1544 t.bitfield.imm32s = 1;
1545 }
1546 else if (fits_in_signed_long (num))
1547 {
1548 t.bitfield.imm32 = 1;
1549 t.bitfield.imm32s = 1;
1550 }
1551 else if (fits_in_unsigned_long (num))
1552 t.bitfield.imm32 = 1;
1553
1554 return t;
47926f60 1555}
252b5132 1556
847f7ad4 1557static offsetT
e3bb37b5 1558offset_in_range (offsetT val, int size)
847f7ad4 1559{
508866be 1560 addressT mask;
ba2adb93 1561
847f7ad4
AM		 1562 switch (size)
1563 {
508866be
L		 1564 case 1: mask = ((addressT) 1 << 8) - 1; break;
1565 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1566 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1567#ifdef BFD64
1568 case 8: mask = ((addressT) 2 << 63) - 1; break;
1569#endif
47926f60 1570 default: abort ();
847f7ad4
AM		 1571 }
1572
ba2adb93 1573 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1574 if (!use_rela_relocations)
1575 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1576 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1577
47926f60 1578 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1579 {
1580 char buf1[40], buf2[40];
1581
1582 sprint_value (buf1, val);
1583 sprint_value (buf2, val & mask);
1584 as_warn (_("%s shortened to %s"), buf1, buf2);
1585 }
1586 return val & mask;
1587}
1588
252b5132
RH		 1589/* Returns 0 if attempting to add a prefix where one from the same
1590 class already exists, 1 if non rep/repne added, 2 if rep/repne
1591 added. */
1592static int
e3bb37b5 1593add_prefix (unsigned int prefix)
252b5132
RH		 1594{
1595 int ret = 1;
b1905489 1596 unsigned int q;
252b5132 1597
29b0f896
AM		 1598 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1599 && flag_code == CODE_64BIT)
b1905489 1600 {
161a04f6
L		 1601 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1602 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1603 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1604 ret = 0;
1605 q = REX_PREFIX;
1606 }
3e73aa7c 1607 else
b1905489
JB		 1608 {
1609 switch (prefix)
1610 {
1611 default:
1612 abort ();
1613
1614 case CS_PREFIX_OPCODE:
1615 case DS_PREFIX_OPCODE:
1616 case ES_PREFIX_OPCODE:
1617 case FS_PREFIX_OPCODE:
1618 case GS_PREFIX_OPCODE:
1619 case SS_PREFIX_OPCODE:
1620 q = SEG_PREFIX;
1621 break;
1622
1623 case REPNE_PREFIX_OPCODE:
1624 case REPE_PREFIX_OPCODE:
1625 ret = 2;
1626 /* fall thru */
1627 case LOCK_PREFIX_OPCODE:
1628 q = LOCKREP_PREFIX;
1629 break;
1630
1631 case FWAIT_OPCODE:
1632 q = WAIT_PREFIX;
1633 break;
1634
1635 case ADDR_PREFIX_OPCODE:
1636 q = ADDR_PREFIX;
1637 break;
1638
1639 case DATA_PREFIX_OPCODE:
1640 q = DATA_PREFIX;
1641 break;
1642 }
1643 if (i.prefix[q] != 0)
1644 ret = 0;
1645 }
252b5132 1646
b1905489 1647 if (ret)
252b5132 1648 {
b1905489
JB		 1649 if (!i.prefix[q])
1650 ++i.prefixes;
1651 i.prefix[q] |= prefix;
252b5132 1652 }
b1905489
JB		 1653 else
1654 as_bad (_("same type of prefix used twice"));
252b5132 1655
252b5132
RH		 1656 return ret;
1657}
1658
1659static void
e3bb37b5 1660set_code_flag (int value)
eecb386c 1661{
3e73aa7c 1662 flag_code = value;
40fb9820
L		 1663 if (flag_code == CODE_64BIT)
1664 {
1665 cpu_arch_flags.bitfield.cpu64 = 1;
1666 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1667 }
1668 else
1669 {
1670 cpu_arch_flags.bitfield.cpu64 = 0;
1671 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1672 }
1673 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1674 {
1675 as_bad (_("64bit mode not supported on this CPU."));
1676 }
40fb9820 1677 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1678 {
1679 as_bad (_("32bit mode not supported on this CPU."));
1680 }
eecb386c
AM		 1681 stackop_size = '\0';
1682}
1683
1684static void
e3bb37b5 1685set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1686{
3e73aa7c 1687 flag_code = new_code_flag;
40fb9820
L		 1688 if (flag_code != CODE_16BIT)
1689 abort ();
1690 cpu_arch_flags.bitfield.cpu64 = 0;
1691 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1692 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1693}
1694
1695static void
e3bb37b5 1696set_intel_syntax (int syntax_flag)
252b5132
RH		 1697{
1698 /* Find out if register prefixing is specified. */
1699 int ask_naked_reg = 0;
1700
1701 SKIP_WHITESPACE ();
29b0f896 1702 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1703 {
1704 char *string = input_line_pointer;
1705 int e = get_symbol_end ();
1706
47926f60 1707 if (strcmp (string, "prefix") == 0)
252b5132 1708 ask_naked_reg = 1;
47926f60 1709 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1710 ask_naked_reg = -1;
1711 else
d0b47220 1712 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1713 *input_line_pointer = e;
1714 }
1715 demand_empty_rest_of_line ();
c3332e24 1716
252b5132
RH		 1717 intel_syntax = syntax_flag;
1718
1719 if (ask_naked_reg == 0)
f86103b7
AM		 1720 allow_naked_reg = (intel_syntax
1721 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1722 else
1723 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1724
e4a3b5a4 1725 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1726 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1727 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1728}
1729
1efbbeb4
L		 1730static void
1731set_intel_mnemonic (int mnemonic_flag)
1732{
e1d4d893 1733 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1734}
1735
db51cc60
L		 1736static void
1737set_allow_index_reg (int flag)
1738{
1739 allow_index_reg = flag;
1740}
1741
e413e4e9 1742static void
e3bb37b5 1743set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1744{
47926f60 1745 SKIP_WHITESPACE ();
e413e4e9 1746
29b0f896 1747 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1748 {
1749 char *string = input_line_pointer;
1750 int e = get_symbol_end ();
9103f4f4 1751 unsigned int i;
40fb9820 1752 i386_cpu_flags flags;
e413e4e9 1753
9103f4f4 1754 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1755 {
1756 if (strcmp (string, cpu_arch[i].name) == 0)
1757 {
5c6af06e
JB		 1758 if (*string != '.')
1759 {
1760 cpu_arch_name = cpu_arch[i].name;
1761 cpu_sub_arch_name = NULL;
40fb9820
L		 1762 cpu_arch_flags = cpu_arch[i].flags;
1763 if (flag_code == CODE_64BIT)
1764 {
1765 cpu_arch_flags.bitfield.cpu64 = 1;
1766 cpu_arch_flags.bitfield.cpuno64 = 0;
1767 }
1768 else
1769 {
1770 cpu_arch_flags.bitfield.cpu64 = 0;
1771 cpu_arch_flags.bitfield.cpuno64 = 1;
1772 }
ccc9c027 1773 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1774 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1775 if (!cpu_arch_tune_set)
1776 {
1777 cpu_arch_tune = cpu_arch_isa;
1778 cpu_arch_tune_flags = cpu_arch_isa_flags;
1779 }
5c6af06e
JB		 1780 break;
1781 }
40fb9820 1782
c6fb90c8
L		 1783 flags = cpu_flags_or (cpu_arch_flags,
1784 cpu_arch[i].flags);
1785 if (!UINTS_EQUAL (flags, cpu_arch_flags))
5c6af06e 1786 {
6305a203
L		 1787 if (cpu_sub_arch_name)
1788 {
1789 char *name = cpu_sub_arch_name;
1790 cpu_sub_arch_name = concat (name,
1791 cpu_arch[i].name,
1bf57e9f 1792 (const char *) NULL);
6305a203
L		 1793 free (name);
1794 }
1795 else
1796 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 1797 cpu_arch_flags = flags;
5c6af06e
JB		 1798 }
1799 *input_line_pointer = e;
1800 demand_empty_rest_of_line ();
1801 return;
e413e4e9
AM		 1802 }
1803 }
9103f4f4 1804 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1805 as_bad (_("no such architecture: `%s'"), string);
1806
1807 *input_line_pointer = e;
1808 }
1809 else
1810 as_bad (_("missing cpu architecture"));
1811
fddf5b5b
AM		 1812 no_cond_jump_promotion = 0;
1813 if (*input_line_pointer == ','
29b0f896 1814 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1815 {
1816 char *string = ++input_line_pointer;
1817 int e = get_symbol_end ();
1818
1819 if (strcmp (string, "nojumps") == 0)
1820 no_cond_jump_promotion = 1;
1821 else if (strcmp (string, "jumps") == 0)
1822 ;
1823 else
1824 as_bad (_("no such architecture modifier: `%s'"), string);
1825
1826 *input_line_pointer = e;
1827 }
1828
e413e4e9
AM		 1829 demand_empty_rest_of_line ();
1830}
1831
b9d79e03
JH		 1832unsigned long
1833i386_mach ()
1834{
1835 if (!strcmp (default_arch, "x86_64"))
1836 return bfd_mach_x86_64;
1837 else if (!strcmp (default_arch, "i386"))
1838 return bfd_mach_i386_i386;
1839 else
1840 as_fatal (_("Unknown architecture"));
1841}
b9d79e03 1842\f
252b5132
RH		 1843void
1844md_begin ()
1845{
1846 const char *hash_err;
1847
47926f60 1848 /* Initialize op_hash hash table. */
252b5132
RH		 1849 op_hash = hash_new ();
1850
1851 {
29b0f896
AM		 1852 const template *optab;
1853 templates *core_optab;
252b5132 1854
47926f60
KH		 1855 /* Setup for loop. */
1856 optab = i386_optab;
252b5132
RH		 1857 core_optab = (templates *) xmalloc (sizeof (templates));
1858 core_optab->start = optab;
1859
1860 while (1)
1861 {
1862 ++optab;
1863 if (optab->name == NULL
1864 || strcmp (optab->name, (optab - 1)->name) != 0)
1865 {
1866 /* different name --> ship out current template list;
47926f60 1867 add to hash table; & begin anew. */
252b5132
RH		 1868 core_optab->end = optab;
1869 hash_err = hash_insert (op_hash,
1870 (optab - 1)->name,
1871 (PTR) core_optab);
1872 if (hash_err)
1873 {
252b5132
RH		 1874 as_fatal (_("Internal Error: Can't hash %s: %s"),
1875 (optab - 1)->name,
1876 hash_err);
1877 }
1878 if (optab->name == NULL)
1879 break;
1880 core_optab = (templates *) xmalloc (sizeof (templates));
1881 core_optab->start = optab;
1882 }
1883 }
1884 }
1885
47926f60 1886 /* Initialize reg_hash hash table. */
252b5132
RH		 1887 reg_hash = hash_new ();
1888 {
29b0f896 1889 const reg_entry *regtab;
c3fe08fa 1890 unsigned int regtab_size = i386_regtab_size;
252b5132 1891
c3fe08fa 1892 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1893 {
1894 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1895 if (hash_err)
3e73aa7c
JH		 1896 as_fatal (_("Internal Error: Can't hash %s: %s"),
1897 regtab->reg_name,
1898 hash_err);
252b5132
RH		 1899 }
1900 }
1901
47926f60 1902 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1903 {
29b0f896
AM		 1904 int c;
1905 char *p;
252b5132
RH		 1906
1907 for (c = 0; c < 256; c++)
1908 {
3882b010 1909 if (ISDIGIT (c))
252b5132
RH		 1910 {
1911 digit_chars[c] = c;
1912 mnemonic_chars[c] = c;
1913 register_chars[c] = c;
1914 operand_chars[c] = c;
1915 }
3882b010 1916 else if (ISLOWER (c))
252b5132
RH		 1917 {
1918 mnemonic_chars[c] = c;
1919 register_chars[c] = c;
1920 operand_chars[c] = c;
1921 }
3882b010 1922 else if (ISUPPER (c))
252b5132 1923 {
3882b010 1924 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1925 register_chars[c] = mnemonic_chars[c];
1926 operand_chars[c] = c;
1927 }
1928
3882b010 1929 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1930 identifier_chars[c] = c;
1931 else if (c >= 128)
1932 {
1933 identifier_chars[c] = c;
1934 operand_chars[c] = c;
1935 }
1936 }
1937
1938#ifdef LEX_AT
1939 identifier_chars['@'] = '@';
32137342
NC		 1940#endif
1941#ifdef LEX_QM
1942 identifier_chars['?'] = '?';
1943 operand_chars['?'] = '?';
252b5132 1944#endif
252b5132 1945 digit_chars['-'] = '-';
791fe849 1946 mnemonic_chars['-'] = '-';
0003779b 1947 mnemonic_chars['.'] = '.';
252b5132
RH		 1948 identifier_chars['_'] = '_';
1949 identifier_chars['.'] = '.';
1950
1951 for (p = operand_special_chars; *p != '\0'; p++)
1952 operand_chars[(unsigned char) *p] = *p;
1953 }
1954
1955#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1956 if (IS_ELF)
252b5132
RH		 1957 {
1958 record_alignment (text_section, 2);
1959 record_alignment (data_section, 2);
1960 record_alignment (bss_section, 2);
1961 }
1962#endif
a4447b93
RH		 1963
1964 if (flag_code == CODE_64BIT)
1965 {
1966 x86_dwarf2_return_column = 16;
1967 x86_cie_data_alignment = -8;
1968 }
1969 else
1970 {
1971 x86_dwarf2_return_column = 8;
1972 x86_cie_data_alignment = -4;
1973 }
252b5132
RH		 1974}
1975
1976void
e3bb37b5 1977i386_print_statistics (FILE *file)
252b5132
RH		 1978{
1979 hash_print_statistics (file, "i386 opcode", op_hash);
1980 hash_print_statistics (file, "i386 register", reg_hash);
1981}
1982\f
252b5132
RH		 1983#ifdef DEBUG386
1984
ce8a8b2f 1985/* Debugging routines for md_assemble. */
e3bb37b5 1986static void pte (template *);
40fb9820 1987static void pt (i386_operand_type);
e3bb37b5
L		 1988static void pe (expressionS *);
1989static void ps (symbolS *);
252b5132
RH		 1990
1991static void
e3bb37b5 1992pi (char *line, i386_insn *x)
252b5132 1993{
09f131f2 1994 unsigned int i;
252b5132
RH		 1995
1996 fprintf (stdout, "%s: template ", line);
1997 pte (&x->tm);
09f131f2
JH		 1998 fprintf (stdout, " address: base %s index %s scale %x\n",
1999 x->base_reg ? x->base_reg->reg_name : "none",
2000 x->index_reg ? x->index_reg->reg_name : "none",
2001 x->log2_scale_factor);
2002 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2003 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2004 fprintf (stdout, " sib: base %x index %x scale %x\n",
2005 x->sib.base, x->sib.index, x->sib.scale);
2006 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2007 (x->rex & REX_W) != 0,
2008 (x->rex & REX_R) != 0,
2009 (x->rex & REX_X) != 0,
2010 (x->rex & REX_B) != 0);
85f10a01
MM		 2011 fprintf (stdout, " drex: reg %d rex 0x%x\n",
2012 x->drex.reg, x->drex.rex);
252b5132
RH		 2013 for (i = 0; i < x->operands; i++)
2014 {
2015 fprintf (stdout, " #%d: ", i + 1);
2016 pt (x->types[i]);
2017 fprintf (stdout, "\n");
40fb9820
L		 2018 if (x->types[i].bitfield.reg8
2019 || x->types[i].bitfield.reg16
2020 || x->types[i].bitfield.reg32
2021 || x->types[i].bitfield.reg64
2022 || x->types[i].bitfield.regmmx
2023 || x->types[i].bitfield.regxmm
2024 || x->types[i].bitfield.sreg2
2025 || x->types[i].bitfield.sreg3
2026 || x->types[i].bitfield.control
2027 || x->types[i].bitfield.debug
2028 || x->types[i].bitfield.test)
520dc8e8 2029 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2030 if (operand_type_check (x->types[i], imm))
520dc8e8 2031 pe (x->op[i].imms);
40fb9820 2032 if (operand_type_check (x->types[i], disp))
520dc8e8 2033 pe (x->op[i].disps);
252b5132
RH		 2034 }
2035}
2036
2037static void
e3bb37b5 2038pte (template *t)
252b5132 2039{
09f131f2 2040 unsigned int i;
252b5132 2041 fprintf (stdout, " %d operands ", t->operands);
47926f60 2042 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2043 if (t->extension_opcode != None)
2044 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2045 if (t->opcode_modifier.d)
252b5132 2046 fprintf (stdout, "D");
40fb9820 2047 if (t->opcode_modifier.w)
252b5132
RH		 2048 fprintf (stdout, "W");
2049 fprintf (stdout, "\n");
2050 for (i = 0; i < t->operands; i++)
2051 {
2052 fprintf (stdout, " #%d type ", i + 1);
2053 pt (t->operand_types[i]);
2054 fprintf (stdout, "\n");
2055 }
2056}
2057
2058static void
e3bb37b5 2059pe (expressionS *e)
252b5132 2060{
24eab124 2061 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2062 fprintf (stdout, " add_number %ld (%lx)\n",
2063 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2064 if (e->X_add_symbol)
2065 {
2066 fprintf (stdout, " add_symbol ");
2067 ps (e->X_add_symbol);
2068 fprintf (stdout, "\n");
2069 }
2070 if (e->X_op_symbol)
2071 {
2072 fprintf (stdout, " op_symbol ");
2073 ps (e->X_op_symbol);
2074 fprintf (stdout, "\n");
2075 }
2076}
2077
2078static void
e3bb37b5 2079ps (symbolS *s)
252b5132
RH		 2080{
2081 fprintf (stdout, "%s type %s%s",
2082 S_GET_NAME (s),
2083 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2084 segment_name (S_GET_SEGMENT (s)));
2085}
2086
7b81dfbb 2087static struct type_name
252b5132 2088 {
40fb9820
L		 2089 i386_operand_type mask;
2090 const char *name;
252b5132 2091 }
7b81dfbb 2092const type_names[] =
252b5132 2093{
40fb9820
L		 2094 { OPERAND_TYPE_REG8, "r8" },
2095 { OPERAND_TYPE_REG16, "r16" },
2096 { OPERAND_TYPE_REG32, "r32" },
2097 { OPERAND_TYPE_REG64, "r64" },
2098 { OPERAND_TYPE_IMM8, "i8" },
2099 { OPERAND_TYPE_IMM8, "i8s" },
2100 { OPERAND_TYPE_IMM16, "i16" },
2101 { OPERAND_TYPE_IMM32, "i32" },
2102 { OPERAND_TYPE_IMM32S, "i32s" },
2103 { OPERAND_TYPE_IMM64, "i64" },
2104 { OPERAND_TYPE_IMM1, "i1" },
2105 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2106 { OPERAND_TYPE_DISP8, "d8" },
2107 { OPERAND_TYPE_DISP16, "d16" },
2108 { OPERAND_TYPE_DISP32, "d32" },
2109 { OPERAND_TYPE_DISP32S, "d32s" },
2110 { OPERAND_TYPE_DISP64, "d64" },
2111 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2112 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2113 { OPERAND_TYPE_CONTROL, "control reg" },
2114 { OPERAND_TYPE_TEST, "test reg" },
2115 { OPERAND_TYPE_DEBUG, "debug reg" },
2116 { OPERAND_TYPE_FLOATREG, "FReg" },
2117 { OPERAND_TYPE_FLOATACC, "FAcc" },
2118 { OPERAND_TYPE_SREG2, "SReg2" },
2119 { OPERAND_TYPE_SREG3, "SReg3" },
2120 { OPERAND_TYPE_ACC, "Acc" },
2121 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2122 { OPERAND_TYPE_REGMMX, "rMMX" },
2123 { OPERAND_TYPE_REGXMM, "rXMM" },
2124 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2125};
2126
2127static void
40fb9820 2128pt (i386_operand_type t)
252b5132 2129{
40fb9820 2130 unsigned int j;
c6fb90c8 2131 i386_operand_type a;
252b5132 2132
40fb9820 2133 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2134 {
2135 a = operand_type_and (t, type_names[j].mask);
2136 if (!UINTS_ALL_ZERO (a))
2137 fprintf (stdout, "%s, ", type_names[j].name);
2138 }
252b5132
RH		 2139 fflush (stdout);
2140}
2141
2142#endif /* DEBUG386 */
2143\f
252b5132 2144static bfd_reloc_code_real_type
3956db08 2145reloc (unsigned int size,
64e74474
AM		 2146 int pcrel,
2147 int sign,
2148 bfd_reloc_code_real_type other)
252b5132 2149{
47926f60 2150 if (other != NO_RELOC)
3956db08
JB		 2151 {
2152 reloc_howto_type *reloc;
2153
2154 if (size == 8)
2155 switch (other)
2156 {
64e74474
AM		 2157 case BFD_RELOC_X86_64_GOT32:
2158 return BFD_RELOC_X86_64_GOT64;
2159 break;
2160 case BFD_RELOC_X86_64_PLTOFF64:
2161 return BFD_RELOC_X86_64_PLTOFF64;
2162 break;
2163 case BFD_RELOC_X86_64_GOTPC32:
2164 other = BFD_RELOC_X86_64_GOTPC64;
2165 break;
2166 case BFD_RELOC_X86_64_GOTPCREL:
2167 other = BFD_RELOC_X86_64_GOTPCREL64;
2168 break;
2169 case BFD_RELOC_X86_64_TPOFF32:
2170 other = BFD_RELOC_X86_64_TPOFF64;
2171 break;
2172 case BFD_RELOC_X86_64_DTPOFF32:
2173 other = BFD_RELOC_X86_64_DTPOFF64;
2174 break;
2175 default:
2176 break;
3956db08 2177 }
e05278af
JB		 2178
2179 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2180 if (size == 4 && flag_code != CODE_64BIT)
2181 sign = -1;
2182
3956db08
JB		 2183 reloc = bfd_reloc_type_lookup (stdoutput, other);
2184 if (!reloc)
2185 as_bad (_("unknown relocation (%u)"), other);
2186 else if (size != bfd_get_reloc_size (reloc))
2187 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2188 bfd_get_reloc_size (reloc),
2189 size);
2190 else if (pcrel && !reloc->pc_relative)
2191 as_bad (_("non-pc-relative relocation for pc-relative field"));
2192 else if ((reloc->complain_on_overflow == complain_overflow_signed
2193 && !sign)
2194 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2195 && sign > 0))
3956db08
JB		 2196 as_bad (_("relocated field and relocation type differ in signedness"));
2197 else
2198 return other;
2199 return NO_RELOC;
2200 }
252b5132
RH		 2201
2202 if (pcrel)
2203 {
3e73aa7c 2204 if (!sign)
3956db08 2205 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2206 switch (size)
2207 {
2208 case 1: return BFD_RELOC_8_PCREL;
2209 case 2: return BFD_RELOC_16_PCREL;
2210 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2211 case 8: return BFD_RELOC_64_PCREL;
252b5132 2212 }
3956db08 2213 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2214 }
2215 else
2216 {
3956db08 2217 if (sign > 0)
e5cb08ac 2218 switch (size)
3e73aa7c
JH		 2219 {
2220 case 4: return BFD_RELOC_X86_64_32S;
2221 }
2222 else
2223 switch (size)
2224 {
2225 case 1: return BFD_RELOC_8;
2226 case 2: return BFD_RELOC_16;
2227 case 4: return BFD_RELOC_32;
2228 case 8: return BFD_RELOC_64;
2229 }
3956db08
JB		 2230 as_bad (_("cannot do %s %u byte relocation"),
2231 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2232 }
2233
bfb32b52 2234 abort ();
252b5132
RH		 2235 return BFD_RELOC_NONE;
2236}
2237
47926f60
KH		 2238/* Here we decide which fixups can be adjusted to make them relative to
2239 the beginning of the section instead of the symbol. Basically we need
2240 to make sure that the dynamic relocations are done correctly, so in
2241 some cases we force the original symbol to be used. */
2242
252b5132 2243int
e3bb37b5 2244tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2245{
6d249963 2246#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2247 if (!IS_ELF)
31312f95
AM		 2248 return 1;
2249
a161fe53
AM		 2250 /* Don't adjust pc-relative references to merge sections in 64-bit
2251 mode. */
2252 if (use_rela_relocations
2253 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2254 && fixP->fx_pcrel)
252b5132 2255 return 0;
31312f95 2256
8d01d9a9
AJ		 2257 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2258 and changed later by validate_fix. */
2259 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2260 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2261 return 0;
2262
ce8a8b2f 2263 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2264 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2265 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2266 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2267 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2268 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2269 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2270 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2271 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2272 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2273 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2274 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2275 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2276 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2277 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2278 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2279 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2280 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2281 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2282 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2283 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2284 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2285 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2286 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2287 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2288 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2289 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2290 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2291 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2292 return 0;
31312f95 2293#endif
252b5132
RH		 2294 return 1;
2295}
252b5132 2296
b4cac588 2297static int
e3bb37b5 2298intel_float_operand (const char *mnemonic)
252b5132 2299{
9306ca4a
JB		 2300 /* Note that the value returned is meaningful only for opcodes with (memory)
2301 operands, hence the code here is free to improperly handle opcodes that
2302 have no operands (for better performance and smaller code). */
2303
2304 if (mnemonic[0] != 'f')
2305 return 0; /* non-math */
2306
2307 switch (mnemonic[1])
2308 {
2309 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2310 the fs segment override prefix not currently handled because no
2311 call path can make opcodes without operands get here */
2312 case 'i':
2313 return 2 /* integer op */;
2314 case 'l':
2315 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2316 return 3; /* fldcw/fldenv */
2317 break;
2318 case 'n':
2319 if (mnemonic[2] != 'o' /* fnop */)
2320 return 3; /* non-waiting control op */
2321 break;
2322 case 'r':
2323 if (mnemonic[2] == 's')
2324 return 3; /* frstor/frstpm */
2325 break;
2326 case 's':
2327 if (mnemonic[2] == 'a')
2328 return 3; /* fsave */
2329 if (mnemonic[2] == 't')
2330 {
2331 switch (mnemonic[3])
2332 {
2333 case 'c': /* fstcw */
2334 case 'd': /* fstdw */
2335 case 'e': /* fstenv */
2336 case 's': /* fsts[gw] */
2337 return 3;
2338 }
2339 }
2340 break;
2341 case 'x':
2342 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2343 return 0; /* fxsave/fxrstor are not really math ops */
2344 break;
2345 }
252b5132 2346
9306ca4a 2347 return 1;
252b5132
RH		 2348}
2349
2350/* This is the guts of the machine-dependent assembler. LINE points to a
2351 machine dependent instruction. This function is supposed to emit
2352 the frags/bytes it assembles to. */
2353
2354void
2355md_assemble (line)
2356 char *line;
2357{
40fb9820 2358 unsigned int j;
252b5132
RH		 2359 char mnemonic[MAX_MNEM_SIZE];
2360
47926f60 2361 /* Initialize globals. */
252b5132
RH		 2362 memset (&i, '\0', sizeof (i));
2363 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2364 i.reloc[j] = NO_RELOC;
252b5132
RH		 2365 memset (disp_expressions, '\0', sizeof (disp_expressions));
2366 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2367 save_stack_p = save_stack;
252b5132
RH		 2368
2369 /* First parse an instruction mnemonic & call i386_operand for the operands.
2370 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2371 start of a (possibly prefixed) mnemonic. */
252b5132 2372
29b0f896
AM		 2373 line = parse_insn (line, mnemonic);
2374 if (line == NULL)
2375 return;
252b5132 2376
29b0f896
AM		 2377 line = parse_operands (line, mnemonic);
2378 if (line == NULL)
2379 return;
252b5132 2380
29b0f896
AM		 2381 /* Now we've parsed the mnemonic into a set of templates, and have the
2382 operands at hand. */
2383
2384 /* All intel opcodes have reversed operands except for "bound" and
2385 "enter". We also don't reverse intersegment "jmp" and "call"
2386 instructions with 2 immediate operands so that the immediate segment
050dfa73 2387 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2388 if (intel_syntax
2389 && i.operands > 1
29b0f896 2390 && (strcmp (mnemonic, "bound") != 0)
30123838 2391 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2392 && !(operand_type_check (i.types[0], imm)
2393 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2394 swap_operands ();
2395
ec56d5c0
JB		 2396 /* The order of the immediates should be reversed
2397 for 2 immediates extrq and insertq instructions */
2398 if (i.imm_operands == 2
2399 && (strcmp (mnemonic, "extrq") == 0
2400 || strcmp (mnemonic, "insertq") == 0))
2401 swap_2_operands (0, 1);
2402
29b0f896
AM		 2403 if (i.imm_operands)
2404 optimize_imm ();
2405
b300c311
L		 2406 /* Don't optimize displacement for movabs since it only takes 64bit
2407 displacement. */
2408 if (i.disp_operands
2409 && (flag_code != CODE_64BIT
2410 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2411 optimize_disp ();
2412
2413 /* Next, we find a template that matches the given insn,
2414 making sure the overlap of the given operands types is consistent
2415 with the template operand types. */
252b5132 2416
29b0f896
AM		 2417 if (!match_template ())
2418 return;
252b5132 2419
321fd21e
L		 2420 /* Zap movzx and movsx suffix. The suffix has been set from
2421 "word ptr" or "byte ptr" on the source operand in Intel syntax
2422 or extracted from mnemonic in AT&T syntax. But we'll use
2423 the destination register to choose the suffix for encoding. */
2424 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2425 {
321fd21e
L		 2426 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2427 there is no suffix, the default will be byte extension. */
2428 if (i.reg_operands != 2
2429 && !i.suffix
2430 && intel_syntax)
2431 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2432
2433 i.suffix = 0;
cd61ebfe 2434 }
24eab124 2435
40fb9820 2436 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2437 if (!add_prefix (FWAIT_OPCODE))
2438 return;
252b5132 2439
29b0f896 2440 /* Check string instruction segment overrides. */
40fb9820 2441 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2442 {
2443 if (!check_string ())
5dd0794d 2444 return;
29b0f896 2445 }
5dd0794d 2446
29b0f896
AM		 2447 if (!process_suffix ())
2448 return;
e413e4e9 2449
29b0f896
AM		 2450 /* Make still unresolved immediate matches conform to size of immediate
2451 given in i.suffix. */
2452 if (!finalize_imm ())
2453 return;
252b5132 2454
40fb9820 2455 if (i.types[0].bitfield.imm1)
29b0f896 2456 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2457
40fb9820 2458 for (j = 0; j < 3; j++)
c6fb90c8
L		 2459 if (i.types[j].bitfield.inoutportreg
2460 || i.types[j].bitfield.shiftcount
2461 || i.types[j].bitfield.acc
2462 || i.types[j].bitfield.floatacc)
40fb9820
L		 2463 i.reg_operands--;
2464
2465 if (i.tm.opcode_modifier.immext)
29b0f896 2466 {
02fc3089
L		 2467 expressionS *exp;
2468
40fb9820 2469 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
ca164297 2470 {
b7d9ef37 2471 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 2472 operands with an opcode suffix which is coded in the same
2473 place as an 8-bit immediate field would be. Here we check
2474 those operands and remove them afterwards. */
2475 unsigned int x;
2476
a4622f40 2477 for (x = 0; x < i.operands; x++)
ca164297 2478 if (i.op[x].regs->reg_num != x)
a540244d
L		 2479 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2480 register_prefix,
2481 i.op[x].regs->reg_name,
2482 x + 1,
2483 i.tm.name);
ca164297
L		 2484 i.operands = 0;
2485 }
2486
29b0f896
AM		 2487 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2488 opcode suffix which is coded in the same place as an 8-bit
2489 immediate field would be. Here we fake an 8-bit immediate
85f10a01
MM		 2490 operand from the opcode suffix stored in tm.extension_opcode.
2491 SSE5 also uses this encoding, for some of its 3 argument
2492 instructions. */
252b5132 2493
85f10a01
MM		 2494 assert (i.imm_operands == 0
2495 && (i.operands <= 2
2496 || (i.tm.cpu_flags.bitfield.cpusse5
2497 && i.operands <= 3)));
252b5132 2498
29b0f896
AM		 2499 exp = &im_expressions[i.imm_operands++];
2500 i.op[i.operands].imms = exp;
c6fb90c8 2501 UINTS_CLEAR (i.types[i.operands]);
40fb9820
L		 2502 i.types[i.operands].bitfield.imm8 = 1;
2503 i.operands++;
29b0f896
AM		 2504 exp->X_op = O_constant;
2505 exp->X_add_number = i.tm.extension_opcode;
2506 i.tm.extension_opcode = None;
2507 }
252b5132 2508
29b0f896
AM		 2509 /* For insns with operands there are more diddles to do to the opcode. */
2510 if (i.operands)
2511 {
2512 if (!process_operands ())
2513 return;
2514 }
40fb9820 2515 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2516 {
2517 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2518 as_warn (_("translating to `%sp'"), i.tm.name);
2519 }
252b5132 2520
29b0f896
AM		 2521 /* Handle conversion of 'int $3' --> special int3 insn. */
2522 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2523 {
2524 i.tm.base_opcode = INT3_OPCODE;
2525 i.imm_operands = 0;
2526 }
252b5132 2527
40fb9820
L		 2528 if ((i.tm.opcode_modifier.jump
2529 || i.tm.opcode_modifier.jumpbyte
2530 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2531 && i.op[0].disps->X_op == O_constant)
2532 {
2533 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2534 the absolute address given by the constant. Since ix86 jumps and
2535 calls are pc relative, we need to generate a reloc. */
2536 i.op[0].disps->X_add_symbol = &abs_symbol;
2537 i.op[0].disps->X_op = O_symbol;
2538 }
252b5132 2539
40fb9820 2540 if (i.tm.opcode_modifier.rex64)
161a04f6 2541 i.rex |= REX_W;
252b5132 2542
29b0f896
AM		 2543 /* For 8 bit registers we need an empty rex prefix. Also if the
2544 instruction already has a prefix, we need to convert old
2545 registers to new ones. */
773f551c 2546
40fb9820 2547 if ((i.types[0].bitfield.reg8
29b0f896 2548 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2549 || (i.types[1].bitfield.reg8
29b0f896 2550 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2551 || ((i.types[0].bitfield.reg8
2552 || i.types[1].bitfield.reg8)
29b0f896
AM		 2553 && i.rex != 0))
2554 {
2555 int x;
726c5dcd 2556
29b0f896
AM		 2557 i.rex |= REX_OPCODE;
2558 for (x = 0; x < 2; x++)
2559 {
2560 /* Look for 8 bit operand that uses old registers. */
40fb9820 2561 if (i.types[x].bitfield.reg8
29b0f896 2562 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2563 {
29b0f896
AM		 2564 /* In case it is "hi" register, give up. */
2565 if (i.op[x].regs->reg_num > 3)
a540244d 2566 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2567 "instruction requiring REX prefix."),
a540244d 2568 register_prefix, i.op[x].regs->reg_name);
773f551c 2569
29b0f896
AM		 2570 /* Otherwise it is equivalent to the extended register.
2571 Since the encoding doesn't change this is merely
2572 cosmetic cleanup for debug output. */
2573
2574 i.op[x].regs = i.op[x].regs + 8;
773f551c 2575 }
29b0f896
AM		 2576 }
2577 }
773f551c 2578
85f10a01
MM		 2579 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2580 REX prefix. */
2581 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2582 {
2583 i.drex.rex = i.rex;
2584 i.rex = 0;
2585 }
2586 else if (i.rex != 0)
29b0f896
AM		 2587 add_prefix (REX_OPCODE | i.rex);
2588
2589 /* We are ready to output the insn. */
2590 output_insn ();
2591}
2592
2593static char *
e3bb37b5 2594parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2595{
2596 char *l = line;
2597 char *token_start = l;
2598 char *mnem_p;
5c6af06e
JB		 2599 int supported;
2600 const template *t;
29b0f896
AM		 2601
2602 /* Non-zero if we found a prefix only acceptable with string insns. */
2603 const char *expecting_string_instruction = NULL;
45288df1 2604
29b0f896
AM		 2605 while (1)
2606 {
2607 mnem_p = mnemonic;
2608 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2609 {
2610 mnem_p++;
2611 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2612 {
29b0f896
AM		 2613 as_bad (_("no such instruction: `%s'"), token_start);
2614 return NULL;
2615 }
2616 l++;
2617 }
2618 if (!is_space_char (*l)
2619 && *l != END_OF_INSN
e44823cf
JB		 2620 && (intel_syntax
2621 || (*l != PREFIX_SEPARATOR
2622 && *l != ',')))
29b0f896
AM		 2623 {
2624 as_bad (_("invalid character %s in mnemonic"),
2625 output_invalid (*l));
2626 return NULL;
2627 }
2628 if (token_start == l)
2629 {
e44823cf 2630 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2631 as_bad (_("expecting prefix; got nothing"));
2632 else
2633 as_bad (_("expecting mnemonic; got nothing"));
2634 return NULL;
2635 }
45288df1 2636
29b0f896
AM		 2637 /* Look up instruction (or prefix) via hash table. */
2638 current_templates = hash_find (op_hash, mnemonic);
47926f60 2639
29b0f896
AM		 2640 if (*l != END_OF_INSN
2641 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2642 && current_templates
40fb9820 2643 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2644 {
c6fb90c8 2645 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2646 {
2647 as_bad ((flag_code != CODE_64BIT
2648 ? _("`%s' is only supported in 64-bit mode")
2649 : _("`%s' is not supported in 64-bit mode")),
2650 current_templates->start->name);
2651 return NULL;
2652 }
29b0f896
AM		 2653 /* If we are in 16-bit mode, do not allow addr16 or data16.
2654 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2655 if ((current_templates->start->opcode_modifier.size16
2656 || current_templates->start->opcode_modifier.size32)
29b0f896 2657 && flag_code != CODE_64BIT
40fb9820 2658 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2659 ^ (flag_code == CODE_16BIT)))
2660 {
2661 as_bad (_("redundant %s prefix"),
2662 current_templates->start->name);
2663 return NULL;
45288df1 2664 }
29b0f896
AM		 2665 /* Add prefix, checking for repeated prefixes. */
2666 switch (add_prefix (current_templates->start->base_opcode))
2667 {
2668 case 0:
2669 return NULL;
2670 case 2:
2671 expecting_string_instruction = current_templates->start->name;
2672 break;
2673 }
2674 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2675 token_start = ++l;
2676 }
2677 else
2678 break;
2679 }
45288df1 2680
29b0f896
AM		 2681 if (!current_templates)
2682 {
2683 /* See if we can get a match by trimming off a suffix. */
2684 switch (mnem_p[-1])
2685 {
2686 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2687 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2688 i.suffix = SHORT_MNEM_SUFFIX;
2689 else
29b0f896
AM		 2690 case BYTE_MNEM_SUFFIX:
2691 case QWORD_MNEM_SUFFIX:
2692 i.suffix = mnem_p[-1];
2693 mnem_p[-1] = '\0';
2694 current_templates = hash_find (op_hash, mnemonic);
2695 break;
2696 case SHORT_MNEM_SUFFIX:
2697 case LONG_MNEM_SUFFIX:
2698 if (!intel_syntax)
2699 {
2700 i.suffix = mnem_p[-1];
2701 mnem_p[-1] = '\0';
2702 current_templates = hash_find (op_hash, mnemonic);
2703 }
2704 break;
252b5132 2705
29b0f896
AM		 2706 /* Intel Syntax. */
2707 case 'd':
2708 if (intel_syntax)
2709 {
9306ca4a 2710 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2711 i.suffix = SHORT_MNEM_SUFFIX;
2712 else
2713 i.suffix = LONG_MNEM_SUFFIX;
2714 mnem_p[-1] = '\0';
2715 current_templates = hash_find (op_hash, mnemonic);
2716 }
2717 break;
2718 }
2719 if (!current_templates)
2720 {
2721 as_bad (_("no such instruction: `%s'"), token_start);
2722 return NULL;
2723 }
2724 }
252b5132 2725
40fb9820
L		 2726 if (current_templates->start->opcode_modifier.jump
2727 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 2728 {
2729 /* Check for a branch hint. We allow ",pt" and ",pn" for
2730 predict taken and predict not taken respectively.
2731 I'm not sure that branch hints actually do anything on loop
2732 and jcxz insns (JumpByte) for current Pentium4 chips. They
2733 may work in the future and it doesn't hurt to accept them
2734 now. */
2735 if (l[0] == ',' && l[1] == 'p')
2736 {
2737 if (l[2] == 't')
2738 {
2739 if (!add_prefix (DS_PREFIX_OPCODE))
2740 return NULL;
2741 l += 3;
2742 }
2743 else if (l[2] == 'n')
2744 {
2745 if (!add_prefix (CS_PREFIX_OPCODE))
2746 return NULL;
2747 l += 3;
2748 }
2749 }
2750 }
2751 /* Any other comma loses. */
2752 if (*l == ',')
2753 {
2754 as_bad (_("invalid character %s in mnemonic"),
2755 output_invalid (*l));
2756 return NULL;
2757 }
252b5132 2758
29b0f896 2759 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2760 supported = 0;
2761 for (t = current_templates->start; t < current_templates->end; ++t)
2762 {
3629bb00
L		 2763 supported |= cpu_flags_match (t->cpu_flags);
2764 if (supported == 3)
2765 goto skip;
5c6af06e 2766 }
3629bb00 2767
5c6af06e
JB		 2768 if (!(supported & 2))
2769 {
2770 as_bad (flag_code == CODE_64BIT
2771 ? _("`%s' is not supported in 64-bit mode")
2772 : _("`%s' is only supported in 64-bit mode"),
2773 current_templates->start->name);
2774 return NULL;
2775 }
2776 if (!(supported & 1))
29b0f896 2777 {
3629bb00
L		 2778 as_bad (_("`%s' is not supported on `%s%s'"),
2779 current_templates->start->name, cpu_arch_name,
2780 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2781 return NULL;
29b0f896 2782 }
3629bb00
L		 2783
2784skip:
2785 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 2786 && (flag_code != CODE_16BIT))
29b0f896
AM		 2787 {
2788 as_warn (_("use .code16 to ensure correct addressing mode"));
2789 }
252b5132 2790
29b0f896 2791 /* Check for rep/repne without a string instruction. */
f41bbced 2792 if (expecting_string_instruction)
29b0f896 2793 {
f41bbced
JB		 2794 static templates override;
2795
2796 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 2797 if (t->opcode_modifier.isstring)
f41bbced
JB		 2798 break;
2799 if (t >= current_templates->end)
2800 {
2801 as_bad (_("expecting string instruction after `%s'"),
64e74474 2802 expecting_string_instruction);
f41bbced
JB		 2803 return NULL;
2804 }
2805 for (override.start = t; t < current_templates->end; ++t)
40fb9820 2806 if (!t->opcode_modifier.isstring)
f41bbced
JB		 2807 break;
2808 override.end = t;
2809 current_templates = &override;
29b0f896 2810 }
252b5132 2811
29b0f896
AM		 2812 return l;
2813}
252b5132 2814
29b0f896 2815static char *
e3bb37b5 2816parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2817{
2818 char *token_start;
3138f287 2819
29b0f896
AM		 2820 /* 1 if operand is pending after ','. */
2821 unsigned int expecting_operand = 0;
252b5132 2822
29b0f896
AM		 2823 /* Non-zero if operand parens not balanced. */
2824 unsigned int paren_not_balanced;
2825
2826 while (*l != END_OF_INSN)
2827 {
2828 /* Skip optional white space before operand. */
2829 if (is_space_char (*l))
2830 ++l;
2831 if (!is_operand_char (*l) && *l != END_OF_INSN)
2832 {
2833 as_bad (_("invalid character %s before operand %d"),
2834 output_invalid (*l),
2835 i.operands + 1);
2836 return NULL;
2837 }
2838 token_start = l; /* after white space */
2839 paren_not_balanced = 0;
2840 while (paren_not_balanced || *l != ',')
2841 {
2842 if (*l == END_OF_INSN)
2843 {
2844 if (paren_not_balanced)
2845 {
2846 if (!intel_syntax)
2847 as_bad (_("unbalanced parenthesis in operand %d."),
2848 i.operands + 1);
2849 else
2850 as_bad (_("unbalanced brackets in operand %d."),
2851 i.operands + 1);
2852 return NULL;
2853 }
2854 else
2855 break; /* we are done */
2856 }
2857 else if (!is_operand_char (*l) && !is_space_char (*l))
2858 {
2859 as_bad (_("invalid character %s in operand %d"),
2860 output_invalid (*l),
2861 i.operands + 1);
2862 return NULL;
2863 }
2864 if (!intel_syntax)
2865 {
2866 if (*l == '(')
2867 ++paren_not_balanced;
2868 if (*l == ')')
2869 --paren_not_balanced;
2870 }
2871 else
2872 {
2873 if (*l == '[')
2874 ++paren_not_balanced;
2875 if (*l == ']')
2876 --paren_not_balanced;
2877 }
2878 l++;
2879 }
2880 if (l != token_start)
2881 { /* Yes, we've read in another operand. */
2882 unsigned int operand_ok;
2883 this_operand = i.operands++;
7d5e4556 2884 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 2885 if (i.operands > MAX_OPERANDS)
2886 {
2887 as_bad (_("spurious operands; (%d operands/instruction max)"),
2888 MAX_OPERANDS);
2889 return NULL;
2890 }
2891 /* Now parse operand adding info to 'i' as we go along. */
2892 END_STRING_AND_SAVE (l);
2893
2894 if (intel_syntax)
2895 operand_ok =
2896 i386_intel_operand (token_start,
2897 intel_float_operand (mnemonic));
2898 else
a7619375 2899 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 2900
2901 RESTORE_END_STRING (l);
2902 if (!operand_ok)
2903 return NULL;
2904 }
2905 else
2906 {
2907 if (expecting_operand)
2908 {
2909 expecting_operand_after_comma:
2910 as_bad (_("expecting operand after ','; got nothing"));
2911 return NULL;
2912 }
2913 if (*l == ',')
2914 {
2915 as_bad (_("expecting operand before ','; got nothing"));
2916 return NULL;
2917 }
2918 }
7f3f1ea2 2919
29b0f896
AM		 2920 /* Now *l must be either ',' or END_OF_INSN. */
2921 if (*l == ',')
2922 {
2923 if (*++l == END_OF_INSN)
2924 {
2925 /* Just skip it, if it's \n complain. */
2926 goto expecting_operand_after_comma;
2927 }
2928 expecting_operand = 1;
2929 }
2930 }
2931 return l;
2932}
7f3f1ea2 2933
050dfa73 2934static void
4d456e3d 2935swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2936{
2937 union i386_op temp_op;
40fb9820 2938 i386_operand_type temp_type;
050dfa73 2939 enum bfd_reloc_code_real temp_reloc;
4eed87de 2940
050dfa73
MM		 2941 temp_type = i.types[xchg2];
2942 i.types[xchg2] = i.types[xchg1];
2943 i.types[xchg1] = temp_type;
2944 temp_op = i.op[xchg2];
2945 i.op[xchg2] = i.op[xchg1];
2946 i.op[xchg1] = temp_op;
2947 temp_reloc = i.reloc[xchg2];
2948 i.reloc[xchg2] = i.reloc[xchg1];
2949 i.reloc[xchg1] = temp_reloc;
2950}
2951
29b0f896 2952static void
e3bb37b5 2953swap_operands (void)
29b0f896 2954{
b7c61d9a 2955 switch (i.operands)
050dfa73 2956 {
b7c61d9a 2957 case 4:
4d456e3d 2958 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2959 case 3:
2960 case 2:
4d456e3d 2961 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2962 break;
2963 default:
2964 abort ();
29b0f896 2965 }
29b0f896
AM		 2966
2967 if (i.mem_operands == 2)
2968 {
2969 const seg_entry *temp_seg;
2970 temp_seg = i.seg[0];
2971 i.seg[0] = i.seg[1];
2972 i.seg[1] = temp_seg;
2973 }
2974}
252b5132 2975
29b0f896
AM		 2976/* Try to ensure constant immediates are represented in the smallest
2977 opcode possible. */
2978static void
e3bb37b5 2979optimize_imm (void)
29b0f896
AM		 2980{
2981 char guess_suffix = 0;
2982 int op;
252b5132 2983
29b0f896
AM		 2984 if (i.suffix)
2985 guess_suffix = i.suffix;
2986 else if (i.reg_operands)
2987 {
2988 /* Figure out a suffix from the last register operand specified.
2989 We can't do this properly yet, ie. excluding InOutPortReg,
2990 but the following works for instructions with immediates.
2991 In any case, we can't set i.suffix yet. */
2992 for (op = i.operands; --op >= 0;)
40fb9820
L		 2993 if (i.types[op].bitfield.reg8)
2994 {
2995 guess_suffix = BYTE_MNEM_SUFFIX;
2996 break;
2997 }
2998 else if (i.types[op].bitfield.reg16)
252b5132 2999 {
40fb9820
L		 3000 guess_suffix = WORD_MNEM_SUFFIX;
3001 break;
3002 }
3003 else if (i.types[op].bitfield.reg32)
3004 {
3005 guess_suffix = LONG_MNEM_SUFFIX;
3006 break;
3007 }
3008 else if (i.types[op].bitfield.reg64)
3009 {
3010 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3011 break;
252b5132 3012 }
29b0f896
AM		 3013 }
3014 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3015 guess_suffix = WORD_MNEM_SUFFIX;
3016
3017 for (op = i.operands; --op >= 0;)
40fb9820 3018 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3019 {
3020 switch (i.op[op].imms->X_op)
252b5132 3021 {
29b0f896
AM		 3022 case O_constant:
3023 /* If a suffix is given, this operand may be shortened. */
3024 switch (guess_suffix)
252b5132 3025 {
29b0f896 3026 case LONG_MNEM_SUFFIX:
40fb9820
L		 3027 i.types[op].bitfield.imm32 = 1;
3028 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3029 break;
3030 case WORD_MNEM_SUFFIX:
40fb9820
L		 3031 i.types[op].bitfield.imm16 = 1;
3032 i.types[op].bitfield.imm32 = 1;
3033 i.types[op].bitfield.imm32s = 1;
3034 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3035 break;
3036 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3037 i.types[op].bitfield.imm8 = 1;
3038 i.types[op].bitfield.imm8s = 1;
3039 i.types[op].bitfield.imm16 = 1;
3040 i.types[op].bitfield.imm32 = 1;
3041 i.types[op].bitfield.imm32s = 1;
3042 i.types[op].bitfield.imm64 = 1;
29b0f896 3043 break;
252b5132 3044 }
252b5132 3045
29b0f896
AM		 3046 /* If this operand is at most 16 bits, convert it
3047 to a signed 16 bit number before trying to see
3048 whether it will fit in an even smaller size.
3049 This allows a 16-bit operand such as $0xffe0 to
3050 be recognised as within Imm8S range. */
40fb9820 3051 if ((i.types[op].bitfield.imm16)
29b0f896 3052 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3053 {
29b0f896
AM		 3054 i.op[op].imms->X_add_number =
3055 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3056 }
40fb9820 3057 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3058 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3059 == 0))
3060 {
3061 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3062 ^ ((offsetT) 1 << 31))
3063 - ((offsetT) 1 << 31));
3064 }
40fb9820 3065 i.types[op]
c6fb90c8
L		 3066 = operand_type_or (i.types[op],
3067 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3068
29b0f896
AM		 3069 /* We must avoid matching of Imm32 templates when 64bit
3070 only immediate is available. */
3071 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3072 i.types[op].bitfield.imm32 = 0;
29b0f896 3073 break;
252b5132 3074
29b0f896
AM		 3075 case O_absent:
3076 case O_register:
3077 abort ();
3078
3079 /* Symbols and expressions. */
3080 default:
9cd96992
JB		 3081 /* Convert symbolic operand to proper sizes for matching, but don't
3082 prevent matching a set of insns that only supports sizes other
3083 than those matching the insn suffix. */
3084 {
40fb9820 3085 i386_operand_type mask, allowed;
9cd96992
JB		 3086 const template *t;
3087
c6fb90c8
L		 3088 UINTS_CLEAR (mask);
3089 UINTS_CLEAR (allowed);
40fb9820 3090
4eed87de
AM		 3091 for (t = current_templates->start;
3092 t < current_templates->end;
3093 ++t)
c6fb90c8
L		 3094 allowed = operand_type_or (allowed,
3095 t->operand_types[op]);
9cd96992
JB		 3096 switch (guess_suffix)
3097 {
3098 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3099 mask.bitfield.imm64 = 1;
3100 mask.bitfield.imm32s = 1;
9cd96992
JB		 3101 break;
3102 case LONG_MNEM_SUFFIX:
40fb9820 3103 mask.bitfield.imm32 = 1;
9cd96992
JB		 3104 break;
3105 case WORD_MNEM_SUFFIX:
40fb9820 3106 mask.bitfield.imm16 = 1;
9cd96992
JB		 3107 break;
3108 case BYTE_MNEM_SUFFIX:
40fb9820 3109 mask.bitfield.imm8 = 1;
9cd96992
JB		 3110 break;
3111 default:
9cd96992
JB		 3112 break;
3113 }
c6fb90c8
L		 3114 allowed = operand_type_and (mask, allowed);
3115 if (!UINTS_ALL_ZERO (allowed))
3116 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3117 }
29b0f896 3118 break;
252b5132 3119 }
29b0f896
AM		 3120 }
3121}
47926f60 3122
29b0f896
AM		 3123/* Try to use the smallest displacement type too. */
3124static void
e3bb37b5 3125optimize_disp (void)
29b0f896
AM		 3126{
3127 int op;
3e73aa7c 3128
29b0f896 3129 for (op = i.operands; --op >= 0;)
40fb9820 3130 if (operand_type_check (i.types[op], disp))
252b5132 3131 {
b300c311 3132 if (i.op[op].disps->X_op == O_constant)
252b5132 3133 {
b300c311 3134 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3135
40fb9820 3136 if (i.types[op].bitfield.disp16
b300c311
L		 3137 && (disp & ~(offsetT) 0xffff) == 0)
3138 {
3139 /* If this operand is at most 16 bits, convert
3140 to a signed 16 bit number and don't use 64bit
3141 displacement. */
3142 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3143 i.types[op].bitfield.disp64 = 0;
b300c311 3144 }
40fb9820 3145 if (i.types[op].bitfield.disp32
b300c311
L		 3146 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3147 {
3148 /* If this operand is at most 32 bits, convert
3149 to a signed 32 bit number and don't use 64bit
3150 displacement. */
3151 disp &= (((offsetT) 2 << 31) - 1);
3152 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3153 i.types[op].bitfield.disp64 = 0;
b300c311 3154 }
40fb9820 3155 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3156 {
40fb9820
L		 3157 i.types[op].bitfield.disp8 = 0;
3158 i.types[op].bitfield.disp16 = 0;
3159 i.types[op].bitfield.disp32 = 0;
3160 i.types[op].bitfield.disp32s = 0;
3161 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3162 i.op[op].disps = 0;
3163 i.disp_operands--;
3164 }
3165 else if (flag_code == CODE_64BIT)
3166 {
3167 if (fits_in_signed_long (disp))
28a9d8f5 3168 {
40fb9820
L		 3169 i.types[op].bitfield.disp64 = 0;
3170 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3171 }
b300c311 3172 if (fits_in_unsigned_long (disp))
40fb9820 3173 i.types[op].bitfield.disp32 = 1;
b300c311 3174 }
40fb9820
L		 3175 if ((i.types[op].bitfield.disp32
3176 || i.types[op].bitfield.disp32s
3177 || i.types[op].bitfield.disp16)
b300c311 3178 && fits_in_signed_byte (disp))
40fb9820 3179 i.types[op].bitfield.disp8 = 1;
252b5132 3180 }
67a4f2b7
AO		 3181 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3182 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3183 {
3184 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3185 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3186 i.types[op].bitfield.disp8 = 0;
3187 i.types[op].bitfield.disp16 = 0;
3188 i.types[op].bitfield.disp32 = 0;
3189 i.types[op].bitfield.disp32s = 0;
3190 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3191 }
3192 else
b300c311 3193 /* We only support 64bit displacement on constants. */
40fb9820 3194 i.types[op].bitfield.disp64 = 0;
252b5132 3195 }
29b0f896
AM		 3196}
3197
3198static int
e3bb37b5 3199match_template (void)
29b0f896
AM		 3200{
3201 /* Points to template once we've found it. */
3202 const template *t;
40fb9820 3203 i386_operand_type overlap0, overlap1, overlap2, overlap3;
29b0f896 3204 unsigned int found_reverse_match;
40fb9820
L		 3205 i386_opcode_modifier suffix_check;
3206 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3207 int addr_prefix_disp;
a5c311ca 3208 unsigned int j;
3629bb00 3209 unsigned int found_cpu_match;
45664ddb 3210 unsigned int check_register;
29b0f896 3211
f48ff2ae
L		 3212#if MAX_OPERANDS != 4
3213# error "MAX_OPERANDS must be 4."
3214#endif
3215
29b0f896 3216 found_reverse_match = 0;
539e75ad 3217 addr_prefix_disp = -1;
40fb9820
L		 3218
3219 memset (&suffix_check, 0, sizeof (suffix_check));
3220 if (i.suffix == BYTE_MNEM_SUFFIX)
3221 suffix_check.no_bsuf = 1;
3222 else if (i.suffix == WORD_MNEM_SUFFIX)
3223 suffix_check.no_wsuf = 1;
3224 else if (i.suffix == SHORT_MNEM_SUFFIX)
3225 suffix_check.no_ssuf = 1;
3226 else if (i.suffix == LONG_MNEM_SUFFIX)
3227 suffix_check.no_lsuf = 1;
3228 else if (i.suffix == QWORD_MNEM_SUFFIX)
3229 suffix_check.no_qsuf = 1;
3230 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3231 suffix_check.no_ldsuf = 1;
29b0f896 3232
45aa61fe 3233 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3234 {
539e75ad
L		 3235 addr_prefix_disp = -1;
3236
29b0f896
AM		 3237 /* Must have right number of operands. */
3238 if (i.operands != t->operands)
3239 continue;
3240
50aecf8c
L		 3241 /* Check processor support. */
3242 found_cpu_match = cpu_flags_match (t->cpu_flags) == 3;
3243 if (!found_cpu_match)
3244 continue;
3245
e1d4d893
L		 3246 /* Check old gcc support. */
3247 if (!old_gcc && t->opcode_modifier.oldgcc)
3248 continue;
3249
3250 /* Check AT&T mnemonic. */
3251 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3252 continue;
3253
5c07affc
L		 3254 /* Check AT&T syntax Intel syntax. */
3255 if ((intel_syntax && t->opcode_modifier.attsyntax)
3256 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3257 continue;
3258
20592a94 3259 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3260 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3261 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3262 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3263 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3264 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3265 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3266 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3267 continue;
3268
5c07affc 3269 if (!operand_size_match (t))
7d5e4556 3270 continue;
539e75ad 3271
5c07affc
L		 3272 for (j = 0; j < MAX_OPERANDS; j++)
3273 operand_types[j] = t->operand_types[j];
3274
45aa61fe
AM		 3275 /* In general, don't allow 64-bit operands in 32-bit mode. */
3276 if (i.suffix == QWORD_MNEM_SUFFIX
3277 && flag_code != CODE_64BIT
3278 && (intel_syntax
40fb9820 3279 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3280 && !intel_float_operand (t->name))
3281 : intel_float_operand (t->name) != 2)
40fb9820
L		 3282 && ((!operand_types[0].bitfield.regmmx
3283 && !operand_types[0].bitfield.regxmm)
3284 || (!operand_types[t->operands > 1].bitfield.regmmx
3285 && !!operand_types[t->operands > 1].bitfield.regxmm))
45aa61fe
AM		 3286 && (t->base_opcode != 0x0fc7
3287 || t->extension_opcode != 1 /* cmpxchg8b */))
3288 continue;
3289
29b0f896 3290 /* Do not verify operands when there are none. */
50aecf8c 3291 else
29b0f896 3292 {
c6fb90c8 3293 if (!t->operands)
2dbab7d5
L		 3294 /* We've found a match; break out of loop. */
3295 break;
29b0f896 3296 }
252b5132 3297
539e75ad
L		 3298 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3299 into Disp32/Disp16/Disp32 operand. */
3300 if (i.prefix[ADDR_PREFIX] != 0)
3301 {
40fb9820 3302 /* There should be only one Disp operand. */
539e75ad
L		 3303 switch (flag_code)
3304 {
3305 case CODE_16BIT:
40fb9820
L		 3306 for (j = 0; j < MAX_OPERANDS; j++)
3307 {
3308 if (operand_types[j].bitfield.disp16)
3309 {
3310 addr_prefix_disp = j;
3311 operand_types[j].bitfield.disp32 = 1;
3312 operand_types[j].bitfield.disp16 = 0;
3313 break;
3314 }
3315 }
539e75ad
L		 3316 break;
3317 case CODE_32BIT:
40fb9820
L		 3318 for (j = 0; j < MAX_OPERANDS; j++)
3319 {
3320 if (operand_types[j].bitfield.disp32)
3321 {
3322 addr_prefix_disp = j;
3323 operand_types[j].bitfield.disp32 = 0;
3324 operand_types[j].bitfield.disp16 = 1;
3325 break;
3326 }
3327 }
539e75ad
L		 3328 break;
3329 case CODE_64BIT:
40fb9820
L		 3330 for (j = 0; j < MAX_OPERANDS; j++)
3331 {
3332 if (operand_types[j].bitfield.disp64)
3333 {
3334 addr_prefix_disp = j;
3335 operand_types[j].bitfield.disp64 = 0;
3336 operand_types[j].bitfield.disp32 = 1;
3337 break;
3338 }
3339 }
539e75ad
L		 3340 break;
3341 }
539e75ad
L		 3342 }
3343
45664ddb
L		 3344 /* We check register size only if size of operands can be
3345 encoded the canonical way. */
3346 check_register = t->opcode_modifier.w;
c6fb90c8 3347 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3348 switch (t->operands)
3349 {
3350 case 1:
40fb9820 3351 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3352 continue;
3353 break;
3354 case 2:
8b38ad71
L		 3355 /* xchg %eax, %eax is a special case. It is an aliase for nop
3356 only in 32bit mode and we can use opcode 0x90. In 64bit
3357 mode, we can't use 0x90 for xchg %eax, %eax since it should
3358 zero-extend %eax to %rax. */
3359 if (flag_code == CODE_64BIT
3360 && t->base_opcode == 0x90
c6fb90c8
L		 3361 && UINTS_EQUAL (i.types [0], acc32)
3362 && UINTS_EQUAL (i.types [1], acc32))
8b38ad71 3363 continue;
29b0f896 3364 case 3:
f48ff2ae 3365 case 4:
c6fb90c8 3366 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3367 if (!operand_type_match (overlap0, i.types[0])
3368 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3369 || (check_register
3370 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3371 operand_types[0],
3372 overlap1, i.types[1],
3373 operand_types[1])))
29b0f896
AM		 3374 {
3375 /* Check if other direction is valid ... */
40fb9820 3376 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3377 continue;
3378
3379 /* Try reversing direction of operands. */
c6fb90c8
L		 3380 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3381 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3382 if (!operand_type_match (overlap0, i.types[0])
3383 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3384 || (check_register
3385 && !operand_type_register_match (overlap0,
3386 i.types[0],
3387 operand_types[1],
3388 overlap1,
3389 i.types[1],
3390 operand_types[0])))
29b0f896
AM		 3391 {
3392 /* Does not match either direction. */
3393 continue;
3394 }
3395 /* found_reverse_match holds which of D or FloatDR
3396 we've found. */
40fb9820 3397 if (t->opcode_modifier.d)
8a2ed489 3398 found_reverse_match = Opcode_D;
40fb9820 3399 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3400 found_reverse_match = Opcode_FloatD;
3401 else
3402 found_reverse_match = 0;
40fb9820 3403 if (t->opcode_modifier.floatr)
8a2ed489 3404 found_reverse_match |= Opcode_FloatR;
29b0f896 3405 }
f48ff2ae 3406 else
29b0f896 3407 {
f48ff2ae 3408 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3409 switch (t->operands)
3410 {
3411 case 4:
c6fb90c8
L		 3412 overlap3 = operand_type_and (i.types[3],
3413 operand_types[3]);
d1cbb4db 3414 case 3:
c6fb90c8
L		 3415 overlap2 = operand_type_and (i.types[2],
3416 operand_types[2]);
d1cbb4db
L		 3417 break;
3418 }
29b0f896 3419
f48ff2ae
L		 3420 switch (t->operands)
3421 {
3422 case 4:
40fb9820 3423 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3424 || (check_register
3425 && !operand_type_register_match (overlap2,
3426 i.types[2],
3427 operand_types[2],
3428 overlap3,
3429 i.types[3],
3430 operand_types[3])))
f48ff2ae
L		 3431 continue;
3432 case 3:
3433 /* Here we make use of the fact that there are no
3434 reverse match 3 operand instructions, and all 3
3435 operand instructions only need to be checked for
3436 register consistency between operands 2 and 3. */
40fb9820 3437 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3438 || (check_register
3439 && !operand_type_register_match (overlap1,
3440 i.types[1],
3441 operand_types[1],
3442 overlap2,
3443 i.types[2],
3444 operand_types[2])))
f48ff2ae
L		 3445 continue;
3446 break;
3447 }
29b0f896 3448 }
f48ff2ae 3449 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3450 slip through to break. */
3451 }
3629bb00 3452 if (!found_cpu_match)
29b0f896
AM		 3453 {
3454 found_reverse_match = 0;
3455 continue;
3456 }
3457 /* We've found a match; break out of loop. */
3458 break;
3459 }
3460
3461 if (t == current_templates->end)
3462 {
3463 /* We found no match. */
3464 as_bad (_("suffix or operands invalid for `%s'"),
3465 current_templates->start->name);
3466 return 0;
3467 }
252b5132 3468
29b0f896
AM		 3469 if (!quiet_warnings)
3470 {
3471 if (!intel_syntax
40fb9820
L		 3472 && (i.types[0].bitfield.jumpabsolute
3473 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3474 {
3475 as_warn (_("indirect %s without `*'"), t->name);
3476 }
3477
40fb9820
L		 3478 if (t->opcode_modifier.isprefix
3479 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3480 {
3481 /* Warn them that a data or address size prefix doesn't
3482 affect assembly of the next line of code. */
3483 as_warn (_("stand-alone `%s' prefix"), t->name);
3484 }
3485 }
3486
3487 /* Copy the template we found. */
3488 i.tm = *t;
539e75ad
L		 3489
3490 if (addr_prefix_disp != -1)
3491 i.tm.operand_types[addr_prefix_disp]
3492 = operand_types[addr_prefix_disp];
3493
29b0f896
AM		 3494 if (found_reverse_match)
3495 {
3496 /* If we found a reverse match we must alter the opcode
3497 direction bit. found_reverse_match holds bits to change
3498 (different for int & float insns). */
3499
3500 i.tm.base_opcode ^= found_reverse_match;
3501
539e75ad
L		 3502 i.tm.operand_types[0] = operand_types[1];
3503 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3504 }
3505
3506 return 1;
3507}
3508
3509static int
e3bb37b5 3510check_string (void)
29b0f896 3511{
40fb9820
L		 3512 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3513 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3514 {
3515 if (i.seg[0] != NULL && i.seg[0] != &es)
3516 {
3517 as_bad (_("`%s' operand %d must use `%%es' segment"),
3518 i.tm.name,
3519 mem_op + 1);
3520 return 0;
3521 }
3522 /* There's only ever one segment override allowed per instruction.
3523 This instruction possibly has a legal segment override on the
3524 second operand, so copy the segment to where non-string
3525 instructions store it, allowing common code. */
3526 i.seg[0] = i.seg[1];
3527 }
40fb9820 3528 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3529 {
3530 if (i.seg[1] != NULL && i.seg[1] != &es)
3531 {
3532 as_bad (_("`%s' operand %d must use `%%es' segment"),
3533 i.tm.name,
3534 mem_op + 2);
3535 return 0;
3536 }
3537 }
3538 return 1;
3539}
3540
3541static int
543613e9 3542process_suffix (void)
29b0f896
AM		 3543{
3544 /* If matched instruction specifies an explicit instruction mnemonic
3545 suffix, use it. */
40fb9820
L		 3546 if (i.tm.opcode_modifier.size16)
3547 i.suffix = WORD_MNEM_SUFFIX;
3548 else if (i.tm.opcode_modifier.size32)
3549 i.suffix = LONG_MNEM_SUFFIX;
3550 else if (i.tm.opcode_modifier.size64)
3551 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3552 else if (i.reg_operands)
3553 {
3554 /* If there's no instruction mnemonic suffix we try to invent one
3555 based on register operands. */
3556 if (!i.suffix)
3557 {
3558 /* We take i.suffix from the last register operand specified,
3559 Destination register type is more significant than source
381d071f
L		 3560 register type. crc32 in SSE4.2 prefers source register
3561 type. */
3562 if (i.tm.base_opcode == 0xf20f38f1)
3563 {
40fb9820
L		 3564 if (i.types[0].bitfield.reg16)
3565 i.suffix = WORD_MNEM_SUFFIX;
3566 else if (i.types[0].bitfield.reg32)
3567 i.suffix = LONG_MNEM_SUFFIX;
3568 else if (i.types[0].bitfield.reg64)
3569 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3570 }
9344ff29 3571 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3572 {
40fb9820 3573 if (i.types[0].bitfield.reg8)
20592a94
L		 3574 i.suffix = BYTE_MNEM_SUFFIX;
3575 }
381d071f
L		 3576
3577 if (!i.suffix)
3578 {
3579 int op;
3580
20592a94
L		 3581 if (i.tm.base_opcode == 0xf20f38f1
3582 || i.tm.base_opcode == 0xf20f38f0)
3583 {
3584 /* We have to know the operand size for crc32. */
3585 as_bad (_("ambiguous memory operand size for `%s`"),
3586 i.tm.name);
3587 return 0;
3588 }
3589
381d071f 3590 for (op = i.operands; --op >= 0;)
40fb9820 3591 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3592 {
40fb9820
L		 3593 if (i.types[op].bitfield.reg8)
3594 {
3595 i.suffix = BYTE_MNEM_SUFFIX;
3596 break;
3597 }
3598 else if (i.types[op].bitfield.reg16)
3599 {
3600 i.suffix = WORD_MNEM_SUFFIX;
3601 break;
3602 }
3603 else if (i.types[op].bitfield.reg32)
3604 {
3605 i.suffix = LONG_MNEM_SUFFIX;
3606 break;
3607 }
3608 else if (i.types[op].bitfield.reg64)
3609 {
3610 i.suffix = QWORD_MNEM_SUFFIX;
3611 break;
3612 }
381d071f
L		 3613 }
3614 }
29b0f896
AM		 3615 }
3616 else if (i.suffix == BYTE_MNEM_SUFFIX)
3617 {
3618 if (!check_byte_reg ())
3619 return 0;
3620 }
3621 else if (i.suffix == LONG_MNEM_SUFFIX)
3622 {
3623 if (!check_long_reg ())
3624 return 0;
3625 }
3626 else if (i.suffix == QWORD_MNEM_SUFFIX)
3627 {
955e1e6a
L		 3628 if (intel_syntax
3629 && i.tm.opcode_modifier.ignoresize
3630 && i.tm.opcode_modifier.no_qsuf)
3631 i.suffix = 0;
3632 else if (!check_qword_reg ())
29b0f896
AM		 3633 return 0;
3634 }
3635 else if (i.suffix == WORD_MNEM_SUFFIX)
3636 {
3637 if (!check_word_reg ())
3638 return 0;
3639 }
582d5edd
L		 3640 else if (i.suffix == XMMWORD_MNEM_SUFFIX)
3641 {
3642 /* Skip if the instruction has x suffix. match_template
3643 should check if it is a valid suffix. */
3644 }
40fb9820 3645 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 3646 /* Do nothing if the instruction is going to ignore the prefix. */
3647 ;
3648 else
3649 abort ();
3650 }
40fb9820 3651 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 3652 && !i.suffix
3653 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 3654 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 3655 {
3656 i.suffix = stackop_size;
3657 }
9306ca4a
JB		 3658 else if (intel_syntax
3659 && !i.suffix
40fb9820
L		 3660 && (i.tm.operand_types[0].bitfield.jumpabsolute
3661 || i.tm.opcode_modifier.jumpbyte
3662 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 3663 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3664 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 3665 {
3666 switch (flag_code)
3667 {
3668 case CODE_64BIT:
40fb9820 3669 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 3670 {
3671 i.suffix = QWORD_MNEM_SUFFIX;
3672 break;
3673 }
3674 case CODE_32BIT:
40fb9820 3675 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 3676 i.suffix = LONG_MNEM_SUFFIX;
3677 break;
3678 case CODE_16BIT:
40fb9820 3679 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 3680 i.suffix = WORD_MNEM_SUFFIX;
3681 break;
3682 }
3683 }
252b5132 3684
9306ca4a 3685 if (!i.suffix)
29b0f896 3686 {
9306ca4a
JB		 3687 if (!intel_syntax)
3688 {
40fb9820 3689 if (i.tm.opcode_modifier.w)
9306ca4a 3690 {
4eed87de
AM		 3691 as_bad (_("no instruction mnemonic suffix given and "
3692 "no register operands; can't size instruction"));
9306ca4a
JB		 3693 return 0;
3694 }
3695 }
3696 else
3697 {
40fb9820
L		 3698 unsigned int suffixes;
3699
3700 suffixes = !i.tm.opcode_modifier.no_bsuf;
3701 if (!i.tm.opcode_modifier.no_wsuf)
3702 suffixes |= 1 << 1;
3703 if (!i.tm.opcode_modifier.no_lsuf)
3704 suffixes |= 1 << 2;
fc4adea1 3705 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 3706 suffixes |= 1 << 3;
3707 if (!i.tm.opcode_modifier.no_ssuf)
3708 suffixes |= 1 << 4;
3709 if (!i.tm.opcode_modifier.no_qsuf)
3710 suffixes |= 1 << 5;
3711
3712 /* There are more than suffix matches. */
3713 if (i.tm.opcode_modifier.w
9306ca4a 3714 || ((suffixes & (suffixes - 1))
40fb9820
L		 3715 && !i.tm.opcode_modifier.defaultsize
3716 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 3717 {
3718 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3719 return 0;
3720 }
3721 }
29b0f896 3722 }
252b5132 3723
9306ca4a
JB		 3724 /* Change the opcode based on the operand size given by i.suffix;
3725 We don't need to change things for byte insns. */
3726
582d5edd
L		 3727 if (i.suffix
3728 && i.suffix != BYTE_MNEM_SUFFIX
3729 && i.suffix != XMMWORD_MNEM_SUFFIX)
29b0f896
AM		 3730 {
3731 /* It's not a byte, select word/dword operation. */
40fb9820 3732 if (i.tm.opcode_modifier.w)
29b0f896 3733 {
40fb9820 3734 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 3735 i.tm.base_opcode |= 8;
3736 else
3737 i.tm.base_opcode |= 1;
3738 }
0f3f3d8b 3739
29b0f896
AM		 3740 /* Now select between word & dword operations via the operand
3741 size prefix, except for instructions that will ignore this
3742 prefix anyway. */
ca61edf2 3743 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 3744 {
ca61edf2
L		 3745 /* The address size override prefix changes the size of the
3746 first operand. */
40fb9820
L		 3747 if ((flag_code == CODE_32BIT
3748 && i.op->regs[0].reg_type.bitfield.reg16)
3749 || (flag_code != CODE_32BIT
3750 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 3751 if (!add_prefix (ADDR_PREFIX_OPCODE))
3752 return 0;
3753 }
3754 else if (i.suffix != QWORD_MNEM_SUFFIX
3755 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 3756 && !i.tm.opcode_modifier.ignoresize
3757 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 3758 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3759 || (flag_code == CODE_64BIT
40fb9820 3760 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 3761 {
3762 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3763
40fb9820 3764 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 3765 prefix = ADDR_PREFIX_OPCODE;
252b5132 3766
29b0f896
AM		 3767 if (!add_prefix (prefix))
3768 return 0;
24eab124 3769 }
252b5132 3770
29b0f896
AM		 3771 /* Set mode64 for an operand. */
3772 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3773 && flag_code == CODE_64BIT
40fb9820 3774 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 3775 {
3776 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 3777 need rex64. cmpxchg8b is also a special case. */
3778 if (! (i.operands == 2
3779 && i.tm.base_opcode == 0x90
3780 && i.tm.extension_opcode == None
c6fb90c8
L		 3781 && UINTS_EQUAL (i.types [0], acc64)
3782 && UINTS_EQUAL (i.types [1], acc64))
d9a5e5e5
L		 3783 && ! (i.operands == 1
3784 && i.tm.base_opcode == 0xfc7
3785 && i.tm.extension_opcode == 1
40fb9820
L		 3786 && !operand_type_check (i.types [0], reg)
3787 && operand_type_check (i.types [0], anymem)))
f6bee062 3788 i.rex |= REX_W;
46e883c5 3789 }
3e73aa7c 3790
29b0f896
AM		 3791 /* Size floating point instruction. */
3792 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 3793 if (i.tm.opcode_modifier.floatmf)
543613e9 3794 i.tm.base_opcode ^= 4;
29b0f896 3795 }
7ecd2f8b 3796
29b0f896
AM		 3797 return 1;
3798}
3e73aa7c 3799
29b0f896 3800static int
543613e9 3801check_byte_reg (void)
29b0f896
AM		 3802{
3803 int op;
543613e9 3804
29b0f896
AM		 3805 for (op = i.operands; --op >= 0;)
3806 {
3807 /* If this is an eight bit register, it's OK. If it's the 16 or
3808 32 bit version of an eight bit register, we will just use the
3809 low portion, and that's OK too. */
40fb9820 3810 if (i.types[op].bitfield.reg8)
29b0f896
AM		 3811 continue;
3812
ca61edf2
L		 3813 /* Don't generate this warning if not needed. */
3814 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 3815 continue;
3816
9344ff29
L		 3817 /* crc32 doesn't generate this warning. */
3818 if (i.tm.base_opcode == 0xf20f38f0)
3819 continue;
3820
40fb9820
L		 3821 if ((i.types[op].bitfield.reg16
3822 || i.types[op].bitfield.reg32
3823 || i.types[op].bitfield.reg64)
3824 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3825 {
3826 /* Prohibit these changes in the 64bit mode, since the
3827 lowering is more complicated. */
3828 if (flag_code == CODE_64BIT
40fb9820 3829 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 3830 {
2ca3ace5
L		 3831 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3832 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3833 i.suffix);
3834 return 0;
3835 }
3836#if REGISTER_WARNINGS
3837 if (!quiet_warnings
40fb9820 3838 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 3839 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3840 register_prefix,
40fb9820 3841 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 3842 ? REGNAM_AL - REGNAM_AX
3843 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3844 register_prefix,
29b0f896
AM		 3845 i.op[op].regs->reg_name,
3846 i.suffix);
3847#endif
3848 continue;
3849 }
3850 /* Any other register is bad. */
40fb9820
L		 3851 if (i.types[op].bitfield.reg16
3852 || i.types[op].bitfield.reg32
3853 || i.types[op].bitfield.reg64
3854 || i.types[op].bitfield.regmmx
3855 || i.types[op].bitfield.regxmm
3856 || i.types[op].bitfield.sreg2
3857 || i.types[op].bitfield.sreg3
3858 || i.types[op].bitfield.control
3859 || i.types[op].bitfield.debug
3860 || i.types[op].bitfield.test
3861 || i.types[op].bitfield.floatreg
3862 || i.types[op].bitfield.floatacc)
29b0f896 3863 {
a540244d
L		 3864 as_bad (_("`%s%s' not allowed with `%s%c'"),
3865 register_prefix,
29b0f896
AM		 3866 i.op[op].regs->reg_name,
3867 i.tm.name,
3868 i.suffix);
3869 return 0;
3870 }
3871 }
3872 return 1;
3873}
3874
3875static int
e3bb37b5 3876check_long_reg (void)
29b0f896
AM		 3877{
3878 int op;
3879
3880 for (op = i.operands; --op >= 0;)
3881 /* Reject eight bit registers, except where the template requires
3882 them. (eg. movzb) */
40fb9820
L		 3883 if (i.types[op].bitfield.reg8
3884 && (i.tm.operand_types[op].bitfield.reg16
3885 || i.tm.operand_types[op].bitfield.reg32
3886 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3887 {
a540244d
L		 3888 as_bad (_("`%s%s' not allowed with `%s%c'"),
3889 register_prefix,
29b0f896
AM		 3890 i.op[op].regs->reg_name,
3891 i.tm.name,
3892 i.suffix);
3893 return 0;
3894 }
3895 /* Warn if the e prefix on a general reg is missing. */
3896 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3897 && i.types[op].bitfield.reg16
3898 && (i.tm.operand_types[op].bitfield.reg32
3899 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3900 {
3901 /* Prohibit these changes in the 64bit mode, since the
3902 lowering is more complicated. */
3903 if (flag_code == CODE_64BIT)
252b5132 3904 {
2ca3ace5
L		 3905 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3906 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3907 i.suffix);
3908 return 0;
252b5132 3909 }
29b0f896
AM		 3910#if REGISTER_WARNINGS
3911 else
a540244d
L		 3912 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3913 register_prefix,
29b0f896 3914 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3915 register_prefix,
29b0f896
AM		 3916 i.op[op].regs->reg_name,
3917 i.suffix);
3918#endif
252b5132 3919 }
29b0f896 3920 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 3921 else if (i.types[op].bitfield.reg64
3922 && (i.tm.operand_types[op].bitfield.reg32
3923 || i.tm.operand_types[op].bitfield.acc))
252b5132 3924 {
34828aad 3925 if (intel_syntax
ca61edf2 3926 && i.tm.opcode_modifier.toqword
40fb9820 3927 && !i.types[0].bitfield.regxmm)
34828aad 3928 {
ca61edf2 3929 /* Convert to QWORD. We want REX byte. */
34828aad
L		 3930 i.suffix = QWORD_MNEM_SUFFIX;
3931 }
3932 else
3933 {
3934 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3935 register_prefix, i.op[op].regs->reg_name,
3936 i.suffix);
3937 return 0;
3938 }
29b0f896
AM		 3939 }
3940 return 1;
3941}
252b5132 3942
29b0f896 3943static int
e3bb37b5 3944check_qword_reg (void)
29b0f896
AM		 3945{
3946 int op;
252b5132 3947
29b0f896
AM		 3948 for (op = i.operands; --op >= 0; )
3949 /* Reject eight bit registers, except where the template requires
3950 them. (eg. movzb) */
40fb9820
L		 3951 if (i.types[op].bitfield.reg8
3952 && (i.tm.operand_types[op].bitfield.reg16
3953 || i.tm.operand_types[op].bitfield.reg32
3954 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3955 {
a540244d
L		 3956 as_bad (_("`%s%s' not allowed with `%s%c'"),
3957 register_prefix,
29b0f896
AM		 3958 i.op[op].regs->reg_name,
3959 i.tm.name,
3960 i.suffix);
3961 return 0;
3962 }
3963 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 3964 else if ((i.types[op].bitfield.reg16
3965 || i.types[op].bitfield.reg32)
3966 && (i.tm.operand_types[op].bitfield.reg32
3967 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3968 {
3969 /* Prohibit these changes in the 64bit mode, since the
3970 lowering is more complicated. */
34828aad 3971 if (intel_syntax
ca61edf2 3972 && i.tm.opcode_modifier.todword
40fb9820 3973 && !i.types[0].bitfield.regxmm)
34828aad 3974 {
ca61edf2 3975 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 3976 i.suffix = LONG_MNEM_SUFFIX;
3977 }
3978 else
3979 {
3980 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3981 register_prefix, i.op[op].regs->reg_name,
3982 i.suffix);
3983 return 0;
3984 }
252b5132 3985 }
29b0f896
AM		 3986 return 1;
3987}
252b5132 3988
29b0f896 3989static int
e3bb37b5 3990check_word_reg (void)
29b0f896
AM		 3991{
3992 int op;
3993 for (op = i.operands; --op >= 0;)
3994 /* Reject eight bit registers, except where the template requires
3995 them. (eg. movzb) */
40fb9820
L		 3996 if (i.types[op].bitfield.reg8
3997 && (i.tm.operand_types[op].bitfield.reg16
3998 || i.tm.operand_types[op].bitfield.reg32
3999 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4000 {
a540244d
L		 4001 as_bad (_("`%s%s' not allowed with `%s%c'"),
4002 register_prefix,
29b0f896
AM		 4003 i.op[op].regs->reg_name,
4004 i.tm.name,
4005 i.suffix);
4006 return 0;
4007 }
4008 /* Warn if the e prefix on a general reg is present. */
4009 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4010 && i.types[op].bitfield.reg32
4011 && (i.tm.operand_types[op].bitfield.reg16
4012 || i.tm.operand_types[op].bitfield.acc))
252b5132 4013 {
29b0f896
AM		 4014 /* Prohibit these changes in the 64bit mode, since the
4015 lowering is more complicated. */
4016 if (flag_code == CODE_64BIT)
252b5132 4017 {
2ca3ace5
L		 4018 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4019 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4020 i.suffix);
4021 return 0;
252b5132 4022 }
29b0f896
AM		 4023 else
4024#if REGISTER_WARNINGS
a540244d
L		 4025 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4026 register_prefix,
29b0f896 4027 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4028 register_prefix,
29b0f896
AM		 4029 i.op[op].regs->reg_name,
4030 i.suffix);
4031#endif
4032 }
4033 return 1;
4034}
252b5132 4035
29b0f896 4036static int
40fb9820 4037update_imm (unsigned int j)
29b0f896 4038{
40fb9820
L		 4039 i386_operand_type overlap;
4040
c6fb90c8 4041 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 4042 if ((overlap.bitfield.imm8
4043 || overlap.bitfield.imm8s
4044 || overlap.bitfield.imm16
4045 || overlap.bitfield.imm32
4046 || overlap.bitfield.imm32s
4047 || overlap.bitfield.imm64)
c6fb90c8
L		 4048 && !UINTS_EQUAL (overlap, imm8)
4049 && !UINTS_EQUAL (overlap, imm8s)
4050 && !UINTS_EQUAL (overlap, imm16)
4051 && !UINTS_EQUAL (overlap, imm32)
4052 && !UINTS_EQUAL (overlap, imm32s)
4053 && !UINTS_EQUAL (overlap, imm64))
29b0f896
AM		 4054 {
4055 if (i.suffix)
4056 {
40fb9820
L		 4057 i386_operand_type temp;
4058
c6fb90c8 4059 UINTS_CLEAR (temp);
40fb9820
L		 4060 if (i.suffix == BYTE_MNEM_SUFFIX)
4061 {
4062 temp.bitfield.imm8 = overlap.bitfield.imm8;
4063 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4064 }
4065 else if (i.suffix == WORD_MNEM_SUFFIX)
4066 temp.bitfield.imm16 = overlap.bitfield.imm16;
4067 else if (i.suffix == QWORD_MNEM_SUFFIX)
4068 {
4069 temp.bitfield.imm64 = overlap.bitfield.imm64;
4070 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4071 }
4072 else
4073 temp.bitfield.imm32 = overlap.bitfield.imm32;
4074 overlap = temp;
29b0f896 4075 }
c6fb90c8
L		 4076 else if (UINTS_EQUAL (overlap, imm16_32_32s)
4077 || UINTS_EQUAL (overlap, imm16_32)
4078 || UINTS_EQUAL (overlap, imm16_32s))
29b0f896 4079 {
c6fb90c8 4080 UINTS_CLEAR (overlap);
40fb9820
L		 4081 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4082 overlap.bitfield.imm16 = 1;
4083 else
4084 overlap.bitfield.imm32s = 1;
29b0f896 4085 }
c6fb90c8
L		 4086 if (!UINTS_EQUAL (overlap, imm8)
4087 && !UINTS_EQUAL (overlap, imm8s)
4088 && !UINTS_EQUAL (overlap, imm16)
4089 && !UINTS_EQUAL (overlap, imm32)
4090 && !UINTS_EQUAL (overlap, imm32s)
4091 && !UINTS_EQUAL (overlap, imm64))
29b0f896 4092 {
4eed87de
AM		 4093 as_bad (_("no instruction mnemonic suffix given; "
4094 "can't determine immediate size"));
29b0f896
AM		 4095 return 0;
4096 }
4097 }
40fb9820 4098 i.types[j] = overlap;
29b0f896 4099
40fb9820
L		 4100 return 1;
4101}
4102
4103static int
4104finalize_imm (void)
4105{
4106 unsigned int j;
29b0f896 4107
40fb9820
L		 4108 for (j = 0; j < 2; j++)
4109 if (update_imm (j) == 0)
4110 return 0;
4111
c6fb90c8 4112 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 4113 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 4114
4115 return 1;
4116}
4117
85f10a01
MM		 4118static void
4119process_drex (void)
4120{
5dd15031
JJ		 4121 i.drex.modrm_reg = 0;
4122 i.drex.modrm_regmem = 0;
85f10a01
MM		 4123
4124 /* SSE5 4 operand instructions must have the destination the same as
4125 one of the inputs. Figure out the destination register and cache
4126 it away in the drex field, and remember which fields to use for
4127 the modrm byte. */
4128 if (i.tm.opcode_modifier.drex
4129 && i.tm.opcode_modifier.drexv
4130 && i.operands == 4)
4131 {
4132 i.tm.extension_opcode = None;
4133
4134 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4135 if (i.types[0].bitfield.regxmm != 0
4136 && i.types[1].bitfield.regxmm != 0
4137 && i.types[2].bitfield.regxmm != 0
4138 && i.types[3].bitfield.regxmm != 0
4139 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4140 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4141 {
4142 /* Clear the arguments that are stored in drex. */
4143 UINTS_CLEAR (i.types[0]);
4144 UINTS_CLEAR (i.types[3]);
4145 i.reg_operands -= 2;
4146
4147 /* There are two different ways to encode a 4 operand
4148 instruction with all registers that uses OC1 set to
4149 0 or 1. Favor setting OC1 to 0 since this mimics the
4150 actions of other SSE5 assemblers. Use modrm encoding 2
4151 for register/register. Include the high order bit that
4152 is normally stored in the REX byte in the register
4153 field. */
4154 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4155 i.drex.modrm_reg = 2;
4156 i.drex.modrm_regmem = 1;
4157 i.drex.reg = (i.op[3].regs->reg_num
4158 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4159 }
4160
4161 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4162 else if (i.types[0].bitfield.regxmm != 0
4163 && i.types[1].bitfield.regxmm != 0
4164 && (i.types[2].bitfield.regxmm
4165 || operand_type_check (i.types[2], anymem))
4166 && i.types[3].bitfield.regxmm != 0
4167 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4168 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4169 {
4170 /* clear the arguments that are stored in drex */
4171 UINTS_CLEAR (i.types[0]);
4172 UINTS_CLEAR (i.types[3]);
4173 i.reg_operands -= 2;
4174
4175 /* Specify the modrm encoding for memory addressing. Include
4176 the high order bit that is normally stored in the REX byte
4177 in the register field. */
4178 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4179 i.drex.modrm_reg = 1;
4180 i.drex.modrm_regmem = 2;
4181 i.drex.reg = (i.op[3].regs->reg_num
4182 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4183 }
4184
4185 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4186 else if (i.types[0].bitfield.regxmm != 0
4187 && operand_type_check (i.types[1], anymem) != 0
4188 && i.types[2].bitfield.regxmm != 0
4189 && i.types[3].bitfield.regxmm != 0
4190 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4191 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4192 {
4193 /* Clear the arguments that are stored in drex. */
4194 UINTS_CLEAR (i.types[0]);
4195 UINTS_CLEAR (i.types[3]);
4196 i.reg_operands -= 2;
4197
4198 /* Specify the modrm encoding for memory addressing. Include
4199 the high order bit that is normally stored in the REX byte
4200 in the register field. */
4201 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4202 i.drex.modrm_reg = 2;
4203 i.drex.modrm_regmem = 1;
4204 i.drex.reg = (i.op[3].regs->reg_num
4205 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4206 }
4207
4208 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4209 else if (i.types[0].bitfield.regxmm != 0
4210 && i.types[1].bitfield.regxmm != 0
4211 && i.types[2].bitfield.regxmm != 0
4212 && i.types[3].bitfield.regxmm != 0
4213 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4214 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4215 {
4216 /* clear the arguments that are stored in drex */
4217 UINTS_CLEAR (i.types[2]);
4218 UINTS_CLEAR (i.types[3]);
4219 i.reg_operands -= 2;
4220
4221 /* There are two different ways to encode a 4 operand
4222 instruction with all registers that uses OC1 set to
4223 0 or 1. Favor setting OC1 to 0 since this mimics the
4224 actions of other SSE5 assemblers. Use modrm encoding
4225 2 for register/register. Include the high order bit that
4226 is normally stored in the REX byte in the register
4227 field. */
4228 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4229 i.drex.modrm_reg = 1;
4230 i.drex.modrm_regmem = 0;
4231
4232 /* Remember the register, including the upper bits */
4233 i.drex.reg = (i.op[3].regs->reg_num
4234 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4235 }
4236
4237 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4238 else if (i.types[0].bitfield.regxmm != 0
4239 && (i.types[1].bitfield.regxmm
4240 || operand_type_check (i.types[1], anymem))
4241 && i.types[2].bitfield.regxmm != 0
4242 && i.types[3].bitfield.regxmm != 0
4243 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4244 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4245 {
4246 /* Clear the arguments that are stored in drex. */
4247 UINTS_CLEAR (i.types[2]);
4248 UINTS_CLEAR (i.types[3]);
4249 i.reg_operands -= 2;
4250
4251 /* Specify the modrm encoding and remember the register
4252 including the bits normally stored in the REX byte. */
4253 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4254 i.drex.modrm_reg = 0;
4255 i.drex.modrm_regmem = 1;
4256 i.drex.reg = (i.op[3].regs->reg_num
4257 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4258 }
4259
4260 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4261 else if (operand_type_check (i.types[0], anymem) != 0
4262 && i.types[1].bitfield.regxmm != 0
4263 && i.types[2].bitfield.regxmm != 0
4264 && i.types[3].bitfield.regxmm != 0
4265 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4266 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4267 {
4268 /* clear the arguments that are stored in drex */
4269 UINTS_CLEAR (i.types[2]);
4270 UINTS_CLEAR (i.types[3]);
4271 i.reg_operands -= 2;
4272
4273 /* Specify the modrm encoding and remember the register
4274 including the bits normally stored in the REX byte. */
4275 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4276 i.drex.modrm_reg = 1;
4277 i.drex.modrm_regmem = 0;
4278 i.drex.reg = (i.op[3].regs->reg_num
4279 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4280 }
4281
4282 else
4283 as_bad (_("Incorrect operands for the '%s' instruction"),
4284 i.tm.name);
4285 }
4286
4287 /* SSE5 instructions with the DREX byte where the only memory operand
4288 is in the 2nd argument, and the first and last xmm register must
4289 match, and is encoded in the DREX byte. */
4290 else if (i.tm.opcode_modifier.drex
4291 && !i.tm.opcode_modifier.drexv
4292 && i.operands == 4)
4293 {
4294 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4295 if (i.types[0].bitfield.regxmm != 0
4296 && (i.types[1].bitfield.regxmm
4297 || operand_type_check(i.types[1], anymem))
4298 && i.types[2].bitfield.regxmm != 0
4299 && i.types[3].bitfield.regxmm != 0
4300 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4301 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4302 {
4303 /* clear the arguments that are stored in drex */
4304 UINTS_CLEAR (i.types[0]);
4305 UINTS_CLEAR (i.types[3]);
4306 i.reg_operands -= 2;
4307
4308 /* Specify the modrm encoding and remember the register
4309 including the high bit normally stored in the REX
4310 byte. */
4311 i.drex.modrm_reg = 2;
4312 i.drex.modrm_regmem = 1;
4313 i.drex.reg = (i.op[3].regs->reg_num
4314 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4315 }
4316
4317 else
4318 as_bad (_("Incorrect operands for the '%s' instruction"),
4319 i.tm.name);
4320 }
4321
4322 /* SSE5 3 operand instructions that the result is a register, being
4323 either operand can be a memory operand, using OC0 to note which
4324 one is the memory. */
4325 else if (i.tm.opcode_modifier.drex
4326 && i.tm.opcode_modifier.drexv
4327 && i.operands == 3)
4328 {
4329 i.tm.extension_opcode = None;
4330
4331 /* Case 1: 3 operand insn, src1 = register. */
4332 if (i.types[0].bitfield.regxmm != 0
4333 && i.types[1].bitfield.regxmm != 0
4334 && i.types[2].bitfield.regxmm != 0)
4335 {
4336 /* Clear the arguments that are stored in drex. */
4337 UINTS_CLEAR (i.types[2]);
4338 i.reg_operands--;
4339
4340 /* Specify the modrm encoding and remember the register
4341 including the high bit normally stored in the REX byte. */
4342 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4343 i.drex.modrm_reg = 1;
4344 i.drex.modrm_regmem = 0;
4345 i.drex.reg = (i.op[2].regs->reg_num
4346 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4347 }
4348
4349 /* Case 2: 3 operand insn, src1 = memory. */
4350 else if (operand_type_check (i.types[0], anymem) != 0
4351 && i.types[1].bitfield.regxmm != 0
4352 && i.types[2].bitfield.regxmm != 0)
4353 {
4354 /* Clear the arguments that are stored in drex. */
4355 UINTS_CLEAR (i.types[2]);
4356 i.reg_operands--;
4357
4358 /* Specify the modrm encoding and remember the register
4359 including the high bit normally stored in the REX
4360 byte. */
4361 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4362 i.drex.modrm_reg = 1;
4363 i.drex.modrm_regmem = 0;
4364 i.drex.reg = (i.op[2].regs->reg_num
4365 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4366 }
4367
4368 /* Case 3: 3 operand insn, src2 = memory. */
4369 else if (i.types[0].bitfield.regxmm != 0
4370 && operand_type_check (i.types[1], anymem) != 0
4371 && i.types[2].bitfield.regxmm != 0)
4372 {
4373 /* Clear the arguments that are stored in drex. */
4374 UINTS_CLEAR (i.types[2]);
4375 i.reg_operands--;
4376
4377 /* Specify the modrm encoding and remember the register
4378 including the high bit normally stored in the REX byte. */
4379 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4380 i.drex.modrm_reg = 0;
4381 i.drex.modrm_regmem = 1;
4382 i.drex.reg = (i.op[2].regs->reg_num
4383 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4384 }
4385
4386 else
4387 as_bad (_("Incorrect operands for the '%s' instruction"),
4388 i.tm.name);
4389 }
4390
4391 /* SSE5 4 operand instructions that are the comparison instructions
4392 where the first operand is the immediate value of the comparison
4393 to be done. */
4394 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4395 {
4396 /* Case 1: 4 operand insn, src1 = reg/memory. */
4397 if (operand_type_check (i.types[0], imm) != 0
4398 && (i.types[1].bitfield.regxmm
4399 || operand_type_check (i.types[1], anymem))
4400 && i.types[2].bitfield.regxmm != 0
4401 && i.types[3].bitfield.regxmm != 0)
4402 {
4403 /* clear the arguments that are stored in drex */
4404 UINTS_CLEAR (i.types[3]);
4405 i.reg_operands--;
4406
4407 /* Specify the modrm encoding and remember the register
4408 including the high bit normally stored in the REX byte. */
4409 i.drex.modrm_reg = 2;
4410 i.drex.modrm_regmem = 1;
4411 i.drex.reg = (i.op[3].regs->reg_num
4412 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4413 }
4414
4415 /* Case 2: 3 operand insn with ImmExt that places the
4416 opcode_extension as an immediate argument. This is used for
4417 all of the varients of comparison that supplies the appropriate
4418 value as part of the instruction. */
4419 else if ((i.types[0].bitfield.regxmm
4420 || operand_type_check (i.types[0], anymem))
4421 && i.types[1].bitfield.regxmm != 0
4422 && i.types[2].bitfield.regxmm != 0
4423 && operand_type_check (i.types[3], imm) != 0)
4424 {
4425 /* clear the arguments that are stored in drex */
4426 UINTS_CLEAR (i.types[2]);
4427 i.reg_operands--;
4428
4429 /* Specify the modrm encoding and remember the register
4430 including the high bit normally stored in the REX byte. */
4431 i.drex.modrm_reg = 1;
4432 i.drex.modrm_regmem = 0;
4433 i.drex.reg = (i.op[2].regs->reg_num
4434 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4435 }
4436
4437 else
4438 as_bad (_("Incorrect operands for the '%s' instruction"),
4439 i.tm.name);
4440 }
4441
4442 else if (i.tm.opcode_modifier.drex
4443 || i.tm.opcode_modifier.drexv
4444 || i.tm.opcode_modifier.drexc)
4445 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4446}
4447
29b0f896 4448static int
e3bb37b5 4449process_operands (void)
29b0f896
AM		 4450{
4451 /* Default segment register this instruction will use for memory
4452 accesses. 0 means unknown. This is only for optimizing out
4453 unnecessary segment overrides. */
4454 const seg_entry *default_seg = 0;
4455
85f10a01
MM		 4456 /* Handle all of the DREX munging that SSE5 needs. */
4457 if (i.tm.opcode_modifier.drex
4458 || i.tm.opcode_modifier.drexv
4459 || i.tm.opcode_modifier.drexc)
4460 process_drex ();
4461
e2ec9d29 4462 if (i.tm.opcode_modifier.firstxmm0)
29b0f896 4463 {
9fcfb3d7
L		 4464 unsigned int j;
4465
e2ec9d29
L		 4466 /* The first operand is implicit and must be xmm0. */
4467 assert (i.reg_operands && UINTS_EQUAL (i.types[0], regxmm));
4468 if (i.op[0].regs->reg_num != 0)
4469 {
4470 if (intel_syntax)
4471 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4472 i.tm.name, register_prefix);
4473 else
4474 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4475 i.tm.name, register_prefix);
4476 return 0;
4477 }
9fcfb3d7
L		 4478
4479 for (j = 1; j < i.operands; j++)
4480 {
4481 i.op[j - 1] = i.op[j];
4482 i.types[j - 1] = i.types[j];
4483
4484 /* We need to adjust fields in i.tm since they are used by
4485 build_modrm_byte. */
4486 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4487 }
4488
e2ec9d29
L		 4489 i.operands--;
4490 i.reg_operands--;
e2ec9d29
L		 4491 i.tm.operands--;
4492 }
4493 else if (i.tm.opcode_modifier.regkludge)
4494 {
4495 /* The imul $imm, %reg instruction is converted into
4496 imul $imm, %reg, %reg, and the clr %reg instruction
4497 is converted into xor %reg, %reg. */
4498
4499 unsigned int first_reg_op;
4500
4501 if (operand_type_check (i.types[0], reg))
4502 first_reg_op = 0;
4503 else
4504 first_reg_op = 1;
4505 /* Pretend we saw the extra register operand. */
4506 assert (i.reg_operands == 1
4507 && i.op[first_reg_op + 1].regs == 0);
4508 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4509 i.types[first_reg_op + 1] = i.types[first_reg_op];
4510 i.operands++;
4511 i.reg_operands++;
29b0f896
AM		 4512 }
4513
40fb9820 4514 if (i.tm.opcode_modifier.shortform)
29b0f896 4515 {
40fb9820
L		 4516 if (i.types[0].bitfield.sreg2
4517 || i.types[0].bitfield.sreg3)
29b0f896 4518 {
4eed87de
AM		 4519 if (i.tm.base_opcode == POP_SEG_SHORT
4520 && i.op[0].regs->reg_num == 1)
29b0f896 4521 {
4eed87de
AM		 4522 as_bad (_("you can't `pop %%cs'"));
4523 return 0;
29b0f896 4524 }
4eed87de
AM		 4525 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4526 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4527 i.rex |= REX_B;
4eed87de
AM		 4528 }
4529 else
4530 {
85f10a01
MM		 4531 /* The register or float register operand is in operand
4532 0 or 1. */
40fb9820
L		 4533 unsigned int op;
4534
4535 if (i.types[0].bitfield.floatreg
4536 || operand_type_check (i.types[0], reg))
4537 op = 0;
4538 else
4539 op = 1;
4eed87de
AM		 4540 /* Register goes in low 3 bits of opcode. */
4541 i.tm.base_opcode |= i.op[op].regs->reg_num;
4542 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4543 i.rex |= REX_B;
40fb9820 4544 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4545 {
4eed87de
AM		 4546 /* Warn about some common errors, but press on regardless.
4547 The first case can be generated by gcc (<= 2.8.1). */
4548 if (i.operands == 2)
4549 {
4550 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 4551 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4552 register_prefix, i.op[1].regs->reg_name,
4553 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 4554 }
4555 else
4556 {
4557 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4558 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4559 register_prefix, i.op[0].regs->reg_name);
4eed87de 4560 }
29b0f896
AM		 4561 }
4562 }
4563 }
40fb9820 4564 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4565 {
4566 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4567 must be put into the modrm byte). Now, we make the modrm and
4568 index base bytes based on all the info we've collected. */
29b0f896
AM		 4569
4570 default_seg = build_modrm_byte ();
4571 }
8a2ed489 4572 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4573 {
4574 default_seg = &ds;
4575 }
40fb9820 4576 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4577 {
4578 /* For the string instructions that allow a segment override
4579 on one of their operands, the default segment is ds. */
4580 default_seg = &ds;
4581 }
4582
75178d9d
L		 4583 if (i.tm.base_opcode == 0x8d /* lea */
4584 && i.seg[0]
4585 && !quiet_warnings)
30123838 4586 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4587
4588 /* If a segment was explicitly specified, and the specified segment
4589 is not the default, use an opcode prefix to select it. If we
4590 never figured out what the default segment is, then default_seg
4591 will be zero at this point, and the specified segment prefix will
4592 always be used. */
29b0f896
AM		 4593 if ((i.seg[0]) && (i.seg[0] != default_seg))
4594 {
4595 if (!add_prefix (i.seg[0]->seg_prefix))
4596 return 0;
4597 }
4598 return 1;
4599}
4600
4601static const seg_entry *
e3bb37b5 4602build_modrm_byte (void)
29b0f896
AM		 4603{
4604 const seg_entry *default_seg = 0;
4605
85f10a01
MM		 4606 /* SSE5 4 operand instructions are encoded in such a way that one of
4607 the inputs must match the destination register. Process_drex hides
4608 the 3rd argument in the drex field, so that by the time we get
4609 here, it looks to GAS as if this is a 2 operand instruction. */
4610 if ((i.tm.opcode_modifier.drex
4611 || i.tm.opcode_modifier.drexv
b5016f89 4612 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4613 && i.reg_operands == 2)
4614 {
4615 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4616 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4617
4618 i.rm.reg = reg->reg_num;
4619 i.rm.regmem = regmem->reg_num;
4620 i.rm.mode = 3;
4621 if ((reg->reg_flags & RegRex) != 0)
4622 i.rex |= REX_R;
4623 if ((regmem->reg_flags & RegRex) != 0)
4624 i.rex |= REX_B;
4625 }
4626
29b0f896
AM		 4627 /* i.reg_operands MUST be the number of real register operands;
4628 implicit registers do not count. */
85f10a01 4629 else if (i.reg_operands == 2)
29b0f896
AM		 4630 {
4631 unsigned int source, dest;
cab737b9
L		 4632
4633 switch (i.operands)
4634 {
4635 case 2:
4636 source = 0;
4637 break;
4638 case 3:
c81128dc
L		 4639 /* When there are 3 operands, one of them may be immediate,
4640 which may be the first or the last operand. Otherwise,
4641 the first operand must be shift count register (cl). */
4642 assert (i.imm_operands == 1
4643 || (i.imm_operands == 0
40fb9820
L		 4644 && i.types[0].bitfield.shiftcount));
4645 if (operand_type_check (i.types[0], imm)
4646 || i.types[0].bitfield.shiftcount)
4647 source = 1;
4648 else
4649 source = 0;
cab737b9
L		 4650 break;
4651 case 4:
368d64cc
L		 4652 /* When there are 4 operands, the first two must be 8bit
4653 immediate operands. The source operand will be the 3rd
4654 one. */
cab737b9 4655 assert (i.imm_operands == 2
368d64cc
L		 4656 && i.types[0].bitfield.imm8
4657 && i.types[1].bitfield.imm8);
cab737b9
L		 4658 source = 2;
4659 break;
4660 default:
4661 abort ();
4662 }
4663
29b0f896
AM		 4664 dest = source + 1;
4665
4666 i.rm.mode = 3;
4667 /* One of the register operands will be encoded in the i.tm.reg
4668 field, the other in the combined i.tm.mode and i.tm.regmem
4669 fields. If no form of this instruction supports a memory
4670 destination operand, then we assume the source operand may
4671 sometimes be a memory operand and so we need to store the
4672 destination in the i.rm.reg field. */
40fb9820
L		 4673 if (!i.tm.operand_types[dest].bitfield.regmem
4674 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 4675 {
4676 i.rm.reg = i.op[dest].regs->reg_num;
4677 i.rm.regmem = i.op[source].regs->reg_num;
4678 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4679 i.rex |= REX_R;
29b0f896 4680 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4681 i.rex |= REX_B;
29b0f896
AM		 4682 }
4683 else
4684 {
4685 i.rm.reg = i.op[source].regs->reg_num;
4686 i.rm.regmem = i.op[dest].regs->reg_num;
4687 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4688 i.rex |= REX_B;
29b0f896 4689 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4690 i.rex |= REX_R;
29b0f896 4691 }
161a04f6 4692 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 4693 {
40fb9820
L		 4694 if (!i.types[0].bitfield.control
4695 && !i.types[1].bitfield.control)
c4a530c5 4696 abort ();
161a04f6 4697 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 4698 add_prefix (LOCK_PREFIX_OPCODE);
4699 }
29b0f896
AM		 4700 }
4701 else
4702 { /* If it's not 2 reg operands... */
4703 if (i.mem_operands)
4704 {
4705 unsigned int fake_zero_displacement = 0;
99018f42 4706 unsigned int op;
4eed87de 4707
85f10a01
MM		 4708 /* This has been precalculated for SSE5 instructions
4709 that have a DREX field earlier in process_drex. */
b5016f89
L		 4710 if (i.tm.opcode_modifier.drex
4711 || i.tm.opcode_modifier.drexv
4712 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4713 op = i.drex.modrm_regmem;
4714 else
4715 {
c0209578
L		 4716 for (op = 0; op < i.operands; op++)
4717 if (operand_type_check (i.types[op], anymem))
4718 break;
4719 assert (op < i.operands);
85f10a01 4720 }
29b0f896
AM		 4721
4722 default_seg = &ds;
4723
4724 if (i.base_reg == 0)
4725 {
4726 i.rm.mode = 0;
4727 if (!i.disp_operands)
4728 fake_zero_displacement = 1;
4729 if (i.index_reg == 0)
4730 {
4731 /* Operand is just <disp> */
20f0a1fc 4732 if (flag_code == CODE_64BIT)
29b0f896
AM		 4733 {
4734 /* 64bit mode overwrites the 32bit absolute
4735 addressing by RIP relative addressing and
4736 absolute addressing is encoded by one of the
4737 redundant SIB forms. */
4738 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4739 i.sib.base = NO_BASE_REGISTER;
4740 i.sib.index = NO_INDEX_REGISTER;
fc225355 4741 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 4742 ? disp32s : disp32);
20f0a1fc 4743 }
fc225355
L		 4744 else if ((flag_code == CODE_16BIT)
4745 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 4746 {
4747 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 4748 i.types[op] = disp16;
20f0a1fc
NC		 4749 }
4750 else
4751 {
4752 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 4753 i.types[op] = disp32;
29b0f896
AM		 4754 }
4755 }
4756 else /* !i.base_reg && i.index_reg */
4757 {
db51cc60
L		 4758 if (i.index_reg->reg_num == RegEiz
4759 || i.index_reg->reg_num == RegRiz)
4760 i.sib.index = NO_INDEX_REGISTER;
4761 else
4762 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4763 i.sib.base = NO_BASE_REGISTER;
4764 i.sib.scale = i.log2_scale_factor;
4765 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 4766 i.types[op].bitfield.disp8 = 0;
4767 i.types[op].bitfield.disp16 = 0;
4768 i.types[op].bitfield.disp64 = 0;
29b0f896 4769 if (flag_code != CODE_64BIT)
40fb9820
L		 4770 {
4771 /* Must be 32 bit */
4772 i.types[op].bitfield.disp32 = 1;
4773 i.types[op].bitfield.disp32s = 0;
4774 }
29b0f896 4775 else
40fb9820
L		 4776 {
4777 i.types[op].bitfield.disp32 = 0;
4778 i.types[op].bitfield.disp32s = 1;
4779 }
29b0f896 4780 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4781 i.rex |= REX_X;
29b0f896
AM		 4782 }
4783 }
4784 /* RIP addressing for 64bit mode. */
9a04903e
JB		 4785 else if (i.base_reg->reg_num == RegRip ||
4786 i.base_reg->reg_num == RegEip)
29b0f896
AM		 4787 {
4788 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 4789 i.types[op].bitfield.disp8 = 0;
4790 i.types[op].bitfield.disp16 = 0;
4791 i.types[op].bitfield.disp32 = 0;
4792 i.types[op].bitfield.disp32s = 1;
4793 i.types[op].bitfield.disp64 = 0;
71903a11 4794 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 4795 if (! i.disp_operands)
4796 fake_zero_displacement = 1;
29b0f896 4797 }
40fb9820 4798 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 4799 {
4800 switch (i.base_reg->reg_num)
4801 {
4802 case 3: /* (%bx) */
4803 if (i.index_reg == 0)
4804 i.rm.regmem = 7;
4805 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4806 i.rm.regmem = i.index_reg->reg_num - 6;
4807 break;
4808 case 5: /* (%bp) */
4809 default_seg = &ss;
4810 if (i.index_reg == 0)
4811 {
4812 i.rm.regmem = 6;
40fb9820 4813 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 4814 {
4815 /* fake (%bp) into 0(%bp) */
40fb9820 4816 i.types[op].bitfield.disp8 = 1;
252b5132 4817 fake_zero_displacement = 1;
29b0f896
AM		 4818 }
4819 }
4820 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4821 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4822 break;
4823 default: /* (%si) -> 4 or (%di) -> 5 */
4824 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4825 }
4826 i.rm.mode = mode_from_disp_size (i.types[op]);
4827 }
4828 else /* i.base_reg and 32/64 bit mode */
4829 {
4830 if (flag_code == CODE_64BIT
40fb9820
L		 4831 && operand_type_check (i.types[op], disp))
4832 {
4833 i386_operand_type temp;
c6fb90c8 4834 UINTS_CLEAR (temp);
40fb9820
L		 4835 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4836 i.types[op] = temp;
4837 if (i.prefix[ADDR_PREFIX] == 0)
4838 i.types[op].bitfield.disp32s = 1;
4839 else
4840 i.types[op].bitfield.disp32 = 1;
4841 }
20f0a1fc 4842
29b0f896
AM		 4843 i.rm.regmem = i.base_reg->reg_num;
4844 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 4845 i.rex |= REX_B;
29b0f896
AM		 4846 i.sib.base = i.base_reg->reg_num;
4847 /* x86-64 ignores REX prefix bit here to avoid decoder
4848 complications. */
4849 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4850 {
4851 default_seg = &ss;
4852 if (i.disp_operands == 0)
4853 {
4854 fake_zero_displacement = 1;
40fb9820 4855 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 4856 }
4857 }
4858 else if (i.base_reg->reg_num == ESP_REG_NUM)
4859 {
4860 default_seg = &ss;
4861 }
4862 i.sib.scale = i.log2_scale_factor;
4863 if (i.index_reg == 0)
4864 {
4865 /* <disp>(%esp) becomes two byte modrm with no index
4866 register. We've already stored the code for esp
4867 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4868 Any base register besides %esp will not use the
4869 extra modrm byte. */
4870 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 4871 }
4872 else
4873 {
db51cc60
L		 4874 if (i.index_reg->reg_num == RegEiz
4875 || i.index_reg->reg_num == RegRiz)
4876 i.sib.index = NO_INDEX_REGISTER;
4877 else
4878 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4879 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4880 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4881 i.rex |= REX_X;
29b0f896 4882 }
67a4f2b7
AO		 4883
4884 if (i.disp_operands
4885 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4886 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4887 i.rm.mode = 0;
4888 else
4889 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 4890 }
252b5132 4891
29b0f896
AM		 4892 if (fake_zero_displacement)
4893 {
4894 /* Fakes a zero displacement assuming that i.types[op]
4895 holds the correct displacement size. */
4896 expressionS *exp;
4897
4898 assert (i.op[op].disps == 0);
4899 exp = &disp_expressions[i.disp_operands++];
4900 i.op[op].disps = exp;
4901 exp->X_op = O_constant;
4902 exp->X_add_number = 0;
4903 exp->X_add_symbol = (symbolS *) 0;
4904 exp->X_op_symbol = (symbolS *) 0;
4905 }
4906 }
252b5132 4907
29b0f896
AM		 4908 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4909 (if any) based on i.tm.extension_opcode. Again, we must be
4910 careful to make sure that segment/control/debug/test/MMX
4911 registers are coded into the i.rm.reg field. */
4912 if (i.reg_operands)
4913 {
99018f42
L		 4914 unsigned int op;
4915
85f10a01
MM		 4916 /* This has been precalculated for SSE5 instructions
4917 that have a DREX field earlier in process_drex. */
b5016f89
L		 4918 if (i.tm.opcode_modifier.drex
4919 || i.tm.opcode_modifier.drexv
4920 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4921 {
4922 op = i.drex.modrm_reg;
4923 i.rm.reg = i.op[op].regs->reg_num;
4924 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4925 i.rex |= REX_R;
4926 }
4927 else
4928 {
c0209578
L		 4929 for (op = 0; op < i.operands; op++)
4930 if (i.types[op].bitfield.reg8
4931 || i.types[op].bitfield.reg16
4932 || i.types[op].bitfield.reg32
4933 || i.types[op].bitfield.reg64
4934 || i.types[op].bitfield.regmmx
4935 || i.types[op].bitfield.regxmm
4936 || i.types[op].bitfield.sreg2
4937 || i.types[op].bitfield.sreg3
4938 || i.types[op].bitfield.control
4939 || i.types[op].bitfield.debug
4940 || i.types[op].bitfield.test)
4941 break;
4942
4943 assert (op < i.operands);
99018f42 4944
85f10a01
MM		 4945 /* If there is an extension opcode to put here, the
4946 register number must be put into the regmem field. */
c0209578
L		 4947 if (i.tm.extension_opcode != None)
4948 {
4949 i.rm.regmem = i.op[op].regs->reg_num;
4950 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4951 i.rex |= REX_B;
4952 }
4953 else
4954 {
4955 i.rm.reg = i.op[op].regs->reg_num;
4956 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4957 i.rex |= REX_R;
4958 }
85f10a01 4959 }
252b5132 4960
29b0f896
AM		 4961 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4962 must set it to 3 to indicate this is a register operand
4963 in the regmem field. */
4964 if (!i.mem_operands)
4965 i.rm.mode = 3;
4966 }
252b5132 4967
29b0f896 4968 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 4969 if (i.tm.extension_opcode != None
4970 && !(i.tm.opcode_modifier.drex
4971 || i.tm.opcode_modifier.drexv
4972 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 4973 i.rm.reg = i.tm.extension_opcode;
4974 }
4975 return default_seg;
4976}
252b5132 4977
29b0f896 4978static void
e3bb37b5 4979output_branch (void)
29b0f896
AM		 4980{
4981 char *p;
4982 int code16;
4983 int prefix;
4984 relax_substateT subtype;
4985 symbolS *sym;
4986 offsetT off;
4987
4988 code16 = 0;
4989 if (flag_code == CODE_16BIT)
4990 code16 = CODE16;
4991
4992 prefix = 0;
4993 if (i.prefix[DATA_PREFIX] != 0)
252b5132 4994 {
29b0f896
AM		 4995 prefix = 1;
4996 i.prefixes -= 1;
4997 code16 ^= CODE16;
252b5132 4998 }
29b0f896
AM		 4999 /* Pentium4 branch hints. */
5000 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5001 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5002 {
29b0f896
AM		 5003 prefix++;
5004 i.prefixes--;
5005 }
5006 if (i.prefix[REX_PREFIX] != 0)
5007 {
5008 prefix++;
5009 i.prefixes--;
2f66722d
AM		 5010 }
5011
29b0f896
AM		 5012 if (i.prefixes != 0 && !intel_syntax)
5013 as_warn (_("skipping prefixes on this instruction"));
5014
5015 /* It's always a symbol; End frag & setup for relax.
5016 Make sure there is enough room in this frag for the largest
5017 instruction we may generate in md_convert_frag. This is 2
5018 bytes for the opcode and room for the prefix and largest
5019 displacement. */
5020 frag_grow (prefix + 2 + 4);
5021 /* Prefix and 1 opcode byte go in fr_fix. */
5022 p = frag_more (prefix + 1);
5023 if (i.prefix[DATA_PREFIX] != 0)
5024 *p++ = DATA_PREFIX_OPCODE;
5025 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5026 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5027 *p++ = i.prefix[SEG_PREFIX];
5028 if (i.prefix[REX_PREFIX] != 0)
5029 *p++ = i.prefix[REX_PREFIX];
5030 *p = i.tm.base_opcode;
5031
5032 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5033 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5034 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5035 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5036 else
5037 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5038 subtype |= code16;
3e73aa7c 5039
29b0f896
AM		 5040 sym = i.op[0].disps->X_add_symbol;
5041 off = i.op[0].disps->X_add_number;
3e73aa7c 5042
29b0f896
AM		 5043 if (i.op[0].disps->X_op != O_constant
5044 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5045 {
29b0f896
AM		 5046 /* Handle complex expressions. */
5047 sym = make_expr_symbol (i.op[0].disps);
5048 off = 0;
5049 }
3e73aa7c 5050
29b0f896
AM		 5051 /* 1 possible extra opcode + 4 byte displacement go in var part.
5052 Pass reloc in fr_var. */
5053 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5054}
3e73aa7c 5055
29b0f896 5056static void
e3bb37b5 5057output_jump (void)
29b0f896
AM		 5058{
5059 char *p;
5060 int size;
3e02c1cc 5061 fixS *fixP;
29b0f896 5062
40fb9820 5063 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5064 {
5065 /* This is a loop or jecxz type instruction. */
5066 size = 1;
5067 if (i.prefix[ADDR_PREFIX] != 0)
5068 {
5069 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5070 i.prefixes -= 1;
5071 }
5072 /* Pentium4 branch hints. */
5073 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5074 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5075 {
5076 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5077 i.prefixes--;
3e73aa7c
JH		 5078 }
5079 }
29b0f896
AM		 5080 else
5081 {
5082 int code16;
3e73aa7c 5083
29b0f896
AM		 5084 code16 = 0;
5085 if (flag_code == CODE_16BIT)
5086 code16 = CODE16;
3e73aa7c 5087
29b0f896
AM		 5088 if (i.prefix[DATA_PREFIX] != 0)
5089 {
5090 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5091 i.prefixes -= 1;
5092 code16 ^= CODE16;
5093 }
252b5132 5094
29b0f896
AM		 5095 size = 4;
5096 if (code16)
5097 size = 2;
5098 }
9fcc94b6 5099
29b0f896
AM		 5100 if (i.prefix[REX_PREFIX] != 0)
5101 {
5102 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5103 i.prefixes -= 1;
5104 }
252b5132 5105
29b0f896
AM		 5106 if (i.prefixes != 0 && !intel_syntax)
5107 as_warn (_("skipping prefixes on this instruction"));
e0890092 5108
29b0f896
AM		 5109 p = frag_more (1 + size);
5110 *p++ = i.tm.base_opcode;
e0890092 5111
3e02c1cc
AM		 5112 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5113 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5114
5115 /* All jumps handled here are signed, but don't use a signed limit
5116 check for 32 and 16 bit jumps as we want to allow wrap around at
5117 4G and 64k respectively. */
5118 if (size == 1)
5119 fixP->fx_signed = 1;
29b0f896 5120}
e0890092 5121
29b0f896 5122static void
e3bb37b5 5123output_interseg_jump (void)
29b0f896
AM		 5124{
5125 char *p;
5126 int size;
5127 int prefix;
5128 int code16;
252b5132 5129
29b0f896
AM		 5130 code16 = 0;
5131 if (flag_code == CODE_16BIT)
5132 code16 = CODE16;
a217f122 5133
29b0f896
AM		 5134 prefix = 0;
5135 if (i.prefix[DATA_PREFIX] != 0)
5136 {
5137 prefix = 1;
5138 i.prefixes -= 1;
5139 code16 ^= CODE16;
5140 }
5141 if (i.prefix[REX_PREFIX] != 0)
5142 {
5143 prefix++;
5144 i.prefixes -= 1;
5145 }
252b5132 5146
29b0f896
AM		 5147 size = 4;
5148 if (code16)
5149 size = 2;
252b5132 5150
29b0f896
AM		 5151 if (i.prefixes != 0 && !intel_syntax)
5152 as_warn (_("skipping prefixes on this instruction"));
252b5132 5153
29b0f896
AM		 5154 /* 1 opcode; 2 segment; offset */
5155 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5156
29b0f896
AM		 5157 if (i.prefix[DATA_PREFIX] != 0)
5158 *p++ = DATA_PREFIX_OPCODE;
252b5132 5159
29b0f896
AM		 5160 if (i.prefix[REX_PREFIX] != 0)
5161 *p++ = i.prefix[REX_PREFIX];
252b5132 5162
29b0f896
AM		 5163 *p++ = i.tm.base_opcode;
5164 if (i.op[1].imms->X_op == O_constant)
5165 {
5166 offsetT n = i.op[1].imms->X_add_number;
252b5132 5167
29b0f896
AM		 5168 if (size == 2
5169 && !fits_in_unsigned_word (n)
5170 && !fits_in_signed_word (n))
5171 {
5172 as_bad (_("16-bit jump out of range"));
5173 return;
5174 }
5175 md_number_to_chars (p, n, size);
5176 }
5177 else
5178 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5179 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5180 if (i.op[0].imms->X_op != O_constant)
5181 as_bad (_("can't handle non absolute segment in `%s'"),
5182 i.tm.name);
5183 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5184}
a217f122 5185
29b0f896 5186static void
e3bb37b5 5187output_insn (void)
29b0f896 5188{
2bbd9c25
JJ		 5189 fragS *insn_start_frag;
5190 offsetT insn_start_off;
5191
29b0f896
AM		 5192 /* Tie dwarf2 debug info to the address at the start of the insn.
5193 We can't do this after the insn has been output as the current
5194 frag may have been closed off. eg. by frag_var. */
5195 dwarf2_emit_insn (0);
5196
2bbd9c25
JJ		 5197 insn_start_frag = frag_now;
5198 insn_start_off = frag_now_fix ();
5199
29b0f896 5200 /* Output jumps. */
40fb9820 5201 if (i.tm.opcode_modifier.jump)
29b0f896 5202 output_branch ();
40fb9820
L		 5203 else if (i.tm.opcode_modifier.jumpbyte
5204 || i.tm.opcode_modifier.jumpdword)
29b0f896 5205 output_jump ();
40fb9820 5206 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5207 output_interseg_jump ();
5208 else
5209 {
5210 /* Output normal instructions here. */
5211 char *p;
5212 unsigned char *q;
47465058 5213 unsigned int j;
331d2d0d 5214 unsigned int prefix;
4dffcebc
L		 5215
5216 switch (i.tm.opcode_length)
bc4bd9ab 5217 {
4dffcebc 5218 case 3:
331d2d0d
L		 5219 if (i.tm.base_opcode & 0xff000000)
5220 {
5221 prefix = (i.tm.base_opcode >> 24) & 0xff;
5222 goto check_prefix;
5223 }
4dffcebc
L		 5224 break;
5225 case 2:
5226 if ((i.tm.base_opcode & 0xff0000) != 0)
bc4bd9ab 5227 {
4dffcebc
L		 5228 prefix = (i.tm.base_opcode >> 16) & 0xff;
5229 if (i.tm.cpu_flags.bitfield.cpupadlock)
5230 {
5231check_prefix:
5232 if (prefix != REPE_PREFIX_OPCODE
5233 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5234 add_prefix (prefix);
5235 }
5236 else
bc4bd9ab
MK		 5237 add_prefix (prefix);
5238 }
4dffcebc
L		 5239 break;
5240 case 1:
5241 break;
5242 default:
5243 abort ();
0f10071e 5244 }
252b5132 5245
29b0f896 5246 /* The prefix bytes. */
47465058
L		 5247 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5248 if (*q)
5249 FRAG_APPEND_1_CHAR (*q);
252b5132 5250
29b0f896 5251 /* Now the opcode; be careful about word order here! */
4dffcebc 5252 if (i.tm.opcode_length == 1)
29b0f896
AM		 5253 {
5254 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5255 }
5256 else
5257 {
4dffcebc 5258 switch (i.tm.opcode_length)
331d2d0d 5259 {
4dffcebc 5260 case 3:
331d2d0d
L		 5261 p = frag_more (3);
5262 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5263 break;
5264 case 2:
5265 p = frag_more (2);
5266 break;
5267 default:
5268 abort ();
5269 break;
331d2d0d 5270 }
0f10071e 5271
29b0f896
AM		 5272 /* Put out high byte first: can't use md_number_to_chars! */
5273 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5274 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5275
5276 /* On SSE5, encode the OC1 bit in the DREX field if this
5277 encoding has multiple formats. */
5278 if (i.tm.opcode_modifier.drex
5279 && i.tm.opcode_modifier.drexv
5280 && DREX_OC1 (i.tm.extension_opcode))
5281 *p |= DREX_OC1_MASK;
29b0f896 5282 }
3e73aa7c 5283
29b0f896 5284 /* Now the modrm byte and sib byte (if present). */
40fb9820 5285 if (i.tm.opcode_modifier.modrm)
29b0f896 5286 {
4a3523fa
L		 5287 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5288 | i.rm.reg << 3
5289 | i.rm.mode << 6));
29b0f896
AM		 5290 /* If i.rm.regmem == ESP (4)
5291 && i.rm.mode != (Register mode)
5292 && not 16 bit
5293 ==> need second modrm byte. */
5294 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5295 && i.rm.mode != 3
40fb9820 5296 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5297 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5298 | i.sib.index << 3
5299 | i.sib.scale << 6));
29b0f896 5300 }
3e73aa7c 5301
85f10a01
MM		 5302 /* Write the DREX byte if needed. */
5303 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5304 {
5305 p = frag_more (1);
5306 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5307
5308 /* Encode the OC0 bit if this encoding has multiple
5309 formats. */
5310 if ((i.tm.opcode_modifier.drex
5311 || i.tm.opcode_modifier.drexv)
5312 && DREX_OC0 (i.tm.extension_opcode))
5313 *p |= DREX_OC0_MASK;
5314 }
5315
29b0f896 5316 if (i.disp_operands)
2bbd9c25 5317 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5318
29b0f896 5319 if (i.imm_operands)
2bbd9c25 5320 output_imm (insn_start_frag, insn_start_off);
29b0f896 5321 }
252b5132 5322
29b0f896
AM		 5323#ifdef DEBUG386
5324 if (flag_debug)
5325 {
7b81dfbb 5326 pi ("" /*line*/, &i);
29b0f896
AM		 5327 }
5328#endif /* DEBUG386 */
5329}
252b5132 5330
e205caa7
L		 5331/* Return the size of the displacement operand N. */
5332
5333static int
5334disp_size (unsigned int n)
5335{
5336 int size = 4;
40fb9820
L		 5337 if (i.types[n].bitfield.disp64)
5338 size = 8;
5339 else if (i.types[n].bitfield.disp8)
5340 size = 1;
5341 else if (i.types[n].bitfield.disp16)
5342 size = 2;
e205caa7
L		 5343 return size;
5344}
5345
5346/* Return the size of the immediate operand N. */
5347
5348static int
5349imm_size (unsigned int n)
5350{
5351 int size = 4;
40fb9820
L		 5352 if (i.types[n].bitfield.imm64)
5353 size = 8;
5354 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5355 size = 1;
5356 else if (i.types[n].bitfield.imm16)
5357 size = 2;
e205caa7
L		 5358 return size;
5359}
5360
29b0f896 5361static void
64e74474 5362output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5363{
5364 char *p;
5365 unsigned int n;
252b5132 5366
29b0f896
AM		 5367 for (n = 0; n < i.operands; n++)
5368 {
40fb9820 5369 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5370 {
5371 if (i.op[n].disps->X_op == O_constant)
5372 {
e205caa7 5373 int size = disp_size (n);
29b0f896 5374 offsetT val;
252b5132 5375
29b0f896
AM		 5376 val = offset_in_range (i.op[n].disps->X_add_number,
5377 size);
5378 p = frag_more (size);
5379 md_number_to_chars (p, val, size);
5380 }
5381 else
5382 {
f86103b7 5383 enum bfd_reloc_code_real reloc_type;
e205caa7 5384 int size = disp_size (n);
40fb9820 5385 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5386 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5387
e205caa7 5388 /* We can't have 8 bit displacement here. */
40fb9820 5389 assert (!i.types[n].bitfield.disp8);
e205caa7 5390
29b0f896
AM		 5391 /* The PC relative address is computed relative
5392 to the instruction boundary, so in case immediate
5393 fields follows, we need to adjust the value. */
5394 if (pcrel && i.imm_operands)
5395 {
29b0f896 5396 unsigned int n1;
e205caa7 5397 int sz = 0;
252b5132 5398
29b0f896 5399 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5400 if (operand_type_check (i.types[n1], imm))
252b5132 5401 {
e205caa7
L		 5402 /* Only one immediate is allowed for PC
5403 relative address. */
5404 assert (sz == 0);
5405 sz = imm_size (n1);
5406 i.op[n].disps->X_add_number -= sz;
252b5132 5407 }
29b0f896 5408 /* We should find the immediate. */
e205caa7 5409 assert (sz != 0);
29b0f896 5410 }
520dc8e8 5411
29b0f896 5412 p = frag_more (size);
2bbd9c25 5413 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5414 if (GOT_symbol
2bbd9c25 5415 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5416 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5417 || reloc_type == BFD_RELOC_X86_64_32S
5418 || (reloc_type == BFD_RELOC_64
5419 && object_64bit))
d6ab8113
JB		 5420 && (i.op[n].disps->X_op == O_symbol
5421 || (i.op[n].disps->X_op == O_add
5422 && ((symbol_get_value_expression
5423 (i.op[n].disps->X_op_symbol)->X_op)
5424 == O_subtract))))
5425 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5426 {
5427 offsetT add;
5428
5429 if (insn_start_frag == frag_now)
5430 add = (p - frag_now->fr_literal) - insn_start_off;
5431 else
5432 {
5433 fragS *fr;
5434
5435 add = insn_start_frag->fr_fix - insn_start_off;
5436 for (fr = insn_start_frag->fr_next;
5437 fr && fr != frag_now; fr = fr->fr_next)
5438 add += fr->fr_fix;
5439 add += p - frag_now->fr_literal;
5440 }
5441
4fa24527 5442 if (!object_64bit)
7b81dfbb
AJ		 5443 {
5444 reloc_type = BFD_RELOC_386_GOTPC;
5445 i.op[n].imms->X_add_number += add;
5446 }
5447 else if (reloc_type == BFD_RELOC_64)
5448 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5449 else
7b81dfbb
AJ		 5450 /* Don't do the adjustment for x86-64, as there
5451 the pcrel addressing is relative to the _next_
5452 insn, and that is taken care of in other code. */
d6ab8113 5453 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5454 }
062cd5e7 5455 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5456 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5457 }
5458 }
5459 }
5460}
252b5132 5461
29b0f896 5462static void
64e74474 5463output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5464{
5465 char *p;
5466 unsigned int n;
252b5132 5467
29b0f896
AM		 5468 for (n = 0; n < i.operands; n++)
5469 {
40fb9820 5470 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5471 {
5472 if (i.op[n].imms->X_op == O_constant)
5473 {
e205caa7 5474 int size = imm_size (n);
29b0f896 5475 offsetT val;
b4cac588 5476
29b0f896
AM		 5477 val = offset_in_range (i.op[n].imms->X_add_number,
5478 size);
5479 p = frag_more (size);
5480 md_number_to_chars (p, val, size);
5481 }
5482 else
5483 {
5484 /* Not absolute_section.
5485 Need a 32-bit fixup (don't support 8bit
5486 non-absolute imms). Try to support other
5487 sizes ... */
f86103b7 5488 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5489 int size = imm_size (n);
5490 int sign;
29b0f896 5491
40fb9820 5492 if (i.types[n].bitfield.imm32s
a7d61044 5493 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5494 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5495 sign = 1;
e205caa7
L		 5496 else
5497 sign = 0;
520dc8e8 5498
29b0f896
AM		 5499 p = frag_more (size);
5500 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5501
2bbd9c25
JJ		 5502 /* This is tough to explain. We end up with this one if we
5503 * have operands that look like
5504 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5505 * obtain the absolute address of the GOT, and it is strongly
5506 * preferable from a performance point of view to avoid using
5507 * a runtime relocation for this. The actual sequence of
5508 * instructions often look something like:
5509 *
5510 * call .L66
5511 * .L66:
5512 * popl %ebx
5513 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5514 *
5515 * The call and pop essentially return the absolute address
5516 * of the label .L66 and store it in %ebx. The linker itself
5517 * will ultimately change the first operand of the addl so
5518 * that %ebx points to the GOT, but to keep things simple, the
5519 * .o file must have this operand set so that it generates not
5520 * the absolute address of .L66, but the absolute address of
5521 * itself. This allows the linker itself simply treat a GOTPC
5522 * relocation as asking for a pcrel offset to the GOT to be
5523 * added in, and the addend of the relocation is stored in the
5524 * operand field for the instruction itself.
5525 *
5526 * Our job here is to fix the operand so that it would add
5527 * the correct offset so that %ebx would point to itself. The
5528 * thing that is tricky is that .-.L66 will point to the
5529 * beginning of the instruction, so we need to further modify
5530 * the operand so that it will point to itself. There are
5531 * other cases where you have something like:
5532 *
5533 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5534 *
5535 * and here no correction would be required. Internally in
5536 * the assembler we treat operands of this form as not being
5537 * pcrel since the '.' is explicitly mentioned, and I wonder
5538 * whether it would simplify matters to do it this way. Who
5539 * knows. In earlier versions of the PIC patches, the
5540 * pcrel_adjust field was used to store the correction, but
5541 * since the expression is not pcrel, I felt it would be
5542 * confusing to do it this way. */
5543
d6ab8113 5544 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5545 || reloc_type == BFD_RELOC_X86_64_32S
5546 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 5547 && GOT_symbol
5548 && GOT_symbol == i.op[n].imms->X_add_symbol
5549 && (i.op[n].imms->X_op == O_symbol
5550 || (i.op[n].imms->X_op == O_add
5551 && ((symbol_get_value_expression
5552 (i.op[n].imms->X_op_symbol)->X_op)
5553 == O_subtract))))
5554 {
2bbd9c25
JJ		 5555 offsetT add;
5556
5557 if (insn_start_frag == frag_now)
5558 add = (p - frag_now->fr_literal) - insn_start_off;
5559 else
5560 {
5561 fragS *fr;
5562
5563 add = insn_start_frag->fr_fix - insn_start_off;
5564 for (fr = insn_start_frag->fr_next;
5565 fr && fr != frag_now; fr = fr->fr_next)
5566 add += fr->fr_fix;
5567 add += p - frag_now->fr_literal;
5568 }
5569
4fa24527 5570 if (!object_64bit)
d6ab8113 5571 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 5572 else if (size == 4)
d6ab8113 5573 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 5574 else if (size == 8)
5575 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 5576 i.op[n].imms->X_add_number += add;
29b0f896 5577 }
29b0f896
AM		 5578 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5579 i.op[n].imms, 0, reloc_type);
5580 }
5581 }
5582 }
252b5132
RH		 5583}
5584\f
d182319b
JB		 5585/* x86_cons_fix_new is called via the expression parsing code when a
5586 reloc is needed. We use this hook to get the correct .got reloc. */
5587static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5588static int cons_sign = -1;
5589
5590void
e3bb37b5 5591x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 5592 expressionS *exp)
d182319b
JB		 5593{
5594 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5595
5596 got_reloc = NO_RELOC;
5597
5598#ifdef TE_PE
5599 if (exp->X_op == O_secrel)
5600 {
5601 exp->X_op = O_symbol;
5602 r = BFD_RELOC_32_SECREL;
5603 }
5604#endif
5605
5606 fix_new_exp (frag, off, len, exp, 0, r);
5607}
5608
718ddfc0
JB		 5609#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5610# define lex_got(reloc, adjust, types) NULL
5611#else
f3c180ae
AM		 5612/* Parse operands of the form
5613 <symbol>@GOTOFF+<nnn>
5614 and similar .plt or .got references.
5615
5616 If we find one, set up the correct relocation in RELOC and copy the
5617 input string, minus the `@GOTOFF' into a malloc'd buffer for
5618 parsing by the calling routine. Return this buffer, and if ADJUST
5619 is non-null set it to the length of the string we removed from the
5620 input line. Otherwise return NULL. */
5621static char *
3956db08 5622lex_got (enum bfd_reloc_code_real *reloc,
64e74474 5623 int *adjust,
40fb9820 5624 i386_operand_type *types)
f3c180ae 5625{
7b81dfbb
AJ		 5626 /* Some of the relocations depend on the size of what field is to
5627 be relocated. But in our callers i386_immediate and i386_displacement
5628 we don't yet know the operand size (this will be set by insn
5629 matching). Hence we record the word32 relocation here,
5630 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 5631 static const struct {
5632 const char *str;
4fa24527 5633 const enum bfd_reloc_code_real rel[2];
40fb9820 5634 const i386_operand_type types64;
f3c180ae 5635 } gotrel[] = {
4eed87de
AM		 5636 { "PLTOFF", { 0,
5637 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 5638 OPERAND_TYPE_IMM64 },
4eed87de
AM		 5639 { "PLT", { BFD_RELOC_386_PLT32,
5640 BFD_RELOC_X86_64_PLT32 },
40fb9820 5641 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5642 { "GOTPLT", { 0,
5643 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 5644 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5645 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5646 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 5647 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5648 { "GOTPCREL", { 0,
5649 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 5650 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5651 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5652 BFD_RELOC_X86_64_TLSGD },
40fb9820 5653 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5654 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5655 0 },
40fb9820 5656 OPERAND_TYPE_NONE },
4eed87de
AM		 5657 { "TLSLD", { 0,
5658 BFD_RELOC_X86_64_TLSLD },
40fb9820 5659 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5660 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5661 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 5662 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5663 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5664 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 5665 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5666 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5667 0 },
40fb9820 5668 OPERAND_TYPE_NONE },
4eed87de
AM		 5669 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5670 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 5671
5672 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5673 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5674 0 },
40fb9820 5675 OPERAND_TYPE_NONE },
4eed87de
AM		 5676 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5677 0 },
40fb9820 5678 OPERAND_TYPE_NONE },
4eed87de
AM		 5679 { "GOT", { BFD_RELOC_386_GOT32,
5680 BFD_RELOC_X86_64_GOT32 },
40fb9820 5681 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 5682 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5683 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 5684 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5685 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5686 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 5687 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 5688 };
5689 char *cp;
5690 unsigned int j;
5691
718ddfc0
JB		 5692 if (!IS_ELF)
5693 return NULL;
5694
f3c180ae 5695 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 5696 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 5697 return NULL;
5698
47465058 5699 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 5700 {
5701 int len;
5702
5703 len = strlen (gotrel[j].str);
28f81592 5704 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 5705 {
4fa24527 5706 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 5707 {
28f81592
AM		 5708 int first, second;
5709 char *tmpbuf, *past_reloc;
f3c180ae 5710
4fa24527 5711 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 5712 if (adjust)
5713 *adjust = len;
f3c180ae 5714
3956db08
JB		 5715 if (types)
5716 {
5717 if (flag_code != CODE_64BIT)
40fb9820
L		 5718 {
5719 types->bitfield.imm32 = 1;
5720 types->bitfield.disp32 = 1;
5721 }
3956db08
JB		 5722 else
5723 *types = gotrel[j].types64;
5724 }
5725
f3c180ae
AM		 5726 if (GOT_symbol == NULL)
5727 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5728
28f81592 5729 /* The length of the first part of our input line. */
f3c180ae 5730 first = cp - input_line_pointer;
28f81592
AM		 5731
5732 /* The second part goes from after the reloc token until
67c11a9b 5733 (and including) an end_of_line char or comma. */
28f81592 5734 past_reloc = cp + 1 + len;
67c11a9b
AM		 5735 cp = past_reloc;
5736 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5737 ++cp;
5738 second = cp + 1 - past_reloc;
28f81592
AM		 5739
5740 /* Allocate and copy string. The trailing NUL shouldn't
5741 be necessary, but be safe. */
5742 tmpbuf = xmalloc (first + second + 2);
f3c180ae 5743 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 5744 if (second != 0 && *past_reloc != ' ')
5745 /* Replace the relocation token with ' ', so that
5746 errors like foo@GOTOFF1 will be detected. */
5747 tmpbuf[first++] = ' ';
5748 memcpy (tmpbuf + first, past_reloc, second);
5749 tmpbuf[first + second] = '\0';
f3c180ae
AM		 5750 return tmpbuf;
5751 }
5752
4fa24527
JB		 5753 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5754 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 5755 return NULL;
5756 }
5757 }
5758
5759 /* Might be a symbol version string. Don't as_bad here. */
5760 return NULL;
5761}
5762
f3c180ae 5763void
e3bb37b5 5764x86_cons (expressionS *exp, int size)
f3c180ae 5765{
4fa24527 5766 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 5767 {
5768 /* Handle @GOTOFF and the like in an expression. */
5769 char *save;
5770 char *gotfree_input_line;
5771 int adjust;
5772
5773 save = input_line_pointer;
3956db08 5774 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 5775 if (gotfree_input_line)
5776 input_line_pointer = gotfree_input_line;
5777
5778 expression (exp);
5779
5780 if (gotfree_input_line)
5781 {
5782 /* expression () has merrily parsed up to the end of line,
5783 or a comma - in the wrong buffer. Transfer how far
5784 input_line_pointer has moved to the right buffer. */
5785 input_line_pointer = (save
5786 + (input_line_pointer - gotfree_input_line)
5787 + adjust);
5788 free (gotfree_input_line);
3992d3b7
AM		 5789 if (exp->X_op == O_constant
5790 || exp->X_op == O_absent
5791 || exp->X_op == O_illegal
5792 || exp->X_op == O_register
5793 || exp->X_op == O_big)
5794 {
5795 char c = *input_line_pointer;
5796 *input_line_pointer = 0;
5797 as_bad (_("missing or invalid expression `%s'"), save);
5798 *input_line_pointer = c;
5799 }
f3c180ae
AM		 5800 }
5801 }
5802 else
5803 expression (exp);
5804}
5805#endif
5806
d182319b 5807static void signed_cons (int size)
6482c264 5808{
d182319b
JB		 5809 if (flag_code == CODE_64BIT)
5810 cons_sign = 1;
5811 cons (size);
5812 cons_sign = -1;
6482c264
NC		 5813}
5814
d182319b 5815#ifdef TE_PE
6482c264
NC		 5816static void
5817pe_directive_secrel (dummy)
5818 int dummy ATTRIBUTE_UNUSED;
5819{
5820 expressionS exp;
5821
5822 do
5823 {
5824 expression (&exp);
5825 if (exp.X_op == O_symbol)
5826 exp.X_op = O_secrel;
5827
5828 emit_expr (&exp, 4);
5829 }
5830 while (*input_line_pointer++ == ',');
5831
5832 input_line_pointer--;
5833 demand_empty_rest_of_line ();
5834}
6482c264
NC		 5835#endif
5836
252b5132 5837static int
70e41ade 5838i386_immediate (char *imm_start)
252b5132
RH		 5839{
5840 char *save_input_line_pointer;
f3c180ae 5841 char *gotfree_input_line;
252b5132 5842 segT exp_seg = 0;
47926f60 5843 expressionS *exp;
40fb9820
L		 5844 i386_operand_type types;
5845
c6fb90c8 5846 UINTS_SET (types, ~0);
252b5132
RH		 5847
5848 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5849 {
31b2323c
L		 5850 as_bad (_("at most %d immediate operands are allowed"),
5851 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 5852 return 0;
5853 }
5854
5855 exp = &im_expressions[i.imm_operands++];
520dc8e8 5856 i.op[this_operand].imms = exp;
252b5132
RH		 5857
5858 if (is_space_char (*imm_start))
5859 ++imm_start;
5860
5861 save_input_line_pointer = input_line_pointer;
5862 input_line_pointer = imm_start;
5863
3956db08 5864 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5865 if (gotfree_input_line)
5866 input_line_pointer = gotfree_input_line;
252b5132
RH		 5867
5868 exp_seg = expression (exp);
5869
83183c0c 5870 SKIP_WHITESPACE ();
252b5132 5871 if (*input_line_pointer)
f3c180ae 5872 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 5873
5874 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 5875 if (gotfree_input_line)
5876 free (gotfree_input_line);
252b5132 5877
3992d3b7
AM		 5878 if (exp->X_op == O_absent
5879 || exp->X_op == O_illegal
5880 || exp->X_op == O_big
5881 || (gotfree_input_line
5882 && (exp->X_op == O_constant
5883 || exp->X_op == O_register)))
252b5132 5884 {
3992d3b7 5885 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 5886 imm_start);
3992d3b7 5887 return 0;
252b5132 5888 }
3e73aa7c 5889 else if (exp->X_op == O_constant)
252b5132 5890 {
47926f60 5891 /* Size it properly later. */
40fb9820 5892 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 5893 /* If BFD64, sign extend val. */
4eed87de
AM		 5894 if (!use_rela_relocations
5895 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5896 exp->X_add_number
5897 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 5898 }
4c63da97 5899#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 5900 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 5901 && exp_seg != absolute_section
47926f60 5902 && exp_seg != text_section
24eab124
AM		 5903 && exp_seg != data_section
5904 && exp_seg != bss_section
5905 && exp_seg != undefined_section
f86103b7 5906 && !bfd_is_com_section (exp_seg))
252b5132 5907 {
d0b47220 5908 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 5909 return 0;
5910 }
5911#endif
bb8f5920
L		 5912 else if (!intel_syntax && exp->X_op == O_register)
5913 {
5914 as_bad (_("illegal immediate register operand %s"), imm_start);
5915 return 0;
5916 }
252b5132
RH		 5917 else
5918 {
5919 /* This is an address. The size of the address will be
24eab124 5920 determined later, depending on destination register,
3e73aa7c 5921 suffix, or the default for the section. */
40fb9820
L		 5922 i.types[this_operand].bitfield.imm8 = 1;
5923 i.types[this_operand].bitfield.imm16 = 1;
5924 i.types[this_operand].bitfield.imm32 = 1;
5925 i.types[this_operand].bitfield.imm32s = 1;
5926 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 5927 i.types[this_operand] = operand_type_and (i.types[this_operand],
5928 types);
252b5132
RH		 5929 }
5930
5931 return 1;
5932}
5933
551c1ca1 5934static char *
e3bb37b5 5935i386_scale (char *scale)
252b5132 5936{
551c1ca1
AM		 5937 offsetT val;
5938 char *save = input_line_pointer;
252b5132 5939
551c1ca1
AM		 5940 input_line_pointer = scale;
5941 val = get_absolute_expression ();
5942
5943 switch (val)
252b5132 5944 {
551c1ca1 5945 case 1:
252b5132
RH		 5946 i.log2_scale_factor = 0;
5947 break;
551c1ca1 5948 case 2:
252b5132
RH		 5949 i.log2_scale_factor = 1;
5950 break;
551c1ca1 5951 case 4:
252b5132
RH		 5952 i.log2_scale_factor = 2;
5953 break;
551c1ca1 5954 case 8:
252b5132
RH		 5955 i.log2_scale_factor = 3;
5956 break;
5957 default:
a724f0f4
JB		 5958 {
5959 char sep = *input_line_pointer;
5960
5961 *input_line_pointer = '\0';
5962 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5963 scale);
5964 *input_line_pointer = sep;
5965 input_line_pointer = save;
5966 return NULL;
5967 }
252b5132 5968 }
29b0f896 5969 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 5970 {
5971 as_warn (_("scale factor of %d without an index register"),
24eab124 5972 1 << i.log2_scale_factor);
252b5132 5973 i.log2_scale_factor = 0;
252b5132 5974 }
551c1ca1
AM		 5975 scale = input_line_pointer;
5976 input_line_pointer = save;
5977 return scale;
252b5132
RH		 5978}
5979
252b5132 5980static int
e3bb37b5 5981i386_displacement (char *disp_start, char *disp_end)
252b5132 5982{
29b0f896 5983 expressionS *exp;
252b5132
RH		 5984 segT exp_seg = 0;
5985 char *save_input_line_pointer;
f3c180ae 5986 char *gotfree_input_line;
40fb9820
L		 5987 int override;
5988 i386_operand_type bigdisp, types = anydisp;
3992d3b7 5989 int ret;
252b5132 5990
31b2323c
L		 5991 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5992 {
5993 as_bad (_("at most %d displacement operands are allowed"),
5994 MAX_MEMORY_OPERANDS);
5995 return 0;
5996 }
5997
c6fb90c8 5998 UINTS_CLEAR (bigdisp);
40fb9820
L		 5999 if ((i.types[this_operand].bitfield.jumpabsolute)
6000 || (!current_templates->start->opcode_modifier.jump
6001 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6002 {
40fb9820 6003 bigdisp.bitfield.disp32 = 1;
e05278af 6004 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6005 if (flag_code == CODE_64BIT)
6006 {
6007 if (!override)
6008 {
6009 bigdisp.bitfield.disp32s = 1;
6010 bigdisp.bitfield.disp64 = 1;
6011 }
6012 }
6013 else if ((flag_code == CODE_16BIT) ^ override)
6014 {
6015 bigdisp.bitfield.disp32 = 0;
6016 bigdisp.bitfield.disp16 = 1;
6017 }
e05278af
JB		 6018 }
6019 else
6020 {
6021 /* For PC-relative branches, the width of the displacement
6022 is dependent upon data size, not address size. */
e05278af 6023 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6024 if (flag_code == CODE_64BIT)
6025 {
6026 if (override || i.suffix == WORD_MNEM_SUFFIX)
6027 bigdisp.bitfield.disp16 = 1;
6028 else
6029 {
6030 bigdisp.bitfield.disp32 = 1;
6031 bigdisp.bitfield.disp32s = 1;
6032 }
6033 }
6034 else
e05278af
JB		 6035 {
6036 if (!override)
6037 override = (i.suffix == (flag_code != CODE_16BIT
6038 ? WORD_MNEM_SUFFIX
6039 : LONG_MNEM_SUFFIX));
40fb9820
L		 6040 bigdisp.bitfield.disp32 = 1;
6041 if ((flag_code == CODE_16BIT) ^ override)
6042 {
6043 bigdisp.bitfield.disp32 = 0;
6044 bigdisp.bitfield.disp16 = 1;
6045 }
e05278af 6046 }
e05278af 6047 }
c6fb90c8
L		 6048 i.types[this_operand] = operand_type_or (i.types[this_operand],
6049 bigdisp);
252b5132
RH		 6050
6051 exp = &disp_expressions[i.disp_operands];
520dc8e8 6052 i.op[this_operand].disps = exp;
252b5132
RH		 6053 i.disp_operands++;
6054 save_input_line_pointer = input_line_pointer;
6055 input_line_pointer = disp_start;
6056 END_STRING_AND_SAVE (disp_end);
6057
6058#ifndef GCC_ASM_O_HACK
6059#define GCC_ASM_O_HACK 0
6060#endif
6061#if GCC_ASM_O_HACK
6062 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6063 if (i.types[this_operand].bitfield.baseIndex
24eab124 6064 && displacement_string_end[-1] == '+')
252b5132
RH		 6065 {
6066 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6067 constraint within gcc asm statements.
6068 For instance:
6069
6070 #define _set_tssldt_desc(n,addr,limit,type) \
6071 __asm__ __volatile__ ( \
6072 "movw %w2,%0\n\t" \
6073 "movw %w1,2+%0\n\t" \
6074 "rorl $16,%1\n\t" \
6075 "movb %b1,4+%0\n\t" \
6076 "movb %4,5+%0\n\t" \
6077 "movb $0,6+%0\n\t" \
6078 "movb %h1,7+%0\n\t" \
6079 "rorl $16,%1" \
6080 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6081
6082 This works great except that the output assembler ends
6083 up looking a bit weird if it turns out that there is
6084 no offset. You end up producing code that looks like:
6085
6086 #APP
6087 movw $235,(%eax)
6088 movw %dx,2+(%eax)
6089 rorl $16,%edx
6090 movb %dl,4+(%eax)
6091 movb $137,5+(%eax)
6092 movb $0,6+(%eax)
6093 movb %dh,7+(%eax)
6094 rorl $16,%edx
6095 #NO_APP
6096
47926f60 6097 So here we provide the missing zero. */
24eab124
AM		 6098
6099 *displacement_string_end = '0';
252b5132
RH		 6100 }
6101#endif
3956db08 6102 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6103 if (gotfree_input_line)
6104 input_line_pointer = gotfree_input_line;
252b5132 6105
24eab124 6106 exp_seg = expression (exp);
252b5132 6107
636c26b0
AM		 6108 SKIP_WHITESPACE ();
6109 if (*input_line_pointer)
6110 as_bad (_("junk `%s' after expression"), input_line_pointer);
6111#if GCC_ASM_O_HACK
6112 RESTORE_END_STRING (disp_end + 1);
6113#endif
636c26b0 6114 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 6115 if (gotfree_input_line)
6116 free (gotfree_input_line);
3992d3b7 6117 ret = 1;
636c26b0 6118
24eab124
AM		 6119 /* We do this to make sure that the section symbol is in
6120 the symbol table. We will ultimately change the relocation
47926f60 6121 to be relative to the beginning of the section. */
1ae12ab7 6122 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6123 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6124 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6125 {
636c26b0 6126 if (exp->X_op != O_symbol)
3992d3b7 6127 goto inv_disp;
636c26b0 6128
e5cb08ac 6129 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6130 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6131 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6132 exp->X_op = O_subtract;
6133 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6134 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6135 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6136 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6137 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6138 else
29b0f896 6139 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6140 }
252b5132 6141
3992d3b7
AM		 6142 else if (exp->X_op == O_absent
6143 || exp->X_op == O_illegal
6144 || exp->X_op == O_big
6145 || (gotfree_input_line
6146 && (exp->X_op == O_constant
6147 || exp->X_op == O_register)))
2daf4fd8 6148 {
3992d3b7
AM		 6149 inv_disp:
6150 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6151 disp_start);
3992d3b7 6152 ret = 0;
2daf4fd8
AM		 6153 }
6154
4c63da97 6155#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6156 else if (exp->X_op != O_constant
6157 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6158 && exp_seg != absolute_section
6159 && exp_seg != text_section
6160 && exp_seg != data_section
6161 && exp_seg != bss_section
6162 && exp_seg != undefined_section
6163 && !bfd_is_com_section (exp_seg))
24eab124 6164 {
d0b47220 6165 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6166 ret = 0;
24eab124 6167 }
252b5132 6168#endif
3956db08 6169
3992d3b7
AM		 6170 RESTORE_END_STRING (disp_end);
6171
40fb9820
L		 6172 /* Check if this is a displacement only operand. */
6173 bigdisp = i.types[this_operand];
6174 bigdisp.bitfield.disp8 = 0;
6175 bigdisp.bitfield.disp16 = 0;
6176 bigdisp.bitfield.disp32 = 0;
6177 bigdisp.bitfield.disp32s = 0;
6178 bigdisp.bitfield.disp64 = 0;
c6fb90c8
L		 6179 if (UINTS_ALL_ZERO (bigdisp))
6180 i.types[this_operand] = operand_type_and (i.types[this_operand],
6181 types);
3956db08 6182
3992d3b7 6183 return ret;
252b5132
RH		 6184}
6185
eecb386c 6186/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6187 Return 1 on success, 0 on a failure. */
6188
252b5132 6189static int
e3bb37b5 6190i386_index_check (const char *operand_string)
252b5132 6191{
3e73aa7c 6192 int ok;
24eab124 6193#if INFER_ADDR_PREFIX
eecb386c
AM		 6194 int fudged = 0;
6195
24eab124
AM		 6196 tryprefix:
6197#endif
3e73aa7c 6198 ok = 1;
75178d9d 6199 if (flag_code == CODE_64BIT)
64e74474 6200 {
64e74474 6201 if ((i.base_reg
40fb9820
L		 6202 && ((i.prefix[ADDR_PREFIX] == 0
6203 && !i.base_reg->reg_type.bitfield.reg64)
6204 || (i.prefix[ADDR_PREFIX]
6205 && !i.base_reg->reg_type.bitfield.reg32))
6206 && (i.index_reg
9a04903e
JB		 6207 || i.base_reg->reg_num !=
6208 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6209 || (i.index_reg
40fb9820
L		 6210 && (!i.index_reg->reg_type.bitfield.baseindex
6211 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6212 && i.index_reg->reg_num != RegRiz
6213 && !i.index_reg->reg_type.bitfield.reg64
6214 )
40fb9820 6215 || (i.prefix[ADDR_PREFIX]
db51cc60 6216 && i.index_reg->reg_num != RegEiz
40fb9820 6217 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6218 ok = 0;
3e73aa7c
JH		 6219 }
6220 else
6221 {
6222 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6223 {
6224 /* 16bit checks. */
6225 if ((i.base_reg
40fb9820
L		 6226 && (!i.base_reg->reg_type.bitfield.reg16
6227 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6228 || (i.index_reg
40fb9820
L		 6229 && (!i.index_reg->reg_type.bitfield.reg16
6230 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6231 || !(i.base_reg
6232 && i.base_reg->reg_num < 6
6233 && i.index_reg->reg_num >= 6
6234 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6235 ok = 0;
6236 }
6237 else
e5cb08ac 6238 {
3e73aa7c
JH		 6239 /* 32bit checks. */
6240 if ((i.base_reg
40fb9820 6241 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6242 || (i.index_reg
db51cc60
L		 6243 && ((!i.index_reg->reg_type.bitfield.reg32
6244 && i.index_reg->reg_num != RegEiz)
40fb9820 6245 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6246 ok = 0;
3e73aa7c
JH		 6247 }
6248 }
6249 if (!ok)
24eab124
AM		 6250 {
6251#if INFER_ADDR_PREFIX
20f0a1fc 6252 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 6253 {
6254 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6255 i.prefixes += 1;
b23bac36
AM		 6256 /* Change the size of any displacement too. At most one of
6257 Disp16 or Disp32 is set.
6258 FIXME. There doesn't seem to be any real need for separate
6259 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6260 Removing them would probably clean up the code quite a lot. */
4eed87de 6261 if (flag_code != CODE_64BIT
40fb9820
L		 6262 && (i.types[this_operand].bitfield.disp16
6263 || i.types[this_operand].bitfield.disp32))
6264 i.types[this_operand]
c6fb90c8 6265 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6266 fudged = 1;
24eab124
AM		 6267 goto tryprefix;
6268 }
eecb386c
AM		 6269 if (fudged)
6270 as_bad (_("`%s' is not a valid base/index expression"),
6271 operand_string);
6272 else
c388dee8 6273#endif
eecb386c
AM		 6274 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6275 operand_string,
3e73aa7c 6276 flag_code_names[flag_code]);
24eab124 6277 }
20f0a1fc 6278 return ok;
24eab124 6279}
252b5132 6280
252b5132 6281/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 6282 on error. */
252b5132 6283
252b5132 6284static int
a7619375 6285i386_att_operand (char *operand_string)
252b5132 6286{
af6bdddf
AM		 6287 const reg_entry *r;
6288 char *end_op;
24eab124 6289 char *op_string = operand_string;
252b5132 6290
24eab124 6291 if (is_space_char (*op_string))
252b5132
RH		 6292 ++op_string;
6293
24eab124 6294 /* We check for an absolute prefix (differentiating,
47926f60 6295 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6296 if (*op_string == ABSOLUTE_PREFIX)
6297 {
6298 ++op_string;
6299 if (is_space_char (*op_string))
6300 ++op_string;
40fb9820 6301 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6302 }
252b5132 6303
47926f60 6304 /* Check if operand is a register. */
4d1bb795 6305 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6306 {
40fb9820
L		 6307 i386_operand_type temp;
6308
24eab124
AM		 6309 /* Check for a segment override by searching for ':' after a
6310 segment register. */
6311 op_string = end_op;
6312 if (is_space_char (*op_string))
6313 ++op_string;
40fb9820
L		 6314 if (*op_string == ':'
6315 && (r->reg_type.bitfield.sreg2
6316 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6317 {
6318 switch (r->reg_num)
6319 {
6320 case 0:
6321 i.seg[i.mem_operands] = &es;
6322 break;
6323 case 1:
6324 i.seg[i.mem_operands] = &cs;
6325 break;
6326 case 2:
6327 i.seg[i.mem_operands] = &ss;
6328 break;
6329 case 3:
6330 i.seg[i.mem_operands] = &ds;
6331 break;
6332 case 4:
6333 i.seg[i.mem_operands] = &fs;
6334 break;
6335 case 5:
6336 i.seg[i.mem_operands] = &gs;
6337 break;
6338 }
252b5132 6339
24eab124 6340 /* Skip the ':' and whitespace. */
252b5132
RH		 6341 ++op_string;
6342 if (is_space_char (*op_string))
24eab124 6343 ++op_string;
252b5132 6344
24eab124
AM		 6345 if (!is_digit_char (*op_string)
6346 && !is_identifier_char (*op_string)
6347 && *op_string != '('
6348 && *op_string != ABSOLUTE_PREFIX)
6349 {
6350 as_bad (_("bad memory operand `%s'"), op_string);
6351 return 0;
6352 }
47926f60 6353 /* Handle case of %es:*foo. */
24eab124
AM		 6354 if (*op_string == ABSOLUTE_PREFIX)
6355 {
6356 ++op_string;
6357 if (is_space_char (*op_string))
6358 ++op_string;
40fb9820 6359 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6360 }
6361 goto do_memory_reference;
6362 }
6363 if (*op_string)
6364 {
d0b47220 6365 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6366 return 0;
6367 }
40fb9820
L		 6368 temp = r->reg_type;
6369 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6370 i.types[this_operand] = operand_type_or (i.types[this_operand],
6371 temp);
7d5e4556 6372 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 6373 i.op[this_operand].regs = r;
24eab124
AM		 6374 i.reg_operands++;
6375 }
af6bdddf
AM		 6376 else if (*op_string == REGISTER_PREFIX)
6377 {
6378 as_bad (_("bad register name `%s'"), op_string);
6379 return 0;
6380 }
24eab124 6381 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6382 {
24eab124 6383 ++op_string;
40fb9820 6384 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6385 {
d0b47220 6386 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6387 return 0;
6388 }
6389 if (!i386_immediate (op_string))
6390 return 0;
6391 }
6392 else if (is_digit_char (*op_string)
6393 || is_identifier_char (*op_string)
e5cb08ac 6394 || *op_string == '(')
24eab124 6395 {
47926f60 6396 /* This is a memory reference of some sort. */
af6bdddf 6397 char *base_string;
252b5132 6398
47926f60 6399 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 6400 char *displacement_string_start;
6401 char *displacement_string_end;
252b5132 6402
24eab124 6403 do_memory_reference:
24eab124 6404 if ((i.mem_operands == 1
40fb9820 6405 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 6406 || i.mem_operands == 2)
6407 {
6408 as_bad (_("too many memory references for `%s'"),
6409 current_templates->start->name);
6410 return 0;
6411 }
252b5132 6412
24eab124
AM		 6413 /* Check for base index form. We detect the base index form by
6414 looking for an ')' at the end of the operand, searching
6415 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6416 after the '('. */
af6bdddf 6417 base_string = op_string + strlen (op_string);
c3332e24 6418
af6bdddf
AM		 6419 --base_string;
6420 if (is_space_char (*base_string))
6421 --base_string;
252b5132 6422
47926f60 6423 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 6424 displacement_string_start = op_string;
6425 displacement_string_end = base_string + 1;
252b5132 6426
24eab124
AM		 6427 if (*base_string == ')')
6428 {
af6bdddf 6429 char *temp_string;
24eab124
AM		 6430 unsigned int parens_balanced = 1;
6431 /* We've already checked that the number of left & right ()'s are
47926f60 6432 equal, so this loop will not be infinite. */
24eab124
AM		 6433 do
6434 {
6435 base_string--;
6436 if (*base_string == ')')
6437 parens_balanced++;
6438 if (*base_string == '(')
6439 parens_balanced--;
6440 }
6441 while (parens_balanced);
c3332e24 6442
af6bdddf 6443 temp_string = base_string;
c3332e24 6444
24eab124 6445 /* Skip past '(' and whitespace. */
252b5132
RH		 6446 ++base_string;
6447 if (is_space_char (*base_string))
24eab124 6448 ++base_string;
252b5132 6449
af6bdddf 6450 if (*base_string == ','
4eed87de
AM		 6451 || ((i.base_reg = parse_register (base_string, &end_op))
6452 != NULL))
252b5132 6453 {
af6bdddf 6454 displacement_string_end = temp_string;
252b5132 6455
40fb9820 6456 i.types[this_operand].bitfield.baseindex = 1;
252b5132 6457
af6bdddf 6458 if (i.base_reg)
24eab124 6459 {
24eab124
AM		 6460 base_string = end_op;
6461 if (is_space_char (*base_string))
6462 ++base_string;
af6bdddf
AM		 6463 }
6464
6465 /* There may be an index reg or scale factor here. */
6466 if (*base_string == ',')
6467 {
6468 ++base_string;
6469 if (is_space_char (*base_string))
6470 ++base_string;
6471
4eed87de
AM		 6472 if ((i.index_reg = parse_register (base_string, &end_op))
6473 != NULL)
24eab124 6474 {
af6bdddf 6475 base_string = end_op;
24eab124
AM		 6476 if (is_space_char (*base_string))
6477 ++base_string;
af6bdddf
AM		 6478 if (*base_string == ',')
6479 {
6480 ++base_string;
6481 if (is_space_char (*base_string))
6482 ++base_string;
6483 }
e5cb08ac 6484 else if (*base_string != ')')
af6bdddf 6485 {
4eed87de
AM		 6486 as_bad (_("expecting `,' or `)' "
6487 "after index register in `%s'"),
af6bdddf
AM		 6488 operand_string);
6489 return 0;
6490 }
24eab124 6491 }
af6bdddf 6492 else if (*base_string == REGISTER_PREFIX)
24eab124 6493 {
af6bdddf 6494 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 6495 return 0;
6496 }
252b5132 6497
47926f60 6498 /* Check for scale factor. */
551c1ca1 6499 if (*base_string != ')')
af6bdddf 6500 {
551c1ca1
AM		 6501 char *end_scale = i386_scale (base_string);
6502
6503 if (!end_scale)
af6bdddf 6504 return 0;
24eab124 6505
551c1ca1 6506 base_string = end_scale;
af6bdddf
AM		 6507 if (is_space_char (*base_string))
6508 ++base_string;
6509 if (*base_string != ')')
6510 {
4eed87de
AM		 6511 as_bad (_("expecting `)' "
6512 "after scale factor in `%s'"),
af6bdddf
AM		 6513 operand_string);
6514 return 0;
6515 }
6516 }
6517 else if (!i.index_reg)
24eab124 6518 {
4eed87de
AM		 6519 as_bad (_("expecting index register or scale factor "
6520 "after `,'; got '%c'"),
af6bdddf 6521 *base_string);
24eab124
AM		 6522 return 0;
6523 }
6524 }
af6bdddf 6525 else if (*base_string != ')')
24eab124 6526 {
4eed87de
AM		 6527 as_bad (_("expecting `,' or `)' "
6528 "after base register in `%s'"),
af6bdddf 6529 operand_string);
24eab124
AM		 6530 return 0;
6531 }
c3332e24 6532 }
af6bdddf 6533 else if (*base_string == REGISTER_PREFIX)
c3332e24 6534 {
af6bdddf 6535 as_bad (_("bad register name `%s'"), base_string);
24eab124 6536 return 0;
c3332e24 6537 }
24eab124
AM		 6538 }
6539
6540 /* If there's an expression beginning the operand, parse it,
6541 assuming displacement_string_start and
6542 displacement_string_end are meaningful. */
6543 if (displacement_string_start != displacement_string_end)
6544 {
6545 if (!i386_displacement (displacement_string_start,
6546 displacement_string_end))
6547 return 0;
6548 }
6549
6550 /* Special case for (%dx) while doing input/output op. */
6551 if (i.base_reg
c6fb90c8 6552 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
24eab124
AM		 6553 && i.index_reg == 0
6554 && i.log2_scale_factor == 0
6555 && i.seg[i.mem_operands] == 0
40fb9820 6556 && !operand_type_check (i.types[this_operand], disp))
24eab124 6557 {
c6fb90c8 6558 UINTS_CLEAR (i.types[this_operand]);
40fb9820 6559 i.types[this_operand].bitfield.inoutportreg = 1;
24eab124
AM		 6560 return 1;
6561 }
6562
eecb386c
AM		 6563 if (i386_index_check (operand_string) == 0)
6564 return 0;
5c07affc 6565 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 6566 i.mem_operands++;
6567 }
6568 else
ce8a8b2f
AM		 6569 {
6570 /* It's not a memory operand; argh! */
24eab124
AM		 6571 as_bad (_("invalid char %s beginning operand %d `%s'"),
6572 output_invalid (*op_string),
6573 this_operand + 1,
6574 op_string);
6575 return 0;
6576 }
47926f60 6577 return 1; /* Normal return. */
252b5132
RH		 6578}
6579\f
ee7fcc42
AM		 6580/* md_estimate_size_before_relax()
6581
6582 Called just before relax() for rs_machine_dependent frags. The x86
6583 assembler uses these frags to handle variable size jump
6584 instructions.
6585
6586 Any symbol that is now undefined will not become defined.
6587 Return the correct fr_subtype in the frag.
6588 Return the initial "guess for variable size of frag" to caller.
6589 The guess is actually the growth beyond the fixed part. Whatever
6590 we do to grow the fixed or variable part contributes to our
6591 returned value. */
6592
252b5132
RH		 6593int
6594md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 6595 fragS *fragP;
6596 segT segment;
252b5132 6597{
252b5132 6598 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 6599 check for un-relaxable symbols. On an ELF system, we can't relax
6600 an externally visible symbol, because it may be overridden by a
6601 shared library. */
6602 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 6603#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6604 || (IS_ELF
31312f95
AM		 6605 && (S_IS_EXTERNAL (fragP->fr_symbol)
6606 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 6607#endif
6608 )
252b5132 6609 {
b98ef147
AM		 6610 /* Symbol is undefined in this segment, or we need to keep a
6611 reloc so that weak symbols can be overridden. */
6612 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 6613 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 6614 unsigned char *opcode;
6615 int old_fr_fix;
f6af82bd 6616
ee7fcc42
AM		 6617 if (fragP->fr_var != NO_RELOC)
6618 reloc_type = fragP->fr_var;
b98ef147 6619 else if (size == 2)
f6af82bd
AM		 6620 reloc_type = BFD_RELOC_16_PCREL;
6621 else
6622 reloc_type = BFD_RELOC_32_PCREL;
252b5132 6623
ee7fcc42
AM		 6624 old_fr_fix = fragP->fr_fix;
6625 opcode = (unsigned char *) fragP->fr_opcode;
6626
fddf5b5b 6627 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 6628 {
fddf5b5b
AM		 6629 case UNCOND_JUMP:
6630 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 6631 opcode[0] = 0xe9;
252b5132 6632 fragP->fr_fix += size;
062cd5e7
AS		 6633 fix_new (fragP, old_fr_fix, size,
6634 fragP->fr_symbol,
6635 fragP->fr_offset, 1,
6636 reloc_type);
252b5132
RH		 6637 break;
6638
fddf5b5b 6639 case COND_JUMP86:
412167cb
AM		 6640 if (size == 2
6641 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 6642 {
6643 /* Negate the condition, and branch past an
6644 unconditional jump. */
6645 opcode[0] ^= 1;
6646 opcode[1] = 3;
6647 /* Insert an unconditional jump. */
6648 opcode[2] = 0xe9;
6649 /* We added two extra opcode bytes, and have a two byte
6650 offset. */
6651 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 6652 fix_new (fragP, old_fr_fix + 2, 2,
6653 fragP->fr_symbol,
6654 fragP->fr_offset, 1,
6655 reloc_type);
fddf5b5b
AM		 6656 break;
6657 }
6658 /* Fall through. */
6659
6660 case COND_JUMP:
412167cb
AM		 6661 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6662 {
3e02c1cc
AM		 6663 fixS *fixP;
6664
412167cb 6665 fragP->fr_fix += 1;
3e02c1cc
AM		 6666 fixP = fix_new (fragP, old_fr_fix, 1,
6667 fragP->fr_symbol,
6668 fragP->fr_offset, 1,
6669 BFD_RELOC_8_PCREL);
6670 fixP->fx_signed = 1;
412167cb
AM		 6671 break;
6672 }
93c2a809 6673
24eab124 6674 /* This changes the byte-displacement jump 0x7N
fddf5b5b 6675 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 6676 opcode[1] = opcode[0] + 0x10;
f6af82bd 6677 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 6678 /* We've added an opcode byte. */
6679 fragP->fr_fix += 1 + size;
062cd5e7
AS		 6680 fix_new (fragP, old_fr_fix + 1, size,
6681 fragP->fr_symbol,
6682 fragP->fr_offset, 1,
6683 reloc_type);
252b5132 6684 break;
fddf5b5b
AM		 6685
6686 default:
6687 BAD_CASE (fragP->fr_subtype);
6688 break;
252b5132
RH		 6689 }
6690 frag_wane (fragP);
ee7fcc42 6691 return fragP->fr_fix - old_fr_fix;
252b5132 6692 }
93c2a809 6693
93c2a809
AM		 6694 /* Guess size depending on current relax state. Initially the relax
6695 state will correspond to a short jump and we return 1, because
6696 the variable part of the frag (the branch offset) is one byte
6697 long. However, we can relax a section more than once and in that
6698 case we must either set fr_subtype back to the unrelaxed state,
6699 or return the value for the appropriate branch. */
6700 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 6701}
6702
47926f60
KH		 6703/* Called after relax() is finished.
6704
6705 In: Address of frag.
6706 fr_type == rs_machine_dependent.
6707 fr_subtype is what the address relaxed to.
6708
6709 Out: Any fixSs and constants are set up.
6710 Caller will turn frag into a ".space 0". */
6711
252b5132
RH		 6712void
6713md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 6714 bfd *abfd ATTRIBUTE_UNUSED;
6715 segT sec ATTRIBUTE_UNUSED;
29b0f896 6716 fragS *fragP;
252b5132 6717{
29b0f896 6718 unsigned char *opcode;
252b5132 6719 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 6720 offsetT target_address;
6721 offsetT opcode_address;
252b5132 6722 unsigned int extension = 0;
847f7ad4 6723 offsetT displacement_from_opcode_start;
252b5132
RH		 6724
6725 opcode = (unsigned char *) fragP->fr_opcode;
6726
47926f60 6727 /* Address we want to reach in file space. */
252b5132 6728 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 6729
47926f60 6730 /* Address opcode resides at in file space. */
252b5132
RH		 6731 opcode_address = fragP->fr_address + fragP->fr_fix;
6732
47926f60 6733 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 6734 displacement_from_opcode_start = target_address - opcode_address;
6735
fddf5b5b 6736 if ((fragP->fr_subtype & BIG) == 0)
252b5132 6737 {
47926f60
KH		 6738 /* Don't have to change opcode. */
6739 extension = 1; /* 1 opcode + 1 displacement */
252b5132 6740 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 6741 }
6742 else
6743 {
6744 if (no_cond_jump_promotion
6745 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 6746 as_warn_where (fragP->fr_file, fragP->fr_line,
6747 _("long jump required"));
252b5132 6748
fddf5b5b
AM		 6749 switch (fragP->fr_subtype)
6750 {
6751 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6752 extension = 4; /* 1 opcode + 4 displacement */
6753 opcode[0] = 0xe9;
6754 where_to_put_displacement = &opcode[1];
6755 break;
252b5132 6756
fddf5b5b
AM		 6757 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6758 extension = 2; /* 1 opcode + 2 displacement */
6759 opcode[0] = 0xe9;
6760 where_to_put_displacement = &opcode[1];
6761 break;
252b5132 6762
fddf5b5b
AM		 6763 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6764 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6765 extension = 5; /* 2 opcode + 4 displacement */
6766 opcode[1] = opcode[0] + 0x10;
6767 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6768 where_to_put_displacement = &opcode[2];
6769 break;
252b5132 6770
fddf5b5b
AM		 6771 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6772 extension = 3; /* 2 opcode + 2 displacement */
6773 opcode[1] = opcode[0] + 0x10;
6774 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6775 where_to_put_displacement = &opcode[2];
6776 break;
252b5132 6777
fddf5b5b
AM		 6778 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6779 extension = 4;
6780 opcode[0] ^= 1;
6781 opcode[1] = 3;
6782 opcode[2] = 0xe9;
6783 where_to_put_displacement = &opcode[3];
6784 break;
6785
6786 default:
6787 BAD_CASE (fragP->fr_subtype);
6788 break;
6789 }
252b5132 6790 }
fddf5b5b 6791
7b81dfbb
AJ		 6792 /* If size if less then four we are sure that the operand fits,
6793 but if it's 4, then it could be that the displacement is larger
6794 then -/+ 2GB. */
6795 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6796 && object_64bit
6797 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 6798 + ((addressT) 1 << 31))
6799 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 6800 {
6801 as_bad_where (fragP->fr_file, fragP->fr_line,
6802 _("jump target out of range"));
6803 /* Make us emit 0. */
6804 displacement_from_opcode_start = extension;
6805 }
47926f60 6806 /* Now put displacement after opcode. */
252b5132
RH		 6807 md_number_to_chars ((char *) where_to_put_displacement,
6808 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 6809 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 6810 fragP->fr_fix += extension;
6811}
6812\f
252b5132
RH		 6813/* Apply a fixup (fixS) to segment data, once it has been determined
6814 by our caller that we have all the info we need to fix it up.
6815
6816 On the 386, immediates, displacements, and data pointers are all in
6817 the same (little-endian) format, so we don't need to care about which
6818 we are handling. */
6819
94f592af 6820void
55cf6793 6821md_apply_fix (fixP, valP, seg)
47926f60
KH		 6822 /* The fix we're to put in. */
6823 fixS *fixP;
47926f60 6824 /* Pointer to the value of the bits. */
c6682705 6825 valueT *valP;
47926f60
KH		 6826 /* Segment fix is from. */
6827 segT seg ATTRIBUTE_UNUSED;
252b5132 6828{
94f592af 6829 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 6830 valueT value = *valP;
252b5132 6831
f86103b7 6832#if !defined (TE_Mach)
93382f6d
AM		 6833 if (fixP->fx_pcrel)
6834 {
6835 switch (fixP->fx_r_type)
6836 {
5865bb77
ILT		 6837 default:
6838 break;
6839
d6ab8113
JB		 6840 case BFD_RELOC_64:
6841 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6842 break;
93382f6d 6843 case BFD_RELOC_32:
ae8887b5 6844 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 6845 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6846 break;
6847 case BFD_RELOC_16:
6848 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6849 break;
6850 case BFD_RELOC_8:
6851 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6852 break;
6853 }
6854 }
252b5132 6855
a161fe53 6856 if (fixP->fx_addsy != NULL
31312f95 6857 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 6858 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 6859 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6860 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6861 && !use_rela_relocations)
252b5132 6862 {
31312f95
AM		 6863 /* This is a hack. There should be a better way to handle this.
6864 This covers for the fact that bfd_install_relocation will
6865 subtract the current location (for partial_inplace, PC relative
6866 relocations); see more below. */
252b5132 6867#ifndef OBJ_AOUT
718ddfc0 6868 if (IS_ELF
252b5132
RH		 6869#ifdef TE_PE
6870 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6871#endif
6872 )
6873 value += fixP->fx_where + fixP->fx_frag->fr_address;
6874#endif
6875#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6876 if (IS_ELF)
252b5132 6877 {
6539b54b 6878 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 6879
6539b54b 6880 if ((sym_seg == seg
2f66722d 6881 || (symbol_section_p (fixP->fx_addsy)
6539b54b 6882 && sym_seg != absolute_section))
ae6063d4 6883 && !generic_force_reloc (fixP))
2f66722d
AM		 6884 {
6885 /* Yes, we add the values in twice. This is because
6539b54b
AM		 6886 bfd_install_relocation subtracts them out again. I think
6887 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 6888 it. FIXME. */
6889 value += fixP->fx_where + fixP->fx_frag->fr_address;
6890 }
252b5132
RH		 6891 }
6892#endif
6893#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 6894 /* For some reason, the PE format does not store a
6895 section address offset for a PC relative symbol. */
6896 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 6897 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 6898 value += md_pcrel_from (fixP);
6899#endif
6900 }
6901
6902 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 6903 and we must not disappoint it. */
252b5132 6904#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6905 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 6906 switch (fixP->fx_r_type)
6907 {
6908 case BFD_RELOC_386_PLT32:
3e73aa7c 6909 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 6910 /* Make the jump instruction point to the address of the operand. At
6911 runtime we merely add the offset to the actual PLT entry. */
6912 value = -4;
6913 break;
31312f95 6914
13ae64f3
JJ		 6915 case BFD_RELOC_386_TLS_GD:
6916 case BFD_RELOC_386_TLS_LDM:
13ae64f3 6917 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6918 case BFD_RELOC_386_TLS_IE:
6919 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 6920 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 6921 case BFD_RELOC_X86_64_TLSGD:
6922 case BFD_RELOC_X86_64_TLSLD:
6923 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 6924 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 6925 value = 0; /* Fully resolved at runtime. No addend. */
6926 /* Fallthrough */
6927 case BFD_RELOC_386_TLS_LE:
6928 case BFD_RELOC_386_TLS_LDO_32:
6929 case BFD_RELOC_386_TLS_LE_32:
6930 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6931 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 6932 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 6933 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 6934 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6935 break;
6936
67a4f2b7
AO		 6937 case BFD_RELOC_386_TLS_DESC_CALL:
6938 case BFD_RELOC_X86_64_TLSDESC_CALL:
6939 value = 0; /* Fully resolved at runtime. No addend. */
6940 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6941 fixP->fx_done = 0;
6942 return;
6943
00f7efb6
JJ		 6944 case BFD_RELOC_386_GOT32:
6945 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 6946 value = 0; /* Fully resolved at runtime. No addend. */
6947 break;
47926f60
KH		 6948
6949 case BFD_RELOC_VTABLE_INHERIT:
6950 case BFD_RELOC_VTABLE_ENTRY:
6951 fixP->fx_done = 0;
94f592af 6952 return;
47926f60
KH		 6953
6954 default:
6955 break;
6956 }
6957#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 6958 *valP = value;
f86103b7 6959#endif /* !defined (TE_Mach) */
3e73aa7c 6960
3e73aa7c 6961 /* Are we finished with this relocation now? */
c6682705 6962 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 6963 fixP->fx_done = 1;
6964 else if (use_rela_relocations)
6965 {
6966 fixP->fx_no_overflow = 1;
062cd5e7
AS		 6967 /* Remember value for tc_gen_reloc. */
6968 fixP->fx_addnumber = value;
3e73aa7c
JH		 6969 value = 0;
6970 }
f86103b7 6971
94f592af 6972 md_number_to_chars (p, value, fixP->fx_size);
252b5132 6973}
252b5132 6974\f
252b5132 6975char *
499ac353 6976md_atof (int type, char *litP, int *sizeP)
252b5132 6977{
499ac353
NC		 6978 /* This outputs the LITTLENUMs in REVERSE order;
6979 in accord with the bigendian 386. */
6980 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 6981}
6982\f
2d545b82 6983static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 6984
252b5132 6985static char *
e3bb37b5 6986output_invalid (int c)
252b5132 6987{
3882b010 6988 if (ISPRINT (c))
f9f21a03
L		 6989 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6990 "'%c'", c);
252b5132 6991 else
f9f21a03 6992 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 6993 "(0x%x)", (unsigned char) c);
252b5132
RH		 6994 return output_invalid_buf;
6995}
6996
af6bdddf 6997/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 6998
6999static const reg_entry *
4d1bb795 7000parse_real_register (char *reg_string, char **end_op)
252b5132 7001{
af6bdddf
AM		 7002 char *s = reg_string;
7003 char *p;
252b5132
RH		 7004 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7005 const reg_entry *r;
7006
7007 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7008 if (*s == REGISTER_PREFIX)
7009 ++s;
7010
7011 if (is_space_char (*s))
7012 ++s;
7013
7014 p = reg_name_given;
af6bdddf 7015 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7016 {
7017 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7018 return (const reg_entry *) NULL;
7019 s++;
252b5132
RH		 7020 }
7021
6588847e
DN		 7022 /* For naked regs, make sure that we are not dealing with an identifier.
7023 This prevents confusing an identifier like `eax_var' with register
7024 `eax'. */
7025 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7026 return (const reg_entry *) NULL;
7027
af6bdddf 7028 *end_op = s;
252b5132
RH		 7029
7030 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7031
5f47d35b 7032 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7033 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7034 {
5f47d35b
AM		 7035 if (is_space_char (*s))
7036 ++s;
7037 if (*s == '(')
7038 {
af6bdddf 7039 ++s;
5f47d35b
AM		 7040 if (is_space_char (*s))
7041 ++s;
7042 if (*s >= '0' && *s <= '7')
7043 {
db557034 7044 int fpr = *s - '0';
af6bdddf 7045 ++s;
5f47d35b
AM		 7046 if (is_space_char (*s))
7047 ++s;
7048 if (*s == ')')
7049 {
7050 *end_op = s + 1;
db557034
AM		 7051 r = hash_find (reg_hash, "st(0)");
7052 know (r);
7053 return r + fpr;
5f47d35b 7054 }
5f47d35b 7055 }
47926f60 7056 /* We have "%st(" then garbage. */
5f47d35b
AM		 7057 return (const reg_entry *) NULL;
7058 }
7059 }
7060
a60de03c
JB		 7061 if (r == NULL || allow_pseudo_reg)
7062 return r;
7063
7064 if (UINTS_ALL_ZERO (r->reg_type))
7065 return (const reg_entry *) NULL;
7066
db51cc60 7067 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7068 if (!allow_index_reg
db51cc60
L		 7069 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7070 return (const reg_entry *) NULL;
7071
a60de03c
JB		 7072 if (((r->reg_flags & (RegRex64 | RegRex))
7073 || r->reg_type.bitfield.reg64)
40fb9820 7074 && (!cpu_arch_flags.bitfield.cpulm
c6fb90c8 7075 || !UINTS_EQUAL (r->reg_type, control))
1ae00879 7076 && flag_code != CODE_64BIT)
20f0a1fc 7077 return (const reg_entry *) NULL;
1ae00879 7078
252b5132
RH		 7079 return r;
7080}
4d1bb795
JB		 7081
7082/* REG_STRING starts *before* REGISTER_PREFIX. */
7083
7084static const reg_entry *
7085parse_register (char *reg_string, char **end_op)
7086{
7087 const reg_entry *r;
7088
7089 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7090 r = parse_real_register (reg_string, end_op);
7091 else
7092 r = NULL;
7093 if (!r)
7094 {
7095 char *save = input_line_pointer;
7096 char c;
7097 symbolS *symbolP;
7098
7099 input_line_pointer = reg_string;
7100 c = get_symbol_end ();
7101 symbolP = symbol_find (reg_string);
7102 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7103 {
7104 const expressionS *e = symbol_get_value_expression (symbolP);
7105
7106 know (e->X_op == O_register);
4eed87de 7107 know (e->X_add_number >= 0
c3fe08fa 7108 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7109 r = i386_regtab + e->X_add_number;
7110 *end_op = input_line_pointer;
7111 }
7112 *input_line_pointer = c;
7113 input_line_pointer = save;
7114 }
7115 return r;
7116}
7117
7118int
7119i386_parse_name (char *name, expressionS *e, char *nextcharP)
7120{
7121 const reg_entry *r;
7122 char *end = input_line_pointer;
7123
7124 *end = *nextcharP;
7125 r = parse_register (name, &input_line_pointer);
7126 if (r && end <= input_line_pointer)
7127 {
7128 *nextcharP = *input_line_pointer;
7129 *input_line_pointer = 0;
7130 e->X_op = O_register;
7131 e->X_add_number = r - i386_regtab;
7132 return 1;
7133 }
7134 input_line_pointer = end;
7135 *end = 0;
7136 return 0;
7137}
7138
7139void
7140md_operand (expressionS *e)
7141{
7142 if (*input_line_pointer == REGISTER_PREFIX)
7143 {
7144 char *end;
7145 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7146
7147 if (r)
7148 {
7149 e->X_op = O_register;
7150 e->X_add_number = r - i386_regtab;
7151 input_line_pointer = end;
7152 }
7153 }
7154}
7155
252b5132 7156\f
4cc782b5 7157#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7158const char *md_shortopts = "kVQ:sqn";
252b5132 7159#else
12b55ccc 7160const char *md_shortopts = "qn";
252b5132 7161#endif
6e0b89ee 7162
3e73aa7c 7163#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7164#define OPTION_64 (OPTION_MD_BASE + 1)
7165#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7166#define OPTION_MARCH (OPTION_MD_BASE + 3)
7167#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7168#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7169#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7170#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7171#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7172#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
b3b91714 7173
99ad8390
NC		 7174struct option md_longopts[] =
7175{
3e73aa7c 7176 {"32", no_argument, NULL, OPTION_32},
99ad8390 7177#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 7178 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7179#endif
b3b91714 7180 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7181 {"march", required_argument, NULL, OPTION_MARCH},
7182 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7183 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7184 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7185 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7186 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7187 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
252b5132
RH		 7188 {NULL, no_argument, NULL, 0}
7189};
7190size_t md_longopts_size = sizeof (md_longopts);
7191
7192int
9103f4f4 7193md_parse_option (int c, char *arg)
252b5132 7194{
9103f4f4 7195 unsigned int i;
6305a203 7196 char *arch, *next;
9103f4f4 7197
252b5132
RH		 7198 switch (c)
7199 {
12b55ccc
L		 7200 case 'n':
7201 optimize_align_code = 0;
7202 break;
7203
a38cf1db
AM		 7204 case 'q':
7205 quiet_warnings = 1;
252b5132
RH		 7206 break;
7207
7208#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7209 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7210 should be emitted or not. FIXME: Not implemented. */
7211 case 'Q':
252b5132
RH		 7212 break;
7213
7214 /* -V: SVR4 argument to print version ID. */
7215 case 'V':
7216 print_version_id ();
7217 break;
7218
a38cf1db
AM		 7219 /* -k: Ignore for FreeBSD compatibility. */
7220 case 'k':
252b5132 7221 break;
4cc782b5
ILT		 7222
7223 case 's':
7224 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7225 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7226 break;
99ad8390
NC		 7227#endif
7228#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 7229 case OPTION_64:
7230 {
7231 const char **list, **l;
7232
3e73aa7c
JH		 7233 list = bfd_target_list ();
7234 for (l = list; *l != NULL; l++)
8620418b 7235 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7236 || strcmp (*l, "coff-x86-64") == 0
7237 || strcmp (*l, "pe-x86-64") == 0
7238 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7239 {
7240 default_arch = "x86_64";
7241 break;
7242 }
3e73aa7c 7243 if (*l == NULL)
6e0b89ee 7244 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7245 free (list);
7246 }
7247 break;
7248#endif
252b5132 7249
6e0b89ee
AM		 7250 case OPTION_32:
7251 default_arch = "i386";
7252 break;
7253
b3b91714
AM		 7254 case OPTION_DIVIDE:
7255#ifdef SVR4_COMMENT_CHARS
7256 {
7257 char *n, *t;
7258 const char *s;
7259
7260 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7261 t = n;
7262 for (s = i386_comment_chars; *s != '\0'; s++)
7263 if (*s != '/')
7264 *t++ = *s;
7265 *t = '\0';
7266 i386_comment_chars = n;
7267 }
7268#endif
7269 break;
7270
9103f4f4 7271 case OPTION_MARCH:
6305a203
L		 7272 arch = xstrdup (arg);
7273 do
9103f4f4 7274 {
6305a203
L		 7275 if (*arch == '.')
7276 as_fatal (_("Invalid -march= option: `%s'"), arg);
7277 next = strchr (arch, '+');
7278 if (next)
7279 *next++ = '\0';
7280 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 7281 {
6305a203 7282 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 7283 {
6305a203
L		 7284 /* Processor. */
7285 cpu_arch_name = cpu_arch[i].name;
7286 cpu_sub_arch_name = NULL;
7287 cpu_arch_flags = cpu_arch[i].flags;
7288 cpu_arch_isa = cpu_arch[i].type;
7289 cpu_arch_isa_flags = cpu_arch[i].flags;
7290 if (!cpu_arch_tune_set)
7291 {
7292 cpu_arch_tune = cpu_arch_isa;
7293 cpu_arch_tune_flags = cpu_arch_isa_flags;
7294 }
7295 break;
7296 }
7297 else if (*cpu_arch [i].name == '.'
7298 && strcmp (arch, cpu_arch [i].name + 1) == 0)
7299 {
7300 /* ISA entension. */
7301 i386_cpu_flags flags;
7302 flags = cpu_flags_or (cpu_arch_flags,
7303 cpu_arch[i].flags);
7304 if (!UINTS_EQUAL (flags, cpu_arch_flags))
7305 {
7306 if (cpu_sub_arch_name)
7307 {
7308 char *name = cpu_sub_arch_name;
7309 cpu_sub_arch_name = concat (name,
7310 cpu_arch[i].name,
1bf57e9f 7311 (const char *) NULL);
6305a203
L		 7312 free (name);
7313 }
7314 else
7315 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
7316 cpu_arch_flags = flags;
7317 }
7318 break;
ccc9c027 7319 }
9103f4f4 7320 }
6305a203
L		 7321
7322 if (i >= ARRAY_SIZE (cpu_arch))
7323 as_fatal (_("Invalid -march= option: `%s'"), arg);
7324
7325 arch = next;
9103f4f4 7326 }
6305a203 7327 while (next != NULL );
9103f4f4
L		 7328 break;
7329
7330 case OPTION_MTUNE:
7331 if (*arg == '.')
7332 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7333 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7334 {
7335 if (strcmp (arg, cpu_arch [i].name) == 0)
7336 {
ccc9c027 7337 cpu_arch_tune_set = 1;
9103f4f4
L		 7338 cpu_arch_tune = cpu_arch [i].type;
7339 cpu_arch_tune_flags = cpu_arch[i].flags;
7340 break;
7341 }
7342 }
7343 if (i >= ARRAY_SIZE (cpu_arch))
7344 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7345 break;
7346
1efbbeb4
L		 7347 case OPTION_MMNEMONIC:
7348 if (strcasecmp (arg, "att") == 0)
7349 intel_mnemonic = 0;
7350 else if (strcasecmp (arg, "intel") == 0)
7351 intel_mnemonic = 1;
7352 else
7353 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7354 break;
7355
7356 case OPTION_MSYNTAX:
7357 if (strcasecmp (arg, "att") == 0)
7358 intel_syntax = 0;
7359 else if (strcasecmp (arg, "intel") == 0)
7360 intel_syntax = 1;
7361 else
7362 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7363 break;
7364
7365 case OPTION_MINDEX_REG:
7366 allow_index_reg = 1;
7367 break;
7368
7369 case OPTION_MNAKED_REG:
7370 allow_naked_reg = 1;
7371 break;
7372
7373 case OPTION_MOLD_GCC:
7374 old_gcc = 1;
1efbbeb4
L		 7375 break;
7376
252b5132
RH		 7377 default:
7378 return 0;
7379 }
7380 return 1;
7381}
7382
7383void
7384md_show_usage (stream)
7385 FILE *stream;
7386{
4cc782b5
ILT		 7387#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7388 fprintf (stream, _("\
a38cf1db
AM		 7389 -Q ignored\n\
7390 -V print assembler version number\n\
b3b91714
AM		 7391 -k ignored\n"));
7392#endif
7393 fprintf (stream, _("\
12b55ccc 7394 -n Do not optimize code alignment\n\
b3b91714
AM		 7395 -q quieten some warnings\n"));
7396#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7397 fprintf (stream, _("\
a38cf1db 7398 -s ignored\n"));
b3b91714 7399#endif
751d281c
L		 7400#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7401 fprintf (stream, _("\
7402 --32/--64 generate 32bit/64bit code\n"));
7403#endif
b3b91714
AM		 7404#ifdef SVR4_COMMENT_CHARS
7405 fprintf (stream, _("\
7406 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 7407#else
7408 fprintf (stream, _("\
b3b91714 7409 --divide ignored\n"));
4cc782b5 7410#endif
9103f4f4 7411 fprintf (stream, _("\
6305a203
L		 7412 -march=CPU[,+EXTENSION...]\n\
7413 generate code for CPU and EXTENSION, CPU is one of:\n\
2cb4f3d5
L		 7414 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7415 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7416 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
7417 generic32, generic64\n\
599121aa
L		 7418 EXTENSION is combination of:\n\
7419 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
f03fe4c1
L		 7420 vmx, smx, xsave, 3dnow, 3dnowa, sse4a, sse5, svme,\n\
7421 abm, padlock\n"));
6305a203 7422 fprintf (stream, _("\
2cb4f3d5
L		 7423 -mtune=CPU optimize for CPU, CPU is one of:\n\
7424 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7425 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7426 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
7427 generic32, generic64\n"));
ba104c83
L		 7428 fprintf (stream, _("\
7429 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7430 fprintf (stream, _("\
7431 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7432 fprintf (stream, _("\
7433 -mindex-reg support pseudo index registers\n"));
7434 fprintf (stream, _("\
7435 -mnaked-reg don't require `%%' prefix for registers\n"));
7436 fprintf (stream, _("\
7437 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 7438}
7439
3e73aa7c 7440#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 7441 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 7442
7443/* Pick the target format to use. */
7444
47926f60 7445const char *
e3bb37b5 7446i386_target_format (void)
252b5132 7447{
3e73aa7c 7448 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 7449 {
7450 set_code_flag (CODE_64BIT);
c6fb90c8 7451 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7452 {
7453 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7454 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7455 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7456 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7457 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7458 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7459 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7460 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 7461 cpu_arch_isa_flags.bitfield.cpusse = 1;
7462 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7463 }
c6fb90c8 7464 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7465 {
7466 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7467 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7468 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7469 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7470 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7471 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7472 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7473 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 7474 cpu_arch_tune_flags.bitfield.cpusse = 1;
7475 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7476 }
9103f4f4 7477 }
3e73aa7c 7478 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 7479 {
7480 set_code_flag (CODE_32BIT);
c6fb90c8 7481 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7482 {
7483 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7484 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7485 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7486 }
c6fb90c8 7487 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7488 {
7489 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7490 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7491 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7492 }
9103f4f4 7493 }
3e73aa7c
JH		 7494 else
7495 as_fatal (_("Unknown architecture"));
252b5132
RH		 7496 switch (OUTPUT_FLAVOR)
7497 {
872ce6ff
L		 7498#ifdef TE_PEP
7499 case bfd_target_coff_flavour:
7500 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7501 break;
7502#endif
4c63da97
AM		 7503#ifdef OBJ_MAYBE_AOUT
7504 case bfd_target_aout_flavour:
47926f60 7505 return AOUT_TARGET_FORMAT;
4c63da97
AM		 7506#endif
7507#ifdef OBJ_MAYBE_COFF
252b5132
RH		 7508 case bfd_target_coff_flavour:
7509 return "coff-i386";
4c63da97 7510#endif
3e73aa7c 7511#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 7512 case bfd_target_elf_flavour:
3e73aa7c 7513 {
e5cb08ac 7514 if (flag_code == CODE_64BIT)
4fa24527
JB		 7515 {
7516 object_64bit = 1;
7517 use_rela_relocations = 1;
7518 }
9d7cbccd 7519 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 7520 }
4c63da97 7521#endif
252b5132
RH		 7522 default:
7523 abort ();
7524 return NULL;
7525 }
7526}
7527
47926f60 7528#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 7529
7530#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 7531void
7532i386_elf_emit_arch_note (void)
a847613f 7533{
718ddfc0 7534 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 7535 {
7536 char *p;
7537 asection *seg = now_seg;
7538 subsegT subseg = now_subseg;
7539 Elf_Internal_Note i_note;
7540 Elf_External_Note e_note;
7541 asection *note_secp;
7542 int len;
7543
7544 /* Create the .note section. */
7545 note_secp = subseg_new (".note", 0);
7546 bfd_set_section_flags (stdoutput,
7547 note_secp,
7548 SEC_HAS_CONTENTS | SEC_READONLY);
7549
7550 /* Process the arch string. */
7551 len = strlen (cpu_arch_name);
7552
7553 i_note.namesz = len + 1;
7554 i_note.descsz = 0;
7555 i_note.type = NT_ARCH;
7556 p = frag_more (sizeof (e_note.namesz));
7557 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7558 p = frag_more (sizeof (e_note.descsz));
7559 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7560 p = frag_more (sizeof (e_note.type));
7561 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7562 p = frag_more (len + 1);
7563 strcpy (p, cpu_arch_name);
7564
7565 frag_align (2, 0, 0);
7566
7567 subseg_set (seg, subseg);
7568 }
7569}
7570#endif
252b5132 7571\f
252b5132
RH		 7572symbolS *
7573md_undefined_symbol (name)
7574 char *name;
7575{
18dc2407
ILT		 7576 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7577 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7578 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7579 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 7580 {
7581 if (!GOT_symbol)
7582 {
7583 if (symbol_find (name))
7584 as_bad (_("GOT already in symbol table"));
7585 GOT_symbol = symbol_new (name, undefined_section,
7586 (valueT) 0, &zero_address_frag);
7587 };
7588 return GOT_symbol;
7589 }
252b5132
RH		 7590 return 0;
7591}
7592
7593/* Round up a section size to the appropriate boundary. */
47926f60 7594
252b5132
RH		 7595valueT
7596md_section_align (segment, size)
ab9da554 7597 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7598 valueT size;
7599{
4c63da97
AM		 7600#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7601 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7602 {
7603 /* For a.out, force the section size to be aligned. If we don't do
7604 this, BFD will align it for us, but it will not write out the
7605 final bytes of the section. This may be a bug in BFD, but it is
7606 easier to fix it here since that is how the other a.out targets
7607 work. */
7608 int align;
7609
7610 align = bfd_get_section_alignment (stdoutput, segment);
7611 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7612 }
252b5132
RH		 7613#endif
7614
7615 return size;
7616}
7617
7618/* On the i386, PC-relative offsets are relative to the start of the
7619 next instruction. That is, the address of the offset, plus its
7620 size, since the offset is always the last part of the insn. */
7621
7622long
e3bb37b5 7623md_pcrel_from (fixS *fixP)
252b5132
RH		 7624{
7625 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7626}
7627
7628#ifndef I386COFF
7629
7630static void
e3bb37b5 7631s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 7632{
29b0f896 7633 int temp;
252b5132 7634
8a75718c
JB		 7635#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7636 if (IS_ELF)
7637 obj_elf_section_change_hook ();
7638#endif
252b5132
RH		 7639 temp = get_absolute_expression ();
7640 subseg_set (bss_section, (subsegT) temp);
7641 demand_empty_rest_of_line ();
7642}
7643
7644#endif
7645
252b5132 7646void
e3bb37b5 7647i386_validate_fix (fixS *fixp)
252b5132
RH		 7648{
7649 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7650 {
23df1078
JH		 7651 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7652 {
4fa24527 7653 if (!object_64bit)
23df1078
JH		 7654 abort ();
7655 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7656 }
7657 else
7658 {
4fa24527 7659 if (!object_64bit)
d6ab8113
JB		 7660 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7661 else
7662 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 7663 }
252b5132
RH		 7664 fixp->fx_subsy = 0;
7665 }
7666}
7667
252b5132
RH		 7668arelent *
7669tc_gen_reloc (section, fixp)
ab9da554 7670 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 7671 fixS *fixp;
7672{
7673 arelent *rel;
7674 bfd_reloc_code_real_type code;
7675
7676 switch (fixp->fx_r_type)
7677 {
3e73aa7c
JH		 7678 case BFD_RELOC_X86_64_PLT32:
7679 case BFD_RELOC_X86_64_GOT32:
7680 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 7681 case BFD_RELOC_386_PLT32:
7682 case BFD_RELOC_386_GOT32:
7683 case BFD_RELOC_386_GOTOFF:
7684 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 7685 case BFD_RELOC_386_TLS_GD:
7686 case BFD_RELOC_386_TLS_LDM:
7687 case BFD_RELOC_386_TLS_LDO_32:
7688 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7689 case BFD_RELOC_386_TLS_IE:
7690 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 7691 case BFD_RELOC_386_TLS_LE_32:
7692 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 7693 case BFD_RELOC_386_TLS_GOTDESC:
7694 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 7695 case BFD_RELOC_X86_64_TLSGD:
7696 case BFD_RELOC_X86_64_TLSLD:
7697 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7698 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 7699 case BFD_RELOC_X86_64_GOTTPOFF:
7700 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 7701 case BFD_RELOC_X86_64_TPOFF64:
7702 case BFD_RELOC_X86_64_GOTOFF64:
7703 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 7704 case BFD_RELOC_X86_64_GOT64:
7705 case BFD_RELOC_X86_64_GOTPCREL64:
7706 case BFD_RELOC_X86_64_GOTPC64:
7707 case BFD_RELOC_X86_64_GOTPLT64:
7708 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 7709 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7710 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 7711 case BFD_RELOC_RVA:
7712 case BFD_RELOC_VTABLE_ENTRY:
7713 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 7714#ifdef TE_PE
7715 case BFD_RELOC_32_SECREL:
7716#endif
252b5132
RH		 7717 code = fixp->fx_r_type;
7718 break;
dbbaec26
L		 7719 case BFD_RELOC_X86_64_32S:
7720 if (!fixp->fx_pcrel)
7721 {
7722 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7723 code = fixp->fx_r_type;
7724 break;
7725 }
252b5132 7726 default:
93382f6d 7727 if (fixp->fx_pcrel)
252b5132 7728 {
93382f6d
AM		 7729 switch (fixp->fx_size)
7730 {
7731 default:
b091f402
AM		 7732 as_bad_where (fixp->fx_file, fixp->fx_line,
7733 _("can not do %d byte pc-relative relocation"),
7734 fixp->fx_size);
93382f6d
AM		 7735 code = BFD_RELOC_32_PCREL;
7736 break;
7737 case 1: code = BFD_RELOC_8_PCREL; break;
7738 case 2: code = BFD_RELOC_16_PCREL; break;
7739 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 7740#ifdef BFD64
7741 case 8: code = BFD_RELOC_64_PCREL; break;
7742#endif
93382f6d
AM		 7743 }
7744 }
7745 else
7746 {
7747 switch (fixp->fx_size)
7748 {
7749 default:
b091f402
AM		 7750 as_bad_where (fixp->fx_file, fixp->fx_line,
7751 _("can not do %d byte relocation"),
7752 fixp->fx_size);
93382f6d
AM		 7753 code = BFD_RELOC_32;
7754 break;
7755 case 1: code = BFD_RELOC_8; break;
7756 case 2: code = BFD_RELOC_16; break;
7757 case 4: code = BFD_RELOC_32; break;
937149dd 7758#ifdef BFD64
3e73aa7c 7759 case 8: code = BFD_RELOC_64; break;
937149dd 7760#endif
93382f6d 7761 }
252b5132
RH		 7762 }
7763 break;
7764 }
252b5132 7765
d182319b
JB		 7766 if ((code == BFD_RELOC_32
7767 || code == BFD_RELOC_32_PCREL
7768 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 7769 && GOT_symbol
7770 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 7771 {
4fa24527 7772 if (!object_64bit)
d6ab8113
JB		 7773 code = BFD_RELOC_386_GOTPC;
7774 else
7775 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 7776 }
7b81dfbb
AJ		 7777 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7778 && GOT_symbol
7779 && fixp->fx_addsy == GOT_symbol)
7780 {
7781 code = BFD_RELOC_X86_64_GOTPC64;
7782 }
252b5132
RH		 7783
7784 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 7785 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7786 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 7787
7788 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 7789
3e73aa7c
JH		 7790 if (!use_rela_relocations)
7791 {
7792 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7793 vtable entry to be used in the relocation's section offset. */
7794 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7795 rel->address = fixp->fx_offset;
252b5132 7796
c6682705 7797 rel->addend = 0;
3e73aa7c
JH		 7798 }
7799 /* Use the rela in 64bit mode. */
252b5132 7800 else
3e73aa7c 7801 {
062cd5e7
AS		 7802 if (!fixp->fx_pcrel)
7803 rel->addend = fixp->fx_offset;
7804 else
7805 switch (code)
7806 {
7807 case BFD_RELOC_X86_64_PLT32:
7808 case BFD_RELOC_X86_64_GOT32:
7809 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 7810 case BFD_RELOC_X86_64_TLSGD:
7811 case BFD_RELOC_X86_64_TLSLD:
7812 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 7813 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7814 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 7815 rel->addend = fixp->fx_offset - fixp->fx_size;
7816 break;
7817 default:
7818 rel->addend = (section->vma
7819 - fixp->fx_size
7820 + fixp->fx_addnumber
7821 + md_pcrel_from (fixp));
7822 break;
7823 }
3e73aa7c
JH		 7824 }
7825
252b5132
RH		 7826 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7827 if (rel->howto == NULL)
7828 {
7829 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 7830 _("cannot represent relocation type %s"),
252b5132
RH		 7831 bfd_get_reloc_code_name (code));
7832 /* Set howto to a garbage value so that we can keep going. */
7833 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7834 assert (rel->howto != NULL);
7835 }
7836
7837 return rel;
7838}
7839
64a0c779
DN		 7840\f
7841/* Parse operands using Intel syntax. This implements a recursive descent
7842 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7843 Programmer's Guide.
7844
7845 FIXME: We do not recognize the full operand grammar defined in the MASM
7846 documentation. In particular, all the structure/union and
7847 high-level macro operands are missing.
7848
7849 Uppercase words are terminals, lower case words are non-terminals.
7850 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7851 bars '|' denote choices. Most grammar productions are implemented in
7852 functions called 'intel_<production>'.
7853
7854 Initial production is 'expr'.
7855
9306ca4a 7856 addOp + | -
64a0c779
DN		 7857
7858 alpha [a-zA-Z]
7859
9306ca4a
JB		 7860 binOp & | AND | \| | OR | ^ | XOR
7861
64a0c779
DN		 7862 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7863
7864 constant digits [[ radixOverride ]]
7865
9306ca4a 7866 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 7867
7868 digits decdigit
b77a7acd
AJ		 7869 | digits decdigit
7870 | digits hexdigit
64a0c779
DN		 7871
7872 decdigit [0-9]
7873
9306ca4a
JB		 7874 e04 e04 addOp e05
7875 | e05
7876
7877 e05 e05 binOp e06
b77a7acd 7878 | e06
64a0c779
DN		 7879
7880 e06 e06 mulOp e09
b77a7acd 7881 | e09
64a0c779
DN		 7882
7883 e09 OFFSET e10
a724f0f4
JB		 7884 | SHORT e10
7885 | + e10
7886 | - e10
9306ca4a
JB		 7887 | ~ e10
7888 | NOT e10
64a0c779
DN		 7889 | e09 PTR e10
7890 | e09 : e10
7891 | e10
7892
7893 e10 e10 [ expr ]
b77a7acd 7894 | e11
64a0c779
DN		 7895
7896 e11 ( expr )
b77a7acd 7897 | [ expr ]
64a0c779
DN		 7898 | constant
7899 | dataType
7900 | id
7901 | $
7902 | register
7903
a724f0f4 7904 => expr expr cmpOp e04
9306ca4a 7905 | e04
64a0c779
DN		 7906
7907 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 7908 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 7909
7910 hexdigit a | b | c | d | e | f
b77a7acd 7911 | A | B | C | D | E | F
64a0c779
DN		 7912
7913 id alpha
b77a7acd 7914 | id alpha
64a0c779
DN		 7915 | id decdigit
7916
9306ca4a 7917 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 7918
7919 quote " | '
7920
7921 register specialRegister
b77a7acd 7922 | gpRegister
64a0c779
DN		 7923 | byteRegister
7924
7925 segmentRegister CS | DS | ES | FS | GS | SS
7926
9306ca4a 7927 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 7928 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 7929 | TR3 | TR4 | TR5 | TR6 | TR7
7930
64a0c779
DN		 7931 We simplify the grammar in obvious places (e.g., register parsing is
7932 done by calling parse_register) and eliminate immediate left recursion
7933 to implement a recursive-descent parser.
7934
a724f0f4
JB		 7935 expr e04 expr'
7936
7937 expr' cmpOp e04 expr'
7938 | Empty
9306ca4a
JB		 7939
7940 e04 e05 e04'
7941
7942 e04' addOp e05 e04'
7943 | Empty
64a0c779
DN		 7944
7945 e05 e06 e05'
7946
9306ca4a 7947 e05' binOp e06 e05'
b77a7acd 7948 | Empty
64a0c779
DN		 7949
7950 e06 e09 e06'
7951
7952 e06' mulOp e09 e06'
b77a7acd 7953 | Empty
64a0c779
DN		 7954
7955 e09 OFFSET e10 e09'
a724f0f4
JB		 7956 | SHORT e10'
7957 | + e10'
7958 | - e10'
7959 | ~ e10'
7960 | NOT e10'
b77a7acd 7961 | e10 e09'
64a0c779
DN		 7962
7963 e09' PTR e10 e09'
b77a7acd 7964 | : e10 e09'
64a0c779
DN		 7965 | Empty
7966
7967 e10 e11 e10'
7968
7969 e10' [ expr ] e10'
b77a7acd 7970 | Empty
64a0c779
DN		 7971
7972 e11 ( expr )
b77a7acd 7973 | [ expr ]
64a0c779
DN		 7974 | BYTE
7975 | WORD
7976 | DWORD
9306ca4a 7977 | FWORD
64a0c779 7978 | QWORD
9306ca4a
JB		 7979 | TBYTE
7980 | OWORD
7981 | XMMWORD
64a0c779
DN		 7982 | .
7983 | $
7984 | register
7985 | id
7986 | constant */
7987
7988/* Parsing structure for the intel syntax parser. Used to implement the
7989 semantic actions for the operand grammar. */
7990struct intel_parser_s
7991 {
7992 char *op_string; /* The string being parsed. */
7993 int got_a_float; /* Whether the operand is a float. */
4a1805b1 7994 int op_modifier; /* Operand modifier. */
64a0c779 7995 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 7996 int in_offset; /* >=1 if parsing operand of offset. */
7997 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 7998 const reg_entry *reg; /* Last register reference found. */
7999 char *disp; /* Displacement string being built. */
a724f0f4 8000 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 8001 };
8002
8003static struct intel_parser_s intel_parser;
8004
8005/* Token structure for parsing intel syntax. */
8006struct intel_token
8007 {
8008 int code; /* Token code. */
8009 const reg_entry *reg; /* Register entry for register tokens. */
8010 char *str; /* String representation. */
8011 };
8012
8013static struct intel_token cur_token, prev_token;
8014
50705ef4
AM		 8015/* Token codes for the intel parser. Since T_SHORT is already used
8016 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 8017#define T_NIL -1
8018#define T_CONST 1
8019#define T_REG 2
8020#define T_BYTE 3
8021#define T_WORD 4
9306ca4a
JB		 8022#define T_DWORD 5
8023#define T_FWORD 6
8024#define T_QWORD 7
8025#define T_TBYTE 8
8026#define T_XMMWORD 9
50705ef4 8027#undef T_SHORT
9306ca4a
JB		 8028#define T_SHORT 10
8029#define T_OFFSET 11
8030#define T_PTR 12
8031#define T_ID 13
8032#define T_SHL 14
8033#define T_SHR 15
64a0c779
DN		 8034
8035/* Prototypes for intel parser functions. */
e3bb37b5
L		 8036static int intel_match_token (int);
8037static void intel_putback_token (void);
8038static void intel_get_token (void);
8039static int intel_expr (void);
8040static int intel_e04 (void);
8041static int intel_e05 (void);
8042static int intel_e06 (void);
8043static int intel_e09 (void);
8044static int intel_e10 (void);
8045static int intel_e11 (void);
64a0c779 8046
64a0c779 8047static int
e3bb37b5 8048i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 8049{
8050 int ret;
8051 char *p;
8052
a724f0f4
JB		 8053 p = intel_parser.op_string = xstrdup (operand_string);
8054 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
8055
8056 for (;;)
64a0c779 8057 {
a724f0f4
JB		 8058 /* Initialize token holders. */
8059 cur_token.code = prev_token.code = T_NIL;
8060 cur_token.reg = prev_token.reg = NULL;
8061 cur_token.str = prev_token.str = NULL;
8062
8063 /* Initialize parser structure. */
8064 intel_parser.got_a_float = got_a_float;
8065 intel_parser.op_modifier = 0;
8066 intel_parser.is_mem = 0;
8067 intel_parser.in_offset = 0;
8068 intel_parser.in_bracket = 0;
8069 intel_parser.reg = NULL;
8070 intel_parser.disp[0] = '\0';
8071 intel_parser.next_operand = NULL;
8072
8073 /* Read the first token and start the parser. */
8074 intel_get_token ();
8075 ret = intel_expr ();
8076
8077 if (!ret)
8078 break;
8079
9306ca4a
JB		 8080 if (cur_token.code != T_NIL)
8081 {
8082 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8083 current_templates->start->name, cur_token.str);
8084 ret = 0;
8085 }
64a0c779
DN		 8086 /* If we found a memory reference, hand it over to i386_displacement
8087 to fill in the rest of the operand fields. */
9306ca4a 8088 else if (intel_parser.is_mem)
64a0c779
DN		 8089 {
8090 if ((i.mem_operands == 1
40fb9820 8091 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 8092 || i.mem_operands == 2)
8093 {
8094 as_bad (_("too many memory references for '%s'"),
8095 current_templates->start->name);
8096 ret = 0;
8097 }
8098 else
8099 {
8100 char *s = intel_parser.disp;
5c07affc 8101 i.types[this_operand].bitfield.mem = 1;
64a0c779
DN		 8102 i.mem_operands++;
8103
a724f0f4
JB		 8104 if (!quiet_warnings && intel_parser.is_mem < 0)
8105 /* See the comments in intel_bracket_expr. */
8106 as_warn (_("Treating `%s' as memory reference"), operand_string);
8107
64a0c779
DN		 8108 /* Add the displacement expression. */
8109 if (*s != '\0')
a4622f40
AM		 8110 ret = i386_displacement (s, s + strlen (s));
8111 if (ret)
a724f0f4
JB		 8112 {
8113 /* Swap base and index in 16-bit memory operands like
8114 [si+bx]. Since i386_index_check is also used in AT&T
8115 mode we have to do that here. */
8116 if (i.base_reg
8117 && i.index_reg
40fb9820
L		 8118 && i.base_reg->reg_type.bitfield.reg16
8119 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 8120 && i.base_reg->reg_num >= 6
8121 && i.index_reg->reg_num < 6)
8122 {
8123 const reg_entry *base = i.index_reg;
8124
8125 i.index_reg = i.base_reg;
8126 i.base_reg = base;
8127 }
8128 ret = i386_index_check (operand_string);
8129 }
64a0c779
DN		 8130 }
8131 }
8132
8133 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 8134 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 8135 || intel_parser.reg == NULL)
8136 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 8137
8138 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 8139 ret = 0;
a724f0f4
JB		 8140 if (!ret || !intel_parser.next_operand)
8141 break;
8142 intel_parser.op_string = intel_parser.next_operand;
8143 this_operand = i.operands++;
7d5e4556 8144 i.types[this_operand].bitfield.unspecified = 1;
64a0c779
DN		 8145 }
8146
8147 free (p);
8148 free (intel_parser.disp);
8149
8150 return ret;
8151}
8152
a724f0f4
JB		 8153#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8154
8155/* expr e04 expr'
8156
8157 expr' cmpOp e04 expr'
8158 | Empty */
64a0c779 8159static int
e3bb37b5 8160intel_expr (void)
64a0c779 8161{
a724f0f4
JB		 8162 /* XXX Implement the comparison operators. */
8163 return intel_e04 ();
9306ca4a
JB		 8164}
8165
a724f0f4 8166/* e04 e05 e04'
9306ca4a 8167
a724f0f4 8168 e04' addOp e05 e04'
9306ca4a
JB		 8169 | Empty */
8170static int
e3bb37b5 8171intel_e04 (void)
9306ca4a 8172{
a724f0f4 8173 int nregs = -1;
9306ca4a 8174
a724f0f4 8175 for (;;)
9306ca4a 8176 {
a724f0f4
JB		 8177 if (!intel_e05())
8178 return 0;
9306ca4a 8179
a724f0f4
JB		 8180 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8181 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 8182
a724f0f4
JB		 8183 if (cur_token.code == '+')
8184 nregs = -1;
8185 else if (cur_token.code == '-')
8186 nregs = NUM_ADDRESS_REGS;
8187 else
8188 return 1;
64a0c779 8189
a724f0f4
JB		 8190 strcat (intel_parser.disp, cur_token.str);
8191 intel_match_token (cur_token.code);
8192 }
64a0c779
DN		 8193}
8194
64a0c779
DN		 8195/* e05 e06 e05'
8196
9306ca4a 8197 e05' binOp e06 e05'
64a0c779
DN		 8198 | Empty */
8199static int
e3bb37b5 8200intel_e05 (void)
64a0c779 8201{
a724f0f4 8202 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 8203
a724f0f4 8204 for (;;)
64a0c779 8205 {
a724f0f4
JB		 8206 if (!intel_e06())
8207 return 0;
8208
4eed87de
AM		 8209 if (cur_token.code == '&'
8210 || cur_token.code == '|'
8211 || cur_token.code == '^')
a724f0f4
JB		 8212 {
8213 char str[2];
8214
8215 str[0] = cur_token.code;
8216 str[1] = 0;
8217 strcat (intel_parser.disp, str);
8218 }
8219 else
8220 break;
9306ca4a 8221
64a0c779
DN		 8222 intel_match_token (cur_token.code);
8223
a724f0f4
JB		 8224 if (nregs < 0)
8225 nregs = ~nregs;
64a0c779 8226 }
a724f0f4
JB		 8227 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8228 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
8229 return 1;
4a1805b1 8230}
64a0c779
DN		 8231
8232/* e06 e09 e06'
8233
8234 e06' mulOp e09 e06'
b77a7acd 8235 | Empty */
64a0c779 8236static int
e3bb37b5 8237intel_e06 (void)
64a0c779 8238{
a724f0f4 8239 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 8240
a724f0f4 8241 for (;;)
64a0c779 8242 {
a724f0f4
JB		 8243 if (!intel_e09())
8244 return 0;
9306ca4a 8245
4eed87de
AM		 8246 if (cur_token.code == '*'
8247 || cur_token.code == '/'
8248 || cur_token.code == '%')
a724f0f4
JB		 8249 {
8250 char str[2];
9306ca4a 8251
a724f0f4
JB		 8252 str[0] = cur_token.code;
8253 str[1] = 0;
8254 strcat (intel_parser.disp, str);
8255 }
8256 else if (cur_token.code == T_SHL)
8257 strcat (intel_parser.disp, "<<");
8258 else if (cur_token.code == T_SHR)
8259 strcat (intel_parser.disp, ">>");
8260 else
8261 break;
9306ca4a 8262
64e74474 8263 intel_match_token (cur_token.code);
64a0c779 8264
a724f0f4
JB		 8265 if (nregs < 0)
8266 nregs = ~nregs;
64a0c779 8267 }
a724f0f4
JB		 8268 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8269 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8270 return 1;
64a0c779
DN		 8271}
8272
a724f0f4
JB		 8273/* e09 OFFSET e09
8274 | SHORT e09
8275 | + e09
8276 | - e09
8277 | ~ e09
8278 | NOT e09
9306ca4a
JB		 8279 | e10 e09'
8280
64a0c779 8281 e09' PTR e10 e09'
b77a7acd 8282 | : e10 e09'
64a0c779
DN		 8283 | Empty */
8284static int
e3bb37b5 8285intel_e09 (void)
64a0c779 8286{
a724f0f4
JB		 8287 int nregs = ~NUM_ADDRESS_REGS;
8288 int in_offset = 0;
8289
8290 for (;;)
64a0c779 8291 {
a724f0f4
JB		 8292 /* Don't consume constants here. */
8293 if (cur_token.code == '+' || cur_token.code == '-')
8294 {
8295 /* Need to look one token ahead - if the next token
8296 is a constant, the current token is its sign. */
8297 int next_code;
8298
8299 intel_match_token (cur_token.code);
8300 next_code = cur_token.code;
8301 intel_putback_token ();
8302 if (next_code == T_CONST)
8303 break;
8304 }
8305
8306 /* e09 OFFSET e09 */
8307 if (cur_token.code == T_OFFSET)
8308 {
8309 if (!in_offset++)
8310 ++intel_parser.in_offset;
8311 }
8312
8313 /* e09 SHORT e09 */
8314 else if (cur_token.code == T_SHORT)
8315 intel_parser.op_modifier |= 1 << T_SHORT;
8316
8317 /* e09 + e09 */
8318 else if (cur_token.code == '+')
8319 strcat (intel_parser.disp, "+");
8320
8321 /* e09 - e09
8322 | ~ e09
8323 | NOT e09 */
8324 else if (cur_token.code == '-' || cur_token.code == '~')
8325 {
8326 char str[2];
64a0c779 8327
a724f0f4
JB		 8328 if (nregs < 0)
8329 nregs = ~nregs;
8330 str[0] = cur_token.code;
8331 str[1] = 0;
8332 strcat (intel_parser.disp, str);
8333 }
8334
8335 /* e09 e10 e09' */
8336 else
8337 break;
8338
8339 intel_match_token (cur_token.code);
64a0c779
DN		 8340 }
8341
a724f0f4 8342 for (;;)
9306ca4a 8343 {
a724f0f4
JB		 8344 if (!intel_e10 ())
8345 return 0;
9306ca4a 8346
a724f0f4
JB		 8347 /* e09' PTR e10 e09' */
8348 if (cur_token.code == T_PTR)
8349 {
8350 char suffix;
9306ca4a 8351
a724f0f4 8352 if (prev_token.code == T_BYTE)
7d5e4556
L		 8353 {
8354 suffix = BYTE_MNEM_SUFFIX;
8355 i.types[this_operand].bitfield.byte = 1;
8356 }
9306ca4a 8357
a724f0f4
JB		 8358 else if (prev_token.code == T_WORD)
8359 {
34b772a6
JB		 8360 if ((current_templates->start->name[0] == 'l'
8361 && current_templates->start->name[2] == 's'
8362 && current_templates->start->name[3] == 0)
8363 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 8364 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8365 else if (intel_parser.got_a_float == 2) /* "fi..." */
8366 suffix = SHORT_MNEM_SUFFIX;
8367 else
8368 suffix = WORD_MNEM_SUFFIX;
7d5e4556 8369 i.types[this_operand].bitfield.word = 1;
a724f0f4 8370 }
64a0c779 8371
a724f0f4
JB		 8372 else if (prev_token.code == T_DWORD)
8373 {
34b772a6
JB		 8374 if ((current_templates->start->name[0] == 'l'
8375 && current_templates->start->name[2] == 's'
8376 && current_templates->start->name[3] == 0)
8377 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 8378 suffix = WORD_MNEM_SUFFIX;
8379 else if (flag_code == CODE_16BIT
40fb9820
L		 8380 && (current_templates->start->opcode_modifier.jump
8381 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 8382 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8383 else if (intel_parser.got_a_float == 1) /* "f..." */
8384 suffix = SHORT_MNEM_SUFFIX;
8385 else
8386 suffix = LONG_MNEM_SUFFIX;
7d5e4556 8387 i.types[this_operand].bitfield.dword = 1;
a724f0f4 8388 }
9306ca4a 8389
a724f0f4
JB		 8390 else if (prev_token.code == T_FWORD)
8391 {
8392 if (current_templates->start->name[0] == 'l'
8393 && current_templates->start->name[2] == 's'
8394 && current_templates->start->name[3] == 0)
8395 suffix = LONG_MNEM_SUFFIX;
8396 else if (!intel_parser.got_a_float)
8397 {
8398 if (flag_code == CODE_16BIT)
8399 add_prefix (DATA_PREFIX_OPCODE);
8400 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8401 }
8402 else
8403 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7d5e4556 8404 i.types[this_operand].bitfield.fword = 1;
a724f0f4 8405 }
64a0c779 8406
a724f0f4
JB		 8407 else if (prev_token.code == T_QWORD)
8408 {
34b772a6
JB		 8409 if (current_templates->start->base_opcode == 0x62 /* bound */
8410 || intel_parser.got_a_float == 1) /* "f..." */
a724f0f4
JB		 8411 suffix = LONG_MNEM_SUFFIX;
8412 else
34b772a6 8413 suffix = QWORD_MNEM_SUFFIX;
7d5e4556 8414 i.types[this_operand].bitfield.qword = 1;
a724f0f4 8415 }
64a0c779 8416
a724f0f4
JB		 8417 else if (prev_token.code == T_TBYTE)
8418 {
8419 if (intel_parser.got_a_float == 1)
8420 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8421 else
8422 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8423 }
9306ca4a 8424
a724f0f4 8425 else if (prev_token.code == T_XMMWORD)
9306ca4a 8426 {
582d5edd 8427 suffix = XMMWORD_MNEM_SUFFIX;
7d5e4556 8428 i.types[this_operand].bitfield.xmmword = 1;
9306ca4a 8429 }
64a0c779 8430
f16b83df 8431 else
a724f0f4
JB		 8432 {
8433 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8434 return 0;
8435 }
8436
7d5e4556
L		 8437 i.types[this_operand].bitfield.unspecified = 0;
8438
435acd52
JB		 8439 /* Operands for jump/call using 'ptr' notation denote absolute
8440 addresses. */
40fb9820
L		 8441 if (current_templates->start->opcode_modifier.jump
8442 || current_templates->start->opcode_modifier.jumpdword)
8443 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8444
a724f0f4
JB		 8445 if (current_templates->start->base_opcode == 0x8d /* lea */)
8446 ;
8447 else if (!i.suffix)
8448 i.suffix = suffix;
8449 else if (i.suffix != suffix)
8450 {
8451 as_bad (_("Conflicting operand modifiers"));
8452 return 0;
8453 }
64a0c779 8454
9306ca4a
JB		 8455 }
8456
a724f0f4
JB		 8457 /* e09' : e10 e09' */
8458 else if (cur_token.code == ':')
9306ca4a 8459 {
a724f0f4
JB		 8460 if (prev_token.code != T_REG)
8461 {
8462 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8463 segment/group identifier (which we don't have), using comma
8464 as the operand separator there is even less consistent, since
8465 there all branches only have a single operand. */
8466 if (this_operand != 0
8467 || intel_parser.in_offset
8468 || intel_parser.in_bracket
40fb9820
L		 8469 || (!current_templates->start->opcode_modifier.jump
8470 && !current_templates->start->opcode_modifier.jumpdword
8471 && !current_templates->start->opcode_modifier.jumpintersegment
8472 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 8473 return intel_match_token (T_NIL);
8474 /* Remember the start of the 2nd operand and terminate 1st
8475 operand here.
8476 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8477 another expression), but it gets at least the simplest case
8478 (a plain number or symbol on the left side) right. */
8479 intel_parser.next_operand = intel_parser.op_string;
8480 *--intel_parser.op_string = '\0';
8481 return intel_match_token (':');
8482 }
9306ca4a 8483 }
64a0c779 8484
a724f0f4 8485 /* e09' Empty */
64a0c779 8486 else
a724f0f4 8487 break;
64a0c779 8488
a724f0f4
JB		 8489 intel_match_token (cur_token.code);
8490
8491 }
8492
8493 if (in_offset)
8494 {
8495 --intel_parser.in_offset;
8496 if (nregs < 0)
8497 nregs = ~nregs;
8498 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 8499 {
a724f0f4 8500 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 8501 return 0;
8502 }
a724f0f4
JB		 8503 intel_parser.op_modifier |= 1 << T_OFFSET;
8504 }
9306ca4a 8505
a724f0f4
JB		 8506 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8507 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8508 return 1;
8509}
64a0c779 8510
a724f0f4 8511static int
e3bb37b5 8512intel_bracket_expr (void)
a724f0f4
JB		 8513{
8514 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8515 const char *start = intel_parser.op_string;
8516 int len;
8517
8518 if (i.op[this_operand].regs)
8519 return intel_match_token (T_NIL);
8520
8521 intel_match_token ('[');
8522
8523 /* Mark as a memory operand only if it's not already known to be an
8524 offset expression. If it's an offset expression, we need to keep
8525 the brace in. */
8526 if (!intel_parser.in_offset)
8527 {
8528 ++intel_parser.in_bracket;
435acd52
JB		 8529
8530 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 8531 if (current_templates->start->opcode_modifier.jump
8532 || current_templates->start->opcode_modifier.jumpdword)
8533 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8534
a724f0f4
JB		 8535 /* Unfortunately gas always diverged from MASM in a respect that can't
8536 be easily fixed without risking to break code sequences likely to be
8537 encountered (the testsuite even check for this): MASM doesn't consider
8538 an expression inside brackets unconditionally as a memory reference.
8539 When that is e.g. a constant, an offset expression, or the sum of the
8540 two, this is still taken as a constant load. gas, however, always
8541 treated these as memory references. As a compromise, we'll try to make
8542 offset expressions inside brackets work the MASM way (since that's
8543 less likely to be found in real world code), but make constants alone
8544 continue to work the traditional gas way. In either case, issue a
8545 warning. */
8546 intel_parser.op_modifier &= ~was_offset;
64a0c779 8547 }
a724f0f4 8548 else
64e74474 8549 strcat (intel_parser.disp, "[");
a724f0f4
JB		 8550
8551 /* Add a '+' to the displacement string if necessary. */
8552 if (*intel_parser.disp != '\0'
8553 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8554 strcat (intel_parser.disp, "+");
64a0c779 8555
a724f0f4
JB		 8556 if (intel_expr ()
8557 && (len = intel_parser.op_string - start - 1,
8558 intel_match_token (']')))
64a0c779 8559 {
a724f0f4
JB		 8560 /* Preserve brackets when the operand is an offset expression. */
8561 if (intel_parser.in_offset)
8562 strcat (intel_parser.disp, "]");
8563 else
8564 {
8565 --intel_parser.in_bracket;
8566 if (i.base_reg || i.index_reg)
8567 intel_parser.is_mem = 1;
8568 if (!intel_parser.is_mem)
8569 {
8570 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8571 /* Defer the warning until all of the operand was parsed. */
8572 intel_parser.is_mem = -1;
8573 else if (!quiet_warnings)
4eed87de
AM		 8574 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8575 len, start, len, start);
a724f0f4
JB		 8576 }
8577 }
8578 intel_parser.op_modifier |= was_offset;
64a0c779 8579
a724f0f4 8580 return 1;
64a0c779 8581 }
a724f0f4 8582 return 0;
64a0c779
DN		 8583}
8584
8585/* e10 e11 e10'
8586
8587 e10' [ expr ] e10'
b77a7acd 8588 | Empty */
64a0c779 8589static int
e3bb37b5 8590intel_e10 (void)
64a0c779 8591{
a724f0f4
JB		 8592 if (!intel_e11 ())
8593 return 0;
64a0c779 8594
a724f0f4 8595 while (cur_token.code == '[')
64a0c779 8596 {
a724f0f4 8597 if (!intel_bracket_expr ())
21d6c4af 8598 return 0;
64a0c779
DN		 8599 }
8600
a724f0f4 8601 return 1;
64a0c779
DN		 8602}
8603
64a0c779 8604/* e11 ( expr )
b77a7acd 8605 | [ expr ]
64a0c779
DN		 8606 | BYTE
8607 | WORD
8608 | DWORD
9306ca4a 8609 | FWORD
64a0c779 8610 | QWORD
9306ca4a
JB		 8611 | TBYTE
8612 | OWORD
8613 | XMMWORD
4a1805b1 8614 | $
64a0c779
DN		 8615 | .
8616 | register
8617 | id
8618 | constant */
8619static int
e3bb37b5 8620intel_e11 (void)
64a0c779 8621{
a724f0f4 8622 switch (cur_token.code)
64a0c779 8623 {
a724f0f4
JB		 8624 /* e11 ( expr ) */
8625 case '(':
64a0c779
DN		 8626 intel_match_token ('(');
8627 strcat (intel_parser.disp, "(");
8628
8629 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 8630 {
8631 strcat (intel_parser.disp, ")");
8632 return 1;
8633 }
a724f0f4 8634 return 0;
4a1805b1 8635
a724f0f4
JB		 8636 /* e11 [ expr ] */
8637 case '[':
a724f0f4 8638 return intel_bracket_expr ();
64a0c779 8639
a724f0f4
JB		 8640 /* e11 $
8641 | . */
8642 case '.':
64a0c779
DN		 8643 strcat (intel_parser.disp, cur_token.str);
8644 intel_match_token (cur_token.code);
21d6c4af
DN		 8645
8646 /* Mark as a memory operand only if it's not already known to be an
8647 offset expression. */
a724f0f4 8648 if (!intel_parser.in_offset)
21d6c4af 8649 intel_parser.is_mem = 1;
64a0c779
DN		 8650
8651 return 1;
64a0c779 8652
a724f0f4
JB		 8653 /* e11 register */
8654 case T_REG:
8655 {
8656 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 8657
a724f0f4 8658 intel_match_token (T_REG);
64a0c779 8659
a724f0f4
JB		 8660 /* Check for segment change. */
8661 if (cur_token.code == ':')
8662 {
40fb9820
L		 8663 if (!reg->reg_type.bitfield.sreg2
8664 && !reg->reg_type.bitfield.sreg3)
a724f0f4 8665 {
4eed87de
AM		 8666 as_bad (_("`%s' is not a valid segment register"),
8667 reg->reg_name);
a724f0f4
JB		 8668 return 0;
8669 }
8670 else if (i.seg[i.mem_operands])
8671 as_warn (_("Extra segment override ignored"));
8672 else
8673 {
8674 if (!intel_parser.in_offset)
8675 intel_parser.is_mem = 1;
8676 switch (reg->reg_num)
8677 {
8678 case 0:
8679 i.seg[i.mem_operands] = &es;
8680 break;
8681 case 1:
8682 i.seg[i.mem_operands] = &cs;
8683 break;
8684 case 2:
8685 i.seg[i.mem_operands] = &ss;
8686 break;
8687 case 3:
8688 i.seg[i.mem_operands] = &ds;
8689 break;
8690 case 4:
8691 i.seg[i.mem_operands] = &fs;
8692 break;
8693 case 5:
8694 i.seg[i.mem_operands] = &gs;
8695 break;
8696 }
8697 }
8698 }
64a0c779 8699
a724f0f4
JB		 8700 /* Not a segment register. Check for register scaling. */
8701 else if (cur_token.code == '*')
8702 {
8703 if (!intel_parser.in_bracket)
8704 {
8705 as_bad (_("Register scaling only allowed in memory operands"));
8706 return 0;
8707 }
64a0c779 8708
40fb9820 8709 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 8710 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8711 else if (i.index_reg)
8712 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 8713
a724f0f4
JB		 8714 /* What follows must be a valid scale. */
8715 intel_match_token ('*');
8716 i.index_reg = reg;
40fb9820 8717 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 8718
a724f0f4
JB		 8719 /* Set the scale after setting the register (otherwise,
8720 i386_scale will complain) */
8721 if (cur_token.code == '+' || cur_token.code == '-')
8722 {
8723 char *str, sign = cur_token.code;
8724 intel_match_token (cur_token.code);
8725 if (cur_token.code != T_CONST)
8726 {
8727 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8728 cur_token.str);
8729 return 0;
8730 }
8731 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8732 strcpy (str + 1, cur_token.str);
8733 *str = sign;
8734 if (!i386_scale (str))
8735 return 0;
8736 free (str);
8737 }
8738 else if (!i386_scale (cur_token.str))
64a0c779 8739 return 0;
a724f0f4
JB		 8740 intel_match_token (cur_token.code);
8741 }
64a0c779 8742
a724f0f4
JB		 8743 /* No scaling. If this is a memory operand, the register is either a
8744 base register (first occurrence) or an index register (second
8745 occurrence). */
7b0441f6 8746 else if (intel_parser.in_bracket)
a724f0f4 8747 {
64a0c779 8748
a724f0f4
JB		 8749 if (!i.base_reg)
8750 i.base_reg = reg;
8751 else if (!i.index_reg)
8752 i.index_reg = reg;
8753 else
8754 {
8755 as_bad (_("Too many register references in memory operand"));
8756 return 0;
8757 }
64a0c779 8758
40fb9820 8759 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 8760 }
4a1805b1 8761
4d1bb795
JB		 8762 /* It's neither base nor index. */
8763 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 8764 {
40fb9820
L		 8765 i386_operand_type temp = reg->reg_type;
8766 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8767 i.types[this_operand] = operand_type_or (i.types[this_operand],
8768 temp);
7d5e4556 8769 i.types[this_operand].bitfield.unspecified = 0;
a724f0f4
JB		 8770 i.op[this_operand].regs = reg;
8771 i.reg_operands++;
8772 }
8773 else
8774 {
8775 as_bad (_("Invalid use of register"));
8776 return 0;
8777 }
64a0c779 8778
a724f0f4
JB		 8779 /* Since registers are not part of the displacement string (except
8780 when we're parsing offset operands), we may need to remove any
8781 preceding '+' from the displacement string. */
8782 if (*intel_parser.disp != '\0'
8783 && !intel_parser.in_offset)
8784 {
8785 char *s = intel_parser.disp;
8786 s += strlen (s) - 1;
8787 if (*s == '+')
8788 *s = '\0';
8789 }
4a1805b1 8790
a724f0f4
JB		 8791 return 1;
8792 }
8793
8794 /* e11 BYTE
8795 | WORD
8796 | DWORD
8797 | FWORD
8798 | QWORD
8799 | TBYTE
8800 | OWORD
8801 | XMMWORD */
8802 case T_BYTE:
8803 case T_WORD:
8804 case T_DWORD:
8805 case T_FWORD:
8806 case T_QWORD:
8807 case T_TBYTE:
8808 case T_XMMWORD:
8809 intel_match_token (cur_token.code);
64a0c779 8810
a724f0f4
JB		 8811 if (cur_token.code == T_PTR)
8812 return 1;
8813
8814 /* It must have been an identifier. */
8815 intel_putback_token ();
8816 cur_token.code = T_ID;
8817 /* FALLTHRU */
8818
8819 /* e11 id
8820 | constant */
8821 case T_ID:
8822 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 8823 {
8824 symbolS *symbolP;
8825
a724f0f4
JB		 8826 /* The identifier represents a memory reference only if it's not
8827 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 8828 symbolP = symbol_find(cur_token.str);
8829 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8830 intel_parser.is_mem = 1;
8831 }
a724f0f4 8832 /* FALLTHRU */
64a0c779 8833
a724f0f4
JB		 8834 case T_CONST:
8835 case '-':
8836 case '+':
8837 {
8838 char *save_str, sign = 0;
64a0c779 8839
a724f0f4
JB		 8840 /* Allow constants that start with `+' or `-'. */
8841 if (cur_token.code == '-' || cur_token.code == '+')
8842 {
8843 sign = cur_token.code;
8844 intel_match_token (cur_token.code);
8845 if (cur_token.code != T_CONST)
8846 {
8847 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8848 cur_token.str);
8849 return 0;
8850 }
8851 }
64a0c779 8852
a724f0f4
JB		 8853 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8854 strcpy (save_str + !!sign, cur_token.str);
8855 if (sign)
8856 *save_str = sign;
64a0c779 8857
a724f0f4
JB		 8858 /* Get the next token to check for register scaling. */
8859 intel_match_token (cur_token.code);
64a0c779 8860
4eed87de
AM		 8861 /* Check if this constant is a scaling factor for an
8862 index register. */
a724f0f4
JB		 8863 if (cur_token.code == '*')
8864 {
8865 if (intel_match_token ('*') && cur_token.code == T_REG)
8866 {
8867 const reg_entry *reg = cur_token.reg;
8868
8869 if (!intel_parser.in_bracket)
8870 {
4eed87de
AM		 8871 as_bad (_("Register scaling only allowed "
8872 "in memory operands"));
a724f0f4
JB		 8873 return 0;
8874 }
8875
4eed87de
AM		 8876 /* Disallow things like [1*si].
8877 sp and esp are invalid as index. */
40fb9820 8878 if (reg->reg_type.bitfield.reg16)
4eed87de 8879 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 8880 else if (i.index_reg)
4eed87de 8881 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 8882
8883 /* The constant is followed by `* reg', so it must be
8884 a valid scale. */
8885 i.index_reg = reg;
40fb9820 8886 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 8887
8888 /* Set the scale after setting the register (otherwise,
8889 i386_scale will complain) */
8890 if (!i386_scale (save_str))
64a0c779 8891 return 0;
a724f0f4
JB		 8892 intel_match_token (T_REG);
8893
8894 /* Since registers are not part of the displacement
8895 string, we may need to remove any preceding '+' from
8896 the displacement string. */
8897 if (*intel_parser.disp != '\0')
8898 {
8899 char *s = intel_parser.disp;
8900 s += strlen (s) - 1;
8901 if (*s == '+')
8902 *s = '\0';
8903 }
8904
8905 free (save_str);
8906
8907 return 1;
8908 }
64a0c779 8909
a724f0f4
JB		 8910 /* The constant was not used for register scaling. Since we have
8911 already consumed the token following `*' we now need to put it
8912 back in the stream. */
64a0c779 8913 intel_putback_token ();
a724f0f4 8914 }
64a0c779 8915
a724f0f4
JB		 8916 /* Add the constant to the displacement string. */
8917 strcat (intel_parser.disp, save_str);
8918 free (save_str);
64a0c779 8919
a724f0f4
JB		 8920 return 1;
8921 }
64a0c779
DN		 8922 }
8923
64a0c779
DN		 8924 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8925 return 0;
8926}
8927
64a0c779
DN		 8928/* Match the given token against cur_token. If they match, read the next
8929 token from the operand string. */
8930static int
e3bb37b5 8931intel_match_token (int code)
64a0c779
DN		 8932{
8933 if (cur_token.code == code)
8934 {
8935 intel_get_token ();
8936 return 1;
8937 }
8938 else
8939 {
0477af35 8940 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 8941 return 0;
8942 }
8943}
8944
64a0c779
DN		 8945/* Read a new token from intel_parser.op_string and store it in cur_token. */
8946static void
e3bb37b5 8947intel_get_token (void)
64a0c779
DN		 8948{
8949 char *end_op;
8950 const reg_entry *reg;
8951 struct intel_token new_token;
8952
8953 new_token.code = T_NIL;
8954 new_token.reg = NULL;
8955 new_token.str = NULL;
8956
4a1805b1 8957 /* Free the memory allocated to the previous token and move
64a0c779
DN		 8958 cur_token to prev_token. */
8959 if (prev_token.str)
8960 free (prev_token.str);
8961
8962 prev_token = cur_token;
8963
8964 /* Skip whitespace. */
8965 while (is_space_char (*intel_parser.op_string))
8966 intel_parser.op_string++;
8967
8968 /* Return an empty token if we find nothing else on the line. */
8969 if (*intel_parser.op_string == '\0')
8970 {
8971 cur_token = new_token;
8972 return;
8973 }
8974
8975 /* The new token cannot be larger than the remainder of the operand
8976 string. */
a724f0f4 8977 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 8978 new_token.str[0] = '\0';
8979
8980 if (strchr ("0123456789", *intel_parser.op_string))
8981 {
8982 char *p = new_token.str;
8983 char *q = intel_parser.op_string;
8984 new_token.code = T_CONST;
8985
8986 /* Allow any kind of identifier char to encompass floating point and
8987 hexadecimal numbers. */
8988 while (is_identifier_char (*q))
8989 *p++ = *q++;
8990 *p = '\0';
8991
8992 /* Recognize special symbol names [0-9][bf]. */
8993 if (strlen (intel_parser.op_string) == 2
4a1805b1 8994 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 8995 || intel_parser.op_string[1] == 'f'))
8996 new_token.code = T_ID;
8997 }
8998
4d1bb795 8999 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 9000 {
4d1bb795
JB		 9001 size_t len = end_op - intel_parser.op_string;
9002
64a0c779
DN		 9003 new_token.code = T_REG;
9004 new_token.reg = reg;
9005
4d1bb795
JB		 9006 memcpy (new_token.str, intel_parser.op_string, len);
9007 new_token.str[len] = '\0';
64a0c779
DN		 9008 }
9009
9010 else if (is_identifier_char (*intel_parser.op_string))
9011 {
9012 char *p = new_token.str;
9013 char *q = intel_parser.op_string;
9014
9015 /* A '.' or '$' followed by an identifier char is an identifier.
9016 Otherwise, it's operator '.' followed by an expression. */
9017 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
9018 {
9306ca4a
JB		 9019 new_token.code = '.';
9020 new_token.str[0] = '.';
64a0c779
DN		 9021 new_token.str[1] = '\0';
9022 }
9023 else
9024 {
9025 while (is_identifier_char (*q) || *q == '@')
9026 *p++ = *q++;
9027 *p = '\0';
9028
9306ca4a
JB		 9029 if (strcasecmp (new_token.str, "NOT") == 0)
9030 new_token.code = '~';
9031
9032 else if (strcasecmp (new_token.str, "MOD") == 0)
9033 new_token.code = '%';
9034
9035 else if (strcasecmp (new_token.str, "AND") == 0)
9036 new_token.code = '&';
9037
9038 else if (strcasecmp (new_token.str, "OR") == 0)
9039 new_token.code = '|';
9040
9041 else if (strcasecmp (new_token.str, "XOR") == 0)
9042 new_token.code = '^';
9043
9044 else if (strcasecmp (new_token.str, "SHL") == 0)
9045 new_token.code = T_SHL;
9046
9047 else if (strcasecmp (new_token.str, "SHR") == 0)
9048 new_token.code = T_SHR;
9049
9050 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 9051 new_token.code = T_BYTE;
9052
9053 else if (strcasecmp (new_token.str, "WORD") == 0)
9054 new_token.code = T_WORD;
9055
9056 else if (strcasecmp (new_token.str, "DWORD") == 0)
9057 new_token.code = T_DWORD;
9058
9306ca4a
JB		 9059 else if (strcasecmp (new_token.str, "FWORD") == 0)
9060 new_token.code = T_FWORD;
9061
64a0c779
DN		 9062 else if (strcasecmp (new_token.str, "QWORD") == 0)
9063 new_token.code = T_QWORD;
9064
9306ca4a
JB		 9065 else if (strcasecmp (new_token.str, "TBYTE") == 0
9066 /* XXX remove (gcc still uses it) */
9067 || strcasecmp (new_token.str, "XWORD") == 0)
9068 new_token.code = T_TBYTE;
9069
9070 else if (strcasecmp (new_token.str, "XMMWORD") == 0
9071 || strcasecmp (new_token.str, "OWORD") == 0)
9072 new_token.code = T_XMMWORD;
64a0c779
DN		 9073
9074 else if (strcasecmp (new_token.str, "PTR") == 0)
9075 new_token.code = T_PTR;
9076
9077 else if (strcasecmp (new_token.str, "SHORT") == 0)
9078 new_token.code = T_SHORT;
9079
9080 else if (strcasecmp (new_token.str, "OFFSET") == 0)
9081 {
9082 new_token.code = T_OFFSET;
9083
9084 /* ??? This is not mentioned in the MASM grammar but gcc
9085 makes use of it with -mintel-syntax. OFFSET may be
9086 followed by FLAT: */
9087 if (strncasecmp (q, " FLAT:", 6) == 0)
9088 strcat (new_token.str, " FLAT:");
9089 }
9090
9091 /* ??? This is not mentioned in the MASM grammar. */
9092 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 9093 {
9094 new_token.code = T_OFFSET;
9095 if (*q == ':')
9096 strcat (new_token.str, ":");
9097 else
9098 as_bad (_("`:' expected"));
9099 }
64a0c779
DN		 9100
9101 else
9102 new_token.code = T_ID;
9103 }
9104 }
9105
9306ca4a
JB		 9106 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
9107 {
9108 new_token.code = *intel_parser.op_string;
9109 new_token.str[0] = *intel_parser.op_string;
9110 new_token.str[1] = '\0';
9111 }
9112
9113 else if (strchr ("<>", *intel_parser.op_string)
9114 && *intel_parser.op_string == *(intel_parser.op_string + 1))
9115 {
9116 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
9117 new_token.str[0] = *intel_parser.op_string;
9118 new_token.str[1] = *intel_parser.op_string;
9119 new_token.str[2] = '\0';
9120 }
9121
64a0c779 9122 else
0477af35 9123 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 9124
9125 intel_parser.op_string += strlen (new_token.str);
9126 cur_token = new_token;
9127}
9128
64a0c779
DN		 9129/* Put cur_token back into the token stream and make cur_token point to
9130 prev_token. */
9131static void
e3bb37b5 9132intel_putback_token (void)
64a0c779 9133{
a724f0f4
JB		 9134 if (cur_token.code != T_NIL)
9135 {
9136 intel_parser.op_string -= strlen (cur_token.str);
9137 free (cur_token.str);
9138 }
64a0c779 9139 cur_token = prev_token;
4a1805b1 9140
64a0c779
DN		 9141 /* Forget prev_token. */
9142 prev_token.code = T_NIL;
9143 prev_token.reg = NULL;
9144 prev_token.str = NULL;
9145}
54cfded0 9146
a60de03c
JB		 9147void
9148tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 9149{
a60de03c
JB		 9150 int saved_naked_reg;
9151 char saved_register_dot;
54cfded0 9152
a60de03c
JB		 9153 saved_naked_reg = allow_naked_reg;
9154 allow_naked_reg = 1;
9155 saved_register_dot = register_chars['.'];
9156 register_chars['.'] = '.';
9157 allow_pseudo_reg = 1;
9158 expression_and_evaluate (exp);
9159 allow_pseudo_reg = 0;
9160 register_chars['.'] = saved_register_dot;
9161 allow_naked_reg = saved_naked_reg;
9162
9163 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 9164 {
a60de03c
JB		 9165 if ((addressT) exp->X_add_number < i386_regtab_size)
9166 {
9167 exp->X_op = O_constant;
9168 exp->X_add_number = i386_regtab[exp->X_add_number]
9169 .dw2_regnum[flag_code >> 1];
9170 }
9171 else
9172 exp->X_op = O_illegal;
54cfded0 9173 }
54cfded0
AM		 9174}
9175
9176void
9177tc_x86_frame_initial_instructions (void)
9178{
a60de03c
JB		 9179 static unsigned int sp_regno[2];
9180
9181 if (!sp_regno[flag_code >> 1])
9182 {
9183 char *saved_input = input_line_pointer;
9184 char sp[][4] = {"esp", "rsp"};
9185 expressionS exp;
a4447b93 9186
a60de03c
JB		 9187 input_line_pointer = sp[flag_code >> 1];
9188 tc_x86_parse_to_dw2regnum (&exp);
9189 assert (exp.X_op == O_constant);
9190 sp_regno[flag_code >> 1] = exp.X_add_number;
9191 input_line_pointer = saved_input;
9192 }
a4447b93 9193
a60de03c 9194 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 9195 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 9196}
d2b2c203
DJ		 9197
9198int
9199i386_elf_section_type (const char *str, size_t len)
9200{
9201 if (flag_code == CODE_64BIT
9202 && len == sizeof ("unwind") - 1
9203 && strncmp (str, "unwind", 6) == 0)
9204 return SHT_X86_64_UNWIND;
9205
9206 return -1;
9207}
bb41ade5
AM		 9208
9209#ifdef TE_PE
9210void
9211tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9212{
9213 expressionS expr;
9214
9215 expr.X_op = O_secrel;
9216 expr.X_add_symbol = symbol;
9217 expr.X_add_number = 0;
9218 emit_expr (&expr, size);
9219}
9220#endif
3b22753a
L		 9221
9222#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9223/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9224
9225int
9226x86_64_section_letter (int letter, char **ptr_msg)
9227{
9228 if (flag_code == CODE_64BIT)
9229 {
9230 if (letter == 'l')
9231 return SHF_X86_64_LARGE;
9232
9233 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9234 }
3b22753a 9235 else
64e74474 9236 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9237 return -1;
9238}
9239
9240int
9241x86_64_section_word (char *str, size_t len)
9242{
8620418b 9243 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9244 return SHF_X86_64_LARGE;
9245
9246 return -1;
9247}
9248
9249static void
9250handle_large_common (int small ATTRIBUTE_UNUSED)
9251{
9252 if (flag_code != CODE_64BIT)
9253 {
9254 s_comm_internal (0, elf_common_parse);
9255 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9256 }
9257 else
9258 {
9259 static segT lbss_section;
9260 asection *saved_com_section_ptr = elf_com_section_ptr;
9261 asection *saved_bss_section = bss_section;
9262
9263 if (lbss_section == NULL)
9264 {
9265 flagword applicable;
9266 segT seg = now_seg;
9267 subsegT subseg = now_subseg;
9268
9269 /* The .lbss section is for local .largecomm symbols. */
9270 lbss_section = subseg_new (".lbss", 0);
9271 applicable = bfd_applicable_section_flags (stdoutput);
9272 bfd_set_section_flags (stdoutput, lbss_section,
9273 applicable & SEC_ALLOC);
9274 seg_info (lbss_section)->bss = 1;
9275
9276 subseg_set (seg, subseg);
9277 }
9278
9279 elf_com_section_ptr = &_bfd_elf_large_com_section;
9280 bss_section = lbss_section;
9281
9282 s_comm_internal (0, elf_common_parse);
9283
9284 elf_com_section_ptr = saved_com_section_ptr;
9285 bss_section = saved_bss_section;
9286 }
9287}
9288#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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