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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
82704155 | 2 | Copyright (C) 1989-2019 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
d2b2c203 | 33 | #include "elf/x86-64.h" |
40fb9820 | 34 | #include "opcodes/i386-init.h" |
252b5132 | 35 | |
41fd2579 L |
36 | #ifdef HAVE_LIMITS_H |
37 | #include <limits.h> | |
38 | #else | |
39 | #ifdef HAVE_SYS_PARAM_H | |
40 | #include <sys/param.h> | |
41 | #endif | |
42 | #ifndef INT_MAX | |
43 | #define INT_MAX (int) (((unsigned) (-1)) >> 1) | |
44 | #endif | |
45 | #endif | |
46 | ||
252b5132 RH |
47 | #ifndef REGISTER_WARNINGS |
48 | #define REGISTER_WARNINGS 1 | |
49 | #endif | |
50 | ||
c3332e24 | 51 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 52 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
53 | #endif |
54 | ||
29b0f896 AM |
55 | #ifndef DEFAULT_ARCH |
56 | #define DEFAULT_ARCH "i386" | |
246fcdee | 57 | #endif |
252b5132 | 58 | |
edde18a5 AM |
59 | #ifndef INLINE |
60 | #if __GNUC__ >= 2 | |
61 | #define INLINE __inline__ | |
62 | #else | |
63 | #define INLINE | |
64 | #endif | |
65 | #endif | |
66 | ||
6305a203 L |
67 | /* Prefixes will be emitted in the order defined below. |
68 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
69 | instruction, and so must come before any prefixes. | |
70 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 71 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
72 | #define WAIT_PREFIX 0 |
73 | #define SEG_PREFIX 1 | |
74 | #define ADDR_PREFIX 2 | |
75 | #define DATA_PREFIX 3 | |
c32fa91d | 76 | #define REP_PREFIX 4 |
42164a71 | 77 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 78 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 79 | #define LOCK_PREFIX 5 |
4e9ac44a L |
80 | #define REX_PREFIX 6 /* must come last. */ |
81 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
82 | |
83 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
84 | #define REGISTER_PREFIX '%' | |
85 | #define IMMEDIATE_PREFIX '$' | |
86 | #define ABSOLUTE_PREFIX '*' | |
87 | ||
88 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
89 | memory operand size in Intel syntax. */ | |
90 | #define WORD_MNEM_SUFFIX 'w' | |
91 | #define BYTE_MNEM_SUFFIX 'b' | |
92 | #define SHORT_MNEM_SUFFIX 's' | |
93 | #define LONG_MNEM_SUFFIX 'l' | |
94 | #define QWORD_MNEM_SUFFIX 'q' | |
6305a203 L |
95 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
96 | in instructions. */ | |
97 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
98 | ||
99 | #define END_OF_INSN '\0' | |
100 | ||
101 | /* | |
102 | 'templates' is for grouping together 'template' structures for opcodes | |
103 | of the same name. This is only used for storing the insns in the grand | |
104 | ole hash table of insns. | |
105 | The templates themselves start at START and range up to (but not including) | |
106 | END. | |
107 | */ | |
108 | typedef struct | |
109 | { | |
d3ce72d0 NC |
110 | const insn_template *start; |
111 | const insn_template *end; | |
6305a203 L |
112 | } |
113 | templates; | |
114 | ||
115 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
116 | typedef struct | |
117 | { | |
118 | unsigned int regmem; /* codes register or memory operand */ | |
119 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
120 | unsigned int mode; /* how to interpret regmem & reg */ | |
121 | } | |
122 | modrm_byte; | |
123 | ||
124 | /* x86-64 extension prefix. */ | |
125 | typedef int rex_byte; | |
126 | ||
6305a203 L |
127 | /* 386 opcode byte to code indirect addressing. */ |
128 | typedef struct | |
129 | { | |
130 | unsigned base; | |
131 | unsigned index; | |
132 | unsigned scale; | |
133 | } | |
134 | sib_byte; | |
135 | ||
6305a203 L |
136 | /* x86 arch names, types and features */ |
137 | typedef struct | |
138 | { | |
139 | const char *name; /* arch name */ | |
8a2c8fef | 140 | unsigned int len; /* arch string length */ |
6305a203 L |
141 | enum processor_type type; /* arch type */ |
142 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 143 | unsigned int skip; /* show_arch should skip this. */ |
6305a203 L |
144 | } |
145 | arch_entry; | |
146 | ||
293f5f65 L |
147 | /* Used to turn off indicated flags. */ |
148 | typedef struct | |
149 | { | |
150 | const char *name; /* arch name */ | |
151 | unsigned int len; /* arch string length */ | |
152 | i386_cpu_flags flags; /* cpu feature flags */ | |
153 | } | |
154 | noarch_entry; | |
155 | ||
78f12dd3 | 156 | static void update_code_flag (int, int); |
e3bb37b5 L |
157 | static void set_code_flag (int); |
158 | static void set_16bit_gcc_code_flag (int); | |
159 | static void set_intel_syntax (int); | |
1efbbeb4 | 160 | static void set_intel_mnemonic (int); |
db51cc60 | 161 | static void set_allow_index_reg (int); |
7bab8ab5 | 162 | static void set_check (int); |
e3bb37b5 | 163 | static void set_cpu_arch (int); |
6482c264 | 164 | #ifdef TE_PE |
e3bb37b5 | 165 | static void pe_directive_secrel (int); |
6482c264 | 166 | #endif |
e3bb37b5 L |
167 | static void signed_cons (int); |
168 | static char *output_invalid (int c); | |
ee86248c JB |
169 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
170 | const char *); | |
171 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
172 | const char *); | |
a7619375 | 173 | static int i386_att_operand (char *); |
e3bb37b5 | 174 | static int i386_intel_operand (char *, int); |
ee86248c JB |
175 | static int i386_intel_simplify (expressionS *); |
176 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
177 | static const reg_entry *parse_register (char *, char **); |
178 | static char *parse_insn (char *, char *); | |
179 | static char *parse_operands (char *, const char *); | |
180 | static void swap_operands (void); | |
4d456e3d | 181 | static void swap_2_operands (int, int); |
e3bb37b5 L |
182 | static void optimize_imm (void); |
183 | static void optimize_disp (void); | |
83b16ac6 | 184 | static const insn_template *match_template (char); |
e3bb37b5 L |
185 | static int check_string (void); |
186 | static int process_suffix (void); | |
187 | static int check_byte_reg (void); | |
188 | static int check_long_reg (void); | |
189 | static int check_qword_reg (void); | |
190 | static int check_word_reg (void); | |
191 | static int finalize_imm (void); | |
192 | static int process_operands (void); | |
193 | static const seg_entry *build_modrm_byte (void); | |
194 | static void output_insn (void); | |
195 | static void output_imm (fragS *, offsetT); | |
196 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 197 | #ifndef I386COFF |
e3bb37b5 | 198 | static void s_bss (int); |
252b5132 | 199 | #endif |
17d4e2a2 L |
200 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
201 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
b4a3a7b4 L |
202 | |
203 | /* GNU_PROPERTY_X86_ISA_1_USED. */ | |
204 | static unsigned int x86_isa_1_used; | |
205 | /* GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
206 | static unsigned int x86_feature_2_used; | |
207 | /* Generate x86 used ISA and feature properties. */ | |
208 | static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE; | |
17d4e2a2 | 209 | #endif |
252b5132 | 210 | |
a847613f | 211 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 212 | |
43234a1e L |
213 | /* This struct describes rounding control and SAE in the instruction. */ |
214 | struct RC_Operation | |
215 | { | |
216 | enum rc_type | |
217 | { | |
218 | rne = 0, | |
219 | rd, | |
220 | ru, | |
221 | rz, | |
222 | saeonly | |
223 | } type; | |
224 | int operand; | |
225 | }; | |
226 | ||
227 | static struct RC_Operation rc_op; | |
228 | ||
229 | /* The struct describes masking, applied to OPERAND in the instruction. | |
230 | MASK is a pointer to the corresponding mask register. ZEROING tells | |
231 | whether merging or zeroing mask is used. */ | |
232 | struct Mask_Operation | |
233 | { | |
234 | const reg_entry *mask; | |
235 | unsigned int zeroing; | |
236 | /* The operand where this operation is associated. */ | |
237 | int operand; | |
238 | }; | |
239 | ||
240 | static struct Mask_Operation mask_op; | |
241 | ||
242 | /* The struct describes broadcasting, applied to OPERAND. FACTOR is | |
243 | broadcast factor. */ | |
244 | struct Broadcast_Operation | |
245 | { | |
8e6e0792 | 246 | /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */ |
43234a1e L |
247 | int type; |
248 | ||
249 | /* Index of broadcasted operand. */ | |
250 | int operand; | |
4a1b91ea L |
251 | |
252 | /* Number of bytes to broadcast. */ | |
253 | int bytes; | |
43234a1e L |
254 | }; |
255 | ||
256 | static struct Broadcast_Operation broadcast_op; | |
257 | ||
c0f3af97 L |
258 | /* VEX prefix. */ |
259 | typedef struct | |
260 | { | |
43234a1e L |
261 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
262 | unsigned char bytes[4]; | |
c0f3af97 L |
263 | unsigned int length; |
264 | /* Destination or source register specifier. */ | |
265 | const reg_entry *register_specifier; | |
266 | } vex_prefix; | |
267 | ||
252b5132 | 268 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 269 | i386_insn. */ |
252b5132 | 270 | |
520dc8e8 AM |
271 | union i386_op |
272 | { | |
273 | expressionS *disps; | |
274 | expressionS *imms; | |
275 | const reg_entry *regs; | |
276 | }; | |
277 | ||
a65babc9 L |
278 | enum i386_error |
279 | { | |
86e026a4 | 280 | operand_size_mismatch, |
a65babc9 L |
281 | operand_type_mismatch, |
282 | register_type_mismatch, | |
283 | number_of_operands_mismatch, | |
284 | invalid_instruction_suffix, | |
285 | bad_imm4, | |
a65babc9 L |
286 | unsupported_with_intel_mnemonic, |
287 | unsupported_syntax, | |
6c30d220 L |
288 | unsupported, |
289 | invalid_vsib_address, | |
7bab8ab5 | 290 | invalid_vector_register_set, |
43234a1e L |
291 | unsupported_vector_index_register, |
292 | unsupported_broadcast, | |
43234a1e L |
293 | broadcast_needed, |
294 | unsupported_masking, | |
295 | mask_not_on_destination, | |
296 | no_default_mask, | |
297 | unsupported_rc_sae, | |
298 | rc_sae_operand_not_last_imm, | |
299 | invalid_register_operand, | |
a65babc9 L |
300 | }; |
301 | ||
252b5132 RH |
302 | struct _i386_insn |
303 | { | |
47926f60 | 304 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 305 | insn_template tm; |
252b5132 | 306 | |
7d5e4556 L |
307 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
308 | or qword, if given. */ | |
252b5132 RH |
309 | char suffix; |
310 | ||
47926f60 | 311 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
312 | unsigned int operands; |
313 | ||
314 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
315 | of given register, displacement, memory operands and immediate | |
47926f60 | 316 | operands. */ |
252b5132 RH |
317 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
318 | ||
319 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 320 | use OP[i] for the corresponding operand. */ |
40fb9820 | 321 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 322 | |
520dc8e8 AM |
323 | /* Displacement expression, immediate expression, or register for each |
324 | operand. */ | |
325 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 326 | |
3e73aa7c JH |
327 | /* Flags for operands. */ |
328 | unsigned int flags[MAX_OPERANDS]; | |
329 | #define Operand_PCrel 1 | |
c48dadc9 | 330 | #define Operand_Mem 2 |
3e73aa7c | 331 | |
252b5132 | 332 | /* Relocation type for operand */ |
f86103b7 | 333 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 334 | |
252b5132 RH |
335 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
336 | the base index byte below. */ | |
337 | const reg_entry *base_reg; | |
338 | const reg_entry *index_reg; | |
339 | unsigned int log2_scale_factor; | |
340 | ||
341 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 342 | explicit segment overrides are given. */ |
ce8a8b2f | 343 | const seg_entry *seg[2]; |
252b5132 | 344 | |
8325cc63 JB |
345 | /* Copied first memory operand string, for re-checking. */ |
346 | char *memop1_string; | |
347 | ||
252b5132 RH |
348 | /* PREFIX holds all the given prefix opcodes (usually null). |
349 | PREFIXES is the number of prefix opcodes. */ | |
350 | unsigned int prefixes; | |
351 | unsigned char prefix[MAX_PREFIXES]; | |
352 | ||
b4a3a7b4 L |
353 | /* Has MMX register operands. */ |
354 | bfd_boolean has_regmmx; | |
355 | ||
356 | /* Has XMM register operands. */ | |
357 | bfd_boolean has_regxmm; | |
358 | ||
359 | /* Has YMM register operands. */ | |
360 | bfd_boolean has_regymm; | |
361 | ||
362 | /* Has ZMM register operands. */ | |
363 | bfd_boolean has_regzmm; | |
364 | ||
252b5132 | 365 | /* RM and SIB are the modrm byte and the sib byte where the |
c1e679ec | 366 | addressing modes of this insn are encoded. */ |
252b5132 | 367 | modrm_byte rm; |
3e73aa7c | 368 | rex_byte rex; |
43234a1e | 369 | rex_byte vrex; |
252b5132 | 370 | sib_byte sib; |
c0f3af97 | 371 | vex_prefix vex; |
b6169b20 | 372 | |
43234a1e L |
373 | /* Masking attributes. */ |
374 | struct Mask_Operation *mask; | |
375 | ||
376 | /* Rounding control and SAE attributes. */ | |
377 | struct RC_Operation *rounding; | |
378 | ||
379 | /* Broadcasting attributes. */ | |
380 | struct Broadcast_Operation *broadcast; | |
381 | ||
382 | /* Compressed disp8*N attribute. */ | |
383 | unsigned int memshift; | |
384 | ||
86fa6981 L |
385 | /* Prefer load or store in encoding. */ |
386 | enum | |
387 | { | |
388 | dir_encoding_default = 0, | |
389 | dir_encoding_load, | |
64c49ab3 JB |
390 | dir_encoding_store, |
391 | dir_encoding_swap | |
86fa6981 | 392 | } dir_encoding; |
891edac4 | 393 | |
a501d77e L |
394 | /* Prefer 8bit or 32bit displacement in encoding. */ |
395 | enum | |
396 | { | |
397 | disp_encoding_default = 0, | |
398 | disp_encoding_8bit, | |
399 | disp_encoding_32bit | |
400 | } disp_encoding; | |
f8a5c266 | 401 | |
6b6b6807 L |
402 | /* Prefer the REX byte in encoding. */ |
403 | bfd_boolean rex_encoding; | |
404 | ||
b6f8c7c4 L |
405 | /* Disable instruction size optimization. */ |
406 | bfd_boolean no_optimize; | |
407 | ||
86fa6981 L |
408 | /* How to encode vector instructions. */ |
409 | enum | |
410 | { | |
411 | vex_encoding_default = 0, | |
412 | vex_encoding_vex2, | |
413 | vex_encoding_vex3, | |
414 | vex_encoding_evex | |
415 | } vec_encoding; | |
416 | ||
d5de92cf L |
417 | /* REP prefix. */ |
418 | const char *rep_prefix; | |
419 | ||
165de32a L |
420 | /* HLE prefix. */ |
421 | const char *hle_prefix; | |
42164a71 | 422 | |
7e8b059b L |
423 | /* Have BND prefix. */ |
424 | const char *bnd_prefix; | |
425 | ||
04ef582a L |
426 | /* Have NOTRACK prefix. */ |
427 | const char *notrack_prefix; | |
428 | ||
891edac4 | 429 | /* Error message. */ |
a65babc9 | 430 | enum i386_error error; |
252b5132 RH |
431 | }; |
432 | ||
433 | typedef struct _i386_insn i386_insn; | |
434 | ||
43234a1e L |
435 | /* Link RC type with corresponding string, that'll be looked for in |
436 | asm. */ | |
437 | struct RC_name | |
438 | { | |
439 | enum rc_type type; | |
440 | const char *name; | |
441 | unsigned int len; | |
442 | }; | |
443 | ||
444 | static const struct RC_name RC_NamesTable[] = | |
445 | { | |
446 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
447 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
448 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
449 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
450 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
451 | }; | |
452 | ||
252b5132 RH |
453 | /* List of chars besides those in app.c:symbol_chars that can start an |
454 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 455 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 456 | #ifdef LEX_AT |
32137342 NC |
457 | "@" |
458 | #endif | |
459 | #ifdef LEX_QM | |
460 | "?" | |
252b5132 | 461 | #endif |
32137342 | 462 | ; |
252b5132 | 463 | |
29b0f896 AM |
464 | #if (defined (TE_I386AIX) \ |
465 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 466 | && !defined (TE_GNU) \ |
29b0f896 | 467 | && !defined (TE_LINUX) \ |
8d63c93e | 468 | && !defined (TE_NACL) \ |
29b0f896 | 469 | && !defined (TE_FreeBSD) \ |
5b806d27 | 470 | && !defined (TE_DragonFly) \ |
29b0f896 | 471 | && !defined (TE_NetBSD))) |
252b5132 | 472 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
473 | pre-processor is disabled, these aren't very useful. The option |
474 | --divide will remove '/' from this list. */ | |
475 | const char *i386_comment_chars = "#/"; | |
476 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 477 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 478 | |
b3b91714 AM |
479 | #else |
480 | const char *i386_comment_chars = "#"; | |
481 | #define PREFIX_SEPARATOR '/' | |
482 | #endif | |
483 | ||
252b5132 RH |
484 | /* This array holds the chars that only start a comment at the beginning of |
485 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
486 | .line and .file directives will appear in the pre-processed output. |
487 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 488 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
489 | #NO_APP at the beginning of its output. |
490 | Also note that comments started like this one will always work if | |
252b5132 | 491 | '/' isn't otherwise defined. */ |
b3b91714 | 492 | const char line_comment_chars[] = "#/"; |
252b5132 | 493 | |
63a0b638 | 494 | const char line_separator_chars[] = ";"; |
252b5132 | 495 | |
ce8a8b2f AM |
496 | /* Chars that can be used to separate mant from exp in floating point |
497 | nums. */ | |
252b5132 RH |
498 | const char EXP_CHARS[] = "eE"; |
499 | ||
ce8a8b2f AM |
500 | /* Chars that mean this number is a floating point constant |
501 | As in 0f12.456 | |
502 | or 0d1.2345e12. */ | |
252b5132 RH |
503 | const char FLT_CHARS[] = "fFdDxX"; |
504 | ||
ce8a8b2f | 505 | /* Tables for lexical analysis. */ |
252b5132 RH |
506 | static char mnemonic_chars[256]; |
507 | static char register_chars[256]; | |
508 | static char operand_chars[256]; | |
509 | static char identifier_chars[256]; | |
510 | static char digit_chars[256]; | |
511 | ||
ce8a8b2f | 512 | /* Lexical macros. */ |
252b5132 RH |
513 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
514 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
515 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
516 | #define is_space_char(x) ((x) == ' ') | |
517 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
518 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
519 | ||
0234cb7c | 520 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
521 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
522 | ||
523 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
524 | effect this we maintain a stack of saved characters that we've smashed | |
525 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 526 | assembler instruction). */ |
252b5132 | 527 | static char save_stack[32]; |
ce8a8b2f | 528 | static char *save_stack_p; |
252b5132 RH |
529 | #define END_STRING_AND_SAVE(s) \ |
530 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
531 | #define RESTORE_END_STRING(s) \ | |
532 | do { *(s) = *--save_stack_p; } while (0) | |
533 | ||
47926f60 | 534 | /* The instruction we're assembling. */ |
252b5132 RH |
535 | static i386_insn i; |
536 | ||
537 | /* Possible templates for current insn. */ | |
538 | static const templates *current_templates; | |
539 | ||
31b2323c L |
540 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
541 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
542 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 543 | |
47926f60 | 544 | /* Current operand we are working on. */ |
ee86248c | 545 | static int this_operand = -1; |
252b5132 | 546 | |
3e73aa7c JH |
547 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
548 | these. */ | |
549 | ||
550 | enum flag_code { | |
551 | CODE_32BIT, | |
552 | CODE_16BIT, | |
553 | CODE_64BIT }; | |
554 | ||
555 | static enum flag_code flag_code; | |
4fa24527 | 556 | static unsigned int object_64bit; |
862be3fb | 557 | static unsigned int disallow_64bit_reloc; |
3e73aa7c JH |
558 | static int use_rela_relocations = 0; |
559 | ||
7af8ed2d NC |
560 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
561 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
562 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
563 | ||
351f65ca L |
564 | /* The ELF ABI to use. */ |
565 | enum x86_elf_abi | |
566 | { | |
567 | I386_ABI, | |
7f56bc95 L |
568 | X86_64_ABI, |
569 | X86_64_X32_ABI | |
351f65ca L |
570 | }; |
571 | ||
572 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 573 | #endif |
351f65ca | 574 | |
167ad85b TG |
575 | #if defined (TE_PE) || defined (TE_PEP) |
576 | /* Use big object file format. */ | |
577 | static int use_big_obj = 0; | |
578 | #endif | |
579 | ||
8dcea932 L |
580 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
581 | /* 1 if generating code for a shared library. */ | |
582 | static int shared = 0; | |
583 | #endif | |
584 | ||
47926f60 KH |
585 | /* 1 for intel syntax, |
586 | 0 if att syntax. */ | |
587 | static int intel_syntax = 0; | |
252b5132 | 588 | |
e89c5eaa L |
589 | /* 1 for Intel64 ISA, |
590 | 0 if AMD64 ISA. */ | |
591 | static int intel64; | |
592 | ||
1efbbeb4 L |
593 | /* 1 for intel mnemonic, |
594 | 0 if att mnemonic. */ | |
595 | static int intel_mnemonic = !SYSV386_COMPAT; | |
596 | ||
a60de03c JB |
597 | /* 1 if pseudo registers are permitted. */ |
598 | static int allow_pseudo_reg = 0; | |
599 | ||
47926f60 KH |
600 | /* 1 if register prefix % not required. */ |
601 | static int allow_naked_reg = 0; | |
252b5132 | 602 | |
33eaf5de | 603 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
604 | instructions supporting it, even if this prefix wasn't specified |
605 | explicitly. */ | |
606 | static int add_bnd_prefix = 0; | |
607 | ||
ba104c83 | 608 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
609 | static int allow_index_reg = 0; |
610 | ||
d022bddd IT |
611 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
612 | specified explicitly. */ | |
613 | static int omit_lock_prefix = 0; | |
614 | ||
e4e00185 AS |
615 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
616 | "lock addl $0, (%{re}sp)". */ | |
617 | static int avoid_fence = 0; | |
618 | ||
0cb4071e L |
619 | /* 1 if the assembler should generate relax relocations. */ |
620 | ||
621 | static int generate_relax_relocations | |
622 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
623 | ||
7bab8ab5 | 624 | static enum check_kind |
daf50ae7 | 625 | { |
7bab8ab5 JB |
626 | check_none = 0, |
627 | check_warning, | |
628 | check_error | |
daf50ae7 | 629 | } |
7bab8ab5 | 630 | sse_check, operand_check = check_warning; |
daf50ae7 | 631 | |
b6f8c7c4 L |
632 | /* Optimization: |
633 | 1. Clear the REX_W bit with register operand if possible. | |
634 | 2. Above plus use 128bit vector instruction to clear the full vector | |
635 | register. | |
636 | */ | |
637 | static int optimize = 0; | |
638 | ||
639 | /* Optimization: | |
640 | 1. Clear the REX_W bit with register operand if possible. | |
641 | 2. Above plus use 128bit vector instruction to clear the full vector | |
642 | register. | |
643 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to | |
644 | "testb $imm7,%r8". | |
645 | */ | |
646 | static int optimize_for_space = 0; | |
647 | ||
2ca3ace5 L |
648 | /* Register prefix used for error message. */ |
649 | static const char *register_prefix = "%"; | |
650 | ||
47926f60 KH |
651 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
652 | leave, push, and pop instructions so that gcc has the same stack | |
653 | frame as in 32 bit mode. */ | |
654 | static char stackop_size = '\0'; | |
eecb386c | 655 | |
12b55ccc L |
656 | /* Non-zero to optimize code alignment. */ |
657 | int optimize_align_code = 1; | |
658 | ||
47926f60 KH |
659 | /* Non-zero to quieten some warnings. */ |
660 | static int quiet_warnings = 0; | |
a38cf1db | 661 | |
47926f60 KH |
662 | /* CPU name. */ |
663 | static const char *cpu_arch_name = NULL; | |
6305a203 | 664 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 665 | |
47926f60 | 666 | /* CPU feature flags. */ |
40fb9820 L |
667 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
668 | ||
ccc9c027 L |
669 | /* If we have selected a cpu we are generating instructions for. */ |
670 | static int cpu_arch_tune_set = 0; | |
671 | ||
9103f4f4 | 672 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 673 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
674 | |
675 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 676 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 677 | |
ccc9c027 | 678 | /* CPU instruction set architecture used. */ |
fbf3f584 | 679 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 680 | |
9103f4f4 | 681 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 682 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 683 | |
fddf5b5b AM |
684 | /* If set, conditional jumps are not automatically promoted to handle |
685 | larger than a byte offset. */ | |
686 | static unsigned int no_cond_jump_promotion = 0; | |
687 | ||
c0f3af97 L |
688 | /* Encode SSE instructions with VEX prefix. */ |
689 | static unsigned int sse2avx; | |
690 | ||
539f890d L |
691 | /* Encode scalar AVX instructions with specific vector length. */ |
692 | static enum | |
693 | { | |
694 | vex128 = 0, | |
695 | vex256 | |
696 | } avxscalar; | |
697 | ||
03751133 L |
698 | /* Encode VEX WIG instructions with specific vex.w. */ |
699 | static enum | |
700 | { | |
701 | vexw0 = 0, | |
702 | vexw1 | |
703 | } vexwig; | |
704 | ||
43234a1e L |
705 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
706 | static enum | |
707 | { | |
708 | evexl128 = 0, | |
709 | evexl256, | |
710 | evexl512 | |
711 | } evexlig; | |
712 | ||
713 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
714 | static enum | |
715 | { | |
716 | evexw0 = 0, | |
717 | evexw1 | |
718 | } evexwig; | |
719 | ||
d3d3c6db IT |
720 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
721 | static enum rc_type evexrcig = rne; | |
722 | ||
29b0f896 | 723 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 724 | static symbolS *GOT_symbol; |
29b0f896 | 725 | |
a4447b93 RH |
726 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
727 | unsigned int x86_dwarf2_return_column; | |
728 | ||
729 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
730 | int x86_cie_data_alignment; | |
731 | ||
252b5132 | 732 | /* Interface to relax_segment. |
fddf5b5b AM |
733 | There are 3 major relax states for 386 jump insns because the |
734 | different types of jumps add different sizes to frags when we're | |
735 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 736 | |
47926f60 | 737 | /* Types. */ |
93c2a809 AM |
738 | #define UNCOND_JUMP 0 |
739 | #define COND_JUMP 1 | |
740 | #define COND_JUMP86 2 | |
fddf5b5b | 741 | |
47926f60 | 742 | /* Sizes. */ |
252b5132 RH |
743 | #define CODE16 1 |
744 | #define SMALL 0 | |
29b0f896 | 745 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 746 | #define BIG 2 |
29b0f896 | 747 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
748 | |
749 | #ifndef INLINE | |
750 | #ifdef __GNUC__ | |
751 | #define INLINE __inline__ | |
752 | #else | |
753 | #define INLINE | |
754 | #endif | |
755 | #endif | |
756 | ||
fddf5b5b AM |
757 | #define ENCODE_RELAX_STATE(type, size) \ |
758 | ((relax_substateT) (((type) << 2) | (size))) | |
759 | #define TYPE_FROM_RELAX_STATE(s) \ | |
760 | ((s) >> 2) | |
761 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
762 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
763 | |
764 | /* This table is used by relax_frag to promote short jumps to long | |
765 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
766 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
767 | don't allow a short jump in a 32 bit code segment to be promoted to | |
768 | a 16 bit offset jump because it's slower (requires data size | |
769 | prefix), and doesn't work, unless the destination is in the bottom | |
770 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
771 | ||
772 | const relax_typeS md_relax_table[] = | |
773 | { | |
24eab124 AM |
774 | /* The fields are: |
775 | 1) most positive reach of this state, | |
776 | 2) most negative reach of this state, | |
93c2a809 | 777 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 778 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 779 | |
fddf5b5b | 780 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
781 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
782 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
783 | /* dword jmp adds 4 bytes to frag: | |
784 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 785 | {0, 0, 4, 0}, |
93c2a809 AM |
786 | /* word jmp adds 2 byte2 to frag: |
787 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
788 | {0, 0, 2, 0}, |
789 | ||
93c2a809 AM |
790 | /* COND_JUMP states. */ |
791 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
792 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
793 | /* dword conditionals adds 5 bytes to frag: | |
794 | 1 extra opcode byte, 4 displacement bytes. */ | |
795 | {0, 0, 5, 0}, | |
fddf5b5b | 796 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
797 | 1 extra opcode byte, 2 displacement bytes. */ |
798 | {0, 0, 3, 0}, | |
799 | ||
800 | /* COND_JUMP86 states. */ | |
801 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
802 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
803 | /* dword conditionals adds 5 bytes to frag: | |
804 | 1 extra opcode byte, 4 displacement bytes. */ | |
805 | {0, 0, 5, 0}, | |
806 | /* word conditionals add 4 bytes to frag: | |
807 | 1 displacement byte and a 3 byte long branch insn. */ | |
808 | {0, 0, 4, 0} | |
252b5132 RH |
809 | }; |
810 | ||
9103f4f4 L |
811 | static const arch_entry cpu_arch[] = |
812 | { | |
89507696 JB |
813 | /* Do not replace the first two entries - i386_target_format() |
814 | relies on them being there in this order. */ | |
8a2c8fef | 815 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
293f5f65 | 816 | CPU_GENERIC32_FLAGS, 0 }, |
8a2c8fef | 817 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
293f5f65 | 818 | CPU_GENERIC64_FLAGS, 0 }, |
8a2c8fef | 819 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
293f5f65 | 820 | CPU_NONE_FLAGS, 0 }, |
8a2c8fef | 821 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
293f5f65 | 822 | CPU_I186_FLAGS, 0 }, |
8a2c8fef | 823 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
293f5f65 | 824 | CPU_I286_FLAGS, 0 }, |
8a2c8fef | 825 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
293f5f65 | 826 | CPU_I386_FLAGS, 0 }, |
8a2c8fef | 827 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
293f5f65 | 828 | CPU_I486_FLAGS, 0 }, |
8a2c8fef | 829 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
293f5f65 | 830 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 831 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 832 | CPU_I686_FLAGS, 0 }, |
8a2c8fef | 833 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
293f5f65 | 834 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 835 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 836 | CPU_PENTIUMPRO_FLAGS, 0 }, |
8a2c8fef | 837 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 838 | CPU_P2_FLAGS, 0 }, |
8a2c8fef | 839 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
293f5f65 | 840 | CPU_P3_FLAGS, 0 }, |
8a2c8fef | 841 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
293f5f65 | 842 | CPU_P4_FLAGS, 0 }, |
8a2c8fef | 843 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
293f5f65 | 844 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 845 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
293f5f65 | 846 | CPU_NOCONA_FLAGS, 0 }, |
8a2c8fef | 847 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
293f5f65 | 848 | CPU_CORE_FLAGS, 1 }, |
8a2c8fef | 849 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
293f5f65 | 850 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 851 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
293f5f65 | 852 | CPU_CORE2_FLAGS, 1 }, |
8a2c8fef | 853 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
293f5f65 | 854 | CPU_CORE2_FLAGS, 0 }, |
8a2c8fef | 855 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
293f5f65 | 856 | CPU_COREI7_FLAGS, 0 }, |
8a2c8fef | 857 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
293f5f65 | 858 | CPU_L1OM_FLAGS, 0 }, |
7a9068fe | 859 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
293f5f65 | 860 | CPU_K1OM_FLAGS, 0 }, |
81486035 | 861 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
293f5f65 | 862 | CPU_IAMCU_FLAGS, 0 }, |
8a2c8fef | 863 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
293f5f65 | 864 | CPU_K6_FLAGS, 0 }, |
8a2c8fef | 865 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
293f5f65 | 866 | CPU_K6_2_FLAGS, 0 }, |
8a2c8fef | 867 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
293f5f65 | 868 | CPU_ATHLON_FLAGS, 0 }, |
8a2c8fef | 869 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
293f5f65 | 870 | CPU_K8_FLAGS, 1 }, |
8a2c8fef | 871 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
293f5f65 | 872 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 873 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
293f5f65 | 874 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 875 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
293f5f65 | 876 | CPU_AMDFAM10_FLAGS, 0 }, |
8aedb9fe | 877 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
293f5f65 | 878 | CPU_BDVER1_FLAGS, 0 }, |
8aedb9fe | 879 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
293f5f65 | 880 | CPU_BDVER2_FLAGS, 0 }, |
5e5c50d3 | 881 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
293f5f65 | 882 | CPU_BDVER3_FLAGS, 0 }, |
c7b0bd56 | 883 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
293f5f65 | 884 | CPU_BDVER4_FLAGS, 0 }, |
029f3522 | 885 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
293f5f65 | 886 | CPU_ZNVER1_FLAGS, 0 }, |
a9660a6f AP |
887 | { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER, |
888 | CPU_ZNVER2_FLAGS, 0 }, | |
7b458c12 | 889 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
293f5f65 | 890 | CPU_BTVER1_FLAGS, 0 }, |
7b458c12 | 891 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
293f5f65 | 892 | CPU_BTVER2_FLAGS, 0 }, |
8a2c8fef | 893 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
293f5f65 | 894 | CPU_8087_FLAGS, 0 }, |
8a2c8fef | 895 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
293f5f65 | 896 | CPU_287_FLAGS, 0 }, |
8a2c8fef | 897 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
293f5f65 | 898 | CPU_387_FLAGS, 0 }, |
1848e567 L |
899 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
900 | CPU_687_FLAGS, 0 }, | |
d871f3f4 L |
901 | { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN, |
902 | CPU_CMOV_FLAGS, 0 }, | |
903 | { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN, | |
904 | CPU_FXSR_FLAGS, 0 }, | |
8a2c8fef | 905 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 906 | CPU_MMX_FLAGS, 0 }, |
8a2c8fef | 907 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
293f5f65 | 908 | CPU_SSE_FLAGS, 0 }, |
8a2c8fef | 909 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
293f5f65 | 910 | CPU_SSE2_FLAGS, 0 }, |
8a2c8fef | 911 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 912 | CPU_SSE3_FLAGS, 0 }, |
8a2c8fef | 913 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 914 | CPU_SSSE3_FLAGS, 0 }, |
8a2c8fef | 915 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
293f5f65 | 916 | CPU_SSE4_1_FLAGS, 0 }, |
8a2c8fef | 917 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
293f5f65 | 918 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 919 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
293f5f65 | 920 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 921 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
293f5f65 | 922 | CPU_AVX_FLAGS, 0 }, |
6c30d220 | 923 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
293f5f65 | 924 | CPU_AVX2_FLAGS, 0 }, |
43234a1e | 925 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
293f5f65 | 926 | CPU_AVX512F_FLAGS, 0 }, |
43234a1e | 927 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
293f5f65 | 928 | CPU_AVX512CD_FLAGS, 0 }, |
43234a1e | 929 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
293f5f65 | 930 | CPU_AVX512ER_FLAGS, 0 }, |
43234a1e | 931 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
293f5f65 | 932 | CPU_AVX512PF_FLAGS, 0 }, |
1dfc6506 | 933 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
293f5f65 | 934 | CPU_AVX512DQ_FLAGS, 0 }, |
1dfc6506 | 935 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
293f5f65 | 936 | CPU_AVX512BW_FLAGS, 0 }, |
1dfc6506 | 937 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
293f5f65 | 938 | CPU_AVX512VL_FLAGS, 0 }, |
8a2c8fef | 939 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 940 | CPU_VMX_FLAGS, 0 }, |
8729a6f6 | 941 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
293f5f65 | 942 | CPU_VMFUNC_FLAGS, 0 }, |
8a2c8fef | 943 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
293f5f65 | 944 | CPU_SMX_FLAGS, 0 }, |
8a2c8fef | 945 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
293f5f65 | 946 | CPU_XSAVE_FLAGS, 0 }, |
c7b8aa3a | 947 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 948 | CPU_XSAVEOPT_FLAGS, 0 }, |
1dfc6506 | 949 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
293f5f65 | 950 | CPU_XSAVEC_FLAGS, 0 }, |
1dfc6506 | 951 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
293f5f65 | 952 | CPU_XSAVES_FLAGS, 0 }, |
8a2c8fef | 953 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
293f5f65 | 954 | CPU_AES_FLAGS, 0 }, |
8a2c8fef | 955 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 956 | CPU_PCLMUL_FLAGS, 0 }, |
8a2c8fef | 957 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 958 | CPU_PCLMUL_FLAGS, 1 }, |
c7b8aa3a | 959 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
293f5f65 | 960 | CPU_FSGSBASE_FLAGS, 0 }, |
c7b8aa3a | 961 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
293f5f65 | 962 | CPU_RDRND_FLAGS, 0 }, |
c7b8aa3a | 963 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
293f5f65 | 964 | CPU_F16C_FLAGS, 0 }, |
6c30d220 | 965 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
293f5f65 | 966 | CPU_BMI2_FLAGS, 0 }, |
8a2c8fef | 967 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
293f5f65 | 968 | CPU_FMA_FLAGS, 0 }, |
8a2c8fef | 969 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
293f5f65 | 970 | CPU_FMA4_FLAGS, 0 }, |
8a2c8fef | 971 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
293f5f65 | 972 | CPU_XOP_FLAGS, 0 }, |
8a2c8fef | 973 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
293f5f65 | 974 | CPU_LWP_FLAGS, 0 }, |
8a2c8fef | 975 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
293f5f65 | 976 | CPU_MOVBE_FLAGS, 0 }, |
60aa667e | 977 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
293f5f65 | 978 | CPU_CX16_FLAGS, 0 }, |
8a2c8fef | 979 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
293f5f65 | 980 | CPU_EPT_FLAGS, 0 }, |
6c30d220 | 981 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
293f5f65 | 982 | CPU_LZCNT_FLAGS, 0 }, |
42164a71 | 983 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
293f5f65 | 984 | CPU_HLE_FLAGS, 0 }, |
42164a71 | 985 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
293f5f65 | 986 | CPU_RTM_FLAGS, 0 }, |
6c30d220 | 987 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
293f5f65 | 988 | CPU_INVPCID_FLAGS, 0 }, |
8a2c8fef | 989 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
293f5f65 | 990 | CPU_CLFLUSH_FLAGS, 0 }, |
22109423 | 991 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
293f5f65 | 992 | CPU_NOP_FLAGS, 0 }, |
8a2c8fef | 993 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
293f5f65 | 994 | CPU_SYSCALL_FLAGS, 0 }, |
8a2c8fef | 995 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
293f5f65 | 996 | CPU_RDTSCP_FLAGS, 0 }, |
8a2c8fef | 997 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
293f5f65 | 998 | CPU_3DNOW_FLAGS, 0 }, |
8a2c8fef | 999 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
293f5f65 | 1000 | CPU_3DNOWA_FLAGS, 0 }, |
8a2c8fef | 1001 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
293f5f65 | 1002 | CPU_PADLOCK_FLAGS, 0 }, |
8a2c8fef | 1003 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
293f5f65 | 1004 | CPU_SVME_FLAGS, 1 }, |
8a2c8fef | 1005 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
293f5f65 | 1006 | CPU_SVME_FLAGS, 0 }, |
8a2c8fef | 1007 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
293f5f65 | 1008 | CPU_SSE4A_FLAGS, 0 }, |
8a2c8fef | 1009 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1010 | CPU_ABM_FLAGS, 0 }, |
87973e9f | 1011 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1012 | CPU_BMI_FLAGS, 0 }, |
2a2a0f38 | 1013 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1014 | CPU_TBM_FLAGS, 0 }, |
e2e1fcde | 1015 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1016 | CPU_ADX_FLAGS, 0 }, |
e2e1fcde | 1017 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
293f5f65 | 1018 | CPU_RDSEED_FLAGS, 0 }, |
e2e1fcde | 1019 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
293f5f65 | 1020 | CPU_PRFCHW_FLAGS, 0 }, |
5c111e37 | 1021 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
293f5f65 | 1022 | CPU_SMAP_FLAGS, 0 }, |
7e8b059b | 1023 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1024 | CPU_MPX_FLAGS, 0 }, |
a0046408 | 1025 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
293f5f65 | 1026 | CPU_SHA_FLAGS, 0 }, |
963f3586 | 1027 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1028 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
dcf893b5 | 1029 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1030 | CPU_PREFETCHWT1_FLAGS, 0 }, |
2cf200a4 | 1031 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1032 | CPU_SE1_FLAGS, 0 }, |
c5e7287a | 1033 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
293f5f65 | 1034 | CPU_CLWB_FLAGS, 0 }, |
2cc1b5aa | 1035 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
293f5f65 | 1036 | CPU_AVX512IFMA_FLAGS, 0 }, |
14f195c9 | 1037 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1038 | CPU_AVX512VBMI_FLAGS, 0 }, |
920d2ddc IT |
1039 | { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, |
1040 | CPU_AVX512_4FMAPS_FLAGS, 0 }, | |
47acf0bd IT |
1041 | { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, |
1042 | CPU_AVX512_4VNNIW_FLAGS, 0 }, | |
620214f7 IT |
1043 | { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, |
1044 | CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, | |
53467f57 IT |
1045 | { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN, |
1046 | CPU_AVX512_VBMI2_FLAGS, 0 }, | |
8cfcb765 IT |
1047 | { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN, |
1048 | CPU_AVX512_VNNI_FLAGS, 0 }, | |
ee6872be IT |
1049 | { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN, |
1050 | CPU_AVX512_BITALG_FLAGS, 0 }, | |
029f3522 | 1051 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
293f5f65 | 1052 | CPU_CLZERO_FLAGS, 0 }, |
9916071f | 1053 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1054 | CPU_MWAITX_FLAGS, 0 }, |
8eab4136 | 1055 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
293f5f65 | 1056 | CPU_OSPKE_FLAGS, 0 }, |
8bc52696 | 1057 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1058 | CPU_RDPID_FLAGS, 0 }, |
6b40c462 L |
1059 | { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, |
1060 | CPU_PTWRITE_FLAGS, 0 }, | |
d777820b IT |
1061 | { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN, |
1062 | CPU_IBT_FLAGS, 0 }, | |
1063 | { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN, | |
1064 | CPU_SHSTK_FLAGS, 0 }, | |
48521003 IT |
1065 | { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN, |
1066 | CPU_GFNI_FLAGS, 0 }, | |
8dcf1fad IT |
1067 | { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN, |
1068 | CPU_VAES_FLAGS, 0 }, | |
ff1982d5 IT |
1069 | { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN, |
1070 | CPU_VPCLMULQDQ_FLAGS, 0 }, | |
3233d7d0 IT |
1071 | { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN, |
1072 | CPU_WBNOINVD_FLAGS, 0 }, | |
be3a8dca IT |
1073 | { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN, |
1074 | CPU_PCONFIG_FLAGS, 0 }, | |
de89d0a3 IT |
1075 | { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN, |
1076 | CPU_WAITPKG_FLAGS, 0 }, | |
c48935d7 IT |
1077 | { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN, |
1078 | CPU_CLDEMOTE_FLAGS, 0 }, | |
c0a30a9f L |
1079 | { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN, |
1080 | CPU_MOVDIRI_FLAGS, 0 }, | |
1081 | { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN, | |
1082 | CPU_MOVDIR64B_FLAGS, 0 }, | |
d6aab7a1 XG |
1083 | { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN, |
1084 | CPU_AVX512_BF16_FLAGS, 0 }, | |
9186c494 L |
1085 | { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN, |
1086 | CPU_AVX512_VP2INTERSECT_FLAGS, 0 }, | |
dd455cf5 L |
1087 | { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN, |
1088 | CPU_ENQCMD_FLAGS, 0 }, | |
293f5f65 L |
1089 | }; |
1090 | ||
1091 | static const noarch_entry cpu_noarch[] = | |
1092 | { | |
1093 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, | |
1848e567 L |
1094 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
1095 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, | |
1096 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, | |
d871f3f4 L |
1097 | { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS }, |
1098 | { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS }, | |
293f5f65 L |
1099 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
1100 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, | |
1848e567 L |
1101 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
1102 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, | |
1103 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, | |
1104 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, | |
1105 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, | |
1106 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, | |
293f5f65 | 1107 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
1848e567 | 1108 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
144b71e2 L |
1109 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
1110 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, | |
1111 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, | |
1112 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, | |
1113 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, | |
1114 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, | |
1115 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, | |
1116 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, | |
1117 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, | |
920d2ddc | 1118 | { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, |
47acf0bd | 1119 | { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, |
620214f7 | 1120 | { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, |
53467f57 | 1121 | { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS }, |
8cfcb765 | 1122 | { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS }, |
ee6872be | 1123 | { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS }, |
d777820b IT |
1124 | { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS }, |
1125 | { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS }, | |
c0a30a9f L |
1126 | { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS }, |
1127 | { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS }, | |
d6aab7a1 | 1128 | { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS }, |
9186c494 | 1129 | { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS }, |
dd455cf5 | 1130 | { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS }, |
e413e4e9 AM |
1131 | }; |
1132 | ||
704209c0 | 1133 | #ifdef I386COFF |
a6c24e68 NC |
1134 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1135 | is allowed to be optional. */ | |
1136 | ||
1137 | static symbolS * | |
1138 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1139 | { | |
1140 | addressT align = 0; | |
1141 | ||
1142 | SKIP_WHITESPACE (); | |
1143 | ||
7ab9ffdd | 1144 | if (needs_align |
a6c24e68 NC |
1145 | && *input_line_pointer == ',') |
1146 | { | |
1147 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1148 | |
a6c24e68 NC |
1149 | if (align == (addressT) -1) |
1150 | return NULL; | |
1151 | } | |
1152 | else | |
1153 | { | |
1154 | if (size >= 8) | |
1155 | align = 3; | |
1156 | else if (size >= 4) | |
1157 | align = 2; | |
1158 | else if (size >= 2) | |
1159 | align = 1; | |
1160 | else | |
1161 | align = 0; | |
1162 | } | |
1163 | ||
1164 | bss_alloc (symbolP, size, align); | |
1165 | return symbolP; | |
1166 | } | |
1167 | ||
704209c0 | 1168 | static void |
a6c24e68 NC |
1169 | pe_lcomm (int needs_align) |
1170 | { | |
1171 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1172 | } | |
704209c0 | 1173 | #endif |
a6c24e68 | 1174 | |
29b0f896 AM |
1175 | const pseudo_typeS md_pseudo_table[] = |
1176 | { | |
1177 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1178 | {"align", s_align_bytes, 0}, | |
1179 | #else | |
1180 | {"align", s_align_ptwo, 0}, | |
1181 | #endif | |
1182 | {"arch", set_cpu_arch, 0}, | |
1183 | #ifndef I386COFF | |
1184 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1185 | #else |
1186 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1187 | #endif |
1188 | {"ffloat", float_cons, 'f'}, | |
1189 | {"dfloat", float_cons, 'd'}, | |
1190 | {"tfloat", float_cons, 'x'}, | |
1191 | {"value", cons, 2}, | |
d182319b | 1192 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1193 | {"noopt", s_ignore, 0}, |
1194 | {"optim", s_ignore, 0}, | |
1195 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1196 | {"code16", set_code_flag, CODE_16BIT}, | |
1197 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1198 | #ifdef BFD64 |
29b0f896 | 1199 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1200 | #endif |
29b0f896 AM |
1201 | {"intel_syntax", set_intel_syntax, 1}, |
1202 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1203 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1204 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1205 | {"allow_index_reg", set_allow_index_reg, 1}, |
1206 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1207 | {"sse_check", set_check, 0}, |
1208 | {"operand_check", set_check, 1}, | |
3b22753a L |
1209 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1210 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1211 | #else |
68d20676 | 1212 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1213 | {"loc", dwarf2_directive_loc, 0}, |
1214 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1215 | #endif |
6482c264 NC |
1216 | #ifdef TE_PE |
1217 | {"secrel32", pe_directive_secrel, 0}, | |
1218 | #endif | |
29b0f896 AM |
1219 | {0, 0, 0} |
1220 | }; | |
1221 | ||
1222 | /* For interface with expression (). */ | |
1223 | extern char *input_line_pointer; | |
1224 | ||
1225 | /* Hash table for instruction mnemonic lookup. */ | |
1226 | static struct hash_control *op_hash; | |
1227 | ||
1228 | /* Hash table for register lookup. */ | |
1229 | static struct hash_control *reg_hash; | |
1230 | \f | |
ce8a8b2f AM |
1231 | /* Various efficient no-op patterns for aligning code labels. |
1232 | Note: Don't try to assemble the instructions in the comments. | |
1233 | 0L and 0w are not legal. */ | |
62a02d25 L |
1234 | static const unsigned char f32_1[] = |
1235 | {0x90}; /* nop */ | |
1236 | static const unsigned char f32_2[] = | |
1237 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1238 | static const unsigned char f32_3[] = | |
1239 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
1240 | static const unsigned char f32_4[] = | |
1241 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
62a02d25 L |
1242 | static const unsigned char f32_6[] = |
1243 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
1244 | static const unsigned char f32_7[] = | |
1245 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
62a02d25 | 1246 | static const unsigned char f16_3[] = |
3ae729d5 | 1247 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
62a02d25 | 1248 | static const unsigned char f16_4[] = |
3ae729d5 L |
1249 | {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */ |
1250 | static const unsigned char jump_disp8[] = | |
1251 | {0xeb}; /* jmp disp8 */ | |
1252 | static const unsigned char jump32_disp32[] = | |
1253 | {0xe9}; /* jmp disp32 */ | |
1254 | static const unsigned char jump16_disp32[] = | |
1255 | {0x66,0xe9}; /* jmp disp32 */ | |
62a02d25 L |
1256 | /* 32-bit NOPs patterns. */ |
1257 | static const unsigned char *const f32_patt[] = { | |
3ae729d5 | 1258 | f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7 |
62a02d25 L |
1259 | }; |
1260 | /* 16-bit NOPs patterns. */ | |
1261 | static const unsigned char *const f16_patt[] = { | |
3ae729d5 | 1262 | f32_1, f32_2, f16_3, f16_4 |
62a02d25 L |
1263 | }; |
1264 | /* nopl (%[re]ax) */ | |
1265 | static const unsigned char alt_3[] = | |
1266 | {0x0f,0x1f,0x00}; | |
1267 | /* nopl 0(%[re]ax) */ | |
1268 | static const unsigned char alt_4[] = | |
1269 | {0x0f,0x1f,0x40,0x00}; | |
1270 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
1271 | static const unsigned char alt_5[] = | |
1272 | {0x0f,0x1f,0x44,0x00,0x00}; | |
1273 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
1274 | static const unsigned char alt_6[] = | |
1275 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1276 | /* nopl 0L(%[re]ax) */ | |
1277 | static const unsigned char alt_7[] = | |
1278 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1279 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
1280 | static const unsigned char alt_8[] = | |
1281 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1282 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
1283 | static const unsigned char alt_9[] = | |
1284 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1285 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1286 | static const unsigned char alt_10[] = | |
1287 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
3ae729d5 L |
1288 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
1289 | static const unsigned char alt_11[] = | |
1290 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
62a02d25 L |
1291 | /* 32-bit and 64-bit NOPs patterns. */ |
1292 | static const unsigned char *const alt_patt[] = { | |
1293 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
3ae729d5 | 1294 | alt_9, alt_10, alt_11 |
62a02d25 L |
1295 | }; |
1296 | ||
1297 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1298 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1299 | ||
1300 | static void | |
1301 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1302 | int count, int max_single_nop_size) | |
1303 | ||
1304 | { | |
3ae729d5 L |
1305 | /* Place the longer NOP first. */ |
1306 | int last; | |
1307 | int offset; | |
3076e594 NC |
1308 | const unsigned char *nops; |
1309 | ||
1310 | if (max_single_nop_size < 1) | |
1311 | { | |
1312 | as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"), | |
1313 | max_single_nop_size); | |
1314 | return; | |
1315 | } | |
1316 | ||
1317 | nops = patt[max_single_nop_size - 1]; | |
3ae729d5 L |
1318 | |
1319 | /* Use the smaller one if the requsted one isn't available. */ | |
1320 | if (nops == NULL) | |
62a02d25 | 1321 | { |
3ae729d5 L |
1322 | max_single_nop_size--; |
1323 | nops = patt[max_single_nop_size - 1]; | |
62a02d25 L |
1324 | } |
1325 | ||
3ae729d5 L |
1326 | last = count % max_single_nop_size; |
1327 | ||
1328 | count -= last; | |
1329 | for (offset = 0; offset < count; offset += max_single_nop_size) | |
1330 | memcpy (where + offset, nops, max_single_nop_size); | |
1331 | ||
1332 | if (last) | |
1333 | { | |
1334 | nops = patt[last - 1]; | |
1335 | if (nops == NULL) | |
1336 | { | |
1337 | /* Use the smaller one plus one-byte NOP if the needed one | |
1338 | isn't available. */ | |
1339 | last--; | |
1340 | nops = patt[last - 1]; | |
1341 | memcpy (where + offset, nops, last); | |
1342 | where[offset + last] = *patt[0]; | |
1343 | } | |
1344 | else | |
1345 | memcpy (where + offset, nops, last); | |
1346 | } | |
62a02d25 L |
1347 | } |
1348 | ||
3ae729d5 L |
1349 | static INLINE int |
1350 | fits_in_imm7 (offsetT num) | |
1351 | { | |
1352 | return (num & 0x7f) == num; | |
1353 | } | |
1354 | ||
1355 | static INLINE int | |
1356 | fits_in_imm31 (offsetT num) | |
1357 | { | |
1358 | return (num & 0x7fffffff) == num; | |
1359 | } | |
62a02d25 L |
1360 | |
1361 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1362 | single NOP instruction LIMIT. */ | |
1363 | ||
1364 | void | |
3ae729d5 | 1365 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
62a02d25 | 1366 | { |
3ae729d5 | 1367 | const unsigned char *const *patt = NULL; |
62a02d25 | 1368 | int max_single_nop_size; |
3ae729d5 L |
1369 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
1370 | int max_number_of_nops; | |
62a02d25 | 1371 | |
3ae729d5 | 1372 | switch (fragP->fr_type) |
62a02d25 | 1373 | { |
3ae729d5 L |
1374 | case rs_fill_nop: |
1375 | case rs_align_code: | |
1376 | break; | |
1377 | default: | |
62a02d25 L |
1378 | return; |
1379 | } | |
1380 | ||
ccc9c027 L |
1381 | /* We need to decide which NOP sequence to use for 32bit and |
1382 | 64bit. When -mtune= is used: | |
4eed87de | 1383 | |
76bc74dc L |
1384 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1385 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1386 | 2. For the rest, alt_patt will be used. |
1387 | ||
1388 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1389 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1390 | be used. |
ccc9c027 L |
1391 | |
1392 | When -march= or .arch is used, we can't use anything beyond | |
1393 | cpu_arch_isa_flags. */ | |
1394 | ||
1395 | if (flag_code == CODE_16BIT) | |
1396 | { | |
3ae729d5 L |
1397 | patt = f16_patt; |
1398 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1399 | /* Limit number of NOPs to 2 in 16-bit mode. */ | |
1400 | max_number_of_nops = 2; | |
252b5132 | 1401 | } |
33fef721 | 1402 | else |
ccc9c027 | 1403 | { |
fbf3f584 | 1404 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1405 | { |
1406 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1407 | switch (cpu_arch_tune) | |
1408 | { | |
1409 | case PROCESSOR_UNKNOWN: | |
1410 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1411 | optimize with nops. */ |
1412 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1413 | patt = alt_patt; |
ccc9c027 L |
1414 | else |
1415 | patt = f32_patt; | |
1416 | break; | |
ccc9c027 L |
1417 | case PROCESSOR_PENTIUM4: |
1418 | case PROCESSOR_NOCONA: | |
ef05d495 | 1419 | case PROCESSOR_CORE: |
76bc74dc | 1420 | case PROCESSOR_CORE2: |
bd5295b2 | 1421 | case PROCESSOR_COREI7: |
3632d14b | 1422 | case PROCESSOR_L1OM: |
7a9068fe | 1423 | case PROCESSOR_K1OM: |
76bc74dc | 1424 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1425 | case PROCESSOR_K6: |
1426 | case PROCESSOR_ATHLON: | |
1427 | case PROCESSOR_K8: | |
4eed87de | 1428 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1429 | case PROCESSOR_BD: |
029f3522 | 1430 | case PROCESSOR_ZNVER: |
7b458c12 | 1431 | case PROCESSOR_BT: |
80b8656c | 1432 | patt = alt_patt; |
ccc9c027 | 1433 | break; |
76bc74dc | 1434 | case PROCESSOR_I386: |
ccc9c027 L |
1435 | case PROCESSOR_I486: |
1436 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1437 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1438 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1439 | case PROCESSOR_GENERIC32: |
1440 | patt = f32_patt; | |
1441 | break; | |
4eed87de | 1442 | } |
ccc9c027 L |
1443 | } |
1444 | else | |
1445 | { | |
fbf3f584 | 1446 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1447 | { |
1448 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1449 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1450 | PROCESSOR_UNKNOWN. */ |
1451 | abort (); | |
1452 | break; | |
1453 | ||
76bc74dc | 1454 | case PROCESSOR_I386: |
ccc9c027 L |
1455 | case PROCESSOR_I486: |
1456 | case PROCESSOR_PENTIUM: | |
81486035 | 1457 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1458 | case PROCESSOR_K6: |
1459 | case PROCESSOR_ATHLON: | |
1460 | case PROCESSOR_K8: | |
4eed87de | 1461 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1462 | case PROCESSOR_BD: |
029f3522 | 1463 | case PROCESSOR_ZNVER: |
7b458c12 | 1464 | case PROCESSOR_BT: |
ccc9c027 L |
1465 | case PROCESSOR_GENERIC32: |
1466 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1467 | with nops. */ |
1468 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1469 | patt = alt_patt; |
ccc9c027 L |
1470 | else |
1471 | patt = f32_patt; | |
1472 | break; | |
76bc74dc L |
1473 | case PROCESSOR_PENTIUMPRO: |
1474 | case PROCESSOR_PENTIUM4: | |
1475 | case PROCESSOR_NOCONA: | |
1476 | case PROCESSOR_CORE: | |
ef05d495 | 1477 | case PROCESSOR_CORE2: |
bd5295b2 | 1478 | case PROCESSOR_COREI7: |
3632d14b | 1479 | case PROCESSOR_L1OM: |
7a9068fe | 1480 | case PROCESSOR_K1OM: |
22109423 | 1481 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1482 | patt = alt_patt; |
ccc9c027 L |
1483 | else |
1484 | patt = f32_patt; | |
1485 | break; | |
1486 | case PROCESSOR_GENERIC64: | |
80b8656c | 1487 | patt = alt_patt; |
ccc9c027 | 1488 | break; |
4eed87de | 1489 | } |
ccc9c027 L |
1490 | } |
1491 | ||
76bc74dc L |
1492 | if (patt == f32_patt) |
1493 | { | |
3ae729d5 L |
1494 | max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]); |
1495 | /* Limit number of NOPs to 2 for older processors. */ | |
1496 | max_number_of_nops = 2; | |
76bc74dc L |
1497 | } |
1498 | else | |
1499 | { | |
3ae729d5 L |
1500 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
1501 | /* Limit number of NOPs to 7 for newer processors. */ | |
1502 | max_number_of_nops = 7; | |
1503 | } | |
1504 | } | |
1505 | ||
1506 | if (limit == 0) | |
1507 | limit = max_single_nop_size; | |
1508 | ||
1509 | if (fragP->fr_type == rs_fill_nop) | |
1510 | { | |
1511 | /* Output NOPs for .nop directive. */ | |
1512 | if (limit > max_single_nop_size) | |
1513 | { | |
1514 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1515 | _("invalid single nop size: %d " | |
1516 | "(expect within [0, %d])"), | |
1517 | limit, max_single_nop_size); | |
1518 | return; | |
1519 | } | |
1520 | } | |
1521 | else | |
1522 | fragP->fr_var = count; | |
1523 | ||
1524 | if ((count / max_single_nop_size) > max_number_of_nops) | |
1525 | { | |
1526 | /* Generate jump over NOPs. */ | |
1527 | offsetT disp = count - 2; | |
1528 | if (fits_in_imm7 (disp)) | |
1529 | { | |
1530 | /* Use "jmp disp8" if possible. */ | |
1531 | count = disp; | |
1532 | where[0] = jump_disp8[0]; | |
1533 | where[1] = count; | |
1534 | where += 2; | |
1535 | } | |
1536 | else | |
1537 | { | |
1538 | unsigned int size_of_jump; | |
1539 | ||
1540 | if (flag_code == CODE_16BIT) | |
1541 | { | |
1542 | where[0] = jump16_disp32[0]; | |
1543 | where[1] = jump16_disp32[1]; | |
1544 | size_of_jump = 2; | |
1545 | } | |
1546 | else | |
1547 | { | |
1548 | where[0] = jump32_disp32[0]; | |
1549 | size_of_jump = 1; | |
1550 | } | |
1551 | ||
1552 | count -= size_of_jump + 4; | |
1553 | if (!fits_in_imm31 (count)) | |
1554 | { | |
1555 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1556 | _("jump over nop padding out of range")); | |
1557 | return; | |
1558 | } | |
1559 | ||
1560 | md_number_to_chars (where + size_of_jump, count, 4); | |
1561 | where += size_of_jump + 4; | |
76bc74dc | 1562 | } |
ccc9c027 | 1563 | } |
3ae729d5 L |
1564 | |
1565 | /* Generate multiple NOPs. */ | |
1566 | i386_output_nops (where, patt, count, limit); | |
252b5132 RH |
1567 | } |
1568 | ||
c6fb90c8 | 1569 | static INLINE int |
0dfbf9d7 | 1570 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1571 | { |
0dfbf9d7 | 1572 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1573 | { |
1574 | case 3: | |
0dfbf9d7 | 1575 | if (x->array[2]) |
c6fb90c8 | 1576 | return 0; |
1a0670f3 | 1577 | /* Fall through. */ |
c6fb90c8 | 1578 | case 2: |
0dfbf9d7 | 1579 | if (x->array[1]) |
c6fb90c8 | 1580 | return 0; |
1a0670f3 | 1581 | /* Fall through. */ |
c6fb90c8 | 1582 | case 1: |
0dfbf9d7 | 1583 | return !x->array[0]; |
c6fb90c8 L |
1584 | default: |
1585 | abort (); | |
1586 | } | |
40fb9820 L |
1587 | } |
1588 | ||
c6fb90c8 | 1589 | static INLINE void |
0dfbf9d7 | 1590 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1591 | { |
0dfbf9d7 | 1592 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1593 | { |
1594 | case 3: | |
0dfbf9d7 | 1595 | x->array[2] = v; |
1a0670f3 | 1596 | /* Fall through. */ |
c6fb90c8 | 1597 | case 2: |
0dfbf9d7 | 1598 | x->array[1] = v; |
1a0670f3 | 1599 | /* Fall through. */ |
c6fb90c8 | 1600 | case 1: |
0dfbf9d7 | 1601 | x->array[0] = v; |
1a0670f3 | 1602 | /* Fall through. */ |
c6fb90c8 L |
1603 | break; |
1604 | default: | |
1605 | abort (); | |
1606 | } | |
1607 | } | |
40fb9820 | 1608 | |
c6fb90c8 | 1609 | static INLINE int |
0dfbf9d7 L |
1610 | operand_type_equal (const union i386_operand_type *x, |
1611 | const union i386_operand_type *y) | |
c6fb90c8 | 1612 | { |
0dfbf9d7 | 1613 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1614 | { |
1615 | case 3: | |
0dfbf9d7 | 1616 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1617 | return 0; |
1a0670f3 | 1618 | /* Fall through. */ |
c6fb90c8 | 1619 | case 2: |
0dfbf9d7 | 1620 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1621 | return 0; |
1a0670f3 | 1622 | /* Fall through. */ |
c6fb90c8 | 1623 | case 1: |
0dfbf9d7 | 1624 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1625 | break; |
1626 | default: | |
1627 | abort (); | |
1628 | } | |
1629 | } | |
40fb9820 | 1630 | |
0dfbf9d7 L |
1631 | static INLINE int |
1632 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1633 | { | |
1634 | switch (ARRAY_SIZE(x->array)) | |
1635 | { | |
53467f57 IT |
1636 | case 4: |
1637 | if (x->array[3]) | |
1638 | return 0; | |
1639 | /* Fall through. */ | |
0dfbf9d7 L |
1640 | case 3: |
1641 | if (x->array[2]) | |
1642 | return 0; | |
1a0670f3 | 1643 | /* Fall through. */ |
0dfbf9d7 L |
1644 | case 2: |
1645 | if (x->array[1]) | |
1646 | return 0; | |
1a0670f3 | 1647 | /* Fall through. */ |
0dfbf9d7 L |
1648 | case 1: |
1649 | return !x->array[0]; | |
1650 | default: | |
1651 | abort (); | |
1652 | } | |
1653 | } | |
1654 | ||
0dfbf9d7 L |
1655 | static INLINE int |
1656 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1657 | const union i386_cpu_flags *y) | |
1658 | { | |
1659 | switch (ARRAY_SIZE(x->array)) | |
1660 | { | |
53467f57 IT |
1661 | case 4: |
1662 | if (x->array[3] != y->array[3]) | |
1663 | return 0; | |
1664 | /* Fall through. */ | |
0dfbf9d7 L |
1665 | case 3: |
1666 | if (x->array[2] != y->array[2]) | |
1667 | return 0; | |
1a0670f3 | 1668 | /* Fall through. */ |
0dfbf9d7 L |
1669 | case 2: |
1670 | if (x->array[1] != y->array[1]) | |
1671 | return 0; | |
1a0670f3 | 1672 | /* Fall through. */ |
0dfbf9d7 L |
1673 | case 1: |
1674 | return x->array[0] == y->array[0]; | |
1675 | break; | |
1676 | default: | |
1677 | abort (); | |
1678 | } | |
1679 | } | |
c6fb90c8 L |
1680 | |
1681 | static INLINE int | |
1682 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1683 | { | |
1684 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1685 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1686 | } |
1687 | ||
c6fb90c8 L |
1688 | static INLINE i386_cpu_flags |
1689 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1690 | { |
c6fb90c8 L |
1691 | switch (ARRAY_SIZE (x.array)) |
1692 | { | |
53467f57 IT |
1693 | case 4: |
1694 | x.array [3] &= y.array [3]; | |
1695 | /* Fall through. */ | |
c6fb90c8 L |
1696 | case 3: |
1697 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1698 | /* Fall through. */ |
c6fb90c8 L |
1699 | case 2: |
1700 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1701 | /* Fall through. */ |
c6fb90c8 L |
1702 | case 1: |
1703 | x.array [0] &= y.array [0]; | |
1704 | break; | |
1705 | default: | |
1706 | abort (); | |
1707 | } | |
1708 | return x; | |
1709 | } | |
40fb9820 | 1710 | |
c6fb90c8 L |
1711 | static INLINE i386_cpu_flags |
1712 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1713 | { |
c6fb90c8 | 1714 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1715 | { |
53467f57 IT |
1716 | case 4: |
1717 | x.array [3] |= y.array [3]; | |
1718 | /* Fall through. */ | |
c6fb90c8 L |
1719 | case 3: |
1720 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1721 | /* Fall through. */ |
c6fb90c8 L |
1722 | case 2: |
1723 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1724 | /* Fall through. */ |
c6fb90c8 L |
1725 | case 1: |
1726 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1727 | break; |
1728 | default: | |
1729 | abort (); | |
1730 | } | |
40fb9820 L |
1731 | return x; |
1732 | } | |
1733 | ||
309d3373 JB |
1734 | static INLINE i386_cpu_flags |
1735 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1736 | { | |
1737 | switch (ARRAY_SIZE (x.array)) | |
1738 | { | |
53467f57 IT |
1739 | case 4: |
1740 | x.array [3] &= ~y.array [3]; | |
1741 | /* Fall through. */ | |
309d3373 JB |
1742 | case 3: |
1743 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1744 | /* Fall through. */ |
309d3373 JB |
1745 | case 2: |
1746 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1747 | /* Fall through. */ |
309d3373 JB |
1748 | case 1: |
1749 | x.array [0] &= ~y.array [0]; | |
1750 | break; | |
1751 | default: | |
1752 | abort (); | |
1753 | } | |
1754 | return x; | |
1755 | } | |
1756 | ||
c0f3af97 L |
1757 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1758 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
1759 | ||
c0f3af97 | 1760 | #define CPU_FLAGS_PERFECT_MATCH \ |
db12e14e | 1761 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
c0f3af97 L |
1762 | |
1763 | /* Return CPU flags match bits. */ | |
3629bb00 | 1764 | |
40fb9820 | 1765 | static int |
d3ce72d0 | 1766 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1767 | { |
c0f3af97 L |
1768 | i386_cpu_flags x = t->cpu_flags; |
1769 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1770 | |
1771 | x.bitfield.cpu64 = 0; | |
1772 | x.bitfield.cpuno64 = 0; | |
1773 | ||
0dfbf9d7 | 1774 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1775 | { |
1776 | /* This instruction is available on all archs. */ | |
db12e14e | 1777 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1778 | } |
3629bb00 L |
1779 | else |
1780 | { | |
c0f3af97 | 1781 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1782 | i386_cpu_flags cpu = cpu_arch_flags; |
1783 | ||
ab592e75 JB |
1784 | /* AVX512VL is no standalone feature - match it and then strip it. */ |
1785 | if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl) | |
1786 | return match; | |
1787 | x.bitfield.cpuavx512vl = 0; | |
1788 | ||
3629bb00 | 1789 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1790 | if (!cpu_flags_all_zero (&cpu)) |
1791 | { | |
a5ff0eb2 L |
1792 | if (x.bitfield.cpuavx) |
1793 | { | |
929f69fa | 1794 | /* We need to check a few extra flags with AVX. */ |
b9d49817 JB |
1795 | if (cpu.bitfield.cpuavx |
1796 | && (!t->opcode_modifier.sse2avx || sse2avx) | |
1797 | && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
929f69fa | 1798 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) |
b9d49817 JB |
1799 | && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul)) |
1800 | match |= CPU_FLAGS_ARCH_MATCH; | |
a5ff0eb2 | 1801 | } |
929f69fa JB |
1802 | else if (x.bitfield.cpuavx512f) |
1803 | { | |
1804 | /* We need to check a few extra flags with AVX512F. */ | |
1805 | if (cpu.bitfield.cpuavx512f | |
1806 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) | |
1807 | && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes) | |
1808 | && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq)) | |
1809 | match |= CPU_FLAGS_ARCH_MATCH; | |
1810 | } | |
a5ff0eb2 | 1811 | else |
db12e14e | 1812 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1813 | } |
3629bb00 | 1814 | } |
c0f3af97 | 1815 | return match; |
40fb9820 L |
1816 | } |
1817 | ||
c6fb90c8 L |
1818 | static INLINE i386_operand_type |
1819 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1820 | { |
c6fb90c8 L |
1821 | switch (ARRAY_SIZE (x.array)) |
1822 | { | |
1823 | case 3: | |
1824 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1825 | /* Fall through. */ |
c6fb90c8 L |
1826 | case 2: |
1827 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1828 | /* Fall through. */ |
c6fb90c8 L |
1829 | case 1: |
1830 | x.array [0] &= y.array [0]; | |
1831 | break; | |
1832 | default: | |
1833 | abort (); | |
1834 | } | |
1835 | return x; | |
40fb9820 L |
1836 | } |
1837 | ||
73053c1f JB |
1838 | static INLINE i386_operand_type |
1839 | operand_type_and_not (i386_operand_type x, i386_operand_type y) | |
1840 | { | |
1841 | switch (ARRAY_SIZE (x.array)) | |
1842 | { | |
1843 | case 3: | |
1844 | x.array [2] &= ~y.array [2]; | |
1845 | /* Fall through. */ | |
1846 | case 2: | |
1847 | x.array [1] &= ~y.array [1]; | |
1848 | /* Fall through. */ | |
1849 | case 1: | |
1850 | x.array [0] &= ~y.array [0]; | |
1851 | break; | |
1852 | default: | |
1853 | abort (); | |
1854 | } | |
1855 | return x; | |
1856 | } | |
1857 | ||
c6fb90c8 L |
1858 | static INLINE i386_operand_type |
1859 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1860 | { |
c6fb90c8 | 1861 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1862 | { |
c6fb90c8 L |
1863 | case 3: |
1864 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1865 | /* Fall through. */ |
c6fb90c8 L |
1866 | case 2: |
1867 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1868 | /* Fall through. */ |
c6fb90c8 L |
1869 | case 1: |
1870 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1871 | break; |
1872 | default: | |
1873 | abort (); | |
1874 | } | |
c6fb90c8 L |
1875 | return x; |
1876 | } | |
40fb9820 | 1877 | |
c6fb90c8 L |
1878 | static INLINE i386_operand_type |
1879 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1880 | { | |
1881 | switch (ARRAY_SIZE (x.array)) | |
1882 | { | |
1883 | case 3: | |
1884 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 1885 | /* Fall through. */ |
c6fb90c8 L |
1886 | case 2: |
1887 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 1888 | /* Fall through. */ |
c6fb90c8 L |
1889 | case 1: |
1890 | x.array [0] ^= y.array [0]; | |
1891 | break; | |
1892 | default: | |
1893 | abort (); | |
1894 | } | |
40fb9820 L |
1895 | return x; |
1896 | } | |
1897 | ||
40fb9820 L |
1898 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; |
1899 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
1900 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
1901 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
1902 | static const i386_operand_type anydisp | |
1903 | = OPERAND_TYPE_ANYDISP; | |
40fb9820 | 1904 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
43234a1e | 1905 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; |
40fb9820 L |
1906 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
1907 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
1908 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
1909 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
1910 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
1911 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
1912 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
1913 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
1914 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
a683cc34 | 1915 | static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4; |
40fb9820 L |
1916 | |
1917 | enum operand_type | |
1918 | { | |
1919 | reg, | |
40fb9820 L |
1920 | imm, |
1921 | disp, | |
1922 | anymem | |
1923 | }; | |
1924 | ||
c6fb90c8 | 1925 | static INLINE int |
40fb9820 L |
1926 | operand_type_check (i386_operand_type t, enum operand_type c) |
1927 | { | |
1928 | switch (c) | |
1929 | { | |
1930 | case reg: | |
dc821c5f | 1931 | return t.bitfield.reg; |
40fb9820 | 1932 | |
40fb9820 L |
1933 | case imm: |
1934 | return (t.bitfield.imm8 | |
1935 | || t.bitfield.imm8s | |
1936 | || t.bitfield.imm16 | |
1937 | || t.bitfield.imm32 | |
1938 | || t.bitfield.imm32s | |
1939 | || t.bitfield.imm64); | |
1940 | ||
1941 | case disp: | |
1942 | return (t.bitfield.disp8 | |
1943 | || t.bitfield.disp16 | |
1944 | || t.bitfield.disp32 | |
1945 | || t.bitfield.disp32s | |
1946 | || t.bitfield.disp64); | |
1947 | ||
1948 | case anymem: | |
1949 | return (t.bitfield.disp8 | |
1950 | || t.bitfield.disp16 | |
1951 | || t.bitfield.disp32 | |
1952 | || t.bitfield.disp32s | |
1953 | || t.bitfield.disp64 | |
1954 | || t.bitfield.baseindex); | |
1955 | ||
1956 | default: | |
1957 | abort (); | |
1958 | } | |
2cfe26b6 AM |
1959 | |
1960 | return 0; | |
40fb9820 L |
1961 | } |
1962 | ||
7a54636a L |
1963 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size |
1964 | between operand GIVEN and opeand WANTED for instruction template T. */ | |
5c07affc L |
1965 | |
1966 | static INLINE int | |
7a54636a L |
1967 | match_operand_size (const insn_template *t, unsigned int wanted, |
1968 | unsigned int given) | |
5c07affc | 1969 | { |
3ac21baa JB |
1970 | return !((i.types[given].bitfield.byte |
1971 | && !t->operand_types[wanted].bitfield.byte) | |
1972 | || (i.types[given].bitfield.word | |
1973 | && !t->operand_types[wanted].bitfield.word) | |
1974 | || (i.types[given].bitfield.dword | |
1975 | && !t->operand_types[wanted].bitfield.dword) | |
1976 | || (i.types[given].bitfield.qword | |
1977 | && !t->operand_types[wanted].bitfield.qword) | |
1978 | || (i.types[given].bitfield.tbyte | |
1979 | && !t->operand_types[wanted].bitfield.tbyte)); | |
5c07affc L |
1980 | } |
1981 | ||
dd40ce22 L |
1982 | /* Return 1 if there is no conflict in SIMD register between operand |
1983 | GIVEN and opeand WANTED for instruction template T. */ | |
1b54b8d7 JB |
1984 | |
1985 | static INLINE int | |
dd40ce22 L |
1986 | match_simd_size (const insn_template *t, unsigned int wanted, |
1987 | unsigned int given) | |
1b54b8d7 | 1988 | { |
3ac21baa JB |
1989 | return !((i.types[given].bitfield.xmmword |
1990 | && !t->operand_types[wanted].bitfield.xmmword) | |
1991 | || (i.types[given].bitfield.ymmword | |
1992 | && !t->operand_types[wanted].bitfield.ymmword) | |
1993 | || (i.types[given].bitfield.zmmword | |
1994 | && !t->operand_types[wanted].bitfield.zmmword)); | |
1b54b8d7 JB |
1995 | } |
1996 | ||
7a54636a L |
1997 | /* Return 1 if there is no conflict in any size between operand GIVEN |
1998 | and opeand WANTED for instruction template T. */ | |
5c07affc L |
1999 | |
2000 | static INLINE int | |
dd40ce22 L |
2001 | match_mem_size (const insn_template *t, unsigned int wanted, |
2002 | unsigned int given) | |
5c07affc | 2003 | { |
7a54636a | 2004 | return (match_operand_size (t, wanted, given) |
3ac21baa | 2005 | && !((i.types[given].bitfield.unspecified |
af508cb9 | 2006 | && !i.broadcast |
3ac21baa JB |
2007 | && !t->operand_types[wanted].bitfield.unspecified) |
2008 | || (i.types[given].bitfield.fword | |
2009 | && !t->operand_types[wanted].bitfield.fword) | |
1b54b8d7 JB |
2010 | /* For scalar opcode templates to allow register and memory |
2011 | operands at the same time, some special casing is needed | |
d6793fa1 JB |
2012 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
2013 | down-conversion vpmov*. */ | |
3ac21baa | 2014 | || ((t->operand_types[wanted].bitfield.regsimd |
1b54b8d7 | 2015 | && !t->opcode_modifier.broadcast |
3ac21baa JB |
2016 | && (t->operand_types[wanted].bitfield.byte |
2017 | || t->operand_types[wanted].bitfield.word | |
2018 | || t->operand_types[wanted].bitfield.dword | |
2019 | || t->operand_types[wanted].bitfield.qword)) | |
2020 | ? (i.types[given].bitfield.xmmword | |
2021 | || i.types[given].bitfield.ymmword | |
2022 | || i.types[given].bitfield.zmmword) | |
2023 | : !match_simd_size(t, wanted, given)))); | |
5c07affc L |
2024 | } |
2025 | ||
3ac21baa JB |
2026 | /* Return value has MATCH_STRAIGHT set if there is no size conflict on any |
2027 | operands for instruction template T, and it has MATCH_REVERSE set if there | |
2028 | is no size conflict on any operands for the template with operands reversed | |
2029 | (and the template allows for reversing in the first place). */ | |
5c07affc | 2030 | |
3ac21baa JB |
2031 | #define MATCH_STRAIGHT 1 |
2032 | #define MATCH_REVERSE 2 | |
2033 | ||
2034 | static INLINE unsigned int | |
d3ce72d0 | 2035 | operand_size_match (const insn_template *t) |
5c07affc | 2036 | { |
3ac21baa | 2037 | unsigned int j, match = MATCH_STRAIGHT; |
5c07affc L |
2038 | |
2039 | /* Don't check jump instructions. */ | |
2040 | if (t->opcode_modifier.jump | |
2041 | || t->opcode_modifier.jumpbyte | |
2042 | || t->opcode_modifier.jumpdword | |
2043 | || t->opcode_modifier.jumpintersegment) | |
2044 | return match; | |
2045 | ||
2046 | /* Check memory and accumulator operand size. */ | |
2047 | for (j = 0; j < i.operands; j++) | |
2048 | { | |
1b54b8d7 JB |
2049 | if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd |
2050 | && t->operand_types[j].bitfield.anysize) | |
5c07affc L |
2051 | continue; |
2052 | ||
1b54b8d7 | 2053 | if (t->operand_types[j].bitfield.reg |
7a54636a | 2054 | && !match_operand_size (t, j, j)) |
5c07affc L |
2055 | { |
2056 | match = 0; | |
2057 | break; | |
2058 | } | |
2059 | ||
1b54b8d7 | 2060 | if (t->operand_types[j].bitfield.regsimd |
3ac21baa | 2061 | && !match_simd_size (t, j, j)) |
1b54b8d7 JB |
2062 | { |
2063 | match = 0; | |
2064 | break; | |
2065 | } | |
2066 | ||
2067 | if (t->operand_types[j].bitfield.acc | |
7a54636a | 2068 | && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j))) |
1b54b8d7 JB |
2069 | { |
2070 | match = 0; | |
2071 | break; | |
2072 | } | |
2073 | ||
c48dadc9 | 2074 | if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j)) |
5c07affc L |
2075 | { |
2076 | match = 0; | |
2077 | break; | |
2078 | } | |
2079 | } | |
2080 | ||
3ac21baa | 2081 | if (!t->opcode_modifier.d) |
891edac4 L |
2082 | { |
2083 | mismatch: | |
3ac21baa JB |
2084 | if (!match) |
2085 | i.error = operand_size_mismatch; | |
2086 | return match; | |
891edac4 | 2087 | } |
5c07affc L |
2088 | |
2089 | /* Check reverse. */ | |
f5eb1d70 | 2090 | gas_assert (i.operands >= 2 && i.operands <= 3); |
5c07affc | 2091 | |
f5eb1d70 | 2092 | for (j = 0; j < i.operands; j++) |
5c07affc | 2093 | { |
f5eb1d70 JB |
2094 | unsigned int given = i.operands - j - 1; |
2095 | ||
dbbc8b7e | 2096 | if (t->operand_types[j].bitfield.reg |
f5eb1d70 | 2097 | && !match_operand_size (t, j, given)) |
891edac4 | 2098 | goto mismatch; |
5c07affc | 2099 | |
dbbc8b7e | 2100 | if (t->operand_types[j].bitfield.regsimd |
f5eb1d70 | 2101 | && !match_simd_size (t, j, given)) |
dbbc8b7e JB |
2102 | goto mismatch; |
2103 | ||
2104 | if (t->operand_types[j].bitfield.acc | |
f5eb1d70 JB |
2105 | && (!match_operand_size (t, j, given) |
2106 | || !match_simd_size (t, j, given))) | |
dbbc8b7e JB |
2107 | goto mismatch; |
2108 | ||
f5eb1d70 | 2109 | if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given)) |
891edac4 | 2110 | goto mismatch; |
5c07affc L |
2111 | } |
2112 | ||
3ac21baa | 2113 | return match | MATCH_REVERSE; |
5c07affc L |
2114 | } |
2115 | ||
c6fb90c8 | 2116 | static INLINE int |
40fb9820 L |
2117 | operand_type_match (i386_operand_type overlap, |
2118 | i386_operand_type given) | |
2119 | { | |
2120 | i386_operand_type temp = overlap; | |
2121 | ||
2122 | temp.bitfield.jumpabsolute = 0; | |
7d5e4556 | 2123 | temp.bitfield.unspecified = 0; |
5c07affc L |
2124 | temp.bitfield.byte = 0; |
2125 | temp.bitfield.word = 0; | |
2126 | temp.bitfield.dword = 0; | |
2127 | temp.bitfield.fword = 0; | |
2128 | temp.bitfield.qword = 0; | |
2129 | temp.bitfield.tbyte = 0; | |
2130 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2131 | temp.bitfield.ymmword = 0; |
43234a1e | 2132 | temp.bitfield.zmmword = 0; |
0dfbf9d7 | 2133 | if (operand_type_all_zero (&temp)) |
891edac4 | 2134 | goto mismatch; |
40fb9820 | 2135 | |
891edac4 L |
2136 | if (given.bitfield.baseindex == overlap.bitfield.baseindex |
2137 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute) | |
2138 | return 1; | |
2139 | ||
2140 | mismatch: | |
a65babc9 | 2141 | i.error = operand_type_mismatch; |
891edac4 | 2142 | return 0; |
40fb9820 L |
2143 | } |
2144 | ||
7d5e4556 | 2145 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd JB |
2146 | unless the expected operand type register overlap is null. |
2147 | Memory operand size of certain SIMD instructions is also being checked | |
2148 | here. */ | |
40fb9820 | 2149 | |
c6fb90c8 | 2150 | static INLINE int |
dc821c5f | 2151 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2152 | i386_operand_type t0, |
40fb9820 L |
2153 | i386_operand_type g1, |
2154 | i386_operand_type t1) | |
2155 | { | |
10c17abd JB |
2156 | if (!g0.bitfield.reg |
2157 | && !g0.bitfield.regsimd | |
2158 | && (!operand_type_check (g0, anymem) | |
2159 | || g0.bitfield.unspecified | |
2160 | || !t0.bitfield.regsimd)) | |
40fb9820 L |
2161 | return 1; |
2162 | ||
10c17abd JB |
2163 | if (!g1.bitfield.reg |
2164 | && !g1.bitfield.regsimd | |
2165 | && (!operand_type_check (g1, anymem) | |
2166 | || g1.bitfield.unspecified | |
2167 | || !t1.bitfield.regsimd)) | |
40fb9820 L |
2168 | return 1; |
2169 | ||
dc821c5f JB |
2170 | if (g0.bitfield.byte == g1.bitfield.byte |
2171 | && g0.bitfield.word == g1.bitfield.word | |
2172 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2173 | && g0.bitfield.qword == g1.bitfield.qword |
2174 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2175 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2176 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2177 | return 1; |
2178 | ||
dc821c5f JB |
2179 | if (!(t0.bitfield.byte & t1.bitfield.byte) |
2180 | && !(t0.bitfield.word & t1.bitfield.word) | |
2181 | && !(t0.bitfield.dword & t1.bitfield.dword) | |
10c17abd JB |
2182 | && !(t0.bitfield.qword & t1.bitfield.qword) |
2183 | && !(t0.bitfield.xmmword & t1.bitfield.xmmword) | |
2184 | && !(t0.bitfield.ymmword & t1.bitfield.ymmword) | |
2185 | && !(t0.bitfield.zmmword & t1.bitfield.zmmword)) | |
891edac4 L |
2186 | return 1; |
2187 | ||
a65babc9 | 2188 | i.error = register_type_mismatch; |
891edac4 L |
2189 | |
2190 | return 0; | |
40fb9820 L |
2191 | } |
2192 | ||
4c692bc7 JB |
2193 | static INLINE unsigned int |
2194 | register_number (const reg_entry *r) | |
2195 | { | |
2196 | unsigned int nr = r->reg_num; | |
2197 | ||
2198 | if (r->reg_flags & RegRex) | |
2199 | nr += 8; | |
2200 | ||
200cbe0f L |
2201 | if (r->reg_flags & RegVRex) |
2202 | nr += 16; | |
2203 | ||
4c692bc7 JB |
2204 | return nr; |
2205 | } | |
2206 | ||
252b5132 | 2207 | static INLINE unsigned int |
40fb9820 | 2208 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2209 | { |
b5014f7a | 2210 | if (t.bitfield.disp8) |
40fb9820 L |
2211 | return 1; |
2212 | else if (t.bitfield.disp16 | |
2213 | || t.bitfield.disp32 | |
2214 | || t.bitfield.disp32s) | |
2215 | return 2; | |
2216 | else | |
2217 | return 0; | |
252b5132 RH |
2218 | } |
2219 | ||
2220 | static INLINE int | |
65879393 | 2221 | fits_in_signed_byte (addressT num) |
252b5132 | 2222 | { |
65879393 | 2223 | return num + 0x80 <= 0xff; |
47926f60 | 2224 | } |
252b5132 RH |
2225 | |
2226 | static INLINE int | |
65879393 | 2227 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2228 | { |
65879393 | 2229 | return num <= 0xff; |
47926f60 | 2230 | } |
252b5132 RH |
2231 | |
2232 | static INLINE int | |
65879393 | 2233 | fits_in_unsigned_word (addressT num) |
252b5132 | 2234 | { |
65879393 | 2235 | return num <= 0xffff; |
47926f60 | 2236 | } |
252b5132 RH |
2237 | |
2238 | static INLINE int | |
65879393 | 2239 | fits_in_signed_word (addressT num) |
252b5132 | 2240 | { |
65879393 | 2241 | return num + 0x8000 <= 0xffff; |
47926f60 | 2242 | } |
2a962e6d | 2243 | |
3e73aa7c | 2244 | static INLINE int |
65879393 | 2245 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2246 | { |
2247 | #ifndef BFD64 | |
2248 | return 1; | |
2249 | #else | |
65879393 | 2250 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2251 | #endif |
2252 | } /* fits_in_signed_long() */ | |
2a962e6d | 2253 | |
3e73aa7c | 2254 | static INLINE int |
65879393 | 2255 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2256 | { |
2257 | #ifndef BFD64 | |
2258 | return 1; | |
2259 | #else | |
65879393 | 2260 | return num <= 0xffffffff; |
3e73aa7c JH |
2261 | #endif |
2262 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2263 | |
43234a1e | 2264 | static INLINE int |
b5014f7a | 2265 | fits_in_disp8 (offsetT num) |
43234a1e L |
2266 | { |
2267 | int shift = i.memshift; | |
2268 | unsigned int mask; | |
2269 | ||
2270 | if (shift == -1) | |
2271 | abort (); | |
2272 | ||
2273 | mask = (1 << shift) - 1; | |
2274 | ||
2275 | /* Return 0 if NUM isn't properly aligned. */ | |
2276 | if ((num & mask)) | |
2277 | return 0; | |
2278 | ||
2279 | /* Check if NUM will fit in 8bit after shift. */ | |
2280 | return fits_in_signed_byte (num >> shift); | |
2281 | } | |
2282 | ||
a683cc34 SP |
2283 | static INLINE int |
2284 | fits_in_imm4 (offsetT num) | |
2285 | { | |
2286 | return (num & 0xf) == num; | |
2287 | } | |
2288 | ||
40fb9820 | 2289 | static i386_operand_type |
e3bb37b5 | 2290 | smallest_imm_type (offsetT num) |
252b5132 | 2291 | { |
40fb9820 | 2292 | i386_operand_type t; |
7ab9ffdd | 2293 | |
0dfbf9d7 | 2294 | operand_type_set (&t, 0); |
40fb9820 L |
2295 | t.bitfield.imm64 = 1; |
2296 | ||
2297 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2298 | { |
2299 | /* This code is disabled on the 486 because all the Imm1 forms | |
2300 | in the opcode table are slower on the i486. They're the | |
2301 | versions with the implicitly specified single-position | |
2302 | displacement, which has another syntax if you really want to | |
2303 | use that form. */ | |
40fb9820 L |
2304 | t.bitfield.imm1 = 1; |
2305 | t.bitfield.imm8 = 1; | |
2306 | t.bitfield.imm8s = 1; | |
2307 | t.bitfield.imm16 = 1; | |
2308 | t.bitfield.imm32 = 1; | |
2309 | t.bitfield.imm32s = 1; | |
2310 | } | |
2311 | else if (fits_in_signed_byte (num)) | |
2312 | { | |
2313 | t.bitfield.imm8 = 1; | |
2314 | t.bitfield.imm8s = 1; | |
2315 | t.bitfield.imm16 = 1; | |
2316 | t.bitfield.imm32 = 1; | |
2317 | t.bitfield.imm32s = 1; | |
2318 | } | |
2319 | else if (fits_in_unsigned_byte (num)) | |
2320 | { | |
2321 | t.bitfield.imm8 = 1; | |
2322 | t.bitfield.imm16 = 1; | |
2323 | t.bitfield.imm32 = 1; | |
2324 | t.bitfield.imm32s = 1; | |
2325 | } | |
2326 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2327 | { | |
2328 | t.bitfield.imm16 = 1; | |
2329 | t.bitfield.imm32 = 1; | |
2330 | t.bitfield.imm32s = 1; | |
2331 | } | |
2332 | else if (fits_in_signed_long (num)) | |
2333 | { | |
2334 | t.bitfield.imm32 = 1; | |
2335 | t.bitfield.imm32s = 1; | |
2336 | } | |
2337 | else if (fits_in_unsigned_long (num)) | |
2338 | t.bitfield.imm32 = 1; | |
2339 | ||
2340 | return t; | |
47926f60 | 2341 | } |
252b5132 | 2342 | |
847f7ad4 | 2343 | static offsetT |
e3bb37b5 | 2344 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2345 | { |
508866be | 2346 | addressT mask; |
ba2adb93 | 2347 | |
847f7ad4 AM |
2348 | switch (size) |
2349 | { | |
508866be L |
2350 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2351 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 2352 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
2353 | #ifdef BFD64 |
2354 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
2355 | #endif | |
47926f60 | 2356 | default: abort (); |
847f7ad4 AM |
2357 | } |
2358 | ||
9de868bf L |
2359 | #ifdef BFD64 |
2360 | /* If BFD64, sign extend val for 32bit address mode. */ | |
2361 | if (flag_code != CODE_64BIT | |
2362 | || i.prefix[ADDR_PREFIX]) | |
3e73aa7c JH |
2363 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
2364 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
fa289fb8 | 2365 | #endif |
ba2adb93 | 2366 | |
47926f60 | 2367 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
2368 | { |
2369 | char buf1[40], buf2[40]; | |
2370 | ||
2371 | sprint_value (buf1, val); | |
2372 | sprint_value (buf2, val & mask); | |
2373 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
2374 | } | |
2375 | return val & mask; | |
2376 | } | |
2377 | ||
c32fa91d L |
2378 | enum PREFIX_GROUP |
2379 | { | |
2380 | PREFIX_EXIST = 0, | |
2381 | PREFIX_LOCK, | |
2382 | PREFIX_REP, | |
04ef582a | 2383 | PREFIX_DS, |
c32fa91d L |
2384 | PREFIX_OTHER |
2385 | }; | |
2386 | ||
2387 | /* Returns | |
2388 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2389 | same class already exists. | |
2390 | b. PREFIX_LOCK if lock prefix is added. | |
2391 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2392 | d. PREFIX_DS if ds prefix is added. |
2393 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2394 | */ |
2395 | ||
2396 | static enum PREFIX_GROUP | |
e3bb37b5 | 2397 | add_prefix (unsigned int prefix) |
252b5132 | 2398 | { |
c32fa91d | 2399 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2400 | unsigned int q; |
252b5132 | 2401 | |
29b0f896 AM |
2402 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2403 | && flag_code == CODE_64BIT) | |
b1905489 | 2404 | { |
161a04f6 | 2405 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
44846f29 JB |
2406 | || (i.prefix[REX_PREFIX] & prefix & REX_R) |
2407 | || (i.prefix[REX_PREFIX] & prefix & REX_X) | |
2408 | || (i.prefix[REX_PREFIX] & prefix & REX_B)) | |
c32fa91d | 2409 | ret = PREFIX_EXIST; |
b1905489 JB |
2410 | q = REX_PREFIX; |
2411 | } | |
3e73aa7c | 2412 | else |
b1905489 JB |
2413 | { |
2414 | switch (prefix) | |
2415 | { | |
2416 | default: | |
2417 | abort (); | |
2418 | ||
b1905489 | 2419 | case DS_PREFIX_OPCODE: |
04ef582a L |
2420 | ret = PREFIX_DS; |
2421 | /* Fall through. */ | |
2422 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2423 | case ES_PREFIX_OPCODE: |
2424 | case FS_PREFIX_OPCODE: | |
2425 | case GS_PREFIX_OPCODE: | |
2426 | case SS_PREFIX_OPCODE: | |
2427 | q = SEG_PREFIX; | |
2428 | break; | |
2429 | ||
2430 | case REPNE_PREFIX_OPCODE: | |
2431 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2432 | q = REP_PREFIX; |
2433 | ret = PREFIX_REP; | |
2434 | break; | |
2435 | ||
b1905489 | 2436 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2437 | q = LOCK_PREFIX; |
2438 | ret = PREFIX_LOCK; | |
b1905489 JB |
2439 | break; |
2440 | ||
2441 | case FWAIT_OPCODE: | |
2442 | q = WAIT_PREFIX; | |
2443 | break; | |
2444 | ||
2445 | case ADDR_PREFIX_OPCODE: | |
2446 | q = ADDR_PREFIX; | |
2447 | break; | |
2448 | ||
2449 | case DATA_PREFIX_OPCODE: | |
2450 | q = DATA_PREFIX; | |
2451 | break; | |
2452 | } | |
2453 | if (i.prefix[q] != 0) | |
c32fa91d | 2454 | ret = PREFIX_EXIST; |
b1905489 | 2455 | } |
252b5132 | 2456 | |
b1905489 | 2457 | if (ret) |
252b5132 | 2458 | { |
b1905489 JB |
2459 | if (!i.prefix[q]) |
2460 | ++i.prefixes; | |
2461 | i.prefix[q] |= prefix; | |
252b5132 | 2462 | } |
b1905489 JB |
2463 | else |
2464 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2465 | |
252b5132 RH |
2466 | return ret; |
2467 | } | |
2468 | ||
2469 | static void | |
78f12dd3 | 2470 | update_code_flag (int value, int check) |
eecb386c | 2471 | { |
78f12dd3 L |
2472 | PRINTF_LIKE ((*as_error)); |
2473 | ||
1e9cc1c2 | 2474 | flag_code = (enum flag_code) value; |
40fb9820 L |
2475 | if (flag_code == CODE_64BIT) |
2476 | { | |
2477 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2478 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2479 | } |
2480 | else | |
2481 | { | |
2482 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2483 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2484 | } |
2485 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2486 | { |
78f12dd3 L |
2487 | if (check) |
2488 | as_error = as_fatal; | |
2489 | else | |
2490 | as_error = as_bad; | |
2491 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2492 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2493 | } |
40fb9820 | 2494 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2495 | { |
78f12dd3 L |
2496 | if (check) |
2497 | as_error = as_fatal; | |
2498 | else | |
2499 | as_error = as_bad; | |
2500 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2501 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2502 | } |
eecb386c AM |
2503 | stackop_size = '\0'; |
2504 | } | |
2505 | ||
78f12dd3 L |
2506 | static void |
2507 | set_code_flag (int value) | |
2508 | { | |
2509 | update_code_flag (value, 0); | |
2510 | } | |
2511 | ||
eecb386c | 2512 | static void |
e3bb37b5 | 2513 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2514 | { |
1e9cc1c2 | 2515 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2516 | if (flag_code != CODE_16BIT) |
2517 | abort (); | |
2518 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2519 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2520 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2521 | } |
2522 | ||
2523 | static void | |
e3bb37b5 | 2524 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2525 | { |
2526 | /* Find out if register prefixing is specified. */ | |
2527 | int ask_naked_reg = 0; | |
2528 | ||
2529 | SKIP_WHITESPACE (); | |
29b0f896 | 2530 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2531 | { |
d02603dc NC |
2532 | char *string; |
2533 | int e = get_symbol_name (&string); | |
252b5132 | 2534 | |
47926f60 | 2535 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2536 | ask_naked_reg = 1; |
47926f60 | 2537 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2538 | ask_naked_reg = -1; |
2539 | else | |
d0b47220 | 2540 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2541 | (void) restore_line_pointer (e); |
252b5132 RH |
2542 | } |
2543 | demand_empty_rest_of_line (); | |
c3332e24 | 2544 | |
252b5132 RH |
2545 | intel_syntax = syntax_flag; |
2546 | ||
2547 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2548 | allow_naked_reg = (intel_syntax |
2549 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2550 | else |
2551 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2552 | |
ee86248c | 2553 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2554 | |
e4a3b5a4 | 2555 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2556 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2557 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2558 | } |
2559 | ||
1efbbeb4 L |
2560 | static void |
2561 | set_intel_mnemonic (int mnemonic_flag) | |
2562 | { | |
e1d4d893 | 2563 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2564 | } |
2565 | ||
db51cc60 L |
2566 | static void |
2567 | set_allow_index_reg (int flag) | |
2568 | { | |
2569 | allow_index_reg = flag; | |
2570 | } | |
2571 | ||
cb19c032 | 2572 | static void |
7bab8ab5 | 2573 | set_check (int what) |
cb19c032 | 2574 | { |
7bab8ab5 JB |
2575 | enum check_kind *kind; |
2576 | const char *str; | |
2577 | ||
2578 | if (what) | |
2579 | { | |
2580 | kind = &operand_check; | |
2581 | str = "operand"; | |
2582 | } | |
2583 | else | |
2584 | { | |
2585 | kind = &sse_check; | |
2586 | str = "sse"; | |
2587 | } | |
2588 | ||
cb19c032 L |
2589 | SKIP_WHITESPACE (); |
2590 | ||
2591 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2592 | { | |
d02603dc NC |
2593 | char *string; |
2594 | int e = get_symbol_name (&string); | |
cb19c032 L |
2595 | |
2596 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2597 | *kind = check_none; |
cb19c032 | 2598 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2599 | *kind = check_warning; |
cb19c032 | 2600 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2601 | *kind = check_error; |
cb19c032 | 2602 | else |
7bab8ab5 | 2603 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2604 | (void) restore_line_pointer (e); |
cb19c032 L |
2605 | } |
2606 | else | |
7bab8ab5 | 2607 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2608 | |
2609 | demand_empty_rest_of_line (); | |
2610 | } | |
2611 | ||
8a9036a4 L |
2612 | static void |
2613 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2614 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2615 | { |
2616 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2617 | static const char *arch; | |
2618 | ||
2619 | /* Intel LIOM is only supported on ELF. */ | |
2620 | if (!IS_ELF) | |
2621 | return; | |
2622 | ||
2623 | if (!arch) | |
2624 | { | |
2625 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2626 | use default_arch. */ | |
2627 | arch = cpu_arch_name; | |
2628 | if (!arch) | |
2629 | arch = default_arch; | |
2630 | } | |
2631 | ||
81486035 L |
2632 | /* If we are targeting Intel MCU, we must enable it. */ |
2633 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU | |
2634 | || new_flag.bitfield.cpuiamcu) | |
2635 | return; | |
2636 | ||
3632d14b | 2637 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2638 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2639 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2640 | return; |
76ba9986 | 2641 | |
7a9068fe L |
2642 | /* If we are targeting Intel K1OM, we must enable it. */ |
2643 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2644 | || new_flag.bitfield.cpuk1om) | |
2645 | return; | |
2646 | ||
8a9036a4 L |
2647 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2648 | #endif | |
2649 | } | |
2650 | ||
e413e4e9 | 2651 | static void |
e3bb37b5 | 2652 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2653 | { |
47926f60 | 2654 | SKIP_WHITESPACE (); |
e413e4e9 | 2655 | |
29b0f896 | 2656 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2657 | { |
d02603dc NC |
2658 | char *string; |
2659 | int e = get_symbol_name (&string); | |
91d6fa6a | 2660 | unsigned int j; |
40fb9820 | 2661 | i386_cpu_flags flags; |
e413e4e9 | 2662 | |
91d6fa6a | 2663 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2664 | { |
91d6fa6a | 2665 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2666 | { |
91d6fa6a | 2667 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2668 | |
5c6af06e JB |
2669 | if (*string != '.') |
2670 | { | |
91d6fa6a | 2671 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2672 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2673 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2674 | if (flag_code == CODE_64BIT) |
2675 | { | |
2676 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2677 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2678 | } | |
2679 | else | |
2680 | { | |
2681 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2682 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2683 | } | |
91d6fa6a NC |
2684 | cpu_arch_isa = cpu_arch[j].type; |
2685 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2686 | if (!cpu_arch_tune_set) |
2687 | { | |
2688 | cpu_arch_tune = cpu_arch_isa; | |
2689 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2690 | } | |
5c6af06e JB |
2691 | break; |
2692 | } | |
40fb9820 | 2693 | |
293f5f65 L |
2694 | flags = cpu_flags_or (cpu_arch_flags, |
2695 | cpu_arch[j].flags); | |
81486035 | 2696 | |
5b64d091 | 2697 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2698 | { |
6305a203 L |
2699 | if (cpu_sub_arch_name) |
2700 | { | |
2701 | char *name = cpu_sub_arch_name; | |
2702 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2703 | cpu_arch[j].name, |
1bf57e9f | 2704 | (const char *) NULL); |
6305a203 L |
2705 | free (name); |
2706 | } | |
2707 | else | |
91d6fa6a | 2708 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2709 | cpu_arch_flags = flags; |
a586129e | 2710 | cpu_arch_isa_flags = flags; |
5c6af06e | 2711 | } |
0089dace L |
2712 | else |
2713 | cpu_arch_isa_flags | |
2714 | = cpu_flags_or (cpu_arch_isa_flags, | |
2715 | cpu_arch[j].flags); | |
d02603dc | 2716 | (void) restore_line_pointer (e); |
5c6af06e JB |
2717 | demand_empty_rest_of_line (); |
2718 | return; | |
e413e4e9 AM |
2719 | } |
2720 | } | |
293f5f65 L |
2721 | |
2722 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) | |
2723 | { | |
33eaf5de | 2724 | /* Disable an ISA extension. */ |
293f5f65 L |
2725 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
2726 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) | |
2727 | { | |
2728 | flags = cpu_flags_and_not (cpu_arch_flags, | |
2729 | cpu_noarch[j].flags); | |
2730 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2731 | { | |
2732 | if (cpu_sub_arch_name) | |
2733 | { | |
2734 | char *name = cpu_sub_arch_name; | |
2735 | cpu_sub_arch_name = concat (name, string, | |
2736 | (const char *) NULL); | |
2737 | free (name); | |
2738 | } | |
2739 | else | |
2740 | cpu_sub_arch_name = xstrdup (string); | |
2741 | cpu_arch_flags = flags; | |
2742 | cpu_arch_isa_flags = flags; | |
2743 | } | |
2744 | (void) restore_line_pointer (e); | |
2745 | demand_empty_rest_of_line (); | |
2746 | return; | |
2747 | } | |
2748 | ||
2749 | j = ARRAY_SIZE (cpu_arch); | |
2750 | } | |
2751 | ||
91d6fa6a | 2752 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2753 | as_bad (_("no such architecture: `%s'"), string); |
2754 | ||
2755 | *input_line_pointer = e; | |
2756 | } | |
2757 | else | |
2758 | as_bad (_("missing cpu architecture")); | |
2759 | ||
fddf5b5b AM |
2760 | no_cond_jump_promotion = 0; |
2761 | if (*input_line_pointer == ',' | |
29b0f896 | 2762 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2763 | { |
d02603dc NC |
2764 | char *string; |
2765 | char e; | |
2766 | ||
2767 | ++input_line_pointer; | |
2768 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2769 | |
2770 | if (strcmp (string, "nojumps") == 0) | |
2771 | no_cond_jump_promotion = 1; | |
2772 | else if (strcmp (string, "jumps") == 0) | |
2773 | ; | |
2774 | else | |
2775 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2776 | ||
d02603dc | 2777 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2778 | } |
2779 | ||
e413e4e9 AM |
2780 | demand_empty_rest_of_line (); |
2781 | } | |
2782 | ||
8a9036a4 L |
2783 | enum bfd_architecture |
2784 | i386_arch (void) | |
2785 | { | |
3632d14b | 2786 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2787 | { |
2788 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2789 | || flag_code != CODE_64BIT) | |
2790 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2791 | return bfd_arch_l1om; | |
2792 | } | |
7a9068fe L |
2793 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2794 | { | |
2795 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2796 | || flag_code != CODE_64BIT) | |
2797 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2798 | return bfd_arch_k1om; | |
2799 | } | |
81486035 L |
2800 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
2801 | { | |
2802 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2803 | || flag_code == CODE_64BIT) | |
2804 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2805 | return bfd_arch_iamcu; | |
2806 | } | |
8a9036a4 L |
2807 | else |
2808 | return bfd_arch_i386; | |
2809 | } | |
2810 | ||
b9d79e03 | 2811 | unsigned long |
7016a5d5 | 2812 | i386_mach (void) |
b9d79e03 | 2813 | { |
351f65ca | 2814 | if (!strncmp (default_arch, "x86_64", 6)) |
8a9036a4 | 2815 | { |
3632d14b | 2816 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 2817 | { |
351f65ca L |
2818 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
2819 | || default_arch[6] != '\0') | |
8a9036a4 L |
2820 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
2821 | return bfd_mach_l1om; | |
2822 | } | |
7a9068fe L |
2823 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2824 | { | |
2825 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2826 | || default_arch[6] != '\0') | |
2827 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2828 | return bfd_mach_k1om; | |
2829 | } | |
351f65ca | 2830 | else if (default_arch[6] == '\0') |
8a9036a4 | 2831 | return bfd_mach_x86_64; |
351f65ca L |
2832 | else |
2833 | return bfd_mach_x64_32; | |
8a9036a4 | 2834 | } |
5197d474 L |
2835 | else if (!strcmp (default_arch, "i386") |
2836 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
2837 | { |
2838 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
2839 | { | |
2840 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
2841 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2842 | return bfd_mach_i386_iamcu; | |
2843 | } | |
2844 | else | |
2845 | return bfd_mach_i386_i386; | |
2846 | } | |
b9d79e03 | 2847 | else |
2b5d6a91 | 2848 | as_fatal (_("unknown architecture")); |
b9d79e03 | 2849 | } |
b9d79e03 | 2850 | \f |
252b5132 | 2851 | void |
7016a5d5 | 2852 | md_begin (void) |
252b5132 RH |
2853 | { |
2854 | const char *hash_err; | |
2855 | ||
86fa6981 L |
2856 | /* Support pseudo prefixes like {disp32}. */ |
2857 | lex_type ['{'] = LEX_BEGIN_NAME; | |
2858 | ||
47926f60 | 2859 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2860 | op_hash = hash_new (); |
2861 | ||
2862 | { | |
d3ce72d0 | 2863 | const insn_template *optab; |
29b0f896 | 2864 | templates *core_optab; |
252b5132 | 2865 | |
47926f60 KH |
2866 | /* Setup for loop. */ |
2867 | optab = i386_optab; | |
add39d23 | 2868 | core_optab = XNEW (templates); |
252b5132 RH |
2869 | core_optab->start = optab; |
2870 | ||
2871 | while (1) | |
2872 | { | |
2873 | ++optab; | |
2874 | if (optab->name == NULL | |
2875 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
2876 | { | |
2877 | /* different name --> ship out current template list; | |
47926f60 | 2878 | add to hash table; & begin anew. */ |
252b5132 RH |
2879 | core_optab->end = optab; |
2880 | hash_err = hash_insert (op_hash, | |
2881 | (optab - 1)->name, | |
5a49b8ac | 2882 | (void *) core_optab); |
252b5132 RH |
2883 | if (hash_err) |
2884 | { | |
b37df7c4 | 2885 | as_fatal (_("can't hash %s: %s"), |
252b5132 RH |
2886 | (optab - 1)->name, |
2887 | hash_err); | |
2888 | } | |
2889 | if (optab->name == NULL) | |
2890 | break; | |
add39d23 | 2891 | core_optab = XNEW (templates); |
252b5132 RH |
2892 | core_optab->start = optab; |
2893 | } | |
2894 | } | |
2895 | } | |
2896 | ||
47926f60 | 2897 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
2898 | reg_hash = hash_new (); |
2899 | { | |
29b0f896 | 2900 | const reg_entry *regtab; |
c3fe08fa | 2901 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 2902 | |
c3fe08fa | 2903 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 2904 | { |
5a49b8ac | 2905 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 2906 | if (hash_err) |
b37df7c4 | 2907 | as_fatal (_("can't hash %s: %s"), |
3e73aa7c JH |
2908 | regtab->reg_name, |
2909 | hash_err); | |
252b5132 RH |
2910 | } |
2911 | } | |
2912 | ||
47926f60 | 2913 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 2914 | { |
29b0f896 AM |
2915 | int c; |
2916 | char *p; | |
252b5132 RH |
2917 | |
2918 | for (c = 0; c < 256; c++) | |
2919 | { | |
3882b010 | 2920 | if (ISDIGIT (c)) |
252b5132 RH |
2921 | { |
2922 | digit_chars[c] = c; | |
2923 | mnemonic_chars[c] = c; | |
2924 | register_chars[c] = c; | |
2925 | operand_chars[c] = c; | |
2926 | } | |
3882b010 | 2927 | else if (ISLOWER (c)) |
252b5132 RH |
2928 | { |
2929 | mnemonic_chars[c] = c; | |
2930 | register_chars[c] = c; | |
2931 | operand_chars[c] = c; | |
2932 | } | |
3882b010 | 2933 | else if (ISUPPER (c)) |
252b5132 | 2934 | { |
3882b010 | 2935 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
2936 | register_chars[c] = mnemonic_chars[c]; |
2937 | operand_chars[c] = c; | |
2938 | } | |
43234a1e | 2939 | else if (c == '{' || c == '}') |
86fa6981 L |
2940 | { |
2941 | mnemonic_chars[c] = c; | |
2942 | operand_chars[c] = c; | |
2943 | } | |
252b5132 | 2944 | |
3882b010 | 2945 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
2946 | identifier_chars[c] = c; |
2947 | else if (c >= 128) | |
2948 | { | |
2949 | identifier_chars[c] = c; | |
2950 | operand_chars[c] = c; | |
2951 | } | |
2952 | } | |
2953 | ||
2954 | #ifdef LEX_AT | |
2955 | identifier_chars['@'] = '@'; | |
32137342 NC |
2956 | #endif |
2957 | #ifdef LEX_QM | |
2958 | identifier_chars['?'] = '?'; | |
2959 | operand_chars['?'] = '?'; | |
252b5132 | 2960 | #endif |
252b5132 | 2961 | digit_chars['-'] = '-'; |
c0f3af97 | 2962 | mnemonic_chars['_'] = '_'; |
791fe849 | 2963 | mnemonic_chars['-'] = '-'; |
0003779b | 2964 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
2965 | identifier_chars['_'] = '_'; |
2966 | identifier_chars['.'] = '.'; | |
2967 | ||
2968 | for (p = operand_special_chars; *p != '\0'; p++) | |
2969 | operand_chars[(unsigned char) *p] = *p; | |
2970 | } | |
2971 | ||
a4447b93 RH |
2972 | if (flag_code == CODE_64BIT) |
2973 | { | |
ca19b261 KT |
2974 | #if defined (OBJ_COFF) && defined (TE_PE) |
2975 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
2976 | ? 32 : 16); | |
2977 | #else | |
a4447b93 | 2978 | x86_dwarf2_return_column = 16; |
ca19b261 | 2979 | #endif |
61ff971f | 2980 | x86_cie_data_alignment = -8; |
a4447b93 RH |
2981 | } |
2982 | else | |
2983 | { | |
2984 | x86_dwarf2_return_column = 8; | |
2985 | x86_cie_data_alignment = -4; | |
2986 | } | |
252b5132 RH |
2987 | } |
2988 | ||
2989 | void | |
e3bb37b5 | 2990 | i386_print_statistics (FILE *file) |
252b5132 RH |
2991 | { |
2992 | hash_print_statistics (file, "i386 opcode", op_hash); | |
2993 | hash_print_statistics (file, "i386 register", reg_hash); | |
2994 | } | |
2995 | \f | |
252b5132 RH |
2996 | #ifdef DEBUG386 |
2997 | ||
ce8a8b2f | 2998 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 2999 | static void pte (insn_template *); |
40fb9820 | 3000 | static void pt (i386_operand_type); |
e3bb37b5 L |
3001 | static void pe (expressionS *); |
3002 | static void ps (symbolS *); | |
252b5132 RH |
3003 | |
3004 | static void | |
2c703856 | 3005 | pi (const char *line, i386_insn *x) |
252b5132 | 3006 | { |
09137c09 | 3007 | unsigned int j; |
252b5132 RH |
3008 | |
3009 | fprintf (stdout, "%s: template ", line); | |
3010 | pte (&x->tm); | |
09f131f2 JH |
3011 | fprintf (stdout, " address: base %s index %s scale %x\n", |
3012 | x->base_reg ? x->base_reg->reg_name : "none", | |
3013 | x->index_reg ? x->index_reg->reg_name : "none", | |
3014 | x->log2_scale_factor); | |
3015 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 3016 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
3017 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
3018 | x->sib.base, x->sib.index, x->sib.scale); | |
3019 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
3020 | (x->rex & REX_W) != 0, |
3021 | (x->rex & REX_R) != 0, | |
3022 | (x->rex & REX_X) != 0, | |
3023 | (x->rex & REX_B) != 0); | |
09137c09 | 3024 | for (j = 0; j < x->operands; j++) |
252b5132 | 3025 | { |
09137c09 SP |
3026 | fprintf (stdout, " #%d: ", j + 1); |
3027 | pt (x->types[j]); | |
252b5132 | 3028 | fprintf (stdout, "\n"); |
dc821c5f | 3029 | if (x->types[j].bitfield.reg |
09137c09 | 3030 | || x->types[j].bitfield.regmmx |
1b54b8d7 | 3031 | || x->types[j].bitfield.regsimd |
09137c09 SP |
3032 | || x->types[j].bitfield.sreg2 |
3033 | || x->types[j].bitfield.sreg3 | |
3034 | || x->types[j].bitfield.control | |
3035 | || x->types[j].bitfield.debug | |
3036 | || x->types[j].bitfield.test) | |
3037 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); | |
3038 | if (operand_type_check (x->types[j], imm)) | |
3039 | pe (x->op[j].imms); | |
3040 | if (operand_type_check (x->types[j], disp)) | |
3041 | pe (x->op[j].disps); | |
252b5132 RH |
3042 | } |
3043 | } | |
3044 | ||
3045 | static void | |
d3ce72d0 | 3046 | pte (insn_template *t) |
252b5132 | 3047 | { |
09137c09 | 3048 | unsigned int j; |
252b5132 | 3049 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 3050 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
3051 | if (t->extension_opcode != None) |
3052 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 3053 | if (t->opcode_modifier.d) |
252b5132 | 3054 | fprintf (stdout, "D"); |
40fb9820 | 3055 | if (t->opcode_modifier.w) |
252b5132 RH |
3056 | fprintf (stdout, "W"); |
3057 | fprintf (stdout, "\n"); | |
09137c09 | 3058 | for (j = 0; j < t->operands; j++) |
252b5132 | 3059 | { |
09137c09 SP |
3060 | fprintf (stdout, " #%d type ", j + 1); |
3061 | pt (t->operand_types[j]); | |
252b5132 RH |
3062 | fprintf (stdout, "\n"); |
3063 | } | |
3064 | } | |
3065 | ||
3066 | static void | |
e3bb37b5 | 3067 | pe (expressionS *e) |
252b5132 | 3068 | { |
24eab124 | 3069 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
3070 | fprintf (stdout, " add_number %ld (%lx)\n", |
3071 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
3072 | if (e->X_add_symbol) |
3073 | { | |
3074 | fprintf (stdout, " add_symbol "); | |
3075 | ps (e->X_add_symbol); | |
3076 | fprintf (stdout, "\n"); | |
3077 | } | |
3078 | if (e->X_op_symbol) | |
3079 | { | |
3080 | fprintf (stdout, " op_symbol "); | |
3081 | ps (e->X_op_symbol); | |
3082 | fprintf (stdout, "\n"); | |
3083 | } | |
3084 | } | |
3085 | ||
3086 | static void | |
e3bb37b5 | 3087 | ps (symbolS *s) |
252b5132 RH |
3088 | { |
3089 | fprintf (stdout, "%s type %s%s", | |
3090 | S_GET_NAME (s), | |
3091 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
3092 | segment_name (S_GET_SEGMENT (s))); | |
3093 | } | |
3094 | ||
7b81dfbb | 3095 | static struct type_name |
252b5132 | 3096 | { |
40fb9820 L |
3097 | i386_operand_type mask; |
3098 | const char *name; | |
252b5132 | 3099 | } |
7b81dfbb | 3100 | const type_names[] = |
252b5132 | 3101 | { |
40fb9820 L |
3102 | { OPERAND_TYPE_REG8, "r8" }, |
3103 | { OPERAND_TYPE_REG16, "r16" }, | |
3104 | { OPERAND_TYPE_REG32, "r32" }, | |
3105 | { OPERAND_TYPE_REG64, "r64" }, | |
2c703856 JB |
3106 | { OPERAND_TYPE_ACC8, "acc8" }, |
3107 | { OPERAND_TYPE_ACC16, "acc16" }, | |
3108 | { OPERAND_TYPE_ACC32, "acc32" }, | |
3109 | { OPERAND_TYPE_ACC64, "acc64" }, | |
40fb9820 L |
3110 | { OPERAND_TYPE_IMM8, "i8" }, |
3111 | { OPERAND_TYPE_IMM8, "i8s" }, | |
3112 | { OPERAND_TYPE_IMM16, "i16" }, | |
3113 | { OPERAND_TYPE_IMM32, "i32" }, | |
3114 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
3115 | { OPERAND_TYPE_IMM64, "i64" }, | |
3116 | { OPERAND_TYPE_IMM1, "i1" }, | |
3117 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
3118 | { OPERAND_TYPE_DISP8, "d8" }, | |
3119 | { OPERAND_TYPE_DISP16, "d16" }, | |
3120 | { OPERAND_TYPE_DISP32, "d32" }, | |
3121 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
3122 | { OPERAND_TYPE_DISP64, "d64" }, | |
3123 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
3124 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
3125 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
3126 | { OPERAND_TYPE_TEST, "test reg" }, | |
3127 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
3128 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
3129 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
3130 | { OPERAND_TYPE_SREG2, "SReg2" }, | |
3131 | { OPERAND_TYPE_SREG3, "SReg3" }, | |
40fb9820 L |
3132 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, |
3133 | { OPERAND_TYPE_REGMMX, "rMMX" }, | |
3134 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 3135 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
43234a1e L |
3136 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
3137 | { OPERAND_TYPE_REGMASK, "Mask reg" }, | |
40fb9820 | 3138 | { OPERAND_TYPE_ESSEG, "es" }, |
252b5132 RH |
3139 | }; |
3140 | ||
3141 | static void | |
40fb9820 | 3142 | pt (i386_operand_type t) |
252b5132 | 3143 | { |
40fb9820 | 3144 | unsigned int j; |
c6fb90c8 | 3145 | i386_operand_type a; |
252b5132 | 3146 | |
40fb9820 | 3147 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3148 | { |
3149 | a = operand_type_and (t, type_names[j].mask); | |
2c703856 | 3150 | if (operand_type_equal (&a, &type_names[j].mask)) |
c6fb90c8 L |
3151 | fprintf (stdout, "%s, ", type_names[j].name); |
3152 | } | |
252b5132 RH |
3153 | fflush (stdout); |
3154 | } | |
3155 | ||
3156 | #endif /* DEBUG386 */ | |
3157 | \f | |
252b5132 | 3158 | static bfd_reloc_code_real_type |
3956db08 | 3159 | reloc (unsigned int size, |
64e74474 AM |
3160 | int pcrel, |
3161 | int sign, | |
3162 | bfd_reloc_code_real_type other) | |
252b5132 | 3163 | { |
47926f60 | 3164 | if (other != NO_RELOC) |
3956db08 | 3165 | { |
91d6fa6a | 3166 | reloc_howto_type *rel; |
3956db08 JB |
3167 | |
3168 | if (size == 8) | |
3169 | switch (other) | |
3170 | { | |
64e74474 AM |
3171 | case BFD_RELOC_X86_64_GOT32: |
3172 | return BFD_RELOC_X86_64_GOT64; | |
3173 | break; | |
553d1284 L |
3174 | case BFD_RELOC_X86_64_GOTPLT64: |
3175 | return BFD_RELOC_X86_64_GOTPLT64; | |
3176 | break; | |
64e74474 AM |
3177 | case BFD_RELOC_X86_64_PLTOFF64: |
3178 | return BFD_RELOC_X86_64_PLTOFF64; | |
3179 | break; | |
3180 | case BFD_RELOC_X86_64_GOTPC32: | |
3181 | other = BFD_RELOC_X86_64_GOTPC64; | |
3182 | break; | |
3183 | case BFD_RELOC_X86_64_GOTPCREL: | |
3184 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3185 | break; | |
3186 | case BFD_RELOC_X86_64_TPOFF32: | |
3187 | other = BFD_RELOC_X86_64_TPOFF64; | |
3188 | break; | |
3189 | case BFD_RELOC_X86_64_DTPOFF32: | |
3190 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3191 | break; | |
3192 | default: | |
3193 | break; | |
3956db08 | 3194 | } |
e05278af | 3195 | |
8ce3d284 | 3196 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3197 | if (other == BFD_RELOC_SIZE32) |
3198 | { | |
3199 | if (size == 8) | |
1ab668bf | 3200 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3201 | if (pcrel) |
1ab668bf AM |
3202 | { |
3203 | as_bad (_("there are no pc-relative size relocations")); | |
3204 | return NO_RELOC; | |
3205 | } | |
8fd4256d | 3206 | } |
8ce3d284 | 3207 | #endif |
8fd4256d | 3208 | |
e05278af | 3209 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3210 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3211 | sign = -1; |
3212 | ||
91d6fa6a NC |
3213 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3214 | if (!rel) | |
3956db08 | 3215 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3216 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3217 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3218 | bfd_get_reloc_size (rel), |
3956db08 | 3219 | size); |
91d6fa6a | 3220 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3221 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3222 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3223 | && !sign) |
91d6fa6a | 3224 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3225 | && sign > 0)) |
3956db08 JB |
3226 | as_bad (_("relocated field and relocation type differ in signedness")); |
3227 | else | |
3228 | return other; | |
3229 | return NO_RELOC; | |
3230 | } | |
252b5132 RH |
3231 | |
3232 | if (pcrel) | |
3233 | { | |
3e73aa7c | 3234 | if (!sign) |
3956db08 | 3235 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3236 | switch (size) |
3237 | { | |
3238 | case 1: return BFD_RELOC_8_PCREL; | |
3239 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3240 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3241 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3242 | } |
3956db08 | 3243 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3244 | } |
3245 | else | |
3246 | { | |
3956db08 | 3247 | if (sign > 0) |
e5cb08ac | 3248 | switch (size) |
3e73aa7c JH |
3249 | { |
3250 | case 4: return BFD_RELOC_X86_64_32S; | |
3251 | } | |
3252 | else | |
3253 | switch (size) | |
3254 | { | |
3255 | case 1: return BFD_RELOC_8; | |
3256 | case 2: return BFD_RELOC_16; | |
3257 | case 4: return BFD_RELOC_32; | |
3258 | case 8: return BFD_RELOC_64; | |
3259 | } | |
3956db08 JB |
3260 | as_bad (_("cannot do %s %u byte relocation"), |
3261 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3262 | } |
3263 | ||
0cc9e1d3 | 3264 | return NO_RELOC; |
252b5132 RH |
3265 | } |
3266 | ||
47926f60 KH |
3267 | /* Here we decide which fixups can be adjusted to make them relative to |
3268 | the beginning of the section instead of the symbol. Basically we need | |
3269 | to make sure that the dynamic relocations are done correctly, so in | |
3270 | some cases we force the original symbol to be used. */ | |
3271 | ||
252b5132 | 3272 | int |
e3bb37b5 | 3273 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3274 | { |
6d249963 | 3275 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3276 | if (!IS_ELF) |
31312f95 AM |
3277 | return 1; |
3278 | ||
a161fe53 AM |
3279 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3280 | mode. */ | |
3281 | if (use_rela_relocations | |
3282 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3283 | && fixP->fx_pcrel) | |
252b5132 | 3284 | return 0; |
31312f95 | 3285 | |
8d01d9a9 AJ |
3286 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3287 | and changed later by validate_fix. */ | |
3288 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3289 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3290 | return 0; | |
3291 | ||
8fd4256d L |
3292 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3293 | for size relocations. */ | |
3294 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3295 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3296 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 RH |
3297 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 |
3298 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
02a86693 | 3299 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3300 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3301 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3302 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3303 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3304 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3305 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3306 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3307 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3308 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3309 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
3310 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
3311 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 3312 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3313 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3314 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3315 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3316 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3317 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3318 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3319 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3320 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3321 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3322 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3323 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3324 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3325 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3326 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3327 | return 0; | |
31312f95 | 3328 | #endif |
252b5132 RH |
3329 | return 1; |
3330 | } | |
252b5132 | 3331 | |
b4cac588 | 3332 | static int |
e3bb37b5 | 3333 | intel_float_operand (const char *mnemonic) |
252b5132 | 3334 | { |
9306ca4a JB |
3335 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3336 | operands, hence the code here is free to improperly handle opcodes that | |
3337 | have no operands (for better performance and smaller code). */ | |
3338 | ||
3339 | if (mnemonic[0] != 'f') | |
3340 | return 0; /* non-math */ | |
3341 | ||
3342 | switch (mnemonic[1]) | |
3343 | { | |
3344 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3345 | the fs segment override prefix not currently handled because no | |
3346 | call path can make opcodes without operands get here */ | |
3347 | case 'i': | |
3348 | return 2 /* integer op */; | |
3349 | case 'l': | |
3350 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3351 | return 3; /* fldcw/fldenv */ | |
3352 | break; | |
3353 | case 'n': | |
3354 | if (mnemonic[2] != 'o' /* fnop */) | |
3355 | return 3; /* non-waiting control op */ | |
3356 | break; | |
3357 | case 'r': | |
3358 | if (mnemonic[2] == 's') | |
3359 | return 3; /* frstor/frstpm */ | |
3360 | break; | |
3361 | case 's': | |
3362 | if (mnemonic[2] == 'a') | |
3363 | return 3; /* fsave */ | |
3364 | if (mnemonic[2] == 't') | |
3365 | { | |
3366 | switch (mnemonic[3]) | |
3367 | { | |
3368 | case 'c': /* fstcw */ | |
3369 | case 'd': /* fstdw */ | |
3370 | case 'e': /* fstenv */ | |
3371 | case 's': /* fsts[gw] */ | |
3372 | return 3; | |
3373 | } | |
3374 | } | |
3375 | break; | |
3376 | case 'x': | |
3377 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3378 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3379 | break; | |
3380 | } | |
252b5132 | 3381 | |
9306ca4a | 3382 | return 1; |
252b5132 RH |
3383 | } |
3384 | ||
c0f3af97 L |
3385 | /* Build the VEX prefix. */ |
3386 | ||
3387 | static void | |
d3ce72d0 | 3388 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3389 | { |
3390 | unsigned int register_specifier; | |
3391 | unsigned int implied_prefix; | |
3392 | unsigned int vector_length; | |
03751133 | 3393 | unsigned int w; |
c0f3af97 L |
3394 | |
3395 | /* Check register specifier. */ | |
3396 | if (i.vex.register_specifier) | |
43234a1e L |
3397 | { |
3398 | register_specifier = | |
3399 | ~register_number (i.vex.register_specifier) & 0xf; | |
3400 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3401 | } | |
c0f3af97 L |
3402 | else |
3403 | register_specifier = 0xf; | |
3404 | ||
79f0fa25 L |
3405 | /* Use 2-byte VEX prefix by swapping destination and source operand |
3406 | if there are more than 1 register operand. */ | |
3407 | if (i.reg_operands > 1 | |
3408 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3409 | && i.dir_encoding == dir_encoding_default |
fa99fab2 | 3410 | && i.operands == i.reg_operands |
dbbc8b7e | 3411 | && operand_type_equal (&i.types[0], &i.types[i.operands - 1]) |
7f399153 | 3412 | && i.tm.opcode_modifier.vexopcode == VEX0F |
dbbc8b7e | 3413 | && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d) |
fa99fab2 L |
3414 | && i.rex == REX_B) |
3415 | { | |
3416 | unsigned int xchg = i.operands - 1; | |
3417 | union i386_op temp_op; | |
3418 | i386_operand_type temp_type; | |
3419 | ||
3420 | temp_type = i.types[xchg]; | |
3421 | i.types[xchg] = i.types[0]; | |
3422 | i.types[0] = temp_type; | |
3423 | temp_op = i.op[xchg]; | |
3424 | i.op[xchg] = i.op[0]; | |
3425 | i.op[0] = temp_op; | |
3426 | ||
9c2799c2 | 3427 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3428 | |
3429 | i.rex = REX_R; | |
3430 | xchg = i.rm.regmem; | |
3431 | i.rm.regmem = i.rm.reg; | |
3432 | i.rm.reg = xchg; | |
3433 | ||
dbbc8b7e JB |
3434 | if (i.tm.opcode_modifier.d) |
3435 | i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e | |
3436 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
3437 | else /* Use the next insn. */ | |
3438 | i.tm = t[1]; | |
fa99fab2 L |
3439 | } |
3440 | ||
539f890d L |
3441 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3442 | vector_length = avxscalar; | |
10c17abd JB |
3443 | else if (i.tm.opcode_modifier.vex == VEX256) |
3444 | vector_length = 1; | |
539f890d | 3445 | else |
10c17abd | 3446 | { |
56522fc5 | 3447 | unsigned int op; |
10c17abd | 3448 | |
c7213af9 L |
3449 | /* Determine vector length from the last multi-length vector |
3450 | operand. */ | |
10c17abd | 3451 | vector_length = 0; |
56522fc5 | 3452 | for (op = t->operands; op--;) |
10c17abd JB |
3453 | if (t->operand_types[op].bitfield.xmmword |
3454 | && t->operand_types[op].bitfield.ymmword | |
3455 | && i.types[op].bitfield.ymmword) | |
3456 | { | |
3457 | vector_length = 1; | |
3458 | break; | |
3459 | } | |
3460 | } | |
c0f3af97 L |
3461 | |
3462 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3463 | { | |
3464 | case 0: | |
3465 | implied_prefix = 0; | |
3466 | break; | |
3467 | case DATA_PREFIX_OPCODE: | |
3468 | implied_prefix = 1; | |
3469 | break; | |
3470 | case REPE_PREFIX_OPCODE: | |
3471 | implied_prefix = 2; | |
3472 | break; | |
3473 | case REPNE_PREFIX_OPCODE: | |
3474 | implied_prefix = 3; | |
3475 | break; | |
3476 | default: | |
3477 | abort (); | |
3478 | } | |
3479 | ||
03751133 L |
3480 | /* Check the REX.W bit and VEXW. */ |
3481 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3482 | w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3483 | else if (i.tm.opcode_modifier.vexw) | |
3484 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3485 | else | |
931d03b7 | 3486 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0; |
03751133 | 3487 | |
c0f3af97 | 3488 | /* Use 2-byte VEX prefix if possible. */ |
03751133 L |
3489 | if (w == 0 |
3490 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3491 | && i.tm.opcode_modifier.vexopcode == VEX0F |
c0f3af97 L |
3492 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3493 | { | |
3494 | /* 2-byte VEX prefix. */ | |
3495 | unsigned int r; | |
3496 | ||
3497 | i.vex.length = 2; | |
3498 | i.vex.bytes[0] = 0xc5; | |
3499 | ||
3500 | /* Check the REX.R bit. */ | |
3501 | r = (i.rex & REX_R) ? 0 : 1; | |
3502 | i.vex.bytes[1] = (r << 7 | |
3503 | | register_specifier << 3 | |
3504 | | vector_length << 2 | |
3505 | | implied_prefix); | |
3506 | } | |
3507 | else | |
3508 | { | |
3509 | /* 3-byte VEX prefix. */ | |
03751133 | 3510 | unsigned int m; |
c0f3af97 | 3511 | |
f88c9eb0 | 3512 | i.vex.length = 3; |
f88c9eb0 | 3513 | |
7f399153 | 3514 | switch (i.tm.opcode_modifier.vexopcode) |
5dd85c99 | 3515 | { |
7f399153 L |
3516 | case VEX0F: |
3517 | m = 0x1; | |
80de6e00 | 3518 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3519 | break; |
3520 | case VEX0F38: | |
3521 | m = 0x2; | |
80de6e00 | 3522 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3523 | break; |
3524 | case VEX0F3A: | |
3525 | m = 0x3; | |
80de6e00 | 3526 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3527 | break; |
3528 | case XOP08: | |
5dd85c99 SP |
3529 | m = 0x8; |
3530 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3531 | break; |
3532 | case XOP09: | |
f88c9eb0 SP |
3533 | m = 0x9; |
3534 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3535 | break; |
3536 | case XOP0A: | |
f88c9eb0 SP |
3537 | m = 0xa; |
3538 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3539 | break; |
3540 | default: | |
3541 | abort (); | |
f88c9eb0 | 3542 | } |
c0f3af97 | 3543 | |
c0f3af97 L |
3544 | /* The high 3 bits of the second VEX byte are 1's compliment |
3545 | of RXB bits from REX. */ | |
3546 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3547 | ||
c0f3af97 L |
3548 | i.vex.bytes[2] = (w << 7 |
3549 | | register_specifier << 3 | |
3550 | | vector_length << 2 | |
3551 | | implied_prefix); | |
3552 | } | |
3553 | } | |
3554 | ||
e771e7c9 JB |
3555 | static INLINE bfd_boolean |
3556 | is_evex_encoding (const insn_template *t) | |
3557 | { | |
7091c612 | 3558 | return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift |
e771e7c9 JB |
3559 | || t->opcode_modifier.broadcast || t->opcode_modifier.masking |
3560 | || t->opcode_modifier.staticrounding || t->opcode_modifier.sae; | |
3561 | } | |
3562 | ||
7a8655d2 JB |
3563 | static INLINE bfd_boolean |
3564 | is_any_vex_encoding (const insn_template *t) | |
3565 | { | |
3566 | return t->opcode_modifier.vex || t->opcode_modifier.vexopcode | |
3567 | || is_evex_encoding (t); | |
3568 | } | |
3569 | ||
43234a1e L |
3570 | /* Build the EVEX prefix. */ |
3571 | ||
3572 | static void | |
3573 | build_evex_prefix (void) | |
3574 | { | |
3575 | unsigned int register_specifier; | |
3576 | unsigned int implied_prefix; | |
3577 | unsigned int m, w; | |
3578 | rex_byte vrex_used = 0; | |
3579 | ||
3580 | /* Check register specifier. */ | |
3581 | if (i.vex.register_specifier) | |
3582 | { | |
3583 | gas_assert ((i.vrex & REX_X) == 0); | |
3584 | ||
3585 | register_specifier = i.vex.register_specifier->reg_num; | |
3586 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3587 | register_specifier += 8; | |
3588 | /* The upper 16 registers are encoded in the fourth byte of the | |
3589 | EVEX prefix. */ | |
3590 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3591 | i.vex.bytes[3] = 0x8; | |
3592 | register_specifier = ~register_specifier & 0xf; | |
3593 | } | |
3594 | else | |
3595 | { | |
3596 | register_specifier = 0xf; | |
3597 | ||
3598 | /* Encode upper 16 vector index register in the fourth byte of | |
3599 | the EVEX prefix. */ | |
3600 | if (!(i.vrex & REX_X)) | |
3601 | i.vex.bytes[3] = 0x8; | |
3602 | else | |
3603 | vrex_used |= REX_X; | |
3604 | } | |
3605 | ||
3606 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3607 | { | |
3608 | case 0: | |
3609 | implied_prefix = 0; | |
3610 | break; | |
3611 | case DATA_PREFIX_OPCODE: | |
3612 | implied_prefix = 1; | |
3613 | break; | |
3614 | case REPE_PREFIX_OPCODE: | |
3615 | implied_prefix = 2; | |
3616 | break; | |
3617 | case REPNE_PREFIX_OPCODE: | |
3618 | implied_prefix = 3; | |
3619 | break; | |
3620 | default: | |
3621 | abort (); | |
3622 | } | |
3623 | ||
3624 | /* 4 byte EVEX prefix. */ | |
3625 | i.vex.length = 4; | |
3626 | i.vex.bytes[0] = 0x62; | |
3627 | ||
3628 | /* mmmm bits. */ | |
3629 | switch (i.tm.opcode_modifier.vexopcode) | |
3630 | { | |
3631 | case VEX0F: | |
3632 | m = 1; | |
3633 | break; | |
3634 | case VEX0F38: | |
3635 | m = 2; | |
3636 | break; | |
3637 | case VEX0F3A: | |
3638 | m = 3; | |
3639 | break; | |
3640 | default: | |
3641 | abort (); | |
3642 | break; | |
3643 | } | |
3644 | ||
3645 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB | |
3646 | bits from REX. */ | |
3647 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3648 | ||
3649 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3650 | REX_R bit in VREX. */ | |
3651 | if (!(i.vrex & REX_R)) | |
3652 | i.vex.bytes[1] |= 0x10; | |
3653 | else | |
3654 | vrex_used |= REX_R; | |
3655 | ||
3656 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3657 | { | |
3658 | /* When all operands are registers, the REX_X bit in REX is not | |
3659 | used. We reuse it to encode the upper 16 registers, which is | |
3660 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3661 | as 1's compliment. */ | |
3662 | if ((i.vrex & REX_B)) | |
3663 | { | |
3664 | vrex_used |= REX_B; | |
3665 | i.vex.bytes[1] &= ~0x40; | |
3666 | } | |
3667 | } | |
3668 | ||
3669 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3670 | i.vrex &= ~vrex_used; | |
3671 | gas_assert (i.vrex == 0); | |
3672 | ||
6865c043 L |
3673 | /* Check the REX.W bit and VEXW. */ |
3674 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3675 | w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3676 | else if (i.tm.opcode_modifier.vexw) | |
3677 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3678 | else | |
931d03b7 | 3679 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0; |
43234a1e L |
3680 | |
3681 | /* Encode the U bit. */ | |
3682 | implied_prefix |= 0x4; | |
3683 | ||
3684 | /* The third byte of the EVEX prefix. */ | |
3685 | i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); | |
3686 | ||
3687 | /* The fourth byte of the EVEX prefix. */ | |
3688 | /* The zeroing-masking bit. */ | |
3689 | if (i.mask && i.mask->zeroing) | |
3690 | i.vex.bytes[3] |= 0x80; | |
3691 | ||
3692 | /* Don't always set the broadcast bit if there is no RC. */ | |
3693 | if (!i.rounding) | |
3694 | { | |
3695 | /* Encode the vector length. */ | |
3696 | unsigned int vec_length; | |
3697 | ||
e771e7c9 JB |
3698 | if (!i.tm.opcode_modifier.evex |
3699 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
3700 | { | |
56522fc5 | 3701 | unsigned int op; |
e771e7c9 | 3702 | |
c7213af9 L |
3703 | /* Determine vector length from the last multi-length vector |
3704 | operand. */ | |
e771e7c9 | 3705 | vec_length = 0; |
56522fc5 | 3706 | for (op = i.operands; op--;) |
e771e7c9 JB |
3707 | if (i.tm.operand_types[op].bitfield.xmmword |
3708 | + i.tm.operand_types[op].bitfield.ymmword | |
3709 | + i.tm.operand_types[op].bitfield.zmmword > 1) | |
3710 | { | |
3711 | if (i.types[op].bitfield.zmmword) | |
c7213af9 L |
3712 | { |
3713 | i.tm.opcode_modifier.evex = EVEX512; | |
3714 | break; | |
3715 | } | |
e771e7c9 | 3716 | else if (i.types[op].bitfield.ymmword) |
c7213af9 L |
3717 | { |
3718 | i.tm.opcode_modifier.evex = EVEX256; | |
3719 | break; | |
3720 | } | |
e771e7c9 | 3721 | else if (i.types[op].bitfield.xmmword) |
c7213af9 L |
3722 | { |
3723 | i.tm.opcode_modifier.evex = EVEX128; | |
3724 | break; | |
3725 | } | |
625cbd7a JB |
3726 | else if (i.broadcast && (int) op == i.broadcast->operand) |
3727 | { | |
4a1b91ea | 3728 | switch (i.broadcast->bytes) |
625cbd7a JB |
3729 | { |
3730 | case 64: | |
3731 | i.tm.opcode_modifier.evex = EVEX512; | |
3732 | break; | |
3733 | case 32: | |
3734 | i.tm.opcode_modifier.evex = EVEX256; | |
3735 | break; | |
3736 | case 16: | |
3737 | i.tm.opcode_modifier.evex = EVEX128; | |
3738 | break; | |
3739 | default: | |
c7213af9 | 3740 | abort (); |
625cbd7a | 3741 | } |
c7213af9 | 3742 | break; |
625cbd7a | 3743 | } |
e771e7c9 | 3744 | } |
c7213af9 | 3745 | |
56522fc5 | 3746 | if (op >= MAX_OPERANDS) |
c7213af9 | 3747 | abort (); |
e771e7c9 JB |
3748 | } |
3749 | ||
43234a1e L |
3750 | switch (i.tm.opcode_modifier.evex) |
3751 | { | |
3752 | case EVEXLIG: /* LL' is ignored */ | |
3753 | vec_length = evexlig << 5; | |
3754 | break; | |
3755 | case EVEX128: | |
3756 | vec_length = 0 << 5; | |
3757 | break; | |
3758 | case EVEX256: | |
3759 | vec_length = 1 << 5; | |
3760 | break; | |
3761 | case EVEX512: | |
3762 | vec_length = 2 << 5; | |
3763 | break; | |
3764 | default: | |
3765 | abort (); | |
3766 | break; | |
3767 | } | |
3768 | i.vex.bytes[3] |= vec_length; | |
3769 | /* Encode the broadcast bit. */ | |
3770 | if (i.broadcast) | |
3771 | i.vex.bytes[3] |= 0x10; | |
3772 | } | |
3773 | else | |
3774 | { | |
3775 | if (i.rounding->type != saeonly) | |
3776 | i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); | |
3777 | else | |
d3d3c6db | 3778 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e L |
3779 | } |
3780 | ||
3781 | if (i.mask && i.mask->mask) | |
3782 | i.vex.bytes[3] |= i.mask->mask->reg_num; | |
3783 | } | |
3784 | ||
65da13b5 L |
3785 | static void |
3786 | process_immext (void) | |
3787 | { | |
3788 | expressionS *exp; | |
3789 | ||
4c692bc7 JB |
3790 | if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme) |
3791 | && i.operands > 0) | |
65da13b5 | 3792 | { |
4c692bc7 JB |
3793 | /* MONITOR/MWAIT as well as SVME instructions have fixed operands |
3794 | with an opcode suffix which is coded in the same place as an | |
3795 | 8-bit immediate field would be. | |
3796 | Here we check those operands and remove them afterwards. */ | |
65da13b5 L |
3797 | unsigned int x; |
3798 | ||
3799 | for (x = 0; x < i.operands; x++) | |
4c692bc7 | 3800 | if (register_number (i.op[x].regs) != x) |
65da13b5 | 3801 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), |
1fed0ba1 L |
3802 | register_prefix, i.op[x].regs->reg_name, x + 1, |
3803 | i.tm.name); | |
3804 | ||
3805 | i.operands = 0; | |
65da13b5 L |
3806 | } |
3807 | ||
9916071f AP |
3808 | if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0) |
3809 | { | |
3810 | /* MONITORX/MWAITX instructions have fixed operands with an opcode | |
3811 | suffix which is coded in the same place as an 8-bit immediate | |
3812 | field would be. | |
3813 | Here we check those operands and remove them afterwards. */ | |
3814 | unsigned int x; | |
3815 | ||
3816 | if (i.operands != 3) | |
3817 | abort(); | |
3818 | ||
3819 | for (x = 0; x < 2; x++) | |
3820 | if (register_number (i.op[x].regs) != x) | |
3821 | goto bad_register_operand; | |
3822 | ||
3823 | /* Check for third operand for mwaitx/monitorx insn. */ | |
3824 | if (register_number (i.op[x].regs) | |
3825 | != (x + (i.tm.extension_opcode == 0xfb))) | |
3826 | { | |
3827 | bad_register_operand: | |
3828 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), | |
3829 | register_prefix, i.op[x].regs->reg_name, x+1, | |
3830 | i.tm.name); | |
3831 | } | |
3832 | ||
3833 | i.operands = 0; | |
3834 | } | |
3835 | ||
c0f3af97 | 3836 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
3837 | which is coded in the same place as an 8-bit immediate field |
3838 | would be. Here we fake an 8-bit immediate operand from the | |
3839 | opcode suffix stored in tm.extension_opcode. | |
3840 | ||
c1e679ec | 3841 | AVX instructions also use this encoding, for some of |
c0f3af97 | 3842 | 3 argument instructions. */ |
65da13b5 | 3843 | |
43234a1e | 3844 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 3845 | && (i.operands <= 2 |
7a8655d2 | 3846 | || (is_any_vex_encoding (&i.tm) |
7ab9ffdd | 3847 | && i.operands <= 4))); |
65da13b5 L |
3848 | |
3849 | exp = &im_expressions[i.imm_operands++]; | |
3850 | i.op[i.operands].imms = exp; | |
3851 | i.types[i.operands] = imm8; | |
3852 | i.operands++; | |
3853 | exp->X_op = O_constant; | |
3854 | exp->X_add_number = i.tm.extension_opcode; | |
3855 | i.tm.extension_opcode = None; | |
3856 | } | |
3857 | ||
42164a71 L |
3858 | |
3859 | static int | |
3860 | check_hle (void) | |
3861 | { | |
3862 | switch (i.tm.opcode_modifier.hleprefixok) | |
3863 | { | |
3864 | default: | |
3865 | abort (); | |
82c2def5 | 3866 | case HLEPrefixNone: |
165de32a L |
3867 | as_bad (_("invalid instruction `%s' after `%s'"), |
3868 | i.tm.name, i.hle_prefix); | |
42164a71 | 3869 | return 0; |
82c2def5 | 3870 | case HLEPrefixLock: |
42164a71 L |
3871 | if (i.prefix[LOCK_PREFIX]) |
3872 | return 1; | |
165de32a | 3873 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 3874 | return 0; |
82c2def5 | 3875 | case HLEPrefixAny: |
42164a71 | 3876 | return 1; |
82c2def5 | 3877 | case HLEPrefixRelease: |
42164a71 L |
3878 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
3879 | { | |
3880 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
3881 | i.tm.name); | |
3882 | return 0; | |
3883 | } | |
3884 | if (i.mem_operands == 0 | |
3885 | || !operand_type_check (i.types[i.operands - 1], anymem)) | |
3886 | { | |
3887 | as_bad (_("memory destination needed for instruction `%s'" | |
3888 | " after `xrelease'"), i.tm.name); | |
3889 | return 0; | |
3890 | } | |
3891 | return 1; | |
3892 | } | |
3893 | } | |
3894 | ||
b6f8c7c4 L |
3895 | /* Try the shortest encoding by shortening operand size. */ |
3896 | ||
3897 | static void | |
3898 | optimize_encoding (void) | |
3899 | { | |
3900 | int j; | |
3901 | ||
3902 | if (optimize_for_space | |
3903 | && i.reg_operands == 1 | |
3904 | && i.imm_operands == 1 | |
3905 | && !i.types[1].bitfield.byte | |
3906 | && i.op[0].imms->X_op == O_constant | |
3907 | && fits_in_imm7 (i.op[0].imms->X_add_number) | |
3908 | && ((i.tm.base_opcode == 0xa8 | |
3909 | && i.tm.extension_opcode == None) | |
3910 | || (i.tm.base_opcode == 0xf6 | |
3911 | && i.tm.extension_opcode == 0x0))) | |
3912 | { | |
3913 | /* Optimize: -Os: | |
3914 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 | |
3915 | */ | |
3916 | unsigned int base_regnum = i.op[1].regs->reg_num; | |
3917 | if (flag_code == CODE_64BIT || base_regnum < 4) | |
3918 | { | |
3919 | i.types[1].bitfield.byte = 1; | |
3920 | /* Ignore the suffix. */ | |
3921 | i.suffix = 0; | |
3922 | if (base_regnum >= 4 | |
3923 | && !(i.op[1].regs->reg_flags & RegRex)) | |
3924 | { | |
3925 | /* Handle SP, BP, SI and DI registers. */ | |
3926 | if (i.types[1].bitfield.word) | |
3927 | j = 16; | |
3928 | else if (i.types[1].bitfield.dword) | |
3929 | j = 32; | |
3930 | else | |
3931 | j = 48; | |
3932 | i.op[1].regs -= j; | |
3933 | } | |
3934 | } | |
3935 | } | |
3936 | else if (flag_code == CODE_64BIT | |
d3d50934 L |
3937 | && ((i.types[1].bitfield.qword |
3938 | && i.reg_operands == 1 | |
b6f8c7c4 L |
3939 | && i.imm_operands == 1 |
3940 | && i.op[0].imms->X_op == O_constant | |
3941 | && ((i.tm.base_opcode == 0xb0 | |
3942 | && i.tm.extension_opcode == None | |
3943 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) | |
3944 | || (fits_in_imm31 (i.op[0].imms->X_add_number) | |
3945 | && (((i.tm.base_opcode == 0x24 | |
3946 | || i.tm.base_opcode == 0xa8) | |
3947 | && i.tm.extension_opcode == None) | |
3948 | || (i.tm.base_opcode == 0x80 | |
3949 | && i.tm.extension_opcode == 0x4) | |
3950 | || ((i.tm.base_opcode == 0xf6 | |
3951 | || i.tm.base_opcode == 0xc6) | |
b8364fa7 JB |
3952 | && i.tm.extension_opcode == 0x0))) |
3953 | || (fits_in_imm7 (i.op[0].imms->X_add_number) | |
3954 | && i.tm.base_opcode == 0x83 | |
3955 | && i.tm.extension_opcode == 0x4))) | |
d3d50934 L |
3956 | || (i.types[0].bitfield.qword |
3957 | && ((i.reg_operands == 2 | |
3958 | && i.op[0].regs == i.op[1].regs | |
3959 | && ((i.tm.base_opcode == 0x30 | |
3960 | || i.tm.base_opcode == 0x28) | |
3961 | && i.tm.extension_opcode == None)) | |
3962 | || (i.reg_operands == 1 | |
3963 | && i.operands == 1 | |
3964 | && i.tm.base_opcode == 0x30 | |
3965 | && i.tm.extension_opcode == None))))) | |
b6f8c7c4 L |
3966 | { |
3967 | /* Optimize: -O: | |
3968 | andq $imm31, %r64 -> andl $imm31, %r32 | |
b8364fa7 | 3969 | andq $imm7, %r64 -> andl $imm7, %r32 |
b6f8c7c4 L |
3970 | testq $imm31, %r64 -> testl $imm31, %r32 |
3971 | xorq %r64, %r64 -> xorl %r32, %r32 | |
3972 | subq %r64, %r64 -> subl %r32, %r32 | |
3973 | movq $imm31, %r64 -> movl $imm31, %r32 | |
3974 | movq $imm32, %r64 -> movl $imm32, %r32 | |
3975 | */ | |
3976 | i.tm.opcode_modifier.norex64 = 1; | |
3977 | if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6) | |
3978 | { | |
3979 | /* Handle | |
3980 | movq $imm31, %r64 -> movl $imm31, %r32 | |
3981 | movq $imm32, %r64 -> movl $imm32, %r32 | |
3982 | */ | |
3983 | i.tm.operand_types[0].bitfield.imm32 = 1; | |
3984 | i.tm.operand_types[0].bitfield.imm32s = 0; | |
3985 | i.tm.operand_types[0].bitfield.imm64 = 0; | |
3986 | i.types[0].bitfield.imm32 = 1; | |
3987 | i.types[0].bitfield.imm32s = 0; | |
3988 | i.types[0].bitfield.imm64 = 0; | |
3989 | i.types[1].bitfield.dword = 1; | |
3990 | i.types[1].bitfield.qword = 0; | |
3991 | if (i.tm.base_opcode == 0xc6) | |
3992 | { | |
3993 | /* Handle | |
3994 | movq $imm31, %r64 -> movl $imm31, %r32 | |
3995 | */ | |
3996 | i.tm.base_opcode = 0xb0; | |
3997 | i.tm.extension_opcode = None; | |
3998 | i.tm.opcode_modifier.shortform = 1; | |
3999 | i.tm.opcode_modifier.modrm = 0; | |
4000 | } | |
4001 | } | |
4002 | } | |
99112332 | 4003 | else if (i.reg_operands == 3 |
b6f8c7c4 L |
4004 | && i.op[0].regs == i.op[1].regs |
4005 | && !i.types[2].bitfield.xmmword | |
4006 | && (i.tm.opcode_modifier.vex | |
7a69eac3 | 4007 | || ((!i.mask || i.mask->zeroing) |
b6f8c7c4 | 4008 | && !i.rounding |
e771e7c9 | 4009 | && is_evex_encoding (&i.tm) |
80c34c38 | 4010 | && (i.vec_encoding != vex_encoding_evex |
dd22218c | 4011 | || cpu_arch_isa_flags.bitfield.cpuavx512vl |
80c34c38 | 4012 | || i.tm.cpu_flags.bitfield.cpuavx512vl |
7091c612 | 4013 | || (i.tm.operand_types[2].bitfield.zmmword |
dd22218c | 4014 | && i.types[2].bitfield.ymmword)))) |
b6f8c7c4 L |
4015 | && ((i.tm.base_opcode == 0x55 |
4016 | || i.tm.base_opcode == 0x6655 | |
4017 | || i.tm.base_opcode == 0x66df | |
4018 | || i.tm.base_opcode == 0x57 | |
4019 | || i.tm.base_opcode == 0x6657 | |
8305403a L |
4020 | || i.tm.base_opcode == 0x66ef |
4021 | || i.tm.base_opcode == 0x66f8 | |
4022 | || i.tm.base_opcode == 0x66f9 | |
4023 | || i.tm.base_opcode == 0x66fa | |
1424ad86 JB |
4024 | || i.tm.base_opcode == 0x66fb |
4025 | || i.tm.base_opcode == 0x42 | |
4026 | || i.tm.base_opcode == 0x6642 | |
4027 | || i.tm.base_opcode == 0x47 | |
4028 | || i.tm.base_opcode == 0x6647) | |
b6f8c7c4 L |
4029 | && i.tm.extension_opcode == None)) |
4030 | { | |
99112332 | 4031 | /* Optimize: -O1: |
8305403a L |
4032 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
4033 | vpsubq and vpsubw: | |
b6f8c7c4 L |
4034 | EVEX VOP %zmmM, %zmmM, %zmmN |
4035 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4036 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4037 | EVEX VOP %ymmM, %ymmM, %ymmN |
4038 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4039 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4040 | VEX VOP %ymmM, %ymmM, %ymmN |
4041 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4042 | VOP, one of vpandn and vpxor: | |
4043 | VEX VOP %ymmM, %ymmM, %ymmN | |
4044 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4045 | VOP, one of vpandnd and vpandnq: | |
4046 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4047 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4048 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4049 | EVEX VOP %ymmM, %ymmM, %ymmN |
4050 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4051 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4052 | VOP, one of vpxord and vpxorq: |
4053 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4054 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4055 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4056 | EVEX VOP %ymmM, %ymmM, %ymmN |
4057 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4058 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
1424ad86 JB |
4059 | VOP, one of kxord and kxorq: |
4060 | VEX VOP %kM, %kM, %kN | |
4061 | -> VEX kxorw %kM, %kM, %kN | |
4062 | VOP, one of kandnd and kandnq: | |
4063 | VEX VOP %kM, %kM, %kN | |
4064 | -> VEX kandnw %kM, %kM, %kN | |
b6f8c7c4 | 4065 | */ |
e771e7c9 | 4066 | if (is_evex_encoding (&i.tm)) |
b6f8c7c4 | 4067 | { |
7b1d7ca1 | 4068 | if (i.vec_encoding != vex_encoding_evex) |
b6f8c7c4 L |
4069 | { |
4070 | i.tm.opcode_modifier.vex = VEX128; | |
4071 | i.tm.opcode_modifier.vexw = VEXW0; | |
4072 | i.tm.opcode_modifier.evex = 0; | |
4073 | } | |
7b1d7ca1 | 4074 | else if (optimize > 1) |
dd22218c L |
4075 | i.tm.opcode_modifier.evex = EVEX128; |
4076 | else | |
4077 | return; | |
b6f8c7c4 | 4078 | } |
1424ad86 JB |
4079 | else if (i.tm.operand_types[0].bitfield.regmask) |
4080 | { | |
4081 | i.tm.base_opcode &= 0xff; | |
4082 | i.tm.opcode_modifier.vexw = VEXW0; | |
4083 | } | |
b6f8c7c4 L |
4084 | else |
4085 | i.tm.opcode_modifier.vex = VEX128; | |
4086 | ||
4087 | if (i.tm.opcode_modifier.vex) | |
4088 | for (j = 0; j < 3; j++) | |
4089 | { | |
4090 | i.types[j].bitfield.xmmword = 1; | |
4091 | i.types[j].bitfield.ymmword = 0; | |
4092 | } | |
4093 | } | |
392a5972 | 4094 | else if (i.vec_encoding != vex_encoding_evex |
97ed31ae | 4095 | && !i.types[0].bitfield.zmmword |
392a5972 | 4096 | && !i.types[1].bitfield.zmmword |
97ed31ae L |
4097 | && !i.mask |
4098 | && is_evex_encoding (&i.tm) | |
392a5972 L |
4099 | && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x666f |
4100 | || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf36f | |
4101 | || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f) | |
97ed31ae L |
4102 | && i.tm.extension_opcode == None) |
4103 | { | |
4104 | /* Optimize: -O1: | |
4105 | VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, | |
4106 | vmovdqu32 and vmovdqu64: | |
4107 | EVEX VOP %xmmM, %xmmN | |
4108 | -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16) | |
4109 | EVEX VOP %ymmM, %ymmN | |
4110 | -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16) | |
4111 | EVEX VOP %xmmM, mem | |
4112 | -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16) | |
4113 | EVEX VOP %ymmM, mem | |
4114 | -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16) | |
4115 | EVEX VOP mem, %xmmN | |
4116 | -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16) | |
4117 | EVEX VOP mem, %ymmN | |
4118 | -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16) | |
4119 | */ | |
392a5972 L |
4120 | for (j = 0; j < 2; j++) |
4121 | if (operand_type_check (i.types[j], disp) | |
4122 | && i.op[j].disps->X_op == O_constant) | |
4123 | { | |
4124 | /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix | |
4125 | has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4 | |
4126 | bytes, we choose EVEX Disp8 over VEX Disp32. */ | |
4127 | int evex_disp8, vex_disp8; | |
4128 | unsigned int memshift = i.memshift; | |
4129 | offsetT n = i.op[j].disps->X_add_number; | |
4130 | ||
4131 | evex_disp8 = fits_in_disp8 (n); | |
4132 | i.memshift = 0; | |
4133 | vex_disp8 = fits_in_disp8 (n); | |
4134 | if (evex_disp8 != vex_disp8) | |
4135 | { | |
4136 | i.memshift = memshift; | |
4137 | return; | |
4138 | } | |
4139 | ||
4140 | i.types[j].bitfield.disp8 = vex_disp8; | |
4141 | break; | |
4142 | } | |
4143 | if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f) | |
4144 | i.tm.base_opcode ^= 0xf36f ^ 0xf26f; | |
97ed31ae L |
4145 | i.tm.opcode_modifier.vex |
4146 | = i.types[0].bitfield.ymmword ? VEX256 : VEX128; | |
4147 | i.tm.opcode_modifier.vexw = VEXW0; | |
4148 | i.tm.opcode_modifier.evex = 0; | |
4149 | i.tm.opcode_modifier.masking = 0; | |
4150 | i.tm.opcode_modifier.disp8memshift = 0; | |
4151 | i.memshift = 0; | |
4152 | for (j = 0; j < 2; j++) | |
4153 | if (operand_type_check (i.types[j], disp) | |
4154 | && i.op[j].disps->X_op == O_constant) | |
4155 | { | |
4156 | i.types[j].bitfield.disp8 | |
4157 | = fits_in_disp8 (i.op[j].disps->X_add_number); | |
4158 | break; | |
4159 | } | |
4160 | } | |
b6f8c7c4 L |
4161 | } |
4162 | ||
252b5132 RH |
4163 | /* This is the guts of the machine-dependent assembler. LINE points to a |
4164 | machine dependent instruction. This function is supposed to emit | |
4165 | the frags/bytes it assembles to. */ | |
4166 | ||
4167 | void | |
65da13b5 | 4168 | md_assemble (char *line) |
252b5132 | 4169 | { |
40fb9820 | 4170 | unsigned int j; |
83b16ac6 | 4171 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
d3ce72d0 | 4172 | const insn_template *t; |
252b5132 | 4173 | |
47926f60 | 4174 | /* Initialize globals. */ |
252b5132 RH |
4175 | memset (&i, '\0', sizeof (i)); |
4176 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 4177 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
4178 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
4179 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 4180 | save_stack_p = save_stack; |
252b5132 RH |
4181 | |
4182 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
4183 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 4184 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 4185 | |
29b0f896 AM |
4186 | line = parse_insn (line, mnemonic); |
4187 | if (line == NULL) | |
4188 | return; | |
83b16ac6 | 4189 | mnem_suffix = i.suffix; |
252b5132 | 4190 | |
29b0f896 | 4191 | line = parse_operands (line, mnemonic); |
ee86248c | 4192 | this_operand = -1; |
8325cc63 JB |
4193 | xfree (i.memop1_string); |
4194 | i.memop1_string = NULL; | |
29b0f896 AM |
4195 | if (line == NULL) |
4196 | return; | |
252b5132 | 4197 | |
29b0f896 AM |
4198 | /* Now we've parsed the mnemonic into a set of templates, and have the |
4199 | operands at hand. */ | |
4200 | ||
4201 | /* All intel opcodes have reversed operands except for "bound" and | |
4202 | "enter". We also don't reverse intersegment "jmp" and "call" | |
4203 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 4204 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
4205 | if (intel_syntax |
4206 | && i.operands > 1 | |
29b0f896 | 4207 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 4208 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
4209 | && !(operand_type_check (i.types[0], imm) |
4210 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
4211 | swap_operands (); |
4212 | ||
ec56d5c0 JB |
4213 | /* The order of the immediates should be reversed |
4214 | for 2 immediates extrq and insertq instructions */ | |
4215 | if (i.imm_operands == 2 | |
4216 | && (strcmp (mnemonic, "extrq") == 0 | |
4217 | || strcmp (mnemonic, "insertq") == 0)) | |
4218 | swap_2_operands (0, 1); | |
4219 | ||
29b0f896 AM |
4220 | if (i.imm_operands) |
4221 | optimize_imm (); | |
4222 | ||
b300c311 L |
4223 | /* Don't optimize displacement for movabs since it only takes 64bit |
4224 | displacement. */ | |
4225 | if (i.disp_operands | |
a501d77e | 4226 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
4227 | && (flag_code != CODE_64BIT |
4228 | || strcmp (mnemonic, "movabs") != 0)) | |
4229 | optimize_disp (); | |
29b0f896 AM |
4230 | |
4231 | /* Next, we find a template that matches the given insn, | |
4232 | making sure the overlap of the given operands types is consistent | |
4233 | with the template operand types. */ | |
252b5132 | 4234 | |
83b16ac6 | 4235 | if (!(t = match_template (mnem_suffix))) |
29b0f896 | 4236 | return; |
252b5132 | 4237 | |
7bab8ab5 | 4238 | if (sse_check != check_none |
81f8a913 | 4239 | && !i.tm.opcode_modifier.noavx |
6e3e5c9e | 4240 | && !i.tm.cpu_flags.bitfield.cpuavx |
daf50ae7 L |
4241 | && (i.tm.cpu_flags.bitfield.cpusse |
4242 | || i.tm.cpu_flags.bitfield.cpusse2 | |
4243 | || i.tm.cpu_flags.bitfield.cpusse3 | |
4244 | || i.tm.cpu_flags.bitfield.cpussse3 | |
4245 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
6e3e5c9e JB |
4246 | || i.tm.cpu_flags.bitfield.cpusse4_2 |
4247 | || i.tm.cpu_flags.bitfield.cpupclmul | |
4248 | || i.tm.cpu_flags.bitfield.cpuaes | |
4249 | || i.tm.cpu_flags.bitfield.cpugfni)) | |
daf50ae7 | 4250 | { |
7bab8ab5 | 4251 | (sse_check == check_warning |
daf50ae7 L |
4252 | ? as_warn |
4253 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
4254 | } | |
4255 | ||
321fd21e L |
4256 | /* Zap movzx and movsx suffix. The suffix has been set from |
4257 | "word ptr" or "byte ptr" on the source operand in Intel syntax | |
4258 | or extracted from mnemonic in AT&T syntax. But we'll use | |
4259 | the destination register to choose the suffix for encoding. */ | |
4260 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
cd61ebfe | 4261 | { |
321fd21e L |
4262 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
4263 | there is no suffix, the default will be byte extension. */ | |
4264 | if (i.reg_operands != 2 | |
4265 | && !i.suffix | |
7ab9ffdd | 4266 | && intel_syntax) |
321fd21e L |
4267 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
4268 | ||
4269 | i.suffix = 0; | |
cd61ebfe | 4270 | } |
24eab124 | 4271 | |
40fb9820 | 4272 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
4273 | if (!add_prefix (FWAIT_OPCODE)) |
4274 | return; | |
252b5132 | 4275 | |
d5de92cf L |
4276 | /* Check if REP prefix is OK. */ |
4277 | if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) | |
4278 | { | |
4279 | as_bad (_("invalid instruction `%s' after `%s'"), | |
4280 | i.tm.name, i.rep_prefix); | |
4281 | return; | |
4282 | } | |
4283 | ||
c1ba0266 L |
4284 | /* Check for lock without a lockable instruction. Destination operand |
4285 | must be memory unless it is xchg (0x86). */ | |
c32fa91d L |
4286 | if (i.prefix[LOCK_PREFIX] |
4287 | && (!i.tm.opcode_modifier.islockable | |
c1ba0266 L |
4288 | || i.mem_operands == 0 |
4289 | || (i.tm.base_opcode != 0x86 | |
4290 | && !operand_type_check (i.types[i.operands - 1], anymem)))) | |
c32fa91d L |
4291 | { |
4292 | as_bad (_("expecting lockable instruction after `lock'")); | |
4293 | return; | |
4294 | } | |
4295 | ||
7a8655d2 JB |
4296 | /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */ |
4297 | if (i.prefix[DATA_PREFIX] && is_any_vex_encoding (&i.tm)) | |
4298 | { | |
4299 | as_bad (_("data size prefix invalid with `%s'"), i.tm.name); | |
4300 | return; | |
4301 | } | |
4302 | ||
42164a71 | 4303 | /* Check if HLE prefix is OK. */ |
165de32a | 4304 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
4305 | return; |
4306 | ||
7e8b059b L |
4307 | /* Check BND prefix. */ |
4308 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
4309 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
4310 | ||
04ef582a | 4311 | /* Check NOTRACK prefix. */ |
9fef80d6 L |
4312 | if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok) |
4313 | as_bad (_("expecting indirect branch instruction after `notrack'")); | |
04ef582a | 4314 | |
327e8c42 JB |
4315 | if (i.tm.cpu_flags.bitfield.cpumpx) |
4316 | { | |
4317 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
4318 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
4319 | else if (flag_code != CODE_16BIT | |
4320 | ? i.prefix[ADDR_PREFIX] | |
4321 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
4322 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
4323 | } | |
7e8b059b L |
4324 | |
4325 | /* Insert BND prefix. */ | |
76d3a78a JB |
4326 | if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok) |
4327 | { | |
4328 | if (!i.prefix[BND_PREFIX]) | |
4329 | add_prefix (BND_PREFIX_OPCODE); | |
4330 | else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE) | |
4331 | { | |
4332 | as_warn (_("replacing `rep'/`repe' prefix by `bnd'")); | |
4333 | i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE; | |
4334 | } | |
4335 | } | |
7e8b059b | 4336 | |
29b0f896 | 4337 | /* Check string instruction segment overrides. */ |
40fb9820 | 4338 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
29b0f896 AM |
4339 | { |
4340 | if (!check_string ()) | |
5dd0794d | 4341 | return; |
fc0763e6 | 4342 | i.disp_operands = 0; |
29b0f896 | 4343 | } |
5dd0794d | 4344 | |
b6f8c7c4 L |
4345 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
4346 | optimize_encoding (); | |
4347 | ||
29b0f896 AM |
4348 | if (!process_suffix ()) |
4349 | return; | |
e413e4e9 | 4350 | |
bc0844ae L |
4351 | /* Update operand types. */ |
4352 | for (j = 0; j < i.operands; j++) | |
4353 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
4354 | ||
29b0f896 AM |
4355 | /* Make still unresolved immediate matches conform to size of immediate |
4356 | given in i.suffix. */ | |
4357 | if (!finalize_imm ()) | |
4358 | return; | |
252b5132 | 4359 | |
40fb9820 | 4360 | if (i.types[0].bitfield.imm1) |
29b0f896 | 4361 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 4362 | |
9afe6eb8 L |
4363 | /* We only need to check those implicit registers for instructions |
4364 | with 3 operands or less. */ | |
4365 | if (i.operands <= 3) | |
4366 | for (j = 0; j < i.operands; j++) | |
4367 | if (i.types[j].bitfield.inoutportreg | |
4368 | || i.types[j].bitfield.shiftcount | |
1b54b8d7 | 4369 | || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword)) |
9afe6eb8 | 4370 | i.reg_operands--; |
40fb9820 | 4371 | |
c0f3af97 L |
4372 | /* ImmExt should be processed after SSE2AVX. */ |
4373 | if (!i.tm.opcode_modifier.sse2avx | |
4374 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 4375 | process_immext (); |
252b5132 | 4376 | |
29b0f896 AM |
4377 | /* For insns with operands there are more diddles to do to the opcode. */ |
4378 | if (i.operands) | |
4379 | { | |
4380 | if (!process_operands ()) | |
4381 | return; | |
4382 | } | |
40fb9820 | 4383 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
4384 | { |
4385 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
4386 | as_warn (_("translating to `%sp'"), i.tm.name); | |
4387 | } | |
252b5132 | 4388 | |
7a8655d2 | 4389 | if (is_any_vex_encoding (&i.tm)) |
9e5e5283 | 4390 | { |
c1dc7af5 | 4391 | if (!cpu_arch_flags.bitfield.cpui286) |
9e5e5283 | 4392 | { |
c1dc7af5 | 4393 | as_bad (_("instruction `%s' isn't supported outside of protected mode."), |
9e5e5283 L |
4394 | i.tm.name); |
4395 | return; | |
4396 | } | |
c0f3af97 | 4397 | |
9e5e5283 L |
4398 | if (i.tm.opcode_modifier.vex) |
4399 | build_vex_prefix (t); | |
4400 | else | |
4401 | build_evex_prefix (); | |
4402 | } | |
43234a1e | 4403 | |
5dd85c99 SP |
4404 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
4405 | instructions may define INT_OPCODE as well, so avoid this corner | |
4406 | case for those instructions that use MODRM. */ | |
4407 | if (i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
4408 | && !i.tm.opcode_modifier.modrm |
4409 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
4410 | { |
4411 | i.tm.base_opcode = INT3_OPCODE; | |
4412 | i.imm_operands = 0; | |
4413 | } | |
252b5132 | 4414 | |
40fb9820 L |
4415 | if ((i.tm.opcode_modifier.jump |
4416 | || i.tm.opcode_modifier.jumpbyte | |
4417 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 AM |
4418 | && i.op[0].disps->X_op == O_constant) |
4419 | { | |
4420 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
4421 | the absolute address given by the constant. Since ix86 jumps and | |
4422 | calls are pc relative, we need to generate a reloc. */ | |
4423 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
4424 | i.op[0].disps->X_op = O_symbol; | |
4425 | } | |
252b5132 | 4426 | |
40fb9820 | 4427 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 4428 | i.rex |= REX_W; |
252b5132 | 4429 | |
29b0f896 AM |
4430 | /* For 8 bit registers we need an empty rex prefix. Also if the |
4431 | instruction already has a prefix, we need to convert old | |
4432 | registers to new ones. */ | |
773f551c | 4433 | |
dc821c5f | 4434 | if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte |
29b0f896 | 4435 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
dc821c5f | 4436 | || (i.types[1].bitfield.reg && i.types[1].bitfield.byte |
29b0f896 | 4437 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
dc821c5f JB |
4438 | || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte) |
4439 | || (i.types[1].bitfield.reg && i.types[1].bitfield.byte)) | |
29b0f896 AM |
4440 | && i.rex != 0)) |
4441 | { | |
4442 | int x; | |
726c5dcd | 4443 | |
29b0f896 AM |
4444 | i.rex |= REX_OPCODE; |
4445 | for (x = 0; x < 2; x++) | |
4446 | { | |
4447 | /* Look for 8 bit operand that uses old registers. */ | |
dc821c5f | 4448 | if (i.types[x].bitfield.reg && i.types[x].bitfield.byte |
29b0f896 | 4449 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 4450 | { |
29b0f896 AM |
4451 | /* In case it is "hi" register, give up. */ |
4452 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 4453 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 4454 | "instruction requiring REX prefix."), |
a540244d | 4455 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 4456 | |
29b0f896 AM |
4457 | /* Otherwise it is equivalent to the extended register. |
4458 | Since the encoding doesn't change this is merely | |
4459 | cosmetic cleanup for debug output. */ | |
4460 | ||
4461 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 4462 | } |
29b0f896 AM |
4463 | } |
4464 | } | |
773f551c | 4465 | |
6b6b6807 L |
4466 | if (i.rex == 0 && i.rex_encoding) |
4467 | { | |
4468 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
4469 | that uses legacy register. If it is "hi" register, don't add | |
4470 | the REX_OPCODE byte. */ | |
4471 | int x; | |
4472 | for (x = 0; x < 2; x++) | |
4473 | if (i.types[x].bitfield.reg | |
4474 | && i.types[x].bitfield.byte | |
4475 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
4476 | && i.op[x].regs->reg_num > 3) | |
4477 | { | |
4478 | i.rex_encoding = FALSE; | |
4479 | break; | |
4480 | } | |
4481 | ||
4482 | if (i.rex_encoding) | |
4483 | i.rex = REX_OPCODE; | |
4484 | } | |
4485 | ||
7ab9ffdd | 4486 | if (i.rex != 0) |
29b0f896 AM |
4487 | add_prefix (REX_OPCODE | i.rex); |
4488 | ||
4489 | /* We are ready to output the insn. */ | |
4490 | output_insn (); | |
4491 | } | |
4492 | ||
4493 | static char * | |
e3bb37b5 | 4494 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
4495 | { |
4496 | char *l = line; | |
4497 | char *token_start = l; | |
4498 | char *mnem_p; | |
5c6af06e | 4499 | int supported; |
d3ce72d0 | 4500 | const insn_template *t; |
b6169b20 | 4501 | char *dot_p = NULL; |
29b0f896 | 4502 | |
29b0f896 AM |
4503 | while (1) |
4504 | { | |
4505 | mnem_p = mnemonic; | |
4506 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
4507 | { | |
b6169b20 L |
4508 | if (*mnem_p == '.') |
4509 | dot_p = mnem_p; | |
29b0f896 AM |
4510 | mnem_p++; |
4511 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 4512 | { |
29b0f896 AM |
4513 | as_bad (_("no such instruction: `%s'"), token_start); |
4514 | return NULL; | |
4515 | } | |
4516 | l++; | |
4517 | } | |
4518 | if (!is_space_char (*l) | |
4519 | && *l != END_OF_INSN | |
e44823cf JB |
4520 | && (intel_syntax |
4521 | || (*l != PREFIX_SEPARATOR | |
4522 | && *l != ','))) | |
29b0f896 AM |
4523 | { |
4524 | as_bad (_("invalid character %s in mnemonic"), | |
4525 | output_invalid (*l)); | |
4526 | return NULL; | |
4527 | } | |
4528 | if (token_start == l) | |
4529 | { | |
e44823cf | 4530 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
4531 | as_bad (_("expecting prefix; got nothing")); |
4532 | else | |
4533 | as_bad (_("expecting mnemonic; got nothing")); | |
4534 | return NULL; | |
4535 | } | |
45288df1 | 4536 | |
29b0f896 | 4537 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 4538 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 4539 | |
29b0f896 AM |
4540 | if (*l != END_OF_INSN |
4541 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
4542 | && current_templates | |
40fb9820 | 4543 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 4544 | { |
c6fb90c8 | 4545 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
4546 | { |
4547 | as_bad ((flag_code != CODE_64BIT | |
4548 | ? _("`%s' is only supported in 64-bit mode") | |
4549 | : _("`%s' is not supported in 64-bit mode")), | |
4550 | current_templates->start->name); | |
4551 | return NULL; | |
4552 | } | |
29b0f896 AM |
4553 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
4554 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
673fe0f0 JB |
4555 | if ((current_templates->start->opcode_modifier.size == SIZE16 |
4556 | || current_templates->start->opcode_modifier.size == SIZE32) | |
29b0f896 | 4557 | && flag_code != CODE_64BIT |
673fe0f0 | 4558 | && ((current_templates->start->opcode_modifier.size == SIZE32) |
29b0f896 AM |
4559 | ^ (flag_code == CODE_16BIT))) |
4560 | { | |
4561 | as_bad (_("redundant %s prefix"), | |
4562 | current_templates->start->name); | |
4563 | return NULL; | |
45288df1 | 4564 | } |
86fa6981 | 4565 | if (current_templates->start->opcode_length == 0) |
29b0f896 | 4566 | { |
86fa6981 L |
4567 | /* Handle pseudo prefixes. */ |
4568 | switch (current_templates->start->base_opcode) | |
4569 | { | |
4570 | case 0x0: | |
4571 | /* {disp8} */ | |
4572 | i.disp_encoding = disp_encoding_8bit; | |
4573 | break; | |
4574 | case 0x1: | |
4575 | /* {disp32} */ | |
4576 | i.disp_encoding = disp_encoding_32bit; | |
4577 | break; | |
4578 | case 0x2: | |
4579 | /* {load} */ | |
4580 | i.dir_encoding = dir_encoding_load; | |
4581 | break; | |
4582 | case 0x3: | |
4583 | /* {store} */ | |
4584 | i.dir_encoding = dir_encoding_store; | |
4585 | break; | |
4586 | case 0x4: | |
4587 | /* {vex2} */ | |
4588 | i.vec_encoding = vex_encoding_vex2; | |
4589 | break; | |
4590 | case 0x5: | |
4591 | /* {vex3} */ | |
4592 | i.vec_encoding = vex_encoding_vex3; | |
4593 | break; | |
4594 | case 0x6: | |
4595 | /* {evex} */ | |
4596 | i.vec_encoding = vex_encoding_evex; | |
4597 | break; | |
6b6b6807 L |
4598 | case 0x7: |
4599 | /* {rex} */ | |
4600 | i.rex_encoding = TRUE; | |
4601 | break; | |
b6f8c7c4 L |
4602 | case 0x8: |
4603 | /* {nooptimize} */ | |
4604 | i.no_optimize = TRUE; | |
4605 | break; | |
86fa6981 L |
4606 | default: |
4607 | abort (); | |
4608 | } | |
4609 | } | |
4610 | else | |
4611 | { | |
4612 | /* Add prefix, checking for repeated prefixes. */ | |
4e9ac44a | 4613 | switch (add_prefix (current_templates->start->base_opcode)) |
86fa6981 | 4614 | { |
4e9ac44a L |
4615 | case PREFIX_EXIST: |
4616 | return NULL; | |
4617 | case PREFIX_DS: | |
d777820b | 4618 | if (current_templates->start->cpu_flags.bitfield.cpuibt) |
4e9ac44a L |
4619 | i.notrack_prefix = current_templates->start->name; |
4620 | break; | |
4621 | case PREFIX_REP: | |
4622 | if (current_templates->start->cpu_flags.bitfield.cpuhle) | |
4623 | i.hle_prefix = current_templates->start->name; | |
4624 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) | |
4625 | i.bnd_prefix = current_templates->start->name; | |
4626 | else | |
4627 | i.rep_prefix = current_templates->start->name; | |
4628 | break; | |
4629 | default: | |
4630 | break; | |
86fa6981 | 4631 | } |
29b0f896 AM |
4632 | } |
4633 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
4634 | token_start = ++l; | |
4635 | } | |
4636 | else | |
4637 | break; | |
4638 | } | |
45288df1 | 4639 | |
30a55f88 | 4640 | if (!current_templates) |
b6169b20 | 4641 | { |
07d5e953 JB |
4642 | /* Deprecated functionality (new code should use pseudo-prefixes instead): |
4643 | Check if we should swap operand or force 32bit displacement in | |
f8a5c266 | 4644 | encoding. */ |
30a55f88 | 4645 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
64c49ab3 | 4646 | i.dir_encoding = dir_encoding_swap; |
8d63c93e | 4647 | else if (mnem_p - 3 == dot_p |
a501d77e L |
4648 | && dot_p[1] == 'd' |
4649 | && dot_p[2] == '8') | |
4650 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 4651 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
4652 | && dot_p[1] == 'd' |
4653 | && dot_p[2] == '3' | |
4654 | && dot_p[3] == '2') | |
a501d77e | 4655 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
4656 | else |
4657 | goto check_suffix; | |
4658 | mnem_p = dot_p; | |
4659 | *dot_p = '\0'; | |
d3ce72d0 | 4660 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
4661 | } |
4662 | ||
29b0f896 AM |
4663 | if (!current_templates) |
4664 | { | |
b6169b20 | 4665 | check_suffix: |
1c529385 | 4666 | if (mnem_p > mnemonic) |
29b0f896 | 4667 | { |
1c529385 LH |
4668 | /* See if we can get a match by trimming off a suffix. */ |
4669 | switch (mnem_p[-1]) | |
29b0f896 | 4670 | { |
1c529385 LH |
4671 | case WORD_MNEM_SUFFIX: |
4672 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) | |
29b0f896 AM |
4673 | i.suffix = SHORT_MNEM_SUFFIX; |
4674 | else | |
1c529385 LH |
4675 | /* Fall through. */ |
4676 | case BYTE_MNEM_SUFFIX: | |
4677 | case QWORD_MNEM_SUFFIX: | |
4678 | i.suffix = mnem_p[-1]; | |
29b0f896 | 4679 | mnem_p[-1] = '\0'; |
d3ce72d0 | 4680 | current_templates = (const templates *) hash_find (op_hash, |
1c529385 LH |
4681 | mnemonic); |
4682 | break; | |
4683 | case SHORT_MNEM_SUFFIX: | |
4684 | case LONG_MNEM_SUFFIX: | |
4685 | if (!intel_syntax) | |
4686 | { | |
4687 | i.suffix = mnem_p[-1]; | |
4688 | mnem_p[-1] = '\0'; | |
4689 | current_templates = (const templates *) hash_find (op_hash, | |
4690 | mnemonic); | |
4691 | } | |
4692 | break; | |
4693 | ||
4694 | /* Intel Syntax. */ | |
4695 | case 'd': | |
4696 | if (intel_syntax) | |
4697 | { | |
4698 | if (intel_float_operand (mnemonic) == 1) | |
4699 | i.suffix = SHORT_MNEM_SUFFIX; | |
4700 | else | |
4701 | i.suffix = LONG_MNEM_SUFFIX; | |
4702 | mnem_p[-1] = '\0'; | |
4703 | current_templates = (const templates *) hash_find (op_hash, | |
4704 | mnemonic); | |
4705 | } | |
4706 | break; | |
29b0f896 | 4707 | } |
29b0f896 | 4708 | } |
1c529385 | 4709 | |
29b0f896 AM |
4710 | if (!current_templates) |
4711 | { | |
4712 | as_bad (_("no such instruction: `%s'"), token_start); | |
4713 | return NULL; | |
4714 | } | |
4715 | } | |
252b5132 | 4716 | |
40fb9820 L |
4717 | if (current_templates->start->opcode_modifier.jump |
4718 | || current_templates->start->opcode_modifier.jumpbyte) | |
29b0f896 AM |
4719 | { |
4720 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
4721 | predict taken and predict not taken respectively. | |
4722 | I'm not sure that branch hints actually do anything on loop | |
4723 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
4724 | may work in the future and it doesn't hurt to accept them | |
4725 | now. */ | |
4726 | if (l[0] == ',' && l[1] == 'p') | |
4727 | { | |
4728 | if (l[2] == 't') | |
4729 | { | |
4730 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
4731 | return NULL; | |
4732 | l += 3; | |
4733 | } | |
4734 | else if (l[2] == 'n') | |
4735 | { | |
4736 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
4737 | return NULL; | |
4738 | l += 3; | |
4739 | } | |
4740 | } | |
4741 | } | |
4742 | /* Any other comma loses. */ | |
4743 | if (*l == ',') | |
4744 | { | |
4745 | as_bad (_("invalid character %s in mnemonic"), | |
4746 | output_invalid (*l)); | |
4747 | return NULL; | |
4748 | } | |
252b5132 | 4749 | |
29b0f896 | 4750 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
4751 | supported = 0; |
4752 | for (t = current_templates->start; t < current_templates->end; ++t) | |
4753 | { | |
c0f3af97 L |
4754 | supported |= cpu_flags_match (t); |
4755 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
548d0ee6 JB |
4756 | { |
4757 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT)) | |
4758 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
3629bb00 | 4759 | |
548d0ee6 JB |
4760 | return l; |
4761 | } | |
29b0f896 | 4762 | } |
3629bb00 | 4763 | |
548d0ee6 JB |
4764 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
4765 | as_bad (flag_code == CODE_64BIT | |
4766 | ? _("`%s' is not supported in 64-bit mode") | |
4767 | : _("`%s' is only supported in 64-bit mode"), | |
4768 | current_templates->start->name); | |
4769 | else | |
4770 | as_bad (_("`%s' is not supported on `%s%s'"), | |
4771 | current_templates->start->name, | |
4772 | cpu_arch_name ? cpu_arch_name : default_arch, | |
4773 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
252b5132 | 4774 | |
548d0ee6 | 4775 | return NULL; |
29b0f896 | 4776 | } |
252b5132 | 4777 | |
29b0f896 | 4778 | static char * |
e3bb37b5 | 4779 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
4780 | { |
4781 | char *token_start; | |
3138f287 | 4782 | |
29b0f896 AM |
4783 | /* 1 if operand is pending after ','. */ |
4784 | unsigned int expecting_operand = 0; | |
252b5132 | 4785 | |
29b0f896 AM |
4786 | /* Non-zero if operand parens not balanced. */ |
4787 | unsigned int paren_not_balanced; | |
4788 | ||
4789 | while (*l != END_OF_INSN) | |
4790 | { | |
4791 | /* Skip optional white space before operand. */ | |
4792 | if (is_space_char (*l)) | |
4793 | ++l; | |
d02603dc | 4794 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
4795 | { |
4796 | as_bad (_("invalid character %s before operand %d"), | |
4797 | output_invalid (*l), | |
4798 | i.operands + 1); | |
4799 | return NULL; | |
4800 | } | |
d02603dc | 4801 | token_start = l; /* After white space. */ |
29b0f896 AM |
4802 | paren_not_balanced = 0; |
4803 | while (paren_not_balanced || *l != ',') | |
4804 | { | |
4805 | if (*l == END_OF_INSN) | |
4806 | { | |
4807 | if (paren_not_balanced) | |
4808 | { | |
4809 | if (!intel_syntax) | |
4810 | as_bad (_("unbalanced parenthesis in operand %d."), | |
4811 | i.operands + 1); | |
4812 | else | |
4813 | as_bad (_("unbalanced brackets in operand %d."), | |
4814 | i.operands + 1); | |
4815 | return NULL; | |
4816 | } | |
4817 | else | |
4818 | break; /* we are done */ | |
4819 | } | |
d02603dc | 4820 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
29b0f896 AM |
4821 | { |
4822 | as_bad (_("invalid character %s in operand %d"), | |
4823 | output_invalid (*l), | |
4824 | i.operands + 1); | |
4825 | return NULL; | |
4826 | } | |
4827 | if (!intel_syntax) | |
4828 | { | |
4829 | if (*l == '(') | |
4830 | ++paren_not_balanced; | |
4831 | if (*l == ')') | |
4832 | --paren_not_balanced; | |
4833 | } | |
4834 | else | |
4835 | { | |
4836 | if (*l == '[') | |
4837 | ++paren_not_balanced; | |
4838 | if (*l == ']') | |
4839 | --paren_not_balanced; | |
4840 | } | |
4841 | l++; | |
4842 | } | |
4843 | if (l != token_start) | |
4844 | { /* Yes, we've read in another operand. */ | |
4845 | unsigned int operand_ok; | |
4846 | this_operand = i.operands++; | |
4847 | if (i.operands > MAX_OPERANDS) | |
4848 | { | |
4849 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
4850 | MAX_OPERANDS); | |
4851 | return NULL; | |
4852 | } | |
9d46ce34 | 4853 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
4854 | /* Now parse operand adding info to 'i' as we go along. */ |
4855 | END_STRING_AND_SAVE (l); | |
4856 | ||
1286ab78 L |
4857 | if (i.mem_operands > 1) |
4858 | { | |
4859 | as_bad (_("too many memory references for `%s'"), | |
4860 | mnemonic); | |
4861 | return 0; | |
4862 | } | |
4863 | ||
29b0f896 AM |
4864 | if (intel_syntax) |
4865 | operand_ok = | |
4866 | i386_intel_operand (token_start, | |
4867 | intel_float_operand (mnemonic)); | |
4868 | else | |
a7619375 | 4869 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
4870 | |
4871 | RESTORE_END_STRING (l); | |
4872 | if (!operand_ok) | |
4873 | return NULL; | |
4874 | } | |
4875 | else | |
4876 | { | |
4877 | if (expecting_operand) | |
4878 | { | |
4879 | expecting_operand_after_comma: | |
4880 | as_bad (_("expecting operand after ','; got nothing")); | |
4881 | return NULL; | |
4882 | } | |
4883 | if (*l == ',') | |
4884 | { | |
4885 | as_bad (_("expecting operand before ','; got nothing")); | |
4886 | return NULL; | |
4887 | } | |
4888 | } | |
7f3f1ea2 | 4889 | |
29b0f896 AM |
4890 | /* Now *l must be either ',' or END_OF_INSN. */ |
4891 | if (*l == ',') | |
4892 | { | |
4893 | if (*++l == END_OF_INSN) | |
4894 | { | |
4895 | /* Just skip it, if it's \n complain. */ | |
4896 | goto expecting_operand_after_comma; | |
4897 | } | |
4898 | expecting_operand = 1; | |
4899 | } | |
4900 | } | |
4901 | return l; | |
4902 | } | |
7f3f1ea2 | 4903 | |
050dfa73 | 4904 | static void |
4d456e3d | 4905 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
4906 | { |
4907 | union i386_op temp_op; | |
40fb9820 | 4908 | i386_operand_type temp_type; |
c48dadc9 | 4909 | unsigned int temp_flags; |
050dfa73 | 4910 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 4911 | |
050dfa73 MM |
4912 | temp_type = i.types[xchg2]; |
4913 | i.types[xchg2] = i.types[xchg1]; | |
4914 | i.types[xchg1] = temp_type; | |
c48dadc9 JB |
4915 | |
4916 | temp_flags = i.flags[xchg2]; | |
4917 | i.flags[xchg2] = i.flags[xchg1]; | |
4918 | i.flags[xchg1] = temp_flags; | |
4919 | ||
050dfa73 MM |
4920 | temp_op = i.op[xchg2]; |
4921 | i.op[xchg2] = i.op[xchg1]; | |
4922 | i.op[xchg1] = temp_op; | |
c48dadc9 | 4923 | |
050dfa73 MM |
4924 | temp_reloc = i.reloc[xchg2]; |
4925 | i.reloc[xchg2] = i.reloc[xchg1]; | |
4926 | i.reloc[xchg1] = temp_reloc; | |
43234a1e L |
4927 | |
4928 | if (i.mask) | |
4929 | { | |
4930 | if (i.mask->operand == xchg1) | |
4931 | i.mask->operand = xchg2; | |
4932 | else if (i.mask->operand == xchg2) | |
4933 | i.mask->operand = xchg1; | |
4934 | } | |
4935 | if (i.broadcast) | |
4936 | { | |
4937 | if (i.broadcast->operand == xchg1) | |
4938 | i.broadcast->operand = xchg2; | |
4939 | else if (i.broadcast->operand == xchg2) | |
4940 | i.broadcast->operand = xchg1; | |
4941 | } | |
4942 | if (i.rounding) | |
4943 | { | |
4944 | if (i.rounding->operand == xchg1) | |
4945 | i.rounding->operand = xchg2; | |
4946 | else if (i.rounding->operand == xchg2) | |
4947 | i.rounding->operand = xchg1; | |
4948 | } | |
050dfa73 MM |
4949 | } |
4950 | ||
29b0f896 | 4951 | static void |
e3bb37b5 | 4952 | swap_operands (void) |
29b0f896 | 4953 | { |
b7c61d9a | 4954 | switch (i.operands) |
050dfa73 | 4955 | { |
c0f3af97 | 4956 | case 5: |
b7c61d9a | 4957 | case 4: |
4d456e3d | 4958 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 4959 | /* Fall through. */ |
b7c61d9a L |
4960 | case 3: |
4961 | case 2: | |
4d456e3d | 4962 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
4963 | break; |
4964 | default: | |
4965 | abort (); | |
29b0f896 | 4966 | } |
29b0f896 AM |
4967 | |
4968 | if (i.mem_operands == 2) | |
4969 | { | |
4970 | const seg_entry *temp_seg; | |
4971 | temp_seg = i.seg[0]; | |
4972 | i.seg[0] = i.seg[1]; | |
4973 | i.seg[1] = temp_seg; | |
4974 | } | |
4975 | } | |
252b5132 | 4976 | |
29b0f896 AM |
4977 | /* Try to ensure constant immediates are represented in the smallest |
4978 | opcode possible. */ | |
4979 | static void | |
e3bb37b5 | 4980 | optimize_imm (void) |
29b0f896 AM |
4981 | { |
4982 | char guess_suffix = 0; | |
4983 | int op; | |
252b5132 | 4984 | |
29b0f896 AM |
4985 | if (i.suffix) |
4986 | guess_suffix = i.suffix; | |
4987 | else if (i.reg_operands) | |
4988 | { | |
4989 | /* Figure out a suffix from the last register operand specified. | |
4990 | We can't do this properly yet, ie. excluding InOutPortReg, | |
4991 | but the following works for instructions with immediates. | |
4992 | In any case, we can't set i.suffix yet. */ | |
4993 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 4994 | if (i.types[op].bitfield.reg && i.types[op].bitfield.byte) |
7ab9ffdd | 4995 | { |
40fb9820 L |
4996 | guess_suffix = BYTE_MNEM_SUFFIX; |
4997 | break; | |
4998 | } | |
dc821c5f | 4999 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.word) |
252b5132 | 5000 | { |
40fb9820 L |
5001 | guess_suffix = WORD_MNEM_SUFFIX; |
5002 | break; | |
5003 | } | |
dc821c5f | 5004 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword) |
40fb9820 L |
5005 | { |
5006 | guess_suffix = LONG_MNEM_SUFFIX; | |
5007 | break; | |
5008 | } | |
dc821c5f | 5009 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword) |
40fb9820 L |
5010 | { |
5011 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 5012 | break; |
252b5132 | 5013 | } |
29b0f896 AM |
5014 | } |
5015 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
5016 | guess_suffix = WORD_MNEM_SUFFIX; | |
5017 | ||
5018 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 5019 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
5020 | { |
5021 | switch (i.op[op].imms->X_op) | |
252b5132 | 5022 | { |
29b0f896 AM |
5023 | case O_constant: |
5024 | /* If a suffix is given, this operand may be shortened. */ | |
5025 | switch (guess_suffix) | |
252b5132 | 5026 | { |
29b0f896 | 5027 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
5028 | i.types[op].bitfield.imm32 = 1; |
5029 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5030 | break; |
5031 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
5032 | i.types[op].bitfield.imm16 = 1; |
5033 | i.types[op].bitfield.imm32 = 1; | |
5034 | i.types[op].bitfield.imm32s = 1; | |
5035 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5036 | break; |
5037 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
5038 | i.types[op].bitfield.imm8 = 1; |
5039 | i.types[op].bitfield.imm8s = 1; | |
5040 | i.types[op].bitfield.imm16 = 1; | |
5041 | i.types[op].bitfield.imm32 = 1; | |
5042 | i.types[op].bitfield.imm32s = 1; | |
5043 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 5044 | break; |
252b5132 | 5045 | } |
252b5132 | 5046 | |
29b0f896 AM |
5047 | /* If this operand is at most 16 bits, convert it |
5048 | to a signed 16 bit number before trying to see | |
5049 | whether it will fit in an even smaller size. | |
5050 | This allows a 16-bit operand such as $0xffe0 to | |
5051 | be recognised as within Imm8S range. */ | |
40fb9820 | 5052 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 5053 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 5054 | { |
29b0f896 AM |
5055 | i.op[op].imms->X_add_number = |
5056 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
5057 | } | |
a28def75 L |
5058 | #ifdef BFD64 |
5059 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 5060 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
5061 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
5062 | == 0)) | |
5063 | { | |
5064 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
5065 | ^ ((offsetT) 1 << 31)) | |
5066 | - ((offsetT) 1 << 31)); | |
5067 | } | |
a28def75 | 5068 | #endif |
40fb9820 | 5069 | i.types[op] |
c6fb90c8 L |
5070 | = operand_type_or (i.types[op], |
5071 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 5072 | |
29b0f896 AM |
5073 | /* We must avoid matching of Imm32 templates when 64bit |
5074 | only immediate is available. */ | |
5075 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 5076 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 5077 | break; |
252b5132 | 5078 | |
29b0f896 AM |
5079 | case O_absent: |
5080 | case O_register: | |
5081 | abort (); | |
5082 | ||
5083 | /* Symbols and expressions. */ | |
5084 | default: | |
9cd96992 JB |
5085 | /* Convert symbolic operand to proper sizes for matching, but don't |
5086 | prevent matching a set of insns that only supports sizes other | |
5087 | than those matching the insn suffix. */ | |
5088 | { | |
40fb9820 | 5089 | i386_operand_type mask, allowed; |
d3ce72d0 | 5090 | const insn_template *t; |
9cd96992 | 5091 | |
0dfbf9d7 L |
5092 | operand_type_set (&mask, 0); |
5093 | operand_type_set (&allowed, 0); | |
40fb9820 | 5094 | |
4eed87de AM |
5095 | for (t = current_templates->start; |
5096 | t < current_templates->end; | |
5097 | ++t) | |
c6fb90c8 L |
5098 | allowed = operand_type_or (allowed, |
5099 | t->operand_types[op]); | |
9cd96992 JB |
5100 | switch (guess_suffix) |
5101 | { | |
5102 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
5103 | mask.bitfield.imm64 = 1; |
5104 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
5105 | break; |
5106 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 5107 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
5108 | break; |
5109 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 5110 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
5111 | break; |
5112 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 5113 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
5114 | break; |
5115 | default: | |
9cd96992 JB |
5116 | break; |
5117 | } | |
c6fb90c8 | 5118 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 5119 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 5120 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 5121 | } |
29b0f896 | 5122 | break; |
252b5132 | 5123 | } |
29b0f896 AM |
5124 | } |
5125 | } | |
47926f60 | 5126 | |
29b0f896 AM |
5127 | /* Try to use the smallest displacement type too. */ |
5128 | static void | |
e3bb37b5 | 5129 | optimize_disp (void) |
29b0f896 AM |
5130 | { |
5131 | int op; | |
3e73aa7c | 5132 | |
29b0f896 | 5133 | for (op = i.operands; --op >= 0;) |
40fb9820 | 5134 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 5135 | { |
b300c311 | 5136 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 5137 | { |
91d6fa6a | 5138 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 5139 | |
40fb9820 | 5140 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 5141 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
5142 | { |
5143 | /* If this operand is at most 16 bits, convert | |
5144 | to a signed 16 bit number and don't use 64bit | |
5145 | displacement. */ | |
91d6fa6a | 5146 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 5147 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5148 | } |
a28def75 L |
5149 | #ifdef BFD64 |
5150 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ | |
40fb9820 | 5151 | if (i.types[op].bitfield.disp32 |
91d6fa6a | 5152 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
b300c311 L |
5153 | { |
5154 | /* If this operand is at most 32 bits, convert | |
5155 | to a signed 32 bit number and don't use 64bit | |
5156 | displacement. */ | |
91d6fa6a NC |
5157 | op_disp &= (((offsetT) 2 << 31) - 1); |
5158 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 5159 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5160 | } |
a28def75 | 5161 | #endif |
91d6fa6a | 5162 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 5163 | { |
40fb9820 L |
5164 | i.types[op].bitfield.disp8 = 0; |
5165 | i.types[op].bitfield.disp16 = 0; | |
5166 | i.types[op].bitfield.disp32 = 0; | |
5167 | i.types[op].bitfield.disp32s = 0; | |
5168 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
5169 | i.op[op].disps = 0; |
5170 | i.disp_operands--; | |
5171 | } | |
5172 | else if (flag_code == CODE_64BIT) | |
5173 | { | |
91d6fa6a | 5174 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 5175 | { |
40fb9820 L |
5176 | i.types[op].bitfield.disp64 = 0; |
5177 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 5178 | } |
0e1147d9 | 5179 | if (i.prefix[ADDR_PREFIX] |
91d6fa6a | 5180 | && fits_in_unsigned_long (op_disp)) |
40fb9820 | 5181 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 5182 | } |
40fb9820 L |
5183 | if ((i.types[op].bitfield.disp32 |
5184 | || i.types[op].bitfield.disp32s | |
5185 | || i.types[op].bitfield.disp16) | |
b5014f7a | 5186 | && fits_in_disp8 (op_disp)) |
40fb9820 | 5187 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 5188 | } |
67a4f2b7 AO |
5189 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
5190 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
5191 | { | |
5192 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
5193 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
5194 | i.types[op].bitfield.disp8 = 0; |
5195 | i.types[op].bitfield.disp16 = 0; | |
5196 | i.types[op].bitfield.disp32 = 0; | |
5197 | i.types[op].bitfield.disp32s = 0; | |
5198 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
5199 | } |
5200 | else | |
b300c311 | 5201 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 5202 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 5203 | } |
29b0f896 AM |
5204 | } |
5205 | ||
4a1b91ea L |
5206 | /* Return 1 if there is a match in broadcast bytes between operand |
5207 | GIVEN and instruction template T. */ | |
5208 | ||
5209 | static INLINE int | |
5210 | match_broadcast_size (const insn_template *t, unsigned int given) | |
5211 | { | |
5212 | return ((t->opcode_modifier.broadcast == BYTE_BROADCAST | |
5213 | && i.types[given].bitfield.byte) | |
5214 | || (t->opcode_modifier.broadcast == WORD_BROADCAST | |
5215 | && i.types[given].bitfield.word) | |
5216 | || (t->opcode_modifier.broadcast == DWORD_BROADCAST | |
5217 | && i.types[given].bitfield.dword) | |
5218 | || (t->opcode_modifier.broadcast == QWORD_BROADCAST | |
5219 | && i.types[given].bitfield.qword)); | |
5220 | } | |
5221 | ||
6c30d220 L |
5222 | /* Check if operands are valid for the instruction. */ |
5223 | ||
5224 | static int | |
5225 | check_VecOperands (const insn_template *t) | |
5226 | { | |
43234a1e | 5227 | unsigned int op; |
e2195274 JB |
5228 | i386_cpu_flags cpu; |
5229 | static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; | |
5230 | ||
5231 | /* Templates allowing for ZMMword as well as YMMword and/or XMMword for | |
5232 | any one operand are implicity requiring AVX512VL support if the actual | |
5233 | operand size is YMMword or XMMword. Since this function runs after | |
5234 | template matching, there's no need to check for YMMword/XMMword in | |
5235 | the template. */ | |
5236 | cpu = cpu_flags_and (t->cpu_flags, avx512); | |
5237 | if (!cpu_flags_all_zero (&cpu) | |
5238 | && !t->cpu_flags.bitfield.cpuavx512vl | |
5239 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
5240 | { | |
5241 | for (op = 0; op < t->operands; ++op) | |
5242 | { | |
5243 | if (t->operand_types[op].bitfield.zmmword | |
5244 | && (i.types[op].bitfield.ymmword | |
5245 | || i.types[op].bitfield.xmmword)) | |
5246 | { | |
5247 | i.error = unsupported; | |
5248 | return 1; | |
5249 | } | |
5250 | } | |
5251 | } | |
43234a1e | 5252 | |
6c30d220 L |
5253 | /* Without VSIB byte, we can't have a vector register for index. */ |
5254 | if (!t->opcode_modifier.vecsib | |
5255 | && i.index_reg | |
1b54b8d7 JB |
5256 | && (i.index_reg->reg_type.bitfield.xmmword |
5257 | || i.index_reg->reg_type.bitfield.ymmword | |
5258 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
5259 | { |
5260 | i.error = unsupported_vector_index_register; | |
5261 | return 1; | |
5262 | } | |
5263 | ||
ad8ecc81 MZ |
5264 | /* Check if default mask is allowed. */ |
5265 | if (t->opcode_modifier.nodefmask | |
5266 | && (!i.mask || i.mask->mask->reg_num == 0)) | |
5267 | { | |
5268 | i.error = no_default_mask; | |
5269 | return 1; | |
5270 | } | |
5271 | ||
7bab8ab5 JB |
5272 | /* For VSIB byte, we need a vector register for index, and all vector |
5273 | registers must be distinct. */ | |
5274 | if (t->opcode_modifier.vecsib) | |
5275 | { | |
5276 | if (!i.index_reg | |
6c30d220 | 5277 | || !((t->opcode_modifier.vecsib == VecSIB128 |
1b54b8d7 | 5278 | && i.index_reg->reg_type.bitfield.xmmword) |
6c30d220 | 5279 | || (t->opcode_modifier.vecsib == VecSIB256 |
1b54b8d7 | 5280 | && i.index_reg->reg_type.bitfield.ymmword) |
43234a1e | 5281 | || (t->opcode_modifier.vecsib == VecSIB512 |
1b54b8d7 | 5282 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
5283 | { |
5284 | i.error = invalid_vsib_address; | |
5285 | return 1; | |
5286 | } | |
5287 | ||
43234a1e L |
5288 | gas_assert (i.reg_operands == 2 || i.mask); |
5289 | if (i.reg_operands == 2 && !i.mask) | |
5290 | { | |
1b54b8d7 JB |
5291 | gas_assert (i.types[0].bitfield.regsimd); |
5292 | gas_assert (i.types[0].bitfield.xmmword | |
5293 | || i.types[0].bitfield.ymmword); | |
5294 | gas_assert (i.types[2].bitfield.regsimd); | |
5295 | gas_assert (i.types[2].bitfield.xmmword | |
5296 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
5297 | if (operand_check == check_none) |
5298 | return 0; | |
5299 | if (register_number (i.op[0].regs) | |
5300 | != register_number (i.index_reg) | |
5301 | && register_number (i.op[2].regs) | |
5302 | != register_number (i.index_reg) | |
5303 | && register_number (i.op[0].regs) | |
5304 | != register_number (i.op[2].regs)) | |
5305 | return 0; | |
5306 | if (operand_check == check_error) | |
5307 | { | |
5308 | i.error = invalid_vector_register_set; | |
5309 | return 1; | |
5310 | } | |
5311 | as_warn (_("mask, index, and destination registers should be distinct")); | |
5312 | } | |
8444f82a MZ |
5313 | else if (i.reg_operands == 1 && i.mask) |
5314 | { | |
1b54b8d7 JB |
5315 | if (i.types[1].bitfield.regsimd |
5316 | && (i.types[1].bitfield.xmmword | |
5317 | || i.types[1].bitfield.ymmword | |
5318 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
5319 | && (register_number (i.op[1].regs) |
5320 | == register_number (i.index_reg))) | |
5321 | { | |
5322 | if (operand_check == check_error) | |
5323 | { | |
5324 | i.error = invalid_vector_register_set; | |
5325 | return 1; | |
5326 | } | |
5327 | if (operand_check != check_none) | |
5328 | as_warn (_("index and destination registers should be distinct")); | |
5329 | } | |
5330 | } | |
43234a1e | 5331 | } |
7bab8ab5 | 5332 | |
43234a1e L |
5333 | /* Check if broadcast is supported by the instruction and is applied |
5334 | to the memory operand. */ | |
5335 | if (i.broadcast) | |
5336 | { | |
8e6e0792 | 5337 | i386_operand_type type, overlap; |
43234a1e L |
5338 | |
5339 | /* Check if specified broadcast is supported in this instruction, | |
4a1b91ea | 5340 | and its broadcast bytes match the memory operand. */ |
32546502 | 5341 | op = i.broadcast->operand; |
8e6e0792 | 5342 | if (!t->opcode_modifier.broadcast |
c48dadc9 | 5343 | || !(i.flags[op] & Operand_Mem) |
c39e5b26 | 5344 | || (!i.types[op].bitfield.unspecified |
4a1b91ea | 5345 | && !match_broadcast_size (t, op))) |
43234a1e L |
5346 | { |
5347 | bad_broadcast: | |
5348 | i.error = unsupported_broadcast; | |
5349 | return 1; | |
5350 | } | |
8e6e0792 | 5351 | |
4a1b91ea L |
5352 | i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1)) |
5353 | * i.broadcast->type); | |
8e6e0792 | 5354 | operand_type_set (&type, 0); |
4a1b91ea | 5355 | switch (i.broadcast->bytes) |
8e6e0792 | 5356 | { |
4a1b91ea L |
5357 | case 2: |
5358 | type.bitfield.word = 1; | |
5359 | break; | |
5360 | case 4: | |
5361 | type.bitfield.dword = 1; | |
5362 | break; | |
8e6e0792 JB |
5363 | case 8: |
5364 | type.bitfield.qword = 1; | |
5365 | break; | |
5366 | case 16: | |
5367 | type.bitfield.xmmword = 1; | |
5368 | break; | |
5369 | case 32: | |
5370 | type.bitfield.ymmword = 1; | |
5371 | break; | |
5372 | case 64: | |
5373 | type.bitfield.zmmword = 1; | |
5374 | break; | |
5375 | default: | |
5376 | goto bad_broadcast; | |
5377 | } | |
5378 | ||
5379 | overlap = operand_type_and (type, t->operand_types[op]); | |
5380 | if (operand_type_all_zero (&overlap)) | |
5381 | goto bad_broadcast; | |
5382 | ||
5383 | if (t->opcode_modifier.checkregsize) | |
5384 | { | |
5385 | unsigned int j; | |
5386 | ||
e2195274 | 5387 | type.bitfield.baseindex = 1; |
8e6e0792 JB |
5388 | for (j = 0; j < i.operands; ++j) |
5389 | { | |
5390 | if (j != op | |
5391 | && !operand_type_register_match(i.types[j], | |
5392 | t->operand_types[j], | |
5393 | type, | |
5394 | t->operand_types[op])) | |
5395 | goto bad_broadcast; | |
5396 | } | |
5397 | } | |
43234a1e L |
5398 | } |
5399 | /* If broadcast is supported in this instruction, we need to check if | |
5400 | operand of one-element size isn't specified without broadcast. */ | |
5401 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
5402 | { | |
5403 | /* Find memory operand. */ | |
5404 | for (op = 0; op < i.operands; op++) | |
5405 | if (operand_type_check (i.types[op], anymem)) | |
5406 | break; | |
5407 | gas_assert (op < i.operands); | |
5408 | /* Check size of the memory operand. */ | |
4a1b91ea | 5409 | if (match_broadcast_size (t, op)) |
43234a1e L |
5410 | { |
5411 | i.error = broadcast_needed; | |
5412 | return 1; | |
5413 | } | |
5414 | } | |
c39e5b26 JB |
5415 | else |
5416 | op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */ | |
43234a1e L |
5417 | |
5418 | /* Check if requested masking is supported. */ | |
ae2387fe | 5419 | if (i.mask) |
43234a1e | 5420 | { |
ae2387fe JB |
5421 | switch (t->opcode_modifier.masking) |
5422 | { | |
5423 | case BOTH_MASKING: | |
5424 | break; | |
5425 | case MERGING_MASKING: | |
5426 | if (i.mask->zeroing) | |
5427 | { | |
5428 | case 0: | |
5429 | i.error = unsupported_masking; | |
5430 | return 1; | |
5431 | } | |
5432 | break; | |
5433 | case DYNAMIC_MASKING: | |
5434 | /* Memory destinations allow only merging masking. */ | |
5435 | if (i.mask->zeroing && i.mem_operands) | |
5436 | { | |
5437 | /* Find memory operand. */ | |
5438 | for (op = 0; op < i.operands; op++) | |
c48dadc9 | 5439 | if (i.flags[op] & Operand_Mem) |
ae2387fe JB |
5440 | break; |
5441 | gas_assert (op < i.operands); | |
5442 | if (op == i.operands - 1) | |
5443 | { | |
5444 | i.error = unsupported_masking; | |
5445 | return 1; | |
5446 | } | |
5447 | } | |
5448 | break; | |
5449 | default: | |
5450 | abort (); | |
5451 | } | |
43234a1e L |
5452 | } |
5453 | ||
5454 | /* Check if masking is applied to dest operand. */ | |
5455 | if (i.mask && (i.mask->operand != (int) (i.operands - 1))) | |
5456 | { | |
5457 | i.error = mask_not_on_destination; | |
5458 | return 1; | |
5459 | } | |
5460 | ||
43234a1e L |
5461 | /* Check RC/SAE. */ |
5462 | if (i.rounding) | |
5463 | { | |
5464 | if ((i.rounding->type != saeonly | |
5465 | && !t->opcode_modifier.staticrounding) | |
5466 | || (i.rounding->type == saeonly | |
5467 | && (t->opcode_modifier.staticrounding | |
5468 | || !t->opcode_modifier.sae))) | |
5469 | { | |
5470 | i.error = unsupported_rc_sae; | |
5471 | return 1; | |
5472 | } | |
5473 | /* If the instruction has several immediate operands and one of | |
5474 | them is rounding, the rounding operand should be the last | |
5475 | immediate operand. */ | |
5476 | if (i.imm_operands > 1 | |
5477 | && i.rounding->operand != (int) (i.imm_operands - 1)) | |
7bab8ab5 | 5478 | { |
43234a1e | 5479 | i.error = rc_sae_operand_not_last_imm; |
7bab8ab5 JB |
5480 | return 1; |
5481 | } | |
6c30d220 L |
5482 | } |
5483 | ||
43234a1e | 5484 | /* Check vector Disp8 operand. */ |
b5014f7a JB |
5485 | if (t->opcode_modifier.disp8memshift |
5486 | && i.disp_encoding != disp_encoding_32bit) | |
43234a1e L |
5487 | { |
5488 | if (i.broadcast) | |
4a1b91ea | 5489 | i.memshift = t->opcode_modifier.broadcast - 1; |
7091c612 | 5490 | else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL) |
43234a1e | 5491 | i.memshift = t->opcode_modifier.disp8memshift; |
7091c612 JB |
5492 | else |
5493 | { | |
5494 | const i386_operand_type *type = NULL; | |
5495 | ||
5496 | i.memshift = 0; | |
5497 | for (op = 0; op < i.operands; op++) | |
5498 | if (operand_type_check (i.types[op], anymem)) | |
5499 | { | |
4174bfff JB |
5500 | if (t->opcode_modifier.evex == EVEXLIG) |
5501 | i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); | |
5502 | else if (t->operand_types[op].bitfield.xmmword | |
5503 | + t->operand_types[op].bitfield.ymmword | |
5504 | + t->operand_types[op].bitfield.zmmword <= 1) | |
7091c612 JB |
5505 | type = &t->operand_types[op]; |
5506 | else if (!i.types[op].bitfield.unspecified) | |
5507 | type = &i.types[op]; | |
5508 | } | |
4174bfff JB |
5509 | else if (i.types[op].bitfield.regsimd |
5510 | && t->opcode_modifier.evex != EVEXLIG) | |
7091c612 JB |
5511 | { |
5512 | if (i.types[op].bitfield.zmmword) | |
5513 | i.memshift = 6; | |
5514 | else if (i.types[op].bitfield.ymmword && i.memshift < 5) | |
5515 | i.memshift = 5; | |
5516 | else if (i.types[op].bitfield.xmmword && i.memshift < 4) | |
5517 | i.memshift = 4; | |
5518 | } | |
5519 | ||
5520 | if (type) | |
5521 | { | |
5522 | if (type->bitfield.zmmword) | |
5523 | i.memshift = 6; | |
5524 | else if (type->bitfield.ymmword) | |
5525 | i.memshift = 5; | |
5526 | else if (type->bitfield.xmmword) | |
5527 | i.memshift = 4; | |
5528 | } | |
5529 | ||
5530 | /* For the check in fits_in_disp8(). */ | |
5531 | if (i.memshift == 0) | |
5532 | i.memshift = -1; | |
5533 | } | |
43234a1e L |
5534 | |
5535 | for (op = 0; op < i.operands; op++) | |
5536 | if (operand_type_check (i.types[op], disp) | |
5537 | && i.op[op].disps->X_op == O_constant) | |
5538 | { | |
b5014f7a | 5539 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 5540 | { |
b5014f7a JB |
5541 | i.types[op].bitfield.disp8 = 1; |
5542 | return 0; | |
43234a1e | 5543 | } |
b5014f7a | 5544 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
5545 | } |
5546 | } | |
b5014f7a JB |
5547 | |
5548 | i.memshift = 0; | |
43234a1e | 5549 | |
6c30d220 L |
5550 | return 0; |
5551 | } | |
5552 | ||
43f3e2ee | 5553 | /* Check if operands are valid for the instruction. Update VEX |
a683cc34 SP |
5554 | operand types. */ |
5555 | ||
5556 | static int | |
5557 | VEX_check_operands (const insn_template *t) | |
5558 | { | |
86fa6981 | 5559 | if (i.vec_encoding == vex_encoding_evex) |
43234a1e | 5560 | { |
86fa6981 | 5561 | /* This instruction must be encoded with EVEX prefix. */ |
e771e7c9 | 5562 | if (!is_evex_encoding (t)) |
86fa6981 L |
5563 | { |
5564 | i.error = unsupported; | |
5565 | return 1; | |
5566 | } | |
5567 | return 0; | |
43234a1e L |
5568 | } |
5569 | ||
a683cc34 | 5570 | if (!t->opcode_modifier.vex) |
86fa6981 L |
5571 | { |
5572 | /* This instruction template doesn't have VEX prefix. */ | |
5573 | if (i.vec_encoding != vex_encoding_default) | |
5574 | { | |
5575 | i.error = unsupported; | |
5576 | return 1; | |
5577 | } | |
5578 | return 0; | |
5579 | } | |
a683cc34 SP |
5580 | |
5581 | /* Only check VEX_Imm4, which must be the first operand. */ | |
5582 | if (t->operand_types[0].bitfield.vec_imm4) | |
5583 | { | |
5584 | if (i.op[0].imms->X_op != O_constant | |
5585 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
891edac4 | 5586 | { |
a65babc9 | 5587 | i.error = bad_imm4; |
891edac4 L |
5588 | return 1; |
5589 | } | |
a683cc34 SP |
5590 | |
5591 | /* Turn off Imm8 so that update_imm won't complain. */ | |
5592 | i.types[0] = vec_imm4; | |
5593 | } | |
5594 | ||
5595 | return 0; | |
5596 | } | |
5597 | ||
d3ce72d0 | 5598 | static const insn_template * |
83b16ac6 | 5599 | match_template (char mnem_suffix) |
29b0f896 AM |
5600 | { |
5601 | /* Points to template once we've found it. */ | |
d3ce72d0 | 5602 | const insn_template *t; |
40fb9820 | 5603 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 5604 | i386_operand_type overlap4; |
29b0f896 | 5605 | unsigned int found_reverse_match; |
83b16ac6 | 5606 | i386_opcode_modifier suffix_check, mnemsuf_check; |
40fb9820 | 5607 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 5608 | int addr_prefix_disp; |
a5c311ca | 5609 | unsigned int j; |
3ac21baa | 5610 | unsigned int found_cpu_match, size_match; |
45664ddb | 5611 | unsigned int check_register; |
5614d22c | 5612 | enum i386_error specific_error = 0; |
29b0f896 | 5613 | |
c0f3af97 L |
5614 | #if MAX_OPERANDS != 5 |
5615 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
5616 | #endif |
5617 | ||
29b0f896 | 5618 | found_reverse_match = 0; |
539e75ad | 5619 | addr_prefix_disp = -1; |
40fb9820 L |
5620 | |
5621 | memset (&suffix_check, 0, sizeof (suffix_check)); | |
e2195274 JB |
5622 | if (intel_syntax && i.broadcast) |
5623 | /* nothing */; | |
5624 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
40fb9820 L |
5625 | suffix_check.no_bsuf = 1; |
5626 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
5627 | suffix_check.no_wsuf = 1; | |
5628 | else if (i.suffix == SHORT_MNEM_SUFFIX) | |
5629 | suffix_check.no_ssuf = 1; | |
5630 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
5631 | suffix_check.no_lsuf = 1; | |
5632 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
5633 | suffix_check.no_qsuf = 1; | |
5634 | else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
7ce189b3 | 5635 | suffix_check.no_ldsuf = 1; |
29b0f896 | 5636 | |
83b16ac6 JB |
5637 | memset (&mnemsuf_check, 0, sizeof (mnemsuf_check)); |
5638 | if (intel_syntax) | |
5639 | { | |
5640 | switch (mnem_suffix) | |
5641 | { | |
5642 | case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break; | |
5643 | case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break; | |
5644 | case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break; | |
5645 | case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break; | |
5646 | case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break; | |
5647 | } | |
5648 | } | |
5649 | ||
01559ecc L |
5650 | /* Must have right number of operands. */ |
5651 | i.error = number_of_operands_mismatch; | |
5652 | ||
45aa61fe | 5653 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 5654 | { |
539e75ad | 5655 | addr_prefix_disp = -1; |
dbbc8b7e | 5656 | found_reverse_match = 0; |
539e75ad | 5657 | |
29b0f896 AM |
5658 | if (i.operands != t->operands) |
5659 | continue; | |
5660 | ||
50aecf8c | 5661 | /* Check processor support. */ |
a65babc9 | 5662 | i.error = unsupported; |
c0f3af97 L |
5663 | found_cpu_match = (cpu_flags_match (t) |
5664 | == CPU_FLAGS_PERFECT_MATCH); | |
50aecf8c L |
5665 | if (!found_cpu_match) |
5666 | continue; | |
5667 | ||
e1d4d893 | 5668 | /* Check AT&T mnemonic. */ |
a65babc9 | 5669 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 5670 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
5671 | continue; |
5672 | ||
e92bae62 | 5673 | /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */ |
a65babc9 | 5674 | i.error = unsupported_syntax; |
5c07affc | 5675 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
e92bae62 L |
5676 | || (!intel_syntax && t->opcode_modifier.intelsyntax) |
5677 | || (intel64 && t->opcode_modifier.amd64) | |
5678 | || (!intel64 && t->opcode_modifier.intel64)) | |
1efbbeb4 L |
5679 | continue; |
5680 | ||
20592a94 | 5681 | /* Check the suffix, except for some instructions in intel mode. */ |
a65babc9 | 5682 | i.error = invalid_instruction_suffix; |
567e4e96 L |
5683 | if ((!intel_syntax || !t->opcode_modifier.ignoresize) |
5684 | && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) | |
5685 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
5686 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
5687 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
5688 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
5689 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) | |
29b0f896 | 5690 | continue; |
83b16ac6 JB |
5691 | /* In Intel mode all mnemonic suffixes must be explicitly allowed. */ |
5692 | if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf) | |
5693 | || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf) | |
5694 | || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf) | |
5695 | || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf) | |
5696 | || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf) | |
5697 | || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf)) | |
5698 | continue; | |
29b0f896 | 5699 | |
3ac21baa JB |
5700 | size_match = operand_size_match (t); |
5701 | if (!size_match) | |
7d5e4556 | 5702 | continue; |
539e75ad | 5703 | |
5c07affc L |
5704 | for (j = 0; j < MAX_OPERANDS; j++) |
5705 | operand_types[j] = t->operand_types[j]; | |
5706 | ||
45aa61fe AM |
5707 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
5708 | if (i.suffix == QWORD_MNEM_SUFFIX | |
5709 | && flag_code != CODE_64BIT | |
5710 | && (intel_syntax | |
40fb9820 | 5711 | ? (!t->opcode_modifier.ignoresize |
625cbd7a | 5712 | && !t->opcode_modifier.broadcast |
45aa61fe AM |
5713 | && !intel_float_operand (t->name)) |
5714 | : intel_float_operand (t->name) != 2) | |
40fb9820 | 5715 | && ((!operand_types[0].bitfield.regmmx |
1b54b8d7 | 5716 | && !operand_types[0].bitfield.regsimd) |
40fb9820 | 5717 | || (!operand_types[t->operands > 1].bitfield.regmmx |
1b54b8d7 | 5718 | && !operand_types[t->operands > 1].bitfield.regsimd)) |
45aa61fe AM |
5719 | && (t->base_opcode != 0x0fc7 |
5720 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
5721 | continue; | |
5722 | ||
192dc9c6 JB |
5723 | /* In general, don't allow 32-bit operands on pre-386. */ |
5724 | else if (i.suffix == LONG_MNEM_SUFFIX | |
5725 | && !cpu_arch_flags.bitfield.cpui386 | |
5726 | && (intel_syntax | |
5727 | ? (!t->opcode_modifier.ignoresize | |
5728 | && !intel_float_operand (t->name)) | |
5729 | : intel_float_operand (t->name) != 2) | |
5730 | && ((!operand_types[0].bitfield.regmmx | |
1b54b8d7 | 5731 | && !operand_types[0].bitfield.regsimd) |
192dc9c6 | 5732 | || (!operand_types[t->operands > 1].bitfield.regmmx |
1b54b8d7 | 5733 | && !operand_types[t->operands > 1].bitfield.regsimd))) |
192dc9c6 JB |
5734 | continue; |
5735 | ||
29b0f896 | 5736 | /* Do not verify operands when there are none. */ |
50aecf8c | 5737 | else |
29b0f896 | 5738 | { |
c6fb90c8 | 5739 | if (!t->operands) |
2dbab7d5 L |
5740 | /* We've found a match; break out of loop. */ |
5741 | break; | |
29b0f896 | 5742 | } |
252b5132 | 5743 | |
539e75ad L |
5744 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
5745 | into Disp32/Disp16/Disp32 operand. */ | |
5746 | if (i.prefix[ADDR_PREFIX] != 0) | |
5747 | { | |
40fb9820 | 5748 | /* There should be only one Disp operand. */ |
539e75ad L |
5749 | switch (flag_code) |
5750 | { | |
5751 | case CODE_16BIT: | |
40fb9820 L |
5752 | for (j = 0; j < MAX_OPERANDS; j++) |
5753 | { | |
5754 | if (operand_types[j].bitfield.disp16) | |
5755 | { | |
5756 | addr_prefix_disp = j; | |
5757 | operand_types[j].bitfield.disp32 = 1; | |
5758 | operand_types[j].bitfield.disp16 = 0; | |
5759 | break; | |
5760 | } | |
5761 | } | |
539e75ad L |
5762 | break; |
5763 | case CODE_32BIT: | |
40fb9820 L |
5764 | for (j = 0; j < MAX_OPERANDS; j++) |
5765 | { | |
5766 | if (operand_types[j].bitfield.disp32) | |
5767 | { | |
5768 | addr_prefix_disp = j; | |
5769 | operand_types[j].bitfield.disp32 = 0; | |
5770 | operand_types[j].bitfield.disp16 = 1; | |
5771 | break; | |
5772 | } | |
5773 | } | |
539e75ad L |
5774 | break; |
5775 | case CODE_64BIT: | |
40fb9820 L |
5776 | for (j = 0; j < MAX_OPERANDS; j++) |
5777 | { | |
5778 | if (operand_types[j].bitfield.disp64) | |
5779 | { | |
5780 | addr_prefix_disp = j; | |
5781 | operand_types[j].bitfield.disp64 = 0; | |
5782 | operand_types[j].bitfield.disp32 = 1; | |
5783 | break; | |
5784 | } | |
5785 | } | |
539e75ad L |
5786 | break; |
5787 | } | |
539e75ad L |
5788 | } |
5789 | ||
02a86693 L |
5790 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
5791 | if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) | |
5792 | continue; | |
5793 | ||
56ffb741 | 5794 | /* We check register size if needed. */ |
e2195274 JB |
5795 | if (t->opcode_modifier.checkregsize) |
5796 | { | |
5797 | check_register = (1 << t->operands) - 1; | |
5798 | if (i.broadcast) | |
5799 | check_register &= ~(1 << i.broadcast->operand); | |
5800 | } | |
5801 | else | |
5802 | check_register = 0; | |
5803 | ||
c6fb90c8 | 5804 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
5805 | switch (t->operands) |
5806 | { | |
5807 | case 1: | |
40fb9820 | 5808 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
5809 | continue; |
5810 | break; | |
5811 | case 2: | |
33eaf5de | 5812 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
5813 | only in 32bit mode and we can use opcode 0x90. In 64bit |
5814 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
5815 | zero-extend %eax to %rax. */ | |
5816 | if (flag_code == CODE_64BIT | |
5817 | && t->base_opcode == 0x90 | |
2c703856 JB |
5818 | && i.types[0].bitfield.acc && i.types[0].bitfield.dword |
5819 | && i.types[1].bitfield.acc && i.types[1].bitfield.dword) | |
8b38ad71 | 5820 | continue; |
1212781b JB |
5821 | /* xrelease mov %eax, <disp> is another special case. It must not |
5822 | match the accumulator-only encoding of mov. */ | |
5823 | if (flag_code != CODE_64BIT | |
5824 | && i.hle_prefix | |
5825 | && t->base_opcode == 0xa0 | |
5826 | && i.types[0].bitfield.acc | |
5827 | && operand_type_check (i.types[1], anymem)) | |
5828 | continue; | |
f5eb1d70 JB |
5829 | /* Fall through. */ |
5830 | ||
5831 | case 3: | |
3ac21baa JB |
5832 | if (!(size_match & MATCH_STRAIGHT)) |
5833 | goto check_reverse; | |
64c49ab3 JB |
5834 | /* Reverse direction of operands if swapping is possible in the first |
5835 | place (operands need to be symmetric) and | |
5836 | - the load form is requested, and the template is a store form, | |
5837 | - the store form is requested, and the template is a load form, | |
5838 | - the non-default (swapped) form is requested. */ | |
5839 | overlap1 = operand_type_and (operand_types[0], operand_types[1]); | |
f5eb1d70 | 5840 | if (t->opcode_modifier.d && i.reg_operands == i.operands |
64c49ab3 JB |
5841 | && !operand_type_all_zero (&overlap1)) |
5842 | switch (i.dir_encoding) | |
5843 | { | |
5844 | case dir_encoding_load: | |
5845 | if (operand_type_check (operand_types[i.operands - 1], anymem) | |
5846 | || operand_types[i.operands - 1].bitfield.regmem) | |
5847 | goto check_reverse; | |
5848 | break; | |
5849 | ||
5850 | case dir_encoding_store: | |
5851 | if (!operand_type_check (operand_types[i.operands - 1], anymem) | |
5852 | && !operand_types[i.operands - 1].bitfield.regmem) | |
5853 | goto check_reverse; | |
5854 | break; | |
5855 | ||
5856 | case dir_encoding_swap: | |
5857 | goto check_reverse; | |
5858 | ||
5859 | case dir_encoding_default: | |
5860 | break; | |
5861 | } | |
86fa6981 | 5862 | /* If we want store form, we skip the current load. */ |
64c49ab3 JB |
5863 | if ((i.dir_encoding == dir_encoding_store |
5864 | || i.dir_encoding == dir_encoding_swap) | |
86fa6981 L |
5865 | && i.mem_operands == 0 |
5866 | && t->opcode_modifier.load) | |
fa99fab2 | 5867 | continue; |
1a0670f3 | 5868 | /* Fall through. */ |
f48ff2ae | 5869 | case 4: |
c0f3af97 | 5870 | case 5: |
c6fb90c8 | 5871 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
5872 | if (!operand_type_match (overlap0, i.types[0]) |
5873 | || !operand_type_match (overlap1, i.types[1]) | |
e2195274 | 5874 | || ((check_register & 3) == 3 |
dc821c5f | 5875 | && !operand_type_register_match (i.types[0], |
40fb9820 | 5876 | operand_types[0], |
dc821c5f | 5877 | i.types[1], |
40fb9820 | 5878 | operand_types[1]))) |
29b0f896 AM |
5879 | { |
5880 | /* Check if other direction is valid ... */ | |
38e314eb | 5881 | if (!t->opcode_modifier.d) |
29b0f896 AM |
5882 | continue; |
5883 | ||
b6169b20 | 5884 | check_reverse: |
3ac21baa JB |
5885 | if (!(size_match & MATCH_REVERSE)) |
5886 | continue; | |
29b0f896 | 5887 | /* Try reversing direction of operands. */ |
f5eb1d70 JB |
5888 | overlap0 = operand_type_and (i.types[0], operand_types[i.operands - 1]); |
5889 | overlap1 = operand_type_and (i.types[i.operands - 1], operand_types[0]); | |
40fb9820 | 5890 | if (!operand_type_match (overlap0, i.types[0]) |
f5eb1d70 | 5891 | || !operand_type_match (overlap1, i.types[i.operands - 1]) |
45664ddb | 5892 | || (check_register |
dc821c5f | 5893 | && !operand_type_register_match (i.types[0], |
f5eb1d70 JB |
5894 | operand_types[i.operands - 1], |
5895 | i.types[i.operands - 1], | |
45664ddb | 5896 | operand_types[0]))) |
29b0f896 AM |
5897 | { |
5898 | /* Does not match either direction. */ | |
5899 | continue; | |
5900 | } | |
38e314eb | 5901 | /* found_reverse_match holds which of D or FloatR |
29b0f896 | 5902 | we've found. */ |
38e314eb JB |
5903 | if (!t->opcode_modifier.d) |
5904 | found_reverse_match = 0; | |
5905 | else if (operand_types[0].bitfield.tbyte) | |
8a2ed489 | 5906 | found_reverse_match = Opcode_FloatD; |
dbbc8b7e | 5907 | else if (operand_types[0].bitfield.xmmword |
f5eb1d70 | 5908 | || operand_types[i.operands - 1].bitfield.xmmword |
dbbc8b7e | 5909 | || operand_types[0].bitfield.regmmx |
f5eb1d70 | 5910 | || operand_types[i.operands - 1].bitfield.regmmx |
dbbc8b7e JB |
5911 | || is_any_vex_encoding(t)) |
5912 | found_reverse_match = (t->base_opcode & 0xee) != 0x6e | |
5913 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
8a2ed489 | 5914 | else |
38e314eb | 5915 | found_reverse_match = Opcode_D; |
40fb9820 | 5916 | if (t->opcode_modifier.floatr) |
8a2ed489 | 5917 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 5918 | } |
f48ff2ae | 5919 | else |
29b0f896 | 5920 | { |
f48ff2ae | 5921 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
5922 | switch (t->operands) |
5923 | { | |
c0f3af97 L |
5924 | case 5: |
5925 | overlap4 = operand_type_and (i.types[4], | |
5926 | operand_types[4]); | |
1a0670f3 | 5927 | /* Fall through. */ |
d1cbb4db | 5928 | case 4: |
c6fb90c8 L |
5929 | overlap3 = operand_type_and (i.types[3], |
5930 | operand_types[3]); | |
1a0670f3 | 5931 | /* Fall through. */ |
d1cbb4db | 5932 | case 3: |
c6fb90c8 L |
5933 | overlap2 = operand_type_and (i.types[2], |
5934 | operand_types[2]); | |
d1cbb4db L |
5935 | break; |
5936 | } | |
29b0f896 | 5937 | |
f48ff2ae L |
5938 | switch (t->operands) |
5939 | { | |
c0f3af97 L |
5940 | case 5: |
5941 | if (!operand_type_match (overlap4, i.types[4]) | |
dc821c5f | 5942 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 5943 | operand_types[3], |
c0f3af97 L |
5944 | i.types[4], |
5945 | operand_types[4])) | |
5946 | continue; | |
1a0670f3 | 5947 | /* Fall through. */ |
f48ff2ae | 5948 | case 4: |
40fb9820 | 5949 | if (!operand_type_match (overlap3, i.types[3]) |
e2195274 JB |
5950 | || ((check_register & 0xa) == 0xa |
5951 | && !operand_type_register_match (i.types[1], | |
f7768225 JB |
5952 | operand_types[1], |
5953 | i.types[3], | |
e2195274 JB |
5954 | operand_types[3])) |
5955 | || ((check_register & 0xc) == 0xc | |
5956 | && !operand_type_register_match (i.types[2], | |
5957 | operand_types[2], | |
5958 | i.types[3], | |
5959 | operand_types[3]))) | |
f48ff2ae | 5960 | continue; |
1a0670f3 | 5961 | /* Fall through. */ |
f48ff2ae L |
5962 | case 3: |
5963 | /* Here we make use of the fact that there are no | |
23e42951 | 5964 | reverse match 3 operand instructions. */ |
40fb9820 | 5965 | if (!operand_type_match (overlap2, i.types[2]) |
e2195274 JB |
5966 | || ((check_register & 5) == 5 |
5967 | && !operand_type_register_match (i.types[0], | |
23e42951 JB |
5968 | operand_types[0], |
5969 | i.types[2], | |
e2195274 JB |
5970 | operand_types[2])) |
5971 | || ((check_register & 6) == 6 | |
5972 | && !operand_type_register_match (i.types[1], | |
5973 | operand_types[1], | |
5974 | i.types[2], | |
5975 | operand_types[2]))) | |
f48ff2ae L |
5976 | continue; |
5977 | break; | |
5978 | } | |
29b0f896 | 5979 | } |
f48ff2ae | 5980 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
5981 | slip through to break. */ |
5982 | } | |
3629bb00 | 5983 | if (!found_cpu_match) |
dbbc8b7e | 5984 | continue; |
c0f3af97 | 5985 | |
5614d22c JB |
5986 | /* Check if vector and VEX operands are valid. */ |
5987 | if (check_VecOperands (t) || VEX_check_operands (t)) | |
5988 | { | |
5989 | specific_error = i.error; | |
5990 | continue; | |
5991 | } | |
a683cc34 | 5992 | |
29b0f896 AM |
5993 | /* We've found a match; break out of loop. */ |
5994 | break; | |
5995 | } | |
5996 | ||
5997 | if (t == current_templates->end) | |
5998 | { | |
5999 | /* We found no match. */ | |
a65babc9 | 6000 | const char *err_msg; |
5614d22c | 6001 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
6002 | { |
6003 | default: | |
6004 | abort (); | |
86e026a4 | 6005 | case operand_size_mismatch: |
a65babc9 L |
6006 | err_msg = _("operand size mismatch"); |
6007 | break; | |
6008 | case operand_type_mismatch: | |
6009 | err_msg = _("operand type mismatch"); | |
6010 | break; | |
6011 | case register_type_mismatch: | |
6012 | err_msg = _("register type mismatch"); | |
6013 | break; | |
6014 | case number_of_operands_mismatch: | |
6015 | err_msg = _("number of operands mismatch"); | |
6016 | break; | |
6017 | case invalid_instruction_suffix: | |
6018 | err_msg = _("invalid instruction suffix"); | |
6019 | break; | |
6020 | case bad_imm4: | |
4a2608e3 | 6021 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 | 6022 | break; |
a65babc9 L |
6023 | case unsupported_with_intel_mnemonic: |
6024 | err_msg = _("unsupported with Intel mnemonic"); | |
6025 | break; | |
6026 | case unsupported_syntax: | |
6027 | err_msg = _("unsupported syntax"); | |
6028 | break; | |
6029 | case unsupported: | |
35262a23 | 6030 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
6031 | current_templates->start->name); |
6032 | return NULL; | |
6c30d220 L |
6033 | case invalid_vsib_address: |
6034 | err_msg = _("invalid VSIB address"); | |
6035 | break; | |
7bab8ab5 JB |
6036 | case invalid_vector_register_set: |
6037 | err_msg = _("mask, index, and destination registers must be distinct"); | |
6038 | break; | |
6c30d220 L |
6039 | case unsupported_vector_index_register: |
6040 | err_msg = _("unsupported vector index register"); | |
6041 | break; | |
43234a1e L |
6042 | case unsupported_broadcast: |
6043 | err_msg = _("unsupported broadcast"); | |
6044 | break; | |
43234a1e L |
6045 | case broadcast_needed: |
6046 | err_msg = _("broadcast is needed for operand of such type"); | |
6047 | break; | |
6048 | case unsupported_masking: | |
6049 | err_msg = _("unsupported masking"); | |
6050 | break; | |
6051 | case mask_not_on_destination: | |
6052 | err_msg = _("mask not on destination operand"); | |
6053 | break; | |
6054 | case no_default_mask: | |
6055 | err_msg = _("default mask isn't allowed"); | |
6056 | break; | |
6057 | case unsupported_rc_sae: | |
6058 | err_msg = _("unsupported static rounding/sae"); | |
6059 | break; | |
6060 | case rc_sae_operand_not_last_imm: | |
6061 | if (intel_syntax) | |
6062 | err_msg = _("RC/SAE operand must precede immediate operands"); | |
6063 | else | |
6064 | err_msg = _("RC/SAE operand must follow immediate operands"); | |
6065 | break; | |
6066 | case invalid_register_operand: | |
6067 | err_msg = _("invalid register operand"); | |
6068 | break; | |
a65babc9 L |
6069 | } |
6070 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 6071 | current_templates->start->name); |
fa99fab2 | 6072 | return NULL; |
29b0f896 | 6073 | } |
252b5132 | 6074 | |
29b0f896 AM |
6075 | if (!quiet_warnings) |
6076 | { | |
6077 | if (!intel_syntax | |
40fb9820 L |
6078 | && (i.types[0].bitfield.jumpabsolute |
6079 | != operand_types[0].bitfield.jumpabsolute)) | |
29b0f896 AM |
6080 | { |
6081 | as_warn (_("indirect %s without `*'"), t->name); | |
6082 | } | |
6083 | ||
40fb9820 L |
6084 | if (t->opcode_modifier.isprefix |
6085 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
6086 | { |
6087 | /* Warn them that a data or address size prefix doesn't | |
6088 | affect assembly of the next line of code. */ | |
6089 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
6090 | } | |
6091 | } | |
6092 | ||
6093 | /* Copy the template we found. */ | |
6094 | i.tm = *t; | |
539e75ad L |
6095 | |
6096 | if (addr_prefix_disp != -1) | |
6097 | i.tm.operand_types[addr_prefix_disp] | |
6098 | = operand_types[addr_prefix_disp]; | |
6099 | ||
29b0f896 AM |
6100 | if (found_reverse_match) |
6101 | { | |
6102 | /* If we found a reverse match we must alter the opcode | |
6103 | direction bit. found_reverse_match holds bits to change | |
6104 | (different for int & float insns). */ | |
6105 | ||
6106 | i.tm.base_opcode ^= found_reverse_match; | |
6107 | ||
f5eb1d70 JB |
6108 | i.tm.operand_types[0] = operand_types[i.operands - 1]; |
6109 | i.tm.operand_types[i.operands - 1] = operand_types[0]; | |
29b0f896 AM |
6110 | } |
6111 | ||
fa99fab2 | 6112 | return t; |
29b0f896 AM |
6113 | } |
6114 | ||
6115 | static int | |
e3bb37b5 | 6116 | check_string (void) |
29b0f896 | 6117 | { |
40fb9820 L |
6118 | int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; |
6119 | if (i.tm.operand_types[mem_op].bitfield.esseg) | |
29b0f896 AM |
6120 | { |
6121 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
6122 | { | |
a87af027 | 6123 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 6124 | i.tm.name, |
a87af027 JB |
6125 | mem_op + 1, |
6126 | register_prefix); | |
29b0f896 AM |
6127 | return 0; |
6128 | } | |
6129 | /* There's only ever one segment override allowed per instruction. | |
6130 | This instruction possibly has a legal segment override on the | |
6131 | second operand, so copy the segment to where non-string | |
6132 | instructions store it, allowing common code. */ | |
6133 | i.seg[0] = i.seg[1]; | |
6134 | } | |
40fb9820 | 6135 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
29b0f896 AM |
6136 | { |
6137 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
6138 | { | |
a87af027 | 6139 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 6140 | i.tm.name, |
a87af027 JB |
6141 | mem_op + 2, |
6142 | register_prefix); | |
29b0f896 AM |
6143 | return 0; |
6144 | } | |
6145 | } | |
6146 | return 1; | |
6147 | } | |
6148 | ||
6149 | static int | |
543613e9 | 6150 | process_suffix (void) |
29b0f896 AM |
6151 | { |
6152 | /* If matched instruction specifies an explicit instruction mnemonic | |
6153 | suffix, use it. */ | |
673fe0f0 | 6154 | if (i.tm.opcode_modifier.size == SIZE16) |
40fb9820 | 6155 | i.suffix = WORD_MNEM_SUFFIX; |
673fe0f0 | 6156 | else if (i.tm.opcode_modifier.size == SIZE32) |
40fb9820 | 6157 | i.suffix = LONG_MNEM_SUFFIX; |
673fe0f0 | 6158 | else if (i.tm.opcode_modifier.size == SIZE64) |
40fb9820 | 6159 | i.suffix = QWORD_MNEM_SUFFIX; |
29b0f896 AM |
6160 | else if (i.reg_operands) |
6161 | { | |
6162 | /* If there's no instruction mnemonic suffix we try to invent one | |
6163 | based on register operands. */ | |
6164 | if (!i.suffix) | |
6165 | { | |
6166 | /* We take i.suffix from the last register operand specified, | |
6167 | Destination register type is more significant than source | |
381d071f L |
6168 | register type. crc32 in SSE4.2 prefers source register |
6169 | type. */ | |
556059dd | 6170 | if (i.tm.base_opcode == 0xf20f38f0 && i.types[0].bitfield.reg) |
381d071f | 6171 | { |
556059dd JB |
6172 | if (i.types[0].bitfield.byte) |
6173 | i.suffix = BYTE_MNEM_SUFFIX; | |
6174 | else if (i.types[0].bitfield.word) | |
40fb9820 | 6175 | i.suffix = WORD_MNEM_SUFFIX; |
556059dd | 6176 | else if (i.types[0].bitfield.dword) |
40fb9820 | 6177 | i.suffix = LONG_MNEM_SUFFIX; |
556059dd | 6178 | else if (i.types[0].bitfield.qword) |
40fb9820 | 6179 | i.suffix = QWORD_MNEM_SUFFIX; |
381d071f L |
6180 | } |
6181 | ||
6182 | if (!i.suffix) | |
6183 | { | |
6184 | int op; | |
6185 | ||
556059dd | 6186 | if (i.tm.base_opcode == 0xf20f38f0) |
20592a94 L |
6187 | { |
6188 | /* We have to know the operand size for crc32. */ | |
6189 | as_bad (_("ambiguous memory operand size for `%s`"), | |
6190 | i.tm.name); | |
6191 | return 0; | |
6192 | } | |
6193 | ||
381d071f | 6194 | for (op = i.operands; --op >= 0;) |
b76bc5d5 JB |
6195 | if (!i.tm.operand_types[op].bitfield.inoutportreg |
6196 | && !i.tm.operand_types[op].bitfield.shiftcount) | |
381d071f | 6197 | { |
8819ada6 JB |
6198 | if (!i.types[op].bitfield.reg) |
6199 | continue; | |
6200 | if (i.types[op].bitfield.byte) | |
6201 | i.suffix = BYTE_MNEM_SUFFIX; | |
6202 | else if (i.types[op].bitfield.word) | |
6203 | i.suffix = WORD_MNEM_SUFFIX; | |
6204 | else if (i.types[op].bitfield.dword) | |
6205 | i.suffix = LONG_MNEM_SUFFIX; | |
6206 | else if (i.types[op].bitfield.qword) | |
6207 | i.suffix = QWORD_MNEM_SUFFIX; | |
6208 | else | |
6209 | continue; | |
6210 | break; | |
381d071f L |
6211 | } |
6212 | } | |
29b0f896 AM |
6213 | } |
6214 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
6215 | { | |
2eb952a4 L |
6216 | if (intel_syntax |
6217 | && i.tm.opcode_modifier.ignoresize | |
6218 | && i.tm.opcode_modifier.no_bsuf) | |
6219 | i.suffix = 0; | |
6220 | else if (!check_byte_reg ()) | |
29b0f896 AM |
6221 | return 0; |
6222 | } | |
6223 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
6224 | { | |
2eb952a4 L |
6225 | if (intel_syntax |
6226 | && i.tm.opcode_modifier.ignoresize | |
9f123b91 JB |
6227 | && i.tm.opcode_modifier.no_lsuf |
6228 | && !i.tm.opcode_modifier.todword | |
6229 | && !i.tm.opcode_modifier.toqword) | |
2eb952a4 L |
6230 | i.suffix = 0; |
6231 | else if (!check_long_reg ()) | |
29b0f896 AM |
6232 | return 0; |
6233 | } | |
6234 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6235 | { | |
955e1e6a L |
6236 | if (intel_syntax |
6237 | && i.tm.opcode_modifier.ignoresize | |
9f123b91 JB |
6238 | && i.tm.opcode_modifier.no_qsuf |
6239 | && !i.tm.opcode_modifier.todword | |
6240 | && !i.tm.opcode_modifier.toqword) | |
955e1e6a L |
6241 | i.suffix = 0; |
6242 | else if (!check_qword_reg ()) | |
29b0f896 AM |
6243 | return 0; |
6244 | } | |
6245 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6246 | { | |
2eb952a4 L |
6247 | if (intel_syntax |
6248 | && i.tm.opcode_modifier.ignoresize | |
6249 | && i.tm.opcode_modifier.no_wsuf) | |
6250 | i.suffix = 0; | |
6251 | else if (!check_word_reg ()) | |
29b0f896 AM |
6252 | return 0; |
6253 | } | |
40fb9820 | 6254 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
6255 | /* Do nothing if the instruction is going to ignore the prefix. */ |
6256 | ; | |
6257 | else | |
6258 | abort (); | |
6259 | } | |
40fb9820 | 6260 | else if (i.tm.opcode_modifier.defaultsize |
9306ca4a JB |
6261 | && !i.suffix |
6262 | /* exclude fldenv/frstor/fsave/fstenv */ | |
40fb9820 | 6263 | && i.tm.opcode_modifier.no_ssuf) |
29b0f896 | 6264 | { |
06f74c5c L |
6265 | if (stackop_size == LONG_MNEM_SUFFIX |
6266 | && i.tm.base_opcode == 0xcf) | |
6267 | { | |
6268 | /* stackop_size is set to LONG_MNEM_SUFFIX for the | |
6269 | .code16gcc directive to support 16-bit mode with | |
6270 | 32-bit address. For IRET without a suffix, generate | |
6271 | 16-bit IRET (opcode 0xcf) to return from an interrupt | |
6272 | handler. */ | |
6273 | i.suffix = WORD_MNEM_SUFFIX; | |
6274 | as_warn (_("generating 16-bit `iret' for .code16gcc directive")); | |
6275 | } | |
6276 | else | |
6277 | i.suffix = stackop_size; | |
29b0f896 | 6278 | } |
9306ca4a JB |
6279 | else if (intel_syntax |
6280 | && !i.suffix | |
40fb9820 L |
6281 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
6282 | || i.tm.opcode_modifier.jumpbyte | |
6283 | || i.tm.opcode_modifier.jumpintersegment | |
64e74474 AM |
6284 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
6285 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
6286 | { |
6287 | switch (flag_code) | |
6288 | { | |
6289 | case CODE_64BIT: | |
40fb9820 | 6290 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
6291 | { |
6292 | i.suffix = QWORD_MNEM_SUFFIX; | |
6293 | break; | |
6294 | } | |
1a0670f3 | 6295 | /* Fall through. */ |
9306ca4a | 6296 | case CODE_32BIT: |
40fb9820 | 6297 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
6298 | i.suffix = LONG_MNEM_SUFFIX; |
6299 | break; | |
6300 | case CODE_16BIT: | |
40fb9820 | 6301 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
6302 | i.suffix = WORD_MNEM_SUFFIX; |
6303 | break; | |
6304 | } | |
6305 | } | |
252b5132 | 6306 | |
9306ca4a | 6307 | if (!i.suffix) |
29b0f896 | 6308 | { |
9306ca4a JB |
6309 | if (!intel_syntax) |
6310 | { | |
40fb9820 | 6311 | if (i.tm.opcode_modifier.w) |
9306ca4a | 6312 | { |
4eed87de AM |
6313 | as_bad (_("no instruction mnemonic suffix given and " |
6314 | "no register operands; can't size instruction")); | |
9306ca4a JB |
6315 | return 0; |
6316 | } | |
6317 | } | |
6318 | else | |
6319 | { | |
40fb9820 | 6320 | unsigned int suffixes; |
7ab9ffdd | 6321 | |
40fb9820 L |
6322 | suffixes = !i.tm.opcode_modifier.no_bsuf; |
6323 | if (!i.tm.opcode_modifier.no_wsuf) | |
6324 | suffixes |= 1 << 1; | |
6325 | if (!i.tm.opcode_modifier.no_lsuf) | |
6326 | suffixes |= 1 << 2; | |
fc4adea1 | 6327 | if (!i.tm.opcode_modifier.no_ldsuf) |
40fb9820 L |
6328 | suffixes |= 1 << 3; |
6329 | if (!i.tm.opcode_modifier.no_ssuf) | |
6330 | suffixes |= 1 << 4; | |
c2b9da16 | 6331 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) |
40fb9820 L |
6332 | suffixes |= 1 << 5; |
6333 | ||
6334 | /* There are more than suffix matches. */ | |
6335 | if (i.tm.opcode_modifier.w | |
9306ca4a | 6336 | || ((suffixes & (suffixes - 1)) |
40fb9820 L |
6337 | && !i.tm.opcode_modifier.defaultsize |
6338 | && !i.tm.opcode_modifier.ignoresize)) | |
9306ca4a JB |
6339 | { |
6340 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
6341 | return 0; | |
6342 | } | |
6343 | } | |
29b0f896 | 6344 | } |
252b5132 | 6345 | |
d2224064 JB |
6346 | /* Change the opcode based on the operand size given by i.suffix. */ |
6347 | switch (i.suffix) | |
29b0f896 | 6348 | { |
d2224064 JB |
6349 | /* Size floating point instruction. */ |
6350 | case LONG_MNEM_SUFFIX: | |
6351 | if (i.tm.opcode_modifier.floatmf) | |
6352 | { | |
6353 | i.tm.base_opcode ^= 4; | |
6354 | break; | |
6355 | } | |
6356 | /* fall through */ | |
6357 | case WORD_MNEM_SUFFIX: | |
6358 | case QWORD_MNEM_SUFFIX: | |
29b0f896 | 6359 | /* It's not a byte, select word/dword operation. */ |
40fb9820 | 6360 | if (i.tm.opcode_modifier.w) |
29b0f896 | 6361 | { |
40fb9820 | 6362 | if (i.tm.opcode_modifier.shortform) |
29b0f896 AM |
6363 | i.tm.base_opcode |= 8; |
6364 | else | |
6365 | i.tm.base_opcode |= 1; | |
6366 | } | |
d2224064 JB |
6367 | /* fall through */ |
6368 | case SHORT_MNEM_SUFFIX: | |
29b0f896 AM |
6369 | /* Now select between word & dword operations via the operand |
6370 | size prefix, except for instructions that will ignore this | |
6371 | prefix anyway. */ | |
75c0a438 L |
6372 | if (i.reg_operands > 0 |
6373 | && i.types[0].bitfield.reg | |
6374 | && i.tm.opcode_modifier.addrprefixopreg | |
6375 | && (i.tm.opcode_modifier.immext | |
6376 | || i.operands == 1)) | |
cb712a9e | 6377 | { |
ca61edf2 L |
6378 | /* The address size override prefix changes the size of the |
6379 | first operand. */ | |
40fb9820 | 6380 | if ((flag_code == CODE_32BIT |
75c0a438 | 6381 | && i.op[0].regs->reg_type.bitfield.word) |
40fb9820 | 6382 | || (flag_code != CODE_32BIT |
75c0a438 | 6383 | && i.op[0].regs->reg_type.bitfield.dword)) |
cb712a9e L |
6384 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
6385 | return 0; | |
6386 | } | |
6387 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
40fb9820 L |
6388 | && !i.tm.opcode_modifier.ignoresize |
6389 | && !i.tm.opcode_modifier.floatmf | |
a38d7118 | 6390 | && !is_any_vex_encoding (&i.tm) |
cb712a9e L |
6391 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
6392 | || (flag_code == CODE_64BIT | |
40fb9820 | 6393 | && i.tm.opcode_modifier.jumpbyte))) |
24eab124 AM |
6394 | { |
6395 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 6396 | |
40fb9820 | 6397 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
29b0f896 | 6398 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 6399 | |
29b0f896 AM |
6400 | if (!add_prefix (prefix)) |
6401 | return 0; | |
24eab124 | 6402 | } |
252b5132 | 6403 | |
29b0f896 AM |
6404 | /* Set mode64 for an operand. */ |
6405 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 6406 | && flag_code == CODE_64BIT |
d2224064 | 6407 | && !i.tm.opcode_modifier.norex64 |
46e883c5 | 6408 | /* Special case for xchg %rax,%rax. It is NOP and doesn't |
d2224064 JB |
6409 | need rex64. */ |
6410 | && ! (i.operands == 2 | |
6411 | && i.tm.base_opcode == 0x90 | |
6412 | && i.tm.extension_opcode == None | |
2c703856 JB |
6413 | && i.types[0].bitfield.acc && i.types[0].bitfield.qword |
6414 | && i.types[1].bitfield.acc && i.types[1].bitfield.qword)) | |
d2224064 | 6415 | i.rex |= REX_W; |
3e73aa7c | 6416 | |
d2224064 | 6417 | break; |
29b0f896 | 6418 | } |
7ecd2f8b | 6419 | |
c0a30a9f L |
6420 | if (i.reg_operands != 0 |
6421 | && i.operands > 1 | |
6422 | && i.tm.opcode_modifier.addrprefixopreg | |
6423 | && !i.tm.opcode_modifier.immext) | |
6424 | { | |
6425 | /* Check invalid register operand when the address size override | |
6426 | prefix changes the size of register operands. */ | |
6427 | unsigned int op; | |
6428 | enum { need_word, need_dword, need_qword } need; | |
6429 | ||
6430 | if (flag_code == CODE_32BIT) | |
6431 | need = i.prefix[ADDR_PREFIX] ? need_word : need_dword; | |
6432 | else | |
6433 | { | |
6434 | if (i.prefix[ADDR_PREFIX]) | |
6435 | need = need_dword; | |
6436 | else | |
6437 | need = flag_code == CODE_64BIT ? need_qword : need_word; | |
6438 | } | |
6439 | ||
6440 | for (op = 0; op < i.operands; op++) | |
6441 | if (i.types[op].bitfield.reg | |
6442 | && ((need == need_word | |
6443 | && !i.op[op].regs->reg_type.bitfield.word) | |
6444 | || (need == need_dword | |
6445 | && !i.op[op].regs->reg_type.bitfield.dword) | |
6446 | || (need == need_qword | |
6447 | && !i.op[op].regs->reg_type.bitfield.qword))) | |
6448 | { | |
6449 | as_bad (_("invalid register operand size for `%s'"), | |
6450 | i.tm.name); | |
6451 | return 0; | |
6452 | } | |
6453 | } | |
6454 | ||
29b0f896 AM |
6455 | return 1; |
6456 | } | |
3e73aa7c | 6457 | |
29b0f896 | 6458 | static int |
543613e9 | 6459 | check_byte_reg (void) |
29b0f896 AM |
6460 | { |
6461 | int op; | |
543613e9 | 6462 | |
29b0f896 AM |
6463 | for (op = i.operands; --op >= 0;) |
6464 | { | |
dc821c5f JB |
6465 | /* Skip non-register operands. */ |
6466 | if (!i.types[op].bitfield.reg) | |
6467 | continue; | |
6468 | ||
29b0f896 AM |
6469 | /* If this is an eight bit register, it's OK. If it's the 16 or |
6470 | 32 bit version of an eight bit register, we will just use the | |
6471 | low portion, and that's OK too. */ | |
dc821c5f | 6472 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
6473 | continue; |
6474 | ||
5a819eb9 JB |
6475 | /* I/O port address operands are OK too. */ |
6476 | if (i.tm.operand_types[op].bitfield.inoutportreg) | |
6477 | continue; | |
6478 | ||
9344ff29 L |
6479 | /* crc32 doesn't generate this warning. */ |
6480 | if (i.tm.base_opcode == 0xf20f38f0) | |
6481 | continue; | |
6482 | ||
dc821c5f JB |
6483 | if ((i.types[op].bitfield.word |
6484 | || i.types[op].bitfield.dword | |
6485 | || i.types[op].bitfield.qword) | |
5a819eb9 JB |
6486 | && i.op[op].regs->reg_num < 4 |
6487 | /* Prohibit these changes in 64bit mode, since the lowering | |
6488 | would be more complicated. */ | |
6489 | && flag_code != CODE_64BIT) | |
29b0f896 | 6490 | { |
29b0f896 | 6491 | #if REGISTER_WARNINGS |
5a819eb9 | 6492 | if (!quiet_warnings) |
a540244d L |
6493 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6494 | register_prefix, | |
dc821c5f | 6495 | (i.op[op].regs + (i.types[op].bitfield.word |
29b0f896 AM |
6496 | ? REGNAM_AL - REGNAM_AX |
6497 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
a540244d | 6498 | register_prefix, |
29b0f896 AM |
6499 | i.op[op].regs->reg_name, |
6500 | i.suffix); | |
6501 | #endif | |
6502 | continue; | |
6503 | } | |
6504 | /* Any other register is bad. */ | |
dc821c5f | 6505 | if (i.types[op].bitfield.reg |
40fb9820 | 6506 | || i.types[op].bitfield.regmmx |
1b54b8d7 | 6507 | || i.types[op].bitfield.regsimd |
40fb9820 L |
6508 | || i.types[op].bitfield.sreg2 |
6509 | || i.types[op].bitfield.sreg3 | |
6510 | || i.types[op].bitfield.control | |
6511 | || i.types[op].bitfield.debug | |
ca0d63fe | 6512 | || i.types[op].bitfield.test) |
29b0f896 | 6513 | { |
a540244d L |
6514 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6515 | register_prefix, | |
29b0f896 AM |
6516 | i.op[op].regs->reg_name, |
6517 | i.tm.name, | |
6518 | i.suffix); | |
6519 | return 0; | |
6520 | } | |
6521 | } | |
6522 | return 1; | |
6523 | } | |
6524 | ||
6525 | static int | |
e3bb37b5 | 6526 | check_long_reg (void) |
29b0f896 AM |
6527 | { |
6528 | int op; | |
6529 | ||
6530 | for (op = i.operands; --op >= 0;) | |
dc821c5f JB |
6531 | /* Skip non-register operands. */ |
6532 | if (!i.types[op].bitfield.reg) | |
6533 | continue; | |
29b0f896 AM |
6534 | /* Reject eight bit registers, except where the template requires |
6535 | them. (eg. movzb) */ | |
dc821c5f JB |
6536 | else if (i.types[op].bitfield.byte |
6537 | && (i.tm.operand_types[op].bitfield.reg | |
6538 | || i.tm.operand_types[op].bitfield.acc) | |
6539 | && (i.tm.operand_types[op].bitfield.word | |
6540 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6541 | { |
a540244d L |
6542 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6543 | register_prefix, | |
29b0f896 AM |
6544 | i.op[op].regs->reg_name, |
6545 | i.tm.name, | |
6546 | i.suffix); | |
6547 | return 0; | |
6548 | } | |
e4630f71 | 6549 | /* Warn if the e prefix on a general reg is missing. */ |
29b0f896 | 6550 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
dc821c5f JB |
6551 | && i.types[op].bitfield.word |
6552 | && (i.tm.operand_types[op].bitfield.reg | |
6553 | || i.tm.operand_types[op].bitfield.acc) | |
6554 | && i.tm.operand_types[op].bitfield.dword) | |
29b0f896 AM |
6555 | { |
6556 | /* Prohibit these changes in the 64bit mode, since the | |
6557 | lowering is more complicated. */ | |
6558 | if (flag_code == CODE_64BIT) | |
252b5132 | 6559 | { |
2b5d6a91 | 6560 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 6561 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
6562 | i.suffix); |
6563 | return 0; | |
252b5132 | 6564 | } |
29b0f896 | 6565 | #if REGISTER_WARNINGS |
cecf1424 JB |
6566 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6567 | register_prefix, | |
6568 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, | |
6569 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 | 6570 | #endif |
252b5132 | 6571 | } |
e4630f71 | 6572 | /* Warn if the r prefix on a general reg is present. */ |
dc821c5f JB |
6573 | else if (i.types[op].bitfield.qword |
6574 | && (i.tm.operand_types[op].bitfield.reg | |
6575 | || i.tm.operand_types[op].bitfield.acc) | |
6576 | && i.tm.operand_types[op].bitfield.dword) | |
252b5132 | 6577 | { |
34828aad | 6578 | if (intel_syntax |
ca61edf2 | 6579 | && i.tm.opcode_modifier.toqword |
1b54b8d7 | 6580 | && !i.types[0].bitfield.regsimd) |
34828aad | 6581 | { |
ca61edf2 | 6582 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
6583 | i.suffix = QWORD_MNEM_SUFFIX; |
6584 | } | |
6585 | else | |
6586 | { | |
2b5d6a91 | 6587 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6588 | register_prefix, i.op[op].regs->reg_name, |
6589 | i.suffix); | |
6590 | return 0; | |
6591 | } | |
29b0f896 AM |
6592 | } |
6593 | return 1; | |
6594 | } | |
252b5132 | 6595 | |
29b0f896 | 6596 | static int |
e3bb37b5 | 6597 | check_qword_reg (void) |
29b0f896 AM |
6598 | { |
6599 | int op; | |
252b5132 | 6600 | |
29b0f896 | 6601 | for (op = i.operands; --op >= 0; ) |
dc821c5f JB |
6602 | /* Skip non-register operands. */ |
6603 | if (!i.types[op].bitfield.reg) | |
6604 | continue; | |
29b0f896 AM |
6605 | /* Reject eight bit registers, except where the template requires |
6606 | them. (eg. movzb) */ | |
dc821c5f JB |
6607 | else if (i.types[op].bitfield.byte |
6608 | && (i.tm.operand_types[op].bitfield.reg | |
6609 | || i.tm.operand_types[op].bitfield.acc) | |
6610 | && (i.tm.operand_types[op].bitfield.word | |
6611 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6612 | { |
a540244d L |
6613 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6614 | register_prefix, | |
29b0f896 AM |
6615 | i.op[op].regs->reg_name, |
6616 | i.tm.name, | |
6617 | i.suffix); | |
6618 | return 0; | |
6619 | } | |
e4630f71 | 6620 | /* Warn if the r prefix on a general reg is missing. */ |
dc821c5f JB |
6621 | else if ((i.types[op].bitfield.word |
6622 | || i.types[op].bitfield.dword) | |
6623 | && (i.tm.operand_types[op].bitfield.reg | |
6624 | || i.tm.operand_types[op].bitfield.acc) | |
6625 | && i.tm.operand_types[op].bitfield.qword) | |
29b0f896 AM |
6626 | { |
6627 | /* Prohibit these changes in the 64bit mode, since the | |
6628 | lowering is more complicated. */ | |
34828aad | 6629 | if (intel_syntax |
ca61edf2 | 6630 | && i.tm.opcode_modifier.todword |
1b54b8d7 | 6631 | && !i.types[0].bitfield.regsimd) |
34828aad | 6632 | { |
ca61edf2 | 6633 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
6634 | i.suffix = LONG_MNEM_SUFFIX; |
6635 | } | |
6636 | else | |
6637 | { | |
2b5d6a91 | 6638 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6639 | register_prefix, i.op[op].regs->reg_name, |
6640 | i.suffix); | |
6641 | return 0; | |
6642 | } | |
252b5132 | 6643 | } |
29b0f896 AM |
6644 | return 1; |
6645 | } | |
252b5132 | 6646 | |
29b0f896 | 6647 | static int |
e3bb37b5 | 6648 | check_word_reg (void) |
29b0f896 AM |
6649 | { |
6650 | int op; | |
6651 | for (op = i.operands; --op >= 0;) | |
dc821c5f JB |
6652 | /* Skip non-register operands. */ |
6653 | if (!i.types[op].bitfield.reg) | |
6654 | continue; | |
29b0f896 AM |
6655 | /* Reject eight bit registers, except where the template requires |
6656 | them. (eg. movzb) */ | |
dc821c5f JB |
6657 | else if (i.types[op].bitfield.byte |
6658 | && (i.tm.operand_types[op].bitfield.reg | |
6659 | || i.tm.operand_types[op].bitfield.acc) | |
6660 | && (i.tm.operand_types[op].bitfield.word | |
6661 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6662 | { |
a540244d L |
6663 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6664 | register_prefix, | |
29b0f896 AM |
6665 | i.op[op].regs->reg_name, |
6666 | i.tm.name, | |
6667 | i.suffix); | |
6668 | return 0; | |
6669 | } | |
e4630f71 | 6670 | /* Warn if the e or r prefix on a general reg is present. */ |
29b0f896 | 6671 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
dc821c5f JB |
6672 | && (i.types[op].bitfield.dword |
6673 | || i.types[op].bitfield.qword) | |
6674 | && (i.tm.operand_types[op].bitfield.reg | |
6675 | || i.tm.operand_types[op].bitfield.acc) | |
6676 | && i.tm.operand_types[op].bitfield.word) | |
252b5132 | 6677 | { |
29b0f896 AM |
6678 | /* Prohibit these changes in the 64bit mode, since the |
6679 | lowering is more complicated. */ | |
6680 | if (flag_code == CODE_64BIT) | |
252b5132 | 6681 | { |
2b5d6a91 | 6682 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 6683 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
6684 | i.suffix); |
6685 | return 0; | |
252b5132 | 6686 | } |
29b0f896 | 6687 | #if REGISTER_WARNINGS |
cecf1424 JB |
6688 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6689 | register_prefix, | |
6690 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, | |
6691 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 AM |
6692 | #endif |
6693 | } | |
6694 | return 1; | |
6695 | } | |
252b5132 | 6696 | |
29b0f896 | 6697 | static int |
40fb9820 | 6698 | update_imm (unsigned int j) |
29b0f896 | 6699 | { |
bc0844ae | 6700 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
6701 | if ((overlap.bitfield.imm8 |
6702 | || overlap.bitfield.imm8s | |
6703 | || overlap.bitfield.imm16 | |
6704 | || overlap.bitfield.imm32 | |
6705 | || overlap.bitfield.imm32s | |
6706 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
6707 | && !operand_type_equal (&overlap, &imm8) |
6708 | && !operand_type_equal (&overlap, &imm8s) | |
6709 | && !operand_type_equal (&overlap, &imm16) | |
6710 | && !operand_type_equal (&overlap, &imm32) | |
6711 | && !operand_type_equal (&overlap, &imm32s) | |
6712 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
6713 | { |
6714 | if (i.suffix) | |
6715 | { | |
40fb9820 L |
6716 | i386_operand_type temp; |
6717 | ||
0dfbf9d7 | 6718 | operand_type_set (&temp, 0); |
7ab9ffdd | 6719 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
6720 | { |
6721 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
6722 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
6723 | } | |
6724 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6725 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
6726 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6727 | { | |
6728 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
6729 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
6730 | } | |
6731 | else | |
6732 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
6733 | overlap = temp; | |
29b0f896 | 6734 | } |
0dfbf9d7 L |
6735 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
6736 | || operand_type_equal (&overlap, &imm16_32) | |
6737 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 6738 | { |
40fb9820 | 6739 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 6740 | overlap = imm16; |
40fb9820 | 6741 | else |
65da13b5 | 6742 | overlap = imm32s; |
29b0f896 | 6743 | } |
0dfbf9d7 L |
6744 | if (!operand_type_equal (&overlap, &imm8) |
6745 | && !operand_type_equal (&overlap, &imm8s) | |
6746 | && !operand_type_equal (&overlap, &imm16) | |
6747 | && !operand_type_equal (&overlap, &imm32) | |
6748 | && !operand_type_equal (&overlap, &imm32s) | |
6749 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 6750 | { |
4eed87de AM |
6751 | as_bad (_("no instruction mnemonic suffix given; " |
6752 | "can't determine immediate size")); | |
29b0f896 AM |
6753 | return 0; |
6754 | } | |
6755 | } | |
40fb9820 | 6756 | i.types[j] = overlap; |
29b0f896 | 6757 | |
40fb9820 L |
6758 | return 1; |
6759 | } | |
6760 | ||
6761 | static int | |
6762 | finalize_imm (void) | |
6763 | { | |
bc0844ae | 6764 | unsigned int j, n; |
29b0f896 | 6765 | |
bc0844ae L |
6766 | /* Update the first 2 immediate operands. */ |
6767 | n = i.operands > 2 ? 2 : i.operands; | |
6768 | if (n) | |
6769 | { | |
6770 | for (j = 0; j < n; j++) | |
6771 | if (update_imm (j) == 0) | |
6772 | return 0; | |
40fb9820 | 6773 | |
bc0844ae L |
6774 | /* The 3rd operand can't be immediate operand. */ |
6775 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
6776 | } | |
29b0f896 AM |
6777 | |
6778 | return 1; | |
6779 | } | |
6780 | ||
6781 | static int | |
e3bb37b5 | 6782 | process_operands (void) |
29b0f896 AM |
6783 | { |
6784 | /* Default segment register this instruction will use for memory | |
6785 | accesses. 0 means unknown. This is only for optimizing out | |
6786 | unnecessary segment overrides. */ | |
6787 | const seg_entry *default_seg = 0; | |
6788 | ||
2426c15f | 6789 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 6790 | { |
91d6fa6a NC |
6791 | unsigned int dupl = i.operands; |
6792 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
6793 | unsigned int j; |
6794 | ||
c0f3af97 | 6795 | /* The destination must be an xmm register. */ |
9c2799c2 | 6796 | gas_assert (i.reg_operands |
91d6fa6a | 6797 | && MAX_OPERANDS > dupl |
7ab9ffdd | 6798 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 6799 | |
1b54b8d7 JB |
6800 | if (i.tm.operand_types[0].bitfield.acc |
6801 | && i.tm.operand_types[0].bitfield.xmmword) | |
e2ec9d29 | 6802 | { |
8cd7925b | 6803 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
6804 | { |
6805 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
6806 | sources. */ | |
1b54b8d7 JB |
6807 | i.tm.operand_types[0].bitfield.acc = 0; |
6808 | i.tm.operand_types[0].bitfield.regsimd = 1; | |
c0f3af97 L |
6809 | goto duplicate; |
6810 | } | |
e2ec9d29 | 6811 | else |
c0f3af97 L |
6812 | { |
6813 | /* We remove the first xmm0 and keep the number of | |
6814 | operands unchanged, which in fact duplicates the | |
6815 | destination. */ | |
6816 | for (j = 1; j < i.operands; j++) | |
6817 | { | |
6818 | i.op[j - 1] = i.op[j]; | |
6819 | i.types[j - 1] = i.types[j]; | |
6820 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
6821 | } | |
6822 | } | |
6823 | } | |
6824 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 6825 | { |
91d6fa6a | 6826 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
6827 | && (i.tm.opcode_modifier.vexsources |
6828 | == VEX3SOURCES)); | |
c0f3af97 L |
6829 | |
6830 | /* Add the implicit xmm0 for instructions with VEX prefix | |
6831 | and 3 sources. */ | |
6832 | for (j = i.operands; j > 0; j--) | |
6833 | { | |
6834 | i.op[j] = i.op[j - 1]; | |
6835 | i.types[j] = i.types[j - 1]; | |
6836 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
6837 | } | |
6838 | i.op[0].regs | |
6839 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 6840 | i.types[0] = regxmm; |
c0f3af97 L |
6841 | i.tm.operand_types[0] = regxmm; |
6842 | ||
6843 | i.operands += 2; | |
6844 | i.reg_operands += 2; | |
6845 | i.tm.operands += 2; | |
6846 | ||
91d6fa6a | 6847 | dupl++; |
c0f3af97 | 6848 | dest++; |
91d6fa6a NC |
6849 | i.op[dupl] = i.op[dest]; |
6850 | i.types[dupl] = i.types[dest]; | |
6851 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
e2ec9d29 | 6852 | } |
c0f3af97 L |
6853 | else |
6854 | { | |
6855 | duplicate: | |
6856 | i.operands++; | |
6857 | i.reg_operands++; | |
6858 | i.tm.operands++; | |
6859 | ||
91d6fa6a NC |
6860 | i.op[dupl] = i.op[dest]; |
6861 | i.types[dupl] = i.types[dest]; | |
6862 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
c0f3af97 L |
6863 | } |
6864 | ||
6865 | if (i.tm.opcode_modifier.immext) | |
6866 | process_immext (); | |
6867 | } | |
1b54b8d7 JB |
6868 | else if (i.tm.operand_types[0].bitfield.acc |
6869 | && i.tm.operand_types[0].bitfield.xmmword) | |
c0f3af97 L |
6870 | { |
6871 | unsigned int j; | |
6872 | ||
9fcfb3d7 L |
6873 | for (j = 1; j < i.operands; j++) |
6874 | { | |
6875 | i.op[j - 1] = i.op[j]; | |
6876 | i.types[j - 1] = i.types[j]; | |
6877 | ||
6878 | /* We need to adjust fields in i.tm since they are used by | |
6879 | build_modrm_byte. */ | |
6880 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
6881 | } | |
6882 | ||
e2ec9d29 L |
6883 | i.operands--; |
6884 | i.reg_operands--; | |
e2ec9d29 L |
6885 | i.tm.operands--; |
6886 | } | |
920d2ddc IT |
6887 | else if (i.tm.opcode_modifier.implicitquadgroup) |
6888 | { | |
a477a8c4 JB |
6889 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
6890 | ||
920d2ddc | 6891 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
10c17abd | 6892 | gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd); |
a477a8c4 JB |
6893 | regnum = register_number (i.op[1].regs); |
6894 | first_reg_in_group = regnum & ~3; | |
6895 | last_reg_in_group = first_reg_in_group + 3; | |
6896 | if (regnum != first_reg_in_group) | |
6897 | as_warn (_("source register `%s%s' implicitly denotes" | |
6898 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), | |
6899 | register_prefix, i.op[1].regs->reg_name, | |
6900 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
6901 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
6902 | i.tm.name); | |
6903 | } | |
e2ec9d29 L |
6904 | else if (i.tm.opcode_modifier.regkludge) |
6905 | { | |
6906 | /* The imul $imm, %reg instruction is converted into | |
6907 | imul $imm, %reg, %reg, and the clr %reg instruction | |
6908 | is converted into xor %reg, %reg. */ | |
6909 | ||
6910 | unsigned int first_reg_op; | |
6911 | ||
6912 | if (operand_type_check (i.types[0], reg)) | |
6913 | first_reg_op = 0; | |
6914 | else | |
6915 | first_reg_op = 1; | |
6916 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 6917 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 6918 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
6919 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
6920 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
6921 | i.operands++; | |
6922 | i.reg_operands++; | |
29b0f896 AM |
6923 | } |
6924 | ||
40fb9820 | 6925 | if (i.tm.opcode_modifier.shortform) |
29b0f896 | 6926 | { |
40fb9820 L |
6927 | if (i.types[0].bitfield.sreg2 |
6928 | || i.types[0].bitfield.sreg3) | |
29b0f896 | 6929 | { |
4eed87de AM |
6930 | if (i.tm.base_opcode == POP_SEG_SHORT |
6931 | && i.op[0].regs->reg_num == 1) | |
29b0f896 | 6932 | { |
a87af027 | 6933 | as_bad (_("you can't `pop %scs'"), register_prefix); |
4eed87de | 6934 | return 0; |
29b0f896 | 6935 | } |
4eed87de AM |
6936 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
6937 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6938 | i.rex |= REX_B; |
4eed87de AM |
6939 | } |
6940 | else | |
6941 | { | |
7ab9ffdd | 6942 | /* The register or float register operand is in operand |
85f10a01 | 6943 | 0 or 1. */ |
40fb9820 | 6944 | unsigned int op; |
7ab9ffdd | 6945 | |
ca0d63fe | 6946 | if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte) |
7ab9ffdd L |
6947 | || operand_type_check (i.types[0], reg)) |
6948 | op = 0; | |
6949 | else | |
6950 | op = 1; | |
4eed87de AM |
6951 | /* Register goes in low 3 bits of opcode. */ |
6952 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
6953 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6954 | i.rex |= REX_B; |
40fb9820 | 6955 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 | 6956 | { |
4eed87de AM |
6957 | /* Warn about some common errors, but press on regardless. |
6958 | The first case can be generated by gcc (<= 2.8.1). */ | |
6959 | if (i.operands == 2) | |
6960 | { | |
6961 | /* Reversed arguments on faddp, fsubp, etc. */ | |
a540244d | 6962 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, |
d8a1b51e JB |
6963 | register_prefix, i.op[!intel_syntax].regs->reg_name, |
6964 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
4eed87de AM |
6965 | } |
6966 | else | |
6967 | { | |
6968 | /* Extraneous `l' suffix on fp insn. */ | |
a540244d L |
6969 | as_warn (_("translating to `%s %s%s'"), i.tm.name, |
6970 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de | 6971 | } |
29b0f896 AM |
6972 | } |
6973 | } | |
6974 | } | |
40fb9820 | 6975 | else if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
6976 | { |
6977 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
6978 | must be put into the modrm byte). Now, we make the modrm and |
6979 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
6980 | |
6981 | default_seg = build_modrm_byte (); | |
6982 | } | |
8a2ed489 | 6983 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
6984 | { |
6985 | default_seg = &ds; | |
6986 | } | |
40fb9820 | 6987 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
6988 | { |
6989 | /* For the string instructions that allow a segment override | |
6990 | on one of their operands, the default segment is ds. */ | |
6991 | default_seg = &ds; | |
6992 | } | |
6993 | ||
75178d9d L |
6994 | if (i.tm.base_opcode == 0x8d /* lea */ |
6995 | && i.seg[0] | |
6996 | && !quiet_warnings) | |
30123838 | 6997 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
6998 | |
6999 | /* If a segment was explicitly specified, and the specified segment | |
7000 | is not the default, use an opcode prefix to select it. If we | |
7001 | never figured out what the default segment is, then default_seg | |
7002 | will be zero at this point, and the specified segment prefix will | |
7003 | always be used. */ | |
29b0f896 AM |
7004 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
7005 | { | |
7006 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
7007 | return 0; | |
7008 | } | |
7009 | return 1; | |
7010 | } | |
7011 | ||
7012 | static const seg_entry * | |
e3bb37b5 | 7013 | build_modrm_byte (void) |
29b0f896 AM |
7014 | { |
7015 | const seg_entry *default_seg = 0; | |
c0f3af97 | 7016 | unsigned int source, dest; |
8cd7925b | 7017 | int vex_3_sources; |
c0f3af97 | 7018 | |
8cd7925b | 7019 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
7020 | if (vex_3_sources) |
7021 | { | |
91d6fa6a | 7022 | unsigned int nds, reg_slot; |
4c2c6516 | 7023 | expressionS *exp; |
c0f3af97 | 7024 | |
6b8d3588 | 7025 | dest = i.operands - 1; |
c0f3af97 | 7026 | nds = dest - 1; |
922d8de8 | 7027 | |
a683cc34 | 7028 | /* There are 2 kinds of instructions: |
bed3d976 JB |
7029 | 1. 5 operands: 4 register operands or 3 register operands |
7030 | plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and | |
7031 | VexW0 or VexW1. The destination must be either XMM, YMM or | |
43234a1e | 7032 | ZMM register. |
bed3d976 | 7033 | 2. 4 operands: 4 register operands or 3 register operands |
2f1bada2 | 7034 | plus 1 memory operand, with VexXDS. */ |
922d8de8 | 7035 | gas_assert ((i.reg_operands == 4 |
bed3d976 JB |
7036 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
7037 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
dcd7e323 JB |
7038 | && i.tm.opcode_modifier.vexw |
7039 | && i.tm.operand_types[dest].bitfield.regsimd); | |
a683cc34 | 7040 | |
48db9223 JB |
7041 | /* If VexW1 is set, the first non-immediate operand is the source and |
7042 | the second non-immediate one is encoded in the immediate operand. */ | |
7043 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
7044 | { | |
7045 | source = i.imm_operands; | |
7046 | reg_slot = i.imm_operands + 1; | |
7047 | } | |
7048 | else | |
7049 | { | |
7050 | source = i.imm_operands + 1; | |
7051 | reg_slot = i.imm_operands; | |
7052 | } | |
7053 | ||
a683cc34 | 7054 | if (i.imm_operands == 0) |
bed3d976 JB |
7055 | { |
7056 | /* When there is no immediate operand, generate an 8bit | |
7057 | immediate operand to encode the first operand. */ | |
7058 | exp = &im_expressions[i.imm_operands++]; | |
7059 | i.op[i.operands].imms = exp; | |
7060 | i.types[i.operands] = imm8; | |
7061 | i.operands++; | |
7062 | ||
7063 | gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); | |
7064 | exp->X_op = O_constant; | |
7065 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; | |
43234a1e L |
7066 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
7067 | } | |
922d8de8 | 7068 | else |
bed3d976 JB |
7069 | { |
7070 | unsigned int imm_slot; | |
a683cc34 | 7071 | |
2f1bada2 JB |
7072 | gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4); |
7073 | ||
bed3d976 JB |
7074 | if (i.tm.opcode_modifier.immext) |
7075 | { | |
7076 | /* When ImmExt is set, the immediate byte is the last | |
7077 | operand. */ | |
7078 | imm_slot = i.operands - 1; | |
7079 | source--; | |
7080 | reg_slot--; | |
7081 | } | |
7082 | else | |
7083 | { | |
7084 | imm_slot = 0; | |
7085 | ||
7086 | /* Turn on Imm8 so that output_imm will generate it. */ | |
7087 | i.types[imm_slot].bitfield.imm8 = 1; | |
7088 | } | |
7089 | ||
7090 | gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); | |
7091 | i.op[imm_slot].imms->X_add_number | |
7092 | |= register_number (i.op[reg_slot].regs) << 4; | |
43234a1e | 7093 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
bed3d976 | 7094 | } |
a683cc34 | 7095 | |
10c17abd | 7096 | gas_assert (i.tm.operand_types[nds].bitfield.regsimd); |
dae39acc | 7097 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
7098 | } |
7099 | else | |
7100 | source = dest = 0; | |
29b0f896 AM |
7101 | |
7102 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
7103 | implicit registers do not count. If there are 3 register |
7104 | operands, it must be a instruction with VexNDS. For a | |
7105 | instruction with VexNDD, the destination register is encoded | |
7106 | in VEX prefix. If there are 4 register operands, it must be | |
7107 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
7108 | if (i.mem_operands == 0 |
7109 | && ((i.reg_operands == 2 | |
2426c15f | 7110 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 7111 | || (i.reg_operands == 3 |
2426c15f | 7112 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 7113 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 7114 | { |
cab737b9 L |
7115 | switch (i.operands) |
7116 | { | |
7117 | case 2: | |
7118 | source = 0; | |
7119 | break; | |
7120 | case 3: | |
c81128dc L |
7121 | /* When there are 3 operands, one of them may be immediate, |
7122 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
7123 | the first operand must be shift count register (cl) or it |
7124 | is an instruction with VexNDS. */ | |
9c2799c2 | 7125 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 7126 | || (i.imm_operands == 0 |
2426c15f | 7127 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd | 7128 | || i.types[0].bitfield.shiftcount))); |
40fb9820 L |
7129 | if (operand_type_check (i.types[0], imm) |
7130 | || i.types[0].bitfield.shiftcount) | |
7131 | source = 1; | |
7132 | else | |
7133 | source = 0; | |
cab737b9 L |
7134 | break; |
7135 | case 4: | |
368d64cc L |
7136 | /* When there are 4 operands, the first two must be 8bit |
7137 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
7138 | one. |
7139 | ||
7140 | For instructions with VexNDS, if the first operand | |
7141 | an imm8, the source operand is the 2nd one. If the last | |
7142 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 7143 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
7144 | && i.types[0].bitfield.imm8 |
7145 | && i.types[1].bitfield.imm8) | |
2426c15f | 7146 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
7147 | && i.imm_operands == 1 |
7148 | && (i.types[0].bitfield.imm8 | |
43234a1e L |
7149 | || i.types[i.operands - 1].bitfield.imm8 |
7150 | || i.rounding))); | |
9f2670f2 L |
7151 | if (i.imm_operands == 2) |
7152 | source = 2; | |
7153 | else | |
c0f3af97 L |
7154 | { |
7155 | if (i.types[0].bitfield.imm8) | |
7156 | source = 1; | |
7157 | else | |
7158 | source = 0; | |
7159 | } | |
c0f3af97 L |
7160 | break; |
7161 | case 5: | |
e771e7c9 | 7162 | if (is_evex_encoding (&i.tm)) |
43234a1e L |
7163 | { |
7164 | /* For EVEX instructions, when there are 5 operands, the | |
7165 | first one must be immediate operand. If the second one | |
7166 | is immediate operand, the source operand is the 3th | |
7167 | one. If the last one is immediate operand, the source | |
7168 | operand is the 2nd one. */ | |
7169 | gas_assert (i.imm_operands == 2 | |
7170 | && i.tm.opcode_modifier.sae | |
7171 | && operand_type_check (i.types[0], imm)); | |
7172 | if (operand_type_check (i.types[1], imm)) | |
7173 | source = 2; | |
7174 | else if (operand_type_check (i.types[4], imm)) | |
7175 | source = 1; | |
7176 | else | |
7177 | abort (); | |
7178 | } | |
cab737b9 L |
7179 | break; |
7180 | default: | |
7181 | abort (); | |
7182 | } | |
7183 | ||
c0f3af97 L |
7184 | if (!vex_3_sources) |
7185 | { | |
7186 | dest = source + 1; | |
7187 | ||
43234a1e L |
7188 | /* RC/SAE operand could be between DEST and SRC. That happens |
7189 | when one operand is GPR and the other one is XMM/YMM/ZMM | |
7190 | register. */ | |
7191 | if (i.rounding && i.rounding->operand == (int) dest) | |
7192 | dest++; | |
7193 | ||
2426c15f | 7194 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 7195 | { |
43234a1e | 7196 | /* For instructions with VexNDS, the register-only source |
c5d0745b | 7197 | operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask |
43234a1e L |
7198 | register. It is encoded in VEX prefix. We need to |
7199 | clear RegMem bit before calling operand_type_equal. */ | |
f12dc422 L |
7200 | |
7201 | i386_operand_type op; | |
7202 | unsigned int vvvv; | |
7203 | ||
7204 | /* Check register-only source operand when two source | |
7205 | operands are swapped. */ | |
7206 | if (!i.tm.operand_types[source].bitfield.baseindex | |
7207 | && i.tm.operand_types[dest].bitfield.baseindex) | |
7208 | { | |
7209 | vvvv = source; | |
7210 | source = dest; | |
7211 | } | |
7212 | else | |
7213 | vvvv = dest; | |
7214 | ||
7215 | op = i.tm.operand_types[vvvv]; | |
fa99fab2 | 7216 | op.bitfield.regmem = 0; |
c0f3af97 | 7217 | if ((dest + 1) >= i.operands |
dc821c5f JB |
7218 | || ((!op.bitfield.reg |
7219 | || (!op.bitfield.dword && !op.bitfield.qword)) | |
10c17abd | 7220 | && !op.bitfield.regsimd |
43234a1e | 7221 | && !operand_type_equal (&op, ®mask))) |
c0f3af97 | 7222 | abort (); |
f12dc422 | 7223 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
7224 | dest++; |
7225 | } | |
7226 | } | |
29b0f896 AM |
7227 | |
7228 | i.rm.mode = 3; | |
7229 | /* One of the register operands will be encoded in the i.tm.reg | |
7230 | field, the other in the combined i.tm.mode and i.tm.regmem | |
7231 | fields. If no form of this instruction supports a memory | |
7232 | destination operand, then we assume the source operand may | |
7233 | sometimes be a memory operand and so we need to store the | |
7234 | destination in the i.rm.reg field. */ | |
40fb9820 L |
7235 | if (!i.tm.operand_types[dest].bitfield.regmem |
7236 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) | |
29b0f896 AM |
7237 | { |
7238 | i.rm.reg = i.op[dest].regs->reg_num; | |
7239 | i.rm.regmem = i.op[source].regs->reg_num; | |
b4a3a7b4 L |
7240 | if (i.op[dest].regs->reg_type.bitfield.regmmx |
7241 | || i.op[source].regs->reg_type.bitfield.regmmx) | |
7242 | i.has_regmmx = TRUE; | |
7243 | else if (i.op[dest].regs->reg_type.bitfield.regsimd | |
7244 | || i.op[source].regs->reg_type.bitfield.regsimd) | |
7245 | { | |
7246 | if (i.types[dest].bitfield.zmmword | |
7247 | || i.types[source].bitfield.zmmword) | |
7248 | i.has_regzmm = TRUE; | |
7249 | else if (i.types[dest].bitfield.ymmword | |
7250 | || i.types[source].bitfield.ymmword) | |
7251 | i.has_regymm = TRUE; | |
7252 | else | |
7253 | i.has_regxmm = TRUE; | |
7254 | } | |
29b0f896 | 7255 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7256 | i.rex |= REX_R; |
43234a1e L |
7257 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7258 | i.vrex |= REX_R; | |
29b0f896 | 7259 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7260 | i.rex |= REX_B; |
43234a1e L |
7261 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7262 | i.vrex |= REX_B; | |
29b0f896 AM |
7263 | } |
7264 | else | |
7265 | { | |
7266 | i.rm.reg = i.op[source].regs->reg_num; | |
7267 | i.rm.regmem = i.op[dest].regs->reg_num; | |
7268 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 7269 | i.rex |= REX_B; |
43234a1e L |
7270 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7271 | i.vrex |= REX_B; | |
29b0f896 | 7272 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7273 | i.rex |= REX_R; |
43234a1e L |
7274 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7275 | i.vrex |= REX_R; | |
29b0f896 | 7276 | } |
e0c7f900 | 7277 | if (flag_code != CODE_64BIT && (i.rex & REX_R)) |
c4a530c5 | 7278 | { |
e0c7f900 | 7279 | if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control) |
c4a530c5 | 7280 | abort (); |
e0c7f900 | 7281 | i.rex &= ~REX_R; |
c4a530c5 JB |
7282 | add_prefix (LOCK_PREFIX_OPCODE); |
7283 | } | |
29b0f896 AM |
7284 | } |
7285 | else | |
7286 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
7287 | unsigned int mem; |
7288 | ||
29b0f896 AM |
7289 | if (i.mem_operands) |
7290 | { | |
7291 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 7292 | unsigned int op; |
4eed87de | 7293 | |
7ab9ffdd L |
7294 | for (op = 0; op < i.operands; op++) |
7295 | if (operand_type_check (i.types[op], anymem)) | |
7296 | break; | |
7ab9ffdd | 7297 | gas_assert (op < i.operands); |
29b0f896 | 7298 | |
6c30d220 L |
7299 | if (i.tm.opcode_modifier.vecsib) |
7300 | { | |
e968fc9b | 7301 | if (i.index_reg->reg_num == RegIZ) |
6c30d220 L |
7302 | abort (); |
7303 | ||
7304 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7305 | if (!i.base_reg) | |
7306 | { | |
7307 | i.sib.base = NO_BASE_REGISTER; | |
7308 | i.sib.scale = i.log2_scale_factor; | |
7309 | i.types[op].bitfield.disp8 = 0; | |
7310 | i.types[op].bitfield.disp16 = 0; | |
7311 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7312 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
6c30d220 L |
7313 | { |
7314 | /* Must be 32 bit */ | |
7315 | i.types[op].bitfield.disp32 = 1; | |
7316 | i.types[op].bitfield.disp32s = 0; | |
7317 | } | |
7318 | else | |
7319 | { | |
7320 | i.types[op].bitfield.disp32 = 0; | |
7321 | i.types[op].bitfield.disp32s = 1; | |
7322 | } | |
7323 | } | |
7324 | i.sib.index = i.index_reg->reg_num; | |
7325 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
7326 | i.rex |= REX_X; | |
43234a1e L |
7327 | if ((i.index_reg->reg_flags & RegVRex) != 0) |
7328 | i.vrex |= REX_X; | |
6c30d220 L |
7329 | } |
7330 | ||
29b0f896 AM |
7331 | default_seg = &ds; |
7332 | ||
7333 | if (i.base_reg == 0) | |
7334 | { | |
7335 | i.rm.mode = 0; | |
7336 | if (!i.disp_operands) | |
9bb129e8 | 7337 | fake_zero_displacement = 1; |
29b0f896 AM |
7338 | if (i.index_reg == 0) |
7339 | { | |
73053c1f JB |
7340 | i386_operand_type newdisp; |
7341 | ||
6c30d220 | 7342 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7343 | /* Operand is just <disp> */ |
20f0a1fc | 7344 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
7345 | { |
7346 | /* 64bit mode overwrites the 32bit absolute | |
7347 | addressing by RIP relative addressing and | |
7348 | absolute addressing is encoded by one of the | |
7349 | redundant SIB forms. */ | |
7350 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7351 | i.sib.base = NO_BASE_REGISTER; | |
7352 | i.sib.index = NO_INDEX_REGISTER; | |
73053c1f | 7353 | newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32); |
20f0a1fc | 7354 | } |
fc225355 L |
7355 | else if ((flag_code == CODE_16BIT) |
7356 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
7357 | { |
7358 | i.rm.regmem = NO_BASE_REGISTER_16; | |
73053c1f | 7359 | newdisp = disp16; |
20f0a1fc NC |
7360 | } |
7361 | else | |
7362 | { | |
7363 | i.rm.regmem = NO_BASE_REGISTER; | |
73053c1f | 7364 | newdisp = disp32; |
29b0f896 | 7365 | } |
73053c1f JB |
7366 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
7367 | i.types[op] = operand_type_or (i.types[op], newdisp); | |
29b0f896 | 7368 | } |
6c30d220 | 7369 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7370 | { |
6c30d220 | 7371 | /* !i.base_reg && i.index_reg */ |
e968fc9b | 7372 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
7373 | i.sib.index = NO_INDEX_REGISTER; |
7374 | else | |
7375 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7376 | i.sib.base = NO_BASE_REGISTER; |
7377 | i.sib.scale = i.log2_scale_factor; | |
7378 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
7379 | i.types[op].bitfield.disp8 = 0; |
7380 | i.types[op].bitfield.disp16 = 0; | |
7381 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7382 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
40fb9820 L |
7383 | { |
7384 | /* Must be 32 bit */ | |
7385 | i.types[op].bitfield.disp32 = 1; | |
7386 | i.types[op].bitfield.disp32s = 0; | |
7387 | } | |
29b0f896 | 7388 | else |
40fb9820 L |
7389 | { |
7390 | i.types[op].bitfield.disp32 = 0; | |
7391 | i.types[op].bitfield.disp32s = 1; | |
7392 | } | |
29b0f896 | 7393 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7394 | i.rex |= REX_X; |
29b0f896 AM |
7395 | } |
7396 | } | |
7397 | /* RIP addressing for 64bit mode. */ | |
e968fc9b | 7398 | else if (i.base_reg->reg_num == RegIP) |
29b0f896 | 7399 | { |
6c30d220 | 7400 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7401 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
7402 | i.types[op].bitfield.disp8 = 0; |
7403 | i.types[op].bitfield.disp16 = 0; | |
7404 | i.types[op].bitfield.disp32 = 0; | |
7405 | i.types[op].bitfield.disp32s = 1; | |
7406 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 7407 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
7408 | if (! i.disp_operands) |
7409 | fake_zero_displacement = 1; | |
29b0f896 | 7410 | } |
dc821c5f | 7411 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 7412 | { |
6c30d220 | 7413 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7414 | switch (i.base_reg->reg_num) |
7415 | { | |
7416 | case 3: /* (%bx) */ | |
7417 | if (i.index_reg == 0) | |
7418 | i.rm.regmem = 7; | |
7419 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
7420 | i.rm.regmem = i.index_reg->reg_num - 6; | |
7421 | break; | |
7422 | case 5: /* (%bp) */ | |
7423 | default_seg = &ss; | |
7424 | if (i.index_reg == 0) | |
7425 | { | |
7426 | i.rm.regmem = 6; | |
40fb9820 | 7427 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
7428 | { |
7429 | /* fake (%bp) into 0(%bp) */ | |
b5014f7a | 7430 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 7431 | fake_zero_displacement = 1; |
29b0f896 AM |
7432 | } |
7433 | } | |
7434 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
7435 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
7436 | break; | |
7437 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
7438 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
7439 | } | |
7440 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7441 | } | |
7442 | else /* i.base_reg and 32/64 bit mode */ | |
7443 | { | |
7444 | if (flag_code == CODE_64BIT | |
40fb9820 L |
7445 | && operand_type_check (i.types[op], disp)) |
7446 | { | |
73053c1f JB |
7447 | i.types[op].bitfield.disp16 = 0; |
7448 | i.types[op].bitfield.disp64 = 0; | |
40fb9820 | 7449 | if (i.prefix[ADDR_PREFIX] == 0) |
73053c1f JB |
7450 | { |
7451 | i.types[op].bitfield.disp32 = 0; | |
7452 | i.types[op].bitfield.disp32s = 1; | |
7453 | } | |
40fb9820 | 7454 | else |
73053c1f JB |
7455 | { |
7456 | i.types[op].bitfield.disp32 = 1; | |
7457 | i.types[op].bitfield.disp32s = 0; | |
7458 | } | |
40fb9820 | 7459 | } |
20f0a1fc | 7460 | |
6c30d220 L |
7461 | if (!i.tm.opcode_modifier.vecsib) |
7462 | i.rm.regmem = i.base_reg->reg_num; | |
29b0f896 | 7463 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7464 | i.rex |= REX_B; |
29b0f896 AM |
7465 | i.sib.base = i.base_reg->reg_num; |
7466 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
7467 | complications. */ | |
848930b2 JB |
7468 | if (!(i.base_reg->reg_flags & RegRex) |
7469 | && (i.base_reg->reg_num == EBP_REG_NUM | |
7470 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
29b0f896 | 7471 | default_seg = &ss; |
848930b2 | 7472 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 7473 | { |
848930b2 | 7474 | fake_zero_displacement = 1; |
b5014f7a | 7475 | i.types[op].bitfield.disp8 = 1; |
29b0f896 AM |
7476 | } |
7477 | i.sib.scale = i.log2_scale_factor; | |
7478 | if (i.index_reg == 0) | |
7479 | { | |
6c30d220 | 7480 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7481 | /* <disp>(%esp) becomes two byte modrm with no index |
7482 | register. We've already stored the code for esp | |
7483 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
7484 | Any base register besides %esp will not use the | |
7485 | extra modrm byte. */ | |
7486 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 7487 | } |
6c30d220 | 7488 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7489 | { |
e968fc9b | 7490 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
7491 | i.sib.index = NO_INDEX_REGISTER; |
7492 | else | |
7493 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7494 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
7495 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 7496 | i.rex |= REX_X; |
29b0f896 | 7497 | } |
67a4f2b7 AO |
7498 | |
7499 | if (i.disp_operands | |
7500 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
7501 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
7502 | i.rm.mode = 0; | |
7503 | else | |
a501d77e L |
7504 | { |
7505 | if (!fake_zero_displacement | |
7506 | && !i.disp_operands | |
7507 | && i.disp_encoding) | |
7508 | { | |
7509 | fake_zero_displacement = 1; | |
7510 | if (i.disp_encoding == disp_encoding_8bit) | |
7511 | i.types[op].bitfield.disp8 = 1; | |
7512 | else | |
7513 | i.types[op].bitfield.disp32 = 1; | |
7514 | } | |
7515 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7516 | } | |
29b0f896 | 7517 | } |
252b5132 | 7518 | |
29b0f896 AM |
7519 | if (fake_zero_displacement) |
7520 | { | |
7521 | /* Fakes a zero displacement assuming that i.types[op] | |
7522 | holds the correct displacement size. */ | |
7523 | expressionS *exp; | |
7524 | ||
9c2799c2 | 7525 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
7526 | exp = &disp_expressions[i.disp_operands++]; |
7527 | i.op[op].disps = exp; | |
7528 | exp->X_op = O_constant; | |
7529 | exp->X_add_number = 0; | |
7530 | exp->X_add_symbol = (symbolS *) 0; | |
7531 | exp->X_op_symbol = (symbolS *) 0; | |
7532 | } | |
c0f3af97 L |
7533 | |
7534 | mem = op; | |
29b0f896 | 7535 | } |
c0f3af97 L |
7536 | else |
7537 | mem = ~0; | |
252b5132 | 7538 | |
8c43a48b | 7539 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
7540 | { |
7541 | if (operand_type_check (i.types[0], imm)) | |
7542 | i.vex.register_specifier = NULL; | |
7543 | else | |
7544 | { | |
7545 | /* VEX.vvvv encodes one of the sources when the first | |
7546 | operand is not an immediate. */ | |
1ef99a7b | 7547 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7548 | i.vex.register_specifier = i.op[0].regs; |
7549 | else | |
7550 | i.vex.register_specifier = i.op[1].regs; | |
7551 | } | |
7552 | ||
7553 | /* Destination is a XMM register encoded in the ModRM.reg | |
7554 | and VEX.R bit. */ | |
7555 | i.rm.reg = i.op[2].regs->reg_num; | |
7556 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
7557 | i.rex |= REX_R; | |
7558 | ||
7559 | /* ModRM.rm and VEX.B encodes the other source. */ | |
7560 | if (!i.mem_operands) | |
7561 | { | |
7562 | i.rm.mode = 3; | |
7563 | ||
1ef99a7b | 7564 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7565 | i.rm.regmem = i.op[1].regs->reg_num; |
7566 | else | |
7567 | i.rm.regmem = i.op[0].regs->reg_num; | |
7568 | ||
7569 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7570 | i.rex |= REX_B; | |
7571 | } | |
7572 | } | |
2426c15f | 7573 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
7574 | { |
7575 | i.vex.register_specifier = i.op[2].regs; | |
7576 | if (!i.mem_operands) | |
7577 | { | |
7578 | i.rm.mode = 3; | |
7579 | i.rm.regmem = i.op[1].regs->reg_num; | |
7580 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7581 | i.rex |= REX_B; | |
7582 | } | |
7583 | } | |
29b0f896 AM |
7584 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
7585 | (if any) based on i.tm.extension_opcode. Again, we must be | |
7586 | careful to make sure that segment/control/debug/test/MMX | |
7587 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 7588 | else if (i.reg_operands) |
29b0f896 | 7589 | { |
99018f42 | 7590 | unsigned int op; |
7ab9ffdd L |
7591 | unsigned int vex_reg = ~0; |
7592 | ||
7593 | for (op = 0; op < i.operands; op++) | |
b4a3a7b4 L |
7594 | { |
7595 | if (i.types[op].bitfield.reg | |
7596 | || i.types[op].bitfield.regbnd | |
7597 | || i.types[op].bitfield.regmask | |
7598 | || i.types[op].bitfield.sreg2 | |
7599 | || i.types[op].bitfield.sreg3 | |
7600 | || i.types[op].bitfield.control | |
7601 | || i.types[op].bitfield.debug | |
7602 | || i.types[op].bitfield.test) | |
7603 | break; | |
7604 | if (i.types[op].bitfield.regsimd) | |
7605 | { | |
7606 | if (i.types[op].bitfield.zmmword) | |
7607 | i.has_regzmm = TRUE; | |
7608 | else if (i.types[op].bitfield.ymmword) | |
7609 | i.has_regymm = TRUE; | |
7610 | else | |
7611 | i.has_regxmm = TRUE; | |
7612 | break; | |
7613 | } | |
7614 | if (i.types[op].bitfield.regmmx) | |
7615 | { | |
7616 | i.has_regmmx = TRUE; | |
7617 | break; | |
7618 | } | |
7619 | } | |
c0209578 | 7620 | |
7ab9ffdd L |
7621 | if (vex_3_sources) |
7622 | op = dest; | |
2426c15f | 7623 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
7624 | { |
7625 | /* For instructions with VexNDS, the register-only | |
7626 | source operand is encoded in VEX prefix. */ | |
7627 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 7628 | |
7ab9ffdd | 7629 | if (op > mem) |
c0f3af97 | 7630 | { |
7ab9ffdd L |
7631 | vex_reg = op++; |
7632 | gas_assert (op < i.operands); | |
c0f3af97 L |
7633 | } |
7634 | else | |
c0f3af97 | 7635 | { |
f12dc422 L |
7636 | /* Check register-only source operand when two source |
7637 | operands are swapped. */ | |
7638 | if (!i.tm.operand_types[op].bitfield.baseindex | |
7639 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
7640 | { | |
7641 | vex_reg = op; | |
7642 | op += 2; | |
7643 | gas_assert (mem == (vex_reg + 1) | |
7644 | && op < i.operands); | |
7645 | } | |
7646 | else | |
7647 | { | |
7648 | vex_reg = op + 1; | |
7649 | gas_assert (vex_reg < i.operands); | |
7650 | } | |
c0f3af97 | 7651 | } |
7ab9ffdd | 7652 | } |
2426c15f | 7653 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 7654 | { |
f12dc422 | 7655 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 7656 | is encoded in VEX prefix. */ |
f12dc422 L |
7657 | if (i.mem_operands == 0) |
7658 | { | |
7659 | /* There is no memory operand. */ | |
7660 | gas_assert ((op + 2) == i.operands); | |
7661 | vex_reg = op + 1; | |
7662 | } | |
7663 | else | |
8d63c93e | 7664 | { |
ed438a93 JB |
7665 | /* There are only 2 non-immediate operands. */ |
7666 | gas_assert (op < i.imm_operands + 2 | |
7667 | && i.operands == i.imm_operands + 2); | |
7668 | vex_reg = i.imm_operands + 1; | |
f12dc422 | 7669 | } |
7ab9ffdd L |
7670 | } |
7671 | else | |
7672 | gas_assert (op < i.operands); | |
99018f42 | 7673 | |
7ab9ffdd L |
7674 | if (vex_reg != (unsigned int) ~0) |
7675 | { | |
f12dc422 | 7676 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 7677 | |
dc821c5f JB |
7678 | if ((!type->bitfield.reg |
7679 | || (!type->bitfield.dword && !type->bitfield.qword)) | |
10c17abd | 7680 | && !type->bitfield.regsimd |
43234a1e | 7681 | && !operand_type_equal (type, ®mask)) |
7ab9ffdd | 7682 | abort (); |
f88c9eb0 | 7683 | |
7ab9ffdd L |
7684 | i.vex.register_specifier = i.op[vex_reg].regs; |
7685 | } | |
7686 | ||
1b9f0c97 L |
7687 | /* Don't set OP operand twice. */ |
7688 | if (vex_reg != op) | |
7ab9ffdd | 7689 | { |
1b9f0c97 L |
7690 | /* If there is an extension opcode to put here, the |
7691 | register number must be put into the regmem field. */ | |
7692 | if (i.tm.extension_opcode != None) | |
7693 | { | |
7694 | i.rm.regmem = i.op[op].regs->reg_num; | |
7695 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7696 | i.rex |= REX_B; | |
43234a1e L |
7697 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7698 | i.vrex |= REX_B; | |
1b9f0c97 L |
7699 | } |
7700 | else | |
7701 | { | |
7702 | i.rm.reg = i.op[op].regs->reg_num; | |
7703 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7704 | i.rex |= REX_R; | |
43234a1e L |
7705 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7706 | i.vrex |= REX_R; | |
1b9f0c97 | 7707 | } |
7ab9ffdd | 7708 | } |
252b5132 | 7709 | |
29b0f896 AM |
7710 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
7711 | must set it to 3 to indicate this is a register operand | |
7712 | in the regmem field. */ | |
7713 | if (!i.mem_operands) | |
7714 | i.rm.mode = 3; | |
7715 | } | |
252b5132 | 7716 | |
29b0f896 | 7717 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 7718 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
7719 | i.rm.reg = i.tm.extension_opcode; |
7720 | } | |
7721 | return default_seg; | |
7722 | } | |
252b5132 | 7723 | |
29b0f896 | 7724 | static void |
e3bb37b5 | 7725 | output_branch (void) |
29b0f896 AM |
7726 | { |
7727 | char *p; | |
f8a5c266 | 7728 | int size; |
29b0f896 AM |
7729 | int code16; |
7730 | int prefix; | |
7731 | relax_substateT subtype; | |
7732 | symbolS *sym; | |
7733 | offsetT off; | |
7734 | ||
f8a5c266 | 7735 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 7736 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
7737 | |
7738 | prefix = 0; | |
7739 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 7740 | { |
29b0f896 AM |
7741 | prefix = 1; |
7742 | i.prefixes -= 1; | |
7743 | code16 ^= CODE16; | |
252b5132 | 7744 | } |
29b0f896 AM |
7745 | /* Pentium4 branch hints. */ |
7746 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
7747 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 7748 | { |
29b0f896 AM |
7749 | prefix++; |
7750 | i.prefixes--; | |
7751 | } | |
7752 | if (i.prefix[REX_PREFIX] != 0) | |
7753 | { | |
7754 | prefix++; | |
7755 | i.prefixes--; | |
2f66722d AM |
7756 | } |
7757 | ||
7e8b059b L |
7758 | /* BND prefixed jump. */ |
7759 | if (i.prefix[BND_PREFIX] != 0) | |
7760 | { | |
7761 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
7762 | i.prefixes -= 1; | |
7763 | } | |
7764 | ||
29b0f896 AM |
7765 | if (i.prefixes != 0 && !intel_syntax) |
7766 | as_warn (_("skipping prefixes on this instruction")); | |
7767 | ||
7768 | /* It's always a symbol; End frag & setup for relax. | |
7769 | Make sure there is enough room in this frag for the largest | |
7770 | instruction we may generate in md_convert_frag. This is 2 | |
7771 | bytes for the opcode and room for the prefix and largest | |
7772 | displacement. */ | |
7773 | frag_grow (prefix + 2 + 4); | |
7774 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
7775 | p = frag_more (prefix + 1); | |
7776 | if (i.prefix[DATA_PREFIX] != 0) | |
7777 | *p++ = DATA_PREFIX_OPCODE; | |
7778 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
7779 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
7780 | *p++ = i.prefix[SEG_PREFIX]; | |
7781 | if (i.prefix[REX_PREFIX] != 0) | |
7782 | *p++ = i.prefix[REX_PREFIX]; | |
7783 | *p = i.tm.base_opcode; | |
7784 | ||
7785 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 7786 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 7787 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 7788 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 7789 | else |
f8a5c266 | 7790 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 7791 | subtype |= code16; |
3e73aa7c | 7792 | |
29b0f896 AM |
7793 | sym = i.op[0].disps->X_add_symbol; |
7794 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 7795 | |
29b0f896 AM |
7796 | if (i.op[0].disps->X_op != O_constant |
7797 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 7798 | { |
29b0f896 AM |
7799 | /* Handle complex expressions. */ |
7800 | sym = make_expr_symbol (i.op[0].disps); | |
7801 | off = 0; | |
7802 | } | |
3e73aa7c | 7803 | |
29b0f896 AM |
7804 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
7805 | Pass reloc in fr_var. */ | |
d258b828 | 7806 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 7807 | } |
3e73aa7c | 7808 | |
bd7ab16b L |
7809 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7810 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
7811 | symbol S. */ | |
7812 | ||
7813 | static bfd_boolean | |
7814 | need_plt32_p (symbolS *s) | |
7815 | { | |
7816 | /* PLT32 relocation is ELF only. */ | |
7817 | if (!IS_ELF) | |
7818 | return FALSE; | |
7819 | ||
a5def729 RO |
7820 | #ifdef TE_SOLARIS |
7821 | /* Don't emit PLT32 relocation on Solaris: neither native linker nor | |
7822 | krtld support it. */ | |
7823 | return FALSE; | |
7824 | #endif | |
7825 | ||
bd7ab16b L |
7826 | /* Since there is no need to prepare for PLT branch on x86-64, we |
7827 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
7828 | be used as a marker for 32-bit PC-relative branches. */ | |
7829 | if (!object_64bit) | |
7830 | return FALSE; | |
7831 | ||
7832 | /* Weak or undefined symbol need PLT32 relocation. */ | |
7833 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
7834 | return TRUE; | |
7835 | ||
7836 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
7837 | if (! S_IS_EXTERNAL (s)) | |
7838 | return FALSE; | |
7839 | ||
7840 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
7841 | non-default visibilities are treated as normal global symbol | |
7842 | so that PLT32 relocation can be used as a marker for 32-bit | |
7843 | PC-relative branches. It is useful for linker relaxation. */ | |
7844 | return TRUE; | |
7845 | } | |
7846 | #endif | |
7847 | ||
29b0f896 | 7848 | static void |
e3bb37b5 | 7849 | output_jump (void) |
29b0f896 AM |
7850 | { |
7851 | char *p; | |
7852 | int size; | |
3e02c1cc | 7853 | fixS *fixP; |
bd7ab16b | 7854 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 7855 | |
40fb9820 | 7856 | if (i.tm.opcode_modifier.jumpbyte) |
29b0f896 AM |
7857 | { |
7858 | /* This is a loop or jecxz type instruction. */ | |
7859 | size = 1; | |
7860 | if (i.prefix[ADDR_PREFIX] != 0) | |
7861 | { | |
7862 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
7863 | i.prefixes -= 1; | |
7864 | } | |
7865 | /* Pentium4 branch hints. */ | |
7866 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
7867 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
7868 | { | |
7869 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
7870 | i.prefixes--; | |
3e73aa7c JH |
7871 | } |
7872 | } | |
29b0f896 AM |
7873 | else |
7874 | { | |
7875 | int code16; | |
3e73aa7c | 7876 | |
29b0f896 AM |
7877 | code16 = 0; |
7878 | if (flag_code == CODE_16BIT) | |
7879 | code16 = CODE16; | |
3e73aa7c | 7880 | |
29b0f896 AM |
7881 | if (i.prefix[DATA_PREFIX] != 0) |
7882 | { | |
7883 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
7884 | i.prefixes -= 1; | |
7885 | code16 ^= CODE16; | |
7886 | } | |
252b5132 | 7887 | |
29b0f896 AM |
7888 | size = 4; |
7889 | if (code16) | |
7890 | size = 2; | |
7891 | } | |
9fcc94b6 | 7892 | |
29b0f896 AM |
7893 | if (i.prefix[REX_PREFIX] != 0) |
7894 | { | |
7895 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
7896 | i.prefixes -= 1; | |
7897 | } | |
252b5132 | 7898 | |
7e8b059b L |
7899 | /* BND prefixed jump. */ |
7900 | if (i.prefix[BND_PREFIX] != 0) | |
7901 | { | |
7902 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
7903 | i.prefixes -= 1; | |
7904 | } | |
7905 | ||
29b0f896 AM |
7906 | if (i.prefixes != 0 && !intel_syntax) |
7907 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 7908 | |
42164a71 L |
7909 | p = frag_more (i.tm.opcode_length + size); |
7910 | switch (i.tm.opcode_length) | |
7911 | { | |
7912 | case 2: | |
7913 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 7914 | /* Fall through. */ |
42164a71 L |
7915 | case 1: |
7916 | *p++ = i.tm.base_opcode; | |
7917 | break; | |
7918 | default: | |
7919 | abort (); | |
7920 | } | |
e0890092 | 7921 | |
bd7ab16b L |
7922 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7923 | if (size == 4 | |
7924 | && jump_reloc == NO_RELOC | |
7925 | && need_plt32_p (i.op[0].disps->X_add_symbol)) | |
7926 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
7927 | #endif | |
7928 | ||
7929 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
7930 | ||
3e02c1cc | 7931 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 7932 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc AM |
7933 | |
7934 | /* All jumps handled here are signed, but don't use a signed limit | |
7935 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
7936 | 4G and 64k respectively. */ | |
7937 | if (size == 1) | |
7938 | fixP->fx_signed = 1; | |
29b0f896 | 7939 | } |
e0890092 | 7940 | |
29b0f896 | 7941 | static void |
e3bb37b5 | 7942 | output_interseg_jump (void) |
29b0f896 AM |
7943 | { |
7944 | char *p; | |
7945 | int size; | |
7946 | int prefix; | |
7947 | int code16; | |
252b5132 | 7948 | |
29b0f896 AM |
7949 | code16 = 0; |
7950 | if (flag_code == CODE_16BIT) | |
7951 | code16 = CODE16; | |
a217f122 | 7952 | |
29b0f896 AM |
7953 | prefix = 0; |
7954 | if (i.prefix[DATA_PREFIX] != 0) | |
7955 | { | |
7956 | prefix = 1; | |
7957 | i.prefixes -= 1; | |
7958 | code16 ^= CODE16; | |
7959 | } | |
7960 | if (i.prefix[REX_PREFIX] != 0) | |
7961 | { | |
7962 | prefix++; | |
7963 | i.prefixes -= 1; | |
7964 | } | |
252b5132 | 7965 | |
29b0f896 AM |
7966 | size = 4; |
7967 | if (code16) | |
7968 | size = 2; | |
252b5132 | 7969 | |
29b0f896 AM |
7970 | if (i.prefixes != 0 && !intel_syntax) |
7971 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 7972 | |
29b0f896 AM |
7973 | /* 1 opcode; 2 segment; offset */ |
7974 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 7975 | |
29b0f896 AM |
7976 | if (i.prefix[DATA_PREFIX] != 0) |
7977 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 7978 | |
29b0f896 AM |
7979 | if (i.prefix[REX_PREFIX] != 0) |
7980 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 7981 | |
29b0f896 AM |
7982 | *p++ = i.tm.base_opcode; |
7983 | if (i.op[1].imms->X_op == O_constant) | |
7984 | { | |
7985 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 7986 | |
29b0f896 AM |
7987 | if (size == 2 |
7988 | && !fits_in_unsigned_word (n) | |
7989 | && !fits_in_signed_word (n)) | |
7990 | { | |
7991 | as_bad (_("16-bit jump out of range")); | |
7992 | return; | |
7993 | } | |
7994 | md_number_to_chars (p, n, size); | |
7995 | } | |
7996 | else | |
7997 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 7998 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
29b0f896 AM |
7999 | if (i.op[0].imms->X_op != O_constant) |
8000 | as_bad (_("can't handle non absolute segment in `%s'"), | |
8001 | i.tm.name); | |
8002 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
8003 | } | |
a217f122 | 8004 | |
b4a3a7b4 L |
8005 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8006 | void | |
8007 | x86_cleanup (void) | |
8008 | { | |
8009 | char *p; | |
8010 | asection *seg = now_seg; | |
8011 | subsegT subseg = now_subseg; | |
8012 | asection *sec; | |
8013 | unsigned int alignment, align_size_1; | |
8014 | unsigned int isa_1_descsz, feature_2_descsz, descsz; | |
8015 | unsigned int isa_1_descsz_raw, feature_2_descsz_raw; | |
8016 | unsigned int padding; | |
8017 | ||
8018 | if (!IS_ELF || !x86_used_note) | |
8019 | return; | |
8020 | ||
b4a3a7b4 L |
8021 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86; |
8022 | ||
8023 | /* The .note.gnu.property section layout: | |
8024 | ||
8025 | Field Length Contents | |
8026 | ---- ---- ---- | |
8027 | n_namsz 4 4 | |
8028 | n_descsz 4 The note descriptor size | |
8029 | n_type 4 NT_GNU_PROPERTY_TYPE_0 | |
8030 | n_name 4 "GNU" | |
8031 | n_desc n_descsz The program property array | |
8032 | .... .... .... | |
8033 | */ | |
8034 | ||
8035 | /* Create the .note.gnu.property section. */ | |
8036 | sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0); | |
8037 | bfd_set_section_flags (stdoutput, sec, | |
8038 | (SEC_ALLOC | |
8039 | | SEC_LOAD | |
8040 | | SEC_DATA | |
8041 | | SEC_HAS_CONTENTS | |
8042 | | SEC_READONLY)); | |
8043 | ||
8044 | if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64) | |
8045 | { | |
8046 | align_size_1 = 7; | |
8047 | alignment = 3; | |
8048 | } | |
8049 | else | |
8050 | { | |
8051 | align_size_1 = 3; | |
8052 | alignment = 2; | |
8053 | } | |
8054 | ||
8055 | bfd_set_section_alignment (stdoutput, sec, alignment); | |
8056 | elf_section_type (sec) = SHT_NOTE; | |
8057 | ||
8058 | /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size | |
8059 | + 4-byte data */ | |
8060 | isa_1_descsz_raw = 4 + 4 + 4; | |
8061 | /* Align GNU_PROPERTY_X86_ISA_1_USED. */ | |
8062 | isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1; | |
8063 | ||
8064 | feature_2_descsz_raw = isa_1_descsz; | |
8065 | /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size | |
8066 | + 4-byte data */ | |
8067 | feature_2_descsz_raw += 4 + 4 + 4; | |
8068 | /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
8069 | feature_2_descsz = ((feature_2_descsz_raw + align_size_1) | |
8070 | & ~align_size_1); | |
8071 | ||
8072 | descsz = feature_2_descsz; | |
8073 | /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */ | |
8074 | p = frag_more (4 + 4 + 4 + 4 + descsz); | |
8075 | ||
8076 | /* Write n_namsz. */ | |
8077 | md_number_to_chars (p, (valueT) 4, 4); | |
8078 | ||
8079 | /* Write n_descsz. */ | |
8080 | md_number_to_chars (p + 4, (valueT) descsz, 4); | |
8081 | ||
8082 | /* Write n_type. */ | |
8083 | md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4); | |
8084 | ||
8085 | /* Write n_name. */ | |
8086 | memcpy (p + 4 * 3, "GNU", 4); | |
8087 | ||
8088 | /* Write 4-byte type. */ | |
8089 | md_number_to_chars (p + 4 * 4, | |
8090 | (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4); | |
8091 | ||
8092 | /* Write 4-byte data size. */ | |
8093 | md_number_to_chars (p + 4 * 5, (valueT) 4, 4); | |
8094 | ||
8095 | /* Write 4-byte data. */ | |
8096 | md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4); | |
8097 | ||
8098 | /* Zero out paddings. */ | |
8099 | padding = isa_1_descsz - isa_1_descsz_raw; | |
8100 | if (padding) | |
8101 | memset (p + 4 * 7, 0, padding); | |
8102 | ||
8103 | /* Write 4-byte type. */ | |
8104 | md_number_to_chars (p + isa_1_descsz + 4 * 4, | |
8105 | (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4); | |
8106 | ||
8107 | /* Write 4-byte data size. */ | |
8108 | md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4); | |
8109 | ||
8110 | /* Write 4-byte data. */ | |
8111 | md_number_to_chars (p + isa_1_descsz + 4 * 6, | |
8112 | (valueT) x86_feature_2_used, 4); | |
8113 | ||
8114 | /* Zero out paddings. */ | |
8115 | padding = feature_2_descsz - feature_2_descsz_raw; | |
8116 | if (padding) | |
8117 | memset (p + isa_1_descsz + 4 * 7, 0, padding); | |
8118 | ||
8119 | /* We probably can't restore the current segment, for there likely | |
8120 | isn't one yet... */ | |
8121 | if (seg && subseg) | |
8122 | subseg_set (seg, subseg); | |
8123 | } | |
8124 | #endif | |
8125 | ||
29b0f896 | 8126 | static void |
e3bb37b5 | 8127 | output_insn (void) |
29b0f896 | 8128 | { |
2bbd9c25 JJ |
8129 | fragS *insn_start_frag; |
8130 | offsetT insn_start_off; | |
8131 | ||
b4a3a7b4 L |
8132 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8133 | if (IS_ELF && x86_used_note) | |
8134 | { | |
8135 | if (i.tm.cpu_flags.bitfield.cpucmov) | |
8136 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_CMOV; | |
8137 | if (i.tm.cpu_flags.bitfield.cpusse) | |
8138 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE; | |
8139 | if (i.tm.cpu_flags.bitfield.cpusse2) | |
8140 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE2; | |
8141 | if (i.tm.cpu_flags.bitfield.cpusse3) | |
8142 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE3; | |
8143 | if (i.tm.cpu_flags.bitfield.cpussse3) | |
8144 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSSE3; | |
8145 | if (i.tm.cpu_flags.bitfield.cpusse4_1) | |
8146 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_1; | |
8147 | if (i.tm.cpu_flags.bitfield.cpusse4_2) | |
8148 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_2; | |
8149 | if (i.tm.cpu_flags.bitfield.cpuavx) | |
8150 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX; | |
8151 | if (i.tm.cpu_flags.bitfield.cpuavx2) | |
8152 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX2; | |
8153 | if (i.tm.cpu_flags.bitfield.cpufma) | |
8154 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_FMA; | |
8155 | if (i.tm.cpu_flags.bitfield.cpuavx512f) | |
8156 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512F; | |
8157 | if (i.tm.cpu_flags.bitfield.cpuavx512cd) | |
8158 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512CD; | |
8159 | if (i.tm.cpu_flags.bitfield.cpuavx512er) | |
8160 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512ER; | |
8161 | if (i.tm.cpu_flags.bitfield.cpuavx512pf) | |
8162 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512PF; | |
8163 | if (i.tm.cpu_flags.bitfield.cpuavx512vl) | |
8164 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512VL; | |
8165 | if (i.tm.cpu_flags.bitfield.cpuavx512dq) | |
8166 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512DQ; | |
8167 | if (i.tm.cpu_flags.bitfield.cpuavx512bw) | |
8168 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512BW; | |
8169 | if (i.tm.cpu_flags.bitfield.cpuavx512_4fmaps) | |
8170 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS; | |
8171 | if (i.tm.cpu_flags.bitfield.cpuavx512_4vnniw) | |
8172 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW; | |
8173 | if (i.tm.cpu_flags.bitfield.cpuavx512_bitalg) | |
8174 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG; | |
8175 | if (i.tm.cpu_flags.bitfield.cpuavx512ifma) | |
8176 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA; | |
8177 | if (i.tm.cpu_flags.bitfield.cpuavx512vbmi) | |
8178 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI; | |
8179 | if (i.tm.cpu_flags.bitfield.cpuavx512_vbmi2) | |
8180 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2; | |
8181 | if (i.tm.cpu_flags.bitfield.cpuavx512_vnni) | |
8182 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI; | |
462cac58 L |
8183 | if (i.tm.cpu_flags.bitfield.cpuavx512_bf16) |
8184 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BF16; | |
b4a3a7b4 L |
8185 | |
8186 | if (i.tm.cpu_flags.bitfield.cpu8087 | |
8187 | || i.tm.cpu_flags.bitfield.cpu287 | |
8188 | || i.tm.cpu_flags.bitfield.cpu387 | |
8189 | || i.tm.cpu_flags.bitfield.cpu687 | |
8190 | || i.tm.cpu_flags.bitfield.cpufisttp) | |
8191 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87; | |
8192 | /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor | |
8193 | Xfence instructions. */ | |
8194 | if (i.tm.base_opcode != 0xf18 | |
8195 | && i.tm.base_opcode != 0xf0d | |
8196 | && i.tm.base_opcode != 0xfae | |
8197 | && (i.has_regmmx | |
8198 | || i.tm.cpu_flags.bitfield.cpummx | |
8199 | || i.tm.cpu_flags.bitfield.cpua3dnow | |
8200 | || i.tm.cpu_flags.bitfield.cpua3dnowa)) | |
8201 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX; | |
8202 | if (i.has_regxmm) | |
8203 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM; | |
8204 | if (i.has_regymm) | |
8205 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM; | |
8206 | if (i.has_regzmm) | |
8207 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM; | |
8208 | if (i.tm.cpu_flags.bitfield.cpufxsr) | |
8209 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR; | |
8210 | if (i.tm.cpu_flags.bitfield.cpuxsave) | |
8211 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE; | |
8212 | if (i.tm.cpu_flags.bitfield.cpuxsaveopt) | |
8213 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT; | |
8214 | if (i.tm.cpu_flags.bitfield.cpuxsavec) | |
8215 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC; | |
8216 | } | |
8217 | #endif | |
8218 | ||
29b0f896 AM |
8219 | /* Tie dwarf2 debug info to the address at the start of the insn. |
8220 | We can't do this after the insn has been output as the current | |
8221 | frag may have been closed off. eg. by frag_var. */ | |
8222 | dwarf2_emit_insn (0); | |
8223 | ||
2bbd9c25 JJ |
8224 | insn_start_frag = frag_now; |
8225 | insn_start_off = frag_now_fix (); | |
8226 | ||
29b0f896 | 8227 | /* Output jumps. */ |
40fb9820 | 8228 | if (i.tm.opcode_modifier.jump) |
29b0f896 | 8229 | output_branch (); |
40fb9820 L |
8230 | else if (i.tm.opcode_modifier.jumpbyte |
8231 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 | 8232 | output_jump (); |
40fb9820 | 8233 | else if (i.tm.opcode_modifier.jumpintersegment) |
29b0f896 AM |
8234 | output_interseg_jump (); |
8235 | else | |
8236 | { | |
8237 | /* Output normal instructions here. */ | |
8238 | char *p; | |
8239 | unsigned char *q; | |
47465058 | 8240 | unsigned int j; |
331d2d0d | 8241 | unsigned int prefix; |
4dffcebc | 8242 | |
e4e00185 AS |
8243 | if (avoid_fence |
8244 | && i.tm.base_opcode == 0xfae | |
8245 | && i.operands == 1 | |
8246 | && i.imm_operands == 1 | |
8247 | && (i.op[0].imms->X_add_number == 0xe8 | |
8248 | || i.op[0].imms->X_add_number == 0xf0 | |
8249 | || i.op[0].imms->X_add_number == 0xf8)) | |
8250 | { | |
8251 | /* Encode lfence, mfence, and sfence as | |
8252 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
8253 | offsetT val = 0x240483f0ULL; | |
8254 | p = frag_more (5); | |
8255 | md_number_to_chars (p, val, 5); | |
8256 | return; | |
8257 | } | |
8258 | ||
d022bddd IT |
8259 | /* Some processors fail on LOCK prefix. This options makes |
8260 | assembler ignore LOCK prefix and serves as a workaround. */ | |
8261 | if (omit_lock_prefix) | |
8262 | { | |
8263 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) | |
8264 | return; | |
8265 | i.prefix[LOCK_PREFIX] = 0; | |
8266 | } | |
8267 | ||
43234a1e L |
8268 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
8269 | don't need the explicit prefix. */ | |
8270 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) | |
bc4bd9ab | 8271 | { |
c0f3af97 | 8272 | switch (i.tm.opcode_length) |
bc4bd9ab | 8273 | { |
c0f3af97 L |
8274 | case 3: |
8275 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 8276 | { |
c0f3af97 | 8277 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
bd59a631 | 8278 | add_prefix (prefix); |
c0f3af97 L |
8279 | } |
8280 | break; | |
8281 | case 2: | |
8282 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
8283 | { | |
8284 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
bd59a631 JB |
8285 | if (!i.tm.cpu_flags.bitfield.cpupadlock |
8286 | || prefix != REPE_PREFIX_OPCODE | |
8287 | || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE)) | |
4dffcebc L |
8288 | add_prefix (prefix); |
8289 | } | |
c0f3af97 L |
8290 | break; |
8291 | case 1: | |
8292 | break; | |
390c91cf L |
8293 | case 0: |
8294 | /* Check for pseudo prefixes. */ | |
8295 | as_bad_where (insn_start_frag->fr_file, | |
8296 | insn_start_frag->fr_line, | |
8297 | _("pseudo prefix without instruction")); | |
8298 | return; | |
c0f3af97 L |
8299 | default: |
8300 | abort (); | |
bc4bd9ab | 8301 | } |
c0f3af97 | 8302 | |
6d19a37a | 8303 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
8304 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
8305 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
8306 | perform IE->LE optimization. */ | |
8307 | if (x86_elf_abi == X86_64_X32_ABI | |
8308 | && i.operands == 2 | |
8309 | && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF | |
8310 | && i.prefix[REX_PREFIX] == 0) | |
8311 | add_prefix (REX_OPCODE); | |
6d19a37a | 8312 | #endif |
cf61b747 | 8313 | |
c0f3af97 L |
8314 | /* The prefix bytes. */ |
8315 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
8316 | if (*q) | |
8317 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 8318 | } |
ae5c1c7b | 8319 | else |
c0f3af97 L |
8320 | { |
8321 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
8322 | if (*q) | |
8323 | switch (j) | |
8324 | { | |
8325 | case REX_PREFIX: | |
8326 | /* REX byte is encoded in VEX prefix. */ | |
8327 | break; | |
8328 | case SEG_PREFIX: | |
8329 | case ADDR_PREFIX: | |
8330 | FRAG_APPEND_1_CHAR (*q); | |
8331 | break; | |
8332 | default: | |
8333 | /* There should be no other prefixes for instructions | |
8334 | with VEX prefix. */ | |
8335 | abort (); | |
8336 | } | |
8337 | ||
43234a1e L |
8338 | /* For EVEX instructions i.vrex should become 0 after |
8339 | build_evex_prefix. For VEX instructions upper 16 registers | |
8340 | aren't available, so VREX should be 0. */ | |
8341 | if (i.vrex) | |
8342 | abort (); | |
c0f3af97 L |
8343 | /* Now the VEX prefix. */ |
8344 | p = frag_more (i.vex.length); | |
8345 | for (j = 0; j < i.vex.length; j++) | |
8346 | p[j] = i.vex.bytes[j]; | |
8347 | } | |
252b5132 | 8348 | |
29b0f896 | 8349 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 8350 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
8351 | { |
8352 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
8353 | } | |
8354 | else | |
8355 | { | |
4dffcebc | 8356 | switch (i.tm.opcode_length) |
331d2d0d | 8357 | { |
43234a1e L |
8358 | case 4: |
8359 | p = frag_more (4); | |
8360 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
8361 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
8362 | break; | |
4dffcebc | 8363 | case 3: |
331d2d0d L |
8364 | p = frag_more (3); |
8365 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
8366 | break; |
8367 | case 2: | |
8368 | p = frag_more (2); | |
8369 | break; | |
8370 | default: | |
8371 | abort (); | |
8372 | break; | |
331d2d0d | 8373 | } |
0f10071e | 8374 | |
29b0f896 AM |
8375 | /* Put out high byte first: can't use md_number_to_chars! */ |
8376 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
8377 | *p = i.tm.base_opcode & 0xff; | |
8378 | } | |
3e73aa7c | 8379 | |
29b0f896 | 8380 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 8381 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 8382 | { |
4a3523fa L |
8383 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
8384 | | i.rm.reg << 3 | |
8385 | | i.rm.mode << 6)); | |
29b0f896 AM |
8386 | /* If i.rm.regmem == ESP (4) |
8387 | && i.rm.mode != (Register mode) | |
8388 | && not 16 bit | |
8389 | ==> need second modrm byte. */ | |
8390 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
8391 | && i.rm.mode != 3 | |
dc821c5f | 8392 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
4a3523fa L |
8393 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
8394 | | i.sib.index << 3 | |
8395 | | i.sib.scale << 6)); | |
29b0f896 | 8396 | } |
3e73aa7c | 8397 | |
29b0f896 | 8398 | if (i.disp_operands) |
2bbd9c25 | 8399 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 8400 | |
29b0f896 | 8401 | if (i.imm_operands) |
2bbd9c25 | 8402 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 8403 | } |
252b5132 | 8404 | |
29b0f896 AM |
8405 | #ifdef DEBUG386 |
8406 | if (flag_debug) | |
8407 | { | |
7b81dfbb | 8408 | pi ("" /*line*/, &i); |
29b0f896 AM |
8409 | } |
8410 | #endif /* DEBUG386 */ | |
8411 | } | |
252b5132 | 8412 | |
e205caa7 L |
8413 | /* Return the size of the displacement operand N. */ |
8414 | ||
8415 | static int | |
8416 | disp_size (unsigned int n) | |
8417 | { | |
8418 | int size = 4; | |
43234a1e | 8419 | |
b5014f7a | 8420 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
8421 | size = 8; |
8422 | else if (i.types[n].bitfield.disp8) | |
8423 | size = 1; | |
8424 | else if (i.types[n].bitfield.disp16) | |
8425 | size = 2; | |
e205caa7 L |
8426 | return size; |
8427 | } | |
8428 | ||
8429 | /* Return the size of the immediate operand N. */ | |
8430 | ||
8431 | static int | |
8432 | imm_size (unsigned int n) | |
8433 | { | |
8434 | int size = 4; | |
40fb9820 L |
8435 | if (i.types[n].bitfield.imm64) |
8436 | size = 8; | |
8437 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
8438 | size = 1; | |
8439 | else if (i.types[n].bitfield.imm16) | |
8440 | size = 2; | |
e205caa7 L |
8441 | return size; |
8442 | } | |
8443 | ||
29b0f896 | 8444 | static void |
64e74474 | 8445 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
8446 | { |
8447 | char *p; | |
8448 | unsigned int n; | |
252b5132 | 8449 | |
29b0f896 AM |
8450 | for (n = 0; n < i.operands; n++) |
8451 | { | |
b5014f7a | 8452 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
8453 | { |
8454 | if (i.op[n].disps->X_op == O_constant) | |
8455 | { | |
e205caa7 | 8456 | int size = disp_size (n); |
43234a1e | 8457 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 8458 | |
629cfaf1 JB |
8459 | val = offset_in_range (val >> (size == 1 ? i.memshift : 0), |
8460 | size); | |
29b0f896 AM |
8461 | p = frag_more (size); |
8462 | md_number_to_chars (p, val, size); | |
8463 | } | |
8464 | else | |
8465 | { | |
f86103b7 | 8466 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 8467 | int size = disp_size (n); |
40fb9820 | 8468 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 | 8469 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
02a86693 | 8470 | fixS *fixP; |
29b0f896 | 8471 | |
e205caa7 | 8472 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 8473 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 8474 | |
29b0f896 AM |
8475 | /* The PC relative address is computed relative |
8476 | to the instruction boundary, so in case immediate | |
8477 | fields follows, we need to adjust the value. */ | |
8478 | if (pcrel && i.imm_operands) | |
8479 | { | |
29b0f896 | 8480 | unsigned int n1; |
e205caa7 | 8481 | int sz = 0; |
252b5132 | 8482 | |
29b0f896 | 8483 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 8484 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 8485 | { |
e205caa7 L |
8486 | /* Only one immediate is allowed for PC |
8487 | relative address. */ | |
9c2799c2 | 8488 | gas_assert (sz == 0); |
e205caa7 L |
8489 | sz = imm_size (n1); |
8490 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 8491 | } |
29b0f896 | 8492 | /* We should find the immediate. */ |
9c2799c2 | 8493 | gas_assert (sz != 0); |
29b0f896 | 8494 | } |
520dc8e8 | 8495 | |
29b0f896 | 8496 | p = frag_more (size); |
d258b828 | 8497 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 8498 | if (GOT_symbol |
2bbd9c25 | 8499 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 8500 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
8501 | || reloc_type == BFD_RELOC_X86_64_32S |
8502 | || (reloc_type == BFD_RELOC_64 | |
8503 | && object_64bit)) | |
d6ab8113 JB |
8504 | && (i.op[n].disps->X_op == O_symbol |
8505 | || (i.op[n].disps->X_op == O_add | |
8506 | && ((symbol_get_value_expression | |
8507 | (i.op[n].disps->X_op_symbol)->X_op) | |
8508 | == O_subtract)))) | |
8509 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 JJ |
8510 | { |
8511 | offsetT add; | |
8512 | ||
8513 | if (insn_start_frag == frag_now) | |
8514 | add = (p - frag_now->fr_literal) - insn_start_off; | |
8515 | else | |
8516 | { | |
8517 | fragS *fr; | |
8518 | ||
8519 | add = insn_start_frag->fr_fix - insn_start_off; | |
8520 | for (fr = insn_start_frag->fr_next; | |
8521 | fr && fr != frag_now; fr = fr->fr_next) | |
8522 | add += fr->fr_fix; | |
8523 | add += p - frag_now->fr_literal; | |
8524 | } | |
8525 | ||
4fa24527 | 8526 | if (!object_64bit) |
7b81dfbb AJ |
8527 | { |
8528 | reloc_type = BFD_RELOC_386_GOTPC; | |
8529 | i.op[n].imms->X_add_number += add; | |
8530 | } | |
8531 | else if (reloc_type == BFD_RELOC_64) | |
8532 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 8533 | else |
7b81dfbb AJ |
8534 | /* Don't do the adjustment for x86-64, as there |
8535 | the pcrel addressing is relative to the _next_ | |
8536 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 8537 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 8538 | } |
02a86693 L |
8539 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
8540 | size, i.op[n].disps, pcrel, | |
8541 | reloc_type); | |
8542 | /* Check for "call/jmp *mem", "mov mem, %reg", | |
8543 | "test %reg, mem" and "binop mem, %reg" where binop | |
8544 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
e60f4d3b L |
8545 | instructions without data prefix. Always generate |
8546 | R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */ | |
8547 | if (i.prefix[DATA_PREFIX] == 0 | |
8548 | && (generate_relax_relocations | |
8549 | || (!object_64bit | |
8550 | && i.rm.mode == 0 | |
8551 | && i.rm.regmem == 5)) | |
0cb4071e L |
8552 | && (i.rm.mode == 2 |
8553 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
02a86693 L |
8554 | && ((i.operands == 1 |
8555 | && i.tm.base_opcode == 0xff | |
8556 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
8557 | || (i.operands == 2 | |
8558 | && (i.tm.base_opcode == 0x8b | |
8559 | || i.tm.base_opcode == 0x85 | |
8560 | || (i.tm.base_opcode & 0xc7) == 0x03)))) | |
8561 | { | |
8562 | if (object_64bit) | |
8563 | { | |
8564 | fixP->fx_tcbit = i.rex != 0; | |
8565 | if (i.base_reg | |
e968fc9b | 8566 | && (i.base_reg->reg_num == RegIP)) |
02a86693 L |
8567 | fixP->fx_tcbit2 = 1; |
8568 | } | |
8569 | else | |
8570 | fixP->fx_tcbit2 = 1; | |
8571 | } | |
29b0f896 AM |
8572 | } |
8573 | } | |
8574 | } | |
8575 | } | |
252b5132 | 8576 | |
29b0f896 | 8577 | static void |
64e74474 | 8578 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
8579 | { |
8580 | char *p; | |
8581 | unsigned int n; | |
252b5132 | 8582 | |
29b0f896 AM |
8583 | for (n = 0; n < i.operands; n++) |
8584 | { | |
43234a1e L |
8585 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
8586 | if (i.rounding && (int) n == i.rounding->operand) | |
8587 | continue; | |
8588 | ||
40fb9820 | 8589 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
8590 | { |
8591 | if (i.op[n].imms->X_op == O_constant) | |
8592 | { | |
e205caa7 | 8593 | int size = imm_size (n); |
29b0f896 | 8594 | offsetT val; |
b4cac588 | 8595 | |
29b0f896 AM |
8596 | val = offset_in_range (i.op[n].imms->X_add_number, |
8597 | size); | |
8598 | p = frag_more (size); | |
8599 | md_number_to_chars (p, val, size); | |
8600 | } | |
8601 | else | |
8602 | { | |
8603 | /* Not absolute_section. | |
8604 | Need a 32-bit fixup (don't support 8bit | |
8605 | non-absolute imms). Try to support other | |
8606 | sizes ... */ | |
f86103b7 | 8607 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
8608 | int size = imm_size (n); |
8609 | int sign; | |
29b0f896 | 8610 | |
40fb9820 | 8611 | if (i.types[n].bitfield.imm32s |
a7d61044 | 8612 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 8613 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 8614 | sign = 1; |
e205caa7 L |
8615 | else |
8616 | sign = 0; | |
520dc8e8 | 8617 | |
29b0f896 | 8618 | p = frag_more (size); |
d258b828 | 8619 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 8620 | |
2bbd9c25 JJ |
8621 | /* This is tough to explain. We end up with this one if we |
8622 | * have operands that look like | |
8623 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
8624 | * obtain the absolute address of the GOT, and it is strongly | |
8625 | * preferable from a performance point of view to avoid using | |
8626 | * a runtime relocation for this. The actual sequence of | |
8627 | * instructions often look something like: | |
8628 | * | |
8629 | * call .L66 | |
8630 | * .L66: | |
8631 | * popl %ebx | |
8632 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
8633 | * | |
8634 | * The call and pop essentially return the absolute address | |
8635 | * of the label .L66 and store it in %ebx. The linker itself | |
8636 | * will ultimately change the first operand of the addl so | |
8637 | * that %ebx points to the GOT, but to keep things simple, the | |
8638 | * .o file must have this operand set so that it generates not | |
8639 | * the absolute address of .L66, but the absolute address of | |
8640 | * itself. This allows the linker itself simply treat a GOTPC | |
8641 | * relocation as asking for a pcrel offset to the GOT to be | |
8642 | * added in, and the addend of the relocation is stored in the | |
8643 | * operand field for the instruction itself. | |
8644 | * | |
8645 | * Our job here is to fix the operand so that it would add | |
8646 | * the correct offset so that %ebx would point to itself. The | |
8647 | * thing that is tricky is that .-.L66 will point to the | |
8648 | * beginning of the instruction, so we need to further modify | |
8649 | * the operand so that it will point to itself. There are | |
8650 | * other cases where you have something like: | |
8651 | * | |
8652 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
8653 | * | |
8654 | * and here no correction would be required. Internally in | |
8655 | * the assembler we treat operands of this form as not being | |
8656 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
8657 | * whether it would simplify matters to do it this way. Who | |
8658 | * knows. In earlier versions of the PIC patches, the | |
8659 | * pcrel_adjust field was used to store the correction, but | |
8660 | * since the expression is not pcrel, I felt it would be | |
8661 | * confusing to do it this way. */ | |
8662 | ||
d6ab8113 | 8663 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
8664 | || reloc_type == BFD_RELOC_X86_64_32S |
8665 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
8666 | && GOT_symbol |
8667 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
8668 | && (i.op[n].imms->X_op == O_symbol | |
8669 | || (i.op[n].imms->X_op == O_add | |
8670 | && ((symbol_get_value_expression | |
8671 | (i.op[n].imms->X_op_symbol)->X_op) | |
8672 | == O_subtract)))) | |
8673 | { | |
2bbd9c25 JJ |
8674 | offsetT add; |
8675 | ||
8676 | if (insn_start_frag == frag_now) | |
8677 | add = (p - frag_now->fr_literal) - insn_start_off; | |
8678 | else | |
8679 | { | |
8680 | fragS *fr; | |
8681 | ||
8682 | add = insn_start_frag->fr_fix - insn_start_off; | |
8683 | for (fr = insn_start_frag->fr_next; | |
8684 | fr && fr != frag_now; fr = fr->fr_next) | |
8685 | add += fr->fr_fix; | |
8686 | add += p - frag_now->fr_literal; | |
8687 | } | |
8688 | ||
4fa24527 | 8689 | if (!object_64bit) |
d6ab8113 | 8690 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 8691 | else if (size == 4) |
d6ab8113 | 8692 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
8693 | else if (size == 8) |
8694 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
2bbd9c25 | 8695 | i.op[n].imms->X_add_number += add; |
29b0f896 | 8696 | } |
29b0f896 AM |
8697 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
8698 | i.op[n].imms, 0, reloc_type); | |
8699 | } | |
8700 | } | |
8701 | } | |
252b5132 RH |
8702 | } |
8703 | \f | |
d182319b JB |
8704 | /* x86_cons_fix_new is called via the expression parsing code when a |
8705 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
8706 | static int cons_sign = -1; |
8707 | ||
8708 | void | |
e3bb37b5 | 8709 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 8710 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 8711 | { |
d258b828 | 8712 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
8713 | |
8714 | #ifdef TE_PE | |
8715 | if (exp->X_op == O_secrel) | |
8716 | { | |
8717 | exp->X_op = O_symbol; | |
8718 | r = BFD_RELOC_32_SECREL; | |
8719 | } | |
8720 | #endif | |
8721 | ||
8722 | fix_new_exp (frag, off, len, exp, 0, r); | |
8723 | } | |
8724 | ||
357d1bd8 L |
8725 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
8726 | purpose of the `.dc.a' internal pseudo-op. */ | |
8727 | ||
8728 | int | |
8729 | x86_address_bytes (void) | |
8730 | { | |
8731 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
8732 | return 4; | |
8733 | return stdoutput->arch_info->bits_per_address / 8; | |
8734 | } | |
8735 | ||
d382c579 TG |
8736 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
8737 | || defined (LEX_AT) | |
d258b828 | 8738 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 8739 | #else |
f3c180ae AM |
8740 | /* Parse operands of the form |
8741 | <symbol>@GOTOFF+<nnn> | |
8742 | and similar .plt or .got references. | |
8743 | ||
8744 | If we find one, set up the correct relocation in RELOC and copy the | |
8745 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
8746 | parsing by the calling routine. Return this buffer, and if ADJUST | |
8747 | is non-null set it to the length of the string we removed from the | |
8748 | input line. Otherwise return NULL. */ | |
8749 | static char * | |
91d6fa6a | 8750 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 8751 | int *adjust, |
d258b828 | 8752 | i386_operand_type *types) |
f3c180ae | 8753 | { |
7b81dfbb AJ |
8754 | /* Some of the relocations depend on the size of what field is to |
8755 | be relocated. But in our callers i386_immediate and i386_displacement | |
8756 | we don't yet know the operand size (this will be set by insn | |
8757 | matching). Hence we record the word32 relocation here, | |
8758 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
8759 | static const struct { |
8760 | const char *str; | |
cff8d58a | 8761 | int len; |
4fa24527 | 8762 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 8763 | const i386_operand_type types64; |
f3c180ae | 8764 | } gotrel[] = { |
8ce3d284 | 8765 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
8766 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
8767 | BFD_RELOC_SIZE32 }, | |
8768 | OPERAND_TYPE_IMM32_64 }, | |
8ce3d284 | 8769 | #endif |
cff8d58a L |
8770 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
8771 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 8772 | OPERAND_TYPE_IMM64 }, |
cff8d58a L |
8773 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
8774 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 8775 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8776 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
8777 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 8778 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
8779 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
8780 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 8781 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
8782 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
8783 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 8784 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8785 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
8786 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 8787 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8788 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
8789 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8790 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8791 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
8792 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 8793 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8794 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
8795 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 8796 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8797 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
8798 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 8799 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
8800 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
8801 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8802 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8803 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
8804 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 | 8805 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
8806 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
8807 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8808 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8809 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
8810 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8811 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8812 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
8813 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 8814 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
cff8d58a L |
8815 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
8816 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 8817 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8818 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
8819 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 8820 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
8821 | }; |
8822 | char *cp; | |
8823 | unsigned int j; | |
8824 | ||
d382c579 | 8825 | #if defined (OBJ_MAYBE_ELF) |
718ddfc0 JB |
8826 | if (!IS_ELF) |
8827 | return NULL; | |
d382c579 | 8828 | #endif |
718ddfc0 | 8829 | |
f3c180ae | 8830 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 8831 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
8832 | return NULL; |
8833 | ||
47465058 | 8834 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 8835 | { |
cff8d58a | 8836 | int len = gotrel[j].len; |
28f81592 | 8837 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 8838 | { |
4fa24527 | 8839 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 8840 | { |
28f81592 AM |
8841 | int first, second; |
8842 | char *tmpbuf, *past_reloc; | |
f3c180ae | 8843 | |
91d6fa6a | 8844 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 8845 | |
3956db08 JB |
8846 | if (types) |
8847 | { | |
8848 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
8849 | { |
8850 | types->bitfield.imm32 = 1; | |
8851 | types->bitfield.disp32 = 1; | |
8852 | } | |
3956db08 JB |
8853 | else |
8854 | *types = gotrel[j].types64; | |
8855 | } | |
8856 | ||
8fd4256d | 8857 | if (j != 0 && GOT_symbol == NULL) |
f3c180ae AM |
8858 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
8859 | ||
28f81592 | 8860 | /* The length of the first part of our input line. */ |
f3c180ae | 8861 | first = cp - input_line_pointer; |
28f81592 AM |
8862 | |
8863 | /* The second part goes from after the reloc token until | |
67c11a9b | 8864 | (and including) an end_of_line char or comma. */ |
28f81592 | 8865 | past_reloc = cp + 1 + len; |
67c11a9b AM |
8866 | cp = past_reloc; |
8867 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
8868 | ++cp; | |
8869 | second = cp + 1 - past_reloc; | |
28f81592 AM |
8870 | |
8871 | /* Allocate and copy string. The trailing NUL shouldn't | |
8872 | be necessary, but be safe. */ | |
add39d23 | 8873 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 8874 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
8875 | if (second != 0 && *past_reloc != ' ') |
8876 | /* Replace the relocation token with ' ', so that | |
8877 | errors like foo@GOTOFF1 will be detected. */ | |
8878 | tmpbuf[first++] = ' '; | |
af89796a L |
8879 | else |
8880 | /* Increment length by 1 if the relocation token is | |
8881 | removed. */ | |
8882 | len++; | |
8883 | if (adjust) | |
8884 | *adjust = len; | |
0787a12d AM |
8885 | memcpy (tmpbuf + first, past_reloc, second); |
8886 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
8887 | return tmpbuf; |
8888 | } | |
8889 | ||
4fa24527 JB |
8890 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
8891 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
8892 | return NULL; |
8893 | } | |
8894 | } | |
8895 | ||
8896 | /* Might be a symbol version string. Don't as_bad here. */ | |
8897 | return NULL; | |
8898 | } | |
4e4f7c87 | 8899 | #endif |
f3c180ae | 8900 | |
a988325c NC |
8901 | #ifdef TE_PE |
8902 | #ifdef lex_got | |
8903 | #undef lex_got | |
8904 | #endif | |
8905 | /* Parse operands of the form | |
8906 | <symbol>@SECREL32+<nnn> | |
8907 | ||
8908 | If we find one, set up the correct relocation in RELOC and copy the | |
8909 | input string, minus the `@SECREL32' into a malloc'd buffer for | |
8910 | parsing by the calling routine. Return this buffer, and if ADJUST | |
8911 | is non-null set it to the length of the string we removed from the | |
34bca508 L |
8912 | input line. Otherwise return NULL. |
8913 | ||
a988325c NC |
8914 | This function is copied from the ELF version above adjusted for PE targets. */ |
8915 | ||
8916 | static char * | |
8917 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, | |
8918 | int *adjust ATTRIBUTE_UNUSED, | |
d258b828 | 8919 | i386_operand_type *types) |
a988325c NC |
8920 | { |
8921 | static const struct | |
8922 | { | |
8923 | const char *str; | |
8924 | int len; | |
8925 | const enum bfd_reloc_code_real rel[2]; | |
8926 | const i386_operand_type types64; | |
8927 | } | |
8928 | gotrel[] = | |
8929 | { | |
8930 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
8931 | BFD_RELOC_32_SECREL }, | |
8932 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
8933 | }; | |
8934 | ||
8935 | char *cp; | |
8936 | unsigned j; | |
8937 | ||
8938 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
8939 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') | |
8940 | return NULL; | |
8941 | ||
8942 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) | |
8943 | { | |
8944 | int len = gotrel[j].len; | |
8945 | ||
8946 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) | |
8947 | { | |
8948 | if (gotrel[j].rel[object_64bit] != 0) | |
8949 | { | |
8950 | int first, second; | |
8951 | char *tmpbuf, *past_reloc; | |
8952 | ||
8953 | *rel = gotrel[j].rel[object_64bit]; | |
8954 | if (adjust) | |
8955 | *adjust = len; | |
8956 | ||
8957 | if (types) | |
8958 | { | |
8959 | if (flag_code != CODE_64BIT) | |
8960 | { | |
8961 | types->bitfield.imm32 = 1; | |
8962 | types->bitfield.disp32 = 1; | |
8963 | } | |
8964 | else | |
8965 | *types = gotrel[j].types64; | |
8966 | } | |
8967 | ||
8968 | /* The length of the first part of our input line. */ | |
8969 | first = cp - input_line_pointer; | |
8970 | ||
8971 | /* The second part goes from after the reloc token until | |
8972 | (and including) an end_of_line char or comma. */ | |
8973 | past_reloc = cp + 1 + len; | |
8974 | cp = past_reloc; | |
8975 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
8976 | ++cp; | |
8977 | second = cp + 1 - past_reloc; | |
8978 | ||
8979 | /* Allocate and copy string. The trailing NUL shouldn't | |
8980 | be necessary, but be safe. */ | |
add39d23 | 8981 | tmpbuf = XNEWVEC (char, first + second + 2); |
a988325c NC |
8982 | memcpy (tmpbuf, input_line_pointer, first); |
8983 | if (second != 0 && *past_reloc != ' ') | |
8984 | /* Replace the relocation token with ' ', so that | |
8985 | errors like foo@SECLREL321 will be detected. */ | |
8986 | tmpbuf[first++] = ' '; | |
8987 | memcpy (tmpbuf + first, past_reloc, second); | |
8988 | tmpbuf[first + second] = '\0'; | |
8989 | return tmpbuf; | |
8990 | } | |
8991 | ||
8992 | as_bad (_("@%s reloc is not supported with %d-bit output format"), | |
8993 | gotrel[j].str, 1 << (5 + object_64bit)); | |
8994 | return NULL; | |
8995 | } | |
8996 | } | |
8997 | ||
8998 | /* Might be a symbol version string. Don't as_bad here. */ | |
8999 | return NULL; | |
9000 | } | |
9001 | ||
9002 | #endif /* TE_PE */ | |
9003 | ||
62ebcb5c | 9004 | bfd_reloc_code_real_type |
e3bb37b5 | 9005 | x86_cons (expressionS *exp, int size) |
f3c180ae | 9006 | { |
62ebcb5c AM |
9007 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
9008 | ||
ee86248c JB |
9009 | intel_syntax = -intel_syntax; |
9010 | ||
3c7b9c2c | 9011 | exp->X_md = 0; |
4fa24527 | 9012 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
9013 | { |
9014 | /* Handle @GOTOFF and the like in an expression. */ | |
9015 | char *save; | |
9016 | char *gotfree_input_line; | |
4a57f2cf | 9017 | int adjust = 0; |
f3c180ae AM |
9018 | |
9019 | save = input_line_pointer; | |
d258b828 | 9020 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
9021 | if (gotfree_input_line) |
9022 | input_line_pointer = gotfree_input_line; | |
9023 | ||
9024 | expression (exp); | |
9025 | ||
9026 | if (gotfree_input_line) | |
9027 | { | |
9028 | /* expression () has merrily parsed up to the end of line, | |
9029 | or a comma - in the wrong buffer. Transfer how far | |
9030 | input_line_pointer has moved to the right buffer. */ | |
9031 | input_line_pointer = (save | |
9032 | + (input_line_pointer - gotfree_input_line) | |
9033 | + adjust); | |
9034 | free (gotfree_input_line); | |
3992d3b7 AM |
9035 | if (exp->X_op == O_constant |
9036 | || exp->X_op == O_absent | |
9037 | || exp->X_op == O_illegal | |
0398aac5 | 9038 | || exp->X_op == O_register |
3992d3b7 AM |
9039 | || exp->X_op == O_big) |
9040 | { | |
9041 | char c = *input_line_pointer; | |
9042 | *input_line_pointer = 0; | |
9043 | as_bad (_("missing or invalid expression `%s'"), save); | |
9044 | *input_line_pointer = c; | |
9045 | } | |
b9519cfe L |
9046 | else if ((got_reloc == BFD_RELOC_386_PLT32 |
9047 | || got_reloc == BFD_RELOC_X86_64_PLT32) | |
9048 | && exp->X_op != O_symbol) | |
9049 | { | |
9050 | char c = *input_line_pointer; | |
9051 | *input_line_pointer = 0; | |
9052 | as_bad (_("invalid PLT expression `%s'"), save); | |
9053 | *input_line_pointer = c; | |
9054 | } | |
f3c180ae AM |
9055 | } |
9056 | } | |
9057 | else | |
9058 | expression (exp); | |
ee86248c JB |
9059 | |
9060 | intel_syntax = -intel_syntax; | |
9061 | ||
9062 | if (intel_syntax) | |
9063 | i386_intel_simplify (exp); | |
62ebcb5c AM |
9064 | |
9065 | return got_reloc; | |
f3c180ae | 9066 | } |
f3c180ae | 9067 | |
9f32dd5b L |
9068 | static void |
9069 | signed_cons (int size) | |
6482c264 | 9070 | { |
d182319b JB |
9071 | if (flag_code == CODE_64BIT) |
9072 | cons_sign = 1; | |
9073 | cons (size); | |
9074 | cons_sign = -1; | |
6482c264 NC |
9075 | } |
9076 | ||
d182319b | 9077 | #ifdef TE_PE |
6482c264 | 9078 | static void |
7016a5d5 | 9079 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
9080 | { |
9081 | expressionS exp; | |
9082 | ||
9083 | do | |
9084 | { | |
9085 | expression (&exp); | |
9086 | if (exp.X_op == O_symbol) | |
9087 | exp.X_op = O_secrel; | |
9088 | ||
9089 | emit_expr (&exp, 4); | |
9090 | } | |
9091 | while (*input_line_pointer++ == ','); | |
9092 | ||
9093 | input_line_pointer--; | |
9094 | demand_empty_rest_of_line (); | |
9095 | } | |
6482c264 NC |
9096 | #endif |
9097 | ||
43234a1e L |
9098 | /* Handle Vector operations. */ |
9099 | ||
9100 | static char * | |
9101 | check_VecOperations (char *op_string, char *op_end) | |
9102 | { | |
9103 | const reg_entry *mask; | |
9104 | const char *saved; | |
9105 | char *end_op; | |
9106 | ||
9107 | while (*op_string | |
9108 | && (op_end == NULL || op_string < op_end)) | |
9109 | { | |
9110 | saved = op_string; | |
9111 | if (*op_string == '{') | |
9112 | { | |
9113 | op_string++; | |
9114 | ||
9115 | /* Check broadcasts. */ | |
9116 | if (strncmp (op_string, "1to", 3) == 0) | |
9117 | { | |
9118 | int bcst_type; | |
9119 | ||
9120 | if (i.broadcast) | |
9121 | goto duplicated_vec_op; | |
9122 | ||
9123 | op_string += 3; | |
9124 | if (*op_string == '8') | |
8e6e0792 | 9125 | bcst_type = 8; |
b28d1bda | 9126 | else if (*op_string == '4') |
8e6e0792 | 9127 | bcst_type = 4; |
b28d1bda | 9128 | else if (*op_string == '2') |
8e6e0792 | 9129 | bcst_type = 2; |
43234a1e L |
9130 | else if (*op_string == '1' |
9131 | && *(op_string+1) == '6') | |
9132 | { | |
8e6e0792 | 9133 | bcst_type = 16; |
43234a1e L |
9134 | op_string++; |
9135 | } | |
9136 | else | |
9137 | { | |
9138 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
9139 | return NULL; | |
9140 | } | |
9141 | op_string++; | |
9142 | ||
9143 | broadcast_op.type = bcst_type; | |
9144 | broadcast_op.operand = this_operand; | |
1f75763a | 9145 | broadcast_op.bytes = 0; |
43234a1e L |
9146 | i.broadcast = &broadcast_op; |
9147 | } | |
9148 | /* Check masking operation. */ | |
9149 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
9150 | { | |
9151 | /* k0 can't be used for write mask. */ | |
6d2cd6b2 | 9152 | if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0) |
43234a1e | 9153 | { |
6d2cd6b2 JB |
9154 | as_bad (_("`%s%s' can't be used for write mask"), |
9155 | register_prefix, mask->reg_name); | |
43234a1e L |
9156 | return NULL; |
9157 | } | |
9158 | ||
9159 | if (!i.mask) | |
9160 | { | |
9161 | mask_op.mask = mask; | |
9162 | mask_op.zeroing = 0; | |
9163 | mask_op.operand = this_operand; | |
9164 | i.mask = &mask_op; | |
9165 | } | |
9166 | else | |
9167 | { | |
9168 | if (i.mask->mask) | |
9169 | goto duplicated_vec_op; | |
9170 | ||
9171 | i.mask->mask = mask; | |
9172 | ||
9173 | /* Only "{z}" is allowed here. No need to check | |
9174 | zeroing mask explicitly. */ | |
9175 | if (i.mask->operand != this_operand) | |
9176 | { | |
9177 | as_bad (_("invalid write mask `%s'"), saved); | |
9178 | return NULL; | |
9179 | } | |
9180 | } | |
9181 | ||
9182 | op_string = end_op; | |
9183 | } | |
9184 | /* Check zeroing-flag for masking operation. */ | |
9185 | else if (*op_string == 'z') | |
9186 | { | |
9187 | if (!i.mask) | |
9188 | { | |
9189 | mask_op.mask = NULL; | |
9190 | mask_op.zeroing = 1; | |
9191 | mask_op.operand = this_operand; | |
9192 | i.mask = &mask_op; | |
9193 | } | |
9194 | else | |
9195 | { | |
9196 | if (i.mask->zeroing) | |
9197 | { | |
9198 | duplicated_vec_op: | |
9199 | as_bad (_("duplicated `%s'"), saved); | |
9200 | return NULL; | |
9201 | } | |
9202 | ||
9203 | i.mask->zeroing = 1; | |
9204 | ||
9205 | /* Only "{%k}" is allowed here. No need to check mask | |
9206 | register explicitly. */ | |
9207 | if (i.mask->operand != this_operand) | |
9208 | { | |
9209 | as_bad (_("invalid zeroing-masking `%s'"), | |
9210 | saved); | |
9211 | return NULL; | |
9212 | } | |
9213 | } | |
9214 | ||
9215 | op_string++; | |
9216 | } | |
9217 | else | |
9218 | goto unknown_vec_op; | |
9219 | ||
9220 | if (*op_string != '}') | |
9221 | { | |
9222 | as_bad (_("missing `}' in `%s'"), saved); | |
9223 | return NULL; | |
9224 | } | |
9225 | op_string++; | |
0ba3a731 L |
9226 | |
9227 | /* Strip whitespace since the addition of pseudo prefixes | |
9228 | changed how the scrubber treats '{'. */ | |
9229 | if (is_space_char (*op_string)) | |
9230 | ++op_string; | |
9231 | ||
43234a1e L |
9232 | continue; |
9233 | } | |
9234 | unknown_vec_op: | |
9235 | /* We don't know this one. */ | |
9236 | as_bad (_("unknown vector operation: `%s'"), saved); | |
9237 | return NULL; | |
9238 | } | |
9239 | ||
6d2cd6b2 JB |
9240 | if (i.mask && i.mask->zeroing && !i.mask->mask) |
9241 | { | |
9242 | as_bad (_("zeroing-masking only allowed with write mask")); | |
9243 | return NULL; | |
9244 | } | |
9245 | ||
43234a1e L |
9246 | return op_string; |
9247 | } | |
9248 | ||
252b5132 | 9249 | static int |
70e41ade | 9250 | i386_immediate (char *imm_start) |
252b5132 RH |
9251 | { |
9252 | char *save_input_line_pointer; | |
f3c180ae | 9253 | char *gotfree_input_line; |
252b5132 | 9254 | segT exp_seg = 0; |
47926f60 | 9255 | expressionS *exp; |
40fb9820 L |
9256 | i386_operand_type types; |
9257 | ||
0dfbf9d7 | 9258 | operand_type_set (&types, ~0); |
252b5132 RH |
9259 | |
9260 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
9261 | { | |
31b2323c L |
9262 | as_bad (_("at most %d immediate operands are allowed"), |
9263 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
9264 | return 0; |
9265 | } | |
9266 | ||
9267 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 9268 | i.op[this_operand].imms = exp; |
252b5132 RH |
9269 | |
9270 | if (is_space_char (*imm_start)) | |
9271 | ++imm_start; | |
9272 | ||
9273 | save_input_line_pointer = input_line_pointer; | |
9274 | input_line_pointer = imm_start; | |
9275 | ||
d258b828 | 9276 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
9277 | if (gotfree_input_line) |
9278 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
9279 | |
9280 | exp_seg = expression (exp); | |
9281 | ||
83183c0c | 9282 | SKIP_WHITESPACE (); |
43234a1e L |
9283 | |
9284 | /* Handle vector operations. */ | |
9285 | if (*input_line_pointer == '{') | |
9286 | { | |
9287 | input_line_pointer = check_VecOperations (input_line_pointer, | |
9288 | NULL); | |
9289 | if (input_line_pointer == NULL) | |
9290 | return 0; | |
9291 | } | |
9292 | ||
252b5132 | 9293 | if (*input_line_pointer) |
f3c180ae | 9294 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
9295 | |
9296 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 9297 | if (gotfree_input_line) |
ee86248c JB |
9298 | { |
9299 | free (gotfree_input_line); | |
9300 | ||
9301 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
9302 | exp->X_op = O_illegal; | |
9303 | } | |
9304 | ||
9305 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
9306 | } | |
252b5132 | 9307 | |
ee86248c JB |
9308 | static int |
9309 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
9310 | i386_operand_type types, const char *imm_start) | |
9311 | { | |
9312 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 9313 | { |
313c53d1 L |
9314 | if (imm_start) |
9315 | as_bad (_("missing or invalid immediate expression `%s'"), | |
9316 | imm_start); | |
3992d3b7 | 9317 | return 0; |
252b5132 | 9318 | } |
3e73aa7c | 9319 | else if (exp->X_op == O_constant) |
252b5132 | 9320 | { |
47926f60 | 9321 | /* Size it properly later. */ |
40fb9820 | 9322 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
9323 | /* If not 64bit, sign extend val. */ |
9324 | if (flag_code != CODE_64BIT | |
4eed87de AM |
9325 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
9326 | exp->X_add_number | |
9327 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 9328 | } |
4c63da97 | 9329 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 9330 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 9331 | && exp_seg != absolute_section |
47926f60 | 9332 | && exp_seg != text_section |
24eab124 AM |
9333 | && exp_seg != data_section |
9334 | && exp_seg != bss_section | |
9335 | && exp_seg != undefined_section | |
f86103b7 | 9336 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 9337 | { |
d0b47220 | 9338 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
9339 | return 0; |
9340 | } | |
9341 | #endif | |
a841bdf5 | 9342 | else if (!intel_syntax && exp_seg == reg_section) |
bb8f5920 | 9343 | { |
313c53d1 L |
9344 | if (imm_start) |
9345 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
bb8f5920 L |
9346 | return 0; |
9347 | } | |
252b5132 RH |
9348 | else |
9349 | { | |
9350 | /* This is an address. The size of the address will be | |
24eab124 | 9351 | determined later, depending on destination register, |
3e73aa7c | 9352 | suffix, or the default for the section. */ |
40fb9820 L |
9353 | i.types[this_operand].bitfield.imm8 = 1; |
9354 | i.types[this_operand].bitfield.imm16 = 1; | |
9355 | i.types[this_operand].bitfield.imm32 = 1; | |
9356 | i.types[this_operand].bitfield.imm32s = 1; | |
9357 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
9358 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
9359 | types); | |
252b5132 RH |
9360 | } |
9361 | ||
9362 | return 1; | |
9363 | } | |
9364 | ||
551c1ca1 | 9365 | static char * |
e3bb37b5 | 9366 | i386_scale (char *scale) |
252b5132 | 9367 | { |
551c1ca1 AM |
9368 | offsetT val; |
9369 | char *save = input_line_pointer; | |
252b5132 | 9370 | |
551c1ca1 AM |
9371 | input_line_pointer = scale; |
9372 | val = get_absolute_expression (); | |
9373 | ||
9374 | switch (val) | |
252b5132 | 9375 | { |
551c1ca1 | 9376 | case 1: |
252b5132 RH |
9377 | i.log2_scale_factor = 0; |
9378 | break; | |
551c1ca1 | 9379 | case 2: |
252b5132 RH |
9380 | i.log2_scale_factor = 1; |
9381 | break; | |
551c1ca1 | 9382 | case 4: |
252b5132 RH |
9383 | i.log2_scale_factor = 2; |
9384 | break; | |
551c1ca1 | 9385 | case 8: |
252b5132 RH |
9386 | i.log2_scale_factor = 3; |
9387 | break; | |
9388 | default: | |
a724f0f4 JB |
9389 | { |
9390 | char sep = *input_line_pointer; | |
9391 | ||
9392 | *input_line_pointer = '\0'; | |
9393 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
9394 | scale); | |
9395 | *input_line_pointer = sep; | |
9396 | input_line_pointer = save; | |
9397 | return NULL; | |
9398 | } | |
252b5132 | 9399 | } |
29b0f896 | 9400 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
9401 | { |
9402 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 9403 | 1 << i.log2_scale_factor); |
252b5132 | 9404 | i.log2_scale_factor = 0; |
252b5132 | 9405 | } |
551c1ca1 AM |
9406 | scale = input_line_pointer; |
9407 | input_line_pointer = save; | |
9408 | return scale; | |
252b5132 RH |
9409 | } |
9410 | ||
252b5132 | 9411 | static int |
e3bb37b5 | 9412 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 9413 | { |
29b0f896 | 9414 | expressionS *exp; |
252b5132 RH |
9415 | segT exp_seg = 0; |
9416 | char *save_input_line_pointer; | |
f3c180ae | 9417 | char *gotfree_input_line; |
40fb9820 L |
9418 | int override; |
9419 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 9420 | int ret; |
252b5132 | 9421 | |
31b2323c L |
9422 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
9423 | { | |
9424 | as_bad (_("at most %d displacement operands are allowed"), | |
9425 | MAX_MEMORY_OPERANDS); | |
9426 | return 0; | |
9427 | } | |
9428 | ||
0dfbf9d7 | 9429 | operand_type_set (&bigdisp, 0); |
40fb9820 L |
9430 | if ((i.types[this_operand].bitfield.jumpabsolute) |
9431 | || (!current_templates->start->opcode_modifier.jump | |
9432 | && !current_templates->start->opcode_modifier.jumpdword)) | |
e05278af | 9433 | { |
40fb9820 | 9434 | bigdisp.bitfield.disp32 = 1; |
e05278af | 9435 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
9436 | if (flag_code == CODE_64BIT) |
9437 | { | |
9438 | if (!override) | |
9439 | { | |
9440 | bigdisp.bitfield.disp32s = 1; | |
9441 | bigdisp.bitfield.disp64 = 1; | |
9442 | } | |
9443 | } | |
9444 | else if ((flag_code == CODE_16BIT) ^ override) | |
9445 | { | |
9446 | bigdisp.bitfield.disp32 = 0; | |
9447 | bigdisp.bitfield.disp16 = 1; | |
9448 | } | |
e05278af JB |
9449 | } |
9450 | else | |
9451 | { | |
9452 | /* For PC-relative branches, the width of the displacement | |
9453 | is dependent upon data size, not address size. */ | |
e05278af | 9454 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
9455 | if (flag_code == CODE_64BIT) |
9456 | { | |
9457 | if (override || i.suffix == WORD_MNEM_SUFFIX) | |
9458 | bigdisp.bitfield.disp16 = 1; | |
9459 | else | |
9460 | { | |
9461 | bigdisp.bitfield.disp32 = 1; | |
9462 | bigdisp.bitfield.disp32s = 1; | |
9463 | } | |
9464 | } | |
9465 | else | |
e05278af JB |
9466 | { |
9467 | if (!override) | |
9468 | override = (i.suffix == (flag_code != CODE_16BIT | |
9469 | ? WORD_MNEM_SUFFIX | |
9470 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
9471 | bigdisp.bitfield.disp32 = 1; |
9472 | if ((flag_code == CODE_16BIT) ^ override) | |
9473 | { | |
9474 | bigdisp.bitfield.disp32 = 0; | |
9475 | bigdisp.bitfield.disp16 = 1; | |
9476 | } | |
e05278af | 9477 | } |
e05278af | 9478 | } |
c6fb90c8 L |
9479 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
9480 | bigdisp); | |
252b5132 RH |
9481 | |
9482 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 9483 | i.op[this_operand].disps = exp; |
252b5132 RH |
9484 | i.disp_operands++; |
9485 | save_input_line_pointer = input_line_pointer; | |
9486 | input_line_pointer = disp_start; | |
9487 | END_STRING_AND_SAVE (disp_end); | |
9488 | ||
9489 | #ifndef GCC_ASM_O_HACK | |
9490 | #define GCC_ASM_O_HACK 0 | |
9491 | #endif | |
9492 | #if GCC_ASM_O_HACK | |
9493 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 9494 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 9495 | && displacement_string_end[-1] == '+') |
252b5132 RH |
9496 | { |
9497 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
9498 | constraint within gcc asm statements. |
9499 | For instance: | |
9500 | ||
9501 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
9502 | __asm__ __volatile__ ( \ | |
9503 | "movw %w2,%0\n\t" \ | |
9504 | "movw %w1,2+%0\n\t" \ | |
9505 | "rorl $16,%1\n\t" \ | |
9506 | "movb %b1,4+%0\n\t" \ | |
9507 | "movb %4,5+%0\n\t" \ | |
9508 | "movb $0,6+%0\n\t" \ | |
9509 | "movb %h1,7+%0\n\t" \ | |
9510 | "rorl $16,%1" \ | |
9511 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
9512 | ||
9513 | This works great except that the output assembler ends | |
9514 | up looking a bit weird if it turns out that there is | |
9515 | no offset. You end up producing code that looks like: | |
9516 | ||
9517 | #APP | |
9518 | movw $235,(%eax) | |
9519 | movw %dx,2+(%eax) | |
9520 | rorl $16,%edx | |
9521 | movb %dl,4+(%eax) | |
9522 | movb $137,5+(%eax) | |
9523 | movb $0,6+(%eax) | |
9524 | movb %dh,7+(%eax) | |
9525 | rorl $16,%edx | |
9526 | #NO_APP | |
9527 | ||
47926f60 | 9528 | So here we provide the missing zero. */ |
24eab124 AM |
9529 | |
9530 | *displacement_string_end = '0'; | |
252b5132 RH |
9531 | } |
9532 | #endif | |
d258b828 | 9533 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
9534 | if (gotfree_input_line) |
9535 | input_line_pointer = gotfree_input_line; | |
252b5132 | 9536 | |
24eab124 | 9537 | exp_seg = expression (exp); |
252b5132 | 9538 | |
636c26b0 AM |
9539 | SKIP_WHITESPACE (); |
9540 | if (*input_line_pointer) | |
9541 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
9542 | #if GCC_ASM_O_HACK | |
9543 | RESTORE_END_STRING (disp_end + 1); | |
9544 | #endif | |
636c26b0 | 9545 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 9546 | if (gotfree_input_line) |
ee86248c JB |
9547 | { |
9548 | free (gotfree_input_line); | |
9549 | ||
9550 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
9551 | exp->X_op = O_illegal; | |
9552 | } | |
9553 | ||
9554 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
9555 | ||
9556 | RESTORE_END_STRING (disp_end); | |
9557 | ||
9558 | return ret; | |
9559 | } | |
9560 | ||
9561 | static int | |
9562 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
9563 | i386_operand_type types, const char *disp_start) | |
9564 | { | |
9565 | i386_operand_type bigdisp; | |
9566 | int ret = 1; | |
636c26b0 | 9567 | |
24eab124 AM |
9568 | /* We do this to make sure that the section symbol is in |
9569 | the symbol table. We will ultimately change the relocation | |
47926f60 | 9570 | to be relative to the beginning of the section. */ |
1ae12ab7 | 9571 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
9572 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
9573 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 9574 | { |
636c26b0 | 9575 | if (exp->X_op != O_symbol) |
3992d3b7 | 9576 | goto inv_disp; |
636c26b0 | 9577 | |
e5cb08ac | 9578 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
9579 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
9580 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 9581 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
9582 | exp->X_op = O_subtract; |
9583 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 9584 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 9585 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
9586 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
9587 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 9588 | else |
29b0f896 | 9589 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 9590 | } |
252b5132 | 9591 | |
3992d3b7 AM |
9592 | else if (exp->X_op == O_absent |
9593 | || exp->X_op == O_illegal | |
ee86248c | 9594 | || exp->X_op == O_big) |
2daf4fd8 | 9595 | { |
3992d3b7 AM |
9596 | inv_disp: |
9597 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 9598 | disp_start); |
3992d3b7 | 9599 | ret = 0; |
2daf4fd8 AM |
9600 | } |
9601 | ||
0e1147d9 L |
9602 | else if (flag_code == CODE_64BIT |
9603 | && !i.prefix[ADDR_PREFIX] | |
9604 | && exp->X_op == O_constant) | |
9605 | { | |
9606 | /* Since displacement is signed extended to 64bit, don't allow | |
9607 | disp32 and turn off disp32s if they are out of range. */ | |
9608 | i.types[this_operand].bitfield.disp32 = 0; | |
9609 | if (!fits_in_signed_long (exp->X_add_number)) | |
9610 | { | |
9611 | i.types[this_operand].bitfield.disp32s = 0; | |
9612 | if (i.types[this_operand].bitfield.baseindex) | |
9613 | { | |
9614 | as_bad (_("0x%lx out range of signed 32bit displacement"), | |
9615 | (long) exp->X_add_number); | |
9616 | ret = 0; | |
9617 | } | |
9618 | } | |
9619 | } | |
9620 | ||
4c63da97 | 9621 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
9622 | else if (exp->X_op != O_constant |
9623 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
9624 | && exp_seg != absolute_section | |
9625 | && exp_seg != text_section | |
9626 | && exp_seg != data_section | |
9627 | && exp_seg != bss_section | |
9628 | && exp_seg != undefined_section | |
9629 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 9630 | { |
d0b47220 | 9631 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 9632 | ret = 0; |
24eab124 | 9633 | } |
252b5132 | 9634 | #endif |
3956db08 | 9635 | |
40fb9820 L |
9636 | /* Check if this is a displacement only operand. */ |
9637 | bigdisp = i.types[this_operand]; | |
9638 | bigdisp.bitfield.disp8 = 0; | |
9639 | bigdisp.bitfield.disp16 = 0; | |
9640 | bigdisp.bitfield.disp32 = 0; | |
9641 | bigdisp.bitfield.disp32s = 0; | |
9642 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 9643 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
9644 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
9645 | types); | |
3956db08 | 9646 | |
3992d3b7 | 9647 | return ret; |
252b5132 RH |
9648 | } |
9649 | ||
2abc2bec JB |
9650 | /* Return the active addressing mode, taking address override and |
9651 | registers forming the address into consideration. Update the | |
9652 | address override prefix if necessary. */ | |
47926f60 | 9653 | |
2abc2bec JB |
9654 | static enum flag_code |
9655 | i386_addressing_mode (void) | |
252b5132 | 9656 | { |
be05d201 L |
9657 | enum flag_code addr_mode; |
9658 | ||
9659 | if (i.prefix[ADDR_PREFIX]) | |
9660 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
9661 | else | |
9662 | { | |
9663 | addr_mode = flag_code; | |
9664 | ||
24eab124 | 9665 | #if INFER_ADDR_PREFIX |
be05d201 L |
9666 | if (i.mem_operands == 0) |
9667 | { | |
9668 | /* Infer address prefix from the first memory operand. */ | |
9669 | const reg_entry *addr_reg = i.base_reg; | |
9670 | ||
9671 | if (addr_reg == NULL) | |
9672 | addr_reg = i.index_reg; | |
eecb386c | 9673 | |
be05d201 L |
9674 | if (addr_reg) |
9675 | { | |
e968fc9b | 9676 | if (addr_reg->reg_type.bitfield.dword) |
be05d201 L |
9677 | addr_mode = CODE_32BIT; |
9678 | else if (flag_code != CODE_64BIT | |
dc821c5f | 9679 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
9680 | addr_mode = CODE_16BIT; |
9681 | ||
9682 | if (addr_mode != flag_code) | |
9683 | { | |
9684 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
9685 | i.prefixes += 1; | |
9686 | /* Change the size of any displacement too. At most one | |
9687 | of Disp16 or Disp32 is set. | |
9688 | FIXME. There doesn't seem to be any real need for | |
9689 | separate Disp16 and Disp32 flags. The same goes for | |
9690 | Imm16 and Imm32. Removing them would probably clean | |
9691 | up the code quite a lot. */ | |
9692 | if (flag_code != CODE_64BIT | |
9693 | && (i.types[this_operand].bitfield.disp16 | |
9694 | || i.types[this_operand].bitfield.disp32)) | |
9695 | i.types[this_operand] | |
9696 | = operand_type_xor (i.types[this_operand], disp16_32); | |
9697 | } | |
9698 | } | |
9699 | } | |
24eab124 | 9700 | #endif |
be05d201 L |
9701 | } |
9702 | ||
2abc2bec JB |
9703 | return addr_mode; |
9704 | } | |
9705 | ||
9706 | /* Make sure the memory operand we've been dealt is valid. | |
9707 | Return 1 on success, 0 on a failure. */ | |
9708 | ||
9709 | static int | |
9710 | i386_index_check (const char *operand_string) | |
9711 | { | |
9712 | const char *kind = "base/index"; | |
9713 | enum flag_code addr_mode = i386_addressing_mode (); | |
9714 | ||
fc0763e6 JB |
9715 | if (current_templates->start->opcode_modifier.isstring |
9716 | && !current_templates->start->opcode_modifier.immext | |
9717 | && (current_templates->end[-1].opcode_modifier.isstring | |
9718 | || i.mem_operands)) | |
9719 | { | |
9720 | /* Memory operands of string insns are special in that they only allow | |
9721 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
9722 | const reg_entry *expected_reg; |
9723 | static const char *di_si[][2] = | |
9724 | { | |
9725 | { "esi", "edi" }, | |
9726 | { "si", "di" }, | |
9727 | { "rsi", "rdi" } | |
9728 | }; | |
9729 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
9730 | |
9731 | kind = "string address"; | |
9732 | ||
8325cc63 | 9733 | if (current_templates->start->opcode_modifier.repprefixok) |
fc0763e6 JB |
9734 | { |
9735 | i386_operand_type type = current_templates->end[-1].operand_types[0]; | |
9736 | ||
9737 | if (!type.bitfield.baseindex | |
9738 | || ((!i.mem_operands != !intel_syntax) | |
9739 | && current_templates->end[-1].operand_types[1] | |
9740 | .bitfield.baseindex)) | |
9741 | type = current_templates->end[-1].operand_types[1]; | |
be05d201 L |
9742 | expected_reg = hash_find (reg_hash, |
9743 | di_si[addr_mode][type.bitfield.esseg]); | |
9744 | ||
fc0763e6 JB |
9745 | } |
9746 | else | |
be05d201 | 9747 | expected_reg = hash_find (reg_hash, bx[addr_mode]); |
fc0763e6 | 9748 | |
be05d201 L |
9749 | if (i.base_reg != expected_reg |
9750 | || i.index_reg | |
fc0763e6 | 9751 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 9752 | { |
be05d201 L |
9753 | /* The second memory operand must have the same size as |
9754 | the first one. */ | |
9755 | if (i.mem_operands | |
9756 | && i.base_reg | |
9757 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 9758 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 9759 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
9760 | ? i.base_reg->reg_type.bitfield.dword |
9761 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
9762 | goto bad_address; |
9763 | ||
fc0763e6 JB |
9764 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
9765 | operand_string, | |
9766 | intel_syntax ? '[' : '(', | |
9767 | register_prefix, | |
be05d201 | 9768 | expected_reg->reg_name, |
fc0763e6 | 9769 | intel_syntax ? ']' : ')'); |
be05d201 | 9770 | return 1; |
fc0763e6 | 9771 | } |
be05d201 L |
9772 | else |
9773 | return 1; | |
9774 | ||
9775 | bad_address: | |
9776 | as_bad (_("`%s' is not a valid %s expression"), | |
9777 | operand_string, kind); | |
9778 | return 0; | |
3e73aa7c JH |
9779 | } |
9780 | else | |
9781 | { | |
be05d201 L |
9782 | if (addr_mode != CODE_16BIT) |
9783 | { | |
9784 | /* 32-bit/64-bit checks. */ | |
9785 | if ((i.base_reg | |
e968fc9b JB |
9786 | && ((addr_mode == CODE_64BIT |
9787 | ? !i.base_reg->reg_type.bitfield.qword | |
9788 | : !i.base_reg->reg_type.bitfield.dword) | |
9789 | || (i.index_reg && i.base_reg->reg_num == RegIP) | |
9790 | || i.base_reg->reg_num == RegIZ)) | |
be05d201 | 9791 | || (i.index_reg |
1b54b8d7 JB |
9792 | && !i.index_reg->reg_type.bitfield.xmmword |
9793 | && !i.index_reg->reg_type.bitfield.ymmword | |
9794 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 9795 | && ((addr_mode == CODE_64BIT |
e968fc9b JB |
9796 | ? !i.index_reg->reg_type.bitfield.qword |
9797 | : !i.index_reg->reg_type.bitfield.dword) | |
be05d201 L |
9798 | || !i.index_reg->reg_type.bitfield.baseindex))) |
9799 | goto bad_address; | |
8178be5b JB |
9800 | |
9801 | /* bndmk, bndldx, and bndstx have special restrictions. */ | |
9802 | if (current_templates->start->base_opcode == 0xf30f1b | |
9803 | || (current_templates->start->base_opcode & ~1) == 0x0f1a) | |
9804 | { | |
9805 | /* They cannot use RIP-relative addressing. */ | |
e968fc9b | 9806 | if (i.base_reg && i.base_reg->reg_num == RegIP) |
8178be5b JB |
9807 | { |
9808 | as_bad (_("`%s' cannot be used here"), operand_string); | |
9809 | return 0; | |
9810 | } | |
9811 | ||
9812 | /* bndldx and bndstx ignore their scale factor. */ | |
9813 | if (current_templates->start->base_opcode != 0xf30f1b | |
9814 | && i.log2_scale_factor) | |
9815 | as_warn (_("register scaling is being ignored here")); | |
9816 | } | |
be05d201 L |
9817 | } |
9818 | else | |
3e73aa7c | 9819 | { |
be05d201 | 9820 | /* 16-bit checks. */ |
3e73aa7c | 9821 | if ((i.base_reg |
dc821c5f | 9822 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 9823 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 9824 | || (i.index_reg |
dc821c5f | 9825 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 9826 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
9827 | || !(i.base_reg |
9828 | && i.base_reg->reg_num < 6 | |
9829 | && i.index_reg->reg_num >= 6 | |
9830 | && i.log2_scale_factor == 0)))) | |
be05d201 | 9831 | goto bad_address; |
3e73aa7c JH |
9832 | } |
9833 | } | |
be05d201 | 9834 | return 1; |
24eab124 | 9835 | } |
252b5132 | 9836 | |
43234a1e L |
9837 | /* Handle vector immediates. */ |
9838 | ||
9839 | static int | |
9840 | RC_SAE_immediate (const char *imm_start) | |
9841 | { | |
9842 | unsigned int match_found, j; | |
9843 | const char *pstr = imm_start; | |
9844 | expressionS *exp; | |
9845 | ||
9846 | if (*pstr != '{') | |
9847 | return 0; | |
9848 | ||
9849 | pstr++; | |
9850 | match_found = 0; | |
9851 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
9852 | { | |
9853 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
9854 | { | |
9855 | if (!i.rounding) | |
9856 | { | |
9857 | rc_op.type = RC_NamesTable[j].type; | |
9858 | rc_op.operand = this_operand; | |
9859 | i.rounding = &rc_op; | |
9860 | } | |
9861 | else | |
9862 | { | |
9863 | as_bad (_("duplicated `%s'"), imm_start); | |
9864 | return 0; | |
9865 | } | |
9866 | pstr += RC_NamesTable[j].len; | |
9867 | match_found = 1; | |
9868 | break; | |
9869 | } | |
9870 | } | |
9871 | if (!match_found) | |
9872 | return 0; | |
9873 | ||
9874 | if (*pstr++ != '}') | |
9875 | { | |
9876 | as_bad (_("Missing '}': '%s'"), imm_start); | |
9877 | return 0; | |
9878 | } | |
9879 | /* RC/SAE immediate string should contain nothing more. */; | |
9880 | if (*pstr != 0) | |
9881 | { | |
9882 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
9883 | return 0; | |
9884 | } | |
9885 | ||
9886 | exp = &im_expressions[i.imm_operands++]; | |
9887 | i.op[this_operand].imms = exp; | |
9888 | ||
9889 | exp->X_op = O_constant; | |
9890 | exp->X_add_number = 0; | |
9891 | exp->X_add_symbol = (symbolS *) 0; | |
9892 | exp->X_op_symbol = (symbolS *) 0; | |
9893 | ||
9894 | i.types[this_operand].bitfield.imm8 = 1; | |
9895 | return 1; | |
9896 | } | |
9897 | ||
8325cc63 JB |
9898 | /* Only string instructions can have a second memory operand, so |
9899 | reduce current_templates to just those if it contains any. */ | |
9900 | static int | |
9901 | maybe_adjust_templates (void) | |
9902 | { | |
9903 | const insn_template *t; | |
9904 | ||
9905 | gas_assert (i.mem_operands == 1); | |
9906 | ||
9907 | for (t = current_templates->start; t < current_templates->end; ++t) | |
9908 | if (t->opcode_modifier.isstring) | |
9909 | break; | |
9910 | ||
9911 | if (t < current_templates->end) | |
9912 | { | |
9913 | static templates aux_templates; | |
9914 | bfd_boolean recheck; | |
9915 | ||
9916 | aux_templates.start = t; | |
9917 | for (; t < current_templates->end; ++t) | |
9918 | if (!t->opcode_modifier.isstring) | |
9919 | break; | |
9920 | aux_templates.end = t; | |
9921 | ||
9922 | /* Determine whether to re-check the first memory operand. */ | |
9923 | recheck = (aux_templates.start != current_templates->start | |
9924 | || t != current_templates->end); | |
9925 | ||
9926 | current_templates = &aux_templates; | |
9927 | ||
9928 | if (recheck) | |
9929 | { | |
9930 | i.mem_operands = 0; | |
9931 | if (i.memop1_string != NULL | |
9932 | && i386_index_check (i.memop1_string) == 0) | |
9933 | return 0; | |
9934 | i.mem_operands = 1; | |
9935 | } | |
9936 | } | |
9937 | ||
9938 | return 1; | |
9939 | } | |
9940 | ||
fc0763e6 | 9941 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 9942 | on error. */ |
252b5132 | 9943 | |
252b5132 | 9944 | static int |
a7619375 | 9945 | i386_att_operand (char *operand_string) |
252b5132 | 9946 | { |
af6bdddf AM |
9947 | const reg_entry *r; |
9948 | char *end_op; | |
24eab124 | 9949 | char *op_string = operand_string; |
252b5132 | 9950 | |
24eab124 | 9951 | if (is_space_char (*op_string)) |
252b5132 RH |
9952 | ++op_string; |
9953 | ||
24eab124 | 9954 | /* We check for an absolute prefix (differentiating, |
47926f60 | 9955 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
9956 | if (*op_string == ABSOLUTE_PREFIX) |
9957 | { | |
9958 | ++op_string; | |
9959 | if (is_space_char (*op_string)) | |
9960 | ++op_string; | |
40fb9820 | 9961 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 | 9962 | } |
252b5132 | 9963 | |
47926f60 | 9964 | /* Check if operand is a register. */ |
4d1bb795 | 9965 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 9966 | { |
40fb9820 L |
9967 | i386_operand_type temp; |
9968 | ||
24eab124 AM |
9969 | /* Check for a segment override by searching for ':' after a |
9970 | segment register. */ | |
9971 | op_string = end_op; | |
9972 | if (is_space_char (*op_string)) | |
9973 | ++op_string; | |
40fb9820 L |
9974 | if (*op_string == ':' |
9975 | && (r->reg_type.bitfield.sreg2 | |
9976 | || r->reg_type.bitfield.sreg3)) | |
24eab124 AM |
9977 | { |
9978 | switch (r->reg_num) | |
9979 | { | |
9980 | case 0: | |
9981 | i.seg[i.mem_operands] = &es; | |
9982 | break; | |
9983 | case 1: | |
9984 | i.seg[i.mem_operands] = &cs; | |
9985 | break; | |
9986 | case 2: | |
9987 | i.seg[i.mem_operands] = &ss; | |
9988 | break; | |
9989 | case 3: | |
9990 | i.seg[i.mem_operands] = &ds; | |
9991 | break; | |
9992 | case 4: | |
9993 | i.seg[i.mem_operands] = &fs; | |
9994 | break; | |
9995 | case 5: | |
9996 | i.seg[i.mem_operands] = &gs; | |
9997 | break; | |
9998 | } | |
252b5132 | 9999 | |
24eab124 | 10000 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
10001 | ++op_string; |
10002 | if (is_space_char (*op_string)) | |
24eab124 | 10003 | ++op_string; |
252b5132 | 10004 | |
24eab124 AM |
10005 | if (!is_digit_char (*op_string) |
10006 | && !is_identifier_char (*op_string) | |
10007 | && *op_string != '(' | |
10008 | && *op_string != ABSOLUTE_PREFIX) | |
10009 | { | |
10010 | as_bad (_("bad memory operand `%s'"), op_string); | |
10011 | return 0; | |
10012 | } | |
47926f60 | 10013 | /* Handle case of %es:*foo. */ |
24eab124 AM |
10014 | if (*op_string == ABSOLUTE_PREFIX) |
10015 | { | |
10016 | ++op_string; | |
10017 | if (is_space_char (*op_string)) | |
10018 | ++op_string; | |
40fb9820 | 10019 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 AM |
10020 | } |
10021 | goto do_memory_reference; | |
10022 | } | |
43234a1e L |
10023 | |
10024 | /* Handle vector operations. */ | |
10025 | if (*op_string == '{') | |
10026 | { | |
10027 | op_string = check_VecOperations (op_string, NULL); | |
10028 | if (op_string == NULL) | |
10029 | return 0; | |
10030 | } | |
10031 | ||
24eab124 AM |
10032 | if (*op_string) |
10033 | { | |
d0b47220 | 10034 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
10035 | return 0; |
10036 | } | |
40fb9820 L |
10037 | temp = r->reg_type; |
10038 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
10039 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
10040 | temp); | |
7d5e4556 | 10041 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 10042 | i.op[this_operand].regs = r; |
24eab124 AM |
10043 | i.reg_operands++; |
10044 | } | |
af6bdddf AM |
10045 | else if (*op_string == REGISTER_PREFIX) |
10046 | { | |
10047 | as_bad (_("bad register name `%s'"), op_string); | |
10048 | return 0; | |
10049 | } | |
24eab124 | 10050 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 10051 | { |
24eab124 | 10052 | ++op_string; |
40fb9820 | 10053 | if (i.types[this_operand].bitfield.jumpabsolute) |
24eab124 | 10054 | { |
d0b47220 | 10055 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
10056 | return 0; |
10057 | } | |
10058 | if (!i386_immediate (op_string)) | |
10059 | return 0; | |
10060 | } | |
43234a1e L |
10061 | else if (RC_SAE_immediate (operand_string)) |
10062 | { | |
10063 | /* If it is a RC or SAE immediate, do nothing. */ | |
10064 | ; | |
10065 | } | |
24eab124 AM |
10066 | else if (is_digit_char (*op_string) |
10067 | || is_identifier_char (*op_string) | |
d02603dc | 10068 | || *op_string == '"' |
e5cb08ac | 10069 | || *op_string == '(') |
24eab124 | 10070 | { |
47926f60 | 10071 | /* This is a memory reference of some sort. */ |
af6bdddf | 10072 | char *base_string; |
252b5132 | 10073 | |
47926f60 | 10074 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
10075 | char *displacement_string_start; |
10076 | char *displacement_string_end; | |
43234a1e | 10077 | char *vop_start; |
252b5132 | 10078 | |
24eab124 | 10079 | do_memory_reference: |
8325cc63 JB |
10080 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
10081 | return 0; | |
24eab124 | 10082 | if ((i.mem_operands == 1 |
40fb9820 | 10083 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
10084 | || i.mem_operands == 2) |
10085 | { | |
10086 | as_bad (_("too many memory references for `%s'"), | |
10087 | current_templates->start->name); | |
10088 | return 0; | |
10089 | } | |
252b5132 | 10090 | |
24eab124 AM |
10091 | /* Check for base index form. We detect the base index form by |
10092 | looking for an ')' at the end of the operand, searching | |
10093 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
10094 | after the '('. */ | |
af6bdddf | 10095 | base_string = op_string + strlen (op_string); |
c3332e24 | 10096 | |
43234a1e L |
10097 | /* Handle vector operations. */ |
10098 | vop_start = strchr (op_string, '{'); | |
10099 | if (vop_start && vop_start < base_string) | |
10100 | { | |
10101 | if (check_VecOperations (vop_start, base_string) == NULL) | |
10102 | return 0; | |
10103 | base_string = vop_start; | |
10104 | } | |
10105 | ||
af6bdddf AM |
10106 | --base_string; |
10107 | if (is_space_char (*base_string)) | |
10108 | --base_string; | |
252b5132 | 10109 | |
47926f60 | 10110 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
10111 | displacement_string_start = op_string; |
10112 | displacement_string_end = base_string + 1; | |
252b5132 | 10113 | |
24eab124 AM |
10114 | if (*base_string == ')') |
10115 | { | |
af6bdddf | 10116 | char *temp_string; |
24eab124 AM |
10117 | unsigned int parens_balanced = 1; |
10118 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 10119 | equal, so this loop will not be infinite. */ |
24eab124 AM |
10120 | do |
10121 | { | |
10122 | base_string--; | |
10123 | if (*base_string == ')') | |
10124 | parens_balanced++; | |
10125 | if (*base_string == '(') | |
10126 | parens_balanced--; | |
10127 | } | |
10128 | while (parens_balanced); | |
c3332e24 | 10129 | |
af6bdddf | 10130 | temp_string = base_string; |
c3332e24 | 10131 | |
24eab124 | 10132 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
10133 | ++base_string; |
10134 | if (is_space_char (*base_string)) | |
24eab124 | 10135 | ++base_string; |
252b5132 | 10136 | |
af6bdddf | 10137 | if (*base_string == ',' |
4eed87de AM |
10138 | || ((i.base_reg = parse_register (base_string, &end_op)) |
10139 | != NULL)) | |
252b5132 | 10140 | { |
af6bdddf | 10141 | displacement_string_end = temp_string; |
252b5132 | 10142 | |
40fb9820 | 10143 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 10144 | |
af6bdddf | 10145 | if (i.base_reg) |
24eab124 | 10146 | { |
24eab124 AM |
10147 | base_string = end_op; |
10148 | if (is_space_char (*base_string)) | |
10149 | ++base_string; | |
af6bdddf AM |
10150 | } |
10151 | ||
10152 | /* There may be an index reg or scale factor here. */ | |
10153 | if (*base_string == ',') | |
10154 | { | |
10155 | ++base_string; | |
10156 | if (is_space_char (*base_string)) | |
10157 | ++base_string; | |
10158 | ||
4eed87de AM |
10159 | if ((i.index_reg = parse_register (base_string, &end_op)) |
10160 | != NULL) | |
24eab124 | 10161 | { |
af6bdddf | 10162 | base_string = end_op; |
24eab124 AM |
10163 | if (is_space_char (*base_string)) |
10164 | ++base_string; | |
af6bdddf AM |
10165 | if (*base_string == ',') |
10166 | { | |
10167 | ++base_string; | |
10168 | if (is_space_char (*base_string)) | |
10169 | ++base_string; | |
10170 | } | |
e5cb08ac | 10171 | else if (*base_string != ')') |
af6bdddf | 10172 | { |
4eed87de AM |
10173 | as_bad (_("expecting `,' or `)' " |
10174 | "after index register in `%s'"), | |
af6bdddf AM |
10175 | operand_string); |
10176 | return 0; | |
10177 | } | |
24eab124 | 10178 | } |
af6bdddf | 10179 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 10180 | { |
f76bf5e0 L |
10181 | end_op = strchr (base_string, ','); |
10182 | if (end_op) | |
10183 | *end_op = '\0'; | |
af6bdddf | 10184 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
10185 | return 0; |
10186 | } | |
252b5132 | 10187 | |
47926f60 | 10188 | /* Check for scale factor. */ |
551c1ca1 | 10189 | if (*base_string != ')') |
af6bdddf | 10190 | { |
551c1ca1 AM |
10191 | char *end_scale = i386_scale (base_string); |
10192 | ||
10193 | if (!end_scale) | |
af6bdddf | 10194 | return 0; |
24eab124 | 10195 | |
551c1ca1 | 10196 | base_string = end_scale; |
af6bdddf AM |
10197 | if (is_space_char (*base_string)) |
10198 | ++base_string; | |
10199 | if (*base_string != ')') | |
10200 | { | |
4eed87de AM |
10201 | as_bad (_("expecting `)' " |
10202 | "after scale factor in `%s'"), | |
af6bdddf AM |
10203 | operand_string); |
10204 | return 0; | |
10205 | } | |
10206 | } | |
10207 | else if (!i.index_reg) | |
24eab124 | 10208 | { |
4eed87de AM |
10209 | as_bad (_("expecting index register or scale factor " |
10210 | "after `,'; got '%c'"), | |
af6bdddf | 10211 | *base_string); |
24eab124 AM |
10212 | return 0; |
10213 | } | |
10214 | } | |
af6bdddf | 10215 | else if (*base_string != ')') |
24eab124 | 10216 | { |
4eed87de AM |
10217 | as_bad (_("expecting `,' or `)' " |
10218 | "after base register in `%s'"), | |
af6bdddf | 10219 | operand_string); |
24eab124 AM |
10220 | return 0; |
10221 | } | |
c3332e24 | 10222 | } |
af6bdddf | 10223 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 10224 | { |
f76bf5e0 L |
10225 | end_op = strchr (base_string, ','); |
10226 | if (end_op) | |
10227 | *end_op = '\0'; | |
af6bdddf | 10228 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 10229 | return 0; |
c3332e24 | 10230 | } |
24eab124 AM |
10231 | } |
10232 | ||
10233 | /* If there's an expression beginning the operand, parse it, | |
10234 | assuming displacement_string_start and | |
10235 | displacement_string_end are meaningful. */ | |
10236 | if (displacement_string_start != displacement_string_end) | |
10237 | { | |
10238 | if (!i386_displacement (displacement_string_start, | |
10239 | displacement_string_end)) | |
10240 | return 0; | |
10241 | } | |
10242 | ||
10243 | /* Special case for (%dx) while doing input/output op. */ | |
10244 | if (i.base_reg | |
2fb5be8d | 10245 | && i.base_reg->reg_type.bitfield.inoutportreg |
24eab124 AM |
10246 | && i.index_reg == 0 |
10247 | && i.log2_scale_factor == 0 | |
10248 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 10249 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 10250 | { |
2fb5be8d | 10251 | i.types[this_operand] = i.base_reg->reg_type; |
24eab124 AM |
10252 | return 1; |
10253 | } | |
10254 | ||
eecb386c AM |
10255 | if (i386_index_check (operand_string) == 0) |
10256 | return 0; | |
c48dadc9 | 10257 | i.flags[this_operand] |= Operand_Mem; |
8325cc63 JB |
10258 | if (i.mem_operands == 0) |
10259 | i.memop1_string = xstrdup (operand_string); | |
24eab124 AM |
10260 | i.mem_operands++; |
10261 | } | |
10262 | else | |
ce8a8b2f AM |
10263 | { |
10264 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
10265 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
10266 | output_invalid (*op_string), | |
10267 | this_operand + 1, | |
10268 | op_string); | |
10269 | return 0; | |
10270 | } | |
47926f60 | 10271 | return 1; /* Normal return. */ |
252b5132 RH |
10272 | } |
10273 | \f | |
fa94de6b RM |
10274 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
10275 | that an rs_machine_dependent frag may reach. */ | |
10276 | ||
10277 | unsigned int | |
10278 | i386_frag_max_var (fragS *frag) | |
10279 | { | |
10280 | /* The only relaxable frags are for jumps. | |
10281 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
10282 | gas_assert (frag->fr_type == rs_machine_dependent); | |
10283 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
10284 | } | |
10285 | ||
b084df0b L |
10286 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10287 | static int | |
8dcea932 | 10288 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
10289 | { |
10290 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
10291 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
10292 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
10293 | return 0; | |
10294 | ||
10295 | if (!S_IS_EXTERNAL (fr_symbol)) | |
10296 | /* Symbol may be weak or local. */ | |
10297 | return !S_IS_WEAK (fr_symbol); | |
10298 | ||
8dcea932 L |
10299 | /* Global symbols with non-default visibility can't be preempted. */ |
10300 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
10301 | return 1; | |
10302 | ||
10303 | if (fr_var != NO_RELOC) | |
10304 | switch ((enum bfd_reloc_code_real) fr_var) | |
10305 | { | |
10306 | case BFD_RELOC_386_PLT32: | |
10307 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 10308 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
10309 | return 0; |
10310 | default: | |
10311 | abort (); | |
10312 | } | |
10313 | ||
b084df0b L |
10314 | /* Global symbols with default visibility in a shared library may be |
10315 | preempted by another definition. */ | |
8dcea932 | 10316 | return !shared; |
b084df0b L |
10317 | } |
10318 | #endif | |
10319 | ||
ee7fcc42 AM |
10320 | /* md_estimate_size_before_relax() |
10321 | ||
10322 | Called just before relax() for rs_machine_dependent frags. The x86 | |
10323 | assembler uses these frags to handle variable size jump | |
10324 | instructions. | |
10325 | ||
10326 | Any symbol that is now undefined will not become defined. | |
10327 | Return the correct fr_subtype in the frag. | |
10328 | Return the initial "guess for variable size of frag" to caller. | |
10329 | The guess is actually the growth beyond the fixed part. Whatever | |
10330 | we do to grow the fixed or variable part contributes to our | |
10331 | returned value. */ | |
10332 | ||
252b5132 | 10333 | int |
7016a5d5 | 10334 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 10335 | { |
252b5132 | 10336 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
10337 | check for un-relaxable symbols. On an ELF system, we can't relax |
10338 | an externally visible symbol, because it may be overridden by a | |
10339 | shared library. */ | |
10340 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 10341 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 10342 | || (IS_ELF |
8dcea932 L |
10343 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
10344 | fragP->fr_var)) | |
fbeb56a4 DK |
10345 | #endif |
10346 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 10347 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 10348 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
10349 | #endif |
10350 | ) | |
252b5132 | 10351 | { |
b98ef147 AM |
10352 | /* Symbol is undefined in this segment, or we need to keep a |
10353 | reloc so that weak symbols can be overridden. */ | |
10354 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 10355 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
10356 | unsigned char *opcode; |
10357 | int old_fr_fix; | |
f6af82bd | 10358 | |
ee7fcc42 | 10359 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 10360 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 10361 | else if (size == 2) |
f6af82bd | 10362 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b L |
10363 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10364 | else if (need_plt32_p (fragP->fr_symbol)) | |
10365 | reloc_type = BFD_RELOC_X86_64_PLT32; | |
10366 | #endif | |
f6af82bd AM |
10367 | else |
10368 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 10369 | |
ee7fcc42 AM |
10370 | old_fr_fix = fragP->fr_fix; |
10371 | opcode = (unsigned char *) fragP->fr_opcode; | |
10372 | ||
fddf5b5b | 10373 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 10374 | { |
fddf5b5b AM |
10375 | case UNCOND_JUMP: |
10376 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 10377 | opcode[0] = 0xe9; |
252b5132 | 10378 | fragP->fr_fix += size; |
062cd5e7 AS |
10379 | fix_new (fragP, old_fr_fix, size, |
10380 | fragP->fr_symbol, | |
10381 | fragP->fr_offset, 1, | |
10382 | reloc_type); | |
252b5132 RH |
10383 | break; |
10384 | ||
fddf5b5b | 10385 | case COND_JUMP86: |
412167cb AM |
10386 | if (size == 2 |
10387 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
10388 | { |
10389 | /* Negate the condition, and branch past an | |
10390 | unconditional jump. */ | |
10391 | opcode[0] ^= 1; | |
10392 | opcode[1] = 3; | |
10393 | /* Insert an unconditional jump. */ | |
10394 | opcode[2] = 0xe9; | |
10395 | /* We added two extra opcode bytes, and have a two byte | |
10396 | offset. */ | |
10397 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
10398 | fix_new (fragP, old_fr_fix + 2, 2, |
10399 | fragP->fr_symbol, | |
10400 | fragP->fr_offset, 1, | |
10401 | reloc_type); | |
fddf5b5b AM |
10402 | break; |
10403 | } | |
10404 | /* Fall through. */ | |
10405 | ||
10406 | case COND_JUMP: | |
412167cb AM |
10407 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
10408 | { | |
3e02c1cc AM |
10409 | fixS *fixP; |
10410 | ||
412167cb | 10411 | fragP->fr_fix += 1; |
3e02c1cc AM |
10412 | fixP = fix_new (fragP, old_fr_fix, 1, |
10413 | fragP->fr_symbol, | |
10414 | fragP->fr_offset, 1, | |
10415 | BFD_RELOC_8_PCREL); | |
10416 | fixP->fx_signed = 1; | |
412167cb AM |
10417 | break; |
10418 | } | |
93c2a809 | 10419 | |
24eab124 | 10420 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 10421 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 10422 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 10423 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
10424 | /* We've added an opcode byte. */ |
10425 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
10426 | fix_new (fragP, old_fr_fix + 1, size, |
10427 | fragP->fr_symbol, | |
10428 | fragP->fr_offset, 1, | |
10429 | reloc_type); | |
252b5132 | 10430 | break; |
fddf5b5b AM |
10431 | |
10432 | default: | |
10433 | BAD_CASE (fragP->fr_subtype); | |
10434 | break; | |
252b5132 RH |
10435 | } |
10436 | frag_wane (fragP); | |
ee7fcc42 | 10437 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 10438 | } |
93c2a809 | 10439 | |
93c2a809 AM |
10440 | /* Guess size depending on current relax state. Initially the relax |
10441 | state will correspond to a short jump and we return 1, because | |
10442 | the variable part of the frag (the branch offset) is one byte | |
10443 | long. However, we can relax a section more than once and in that | |
10444 | case we must either set fr_subtype back to the unrelaxed state, | |
10445 | or return the value for the appropriate branch. */ | |
10446 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
10447 | } |
10448 | ||
47926f60 KH |
10449 | /* Called after relax() is finished. |
10450 | ||
10451 | In: Address of frag. | |
10452 | fr_type == rs_machine_dependent. | |
10453 | fr_subtype is what the address relaxed to. | |
10454 | ||
10455 | Out: Any fixSs and constants are set up. | |
10456 | Caller will turn frag into a ".space 0". */ | |
10457 | ||
252b5132 | 10458 | void |
7016a5d5 TG |
10459 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
10460 | fragS *fragP) | |
252b5132 | 10461 | { |
29b0f896 | 10462 | unsigned char *opcode; |
252b5132 | 10463 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
10464 | offsetT target_address; |
10465 | offsetT opcode_address; | |
252b5132 | 10466 | unsigned int extension = 0; |
847f7ad4 | 10467 | offsetT displacement_from_opcode_start; |
252b5132 RH |
10468 | |
10469 | opcode = (unsigned char *) fragP->fr_opcode; | |
10470 | ||
47926f60 | 10471 | /* Address we want to reach in file space. */ |
252b5132 | 10472 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 10473 | |
47926f60 | 10474 | /* Address opcode resides at in file space. */ |
252b5132 RH |
10475 | opcode_address = fragP->fr_address + fragP->fr_fix; |
10476 | ||
47926f60 | 10477 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
10478 | displacement_from_opcode_start = target_address - opcode_address; |
10479 | ||
fddf5b5b | 10480 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 10481 | { |
47926f60 KH |
10482 | /* Don't have to change opcode. */ |
10483 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 10484 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
10485 | } |
10486 | else | |
10487 | { | |
10488 | if (no_cond_jump_promotion | |
10489 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
10490 | as_warn_where (fragP->fr_file, fragP->fr_line, |
10491 | _("long jump required")); | |
252b5132 | 10492 | |
fddf5b5b AM |
10493 | switch (fragP->fr_subtype) |
10494 | { | |
10495 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
10496 | extension = 4; /* 1 opcode + 4 displacement */ | |
10497 | opcode[0] = 0xe9; | |
10498 | where_to_put_displacement = &opcode[1]; | |
10499 | break; | |
252b5132 | 10500 | |
fddf5b5b AM |
10501 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
10502 | extension = 2; /* 1 opcode + 2 displacement */ | |
10503 | opcode[0] = 0xe9; | |
10504 | where_to_put_displacement = &opcode[1]; | |
10505 | break; | |
252b5132 | 10506 | |
fddf5b5b AM |
10507 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
10508 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
10509 | extension = 5; /* 2 opcode + 4 displacement */ | |
10510 | opcode[1] = opcode[0] + 0x10; | |
10511 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
10512 | where_to_put_displacement = &opcode[2]; | |
10513 | break; | |
252b5132 | 10514 | |
fddf5b5b AM |
10515 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
10516 | extension = 3; /* 2 opcode + 2 displacement */ | |
10517 | opcode[1] = opcode[0] + 0x10; | |
10518 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
10519 | where_to_put_displacement = &opcode[2]; | |
10520 | break; | |
252b5132 | 10521 | |
fddf5b5b AM |
10522 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
10523 | extension = 4; | |
10524 | opcode[0] ^= 1; | |
10525 | opcode[1] = 3; | |
10526 | opcode[2] = 0xe9; | |
10527 | where_to_put_displacement = &opcode[3]; | |
10528 | break; | |
10529 | ||
10530 | default: | |
10531 | BAD_CASE (fragP->fr_subtype); | |
10532 | break; | |
10533 | } | |
252b5132 | 10534 | } |
fddf5b5b | 10535 | |
7b81dfbb AJ |
10536 | /* If size if less then four we are sure that the operand fits, |
10537 | but if it's 4, then it could be that the displacement is larger | |
10538 | then -/+ 2GB. */ | |
10539 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
10540 | && object_64bit | |
10541 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
10542 | + ((addressT) 1 << 31)) |
10543 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
10544 | { |
10545 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
10546 | _("jump target out of range")); | |
10547 | /* Make us emit 0. */ | |
10548 | displacement_from_opcode_start = extension; | |
10549 | } | |
47926f60 | 10550 | /* Now put displacement after opcode. */ |
252b5132 RH |
10551 | md_number_to_chars ((char *) where_to_put_displacement, |
10552 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 10553 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
10554 | fragP->fr_fix += extension; |
10555 | } | |
10556 | \f | |
7016a5d5 | 10557 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
10558 | by our caller that we have all the info we need to fix it up. |
10559 | ||
7016a5d5 TG |
10560 | Parameter valP is the pointer to the value of the bits. |
10561 | ||
252b5132 RH |
10562 | On the 386, immediates, displacements, and data pointers are all in |
10563 | the same (little-endian) format, so we don't need to care about which | |
10564 | we are handling. */ | |
10565 | ||
94f592af | 10566 | void |
7016a5d5 | 10567 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 10568 | { |
94f592af | 10569 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 10570 | valueT value = *valP; |
252b5132 | 10571 | |
f86103b7 | 10572 | #if !defined (TE_Mach) |
93382f6d AM |
10573 | if (fixP->fx_pcrel) |
10574 | { | |
10575 | switch (fixP->fx_r_type) | |
10576 | { | |
5865bb77 ILT |
10577 | default: |
10578 | break; | |
10579 | ||
d6ab8113 JB |
10580 | case BFD_RELOC_64: |
10581 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
10582 | break; | |
93382f6d | 10583 | case BFD_RELOC_32: |
ae8887b5 | 10584 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
10585 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
10586 | break; | |
10587 | case BFD_RELOC_16: | |
10588 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
10589 | break; | |
10590 | case BFD_RELOC_8: | |
10591 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
10592 | break; | |
10593 | } | |
10594 | } | |
252b5132 | 10595 | |
a161fe53 | 10596 | if (fixP->fx_addsy != NULL |
31312f95 | 10597 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 10598 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 10599 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 10600 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 10601 | && !use_rela_relocations) |
252b5132 | 10602 | { |
31312f95 AM |
10603 | /* This is a hack. There should be a better way to handle this. |
10604 | This covers for the fact that bfd_install_relocation will | |
10605 | subtract the current location (for partial_inplace, PC relative | |
10606 | relocations); see more below. */ | |
252b5132 | 10607 | #ifndef OBJ_AOUT |
718ddfc0 | 10608 | if (IS_ELF |
252b5132 RH |
10609 | #ifdef TE_PE |
10610 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
10611 | #endif | |
10612 | ) | |
10613 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
10614 | #endif | |
10615 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 10616 | if (IS_ELF) |
252b5132 | 10617 | { |
6539b54b | 10618 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 10619 | |
6539b54b | 10620 | if ((sym_seg == seg |
2f66722d | 10621 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 10622 | && sym_seg != absolute_section)) |
af65af87 | 10623 | && !generic_force_reloc (fixP)) |
2f66722d AM |
10624 | { |
10625 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
10626 | bfd_install_relocation subtracts them out again. I think |
10627 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
10628 | it. FIXME. */ |
10629 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
10630 | } | |
252b5132 RH |
10631 | } |
10632 | #endif | |
10633 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
10634 | /* For some reason, the PE format does not store a |
10635 | section address offset for a PC relative symbol. */ | |
10636 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 10637 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
10638 | value += md_pcrel_from (fixP); |
10639 | #endif | |
10640 | } | |
fbeb56a4 | 10641 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
10642 | if (fixP->fx_addsy != NULL |
10643 | && S_IS_WEAK (fixP->fx_addsy) | |
10644 | /* PR 16858: Do not modify weak function references. */ | |
10645 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 10646 | { |
296a8689 NC |
10647 | #if !defined (TE_PEP) |
10648 | /* For x86 PE weak function symbols are neither PC-relative | |
10649 | nor do they set S_IS_FUNCTION. So the only reliable way | |
10650 | to detect them is to check the flags of their containing | |
10651 | section. */ | |
10652 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
10653 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
10654 | ; | |
10655 | else | |
10656 | #endif | |
fbeb56a4 DK |
10657 | value -= S_GET_VALUE (fixP->fx_addsy); |
10658 | } | |
10659 | #endif | |
252b5132 RH |
10660 | |
10661 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 10662 | and we must not disappoint it. */ |
252b5132 | 10663 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 10664 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
10665 | switch (fixP->fx_r_type) |
10666 | { | |
10667 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 10668 | case BFD_RELOC_X86_64_PLT32: |
b9519cfe L |
10669 | /* Make the jump instruction point to the address of the operand. |
10670 | At runtime we merely add the offset to the actual PLT entry. | |
10671 | NB: Subtract the offset size only for jump instructions. */ | |
10672 | if (fixP->fx_pcrel) | |
10673 | value = -4; | |
47926f60 | 10674 | break; |
31312f95 | 10675 | |
13ae64f3 JJ |
10676 | case BFD_RELOC_386_TLS_GD: |
10677 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 10678 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
10679 | case BFD_RELOC_386_TLS_IE: |
10680 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 10681 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
10682 | case BFD_RELOC_X86_64_TLSGD: |
10683 | case BFD_RELOC_X86_64_TLSLD: | |
10684 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 10685 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
10686 | value = 0; /* Fully resolved at runtime. No addend. */ |
10687 | /* Fallthrough */ | |
10688 | case BFD_RELOC_386_TLS_LE: | |
10689 | case BFD_RELOC_386_TLS_LDO_32: | |
10690 | case BFD_RELOC_386_TLS_LE_32: | |
10691 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 10692 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 10693 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 10694 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
10695 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
10696 | break; | |
10697 | ||
67a4f2b7 AO |
10698 | case BFD_RELOC_386_TLS_DESC_CALL: |
10699 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
10700 | value = 0; /* Fully resolved at runtime. No addend. */ | |
10701 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
10702 | fixP->fx_done = 0; | |
10703 | return; | |
10704 | ||
47926f60 KH |
10705 | case BFD_RELOC_VTABLE_INHERIT: |
10706 | case BFD_RELOC_VTABLE_ENTRY: | |
10707 | fixP->fx_done = 0; | |
94f592af | 10708 | return; |
47926f60 KH |
10709 | |
10710 | default: | |
10711 | break; | |
10712 | } | |
10713 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 10714 | *valP = value; |
f86103b7 | 10715 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 10716 | |
3e73aa7c | 10717 | /* Are we finished with this relocation now? */ |
c6682705 | 10718 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 10719 | fixP->fx_done = 1; |
fbeb56a4 DK |
10720 | #if defined (OBJ_COFF) && defined (TE_PE) |
10721 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
10722 | { | |
10723 | fixP->fx_done = 0; | |
10724 | /* Remember value for tc_gen_reloc. */ | |
10725 | fixP->fx_addnumber = value; | |
10726 | /* Clear out the frag for now. */ | |
10727 | value = 0; | |
10728 | } | |
10729 | #endif | |
3e73aa7c JH |
10730 | else if (use_rela_relocations) |
10731 | { | |
10732 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
10733 | /* Remember value for tc_gen_reloc. */ |
10734 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
10735 | value = 0; |
10736 | } | |
f86103b7 | 10737 | |
94f592af | 10738 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 10739 | } |
252b5132 | 10740 | \f |
6d4af3c2 | 10741 | const char * |
499ac353 | 10742 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 10743 | { |
499ac353 NC |
10744 | /* This outputs the LITTLENUMs in REVERSE order; |
10745 | in accord with the bigendian 386. */ | |
10746 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
10747 | } |
10748 | \f | |
2d545b82 | 10749 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 10750 | |
252b5132 | 10751 | static char * |
e3bb37b5 | 10752 | output_invalid (int c) |
252b5132 | 10753 | { |
3882b010 | 10754 | if (ISPRINT (c)) |
f9f21a03 L |
10755 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
10756 | "'%c'", c); | |
252b5132 | 10757 | else |
f9f21a03 | 10758 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 10759 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
10760 | return output_invalid_buf; |
10761 | } | |
10762 | ||
af6bdddf | 10763 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
10764 | |
10765 | static const reg_entry * | |
4d1bb795 | 10766 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 10767 | { |
af6bdddf AM |
10768 | char *s = reg_string; |
10769 | char *p; | |
252b5132 RH |
10770 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
10771 | const reg_entry *r; | |
10772 | ||
10773 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
10774 | if (*s == REGISTER_PREFIX) | |
10775 | ++s; | |
10776 | ||
10777 | if (is_space_char (*s)) | |
10778 | ++s; | |
10779 | ||
10780 | p = reg_name_given; | |
af6bdddf | 10781 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
10782 | { |
10783 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
10784 | return (const reg_entry *) NULL; |
10785 | s++; | |
252b5132 RH |
10786 | } |
10787 | ||
6588847e DN |
10788 | /* For naked regs, make sure that we are not dealing with an identifier. |
10789 | This prevents confusing an identifier like `eax_var' with register | |
10790 | `eax'. */ | |
10791 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
10792 | return (const reg_entry *) NULL; | |
10793 | ||
af6bdddf | 10794 | *end_op = s; |
252b5132 RH |
10795 | |
10796 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
10797 | ||
5f47d35b | 10798 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 10799 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 10800 | { |
0e0eea78 JB |
10801 | if (!cpu_arch_flags.bitfield.cpu8087 |
10802 | && !cpu_arch_flags.bitfield.cpu287 | |
10803 | && !cpu_arch_flags.bitfield.cpu387) | |
10804 | return (const reg_entry *) NULL; | |
10805 | ||
5f47d35b AM |
10806 | if (is_space_char (*s)) |
10807 | ++s; | |
10808 | if (*s == '(') | |
10809 | { | |
af6bdddf | 10810 | ++s; |
5f47d35b AM |
10811 | if (is_space_char (*s)) |
10812 | ++s; | |
10813 | if (*s >= '0' && *s <= '7') | |
10814 | { | |
db557034 | 10815 | int fpr = *s - '0'; |
af6bdddf | 10816 | ++s; |
5f47d35b AM |
10817 | if (is_space_char (*s)) |
10818 | ++s; | |
10819 | if (*s == ')') | |
10820 | { | |
10821 | *end_op = s + 1; | |
1e9cc1c2 | 10822 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
db557034 AM |
10823 | know (r); |
10824 | return r + fpr; | |
5f47d35b | 10825 | } |
5f47d35b | 10826 | } |
47926f60 | 10827 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
10828 | return (const reg_entry *) NULL; |
10829 | } | |
10830 | } | |
10831 | ||
a60de03c JB |
10832 | if (r == NULL || allow_pseudo_reg) |
10833 | return r; | |
10834 | ||
0dfbf9d7 | 10835 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
10836 | return (const reg_entry *) NULL; |
10837 | ||
dc821c5f | 10838 | if ((r->reg_type.bitfield.dword |
192dc9c6 JB |
10839 | || r->reg_type.bitfield.sreg3 |
10840 | || r->reg_type.bitfield.control | |
10841 | || r->reg_type.bitfield.debug | |
10842 | || r->reg_type.bitfield.test) | |
10843 | && !cpu_arch_flags.bitfield.cpui386) | |
10844 | return (const reg_entry *) NULL; | |
10845 | ||
6e041cf4 | 10846 | if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx) |
192dc9c6 JB |
10847 | return (const reg_entry *) NULL; |
10848 | ||
6e041cf4 JB |
10849 | if (!cpu_arch_flags.bitfield.cpuavx512f) |
10850 | { | |
10851 | if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask) | |
10852 | return (const reg_entry *) NULL; | |
40f12533 | 10853 | |
6e041cf4 JB |
10854 | if (!cpu_arch_flags.bitfield.cpuavx) |
10855 | { | |
10856 | if (r->reg_type.bitfield.ymmword) | |
10857 | return (const reg_entry *) NULL; | |
1848e567 | 10858 | |
6e041cf4 JB |
10859 | if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword) |
10860 | return (const reg_entry *) NULL; | |
10861 | } | |
10862 | } | |
43234a1e | 10863 | |
1adf7f56 JB |
10864 | if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx) |
10865 | return (const reg_entry *) NULL; | |
10866 | ||
db51cc60 | 10867 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
e968fc9b | 10868 | if (!allow_index_reg && r->reg_num == RegIZ) |
db51cc60 L |
10869 | return (const reg_entry *) NULL; |
10870 | ||
1d3f8286 JB |
10871 | /* Upper 16 vector registers are only available with VREX in 64bit |
10872 | mode, and require EVEX encoding. */ | |
10873 | if (r->reg_flags & RegVRex) | |
43234a1e | 10874 | { |
e951d5ca | 10875 | if (!cpu_arch_flags.bitfield.cpuavx512f |
43234a1e L |
10876 | || flag_code != CODE_64BIT) |
10877 | return (const reg_entry *) NULL; | |
1d3f8286 JB |
10878 | |
10879 | i.vec_encoding = vex_encoding_evex; | |
43234a1e L |
10880 | } |
10881 | ||
4787f4a5 JB |
10882 | if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) |
10883 | && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control) | |
1ae00879 | 10884 | && flag_code != CODE_64BIT) |
20f0a1fc | 10885 | return (const reg_entry *) NULL; |
1ae00879 | 10886 | |
b7240065 JB |
10887 | if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) |
10888 | return (const reg_entry *) NULL; | |
10889 | ||
252b5132 RH |
10890 | return r; |
10891 | } | |
4d1bb795 JB |
10892 | |
10893 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
10894 | ||
10895 | static const reg_entry * | |
10896 | parse_register (char *reg_string, char **end_op) | |
10897 | { | |
10898 | const reg_entry *r; | |
10899 | ||
10900 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
10901 | r = parse_real_register (reg_string, end_op); | |
10902 | else | |
10903 | r = NULL; | |
10904 | if (!r) | |
10905 | { | |
10906 | char *save = input_line_pointer; | |
10907 | char c; | |
10908 | symbolS *symbolP; | |
10909 | ||
10910 | input_line_pointer = reg_string; | |
d02603dc | 10911 | c = get_symbol_name (®_string); |
4d1bb795 JB |
10912 | symbolP = symbol_find (reg_string); |
10913 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
10914 | { | |
10915 | const expressionS *e = symbol_get_value_expression (symbolP); | |
10916 | ||
0398aac5 | 10917 | know (e->X_op == O_register); |
4eed87de | 10918 | know (e->X_add_number >= 0 |
c3fe08fa | 10919 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 | 10920 | r = i386_regtab + e->X_add_number; |
d3bb6b49 | 10921 | if ((r->reg_flags & RegVRex)) |
86fa6981 | 10922 | i.vec_encoding = vex_encoding_evex; |
4d1bb795 JB |
10923 | *end_op = input_line_pointer; |
10924 | } | |
10925 | *input_line_pointer = c; | |
10926 | input_line_pointer = save; | |
10927 | } | |
10928 | return r; | |
10929 | } | |
10930 | ||
10931 | int | |
10932 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
10933 | { | |
10934 | const reg_entry *r; | |
10935 | char *end = input_line_pointer; | |
10936 | ||
10937 | *end = *nextcharP; | |
10938 | r = parse_register (name, &input_line_pointer); | |
10939 | if (r && end <= input_line_pointer) | |
10940 | { | |
10941 | *nextcharP = *input_line_pointer; | |
10942 | *input_line_pointer = 0; | |
10943 | e->X_op = O_register; | |
10944 | e->X_add_number = r - i386_regtab; | |
10945 | return 1; | |
10946 | } | |
10947 | input_line_pointer = end; | |
10948 | *end = 0; | |
ee86248c | 10949 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
10950 | } |
10951 | ||
10952 | void | |
10953 | md_operand (expressionS *e) | |
10954 | { | |
ee86248c JB |
10955 | char *end; |
10956 | const reg_entry *r; | |
4d1bb795 | 10957 | |
ee86248c JB |
10958 | switch (*input_line_pointer) |
10959 | { | |
10960 | case REGISTER_PREFIX: | |
10961 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
10962 | if (r) |
10963 | { | |
10964 | e->X_op = O_register; | |
10965 | e->X_add_number = r - i386_regtab; | |
10966 | input_line_pointer = end; | |
10967 | } | |
ee86248c JB |
10968 | break; |
10969 | ||
10970 | case '[': | |
9c2799c2 | 10971 | gas_assert (intel_syntax); |
ee86248c JB |
10972 | end = input_line_pointer++; |
10973 | expression (e); | |
10974 | if (*input_line_pointer == ']') | |
10975 | { | |
10976 | ++input_line_pointer; | |
10977 | e->X_op_symbol = make_expr_symbol (e); | |
10978 | e->X_add_symbol = NULL; | |
10979 | e->X_add_number = 0; | |
10980 | e->X_op = O_index; | |
10981 | } | |
10982 | else | |
10983 | { | |
10984 | e->X_op = O_absent; | |
10985 | input_line_pointer = end; | |
10986 | } | |
10987 | break; | |
4d1bb795 JB |
10988 | } |
10989 | } | |
10990 | ||
252b5132 | 10991 | \f |
4cc782b5 | 10992 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b6f8c7c4 | 10993 | const char *md_shortopts = "kVQ:sqnO::"; |
252b5132 | 10994 | #else |
b6f8c7c4 | 10995 | const char *md_shortopts = "qnO::"; |
252b5132 | 10996 | #endif |
6e0b89ee | 10997 | |
3e73aa7c | 10998 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
10999 | #define OPTION_64 (OPTION_MD_BASE + 1) |
11000 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
11001 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
11002 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
11003 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
11004 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
11005 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
11006 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
bd5dea88 | 11007 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
c0f3af97 | 11008 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 11009 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
11010 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
11011 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
11012 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 11013 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
11014 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
11015 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 11016 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 11017 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 11018 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 11019 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
11020 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
11021 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 11022 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
b4a3a7b4 | 11023 | #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25) |
03751133 | 11024 | #define OPTION_MVEXWIG (OPTION_MD_BASE + 26) |
b3b91714 | 11025 | |
99ad8390 NC |
11026 | struct option md_longopts[] = |
11027 | { | |
3e73aa7c | 11028 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 11029 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 11030 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 11031 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
11032 | #endif |
11033 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 11034 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 11035 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
b4a3a7b4 | 11036 | {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE}, |
6e0b89ee | 11037 | #endif |
b3b91714 | 11038 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
11039 | {"march", required_argument, NULL, OPTION_MARCH}, |
11040 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
11041 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
11042 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
11043 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
11044 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
c0f3af97 | 11045 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 11046 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 11047 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 11048 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
03751133 | 11049 | {"mvexwig", required_argument, NULL, OPTION_MVEXWIG}, |
7e8b059b | 11050 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
11051 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
11052 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
11053 | # if defined (TE_PE) || defined (TE_PEP) |
11054 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
11055 | #endif | |
d1982f93 | 11056 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 11057 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 11058 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 11059 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
5db04b09 L |
11060 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
11061 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
11062 | {NULL, no_argument, NULL, 0} |
11063 | }; | |
11064 | size_t md_longopts_size = sizeof (md_longopts); | |
11065 | ||
11066 | int | |
17b9d67d | 11067 | md_parse_option (int c, const char *arg) |
252b5132 | 11068 | { |
91d6fa6a | 11069 | unsigned int j; |
293f5f65 | 11070 | char *arch, *next, *saved; |
9103f4f4 | 11071 | |
252b5132 RH |
11072 | switch (c) |
11073 | { | |
12b55ccc L |
11074 | case 'n': |
11075 | optimize_align_code = 0; | |
11076 | break; | |
11077 | ||
a38cf1db AM |
11078 | case 'q': |
11079 | quiet_warnings = 1; | |
252b5132 RH |
11080 | break; |
11081 | ||
11082 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
11083 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
11084 | should be emitted or not. FIXME: Not implemented. */ | |
11085 | case 'Q': | |
252b5132 RH |
11086 | break; |
11087 | ||
11088 | /* -V: SVR4 argument to print version ID. */ | |
11089 | case 'V': | |
11090 | print_version_id (); | |
11091 | break; | |
11092 | ||
a38cf1db AM |
11093 | /* -k: Ignore for FreeBSD compatibility. */ |
11094 | case 'k': | |
252b5132 | 11095 | break; |
4cc782b5 ILT |
11096 | |
11097 | case 's': | |
11098 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 11099 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 11100 | break; |
8dcea932 L |
11101 | |
11102 | case OPTION_MSHARED: | |
11103 | shared = 1; | |
11104 | break; | |
b4a3a7b4 L |
11105 | |
11106 | case OPTION_X86_USED_NOTE: | |
11107 | if (strcasecmp (arg, "yes") == 0) | |
11108 | x86_used_note = 1; | |
11109 | else if (strcasecmp (arg, "no") == 0) | |
11110 | x86_used_note = 0; | |
11111 | else | |
11112 | as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg); | |
11113 | break; | |
11114 | ||
11115 | ||
99ad8390 | 11116 | #endif |
321098a5 | 11117 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 11118 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
11119 | case OPTION_64: |
11120 | { | |
11121 | const char **list, **l; | |
11122 | ||
3e73aa7c JH |
11123 | list = bfd_target_list (); |
11124 | for (l = list; *l != NULL; l++) | |
8620418b | 11125 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
11126 | || strcmp (*l, "coff-x86-64") == 0 |
11127 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
11128 | || strcmp (*l, "pei-x86-64") == 0 |
11129 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
11130 | { |
11131 | default_arch = "x86_64"; | |
11132 | break; | |
11133 | } | |
3e73aa7c | 11134 | if (*l == NULL) |
2b5d6a91 | 11135 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
11136 | free (list); |
11137 | } | |
11138 | break; | |
11139 | #endif | |
252b5132 | 11140 | |
351f65ca | 11141 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 11142 | case OPTION_X32: |
351f65ca L |
11143 | if (IS_ELF) |
11144 | { | |
11145 | const char **list, **l; | |
11146 | ||
11147 | list = bfd_target_list (); | |
11148 | for (l = list; *l != NULL; l++) | |
11149 | if (CONST_STRNEQ (*l, "elf32-x86-64")) | |
11150 | { | |
11151 | default_arch = "x86_64:32"; | |
11152 | break; | |
11153 | } | |
11154 | if (*l == NULL) | |
2b5d6a91 | 11155 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
11156 | free (list); |
11157 | } | |
11158 | else | |
11159 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
11160 | break; | |
11161 | #endif | |
11162 | ||
6e0b89ee AM |
11163 | case OPTION_32: |
11164 | default_arch = "i386"; | |
11165 | break; | |
11166 | ||
b3b91714 AM |
11167 | case OPTION_DIVIDE: |
11168 | #ifdef SVR4_COMMENT_CHARS | |
11169 | { | |
11170 | char *n, *t; | |
11171 | const char *s; | |
11172 | ||
add39d23 | 11173 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
11174 | t = n; |
11175 | for (s = i386_comment_chars; *s != '\0'; s++) | |
11176 | if (*s != '/') | |
11177 | *t++ = *s; | |
11178 | *t = '\0'; | |
11179 | i386_comment_chars = n; | |
11180 | } | |
11181 | #endif | |
11182 | break; | |
11183 | ||
9103f4f4 | 11184 | case OPTION_MARCH: |
293f5f65 L |
11185 | saved = xstrdup (arg); |
11186 | arch = saved; | |
11187 | /* Allow -march=+nosse. */ | |
11188 | if (*arch == '+') | |
11189 | arch++; | |
6305a203 | 11190 | do |
9103f4f4 | 11191 | { |
6305a203 | 11192 | if (*arch == '.') |
2b5d6a91 | 11193 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
11194 | next = strchr (arch, '+'); |
11195 | if (next) | |
11196 | *next++ = '\0'; | |
91d6fa6a | 11197 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 11198 | { |
91d6fa6a | 11199 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 11200 | { |
6305a203 | 11201 | /* Processor. */ |
1ded5609 JB |
11202 | if (! cpu_arch[j].flags.bitfield.cpui386) |
11203 | continue; | |
11204 | ||
91d6fa6a | 11205 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 11206 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
11207 | cpu_arch_flags = cpu_arch[j].flags; |
11208 | cpu_arch_isa = cpu_arch[j].type; | |
11209 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
11210 | if (!cpu_arch_tune_set) |
11211 | { | |
11212 | cpu_arch_tune = cpu_arch_isa; | |
11213 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
11214 | } | |
11215 | break; | |
11216 | } | |
91d6fa6a NC |
11217 | else if (*cpu_arch [j].name == '.' |
11218 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 | 11219 | { |
33eaf5de | 11220 | /* ISA extension. */ |
6305a203 | 11221 | i386_cpu_flags flags; |
309d3373 | 11222 | |
293f5f65 L |
11223 | flags = cpu_flags_or (cpu_arch_flags, |
11224 | cpu_arch[j].flags); | |
81486035 | 11225 | |
5b64d091 | 11226 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
11227 | { |
11228 | if (cpu_sub_arch_name) | |
11229 | { | |
11230 | char *name = cpu_sub_arch_name; | |
11231 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 11232 | cpu_arch[j].name, |
1bf57e9f | 11233 | (const char *) NULL); |
6305a203 L |
11234 | free (name); |
11235 | } | |
11236 | else | |
91d6fa6a | 11237 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 11238 | cpu_arch_flags = flags; |
a586129e | 11239 | cpu_arch_isa_flags = flags; |
6305a203 | 11240 | } |
0089dace L |
11241 | else |
11242 | cpu_arch_isa_flags | |
11243 | = cpu_flags_or (cpu_arch_isa_flags, | |
11244 | cpu_arch[j].flags); | |
6305a203 | 11245 | break; |
ccc9c027 | 11246 | } |
9103f4f4 | 11247 | } |
6305a203 | 11248 | |
293f5f65 L |
11249 | if (j >= ARRAY_SIZE (cpu_arch)) |
11250 | { | |
33eaf5de | 11251 | /* Disable an ISA extension. */ |
293f5f65 L |
11252 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
11253 | if (strcmp (arch, cpu_noarch [j].name) == 0) | |
11254 | { | |
11255 | i386_cpu_flags flags; | |
11256 | ||
11257 | flags = cpu_flags_and_not (cpu_arch_flags, | |
11258 | cpu_noarch[j].flags); | |
11259 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
11260 | { | |
11261 | if (cpu_sub_arch_name) | |
11262 | { | |
11263 | char *name = cpu_sub_arch_name; | |
11264 | cpu_sub_arch_name = concat (arch, | |
11265 | (const char *) NULL); | |
11266 | free (name); | |
11267 | } | |
11268 | else | |
11269 | cpu_sub_arch_name = xstrdup (arch); | |
11270 | cpu_arch_flags = flags; | |
11271 | cpu_arch_isa_flags = flags; | |
11272 | } | |
11273 | break; | |
11274 | } | |
11275 | ||
11276 | if (j >= ARRAY_SIZE (cpu_noarch)) | |
11277 | j = ARRAY_SIZE (cpu_arch); | |
11278 | } | |
11279 | ||
91d6fa6a | 11280 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 11281 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
11282 | |
11283 | arch = next; | |
9103f4f4 | 11284 | } |
293f5f65 L |
11285 | while (next != NULL); |
11286 | free (saved); | |
9103f4f4 L |
11287 | break; |
11288 | ||
11289 | case OPTION_MTUNE: | |
11290 | if (*arg == '.') | |
2b5d6a91 | 11291 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 11292 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 11293 | { |
91d6fa6a | 11294 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 11295 | { |
ccc9c027 | 11296 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
11297 | cpu_arch_tune = cpu_arch [j].type; |
11298 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
11299 | break; |
11300 | } | |
11301 | } | |
91d6fa6a | 11302 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 11303 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
11304 | break; |
11305 | ||
1efbbeb4 L |
11306 | case OPTION_MMNEMONIC: |
11307 | if (strcasecmp (arg, "att") == 0) | |
11308 | intel_mnemonic = 0; | |
11309 | else if (strcasecmp (arg, "intel") == 0) | |
11310 | intel_mnemonic = 1; | |
11311 | else | |
2b5d6a91 | 11312 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
11313 | break; |
11314 | ||
11315 | case OPTION_MSYNTAX: | |
11316 | if (strcasecmp (arg, "att") == 0) | |
11317 | intel_syntax = 0; | |
11318 | else if (strcasecmp (arg, "intel") == 0) | |
11319 | intel_syntax = 1; | |
11320 | else | |
2b5d6a91 | 11321 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
11322 | break; |
11323 | ||
11324 | case OPTION_MINDEX_REG: | |
11325 | allow_index_reg = 1; | |
11326 | break; | |
11327 | ||
11328 | case OPTION_MNAKED_REG: | |
11329 | allow_naked_reg = 1; | |
11330 | break; | |
11331 | ||
c0f3af97 L |
11332 | case OPTION_MSSE2AVX: |
11333 | sse2avx = 1; | |
11334 | break; | |
11335 | ||
daf50ae7 L |
11336 | case OPTION_MSSE_CHECK: |
11337 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 11338 | sse_check = check_error; |
daf50ae7 | 11339 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 11340 | sse_check = check_warning; |
daf50ae7 | 11341 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 11342 | sse_check = check_none; |
daf50ae7 | 11343 | else |
2b5d6a91 | 11344 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
11345 | break; |
11346 | ||
7bab8ab5 JB |
11347 | case OPTION_MOPERAND_CHECK: |
11348 | if (strcasecmp (arg, "error") == 0) | |
11349 | operand_check = check_error; | |
11350 | else if (strcasecmp (arg, "warning") == 0) | |
11351 | operand_check = check_warning; | |
11352 | else if (strcasecmp (arg, "none") == 0) | |
11353 | operand_check = check_none; | |
11354 | else | |
11355 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
11356 | break; | |
11357 | ||
539f890d L |
11358 | case OPTION_MAVXSCALAR: |
11359 | if (strcasecmp (arg, "128") == 0) | |
11360 | avxscalar = vex128; | |
11361 | else if (strcasecmp (arg, "256") == 0) | |
11362 | avxscalar = vex256; | |
11363 | else | |
2b5d6a91 | 11364 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
11365 | break; |
11366 | ||
03751133 L |
11367 | case OPTION_MVEXWIG: |
11368 | if (strcmp (arg, "0") == 0) | |
11369 | vexwig = evexw0; | |
11370 | else if (strcmp (arg, "1") == 0) | |
11371 | vexwig = evexw1; | |
11372 | else | |
11373 | as_fatal (_("invalid -mvexwig= option: `%s'"), arg); | |
11374 | break; | |
11375 | ||
7e8b059b L |
11376 | case OPTION_MADD_BND_PREFIX: |
11377 | add_bnd_prefix = 1; | |
11378 | break; | |
11379 | ||
43234a1e L |
11380 | case OPTION_MEVEXLIG: |
11381 | if (strcmp (arg, "128") == 0) | |
11382 | evexlig = evexl128; | |
11383 | else if (strcmp (arg, "256") == 0) | |
11384 | evexlig = evexl256; | |
11385 | else if (strcmp (arg, "512") == 0) | |
11386 | evexlig = evexl512; | |
11387 | else | |
11388 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
11389 | break; | |
11390 | ||
d3d3c6db IT |
11391 | case OPTION_MEVEXRCIG: |
11392 | if (strcmp (arg, "rne") == 0) | |
11393 | evexrcig = rne; | |
11394 | else if (strcmp (arg, "rd") == 0) | |
11395 | evexrcig = rd; | |
11396 | else if (strcmp (arg, "ru") == 0) | |
11397 | evexrcig = ru; | |
11398 | else if (strcmp (arg, "rz") == 0) | |
11399 | evexrcig = rz; | |
11400 | else | |
11401 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
11402 | break; | |
11403 | ||
43234a1e L |
11404 | case OPTION_MEVEXWIG: |
11405 | if (strcmp (arg, "0") == 0) | |
11406 | evexwig = evexw0; | |
11407 | else if (strcmp (arg, "1") == 0) | |
11408 | evexwig = evexw1; | |
11409 | else | |
11410 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
11411 | break; | |
11412 | ||
167ad85b TG |
11413 | # if defined (TE_PE) || defined (TE_PEP) |
11414 | case OPTION_MBIG_OBJ: | |
11415 | use_big_obj = 1; | |
11416 | break; | |
11417 | #endif | |
11418 | ||
d1982f93 | 11419 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
11420 | if (strcasecmp (arg, "yes") == 0) |
11421 | omit_lock_prefix = 1; | |
11422 | else if (strcasecmp (arg, "no") == 0) | |
11423 | omit_lock_prefix = 0; | |
11424 | else | |
11425 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
11426 | break; | |
11427 | ||
e4e00185 AS |
11428 | case OPTION_MFENCE_AS_LOCK_ADD: |
11429 | if (strcasecmp (arg, "yes") == 0) | |
11430 | avoid_fence = 1; | |
11431 | else if (strcasecmp (arg, "no") == 0) | |
11432 | avoid_fence = 0; | |
11433 | else | |
11434 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
11435 | break; | |
11436 | ||
0cb4071e L |
11437 | case OPTION_MRELAX_RELOCATIONS: |
11438 | if (strcasecmp (arg, "yes") == 0) | |
11439 | generate_relax_relocations = 1; | |
11440 | else if (strcasecmp (arg, "no") == 0) | |
11441 | generate_relax_relocations = 0; | |
11442 | else | |
11443 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
11444 | break; | |
11445 | ||
5db04b09 | 11446 | case OPTION_MAMD64: |
e89c5eaa | 11447 | intel64 = 0; |
5db04b09 L |
11448 | break; |
11449 | ||
11450 | case OPTION_MINTEL64: | |
e89c5eaa | 11451 | intel64 = 1; |
5db04b09 L |
11452 | break; |
11453 | ||
b6f8c7c4 L |
11454 | case 'O': |
11455 | if (arg == NULL) | |
11456 | { | |
11457 | optimize = 1; | |
11458 | /* Turn off -Os. */ | |
11459 | optimize_for_space = 0; | |
11460 | } | |
11461 | else if (*arg == 's') | |
11462 | { | |
11463 | optimize_for_space = 1; | |
11464 | /* Turn on all encoding optimizations. */ | |
41fd2579 | 11465 | optimize = INT_MAX; |
b6f8c7c4 L |
11466 | } |
11467 | else | |
11468 | { | |
11469 | optimize = atoi (arg); | |
11470 | /* Turn off -Os. */ | |
11471 | optimize_for_space = 0; | |
11472 | } | |
11473 | break; | |
11474 | ||
252b5132 RH |
11475 | default: |
11476 | return 0; | |
11477 | } | |
11478 | return 1; | |
11479 | } | |
11480 | ||
8a2c8fef L |
11481 | #define MESSAGE_TEMPLATE \ |
11482 | " " | |
11483 | ||
293f5f65 L |
11484 | static char * |
11485 | output_message (FILE *stream, char *p, char *message, char *start, | |
11486 | int *left_p, const char *name, int len) | |
11487 | { | |
11488 | int size = sizeof (MESSAGE_TEMPLATE); | |
11489 | int left = *left_p; | |
11490 | ||
11491 | /* Reserve 2 spaces for ", " or ",\0" */ | |
11492 | left -= len + 2; | |
11493 | ||
11494 | /* Check if there is any room. */ | |
11495 | if (left >= 0) | |
11496 | { | |
11497 | if (p != start) | |
11498 | { | |
11499 | *p++ = ','; | |
11500 | *p++ = ' '; | |
11501 | } | |
11502 | p = mempcpy (p, name, len); | |
11503 | } | |
11504 | else | |
11505 | { | |
11506 | /* Output the current message now and start a new one. */ | |
11507 | *p++ = ','; | |
11508 | *p = '\0'; | |
11509 | fprintf (stream, "%s\n", message); | |
11510 | p = start; | |
11511 | left = size - (start - message) - len - 2; | |
11512 | ||
11513 | gas_assert (left >= 0); | |
11514 | ||
11515 | p = mempcpy (p, name, len); | |
11516 | } | |
11517 | ||
11518 | *left_p = left; | |
11519 | return p; | |
11520 | } | |
11521 | ||
8a2c8fef | 11522 | static void |
1ded5609 | 11523 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
11524 | { |
11525 | static char message[] = MESSAGE_TEMPLATE; | |
11526 | char *start = message + 27; | |
11527 | char *p; | |
11528 | int size = sizeof (MESSAGE_TEMPLATE); | |
11529 | int left; | |
11530 | const char *name; | |
11531 | int len; | |
11532 | unsigned int j; | |
11533 | ||
11534 | p = start; | |
11535 | left = size - (start - message); | |
11536 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
11537 | { | |
11538 | /* Should it be skipped? */ | |
11539 | if (cpu_arch [j].skip) | |
11540 | continue; | |
11541 | ||
11542 | name = cpu_arch [j].name; | |
11543 | len = cpu_arch [j].len; | |
11544 | if (*name == '.') | |
11545 | { | |
11546 | /* It is an extension. Skip if we aren't asked to show it. */ | |
11547 | if (ext) | |
11548 | { | |
11549 | name++; | |
11550 | len--; | |
11551 | } | |
11552 | else | |
11553 | continue; | |
11554 | } | |
11555 | else if (ext) | |
11556 | { | |
11557 | /* It is an processor. Skip if we show only extension. */ | |
11558 | continue; | |
11559 | } | |
1ded5609 JB |
11560 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
11561 | { | |
11562 | /* It is an impossible processor - skip. */ | |
11563 | continue; | |
11564 | } | |
8a2c8fef | 11565 | |
293f5f65 | 11566 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
11567 | } |
11568 | ||
293f5f65 L |
11569 | /* Display disabled extensions. */ |
11570 | if (ext) | |
11571 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
11572 | { | |
11573 | name = cpu_noarch [j].name; | |
11574 | len = cpu_noarch [j].len; | |
11575 | p = output_message (stream, p, message, start, &left, name, | |
11576 | len); | |
11577 | } | |
11578 | ||
8a2c8fef L |
11579 | *p = '\0'; |
11580 | fprintf (stream, "%s\n", message); | |
11581 | } | |
11582 | ||
252b5132 | 11583 | void |
8a2c8fef | 11584 | md_show_usage (FILE *stream) |
252b5132 | 11585 | { |
4cc782b5 ILT |
11586 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11587 | fprintf (stream, _("\ | |
a38cf1db AM |
11588 | -Q ignored\n\ |
11589 | -V print assembler version number\n\ | |
b3b91714 AM |
11590 | -k ignored\n")); |
11591 | #endif | |
11592 | fprintf (stream, _("\ | |
12b55ccc | 11593 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
11594 | -q quieten some warnings\n")); |
11595 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11596 | fprintf (stream, _("\ | |
a38cf1db | 11597 | -s ignored\n")); |
b3b91714 | 11598 | #endif |
d7f449c0 L |
11599 | #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
11600 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 11601 | fprintf (stream, _("\ |
570561f7 | 11602 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 11603 | #endif |
b3b91714 AM |
11604 | #ifdef SVR4_COMMENT_CHARS |
11605 | fprintf (stream, _("\ | |
11606 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
11607 | #else |
11608 | fprintf (stream, _("\ | |
b3b91714 | 11609 | --divide ignored\n")); |
4cc782b5 | 11610 | #endif |
9103f4f4 | 11611 | fprintf (stream, _("\ |
6305a203 | 11612 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 11613 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 11614 | show_arch (stream, 0, 1); |
8a2c8fef L |
11615 | fprintf (stream, _("\ |
11616 | EXTENSION is combination of:\n")); | |
1ded5609 | 11617 | show_arch (stream, 1, 0); |
6305a203 | 11618 | fprintf (stream, _("\ |
8a2c8fef | 11619 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 11620 | show_arch (stream, 0, 0); |
ba104c83 | 11621 | fprintf (stream, _("\ |
c0f3af97 L |
11622 | -msse2avx encode SSE instructions with VEX prefix\n")); |
11623 | fprintf (stream, _("\ | |
7c5c05ef | 11624 | -msse-check=[none|error|warning] (default: warning)\n\ |
daf50ae7 L |
11625 | check SSE instructions\n")); |
11626 | fprintf (stream, _("\ | |
7c5c05ef | 11627 | -moperand-check=[none|error|warning] (default: warning)\n\ |
7bab8ab5 JB |
11628 | check operand combinations for validity\n")); |
11629 | fprintf (stream, _("\ | |
7c5c05ef L |
11630 | -mavxscalar=[128|256] (default: 128)\n\ |
11631 | encode scalar AVX instructions with specific vector\n\ | |
539f890d L |
11632 | length\n")); |
11633 | fprintf (stream, _("\ | |
03751133 L |
11634 | -mvexwig=[0|1] (default: 0)\n\ |
11635 | encode VEX instructions with specific VEX.W value\n\ | |
11636 | for VEX.W bit ignored instructions\n")); | |
11637 | fprintf (stream, _("\ | |
7c5c05ef L |
11638 | -mevexlig=[128|256|512] (default: 128)\n\ |
11639 | encode scalar EVEX instructions with specific vector\n\ | |
43234a1e L |
11640 | length\n")); |
11641 | fprintf (stream, _("\ | |
7c5c05ef L |
11642 | -mevexwig=[0|1] (default: 0)\n\ |
11643 | encode EVEX instructions with specific EVEX.W value\n\ | |
43234a1e L |
11644 | for EVEX.W bit ignored instructions\n")); |
11645 | fprintf (stream, _("\ | |
7c5c05ef | 11646 | -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\ |
d3d3c6db IT |
11647 | encode EVEX instructions with specific EVEX.RC value\n\ |
11648 | for SAE-only ignored instructions\n")); | |
11649 | fprintf (stream, _("\ | |
7c5c05ef L |
11650 | -mmnemonic=[att|intel] ")); |
11651 | if (SYSV386_COMPAT) | |
11652 | fprintf (stream, _("(default: att)\n")); | |
11653 | else | |
11654 | fprintf (stream, _("(default: intel)\n")); | |
11655 | fprintf (stream, _("\ | |
11656 | use AT&T/Intel mnemonic\n")); | |
ba104c83 | 11657 | fprintf (stream, _("\ |
7c5c05ef L |
11658 | -msyntax=[att|intel] (default: att)\n\ |
11659 | use AT&T/Intel syntax\n")); | |
ba104c83 L |
11660 | fprintf (stream, _("\ |
11661 | -mindex-reg support pseudo index registers\n")); | |
11662 | fprintf (stream, _("\ | |
11663 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
11664 | fprintf (stream, _("\ | |
7e8b059b | 11665 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
b4a3a7b4 | 11666 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8dcea932 L |
11667 | fprintf (stream, _("\ |
11668 | -mshared disable branch optimization for shared code\n")); | |
b4a3a7b4 L |
11669 | fprintf (stream, _("\ |
11670 | -mx86-used-note=[no|yes] ")); | |
11671 | if (DEFAULT_X86_USED_NOTE) | |
11672 | fprintf (stream, _("(default: yes)\n")); | |
11673 | else | |
11674 | fprintf (stream, _("(default: no)\n")); | |
11675 | fprintf (stream, _("\ | |
11676 | generate x86 used ISA and feature properties\n")); | |
11677 | #endif | |
11678 | #if defined (TE_PE) || defined (TE_PEP) | |
167ad85b TG |
11679 | fprintf (stream, _("\ |
11680 | -mbig-obj generate big object files\n")); | |
11681 | #endif | |
d022bddd | 11682 | fprintf (stream, _("\ |
7c5c05ef | 11683 | -momit-lock-prefix=[no|yes] (default: no)\n\ |
d022bddd | 11684 | strip all lock prefixes\n")); |
5db04b09 | 11685 | fprintf (stream, _("\ |
7c5c05ef | 11686 | -mfence-as-lock-add=[no|yes] (default: no)\n\ |
e4e00185 AS |
11687 | encode lfence, mfence and sfence as\n\ |
11688 | lock addl $0x0, (%%{re}sp)\n")); | |
11689 | fprintf (stream, _("\ | |
7c5c05ef L |
11690 | -mrelax-relocations=[no|yes] ")); |
11691 | if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS) | |
11692 | fprintf (stream, _("(default: yes)\n")); | |
11693 | else | |
11694 | fprintf (stream, _("(default: no)\n")); | |
11695 | fprintf (stream, _("\ | |
0cb4071e L |
11696 | generate relax relocations\n")); |
11697 | fprintf (stream, _("\ | |
7c5c05ef | 11698 | -mamd64 accept only AMD64 ISA [default]\n")); |
5db04b09 L |
11699 | fprintf (stream, _("\ |
11700 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
11701 | } |
11702 | ||
3e73aa7c | 11703 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 11704 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 11705 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
11706 | |
11707 | /* Pick the target format to use. */ | |
11708 | ||
47926f60 | 11709 | const char * |
e3bb37b5 | 11710 | i386_target_format (void) |
252b5132 | 11711 | { |
351f65ca L |
11712 | if (!strncmp (default_arch, "x86_64", 6)) |
11713 | { | |
11714 | update_code_flag (CODE_64BIT, 1); | |
11715 | if (default_arch[6] == '\0') | |
7f56bc95 | 11716 | x86_elf_abi = X86_64_ABI; |
351f65ca | 11717 | else |
7f56bc95 | 11718 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 11719 | } |
3e73aa7c | 11720 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 11721 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
11722 | else if (!strcmp (default_arch, "iamcu")) |
11723 | { | |
11724 | update_code_flag (CODE_32BIT, 1); | |
11725 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
11726 | { | |
11727 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
11728 | cpu_arch_name = "iamcu"; | |
11729 | cpu_sub_arch_name = NULL; | |
11730 | cpu_arch_flags = iamcu_flags; | |
11731 | cpu_arch_isa = PROCESSOR_IAMCU; | |
11732 | cpu_arch_isa_flags = iamcu_flags; | |
11733 | if (!cpu_arch_tune_set) | |
11734 | { | |
11735 | cpu_arch_tune = cpu_arch_isa; | |
11736 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
11737 | } | |
11738 | } | |
8d471ec1 | 11739 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
11740 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
11741 | cpu_arch_name); | |
11742 | } | |
3e73aa7c | 11743 | else |
2b5d6a91 | 11744 | as_fatal (_("unknown architecture")); |
89507696 JB |
11745 | |
11746 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
11747 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
11748 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
11749 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
11750 | ||
252b5132 RH |
11751 | switch (OUTPUT_FLAVOR) |
11752 | { | |
9384f2ff | 11753 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 11754 | case bfd_target_aout_flavour: |
47926f60 | 11755 | return AOUT_TARGET_FORMAT; |
4c63da97 | 11756 | #endif |
9384f2ff AM |
11757 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
11758 | # if defined (TE_PE) || defined (TE_PEP) | |
11759 | case bfd_target_coff_flavour: | |
167ad85b TG |
11760 | if (flag_code == CODE_64BIT) |
11761 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
11762 | else | |
11763 | return "pe-i386"; | |
9384f2ff | 11764 | # elif defined (TE_GO32) |
0561d57c JK |
11765 | case bfd_target_coff_flavour: |
11766 | return "coff-go32"; | |
9384f2ff | 11767 | # else |
252b5132 RH |
11768 | case bfd_target_coff_flavour: |
11769 | return "coff-i386"; | |
9384f2ff | 11770 | # endif |
4c63da97 | 11771 | #endif |
3e73aa7c | 11772 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 11773 | case bfd_target_elf_flavour: |
3e73aa7c | 11774 | { |
351f65ca L |
11775 | const char *format; |
11776 | ||
11777 | switch (x86_elf_abi) | |
4fa24527 | 11778 | { |
351f65ca L |
11779 | default: |
11780 | format = ELF_TARGET_FORMAT; | |
11781 | break; | |
7f56bc95 | 11782 | case X86_64_ABI: |
351f65ca | 11783 | use_rela_relocations = 1; |
4fa24527 | 11784 | object_64bit = 1; |
351f65ca L |
11785 | format = ELF_TARGET_FORMAT64; |
11786 | break; | |
7f56bc95 | 11787 | case X86_64_X32_ABI: |
4fa24527 | 11788 | use_rela_relocations = 1; |
351f65ca | 11789 | object_64bit = 1; |
862be3fb | 11790 | disallow_64bit_reloc = 1; |
351f65ca L |
11791 | format = ELF_TARGET_FORMAT32; |
11792 | break; | |
4fa24527 | 11793 | } |
3632d14b | 11794 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 11795 | { |
7f56bc95 | 11796 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
11797 | as_fatal (_("Intel L1OM is 64bit only")); |
11798 | return ELF_TARGET_L1OM_FORMAT; | |
11799 | } | |
b49f93f6 | 11800 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
7a9068fe L |
11801 | { |
11802 | if (x86_elf_abi != X86_64_ABI) | |
11803 | as_fatal (_("Intel K1OM is 64bit only")); | |
11804 | return ELF_TARGET_K1OM_FORMAT; | |
11805 | } | |
81486035 L |
11806 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
11807 | { | |
11808 | if (x86_elf_abi != I386_ABI) | |
11809 | as_fatal (_("Intel MCU is 32bit only")); | |
11810 | return ELF_TARGET_IAMCU_FORMAT; | |
11811 | } | |
8a9036a4 | 11812 | else |
351f65ca | 11813 | return format; |
3e73aa7c | 11814 | } |
e57f8c65 TG |
11815 | #endif |
11816 | #if defined (OBJ_MACH_O) | |
11817 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
11818 | if (flag_code == CODE_64BIT) |
11819 | { | |
11820 | use_rela_relocations = 1; | |
11821 | object_64bit = 1; | |
11822 | return "mach-o-x86-64"; | |
11823 | } | |
11824 | else | |
11825 | return "mach-o-i386"; | |
4c63da97 | 11826 | #endif |
252b5132 RH |
11827 | default: |
11828 | abort (); | |
11829 | return NULL; | |
11830 | } | |
11831 | } | |
11832 | ||
47926f60 | 11833 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 11834 | \f |
252b5132 | 11835 | symbolS * |
7016a5d5 | 11836 | md_undefined_symbol (char *name) |
252b5132 | 11837 | { |
18dc2407 ILT |
11838 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
11839 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
11840 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
11841 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
11842 | { |
11843 | if (!GOT_symbol) | |
11844 | { | |
11845 | if (symbol_find (name)) | |
11846 | as_bad (_("GOT already in symbol table")); | |
11847 | GOT_symbol = symbol_new (name, undefined_section, | |
11848 | (valueT) 0, &zero_address_frag); | |
11849 | }; | |
11850 | return GOT_symbol; | |
11851 | } | |
252b5132 RH |
11852 | return 0; |
11853 | } | |
11854 | ||
11855 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 11856 | |
252b5132 | 11857 | valueT |
7016a5d5 | 11858 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 11859 | { |
4c63da97 AM |
11860 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
11861 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
11862 | { | |
11863 | /* For a.out, force the section size to be aligned. If we don't do | |
11864 | this, BFD will align it for us, but it will not write out the | |
11865 | final bytes of the section. This may be a bug in BFD, but it is | |
11866 | easier to fix it here since that is how the other a.out targets | |
11867 | work. */ | |
11868 | int align; | |
11869 | ||
11870 | align = bfd_get_section_alignment (stdoutput, segment); | |
8d3842cd | 11871 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 11872 | } |
252b5132 RH |
11873 | #endif |
11874 | ||
11875 | return size; | |
11876 | } | |
11877 | ||
11878 | /* On the i386, PC-relative offsets are relative to the start of the | |
11879 | next instruction. That is, the address of the offset, plus its | |
11880 | size, since the offset is always the last part of the insn. */ | |
11881 | ||
11882 | long | |
e3bb37b5 | 11883 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
11884 | { |
11885 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
11886 | } | |
11887 | ||
11888 | #ifndef I386COFF | |
11889 | ||
11890 | static void | |
e3bb37b5 | 11891 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 11892 | { |
29b0f896 | 11893 | int temp; |
252b5132 | 11894 | |
8a75718c JB |
11895 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11896 | if (IS_ELF) | |
11897 | obj_elf_section_change_hook (); | |
11898 | #endif | |
252b5132 RH |
11899 | temp = get_absolute_expression (); |
11900 | subseg_set (bss_section, (subsegT) temp); | |
11901 | demand_empty_rest_of_line (); | |
11902 | } | |
11903 | ||
11904 | #endif | |
11905 | ||
252b5132 | 11906 | void |
e3bb37b5 | 11907 | i386_validate_fix (fixS *fixp) |
252b5132 | 11908 | { |
02a86693 | 11909 | if (fixp->fx_subsy) |
252b5132 | 11910 | { |
02a86693 | 11911 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 11912 | { |
02a86693 L |
11913 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
11914 | { | |
11915 | if (!object_64bit) | |
11916 | abort (); | |
11917 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11918 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
11919 | fixp->fx_r_type = (fixp->fx_tcbit |
11920 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
11921 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
11922 | else |
11923 | #endif | |
11924 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
11925 | } | |
d6ab8113 | 11926 | else |
02a86693 L |
11927 | { |
11928 | if (!object_64bit) | |
11929 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
11930 | else | |
11931 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
11932 | } | |
11933 | fixp->fx_subsy = 0; | |
23df1078 | 11934 | } |
252b5132 | 11935 | } |
02a86693 L |
11936 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11937 | else if (!object_64bit) | |
11938 | { | |
11939 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
11940 | && fixp->fx_tcbit2) | |
11941 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
11942 | } | |
11943 | #endif | |
252b5132 RH |
11944 | } |
11945 | ||
252b5132 | 11946 | arelent * |
7016a5d5 | 11947 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
11948 | { |
11949 | arelent *rel; | |
11950 | bfd_reloc_code_real_type code; | |
11951 | ||
11952 | switch (fixp->fx_r_type) | |
11953 | { | |
8ce3d284 | 11954 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
11955 | case BFD_RELOC_SIZE32: |
11956 | case BFD_RELOC_SIZE64: | |
11957 | if (S_IS_DEFINED (fixp->fx_addsy) | |
11958 | && !S_IS_EXTERNAL (fixp->fx_addsy)) | |
11959 | { | |
11960 | /* Resolve size relocation against local symbol to size of | |
11961 | the symbol plus addend. */ | |
11962 | valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; | |
11963 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
11964 | && !fits_in_unsigned_long (value)) | |
11965 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11966 | _("symbol size computation overflow")); | |
11967 | fixp->fx_addsy = NULL; | |
11968 | fixp->fx_subsy = NULL; | |
11969 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
11970 | return NULL; | |
11971 | } | |
8ce3d284 | 11972 | #endif |
1a0670f3 | 11973 | /* Fall through. */ |
8fd4256d | 11974 | |
3e73aa7c JH |
11975 | case BFD_RELOC_X86_64_PLT32: |
11976 | case BFD_RELOC_X86_64_GOT32: | |
11977 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
11978 | case BFD_RELOC_X86_64_GOTPCRELX: |
11979 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
11980 | case BFD_RELOC_386_PLT32: |
11981 | case BFD_RELOC_386_GOT32: | |
02a86693 | 11982 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
11983 | case BFD_RELOC_386_GOTOFF: |
11984 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
11985 | case BFD_RELOC_386_TLS_GD: |
11986 | case BFD_RELOC_386_TLS_LDM: | |
11987 | case BFD_RELOC_386_TLS_LDO_32: | |
11988 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
11989 | case BFD_RELOC_386_TLS_IE: |
11990 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
11991 | case BFD_RELOC_386_TLS_LE_32: |
11992 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
11993 | case BFD_RELOC_386_TLS_GOTDESC: |
11994 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
11995 | case BFD_RELOC_X86_64_TLSGD: |
11996 | case BFD_RELOC_X86_64_TLSLD: | |
11997 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 11998 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
11999 | case BFD_RELOC_X86_64_GOTTPOFF: |
12000 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
12001 | case BFD_RELOC_X86_64_TPOFF64: |
12002 | case BFD_RELOC_X86_64_GOTOFF64: | |
12003 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
12004 | case BFD_RELOC_X86_64_GOT64: |
12005 | case BFD_RELOC_X86_64_GOTPCREL64: | |
12006 | case BFD_RELOC_X86_64_GOTPC64: | |
12007 | case BFD_RELOC_X86_64_GOTPLT64: | |
12008 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
12009 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
12010 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
12011 | case BFD_RELOC_RVA: |
12012 | case BFD_RELOC_VTABLE_ENTRY: | |
12013 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
12014 | #ifdef TE_PE |
12015 | case BFD_RELOC_32_SECREL: | |
12016 | #endif | |
252b5132 RH |
12017 | code = fixp->fx_r_type; |
12018 | break; | |
dbbaec26 L |
12019 | case BFD_RELOC_X86_64_32S: |
12020 | if (!fixp->fx_pcrel) | |
12021 | { | |
12022 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
12023 | code = fixp->fx_r_type; | |
12024 | break; | |
12025 | } | |
1a0670f3 | 12026 | /* Fall through. */ |
252b5132 | 12027 | default: |
93382f6d | 12028 | if (fixp->fx_pcrel) |
252b5132 | 12029 | { |
93382f6d AM |
12030 | switch (fixp->fx_size) |
12031 | { | |
12032 | default: | |
b091f402 AM |
12033 | as_bad_where (fixp->fx_file, fixp->fx_line, |
12034 | _("can not do %d byte pc-relative relocation"), | |
12035 | fixp->fx_size); | |
93382f6d AM |
12036 | code = BFD_RELOC_32_PCREL; |
12037 | break; | |
12038 | case 1: code = BFD_RELOC_8_PCREL; break; | |
12039 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 12040 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
12041 | #ifdef BFD64 |
12042 | case 8: code = BFD_RELOC_64_PCREL; break; | |
12043 | #endif | |
93382f6d AM |
12044 | } |
12045 | } | |
12046 | else | |
12047 | { | |
12048 | switch (fixp->fx_size) | |
12049 | { | |
12050 | default: | |
b091f402 AM |
12051 | as_bad_where (fixp->fx_file, fixp->fx_line, |
12052 | _("can not do %d byte relocation"), | |
12053 | fixp->fx_size); | |
93382f6d AM |
12054 | code = BFD_RELOC_32; |
12055 | break; | |
12056 | case 1: code = BFD_RELOC_8; break; | |
12057 | case 2: code = BFD_RELOC_16; break; | |
12058 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 12059 | #ifdef BFD64 |
3e73aa7c | 12060 | case 8: code = BFD_RELOC_64; break; |
937149dd | 12061 | #endif |
93382f6d | 12062 | } |
252b5132 RH |
12063 | } |
12064 | break; | |
12065 | } | |
252b5132 | 12066 | |
d182319b JB |
12067 | if ((code == BFD_RELOC_32 |
12068 | || code == BFD_RELOC_32_PCREL | |
12069 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
12070 | && GOT_symbol |
12071 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 12072 | { |
4fa24527 | 12073 | if (!object_64bit) |
d6ab8113 JB |
12074 | code = BFD_RELOC_386_GOTPC; |
12075 | else | |
12076 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 12077 | } |
7b81dfbb AJ |
12078 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
12079 | && GOT_symbol | |
12080 | && fixp->fx_addsy == GOT_symbol) | |
12081 | { | |
12082 | code = BFD_RELOC_X86_64_GOTPC64; | |
12083 | } | |
252b5132 | 12084 | |
add39d23 TS |
12085 | rel = XNEW (arelent); |
12086 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 12087 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
12088 | |
12089 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 12090 | |
3e73aa7c JH |
12091 | if (!use_rela_relocations) |
12092 | { | |
12093 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
12094 | vtable entry to be used in the relocation's section offset. */ | |
12095 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12096 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
12097 | #if defined (OBJ_COFF) && defined (TE_PE) |
12098 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
12099 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
12100 | else | |
12101 | #endif | |
c6682705 | 12102 | rel->addend = 0; |
3e73aa7c JH |
12103 | } |
12104 | /* Use the rela in 64bit mode. */ | |
252b5132 | 12105 | else |
3e73aa7c | 12106 | { |
862be3fb L |
12107 | if (disallow_64bit_reloc) |
12108 | switch (code) | |
12109 | { | |
862be3fb L |
12110 | case BFD_RELOC_X86_64_DTPOFF64: |
12111 | case BFD_RELOC_X86_64_TPOFF64: | |
12112 | case BFD_RELOC_64_PCREL: | |
12113 | case BFD_RELOC_X86_64_GOTOFF64: | |
12114 | case BFD_RELOC_X86_64_GOT64: | |
12115 | case BFD_RELOC_X86_64_GOTPCREL64: | |
12116 | case BFD_RELOC_X86_64_GOTPC64: | |
12117 | case BFD_RELOC_X86_64_GOTPLT64: | |
12118 | case BFD_RELOC_X86_64_PLTOFF64: | |
12119 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12120 | _("cannot represent relocation type %s in x32 mode"), | |
12121 | bfd_get_reloc_code_name (code)); | |
12122 | break; | |
12123 | default: | |
12124 | break; | |
12125 | } | |
12126 | ||
062cd5e7 AS |
12127 | if (!fixp->fx_pcrel) |
12128 | rel->addend = fixp->fx_offset; | |
12129 | else | |
12130 | switch (code) | |
12131 | { | |
12132 | case BFD_RELOC_X86_64_PLT32: | |
12133 | case BFD_RELOC_X86_64_GOT32: | |
12134 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
12135 | case BFD_RELOC_X86_64_GOTPCRELX: |
12136 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
12137 | case BFD_RELOC_X86_64_TLSGD: |
12138 | case BFD_RELOC_X86_64_TLSLD: | |
12139 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
12140 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
12141 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
12142 | rel->addend = fixp->fx_offset - fixp->fx_size; |
12143 | break; | |
12144 | default: | |
12145 | rel->addend = (section->vma | |
12146 | - fixp->fx_size | |
12147 | + fixp->fx_addnumber | |
12148 | + md_pcrel_from (fixp)); | |
12149 | break; | |
12150 | } | |
3e73aa7c JH |
12151 | } |
12152 | ||
252b5132 RH |
12153 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
12154 | if (rel->howto == NULL) | |
12155 | { | |
12156 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 12157 | _("cannot represent relocation type %s"), |
252b5132 RH |
12158 | bfd_get_reloc_code_name (code)); |
12159 | /* Set howto to a garbage value so that we can keep going. */ | |
12160 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 12161 | gas_assert (rel->howto != NULL); |
252b5132 RH |
12162 | } |
12163 | ||
12164 | return rel; | |
12165 | } | |
12166 | ||
ee86248c | 12167 | #include "tc-i386-intel.c" |
54cfded0 | 12168 | |
a60de03c JB |
12169 | void |
12170 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 12171 | { |
a60de03c JB |
12172 | int saved_naked_reg; |
12173 | char saved_register_dot; | |
54cfded0 | 12174 | |
a60de03c JB |
12175 | saved_naked_reg = allow_naked_reg; |
12176 | allow_naked_reg = 1; | |
12177 | saved_register_dot = register_chars['.']; | |
12178 | register_chars['.'] = '.'; | |
12179 | allow_pseudo_reg = 1; | |
12180 | expression_and_evaluate (exp); | |
12181 | allow_pseudo_reg = 0; | |
12182 | register_chars['.'] = saved_register_dot; | |
12183 | allow_naked_reg = saved_naked_reg; | |
12184 | ||
e96d56a1 | 12185 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 12186 | { |
a60de03c JB |
12187 | if ((addressT) exp->X_add_number < i386_regtab_size) |
12188 | { | |
12189 | exp->X_op = O_constant; | |
12190 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
12191 | .dw2_regnum[flag_code >> 1]; | |
12192 | } | |
12193 | else | |
12194 | exp->X_op = O_illegal; | |
54cfded0 | 12195 | } |
54cfded0 AM |
12196 | } |
12197 | ||
12198 | void | |
12199 | tc_x86_frame_initial_instructions (void) | |
12200 | { | |
a60de03c JB |
12201 | static unsigned int sp_regno[2]; |
12202 | ||
12203 | if (!sp_regno[flag_code >> 1]) | |
12204 | { | |
12205 | char *saved_input = input_line_pointer; | |
12206 | char sp[][4] = {"esp", "rsp"}; | |
12207 | expressionS exp; | |
a4447b93 | 12208 | |
a60de03c JB |
12209 | input_line_pointer = sp[flag_code >> 1]; |
12210 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 12211 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
12212 | sp_regno[flag_code >> 1] = exp.X_add_number; |
12213 | input_line_pointer = saved_input; | |
12214 | } | |
a4447b93 | 12215 | |
61ff971f L |
12216 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
12217 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 12218 | } |
d2b2c203 | 12219 | |
d7921315 L |
12220 | int |
12221 | x86_dwarf2_addr_size (void) | |
12222 | { | |
12223 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
12224 | if (x86_elf_abi == X86_64_X32_ABI) | |
12225 | return 4; | |
12226 | #endif | |
12227 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
12228 | } | |
12229 | ||
d2b2c203 DJ |
12230 | int |
12231 | i386_elf_section_type (const char *str, size_t len) | |
12232 | { | |
12233 | if (flag_code == CODE_64BIT | |
12234 | && len == sizeof ("unwind") - 1 | |
12235 | && strncmp (str, "unwind", 6) == 0) | |
12236 | return SHT_X86_64_UNWIND; | |
12237 | ||
12238 | return -1; | |
12239 | } | |
bb41ade5 | 12240 | |
ad5fec3b EB |
12241 | #ifdef TE_SOLARIS |
12242 | void | |
12243 | i386_solaris_fix_up_eh_frame (segT sec) | |
12244 | { | |
12245 | if (flag_code == CODE_64BIT) | |
12246 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
12247 | } | |
12248 | #endif | |
12249 | ||
bb41ade5 AM |
12250 | #ifdef TE_PE |
12251 | void | |
12252 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
12253 | { | |
91d6fa6a | 12254 | expressionS exp; |
bb41ade5 | 12255 | |
91d6fa6a NC |
12256 | exp.X_op = O_secrel; |
12257 | exp.X_add_symbol = symbol; | |
12258 | exp.X_add_number = 0; | |
12259 | emit_expr (&exp, size); | |
bb41ade5 AM |
12260 | } |
12261 | #endif | |
3b22753a L |
12262 | |
12263 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
12264 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
12265 | ||
01e1a5bc | 12266 | bfd_vma |
6d4af3c2 | 12267 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
12268 | { |
12269 | if (flag_code == CODE_64BIT) | |
12270 | { | |
12271 | if (letter == 'l') | |
12272 | return SHF_X86_64_LARGE; | |
12273 | ||
8f3bae45 | 12274 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 12275 | } |
3b22753a | 12276 | else |
8f3bae45 | 12277 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
12278 | return -1; |
12279 | } | |
12280 | ||
01e1a5bc | 12281 | bfd_vma |
3b22753a L |
12282 | x86_64_section_word (char *str, size_t len) |
12283 | { | |
8620418b | 12284 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
12285 | return SHF_X86_64_LARGE; |
12286 | ||
12287 | return -1; | |
12288 | } | |
12289 | ||
12290 | static void | |
12291 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
12292 | { | |
12293 | if (flag_code != CODE_64BIT) | |
12294 | { | |
12295 | s_comm_internal (0, elf_common_parse); | |
12296 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
12297 | } | |
12298 | else | |
12299 | { | |
12300 | static segT lbss_section; | |
12301 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
12302 | asection *saved_bss_section = bss_section; | |
12303 | ||
12304 | if (lbss_section == NULL) | |
12305 | { | |
12306 | flagword applicable; | |
12307 | segT seg = now_seg; | |
12308 | subsegT subseg = now_subseg; | |
12309 | ||
12310 | /* The .lbss section is for local .largecomm symbols. */ | |
12311 | lbss_section = subseg_new (".lbss", 0); | |
12312 | applicable = bfd_applicable_section_flags (stdoutput); | |
12313 | bfd_set_section_flags (stdoutput, lbss_section, | |
12314 | applicable & SEC_ALLOC); | |
12315 | seg_info (lbss_section)->bss = 1; | |
12316 | ||
12317 | subseg_set (seg, subseg); | |
12318 | } | |
12319 | ||
12320 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
12321 | bss_section = lbss_section; | |
12322 | ||
12323 | s_comm_internal (0, elf_common_parse); | |
12324 | ||
12325 | elf_com_section_ptr = saved_com_section_ptr; | |
12326 | bss_section = saved_bss_section; | |
12327 | } | |
12328 | } | |
12329 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |