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* app.c (do_scrub_chars <LEX_IS_SYMBOL_COMPONENT>): Check for full
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
aef6203b 3 2000, 2001, 2002, 2003, 2004, 2005
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
29b0f896
AM		 83static char *output_invalid PARAMS ((int c));
84static int i386_operand PARAMS ((char *operand_string));
85static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
86static const reg_entry *parse_register PARAMS ((char *reg_string,
87 char **end_op));
88static char *parse_insn PARAMS ((char *, char *));
89static char *parse_operands PARAMS ((char *, const char *));
90static void swap_operands PARAMS ((void));
91static void optimize_imm PARAMS ((void));
92static void optimize_disp PARAMS ((void));
93static int match_template PARAMS ((void));
94static int check_string PARAMS ((void));
95static int process_suffix PARAMS ((void));
96static int check_byte_reg PARAMS ((void));
97static int check_long_reg PARAMS ((void));
98static int check_qword_reg PARAMS ((void));
99static int check_word_reg PARAMS ((void));
100static int finalize_imm PARAMS ((void));
101static int process_operands PARAMS ((void));
102static const seg_entry *build_modrm_byte PARAMS ((void));
103static void output_insn PARAMS ((void));
104static void output_branch PARAMS ((void));
105static void output_jump PARAMS ((void));
106static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 107static void output_imm PARAMS ((fragS *insn_start_frag,
108 offsetT insn_start_off));
109static void output_disp PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
29b0f896
AM		 111#ifndef I386COFF
112static void s_bss PARAMS ((int));
252b5132 113#endif
17d4e2a2
L		 114#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
115static void handle_large_common (int small ATTRIBUTE_UNUSED);
116#endif
252b5132 117
a847613f 118static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 119
252b5132 120/* 'md_assemble ()' gathers together information and puts it into a
47926f60 121 i386_insn. */
252b5132 122
520dc8e8
AM		 123union i386_op
124 {
125 expressionS *disps;
126 expressionS *imms;
127 const reg_entry *regs;
128 };
129
252b5132
RH		 130struct _i386_insn
131 {
47926f60 132 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 133 template tm;
134
135 /* SUFFIX holds the instruction mnemonic suffix if given.
136 (e.g. 'l' for 'movl') */
137 char suffix;
138
47926f60 139 /* OPERANDS gives the number of given operands. */
252b5132
RH		 140 unsigned int operands;
141
142 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
143 of given register, displacement, memory operands and immediate
47926f60 144 operands. */
252b5132
RH		 145 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
146
147 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 148 use OP[i] for the corresponding operand. */
252b5132
RH		 149 unsigned int types[MAX_OPERANDS];
150
520dc8e8
AM		 151 /* Displacement expression, immediate expression, or register for each
152 operand. */
153 union i386_op op[MAX_OPERANDS];
252b5132 154
3e73aa7c
JH		 155 /* Flags for operands. */
156 unsigned int flags[MAX_OPERANDS];
157#define Operand_PCrel 1
158
252b5132 159 /* Relocation type for operand */
f86103b7 160 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 161
252b5132
RH		 162 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
163 the base index byte below. */
164 const reg_entry *base_reg;
165 const reg_entry *index_reg;
166 unsigned int log2_scale_factor;
167
168 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 169 explicit segment overrides are given. */
ce8a8b2f 170 const seg_entry *seg[2];
252b5132
RH		 171
172 /* PREFIX holds all the given prefix opcodes (usually null).
173 PREFIXES is the number of prefix opcodes. */
174 unsigned int prefixes;
175 unsigned char prefix[MAX_PREFIXES];
176
177 /* RM and SIB are the modrm byte and the sib byte where the
178 addressing modes of this insn are encoded. */
179
180 modrm_byte rm;
3e73aa7c 181 rex_byte rex;
252b5132
RH		 182 sib_byte sib;
183 };
184
185typedef struct _i386_insn i386_insn;
186
187/* List of chars besides those in app.c:symbol_chars that can start an
188 operand. Used to prevent the scrubber eating vital white-space. */
32137342 189const char extra_symbol_chars[] = "*%-(["
252b5132 190#ifdef LEX_AT
32137342
NC		 191 "@"
192#endif
193#ifdef LEX_QM
194 "?"
252b5132 195#endif
32137342 196 ;
252b5132 197
29b0f896
AM		 198#if (defined (TE_I386AIX) \
199 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
200 && !defined (TE_LINUX) \
32137342 201 && !defined (TE_NETWARE) \
29b0f896
AM		 202 && !defined (TE_FreeBSD) \
203 && !defined (TE_NetBSD)))
252b5132 204/* This array holds the chars that always start a comment. If the
ce8a8b2f 205 pre-processor is disabled, these aren't very useful. */
252b5132
RH		 206const char comment_chars[] = "#/";
207#define PREFIX_SEPARATOR '\\'
252b5132
RH		 208
209/* This array holds the chars that only start a comment at the beginning of
210 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 211 .line and .file directives will appear in the pre-processed output.
212 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 213 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 214 #NO_APP at the beginning of its output.
215 Also note that comments started like this one will always work if
252b5132 216 '/' isn't otherwise defined. */
0d9f6d04 217const char line_comment_chars[] = "#";
29b0f896 218
252b5132 219#else
29b0f896
AM		 220/* Putting '/' here makes it impossible to use the divide operator.
221 However, we need it for compatibility with SVR4 systems. */
222const char comment_chars[] = "#";
223#define PREFIX_SEPARATOR '/'
224
0d9f6d04 225const char line_comment_chars[] = "/#";
252b5132
RH		 226#endif
227
63a0b638 228const char line_separator_chars[] = ";";
252b5132 229
ce8a8b2f
AM		 230/* Chars that can be used to separate mant from exp in floating point
231 nums. */
252b5132
RH		 232const char EXP_CHARS[] = "eE";
233
ce8a8b2f
AM		 234/* Chars that mean this number is a floating point constant
235 As in 0f12.456
236 or 0d1.2345e12. */
252b5132
RH		 237const char FLT_CHARS[] = "fFdDxX";
238
ce8a8b2f 239/* Tables for lexical analysis. */
252b5132
RH		 240static char mnemonic_chars[256];
241static char register_chars[256];
242static char operand_chars[256];
243static char identifier_chars[256];
244static char digit_chars[256];
245
ce8a8b2f 246/* Lexical macros. */
252b5132
RH		 247#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
248#define is_operand_char(x) (operand_chars[(unsigned char) x])
249#define is_register_char(x) (register_chars[(unsigned char) x])
250#define is_space_char(x) ((x) == ' ')
251#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
252#define is_digit_char(x) (digit_chars[(unsigned char) x])
253
0234cb7c 254/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 255static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
256
257/* md_assemble() always leaves the strings it's passed unaltered. To
258 effect this we maintain a stack of saved characters that we've smashed
259 with '\0's (indicating end of strings for various sub-fields of the
47926f60 260 assembler instruction). */
252b5132 261static char save_stack[32];
ce8a8b2f 262static char *save_stack_p;
252b5132
RH		 263#define END_STRING_AND_SAVE(s) \
264 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
265#define RESTORE_END_STRING(s) \
266 do { *(s) = *--save_stack_p; } while (0)
267
47926f60 268/* The instruction we're assembling. */
252b5132
RH		 269static i386_insn i;
270
271/* Possible templates for current insn. */
272static const templates *current_templates;
273
47926f60 274/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 275static expressionS disp_expressions[2], im_expressions[2];
276
47926f60
KH		 277/* Current operand we are working on. */
278static int this_operand;
252b5132 279
3e73aa7c
JH		 280/* We support four different modes. FLAG_CODE variable is used to distinguish
281 these. */
282
283enum flag_code {
284 CODE_32BIT,
285 CODE_16BIT,
286 CODE_64BIT };
f3c180ae 287#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 288
289static enum flag_code flag_code;
4fa24527 290static unsigned int object_64bit;
3e73aa7c
JH		 291static int use_rela_relocations = 0;
292
293/* The names used to print error messages. */
b77a7acd 294static const char *flag_code_names[] =
3e73aa7c
JH		 295 {
296 "32",
297 "16",
298 "64"
299 };
252b5132 300
47926f60
KH		 301/* 1 for intel syntax,
302 0 if att syntax. */
303static int intel_syntax = 0;
252b5132 304
47926f60
KH		 305/* 1 if register prefix % not required. */
306static int allow_naked_reg = 0;
252b5132 307
47926f60
KH		 308/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
309 leave, push, and pop instructions so that gcc has the same stack
310 frame as in 32 bit mode. */
311static char stackop_size = '\0';
eecb386c 312
12b55ccc
L		 313/* Non-zero to optimize code alignment. */
314int optimize_align_code = 1;
315
47926f60
KH		 316/* Non-zero to quieten some warnings. */
317static int quiet_warnings = 0;
a38cf1db 318
47926f60
KH		 319/* CPU name. */
320static const char *cpu_arch_name = NULL;
5c6af06e 321static const char *cpu_sub_arch_name = NULL;
a38cf1db 322
47926f60 323/* CPU feature flags. */
29b0f896 324static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 325
fddf5b5b
AM		 326/* If set, conditional jumps are not automatically promoted to handle
327 larger than a byte offset. */
328static unsigned int no_cond_jump_promotion = 0;
329
29b0f896 330/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 331static symbolS *GOT_symbol;
29b0f896 332
a4447b93
RH		 333/* The dwarf2 return column, adjusted for 32 or 64 bit. */
334unsigned int x86_dwarf2_return_column;
335
336/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
337int x86_cie_data_alignment;
338
252b5132 339/* Interface to relax_segment.
fddf5b5b
AM		 340 There are 3 major relax states for 386 jump insns because the
341 different types of jumps add different sizes to frags when we're
342 figuring out what sort of jump to choose to reach a given label. */
252b5132 343
47926f60 344/* Types. */
93c2a809
AM		 345#define UNCOND_JUMP 0
346#define COND_JUMP 1
347#define COND_JUMP86 2
fddf5b5b 348
47926f60 349/* Sizes. */
252b5132
RH		 350#define CODE16 1
351#define SMALL 0
29b0f896 352#define SMALL16 (SMALL | CODE16)
252b5132 353#define BIG 2
29b0f896 354#define BIG16 (BIG | CODE16)
252b5132
RH		 355
356#ifndef INLINE
357#ifdef __GNUC__
358#define INLINE __inline__
359#else
360#define INLINE
361#endif
362#endif
363
fddf5b5b
AM		 364#define ENCODE_RELAX_STATE(type, size) \
365 ((relax_substateT) (((type) << 2) | (size)))
366#define TYPE_FROM_RELAX_STATE(s) \
367 ((s) >> 2)
368#define DISP_SIZE_FROM_RELAX_STATE(s) \
369 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 370
371/* This table is used by relax_frag to promote short jumps to long
372 ones where necessary. SMALL (short) jumps may be promoted to BIG
373 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
374 don't allow a short jump in a 32 bit code segment to be promoted to
375 a 16 bit offset jump because it's slower (requires data size
376 prefix), and doesn't work, unless the destination is in the bottom
377 64k of the code segment (The top 16 bits of eip are zeroed). */
378
379const relax_typeS md_relax_table[] =
380{
24eab124
AM		 381 /* The fields are:
382 1) most positive reach of this state,
383 2) most negative reach of this state,
93c2a809 384 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 385 4) which index into the table to try if we can't fit into this one. */
252b5132 386
fddf5b5b 387 /* UNCOND_JUMP states. */
93c2a809
AM		 388 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
390 /* dword jmp adds 4 bytes to frag:
391 0 extra opcode bytes, 4 displacement bytes. */
252b5132 392 {0, 0, 4, 0},
93c2a809
AM		 393 /* word jmp adds 2 byte2 to frag:
394 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 395 {0, 0, 2, 0},
396
93c2a809
AM		 397 /* COND_JUMP states. */
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
400 /* dword conditionals adds 5 bytes to frag:
401 1 extra opcode byte, 4 displacement bytes. */
402 {0, 0, 5, 0},
fddf5b5b 403 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 404 1 extra opcode byte, 2 displacement bytes. */
405 {0, 0, 3, 0},
406
407 /* COND_JUMP86 states. */
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
410 /* dword conditionals adds 5 bytes to frag:
411 1 extra opcode byte, 4 displacement bytes. */
412 {0, 0, 5, 0},
413 /* word conditionals add 4 bytes to frag:
414 1 displacement byte and a 3 byte long branch insn. */
415 {0, 0, 4, 0}
252b5132
RH		 416};
417
e413e4e9
AM		 418static const arch_entry cpu_arch[] = {
419 {"i8086", Cpu086 },
420 {"i186", Cpu086|Cpu186 },
421 {"i286", Cpu086|Cpu186|Cpu286 },
422 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
423 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
5c6af06e
JB		 424 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
425 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
426 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
427 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
428 {"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
429 {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
430 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
431 {"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
432 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
433 {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
434 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
435 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
30123838 436 {"opteron", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
5c6af06e
JB		 437 {".mmx", CpuMMX },
438 {".sse", CpuMMX|CpuMMX2|CpuSSE },
439 {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
bf50992e 440 {".sse3", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3 },
5c6af06e
JB		 441 {".3dnow", CpuMMX|Cpu3dnow },
442 {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
443 {".padlock", CpuPadLock },
30123838
JB		 444 {".pacifica", CpuSVME },
445 {".svme", CpuSVME },
e413e4e9
AM		 446 {NULL, 0 }
447};
448
29b0f896
AM		 449const pseudo_typeS md_pseudo_table[] =
450{
451#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
452 {"align", s_align_bytes, 0},
453#else
454 {"align", s_align_ptwo, 0},
455#endif
456 {"arch", set_cpu_arch, 0},
457#ifndef I386COFF
458 {"bss", s_bss, 0},
459#endif
460 {"ffloat", float_cons, 'f'},
461 {"dfloat", float_cons, 'd'},
462 {"tfloat", float_cons, 'x'},
463 {"value", cons, 2},
464 {"noopt", s_ignore, 0},
465 {"optim", s_ignore, 0},
466 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
467 {"code16", set_code_flag, CODE_16BIT},
468 {"code32", set_code_flag, CODE_32BIT},
469 {"code64", set_code_flag, CODE_64BIT},
470 {"intel_syntax", set_intel_syntax, 1},
471 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 472#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
473 {"largecomm", handle_large_common, 0},
07a53e5c
RH		 474#else
475 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
476 {"loc", dwarf2_directive_loc, 0},
477 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 478#endif
6482c264
NC		 479#ifdef TE_PE
480 {"secrel32", pe_directive_secrel, 0},
481#endif
29b0f896
AM		 482 {0, 0, 0}
483};
484
485/* For interface with expression (). */
486extern char *input_line_pointer;
487
488/* Hash table for instruction mnemonic lookup. */
489static struct hash_control *op_hash;
490
491/* Hash table for register lookup. */
492static struct hash_control *reg_hash;
493\f
252b5132
RH		 494void
495i386_align_code (fragP, count)
496 fragS *fragP;
497 int count;
498{
ce8a8b2f
AM		 499 /* Various efficient no-op patterns for aligning code labels.
500 Note: Don't try to assemble the instructions in the comments.
501 0L and 0w are not legal. */
252b5132
RH		 502 static const char f32_1[] =
503 {0x90}; /* nop */
504 static const char f32_2[] =
505 {0x89,0xf6}; /* movl %esi,%esi */
506 static const char f32_3[] =
507 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
508 static const char f32_4[] =
509 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
510 static const char f32_5[] =
511 {0x90, /* nop */
512 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
513 static const char f32_6[] =
514 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
515 static const char f32_7[] =
516 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
517 static const char f32_8[] =
518 {0x90, /* nop */
519 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
520 static const char f32_9[] =
521 {0x89,0xf6, /* movl %esi,%esi */
522 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
523 static const char f32_10[] =
524 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
525 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
526 static const char f32_11[] =
527 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
528 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
529 static const char f32_12[] =
530 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
531 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
532 static const char f32_13[] =
533 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
534 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
535 static const char f32_14[] =
536 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
537 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
538 static const char f32_15[] =
539 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
540 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 541 static const char f16_3[] =
542 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 543 static const char f16_4[] =
544 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
545 static const char f16_5[] =
546 {0x90, /* nop */
547 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
548 static const char f16_6[] =
549 {0x89,0xf6, /* mov %si,%si */
550 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
551 static const char f16_7[] =
552 {0x8d,0x74,0x00, /* lea 0(%si),%si */
553 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
554 static const char f16_8[] =
555 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
556 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
557 static const char *const f32_patt[] = {
558 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
559 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
560 };
561 static const char *const f16_patt[] = {
c3332e24 562 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 563 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
564 };
565
33fef721
JH		 566 if (count <= 0 || count > 15)
567 return;
3e73aa7c 568
33fef721
JH		 569 /* The recommended way to pad 64bit code is to use NOPs preceded by
570 maximally four 0x66 prefixes. Balance the size of nops. */
571 if (flag_code == CODE_64BIT)
252b5132 572 {
33fef721
JH		 573 int i;
574 int nnops = (count + 3) / 4;
575 int len = count / nnops;
576 int remains = count - nnops * len;
577 int pos = 0;
578
579 for (i = 0; i < remains; i++)
252b5132 580 {
33fef721
JH		 581 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
582 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
583 pos += len + 1;
584 }
585 for (; i < nnops; i++)
586 {
587 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
588 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
589 pos += len;
252b5132 590 }
252b5132 591 }
33fef721
JH		 592 else
593 if (flag_code == CODE_16BIT)
594 {
595 memcpy (fragP->fr_literal + fragP->fr_fix,
596 f16_patt[count - 1], count);
597 if (count > 8)
598 /* Adjust jump offset. */
599 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
600 }
601 else
602 memcpy (fragP->fr_literal + fragP->fr_fix,
603 f32_patt[count - 1], count);
604 fragP->fr_var = count;
252b5132
RH		 605}
606
252b5132
RH		 607static INLINE unsigned int
608mode_from_disp_size (t)
609 unsigned int t;
610{
3e73aa7c 611 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 612}
613
614static INLINE int
615fits_in_signed_byte (num)
847f7ad4 616 offsetT num;
252b5132
RH		 617{
618 return (num >= -128) && (num <= 127);
47926f60 619}
252b5132
RH		 620
621static INLINE int
622fits_in_unsigned_byte (num)
847f7ad4 623 offsetT num;
252b5132
RH		 624{
625 return (num & 0xff) == num;
47926f60 626}
252b5132
RH		 627
628static INLINE int
629fits_in_unsigned_word (num)
847f7ad4 630 offsetT num;
252b5132
RH		 631{
632 return (num & 0xffff) == num;
47926f60 633}
252b5132
RH		 634
635static INLINE int
636fits_in_signed_word (num)
847f7ad4 637 offsetT num;
252b5132
RH		 638{
639 return (-32768 <= num) && (num <= 32767);
47926f60 640}
3e73aa7c
JH		 641static INLINE int
642fits_in_signed_long (num)
643 offsetT num ATTRIBUTE_UNUSED;
644{
645#ifndef BFD64
646 return 1;
647#else
648 return (!(((offsetT) -1 << 31) & num)
649 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
650#endif
651} /* fits_in_signed_long() */
652static INLINE int
653fits_in_unsigned_long (num)
654 offsetT num ATTRIBUTE_UNUSED;
655{
656#ifndef BFD64
657 return 1;
658#else
659 return (num & (((offsetT) 2 << 31) - 1)) == num;
660#endif
661} /* fits_in_unsigned_long() */
252b5132
RH		 662
663static int
664smallest_imm_type (num)
847f7ad4 665 offsetT num;
252b5132 666{
a847613f 667 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 668 {
669 /* This code is disabled on the 486 because all the Imm1 forms
670 in the opcode table are slower on the i486. They're the
671 versions with the implicitly specified single-position
672 displacement, which has another syntax if you really want to
673 use that form. */
674 if (num == 1)
3e73aa7c 675 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 676 }
252b5132 677 return (fits_in_signed_byte (num)
3e73aa7c 678 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 679 : fits_in_unsigned_byte (num)
3e73aa7c 680 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 681 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 682 ? (Imm16 | Imm32 | Imm32S | Imm64)
683 : fits_in_signed_long (num)
684 ? (Imm32 | Imm32S | Imm64)
685 : fits_in_unsigned_long (num)
686 ? (Imm32 | Imm64)
687 : Imm64);
47926f60 688}
252b5132 689
847f7ad4
AM		 690static offsetT
691offset_in_range (val, size)
692 offsetT val;
693 int size;
694{
508866be 695 addressT mask;
ba2adb93 696
847f7ad4
AM		 697 switch (size)
698 {
508866be
L		 699 case 1: mask = ((addressT) 1 << 8) - 1; break;
700 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 701 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 702#ifdef BFD64
703 case 8: mask = ((addressT) 2 << 63) - 1; break;
704#endif
47926f60 705 default: abort ();
847f7ad4
AM		 706 }
707
ba2adb93 708 /* If BFD64, sign extend val. */
3e73aa7c
JH		 709 if (!use_rela_relocations)
710 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
711 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 712
47926f60 713 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 714 {
715 char buf1[40], buf2[40];
716
717 sprint_value (buf1, val);
718 sprint_value (buf2, val & mask);
719 as_warn (_("%s shortened to %s"), buf1, buf2);
720 }
721 return val & mask;
722}
723
252b5132
RH		 724/* Returns 0 if attempting to add a prefix where one from the same
725 class already exists, 1 if non rep/repne added, 2 if rep/repne
726 added. */
727static int
728add_prefix (prefix)
729 unsigned int prefix;
730{
731 int ret = 1;
732 int q;
733
29b0f896
AM		 734 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
735 && flag_code == CODE_64BIT)
3e73aa7c
JH		 736 q = REX_PREFIX;
737 else
738 switch (prefix)
739 {
740 default:
741 abort ();
742
743 case CS_PREFIX_OPCODE:
744 case DS_PREFIX_OPCODE:
745 case ES_PREFIX_OPCODE:
746 case FS_PREFIX_OPCODE:
747 case GS_PREFIX_OPCODE:
748 case SS_PREFIX_OPCODE:
749 q = SEG_PREFIX;
750 break;
252b5132 751
3e73aa7c
JH		 752 case REPNE_PREFIX_OPCODE:
753 case REPE_PREFIX_OPCODE:
754 ret = 2;
755 /* fall thru */
756 case LOCK_PREFIX_OPCODE:
757 q = LOCKREP_PREFIX;
758 break;
252b5132 759
3e73aa7c
JH		 760 case FWAIT_OPCODE:
761 q = WAIT_PREFIX;
762 break;
252b5132 763
3e73aa7c
JH		 764 case ADDR_PREFIX_OPCODE:
765 q = ADDR_PREFIX;
766 break;
252b5132 767
3e73aa7c
JH		 768 case DATA_PREFIX_OPCODE:
769 q = DATA_PREFIX;
770 break;
771 }
252b5132 772
29b0f896 773 if (i.prefix[q] != 0)
252b5132
RH		 774 {
775 as_bad (_("same type of prefix used twice"));
776 return 0;
777 }
778
779 i.prefixes += 1;
780 i.prefix[q] = prefix;
781 return ret;
782}
783
784static void
3e73aa7c 785set_code_flag (value)
e5cb08ac 786 int value;
eecb386c 787{
3e73aa7c
JH		 788 flag_code = value;
789 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
790 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
791 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
792 {
793 as_bad (_("64bit mode not supported on this CPU."));
794 }
795 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
796 {
797 as_bad (_("32bit mode not supported on this CPU."));
798 }
eecb386c
AM		 799 stackop_size = '\0';
800}
801
802static void
3e73aa7c
JH		 803set_16bit_gcc_code_flag (new_code_flag)
804 int new_code_flag;
252b5132 805{
3e73aa7c
JH		 806 flag_code = new_code_flag;
807 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
808 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 809 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 810}
811
812static void
813set_intel_syntax (syntax_flag)
eecb386c 814 int syntax_flag;
252b5132
RH		 815{
816 /* Find out if register prefixing is specified. */
817 int ask_naked_reg = 0;
818
819 SKIP_WHITESPACE ();
29b0f896 820 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 821 {
822 char *string = input_line_pointer;
823 int e = get_symbol_end ();
824
47926f60 825 if (strcmp (string, "prefix") == 0)
252b5132 826 ask_naked_reg = 1;
47926f60 827 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 828 ask_naked_reg = -1;
829 else
d0b47220 830 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 831 *input_line_pointer = e;
832 }
833 demand_empty_rest_of_line ();
c3332e24 834
252b5132
RH		 835 intel_syntax = syntax_flag;
836
837 if (ask_naked_reg == 0)
f86103b7
AM		 838 allow_naked_reg = (intel_syntax
839 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 840 else
841 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 842
843 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
844 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 845}
846
e413e4e9
AM		 847static void
848set_cpu_arch (dummy)
47926f60 849 int dummy ATTRIBUTE_UNUSED;
e413e4e9 850{
47926f60 851 SKIP_WHITESPACE ();
e413e4e9 852
29b0f896 853 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 854 {
855 char *string = input_line_pointer;
856 int e = get_symbol_end ();
857 int i;
858
859 for (i = 0; cpu_arch[i].name; i++)
860 {
861 if (strcmp (string, cpu_arch[i].name) == 0)
862 {
5c6af06e
JB		 863 if (*string != '.')
864 {
865 cpu_arch_name = cpu_arch[i].name;
866 cpu_sub_arch_name = NULL;
867 cpu_arch_flags = (cpu_arch[i].flags
868 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
869 break;
870 }
871 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
872 {
873 cpu_sub_arch_name = cpu_arch[i].name;
874 cpu_arch_flags |= cpu_arch[i].flags;
875 }
876 *input_line_pointer = e;
877 demand_empty_rest_of_line ();
878 return;
e413e4e9
AM		 879 }
880 }
881 if (!cpu_arch[i].name)
882 as_bad (_("no such architecture: `%s'"), string);
883
884 *input_line_pointer = e;
885 }
886 else
887 as_bad (_("missing cpu architecture"));
888
fddf5b5b
AM		 889 no_cond_jump_promotion = 0;
890 if (*input_line_pointer == ','
29b0f896 891 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 892 {
893 char *string = ++input_line_pointer;
894 int e = get_symbol_end ();
895
896 if (strcmp (string, "nojumps") == 0)
897 no_cond_jump_promotion = 1;
898 else if (strcmp (string, "jumps") == 0)
899 ;
900 else
901 as_bad (_("no such architecture modifier: `%s'"), string);
902
903 *input_line_pointer = e;
904 }
905
e413e4e9
AM		 906 demand_empty_rest_of_line ();
907}
908
b9d79e03
JH		 909unsigned long
910i386_mach ()
911{
912 if (!strcmp (default_arch, "x86_64"))
913 return bfd_mach_x86_64;
914 else if (!strcmp (default_arch, "i386"))
915 return bfd_mach_i386_i386;
916 else
917 as_fatal (_("Unknown architecture"));
918}
b9d79e03 919\f
252b5132
RH		 920void
921md_begin ()
922{
923 const char *hash_err;
924
47926f60 925 /* Initialize op_hash hash table. */
252b5132
RH		 926 op_hash = hash_new ();
927
928 {
29b0f896
AM		 929 const template *optab;
930 templates *core_optab;
252b5132 931
47926f60
KH		 932 /* Setup for loop. */
933 optab = i386_optab;
252b5132
RH		 934 core_optab = (templates *) xmalloc (sizeof (templates));
935 core_optab->start = optab;
936
937 while (1)
938 {
939 ++optab;
940 if (optab->name == NULL
941 || strcmp (optab->name, (optab - 1)->name) != 0)
942 {
943 /* different name --> ship out current template list;
47926f60 944 add to hash table; & begin anew. */
252b5132
RH		 945 core_optab->end = optab;
946 hash_err = hash_insert (op_hash,
947 (optab - 1)->name,
948 (PTR) core_optab);
949 if (hash_err)
950 {
252b5132
RH		 951 as_fatal (_("Internal Error: Can't hash %s: %s"),
952 (optab - 1)->name,
953 hash_err);
954 }
955 if (optab->name == NULL)
956 break;
957 core_optab = (templates *) xmalloc (sizeof (templates));
958 core_optab->start = optab;
959 }
960 }
961 }
962
47926f60 963 /* Initialize reg_hash hash table. */
252b5132
RH		 964 reg_hash = hash_new ();
965 {
29b0f896 966 const reg_entry *regtab;
252b5132
RH		 967
968 for (regtab = i386_regtab;
969 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
970 regtab++)
971 {
972 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
973 if (hash_err)
3e73aa7c
JH		 974 as_fatal (_("Internal Error: Can't hash %s: %s"),
975 regtab->reg_name,
976 hash_err);
252b5132
RH		 977 }
978 }
979
47926f60 980 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 981 {
29b0f896
AM		 982 int c;
983 char *p;
252b5132
RH		 984
985 for (c = 0; c < 256; c++)
986 {
3882b010 987 if (ISDIGIT (c))
252b5132
RH		 988 {
989 digit_chars[c] = c;
990 mnemonic_chars[c] = c;
991 register_chars[c] = c;
992 operand_chars[c] = c;
993 }
3882b010 994 else if (ISLOWER (c))
252b5132
RH		 995 {
996 mnemonic_chars[c] = c;
997 register_chars[c] = c;
998 operand_chars[c] = c;
999 }
3882b010 1000 else if (ISUPPER (c))
252b5132 1001 {
3882b010 1002 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1003 register_chars[c] = mnemonic_chars[c];
1004 operand_chars[c] = c;
1005 }
1006
3882b010 1007 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1008 identifier_chars[c] = c;
1009 else if (c >= 128)
1010 {
1011 identifier_chars[c] = c;
1012 operand_chars[c] = c;
1013 }
1014 }
1015
1016#ifdef LEX_AT
1017 identifier_chars['@'] = '@';
32137342
NC		 1018#endif
1019#ifdef LEX_QM
1020 identifier_chars['?'] = '?';
1021 operand_chars['?'] = '?';
252b5132 1022#endif
252b5132 1023 digit_chars['-'] = '-';
791fe849 1024 mnemonic_chars['-'] = '-';
252b5132
RH		 1025 identifier_chars['_'] = '_';
1026 identifier_chars['.'] = '.';
1027
1028 for (p = operand_special_chars; *p != '\0'; p++)
1029 operand_chars[(unsigned char) *p] = *p;
1030 }
1031
1032#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1033 if (IS_ELF)
252b5132
RH		 1034 {
1035 record_alignment (text_section, 2);
1036 record_alignment (data_section, 2);
1037 record_alignment (bss_section, 2);
1038 }
1039#endif
a4447b93
RH		 1040
1041 if (flag_code == CODE_64BIT)
1042 {
1043 x86_dwarf2_return_column = 16;
1044 x86_cie_data_alignment = -8;
1045 }
1046 else
1047 {
1048 x86_dwarf2_return_column = 8;
1049 x86_cie_data_alignment = -4;
1050 }
252b5132
RH		 1051}
1052
1053void
1054i386_print_statistics (file)
1055 FILE *file;
1056{
1057 hash_print_statistics (file, "i386 opcode", op_hash);
1058 hash_print_statistics (file, "i386 register", reg_hash);
1059}
1060\f
252b5132
RH		 1061#ifdef DEBUG386
1062
ce8a8b2f 1063/* Debugging routines for md_assemble. */
252b5132
RH		 1064static void pi PARAMS ((char *, i386_insn *));
1065static void pte PARAMS ((template *));
1066static void pt PARAMS ((unsigned int));
1067static void pe PARAMS ((expressionS *));
1068static void ps PARAMS ((symbolS *));
1069
1070static void
1071pi (line, x)
1072 char *line;
1073 i386_insn *x;
1074{
09f131f2 1075 unsigned int i;
252b5132
RH		 1076
1077 fprintf (stdout, "%s: template ", line);
1078 pte (&x->tm);
09f131f2
JH		 1079 fprintf (stdout, " address: base %s index %s scale %x\n",
1080 x->base_reg ? x->base_reg->reg_name : "none",
1081 x->index_reg ? x->index_reg->reg_name : "none",
1082 x->log2_scale_factor);
1083 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1084 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1085 fprintf (stdout, " sib: base %x index %x scale %x\n",
1086 x->sib.base, x->sib.index, x->sib.scale);
1087 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1088 (x->rex & REX_MODE64) != 0,
1089 (x->rex & REX_EXTX) != 0,
1090 (x->rex & REX_EXTY) != 0,
1091 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1092 for (i = 0; i < x->operands; i++)
1093 {
1094 fprintf (stdout, " #%d: ", i + 1);
1095 pt (x->types[i]);
1096 fprintf (stdout, "\n");
1097 if (x->types[i]
3f4438ab 1098 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1099 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1100 if (x->types[i] & Imm)
520dc8e8 1101 pe (x->op[i].imms);
252b5132 1102 if (x->types[i] & Disp)
520dc8e8 1103 pe (x->op[i].disps);
252b5132
RH		 1104 }
1105}
1106
1107static void
1108pte (t)
1109 template *t;
1110{
09f131f2 1111 unsigned int i;
252b5132 1112 fprintf (stdout, " %d operands ", t->operands);
47926f60 1113 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1114 if (t->extension_opcode != None)
1115 fprintf (stdout, "ext %x ", t->extension_opcode);
1116 if (t->opcode_modifier & D)
1117 fprintf (stdout, "D");
1118 if (t->opcode_modifier & W)
1119 fprintf (stdout, "W");
1120 fprintf (stdout, "\n");
1121 for (i = 0; i < t->operands; i++)
1122 {
1123 fprintf (stdout, " #%d type ", i + 1);
1124 pt (t->operand_types[i]);
1125 fprintf (stdout, "\n");
1126 }
1127}
1128
1129static void
1130pe (e)
1131 expressionS *e;
1132{
24eab124 1133 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1134 fprintf (stdout, " add_number %ld (%lx)\n",
1135 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1136 if (e->X_add_symbol)
1137 {
1138 fprintf (stdout, " add_symbol ");
1139 ps (e->X_add_symbol);
1140 fprintf (stdout, "\n");
1141 }
1142 if (e->X_op_symbol)
1143 {
1144 fprintf (stdout, " op_symbol ");
1145 ps (e->X_op_symbol);
1146 fprintf (stdout, "\n");
1147 }
1148}
1149
1150static void
1151ps (s)
1152 symbolS *s;
1153{
1154 fprintf (stdout, "%s type %s%s",
1155 S_GET_NAME (s),
1156 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1157 segment_name (S_GET_SEGMENT (s)));
1158}
1159
1160struct type_name
1161 {
1162 unsigned int mask;
1163 char *tname;
1164 }
1165
29b0f896 1166static const type_names[] =
252b5132
RH		 1167{
1168 { Reg8, "r8" },
1169 { Reg16, "r16" },
1170 { Reg32, "r32" },
09f131f2 1171 { Reg64, "r64" },
252b5132
RH		 1172 { Imm8, "i8" },
1173 { Imm8S, "i8s" },
1174 { Imm16, "i16" },
1175 { Imm32, "i32" },
09f131f2
JH		 1176 { Imm32S, "i32s" },
1177 { Imm64, "i64" },
252b5132
RH		 1178 { Imm1, "i1" },
1179 { BaseIndex, "BaseIndex" },
1180 { Disp8, "d8" },
1181 { Disp16, "d16" },
1182 { Disp32, "d32" },
09f131f2
JH		 1183 { Disp32S, "d32s" },
1184 { Disp64, "d64" },
252b5132
RH		 1185 { InOutPortReg, "InOutPortReg" },
1186 { ShiftCount, "ShiftCount" },
1187 { Control, "control reg" },
1188 { Test, "test reg" },
1189 { Debug, "debug reg" },
1190 { FloatReg, "FReg" },
1191 { FloatAcc, "FAcc" },
1192 { SReg2, "SReg2" },
1193 { SReg3, "SReg3" },
1194 { Acc, "Acc" },
1195 { JumpAbsolute, "Jump Absolute" },
1196 { RegMMX, "rMMX" },
3f4438ab 1197 { RegXMM, "rXMM" },
252b5132
RH		 1198 { EsSeg, "es" },
1199 { 0, "" }
1200};
1201
1202static void
1203pt (t)
1204 unsigned int t;
1205{
29b0f896 1206 const struct type_name *ty;
252b5132 1207
09f131f2
JH		 1208 for (ty = type_names; ty->mask; ty++)
1209 if (t & ty->mask)
1210 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1211 fflush (stdout);
1212}
1213
1214#endif /* DEBUG386 */
1215\f
252b5132 1216static bfd_reloc_code_real_type
3956db08
JB		 1217reloc (unsigned int size,
1218 int pcrel,
1219 int sign,
1220 bfd_reloc_code_real_type other)
252b5132 1221{
47926f60 1222 if (other != NO_RELOC)
3956db08
JB		 1223 {
1224 reloc_howto_type *reloc;
1225
1226 if (size == 8)
1227 switch (other)
1228 {
1229 case BFD_RELOC_X86_64_TPOFF32:
1230 other = BFD_RELOC_X86_64_TPOFF64;
1231 break;
1232 case BFD_RELOC_X86_64_DTPOFF32:
1233 other = BFD_RELOC_X86_64_DTPOFF64;
1234 break;
1235 default:
1236 break;
1237 }
1238 reloc = bfd_reloc_type_lookup (stdoutput, other);
1239 if (!reloc)
1240 as_bad (_("unknown relocation (%u)"), other);
1241 else if (size != bfd_get_reloc_size (reloc))
1242 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1243 bfd_get_reloc_size (reloc),
1244 size);
1245 else if (pcrel && !reloc->pc_relative)
1246 as_bad (_("non-pc-relative relocation for pc-relative field"));
1247 else if ((reloc->complain_on_overflow == complain_overflow_signed
1248 && !sign)
1249 || (reloc->complain_on_overflow == complain_overflow_unsigned
1250 && sign > 0))
1251 as_bad (_("relocated field and relocation type differ in signedness"));
1252 else
1253 return other;
1254 return NO_RELOC;
1255 }
252b5132
RH		 1256
1257 if (pcrel)
1258 {
3e73aa7c 1259 if (!sign)
3956db08 1260 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1261 switch (size)
1262 {
1263 case 1: return BFD_RELOC_8_PCREL;
1264 case 2: return BFD_RELOC_16_PCREL;
1265 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1266 case 8: return BFD_RELOC_64_PCREL;
252b5132 1267 }
3956db08 1268 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1269 }
1270 else
1271 {
3956db08 1272 if (sign > 0)
e5cb08ac 1273 switch (size)
3e73aa7c
JH		 1274 {
1275 case 4: return BFD_RELOC_X86_64_32S;
1276 }
1277 else
1278 switch (size)
1279 {
1280 case 1: return BFD_RELOC_8;
1281 case 2: return BFD_RELOC_16;
1282 case 4: return BFD_RELOC_32;
1283 case 8: return BFD_RELOC_64;
1284 }
3956db08
JB		 1285 as_bad (_("cannot do %s %u byte relocation"),
1286 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1287 }
1288
bfb32b52 1289 abort ();
252b5132
RH		 1290 return BFD_RELOC_NONE;
1291}
1292
47926f60
KH		 1293/* Here we decide which fixups can be adjusted to make them relative to
1294 the beginning of the section instead of the symbol. Basically we need
1295 to make sure that the dynamic relocations are done correctly, so in
1296 some cases we force the original symbol to be used. */
1297
252b5132 1298int
c0c949c7 1299tc_i386_fix_adjustable (fixP)
31312f95 1300 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1301{
6d249963 1302#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1303 if (!IS_ELF)
31312f95
AM		 1304 return 1;
1305
a161fe53
AM		 1306 /* Don't adjust pc-relative references to merge sections in 64-bit
1307 mode. */
1308 if (use_rela_relocations
1309 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1310 && fixP->fx_pcrel)
252b5132 1311 return 0;
31312f95 1312
8d01d9a9
AJ		 1313 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1314 and changed later by validate_fix. */
1315 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1316 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1317 return 0;
1318
ce8a8b2f 1319 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1320 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1321 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1322 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1323 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1324 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1325 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1326 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1327 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1328 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1329 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1330 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3e73aa7c
JH		 1331 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1332 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1333 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1334 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1335 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1336 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1337 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1338 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1339 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1340 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1341 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
252b5132
RH		 1342 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1343 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1344 return 0;
31312f95 1345#endif
252b5132
RH		 1346 return 1;
1347}
252b5132 1348
29b0f896 1349static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1350
1351static int
252b5132 1352intel_float_operand (mnemonic)
29b0f896 1353 const char *mnemonic;
252b5132 1354{
9306ca4a
JB		 1355 /* Note that the value returned is meaningful only for opcodes with (memory)
1356 operands, hence the code here is free to improperly handle opcodes that
1357 have no operands (for better performance and smaller code). */
1358
1359 if (mnemonic[0] != 'f')
1360 return 0; /* non-math */
1361
1362 switch (mnemonic[1])
1363 {
1364 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1365 the fs segment override prefix not currently handled because no
1366 call path can make opcodes without operands get here */
1367 case 'i':
1368 return 2 /* integer op */;
1369 case 'l':
1370 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1371 return 3; /* fldcw/fldenv */
1372 break;
1373 case 'n':
1374 if (mnemonic[2] != 'o' /* fnop */)
1375 return 3; /* non-waiting control op */
1376 break;
1377 case 'r':
1378 if (mnemonic[2] == 's')
1379 return 3; /* frstor/frstpm */
1380 break;
1381 case 's':
1382 if (mnemonic[2] == 'a')
1383 return 3; /* fsave */
1384 if (mnemonic[2] == 't')
1385 {
1386 switch (mnemonic[3])
1387 {
1388 case 'c': /* fstcw */
1389 case 'd': /* fstdw */
1390 case 'e': /* fstenv */
1391 case 's': /* fsts[gw] */
1392 return 3;
1393 }
1394 }
1395 break;
1396 case 'x':
1397 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1398 return 0; /* fxsave/fxrstor are not really math ops */
1399 break;
1400 }
252b5132 1401
9306ca4a 1402 return 1;
252b5132
RH		 1403}
1404
1405/* This is the guts of the machine-dependent assembler. LINE points to a
1406 machine dependent instruction. This function is supposed to emit
1407 the frags/bytes it assembles to. */
1408
1409void
1410md_assemble (line)
1411 char *line;
1412{
252b5132 1413 int j;
252b5132
RH		 1414 char mnemonic[MAX_MNEM_SIZE];
1415
47926f60 1416 /* Initialize globals. */
252b5132
RH		 1417 memset (&i, '\0', sizeof (i));
1418 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1419 i.reloc[j] = NO_RELOC;
252b5132
RH		 1420 memset (disp_expressions, '\0', sizeof (disp_expressions));
1421 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1422 save_stack_p = save_stack;
252b5132
RH		 1423
1424 /* First parse an instruction mnemonic & call i386_operand for the operands.
1425 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1426 start of a (possibly prefixed) mnemonic. */
252b5132 1427
29b0f896
AM		 1428 line = parse_insn (line, mnemonic);
1429 if (line == NULL)
1430 return;
252b5132 1431
29b0f896
AM		 1432 line = parse_operands (line, mnemonic);
1433 if (line == NULL)
1434 return;
252b5132 1435
29b0f896
AM		 1436 /* Now we've parsed the mnemonic into a set of templates, and have the
1437 operands at hand. */
1438
1439 /* All intel opcodes have reversed operands except for "bound" and
1440 "enter". We also don't reverse intersegment "jmp" and "call"
1441 instructions with 2 immediate operands so that the immediate segment
1442 precedes the offset, as it does when in AT&T mode. "enter" and the
1443 intersegment "jmp" and "call" instructions are the only ones that
1444 have two immediate operands. */
1445 if (intel_syntax && i.operands > 1
1446 && (strcmp (mnemonic, "bound") != 0)
30123838 1447 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1448 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1449 swap_operands ();
1450
1451 if (i.imm_operands)
1452 optimize_imm ();
1453
b300c311
L		 1454 /* Don't optimize displacement for movabs since it only takes 64bit
1455 displacement. */
1456 if (i.disp_operands
1457 && (flag_code != CODE_64BIT
1458 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1459 optimize_disp ();
1460
1461 /* Next, we find a template that matches the given insn,
1462 making sure the overlap of the given operands types is consistent
1463 with the template operand types. */
252b5132 1464
29b0f896
AM		 1465 if (!match_template ())
1466 return;
252b5132 1467
cd61ebfe
AM		 1468 if (intel_syntax)
1469 {
1470 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1471 if (SYSV386_COMPAT
1472 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1473 i.tm.base_opcode ^= FloatR;
1474
1475 /* Zap movzx and movsx suffix. The suffix may have been set from
1476 "word ptr" or "byte ptr" on the source operand, but we'll use
1477 the suffix later to choose the destination register. */
1478 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1479 {
1480 if (i.reg_operands < 2
1481 && !i.suffix
1482 && (~i.tm.opcode_modifier
1483 & (No_bSuf
1484 | No_wSuf
1485 | No_lSuf
1486 | No_sSuf
1487 | No_xSuf
1488 | No_qSuf)))
1489 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1490
1491 i.suffix = 0;
1492 }
cd61ebfe 1493 }
24eab124 1494
29b0f896
AM		 1495 if (i.tm.opcode_modifier & FWait)
1496 if (!add_prefix (FWAIT_OPCODE))
1497 return;
252b5132 1498
29b0f896
AM		 1499 /* Check string instruction segment overrides. */
1500 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1501 {
1502 if (!check_string ())
5dd0794d 1503 return;
29b0f896 1504 }
5dd0794d 1505
29b0f896
AM		 1506 if (!process_suffix ())
1507 return;
e413e4e9 1508
29b0f896
AM		 1509 /* Make still unresolved immediate matches conform to size of immediate
1510 given in i.suffix. */
1511 if (!finalize_imm ())
1512 return;
252b5132 1513
29b0f896
AM		 1514 if (i.types[0] & Imm1)
1515 i.imm_operands = 0; /* kludge for shift insns. */
1516 if (i.types[0] & ImplicitRegister)
1517 i.reg_operands--;
1518 if (i.types[1] & ImplicitRegister)
1519 i.reg_operands--;
1520 if (i.types[2] & ImplicitRegister)
1521 i.reg_operands--;
252b5132 1522
29b0f896
AM		 1523 if (i.tm.opcode_modifier & ImmExt)
1524 {
02fc3089
L		 1525 expressionS *exp;
1526
ca164297
L		 1527 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1528 {
67c1ffbe 1529 /* These Intel Prescott New Instructions have the fixed
ca164297
L		 1530 operands with an opcode suffix which is coded in the same
1531 place as an 8-bit immediate field would be. Here we check
1532 those operands and remove them afterwards. */
1533 unsigned int x;
1534
a4622f40 1535 for (x = 0; x < i.operands; x++)
ca164297
L		 1536 if (i.op[x].regs->reg_num != x)
1537 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1538 i.op[x].regs->reg_name, x + 1, i.tm.name);
1539 i.operands = 0;
1540 }
1541
29b0f896
AM		 1542 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1543 opcode suffix which is coded in the same place as an 8-bit
1544 immediate field would be. Here we fake an 8-bit immediate
1545 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1546
29b0f896 1547 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1548
29b0f896
AM		 1549 exp = &im_expressions[i.imm_operands++];
1550 i.op[i.operands].imms = exp;
1551 i.types[i.operands++] = Imm8;
1552 exp->X_op = O_constant;
1553 exp->X_add_number = i.tm.extension_opcode;
1554 i.tm.extension_opcode = None;
1555 }
252b5132 1556
29b0f896
AM		 1557 /* For insns with operands there are more diddles to do to the opcode. */
1558 if (i.operands)
1559 {
1560 if (!process_operands ())
1561 return;
1562 }
1563 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1564 {
1565 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1566 as_warn (_("translating to `%sp'"), i.tm.name);
1567 }
252b5132 1568
29b0f896
AM		 1569 /* Handle conversion of 'int $3' --> special int3 insn. */
1570 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1571 {
1572 i.tm.base_opcode = INT3_OPCODE;
1573 i.imm_operands = 0;
1574 }
252b5132 1575
29b0f896
AM		 1576 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1577 && i.op[0].disps->X_op == O_constant)
1578 {
1579 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1580 the absolute address given by the constant. Since ix86 jumps and
1581 calls are pc relative, we need to generate a reloc. */
1582 i.op[0].disps->X_add_symbol = &abs_symbol;
1583 i.op[0].disps->X_op = O_symbol;
1584 }
252b5132 1585
29b0f896
AM		 1586 if ((i.tm.opcode_modifier & Rex64) != 0)
1587 i.rex |= REX_MODE64;
252b5132 1588
29b0f896
AM		 1589 /* For 8 bit registers we need an empty rex prefix. Also if the
1590 instruction already has a prefix, we need to convert old
1591 registers to new ones. */
773f551c 1592
29b0f896
AM		 1593 if (((i.types[0] & Reg8) != 0
1594 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1595 || ((i.types[1] & Reg8) != 0
1596 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1597 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1598 && i.rex != 0))
1599 {
1600 int x;
726c5dcd 1601
29b0f896
AM		 1602 i.rex |= REX_OPCODE;
1603 for (x = 0; x < 2; x++)
1604 {
1605 /* Look for 8 bit operand that uses old registers. */
1606 if ((i.types[x] & Reg8) != 0
1607 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1608 {
29b0f896
AM		 1609 /* In case it is "hi" register, give up. */
1610 if (i.op[x].regs->reg_num > 3)
0477af35 1611 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1612 i.op[x].regs->reg_name);
773f551c 1613
29b0f896
AM		 1614 /* Otherwise it is equivalent to the extended register.
1615 Since the encoding doesn't change this is merely
1616 cosmetic cleanup for debug output. */
1617
1618 i.op[x].regs = i.op[x].regs + 8;
773f551c 1619 }
29b0f896
AM		 1620 }
1621 }
773f551c 1622
29b0f896
AM		 1623 if (i.rex != 0)
1624 add_prefix (REX_OPCODE | i.rex);
1625
1626 /* We are ready to output the insn. */
1627 output_insn ();
1628}
1629
1630static char *
1631parse_insn (line, mnemonic)
1632 char *line;
1633 char *mnemonic;
1634{
1635 char *l = line;
1636 char *token_start = l;
1637 char *mnem_p;
5c6af06e
JB		 1638 int supported;
1639 const template *t;
29b0f896
AM		 1640
1641 /* Non-zero if we found a prefix only acceptable with string insns. */
1642 const char *expecting_string_instruction = NULL;
45288df1 1643
29b0f896
AM		 1644 while (1)
1645 {
1646 mnem_p = mnemonic;
1647 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1648 {
1649 mnem_p++;
1650 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1651 {
29b0f896
AM		 1652 as_bad (_("no such instruction: `%s'"), token_start);
1653 return NULL;
1654 }
1655 l++;
1656 }
1657 if (!is_space_char (*l)
1658 && *l != END_OF_INSN
e44823cf
JB		 1659 && (intel_syntax
1660 || (*l != PREFIX_SEPARATOR
1661 && *l != ',')))
29b0f896
AM		 1662 {
1663 as_bad (_("invalid character %s in mnemonic"),
1664 output_invalid (*l));
1665 return NULL;
1666 }
1667 if (token_start == l)
1668 {
e44823cf 1669 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1670 as_bad (_("expecting prefix; got nothing"));
1671 else
1672 as_bad (_("expecting mnemonic; got nothing"));
1673 return NULL;
1674 }
45288df1 1675
29b0f896
AM		 1676 /* Look up instruction (or prefix) via hash table. */
1677 current_templates = hash_find (op_hash, mnemonic);
47926f60 1678
29b0f896
AM		 1679 if (*l != END_OF_INSN
1680 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1681 && current_templates
1682 && (current_templates->start->opcode_modifier & IsPrefix))
1683 {
2dd88dca
JB		 1684 if (current_templates->start->cpu_flags
1685 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1686 {
1687 as_bad ((flag_code != CODE_64BIT
1688 ? _("`%s' is only supported in 64-bit mode")
1689 : _("`%s' is not supported in 64-bit mode")),
1690 current_templates->start->name);
1691 return NULL;
1692 }
29b0f896
AM		 1693 /* If we are in 16-bit mode, do not allow addr16 or data16.
1694 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1695 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1696 && flag_code != CODE_64BIT
1697 && (((current_templates->start->opcode_modifier & Size32) != 0)
1698 ^ (flag_code == CODE_16BIT)))
1699 {
1700 as_bad (_("redundant %s prefix"),
1701 current_templates->start->name);
1702 return NULL;
45288df1 1703 }
29b0f896
AM		 1704 /* Add prefix, checking for repeated prefixes. */
1705 switch (add_prefix (current_templates->start->base_opcode))
1706 {
1707 case 0:
1708 return NULL;
1709 case 2:
1710 expecting_string_instruction = current_templates->start->name;
1711 break;
1712 }
1713 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1714 token_start = ++l;
1715 }
1716 else
1717 break;
1718 }
45288df1 1719
29b0f896
AM		 1720 if (!current_templates)
1721 {
1722 /* See if we can get a match by trimming off a suffix. */
1723 switch (mnem_p[-1])
1724 {
1725 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 1726 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
1727 i.suffix = SHORT_MNEM_SUFFIX;
1728 else
29b0f896
AM		 1729 case BYTE_MNEM_SUFFIX:
1730 case QWORD_MNEM_SUFFIX:
1731 i.suffix = mnem_p[-1];
1732 mnem_p[-1] = '\0';
1733 current_templates = hash_find (op_hash, mnemonic);
1734 break;
1735 case SHORT_MNEM_SUFFIX:
1736 case LONG_MNEM_SUFFIX:
1737 if (!intel_syntax)
1738 {
1739 i.suffix = mnem_p[-1];
1740 mnem_p[-1] = '\0';
1741 current_templates = hash_find (op_hash, mnemonic);
1742 }
1743 break;
252b5132 1744
29b0f896
AM		 1745 /* Intel Syntax. */
1746 case 'd':
1747 if (intel_syntax)
1748 {
9306ca4a 1749 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 1750 i.suffix = SHORT_MNEM_SUFFIX;
1751 else
1752 i.suffix = LONG_MNEM_SUFFIX;
1753 mnem_p[-1] = '\0';
1754 current_templates = hash_find (op_hash, mnemonic);
1755 }
1756 break;
1757 }
1758 if (!current_templates)
1759 {
1760 as_bad (_("no such instruction: `%s'"), token_start);
1761 return NULL;
1762 }
1763 }
252b5132 1764
29b0f896
AM		 1765 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1766 {
1767 /* Check for a branch hint. We allow ",pt" and ",pn" for
1768 predict taken and predict not taken respectively.
1769 I'm not sure that branch hints actually do anything on loop
1770 and jcxz insns (JumpByte) for current Pentium4 chips. They
1771 may work in the future and it doesn't hurt to accept them
1772 now. */
1773 if (l[0] == ',' && l[1] == 'p')
1774 {
1775 if (l[2] == 't')
1776 {
1777 if (!add_prefix (DS_PREFIX_OPCODE))
1778 return NULL;
1779 l += 3;
1780 }
1781 else if (l[2] == 'n')
1782 {
1783 if (!add_prefix (CS_PREFIX_OPCODE))
1784 return NULL;
1785 l += 3;
1786 }
1787 }
1788 }
1789 /* Any other comma loses. */
1790 if (*l == ',')
1791 {
1792 as_bad (_("invalid character %s in mnemonic"),
1793 output_invalid (*l));
1794 return NULL;
1795 }
252b5132 1796
29b0f896 1797 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 1798 supported = 0;
1799 for (t = current_templates->start; t < current_templates->end; ++t)
1800 {
1801 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
1802 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
1803 supported |= 1;
1804 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
1805 supported |= 2;
1806 }
1807 if (!(supported & 2))
1808 {
1809 as_bad (flag_code == CODE_64BIT
1810 ? _("`%s' is not supported in 64-bit mode")
1811 : _("`%s' is only supported in 64-bit mode"),
1812 current_templates->start->name);
1813 return NULL;
1814 }
1815 if (!(supported & 1))
29b0f896 1816 {
5c6af06e
JB		 1817 as_warn (_("`%s' is not supported on `%s%s'"),
1818 current_templates->start->name,
1819 cpu_arch_name,
1820 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 1821 }
1822 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1823 {
1824 as_warn (_("use .code16 to ensure correct addressing mode"));
1825 }
252b5132 1826
29b0f896 1827 /* Check for rep/repne without a string instruction. */
f41bbced 1828 if (expecting_string_instruction)
29b0f896 1829 {
f41bbced
JB		 1830 static templates override;
1831
1832 for (t = current_templates->start; t < current_templates->end; ++t)
1833 if (t->opcode_modifier & IsString)
1834 break;
1835 if (t >= current_templates->end)
1836 {
1837 as_bad (_("expecting string instruction after `%s'"),
1838 expecting_string_instruction);
1839 return NULL;
1840 }
1841 for (override.start = t; t < current_templates->end; ++t)
1842 if (!(t->opcode_modifier & IsString))
1843 break;
1844 override.end = t;
1845 current_templates = &override;
29b0f896 1846 }
252b5132 1847
29b0f896
AM		 1848 return l;
1849}
252b5132 1850
29b0f896
AM		 1851static char *
1852parse_operands (l, mnemonic)
1853 char *l;
1854 const char *mnemonic;
1855{
1856 char *token_start;
3138f287 1857
29b0f896
AM		 1858 /* 1 if operand is pending after ','. */
1859 unsigned int expecting_operand = 0;
252b5132 1860
29b0f896
AM		 1861 /* Non-zero if operand parens not balanced. */
1862 unsigned int paren_not_balanced;
1863
1864 while (*l != END_OF_INSN)
1865 {
1866 /* Skip optional white space before operand. */
1867 if (is_space_char (*l))
1868 ++l;
1869 if (!is_operand_char (*l) && *l != END_OF_INSN)
1870 {
1871 as_bad (_("invalid character %s before operand %d"),
1872 output_invalid (*l),
1873 i.operands + 1);
1874 return NULL;
1875 }
1876 token_start = l; /* after white space */
1877 paren_not_balanced = 0;
1878 while (paren_not_balanced || *l != ',')
1879 {
1880 if (*l == END_OF_INSN)
1881 {
1882 if (paren_not_balanced)
1883 {
1884 if (!intel_syntax)
1885 as_bad (_("unbalanced parenthesis in operand %d."),
1886 i.operands + 1);
1887 else
1888 as_bad (_("unbalanced brackets in operand %d."),
1889 i.operands + 1);
1890 return NULL;
1891 }
1892 else
1893 break; /* we are done */
1894 }
1895 else if (!is_operand_char (*l) && !is_space_char (*l))
1896 {
1897 as_bad (_("invalid character %s in operand %d"),
1898 output_invalid (*l),
1899 i.operands + 1);
1900 return NULL;
1901 }
1902 if (!intel_syntax)
1903 {
1904 if (*l == '(')
1905 ++paren_not_balanced;
1906 if (*l == ')')
1907 --paren_not_balanced;
1908 }
1909 else
1910 {
1911 if (*l == '[')
1912 ++paren_not_balanced;
1913 if (*l == ']')
1914 --paren_not_balanced;
1915 }
1916 l++;
1917 }
1918 if (l != token_start)
1919 { /* Yes, we've read in another operand. */
1920 unsigned int operand_ok;
1921 this_operand = i.operands++;
1922 if (i.operands > MAX_OPERANDS)
1923 {
1924 as_bad (_("spurious operands; (%d operands/instruction max)"),
1925 MAX_OPERANDS);
1926 return NULL;
1927 }
1928 /* Now parse operand adding info to 'i' as we go along. */
1929 END_STRING_AND_SAVE (l);
1930
1931 if (intel_syntax)
1932 operand_ok =
1933 i386_intel_operand (token_start,
1934 intel_float_operand (mnemonic));
1935 else
1936 operand_ok = i386_operand (token_start);
1937
1938 RESTORE_END_STRING (l);
1939 if (!operand_ok)
1940 return NULL;
1941 }
1942 else
1943 {
1944 if (expecting_operand)
1945 {
1946 expecting_operand_after_comma:
1947 as_bad (_("expecting operand after ','; got nothing"));
1948 return NULL;
1949 }
1950 if (*l == ',')
1951 {
1952 as_bad (_("expecting operand before ','; got nothing"));
1953 return NULL;
1954 }
1955 }
7f3f1ea2 1956
29b0f896
AM		 1957 /* Now *l must be either ',' or END_OF_INSN. */
1958 if (*l == ',')
1959 {
1960 if (*++l == END_OF_INSN)
1961 {
1962 /* Just skip it, if it's \n complain. */
1963 goto expecting_operand_after_comma;
1964 }
1965 expecting_operand = 1;
1966 }
1967 }
1968 return l;
1969}
7f3f1ea2 1970
29b0f896
AM		 1971static void
1972swap_operands ()
1973{
1974 union i386_op temp_op;
1975 unsigned int temp_type;
f86103b7 1976 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 1977 int xchg1 = 0;
1978 int xchg2 = 0;
252b5132 1979
29b0f896
AM		 1980 if (i.operands == 2)
1981 {
1982 xchg1 = 0;
1983 xchg2 = 1;
1984 }
1985 else if (i.operands == 3)
1986 {
1987 xchg1 = 0;
1988 xchg2 = 2;
1989 }
1990 temp_type = i.types[xchg2];
1991 i.types[xchg2] = i.types[xchg1];
1992 i.types[xchg1] = temp_type;
1993 temp_op = i.op[xchg2];
1994 i.op[xchg2] = i.op[xchg1];
1995 i.op[xchg1] = temp_op;
1996 temp_reloc = i.reloc[xchg2];
1997 i.reloc[xchg2] = i.reloc[xchg1];
1998 i.reloc[xchg1] = temp_reloc;
1999
2000 if (i.mem_operands == 2)
2001 {
2002 const seg_entry *temp_seg;
2003 temp_seg = i.seg[0];
2004 i.seg[0] = i.seg[1];
2005 i.seg[1] = temp_seg;
2006 }
2007}
252b5132 2008
29b0f896
AM		 2009/* Try to ensure constant immediates are represented in the smallest
2010 opcode possible. */
2011static void
2012optimize_imm ()
2013{
2014 char guess_suffix = 0;
2015 int op;
252b5132 2016
29b0f896
AM		 2017 if (i.suffix)
2018 guess_suffix = i.suffix;
2019 else if (i.reg_operands)
2020 {
2021 /* Figure out a suffix from the last register operand specified.
2022 We can't do this properly yet, ie. excluding InOutPortReg,
2023 but the following works for instructions with immediates.
2024 In any case, we can't set i.suffix yet. */
2025 for (op = i.operands; --op >= 0;)
2026 if (i.types[op] & Reg)
252b5132 2027 {
29b0f896
AM		 2028 if (i.types[op] & Reg8)
2029 guess_suffix = BYTE_MNEM_SUFFIX;
2030 else if (i.types[op] & Reg16)
2031 guess_suffix = WORD_MNEM_SUFFIX;
2032 else if (i.types[op] & Reg32)
2033 guess_suffix = LONG_MNEM_SUFFIX;
2034 else if (i.types[op] & Reg64)
2035 guess_suffix = QWORD_MNEM_SUFFIX;
2036 break;
252b5132 2037 }
29b0f896
AM		 2038 }
2039 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2040 guess_suffix = WORD_MNEM_SUFFIX;
2041
2042 for (op = i.operands; --op >= 0;)
2043 if (i.types[op] & Imm)
2044 {
2045 switch (i.op[op].imms->X_op)
252b5132 2046 {
29b0f896
AM		 2047 case O_constant:
2048 /* If a suffix is given, this operand may be shortened. */
2049 switch (guess_suffix)
252b5132 2050 {
29b0f896
AM		 2051 case LONG_MNEM_SUFFIX:
2052 i.types[op] |= Imm32 | Imm64;
2053 break;
2054 case WORD_MNEM_SUFFIX:
2055 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2056 break;
2057 case BYTE_MNEM_SUFFIX:
2058 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2059 break;
252b5132 2060 }
252b5132 2061
29b0f896
AM		 2062 /* If this operand is at most 16 bits, convert it
2063 to a signed 16 bit number before trying to see
2064 whether it will fit in an even smaller size.
2065 This allows a 16-bit operand such as $0xffe0 to
2066 be recognised as within Imm8S range. */
2067 if ((i.types[op] & Imm16)
2068 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2069 {
29b0f896
AM		 2070 i.op[op].imms->X_add_number =
2071 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2072 }
2073 if ((i.types[op] & Imm32)
2074 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2075 == 0))
2076 {
2077 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2078 ^ ((offsetT) 1 << 31))
2079 - ((offsetT) 1 << 31));
2080 }
2081 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2082
29b0f896
AM		 2083 /* We must avoid matching of Imm32 templates when 64bit
2084 only immediate is available. */
2085 if (guess_suffix == QWORD_MNEM_SUFFIX)
2086 i.types[op] &= ~Imm32;
2087 break;
252b5132 2088
29b0f896
AM		 2089 case O_absent:
2090 case O_register:
2091 abort ();
2092
2093 /* Symbols and expressions. */
2094 default:
9cd96992
JB		 2095 /* Convert symbolic operand to proper sizes for matching, but don't
2096 prevent matching a set of insns that only supports sizes other
2097 than those matching the insn suffix. */
2098 {
2099 unsigned int mask, allowed = 0;
2100 const template *t;
2101
2102 for (t = current_templates->start; t < current_templates->end; ++t)
2103 allowed |= t->operand_types[op];
2104 switch (guess_suffix)
2105 {
2106 case QWORD_MNEM_SUFFIX:
2107 mask = Imm64 | Imm32S;
2108 break;
2109 case LONG_MNEM_SUFFIX:
2110 mask = Imm32;
2111 break;
2112 case WORD_MNEM_SUFFIX:
2113 mask = Imm16;
2114 break;
2115 case BYTE_MNEM_SUFFIX:
2116 mask = Imm8;
2117 break;
2118 default:
2119 mask = 0;
2120 break;
2121 }
2122 if (mask & allowed)
2123 i.types[op] &= mask;
2124 }
29b0f896 2125 break;
252b5132 2126 }
29b0f896
AM		 2127 }
2128}
47926f60 2129
29b0f896
AM		 2130/* Try to use the smallest displacement type too. */
2131static void
2132optimize_disp ()
2133{
2134 int op;
3e73aa7c 2135
29b0f896 2136 for (op = i.operands; --op >= 0;)
b300c311 2137 if (i.types[op] & Disp)
252b5132 2138 {
b300c311 2139 if (i.op[op].disps->X_op == O_constant)
252b5132 2140 {
b300c311 2141 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2142
b300c311
L		 2143 if ((i.types[op] & Disp16)
2144 && (disp & ~(offsetT) 0xffff) == 0)
2145 {
2146 /* If this operand is at most 16 bits, convert
2147 to a signed 16 bit number and don't use 64bit
2148 displacement. */
2149 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2150 i.types[op] &= ~Disp64;
2151 }
2152 if ((i.types[op] & Disp32)
2153 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2154 {
2155 /* If this operand is at most 32 bits, convert
2156 to a signed 32 bit number and don't use 64bit
2157 displacement. */
2158 disp &= (((offsetT) 2 << 31) - 1);
2159 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2160 i.types[op] &= ~Disp64;
2161 }
2162 if (!disp && (i.types[op] & BaseIndex))
2163 {
2164 i.types[op] &= ~Disp;
2165 i.op[op].disps = 0;
2166 i.disp_operands--;
2167 }
2168 else if (flag_code == CODE_64BIT)
2169 {
2170 if (fits_in_signed_long (disp))
28a9d8f5
L		 2171 {
2172 i.types[op] &= ~Disp64;
2173 i.types[op] |= Disp32S;
2174 }
b300c311
L		 2175 if (fits_in_unsigned_long (disp))
2176 i.types[op] |= Disp32;
2177 }
2178 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2179 && fits_in_signed_byte (disp))
2180 i.types[op] |= Disp8;
252b5132 2181 }
b300c311
L		 2182 else
2183 /* We only support 64bit displacement on constants. */
2184 i.types[op] &= ~Disp64;
252b5132 2185 }
29b0f896
AM		 2186}
2187
2188static int
2189match_template ()
2190{
2191 /* Points to template once we've found it. */
2192 const template *t;
2193 unsigned int overlap0, overlap1, overlap2;
2194 unsigned int found_reverse_match;
2195 int suffix_check;
2196
2197#define MATCH(overlap, given, template) \
2198 ((overlap & ~JumpAbsolute) \
2199 && (((given) & (BaseIndex | JumpAbsolute)) \
2200 == ((overlap) & (BaseIndex | JumpAbsolute))))
2201
2202 /* If given types r0 and r1 are registers they must be of the same type
2203 unless the expected operand type register overlap is null.
2204 Note that Acc in a template matches every size of reg. */
2205#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2206 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2207 || ((g0) & Reg) == ((g1) & Reg) \
2208 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2209
2210 overlap0 = 0;
2211 overlap1 = 0;
2212 overlap2 = 0;
2213 found_reverse_match = 0;
2214 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2215 ? No_bSuf
2216 : (i.suffix == WORD_MNEM_SUFFIX
2217 ? No_wSuf
2218 : (i.suffix == SHORT_MNEM_SUFFIX
2219 ? No_sSuf
2220 : (i.suffix == LONG_MNEM_SUFFIX
2221 ? No_lSuf
2222 : (i.suffix == QWORD_MNEM_SUFFIX
2223 ? No_qSuf
2224 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2225 ? No_xSuf : 0))))));
2226
20f0a1fc
NC		 2227 t = current_templates->start;
2228 if (i.suffix == QWORD_MNEM_SUFFIX
2229 && flag_code != CODE_64BIT
9306ca4a
JB		 2230 && (intel_syntax
2231 ? !(t->opcode_modifier & IgnoreSize)
2232 && !intel_float_operand (t->name)
2233 : intel_float_operand (t->name) != 2)
20f0a1fc
NC		 2234 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2235 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2236 && (t->base_opcode != 0x0fc7
2237 || t->extension_opcode != 1 /* cmpxchg8b */))
2238 t = current_templates->end;
2239 for (; t < current_templates->end; t++)
29b0f896
AM		 2240 {
2241 /* Must have right number of operands. */
2242 if (i.operands != t->operands)
2243 continue;
2244
2245 /* Check the suffix, except for some instructions in intel mode. */
2246 if ((t->opcode_modifier & suffix_check)
2247 && !(intel_syntax
9306ca4a 2248 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2249 continue;
2250
2251 /* Do not verify operands when there are none. */
2252 else if (!t->operands)
2253 {
2254 if (t->cpu_flags & ~cpu_arch_flags)
2255 continue;
2256 /* We've found a match; break out of loop. */
2257 break;
2258 }
252b5132 2259
29b0f896
AM		 2260 overlap0 = i.types[0] & t->operand_types[0];
2261 switch (t->operands)
2262 {
2263 case 1:
2264 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2265 continue;
2266 break;
2267 case 2:
2268 case 3:
2269 overlap1 = i.types[1] & t->operand_types[1];
2270 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2271 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2272 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2273 t->operand_types[0],
2274 overlap1, i.types[1],
2275 t->operand_types[1]))
2276 {
2277 /* Check if other direction is valid ... */
2278 if ((t->opcode_modifier & (D | FloatD)) == 0)
2279 continue;
2280
2281 /* Try reversing direction of operands. */
2282 overlap0 = i.types[0] & t->operand_types[1];
2283 overlap1 = i.types[1] & t->operand_types[0];
2284 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2285 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2286 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2287 t->operand_types[1],
2288 overlap1, i.types[1],
2289 t->operand_types[0]))
2290 {
2291 /* Does not match either direction. */
2292 continue;
2293 }
2294 /* found_reverse_match holds which of D or FloatDR
2295 we've found. */
2296 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2297 }
2298 /* Found a forward 2 operand match here. */
2299 else if (t->operands == 3)
2300 {
2301 /* Here we make use of the fact that there are no
2302 reverse match 3 operand instructions, and all 3
2303 operand instructions only need to be checked for
2304 register consistency between operands 2 and 3. */
2305 overlap2 = i.types[2] & t->operand_types[2];
2306 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2307 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2308 t->operand_types[1],
2309 overlap2, i.types[2],
2310 t->operand_types[2]))
2311
2312 continue;
2313 }
2314 /* Found either forward/reverse 2 or 3 operand match here:
2315 slip through to break. */
2316 }
2317 if (t->cpu_flags & ~cpu_arch_flags)
2318 {
2319 found_reverse_match = 0;
2320 continue;
2321 }
2322 /* We've found a match; break out of loop. */
2323 break;
2324 }
2325
2326 if (t == current_templates->end)
2327 {
2328 /* We found no match. */
2329 as_bad (_("suffix or operands invalid for `%s'"),
2330 current_templates->start->name);
2331 return 0;
2332 }
252b5132 2333
29b0f896
AM		 2334 if (!quiet_warnings)
2335 {
2336 if (!intel_syntax
2337 && ((i.types[0] & JumpAbsolute)
2338 != (t->operand_types[0] & JumpAbsolute)))
2339 {
2340 as_warn (_("indirect %s without `*'"), t->name);
2341 }
2342
2343 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2344 == (IsPrefix | IgnoreSize))
2345 {
2346 /* Warn them that a data or address size prefix doesn't
2347 affect assembly of the next line of code. */
2348 as_warn (_("stand-alone `%s' prefix"), t->name);
2349 }
2350 }
2351
2352 /* Copy the template we found. */
2353 i.tm = *t;
2354 if (found_reverse_match)
2355 {
2356 /* If we found a reverse match we must alter the opcode
2357 direction bit. found_reverse_match holds bits to change
2358 (different for int & float insns). */
2359
2360 i.tm.base_opcode ^= found_reverse_match;
2361
2362 i.tm.operand_types[0] = t->operand_types[1];
2363 i.tm.operand_types[1] = t->operand_types[0];
2364 }
2365
2366 return 1;
2367}
2368
2369static int
2370check_string ()
2371{
2372 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2373 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2374 {
2375 if (i.seg[0] != NULL && i.seg[0] != &es)
2376 {
2377 as_bad (_("`%s' operand %d must use `%%es' segment"),
2378 i.tm.name,
2379 mem_op + 1);
2380 return 0;
2381 }
2382 /* There's only ever one segment override allowed per instruction.
2383 This instruction possibly has a legal segment override on the
2384 second operand, so copy the segment to where non-string
2385 instructions store it, allowing common code. */
2386 i.seg[0] = i.seg[1];
2387 }
2388 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2389 {
2390 if (i.seg[1] != NULL && i.seg[1] != &es)
2391 {
2392 as_bad (_("`%s' operand %d must use `%%es' segment"),
2393 i.tm.name,
2394 mem_op + 2);
2395 return 0;
2396 }
2397 }
2398 return 1;
2399}
2400
2401static int
543613e9 2402process_suffix (void)
29b0f896
AM		 2403{
2404 /* If matched instruction specifies an explicit instruction mnemonic
2405 suffix, use it. */
2406 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2407 {
2408 if (i.tm.opcode_modifier & Size16)
2409 i.suffix = WORD_MNEM_SUFFIX;
2410 else if (i.tm.opcode_modifier & Size64)
2411 i.suffix = QWORD_MNEM_SUFFIX;
2412 else
2413 i.suffix = LONG_MNEM_SUFFIX;
2414 }
2415 else if (i.reg_operands)
2416 {
2417 /* If there's no instruction mnemonic suffix we try to invent one
2418 based on register operands. */
2419 if (!i.suffix)
2420 {
2421 /* We take i.suffix from the last register operand specified,
2422 Destination register type is more significant than source
2423 register type. */
2424 int op;
543613e9 2425
29b0f896
AM		 2426 for (op = i.operands; --op >= 0;)
2427 if ((i.types[op] & Reg)
2428 && !(i.tm.operand_types[op] & InOutPortReg))
2429 {
2430 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2431 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2432 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2433 LONG_MNEM_SUFFIX);
2434 break;
2435 }
2436 }
2437 else if (i.suffix == BYTE_MNEM_SUFFIX)
2438 {
2439 if (!check_byte_reg ())
2440 return 0;
2441 }
2442 else if (i.suffix == LONG_MNEM_SUFFIX)
2443 {
2444 if (!check_long_reg ())
2445 return 0;
2446 }
2447 else if (i.suffix == QWORD_MNEM_SUFFIX)
2448 {
2449 if (!check_qword_reg ())
2450 return 0;
2451 }
2452 else if (i.suffix == WORD_MNEM_SUFFIX)
2453 {
2454 if (!check_word_reg ())
2455 return 0;
2456 }
2457 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2458 /* Do nothing if the instruction is going to ignore the prefix. */
2459 ;
2460 else
2461 abort ();
2462 }
9306ca4a
JB		 2463 else if ((i.tm.opcode_modifier & DefaultSize)
2464 && !i.suffix
2465 /* exclude fldenv/frstor/fsave/fstenv */
2466 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2467 {
2468 i.suffix = stackop_size;
2469 }
9306ca4a
JB		 2470 else if (intel_syntax
2471 && !i.suffix
2472 && ((i.tm.operand_types[0] & JumpAbsolute)
2473 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2474 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2475 && i.tm.extension_opcode <= 3)))
2476 {
2477 switch (flag_code)
2478 {
2479 case CODE_64BIT:
2480 if (!(i.tm.opcode_modifier & No_qSuf))
2481 {
2482 i.suffix = QWORD_MNEM_SUFFIX;
2483 break;
2484 }
2485 case CODE_32BIT:
2486 if (!(i.tm.opcode_modifier & No_lSuf))
2487 i.suffix = LONG_MNEM_SUFFIX;
2488 break;
2489 case CODE_16BIT:
2490 if (!(i.tm.opcode_modifier & No_wSuf))
2491 i.suffix = WORD_MNEM_SUFFIX;
2492 break;
2493 }
2494 }
252b5132 2495
9306ca4a 2496 if (!i.suffix)
29b0f896 2497 {
9306ca4a
JB		 2498 if (!intel_syntax)
2499 {
2500 if (i.tm.opcode_modifier & W)
2501 {
2502 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2503 return 0;
2504 }
2505 }
2506 else
2507 {
2508 unsigned int suffixes = ~i.tm.opcode_modifier
2509 & (No_bSuf
2510 | No_wSuf
2511 | No_lSuf
2512 | No_sSuf
2513 | No_xSuf
2514 | No_qSuf);
2515
2516 if ((i.tm.opcode_modifier & W)
2517 || ((suffixes & (suffixes - 1))
2518 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2519 {
2520 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2521 return 0;
2522 }
2523 }
29b0f896 2524 }
252b5132 2525
9306ca4a
JB		 2526 /* Change the opcode based on the operand size given by i.suffix;
2527 We don't need to change things for byte insns. */
2528
29b0f896
AM		 2529 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2530 {
2531 /* It's not a byte, select word/dword operation. */
2532 if (i.tm.opcode_modifier & W)
2533 {
2534 if (i.tm.opcode_modifier & ShortForm)
2535 i.tm.base_opcode |= 8;
2536 else
2537 i.tm.base_opcode |= 1;
2538 }
0f3f3d8b 2539
29b0f896
AM		 2540 /* Now select between word & dword operations via the operand
2541 size prefix, except for instructions that will ignore this
2542 prefix anyway. */
2543 if (i.suffix != QWORD_MNEM_SUFFIX
9306ca4a
JB		 2544 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2545 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
9146926a
AM		 2546 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2547 || (flag_code == CODE_64BIT
2548 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2549 {
2550 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2551
29b0f896
AM		 2552 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2553 prefix = ADDR_PREFIX_OPCODE;
252b5132 2554
29b0f896
AM		 2555 if (!add_prefix (prefix))
2556 return 0;
24eab124 2557 }
252b5132 2558
29b0f896
AM		 2559 /* Set mode64 for an operand. */
2560 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2561 && flag_code == CODE_64BIT
29b0f896 2562 && (i.tm.opcode_modifier & NoRex64) == 0)
9146926a 2563 i.rex |= REX_MODE64;
3e73aa7c 2564
29b0f896
AM		 2565 /* Size floating point instruction. */
2566 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 2567 if (i.tm.opcode_modifier & FloatMF)
2568 i.tm.base_opcode ^= 4;
29b0f896 2569 }
7ecd2f8b 2570
29b0f896
AM		 2571 return 1;
2572}
3e73aa7c 2573
29b0f896 2574static int
543613e9 2575check_byte_reg (void)
29b0f896
AM		 2576{
2577 int op;
543613e9 2578
29b0f896
AM		 2579 for (op = i.operands; --op >= 0;)
2580 {
2581 /* If this is an eight bit register, it's OK. If it's the 16 or
2582 32 bit version of an eight bit register, we will just use the
2583 low portion, and that's OK too. */
2584 if (i.types[op] & Reg8)
2585 continue;
2586
2587 /* movzx and movsx should not generate this warning. */
2588 if (intel_syntax
2589 && (i.tm.base_opcode == 0xfb7
2590 || i.tm.base_opcode == 0xfb6
2591 || i.tm.base_opcode == 0x63
2592 || i.tm.base_opcode == 0xfbe
2593 || i.tm.base_opcode == 0xfbf))
2594 continue;
2595
65ec77d2 2596 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 2597 {
2598 /* Prohibit these changes in the 64bit mode, since the
2599 lowering is more complicated. */
2600 if (flag_code == CODE_64BIT
2601 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2602 {
0f3f3d8b 2603 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2604 i.op[op].regs->reg_name,
2605 i.suffix);
2606 return 0;
2607 }
2608#if REGISTER_WARNINGS
2609 if (!quiet_warnings
2610 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2611 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2612 (i.op[op].regs + (i.types[op] & Reg16
2613 ? REGNAM_AL - REGNAM_AX
2614 : REGNAM_AL - REGNAM_EAX))->reg_name,
2615 i.op[op].regs->reg_name,
2616 i.suffix);
2617#endif
2618 continue;
2619 }
2620 /* Any other register is bad. */
2621 if (i.types[op] & (Reg | RegMMX | RegXMM
2622 | SReg2 | SReg3
2623 | Control | Debug | Test
2624 | FloatReg | FloatAcc))
2625 {
2626 as_bad (_("`%%%s' not allowed with `%s%c'"),
2627 i.op[op].regs->reg_name,
2628 i.tm.name,
2629 i.suffix);
2630 return 0;
2631 }
2632 }
2633 return 1;
2634}
2635
2636static int
2637check_long_reg ()
2638{
2639 int op;
2640
2641 for (op = i.operands; --op >= 0;)
2642 /* Reject eight bit registers, except where the template requires
2643 them. (eg. movzb) */
2644 if ((i.types[op] & Reg8) != 0
2645 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2646 {
2647 as_bad (_("`%%%s' not allowed with `%s%c'"),
2648 i.op[op].regs->reg_name,
2649 i.tm.name,
2650 i.suffix);
2651 return 0;
2652 }
2653 /* Warn if the e prefix on a general reg is missing. */
2654 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2655 && (i.types[op] & Reg16) != 0
2656 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2657 {
2658 /* Prohibit these changes in the 64bit mode, since the
2659 lowering is more complicated. */
2660 if (flag_code == CODE_64BIT)
252b5132 2661 {
0f3f3d8b 2662 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2663 i.op[op].regs->reg_name,
2664 i.suffix);
2665 return 0;
252b5132 2666 }
29b0f896
AM		 2667#if REGISTER_WARNINGS
2668 else
2669 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2670 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2671 i.op[op].regs->reg_name,
2672 i.suffix);
2673#endif
252b5132 2674 }
29b0f896
AM		 2675 /* Warn if the r prefix on a general reg is missing. */
2676 else if ((i.types[op] & Reg64) != 0
2677 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2678 {
0f3f3d8b 2679 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2680 i.op[op].regs->reg_name,
2681 i.suffix);
2682 return 0;
2683 }
2684 return 1;
2685}
252b5132 2686
29b0f896
AM		 2687static int
2688check_qword_reg ()
2689{
2690 int op;
252b5132 2691
29b0f896
AM		 2692 for (op = i.operands; --op >= 0; )
2693 /* Reject eight bit registers, except where the template requires
2694 them. (eg. movzb) */
2695 if ((i.types[op] & Reg8) != 0
2696 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2697 {
2698 as_bad (_("`%%%s' not allowed with `%s%c'"),
2699 i.op[op].regs->reg_name,
2700 i.tm.name,
2701 i.suffix);
2702 return 0;
2703 }
2704 /* Warn if the e prefix on a general reg is missing. */
2705 else if (((i.types[op] & Reg16) != 0
2706 || (i.types[op] & Reg32) != 0)
2707 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2708 {
2709 /* Prohibit these changes in the 64bit mode, since the
2710 lowering is more complicated. */
0f3f3d8b 2711 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2712 i.op[op].regs->reg_name,
2713 i.suffix);
2714 return 0;
252b5132 2715 }
29b0f896
AM		 2716 return 1;
2717}
252b5132 2718
29b0f896
AM		 2719static int
2720check_word_reg ()
2721{
2722 int op;
2723 for (op = i.operands; --op >= 0;)
2724 /* Reject eight bit registers, except where the template requires
2725 them. (eg. movzb) */
2726 if ((i.types[op] & Reg8) != 0
2727 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2728 {
2729 as_bad (_("`%%%s' not allowed with `%s%c'"),
2730 i.op[op].regs->reg_name,
2731 i.tm.name,
2732 i.suffix);
2733 return 0;
2734 }
2735 /* Warn if the e prefix on a general reg is present. */
2736 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2737 && (i.types[op] & Reg32) != 0
2738 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2739 {
29b0f896
AM		 2740 /* Prohibit these changes in the 64bit mode, since the
2741 lowering is more complicated. */
2742 if (flag_code == CODE_64BIT)
252b5132 2743 {
0f3f3d8b 2744 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2745 i.op[op].regs->reg_name,
2746 i.suffix);
2747 return 0;
252b5132 2748 }
29b0f896
AM		 2749 else
2750#if REGISTER_WARNINGS
2751 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2752 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2753 i.op[op].regs->reg_name,
2754 i.suffix);
2755#endif
2756 }
2757 return 1;
2758}
252b5132 2759
29b0f896
AM		 2760static int
2761finalize_imm ()
2762{
2763 unsigned int overlap0, overlap1, overlap2;
2764
2765 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 2766 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 2767 && overlap0 != Imm8 && overlap0 != Imm8S
2768 && overlap0 != Imm16 && overlap0 != Imm32S
2769 && overlap0 != Imm32 && overlap0 != Imm64)
2770 {
2771 if (i.suffix)
2772 {
2773 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2774 ? Imm8 | Imm8S
2775 : (i.suffix == WORD_MNEM_SUFFIX
2776 ? Imm16
2777 : (i.suffix == QWORD_MNEM_SUFFIX
2778 ? Imm64 | Imm32S
2779 : Imm32)));
2780 }
2781 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2782 || overlap0 == (Imm16 | Imm32)
2783 || overlap0 == (Imm16 | Imm32S))
2784 {
2785 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2786 ? Imm16 : Imm32S);
2787 }
2788 if (overlap0 != Imm8 && overlap0 != Imm8S
2789 && overlap0 != Imm16 && overlap0 != Imm32S
2790 && overlap0 != Imm32 && overlap0 != Imm64)
2791 {
2792 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2793 return 0;
2794 }
2795 }
2796 i.types[0] = overlap0;
2797
2798 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 2799 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 2800 && overlap1 != Imm8 && overlap1 != Imm8S
2801 && overlap1 != Imm16 && overlap1 != Imm32S
2802 && overlap1 != Imm32 && overlap1 != Imm64)
2803 {
2804 if (i.suffix)
2805 {
2806 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2807 ? Imm8 | Imm8S
2808 : (i.suffix == WORD_MNEM_SUFFIX
2809 ? Imm16
2810 : (i.suffix == QWORD_MNEM_SUFFIX
2811 ? Imm64 | Imm32S
2812 : Imm32)));
2813 }
2814 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2815 || overlap1 == (Imm16 | Imm32)
2816 || overlap1 == (Imm16 | Imm32S))
2817 {
2818 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2819 ? Imm16 : Imm32S);
2820 }
2821 if (overlap1 != Imm8 && overlap1 != Imm8S
2822 && overlap1 != Imm16 && overlap1 != Imm32S
2823 && overlap1 != Imm32 && overlap1 != Imm64)
2824 {
2825 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2826 return 0;
2827 }
2828 }
2829 i.types[1] = overlap1;
2830
2831 overlap2 = i.types[2] & i.tm.operand_types[2];
2832 assert ((overlap2 & Imm) == 0);
2833 i.types[2] = overlap2;
2834
2835 return 1;
2836}
2837
2838static int
2839process_operands ()
2840{
2841 /* Default segment register this instruction will use for memory
2842 accesses. 0 means unknown. This is only for optimizing out
2843 unnecessary segment overrides. */
2844 const seg_entry *default_seg = 0;
2845
2846 /* The imul $imm, %reg instruction is converted into
2847 imul $imm, %reg, %reg, and the clr %reg instruction
2848 is converted into xor %reg, %reg. */
2849 if (i.tm.opcode_modifier & regKludge)
2850 {
2851 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2852 /* Pretend we saw the extra register operand. */
2853 assert (i.op[first_reg_op + 1].regs == 0);
2854 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2855 i.types[first_reg_op + 1] = i.types[first_reg_op];
2856 i.reg_operands = 2;
2857 }
2858
2859 if (i.tm.opcode_modifier & ShortForm)
2860 {
2861 /* The register or float register operand is in operand 0 or 1. */
2862 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2863 /* Register goes in low 3 bits of opcode. */
2864 i.tm.base_opcode |= i.op[op].regs->reg_num;
2865 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2866 i.rex |= REX_EXTZ;
2867 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2868 {
2869 /* Warn about some common errors, but press on regardless.
2870 The first case can be generated by gcc (<= 2.8.1). */
2871 if (i.operands == 2)
2872 {
2873 /* Reversed arguments on faddp, fsubp, etc. */
2874 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2875 i.op[1].regs->reg_name,
2876 i.op[0].regs->reg_name);
2877 }
2878 else
2879 {
2880 /* Extraneous `l' suffix on fp insn. */
2881 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2882 i.op[0].regs->reg_name);
2883 }
2884 }
2885 }
2886 else if (i.tm.opcode_modifier & Modrm)
2887 {
2888 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 2889 must be put into the modrm byte). Now, we make the modrm and
2890 index base bytes based on all the info we've collected. */
29b0f896
AM		 2891
2892 default_seg = build_modrm_byte ();
2893 }
2894 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2895 {
2896 if (i.tm.base_opcode == POP_SEG_SHORT
2897 && i.op[0].regs->reg_num == 1)
2898 {
2899 as_bad (_("you can't `pop %%cs'"));
2900 return 0;
2901 }
2902 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2903 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2904 i.rex |= REX_EXTZ;
2905 }
2906 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2907 {
2908 default_seg = &ds;
2909 }
2910 else if ((i.tm.opcode_modifier & IsString) != 0)
2911 {
2912 /* For the string instructions that allow a segment override
2913 on one of their operands, the default segment is ds. */
2914 default_seg = &ds;
2915 }
2916
30123838
JB		 2917 if ((i.tm.base_opcode == 0x8d /* lea */
2918 || (i.tm.cpu_flags & CpuSVME))
2919 && i.seg[0] && !quiet_warnings)
2920 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 2921
2922 /* If a segment was explicitly specified, and the specified segment
2923 is not the default, use an opcode prefix to select it. If we
2924 never figured out what the default segment is, then default_seg
2925 will be zero at this point, and the specified segment prefix will
2926 always be used. */
29b0f896
AM		 2927 if ((i.seg[0]) && (i.seg[0] != default_seg))
2928 {
2929 if (!add_prefix (i.seg[0]->seg_prefix))
2930 return 0;
2931 }
2932 return 1;
2933}
2934
2935static const seg_entry *
2936build_modrm_byte ()
2937{
2938 const seg_entry *default_seg = 0;
2939
2940 /* i.reg_operands MUST be the number of real register operands;
2941 implicit registers do not count. */
2942 if (i.reg_operands == 2)
2943 {
2944 unsigned int source, dest;
2945 source = ((i.types[0]
2946 & (Reg | RegMMX | RegXMM
2947 | SReg2 | SReg3
2948 | Control | Debug | Test))
2949 ? 0 : 1);
2950 dest = source + 1;
2951
2952 i.rm.mode = 3;
2953 /* One of the register operands will be encoded in the i.tm.reg
2954 field, the other in the combined i.tm.mode and i.tm.regmem
2955 fields. If no form of this instruction supports a memory
2956 destination operand, then we assume the source operand may
2957 sometimes be a memory operand and so we need to store the
2958 destination in the i.rm.reg field. */
2959 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2960 {
2961 i.rm.reg = i.op[dest].regs->reg_num;
2962 i.rm.regmem = i.op[source].regs->reg_num;
2963 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2964 i.rex |= REX_EXTX;
2965 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2966 i.rex |= REX_EXTZ;
2967 }
2968 else
2969 {
2970 i.rm.reg = i.op[source].regs->reg_num;
2971 i.rm.regmem = i.op[dest].regs->reg_num;
2972 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2973 i.rex |= REX_EXTZ;
2974 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2975 i.rex |= REX_EXTX;
2976 }
c4a530c5
JB		 2977 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
2978 {
2979 if (!((i.types[0] | i.types[1]) & Control))
2980 abort ();
2981 i.rex &= ~(REX_EXTX | REX_EXTZ);
2982 add_prefix (LOCK_PREFIX_OPCODE);
2983 }
29b0f896
AM		 2984 }
2985 else
2986 { /* If it's not 2 reg operands... */
2987 if (i.mem_operands)
2988 {
2989 unsigned int fake_zero_displacement = 0;
2990 unsigned int op = ((i.types[0] & AnyMem)
2991 ? 0
2992 : (i.types[1] & AnyMem) ? 1 : 2);
2993
2994 default_seg = &ds;
2995
2996 if (i.base_reg == 0)
2997 {
2998 i.rm.mode = 0;
2999 if (!i.disp_operands)
3000 fake_zero_displacement = 1;
3001 if (i.index_reg == 0)
3002 {
3003 /* Operand is just <disp> */
20f0a1fc 3004 if (flag_code == CODE_64BIT)
29b0f896
AM		 3005 {
3006 /* 64bit mode overwrites the 32bit absolute
3007 addressing by RIP relative addressing and
3008 absolute addressing is encoded by one of the
3009 redundant SIB forms. */
3010 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3011 i.sib.base = NO_BASE_REGISTER;
3012 i.sib.index = NO_INDEX_REGISTER;
20f0a1fc
NC		 3013 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
3014 }
3015 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3016 {
3017 i.rm.regmem = NO_BASE_REGISTER_16;
3018 i.types[op] = Disp16;
3019 }
3020 else
3021 {
3022 i.rm.regmem = NO_BASE_REGISTER;
3023 i.types[op] = Disp32;
29b0f896
AM		 3024 }
3025 }
3026 else /* !i.base_reg && i.index_reg */
3027 {
3028 i.sib.index = i.index_reg->reg_num;
3029 i.sib.base = NO_BASE_REGISTER;
3030 i.sib.scale = i.log2_scale_factor;
3031 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3032 i.types[op] &= ~Disp;
3033 if (flag_code != CODE_64BIT)
3034 i.types[op] |= Disp32; /* Must be 32 bit */
3035 else
3036 i.types[op] |= Disp32S;
3037 if ((i.index_reg->reg_flags & RegRex) != 0)
3038 i.rex |= REX_EXTY;
3039 }
3040 }
3041 /* RIP addressing for 64bit mode. */
3042 else if (i.base_reg->reg_type == BaseIndex)
3043 {
3044 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3045 i.types[op] &= ~ Disp;
29b0f896
AM		 3046 i.types[op] |= Disp32S;
3047 i.flags[op] = Operand_PCrel;
20f0a1fc
NC		 3048 if (! i.disp_operands)
3049 fake_zero_displacement = 1;
29b0f896
AM		 3050 }
3051 else if (i.base_reg->reg_type & Reg16)
3052 {
3053 switch (i.base_reg->reg_num)
3054 {
3055 case 3: /* (%bx) */
3056 if (i.index_reg == 0)
3057 i.rm.regmem = 7;
3058 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3059 i.rm.regmem = i.index_reg->reg_num - 6;
3060 break;
3061 case 5: /* (%bp) */
3062 default_seg = &ss;
3063 if (i.index_reg == 0)
3064 {
3065 i.rm.regmem = 6;
3066 if ((i.types[op] & Disp) == 0)
3067 {
3068 /* fake (%bp) into 0(%bp) */
3069 i.types[op] |= Disp8;
252b5132 3070 fake_zero_displacement = 1;
29b0f896
AM		 3071 }
3072 }
3073 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3074 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3075 break;
3076 default: /* (%si) -> 4 or (%di) -> 5 */
3077 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3078 }
3079 i.rm.mode = mode_from_disp_size (i.types[op]);
3080 }
3081 else /* i.base_reg and 32/64 bit mode */
3082 {
3083 if (flag_code == CODE_64BIT
3084 && (i.types[op] & Disp))
20f0a1fc
NC		 3085 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3086
29b0f896
AM		 3087 i.rm.regmem = i.base_reg->reg_num;
3088 if ((i.base_reg->reg_flags & RegRex) != 0)
3089 i.rex |= REX_EXTZ;
3090 i.sib.base = i.base_reg->reg_num;
3091 /* x86-64 ignores REX prefix bit here to avoid decoder
3092 complications. */
3093 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3094 {
3095 default_seg = &ss;
3096 if (i.disp_operands == 0)
3097 {
3098 fake_zero_displacement = 1;
3099 i.types[op] |= Disp8;
3100 }
3101 }
3102 else if (i.base_reg->reg_num == ESP_REG_NUM)
3103 {
3104 default_seg = &ss;
3105 }
3106 i.sib.scale = i.log2_scale_factor;
3107 if (i.index_reg == 0)
3108 {
3109 /* <disp>(%esp) becomes two byte modrm with no index
3110 register. We've already stored the code for esp
3111 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3112 Any base register besides %esp will not use the
3113 extra modrm byte. */
3114 i.sib.index = NO_INDEX_REGISTER;
3115#if !SCALE1_WHEN_NO_INDEX
3116 /* Another case where we force the second modrm byte. */
3117 if (i.log2_scale_factor)
3118 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3119#endif
29b0f896
AM		 3120 }
3121 else
3122 {
3123 i.sib.index = i.index_reg->reg_num;
3124 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3125 if ((i.index_reg->reg_flags & RegRex) != 0)
3126 i.rex |= REX_EXTY;
3127 }
3128 i.rm.mode = mode_from_disp_size (i.types[op]);
3129 }
252b5132 3130
29b0f896
AM		 3131 if (fake_zero_displacement)
3132 {
3133 /* Fakes a zero displacement assuming that i.types[op]
3134 holds the correct displacement size. */
3135 expressionS *exp;
3136
3137 assert (i.op[op].disps == 0);
3138 exp = &disp_expressions[i.disp_operands++];
3139 i.op[op].disps = exp;
3140 exp->X_op = O_constant;
3141 exp->X_add_number = 0;
3142 exp->X_add_symbol = (symbolS *) 0;
3143 exp->X_op_symbol = (symbolS *) 0;
3144 }
3145 }
252b5132 3146
29b0f896
AM		 3147 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3148 (if any) based on i.tm.extension_opcode. Again, we must be
3149 careful to make sure that segment/control/debug/test/MMX
3150 registers are coded into the i.rm.reg field. */
3151 if (i.reg_operands)
3152 {
3153 unsigned int op =
3154 ((i.types[0]
3155 & (Reg | RegMMX | RegXMM
3156 | SReg2 | SReg3
3157 | Control | Debug | Test))
3158 ? 0
3159 : ((i.types[1]
3160 & (Reg | RegMMX | RegXMM
3161 | SReg2 | SReg3
3162 | Control | Debug | Test))
3163 ? 1
3164 : 2));
3165 /* If there is an extension opcode to put here, the register
3166 number must be put into the regmem field. */
3167 if (i.tm.extension_opcode != None)
3168 {
3169 i.rm.regmem = i.op[op].regs->reg_num;
3170 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3171 i.rex |= REX_EXTZ;
3172 }
3173 else
3174 {
3175 i.rm.reg = i.op[op].regs->reg_num;
3176 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3177 i.rex |= REX_EXTX;
3178 }
252b5132 3179
29b0f896
AM		 3180 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3181 must set it to 3 to indicate this is a register operand
3182 in the regmem field. */
3183 if (!i.mem_operands)
3184 i.rm.mode = 3;
3185 }
252b5132 3186
29b0f896
AM		 3187 /* Fill in i.rm.reg field with extension opcode (if any). */
3188 if (i.tm.extension_opcode != None)
3189 i.rm.reg = i.tm.extension_opcode;
3190 }
3191 return default_seg;
3192}
252b5132 3193
29b0f896
AM		 3194static void
3195output_branch ()
3196{
3197 char *p;
3198 int code16;
3199 int prefix;
3200 relax_substateT subtype;
3201 symbolS *sym;
3202 offsetT off;
3203
3204 code16 = 0;
3205 if (flag_code == CODE_16BIT)
3206 code16 = CODE16;
3207
3208 prefix = 0;
3209 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3210 {
29b0f896
AM		 3211 prefix = 1;
3212 i.prefixes -= 1;
3213 code16 ^= CODE16;
252b5132 3214 }
29b0f896
AM		 3215 /* Pentium4 branch hints. */
3216 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3217 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3218 {
29b0f896
AM		 3219 prefix++;
3220 i.prefixes--;
3221 }
3222 if (i.prefix[REX_PREFIX] != 0)
3223 {
3224 prefix++;
3225 i.prefixes--;
2f66722d
AM		 3226 }
3227
29b0f896
AM		 3228 if (i.prefixes != 0 && !intel_syntax)
3229 as_warn (_("skipping prefixes on this instruction"));
3230
3231 /* It's always a symbol; End frag & setup for relax.
3232 Make sure there is enough room in this frag for the largest
3233 instruction we may generate in md_convert_frag. This is 2
3234 bytes for the opcode and room for the prefix and largest
3235 displacement. */
3236 frag_grow (prefix + 2 + 4);
3237 /* Prefix and 1 opcode byte go in fr_fix. */
3238 p = frag_more (prefix + 1);
3239 if (i.prefix[DATA_PREFIX] != 0)
3240 *p++ = DATA_PREFIX_OPCODE;
3241 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3242 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3243 *p++ = i.prefix[SEG_PREFIX];
3244 if (i.prefix[REX_PREFIX] != 0)
3245 *p++ = i.prefix[REX_PREFIX];
3246 *p = i.tm.base_opcode;
3247
3248 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3249 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3250 else if ((cpu_arch_flags & Cpu386) != 0)
3251 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3252 else
3253 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3254 subtype |= code16;
3e73aa7c 3255
29b0f896
AM		 3256 sym = i.op[0].disps->X_add_symbol;
3257 off = i.op[0].disps->X_add_number;
3e73aa7c 3258
29b0f896
AM		 3259 if (i.op[0].disps->X_op != O_constant
3260 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3261 {
29b0f896
AM		 3262 /* Handle complex expressions. */
3263 sym = make_expr_symbol (i.op[0].disps);
3264 off = 0;
3265 }
3e73aa7c 3266
29b0f896
AM		 3267 /* 1 possible extra opcode + 4 byte displacement go in var part.
3268 Pass reloc in fr_var. */
3269 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3270}
3e73aa7c 3271
29b0f896
AM		 3272static void
3273output_jump ()
3274{
3275 char *p;
3276 int size;
3e02c1cc 3277 fixS *fixP;
29b0f896
AM		 3278
3279 if (i.tm.opcode_modifier & JumpByte)
3280 {
3281 /* This is a loop or jecxz type instruction. */
3282 size = 1;
3283 if (i.prefix[ADDR_PREFIX] != 0)
3284 {
3285 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3286 i.prefixes -= 1;
3287 }
3288 /* Pentium4 branch hints. */
3289 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3290 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3291 {
3292 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3293 i.prefixes--;
3e73aa7c
JH		 3294 }
3295 }
29b0f896
AM		 3296 else
3297 {
3298 int code16;
3e73aa7c 3299
29b0f896
AM		 3300 code16 = 0;
3301 if (flag_code == CODE_16BIT)
3302 code16 = CODE16;
3e73aa7c 3303
29b0f896
AM		 3304 if (i.prefix[DATA_PREFIX] != 0)
3305 {
3306 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3307 i.prefixes -= 1;
3308 code16 ^= CODE16;
3309 }
252b5132 3310
29b0f896
AM		 3311 size = 4;
3312 if (code16)
3313 size = 2;
3314 }
9fcc94b6 3315
29b0f896
AM		 3316 if (i.prefix[REX_PREFIX] != 0)
3317 {
3318 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3319 i.prefixes -= 1;
3320 }
252b5132 3321
29b0f896
AM		 3322 if (i.prefixes != 0 && !intel_syntax)
3323 as_warn (_("skipping prefixes on this instruction"));
e0890092 3324
29b0f896
AM		 3325 p = frag_more (1 + size);
3326 *p++ = i.tm.base_opcode;
e0890092 3327
3e02c1cc
AM		 3328 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3329 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3330
3331 /* All jumps handled here are signed, but don't use a signed limit
3332 check for 32 and 16 bit jumps as we want to allow wrap around at
3333 4G and 64k respectively. */
3334 if (size == 1)
3335 fixP->fx_signed = 1;
29b0f896 3336}
e0890092 3337
29b0f896
AM		 3338static void
3339output_interseg_jump ()
3340{
3341 char *p;
3342 int size;
3343 int prefix;
3344 int code16;
252b5132 3345
29b0f896
AM		 3346 code16 = 0;
3347 if (flag_code == CODE_16BIT)
3348 code16 = CODE16;
a217f122 3349
29b0f896
AM		 3350 prefix = 0;
3351 if (i.prefix[DATA_PREFIX] != 0)
3352 {
3353 prefix = 1;
3354 i.prefixes -= 1;
3355 code16 ^= CODE16;
3356 }
3357 if (i.prefix[REX_PREFIX] != 0)
3358 {
3359 prefix++;
3360 i.prefixes -= 1;
3361 }
252b5132 3362
29b0f896
AM		 3363 size = 4;
3364 if (code16)
3365 size = 2;
252b5132 3366
29b0f896
AM		 3367 if (i.prefixes != 0 && !intel_syntax)
3368 as_warn (_("skipping prefixes on this instruction"));
252b5132 3369
29b0f896
AM		 3370 /* 1 opcode; 2 segment; offset */
3371 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3372
29b0f896
AM		 3373 if (i.prefix[DATA_PREFIX] != 0)
3374 *p++ = DATA_PREFIX_OPCODE;
252b5132 3375
29b0f896
AM		 3376 if (i.prefix[REX_PREFIX] != 0)
3377 *p++ = i.prefix[REX_PREFIX];
252b5132 3378
29b0f896
AM		 3379 *p++ = i.tm.base_opcode;
3380 if (i.op[1].imms->X_op == O_constant)
3381 {
3382 offsetT n = i.op[1].imms->X_add_number;
252b5132 3383
29b0f896
AM		 3384 if (size == 2
3385 && !fits_in_unsigned_word (n)
3386 && !fits_in_signed_word (n))
3387 {
3388 as_bad (_("16-bit jump out of range"));
3389 return;
3390 }
3391 md_number_to_chars (p, n, size);
3392 }
3393 else
3394 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3395 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3396 if (i.op[0].imms->X_op != O_constant)
3397 as_bad (_("can't handle non absolute segment in `%s'"),
3398 i.tm.name);
3399 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3400}
a217f122 3401
29b0f896
AM		 3402static void
3403output_insn ()
3404{
2bbd9c25
JJ		 3405 fragS *insn_start_frag;
3406 offsetT insn_start_off;
3407
29b0f896
AM		 3408 /* Tie dwarf2 debug info to the address at the start of the insn.
3409 We can't do this after the insn has been output as the current
3410 frag may have been closed off. eg. by frag_var. */
3411 dwarf2_emit_insn (0);
3412
2bbd9c25
JJ		 3413 insn_start_frag = frag_now;
3414 insn_start_off = frag_now_fix ();
3415
29b0f896
AM		 3416 /* Output jumps. */
3417 if (i.tm.opcode_modifier & Jump)
3418 output_branch ();
3419 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3420 output_jump ();
3421 else if (i.tm.opcode_modifier & JumpInterSegment)
3422 output_interseg_jump ();
3423 else
3424 {
3425 /* Output normal instructions here. */
3426 char *p;
3427 unsigned char *q;
252b5132 3428
bc4bd9ab
MK		 3429 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3430 more higher byte to specify a prefix the instruction
3431 requires. */
3432 if ((i.tm.base_opcode & 0xff0000) != 0)
3433 {
3434 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3435 {
3436 unsigned int prefix;
3437 prefix = (i.tm.base_opcode >> 16) & 0xff;
3438
3439 if (prefix != REPE_PREFIX_OPCODE
3440 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3441 add_prefix (prefix);
3442 }
3443 else
3444 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
0f10071e 3445 }
252b5132 3446
29b0f896
AM		 3447 /* The prefix bytes. */
3448 for (q = i.prefix;
3449 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3450 q++)
3451 {
3452 if (*q)
3453 {
3454 p = frag_more (1);
3455 md_number_to_chars (p, (valueT) *q, 1);
3456 }
3457 }
252b5132 3458
29b0f896
AM		 3459 /* Now the opcode; be careful about word order here! */
3460 if (fits_in_unsigned_byte (i.tm.base_opcode))
3461 {
3462 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3463 }
3464 else
3465 {
bc4bd9ab 3466 p = frag_more (2);
0f10071e 3467
29b0f896
AM		 3468 /* Put out high byte first: can't use md_number_to_chars! */
3469 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3470 *p = i.tm.base_opcode & 0xff;
3471 }
3e73aa7c 3472
29b0f896
AM		 3473 /* Now the modrm byte and sib byte (if present). */
3474 if (i.tm.opcode_modifier & Modrm)
3475 {
3476 p = frag_more (1);
3477 md_number_to_chars (p,
3478 (valueT) (i.rm.regmem << 0
3479 | i.rm.reg << 3
3480 | i.rm.mode << 6),
3481 1);
3482 /* If i.rm.regmem == ESP (4)
3483 && i.rm.mode != (Register mode)
3484 && not 16 bit
3485 ==> need second modrm byte. */
3486 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3487 && i.rm.mode != 3
3488 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3489 {
3490 p = frag_more (1);
3491 md_number_to_chars (p,
3492 (valueT) (i.sib.base << 0
3493 | i.sib.index << 3
3494 | i.sib.scale << 6),
3495 1);
3496 }
3497 }
3e73aa7c 3498
29b0f896 3499 if (i.disp_operands)
2bbd9c25 3500 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3501
29b0f896 3502 if (i.imm_operands)
2bbd9c25 3503 output_imm (insn_start_frag, insn_start_off);
29b0f896 3504 }
252b5132 3505
29b0f896
AM		 3506#ifdef DEBUG386
3507 if (flag_debug)
3508 {
3509 pi (line, &i);
3510 }
3511#endif /* DEBUG386 */
3512}
252b5132 3513
29b0f896 3514static void
2bbd9c25
JJ		 3515output_disp (insn_start_frag, insn_start_off)
3516 fragS *insn_start_frag;
3517 offsetT insn_start_off;
29b0f896
AM		 3518{
3519 char *p;
3520 unsigned int n;
252b5132 3521
29b0f896
AM		 3522 for (n = 0; n < i.operands; n++)
3523 {
3524 if (i.types[n] & Disp)
3525 {
3526 if (i.op[n].disps->X_op == O_constant)
3527 {
3528 int size;
3529 offsetT val;
252b5132 3530
29b0f896
AM		 3531 size = 4;
3532 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3533 {
3534 size = 2;
3535 if (i.types[n] & Disp8)
3536 size = 1;
3537 if (i.types[n] & Disp64)
3538 size = 8;
3539 }
3540 val = offset_in_range (i.op[n].disps->X_add_number,
3541 size);
3542 p = frag_more (size);
3543 md_number_to_chars (p, val, size);
3544 }
3545 else
3546 {
f86103b7 3547 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3548 int size = 4;
3549 int sign = 0;
3550 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3551
3552 /* The PC relative address is computed relative
3553 to the instruction boundary, so in case immediate
3554 fields follows, we need to adjust the value. */
3555 if (pcrel && i.imm_operands)
3556 {
3557 int imm_size = 4;
3558 unsigned int n1;
252b5132 3559
29b0f896
AM		 3560 for (n1 = 0; n1 < i.operands; n1++)
3561 if (i.types[n1] & Imm)
252b5132 3562 {
29b0f896 3563 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3564 {
29b0f896
AM		 3565 imm_size = 2;
3566 if (i.types[n1] & (Imm8 | Imm8S))
3567 imm_size = 1;
3568 if (i.types[n1] & Imm64)
3569 imm_size = 8;
252b5132 3570 }
29b0f896 3571 break;
252b5132 3572 }
29b0f896
AM		 3573 /* We should find the immediate. */
3574 if (n1 == i.operands)
3575 abort ();
3576 i.op[n].disps->X_add_number -= imm_size;
3577 }
520dc8e8 3578
29b0f896
AM		 3579 if (i.types[n] & Disp32S)
3580 sign = 1;
3e73aa7c 3581
29b0f896
AM		 3582 if (i.types[n] & (Disp16 | Disp64))
3583 {
3584 size = 2;
3585 if (i.types[n] & Disp64)
3586 size = 8;
3587 }
520dc8e8 3588
29b0f896 3589 p = frag_more (size);
2bbd9c25 3590 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 3591 if (GOT_symbol
2bbd9c25 3592 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113
JB		 3593 && (((reloc_type == BFD_RELOC_32
3594 || reloc_type == BFD_RELOC_X86_64_32S)
3595 && (i.op[n].disps->X_op == O_symbol
3596 || (i.op[n].disps->X_op == O_add
3597 && ((symbol_get_value_expression
3598 (i.op[n].disps->X_op_symbol)->X_op)
3599 == O_subtract))))
3600 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 3601 {
3602 offsetT add;
3603
3604 if (insn_start_frag == frag_now)
3605 add = (p - frag_now->fr_literal) - insn_start_off;
3606 else
3607 {
3608 fragS *fr;
3609
3610 add = insn_start_frag->fr_fix - insn_start_off;
3611 for (fr = insn_start_frag->fr_next;
3612 fr && fr != frag_now; fr = fr->fr_next)
3613 add += fr->fr_fix;
3614 add += p - frag_now->fr_literal;
3615 }
3616
4fa24527 3617 if (!object_64bit)
d6ab8113
JB		 3618 reloc_type = BFD_RELOC_386_GOTPC;
3619 else
3620 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25
JJ		 3621 i.op[n].disps->X_add_number += add;
3622 }
062cd5e7 3623 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 3624 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 3625 }
3626 }
3627 }
3628}
252b5132 3629
29b0f896 3630static void
2bbd9c25
JJ		 3631output_imm (insn_start_frag, insn_start_off)
3632 fragS *insn_start_frag;
3633 offsetT insn_start_off;
29b0f896
AM		 3634{
3635 char *p;
3636 unsigned int n;
252b5132 3637
29b0f896
AM		 3638 for (n = 0; n < i.operands; n++)
3639 {
3640 if (i.types[n] & Imm)
3641 {
3642 if (i.op[n].imms->X_op == O_constant)
3643 {
3644 int size;
3645 offsetT val;
b4cac588 3646
29b0f896
AM		 3647 size = 4;
3648 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3649 {
3650 size = 2;
3651 if (i.types[n] & (Imm8 | Imm8S))
3652 size = 1;
3653 else if (i.types[n] & Imm64)
3654 size = 8;
3655 }
3656 val = offset_in_range (i.op[n].imms->X_add_number,
3657 size);
3658 p = frag_more (size);
3659 md_number_to_chars (p, val, size);
3660 }
3661 else
3662 {
3663 /* Not absolute_section.
3664 Need a 32-bit fixup (don't support 8bit
3665 non-absolute imms). Try to support other
3666 sizes ... */
f86103b7 3667 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3668 int size = 4;
3669 int sign = 0;
3670
3671 if ((i.types[n] & (Imm32S))
a7d61044
JB		 3672 && (i.suffix == QWORD_MNEM_SUFFIX
3673 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 3674 sign = 1;
3675 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3676 {
3677 size = 2;
3678 if (i.types[n] & (Imm8 | Imm8S))
3679 size = 1;
3680 if (i.types[n] & Imm64)
3681 size = 8;
3682 }
520dc8e8 3683
29b0f896
AM		 3684 p = frag_more (size);
3685 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 3686
2bbd9c25
JJ		 3687 /* This is tough to explain. We end up with this one if we
3688 * have operands that look like
3689 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3690 * obtain the absolute address of the GOT, and it is strongly
3691 * preferable from a performance point of view to avoid using
3692 * a runtime relocation for this. The actual sequence of
3693 * instructions often look something like:
3694 *
3695 * call .L66
3696 * .L66:
3697 * popl %ebx
3698 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3699 *
3700 * The call and pop essentially return the absolute address
3701 * of the label .L66 and store it in %ebx. The linker itself
3702 * will ultimately change the first operand of the addl so
3703 * that %ebx points to the GOT, but to keep things simple, the
3704 * .o file must have this operand set so that it generates not
3705 * the absolute address of .L66, but the absolute address of
3706 * itself. This allows the linker itself simply treat a GOTPC
3707 * relocation as asking for a pcrel offset to the GOT to be
3708 * added in, and the addend of the relocation is stored in the
3709 * operand field for the instruction itself.
3710 *
3711 * Our job here is to fix the operand so that it would add
3712 * the correct offset so that %ebx would point to itself. The
3713 * thing that is tricky is that .-.L66 will point to the
3714 * beginning of the instruction, so we need to further modify
3715 * the operand so that it will point to itself. There are
3716 * other cases where you have something like:
3717 *
3718 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3719 *
3720 * and here no correction would be required. Internally in
3721 * the assembler we treat operands of this form as not being
3722 * pcrel since the '.' is explicitly mentioned, and I wonder
3723 * whether it would simplify matters to do it this way. Who
3724 * knows. In earlier versions of the PIC patches, the
3725 * pcrel_adjust field was used to store the correction, but
3726 * since the expression is not pcrel, I felt it would be
3727 * confusing to do it this way. */
3728
d6ab8113
JB		 3729 if ((reloc_type == BFD_RELOC_32
3730 || reloc_type == BFD_RELOC_X86_64_32S)
29b0f896
AM		 3731 && GOT_symbol
3732 && GOT_symbol == i.op[n].imms->X_add_symbol
3733 && (i.op[n].imms->X_op == O_symbol
3734 || (i.op[n].imms->X_op == O_add
3735 && ((symbol_get_value_expression
3736 (i.op[n].imms->X_op_symbol)->X_op)
3737 == O_subtract))))
3738 {
2bbd9c25
JJ		 3739 offsetT add;
3740
3741 if (insn_start_frag == frag_now)
3742 add = (p - frag_now->fr_literal) - insn_start_off;
3743 else
3744 {
3745 fragS *fr;
3746
3747 add = insn_start_frag->fr_fix - insn_start_off;
3748 for (fr = insn_start_frag->fr_next;
3749 fr && fr != frag_now; fr = fr->fr_next)
3750 add += fr->fr_fix;
3751 add += p - frag_now->fr_literal;
3752 }
3753
4fa24527 3754 if (!object_64bit)
d6ab8113
JB		 3755 reloc_type = BFD_RELOC_386_GOTPC;
3756 else
3757 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 3758 i.op[n].imms->X_add_number += add;
29b0f896 3759 }
29b0f896
AM		 3760 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3761 i.op[n].imms, 0, reloc_type);
3762 }
3763 }
3764 }
252b5132
RH		 3765}
3766\f
718ddfc0
JB		 3767#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
3768# define lex_got(reloc, adjust, types) NULL
3769#else
f3c180ae
AM		 3770/* Parse operands of the form
3771 <symbol>@GOTOFF+<nnn>
3772 and similar .plt or .got references.
3773
3774 If we find one, set up the correct relocation in RELOC and copy the
3775 input string, minus the `@GOTOFF' into a malloc'd buffer for
3776 parsing by the calling routine. Return this buffer, and if ADJUST
3777 is non-null set it to the length of the string we removed from the
3778 input line. Otherwise return NULL. */
3779static char *
3956db08
JB		 3780lex_got (enum bfd_reloc_code_real *reloc,
3781 int *adjust,
3782 unsigned int *types)
f3c180ae 3783{
f3c180ae
AM		 3784 static const struct {
3785 const char *str;
4fa24527 3786 const enum bfd_reloc_code_real rel[2];
3956db08 3787 const unsigned int types64;
f3c180ae 3788 } gotrel[] = {
4fa24527
JB		 3789 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
3790 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
3791 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
3792 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
3793 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
3794 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
3795 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
3796 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3797 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
3798 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3799 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
3800 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
3801 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 3802 };
3803 char *cp;
3804 unsigned int j;
3805
718ddfc0
JB		 3806 if (!IS_ELF)
3807 return NULL;
3808
f3c180ae
AM		 3809 for (cp = input_line_pointer; *cp != '@'; cp++)
3810 if (is_end_of_line[(unsigned char) *cp])
3811 return NULL;
3812
3813 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3814 {
3815 int len;
3816
3817 len = strlen (gotrel[j].str);
28f81592 3818 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 3819 {
4fa24527 3820 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 3821 {
28f81592
AM		 3822 int first, second;
3823 char *tmpbuf, *past_reloc;
f3c180ae 3824
4fa24527 3825 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 3826 if (adjust)
3827 *adjust = len;
f3c180ae 3828
3956db08
JB		 3829 if (types)
3830 {
3831 if (flag_code != CODE_64BIT)
3832 *types = Imm32|Disp32;
3833 else
3834 *types = gotrel[j].types64;
3835 }
3836
f3c180ae
AM		 3837 if (GOT_symbol == NULL)
3838 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3839
3840 /* Replace the relocation token with ' ', so that
3841 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3842
3843 /* The length of the first part of our input line. */
f3c180ae 3844 first = cp - input_line_pointer;
28f81592
AM		 3845
3846 /* The second part goes from after the reloc token until
3847 (and including) an end_of_line char. Don't use strlen
3848 here as the end_of_line char may not be a NUL. */
3849 past_reloc = cp + 1 + len;
3850 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3851 ;
3852 second = cp - past_reloc;
3853
3854 /* Allocate and copy string. The trailing NUL shouldn't
3855 be necessary, but be safe. */
3856 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3857 memcpy (tmpbuf, input_line_pointer, first);
3858 tmpbuf[first] = ' ';
28f81592
AM		 3859 memcpy (tmpbuf + first + 1, past_reloc, second);
3860 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3861 return tmpbuf;
3862 }
3863
4fa24527
JB		 3864 as_bad (_("@%s reloc is not supported with %d-bit output format"),
3865 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 3866 return NULL;
3867 }
3868 }
3869
3870 /* Might be a symbol version string. Don't as_bad here. */
3871 return NULL;
3872}
3873
3874/* x86_cons_fix_new is called via the expression parsing code when a
3875 reloc is needed. We use this hook to get the correct .got reloc. */
f86103b7 3876static enum bfd_reloc_code_real got_reloc = NO_RELOC;
f3c180ae
AM		 3877
3878void
3879x86_cons_fix_new (frag, off, len, exp)
3880 fragS *frag;
3881 unsigned int off;
3882 unsigned int len;
3883 expressionS *exp;
3884{
3956db08 3885 enum bfd_reloc_code_real r = reloc (len, 0, -1, got_reloc);
f3c180ae
AM		 3886 got_reloc = NO_RELOC;
3887 fix_new_exp (frag, off, len, exp, 0, r);
3888}
3889
3890void
3891x86_cons (exp, size)
3892 expressionS *exp;
3893 int size;
3894{
4fa24527 3895 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 3896 {
3897 /* Handle @GOTOFF and the like in an expression. */
3898 char *save;
3899 char *gotfree_input_line;
3900 int adjust;
3901
3902 save = input_line_pointer;
3956db08 3903 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 3904 if (gotfree_input_line)
3905 input_line_pointer = gotfree_input_line;
3906
3907 expression (exp);
3908
3909 if (gotfree_input_line)
3910 {
3911 /* expression () has merrily parsed up to the end of line,
3912 or a comma - in the wrong buffer. Transfer how far
3913 input_line_pointer has moved to the right buffer. */
3914 input_line_pointer = (save
3915 + (input_line_pointer - gotfree_input_line)
3916 + adjust);
3917 free (gotfree_input_line);
3918 }
3919 }
3920 else
3921 expression (exp);
3922}
3923#endif
3924
6482c264
NC		 3925#ifdef TE_PE
3926
6482c264
NC		 3927void
3928x86_pe_cons_fix_new (frag, off, len, exp)
3929 fragS *frag;
3930 unsigned int off;
3931 unsigned int len;
3932 expressionS *exp;
3933{
3956db08 3934 enum bfd_reloc_code_real r = reloc (len, 0, -1, NO_RELOC);
6482c264
NC		 3935
3936 if (exp->X_op == O_secrel)
3937 {
3938 exp->X_op = O_symbol;
3939 r = BFD_RELOC_32_SECREL;
3940 }
3941
3942 fix_new_exp (frag, off, len, exp, 0, r);
3943}
3944
3945static void
3946pe_directive_secrel (dummy)
3947 int dummy ATTRIBUTE_UNUSED;
3948{
3949 expressionS exp;
3950
3951 do
3952 {
3953 expression (&exp);
3954 if (exp.X_op == O_symbol)
3955 exp.X_op = O_secrel;
3956
3957 emit_expr (&exp, 4);
3958 }
3959 while (*input_line_pointer++ == ',');
3960
3961 input_line_pointer--;
3962 demand_empty_rest_of_line ();
3963}
3964
3965#endif
3966
252b5132
RH		 3967static int i386_immediate PARAMS ((char *));
3968
3969static int
3970i386_immediate (imm_start)
3971 char *imm_start;
3972{
3973 char *save_input_line_pointer;
f3c180ae 3974 char *gotfree_input_line;
252b5132 3975 segT exp_seg = 0;
47926f60 3976 expressionS *exp;
3956db08 3977 unsigned int types = ~0U;
252b5132
RH		 3978
3979 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3980 {
d0b47220 3981 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3982 return 0;
3983 }
3984
3985 exp = &im_expressions[i.imm_operands++];
520dc8e8 3986 i.op[this_operand].imms = exp;
252b5132
RH		 3987
3988 if (is_space_char (*imm_start))
3989 ++imm_start;
3990
3991 save_input_line_pointer = input_line_pointer;
3992 input_line_pointer = imm_start;
3993
3956db08 3994 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 3995 if (gotfree_input_line)
3996 input_line_pointer = gotfree_input_line;
252b5132
RH		 3997
3998 exp_seg = expression (exp);
3999
83183c0c 4000 SKIP_WHITESPACE ();
252b5132 4001 if (*input_line_pointer)
f3c180ae 4002 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4003
4004 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4005 if (gotfree_input_line)
4006 free (gotfree_input_line);
252b5132 4007
2daf4fd8 4008 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4009 {
47926f60 4010 /* Missing or bad expr becomes absolute 0. */
d0b47220 4011 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4012 imm_start);
252b5132
RH		 4013 exp->X_op = O_constant;
4014 exp->X_add_number = 0;
4015 exp->X_add_symbol = (symbolS *) 0;
4016 exp->X_op_symbol = (symbolS *) 0;
252b5132 4017 }
3e73aa7c 4018 else if (exp->X_op == O_constant)
252b5132 4019 {
47926f60 4020 /* Size it properly later. */
3e73aa7c
JH		 4021 i.types[this_operand] |= Imm64;
4022 /* If BFD64, sign extend val. */
4023 if (!use_rela_relocations)
4024 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4025 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4026 }
4c63da97 4027#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4028 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4029 && exp_seg != absolute_section
47926f60 4030 && exp_seg != text_section
24eab124
AM		 4031 && exp_seg != data_section
4032 && exp_seg != bss_section
4033 && exp_seg != undefined_section
f86103b7 4034 && !bfd_is_com_section (exp_seg))
252b5132 4035 {
d0b47220 4036 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4037 return 0;
4038 }
4039#endif
4040 else
4041 {
4042 /* This is an address. The size of the address will be
24eab124 4043 determined later, depending on destination register,
3e73aa7c
JH		 4044 suffix, or the default for the section. */
4045 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4046 i.types[this_operand] &= types;
252b5132
RH		 4047 }
4048
4049 return 1;
4050}
4051
551c1ca1 4052static char *i386_scale PARAMS ((char *));
252b5132 4053
551c1ca1 4054static char *
252b5132
RH		 4055i386_scale (scale)
4056 char *scale;
4057{
551c1ca1
AM		 4058 offsetT val;
4059 char *save = input_line_pointer;
252b5132 4060
551c1ca1
AM		 4061 input_line_pointer = scale;
4062 val = get_absolute_expression ();
4063
4064 switch (val)
252b5132 4065 {
551c1ca1 4066 case 1:
252b5132
RH		 4067 i.log2_scale_factor = 0;
4068 break;
551c1ca1 4069 case 2:
252b5132
RH		 4070 i.log2_scale_factor = 1;
4071 break;
551c1ca1 4072 case 4:
252b5132
RH		 4073 i.log2_scale_factor = 2;
4074 break;
551c1ca1 4075 case 8:
252b5132
RH		 4076 i.log2_scale_factor = 3;
4077 break;
4078 default:
a724f0f4
JB		 4079 {
4080 char sep = *input_line_pointer;
4081
4082 *input_line_pointer = '\0';
4083 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4084 scale);
4085 *input_line_pointer = sep;
4086 input_line_pointer = save;
4087 return NULL;
4088 }
252b5132 4089 }
29b0f896 4090 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4091 {
4092 as_warn (_("scale factor of %d without an index register"),
24eab124 4093 1 << i.log2_scale_factor);
252b5132
RH		 4094#if SCALE1_WHEN_NO_INDEX
4095 i.log2_scale_factor = 0;
4096#endif
4097 }
551c1ca1
AM		 4098 scale = input_line_pointer;
4099 input_line_pointer = save;
4100 return scale;
252b5132
RH		 4101}
4102
4103static int i386_displacement PARAMS ((char *, char *));
4104
4105static int
4106i386_displacement (disp_start, disp_end)
4107 char *disp_start;
4108 char *disp_end;
4109{
29b0f896 4110 expressionS *exp;
252b5132
RH		 4111 segT exp_seg = 0;
4112 char *save_input_line_pointer;
f3c180ae 4113 char *gotfree_input_line;
252b5132 4114 int bigdisp = Disp32;
3956db08 4115 unsigned int types = Disp;
252b5132 4116
3e73aa7c 4117 if (flag_code == CODE_64BIT)
7ecd2f8b 4118 {
29b0f896 4119 if (i.prefix[ADDR_PREFIX] == 0)
3956db08 4120 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b
JH		 4121 }
4122 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4123 bigdisp = Disp16;
252b5132
RH		 4124 i.types[this_operand] |= bigdisp;
4125
4126 exp = &disp_expressions[i.disp_operands];
520dc8e8 4127 i.op[this_operand].disps = exp;
252b5132
RH		 4128 i.disp_operands++;
4129 save_input_line_pointer = input_line_pointer;
4130 input_line_pointer = disp_start;
4131 END_STRING_AND_SAVE (disp_end);
4132
4133#ifndef GCC_ASM_O_HACK
4134#define GCC_ASM_O_HACK 0
4135#endif
4136#if GCC_ASM_O_HACK
4137 END_STRING_AND_SAVE (disp_end + 1);
4138 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4139 && displacement_string_end[-1] == '+')
252b5132
RH		 4140 {
4141 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4142 constraint within gcc asm statements.
4143 For instance:
4144
4145 #define _set_tssldt_desc(n,addr,limit,type) \
4146 __asm__ __volatile__ ( \
4147 "movw %w2,%0\n\t" \
4148 "movw %w1,2+%0\n\t" \
4149 "rorl $16,%1\n\t" \
4150 "movb %b1,4+%0\n\t" \
4151 "movb %4,5+%0\n\t" \
4152 "movb $0,6+%0\n\t" \
4153 "movb %h1,7+%0\n\t" \
4154 "rorl $16,%1" \
4155 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4156
4157 This works great except that the output assembler ends
4158 up looking a bit weird if it turns out that there is
4159 no offset. You end up producing code that looks like:
4160
4161 #APP
4162 movw $235,(%eax)
4163 movw %dx,2+(%eax)
4164 rorl $16,%edx
4165 movb %dl,4+(%eax)
4166 movb $137,5+(%eax)
4167 movb $0,6+(%eax)
4168 movb %dh,7+(%eax)
4169 rorl $16,%edx
4170 #NO_APP
4171
47926f60 4172 So here we provide the missing zero. */
24eab124
AM		 4173
4174 *displacement_string_end = '0';
252b5132
RH		 4175 }
4176#endif
3956db08 4177 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4178 if (gotfree_input_line)
4179 input_line_pointer = gotfree_input_line;
252b5132 4180
24eab124 4181 exp_seg = expression (exp);
252b5132 4182
636c26b0
AM		 4183 SKIP_WHITESPACE ();
4184 if (*input_line_pointer)
4185 as_bad (_("junk `%s' after expression"), input_line_pointer);
4186#if GCC_ASM_O_HACK
4187 RESTORE_END_STRING (disp_end + 1);
4188#endif
4189 RESTORE_END_STRING (disp_end);
4190 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4191 if (gotfree_input_line)
4192 free (gotfree_input_line);
636c26b0 4193
24eab124
AM		 4194 /* We do this to make sure that the section symbol is in
4195 the symbol table. We will ultimately change the relocation
47926f60 4196 to be relative to the beginning of the section. */
1ae12ab7 4197 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4198 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4199 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4200 {
636c26b0
AM		 4201 if (exp->X_op != O_symbol)
4202 {
4203 as_bad (_("bad expression used with @%s"),
4204 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4205 ? "GOTPCREL"
4206 : "GOTOFF"));
4207 return 0;
4208 }
4209
e5cb08ac 4210 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4211 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4212 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4213 exp->X_op = O_subtract;
4214 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4215 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4216 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4217 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4218 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4219 else
29b0f896 4220 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4221 }
252b5132 4222
2daf4fd8
AM		 4223 if (exp->X_op == O_absent || exp->X_op == O_big)
4224 {
47926f60 4225 /* Missing or bad expr becomes absolute 0. */
d0b47220 4226 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4227 disp_start);
4228 exp->X_op = O_constant;
4229 exp->X_add_number = 0;
4230 exp->X_add_symbol = (symbolS *) 0;
4231 exp->X_op_symbol = (symbolS *) 0;
4232 }
4233
4c63da97 4234#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4235 if (exp->X_op != O_constant
45288df1 4236 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4237 && exp_seg != absolute_section
45288df1
AM		 4238 && exp_seg != text_section
4239 && exp_seg != data_section
4240 && exp_seg != bss_section
31312f95 4241 && exp_seg != undefined_section
f86103b7 4242 && !bfd_is_com_section (exp_seg))
24eab124 4243 {
d0b47220 4244 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4245 return 0;
4246 }
252b5132 4247#endif
3956db08
JB		 4248
4249 if (!(i.types[this_operand] & ~Disp))
4250 i.types[this_operand] &= types;
4251
252b5132
RH		 4252 return 1;
4253}
4254
e5cb08ac 4255static int i386_index_check PARAMS ((const char *));
252b5132 4256
eecb386c 4257/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4258 Return 1 on success, 0 on a failure. */
4259
252b5132 4260static int
eecb386c
AM		 4261i386_index_check (operand_string)
4262 const char *operand_string;
252b5132 4263{
3e73aa7c 4264 int ok;
24eab124 4265#if INFER_ADDR_PREFIX
eecb386c
AM		 4266 int fudged = 0;
4267
24eab124
AM		 4268 tryprefix:
4269#endif
3e73aa7c 4270 ok = 1;
30123838
JB		 4271 if ((current_templates->start->cpu_flags & CpuSVME)
4272 && current_templates->end[-1].operand_types[0] == AnyMem)
4273 {
4274 /* Memory operands of SVME insns are special in that they only allow
4275 rAX as their memory address and ignore any segment override. */
4276 unsigned RegXX;
4277
4278 /* SKINIT is even more restrictive: it always requires EAX. */
4279 if (strcmp (current_templates->start->name, "skinit") == 0)
4280 RegXX = Reg32;
4281 else if (flag_code == CODE_64BIT)
4282 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4283 else
4284 RegXX = (flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4285 ? Reg16
4286 : Reg32;
4287 if (!i.base_reg
4288 || !(i.base_reg->reg_type & Acc)
4289 || !(i.base_reg->reg_type & RegXX)
4290 || i.index_reg
4291 || (i.types[0] & Disp))
4292 ok = 0;
4293 }
4294 else if (flag_code == CODE_64BIT)
20f0a1fc
NC		 4295 {
4296 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4297
4298 if ((i.base_reg
4299 && ((i.base_reg->reg_type & RegXX) == 0)
4300 && (i.base_reg->reg_type != BaseIndex
4301 || i.index_reg))
4302 || (i.index_reg
4303 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4304 != (RegXX | BaseIndex))))
4305 ok = 0;
3e73aa7c
JH		 4306 }
4307 else
4308 {
4309 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4310 {
4311 /* 16bit checks. */
4312 if ((i.base_reg
29b0f896
AM		 4313 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4314 != (Reg16 | BaseIndex)))
3e73aa7c 4315 || (i.index_reg
29b0f896
AM		 4316 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4317 != (Reg16 | BaseIndex))
4318 || !(i.base_reg
4319 && i.base_reg->reg_num < 6
4320 && i.index_reg->reg_num >= 6
4321 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4322 ok = 0;
4323 }
4324 else
e5cb08ac 4325 {
3e73aa7c
JH		 4326 /* 32bit checks. */
4327 if ((i.base_reg
4328 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4329 || (i.index_reg
29b0f896
AM		 4330 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4331 != (Reg32 | BaseIndex))))
e5cb08ac 4332 ok = 0;
3e73aa7c
JH		 4333 }
4334 }
4335 if (!ok)
24eab124
AM		 4336 {
4337#if INFER_ADDR_PREFIX
20f0a1fc 4338 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4339 {
4340 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4341 i.prefixes += 1;
b23bac36
AM		 4342 /* Change the size of any displacement too. At most one of
4343 Disp16 or Disp32 is set.
4344 FIXME. There doesn't seem to be any real need for separate
4345 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4346 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4347 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
29b0f896 4348 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4349 fudged = 1;
24eab124
AM		 4350 goto tryprefix;
4351 }
eecb386c
AM		 4352 if (fudged)
4353 as_bad (_("`%s' is not a valid base/index expression"),
4354 operand_string);
4355 else
c388dee8 4356#endif
eecb386c
AM		 4357 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4358 operand_string,
3e73aa7c 4359 flag_code_names[flag_code]);
24eab124 4360 }
20f0a1fc 4361 return ok;
24eab124 4362}
252b5132 4363
252b5132 4364/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4365 on error. */
252b5132 4366
252b5132
RH		 4367static int
4368i386_operand (operand_string)
4369 char *operand_string;
4370{
af6bdddf
AM		 4371 const reg_entry *r;
4372 char *end_op;
24eab124 4373 char *op_string = operand_string;
252b5132 4374
24eab124 4375 if (is_space_char (*op_string))
252b5132
RH		 4376 ++op_string;
4377
24eab124 4378 /* We check for an absolute prefix (differentiating,
47926f60 4379 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4380 if (*op_string == ABSOLUTE_PREFIX)
4381 {
4382 ++op_string;
4383 if (is_space_char (*op_string))
4384 ++op_string;
4385 i.types[this_operand] |= JumpAbsolute;
4386 }
252b5132 4387
47926f60 4388 /* Check if operand is a register. */
af6bdddf
AM		 4389 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
4390 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 4391 {
24eab124
AM		 4392 /* Check for a segment override by searching for ':' after a
4393 segment register. */
4394 op_string = end_op;
4395 if (is_space_char (*op_string))
4396 ++op_string;
4397 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4398 {
4399 switch (r->reg_num)
4400 {
4401 case 0:
4402 i.seg[i.mem_operands] = &es;
4403 break;
4404 case 1:
4405 i.seg[i.mem_operands] = &cs;
4406 break;
4407 case 2:
4408 i.seg[i.mem_operands] = &ss;
4409 break;
4410 case 3:
4411 i.seg[i.mem_operands] = &ds;
4412 break;
4413 case 4:
4414 i.seg[i.mem_operands] = &fs;
4415 break;
4416 case 5:
4417 i.seg[i.mem_operands] = &gs;
4418 break;
4419 }
252b5132 4420
24eab124 4421 /* Skip the ':' and whitespace. */
252b5132
RH		 4422 ++op_string;
4423 if (is_space_char (*op_string))
24eab124 4424 ++op_string;
252b5132 4425
24eab124
AM		 4426 if (!is_digit_char (*op_string)
4427 && !is_identifier_char (*op_string)
4428 && *op_string != '('
4429 && *op_string != ABSOLUTE_PREFIX)
4430 {
4431 as_bad (_("bad memory operand `%s'"), op_string);
4432 return 0;
4433 }
47926f60 4434 /* Handle case of %es:*foo. */
24eab124
AM		 4435 if (*op_string == ABSOLUTE_PREFIX)
4436 {
4437 ++op_string;
4438 if (is_space_char (*op_string))
4439 ++op_string;
4440 i.types[this_operand] |= JumpAbsolute;
4441 }
4442 goto do_memory_reference;
4443 }
4444 if (*op_string)
4445 {
d0b47220 4446 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4447 return 0;
4448 }
4449 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4450 i.op[this_operand].regs = r;
24eab124
AM		 4451 i.reg_operands++;
4452 }
af6bdddf
AM		 4453 else if (*op_string == REGISTER_PREFIX)
4454 {
4455 as_bad (_("bad register name `%s'"), op_string);
4456 return 0;
4457 }
24eab124 4458 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4459 {
24eab124
AM		 4460 ++op_string;
4461 if (i.types[this_operand] & JumpAbsolute)
4462 {
d0b47220 4463 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4464 return 0;
4465 }
4466 if (!i386_immediate (op_string))
4467 return 0;
4468 }
4469 else if (is_digit_char (*op_string)
4470 || is_identifier_char (*op_string)
e5cb08ac 4471 || *op_string == '(')
24eab124 4472 {
47926f60 4473 /* This is a memory reference of some sort. */
af6bdddf 4474 char *base_string;
252b5132 4475
47926f60 4476 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4477 char *displacement_string_start;
4478 char *displacement_string_end;
252b5132 4479
24eab124 4480 do_memory_reference:
24eab124
AM		 4481 if ((i.mem_operands == 1
4482 && (current_templates->start->opcode_modifier & IsString) == 0)
4483 || i.mem_operands == 2)
4484 {
4485 as_bad (_("too many memory references for `%s'"),
4486 current_templates->start->name);
4487 return 0;
4488 }
252b5132 4489
24eab124
AM		 4490 /* Check for base index form. We detect the base index form by
4491 looking for an ')' at the end of the operand, searching
4492 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4493 after the '('. */
af6bdddf 4494 base_string = op_string + strlen (op_string);
c3332e24 4495
af6bdddf
AM		 4496 --base_string;
4497 if (is_space_char (*base_string))
4498 --base_string;
252b5132 4499
47926f60 4500 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4501 displacement_string_start = op_string;
4502 displacement_string_end = base_string + 1;
252b5132 4503
24eab124
AM		 4504 if (*base_string == ')')
4505 {
af6bdddf 4506 char *temp_string;
24eab124
AM		 4507 unsigned int parens_balanced = 1;
4508 /* We've already checked that the number of left & right ()'s are
47926f60 4509 equal, so this loop will not be infinite. */
24eab124
AM		 4510 do
4511 {
4512 base_string--;
4513 if (*base_string == ')')
4514 parens_balanced++;
4515 if (*base_string == '(')
4516 parens_balanced--;
4517 }
4518 while (parens_balanced);
c3332e24 4519
af6bdddf 4520 temp_string = base_string;
c3332e24 4521
24eab124 4522 /* Skip past '(' and whitespace. */
252b5132
RH		 4523 ++base_string;
4524 if (is_space_char (*base_string))
24eab124 4525 ++base_string;
252b5132 4526
af6bdddf
AM		 4527 if (*base_string == ','
4528 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4529 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4530 {
af6bdddf 4531 displacement_string_end = temp_string;
252b5132 4532
af6bdddf 4533 i.types[this_operand] |= BaseIndex;
252b5132 4534
af6bdddf 4535 if (i.base_reg)
24eab124 4536 {
24eab124
AM		 4537 base_string = end_op;
4538 if (is_space_char (*base_string))
4539 ++base_string;
af6bdddf
AM		 4540 }
4541
4542 /* There may be an index reg or scale factor here. */
4543 if (*base_string == ',')
4544 {
4545 ++base_string;
4546 if (is_space_char (*base_string))
4547 ++base_string;
4548
4549 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4550 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4551 {
af6bdddf 4552 base_string = end_op;
24eab124
AM		 4553 if (is_space_char (*base_string))
4554 ++base_string;
af6bdddf
AM		 4555 if (*base_string == ',')
4556 {
4557 ++base_string;
4558 if (is_space_char (*base_string))
4559 ++base_string;
4560 }
e5cb08ac 4561 else if (*base_string != ')')
af6bdddf
AM		 4562 {
4563 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4564 operand_string);
4565 return 0;
4566 }
24eab124 4567 }
af6bdddf 4568 else if (*base_string == REGISTER_PREFIX)
24eab124 4569 {
af6bdddf 4570 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4571 return 0;
4572 }
252b5132 4573
47926f60 4574 /* Check for scale factor. */
551c1ca1 4575 if (*base_string != ')')
af6bdddf 4576 {
551c1ca1
AM		 4577 char *end_scale = i386_scale (base_string);
4578
4579 if (!end_scale)
af6bdddf 4580 return 0;
24eab124 4581
551c1ca1 4582 base_string = end_scale;
af6bdddf
AM		 4583 if (is_space_char (*base_string))
4584 ++base_string;
4585 if (*base_string != ')')
4586 {
4587 as_bad (_("expecting `)' after scale factor in `%s'"),
4588 operand_string);
4589 return 0;
4590 }
4591 }
4592 else if (!i.index_reg)
24eab124 4593 {
af6bdddf
AM		 4594 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4595 *base_string);
24eab124
AM		 4596 return 0;
4597 }
4598 }
af6bdddf 4599 else if (*base_string != ')')
24eab124 4600 {
af6bdddf
AM		 4601 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4602 operand_string);
24eab124
AM		 4603 return 0;
4604 }
c3332e24 4605 }
af6bdddf 4606 else if (*base_string == REGISTER_PREFIX)
c3332e24 4607 {
af6bdddf 4608 as_bad (_("bad register name `%s'"), base_string);
24eab124 4609 return 0;
c3332e24 4610 }
24eab124
AM		 4611 }
4612
4613 /* If there's an expression beginning the operand, parse it,
4614 assuming displacement_string_start and
4615 displacement_string_end are meaningful. */
4616 if (displacement_string_start != displacement_string_end)
4617 {
4618 if (!i386_displacement (displacement_string_start,
4619 displacement_string_end))
4620 return 0;
4621 }
4622
4623 /* Special case for (%dx) while doing input/output op. */
4624 if (i.base_reg
4625 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4626 && i.index_reg == 0
4627 && i.log2_scale_factor == 0
4628 && i.seg[i.mem_operands] == 0
4629 && (i.types[this_operand] & Disp) == 0)
4630 {
4631 i.types[this_operand] = InOutPortReg;
4632 return 1;
4633 }
4634
eecb386c
AM		 4635 if (i386_index_check (operand_string) == 0)
4636 return 0;
24eab124
AM		 4637 i.mem_operands++;
4638 }
4639 else
ce8a8b2f
AM		 4640 {
4641 /* It's not a memory operand; argh! */
24eab124
AM		 4642 as_bad (_("invalid char %s beginning operand %d `%s'"),
4643 output_invalid (*op_string),
4644 this_operand + 1,
4645 op_string);
4646 return 0;
4647 }
47926f60 4648 return 1; /* Normal return. */
252b5132
RH		 4649}
4650\f
ee7fcc42
AM		 4651/* md_estimate_size_before_relax()
4652
4653 Called just before relax() for rs_machine_dependent frags. The x86
4654 assembler uses these frags to handle variable size jump
4655 instructions.
4656
4657 Any symbol that is now undefined will not become defined.
4658 Return the correct fr_subtype in the frag.
4659 Return the initial "guess for variable size of frag" to caller.
4660 The guess is actually the growth beyond the fixed part. Whatever
4661 we do to grow the fixed or variable part contributes to our
4662 returned value. */
4663
252b5132
RH		 4664int
4665md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4666 fragS *fragP;
4667 segT segment;
252b5132 4668{
252b5132 4669 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4670 check for un-relaxable symbols. On an ELF system, we can't relax
4671 an externally visible symbol, because it may be overridden by a
4672 shared library. */
4673 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4674#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 4675 || (IS_ELF
31312f95
AM		 4676 && (S_IS_EXTERNAL (fragP->fr_symbol)
4677 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 4678#endif
4679 )
252b5132 4680 {
b98ef147
AM		 4681 /* Symbol is undefined in this segment, or we need to keep a
4682 reloc so that weak symbols can be overridden. */
4683 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 4684 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 4685 unsigned char *opcode;
4686 int old_fr_fix;
f6af82bd 4687
ee7fcc42
AM		 4688 if (fragP->fr_var != NO_RELOC)
4689 reloc_type = fragP->fr_var;
b98ef147 4690 else if (size == 2)
f6af82bd
AM		 4691 reloc_type = BFD_RELOC_16_PCREL;
4692 else
4693 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4694
ee7fcc42
AM		 4695 old_fr_fix = fragP->fr_fix;
4696 opcode = (unsigned char *) fragP->fr_opcode;
4697
fddf5b5b 4698 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4699 {
fddf5b5b
AM		 4700 case UNCOND_JUMP:
4701 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4702 opcode[0] = 0xe9;
252b5132 4703 fragP->fr_fix += size;
062cd5e7
AS		 4704 fix_new (fragP, old_fr_fix, size,
4705 fragP->fr_symbol,
4706 fragP->fr_offset, 1,
4707 reloc_type);
252b5132
RH		 4708 break;
4709
fddf5b5b 4710 case COND_JUMP86:
412167cb
AM		 4711 if (size == 2
4712 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4713 {
4714 /* Negate the condition, and branch past an
4715 unconditional jump. */
4716 opcode[0] ^= 1;
4717 opcode[1] = 3;
4718 /* Insert an unconditional jump. */
4719 opcode[2] = 0xe9;
4720 /* We added two extra opcode bytes, and have a two byte
4721 offset. */
4722 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4723 fix_new (fragP, old_fr_fix + 2, 2,
4724 fragP->fr_symbol,
4725 fragP->fr_offset, 1,
4726 reloc_type);
fddf5b5b
AM		 4727 break;
4728 }
4729 /* Fall through. */
4730
4731 case COND_JUMP:
412167cb
AM		 4732 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4733 {
3e02c1cc
AM		 4734 fixS *fixP;
4735
412167cb 4736 fragP->fr_fix += 1;
3e02c1cc
AM		 4737 fixP = fix_new (fragP, old_fr_fix, 1,
4738 fragP->fr_symbol,
4739 fragP->fr_offset, 1,
4740 BFD_RELOC_8_PCREL);
4741 fixP->fx_signed = 1;
412167cb
AM		 4742 break;
4743 }
93c2a809 4744
24eab124 4745 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4746 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4747 opcode[1] = opcode[0] + 0x10;
f6af82bd 4748 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4749 /* We've added an opcode byte. */
4750 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4751 fix_new (fragP, old_fr_fix + 1, size,
4752 fragP->fr_symbol,
4753 fragP->fr_offset, 1,
4754 reloc_type);
252b5132 4755 break;
fddf5b5b
AM		 4756
4757 default:
4758 BAD_CASE (fragP->fr_subtype);
4759 break;
252b5132
RH		 4760 }
4761 frag_wane (fragP);
ee7fcc42 4762 return fragP->fr_fix - old_fr_fix;
252b5132 4763 }
93c2a809 4764
93c2a809
AM		 4765 /* Guess size depending on current relax state. Initially the relax
4766 state will correspond to a short jump and we return 1, because
4767 the variable part of the frag (the branch offset) is one byte
4768 long. However, we can relax a section more than once and in that
4769 case we must either set fr_subtype back to the unrelaxed state,
4770 or return the value for the appropriate branch. */
4771 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4772}
4773
47926f60
KH		 4774/* Called after relax() is finished.
4775
4776 In: Address of frag.
4777 fr_type == rs_machine_dependent.
4778 fr_subtype is what the address relaxed to.
4779
4780 Out: Any fixSs and constants are set up.
4781 Caller will turn frag into a ".space 0". */
4782
252b5132
RH		 4783void
4784md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4785 bfd *abfd ATTRIBUTE_UNUSED;
4786 segT sec ATTRIBUTE_UNUSED;
29b0f896 4787 fragS *fragP;
252b5132 4788{
29b0f896 4789 unsigned char *opcode;
252b5132 4790 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4791 offsetT target_address;
4792 offsetT opcode_address;
252b5132 4793 unsigned int extension = 0;
847f7ad4 4794 offsetT displacement_from_opcode_start;
252b5132
RH		 4795
4796 opcode = (unsigned char *) fragP->fr_opcode;
4797
47926f60 4798 /* Address we want to reach in file space. */
252b5132 4799 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4800
47926f60 4801 /* Address opcode resides at in file space. */
252b5132
RH		 4802 opcode_address = fragP->fr_address + fragP->fr_fix;
4803
47926f60 4804 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4805 displacement_from_opcode_start = target_address - opcode_address;
4806
fddf5b5b 4807 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4808 {
47926f60
KH		 4809 /* Don't have to change opcode. */
4810 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4811 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4812 }
4813 else
4814 {
4815 if (no_cond_jump_promotion
4816 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4817 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4818
fddf5b5b
AM		 4819 switch (fragP->fr_subtype)
4820 {
4821 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4822 extension = 4; /* 1 opcode + 4 displacement */
4823 opcode[0] = 0xe9;
4824 where_to_put_displacement = &opcode[1];
4825 break;
252b5132 4826
fddf5b5b
AM		 4827 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4828 extension = 2; /* 1 opcode + 2 displacement */
4829 opcode[0] = 0xe9;
4830 where_to_put_displacement = &opcode[1];
4831 break;
252b5132 4832
fddf5b5b
AM		 4833 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4834 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4835 extension = 5; /* 2 opcode + 4 displacement */
4836 opcode[1] = opcode[0] + 0x10;
4837 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4838 where_to_put_displacement = &opcode[2];
4839 break;
252b5132 4840
fddf5b5b
AM		 4841 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4842 extension = 3; /* 2 opcode + 2 displacement */
4843 opcode[1] = opcode[0] + 0x10;
4844 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4845 where_to_put_displacement = &opcode[2];
4846 break;
252b5132 4847
fddf5b5b
AM		 4848 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4849 extension = 4;
4850 opcode[0] ^= 1;
4851 opcode[1] = 3;
4852 opcode[2] = 0xe9;
4853 where_to_put_displacement = &opcode[3];
4854 break;
4855
4856 default:
4857 BAD_CASE (fragP->fr_subtype);
4858 break;
4859 }
252b5132 4860 }
fddf5b5b 4861
47926f60 4862 /* Now put displacement after opcode. */
252b5132
RH		 4863 md_number_to_chars ((char *) where_to_put_displacement,
4864 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4865 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4866 fragP->fr_fix += extension;
4867}
4868\f
47926f60
KH		 4869/* Size of byte displacement jmp. */
4870int md_short_jump_size = 2;
4871
4872/* Size of dword displacement jmp. */
4873int md_long_jump_size = 5;
252b5132 4874
252b5132
RH		 4875void
4876md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4877 char *ptr;
4878 addressT from_addr, to_addr;
ab9da554
ILT		 4879 fragS *frag ATTRIBUTE_UNUSED;
4880 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4881{
847f7ad4 4882 offsetT offset;
252b5132
RH		 4883
4884 offset = to_addr - (from_addr + 2);
47926f60
KH		 4885 /* Opcode for byte-disp jump. */
4886 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4887 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4888}
4889
4890void
4891md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4892 char *ptr;
4893 addressT from_addr, to_addr;
a38cf1db
AM		 4894 fragS *frag ATTRIBUTE_UNUSED;
4895 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4896{
847f7ad4 4897 offsetT offset;
252b5132 4898
a38cf1db
AM		 4899 offset = to_addr - (from_addr + 5);
4900 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4901 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4902}
4903\f
4904/* Apply a fixup (fixS) to segment data, once it has been determined
4905 by our caller that we have all the info we need to fix it up.
4906
4907 On the 386, immediates, displacements, and data pointers are all in
4908 the same (little-endian) format, so we don't need to care about which
4909 we are handling. */
4910
94f592af 4911void
55cf6793 4912md_apply_fix (fixP, valP, seg)
47926f60
KH		 4913 /* The fix we're to put in. */
4914 fixS *fixP;
47926f60 4915 /* Pointer to the value of the bits. */
c6682705 4916 valueT *valP;
47926f60
KH		 4917 /* Segment fix is from. */
4918 segT seg ATTRIBUTE_UNUSED;
252b5132 4919{
94f592af 4920 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 4921 valueT value = *valP;
252b5132 4922
f86103b7 4923#if !defined (TE_Mach)
93382f6d
AM		 4924 if (fixP->fx_pcrel)
4925 {
4926 switch (fixP->fx_r_type)
4927 {
5865bb77
ILT		 4928 default:
4929 break;
4930
d6ab8113
JB		 4931 case BFD_RELOC_64:
4932 fixP->fx_r_type = BFD_RELOC_64_PCREL;
4933 break;
93382f6d 4934 case BFD_RELOC_32:
ae8887b5 4935 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 4936 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4937 break;
4938 case BFD_RELOC_16:
4939 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4940 break;
4941 case BFD_RELOC_8:
4942 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4943 break;
4944 }
4945 }
252b5132 4946
a161fe53 4947 if (fixP->fx_addsy != NULL
31312f95 4948 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 4949 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 4950 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4951 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4952 && !use_rela_relocations)
252b5132 4953 {
31312f95
AM		 4954 /* This is a hack. There should be a better way to handle this.
4955 This covers for the fact that bfd_install_relocation will
4956 subtract the current location (for partial_inplace, PC relative
4957 relocations); see more below. */
252b5132 4958#ifndef OBJ_AOUT
718ddfc0 4959 if (IS_ELF
252b5132
RH		 4960#ifdef TE_PE
4961 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4962#endif
4963 )
4964 value += fixP->fx_where + fixP->fx_frag->fr_address;
4965#endif
4966#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 4967 if (IS_ELF)
252b5132 4968 {
6539b54b 4969 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 4970
6539b54b 4971 if ((sym_seg == seg
2f66722d 4972 || (symbol_section_p (fixP->fx_addsy)
6539b54b 4973 && sym_seg != absolute_section))
ae6063d4 4974 && !generic_force_reloc (fixP))
2f66722d
AM		 4975 {
4976 /* Yes, we add the values in twice. This is because
6539b54b
AM		 4977 bfd_install_relocation subtracts them out again. I think
4978 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 4979 it. FIXME. */
4980 value += fixP->fx_where + fixP->fx_frag->fr_address;
4981 }
252b5132
RH		 4982 }
4983#endif
4984#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 4985 /* For some reason, the PE format does not store a
4986 section address offset for a PC relative symbol. */
4987 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 4988 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 4989 value += md_pcrel_from (fixP);
4990#endif
4991 }
4992
4993 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 4994 and we must not disappoint it. */
252b5132 4995#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 4996 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 4997 switch (fixP->fx_r_type)
4998 {
4999 case BFD_RELOC_386_PLT32:
3e73aa7c 5000 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5001 /* Make the jump instruction point to the address of the operand. At
5002 runtime we merely add the offset to the actual PLT entry. */
5003 value = -4;
5004 break;
31312f95 5005
13ae64f3
JJ		 5006 case BFD_RELOC_386_TLS_GD:
5007 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5008 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5009 case BFD_RELOC_386_TLS_IE:
5010 case BFD_RELOC_386_TLS_GOTIE:
bffbf940
JJ		 5011 case BFD_RELOC_X86_64_TLSGD:
5012 case BFD_RELOC_X86_64_TLSLD:
5013 case BFD_RELOC_X86_64_GOTTPOFF:
00f7efb6
JJ		 5014 value = 0; /* Fully resolved at runtime. No addend. */
5015 /* Fallthrough */
5016 case BFD_RELOC_386_TLS_LE:
5017 case BFD_RELOC_386_TLS_LDO_32:
5018 case BFD_RELOC_386_TLS_LE_32:
5019 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5020 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5021 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5022 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5023 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5024 break;
5025
5026 case BFD_RELOC_386_GOT32:
5027 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5028 value = 0; /* Fully resolved at runtime. No addend. */
5029 break;
47926f60
KH		 5030
5031 case BFD_RELOC_VTABLE_INHERIT:
5032 case BFD_RELOC_VTABLE_ENTRY:
5033 fixP->fx_done = 0;
94f592af 5034 return;
47926f60
KH		 5035
5036 default:
5037 break;
5038 }
5039#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5040 *valP = value;
f86103b7 5041#endif /* !defined (TE_Mach) */
3e73aa7c 5042
3e73aa7c 5043 /* Are we finished with this relocation now? */
c6682705 5044 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5045 fixP->fx_done = 1;
5046 else if (use_rela_relocations)
5047 {
5048 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5049 /* Remember value for tc_gen_reloc. */
5050 fixP->fx_addnumber = value;
3e73aa7c
JH		 5051 value = 0;
5052 }
f86103b7 5053
94f592af 5054 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5055}
252b5132 5056\f
252b5132
RH		 5057#define MAX_LITTLENUMS 6
5058
47926f60
KH		 5059/* Turn the string pointed to by litP into a floating point constant
5060 of type TYPE, and emit the appropriate bytes. The number of
5061 LITTLENUMS emitted is stored in *SIZEP. An error message is
5062 returned, or NULL on OK. */
5063
252b5132
RH		 5064char *
5065md_atof (type, litP, sizeP)
2ab9b79e 5066 int type;
252b5132
RH		 5067 char *litP;
5068 int *sizeP;
5069{
5070 int prec;
5071 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5072 LITTLENUM_TYPE *wordP;
5073 char *t;
5074
5075 switch (type)
5076 {
5077 case 'f':
5078 case 'F':
5079 prec = 2;
5080 break;
5081
5082 case 'd':
5083 case 'D':
5084 prec = 4;
5085 break;
5086
5087 case 'x':
5088 case 'X':
5089 prec = 5;
5090 break;
5091
5092 default:
5093 *sizeP = 0;
5094 return _("Bad call to md_atof ()");
5095 }
5096 t = atof_ieee (input_line_pointer, type, words);
5097 if (t)
5098 input_line_pointer = t;
5099
5100 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5101 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5102 the bigendian 386. */
5103 for (wordP = words + prec - 1; prec--;)
5104 {
5105 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5106 litP += sizeof (LITTLENUM_TYPE);
5107 }
5108 return 0;
5109}
5110\f
87c245cc 5111static char output_invalid_buf[8];
252b5132 5112
252b5132
RH		 5113static char *
5114output_invalid (c)
5115 int c;
5116{
3882b010 5117 if (ISPRINT (c))
252b5132
RH		 5118 sprintf (output_invalid_buf, "'%c'", c);
5119 else
5120 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
5121 return output_invalid_buf;
5122}
5123
af6bdddf 5124/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5125
5126static const reg_entry *
5127parse_register (reg_string, end_op)
5128 char *reg_string;
5129 char **end_op;
5130{
af6bdddf
AM		 5131 char *s = reg_string;
5132 char *p;
252b5132
RH		 5133 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5134 const reg_entry *r;
5135
5136 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5137 if (*s == REGISTER_PREFIX)
5138 ++s;
5139
5140 if (is_space_char (*s))
5141 ++s;
5142
5143 p = reg_name_given;
af6bdddf 5144 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5145 {
5146 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5147 return (const reg_entry *) NULL;
5148 s++;
252b5132
RH		 5149 }
5150
6588847e
DN		 5151 /* For naked regs, make sure that we are not dealing with an identifier.
5152 This prevents confusing an identifier like `eax_var' with register
5153 `eax'. */
5154 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5155 return (const reg_entry *) NULL;
5156
af6bdddf 5157 *end_op = s;
252b5132
RH		 5158
5159 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5160
5f47d35b 5161 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5162 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5163 {
5f47d35b
AM		 5164 if (is_space_char (*s))
5165 ++s;
5166 if (*s == '(')
5167 {
af6bdddf 5168 ++s;
5f47d35b
AM		 5169 if (is_space_char (*s))
5170 ++s;
5171 if (*s >= '0' && *s <= '7')
5172 {
5173 r = &i386_float_regtab[*s - '0'];
af6bdddf 5174 ++s;
5f47d35b
AM		 5175 if (is_space_char (*s))
5176 ++s;
5177 if (*s == ')')
5178 {
5179 *end_op = s + 1;
5180 return r;
5181 }
5f47d35b 5182 }
47926f60 5183 /* We have "%st(" then garbage. */
5f47d35b
AM		 5184 return (const reg_entry *) NULL;
5185 }
5186 }
5187
1ae00879 5188 if (r != NULL
20f0a1fc 5189 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5190 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5191 && flag_code != CODE_64BIT)
20f0a1fc 5192 return (const reg_entry *) NULL;
1ae00879 5193
252b5132
RH		 5194 return r;
5195}
5196\f
4cc782b5 5197#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5198const char *md_shortopts = "kVQ:sqn";
252b5132 5199#else
12b55ccc 5200const char *md_shortopts = "qn";
252b5132 5201#endif
6e0b89ee 5202
252b5132 5203struct option md_longopts[] = {
3e73aa7c
JH		 5204#define OPTION_32 (OPTION_MD_BASE + 0)
5205 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 5206#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c
JH		 5207#define OPTION_64 (OPTION_MD_BASE + 1)
5208 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5209#endif
252b5132
RH		 5210 {NULL, no_argument, NULL, 0}
5211};
5212size_t md_longopts_size = sizeof (md_longopts);
5213
5214int
5215md_parse_option (c, arg)
5216 int c;
ab9da554 5217 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 5218{
5219 switch (c)
5220 {
12b55ccc
L		 5221 case 'n':
5222 optimize_align_code = 0;
5223 break;
5224
a38cf1db
AM		 5225 case 'q':
5226 quiet_warnings = 1;
252b5132
RH		 5227 break;
5228
5229#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5230 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5231 should be emitted or not. FIXME: Not implemented. */
5232 case 'Q':
252b5132
RH		 5233 break;
5234
5235 /* -V: SVR4 argument to print version ID. */
5236 case 'V':
5237 print_version_id ();
5238 break;
5239
a38cf1db
AM		 5240 /* -k: Ignore for FreeBSD compatibility. */
5241 case 'k':
252b5132 5242 break;
4cc782b5
ILT		 5243
5244 case 's':
5245 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5246 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5247 break;
6e0b89ee 5248
3e73aa7c
JH		 5249 case OPTION_64:
5250 {
5251 const char **list, **l;
5252
3e73aa7c
JH		 5253 list = bfd_target_list ();
5254 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 5255 if (strcmp (*l, "elf64-x86-64") == 0)
5256 {
5257 default_arch = "x86_64";
5258 break;
5259 }
3e73aa7c 5260 if (*l == NULL)
6e0b89ee 5261 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5262 free (list);
5263 }
5264 break;
5265#endif
252b5132 5266
6e0b89ee
AM		 5267 case OPTION_32:
5268 default_arch = "i386";
5269 break;
5270
252b5132
RH		 5271 default:
5272 return 0;
5273 }
5274 return 1;
5275}
5276
5277void
5278md_show_usage (stream)
5279 FILE *stream;
5280{
4cc782b5
ILT		 5281#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5282 fprintf (stream, _("\
a38cf1db
AM		 5283 -Q ignored\n\
5284 -V print assembler version number\n\
5285 -k ignored\n\
12b55ccc 5286 -n Do not optimize code alignment\n\
a38cf1db
AM		 5287 -q quieten some warnings\n\
5288 -s ignored\n"));
5289#else
5290 fprintf (stream, _("\
12b55ccc 5291 -n Do not optimize code alignment\n\
a38cf1db 5292 -q quieten some warnings\n"));
4cc782b5 5293#endif
252b5132
RH		 5294}
5295
3e73aa7c
JH		 5296#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5297 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 5298
5299/* Pick the target format to use. */
5300
47926f60 5301const char *
252b5132
RH		 5302i386_target_format ()
5303{
3e73aa7c
JH		 5304 if (!strcmp (default_arch, "x86_64"))
5305 set_code_flag (CODE_64BIT);
5306 else if (!strcmp (default_arch, "i386"))
5307 set_code_flag (CODE_32BIT);
5308 else
5309 as_fatal (_("Unknown architecture"));
252b5132
RH		 5310 switch (OUTPUT_FLAVOR)
5311 {
4c63da97
AM		 5312#ifdef OBJ_MAYBE_AOUT
5313 case bfd_target_aout_flavour:
47926f60 5314 return AOUT_TARGET_FORMAT;
4c63da97
AM		 5315#endif
5316#ifdef OBJ_MAYBE_COFF
252b5132
RH		 5317 case bfd_target_coff_flavour:
5318 return "coff-i386";
4c63da97 5319#endif
3e73aa7c 5320#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 5321 case bfd_target_elf_flavour:
3e73aa7c 5322 {
e5cb08ac 5323 if (flag_code == CODE_64BIT)
4fa24527
JB		 5324 {
5325 object_64bit = 1;
5326 use_rela_relocations = 1;
5327 }
4ada7262 5328 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
3e73aa7c 5329 }
4c63da97 5330#endif
252b5132
RH		 5331 default:
5332 abort ();
5333 return NULL;
5334 }
5335}
5336
47926f60 5337#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 5338
5339#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5340void i386_elf_emit_arch_note ()
5341{
718ddfc0 5342 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 5343 {
5344 char *p;
5345 asection *seg = now_seg;
5346 subsegT subseg = now_subseg;
5347 Elf_Internal_Note i_note;
5348 Elf_External_Note e_note;
5349 asection *note_secp;
5350 int len;
5351
5352 /* Create the .note section. */
5353 note_secp = subseg_new (".note", 0);
5354 bfd_set_section_flags (stdoutput,
5355 note_secp,
5356 SEC_HAS_CONTENTS | SEC_READONLY);
5357
5358 /* Process the arch string. */
5359 len = strlen (cpu_arch_name);
5360
5361 i_note.namesz = len + 1;
5362 i_note.descsz = 0;
5363 i_note.type = NT_ARCH;
5364 p = frag_more (sizeof (e_note.namesz));
5365 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5366 p = frag_more (sizeof (e_note.descsz));
5367 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5368 p = frag_more (sizeof (e_note.type));
5369 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5370 p = frag_more (len + 1);
5371 strcpy (p, cpu_arch_name);
5372
5373 frag_align (2, 0, 0);
5374
5375 subseg_set (seg, subseg);
5376 }
5377}
5378#endif
252b5132 5379\f
252b5132
RH		 5380symbolS *
5381md_undefined_symbol (name)
5382 char *name;
5383{
18dc2407
ILT		 5384 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5385 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5386 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5387 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 5388 {
5389 if (!GOT_symbol)
5390 {
5391 if (symbol_find (name))
5392 as_bad (_("GOT already in symbol table"));
5393 GOT_symbol = symbol_new (name, undefined_section,
5394 (valueT) 0, &zero_address_frag);
5395 };
5396 return GOT_symbol;
5397 }
252b5132
RH		 5398 return 0;
5399}
5400
5401/* Round up a section size to the appropriate boundary. */
47926f60 5402
252b5132
RH		 5403valueT
5404md_section_align (segment, size)
ab9da554 5405 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 5406 valueT size;
5407{
4c63da97
AM		 5408#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5409 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5410 {
5411 /* For a.out, force the section size to be aligned. If we don't do
5412 this, BFD will align it for us, but it will not write out the
5413 final bytes of the section. This may be a bug in BFD, but it is
5414 easier to fix it here since that is how the other a.out targets
5415 work. */
5416 int align;
5417
5418 align = bfd_get_section_alignment (stdoutput, segment);
5419 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5420 }
252b5132
RH		 5421#endif
5422
5423 return size;
5424}
5425
5426/* On the i386, PC-relative offsets are relative to the start of the
5427 next instruction. That is, the address of the offset, plus its
5428 size, since the offset is always the last part of the insn. */
5429
5430long
5431md_pcrel_from (fixP)
5432 fixS *fixP;
5433{
5434 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5435}
5436
5437#ifndef I386COFF
5438
5439static void
5440s_bss (ignore)
ab9da554 5441 int ignore ATTRIBUTE_UNUSED;
252b5132 5442{
29b0f896 5443 int temp;
252b5132 5444
8a75718c
JB		 5445#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5446 if (IS_ELF)
5447 obj_elf_section_change_hook ();
5448#endif
252b5132
RH		 5449 temp = get_absolute_expression ();
5450 subseg_set (bss_section, (subsegT) temp);
5451 demand_empty_rest_of_line ();
5452}
5453
5454#endif
5455
252b5132
RH		 5456void
5457i386_validate_fix (fixp)
5458 fixS *fixp;
5459{
5460 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5461 {
23df1078
JH		 5462 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5463 {
4fa24527 5464 if (!object_64bit)
23df1078
JH		 5465 abort ();
5466 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5467 }
5468 else
5469 {
4fa24527 5470 if (!object_64bit)
d6ab8113
JB		 5471 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5472 else
5473 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 5474 }
252b5132
RH		 5475 fixp->fx_subsy = 0;
5476 }
5477}
5478
252b5132
RH		 5479arelent *
5480tc_gen_reloc (section, fixp)
ab9da554 5481 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5482 fixS *fixp;
5483{
5484 arelent *rel;
5485 bfd_reloc_code_real_type code;
5486
5487 switch (fixp->fx_r_type)
5488 {
3e73aa7c
JH		 5489 case BFD_RELOC_X86_64_PLT32:
5490 case BFD_RELOC_X86_64_GOT32:
5491 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5492 case BFD_RELOC_386_PLT32:
5493 case BFD_RELOC_386_GOT32:
5494 case BFD_RELOC_386_GOTOFF:
5495 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5496 case BFD_RELOC_386_TLS_GD:
5497 case BFD_RELOC_386_TLS_LDM:
5498 case BFD_RELOC_386_TLS_LDO_32:
5499 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5500 case BFD_RELOC_386_TLS_IE:
5501 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 5502 case BFD_RELOC_386_TLS_LE_32:
5503 case BFD_RELOC_386_TLS_LE:
bffbf940
JJ		 5504 case BFD_RELOC_X86_64_TLSGD:
5505 case BFD_RELOC_X86_64_TLSLD:
5506 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5507 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 5508 case BFD_RELOC_X86_64_GOTTPOFF:
5509 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 5510 case BFD_RELOC_X86_64_TPOFF64:
5511 case BFD_RELOC_X86_64_GOTOFF64:
5512 case BFD_RELOC_X86_64_GOTPC32:
252b5132
RH		 5513 case BFD_RELOC_RVA:
5514 case BFD_RELOC_VTABLE_ENTRY:
5515 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 5516#ifdef TE_PE
5517 case BFD_RELOC_32_SECREL:
5518#endif
252b5132
RH		 5519 code = fixp->fx_r_type;
5520 break;
dbbaec26
L		 5521 case BFD_RELOC_X86_64_32S:
5522 if (!fixp->fx_pcrel)
5523 {
5524 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5525 code = fixp->fx_r_type;
5526 break;
5527 }
252b5132 5528 default:
93382f6d 5529 if (fixp->fx_pcrel)
252b5132 5530 {
93382f6d
AM		 5531 switch (fixp->fx_size)
5532 {
5533 default:
b091f402
AM		 5534 as_bad_where (fixp->fx_file, fixp->fx_line,
5535 _("can not do %d byte pc-relative relocation"),
5536 fixp->fx_size);
93382f6d
AM		 5537 code = BFD_RELOC_32_PCREL;
5538 break;
5539 case 1: code = BFD_RELOC_8_PCREL; break;
5540 case 2: code = BFD_RELOC_16_PCREL; break;
5541 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 5542#ifdef BFD64
5543 case 8: code = BFD_RELOC_64_PCREL; break;
5544#endif
93382f6d
AM		 5545 }
5546 }
5547 else
5548 {
5549 switch (fixp->fx_size)
5550 {
5551 default:
b091f402
AM		 5552 as_bad_where (fixp->fx_file, fixp->fx_line,
5553 _("can not do %d byte relocation"),
5554 fixp->fx_size);
93382f6d
AM		 5555 code = BFD_RELOC_32;
5556 break;
5557 case 1: code = BFD_RELOC_8; break;
5558 case 2: code = BFD_RELOC_16; break;
5559 case 4: code = BFD_RELOC_32; break;
937149dd 5560#ifdef BFD64
3e73aa7c 5561 case 8: code = BFD_RELOC_64; break;
937149dd 5562#endif
93382f6d 5563 }
252b5132
RH		 5564 }
5565 break;
5566 }
252b5132 5567
d6ab8113 5568 if ((code == BFD_RELOC_32 || code == BFD_RELOC_32_PCREL)
252b5132
RH		 5569 && GOT_symbol
5570 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 5571 {
4fa24527 5572 if (!object_64bit)
d6ab8113
JB		 5573 code = BFD_RELOC_386_GOTPC;
5574 else
5575 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 5576 }
252b5132
RH		 5577
5578 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5579 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5580 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5581
5582 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 5583
3e73aa7c
JH		 5584 if (!use_rela_relocations)
5585 {
5586 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5587 vtable entry to be used in the relocation's section offset. */
5588 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5589 rel->address = fixp->fx_offset;
252b5132 5590
c6682705 5591 rel->addend = 0;
3e73aa7c
JH		 5592 }
5593 /* Use the rela in 64bit mode. */
252b5132 5594 else
3e73aa7c 5595 {
062cd5e7
AS		 5596 if (!fixp->fx_pcrel)
5597 rel->addend = fixp->fx_offset;
5598 else
5599 switch (code)
5600 {
5601 case BFD_RELOC_X86_64_PLT32:
5602 case BFD_RELOC_X86_64_GOT32:
5603 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 5604 case BFD_RELOC_X86_64_TLSGD:
5605 case BFD_RELOC_X86_64_TLSLD:
5606 case BFD_RELOC_X86_64_GOTTPOFF:
062cd5e7
AS		 5607 rel->addend = fixp->fx_offset - fixp->fx_size;
5608 break;
5609 default:
5610 rel->addend = (section->vma
5611 - fixp->fx_size
5612 + fixp->fx_addnumber
5613 + md_pcrel_from (fixp));
5614 break;
5615 }
3e73aa7c
JH		 5616 }
5617
252b5132
RH		 5618 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5619 if (rel->howto == NULL)
5620 {
5621 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5622 _("cannot represent relocation type %s"),
252b5132
RH		 5623 bfd_get_reloc_code_name (code));
5624 /* Set howto to a garbage value so that we can keep going. */
5625 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5626 assert (rel->howto != NULL);
5627 }
5628
5629 return rel;
5630}
5631
64a0c779
DN		 5632\f
5633/* Parse operands using Intel syntax. This implements a recursive descent
5634 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5635 Programmer's Guide.
5636
5637 FIXME: We do not recognize the full operand grammar defined in the MASM
5638 documentation. In particular, all the structure/union and
5639 high-level macro operands are missing.
5640
5641 Uppercase words are terminals, lower case words are non-terminals.
5642 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5643 bars '|' denote choices. Most grammar productions are implemented in
5644 functions called 'intel_<production>'.
5645
5646 Initial production is 'expr'.
5647
9306ca4a 5648 addOp + | -
64a0c779
DN		 5649
5650 alpha [a-zA-Z]
5651
9306ca4a
JB		 5652 binOp & | AND | \| | OR | ^ | XOR
5653
64a0c779
DN		 5654 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5655
5656 constant digits [[ radixOverride ]]
5657
9306ca4a 5658 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 5659
5660 digits decdigit
b77a7acd
AJ		 5661 | digits decdigit
5662 | digits hexdigit
64a0c779
DN		 5663
5664 decdigit [0-9]
5665
9306ca4a
JB		 5666 e04 e04 addOp e05
5667 | e05
5668
5669 e05 e05 binOp e06
b77a7acd 5670 | e06
64a0c779
DN		 5671
5672 e06 e06 mulOp e09
b77a7acd 5673 | e09
64a0c779
DN		 5674
5675 e09 OFFSET e10
a724f0f4
JB		 5676 | SHORT e10
5677 | + e10
5678 | - e10
9306ca4a
JB		 5679 | ~ e10
5680 | NOT e10
64a0c779
DN		 5681 | e09 PTR e10
5682 | e09 : e10
5683 | e10
5684
5685 e10 e10 [ expr ]
b77a7acd 5686 | e11
64a0c779
DN		 5687
5688 e11 ( expr )
b77a7acd 5689 | [ expr ]
64a0c779
DN		 5690 | constant
5691 | dataType
5692 | id
5693 | $
5694 | register
5695
a724f0f4 5696 => expr expr cmpOp e04
9306ca4a 5697 | e04
64a0c779
DN		 5698
5699 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5700 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5701
5702 hexdigit a | b | c | d | e | f
b77a7acd 5703 | A | B | C | D | E | F
64a0c779
DN		 5704
5705 id alpha
b77a7acd 5706 | id alpha
64a0c779
DN		 5707 | id decdigit
5708
9306ca4a 5709 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 5710
5711 quote " | '
5712
5713 register specialRegister
b77a7acd 5714 | gpRegister
64a0c779
DN		 5715 | byteRegister
5716
5717 segmentRegister CS | DS | ES | FS | GS | SS
5718
9306ca4a 5719 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 5720 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5721 | TR3 | TR4 | TR5 | TR6 | TR7
5722
64a0c779
DN		 5723 We simplify the grammar in obvious places (e.g., register parsing is
5724 done by calling parse_register) and eliminate immediate left recursion
5725 to implement a recursive-descent parser.
5726
a724f0f4
JB		 5727 expr e04 expr'
5728
5729 expr' cmpOp e04 expr'
5730 | Empty
9306ca4a
JB		 5731
5732 e04 e05 e04'
5733
5734 e04' addOp e05 e04'
5735 | Empty
64a0c779
DN		 5736
5737 e05 e06 e05'
5738
9306ca4a 5739 e05' binOp e06 e05'
b77a7acd 5740 | Empty
64a0c779
DN		 5741
5742 e06 e09 e06'
5743
5744 e06' mulOp e09 e06'
b77a7acd 5745 | Empty
64a0c779
DN		 5746
5747 e09 OFFSET e10 e09'
a724f0f4
JB		 5748 | SHORT e10'
5749 | + e10'
5750 | - e10'
5751 | ~ e10'
5752 | NOT e10'
b77a7acd 5753 | e10 e09'
64a0c779
DN		 5754
5755 e09' PTR e10 e09'
b77a7acd 5756 | : e10 e09'
64a0c779
DN		 5757 | Empty
5758
5759 e10 e11 e10'
5760
5761 e10' [ expr ] e10'
b77a7acd 5762 | Empty
64a0c779
DN		 5763
5764 e11 ( expr )
b77a7acd 5765 | [ expr ]
64a0c779
DN		 5766 | BYTE
5767 | WORD
5768 | DWORD
9306ca4a 5769 | FWORD
64a0c779 5770 | QWORD
9306ca4a
JB		 5771 | TBYTE
5772 | OWORD
5773 | XMMWORD
64a0c779
DN		 5774 | .
5775 | $
5776 | register
5777 | id
5778 | constant */
5779
5780/* Parsing structure for the intel syntax parser. Used to implement the
5781 semantic actions for the operand grammar. */
5782struct intel_parser_s
5783 {
5784 char *op_string; /* The string being parsed. */
5785 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5786 int op_modifier; /* Operand modifier. */
64a0c779 5787 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 5788 int in_offset; /* >=1 if parsing operand of offset. */
5789 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 5790 const reg_entry *reg; /* Last register reference found. */
5791 char *disp; /* Displacement string being built. */
a724f0f4 5792 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 5793 };
5794
5795static struct intel_parser_s intel_parser;
5796
5797/* Token structure for parsing intel syntax. */
5798struct intel_token
5799 {
5800 int code; /* Token code. */
5801 const reg_entry *reg; /* Register entry for register tokens. */
5802 char *str; /* String representation. */
5803 };
5804
5805static struct intel_token cur_token, prev_token;
5806
50705ef4
AM		 5807/* Token codes for the intel parser. Since T_SHORT is already used
5808 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5809#define T_NIL -1
5810#define T_CONST 1
5811#define T_REG 2
5812#define T_BYTE 3
5813#define T_WORD 4
9306ca4a
JB		 5814#define T_DWORD 5
5815#define T_FWORD 6
5816#define T_QWORD 7
5817#define T_TBYTE 8
5818#define T_XMMWORD 9
50705ef4 5819#undef T_SHORT
9306ca4a
JB		 5820#define T_SHORT 10
5821#define T_OFFSET 11
5822#define T_PTR 12
5823#define T_ID 13
5824#define T_SHL 14
5825#define T_SHR 15
64a0c779
DN		 5826
5827/* Prototypes for intel parser functions. */
5828static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5829static void intel_get_token PARAMS ((void));
5830static void intel_putback_token PARAMS ((void));
5831static int intel_expr PARAMS ((void));
9306ca4a 5832static int intel_e04 PARAMS ((void));
cce0cbdc 5833static int intel_e05 PARAMS ((void));
cce0cbdc 5834static int intel_e06 PARAMS ((void));
cce0cbdc 5835static int intel_e09 PARAMS ((void));
a724f0f4 5836static int intel_bracket_expr PARAMS ((void));
cce0cbdc 5837static int intel_e10 PARAMS ((void));
cce0cbdc 5838static int intel_e11 PARAMS ((void));
64a0c779 5839
64a0c779
DN		 5840static int
5841i386_intel_operand (operand_string, got_a_float)
5842 char *operand_string;
5843 int got_a_float;
5844{
5845 int ret;
5846 char *p;
5847
a724f0f4
JB		 5848 p = intel_parser.op_string = xstrdup (operand_string);
5849 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
5850
5851 for (;;)
64a0c779 5852 {
a724f0f4
JB		 5853 /* Initialize token holders. */
5854 cur_token.code = prev_token.code = T_NIL;
5855 cur_token.reg = prev_token.reg = NULL;
5856 cur_token.str = prev_token.str = NULL;
5857
5858 /* Initialize parser structure. */
5859 intel_parser.got_a_float = got_a_float;
5860 intel_parser.op_modifier = 0;
5861 intel_parser.is_mem = 0;
5862 intel_parser.in_offset = 0;
5863 intel_parser.in_bracket = 0;
5864 intel_parser.reg = NULL;
5865 intel_parser.disp[0] = '\0';
5866 intel_parser.next_operand = NULL;
5867
5868 /* Read the first token and start the parser. */
5869 intel_get_token ();
5870 ret = intel_expr ();
5871
5872 if (!ret)
5873 break;
5874
9306ca4a
JB		 5875 if (cur_token.code != T_NIL)
5876 {
5877 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
5878 current_templates->start->name, cur_token.str);
5879 ret = 0;
5880 }
64a0c779
DN		 5881 /* If we found a memory reference, hand it over to i386_displacement
5882 to fill in the rest of the operand fields. */
9306ca4a 5883 else if (intel_parser.is_mem)
64a0c779
DN		 5884 {
5885 if ((i.mem_operands == 1
5886 && (current_templates->start->opcode_modifier & IsString) == 0)
5887 || i.mem_operands == 2)
5888 {
5889 as_bad (_("too many memory references for '%s'"),
5890 current_templates->start->name);
5891 ret = 0;
5892 }
5893 else
5894 {
5895 char *s = intel_parser.disp;
5896 i.mem_operands++;
5897
a724f0f4
JB		 5898 if (!quiet_warnings && intel_parser.is_mem < 0)
5899 /* See the comments in intel_bracket_expr. */
5900 as_warn (_("Treating `%s' as memory reference"), operand_string);
5901
64a0c779
DN		 5902 /* Add the displacement expression. */
5903 if (*s != '\0')
a4622f40
AM		 5904 ret = i386_displacement (s, s + strlen (s));
5905 if (ret)
a724f0f4
JB		 5906 {
5907 /* Swap base and index in 16-bit memory operands like
5908 [si+bx]. Since i386_index_check is also used in AT&T
5909 mode we have to do that here. */
5910 if (i.base_reg
5911 && i.index_reg
5912 && (i.base_reg->reg_type & Reg16)
5913 && (i.index_reg->reg_type & Reg16)
5914 && i.base_reg->reg_num >= 6
5915 && i.index_reg->reg_num < 6)
5916 {
5917 const reg_entry *base = i.index_reg;
5918
5919 i.index_reg = i.base_reg;
5920 i.base_reg = base;
5921 }
5922 ret = i386_index_check (operand_string);
5923 }
64a0c779
DN		 5924 }
5925 }
5926
5927 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 5928 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 5929 || intel_parser.reg == NULL)
5930 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 5931
5932 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
5933 ret = 0;
5934 if (!ret || !intel_parser.next_operand)
5935 break;
5936 intel_parser.op_string = intel_parser.next_operand;
5937 this_operand = i.operands++;
64a0c779
DN		 5938 }
5939
5940 free (p);
5941 free (intel_parser.disp);
5942
5943 return ret;
5944}
5945
a724f0f4
JB		 5946#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
5947
5948/* expr e04 expr'
5949
5950 expr' cmpOp e04 expr'
5951 | Empty */
64a0c779
DN		 5952static int
5953intel_expr ()
5954{
a724f0f4
JB		 5955 /* XXX Implement the comparison operators. */
5956 return intel_e04 ();
9306ca4a
JB		 5957}
5958
a724f0f4 5959/* e04 e05 e04'
9306ca4a 5960
a724f0f4 5961 e04' addOp e05 e04'
9306ca4a
JB		 5962 | Empty */
5963static int
5964intel_e04 ()
5965{
a724f0f4 5966 int nregs = -1;
9306ca4a 5967
a724f0f4 5968 for (;;)
9306ca4a 5969 {
a724f0f4
JB		 5970 if (!intel_e05())
5971 return 0;
9306ca4a 5972
a724f0f4
JB		 5973 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
5974 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 5975
a724f0f4
JB		 5976 if (cur_token.code == '+')
5977 nregs = -1;
5978 else if (cur_token.code == '-')
5979 nregs = NUM_ADDRESS_REGS;
5980 else
5981 return 1;
64a0c779 5982
a724f0f4
JB		 5983 strcat (intel_parser.disp, cur_token.str);
5984 intel_match_token (cur_token.code);
5985 }
64a0c779
DN		 5986}
5987
64a0c779
DN		 5988/* e05 e06 e05'
5989
9306ca4a 5990 e05' binOp e06 e05'
64a0c779
DN		 5991 | Empty */
5992static int
5993intel_e05 ()
5994{
a724f0f4 5995 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 5996
a724f0f4 5997 for (;;)
64a0c779 5998 {
a724f0f4
JB		 5999 if (!intel_e06())
6000 return 0;
6001
6002 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6003 {
6004 char str[2];
6005
6006 str[0] = cur_token.code;
6007 str[1] = 0;
6008 strcat (intel_parser.disp, str);
6009 }
6010 else
6011 break;
9306ca4a 6012
64a0c779
DN		 6013 intel_match_token (cur_token.code);
6014
a724f0f4
JB		 6015 if (nregs < 0)
6016 nregs = ~nregs;
64a0c779 6017 }
a724f0f4
JB		 6018 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6019 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6020 return 1;
4a1805b1 6021}
64a0c779
DN		 6022
6023/* e06 e09 e06'
6024
6025 e06' mulOp e09 e06'
b77a7acd 6026 | Empty */
64a0c779
DN		 6027static int
6028intel_e06 ()
6029{
a724f0f4 6030 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6031
a724f0f4 6032 for (;;)
64a0c779 6033 {
a724f0f4
JB		 6034 if (!intel_e09())
6035 return 0;
9306ca4a 6036
a724f0f4
JB		 6037 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6038 {
6039 char str[2];
9306ca4a 6040
a724f0f4
JB		 6041 str[0] = cur_token.code;
6042 str[1] = 0;
6043 strcat (intel_parser.disp, str);
6044 }
6045 else if (cur_token.code == T_SHL)
6046 strcat (intel_parser.disp, "<<");
6047 else if (cur_token.code == T_SHR)
6048 strcat (intel_parser.disp, ">>");
6049 else
6050 break;
9306ca4a 6051
a724f0f4 6052 intel_match_token (cur_token.code);
64a0c779 6053
a724f0f4
JB		 6054 if (nregs < 0)
6055 nregs = ~nregs;
64a0c779 6056 }
a724f0f4
JB		 6057 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6058 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6059 return 1;
64a0c779
DN		 6060}
6061
a724f0f4
JB		 6062/* e09 OFFSET e09
6063 | SHORT e09
6064 | + e09
6065 | - e09
6066 | ~ e09
6067 | NOT e09
9306ca4a
JB		 6068 | e10 e09'
6069
64a0c779 6070 e09' PTR e10 e09'
b77a7acd 6071 | : e10 e09'
64a0c779
DN		 6072 | Empty */
6073static int
6074intel_e09 ()
6075{
a724f0f4
JB		 6076 int nregs = ~NUM_ADDRESS_REGS;
6077 int in_offset = 0;
6078
6079 for (;;)
64a0c779 6080 {
a724f0f4
JB		 6081 /* Don't consume constants here. */
6082 if (cur_token.code == '+' || cur_token.code == '-')
6083 {
6084 /* Need to look one token ahead - if the next token
6085 is a constant, the current token is its sign. */
6086 int next_code;
6087
6088 intel_match_token (cur_token.code);
6089 next_code = cur_token.code;
6090 intel_putback_token ();
6091 if (next_code == T_CONST)
6092 break;
6093 }
6094
6095 /* e09 OFFSET e09 */
6096 if (cur_token.code == T_OFFSET)
6097 {
6098 if (!in_offset++)
6099 ++intel_parser.in_offset;
6100 }
6101
6102 /* e09 SHORT e09 */
6103 else if (cur_token.code == T_SHORT)
6104 intel_parser.op_modifier |= 1 << T_SHORT;
6105
6106 /* e09 + e09 */
6107 else if (cur_token.code == '+')
6108 strcat (intel_parser.disp, "+");
6109
6110 /* e09 - e09
6111 | ~ e09
6112 | NOT e09 */
6113 else if (cur_token.code == '-' || cur_token.code == '~')
6114 {
6115 char str[2];
64a0c779 6116
a724f0f4
JB		 6117 if (nregs < 0)
6118 nregs = ~nregs;
6119 str[0] = cur_token.code;
6120 str[1] = 0;
6121 strcat (intel_parser.disp, str);
6122 }
6123
6124 /* e09 e10 e09' */
6125 else
6126 break;
6127
6128 intel_match_token (cur_token.code);
64a0c779
DN		 6129 }
6130
a724f0f4 6131 for (;;)
9306ca4a 6132 {
a724f0f4
JB		 6133 if (!intel_e10 ())
6134 return 0;
9306ca4a 6135
a724f0f4
JB		 6136 /* e09' PTR e10 e09' */
6137 if (cur_token.code == T_PTR)
6138 {
6139 char suffix;
9306ca4a 6140
a724f0f4
JB		 6141 if (prev_token.code == T_BYTE)
6142 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6143
a724f0f4
JB		 6144 else if (prev_token.code == T_WORD)
6145 {
6146 if (current_templates->start->name[0] == 'l'
6147 && current_templates->start->name[2] == 's'
6148 && current_templates->start->name[3] == 0)
6149 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6150 else if (intel_parser.got_a_float == 2) /* "fi..." */
6151 suffix = SHORT_MNEM_SUFFIX;
6152 else
6153 suffix = WORD_MNEM_SUFFIX;
6154 }
64a0c779 6155
a724f0f4
JB		 6156 else if (prev_token.code == T_DWORD)
6157 {
6158 if (current_templates->start->name[0] == 'l'
6159 && current_templates->start->name[2] == 's'
6160 && current_templates->start->name[3] == 0)
6161 suffix = WORD_MNEM_SUFFIX;
6162 else if (flag_code == CODE_16BIT
6163 && (current_templates->start->opcode_modifier
435acd52 6164 & (Jump | JumpDword)))
a724f0f4
JB		 6165 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6166 else if (intel_parser.got_a_float == 1) /* "f..." */
6167 suffix = SHORT_MNEM_SUFFIX;
6168 else
6169 suffix = LONG_MNEM_SUFFIX;
6170 }
9306ca4a 6171
a724f0f4
JB		 6172 else if (prev_token.code == T_FWORD)
6173 {
6174 if (current_templates->start->name[0] == 'l'
6175 && current_templates->start->name[2] == 's'
6176 && current_templates->start->name[3] == 0)
6177 suffix = LONG_MNEM_SUFFIX;
6178 else if (!intel_parser.got_a_float)
6179 {
6180 if (flag_code == CODE_16BIT)
6181 add_prefix (DATA_PREFIX_OPCODE);
6182 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6183 }
6184 else
6185 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6186 }
64a0c779 6187
a724f0f4
JB		 6188 else if (prev_token.code == T_QWORD)
6189 {
6190 if (intel_parser.got_a_float == 1) /* "f..." */
6191 suffix = LONG_MNEM_SUFFIX;
6192 else
6193 suffix = QWORD_MNEM_SUFFIX;
6194 }
64a0c779 6195
a724f0f4
JB		 6196 else if (prev_token.code == T_TBYTE)
6197 {
6198 if (intel_parser.got_a_float == 1)
6199 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6200 else
6201 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6202 }
9306ca4a 6203
a724f0f4 6204 else if (prev_token.code == T_XMMWORD)
9306ca4a 6205 {
a724f0f4
JB		 6206 /* XXX ignored for now, but accepted since gcc uses it */
6207 suffix = 0;
9306ca4a 6208 }
64a0c779 6209
f16b83df 6210 else
a724f0f4
JB		 6211 {
6212 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6213 return 0;
6214 }
6215
435acd52
JB		 6216 /* Operands for jump/call using 'ptr' notation denote absolute
6217 addresses. */
6218 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6219 i.types[this_operand] |= JumpAbsolute;
6220
a724f0f4
JB		 6221 if (current_templates->start->base_opcode == 0x8d /* lea */)
6222 ;
6223 else if (!i.suffix)
6224 i.suffix = suffix;
6225 else if (i.suffix != suffix)
6226 {
6227 as_bad (_("Conflicting operand modifiers"));
6228 return 0;
6229 }
64a0c779 6230
9306ca4a
JB		 6231 }
6232
a724f0f4
JB		 6233 /* e09' : e10 e09' */
6234 else if (cur_token.code == ':')
9306ca4a 6235 {
a724f0f4
JB		 6236 if (prev_token.code != T_REG)
6237 {
6238 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6239 segment/group identifier (which we don't have), using comma
6240 as the operand separator there is even less consistent, since
6241 there all branches only have a single operand. */
6242 if (this_operand != 0
6243 || intel_parser.in_offset
6244 || intel_parser.in_bracket
6245 || (!(current_templates->start->opcode_modifier
6246 & (Jump|JumpDword|JumpInterSegment))
6247 && !(current_templates->start->operand_types[0]
6248 & JumpAbsolute)))
6249 return intel_match_token (T_NIL);
6250 /* Remember the start of the 2nd operand and terminate 1st
6251 operand here.
6252 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6253 another expression), but it gets at least the simplest case
6254 (a plain number or symbol on the left side) right. */
6255 intel_parser.next_operand = intel_parser.op_string;
6256 *--intel_parser.op_string = '\0';
6257 return intel_match_token (':');
6258 }
9306ca4a 6259 }
64a0c779 6260
a724f0f4 6261 /* e09' Empty */
64a0c779 6262 else
a724f0f4 6263 break;
64a0c779 6264
a724f0f4
JB		 6265 intel_match_token (cur_token.code);
6266
6267 }
6268
6269 if (in_offset)
6270 {
6271 --intel_parser.in_offset;
6272 if (nregs < 0)
6273 nregs = ~nregs;
6274 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 6275 {
a724f0f4 6276 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 6277 return 0;
6278 }
a724f0f4
JB		 6279 intel_parser.op_modifier |= 1 << T_OFFSET;
6280 }
9306ca4a 6281
a724f0f4
JB		 6282 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6283 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
6284 return 1;
6285}
64a0c779 6286
a724f0f4
JB		 6287static int
6288intel_bracket_expr ()
6289{
6290 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
6291 const char *start = intel_parser.op_string;
6292 int len;
6293
6294 if (i.op[this_operand].regs)
6295 return intel_match_token (T_NIL);
6296
6297 intel_match_token ('[');
6298
6299 /* Mark as a memory operand only if it's not already known to be an
6300 offset expression. If it's an offset expression, we need to keep
6301 the brace in. */
6302 if (!intel_parser.in_offset)
6303 {
6304 ++intel_parser.in_bracket;
435acd52
JB		 6305
6306 /* Operands for jump/call inside brackets denote absolute addresses. */
6307 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6308 i.types[this_operand] |= JumpAbsolute;
6309
a724f0f4
JB		 6310 /* Unfortunately gas always diverged from MASM in a respect that can't
6311 be easily fixed without risking to break code sequences likely to be
6312 encountered (the testsuite even check for this): MASM doesn't consider
6313 an expression inside brackets unconditionally as a memory reference.
6314 When that is e.g. a constant, an offset expression, or the sum of the
6315 two, this is still taken as a constant load. gas, however, always
6316 treated these as memory references. As a compromise, we'll try to make
6317 offset expressions inside brackets work the MASM way (since that's
6318 less likely to be found in real world code), but make constants alone
6319 continue to work the traditional gas way. In either case, issue a
6320 warning. */
6321 intel_parser.op_modifier &= ~was_offset;
64a0c779 6322 }
a724f0f4
JB		 6323 else
6324 strcat (intel_parser.disp, "[");
6325
6326 /* Add a '+' to the displacement string if necessary. */
6327 if (*intel_parser.disp != '\0'
6328 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
6329 strcat (intel_parser.disp, "+");
64a0c779 6330
a724f0f4
JB		 6331 if (intel_expr ()
6332 && (len = intel_parser.op_string - start - 1,
6333 intel_match_token (']')))
64a0c779 6334 {
a724f0f4
JB		 6335 /* Preserve brackets when the operand is an offset expression. */
6336 if (intel_parser.in_offset)
6337 strcat (intel_parser.disp, "]");
6338 else
6339 {
6340 --intel_parser.in_bracket;
6341 if (i.base_reg || i.index_reg)
6342 intel_parser.is_mem = 1;
6343 if (!intel_parser.is_mem)
6344 {
6345 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
6346 /* Defer the warning until all of the operand was parsed. */
6347 intel_parser.is_mem = -1;
6348 else if (!quiet_warnings)
6349 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
6350 }
6351 }
6352 intel_parser.op_modifier |= was_offset;
64a0c779 6353
a724f0f4 6354 return 1;
64a0c779 6355 }
a724f0f4 6356 return 0;
64a0c779
DN		 6357}
6358
6359/* e10 e11 e10'
6360
6361 e10' [ expr ] e10'
b77a7acd 6362 | Empty */
64a0c779
DN		 6363static int
6364intel_e10 ()
6365{
a724f0f4
JB		 6366 if (!intel_e11 ())
6367 return 0;
64a0c779 6368
a724f0f4 6369 while (cur_token.code == '[')
64a0c779 6370 {
a724f0f4 6371 if (!intel_bracket_expr ())
21d6c4af 6372 return 0;
64a0c779
DN		 6373 }
6374
a724f0f4 6375 return 1;
64a0c779
DN		 6376}
6377
64a0c779 6378/* e11 ( expr )
b77a7acd 6379 | [ expr ]
64a0c779
DN		 6380 | BYTE
6381 | WORD
6382 | DWORD
9306ca4a 6383 | FWORD
64a0c779 6384 | QWORD
9306ca4a
JB		 6385 | TBYTE
6386 | OWORD
6387 | XMMWORD
4a1805b1 6388 | $
64a0c779
DN		 6389 | .
6390 | register
6391 | id
6392 | constant */
6393static int
6394intel_e11 ()
6395{
a724f0f4 6396 switch (cur_token.code)
64a0c779 6397 {
a724f0f4
JB		 6398 /* e11 ( expr ) */
6399 case '(':
64a0c779
DN		 6400 intel_match_token ('(');
6401 strcat (intel_parser.disp, "(");
6402
6403 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 6404 {
6405 strcat (intel_parser.disp, ")");
6406 return 1;
6407 }
a724f0f4 6408 return 0;
4a1805b1 6409
a724f0f4
JB		 6410 /* e11 [ expr ] */
6411 case '[':
a724f0f4 6412 return intel_bracket_expr ();
64a0c779 6413
a724f0f4
JB		 6414 /* e11 $
6415 | . */
6416 case '.':
64a0c779
DN		 6417 strcat (intel_parser.disp, cur_token.str);
6418 intel_match_token (cur_token.code);
21d6c4af
DN		 6419
6420 /* Mark as a memory operand only if it's not already known to be an
6421 offset expression. */
a724f0f4 6422 if (!intel_parser.in_offset)
21d6c4af 6423 intel_parser.is_mem = 1;
64a0c779
DN		 6424
6425 return 1;
64a0c779 6426
a724f0f4
JB		 6427 /* e11 register */
6428 case T_REG:
6429 {
6430 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 6431
a724f0f4 6432 intel_match_token (T_REG);
64a0c779 6433
a724f0f4
JB		 6434 /* Check for segment change. */
6435 if (cur_token.code == ':')
6436 {
6437 if (!(reg->reg_type & (SReg2 | SReg3)))
6438 {
6439 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
6440 return 0;
6441 }
6442 else if (i.seg[i.mem_operands])
6443 as_warn (_("Extra segment override ignored"));
6444 else
6445 {
6446 if (!intel_parser.in_offset)
6447 intel_parser.is_mem = 1;
6448 switch (reg->reg_num)
6449 {
6450 case 0:
6451 i.seg[i.mem_operands] = &es;
6452 break;
6453 case 1:
6454 i.seg[i.mem_operands] = &cs;
6455 break;
6456 case 2:
6457 i.seg[i.mem_operands] = &ss;
6458 break;
6459 case 3:
6460 i.seg[i.mem_operands] = &ds;
6461 break;
6462 case 4:
6463 i.seg[i.mem_operands] = &fs;
6464 break;
6465 case 5:
6466 i.seg[i.mem_operands] = &gs;
6467 break;
6468 }
6469 }
6470 }
64a0c779 6471
a724f0f4
JB		 6472 /* Not a segment register. Check for register scaling. */
6473 else if (cur_token.code == '*')
6474 {
6475 if (!intel_parser.in_bracket)
6476 {
6477 as_bad (_("Register scaling only allowed in memory operands"));
6478 return 0;
6479 }
64a0c779 6480
a724f0f4
JB		 6481 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
6482 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6483 else if (i.index_reg)
6484 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 6485
a724f0f4
JB		 6486 /* What follows must be a valid scale. */
6487 intel_match_token ('*');
6488 i.index_reg = reg;
6489 i.types[this_operand] |= BaseIndex;
64a0c779 6490
a724f0f4
JB		 6491 /* Set the scale after setting the register (otherwise,
6492 i386_scale will complain) */
6493 if (cur_token.code == '+' || cur_token.code == '-')
6494 {
6495 char *str, sign = cur_token.code;
6496 intel_match_token (cur_token.code);
6497 if (cur_token.code != T_CONST)
6498 {
6499 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6500 cur_token.str);
6501 return 0;
6502 }
6503 str = (char *) xmalloc (strlen (cur_token.str) + 2);
6504 strcpy (str + 1, cur_token.str);
6505 *str = sign;
6506 if (!i386_scale (str))
6507 return 0;
6508 free (str);
6509 }
6510 else if (!i386_scale (cur_token.str))
64a0c779 6511 return 0;
a724f0f4
JB		 6512 intel_match_token (cur_token.code);
6513 }
64a0c779 6514
a724f0f4
JB		 6515 /* No scaling. If this is a memory operand, the register is either a
6516 base register (first occurrence) or an index register (second
6517 occurrence). */
6518 else if (intel_parser.in_bracket && !(reg->reg_type & (SReg2 | SReg3)))
6519 {
64a0c779 6520
a724f0f4
JB		 6521 if (!i.base_reg)
6522 i.base_reg = reg;
6523 else if (!i.index_reg)
6524 i.index_reg = reg;
6525 else
6526 {
6527 as_bad (_("Too many register references in memory operand"));
6528 return 0;
6529 }
64a0c779 6530
a724f0f4
JB		 6531 i.types[this_operand] |= BaseIndex;
6532 }
4a1805b1 6533
a724f0f4
JB		 6534 /* Offset modifier. Add the register to the displacement string to be
6535 parsed as an immediate expression after we're done. */
6536 else if (intel_parser.in_offset)
6537 {
6538 as_warn (_("Using register names in OFFSET expressions is deprecated"));
6539 strcat (intel_parser.disp, reg->reg_name);
6540 }
64a0c779 6541
a724f0f4
JB		 6542 /* It's neither base nor index nor offset. */
6543 else if (!intel_parser.is_mem)
6544 {
6545 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
6546 i.op[this_operand].regs = reg;
6547 i.reg_operands++;
6548 }
6549 else
6550 {
6551 as_bad (_("Invalid use of register"));
6552 return 0;
6553 }
64a0c779 6554
a724f0f4
JB		 6555 /* Since registers are not part of the displacement string (except
6556 when we're parsing offset operands), we may need to remove any
6557 preceding '+' from the displacement string. */
6558 if (*intel_parser.disp != '\0'
6559 && !intel_parser.in_offset)
6560 {
6561 char *s = intel_parser.disp;
6562 s += strlen (s) - 1;
6563 if (*s == '+')
6564 *s = '\0';
6565 }
4a1805b1 6566
a724f0f4
JB		 6567 return 1;
6568 }
6569
6570 /* e11 BYTE
6571 | WORD
6572 | DWORD
6573 | FWORD
6574 | QWORD
6575 | TBYTE
6576 | OWORD
6577 | XMMWORD */
6578 case T_BYTE:
6579 case T_WORD:
6580 case T_DWORD:
6581 case T_FWORD:
6582 case T_QWORD:
6583 case T_TBYTE:
6584 case T_XMMWORD:
6585 intel_match_token (cur_token.code);
64a0c779 6586
a724f0f4
JB		 6587 if (cur_token.code == T_PTR)
6588 return 1;
6589
6590 /* It must have been an identifier. */
6591 intel_putback_token ();
6592 cur_token.code = T_ID;
6593 /* FALLTHRU */
6594
6595 /* e11 id
6596 | constant */
6597 case T_ID:
6598 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 6599 {
6600 symbolS *symbolP;
6601
a724f0f4
JB		 6602 /* The identifier represents a memory reference only if it's not
6603 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 6604 symbolP = symbol_find(cur_token.str);
6605 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
6606 intel_parser.is_mem = 1;
6607 }
a724f0f4 6608 /* FALLTHRU */
64a0c779 6609
a724f0f4
JB		 6610 case T_CONST:
6611 case '-':
6612 case '+':
6613 {
6614 char *save_str, sign = 0;
64a0c779 6615
a724f0f4
JB		 6616 /* Allow constants that start with `+' or `-'. */
6617 if (cur_token.code == '-' || cur_token.code == '+')
6618 {
6619 sign = cur_token.code;
6620 intel_match_token (cur_token.code);
6621 if (cur_token.code != T_CONST)
6622 {
6623 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6624 cur_token.str);
6625 return 0;
6626 }
6627 }
64a0c779 6628
a724f0f4
JB		 6629 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
6630 strcpy (save_str + !!sign, cur_token.str);
6631 if (sign)
6632 *save_str = sign;
64a0c779 6633
a724f0f4
JB		 6634 /* Get the next token to check for register scaling. */
6635 intel_match_token (cur_token.code);
64a0c779 6636
a724f0f4
JB		 6637 /* Check if this constant is a scaling factor for an index register. */
6638 if (cur_token.code == '*')
6639 {
6640 if (intel_match_token ('*') && cur_token.code == T_REG)
6641 {
6642 const reg_entry *reg = cur_token.reg;
6643
6644 if (!intel_parser.in_bracket)
6645 {
6646 as_bad (_("Register scaling only allowed in memory operands"));
6647 return 0;
6648 }
6649
6650 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
6651 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6652 else if (i.index_reg)
6653 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
6654
6655 /* The constant is followed by `* reg', so it must be
6656 a valid scale. */
6657 i.index_reg = reg;
6658 i.types[this_operand] |= BaseIndex;
6659
6660 /* Set the scale after setting the register (otherwise,
6661 i386_scale will complain) */
6662 if (!i386_scale (save_str))
64a0c779 6663 return 0;
a724f0f4
JB		 6664 intel_match_token (T_REG);
6665
6666 /* Since registers are not part of the displacement
6667 string, we may need to remove any preceding '+' from
6668 the displacement string. */
6669 if (*intel_parser.disp != '\0')
6670 {
6671 char *s = intel_parser.disp;
6672 s += strlen (s) - 1;
6673 if (*s == '+')
6674 *s = '\0';
6675 }
6676
6677 free (save_str);
6678
6679 return 1;
6680 }
64a0c779 6681
a724f0f4
JB		 6682 /* The constant was not used for register scaling. Since we have
6683 already consumed the token following `*' we now need to put it
6684 back in the stream. */
64a0c779 6685 intel_putback_token ();
a724f0f4 6686 }
64a0c779 6687
a724f0f4
JB		 6688 /* Add the constant to the displacement string. */
6689 strcat (intel_parser.disp, save_str);
6690 free (save_str);
64a0c779 6691
a724f0f4
JB		 6692 return 1;
6693 }
64a0c779
DN		 6694 }
6695
64a0c779
DN		 6696 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6697 return 0;
6698}
6699
64a0c779
DN		 6700/* Match the given token against cur_token. If they match, read the next
6701 token from the operand string. */
6702static int
6703intel_match_token (code)
e5cb08ac 6704 int code;
64a0c779
DN		 6705{
6706 if (cur_token.code == code)
6707 {
6708 intel_get_token ();
6709 return 1;
6710 }
6711 else
6712 {
0477af35 6713 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 6714 return 0;
6715 }
6716}
6717
64a0c779
DN		 6718/* Read a new token from intel_parser.op_string and store it in cur_token. */
6719static void
6720intel_get_token ()
6721{
6722 char *end_op;
6723 const reg_entry *reg;
6724 struct intel_token new_token;
6725
6726 new_token.code = T_NIL;
6727 new_token.reg = NULL;
6728 new_token.str = NULL;
6729
4a1805b1 6730 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6731 cur_token to prev_token. */
6732 if (prev_token.str)
6733 free (prev_token.str);
6734
6735 prev_token = cur_token;
6736
6737 /* Skip whitespace. */
6738 while (is_space_char (*intel_parser.op_string))
6739 intel_parser.op_string++;
6740
6741 /* Return an empty token if we find nothing else on the line. */
6742 if (*intel_parser.op_string == '\0')
6743 {
6744 cur_token = new_token;
6745 return;
6746 }
6747
6748 /* The new token cannot be larger than the remainder of the operand
6749 string. */
a724f0f4 6750 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 6751 new_token.str[0] = '\0';
6752
6753 if (strchr ("0123456789", *intel_parser.op_string))
6754 {
6755 char *p = new_token.str;
6756 char *q = intel_parser.op_string;
6757 new_token.code = T_CONST;
6758
6759 /* Allow any kind of identifier char to encompass floating point and
6760 hexadecimal numbers. */
6761 while (is_identifier_char (*q))
6762 *p++ = *q++;
6763 *p = '\0';
6764
6765 /* Recognize special symbol names [0-9][bf]. */
6766 if (strlen (intel_parser.op_string) == 2
4a1805b1 6767 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6768 || intel_parser.op_string[1] == 'f'))
6769 new_token.code = T_ID;
6770 }
6771
64a0c779
DN		 6772 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6773 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6774 {
6775 new_token.code = T_REG;
6776 new_token.reg = reg;
6777
6778 if (*intel_parser.op_string == REGISTER_PREFIX)
6779 {
6780 new_token.str[0] = REGISTER_PREFIX;
6781 new_token.str[1] = '\0';
6782 }
6783
6784 strcat (new_token.str, reg->reg_name);
6785 }
6786
6787 else if (is_identifier_char (*intel_parser.op_string))
6788 {
6789 char *p = new_token.str;
6790 char *q = intel_parser.op_string;
6791
6792 /* A '.' or '$' followed by an identifier char is an identifier.
6793 Otherwise, it's operator '.' followed by an expression. */
6794 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6795 {
9306ca4a
JB		 6796 new_token.code = '.';
6797 new_token.str[0] = '.';
64a0c779
DN		 6798 new_token.str[1] = '\0';
6799 }
6800 else
6801 {
6802 while (is_identifier_char (*q) || *q == '@')
6803 *p++ = *q++;
6804 *p = '\0';
6805
9306ca4a
JB		 6806 if (strcasecmp (new_token.str, "NOT") == 0)
6807 new_token.code = '~';
6808
6809 else if (strcasecmp (new_token.str, "MOD") == 0)
6810 new_token.code = '%';
6811
6812 else if (strcasecmp (new_token.str, "AND") == 0)
6813 new_token.code = '&';
6814
6815 else if (strcasecmp (new_token.str, "OR") == 0)
6816 new_token.code = '|';
6817
6818 else if (strcasecmp (new_token.str, "XOR") == 0)
6819 new_token.code = '^';
6820
6821 else if (strcasecmp (new_token.str, "SHL") == 0)
6822 new_token.code = T_SHL;
6823
6824 else if (strcasecmp (new_token.str, "SHR") == 0)
6825 new_token.code = T_SHR;
6826
6827 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 6828 new_token.code = T_BYTE;
6829
6830 else if (strcasecmp (new_token.str, "WORD") == 0)
6831 new_token.code = T_WORD;
6832
6833 else if (strcasecmp (new_token.str, "DWORD") == 0)
6834 new_token.code = T_DWORD;
6835
9306ca4a
JB		 6836 else if (strcasecmp (new_token.str, "FWORD") == 0)
6837 new_token.code = T_FWORD;
6838
64a0c779
DN		 6839 else if (strcasecmp (new_token.str, "QWORD") == 0)
6840 new_token.code = T_QWORD;
6841
9306ca4a
JB		 6842 else if (strcasecmp (new_token.str, "TBYTE") == 0
6843 /* XXX remove (gcc still uses it) */
6844 || strcasecmp (new_token.str, "XWORD") == 0)
6845 new_token.code = T_TBYTE;
6846
6847 else if (strcasecmp (new_token.str, "XMMWORD") == 0
6848 || strcasecmp (new_token.str, "OWORD") == 0)
6849 new_token.code = T_XMMWORD;
64a0c779
DN		 6850
6851 else if (strcasecmp (new_token.str, "PTR") == 0)
6852 new_token.code = T_PTR;
6853
6854 else if (strcasecmp (new_token.str, "SHORT") == 0)
6855 new_token.code = T_SHORT;
6856
6857 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6858 {
6859 new_token.code = T_OFFSET;
6860
6861 /* ??? This is not mentioned in the MASM grammar but gcc
6862 makes use of it with -mintel-syntax. OFFSET may be
6863 followed by FLAT: */
6864 if (strncasecmp (q, " FLAT:", 6) == 0)
6865 strcat (new_token.str, " FLAT:");
6866 }
6867
6868 /* ??? This is not mentioned in the MASM grammar. */
6869 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 6870 {
6871 new_token.code = T_OFFSET;
6872 if (*q == ':')
6873 strcat (new_token.str, ":");
6874 else
6875 as_bad (_("`:' expected"));
6876 }
64a0c779
DN		 6877
6878 else
6879 new_token.code = T_ID;
6880 }
6881 }
6882
9306ca4a
JB		 6883 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
6884 {
6885 new_token.code = *intel_parser.op_string;
6886 new_token.str[0] = *intel_parser.op_string;
6887 new_token.str[1] = '\0';
6888 }
6889
6890 else if (strchr ("<>", *intel_parser.op_string)
6891 && *intel_parser.op_string == *(intel_parser.op_string + 1))
6892 {
6893 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
6894 new_token.str[0] = *intel_parser.op_string;
6895 new_token.str[1] = *intel_parser.op_string;
6896 new_token.str[2] = '\0';
6897 }
6898
64a0c779 6899 else
0477af35 6900 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 6901
6902 intel_parser.op_string += strlen (new_token.str);
6903 cur_token = new_token;
6904}
6905
64a0c779
DN		 6906/* Put cur_token back into the token stream and make cur_token point to
6907 prev_token. */
6908static void
6909intel_putback_token ()
6910{
a724f0f4
JB		 6911 if (cur_token.code != T_NIL)
6912 {
6913 intel_parser.op_string -= strlen (cur_token.str);
6914 free (cur_token.str);
6915 }
64a0c779 6916 cur_token = prev_token;
4a1805b1 6917
64a0c779
DN		 6918 /* Forget prev_token. */
6919 prev_token.code = T_NIL;
6920 prev_token.reg = NULL;
6921 prev_token.str = NULL;
6922}
54cfded0 6923
a4447b93 6924int
54cfded0
AM		 6925tc_x86_regname_to_dw2regnum (const char *regname)
6926{
6927 unsigned int regnum;
6928 unsigned int regnames_count;
089dfecd 6929 static const char *const regnames_32[] =
54cfded0 6930 {
a4447b93
RH		 6931 "eax", "ecx", "edx", "ebx",
6932 "esp", "ebp", "esi", "edi",
089dfecd
JB		 6933 "eip", "eflags", NULL,
6934 "st0", "st1", "st2", "st3",
6935 "st4", "st5", "st6", "st7",
6936 NULL, NULL,
6937 "xmm0", "xmm1", "xmm2", "xmm3",
6938 "xmm4", "xmm5", "xmm6", "xmm7",
6939 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 6940 "mm4", "mm5", "mm6", "mm7",
6941 "fcw", "fsw", "mxcsr",
6942 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
6943 "tr", "ldtr"
54cfded0 6944 };
089dfecd 6945 static const char *const regnames_64[] =
54cfded0 6946 {
089dfecd
JB		 6947 "rax", "rdx", "rcx", "rbx",
6948 "rsi", "rdi", "rbp", "rsp",
6949 "r8", "r9", "r10", "r11",
54cfded0 6950 "r12", "r13", "r14", "r15",
089dfecd
JB		 6951 "rip",
6952 "xmm0", "xmm1", "xmm2", "xmm3",
6953 "xmm4", "xmm5", "xmm6", "xmm7",
6954 "xmm8", "xmm9", "xmm10", "xmm11",
6955 "xmm12", "xmm13", "xmm14", "xmm15",
6956 "st0", "st1", "st2", "st3",
6957 "st4", "st5", "st6", "st7",
6958 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 6959 "mm4", "mm5", "mm6", "mm7",
6960 "rflags",
6961 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
6962 "fs.base", "gs.base", NULL, NULL,
6963 "tr", "ldtr",
6964 "mxcsr", "fcw", "fsw"
54cfded0 6965 };
089dfecd 6966 const char *const *regnames;
54cfded0
AM		 6967
6968 if (flag_code == CODE_64BIT)
6969 {
6970 regnames = regnames_64;
0cea6190 6971 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 6972 }
6973 else
6974 {
6975 regnames = regnames_32;
0cea6190 6976 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 6977 }
6978
6979 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 6980 if (regnames[regnum] != NULL
6981 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 6982 return regnum;
6983
54cfded0
AM		 6984 return -1;
6985}
6986
6987void
6988tc_x86_frame_initial_instructions (void)
6989{
a4447b93
RH		 6990 static unsigned int sp_regno;
6991
6992 if (!sp_regno)
6993 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
6994 ? "rsp" : "esp");
6995
6996 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
6997 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 6998}
d2b2c203
DJ		 6999
7000int
7001i386_elf_section_type (const char *str, size_t len)
7002{
7003 if (flag_code == CODE_64BIT
7004 && len == sizeof ("unwind") - 1
7005 && strncmp (str, "unwind", 6) == 0)
7006 return SHT_X86_64_UNWIND;
7007
7008 return -1;
7009}
bb41ade5
AM		 7010
7011#ifdef TE_PE
7012void
7013tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7014{
7015 expressionS expr;
7016
7017 expr.X_op = O_secrel;
7018 expr.X_add_symbol = symbol;
7019 expr.X_add_number = 0;
7020 emit_expr (&expr, size);
7021}
7022#endif
3b22753a
L		 7023
7024#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7025/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7026
7027int
7028x86_64_section_letter (int letter, char **ptr_msg)
7029{
7030 if (flag_code == CODE_64BIT)
7031 {
7032 if (letter == 'l')
7033 return SHF_X86_64_LARGE;
7034
7035 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7036 }
7037 else
7038 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
7039 return -1;
7040}
7041
7042int
7043x86_64_section_word (char *str, size_t len)
7044{
7045 if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
7046 return SHF_X86_64_LARGE;
7047
7048 return -1;
7049}
7050
7051static void
7052handle_large_common (int small ATTRIBUTE_UNUSED)
7053{
7054 if (flag_code != CODE_64BIT)
7055 {
7056 s_comm_internal (0, elf_common_parse);
7057 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7058 }
7059 else
7060 {
7061 static segT lbss_section;
7062 asection *saved_com_section_ptr = elf_com_section_ptr;
7063 asection *saved_bss_section = bss_section;
7064
7065 if (lbss_section == NULL)
7066 {
7067 flagword applicable;
7068 segT seg = now_seg;
7069 subsegT subseg = now_subseg;
7070
7071 /* The .lbss section is for local .largecomm symbols. */
7072 lbss_section = subseg_new (".lbss", 0);
7073 applicable = bfd_applicable_section_flags (stdoutput);
7074 bfd_set_section_flags (stdoutput, lbss_section,
7075 applicable & SEC_ALLOC);
7076 seg_info (lbss_section)->bss = 1;
7077
7078 subseg_set (seg, subseg);
7079 }
7080
7081 elf_com_section_ptr = &_bfd_elf_large_com_section;
7082 bss_section = lbss_section;
7083
7084 s_comm_internal (0, elf_common_parse);
7085
7086 elf_com_section_ptr = saved_com_section_ptr;
7087 bss_section = saved_bss_section;
7088 }
7089}
7090#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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