projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Fix name of ser_base_setstopbits's second argument.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
b90efa5b 2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
89e7505f
L		 36#ifdef TE_LINUX
37/* Default to compress debug sections for Linux. */
38int flag_compress_debug = 1;
39#endif
40
252b5132
RH		 41#ifndef REGISTER_WARNINGS
42#define REGISTER_WARNINGS 1
43#endif
44
c3332e24 45#ifndef INFER_ADDR_PREFIX
eecb386c 46#define INFER_ADDR_PREFIX 1
c3332e24
AM		 47#endif
48
29b0f896
AM		 49#ifndef DEFAULT_ARCH
50#define DEFAULT_ARCH "i386"
246fcdee 51#endif
252b5132 52
edde18a5
AM		 53#ifndef INLINE
54#if __GNUC__ >= 2
55#define INLINE __inline__
56#else
57#define INLINE
58#endif
59#endif
60
6305a203
L		 61/* Prefixes will be emitted in the order defined below.
62 WAIT_PREFIX must be the first prefix since FWAIT is really is an
63 instruction, and so must come before any prefixes.
64 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 65 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 66#define WAIT_PREFIX 0
67#define SEG_PREFIX 1
68#define ADDR_PREFIX 2
69#define DATA_PREFIX 3
c32fa91d 70#define REP_PREFIX 4
42164a71 71#define HLE_PREFIX REP_PREFIX
7e8b059b 72#define BND_PREFIX REP_PREFIX
c32fa91d
L		 73#define LOCK_PREFIX 5
74#define REX_PREFIX 6 /* must come last. */
75#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 76
77/* we define the syntax here (modulo base,index,scale syntax) */
78#define REGISTER_PREFIX '%'
79#define IMMEDIATE_PREFIX '$'
80#define ABSOLUTE_PREFIX '*'
81
82/* these are the instruction mnemonic suffixes in AT&T syntax or
83 memory operand size in Intel syntax. */
84#define WORD_MNEM_SUFFIX 'w'
85#define BYTE_MNEM_SUFFIX 'b'
86#define SHORT_MNEM_SUFFIX 's'
87#define LONG_MNEM_SUFFIX 'l'
88#define QWORD_MNEM_SUFFIX 'q'
89#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 90#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 91#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 92/* Intel Syntax. Use a non-ascii letter since since it never appears
93 in instructions. */
94#define LONG_DOUBLE_MNEM_SUFFIX '\1'
95
96#define END_OF_INSN '\0'
97
98/*
99 'templates' is for grouping together 'template' structures for opcodes
100 of the same name. This is only used for storing the insns in the grand
101 ole hash table of insns.
102 The templates themselves start at START and range up to (but not including)
103 END.
104 */
105typedef struct
106{
d3ce72d0
NC		 107 const insn_template *start;
108 const insn_template *end;
6305a203
L		 109}
110templates;
111
112/* 386 operand encoding bytes: see 386 book for details of this. */
113typedef struct
114{
115 unsigned int regmem; /* codes register or memory operand */
116 unsigned int reg; /* codes register operand (or extended opcode) */
117 unsigned int mode; /* how to interpret regmem & reg */
118}
119modrm_byte;
120
121/* x86-64 extension prefix. */
122typedef int rex_byte;
123
6305a203
L		 124/* 386 opcode byte to code indirect addressing. */
125typedef struct
126{
127 unsigned base;
128 unsigned index;
129 unsigned scale;
130}
131sib_byte;
132
6305a203
L		 133/* x86 arch names, types and features */
134typedef struct
135{
136 const char *name; /* arch name */
8a2c8fef 137 unsigned int len; /* arch string length */
6305a203
L		 138 enum processor_type type; /* arch type */
139 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 140 unsigned int skip; /* show_arch should skip this. */
22109423 141 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 142}
143arch_entry;
144
78f12dd3 145static void update_code_flag (int, int);
e3bb37b5
L		 146static void set_code_flag (int);
147static void set_16bit_gcc_code_flag (int);
148static void set_intel_syntax (int);
1efbbeb4 149static void set_intel_mnemonic (int);
db51cc60 150static void set_allow_index_reg (int);
7bab8ab5 151static void set_check (int);
e3bb37b5 152static void set_cpu_arch (int);
6482c264 153#ifdef TE_PE
e3bb37b5 154static void pe_directive_secrel (int);
6482c264 155#endif
e3bb37b5
L		 156static void signed_cons (int);
157static char *output_invalid (int c);
ee86248c
JB		 158static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
159 const char *);
160static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
161 const char *);
a7619375 162static int i386_att_operand (char *);
e3bb37b5 163static int i386_intel_operand (char *, int);
ee86248c
JB		 164static int i386_intel_simplify (expressionS *);
165static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 166static const reg_entry *parse_register (char *, char **);
167static char *parse_insn (char *, char *);
168static char *parse_operands (char *, const char *);
169static void swap_operands (void);
4d456e3d 170static void swap_2_operands (int, int);
e3bb37b5
L		 171static void optimize_imm (void);
172static void optimize_disp (void);
d3ce72d0 173static const insn_template *match_template (void);
e3bb37b5
L		 174static int check_string (void);
175static int process_suffix (void);
176static int check_byte_reg (void);
177static int check_long_reg (void);
178static int check_qword_reg (void);
179static int check_word_reg (void);
180static int finalize_imm (void);
181static int process_operands (void);
182static const seg_entry *build_modrm_byte (void);
183static void output_insn (void);
184static void output_imm (fragS *, offsetT);
185static void output_disp (fragS *, offsetT);
29b0f896 186#ifndef I386COFF
e3bb37b5 187static void s_bss (int);
252b5132 188#endif
17d4e2a2
L		 189#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190static void handle_large_common (int small ATTRIBUTE_UNUSED);
191#endif
252b5132 192
a847613f 193static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 194
43234a1e
L		 195/* This struct describes rounding control and SAE in the instruction. */
196struct RC_Operation
197{
198 enum rc_type
199 {
200 rne = 0,
201 rd,
202 ru,
203 rz,
204 saeonly
205 } type;
206 int operand;
207};
208
209static struct RC_Operation rc_op;
210
211/* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214struct Mask_Operation
215{
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
219 int operand;
220};
221
222static struct Mask_Operation mask_op;
223
224/* The struct describes broadcasting, applied to OPERAND. FACTOR is
225 broadcast factor. */
226struct Broadcast_Operation
227{
228 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
229 int type;
230
231 /* Index of broadcasted operand. */
232 int operand;
233};
234
235static struct Broadcast_Operation broadcast_op;
236
c0f3af97
L		 237/* VEX prefix. */
238typedef struct
239{
43234a1e
L		 240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
c0f3af97
L		 242 unsigned int length;
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
245} vex_prefix;
246
252b5132 247/* 'md_assemble ()' gathers together information and puts it into a
47926f60 248 i386_insn. */
252b5132 249
520dc8e8
AM		 250union i386_op
251 {
252 expressionS *disps;
253 expressionS *imms;
254 const reg_entry *regs;
255 };
256
a65babc9
L		 257enum i386_error
258 {
86e026a4 259 operand_size_mismatch,
a65babc9
L		 260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
264 bad_imm4,
265 old_gcc_only,
266 unsupported_with_intel_mnemonic,
267 unsupported_syntax,
6c30d220
L		 268 unsupported,
269 invalid_vsib_address,
7bab8ab5 270 invalid_vector_register_set,
43234a1e
L		 271 unsupported_vector_index_register,
272 unsupported_broadcast,
273 broadcast_not_on_src_operand,
274 broadcast_needed,
275 unsupported_masking,
276 mask_not_on_destination,
277 no_default_mask,
278 unsupported_rc_sae,
279 rc_sae_operand_not_last_imm,
280 invalid_register_operand,
281 try_vector_disp8
a65babc9
L		 282 };
283
252b5132
RH		 284struct _i386_insn
285 {
47926f60 286 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 287 insn_template tm;
252b5132 288
7d5e4556
L		 289 /* SUFFIX holds the instruction size suffix for byte, word, dword
290 or qword, if given. */
252b5132
RH		 291 char suffix;
292
47926f60 293 /* OPERANDS gives the number of given operands. */
252b5132
RH		 294 unsigned int operands;
295
296 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
297 of given register, displacement, memory operands and immediate
47926f60 298 operands. */
252b5132
RH		 299 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
300
301 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 302 use OP[i] for the corresponding operand. */
40fb9820 303 i386_operand_type types[MAX_OPERANDS];
252b5132 304
520dc8e8
AM		 305 /* Displacement expression, immediate expression, or register for each
306 operand. */
307 union i386_op op[MAX_OPERANDS];
252b5132 308
3e73aa7c
JH		 309 /* Flags for operands. */
310 unsigned int flags[MAX_OPERANDS];
311#define Operand_PCrel 1
312
252b5132 313 /* Relocation type for operand */
f86103b7 314 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 315
252b5132
RH		 316 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
317 the base index byte below. */
318 const reg_entry *base_reg;
319 const reg_entry *index_reg;
320 unsigned int log2_scale_factor;
321
322 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 323 explicit segment overrides are given. */
ce8a8b2f 324 const seg_entry *seg[2];
252b5132
RH		 325
326 /* PREFIX holds all the given prefix opcodes (usually null).
327 PREFIXES is the number of prefix opcodes. */
328 unsigned int prefixes;
329 unsigned char prefix[MAX_PREFIXES];
330
331 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 332 addressing modes of this insn are encoded. */
252b5132 333 modrm_byte rm;
3e73aa7c 334 rex_byte rex;
43234a1e 335 rex_byte vrex;
252b5132 336 sib_byte sib;
c0f3af97 337 vex_prefix vex;
b6169b20 338
43234a1e
L		 339 /* Masking attributes. */
340 struct Mask_Operation *mask;
341
342 /* Rounding control and SAE attributes. */
343 struct RC_Operation *rounding;
344
345 /* Broadcasting attributes. */
346 struct Broadcast_Operation *broadcast;
347
348 /* Compressed disp8*N attribute. */
349 unsigned int memshift;
350
b6169b20 351 /* Swap operand in encoding. */
4473e004 352 unsigned int swap_operand;
891edac4 353
a501d77e
L		 354 /* Prefer 8bit or 32bit displacement in encoding. */
355 enum
356 {
357 disp_encoding_default = 0,
358 disp_encoding_8bit,
359 disp_encoding_32bit
360 } disp_encoding;
f8a5c266 361
d5de92cf
L		 362 /* REP prefix. */
363 const char *rep_prefix;
364
165de32a
L		 365 /* HLE prefix. */
366 const char *hle_prefix;
42164a71 367
7e8b059b
L		 368 /* Have BND prefix. */
369 const char *bnd_prefix;
370
43234a1e
L		 371 /* Need VREX to support upper 16 registers. */
372 int need_vrex;
373
891edac4 374 /* Error message. */
a65babc9 375 enum i386_error error;
252b5132
RH		 376 };
377
378typedef struct _i386_insn i386_insn;
379
43234a1e
L		 380/* Link RC type with corresponding string, that'll be looked for in
381 asm. */
382struct RC_name
383{
384 enum rc_type type;
385 const char *name;
386 unsigned int len;
387};
388
389static const struct RC_name RC_NamesTable[] =
390{
391 { rne, STRING_COMMA_LEN ("rn-sae") },
392 { rd, STRING_COMMA_LEN ("rd-sae") },
393 { ru, STRING_COMMA_LEN ("ru-sae") },
394 { rz, STRING_COMMA_LEN ("rz-sae") },
395 { saeonly, STRING_COMMA_LEN ("sae") },
396};
397
252b5132
RH		 398/* List of chars besides those in app.c:symbol_chars that can start an
399 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 400const char extra_symbol_chars[] = "*%-([{"
252b5132 401#ifdef LEX_AT
32137342
NC		 402 "@"
403#endif
404#ifdef LEX_QM
405 "?"
252b5132 406#endif
32137342 407 ;
252b5132 408
29b0f896
AM		 409#if (defined (TE_I386AIX) \
410 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 411 && !defined (TE_GNU) \
29b0f896 412 && !defined (TE_LINUX) \
8d63c93e
RM		 413 && !defined (TE_NACL) \
414 && !defined (TE_NETWARE) \
29b0f896 415 && !defined (TE_FreeBSD) \
5b806d27 416 && !defined (TE_DragonFly) \
29b0f896 417 && !defined (TE_NetBSD)))
252b5132 418/* This array holds the chars that always start a comment. If the
b3b91714
AM		 419 pre-processor is disabled, these aren't very useful. The option
420 --divide will remove '/' from this list. */
421const char *i386_comment_chars = "#/";
422#define SVR4_COMMENT_CHARS 1
252b5132 423#define PREFIX_SEPARATOR '\\'
252b5132 424
b3b91714
AM		 425#else
426const char *i386_comment_chars = "#";
427#define PREFIX_SEPARATOR '/'
428#endif
429
252b5132
RH		 430/* This array holds the chars that only start a comment at the beginning of
431 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 432 .line and .file directives will appear in the pre-processed output.
433 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 434 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 435 #NO_APP at the beginning of its output.
436 Also note that comments started like this one will always work if
252b5132 437 '/' isn't otherwise defined. */
b3b91714 438const char line_comment_chars[] = "#/";
252b5132 439
63a0b638 440const char line_separator_chars[] = ";";
252b5132 441
ce8a8b2f
AM		 442/* Chars that can be used to separate mant from exp in floating point
443 nums. */
252b5132
RH		 444const char EXP_CHARS[] = "eE";
445
ce8a8b2f
AM		 446/* Chars that mean this number is a floating point constant
447 As in 0f12.456
448 or 0d1.2345e12. */
252b5132
RH		 449const char FLT_CHARS[] = "fFdDxX";
450
ce8a8b2f 451/* Tables for lexical analysis. */
252b5132
RH		 452static char mnemonic_chars[256];
453static char register_chars[256];
454static char operand_chars[256];
455static char identifier_chars[256];
456static char digit_chars[256];
457
ce8a8b2f 458/* Lexical macros. */
252b5132
RH		 459#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
460#define is_operand_char(x) (operand_chars[(unsigned char) x])
461#define is_register_char(x) (register_chars[(unsigned char) x])
462#define is_space_char(x) ((x) == ' ')
463#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
464#define is_digit_char(x) (digit_chars[(unsigned char) x])
465
0234cb7c 466/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 467static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
468
469/* md_assemble() always leaves the strings it's passed unaltered. To
470 effect this we maintain a stack of saved characters that we've smashed
471 with '\0's (indicating end of strings for various sub-fields of the
47926f60 472 assembler instruction). */
252b5132 473static char save_stack[32];
ce8a8b2f 474static char *save_stack_p;
252b5132
RH		 475#define END_STRING_AND_SAVE(s) \
476 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
477#define RESTORE_END_STRING(s) \
478 do { *(s) = *--save_stack_p; } while (0)
479
47926f60 480/* The instruction we're assembling. */
252b5132
RH		 481static i386_insn i;
482
483/* Possible templates for current insn. */
484static const templates *current_templates;
485
31b2323c
L		 486/* Per instruction expressionS buffers: max displacements & immediates. */
487static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
488static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 489
47926f60 490/* Current operand we are working on. */
ee86248c 491static int this_operand = -1;
252b5132 492
3e73aa7c
JH		 493/* We support four different modes. FLAG_CODE variable is used to distinguish
494 these. */
495
496enum flag_code {
497 CODE_32BIT,
498 CODE_16BIT,
499 CODE_64BIT };
500
501static enum flag_code flag_code;
4fa24527 502static unsigned int object_64bit;
862be3fb 503static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 504static int use_rela_relocations = 0;
505
7af8ed2d
NC		 506#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
507 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
508 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
509
351f65ca
L		 510/* The ELF ABI to use. */
511enum x86_elf_abi
512{
513 I386_ABI,
7f56bc95
L		 514 X86_64_ABI,
515 X86_64_X32_ABI
351f65ca
L		 516};
517
518static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 519#endif
351f65ca 520
167ad85b
TG		 521#if defined (TE_PE) || defined (TE_PEP)
522/* Use big object file format. */
523static int use_big_obj = 0;
524#endif
525
47926f60
KH		 526/* 1 for intel syntax,
527 0 if att syntax. */
528static int intel_syntax = 0;
252b5132 529
1efbbeb4
L		 530/* 1 for intel mnemonic,
531 0 if att mnemonic. */
532static int intel_mnemonic = !SYSV386_COMPAT;
533
5209009a 534/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 535static int old_gcc = OLDGCC_COMPAT;
536
a60de03c
JB		 537/* 1 if pseudo registers are permitted. */
538static int allow_pseudo_reg = 0;
539
47926f60
KH		 540/* 1 if register prefix % not required. */
541static int allow_naked_reg = 0;
252b5132 542
7e8b059b
L		 543/* 1 if the assembler should add BND prefix for all control-tranferring
544 instructions supporting it, even if this prefix wasn't specified
545 explicitly. */
546static int add_bnd_prefix = 0;
547
ba104c83 548/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 549static int allow_index_reg = 0;
550
d022bddd
IT		 551/* 1 if the assembler should ignore LOCK prefix, even if it was
552 specified explicitly. */
553static int omit_lock_prefix = 0;
554
7bab8ab5 555static enum check_kind
daf50ae7 556 {
7bab8ab5
JB		 557 check_none = 0,
558 check_warning,
559 check_error
daf50ae7 560 }
7bab8ab5 561sse_check, operand_check = check_warning;
daf50ae7 562
2ca3ace5
L		 563/* Register prefix used for error message. */
564static const char *register_prefix = "%";
565
47926f60
KH		 566/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
567 leave, push, and pop instructions so that gcc has the same stack
568 frame as in 32 bit mode. */
569static char stackop_size = '\0';
eecb386c 570
12b55ccc
L		 571/* Non-zero to optimize code alignment. */
572int optimize_align_code = 1;
573
47926f60
KH		 574/* Non-zero to quieten some warnings. */
575static int quiet_warnings = 0;
a38cf1db 576
47926f60
KH		 577/* CPU name. */
578static const char *cpu_arch_name = NULL;
6305a203 579static char *cpu_sub_arch_name = NULL;
a38cf1db 580
47926f60 581/* CPU feature flags. */
40fb9820
L		 582static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
583
ccc9c027
L		 584/* If we have selected a cpu we are generating instructions for. */
585static int cpu_arch_tune_set = 0;
586
9103f4f4 587/* Cpu we are generating instructions for. */
fbf3f584 588enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 589
590/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 591static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 592
ccc9c027 593/* CPU instruction set architecture used. */
fbf3f584 594enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 595
9103f4f4 596/* CPU feature flags of instruction set architecture used. */
fbf3f584 597i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 598
fddf5b5b
AM		 599/* If set, conditional jumps are not automatically promoted to handle
600 larger than a byte offset. */
601static unsigned int no_cond_jump_promotion = 0;
602
c0f3af97
L		 603/* Encode SSE instructions with VEX prefix. */
604static unsigned int sse2avx;
605
539f890d
L		 606/* Encode scalar AVX instructions with specific vector length. */
607static enum
608 {
609 vex128 = 0,
610 vex256
611 } avxscalar;
612
43234a1e
L		 613/* Encode scalar EVEX LIG instructions with specific vector length. */
614static enum
615 {
616 evexl128 = 0,
617 evexl256,
618 evexl512
619 } evexlig;
620
621/* Encode EVEX WIG instructions with specific evex.w. */
622static enum
623 {
624 evexw0 = 0,
625 evexw1
626 } evexwig;
627
d3d3c6db
IT		 628/* Value to encode in EVEX RC bits, for SAE-only instructions. */
629static enum rc_type evexrcig = rne;
630
29b0f896 631/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 632static symbolS *GOT_symbol;
29b0f896 633
a4447b93
RH		 634/* The dwarf2 return column, adjusted for 32 or 64 bit. */
635unsigned int x86_dwarf2_return_column;
636
637/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
638int x86_cie_data_alignment;
639
252b5132 640/* Interface to relax_segment.
fddf5b5b
AM		 641 There are 3 major relax states for 386 jump insns because the
642 different types of jumps add different sizes to frags when we're
643 figuring out what sort of jump to choose to reach a given label. */
252b5132 644
47926f60 645/* Types. */
93c2a809
AM		 646#define UNCOND_JUMP 0
647#define COND_JUMP 1
648#define COND_JUMP86 2
fddf5b5b 649
47926f60 650/* Sizes. */
252b5132
RH		 651#define CODE16 1
652#define SMALL 0
29b0f896 653#define SMALL16 (SMALL | CODE16)
252b5132 654#define BIG 2
29b0f896 655#define BIG16 (BIG | CODE16)
252b5132
RH		 656
657#ifndef INLINE
658#ifdef __GNUC__
659#define INLINE __inline__
660#else
661#define INLINE
662#endif
663#endif
664
fddf5b5b
AM		 665#define ENCODE_RELAX_STATE(type, size) \
666 ((relax_substateT) (((type) << 2) | (size)))
667#define TYPE_FROM_RELAX_STATE(s) \
668 ((s) >> 2)
669#define DISP_SIZE_FROM_RELAX_STATE(s) \
670 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 671
672/* This table is used by relax_frag to promote short jumps to long
673 ones where necessary. SMALL (short) jumps may be promoted to BIG
674 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
675 don't allow a short jump in a 32 bit code segment to be promoted to
676 a 16 bit offset jump because it's slower (requires data size
677 prefix), and doesn't work, unless the destination is in the bottom
678 64k of the code segment (The top 16 bits of eip are zeroed). */
679
680const relax_typeS md_relax_table[] =
681{
24eab124
AM		 682 /* The fields are:
683 1) most positive reach of this state,
684 2) most negative reach of this state,
93c2a809 685 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 686 4) which index into the table to try if we can't fit into this one. */
252b5132 687
fddf5b5b 688 /* UNCOND_JUMP states. */
93c2a809
AM		 689 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
690 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
691 /* dword jmp adds 4 bytes to frag:
692 0 extra opcode bytes, 4 displacement bytes. */
252b5132 693 {0, 0, 4, 0},
93c2a809
AM		 694 /* word jmp adds 2 byte2 to frag:
695 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 696 {0, 0, 2, 0},
697
93c2a809
AM		 698 /* COND_JUMP states. */
699 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
700 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
701 /* dword conditionals adds 5 bytes to frag:
702 1 extra opcode byte, 4 displacement bytes. */
703 {0, 0, 5, 0},
fddf5b5b 704 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 705 1 extra opcode byte, 2 displacement bytes. */
706 {0, 0, 3, 0},
707
708 /* COND_JUMP86 states. */
709 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
710 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
711 /* dword conditionals adds 5 bytes to frag:
712 1 extra opcode byte, 4 displacement bytes. */
713 {0, 0, 5, 0},
714 /* word conditionals add 4 bytes to frag:
715 1 displacement byte and a 3 byte long branch insn. */
716 {0, 0, 4, 0}
252b5132
RH		 717};
718
9103f4f4
L		 719static const arch_entry cpu_arch[] =
720{
89507696
JB		 721 /* Do not replace the first two entries - i386_target_format()
722 relies on them being there in this order. */
8a2c8fef 723 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 724 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 725 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 726 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 727 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 728 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 729 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 730 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 731 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 732 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 733 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 734 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 735 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 736 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 737 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 738 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 739 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 740 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 741 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 742 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 743 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 744 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 745 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 746 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 747 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 748 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 749 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 750 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 751 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 752 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 753 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 754 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 755 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 756 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 757 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 758 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 759 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 760 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 761 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 762 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 764 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 766 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 767 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
768 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 769 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 770 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 771 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 772 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 773 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 774 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 775 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 776 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 777 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 778 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 779 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 780 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 781 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 782 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 783 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 784 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 785 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 786 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 787 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
788 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 789 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
790 CPU_BDVER4_FLAGS, 0, 0 },
7b458c12
L		 791 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
792 CPU_BTVER1_FLAGS, 0, 0 },
793 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
794 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 795 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 796 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 797 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 798 CPU_287_FLAGS, 0, 0 },
8a2c8fef 799 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 800 CPU_387_FLAGS, 0, 0 },
8a2c8fef 801 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 802 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 803 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 804 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 805 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 806 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 807 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 808 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 809 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 810 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 811 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 812 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 813 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 814 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 815 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 816 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 817 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 818 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 819 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 820 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 821 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 822 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 823 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 824 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 825 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
826 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 827 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
828 CPU_AVX512F_FLAGS, 0, 0 },
829 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
830 CPU_AVX512CD_FLAGS, 0, 0 },
831 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
832 CPU_AVX512ER_FLAGS, 0, 0 },
833 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
834 CPU_AVX512PF_FLAGS, 0, 0 },
1dfc6506
L		 835 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
836 CPU_AVX512DQ_FLAGS, 0, 0 },
837 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
838 CPU_AVX512BW_FLAGS, 0, 0 },
839 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
840 CPU_AVX512VL_FLAGS, 0, 0 },
8a2c8fef 841 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 842 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 843 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 844 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 845 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
846 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 847 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 848 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 849 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 850 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 851 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 852 CPU_XSAVEOPT_FLAGS, 0, 0 },
1dfc6506
L		 853 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
854 CPU_XSAVEC_FLAGS, 0, 0 },
855 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
856 CPU_XSAVES_FLAGS, 0, 0 },
8a2c8fef 857 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 858 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 859 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 860 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 861 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 862 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 863 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 864 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 865 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 866 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 867 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 868 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 869 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
870 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 871 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 872 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 873 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 874 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 875 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 876 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 877 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 878 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 880 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 881 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
882 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 884 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 885 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
886 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 887 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
888 CPU_HLE_FLAGS, 0, 0 },
889 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
890 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 891 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
892 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 893 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 894 CPU_CLFLUSH_FLAGS, 0, 0 },
895 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
896 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 897 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 898 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 899 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 900 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 901 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 902 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 903 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 904 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 905 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 906 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 907 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 908 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 909 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 910 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 911 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 912 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 913 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 914 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 915 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
916 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 917 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
918 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 919 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
920 CPU_ADX_FLAGS, 0, 0 },
921 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
922 CPU_RDSEED_FLAGS, 0, 0 },
923 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
924 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 925 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
926 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 927 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
928 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 929 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
930 CPU_SHA_FLAGS, 0, 0 },
963f3586
IT		 931 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
932 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
dcf893b5
IT		 933 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
934 CPU_PREFETCHWT1_FLAGS, 0, 0 },
2cf200a4
IT		 935 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
936 CPU_SE1_FLAGS, 0, 0 },
c5e7287a
IT		 937 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
938 CPU_CLWB_FLAGS, 0, 0 },
9d8596f0
IT		 939 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
940 CPU_PCOMMIT_FLAGS, 0, 0 },
2cc1b5aa
IT		 941 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
942 CPU_AVX512IFMA_FLAGS, 0, 0 },
14f195c9
IT		 943 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
944 CPU_AVX512VBMI_FLAGS, 0, 0 },
e413e4e9
AM		 945};
946
704209c0 947#ifdef I386COFF
a6c24e68
NC		 948/* Like s_lcomm_internal in gas/read.c but the alignment string
949 is allowed to be optional. */
950
951static symbolS *
952pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
953{
954 addressT align = 0;
955
956 SKIP_WHITESPACE ();
957
7ab9ffdd 958 if (needs_align
a6c24e68
NC		 959 && *input_line_pointer == ',')
960 {
961 align = parse_align (needs_align - 1);
7ab9ffdd 962
a6c24e68
NC		 963 if (align == (addressT) -1)
964 return NULL;
965 }
966 else
967 {
968 if (size >= 8)
969 align = 3;
970 else if (size >= 4)
971 align = 2;
972 else if (size >= 2)
973 align = 1;
974 else
975 align = 0;
976 }
977
978 bss_alloc (symbolP, size, align);
979 return symbolP;
980}
981
704209c0 982static void
a6c24e68
NC		 983pe_lcomm (int needs_align)
984{
985 s_comm_internal (needs_align * 2, pe_lcomm_internal);
986}
704209c0 987#endif
a6c24e68 988
29b0f896
AM		 989const pseudo_typeS md_pseudo_table[] =
990{
991#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
992 {"align", s_align_bytes, 0},
993#else
994 {"align", s_align_ptwo, 0},
995#endif
996 {"arch", set_cpu_arch, 0},
997#ifndef I386COFF
998 {"bss", s_bss, 0},
a6c24e68
NC		 999#else
1000 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1001#endif
1002 {"ffloat", float_cons, 'f'},
1003 {"dfloat", float_cons, 'd'},
1004 {"tfloat", float_cons, 'x'},
1005 {"value", cons, 2},
d182319b 1006 {"slong", signed_cons, 4},
29b0f896
AM		 1007 {"noopt", s_ignore, 0},
1008 {"optim", s_ignore, 0},
1009 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1010 {"code16", set_code_flag, CODE_16BIT},
1011 {"code32", set_code_flag, CODE_32BIT},
1012 {"code64", set_code_flag, CODE_64BIT},
1013 {"intel_syntax", set_intel_syntax, 1},
1014 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1015 {"intel_mnemonic", set_intel_mnemonic, 1},
1016 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1017 {"allow_index_reg", set_allow_index_reg, 1},
1018 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1019 {"sse_check", set_check, 0},
1020 {"operand_check", set_check, 1},
3b22753a
L		 1021#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1022 {"largecomm", handle_large_common, 0},
07a53e5c 1023#else
e3bb37b5 1024 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1025 {"loc", dwarf2_directive_loc, 0},
1026 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1027#endif
6482c264
NC		 1028#ifdef TE_PE
1029 {"secrel32", pe_directive_secrel, 0},
1030#endif
29b0f896
AM		 1031 {0, 0, 0}
1032};
1033
1034/* For interface with expression (). */
1035extern char *input_line_pointer;
1036
1037/* Hash table for instruction mnemonic lookup. */
1038static struct hash_control *op_hash;
1039
1040/* Hash table for register lookup. */
1041static struct hash_control *reg_hash;
1042\f
252b5132 1043void
e3bb37b5 1044i386_align_code (fragS *fragP, int count)
252b5132 1045{
ce8a8b2f
AM		 1046 /* Various efficient no-op patterns for aligning code labels.
1047 Note: Don't try to assemble the instructions in the comments.
1048 0L and 0w are not legal. */
252b5132
RH		 1049 static const char f32_1[] =
1050 {0x90}; /* nop */
1051 static const char f32_2[] =
ccc9c027 1052 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1053 static const char f32_3[] =
1054 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1055 static const char f32_4[] =
1056 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1057 static const char f32_5[] =
1058 {0x90, /* nop */
1059 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1060 static const char f32_6[] =
1061 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1062 static const char f32_7[] =
1063 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1064 static const char f32_8[] =
1065 {0x90, /* nop */
1066 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1067 static const char f32_9[] =
1068 {0x89,0xf6, /* movl %esi,%esi */
1069 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1070 static const char f32_10[] =
1071 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1072 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1073 static const char f32_11[] =
1074 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1075 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1076 static const char f32_12[] =
1077 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1078 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1079 static const char f32_13[] =
1080 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1081 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1082 static const char f32_14[] =
1083 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1084 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1085 static const char f16_3[] =
1086 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1087 static const char f16_4[] =
1088 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1089 static const char f16_5[] =
1090 {0x90, /* nop */
1091 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1092 static const char f16_6[] =
1093 {0x89,0xf6, /* mov %si,%si */
1094 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1095 static const char f16_7[] =
1096 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1097 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1098 static const char f16_8[] =
1099 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1100 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1101 static const char jump_31[] =
1102 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1103 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1104 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1105 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1106 static const char *const f32_patt[] = {
1107 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1108 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1109 };
1110 static const char *const f16_patt[] = {
76bc74dc 1111 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1112 };
ccc9c027
L		 1113 /* nopl (%[re]ax) */
1114 static const char alt_3[] =
1115 {0x0f,0x1f,0x00};
1116 /* nopl 0(%[re]ax) */
1117 static const char alt_4[] =
1118 {0x0f,0x1f,0x40,0x00};
1119 /* nopl 0(%[re]ax,%[re]ax,1) */
1120 static const char alt_5[] =
1121 {0x0f,0x1f,0x44,0x00,0x00};
1122 /* nopw 0(%[re]ax,%[re]ax,1) */
1123 static const char alt_6[] =
1124 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1125 /* nopl 0L(%[re]ax) */
1126 static const char alt_7[] =
1127 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1128 /* nopl 0L(%[re]ax,%[re]ax,1) */
1129 static const char alt_8[] =
1130 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1131 /* nopw 0L(%[re]ax,%[re]ax,1) */
1132 static const char alt_9[] =
1133 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1134 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1135 static const char alt_10[] =
1136 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1137 /* data16
1138 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1139 static const char alt_long_11[] =
1140 {0x66,
1141 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1142 /* data16
1143 data16
1144 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1145 static const char alt_long_12[] =
1146 {0x66,
1147 0x66,
1148 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1149 /* data16
1150 data16
1151 data16
1152 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1153 static const char alt_long_13[] =
1154 {0x66,
1155 0x66,
1156 0x66,
1157 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1158 /* data16
1159 data16
1160 data16
1161 data16
1162 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1163 static const char alt_long_14[] =
1164 {0x66,
1165 0x66,
1166 0x66,
1167 0x66,
1168 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1169 /* data16
1170 data16
1171 data16
1172 data16
1173 data16
1174 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1175 static const char alt_long_15[] =
1176 {0x66,
1177 0x66,
1178 0x66,
1179 0x66,
1180 0x66,
1181 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1182 /* nopl 0(%[re]ax,%[re]ax,1)
1183 nopw 0(%[re]ax,%[re]ax,1) */
1184 static const char alt_short_11[] =
1185 {0x0f,0x1f,0x44,0x00,0x00,
1186 0x66,0x0f,0x1f,0x44,0x00,0x00};
1187 /* nopw 0(%[re]ax,%[re]ax,1)
1188 nopw 0(%[re]ax,%[re]ax,1) */
1189 static const char alt_short_12[] =
1190 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1191 0x66,0x0f,0x1f,0x44,0x00,0x00};
1192 /* nopw 0(%[re]ax,%[re]ax,1)
1193 nopl 0L(%[re]ax) */
1194 static const char alt_short_13[] =
1195 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1196 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1197 /* nopl 0L(%[re]ax)
1198 nopl 0L(%[re]ax) */
1199 static const char alt_short_14[] =
1200 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1201 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1202 /* nopl 0L(%[re]ax)
1203 nopl 0L(%[re]ax,%[re]ax,1) */
1204 static const char alt_short_15[] =
1205 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1206 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1207 static const char *const alt_short_patt[] = {
1208 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1209 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1210 alt_short_14, alt_short_15
1211 };
1212 static const char *const alt_long_patt[] = {
1213 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1214 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1215 alt_long_14, alt_long_15
1216 };
252b5132 1217
76bc74dc
L		 1218 /* Only align for at least a positive non-zero boundary. */
1219 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1220 return;
3e73aa7c 1221
ccc9c027
L		 1222 /* We need to decide which NOP sequence to use for 32bit and
1223 64bit. When -mtune= is used:
4eed87de 1224
76bc74dc
L		 1225 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1226 PROCESSOR_GENERIC32, f32_patt will be used.
1227 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1228 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1229 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1230 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
7b458c12 1231 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
69dd9865 1232 will be used.
ccc9c027 1233
76bc74dc 1234 When -mtune= isn't used, alt_long_patt will be used if
22109423 1235 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1236 be used.
ccc9c027
L		 1237
1238 When -march= or .arch is used, we can't use anything beyond
1239 cpu_arch_isa_flags. */
1240
1241 if (flag_code == CODE_16BIT)
1242 {
ccc9c027 1243 if (count > 8)
33fef721 1244 {
76bc74dc
L		 1245 memcpy (fragP->fr_literal + fragP->fr_fix,
1246 jump_31, count);
1247 /* Adjust jump offset. */
1248 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1249 }
76bc74dc
L		 1250 else
1251 memcpy (fragP->fr_literal + fragP->fr_fix,
1252 f16_patt[count - 1], count);
252b5132 1253 }
33fef721 1254 else
ccc9c027
L		 1255 {
1256 const char *const *patt = NULL;
1257
fbf3f584 1258 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1259 {
1260 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1261 switch (cpu_arch_tune)
1262 {
1263 case PROCESSOR_UNKNOWN:
1264 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1265 optimize with nops. */
1266 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1267 patt = alt_long_patt;
ccc9c027
L		 1268 else
1269 patt = f32_patt;
1270 break;
ccc9c027
L		 1271 case PROCESSOR_PENTIUM4:
1272 case PROCESSOR_NOCONA:
ef05d495 1273 case PROCESSOR_CORE:
76bc74dc 1274 case PROCESSOR_CORE2:
bd5295b2 1275 case PROCESSOR_COREI7:
3632d14b 1276 case PROCESSOR_L1OM:
7a9068fe 1277 case PROCESSOR_K1OM:
76bc74dc
L		 1278 case PROCESSOR_GENERIC64:
1279 patt = alt_long_patt;
1280 break;
ccc9c027
L		 1281 case PROCESSOR_K6:
1282 case PROCESSOR_ATHLON:
1283 case PROCESSOR_K8:
4eed87de 1284 case PROCESSOR_AMDFAM10:
8aedb9fe 1285 case PROCESSOR_BD:
7b458c12 1286 case PROCESSOR_BT:
ccc9c027
L		 1287 patt = alt_short_patt;
1288 break;
76bc74dc 1289 case PROCESSOR_I386:
ccc9c027
L		 1290 case PROCESSOR_I486:
1291 case PROCESSOR_PENTIUM:
2dde1948 1292 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1293 case PROCESSOR_GENERIC32:
1294 patt = f32_patt;
1295 break;
4eed87de 1296 }
ccc9c027
L		 1297 }
1298 else
1299 {
fbf3f584 1300 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1301 {
1302 case PROCESSOR_UNKNOWN:
e6a14101 1303 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1304 PROCESSOR_UNKNOWN. */
1305 abort ();
1306 break;
1307
76bc74dc 1308 case PROCESSOR_I386:
ccc9c027
L		 1309 case PROCESSOR_I486:
1310 case PROCESSOR_PENTIUM:
ccc9c027
L		 1311 case PROCESSOR_K6:
1312 case PROCESSOR_ATHLON:
1313 case PROCESSOR_K8:
4eed87de 1314 case PROCESSOR_AMDFAM10:
8aedb9fe 1315 case PROCESSOR_BD:
7b458c12 1316 case PROCESSOR_BT:
ccc9c027
L		 1317 case PROCESSOR_GENERIC32:
1318 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1319 with nops. */
1320 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1321 patt = alt_short_patt;
1322 else
1323 patt = f32_patt;
1324 break;
76bc74dc
L		 1325 case PROCESSOR_PENTIUMPRO:
1326 case PROCESSOR_PENTIUM4:
1327 case PROCESSOR_NOCONA:
1328 case PROCESSOR_CORE:
ef05d495 1329 case PROCESSOR_CORE2:
bd5295b2 1330 case PROCESSOR_COREI7:
3632d14b 1331 case PROCESSOR_L1OM:
7a9068fe 1332 case PROCESSOR_K1OM:
22109423 1333 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1334 patt = alt_long_patt;
1335 else
1336 patt = f32_patt;
1337 break;
1338 case PROCESSOR_GENERIC64:
76bc74dc 1339 patt = alt_long_patt;
ccc9c027 1340 break;
4eed87de 1341 }
ccc9c027
L		 1342 }
1343
76bc74dc
L		 1344 if (patt == f32_patt)
1345 {
1346 /* If the padding is less than 15 bytes, we use the normal
1347 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1348 its offset. */
1349 int limit;
76ba9986 1350
711eedef
L		 1351 /* For 64bit, the limit is 3 bytes. */
1352 if (flag_code == CODE_64BIT
1353 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1354 limit = 3;
1355 else
1356 limit = 15;
1357 if (count < limit)
76bc74dc
L		 1358 memcpy (fragP->fr_literal + fragP->fr_fix,
1359 patt[count - 1], count);
1360 else
1361 {
1362 memcpy (fragP->fr_literal + fragP->fr_fix,
1363 jump_31, count);
1364 /* Adjust jump offset. */
1365 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1366 }
1367 }
1368 else
1369 {
1370 /* Maximum length of an instruction is 15 byte. If the
1371 padding is greater than 15 bytes and we don't use jump,
1372 we have to break it into smaller pieces. */
1373 int padding = count;
1374 while (padding > 15)
1375 {
1376 padding -= 15;
1377 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1378 patt [14], 15);
1379 }
1380
1381 if (padding)
1382 memcpy (fragP->fr_literal + fragP->fr_fix,
1383 patt [padding - 1], padding);
1384 }
ccc9c027 1385 }
33fef721 1386 fragP->fr_var = count;
252b5132
RH		 1387}
1388
c6fb90c8 1389static INLINE int
0dfbf9d7 1390operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1391{
0dfbf9d7 1392 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1393 {
1394 case 3:
0dfbf9d7 1395 if (x->array[2])
c6fb90c8
L		 1396 return 0;
1397 case 2:
0dfbf9d7 1398 if (x->array[1])
c6fb90c8
L		 1399 return 0;
1400 case 1:
0dfbf9d7 1401 return !x->array[0];
c6fb90c8
L		 1402 default:
1403 abort ();
1404 }
40fb9820
L		 1405}
1406
c6fb90c8 1407static INLINE void
0dfbf9d7 1408operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1409{
0dfbf9d7 1410 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1411 {
1412 case 3:
0dfbf9d7 1413 x->array[2] = v;
c6fb90c8 1414 case 2:
0dfbf9d7 1415 x->array[1] = v;
c6fb90c8 1416 case 1:
0dfbf9d7 1417 x->array[0] = v;
c6fb90c8
L		 1418 break;
1419 default:
1420 abort ();
1421 }
1422}
40fb9820 1423
c6fb90c8 1424static INLINE int
0dfbf9d7
L		 1425operand_type_equal (const union i386_operand_type *x,
1426 const union i386_operand_type *y)
c6fb90c8 1427{
0dfbf9d7 1428 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1429 {
1430 case 3:
0dfbf9d7 1431 if (x->array[2] != y->array[2])
c6fb90c8
L		 1432 return 0;
1433 case 2:
0dfbf9d7 1434 if (x->array[1] != y->array[1])
c6fb90c8
L		 1435 return 0;
1436 case 1:
0dfbf9d7 1437 return x->array[0] == y->array[0];
c6fb90c8
L		 1438 break;
1439 default:
1440 abort ();
1441 }
1442}
40fb9820 1443
0dfbf9d7
L		 1444static INLINE int
1445cpu_flags_all_zero (const union i386_cpu_flags *x)
1446{
1447 switch (ARRAY_SIZE(x->array))
1448 {
1449 case 3:
1450 if (x->array[2])
1451 return 0;
1452 case 2:
1453 if (x->array[1])
1454 return 0;
1455 case 1:
1456 return !x->array[0];
1457 default:
1458 abort ();
1459 }
1460}
1461
1462static INLINE void
1463cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1464{
1465 switch (ARRAY_SIZE(x->array))
1466 {
1467 case 3:
1468 x->array[2] = v;
1469 case 2:
1470 x->array[1] = v;
1471 case 1:
1472 x->array[0] = v;
1473 break;
1474 default:
1475 abort ();
1476 }
1477}
1478
1479static INLINE int
1480cpu_flags_equal (const union i386_cpu_flags *x,
1481 const union i386_cpu_flags *y)
1482{
1483 switch (ARRAY_SIZE(x->array))
1484 {
1485 case 3:
1486 if (x->array[2] != y->array[2])
1487 return 0;
1488 case 2:
1489 if (x->array[1] != y->array[1])
1490 return 0;
1491 case 1:
1492 return x->array[0] == y->array[0];
1493 break;
1494 default:
1495 abort ();
1496 }
1497}
c6fb90c8
L		 1498
1499static INLINE int
1500cpu_flags_check_cpu64 (i386_cpu_flags f)
1501{
1502 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1503 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1504}
1505
c6fb90c8
L		 1506static INLINE i386_cpu_flags
1507cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1508{
c6fb90c8
L		 1509 switch (ARRAY_SIZE (x.array))
1510 {
1511 case 3:
1512 x.array [2] &= y.array [2];
1513 case 2:
1514 x.array [1] &= y.array [1];
1515 case 1:
1516 x.array [0] &= y.array [0];
1517 break;
1518 default:
1519 abort ();
1520 }
1521 return x;
1522}
40fb9820 1523
c6fb90c8
L		 1524static INLINE i386_cpu_flags
1525cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1526{
c6fb90c8 1527 switch (ARRAY_SIZE (x.array))
40fb9820 1528 {
c6fb90c8
L		 1529 case 3:
1530 x.array [2] |= y.array [2];
1531 case 2:
1532 x.array [1] |= y.array [1];
1533 case 1:
1534 x.array [0] |= y.array [0];
40fb9820
L		 1535 break;
1536 default:
1537 abort ();
1538 }
40fb9820
L		 1539 return x;
1540}
1541
309d3373
JB		 1542static INLINE i386_cpu_flags
1543cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1544{
1545 switch (ARRAY_SIZE (x.array))
1546 {
1547 case 3:
1548 x.array [2] &= ~y.array [2];
1549 case 2:
1550 x.array [1] &= ~y.array [1];
1551 case 1:
1552 x.array [0] &= ~y.array [0];
1553 break;
1554 default:
1555 abort ();
1556 }
1557 return x;
1558}
1559
c0f3af97
L		 1560#define CPU_FLAGS_ARCH_MATCH 0x1
1561#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1562#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1563#define CPU_FLAGS_PCLMUL_MATCH 0x8
1564#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1565
a5ff0eb2 1566#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1567 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1568 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1569#define CPU_FLAGS_PERFECT_MATCH \
1570 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1571
1572/* Return CPU flags match bits. */
3629bb00 1573
40fb9820 1574static int
d3ce72d0 1575cpu_flags_match (const insn_template *t)
40fb9820 1576{
c0f3af97
L		 1577 i386_cpu_flags x = t->cpu_flags;
1578 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1579
1580 x.bitfield.cpu64 = 0;
1581 x.bitfield.cpuno64 = 0;
1582
0dfbf9d7 1583 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1584 {
1585 /* This instruction is available on all archs. */
1586 match |= CPU_FLAGS_32BIT_MATCH;
1587 }
3629bb00
L		 1588 else
1589 {
c0f3af97 1590 /* This instruction is available only on some archs. */
3629bb00
L		 1591 i386_cpu_flags cpu = cpu_arch_flags;
1592
1593 cpu.bitfield.cpu64 = 0;
1594 cpu.bitfield.cpuno64 = 0;
1595 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1596 if (!cpu_flags_all_zero (&cpu))
1597 {
a5ff0eb2
L		 1598 if (x.bitfield.cpuavx)
1599 {
ce2f5b3c 1600 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1601 if (cpu.bitfield.cpuavx)
1602 {
1603 /* Check SSE2AVX. */
1604 if (!t->opcode_modifier.sse2avx|| sse2avx)
1605 {
1606 match |= (CPU_FLAGS_ARCH_MATCH
1607 | CPU_FLAGS_AVX_MATCH);
1608 /* Check AES. */
1609 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1610 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1611 /* Check PCLMUL. */
1612 if (!x.bitfield.cpupclmul
1613 || cpu.bitfield.cpupclmul)
1614 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1615 }
1616 }
1617 else
1618 match |= CPU_FLAGS_ARCH_MATCH;
1619 }
1620 else
c0f3af97
L		 1621 match |= CPU_FLAGS_32BIT_MATCH;
1622 }
3629bb00 1623 }
c0f3af97 1624 return match;
40fb9820
L		 1625}
1626
c6fb90c8
L		 1627static INLINE i386_operand_type
1628operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1629{
c6fb90c8
L		 1630 switch (ARRAY_SIZE (x.array))
1631 {
1632 case 3:
1633 x.array [2] &= y.array [2];
1634 case 2:
1635 x.array [1] &= y.array [1];
1636 case 1:
1637 x.array [0] &= y.array [0];
1638 break;
1639 default:
1640 abort ();
1641 }
1642 return x;
40fb9820
L		 1643}
1644
c6fb90c8
L		 1645static INLINE i386_operand_type
1646operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1647{
c6fb90c8 1648 switch (ARRAY_SIZE (x.array))
40fb9820 1649 {
c6fb90c8
L		 1650 case 3:
1651 x.array [2] |= y.array [2];
1652 case 2:
1653 x.array [1] |= y.array [1];
1654 case 1:
1655 x.array [0] |= y.array [0];
40fb9820
L		 1656 break;
1657 default:
1658 abort ();
1659 }
c6fb90c8
L		 1660 return x;
1661}
40fb9820 1662
c6fb90c8
L		 1663static INLINE i386_operand_type
1664operand_type_xor (i386_operand_type x, i386_operand_type y)
1665{
1666 switch (ARRAY_SIZE (x.array))
1667 {
1668 case 3:
1669 x.array [2] ^= y.array [2];
1670 case 2:
1671 x.array [1] ^= y.array [1];
1672 case 1:
1673 x.array [0] ^= y.array [0];
1674 break;
1675 default:
1676 abort ();
1677 }
40fb9820
L		 1678 return x;
1679}
1680
1681static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1682static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1683static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1684static const i386_operand_type inoutportreg
1685 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1686static const i386_operand_type reg16_inoutportreg
1687 = OPERAND_TYPE_REG16_INOUTPORTREG;
1688static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1689static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1690static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1691static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1692static const i386_operand_type anydisp
1693 = OPERAND_TYPE_ANYDISP;
40fb9820 1694static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1695static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1696static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1697static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1698static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1699static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1700static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1701static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1702static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1703static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1704static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1705static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1706static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1707static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1708
1709enum operand_type
1710{
1711 reg,
40fb9820
L		 1712 imm,
1713 disp,
1714 anymem
1715};
1716
c6fb90c8 1717static INLINE int
40fb9820
L		 1718operand_type_check (i386_operand_type t, enum operand_type c)
1719{
1720 switch (c)
1721 {
1722 case reg:
1723 return (t.bitfield.reg8
1724 || t.bitfield.reg16
1725 || t.bitfield.reg32
1726 || t.bitfield.reg64);
1727
40fb9820
L		 1728 case imm:
1729 return (t.bitfield.imm8
1730 || t.bitfield.imm8s
1731 || t.bitfield.imm16
1732 || t.bitfield.imm32
1733 || t.bitfield.imm32s
1734 || t.bitfield.imm64);
1735
1736 case disp:
1737 return (t.bitfield.disp8
1738 || t.bitfield.disp16
1739 || t.bitfield.disp32
1740 || t.bitfield.disp32s
1741 || t.bitfield.disp64);
1742
1743 case anymem:
1744 return (t.bitfield.disp8
1745 || t.bitfield.disp16
1746 || t.bitfield.disp32
1747 || t.bitfield.disp32s
1748 || t.bitfield.disp64
1749 || t.bitfield.baseindex);
1750
1751 default:
1752 abort ();
1753 }
2cfe26b6
AM		 1754
1755 return 0;
40fb9820
L		 1756}
1757
5c07affc
L		 1758/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1759 operand J for instruction template T. */
1760
1761static INLINE int
d3ce72d0 1762match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1763{
1764 return !((i.types[j].bitfield.byte
1765 && !t->operand_types[j].bitfield.byte)
1766 || (i.types[j].bitfield.word
1767 && !t->operand_types[j].bitfield.word)
1768 || (i.types[j].bitfield.dword
1769 && !t->operand_types[j].bitfield.dword)
1770 || (i.types[j].bitfield.qword
1771 && !t->operand_types[j].bitfield.qword));
1772}
1773
1774/* Return 1 if there is no conflict in any size on operand J for
1775 instruction template T. */
1776
1777static INLINE int
d3ce72d0 1778match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1779{
1780 return (match_reg_size (t, j)
1781 && !((i.types[j].bitfield.unspecified
1782 && !t->operand_types[j].bitfield.unspecified)
1783 || (i.types[j].bitfield.fword
1784 && !t->operand_types[j].bitfield.fword)
1785 || (i.types[j].bitfield.tbyte
1786 && !t->operand_types[j].bitfield.tbyte)
1787 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1788 && !t->operand_types[j].bitfield.xmmword)
1789 || (i.types[j].bitfield.ymmword
43234a1e
L		 1790 && !t->operand_types[j].bitfield.ymmword)
1791 || (i.types[j].bitfield.zmmword
1792 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1793}
1794
1795/* Return 1 if there is no size conflict on any operands for
1796 instruction template T. */
1797
1798static INLINE int
d3ce72d0 1799operand_size_match (const insn_template *t)
5c07affc
L		 1800{
1801 unsigned int j;
1802 int match = 1;
1803
1804 /* Don't check jump instructions. */
1805 if (t->opcode_modifier.jump
1806 || t->opcode_modifier.jumpbyte
1807 || t->opcode_modifier.jumpdword
1808 || t->opcode_modifier.jumpintersegment)
1809 return match;
1810
1811 /* Check memory and accumulator operand size. */
1812 for (j = 0; j < i.operands; j++)
1813 {
1814 if (t->operand_types[j].bitfield.anysize)
1815 continue;
1816
1817 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1818 {
1819 match = 0;
1820 break;
1821 }
1822
1823 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1824 {
1825 match = 0;
1826 break;
1827 }
1828 }
1829
891edac4 1830 if (match)
5c07affc 1831 return match;
891edac4
L		 1832 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1833 {
1834mismatch:
86e026a4 1835 i.error = operand_size_mismatch;
891edac4
L		 1836 return 0;
1837 }
5c07affc
L		 1838
1839 /* Check reverse. */
9c2799c2 1840 gas_assert (i.operands == 2);
5c07affc
L		 1841
1842 match = 1;
1843 for (j = 0; j < 2; j++)
1844 {
1845 if (t->operand_types[j].bitfield.acc
1846 && !match_reg_size (t, j ? 0 : 1))
891edac4 1847 goto mismatch;
5c07affc
L		 1848
1849 if (i.types[j].bitfield.mem
1850 && !match_mem_size (t, j ? 0 : 1))
891edac4 1851 goto mismatch;
5c07affc
L		 1852 }
1853
1854 return match;
1855}
1856
c6fb90c8 1857static INLINE int
40fb9820
L		 1858operand_type_match (i386_operand_type overlap,
1859 i386_operand_type given)
1860{
1861 i386_operand_type temp = overlap;
1862
1863 temp.bitfield.jumpabsolute = 0;
7d5e4556 1864 temp.bitfield.unspecified = 0;
5c07affc
L		 1865 temp.bitfield.byte = 0;
1866 temp.bitfield.word = 0;
1867 temp.bitfield.dword = 0;
1868 temp.bitfield.fword = 0;
1869 temp.bitfield.qword = 0;
1870 temp.bitfield.tbyte = 0;
1871 temp.bitfield.xmmword = 0;
c0f3af97 1872 temp.bitfield.ymmword = 0;
43234a1e 1873 temp.bitfield.zmmword = 0;
0dfbf9d7 1874 if (operand_type_all_zero (&temp))
891edac4 1875 goto mismatch;
40fb9820 1876
891edac4
L		 1877 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1878 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1879 return 1;
1880
1881mismatch:
a65babc9 1882 i.error = operand_type_mismatch;
891edac4 1883 return 0;
40fb9820
L		 1884}
1885
7d5e4556 1886/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1887 unless the expected operand type register overlap is null.
1888 Note that Acc in a template matches every size of reg. */
1889
c6fb90c8 1890static INLINE int
40fb9820
L		 1891operand_type_register_match (i386_operand_type m0,
1892 i386_operand_type g0,
1893 i386_operand_type t0,
1894 i386_operand_type m1,
1895 i386_operand_type g1,
1896 i386_operand_type t1)
1897{
1898 if (!operand_type_check (g0, reg))
1899 return 1;
1900
1901 if (!operand_type_check (g1, reg))
1902 return 1;
1903
1904 if (g0.bitfield.reg8 == g1.bitfield.reg8
1905 && g0.bitfield.reg16 == g1.bitfield.reg16
1906 && g0.bitfield.reg32 == g1.bitfield.reg32
1907 && g0.bitfield.reg64 == g1.bitfield.reg64)
1908 return 1;
1909
1910 if (m0.bitfield.acc)
1911 {
1912 t0.bitfield.reg8 = 1;
1913 t0.bitfield.reg16 = 1;
1914 t0.bitfield.reg32 = 1;
1915 t0.bitfield.reg64 = 1;
1916 }
1917
1918 if (m1.bitfield.acc)
1919 {
1920 t1.bitfield.reg8 = 1;
1921 t1.bitfield.reg16 = 1;
1922 t1.bitfield.reg32 = 1;
1923 t1.bitfield.reg64 = 1;
1924 }
1925
891edac4
L		 1926 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1927 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1928 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1929 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1930 return 1;
1931
a65babc9 1932 i.error = register_type_mismatch;
891edac4
L		 1933
1934 return 0;
40fb9820
L		 1935}
1936
4c692bc7
JB		 1937static INLINE unsigned int
1938register_number (const reg_entry *r)
1939{
1940 unsigned int nr = r->reg_num;
1941
1942 if (r->reg_flags & RegRex)
1943 nr += 8;
1944
1945 return nr;
1946}
1947
252b5132 1948static INLINE unsigned int
40fb9820 1949mode_from_disp_size (i386_operand_type t)
252b5132 1950{
43234a1e 1951 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1952 return 1;
1953 else if (t.bitfield.disp16
1954 || t.bitfield.disp32
1955 || t.bitfield.disp32s)
1956 return 2;
1957 else
1958 return 0;
252b5132
RH		 1959}
1960
1961static INLINE int
65879393 1962fits_in_signed_byte (addressT num)
252b5132 1963{
65879393 1964 return num + 0x80 <= 0xff;
47926f60 1965}
252b5132
RH		 1966
1967static INLINE int
65879393 1968fits_in_unsigned_byte (addressT num)
252b5132 1969{
65879393 1970 return num <= 0xff;
47926f60 1971}
252b5132
RH		 1972
1973static INLINE int
65879393 1974fits_in_unsigned_word (addressT num)
252b5132 1975{
65879393 1976 return num <= 0xffff;
47926f60 1977}
252b5132
RH		 1978
1979static INLINE int
65879393 1980fits_in_signed_word (addressT num)
252b5132 1981{
65879393 1982 return num + 0x8000 <= 0xffff;
47926f60 1983}
2a962e6d 1984
3e73aa7c 1985static INLINE int
65879393 1986fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1987{
1988#ifndef BFD64
1989 return 1;
1990#else
65879393 1991 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1992#endif
1993} /* fits_in_signed_long() */
2a962e6d 1994
3e73aa7c 1995static INLINE int
65879393 1996fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1997{
1998#ifndef BFD64
1999 return 1;
2000#else
65879393 2001 return num <= 0xffffffff;
3e73aa7c
JH		 2002#endif
2003} /* fits_in_unsigned_long() */
252b5132 2004
43234a1e
L		 2005static INLINE int
2006fits_in_vec_disp8 (offsetT num)
2007{
2008 int shift = i.memshift;
2009 unsigned int mask;
2010
2011 if (shift == -1)
2012 abort ();
2013
2014 mask = (1 << shift) - 1;
2015
2016 /* Return 0 if NUM isn't properly aligned. */
2017 if ((num & mask))
2018 return 0;
2019
2020 /* Check if NUM will fit in 8bit after shift. */
2021 return fits_in_signed_byte (num >> shift);
2022}
2023
a683cc34
SP		 2024static INLINE int
2025fits_in_imm4 (offsetT num)
2026{
2027 return (num & 0xf) == num;
2028}
2029
40fb9820 2030static i386_operand_type
e3bb37b5 2031smallest_imm_type (offsetT num)
252b5132 2032{
40fb9820 2033 i386_operand_type t;
7ab9ffdd 2034
0dfbf9d7 2035 operand_type_set (&t, 0);
40fb9820
L		 2036 t.bitfield.imm64 = 1;
2037
2038 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2039 {
2040 /* This code is disabled on the 486 because all the Imm1 forms
2041 in the opcode table are slower on the i486. They're the
2042 versions with the implicitly specified single-position
2043 displacement, which has another syntax if you really want to
2044 use that form. */
40fb9820
L		 2045 t.bitfield.imm1 = 1;
2046 t.bitfield.imm8 = 1;
2047 t.bitfield.imm8s = 1;
2048 t.bitfield.imm16 = 1;
2049 t.bitfield.imm32 = 1;
2050 t.bitfield.imm32s = 1;
2051 }
2052 else if (fits_in_signed_byte (num))
2053 {
2054 t.bitfield.imm8 = 1;
2055 t.bitfield.imm8s = 1;
2056 t.bitfield.imm16 = 1;
2057 t.bitfield.imm32 = 1;
2058 t.bitfield.imm32s = 1;
2059 }
2060 else if (fits_in_unsigned_byte (num))
2061 {
2062 t.bitfield.imm8 = 1;
2063 t.bitfield.imm16 = 1;
2064 t.bitfield.imm32 = 1;
2065 t.bitfield.imm32s = 1;
2066 }
2067 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2068 {
2069 t.bitfield.imm16 = 1;
2070 t.bitfield.imm32 = 1;
2071 t.bitfield.imm32s = 1;
2072 }
2073 else if (fits_in_signed_long (num))
2074 {
2075 t.bitfield.imm32 = 1;
2076 t.bitfield.imm32s = 1;
2077 }
2078 else if (fits_in_unsigned_long (num))
2079 t.bitfield.imm32 = 1;
2080
2081 return t;
47926f60 2082}
252b5132 2083
847f7ad4 2084static offsetT
e3bb37b5 2085offset_in_range (offsetT val, int size)
847f7ad4 2086{
508866be 2087 addressT mask;
ba2adb93 2088
847f7ad4
AM		 2089 switch (size)
2090 {
508866be
L		 2091 case 1: mask = ((addressT) 1 << 8) - 1; break;
2092 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2093 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2094#ifdef BFD64
2095 case 8: mask = ((addressT) 2 << 63) - 1; break;
2096#endif
47926f60 2097 default: abort ();
847f7ad4
AM		 2098 }
2099
9de868bf
L		 2100#ifdef BFD64
2101 /* If BFD64, sign extend val for 32bit address mode. */
2102 if (flag_code != CODE_64BIT
2103 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2104 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2105 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2106#endif
ba2adb93 2107
47926f60 2108 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2109 {
2110 char buf1[40], buf2[40];
2111
2112 sprint_value (buf1, val);
2113 sprint_value (buf2, val & mask);
2114 as_warn (_("%s shortened to %s"), buf1, buf2);
2115 }
2116 return val & mask;
2117}
2118
c32fa91d
L		 2119enum PREFIX_GROUP
2120{
2121 PREFIX_EXIST = 0,
2122 PREFIX_LOCK,
2123 PREFIX_REP,
2124 PREFIX_OTHER
2125};
2126
2127/* Returns
2128 a. PREFIX_EXIST if attempting to add a prefix where one from the
2129 same class already exists.
2130 b. PREFIX_LOCK if lock prefix is added.
2131 c. PREFIX_REP if rep/repne prefix is added.
2132 d. PREFIX_OTHER if other prefix is added.
2133 */
2134
2135static enum PREFIX_GROUP
e3bb37b5 2136add_prefix (unsigned int prefix)
252b5132 2137{
c32fa91d 2138 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2139 unsigned int q;
252b5132 2140
29b0f896
AM		 2141 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2142 && flag_code == CODE_64BIT)
b1905489 2143 {
161a04f6
L		 2144 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2145 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2146 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2147 ret = PREFIX_EXIST;
b1905489
JB		 2148 q = REX_PREFIX;
2149 }
3e73aa7c 2150 else
b1905489
JB		 2151 {
2152 switch (prefix)
2153 {
2154 default:
2155 abort ();
2156
2157 case CS_PREFIX_OPCODE:
2158 case DS_PREFIX_OPCODE:
2159 case ES_PREFIX_OPCODE:
2160 case FS_PREFIX_OPCODE:
2161 case GS_PREFIX_OPCODE:
2162 case SS_PREFIX_OPCODE:
2163 q = SEG_PREFIX;
2164 break;
2165
2166 case REPNE_PREFIX_OPCODE:
2167 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2168 q = REP_PREFIX;
2169 ret = PREFIX_REP;
2170 break;
2171
b1905489 2172 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2173 q = LOCK_PREFIX;
2174 ret = PREFIX_LOCK;
b1905489
JB		 2175 break;
2176
2177 case FWAIT_OPCODE:
2178 q = WAIT_PREFIX;
2179 break;
2180
2181 case ADDR_PREFIX_OPCODE:
2182 q = ADDR_PREFIX;
2183 break;
2184
2185 case DATA_PREFIX_OPCODE:
2186 q = DATA_PREFIX;
2187 break;
2188 }
2189 if (i.prefix[q] != 0)
c32fa91d 2190 ret = PREFIX_EXIST;
b1905489 2191 }
252b5132 2192
b1905489 2193 if (ret)
252b5132 2194 {
b1905489
JB		 2195 if (!i.prefix[q])
2196 ++i.prefixes;
2197 i.prefix[q] |= prefix;
252b5132 2198 }
b1905489
JB		 2199 else
2200 as_bad (_("same type of prefix used twice"));
252b5132 2201
252b5132
RH		 2202 return ret;
2203}
2204
2205static void
78f12dd3 2206update_code_flag (int value, int check)
eecb386c 2207{
78f12dd3
L		 2208 PRINTF_LIKE ((*as_error));
2209
1e9cc1c2 2210 flag_code = (enum flag_code) value;
40fb9820
L		 2211 if (flag_code == CODE_64BIT)
2212 {
2213 cpu_arch_flags.bitfield.cpu64 = 1;
2214 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2215 }
2216 else
2217 {
2218 cpu_arch_flags.bitfield.cpu64 = 0;
2219 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2220 }
2221 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2222 {
78f12dd3
L		 2223 if (check)
2224 as_error = as_fatal;
2225 else
2226 as_error = as_bad;
2227 (*as_error) (_("64bit mode not supported on `%s'."),
2228 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2229 }
40fb9820 2230 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2231 {
78f12dd3
L		 2232 if (check)
2233 as_error = as_fatal;
2234 else
2235 as_error = as_bad;
2236 (*as_error) (_("32bit mode not supported on `%s'."),
2237 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2238 }
eecb386c
AM		 2239 stackop_size = '\0';
2240}
2241
78f12dd3
L		 2242static void
2243set_code_flag (int value)
2244{
2245 update_code_flag (value, 0);
2246}
2247
eecb386c 2248static void
e3bb37b5 2249set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2250{
1e9cc1c2 2251 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2252 if (flag_code != CODE_16BIT)
2253 abort ();
2254 cpu_arch_flags.bitfield.cpu64 = 0;
2255 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2256 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2257}
2258
2259static void
e3bb37b5 2260set_intel_syntax (int syntax_flag)
252b5132
RH		 2261{
2262 /* Find out if register prefixing is specified. */
2263 int ask_naked_reg = 0;
2264
2265 SKIP_WHITESPACE ();
29b0f896 2266 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2267 {
2268 char *string = input_line_pointer;
2269 int e = get_symbol_end ();
2270
47926f60 2271 if (strcmp (string, "prefix") == 0)
252b5132 2272 ask_naked_reg = 1;
47926f60 2273 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2274 ask_naked_reg = -1;
2275 else
d0b47220 2276 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2277 *input_line_pointer = e;
2278 }
2279 demand_empty_rest_of_line ();
c3332e24 2280
252b5132
RH		 2281 intel_syntax = syntax_flag;
2282
2283 if (ask_naked_reg == 0)
f86103b7
AM		 2284 allow_naked_reg = (intel_syntax
2285 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2286 else
2287 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2288
ee86248c 2289 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2290
e4a3b5a4 2291 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2292 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2293 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2294}
2295
1efbbeb4
L		 2296static void
2297set_intel_mnemonic (int mnemonic_flag)
2298{
e1d4d893 2299 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2300}
2301
db51cc60
L		 2302static void
2303set_allow_index_reg (int flag)
2304{
2305 allow_index_reg = flag;
2306}
2307
cb19c032 2308static void
7bab8ab5 2309set_check (int what)
cb19c032 2310{
7bab8ab5
JB		 2311 enum check_kind *kind;
2312 const char *str;
2313
2314 if (what)
2315 {
2316 kind = &operand_check;
2317 str = "operand";
2318 }
2319 else
2320 {
2321 kind = &sse_check;
2322 str = "sse";
2323 }
2324
cb19c032
L		 2325 SKIP_WHITESPACE ();
2326
2327 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2328 {
2329 char *string = input_line_pointer;
2330 int e = get_symbol_end ();
2331
2332 if (strcmp (string, "none") == 0)
7bab8ab5 2333 *kind = check_none;
cb19c032 2334 else if (strcmp (string, "warning") == 0)
7bab8ab5 2335 *kind = check_warning;
cb19c032 2336 else if (strcmp (string, "error") == 0)
7bab8ab5 2337 *kind = check_error;
cb19c032 2338 else
7bab8ab5 2339 as_bad (_("bad argument to %s_check directive."), str);
cb19c032
L		 2340 *input_line_pointer = e;
2341 }
2342 else
7bab8ab5 2343 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2344
2345 demand_empty_rest_of_line ();
2346}
2347
8a9036a4
L		 2348static void
2349check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2350 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2351{
2352#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2353 static const char *arch;
2354
2355 /* Intel LIOM is only supported on ELF. */
2356 if (!IS_ELF)
2357 return;
2358
2359 if (!arch)
2360 {
2361 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2362 use default_arch. */
2363 arch = cpu_arch_name;
2364 if (!arch)
2365 arch = default_arch;
2366 }
2367
3632d14b 2368 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2369 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2370 || new_flag.bitfield.cpul1om)
8a9036a4 2371 return;
76ba9986 2372
7a9068fe
L		 2373 /* If we are targeting Intel K1OM, we must enable it. */
2374 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2375 || new_flag.bitfield.cpuk1om)
2376 return;
2377
8a9036a4
L		 2378 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2379#endif
2380}
2381
e413e4e9 2382static void
e3bb37b5 2383set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2384{
47926f60 2385 SKIP_WHITESPACE ();
e413e4e9 2386
29b0f896 2387 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2388 {
2389 char *string = input_line_pointer;
2390 int e = get_symbol_end ();
91d6fa6a 2391 unsigned int j;
40fb9820 2392 i386_cpu_flags flags;
e413e4e9 2393
91d6fa6a 2394 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2395 {
91d6fa6a 2396 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2397 {
91d6fa6a 2398 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2399
5c6af06e
JB		 2400 if (*string != '.')
2401 {
91d6fa6a 2402 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2403 cpu_sub_arch_name = NULL;
91d6fa6a 2404 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2405 if (flag_code == CODE_64BIT)
2406 {
2407 cpu_arch_flags.bitfield.cpu64 = 1;
2408 cpu_arch_flags.bitfield.cpuno64 = 0;
2409 }
2410 else
2411 {
2412 cpu_arch_flags.bitfield.cpu64 = 0;
2413 cpu_arch_flags.bitfield.cpuno64 = 1;
2414 }
91d6fa6a
NC		 2415 cpu_arch_isa = cpu_arch[j].type;
2416 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2417 if (!cpu_arch_tune_set)
2418 {
2419 cpu_arch_tune = cpu_arch_isa;
2420 cpu_arch_tune_flags = cpu_arch_isa_flags;
2421 }
5c6af06e
JB		 2422 break;
2423 }
40fb9820 2424
22109423 2425 if (!cpu_arch[j].negated)
309d3373 2426 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2427 cpu_arch[j].flags);
309d3373
JB		 2428 else
2429 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2430 cpu_arch[j].flags);
0dfbf9d7 2431 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2432 {
6305a203
L		 2433 if (cpu_sub_arch_name)
2434 {
2435 char *name = cpu_sub_arch_name;
2436 cpu_sub_arch_name = concat (name,
91d6fa6a 2437 cpu_arch[j].name,
1bf57e9f 2438 (const char *) NULL);
6305a203
L		 2439 free (name);
2440 }
2441 else
91d6fa6a 2442 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2443 cpu_arch_flags = flags;
a586129e 2444 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2445 }
2446 *input_line_pointer = e;
2447 demand_empty_rest_of_line ();
2448 return;
e413e4e9
AM		 2449 }
2450 }
91d6fa6a 2451 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2452 as_bad (_("no such architecture: `%s'"), string);
2453
2454 *input_line_pointer = e;
2455 }
2456 else
2457 as_bad (_("missing cpu architecture"));
2458
fddf5b5b
AM		 2459 no_cond_jump_promotion = 0;
2460 if (*input_line_pointer == ','
29b0f896 2461 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2462 {
2463 char *string = ++input_line_pointer;
2464 int e = get_symbol_end ();
2465
2466 if (strcmp (string, "nojumps") == 0)
2467 no_cond_jump_promotion = 1;
2468 else if (strcmp (string, "jumps") == 0)
2469 ;
2470 else
2471 as_bad (_("no such architecture modifier: `%s'"), string);
2472
2473 *input_line_pointer = e;
2474 }
2475
e413e4e9
AM		 2476 demand_empty_rest_of_line ();
2477}
2478
8a9036a4
L		 2479enum bfd_architecture
2480i386_arch (void)
2481{
3632d14b 2482 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2483 {
2484 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2485 || flag_code != CODE_64BIT)
2486 as_fatal (_("Intel L1OM is 64bit ELF only"));
2487 return bfd_arch_l1om;
2488 }
7a9068fe
L		 2489 else if (cpu_arch_isa == PROCESSOR_K1OM)
2490 {
2491 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2492 || flag_code != CODE_64BIT)
2493 as_fatal (_("Intel K1OM is 64bit ELF only"));
2494 return bfd_arch_k1om;
2495 }
8a9036a4
L		 2496 else
2497 return bfd_arch_i386;
2498}
2499
b9d79e03 2500unsigned long
7016a5d5 2501i386_mach (void)
b9d79e03 2502{
351f65ca 2503 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2504 {
3632d14b 2505 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2506 {
351f65ca
L		 2507 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2508 || default_arch[6] != '\0')
8a9036a4
L		 2509 as_fatal (_("Intel L1OM is 64bit ELF only"));
2510 return bfd_mach_l1om;
2511 }
7a9068fe
L		 2512 else if (cpu_arch_isa == PROCESSOR_K1OM)
2513 {
2514 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2515 || default_arch[6] != '\0')
2516 as_fatal (_("Intel K1OM is 64bit ELF only"));
2517 return bfd_mach_k1om;
2518 }
351f65ca 2519 else if (default_arch[6] == '\0')
8a9036a4 2520 return bfd_mach_x86_64;
351f65ca
L		 2521 else
2522 return bfd_mach_x64_32;
8a9036a4 2523 }
b9d79e03
JH		 2524 else if (!strcmp (default_arch, "i386"))
2525 return bfd_mach_i386_i386;
2526 else
2b5d6a91 2527 as_fatal (_("unknown architecture"));
b9d79e03 2528}
b9d79e03 2529\f
252b5132 2530void
7016a5d5 2531md_begin (void)
252b5132
RH		 2532{
2533 const char *hash_err;
2534
47926f60 2535 /* Initialize op_hash hash table. */
252b5132
RH		 2536 op_hash = hash_new ();
2537
2538 {
d3ce72d0 2539 const insn_template *optab;
29b0f896 2540 templates *core_optab;
252b5132 2541
47926f60
KH		 2542 /* Setup for loop. */
2543 optab = i386_optab;
252b5132
RH		 2544 core_optab = (templates *) xmalloc (sizeof (templates));
2545 core_optab->start = optab;
2546
2547 while (1)
2548 {
2549 ++optab;
2550 if (optab->name == NULL
2551 || strcmp (optab->name, (optab - 1)->name) != 0)
2552 {
2553 /* different name --> ship out current template list;
47926f60 2554 add to hash table; & begin anew. */
252b5132
RH		 2555 core_optab->end = optab;
2556 hash_err = hash_insert (op_hash,
2557 (optab - 1)->name,
5a49b8ac 2558 (void *) core_optab);
252b5132
RH		 2559 if (hash_err)
2560 {
b37df7c4 2561 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2562 (optab - 1)->name,
2563 hash_err);
2564 }
2565 if (optab->name == NULL)
2566 break;
2567 core_optab = (templates *) xmalloc (sizeof (templates));
2568 core_optab->start = optab;
2569 }
2570 }
2571 }
2572
47926f60 2573 /* Initialize reg_hash hash table. */
252b5132
RH		 2574 reg_hash = hash_new ();
2575 {
29b0f896 2576 const reg_entry *regtab;
c3fe08fa 2577 unsigned int regtab_size = i386_regtab_size;
252b5132 2578
c3fe08fa 2579 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2580 {
5a49b8ac 2581 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2582 if (hash_err)
b37df7c4 2583 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2584 regtab->reg_name,
2585 hash_err);
252b5132
RH		 2586 }
2587 }
2588
47926f60 2589 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2590 {
29b0f896
AM		 2591 int c;
2592 char *p;
252b5132
RH		 2593
2594 for (c = 0; c < 256; c++)
2595 {
3882b010 2596 if (ISDIGIT (c))
252b5132
RH		 2597 {
2598 digit_chars[c] = c;
2599 mnemonic_chars[c] = c;
2600 register_chars[c] = c;
2601 operand_chars[c] = c;
2602 }
3882b010 2603 else if (ISLOWER (c))
252b5132
RH		 2604 {
2605 mnemonic_chars[c] = c;
2606 register_chars[c] = c;
2607 operand_chars[c] = c;
2608 }
3882b010 2609 else if (ISUPPER (c))
252b5132 2610 {
3882b010 2611 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2612 register_chars[c] = mnemonic_chars[c];
2613 operand_chars[c] = c;
2614 }
43234a1e
L		 2615 else if (c == '{' || c == '}')
2616 operand_chars[c] = c;
252b5132 2617
3882b010 2618 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2619 identifier_chars[c] = c;
2620 else if (c >= 128)
2621 {
2622 identifier_chars[c] = c;
2623 operand_chars[c] = c;
2624 }
2625 }
2626
2627#ifdef LEX_AT
2628 identifier_chars['@'] = '@';
32137342
NC		 2629#endif
2630#ifdef LEX_QM
2631 identifier_chars['?'] = '?';
2632 operand_chars['?'] = '?';
252b5132 2633#endif
252b5132 2634 digit_chars['-'] = '-';
c0f3af97 2635 mnemonic_chars['_'] = '_';
791fe849 2636 mnemonic_chars['-'] = '-';
0003779b 2637 mnemonic_chars['.'] = '.';
252b5132
RH		 2638 identifier_chars['_'] = '_';
2639 identifier_chars['.'] = '.';
2640
2641 for (p = operand_special_chars; *p != '\0'; p++)
2642 operand_chars[(unsigned char) *p] = *p;
2643 }
2644
a4447b93
RH		 2645 if (flag_code == CODE_64BIT)
2646 {
ca19b261
KT		 2647#if defined (OBJ_COFF) && defined (TE_PE)
2648 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2649 ? 32 : 16);
2650#else
a4447b93 2651 x86_dwarf2_return_column = 16;
ca19b261 2652#endif
61ff971f 2653 x86_cie_data_alignment = -8;
a4447b93
RH		 2654 }
2655 else
2656 {
2657 x86_dwarf2_return_column = 8;
2658 x86_cie_data_alignment = -4;
2659 }
252b5132
RH		 2660}
2661
2662void
e3bb37b5 2663i386_print_statistics (FILE *file)
252b5132
RH		 2664{
2665 hash_print_statistics (file, "i386 opcode", op_hash);
2666 hash_print_statistics (file, "i386 register", reg_hash);
2667}
2668\f
252b5132
RH		 2669#ifdef DEBUG386
2670
ce8a8b2f 2671/* Debugging routines for md_assemble. */
d3ce72d0 2672static void pte (insn_template *);
40fb9820 2673static void pt (i386_operand_type);
e3bb37b5
L		 2674static void pe (expressionS *);
2675static void ps (symbolS *);
252b5132
RH		 2676
2677static void
e3bb37b5 2678pi (char *line, i386_insn *x)
252b5132 2679{
09137c09 2680 unsigned int j;
252b5132
RH		 2681
2682 fprintf (stdout, "%s: template ", line);
2683 pte (&x->tm);
09f131f2
JH		 2684 fprintf (stdout, " address: base %s index %s scale %x\n",
2685 x->base_reg ? x->base_reg->reg_name : "none",
2686 x->index_reg ? x->index_reg->reg_name : "none",
2687 x->log2_scale_factor);
2688 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2689 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2690 fprintf (stdout, " sib: base %x index %x scale %x\n",
2691 x->sib.base, x->sib.index, x->sib.scale);
2692 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2693 (x->rex & REX_W) != 0,
2694 (x->rex & REX_R) != 0,
2695 (x->rex & REX_X) != 0,
2696 (x->rex & REX_B) != 0);
09137c09 2697 for (j = 0; j < x->operands; j++)
252b5132 2698 {
09137c09
SP		 2699 fprintf (stdout, " #%d: ", j + 1);
2700 pt (x->types[j]);
252b5132 2701 fprintf (stdout, "\n");
09137c09
SP		 2702 if (x->types[j].bitfield.reg8
2703 || x->types[j].bitfield.reg16
2704 || x->types[j].bitfield.reg32
2705 || x->types[j].bitfield.reg64
2706 || x->types[j].bitfield.regmmx
2707 || x->types[j].bitfield.regxmm
2708 || x->types[j].bitfield.regymm
43234a1e 2709 || x->types[j].bitfield.regzmm
09137c09
SP		 2710 || x->types[j].bitfield.sreg2
2711 || x->types[j].bitfield.sreg3
2712 || x->types[j].bitfield.control
2713 || x->types[j].bitfield.debug
2714 || x->types[j].bitfield.test)
2715 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2716 if (operand_type_check (x->types[j], imm))
2717 pe (x->op[j].imms);
2718 if (operand_type_check (x->types[j], disp))
2719 pe (x->op[j].disps);
252b5132
RH		 2720 }
2721}
2722
2723static void
d3ce72d0 2724pte (insn_template *t)
252b5132 2725{
09137c09 2726 unsigned int j;
252b5132 2727 fprintf (stdout, " %d operands ", t->operands);
47926f60 2728 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2729 if (t->extension_opcode != None)
2730 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2731 if (t->opcode_modifier.d)
252b5132 2732 fprintf (stdout, "D");
40fb9820 2733 if (t->opcode_modifier.w)
252b5132
RH		 2734 fprintf (stdout, "W");
2735 fprintf (stdout, "\n");
09137c09 2736 for (j = 0; j < t->operands; j++)
252b5132 2737 {
09137c09
SP		 2738 fprintf (stdout, " #%d type ", j + 1);
2739 pt (t->operand_types[j]);
252b5132
RH		 2740 fprintf (stdout, "\n");
2741 }
2742}
2743
2744static void
e3bb37b5 2745pe (expressionS *e)
252b5132 2746{
24eab124 2747 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2748 fprintf (stdout, " add_number %ld (%lx)\n",
2749 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2750 if (e->X_add_symbol)
2751 {
2752 fprintf (stdout, " add_symbol ");
2753 ps (e->X_add_symbol);
2754 fprintf (stdout, "\n");
2755 }
2756 if (e->X_op_symbol)
2757 {
2758 fprintf (stdout, " op_symbol ");
2759 ps (e->X_op_symbol);
2760 fprintf (stdout, "\n");
2761 }
2762}
2763
2764static void
e3bb37b5 2765ps (symbolS *s)
252b5132
RH		 2766{
2767 fprintf (stdout, "%s type %s%s",
2768 S_GET_NAME (s),
2769 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2770 segment_name (S_GET_SEGMENT (s)));
2771}
2772
7b81dfbb 2773static struct type_name
252b5132 2774 {
40fb9820
L		 2775 i386_operand_type mask;
2776 const char *name;
252b5132 2777 }
7b81dfbb 2778const type_names[] =
252b5132 2779{
40fb9820
L		 2780 { OPERAND_TYPE_REG8, "r8" },
2781 { OPERAND_TYPE_REG16, "r16" },
2782 { OPERAND_TYPE_REG32, "r32" },
2783 { OPERAND_TYPE_REG64, "r64" },
2784 { OPERAND_TYPE_IMM8, "i8" },
2785 { OPERAND_TYPE_IMM8, "i8s" },
2786 { OPERAND_TYPE_IMM16, "i16" },
2787 { OPERAND_TYPE_IMM32, "i32" },
2788 { OPERAND_TYPE_IMM32S, "i32s" },
2789 { OPERAND_TYPE_IMM64, "i64" },
2790 { OPERAND_TYPE_IMM1, "i1" },
2791 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2792 { OPERAND_TYPE_DISP8, "d8" },
2793 { OPERAND_TYPE_DISP16, "d16" },
2794 { OPERAND_TYPE_DISP32, "d32" },
2795 { OPERAND_TYPE_DISP32S, "d32s" },
2796 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2797 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2798 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2799 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2800 { OPERAND_TYPE_CONTROL, "control reg" },
2801 { OPERAND_TYPE_TEST, "test reg" },
2802 { OPERAND_TYPE_DEBUG, "debug reg" },
2803 { OPERAND_TYPE_FLOATREG, "FReg" },
2804 { OPERAND_TYPE_FLOATACC, "FAcc" },
2805 { OPERAND_TYPE_SREG2, "SReg2" },
2806 { OPERAND_TYPE_SREG3, "SReg3" },
2807 { OPERAND_TYPE_ACC, "Acc" },
2808 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2809 { OPERAND_TYPE_REGMMX, "rMMX" },
2810 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2811 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2812 { OPERAND_TYPE_REGZMM, "rZMM" },
2813 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2814 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2815};
2816
2817static void
40fb9820 2818pt (i386_operand_type t)
252b5132 2819{
40fb9820 2820 unsigned int j;
c6fb90c8 2821 i386_operand_type a;
252b5132 2822
40fb9820 2823 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2824 {
2825 a = operand_type_and (t, type_names[j].mask);
0349dc08 2826 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2827 fprintf (stdout, "%s, ", type_names[j].name);
2828 }
252b5132
RH		 2829 fflush (stdout);
2830}
2831
2832#endif /* DEBUG386 */
2833\f
252b5132 2834static bfd_reloc_code_real_type
3956db08 2835reloc (unsigned int size,
64e74474
AM		 2836 int pcrel,
2837 int sign,
2838 bfd_reloc_code_real_type other)
252b5132 2839{
47926f60 2840 if (other != NO_RELOC)
3956db08 2841 {
91d6fa6a 2842 reloc_howto_type *rel;
3956db08
JB		 2843
2844 if (size == 8)
2845 switch (other)
2846 {
64e74474
AM		 2847 case BFD_RELOC_X86_64_GOT32:
2848 return BFD_RELOC_X86_64_GOT64;
2849 break;
553d1284
L		 2850 case BFD_RELOC_X86_64_GOTPLT64:
2851 return BFD_RELOC_X86_64_GOTPLT64;
2852 break;
64e74474
AM		 2853 case BFD_RELOC_X86_64_PLTOFF64:
2854 return BFD_RELOC_X86_64_PLTOFF64;
2855 break;
2856 case BFD_RELOC_X86_64_GOTPC32:
2857 other = BFD_RELOC_X86_64_GOTPC64;
2858 break;
2859 case BFD_RELOC_X86_64_GOTPCREL:
2860 other = BFD_RELOC_X86_64_GOTPCREL64;
2861 break;
2862 case BFD_RELOC_X86_64_TPOFF32:
2863 other = BFD_RELOC_X86_64_TPOFF64;
2864 break;
2865 case BFD_RELOC_X86_64_DTPOFF32:
2866 other = BFD_RELOC_X86_64_DTPOFF64;
2867 break;
2868 default:
2869 break;
3956db08 2870 }
e05278af 2871
8ce3d284 2872#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2873 if (other == BFD_RELOC_SIZE32)
2874 {
2875 if (size == 8)
1ab668bf 2876 other = BFD_RELOC_SIZE64;
8fd4256d 2877 if (pcrel)
1ab668bf
AM		 2878 {
2879 as_bad (_("there are no pc-relative size relocations"));
2880 return NO_RELOC;
2881 }
8fd4256d 2882 }
8ce3d284 2883#endif
8fd4256d 2884
e05278af 2885 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2886 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2887 sign = -1;
2888
91d6fa6a
NC		 2889 rel = bfd_reloc_type_lookup (stdoutput, other);
2890 if (!rel)
3956db08 2891 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2892 else if (size != bfd_get_reloc_size (rel))
3956db08 2893 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2894 bfd_get_reloc_size (rel),
3956db08 2895 size);
91d6fa6a 2896 else if (pcrel && !rel->pc_relative)
3956db08 2897 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2898 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2899 && !sign)
91d6fa6a 2900 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2901 && sign > 0))
3956db08
JB		 2902 as_bad (_("relocated field and relocation type differ in signedness"));
2903 else
2904 return other;
2905 return NO_RELOC;
2906 }
252b5132
RH		 2907
2908 if (pcrel)
2909 {
3e73aa7c 2910 if (!sign)
3956db08 2911 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2912 switch (size)
2913 {
2914 case 1: return BFD_RELOC_8_PCREL;
2915 case 2: return BFD_RELOC_16_PCREL;
d258b828 2916 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2917 case 8: return BFD_RELOC_64_PCREL;
252b5132 2918 }
3956db08 2919 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2920 }
2921 else
2922 {
3956db08 2923 if (sign > 0)
e5cb08ac 2924 switch (size)
3e73aa7c
JH		 2925 {
2926 case 4: return BFD_RELOC_X86_64_32S;
2927 }
2928 else
2929 switch (size)
2930 {
2931 case 1: return BFD_RELOC_8;
2932 case 2: return BFD_RELOC_16;
2933 case 4: return BFD_RELOC_32;
2934 case 8: return BFD_RELOC_64;
2935 }
3956db08
JB		 2936 as_bad (_("cannot do %s %u byte relocation"),
2937 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2938 }
2939
0cc9e1d3 2940 return NO_RELOC;
252b5132
RH		 2941}
2942
47926f60
KH		 2943/* Here we decide which fixups can be adjusted to make them relative to
2944 the beginning of the section instead of the symbol. Basically we need
2945 to make sure that the dynamic relocations are done correctly, so in
2946 some cases we force the original symbol to be used. */
2947
252b5132 2948int
e3bb37b5 2949tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2950{
6d249963 2951#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2952 if (!IS_ELF)
31312f95
AM		 2953 return 1;
2954
a161fe53
AM		 2955 /* Don't adjust pc-relative references to merge sections in 64-bit
2956 mode. */
2957 if (use_rela_relocations
2958 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2959 && fixP->fx_pcrel)
252b5132 2960 return 0;
31312f95 2961
8d01d9a9
AJ		 2962 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2963 and changed later by validate_fix. */
2964 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2965 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2966 return 0;
2967
8fd4256d
L		 2968 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2969 for size relocations. */
2970 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2971 || fixP->fx_r_type == BFD_RELOC_SIZE64
2972 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2973 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2974 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2975 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2976 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2977 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2978 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2979 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2980 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2981 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2982 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2983 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2984 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2985 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2986 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2987 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2988 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2989 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2990 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2991 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2992 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2993 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2994 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2995 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2996 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2997 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2998 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2999 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3000 return 0;
31312f95 3001#endif
252b5132
RH		 3002 return 1;
3003}
252b5132 3004
b4cac588 3005static int
e3bb37b5 3006intel_float_operand (const char *mnemonic)
252b5132 3007{
9306ca4a
JB		 3008 /* Note that the value returned is meaningful only for opcodes with (memory)
3009 operands, hence the code here is free to improperly handle opcodes that
3010 have no operands (for better performance and smaller code). */
3011
3012 if (mnemonic[0] != 'f')
3013 return 0; /* non-math */
3014
3015 switch (mnemonic[1])
3016 {
3017 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3018 the fs segment override prefix not currently handled because no
3019 call path can make opcodes without operands get here */
3020 case 'i':
3021 return 2 /* integer op */;
3022 case 'l':
3023 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3024 return 3; /* fldcw/fldenv */
3025 break;
3026 case 'n':
3027 if (mnemonic[2] != 'o' /* fnop */)
3028 return 3; /* non-waiting control op */
3029 break;
3030 case 'r':
3031 if (mnemonic[2] == 's')
3032 return 3; /* frstor/frstpm */
3033 break;
3034 case 's':
3035 if (mnemonic[2] == 'a')
3036 return 3; /* fsave */
3037 if (mnemonic[2] == 't')
3038 {
3039 switch (mnemonic[3])
3040 {
3041 case 'c': /* fstcw */
3042 case 'd': /* fstdw */
3043 case 'e': /* fstenv */
3044 case 's': /* fsts[gw] */
3045 return 3;
3046 }
3047 }
3048 break;
3049 case 'x':
3050 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3051 return 0; /* fxsave/fxrstor are not really math ops */
3052 break;
3053 }
252b5132 3054
9306ca4a 3055 return 1;
252b5132
RH		 3056}
3057
c0f3af97
L		 3058/* Build the VEX prefix. */
3059
3060static void
d3ce72d0 3061build_vex_prefix (const insn_template *t)
c0f3af97
L		 3062{
3063 unsigned int register_specifier;
3064 unsigned int implied_prefix;
3065 unsigned int vector_length;
3066
3067 /* Check register specifier. */
3068 if (i.vex.register_specifier)
43234a1e
L		 3069 {
3070 register_specifier =
3071 ~register_number (i.vex.register_specifier) & 0xf;
3072 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3073 }
c0f3af97
L		 3074 else
3075 register_specifier = 0xf;
3076
fa99fab2
L		 3077 /* Use 2-byte VEX prefix by swappping destination and source
3078 operand. */
3079 if (!i.swap_operand
3080 && i.operands == i.reg_operands
7f399153 3081 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3082 && i.tm.opcode_modifier.s
3083 && i.rex == REX_B)
3084 {
3085 unsigned int xchg = i.operands - 1;
3086 union i386_op temp_op;
3087 i386_operand_type temp_type;
3088
3089 temp_type = i.types[xchg];
3090 i.types[xchg] = i.types[0];
3091 i.types[0] = temp_type;
3092 temp_op = i.op[xchg];
3093 i.op[xchg] = i.op[0];
3094 i.op[0] = temp_op;
3095
9c2799c2 3096 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3097
3098 i.rex = REX_R;
3099 xchg = i.rm.regmem;
3100 i.rm.regmem = i.rm.reg;
3101 i.rm.reg = xchg;
3102
3103 /* Use the next insn. */
3104 i.tm = t[1];
3105 }
3106
539f890d
L		 3107 if (i.tm.opcode_modifier.vex == VEXScalar)
3108 vector_length = avxscalar;
3109 else
3110 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3111
3112 switch ((i.tm.base_opcode >> 8) & 0xff)
3113 {
3114 case 0:
3115 implied_prefix = 0;
3116 break;
3117 case DATA_PREFIX_OPCODE:
3118 implied_prefix = 1;
3119 break;
3120 case REPE_PREFIX_OPCODE:
3121 implied_prefix = 2;
3122 break;
3123 case REPNE_PREFIX_OPCODE:
3124 implied_prefix = 3;
3125 break;
3126 default:
3127 abort ();
3128 }
3129
3130 /* Use 2-byte VEX prefix if possible. */
7f399153 3131 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3132 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3133 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3134 {
3135 /* 2-byte VEX prefix. */
3136 unsigned int r;
3137
3138 i.vex.length = 2;
3139 i.vex.bytes[0] = 0xc5;
3140
3141 /* Check the REX.R bit. */
3142 r = (i.rex & REX_R) ? 0 : 1;
3143 i.vex.bytes[1] = (r << 7
3144 | register_specifier << 3
3145 | vector_length << 2
3146 | implied_prefix);
3147 }
3148 else
3149 {
3150 /* 3-byte VEX prefix. */
3151 unsigned int m, w;
3152
f88c9eb0 3153 i.vex.length = 3;
f88c9eb0 3154
7f399153 3155 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3156 {
7f399153
L		 3157 case VEX0F:
3158 m = 0x1;
80de6e00 3159 i.vex.bytes[0] = 0xc4;
7f399153
L		 3160 break;
3161 case VEX0F38:
3162 m = 0x2;
80de6e00 3163 i.vex.bytes[0] = 0xc4;
7f399153
L		 3164 break;
3165 case VEX0F3A:
3166 m = 0x3;
80de6e00 3167 i.vex.bytes[0] = 0xc4;
7f399153
L		 3168 break;
3169 case XOP08:
5dd85c99
SP		 3170 m = 0x8;
3171 i.vex.bytes[0] = 0x8f;
7f399153
L		 3172 break;
3173 case XOP09:
f88c9eb0
SP		 3174 m = 0x9;
3175 i.vex.bytes[0] = 0x8f;
7f399153
L		 3176 break;
3177 case XOP0A:
f88c9eb0
SP		 3178 m = 0xa;
3179 i.vex.bytes[0] = 0x8f;
7f399153
L		 3180 break;
3181 default:
3182 abort ();
f88c9eb0 3183 }
c0f3af97 3184
c0f3af97
L		 3185 /* The high 3 bits of the second VEX byte are 1's compliment
3186 of RXB bits from REX. */
3187 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3188
3189 /* Check the REX.W bit. */
3190 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3191 if (i.tm.opcode_modifier.vexw == VEXW1)
3192 w = 1;
c0f3af97
L		 3193
3194 i.vex.bytes[2] = (w << 7
3195 | register_specifier << 3
3196 | vector_length << 2
3197 | implied_prefix);
3198 }
3199}
3200
43234a1e
L		 3201/* Build the EVEX prefix. */
3202
3203static void
3204build_evex_prefix (void)
3205{
3206 unsigned int register_specifier;
3207 unsigned int implied_prefix;
3208 unsigned int m, w;
3209 rex_byte vrex_used = 0;
3210
3211 /* Check register specifier. */
3212 if (i.vex.register_specifier)
3213 {
3214 gas_assert ((i.vrex & REX_X) == 0);
3215
3216 register_specifier = i.vex.register_specifier->reg_num;
3217 if ((i.vex.register_specifier->reg_flags & RegRex))
3218 register_specifier += 8;
3219 /* The upper 16 registers are encoded in the fourth byte of the
3220 EVEX prefix. */
3221 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3222 i.vex.bytes[3] = 0x8;
3223 register_specifier = ~register_specifier & 0xf;
3224 }
3225 else
3226 {
3227 register_specifier = 0xf;
3228
3229 /* Encode upper 16 vector index register in the fourth byte of
3230 the EVEX prefix. */
3231 if (!(i.vrex & REX_X))
3232 i.vex.bytes[3] = 0x8;
3233 else
3234 vrex_used |= REX_X;
3235 }
3236
3237 switch ((i.tm.base_opcode >> 8) & 0xff)
3238 {
3239 case 0:
3240 implied_prefix = 0;
3241 break;
3242 case DATA_PREFIX_OPCODE:
3243 implied_prefix = 1;
3244 break;
3245 case REPE_PREFIX_OPCODE:
3246 implied_prefix = 2;
3247 break;
3248 case REPNE_PREFIX_OPCODE:
3249 implied_prefix = 3;
3250 break;
3251 default:
3252 abort ();
3253 }
3254
3255 /* 4 byte EVEX prefix. */
3256 i.vex.length = 4;
3257 i.vex.bytes[0] = 0x62;
3258
3259 /* mmmm bits. */
3260 switch (i.tm.opcode_modifier.vexopcode)
3261 {
3262 case VEX0F:
3263 m = 1;
3264 break;
3265 case VEX0F38:
3266 m = 2;
3267 break;
3268 case VEX0F3A:
3269 m = 3;
3270 break;
3271 default:
3272 abort ();
3273 break;
3274 }
3275
3276 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3277 bits from REX. */
3278 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3279
3280 /* The fifth bit of the second EVEX byte is 1's compliment of the
3281 REX_R bit in VREX. */
3282 if (!(i.vrex & REX_R))
3283 i.vex.bytes[1] |= 0x10;
3284 else
3285 vrex_used |= REX_R;
3286
3287 if ((i.reg_operands + i.imm_operands) == i.operands)
3288 {
3289 /* When all operands are registers, the REX_X bit in REX is not
3290 used. We reuse it to encode the upper 16 registers, which is
3291 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3292 as 1's compliment. */
3293 if ((i.vrex & REX_B))
3294 {
3295 vrex_used |= REX_B;
3296 i.vex.bytes[1] &= ~0x40;
3297 }
3298 }
3299
3300 /* EVEX instructions shouldn't need the REX prefix. */
3301 i.vrex &= ~vrex_used;
3302 gas_assert (i.vrex == 0);
3303
3304 /* Check the REX.W bit. */
3305 w = (i.rex & REX_W) ? 1 : 0;
3306 if (i.tm.opcode_modifier.vexw)
3307 {
3308 if (i.tm.opcode_modifier.vexw == VEXW1)
3309 w = 1;
3310 }
3311 /* If w is not set it means we are dealing with WIG instruction. */
3312 else if (!w)
3313 {
3314 if (evexwig == evexw1)
3315 w = 1;
3316 }
3317
3318 /* Encode the U bit. */
3319 implied_prefix |= 0x4;
3320
3321 /* The third byte of the EVEX prefix. */
3322 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3323
3324 /* The fourth byte of the EVEX prefix. */
3325 /* The zeroing-masking bit. */
3326 if (i.mask && i.mask->zeroing)
3327 i.vex.bytes[3] |= 0x80;
3328
3329 /* Don't always set the broadcast bit if there is no RC. */
3330 if (!i.rounding)
3331 {
3332 /* Encode the vector length. */
3333 unsigned int vec_length;
3334
3335 switch (i.tm.opcode_modifier.evex)
3336 {
3337 case EVEXLIG: /* LL' is ignored */
3338 vec_length = evexlig << 5;
3339 break;
3340 case EVEX128:
3341 vec_length = 0 << 5;
3342 break;
3343 case EVEX256:
3344 vec_length = 1 << 5;
3345 break;
3346 case EVEX512:
3347 vec_length = 2 << 5;
3348 break;
3349 default:
3350 abort ();
3351 break;
3352 }
3353 i.vex.bytes[3] |= vec_length;
3354 /* Encode the broadcast bit. */
3355 if (i.broadcast)
3356 i.vex.bytes[3] |= 0x10;
3357 }
3358 else
3359 {
3360 if (i.rounding->type != saeonly)
3361 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3362 else
d3d3c6db 3363 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3364 }
3365
3366 if (i.mask && i.mask->mask)
3367 i.vex.bytes[3] |= i.mask->mask->reg_num;
3368}
3369
65da13b5
L		 3370static void
3371process_immext (void)
3372{
3373 expressionS *exp;
3374
4c692bc7
JB		 3375 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3376 && i.operands > 0)
65da13b5 3377 {
4c692bc7
JB		 3378 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3379 with an opcode suffix which is coded in the same place as an
3380 8-bit immediate field would be.
3381 Here we check those operands and remove them afterwards. */
65da13b5
L		 3382 unsigned int x;
3383
3384 for (x = 0; x < i.operands; x++)
4c692bc7 3385 if (register_number (i.op[x].regs) != x)
65da13b5 3386 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3387 register_prefix, i.op[x].regs->reg_name, x + 1,
3388 i.tm.name);
3389
3390 i.operands = 0;
65da13b5
L		 3391 }
3392
c0f3af97 3393 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3394 which is coded in the same place as an 8-bit immediate field
3395 would be. Here we fake an 8-bit immediate operand from the
3396 opcode suffix stored in tm.extension_opcode.
3397
c1e679ec 3398 AVX instructions also use this encoding, for some of
c0f3af97 3399 3 argument instructions. */
65da13b5 3400
43234a1e 3401 gas_assert (i.imm_operands <= 1
7ab9ffdd 3402 && (i.operands <= 2
43234a1e
L		 3403 || ((i.tm.opcode_modifier.vex
3404 || i.tm.opcode_modifier.evex)
7ab9ffdd 3405 && i.operands <= 4)));
65da13b5
L		 3406
3407 exp = &im_expressions[i.imm_operands++];
3408 i.op[i.operands].imms = exp;
3409 i.types[i.operands] = imm8;
3410 i.operands++;
3411 exp->X_op = O_constant;
3412 exp->X_add_number = i.tm.extension_opcode;
3413 i.tm.extension_opcode = None;
3414}
3415
42164a71
L		 3416
3417static int
3418check_hle (void)
3419{
3420 switch (i.tm.opcode_modifier.hleprefixok)
3421 {
3422 default:
3423 abort ();
82c2def5 3424 case HLEPrefixNone:
165de32a
L		 3425 as_bad (_("invalid instruction `%s' after `%s'"),
3426 i.tm.name, i.hle_prefix);
42164a71 3427 return 0;
82c2def5 3428 case HLEPrefixLock:
42164a71
L		 3429 if (i.prefix[LOCK_PREFIX])
3430 return 1;
165de32a 3431 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3432 return 0;
82c2def5 3433 case HLEPrefixAny:
42164a71 3434 return 1;
82c2def5 3435 case HLEPrefixRelease:
42164a71
L		 3436 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3437 {
3438 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3439 i.tm.name);
3440 return 0;
3441 }
3442 if (i.mem_operands == 0
3443 || !operand_type_check (i.types[i.operands - 1], anymem))
3444 {
3445 as_bad (_("memory destination needed for instruction `%s'"
3446 " after `xrelease'"), i.tm.name);
3447 return 0;
3448 }
3449 return 1;
3450 }
3451}
3452
252b5132
RH		 3453/* This is the guts of the machine-dependent assembler. LINE points to a
3454 machine dependent instruction. This function is supposed to emit
3455 the frags/bytes it assembles to. */
3456
3457void
65da13b5 3458md_assemble (char *line)
252b5132 3459{
40fb9820 3460 unsigned int j;
252b5132 3461 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3462 const insn_template *t;
252b5132 3463
47926f60 3464 /* Initialize globals. */
252b5132
RH		 3465 memset (&i, '\0', sizeof (i));
3466 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3467 i.reloc[j] = NO_RELOC;
252b5132
RH		 3468 memset (disp_expressions, '\0', sizeof (disp_expressions));
3469 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3470 save_stack_p = save_stack;
252b5132
RH		 3471
3472 /* First parse an instruction mnemonic & call i386_operand for the operands.
3473 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3474 start of a (possibly prefixed) mnemonic. */
252b5132 3475
29b0f896
AM		 3476 line = parse_insn (line, mnemonic);
3477 if (line == NULL)
3478 return;
252b5132 3479
29b0f896 3480 line = parse_operands (line, mnemonic);
ee86248c 3481 this_operand = -1;
29b0f896
AM		 3482 if (line == NULL)
3483 return;
252b5132 3484
29b0f896
AM		 3485 /* Now we've parsed the mnemonic into a set of templates, and have the
3486 operands at hand. */
3487
3488 /* All intel opcodes have reversed operands except for "bound" and
3489 "enter". We also don't reverse intersegment "jmp" and "call"
3490 instructions with 2 immediate operands so that the immediate segment
050dfa73 3491 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3492 if (intel_syntax
3493 && i.operands > 1
29b0f896 3494 && (strcmp (mnemonic, "bound") != 0)
30123838 3495 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3496 && !(operand_type_check (i.types[0], imm)
3497 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3498 swap_operands ();
3499
ec56d5c0
JB		 3500 /* The order of the immediates should be reversed
3501 for 2 immediates extrq and insertq instructions */
3502 if (i.imm_operands == 2
3503 && (strcmp (mnemonic, "extrq") == 0
3504 || strcmp (mnemonic, "insertq") == 0))
3505 swap_2_operands (0, 1);
3506
29b0f896
AM		 3507 if (i.imm_operands)
3508 optimize_imm ();
3509
b300c311
L		 3510 /* Don't optimize displacement for movabs since it only takes 64bit
3511 displacement. */
3512 if (i.disp_operands
a501d77e 3513 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3514 && (flag_code != CODE_64BIT
3515 || strcmp (mnemonic, "movabs") != 0))
3516 optimize_disp ();
29b0f896
AM		 3517
3518 /* Next, we find a template that matches the given insn,
3519 making sure the overlap of the given operands types is consistent
3520 with the template operand types. */
252b5132 3521
fa99fab2 3522 if (!(t = match_template ()))
29b0f896 3523 return;
252b5132 3524
7bab8ab5 3525 if (sse_check != check_none
81f8a913 3526 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3527 && (i.tm.cpu_flags.bitfield.cpusse
3528 || i.tm.cpu_flags.bitfield.cpusse2
3529 || i.tm.cpu_flags.bitfield.cpusse3
3530 || i.tm.cpu_flags.bitfield.cpussse3
3531 || i.tm.cpu_flags.bitfield.cpusse4_1
3532 || i.tm.cpu_flags.bitfield.cpusse4_2))
3533 {
7bab8ab5 3534 (sse_check == check_warning
daf50ae7
L		 3535 ? as_warn
3536 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3537 }
3538
321fd21e
L		 3539 /* Zap movzx and movsx suffix. The suffix has been set from
3540 "word ptr" or "byte ptr" on the source operand in Intel syntax
3541 or extracted from mnemonic in AT&T syntax. But we'll use
3542 the destination register to choose the suffix for encoding. */
3543 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3544 {
321fd21e
L		 3545 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3546 there is no suffix, the default will be byte extension. */
3547 if (i.reg_operands != 2
3548 && !i.suffix
7ab9ffdd 3549 && intel_syntax)
321fd21e
L		 3550 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3551
3552 i.suffix = 0;
cd61ebfe 3553 }
24eab124 3554
40fb9820 3555 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3556 if (!add_prefix (FWAIT_OPCODE))
3557 return;
252b5132 3558
d5de92cf
L		 3559 /* Check if REP prefix is OK. */
3560 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3561 {
3562 as_bad (_("invalid instruction `%s' after `%s'"),
3563 i.tm.name, i.rep_prefix);
3564 return;
3565 }
3566
c1ba0266
L		 3567 /* Check for lock without a lockable instruction. Destination operand
3568 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3569 if (i.prefix[LOCK_PREFIX]
3570 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3571 || i.mem_operands == 0
3572 || (i.tm.base_opcode != 0x86
3573 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3574 {
3575 as_bad (_("expecting lockable instruction after `lock'"));
3576 return;
3577 }
3578
42164a71 3579 /* Check if HLE prefix is OK. */
165de32a 3580 if (i.hle_prefix && !check_hle ())
42164a71
L		 3581 return;
3582
7e8b059b
L		 3583 /* Check BND prefix. */
3584 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3585 as_bad (_("expecting valid branch instruction after `bnd'"));
3586
3587 if (i.tm.cpu_flags.bitfield.cpumpx
3588 && flag_code == CODE_64BIT
3589 && i.prefix[ADDR_PREFIX])
3590 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3591
3592 /* Insert BND prefix. */
3593 if (add_bnd_prefix
3594 && i.tm.opcode_modifier.bndprefixok
3595 && !i.prefix[BND_PREFIX])
3596 add_prefix (BND_PREFIX_OPCODE);
3597
29b0f896 3598 /* Check string instruction segment overrides. */
40fb9820 3599 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3600 {
3601 if (!check_string ())
5dd0794d 3602 return;
fc0763e6 3603 i.disp_operands = 0;
29b0f896 3604 }
5dd0794d 3605
29b0f896
AM		 3606 if (!process_suffix ())
3607 return;
e413e4e9 3608
bc0844ae
L		 3609 /* Update operand types. */
3610 for (j = 0; j < i.operands; j++)
3611 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3612
29b0f896
AM		 3613 /* Make still unresolved immediate matches conform to size of immediate
3614 given in i.suffix. */
3615 if (!finalize_imm ())
3616 return;
252b5132 3617
40fb9820 3618 if (i.types[0].bitfield.imm1)
29b0f896 3619 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3620
9afe6eb8
L		 3621 /* We only need to check those implicit registers for instructions
3622 with 3 operands or less. */
3623 if (i.operands <= 3)
3624 for (j = 0; j < i.operands; j++)
3625 if (i.types[j].bitfield.inoutportreg
3626 || i.types[j].bitfield.shiftcount
3627 || i.types[j].bitfield.acc
3628 || i.types[j].bitfield.floatacc)
3629 i.reg_operands--;
40fb9820 3630
c0f3af97
L		 3631 /* ImmExt should be processed after SSE2AVX. */
3632 if (!i.tm.opcode_modifier.sse2avx
3633 && i.tm.opcode_modifier.immext)
65da13b5 3634 process_immext ();
252b5132 3635
29b0f896
AM		 3636 /* For insns with operands there are more diddles to do to the opcode. */
3637 if (i.operands)
3638 {
3639 if (!process_operands ())
3640 return;
3641 }
40fb9820 3642 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3643 {
3644 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3645 as_warn (_("translating to `%sp'"), i.tm.name);
3646 }
252b5132 3647
9e5e5283
L		 3648 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3649 {
3650 if (flag_code == CODE_16BIT)
3651 {
3652 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3653 i.tm.name);
3654 return;
3655 }
c0f3af97 3656
9e5e5283
L		 3657 if (i.tm.opcode_modifier.vex)
3658 build_vex_prefix (t);
3659 else
3660 build_evex_prefix ();
3661 }
43234a1e 3662
5dd85c99
SP		 3663 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3664 instructions may define INT_OPCODE as well, so avoid this corner
3665 case for those instructions that use MODRM. */
3666 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3667 && !i.tm.opcode_modifier.modrm
3668 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3669 {
3670 i.tm.base_opcode = INT3_OPCODE;
3671 i.imm_operands = 0;
3672 }
252b5132 3673
40fb9820
L		 3674 if ((i.tm.opcode_modifier.jump
3675 || i.tm.opcode_modifier.jumpbyte
3676 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3677 && i.op[0].disps->X_op == O_constant)
3678 {
3679 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3680 the absolute address given by the constant. Since ix86 jumps and
3681 calls are pc relative, we need to generate a reloc. */
3682 i.op[0].disps->X_add_symbol = &abs_symbol;
3683 i.op[0].disps->X_op = O_symbol;
3684 }
252b5132 3685
40fb9820 3686 if (i.tm.opcode_modifier.rex64)
161a04f6 3687 i.rex |= REX_W;
252b5132 3688
29b0f896
AM		 3689 /* For 8 bit registers we need an empty rex prefix. Also if the
3690 instruction already has a prefix, we need to convert old
3691 registers to new ones. */
773f551c 3692
40fb9820 3693 if ((i.types[0].bitfield.reg8
29b0f896 3694 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3695 || (i.types[1].bitfield.reg8
29b0f896 3696 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3697 || ((i.types[0].bitfield.reg8
3698 || i.types[1].bitfield.reg8)
29b0f896
AM		 3699 && i.rex != 0))
3700 {
3701 int x;
726c5dcd 3702
29b0f896
AM		 3703 i.rex |= REX_OPCODE;
3704 for (x = 0; x < 2; x++)
3705 {
3706 /* Look for 8 bit operand that uses old registers. */
40fb9820 3707 if (i.types[x].bitfield.reg8
29b0f896 3708 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3709 {
29b0f896
AM		 3710 /* In case it is "hi" register, give up. */
3711 if (i.op[x].regs->reg_num > 3)
a540244d 3712 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3713 "instruction requiring REX prefix."),
a540244d 3714 register_prefix, i.op[x].regs->reg_name);
773f551c 3715
29b0f896
AM		 3716 /* Otherwise it is equivalent to the extended register.
3717 Since the encoding doesn't change this is merely
3718 cosmetic cleanup for debug output. */
3719
3720 i.op[x].regs = i.op[x].regs + 8;
773f551c 3721 }
29b0f896
AM		 3722 }
3723 }
773f551c 3724
7ab9ffdd 3725 if (i.rex != 0)
29b0f896
AM		 3726 add_prefix (REX_OPCODE | i.rex);
3727
3728 /* We are ready to output the insn. */
3729 output_insn ();
3730}
3731
3732static char *
e3bb37b5 3733parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3734{
3735 char *l = line;
3736 char *token_start = l;
3737 char *mnem_p;
5c6af06e 3738 int supported;
d3ce72d0 3739 const insn_template *t;
b6169b20 3740 char *dot_p = NULL;
29b0f896 3741
29b0f896
AM		 3742 while (1)
3743 {
3744 mnem_p = mnemonic;
3745 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3746 {
b6169b20
L		 3747 if (*mnem_p == '.')
3748 dot_p = mnem_p;
29b0f896
AM		 3749 mnem_p++;
3750 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3751 {
29b0f896
AM		 3752 as_bad (_("no such instruction: `%s'"), token_start);
3753 return NULL;
3754 }
3755 l++;
3756 }
3757 if (!is_space_char (*l)
3758 && *l != END_OF_INSN
e44823cf
JB		 3759 && (intel_syntax
3760 || (*l != PREFIX_SEPARATOR
3761 && *l != ',')))
29b0f896
AM		 3762 {
3763 as_bad (_("invalid character %s in mnemonic"),
3764 output_invalid (*l));
3765 return NULL;
3766 }
3767 if (token_start == l)
3768 {
e44823cf 3769 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3770 as_bad (_("expecting prefix; got nothing"));
3771 else
3772 as_bad (_("expecting mnemonic; got nothing"));
3773 return NULL;
3774 }
45288df1 3775
29b0f896 3776 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3777 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3778
29b0f896
AM		 3779 if (*l != END_OF_INSN
3780 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3781 && current_templates
40fb9820 3782 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3783 {
c6fb90c8 3784 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3785 {
3786 as_bad ((flag_code != CODE_64BIT
3787 ? _("`%s' is only supported in 64-bit mode")
3788 : _("`%s' is not supported in 64-bit mode")),
3789 current_templates->start->name);
3790 return NULL;
3791 }
29b0f896
AM		 3792 /* If we are in 16-bit mode, do not allow addr16 or data16.
3793 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3794 if ((current_templates->start->opcode_modifier.size16
3795 || current_templates->start->opcode_modifier.size32)
29b0f896 3796 && flag_code != CODE_64BIT
40fb9820 3797 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3798 ^ (flag_code == CODE_16BIT)))
3799 {
3800 as_bad (_("redundant %s prefix"),
3801 current_templates->start->name);
3802 return NULL;
45288df1 3803 }
29b0f896
AM		 3804 /* Add prefix, checking for repeated prefixes. */
3805 switch (add_prefix (current_templates->start->base_opcode))
3806 {
c32fa91d 3807 case PREFIX_EXIST:
29b0f896 3808 return NULL;
c32fa91d 3809 case PREFIX_REP:
42164a71 3810 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3811 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3812 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3813 i.bnd_prefix = current_templates->start->name;
42164a71 3814 else
d5de92cf 3815 i.rep_prefix = current_templates->start->name;
29b0f896 3816 break;
c32fa91d
L		 3817 default:
3818 break;
29b0f896
AM		 3819 }
3820 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3821 token_start = ++l;
3822 }
3823 else
3824 break;
3825 }
45288df1 3826
30a55f88 3827 if (!current_templates)
b6169b20 3828 {
f8a5c266
L		 3829 /* Check if we should swap operand or force 32bit displacement in
3830 encoding. */
30a55f88
L		 3831 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3832 i.swap_operand = 1;
8d63c93e 3833 else if (mnem_p - 3 == dot_p
a501d77e
L		 3834 && dot_p[1] == 'd'
3835 && dot_p[2] == '8')
3836 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3837 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3838 && dot_p[1] == 'd'
3839 && dot_p[2] == '3'
3840 && dot_p[3] == '2')
a501d77e 3841 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3842 else
3843 goto check_suffix;
3844 mnem_p = dot_p;
3845 *dot_p = '\0';
d3ce72d0 3846 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3847 }
3848
29b0f896
AM		 3849 if (!current_templates)
3850 {
b6169b20 3851check_suffix:
29b0f896
AM		 3852 /* See if we can get a match by trimming off a suffix. */
3853 switch (mnem_p[-1])
3854 {
3855 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3856 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3857 i.suffix = SHORT_MNEM_SUFFIX;
3858 else
29b0f896
AM		 3859 case BYTE_MNEM_SUFFIX:
3860 case QWORD_MNEM_SUFFIX:
3861 i.suffix = mnem_p[-1];
3862 mnem_p[-1] = '\0';
d3ce72d0
NC		 3863 current_templates = (const templates *) hash_find (op_hash,
3864 mnemonic);
29b0f896
AM		 3865 break;
3866 case SHORT_MNEM_SUFFIX:
3867 case LONG_MNEM_SUFFIX:
3868 if (!intel_syntax)
3869 {
3870 i.suffix = mnem_p[-1];
3871 mnem_p[-1] = '\0';
d3ce72d0
NC		 3872 current_templates = (const templates *) hash_find (op_hash,
3873 mnemonic);
29b0f896
AM		 3874 }
3875 break;
252b5132 3876
29b0f896
AM		 3877 /* Intel Syntax. */
3878 case 'd':
3879 if (intel_syntax)
3880 {
9306ca4a 3881 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3882 i.suffix = SHORT_MNEM_SUFFIX;
3883 else
3884 i.suffix = LONG_MNEM_SUFFIX;
3885 mnem_p[-1] = '\0';
d3ce72d0
NC		 3886 current_templates = (const templates *) hash_find (op_hash,
3887 mnemonic);
29b0f896
AM		 3888 }
3889 break;
3890 }
3891 if (!current_templates)
3892 {
3893 as_bad (_("no such instruction: `%s'"), token_start);
3894 return NULL;
3895 }
3896 }
252b5132 3897
40fb9820
L		 3898 if (current_templates->start->opcode_modifier.jump
3899 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3900 {
3901 /* Check for a branch hint. We allow ",pt" and ",pn" for
3902 predict taken and predict not taken respectively.
3903 I'm not sure that branch hints actually do anything on loop
3904 and jcxz insns (JumpByte) for current Pentium4 chips. They
3905 may work in the future and it doesn't hurt to accept them
3906 now. */
3907 if (l[0] == ',' && l[1] == 'p')
3908 {
3909 if (l[2] == 't')
3910 {
3911 if (!add_prefix (DS_PREFIX_OPCODE))
3912 return NULL;
3913 l += 3;
3914 }
3915 else if (l[2] == 'n')
3916 {
3917 if (!add_prefix (CS_PREFIX_OPCODE))
3918 return NULL;
3919 l += 3;
3920 }
3921 }
3922 }
3923 /* Any other comma loses. */
3924 if (*l == ',')
3925 {
3926 as_bad (_("invalid character %s in mnemonic"),
3927 output_invalid (*l));
3928 return NULL;
3929 }
252b5132 3930
29b0f896 3931 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3932 supported = 0;
3933 for (t = current_templates->start; t < current_templates->end; ++t)
3934 {
c0f3af97
L		 3935 supported |= cpu_flags_match (t);
3936 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3937 goto skip;
5c6af06e 3938 }
3629bb00 3939
c0f3af97 3940 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3941 {
3942 as_bad (flag_code == CODE_64BIT
3943 ? _("`%s' is not supported in 64-bit mode")
3944 : _("`%s' is only supported in 64-bit mode"),
3945 current_templates->start->name);
3946 return NULL;
3947 }
c0f3af97 3948 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3949 {
3629bb00 3950 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3951 current_templates->start->name,
41aacd83 3952 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3953 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3954 return NULL;
29b0f896 3955 }
3629bb00
L		 3956
3957skip:
3958 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3959 && (flag_code != CODE_16BIT))
29b0f896
AM		 3960 {
3961 as_warn (_("use .code16 to ensure correct addressing mode"));
3962 }
252b5132 3963
29b0f896
AM		 3964 return l;
3965}
252b5132 3966
29b0f896 3967static char *
e3bb37b5 3968parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3969{
3970 char *token_start;
3138f287 3971
29b0f896
AM		 3972 /* 1 if operand is pending after ','. */
3973 unsigned int expecting_operand = 0;
252b5132 3974
29b0f896
AM		 3975 /* Non-zero if operand parens not balanced. */
3976 unsigned int paren_not_balanced;
3977
3978 while (*l != END_OF_INSN)
3979 {
3980 /* Skip optional white space before operand. */
3981 if (is_space_char (*l))
3982 ++l;
3983 if (!is_operand_char (*l) && *l != END_OF_INSN)
3984 {
3985 as_bad (_("invalid character %s before operand %d"),
3986 output_invalid (*l),
3987 i.operands + 1);
3988 return NULL;
3989 }
3990 token_start = l; /* after white space */
3991 paren_not_balanced = 0;
3992 while (paren_not_balanced || *l != ',')
3993 {
3994 if (*l == END_OF_INSN)
3995 {
3996 if (paren_not_balanced)
3997 {
3998 if (!intel_syntax)
3999 as_bad (_("unbalanced parenthesis in operand %d."),
4000 i.operands + 1);
4001 else
4002 as_bad (_("unbalanced brackets in operand %d."),
4003 i.operands + 1);
4004 return NULL;
4005 }
4006 else
4007 break; /* we are done */
4008 }
4009 else if (!is_operand_char (*l) && !is_space_char (*l))
4010 {
4011 as_bad (_("invalid character %s in operand %d"),
4012 output_invalid (*l),
4013 i.operands + 1);
4014 return NULL;
4015 }
4016 if (!intel_syntax)
4017 {
4018 if (*l == '(')
4019 ++paren_not_balanced;
4020 if (*l == ')')
4021 --paren_not_balanced;
4022 }
4023 else
4024 {
4025 if (*l == '[')
4026 ++paren_not_balanced;
4027 if (*l == ']')
4028 --paren_not_balanced;
4029 }
4030 l++;
4031 }
4032 if (l != token_start)
4033 { /* Yes, we've read in another operand. */
4034 unsigned int operand_ok;
4035 this_operand = i.operands++;
7d5e4556 4036 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4037 if (i.operands > MAX_OPERANDS)
4038 {
4039 as_bad (_("spurious operands; (%d operands/instruction max)"),
4040 MAX_OPERANDS);
4041 return NULL;
4042 }
4043 /* Now parse operand adding info to 'i' as we go along. */
4044 END_STRING_AND_SAVE (l);
4045
4046 if (intel_syntax)
4047 operand_ok =
4048 i386_intel_operand (token_start,
4049 intel_float_operand (mnemonic));
4050 else
a7619375 4051 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4052
4053 RESTORE_END_STRING (l);
4054 if (!operand_ok)
4055 return NULL;
4056 }
4057 else
4058 {
4059 if (expecting_operand)
4060 {
4061 expecting_operand_after_comma:
4062 as_bad (_("expecting operand after ','; got nothing"));
4063 return NULL;
4064 }
4065 if (*l == ',')
4066 {
4067 as_bad (_("expecting operand before ','; got nothing"));
4068 return NULL;
4069 }
4070 }
7f3f1ea2 4071
29b0f896
AM		 4072 /* Now *l must be either ',' or END_OF_INSN. */
4073 if (*l == ',')
4074 {
4075 if (*++l == END_OF_INSN)
4076 {
4077 /* Just skip it, if it's \n complain. */
4078 goto expecting_operand_after_comma;
4079 }
4080 expecting_operand = 1;
4081 }
4082 }
4083 return l;
4084}
7f3f1ea2 4085
050dfa73 4086static void
4d456e3d 4087swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4088{
4089 union i386_op temp_op;
40fb9820 4090 i386_operand_type temp_type;
050dfa73 4091 enum bfd_reloc_code_real temp_reloc;
4eed87de 4092
050dfa73
MM		 4093 temp_type = i.types[xchg2];
4094 i.types[xchg2] = i.types[xchg1];
4095 i.types[xchg1] = temp_type;
4096 temp_op = i.op[xchg2];
4097 i.op[xchg2] = i.op[xchg1];
4098 i.op[xchg1] = temp_op;
4099 temp_reloc = i.reloc[xchg2];
4100 i.reloc[xchg2] = i.reloc[xchg1];
4101 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4102
4103 if (i.mask)
4104 {
4105 if (i.mask->operand == xchg1)
4106 i.mask->operand = xchg2;
4107 else if (i.mask->operand == xchg2)
4108 i.mask->operand = xchg1;
4109 }
4110 if (i.broadcast)
4111 {
4112 if (i.broadcast->operand == xchg1)
4113 i.broadcast->operand = xchg2;
4114 else if (i.broadcast->operand == xchg2)
4115 i.broadcast->operand = xchg1;
4116 }
4117 if (i.rounding)
4118 {
4119 if (i.rounding->operand == xchg1)
4120 i.rounding->operand = xchg2;
4121 else if (i.rounding->operand == xchg2)
4122 i.rounding->operand = xchg1;
4123 }
050dfa73
MM		 4124}
4125
29b0f896 4126static void
e3bb37b5 4127swap_operands (void)
29b0f896 4128{
b7c61d9a 4129 switch (i.operands)
050dfa73 4130 {
c0f3af97 4131 case 5:
b7c61d9a 4132 case 4:
4d456e3d 4133 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4134 case 3:
4135 case 2:
4d456e3d 4136 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4137 break;
4138 default:
4139 abort ();
29b0f896 4140 }
29b0f896
AM		 4141
4142 if (i.mem_operands == 2)
4143 {
4144 const seg_entry *temp_seg;
4145 temp_seg = i.seg[0];
4146 i.seg[0] = i.seg[1];
4147 i.seg[1] = temp_seg;
4148 }
4149}
252b5132 4150
29b0f896
AM		 4151/* Try to ensure constant immediates are represented in the smallest
4152 opcode possible. */
4153static void
e3bb37b5 4154optimize_imm (void)
29b0f896
AM		 4155{
4156 char guess_suffix = 0;
4157 int op;
252b5132 4158
29b0f896
AM		 4159 if (i.suffix)
4160 guess_suffix = i.suffix;
4161 else if (i.reg_operands)
4162 {
4163 /* Figure out a suffix from the last register operand specified.
4164 We can't do this properly yet, ie. excluding InOutPortReg,
4165 but the following works for instructions with immediates.
4166 In any case, we can't set i.suffix yet. */
4167 for (op = i.operands; --op >= 0;)
40fb9820 4168 if (i.types[op].bitfield.reg8)
7ab9ffdd 4169 {
40fb9820
L		 4170 guess_suffix = BYTE_MNEM_SUFFIX;
4171 break;
4172 }
4173 else if (i.types[op].bitfield.reg16)
252b5132 4174 {
40fb9820
L		 4175 guess_suffix = WORD_MNEM_SUFFIX;
4176 break;
4177 }
4178 else if (i.types[op].bitfield.reg32)
4179 {
4180 guess_suffix = LONG_MNEM_SUFFIX;
4181 break;
4182 }
4183 else if (i.types[op].bitfield.reg64)
4184 {
4185 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4186 break;
252b5132 4187 }
29b0f896
AM		 4188 }
4189 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4190 guess_suffix = WORD_MNEM_SUFFIX;
4191
4192 for (op = i.operands; --op >= 0;)
40fb9820 4193 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4194 {
4195 switch (i.op[op].imms->X_op)
252b5132 4196 {
29b0f896
AM		 4197 case O_constant:
4198 /* If a suffix is given, this operand may be shortened. */
4199 switch (guess_suffix)
252b5132 4200 {
29b0f896 4201 case LONG_MNEM_SUFFIX:
40fb9820
L		 4202 i.types[op].bitfield.imm32 = 1;
4203 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4204 break;
4205 case WORD_MNEM_SUFFIX:
40fb9820
L		 4206 i.types[op].bitfield.imm16 = 1;
4207 i.types[op].bitfield.imm32 = 1;
4208 i.types[op].bitfield.imm32s = 1;
4209 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4210 break;
4211 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4212 i.types[op].bitfield.imm8 = 1;
4213 i.types[op].bitfield.imm8s = 1;
4214 i.types[op].bitfield.imm16 = 1;
4215 i.types[op].bitfield.imm32 = 1;
4216 i.types[op].bitfield.imm32s = 1;
4217 i.types[op].bitfield.imm64 = 1;
29b0f896 4218 break;
252b5132 4219 }
252b5132 4220
29b0f896
AM		 4221 /* If this operand is at most 16 bits, convert it
4222 to a signed 16 bit number before trying to see
4223 whether it will fit in an even smaller size.
4224 This allows a 16-bit operand such as $0xffe0 to
4225 be recognised as within Imm8S range. */
40fb9820 4226 if ((i.types[op].bitfield.imm16)
29b0f896 4227 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4228 {
29b0f896
AM		 4229 i.op[op].imms->X_add_number =
4230 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4231 }
40fb9820 4232 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4233 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4234 == 0))
4235 {
4236 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4237 ^ ((offsetT) 1 << 31))
4238 - ((offsetT) 1 << 31));
4239 }
40fb9820 4240 i.types[op]
c6fb90c8
L		 4241 = operand_type_or (i.types[op],
4242 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4243
29b0f896
AM		 4244 /* We must avoid matching of Imm32 templates when 64bit
4245 only immediate is available. */
4246 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4247 i.types[op].bitfield.imm32 = 0;
29b0f896 4248 break;
252b5132 4249
29b0f896
AM		 4250 case O_absent:
4251 case O_register:
4252 abort ();
4253
4254 /* Symbols and expressions. */
4255 default:
9cd96992
JB		 4256 /* Convert symbolic operand to proper sizes for matching, but don't
4257 prevent matching a set of insns that only supports sizes other
4258 than those matching the insn suffix. */
4259 {
40fb9820 4260 i386_operand_type mask, allowed;
d3ce72d0 4261 const insn_template *t;
9cd96992 4262
0dfbf9d7
L		 4263 operand_type_set (&mask, 0);
4264 operand_type_set (&allowed, 0);
40fb9820 4265
4eed87de
AM		 4266 for (t = current_templates->start;
4267 t < current_templates->end;
4268 ++t)
c6fb90c8
L		 4269 allowed = operand_type_or (allowed,
4270 t->operand_types[op]);
9cd96992
JB		 4271 switch (guess_suffix)
4272 {
4273 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4274 mask.bitfield.imm64 = 1;
4275 mask.bitfield.imm32s = 1;
9cd96992
JB		 4276 break;
4277 case LONG_MNEM_SUFFIX:
40fb9820 4278 mask.bitfield.imm32 = 1;
9cd96992
JB		 4279 break;
4280 case WORD_MNEM_SUFFIX:
40fb9820 4281 mask.bitfield.imm16 = 1;
9cd96992
JB		 4282 break;
4283 case BYTE_MNEM_SUFFIX:
40fb9820 4284 mask.bitfield.imm8 = 1;
9cd96992
JB		 4285 break;
4286 default:
9cd96992
JB		 4287 break;
4288 }
c6fb90c8 4289 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4290 if (!operand_type_all_zero (&allowed))
c6fb90c8 4291 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4292 }
29b0f896 4293 break;
252b5132 4294 }
29b0f896
AM		 4295 }
4296}
47926f60 4297
29b0f896
AM		 4298/* Try to use the smallest displacement type too. */
4299static void
e3bb37b5 4300optimize_disp (void)
29b0f896
AM		 4301{
4302 int op;
3e73aa7c 4303
29b0f896 4304 for (op = i.operands; --op >= 0;)
40fb9820 4305 if (operand_type_check (i.types[op], disp))
252b5132 4306 {
b300c311 4307 if (i.op[op].disps->X_op == O_constant)
252b5132 4308 {
91d6fa6a 4309 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4310
40fb9820 4311 if (i.types[op].bitfield.disp16
91d6fa6a 4312 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4313 {
4314 /* If this operand is at most 16 bits, convert
4315 to a signed 16 bit number and don't use 64bit
4316 displacement. */
91d6fa6a 4317 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4318 i.types[op].bitfield.disp64 = 0;
b300c311 4319 }
40fb9820 4320 if (i.types[op].bitfield.disp32
91d6fa6a 4321 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4322 {
4323 /* If this operand is at most 32 bits, convert
4324 to a signed 32 bit number and don't use 64bit
4325 displacement. */
91d6fa6a
NC		 4326 op_disp &= (((offsetT) 2 << 31) - 1);
4327 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4328 i.types[op].bitfield.disp64 = 0;
b300c311 4329 }
91d6fa6a 4330 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4331 {
40fb9820
L		 4332 i.types[op].bitfield.disp8 = 0;
4333 i.types[op].bitfield.disp16 = 0;
4334 i.types[op].bitfield.disp32 = 0;
4335 i.types[op].bitfield.disp32s = 0;
4336 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4337 i.op[op].disps = 0;
4338 i.disp_operands--;
4339 }
4340 else if (flag_code == CODE_64BIT)
4341 {
91d6fa6a 4342 if (fits_in_signed_long (op_disp))
28a9d8f5 4343 {
40fb9820
L		 4344 i.types[op].bitfield.disp64 = 0;
4345 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4346 }
0e1147d9 4347 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4348 && fits_in_unsigned_long (op_disp))
40fb9820 4349 i.types[op].bitfield.disp32 = 1;
b300c311 4350 }
40fb9820
L		 4351 if ((i.types[op].bitfield.disp32
4352 || i.types[op].bitfield.disp32s
4353 || i.types[op].bitfield.disp16)
91d6fa6a 4354 && fits_in_signed_byte (op_disp))
40fb9820 4355 i.types[op].bitfield.disp8 = 1;
252b5132 4356 }
67a4f2b7
AO		 4357 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4358 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4359 {
4360 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4361 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4362 i.types[op].bitfield.disp8 = 0;
4363 i.types[op].bitfield.disp16 = 0;
4364 i.types[op].bitfield.disp32 = 0;
4365 i.types[op].bitfield.disp32s = 0;
4366 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4367 }
4368 else
b300c311 4369 /* We only support 64bit displacement on constants. */
40fb9820 4370 i.types[op].bitfield.disp64 = 0;
252b5132 4371 }
29b0f896
AM		 4372}
4373
6c30d220
L		 4374/* Check if operands are valid for the instruction. */
4375
4376static int
4377check_VecOperands (const insn_template *t)
4378{
43234a1e
L		 4379 unsigned int op;
4380
6c30d220
L		 4381 /* Without VSIB byte, we can't have a vector register for index. */
4382 if (!t->opcode_modifier.vecsib
4383 && i.index_reg
4384 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4385 || i.index_reg->reg_type.bitfield.regymm
4386 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4387 {
4388 i.error = unsupported_vector_index_register;
4389 return 1;
4390 }
4391
ad8ecc81
MZ		 4392 /* Check if default mask is allowed. */
4393 if (t->opcode_modifier.nodefmask
4394 && (!i.mask || i.mask->mask->reg_num == 0))
4395 {
4396 i.error = no_default_mask;
4397 return 1;
4398 }
4399
7bab8ab5
JB		 4400 /* For VSIB byte, we need a vector register for index, and all vector
4401 registers must be distinct. */
4402 if (t->opcode_modifier.vecsib)
4403 {
4404 if (!i.index_reg
6c30d220
L		 4405 || !((t->opcode_modifier.vecsib == VecSIB128
4406 && i.index_reg->reg_type.bitfield.regxmm)
4407 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4408 && i.index_reg->reg_type.bitfield.regymm)
4409 || (t->opcode_modifier.vecsib == VecSIB512
4410 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4411 {
4412 i.error = invalid_vsib_address;
4413 return 1;
4414 }
4415
43234a1e
L		 4416 gas_assert (i.reg_operands == 2 || i.mask);
4417 if (i.reg_operands == 2 && !i.mask)
4418 {
4419 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4420 || i.types[0].bitfield.regymm);
43234a1e 4421 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4422 || i.types[2].bitfield.regymm);
43234a1e
L		 4423 if (operand_check == check_none)
4424 return 0;
4425 if (register_number (i.op[0].regs)
4426 != register_number (i.index_reg)
4427 && register_number (i.op[2].regs)
4428 != register_number (i.index_reg)
4429 && register_number (i.op[0].regs)
4430 != register_number (i.op[2].regs))
4431 return 0;
4432 if (operand_check == check_error)
4433 {
4434 i.error = invalid_vector_register_set;
4435 return 1;
4436 }
4437 as_warn (_("mask, index, and destination registers should be distinct"));
4438 }
8444f82a
MZ		 4439 else if (i.reg_operands == 1 && i.mask)
4440 {
4441 if ((i.types[1].bitfield.regymm
4442 || i.types[1].bitfield.regzmm)
4443 && (register_number (i.op[1].regs)
4444 == register_number (i.index_reg)))
4445 {
4446 if (operand_check == check_error)
4447 {
4448 i.error = invalid_vector_register_set;
4449 return 1;
4450 }
4451 if (operand_check != check_none)
4452 as_warn (_("index and destination registers should be distinct"));
4453 }
4454 }
43234a1e 4455 }
7bab8ab5 4456
43234a1e
L		 4457 /* Check if broadcast is supported by the instruction and is applied
4458 to the memory operand. */
4459 if (i.broadcast)
4460 {
4461 int broadcasted_opnd_size;
4462
4463 /* Check if specified broadcast is supported in this instruction,
4464 and it's applied to memory operand of DWORD or QWORD type,
4465 depending on VecESize. */
4466 if (i.broadcast->type != t->opcode_modifier.broadcast
4467 || !i.types[i.broadcast->operand].bitfield.mem
4468 || (t->opcode_modifier.vecesize == 0
4469 && !i.types[i.broadcast->operand].bitfield.dword
4470 && !i.types[i.broadcast->operand].bitfield.unspecified)
4471 || (t->opcode_modifier.vecesize == 1
4472 && !i.types[i.broadcast->operand].bitfield.qword
4473 && !i.types[i.broadcast->operand].bitfield.unspecified))
4474 goto bad_broadcast;
4475
4476 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4477 if (i.broadcast->type == BROADCAST_1TO16)
4478 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4479 else if (i.broadcast->type == BROADCAST_1TO8)
4480 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4481 else if (i.broadcast->type == BROADCAST_1TO4)
4482 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4483 else if (i.broadcast->type == BROADCAST_1TO2)
4484 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4485 else
4486 goto bad_broadcast;
4487
4488 if ((broadcasted_opnd_size == 256
4489 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4490 || (broadcasted_opnd_size == 512
4491 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4492 {
4493 bad_broadcast:
4494 i.error = unsupported_broadcast;
4495 return 1;
4496 }
4497 }
4498 /* If broadcast is supported in this instruction, we need to check if
4499 operand of one-element size isn't specified without broadcast. */
4500 else if (t->opcode_modifier.broadcast && i.mem_operands)
4501 {
4502 /* Find memory operand. */
4503 for (op = 0; op < i.operands; op++)
4504 if (operand_type_check (i.types[op], anymem))
4505 break;
4506 gas_assert (op < i.operands);
4507 /* Check size of the memory operand. */
4508 if ((t->opcode_modifier.vecesize == 0
4509 && i.types[op].bitfield.dword)
4510 || (t->opcode_modifier.vecesize == 1
4511 && i.types[op].bitfield.qword))
4512 {
4513 i.error = broadcast_needed;
4514 return 1;
4515 }
4516 }
4517
4518 /* Check if requested masking is supported. */
4519 if (i.mask
4520 && (!t->opcode_modifier.masking
4521 || (i.mask->zeroing
4522 && t->opcode_modifier.masking == MERGING_MASKING)))
4523 {
4524 i.error = unsupported_masking;
4525 return 1;
4526 }
4527
4528 /* Check if masking is applied to dest operand. */
4529 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4530 {
4531 i.error = mask_not_on_destination;
4532 return 1;
4533 }
4534
43234a1e
L		 4535 /* Check RC/SAE. */
4536 if (i.rounding)
4537 {
4538 if ((i.rounding->type != saeonly
4539 && !t->opcode_modifier.staticrounding)
4540 || (i.rounding->type == saeonly
4541 && (t->opcode_modifier.staticrounding
4542 || !t->opcode_modifier.sae)))
4543 {
4544 i.error = unsupported_rc_sae;
4545 return 1;
4546 }
4547 /* If the instruction has several immediate operands and one of
4548 them is rounding, the rounding operand should be the last
4549 immediate operand. */
4550 if (i.imm_operands > 1
4551 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4552 {
43234a1e 4553 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4554 return 1;
4555 }
6c30d220
L		 4556 }
4557
43234a1e
L		 4558 /* Check vector Disp8 operand. */
4559 if (t->opcode_modifier.disp8memshift)
4560 {
4561 if (i.broadcast)
4562 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4563 else
4564 i.memshift = t->opcode_modifier.disp8memshift;
4565
4566 for (op = 0; op < i.operands; op++)
4567 if (operand_type_check (i.types[op], disp)
4568 && i.op[op].disps->X_op == O_constant)
4569 {
4570 offsetT value = i.op[op].disps->X_add_number;
4571 int vec_disp8_ok = fits_in_vec_disp8 (value);
4572 if (t->operand_types [op].bitfield.vec_disp8)
4573 {
4574 if (vec_disp8_ok)
4575 i.types[op].bitfield.vec_disp8 = 1;
4576 else
4577 {
4578 /* Vector insn can only have Vec_Disp8/Disp32 in
4579 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4580 mode. */
4581 i.types[op].bitfield.disp8 = 0;
4582 if (flag_code != CODE_16BIT)
4583 i.types[op].bitfield.disp16 = 0;
4584 }
4585 }
4586 else if (flag_code != CODE_16BIT)
4587 {
4588 /* One form of this instruction supports vector Disp8.
4589 Try vector Disp8 if we need to use Disp32. */
4590 if (vec_disp8_ok && !fits_in_signed_byte (value))
4591 {
4592 i.error = try_vector_disp8;
4593 return 1;
4594 }
4595 }
4596 }
4597 }
4598 else
4599 i.memshift = -1;
4600
6c30d220
L		 4601 return 0;
4602}
4603
43f3e2ee 4604/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4605 operand types. */
4606
4607static int
4608VEX_check_operands (const insn_template *t)
4609{
43234a1e
L		 4610 /* VREX is only valid with EVEX prefix. */
4611 if (i.need_vrex && !t->opcode_modifier.evex)
4612 {
4613 i.error = invalid_register_operand;
4614 return 1;
4615 }
4616
a683cc34
SP		 4617 if (!t->opcode_modifier.vex)
4618 return 0;
4619
4620 /* Only check VEX_Imm4, which must be the first operand. */
4621 if (t->operand_types[0].bitfield.vec_imm4)
4622 {
4623 if (i.op[0].imms->X_op != O_constant
4624 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4625 {
a65babc9 4626 i.error = bad_imm4;
891edac4
L		 4627 return 1;
4628 }
a683cc34
SP		 4629
4630 /* Turn off Imm8 so that update_imm won't complain. */
4631 i.types[0] = vec_imm4;
4632 }
4633
4634 return 0;
4635}
4636
d3ce72d0 4637static const insn_template *
e3bb37b5 4638match_template (void)
29b0f896
AM		 4639{
4640 /* Points to template once we've found it. */
d3ce72d0 4641 const insn_template *t;
40fb9820 4642 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4643 i386_operand_type overlap4;
29b0f896 4644 unsigned int found_reverse_match;
40fb9820
L		 4645 i386_opcode_modifier suffix_check;
4646 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4647 int addr_prefix_disp;
a5c311ca 4648 unsigned int j;
3629bb00 4649 unsigned int found_cpu_match;
45664ddb 4650 unsigned int check_register;
5614d22c 4651 enum i386_error specific_error = 0;
29b0f896 4652
c0f3af97
L		 4653#if MAX_OPERANDS != 5
4654# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4655#endif
4656
29b0f896 4657 found_reverse_match = 0;
539e75ad 4658 addr_prefix_disp = -1;
40fb9820
L		 4659
4660 memset (&suffix_check, 0, sizeof (suffix_check));
4661 if (i.suffix == BYTE_MNEM_SUFFIX)
4662 suffix_check.no_bsuf = 1;
4663 else if (i.suffix == WORD_MNEM_SUFFIX)
4664 suffix_check.no_wsuf = 1;
4665 else if (i.suffix == SHORT_MNEM_SUFFIX)
4666 suffix_check.no_ssuf = 1;
4667 else if (i.suffix == LONG_MNEM_SUFFIX)
4668 suffix_check.no_lsuf = 1;
4669 else if (i.suffix == QWORD_MNEM_SUFFIX)
4670 suffix_check.no_qsuf = 1;
4671 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4672 suffix_check.no_ldsuf = 1;
29b0f896 4673
01559ecc
L		 4674 /* Must have right number of operands. */
4675 i.error = number_of_operands_mismatch;
4676
45aa61fe 4677 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4678 {
539e75ad
L		 4679 addr_prefix_disp = -1;
4680
29b0f896
AM		 4681 if (i.operands != t->operands)
4682 continue;
4683
50aecf8c 4684 /* Check processor support. */
a65babc9 4685 i.error = unsupported;
c0f3af97
L		 4686 found_cpu_match = (cpu_flags_match (t)
4687 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4688 if (!found_cpu_match)
4689 continue;
4690
e1d4d893 4691 /* Check old gcc support. */
a65babc9 4692 i.error = old_gcc_only;
e1d4d893
L		 4693 if (!old_gcc && t->opcode_modifier.oldgcc)
4694 continue;
4695
4696 /* Check AT&T mnemonic. */
a65babc9 4697 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4698 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4699 continue;
4700
891edac4 4701 /* Check AT&T/Intel syntax. */
a65babc9 4702 i.error = unsupported_syntax;
5c07affc
L		 4703 if ((intel_syntax && t->opcode_modifier.attsyntax)
4704 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4705 continue;
4706
20592a94 4707 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4708 i.error = invalid_instruction_suffix;
567e4e96
L		 4709 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4710 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4711 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4712 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4713 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4714 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4715 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4716 continue;
4717
5c07affc 4718 if (!operand_size_match (t))
7d5e4556 4719 continue;
539e75ad 4720
5c07affc
L		 4721 for (j = 0; j < MAX_OPERANDS; j++)
4722 operand_types[j] = t->operand_types[j];
4723
45aa61fe
AM		 4724 /* In general, don't allow 64-bit operands in 32-bit mode. */
4725 if (i.suffix == QWORD_MNEM_SUFFIX
4726 && flag_code != CODE_64BIT
4727 && (intel_syntax
40fb9820 4728 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4729 && !intel_float_operand (t->name))
4730 : intel_float_operand (t->name) != 2)
40fb9820 4731 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4732 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4733 && !operand_types[0].bitfield.regymm
4734 && !operand_types[0].bitfield.regzmm)
40fb9820 4735 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4736 && operand_types[t->operands > 1].bitfield.regxmm
4737 && operand_types[t->operands > 1].bitfield.regymm
4738 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4739 && (t->base_opcode != 0x0fc7
4740 || t->extension_opcode != 1 /* cmpxchg8b */))
4741 continue;
4742
192dc9c6
JB		 4743 /* In general, don't allow 32-bit operands on pre-386. */
4744 else if (i.suffix == LONG_MNEM_SUFFIX
4745 && !cpu_arch_flags.bitfield.cpui386
4746 && (intel_syntax
4747 ? (!t->opcode_modifier.ignoresize
4748 && !intel_float_operand (t->name))
4749 : intel_float_operand (t->name) != 2)
4750 && ((!operand_types[0].bitfield.regmmx
4751 && !operand_types[0].bitfield.regxmm)
4752 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4753 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4754 continue;
4755
29b0f896 4756 /* Do not verify operands when there are none. */
50aecf8c 4757 else
29b0f896 4758 {
c6fb90c8 4759 if (!t->operands)
2dbab7d5
L		 4760 /* We've found a match; break out of loop. */
4761 break;
29b0f896 4762 }
252b5132 4763
539e75ad
L		 4764 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4765 into Disp32/Disp16/Disp32 operand. */
4766 if (i.prefix[ADDR_PREFIX] != 0)
4767 {
40fb9820 4768 /* There should be only one Disp operand. */
539e75ad
L		 4769 switch (flag_code)
4770 {
4771 case CODE_16BIT:
40fb9820
L		 4772 for (j = 0; j < MAX_OPERANDS; j++)
4773 {
4774 if (operand_types[j].bitfield.disp16)
4775 {
4776 addr_prefix_disp = j;
4777 operand_types[j].bitfield.disp32 = 1;
4778 operand_types[j].bitfield.disp16 = 0;
4779 break;
4780 }
4781 }
539e75ad
L		 4782 break;
4783 case CODE_32BIT:
40fb9820
L		 4784 for (j = 0; j < MAX_OPERANDS; j++)
4785 {
4786 if (operand_types[j].bitfield.disp32)
4787 {
4788 addr_prefix_disp = j;
4789 operand_types[j].bitfield.disp32 = 0;
4790 operand_types[j].bitfield.disp16 = 1;
4791 break;
4792 }
4793 }
539e75ad
L		 4794 break;
4795 case CODE_64BIT:
40fb9820
L		 4796 for (j = 0; j < MAX_OPERANDS; j++)
4797 {
4798 if (operand_types[j].bitfield.disp64)
4799 {
4800 addr_prefix_disp = j;
4801 operand_types[j].bitfield.disp64 = 0;
4802 operand_types[j].bitfield.disp32 = 1;
4803 break;
4804 }
4805 }
539e75ad
L		 4806 break;
4807 }
539e75ad
L		 4808 }
4809
56ffb741
L		 4810 /* We check register size if needed. */
4811 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4812 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4813 switch (t->operands)
4814 {
4815 case 1:
40fb9820 4816 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4817 continue;
4818 break;
4819 case 2:
8b38ad71
L		 4820 /* xchg %eax, %eax is a special case. It is an aliase for nop
4821 only in 32bit mode and we can use opcode 0x90. In 64bit
4822 mode, we can't use 0x90 for xchg %eax, %eax since it should
4823 zero-extend %eax to %rax. */
4824 if (flag_code == CODE_64BIT
4825 && t->base_opcode == 0x90
0dfbf9d7
L		 4826 && operand_type_equal (&i.types [0], &acc32)
4827 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4828 continue;
b6169b20
L		 4829 if (i.swap_operand)
4830 {
4831 /* If we swap operand in encoding, we either match
4832 the next one or reverse direction of operands. */
4833 if (t->opcode_modifier.s)
4834 continue;
4835 else if (t->opcode_modifier.d)
4836 goto check_reverse;
4837 }
4838
29b0f896 4839 case 3:
fa99fab2
L		 4840 /* If we swap operand in encoding, we match the next one. */
4841 if (i.swap_operand && t->opcode_modifier.s)
4842 continue;
f48ff2ae 4843 case 4:
c0f3af97 4844 case 5:
c6fb90c8 4845 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4846 if (!operand_type_match (overlap0, i.types[0])
4847 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4848 || (check_register
4849 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4850 operand_types[0],
4851 overlap1, i.types[1],
4852 operand_types[1])))
29b0f896
AM		 4853 {
4854 /* Check if other direction is valid ... */
40fb9820 4855 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4856 continue;
4857
b6169b20 4858check_reverse:
29b0f896 4859 /* Try reversing direction of operands. */
c6fb90c8
L		 4860 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4861 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4862 if (!operand_type_match (overlap0, i.types[0])
4863 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4864 || (check_register
4865 && !operand_type_register_match (overlap0,
4866 i.types[0],
4867 operand_types[1],
4868 overlap1,
4869 i.types[1],
4870 operand_types[0])))
29b0f896
AM		 4871 {
4872 /* Does not match either direction. */
4873 continue;
4874 }
4875 /* found_reverse_match holds which of D or FloatDR
4876 we've found. */
40fb9820 4877 if (t->opcode_modifier.d)
8a2ed489 4878 found_reverse_match = Opcode_D;
40fb9820 4879 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4880 found_reverse_match = Opcode_FloatD;
4881 else
4882 found_reverse_match = 0;
40fb9820 4883 if (t->opcode_modifier.floatr)
8a2ed489 4884 found_reverse_match |= Opcode_FloatR;
29b0f896 4885 }
f48ff2ae 4886 else
29b0f896 4887 {
f48ff2ae 4888 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4889 switch (t->operands)
4890 {
c0f3af97
L		 4891 case 5:
4892 overlap4 = operand_type_and (i.types[4],
4893 operand_types[4]);
d1cbb4db 4894 case 4:
c6fb90c8
L		 4895 overlap3 = operand_type_and (i.types[3],
4896 operand_types[3]);
d1cbb4db 4897 case 3:
c6fb90c8
L		 4898 overlap2 = operand_type_and (i.types[2],
4899 operand_types[2]);
d1cbb4db
L		 4900 break;
4901 }
29b0f896 4902
f48ff2ae
L		 4903 switch (t->operands)
4904 {
c0f3af97
L		 4905 case 5:
4906 if (!operand_type_match (overlap4, i.types[4])
4907 || !operand_type_register_match (overlap3,
4908 i.types[3],
4909 operand_types[3],
4910 overlap4,
4911 i.types[4],
4912 operand_types[4]))
4913 continue;
f48ff2ae 4914 case 4:
40fb9820 4915 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4916 || (check_register
4917 && !operand_type_register_match (overlap2,
4918 i.types[2],
4919 operand_types[2],
4920 overlap3,
4921 i.types[3],
4922 operand_types[3])))
f48ff2ae
L		 4923 continue;
4924 case 3:
4925 /* Here we make use of the fact that there are no
4926 reverse match 3 operand instructions, and all 3
4927 operand instructions only need to be checked for
4928 register consistency between operands 2 and 3. */
40fb9820 4929 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4930 || (check_register
4931 && !operand_type_register_match (overlap1,
4932 i.types[1],
4933 operand_types[1],
4934 overlap2,
4935 i.types[2],
4936 operand_types[2])))
f48ff2ae
L		 4937 continue;
4938 break;
4939 }
29b0f896 4940 }
f48ff2ae 4941 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4942 slip through to break. */
4943 }
3629bb00 4944 if (!found_cpu_match)
29b0f896
AM		 4945 {
4946 found_reverse_match = 0;
4947 continue;
4948 }
c0f3af97 4949
5614d22c
JB		 4950 /* Check if vector and VEX operands are valid. */
4951 if (check_VecOperands (t) || VEX_check_operands (t))
4952 {
4953 specific_error = i.error;
4954 continue;
4955 }
a683cc34 4956
29b0f896
AM		 4957 /* We've found a match; break out of loop. */
4958 break;
4959 }
4960
4961 if (t == current_templates->end)
4962 {
4963 /* We found no match. */
a65babc9 4964 const char *err_msg;
5614d22c 4965 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4966 {
4967 default:
4968 abort ();
86e026a4 4969 case operand_size_mismatch:
a65babc9
L		 4970 err_msg = _("operand size mismatch");
4971 break;
4972 case operand_type_mismatch:
4973 err_msg = _("operand type mismatch");
4974 break;
4975 case register_type_mismatch:
4976 err_msg = _("register type mismatch");
4977 break;
4978 case number_of_operands_mismatch:
4979 err_msg = _("number of operands mismatch");
4980 break;
4981 case invalid_instruction_suffix:
4982 err_msg = _("invalid instruction suffix");
4983 break;
4984 case bad_imm4:
4a2608e3 4985 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4986 break;
4987 case old_gcc_only:
4988 err_msg = _("only supported with old gcc");
4989 break;
4990 case unsupported_with_intel_mnemonic:
4991 err_msg = _("unsupported with Intel mnemonic");
4992 break;
4993 case unsupported_syntax:
4994 err_msg = _("unsupported syntax");
4995 break;
4996 case unsupported:
35262a23 4997 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4998 current_templates->start->name);
4999 return NULL;
6c30d220
L		 5000 case invalid_vsib_address:
5001 err_msg = _("invalid VSIB address");
5002 break;
7bab8ab5
JB		 5003 case invalid_vector_register_set:
5004 err_msg = _("mask, index, and destination registers must be distinct");
5005 break;
6c30d220
L		 5006 case unsupported_vector_index_register:
5007 err_msg = _("unsupported vector index register");
5008 break;
43234a1e
L		 5009 case unsupported_broadcast:
5010 err_msg = _("unsupported broadcast");
5011 break;
5012 case broadcast_not_on_src_operand:
5013 err_msg = _("broadcast not on source memory operand");
5014 break;
5015 case broadcast_needed:
5016 err_msg = _("broadcast is needed for operand of such type");
5017 break;
5018 case unsupported_masking:
5019 err_msg = _("unsupported masking");
5020 break;
5021 case mask_not_on_destination:
5022 err_msg = _("mask not on destination operand");
5023 break;
5024 case no_default_mask:
5025 err_msg = _("default mask isn't allowed");
5026 break;
5027 case unsupported_rc_sae:
5028 err_msg = _("unsupported static rounding/sae");
5029 break;
5030 case rc_sae_operand_not_last_imm:
5031 if (intel_syntax)
5032 err_msg = _("RC/SAE operand must precede immediate operands");
5033 else
5034 err_msg = _("RC/SAE operand must follow immediate operands");
5035 break;
5036 case invalid_register_operand:
5037 err_msg = _("invalid register operand");
5038 break;
a65babc9
L		 5039 }
5040 as_bad (_("%s for `%s'"), err_msg,
891edac4 5041 current_templates->start->name);
fa99fab2 5042 return NULL;
29b0f896 5043 }
252b5132 5044
29b0f896
AM		 5045 if (!quiet_warnings)
5046 {
5047 if (!intel_syntax
40fb9820
L		 5048 && (i.types[0].bitfield.jumpabsolute
5049 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5050 {
5051 as_warn (_("indirect %s without `*'"), t->name);
5052 }
5053
40fb9820
L		 5054 if (t->opcode_modifier.isprefix
5055 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5056 {
5057 /* Warn them that a data or address size prefix doesn't
5058 affect assembly of the next line of code. */
5059 as_warn (_("stand-alone `%s' prefix"), t->name);
5060 }
5061 }
5062
5063 /* Copy the template we found. */
5064 i.tm = *t;
539e75ad
L		 5065
5066 if (addr_prefix_disp != -1)
5067 i.tm.operand_types[addr_prefix_disp]
5068 = operand_types[addr_prefix_disp];
5069
29b0f896
AM		 5070 if (found_reverse_match)
5071 {
5072 /* If we found a reverse match we must alter the opcode
5073 direction bit. found_reverse_match holds bits to change
5074 (different for int & float insns). */
5075
5076 i.tm.base_opcode ^= found_reverse_match;
5077
539e75ad
L		 5078 i.tm.operand_types[0] = operand_types[1];
5079 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5080 }
5081
fa99fab2 5082 return t;
29b0f896
AM		 5083}
5084
5085static int
e3bb37b5 5086check_string (void)
29b0f896 5087{
40fb9820
L		 5088 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5089 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5090 {
5091 if (i.seg[0] != NULL && i.seg[0] != &es)
5092 {
a87af027 5093 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5094 i.tm.name,
a87af027
JB		 5095 mem_op + 1,
5096 register_prefix);
29b0f896
AM		 5097 return 0;
5098 }
5099 /* There's only ever one segment override allowed per instruction.
5100 This instruction possibly has a legal segment override on the
5101 second operand, so copy the segment to where non-string
5102 instructions store it, allowing common code. */
5103 i.seg[0] = i.seg[1];
5104 }
40fb9820 5105 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5106 {
5107 if (i.seg[1] != NULL && i.seg[1] != &es)
5108 {
a87af027 5109 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5110 i.tm.name,
a87af027
JB		 5111 mem_op + 2,
5112 register_prefix);
29b0f896
AM		 5113 return 0;
5114 }
5115 }
5116 return 1;
5117}
5118
5119static int
543613e9 5120process_suffix (void)
29b0f896
AM		 5121{
5122 /* If matched instruction specifies an explicit instruction mnemonic
5123 suffix, use it. */
40fb9820
L		 5124 if (i.tm.opcode_modifier.size16)
5125 i.suffix = WORD_MNEM_SUFFIX;
5126 else if (i.tm.opcode_modifier.size32)
5127 i.suffix = LONG_MNEM_SUFFIX;
5128 else if (i.tm.opcode_modifier.size64)
5129 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5130 else if (i.reg_operands)
5131 {
5132 /* If there's no instruction mnemonic suffix we try to invent one
5133 based on register operands. */
5134 if (!i.suffix)
5135 {
5136 /* We take i.suffix from the last register operand specified,
5137 Destination register type is more significant than source
381d071f
L		 5138 register type. crc32 in SSE4.2 prefers source register
5139 type. */
5140 if (i.tm.base_opcode == 0xf20f38f1)
5141 {
40fb9820
L		 5142 if (i.types[0].bitfield.reg16)
5143 i.suffix = WORD_MNEM_SUFFIX;
5144 else if (i.types[0].bitfield.reg32)
5145 i.suffix = LONG_MNEM_SUFFIX;
5146 else if (i.types[0].bitfield.reg64)
5147 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5148 }
9344ff29 5149 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5150 {
40fb9820 5151 if (i.types[0].bitfield.reg8)
20592a94
L		 5152 i.suffix = BYTE_MNEM_SUFFIX;
5153 }
381d071f
L		 5154
5155 if (!i.suffix)
5156 {
5157 int op;
5158
20592a94
L		 5159 if (i.tm.base_opcode == 0xf20f38f1
5160 || i.tm.base_opcode == 0xf20f38f0)
5161 {
5162 /* We have to know the operand size for crc32. */
5163 as_bad (_("ambiguous memory operand size for `%s`"),
5164 i.tm.name);
5165 return 0;
5166 }
5167
381d071f 5168 for (op = i.operands; --op >= 0;)
40fb9820 5169 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5170 {
40fb9820
L		 5171 if (i.types[op].bitfield.reg8)
5172 {
5173 i.suffix = BYTE_MNEM_SUFFIX;
5174 break;
5175 }
5176 else if (i.types[op].bitfield.reg16)
5177 {
5178 i.suffix = WORD_MNEM_SUFFIX;
5179 break;
5180 }
5181 else if (i.types[op].bitfield.reg32)
5182 {
5183 i.suffix = LONG_MNEM_SUFFIX;
5184 break;
5185 }
5186 else if (i.types[op].bitfield.reg64)
5187 {
5188 i.suffix = QWORD_MNEM_SUFFIX;
5189 break;
5190 }
381d071f
L		 5191 }
5192 }
29b0f896
AM		 5193 }
5194 else if (i.suffix == BYTE_MNEM_SUFFIX)
5195 {
2eb952a4
L		 5196 if (intel_syntax
5197 && i.tm.opcode_modifier.ignoresize
5198 && i.tm.opcode_modifier.no_bsuf)
5199 i.suffix = 0;
5200 else if (!check_byte_reg ())
29b0f896
AM		 5201 return 0;
5202 }
5203 else if (i.suffix == LONG_MNEM_SUFFIX)
5204 {
2eb952a4
L		 5205 if (intel_syntax
5206 && i.tm.opcode_modifier.ignoresize
5207 && i.tm.opcode_modifier.no_lsuf)
5208 i.suffix = 0;
5209 else if (!check_long_reg ())
29b0f896
AM		 5210 return 0;
5211 }
5212 else if (i.suffix == QWORD_MNEM_SUFFIX)
5213 {
955e1e6a
L		 5214 if (intel_syntax
5215 && i.tm.opcode_modifier.ignoresize
5216 && i.tm.opcode_modifier.no_qsuf)
5217 i.suffix = 0;
5218 else if (!check_qword_reg ())
29b0f896
AM		 5219 return 0;
5220 }
5221 else if (i.suffix == WORD_MNEM_SUFFIX)
5222 {
2eb952a4
L		 5223 if (intel_syntax
5224 && i.tm.opcode_modifier.ignoresize
5225 && i.tm.opcode_modifier.no_wsuf)
5226 i.suffix = 0;
5227 else if (!check_word_reg ())
29b0f896
AM		 5228 return 0;
5229 }
c0f3af97 5230 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5231 || i.suffix == YMMWORD_MNEM_SUFFIX
5232 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5233 {
43234a1e 5234 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5235 should check if it is a valid suffix. */
5236 }
40fb9820 5237 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5238 /* Do nothing if the instruction is going to ignore the prefix. */
5239 ;
5240 else
5241 abort ();
5242 }
40fb9820 5243 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5244 && !i.suffix
5245 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5246 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5247 {
5248 i.suffix = stackop_size;
5249 }
9306ca4a
JB		 5250 else if (intel_syntax
5251 && !i.suffix
40fb9820
L		 5252 && (i.tm.operand_types[0].bitfield.jumpabsolute
5253 || i.tm.opcode_modifier.jumpbyte
5254 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5255 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5256 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5257 {
5258 switch (flag_code)
5259 {
5260 case CODE_64BIT:
40fb9820 5261 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5262 {
5263 i.suffix = QWORD_MNEM_SUFFIX;
5264 break;
5265 }
5266 case CODE_32BIT:
40fb9820 5267 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5268 i.suffix = LONG_MNEM_SUFFIX;
5269 break;
5270 case CODE_16BIT:
40fb9820 5271 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5272 i.suffix = WORD_MNEM_SUFFIX;
5273 break;
5274 }
5275 }
252b5132 5276
9306ca4a 5277 if (!i.suffix)
29b0f896 5278 {
9306ca4a
JB		 5279 if (!intel_syntax)
5280 {
40fb9820 5281 if (i.tm.opcode_modifier.w)
9306ca4a 5282 {
4eed87de
AM		 5283 as_bad (_("no instruction mnemonic suffix given and "
5284 "no register operands; can't size instruction"));
9306ca4a
JB		 5285 return 0;
5286 }
5287 }
5288 else
5289 {
40fb9820 5290 unsigned int suffixes;
7ab9ffdd 5291
40fb9820
L		 5292 suffixes = !i.tm.opcode_modifier.no_bsuf;
5293 if (!i.tm.opcode_modifier.no_wsuf)
5294 suffixes |= 1 << 1;
5295 if (!i.tm.opcode_modifier.no_lsuf)
5296 suffixes |= 1 << 2;
fc4adea1 5297 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5298 suffixes |= 1 << 3;
5299 if (!i.tm.opcode_modifier.no_ssuf)
5300 suffixes |= 1 << 4;
5301 if (!i.tm.opcode_modifier.no_qsuf)
5302 suffixes |= 1 << 5;
5303
5304 /* There are more than suffix matches. */
5305 if (i.tm.opcode_modifier.w
9306ca4a 5306 || ((suffixes & (suffixes - 1))
40fb9820
L		 5307 && !i.tm.opcode_modifier.defaultsize
5308 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5309 {
5310 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5311 return 0;
5312 }
5313 }
29b0f896 5314 }
252b5132 5315
9306ca4a
JB		 5316 /* Change the opcode based on the operand size given by i.suffix;
5317 We don't need to change things for byte insns. */
5318
582d5edd
L		 5319 if (i.suffix
5320 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5321 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5322 && i.suffix != YMMWORD_MNEM_SUFFIX
5323 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5324 {
5325 /* It's not a byte, select word/dword operation. */
40fb9820 5326 if (i.tm.opcode_modifier.w)
29b0f896 5327 {
40fb9820 5328 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5329 i.tm.base_opcode |= 8;
5330 else
5331 i.tm.base_opcode |= 1;
5332 }
0f3f3d8b 5333
29b0f896
AM		 5334 /* Now select between word & dword operations via the operand
5335 size prefix, except for instructions that will ignore this
5336 prefix anyway. */
ca61edf2 5337 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5338 {
ca61edf2
L		 5339 /* The address size override prefix changes the size of the
5340 first operand. */
40fb9820
L		 5341 if ((flag_code == CODE_32BIT
5342 && i.op->regs[0].reg_type.bitfield.reg16)
5343 || (flag_code != CODE_32BIT
5344 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5345 if (!add_prefix (ADDR_PREFIX_OPCODE))
5346 return 0;
5347 }
5348 else if (i.suffix != QWORD_MNEM_SUFFIX
5349 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5350 && !i.tm.opcode_modifier.ignoresize
5351 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5352 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5353 || (flag_code == CODE_64BIT
40fb9820 5354 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5355 {
5356 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5357
40fb9820 5358 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5359 prefix = ADDR_PREFIX_OPCODE;
252b5132 5360
29b0f896
AM		 5361 if (!add_prefix (prefix))
5362 return 0;
24eab124 5363 }
252b5132 5364
29b0f896
AM		 5365 /* Set mode64 for an operand. */
5366 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5367 && flag_code == CODE_64BIT
40fb9820 5368 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5369 {
5370 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5371 need rex64. cmpxchg8b is also a special case. */
5372 if (! (i.operands == 2
5373 && i.tm.base_opcode == 0x90
5374 && i.tm.extension_opcode == None
0dfbf9d7
L		 5375 && operand_type_equal (&i.types [0], &acc64)
5376 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5377 && ! (i.operands == 1
5378 && i.tm.base_opcode == 0xfc7
5379 && i.tm.extension_opcode == 1
40fb9820
L		 5380 && !operand_type_check (i.types [0], reg)
5381 && operand_type_check (i.types [0], anymem)))
f6bee062 5382 i.rex |= REX_W;
46e883c5 5383 }
3e73aa7c 5384
29b0f896
AM		 5385 /* Size floating point instruction. */
5386 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5387 if (i.tm.opcode_modifier.floatmf)
543613e9 5388 i.tm.base_opcode ^= 4;
29b0f896 5389 }
7ecd2f8b 5390
29b0f896
AM		 5391 return 1;
5392}
3e73aa7c 5393
29b0f896 5394static int
543613e9 5395check_byte_reg (void)
29b0f896
AM		 5396{
5397 int op;
543613e9 5398
29b0f896
AM		 5399 for (op = i.operands; --op >= 0;)
5400 {
5401 /* If this is an eight bit register, it's OK. If it's the 16 or
5402 32 bit version of an eight bit register, we will just use the
5403 low portion, and that's OK too. */
40fb9820 5404 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5405 continue;
5406
5a819eb9
JB		 5407 /* I/O port address operands are OK too. */
5408 if (i.tm.operand_types[op].bitfield.inoutportreg)
5409 continue;
5410
9344ff29
L		 5411 /* crc32 doesn't generate this warning. */
5412 if (i.tm.base_opcode == 0xf20f38f0)
5413 continue;
5414
40fb9820
L		 5415 if ((i.types[op].bitfield.reg16
5416 || i.types[op].bitfield.reg32
5417 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5418 && i.op[op].regs->reg_num < 4
5419 /* Prohibit these changes in 64bit mode, since the lowering
5420 would be more complicated. */
5421 && flag_code != CODE_64BIT)
29b0f896 5422 {
29b0f896 5423#if REGISTER_WARNINGS
5a819eb9 5424 if (!quiet_warnings)
a540244d
L		 5425 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5426 register_prefix,
40fb9820 5427 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5428 ? REGNAM_AL - REGNAM_AX
5429 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5430 register_prefix,
29b0f896
AM		 5431 i.op[op].regs->reg_name,
5432 i.suffix);
5433#endif
5434 continue;
5435 }
5436 /* Any other register is bad. */
40fb9820
L		 5437 if (i.types[op].bitfield.reg16
5438 || i.types[op].bitfield.reg32
5439 || i.types[op].bitfield.reg64
5440 || i.types[op].bitfield.regmmx
5441 || i.types[op].bitfield.regxmm
c0f3af97 5442 || i.types[op].bitfield.regymm
43234a1e 5443 || i.types[op].bitfield.regzmm
40fb9820
L		 5444 || i.types[op].bitfield.sreg2
5445 || i.types[op].bitfield.sreg3
5446 || i.types[op].bitfield.control
5447 || i.types[op].bitfield.debug
5448 || i.types[op].bitfield.test
5449 || i.types[op].bitfield.floatreg
5450 || i.types[op].bitfield.floatacc)
29b0f896 5451 {
a540244d
L		 5452 as_bad (_("`%s%s' not allowed with `%s%c'"),
5453 register_prefix,
29b0f896
AM		 5454 i.op[op].regs->reg_name,
5455 i.tm.name,
5456 i.suffix);
5457 return 0;
5458 }
5459 }
5460 return 1;
5461}
5462
5463static int
e3bb37b5 5464check_long_reg (void)
29b0f896
AM		 5465{
5466 int op;
5467
5468 for (op = i.operands; --op >= 0;)
5469 /* Reject eight bit registers, except where the template requires
5470 them. (eg. movzb) */
40fb9820
L		 5471 if (i.types[op].bitfield.reg8
5472 && (i.tm.operand_types[op].bitfield.reg16
5473 || i.tm.operand_types[op].bitfield.reg32
5474 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5475 {
a540244d
L		 5476 as_bad (_("`%s%s' not allowed with `%s%c'"),
5477 register_prefix,
29b0f896
AM		 5478 i.op[op].regs->reg_name,
5479 i.tm.name,
5480 i.suffix);
5481 return 0;
5482 }
e4630f71 5483 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5484 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5485 && i.types[op].bitfield.reg16
5486 && (i.tm.operand_types[op].bitfield.reg32
5487 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5488 {
5489 /* Prohibit these changes in the 64bit mode, since the
5490 lowering is more complicated. */
5491 if (flag_code == CODE_64BIT)
252b5132 5492 {
2b5d6a91 5493 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5494 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5495 i.suffix);
5496 return 0;
252b5132 5497 }
29b0f896 5498#if REGISTER_WARNINGS
cecf1424
JB		 5499 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5500 register_prefix,
5501 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5502 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5503#endif
252b5132 5504 }
e4630f71 5505 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5506 else if (i.types[op].bitfield.reg64
5507 && (i.tm.operand_types[op].bitfield.reg32
5508 || i.tm.operand_types[op].bitfield.acc))
252b5132 5509 {
34828aad 5510 if (intel_syntax
ca61edf2 5511 && i.tm.opcode_modifier.toqword
40fb9820 5512 && !i.types[0].bitfield.regxmm)
34828aad 5513 {
ca61edf2 5514 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5515 i.suffix = QWORD_MNEM_SUFFIX;
5516 }
5517 else
5518 {
2b5d6a91 5519 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5520 register_prefix, i.op[op].regs->reg_name,
5521 i.suffix);
5522 return 0;
5523 }
29b0f896
AM		 5524 }
5525 return 1;
5526}
252b5132 5527
29b0f896 5528static int
e3bb37b5 5529check_qword_reg (void)
29b0f896
AM		 5530{
5531 int op;
252b5132 5532
29b0f896
AM		 5533 for (op = i.operands; --op >= 0; )
5534 /* Reject eight bit registers, except where the template requires
5535 them. (eg. movzb) */
40fb9820
L		 5536 if (i.types[op].bitfield.reg8
5537 && (i.tm.operand_types[op].bitfield.reg16
5538 || i.tm.operand_types[op].bitfield.reg32
5539 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5540 {
a540244d
L		 5541 as_bad (_("`%s%s' not allowed with `%s%c'"),
5542 register_prefix,
29b0f896
AM		 5543 i.op[op].regs->reg_name,
5544 i.tm.name,
5545 i.suffix);
5546 return 0;
5547 }
e4630f71 5548 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5549 else if ((i.types[op].bitfield.reg16
5550 || i.types[op].bitfield.reg32)
5551 && (i.tm.operand_types[op].bitfield.reg32
5552 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5553 {
5554 /* Prohibit these changes in the 64bit mode, since the
5555 lowering is more complicated. */
34828aad 5556 if (intel_syntax
ca61edf2 5557 && i.tm.opcode_modifier.todword
40fb9820 5558 && !i.types[0].bitfield.regxmm)
34828aad 5559 {
ca61edf2 5560 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5561 i.suffix = LONG_MNEM_SUFFIX;
5562 }
5563 else
5564 {
2b5d6a91 5565 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5566 register_prefix, i.op[op].regs->reg_name,
5567 i.suffix);
5568 return 0;
5569 }
252b5132 5570 }
29b0f896
AM		 5571 return 1;
5572}
252b5132 5573
29b0f896 5574static int
e3bb37b5 5575check_word_reg (void)
29b0f896
AM		 5576{
5577 int op;
5578 for (op = i.operands; --op >= 0;)
5579 /* Reject eight bit registers, except where the template requires
5580 them. (eg. movzb) */
40fb9820
L		 5581 if (i.types[op].bitfield.reg8
5582 && (i.tm.operand_types[op].bitfield.reg16
5583 || i.tm.operand_types[op].bitfield.reg32
5584 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5585 {
a540244d
L		 5586 as_bad (_("`%s%s' not allowed with `%s%c'"),
5587 register_prefix,
29b0f896
AM		 5588 i.op[op].regs->reg_name,
5589 i.tm.name,
5590 i.suffix);
5591 return 0;
5592 }
e4630f71 5593 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5594 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5595 && (i.types[op].bitfield.reg32
5596 || i.types[op].bitfield.reg64)
40fb9820
L		 5597 && (i.tm.operand_types[op].bitfield.reg16
5598 || i.tm.operand_types[op].bitfield.acc))
252b5132 5599 {
29b0f896
AM		 5600 /* Prohibit these changes in the 64bit mode, since the
5601 lowering is more complicated. */
5602 if (flag_code == CODE_64BIT)
252b5132 5603 {
2b5d6a91 5604 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5605 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5606 i.suffix);
5607 return 0;
252b5132 5608 }
29b0f896 5609#if REGISTER_WARNINGS
cecf1424
JB		 5610 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5611 register_prefix,
5612 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5613 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5614#endif
5615 }
5616 return 1;
5617}
252b5132 5618
29b0f896 5619static int
40fb9820 5620update_imm (unsigned int j)
29b0f896 5621{
bc0844ae 5622 i386_operand_type overlap = i.types[j];
40fb9820
L		 5623 if ((overlap.bitfield.imm8
5624 || overlap.bitfield.imm8s
5625 || overlap.bitfield.imm16
5626 || overlap.bitfield.imm32
5627 || overlap.bitfield.imm32s
5628 || overlap.bitfield.imm64)
0dfbf9d7
L		 5629 && !operand_type_equal (&overlap, &imm8)
5630 && !operand_type_equal (&overlap, &imm8s)
5631 && !operand_type_equal (&overlap, &imm16)
5632 && !operand_type_equal (&overlap, &imm32)
5633 && !operand_type_equal (&overlap, &imm32s)
5634 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5635 {
5636 if (i.suffix)
5637 {
40fb9820
L		 5638 i386_operand_type temp;
5639
0dfbf9d7 5640 operand_type_set (&temp, 0);
7ab9ffdd 5641 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5642 {
5643 temp.bitfield.imm8 = overlap.bitfield.imm8;
5644 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5645 }
5646 else if (i.suffix == WORD_MNEM_SUFFIX)
5647 temp.bitfield.imm16 = overlap.bitfield.imm16;
5648 else if (i.suffix == QWORD_MNEM_SUFFIX)
5649 {
5650 temp.bitfield.imm64 = overlap.bitfield.imm64;
5651 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5652 }
5653 else
5654 temp.bitfield.imm32 = overlap.bitfield.imm32;
5655 overlap = temp;
29b0f896 5656 }
0dfbf9d7
L		 5657 else if (operand_type_equal (&overlap, &imm16_32_32s)
5658 || operand_type_equal (&overlap, &imm16_32)
5659 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5660 {
40fb9820 5661 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5662 overlap = imm16;
40fb9820 5663 else
65da13b5 5664 overlap = imm32s;
29b0f896 5665 }
0dfbf9d7
L		 5666 if (!operand_type_equal (&overlap, &imm8)
5667 && !operand_type_equal (&overlap, &imm8s)
5668 && !operand_type_equal (&overlap, &imm16)
5669 && !operand_type_equal (&overlap, &imm32)
5670 && !operand_type_equal (&overlap, &imm32s)
5671 && !operand_type_equal (&overlap, &imm64))
29b0f896 5672 {
4eed87de
AM		 5673 as_bad (_("no instruction mnemonic suffix given; "
5674 "can't determine immediate size"));
29b0f896
AM		 5675 return 0;
5676 }
5677 }
40fb9820 5678 i.types[j] = overlap;
29b0f896 5679
40fb9820
L		 5680 return 1;
5681}
5682
5683static int
5684finalize_imm (void)
5685{
bc0844ae 5686 unsigned int j, n;
29b0f896 5687
bc0844ae
L		 5688 /* Update the first 2 immediate operands. */
5689 n = i.operands > 2 ? 2 : i.operands;
5690 if (n)
5691 {
5692 for (j = 0; j < n; j++)
5693 if (update_imm (j) == 0)
5694 return 0;
40fb9820 5695
bc0844ae
L		 5696 /* The 3rd operand can't be immediate operand. */
5697 gas_assert (operand_type_check (i.types[2], imm) == 0);
5698 }
29b0f896
AM		 5699
5700 return 1;
5701}
5702
c0f3af97
L		 5703static int
5704bad_implicit_operand (int xmm)
5705{
91d6fa6a
NC		 5706 const char *ireg = xmm ? "xmm0" : "ymm0";
5707
c0f3af97
L		 5708 if (intel_syntax)
5709 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5710 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5711 else
5712 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5713 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5714 return 0;
5715}
5716
29b0f896 5717static int
e3bb37b5 5718process_operands (void)
29b0f896
AM		 5719{
5720 /* Default segment register this instruction will use for memory
5721 accesses. 0 means unknown. This is only for optimizing out
5722 unnecessary segment overrides. */
5723 const seg_entry *default_seg = 0;
5724
2426c15f 5725 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5726 {
91d6fa6a
NC		 5727 unsigned int dupl = i.operands;
5728 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5729 unsigned int j;
5730
c0f3af97 5731 /* The destination must be an xmm register. */
9c2799c2 5732 gas_assert (i.reg_operands
91d6fa6a 5733 && MAX_OPERANDS > dupl
7ab9ffdd 5734 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5735
5736 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5737 {
c0f3af97 5738 /* The first operand is implicit and must be xmm0. */
9c2799c2 5739 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5740 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5741 return bad_implicit_operand (1);
5742
8cd7925b 5743 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5744 {
5745 /* Keep xmm0 for instructions with VEX prefix and 3
5746 sources. */
5747 goto duplicate;
5748 }
e2ec9d29 5749 else
c0f3af97
L		 5750 {
5751 /* We remove the first xmm0 and keep the number of
5752 operands unchanged, which in fact duplicates the
5753 destination. */
5754 for (j = 1; j < i.operands; j++)
5755 {
5756 i.op[j - 1] = i.op[j];
5757 i.types[j - 1] = i.types[j];
5758 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5759 }
5760 }
5761 }
5762 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5763 {
91d6fa6a 5764 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5765 && (i.tm.opcode_modifier.vexsources
5766 == VEX3SOURCES));
c0f3af97
L		 5767
5768 /* Add the implicit xmm0 for instructions with VEX prefix
5769 and 3 sources. */
5770 for (j = i.operands; j > 0; j--)
5771 {
5772 i.op[j] = i.op[j - 1];
5773 i.types[j] = i.types[j - 1];
5774 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5775 }
5776 i.op[0].regs
5777 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5778 i.types[0] = regxmm;
c0f3af97
L		 5779 i.tm.operand_types[0] = regxmm;
5780
5781 i.operands += 2;
5782 i.reg_operands += 2;
5783 i.tm.operands += 2;
5784
91d6fa6a 5785 dupl++;
c0f3af97 5786 dest++;
91d6fa6a
NC		 5787 i.op[dupl] = i.op[dest];
5788 i.types[dupl] = i.types[dest];
5789 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5790 }
c0f3af97
L		 5791 else
5792 {
5793duplicate:
5794 i.operands++;
5795 i.reg_operands++;
5796 i.tm.operands++;
5797
91d6fa6a
NC		 5798 i.op[dupl] = i.op[dest];
5799 i.types[dupl] = i.types[dest];
5800 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5801 }
5802
5803 if (i.tm.opcode_modifier.immext)
5804 process_immext ();
5805 }
5806 else if (i.tm.opcode_modifier.firstxmm0)
5807 {
5808 unsigned int j;
5809
43234a1e 5810 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5811 gas_assert (i.reg_operands
7ab9ffdd 5812 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5813 || operand_type_equal (&i.types[0], &regymm)
5814 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5815 if (register_number (i.op[0].regs) != 0)
c0f3af97 5816 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5817
5818 for (j = 1; j < i.operands; j++)
5819 {
5820 i.op[j - 1] = i.op[j];
5821 i.types[j - 1] = i.types[j];
5822
5823 /* We need to adjust fields in i.tm since they are used by
5824 build_modrm_byte. */
5825 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5826 }
5827
e2ec9d29
L		 5828 i.operands--;
5829 i.reg_operands--;
e2ec9d29
L		 5830 i.tm.operands--;
5831 }
5832 else if (i.tm.opcode_modifier.regkludge)
5833 {
5834 /* The imul $imm, %reg instruction is converted into
5835 imul $imm, %reg, %reg, and the clr %reg instruction
5836 is converted into xor %reg, %reg. */
5837
5838 unsigned int first_reg_op;
5839
5840 if (operand_type_check (i.types[0], reg))
5841 first_reg_op = 0;
5842 else
5843 first_reg_op = 1;
5844 /* Pretend we saw the extra register operand. */
9c2799c2 5845 gas_assert (i.reg_operands == 1
7ab9ffdd 5846 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5847 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5848 i.types[first_reg_op + 1] = i.types[first_reg_op];
5849 i.operands++;
5850 i.reg_operands++;
29b0f896
AM		 5851 }
5852
40fb9820 5853 if (i.tm.opcode_modifier.shortform)
29b0f896 5854 {
40fb9820
L		 5855 if (i.types[0].bitfield.sreg2
5856 || i.types[0].bitfield.sreg3)
29b0f896 5857 {
4eed87de
AM		 5858 if (i.tm.base_opcode == POP_SEG_SHORT
5859 && i.op[0].regs->reg_num == 1)
29b0f896 5860 {
a87af027 5861 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5862 return 0;
29b0f896 5863 }
4eed87de
AM		 5864 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5865 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5866 i.rex |= REX_B;
4eed87de
AM		 5867 }
5868 else
5869 {
7ab9ffdd 5870 /* The register or float register operand is in operand
85f10a01 5871 0 or 1. */
40fb9820 5872 unsigned int op;
7ab9ffdd
L		 5873
5874 if (i.types[0].bitfield.floatreg
5875 || operand_type_check (i.types[0], reg))
5876 op = 0;
5877 else
5878 op = 1;
4eed87de
AM		 5879 /* Register goes in low 3 bits of opcode. */
5880 i.tm.base_opcode |= i.op[op].regs->reg_num;
5881 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5882 i.rex |= REX_B;
40fb9820 5883 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5884 {
4eed87de
AM		 5885 /* Warn about some common errors, but press on regardless.
5886 The first case can be generated by gcc (<= 2.8.1). */
5887 if (i.operands == 2)
5888 {
5889 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5890 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5891 register_prefix, i.op[!intel_syntax].regs->reg_name,
5892 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5893 }
5894 else
5895 {
5896 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5897 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5898 register_prefix, i.op[0].regs->reg_name);
4eed87de 5899 }
29b0f896
AM		 5900 }
5901 }
5902 }
40fb9820 5903 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5904 {
5905 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5906 must be put into the modrm byte). Now, we make the modrm and
5907 index base bytes based on all the info we've collected. */
29b0f896
AM		 5908
5909 default_seg = build_modrm_byte ();
5910 }
8a2ed489 5911 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5912 {
5913 default_seg = &ds;
5914 }
40fb9820 5915 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5916 {
5917 /* For the string instructions that allow a segment override
5918 on one of their operands, the default segment is ds. */
5919 default_seg = &ds;
5920 }
5921
75178d9d
L		 5922 if (i.tm.base_opcode == 0x8d /* lea */
5923 && i.seg[0]
5924 && !quiet_warnings)
30123838 5925 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5926
5927 /* If a segment was explicitly specified, and the specified segment
5928 is not the default, use an opcode prefix to select it. If we
5929 never figured out what the default segment is, then default_seg
5930 will be zero at this point, and the specified segment prefix will
5931 always be used. */
29b0f896
AM		 5932 if ((i.seg[0]) && (i.seg[0] != default_seg))
5933 {
5934 if (!add_prefix (i.seg[0]->seg_prefix))
5935 return 0;
5936 }
5937 return 1;
5938}
5939
5940static const seg_entry *
e3bb37b5 5941build_modrm_byte (void)
29b0f896
AM		 5942{
5943 const seg_entry *default_seg = 0;
c0f3af97 5944 unsigned int source, dest;
8cd7925b 5945 int vex_3_sources;
c0f3af97
L		 5946
5947 /* The first operand of instructions with VEX prefix and 3 sources
5948 must be VEX_Imm4. */
8cd7925b 5949 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5950 if (vex_3_sources)
5951 {
91d6fa6a 5952 unsigned int nds, reg_slot;
4c2c6516 5953 expressionS *exp;
c0f3af97 5954
922d8de8 5955 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5956 && i.tm.opcode_modifier.immext)
5957 {
5958 dest = i.operands - 2;
5959 gas_assert (dest == 3);
5960 }
922d8de8 5961 else
a683cc34 5962 dest = i.operands - 1;
c0f3af97 5963 nds = dest - 1;
922d8de8 5964
a683cc34
SP		 5965 /* There are 2 kinds of instructions:
5966 1. 5 operands: 4 register operands or 3 register operands
5967 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5968 VexW0 or VexW1. The destination must be either XMM, YMM or
5969 ZMM register.
a683cc34
SP		 5970 2. 4 operands: 4 register operands or 3 register operands
5971 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5972 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5973 || (i.reg_operands == 3 && i.mem_operands == 1))
5974 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5975 && (i.tm.opcode_modifier.veximmext
5976 || (i.imm_operands == 1
5977 && i.types[0].bitfield.vec_imm4
5978 && (i.tm.opcode_modifier.vexw == VEXW0
5979 || i.tm.opcode_modifier.vexw == VEXW1)
5980 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5981 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5982 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5983
5984 if (i.imm_operands == 0)
5985 {
5986 /* When there is no immediate operand, generate an 8bit
5987 immediate operand to encode the first operand. */
5988 exp = &im_expressions[i.imm_operands++];
5989 i.op[i.operands].imms = exp;
5990 i.types[i.operands] = imm8;
5991 i.operands++;
5992 /* If VexW1 is set, the first operand is the source and
5993 the second operand is encoded in the immediate operand. */
5994 if (i.tm.opcode_modifier.vexw == VEXW1)
5995 {
5996 source = 0;
5997 reg_slot = 1;
5998 }
5999 else
6000 {
6001 source = 1;
6002 reg_slot = 0;
6003 }
6004
6005 /* FMA swaps REG and NDS. */
6006 if (i.tm.cpu_flags.bitfield.cpufma)
6007 {
6008 unsigned int tmp;
6009 tmp = reg_slot;
6010 reg_slot = nds;
6011 nds = tmp;
6012 }
6013
24981e7b
L		 6014 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6015 &regxmm)
a683cc34 6016 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6017 &regymm)
6018 || operand_type_equal (&i.tm.operand_types[reg_slot],
6019 &regzmm));
a683cc34 6020 exp->X_op = O_constant;
4c692bc7 6021 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6022 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6023 }
922d8de8 6024 else
a683cc34
SP		 6025 {
6026 unsigned int imm_slot;
6027
6028 if (i.tm.opcode_modifier.vexw == VEXW0)
6029 {
6030 /* If VexW0 is set, the third operand is the source and
6031 the second operand is encoded in the immediate
6032 operand. */
6033 source = 2;
6034 reg_slot = 1;
6035 }
6036 else
6037 {
6038 /* VexW1 is set, the second operand is the source and
6039 the third operand is encoded in the immediate
6040 operand. */
6041 source = 1;
6042 reg_slot = 2;
6043 }
6044
6045 if (i.tm.opcode_modifier.immext)
6046 {
6047 /* When ImmExt is set, the immdiate byte is the last
6048 operand. */
6049 imm_slot = i.operands - 1;
6050 source--;
6051 reg_slot--;
6052 }
6053 else
6054 {
6055 imm_slot = 0;
6056
6057 /* Turn on Imm8 so that output_imm will generate it. */
6058 i.types[imm_slot].bitfield.imm8 = 1;
6059 }
6060
24981e7b
L		 6061 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6062 &regxmm)
6063 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6064 &regymm)
6065 || operand_type_equal (&i.tm.operand_types[reg_slot],
6066 &regzmm));
a683cc34 6067 i.op[imm_slot].imms->X_add_number
4c692bc7 6068 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6069 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6070 }
6071
6072 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6073 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6074 &regymm)
6075 || operand_type_equal (&i.tm.operand_types[nds],
6076 &regzmm));
dae39acc 6077 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6078 }
6079 else
6080 source = dest = 0;
29b0f896
AM		 6081
6082 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6083 implicit registers do not count. If there are 3 register
6084 operands, it must be a instruction with VexNDS. For a
6085 instruction with VexNDD, the destination register is encoded
6086 in VEX prefix. If there are 4 register operands, it must be
6087 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6088 if (i.mem_operands == 0
6089 && ((i.reg_operands == 2
2426c15f 6090 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6091 || (i.reg_operands == 3
2426c15f 6092 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6093 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6094 {
cab737b9
L		 6095 switch (i.operands)
6096 {
6097 case 2:
6098 source = 0;
6099 break;
6100 case 3:
c81128dc
L		 6101 /* When there are 3 operands, one of them may be immediate,
6102 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6103 the first operand must be shift count register (cl) or it
6104 is an instruction with VexNDS. */
9c2799c2 6105 gas_assert (i.imm_operands == 1
7ab9ffdd 6106 || (i.imm_operands == 0
2426c15f 6107 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6108 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6109 if (operand_type_check (i.types[0], imm)
6110 || i.types[0].bitfield.shiftcount)
6111 source = 1;
6112 else
6113 source = 0;
cab737b9
L		 6114 break;
6115 case 4:
368d64cc
L		 6116 /* When there are 4 operands, the first two must be 8bit
6117 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6118 one.
6119
6120 For instructions with VexNDS, if the first operand
6121 an imm8, the source operand is the 2nd one. If the last
6122 operand is imm8, the source operand is the first one. */
9c2799c2 6123 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6124 && i.types[0].bitfield.imm8
6125 && i.types[1].bitfield.imm8)
2426c15f 6126 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6127 && i.imm_operands == 1
6128 && (i.types[0].bitfield.imm8
43234a1e
L		 6129 || i.types[i.operands - 1].bitfield.imm8
6130 || i.rounding)));
9f2670f2
L		 6131 if (i.imm_operands == 2)
6132 source = 2;
6133 else
c0f3af97
L		 6134 {
6135 if (i.types[0].bitfield.imm8)
6136 source = 1;
6137 else
6138 source = 0;
6139 }
c0f3af97
L		 6140 break;
6141 case 5:
43234a1e
L		 6142 if (i.tm.opcode_modifier.evex)
6143 {
6144 /* For EVEX instructions, when there are 5 operands, the
6145 first one must be immediate operand. If the second one
6146 is immediate operand, the source operand is the 3th
6147 one. If the last one is immediate operand, the source
6148 operand is the 2nd one. */
6149 gas_assert (i.imm_operands == 2
6150 && i.tm.opcode_modifier.sae
6151 && operand_type_check (i.types[0], imm));
6152 if (operand_type_check (i.types[1], imm))
6153 source = 2;
6154 else if (operand_type_check (i.types[4], imm))
6155 source = 1;
6156 else
6157 abort ();
6158 }
cab737b9
L		 6159 break;
6160 default:
6161 abort ();
6162 }
6163
c0f3af97
L		 6164 if (!vex_3_sources)
6165 {
6166 dest = source + 1;
6167
43234a1e
L		 6168 /* RC/SAE operand could be between DEST and SRC. That happens
6169 when one operand is GPR and the other one is XMM/YMM/ZMM
6170 register. */
6171 if (i.rounding && i.rounding->operand == (int) dest)
6172 dest++;
6173
2426c15f 6174 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6175 {
43234a1e
L		 6176 /* For instructions with VexNDS, the register-only source
6177 operand must be 32/64bit integer, XMM, YMM or ZMM
6178 register. It is encoded in VEX prefix. We need to
6179 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6180
6181 i386_operand_type op;
6182 unsigned int vvvv;
6183
6184 /* Check register-only source operand when two source
6185 operands are swapped. */
6186 if (!i.tm.operand_types[source].bitfield.baseindex
6187 && i.tm.operand_types[dest].bitfield.baseindex)
6188 {
6189 vvvv = source;
6190 source = dest;
6191 }
6192 else
6193 vvvv = dest;
6194
6195 op = i.tm.operand_types[vvvv];
fa99fab2 6196 op.bitfield.regmem = 0;
c0f3af97 6197 if ((dest + 1) >= i.operands
ac4eb736
AM		 6198 || (!op.bitfield.reg32
6199 && op.bitfield.reg64
f12dc422 6200 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6201 && !operand_type_equal (&op, &regymm)
6202 && !operand_type_equal (&op, &regzmm)
6203 && !operand_type_equal (&op, &regmask)))
c0f3af97 6204 abort ();
f12dc422 6205 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6206 dest++;
6207 }
6208 }
29b0f896
AM		 6209
6210 i.rm.mode = 3;
6211 /* One of the register operands will be encoded in the i.tm.reg
6212 field, the other in the combined i.tm.mode and i.tm.regmem
6213 fields. If no form of this instruction supports a memory
6214 destination operand, then we assume the source operand may
6215 sometimes be a memory operand and so we need to store the
6216 destination in the i.rm.reg field. */
40fb9820
L		 6217 if (!i.tm.operand_types[dest].bitfield.regmem
6218 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6219 {
6220 i.rm.reg = i.op[dest].regs->reg_num;
6221 i.rm.regmem = i.op[source].regs->reg_num;
6222 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6223 i.rex |= REX_R;
43234a1e
L		 6224 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6225 i.vrex |= REX_R;
29b0f896 6226 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6227 i.rex |= REX_B;
43234a1e
L		 6228 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6229 i.vrex |= REX_B;
29b0f896
AM		 6230 }
6231 else
6232 {
6233 i.rm.reg = i.op[source].regs->reg_num;
6234 i.rm.regmem = i.op[dest].regs->reg_num;
6235 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6236 i.rex |= REX_B;
43234a1e
L		 6237 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6238 i.vrex |= REX_B;
29b0f896 6239 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6240 i.rex |= REX_R;
43234a1e
L		 6241 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6242 i.vrex |= REX_R;
29b0f896 6243 }
161a04f6 6244 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6245 {
40fb9820
L		 6246 if (!i.types[0].bitfield.control
6247 && !i.types[1].bitfield.control)
c4a530c5 6248 abort ();
161a04f6 6249 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6250 add_prefix (LOCK_PREFIX_OPCODE);
6251 }
29b0f896
AM		 6252 }
6253 else
6254 { /* If it's not 2 reg operands... */
c0f3af97
L		 6255 unsigned int mem;
6256
29b0f896
AM		 6257 if (i.mem_operands)
6258 {
6259 unsigned int fake_zero_displacement = 0;
99018f42 6260 unsigned int op;
4eed87de 6261
7ab9ffdd
L		 6262 for (op = 0; op < i.operands; op++)
6263 if (operand_type_check (i.types[op], anymem))
6264 break;
7ab9ffdd 6265 gas_assert (op < i.operands);
29b0f896 6266
6c30d220
L		 6267 if (i.tm.opcode_modifier.vecsib)
6268 {
6269 if (i.index_reg->reg_num == RegEiz
6270 || i.index_reg->reg_num == RegRiz)
6271 abort ();
6272
6273 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6274 if (!i.base_reg)
6275 {
6276 i.sib.base = NO_BASE_REGISTER;
6277 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6278 /* No Vec_Disp8 if there is no base. */
6279 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6280 i.types[op].bitfield.disp8 = 0;
6281 i.types[op].bitfield.disp16 = 0;
6282 i.types[op].bitfield.disp64 = 0;
6283 if (flag_code != CODE_64BIT)
6284 {
6285 /* Must be 32 bit */
6286 i.types[op].bitfield.disp32 = 1;
6287 i.types[op].bitfield.disp32s = 0;
6288 }
6289 else
6290 {
6291 i.types[op].bitfield.disp32 = 0;
6292 i.types[op].bitfield.disp32s = 1;
6293 }
6294 }
6295 i.sib.index = i.index_reg->reg_num;
6296 if ((i.index_reg->reg_flags & RegRex) != 0)
6297 i.rex |= REX_X;
43234a1e
L		 6298 if ((i.index_reg->reg_flags & RegVRex) != 0)
6299 i.vrex |= REX_X;
6c30d220
L		 6300 }
6301
29b0f896
AM		 6302 default_seg = &ds;
6303
6304 if (i.base_reg == 0)
6305 {
6306 i.rm.mode = 0;
6307 if (!i.disp_operands)
6c30d220
L		 6308 {
6309 fake_zero_displacement = 1;
6310 /* Instructions with VSIB byte need 32bit displacement
6311 if there is no base register. */
6312 if (i.tm.opcode_modifier.vecsib)
6313 i.types[op].bitfield.disp32 = 1;
6314 }
29b0f896
AM		 6315 if (i.index_reg == 0)
6316 {
6c30d220 6317 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6318 /* Operand is just <disp> */
20f0a1fc 6319 if (flag_code == CODE_64BIT)
29b0f896
AM		 6320 {
6321 /* 64bit mode overwrites the 32bit absolute
6322 addressing by RIP relative addressing and
6323 absolute addressing is encoded by one of the
6324 redundant SIB forms. */
6325 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6326 i.sib.base = NO_BASE_REGISTER;
6327 i.sib.index = NO_INDEX_REGISTER;
fc225355 6328 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6329 ? disp32s : disp32);
20f0a1fc 6330 }
fc225355
L		 6331 else if ((flag_code == CODE_16BIT)
6332 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6333 {
6334 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6335 i.types[op] = disp16;
20f0a1fc
NC		 6336 }
6337 else
6338 {
6339 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6340 i.types[op] = disp32;
29b0f896
AM		 6341 }
6342 }
6c30d220 6343 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6344 {
6c30d220 6345 /* !i.base_reg && i.index_reg */
db51cc60
L		 6346 if (i.index_reg->reg_num == RegEiz
6347 || i.index_reg->reg_num == RegRiz)
6348 i.sib.index = NO_INDEX_REGISTER;
6349 else
6350 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6351 i.sib.base = NO_BASE_REGISTER;
6352 i.sib.scale = i.log2_scale_factor;
6353 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6354 /* No Vec_Disp8 if there is no base. */
6355 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6356 i.types[op].bitfield.disp8 = 0;
6357 i.types[op].bitfield.disp16 = 0;
6358 i.types[op].bitfield.disp64 = 0;
29b0f896 6359 if (flag_code != CODE_64BIT)
40fb9820
L		 6360 {
6361 /* Must be 32 bit */
6362 i.types[op].bitfield.disp32 = 1;
6363 i.types[op].bitfield.disp32s = 0;
6364 }
29b0f896 6365 else
40fb9820
L		 6366 {
6367 i.types[op].bitfield.disp32 = 0;
6368 i.types[op].bitfield.disp32s = 1;
6369 }
29b0f896 6370 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6371 i.rex |= REX_X;
29b0f896
AM		 6372 }
6373 }
6374 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6375 else if (i.base_reg->reg_num == RegRip ||
6376 i.base_reg->reg_num == RegEip)
29b0f896 6377 {
6c30d220 6378 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6379 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6380 i.types[op].bitfield.disp8 = 0;
6381 i.types[op].bitfield.disp16 = 0;
6382 i.types[op].bitfield.disp32 = 0;
6383 i.types[op].bitfield.disp32s = 1;
6384 i.types[op].bitfield.disp64 = 0;
43234a1e 6385 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6386 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6387 if (! i.disp_operands)
6388 fake_zero_displacement = 1;
29b0f896 6389 }
40fb9820 6390 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6391 {
6c30d220 6392 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6393 switch (i.base_reg->reg_num)
6394 {
6395 case 3: /* (%bx) */
6396 if (i.index_reg == 0)
6397 i.rm.regmem = 7;
6398 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6399 i.rm.regmem = i.index_reg->reg_num - 6;
6400 break;
6401 case 5: /* (%bp) */
6402 default_seg = &ss;
6403 if (i.index_reg == 0)
6404 {
6405 i.rm.regmem = 6;
40fb9820 6406 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6407 {
6408 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6409 if (i.tm.operand_types[op].bitfield.vec_disp8)
6410 i.types[op].bitfield.vec_disp8 = 1;
6411 else
6412 i.types[op].bitfield.disp8 = 1;
252b5132 6413 fake_zero_displacement = 1;
29b0f896
AM		 6414 }
6415 }
6416 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6417 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6418 break;
6419 default: /* (%si) -> 4 or (%di) -> 5 */
6420 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6421 }
6422 i.rm.mode = mode_from_disp_size (i.types[op]);
6423 }
6424 else /* i.base_reg and 32/64 bit mode */
6425 {
6426 if (flag_code == CODE_64BIT
40fb9820
L		 6427 && operand_type_check (i.types[op], disp))
6428 {
6429 i386_operand_type temp;
0dfbf9d7 6430 operand_type_set (&temp, 0);
40fb9820 6431 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6432 temp.bitfield.vec_disp8
6433 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6434 i.types[op] = temp;
6435 if (i.prefix[ADDR_PREFIX] == 0)
6436 i.types[op].bitfield.disp32s = 1;
6437 else
6438 i.types[op].bitfield.disp32 = 1;
6439 }
20f0a1fc 6440
6c30d220
L		 6441 if (!i.tm.opcode_modifier.vecsib)
6442 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6443 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6444 i.rex |= REX_B;
29b0f896
AM		 6445 i.sib.base = i.base_reg->reg_num;
6446 /* x86-64 ignores REX prefix bit here to avoid decoder
6447 complications. */
848930b2
JB		 6448 if (!(i.base_reg->reg_flags & RegRex)
6449 && (i.base_reg->reg_num == EBP_REG_NUM
6450 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6451 default_seg = &ss;
848930b2 6452 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6453 {
848930b2 6454 fake_zero_displacement = 1;
43234a1e
L		 6455 if (i.tm.operand_types [op].bitfield.vec_disp8)
6456 i.types[op].bitfield.vec_disp8 = 1;
6457 else
6458 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6459 }
6460 i.sib.scale = i.log2_scale_factor;
6461 if (i.index_reg == 0)
6462 {
6c30d220 6463 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6464 /* <disp>(%esp) becomes two byte modrm with no index
6465 register. We've already stored the code for esp
6466 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6467 Any base register besides %esp will not use the
6468 extra modrm byte. */
6469 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6470 }
6c30d220 6471 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6472 {
db51cc60
L		 6473 if (i.index_reg->reg_num == RegEiz
6474 || i.index_reg->reg_num == RegRiz)
6475 i.sib.index = NO_INDEX_REGISTER;
6476 else
6477 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6478 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6479 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6480 i.rex |= REX_X;
29b0f896 6481 }
67a4f2b7
AO		 6482
6483 if (i.disp_operands
6484 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6485 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6486 i.rm.mode = 0;
6487 else
a501d77e
L		 6488 {
6489 if (!fake_zero_displacement
6490 && !i.disp_operands
6491 && i.disp_encoding)
6492 {
6493 fake_zero_displacement = 1;
6494 if (i.disp_encoding == disp_encoding_8bit)
6495 i.types[op].bitfield.disp8 = 1;
6496 else
6497 i.types[op].bitfield.disp32 = 1;
6498 }
6499 i.rm.mode = mode_from_disp_size (i.types[op]);
6500 }
29b0f896 6501 }
252b5132 6502
29b0f896
AM		 6503 if (fake_zero_displacement)
6504 {
6505 /* Fakes a zero displacement assuming that i.types[op]
6506 holds the correct displacement size. */
6507 expressionS *exp;
6508
9c2799c2 6509 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6510 exp = &disp_expressions[i.disp_operands++];
6511 i.op[op].disps = exp;
6512 exp->X_op = O_constant;
6513 exp->X_add_number = 0;
6514 exp->X_add_symbol = (symbolS *) 0;
6515 exp->X_op_symbol = (symbolS *) 0;
6516 }
c0f3af97
L		 6517
6518 mem = op;
29b0f896 6519 }
c0f3af97
L		 6520 else
6521 mem = ~0;
252b5132 6522
8c43a48b 6523 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6524 {
6525 if (operand_type_check (i.types[0], imm))
6526 i.vex.register_specifier = NULL;
6527 else
6528 {
6529 /* VEX.vvvv encodes one of the sources when the first
6530 operand is not an immediate. */
1ef99a7b 6531 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6532 i.vex.register_specifier = i.op[0].regs;
6533 else
6534 i.vex.register_specifier = i.op[1].regs;
6535 }
6536
6537 /* Destination is a XMM register encoded in the ModRM.reg
6538 and VEX.R bit. */
6539 i.rm.reg = i.op[2].regs->reg_num;
6540 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6541 i.rex |= REX_R;
6542
6543 /* ModRM.rm and VEX.B encodes the other source. */
6544 if (!i.mem_operands)
6545 {
6546 i.rm.mode = 3;
6547
1ef99a7b 6548 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6549 i.rm.regmem = i.op[1].regs->reg_num;
6550 else
6551 i.rm.regmem = i.op[0].regs->reg_num;
6552
6553 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6554 i.rex |= REX_B;
6555 }
6556 }
2426c15f 6557 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6558 {
6559 i.vex.register_specifier = i.op[2].regs;
6560 if (!i.mem_operands)
6561 {
6562 i.rm.mode = 3;
6563 i.rm.regmem = i.op[1].regs->reg_num;
6564 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6565 i.rex |= REX_B;
6566 }
6567 }
29b0f896
AM		 6568 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6569 (if any) based on i.tm.extension_opcode. Again, we must be
6570 careful to make sure that segment/control/debug/test/MMX
6571 registers are coded into the i.rm.reg field. */
f88c9eb0 6572 else if (i.reg_operands)
29b0f896 6573 {
99018f42 6574 unsigned int op;
7ab9ffdd
L		 6575 unsigned int vex_reg = ~0;
6576
6577 for (op = 0; op < i.operands; op++)
6578 if (i.types[op].bitfield.reg8
6579 || i.types[op].bitfield.reg16
6580 || i.types[op].bitfield.reg32
6581 || i.types[op].bitfield.reg64
6582 || i.types[op].bitfield.regmmx
6583 || i.types[op].bitfield.regxmm
6584 || i.types[op].bitfield.regymm
7e8b059b 6585 || i.types[op].bitfield.regbnd
43234a1e
L		 6586 || i.types[op].bitfield.regzmm
6587 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6588 || i.types[op].bitfield.sreg2
6589 || i.types[op].bitfield.sreg3
6590 || i.types[op].bitfield.control
6591 || i.types[op].bitfield.debug
6592 || i.types[op].bitfield.test)
6593 break;
c0209578 6594
7ab9ffdd
L		 6595 if (vex_3_sources)
6596 op = dest;
2426c15f 6597 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6598 {
6599 /* For instructions with VexNDS, the register-only
6600 source operand is encoded in VEX prefix. */
6601 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6602
7ab9ffdd 6603 if (op > mem)
c0f3af97 6604 {
7ab9ffdd
L		 6605 vex_reg = op++;
6606 gas_assert (op < i.operands);
c0f3af97
L		 6607 }
6608 else
c0f3af97 6609 {
f12dc422
L		 6610 /* Check register-only source operand when two source
6611 operands are swapped. */
6612 if (!i.tm.operand_types[op].bitfield.baseindex
6613 && i.tm.operand_types[op + 1].bitfield.baseindex)
6614 {
6615 vex_reg = op;
6616 op += 2;
6617 gas_assert (mem == (vex_reg + 1)
6618 && op < i.operands);
6619 }
6620 else
6621 {
6622 vex_reg = op + 1;
6623 gas_assert (vex_reg < i.operands);
6624 }
c0f3af97 6625 }
7ab9ffdd 6626 }
2426c15f 6627 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6628 {
f12dc422 6629 /* For instructions with VexNDD, the register destination
7ab9ffdd 6630 is encoded in VEX prefix. */
f12dc422
L		 6631 if (i.mem_operands == 0)
6632 {
6633 /* There is no memory operand. */
6634 gas_assert ((op + 2) == i.operands);
6635 vex_reg = op + 1;
6636 }
6637 else
8d63c93e 6638 {
f12dc422
L		 6639 /* There are only 2 operands. */
6640 gas_assert (op < 2 && i.operands == 2);
6641 vex_reg = 1;
6642 }
7ab9ffdd
L		 6643 }
6644 else
6645 gas_assert (op < i.operands);
99018f42 6646
7ab9ffdd
L		 6647 if (vex_reg != (unsigned int) ~0)
6648 {
f12dc422 6649 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6650
f12dc422
L		 6651 if (type->bitfield.reg32 != 1
6652 && type->bitfield.reg64 != 1
6653 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6654 && !operand_type_equal (type, &regymm)
6655 && !operand_type_equal (type, &regzmm)
6656 && !operand_type_equal (type, &regmask))
7ab9ffdd 6657 abort ();
f88c9eb0 6658
7ab9ffdd
L		 6659 i.vex.register_specifier = i.op[vex_reg].regs;
6660 }
6661
1b9f0c97
L		 6662 /* Don't set OP operand twice. */
6663 if (vex_reg != op)
7ab9ffdd 6664 {
1b9f0c97
L		 6665 /* If there is an extension opcode to put here, the
6666 register number must be put into the regmem field. */
6667 if (i.tm.extension_opcode != None)
6668 {
6669 i.rm.regmem = i.op[op].regs->reg_num;
6670 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6671 i.rex |= REX_B;
43234a1e
L		 6672 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6673 i.vrex |= REX_B;
1b9f0c97
L		 6674 }
6675 else
6676 {
6677 i.rm.reg = i.op[op].regs->reg_num;
6678 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6679 i.rex |= REX_R;
43234a1e
L		 6680 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6681 i.vrex |= REX_R;
1b9f0c97 6682 }
7ab9ffdd 6683 }
252b5132 6684
29b0f896
AM		 6685 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6686 must set it to 3 to indicate this is a register operand
6687 in the regmem field. */
6688 if (!i.mem_operands)
6689 i.rm.mode = 3;
6690 }
252b5132 6691
29b0f896 6692 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6693 if (i.tm.extension_opcode != None)
29b0f896
AM		 6694 i.rm.reg = i.tm.extension_opcode;
6695 }
6696 return default_seg;
6697}
252b5132 6698
29b0f896 6699static void
e3bb37b5 6700output_branch (void)
29b0f896
AM		 6701{
6702 char *p;
f8a5c266 6703 int size;
29b0f896
AM		 6704 int code16;
6705 int prefix;
6706 relax_substateT subtype;
6707 symbolS *sym;
6708 offsetT off;
6709
f8a5c266 6710 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6711 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6712
6713 prefix = 0;
6714 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6715 {
29b0f896
AM		 6716 prefix = 1;
6717 i.prefixes -= 1;
6718 code16 ^= CODE16;
252b5132 6719 }
29b0f896
AM		 6720 /* Pentium4 branch hints. */
6721 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6722 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6723 {
29b0f896
AM		 6724 prefix++;
6725 i.prefixes--;
6726 }
6727 if (i.prefix[REX_PREFIX] != 0)
6728 {
6729 prefix++;
6730 i.prefixes--;
2f66722d
AM		 6731 }
6732
7e8b059b
L		 6733 /* BND prefixed jump. */
6734 if (i.prefix[BND_PREFIX] != 0)
6735 {
6736 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6737 i.prefixes -= 1;
6738 }
6739
29b0f896
AM		 6740 if (i.prefixes != 0 && !intel_syntax)
6741 as_warn (_("skipping prefixes on this instruction"));
6742
6743 /* It's always a symbol; End frag & setup for relax.
6744 Make sure there is enough room in this frag for the largest
6745 instruction we may generate in md_convert_frag. This is 2
6746 bytes for the opcode and room for the prefix and largest
6747 displacement. */
6748 frag_grow (prefix + 2 + 4);
6749 /* Prefix and 1 opcode byte go in fr_fix. */
6750 p = frag_more (prefix + 1);
6751 if (i.prefix[DATA_PREFIX] != 0)
6752 *p++ = DATA_PREFIX_OPCODE;
6753 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6754 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6755 *p++ = i.prefix[SEG_PREFIX];
6756 if (i.prefix[REX_PREFIX] != 0)
6757 *p++ = i.prefix[REX_PREFIX];
6758 *p = i.tm.base_opcode;
6759
6760 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6761 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6762 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6763 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6764 else
f8a5c266 6765 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6766 subtype |= code16;
3e73aa7c 6767
29b0f896
AM		 6768 sym = i.op[0].disps->X_add_symbol;
6769 off = i.op[0].disps->X_add_number;
3e73aa7c 6770
29b0f896
AM		 6771 if (i.op[0].disps->X_op != O_constant
6772 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6773 {
29b0f896
AM		 6774 /* Handle complex expressions. */
6775 sym = make_expr_symbol (i.op[0].disps);
6776 off = 0;
6777 }
3e73aa7c 6778
29b0f896
AM		 6779 /* 1 possible extra opcode + 4 byte displacement go in var part.
6780 Pass reloc in fr_var. */
d258b828 6781 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 6782}
3e73aa7c 6783
29b0f896 6784static void
e3bb37b5 6785output_jump (void)
29b0f896
AM		 6786{
6787 char *p;
6788 int size;
3e02c1cc 6789 fixS *fixP;
29b0f896 6790
40fb9820 6791 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6792 {
6793 /* This is a loop or jecxz type instruction. */
6794 size = 1;
6795 if (i.prefix[ADDR_PREFIX] != 0)
6796 {
6797 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6798 i.prefixes -= 1;
6799 }
6800 /* Pentium4 branch hints. */
6801 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6802 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6803 {
6804 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6805 i.prefixes--;
3e73aa7c
JH		 6806 }
6807 }
29b0f896
AM		 6808 else
6809 {
6810 int code16;
3e73aa7c 6811
29b0f896
AM		 6812 code16 = 0;
6813 if (flag_code == CODE_16BIT)
6814 code16 = CODE16;
3e73aa7c 6815
29b0f896
AM		 6816 if (i.prefix[DATA_PREFIX] != 0)
6817 {
6818 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6819 i.prefixes -= 1;
6820 code16 ^= CODE16;
6821 }
252b5132 6822
29b0f896
AM		 6823 size = 4;
6824 if (code16)
6825 size = 2;
6826 }
9fcc94b6 6827
29b0f896
AM		 6828 if (i.prefix[REX_PREFIX] != 0)
6829 {
6830 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6831 i.prefixes -= 1;
6832 }
252b5132 6833
7e8b059b
L		 6834 /* BND prefixed jump. */
6835 if (i.prefix[BND_PREFIX] != 0)
6836 {
6837 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6838 i.prefixes -= 1;
6839 }
6840
29b0f896
AM		 6841 if (i.prefixes != 0 && !intel_syntax)
6842 as_warn (_("skipping prefixes on this instruction"));
e0890092 6843
42164a71
L		 6844 p = frag_more (i.tm.opcode_length + size);
6845 switch (i.tm.opcode_length)
6846 {
6847 case 2:
6848 *p++ = i.tm.base_opcode >> 8;
6849 case 1:
6850 *p++ = i.tm.base_opcode;
6851 break;
6852 default:
6853 abort ();
6854 }
e0890092 6855
3e02c1cc 6856 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6857 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 6858
6859 /* All jumps handled here are signed, but don't use a signed limit
6860 check for 32 and 16 bit jumps as we want to allow wrap around at
6861 4G and 64k respectively. */
6862 if (size == 1)
6863 fixP->fx_signed = 1;
29b0f896 6864}
e0890092 6865
29b0f896 6866static void
e3bb37b5 6867output_interseg_jump (void)
29b0f896
AM		 6868{
6869 char *p;
6870 int size;
6871 int prefix;
6872 int code16;
252b5132 6873
29b0f896
AM		 6874 code16 = 0;
6875 if (flag_code == CODE_16BIT)
6876 code16 = CODE16;
a217f122 6877
29b0f896
AM		 6878 prefix = 0;
6879 if (i.prefix[DATA_PREFIX] != 0)
6880 {
6881 prefix = 1;
6882 i.prefixes -= 1;
6883 code16 ^= CODE16;
6884 }
6885 if (i.prefix[REX_PREFIX] != 0)
6886 {
6887 prefix++;
6888 i.prefixes -= 1;
6889 }
252b5132 6890
29b0f896
AM		 6891 size = 4;
6892 if (code16)
6893 size = 2;
252b5132 6894
29b0f896
AM		 6895 if (i.prefixes != 0 && !intel_syntax)
6896 as_warn (_("skipping prefixes on this instruction"));
252b5132 6897
29b0f896
AM		 6898 /* 1 opcode; 2 segment; offset */
6899 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6900
29b0f896
AM		 6901 if (i.prefix[DATA_PREFIX] != 0)
6902 *p++ = DATA_PREFIX_OPCODE;
252b5132 6903
29b0f896
AM		 6904 if (i.prefix[REX_PREFIX] != 0)
6905 *p++ = i.prefix[REX_PREFIX];
252b5132 6906
29b0f896
AM		 6907 *p++ = i.tm.base_opcode;
6908 if (i.op[1].imms->X_op == O_constant)
6909 {
6910 offsetT n = i.op[1].imms->X_add_number;
252b5132 6911
29b0f896
AM		 6912 if (size == 2
6913 && !fits_in_unsigned_word (n)
6914 && !fits_in_signed_word (n))
6915 {
6916 as_bad (_("16-bit jump out of range"));
6917 return;
6918 }
6919 md_number_to_chars (p, n, size);
6920 }
6921 else
6922 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6923 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 6924 if (i.op[0].imms->X_op != O_constant)
6925 as_bad (_("can't handle non absolute segment in `%s'"),
6926 i.tm.name);
6927 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6928}
a217f122 6929
29b0f896 6930static void
e3bb37b5 6931output_insn (void)
29b0f896 6932{
2bbd9c25
JJ		 6933 fragS *insn_start_frag;
6934 offsetT insn_start_off;
6935
29b0f896
AM		 6936 /* Tie dwarf2 debug info to the address at the start of the insn.
6937 We can't do this after the insn has been output as the current
6938 frag may have been closed off. eg. by frag_var. */
6939 dwarf2_emit_insn (0);
6940
2bbd9c25
JJ		 6941 insn_start_frag = frag_now;
6942 insn_start_off = frag_now_fix ();
6943
29b0f896 6944 /* Output jumps. */
40fb9820 6945 if (i.tm.opcode_modifier.jump)
29b0f896 6946 output_branch ();
40fb9820
L		 6947 else if (i.tm.opcode_modifier.jumpbyte
6948 || i.tm.opcode_modifier.jumpdword)
29b0f896 6949 output_jump ();
40fb9820 6950 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6951 output_interseg_jump ();
6952 else
6953 {
6954 /* Output normal instructions here. */
6955 char *p;
6956 unsigned char *q;
47465058 6957 unsigned int j;
331d2d0d 6958 unsigned int prefix;
4dffcebc 6959
d022bddd
IT		 6960 /* Some processors fail on LOCK prefix. This options makes
6961 assembler ignore LOCK prefix and serves as a workaround. */
6962 if (omit_lock_prefix)
6963 {
6964 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
6965 return;
6966 i.prefix[LOCK_PREFIX] = 0;
6967 }
6968
43234a1e
L		 6969 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6970 don't need the explicit prefix. */
6971 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6972 {
c0f3af97 6973 switch (i.tm.opcode_length)
bc4bd9ab 6974 {
c0f3af97
L		 6975 case 3:
6976 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6977 {
c0f3af97
L		 6978 prefix = (i.tm.base_opcode >> 24) & 0xff;
6979 goto check_prefix;
6980 }
6981 break;
6982 case 2:
6983 if ((i.tm.base_opcode & 0xff0000) != 0)
6984 {
6985 prefix = (i.tm.base_opcode >> 16) & 0xff;
6986 if (i.tm.cpu_flags.bitfield.cpupadlock)
6987 {
4dffcebc 6988check_prefix:
c0f3af97 6989 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6990 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6991 != REPE_PREFIX_OPCODE))
6992 add_prefix (prefix);
6993 }
6994 else
4dffcebc
L		 6995 add_prefix (prefix);
6996 }
c0f3af97
L		 6997 break;
6998 case 1:
6999 break;
7000 default:
7001 abort ();
bc4bd9ab 7002 }
c0f3af97 7003
6d19a37a 7004#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7005 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7006 R_X86_64_GOTTPOFF relocation so that linker can safely
7007 perform IE->LE optimization. */
7008 if (x86_elf_abi == X86_64_X32_ABI
7009 && i.operands == 2
7010 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7011 && i.prefix[REX_PREFIX] == 0)
7012 add_prefix (REX_OPCODE);
6d19a37a 7013#endif
cf61b747 7014
c0f3af97
L		 7015 /* The prefix bytes. */
7016 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7017 if (*q)
7018 FRAG_APPEND_1_CHAR (*q);
0f10071e 7019 }
ae5c1c7b 7020 else
c0f3af97
L		 7021 {
7022 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7023 if (*q)
7024 switch (j)
7025 {
7026 case REX_PREFIX:
7027 /* REX byte is encoded in VEX prefix. */
7028 break;
7029 case SEG_PREFIX:
7030 case ADDR_PREFIX:
7031 FRAG_APPEND_1_CHAR (*q);
7032 break;
7033 default:
7034 /* There should be no other prefixes for instructions
7035 with VEX prefix. */
7036 abort ();
7037 }
7038
43234a1e
L		 7039 /* For EVEX instructions i.vrex should become 0 after
7040 build_evex_prefix. For VEX instructions upper 16 registers
7041 aren't available, so VREX should be 0. */
7042 if (i.vrex)
7043 abort ();
c0f3af97
L		 7044 /* Now the VEX prefix. */
7045 p = frag_more (i.vex.length);
7046 for (j = 0; j < i.vex.length; j++)
7047 p[j] = i.vex.bytes[j];
7048 }
252b5132 7049
29b0f896 7050 /* Now the opcode; be careful about word order here! */
4dffcebc 7051 if (i.tm.opcode_length == 1)
29b0f896
AM		 7052 {
7053 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7054 }
7055 else
7056 {
4dffcebc 7057 switch (i.tm.opcode_length)
331d2d0d 7058 {
43234a1e
L		 7059 case 4:
7060 p = frag_more (4);
7061 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7062 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7063 break;
4dffcebc 7064 case 3:
331d2d0d
L		 7065 p = frag_more (3);
7066 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7067 break;
7068 case 2:
7069 p = frag_more (2);
7070 break;
7071 default:
7072 abort ();
7073 break;
331d2d0d 7074 }
0f10071e 7075
29b0f896
AM		 7076 /* Put out high byte first: can't use md_number_to_chars! */
7077 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7078 *p = i.tm.base_opcode & 0xff;
7079 }
3e73aa7c 7080
29b0f896 7081 /* Now the modrm byte and sib byte (if present). */
40fb9820 7082 if (i.tm.opcode_modifier.modrm)
29b0f896 7083 {
4a3523fa
L		 7084 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7085 | i.rm.reg << 3
7086 | i.rm.mode << 6));
29b0f896
AM		 7087 /* If i.rm.regmem == ESP (4)
7088 && i.rm.mode != (Register mode)
7089 && not 16 bit
7090 ==> need second modrm byte. */
7091 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7092 && i.rm.mode != 3
40fb9820 7093 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7094 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7095 | i.sib.index << 3
7096 | i.sib.scale << 6));
29b0f896 7097 }
3e73aa7c 7098
29b0f896 7099 if (i.disp_operands)
2bbd9c25 7100 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7101
29b0f896 7102 if (i.imm_operands)
2bbd9c25 7103 output_imm (insn_start_frag, insn_start_off);
29b0f896 7104 }
252b5132 7105
29b0f896
AM		 7106#ifdef DEBUG386
7107 if (flag_debug)
7108 {
7b81dfbb 7109 pi ("" /*line*/, &i);
29b0f896
AM		 7110 }
7111#endif /* DEBUG386 */
7112}
252b5132 7113
e205caa7
L		 7114/* Return the size of the displacement operand N. */
7115
7116static int
7117disp_size (unsigned int n)
7118{
7119 int size = 4;
43234a1e
L		 7120
7121 /* Vec_Disp8 has to be 8bit. */
7122 if (i.types[n].bitfield.vec_disp8)
7123 size = 1;
7124 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7125 size = 8;
7126 else if (i.types[n].bitfield.disp8)
7127 size = 1;
7128 else if (i.types[n].bitfield.disp16)
7129 size = 2;
e205caa7
L		 7130 return size;
7131}
7132
7133/* Return the size of the immediate operand N. */
7134
7135static int
7136imm_size (unsigned int n)
7137{
7138 int size = 4;
40fb9820
L		 7139 if (i.types[n].bitfield.imm64)
7140 size = 8;
7141 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7142 size = 1;
7143 else if (i.types[n].bitfield.imm16)
7144 size = 2;
e205caa7
L		 7145 return size;
7146}
7147
29b0f896 7148static void
64e74474 7149output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7150{
7151 char *p;
7152 unsigned int n;
252b5132 7153
29b0f896
AM		 7154 for (n = 0; n < i.operands; n++)
7155 {
43234a1e
L		 7156 if (i.types[n].bitfield.vec_disp8
7157 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7158 {
7159 if (i.op[n].disps->X_op == O_constant)
7160 {
e205caa7 7161 int size = disp_size (n);
43234a1e 7162 offsetT val = i.op[n].disps->X_add_number;
252b5132 7163
43234a1e
L		 7164 if (i.types[n].bitfield.vec_disp8)
7165 val >>= i.memshift;
7166 val = offset_in_range (val, size);
29b0f896
AM		 7167 p = frag_more (size);
7168 md_number_to_chars (p, val, size);
7169 }
7170 else
7171 {
f86103b7 7172 enum bfd_reloc_code_real reloc_type;
e205caa7 7173 int size = disp_size (n);
40fb9820 7174 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 7175 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7176
e205caa7 7177 /* We can't have 8 bit displacement here. */
9c2799c2 7178 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7179
29b0f896
AM		 7180 /* The PC relative address is computed relative
7181 to the instruction boundary, so in case immediate
7182 fields follows, we need to adjust the value. */
7183 if (pcrel && i.imm_operands)
7184 {
29b0f896 7185 unsigned int n1;
e205caa7 7186 int sz = 0;
252b5132 7187
29b0f896 7188 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7189 if (operand_type_check (i.types[n1], imm))
252b5132 7190 {
e205caa7
L		 7191 /* Only one immediate is allowed for PC
7192 relative address. */
9c2799c2 7193 gas_assert (sz == 0);
e205caa7
L		 7194 sz = imm_size (n1);
7195 i.op[n].disps->X_add_number -= sz;
252b5132 7196 }
29b0f896 7197 /* We should find the immediate. */
9c2799c2 7198 gas_assert (sz != 0);
29b0f896 7199 }
520dc8e8 7200
29b0f896 7201 p = frag_more (size);
d258b828 7202 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7203 if (GOT_symbol
2bbd9c25 7204 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7205 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7206 || reloc_type == BFD_RELOC_X86_64_32S
7207 || (reloc_type == BFD_RELOC_64
7208 && object_64bit))
d6ab8113
JB		 7209 && (i.op[n].disps->X_op == O_symbol
7210 || (i.op[n].disps->X_op == O_add
7211 && ((symbol_get_value_expression
7212 (i.op[n].disps->X_op_symbol)->X_op)
7213 == O_subtract))))
7214 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7215 {
7216 offsetT add;
7217
7218 if (insn_start_frag == frag_now)
7219 add = (p - frag_now->fr_literal) - insn_start_off;
7220 else
7221 {
7222 fragS *fr;
7223
7224 add = insn_start_frag->fr_fix - insn_start_off;
7225 for (fr = insn_start_frag->fr_next;
7226 fr && fr != frag_now; fr = fr->fr_next)
7227 add += fr->fr_fix;
7228 add += p - frag_now->fr_literal;
7229 }
7230
4fa24527 7231 if (!object_64bit)
7b81dfbb
AJ		 7232 {
7233 reloc_type = BFD_RELOC_386_GOTPC;
7234 i.op[n].imms->X_add_number += add;
7235 }
7236 else if (reloc_type == BFD_RELOC_64)
7237 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7238 else
7b81dfbb
AJ		 7239 /* Don't do the adjustment for x86-64, as there
7240 the pcrel addressing is relative to the _next_
7241 insn, and that is taken care of in other code. */
d6ab8113 7242 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7243 }
062cd5e7 7244 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 7245 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 7246 }
7247 }
7248 }
7249}
252b5132 7250
29b0f896 7251static void
64e74474 7252output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7253{
7254 char *p;
7255 unsigned int n;
252b5132 7256
29b0f896
AM		 7257 for (n = 0; n < i.operands; n++)
7258 {
43234a1e
L		 7259 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7260 if (i.rounding && (int) n == i.rounding->operand)
7261 continue;
7262
40fb9820 7263 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7264 {
7265 if (i.op[n].imms->X_op == O_constant)
7266 {
e205caa7 7267 int size = imm_size (n);
29b0f896 7268 offsetT val;
b4cac588 7269
29b0f896
AM		 7270 val = offset_in_range (i.op[n].imms->X_add_number,
7271 size);
7272 p = frag_more (size);
7273 md_number_to_chars (p, val, size);
7274 }
7275 else
7276 {
7277 /* Not absolute_section.
7278 Need a 32-bit fixup (don't support 8bit
7279 non-absolute imms). Try to support other
7280 sizes ... */
f86103b7 7281 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7282 int size = imm_size (n);
7283 int sign;
29b0f896 7284
40fb9820 7285 if (i.types[n].bitfield.imm32s
a7d61044 7286 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7287 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7288 sign = 1;
e205caa7
L		 7289 else
7290 sign = 0;
520dc8e8 7291
29b0f896 7292 p = frag_more (size);
d258b828 7293 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7294
2bbd9c25
JJ		 7295 /* This is tough to explain. We end up with this one if we
7296 * have operands that look like
7297 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7298 * obtain the absolute address of the GOT, and it is strongly
7299 * preferable from a performance point of view to avoid using
7300 * a runtime relocation for this. The actual sequence of
7301 * instructions often look something like:
7302 *
7303 * call .L66
7304 * .L66:
7305 * popl %ebx
7306 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7307 *
7308 * The call and pop essentially return the absolute address
7309 * of the label .L66 and store it in %ebx. The linker itself
7310 * will ultimately change the first operand of the addl so
7311 * that %ebx points to the GOT, but to keep things simple, the
7312 * .o file must have this operand set so that it generates not
7313 * the absolute address of .L66, but the absolute address of
7314 * itself. This allows the linker itself simply treat a GOTPC
7315 * relocation as asking for a pcrel offset to the GOT to be
7316 * added in, and the addend of the relocation is stored in the
7317 * operand field for the instruction itself.
7318 *
7319 * Our job here is to fix the operand so that it would add
7320 * the correct offset so that %ebx would point to itself. The
7321 * thing that is tricky is that .-.L66 will point to the
7322 * beginning of the instruction, so we need to further modify
7323 * the operand so that it will point to itself. There are
7324 * other cases where you have something like:
7325 *
7326 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7327 *
7328 * and here no correction would be required. Internally in
7329 * the assembler we treat operands of this form as not being
7330 * pcrel since the '.' is explicitly mentioned, and I wonder
7331 * whether it would simplify matters to do it this way. Who
7332 * knows. In earlier versions of the PIC patches, the
7333 * pcrel_adjust field was used to store the correction, but
7334 * since the expression is not pcrel, I felt it would be
7335 * confusing to do it this way. */
7336
d6ab8113 7337 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7338 || reloc_type == BFD_RELOC_X86_64_32S
7339 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7340 && GOT_symbol
7341 && GOT_symbol == i.op[n].imms->X_add_symbol
7342 && (i.op[n].imms->X_op == O_symbol
7343 || (i.op[n].imms->X_op == O_add
7344 && ((symbol_get_value_expression
7345 (i.op[n].imms->X_op_symbol)->X_op)
7346 == O_subtract))))
7347 {
2bbd9c25
JJ		 7348 offsetT add;
7349
7350 if (insn_start_frag == frag_now)
7351 add = (p - frag_now->fr_literal) - insn_start_off;
7352 else
7353 {
7354 fragS *fr;
7355
7356 add = insn_start_frag->fr_fix - insn_start_off;
7357 for (fr = insn_start_frag->fr_next;
7358 fr && fr != frag_now; fr = fr->fr_next)
7359 add += fr->fr_fix;
7360 add += p - frag_now->fr_literal;
7361 }
7362
4fa24527 7363 if (!object_64bit)
d6ab8113 7364 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7365 else if (size == 4)
d6ab8113 7366 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7367 else if (size == 8)
7368 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7369 i.op[n].imms->X_add_number += add;
29b0f896 7370 }
29b0f896
AM		 7371 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7372 i.op[n].imms, 0, reloc_type);
7373 }
7374 }
7375 }
252b5132
RH		 7376}
7377\f
d182319b
JB		 7378/* x86_cons_fix_new is called via the expression parsing code when a
7379 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7380static int cons_sign = -1;
7381
7382void
e3bb37b5 7383x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7384 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7385{
d258b828 7386 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7387
7388#ifdef TE_PE
7389 if (exp->X_op == O_secrel)
7390 {
7391 exp->X_op = O_symbol;
7392 r = BFD_RELOC_32_SECREL;
7393 }
7394#endif
7395
7396 fix_new_exp (frag, off, len, exp, 0, r);
7397}
7398
357d1bd8
L		 7399/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7400 purpose of the `.dc.a' internal pseudo-op. */
7401
7402int
7403x86_address_bytes (void)
7404{
7405 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7406 return 4;
7407 return stdoutput->arch_info->bits_per_address / 8;
7408}
7409
d382c579
TG		 7410#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7411 || defined (LEX_AT)
d258b828 7412# define lex_got(reloc, adjust, types) NULL
718ddfc0 7413#else
f3c180ae
AM		 7414/* Parse operands of the form
7415 <symbol>@GOTOFF+<nnn>
7416 and similar .plt or .got references.
7417
7418 If we find one, set up the correct relocation in RELOC and copy the
7419 input string, minus the `@GOTOFF' into a malloc'd buffer for
7420 parsing by the calling routine. Return this buffer, and if ADJUST
7421 is non-null set it to the length of the string we removed from the
7422 input line. Otherwise return NULL. */
7423static char *
91d6fa6a 7424lex_got (enum bfd_reloc_code_real *rel,
64e74474 7425 int *adjust,
d258b828 7426 i386_operand_type *types)
f3c180ae 7427{
7b81dfbb
AJ		 7428 /* Some of the relocations depend on the size of what field is to
7429 be relocated. But in our callers i386_immediate and i386_displacement
7430 we don't yet know the operand size (this will be set by insn
7431 matching). Hence we record the word32 relocation here,
7432 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7433 static const struct {
7434 const char *str;
cff8d58a 7435 int len;
4fa24527 7436 const enum bfd_reloc_code_real rel[2];
40fb9820 7437 const i386_operand_type types64;
f3c180ae 7438 } gotrel[] = {
8ce3d284 7439#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7440 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7441 BFD_RELOC_SIZE32 },
7442 OPERAND_TYPE_IMM32_64 },
8ce3d284 7443#endif
cff8d58a
L		 7444 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7445 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7446 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7447 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7448 BFD_RELOC_X86_64_PLT32 },
40fb9820 7449 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7450 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7451 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7452 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7453 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7454 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7455 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7456 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7457 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7458 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7459 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7460 BFD_RELOC_X86_64_TLSGD },
40fb9820 7461 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7462 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7463 _dummy_first_bfd_reloc_code_real },
40fb9820 7464 OPERAND_TYPE_NONE },
cff8d58a
L		 7465 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7466 BFD_RELOC_X86_64_TLSLD },
40fb9820 7467 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7468 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7469 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7470 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7471 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7472 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7473 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7474 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7475 _dummy_first_bfd_reloc_code_real },
40fb9820 7476 OPERAND_TYPE_NONE },
cff8d58a
L		 7477 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7478 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7479 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7480 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7481 _dummy_first_bfd_reloc_code_real },
40fb9820 7482 OPERAND_TYPE_NONE },
cff8d58a
L		 7483 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7484 _dummy_first_bfd_reloc_code_real },
40fb9820 7485 OPERAND_TYPE_NONE },
cff8d58a
L		 7486 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7487 BFD_RELOC_X86_64_GOT32 },
40fb9820 7488 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7489 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7490 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7491 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7492 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7493 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7494 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7495 };
7496 char *cp;
7497 unsigned int j;
7498
d382c579 7499#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7500 if (!IS_ELF)
7501 return NULL;
d382c579 7502#endif
718ddfc0 7503
f3c180ae 7504 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7505 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7506 return NULL;
7507
47465058 7508 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7509 {
cff8d58a 7510 int len = gotrel[j].len;
28f81592 7511 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7512 {
4fa24527 7513 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7514 {
28f81592
AM		 7515 int first, second;
7516 char *tmpbuf, *past_reloc;
f3c180ae 7517
91d6fa6a 7518 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7519
3956db08
JB		 7520 if (types)
7521 {
7522 if (flag_code != CODE_64BIT)
40fb9820
L		 7523 {
7524 types->bitfield.imm32 = 1;
7525 types->bitfield.disp32 = 1;
7526 }
3956db08
JB		 7527 else
7528 *types = gotrel[j].types64;
7529 }
7530
8fd4256d 7531 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7532 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7533
28f81592 7534 /* The length of the first part of our input line. */
f3c180ae 7535 first = cp - input_line_pointer;
28f81592
AM		 7536
7537 /* The second part goes from after the reloc token until
67c11a9b 7538 (and including) an end_of_line char or comma. */
28f81592 7539 past_reloc = cp + 1 + len;
67c11a9b
AM		 7540 cp = past_reloc;
7541 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7542 ++cp;
7543 second = cp + 1 - past_reloc;
28f81592
AM		 7544
7545 /* Allocate and copy string. The trailing NUL shouldn't
7546 be necessary, but be safe. */
1e9cc1c2 7547 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7548 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7549 if (second != 0 && *past_reloc != ' ')
7550 /* Replace the relocation token with ' ', so that
7551 errors like foo@GOTOFF1 will be detected. */
7552 tmpbuf[first++] = ' ';
af89796a
L		 7553 else
7554 /* Increment length by 1 if the relocation token is
7555 removed. */
7556 len++;
7557 if (adjust)
7558 *adjust = len;
0787a12d
AM		 7559 memcpy (tmpbuf + first, past_reloc, second);
7560 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7561 return tmpbuf;
7562 }
7563
4fa24527
JB		 7564 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7565 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7566 return NULL;
7567 }
7568 }
7569
7570 /* Might be a symbol version string. Don't as_bad here. */
7571 return NULL;
7572}
4e4f7c87 7573#endif
f3c180ae 7574
a988325c
NC		 7575#ifdef TE_PE
7576#ifdef lex_got
7577#undef lex_got
7578#endif
7579/* Parse operands of the form
7580 <symbol>@SECREL32+<nnn>
7581
7582 If we find one, set up the correct relocation in RELOC and copy the
7583 input string, minus the `@SECREL32' into a malloc'd buffer for
7584 parsing by the calling routine. Return this buffer, and if ADJUST
7585 is non-null set it to the length of the string we removed from the
34bca508
L		 7586 input line. Otherwise return NULL.
7587
a988325c
NC		 7588 This function is copied from the ELF version above adjusted for PE targets. */
7589
7590static char *
7591lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7592 int *adjust ATTRIBUTE_UNUSED,
d258b828 7593 i386_operand_type *types)
a988325c
NC		 7594{
7595 static const struct
7596 {
7597 const char *str;
7598 int len;
7599 const enum bfd_reloc_code_real rel[2];
7600 const i386_operand_type types64;
7601 }
7602 gotrel[] =
7603 {
7604 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7605 BFD_RELOC_32_SECREL },
7606 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7607 };
7608
7609 char *cp;
7610 unsigned j;
7611
7612 for (cp = input_line_pointer; *cp != '@'; cp++)
7613 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7614 return NULL;
7615
7616 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7617 {
7618 int len = gotrel[j].len;
7619
7620 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7621 {
7622 if (gotrel[j].rel[object_64bit] != 0)
7623 {
7624 int first, second;
7625 char *tmpbuf, *past_reloc;
7626
7627 *rel = gotrel[j].rel[object_64bit];
7628 if (adjust)
7629 *adjust = len;
7630
7631 if (types)
7632 {
7633 if (flag_code != CODE_64BIT)
7634 {
7635 types->bitfield.imm32 = 1;
7636 types->bitfield.disp32 = 1;
7637 }
7638 else
7639 *types = gotrel[j].types64;
7640 }
7641
7642 /* The length of the first part of our input line. */
7643 first = cp - input_line_pointer;
7644
7645 /* The second part goes from after the reloc token until
7646 (and including) an end_of_line char or comma. */
7647 past_reloc = cp + 1 + len;
7648 cp = past_reloc;
7649 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7650 ++cp;
7651 second = cp + 1 - past_reloc;
7652
7653 /* Allocate and copy string. The trailing NUL shouldn't
7654 be necessary, but be safe. */
7655 tmpbuf = (char *) xmalloc (first + second + 2);
7656 memcpy (tmpbuf, input_line_pointer, first);
7657 if (second != 0 && *past_reloc != ' ')
7658 /* Replace the relocation token with ' ', so that
7659 errors like foo@SECLREL321 will be detected. */
7660 tmpbuf[first++] = ' ';
7661 memcpy (tmpbuf + first, past_reloc, second);
7662 tmpbuf[first + second] = '\0';
7663 return tmpbuf;
7664 }
7665
7666 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7667 gotrel[j].str, 1 << (5 + object_64bit));
7668 return NULL;
7669 }
7670 }
7671
7672 /* Might be a symbol version string. Don't as_bad here. */
7673 return NULL;
7674}
7675
7676#endif /* TE_PE */
7677
62ebcb5c 7678bfd_reloc_code_real_type
e3bb37b5 7679x86_cons (expressionS *exp, int size)
f3c180ae 7680{
62ebcb5c
AM		 7681 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7682
ee86248c
JB		 7683 intel_syntax = -intel_syntax;
7684
3c7b9c2c 7685 exp->X_md = 0;
4fa24527 7686 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7687 {
7688 /* Handle @GOTOFF and the like in an expression. */
7689 char *save;
7690 char *gotfree_input_line;
4a57f2cf 7691 int adjust = 0;
f3c180ae
AM		 7692
7693 save = input_line_pointer;
d258b828 7694 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7695 if (gotfree_input_line)
7696 input_line_pointer = gotfree_input_line;
7697
7698 expression (exp);
7699
7700 if (gotfree_input_line)
7701 {
7702 /* expression () has merrily parsed up to the end of line,
7703 or a comma - in the wrong buffer. Transfer how far
7704 input_line_pointer has moved to the right buffer. */
7705 input_line_pointer = (save
7706 + (input_line_pointer - gotfree_input_line)
7707 + adjust);
7708 free (gotfree_input_line);
3992d3b7
AM		 7709 if (exp->X_op == O_constant
7710 || exp->X_op == O_absent
7711 || exp->X_op == O_illegal
0398aac5 7712 || exp->X_op == O_register
3992d3b7
AM		 7713 || exp->X_op == O_big)
7714 {
7715 char c = *input_line_pointer;
7716 *input_line_pointer = 0;
7717 as_bad (_("missing or invalid expression `%s'"), save);
7718 *input_line_pointer = c;
7719 }
f3c180ae
AM		 7720 }
7721 }
7722 else
7723 expression (exp);
ee86248c
JB		 7724
7725 intel_syntax = -intel_syntax;
7726
7727 if (intel_syntax)
7728 i386_intel_simplify (exp);
62ebcb5c
AM		 7729
7730 return got_reloc;
f3c180ae 7731}
f3c180ae 7732
9f32dd5b
L		 7733static void
7734signed_cons (int size)
6482c264 7735{
d182319b
JB		 7736 if (flag_code == CODE_64BIT)
7737 cons_sign = 1;
7738 cons (size);
7739 cons_sign = -1;
6482c264
NC		 7740}
7741
d182319b 7742#ifdef TE_PE
6482c264 7743static void
7016a5d5 7744pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7745{
7746 expressionS exp;
7747
7748 do
7749 {
7750 expression (&exp);
7751 if (exp.X_op == O_symbol)
7752 exp.X_op = O_secrel;
7753
7754 emit_expr (&exp, 4);
7755 }
7756 while (*input_line_pointer++ == ',');
7757
7758 input_line_pointer--;
7759 demand_empty_rest_of_line ();
7760}
6482c264
NC		 7761#endif
7762
43234a1e
L		 7763/* Handle Vector operations. */
7764
7765static char *
7766check_VecOperations (char *op_string, char *op_end)
7767{
7768 const reg_entry *mask;
7769 const char *saved;
7770 char *end_op;
7771
7772 while (*op_string
7773 && (op_end == NULL || op_string < op_end))
7774 {
7775 saved = op_string;
7776 if (*op_string == '{')
7777 {
7778 op_string++;
7779
7780 /* Check broadcasts. */
7781 if (strncmp (op_string, "1to", 3) == 0)
7782 {
7783 int bcst_type;
7784
7785 if (i.broadcast)
7786 goto duplicated_vec_op;
7787
7788 op_string += 3;
7789 if (*op_string == '8')
7790 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7791 else if (*op_string == '4')
7792 bcst_type = BROADCAST_1TO4;
7793 else if (*op_string == '2')
7794 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7795 else if (*op_string == '1'
7796 && *(op_string+1) == '6')
7797 {
7798 bcst_type = BROADCAST_1TO16;
7799 op_string++;
7800 }
7801 else
7802 {
7803 as_bad (_("Unsupported broadcast: `%s'"), saved);
7804 return NULL;
7805 }
7806 op_string++;
7807
7808 broadcast_op.type = bcst_type;
7809 broadcast_op.operand = this_operand;
7810 i.broadcast = &broadcast_op;
7811 }
7812 /* Check masking operation. */
7813 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7814 {
7815 /* k0 can't be used for write mask. */
7816 if (mask->reg_num == 0)
7817 {
7818 as_bad (_("`%s' can't be used for write mask"),
7819 op_string);
7820 return NULL;
7821 }
7822
7823 if (!i.mask)
7824 {
7825 mask_op.mask = mask;
7826 mask_op.zeroing = 0;
7827 mask_op.operand = this_operand;
7828 i.mask = &mask_op;
7829 }
7830 else
7831 {
7832 if (i.mask->mask)
7833 goto duplicated_vec_op;
7834
7835 i.mask->mask = mask;
7836
7837 /* Only "{z}" is allowed here. No need to check
7838 zeroing mask explicitly. */
7839 if (i.mask->operand != this_operand)
7840 {
7841 as_bad (_("invalid write mask `%s'"), saved);
7842 return NULL;
7843 }
7844 }
7845
7846 op_string = end_op;
7847 }
7848 /* Check zeroing-flag for masking operation. */
7849 else if (*op_string == 'z')
7850 {
7851 if (!i.mask)
7852 {
7853 mask_op.mask = NULL;
7854 mask_op.zeroing = 1;
7855 mask_op.operand = this_operand;
7856 i.mask = &mask_op;
7857 }
7858 else
7859 {
7860 if (i.mask->zeroing)
7861 {
7862 duplicated_vec_op:
7863 as_bad (_("duplicated `%s'"), saved);
7864 return NULL;
7865 }
7866
7867 i.mask->zeroing = 1;
7868
7869 /* Only "{%k}" is allowed here. No need to check mask
7870 register explicitly. */
7871 if (i.mask->operand != this_operand)
7872 {
7873 as_bad (_("invalid zeroing-masking `%s'"),
7874 saved);
7875 return NULL;
7876 }
7877 }
7878
7879 op_string++;
7880 }
7881 else
7882 goto unknown_vec_op;
7883
7884 if (*op_string != '}')
7885 {
7886 as_bad (_("missing `}' in `%s'"), saved);
7887 return NULL;
7888 }
7889 op_string++;
7890 continue;
7891 }
7892 unknown_vec_op:
7893 /* We don't know this one. */
7894 as_bad (_("unknown vector operation: `%s'"), saved);
7895 return NULL;
7896 }
7897
7898 return op_string;
7899}
7900
252b5132 7901static int
70e41ade 7902i386_immediate (char *imm_start)
252b5132
RH		 7903{
7904 char *save_input_line_pointer;
f3c180ae 7905 char *gotfree_input_line;
252b5132 7906 segT exp_seg = 0;
47926f60 7907 expressionS *exp;
40fb9820
L		 7908 i386_operand_type types;
7909
0dfbf9d7 7910 operand_type_set (&types, ~0);
252b5132
RH		 7911
7912 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7913 {
31b2323c
L		 7914 as_bad (_("at most %d immediate operands are allowed"),
7915 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7916 return 0;
7917 }
7918
7919 exp = &im_expressions[i.imm_operands++];
520dc8e8 7920 i.op[this_operand].imms = exp;
252b5132
RH		 7921
7922 if (is_space_char (*imm_start))
7923 ++imm_start;
7924
7925 save_input_line_pointer = input_line_pointer;
7926 input_line_pointer = imm_start;
7927
d258b828 7928 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7929 if (gotfree_input_line)
7930 input_line_pointer = gotfree_input_line;
252b5132
RH		 7931
7932 exp_seg = expression (exp);
7933
83183c0c 7934 SKIP_WHITESPACE ();
43234a1e
L		 7935
7936 /* Handle vector operations. */
7937 if (*input_line_pointer == '{')
7938 {
7939 input_line_pointer = check_VecOperations (input_line_pointer,
7940 NULL);
7941 if (input_line_pointer == NULL)
7942 return 0;
7943 }
7944
252b5132 7945 if (*input_line_pointer)
f3c180ae 7946 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7947
7948 input_line_pointer = save_input_line_pointer;
f3c180ae 7949 if (gotfree_input_line)
ee86248c
JB		 7950 {
7951 free (gotfree_input_line);
7952
7953 if (exp->X_op == O_constant || exp->X_op == O_register)
7954 exp->X_op = O_illegal;
7955 }
7956
7957 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7958}
252b5132 7959
ee86248c
JB		 7960static int
7961i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7962 i386_operand_type types, const char *imm_start)
7963{
7964 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7965 {
313c53d1
L		 7966 if (imm_start)
7967 as_bad (_("missing or invalid immediate expression `%s'"),
7968 imm_start);
3992d3b7 7969 return 0;
252b5132 7970 }
3e73aa7c 7971 else if (exp->X_op == O_constant)
252b5132 7972 {
47926f60 7973 /* Size it properly later. */
40fb9820 7974 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7975 /* If not 64bit, sign extend val. */
7976 if (flag_code != CODE_64BIT
4eed87de
AM		 7977 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7978 exp->X_add_number
7979 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7980 }
4c63da97 7981#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7982 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7983 && exp_seg != absolute_section
47926f60 7984 && exp_seg != text_section
24eab124
AM		 7985 && exp_seg != data_section
7986 && exp_seg != bss_section
7987 && exp_seg != undefined_section
f86103b7 7988 && !bfd_is_com_section (exp_seg))
252b5132 7989 {
d0b47220 7990 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 7991 return 0;
7992 }
7993#endif
a841bdf5 7994 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 7995 {
313c53d1
L		 7996 if (imm_start)
7997 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 7998 return 0;
7999 }
252b5132
RH		 8000 else
8001 {
8002 /* This is an address. The size of the address will be
24eab124 8003 determined later, depending on destination register,
3e73aa7c 8004 suffix, or the default for the section. */
40fb9820
L		 8005 i.types[this_operand].bitfield.imm8 = 1;
8006 i.types[this_operand].bitfield.imm16 = 1;
8007 i.types[this_operand].bitfield.imm32 = 1;
8008 i.types[this_operand].bitfield.imm32s = 1;
8009 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8010 i.types[this_operand] = operand_type_and (i.types[this_operand],
8011 types);
252b5132
RH		 8012 }
8013
8014 return 1;
8015}
8016
551c1ca1 8017static char *
e3bb37b5 8018i386_scale (char *scale)
252b5132 8019{
551c1ca1
AM		 8020 offsetT val;
8021 char *save = input_line_pointer;
252b5132 8022
551c1ca1
AM		 8023 input_line_pointer = scale;
8024 val = get_absolute_expression ();
8025
8026 switch (val)
252b5132 8027 {
551c1ca1 8028 case 1:
252b5132
RH		 8029 i.log2_scale_factor = 0;
8030 break;
551c1ca1 8031 case 2:
252b5132
RH		 8032 i.log2_scale_factor = 1;
8033 break;
551c1ca1 8034 case 4:
252b5132
RH		 8035 i.log2_scale_factor = 2;
8036 break;
551c1ca1 8037 case 8:
252b5132
RH		 8038 i.log2_scale_factor = 3;
8039 break;
8040 default:
a724f0f4
JB		 8041 {
8042 char sep = *input_line_pointer;
8043
8044 *input_line_pointer = '\0';
8045 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8046 scale);
8047 *input_line_pointer = sep;
8048 input_line_pointer = save;
8049 return NULL;
8050 }
252b5132 8051 }
29b0f896 8052 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8053 {
8054 as_warn (_("scale factor of %d without an index register"),
24eab124 8055 1 << i.log2_scale_factor);
252b5132 8056 i.log2_scale_factor = 0;
252b5132 8057 }
551c1ca1
AM		 8058 scale = input_line_pointer;
8059 input_line_pointer = save;
8060 return scale;
252b5132
RH		 8061}
8062
252b5132 8063static int
e3bb37b5 8064i386_displacement (char *disp_start, char *disp_end)
252b5132 8065{
29b0f896 8066 expressionS *exp;
252b5132
RH		 8067 segT exp_seg = 0;
8068 char *save_input_line_pointer;
f3c180ae 8069 char *gotfree_input_line;
40fb9820
L		 8070 int override;
8071 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8072 int ret;
252b5132 8073
31b2323c
L		 8074 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8075 {
8076 as_bad (_("at most %d displacement operands are allowed"),
8077 MAX_MEMORY_OPERANDS);
8078 return 0;
8079 }
8080
0dfbf9d7 8081 operand_type_set (&bigdisp, 0);
40fb9820
L		 8082 if ((i.types[this_operand].bitfield.jumpabsolute)
8083 || (!current_templates->start->opcode_modifier.jump
8084 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8085 {
40fb9820 8086 bigdisp.bitfield.disp32 = 1;
e05278af 8087 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8088 if (flag_code == CODE_64BIT)
8089 {
8090 if (!override)
8091 {
8092 bigdisp.bitfield.disp32s = 1;
8093 bigdisp.bitfield.disp64 = 1;
8094 }
8095 }
8096 else if ((flag_code == CODE_16BIT) ^ override)
8097 {
8098 bigdisp.bitfield.disp32 = 0;
8099 bigdisp.bitfield.disp16 = 1;
8100 }
e05278af
JB		 8101 }
8102 else
8103 {
8104 /* For PC-relative branches, the width of the displacement
8105 is dependent upon data size, not address size. */
e05278af 8106 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8107 if (flag_code == CODE_64BIT)
8108 {
8109 if (override || i.suffix == WORD_MNEM_SUFFIX)
8110 bigdisp.bitfield.disp16 = 1;
8111 else
8112 {
8113 bigdisp.bitfield.disp32 = 1;
8114 bigdisp.bitfield.disp32s = 1;
8115 }
8116 }
8117 else
e05278af
JB		 8118 {
8119 if (!override)
8120 override = (i.suffix == (flag_code != CODE_16BIT
8121 ? WORD_MNEM_SUFFIX
8122 : LONG_MNEM_SUFFIX));
40fb9820
L		 8123 bigdisp.bitfield.disp32 = 1;
8124 if ((flag_code == CODE_16BIT) ^ override)
8125 {
8126 bigdisp.bitfield.disp32 = 0;
8127 bigdisp.bitfield.disp16 = 1;
8128 }
e05278af 8129 }
e05278af 8130 }
c6fb90c8
L		 8131 i.types[this_operand] = operand_type_or (i.types[this_operand],
8132 bigdisp);
252b5132
RH		 8133
8134 exp = &disp_expressions[i.disp_operands];
520dc8e8 8135 i.op[this_operand].disps = exp;
252b5132
RH		 8136 i.disp_operands++;
8137 save_input_line_pointer = input_line_pointer;
8138 input_line_pointer = disp_start;
8139 END_STRING_AND_SAVE (disp_end);
8140
8141#ifndef GCC_ASM_O_HACK
8142#define GCC_ASM_O_HACK 0
8143#endif
8144#if GCC_ASM_O_HACK
8145 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8146 if (i.types[this_operand].bitfield.baseIndex
24eab124 8147 && displacement_string_end[-1] == '+')
252b5132
RH		 8148 {
8149 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8150 constraint within gcc asm statements.
8151 For instance:
8152
8153 #define _set_tssldt_desc(n,addr,limit,type) \
8154 __asm__ __volatile__ ( \
8155 "movw %w2,%0\n\t" \
8156 "movw %w1,2+%0\n\t" \
8157 "rorl $16,%1\n\t" \
8158 "movb %b1,4+%0\n\t" \
8159 "movb %4,5+%0\n\t" \
8160 "movb $0,6+%0\n\t" \
8161 "movb %h1,7+%0\n\t" \
8162 "rorl $16,%1" \
8163 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8164
8165 This works great except that the output assembler ends
8166 up looking a bit weird if it turns out that there is
8167 no offset. You end up producing code that looks like:
8168
8169 #APP
8170 movw $235,(%eax)
8171 movw %dx,2+(%eax)
8172 rorl $16,%edx
8173 movb %dl,4+(%eax)
8174 movb $137,5+(%eax)
8175 movb $0,6+(%eax)
8176 movb %dh,7+(%eax)
8177 rorl $16,%edx
8178 #NO_APP
8179
47926f60 8180 So here we provide the missing zero. */
24eab124
AM		 8181
8182 *displacement_string_end = '0';
252b5132
RH		 8183 }
8184#endif
d258b828 8185 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8186 if (gotfree_input_line)
8187 input_line_pointer = gotfree_input_line;
252b5132 8188
24eab124 8189 exp_seg = expression (exp);
252b5132 8190
636c26b0
AM		 8191 SKIP_WHITESPACE ();
8192 if (*input_line_pointer)
8193 as_bad (_("junk `%s' after expression"), input_line_pointer);
8194#if GCC_ASM_O_HACK
8195 RESTORE_END_STRING (disp_end + 1);
8196#endif
636c26b0 8197 input_line_pointer = save_input_line_pointer;
636c26b0 8198 if (gotfree_input_line)
ee86248c
JB		 8199 {
8200 free (gotfree_input_line);
8201
8202 if (exp->X_op == O_constant || exp->X_op == O_register)
8203 exp->X_op = O_illegal;
8204 }
8205
8206 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8207
8208 RESTORE_END_STRING (disp_end);
8209
8210 return ret;
8211}
8212
8213static int
8214i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8215 i386_operand_type types, const char *disp_start)
8216{
8217 i386_operand_type bigdisp;
8218 int ret = 1;
636c26b0 8219
24eab124
AM		 8220 /* We do this to make sure that the section symbol is in
8221 the symbol table. We will ultimately change the relocation
47926f60 8222 to be relative to the beginning of the section. */
1ae12ab7 8223 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8224 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8225 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8226 {
636c26b0 8227 if (exp->X_op != O_symbol)
3992d3b7 8228 goto inv_disp;
636c26b0 8229
e5cb08ac 8230 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8231 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8232 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8233 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8234 exp->X_op = O_subtract;
8235 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8236 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8237 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8238 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8239 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8240 else
29b0f896 8241 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8242 }
252b5132 8243
3992d3b7
AM		 8244 else if (exp->X_op == O_absent
8245 || exp->X_op == O_illegal
ee86248c 8246 || exp->X_op == O_big)
2daf4fd8 8247 {
3992d3b7
AM		 8248 inv_disp:
8249 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8250 disp_start);
3992d3b7 8251 ret = 0;
2daf4fd8
AM		 8252 }
8253
0e1147d9
L		 8254 else if (flag_code == CODE_64BIT
8255 && !i.prefix[ADDR_PREFIX]
8256 && exp->X_op == O_constant)
8257 {
8258 /* Since displacement is signed extended to 64bit, don't allow
8259 disp32 and turn off disp32s if they are out of range. */
8260 i.types[this_operand].bitfield.disp32 = 0;
8261 if (!fits_in_signed_long (exp->X_add_number))
8262 {
8263 i.types[this_operand].bitfield.disp32s = 0;
8264 if (i.types[this_operand].bitfield.baseindex)
8265 {
8266 as_bad (_("0x%lx out range of signed 32bit displacement"),
8267 (long) exp->X_add_number);
8268 ret = 0;
8269 }
8270 }
8271 }
8272
4c63da97 8273#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8274 else if (exp->X_op != O_constant
8275 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8276 && exp_seg != absolute_section
8277 && exp_seg != text_section
8278 && exp_seg != data_section
8279 && exp_seg != bss_section
8280 && exp_seg != undefined_section
8281 && !bfd_is_com_section (exp_seg))
24eab124 8282 {
d0b47220 8283 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8284 ret = 0;
24eab124 8285 }
252b5132 8286#endif
3956db08 8287
40fb9820
L		 8288 /* Check if this is a displacement only operand. */
8289 bigdisp = i.types[this_operand];
8290 bigdisp.bitfield.disp8 = 0;
8291 bigdisp.bitfield.disp16 = 0;
8292 bigdisp.bitfield.disp32 = 0;
8293 bigdisp.bitfield.disp32s = 0;
8294 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8295 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8296 i.types[this_operand] = operand_type_and (i.types[this_operand],
8297 types);
3956db08 8298
3992d3b7 8299 return ret;
252b5132
RH		 8300}
8301
eecb386c 8302/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8303 Return 1 on success, 0 on a failure. */
8304
252b5132 8305static int
e3bb37b5 8306i386_index_check (const char *operand_string)
252b5132 8307{
fc0763e6 8308 const char *kind = "base/index";
be05d201
L		 8309 enum flag_code addr_mode;
8310
8311 if (i.prefix[ADDR_PREFIX])
8312 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8313 else
8314 {
8315 addr_mode = flag_code;
8316
24eab124 8317#if INFER_ADDR_PREFIX
be05d201
L		 8318 if (i.mem_operands == 0)
8319 {
8320 /* Infer address prefix from the first memory operand. */
8321 const reg_entry *addr_reg = i.base_reg;
8322
8323 if (addr_reg == NULL)
8324 addr_reg = i.index_reg;
eecb386c 8325
be05d201
L		 8326 if (addr_reg)
8327 {
8328 if (addr_reg->reg_num == RegEip
8329 || addr_reg->reg_num == RegEiz
8330 || addr_reg->reg_type.bitfield.reg32)
8331 addr_mode = CODE_32BIT;
8332 else if (flag_code != CODE_64BIT
8333 && addr_reg->reg_type.bitfield.reg16)
8334 addr_mode = CODE_16BIT;
8335
8336 if (addr_mode != flag_code)
8337 {
8338 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8339 i.prefixes += 1;
8340 /* Change the size of any displacement too. At most one
8341 of Disp16 or Disp32 is set.
8342 FIXME. There doesn't seem to be any real need for
8343 separate Disp16 and Disp32 flags. The same goes for
8344 Imm16 and Imm32. Removing them would probably clean
8345 up the code quite a lot. */
8346 if (flag_code != CODE_64BIT
8347 && (i.types[this_operand].bitfield.disp16
8348 || i.types[this_operand].bitfield.disp32))
8349 i.types[this_operand]
8350 = operand_type_xor (i.types[this_operand], disp16_32);
8351 }
8352 }
8353 }
24eab124 8354#endif
be05d201
L		 8355 }
8356
fc0763e6
JB		 8357 if (current_templates->start->opcode_modifier.isstring
8358 && !current_templates->start->opcode_modifier.immext
8359 && (current_templates->end[-1].opcode_modifier.isstring
8360 || i.mem_operands))
8361 {
8362 /* Memory operands of string insns are special in that they only allow
8363 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8364 const reg_entry *expected_reg;
8365 static const char *di_si[][2] =
8366 {
8367 { "esi", "edi" },
8368 { "si", "di" },
8369 { "rsi", "rdi" }
8370 };
8371 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8372
8373 kind = "string address";
8374
8375 if (current_templates->start->opcode_modifier.w)
8376 {
8377 i386_operand_type type = current_templates->end[-1].operand_types[0];
8378
8379 if (!type.bitfield.baseindex
8380 || ((!i.mem_operands != !intel_syntax)
8381 && current_templates->end[-1].operand_types[1]
8382 .bitfield.baseindex))
8383 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8384 expected_reg = hash_find (reg_hash,
8385 di_si[addr_mode][type.bitfield.esseg]);
8386
fc0763e6
JB		 8387 }
8388 else
be05d201 8389 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8390
be05d201
L		 8391 if (i.base_reg != expected_reg
8392 || i.index_reg
fc0763e6 8393 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8394 {
be05d201
L		 8395 /* The second memory operand must have the same size as
8396 the first one. */
8397 if (i.mem_operands
8398 && i.base_reg
8399 && !((addr_mode == CODE_64BIT
8400 && i.base_reg->reg_type.bitfield.reg64)
8401 || (addr_mode == CODE_32BIT
8402 ? i.base_reg->reg_type.bitfield.reg32
8403 : i.base_reg->reg_type.bitfield.reg16)))
8404 goto bad_address;
8405
fc0763e6
JB		 8406 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8407 operand_string,
8408 intel_syntax ? '[' : '(',
8409 register_prefix,
be05d201 8410 expected_reg->reg_name,
fc0763e6 8411 intel_syntax ? ']' : ')');
be05d201 8412 return 1;
fc0763e6 8413 }
be05d201
L		 8414 else
8415 return 1;
8416
8417bad_address:
8418 as_bad (_("`%s' is not a valid %s expression"),
8419 operand_string, kind);
8420 return 0;
3e73aa7c
JH		 8421 }
8422 else
8423 {
be05d201
L		 8424 if (addr_mode != CODE_16BIT)
8425 {
8426 /* 32-bit/64-bit checks. */
8427 if ((i.base_reg
8428 && (addr_mode == CODE_64BIT
8429 ? !i.base_reg->reg_type.bitfield.reg64
8430 : !i.base_reg->reg_type.bitfield.reg32)
8431 && (i.index_reg
8432 || (i.base_reg->reg_num
8433 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8434 || (i.index_reg
8435 && !i.index_reg->reg_type.bitfield.regxmm
8436 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8437 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8438 && ((addr_mode == CODE_64BIT
8439 ? !(i.index_reg->reg_type.bitfield.reg64
8440 || i.index_reg->reg_num == RegRiz)
8441 : !(i.index_reg->reg_type.bitfield.reg32
8442 || i.index_reg->reg_num == RegEiz))
8443 || !i.index_reg->reg_type.bitfield.baseindex)))
8444 goto bad_address;
8445 }
8446 else
3e73aa7c 8447 {
be05d201 8448 /* 16-bit checks. */
3e73aa7c 8449 if ((i.base_reg
40fb9820
L		 8450 && (!i.base_reg->reg_type.bitfield.reg16
8451 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8452 || (i.index_reg
40fb9820
L		 8453 && (!i.index_reg->reg_type.bitfield.reg16
8454 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8455 || !(i.base_reg
8456 && i.base_reg->reg_num < 6
8457 && i.index_reg->reg_num >= 6
8458 && i.log2_scale_factor == 0))))
be05d201 8459 goto bad_address;
3e73aa7c
JH		 8460 }
8461 }
be05d201 8462 return 1;
24eab124 8463}
252b5132 8464
43234a1e
L		 8465/* Handle vector immediates. */
8466
8467static int
8468RC_SAE_immediate (const char *imm_start)
8469{
8470 unsigned int match_found, j;
8471 const char *pstr = imm_start;
8472 expressionS *exp;
8473
8474 if (*pstr != '{')
8475 return 0;
8476
8477 pstr++;
8478 match_found = 0;
8479 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8480 {
8481 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8482 {
8483 if (!i.rounding)
8484 {
8485 rc_op.type = RC_NamesTable[j].type;
8486 rc_op.operand = this_operand;
8487 i.rounding = &rc_op;
8488 }
8489 else
8490 {
8491 as_bad (_("duplicated `%s'"), imm_start);
8492 return 0;
8493 }
8494 pstr += RC_NamesTable[j].len;
8495 match_found = 1;
8496 break;
8497 }
8498 }
8499 if (!match_found)
8500 return 0;
8501
8502 if (*pstr++ != '}')
8503 {
8504 as_bad (_("Missing '}': '%s'"), imm_start);
8505 return 0;
8506 }
8507 /* RC/SAE immediate string should contain nothing more. */;
8508 if (*pstr != 0)
8509 {
8510 as_bad (_("Junk after '}': '%s'"), imm_start);
8511 return 0;
8512 }
8513
8514 exp = &im_expressions[i.imm_operands++];
8515 i.op[this_operand].imms = exp;
8516
8517 exp->X_op = O_constant;
8518 exp->X_add_number = 0;
8519 exp->X_add_symbol = (symbolS *) 0;
8520 exp->X_op_symbol = (symbolS *) 0;
8521
8522 i.types[this_operand].bitfield.imm8 = 1;
8523 return 1;
8524}
8525
fc0763e6 8526/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8527 on error. */
252b5132 8528
252b5132 8529static int
a7619375 8530i386_att_operand (char *operand_string)
252b5132 8531{
af6bdddf
AM		 8532 const reg_entry *r;
8533 char *end_op;
24eab124 8534 char *op_string = operand_string;
252b5132 8535
24eab124 8536 if (is_space_char (*op_string))
252b5132
RH		 8537 ++op_string;
8538
24eab124 8539 /* We check for an absolute prefix (differentiating,
47926f60 8540 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8541 if (*op_string == ABSOLUTE_PREFIX)
8542 {
8543 ++op_string;
8544 if (is_space_char (*op_string))
8545 ++op_string;
40fb9820 8546 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8547 }
252b5132 8548
47926f60 8549 /* Check if operand is a register. */
4d1bb795 8550 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8551 {
40fb9820
L		 8552 i386_operand_type temp;
8553
24eab124
AM		 8554 /* Check for a segment override by searching for ':' after a
8555 segment register. */
8556 op_string = end_op;
8557 if (is_space_char (*op_string))
8558 ++op_string;
40fb9820
L		 8559 if (*op_string == ':'
8560 && (r->reg_type.bitfield.sreg2
8561 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8562 {
8563 switch (r->reg_num)
8564 {
8565 case 0:
8566 i.seg[i.mem_operands] = &es;
8567 break;
8568 case 1:
8569 i.seg[i.mem_operands] = &cs;
8570 break;
8571 case 2:
8572 i.seg[i.mem_operands] = &ss;
8573 break;
8574 case 3:
8575 i.seg[i.mem_operands] = &ds;
8576 break;
8577 case 4:
8578 i.seg[i.mem_operands] = &fs;
8579 break;
8580 case 5:
8581 i.seg[i.mem_operands] = &gs;
8582 break;
8583 }
252b5132 8584
24eab124 8585 /* Skip the ':' and whitespace. */
252b5132
RH		 8586 ++op_string;
8587 if (is_space_char (*op_string))
24eab124 8588 ++op_string;
252b5132 8589
24eab124
AM		 8590 if (!is_digit_char (*op_string)
8591 && !is_identifier_char (*op_string)
8592 && *op_string != '('
8593 && *op_string != ABSOLUTE_PREFIX)
8594 {
8595 as_bad (_("bad memory operand `%s'"), op_string);
8596 return 0;
8597 }
47926f60 8598 /* Handle case of %es:*foo. */
24eab124
AM		 8599 if (*op_string == ABSOLUTE_PREFIX)
8600 {
8601 ++op_string;
8602 if (is_space_char (*op_string))
8603 ++op_string;
40fb9820 8604 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8605 }
8606 goto do_memory_reference;
8607 }
43234a1e
L		 8608
8609 /* Handle vector operations. */
8610 if (*op_string == '{')
8611 {
8612 op_string = check_VecOperations (op_string, NULL);
8613 if (op_string == NULL)
8614 return 0;
8615 }
8616
24eab124
AM		 8617 if (*op_string)
8618 {
d0b47220 8619 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8620 return 0;
8621 }
40fb9820
L		 8622 temp = r->reg_type;
8623 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8624 i.types[this_operand] = operand_type_or (i.types[this_operand],
8625 temp);
7d5e4556 8626 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8627 i.op[this_operand].regs = r;
24eab124
AM		 8628 i.reg_operands++;
8629 }
af6bdddf
AM		 8630 else if (*op_string == REGISTER_PREFIX)
8631 {
8632 as_bad (_("bad register name `%s'"), op_string);
8633 return 0;
8634 }
24eab124 8635 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8636 {
24eab124 8637 ++op_string;
40fb9820 8638 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8639 {
d0b47220 8640 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8641 return 0;
8642 }
8643 if (!i386_immediate (op_string))
8644 return 0;
8645 }
43234a1e
L		 8646 else if (RC_SAE_immediate (operand_string))
8647 {
8648 /* If it is a RC or SAE immediate, do nothing. */
8649 ;
8650 }
24eab124
AM		 8651 else if (is_digit_char (*op_string)
8652 || is_identifier_char (*op_string)
e5cb08ac 8653 || *op_string == '(')
24eab124 8654 {
47926f60 8655 /* This is a memory reference of some sort. */
af6bdddf 8656 char *base_string;
252b5132 8657
47926f60 8658 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8659 char *displacement_string_start;
8660 char *displacement_string_end;
43234a1e 8661 char *vop_start;
252b5132 8662
24eab124 8663 do_memory_reference:
24eab124 8664 if ((i.mem_operands == 1
40fb9820 8665 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8666 || i.mem_operands == 2)
8667 {
8668 as_bad (_("too many memory references for `%s'"),
8669 current_templates->start->name);
8670 return 0;
8671 }
252b5132 8672
24eab124
AM		 8673 /* Check for base index form. We detect the base index form by
8674 looking for an ')' at the end of the operand, searching
8675 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8676 after the '('. */
af6bdddf 8677 base_string = op_string + strlen (op_string);
c3332e24 8678
43234a1e
L		 8679 /* Handle vector operations. */
8680 vop_start = strchr (op_string, '{');
8681 if (vop_start && vop_start < base_string)
8682 {
8683 if (check_VecOperations (vop_start, base_string) == NULL)
8684 return 0;
8685 base_string = vop_start;
8686 }
8687
af6bdddf
AM		 8688 --base_string;
8689 if (is_space_char (*base_string))
8690 --base_string;
252b5132 8691
47926f60 8692 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8693 displacement_string_start = op_string;
8694 displacement_string_end = base_string + 1;
252b5132 8695
24eab124
AM		 8696 if (*base_string == ')')
8697 {
af6bdddf 8698 char *temp_string;
24eab124
AM		 8699 unsigned int parens_balanced = 1;
8700 /* We've already checked that the number of left & right ()'s are
47926f60 8701 equal, so this loop will not be infinite. */
24eab124
AM		 8702 do
8703 {
8704 base_string--;
8705 if (*base_string == ')')
8706 parens_balanced++;
8707 if (*base_string == '(')
8708 parens_balanced--;
8709 }
8710 while (parens_balanced);
c3332e24 8711
af6bdddf 8712 temp_string = base_string;
c3332e24 8713
24eab124 8714 /* Skip past '(' and whitespace. */
252b5132
RH		 8715 ++base_string;
8716 if (is_space_char (*base_string))
24eab124 8717 ++base_string;
252b5132 8718
af6bdddf 8719 if (*base_string == ','
4eed87de
AM		 8720 || ((i.base_reg = parse_register (base_string, &end_op))
8721 != NULL))
252b5132 8722 {
af6bdddf 8723 displacement_string_end = temp_string;
252b5132 8724
40fb9820 8725 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8726
af6bdddf 8727 if (i.base_reg)
24eab124 8728 {
24eab124
AM		 8729 base_string = end_op;
8730 if (is_space_char (*base_string))
8731 ++base_string;
af6bdddf
AM		 8732 }
8733
8734 /* There may be an index reg or scale factor here. */
8735 if (*base_string == ',')
8736 {
8737 ++base_string;
8738 if (is_space_char (*base_string))
8739 ++base_string;
8740
4eed87de
AM		 8741 if ((i.index_reg = parse_register (base_string, &end_op))
8742 != NULL)
24eab124 8743 {
af6bdddf 8744 base_string = end_op;
24eab124
AM		 8745 if (is_space_char (*base_string))
8746 ++base_string;
af6bdddf
AM		 8747 if (*base_string == ',')
8748 {
8749 ++base_string;
8750 if (is_space_char (*base_string))
8751 ++base_string;
8752 }
e5cb08ac 8753 else if (*base_string != ')')
af6bdddf 8754 {
4eed87de
AM		 8755 as_bad (_("expecting `,' or `)' "
8756 "after index register in `%s'"),
af6bdddf
AM		 8757 operand_string);
8758 return 0;
8759 }
24eab124 8760 }
af6bdddf 8761 else if (*base_string == REGISTER_PREFIX)
24eab124 8762 {
f76bf5e0
L		 8763 end_op = strchr (base_string, ',');
8764 if (end_op)
8765 *end_op = '\0';
af6bdddf 8766 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8767 return 0;
8768 }
252b5132 8769
47926f60 8770 /* Check for scale factor. */
551c1ca1 8771 if (*base_string != ')')
af6bdddf 8772 {
551c1ca1
AM		 8773 char *end_scale = i386_scale (base_string);
8774
8775 if (!end_scale)
af6bdddf 8776 return 0;
24eab124 8777
551c1ca1 8778 base_string = end_scale;
af6bdddf
AM		 8779 if (is_space_char (*base_string))
8780 ++base_string;
8781 if (*base_string != ')')
8782 {
4eed87de
AM		 8783 as_bad (_("expecting `)' "
8784 "after scale factor in `%s'"),
af6bdddf
AM		 8785 operand_string);
8786 return 0;
8787 }
8788 }
8789 else if (!i.index_reg)
24eab124 8790 {
4eed87de
AM		 8791 as_bad (_("expecting index register or scale factor "
8792 "after `,'; got '%c'"),
af6bdddf 8793 *base_string);
24eab124
AM		 8794 return 0;
8795 }
8796 }
af6bdddf 8797 else if (*base_string != ')')
24eab124 8798 {
4eed87de
AM		 8799 as_bad (_("expecting `,' or `)' "
8800 "after base register in `%s'"),
af6bdddf 8801 operand_string);
24eab124
AM		 8802 return 0;
8803 }
c3332e24 8804 }
af6bdddf 8805 else if (*base_string == REGISTER_PREFIX)
c3332e24 8806 {
f76bf5e0
L		 8807 end_op = strchr (base_string, ',');
8808 if (end_op)
8809 *end_op = '\0';
af6bdddf 8810 as_bad (_("bad register name `%s'"), base_string);
24eab124 8811 return 0;
c3332e24 8812 }
24eab124
AM		 8813 }
8814
8815 /* If there's an expression beginning the operand, parse it,
8816 assuming displacement_string_start and
8817 displacement_string_end are meaningful. */
8818 if (displacement_string_start != displacement_string_end)
8819 {
8820 if (!i386_displacement (displacement_string_start,
8821 displacement_string_end))
8822 return 0;
8823 }
8824
8825 /* Special case for (%dx) while doing input/output op. */
8826 if (i.base_reg
0dfbf9d7
L		 8827 && operand_type_equal (&i.base_reg->reg_type,
8828 &reg16_inoutportreg)
24eab124
AM		 8829 && i.index_reg == 0
8830 && i.log2_scale_factor == 0
8831 && i.seg[i.mem_operands] == 0
40fb9820 8832 && !operand_type_check (i.types[this_operand], disp))
24eab124 8833 {
65da13b5 8834 i.types[this_operand] = inoutportreg;
24eab124
AM		 8835 return 1;
8836 }
8837
eecb386c
AM		 8838 if (i386_index_check (operand_string) == 0)
8839 return 0;
5c07affc 8840 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8841 i.mem_operands++;
8842 }
8843 else
ce8a8b2f
AM		 8844 {
8845 /* It's not a memory operand; argh! */
24eab124
AM		 8846 as_bad (_("invalid char %s beginning operand %d `%s'"),
8847 output_invalid (*op_string),
8848 this_operand + 1,
8849 op_string);
8850 return 0;
8851 }
47926f60 8852 return 1; /* Normal return. */
252b5132
RH		 8853}
8854\f
fa94de6b
RM		 8855/* Calculate the maximum variable size (i.e., excluding fr_fix)
8856 that an rs_machine_dependent frag may reach. */
8857
8858unsigned int
8859i386_frag_max_var (fragS *frag)
8860{
8861 /* The only relaxable frags are for jumps.
8862 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8863 gas_assert (frag->fr_type == rs_machine_dependent);
8864 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8865}
8866
ee7fcc42
AM		 8867/* md_estimate_size_before_relax()
8868
8869 Called just before relax() for rs_machine_dependent frags. The x86
8870 assembler uses these frags to handle variable size jump
8871 instructions.
8872
8873 Any symbol that is now undefined will not become defined.
8874 Return the correct fr_subtype in the frag.
8875 Return the initial "guess for variable size of frag" to caller.
8876 The guess is actually the growth beyond the fixed part. Whatever
8877 we do to grow the fixed or variable part contributes to our
8878 returned value. */
8879
252b5132 8880int
7016a5d5 8881md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8882{
252b5132 8883 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8884 check for un-relaxable symbols. On an ELF system, we can't relax
8885 an externally visible symbol, because it may be overridden by a
8886 shared library. */
8887 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8888#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8889 || (IS_ELF
31312f95 8890 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 8891 || S_IS_WEAK (fragP->fr_symbol)
8892 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
8893 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 8894#endif
8895#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8896 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8897 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8898#endif
8899 )
252b5132 8900 {
b98ef147
AM		 8901 /* Symbol is undefined in this segment, or we need to keep a
8902 reloc so that weak symbols can be overridden. */
8903 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8904 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8905 unsigned char *opcode;
8906 int old_fr_fix;
f6af82bd 8907
ee7fcc42 8908 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8909 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8910 else if (size == 2)
f6af82bd
AM		 8911 reloc_type = BFD_RELOC_16_PCREL;
8912 else
8913 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8914
ee7fcc42
AM		 8915 old_fr_fix = fragP->fr_fix;
8916 opcode = (unsigned char *) fragP->fr_opcode;
8917
fddf5b5b 8918 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8919 {
fddf5b5b
AM		 8920 case UNCOND_JUMP:
8921 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8922 opcode[0] = 0xe9;
252b5132 8923 fragP->fr_fix += size;
062cd5e7
AS		 8924 fix_new (fragP, old_fr_fix, size,
8925 fragP->fr_symbol,
8926 fragP->fr_offset, 1,
8927 reloc_type);
252b5132
RH		 8928 break;
8929
fddf5b5b 8930 case COND_JUMP86:
412167cb
AM		 8931 if (size == 2
8932 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8933 {
8934 /* Negate the condition, and branch past an
8935 unconditional jump. */
8936 opcode[0] ^= 1;
8937 opcode[1] = 3;
8938 /* Insert an unconditional jump. */
8939 opcode[2] = 0xe9;
8940 /* We added two extra opcode bytes, and have a two byte
8941 offset. */
8942 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8943 fix_new (fragP, old_fr_fix + 2, 2,
8944 fragP->fr_symbol,
8945 fragP->fr_offset, 1,
8946 reloc_type);
fddf5b5b
AM		 8947 break;
8948 }
8949 /* Fall through. */
8950
8951 case COND_JUMP:
412167cb
AM		 8952 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8953 {
3e02c1cc
AM		 8954 fixS *fixP;
8955
412167cb 8956 fragP->fr_fix += 1;
3e02c1cc
AM		 8957 fixP = fix_new (fragP, old_fr_fix, 1,
8958 fragP->fr_symbol,
8959 fragP->fr_offset, 1,
8960 BFD_RELOC_8_PCREL);
8961 fixP->fx_signed = 1;
412167cb
AM		 8962 break;
8963 }
93c2a809 8964
24eab124 8965 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8966 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8967 opcode[1] = opcode[0] + 0x10;
f6af82bd 8968 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8969 /* We've added an opcode byte. */
8970 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8971 fix_new (fragP, old_fr_fix + 1, size,
8972 fragP->fr_symbol,
8973 fragP->fr_offset, 1,
8974 reloc_type);
252b5132 8975 break;
fddf5b5b
AM		 8976
8977 default:
8978 BAD_CASE (fragP->fr_subtype);
8979 break;
252b5132
RH		 8980 }
8981 frag_wane (fragP);
ee7fcc42 8982 return fragP->fr_fix - old_fr_fix;
252b5132 8983 }
93c2a809 8984
93c2a809
AM		 8985 /* Guess size depending on current relax state. Initially the relax
8986 state will correspond to a short jump and we return 1, because
8987 the variable part of the frag (the branch offset) is one byte
8988 long. However, we can relax a section more than once and in that
8989 case we must either set fr_subtype back to the unrelaxed state,
8990 or return the value for the appropriate branch. */
8991 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 8992}
8993
47926f60
KH		 8994/* Called after relax() is finished.
8995
8996 In: Address of frag.
8997 fr_type == rs_machine_dependent.
8998 fr_subtype is what the address relaxed to.
8999
9000 Out: Any fixSs and constants are set up.
9001 Caller will turn frag into a ".space 0". */
9002
252b5132 9003void
7016a5d5
TG		 9004md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9005 fragS *fragP)
252b5132 9006{
29b0f896 9007 unsigned char *opcode;
252b5132 9008 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9009 offsetT target_address;
9010 offsetT opcode_address;
252b5132 9011 unsigned int extension = 0;
847f7ad4 9012 offsetT displacement_from_opcode_start;
252b5132
RH		 9013
9014 opcode = (unsigned char *) fragP->fr_opcode;
9015
47926f60 9016 /* Address we want to reach in file space. */
252b5132 9017 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9018
47926f60 9019 /* Address opcode resides at in file space. */
252b5132
RH		 9020 opcode_address = fragP->fr_address + fragP->fr_fix;
9021
47926f60 9022 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9023 displacement_from_opcode_start = target_address - opcode_address;
9024
fddf5b5b 9025 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9026 {
47926f60
KH		 9027 /* Don't have to change opcode. */
9028 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9029 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9030 }
9031 else
9032 {
9033 if (no_cond_jump_promotion
9034 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9035 as_warn_where (fragP->fr_file, fragP->fr_line,
9036 _("long jump required"));
252b5132 9037
fddf5b5b
AM		 9038 switch (fragP->fr_subtype)
9039 {
9040 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9041 extension = 4; /* 1 opcode + 4 displacement */
9042 opcode[0] = 0xe9;
9043 where_to_put_displacement = &opcode[1];
9044 break;
252b5132 9045
fddf5b5b
AM		 9046 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9047 extension = 2; /* 1 opcode + 2 displacement */
9048 opcode[0] = 0xe9;
9049 where_to_put_displacement = &opcode[1];
9050 break;
252b5132 9051
fddf5b5b
AM		 9052 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9053 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9054 extension = 5; /* 2 opcode + 4 displacement */
9055 opcode[1] = opcode[0] + 0x10;
9056 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9057 where_to_put_displacement = &opcode[2];
9058 break;
252b5132 9059
fddf5b5b
AM		 9060 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9061 extension = 3; /* 2 opcode + 2 displacement */
9062 opcode[1] = opcode[0] + 0x10;
9063 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9064 where_to_put_displacement = &opcode[2];
9065 break;
252b5132 9066
fddf5b5b
AM		 9067 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9068 extension = 4;
9069 opcode[0] ^= 1;
9070 opcode[1] = 3;
9071 opcode[2] = 0xe9;
9072 where_to_put_displacement = &opcode[3];
9073 break;
9074
9075 default:
9076 BAD_CASE (fragP->fr_subtype);
9077 break;
9078 }
252b5132 9079 }
fddf5b5b 9080
7b81dfbb
AJ		 9081 /* If size if less then four we are sure that the operand fits,
9082 but if it's 4, then it could be that the displacement is larger
9083 then -/+ 2GB. */
9084 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9085 && object_64bit
9086 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9087 + ((addressT) 1 << 31))
9088 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9089 {
9090 as_bad_where (fragP->fr_file, fragP->fr_line,
9091 _("jump target out of range"));
9092 /* Make us emit 0. */
9093 displacement_from_opcode_start = extension;
9094 }
47926f60 9095 /* Now put displacement after opcode. */
252b5132
RH		 9096 md_number_to_chars ((char *) where_to_put_displacement,
9097 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9098 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9099 fragP->fr_fix += extension;
9100}
9101\f
7016a5d5 9102/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9103 by our caller that we have all the info we need to fix it up.
9104
7016a5d5
TG		 9105 Parameter valP is the pointer to the value of the bits.
9106
252b5132
RH		 9107 On the 386, immediates, displacements, and data pointers are all in
9108 the same (little-endian) format, so we don't need to care about which
9109 we are handling. */
9110
94f592af 9111void
7016a5d5 9112md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9113{
94f592af 9114 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9115 valueT value = *valP;
252b5132 9116
f86103b7 9117#if !defined (TE_Mach)
93382f6d
AM		 9118 if (fixP->fx_pcrel)
9119 {
9120 switch (fixP->fx_r_type)
9121 {
5865bb77
ILT		 9122 default:
9123 break;
9124
d6ab8113
JB		 9125 case BFD_RELOC_64:
9126 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9127 break;
93382f6d 9128 case BFD_RELOC_32:
ae8887b5 9129 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9130 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9131 break;
9132 case BFD_RELOC_16:
9133 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9134 break;
9135 case BFD_RELOC_8:
9136 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9137 break;
9138 }
9139 }
252b5132 9140
a161fe53 9141 if (fixP->fx_addsy != NULL
31312f95 9142 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9143 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9144 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9145 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9146 && !use_rela_relocations)
252b5132 9147 {
31312f95
AM		 9148 /* This is a hack. There should be a better way to handle this.
9149 This covers for the fact that bfd_install_relocation will
9150 subtract the current location (for partial_inplace, PC relative
9151 relocations); see more below. */
252b5132 9152#ifndef OBJ_AOUT
718ddfc0 9153 if (IS_ELF
252b5132
RH		 9154#ifdef TE_PE
9155 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9156#endif
9157 )
9158 value += fixP->fx_where + fixP->fx_frag->fr_address;
9159#endif
9160#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9161 if (IS_ELF)
252b5132 9162 {
6539b54b 9163 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9164
6539b54b 9165 if ((sym_seg == seg
2f66722d 9166 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9167 && sym_seg != absolute_section))
af65af87 9168 && !generic_force_reloc (fixP))
2f66722d
AM		 9169 {
9170 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9171 bfd_install_relocation subtracts them out again. I think
9172 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9173 it. FIXME. */
9174 value += fixP->fx_where + fixP->fx_frag->fr_address;
9175 }
252b5132
RH		 9176 }
9177#endif
9178#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9179 /* For some reason, the PE format does not store a
9180 section address offset for a PC relative symbol. */
9181 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9182 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9183 value += md_pcrel_from (fixP);
9184#endif
9185 }
fbeb56a4 9186#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9187 if (fixP->fx_addsy != NULL
9188 && S_IS_WEAK (fixP->fx_addsy)
9189 /* PR 16858: Do not modify weak function references. */
9190 && ! fixP->fx_pcrel)
fbeb56a4 9191 {
296a8689
NC		 9192#if !defined (TE_PEP)
9193 /* For x86 PE weak function symbols are neither PC-relative
9194 nor do they set S_IS_FUNCTION. So the only reliable way
9195 to detect them is to check the flags of their containing
9196 section. */
9197 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9198 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9199 ;
9200 else
9201#endif
fbeb56a4
DK		 9202 value -= S_GET_VALUE (fixP->fx_addsy);
9203 }
9204#endif
252b5132
RH		 9205
9206 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9207 and we must not disappoint it. */
252b5132 9208#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9209 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9210 switch (fixP->fx_r_type)
9211 {
9212 case BFD_RELOC_386_PLT32:
3e73aa7c 9213 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9214 /* Make the jump instruction point to the address of the operand. At
9215 runtime we merely add the offset to the actual PLT entry. */
9216 value = -4;
9217 break;
31312f95 9218
13ae64f3
JJ		 9219 case BFD_RELOC_386_TLS_GD:
9220 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9221 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9222 case BFD_RELOC_386_TLS_IE:
9223 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9224 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9225 case BFD_RELOC_X86_64_TLSGD:
9226 case BFD_RELOC_X86_64_TLSLD:
9227 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9228 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9229 value = 0; /* Fully resolved at runtime. No addend. */
9230 /* Fallthrough */
9231 case BFD_RELOC_386_TLS_LE:
9232 case BFD_RELOC_386_TLS_LDO_32:
9233 case BFD_RELOC_386_TLS_LE_32:
9234 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9235 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9236 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9237 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9238 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9239 break;
9240
67a4f2b7
AO		 9241 case BFD_RELOC_386_TLS_DESC_CALL:
9242 case BFD_RELOC_X86_64_TLSDESC_CALL:
9243 value = 0; /* Fully resolved at runtime. No addend. */
9244 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9245 fixP->fx_done = 0;
9246 return;
9247
00f7efb6
JJ		 9248 case BFD_RELOC_386_GOT32:
9249 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9250 value = 0; /* Fully resolved at runtime. No addend. */
9251 break;
47926f60
KH		 9252
9253 case BFD_RELOC_VTABLE_INHERIT:
9254 case BFD_RELOC_VTABLE_ENTRY:
9255 fixP->fx_done = 0;
94f592af 9256 return;
47926f60
KH		 9257
9258 default:
9259 break;
9260 }
9261#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9262 *valP = value;
f86103b7 9263#endif /* !defined (TE_Mach) */
3e73aa7c 9264
3e73aa7c 9265 /* Are we finished with this relocation now? */
c6682705 9266 if (fixP->fx_addsy == NULL)
3e73aa7c 9267 fixP->fx_done = 1;
fbeb56a4
DK		 9268#if defined (OBJ_COFF) && defined (TE_PE)
9269 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9270 {
9271 fixP->fx_done = 0;
9272 /* Remember value for tc_gen_reloc. */
9273 fixP->fx_addnumber = value;
9274 /* Clear out the frag for now. */
9275 value = 0;
9276 }
9277#endif
3e73aa7c
JH		 9278 else if (use_rela_relocations)
9279 {
9280 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9281 /* Remember value for tc_gen_reloc. */
9282 fixP->fx_addnumber = value;
3e73aa7c
JH		 9283 value = 0;
9284 }
f86103b7 9285
94f592af 9286 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9287}
252b5132 9288\f
252b5132 9289char *
499ac353 9290md_atof (int type, char *litP, int *sizeP)
252b5132 9291{
499ac353
NC		 9292 /* This outputs the LITTLENUMs in REVERSE order;
9293 in accord with the bigendian 386. */
9294 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9295}
9296\f
2d545b82 9297static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9298
252b5132 9299static char *
e3bb37b5 9300output_invalid (int c)
252b5132 9301{
3882b010 9302 if (ISPRINT (c))
f9f21a03
L		 9303 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9304 "'%c'", c);
252b5132 9305 else
f9f21a03 9306 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9307 "(0x%x)", (unsigned char) c);
252b5132
RH		 9308 return output_invalid_buf;
9309}
9310
af6bdddf 9311/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9312
9313static const reg_entry *
4d1bb795 9314parse_real_register (char *reg_string, char **end_op)
252b5132 9315{
af6bdddf
AM		 9316 char *s = reg_string;
9317 char *p;
252b5132
RH		 9318 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9319 const reg_entry *r;
9320
9321 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9322 if (*s == REGISTER_PREFIX)
9323 ++s;
9324
9325 if (is_space_char (*s))
9326 ++s;
9327
9328 p = reg_name_given;
af6bdddf 9329 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9330 {
9331 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9332 return (const reg_entry *) NULL;
9333 s++;
252b5132
RH		 9334 }
9335
6588847e
DN		 9336 /* For naked regs, make sure that we are not dealing with an identifier.
9337 This prevents confusing an identifier like `eax_var' with register
9338 `eax'. */
9339 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9340 return (const reg_entry *) NULL;
9341
af6bdddf 9342 *end_op = s;
252b5132
RH		 9343
9344 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9345
5f47d35b 9346 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9347 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9348 {
5f47d35b
AM		 9349 if (is_space_char (*s))
9350 ++s;
9351 if (*s == '(')
9352 {
af6bdddf 9353 ++s;
5f47d35b
AM		 9354 if (is_space_char (*s))
9355 ++s;
9356 if (*s >= '0' && *s <= '7')
9357 {
db557034 9358 int fpr = *s - '0';
af6bdddf 9359 ++s;
5f47d35b
AM		 9360 if (is_space_char (*s))
9361 ++s;
9362 if (*s == ')')
9363 {
9364 *end_op = s + 1;
1e9cc1c2 9365 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9366 know (r);
9367 return r + fpr;
5f47d35b 9368 }
5f47d35b 9369 }
47926f60 9370 /* We have "%st(" then garbage. */
5f47d35b
AM		 9371 return (const reg_entry *) NULL;
9372 }
9373 }
9374
a60de03c
JB		 9375 if (r == NULL || allow_pseudo_reg)
9376 return r;
9377
0dfbf9d7 9378 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9379 return (const reg_entry *) NULL;
9380
192dc9c6
JB		 9381 if ((r->reg_type.bitfield.reg32
9382 || r->reg_type.bitfield.sreg3
9383 || r->reg_type.bitfield.control
9384 || r->reg_type.bitfield.debug
9385 || r->reg_type.bitfield.test)
9386 && !cpu_arch_flags.bitfield.cpui386)
9387 return (const reg_entry *) NULL;
9388
309d3373
JB		 9389 if (r->reg_type.bitfield.floatreg
9390 && !cpu_arch_flags.bitfield.cpu8087
9391 && !cpu_arch_flags.bitfield.cpu287
9392 && !cpu_arch_flags.bitfield.cpu387)
9393 return (const reg_entry *) NULL;
9394
192dc9c6
JB		 9395 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9396 return (const reg_entry *) NULL;
9397
9398 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9399 return (const reg_entry *) NULL;
9400
40f12533
L		 9401 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9402 return (const reg_entry *) NULL;
9403
43234a1e
L		 9404 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9405 && !cpu_arch_flags.bitfield.cpuavx512f)
9406 return (const reg_entry *) NULL;
9407
db51cc60 9408 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9409 if (!allow_index_reg
db51cc60
L		 9410 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9411 return (const reg_entry *) NULL;
9412
43234a1e
L		 9413 /* Upper 16 vector register is only available with VREX in 64bit
9414 mode. */
9415 if ((r->reg_flags & RegVRex))
9416 {
9417 if (!cpu_arch_flags.bitfield.cpuvrex
9418 || flag_code != CODE_64BIT)
9419 return (const reg_entry *) NULL;
9420
9421 i.need_vrex = 1;
9422 }
9423
a60de03c
JB		 9424 if (((r->reg_flags & (RegRex64 | RegRex))
9425 || r->reg_type.bitfield.reg64)
40fb9820 9426 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9427 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9428 && flag_code != CODE_64BIT)
20f0a1fc 9429 return (const reg_entry *) NULL;
1ae00879 9430
b7240065
JB		 9431 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9432 return (const reg_entry *) NULL;
9433
252b5132
RH		 9434 return r;
9435}
4d1bb795
JB		 9436
9437/* REG_STRING starts *before* REGISTER_PREFIX. */
9438
9439static const reg_entry *
9440parse_register (char *reg_string, char **end_op)
9441{
9442 const reg_entry *r;
9443
9444 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9445 r = parse_real_register (reg_string, end_op);
9446 else
9447 r = NULL;
9448 if (!r)
9449 {
9450 char *save = input_line_pointer;
9451 char c;
9452 symbolS *symbolP;
9453
9454 input_line_pointer = reg_string;
9455 c = get_symbol_end ();
9456 symbolP = symbol_find (reg_string);
9457 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9458 {
9459 const expressionS *e = symbol_get_value_expression (symbolP);
9460
0398aac5 9461 know (e->X_op == O_register);
4eed87de 9462 know (e->X_add_number >= 0
c3fe08fa 9463 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9464 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9465 if ((r->reg_flags & RegVRex))
9466 i.need_vrex = 1;
4d1bb795
JB		 9467 *end_op = input_line_pointer;
9468 }
9469 *input_line_pointer = c;
9470 input_line_pointer = save;
9471 }
9472 return r;
9473}
9474
9475int
9476i386_parse_name (char *name, expressionS *e, char *nextcharP)
9477{
9478 const reg_entry *r;
9479 char *end = input_line_pointer;
9480
9481 *end = *nextcharP;
9482 r = parse_register (name, &input_line_pointer);
9483 if (r && end <= input_line_pointer)
9484 {
9485 *nextcharP = *input_line_pointer;
9486 *input_line_pointer = 0;
9487 e->X_op = O_register;
9488 e->X_add_number = r - i386_regtab;
9489 return 1;
9490 }
9491 input_line_pointer = end;
9492 *end = 0;
ee86248c 9493 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9494}
9495
9496void
9497md_operand (expressionS *e)
9498{
ee86248c
JB		 9499 char *end;
9500 const reg_entry *r;
4d1bb795 9501
ee86248c
JB		 9502 switch (*input_line_pointer)
9503 {
9504 case REGISTER_PREFIX:
9505 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9506 if (r)
9507 {
9508 e->X_op = O_register;
9509 e->X_add_number = r - i386_regtab;
9510 input_line_pointer = end;
9511 }
ee86248c
JB		 9512 break;
9513
9514 case '[':
9c2799c2 9515 gas_assert (intel_syntax);
ee86248c
JB		 9516 end = input_line_pointer++;
9517 expression (e);
9518 if (*input_line_pointer == ']')
9519 {
9520 ++input_line_pointer;
9521 e->X_op_symbol = make_expr_symbol (e);
9522 e->X_add_symbol = NULL;
9523 e->X_add_number = 0;
9524 e->X_op = O_index;
9525 }
9526 else
9527 {
9528 e->X_op = O_absent;
9529 input_line_pointer = end;
9530 }
9531 break;
4d1bb795
JB		 9532 }
9533}
9534
252b5132 9535\f
4cc782b5 9536#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9537const char *md_shortopts = "kVQ:sqn";
252b5132 9538#else
12b55ccc 9539const char *md_shortopts = "qn";
252b5132 9540#endif
6e0b89ee 9541
3e73aa7c 9542#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9543#define OPTION_64 (OPTION_MD_BASE + 1)
9544#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9545#define OPTION_MARCH (OPTION_MD_BASE + 3)
9546#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9547#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9548#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9549#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9550#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9551#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9552#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9553#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9554#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9555#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9556#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9557#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9558#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9559#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9560#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
a5094208 9561#define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9562#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
b3b91714 9563
99ad8390
NC		 9564struct option md_longopts[] =
9565{
3e73aa7c 9566 {"32", no_argument, NULL, OPTION_32},
321098a5 9567#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9568 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9569 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9570#endif
9571#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9572 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 9573#endif
b3b91714 9574 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9575 {"march", required_argument, NULL, OPTION_MARCH},
9576 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9577 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9578 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9579 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9580 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9581 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9582 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9583 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9584 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9585 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9586 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9587 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9588 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9589# if defined (TE_PE) || defined (TE_PEP)
9590 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9591#endif
a5094208 9592 {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX},
d3d3c6db 9593 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
252b5132
RH		 9594 {NULL, no_argument, NULL, 0}
9595};
9596size_t md_longopts_size = sizeof (md_longopts);
9597
9598int
9103f4f4 9599md_parse_option (int c, char *arg)
252b5132 9600{
91d6fa6a 9601 unsigned int j;
6305a203 9602 char *arch, *next;
9103f4f4 9603
252b5132
RH		 9604 switch (c)
9605 {
12b55ccc
L		 9606 case 'n':
9607 optimize_align_code = 0;
9608 break;
9609
a38cf1db
AM		 9610 case 'q':
9611 quiet_warnings = 1;
252b5132
RH		 9612 break;
9613
9614#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9615 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9616 should be emitted or not. FIXME: Not implemented. */
9617 case 'Q':
252b5132
RH		 9618 break;
9619
9620 /* -V: SVR4 argument to print version ID. */
9621 case 'V':
9622 print_version_id ();
9623 break;
9624
a38cf1db
AM		 9625 /* -k: Ignore for FreeBSD compatibility. */
9626 case 'k':
252b5132 9627 break;
4cc782b5
ILT		 9628
9629 case 's':
9630 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9631 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9632 break;
99ad8390 9633#endif
321098a5 9634#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9635 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9636 case OPTION_64:
9637 {
9638 const char **list, **l;
9639
3e73aa7c
JH		 9640 list = bfd_target_list ();
9641 for (l = list; *l != NULL; l++)
8620418b 9642 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9643 || strcmp (*l, "coff-x86-64") == 0
9644 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9645 || strcmp (*l, "pei-x86-64") == 0
9646 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9647 {
9648 default_arch = "x86_64";
9649 break;
9650 }
3e73aa7c 9651 if (*l == NULL)
2b5d6a91 9652 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9653 free (list);
9654 }
9655 break;
9656#endif
252b5132 9657
351f65ca 9658#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9659 case OPTION_X32:
351f65ca
L		 9660 if (IS_ELF)
9661 {
9662 const char **list, **l;
9663
9664 list = bfd_target_list ();
9665 for (l = list; *l != NULL; l++)
9666 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9667 {
9668 default_arch = "x86_64:32";
9669 break;
9670 }
9671 if (*l == NULL)
2b5d6a91 9672 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9673 free (list);
9674 }
9675 else
9676 as_fatal (_("32bit x86_64 is only supported for ELF"));
9677 break;
9678#endif
9679
6e0b89ee
AM		 9680 case OPTION_32:
9681 default_arch = "i386";
9682 break;
9683
b3b91714
AM		 9684 case OPTION_DIVIDE:
9685#ifdef SVR4_COMMENT_CHARS
9686 {
9687 char *n, *t;
9688 const char *s;
9689
9690 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9691 t = n;
9692 for (s = i386_comment_chars; *s != '\0'; s++)
9693 if (*s != '/')
9694 *t++ = *s;
9695 *t = '\0';
9696 i386_comment_chars = n;
9697 }
9698#endif
9699 break;
9700
9103f4f4 9701 case OPTION_MARCH:
6305a203
L		 9702 arch = xstrdup (arg);
9703 do
9103f4f4 9704 {
6305a203 9705 if (*arch == '.')
2b5d6a91 9706 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9707 next = strchr (arch, '+');
9708 if (next)
9709 *next++ = '\0';
91d6fa6a 9710 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9711 {
91d6fa6a 9712 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9713 {
6305a203 9714 /* Processor. */
1ded5609
JB		 9715 if (! cpu_arch[j].flags.bitfield.cpui386)
9716 continue;
9717
91d6fa6a 9718 cpu_arch_name = cpu_arch[j].name;
6305a203 9719 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9720 cpu_arch_flags = cpu_arch[j].flags;
9721 cpu_arch_isa = cpu_arch[j].type;
9722 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9723 if (!cpu_arch_tune_set)
9724 {
9725 cpu_arch_tune = cpu_arch_isa;
9726 cpu_arch_tune_flags = cpu_arch_isa_flags;
9727 }
9728 break;
9729 }
91d6fa6a
NC		 9730 else if (*cpu_arch [j].name == '.'
9731 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9732 {
9733 /* ISA entension. */
9734 i386_cpu_flags flags;
309d3373 9735
49021df2 9736 if (!cpu_arch[j].negated)
309d3373 9737 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9738 cpu_arch[j].flags);
309d3373
JB		 9739 else
9740 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9741 cpu_arch[j].flags);
0dfbf9d7 9742 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9743 {
9744 if (cpu_sub_arch_name)
9745 {
9746 char *name = cpu_sub_arch_name;
9747 cpu_sub_arch_name = concat (name,
91d6fa6a 9748 cpu_arch[j].name,
1bf57e9f 9749 (const char *) NULL);
6305a203
L		 9750 free (name);
9751 }
9752 else
91d6fa6a 9753 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9754 cpu_arch_flags = flags;
a586129e 9755 cpu_arch_isa_flags = flags;
6305a203
L		 9756 }
9757 break;
ccc9c027 9758 }
9103f4f4 9759 }
6305a203 9760
91d6fa6a 9761 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9762 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9763
9764 arch = next;
9103f4f4 9765 }
6305a203 9766 while (next != NULL );
9103f4f4
L		 9767 break;
9768
9769 case OPTION_MTUNE:
9770 if (*arg == '.')
2b5d6a91 9771 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9772 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9773 {
91d6fa6a 9774 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9775 {
ccc9c027 9776 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9777 cpu_arch_tune = cpu_arch [j].type;
9778 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9779 break;
9780 }
9781 }
91d6fa6a 9782 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9783 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9784 break;
9785
1efbbeb4
L		 9786 case OPTION_MMNEMONIC:
9787 if (strcasecmp (arg, "att") == 0)
9788 intel_mnemonic = 0;
9789 else if (strcasecmp (arg, "intel") == 0)
9790 intel_mnemonic = 1;
9791 else
2b5d6a91 9792 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9793 break;
9794
9795 case OPTION_MSYNTAX:
9796 if (strcasecmp (arg, "att") == 0)
9797 intel_syntax = 0;
9798 else if (strcasecmp (arg, "intel") == 0)
9799 intel_syntax = 1;
9800 else
2b5d6a91 9801 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9802 break;
9803
9804 case OPTION_MINDEX_REG:
9805 allow_index_reg = 1;
9806 break;
9807
9808 case OPTION_MNAKED_REG:
9809 allow_naked_reg = 1;
9810 break;
9811
9812 case OPTION_MOLD_GCC:
9813 old_gcc = 1;
1efbbeb4
L		 9814 break;
9815
c0f3af97
L		 9816 case OPTION_MSSE2AVX:
9817 sse2avx = 1;
9818 break;
9819
daf50ae7
L		 9820 case OPTION_MSSE_CHECK:
9821 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9822 sse_check = check_error;
daf50ae7 9823 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9824 sse_check = check_warning;
daf50ae7 9825 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9826 sse_check = check_none;
daf50ae7 9827 else
2b5d6a91 9828 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9829 break;
9830
7bab8ab5
JB		 9831 case OPTION_MOPERAND_CHECK:
9832 if (strcasecmp (arg, "error") == 0)
9833 operand_check = check_error;
9834 else if (strcasecmp (arg, "warning") == 0)
9835 operand_check = check_warning;
9836 else if (strcasecmp (arg, "none") == 0)
9837 operand_check = check_none;
9838 else
9839 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9840 break;
9841
539f890d
L		 9842 case OPTION_MAVXSCALAR:
9843 if (strcasecmp (arg, "128") == 0)
9844 avxscalar = vex128;
9845 else if (strcasecmp (arg, "256") == 0)
9846 avxscalar = vex256;
9847 else
2b5d6a91 9848 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9849 break;
9850
7e8b059b
L		 9851 case OPTION_MADD_BND_PREFIX:
9852 add_bnd_prefix = 1;
9853 break;
9854
43234a1e
L		 9855 case OPTION_MEVEXLIG:
9856 if (strcmp (arg, "128") == 0)
9857 evexlig = evexl128;
9858 else if (strcmp (arg, "256") == 0)
9859 evexlig = evexl256;
9860 else if (strcmp (arg, "512") == 0)
9861 evexlig = evexl512;
9862 else
9863 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9864 break;
9865
d3d3c6db
IT		 9866 case OPTION_MEVEXRCIG:
9867 if (strcmp (arg, "rne") == 0)
9868 evexrcig = rne;
9869 else if (strcmp (arg, "rd") == 0)
9870 evexrcig = rd;
9871 else if (strcmp (arg, "ru") == 0)
9872 evexrcig = ru;
9873 else if (strcmp (arg, "rz") == 0)
9874 evexrcig = rz;
9875 else
9876 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
9877 break;
9878
43234a1e
L		 9879 case OPTION_MEVEXWIG:
9880 if (strcmp (arg, "0") == 0)
9881 evexwig = evexw0;
9882 else if (strcmp (arg, "1") == 0)
9883 evexwig = evexw1;
9884 else
9885 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9886 break;
9887
167ad85b
TG		 9888# if defined (TE_PE) || defined (TE_PEP)
9889 case OPTION_MBIG_OBJ:
9890 use_big_obj = 1;
9891 break;
9892#endif
9893
a5094208 9894 case OPTION_OMIT_LOCK_PREFIX:
d022bddd
IT		 9895 if (strcasecmp (arg, "yes") == 0)
9896 omit_lock_prefix = 1;
9897 else if (strcasecmp (arg, "no") == 0)
9898 omit_lock_prefix = 0;
9899 else
9900 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
9901 break;
9902
252b5132
RH		 9903 default:
9904 return 0;
9905 }
9906 return 1;
9907}
9908
8a2c8fef
L		 9909#define MESSAGE_TEMPLATE \
9910" "
9911
9912static void
1ded5609 9913show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9914{
9915 static char message[] = MESSAGE_TEMPLATE;
9916 char *start = message + 27;
9917 char *p;
9918 int size = sizeof (MESSAGE_TEMPLATE);
9919 int left;
9920 const char *name;
9921 int len;
9922 unsigned int j;
9923
9924 p = start;
9925 left = size - (start - message);
9926 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9927 {
9928 /* Should it be skipped? */
9929 if (cpu_arch [j].skip)
9930 continue;
9931
9932 name = cpu_arch [j].name;
9933 len = cpu_arch [j].len;
9934 if (*name == '.')
9935 {
9936 /* It is an extension. Skip if we aren't asked to show it. */
9937 if (ext)
9938 {
9939 name++;
9940 len--;
9941 }
9942 else
9943 continue;
9944 }
9945 else if (ext)
9946 {
9947 /* It is an processor. Skip if we show only extension. */
9948 continue;
9949 }
1ded5609
JB		 9950 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9951 {
9952 /* It is an impossible processor - skip. */
9953 continue;
9954 }
8a2c8fef
L		 9955
9956 /* Reserve 2 spaces for ", " or ",\0" */
9957 left -= len + 2;
9958
9959 /* Check if there is any room. */
9960 if (left >= 0)
9961 {
9962 if (p != start)
9963 {
9964 *p++ = ',';
9965 *p++ = ' ';
9966 }
9967 p = mempcpy (p, name, len);
9968 }
9969 else
9970 {
9971 /* Output the current message now and start a new one. */
9972 *p++ = ',';
9973 *p = '\0';
9974 fprintf (stream, "%s\n", message);
9975 p = start;
9976 left = size - (start - message) - len - 2;
8d63c93e 9977
8a2c8fef
L		 9978 gas_assert (left >= 0);
9979
9980 p = mempcpy (p, name, len);
9981 }
9982 }
9983
9984 *p = '\0';
9985 fprintf (stream, "%s\n", message);
9986}
9987
252b5132 9988void
8a2c8fef 9989md_show_usage (FILE *stream)
252b5132 9990{
4cc782b5
ILT		 9991#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9992 fprintf (stream, _("\
a38cf1db
AM		 9993 -Q ignored\n\
9994 -V print assembler version number\n\
b3b91714
AM		 9995 -k ignored\n"));
9996#endif
9997 fprintf (stream, _("\
12b55ccc 9998 -n Do not optimize code alignment\n\
b3b91714
AM		 9999 -q quieten some warnings\n"));
10000#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10001 fprintf (stream, _("\
a38cf1db 10002 -s ignored\n"));
b3b91714 10003#endif
321098a5
L		 10004#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10005 || defined (TE_PE) || defined (TE_PEP))
751d281c 10006 fprintf (stream, _("\
570561f7 10007 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10008#endif
b3b91714
AM		 10009#ifdef SVR4_COMMENT_CHARS
10010 fprintf (stream, _("\
10011 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10012#else
10013 fprintf (stream, _("\
b3b91714 10014 --divide ignored\n"));
4cc782b5 10015#endif
9103f4f4 10016 fprintf (stream, _("\
6305a203 10017 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10018 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10019 show_arch (stream, 0, 1);
8a2c8fef
L		 10020 fprintf (stream, _("\
10021 EXTENSION is combination of:\n"));
1ded5609 10022 show_arch (stream, 1, 0);
6305a203 10023 fprintf (stream, _("\
8a2c8fef 10024 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10025 show_arch (stream, 0, 0);
ba104c83 10026 fprintf (stream, _("\
c0f3af97
L		 10027 -msse2avx encode SSE instructions with VEX prefix\n"));
10028 fprintf (stream, _("\
daf50ae7
L		 10029 -msse-check=[none|error|warning]\n\
10030 check SSE instructions\n"));
10031 fprintf (stream, _("\
7bab8ab5
JB		 10032 -moperand-check=[none|error|warning]\n\
10033 check operand combinations for validity\n"));
10034 fprintf (stream, _("\
539f890d
L		 10035 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10036 length\n"));
10037 fprintf (stream, _("\
43234a1e
L		 10038 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10039 length\n"));
10040 fprintf (stream, _("\
10041 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10042 for EVEX.W bit ignored instructions\n"));
10043 fprintf (stream, _("\
d3d3c6db
IT		 10044 -mevexrcig=[rne|rd|ru|rz]\n\
10045 encode EVEX instructions with specific EVEX.RC value\n\
10046 for SAE-only ignored instructions\n"));
10047 fprintf (stream, _("\
ba104c83
L		 10048 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10049 fprintf (stream, _("\
10050 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10051 fprintf (stream, _("\
10052 -mindex-reg support pseudo index registers\n"));
10053 fprintf (stream, _("\
10054 -mnaked-reg don't require `%%' prefix for registers\n"));
10055 fprintf (stream, _("\
10056 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10057 fprintf (stream, _("\
10058 -madd-bnd-prefix add BND prefix for all valid branches\n"));
167ad85b
TG		 10059# if defined (TE_PE) || defined (TE_PEP)
10060 fprintf (stream, _("\
10061 -mbig-obj generate big object files\n"));
10062#endif
d022bddd
IT		 10063 fprintf (stream, _("\
10064 -momit-lock-prefix=[no|yes]\n\
10065 strip all lock prefixes\n"));
252b5132
RH		 10066}
10067
3e73aa7c 10068#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10069 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10070 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10071
10072/* Pick the target format to use. */
10073
47926f60 10074const char *
e3bb37b5 10075i386_target_format (void)
252b5132 10076{
351f65ca
L		 10077 if (!strncmp (default_arch, "x86_64", 6))
10078 {
10079 update_code_flag (CODE_64BIT, 1);
10080 if (default_arch[6] == '\0')
7f56bc95 10081 x86_elf_abi = X86_64_ABI;
351f65ca 10082 else
7f56bc95 10083 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10084 }
3e73aa7c 10085 else if (!strcmp (default_arch, "i386"))
78f12dd3 10086 update_code_flag (CODE_32BIT, 1);
3e73aa7c 10087 else
2b5d6a91 10088 as_fatal (_("unknown architecture"));
89507696
JB		 10089
10090 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10091 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10092 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10093 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10094
252b5132
RH		 10095 switch (OUTPUT_FLAVOR)
10096 {
9384f2ff 10097#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10098 case bfd_target_aout_flavour:
47926f60 10099 return AOUT_TARGET_FORMAT;
4c63da97 10100#endif
9384f2ff
AM		 10101#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10102# if defined (TE_PE) || defined (TE_PEP)
10103 case bfd_target_coff_flavour:
167ad85b
TG		 10104 if (flag_code == CODE_64BIT)
10105 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10106 else
10107 return "pe-i386";
9384f2ff 10108# elif defined (TE_GO32)
0561d57c
JK		 10109 case bfd_target_coff_flavour:
10110 return "coff-go32";
9384f2ff 10111# else
252b5132
RH		 10112 case bfd_target_coff_flavour:
10113 return "coff-i386";
9384f2ff 10114# endif
4c63da97 10115#endif
3e73aa7c 10116#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10117 case bfd_target_elf_flavour:
3e73aa7c 10118 {
351f65ca
L		 10119 const char *format;
10120
10121 switch (x86_elf_abi)
4fa24527 10122 {
351f65ca
L		 10123 default:
10124 format = ELF_TARGET_FORMAT;
10125 break;
7f56bc95 10126 case X86_64_ABI:
351f65ca 10127 use_rela_relocations = 1;
4fa24527 10128 object_64bit = 1;
351f65ca
L		 10129 format = ELF_TARGET_FORMAT64;
10130 break;
7f56bc95 10131 case X86_64_X32_ABI:
4fa24527 10132 use_rela_relocations = 1;
351f65ca 10133 object_64bit = 1;
862be3fb 10134 disallow_64bit_reloc = 1;
351f65ca
L		 10135 format = ELF_TARGET_FORMAT32;
10136 break;
4fa24527 10137 }
3632d14b 10138 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10139 {
7f56bc95 10140 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10141 as_fatal (_("Intel L1OM is 64bit only"));
10142 return ELF_TARGET_L1OM_FORMAT;
10143 }
7a9068fe
L		 10144 if (cpu_arch_isa == PROCESSOR_K1OM)
10145 {
10146 if (x86_elf_abi != X86_64_ABI)
10147 as_fatal (_("Intel K1OM is 64bit only"));
10148 return ELF_TARGET_K1OM_FORMAT;
10149 }
8a9036a4 10150 else
351f65ca 10151 return format;
3e73aa7c 10152 }
e57f8c65
TG		 10153#endif
10154#if defined (OBJ_MACH_O)
10155 case bfd_target_mach_o_flavour:
d382c579
TG		 10156 if (flag_code == CODE_64BIT)
10157 {
10158 use_rela_relocations = 1;
10159 object_64bit = 1;
10160 return "mach-o-x86-64";
10161 }
10162 else
10163 return "mach-o-i386";
4c63da97 10164#endif
252b5132
RH		 10165 default:
10166 abort ();
10167 return NULL;
10168 }
10169}
10170
47926f60 10171#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 10172
10173#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 10174void
10175i386_elf_emit_arch_note (void)
a847613f 10176{
718ddfc0 10177 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 10178 {
10179 char *p;
10180 asection *seg = now_seg;
10181 subsegT subseg = now_subseg;
10182 Elf_Internal_Note i_note;
10183 Elf_External_Note e_note;
10184 asection *note_secp;
10185 int len;
10186
10187 /* Create the .note section. */
10188 note_secp = subseg_new (".note", 0);
10189 bfd_set_section_flags (stdoutput,
10190 note_secp,
10191 SEC_HAS_CONTENTS | SEC_READONLY);
10192
10193 /* Process the arch string. */
10194 len = strlen (cpu_arch_name);
10195
10196 i_note.namesz = len + 1;
10197 i_note.descsz = 0;
10198 i_note.type = NT_ARCH;
10199 p = frag_more (sizeof (e_note.namesz));
10200 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
10201 p = frag_more (sizeof (e_note.descsz));
10202 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
10203 p = frag_more (sizeof (e_note.type));
10204 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
10205 p = frag_more (len + 1);
10206 strcpy (p, cpu_arch_name);
10207
10208 frag_align (2, 0, 0);
10209
10210 subseg_set (seg, subseg);
10211 }
10212}
10213#endif
252b5132 10214\f
252b5132 10215symbolS *
7016a5d5 10216md_undefined_symbol (char *name)
252b5132 10217{
18dc2407
ILT		 10218 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10219 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10220 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10221 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10222 {
10223 if (!GOT_symbol)
10224 {
10225 if (symbol_find (name))
10226 as_bad (_("GOT already in symbol table"));
10227 GOT_symbol = symbol_new (name, undefined_section,
10228 (valueT) 0, &zero_address_frag);
10229 };
10230 return GOT_symbol;
10231 }
252b5132
RH		 10232 return 0;
10233}
10234
10235/* Round up a section size to the appropriate boundary. */
47926f60 10236
252b5132 10237valueT
7016a5d5 10238md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10239{
4c63da97
AM		 10240#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10241 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10242 {
10243 /* For a.out, force the section size to be aligned. If we don't do
10244 this, BFD will align it for us, but it will not write out the
10245 final bytes of the section. This may be a bug in BFD, but it is
10246 easier to fix it here since that is how the other a.out targets
10247 work. */
10248 int align;
10249
10250 align = bfd_get_section_alignment (stdoutput, segment);
10251 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10252 }
252b5132
RH		 10253#endif
10254
10255 return size;
10256}
10257
10258/* On the i386, PC-relative offsets are relative to the start of the
10259 next instruction. That is, the address of the offset, plus its
10260 size, since the offset is always the last part of the insn. */
10261
10262long
e3bb37b5 10263md_pcrel_from (fixS *fixP)
252b5132
RH		 10264{
10265 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10266}
10267
10268#ifndef I386COFF
10269
10270static void
e3bb37b5 10271s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10272{
29b0f896 10273 int temp;
252b5132 10274
8a75718c
JB		 10275#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10276 if (IS_ELF)
10277 obj_elf_section_change_hook ();
10278#endif
252b5132
RH		 10279 temp = get_absolute_expression ();
10280 subseg_set (bss_section, (subsegT) temp);
10281 demand_empty_rest_of_line ();
10282}
10283
10284#endif
10285
252b5132 10286void
e3bb37b5 10287i386_validate_fix (fixS *fixp)
252b5132
RH		 10288{
10289 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10290 {
23df1078
JH		 10291 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10292 {
4fa24527 10293 if (!object_64bit)
23df1078
JH		 10294 abort ();
10295 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10296 }
10297 else
10298 {
4fa24527 10299 if (!object_64bit)
d6ab8113
JB		 10300 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10301 else
10302 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 10303 }
252b5132
RH		 10304 fixp->fx_subsy = 0;
10305 }
10306}
10307
252b5132 10308arelent *
7016a5d5 10309tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10310{
10311 arelent *rel;
10312 bfd_reloc_code_real_type code;
10313
10314 switch (fixp->fx_r_type)
10315 {
8ce3d284 10316#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10317 case BFD_RELOC_SIZE32:
10318 case BFD_RELOC_SIZE64:
10319 if (S_IS_DEFINED (fixp->fx_addsy)
10320 && !S_IS_EXTERNAL (fixp->fx_addsy))
10321 {
10322 /* Resolve size relocation against local symbol to size of
10323 the symbol plus addend. */
10324 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10325 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10326 && !fits_in_unsigned_long (value))
10327 as_bad_where (fixp->fx_file, fixp->fx_line,
10328 _("symbol size computation overflow"));
10329 fixp->fx_addsy = NULL;
10330 fixp->fx_subsy = NULL;
10331 md_apply_fix (fixp, (valueT *) &value, NULL);
10332 return NULL;
10333 }
8ce3d284 10334#endif
8fd4256d 10335
3e73aa7c
JH		 10336 case BFD_RELOC_X86_64_PLT32:
10337 case BFD_RELOC_X86_64_GOT32:
10338 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 10339 case BFD_RELOC_386_PLT32:
10340 case BFD_RELOC_386_GOT32:
10341 case BFD_RELOC_386_GOTOFF:
10342 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10343 case BFD_RELOC_386_TLS_GD:
10344 case BFD_RELOC_386_TLS_LDM:
10345 case BFD_RELOC_386_TLS_LDO_32:
10346 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10347 case BFD_RELOC_386_TLS_IE:
10348 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10349 case BFD_RELOC_386_TLS_LE_32:
10350 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10351 case BFD_RELOC_386_TLS_GOTDESC:
10352 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10353 case BFD_RELOC_X86_64_TLSGD:
10354 case BFD_RELOC_X86_64_TLSLD:
10355 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10356 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10357 case BFD_RELOC_X86_64_GOTTPOFF:
10358 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10359 case BFD_RELOC_X86_64_TPOFF64:
10360 case BFD_RELOC_X86_64_GOTOFF64:
10361 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10362 case BFD_RELOC_X86_64_GOT64:
10363 case BFD_RELOC_X86_64_GOTPCREL64:
10364 case BFD_RELOC_X86_64_GOTPC64:
10365 case BFD_RELOC_X86_64_GOTPLT64:
10366 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10367 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10368 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10369 case BFD_RELOC_RVA:
10370 case BFD_RELOC_VTABLE_ENTRY:
10371 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10372#ifdef TE_PE
10373 case BFD_RELOC_32_SECREL:
10374#endif
252b5132
RH		 10375 code = fixp->fx_r_type;
10376 break;
dbbaec26
L		 10377 case BFD_RELOC_X86_64_32S:
10378 if (!fixp->fx_pcrel)
10379 {
10380 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10381 code = fixp->fx_r_type;
10382 break;
10383 }
252b5132 10384 default:
93382f6d 10385 if (fixp->fx_pcrel)
252b5132 10386 {
93382f6d
AM		 10387 switch (fixp->fx_size)
10388 {
10389 default:
b091f402
AM		 10390 as_bad_where (fixp->fx_file, fixp->fx_line,
10391 _("can not do %d byte pc-relative relocation"),
10392 fixp->fx_size);
93382f6d
AM		 10393 code = BFD_RELOC_32_PCREL;
10394 break;
10395 case 1: code = BFD_RELOC_8_PCREL; break;
10396 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10397 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10398#ifdef BFD64
10399 case 8: code = BFD_RELOC_64_PCREL; break;
10400#endif
93382f6d
AM		 10401 }
10402 }
10403 else
10404 {
10405 switch (fixp->fx_size)
10406 {
10407 default:
b091f402
AM		 10408 as_bad_where (fixp->fx_file, fixp->fx_line,
10409 _("can not do %d byte relocation"),
10410 fixp->fx_size);
93382f6d
AM		 10411 code = BFD_RELOC_32;
10412 break;
10413 case 1: code = BFD_RELOC_8; break;
10414 case 2: code = BFD_RELOC_16; break;
10415 case 4: code = BFD_RELOC_32; break;
937149dd 10416#ifdef BFD64
3e73aa7c 10417 case 8: code = BFD_RELOC_64; break;
937149dd 10418#endif
93382f6d 10419 }
252b5132
RH		 10420 }
10421 break;
10422 }
252b5132 10423
d182319b
JB		 10424 if ((code == BFD_RELOC_32
10425 || code == BFD_RELOC_32_PCREL
10426 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10427 && GOT_symbol
10428 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10429 {
4fa24527 10430 if (!object_64bit)
d6ab8113
JB		 10431 code = BFD_RELOC_386_GOTPC;
10432 else
10433 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10434 }
7b81dfbb
AJ		 10435 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10436 && GOT_symbol
10437 && fixp->fx_addsy == GOT_symbol)
10438 {
10439 code = BFD_RELOC_X86_64_GOTPC64;
10440 }
252b5132
RH		 10441
10442 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10443 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10444 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10445
10446 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10447
3e73aa7c
JH		 10448 if (!use_rela_relocations)
10449 {
10450 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10451 vtable entry to be used in the relocation's section offset. */
10452 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10453 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10454#if defined (OBJ_COFF) && defined (TE_PE)
10455 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10456 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10457 else
10458#endif
c6682705 10459 rel->addend = 0;
3e73aa7c
JH		 10460 }
10461 /* Use the rela in 64bit mode. */
252b5132 10462 else
3e73aa7c 10463 {
862be3fb
L		 10464 if (disallow_64bit_reloc)
10465 switch (code)
10466 {
862be3fb
L		 10467 case BFD_RELOC_X86_64_DTPOFF64:
10468 case BFD_RELOC_X86_64_TPOFF64:
10469 case BFD_RELOC_64_PCREL:
10470 case BFD_RELOC_X86_64_GOTOFF64:
10471 case BFD_RELOC_X86_64_GOT64:
10472 case BFD_RELOC_X86_64_GOTPCREL64:
10473 case BFD_RELOC_X86_64_GOTPC64:
10474 case BFD_RELOC_X86_64_GOTPLT64:
10475 case BFD_RELOC_X86_64_PLTOFF64:
10476 as_bad_where (fixp->fx_file, fixp->fx_line,
10477 _("cannot represent relocation type %s in x32 mode"),
10478 bfd_get_reloc_code_name (code));
10479 break;
10480 default:
10481 break;
10482 }
10483
062cd5e7
AS		 10484 if (!fixp->fx_pcrel)
10485 rel->addend = fixp->fx_offset;
10486 else
10487 switch (code)
10488 {
10489 case BFD_RELOC_X86_64_PLT32:
10490 case BFD_RELOC_X86_64_GOT32:
10491 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 10492 case BFD_RELOC_X86_64_TLSGD:
10493 case BFD_RELOC_X86_64_TLSLD:
10494 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10495 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10496 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10497 rel->addend = fixp->fx_offset - fixp->fx_size;
10498 break;
10499 default:
10500 rel->addend = (section->vma
10501 - fixp->fx_size
10502 + fixp->fx_addnumber
10503 + md_pcrel_from (fixp));
10504 break;
10505 }
3e73aa7c
JH		 10506 }
10507
252b5132
RH		 10508 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10509 if (rel->howto == NULL)
10510 {
10511 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10512 _("cannot represent relocation type %s"),
252b5132
RH		 10513 bfd_get_reloc_code_name (code));
10514 /* Set howto to a garbage value so that we can keep going. */
10515 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10516 gas_assert (rel->howto != NULL);
252b5132
RH		 10517 }
10518
10519 return rel;
10520}
10521
ee86248c 10522#include "tc-i386-intel.c"
54cfded0 10523
a60de03c
JB		 10524void
10525tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10526{
a60de03c
JB		 10527 int saved_naked_reg;
10528 char saved_register_dot;
54cfded0 10529
a60de03c
JB		 10530 saved_naked_reg = allow_naked_reg;
10531 allow_naked_reg = 1;
10532 saved_register_dot = register_chars['.'];
10533 register_chars['.'] = '.';
10534 allow_pseudo_reg = 1;
10535 expression_and_evaluate (exp);
10536 allow_pseudo_reg = 0;
10537 register_chars['.'] = saved_register_dot;
10538 allow_naked_reg = saved_naked_reg;
10539
e96d56a1 10540 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10541 {
a60de03c
JB		 10542 if ((addressT) exp->X_add_number < i386_regtab_size)
10543 {
10544 exp->X_op = O_constant;
10545 exp->X_add_number = i386_regtab[exp->X_add_number]
10546 .dw2_regnum[flag_code >> 1];
10547 }
10548 else
10549 exp->X_op = O_illegal;
54cfded0 10550 }
54cfded0
AM		 10551}
10552
10553void
10554tc_x86_frame_initial_instructions (void)
10555{
a60de03c
JB		 10556 static unsigned int sp_regno[2];
10557
10558 if (!sp_regno[flag_code >> 1])
10559 {
10560 char *saved_input = input_line_pointer;
10561 char sp[][4] = {"esp", "rsp"};
10562 expressionS exp;
a4447b93 10563
a60de03c
JB		 10564 input_line_pointer = sp[flag_code >> 1];
10565 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10566 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10567 sp_regno[flag_code >> 1] = exp.X_add_number;
10568 input_line_pointer = saved_input;
10569 }
a4447b93 10570
61ff971f
L		 10571 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10572 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10573}
d2b2c203 10574
d7921315
L		 10575int
10576x86_dwarf2_addr_size (void)
10577{
10578#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10579 if (x86_elf_abi == X86_64_X32_ABI)
10580 return 4;
10581#endif
10582 return bfd_arch_bits_per_address (stdoutput) / 8;
10583}
10584
d2b2c203
DJ		 10585int
10586i386_elf_section_type (const char *str, size_t len)
10587{
10588 if (flag_code == CODE_64BIT
10589 && len == sizeof ("unwind") - 1
10590 && strncmp (str, "unwind", 6) == 0)
10591 return SHT_X86_64_UNWIND;
10592
10593 return -1;
10594}
bb41ade5 10595
ad5fec3b
EB		 10596#ifdef TE_SOLARIS
10597void
10598i386_solaris_fix_up_eh_frame (segT sec)
10599{
10600 if (flag_code == CODE_64BIT)
10601 elf_section_type (sec) = SHT_X86_64_UNWIND;
10602}
10603#endif
10604
bb41ade5
AM		 10605#ifdef TE_PE
10606void
10607tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10608{
91d6fa6a 10609 expressionS exp;
bb41ade5 10610
91d6fa6a
NC		 10611 exp.X_op = O_secrel;
10612 exp.X_add_symbol = symbol;
10613 exp.X_add_number = 0;
10614 emit_expr (&exp, size);
bb41ade5
AM		 10615}
10616#endif
3b22753a
L		 10617
10618#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10619/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10620
01e1a5bc 10621bfd_vma
3b22753a
L		 10622x86_64_section_letter (int letter, char **ptr_msg)
10623{
10624 if (flag_code == CODE_64BIT)
10625 {
10626 if (letter == 'l')
10627 return SHF_X86_64_LARGE;
10628
8f3bae45 10629 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10630 }
3b22753a 10631 else
8f3bae45 10632 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10633 return -1;
10634}
10635
01e1a5bc 10636bfd_vma
3b22753a
L		 10637x86_64_section_word (char *str, size_t len)
10638{
8620418b 10639 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10640 return SHF_X86_64_LARGE;
10641
10642 return -1;
10643}
10644
10645static void
10646handle_large_common (int small ATTRIBUTE_UNUSED)
10647{
10648 if (flag_code != CODE_64BIT)
10649 {
10650 s_comm_internal (0, elf_common_parse);
10651 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10652 }
10653 else
10654 {
10655 static segT lbss_section;
10656 asection *saved_com_section_ptr = elf_com_section_ptr;
10657 asection *saved_bss_section = bss_section;
10658
10659 if (lbss_section == NULL)
10660 {
10661 flagword applicable;
10662 segT seg = now_seg;
10663 subsegT subseg = now_subseg;
10664
10665 /* The .lbss section is for local .largecomm symbols. */
10666 lbss_section = subseg_new (".lbss", 0);
10667 applicable = bfd_applicable_section_flags (stdoutput);
10668 bfd_set_section_flags (stdoutput, lbss_section,
10669 applicable & SEC_ALLOC);
10670 seg_info (lbss_section)->bss = 1;
10671
10672 subseg_set (seg, subseg);
10673 }
10674
10675 elf_com_section_ptr = &_bfd_elf_large_com_section;
10676 bss_section = lbss_section;
10677
10678 s_comm_internal (0, elf_common_parse);
10679
10680 elf_com_section_ptr = saved_com_section_ptr;
10681 bss_section = saved_bss_section;
10682 }
10683}
10684#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
This page took 2.393429 seconds and 4 git commands to generate.