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x86: simplify control register check
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
219d1afa 2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d 68#define LOCK_PREFIX 5
4e9ac44a
L		 69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
6305a203
L		 84/* Intel Syntax. Use a non-ascii letter since since it never appears
85 in instructions. */
86#define LONG_DOUBLE_MNEM_SUFFIX '\1'
87
88#define END_OF_INSN '\0'
89
90/*
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
95 END.
96 */
97typedef struct
98{
d3ce72d0
NC		 99 const insn_template *start;
100 const insn_template *end;
6305a203
L		 101}
102templates;
103
104/* 386 operand encoding bytes: see 386 book for details of this. */
105typedef struct
106{
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
110}
111modrm_byte;
112
113/* x86-64 extension prefix. */
114typedef int rex_byte;
115
6305a203
L		 116/* 386 opcode byte to code indirect addressing. */
117typedef struct
118{
119 unsigned base;
120 unsigned index;
121 unsigned scale;
122}
123sib_byte;
124
6305a203
L		 125/* x86 arch names, types and features */
126typedef struct
127{
128 const char *name; /* arch name */
8a2c8fef 129 unsigned int len; /* arch string length */
6305a203
L		 130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 132 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 133}
134arch_entry;
135
293f5f65
L		 136/* Used to turn off indicated flags. */
137typedef struct
138{
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
142}
143noarch_entry;
144
78f12dd3 145static void update_code_flag (int, int);
e3bb37b5
L		 146static void set_code_flag (int);
147static void set_16bit_gcc_code_flag (int);
148static void set_intel_syntax (int);
1efbbeb4 149static void set_intel_mnemonic (int);
db51cc60 150static void set_allow_index_reg (int);
7bab8ab5 151static void set_check (int);
e3bb37b5 152static void set_cpu_arch (int);
6482c264 153#ifdef TE_PE
e3bb37b5 154static void pe_directive_secrel (int);
6482c264 155#endif
e3bb37b5
L		 156static void signed_cons (int);
157static char *output_invalid (int c);
ee86248c
JB		 158static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
159 const char *);
160static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
161 const char *);
a7619375 162static int i386_att_operand (char *);
e3bb37b5 163static int i386_intel_operand (char *, int);
ee86248c
JB		 164static int i386_intel_simplify (expressionS *);
165static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 166static const reg_entry *parse_register (char *, char **);
167static char *parse_insn (char *, char *);
168static char *parse_operands (char *, const char *);
169static void swap_operands (void);
4d456e3d 170static void swap_2_operands (int, int);
e3bb37b5
L		 171static void optimize_imm (void);
172static void optimize_disp (void);
83b16ac6 173static const insn_template *match_template (char);
e3bb37b5
L		 174static int check_string (void);
175static int process_suffix (void);
176static int check_byte_reg (void);
177static int check_long_reg (void);
178static int check_qword_reg (void);
179static int check_word_reg (void);
180static int finalize_imm (void);
181static int process_operands (void);
182static const seg_entry *build_modrm_byte (void);
183static void output_insn (void);
184static void output_imm (fragS *, offsetT);
185static void output_disp (fragS *, offsetT);
29b0f896 186#ifndef I386COFF
e3bb37b5 187static void s_bss (int);
252b5132 188#endif
17d4e2a2
L		 189#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190static void handle_large_common (int small ATTRIBUTE_UNUSED);
191#endif
252b5132 192
a847613f 193static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 194
43234a1e
L		 195/* This struct describes rounding control and SAE in the instruction. */
196struct RC_Operation
197{
198 enum rc_type
199 {
200 rne = 0,
201 rd,
202 ru,
203 rz,
204 saeonly
205 } type;
206 int operand;
207};
208
209static struct RC_Operation rc_op;
210
211/* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214struct Mask_Operation
215{
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
219 int operand;
220};
221
222static struct Mask_Operation mask_op;
223
224/* The struct describes broadcasting, applied to OPERAND. FACTOR is
225 broadcast factor. */
226struct Broadcast_Operation
227{
8e6e0792 228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
43234a1e
L		 229 int type;
230
231 /* Index of broadcasted operand. */
232 int operand;
233};
234
235static struct Broadcast_Operation broadcast_op;
236
c0f3af97
L		 237/* VEX prefix. */
238typedef struct
239{
43234a1e
L		 240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
c0f3af97
L		 242 unsigned int length;
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
245} vex_prefix;
246
252b5132 247/* 'md_assemble ()' gathers together information and puts it into a
47926f60 248 i386_insn. */
252b5132 249
520dc8e8
AM		 250union i386_op
251 {
252 expressionS *disps;
253 expressionS *imms;
254 const reg_entry *regs;
255 };
256
a65babc9
L		 257enum i386_error
258 {
86e026a4 259 operand_size_mismatch,
a65babc9
L		 260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
264 bad_imm4,
a65babc9
L		 265 unsupported_with_intel_mnemonic,
266 unsupported_syntax,
6c30d220
L		 267 unsupported,
268 invalid_vsib_address,
7bab8ab5 269 invalid_vector_register_set,
43234a1e
L		 270 unsupported_vector_index_register,
271 unsupported_broadcast,
272 broadcast_not_on_src_operand,
273 broadcast_needed,
274 unsupported_masking,
275 mask_not_on_destination,
276 no_default_mask,
277 unsupported_rc_sae,
278 rc_sae_operand_not_last_imm,
279 invalid_register_operand,
a65babc9
L		 280 };
281
252b5132
RH		 282struct _i386_insn
283 {
47926f60 284 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 285 insn_template tm;
252b5132 286
7d5e4556
L		 287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
252b5132
RH		 289 char suffix;
290
47926f60 291 /* OPERANDS gives the number of given operands. */
252b5132
RH		 292 unsigned int operands;
293
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
47926f60 296 operands. */
252b5132
RH		 297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
298
299 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 300 use OP[i] for the corresponding operand. */
40fb9820 301 i386_operand_type types[MAX_OPERANDS];
252b5132 302
520dc8e8
AM		 303 /* Displacement expression, immediate expression, or register for each
304 operand. */
305 union i386_op op[MAX_OPERANDS];
252b5132 306
3e73aa7c
JH		 307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309#define Operand_PCrel 1
310
252b5132 311 /* Relocation type for operand */
f86103b7 312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 313
252b5132
RH		 314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
319
320 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 321 explicit segment overrides are given. */
ce8a8b2f 322 const seg_entry *seg[2];
252b5132 323
8325cc63
JB		 324 /* Copied first memory operand string, for re-checking. */
325 char *memop1_string;
326
252b5132
RH		 327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
331
332 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 333 addressing modes of this insn are encoded. */
252b5132 334 modrm_byte rm;
3e73aa7c 335 rex_byte rex;
43234a1e 336 rex_byte vrex;
252b5132 337 sib_byte sib;
c0f3af97 338 vex_prefix vex;
b6169b20 339
43234a1e
L		 340 /* Masking attributes. */
341 struct Mask_Operation *mask;
342
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
345
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
348
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
351
86fa6981
L		 352 /* Prefer load or store in encoding. */
353 enum
354 {
355 dir_encoding_default = 0,
356 dir_encoding_load,
357 dir_encoding_store
358 } dir_encoding;
891edac4 359
a501d77e
L		 360 /* Prefer 8bit or 32bit displacement in encoding. */
361 enum
362 {
363 disp_encoding_default = 0,
364 disp_encoding_8bit,
365 disp_encoding_32bit
366 } disp_encoding;
f8a5c266 367
6b6b6807
L		 368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding;
370
b6f8c7c4
L		 371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize;
373
86fa6981
L		 374 /* How to encode vector instructions. */
375 enum
376 {
377 vex_encoding_default = 0,
378 vex_encoding_vex2,
379 vex_encoding_vex3,
380 vex_encoding_evex
381 } vec_encoding;
382
d5de92cf
L		 383 /* REP prefix. */
384 const char *rep_prefix;
385
165de32a
L		 386 /* HLE prefix. */
387 const char *hle_prefix;
42164a71 388
7e8b059b
L		 389 /* Have BND prefix. */
390 const char *bnd_prefix;
391
04ef582a
L		 392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix;
394
891edac4 395 /* Error message. */
a65babc9 396 enum i386_error error;
252b5132
RH		 397 };
398
399typedef struct _i386_insn i386_insn;
400
43234a1e
L		 401/* Link RC type with corresponding string, that'll be looked for in
402 asm. */
403struct RC_name
404{
405 enum rc_type type;
406 const char *name;
407 unsigned int len;
408};
409
410static const struct RC_name RC_NamesTable[] =
411{
412 { rne, STRING_COMMA_LEN ("rn-sae") },
413 { rd, STRING_COMMA_LEN ("rd-sae") },
414 { ru, STRING_COMMA_LEN ("ru-sae") },
415 { rz, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly, STRING_COMMA_LEN ("sae") },
417};
418
252b5132
RH		 419/* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 421const char extra_symbol_chars[] = "*%-([{}"
252b5132 422#ifdef LEX_AT
32137342
NC		 423 "@"
424#endif
425#ifdef LEX_QM
426 "?"
252b5132 427#endif
32137342 428 ;
252b5132 429
29b0f896
AM		 430#if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 432 && !defined (TE_GNU) \
29b0f896 433 && !defined (TE_LINUX) \
8d63c93e 434 && !defined (TE_NACL) \
29b0f896 435 && !defined (TE_FreeBSD) \
5b806d27 436 && !defined (TE_DragonFly) \
29b0f896 437 && !defined (TE_NetBSD)))
252b5132 438/* This array holds the chars that always start a comment. If the
b3b91714
AM		 439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441const char *i386_comment_chars = "#/";
442#define SVR4_COMMENT_CHARS 1
252b5132 443#define PREFIX_SEPARATOR '\\'
252b5132 444
b3b91714
AM		 445#else
446const char *i386_comment_chars = "#";
447#define PREFIX_SEPARATOR '/'
448#endif
449
252b5132
RH		 450/* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 454 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
252b5132 457 '/' isn't otherwise defined. */
b3b91714 458const char line_comment_chars[] = "#/";
252b5132 459
63a0b638 460const char line_separator_chars[] = ";";
252b5132 461
ce8a8b2f
AM		 462/* Chars that can be used to separate mant from exp in floating point
463 nums. */
252b5132
RH		 464const char EXP_CHARS[] = "eE";
465
ce8a8b2f
AM		 466/* Chars that mean this number is a floating point constant
467 As in 0f12.456
468 or 0d1.2345e12. */
252b5132
RH		 469const char FLT_CHARS[] = "fFdDxX";
470
ce8a8b2f 471/* Tables for lexical analysis. */
252b5132
RH		 472static char mnemonic_chars[256];
473static char register_chars[256];
474static char operand_chars[256];
475static char identifier_chars[256];
476static char digit_chars[256];
477
ce8a8b2f 478/* Lexical macros. */
252b5132
RH		 479#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480#define is_operand_char(x) (operand_chars[(unsigned char) x])
481#define is_register_char(x) (register_chars[(unsigned char) x])
482#define is_space_char(x) ((x) == ' ')
483#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484#define is_digit_char(x) (digit_chars[(unsigned char) x])
485
0234cb7c 486/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 487static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
488
489/* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
47926f60 492 assembler instruction). */
252b5132 493static char save_stack[32];
ce8a8b2f 494static char *save_stack_p;
252b5132
RH		 495#define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497#define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
499
47926f60 500/* The instruction we're assembling. */
252b5132
RH		 501static i386_insn i;
502
503/* Possible templates for current insn. */
504static const templates *current_templates;
505
31b2323c
L		 506/* Per instruction expressionS buffers: max displacements & immediates. */
507static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
508static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 509
47926f60 510/* Current operand we are working on. */
ee86248c 511static int this_operand = -1;
252b5132 512
3e73aa7c
JH		 513/* We support four different modes. FLAG_CODE variable is used to distinguish
514 these. */
515
516enum flag_code {
517 CODE_32BIT,
518 CODE_16BIT,
519 CODE_64BIT };
520
521static enum flag_code flag_code;
4fa24527 522static unsigned int object_64bit;
862be3fb 523static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 524static int use_rela_relocations = 0;
525
7af8ed2d
NC		 526#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
529
351f65ca
L		 530/* The ELF ABI to use. */
531enum x86_elf_abi
532{
533 I386_ABI,
7f56bc95
L		 534 X86_64_ABI,
535 X86_64_X32_ABI
351f65ca
L		 536};
537
538static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 539#endif
351f65ca 540
167ad85b
TG		 541#if defined (TE_PE) || defined (TE_PEP)
542/* Use big object file format. */
543static int use_big_obj = 0;
544#endif
545
8dcea932
L		 546#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547/* 1 if generating code for a shared library. */
548static int shared = 0;
549#endif
550
47926f60
KH		 551/* 1 for intel syntax,
552 0 if att syntax. */
553static int intel_syntax = 0;
252b5132 554
e89c5eaa
L		 555/* 1 for Intel64 ISA,
556 0 if AMD64 ISA. */
557static int intel64;
558
1efbbeb4
L		 559/* 1 for intel mnemonic,
560 0 if att mnemonic. */
561static int intel_mnemonic = !SYSV386_COMPAT;
562
a60de03c
JB		 563/* 1 if pseudo registers are permitted. */
564static int allow_pseudo_reg = 0;
565
47926f60
KH		 566/* 1 if register prefix % not required. */
567static int allow_naked_reg = 0;
252b5132 568
33eaf5de 569/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 570 instructions supporting it, even if this prefix wasn't specified
571 explicitly. */
572static int add_bnd_prefix = 0;
573
ba104c83 574/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 575static int allow_index_reg = 0;
576
d022bddd
IT		 577/* 1 if the assembler should ignore LOCK prefix, even if it was
578 specified explicitly. */
579static int omit_lock_prefix = 0;
580
e4e00185
AS		 581/* 1 if the assembler should encode lfence, mfence, and sfence as
582 "lock addl $0, (%{re}sp)". */
583static int avoid_fence = 0;
584
0cb4071e
L		 585/* 1 if the assembler should generate relax relocations. */
586
587static int generate_relax_relocations
588 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
589
7bab8ab5 590static enum check_kind
daf50ae7 591 {
7bab8ab5
JB		 592 check_none = 0,
593 check_warning,
594 check_error
daf50ae7 595 }
7bab8ab5 596sse_check, operand_check = check_warning;
daf50ae7 597
b6f8c7c4
L		 598/* Optimization:
599 1. Clear the REX_W bit with register operand if possible.
600 2. Above plus use 128bit vector instruction to clear the full vector
601 register.
602 */
603static int optimize = 0;
604
605/* Optimization:
606 1. Clear the REX_W bit with register operand if possible.
607 2. Above plus use 128bit vector instruction to clear the full vector
608 register.
609 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
610 "testb $imm7,%r8".
611 */
612static int optimize_for_space = 0;
613
2ca3ace5
L		 614/* Register prefix used for error message. */
615static const char *register_prefix = "%";
616
47926f60
KH		 617/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
618 leave, push, and pop instructions so that gcc has the same stack
619 frame as in 32 bit mode. */
620static char stackop_size = '\0';
eecb386c 621
12b55ccc
L		 622/* Non-zero to optimize code alignment. */
623int optimize_align_code = 1;
624
47926f60
KH		 625/* Non-zero to quieten some warnings. */
626static int quiet_warnings = 0;
a38cf1db 627
47926f60
KH		 628/* CPU name. */
629static const char *cpu_arch_name = NULL;
6305a203 630static char *cpu_sub_arch_name = NULL;
a38cf1db 631
47926f60 632/* CPU feature flags. */
40fb9820
L		 633static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
634
ccc9c027
L		 635/* If we have selected a cpu we are generating instructions for. */
636static int cpu_arch_tune_set = 0;
637
9103f4f4 638/* Cpu we are generating instructions for. */
fbf3f584 639enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 640
641/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 642static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 643
ccc9c027 644/* CPU instruction set architecture used. */
fbf3f584 645enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 646
9103f4f4 647/* CPU feature flags of instruction set architecture used. */
fbf3f584 648i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 649
fddf5b5b
AM		 650/* If set, conditional jumps are not automatically promoted to handle
651 larger than a byte offset. */
652static unsigned int no_cond_jump_promotion = 0;
653
c0f3af97
L		 654/* Encode SSE instructions with VEX prefix. */
655static unsigned int sse2avx;
656
539f890d
L		 657/* Encode scalar AVX instructions with specific vector length. */
658static enum
659 {
660 vex128 = 0,
661 vex256
662 } avxscalar;
663
43234a1e
L		 664/* Encode scalar EVEX LIG instructions with specific vector length. */
665static enum
666 {
667 evexl128 = 0,
668 evexl256,
669 evexl512
670 } evexlig;
671
672/* Encode EVEX WIG instructions with specific evex.w. */
673static enum
674 {
675 evexw0 = 0,
676 evexw1
677 } evexwig;
678
d3d3c6db
IT		 679/* Value to encode in EVEX RC bits, for SAE-only instructions. */
680static enum rc_type evexrcig = rne;
681
29b0f896 682/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 683static symbolS *GOT_symbol;
29b0f896 684
a4447b93
RH		 685/* The dwarf2 return column, adjusted for 32 or 64 bit. */
686unsigned int x86_dwarf2_return_column;
687
688/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
689int x86_cie_data_alignment;
690
252b5132 691/* Interface to relax_segment.
fddf5b5b
AM		 692 There are 3 major relax states for 386 jump insns because the
693 different types of jumps add different sizes to frags when we're
694 figuring out what sort of jump to choose to reach a given label. */
252b5132 695
47926f60 696/* Types. */
93c2a809
AM		 697#define UNCOND_JUMP 0
698#define COND_JUMP 1
699#define COND_JUMP86 2
fddf5b5b 700
47926f60 701/* Sizes. */
252b5132
RH		 702#define CODE16 1
703#define SMALL 0
29b0f896 704#define SMALL16 (SMALL | CODE16)
252b5132 705#define BIG 2
29b0f896 706#define BIG16 (BIG | CODE16)
252b5132
RH		 707
708#ifndef INLINE
709#ifdef __GNUC__
710#define INLINE __inline__
711#else
712#define INLINE
713#endif
714#endif
715
fddf5b5b
AM		 716#define ENCODE_RELAX_STATE(type, size) \
717 ((relax_substateT) (((type) << 2) | (size)))
718#define TYPE_FROM_RELAX_STATE(s) \
719 ((s) >> 2)
720#define DISP_SIZE_FROM_RELAX_STATE(s) \
721 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 722
723/* This table is used by relax_frag to promote short jumps to long
724 ones where necessary. SMALL (short) jumps may be promoted to BIG
725 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
726 don't allow a short jump in a 32 bit code segment to be promoted to
727 a 16 bit offset jump because it's slower (requires data size
728 prefix), and doesn't work, unless the destination is in the bottom
729 64k of the code segment (The top 16 bits of eip are zeroed). */
730
731const relax_typeS md_relax_table[] =
732{
24eab124
AM		 733 /* The fields are:
734 1) most positive reach of this state,
735 2) most negative reach of this state,
93c2a809 736 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 737 4) which index into the table to try if we can't fit into this one. */
252b5132 738
fddf5b5b 739 /* UNCOND_JUMP states. */
93c2a809
AM		 740 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
742 /* dword jmp adds 4 bytes to frag:
743 0 extra opcode bytes, 4 displacement bytes. */
252b5132 744 {0, 0, 4, 0},
93c2a809
AM		 745 /* word jmp adds 2 byte2 to frag:
746 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 747 {0, 0, 2, 0},
748
93c2a809
AM		 749 /* COND_JUMP states. */
750 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
752 /* dword conditionals adds 5 bytes to frag:
753 1 extra opcode byte, 4 displacement bytes. */
754 {0, 0, 5, 0},
fddf5b5b 755 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 756 1 extra opcode byte, 2 displacement bytes. */
757 {0, 0, 3, 0},
758
759 /* COND_JUMP86 states. */
760 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
762 /* dword conditionals adds 5 bytes to frag:
763 1 extra opcode byte, 4 displacement bytes. */
764 {0, 0, 5, 0},
765 /* word conditionals add 4 bytes to frag:
766 1 displacement byte and a 3 byte long branch insn. */
767 {0, 0, 4, 0}
252b5132
RH		 768};
769
9103f4f4
L		 770static const arch_entry cpu_arch[] =
771{
89507696
JB		 772 /* Do not replace the first two entries - i386_target_format()
773 relies on them being there in this order. */
8a2c8fef 774 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 775 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 776 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 777 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 778 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 779 CPU_NONE_FLAGS, 0 },
8a2c8fef 780 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 781 CPU_I186_FLAGS, 0 },
8a2c8fef 782 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 783 CPU_I286_FLAGS, 0 },
8a2c8fef 784 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 785 CPU_I386_FLAGS, 0 },
8a2c8fef 786 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 787 CPU_I486_FLAGS, 0 },
8a2c8fef 788 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 789 CPU_I586_FLAGS, 0 },
8a2c8fef 790 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 791 CPU_I686_FLAGS, 0 },
8a2c8fef 792 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 793 CPU_I586_FLAGS, 0 },
8a2c8fef 794 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 795 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 796 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 797 CPU_P2_FLAGS, 0 },
8a2c8fef 798 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 799 CPU_P3_FLAGS, 0 },
8a2c8fef 800 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 801 CPU_P4_FLAGS, 0 },
8a2c8fef 802 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 803 CPU_CORE_FLAGS, 0 },
8a2c8fef 804 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 805 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 806 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 807 CPU_CORE_FLAGS, 1 },
8a2c8fef 808 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 809 CPU_CORE_FLAGS, 0 },
8a2c8fef 810 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 811 CPU_CORE2_FLAGS, 1 },
8a2c8fef 812 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 813 CPU_CORE2_FLAGS, 0 },
8a2c8fef 814 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 815 CPU_COREI7_FLAGS, 0 },
8a2c8fef 816 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 817 CPU_L1OM_FLAGS, 0 },
7a9068fe 818 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 819 CPU_K1OM_FLAGS, 0 },
81486035 820 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 821 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 822 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 823 CPU_K6_FLAGS, 0 },
8a2c8fef 824 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 825 CPU_K6_2_FLAGS, 0 },
8a2c8fef 826 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 827 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 828 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 829 CPU_K8_FLAGS, 1 },
8a2c8fef 830 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 831 CPU_K8_FLAGS, 0 },
8a2c8fef 832 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 833 CPU_K8_FLAGS, 0 },
8a2c8fef 834 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 835 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 836 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 837 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 838 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 839 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 840 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 841 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 842 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 843 CPU_BDVER4_FLAGS, 0 },
029f3522 844 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 845 CPU_ZNVER1_FLAGS, 0 },
a9660a6f
AP		 846 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER,
847 CPU_ZNVER2_FLAGS, 0 },
7b458c12 848 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 849 CPU_BTVER1_FLAGS, 0 },
7b458c12 850 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 851 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 852 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 853 CPU_8087_FLAGS, 0 },
8a2c8fef 854 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 855 CPU_287_FLAGS, 0 },
8a2c8fef 856 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 857 CPU_387_FLAGS, 0 },
1848e567
L		 858 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
859 CPU_687_FLAGS, 0 },
8a2c8fef 860 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 861 CPU_MMX_FLAGS, 0 },
8a2c8fef 862 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 863 CPU_SSE_FLAGS, 0 },
8a2c8fef 864 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 865 CPU_SSE2_FLAGS, 0 },
8a2c8fef 866 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 867 CPU_SSE3_FLAGS, 0 },
8a2c8fef 868 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 869 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 870 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 871 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 872 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 873 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 874 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 875 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 876 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 877 CPU_AVX_FLAGS, 0 },
6c30d220 878 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 879 CPU_AVX2_FLAGS, 0 },
43234a1e 880 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 881 CPU_AVX512F_FLAGS, 0 },
43234a1e 882 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 883 CPU_AVX512CD_FLAGS, 0 },
43234a1e 884 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 885 CPU_AVX512ER_FLAGS, 0 },
43234a1e 886 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 887 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 888 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 889 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 890 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 891 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 892 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 893 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 894 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 895 CPU_VMX_FLAGS, 0 },
8729a6f6 896 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 897 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 898 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 899 CPU_SMX_FLAGS, 0 },
8a2c8fef 900 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 901 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 902 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 903 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 904 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 905 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 906 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 907 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 908 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 909 CPU_AES_FLAGS, 0 },
8a2c8fef 910 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 911 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 912 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 913 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 914 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 915 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 916 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 917 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 918 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 919 CPU_F16C_FLAGS, 0 },
6c30d220 920 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 921 CPU_BMI2_FLAGS, 0 },
8a2c8fef 922 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 923 CPU_FMA_FLAGS, 0 },
8a2c8fef 924 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 925 CPU_FMA4_FLAGS, 0 },
8a2c8fef 926 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 927 CPU_XOP_FLAGS, 0 },
8a2c8fef 928 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 929 CPU_LWP_FLAGS, 0 },
8a2c8fef 930 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 931 CPU_MOVBE_FLAGS, 0 },
60aa667e 932 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 933 CPU_CX16_FLAGS, 0 },
8a2c8fef 934 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 935 CPU_EPT_FLAGS, 0 },
6c30d220 936 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 937 CPU_LZCNT_FLAGS, 0 },
42164a71 938 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 939 CPU_HLE_FLAGS, 0 },
42164a71 940 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 941 CPU_RTM_FLAGS, 0 },
6c30d220 942 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 943 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 944 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 945 CPU_CLFLUSH_FLAGS, 0 },
22109423 946 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 947 CPU_NOP_FLAGS, 0 },
8a2c8fef 948 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 949 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 950 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 951 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 952 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 953 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 954 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 955 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 956 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 957 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 958 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 959 CPU_SVME_FLAGS, 1 },
8a2c8fef 960 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 961 CPU_SVME_FLAGS, 0 },
8a2c8fef 962 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 963 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 964 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 965 CPU_ABM_FLAGS, 0 },
87973e9f 966 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 967 CPU_BMI_FLAGS, 0 },
2a2a0f38 968 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 969 CPU_TBM_FLAGS, 0 },
e2e1fcde 970 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 971 CPU_ADX_FLAGS, 0 },
e2e1fcde 972 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 973 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 974 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 975 CPU_PRFCHW_FLAGS, 0 },
5c111e37 976 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 977 CPU_SMAP_FLAGS, 0 },
7e8b059b 978 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 979 CPU_MPX_FLAGS, 0 },
a0046408 980 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 981 CPU_SHA_FLAGS, 0 },
963f3586 982 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 983 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 984 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 985 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 986 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 987 CPU_SE1_FLAGS, 0 },
c5e7287a 988 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 989 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 990 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 991 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 992 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 993 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 994 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
995 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 996 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
997 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 998 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
999 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
53467f57
IT		 1000 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1001 CPU_AVX512_VBMI2_FLAGS, 0 },
8cfcb765
IT		 1002 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1003 CPU_AVX512_VNNI_FLAGS, 0 },
ee6872be
IT		 1004 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1005 CPU_AVX512_BITALG_FLAGS, 0 },
029f3522 1006 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 1007 CPU_CLZERO_FLAGS, 0 },
9916071f 1008 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 1009 CPU_MWAITX_FLAGS, 0 },
8eab4136 1010 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 1011 CPU_OSPKE_FLAGS, 0 },
8bc52696 1012 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 1013 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 1014 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1015 CPU_PTWRITE_FLAGS, 0 },
d777820b
IT		 1016 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1017 CPU_IBT_FLAGS, 0 },
1018 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1019 CPU_SHSTK_FLAGS, 0 },
48521003
IT		 1020 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1021 CPU_GFNI_FLAGS, 0 },
8dcf1fad
IT		 1022 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1023 CPU_VAES_FLAGS, 0 },
ff1982d5
IT		 1024 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1025 CPU_VPCLMULQDQ_FLAGS, 0 },
3233d7d0
IT		 1026 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1027 CPU_WBNOINVD_FLAGS, 0 },
be3a8dca
IT		 1028 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1029 CPU_PCONFIG_FLAGS, 0 },
de89d0a3
IT		 1030 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1031 CPU_WAITPKG_FLAGS, 0 },
c48935d7
IT		 1032 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1033 CPU_CLDEMOTE_FLAGS, 0 },
c0a30a9f
L		 1034 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN,
1035 CPU_MOVDIRI_FLAGS, 0 },
1036 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
1037 CPU_MOVDIR64B_FLAGS, 0 },
293f5f65
L		 1038};
1039
1040static const noarch_entry cpu_noarch[] =
1041{
1042 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 1043 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1044 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1045 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 1046 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1047 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1048 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1049 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1050 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1051 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1052 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1053 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1054 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1055 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1056 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1063 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1064 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1065 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1066 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1067 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
53467f57 1068 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
8cfcb765 1069 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
ee6872be 1070 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
d777820b
IT		 1071 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1072 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
c0a30a9f
L		 1073 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
1074 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
e413e4e9
AM		 1075};
1076
704209c0 1077#ifdef I386COFF
a6c24e68
NC		 1078/* Like s_lcomm_internal in gas/read.c but the alignment string
1079 is allowed to be optional. */
1080
1081static symbolS *
1082pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1083{
1084 addressT align = 0;
1085
1086 SKIP_WHITESPACE ();
1087
7ab9ffdd 1088 if (needs_align
a6c24e68
NC		 1089 && *input_line_pointer == ',')
1090 {
1091 align = parse_align (needs_align - 1);
7ab9ffdd 1092
a6c24e68
NC		 1093 if (align == (addressT) -1)
1094 return NULL;
1095 }
1096 else
1097 {
1098 if (size >= 8)
1099 align = 3;
1100 else if (size >= 4)
1101 align = 2;
1102 else if (size >= 2)
1103 align = 1;
1104 else
1105 align = 0;
1106 }
1107
1108 bss_alloc (symbolP, size, align);
1109 return symbolP;
1110}
1111
704209c0 1112static void
a6c24e68
NC		 1113pe_lcomm (int needs_align)
1114{
1115 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1116}
704209c0 1117#endif
a6c24e68 1118
29b0f896
AM		 1119const pseudo_typeS md_pseudo_table[] =
1120{
1121#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1122 {"align", s_align_bytes, 0},
1123#else
1124 {"align", s_align_ptwo, 0},
1125#endif
1126 {"arch", set_cpu_arch, 0},
1127#ifndef I386COFF
1128 {"bss", s_bss, 0},
a6c24e68
NC		 1129#else
1130 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1131#endif
1132 {"ffloat", float_cons, 'f'},
1133 {"dfloat", float_cons, 'd'},
1134 {"tfloat", float_cons, 'x'},
1135 {"value", cons, 2},
d182319b 1136 {"slong", signed_cons, 4},
29b0f896
AM		 1137 {"noopt", s_ignore, 0},
1138 {"optim", s_ignore, 0},
1139 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1140 {"code16", set_code_flag, CODE_16BIT},
1141 {"code32", set_code_flag, CODE_32BIT},
da5f19a2 1142#ifdef BFD64
29b0f896 1143 {"code64", set_code_flag, CODE_64BIT},
da5f19a2 1144#endif
29b0f896
AM		 1145 {"intel_syntax", set_intel_syntax, 1},
1146 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1147 {"intel_mnemonic", set_intel_mnemonic, 1},
1148 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1149 {"allow_index_reg", set_allow_index_reg, 1},
1150 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1151 {"sse_check", set_check, 0},
1152 {"operand_check", set_check, 1},
3b22753a
L		 1153#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1154 {"largecomm", handle_large_common, 0},
07a53e5c 1155#else
68d20676 1156 {"file", dwarf2_directive_file, 0},
07a53e5c
RH		 1157 {"loc", dwarf2_directive_loc, 0},
1158 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1159#endif
6482c264
NC		 1160#ifdef TE_PE
1161 {"secrel32", pe_directive_secrel, 0},
1162#endif
29b0f896
AM		 1163 {0, 0, 0}
1164};
1165
1166/* For interface with expression (). */
1167extern char *input_line_pointer;
1168
1169/* Hash table for instruction mnemonic lookup. */
1170static struct hash_control *op_hash;
1171
1172/* Hash table for register lookup. */
1173static struct hash_control *reg_hash;
1174\f
ce8a8b2f
AM		 1175 /* Various efficient no-op patterns for aligning code labels.
1176 Note: Don't try to assemble the instructions in the comments.
1177 0L and 0w are not legal. */
62a02d25
L		 1178static const unsigned char f32_1[] =
1179 {0x90}; /* nop */
1180static const unsigned char f32_2[] =
1181 {0x66,0x90}; /* xchg %ax,%ax */
1182static const unsigned char f32_3[] =
1183 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1184static const unsigned char f32_4[] =
1185 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
62a02d25
L		 1186static const unsigned char f32_6[] =
1187 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1188static const unsigned char f32_7[] =
1189 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
62a02d25 1190static const unsigned char f16_3[] =
3ae729d5 1191 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
62a02d25 1192static const unsigned char f16_4[] =
3ae729d5
L		 1193 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1194static const unsigned char jump_disp8[] =
1195 {0xeb}; /* jmp disp8 */
1196static const unsigned char jump32_disp32[] =
1197 {0xe9}; /* jmp disp32 */
1198static const unsigned char jump16_disp32[] =
1199 {0x66,0xe9}; /* jmp disp32 */
62a02d25
L		 1200/* 32-bit NOPs patterns. */
1201static const unsigned char *const f32_patt[] = {
3ae729d5 1202 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
62a02d25
L		 1203};
1204/* 16-bit NOPs patterns. */
1205static const unsigned char *const f16_patt[] = {
3ae729d5 1206 f32_1, f32_2, f16_3, f16_4
62a02d25
L		 1207};
1208/* nopl (%[re]ax) */
1209static const unsigned char alt_3[] =
1210 {0x0f,0x1f,0x00};
1211/* nopl 0(%[re]ax) */
1212static const unsigned char alt_4[] =
1213 {0x0f,0x1f,0x40,0x00};
1214/* nopl 0(%[re]ax,%[re]ax,1) */
1215static const unsigned char alt_5[] =
1216 {0x0f,0x1f,0x44,0x00,0x00};
1217/* nopw 0(%[re]ax,%[re]ax,1) */
1218static const unsigned char alt_6[] =
1219 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1220/* nopl 0L(%[re]ax) */
1221static const unsigned char alt_7[] =
1222 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1223/* nopl 0L(%[re]ax,%[re]ax,1) */
1224static const unsigned char alt_8[] =
1225 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1226/* nopw 0L(%[re]ax,%[re]ax,1) */
1227static const unsigned char alt_9[] =
1228 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1229/* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1230static const unsigned char alt_10[] =
1231 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
3ae729d5
L		 1232/* data16 nopw %cs:0L(%eax,%eax,1) */
1233static const unsigned char alt_11[] =
1234 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
62a02d25
L		 1235/* 32-bit and 64-bit NOPs patterns. */
1236static const unsigned char *const alt_patt[] = {
1237 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
3ae729d5 1238 alt_9, alt_10, alt_11
62a02d25
L		 1239};
1240
1241/* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1242 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1243
1244static void
1245i386_output_nops (char *where, const unsigned char *const *patt,
1246 int count, int max_single_nop_size)
1247
1248{
3ae729d5
L		 1249 /* Place the longer NOP first. */
1250 int last;
1251 int offset;
1252 const unsigned char *nops = patt[max_single_nop_size - 1];
1253
1254 /* Use the smaller one if the requsted one isn't available. */
1255 if (nops == NULL)
62a02d25 1256 {
3ae729d5
L		 1257 max_single_nop_size--;
1258 nops = patt[max_single_nop_size - 1];
62a02d25
L		 1259 }
1260
3ae729d5
L		 1261 last = count % max_single_nop_size;
1262
1263 count -= last;
1264 for (offset = 0; offset < count; offset += max_single_nop_size)
1265 memcpy (where + offset, nops, max_single_nop_size);
1266
1267 if (last)
1268 {
1269 nops = patt[last - 1];
1270 if (nops == NULL)
1271 {
1272 /* Use the smaller one plus one-byte NOP if the needed one
1273 isn't available. */
1274 last--;
1275 nops = patt[last - 1];
1276 memcpy (where + offset, nops, last);
1277 where[offset + last] = *patt[0];
1278 }
1279 else
1280 memcpy (where + offset, nops, last);
1281 }
62a02d25
L		 1282}
1283
3ae729d5
L		 1284static INLINE int
1285fits_in_imm7 (offsetT num)
1286{
1287 return (num & 0x7f) == num;
1288}
1289
1290static INLINE int
1291fits_in_imm31 (offsetT num)
1292{
1293 return (num & 0x7fffffff) == num;
1294}
62a02d25
L		 1295
1296/* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1297 single NOP instruction LIMIT. */
1298
1299void
3ae729d5 1300i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
62a02d25 1301{
3ae729d5 1302 const unsigned char *const *patt = NULL;
62a02d25 1303 int max_single_nop_size;
3ae729d5
L		 1304 /* Maximum number of NOPs before switching to jump over NOPs. */
1305 int max_number_of_nops;
62a02d25 1306
3ae729d5 1307 switch (fragP->fr_type)
62a02d25 1308 {
3ae729d5
L		 1309 case rs_fill_nop:
1310 case rs_align_code:
1311 break;
1312 default:
62a02d25
L		 1313 return;
1314 }
1315
ccc9c027
L		 1316 /* We need to decide which NOP sequence to use for 32bit and
1317 64bit. When -mtune= is used:
4eed87de 1318
76bc74dc
L		 1319 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1320 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1321 2. For the rest, alt_patt will be used.
1322
1323 When -mtune= isn't used, alt_patt will be used if
22109423 1324 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1325 be used.
ccc9c027
L		 1326
1327 When -march= or .arch is used, we can't use anything beyond
1328 cpu_arch_isa_flags. */
1329
1330 if (flag_code == CODE_16BIT)
1331 {
3ae729d5
L		 1332 patt = f16_patt;
1333 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1334 /* Limit number of NOPs to 2 in 16-bit mode. */
1335 max_number_of_nops = 2;
252b5132 1336 }
33fef721 1337 else
ccc9c027 1338 {
fbf3f584 1339 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1340 {
1341 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1342 switch (cpu_arch_tune)
1343 {
1344 case PROCESSOR_UNKNOWN:
1345 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1346 optimize with nops. */
1347 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1348 patt = alt_patt;
ccc9c027
L		 1349 else
1350 patt = f32_patt;
1351 break;
ccc9c027
L		 1352 case PROCESSOR_PENTIUM4:
1353 case PROCESSOR_NOCONA:
ef05d495 1354 case PROCESSOR_CORE:
76bc74dc 1355 case PROCESSOR_CORE2:
bd5295b2 1356 case PROCESSOR_COREI7:
3632d14b 1357 case PROCESSOR_L1OM:
7a9068fe 1358 case PROCESSOR_K1OM:
76bc74dc 1359 case PROCESSOR_GENERIC64:
ccc9c027
L		 1360 case PROCESSOR_K6:
1361 case PROCESSOR_ATHLON:
1362 case PROCESSOR_K8:
4eed87de 1363 case PROCESSOR_AMDFAM10:
8aedb9fe 1364 case PROCESSOR_BD:
029f3522 1365 case PROCESSOR_ZNVER:
7b458c12 1366 case PROCESSOR_BT:
80b8656c 1367 patt = alt_patt;
ccc9c027 1368 break;
76bc74dc 1369 case PROCESSOR_I386:
ccc9c027
L		 1370 case PROCESSOR_I486:
1371 case PROCESSOR_PENTIUM:
2dde1948 1372 case PROCESSOR_PENTIUMPRO:
81486035 1373 case PROCESSOR_IAMCU:
ccc9c027
L		 1374 case PROCESSOR_GENERIC32:
1375 patt = f32_patt;
1376 break;
4eed87de 1377 }
ccc9c027
L		 1378 }
1379 else
1380 {
fbf3f584 1381 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1382 {
1383 case PROCESSOR_UNKNOWN:
e6a14101 1384 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1385 PROCESSOR_UNKNOWN. */
1386 abort ();
1387 break;
1388
76bc74dc 1389 case PROCESSOR_I386:
ccc9c027
L		 1390 case PROCESSOR_I486:
1391 case PROCESSOR_PENTIUM:
81486035 1392 case PROCESSOR_IAMCU:
ccc9c027
L		 1393 case PROCESSOR_K6:
1394 case PROCESSOR_ATHLON:
1395 case PROCESSOR_K8:
4eed87de 1396 case PROCESSOR_AMDFAM10:
8aedb9fe 1397 case PROCESSOR_BD:
029f3522 1398 case PROCESSOR_ZNVER:
7b458c12 1399 case PROCESSOR_BT:
ccc9c027
L		 1400 case PROCESSOR_GENERIC32:
1401 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1402 with nops. */
1403 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1404 patt = alt_patt;
ccc9c027
L		 1405 else
1406 patt = f32_patt;
1407 break;
76bc74dc
L		 1408 case PROCESSOR_PENTIUMPRO:
1409 case PROCESSOR_PENTIUM4:
1410 case PROCESSOR_NOCONA:
1411 case PROCESSOR_CORE:
ef05d495 1412 case PROCESSOR_CORE2:
bd5295b2 1413 case PROCESSOR_COREI7:
3632d14b 1414 case PROCESSOR_L1OM:
7a9068fe 1415 case PROCESSOR_K1OM:
22109423 1416 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1417 patt = alt_patt;
ccc9c027
L		 1418 else
1419 patt = f32_patt;
1420 break;
1421 case PROCESSOR_GENERIC64:
80b8656c 1422 patt = alt_patt;
ccc9c027 1423 break;
4eed87de 1424 }
ccc9c027
L		 1425 }
1426
76bc74dc
L		 1427 if (patt == f32_patt)
1428 {
3ae729d5
L		 1429 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1430 /* Limit number of NOPs to 2 for older processors. */
1431 max_number_of_nops = 2;
76bc74dc
L		 1432 }
1433 else
1434 {
3ae729d5
L		 1435 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1436 /* Limit number of NOPs to 7 for newer processors. */
1437 max_number_of_nops = 7;
1438 }
1439 }
1440
1441 if (limit == 0)
1442 limit = max_single_nop_size;
1443
1444 if (fragP->fr_type == rs_fill_nop)
1445 {
1446 /* Output NOPs for .nop directive. */
1447 if (limit > max_single_nop_size)
1448 {
1449 as_bad_where (fragP->fr_file, fragP->fr_line,
1450 _("invalid single nop size: %d "
1451 "(expect within [0, %d])"),
1452 limit, max_single_nop_size);
1453 return;
1454 }
1455 }
1456 else
1457 fragP->fr_var = count;
1458
1459 if ((count / max_single_nop_size) > max_number_of_nops)
1460 {
1461 /* Generate jump over NOPs. */
1462 offsetT disp = count - 2;
1463 if (fits_in_imm7 (disp))
1464 {
1465 /* Use "jmp disp8" if possible. */
1466 count = disp;
1467 where[0] = jump_disp8[0];
1468 where[1] = count;
1469 where += 2;
1470 }
1471 else
1472 {
1473 unsigned int size_of_jump;
1474
1475 if (flag_code == CODE_16BIT)
1476 {
1477 where[0] = jump16_disp32[0];
1478 where[1] = jump16_disp32[1];
1479 size_of_jump = 2;
1480 }
1481 else
1482 {
1483 where[0] = jump32_disp32[0];
1484 size_of_jump = 1;
1485 }
1486
1487 count -= size_of_jump + 4;
1488 if (!fits_in_imm31 (count))
1489 {
1490 as_bad_where (fragP->fr_file, fragP->fr_line,
1491 _("jump over nop padding out of range"));
1492 return;
1493 }
1494
1495 md_number_to_chars (where + size_of_jump, count, 4);
1496 where += size_of_jump + 4;
76bc74dc 1497 }
ccc9c027 1498 }
3ae729d5
L		 1499
1500 /* Generate multiple NOPs. */
1501 i386_output_nops (where, patt, count, limit);
252b5132
RH		 1502}
1503
c6fb90c8 1504static INLINE int
0dfbf9d7 1505operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1506{
0dfbf9d7 1507 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1508 {
1509 case 3:
0dfbf9d7 1510 if (x->array[2])
c6fb90c8 1511 return 0;
1a0670f3 1512 /* Fall through. */
c6fb90c8 1513 case 2:
0dfbf9d7 1514 if (x->array[1])
c6fb90c8 1515 return 0;
1a0670f3 1516 /* Fall through. */
c6fb90c8 1517 case 1:
0dfbf9d7 1518 return !x->array[0];
c6fb90c8
L		 1519 default:
1520 abort ();
1521 }
40fb9820
L		 1522}
1523
c6fb90c8 1524static INLINE void
0dfbf9d7 1525operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1526{
0dfbf9d7 1527 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1528 {
1529 case 3:
0dfbf9d7 1530 x->array[2] = v;
1a0670f3 1531 /* Fall through. */
c6fb90c8 1532 case 2:
0dfbf9d7 1533 x->array[1] = v;
1a0670f3 1534 /* Fall through. */
c6fb90c8 1535 case 1:
0dfbf9d7 1536 x->array[0] = v;
1a0670f3 1537 /* Fall through. */
c6fb90c8
L		 1538 break;
1539 default:
1540 abort ();
1541 }
1542}
40fb9820 1543
c6fb90c8 1544static INLINE int
0dfbf9d7
L		 1545operand_type_equal (const union i386_operand_type *x,
1546 const union i386_operand_type *y)
c6fb90c8 1547{
0dfbf9d7 1548 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1549 {
1550 case 3:
0dfbf9d7 1551 if (x->array[2] != y->array[2])
c6fb90c8 1552 return 0;
1a0670f3 1553 /* Fall through. */
c6fb90c8 1554 case 2:
0dfbf9d7 1555 if (x->array[1] != y->array[1])
c6fb90c8 1556 return 0;
1a0670f3 1557 /* Fall through. */
c6fb90c8 1558 case 1:
0dfbf9d7 1559 return x->array[0] == y->array[0];
c6fb90c8
L		 1560 break;
1561 default:
1562 abort ();
1563 }
1564}
40fb9820 1565
0dfbf9d7
L		 1566static INLINE int
1567cpu_flags_all_zero (const union i386_cpu_flags *x)
1568{
1569 switch (ARRAY_SIZE(x->array))
1570 {
53467f57
IT		 1571 case 4:
1572 if (x->array[3])
1573 return 0;
1574 /* Fall through. */
0dfbf9d7
L		 1575 case 3:
1576 if (x->array[2])
1577 return 0;
1a0670f3 1578 /* Fall through. */
0dfbf9d7
L		 1579 case 2:
1580 if (x->array[1])
1581 return 0;
1a0670f3 1582 /* Fall through. */
0dfbf9d7
L		 1583 case 1:
1584 return !x->array[0];
1585 default:
1586 abort ();
1587 }
1588}
1589
0dfbf9d7
L		 1590static INLINE int
1591cpu_flags_equal (const union i386_cpu_flags *x,
1592 const union i386_cpu_flags *y)
1593{
1594 switch (ARRAY_SIZE(x->array))
1595 {
53467f57
IT		 1596 case 4:
1597 if (x->array[3] != y->array[3])
1598 return 0;
1599 /* Fall through. */
0dfbf9d7
L		 1600 case 3:
1601 if (x->array[2] != y->array[2])
1602 return 0;
1a0670f3 1603 /* Fall through. */
0dfbf9d7
L		 1604 case 2:
1605 if (x->array[1] != y->array[1])
1606 return 0;
1a0670f3 1607 /* Fall through. */
0dfbf9d7
L		 1608 case 1:
1609 return x->array[0] == y->array[0];
1610 break;
1611 default:
1612 abort ();
1613 }
1614}
c6fb90c8
L		 1615
1616static INLINE int
1617cpu_flags_check_cpu64 (i386_cpu_flags f)
1618{
1619 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1620 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1621}
1622
c6fb90c8
L		 1623static INLINE i386_cpu_flags
1624cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1625{
c6fb90c8
L		 1626 switch (ARRAY_SIZE (x.array))
1627 {
53467f57
IT		 1628 case 4:
1629 x.array [3] &= y.array [3];
1630 /* Fall through. */
c6fb90c8
L		 1631 case 3:
1632 x.array [2] &= y.array [2];
1a0670f3 1633 /* Fall through. */
c6fb90c8
L		 1634 case 2:
1635 x.array [1] &= y.array [1];
1a0670f3 1636 /* Fall through. */
c6fb90c8
L		 1637 case 1:
1638 x.array [0] &= y.array [0];
1639 break;
1640 default:
1641 abort ();
1642 }
1643 return x;
1644}
40fb9820 1645
c6fb90c8
L		 1646static INLINE i386_cpu_flags
1647cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1648{
c6fb90c8 1649 switch (ARRAY_SIZE (x.array))
40fb9820 1650 {
53467f57
IT		 1651 case 4:
1652 x.array [3] |= y.array [3];
1653 /* Fall through. */
c6fb90c8
L		 1654 case 3:
1655 x.array [2] |= y.array [2];
1a0670f3 1656 /* Fall through. */
c6fb90c8
L		 1657 case 2:
1658 x.array [1] |= y.array [1];
1a0670f3 1659 /* Fall through. */
c6fb90c8
L		 1660 case 1:
1661 x.array [0] |= y.array [0];
40fb9820
L		 1662 break;
1663 default:
1664 abort ();
1665 }
40fb9820
L		 1666 return x;
1667}
1668
309d3373
JB		 1669static INLINE i386_cpu_flags
1670cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1671{
1672 switch (ARRAY_SIZE (x.array))
1673 {
53467f57
IT		 1674 case 4:
1675 x.array [3] &= ~y.array [3];
1676 /* Fall through. */
309d3373
JB		 1677 case 3:
1678 x.array [2] &= ~y.array [2];
1a0670f3 1679 /* Fall through. */
309d3373
JB		 1680 case 2:
1681 x.array [1] &= ~y.array [1];
1a0670f3 1682 /* Fall through. */
309d3373
JB		 1683 case 1:
1684 x.array [0] &= ~y.array [0];
1685 break;
1686 default:
1687 abort ();
1688 }
1689 return x;
1690}
1691
c0f3af97
L		 1692#define CPU_FLAGS_ARCH_MATCH 0x1
1693#define CPU_FLAGS_64BIT_MATCH 0x2
1694
c0f3af97 1695#define CPU_FLAGS_PERFECT_MATCH \
db12e14e 1696 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
c0f3af97
L		 1697
1698/* Return CPU flags match bits. */
3629bb00 1699
40fb9820 1700static int
d3ce72d0 1701cpu_flags_match (const insn_template *t)
40fb9820 1702{
c0f3af97
L		 1703 i386_cpu_flags x = t->cpu_flags;
1704 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1705
1706 x.bitfield.cpu64 = 0;
1707 x.bitfield.cpuno64 = 0;
1708
0dfbf9d7 1709 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1710 {
1711 /* This instruction is available on all archs. */
db12e14e 1712 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1713 }
3629bb00
L		 1714 else
1715 {
c0f3af97 1716 /* This instruction is available only on some archs. */
3629bb00
L		 1717 i386_cpu_flags cpu = cpu_arch_flags;
1718
ab592e75
JB		 1719 /* AVX512VL is no standalone feature - match it and then strip it. */
1720 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1721 return match;
1722 x.bitfield.cpuavx512vl = 0;
1723
3629bb00 1724 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1725 if (!cpu_flags_all_zero (&cpu))
1726 {
a5ff0eb2
L		 1727 if (x.bitfield.cpuavx)
1728 {
929f69fa 1729 /* We need to check a few extra flags with AVX. */
b9d49817
JB		 1730 if (cpu.bitfield.cpuavx
1731 && (!t->opcode_modifier.sse2avx || sse2avx)
1732 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
929f69fa 1733 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
b9d49817
JB		 1734 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1735 match |= CPU_FLAGS_ARCH_MATCH;
a5ff0eb2 1736 }
929f69fa
JB		 1737 else if (x.bitfield.cpuavx512f)
1738 {
1739 /* We need to check a few extra flags with AVX512F. */
1740 if (cpu.bitfield.cpuavx512f
1741 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1742 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1743 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1744 match |= CPU_FLAGS_ARCH_MATCH;
1745 }
a5ff0eb2 1746 else
db12e14e 1747 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1748 }
3629bb00 1749 }
c0f3af97 1750 return match;
40fb9820
L		 1751}
1752
c6fb90c8
L		 1753static INLINE i386_operand_type
1754operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1755{
c6fb90c8
L		 1756 switch (ARRAY_SIZE (x.array))
1757 {
1758 case 3:
1759 x.array [2] &= y.array [2];
1a0670f3 1760 /* Fall through. */
c6fb90c8
L		 1761 case 2:
1762 x.array [1] &= y.array [1];
1a0670f3 1763 /* Fall through. */
c6fb90c8
L		 1764 case 1:
1765 x.array [0] &= y.array [0];
1766 break;
1767 default:
1768 abort ();
1769 }
1770 return x;
40fb9820
L		 1771}
1772
73053c1f
JB		 1773static INLINE i386_operand_type
1774operand_type_and_not (i386_operand_type x, i386_operand_type y)
1775{
1776 switch (ARRAY_SIZE (x.array))
1777 {
1778 case 3:
1779 x.array [2] &= ~y.array [2];
1780 /* Fall through. */
1781 case 2:
1782 x.array [1] &= ~y.array [1];
1783 /* Fall through. */
1784 case 1:
1785 x.array [0] &= ~y.array [0];
1786 break;
1787 default:
1788 abort ();
1789 }
1790 return x;
1791}
1792
c6fb90c8
L		 1793static INLINE i386_operand_type
1794operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1795{
c6fb90c8 1796 switch (ARRAY_SIZE (x.array))
40fb9820 1797 {
c6fb90c8
L		 1798 case 3:
1799 x.array [2] |= y.array [2];
1a0670f3 1800 /* Fall through. */
c6fb90c8
L		 1801 case 2:
1802 x.array [1] |= y.array [1];
1a0670f3 1803 /* Fall through. */
c6fb90c8
L		 1804 case 1:
1805 x.array [0] |= y.array [0];
40fb9820
L		 1806 break;
1807 default:
1808 abort ();
1809 }
c6fb90c8
L		 1810 return x;
1811}
40fb9820 1812
c6fb90c8
L		 1813static INLINE i386_operand_type
1814operand_type_xor (i386_operand_type x, i386_operand_type y)
1815{
1816 switch (ARRAY_SIZE (x.array))
1817 {
1818 case 3:
1819 x.array [2] ^= y.array [2];
1a0670f3 1820 /* Fall through. */
c6fb90c8
L		 1821 case 2:
1822 x.array [1] ^= y.array [1];
1a0670f3 1823 /* Fall through. */
c6fb90c8
L		 1824 case 1:
1825 x.array [0] ^= y.array [0];
1826 break;
1827 default:
1828 abort ();
1829 }
40fb9820
L		 1830 return x;
1831}
1832
1833static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1834static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
65da13b5
L		 1835static const i386_operand_type inoutportreg
1836 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1837static const i386_operand_type reg16_inoutportreg
1838 = OPERAND_TYPE_REG16_INOUTPORTREG;
1839static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1840static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1841static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1842static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1843static const i386_operand_type anydisp
1844 = OPERAND_TYPE_ANYDISP;
40fb9820 1845static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
43234a1e 1846static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1847static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1848static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1849static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1850static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1851static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1852static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1853static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1854static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1855static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1856static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1857
1858enum operand_type
1859{
1860 reg,
40fb9820
L		 1861 imm,
1862 disp,
1863 anymem
1864};
1865
c6fb90c8 1866static INLINE int
40fb9820
L		 1867operand_type_check (i386_operand_type t, enum operand_type c)
1868{
1869 switch (c)
1870 {
1871 case reg:
dc821c5f 1872 return t.bitfield.reg;
40fb9820 1873
40fb9820
L		 1874 case imm:
1875 return (t.bitfield.imm8
1876 || t.bitfield.imm8s
1877 || t.bitfield.imm16
1878 || t.bitfield.imm32
1879 || t.bitfield.imm32s
1880 || t.bitfield.imm64);
1881
1882 case disp:
1883 return (t.bitfield.disp8
1884 || t.bitfield.disp16
1885 || t.bitfield.disp32
1886 || t.bitfield.disp32s
1887 || t.bitfield.disp64);
1888
1889 case anymem:
1890 return (t.bitfield.disp8
1891 || t.bitfield.disp16
1892 || t.bitfield.disp32
1893 || t.bitfield.disp32s
1894 || t.bitfield.disp64
1895 || t.bitfield.baseindex);
1896
1897 default:
1898 abort ();
1899 }
2cfe26b6
AM		 1900
1901 return 0;
40fb9820
L		 1902}
1903
ca0d63fe 1904/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
5c07affc
L		 1905 operand J for instruction template T. */
1906
1907static INLINE int
d3ce72d0 1908match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1909{
1910 return !((i.types[j].bitfield.byte
1911 && !t->operand_types[j].bitfield.byte)
1912 || (i.types[j].bitfield.word
1913 && !t->operand_types[j].bitfield.word)
1914 || (i.types[j].bitfield.dword
1915 && !t->operand_types[j].bitfield.dword)
1916 || (i.types[j].bitfield.qword
ca0d63fe
JB		 1917 && !t->operand_types[j].bitfield.qword)
1918 || (i.types[j].bitfield.tbyte
1919 && !t->operand_types[j].bitfield.tbyte));
5c07affc
L		 1920}
1921
1b54b8d7
JB		 1922/* Return 1 if there is no conflict in SIMD register on
1923 operand J for instruction template T. */
1924
1925static INLINE int
1926match_simd_size (const insn_template *t, unsigned int j)
1927{
1928 return !((i.types[j].bitfield.xmmword
1929 && !t->operand_types[j].bitfield.xmmword)
1930 || (i.types[j].bitfield.ymmword
1931 && !t->operand_types[j].bitfield.ymmword)
1932 || (i.types[j].bitfield.zmmword
1933 && !t->operand_types[j].bitfield.zmmword));
1934}
1935
5c07affc
L		 1936/* Return 1 if there is no conflict in any size on operand J for
1937 instruction template T. */
1938
1939static INLINE int
d3ce72d0 1940match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1941{
1942 return (match_reg_size (t, j)
1943 && !((i.types[j].bitfield.unspecified
af508cb9 1944 && !i.broadcast
5c07affc
L		 1945 && !t->operand_types[j].bitfield.unspecified)
1946 || (i.types[j].bitfield.fword
1947 && !t->operand_types[j].bitfield.fword)
1b54b8d7
JB		 1948 /* For scalar opcode templates to allow register and memory
1949 operands at the same time, some special casing is needed
d6793fa1
JB		 1950 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1951 down-conversion vpmov*. */
1b54b8d7
JB		 1952 || ((t->operand_types[j].bitfield.regsimd
1953 && !t->opcode_modifier.broadcast
d6793fa1
JB		 1954 && (t->operand_types[j].bitfield.byte
1955 || t->operand_types[j].bitfield.word
1956 || t->operand_types[j].bitfield.dword
1b54b8d7
JB		 1957 || t->operand_types[j].bitfield.qword))
1958 ? (i.types[j].bitfield.xmmword
1959 || i.types[j].bitfield.ymmword
1960 || i.types[j].bitfield.zmmword)
1961 : !match_simd_size(t, j))));
5c07affc
L		 1962}
1963
1964/* Return 1 if there is no size conflict on any operands for
1965 instruction template T. */
1966
1967static INLINE int
d3ce72d0 1968operand_size_match (const insn_template *t)
5c07affc
L		 1969{
1970 unsigned int j;
1971 int match = 1;
1972
1973 /* Don't check jump instructions. */
1974 if (t->opcode_modifier.jump
1975 || t->opcode_modifier.jumpbyte
1976 || t->opcode_modifier.jumpdword
1977 || t->opcode_modifier.jumpintersegment)
1978 return match;
1979
1980 /* Check memory and accumulator operand size. */
1981 for (j = 0; j < i.operands; j++)
1982 {
1b54b8d7
JB		 1983 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1984 && t->operand_types[j].bitfield.anysize)
5c07affc
L		 1985 continue;
1986
1b54b8d7 1987 if (t->operand_types[j].bitfield.reg
dc821c5f 1988 && !match_reg_size (t, j))
5c07affc
L		 1989 {
1990 match = 0;
1991 break;
1992 }
1993
1b54b8d7
JB		 1994 if (t->operand_types[j].bitfield.regsimd
1995 && !match_simd_size (t, j))
1996 {
1997 match = 0;
1998 break;
1999 }
2000
2001 if (t->operand_types[j].bitfield.acc
2002 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
2003 {
2004 match = 0;
2005 break;
2006 }
2007
5c07affc
L		 2008 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
2009 {
2010 match = 0;
2011 break;
2012 }
2013 }
2014
891edac4 2015 if (match)
5c07affc 2016 return match;
38e314eb 2017 else if (!t->opcode_modifier.d)
891edac4
L		 2018 {
2019mismatch:
86e026a4 2020 i.error = operand_size_mismatch;
891edac4
L		 2021 return 0;
2022 }
5c07affc
L		 2023
2024 /* Check reverse. */
9c2799c2 2025 gas_assert (i.operands == 2);
5c07affc
L		 2026
2027 match = 1;
2028 for (j = 0; j < 2; j++)
2029 {
dc821c5f
JB		 2030 if ((t->operand_types[j].bitfield.reg
2031 || t->operand_types[j].bitfield.acc)
5c07affc 2032 && !match_reg_size (t, j ? 0 : 1))
891edac4 2033 goto mismatch;
5c07affc
L		 2034
2035 if (i.types[j].bitfield.mem
2036 && !match_mem_size (t, j ? 0 : 1))
891edac4 2037 goto mismatch;
5c07affc
L		 2038 }
2039
2040 return match;
2041}
2042
c6fb90c8 2043static INLINE int
40fb9820
L		 2044operand_type_match (i386_operand_type overlap,
2045 i386_operand_type given)
2046{
2047 i386_operand_type temp = overlap;
2048
2049 temp.bitfield.jumpabsolute = 0;
7d5e4556 2050 temp.bitfield.unspecified = 0;
5c07affc
L		 2051 temp.bitfield.byte = 0;
2052 temp.bitfield.word = 0;
2053 temp.bitfield.dword = 0;
2054 temp.bitfield.fword = 0;
2055 temp.bitfield.qword = 0;
2056 temp.bitfield.tbyte = 0;
2057 temp.bitfield.xmmword = 0;
c0f3af97 2058 temp.bitfield.ymmword = 0;
43234a1e 2059 temp.bitfield.zmmword = 0;
0dfbf9d7 2060 if (operand_type_all_zero (&temp))
891edac4 2061 goto mismatch;
40fb9820 2062
891edac4
L		 2063 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2064 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2065 return 1;
2066
2067mismatch:
a65babc9 2068 i.error = operand_type_mismatch;
891edac4 2069 return 0;
40fb9820
L		 2070}
2071
7d5e4556 2072/* If given types g0 and g1 are registers they must be of the same type
10c17abd
JB		 2073 unless the expected operand type register overlap is null.
2074 Memory operand size of certain SIMD instructions is also being checked
2075 here. */
40fb9820 2076
c6fb90c8 2077static INLINE int
dc821c5f 2078operand_type_register_match (i386_operand_type g0,
40fb9820 2079 i386_operand_type t0,
40fb9820
L		 2080 i386_operand_type g1,
2081 i386_operand_type t1)
2082{
10c17abd
JB		 2083 if (!g0.bitfield.reg
2084 && !g0.bitfield.regsimd
2085 && (!operand_type_check (g0, anymem)
2086 || g0.bitfield.unspecified
2087 || !t0.bitfield.regsimd))
40fb9820
L		 2088 return 1;
2089
10c17abd
JB		 2090 if (!g1.bitfield.reg
2091 && !g1.bitfield.regsimd
2092 && (!operand_type_check (g1, anymem)
2093 || g1.bitfield.unspecified
2094 || !t1.bitfield.regsimd))
40fb9820
L		 2095 return 1;
2096
dc821c5f
JB		 2097 if (g0.bitfield.byte == g1.bitfield.byte
2098 && g0.bitfield.word == g1.bitfield.word
2099 && g0.bitfield.dword == g1.bitfield.dword
10c17abd
JB		 2100 && g0.bitfield.qword == g1.bitfield.qword
2101 && g0.bitfield.xmmword == g1.bitfield.xmmword
2102 && g0.bitfield.ymmword == g1.bitfield.ymmword
2103 && g0.bitfield.zmmword == g1.bitfield.zmmword)
40fb9820
L		 2104 return 1;
2105
dc821c5f
JB		 2106 if (!(t0.bitfield.byte & t1.bitfield.byte)
2107 && !(t0.bitfield.word & t1.bitfield.word)
2108 && !(t0.bitfield.dword & t1.bitfield.dword)
10c17abd
JB		 2109 && !(t0.bitfield.qword & t1.bitfield.qword)
2110 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2111 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2112 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
891edac4
L		 2113 return 1;
2114
a65babc9 2115 i.error = register_type_mismatch;
891edac4
L		 2116
2117 return 0;
40fb9820
L		 2118}
2119
4c692bc7
JB		 2120static INLINE unsigned int
2121register_number (const reg_entry *r)
2122{
2123 unsigned int nr = r->reg_num;
2124
2125 if (r->reg_flags & RegRex)
2126 nr += 8;
2127
200cbe0f
L		 2128 if (r->reg_flags & RegVRex)
2129 nr += 16;
2130
4c692bc7
JB		 2131 return nr;
2132}
2133
252b5132 2134static INLINE unsigned int
40fb9820 2135mode_from_disp_size (i386_operand_type t)
252b5132 2136{
b5014f7a 2137 if (t.bitfield.disp8)
40fb9820
L		 2138 return 1;
2139 else if (t.bitfield.disp16
2140 || t.bitfield.disp32
2141 || t.bitfield.disp32s)
2142 return 2;
2143 else
2144 return 0;
252b5132
RH		 2145}
2146
2147static INLINE int
65879393 2148fits_in_signed_byte (addressT num)
252b5132 2149{
65879393 2150 return num + 0x80 <= 0xff;
47926f60 2151}
252b5132
RH		 2152
2153static INLINE int
65879393 2154fits_in_unsigned_byte (addressT num)
252b5132 2155{
65879393 2156 return num <= 0xff;
47926f60 2157}
252b5132
RH		 2158
2159static INLINE int
65879393 2160fits_in_unsigned_word (addressT num)
252b5132 2161{
65879393 2162 return num <= 0xffff;
47926f60 2163}
252b5132
RH		 2164
2165static INLINE int
65879393 2166fits_in_signed_word (addressT num)
252b5132 2167{
65879393 2168 return num + 0x8000 <= 0xffff;
47926f60 2169}
2a962e6d 2170
3e73aa7c 2171static INLINE int
65879393 2172fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2173{
2174#ifndef BFD64
2175 return 1;
2176#else
65879393 2177 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2178#endif
2179} /* fits_in_signed_long() */
2a962e6d 2180
3e73aa7c 2181static INLINE int
65879393 2182fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2183{
2184#ifndef BFD64
2185 return 1;
2186#else
65879393 2187 return num <= 0xffffffff;
3e73aa7c
JH		 2188#endif
2189} /* fits_in_unsigned_long() */
252b5132 2190
43234a1e 2191static INLINE int
b5014f7a 2192fits_in_disp8 (offsetT num)
43234a1e
L		 2193{
2194 int shift = i.memshift;
2195 unsigned int mask;
2196
2197 if (shift == -1)
2198 abort ();
2199
2200 mask = (1 << shift) - 1;
2201
2202 /* Return 0 if NUM isn't properly aligned. */
2203 if ((num & mask))
2204 return 0;
2205
2206 /* Check if NUM will fit in 8bit after shift. */
2207 return fits_in_signed_byte (num >> shift);
2208}
2209
a683cc34
SP		 2210static INLINE int
2211fits_in_imm4 (offsetT num)
2212{
2213 return (num & 0xf) == num;
2214}
2215
40fb9820 2216static i386_operand_type
e3bb37b5 2217smallest_imm_type (offsetT num)
252b5132 2218{
40fb9820 2219 i386_operand_type t;
7ab9ffdd 2220
0dfbf9d7 2221 operand_type_set (&t, 0);
40fb9820
L		 2222 t.bitfield.imm64 = 1;
2223
2224 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2225 {
2226 /* This code is disabled on the 486 because all the Imm1 forms
2227 in the opcode table are slower on the i486. They're the
2228 versions with the implicitly specified single-position
2229 displacement, which has another syntax if you really want to
2230 use that form. */
40fb9820
L		 2231 t.bitfield.imm1 = 1;
2232 t.bitfield.imm8 = 1;
2233 t.bitfield.imm8s = 1;
2234 t.bitfield.imm16 = 1;
2235 t.bitfield.imm32 = 1;
2236 t.bitfield.imm32s = 1;
2237 }
2238 else if (fits_in_signed_byte (num))
2239 {
2240 t.bitfield.imm8 = 1;
2241 t.bitfield.imm8s = 1;
2242 t.bitfield.imm16 = 1;
2243 t.bitfield.imm32 = 1;
2244 t.bitfield.imm32s = 1;
2245 }
2246 else if (fits_in_unsigned_byte (num))
2247 {
2248 t.bitfield.imm8 = 1;
2249 t.bitfield.imm16 = 1;
2250 t.bitfield.imm32 = 1;
2251 t.bitfield.imm32s = 1;
2252 }
2253 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2254 {
2255 t.bitfield.imm16 = 1;
2256 t.bitfield.imm32 = 1;
2257 t.bitfield.imm32s = 1;
2258 }
2259 else if (fits_in_signed_long (num))
2260 {
2261 t.bitfield.imm32 = 1;
2262 t.bitfield.imm32s = 1;
2263 }
2264 else if (fits_in_unsigned_long (num))
2265 t.bitfield.imm32 = 1;
2266
2267 return t;
47926f60 2268}
252b5132 2269
847f7ad4 2270static offsetT
e3bb37b5 2271offset_in_range (offsetT val, int size)
847f7ad4 2272{
508866be 2273 addressT mask;
ba2adb93 2274
847f7ad4
AM		 2275 switch (size)
2276 {
508866be
L		 2277 case 1: mask = ((addressT) 1 << 8) - 1; break;
2278 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2279 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2280#ifdef BFD64
2281 case 8: mask = ((addressT) 2 << 63) - 1; break;
2282#endif
47926f60 2283 default: abort ();
847f7ad4
AM		 2284 }
2285
9de868bf
L		 2286#ifdef BFD64
2287 /* If BFD64, sign extend val for 32bit address mode. */
2288 if (flag_code != CODE_64BIT
2289 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2290 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2291 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2292#endif
ba2adb93 2293
47926f60 2294 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2295 {
2296 char buf1[40], buf2[40];
2297
2298 sprint_value (buf1, val);
2299 sprint_value (buf2, val & mask);
2300 as_warn (_("%s shortened to %s"), buf1, buf2);
2301 }
2302 return val & mask;
2303}
2304
c32fa91d
L		 2305enum PREFIX_GROUP
2306{
2307 PREFIX_EXIST = 0,
2308 PREFIX_LOCK,
2309 PREFIX_REP,
04ef582a 2310 PREFIX_DS,
c32fa91d
L		 2311 PREFIX_OTHER
2312};
2313
2314/* Returns
2315 a. PREFIX_EXIST if attempting to add a prefix where one from the
2316 same class already exists.
2317 b. PREFIX_LOCK if lock prefix is added.
2318 c. PREFIX_REP if rep/repne prefix is added.
04ef582a
L		 2319 d. PREFIX_DS if ds prefix is added.
2320 e. PREFIX_OTHER if other prefix is added.
c32fa91d
L		 2321 */
2322
2323static enum PREFIX_GROUP
e3bb37b5 2324add_prefix (unsigned int prefix)
252b5132 2325{
c32fa91d 2326 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2327 unsigned int q;
252b5132 2328
29b0f896
AM		 2329 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2330 && flag_code == CODE_64BIT)
b1905489 2331 {
161a04f6
L		 2332 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2333 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2334 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2335 ret = PREFIX_EXIST;
b1905489
JB		 2336 q = REX_PREFIX;
2337 }
3e73aa7c 2338 else
b1905489
JB		 2339 {
2340 switch (prefix)
2341 {
2342 default:
2343 abort ();
2344
b1905489 2345 case DS_PREFIX_OPCODE:
04ef582a
L		 2346 ret = PREFIX_DS;
2347 /* Fall through. */
2348 case CS_PREFIX_OPCODE:
b1905489
JB		 2349 case ES_PREFIX_OPCODE:
2350 case FS_PREFIX_OPCODE:
2351 case GS_PREFIX_OPCODE:
2352 case SS_PREFIX_OPCODE:
2353 q = SEG_PREFIX;
2354 break;
2355
2356 case REPNE_PREFIX_OPCODE:
2357 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2358 q = REP_PREFIX;
2359 ret = PREFIX_REP;
2360 break;
2361
b1905489 2362 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2363 q = LOCK_PREFIX;
2364 ret = PREFIX_LOCK;
b1905489
JB		 2365 break;
2366
2367 case FWAIT_OPCODE:
2368 q = WAIT_PREFIX;
2369 break;
2370
2371 case ADDR_PREFIX_OPCODE:
2372 q = ADDR_PREFIX;
2373 break;
2374
2375 case DATA_PREFIX_OPCODE:
2376 q = DATA_PREFIX;
2377 break;
2378 }
2379 if (i.prefix[q] != 0)
c32fa91d 2380 ret = PREFIX_EXIST;
b1905489 2381 }
252b5132 2382
b1905489 2383 if (ret)
252b5132 2384 {
b1905489
JB		 2385 if (!i.prefix[q])
2386 ++i.prefixes;
2387 i.prefix[q] |= prefix;
252b5132 2388 }
b1905489
JB		 2389 else
2390 as_bad (_("same type of prefix used twice"));
252b5132 2391
252b5132
RH		 2392 return ret;
2393}
2394
2395static void
78f12dd3 2396update_code_flag (int value, int check)
eecb386c 2397{
78f12dd3
L		 2398 PRINTF_LIKE ((*as_error));
2399
1e9cc1c2 2400 flag_code = (enum flag_code) value;
40fb9820
L		 2401 if (flag_code == CODE_64BIT)
2402 {
2403 cpu_arch_flags.bitfield.cpu64 = 1;
2404 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2405 }
2406 else
2407 {
2408 cpu_arch_flags.bitfield.cpu64 = 0;
2409 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2410 }
2411 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2412 {
78f12dd3
L		 2413 if (check)
2414 as_error = as_fatal;
2415 else
2416 as_error = as_bad;
2417 (*as_error) (_("64bit mode not supported on `%s'."),
2418 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2419 }
40fb9820 2420 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2421 {
78f12dd3
L		 2422 if (check)
2423 as_error = as_fatal;
2424 else
2425 as_error = as_bad;
2426 (*as_error) (_("32bit mode not supported on `%s'."),
2427 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2428 }
eecb386c
AM		 2429 stackop_size = '\0';
2430}
2431
78f12dd3
L		 2432static void
2433set_code_flag (int value)
2434{
2435 update_code_flag (value, 0);
2436}
2437
eecb386c 2438static void
e3bb37b5 2439set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2440{
1e9cc1c2 2441 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2442 if (flag_code != CODE_16BIT)
2443 abort ();
2444 cpu_arch_flags.bitfield.cpu64 = 0;
2445 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2446 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2447}
2448
2449static void
e3bb37b5 2450set_intel_syntax (int syntax_flag)
252b5132
RH		 2451{
2452 /* Find out if register prefixing is specified. */
2453 int ask_naked_reg = 0;
2454
2455 SKIP_WHITESPACE ();
29b0f896 2456 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2457 {
d02603dc
NC		 2458 char *string;
2459 int e = get_symbol_name (&string);
252b5132 2460
47926f60 2461 if (strcmp (string, "prefix") == 0)
252b5132 2462 ask_naked_reg = 1;
47926f60 2463 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2464 ask_naked_reg = -1;
2465 else
d0b47220 2466 as_bad (_("bad argument to syntax directive."));
d02603dc 2467 (void) restore_line_pointer (e);
252b5132
RH		 2468 }
2469 demand_empty_rest_of_line ();
c3332e24 2470
252b5132
RH		 2471 intel_syntax = syntax_flag;
2472
2473 if (ask_naked_reg == 0)
f86103b7
AM		 2474 allow_naked_reg = (intel_syntax
2475 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2476 else
2477 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2478
ee86248c 2479 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2480
e4a3b5a4 2481 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2482 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2483 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2484}
2485
1efbbeb4
L		 2486static void
2487set_intel_mnemonic (int mnemonic_flag)
2488{
e1d4d893 2489 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2490}
2491
db51cc60
L		 2492static void
2493set_allow_index_reg (int flag)
2494{
2495 allow_index_reg = flag;
2496}
2497
cb19c032 2498static void
7bab8ab5 2499set_check (int what)
cb19c032 2500{
7bab8ab5
JB		 2501 enum check_kind *kind;
2502 const char *str;
2503
2504 if (what)
2505 {
2506 kind = &operand_check;
2507 str = "operand";
2508 }
2509 else
2510 {
2511 kind = &sse_check;
2512 str = "sse";
2513 }
2514
cb19c032
L		 2515 SKIP_WHITESPACE ();
2516
2517 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2518 {
d02603dc
NC		 2519 char *string;
2520 int e = get_symbol_name (&string);
cb19c032
L		 2521
2522 if (strcmp (string, "none") == 0)
7bab8ab5 2523 *kind = check_none;
cb19c032 2524 else if (strcmp (string, "warning") == 0)
7bab8ab5 2525 *kind = check_warning;
cb19c032 2526 else if (strcmp (string, "error") == 0)
7bab8ab5 2527 *kind = check_error;
cb19c032 2528 else
7bab8ab5 2529 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2530 (void) restore_line_pointer (e);
cb19c032
L		 2531 }
2532 else
7bab8ab5 2533 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2534
2535 demand_empty_rest_of_line ();
2536}
2537
8a9036a4
L		 2538static void
2539check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2540 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2541{
2542#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2543 static const char *arch;
2544
2545 /* Intel LIOM is only supported on ELF. */
2546 if (!IS_ELF)
2547 return;
2548
2549 if (!arch)
2550 {
2551 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2552 use default_arch. */
2553 arch = cpu_arch_name;
2554 if (!arch)
2555 arch = default_arch;
2556 }
2557
81486035
L		 2558 /* If we are targeting Intel MCU, we must enable it. */
2559 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2560 || new_flag.bitfield.cpuiamcu)
2561 return;
2562
3632d14b 2563 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2564 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2565 || new_flag.bitfield.cpul1om)
8a9036a4 2566 return;
76ba9986 2567
7a9068fe
L		 2568 /* If we are targeting Intel K1OM, we must enable it. */
2569 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2570 || new_flag.bitfield.cpuk1om)
2571 return;
2572
8a9036a4
L		 2573 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2574#endif
2575}
2576
e413e4e9 2577static void
e3bb37b5 2578set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2579{
47926f60 2580 SKIP_WHITESPACE ();
e413e4e9 2581
29b0f896 2582 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2583 {
d02603dc
NC		 2584 char *string;
2585 int e = get_symbol_name (&string);
91d6fa6a 2586 unsigned int j;
40fb9820 2587 i386_cpu_flags flags;
e413e4e9 2588
91d6fa6a 2589 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2590 {
91d6fa6a 2591 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2592 {
91d6fa6a 2593 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2594
5c6af06e
JB		 2595 if (*string != '.')
2596 {
91d6fa6a 2597 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2598 cpu_sub_arch_name = NULL;
91d6fa6a 2599 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2600 if (flag_code == CODE_64BIT)
2601 {
2602 cpu_arch_flags.bitfield.cpu64 = 1;
2603 cpu_arch_flags.bitfield.cpuno64 = 0;
2604 }
2605 else
2606 {
2607 cpu_arch_flags.bitfield.cpu64 = 0;
2608 cpu_arch_flags.bitfield.cpuno64 = 1;
2609 }
91d6fa6a
NC		 2610 cpu_arch_isa = cpu_arch[j].type;
2611 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2612 if (!cpu_arch_tune_set)
2613 {
2614 cpu_arch_tune = cpu_arch_isa;
2615 cpu_arch_tune_flags = cpu_arch_isa_flags;
2616 }
5c6af06e
JB		 2617 break;
2618 }
40fb9820 2619
293f5f65
L		 2620 flags = cpu_flags_or (cpu_arch_flags,
2621 cpu_arch[j].flags);
81486035 2622
5b64d091 2623 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2624 {
6305a203
L		 2625 if (cpu_sub_arch_name)
2626 {
2627 char *name = cpu_sub_arch_name;
2628 cpu_sub_arch_name = concat (name,
91d6fa6a 2629 cpu_arch[j].name,
1bf57e9f 2630 (const char *) NULL);
6305a203
L		 2631 free (name);
2632 }
2633 else
91d6fa6a 2634 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2635 cpu_arch_flags = flags;
a586129e 2636 cpu_arch_isa_flags = flags;
5c6af06e 2637 }
0089dace
L		 2638 else
2639 cpu_arch_isa_flags
2640 = cpu_flags_or (cpu_arch_isa_flags,
2641 cpu_arch[j].flags);
d02603dc 2642 (void) restore_line_pointer (e);
5c6af06e
JB		 2643 demand_empty_rest_of_line ();
2644 return;
e413e4e9
AM		 2645 }
2646 }
293f5f65
L		 2647
2648 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2649 {
33eaf5de 2650 /* Disable an ISA extension. */
293f5f65
L		 2651 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2652 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2653 {
2654 flags = cpu_flags_and_not (cpu_arch_flags,
2655 cpu_noarch[j].flags);
2656 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2657 {
2658 if (cpu_sub_arch_name)
2659 {
2660 char *name = cpu_sub_arch_name;
2661 cpu_sub_arch_name = concat (name, string,
2662 (const char *) NULL);
2663 free (name);
2664 }
2665 else
2666 cpu_sub_arch_name = xstrdup (string);
2667 cpu_arch_flags = flags;
2668 cpu_arch_isa_flags = flags;
2669 }
2670 (void) restore_line_pointer (e);
2671 demand_empty_rest_of_line ();
2672 return;
2673 }
2674
2675 j = ARRAY_SIZE (cpu_arch);
2676 }
2677
91d6fa6a 2678 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2679 as_bad (_("no such architecture: `%s'"), string);
2680
2681 *input_line_pointer = e;
2682 }
2683 else
2684 as_bad (_("missing cpu architecture"));
2685
fddf5b5b
AM		 2686 no_cond_jump_promotion = 0;
2687 if (*input_line_pointer == ','
29b0f896 2688 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2689 {
d02603dc
NC		 2690 char *string;
2691 char e;
2692
2693 ++input_line_pointer;
2694 e = get_symbol_name (&string);
fddf5b5b
AM		 2695
2696 if (strcmp (string, "nojumps") == 0)
2697 no_cond_jump_promotion = 1;
2698 else if (strcmp (string, "jumps") == 0)
2699 ;
2700 else
2701 as_bad (_("no such architecture modifier: `%s'"), string);
2702
d02603dc 2703 (void) restore_line_pointer (e);
fddf5b5b
AM		 2704 }
2705
e413e4e9
AM		 2706 demand_empty_rest_of_line ();
2707}
2708
8a9036a4
L		 2709enum bfd_architecture
2710i386_arch (void)
2711{
3632d14b 2712 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2713 {
2714 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2715 || flag_code != CODE_64BIT)
2716 as_fatal (_("Intel L1OM is 64bit ELF only"));
2717 return bfd_arch_l1om;
2718 }
7a9068fe
L		 2719 else if (cpu_arch_isa == PROCESSOR_K1OM)
2720 {
2721 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2722 || flag_code != CODE_64BIT)
2723 as_fatal (_("Intel K1OM is 64bit ELF only"));
2724 return bfd_arch_k1om;
2725 }
81486035
L		 2726 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2727 {
2728 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2729 || flag_code == CODE_64BIT)
2730 as_fatal (_("Intel MCU is 32bit ELF only"));
2731 return bfd_arch_iamcu;
2732 }
8a9036a4
L		 2733 else
2734 return bfd_arch_i386;
2735}
2736
b9d79e03 2737unsigned long
7016a5d5 2738i386_mach (void)
b9d79e03 2739{
351f65ca 2740 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2741 {
3632d14b 2742 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2743 {
351f65ca
L		 2744 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2745 || default_arch[6] != '\0')
8a9036a4
L		 2746 as_fatal (_("Intel L1OM is 64bit ELF only"));
2747 return bfd_mach_l1om;
2748 }
7a9068fe
L		 2749 else if (cpu_arch_isa == PROCESSOR_K1OM)
2750 {
2751 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2752 || default_arch[6] != '\0')
2753 as_fatal (_("Intel K1OM is 64bit ELF only"));
2754 return bfd_mach_k1om;
2755 }
351f65ca 2756 else if (default_arch[6] == '\0')
8a9036a4 2757 return bfd_mach_x86_64;
351f65ca
L		 2758 else
2759 return bfd_mach_x64_32;
8a9036a4 2760 }
5197d474
L		 2761 else if (!strcmp (default_arch, "i386")
2762 || !strcmp (default_arch, "iamcu"))
81486035
L		 2763 {
2764 if (cpu_arch_isa == PROCESSOR_IAMCU)
2765 {
2766 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2767 as_fatal (_("Intel MCU is 32bit ELF only"));
2768 return bfd_mach_i386_iamcu;
2769 }
2770 else
2771 return bfd_mach_i386_i386;
2772 }
b9d79e03 2773 else
2b5d6a91 2774 as_fatal (_("unknown architecture"));
b9d79e03 2775}
b9d79e03 2776\f
252b5132 2777void
7016a5d5 2778md_begin (void)
252b5132
RH		 2779{
2780 const char *hash_err;
2781
86fa6981
L		 2782 /* Support pseudo prefixes like {disp32}. */
2783 lex_type ['{'] = LEX_BEGIN_NAME;
2784
47926f60 2785 /* Initialize op_hash hash table. */
252b5132
RH		 2786 op_hash = hash_new ();
2787
2788 {
d3ce72d0 2789 const insn_template *optab;
29b0f896 2790 templates *core_optab;
252b5132 2791
47926f60
KH		 2792 /* Setup for loop. */
2793 optab = i386_optab;
add39d23 2794 core_optab = XNEW (templates);
252b5132
RH		 2795 core_optab->start = optab;
2796
2797 while (1)
2798 {
2799 ++optab;
2800 if (optab->name == NULL
2801 || strcmp (optab->name, (optab - 1)->name) != 0)
2802 {
2803 /* different name --> ship out current template list;
47926f60 2804 add to hash table; & begin anew. */
252b5132
RH		 2805 core_optab->end = optab;
2806 hash_err = hash_insert (op_hash,
2807 (optab - 1)->name,
5a49b8ac 2808 (void *) core_optab);
252b5132
RH		 2809 if (hash_err)
2810 {
b37df7c4 2811 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2812 (optab - 1)->name,
2813 hash_err);
2814 }
2815 if (optab->name == NULL)
2816 break;
add39d23 2817 core_optab = XNEW (templates);
252b5132
RH		 2818 core_optab->start = optab;
2819 }
2820 }
2821 }
2822
47926f60 2823 /* Initialize reg_hash hash table. */
252b5132
RH		 2824 reg_hash = hash_new ();
2825 {
29b0f896 2826 const reg_entry *regtab;
c3fe08fa 2827 unsigned int regtab_size = i386_regtab_size;
252b5132 2828
c3fe08fa 2829 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2830 {
5a49b8ac 2831 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2832 if (hash_err)
b37df7c4 2833 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2834 regtab->reg_name,
2835 hash_err);
252b5132
RH		 2836 }
2837 }
2838
47926f60 2839 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2840 {
29b0f896
AM		 2841 int c;
2842 char *p;
252b5132
RH		 2843
2844 for (c = 0; c < 256; c++)
2845 {
3882b010 2846 if (ISDIGIT (c))
252b5132
RH		 2847 {
2848 digit_chars[c] = c;
2849 mnemonic_chars[c] = c;
2850 register_chars[c] = c;
2851 operand_chars[c] = c;
2852 }
3882b010 2853 else if (ISLOWER (c))
252b5132
RH		 2854 {
2855 mnemonic_chars[c] = c;
2856 register_chars[c] = c;
2857 operand_chars[c] = c;
2858 }
3882b010 2859 else if (ISUPPER (c))
252b5132 2860 {
3882b010 2861 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2862 register_chars[c] = mnemonic_chars[c];
2863 operand_chars[c] = c;
2864 }
43234a1e 2865 else if (c == '{' || c == '}')
86fa6981
L		 2866 {
2867 mnemonic_chars[c] = c;
2868 operand_chars[c] = c;
2869 }
252b5132 2870
3882b010 2871 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2872 identifier_chars[c] = c;
2873 else if (c >= 128)
2874 {
2875 identifier_chars[c] = c;
2876 operand_chars[c] = c;
2877 }
2878 }
2879
2880#ifdef LEX_AT
2881 identifier_chars['@'] = '@';
32137342
NC		 2882#endif
2883#ifdef LEX_QM
2884 identifier_chars['?'] = '?';
2885 operand_chars['?'] = '?';
252b5132 2886#endif
252b5132 2887 digit_chars['-'] = '-';
c0f3af97 2888 mnemonic_chars['_'] = '_';
791fe849 2889 mnemonic_chars['-'] = '-';
0003779b 2890 mnemonic_chars['.'] = '.';
252b5132
RH		 2891 identifier_chars['_'] = '_';
2892 identifier_chars['.'] = '.';
2893
2894 for (p = operand_special_chars; *p != '\0'; p++)
2895 operand_chars[(unsigned char) *p] = *p;
2896 }
2897
a4447b93
RH		 2898 if (flag_code == CODE_64BIT)
2899 {
ca19b261
KT		 2900#if defined (OBJ_COFF) && defined (TE_PE)
2901 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2902 ? 32 : 16);
2903#else
a4447b93 2904 x86_dwarf2_return_column = 16;
ca19b261 2905#endif
61ff971f 2906 x86_cie_data_alignment = -8;
a4447b93
RH		 2907 }
2908 else
2909 {
2910 x86_dwarf2_return_column = 8;
2911 x86_cie_data_alignment = -4;
2912 }
252b5132
RH		 2913}
2914
2915void
e3bb37b5 2916i386_print_statistics (FILE *file)
252b5132
RH		 2917{
2918 hash_print_statistics (file, "i386 opcode", op_hash);
2919 hash_print_statistics (file, "i386 register", reg_hash);
2920}
2921\f
252b5132
RH		 2922#ifdef DEBUG386
2923
ce8a8b2f 2924/* Debugging routines for md_assemble. */
d3ce72d0 2925static void pte (insn_template *);
40fb9820 2926static void pt (i386_operand_type);
e3bb37b5
L		 2927static void pe (expressionS *);
2928static void ps (symbolS *);
252b5132
RH		 2929
2930static void
e3bb37b5 2931pi (char *line, i386_insn *x)
252b5132 2932{
09137c09 2933 unsigned int j;
252b5132
RH		 2934
2935 fprintf (stdout, "%s: template ", line);
2936 pte (&x->tm);
09f131f2
JH		 2937 fprintf (stdout, " address: base %s index %s scale %x\n",
2938 x->base_reg ? x->base_reg->reg_name : "none",
2939 x->index_reg ? x->index_reg->reg_name : "none",
2940 x->log2_scale_factor);
2941 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2942 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2943 fprintf (stdout, " sib: base %x index %x scale %x\n",
2944 x->sib.base, x->sib.index, x->sib.scale);
2945 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2946 (x->rex & REX_W) != 0,
2947 (x->rex & REX_R) != 0,
2948 (x->rex & REX_X) != 0,
2949 (x->rex & REX_B) != 0);
09137c09 2950 for (j = 0; j < x->operands; j++)
252b5132 2951 {
09137c09
SP		 2952 fprintf (stdout, " #%d: ", j + 1);
2953 pt (x->types[j]);
252b5132 2954 fprintf (stdout, "\n");
dc821c5f 2955 if (x->types[j].bitfield.reg
09137c09 2956 || x->types[j].bitfield.regmmx
1b54b8d7 2957 || x->types[j].bitfield.regsimd
09137c09
SP		 2958 || x->types[j].bitfield.sreg2
2959 || x->types[j].bitfield.sreg3
2960 || x->types[j].bitfield.control
2961 || x->types[j].bitfield.debug
2962 || x->types[j].bitfield.test)
2963 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2964 if (operand_type_check (x->types[j], imm))
2965 pe (x->op[j].imms);
2966 if (operand_type_check (x->types[j], disp))
2967 pe (x->op[j].disps);
252b5132
RH		 2968 }
2969}
2970
2971static void
d3ce72d0 2972pte (insn_template *t)
252b5132 2973{
09137c09 2974 unsigned int j;
252b5132 2975 fprintf (stdout, " %d operands ", t->operands);
47926f60 2976 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2977 if (t->extension_opcode != None)
2978 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2979 if (t->opcode_modifier.d)
252b5132 2980 fprintf (stdout, "D");
40fb9820 2981 if (t->opcode_modifier.w)
252b5132
RH		 2982 fprintf (stdout, "W");
2983 fprintf (stdout, "\n");
09137c09 2984 for (j = 0; j < t->operands; j++)
252b5132 2985 {
09137c09
SP		 2986 fprintf (stdout, " #%d type ", j + 1);
2987 pt (t->operand_types[j]);
252b5132
RH		 2988 fprintf (stdout, "\n");
2989 }
2990}
2991
2992static void
e3bb37b5 2993pe (expressionS *e)
252b5132 2994{
24eab124 2995 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2996 fprintf (stdout, " add_number %ld (%lx)\n",
2997 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2998 if (e->X_add_symbol)
2999 {
3000 fprintf (stdout, " add_symbol ");
3001 ps (e->X_add_symbol);
3002 fprintf (stdout, "\n");
3003 }
3004 if (e->X_op_symbol)
3005 {
3006 fprintf (stdout, " op_symbol ");
3007 ps (e->X_op_symbol);
3008 fprintf (stdout, "\n");
3009 }
3010}
3011
3012static void
e3bb37b5 3013ps (symbolS *s)
252b5132
RH		 3014{
3015 fprintf (stdout, "%s type %s%s",
3016 S_GET_NAME (s),
3017 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3018 segment_name (S_GET_SEGMENT (s)));
3019}
3020
7b81dfbb 3021static struct type_name
252b5132 3022 {
40fb9820
L		 3023 i386_operand_type mask;
3024 const char *name;
252b5132 3025 }
7b81dfbb 3026const type_names[] =
252b5132 3027{
40fb9820
L		 3028 { OPERAND_TYPE_REG8, "r8" },
3029 { OPERAND_TYPE_REG16, "r16" },
3030 { OPERAND_TYPE_REG32, "r32" },
3031 { OPERAND_TYPE_REG64, "r64" },
3032 { OPERAND_TYPE_IMM8, "i8" },
3033 { OPERAND_TYPE_IMM8, "i8s" },
3034 { OPERAND_TYPE_IMM16, "i16" },
3035 { OPERAND_TYPE_IMM32, "i32" },
3036 { OPERAND_TYPE_IMM32S, "i32s" },
3037 { OPERAND_TYPE_IMM64, "i64" },
3038 { OPERAND_TYPE_IMM1, "i1" },
3039 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3040 { OPERAND_TYPE_DISP8, "d8" },
3041 { OPERAND_TYPE_DISP16, "d16" },
3042 { OPERAND_TYPE_DISP32, "d32" },
3043 { OPERAND_TYPE_DISP32S, "d32s" },
3044 { OPERAND_TYPE_DISP64, "d64" },
3045 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3046 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3047 { OPERAND_TYPE_CONTROL, "control reg" },
3048 { OPERAND_TYPE_TEST, "test reg" },
3049 { OPERAND_TYPE_DEBUG, "debug reg" },
3050 { OPERAND_TYPE_FLOATREG, "FReg" },
3051 { OPERAND_TYPE_FLOATACC, "FAcc" },
3052 { OPERAND_TYPE_SREG2, "SReg2" },
3053 { OPERAND_TYPE_SREG3, "SReg3" },
3054 { OPERAND_TYPE_ACC, "Acc" },
3055 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3056 { OPERAND_TYPE_REGMMX, "rMMX" },
3057 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 3058 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 3059 { OPERAND_TYPE_REGZMM, "rZMM" },
3060 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 3061 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 3062};
3063
3064static void
40fb9820 3065pt (i386_operand_type t)
252b5132 3066{
40fb9820 3067 unsigned int j;
c6fb90c8 3068 i386_operand_type a;
252b5132 3069
40fb9820 3070 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 3071 {
3072 a = operand_type_and (t, type_names[j].mask);
0349dc08 3073 if (!operand_type_all_zero (&a))
c6fb90c8
L		 3074 fprintf (stdout, "%s, ", type_names[j].name);
3075 }
252b5132
RH		 3076 fflush (stdout);
3077}
3078
3079#endif /* DEBUG386 */
3080\f
252b5132 3081static bfd_reloc_code_real_type
3956db08 3082reloc (unsigned int size,
64e74474
AM		 3083 int pcrel,
3084 int sign,
3085 bfd_reloc_code_real_type other)
252b5132 3086{
47926f60 3087 if (other != NO_RELOC)
3956db08 3088 {
91d6fa6a 3089 reloc_howto_type *rel;
3956db08
JB		 3090
3091 if (size == 8)
3092 switch (other)
3093 {
64e74474
AM		 3094 case BFD_RELOC_X86_64_GOT32:
3095 return BFD_RELOC_X86_64_GOT64;
3096 break;
553d1284
L		 3097 case BFD_RELOC_X86_64_GOTPLT64:
3098 return BFD_RELOC_X86_64_GOTPLT64;
3099 break;
64e74474
AM		 3100 case BFD_RELOC_X86_64_PLTOFF64:
3101 return BFD_RELOC_X86_64_PLTOFF64;
3102 break;
3103 case BFD_RELOC_X86_64_GOTPC32:
3104 other = BFD_RELOC_X86_64_GOTPC64;
3105 break;
3106 case BFD_RELOC_X86_64_GOTPCREL:
3107 other = BFD_RELOC_X86_64_GOTPCREL64;
3108 break;
3109 case BFD_RELOC_X86_64_TPOFF32:
3110 other = BFD_RELOC_X86_64_TPOFF64;
3111 break;
3112 case BFD_RELOC_X86_64_DTPOFF32:
3113 other = BFD_RELOC_X86_64_DTPOFF64;
3114 break;
3115 default:
3116 break;
3956db08 3117 }
e05278af 3118
8ce3d284 3119#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 3120 if (other == BFD_RELOC_SIZE32)
3121 {
3122 if (size == 8)
1ab668bf 3123 other = BFD_RELOC_SIZE64;
8fd4256d 3124 if (pcrel)
1ab668bf
AM		 3125 {
3126 as_bad (_("there are no pc-relative size relocations"));
3127 return NO_RELOC;
3128 }
8fd4256d 3129 }
8ce3d284 3130#endif
8fd4256d 3131
e05278af 3132 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 3133 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 3134 sign = -1;
3135
91d6fa6a
NC		 3136 rel = bfd_reloc_type_lookup (stdoutput, other);
3137 if (!rel)
3956db08 3138 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 3139 else if (size != bfd_get_reloc_size (rel))
3956db08 3140 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 3141 bfd_get_reloc_size (rel),
3956db08 3142 size);
91d6fa6a 3143 else if (pcrel && !rel->pc_relative)
3956db08 3144 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 3145 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 3146 && !sign)
91d6fa6a 3147 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 3148 && sign > 0))
3956db08
JB		 3149 as_bad (_("relocated field and relocation type differ in signedness"));
3150 else
3151 return other;
3152 return NO_RELOC;
3153 }
252b5132
RH		 3154
3155 if (pcrel)
3156 {
3e73aa7c 3157 if (!sign)
3956db08 3158 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 3159 switch (size)
3160 {
3161 case 1: return BFD_RELOC_8_PCREL;
3162 case 2: return BFD_RELOC_16_PCREL;
d258b828 3163 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 3164 case 8: return BFD_RELOC_64_PCREL;
252b5132 3165 }
3956db08 3166 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3167 }
3168 else
3169 {
3956db08 3170 if (sign > 0)
e5cb08ac 3171 switch (size)
3e73aa7c
JH		 3172 {
3173 case 4: return BFD_RELOC_X86_64_32S;
3174 }
3175 else
3176 switch (size)
3177 {
3178 case 1: return BFD_RELOC_8;
3179 case 2: return BFD_RELOC_16;
3180 case 4: return BFD_RELOC_32;
3181 case 8: return BFD_RELOC_64;
3182 }
3956db08
JB		 3183 as_bad (_("cannot do %s %u byte relocation"),
3184 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3185 }
3186
0cc9e1d3 3187 return NO_RELOC;
252b5132
RH		 3188}
3189
47926f60
KH		 3190/* Here we decide which fixups can be adjusted to make them relative to
3191 the beginning of the section instead of the symbol. Basically we need
3192 to make sure that the dynamic relocations are done correctly, so in
3193 some cases we force the original symbol to be used. */
3194
252b5132 3195int
e3bb37b5 3196tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3197{
6d249963 3198#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3199 if (!IS_ELF)
31312f95
AM		 3200 return 1;
3201
a161fe53
AM		 3202 /* Don't adjust pc-relative references to merge sections in 64-bit
3203 mode. */
3204 if (use_rela_relocations
3205 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3206 && fixP->fx_pcrel)
252b5132 3207 return 0;
31312f95 3208
8d01d9a9
AJ		 3209 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3210 and changed later by validate_fix. */
3211 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3212 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3213 return 0;
3214
8fd4256d
L		 3215 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3216 for size relocations. */
3217 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3218 || fixP->fx_r_type == BFD_RELOC_SIZE64
3219 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3220 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3221 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3222 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3223 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3224 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3225 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3226 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3227 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3228 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3229 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3230 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3231 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3232 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3233 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3234 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3235 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3236 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3237 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3238 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3239 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3240 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3241 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3242 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3243 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3244 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3245 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3246 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3247 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3248 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3249 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3250 return 0;
31312f95 3251#endif
252b5132
RH		 3252 return 1;
3253}
252b5132 3254
b4cac588 3255static int
e3bb37b5 3256intel_float_operand (const char *mnemonic)
252b5132 3257{
9306ca4a
JB		 3258 /* Note that the value returned is meaningful only for opcodes with (memory)
3259 operands, hence the code here is free to improperly handle opcodes that
3260 have no operands (for better performance and smaller code). */
3261
3262 if (mnemonic[0] != 'f')
3263 return 0; /* non-math */
3264
3265 switch (mnemonic[1])
3266 {
3267 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3268 the fs segment override prefix not currently handled because no
3269 call path can make opcodes without operands get here */
3270 case 'i':
3271 return 2 /* integer op */;
3272 case 'l':
3273 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3274 return 3; /* fldcw/fldenv */
3275 break;
3276 case 'n':
3277 if (mnemonic[2] != 'o' /* fnop */)
3278 return 3; /* non-waiting control op */
3279 break;
3280 case 'r':
3281 if (mnemonic[2] == 's')
3282 return 3; /* frstor/frstpm */
3283 break;
3284 case 's':
3285 if (mnemonic[2] == 'a')
3286 return 3; /* fsave */
3287 if (mnemonic[2] == 't')
3288 {
3289 switch (mnemonic[3])
3290 {
3291 case 'c': /* fstcw */
3292 case 'd': /* fstdw */
3293 case 'e': /* fstenv */
3294 case 's': /* fsts[gw] */
3295 return 3;
3296 }
3297 }
3298 break;
3299 case 'x':
3300 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3301 return 0; /* fxsave/fxrstor are not really math ops */
3302 break;
3303 }
252b5132 3304
9306ca4a 3305 return 1;
252b5132
RH		 3306}
3307
c0f3af97
L		 3308/* Build the VEX prefix. */
3309
3310static void
d3ce72d0 3311build_vex_prefix (const insn_template *t)
c0f3af97
L		 3312{
3313 unsigned int register_specifier;
3314 unsigned int implied_prefix;
3315 unsigned int vector_length;
3316
3317 /* Check register specifier. */
3318 if (i.vex.register_specifier)
43234a1e
L		 3319 {
3320 register_specifier =
3321 ~register_number (i.vex.register_specifier) & 0xf;
3322 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3323 }
c0f3af97
L		 3324 else
3325 register_specifier = 0xf;
3326
33eaf5de 3327 /* Use 2-byte VEX prefix by swapping destination and source
fa99fab2 3328 operand. */
86fa6981
L		 3329 if (i.vec_encoding != vex_encoding_vex3
3330 && i.dir_encoding == dir_encoding_default
fa99fab2 3331 && i.operands == i.reg_operands
7f399153 3332 && i.tm.opcode_modifier.vexopcode == VEX0F
86fa6981 3333 && i.tm.opcode_modifier.load
fa99fab2
L		 3334 && i.rex == REX_B)
3335 {
3336 unsigned int xchg = i.operands - 1;
3337 union i386_op temp_op;
3338 i386_operand_type temp_type;
3339
3340 temp_type = i.types[xchg];
3341 i.types[xchg] = i.types[0];
3342 i.types[0] = temp_type;
3343 temp_op = i.op[xchg];
3344 i.op[xchg] = i.op[0];
3345 i.op[0] = temp_op;
3346
9c2799c2 3347 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3348
3349 i.rex = REX_R;
3350 xchg = i.rm.regmem;
3351 i.rm.regmem = i.rm.reg;
3352 i.rm.reg = xchg;
3353
3354 /* Use the next insn. */
3355 i.tm = t[1];
3356 }
3357
539f890d
L		 3358 if (i.tm.opcode_modifier.vex == VEXScalar)
3359 vector_length = avxscalar;
10c17abd
JB		 3360 else if (i.tm.opcode_modifier.vex == VEX256)
3361 vector_length = 1;
539f890d 3362 else
10c17abd
JB		 3363 {
3364 unsigned int op;
3365
3366 vector_length = 0;
3367 for (op = 0; op < t->operands; ++op)
3368 if (t->operand_types[op].bitfield.xmmword
3369 && t->operand_types[op].bitfield.ymmword
3370 && i.types[op].bitfield.ymmword)
3371 {
3372 vector_length = 1;
3373 break;
3374 }
3375 }
c0f3af97
L		 3376
3377 switch ((i.tm.base_opcode >> 8) & 0xff)
3378 {
3379 case 0:
3380 implied_prefix = 0;
3381 break;
3382 case DATA_PREFIX_OPCODE:
3383 implied_prefix = 1;
3384 break;
3385 case REPE_PREFIX_OPCODE:
3386 implied_prefix = 2;
3387 break;
3388 case REPNE_PREFIX_OPCODE:
3389 implied_prefix = 3;
3390 break;
3391 default:
3392 abort ();
3393 }
3394
3395 /* Use 2-byte VEX prefix if possible. */
86fa6981
L		 3396 if (i.vec_encoding != vex_encoding_vex3
3397 && i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3398 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3399 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3400 {
3401 /* 2-byte VEX prefix. */
3402 unsigned int r;
3403
3404 i.vex.length = 2;
3405 i.vex.bytes[0] = 0xc5;
3406
3407 /* Check the REX.R bit. */
3408 r = (i.rex & REX_R) ? 0 : 1;
3409 i.vex.bytes[1] = (r << 7
3410 | register_specifier << 3
3411 | vector_length << 2
3412 | implied_prefix);
3413 }
3414 else
3415 {
3416 /* 3-byte VEX prefix. */
3417 unsigned int m, w;
3418
f88c9eb0 3419 i.vex.length = 3;
f88c9eb0 3420
7f399153 3421 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3422 {
7f399153
L		 3423 case VEX0F:
3424 m = 0x1;
80de6e00 3425 i.vex.bytes[0] = 0xc4;
7f399153
L		 3426 break;
3427 case VEX0F38:
3428 m = 0x2;
80de6e00 3429 i.vex.bytes[0] = 0xc4;
7f399153
L		 3430 break;
3431 case VEX0F3A:
3432 m = 0x3;
80de6e00 3433 i.vex.bytes[0] = 0xc4;
7f399153
L		 3434 break;
3435 case XOP08:
5dd85c99
SP		 3436 m = 0x8;
3437 i.vex.bytes[0] = 0x8f;
7f399153
L		 3438 break;
3439 case XOP09:
f88c9eb0
SP		 3440 m = 0x9;
3441 i.vex.bytes[0] = 0x8f;
7f399153
L		 3442 break;
3443 case XOP0A:
f88c9eb0
SP		 3444 m = 0xa;
3445 i.vex.bytes[0] = 0x8f;
7f399153
L		 3446 break;
3447 default:
3448 abort ();
f88c9eb0 3449 }
c0f3af97 3450
c0f3af97
L		 3451 /* The high 3 bits of the second VEX byte are 1's compliment
3452 of RXB bits from REX. */
3453 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3454
3455 /* Check the REX.W bit. */
3456 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3457 if (i.tm.opcode_modifier.vexw == VEXW1)
3458 w = 1;
c0f3af97
L		 3459
3460 i.vex.bytes[2] = (w << 7
3461 | register_specifier << 3
3462 | vector_length << 2
3463 | implied_prefix);
3464 }
3465}
3466
e771e7c9
JB		 3467static INLINE bfd_boolean
3468is_evex_encoding (const insn_template *t)
3469{
3470 return t->opcode_modifier.evex
3471 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3472 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3473}
3474
43234a1e
L		 3475/* Build the EVEX prefix. */
3476
3477static void
3478build_evex_prefix (void)
3479{
3480 unsigned int register_specifier;
3481 unsigned int implied_prefix;
3482 unsigned int m, w;
3483 rex_byte vrex_used = 0;
3484
3485 /* Check register specifier. */
3486 if (i.vex.register_specifier)
3487 {
3488 gas_assert ((i.vrex & REX_X) == 0);
3489
3490 register_specifier = i.vex.register_specifier->reg_num;
3491 if ((i.vex.register_specifier->reg_flags & RegRex))
3492 register_specifier += 8;
3493 /* The upper 16 registers are encoded in the fourth byte of the
3494 EVEX prefix. */
3495 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3496 i.vex.bytes[3] = 0x8;
3497 register_specifier = ~register_specifier & 0xf;
3498 }
3499 else
3500 {
3501 register_specifier = 0xf;
3502
3503 /* Encode upper 16 vector index register in the fourth byte of
3504 the EVEX prefix. */
3505 if (!(i.vrex & REX_X))
3506 i.vex.bytes[3] = 0x8;
3507 else
3508 vrex_used |= REX_X;
3509 }
3510
3511 switch ((i.tm.base_opcode >> 8) & 0xff)
3512 {
3513 case 0:
3514 implied_prefix = 0;
3515 break;
3516 case DATA_PREFIX_OPCODE:
3517 implied_prefix = 1;
3518 break;
3519 case REPE_PREFIX_OPCODE:
3520 implied_prefix = 2;
3521 break;
3522 case REPNE_PREFIX_OPCODE:
3523 implied_prefix = 3;
3524 break;
3525 default:
3526 abort ();
3527 }
3528
3529 /* 4 byte EVEX prefix. */
3530 i.vex.length = 4;
3531 i.vex.bytes[0] = 0x62;
3532
3533 /* mmmm bits. */
3534 switch (i.tm.opcode_modifier.vexopcode)
3535 {
3536 case VEX0F:
3537 m = 1;
3538 break;
3539 case VEX0F38:
3540 m = 2;
3541 break;
3542 case VEX0F3A:
3543 m = 3;
3544 break;
3545 default:
3546 abort ();
3547 break;
3548 }
3549
3550 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3551 bits from REX. */
3552 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3553
3554 /* The fifth bit of the second EVEX byte is 1's compliment of the
3555 REX_R bit in VREX. */
3556 if (!(i.vrex & REX_R))
3557 i.vex.bytes[1] |= 0x10;
3558 else
3559 vrex_used |= REX_R;
3560
3561 if ((i.reg_operands + i.imm_operands) == i.operands)
3562 {
3563 /* When all operands are registers, the REX_X bit in REX is not
3564 used. We reuse it to encode the upper 16 registers, which is
3565 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3566 as 1's compliment. */
3567 if ((i.vrex & REX_B))
3568 {
3569 vrex_used |= REX_B;
3570 i.vex.bytes[1] &= ~0x40;
3571 }
3572 }
3573
3574 /* EVEX instructions shouldn't need the REX prefix. */
3575 i.vrex &= ~vrex_used;
3576 gas_assert (i.vrex == 0);
3577
3578 /* Check the REX.W bit. */
3579 w = (i.rex & REX_W) ? 1 : 0;
3580 if (i.tm.opcode_modifier.vexw)
3581 {
3582 if (i.tm.opcode_modifier.vexw == VEXW1)
3583 w = 1;
3584 }
3585 /* If w is not set it means we are dealing with WIG instruction. */
3586 else if (!w)
3587 {
3588 if (evexwig == evexw1)
3589 w = 1;
3590 }
3591
3592 /* Encode the U bit. */
3593 implied_prefix |= 0x4;
3594
3595 /* The third byte of the EVEX prefix. */
3596 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3597
3598 /* The fourth byte of the EVEX prefix. */
3599 /* The zeroing-masking bit. */
3600 if (i.mask && i.mask->zeroing)
3601 i.vex.bytes[3] |= 0x80;
3602
3603 /* Don't always set the broadcast bit if there is no RC. */
3604 if (!i.rounding)
3605 {
3606 /* Encode the vector length. */
3607 unsigned int vec_length;
3608
e771e7c9
JB		 3609 if (!i.tm.opcode_modifier.evex
3610 || i.tm.opcode_modifier.evex == EVEXDYN)
3611 {
3612 unsigned int op;
3613
3614 vec_length = 0;
3615 for (op = 0; op < i.tm.operands; ++op)
3616 if (i.tm.operand_types[op].bitfield.xmmword
3617 + i.tm.operand_types[op].bitfield.ymmword
3618 + i.tm.operand_types[op].bitfield.zmmword > 1)
3619 {
3620 if (i.types[op].bitfield.zmmword)
3621 i.tm.opcode_modifier.evex = EVEX512;
3622 else if (i.types[op].bitfield.ymmword)
3623 i.tm.opcode_modifier.evex = EVEX256;
3624 else if (i.types[op].bitfield.xmmword)
3625 i.tm.opcode_modifier.evex = EVEX128;
3626 else
3627 continue;
3628 break;
3629 }
3630 }
3631
43234a1e
L		 3632 switch (i.tm.opcode_modifier.evex)
3633 {
3634 case EVEXLIG: /* LL' is ignored */
3635 vec_length = evexlig << 5;
3636 break;
3637 case EVEX128:
3638 vec_length = 0 << 5;
3639 break;
3640 case EVEX256:
3641 vec_length = 1 << 5;
3642 break;
3643 case EVEX512:
3644 vec_length = 2 << 5;
3645 break;
3646 default:
3647 abort ();
3648 break;
3649 }
3650 i.vex.bytes[3] |= vec_length;
3651 /* Encode the broadcast bit. */
3652 if (i.broadcast)
3653 i.vex.bytes[3] |= 0x10;
3654 }
3655 else
3656 {
3657 if (i.rounding->type != saeonly)
3658 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3659 else
d3d3c6db 3660 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3661 }
3662
3663 if (i.mask && i.mask->mask)
3664 i.vex.bytes[3] |= i.mask->mask->reg_num;
3665}
3666
65da13b5
L		 3667static void
3668process_immext (void)
3669{
3670 expressionS *exp;
3671
4c692bc7
JB		 3672 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3673 && i.operands > 0)
65da13b5 3674 {
4c692bc7
JB		 3675 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3676 with an opcode suffix which is coded in the same place as an
3677 8-bit immediate field would be.
3678 Here we check those operands and remove them afterwards. */
65da13b5
L		 3679 unsigned int x;
3680
3681 for (x = 0; x < i.operands; x++)
4c692bc7 3682 if (register_number (i.op[x].regs) != x)
65da13b5 3683 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3684 register_prefix, i.op[x].regs->reg_name, x + 1,
3685 i.tm.name);
3686
3687 i.operands = 0;
65da13b5
L		 3688 }
3689
9916071f
AP		 3690 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3691 {
3692 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3693 suffix which is coded in the same place as an 8-bit immediate
3694 field would be.
3695 Here we check those operands and remove them afterwards. */
3696 unsigned int x;
3697
3698 if (i.operands != 3)
3699 abort();
3700
3701 for (x = 0; x < 2; x++)
3702 if (register_number (i.op[x].regs) != x)
3703 goto bad_register_operand;
3704
3705 /* Check for third operand for mwaitx/monitorx insn. */
3706 if (register_number (i.op[x].regs)
3707 != (x + (i.tm.extension_opcode == 0xfb)))
3708 {
3709bad_register_operand:
3710 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3711 register_prefix, i.op[x].regs->reg_name, x+1,
3712 i.tm.name);
3713 }
3714
3715 i.operands = 0;
3716 }
3717
c0f3af97 3718 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3719 which is coded in the same place as an 8-bit immediate field
3720 would be. Here we fake an 8-bit immediate operand from the
3721 opcode suffix stored in tm.extension_opcode.
3722
c1e679ec 3723 AVX instructions also use this encoding, for some of
c0f3af97 3724 3 argument instructions. */
65da13b5 3725
43234a1e 3726 gas_assert (i.imm_operands <= 1
7ab9ffdd 3727 && (i.operands <= 2
43234a1e 3728 || ((i.tm.opcode_modifier.vex
e771e7c9
JB		 3729 || i.tm.opcode_modifier.vexopcode
3730 || is_evex_encoding (&i.tm))
7ab9ffdd 3731 && i.operands <= 4)));
65da13b5
L		 3732
3733 exp = &im_expressions[i.imm_operands++];
3734 i.op[i.operands].imms = exp;
3735 i.types[i.operands] = imm8;
3736 i.operands++;
3737 exp->X_op = O_constant;
3738 exp->X_add_number = i.tm.extension_opcode;
3739 i.tm.extension_opcode = None;
3740}
3741
42164a71
L		 3742
3743static int
3744check_hle (void)
3745{
3746 switch (i.tm.opcode_modifier.hleprefixok)
3747 {
3748 default:
3749 abort ();
82c2def5 3750 case HLEPrefixNone:
165de32a
L		 3751 as_bad (_("invalid instruction `%s' after `%s'"),
3752 i.tm.name, i.hle_prefix);
42164a71 3753 return 0;
82c2def5 3754 case HLEPrefixLock:
42164a71
L		 3755 if (i.prefix[LOCK_PREFIX])
3756 return 1;
165de32a 3757 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3758 return 0;
82c2def5 3759 case HLEPrefixAny:
42164a71 3760 return 1;
82c2def5 3761 case HLEPrefixRelease:
42164a71
L		 3762 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3763 {
3764 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3765 i.tm.name);
3766 return 0;
3767 }
3768 if (i.mem_operands == 0
3769 || !operand_type_check (i.types[i.operands - 1], anymem))
3770 {
3771 as_bad (_("memory destination needed for instruction `%s'"
3772 " after `xrelease'"), i.tm.name);
3773 return 0;
3774 }
3775 return 1;
3776 }
3777}
3778
b6f8c7c4
L		 3779/* Try the shortest encoding by shortening operand size. */
3780
3781static void
3782optimize_encoding (void)
3783{
3784 int j;
3785
3786 if (optimize_for_space
3787 && i.reg_operands == 1
3788 && i.imm_operands == 1
3789 && !i.types[1].bitfield.byte
3790 && i.op[0].imms->X_op == O_constant
3791 && fits_in_imm7 (i.op[0].imms->X_add_number)
3792 && ((i.tm.base_opcode == 0xa8
3793 && i.tm.extension_opcode == None)
3794 || (i.tm.base_opcode == 0xf6
3795 && i.tm.extension_opcode == 0x0)))
3796 {
3797 /* Optimize: -Os:
3798 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3799 */
3800 unsigned int base_regnum = i.op[1].regs->reg_num;
3801 if (flag_code == CODE_64BIT || base_regnum < 4)
3802 {
3803 i.types[1].bitfield.byte = 1;
3804 /* Ignore the suffix. */
3805 i.suffix = 0;
3806 if (base_regnum >= 4
3807 && !(i.op[1].regs->reg_flags & RegRex))
3808 {
3809 /* Handle SP, BP, SI and DI registers. */
3810 if (i.types[1].bitfield.word)
3811 j = 16;
3812 else if (i.types[1].bitfield.dword)
3813 j = 32;
3814 else
3815 j = 48;
3816 i.op[1].regs -= j;
3817 }
3818 }
3819 }
3820 else if (flag_code == CODE_64BIT
d3d50934
L		 3821 && ((i.types[1].bitfield.qword
3822 && i.reg_operands == 1
b6f8c7c4
L		 3823 && i.imm_operands == 1
3824 && i.op[0].imms->X_op == O_constant
3825 && ((i.tm.base_opcode == 0xb0
3826 && i.tm.extension_opcode == None
3827 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3828 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3829 && (((i.tm.base_opcode == 0x24
3830 || i.tm.base_opcode == 0xa8)
3831 && i.tm.extension_opcode == None)
3832 || (i.tm.base_opcode == 0x80
3833 && i.tm.extension_opcode == 0x4)
3834 || ((i.tm.base_opcode == 0xf6
3835 || i.tm.base_opcode == 0xc6)
3836 && i.tm.extension_opcode == 0x0)))))
d3d50934
L		 3837 || (i.types[0].bitfield.qword
3838 && ((i.reg_operands == 2
3839 && i.op[0].regs == i.op[1].regs
3840 && ((i.tm.base_opcode == 0x30
3841 || i.tm.base_opcode == 0x28)
3842 && i.tm.extension_opcode == None))
3843 || (i.reg_operands == 1
3844 && i.operands == 1
3845 && i.tm.base_opcode == 0x30
3846 && i.tm.extension_opcode == None)))))
b6f8c7c4
L		 3847 {
3848 /* Optimize: -O:
3849 andq $imm31, %r64 -> andl $imm31, %r32
3850 testq $imm31, %r64 -> testl $imm31, %r32
3851 xorq %r64, %r64 -> xorl %r32, %r32
3852 subq %r64, %r64 -> subl %r32, %r32
3853 movq $imm31, %r64 -> movl $imm31, %r32
3854 movq $imm32, %r64 -> movl $imm32, %r32
3855 */
3856 i.tm.opcode_modifier.norex64 = 1;
3857 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3858 {
3859 /* Handle
3860 movq $imm31, %r64 -> movl $imm31, %r32
3861 movq $imm32, %r64 -> movl $imm32, %r32
3862 */
3863 i.tm.operand_types[0].bitfield.imm32 = 1;
3864 i.tm.operand_types[0].bitfield.imm32s = 0;
3865 i.tm.operand_types[0].bitfield.imm64 = 0;
3866 i.types[0].bitfield.imm32 = 1;
3867 i.types[0].bitfield.imm32s = 0;
3868 i.types[0].bitfield.imm64 = 0;
3869 i.types[1].bitfield.dword = 1;
3870 i.types[1].bitfield.qword = 0;
3871 if (i.tm.base_opcode == 0xc6)
3872 {
3873 /* Handle
3874 movq $imm31, %r64 -> movl $imm31, %r32
3875 */
3876 i.tm.base_opcode = 0xb0;
3877 i.tm.extension_opcode = None;
3878 i.tm.opcode_modifier.shortform = 1;
3879 i.tm.opcode_modifier.modrm = 0;
3880 }
3881 }
3882 }
3883 else if (optimize > 1
3884 && i.reg_operands == 3
3885 && i.op[0].regs == i.op[1].regs
3886 && !i.types[2].bitfield.xmmword
3887 && (i.tm.opcode_modifier.vex
7a69eac3 3888 || ((!i.mask || i.mask->zeroing)
b6f8c7c4 3889 && !i.rounding
e771e7c9 3890 && is_evex_encoding (&i.tm)
80c34c38
L		 3891 && (i.vec_encoding != vex_encoding_evex
3892 || i.tm.cpu_flags.bitfield.cpuavx512vl
0089dace 3893 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
b6f8c7c4
L		 3894 && ((i.tm.base_opcode == 0x55
3895 || i.tm.base_opcode == 0x6655
3896 || i.tm.base_opcode == 0x66df
3897 || i.tm.base_opcode == 0x57
3898 || i.tm.base_opcode == 0x6657
8305403a
L		 3899 || i.tm.base_opcode == 0x66ef
3900 || i.tm.base_opcode == 0x66f8
3901 || i.tm.base_opcode == 0x66f9
3902 || i.tm.base_opcode == 0x66fa
3903 || i.tm.base_opcode == 0x66fb)
b6f8c7c4
L		 3904 && i.tm.extension_opcode == None))
3905 {
3906 /* Optimize: -O2:
8305403a
L		 3907 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3908 vpsubq and vpsubw:
b6f8c7c4
L		 3909 EVEX VOP %zmmM, %zmmM, %zmmN
3910 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3911 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3912 EVEX VOP %ymmM, %ymmM, %ymmN
3913 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3914 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3915 VEX VOP %ymmM, %ymmM, %ymmN
3916 -> VEX VOP %xmmM, %xmmM, %xmmN
3917 VOP, one of vpandn and vpxor:
3918 VEX VOP %ymmM, %ymmM, %ymmN
3919 -> VEX VOP %xmmM, %xmmM, %xmmN
3920 VOP, one of vpandnd and vpandnq:
3921 EVEX VOP %zmmM, %zmmM, %zmmN
3922 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3923 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3924 EVEX VOP %ymmM, %ymmM, %ymmN
3925 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3926 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3927 VOP, one of vpxord and vpxorq:
3928 EVEX VOP %zmmM, %zmmM, %zmmN
3929 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3930 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3931 EVEX VOP %ymmM, %ymmM, %ymmN
3932 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3933 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3934 */
e771e7c9 3935 if (is_evex_encoding (&i.tm))
b6f8c7c4 3936 {
0089dace 3937 if (i.vec_encoding == vex_encoding_evex)
b6f8c7c4
L		 3938 i.tm.opcode_modifier.evex = EVEX128;
3939 else
3940 {
3941 i.tm.opcode_modifier.vex = VEX128;
3942 i.tm.opcode_modifier.vexw = VEXW0;
3943 i.tm.opcode_modifier.evex = 0;
3944 }
3945 }
3946 else
3947 i.tm.opcode_modifier.vex = VEX128;
3948
3949 if (i.tm.opcode_modifier.vex)
3950 for (j = 0; j < 3; j++)
3951 {
3952 i.types[j].bitfield.xmmword = 1;
3953 i.types[j].bitfield.ymmword = 0;
3954 }
3955 }
3956}
3957
252b5132
RH		 3958/* This is the guts of the machine-dependent assembler. LINE points to a
3959 machine dependent instruction. This function is supposed to emit
3960 the frags/bytes it assembles to. */
3961
3962void
65da13b5 3963md_assemble (char *line)
252b5132 3964{
40fb9820 3965 unsigned int j;
83b16ac6 3966 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3967 const insn_template *t;
252b5132 3968
47926f60 3969 /* Initialize globals. */
252b5132
RH		 3970 memset (&i, '\0', sizeof (i));
3971 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3972 i.reloc[j] = NO_RELOC;
252b5132
RH		 3973 memset (disp_expressions, '\0', sizeof (disp_expressions));
3974 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3975 save_stack_p = save_stack;
252b5132
RH		 3976
3977 /* First parse an instruction mnemonic & call i386_operand for the operands.
3978 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3979 start of a (possibly prefixed) mnemonic. */
252b5132 3980
29b0f896
AM		 3981 line = parse_insn (line, mnemonic);
3982 if (line == NULL)
3983 return;
83b16ac6 3984 mnem_suffix = i.suffix;
252b5132 3985
29b0f896 3986 line = parse_operands (line, mnemonic);
ee86248c 3987 this_operand = -1;
8325cc63
JB		 3988 xfree (i.memop1_string);
3989 i.memop1_string = NULL;
29b0f896
AM		 3990 if (line == NULL)
3991 return;
252b5132 3992
29b0f896
AM		 3993 /* Now we've parsed the mnemonic into a set of templates, and have the
3994 operands at hand. */
3995
3996 /* All intel opcodes have reversed operands except for "bound" and
3997 "enter". We also don't reverse intersegment "jmp" and "call"
3998 instructions with 2 immediate operands so that the immediate segment
050dfa73 3999 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 4000 if (intel_syntax
4001 && i.operands > 1
29b0f896 4002 && (strcmp (mnemonic, "bound") != 0)
30123838 4003 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 4004 && !(operand_type_check (i.types[0], imm)
4005 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 4006 swap_operands ();
4007
ec56d5c0
JB		 4008 /* The order of the immediates should be reversed
4009 for 2 immediates extrq and insertq instructions */
4010 if (i.imm_operands == 2
4011 && (strcmp (mnemonic, "extrq") == 0
4012 || strcmp (mnemonic, "insertq") == 0))
4013 swap_2_operands (0, 1);
4014
29b0f896
AM		 4015 if (i.imm_operands)
4016 optimize_imm ();
4017
b300c311
L		 4018 /* Don't optimize displacement for movabs since it only takes 64bit
4019 displacement. */
4020 if (i.disp_operands
a501d77e 4021 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 4022 && (flag_code != CODE_64BIT
4023 || strcmp (mnemonic, "movabs") != 0))
4024 optimize_disp ();
29b0f896
AM		 4025
4026 /* Next, we find a template that matches the given insn,
4027 making sure the overlap of the given operands types is consistent
4028 with the template operand types. */
252b5132 4029
83b16ac6 4030 if (!(t = match_template (mnem_suffix)))
29b0f896 4031 return;
252b5132 4032
7bab8ab5 4033 if (sse_check != check_none
81f8a913 4034 && !i.tm.opcode_modifier.noavx
6e3e5c9e 4035 && !i.tm.cpu_flags.bitfield.cpuavx
daf50ae7
L		 4036 && (i.tm.cpu_flags.bitfield.cpusse
4037 || i.tm.cpu_flags.bitfield.cpusse2
4038 || i.tm.cpu_flags.bitfield.cpusse3
4039 || i.tm.cpu_flags.bitfield.cpussse3
4040 || i.tm.cpu_flags.bitfield.cpusse4_1
6e3e5c9e
JB		 4041 || i.tm.cpu_flags.bitfield.cpusse4_2
4042 || i.tm.cpu_flags.bitfield.cpupclmul
4043 || i.tm.cpu_flags.bitfield.cpuaes
4044 || i.tm.cpu_flags.bitfield.cpugfni))
daf50ae7 4045 {
7bab8ab5 4046 (sse_check == check_warning
daf50ae7
L		 4047 ? as_warn
4048 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4049 }
4050
321fd21e
L		 4051 /* Zap movzx and movsx suffix. The suffix has been set from
4052 "word ptr" or "byte ptr" on the source operand in Intel syntax
4053 or extracted from mnemonic in AT&T syntax. But we'll use
4054 the destination register to choose the suffix for encoding. */
4055 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 4056 {
321fd21e
L		 4057 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4058 there is no suffix, the default will be byte extension. */
4059 if (i.reg_operands != 2
4060 && !i.suffix
7ab9ffdd 4061 && intel_syntax)
321fd21e
L		 4062 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4063
4064 i.suffix = 0;
cd61ebfe 4065 }
24eab124 4066
40fb9820 4067 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 4068 if (!add_prefix (FWAIT_OPCODE))
4069 return;
252b5132 4070
d5de92cf
L		 4071 /* Check if REP prefix is OK. */
4072 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4073 {
4074 as_bad (_("invalid instruction `%s' after `%s'"),
4075 i.tm.name, i.rep_prefix);
4076 return;
4077 }
4078
c1ba0266
L		 4079 /* Check for lock without a lockable instruction. Destination operand
4080 must be memory unless it is xchg (0x86). */
c32fa91d
L		 4081 if (i.prefix[LOCK_PREFIX]
4082 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 4083 || i.mem_operands == 0
4084 || (i.tm.base_opcode != 0x86
4085 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 4086 {
4087 as_bad (_("expecting lockable instruction after `lock'"));
4088 return;
4089 }
4090
42164a71 4091 /* Check if HLE prefix is OK. */
165de32a 4092 if (i.hle_prefix && !check_hle ())
42164a71
L		 4093 return;
4094
7e8b059b
L		 4095 /* Check BND prefix. */
4096 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4097 as_bad (_("expecting valid branch instruction after `bnd'"));
4098
04ef582a 4099 /* Check NOTRACK prefix. */
9fef80d6
L		 4100 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4101 as_bad (_("expecting indirect branch instruction after `notrack'"));
04ef582a 4102
327e8c42
JB		 4103 if (i.tm.cpu_flags.bitfield.cpumpx)
4104 {
4105 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4106 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4107 else if (flag_code != CODE_16BIT
4108 ? i.prefix[ADDR_PREFIX]
4109 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4110 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4111 }
7e8b059b
L		 4112
4113 /* Insert BND prefix. */
4114 if (add_bnd_prefix
4115 && i.tm.opcode_modifier.bndprefixok
4116 && !i.prefix[BND_PREFIX])
4117 add_prefix (BND_PREFIX_OPCODE);
4118
29b0f896 4119 /* Check string instruction segment overrides. */
40fb9820 4120 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 4121 {
4122 if (!check_string ())
5dd0794d 4123 return;
fc0763e6 4124 i.disp_operands = 0;
29b0f896 4125 }
5dd0794d 4126
b6f8c7c4
L		 4127 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4128 optimize_encoding ();
4129
29b0f896
AM		 4130 if (!process_suffix ())
4131 return;
e413e4e9 4132
bc0844ae
L		 4133 /* Update operand types. */
4134 for (j = 0; j < i.operands; j++)
4135 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4136
29b0f896
AM		 4137 /* Make still unresolved immediate matches conform to size of immediate
4138 given in i.suffix. */
4139 if (!finalize_imm ())
4140 return;
252b5132 4141
40fb9820 4142 if (i.types[0].bitfield.imm1)
29b0f896 4143 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 4144
9afe6eb8
L		 4145 /* We only need to check those implicit registers for instructions
4146 with 3 operands or less. */
4147 if (i.operands <= 3)
4148 for (j = 0; j < i.operands; j++)
4149 if (i.types[j].bitfield.inoutportreg
4150 || i.types[j].bitfield.shiftcount
1b54b8d7 4151 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
9afe6eb8 4152 i.reg_operands--;
40fb9820 4153
c0f3af97
L		 4154 /* ImmExt should be processed after SSE2AVX. */
4155 if (!i.tm.opcode_modifier.sse2avx
4156 && i.tm.opcode_modifier.immext)
65da13b5 4157 process_immext ();
252b5132 4158
29b0f896
AM		 4159 /* For insns with operands there are more diddles to do to the opcode. */
4160 if (i.operands)
4161 {
4162 if (!process_operands ())
4163 return;
4164 }
40fb9820 4165 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 4166 {
4167 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4168 as_warn (_("translating to `%sp'"), i.tm.name);
4169 }
252b5132 4170
e771e7c9
JB		 4171 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4172 || is_evex_encoding (&i.tm))
9e5e5283
L		 4173 {
4174 if (flag_code == CODE_16BIT)
4175 {
4176 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4177 i.tm.name);
4178 return;
4179 }
c0f3af97 4180
9e5e5283
L		 4181 if (i.tm.opcode_modifier.vex)
4182 build_vex_prefix (t);
4183 else
4184 build_evex_prefix ();
4185 }
43234a1e 4186
5dd85c99
SP		 4187 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4188 instructions may define INT_OPCODE as well, so avoid this corner
4189 case for those instructions that use MODRM. */
4190 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 4191 && !i.tm.opcode_modifier.modrm
4192 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 4193 {
4194 i.tm.base_opcode = INT3_OPCODE;
4195 i.imm_operands = 0;
4196 }
252b5132 4197
40fb9820
L		 4198 if ((i.tm.opcode_modifier.jump
4199 || i.tm.opcode_modifier.jumpbyte
4200 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 4201 && i.op[0].disps->X_op == O_constant)
4202 {
4203 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4204 the absolute address given by the constant. Since ix86 jumps and
4205 calls are pc relative, we need to generate a reloc. */
4206 i.op[0].disps->X_add_symbol = &abs_symbol;
4207 i.op[0].disps->X_op = O_symbol;
4208 }
252b5132 4209
40fb9820 4210 if (i.tm.opcode_modifier.rex64)
161a04f6 4211 i.rex |= REX_W;
252b5132 4212
29b0f896
AM		 4213 /* For 8 bit registers we need an empty rex prefix. Also if the
4214 instruction already has a prefix, we need to convert old
4215 registers to new ones. */
773f551c 4216
dc821c5f 4217 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
29b0f896 4218 && (i.op[0].regs->reg_flags & RegRex64) != 0)
dc821c5f 4219 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
29b0f896 4220 && (i.op[1].regs->reg_flags & RegRex64) != 0)
dc821c5f
JB		 4221 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4222 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
29b0f896
AM		 4223 && i.rex != 0))
4224 {
4225 int x;
726c5dcd 4226
29b0f896
AM		 4227 i.rex |= REX_OPCODE;
4228 for (x = 0; x < 2; x++)
4229 {
4230 /* Look for 8 bit operand that uses old registers. */
dc821c5f 4231 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
29b0f896 4232 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 4233 {
29b0f896
AM		 4234 /* In case it is "hi" register, give up. */
4235 if (i.op[x].regs->reg_num > 3)
a540244d 4236 as_bad (_("can't encode register '%s%s' in an "
4eed87de 4237 "instruction requiring REX prefix."),
a540244d 4238 register_prefix, i.op[x].regs->reg_name);
773f551c 4239
29b0f896
AM		 4240 /* Otherwise it is equivalent to the extended register.
4241 Since the encoding doesn't change this is merely
4242 cosmetic cleanup for debug output. */
4243
4244 i.op[x].regs = i.op[x].regs + 8;
773f551c 4245 }
29b0f896
AM		 4246 }
4247 }
773f551c 4248
6b6b6807
L		 4249 if (i.rex == 0 && i.rex_encoding)
4250 {
4251 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4252 that uses legacy register. If it is "hi" register, don't add
4253 the REX_OPCODE byte. */
4254 int x;
4255 for (x = 0; x < 2; x++)
4256 if (i.types[x].bitfield.reg
4257 && i.types[x].bitfield.byte
4258 && (i.op[x].regs->reg_flags & RegRex64) == 0
4259 && i.op[x].regs->reg_num > 3)
4260 {
4261 i.rex_encoding = FALSE;
4262 break;
4263 }
4264
4265 if (i.rex_encoding)
4266 i.rex = REX_OPCODE;
4267 }
4268
7ab9ffdd 4269 if (i.rex != 0)
29b0f896
AM		 4270 add_prefix (REX_OPCODE | i.rex);
4271
4272 /* We are ready to output the insn. */
4273 output_insn ();
4274}
4275
4276static char *
e3bb37b5 4277parse_insn (char *line, char *mnemonic)
29b0f896
AM		 4278{
4279 char *l = line;
4280 char *token_start = l;
4281 char *mnem_p;
5c6af06e 4282 int supported;
d3ce72d0 4283 const insn_template *t;
b6169b20 4284 char *dot_p = NULL;
29b0f896 4285
29b0f896
AM		 4286 while (1)
4287 {
4288 mnem_p = mnemonic;
4289 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4290 {
b6169b20
L		 4291 if (*mnem_p == '.')
4292 dot_p = mnem_p;
29b0f896
AM		 4293 mnem_p++;
4294 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 4295 {
29b0f896
AM		 4296 as_bad (_("no such instruction: `%s'"), token_start);
4297 return NULL;
4298 }
4299 l++;
4300 }
4301 if (!is_space_char (*l)
4302 && *l != END_OF_INSN
e44823cf
JB		 4303 && (intel_syntax
4304 || (*l != PREFIX_SEPARATOR
4305 && *l != ',')))
29b0f896
AM		 4306 {
4307 as_bad (_("invalid character %s in mnemonic"),
4308 output_invalid (*l));
4309 return NULL;
4310 }
4311 if (token_start == l)
4312 {
e44823cf 4313 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 4314 as_bad (_("expecting prefix; got nothing"));
4315 else
4316 as_bad (_("expecting mnemonic; got nothing"));
4317 return NULL;
4318 }
45288df1 4319
29b0f896 4320 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 4321 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 4322
29b0f896
AM		 4323 if (*l != END_OF_INSN
4324 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4325 && current_templates
40fb9820 4326 && current_templates->start->opcode_modifier.isprefix)
29b0f896 4327 {
c6fb90c8 4328 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 4329 {
4330 as_bad ((flag_code != CODE_64BIT
4331 ? _("`%s' is only supported in 64-bit mode")
4332 : _("`%s' is not supported in 64-bit mode")),
4333 current_templates->start->name);
4334 return NULL;
4335 }
29b0f896
AM		 4336 /* If we are in 16-bit mode, do not allow addr16 or data16.
4337 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 4338 if ((current_templates->start->opcode_modifier.size16
4339 || current_templates->start->opcode_modifier.size32)
29b0f896 4340 && flag_code != CODE_64BIT
40fb9820 4341 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 4342 ^ (flag_code == CODE_16BIT)))
4343 {
4344 as_bad (_("redundant %s prefix"),
4345 current_templates->start->name);
4346 return NULL;
45288df1 4347 }
86fa6981 4348 if (current_templates->start->opcode_length == 0)
29b0f896 4349 {
86fa6981
L		 4350 /* Handle pseudo prefixes. */
4351 switch (current_templates->start->base_opcode)
4352 {
4353 case 0x0:
4354 /* {disp8} */
4355 i.disp_encoding = disp_encoding_8bit;
4356 break;
4357 case 0x1:
4358 /* {disp32} */
4359 i.disp_encoding = disp_encoding_32bit;
4360 break;
4361 case 0x2:
4362 /* {load} */
4363 i.dir_encoding = dir_encoding_load;
4364 break;
4365 case 0x3:
4366 /* {store} */
4367 i.dir_encoding = dir_encoding_store;
4368 break;
4369 case 0x4:
4370 /* {vex2} */
4371 i.vec_encoding = vex_encoding_vex2;
4372 break;
4373 case 0x5:
4374 /* {vex3} */
4375 i.vec_encoding = vex_encoding_vex3;
4376 break;
4377 case 0x6:
4378 /* {evex} */
4379 i.vec_encoding = vex_encoding_evex;
4380 break;
6b6b6807
L		 4381 case 0x7:
4382 /* {rex} */
4383 i.rex_encoding = TRUE;
4384 break;
b6f8c7c4
L		 4385 case 0x8:
4386 /* {nooptimize} */
4387 i.no_optimize = TRUE;
4388 break;
86fa6981
L		 4389 default:
4390 abort ();
4391 }
4392 }
4393 else
4394 {
4395 /* Add prefix, checking for repeated prefixes. */
4e9ac44a 4396 switch (add_prefix (current_templates->start->base_opcode))
86fa6981 4397 {
4e9ac44a
L		 4398 case PREFIX_EXIST:
4399 return NULL;
4400 case PREFIX_DS:
d777820b 4401 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4e9ac44a
L		 4402 i.notrack_prefix = current_templates->start->name;
4403 break;
4404 case PREFIX_REP:
4405 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4406 i.hle_prefix = current_templates->start->name;
4407 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4408 i.bnd_prefix = current_templates->start->name;
4409 else
4410 i.rep_prefix = current_templates->start->name;
4411 break;
4412 default:
4413 break;
86fa6981 4414 }
29b0f896
AM		 4415 }
4416 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4417 token_start = ++l;
4418 }
4419 else
4420 break;
4421 }
45288df1 4422
30a55f88 4423 if (!current_templates)
b6169b20 4424 {
f8a5c266
L		 4425 /* Check if we should swap operand or force 32bit displacement in
4426 encoding. */
30a55f88 4427 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
86fa6981 4428 i.dir_encoding = dir_encoding_store;
8d63c93e 4429 else if (mnem_p - 3 == dot_p
a501d77e
L		 4430 && dot_p[1] == 'd'
4431 && dot_p[2] == '8')
4432 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4433 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4434 && dot_p[1] == 'd'
4435 && dot_p[2] == '3'
4436 && dot_p[3] == '2')
a501d77e 4437 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4438 else
4439 goto check_suffix;
4440 mnem_p = dot_p;
4441 *dot_p = '\0';
d3ce72d0 4442 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4443 }
4444
29b0f896
AM		 4445 if (!current_templates)
4446 {
b6169b20 4447check_suffix:
29b0f896
AM		 4448 /* See if we can get a match by trimming off a suffix. */
4449 switch (mnem_p[-1])
4450 {
4451 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 4452 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4453 i.suffix = SHORT_MNEM_SUFFIX;
4454 else
1a0670f3 4455 /* Fall through. */
29b0f896
AM		 4456 case BYTE_MNEM_SUFFIX:
4457 case QWORD_MNEM_SUFFIX:
4458 i.suffix = mnem_p[-1];
4459 mnem_p[-1] = '\0';
d3ce72d0
NC		 4460 current_templates = (const templates *) hash_find (op_hash,
4461 mnemonic);
29b0f896
AM		 4462 break;
4463 case SHORT_MNEM_SUFFIX:
4464 case LONG_MNEM_SUFFIX:
4465 if (!intel_syntax)
4466 {
4467 i.suffix = mnem_p[-1];
4468 mnem_p[-1] = '\0';
d3ce72d0
NC		 4469 current_templates = (const templates *) hash_find (op_hash,
4470 mnemonic);
29b0f896
AM		 4471 }
4472 break;
252b5132 4473
29b0f896
AM		 4474 /* Intel Syntax. */
4475 case 'd':
4476 if (intel_syntax)
4477 {
9306ca4a 4478 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 4479 i.suffix = SHORT_MNEM_SUFFIX;
4480 else
4481 i.suffix = LONG_MNEM_SUFFIX;
4482 mnem_p[-1] = '\0';
d3ce72d0
NC		 4483 current_templates = (const templates *) hash_find (op_hash,
4484 mnemonic);
29b0f896
AM		 4485 }
4486 break;
4487 }
4488 if (!current_templates)
4489 {
4490 as_bad (_("no such instruction: `%s'"), token_start);
4491 return NULL;
4492 }
4493 }
252b5132 4494
40fb9820
L		 4495 if (current_templates->start->opcode_modifier.jump
4496 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4497 {
4498 /* Check for a branch hint. We allow ",pt" and ",pn" for
4499 predict taken and predict not taken respectively.
4500 I'm not sure that branch hints actually do anything on loop
4501 and jcxz insns (JumpByte) for current Pentium4 chips. They
4502 may work in the future and it doesn't hurt to accept them
4503 now. */
4504 if (l[0] == ',' && l[1] == 'p')
4505 {
4506 if (l[2] == 't')
4507 {
4508 if (!add_prefix (DS_PREFIX_OPCODE))
4509 return NULL;
4510 l += 3;
4511 }
4512 else if (l[2] == 'n')
4513 {
4514 if (!add_prefix (CS_PREFIX_OPCODE))
4515 return NULL;
4516 l += 3;
4517 }
4518 }
4519 }
4520 /* Any other comma loses. */
4521 if (*l == ',')
4522 {
4523 as_bad (_("invalid character %s in mnemonic"),
4524 output_invalid (*l));
4525 return NULL;
4526 }
252b5132 4527
29b0f896 4528 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4529 supported = 0;
4530 for (t = current_templates->start; t < current_templates->end; ++t)
4531 {
c0f3af97
L		 4532 supported |= cpu_flags_match (t);
4533 if (supported == CPU_FLAGS_PERFECT_MATCH)
548d0ee6
JB		 4534 {
4535 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4536 as_warn (_("use .code16 to ensure correct addressing mode"));
3629bb00 4537
548d0ee6
JB		 4538 return l;
4539 }
29b0f896 4540 }
3629bb00 4541
548d0ee6
JB		 4542 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4543 as_bad (flag_code == CODE_64BIT
4544 ? _("`%s' is not supported in 64-bit mode")
4545 : _("`%s' is only supported in 64-bit mode"),
4546 current_templates->start->name);
4547 else
4548 as_bad (_("`%s' is not supported on `%s%s'"),
4549 current_templates->start->name,
4550 cpu_arch_name ? cpu_arch_name : default_arch,
4551 cpu_sub_arch_name ? cpu_sub_arch_name : "");
252b5132 4552
548d0ee6 4553 return NULL;
29b0f896 4554}
252b5132 4555
29b0f896 4556static char *
e3bb37b5 4557parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4558{
4559 char *token_start;
3138f287 4560
29b0f896
AM		 4561 /* 1 if operand is pending after ','. */
4562 unsigned int expecting_operand = 0;
252b5132 4563
29b0f896
AM		 4564 /* Non-zero if operand parens not balanced. */
4565 unsigned int paren_not_balanced;
4566
4567 while (*l != END_OF_INSN)
4568 {
4569 /* Skip optional white space before operand. */
4570 if (is_space_char (*l))
4571 ++l;
d02603dc 4572 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4573 {
4574 as_bad (_("invalid character %s before operand %d"),
4575 output_invalid (*l),
4576 i.operands + 1);
4577 return NULL;
4578 }
d02603dc 4579 token_start = l; /* After white space. */
29b0f896
AM		 4580 paren_not_balanced = 0;
4581 while (paren_not_balanced || *l != ',')
4582 {
4583 if (*l == END_OF_INSN)
4584 {
4585 if (paren_not_balanced)
4586 {
4587 if (!intel_syntax)
4588 as_bad (_("unbalanced parenthesis in operand %d."),
4589 i.operands + 1);
4590 else
4591 as_bad (_("unbalanced brackets in operand %d."),
4592 i.operands + 1);
4593 return NULL;
4594 }
4595 else
4596 break; /* we are done */
4597 }
d02603dc 4598 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4599 {
4600 as_bad (_("invalid character %s in operand %d"),
4601 output_invalid (*l),
4602 i.operands + 1);
4603 return NULL;
4604 }
4605 if (!intel_syntax)
4606 {
4607 if (*l == '(')
4608 ++paren_not_balanced;
4609 if (*l == ')')
4610 --paren_not_balanced;
4611 }
4612 else
4613 {
4614 if (*l == '[')
4615 ++paren_not_balanced;
4616 if (*l == ']')
4617 --paren_not_balanced;
4618 }
4619 l++;
4620 }
4621 if (l != token_start)
4622 { /* Yes, we've read in another operand. */
4623 unsigned int operand_ok;
4624 this_operand = i.operands++;
4625 if (i.operands > MAX_OPERANDS)
4626 {
4627 as_bad (_("spurious operands; (%d operands/instruction max)"),
4628 MAX_OPERANDS);
4629 return NULL;
4630 }
9d46ce34 4631 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4632 /* Now parse operand adding info to 'i' as we go along. */
4633 END_STRING_AND_SAVE (l);
4634
4635 if (intel_syntax)
4636 operand_ok =
4637 i386_intel_operand (token_start,
4638 intel_float_operand (mnemonic));
4639 else
a7619375 4640 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4641
4642 RESTORE_END_STRING (l);
4643 if (!operand_ok)
4644 return NULL;
4645 }
4646 else
4647 {
4648 if (expecting_operand)
4649 {
4650 expecting_operand_after_comma:
4651 as_bad (_("expecting operand after ','; got nothing"));
4652 return NULL;
4653 }
4654 if (*l == ',')
4655 {
4656 as_bad (_("expecting operand before ','; got nothing"));
4657 return NULL;
4658 }
4659 }
7f3f1ea2 4660
29b0f896
AM		 4661 /* Now *l must be either ',' or END_OF_INSN. */
4662 if (*l == ',')
4663 {
4664 if (*++l == END_OF_INSN)
4665 {
4666 /* Just skip it, if it's \n complain. */
4667 goto expecting_operand_after_comma;
4668 }
4669 expecting_operand = 1;
4670 }
4671 }
4672 return l;
4673}
7f3f1ea2 4674
050dfa73 4675static void
4d456e3d 4676swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4677{
4678 union i386_op temp_op;
40fb9820 4679 i386_operand_type temp_type;
050dfa73 4680 enum bfd_reloc_code_real temp_reloc;
4eed87de 4681
050dfa73
MM		 4682 temp_type = i.types[xchg2];
4683 i.types[xchg2] = i.types[xchg1];
4684 i.types[xchg1] = temp_type;
4685 temp_op = i.op[xchg2];
4686 i.op[xchg2] = i.op[xchg1];
4687 i.op[xchg1] = temp_op;
4688 temp_reloc = i.reloc[xchg2];
4689 i.reloc[xchg2] = i.reloc[xchg1];
4690 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4691
4692 if (i.mask)
4693 {
4694 if (i.mask->operand == xchg1)
4695 i.mask->operand = xchg2;
4696 else if (i.mask->operand == xchg2)
4697 i.mask->operand = xchg1;
4698 }
4699 if (i.broadcast)
4700 {
4701 if (i.broadcast->operand == xchg1)
4702 i.broadcast->operand = xchg2;
4703 else if (i.broadcast->operand == xchg2)
4704 i.broadcast->operand = xchg1;
4705 }
4706 if (i.rounding)
4707 {
4708 if (i.rounding->operand == xchg1)
4709 i.rounding->operand = xchg2;
4710 else if (i.rounding->operand == xchg2)
4711 i.rounding->operand = xchg1;
4712 }
050dfa73
MM		 4713}
4714
29b0f896 4715static void
e3bb37b5 4716swap_operands (void)
29b0f896 4717{
b7c61d9a 4718 switch (i.operands)
050dfa73 4719 {
c0f3af97 4720 case 5:
b7c61d9a 4721 case 4:
4d456e3d 4722 swap_2_operands (1, i.operands - 2);
1a0670f3 4723 /* Fall through. */
b7c61d9a
L		 4724 case 3:
4725 case 2:
4d456e3d 4726 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4727 break;
4728 default:
4729 abort ();
29b0f896 4730 }
29b0f896
AM		 4731
4732 if (i.mem_operands == 2)
4733 {
4734 const seg_entry *temp_seg;
4735 temp_seg = i.seg[0];
4736 i.seg[0] = i.seg[1];
4737 i.seg[1] = temp_seg;
4738 }
4739}
252b5132 4740
29b0f896
AM		 4741/* Try to ensure constant immediates are represented in the smallest
4742 opcode possible. */
4743static void
e3bb37b5 4744optimize_imm (void)
29b0f896
AM		 4745{
4746 char guess_suffix = 0;
4747 int op;
252b5132 4748
29b0f896
AM		 4749 if (i.suffix)
4750 guess_suffix = i.suffix;
4751 else if (i.reg_operands)
4752 {
4753 /* Figure out a suffix from the last register operand specified.
4754 We can't do this properly yet, ie. excluding InOutPortReg,
4755 but the following works for instructions with immediates.
4756 In any case, we can't set i.suffix yet. */
4757 for (op = i.operands; --op >= 0;)
dc821c5f 4758 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
7ab9ffdd 4759 {
40fb9820
L		 4760 guess_suffix = BYTE_MNEM_SUFFIX;
4761 break;
4762 }
dc821c5f 4763 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
252b5132 4764 {
40fb9820
L		 4765 guess_suffix = WORD_MNEM_SUFFIX;
4766 break;
4767 }
dc821c5f 4768 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
40fb9820
L		 4769 {
4770 guess_suffix = LONG_MNEM_SUFFIX;
4771 break;
4772 }
dc821c5f 4773 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
40fb9820
L		 4774 {
4775 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4776 break;
252b5132 4777 }
29b0f896
AM		 4778 }
4779 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4780 guess_suffix = WORD_MNEM_SUFFIX;
4781
4782 for (op = i.operands; --op >= 0;)
40fb9820 4783 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4784 {
4785 switch (i.op[op].imms->X_op)
252b5132 4786 {
29b0f896
AM		 4787 case O_constant:
4788 /* If a suffix is given, this operand may be shortened. */
4789 switch (guess_suffix)
252b5132 4790 {
29b0f896 4791 case LONG_MNEM_SUFFIX:
40fb9820
L		 4792 i.types[op].bitfield.imm32 = 1;
4793 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4794 break;
4795 case WORD_MNEM_SUFFIX:
40fb9820
L		 4796 i.types[op].bitfield.imm16 = 1;
4797 i.types[op].bitfield.imm32 = 1;
4798 i.types[op].bitfield.imm32s = 1;
4799 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4800 break;
4801 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4802 i.types[op].bitfield.imm8 = 1;
4803 i.types[op].bitfield.imm8s = 1;
4804 i.types[op].bitfield.imm16 = 1;
4805 i.types[op].bitfield.imm32 = 1;
4806 i.types[op].bitfield.imm32s = 1;
4807 i.types[op].bitfield.imm64 = 1;
29b0f896 4808 break;
252b5132 4809 }
252b5132 4810
29b0f896
AM		 4811 /* If this operand is at most 16 bits, convert it
4812 to a signed 16 bit number before trying to see
4813 whether it will fit in an even smaller size.
4814 This allows a 16-bit operand such as $0xffe0 to
4815 be recognised as within Imm8S range. */
40fb9820 4816 if ((i.types[op].bitfield.imm16)
29b0f896 4817 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4818 {
29b0f896
AM		 4819 i.op[op].imms->X_add_number =
4820 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4821 }
a28def75
L		 4822#ifdef BFD64
4823 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4824 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4825 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4826 == 0))
4827 {
4828 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4829 ^ ((offsetT) 1 << 31))
4830 - ((offsetT) 1 << 31));
4831 }
a28def75 4832#endif
40fb9820 4833 i.types[op]
c6fb90c8
L		 4834 = operand_type_or (i.types[op],
4835 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4836
29b0f896
AM		 4837 /* We must avoid matching of Imm32 templates when 64bit
4838 only immediate is available. */
4839 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4840 i.types[op].bitfield.imm32 = 0;
29b0f896 4841 break;
252b5132 4842
29b0f896
AM		 4843 case O_absent:
4844 case O_register:
4845 abort ();
4846
4847 /* Symbols and expressions. */
4848 default:
9cd96992
JB		 4849 /* Convert symbolic operand to proper sizes for matching, but don't
4850 prevent matching a set of insns that only supports sizes other
4851 than those matching the insn suffix. */
4852 {
40fb9820 4853 i386_operand_type mask, allowed;
d3ce72d0 4854 const insn_template *t;
9cd96992 4855
0dfbf9d7
L		 4856 operand_type_set (&mask, 0);
4857 operand_type_set (&allowed, 0);
40fb9820 4858
4eed87de
AM		 4859 for (t = current_templates->start;
4860 t < current_templates->end;
4861 ++t)
c6fb90c8
L		 4862 allowed = operand_type_or (allowed,
4863 t->operand_types[op]);
9cd96992
JB		 4864 switch (guess_suffix)
4865 {
4866 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4867 mask.bitfield.imm64 = 1;
4868 mask.bitfield.imm32s = 1;
9cd96992
JB		 4869 break;
4870 case LONG_MNEM_SUFFIX:
40fb9820 4871 mask.bitfield.imm32 = 1;
9cd96992
JB		 4872 break;
4873 case WORD_MNEM_SUFFIX:
40fb9820 4874 mask.bitfield.imm16 = 1;
9cd96992
JB		 4875 break;
4876 case BYTE_MNEM_SUFFIX:
40fb9820 4877 mask.bitfield.imm8 = 1;
9cd96992
JB		 4878 break;
4879 default:
9cd96992
JB		 4880 break;
4881 }
c6fb90c8 4882 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4883 if (!operand_type_all_zero (&allowed))
c6fb90c8 4884 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4885 }
29b0f896 4886 break;
252b5132 4887 }
29b0f896
AM		 4888 }
4889}
47926f60 4890
29b0f896
AM		 4891/* Try to use the smallest displacement type too. */
4892static void
e3bb37b5 4893optimize_disp (void)
29b0f896
AM		 4894{
4895 int op;
3e73aa7c 4896
29b0f896 4897 for (op = i.operands; --op >= 0;)
40fb9820 4898 if (operand_type_check (i.types[op], disp))
252b5132 4899 {
b300c311 4900 if (i.op[op].disps->X_op == O_constant)
252b5132 4901 {
91d6fa6a 4902 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4903
40fb9820 4904 if (i.types[op].bitfield.disp16
91d6fa6a 4905 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4906 {
4907 /* If this operand is at most 16 bits, convert
4908 to a signed 16 bit number and don't use 64bit
4909 displacement. */
91d6fa6a 4910 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4911 i.types[op].bitfield.disp64 = 0;
b300c311 4912 }
a28def75
L		 4913#ifdef BFD64
4914 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4915 if (i.types[op].bitfield.disp32
91d6fa6a 4916 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4917 {
4918 /* If this operand is at most 32 bits, convert
4919 to a signed 32 bit number and don't use 64bit
4920 displacement. */
91d6fa6a
NC		 4921 op_disp &= (((offsetT) 2 << 31) - 1);
4922 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4923 i.types[op].bitfield.disp64 = 0;
b300c311 4924 }
a28def75 4925#endif
91d6fa6a 4926 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4927 {
40fb9820
L		 4928 i.types[op].bitfield.disp8 = 0;
4929 i.types[op].bitfield.disp16 = 0;
4930 i.types[op].bitfield.disp32 = 0;
4931 i.types[op].bitfield.disp32s = 0;
4932 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4933 i.op[op].disps = 0;
4934 i.disp_operands--;
4935 }
4936 else if (flag_code == CODE_64BIT)
4937 {
91d6fa6a 4938 if (fits_in_signed_long (op_disp))
28a9d8f5 4939 {
40fb9820
L		 4940 i.types[op].bitfield.disp64 = 0;
4941 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4942 }
0e1147d9 4943 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4944 && fits_in_unsigned_long (op_disp))
40fb9820 4945 i.types[op].bitfield.disp32 = 1;
b300c311 4946 }
40fb9820
L		 4947 if ((i.types[op].bitfield.disp32
4948 || i.types[op].bitfield.disp32s
4949 || i.types[op].bitfield.disp16)
b5014f7a 4950 && fits_in_disp8 (op_disp))
40fb9820 4951 i.types[op].bitfield.disp8 = 1;
252b5132 4952 }
67a4f2b7
AO		 4953 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4954 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4955 {
4956 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4957 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4958 i.types[op].bitfield.disp8 = 0;
4959 i.types[op].bitfield.disp16 = 0;
4960 i.types[op].bitfield.disp32 = 0;
4961 i.types[op].bitfield.disp32s = 0;
4962 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4963 }
4964 else
b300c311 4965 /* We only support 64bit displacement on constants. */
40fb9820 4966 i.types[op].bitfield.disp64 = 0;
252b5132 4967 }
29b0f896
AM		 4968}
4969
6c30d220
L		 4970/* Check if operands are valid for the instruction. */
4971
4972static int
4973check_VecOperands (const insn_template *t)
4974{
43234a1e 4975 unsigned int op;
e2195274
JB		 4976 i386_cpu_flags cpu;
4977 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
4978
4979 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
4980 any one operand are implicity requiring AVX512VL support if the actual
4981 operand size is YMMword or XMMword. Since this function runs after
4982 template matching, there's no need to check for YMMword/XMMword in
4983 the template. */
4984 cpu = cpu_flags_and (t->cpu_flags, avx512);
4985 if (!cpu_flags_all_zero (&cpu)
4986 && !t->cpu_flags.bitfield.cpuavx512vl
4987 && !cpu_arch_flags.bitfield.cpuavx512vl)
4988 {
4989 for (op = 0; op < t->operands; ++op)
4990 {
4991 if (t->operand_types[op].bitfield.zmmword
4992 && (i.types[op].bitfield.ymmword
4993 || i.types[op].bitfield.xmmword))
4994 {
4995 i.error = unsupported;
4996 return 1;
4997 }
4998 }
4999 }
43234a1e 5000
6c30d220
L		 5001 /* Without VSIB byte, we can't have a vector register for index. */
5002 if (!t->opcode_modifier.vecsib
5003 && i.index_reg
1b54b8d7
JB		 5004 && (i.index_reg->reg_type.bitfield.xmmword
5005 || i.index_reg->reg_type.bitfield.ymmword
5006 || i.index_reg->reg_type.bitfield.zmmword))
6c30d220
L		 5007 {
5008 i.error = unsupported_vector_index_register;
5009 return 1;
5010 }
5011
ad8ecc81
MZ		 5012 /* Check if default mask is allowed. */
5013 if (t->opcode_modifier.nodefmask
5014 && (!i.mask || i.mask->mask->reg_num == 0))
5015 {
5016 i.error = no_default_mask;
5017 return 1;
5018 }
5019
7bab8ab5
JB		 5020 /* For VSIB byte, we need a vector register for index, and all vector
5021 registers must be distinct. */
5022 if (t->opcode_modifier.vecsib)
5023 {
5024 if (!i.index_reg
6c30d220 5025 || !((t->opcode_modifier.vecsib == VecSIB128
1b54b8d7 5026 && i.index_reg->reg_type.bitfield.xmmword)
6c30d220 5027 || (t->opcode_modifier.vecsib == VecSIB256
1b54b8d7 5028 && i.index_reg->reg_type.bitfield.ymmword)
43234a1e 5029 || (t->opcode_modifier.vecsib == VecSIB512
1b54b8d7 5030 && i.index_reg->reg_type.bitfield.zmmword)))
7bab8ab5
JB		 5031 {
5032 i.error = invalid_vsib_address;
5033 return 1;
5034 }
5035
43234a1e
L		 5036 gas_assert (i.reg_operands == 2 || i.mask);
5037 if (i.reg_operands == 2 && !i.mask)
5038 {
1b54b8d7
JB		 5039 gas_assert (i.types[0].bitfield.regsimd);
5040 gas_assert (i.types[0].bitfield.xmmword
5041 || i.types[0].bitfield.ymmword);
5042 gas_assert (i.types[2].bitfield.regsimd);
5043 gas_assert (i.types[2].bitfield.xmmword
5044 || i.types[2].bitfield.ymmword);
43234a1e
L		 5045 if (operand_check == check_none)
5046 return 0;
5047 if (register_number (i.op[0].regs)
5048 != register_number (i.index_reg)
5049 && register_number (i.op[2].regs)
5050 != register_number (i.index_reg)
5051 && register_number (i.op[0].regs)
5052 != register_number (i.op[2].regs))
5053 return 0;
5054 if (operand_check == check_error)
5055 {
5056 i.error = invalid_vector_register_set;
5057 return 1;
5058 }
5059 as_warn (_("mask, index, and destination registers should be distinct"));
5060 }
8444f82a
MZ		 5061 else if (i.reg_operands == 1 && i.mask)
5062 {
1b54b8d7
JB		 5063 if (i.types[1].bitfield.regsimd
5064 && (i.types[1].bitfield.xmmword
5065 || i.types[1].bitfield.ymmword
5066 || i.types[1].bitfield.zmmword)
8444f82a
MZ		 5067 && (register_number (i.op[1].regs)
5068 == register_number (i.index_reg)))
5069 {
5070 if (operand_check == check_error)
5071 {
5072 i.error = invalid_vector_register_set;
5073 return 1;
5074 }
5075 if (operand_check != check_none)
5076 as_warn (_("index and destination registers should be distinct"));
5077 }
5078 }
43234a1e 5079 }
7bab8ab5 5080
43234a1e
L		 5081 /* Check if broadcast is supported by the instruction and is applied
5082 to the memory operand. */
5083 if (i.broadcast)
5084 {
8e6e0792 5085 i386_operand_type type, overlap;
43234a1e
L		 5086
5087 /* Check if specified broadcast is supported in this instruction,
c39e5b26 5088 and it's applied to memory operand of DWORD or QWORD type. */
32546502 5089 op = i.broadcast->operand;
8e6e0792 5090 if (!t->opcode_modifier.broadcast
32546502 5091 || !i.types[op].bitfield.mem
c39e5b26
JB		 5092 || (!i.types[op].bitfield.unspecified
5093 && (t->operand_types[op].bitfield.dword
5094 ? !i.types[op].bitfield.dword
5095 : !i.types[op].bitfield.qword)))
43234a1e
L		 5096 {
5097 bad_broadcast:
5098 i.error = unsupported_broadcast;
5099 return 1;
5100 }
8e6e0792
JB		 5101
5102 operand_type_set (&type, 0);
c39e5b26 5103 switch ((t->operand_types[op].bitfield.dword ? 4 : 8) * i.broadcast->type)
8e6e0792
JB		 5104 {
5105 case 8:
5106 type.bitfield.qword = 1;
5107 break;
5108 case 16:
5109 type.bitfield.xmmword = 1;
5110 break;
5111 case 32:
5112 type.bitfield.ymmword = 1;
5113 break;
5114 case 64:
5115 type.bitfield.zmmword = 1;
5116 break;
5117 default:
5118 goto bad_broadcast;
5119 }
5120
5121 overlap = operand_type_and (type, t->operand_types[op]);
5122 if (operand_type_all_zero (&overlap))
5123 goto bad_broadcast;
5124
5125 if (t->opcode_modifier.checkregsize)
5126 {
5127 unsigned int j;
5128
e2195274 5129 type.bitfield.baseindex = 1;
8e6e0792
JB		 5130 for (j = 0; j < i.operands; ++j)
5131 {
5132 if (j != op
5133 && !operand_type_register_match(i.types[j],
5134 t->operand_types[j],
5135 type,
5136 t->operand_types[op]))
5137 goto bad_broadcast;
5138 }
5139 }
43234a1e
L		 5140 }
5141 /* If broadcast is supported in this instruction, we need to check if
5142 operand of one-element size isn't specified without broadcast. */
5143 else if (t->opcode_modifier.broadcast && i.mem_operands)
5144 {
5145 /* Find memory operand. */
5146 for (op = 0; op < i.operands; op++)
5147 if (operand_type_check (i.types[op], anymem))
5148 break;
5149 gas_assert (op < i.operands);
5150 /* Check size of the memory operand. */
c39e5b26
JB		 5151 if (t->operand_types[op].bitfield.dword
5152 ? i.types[op].bitfield.dword
5153 : i.types[op].bitfield.qword)
43234a1e
L		 5154 {
5155 i.error = broadcast_needed;
5156 return 1;
5157 }
5158 }
c39e5b26
JB		 5159 else
5160 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
43234a1e
L		 5161
5162 /* Check if requested masking is supported. */
5163 if (i.mask
5164 && (!t->opcode_modifier.masking
5165 || (i.mask->zeroing
5166 && t->opcode_modifier.masking == MERGING_MASKING)))
5167 {
5168 i.error = unsupported_masking;
5169 return 1;
5170 }
5171
5172 /* Check if masking is applied to dest operand. */
5173 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5174 {
5175 i.error = mask_not_on_destination;
5176 return 1;
5177 }
5178
43234a1e
L		 5179 /* Check RC/SAE. */
5180 if (i.rounding)
5181 {
5182 if ((i.rounding->type != saeonly
5183 && !t->opcode_modifier.staticrounding)
5184 || (i.rounding->type == saeonly
5185 && (t->opcode_modifier.staticrounding
5186 || !t->opcode_modifier.sae)))
5187 {
5188 i.error = unsupported_rc_sae;
5189 return 1;
5190 }
5191 /* If the instruction has several immediate operands and one of
5192 them is rounding, the rounding operand should be the last
5193 immediate operand. */
5194 if (i.imm_operands > 1
5195 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 5196 {
43234a1e 5197 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 5198 return 1;
5199 }
6c30d220
L		 5200 }
5201
43234a1e 5202 /* Check vector Disp8 operand. */
b5014f7a
JB		 5203 if (t->opcode_modifier.disp8memshift
5204 && i.disp_encoding != disp_encoding_32bit)
43234a1e
L		 5205 {
5206 if (i.broadcast)
c39e5b26 5207 i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
43234a1e
L		 5208 else
5209 i.memshift = t->opcode_modifier.disp8memshift;
5210
5211 for (op = 0; op < i.operands; op++)
5212 if (operand_type_check (i.types[op], disp)
5213 && i.op[op].disps->X_op == O_constant)
5214 {
b5014f7a 5215 if (fits_in_disp8 (i.op[op].disps->X_add_number))
43234a1e 5216 {
b5014f7a
JB		 5217 i.types[op].bitfield.disp8 = 1;
5218 return 0;
43234a1e 5219 }
b5014f7a 5220 i.types[op].bitfield.disp8 = 0;
43234a1e
L		 5221 }
5222 }
b5014f7a
JB		 5223
5224 i.memshift = 0;
43234a1e 5225
6c30d220
L		 5226 return 0;
5227}
5228
43f3e2ee 5229/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 5230 operand types. */
5231
5232static int
5233VEX_check_operands (const insn_template *t)
5234{
86fa6981 5235 if (i.vec_encoding == vex_encoding_evex)
43234a1e 5236 {
86fa6981 5237 /* This instruction must be encoded with EVEX prefix. */
e771e7c9 5238 if (!is_evex_encoding (t))
86fa6981
L		 5239 {
5240 i.error = unsupported;
5241 return 1;
5242 }
5243 return 0;
43234a1e
L		 5244 }
5245
a683cc34 5246 if (!t->opcode_modifier.vex)
86fa6981
L		 5247 {
5248 /* This instruction template doesn't have VEX prefix. */
5249 if (i.vec_encoding != vex_encoding_default)
5250 {
5251 i.error = unsupported;
5252 return 1;
5253 }
5254 return 0;
5255 }
a683cc34
SP		 5256
5257 /* Only check VEX_Imm4, which must be the first operand. */
5258 if (t->operand_types[0].bitfield.vec_imm4)
5259 {
5260 if (i.op[0].imms->X_op != O_constant
5261 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 5262 {
a65babc9 5263 i.error = bad_imm4;
891edac4
L		 5264 return 1;
5265 }
a683cc34
SP		 5266
5267 /* Turn off Imm8 so that update_imm won't complain. */
5268 i.types[0] = vec_imm4;
5269 }
5270
5271 return 0;
5272}
5273
d3ce72d0 5274static const insn_template *
83b16ac6 5275match_template (char mnem_suffix)
29b0f896
AM		 5276{
5277 /* Points to template once we've found it. */
d3ce72d0 5278 const insn_template *t;
40fb9820 5279 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 5280 i386_operand_type overlap4;
29b0f896 5281 unsigned int found_reverse_match;
83b16ac6 5282 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 5283 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 5284 int addr_prefix_disp;
a5c311ca 5285 unsigned int j;
3629bb00 5286 unsigned int found_cpu_match;
45664ddb 5287 unsigned int check_register;
5614d22c 5288 enum i386_error specific_error = 0;
29b0f896 5289
c0f3af97
L		 5290#if MAX_OPERANDS != 5
5291# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 5292#endif
5293
29b0f896 5294 found_reverse_match = 0;
539e75ad 5295 addr_prefix_disp = -1;
40fb9820
L		 5296
5297 memset (&suffix_check, 0, sizeof (suffix_check));
e2195274
JB		 5298 if (intel_syntax && i.broadcast)
5299 /* nothing */;
5300 else if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5301 suffix_check.no_bsuf = 1;
5302 else if (i.suffix == WORD_MNEM_SUFFIX)
5303 suffix_check.no_wsuf = 1;
5304 else if (i.suffix == SHORT_MNEM_SUFFIX)
5305 suffix_check.no_ssuf = 1;
5306 else if (i.suffix == LONG_MNEM_SUFFIX)
5307 suffix_check.no_lsuf = 1;
5308 else if (i.suffix == QWORD_MNEM_SUFFIX)
5309 suffix_check.no_qsuf = 1;
5310 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 5311 suffix_check.no_ldsuf = 1;
29b0f896 5312
83b16ac6
JB		 5313 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5314 if (intel_syntax)
5315 {
5316 switch (mnem_suffix)
5317 {
5318 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5319 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5320 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5321 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5322 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5323 }
5324 }
5325
01559ecc
L		 5326 /* Must have right number of operands. */
5327 i.error = number_of_operands_mismatch;
5328
45aa61fe 5329 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 5330 {
539e75ad
L		 5331 addr_prefix_disp = -1;
5332
29b0f896
AM		 5333 if (i.operands != t->operands)
5334 continue;
5335
50aecf8c 5336 /* Check processor support. */
a65babc9 5337 i.error = unsupported;
c0f3af97
L		 5338 found_cpu_match = (cpu_flags_match (t)
5339 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 5340 if (!found_cpu_match)
5341 continue;
5342
e1d4d893 5343 /* Check AT&T mnemonic. */
a65babc9 5344 i.error = unsupported_with_intel_mnemonic;
e1d4d893 5345 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 5346 continue;
5347
e92bae62 5348 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 5349 i.error = unsupported_syntax;
5c07affc 5350 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 5351 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5352 || (intel64 && t->opcode_modifier.amd64)
5353 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 5354 continue;
5355
20592a94 5356 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 5357 i.error = invalid_instruction_suffix;
567e4e96
L		 5358 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5359 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5360 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5361 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5362 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5363 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5364 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 5365 continue;
83b16ac6
JB		 5366 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5367 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5368 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5369 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5370 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5371 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5372 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5373 continue;
29b0f896 5374
5c07affc 5375 if (!operand_size_match (t))
7d5e4556 5376 continue;
539e75ad 5377
5c07affc
L		 5378 for (j = 0; j < MAX_OPERANDS; j++)
5379 operand_types[j] = t->operand_types[j];
5380
45aa61fe
AM		 5381 /* In general, don't allow 64-bit operands in 32-bit mode. */
5382 if (i.suffix == QWORD_MNEM_SUFFIX
5383 && flag_code != CODE_64BIT
5384 && (intel_syntax
40fb9820 5385 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 5386 && !intel_float_operand (t->name))
5387 : intel_float_operand (t->name) != 2)
40fb9820 5388 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5389 && !operand_types[0].bitfield.regsimd)
40fb9820 5390 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5391 && !operand_types[t->operands > 1].bitfield.regsimd))
45aa61fe
AM		 5392 && (t->base_opcode != 0x0fc7
5393 || t->extension_opcode != 1 /* cmpxchg8b */))
5394 continue;
5395
192dc9c6
JB		 5396 /* In general, don't allow 32-bit operands on pre-386. */
5397 else if (i.suffix == LONG_MNEM_SUFFIX
5398 && !cpu_arch_flags.bitfield.cpui386
5399 && (intel_syntax
5400 ? (!t->opcode_modifier.ignoresize
5401 && !intel_float_operand (t->name))
5402 : intel_float_operand (t->name) != 2)
5403 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5404 && !operand_types[0].bitfield.regsimd)
192dc9c6 5405 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5406 && !operand_types[t->operands > 1].bitfield.regsimd)))
192dc9c6
JB		 5407 continue;
5408
29b0f896 5409 /* Do not verify operands when there are none. */
50aecf8c 5410 else
29b0f896 5411 {
c6fb90c8 5412 if (!t->operands)
2dbab7d5
L		 5413 /* We've found a match; break out of loop. */
5414 break;
29b0f896 5415 }
252b5132 5416
539e75ad
L		 5417 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5418 into Disp32/Disp16/Disp32 operand. */
5419 if (i.prefix[ADDR_PREFIX] != 0)
5420 {
40fb9820 5421 /* There should be only one Disp operand. */
539e75ad
L		 5422 switch (flag_code)
5423 {
5424 case CODE_16BIT:
40fb9820
L		 5425 for (j = 0; j < MAX_OPERANDS; j++)
5426 {
5427 if (operand_types[j].bitfield.disp16)
5428 {
5429 addr_prefix_disp = j;
5430 operand_types[j].bitfield.disp32 = 1;
5431 operand_types[j].bitfield.disp16 = 0;
5432 break;
5433 }
5434 }
539e75ad
L		 5435 break;
5436 case CODE_32BIT:
40fb9820
L		 5437 for (j = 0; j < MAX_OPERANDS; j++)
5438 {
5439 if (operand_types[j].bitfield.disp32)
5440 {
5441 addr_prefix_disp = j;
5442 operand_types[j].bitfield.disp32 = 0;
5443 operand_types[j].bitfield.disp16 = 1;
5444 break;
5445 }
5446 }
539e75ad
L		 5447 break;
5448 case CODE_64BIT:
40fb9820
L		 5449 for (j = 0; j < MAX_OPERANDS; j++)
5450 {
5451 if (operand_types[j].bitfield.disp64)
5452 {
5453 addr_prefix_disp = j;
5454 operand_types[j].bitfield.disp64 = 0;
5455 operand_types[j].bitfield.disp32 = 1;
5456 break;
5457 }
5458 }
539e75ad
L		 5459 break;
5460 }
539e75ad
L		 5461 }
5462
02a86693
L		 5463 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5464 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5465 continue;
5466
56ffb741 5467 /* We check register size if needed. */
e2195274
JB		 5468 if (t->opcode_modifier.checkregsize)
5469 {
5470 check_register = (1 << t->operands) - 1;
5471 if (i.broadcast)
5472 check_register &= ~(1 << i.broadcast->operand);
5473 }
5474 else
5475 check_register = 0;
5476
c6fb90c8 5477 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5478 switch (t->operands)
5479 {
5480 case 1:
40fb9820 5481 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5482 continue;
5483 break;
5484 case 2:
33eaf5de 5485 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5486 only in 32bit mode and we can use opcode 0x90. In 64bit
5487 mode, we can't use 0x90 for xchg %eax, %eax since it should
5488 zero-extend %eax to %rax. */
5489 if (flag_code == CODE_64BIT
5490 && t->base_opcode == 0x90
0dfbf9d7
L		 5491 && operand_type_equal (&i.types [0], &acc32)
5492 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 5493 continue;
1212781b
JB		 5494 /* xrelease mov %eax, <disp> is another special case. It must not
5495 match the accumulator-only encoding of mov. */
5496 if (flag_code != CODE_64BIT
5497 && i.hle_prefix
5498 && t->base_opcode == 0xa0
5499 && i.types[0].bitfield.acc
5500 && operand_type_check (i.types[1], anymem))
5501 continue;
86fa6981
L		 5502 /* If we want store form, we reverse direction of operands. */
5503 if (i.dir_encoding == dir_encoding_store
5504 && t->opcode_modifier.d)
5505 goto check_reverse;
1a0670f3 5506 /* Fall through. */
b6169b20 5507
29b0f896 5508 case 3:
86fa6981
L		 5509 /* If we want store form, we skip the current load. */
5510 if (i.dir_encoding == dir_encoding_store
5511 && i.mem_operands == 0
5512 && t->opcode_modifier.load)
fa99fab2 5513 continue;
1a0670f3 5514 /* Fall through. */
f48ff2ae 5515 case 4:
c0f3af97 5516 case 5:
c6fb90c8 5517 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5518 if (!operand_type_match (overlap0, i.types[0])
5519 || !operand_type_match (overlap1, i.types[1])
e2195274 5520 || ((check_register & 3) == 3
dc821c5f 5521 && !operand_type_register_match (i.types[0],
40fb9820 5522 operand_types[0],
dc821c5f 5523 i.types[1],
40fb9820 5524 operand_types[1])))
29b0f896
AM		 5525 {
5526 /* Check if other direction is valid ... */
38e314eb 5527 if (!t->opcode_modifier.d)
29b0f896
AM		 5528 continue;
5529
b6169b20 5530check_reverse:
29b0f896 5531 /* Try reversing direction of operands. */
c6fb90c8
L		 5532 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5533 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 5534 if (!operand_type_match (overlap0, i.types[0])
5535 || !operand_type_match (overlap1, i.types[1])
45664ddb 5536 || (check_register
dc821c5f 5537 && !operand_type_register_match (i.types[0],
45664ddb 5538 operand_types[1],
45664ddb
L		 5539 i.types[1],
5540 operand_types[0])))
29b0f896
AM		 5541 {
5542 /* Does not match either direction. */
5543 continue;
5544 }
38e314eb 5545 /* found_reverse_match holds which of D or FloatR
29b0f896 5546 we've found. */
38e314eb
JB		 5547 if (!t->opcode_modifier.d)
5548 found_reverse_match = 0;
5549 else if (operand_types[0].bitfield.tbyte)
8a2ed489
L		 5550 found_reverse_match = Opcode_FloatD;
5551 else
38e314eb 5552 found_reverse_match = Opcode_D;
40fb9820 5553 if (t->opcode_modifier.floatr)
8a2ed489 5554 found_reverse_match |= Opcode_FloatR;
29b0f896 5555 }
f48ff2ae 5556 else
29b0f896 5557 {
f48ff2ae 5558 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5559 switch (t->operands)
5560 {
c0f3af97
L		 5561 case 5:
5562 overlap4 = operand_type_and (i.types[4],
5563 operand_types[4]);
1a0670f3 5564 /* Fall through. */
d1cbb4db 5565 case 4:
c6fb90c8
L		 5566 overlap3 = operand_type_and (i.types[3],
5567 operand_types[3]);
1a0670f3 5568 /* Fall through. */
d1cbb4db 5569 case 3:
c6fb90c8
L		 5570 overlap2 = operand_type_and (i.types[2],
5571 operand_types[2]);
d1cbb4db
L		 5572 break;
5573 }
29b0f896 5574
f48ff2ae
L		 5575 switch (t->operands)
5576 {
c0f3af97
L		 5577 case 5:
5578 if (!operand_type_match (overlap4, i.types[4])
dc821c5f 5579 || !operand_type_register_match (i.types[3],
c0f3af97 5580 operand_types[3],
c0f3af97
L		 5581 i.types[4],
5582 operand_types[4]))
5583 continue;
1a0670f3 5584 /* Fall through. */
f48ff2ae 5585 case 4:
40fb9820 5586 if (!operand_type_match (overlap3, i.types[3])
e2195274
JB		 5587 || ((check_register & 0xa) == 0xa
5588 && !operand_type_register_match (i.types[1],
f7768225
JB		 5589 operand_types[1],
5590 i.types[3],
e2195274
JB		 5591 operand_types[3]))
5592 || ((check_register & 0xc) == 0xc
5593 && !operand_type_register_match (i.types[2],
5594 operand_types[2],
5595 i.types[3],
5596 operand_types[3])))
f48ff2ae 5597 continue;
1a0670f3 5598 /* Fall through. */
f48ff2ae
L		 5599 case 3:
5600 /* Here we make use of the fact that there are no
23e42951 5601 reverse match 3 operand instructions. */
40fb9820 5602 if (!operand_type_match (overlap2, i.types[2])
e2195274
JB		 5603 || ((check_register & 5) == 5
5604 && !operand_type_register_match (i.types[0],
23e42951
JB		 5605 operand_types[0],
5606 i.types[2],
e2195274
JB		 5607 operand_types[2]))
5608 || ((check_register & 6) == 6
5609 && !operand_type_register_match (i.types[1],
5610 operand_types[1],
5611 i.types[2],
5612 operand_types[2])))
f48ff2ae
L		 5613 continue;
5614 break;
5615 }
29b0f896 5616 }
f48ff2ae 5617 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5618 slip through to break. */
5619 }
3629bb00 5620 if (!found_cpu_match)
29b0f896
AM		 5621 {
5622 found_reverse_match = 0;
5623 continue;
5624 }
c0f3af97 5625
5614d22c
JB		 5626 /* Check if vector and VEX operands are valid. */
5627 if (check_VecOperands (t) || VEX_check_operands (t))
5628 {
5629 specific_error = i.error;
5630 continue;
5631 }
a683cc34 5632
29b0f896
AM		 5633 /* We've found a match; break out of loop. */
5634 break;
5635 }
5636
5637 if (t == current_templates->end)
5638 {
5639 /* We found no match. */
a65babc9 5640 const char *err_msg;
5614d22c 5641 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5642 {
5643 default:
5644 abort ();
86e026a4 5645 case operand_size_mismatch:
a65babc9
L		 5646 err_msg = _("operand size mismatch");
5647 break;
5648 case operand_type_mismatch:
5649 err_msg = _("operand type mismatch");
5650 break;
5651 case register_type_mismatch:
5652 err_msg = _("register type mismatch");
5653 break;
5654 case number_of_operands_mismatch:
5655 err_msg = _("number of operands mismatch");
5656 break;
5657 case invalid_instruction_suffix:
5658 err_msg = _("invalid instruction suffix");
5659 break;
5660 case bad_imm4:
4a2608e3 5661 err_msg = _("constant doesn't fit in 4 bits");
a65babc9 5662 break;
a65babc9
L		 5663 case unsupported_with_intel_mnemonic:
5664 err_msg = _("unsupported with Intel mnemonic");
5665 break;
5666 case unsupported_syntax:
5667 err_msg = _("unsupported syntax");
5668 break;
5669 case unsupported:
35262a23 5670 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5671 current_templates->start->name);
5672 return NULL;
6c30d220
L		 5673 case invalid_vsib_address:
5674 err_msg = _("invalid VSIB address");
5675 break;
7bab8ab5
JB		 5676 case invalid_vector_register_set:
5677 err_msg = _("mask, index, and destination registers must be distinct");
5678 break;
6c30d220
L		 5679 case unsupported_vector_index_register:
5680 err_msg = _("unsupported vector index register");
5681 break;
43234a1e
L		 5682 case unsupported_broadcast:
5683 err_msg = _("unsupported broadcast");
5684 break;
5685 case broadcast_not_on_src_operand:
5686 err_msg = _("broadcast not on source memory operand");
5687 break;
5688 case broadcast_needed:
5689 err_msg = _("broadcast is needed for operand of such type");
5690 break;
5691 case unsupported_masking:
5692 err_msg = _("unsupported masking");
5693 break;
5694 case mask_not_on_destination:
5695 err_msg = _("mask not on destination operand");
5696 break;
5697 case no_default_mask:
5698 err_msg = _("default mask isn't allowed");
5699 break;
5700 case unsupported_rc_sae:
5701 err_msg = _("unsupported static rounding/sae");
5702 break;
5703 case rc_sae_operand_not_last_imm:
5704 if (intel_syntax)
5705 err_msg = _("RC/SAE operand must precede immediate operands");
5706 else
5707 err_msg = _("RC/SAE operand must follow immediate operands");
5708 break;
5709 case invalid_register_operand:
5710 err_msg = _("invalid register operand");
5711 break;
a65babc9
L		 5712 }
5713 as_bad (_("%s for `%s'"), err_msg,
891edac4 5714 current_templates->start->name);
fa99fab2 5715 return NULL;
29b0f896 5716 }
252b5132 5717
29b0f896
AM		 5718 if (!quiet_warnings)
5719 {
5720 if (!intel_syntax
40fb9820
L		 5721 && (i.types[0].bitfield.jumpabsolute
5722 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5723 {
5724 as_warn (_("indirect %s without `*'"), t->name);
5725 }
5726
40fb9820
L		 5727 if (t->opcode_modifier.isprefix
5728 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5729 {
5730 /* Warn them that a data or address size prefix doesn't
5731 affect assembly of the next line of code. */
5732 as_warn (_("stand-alone `%s' prefix"), t->name);
5733 }
5734 }
5735
5736 /* Copy the template we found. */
5737 i.tm = *t;
539e75ad
L		 5738
5739 if (addr_prefix_disp != -1)
5740 i.tm.operand_types[addr_prefix_disp]
5741 = operand_types[addr_prefix_disp];
5742
29b0f896
AM		 5743 if (found_reverse_match)
5744 {
5745 /* If we found a reverse match we must alter the opcode
5746 direction bit. found_reverse_match holds bits to change
5747 (different for int & float insns). */
5748
5749 i.tm.base_opcode ^= found_reverse_match;
5750
539e75ad
L		 5751 i.tm.operand_types[0] = operand_types[1];
5752 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5753 }
5754
fa99fab2 5755 return t;
29b0f896
AM		 5756}
5757
5758static int
e3bb37b5 5759check_string (void)
29b0f896 5760{
40fb9820
L		 5761 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5762 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5763 {
5764 if (i.seg[0] != NULL && i.seg[0] != &es)
5765 {
a87af027 5766 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5767 i.tm.name,
a87af027
JB		 5768 mem_op + 1,
5769 register_prefix);
29b0f896
AM		 5770 return 0;
5771 }
5772 /* There's only ever one segment override allowed per instruction.
5773 This instruction possibly has a legal segment override on the
5774 second operand, so copy the segment to where non-string
5775 instructions store it, allowing common code. */
5776 i.seg[0] = i.seg[1];
5777 }
40fb9820 5778 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5779 {
5780 if (i.seg[1] != NULL && i.seg[1] != &es)
5781 {
a87af027 5782 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5783 i.tm.name,
a87af027
JB		 5784 mem_op + 2,
5785 register_prefix);
29b0f896
AM		 5786 return 0;
5787 }
5788 }
5789 return 1;
5790}
5791
5792static int
543613e9 5793process_suffix (void)
29b0f896
AM		 5794{
5795 /* If matched instruction specifies an explicit instruction mnemonic
5796 suffix, use it. */
40fb9820
L		 5797 if (i.tm.opcode_modifier.size16)
5798 i.suffix = WORD_MNEM_SUFFIX;
5799 else if (i.tm.opcode_modifier.size32)
5800 i.suffix = LONG_MNEM_SUFFIX;
5801 else if (i.tm.opcode_modifier.size64)
5802 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5803 else if (i.reg_operands)
5804 {
5805 /* If there's no instruction mnemonic suffix we try to invent one
5806 based on register operands. */
5807 if (!i.suffix)
5808 {
5809 /* We take i.suffix from the last register operand specified,
5810 Destination register type is more significant than source
381d071f
L		 5811 register type. crc32 in SSE4.2 prefers source register
5812 type. */
5813 if (i.tm.base_opcode == 0xf20f38f1)
5814 {
dc821c5f 5815 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
40fb9820 5816 i.suffix = WORD_MNEM_SUFFIX;
dc821c5f 5817 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
40fb9820 5818 i.suffix = LONG_MNEM_SUFFIX;
dc821c5f 5819 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
40fb9820 5820 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5821 }
9344ff29 5822 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5823 {
dc821c5f 5824 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
20592a94
L		 5825 i.suffix = BYTE_MNEM_SUFFIX;
5826 }
381d071f
L		 5827
5828 if (!i.suffix)
5829 {
5830 int op;
5831
20592a94
L		 5832 if (i.tm.base_opcode == 0xf20f38f1
5833 || i.tm.base_opcode == 0xf20f38f0)
5834 {
5835 /* We have to know the operand size for crc32. */
5836 as_bad (_("ambiguous memory operand size for `%s`"),
5837 i.tm.name);
5838 return 0;
5839 }
5840
381d071f 5841 for (op = i.operands; --op >= 0;)
b76bc5d5
JB		 5842 if (!i.tm.operand_types[op].bitfield.inoutportreg
5843 && !i.tm.operand_types[op].bitfield.shiftcount)
381d071f 5844 {
8819ada6
JB		 5845 if (!i.types[op].bitfield.reg)
5846 continue;
5847 if (i.types[op].bitfield.byte)
5848 i.suffix = BYTE_MNEM_SUFFIX;
5849 else if (i.types[op].bitfield.word)
5850 i.suffix = WORD_MNEM_SUFFIX;
5851 else if (i.types[op].bitfield.dword)
5852 i.suffix = LONG_MNEM_SUFFIX;
5853 else if (i.types[op].bitfield.qword)
5854 i.suffix = QWORD_MNEM_SUFFIX;
5855 else
5856 continue;
5857 break;
381d071f
L		 5858 }
5859 }
29b0f896
AM		 5860 }
5861 else if (i.suffix == BYTE_MNEM_SUFFIX)
5862 {
2eb952a4
L		 5863 if (intel_syntax
5864 && i.tm.opcode_modifier.ignoresize
5865 && i.tm.opcode_modifier.no_bsuf)
5866 i.suffix = 0;
5867 else if (!check_byte_reg ())
29b0f896
AM		 5868 return 0;
5869 }
5870 else if (i.suffix == LONG_MNEM_SUFFIX)
5871 {
2eb952a4
L		 5872 if (intel_syntax
5873 && i.tm.opcode_modifier.ignoresize
9f123b91
JB		 5874 && i.tm.opcode_modifier.no_lsuf
5875 && !i.tm.opcode_modifier.todword
5876 && !i.tm.opcode_modifier.toqword)
2eb952a4
L		 5877 i.suffix = 0;
5878 else if (!check_long_reg ())
29b0f896
AM		 5879 return 0;
5880 }
5881 else if (i.suffix == QWORD_MNEM_SUFFIX)
5882 {
955e1e6a
L		 5883 if (intel_syntax
5884 && i.tm.opcode_modifier.ignoresize
9f123b91
JB		 5885 && i.tm.opcode_modifier.no_qsuf
5886 && !i.tm.opcode_modifier.todword
5887 && !i.tm.opcode_modifier.toqword)
955e1e6a
L		 5888 i.suffix = 0;
5889 else if (!check_qword_reg ())
29b0f896
AM		 5890 return 0;
5891 }
5892 else if (i.suffix == WORD_MNEM_SUFFIX)
5893 {
2eb952a4
L		 5894 if (intel_syntax
5895 && i.tm.opcode_modifier.ignoresize
5896 && i.tm.opcode_modifier.no_wsuf)
5897 i.suffix = 0;
5898 else if (!check_word_reg ())
29b0f896
AM		 5899 return 0;
5900 }
40fb9820 5901 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5902 /* Do nothing if the instruction is going to ignore the prefix. */
5903 ;
5904 else
5905 abort ();
5906 }
40fb9820 5907 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5908 && !i.suffix
5909 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5910 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5911 {
5912 i.suffix = stackop_size;
5913 }
9306ca4a
JB		 5914 else if (intel_syntax
5915 && !i.suffix
40fb9820
L		 5916 && (i.tm.operand_types[0].bitfield.jumpabsolute
5917 || i.tm.opcode_modifier.jumpbyte
5918 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5919 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5920 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5921 {
5922 switch (flag_code)
5923 {
5924 case CODE_64BIT:
40fb9820 5925 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5926 {
5927 i.suffix = QWORD_MNEM_SUFFIX;
5928 break;
5929 }
1a0670f3 5930 /* Fall through. */
9306ca4a 5931 case CODE_32BIT:
40fb9820 5932 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5933 i.suffix = LONG_MNEM_SUFFIX;
5934 break;
5935 case CODE_16BIT:
40fb9820 5936 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5937 i.suffix = WORD_MNEM_SUFFIX;
5938 break;
5939 }
5940 }
252b5132 5941
9306ca4a 5942 if (!i.suffix)
29b0f896 5943 {
9306ca4a
JB		 5944 if (!intel_syntax)
5945 {
40fb9820 5946 if (i.tm.opcode_modifier.w)
9306ca4a 5947 {
4eed87de
AM		 5948 as_bad (_("no instruction mnemonic suffix given and "
5949 "no register operands; can't size instruction"));
9306ca4a
JB		 5950 return 0;
5951 }
5952 }
5953 else
5954 {
40fb9820 5955 unsigned int suffixes;
7ab9ffdd 5956
40fb9820
L		 5957 suffixes = !i.tm.opcode_modifier.no_bsuf;
5958 if (!i.tm.opcode_modifier.no_wsuf)
5959 suffixes |= 1 << 1;
5960 if (!i.tm.opcode_modifier.no_lsuf)
5961 suffixes |= 1 << 2;
fc4adea1 5962 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5963 suffixes |= 1 << 3;
5964 if (!i.tm.opcode_modifier.no_ssuf)
5965 suffixes |= 1 << 4;
c2b9da16 5966 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
40fb9820
L		 5967 suffixes |= 1 << 5;
5968
5969 /* There are more than suffix matches. */
5970 if (i.tm.opcode_modifier.w
9306ca4a 5971 || ((suffixes & (suffixes - 1))
40fb9820
L		 5972 && !i.tm.opcode_modifier.defaultsize
5973 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5974 {
5975 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5976 return 0;
5977 }
5978 }
29b0f896 5979 }
252b5132 5980
d2224064
JB		 5981 /* Change the opcode based on the operand size given by i.suffix. */
5982 switch (i.suffix)
29b0f896 5983 {
d2224064
JB		 5984 /* Size floating point instruction. */
5985 case LONG_MNEM_SUFFIX:
5986 if (i.tm.opcode_modifier.floatmf)
5987 {
5988 i.tm.base_opcode ^= 4;
5989 break;
5990 }
5991 /* fall through */
5992 case WORD_MNEM_SUFFIX:
5993 case QWORD_MNEM_SUFFIX:
29b0f896 5994 /* It's not a byte, select word/dword operation. */
40fb9820 5995 if (i.tm.opcode_modifier.w)
29b0f896 5996 {
40fb9820 5997 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5998 i.tm.base_opcode |= 8;
5999 else
6000 i.tm.base_opcode |= 1;
6001 }
d2224064
JB		 6002 /* fall through */
6003 case SHORT_MNEM_SUFFIX:
29b0f896
AM		 6004 /* Now select between word & dword operations via the operand
6005 size prefix, except for instructions that will ignore this
6006 prefix anyway. */
75c0a438
L		 6007 if (i.reg_operands > 0
6008 && i.types[0].bitfield.reg
6009 && i.tm.opcode_modifier.addrprefixopreg
6010 && (i.tm.opcode_modifier.immext
6011 || i.operands == 1))
cb712a9e 6012 {
ca61edf2
L		 6013 /* The address size override prefix changes the size of the
6014 first operand. */
40fb9820 6015 if ((flag_code == CODE_32BIT
75c0a438 6016 && i.op[0].regs->reg_type.bitfield.word)
40fb9820 6017 || (flag_code != CODE_32BIT
75c0a438 6018 && i.op[0].regs->reg_type.bitfield.dword))
cb712a9e
L		 6019 if (!add_prefix (ADDR_PREFIX_OPCODE))
6020 return 0;
6021 }
6022 else if (i.suffix != QWORD_MNEM_SUFFIX
40fb9820
L		 6023 && !i.tm.opcode_modifier.ignoresize
6024 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 6025 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
6026 || (flag_code == CODE_64BIT
40fb9820 6027 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 6028 {
6029 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 6030
40fb9820 6031 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 6032 prefix = ADDR_PREFIX_OPCODE;
252b5132 6033
29b0f896
AM		 6034 if (!add_prefix (prefix))
6035 return 0;
24eab124 6036 }
252b5132 6037
29b0f896
AM		 6038 /* Set mode64 for an operand. */
6039 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 6040 && flag_code == CODE_64BIT
d2224064 6041 && !i.tm.opcode_modifier.norex64
46e883c5 6042 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d2224064
JB		 6043 need rex64. */
6044 && ! (i.operands == 2
6045 && i.tm.base_opcode == 0x90
6046 && i.tm.extension_opcode == None
6047 && operand_type_equal (&i.types [0], &acc64)
6048 && operand_type_equal (&i.types [1], &acc64)))
6049 i.rex |= REX_W;
3e73aa7c 6050
d2224064 6051 break;
29b0f896 6052 }
7ecd2f8b 6053
c0a30a9f
L		 6054 if (i.reg_operands != 0
6055 && i.operands > 1
6056 && i.tm.opcode_modifier.addrprefixopreg
6057 && !i.tm.opcode_modifier.immext)
6058 {
6059 /* Check invalid register operand when the address size override
6060 prefix changes the size of register operands. */
6061 unsigned int op;
6062 enum { need_word, need_dword, need_qword } need;
6063
6064 if (flag_code == CODE_32BIT)
6065 need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
6066 else
6067 {
6068 if (i.prefix[ADDR_PREFIX])
6069 need = need_dword;
6070 else
6071 need = flag_code == CODE_64BIT ? need_qword : need_word;
6072 }
6073
6074 for (op = 0; op < i.operands; op++)
6075 if (i.types[op].bitfield.reg
6076 && ((need == need_word
6077 && !i.op[op].regs->reg_type.bitfield.word)
6078 || (need == need_dword
6079 && !i.op[op].regs->reg_type.bitfield.dword)
6080 || (need == need_qword
6081 && !i.op[op].regs->reg_type.bitfield.qword)))
6082 {
6083 as_bad (_("invalid register operand size for `%s'"),
6084 i.tm.name);
6085 return 0;
6086 }
6087 }
6088
29b0f896
AM		 6089 return 1;
6090}
3e73aa7c 6091
29b0f896 6092static int
543613e9 6093check_byte_reg (void)
29b0f896
AM		 6094{
6095 int op;
543613e9 6096
29b0f896
AM		 6097 for (op = i.operands; --op >= 0;)
6098 {
dc821c5f
JB		 6099 /* Skip non-register operands. */
6100 if (!i.types[op].bitfield.reg)
6101 continue;
6102
29b0f896
AM		 6103 /* If this is an eight bit register, it's OK. If it's the 16 or
6104 32 bit version of an eight bit register, we will just use the
6105 low portion, and that's OK too. */
dc821c5f 6106 if (i.types[op].bitfield.byte)
29b0f896
AM		 6107 continue;
6108
5a819eb9
JB		 6109 /* I/O port address operands are OK too. */
6110 if (i.tm.operand_types[op].bitfield.inoutportreg)
6111 continue;
6112
9344ff29
L		 6113 /* crc32 doesn't generate this warning. */
6114 if (i.tm.base_opcode == 0xf20f38f0)
6115 continue;
6116
dc821c5f
JB		 6117 if ((i.types[op].bitfield.word
6118 || i.types[op].bitfield.dword
6119 || i.types[op].bitfield.qword)
5a819eb9
JB		 6120 && i.op[op].regs->reg_num < 4
6121 /* Prohibit these changes in 64bit mode, since the lowering
6122 would be more complicated. */
6123 && flag_code != CODE_64BIT)
29b0f896 6124 {
29b0f896 6125#if REGISTER_WARNINGS
5a819eb9 6126 if (!quiet_warnings)
a540244d
L		 6127 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6128 register_prefix,
dc821c5f 6129 (i.op[op].regs + (i.types[op].bitfield.word
29b0f896
AM		 6130 ? REGNAM_AL - REGNAM_AX
6131 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 6132 register_prefix,
29b0f896
AM		 6133 i.op[op].regs->reg_name,
6134 i.suffix);
6135#endif
6136 continue;
6137 }
6138 /* Any other register is bad. */
dc821c5f 6139 if (i.types[op].bitfield.reg
40fb9820 6140 || i.types[op].bitfield.regmmx
1b54b8d7 6141 || i.types[op].bitfield.regsimd
40fb9820
L		 6142 || i.types[op].bitfield.sreg2
6143 || i.types[op].bitfield.sreg3
6144 || i.types[op].bitfield.control
6145 || i.types[op].bitfield.debug
ca0d63fe 6146 || i.types[op].bitfield.test)
29b0f896 6147 {
a540244d
L		 6148 as_bad (_("`%s%s' not allowed with `%s%c'"),
6149 register_prefix,
29b0f896
AM		 6150 i.op[op].regs->reg_name,
6151 i.tm.name,
6152 i.suffix);
6153 return 0;
6154 }
6155 }
6156 return 1;
6157}
6158
6159static int
e3bb37b5 6160check_long_reg (void)
29b0f896
AM		 6161{
6162 int op;
6163
6164 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6165 /* Skip non-register operands. */
6166 if (!i.types[op].bitfield.reg)
6167 continue;
29b0f896
AM		 6168 /* Reject eight bit registers, except where the template requires
6169 them. (eg. movzb) */
dc821c5f
JB		 6170 else if (i.types[op].bitfield.byte
6171 && (i.tm.operand_types[op].bitfield.reg
6172 || i.tm.operand_types[op].bitfield.acc)
6173 && (i.tm.operand_types[op].bitfield.word
6174 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6175 {
a540244d
L		 6176 as_bad (_("`%s%s' not allowed with `%s%c'"),
6177 register_prefix,
29b0f896
AM		 6178 i.op[op].regs->reg_name,
6179 i.tm.name,
6180 i.suffix);
6181 return 0;
6182 }
e4630f71 6183 /* Warn if the e prefix on a general reg is missing. */
29b0f896 6184 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6185 && i.types[op].bitfield.word
6186 && (i.tm.operand_types[op].bitfield.reg
6187 || i.tm.operand_types[op].bitfield.acc)
6188 && i.tm.operand_types[op].bitfield.dword)
29b0f896
AM		 6189 {
6190 /* Prohibit these changes in the 64bit mode, since the
6191 lowering is more complicated. */
6192 if (flag_code == CODE_64BIT)
252b5132 6193 {
2b5d6a91 6194 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6195 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6196 i.suffix);
6197 return 0;
252b5132 6198 }
29b0f896 6199#if REGISTER_WARNINGS
cecf1424
JB		 6200 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6201 register_prefix,
6202 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6203 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 6204#endif
252b5132 6205 }
e4630f71 6206 /* Warn if the r prefix on a general reg is present. */
dc821c5f
JB		 6207 else if (i.types[op].bitfield.qword
6208 && (i.tm.operand_types[op].bitfield.reg
6209 || i.tm.operand_types[op].bitfield.acc)
6210 && i.tm.operand_types[op].bitfield.dword)
252b5132 6211 {
34828aad 6212 if (intel_syntax
ca61edf2 6213 && i.tm.opcode_modifier.toqword
1b54b8d7 6214 && !i.types[0].bitfield.regsimd)
34828aad 6215 {
ca61edf2 6216 /* Convert to QWORD. We want REX byte. */
34828aad
L		 6217 i.suffix = QWORD_MNEM_SUFFIX;
6218 }
6219 else
6220 {
2b5d6a91 6221 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6222 register_prefix, i.op[op].regs->reg_name,
6223 i.suffix);
6224 return 0;
6225 }
29b0f896
AM		 6226 }
6227 return 1;
6228}
252b5132 6229
29b0f896 6230static int
e3bb37b5 6231check_qword_reg (void)
29b0f896
AM		 6232{
6233 int op;
252b5132 6234
29b0f896 6235 for (op = i.operands; --op >= 0; )
dc821c5f
JB		 6236 /* Skip non-register operands. */
6237 if (!i.types[op].bitfield.reg)
6238 continue;
29b0f896
AM		 6239 /* Reject eight bit registers, except where the template requires
6240 them. (eg. movzb) */
dc821c5f
JB		 6241 else if (i.types[op].bitfield.byte
6242 && (i.tm.operand_types[op].bitfield.reg
6243 || i.tm.operand_types[op].bitfield.acc)
6244 && (i.tm.operand_types[op].bitfield.word
6245 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6246 {
a540244d
L		 6247 as_bad (_("`%s%s' not allowed with `%s%c'"),
6248 register_prefix,
29b0f896
AM		 6249 i.op[op].regs->reg_name,
6250 i.tm.name,
6251 i.suffix);
6252 return 0;
6253 }
e4630f71 6254 /* Warn if the r prefix on a general reg is missing. */
dc821c5f
JB		 6255 else if ((i.types[op].bitfield.word
6256 || i.types[op].bitfield.dword)
6257 && (i.tm.operand_types[op].bitfield.reg
6258 || i.tm.operand_types[op].bitfield.acc)
6259 && i.tm.operand_types[op].bitfield.qword)
29b0f896
AM		 6260 {
6261 /* Prohibit these changes in the 64bit mode, since the
6262 lowering is more complicated. */
34828aad 6263 if (intel_syntax
ca61edf2 6264 && i.tm.opcode_modifier.todword
1b54b8d7 6265 && !i.types[0].bitfield.regsimd)
34828aad 6266 {
ca61edf2 6267 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 6268 i.suffix = LONG_MNEM_SUFFIX;
6269 }
6270 else
6271 {
2b5d6a91 6272 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6273 register_prefix, i.op[op].regs->reg_name,
6274 i.suffix);
6275 return 0;
6276 }
252b5132 6277 }
29b0f896
AM		 6278 return 1;
6279}
252b5132 6280
29b0f896 6281static int
e3bb37b5 6282check_word_reg (void)
29b0f896
AM		 6283{
6284 int op;
6285 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6286 /* Skip non-register operands. */
6287 if (!i.types[op].bitfield.reg)
6288 continue;
29b0f896
AM		 6289 /* Reject eight bit registers, except where the template requires
6290 them. (eg. movzb) */
dc821c5f
JB		 6291 else if (i.types[op].bitfield.byte
6292 && (i.tm.operand_types[op].bitfield.reg
6293 || i.tm.operand_types[op].bitfield.acc)
6294 && (i.tm.operand_types[op].bitfield.word
6295 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6296 {
a540244d
L		 6297 as_bad (_("`%s%s' not allowed with `%s%c'"),
6298 register_prefix,
29b0f896
AM		 6299 i.op[op].regs->reg_name,
6300 i.tm.name,
6301 i.suffix);
6302 return 0;
6303 }
e4630f71 6304 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 6305 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6306 && (i.types[op].bitfield.dword
6307 || i.types[op].bitfield.qword)
6308 && (i.tm.operand_types[op].bitfield.reg
6309 || i.tm.operand_types[op].bitfield.acc)
6310 && i.tm.operand_types[op].bitfield.word)
252b5132 6311 {
29b0f896
AM		 6312 /* Prohibit these changes in the 64bit mode, since the
6313 lowering is more complicated. */
6314 if (flag_code == CODE_64BIT)
252b5132 6315 {
2b5d6a91 6316 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6317 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6318 i.suffix);
6319 return 0;
252b5132 6320 }
29b0f896 6321#if REGISTER_WARNINGS
cecf1424
JB		 6322 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6323 register_prefix,
6324 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6325 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 6326#endif
6327 }
6328 return 1;
6329}
252b5132 6330
29b0f896 6331static int
40fb9820 6332update_imm (unsigned int j)
29b0f896 6333{
bc0844ae 6334 i386_operand_type overlap = i.types[j];
40fb9820
L		 6335 if ((overlap.bitfield.imm8
6336 || overlap.bitfield.imm8s
6337 || overlap.bitfield.imm16
6338 || overlap.bitfield.imm32
6339 || overlap.bitfield.imm32s
6340 || overlap.bitfield.imm64)
0dfbf9d7
L		 6341 && !operand_type_equal (&overlap, &imm8)
6342 && !operand_type_equal (&overlap, &imm8s)
6343 && !operand_type_equal (&overlap, &imm16)
6344 && !operand_type_equal (&overlap, &imm32)
6345 && !operand_type_equal (&overlap, &imm32s)
6346 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 6347 {
6348 if (i.suffix)
6349 {
40fb9820
L		 6350 i386_operand_type temp;
6351
0dfbf9d7 6352 operand_type_set (&temp, 0);
7ab9ffdd 6353 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 6354 {
6355 temp.bitfield.imm8 = overlap.bitfield.imm8;
6356 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6357 }
6358 else if (i.suffix == WORD_MNEM_SUFFIX)
6359 temp.bitfield.imm16 = overlap.bitfield.imm16;
6360 else if (i.suffix == QWORD_MNEM_SUFFIX)
6361 {
6362 temp.bitfield.imm64 = overlap.bitfield.imm64;
6363 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6364 }
6365 else
6366 temp.bitfield.imm32 = overlap.bitfield.imm32;
6367 overlap = temp;
29b0f896 6368 }
0dfbf9d7
L		 6369 else if (operand_type_equal (&overlap, &imm16_32_32s)
6370 || operand_type_equal (&overlap, &imm16_32)
6371 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 6372 {
40fb9820 6373 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 6374 overlap = imm16;
40fb9820 6375 else
65da13b5 6376 overlap = imm32s;
29b0f896 6377 }
0dfbf9d7
L		 6378 if (!operand_type_equal (&overlap, &imm8)
6379 && !operand_type_equal (&overlap, &imm8s)
6380 && !operand_type_equal (&overlap, &imm16)
6381 && !operand_type_equal (&overlap, &imm32)
6382 && !operand_type_equal (&overlap, &imm32s)
6383 && !operand_type_equal (&overlap, &imm64))
29b0f896 6384 {
4eed87de
AM		 6385 as_bad (_("no instruction mnemonic suffix given; "
6386 "can't determine immediate size"));
29b0f896
AM		 6387 return 0;
6388 }
6389 }
40fb9820 6390 i.types[j] = overlap;
29b0f896 6391
40fb9820
L		 6392 return 1;
6393}
6394
6395static int
6396finalize_imm (void)
6397{
bc0844ae 6398 unsigned int j, n;
29b0f896 6399
bc0844ae
L		 6400 /* Update the first 2 immediate operands. */
6401 n = i.operands > 2 ? 2 : i.operands;
6402 if (n)
6403 {
6404 for (j = 0; j < n; j++)
6405 if (update_imm (j) == 0)
6406 return 0;
40fb9820 6407
bc0844ae
L		 6408 /* The 3rd operand can't be immediate operand. */
6409 gas_assert (operand_type_check (i.types[2], imm) == 0);
6410 }
29b0f896
AM		 6411
6412 return 1;
6413}
6414
6415static int
e3bb37b5 6416process_operands (void)
29b0f896
AM		 6417{
6418 /* Default segment register this instruction will use for memory
6419 accesses. 0 means unknown. This is only for optimizing out
6420 unnecessary segment overrides. */
6421 const seg_entry *default_seg = 0;
6422
2426c15f 6423 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 6424 {
91d6fa6a
NC		 6425 unsigned int dupl = i.operands;
6426 unsigned int dest = dupl - 1;
9fcfb3d7
L		 6427 unsigned int j;
6428
c0f3af97 6429 /* The destination must be an xmm register. */
9c2799c2 6430 gas_assert (i.reg_operands
91d6fa6a 6431 && MAX_OPERANDS > dupl
7ab9ffdd 6432 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97 6433
1b54b8d7
JB		 6434 if (i.tm.operand_types[0].bitfield.acc
6435 && i.tm.operand_types[0].bitfield.xmmword)
e2ec9d29 6436 {
8cd7925b 6437 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 6438 {
6439 /* Keep xmm0 for instructions with VEX prefix and 3
6440 sources. */
1b54b8d7
JB		 6441 i.tm.operand_types[0].bitfield.acc = 0;
6442 i.tm.operand_types[0].bitfield.regsimd = 1;
c0f3af97
L		 6443 goto duplicate;
6444 }
e2ec9d29 6445 else
c0f3af97
L		 6446 {
6447 /* We remove the first xmm0 and keep the number of
6448 operands unchanged, which in fact duplicates the
6449 destination. */
6450 for (j = 1; j < i.operands; j++)
6451 {
6452 i.op[j - 1] = i.op[j];
6453 i.types[j - 1] = i.types[j];
6454 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6455 }
6456 }
6457 }
6458 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 6459 {
91d6fa6a 6460 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 6461 && (i.tm.opcode_modifier.vexsources
6462 == VEX3SOURCES));
c0f3af97
L		 6463
6464 /* Add the implicit xmm0 for instructions with VEX prefix
6465 and 3 sources. */
6466 for (j = i.operands; j > 0; j--)
6467 {
6468 i.op[j] = i.op[j - 1];
6469 i.types[j] = i.types[j - 1];
6470 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6471 }
6472 i.op[0].regs
6473 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 6474 i.types[0] = regxmm;
c0f3af97
L		 6475 i.tm.operand_types[0] = regxmm;
6476
6477 i.operands += 2;
6478 i.reg_operands += 2;
6479 i.tm.operands += 2;
6480
91d6fa6a 6481 dupl++;
c0f3af97 6482 dest++;
91d6fa6a
NC		 6483 i.op[dupl] = i.op[dest];
6484 i.types[dupl] = i.types[dest];
6485 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6486 }
c0f3af97
L		 6487 else
6488 {
6489duplicate:
6490 i.operands++;
6491 i.reg_operands++;
6492 i.tm.operands++;
6493
91d6fa6a
NC		 6494 i.op[dupl] = i.op[dest];
6495 i.types[dupl] = i.types[dest];
6496 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6497 }
6498
6499 if (i.tm.opcode_modifier.immext)
6500 process_immext ();
6501 }
1b54b8d7
JB		 6502 else if (i.tm.operand_types[0].bitfield.acc
6503 && i.tm.operand_types[0].bitfield.xmmword)
c0f3af97
L		 6504 {
6505 unsigned int j;
6506
9fcfb3d7
L		 6507 for (j = 1; j < i.operands; j++)
6508 {
6509 i.op[j - 1] = i.op[j];
6510 i.types[j - 1] = i.types[j];
6511
6512 /* We need to adjust fields in i.tm since they are used by
6513 build_modrm_byte. */
6514 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6515 }
6516
e2ec9d29
L		 6517 i.operands--;
6518 i.reg_operands--;
e2ec9d29
L		 6519 i.tm.operands--;
6520 }
920d2ddc
IT		 6521 else if (i.tm.opcode_modifier.implicitquadgroup)
6522 {
a477a8c4
JB		 6523 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6524
920d2ddc 6525 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
10c17abd 6526 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
a477a8c4
JB		 6527 regnum = register_number (i.op[1].regs);
6528 first_reg_in_group = regnum & ~3;
6529 last_reg_in_group = first_reg_in_group + 3;
6530 if (regnum != first_reg_in_group)
6531 as_warn (_("source register `%s%s' implicitly denotes"
6532 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6533 register_prefix, i.op[1].regs->reg_name,
6534 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6535 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6536 i.tm.name);
6537 }
e2ec9d29
L		 6538 else if (i.tm.opcode_modifier.regkludge)
6539 {
6540 /* The imul $imm, %reg instruction is converted into
6541 imul $imm, %reg, %reg, and the clr %reg instruction
6542 is converted into xor %reg, %reg. */
6543
6544 unsigned int first_reg_op;
6545
6546 if (operand_type_check (i.types[0], reg))
6547 first_reg_op = 0;
6548 else
6549 first_reg_op = 1;
6550 /* Pretend we saw the extra register operand. */
9c2799c2 6551 gas_assert (i.reg_operands == 1
7ab9ffdd 6552 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6553 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6554 i.types[first_reg_op + 1] = i.types[first_reg_op];
6555 i.operands++;
6556 i.reg_operands++;
29b0f896
AM		 6557 }
6558
40fb9820 6559 if (i.tm.opcode_modifier.shortform)
29b0f896 6560 {
40fb9820
L		 6561 if (i.types[0].bitfield.sreg2
6562 || i.types[0].bitfield.sreg3)
29b0f896 6563 {
4eed87de
AM		 6564 if (i.tm.base_opcode == POP_SEG_SHORT
6565 && i.op[0].regs->reg_num == 1)
29b0f896 6566 {
a87af027 6567 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6568 return 0;
29b0f896 6569 }
4eed87de
AM		 6570 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6571 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6572 i.rex |= REX_B;
4eed87de
AM		 6573 }
6574 else
6575 {
7ab9ffdd 6576 /* The register or float register operand is in operand
85f10a01 6577 0 or 1. */
40fb9820 6578 unsigned int op;
7ab9ffdd 6579
ca0d63fe 6580 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
7ab9ffdd
L		 6581 || operand_type_check (i.types[0], reg))
6582 op = 0;
6583 else
6584 op = 1;
4eed87de
AM		 6585 /* Register goes in low 3 bits of opcode. */
6586 i.tm.base_opcode |= i.op[op].regs->reg_num;
6587 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6588 i.rex |= REX_B;
40fb9820 6589 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6590 {
4eed87de
AM		 6591 /* Warn about some common errors, but press on regardless.
6592 The first case can be generated by gcc (<= 2.8.1). */
6593 if (i.operands == 2)
6594 {
6595 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6596 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6597 register_prefix, i.op[!intel_syntax].regs->reg_name,
6598 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6599 }
6600 else
6601 {
6602 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6603 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6604 register_prefix, i.op[0].regs->reg_name);
4eed87de 6605 }
29b0f896
AM		 6606 }
6607 }
6608 }
40fb9820 6609 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6610 {
6611 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6612 must be put into the modrm byte). Now, we make the modrm and
6613 index base bytes based on all the info we've collected. */
29b0f896
AM		 6614
6615 default_seg = build_modrm_byte ();
6616 }
8a2ed489 6617 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6618 {
6619 default_seg = &ds;
6620 }
40fb9820 6621 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6622 {
6623 /* For the string instructions that allow a segment override
6624 on one of their operands, the default segment is ds. */
6625 default_seg = &ds;
6626 }
6627
75178d9d
L		 6628 if (i.tm.base_opcode == 0x8d /* lea */
6629 && i.seg[0]
6630 && !quiet_warnings)
30123838 6631 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6632
6633 /* If a segment was explicitly specified, and the specified segment
6634 is not the default, use an opcode prefix to select it. If we
6635 never figured out what the default segment is, then default_seg
6636 will be zero at this point, and the specified segment prefix will
6637 always be used. */
29b0f896
AM		 6638 if ((i.seg[0]) && (i.seg[0] != default_seg))
6639 {
6640 if (!add_prefix (i.seg[0]->seg_prefix))
6641 return 0;
6642 }
6643 return 1;
6644}
6645
6646static const seg_entry *
e3bb37b5 6647build_modrm_byte (void)
29b0f896
AM		 6648{
6649 const seg_entry *default_seg = 0;
c0f3af97 6650 unsigned int source, dest;
8cd7925b 6651 int vex_3_sources;
c0f3af97 6652
8cd7925b 6653 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6654 if (vex_3_sources)
6655 {
91d6fa6a 6656 unsigned int nds, reg_slot;
4c2c6516 6657 expressionS *exp;
c0f3af97 6658
6b8d3588 6659 dest = i.operands - 1;
c0f3af97 6660 nds = dest - 1;
922d8de8 6661
a683cc34 6662 /* There are 2 kinds of instructions:
bed3d976
JB		 6663 1. 5 operands: 4 register operands or 3 register operands
6664 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6665 VexW0 or VexW1. The destination must be either XMM, YMM or
43234a1e 6666 ZMM register.
bed3d976 6667 2. 4 operands: 4 register operands or 3 register operands
2f1bada2 6668 plus 1 memory operand, with VexXDS. */
922d8de8 6669 gas_assert ((i.reg_operands == 4
bed3d976
JB		 6670 || (i.reg_operands == 3 && i.mem_operands == 1))
6671 && i.tm.opcode_modifier.vexvvvv == VEXXDS
dcd7e323
JB		 6672 && i.tm.opcode_modifier.vexw
6673 && i.tm.operand_types[dest].bitfield.regsimd);
a683cc34 6674
48db9223
JB		 6675 /* If VexW1 is set, the first non-immediate operand is the source and
6676 the second non-immediate one is encoded in the immediate operand. */
6677 if (i.tm.opcode_modifier.vexw == VEXW1)
6678 {
6679 source = i.imm_operands;
6680 reg_slot = i.imm_operands + 1;
6681 }
6682 else
6683 {
6684 source = i.imm_operands + 1;
6685 reg_slot = i.imm_operands;
6686 }
6687
a683cc34 6688 if (i.imm_operands == 0)
bed3d976
JB		 6689 {
6690 /* When there is no immediate operand, generate an 8bit
6691 immediate operand to encode the first operand. */
6692 exp = &im_expressions[i.imm_operands++];
6693 i.op[i.operands].imms = exp;
6694 i.types[i.operands] = imm8;
6695 i.operands++;
6696
6697 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6698 exp->X_op = O_constant;
6699 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6700 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6701 }
922d8de8 6702 else
bed3d976
JB		 6703 {
6704 unsigned int imm_slot;
a683cc34 6705
2f1bada2
JB		 6706 gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
6707
bed3d976
JB		 6708 if (i.tm.opcode_modifier.immext)
6709 {
6710 /* When ImmExt is set, the immediate byte is the last
6711 operand. */
6712 imm_slot = i.operands - 1;
6713 source--;
6714 reg_slot--;
6715 }
6716 else
6717 {
6718 imm_slot = 0;
6719
6720 /* Turn on Imm8 so that output_imm will generate it. */
6721 i.types[imm_slot].bitfield.imm8 = 1;
6722 }
6723
6724 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6725 i.op[imm_slot].imms->X_add_number
6726 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6727 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
bed3d976 6728 }
a683cc34 6729
10c17abd 6730 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
dae39acc 6731 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6732 }
6733 else
6734 source = dest = 0;
29b0f896
AM		 6735
6736 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6737 implicit registers do not count. If there are 3 register
6738 operands, it must be a instruction with VexNDS. For a
6739 instruction with VexNDD, the destination register is encoded
6740 in VEX prefix. If there are 4 register operands, it must be
6741 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6742 if (i.mem_operands == 0
6743 && ((i.reg_operands == 2
2426c15f 6744 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6745 || (i.reg_operands == 3
2426c15f 6746 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6747 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6748 {
cab737b9
L		 6749 switch (i.operands)
6750 {
6751 case 2:
6752 source = 0;
6753 break;
6754 case 3:
c81128dc
L		 6755 /* When there are 3 operands, one of them may be immediate,
6756 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6757 the first operand must be shift count register (cl) or it
6758 is an instruction with VexNDS. */
9c2799c2 6759 gas_assert (i.imm_operands == 1
7ab9ffdd 6760 || (i.imm_operands == 0
2426c15f 6761 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6762 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6763 if (operand_type_check (i.types[0], imm)
6764 || i.types[0].bitfield.shiftcount)
6765 source = 1;
6766 else
6767 source = 0;
cab737b9
L		 6768 break;
6769 case 4:
368d64cc
L		 6770 /* When there are 4 operands, the first two must be 8bit
6771 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6772 one.
6773
6774 For instructions with VexNDS, if the first operand
6775 an imm8, the source operand is the 2nd one. If the last
6776 operand is imm8, the source operand is the first one. */
9c2799c2 6777 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6778 && i.types[0].bitfield.imm8
6779 && i.types[1].bitfield.imm8)
2426c15f 6780 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6781 && i.imm_operands == 1
6782 && (i.types[0].bitfield.imm8
43234a1e
L		 6783 || i.types[i.operands - 1].bitfield.imm8
6784 || i.rounding)));
9f2670f2
L		 6785 if (i.imm_operands == 2)
6786 source = 2;
6787 else
c0f3af97
L		 6788 {
6789 if (i.types[0].bitfield.imm8)
6790 source = 1;
6791 else
6792 source = 0;
6793 }
c0f3af97
L		 6794 break;
6795 case 5:
e771e7c9 6796 if (is_evex_encoding (&i.tm))
43234a1e
L		 6797 {
6798 /* For EVEX instructions, when there are 5 operands, the
6799 first one must be immediate operand. If the second one
6800 is immediate operand, the source operand is the 3th
6801 one. If the last one is immediate operand, the source
6802 operand is the 2nd one. */
6803 gas_assert (i.imm_operands == 2
6804 && i.tm.opcode_modifier.sae
6805 && operand_type_check (i.types[0], imm));
6806 if (operand_type_check (i.types[1], imm))
6807 source = 2;
6808 else if (operand_type_check (i.types[4], imm))
6809 source = 1;
6810 else
6811 abort ();
6812 }
cab737b9
L		 6813 break;
6814 default:
6815 abort ();
6816 }
6817
c0f3af97
L		 6818 if (!vex_3_sources)
6819 {
6820 dest = source + 1;
6821
43234a1e
L		 6822 /* RC/SAE operand could be between DEST and SRC. That happens
6823 when one operand is GPR and the other one is XMM/YMM/ZMM
6824 register. */
6825 if (i.rounding && i.rounding->operand == (int) dest)
6826 dest++;
6827
2426c15f 6828 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6829 {
43234a1e 6830 /* For instructions with VexNDS, the register-only source
c5d0745b 6831 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
43234a1e
L		 6832 register. It is encoded in VEX prefix. We need to
6833 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6834
6835 i386_operand_type op;
6836 unsigned int vvvv;
6837
6838 /* Check register-only source operand when two source
6839 operands are swapped. */
6840 if (!i.tm.operand_types[source].bitfield.baseindex
6841 && i.tm.operand_types[dest].bitfield.baseindex)
6842 {
6843 vvvv = source;
6844 source = dest;
6845 }
6846 else
6847 vvvv = dest;
6848
6849 op = i.tm.operand_types[vvvv];
fa99fab2 6850 op.bitfield.regmem = 0;
c0f3af97 6851 if ((dest + 1) >= i.operands
dc821c5f
JB		 6852 || ((!op.bitfield.reg
6853 || (!op.bitfield.dword && !op.bitfield.qword))
10c17abd 6854 && !op.bitfield.regsimd
43234a1e 6855 && !operand_type_equal (&op, &regmask)))
c0f3af97 6856 abort ();
f12dc422 6857 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6858 dest++;
6859 }
6860 }
29b0f896
AM		 6861
6862 i.rm.mode = 3;
6863 /* One of the register operands will be encoded in the i.tm.reg
6864 field, the other in the combined i.tm.mode and i.tm.regmem
6865 fields. If no form of this instruction supports a memory
6866 destination operand, then we assume the source operand may
6867 sometimes be a memory operand and so we need to store the
6868 destination in the i.rm.reg field. */
40fb9820
L		 6869 if (!i.tm.operand_types[dest].bitfield.regmem
6870 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6871 {
6872 i.rm.reg = i.op[dest].regs->reg_num;
6873 i.rm.regmem = i.op[source].regs->reg_num;
6874 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6875 i.rex |= REX_R;
43234a1e
L		 6876 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6877 i.vrex |= REX_R;
29b0f896 6878 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6879 i.rex |= REX_B;
43234a1e
L		 6880 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6881 i.vrex |= REX_B;
29b0f896
AM		 6882 }
6883 else
6884 {
6885 i.rm.reg = i.op[source].regs->reg_num;
6886 i.rm.regmem = i.op[dest].regs->reg_num;
6887 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6888 i.rex |= REX_B;
43234a1e
L		 6889 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6890 i.vrex |= REX_B;
29b0f896 6891 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6892 i.rex |= REX_R;
43234a1e
L		 6893 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6894 i.vrex |= REX_R;
29b0f896 6895 }
e0c7f900 6896 if (flag_code != CODE_64BIT && (i.rex & REX_R))
c4a530c5 6897 {
e0c7f900 6898 if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control)
c4a530c5 6899 abort ();
e0c7f900 6900 i.rex &= ~REX_R;
c4a530c5
JB		 6901 add_prefix (LOCK_PREFIX_OPCODE);
6902 }
29b0f896
AM		 6903 }
6904 else
6905 { /* If it's not 2 reg operands... */
c0f3af97
L		 6906 unsigned int mem;
6907
29b0f896
AM		 6908 if (i.mem_operands)
6909 {
6910 unsigned int fake_zero_displacement = 0;
99018f42 6911 unsigned int op;
4eed87de 6912
7ab9ffdd
L		 6913 for (op = 0; op < i.operands; op++)
6914 if (operand_type_check (i.types[op], anymem))
6915 break;
7ab9ffdd 6916 gas_assert (op < i.operands);
29b0f896 6917
6c30d220
L		 6918 if (i.tm.opcode_modifier.vecsib)
6919 {
6920 if (i.index_reg->reg_num == RegEiz
6921 || i.index_reg->reg_num == RegRiz)
6922 abort ();
6923
6924 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6925 if (!i.base_reg)
6926 {
6927 i.sib.base = NO_BASE_REGISTER;
6928 i.sib.scale = i.log2_scale_factor;
6929 i.types[op].bitfield.disp8 = 0;
6930 i.types[op].bitfield.disp16 = 0;
6931 i.types[op].bitfield.disp64 = 0;
43083a50 6932 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6c30d220
L		 6933 {
6934 /* Must be 32 bit */
6935 i.types[op].bitfield.disp32 = 1;
6936 i.types[op].bitfield.disp32s = 0;
6937 }
6938 else
6939 {
6940 i.types[op].bitfield.disp32 = 0;
6941 i.types[op].bitfield.disp32s = 1;
6942 }
6943 }
6944 i.sib.index = i.index_reg->reg_num;
6945 if ((i.index_reg->reg_flags & RegRex) != 0)
6946 i.rex |= REX_X;
43234a1e
L		 6947 if ((i.index_reg->reg_flags & RegVRex) != 0)
6948 i.vrex |= REX_X;
6c30d220
L		 6949 }
6950
29b0f896
AM		 6951 default_seg = &ds;
6952
6953 if (i.base_reg == 0)
6954 {
6955 i.rm.mode = 0;
6956 if (!i.disp_operands)
9bb129e8 6957 fake_zero_displacement = 1;
29b0f896
AM		 6958 if (i.index_reg == 0)
6959 {
73053c1f
JB		 6960 i386_operand_type newdisp;
6961
6c30d220 6962 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6963 /* Operand is just <disp> */
20f0a1fc 6964 if (flag_code == CODE_64BIT)
29b0f896
AM		 6965 {
6966 /* 64bit mode overwrites the 32bit absolute
6967 addressing by RIP relative addressing and
6968 absolute addressing is encoded by one of the
6969 redundant SIB forms. */
6970 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6971 i.sib.base = NO_BASE_REGISTER;
6972 i.sib.index = NO_INDEX_REGISTER;
73053c1f 6973 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
20f0a1fc 6974 }
fc225355
L		 6975 else if ((flag_code == CODE_16BIT)
6976 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6977 {
6978 i.rm.regmem = NO_BASE_REGISTER_16;
73053c1f 6979 newdisp = disp16;
20f0a1fc
NC		 6980 }
6981 else
6982 {
6983 i.rm.regmem = NO_BASE_REGISTER;
73053c1f 6984 newdisp = disp32;
29b0f896 6985 }
73053c1f
JB		 6986 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6987 i.types[op] = operand_type_or (i.types[op], newdisp);
29b0f896 6988 }
6c30d220 6989 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6990 {
6c30d220 6991 /* !i.base_reg && i.index_reg */
db51cc60
L		 6992 if (i.index_reg->reg_num == RegEiz
6993 || i.index_reg->reg_num == RegRiz)
6994 i.sib.index = NO_INDEX_REGISTER;
6995 else
6996 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6997 i.sib.base = NO_BASE_REGISTER;
6998 i.sib.scale = i.log2_scale_factor;
6999 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 7000 i.types[op].bitfield.disp8 = 0;
7001 i.types[op].bitfield.disp16 = 0;
7002 i.types[op].bitfield.disp64 = 0;
43083a50 7003 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
40fb9820
L		 7004 {
7005 /* Must be 32 bit */
7006 i.types[op].bitfield.disp32 = 1;
7007 i.types[op].bitfield.disp32s = 0;
7008 }
29b0f896 7009 else
40fb9820
L		 7010 {
7011 i.types[op].bitfield.disp32 = 0;
7012 i.types[op].bitfield.disp32s = 1;
7013 }
29b0f896 7014 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 7015 i.rex |= REX_X;
29b0f896
AM		 7016 }
7017 }
7018 /* RIP addressing for 64bit mode. */
9a04903e
JB		 7019 else if (i.base_reg->reg_num == RegRip ||
7020 i.base_reg->reg_num == RegEip)
29b0f896 7021 {
6c30d220 7022 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 7023 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 7024 i.types[op].bitfield.disp8 = 0;
7025 i.types[op].bitfield.disp16 = 0;
7026 i.types[op].bitfield.disp32 = 0;
7027 i.types[op].bitfield.disp32s = 1;
7028 i.types[op].bitfield.disp64 = 0;
71903a11 7029 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 7030 if (! i.disp_operands)
7031 fake_zero_displacement = 1;
29b0f896 7032 }
dc821c5f 7033 else if (i.base_reg->reg_type.bitfield.word)
29b0f896 7034 {
6c30d220 7035 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 7036 switch (i.base_reg->reg_num)
7037 {
7038 case 3: /* (%bx) */
7039 if (i.index_reg == 0)
7040 i.rm.regmem = 7;
7041 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7042 i.rm.regmem = i.index_reg->reg_num - 6;
7043 break;
7044 case 5: /* (%bp) */
7045 default_seg = &ss;
7046 if (i.index_reg == 0)
7047 {
7048 i.rm.regmem = 6;
40fb9820 7049 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 7050 {
7051 /* fake (%bp) into 0(%bp) */
b5014f7a 7052 i.types[op].bitfield.disp8 = 1;
252b5132 7053 fake_zero_displacement = 1;
29b0f896
AM		 7054 }
7055 }
7056 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7057 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7058 break;
7059 default: /* (%si) -> 4 or (%di) -> 5 */
7060 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7061 }
7062 i.rm.mode = mode_from_disp_size (i.types[op]);
7063 }
7064 else /* i.base_reg and 32/64 bit mode */
7065 {
7066 if (flag_code == CODE_64BIT
40fb9820
L		 7067 && operand_type_check (i.types[op], disp))
7068 {
73053c1f
JB		 7069 i.types[op].bitfield.disp16 = 0;
7070 i.types[op].bitfield.disp64 = 0;
40fb9820 7071 if (i.prefix[ADDR_PREFIX] == 0)
73053c1f
JB		 7072 {
7073 i.types[op].bitfield.disp32 = 0;
7074 i.types[op].bitfield.disp32s = 1;
7075 }
40fb9820 7076 else
73053c1f
JB		 7077 {
7078 i.types[op].bitfield.disp32 = 1;
7079 i.types[op].bitfield.disp32s = 0;
7080 }
40fb9820 7081 }
20f0a1fc 7082
6c30d220
L		 7083 if (!i.tm.opcode_modifier.vecsib)
7084 i.rm.regmem = i.base_reg->reg_num;
29b0f896 7085 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 7086 i.rex |= REX_B;
29b0f896
AM		 7087 i.sib.base = i.base_reg->reg_num;
7088 /* x86-64 ignores REX prefix bit here to avoid decoder
7089 complications. */
848930b2
JB		 7090 if (!(i.base_reg->reg_flags & RegRex)
7091 && (i.base_reg->reg_num == EBP_REG_NUM
7092 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 7093 default_seg = &ss;
848930b2 7094 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 7095 {
848930b2 7096 fake_zero_displacement = 1;
b5014f7a 7097 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 7098 }
7099 i.sib.scale = i.log2_scale_factor;
7100 if (i.index_reg == 0)
7101 {
6c30d220 7102 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 7103 /* <disp>(%esp) becomes two byte modrm with no index
7104 register. We've already stored the code for esp
7105 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7106 Any base register besides %esp will not use the
7107 extra modrm byte. */
7108 i.sib.index = NO_INDEX_REGISTER;
29b0f896 7109 }
6c30d220 7110 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 7111 {
db51cc60
L		 7112 if (i.index_reg->reg_num == RegEiz
7113 || i.index_reg->reg_num == RegRiz)
7114 i.sib.index = NO_INDEX_REGISTER;
7115 else
7116 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 7117 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7118 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 7119 i.rex |= REX_X;
29b0f896 7120 }
67a4f2b7
AO		 7121
7122 if (i.disp_operands
7123 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7124 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7125 i.rm.mode = 0;
7126 else
a501d77e
L		 7127 {
7128 if (!fake_zero_displacement
7129 && !i.disp_operands
7130 && i.disp_encoding)
7131 {
7132 fake_zero_displacement = 1;
7133 if (i.disp_encoding == disp_encoding_8bit)
7134 i.types[op].bitfield.disp8 = 1;
7135 else
7136 i.types[op].bitfield.disp32 = 1;
7137 }
7138 i.rm.mode = mode_from_disp_size (i.types[op]);
7139 }
29b0f896 7140 }
252b5132 7141
29b0f896
AM		 7142 if (fake_zero_displacement)
7143 {
7144 /* Fakes a zero displacement assuming that i.types[op]
7145 holds the correct displacement size. */
7146 expressionS *exp;
7147
9c2799c2 7148 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 7149 exp = &disp_expressions[i.disp_operands++];
7150 i.op[op].disps = exp;
7151 exp->X_op = O_constant;
7152 exp->X_add_number = 0;
7153 exp->X_add_symbol = (symbolS *) 0;
7154 exp->X_op_symbol = (symbolS *) 0;
7155 }
c0f3af97
L		 7156
7157 mem = op;
29b0f896 7158 }
c0f3af97
L		 7159 else
7160 mem = ~0;
252b5132 7161
8c43a48b 7162 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 7163 {
7164 if (operand_type_check (i.types[0], imm))
7165 i.vex.register_specifier = NULL;
7166 else
7167 {
7168 /* VEX.vvvv encodes one of the sources when the first
7169 operand is not an immediate. */
1ef99a7b 7170 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7171 i.vex.register_specifier = i.op[0].regs;
7172 else
7173 i.vex.register_specifier = i.op[1].regs;
7174 }
7175
7176 /* Destination is a XMM register encoded in the ModRM.reg
7177 and VEX.R bit. */
7178 i.rm.reg = i.op[2].regs->reg_num;
7179 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7180 i.rex |= REX_R;
7181
7182 /* ModRM.rm and VEX.B encodes the other source. */
7183 if (!i.mem_operands)
7184 {
7185 i.rm.mode = 3;
7186
1ef99a7b 7187 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7188 i.rm.regmem = i.op[1].regs->reg_num;
7189 else
7190 i.rm.regmem = i.op[0].regs->reg_num;
7191
7192 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7193 i.rex |= REX_B;
7194 }
7195 }
2426c15f 7196 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 7197 {
7198 i.vex.register_specifier = i.op[2].regs;
7199 if (!i.mem_operands)
7200 {
7201 i.rm.mode = 3;
7202 i.rm.regmem = i.op[1].regs->reg_num;
7203 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7204 i.rex |= REX_B;
7205 }
7206 }
29b0f896
AM		 7207 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7208 (if any) based on i.tm.extension_opcode. Again, we must be
7209 careful to make sure that segment/control/debug/test/MMX
7210 registers are coded into the i.rm.reg field. */
f88c9eb0 7211 else if (i.reg_operands)
29b0f896 7212 {
99018f42 7213 unsigned int op;
7ab9ffdd
L		 7214 unsigned int vex_reg = ~0;
7215
7216 for (op = 0; op < i.operands; op++)
dc821c5f 7217 if (i.types[op].bitfield.reg
7ab9ffdd 7218 || i.types[op].bitfield.regmmx
1b54b8d7 7219 || i.types[op].bitfield.regsimd
7e8b059b 7220 || i.types[op].bitfield.regbnd
43234a1e 7221 || i.types[op].bitfield.regmask
7ab9ffdd
L		 7222 || i.types[op].bitfield.sreg2
7223 || i.types[op].bitfield.sreg3
7224 || i.types[op].bitfield.control
7225 || i.types[op].bitfield.debug
7226 || i.types[op].bitfield.test)
7227 break;
c0209578 7228
7ab9ffdd
L		 7229 if (vex_3_sources)
7230 op = dest;
2426c15f 7231 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 7232 {
7233 /* For instructions with VexNDS, the register-only
7234 source operand is encoded in VEX prefix. */
7235 gas_assert (mem != (unsigned int) ~0);
c0f3af97 7236
7ab9ffdd 7237 if (op > mem)
c0f3af97 7238 {
7ab9ffdd
L		 7239 vex_reg = op++;
7240 gas_assert (op < i.operands);
c0f3af97
L		 7241 }
7242 else
c0f3af97 7243 {
f12dc422
L		 7244 /* Check register-only source operand when two source
7245 operands are swapped. */
7246 if (!i.tm.operand_types[op].bitfield.baseindex
7247 && i.tm.operand_types[op + 1].bitfield.baseindex)
7248 {
7249 vex_reg = op;
7250 op += 2;
7251 gas_assert (mem == (vex_reg + 1)
7252 && op < i.operands);
7253 }
7254 else
7255 {
7256 vex_reg = op + 1;
7257 gas_assert (vex_reg < i.operands);
7258 }
c0f3af97 7259 }
7ab9ffdd 7260 }
2426c15f 7261 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 7262 {
f12dc422 7263 /* For instructions with VexNDD, the register destination
7ab9ffdd 7264 is encoded in VEX prefix. */
f12dc422
L		 7265 if (i.mem_operands == 0)
7266 {
7267 /* There is no memory operand. */
7268 gas_assert ((op + 2) == i.operands);
7269 vex_reg = op + 1;
7270 }
7271 else
8d63c93e 7272 {
ed438a93
JB		 7273 /* There are only 2 non-immediate operands. */
7274 gas_assert (op < i.imm_operands + 2
7275 && i.operands == i.imm_operands + 2);
7276 vex_reg = i.imm_operands + 1;
f12dc422 7277 }
7ab9ffdd
L		 7278 }
7279 else
7280 gas_assert (op < i.operands);
99018f42 7281
7ab9ffdd
L		 7282 if (vex_reg != (unsigned int) ~0)
7283 {
f12dc422 7284 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 7285
dc821c5f
JB		 7286 if ((!type->bitfield.reg
7287 || (!type->bitfield.dword && !type->bitfield.qword))
10c17abd 7288 && !type->bitfield.regsimd
43234a1e 7289 && !operand_type_equal (type, &regmask))
7ab9ffdd 7290 abort ();
f88c9eb0 7291
7ab9ffdd
L		 7292 i.vex.register_specifier = i.op[vex_reg].regs;
7293 }
7294
1b9f0c97
L		 7295 /* Don't set OP operand twice. */
7296 if (vex_reg != op)
7ab9ffdd 7297 {
1b9f0c97
L		 7298 /* If there is an extension opcode to put here, the
7299 register number must be put into the regmem field. */
7300 if (i.tm.extension_opcode != None)
7301 {
7302 i.rm.regmem = i.op[op].regs->reg_num;
7303 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7304 i.rex |= REX_B;
43234a1e
L		 7305 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7306 i.vrex |= REX_B;
1b9f0c97
L		 7307 }
7308 else
7309 {
7310 i.rm.reg = i.op[op].regs->reg_num;
7311 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7312 i.rex |= REX_R;
43234a1e
L		 7313 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7314 i.vrex |= REX_R;
1b9f0c97 7315 }
7ab9ffdd 7316 }
252b5132 7317
29b0f896
AM		 7318 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7319 must set it to 3 to indicate this is a register operand
7320 in the regmem field. */
7321 if (!i.mem_operands)
7322 i.rm.mode = 3;
7323 }
252b5132 7324
29b0f896 7325 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 7326 if (i.tm.extension_opcode != None)
29b0f896
AM		 7327 i.rm.reg = i.tm.extension_opcode;
7328 }
7329 return default_seg;
7330}
252b5132 7331
29b0f896 7332static void
e3bb37b5 7333output_branch (void)
29b0f896
AM		 7334{
7335 char *p;
f8a5c266 7336 int size;
29b0f896
AM		 7337 int code16;
7338 int prefix;
7339 relax_substateT subtype;
7340 symbolS *sym;
7341 offsetT off;
7342
f8a5c266 7343 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 7344 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 7345
7346 prefix = 0;
7347 if (i.prefix[DATA_PREFIX] != 0)
252b5132 7348 {
29b0f896
AM		 7349 prefix = 1;
7350 i.prefixes -= 1;
7351 code16 ^= CODE16;
252b5132 7352 }
29b0f896
AM		 7353 /* Pentium4 branch hints. */
7354 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7355 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 7356 {
29b0f896
AM		 7357 prefix++;
7358 i.prefixes--;
7359 }
7360 if (i.prefix[REX_PREFIX] != 0)
7361 {
7362 prefix++;
7363 i.prefixes--;
2f66722d
AM		 7364 }
7365
7e8b059b
L		 7366 /* BND prefixed jump. */
7367 if (i.prefix[BND_PREFIX] != 0)
7368 {
7369 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7370 i.prefixes -= 1;
7371 }
7372
29b0f896
AM		 7373 if (i.prefixes != 0 && !intel_syntax)
7374 as_warn (_("skipping prefixes on this instruction"));
7375
7376 /* It's always a symbol; End frag & setup for relax.
7377 Make sure there is enough room in this frag for the largest
7378 instruction we may generate in md_convert_frag. This is 2
7379 bytes for the opcode and room for the prefix and largest
7380 displacement. */
7381 frag_grow (prefix + 2 + 4);
7382 /* Prefix and 1 opcode byte go in fr_fix. */
7383 p = frag_more (prefix + 1);
7384 if (i.prefix[DATA_PREFIX] != 0)
7385 *p++ = DATA_PREFIX_OPCODE;
7386 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7387 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7388 *p++ = i.prefix[SEG_PREFIX];
7389 if (i.prefix[REX_PREFIX] != 0)
7390 *p++ = i.prefix[REX_PREFIX];
7391 *p = i.tm.base_opcode;
7392
7393 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 7394 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 7395 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 7396 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 7397 else
f8a5c266 7398 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 7399 subtype |= code16;
3e73aa7c 7400
29b0f896
AM		 7401 sym = i.op[0].disps->X_add_symbol;
7402 off = i.op[0].disps->X_add_number;
3e73aa7c 7403
29b0f896
AM		 7404 if (i.op[0].disps->X_op != O_constant
7405 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7406 {
29b0f896
AM		 7407 /* Handle complex expressions. */
7408 sym = make_expr_symbol (i.op[0].disps);
7409 off = 0;
7410 }
3e73aa7c 7411
29b0f896
AM		 7412 /* 1 possible extra opcode + 4 byte displacement go in var part.
7413 Pass reloc in fr_var. */
d258b828 7414 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7415}
3e73aa7c 7416
bd7ab16b
L		 7417#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7418/* Return TRUE iff PLT32 relocation should be used for branching to
7419 symbol S. */
7420
7421static bfd_boolean
7422need_plt32_p (symbolS *s)
7423{
7424 /* PLT32 relocation is ELF only. */
7425 if (!IS_ELF)
7426 return FALSE;
7427
7428 /* Since there is no need to prepare for PLT branch on x86-64, we
7429 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7430 be used as a marker for 32-bit PC-relative branches. */
7431 if (!object_64bit)
7432 return FALSE;
7433
7434 /* Weak or undefined symbol need PLT32 relocation. */
7435 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7436 return TRUE;
7437
7438 /* Non-global symbol doesn't need PLT32 relocation. */
7439 if (! S_IS_EXTERNAL (s))
7440 return FALSE;
7441
7442 /* Other global symbols need PLT32 relocation. NB: Symbol with
7443 non-default visibilities are treated as normal global symbol
7444 so that PLT32 relocation can be used as a marker for 32-bit
7445 PC-relative branches. It is useful for linker relaxation. */
7446 return TRUE;
7447}
7448#endif
7449
29b0f896 7450static void
e3bb37b5 7451output_jump (void)
29b0f896
AM		 7452{
7453 char *p;
7454 int size;
3e02c1cc 7455 fixS *fixP;
bd7ab16b 7456 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
29b0f896 7457
40fb9820 7458 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7459 {
7460 /* This is a loop or jecxz type instruction. */
7461 size = 1;
7462 if (i.prefix[ADDR_PREFIX] != 0)
7463 {
7464 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7465 i.prefixes -= 1;
7466 }
7467 /* Pentium4 branch hints. */
7468 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7469 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7470 {
7471 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7472 i.prefixes--;
3e73aa7c
JH		 7473 }
7474 }
29b0f896
AM		 7475 else
7476 {
7477 int code16;
3e73aa7c 7478
29b0f896
AM		 7479 code16 = 0;
7480 if (flag_code == CODE_16BIT)
7481 code16 = CODE16;
3e73aa7c 7482
29b0f896
AM		 7483 if (i.prefix[DATA_PREFIX] != 0)
7484 {
7485 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7486 i.prefixes -= 1;
7487 code16 ^= CODE16;
7488 }
252b5132 7489
29b0f896
AM		 7490 size = 4;
7491 if (code16)
7492 size = 2;
7493 }
9fcc94b6 7494
29b0f896
AM		 7495 if (i.prefix[REX_PREFIX] != 0)
7496 {
7497 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7498 i.prefixes -= 1;
7499 }
252b5132 7500
7e8b059b
L		 7501 /* BND prefixed jump. */
7502 if (i.prefix[BND_PREFIX] != 0)
7503 {
7504 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7505 i.prefixes -= 1;
7506 }
7507
29b0f896
AM		 7508 if (i.prefixes != 0 && !intel_syntax)
7509 as_warn (_("skipping prefixes on this instruction"));
e0890092 7510
42164a71
L		 7511 p = frag_more (i.tm.opcode_length + size);
7512 switch (i.tm.opcode_length)
7513 {
7514 case 2:
7515 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7516 /* Fall through. */
42164a71
L		 7517 case 1:
7518 *p++ = i.tm.base_opcode;
7519 break;
7520 default:
7521 abort ();
7522 }
e0890092 7523
bd7ab16b
L		 7524#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7525 if (size == 4
7526 && jump_reloc == NO_RELOC
7527 && need_plt32_p (i.op[0].disps->X_add_symbol))
7528 jump_reloc = BFD_RELOC_X86_64_PLT32;
7529#endif
7530
7531 jump_reloc = reloc (size, 1, 1, jump_reloc);
7532
3e02c1cc 7533 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
bd7ab16b 7534 i.op[0].disps, 1, jump_reloc);
3e02c1cc
AM		 7535
7536 /* All jumps handled here are signed, but don't use a signed limit
7537 check for 32 and 16 bit jumps as we want to allow wrap around at
7538 4G and 64k respectively. */
7539 if (size == 1)
7540 fixP->fx_signed = 1;
29b0f896 7541}
e0890092 7542
29b0f896 7543static void
e3bb37b5 7544output_interseg_jump (void)
29b0f896
AM		 7545{
7546 char *p;
7547 int size;
7548 int prefix;
7549 int code16;
252b5132 7550
29b0f896
AM		 7551 code16 = 0;
7552 if (flag_code == CODE_16BIT)
7553 code16 = CODE16;
a217f122 7554
29b0f896
AM		 7555 prefix = 0;
7556 if (i.prefix[DATA_PREFIX] != 0)
7557 {
7558 prefix = 1;
7559 i.prefixes -= 1;
7560 code16 ^= CODE16;
7561 }
7562 if (i.prefix[REX_PREFIX] != 0)
7563 {
7564 prefix++;
7565 i.prefixes -= 1;
7566 }
252b5132 7567
29b0f896
AM		 7568 size = 4;
7569 if (code16)
7570 size = 2;
252b5132 7571
29b0f896
AM		 7572 if (i.prefixes != 0 && !intel_syntax)
7573 as_warn (_("skipping prefixes on this instruction"));
252b5132 7574
29b0f896
AM		 7575 /* 1 opcode; 2 segment; offset */
7576 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7577
29b0f896
AM		 7578 if (i.prefix[DATA_PREFIX] != 0)
7579 *p++ = DATA_PREFIX_OPCODE;
252b5132 7580
29b0f896
AM		 7581 if (i.prefix[REX_PREFIX] != 0)
7582 *p++ = i.prefix[REX_PREFIX];
252b5132 7583
29b0f896
AM		 7584 *p++ = i.tm.base_opcode;
7585 if (i.op[1].imms->X_op == O_constant)
7586 {
7587 offsetT n = i.op[1].imms->X_add_number;
252b5132 7588
29b0f896
AM		 7589 if (size == 2
7590 && !fits_in_unsigned_word (n)
7591 && !fits_in_signed_word (n))
7592 {
7593 as_bad (_("16-bit jump out of range"));
7594 return;
7595 }
7596 md_number_to_chars (p, n, size);
7597 }
7598 else
7599 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7600 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7601 if (i.op[0].imms->X_op != O_constant)
7602 as_bad (_("can't handle non absolute segment in `%s'"),
7603 i.tm.name);
7604 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7605}
a217f122 7606
29b0f896 7607static void
e3bb37b5 7608output_insn (void)
29b0f896 7609{
2bbd9c25
JJ		 7610 fragS *insn_start_frag;
7611 offsetT insn_start_off;
7612
29b0f896
AM		 7613 /* Tie dwarf2 debug info to the address at the start of the insn.
7614 We can't do this after the insn has been output as the current
7615 frag may have been closed off. eg. by frag_var. */
7616 dwarf2_emit_insn (0);
7617
2bbd9c25
JJ		 7618 insn_start_frag = frag_now;
7619 insn_start_off = frag_now_fix ();
7620
29b0f896 7621 /* Output jumps. */
40fb9820 7622 if (i.tm.opcode_modifier.jump)
29b0f896 7623 output_branch ();
40fb9820
L		 7624 else if (i.tm.opcode_modifier.jumpbyte
7625 || i.tm.opcode_modifier.jumpdword)
29b0f896 7626 output_jump ();
40fb9820 7627 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7628 output_interseg_jump ();
7629 else
7630 {
7631 /* Output normal instructions here. */
7632 char *p;
7633 unsigned char *q;
47465058 7634 unsigned int j;
331d2d0d 7635 unsigned int prefix;
4dffcebc 7636
e4e00185
AS		 7637 if (avoid_fence
7638 && i.tm.base_opcode == 0xfae
7639 && i.operands == 1
7640 && i.imm_operands == 1
7641 && (i.op[0].imms->X_add_number == 0xe8
7642 || i.op[0].imms->X_add_number == 0xf0
7643 || i.op[0].imms->X_add_number == 0xf8))
7644 {
7645 /* Encode lfence, mfence, and sfence as
7646 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7647 offsetT val = 0x240483f0ULL;
7648 p = frag_more (5);
7649 md_number_to_chars (p, val, 5);
7650 return;
7651 }
7652
d022bddd
IT		 7653 /* Some processors fail on LOCK prefix. This options makes
7654 assembler ignore LOCK prefix and serves as a workaround. */
7655 if (omit_lock_prefix)
7656 {
7657 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7658 return;
7659 i.prefix[LOCK_PREFIX] = 0;
7660 }
7661
43234a1e
L		 7662 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7663 don't need the explicit prefix. */
7664 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7665 {
c0f3af97 7666 switch (i.tm.opcode_length)
bc4bd9ab 7667 {
c0f3af97
L		 7668 case 3:
7669 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7670 {
c0f3af97
L		 7671 prefix = (i.tm.base_opcode >> 24) & 0xff;
7672 goto check_prefix;
7673 }
7674 break;
7675 case 2:
7676 if ((i.tm.base_opcode & 0xff0000) != 0)
7677 {
7678 prefix = (i.tm.base_opcode >> 16) & 0xff;
7679 if (i.tm.cpu_flags.bitfield.cpupadlock)
7680 {
4dffcebc 7681check_prefix:
c0f3af97 7682 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7683 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7684 != REPE_PREFIX_OPCODE))
7685 add_prefix (prefix);
7686 }
7687 else
4dffcebc
L		 7688 add_prefix (prefix);
7689 }
c0f3af97
L		 7690 break;
7691 case 1:
7692 break;
390c91cf
L		 7693 case 0:
7694 /* Check for pseudo prefixes. */
7695 as_bad_where (insn_start_frag->fr_file,
7696 insn_start_frag->fr_line,
7697 _("pseudo prefix without instruction"));
7698 return;
c0f3af97
L		 7699 default:
7700 abort ();
bc4bd9ab 7701 }
c0f3af97 7702
6d19a37a 7703#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7704 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7705 R_X86_64_GOTTPOFF relocation so that linker can safely
7706 perform IE->LE optimization. */
7707 if (x86_elf_abi == X86_64_X32_ABI
7708 && i.operands == 2
7709 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7710 && i.prefix[REX_PREFIX] == 0)
7711 add_prefix (REX_OPCODE);
6d19a37a 7712#endif
cf61b747 7713
c0f3af97
L		 7714 /* The prefix bytes. */
7715 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7716 if (*q)
7717 FRAG_APPEND_1_CHAR (*q);
0f10071e 7718 }
ae5c1c7b 7719 else
c0f3af97
L		 7720 {
7721 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7722 if (*q)
7723 switch (j)
7724 {
7725 case REX_PREFIX:
7726 /* REX byte is encoded in VEX prefix. */
7727 break;
7728 case SEG_PREFIX:
7729 case ADDR_PREFIX:
7730 FRAG_APPEND_1_CHAR (*q);
7731 break;
7732 default:
7733 /* There should be no other prefixes for instructions
7734 with VEX prefix. */
7735 abort ();
7736 }
7737
43234a1e
L		 7738 /* For EVEX instructions i.vrex should become 0 after
7739 build_evex_prefix. For VEX instructions upper 16 registers
7740 aren't available, so VREX should be 0. */
7741 if (i.vrex)
7742 abort ();
c0f3af97
L		 7743 /* Now the VEX prefix. */
7744 p = frag_more (i.vex.length);
7745 for (j = 0; j < i.vex.length; j++)
7746 p[j] = i.vex.bytes[j];
7747 }
252b5132 7748
29b0f896 7749 /* Now the opcode; be careful about word order here! */
4dffcebc 7750 if (i.tm.opcode_length == 1)
29b0f896
AM		 7751 {
7752 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7753 }
7754 else
7755 {
4dffcebc 7756 switch (i.tm.opcode_length)
331d2d0d 7757 {
43234a1e
L		 7758 case 4:
7759 p = frag_more (4);
7760 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7761 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7762 break;
4dffcebc 7763 case 3:
331d2d0d
L		 7764 p = frag_more (3);
7765 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7766 break;
7767 case 2:
7768 p = frag_more (2);
7769 break;
7770 default:
7771 abort ();
7772 break;
331d2d0d 7773 }
0f10071e 7774
29b0f896
AM		 7775 /* Put out high byte first: can't use md_number_to_chars! */
7776 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7777 *p = i.tm.base_opcode & 0xff;
7778 }
3e73aa7c 7779
29b0f896 7780 /* Now the modrm byte and sib byte (if present). */
40fb9820 7781 if (i.tm.opcode_modifier.modrm)
29b0f896 7782 {
4a3523fa
L		 7783 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7784 | i.rm.reg << 3
7785 | i.rm.mode << 6));
29b0f896
AM		 7786 /* If i.rm.regmem == ESP (4)
7787 && i.rm.mode != (Register mode)
7788 && not 16 bit
7789 ==> need second modrm byte. */
7790 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7791 && i.rm.mode != 3
dc821c5f 7792 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
4a3523fa
L		 7793 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7794 | i.sib.index << 3
7795 | i.sib.scale << 6));
29b0f896 7796 }
3e73aa7c 7797
29b0f896 7798 if (i.disp_operands)
2bbd9c25 7799 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7800
29b0f896 7801 if (i.imm_operands)
2bbd9c25 7802 output_imm (insn_start_frag, insn_start_off);
29b0f896 7803 }
252b5132 7804
29b0f896
AM		 7805#ifdef DEBUG386
7806 if (flag_debug)
7807 {
7b81dfbb 7808 pi ("" /*line*/, &i);
29b0f896
AM		 7809 }
7810#endif /* DEBUG386 */
7811}
252b5132 7812
e205caa7
L		 7813/* Return the size of the displacement operand N. */
7814
7815static int
7816disp_size (unsigned int n)
7817{
7818 int size = 4;
43234a1e 7819
b5014f7a 7820 if (i.types[n].bitfield.disp64)
40fb9820
L		 7821 size = 8;
7822 else if (i.types[n].bitfield.disp8)
7823 size = 1;
7824 else if (i.types[n].bitfield.disp16)
7825 size = 2;
e205caa7
L		 7826 return size;
7827}
7828
7829/* Return the size of the immediate operand N. */
7830
7831static int
7832imm_size (unsigned int n)
7833{
7834 int size = 4;
40fb9820
L		 7835 if (i.types[n].bitfield.imm64)
7836 size = 8;
7837 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7838 size = 1;
7839 else if (i.types[n].bitfield.imm16)
7840 size = 2;
e205caa7
L		 7841 return size;
7842}
7843
29b0f896 7844static void
64e74474 7845output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7846{
7847 char *p;
7848 unsigned int n;
252b5132 7849
29b0f896
AM		 7850 for (n = 0; n < i.operands; n++)
7851 {
b5014f7a 7852 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 7853 {
7854 if (i.op[n].disps->X_op == O_constant)
7855 {
e205caa7 7856 int size = disp_size (n);
43234a1e 7857 offsetT val = i.op[n].disps->X_add_number;
252b5132 7858
b5014f7a 7859 val = offset_in_range (val >> i.memshift, size);
29b0f896
AM		 7860 p = frag_more (size);
7861 md_number_to_chars (p, val, size);
7862 }
7863 else
7864 {
f86103b7 7865 enum bfd_reloc_code_real reloc_type;
e205caa7 7866 int size = disp_size (n);
40fb9820 7867 int sign = i.types[n].bitfield.disp32s;
29b0f896 7868 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7869 fixS *fixP;
29b0f896 7870
e205caa7 7871 /* We can't have 8 bit displacement here. */
9c2799c2 7872 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7873
29b0f896
AM		 7874 /* The PC relative address is computed relative
7875 to the instruction boundary, so in case immediate
7876 fields follows, we need to adjust the value. */
7877 if (pcrel && i.imm_operands)
7878 {
29b0f896 7879 unsigned int n1;
e205caa7 7880 int sz = 0;
252b5132 7881
29b0f896 7882 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7883 if (operand_type_check (i.types[n1], imm))
252b5132 7884 {
e205caa7
L		 7885 /* Only one immediate is allowed for PC
7886 relative address. */
9c2799c2 7887 gas_assert (sz == 0);
e205caa7
L		 7888 sz = imm_size (n1);
7889 i.op[n].disps->X_add_number -= sz;
252b5132 7890 }
29b0f896 7891 /* We should find the immediate. */
9c2799c2 7892 gas_assert (sz != 0);
29b0f896 7893 }
520dc8e8 7894
29b0f896 7895 p = frag_more (size);
d258b828 7896 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7897 if (GOT_symbol
2bbd9c25 7898 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7899 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7900 || reloc_type == BFD_RELOC_X86_64_32S
7901 || (reloc_type == BFD_RELOC_64
7902 && object_64bit))
d6ab8113
JB		 7903 && (i.op[n].disps->X_op == O_symbol
7904 || (i.op[n].disps->X_op == O_add
7905 && ((symbol_get_value_expression
7906 (i.op[n].disps->X_op_symbol)->X_op)
7907 == O_subtract))))
7908 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7909 {
7910 offsetT add;
7911
7912 if (insn_start_frag == frag_now)
7913 add = (p - frag_now->fr_literal) - insn_start_off;
7914 else
7915 {
7916 fragS *fr;
7917
7918 add = insn_start_frag->fr_fix - insn_start_off;
7919 for (fr = insn_start_frag->fr_next;
7920 fr && fr != frag_now; fr = fr->fr_next)
7921 add += fr->fr_fix;
7922 add += p - frag_now->fr_literal;
7923 }
7924
4fa24527 7925 if (!object_64bit)
7b81dfbb
AJ		 7926 {
7927 reloc_type = BFD_RELOC_386_GOTPC;
7928 i.op[n].imms->X_add_number += add;
7929 }
7930 else if (reloc_type == BFD_RELOC_64)
7931 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7932 else
7b81dfbb
AJ		 7933 /* Don't do the adjustment for x86-64, as there
7934 the pcrel addressing is relative to the _next_
7935 insn, and that is taken care of in other code. */
d6ab8113 7936 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7937 }
02a86693
L		 7938 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7939 size, i.op[n].disps, pcrel,
7940 reloc_type);
7941 /* Check for "call/jmp *mem", "mov mem, %reg",
7942 "test %reg, mem" and "binop mem, %reg" where binop
7943 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7944 instructions. Always generate R_386_GOT32X for
7945 "sym*GOT" operand in 32-bit mode. */
7946 if ((generate_relax_relocations
7947 || (!object_64bit
7948 && i.rm.mode == 0
7949 && i.rm.regmem == 5))
7950 && (i.rm.mode == 2
7951 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7952 && ((i.operands == 1
7953 && i.tm.base_opcode == 0xff
7954 && (i.rm.reg == 2 || i.rm.reg == 4))
7955 || (i.operands == 2
7956 && (i.tm.base_opcode == 0x8b
7957 || i.tm.base_opcode == 0x85
7958 || (i.tm.base_opcode & 0xc7) == 0x03))))
7959 {
7960 if (object_64bit)
7961 {
7962 fixP->fx_tcbit = i.rex != 0;
7963 if (i.base_reg
7964 && (i.base_reg->reg_num == RegRip
7965 || i.base_reg->reg_num == RegEip))
7966 fixP->fx_tcbit2 = 1;
7967 }
7968 else
7969 fixP->fx_tcbit2 = 1;
7970 }
29b0f896
AM		 7971 }
7972 }
7973 }
7974}
252b5132 7975
29b0f896 7976static void
64e74474 7977output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7978{
7979 char *p;
7980 unsigned int n;
252b5132 7981
29b0f896
AM		 7982 for (n = 0; n < i.operands; n++)
7983 {
43234a1e
L		 7984 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7985 if (i.rounding && (int) n == i.rounding->operand)
7986 continue;
7987
40fb9820 7988 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7989 {
7990 if (i.op[n].imms->X_op == O_constant)
7991 {
e205caa7 7992 int size = imm_size (n);
29b0f896 7993 offsetT val;
b4cac588 7994
29b0f896
AM		 7995 val = offset_in_range (i.op[n].imms->X_add_number,
7996 size);
7997 p = frag_more (size);
7998 md_number_to_chars (p, val, size);
7999 }
8000 else
8001 {
8002 /* Not absolute_section.
8003 Need a 32-bit fixup (don't support 8bit
8004 non-absolute imms). Try to support other
8005 sizes ... */
f86103b7 8006 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 8007 int size = imm_size (n);
8008 int sign;
29b0f896 8009
40fb9820 8010 if (i.types[n].bitfield.imm32s
a7d61044 8011 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 8012 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 8013 sign = 1;
e205caa7
L		 8014 else
8015 sign = 0;
520dc8e8 8016
29b0f896 8017 p = frag_more (size);
d258b828 8018 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 8019
2bbd9c25
JJ		 8020 /* This is tough to explain. We end up with this one if we
8021 * have operands that look like
8022 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8023 * obtain the absolute address of the GOT, and it is strongly
8024 * preferable from a performance point of view to avoid using
8025 * a runtime relocation for this. The actual sequence of
8026 * instructions often look something like:
8027 *
8028 * call .L66
8029 * .L66:
8030 * popl %ebx
8031 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8032 *
8033 * The call and pop essentially return the absolute address
8034 * of the label .L66 and store it in %ebx. The linker itself
8035 * will ultimately change the first operand of the addl so
8036 * that %ebx points to the GOT, but to keep things simple, the
8037 * .o file must have this operand set so that it generates not
8038 * the absolute address of .L66, but the absolute address of
8039 * itself. This allows the linker itself simply treat a GOTPC
8040 * relocation as asking for a pcrel offset to the GOT to be
8041 * added in, and the addend of the relocation is stored in the
8042 * operand field for the instruction itself.
8043 *
8044 * Our job here is to fix the operand so that it would add
8045 * the correct offset so that %ebx would point to itself. The
8046 * thing that is tricky is that .-.L66 will point to the
8047 * beginning of the instruction, so we need to further modify
8048 * the operand so that it will point to itself. There are
8049 * other cases where you have something like:
8050 *
8051 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8052 *
8053 * and here no correction would be required. Internally in
8054 * the assembler we treat operands of this form as not being
8055 * pcrel since the '.' is explicitly mentioned, and I wonder
8056 * whether it would simplify matters to do it this way. Who
8057 * knows. In earlier versions of the PIC patches, the
8058 * pcrel_adjust field was used to store the correction, but
8059 * since the expression is not pcrel, I felt it would be
8060 * confusing to do it this way. */
8061
d6ab8113 8062 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 8063 || reloc_type == BFD_RELOC_X86_64_32S
8064 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 8065 && GOT_symbol
8066 && GOT_symbol == i.op[n].imms->X_add_symbol
8067 && (i.op[n].imms->X_op == O_symbol
8068 || (i.op[n].imms->X_op == O_add
8069 && ((symbol_get_value_expression
8070 (i.op[n].imms->X_op_symbol)->X_op)
8071 == O_subtract))))
8072 {
2bbd9c25
JJ		 8073 offsetT add;
8074
8075 if (insn_start_frag == frag_now)
8076 add = (p - frag_now->fr_literal) - insn_start_off;
8077 else
8078 {
8079 fragS *fr;
8080
8081 add = insn_start_frag->fr_fix - insn_start_off;
8082 for (fr = insn_start_frag->fr_next;
8083 fr && fr != frag_now; fr = fr->fr_next)
8084 add += fr->fr_fix;
8085 add += p - frag_now->fr_literal;
8086 }
8087
4fa24527 8088 if (!object_64bit)
d6ab8113 8089 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 8090 else if (size == 4)
d6ab8113 8091 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 8092 else if (size == 8)
8093 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 8094 i.op[n].imms->X_add_number += add;
29b0f896 8095 }
29b0f896
AM		 8096 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8097 i.op[n].imms, 0, reloc_type);
8098 }
8099 }
8100 }
252b5132
RH		 8101}
8102\f
d182319b
JB		 8103/* x86_cons_fix_new is called via the expression parsing code when a
8104 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 8105static int cons_sign = -1;
8106
8107void
e3bb37b5 8108x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 8109 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 8110{
d258b828 8111 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 8112
8113#ifdef TE_PE
8114 if (exp->X_op == O_secrel)
8115 {
8116 exp->X_op = O_symbol;
8117 r = BFD_RELOC_32_SECREL;
8118 }
8119#endif
8120
8121 fix_new_exp (frag, off, len, exp, 0, r);
8122}
8123
357d1bd8
L		 8124/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8125 purpose of the `.dc.a' internal pseudo-op. */
8126
8127int
8128x86_address_bytes (void)
8129{
8130 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8131 return 4;
8132 return stdoutput->arch_info->bits_per_address / 8;
8133}
8134
d382c579
TG		 8135#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8136 || defined (LEX_AT)
d258b828 8137# define lex_got(reloc, adjust, types) NULL
718ddfc0 8138#else
f3c180ae
AM		 8139/* Parse operands of the form
8140 <symbol>@GOTOFF+<nnn>
8141 and similar .plt or .got references.
8142
8143 If we find one, set up the correct relocation in RELOC and copy the
8144 input string, minus the `@GOTOFF' into a malloc'd buffer for
8145 parsing by the calling routine. Return this buffer, and if ADJUST
8146 is non-null set it to the length of the string we removed from the
8147 input line. Otherwise return NULL. */
8148static char *
91d6fa6a 8149lex_got (enum bfd_reloc_code_real *rel,
64e74474 8150 int *adjust,
d258b828 8151 i386_operand_type *types)
f3c180ae 8152{
7b81dfbb
AJ		 8153 /* Some of the relocations depend on the size of what field is to
8154 be relocated. But in our callers i386_immediate and i386_displacement
8155 we don't yet know the operand size (this will be set by insn
8156 matching). Hence we record the word32 relocation here,
8157 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 8158 static const struct {
8159 const char *str;
cff8d58a 8160 int len;
4fa24527 8161 const enum bfd_reloc_code_real rel[2];
40fb9820 8162 const i386_operand_type types64;
f3c180ae 8163 } gotrel[] = {
8ce3d284 8164#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 8165 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8166 BFD_RELOC_SIZE32 },
8167 OPERAND_TYPE_IMM32_64 },
8ce3d284 8168#endif
cff8d58a
L		 8169 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8170 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 8171 OPERAND_TYPE_IMM64 },
cff8d58a
L		 8172 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8173 BFD_RELOC_X86_64_PLT32 },
40fb9820 8174 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8175 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8176 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 8177 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8178 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8179 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 8180 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8181 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8182 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 8183 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8184 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8185 BFD_RELOC_X86_64_TLSGD },
40fb9820 8186 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8187 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8188 _dummy_first_bfd_reloc_code_real },
40fb9820 8189 OPERAND_TYPE_NONE },
cff8d58a
L		 8190 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8191 BFD_RELOC_X86_64_TLSLD },
40fb9820 8192 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8193 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8194 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 8195 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8196 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8197 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 8198 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8199 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8200 _dummy_first_bfd_reloc_code_real },
40fb9820 8201 OPERAND_TYPE_NONE },
cff8d58a
L		 8202 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8203 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 8204 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8205 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8206 _dummy_first_bfd_reloc_code_real },
40fb9820 8207 OPERAND_TYPE_NONE },
cff8d58a
L		 8208 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8209 _dummy_first_bfd_reloc_code_real },
40fb9820 8210 OPERAND_TYPE_NONE },
cff8d58a
L		 8211 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8212 BFD_RELOC_X86_64_GOT32 },
40fb9820 8213 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 8214 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8215 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 8216 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8217 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8218 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 8219 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 8220 };
8221 char *cp;
8222 unsigned int j;
8223
d382c579 8224#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 8225 if (!IS_ELF)
8226 return NULL;
d382c579 8227#endif
718ddfc0 8228
f3c180ae 8229 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 8230 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 8231 return NULL;
8232
47465058 8233 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 8234 {
cff8d58a 8235 int len = gotrel[j].len;
28f81592 8236 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 8237 {
4fa24527 8238 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 8239 {
28f81592
AM		 8240 int first, second;
8241 char *tmpbuf, *past_reloc;
f3c180ae 8242
91d6fa6a 8243 *rel = gotrel[j].rel[object_64bit];
f3c180ae 8244
3956db08
JB		 8245 if (types)
8246 {
8247 if (flag_code != CODE_64BIT)
40fb9820
L		 8248 {
8249 types->bitfield.imm32 = 1;
8250 types->bitfield.disp32 = 1;
8251 }
3956db08
JB		 8252 else
8253 *types = gotrel[j].types64;
8254 }
8255
8fd4256d 8256 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 8257 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8258
28f81592 8259 /* The length of the first part of our input line. */
f3c180ae 8260 first = cp - input_line_pointer;
28f81592
AM		 8261
8262 /* The second part goes from after the reloc token until
67c11a9b 8263 (and including) an end_of_line char or comma. */
28f81592 8264 past_reloc = cp + 1 + len;
67c11a9b
AM		 8265 cp = past_reloc;
8266 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8267 ++cp;
8268 second = cp + 1 - past_reloc;
28f81592
AM		 8269
8270 /* Allocate and copy string. The trailing NUL shouldn't
8271 be necessary, but be safe. */
add39d23 8272 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 8273 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 8274 if (second != 0 && *past_reloc != ' ')
8275 /* Replace the relocation token with ' ', so that
8276 errors like foo@GOTOFF1 will be detected. */
8277 tmpbuf[first++] = ' ';
af89796a
L		 8278 else
8279 /* Increment length by 1 if the relocation token is
8280 removed. */
8281 len++;
8282 if (adjust)
8283 *adjust = len;
0787a12d
AM		 8284 memcpy (tmpbuf + first, past_reloc, second);
8285 tmpbuf[first + second] = '\0';
f3c180ae
AM		 8286 return tmpbuf;
8287 }
8288
4fa24527
JB		 8289 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8290 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 8291 return NULL;
8292 }
8293 }
8294
8295 /* Might be a symbol version string. Don't as_bad here. */
8296 return NULL;
8297}
4e4f7c87 8298#endif
f3c180ae 8299
a988325c
NC		 8300#ifdef TE_PE
8301#ifdef lex_got
8302#undef lex_got
8303#endif
8304/* Parse operands of the form
8305 <symbol>@SECREL32+<nnn>
8306
8307 If we find one, set up the correct relocation in RELOC and copy the
8308 input string, minus the `@SECREL32' into a malloc'd buffer for
8309 parsing by the calling routine. Return this buffer, and if ADJUST
8310 is non-null set it to the length of the string we removed from the
34bca508
L		 8311 input line. Otherwise return NULL.
8312
a988325c
NC		 8313 This function is copied from the ELF version above adjusted for PE targets. */
8314
8315static char *
8316lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8317 int *adjust ATTRIBUTE_UNUSED,
d258b828 8318 i386_operand_type *types)
a988325c
NC		 8319{
8320 static const struct
8321 {
8322 const char *str;
8323 int len;
8324 const enum bfd_reloc_code_real rel[2];
8325 const i386_operand_type types64;
8326 }
8327 gotrel[] =
8328 {
8329 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8330 BFD_RELOC_32_SECREL },
8331 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8332 };
8333
8334 char *cp;
8335 unsigned j;
8336
8337 for (cp = input_line_pointer; *cp != '@'; cp++)
8338 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8339 return NULL;
8340
8341 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8342 {
8343 int len = gotrel[j].len;
8344
8345 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8346 {
8347 if (gotrel[j].rel[object_64bit] != 0)
8348 {
8349 int first, second;
8350 char *tmpbuf, *past_reloc;
8351
8352 *rel = gotrel[j].rel[object_64bit];
8353 if (adjust)
8354 *adjust = len;
8355
8356 if (types)
8357 {
8358 if (flag_code != CODE_64BIT)
8359 {
8360 types->bitfield.imm32 = 1;
8361 types->bitfield.disp32 = 1;
8362 }
8363 else
8364 *types = gotrel[j].types64;
8365 }
8366
8367 /* The length of the first part of our input line. */
8368 first = cp - input_line_pointer;
8369
8370 /* The second part goes from after the reloc token until
8371 (and including) an end_of_line char or comma. */
8372 past_reloc = cp + 1 + len;
8373 cp = past_reloc;
8374 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8375 ++cp;
8376 second = cp + 1 - past_reloc;
8377
8378 /* Allocate and copy string. The trailing NUL shouldn't
8379 be necessary, but be safe. */
add39d23 8380 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 8381 memcpy (tmpbuf, input_line_pointer, first);
8382 if (second != 0 && *past_reloc != ' ')
8383 /* Replace the relocation token with ' ', so that
8384 errors like foo@SECLREL321 will be detected. */
8385 tmpbuf[first++] = ' ';
8386 memcpy (tmpbuf + first, past_reloc, second);
8387 tmpbuf[first + second] = '\0';
8388 return tmpbuf;
8389 }
8390
8391 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8392 gotrel[j].str, 1 << (5 + object_64bit));
8393 return NULL;
8394 }
8395 }
8396
8397 /* Might be a symbol version string. Don't as_bad here. */
8398 return NULL;
8399}
8400
8401#endif /* TE_PE */
8402
62ebcb5c 8403bfd_reloc_code_real_type
e3bb37b5 8404x86_cons (expressionS *exp, int size)
f3c180ae 8405{
62ebcb5c
AM		 8406 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8407
ee86248c
JB		 8408 intel_syntax = -intel_syntax;
8409
3c7b9c2c 8410 exp->X_md = 0;
4fa24527 8411 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 8412 {
8413 /* Handle @GOTOFF and the like in an expression. */
8414 char *save;
8415 char *gotfree_input_line;
4a57f2cf 8416 int adjust = 0;
f3c180ae
AM		 8417
8418 save = input_line_pointer;
d258b828 8419 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 8420 if (gotfree_input_line)
8421 input_line_pointer = gotfree_input_line;
8422
8423 expression (exp);
8424
8425 if (gotfree_input_line)
8426 {
8427 /* expression () has merrily parsed up to the end of line,
8428 or a comma - in the wrong buffer. Transfer how far
8429 input_line_pointer has moved to the right buffer. */
8430 input_line_pointer = (save
8431 + (input_line_pointer - gotfree_input_line)
8432 + adjust);
8433 free (gotfree_input_line);
3992d3b7
AM		 8434 if (exp->X_op == O_constant
8435 || exp->X_op == O_absent
8436 || exp->X_op == O_illegal
0398aac5 8437 || exp->X_op == O_register
3992d3b7
AM		 8438 || exp->X_op == O_big)
8439 {
8440 char c = *input_line_pointer;
8441 *input_line_pointer = 0;
8442 as_bad (_("missing or invalid expression `%s'"), save);
8443 *input_line_pointer = c;
8444 }
f3c180ae
AM		 8445 }
8446 }
8447 else
8448 expression (exp);
ee86248c
JB		 8449
8450 intel_syntax = -intel_syntax;
8451
8452 if (intel_syntax)
8453 i386_intel_simplify (exp);
62ebcb5c
AM		 8454
8455 return got_reloc;
f3c180ae 8456}
f3c180ae 8457
9f32dd5b
L		 8458static void
8459signed_cons (int size)
6482c264 8460{
d182319b
JB		 8461 if (flag_code == CODE_64BIT)
8462 cons_sign = 1;
8463 cons (size);
8464 cons_sign = -1;
6482c264
NC		 8465}
8466
d182319b 8467#ifdef TE_PE
6482c264 8468static void
7016a5d5 8469pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 8470{
8471 expressionS exp;
8472
8473 do
8474 {
8475 expression (&exp);
8476 if (exp.X_op == O_symbol)
8477 exp.X_op = O_secrel;
8478
8479 emit_expr (&exp, 4);
8480 }
8481 while (*input_line_pointer++ == ',');
8482
8483 input_line_pointer--;
8484 demand_empty_rest_of_line ();
8485}
6482c264
NC		 8486#endif
8487
43234a1e
L		 8488/* Handle Vector operations. */
8489
8490static char *
8491check_VecOperations (char *op_string, char *op_end)
8492{
8493 const reg_entry *mask;
8494 const char *saved;
8495 char *end_op;
8496
8497 while (*op_string
8498 && (op_end == NULL || op_string < op_end))
8499 {
8500 saved = op_string;
8501 if (*op_string == '{')
8502 {
8503 op_string++;
8504
8505 /* Check broadcasts. */
8506 if (strncmp (op_string, "1to", 3) == 0)
8507 {
8508 int bcst_type;
8509
8510 if (i.broadcast)
8511 goto duplicated_vec_op;
8512
8513 op_string += 3;
8514 if (*op_string == '8')
8e6e0792 8515 bcst_type = 8;
b28d1bda 8516 else if (*op_string == '4')
8e6e0792 8517 bcst_type = 4;
b28d1bda 8518 else if (*op_string == '2')
8e6e0792 8519 bcst_type = 2;
43234a1e
L		 8520 else if (*op_string == '1'
8521 && *(op_string+1) == '6')
8522 {
8e6e0792 8523 bcst_type = 16;
43234a1e
L		 8524 op_string++;
8525 }
8526 else
8527 {
8528 as_bad (_("Unsupported broadcast: `%s'"), saved);
8529 return NULL;
8530 }
8531 op_string++;
8532
8533 broadcast_op.type = bcst_type;
8534 broadcast_op.operand = this_operand;
8535 i.broadcast = &broadcast_op;
8536 }
8537 /* Check masking operation. */
8538 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8539 {
8540 /* k0 can't be used for write mask. */
6d2cd6b2 8541 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
43234a1e 8542 {
6d2cd6b2
JB		 8543 as_bad (_("`%s%s' can't be used for write mask"),
8544 register_prefix, mask->reg_name);
43234a1e
L		 8545 return NULL;
8546 }
8547
8548 if (!i.mask)
8549 {
8550 mask_op.mask = mask;
8551 mask_op.zeroing = 0;
8552 mask_op.operand = this_operand;
8553 i.mask = &mask_op;
8554 }
8555 else
8556 {
8557 if (i.mask->mask)
8558 goto duplicated_vec_op;
8559
8560 i.mask->mask = mask;
8561
8562 /* Only "{z}" is allowed here. No need to check
8563 zeroing mask explicitly. */
8564 if (i.mask->operand != this_operand)
8565 {
8566 as_bad (_("invalid write mask `%s'"), saved);
8567 return NULL;
8568 }
8569 }
8570
8571 op_string = end_op;
8572 }
8573 /* Check zeroing-flag for masking operation. */
8574 else if (*op_string == 'z')
8575 {
8576 if (!i.mask)
8577 {
8578 mask_op.mask = NULL;
8579 mask_op.zeroing = 1;
8580 mask_op.operand = this_operand;
8581 i.mask = &mask_op;
8582 }
8583 else
8584 {
8585 if (i.mask->zeroing)
8586 {
8587 duplicated_vec_op:
8588 as_bad (_("duplicated `%s'"), saved);
8589 return NULL;
8590 }
8591
8592 i.mask->zeroing = 1;
8593
8594 /* Only "{%k}" is allowed here. No need to check mask
8595 register explicitly. */
8596 if (i.mask->operand != this_operand)
8597 {
8598 as_bad (_("invalid zeroing-masking `%s'"),
8599 saved);
8600 return NULL;
8601 }
8602 }
8603
8604 op_string++;
8605 }
8606 else
8607 goto unknown_vec_op;
8608
8609 if (*op_string != '}')
8610 {
8611 as_bad (_("missing `}' in `%s'"), saved);
8612 return NULL;
8613 }
8614 op_string++;
0ba3a731
L		 8615
8616 /* Strip whitespace since the addition of pseudo prefixes
8617 changed how the scrubber treats '{'. */
8618 if (is_space_char (*op_string))
8619 ++op_string;
8620
43234a1e
L		 8621 continue;
8622 }
8623 unknown_vec_op:
8624 /* We don't know this one. */
8625 as_bad (_("unknown vector operation: `%s'"), saved);
8626 return NULL;
8627 }
8628
6d2cd6b2
JB		 8629 if (i.mask && i.mask->zeroing && !i.mask->mask)
8630 {
8631 as_bad (_("zeroing-masking only allowed with write mask"));
8632 return NULL;
8633 }
8634
43234a1e
L		 8635 return op_string;
8636}
8637
252b5132 8638static int
70e41ade 8639i386_immediate (char *imm_start)
252b5132
RH		 8640{
8641 char *save_input_line_pointer;
f3c180ae 8642 char *gotfree_input_line;
252b5132 8643 segT exp_seg = 0;
47926f60 8644 expressionS *exp;
40fb9820
L		 8645 i386_operand_type types;
8646
0dfbf9d7 8647 operand_type_set (&types, ~0);
252b5132
RH		 8648
8649 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8650 {
31b2323c
L		 8651 as_bad (_("at most %d immediate operands are allowed"),
8652 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8653 return 0;
8654 }
8655
8656 exp = &im_expressions[i.imm_operands++];
520dc8e8 8657 i.op[this_operand].imms = exp;
252b5132
RH		 8658
8659 if (is_space_char (*imm_start))
8660 ++imm_start;
8661
8662 save_input_line_pointer = input_line_pointer;
8663 input_line_pointer = imm_start;
8664
d258b828 8665 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8666 if (gotfree_input_line)
8667 input_line_pointer = gotfree_input_line;
252b5132
RH		 8668
8669 exp_seg = expression (exp);
8670
83183c0c 8671 SKIP_WHITESPACE ();
43234a1e
L		 8672
8673 /* Handle vector operations. */
8674 if (*input_line_pointer == '{')
8675 {
8676 input_line_pointer = check_VecOperations (input_line_pointer,
8677 NULL);
8678 if (input_line_pointer == NULL)
8679 return 0;
8680 }
8681
252b5132 8682 if (*input_line_pointer)
f3c180ae 8683 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8684
8685 input_line_pointer = save_input_line_pointer;
f3c180ae 8686 if (gotfree_input_line)
ee86248c
JB		 8687 {
8688 free (gotfree_input_line);
8689
8690 if (exp->X_op == O_constant || exp->X_op == O_register)
8691 exp->X_op = O_illegal;
8692 }
8693
8694 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8695}
252b5132 8696
ee86248c
JB		 8697static int
8698i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8699 i386_operand_type types, const char *imm_start)
8700{
8701 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8702 {
313c53d1
L		 8703 if (imm_start)
8704 as_bad (_("missing or invalid immediate expression `%s'"),
8705 imm_start);
3992d3b7 8706 return 0;
252b5132 8707 }
3e73aa7c 8708 else if (exp->X_op == O_constant)
252b5132 8709 {
47926f60 8710 /* Size it properly later. */
40fb9820 8711 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8712 /* If not 64bit, sign extend val. */
8713 if (flag_code != CODE_64BIT
4eed87de
AM		 8714 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8715 exp->X_add_number
8716 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8717 }
4c63da97 8718#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8719 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8720 && exp_seg != absolute_section
47926f60 8721 && exp_seg != text_section
24eab124
AM		 8722 && exp_seg != data_section
8723 && exp_seg != bss_section
8724 && exp_seg != undefined_section
f86103b7 8725 && !bfd_is_com_section (exp_seg))
252b5132 8726 {
d0b47220 8727 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8728 return 0;
8729 }
8730#endif
a841bdf5 8731 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8732 {
313c53d1
L		 8733 if (imm_start)
8734 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8735 return 0;
8736 }
252b5132
RH		 8737 else
8738 {
8739 /* This is an address. The size of the address will be
24eab124 8740 determined later, depending on destination register,
3e73aa7c 8741 suffix, or the default for the section. */
40fb9820
L		 8742 i.types[this_operand].bitfield.imm8 = 1;
8743 i.types[this_operand].bitfield.imm16 = 1;
8744 i.types[this_operand].bitfield.imm32 = 1;
8745 i.types[this_operand].bitfield.imm32s = 1;
8746 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8747 i.types[this_operand] = operand_type_and (i.types[this_operand],
8748 types);
252b5132
RH		 8749 }
8750
8751 return 1;
8752}
8753
551c1ca1 8754static char *
e3bb37b5 8755i386_scale (char *scale)
252b5132 8756{
551c1ca1
AM		 8757 offsetT val;
8758 char *save = input_line_pointer;
252b5132 8759
551c1ca1
AM		 8760 input_line_pointer = scale;
8761 val = get_absolute_expression ();
8762
8763 switch (val)
252b5132 8764 {
551c1ca1 8765 case 1:
252b5132
RH		 8766 i.log2_scale_factor = 0;
8767 break;
551c1ca1 8768 case 2:
252b5132
RH		 8769 i.log2_scale_factor = 1;
8770 break;
551c1ca1 8771 case 4:
252b5132
RH		 8772 i.log2_scale_factor = 2;
8773 break;
551c1ca1 8774 case 8:
252b5132
RH		 8775 i.log2_scale_factor = 3;
8776 break;
8777 default:
a724f0f4
JB		 8778 {
8779 char sep = *input_line_pointer;
8780
8781 *input_line_pointer = '\0';
8782 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8783 scale);
8784 *input_line_pointer = sep;
8785 input_line_pointer = save;
8786 return NULL;
8787 }
252b5132 8788 }
29b0f896 8789 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8790 {
8791 as_warn (_("scale factor of %d without an index register"),
24eab124 8792 1 << i.log2_scale_factor);
252b5132 8793 i.log2_scale_factor = 0;
252b5132 8794 }
551c1ca1
AM		 8795 scale = input_line_pointer;
8796 input_line_pointer = save;
8797 return scale;
252b5132
RH		 8798}
8799
252b5132 8800static int
e3bb37b5 8801i386_displacement (char *disp_start, char *disp_end)
252b5132 8802{
29b0f896 8803 expressionS *exp;
252b5132
RH		 8804 segT exp_seg = 0;
8805 char *save_input_line_pointer;
f3c180ae 8806 char *gotfree_input_line;
40fb9820
L		 8807 int override;
8808 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8809 int ret;
252b5132 8810
31b2323c
L		 8811 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8812 {
8813 as_bad (_("at most %d displacement operands are allowed"),
8814 MAX_MEMORY_OPERANDS);
8815 return 0;
8816 }
8817
0dfbf9d7 8818 operand_type_set (&bigdisp, 0);
40fb9820
L		 8819 if ((i.types[this_operand].bitfield.jumpabsolute)
8820 || (!current_templates->start->opcode_modifier.jump
8821 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8822 {
40fb9820 8823 bigdisp.bitfield.disp32 = 1;
e05278af 8824 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8825 if (flag_code == CODE_64BIT)
8826 {
8827 if (!override)
8828 {
8829 bigdisp.bitfield.disp32s = 1;
8830 bigdisp.bitfield.disp64 = 1;
8831 }
8832 }
8833 else if ((flag_code == CODE_16BIT) ^ override)
8834 {
8835 bigdisp.bitfield.disp32 = 0;
8836 bigdisp.bitfield.disp16 = 1;
8837 }
e05278af
JB		 8838 }
8839 else
8840 {
8841 /* For PC-relative branches, the width of the displacement
8842 is dependent upon data size, not address size. */
e05278af 8843 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8844 if (flag_code == CODE_64BIT)
8845 {
8846 if (override || i.suffix == WORD_MNEM_SUFFIX)
8847 bigdisp.bitfield.disp16 = 1;
8848 else
8849 {
8850 bigdisp.bitfield.disp32 = 1;
8851 bigdisp.bitfield.disp32s = 1;
8852 }
8853 }
8854 else
e05278af
JB		 8855 {
8856 if (!override)
8857 override = (i.suffix == (flag_code != CODE_16BIT
8858 ? WORD_MNEM_SUFFIX
8859 : LONG_MNEM_SUFFIX));
40fb9820
L		 8860 bigdisp.bitfield.disp32 = 1;
8861 if ((flag_code == CODE_16BIT) ^ override)
8862 {
8863 bigdisp.bitfield.disp32 = 0;
8864 bigdisp.bitfield.disp16 = 1;
8865 }
e05278af 8866 }
e05278af 8867 }
c6fb90c8
L		 8868 i.types[this_operand] = operand_type_or (i.types[this_operand],
8869 bigdisp);
252b5132
RH		 8870
8871 exp = &disp_expressions[i.disp_operands];
520dc8e8 8872 i.op[this_operand].disps = exp;
252b5132
RH		 8873 i.disp_operands++;
8874 save_input_line_pointer = input_line_pointer;
8875 input_line_pointer = disp_start;
8876 END_STRING_AND_SAVE (disp_end);
8877
8878#ifndef GCC_ASM_O_HACK
8879#define GCC_ASM_O_HACK 0
8880#endif
8881#if GCC_ASM_O_HACK
8882 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8883 if (i.types[this_operand].bitfield.baseIndex
24eab124 8884 && displacement_string_end[-1] == '+')
252b5132
RH		 8885 {
8886 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8887 constraint within gcc asm statements.
8888 For instance:
8889
8890 #define _set_tssldt_desc(n,addr,limit,type) \
8891 __asm__ __volatile__ ( \
8892 "movw %w2,%0\n\t" \
8893 "movw %w1,2+%0\n\t" \
8894 "rorl $16,%1\n\t" \
8895 "movb %b1,4+%0\n\t" \
8896 "movb %4,5+%0\n\t" \
8897 "movb $0,6+%0\n\t" \
8898 "movb %h1,7+%0\n\t" \
8899 "rorl $16,%1" \
8900 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8901
8902 This works great except that the output assembler ends
8903 up looking a bit weird if it turns out that there is
8904 no offset. You end up producing code that looks like:
8905
8906 #APP
8907 movw $235,(%eax)
8908 movw %dx,2+(%eax)
8909 rorl $16,%edx
8910 movb %dl,4+(%eax)
8911 movb $137,5+(%eax)
8912 movb $0,6+(%eax)
8913 movb %dh,7+(%eax)
8914 rorl $16,%edx
8915 #NO_APP
8916
47926f60 8917 So here we provide the missing zero. */
24eab124
AM		 8918
8919 *displacement_string_end = '0';
252b5132
RH		 8920 }
8921#endif
d258b828 8922 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8923 if (gotfree_input_line)
8924 input_line_pointer = gotfree_input_line;
252b5132 8925
24eab124 8926 exp_seg = expression (exp);
252b5132 8927
636c26b0
AM		 8928 SKIP_WHITESPACE ();
8929 if (*input_line_pointer)
8930 as_bad (_("junk `%s' after expression"), input_line_pointer);
8931#if GCC_ASM_O_HACK
8932 RESTORE_END_STRING (disp_end + 1);
8933#endif
636c26b0 8934 input_line_pointer = save_input_line_pointer;
636c26b0 8935 if (gotfree_input_line)
ee86248c
JB		 8936 {
8937 free (gotfree_input_line);
8938
8939 if (exp->X_op == O_constant || exp->X_op == O_register)
8940 exp->X_op = O_illegal;
8941 }
8942
8943 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8944
8945 RESTORE_END_STRING (disp_end);
8946
8947 return ret;
8948}
8949
8950static int
8951i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8952 i386_operand_type types, const char *disp_start)
8953{
8954 i386_operand_type bigdisp;
8955 int ret = 1;
636c26b0 8956
24eab124
AM		 8957 /* We do this to make sure that the section symbol is in
8958 the symbol table. We will ultimately change the relocation
47926f60 8959 to be relative to the beginning of the section. */
1ae12ab7 8960 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8961 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8962 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8963 {
636c26b0 8964 if (exp->X_op != O_symbol)
3992d3b7 8965 goto inv_disp;
636c26b0 8966
e5cb08ac 8967 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8968 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8969 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8970 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8971 exp->X_op = O_subtract;
8972 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8973 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8974 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8975 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8976 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8977 else
29b0f896 8978 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8979 }
252b5132 8980
3992d3b7
AM		 8981 else if (exp->X_op == O_absent
8982 || exp->X_op == O_illegal
ee86248c 8983 || exp->X_op == O_big)
2daf4fd8 8984 {
3992d3b7
AM		 8985 inv_disp:
8986 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8987 disp_start);
3992d3b7 8988 ret = 0;
2daf4fd8
AM		 8989 }
8990
0e1147d9
L		 8991 else if (flag_code == CODE_64BIT
8992 && !i.prefix[ADDR_PREFIX]
8993 && exp->X_op == O_constant)
8994 {
8995 /* Since displacement is signed extended to 64bit, don't allow
8996 disp32 and turn off disp32s if they are out of range. */
8997 i.types[this_operand].bitfield.disp32 = 0;
8998 if (!fits_in_signed_long (exp->X_add_number))
8999 {
9000 i.types[this_operand].bitfield.disp32s = 0;
9001 if (i.types[this_operand].bitfield.baseindex)
9002 {
9003 as_bad (_("0x%lx out range of signed 32bit displacement"),
9004 (long) exp->X_add_number);
9005 ret = 0;
9006 }
9007 }
9008 }
9009
4c63da97 9010#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 9011 else if (exp->X_op != O_constant
9012 && OUTPUT_FLAVOR == bfd_target_aout_flavour
9013 && exp_seg != absolute_section
9014 && exp_seg != text_section
9015 && exp_seg != data_section
9016 && exp_seg != bss_section
9017 && exp_seg != undefined_section
9018 && !bfd_is_com_section (exp_seg))
24eab124 9019 {
d0b47220 9020 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 9021 ret = 0;
24eab124 9022 }
252b5132 9023#endif
3956db08 9024
40fb9820
L		 9025 /* Check if this is a displacement only operand. */
9026 bigdisp = i.types[this_operand];
9027 bigdisp.bitfield.disp8 = 0;
9028 bigdisp.bitfield.disp16 = 0;
9029 bigdisp.bitfield.disp32 = 0;
9030 bigdisp.bitfield.disp32s = 0;
9031 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 9032 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 9033 i.types[this_operand] = operand_type_and (i.types[this_operand],
9034 types);
3956db08 9035
3992d3b7 9036 return ret;
252b5132
RH		 9037}
9038
2abc2bec
JB		 9039/* Return the active addressing mode, taking address override and
9040 registers forming the address into consideration. Update the
9041 address override prefix if necessary. */
47926f60 9042
2abc2bec
JB		 9043static enum flag_code
9044i386_addressing_mode (void)
252b5132 9045{
be05d201
L		 9046 enum flag_code addr_mode;
9047
9048 if (i.prefix[ADDR_PREFIX])
9049 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9050 else
9051 {
9052 addr_mode = flag_code;
9053
24eab124 9054#if INFER_ADDR_PREFIX
be05d201
L		 9055 if (i.mem_operands == 0)
9056 {
9057 /* Infer address prefix from the first memory operand. */
9058 const reg_entry *addr_reg = i.base_reg;
9059
9060 if (addr_reg == NULL)
9061 addr_reg = i.index_reg;
eecb386c 9062
be05d201
L		 9063 if (addr_reg)
9064 {
9065 if (addr_reg->reg_num == RegEip
9066 || addr_reg->reg_num == RegEiz
dc821c5f 9067 || addr_reg->reg_type.bitfield.dword)
be05d201
L		 9068 addr_mode = CODE_32BIT;
9069 else if (flag_code != CODE_64BIT
dc821c5f 9070 && addr_reg->reg_type.bitfield.word)
be05d201
L		 9071 addr_mode = CODE_16BIT;
9072
9073 if (addr_mode != flag_code)
9074 {
9075 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9076 i.prefixes += 1;
9077 /* Change the size of any displacement too. At most one
9078 of Disp16 or Disp32 is set.
9079 FIXME. There doesn't seem to be any real need for
9080 separate Disp16 and Disp32 flags. The same goes for
9081 Imm16 and Imm32. Removing them would probably clean
9082 up the code quite a lot. */
9083 if (flag_code != CODE_64BIT
9084 && (i.types[this_operand].bitfield.disp16
9085 || i.types[this_operand].bitfield.disp32))
9086 i.types[this_operand]
9087 = operand_type_xor (i.types[this_operand], disp16_32);
9088 }
9089 }
9090 }
24eab124 9091#endif
be05d201
L		 9092 }
9093
2abc2bec
JB		 9094 return addr_mode;
9095}
9096
9097/* Make sure the memory operand we've been dealt is valid.
9098 Return 1 on success, 0 on a failure. */
9099
9100static int
9101i386_index_check (const char *operand_string)
9102{
9103 const char *kind = "base/index";
9104 enum flag_code addr_mode = i386_addressing_mode ();
9105
fc0763e6
JB		 9106 if (current_templates->start->opcode_modifier.isstring
9107 && !current_templates->start->opcode_modifier.immext
9108 && (current_templates->end[-1].opcode_modifier.isstring
9109 || i.mem_operands))
9110 {
9111 /* Memory operands of string insns are special in that they only allow
9112 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 9113 const reg_entry *expected_reg;
9114 static const char *di_si[][2] =
9115 {
9116 { "esi", "edi" },
9117 { "si", "di" },
9118 { "rsi", "rdi" }
9119 };
9120 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 9121
9122 kind = "string address";
9123
8325cc63 9124 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 9125 {
9126 i386_operand_type type = current_templates->end[-1].operand_types[0];
9127
9128 if (!type.bitfield.baseindex
9129 || ((!i.mem_operands != !intel_syntax)
9130 && current_templates->end[-1].operand_types[1]
9131 .bitfield.baseindex))
9132 type = current_templates->end[-1].operand_types[1];
be05d201
L		 9133 expected_reg = hash_find (reg_hash,
9134 di_si[addr_mode][type.bitfield.esseg]);
9135
fc0763e6
JB		 9136 }
9137 else
be05d201 9138 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 9139
be05d201
L		 9140 if (i.base_reg != expected_reg
9141 || i.index_reg
fc0763e6 9142 || operand_type_check (i.types[this_operand], disp))
fc0763e6 9143 {
be05d201
L		 9144 /* The second memory operand must have the same size as
9145 the first one. */
9146 if (i.mem_operands
9147 && i.base_reg
9148 && !((addr_mode == CODE_64BIT
dc821c5f 9149 && i.base_reg->reg_type.bitfield.qword)
be05d201 9150 || (addr_mode == CODE_32BIT
dc821c5f
JB		 9151 ? i.base_reg->reg_type.bitfield.dword
9152 : i.base_reg->reg_type.bitfield.word)))
be05d201
L		 9153 goto bad_address;
9154
fc0763e6
JB		 9155 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9156 operand_string,
9157 intel_syntax ? '[' : '(',
9158 register_prefix,
be05d201 9159 expected_reg->reg_name,
fc0763e6 9160 intel_syntax ? ']' : ')');
be05d201 9161 return 1;
fc0763e6 9162 }
be05d201
L		 9163 else
9164 return 1;
9165
9166bad_address:
9167 as_bad (_("`%s' is not a valid %s expression"),
9168 operand_string, kind);
9169 return 0;
3e73aa7c
JH		 9170 }
9171 else
9172 {
be05d201
L		 9173 if (addr_mode != CODE_16BIT)
9174 {
9175 /* 32-bit/64-bit checks. */
9176 if ((i.base_reg
9177 && (addr_mode == CODE_64BIT
dc821c5f
JB		 9178 ? !i.base_reg->reg_type.bitfield.qword
9179 : !i.base_reg->reg_type.bitfield.dword)
be05d201
L		 9180 && (i.index_reg
9181 || (i.base_reg->reg_num
9182 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9183 || (i.index_reg
1b54b8d7
JB		 9184 && !i.index_reg->reg_type.bitfield.xmmword
9185 && !i.index_reg->reg_type.bitfield.ymmword
9186 && !i.index_reg->reg_type.bitfield.zmmword
be05d201 9187 && ((addr_mode == CODE_64BIT
dc821c5f 9188 ? !(i.index_reg->reg_type.bitfield.qword
be05d201 9189 || i.index_reg->reg_num == RegRiz)
dc821c5f 9190 : !(i.index_reg->reg_type.bitfield.dword
be05d201
L		 9191 || i.index_reg->reg_num == RegEiz))
9192 || !i.index_reg->reg_type.bitfield.baseindex)))
9193 goto bad_address;
8178be5b
JB		 9194
9195 /* bndmk, bndldx, and bndstx have special restrictions. */
9196 if (current_templates->start->base_opcode == 0xf30f1b
9197 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9198 {
9199 /* They cannot use RIP-relative addressing. */
9200 if (i.base_reg && i.base_reg->reg_num == RegRip)
9201 {
9202 as_bad (_("`%s' cannot be used here"), operand_string);
9203 return 0;
9204 }
9205
9206 /* bndldx and bndstx ignore their scale factor. */
9207 if (current_templates->start->base_opcode != 0xf30f1b
9208 && i.log2_scale_factor)
9209 as_warn (_("register scaling is being ignored here"));
9210 }
be05d201
L		 9211 }
9212 else
3e73aa7c 9213 {
be05d201 9214 /* 16-bit checks. */
3e73aa7c 9215 if ((i.base_reg
dc821c5f 9216 && (!i.base_reg->reg_type.bitfield.word
40fb9820 9217 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 9218 || (i.index_reg
dc821c5f 9219 && (!i.index_reg->reg_type.bitfield.word
40fb9820 9220 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 9221 || !(i.base_reg
9222 && i.base_reg->reg_num < 6
9223 && i.index_reg->reg_num >= 6
9224 && i.log2_scale_factor == 0))))
be05d201 9225 goto bad_address;
3e73aa7c
JH		 9226 }
9227 }
be05d201 9228 return 1;
24eab124 9229}
252b5132 9230
43234a1e
L		 9231/* Handle vector immediates. */
9232
9233static int
9234RC_SAE_immediate (const char *imm_start)
9235{
9236 unsigned int match_found, j;
9237 const char *pstr = imm_start;
9238 expressionS *exp;
9239
9240 if (*pstr != '{')
9241 return 0;
9242
9243 pstr++;
9244 match_found = 0;
9245 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9246 {
9247 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9248 {
9249 if (!i.rounding)
9250 {
9251 rc_op.type = RC_NamesTable[j].type;
9252 rc_op.operand = this_operand;
9253 i.rounding = &rc_op;
9254 }
9255 else
9256 {
9257 as_bad (_("duplicated `%s'"), imm_start);
9258 return 0;
9259 }
9260 pstr += RC_NamesTable[j].len;
9261 match_found = 1;
9262 break;
9263 }
9264 }
9265 if (!match_found)
9266 return 0;
9267
9268 if (*pstr++ != '}')
9269 {
9270 as_bad (_("Missing '}': '%s'"), imm_start);
9271 return 0;
9272 }
9273 /* RC/SAE immediate string should contain nothing more. */;
9274 if (*pstr != 0)
9275 {
9276 as_bad (_("Junk after '}': '%s'"), imm_start);
9277 return 0;
9278 }
9279
9280 exp = &im_expressions[i.imm_operands++];
9281 i.op[this_operand].imms = exp;
9282
9283 exp->X_op = O_constant;
9284 exp->X_add_number = 0;
9285 exp->X_add_symbol = (symbolS *) 0;
9286 exp->X_op_symbol = (symbolS *) 0;
9287
9288 i.types[this_operand].bitfield.imm8 = 1;
9289 return 1;
9290}
9291
8325cc63
JB		 9292/* Only string instructions can have a second memory operand, so
9293 reduce current_templates to just those if it contains any. */
9294static int
9295maybe_adjust_templates (void)
9296{
9297 const insn_template *t;
9298
9299 gas_assert (i.mem_operands == 1);
9300
9301 for (t = current_templates->start; t < current_templates->end; ++t)
9302 if (t->opcode_modifier.isstring)
9303 break;
9304
9305 if (t < current_templates->end)
9306 {
9307 static templates aux_templates;
9308 bfd_boolean recheck;
9309
9310 aux_templates.start = t;
9311 for (; t < current_templates->end; ++t)
9312 if (!t->opcode_modifier.isstring)
9313 break;
9314 aux_templates.end = t;
9315
9316 /* Determine whether to re-check the first memory operand. */
9317 recheck = (aux_templates.start != current_templates->start
9318 || t != current_templates->end);
9319
9320 current_templates = &aux_templates;
9321
9322 if (recheck)
9323 {
9324 i.mem_operands = 0;
9325 if (i.memop1_string != NULL
9326 && i386_index_check (i.memop1_string) == 0)
9327 return 0;
9328 i.mem_operands = 1;
9329 }
9330 }
9331
9332 return 1;
9333}
9334
fc0763e6 9335/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 9336 on error. */
252b5132 9337
252b5132 9338static int
a7619375 9339i386_att_operand (char *operand_string)
252b5132 9340{
af6bdddf
AM		 9341 const reg_entry *r;
9342 char *end_op;
24eab124 9343 char *op_string = operand_string;
252b5132 9344
24eab124 9345 if (is_space_char (*op_string))
252b5132
RH		 9346 ++op_string;
9347
24eab124 9348 /* We check for an absolute prefix (differentiating,
47926f60 9349 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 9350 if (*op_string == ABSOLUTE_PREFIX)
9351 {
9352 ++op_string;
9353 if (is_space_char (*op_string))
9354 ++op_string;
40fb9820 9355 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 9356 }
252b5132 9357
47926f60 9358 /* Check if operand is a register. */
4d1bb795 9359 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 9360 {
40fb9820
L		 9361 i386_operand_type temp;
9362
24eab124
AM		 9363 /* Check for a segment override by searching for ':' after a
9364 segment register. */
9365 op_string = end_op;
9366 if (is_space_char (*op_string))
9367 ++op_string;
40fb9820
L		 9368 if (*op_string == ':'
9369 && (r->reg_type.bitfield.sreg2
9370 || r->reg_type.bitfield.sreg3))
24eab124
AM		 9371 {
9372 switch (r->reg_num)
9373 {
9374 case 0:
9375 i.seg[i.mem_operands] = &es;
9376 break;
9377 case 1:
9378 i.seg[i.mem_operands] = &cs;
9379 break;
9380 case 2:
9381 i.seg[i.mem_operands] = &ss;
9382 break;
9383 case 3:
9384 i.seg[i.mem_operands] = &ds;
9385 break;
9386 case 4:
9387 i.seg[i.mem_operands] = &fs;
9388 break;
9389 case 5:
9390 i.seg[i.mem_operands] = &gs;
9391 break;
9392 }
252b5132 9393
24eab124 9394 /* Skip the ':' and whitespace. */
252b5132
RH		 9395 ++op_string;
9396 if (is_space_char (*op_string))
24eab124 9397 ++op_string;
252b5132 9398
24eab124
AM		 9399 if (!is_digit_char (*op_string)
9400 && !is_identifier_char (*op_string)
9401 && *op_string != '('
9402 && *op_string != ABSOLUTE_PREFIX)
9403 {
9404 as_bad (_("bad memory operand `%s'"), op_string);
9405 return 0;
9406 }
47926f60 9407 /* Handle case of %es:*foo. */
24eab124
AM		 9408 if (*op_string == ABSOLUTE_PREFIX)
9409 {
9410 ++op_string;
9411 if (is_space_char (*op_string))
9412 ++op_string;
40fb9820 9413 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 9414 }
9415 goto do_memory_reference;
9416 }
43234a1e
L		 9417
9418 /* Handle vector operations. */
9419 if (*op_string == '{')
9420 {
9421 op_string = check_VecOperations (op_string, NULL);
9422 if (op_string == NULL)
9423 return 0;
9424 }
9425
24eab124
AM		 9426 if (*op_string)
9427 {
d0b47220 9428 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 9429 return 0;
9430 }
40fb9820
L		 9431 temp = r->reg_type;
9432 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9433 i.types[this_operand] = operand_type_or (i.types[this_operand],
9434 temp);
7d5e4556 9435 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 9436 i.op[this_operand].regs = r;
24eab124
AM		 9437 i.reg_operands++;
9438 }
af6bdddf
AM		 9439 else if (*op_string == REGISTER_PREFIX)
9440 {
9441 as_bad (_("bad register name `%s'"), op_string);
9442 return 0;
9443 }
24eab124 9444 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 9445 {
24eab124 9446 ++op_string;
40fb9820 9447 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 9448 {
d0b47220 9449 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 9450 return 0;
9451 }
9452 if (!i386_immediate (op_string))
9453 return 0;
9454 }
43234a1e
L		 9455 else if (RC_SAE_immediate (operand_string))
9456 {
9457 /* If it is a RC or SAE immediate, do nothing. */
9458 ;
9459 }
24eab124
AM		 9460 else if (is_digit_char (*op_string)
9461 || is_identifier_char (*op_string)
d02603dc 9462 || *op_string == '"'
e5cb08ac 9463 || *op_string == '(')
24eab124 9464 {
47926f60 9465 /* This is a memory reference of some sort. */
af6bdddf 9466 char *base_string;
252b5132 9467
47926f60 9468 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 9469 char *displacement_string_start;
9470 char *displacement_string_end;
43234a1e 9471 char *vop_start;
252b5132 9472
24eab124 9473 do_memory_reference:
8325cc63
JB		 9474 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9475 return 0;
24eab124 9476 if ((i.mem_operands == 1
40fb9820 9477 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 9478 || i.mem_operands == 2)
9479 {
9480 as_bad (_("too many memory references for `%s'"),
9481 current_templates->start->name);
9482 return 0;
9483 }
252b5132 9484
24eab124
AM		 9485 /* Check for base index form. We detect the base index form by
9486 looking for an ')' at the end of the operand, searching
9487 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9488 after the '('. */
af6bdddf 9489 base_string = op_string + strlen (op_string);
c3332e24 9490
43234a1e
L		 9491 /* Handle vector operations. */
9492 vop_start = strchr (op_string, '{');
9493 if (vop_start && vop_start < base_string)
9494 {
9495 if (check_VecOperations (vop_start, base_string) == NULL)
9496 return 0;
9497 base_string = vop_start;
9498 }
9499
af6bdddf
AM		 9500 --base_string;
9501 if (is_space_char (*base_string))
9502 --base_string;
252b5132 9503
47926f60 9504 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 9505 displacement_string_start = op_string;
9506 displacement_string_end = base_string + 1;
252b5132 9507
24eab124
AM		 9508 if (*base_string == ')')
9509 {
af6bdddf 9510 char *temp_string;
24eab124
AM		 9511 unsigned int parens_balanced = 1;
9512 /* We've already checked that the number of left & right ()'s are
47926f60 9513 equal, so this loop will not be infinite. */
24eab124
AM		 9514 do
9515 {
9516 base_string--;
9517 if (*base_string == ')')
9518 parens_balanced++;
9519 if (*base_string == '(')
9520 parens_balanced--;
9521 }
9522 while (parens_balanced);
c3332e24 9523
af6bdddf 9524 temp_string = base_string;
c3332e24 9525
24eab124 9526 /* Skip past '(' and whitespace. */
252b5132
RH		 9527 ++base_string;
9528 if (is_space_char (*base_string))
24eab124 9529 ++base_string;
252b5132 9530
af6bdddf 9531 if (*base_string == ','
4eed87de
AM		 9532 || ((i.base_reg = parse_register (base_string, &end_op))
9533 != NULL))
252b5132 9534 {
af6bdddf 9535 displacement_string_end = temp_string;
252b5132 9536
40fb9820 9537 i.types[this_operand].bitfield.baseindex = 1;
252b5132 9538
af6bdddf 9539 if (i.base_reg)
24eab124 9540 {
24eab124
AM		 9541 base_string = end_op;
9542 if (is_space_char (*base_string))
9543 ++base_string;
af6bdddf
AM		 9544 }
9545
9546 /* There may be an index reg or scale factor here. */
9547 if (*base_string == ',')
9548 {
9549 ++base_string;
9550 if (is_space_char (*base_string))
9551 ++base_string;
9552
4eed87de
AM		 9553 if ((i.index_reg = parse_register (base_string, &end_op))
9554 != NULL)
24eab124 9555 {
af6bdddf 9556 base_string = end_op;
24eab124
AM		 9557 if (is_space_char (*base_string))
9558 ++base_string;
af6bdddf
AM		 9559 if (*base_string == ',')
9560 {
9561 ++base_string;
9562 if (is_space_char (*base_string))
9563 ++base_string;
9564 }
e5cb08ac 9565 else if (*base_string != ')')
af6bdddf 9566 {
4eed87de
AM		 9567 as_bad (_("expecting `,' or `)' "
9568 "after index register in `%s'"),
af6bdddf
AM		 9569 operand_string);
9570 return 0;
9571 }
24eab124 9572 }
af6bdddf 9573 else if (*base_string == REGISTER_PREFIX)
24eab124 9574 {
f76bf5e0
L		 9575 end_op = strchr (base_string, ',');
9576 if (end_op)
9577 *end_op = '\0';
af6bdddf 9578 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9579 return 0;
9580 }
252b5132 9581
47926f60 9582 /* Check for scale factor. */
551c1ca1 9583 if (*base_string != ')')
af6bdddf 9584 {
551c1ca1
AM		 9585 char *end_scale = i386_scale (base_string);
9586
9587 if (!end_scale)
af6bdddf 9588 return 0;
24eab124 9589
551c1ca1 9590 base_string = end_scale;
af6bdddf
AM		 9591 if (is_space_char (*base_string))
9592 ++base_string;
9593 if (*base_string != ')')
9594 {
4eed87de
AM		 9595 as_bad (_("expecting `)' "
9596 "after scale factor in `%s'"),
af6bdddf
AM		 9597 operand_string);
9598 return 0;
9599 }
9600 }
9601 else if (!i.index_reg)
24eab124 9602 {
4eed87de
AM		 9603 as_bad (_("expecting index register or scale factor "
9604 "after `,'; got '%c'"),
af6bdddf 9605 *base_string);
24eab124
AM		 9606 return 0;
9607 }
9608 }
af6bdddf 9609 else if (*base_string != ')')
24eab124 9610 {
4eed87de
AM		 9611 as_bad (_("expecting `,' or `)' "
9612 "after base register in `%s'"),
af6bdddf 9613 operand_string);
24eab124
AM		 9614 return 0;
9615 }
c3332e24 9616 }
af6bdddf 9617 else if (*base_string == REGISTER_PREFIX)
c3332e24 9618 {
f76bf5e0
L		 9619 end_op = strchr (base_string, ',');
9620 if (end_op)
9621 *end_op = '\0';
af6bdddf 9622 as_bad (_("bad register name `%s'"), base_string);
24eab124 9623 return 0;
c3332e24 9624 }
24eab124
AM		 9625 }
9626
9627 /* If there's an expression beginning the operand, parse it,
9628 assuming displacement_string_start and
9629 displacement_string_end are meaningful. */
9630 if (displacement_string_start != displacement_string_end)
9631 {
9632 if (!i386_displacement (displacement_string_start,
9633 displacement_string_end))
9634 return 0;
9635 }
9636
9637 /* Special case for (%dx) while doing input/output op. */
9638 if (i.base_reg
0dfbf9d7
L		 9639 && operand_type_equal (&i.base_reg->reg_type,
9640 &reg16_inoutportreg)
24eab124
AM		 9641 && i.index_reg == 0
9642 && i.log2_scale_factor == 0
9643 && i.seg[i.mem_operands] == 0
40fb9820 9644 && !operand_type_check (i.types[this_operand], disp))
24eab124 9645 {
65da13b5 9646 i.types[this_operand] = inoutportreg;
24eab124
AM		 9647 return 1;
9648 }
9649
eecb386c
AM		 9650 if (i386_index_check (operand_string) == 0)
9651 return 0;
5c07affc 9652 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9653 if (i.mem_operands == 0)
9654 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9655 i.mem_operands++;
9656 }
9657 else
ce8a8b2f
AM		 9658 {
9659 /* It's not a memory operand; argh! */
24eab124
AM		 9660 as_bad (_("invalid char %s beginning operand %d `%s'"),
9661 output_invalid (*op_string),
9662 this_operand + 1,
9663 op_string);
9664 return 0;
9665 }
47926f60 9666 return 1; /* Normal return. */
252b5132
RH		 9667}
9668\f
fa94de6b
RM		 9669/* Calculate the maximum variable size (i.e., excluding fr_fix)
9670 that an rs_machine_dependent frag may reach. */
9671
9672unsigned int
9673i386_frag_max_var (fragS *frag)
9674{
9675 /* The only relaxable frags are for jumps.
9676 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9677 gas_assert (frag->fr_type == rs_machine_dependent);
9678 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9679}
9680
b084df0b
L		 9681#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9682static int
8dcea932 9683elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9684{
9685 /* STT_GNU_IFUNC symbol must go through PLT. */
9686 if ((symbol_get_bfdsym (fr_symbol)->flags
9687 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9688 return 0;
9689
9690 if (!S_IS_EXTERNAL (fr_symbol))
9691 /* Symbol may be weak or local. */
9692 return !S_IS_WEAK (fr_symbol);
9693
8dcea932
L		 9694 /* Global symbols with non-default visibility can't be preempted. */
9695 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9696 return 1;
9697
9698 if (fr_var != NO_RELOC)
9699 switch ((enum bfd_reloc_code_real) fr_var)
9700 {
9701 case BFD_RELOC_386_PLT32:
9702 case BFD_RELOC_X86_64_PLT32:
33eaf5de 9703 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 9704 return 0;
9705 default:
9706 abort ();
9707 }
9708
b084df0b
L		 9709 /* Global symbols with default visibility in a shared library may be
9710 preempted by another definition. */
8dcea932 9711 return !shared;
b084df0b
L		 9712}
9713#endif
9714
ee7fcc42
AM		 9715/* md_estimate_size_before_relax()
9716
9717 Called just before relax() for rs_machine_dependent frags. The x86
9718 assembler uses these frags to handle variable size jump
9719 instructions.
9720
9721 Any symbol that is now undefined will not become defined.
9722 Return the correct fr_subtype in the frag.
9723 Return the initial "guess for variable size of frag" to caller.
9724 The guess is actually the growth beyond the fixed part. Whatever
9725 we do to grow the fixed or variable part contributes to our
9726 returned value. */
9727
252b5132 9728int
7016a5d5 9729md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9730{
252b5132 9731 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9732 check for un-relaxable symbols. On an ELF system, we can't relax
9733 an externally visible symbol, because it may be overridden by a
9734 shared library. */
9735 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9736#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9737 || (IS_ELF
8dcea932
L		 9738 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9739 fragP->fr_var))
fbeb56a4
DK		 9740#endif
9741#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9742 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9743 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9744#endif
9745 )
252b5132 9746 {
b98ef147
AM		 9747 /* Symbol is undefined in this segment, or we need to keep a
9748 reloc so that weak symbols can be overridden. */
9749 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9750 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9751 unsigned char *opcode;
9752 int old_fr_fix;
f6af82bd 9753
ee7fcc42 9754 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9755 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9756 else if (size == 2)
f6af82bd 9757 reloc_type = BFD_RELOC_16_PCREL;
bd7ab16b
L		 9758#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9759 else if (need_plt32_p (fragP->fr_symbol))
9760 reloc_type = BFD_RELOC_X86_64_PLT32;
9761#endif
f6af82bd
AM		 9762 else
9763 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9764
ee7fcc42
AM		 9765 old_fr_fix = fragP->fr_fix;
9766 opcode = (unsigned char *) fragP->fr_opcode;
9767
fddf5b5b 9768 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9769 {
fddf5b5b
AM		 9770 case UNCOND_JUMP:
9771 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9772 opcode[0] = 0xe9;
252b5132 9773 fragP->fr_fix += size;
062cd5e7
AS		 9774 fix_new (fragP, old_fr_fix, size,
9775 fragP->fr_symbol,
9776 fragP->fr_offset, 1,
9777 reloc_type);
252b5132
RH		 9778 break;
9779
fddf5b5b 9780 case COND_JUMP86:
412167cb
AM		 9781 if (size == 2
9782 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9783 {
9784 /* Negate the condition, and branch past an
9785 unconditional jump. */
9786 opcode[0] ^= 1;
9787 opcode[1] = 3;
9788 /* Insert an unconditional jump. */
9789 opcode[2] = 0xe9;
9790 /* We added two extra opcode bytes, and have a two byte
9791 offset. */
9792 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9793 fix_new (fragP, old_fr_fix + 2, 2,
9794 fragP->fr_symbol,
9795 fragP->fr_offset, 1,
9796 reloc_type);
fddf5b5b
AM		 9797 break;
9798 }
9799 /* Fall through. */
9800
9801 case COND_JUMP:
412167cb
AM		 9802 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9803 {
3e02c1cc
AM		 9804 fixS *fixP;
9805
412167cb 9806 fragP->fr_fix += 1;
3e02c1cc
AM		 9807 fixP = fix_new (fragP, old_fr_fix, 1,
9808 fragP->fr_symbol,
9809 fragP->fr_offset, 1,
9810 BFD_RELOC_8_PCREL);
9811 fixP->fx_signed = 1;
412167cb
AM		 9812 break;
9813 }
93c2a809 9814
24eab124 9815 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9816 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9817 opcode[1] = opcode[0] + 0x10;
f6af82bd 9818 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9819 /* We've added an opcode byte. */
9820 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9821 fix_new (fragP, old_fr_fix + 1, size,
9822 fragP->fr_symbol,
9823 fragP->fr_offset, 1,
9824 reloc_type);
252b5132 9825 break;
fddf5b5b
AM		 9826
9827 default:
9828 BAD_CASE (fragP->fr_subtype);
9829 break;
252b5132
RH		 9830 }
9831 frag_wane (fragP);
ee7fcc42 9832 return fragP->fr_fix - old_fr_fix;
252b5132 9833 }
93c2a809 9834
93c2a809
AM		 9835 /* Guess size depending on current relax state. Initially the relax
9836 state will correspond to a short jump and we return 1, because
9837 the variable part of the frag (the branch offset) is one byte
9838 long. However, we can relax a section more than once and in that
9839 case we must either set fr_subtype back to the unrelaxed state,
9840 or return the value for the appropriate branch. */
9841 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9842}
9843
47926f60
KH		 9844/* Called after relax() is finished.
9845
9846 In: Address of frag.
9847 fr_type == rs_machine_dependent.
9848 fr_subtype is what the address relaxed to.
9849
9850 Out: Any fixSs and constants are set up.
9851 Caller will turn frag into a ".space 0". */
9852
252b5132 9853void
7016a5d5
TG		 9854md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9855 fragS *fragP)
252b5132 9856{
29b0f896 9857 unsigned char *opcode;
252b5132 9858 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9859 offsetT target_address;
9860 offsetT opcode_address;
252b5132 9861 unsigned int extension = 0;
847f7ad4 9862 offsetT displacement_from_opcode_start;
252b5132
RH		 9863
9864 opcode = (unsigned char *) fragP->fr_opcode;
9865
47926f60 9866 /* Address we want to reach in file space. */
252b5132 9867 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9868
47926f60 9869 /* Address opcode resides at in file space. */
252b5132
RH		 9870 opcode_address = fragP->fr_address + fragP->fr_fix;
9871
47926f60 9872 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9873 displacement_from_opcode_start = target_address - opcode_address;
9874
fddf5b5b 9875 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9876 {
47926f60
KH		 9877 /* Don't have to change opcode. */
9878 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9879 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9880 }
9881 else
9882 {
9883 if (no_cond_jump_promotion
9884 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9885 as_warn_where (fragP->fr_file, fragP->fr_line,
9886 _("long jump required"));
252b5132 9887
fddf5b5b
AM		 9888 switch (fragP->fr_subtype)
9889 {
9890 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9891 extension = 4; /* 1 opcode + 4 displacement */
9892 opcode[0] = 0xe9;
9893 where_to_put_displacement = &opcode[1];
9894 break;
252b5132 9895
fddf5b5b
AM		 9896 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9897 extension = 2; /* 1 opcode + 2 displacement */
9898 opcode[0] = 0xe9;
9899 where_to_put_displacement = &opcode[1];
9900 break;
252b5132 9901
fddf5b5b
AM		 9902 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9903 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9904 extension = 5; /* 2 opcode + 4 displacement */
9905 opcode[1] = opcode[0] + 0x10;
9906 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9907 where_to_put_displacement = &opcode[2];
9908 break;
252b5132 9909
fddf5b5b
AM		 9910 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9911 extension = 3; /* 2 opcode + 2 displacement */
9912 opcode[1] = opcode[0] + 0x10;
9913 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9914 where_to_put_displacement = &opcode[2];
9915 break;
252b5132 9916
fddf5b5b
AM		 9917 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9918 extension = 4;
9919 opcode[0] ^= 1;
9920 opcode[1] = 3;
9921 opcode[2] = 0xe9;
9922 where_to_put_displacement = &opcode[3];
9923 break;
9924
9925 default:
9926 BAD_CASE (fragP->fr_subtype);
9927 break;
9928 }
252b5132 9929 }
fddf5b5b 9930
7b81dfbb
AJ		 9931 /* If size if less then four we are sure that the operand fits,
9932 but if it's 4, then it could be that the displacement is larger
9933 then -/+ 2GB. */
9934 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9935 && object_64bit
9936 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9937 + ((addressT) 1 << 31))
9938 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9939 {
9940 as_bad_where (fragP->fr_file, fragP->fr_line,
9941 _("jump target out of range"));
9942 /* Make us emit 0. */
9943 displacement_from_opcode_start = extension;
9944 }
47926f60 9945 /* Now put displacement after opcode. */
252b5132
RH		 9946 md_number_to_chars ((char *) where_to_put_displacement,
9947 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9948 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9949 fragP->fr_fix += extension;
9950}
9951\f
7016a5d5 9952/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9953 by our caller that we have all the info we need to fix it up.
9954
7016a5d5
TG		 9955 Parameter valP is the pointer to the value of the bits.
9956
252b5132
RH		 9957 On the 386, immediates, displacements, and data pointers are all in
9958 the same (little-endian) format, so we don't need to care about which
9959 we are handling. */
9960
94f592af 9961void
7016a5d5 9962md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9963{
94f592af 9964 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9965 valueT value = *valP;
252b5132 9966
f86103b7 9967#if !defined (TE_Mach)
93382f6d
AM		 9968 if (fixP->fx_pcrel)
9969 {
9970 switch (fixP->fx_r_type)
9971 {
5865bb77
ILT		 9972 default:
9973 break;
9974
d6ab8113
JB		 9975 case BFD_RELOC_64:
9976 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9977 break;
93382f6d 9978 case BFD_RELOC_32:
ae8887b5 9979 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9980 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9981 break;
9982 case BFD_RELOC_16:
9983 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9984 break;
9985 case BFD_RELOC_8:
9986 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9987 break;
9988 }
9989 }
252b5132 9990
a161fe53 9991 if (fixP->fx_addsy != NULL
31312f95 9992 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9993 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9994 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9995 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9996 && !use_rela_relocations)
252b5132 9997 {
31312f95
AM		 9998 /* This is a hack. There should be a better way to handle this.
9999 This covers for the fact that bfd_install_relocation will
10000 subtract the current location (for partial_inplace, PC relative
10001 relocations); see more below. */
252b5132 10002#ifndef OBJ_AOUT
718ddfc0 10003 if (IS_ELF
252b5132
RH		 10004#ifdef TE_PE
10005 || OUTPUT_FLAVOR == bfd_target_coff_flavour
10006#endif
10007 )
10008 value += fixP->fx_where + fixP->fx_frag->fr_address;
10009#endif
10010#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 10011 if (IS_ELF)
252b5132 10012 {
6539b54b 10013 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 10014
6539b54b 10015 if ((sym_seg == seg
2f66722d 10016 || (symbol_section_p (fixP->fx_addsy)
6539b54b 10017 && sym_seg != absolute_section))
af65af87 10018 && !generic_force_reloc (fixP))
2f66722d
AM		 10019 {
10020 /* Yes, we add the values in twice. This is because
6539b54b
AM		 10021 bfd_install_relocation subtracts them out again. I think
10022 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 10023 it. FIXME. */
10024 value += fixP->fx_where + fixP->fx_frag->fr_address;
10025 }
252b5132
RH		 10026 }
10027#endif
10028#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 10029 /* For some reason, the PE format does not store a
10030 section address offset for a PC relative symbol. */
10031 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 10032 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 10033 value += md_pcrel_from (fixP);
10034#endif
10035 }
fbeb56a4 10036#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 10037 if (fixP->fx_addsy != NULL
10038 && S_IS_WEAK (fixP->fx_addsy)
10039 /* PR 16858: Do not modify weak function references. */
10040 && ! fixP->fx_pcrel)
fbeb56a4 10041 {
296a8689
NC		 10042#if !defined (TE_PEP)
10043 /* For x86 PE weak function symbols are neither PC-relative
10044 nor do they set S_IS_FUNCTION. So the only reliable way
10045 to detect them is to check the flags of their containing
10046 section. */
10047 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
10048 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10049 ;
10050 else
10051#endif
fbeb56a4
DK		 10052 value -= S_GET_VALUE (fixP->fx_addsy);
10053 }
10054#endif
252b5132
RH		 10055
10056 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 10057 and we must not disappoint it. */
252b5132 10058#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 10059 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 10060 switch (fixP->fx_r_type)
10061 {
10062 case BFD_RELOC_386_PLT32:
3e73aa7c 10063 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 10064 /* Make the jump instruction point to the address of the operand. At
10065 runtime we merely add the offset to the actual PLT entry. */
10066 value = -4;
10067 break;
31312f95 10068
13ae64f3
JJ		 10069 case BFD_RELOC_386_TLS_GD:
10070 case BFD_RELOC_386_TLS_LDM:
13ae64f3 10071 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10072 case BFD_RELOC_386_TLS_IE:
10073 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 10074 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 10075 case BFD_RELOC_X86_64_TLSGD:
10076 case BFD_RELOC_X86_64_TLSLD:
10077 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 10078 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 10079 value = 0; /* Fully resolved at runtime. No addend. */
10080 /* Fallthrough */
10081 case BFD_RELOC_386_TLS_LE:
10082 case BFD_RELOC_386_TLS_LDO_32:
10083 case BFD_RELOC_386_TLS_LE_32:
10084 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10085 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 10086 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 10087 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 10088 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10089 break;
10090
67a4f2b7
AO		 10091 case BFD_RELOC_386_TLS_DESC_CALL:
10092 case BFD_RELOC_X86_64_TLSDESC_CALL:
10093 value = 0; /* Fully resolved at runtime. No addend. */
10094 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10095 fixP->fx_done = 0;
10096 return;
10097
47926f60
KH		 10098 case BFD_RELOC_VTABLE_INHERIT:
10099 case BFD_RELOC_VTABLE_ENTRY:
10100 fixP->fx_done = 0;
94f592af 10101 return;
47926f60
KH		 10102
10103 default:
10104 break;
10105 }
10106#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 10107 *valP = value;
f86103b7 10108#endif /* !defined (TE_Mach) */
3e73aa7c 10109
3e73aa7c 10110 /* Are we finished with this relocation now? */
c6682705 10111 if (fixP->fx_addsy == NULL)
3e73aa7c 10112 fixP->fx_done = 1;
fbeb56a4
DK		 10113#if defined (OBJ_COFF) && defined (TE_PE)
10114 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10115 {
10116 fixP->fx_done = 0;
10117 /* Remember value for tc_gen_reloc. */
10118 fixP->fx_addnumber = value;
10119 /* Clear out the frag for now. */
10120 value = 0;
10121 }
10122#endif
3e73aa7c
JH		 10123 else if (use_rela_relocations)
10124 {
10125 fixP->fx_no_overflow = 1;
062cd5e7
AS		 10126 /* Remember value for tc_gen_reloc. */
10127 fixP->fx_addnumber = value;
3e73aa7c
JH		 10128 value = 0;
10129 }
f86103b7 10130
94f592af 10131 md_number_to_chars (p, value, fixP->fx_size);
252b5132 10132}
252b5132 10133\f
6d4af3c2 10134const char *
499ac353 10135md_atof (int type, char *litP, int *sizeP)
252b5132 10136{
499ac353
NC		 10137 /* This outputs the LITTLENUMs in REVERSE order;
10138 in accord with the bigendian 386. */
10139 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 10140}
10141\f
2d545b82 10142static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 10143
252b5132 10144static char *
e3bb37b5 10145output_invalid (int c)
252b5132 10146{
3882b010 10147 if (ISPRINT (c))
f9f21a03
L		 10148 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10149 "'%c'", c);
252b5132 10150 else
f9f21a03 10151 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 10152 "(0x%x)", (unsigned char) c);
252b5132
RH		 10153 return output_invalid_buf;
10154}
10155
af6bdddf 10156/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 10157
10158static const reg_entry *
4d1bb795 10159parse_real_register (char *reg_string, char **end_op)
252b5132 10160{
af6bdddf
AM		 10161 char *s = reg_string;
10162 char *p;
252b5132
RH		 10163 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10164 const reg_entry *r;
10165
10166 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10167 if (*s == REGISTER_PREFIX)
10168 ++s;
10169
10170 if (is_space_char (*s))
10171 ++s;
10172
10173 p = reg_name_given;
af6bdddf 10174 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 10175 {
10176 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 10177 return (const reg_entry *) NULL;
10178 s++;
252b5132
RH		 10179 }
10180
6588847e
DN		 10181 /* For naked regs, make sure that we are not dealing with an identifier.
10182 This prevents confusing an identifier like `eax_var' with register
10183 `eax'. */
10184 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10185 return (const reg_entry *) NULL;
10186
af6bdddf 10187 *end_op = s;
252b5132
RH		 10188
10189 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10190
5f47d35b 10191 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 10192 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 10193 {
0e0eea78
JB		 10194 if (!cpu_arch_flags.bitfield.cpu8087
10195 && !cpu_arch_flags.bitfield.cpu287
10196 && !cpu_arch_flags.bitfield.cpu387)
10197 return (const reg_entry *) NULL;
10198
5f47d35b
AM		 10199 if (is_space_char (*s))
10200 ++s;
10201 if (*s == '(')
10202 {
af6bdddf 10203 ++s;
5f47d35b
AM		 10204 if (is_space_char (*s))
10205 ++s;
10206 if (*s >= '0' && *s <= '7')
10207 {
db557034 10208 int fpr = *s - '0';
af6bdddf 10209 ++s;
5f47d35b
AM		 10210 if (is_space_char (*s))
10211 ++s;
10212 if (*s == ')')
10213 {
10214 *end_op = s + 1;
1e9cc1c2 10215 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 10216 know (r);
10217 return r + fpr;
5f47d35b 10218 }
5f47d35b 10219 }
47926f60 10220 /* We have "%st(" then garbage. */
5f47d35b
AM		 10221 return (const reg_entry *) NULL;
10222 }
10223 }
10224
a60de03c
JB		 10225 if (r == NULL || allow_pseudo_reg)
10226 return r;
10227
0dfbf9d7 10228 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 10229 return (const reg_entry *) NULL;
10230
dc821c5f 10231 if ((r->reg_type.bitfield.dword
192dc9c6
JB		 10232 || r->reg_type.bitfield.sreg3
10233 || r->reg_type.bitfield.control
10234 || r->reg_type.bitfield.debug
10235 || r->reg_type.bitfield.test)
10236 && !cpu_arch_flags.bitfield.cpui386)
10237 return (const reg_entry *) NULL;
10238
6e041cf4 10239 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
192dc9c6
JB		 10240 return (const reg_entry *) NULL;
10241
6e041cf4
JB		 10242 if (!cpu_arch_flags.bitfield.cpuavx512f)
10243 {
10244 if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
10245 return (const reg_entry *) NULL;
40f12533 10246
6e041cf4
JB		 10247 if (!cpu_arch_flags.bitfield.cpuavx)
10248 {
10249 if (r->reg_type.bitfield.ymmword)
10250 return (const reg_entry *) NULL;
1848e567 10251
6e041cf4
JB		 10252 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
10253 return (const reg_entry *) NULL;
10254 }
10255 }
43234a1e 10256
1adf7f56
JB		 10257 if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
10258 return (const reg_entry *) NULL;
10259
db51cc60 10260 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 10261 if (!allow_index_reg
db51cc60
L		 10262 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10263 return (const reg_entry *) NULL;
10264
1d3f8286
JB		 10265 /* Upper 16 vector registers are only available with VREX in 64bit
10266 mode, and require EVEX encoding. */
10267 if (r->reg_flags & RegVRex)
43234a1e
L		 10268 {
10269 if (!cpu_arch_flags.bitfield.cpuvrex
10270 || flag_code != CODE_64BIT)
10271 return (const reg_entry *) NULL;
1d3f8286
JB		 10272
10273 i.vec_encoding = vex_encoding_evex;
43234a1e
L		 10274 }
10275
4787f4a5
JB		 10276 if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
10277 && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control)
1ae00879 10278 && flag_code != CODE_64BIT)
20f0a1fc 10279 return (const reg_entry *) NULL;
1ae00879 10280
b7240065
JB		 10281 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10282 return (const reg_entry *) NULL;
10283
252b5132
RH		 10284 return r;
10285}
4d1bb795
JB		 10286
10287/* REG_STRING starts *before* REGISTER_PREFIX. */
10288
10289static const reg_entry *
10290parse_register (char *reg_string, char **end_op)
10291{
10292 const reg_entry *r;
10293
10294 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10295 r = parse_real_register (reg_string, end_op);
10296 else
10297 r = NULL;
10298 if (!r)
10299 {
10300 char *save = input_line_pointer;
10301 char c;
10302 symbolS *symbolP;
10303
10304 input_line_pointer = reg_string;
d02603dc 10305 c = get_symbol_name (&reg_string);
4d1bb795
JB		 10306 symbolP = symbol_find (reg_string);
10307 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10308 {
10309 const expressionS *e = symbol_get_value_expression (symbolP);
10310
0398aac5 10311 know (e->X_op == O_register);
4eed87de 10312 know (e->X_add_number >= 0
c3fe08fa 10313 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 10314 r = i386_regtab + e->X_add_number;
d3bb6b49 10315 if ((r->reg_flags & RegVRex))
86fa6981 10316 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 10317 *end_op = input_line_pointer;
10318 }
10319 *input_line_pointer = c;
10320 input_line_pointer = save;
10321 }
10322 return r;
10323}
10324
10325int
10326i386_parse_name (char *name, expressionS *e, char *nextcharP)
10327{
10328 const reg_entry *r;
10329 char *end = input_line_pointer;
10330
10331 *end = *nextcharP;
10332 r = parse_register (name, &input_line_pointer);
10333 if (r && end <= input_line_pointer)
10334 {
10335 *nextcharP = *input_line_pointer;
10336 *input_line_pointer = 0;
10337 e->X_op = O_register;
10338 e->X_add_number = r - i386_regtab;
10339 return 1;
10340 }
10341 input_line_pointer = end;
10342 *end = 0;
ee86248c 10343 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 10344}
10345
10346void
10347md_operand (expressionS *e)
10348{
ee86248c
JB		 10349 char *end;
10350 const reg_entry *r;
4d1bb795 10351
ee86248c
JB		 10352 switch (*input_line_pointer)
10353 {
10354 case REGISTER_PREFIX:
10355 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 10356 if (r)
10357 {
10358 e->X_op = O_register;
10359 e->X_add_number = r - i386_regtab;
10360 input_line_pointer = end;
10361 }
ee86248c
JB		 10362 break;
10363
10364 case '[':
9c2799c2 10365 gas_assert (intel_syntax);
ee86248c
JB		 10366 end = input_line_pointer++;
10367 expression (e);
10368 if (*input_line_pointer == ']')
10369 {
10370 ++input_line_pointer;
10371 e->X_op_symbol = make_expr_symbol (e);
10372 e->X_add_symbol = NULL;
10373 e->X_add_number = 0;
10374 e->X_op = O_index;
10375 }
10376 else
10377 {
10378 e->X_op = O_absent;
10379 input_line_pointer = end;
10380 }
10381 break;
4d1bb795
JB		 10382 }
10383}
10384
252b5132 10385\f
4cc782b5 10386#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
b6f8c7c4 10387const char *md_shortopts = "kVQ:sqnO::";
252b5132 10388#else
b6f8c7c4 10389const char *md_shortopts = "qnO::";
252b5132 10390#endif
6e0b89ee 10391
3e73aa7c 10392#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 10393#define OPTION_64 (OPTION_MD_BASE + 1)
10394#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 10395#define OPTION_MARCH (OPTION_MD_BASE + 3)
10396#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 10397#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10398#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10399#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10400#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
bd5dea88 10401#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
c0f3af97 10402#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 10403#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 10404#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10405#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10406#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 10407#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 10408#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10409#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 10410#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 10411#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 10412#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 10413#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 10414#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10415#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 10416#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
b3b91714 10417
99ad8390
NC		 10418struct option md_longopts[] =
10419{
3e73aa7c 10420 {"32", no_argument, NULL, OPTION_32},
321098a5 10421#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10422 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 10423 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 10424#endif
10425#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10426 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 10427 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 10428#endif
b3b91714 10429 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 10430 {"march", required_argument, NULL, OPTION_MARCH},
10431 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 10432 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10433 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10434 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10435 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
c0f3af97 10436 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 10437 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 10438 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 10439 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 10440 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 10441 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10442 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 10443# if defined (TE_PE) || defined (TE_PEP)
10444 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10445#endif
d1982f93 10446 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 10447 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 10448 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 10449 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 10450 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10451 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 10452 {NULL, no_argument, NULL, 0}
10453};
10454size_t md_longopts_size = sizeof (md_longopts);
10455
10456int
17b9d67d 10457md_parse_option (int c, const char *arg)
252b5132 10458{
91d6fa6a 10459 unsigned int j;
293f5f65 10460 char *arch, *next, *saved;
9103f4f4 10461
252b5132
RH		 10462 switch (c)
10463 {
12b55ccc
L		 10464 case 'n':
10465 optimize_align_code = 0;
10466 break;
10467
a38cf1db
AM		 10468 case 'q':
10469 quiet_warnings = 1;
252b5132
RH		 10470 break;
10471
10472#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 10473 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10474 should be emitted or not. FIXME: Not implemented. */
10475 case 'Q':
252b5132
RH		 10476 break;
10477
10478 /* -V: SVR4 argument to print version ID. */
10479 case 'V':
10480 print_version_id ();
10481 break;
10482
a38cf1db
AM		 10483 /* -k: Ignore for FreeBSD compatibility. */
10484 case 'k':
252b5132 10485 break;
4cc782b5
ILT		 10486
10487 case 's':
10488 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 10489 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 10490 break;
8dcea932
L		 10491
10492 case OPTION_MSHARED:
10493 shared = 1;
10494 break;
99ad8390 10495#endif
321098a5 10496#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10497 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 10498 case OPTION_64:
10499 {
10500 const char **list, **l;
10501
3e73aa7c
JH		 10502 list = bfd_target_list ();
10503 for (l = list; *l != NULL; l++)
8620418b 10504 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 10505 || strcmp (*l, "coff-x86-64") == 0
10506 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 10507 || strcmp (*l, "pei-x86-64") == 0
10508 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 10509 {
10510 default_arch = "x86_64";
10511 break;
10512 }
3e73aa7c 10513 if (*l == NULL)
2b5d6a91 10514 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 10515 free (list);
10516 }
10517 break;
10518#endif
252b5132 10519
351f65ca 10520#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10521 case OPTION_X32:
351f65ca
L		 10522 if (IS_ELF)
10523 {
10524 const char **list, **l;
10525
10526 list = bfd_target_list ();
10527 for (l = list; *l != NULL; l++)
10528 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10529 {
10530 default_arch = "x86_64:32";
10531 break;
10532 }
10533 if (*l == NULL)
2b5d6a91 10534 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 10535 free (list);
10536 }
10537 else
10538 as_fatal (_("32bit x86_64 is only supported for ELF"));
10539 break;
10540#endif
10541
6e0b89ee
AM		 10542 case OPTION_32:
10543 default_arch = "i386";
10544 break;
10545
b3b91714
AM		 10546 case OPTION_DIVIDE:
10547#ifdef SVR4_COMMENT_CHARS
10548 {
10549 char *n, *t;
10550 const char *s;
10551
add39d23 10552 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 10553 t = n;
10554 for (s = i386_comment_chars; *s != '\0'; s++)
10555 if (*s != '/')
10556 *t++ = *s;
10557 *t = '\0';
10558 i386_comment_chars = n;
10559 }
10560#endif
10561 break;
10562
9103f4f4 10563 case OPTION_MARCH:
293f5f65
L		 10564 saved = xstrdup (arg);
10565 arch = saved;
10566 /* Allow -march=+nosse. */
10567 if (*arch == '+')
10568 arch++;
6305a203 10569 do
9103f4f4 10570 {
6305a203 10571 if (*arch == '.')
2b5d6a91 10572 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10573 next = strchr (arch, '+');
10574 if (next)
10575 *next++ = '\0';
91d6fa6a 10576 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10577 {
91d6fa6a 10578 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10579 {
6305a203 10580 /* Processor. */
1ded5609
JB		 10581 if (! cpu_arch[j].flags.bitfield.cpui386)
10582 continue;
10583
91d6fa6a 10584 cpu_arch_name = cpu_arch[j].name;
6305a203 10585 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10586 cpu_arch_flags = cpu_arch[j].flags;
10587 cpu_arch_isa = cpu_arch[j].type;
10588 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10589 if (!cpu_arch_tune_set)
10590 {
10591 cpu_arch_tune = cpu_arch_isa;
10592 cpu_arch_tune_flags = cpu_arch_isa_flags;
10593 }
10594 break;
10595 }
91d6fa6a
NC		 10596 else if (*cpu_arch [j].name == '.'
10597 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 10598 {
33eaf5de 10599 /* ISA extension. */
6305a203 10600 i386_cpu_flags flags;
309d3373 10601
293f5f65
L		 10602 flags = cpu_flags_or (cpu_arch_flags,
10603 cpu_arch[j].flags);
81486035 10604
5b64d091 10605 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10606 {
10607 if (cpu_sub_arch_name)
10608 {
10609 char *name = cpu_sub_arch_name;
10610 cpu_sub_arch_name = concat (name,
91d6fa6a 10611 cpu_arch[j].name,
1bf57e9f 10612 (const char *) NULL);
6305a203
L		 10613 free (name);
10614 }
10615 else
91d6fa6a 10616 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10617 cpu_arch_flags = flags;
a586129e 10618 cpu_arch_isa_flags = flags;
6305a203 10619 }
0089dace
L		 10620 else
10621 cpu_arch_isa_flags
10622 = cpu_flags_or (cpu_arch_isa_flags,
10623 cpu_arch[j].flags);
6305a203 10624 break;
ccc9c027 10625 }
9103f4f4 10626 }
6305a203 10627
293f5f65
L		 10628 if (j >= ARRAY_SIZE (cpu_arch))
10629 {
33eaf5de 10630 /* Disable an ISA extension. */
293f5f65
L		 10631 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10632 if (strcmp (arch, cpu_noarch [j].name) == 0)
10633 {
10634 i386_cpu_flags flags;
10635
10636 flags = cpu_flags_and_not (cpu_arch_flags,
10637 cpu_noarch[j].flags);
10638 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10639 {
10640 if (cpu_sub_arch_name)
10641 {
10642 char *name = cpu_sub_arch_name;
10643 cpu_sub_arch_name = concat (arch,
10644 (const char *) NULL);
10645 free (name);
10646 }
10647 else
10648 cpu_sub_arch_name = xstrdup (arch);
10649 cpu_arch_flags = flags;
10650 cpu_arch_isa_flags = flags;
10651 }
10652 break;
10653 }
10654
10655 if (j >= ARRAY_SIZE (cpu_noarch))
10656 j = ARRAY_SIZE (cpu_arch);
10657 }
10658
91d6fa6a 10659 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10660 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10661
10662 arch = next;
9103f4f4 10663 }
293f5f65
L		 10664 while (next != NULL);
10665 free (saved);
9103f4f4
L		 10666 break;
10667
10668 case OPTION_MTUNE:
10669 if (*arg == '.')
2b5d6a91 10670 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10671 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10672 {
91d6fa6a 10673 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10674 {
ccc9c027 10675 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10676 cpu_arch_tune = cpu_arch [j].type;
10677 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10678 break;
10679 }
10680 }
91d6fa6a 10681 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10682 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10683 break;
10684
1efbbeb4
L		 10685 case OPTION_MMNEMONIC:
10686 if (strcasecmp (arg, "att") == 0)
10687 intel_mnemonic = 0;
10688 else if (strcasecmp (arg, "intel") == 0)
10689 intel_mnemonic = 1;
10690 else
2b5d6a91 10691 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10692 break;
10693
10694 case OPTION_MSYNTAX:
10695 if (strcasecmp (arg, "att") == 0)
10696 intel_syntax = 0;
10697 else if (strcasecmp (arg, "intel") == 0)
10698 intel_syntax = 1;
10699 else
2b5d6a91 10700 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10701 break;
10702
10703 case OPTION_MINDEX_REG:
10704 allow_index_reg = 1;
10705 break;
10706
10707 case OPTION_MNAKED_REG:
10708 allow_naked_reg = 1;
10709 break;
10710
c0f3af97
L		 10711 case OPTION_MSSE2AVX:
10712 sse2avx = 1;
10713 break;
10714
daf50ae7
L		 10715 case OPTION_MSSE_CHECK:
10716 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10717 sse_check = check_error;
daf50ae7 10718 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10719 sse_check = check_warning;
daf50ae7 10720 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10721 sse_check = check_none;
daf50ae7 10722 else
2b5d6a91 10723 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10724 break;
10725
7bab8ab5
JB		 10726 case OPTION_MOPERAND_CHECK:
10727 if (strcasecmp (arg, "error") == 0)
10728 operand_check = check_error;
10729 else if (strcasecmp (arg, "warning") == 0)
10730 operand_check = check_warning;
10731 else if (strcasecmp (arg, "none") == 0)
10732 operand_check = check_none;
10733 else
10734 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10735 break;
10736
539f890d
L		 10737 case OPTION_MAVXSCALAR:
10738 if (strcasecmp (arg, "128") == 0)
10739 avxscalar = vex128;
10740 else if (strcasecmp (arg, "256") == 0)
10741 avxscalar = vex256;
10742 else
2b5d6a91 10743 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10744 break;
10745
7e8b059b
L		 10746 case OPTION_MADD_BND_PREFIX:
10747 add_bnd_prefix = 1;
10748 break;
10749
43234a1e
L		 10750 case OPTION_MEVEXLIG:
10751 if (strcmp (arg, "128") == 0)
10752 evexlig = evexl128;
10753 else if (strcmp (arg, "256") == 0)
10754 evexlig = evexl256;
10755 else if (strcmp (arg, "512") == 0)
10756 evexlig = evexl512;
10757 else
10758 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10759 break;
10760
d3d3c6db
IT		 10761 case OPTION_MEVEXRCIG:
10762 if (strcmp (arg, "rne") == 0)
10763 evexrcig = rne;
10764 else if (strcmp (arg, "rd") == 0)
10765 evexrcig = rd;
10766 else if (strcmp (arg, "ru") == 0)
10767 evexrcig = ru;
10768 else if (strcmp (arg, "rz") == 0)
10769 evexrcig = rz;
10770 else
10771 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10772 break;
10773
43234a1e
L		 10774 case OPTION_MEVEXWIG:
10775 if (strcmp (arg, "0") == 0)
10776 evexwig = evexw0;
10777 else if (strcmp (arg, "1") == 0)
10778 evexwig = evexw1;
10779 else
10780 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10781 break;
10782
167ad85b
TG		 10783# if defined (TE_PE) || defined (TE_PEP)
10784 case OPTION_MBIG_OBJ:
10785 use_big_obj = 1;
10786 break;
10787#endif
10788
d1982f93 10789 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10790 if (strcasecmp (arg, "yes") == 0)
10791 omit_lock_prefix = 1;
10792 else if (strcasecmp (arg, "no") == 0)
10793 omit_lock_prefix = 0;
10794 else
10795 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10796 break;
10797
e4e00185
AS		 10798 case OPTION_MFENCE_AS_LOCK_ADD:
10799 if (strcasecmp (arg, "yes") == 0)
10800 avoid_fence = 1;
10801 else if (strcasecmp (arg, "no") == 0)
10802 avoid_fence = 0;
10803 else
10804 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10805 break;
10806
0cb4071e
L		 10807 case OPTION_MRELAX_RELOCATIONS:
10808 if (strcasecmp (arg, "yes") == 0)
10809 generate_relax_relocations = 1;
10810 else if (strcasecmp (arg, "no") == 0)
10811 generate_relax_relocations = 0;
10812 else
10813 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10814 break;
10815
5db04b09 10816 case OPTION_MAMD64:
e89c5eaa 10817 intel64 = 0;
5db04b09
L		 10818 break;
10819
10820 case OPTION_MINTEL64:
e89c5eaa 10821 intel64 = 1;
5db04b09
L		 10822 break;
10823
b6f8c7c4
L		 10824 case 'O':
10825 if (arg == NULL)
10826 {
10827 optimize = 1;
10828 /* Turn off -Os. */
10829 optimize_for_space = 0;
10830 }
10831 else if (*arg == 's')
10832 {
10833 optimize_for_space = 1;
10834 /* Turn on all encoding optimizations. */
10835 optimize = -1;
10836 }
10837 else
10838 {
10839 optimize = atoi (arg);
10840 /* Turn off -Os. */
10841 optimize_for_space = 0;
10842 }
10843 break;
10844
252b5132
RH		 10845 default:
10846 return 0;
10847 }
10848 return 1;
10849}
10850
8a2c8fef
L		 10851#define MESSAGE_TEMPLATE \
10852" "
10853
293f5f65
L		 10854static char *
10855output_message (FILE *stream, char *p, char *message, char *start,
10856 int *left_p, const char *name, int len)
10857{
10858 int size = sizeof (MESSAGE_TEMPLATE);
10859 int left = *left_p;
10860
10861 /* Reserve 2 spaces for ", " or ",\0" */
10862 left -= len + 2;
10863
10864 /* Check if there is any room. */
10865 if (left >= 0)
10866 {
10867 if (p != start)
10868 {
10869 *p++ = ',';
10870 *p++ = ' ';
10871 }
10872 p = mempcpy (p, name, len);
10873 }
10874 else
10875 {
10876 /* Output the current message now and start a new one. */
10877 *p++ = ',';
10878 *p = '\0';
10879 fprintf (stream, "%s\n", message);
10880 p = start;
10881 left = size - (start - message) - len - 2;
10882
10883 gas_assert (left >= 0);
10884
10885 p = mempcpy (p, name, len);
10886 }
10887
10888 *left_p = left;
10889 return p;
10890}
10891
8a2c8fef 10892static void
1ded5609 10893show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10894{
10895 static char message[] = MESSAGE_TEMPLATE;
10896 char *start = message + 27;
10897 char *p;
10898 int size = sizeof (MESSAGE_TEMPLATE);
10899 int left;
10900 const char *name;
10901 int len;
10902 unsigned int j;
10903
10904 p = start;
10905 left = size - (start - message);
10906 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10907 {
10908 /* Should it be skipped? */
10909 if (cpu_arch [j].skip)
10910 continue;
10911
10912 name = cpu_arch [j].name;
10913 len = cpu_arch [j].len;
10914 if (*name == '.')
10915 {
10916 /* It is an extension. Skip if we aren't asked to show it. */
10917 if (ext)
10918 {
10919 name++;
10920 len--;
10921 }
10922 else
10923 continue;
10924 }
10925 else if (ext)
10926 {
10927 /* It is an processor. Skip if we show only extension. */
10928 continue;
10929 }
1ded5609
JB		 10930 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10931 {
10932 /* It is an impossible processor - skip. */
10933 continue;
10934 }
8a2c8fef 10935
293f5f65 10936 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10937 }
10938
293f5f65
L		 10939 /* Display disabled extensions. */
10940 if (ext)
10941 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10942 {
10943 name = cpu_noarch [j].name;
10944 len = cpu_noarch [j].len;
10945 p = output_message (stream, p, message, start, &left, name,
10946 len);
10947 }
10948
8a2c8fef
L		 10949 *p = '\0';
10950 fprintf (stream, "%s\n", message);
10951}
10952
252b5132 10953void
8a2c8fef 10954md_show_usage (FILE *stream)
252b5132 10955{
4cc782b5
ILT		 10956#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10957 fprintf (stream, _("\
a38cf1db
AM		 10958 -Q ignored\n\
10959 -V print assembler version number\n\
b3b91714
AM		 10960 -k ignored\n"));
10961#endif
10962 fprintf (stream, _("\
12b55ccc 10963 -n Do not optimize code alignment\n\
b3b91714
AM		 10964 -q quieten some warnings\n"));
10965#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10966 fprintf (stream, _("\
a38cf1db 10967 -s ignored\n"));
b3b91714 10968#endif
321098a5
L		 10969#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10970 || defined (TE_PE) || defined (TE_PEP))
751d281c 10971 fprintf (stream, _("\
570561f7 10972 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10973#endif
b3b91714
AM		 10974#ifdef SVR4_COMMENT_CHARS
10975 fprintf (stream, _("\
10976 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10977#else
10978 fprintf (stream, _("\
b3b91714 10979 --divide ignored\n"));
4cc782b5 10980#endif
9103f4f4 10981 fprintf (stream, _("\
6305a203 10982 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10983 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10984 show_arch (stream, 0, 1);
8a2c8fef
L		 10985 fprintf (stream, _("\
10986 EXTENSION is combination of:\n"));
1ded5609 10987 show_arch (stream, 1, 0);
6305a203 10988 fprintf (stream, _("\
8a2c8fef 10989 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10990 show_arch (stream, 0, 0);
ba104c83 10991 fprintf (stream, _("\
c0f3af97
L		 10992 -msse2avx encode SSE instructions with VEX prefix\n"));
10993 fprintf (stream, _("\
daf50ae7
L		 10994 -msse-check=[none|error|warning]\n\
10995 check SSE instructions\n"));
10996 fprintf (stream, _("\
7bab8ab5
JB		 10997 -moperand-check=[none|error|warning]\n\
10998 check operand combinations for validity\n"));
10999 fprintf (stream, _("\
539f890d
L		 11000 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
11001 length\n"));
11002 fprintf (stream, _("\
43234a1e
L		 11003 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
11004 length\n"));
11005 fprintf (stream, _("\
11006 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
11007 for EVEX.W bit ignored instructions\n"));
11008 fprintf (stream, _("\
d3d3c6db
IT		 11009 -mevexrcig=[rne|rd|ru|rz]\n\
11010 encode EVEX instructions with specific EVEX.RC value\n\
11011 for SAE-only ignored instructions\n"));
11012 fprintf (stream, _("\
ba104c83
L		 11013 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
11014 fprintf (stream, _("\
11015 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
11016 fprintf (stream, _("\
11017 -mindex-reg support pseudo index registers\n"));
11018 fprintf (stream, _("\
11019 -mnaked-reg don't require `%%' prefix for registers\n"));
11020 fprintf (stream, _("\
7e8b059b 11021 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 11022 fprintf (stream, _("\
11023 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 11024# if defined (TE_PE) || defined (TE_PEP)
11025 fprintf (stream, _("\
11026 -mbig-obj generate big object files\n"));
11027#endif
d022bddd
IT		 11028 fprintf (stream, _("\
11029 -momit-lock-prefix=[no|yes]\n\
11030 strip all lock prefixes\n"));
5db04b09 11031 fprintf (stream, _("\
e4e00185
AS		 11032 -mfence-as-lock-add=[no|yes]\n\
11033 encode lfence, mfence and sfence as\n\
11034 lock addl $0x0, (%%{re}sp)\n"));
11035 fprintf (stream, _("\
0cb4071e
L		 11036 -mrelax-relocations=[no|yes]\n\
11037 generate relax relocations\n"));
11038 fprintf (stream, _("\
5db04b09
L		 11039 -mamd64 accept only AMD64 ISA\n"));
11040 fprintf (stream, _("\
11041 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 11042}
11043
3e73aa7c 11044#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 11045 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 11046 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 11047
11048/* Pick the target format to use. */
11049
47926f60 11050const char *
e3bb37b5 11051i386_target_format (void)
252b5132 11052{
351f65ca
L		 11053 if (!strncmp (default_arch, "x86_64", 6))
11054 {
11055 update_code_flag (CODE_64BIT, 1);
11056 if (default_arch[6] == '\0')
7f56bc95 11057 x86_elf_abi = X86_64_ABI;
351f65ca 11058 else
7f56bc95 11059 x86_elf_abi = X86_64_X32_ABI;
351f65ca 11060 }
3e73aa7c 11061 else if (!strcmp (default_arch, "i386"))
78f12dd3 11062 update_code_flag (CODE_32BIT, 1);
5197d474
L		 11063 else if (!strcmp (default_arch, "iamcu"))
11064 {
11065 update_code_flag (CODE_32BIT, 1);
11066 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11067 {
11068 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11069 cpu_arch_name = "iamcu";
11070 cpu_sub_arch_name = NULL;
11071 cpu_arch_flags = iamcu_flags;
11072 cpu_arch_isa = PROCESSOR_IAMCU;
11073 cpu_arch_isa_flags = iamcu_flags;
11074 if (!cpu_arch_tune_set)
11075 {
11076 cpu_arch_tune = cpu_arch_isa;
11077 cpu_arch_tune_flags = cpu_arch_isa_flags;
11078 }
11079 }
8d471ec1 11080 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 11081 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11082 cpu_arch_name);
11083 }
3e73aa7c 11084 else
2b5d6a91 11085 as_fatal (_("unknown architecture"));
89507696
JB		 11086
11087 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11088 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11089 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11090 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11091
252b5132
RH		 11092 switch (OUTPUT_FLAVOR)
11093 {
9384f2ff 11094#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 11095 case bfd_target_aout_flavour:
47926f60 11096 return AOUT_TARGET_FORMAT;
4c63da97 11097#endif
9384f2ff
AM		 11098#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11099# if defined (TE_PE) || defined (TE_PEP)
11100 case bfd_target_coff_flavour:
167ad85b
TG		 11101 if (flag_code == CODE_64BIT)
11102 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11103 else
11104 return "pe-i386";
9384f2ff 11105# elif defined (TE_GO32)
0561d57c
JK		 11106 case bfd_target_coff_flavour:
11107 return "coff-go32";
9384f2ff 11108# else
252b5132
RH		 11109 case bfd_target_coff_flavour:
11110 return "coff-i386";
9384f2ff 11111# endif
4c63da97 11112#endif
3e73aa7c 11113#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 11114 case bfd_target_elf_flavour:
3e73aa7c 11115 {
351f65ca
L		 11116 const char *format;
11117
11118 switch (x86_elf_abi)
4fa24527 11119 {
351f65ca
L		 11120 default:
11121 format = ELF_TARGET_FORMAT;
11122 break;
7f56bc95 11123 case X86_64_ABI:
351f65ca 11124 use_rela_relocations = 1;
4fa24527 11125 object_64bit = 1;
351f65ca
L		 11126 format = ELF_TARGET_FORMAT64;
11127 break;
7f56bc95 11128 case X86_64_X32_ABI:
4fa24527 11129 use_rela_relocations = 1;
351f65ca 11130 object_64bit = 1;
862be3fb 11131 disallow_64bit_reloc = 1;
351f65ca
L		 11132 format = ELF_TARGET_FORMAT32;
11133 break;
4fa24527 11134 }
3632d14b 11135 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 11136 {
7f56bc95 11137 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 11138 as_fatal (_("Intel L1OM is 64bit only"));
11139 return ELF_TARGET_L1OM_FORMAT;
11140 }
b49f93f6 11141 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 11142 {
11143 if (x86_elf_abi != X86_64_ABI)
11144 as_fatal (_("Intel K1OM is 64bit only"));
11145 return ELF_TARGET_K1OM_FORMAT;
11146 }
81486035
L		 11147 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11148 {
11149 if (x86_elf_abi != I386_ABI)
11150 as_fatal (_("Intel MCU is 32bit only"));
11151 return ELF_TARGET_IAMCU_FORMAT;
11152 }
8a9036a4 11153 else
351f65ca 11154 return format;
3e73aa7c 11155 }
e57f8c65
TG		 11156#endif
11157#if defined (OBJ_MACH_O)
11158 case bfd_target_mach_o_flavour:
d382c579
TG		 11159 if (flag_code == CODE_64BIT)
11160 {
11161 use_rela_relocations = 1;
11162 object_64bit = 1;
11163 return "mach-o-x86-64";
11164 }
11165 else
11166 return "mach-o-i386";
4c63da97 11167#endif
252b5132
RH		 11168 default:
11169 abort ();
11170 return NULL;
11171 }
11172}
11173
47926f60 11174#endif /* OBJ_MAYBE_ more than one */
252b5132 11175\f
252b5132 11176symbolS *
7016a5d5 11177md_undefined_symbol (char *name)
252b5132 11178{
18dc2407
ILT		 11179 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11180 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11181 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11182 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 11183 {
11184 if (!GOT_symbol)
11185 {
11186 if (symbol_find (name))
11187 as_bad (_("GOT already in symbol table"));
11188 GOT_symbol = symbol_new (name, undefined_section,
11189 (valueT) 0, &zero_address_frag);
11190 };
11191 return GOT_symbol;
11192 }
252b5132
RH		 11193 return 0;
11194}
11195
11196/* Round up a section size to the appropriate boundary. */
47926f60 11197
252b5132 11198valueT
7016a5d5 11199md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 11200{
4c63da97
AM		 11201#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11202 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11203 {
11204 /* For a.out, force the section size to be aligned. If we don't do
11205 this, BFD will align it for us, but it will not write out the
11206 final bytes of the section. This may be a bug in BFD, but it is
11207 easier to fix it here since that is how the other a.out targets
11208 work. */
11209 int align;
11210
11211 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 11212 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 11213 }
252b5132
RH		 11214#endif
11215
11216 return size;
11217}
11218
11219/* On the i386, PC-relative offsets are relative to the start of the
11220 next instruction. That is, the address of the offset, plus its
11221 size, since the offset is always the last part of the insn. */
11222
11223long
e3bb37b5 11224md_pcrel_from (fixS *fixP)
252b5132
RH		 11225{
11226 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11227}
11228
11229#ifndef I386COFF
11230
11231static void
e3bb37b5 11232s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 11233{
29b0f896 11234 int temp;
252b5132 11235
8a75718c
JB		 11236#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11237 if (IS_ELF)
11238 obj_elf_section_change_hook ();
11239#endif
252b5132
RH		 11240 temp = get_absolute_expression ();
11241 subseg_set (bss_section, (subsegT) temp);
11242 demand_empty_rest_of_line ();
11243}
11244
11245#endif
11246
252b5132 11247void
e3bb37b5 11248i386_validate_fix (fixS *fixp)
252b5132 11249{
02a86693 11250 if (fixp->fx_subsy)
252b5132 11251 {
02a86693 11252 if (fixp->fx_subsy == GOT_symbol)
23df1078 11253 {
02a86693
L		 11254 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11255 {
11256 if (!object_64bit)
11257 abort ();
11258#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11259 if (fixp->fx_tcbit2)
56ceb5b5
L		 11260 fixp->fx_r_type = (fixp->fx_tcbit
11261 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11262 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 11263 else
11264#endif
11265 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11266 }
d6ab8113 11267 else
02a86693
L		 11268 {
11269 if (!object_64bit)
11270 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11271 else
11272 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11273 }
11274 fixp->fx_subsy = 0;
23df1078 11275 }
252b5132 11276 }
02a86693
L		 11277#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11278 else if (!object_64bit)
11279 {
11280 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11281 && fixp->fx_tcbit2)
11282 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11283 }
11284#endif
252b5132
RH		 11285}
11286
252b5132 11287arelent *
7016a5d5 11288tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 11289{
11290 arelent *rel;
11291 bfd_reloc_code_real_type code;
11292
11293 switch (fixp->fx_r_type)
11294 {
8ce3d284 11295#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 11296 case BFD_RELOC_SIZE32:
11297 case BFD_RELOC_SIZE64:
11298 if (S_IS_DEFINED (fixp->fx_addsy)
11299 && !S_IS_EXTERNAL (fixp->fx_addsy))
11300 {
11301 /* Resolve size relocation against local symbol to size of
11302 the symbol plus addend. */
11303 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11304 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11305 && !fits_in_unsigned_long (value))
11306 as_bad_where (fixp->fx_file, fixp->fx_line,
11307 _("symbol size computation overflow"));
11308 fixp->fx_addsy = NULL;
11309 fixp->fx_subsy = NULL;
11310 md_apply_fix (fixp, (valueT *) &value, NULL);
11311 return NULL;
11312 }
8ce3d284 11313#endif
1a0670f3 11314 /* Fall through. */
8fd4256d 11315
3e73aa7c
JH		 11316 case BFD_RELOC_X86_64_PLT32:
11317 case BFD_RELOC_X86_64_GOT32:
11318 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11319 case BFD_RELOC_X86_64_GOTPCRELX:
11320 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 11321 case BFD_RELOC_386_PLT32:
11322 case BFD_RELOC_386_GOT32:
02a86693 11323 case BFD_RELOC_386_GOT32X:
252b5132
RH		 11324 case BFD_RELOC_386_GOTOFF:
11325 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 11326 case BFD_RELOC_386_TLS_GD:
11327 case BFD_RELOC_386_TLS_LDM:
11328 case BFD_RELOC_386_TLS_LDO_32:
11329 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 11330 case BFD_RELOC_386_TLS_IE:
11331 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 11332 case BFD_RELOC_386_TLS_LE_32:
11333 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 11334 case BFD_RELOC_386_TLS_GOTDESC:
11335 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 11336 case BFD_RELOC_X86_64_TLSGD:
11337 case BFD_RELOC_X86_64_TLSLD:
11338 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 11339 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 11340 case BFD_RELOC_X86_64_GOTTPOFF:
11341 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 11342 case BFD_RELOC_X86_64_TPOFF64:
11343 case BFD_RELOC_X86_64_GOTOFF64:
11344 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 11345 case BFD_RELOC_X86_64_GOT64:
11346 case BFD_RELOC_X86_64_GOTPCREL64:
11347 case BFD_RELOC_X86_64_GOTPC64:
11348 case BFD_RELOC_X86_64_GOTPLT64:
11349 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 11350 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11351 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 11352 case BFD_RELOC_RVA:
11353 case BFD_RELOC_VTABLE_ENTRY:
11354 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 11355#ifdef TE_PE
11356 case BFD_RELOC_32_SECREL:
11357#endif
252b5132
RH		 11358 code = fixp->fx_r_type;
11359 break;
dbbaec26
L		 11360 case BFD_RELOC_X86_64_32S:
11361 if (!fixp->fx_pcrel)
11362 {
11363 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11364 code = fixp->fx_r_type;
11365 break;
11366 }
1a0670f3 11367 /* Fall through. */
252b5132 11368 default:
93382f6d 11369 if (fixp->fx_pcrel)
252b5132 11370 {
93382f6d
AM		 11371 switch (fixp->fx_size)
11372 {
11373 default:
b091f402
AM		 11374 as_bad_where (fixp->fx_file, fixp->fx_line,
11375 _("can not do %d byte pc-relative relocation"),
11376 fixp->fx_size);
93382f6d
AM		 11377 code = BFD_RELOC_32_PCREL;
11378 break;
11379 case 1: code = BFD_RELOC_8_PCREL; break;
11380 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 11381 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 11382#ifdef BFD64
11383 case 8: code = BFD_RELOC_64_PCREL; break;
11384#endif
93382f6d
AM		 11385 }
11386 }
11387 else
11388 {
11389 switch (fixp->fx_size)
11390 {
11391 default:
b091f402
AM		 11392 as_bad_where (fixp->fx_file, fixp->fx_line,
11393 _("can not do %d byte relocation"),
11394 fixp->fx_size);
93382f6d
AM		 11395 code = BFD_RELOC_32;
11396 break;
11397 case 1: code = BFD_RELOC_8; break;
11398 case 2: code = BFD_RELOC_16; break;
11399 case 4: code = BFD_RELOC_32; break;
937149dd 11400#ifdef BFD64
3e73aa7c 11401 case 8: code = BFD_RELOC_64; break;
937149dd 11402#endif
93382f6d 11403 }
252b5132
RH		 11404 }
11405 break;
11406 }
252b5132 11407
d182319b
JB		 11408 if ((code == BFD_RELOC_32
11409 || code == BFD_RELOC_32_PCREL
11410 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 11411 && GOT_symbol
11412 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 11413 {
4fa24527 11414 if (!object_64bit)
d6ab8113
JB		 11415 code = BFD_RELOC_386_GOTPC;
11416 else
11417 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 11418 }
7b81dfbb
AJ		 11419 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11420 && GOT_symbol
11421 && fixp->fx_addsy == GOT_symbol)
11422 {
11423 code = BFD_RELOC_X86_64_GOTPC64;
11424 }
252b5132 11425
add39d23
TS		 11426 rel = XNEW (arelent);
11427 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 11428 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 11429
11430 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 11431
3e73aa7c
JH		 11432 if (!use_rela_relocations)
11433 {
11434 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11435 vtable entry to be used in the relocation's section offset. */
11436 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11437 rel->address = fixp->fx_offset;
fbeb56a4
DK		 11438#if defined (OBJ_COFF) && defined (TE_PE)
11439 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11440 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11441 else
11442#endif
c6682705 11443 rel->addend = 0;
3e73aa7c
JH		 11444 }
11445 /* Use the rela in 64bit mode. */
252b5132 11446 else
3e73aa7c 11447 {
862be3fb
L		 11448 if (disallow_64bit_reloc)
11449 switch (code)
11450 {
862be3fb
L		 11451 case BFD_RELOC_X86_64_DTPOFF64:
11452 case BFD_RELOC_X86_64_TPOFF64:
11453 case BFD_RELOC_64_PCREL:
11454 case BFD_RELOC_X86_64_GOTOFF64:
11455 case BFD_RELOC_X86_64_GOT64:
11456 case BFD_RELOC_X86_64_GOTPCREL64:
11457 case BFD_RELOC_X86_64_GOTPC64:
11458 case BFD_RELOC_X86_64_GOTPLT64:
11459 case BFD_RELOC_X86_64_PLTOFF64:
11460 as_bad_where (fixp->fx_file, fixp->fx_line,
11461 _("cannot represent relocation type %s in x32 mode"),
11462 bfd_get_reloc_code_name (code));
11463 break;
11464 default:
11465 break;
11466 }
11467
062cd5e7
AS		 11468 if (!fixp->fx_pcrel)
11469 rel->addend = fixp->fx_offset;
11470 else
11471 switch (code)
11472 {
11473 case BFD_RELOC_X86_64_PLT32:
11474 case BFD_RELOC_X86_64_GOT32:
11475 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11476 case BFD_RELOC_X86_64_GOTPCRELX:
11477 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 11478 case BFD_RELOC_X86_64_TLSGD:
11479 case BFD_RELOC_X86_64_TLSLD:
11480 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 11481 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11482 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 11483 rel->addend = fixp->fx_offset - fixp->fx_size;
11484 break;
11485 default:
11486 rel->addend = (section->vma
11487 - fixp->fx_size
11488 + fixp->fx_addnumber
11489 + md_pcrel_from (fixp));
11490 break;
11491 }
3e73aa7c
JH		 11492 }
11493
252b5132
RH		 11494 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11495 if (rel->howto == NULL)
11496 {
11497 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 11498 _("cannot represent relocation type %s"),
252b5132
RH		 11499 bfd_get_reloc_code_name (code));
11500 /* Set howto to a garbage value so that we can keep going. */
11501 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 11502 gas_assert (rel->howto != NULL);
252b5132
RH		 11503 }
11504
11505 return rel;
11506}
11507
ee86248c 11508#include "tc-i386-intel.c"
54cfded0 11509
a60de03c
JB		 11510void
11511tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 11512{
a60de03c
JB		 11513 int saved_naked_reg;
11514 char saved_register_dot;
54cfded0 11515
a60de03c
JB		 11516 saved_naked_reg = allow_naked_reg;
11517 allow_naked_reg = 1;
11518 saved_register_dot = register_chars['.'];
11519 register_chars['.'] = '.';
11520 allow_pseudo_reg = 1;
11521 expression_and_evaluate (exp);
11522 allow_pseudo_reg = 0;
11523 register_chars['.'] = saved_register_dot;
11524 allow_naked_reg = saved_naked_reg;
11525
e96d56a1 11526 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 11527 {
a60de03c
JB		 11528 if ((addressT) exp->X_add_number < i386_regtab_size)
11529 {
11530 exp->X_op = O_constant;
11531 exp->X_add_number = i386_regtab[exp->X_add_number]
11532 .dw2_regnum[flag_code >> 1];
11533 }
11534 else
11535 exp->X_op = O_illegal;
54cfded0 11536 }
54cfded0
AM		 11537}
11538
11539void
11540tc_x86_frame_initial_instructions (void)
11541{
a60de03c
JB		 11542 static unsigned int sp_regno[2];
11543
11544 if (!sp_regno[flag_code >> 1])
11545 {
11546 char *saved_input = input_line_pointer;
11547 char sp[][4] = {"esp", "rsp"};
11548 expressionS exp;
a4447b93 11549
a60de03c
JB		 11550 input_line_pointer = sp[flag_code >> 1];
11551 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 11552 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 11553 sp_regno[flag_code >> 1] = exp.X_add_number;
11554 input_line_pointer = saved_input;
11555 }
a4447b93 11556
61ff971f
L		 11557 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11558 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 11559}
d2b2c203 11560
d7921315
L		 11561int
11562x86_dwarf2_addr_size (void)
11563{
11564#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11565 if (x86_elf_abi == X86_64_X32_ABI)
11566 return 4;
11567#endif
11568 return bfd_arch_bits_per_address (stdoutput) / 8;
11569}
11570
d2b2c203
DJ		 11571int
11572i386_elf_section_type (const char *str, size_t len)
11573{
11574 if (flag_code == CODE_64BIT
11575 && len == sizeof ("unwind") - 1
11576 && strncmp (str, "unwind", 6) == 0)
11577 return SHT_X86_64_UNWIND;
11578
11579 return -1;
11580}
bb41ade5 11581
ad5fec3b
EB		 11582#ifdef TE_SOLARIS
11583void
11584i386_solaris_fix_up_eh_frame (segT sec)
11585{
11586 if (flag_code == CODE_64BIT)
11587 elf_section_type (sec) = SHT_X86_64_UNWIND;
11588}
11589#endif
11590
bb41ade5
AM		 11591#ifdef TE_PE
11592void
11593tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11594{
91d6fa6a 11595 expressionS exp;
bb41ade5 11596
91d6fa6a
NC		 11597 exp.X_op = O_secrel;
11598 exp.X_add_symbol = symbol;
11599 exp.X_add_number = 0;
11600 emit_expr (&exp, size);
bb41ade5
AM		 11601}
11602#endif
3b22753a
L		 11603
11604#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11605/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11606
01e1a5bc 11607bfd_vma
6d4af3c2 11608x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11609{
11610 if (flag_code == CODE_64BIT)
11611 {
11612 if (letter == 'l')
11613 return SHF_X86_64_LARGE;
11614
8f3bae45 11615 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11616 }
3b22753a 11617 else
8f3bae45 11618 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11619 return -1;
11620}
11621
01e1a5bc 11622bfd_vma
3b22753a
L		 11623x86_64_section_word (char *str, size_t len)
11624{
8620418b 11625 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11626 return SHF_X86_64_LARGE;
11627
11628 return -1;
11629}
11630
11631static void
11632handle_large_common (int small ATTRIBUTE_UNUSED)
11633{
11634 if (flag_code != CODE_64BIT)
11635 {
11636 s_comm_internal (0, elf_common_parse);
11637 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11638 }
11639 else
11640 {
11641 static segT lbss_section;
11642 asection *saved_com_section_ptr = elf_com_section_ptr;
11643 asection *saved_bss_section = bss_section;
11644
11645 if (lbss_section == NULL)
11646 {
11647 flagword applicable;
11648 segT seg = now_seg;
11649 subsegT subseg = now_subseg;
11650
11651 /* The .lbss section is for local .largecomm symbols. */
11652 lbss_section = subseg_new (".lbss", 0);
11653 applicable = bfd_applicable_section_flags (stdoutput);
11654 bfd_set_section_flags (stdoutput, lbss_section,
11655 applicable & SEC_ALLOC);
11656 seg_info (lbss_section)->bss = 1;
11657
11658 subseg_set (seg, subseg);
11659 }
11660
11661 elf_com_section_ptr = &_bfd_elf_large_com_section;
11662 bss_section = lbss_section;
11663
11664 s_comm_internal (0, elf_common_parse);
11665
11666 elf_com_section_ptr = saved_com_section_ptr;
11667 bss_section = saved_bss_section;
11668 }
11669}
11670#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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