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* gdb.mi/mi-watch.exp (test_watchpoint_all): Pass the watchpoint
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4dc85607 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
e3bb37b5
L		 66static void set_code_flag (int);
67static void set_16bit_gcc_code_flag (int);
68static void set_intel_syntax (int);
69static void set_cpu_arch (int);
6482c264 70#ifdef TE_PE
e3bb37b5 71static void pe_directive_secrel (int);
6482c264 72#endif
e3bb37b5
L		 73static void signed_cons (int);
74static char *output_invalid (int c);
75static int i386_operand (char *);
76static int i386_intel_operand (char *, int);
77static const reg_entry *parse_register (char *, char **);
78static char *parse_insn (char *, char *);
79static char *parse_operands (char *, const char *);
80static void swap_operands (void);
4d456e3d 81static void swap_2_operands (int, int);
e3bb37b5
L		 82static void optimize_imm (void);
83static void optimize_disp (void);
84static int match_template (void);
85static int check_string (void);
86static int process_suffix (void);
87static int check_byte_reg (void);
88static int check_long_reg (void);
89static int check_qword_reg (void);
90static int check_word_reg (void);
91static int finalize_imm (void);
92static int process_operands (void);
93static const seg_entry *build_modrm_byte (void);
94static void output_insn (void);
95static void output_imm (fragS *, offsetT);
96static void output_disp (fragS *, offsetT);
29b0f896 97#ifndef I386COFF
e3bb37b5 98static void s_bss (int);
252b5132 99#endif
17d4e2a2
L		 100#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
101static void handle_large_common (int small ATTRIBUTE_UNUSED);
102#endif
252b5132 103
a847613f 104static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 105
252b5132 106/* 'md_assemble ()' gathers together information and puts it into a
47926f60 107 i386_insn. */
252b5132 108
520dc8e8
AM		 109union i386_op
110 {
111 expressionS *disps;
112 expressionS *imms;
113 const reg_entry *regs;
114 };
115
252b5132
RH		 116struct _i386_insn
117 {
47926f60 118 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 119 template tm;
120
121 /* SUFFIX holds the instruction mnemonic suffix if given.
122 (e.g. 'l' for 'movl') */
123 char suffix;
124
47926f60 125 /* OPERANDS gives the number of given operands. */
252b5132
RH		 126 unsigned int operands;
127
128 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
129 of given register, displacement, memory operands and immediate
47926f60 130 operands. */
252b5132
RH		 131 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
132
133 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 134 use OP[i] for the corresponding operand. */
40fb9820 135 i386_operand_type types[MAX_OPERANDS];
252b5132 136
520dc8e8
AM		 137 /* Displacement expression, immediate expression, or register for each
138 operand. */
139 union i386_op op[MAX_OPERANDS];
252b5132 140
3e73aa7c
JH		 141 /* Flags for operands. */
142 unsigned int flags[MAX_OPERANDS];
143#define Operand_PCrel 1
144
252b5132 145 /* Relocation type for operand */
f86103b7 146 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 147
252b5132
RH		 148 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
149 the base index byte below. */
150 const reg_entry *base_reg;
151 const reg_entry *index_reg;
152 unsigned int log2_scale_factor;
153
154 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 155 explicit segment overrides are given. */
ce8a8b2f 156 const seg_entry *seg[2];
252b5132
RH		 157
158 /* PREFIX holds all the given prefix opcodes (usually null).
159 PREFIXES is the number of prefix opcodes. */
160 unsigned int prefixes;
161 unsigned char prefix[MAX_PREFIXES];
162
163 /* RM and SIB are the modrm byte and the sib byte where the
164 addressing modes of this insn are encoded. */
165
166 modrm_byte rm;
3e73aa7c 167 rex_byte rex;
252b5132
RH		 168 sib_byte sib;
169 };
170
171typedef struct _i386_insn i386_insn;
172
173/* List of chars besides those in app.c:symbol_chars that can start an
174 operand. Used to prevent the scrubber eating vital white-space. */
32137342 175const char extra_symbol_chars[] = "*%-(["
252b5132 176#ifdef LEX_AT
32137342
NC		 177 "@"
178#endif
179#ifdef LEX_QM
180 "?"
252b5132 181#endif
32137342 182 ;
252b5132 183
29b0f896
AM		 184#if (defined (TE_I386AIX) \
185 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 186 && !defined (TE_GNU) \
29b0f896 187 && !defined (TE_LINUX) \
32137342 188 && !defined (TE_NETWARE) \
29b0f896
AM		 189 && !defined (TE_FreeBSD) \
190 && !defined (TE_NetBSD)))
252b5132 191/* This array holds the chars that always start a comment. If the
b3b91714
AM		 192 pre-processor is disabled, these aren't very useful. The option
193 --divide will remove '/' from this list. */
194const char *i386_comment_chars = "#/";
195#define SVR4_COMMENT_CHARS 1
252b5132 196#define PREFIX_SEPARATOR '\\'
252b5132 197
b3b91714
AM		 198#else
199const char *i386_comment_chars = "#";
200#define PREFIX_SEPARATOR '/'
201#endif
202
252b5132
RH		 203/* This array holds the chars that only start a comment at the beginning of
204 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 205 .line and .file directives will appear in the pre-processed output.
206 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 207 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 208 #NO_APP at the beginning of its output.
209 Also note that comments started like this one will always work if
252b5132 210 '/' isn't otherwise defined. */
b3b91714 211const char line_comment_chars[] = "#/";
252b5132 212
63a0b638 213const char line_separator_chars[] = ";";
252b5132 214
ce8a8b2f
AM		 215/* Chars that can be used to separate mant from exp in floating point
216 nums. */
252b5132
RH		 217const char EXP_CHARS[] = "eE";
218
ce8a8b2f
AM		 219/* Chars that mean this number is a floating point constant
220 As in 0f12.456
221 or 0d1.2345e12. */
252b5132
RH		 222const char FLT_CHARS[] = "fFdDxX";
223
ce8a8b2f 224/* Tables for lexical analysis. */
252b5132
RH		 225static char mnemonic_chars[256];
226static char register_chars[256];
227static char operand_chars[256];
228static char identifier_chars[256];
229static char digit_chars[256];
230
ce8a8b2f 231/* Lexical macros. */
252b5132
RH		 232#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
233#define is_operand_char(x) (operand_chars[(unsigned char) x])
234#define is_register_char(x) (register_chars[(unsigned char) x])
235#define is_space_char(x) ((x) == ' ')
236#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
237#define is_digit_char(x) (digit_chars[(unsigned char) x])
238
0234cb7c 239/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 240static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
241
242/* md_assemble() always leaves the strings it's passed unaltered. To
243 effect this we maintain a stack of saved characters that we've smashed
244 with '\0's (indicating end of strings for various sub-fields of the
47926f60 245 assembler instruction). */
252b5132 246static char save_stack[32];
ce8a8b2f 247static char *save_stack_p;
252b5132
RH		 248#define END_STRING_AND_SAVE(s) \
249 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
250#define RESTORE_END_STRING(s) \
251 do { *(s) = *--save_stack_p; } while (0)
252
47926f60 253/* The instruction we're assembling. */
252b5132
RH		 254static i386_insn i;
255
256/* Possible templates for current insn. */
257static const templates *current_templates;
258
31b2323c
L		 259/* Per instruction expressionS buffers: max displacements & immediates. */
260static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
261static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 262
47926f60
KH		 263/* Current operand we are working on. */
264static int this_operand;
252b5132 265
3e73aa7c
JH		 266/* We support four different modes. FLAG_CODE variable is used to distinguish
267 these. */
268
269enum flag_code {
270 CODE_32BIT,
271 CODE_16BIT,
272 CODE_64BIT };
f3c180ae 273#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 274
275static enum flag_code flag_code;
4fa24527 276static unsigned int object_64bit;
3e73aa7c
JH		 277static int use_rela_relocations = 0;
278
279/* The names used to print error messages. */
b77a7acd 280static const char *flag_code_names[] =
3e73aa7c
JH		 281 {
282 "32",
283 "16",
284 "64"
285 };
252b5132 286
47926f60
KH		 287/* 1 for intel syntax,
288 0 if att syntax. */
289static int intel_syntax = 0;
252b5132 290
47926f60
KH		 291/* 1 if register prefix % not required. */
292static int allow_naked_reg = 0;
252b5132 293
2ca3ace5
L		 294/* Register prefix used for error message. */
295static const char *register_prefix = "%";
296
47926f60
KH		 297/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
298 leave, push, and pop instructions so that gcc has the same stack
299 frame as in 32 bit mode. */
300static char stackop_size = '\0';
eecb386c 301
12b55ccc
L		 302/* Non-zero to optimize code alignment. */
303int optimize_align_code = 1;
304
47926f60
KH		 305/* Non-zero to quieten some warnings. */
306static int quiet_warnings = 0;
a38cf1db 307
47926f60
KH		 308/* CPU name. */
309static const char *cpu_arch_name = NULL;
5c6af06e 310static const char *cpu_sub_arch_name = NULL;
a38cf1db 311
47926f60 312/* CPU feature flags. */
40fb9820
L		 313static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
314
315/* Bitwise NOT of cpu_arch_flags. */
316static i386_cpu_flags cpu_arch_flags_not;
a38cf1db 317
ccc9c027
L		 318/* If we have selected a cpu we are generating instructions for. */
319static int cpu_arch_tune_set = 0;
320
9103f4f4
L		 321/* Cpu we are generating instructions for. */
322static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
323
324/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 325static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 326
ccc9c027
L		 327/* CPU instruction set architecture used. */
328static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
329
9103f4f4 330/* CPU feature flags of instruction set architecture used. */
40fb9820 331static i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 332
fddf5b5b
AM		 333/* If set, conditional jumps are not automatically promoted to handle
334 larger than a byte offset. */
335static unsigned int no_cond_jump_promotion = 0;
336
29b0f896 337/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 338static symbolS *GOT_symbol;
29b0f896 339
a4447b93
RH		 340/* The dwarf2 return column, adjusted for 32 or 64 bit. */
341unsigned int x86_dwarf2_return_column;
342
343/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
344int x86_cie_data_alignment;
345
252b5132 346/* Interface to relax_segment.
fddf5b5b
AM		 347 There are 3 major relax states for 386 jump insns because the
348 different types of jumps add different sizes to frags when we're
349 figuring out what sort of jump to choose to reach a given label. */
252b5132 350
47926f60 351/* Types. */
93c2a809
AM		 352#define UNCOND_JUMP 0
353#define COND_JUMP 1
354#define COND_JUMP86 2
fddf5b5b 355
47926f60 356/* Sizes. */
252b5132
RH		 357#define CODE16 1
358#define SMALL 0
29b0f896 359#define SMALL16 (SMALL | CODE16)
252b5132 360#define BIG 2
29b0f896 361#define BIG16 (BIG | CODE16)
252b5132
RH		 362
363#ifndef INLINE
364#ifdef __GNUC__
365#define INLINE __inline__
366#else
367#define INLINE
368#endif
369#endif
370
fddf5b5b
AM		 371#define ENCODE_RELAX_STATE(type, size) \
372 ((relax_substateT) (((type) << 2) | (size)))
373#define TYPE_FROM_RELAX_STATE(s) \
374 ((s) >> 2)
375#define DISP_SIZE_FROM_RELAX_STATE(s) \
376 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 377
378/* This table is used by relax_frag to promote short jumps to long
379 ones where necessary. SMALL (short) jumps may be promoted to BIG
380 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
381 don't allow a short jump in a 32 bit code segment to be promoted to
382 a 16 bit offset jump because it's slower (requires data size
383 prefix), and doesn't work, unless the destination is in the bottom
384 64k of the code segment (The top 16 bits of eip are zeroed). */
385
386const relax_typeS md_relax_table[] =
387{
24eab124
AM		 388 /* The fields are:
389 1) most positive reach of this state,
390 2) most negative reach of this state,
93c2a809 391 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 392 4) which index into the table to try if we can't fit into this one. */
252b5132 393
fddf5b5b 394 /* UNCOND_JUMP states. */
93c2a809
AM		 395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
396 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
397 /* dword jmp adds 4 bytes to frag:
398 0 extra opcode bytes, 4 displacement bytes. */
252b5132 399 {0, 0, 4, 0},
93c2a809
AM		 400 /* word jmp adds 2 byte2 to frag:
401 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 402 {0, 0, 2, 0},
403
93c2a809
AM		 404 /* COND_JUMP states. */
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
406 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
407 /* dword conditionals adds 5 bytes to frag:
408 1 extra opcode byte, 4 displacement bytes. */
409 {0, 0, 5, 0},
fddf5b5b 410 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 411 1 extra opcode byte, 2 displacement bytes. */
412 {0, 0, 3, 0},
413
414 /* COND_JUMP86 states. */
415 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
416 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
417 /* dword conditionals adds 5 bytes to frag:
418 1 extra opcode byte, 4 displacement bytes. */
419 {0, 0, 5, 0},
420 /* word conditionals add 4 bytes to frag:
421 1 displacement byte and a 3 byte long branch insn. */
422 {0, 0, 4, 0}
252b5132
RH		 423};
424
9103f4f4
L		 425static const arch_entry cpu_arch[] =
426{
427 {"generic32", PROCESSOR_GENERIC32,
40fb9820 428 CPU_GENERIC32_FLAGS },
9103f4f4 429 {"generic64", PROCESSOR_GENERIC64,
40fb9820 430 CPU_GENERIC64_FLAGS },
9103f4f4 431 {"i8086", PROCESSOR_UNKNOWN,
40fb9820 432 CPU_NONE_FLAGS },
9103f4f4 433 {"i186", PROCESSOR_UNKNOWN,
40fb9820 434 CPU_I186_FLAGS },
9103f4f4 435 {"i286", PROCESSOR_UNKNOWN,
40fb9820 436 CPU_I286_FLAGS },
76bc74dc 437 {"i386", PROCESSOR_I386,
40fb9820 438 CPU_I386_FLAGS },
9103f4f4 439 {"i486", PROCESSOR_I486,
40fb9820 440 CPU_I486_FLAGS },
9103f4f4 441 {"i586", PROCESSOR_PENTIUM,
40fb9820 442 CPU_I586_FLAGS },
9103f4f4 443 {"i686", PROCESSOR_PENTIUMPRO,
40fb9820 444 CPU_I686_FLAGS },
9103f4f4 445 {"pentium", PROCESSOR_PENTIUM,
40fb9820 446 CPU_I586_FLAGS },
9103f4f4 447 {"pentiumpro",PROCESSOR_PENTIUMPRO,
40fb9820 448 CPU_I686_FLAGS },
9103f4f4 449 {"pentiumii", PROCESSOR_PENTIUMPRO,
40fb9820 450 CPU_P2_FLAGS },
9103f4f4 451 {"pentiumiii",PROCESSOR_PENTIUMPRO,
40fb9820 452 CPU_P3_FLAGS },
9103f4f4 453 {"pentium4", PROCESSOR_PENTIUM4,
40fb9820 454 CPU_P4_FLAGS },
9103f4f4 455 {"prescott", PROCESSOR_NOCONA,
40fb9820 456 CPU_CORE_FLAGS },
9103f4f4 457 {"nocona", PROCESSOR_NOCONA,
40fb9820 458 CPU_NOCONA_FLAGS },
ef05d495 459 {"yonah", PROCESSOR_CORE,
40fb9820 460 CPU_CORE_FLAGS },
ef05d495 461 {"core", PROCESSOR_CORE,
40fb9820 462 CPU_CORE_FLAGS },
ef05d495 463 {"merom", PROCESSOR_CORE2,
40fb9820 464 CPU_CORE2_FLAGS },
ef05d495 465 {"core2", PROCESSOR_CORE2,
40fb9820 466 CPU_CORE2_FLAGS },
9103f4f4 467 {"k6", PROCESSOR_K6,
40fb9820 468 CPU_K6_FLAGS },
9103f4f4 469 {"k6_2", PROCESSOR_K6,
40fb9820 470 CPU_K6_2_FLAGS },
9103f4f4 471 {"athlon", PROCESSOR_ATHLON,
40fb9820 472 CPU_ATHLON_FLAGS },
9103f4f4 473 {"sledgehammer", PROCESSOR_K8,
40fb9820 474 CPU_K8_FLAGS },
9103f4f4 475 {"opteron", PROCESSOR_K8,
40fb9820 476 CPU_K8_FLAGS },
9103f4f4 477 {"k8", PROCESSOR_K8,
40fb9820 478 CPU_K8_FLAGS },
050dfa73 479 {"amdfam10", PROCESSOR_AMDFAM10,
40fb9820 480 CPU_AMDFAM10_FLAGS },
9103f4f4 481 {".mmx", PROCESSOR_UNKNOWN,
40fb9820 482 CPU_MMX_FLAGS },
9103f4f4 483 {".sse", PROCESSOR_UNKNOWN,
40fb9820 484 CPU_SSE_FLAGS },
9103f4f4 485 {".sse2", PROCESSOR_UNKNOWN,
40fb9820 486 CPU_SSE2_FLAGS },
9103f4f4 487 {".sse3", PROCESSOR_UNKNOWN,
40fb9820 488 CPU_SSE3_FLAGS },
ef05d495 489 {".ssse3", PROCESSOR_UNKNOWN,
40fb9820 490 CPU_SSSE3_FLAGS },
42903f7f 491 {".sse4.1", PROCESSOR_UNKNOWN,
40fb9820 492 CPU_SSE4_1_FLAGS },
381d071f 493 {".sse4.2", PROCESSOR_UNKNOWN,
40fb9820 494 CPU_SSE4_2_FLAGS },
381d071f 495 {".sse4", PROCESSOR_UNKNOWN,
40fb9820 496 CPU_SSE4_2_FLAGS },
9103f4f4 497 {".3dnow", PROCESSOR_UNKNOWN,
40fb9820 498 CPU_3DNOW_FLAGS },
9103f4f4 499 {".3dnowa", PROCESSOR_UNKNOWN,
40fb9820 500 CPU_3DNOWA_FLAGS },
9103f4f4 501 {".padlock", PROCESSOR_UNKNOWN,
40fb9820 502 CPU_PADLOCK_FLAGS },
9103f4f4 503 {".pacifica", PROCESSOR_UNKNOWN,
40fb9820 504 CPU_SVME_FLAGS },
9103f4f4 505 {".svme", PROCESSOR_UNKNOWN,
40fb9820 506 CPU_SVME_FLAGS },
050dfa73 507 {".sse4a", PROCESSOR_UNKNOWN,
40fb9820 508 CPU_SSE4A_FLAGS },
050dfa73 509 {".abm", PROCESSOR_UNKNOWN,
40fb9820 510 CPU_ABM_FLAGS },
e413e4e9
AM		 511};
512
29b0f896
AM		 513const pseudo_typeS md_pseudo_table[] =
514{
515#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
516 {"align", s_align_bytes, 0},
517#else
518 {"align", s_align_ptwo, 0},
519#endif
520 {"arch", set_cpu_arch, 0},
521#ifndef I386COFF
522 {"bss", s_bss, 0},
523#endif
524 {"ffloat", float_cons, 'f'},
525 {"dfloat", float_cons, 'd'},
526 {"tfloat", float_cons, 'x'},
527 {"value", cons, 2},
d182319b 528 {"slong", signed_cons, 4},
29b0f896
AM		 529 {"noopt", s_ignore, 0},
530 {"optim", s_ignore, 0},
531 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
532 {"code16", set_code_flag, CODE_16BIT},
533 {"code32", set_code_flag, CODE_32BIT},
534 {"code64", set_code_flag, CODE_64BIT},
535 {"intel_syntax", set_intel_syntax, 1},
536 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 537#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
538 {"largecomm", handle_large_common, 0},
07a53e5c 539#else
e3bb37b5 540 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 541 {"loc", dwarf2_directive_loc, 0},
542 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 543#endif
6482c264
NC		 544#ifdef TE_PE
545 {"secrel32", pe_directive_secrel, 0},
546#endif
29b0f896
AM		 547 {0, 0, 0}
548};
549
550/* For interface with expression (). */
551extern char *input_line_pointer;
552
553/* Hash table for instruction mnemonic lookup. */
554static struct hash_control *op_hash;
555
556/* Hash table for register lookup. */
557static struct hash_control *reg_hash;
558\f
252b5132 559void
e3bb37b5 560i386_align_code (fragS *fragP, int count)
252b5132 561{
ce8a8b2f
AM		 562 /* Various efficient no-op patterns for aligning code labels.
563 Note: Don't try to assemble the instructions in the comments.
564 0L and 0w are not legal. */
252b5132
RH		 565 static const char f32_1[] =
566 {0x90}; /* nop */
567 static const char f32_2[] =
ccc9c027 568 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 569 static const char f32_3[] =
570 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
571 static const char f32_4[] =
572 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
573 static const char f32_5[] =
574 {0x90, /* nop */
575 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
576 static const char f32_6[] =
577 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
578 static const char f32_7[] =
579 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
580 static const char f32_8[] =
581 {0x90, /* nop */
582 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
583 static const char f32_9[] =
584 {0x89,0xf6, /* movl %esi,%esi */
585 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
586 static const char f32_10[] =
587 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
588 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
589 static const char f32_11[] =
590 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
591 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
592 static const char f32_12[] =
593 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
594 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
595 static const char f32_13[] =
596 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
597 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
598 static const char f32_14[] =
599 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
600 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 601 static const char f16_3[] =
602 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 603 static const char f16_4[] =
604 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
605 static const char f16_5[] =
606 {0x90, /* nop */
607 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
608 static const char f16_6[] =
609 {0x89,0xf6, /* mov %si,%si */
610 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
611 static const char f16_7[] =
612 {0x8d,0x74,0x00, /* lea 0(%si),%si */
613 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
614 static const char f16_8[] =
615 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
616 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 617 static const char jump_31[] =
618 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
619 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
620 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
621 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 622 static const char *const f32_patt[] = {
623 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 624 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 625 };
626 static const char *const f16_patt[] = {
76bc74dc 627 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 628 };
ccc9c027
L		 629 /* nopl (%[re]ax) */
630 static const char alt_3[] =
631 {0x0f,0x1f,0x00};
632 /* nopl 0(%[re]ax) */
633 static const char alt_4[] =
634 {0x0f,0x1f,0x40,0x00};
635 /* nopl 0(%[re]ax,%[re]ax,1) */
636 static const char alt_5[] =
637 {0x0f,0x1f,0x44,0x00,0x00};
638 /* nopw 0(%[re]ax,%[re]ax,1) */
639 static const char alt_6[] =
640 {0x66,0x0f,0x1f,0x44,0x00,0x00};
641 /* nopl 0L(%[re]ax) */
642 static const char alt_7[] =
643 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
644 /* nopl 0L(%[re]ax,%[re]ax,1) */
645 static const char alt_8[] =
646 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
647 /* nopw 0L(%[re]ax,%[re]ax,1) */
648 static const char alt_9[] =
649 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
650 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
651 static const char alt_10[] =
652 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
653 /* data16
654 nopw %cs:0L(%[re]ax,%[re]ax,1) */
655 static const char alt_long_11[] =
656 {0x66,
657 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
658 /* data16
659 data16
660 nopw %cs:0L(%[re]ax,%[re]ax,1) */
661 static const char alt_long_12[] =
662 {0x66,
663 0x66,
664 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
665 /* data16
666 data16
667 data16
668 nopw %cs:0L(%[re]ax,%[re]ax,1) */
669 static const char alt_long_13[] =
670 {0x66,
671 0x66,
672 0x66,
673 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
674 /* data16
675 data16
676 data16
677 data16
678 nopw %cs:0L(%[re]ax,%[re]ax,1) */
679 static const char alt_long_14[] =
680 {0x66,
681 0x66,
682 0x66,
683 0x66,
684 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
685 /* data16
686 data16
687 data16
688 data16
689 data16
690 nopw %cs:0L(%[re]ax,%[re]ax,1) */
691 static const char alt_long_15[] =
692 {0x66,
693 0x66,
694 0x66,
695 0x66,
696 0x66,
697 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
698 /* nopl 0(%[re]ax,%[re]ax,1)
699 nopw 0(%[re]ax,%[re]ax,1) */
700 static const char alt_short_11[] =
701 {0x0f,0x1f,0x44,0x00,0x00,
702 0x66,0x0f,0x1f,0x44,0x00,0x00};
703 /* nopw 0(%[re]ax,%[re]ax,1)
704 nopw 0(%[re]ax,%[re]ax,1) */
705 static const char alt_short_12[] =
706 {0x66,0x0f,0x1f,0x44,0x00,0x00,
707 0x66,0x0f,0x1f,0x44,0x00,0x00};
708 /* nopw 0(%[re]ax,%[re]ax,1)
709 nopl 0L(%[re]ax) */
710 static const char alt_short_13[] =
711 {0x66,0x0f,0x1f,0x44,0x00,0x00,
712 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
713 /* nopl 0L(%[re]ax)
714 nopl 0L(%[re]ax) */
715 static const char alt_short_14[] =
716 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
717 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
718 /* nopl 0L(%[re]ax)
719 nopl 0L(%[re]ax,%[re]ax,1) */
720 static const char alt_short_15[] =
721 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
722 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
723 static const char *const alt_short_patt[] = {
724 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
725 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
726 alt_short_14, alt_short_15
727 };
728 static const char *const alt_long_patt[] = {
729 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
730 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
731 alt_long_14, alt_long_15
732 };
252b5132 733
76bc74dc
L		 734 /* Only align for at least a positive non-zero boundary. */
735 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 736 return;
3e73aa7c 737
ccc9c027
L		 738 /* We need to decide which NOP sequence to use for 32bit and
739 64bit. When -mtune= is used:
4eed87de 740
76bc74dc
L		 741 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
742 PROCESSOR_GENERIC32, f32_patt will be used.
743 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
744 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
745 alt_long_patt will be used.
746 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
747 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 748
76bc74dc
L		 749 When -mtune= isn't used, alt_long_patt will be used if
750 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
751 be used.
ccc9c027
L		 752
753 When -march= or .arch is used, we can't use anything beyond
754 cpu_arch_isa_flags. */
755
756 if (flag_code == CODE_16BIT)
757 {
ccc9c027 758 if (count > 8)
33fef721 759 {
76bc74dc
L		 760 memcpy (fragP->fr_literal + fragP->fr_fix,
761 jump_31, count);
762 /* Adjust jump offset. */
763 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 764 }
76bc74dc
L		 765 else
766 memcpy (fragP->fr_literal + fragP->fr_fix,
767 f16_patt[count - 1], count);
252b5132 768 }
33fef721 769 else
ccc9c027
L		 770 {
771 const char *const *patt = NULL;
772
773 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
774 {
775 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
776 switch (cpu_arch_tune)
777 {
778 case PROCESSOR_UNKNOWN:
779 /* We use cpu_arch_isa_flags to check if we SHOULD
780 optimize for Cpu686. */
40fb9820 781 if (cpu_arch_isa_flags.bitfield.cpui686)
76bc74dc 782 patt = alt_long_patt;
ccc9c027
L		 783 else
784 patt = f32_patt;
785 break;
ccc9c027
L		 786 case PROCESSOR_PENTIUMPRO:
787 case PROCESSOR_PENTIUM4:
788 case PROCESSOR_NOCONA:
ef05d495 789 case PROCESSOR_CORE:
76bc74dc
L		 790 case PROCESSOR_CORE2:
791 case PROCESSOR_GENERIC64:
792 patt = alt_long_patt;
793 break;
ccc9c027
L		 794 case PROCESSOR_K6:
795 case PROCESSOR_ATHLON:
796 case PROCESSOR_K8:
4eed87de 797 case PROCESSOR_AMDFAM10:
ccc9c027
L		 798 patt = alt_short_patt;
799 break;
76bc74dc 800 case PROCESSOR_I386:
ccc9c027
L		 801 case PROCESSOR_I486:
802 case PROCESSOR_PENTIUM:
803 case PROCESSOR_GENERIC32:
804 patt = f32_patt;
805 break;
4eed87de 806 }
ccc9c027
L		 807 }
808 else
809 {
810 switch (cpu_arch_tune)
811 {
812 case PROCESSOR_UNKNOWN:
813 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
814 PROCESSOR_UNKNOWN. */
815 abort ();
816 break;
817
76bc74dc 818 case PROCESSOR_I386:
ccc9c027
L		 819 case PROCESSOR_I486:
820 case PROCESSOR_PENTIUM:
ccc9c027
L		 821 case PROCESSOR_K6:
822 case PROCESSOR_ATHLON:
823 case PROCESSOR_K8:
4eed87de 824 case PROCESSOR_AMDFAM10:
ccc9c027
L		 825 case PROCESSOR_GENERIC32:
826 /* We use cpu_arch_isa_flags to check if we CAN optimize
827 for Cpu686. */
40fb9820 828 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 829 patt = alt_short_patt;
830 else
831 patt = f32_patt;
832 break;
76bc74dc
L		 833 case PROCESSOR_PENTIUMPRO:
834 case PROCESSOR_PENTIUM4:
835 case PROCESSOR_NOCONA:
836 case PROCESSOR_CORE:
ef05d495 837 case PROCESSOR_CORE2:
40fb9820 838 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 839 patt = alt_long_patt;
840 else
841 patt = f32_patt;
842 break;
843 case PROCESSOR_GENERIC64:
76bc74dc 844 patt = alt_long_patt;
ccc9c027 845 break;
4eed87de 846 }
ccc9c027
L		 847 }
848
76bc74dc
L		 849 if (patt == f32_patt)
850 {
851 /* If the padding is less than 15 bytes, we use the normal
852 ones. Otherwise, we use a jump instruction and adjust
853 its offset. */
854 if (count < 15)
855 memcpy (fragP->fr_literal + fragP->fr_fix,
856 patt[count - 1], count);
857 else
858 {
859 memcpy (fragP->fr_literal + fragP->fr_fix,
860 jump_31, count);
861 /* Adjust jump offset. */
862 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
863 }
864 }
865 else
866 {
867 /* Maximum length of an instruction is 15 byte. If the
868 padding is greater than 15 bytes and we don't use jump,
869 we have to break it into smaller pieces. */
870 int padding = count;
871 while (padding > 15)
872 {
873 padding -= 15;
874 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
875 patt [14], 15);
876 }
877
878 if (padding)
879 memcpy (fragP->fr_literal + fragP->fr_fix,
880 patt [padding - 1], padding);
881 }
ccc9c027 882 }
33fef721 883 fragP->fr_var = count;
252b5132
RH		 884}
885
c6fb90c8
L		 886static INLINE int
887uints_all_zero (const unsigned int *x, unsigned int size)
40fb9820 888{
c6fb90c8
L		 889 switch (size)
890 {
891 case 3:
892 if (x[2])
893 return 0;
894 case 2:
895 if (x[1])
896 return 0;
897 case 1:
898 return !x[0];
899 default:
900 abort ();
901 }
40fb9820
L		 902}
903
c6fb90c8
L		 904static INLINE void
905uints_set (unsigned int *x, unsigned int v, unsigned int size)
40fb9820 906{
c6fb90c8
L		 907 switch (size)
908 {
909 case 3:
910 x[2] = v;
911 case 2:
912 x[1] = v;
913 case 1:
914 x[0] = v;
915 break;
916 default:
917 abort ();
918 }
919}
40fb9820 920
c6fb90c8
L		 921static INLINE int
922uints_equal (const unsigned int *x, const unsigned int *y,
923 unsigned int size)
924{
925 switch (size)
926 {
927 case 3:
928 if (x[2] != y [2])
929 return 0;
930 case 2:
931 if (x[1] != y [1])
932 return 0;
933 case 1:
934 return x[0] == y [0];
935 break;
936 default:
937 abort ();
938 }
939}
40fb9820 940
c6fb90c8
L		 941#define UINTS_ALL_ZERO(x) \
942 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
943#define UINTS_SET(x, v) \
944 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
945#define UINTS_CLEAR(x) \
946 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
947#define UINTS_EQUAL(x, y) \
948 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
949
950static INLINE int
951cpu_flags_check_cpu64 (i386_cpu_flags f)
952{
953 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
954 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 955}
956
c6fb90c8 957static INLINE i386_cpu_flags
40fb9820
L		 958cpu_flags_not (i386_cpu_flags x)
959{
c6fb90c8
L		 960 switch (ARRAY_SIZE (x.array))
961 {
962 case 3:
963 x.array [2] = ~x.array [2];
964 case 2:
965 x.array [1] = ~x.array [1];
966 case 1:
967 x.array [0] = ~x.array [0];
968 break;
969 default:
970 abort ();
971 }
40fb9820
L		 972
973#ifdef CpuUnused
974 x.bitfield.unused = 0;
975#endif
976
977 return x;
978}
979
c6fb90c8
L		 980static INLINE i386_cpu_flags
981cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 982{
c6fb90c8
L		 983 switch (ARRAY_SIZE (x.array))
984 {
985 case 3:
986 x.array [2] &= y.array [2];
987 case 2:
988 x.array [1] &= y.array [1];
989 case 1:
990 x.array [0] &= y.array [0];
991 break;
992 default:
993 abort ();
994 }
995 return x;
996}
40fb9820 997
c6fb90c8
L		 998static INLINE i386_cpu_flags
999cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1000{
c6fb90c8 1001 switch (ARRAY_SIZE (x.array))
40fb9820 1002 {
c6fb90c8
L		 1003 case 3:
1004 x.array [2] |= y.array [2];
1005 case 2:
1006 x.array [1] |= y.array [1];
1007 case 1:
1008 x.array [0] |= y.array [0];
40fb9820
L		 1009 break;
1010 default:
1011 abort ();
1012 }
40fb9820
L		 1013 return x;
1014}
1015
1016static int
1017cpu_flags_match (i386_cpu_flags x)
1018{
1019 i386_cpu_flags not = cpu_arch_flags_not;
1020
1021 not.bitfield.cpu64 = 1;
1022 not.bitfield.cpuno64 = 1;
1023
1024 x.bitfield.cpu64 = 0;
1025 x.bitfield.cpuno64 = 0;
1026
c6fb90c8
L		 1027 not = cpu_flags_and (x, not);
1028 return UINTS_ALL_ZERO (not);
40fb9820
L		 1029}
1030
c6fb90c8
L		 1031static INLINE i386_operand_type
1032operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1033{
c6fb90c8
L		 1034 switch (ARRAY_SIZE (x.array))
1035 {
1036 case 3:
1037 x.array [2] &= y.array [2];
1038 case 2:
1039 x.array [1] &= y.array [1];
1040 case 1:
1041 x.array [0] &= y.array [0];
1042 break;
1043 default:
1044 abort ();
1045 }
1046 return x;
40fb9820
L		 1047}
1048
c6fb90c8
L		 1049static INLINE i386_operand_type
1050operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1051{
c6fb90c8 1052 switch (ARRAY_SIZE (x.array))
40fb9820 1053 {
c6fb90c8
L		 1054 case 3:
1055 x.array [2] |= y.array [2];
1056 case 2:
1057 x.array [1] |= y.array [1];
1058 case 1:
1059 x.array [0] |= y.array [0];
40fb9820
L		 1060 break;
1061 default:
1062 abort ();
1063 }
c6fb90c8
L		 1064 return x;
1065}
40fb9820 1066
c6fb90c8
L		 1067static INLINE i386_operand_type
1068operand_type_xor (i386_operand_type x, i386_operand_type y)
1069{
1070 switch (ARRAY_SIZE (x.array))
1071 {
1072 case 3:
1073 x.array [2] ^= y.array [2];
1074 case 2:
1075 x.array [1] ^= y.array [1];
1076 case 1:
1077 x.array [0] ^= y.array [0];
1078 break;
1079 default:
1080 abort ();
1081 }
40fb9820
L		 1082 return x;
1083}
1084
1085static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1086static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1087static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1088static const i386_operand_type reg16_inoutportreg
1089 = OPERAND_TYPE_REG16_INOUTPORTREG;
1090static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1091static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1092static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1093static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1094static const i386_operand_type anydisp
1095 = OPERAND_TYPE_ANYDISP;
1096static const i386_operand_type baseindex = OPERAND_TYPE_BASEINDEX;
1097static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1098static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1099static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1100static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1101static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1102static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1103static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1104static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1105static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1106static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1107
1108enum operand_type
1109{
1110 reg,
40fb9820
L		 1111 imm,
1112 disp,
1113 anymem
1114};
1115
c6fb90c8 1116static INLINE int
40fb9820
L		 1117operand_type_check (i386_operand_type t, enum operand_type c)
1118{
1119 switch (c)
1120 {
1121 case reg:
1122 return (t.bitfield.reg8
1123 || t.bitfield.reg16
1124 || t.bitfield.reg32
1125 || t.bitfield.reg64);
1126
40fb9820
L		 1127 case imm:
1128 return (t.bitfield.imm8
1129 || t.bitfield.imm8s
1130 || t.bitfield.imm16
1131 || t.bitfield.imm32
1132 || t.bitfield.imm32s
1133 || t.bitfield.imm64);
1134
1135 case disp:
1136 return (t.bitfield.disp8
1137 || t.bitfield.disp16
1138 || t.bitfield.disp32
1139 || t.bitfield.disp32s
1140 || t.bitfield.disp64);
1141
1142 case anymem:
1143 return (t.bitfield.disp8
1144 || t.bitfield.disp16
1145 || t.bitfield.disp32
1146 || t.bitfield.disp32s
1147 || t.bitfield.disp64
1148 || t.bitfield.baseindex);
1149
1150 default:
1151 abort ();
1152 }
1153}
1154
c6fb90c8 1155static INLINE int
40fb9820
L		 1156operand_type_match (i386_operand_type overlap,
1157 i386_operand_type given)
1158{
1159 i386_operand_type temp = overlap;
1160
1161 temp.bitfield.jumpabsolute = 0;
c6fb90c8 1162 if (UINTS_ALL_ZERO (temp))
40fb9820
L		 1163 return 0;
1164
1165 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1166 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1167}
1168
1169/* If given types r0 and r1 are registers they must be of the same type
1170 unless the expected operand type register overlap is null.
1171 Note that Acc in a template matches every size of reg. */
1172
c6fb90c8 1173static INLINE int
40fb9820
L		 1174operand_type_register_match (i386_operand_type m0,
1175 i386_operand_type g0,
1176 i386_operand_type t0,
1177 i386_operand_type m1,
1178 i386_operand_type g1,
1179 i386_operand_type t1)
1180{
1181 if (!operand_type_check (g0, reg))
1182 return 1;
1183
1184 if (!operand_type_check (g1, reg))
1185 return 1;
1186
1187 if (g0.bitfield.reg8 == g1.bitfield.reg8
1188 && g0.bitfield.reg16 == g1.bitfield.reg16
1189 && g0.bitfield.reg32 == g1.bitfield.reg32
1190 && g0.bitfield.reg64 == g1.bitfield.reg64)
1191 return 1;
1192
1193 if (m0.bitfield.acc)
1194 {
1195 t0.bitfield.reg8 = 1;
1196 t0.bitfield.reg16 = 1;
1197 t0.bitfield.reg32 = 1;
1198 t0.bitfield.reg64 = 1;
1199 }
1200
1201 if (m1.bitfield.acc)
1202 {
1203 t1.bitfield.reg8 = 1;
1204 t1.bitfield.reg16 = 1;
1205 t1.bitfield.reg32 = 1;
1206 t1.bitfield.reg64 = 1;
1207 }
1208
1209 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1210 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1211 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1212 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1213}
1214
252b5132 1215static INLINE unsigned int
40fb9820 1216mode_from_disp_size (i386_operand_type t)
252b5132 1217{
40fb9820
L		 1218 if (t.bitfield.disp8)
1219 return 1;
1220 else if (t.bitfield.disp16
1221 || t.bitfield.disp32
1222 || t.bitfield.disp32s)
1223 return 2;
1224 else
1225 return 0;
252b5132
RH		 1226}
1227
1228static INLINE int
e3bb37b5 1229fits_in_signed_byte (offsetT num)
252b5132
RH		 1230{
1231 return (num >= -128) && (num <= 127);
47926f60 1232}
252b5132
RH		 1233
1234static INLINE int
e3bb37b5 1235fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1236{
1237 return (num & 0xff) == num;
47926f60 1238}
252b5132
RH		 1239
1240static INLINE int
e3bb37b5 1241fits_in_unsigned_word (offsetT num)
252b5132
RH		 1242{
1243 return (num & 0xffff) == num;
47926f60 1244}
252b5132
RH		 1245
1246static INLINE int
e3bb37b5 1247fits_in_signed_word (offsetT num)
252b5132
RH		 1248{
1249 return (-32768 <= num) && (num <= 32767);
47926f60 1250}
2a962e6d 1251
3e73aa7c 1252static INLINE int
e3bb37b5 1253fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1254{
1255#ifndef BFD64
1256 return 1;
1257#else
1258 return (!(((offsetT) -1 << 31) & num)
1259 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1260#endif
1261} /* fits_in_signed_long() */
2a962e6d 1262
3e73aa7c 1263static INLINE int
e3bb37b5 1264fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1265{
1266#ifndef BFD64
1267 return 1;
1268#else
1269 return (num & (((offsetT) 2 << 31) - 1)) == num;
1270#endif
1271} /* fits_in_unsigned_long() */
252b5132 1272
40fb9820 1273static i386_operand_type
e3bb37b5 1274smallest_imm_type (offsetT num)
252b5132 1275{
40fb9820
L		 1276 i386_operand_type t;
1277
c6fb90c8 1278 UINTS_CLEAR (t);
40fb9820
L		 1279 t.bitfield.imm64 = 1;
1280
1281 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1282 {
1283 /* This code is disabled on the 486 because all the Imm1 forms
1284 in the opcode table are slower on the i486. They're the
1285 versions with the implicitly specified single-position
1286 displacement, which has another syntax if you really want to
1287 use that form. */
40fb9820
L		 1288 t.bitfield.imm1 = 1;
1289 t.bitfield.imm8 = 1;
1290 t.bitfield.imm8s = 1;
1291 t.bitfield.imm16 = 1;
1292 t.bitfield.imm32 = 1;
1293 t.bitfield.imm32s = 1;
1294 }
1295 else if (fits_in_signed_byte (num))
1296 {
1297 t.bitfield.imm8 = 1;
1298 t.bitfield.imm8s = 1;
1299 t.bitfield.imm16 = 1;
1300 t.bitfield.imm32 = 1;
1301 t.bitfield.imm32s = 1;
1302 }
1303 else if (fits_in_unsigned_byte (num))
1304 {
1305 t.bitfield.imm8 = 1;
1306 t.bitfield.imm16 = 1;
1307 t.bitfield.imm32 = 1;
1308 t.bitfield.imm32s = 1;
1309 }
1310 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1311 {
1312 t.bitfield.imm16 = 1;
1313 t.bitfield.imm32 = 1;
1314 t.bitfield.imm32s = 1;
1315 }
1316 else if (fits_in_signed_long (num))
1317 {
1318 t.bitfield.imm32 = 1;
1319 t.bitfield.imm32s = 1;
1320 }
1321 else if (fits_in_unsigned_long (num))
1322 t.bitfield.imm32 = 1;
1323
1324 return t;
47926f60 1325}
252b5132 1326
847f7ad4 1327static offsetT
e3bb37b5 1328offset_in_range (offsetT val, int size)
847f7ad4 1329{
508866be 1330 addressT mask;
ba2adb93 1331
847f7ad4
AM		 1332 switch (size)
1333 {
508866be
L		 1334 case 1: mask = ((addressT) 1 << 8) - 1; break;
1335 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1336 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1337#ifdef BFD64
1338 case 8: mask = ((addressT) 2 << 63) - 1; break;
1339#endif
47926f60 1340 default: abort ();
847f7ad4
AM		 1341 }
1342
ba2adb93 1343 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1344 if (!use_rela_relocations)
1345 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1346 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1347
47926f60 1348 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1349 {
1350 char buf1[40], buf2[40];
1351
1352 sprint_value (buf1, val);
1353 sprint_value (buf2, val & mask);
1354 as_warn (_("%s shortened to %s"), buf1, buf2);
1355 }
1356 return val & mask;
1357}
1358
252b5132
RH		 1359/* Returns 0 if attempting to add a prefix where one from the same
1360 class already exists, 1 if non rep/repne added, 2 if rep/repne
1361 added. */
1362static int
e3bb37b5 1363add_prefix (unsigned int prefix)
252b5132
RH		 1364{
1365 int ret = 1;
b1905489 1366 unsigned int q;
252b5132 1367
29b0f896
AM		 1368 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1369 && flag_code == CODE_64BIT)
b1905489 1370 {
161a04f6
L		 1371 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1372 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1373 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1374 ret = 0;
1375 q = REX_PREFIX;
1376 }
3e73aa7c 1377 else
b1905489
JB		 1378 {
1379 switch (prefix)
1380 {
1381 default:
1382 abort ();
1383
1384 case CS_PREFIX_OPCODE:
1385 case DS_PREFIX_OPCODE:
1386 case ES_PREFIX_OPCODE:
1387 case FS_PREFIX_OPCODE:
1388 case GS_PREFIX_OPCODE:
1389 case SS_PREFIX_OPCODE:
1390 q = SEG_PREFIX;
1391 break;
1392
1393 case REPNE_PREFIX_OPCODE:
1394 case REPE_PREFIX_OPCODE:
1395 ret = 2;
1396 /* fall thru */
1397 case LOCK_PREFIX_OPCODE:
1398 q = LOCKREP_PREFIX;
1399 break;
1400
1401 case FWAIT_OPCODE:
1402 q = WAIT_PREFIX;
1403 break;
1404
1405 case ADDR_PREFIX_OPCODE:
1406 q = ADDR_PREFIX;
1407 break;
1408
1409 case DATA_PREFIX_OPCODE:
1410 q = DATA_PREFIX;
1411 break;
1412 }
1413 if (i.prefix[q] != 0)
1414 ret = 0;
1415 }
252b5132 1416
b1905489 1417 if (ret)
252b5132 1418 {
b1905489
JB		 1419 if (!i.prefix[q])
1420 ++i.prefixes;
1421 i.prefix[q] |= prefix;
252b5132 1422 }
b1905489
JB		 1423 else
1424 as_bad (_("same type of prefix used twice"));
252b5132 1425
252b5132
RH		 1426 return ret;
1427}
1428
1429static void
e3bb37b5 1430set_code_flag (int value)
eecb386c 1431{
3e73aa7c 1432 flag_code = value;
40fb9820
L		 1433 if (flag_code == CODE_64BIT)
1434 {
1435 cpu_arch_flags.bitfield.cpu64 = 1;
1436 cpu_arch_flags.bitfield.cpuno64 = 0;
1437 cpu_arch_flags_not.bitfield.cpu64 = 0;
1438 cpu_arch_flags_not.bitfield.cpuno64 = 1;
1439 }
1440 else
1441 {
1442 cpu_arch_flags.bitfield.cpu64 = 0;
1443 cpu_arch_flags.bitfield.cpuno64 = 1;
1444 cpu_arch_flags_not.bitfield.cpu64 = 1;
1445 cpu_arch_flags_not.bitfield.cpuno64 = 0;
1446 }
1447 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1448 {
1449 as_bad (_("64bit mode not supported on this CPU."));
1450 }
40fb9820 1451 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1452 {
1453 as_bad (_("32bit mode not supported on this CPU."));
1454 }
eecb386c
AM		 1455 stackop_size = '\0';
1456}
1457
1458static void
e3bb37b5 1459set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1460{
3e73aa7c 1461 flag_code = new_code_flag;
40fb9820
L		 1462 if (flag_code != CODE_16BIT)
1463 abort ();
1464 cpu_arch_flags.bitfield.cpu64 = 0;
1465 cpu_arch_flags.bitfield.cpuno64 = 1;
1466 cpu_arch_flags_not.bitfield.cpu64 = 1;
1467 cpu_arch_flags_not.bitfield.cpuno64 = 0;
9306ca4a 1468 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1469}
1470
1471static void
e3bb37b5 1472set_intel_syntax (int syntax_flag)
252b5132
RH		 1473{
1474 /* Find out if register prefixing is specified. */
1475 int ask_naked_reg = 0;
1476
1477 SKIP_WHITESPACE ();
29b0f896 1478 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1479 {
1480 char *string = input_line_pointer;
1481 int e = get_symbol_end ();
1482
47926f60 1483 if (strcmp (string, "prefix") == 0)
252b5132 1484 ask_naked_reg = 1;
47926f60 1485 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1486 ask_naked_reg = -1;
1487 else
d0b47220 1488 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1489 *input_line_pointer = e;
1490 }
1491 demand_empty_rest_of_line ();
c3332e24 1492
252b5132
RH		 1493 intel_syntax = syntax_flag;
1494
1495 if (ask_naked_reg == 0)
f86103b7
AM		 1496 allow_naked_reg = (intel_syntax
1497 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1498 else
1499 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1500
e4a3b5a4 1501 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1502 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1503 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1504}
1505
e413e4e9 1506static void
e3bb37b5 1507set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1508{
47926f60 1509 SKIP_WHITESPACE ();
e413e4e9 1510
29b0f896 1511 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1512 {
1513 char *string = input_line_pointer;
1514 int e = get_symbol_end ();
9103f4f4 1515 unsigned int i;
40fb9820 1516 i386_cpu_flags flags;
e413e4e9 1517
9103f4f4 1518 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1519 {
1520 if (strcmp (string, cpu_arch[i].name) == 0)
1521 {
5c6af06e
JB		 1522 if (*string != '.')
1523 {
1524 cpu_arch_name = cpu_arch[i].name;
1525 cpu_sub_arch_name = NULL;
40fb9820
L		 1526 cpu_arch_flags = cpu_arch[i].flags;
1527 if (flag_code == CODE_64BIT)
1528 {
1529 cpu_arch_flags.bitfield.cpu64 = 1;
1530 cpu_arch_flags.bitfield.cpuno64 = 0;
1531 }
1532 else
1533 {
1534 cpu_arch_flags.bitfield.cpu64 = 0;
1535 cpu_arch_flags.bitfield.cpuno64 = 1;
1536 }
1537 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
ccc9c027 1538 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1539 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1540 if (!cpu_arch_tune_set)
1541 {
1542 cpu_arch_tune = cpu_arch_isa;
1543 cpu_arch_tune_flags = cpu_arch_isa_flags;
1544 }
5c6af06e
JB		 1545 break;
1546 }
40fb9820 1547
c6fb90c8
L		 1548 flags = cpu_flags_or (cpu_arch_flags,
1549 cpu_arch[i].flags);
1550 if (!UINTS_EQUAL (flags, cpu_arch_flags))
5c6af06e
JB		 1551 {
1552 cpu_sub_arch_name = cpu_arch[i].name;
40fb9820
L		 1553 cpu_arch_flags = flags;
1554 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
5c6af06e
JB		 1555 }
1556 *input_line_pointer = e;
1557 demand_empty_rest_of_line ();
1558 return;
e413e4e9
AM		 1559 }
1560 }
9103f4f4 1561 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1562 as_bad (_("no such architecture: `%s'"), string);
1563
1564 *input_line_pointer = e;
1565 }
1566 else
1567 as_bad (_("missing cpu architecture"));
1568
fddf5b5b
AM		 1569 no_cond_jump_promotion = 0;
1570 if (*input_line_pointer == ','
29b0f896 1571 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1572 {
1573 char *string = ++input_line_pointer;
1574 int e = get_symbol_end ();
1575
1576 if (strcmp (string, "nojumps") == 0)
1577 no_cond_jump_promotion = 1;
1578 else if (strcmp (string, "jumps") == 0)
1579 ;
1580 else
1581 as_bad (_("no such architecture modifier: `%s'"), string);
1582
1583 *input_line_pointer = e;
1584 }
1585
e413e4e9
AM		 1586 demand_empty_rest_of_line ();
1587}
1588
b9d79e03
JH		 1589unsigned long
1590i386_mach ()
1591{
1592 if (!strcmp (default_arch, "x86_64"))
1593 return bfd_mach_x86_64;
1594 else if (!strcmp (default_arch, "i386"))
1595 return bfd_mach_i386_i386;
1596 else
1597 as_fatal (_("Unknown architecture"));
1598}
b9d79e03 1599\f
252b5132
RH		 1600void
1601md_begin ()
1602{
1603 const char *hash_err;
1604
40fb9820
L		 1605 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
1606
47926f60 1607 /* Initialize op_hash hash table. */
252b5132
RH		 1608 op_hash = hash_new ();
1609
1610 {
29b0f896
AM		 1611 const template *optab;
1612 templates *core_optab;
252b5132 1613
47926f60
KH		 1614 /* Setup for loop. */
1615 optab = i386_optab;
252b5132
RH		 1616 core_optab = (templates *) xmalloc (sizeof (templates));
1617 core_optab->start = optab;
1618
1619 while (1)
1620 {
1621 ++optab;
1622 if (optab->name == NULL
1623 || strcmp (optab->name, (optab - 1)->name) != 0)
1624 {
1625 /* different name --> ship out current template list;
47926f60 1626 add to hash table; & begin anew. */
252b5132
RH		 1627 core_optab->end = optab;
1628 hash_err = hash_insert (op_hash,
1629 (optab - 1)->name,
1630 (PTR) core_optab);
1631 if (hash_err)
1632 {
252b5132
RH		 1633 as_fatal (_("Internal Error: Can't hash %s: %s"),
1634 (optab - 1)->name,
1635 hash_err);
1636 }
1637 if (optab->name == NULL)
1638 break;
1639 core_optab = (templates *) xmalloc (sizeof (templates));
1640 core_optab->start = optab;
1641 }
1642 }
1643 }
1644
47926f60 1645 /* Initialize reg_hash hash table. */
252b5132
RH		 1646 reg_hash = hash_new ();
1647 {
29b0f896 1648 const reg_entry *regtab;
c3fe08fa 1649 unsigned int regtab_size = i386_regtab_size;
252b5132 1650
c3fe08fa 1651 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1652 {
1653 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1654 if (hash_err)
3e73aa7c
JH		 1655 as_fatal (_("Internal Error: Can't hash %s: %s"),
1656 regtab->reg_name,
1657 hash_err);
252b5132
RH		 1658 }
1659 }
1660
47926f60 1661 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1662 {
29b0f896
AM		 1663 int c;
1664 char *p;
252b5132
RH		 1665
1666 for (c = 0; c < 256; c++)
1667 {
3882b010 1668 if (ISDIGIT (c))
252b5132
RH		 1669 {
1670 digit_chars[c] = c;
1671 mnemonic_chars[c] = c;
1672 register_chars[c] = c;
1673 operand_chars[c] = c;
1674 }
3882b010 1675 else if (ISLOWER (c))
252b5132
RH		 1676 {
1677 mnemonic_chars[c] = c;
1678 register_chars[c] = c;
1679 operand_chars[c] = c;
1680 }
3882b010 1681 else if (ISUPPER (c))
252b5132 1682 {
3882b010 1683 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1684 register_chars[c] = mnemonic_chars[c];
1685 operand_chars[c] = c;
1686 }
1687
3882b010 1688 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1689 identifier_chars[c] = c;
1690 else if (c >= 128)
1691 {
1692 identifier_chars[c] = c;
1693 operand_chars[c] = c;
1694 }
1695 }
1696
1697#ifdef LEX_AT
1698 identifier_chars['@'] = '@';
32137342
NC		 1699#endif
1700#ifdef LEX_QM
1701 identifier_chars['?'] = '?';
1702 operand_chars['?'] = '?';
252b5132 1703#endif
252b5132 1704 digit_chars['-'] = '-';
791fe849 1705 mnemonic_chars['-'] = '-';
0003779b 1706 mnemonic_chars['.'] = '.';
252b5132
RH		 1707 identifier_chars['_'] = '_';
1708 identifier_chars['.'] = '.';
1709
1710 for (p = operand_special_chars; *p != '\0'; p++)
1711 operand_chars[(unsigned char) *p] = *p;
1712 }
1713
1714#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1715 if (IS_ELF)
252b5132
RH		 1716 {
1717 record_alignment (text_section, 2);
1718 record_alignment (data_section, 2);
1719 record_alignment (bss_section, 2);
1720 }
1721#endif
a4447b93
RH		 1722
1723 if (flag_code == CODE_64BIT)
1724 {
1725 x86_dwarf2_return_column = 16;
1726 x86_cie_data_alignment = -8;
1727 }
1728 else
1729 {
1730 x86_dwarf2_return_column = 8;
1731 x86_cie_data_alignment = -4;
1732 }
252b5132
RH		 1733}
1734
1735void
e3bb37b5 1736i386_print_statistics (FILE *file)
252b5132
RH		 1737{
1738 hash_print_statistics (file, "i386 opcode", op_hash);
1739 hash_print_statistics (file, "i386 register", reg_hash);
1740}
1741\f
252b5132
RH		 1742#ifdef DEBUG386
1743
ce8a8b2f 1744/* Debugging routines for md_assemble. */
e3bb37b5 1745static void pte (template *);
40fb9820 1746static void pt (i386_operand_type);
e3bb37b5
L		 1747static void pe (expressionS *);
1748static void ps (symbolS *);
252b5132
RH		 1749
1750static void
e3bb37b5 1751pi (char *line, i386_insn *x)
252b5132 1752{
09f131f2 1753 unsigned int i;
252b5132
RH		 1754
1755 fprintf (stdout, "%s: template ", line);
1756 pte (&x->tm);
09f131f2
JH		 1757 fprintf (stdout, " address: base %s index %s scale %x\n",
1758 x->base_reg ? x->base_reg->reg_name : "none",
1759 x->index_reg ? x->index_reg->reg_name : "none",
1760 x->log2_scale_factor);
1761 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1762 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1763 fprintf (stdout, " sib: base %x index %x scale %x\n",
1764 x->sib.base, x->sib.index, x->sib.scale);
1765 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 1766 (x->rex & REX_W) != 0,
1767 (x->rex & REX_R) != 0,
1768 (x->rex & REX_X) != 0,
1769 (x->rex & REX_B) != 0);
252b5132
RH		 1770 for (i = 0; i < x->operands; i++)
1771 {
1772 fprintf (stdout, " #%d: ", i + 1);
1773 pt (x->types[i]);
1774 fprintf (stdout, "\n");
40fb9820
L		 1775 if (x->types[i].bitfield.reg8
1776 || x->types[i].bitfield.reg16
1777 || x->types[i].bitfield.reg32
1778 || x->types[i].bitfield.reg64
1779 || x->types[i].bitfield.regmmx
1780 || x->types[i].bitfield.regxmm
1781 || x->types[i].bitfield.sreg2
1782 || x->types[i].bitfield.sreg3
1783 || x->types[i].bitfield.control
1784 || x->types[i].bitfield.debug
1785 || x->types[i].bitfield.test)
520dc8e8 1786 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 1787 if (operand_type_check (x->types[i], imm))
520dc8e8 1788 pe (x->op[i].imms);
40fb9820 1789 if (operand_type_check (x->types[i], disp))
520dc8e8 1790 pe (x->op[i].disps);
252b5132
RH		 1791 }
1792}
1793
1794static void
e3bb37b5 1795pte (template *t)
252b5132 1796{
09f131f2 1797 unsigned int i;
252b5132 1798 fprintf (stdout, " %d operands ", t->operands);
47926f60 1799 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1800 if (t->extension_opcode != None)
1801 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 1802 if (t->opcode_modifier.d)
252b5132 1803 fprintf (stdout, "D");
40fb9820 1804 if (t->opcode_modifier.w)
252b5132
RH		 1805 fprintf (stdout, "W");
1806 fprintf (stdout, "\n");
1807 for (i = 0; i < t->operands; i++)
1808 {
1809 fprintf (stdout, " #%d type ", i + 1);
1810 pt (t->operand_types[i]);
1811 fprintf (stdout, "\n");
1812 }
1813}
1814
1815static void
e3bb37b5 1816pe (expressionS *e)
252b5132 1817{
24eab124 1818 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1819 fprintf (stdout, " add_number %ld (%lx)\n",
1820 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1821 if (e->X_add_symbol)
1822 {
1823 fprintf (stdout, " add_symbol ");
1824 ps (e->X_add_symbol);
1825 fprintf (stdout, "\n");
1826 }
1827 if (e->X_op_symbol)
1828 {
1829 fprintf (stdout, " op_symbol ");
1830 ps (e->X_op_symbol);
1831 fprintf (stdout, "\n");
1832 }
1833}
1834
1835static void
e3bb37b5 1836ps (symbolS *s)
252b5132
RH		 1837{
1838 fprintf (stdout, "%s type %s%s",
1839 S_GET_NAME (s),
1840 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1841 segment_name (S_GET_SEGMENT (s)));
1842}
1843
7b81dfbb 1844static struct type_name
252b5132 1845 {
40fb9820
L		 1846 i386_operand_type mask;
1847 const char *name;
252b5132 1848 }
7b81dfbb 1849const type_names[] =
252b5132 1850{
40fb9820
L		 1851 { OPERAND_TYPE_REG8, "r8" },
1852 { OPERAND_TYPE_REG16, "r16" },
1853 { OPERAND_TYPE_REG32, "r32" },
1854 { OPERAND_TYPE_REG64, "r64" },
1855 { OPERAND_TYPE_IMM8, "i8" },
1856 { OPERAND_TYPE_IMM8, "i8s" },
1857 { OPERAND_TYPE_IMM16, "i16" },
1858 { OPERAND_TYPE_IMM32, "i32" },
1859 { OPERAND_TYPE_IMM32S, "i32s" },
1860 { OPERAND_TYPE_IMM64, "i64" },
1861 { OPERAND_TYPE_IMM1, "i1" },
1862 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
1863 { OPERAND_TYPE_DISP8, "d8" },
1864 { OPERAND_TYPE_DISP16, "d16" },
1865 { OPERAND_TYPE_DISP32, "d32" },
1866 { OPERAND_TYPE_DISP32S, "d32s" },
1867 { OPERAND_TYPE_DISP64, "d64" },
1868 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
1869 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
1870 { OPERAND_TYPE_CONTROL, "control reg" },
1871 { OPERAND_TYPE_TEST, "test reg" },
1872 { OPERAND_TYPE_DEBUG, "debug reg" },
1873 { OPERAND_TYPE_FLOATREG, "FReg" },
1874 { OPERAND_TYPE_FLOATACC, "FAcc" },
1875 { OPERAND_TYPE_SREG2, "SReg2" },
1876 { OPERAND_TYPE_SREG3, "SReg3" },
1877 { OPERAND_TYPE_ACC, "Acc" },
1878 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
1879 { OPERAND_TYPE_REGMMX, "rMMX" },
1880 { OPERAND_TYPE_REGXMM, "rXMM" },
1881 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 1882};
1883
1884static void
40fb9820 1885pt (i386_operand_type t)
252b5132 1886{
40fb9820 1887 unsigned int j;
c6fb90c8 1888 i386_operand_type a;
252b5132 1889
40fb9820 1890 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 1891 {
1892 a = operand_type_and (t, type_names[j].mask);
1893 if (!UINTS_ALL_ZERO (a))
1894 fprintf (stdout, "%s, ", type_names[j].name);
1895 }
252b5132
RH		 1896 fflush (stdout);
1897}
1898
1899#endif /* DEBUG386 */
1900\f
252b5132 1901static bfd_reloc_code_real_type
3956db08 1902reloc (unsigned int size,
64e74474
AM		 1903 int pcrel,
1904 int sign,
1905 bfd_reloc_code_real_type other)
252b5132 1906{
47926f60 1907 if (other != NO_RELOC)
3956db08
JB		 1908 {
1909 reloc_howto_type *reloc;
1910
1911 if (size == 8)
1912 switch (other)
1913 {
64e74474
AM		 1914 case BFD_RELOC_X86_64_GOT32:
1915 return BFD_RELOC_X86_64_GOT64;
1916 break;
1917 case BFD_RELOC_X86_64_PLTOFF64:
1918 return BFD_RELOC_X86_64_PLTOFF64;
1919 break;
1920 case BFD_RELOC_X86_64_GOTPC32:
1921 other = BFD_RELOC_X86_64_GOTPC64;
1922 break;
1923 case BFD_RELOC_X86_64_GOTPCREL:
1924 other = BFD_RELOC_X86_64_GOTPCREL64;
1925 break;
1926 case BFD_RELOC_X86_64_TPOFF32:
1927 other = BFD_RELOC_X86_64_TPOFF64;
1928 break;
1929 case BFD_RELOC_X86_64_DTPOFF32:
1930 other = BFD_RELOC_X86_64_DTPOFF64;
1931 break;
1932 default:
1933 break;
3956db08 1934 }
e05278af
JB		 1935
1936 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1937 if (size == 4 && flag_code != CODE_64BIT)
1938 sign = -1;
1939
3956db08
JB		 1940 reloc = bfd_reloc_type_lookup (stdoutput, other);
1941 if (!reloc)
1942 as_bad (_("unknown relocation (%u)"), other);
1943 else if (size != bfd_get_reloc_size (reloc))
1944 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1945 bfd_get_reloc_size (reloc),
1946 size);
1947 else if (pcrel && !reloc->pc_relative)
1948 as_bad (_("non-pc-relative relocation for pc-relative field"));
1949 else if ((reloc->complain_on_overflow == complain_overflow_signed
1950 && !sign)
1951 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1952 && sign > 0))
3956db08
JB		 1953 as_bad (_("relocated field and relocation type differ in signedness"));
1954 else
1955 return other;
1956 return NO_RELOC;
1957 }
252b5132
RH		 1958
1959 if (pcrel)
1960 {
3e73aa7c 1961 if (!sign)
3956db08 1962 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1963 switch (size)
1964 {
1965 case 1: return BFD_RELOC_8_PCREL;
1966 case 2: return BFD_RELOC_16_PCREL;
1967 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1968 case 8: return BFD_RELOC_64_PCREL;
252b5132 1969 }
3956db08 1970 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1971 }
1972 else
1973 {
3956db08 1974 if (sign > 0)
e5cb08ac 1975 switch (size)
3e73aa7c
JH		 1976 {
1977 case 4: return BFD_RELOC_X86_64_32S;
1978 }
1979 else
1980 switch (size)
1981 {
1982 case 1: return BFD_RELOC_8;
1983 case 2: return BFD_RELOC_16;
1984 case 4: return BFD_RELOC_32;
1985 case 8: return BFD_RELOC_64;
1986 }
3956db08
JB		 1987 as_bad (_("cannot do %s %u byte relocation"),
1988 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1989 }
1990
bfb32b52 1991 abort ();
252b5132
RH		 1992 return BFD_RELOC_NONE;
1993}
1994
47926f60
KH		 1995/* Here we decide which fixups can be adjusted to make them relative to
1996 the beginning of the section instead of the symbol. Basically we need
1997 to make sure that the dynamic relocations are done correctly, so in
1998 some cases we force the original symbol to be used. */
1999
252b5132 2000int
e3bb37b5 2001tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2002{
6d249963 2003#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2004 if (!IS_ELF)
31312f95
AM		 2005 return 1;
2006
a161fe53
AM		 2007 /* Don't adjust pc-relative references to merge sections in 64-bit
2008 mode. */
2009 if (use_rela_relocations
2010 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2011 && fixP->fx_pcrel)
252b5132 2012 return 0;
31312f95 2013
8d01d9a9
AJ		 2014 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2015 and changed later by validate_fix. */
2016 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2017 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2018 return 0;
2019
ce8a8b2f 2020 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2021 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2022 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2023 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2024 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2025 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2026 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2027 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2028 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2029 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2030 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2031 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2032 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2033 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2034 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2035 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2036 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2037 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2038 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2039 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2040 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2041 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2042 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2043 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2044 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2045 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2046 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2047 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2048 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2049 return 0;
31312f95 2050#endif
252b5132
RH		 2051 return 1;
2052}
252b5132 2053
b4cac588 2054static int
e3bb37b5 2055intel_float_operand (const char *mnemonic)
252b5132 2056{
9306ca4a
JB		 2057 /* Note that the value returned is meaningful only for opcodes with (memory)
2058 operands, hence the code here is free to improperly handle opcodes that
2059 have no operands (for better performance and smaller code). */
2060
2061 if (mnemonic[0] != 'f')
2062 return 0; /* non-math */
2063
2064 switch (mnemonic[1])
2065 {
2066 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2067 the fs segment override prefix not currently handled because no
2068 call path can make opcodes without operands get here */
2069 case 'i':
2070 return 2 /* integer op */;
2071 case 'l':
2072 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2073 return 3; /* fldcw/fldenv */
2074 break;
2075 case 'n':
2076 if (mnemonic[2] != 'o' /* fnop */)
2077 return 3; /* non-waiting control op */
2078 break;
2079 case 'r':
2080 if (mnemonic[2] == 's')
2081 return 3; /* frstor/frstpm */
2082 break;
2083 case 's':
2084 if (mnemonic[2] == 'a')
2085 return 3; /* fsave */
2086 if (mnemonic[2] == 't')
2087 {
2088 switch (mnemonic[3])
2089 {
2090 case 'c': /* fstcw */
2091 case 'd': /* fstdw */
2092 case 'e': /* fstenv */
2093 case 's': /* fsts[gw] */
2094 return 3;
2095 }
2096 }
2097 break;
2098 case 'x':
2099 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2100 return 0; /* fxsave/fxrstor are not really math ops */
2101 break;
2102 }
252b5132 2103
9306ca4a 2104 return 1;
252b5132
RH		 2105}
2106
2107/* This is the guts of the machine-dependent assembler. LINE points to a
2108 machine dependent instruction. This function is supposed to emit
2109 the frags/bytes it assembles to. */
2110
2111void
2112md_assemble (line)
2113 char *line;
2114{
40fb9820 2115 unsigned int j;
252b5132
RH		 2116 char mnemonic[MAX_MNEM_SIZE];
2117
47926f60 2118 /* Initialize globals. */
252b5132
RH		 2119 memset (&i, '\0', sizeof (i));
2120 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2121 i.reloc[j] = NO_RELOC;
252b5132
RH		 2122 memset (disp_expressions, '\0', sizeof (disp_expressions));
2123 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2124 save_stack_p = save_stack;
252b5132
RH		 2125
2126 /* First parse an instruction mnemonic & call i386_operand for the operands.
2127 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2128 start of a (possibly prefixed) mnemonic. */
252b5132 2129
29b0f896
AM		 2130 line = parse_insn (line, mnemonic);
2131 if (line == NULL)
2132 return;
252b5132 2133
29b0f896
AM		 2134 line = parse_operands (line, mnemonic);
2135 if (line == NULL)
2136 return;
252b5132 2137
29b0f896
AM		 2138 /* Now we've parsed the mnemonic into a set of templates, and have the
2139 operands at hand. */
2140
2141 /* All intel opcodes have reversed operands except for "bound" and
2142 "enter". We also don't reverse intersegment "jmp" and "call"
2143 instructions with 2 immediate operands so that the immediate segment
050dfa73 2144 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2145 if (intel_syntax
2146 && i.operands > 1
29b0f896 2147 && (strcmp (mnemonic, "bound") != 0)
30123838 2148 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2149 && !(operand_type_check (i.types[0], imm)
2150 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2151 swap_operands ();
2152
ec56d5c0
JB		 2153 /* The order of the immediates should be reversed
2154 for 2 immediates extrq and insertq instructions */
2155 if (i.imm_operands == 2
2156 && (strcmp (mnemonic, "extrq") == 0
2157 || strcmp (mnemonic, "insertq") == 0))
2158 swap_2_operands (0, 1);
2159
29b0f896
AM		 2160 if (i.imm_operands)
2161 optimize_imm ();
2162
b300c311
L		 2163 /* Don't optimize displacement for movabs since it only takes 64bit
2164 displacement. */
2165 if (i.disp_operands
2166 && (flag_code != CODE_64BIT
2167 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2168 optimize_disp ();
2169
2170 /* Next, we find a template that matches the given insn,
2171 making sure the overlap of the given operands types is consistent
2172 with the template operand types. */
252b5132 2173
29b0f896
AM		 2174 if (!match_template ())
2175 return;
252b5132 2176
cd61ebfe
AM		 2177 if (intel_syntax)
2178 {
2179 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
2180 if (SYSV386_COMPAT
2181 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
8a2ed489 2182 i.tm.base_opcode ^= Opcode_FloatR;
cd61ebfe
AM		 2183
2184 /* Zap movzx and movsx suffix. The suffix may have been set from
2185 "word ptr" or "byte ptr" on the source operand, but we'll use
2186 the suffix later to choose the destination register. */
2187 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 2188 {
2189 if (i.reg_operands < 2
2190 && !i.suffix
40fb9820
L		 2191 && (!i.tm.opcode_modifier.no_bsuf
2192 || !i.tm.opcode_modifier.no_wsuf
2193 || !i.tm.opcode_modifier.no_lsuf
2194 || !i.tm.opcode_modifier.no_ssuf
2195 || !i.tm.opcode_modifier.no_xsuf
2196 || !i.tm.opcode_modifier.no_qsuf))
9306ca4a
JB		 2197 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2198
2199 i.suffix = 0;
2200 }
cd61ebfe 2201 }
24eab124 2202
40fb9820 2203 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2204 if (!add_prefix (FWAIT_OPCODE))
2205 return;
252b5132 2206
29b0f896 2207 /* Check string instruction segment overrides. */
40fb9820 2208 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2209 {
2210 if (!check_string ())
5dd0794d 2211 return;
29b0f896 2212 }
5dd0794d 2213
29b0f896
AM		 2214 if (!process_suffix ())
2215 return;
e413e4e9 2216
29b0f896
AM		 2217 /* Make still unresolved immediate matches conform to size of immediate
2218 given in i.suffix. */
2219 if (!finalize_imm ())
2220 return;
252b5132 2221
40fb9820 2222 if (i.types[0].bitfield.imm1)
29b0f896 2223 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2224
40fb9820 2225 for (j = 0; j < 3; j++)
c6fb90c8
L		 2226 if (i.types[j].bitfield.inoutportreg
2227 || i.types[j].bitfield.shiftcount
2228 || i.types[j].bitfield.acc
2229 || i.types[j].bitfield.floatacc)
40fb9820
L		 2230 i.reg_operands--;
2231
2232 if (i.tm.opcode_modifier.immext)
29b0f896 2233 {
02fc3089
L		 2234 expressionS *exp;
2235
40fb9820 2236 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
ca164297 2237 {
b7d9ef37 2238 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 2239 operands with an opcode suffix which is coded in the same
2240 place as an 8-bit immediate field would be. Here we check
2241 those operands and remove them afterwards. */
2242 unsigned int x;
2243
a4622f40 2244 for (x = 0; x < i.operands; x++)
ca164297 2245 if (i.op[x].regs->reg_num != x)
a540244d
L		 2246 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2247 register_prefix,
2248 i.op[x].regs->reg_name,
2249 x + 1,
2250 i.tm.name);
ca164297
L		 2251 i.operands = 0;
2252 }
2253
29b0f896
AM		 2254 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2255 opcode suffix which is coded in the same place as an 8-bit
2256 immediate field would be. Here we fake an 8-bit immediate
2257 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 2258
29b0f896 2259 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 2260
29b0f896
AM		 2261 exp = &im_expressions[i.imm_operands++];
2262 i.op[i.operands].imms = exp;
c6fb90c8 2263 UINTS_CLEAR (i.types[i.operands]);
40fb9820
L		 2264 i.types[i.operands].bitfield.imm8 = 1;
2265 i.operands++;
29b0f896
AM		 2266 exp->X_op = O_constant;
2267 exp->X_add_number = i.tm.extension_opcode;
2268 i.tm.extension_opcode = None;
2269 }
252b5132 2270
29b0f896
AM		 2271 /* For insns with operands there are more diddles to do to the opcode. */
2272 if (i.operands)
2273 {
2274 if (!process_operands ())
2275 return;
2276 }
40fb9820 2277 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2278 {
2279 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2280 as_warn (_("translating to `%sp'"), i.tm.name);
2281 }
252b5132 2282
29b0f896
AM		 2283 /* Handle conversion of 'int $3' --> special int3 insn. */
2284 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2285 {
2286 i.tm.base_opcode = INT3_OPCODE;
2287 i.imm_operands = 0;
2288 }
252b5132 2289
40fb9820
L		 2290 if ((i.tm.opcode_modifier.jump
2291 || i.tm.opcode_modifier.jumpbyte
2292 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2293 && i.op[0].disps->X_op == O_constant)
2294 {
2295 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2296 the absolute address given by the constant. Since ix86 jumps and
2297 calls are pc relative, we need to generate a reloc. */
2298 i.op[0].disps->X_add_symbol = &abs_symbol;
2299 i.op[0].disps->X_op = O_symbol;
2300 }
252b5132 2301
40fb9820 2302 if (i.tm.opcode_modifier.rex64)
161a04f6 2303 i.rex |= REX_W;
252b5132 2304
29b0f896
AM		 2305 /* For 8 bit registers we need an empty rex prefix. Also if the
2306 instruction already has a prefix, we need to convert old
2307 registers to new ones. */
773f551c 2308
40fb9820 2309 if ((i.types[0].bitfield.reg8
29b0f896 2310 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2311 || (i.types[1].bitfield.reg8
29b0f896 2312 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2313 || ((i.types[0].bitfield.reg8
2314 || i.types[1].bitfield.reg8)
29b0f896
AM		 2315 && i.rex != 0))
2316 {
2317 int x;
726c5dcd 2318
29b0f896
AM		 2319 i.rex |= REX_OPCODE;
2320 for (x = 0; x < 2; x++)
2321 {
2322 /* Look for 8 bit operand that uses old registers. */
40fb9820 2323 if (i.types[x].bitfield.reg8
29b0f896 2324 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2325 {
29b0f896
AM		 2326 /* In case it is "hi" register, give up. */
2327 if (i.op[x].regs->reg_num > 3)
a540244d 2328 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2329 "instruction requiring REX prefix."),
a540244d 2330 register_prefix, i.op[x].regs->reg_name);
773f551c 2331
29b0f896
AM		 2332 /* Otherwise it is equivalent to the extended register.
2333 Since the encoding doesn't change this is merely
2334 cosmetic cleanup for debug output. */
2335
2336 i.op[x].regs = i.op[x].regs + 8;
773f551c 2337 }
29b0f896
AM		 2338 }
2339 }
773f551c 2340
29b0f896
AM		 2341 if (i.rex != 0)
2342 add_prefix (REX_OPCODE | i.rex);
2343
2344 /* We are ready to output the insn. */
2345 output_insn ();
2346}
2347
2348static char *
e3bb37b5 2349parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2350{
2351 char *l = line;
2352 char *token_start = l;
2353 char *mnem_p;
5c6af06e
JB		 2354 int supported;
2355 const template *t;
29b0f896
AM		 2356
2357 /* Non-zero if we found a prefix only acceptable with string insns. */
2358 const char *expecting_string_instruction = NULL;
45288df1 2359
29b0f896
AM		 2360 while (1)
2361 {
2362 mnem_p = mnemonic;
2363 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2364 {
2365 mnem_p++;
2366 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2367 {
29b0f896
AM		 2368 as_bad (_("no such instruction: `%s'"), token_start);
2369 return NULL;
2370 }
2371 l++;
2372 }
2373 if (!is_space_char (*l)
2374 && *l != END_OF_INSN
e44823cf
JB		 2375 && (intel_syntax
2376 || (*l != PREFIX_SEPARATOR
2377 && *l != ',')))
29b0f896
AM		 2378 {
2379 as_bad (_("invalid character %s in mnemonic"),
2380 output_invalid (*l));
2381 return NULL;
2382 }
2383 if (token_start == l)
2384 {
e44823cf 2385 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2386 as_bad (_("expecting prefix; got nothing"));
2387 else
2388 as_bad (_("expecting mnemonic; got nothing"));
2389 return NULL;
2390 }
45288df1 2391
29b0f896
AM		 2392 /* Look up instruction (or prefix) via hash table. */
2393 current_templates = hash_find (op_hash, mnemonic);
47926f60 2394
29b0f896
AM		 2395 if (*l != END_OF_INSN
2396 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2397 && current_templates
40fb9820 2398 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2399 {
c6fb90c8 2400 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2401 {
2402 as_bad ((flag_code != CODE_64BIT
2403 ? _("`%s' is only supported in 64-bit mode")
2404 : _("`%s' is not supported in 64-bit mode")),
2405 current_templates->start->name);
2406 return NULL;
2407 }
29b0f896
AM		 2408 /* If we are in 16-bit mode, do not allow addr16 or data16.
2409 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2410 if ((current_templates->start->opcode_modifier.size16
2411 || current_templates->start->opcode_modifier.size32)
29b0f896 2412 && flag_code != CODE_64BIT
40fb9820 2413 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2414 ^ (flag_code == CODE_16BIT)))
2415 {
2416 as_bad (_("redundant %s prefix"),
2417 current_templates->start->name);
2418 return NULL;
45288df1 2419 }
29b0f896
AM		 2420 /* Add prefix, checking for repeated prefixes. */
2421 switch (add_prefix (current_templates->start->base_opcode))
2422 {
2423 case 0:
2424 return NULL;
2425 case 2:
2426 expecting_string_instruction = current_templates->start->name;
2427 break;
2428 }
2429 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2430 token_start = ++l;
2431 }
2432 else
2433 break;
2434 }
45288df1 2435
29b0f896
AM		 2436 if (!current_templates)
2437 {
2438 /* See if we can get a match by trimming off a suffix. */
2439 switch (mnem_p[-1])
2440 {
2441 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2442 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2443 i.suffix = SHORT_MNEM_SUFFIX;
2444 else
29b0f896
AM		 2445 case BYTE_MNEM_SUFFIX:
2446 case QWORD_MNEM_SUFFIX:
2447 i.suffix = mnem_p[-1];
2448 mnem_p[-1] = '\0';
2449 current_templates = hash_find (op_hash, mnemonic);
2450 break;
2451 case SHORT_MNEM_SUFFIX:
2452 case LONG_MNEM_SUFFIX:
2453 if (!intel_syntax)
2454 {
2455 i.suffix = mnem_p[-1];
2456 mnem_p[-1] = '\0';
2457 current_templates = hash_find (op_hash, mnemonic);
2458 }
2459 break;
252b5132 2460
29b0f896
AM		 2461 /* Intel Syntax. */
2462 case 'd':
2463 if (intel_syntax)
2464 {
9306ca4a 2465 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2466 i.suffix = SHORT_MNEM_SUFFIX;
2467 else
2468 i.suffix = LONG_MNEM_SUFFIX;
2469 mnem_p[-1] = '\0';
2470 current_templates = hash_find (op_hash, mnemonic);
2471 }
2472 break;
2473 }
2474 if (!current_templates)
2475 {
2476 as_bad (_("no such instruction: `%s'"), token_start);
2477 return NULL;
2478 }
2479 }
252b5132 2480
40fb9820
L		 2481 if (current_templates->start->opcode_modifier.jump
2482 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 2483 {
2484 /* Check for a branch hint. We allow ",pt" and ",pn" for
2485 predict taken and predict not taken respectively.
2486 I'm not sure that branch hints actually do anything on loop
2487 and jcxz insns (JumpByte) for current Pentium4 chips. They
2488 may work in the future and it doesn't hurt to accept them
2489 now. */
2490 if (l[0] == ',' && l[1] == 'p')
2491 {
2492 if (l[2] == 't')
2493 {
2494 if (!add_prefix (DS_PREFIX_OPCODE))
2495 return NULL;
2496 l += 3;
2497 }
2498 else if (l[2] == 'n')
2499 {
2500 if (!add_prefix (CS_PREFIX_OPCODE))
2501 return NULL;
2502 l += 3;
2503 }
2504 }
2505 }
2506 /* Any other comma loses. */
2507 if (*l == ',')
2508 {
2509 as_bad (_("invalid character %s in mnemonic"),
2510 output_invalid (*l));
2511 return NULL;
2512 }
252b5132 2513
29b0f896 2514 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2515 supported = 0;
2516 for (t = current_templates->start; t < current_templates->end; ++t)
2517 {
40fb9820 2518 if (cpu_flags_match (t->cpu_flags))
64e74474 2519 supported |= 1;
c6fb90c8 2520 if (cpu_flags_check_cpu64 (t->cpu_flags))
64e74474 2521 supported |= 2;
5c6af06e
JB		 2522 }
2523 if (!(supported & 2))
2524 {
2525 as_bad (flag_code == CODE_64BIT
2526 ? _("`%s' is not supported in 64-bit mode")
2527 : _("`%s' is only supported in 64-bit mode"),
2528 current_templates->start->name);
2529 return NULL;
2530 }
2531 if (!(supported & 1))
29b0f896 2532 {
5c6af06e
JB		 2533 as_warn (_("`%s' is not supported on `%s%s'"),
2534 current_templates->start->name,
2535 cpu_arch_name,
2536 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896 2537 }
40fb9820
L		 2538 else if (!cpu_arch_flags.bitfield.cpui386
2539 && (flag_code != CODE_16BIT))
29b0f896
AM		 2540 {
2541 as_warn (_("use .code16 to ensure correct addressing mode"));
2542 }
252b5132 2543
29b0f896 2544 /* Check for rep/repne without a string instruction. */
f41bbced 2545 if (expecting_string_instruction)
29b0f896 2546 {
f41bbced
JB		 2547 static templates override;
2548
2549 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 2550 if (t->opcode_modifier.isstring)
f41bbced
JB		 2551 break;
2552 if (t >= current_templates->end)
2553 {
2554 as_bad (_("expecting string instruction after `%s'"),
64e74474 2555 expecting_string_instruction);
f41bbced
JB		 2556 return NULL;
2557 }
2558 for (override.start = t; t < current_templates->end; ++t)
40fb9820 2559 if (!t->opcode_modifier.isstring)
f41bbced
JB		 2560 break;
2561 override.end = t;
2562 current_templates = &override;
29b0f896 2563 }
252b5132 2564
29b0f896
AM		 2565 return l;
2566}
252b5132 2567
29b0f896 2568static char *
e3bb37b5 2569parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2570{
2571 char *token_start;
3138f287 2572
29b0f896
AM		 2573 /* 1 if operand is pending after ','. */
2574 unsigned int expecting_operand = 0;
252b5132 2575
29b0f896
AM		 2576 /* Non-zero if operand parens not balanced. */
2577 unsigned int paren_not_balanced;
2578
2579 while (*l != END_OF_INSN)
2580 {
2581 /* Skip optional white space before operand. */
2582 if (is_space_char (*l))
2583 ++l;
2584 if (!is_operand_char (*l) && *l != END_OF_INSN)
2585 {
2586 as_bad (_("invalid character %s before operand %d"),
2587 output_invalid (*l),
2588 i.operands + 1);
2589 return NULL;
2590 }
2591 token_start = l; /* after white space */
2592 paren_not_balanced = 0;
2593 while (paren_not_balanced || *l != ',')
2594 {
2595 if (*l == END_OF_INSN)
2596 {
2597 if (paren_not_balanced)
2598 {
2599 if (!intel_syntax)
2600 as_bad (_("unbalanced parenthesis in operand %d."),
2601 i.operands + 1);
2602 else
2603 as_bad (_("unbalanced brackets in operand %d."),
2604 i.operands + 1);
2605 return NULL;
2606 }
2607 else
2608 break; /* we are done */
2609 }
2610 else if (!is_operand_char (*l) && !is_space_char (*l))
2611 {
2612 as_bad (_("invalid character %s in operand %d"),
2613 output_invalid (*l),
2614 i.operands + 1);
2615 return NULL;
2616 }
2617 if (!intel_syntax)
2618 {
2619 if (*l == '(')
2620 ++paren_not_balanced;
2621 if (*l == ')')
2622 --paren_not_balanced;
2623 }
2624 else
2625 {
2626 if (*l == '[')
2627 ++paren_not_balanced;
2628 if (*l == ']')
2629 --paren_not_balanced;
2630 }
2631 l++;
2632 }
2633 if (l != token_start)
2634 { /* Yes, we've read in another operand. */
2635 unsigned int operand_ok;
2636 this_operand = i.operands++;
2637 if (i.operands > MAX_OPERANDS)
2638 {
2639 as_bad (_("spurious operands; (%d operands/instruction max)"),
2640 MAX_OPERANDS);
2641 return NULL;
2642 }
2643 /* Now parse operand adding info to 'i' as we go along. */
2644 END_STRING_AND_SAVE (l);
2645
2646 if (intel_syntax)
2647 operand_ok =
2648 i386_intel_operand (token_start,
2649 intel_float_operand (mnemonic));
2650 else
2651 operand_ok = i386_operand (token_start);
2652
2653 RESTORE_END_STRING (l);
2654 if (!operand_ok)
2655 return NULL;
2656 }
2657 else
2658 {
2659 if (expecting_operand)
2660 {
2661 expecting_operand_after_comma:
2662 as_bad (_("expecting operand after ','; got nothing"));
2663 return NULL;
2664 }
2665 if (*l == ',')
2666 {
2667 as_bad (_("expecting operand before ','; got nothing"));
2668 return NULL;
2669 }
2670 }
7f3f1ea2 2671
29b0f896
AM		 2672 /* Now *l must be either ',' or END_OF_INSN. */
2673 if (*l == ',')
2674 {
2675 if (*++l == END_OF_INSN)
2676 {
2677 /* Just skip it, if it's \n complain. */
2678 goto expecting_operand_after_comma;
2679 }
2680 expecting_operand = 1;
2681 }
2682 }
2683 return l;
2684}
7f3f1ea2 2685
050dfa73 2686static void
4d456e3d 2687swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2688{
2689 union i386_op temp_op;
40fb9820 2690 i386_operand_type temp_type;
050dfa73 2691 enum bfd_reloc_code_real temp_reloc;
4eed87de 2692
050dfa73
MM		 2693 temp_type = i.types[xchg2];
2694 i.types[xchg2] = i.types[xchg1];
2695 i.types[xchg1] = temp_type;
2696 temp_op = i.op[xchg2];
2697 i.op[xchg2] = i.op[xchg1];
2698 i.op[xchg1] = temp_op;
2699 temp_reloc = i.reloc[xchg2];
2700 i.reloc[xchg2] = i.reloc[xchg1];
2701 i.reloc[xchg1] = temp_reloc;
2702}
2703
29b0f896 2704static void
e3bb37b5 2705swap_operands (void)
29b0f896 2706{
b7c61d9a 2707 switch (i.operands)
050dfa73 2708 {
b7c61d9a 2709 case 4:
4d456e3d 2710 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2711 case 3:
2712 case 2:
4d456e3d 2713 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2714 break;
2715 default:
2716 abort ();
29b0f896 2717 }
29b0f896
AM		 2718
2719 if (i.mem_operands == 2)
2720 {
2721 const seg_entry *temp_seg;
2722 temp_seg = i.seg[0];
2723 i.seg[0] = i.seg[1];
2724 i.seg[1] = temp_seg;
2725 }
2726}
252b5132 2727
29b0f896
AM		 2728/* Try to ensure constant immediates are represented in the smallest
2729 opcode possible. */
2730static void
e3bb37b5 2731optimize_imm (void)
29b0f896
AM		 2732{
2733 char guess_suffix = 0;
2734 int op;
252b5132 2735
29b0f896
AM		 2736 if (i.suffix)
2737 guess_suffix = i.suffix;
2738 else if (i.reg_operands)
2739 {
2740 /* Figure out a suffix from the last register operand specified.
2741 We can't do this properly yet, ie. excluding InOutPortReg,
2742 but the following works for instructions with immediates.
2743 In any case, we can't set i.suffix yet. */
2744 for (op = i.operands; --op >= 0;)
40fb9820
L		 2745 if (i.types[op].bitfield.reg8)
2746 {
2747 guess_suffix = BYTE_MNEM_SUFFIX;
2748 break;
2749 }
2750 else if (i.types[op].bitfield.reg16)
252b5132 2751 {
40fb9820
L		 2752 guess_suffix = WORD_MNEM_SUFFIX;
2753 break;
2754 }
2755 else if (i.types[op].bitfield.reg32)
2756 {
2757 guess_suffix = LONG_MNEM_SUFFIX;
2758 break;
2759 }
2760 else if (i.types[op].bitfield.reg64)
2761 {
2762 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 2763 break;
252b5132 2764 }
29b0f896
AM		 2765 }
2766 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2767 guess_suffix = WORD_MNEM_SUFFIX;
2768
2769 for (op = i.operands; --op >= 0;)
40fb9820 2770 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 2771 {
2772 switch (i.op[op].imms->X_op)
252b5132 2773 {
29b0f896
AM		 2774 case O_constant:
2775 /* If a suffix is given, this operand may be shortened. */
2776 switch (guess_suffix)
252b5132 2777 {
29b0f896 2778 case LONG_MNEM_SUFFIX:
40fb9820
L		 2779 i.types[op].bitfield.imm32 = 1;
2780 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2781 break;
2782 case WORD_MNEM_SUFFIX:
40fb9820
L		 2783 i.types[op].bitfield.imm16 = 1;
2784 i.types[op].bitfield.imm32 = 1;
2785 i.types[op].bitfield.imm32s = 1;
2786 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2787 break;
2788 case BYTE_MNEM_SUFFIX:
40fb9820
L		 2789 i.types[op].bitfield.imm8 = 1;
2790 i.types[op].bitfield.imm8s = 1;
2791 i.types[op].bitfield.imm16 = 1;
2792 i.types[op].bitfield.imm32 = 1;
2793 i.types[op].bitfield.imm32s = 1;
2794 i.types[op].bitfield.imm64 = 1;
29b0f896 2795 break;
252b5132 2796 }
252b5132 2797
29b0f896
AM		 2798 /* If this operand is at most 16 bits, convert it
2799 to a signed 16 bit number before trying to see
2800 whether it will fit in an even smaller size.
2801 This allows a 16-bit operand such as $0xffe0 to
2802 be recognised as within Imm8S range. */
40fb9820 2803 if ((i.types[op].bitfield.imm16)
29b0f896 2804 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2805 {
29b0f896
AM		 2806 i.op[op].imms->X_add_number =
2807 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2808 }
40fb9820 2809 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 2810 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2811 == 0))
2812 {
2813 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2814 ^ ((offsetT) 1 << 31))
2815 - ((offsetT) 1 << 31));
2816 }
40fb9820 2817 i.types[op]
c6fb90c8
L		 2818 = operand_type_or (i.types[op],
2819 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 2820
29b0f896
AM		 2821 /* We must avoid matching of Imm32 templates when 64bit
2822 only immediate is available. */
2823 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 2824 i.types[op].bitfield.imm32 = 0;
29b0f896 2825 break;
252b5132 2826
29b0f896
AM		 2827 case O_absent:
2828 case O_register:
2829 abort ();
2830
2831 /* Symbols and expressions. */
2832 default:
9cd96992
JB		 2833 /* Convert symbolic operand to proper sizes for matching, but don't
2834 prevent matching a set of insns that only supports sizes other
2835 than those matching the insn suffix. */
2836 {
40fb9820 2837 i386_operand_type mask, allowed;
9cd96992
JB		 2838 const template *t;
2839
c6fb90c8
L		 2840 UINTS_CLEAR (mask);
2841 UINTS_CLEAR (allowed);
40fb9820 2842
4eed87de
AM		 2843 for (t = current_templates->start;
2844 t < current_templates->end;
2845 ++t)
c6fb90c8
L		 2846 allowed = operand_type_or (allowed,
2847 t->operand_types[op]);
9cd96992
JB		 2848 switch (guess_suffix)
2849 {
2850 case QWORD_MNEM_SUFFIX:
40fb9820
L		 2851 mask.bitfield.imm64 = 1;
2852 mask.bitfield.imm32s = 1;
9cd96992
JB		 2853 break;
2854 case LONG_MNEM_SUFFIX:
40fb9820 2855 mask.bitfield.imm32 = 1;
9cd96992
JB		 2856 break;
2857 case WORD_MNEM_SUFFIX:
40fb9820 2858 mask.bitfield.imm16 = 1;
9cd96992
JB		 2859 break;
2860 case BYTE_MNEM_SUFFIX:
40fb9820 2861 mask.bitfield.imm8 = 1;
9cd96992
JB		 2862 break;
2863 default:
9cd96992
JB		 2864 break;
2865 }
c6fb90c8
L		 2866 allowed = operand_type_and (mask, allowed);
2867 if (!UINTS_ALL_ZERO (allowed))
2868 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 2869 }
29b0f896 2870 break;
252b5132 2871 }
29b0f896
AM		 2872 }
2873}
47926f60 2874
29b0f896
AM		 2875/* Try to use the smallest displacement type too. */
2876static void
e3bb37b5 2877optimize_disp (void)
29b0f896
AM		 2878{
2879 int op;
3e73aa7c 2880
29b0f896 2881 for (op = i.operands; --op >= 0;)
40fb9820 2882 if (operand_type_check (i.types[op], disp))
252b5132 2883 {
b300c311 2884 if (i.op[op].disps->X_op == O_constant)
252b5132 2885 {
b300c311 2886 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2887
40fb9820 2888 if (i.types[op].bitfield.disp16
b300c311
L		 2889 && (disp & ~(offsetT) 0xffff) == 0)
2890 {
2891 /* If this operand is at most 16 bits, convert
2892 to a signed 16 bit number and don't use 64bit
2893 displacement. */
2894 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 2895 i.types[op].bitfield.disp64 = 0;
b300c311 2896 }
40fb9820 2897 if (i.types[op].bitfield.disp32
b300c311
L		 2898 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2899 {
2900 /* If this operand is at most 32 bits, convert
2901 to a signed 32 bit number and don't use 64bit
2902 displacement. */
2903 disp &= (((offsetT) 2 << 31) - 1);
2904 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 2905 i.types[op].bitfield.disp64 = 0;
b300c311 2906 }
40fb9820 2907 if (!disp && i.types[op].bitfield.baseindex)
b300c311 2908 {
40fb9820
L		 2909 i.types[op].bitfield.disp8 = 0;
2910 i.types[op].bitfield.disp16 = 0;
2911 i.types[op].bitfield.disp32 = 0;
2912 i.types[op].bitfield.disp32s = 0;
2913 i.types[op].bitfield.disp64 = 0;
b300c311
L		 2914 i.op[op].disps = 0;
2915 i.disp_operands--;
2916 }
2917 else if (flag_code == CODE_64BIT)
2918 {
2919 if (fits_in_signed_long (disp))
28a9d8f5 2920 {
40fb9820
L		 2921 i.types[op].bitfield.disp64 = 0;
2922 i.types[op].bitfield.disp32s = 1;
28a9d8f5 2923 }
b300c311 2924 if (fits_in_unsigned_long (disp))
40fb9820 2925 i.types[op].bitfield.disp32 = 1;
b300c311 2926 }
40fb9820
L		 2927 if ((i.types[op].bitfield.disp32
2928 || i.types[op].bitfield.disp32s
2929 || i.types[op].bitfield.disp16)
b300c311 2930 && fits_in_signed_byte (disp))
40fb9820 2931 i.types[op].bitfield.disp8 = 1;
252b5132 2932 }
67a4f2b7
AO		 2933 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2934 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2935 {
2936 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2937 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 2938 i.types[op].bitfield.disp8 = 0;
2939 i.types[op].bitfield.disp16 = 0;
2940 i.types[op].bitfield.disp32 = 0;
2941 i.types[op].bitfield.disp32s = 0;
2942 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 2943 }
2944 else
b300c311 2945 /* We only support 64bit displacement on constants. */
40fb9820 2946 i.types[op].bitfield.disp64 = 0;
252b5132 2947 }
29b0f896
AM		 2948}
2949
2950static int
e3bb37b5 2951match_template (void)
29b0f896
AM		 2952{
2953 /* Points to template once we've found it. */
2954 const template *t;
40fb9820 2955 i386_operand_type overlap0, overlap1, overlap2, overlap3;
29b0f896 2956 unsigned int found_reverse_match;
40fb9820
L		 2957 i386_opcode_modifier suffix_check;
2958 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 2959 int addr_prefix_disp;
a5c311ca 2960 unsigned int j;
c6fb90c8 2961 i386_cpu_flags overlap;
29b0f896 2962
f48ff2ae
L		 2963#if MAX_OPERANDS != 4
2964# error "MAX_OPERANDS must be 4."
2965#endif
2966
29b0f896 2967 found_reverse_match = 0;
539e75ad 2968 addr_prefix_disp = -1;
40fb9820
L		 2969
2970 memset (&suffix_check, 0, sizeof (suffix_check));
2971 if (i.suffix == BYTE_MNEM_SUFFIX)
2972 suffix_check.no_bsuf = 1;
2973 else if (i.suffix == WORD_MNEM_SUFFIX)
2974 suffix_check.no_wsuf = 1;
2975 else if (i.suffix == SHORT_MNEM_SUFFIX)
2976 suffix_check.no_ssuf = 1;
2977 else if (i.suffix == LONG_MNEM_SUFFIX)
2978 suffix_check.no_lsuf = 1;
2979 else if (i.suffix == QWORD_MNEM_SUFFIX)
2980 suffix_check.no_qsuf = 1;
2981 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
2982 suffix_check.no_xsuf = 1;
29b0f896 2983
45aa61fe 2984 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2985 {
539e75ad
L		 2986 addr_prefix_disp = -1;
2987
29b0f896
AM		 2988 /* Must have right number of operands. */
2989 if (i.operands != t->operands)
2990 continue;
2991
20592a94 2992 /* Check the suffix, except for some instructions in intel mode. */
40fb9820
L		 2993 if (((t->opcode_modifier.no_bsuf & suffix_check.no_bsuf)
2994 || (t->opcode_modifier.no_wsuf & suffix_check.no_wsuf)
2995 || (t->opcode_modifier.no_lsuf & suffix_check.no_lsuf)
2996 || (t->opcode_modifier.no_ssuf & suffix_check.no_ssuf)
2997 || (t->opcode_modifier.no_qsuf & suffix_check.no_qsuf)
2998 || (t->opcode_modifier.no_xsuf & suffix_check.no_xsuf))
2999 && !(intel_syntax && t->opcode_modifier.ignoresize))
29b0f896
AM		 3000 continue;
3001
a5c311ca
L		 3002 for (j = 0; j < MAX_OPERANDS; j++)
3003 operand_types [j] = t->operand_types [j];
539e75ad 3004
45aa61fe
AM		 3005 /* In general, don't allow 64-bit operands in 32-bit mode. */
3006 if (i.suffix == QWORD_MNEM_SUFFIX
3007 && flag_code != CODE_64BIT
3008 && (intel_syntax
40fb9820 3009 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3010 && !intel_float_operand (t->name))
3011 : intel_float_operand (t->name) != 2)
40fb9820
L		 3012 && ((!operand_types[0].bitfield.regmmx
3013 && !operand_types[0].bitfield.regxmm)
3014 || (!operand_types[t->operands > 1].bitfield.regmmx
3015 && !!operand_types[t->operands > 1].bitfield.regxmm))
45aa61fe
AM		 3016 && (t->base_opcode != 0x0fc7
3017 || t->extension_opcode != 1 /* cmpxchg8b */))
3018 continue;
3019
29b0f896 3020 /* Do not verify operands when there are none. */
c6fb90c8 3021 else
29b0f896 3022 {
c6fb90c8
L		 3023 overlap = cpu_flags_and (t->cpu_flags, cpu_arch_flags_not);
3024 if (!t->operands)
3025 {
3026 if (!UINTS_ALL_ZERO (overlap))
3027 continue;
3028 /* We've found a match; break out of loop. */
3029 break;
3030 }
29b0f896 3031 }
252b5132 3032
539e75ad
L		 3033 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3034 into Disp32/Disp16/Disp32 operand. */
3035 if (i.prefix[ADDR_PREFIX] != 0)
3036 {
40fb9820 3037 /* There should be only one Disp operand. */
539e75ad
L		 3038 switch (flag_code)
3039 {
3040 case CODE_16BIT:
40fb9820
L		 3041 for (j = 0; j < MAX_OPERANDS; j++)
3042 {
3043 if (operand_types[j].bitfield.disp16)
3044 {
3045 addr_prefix_disp = j;
3046 operand_types[j].bitfield.disp32 = 1;
3047 operand_types[j].bitfield.disp16 = 0;
3048 break;
3049 }
3050 }
539e75ad
L		 3051 break;
3052 case CODE_32BIT:
40fb9820
L		 3053 for (j = 0; j < MAX_OPERANDS; j++)
3054 {
3055 if (operand_types[j].bitfield.disp32)
3056 {
3057 addr_prefix_disp = j;
3058 operand_types[j].bitfield.disp32 = 0;
3059 operand_types[j].bitfield.disp16 = 1;
3060 break;
3061 }
3062 }
539e75ad
L		 3063 break;
3064 case CODE_64BIT:
40fb9820
L		 3065 for (j = 0; j < MAX_OPERANDS; j++)
3066 {
3067 if (operand_types[j].bitfield.disp64)
3068 {
3069 addr_prefix_disp = j;
3070 operand_types[j].bitfield.disp64 = 0;
3071 operand_types[j].bitfield.disp32 = 1;
3072 break;
3073 }
3074 }
539e75ad
L		 3075 break;
3076 }
539e75ad
L		 3077 }
3078
c6fb90c8 3079 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3080 switch (t->operands)
3081 {
3082 case 1:
40fb9820 3083 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3084 continue;
3085 break;
3086 case 2:
8b38ad71
L		 3087 /* xchg %eax, %eax is a special case. It is an aliase for nop
3088 only in 32bit mode and we can use opcode 0x90. In 64bit
3089 mode, we can't use 0x90 for xchg %eax, %eax since it should
3090 zero-extend %eax to %rax. */
3091 if (flag_code == CODE_64BIT
3092 && t->base_opcode == 0x90
c6fb90c8
L		 3093 && UINTS_EQUAL (i.types [0], acc32)
3094 && UINTS_EQUAL (i.types [1], acc32))
8b38ad71 3095 continue;
29b0f896 3096 case 3:
f48ff2ae 3097 case 4:
c6fb90c8 3098 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3099 if (!operand_type_match (overlap0, i.types[0])
3100 || !operand_type_match (overlap1, i.types[1])
cb712a9e 3101 /* monitor in SSE3 is a very special case. The first
708587a4 3102 register and the second register may have different
26186d74
L		 3103 sizes. The same applies to crc32 in SSE4.2. It is
3104 also true for invlpga, vmload, vmrun and vmsave in
3105 SVME. */
cb712a9e 3106 || !((t->base_opcode == 0x0f01
26186d74
L		 3107 && (t->extension_opcode == 0xc8
3108 || t->extension_opcode == 0xd8
3109 || t->extension_opcode == 0xda
3110 || t->extension_opcode == 0xdb
3111 || t->extension_opcode == 0xdf))
381d071f 3112 || t->base_opcode == 0xf20f38f1
40fb9820
L		 3113 || operand_type_register_match (overlap0, i.types[0],
3114 operand_types[0],
3115 overlap1, i.types[1],
3116 operand_types[1])))
29b0f896
AM		 3117 {
3118 /* Check if other direction is valid ... */
40fb9820 3119 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3120 continue;
3121
3122 /* Try reversing direction of operands. */
c6fb90c8
L		 3123 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3124 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3125 if (!operand_type_match (overlap0, i.types[0])
3126 || !operand_type_match (overlap1, i.types[1])
3127 || !operand_type_register_match (overlap0, i.types[0],
3128 operand_types[1],
3129 overlap1, i.types[1],
3130 operand_types[0]))
29b0f896
AM		 3131 {
3132 /* Does not match either direction. */
3133 continue;
3134 }
3135 /* found_reverse_match holds which of D or FloatDR
3136 we've found. */
40fb9820 3137 if (t->opcode_modifier.d)
8a2ed489 3138 found_reverse_match = Opcode_D;
40fb9820 3139 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3140 found_reverse_match = Opcode_FloatD;
3141 else
3142 found_reverse_match = 0;
40fb9820 3143 if (t->opcode_modifier.floatr)
8a2ed489 3144 found_reverse_match |= Opcode_FloatR;
29b0f896 3145 }
f48ff2ae 3146 else
29b0f896 3147 {
f48ff2ae 3148 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3149 switch (t->operands)
3150 {
3151 case 4:
c6fb90c8
L		 3152 overlap3 = operand_type_and (i.types[3],
3153 operand_types[3]);
d1cbb4db 3154 case 3:
c6fb90c8
L		 3155 overlap2 = operand_type_and (i.types[2],
3156 operand_types[2]);
d1cbb4db
L		 3157 break;
3158 }
29b0f896 3159
f48ff2ae
L		 3160 switch (t->operands)
3161 {
3162 case 4:
40fb9820
L		 3163 if (!operand_type_match (overlap3, i.types[3])
3164 || !operand_type_register_match (overlap2,
3165 i.types[2],
3166 operand_types[2],
3167 overlap3,
3168 i.types[3],
3169 operand_types[3]))
f48ff2ae
L		 3170 continue;
3171 case 3:
3172 /* Here we make use of the fact that there are no
3173 reverse match 3 operand instructions, and all 3
3174 operand instructions only need to be checked for
3175 register consistency between operands 2 and 3. */
40fb9820
L		 3176 if (!operand_type_match (overlap2, i.types[2])
3177 || !operand_type_register_match (overlap1,
3178 i.types[1],
3179 operand_types[1],
3180 overlap2,
3181 i.types[2],
3182 operand_types[2]))
f48ff2ae
L		 3183 continue;
3184 break;
3185 }
29b0f896 3186 }
f48ff2ae 3187 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3188 slip through to break. */
3189 }
c6fb90c8 3190 if (!UINTS_ALL_ZERO (overlap))
29b0f896
AM		 3191 {
3192 found_reverse_match = 0;
3193 continue;
3194 }
3195 /* We've found a match; break out of loop. */
3196 break;
3197 }
3198
3199 if (t == current_templates->end)
3200 {
3201 /* We found no match. */
3202 as_bad (_("suffix or operands invalid for `%s'"),
3203 current_templates->start->name);
3204 return 0;
3205 }
252b5132 3206
29b0f896
AM		 3207 if (!quiet_warnings)
3208 {
3209 if (!intel_syntax
40fb9820
L		 3210 && (i.types[0].bitfield.jumpabsolute
3211 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3212 {
3213 as_warn (_("indirect %s without `*'"), t->name);
3214 }
3215
40fb9820
L		 3216 if (t->opcode_modifier.isprefix
3217 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3218 {
3219 /* Warn them that a data or address size prefix doesn't
3220 affect assembly of the next line of code. */
3221 as_warn (_("stand-alone `%s' prefix"), t->name);
3222 }
3223 }
3224
3225 /* Copy the template we found. */
3226 i.tm = *t;
539e75ad
L		 3227
3228 if (addr_prefix_disp != -1)
3229 i.tm.operand_types[addr_prefix_disp]
3230 = operand_types[addr_prefix_disp];
3231
29b0f896
AM		 3232 if (found_reverse_match)
3233 {
3234 /* If we found a reverse match we must alter the opcode
3235 direction bit. found_reverse_match holds bits to change
3236 (different for int & float insns). */
3237
3238 i.tm.base_opcode ^= found_reverse_match;
3239
539e75ad
L		 3240 i.tm.operand_types[0] = operand_types[1];
3241 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3242 }
3243
3244 return 1;
3245}
3246
3247static int
e3bb37b5 3248check_string (void)
29b0f896 3249{
40fb9820
L		 3250 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3251 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3252 {
3253 if (i.seg[0] != NULL && i.seg[0] != &es)
3254 {
3255 as_bad (_("`%s' operand %d must use `%%es' segment"),
3256 i.tm.name,
3257 mem_op + 1);
3258 return 0;
3259 }
3260 /* There's only ever one segment override allowed per instruction.
3261 This instruction possibly has a legal segment override on the
3262 second operand, so copy the segment to where non-string
3263 instructions store it, allowing common code. */
3264 i.seg[0] = i.seg[1];
3265 }
40fb9820 3266 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3267 {
3268 if (i.seg[1] != NULL && i.seg[1] != &es)
3269 {
3270 as_bad (_("`%s' operand %d must use `%%es' segment"),
3271 i.tm.name,
3272 mem_op + 2);
3273 return 0;
3274 }
3275 }
3276 return 1;
3277}
3278
3279static int
543613e9 3280process_suffix (void)
29b0f896
AM		 3281{
3282 /* If matched instruction specifies an explicit instruction mnemonic
3283 suffix, use it. */
40fb9820
L		 3284 if (i.tm.opcode_modifier.size16)
3285 i.suffix = WORD_MNEM_SUFFIX;
3286 else if (i.tm.opcode_modifier.size32)
3287 i.suffix = LONG_MNEM_SUFFIX;
3288 else if (i.tm.opcode_modifier.size64)
3289 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3290 else if (i.reg_operands)
3291 {
3292 /* If there's no instruction mnemonic suffix we try to invent one
3293 based on register operands. */
3294 if (!i.suffix)
3295 {
3296 /* We take i.suffix from the last register operand specified,
3297 Destination register type is more significant than source
381d071f
L		 3298 register type. crc32 in SSE4.2 prefers source register
3299 type. */
3300 if (i.tm.base_opcode == 0xf20f38f1)
3301 {
40fb9820
L		 3302 if (i.types[0].bitfield.reg16)
3303 i.suffix = WORD_MNEM_SUFFIX;
3304 else if (i.types[0].bitfield.reg32)
3305 i.suffix = LONG_MNEM_SUFFIX;
3306 else if (i.types[0].bitfield.reg64)
3307 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3308 }
9344ff29 3309 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3310 {
40fb9820 3311 if (i.types[0].bitfield.reg8)
20592a94
L		 3312 i.suffix = BYTE_MNEM_SUFFIX;
3313 }
381d071f
L		 3314
3315 if (!i.suffix)
3316 {
3317 int op;
3318
20592a94
L		 3319 if (i.tm.base_opcode == 0xf20f38f1
3320 || i.tm.base_opcode == 0xf20f38f0)
3321 {
3322 /* We have to know the operand size for crc32. */
3323 as_bad (_("ambiguous memory operand size for `%s`"),
3324 i.tm.name);
3325 return 0;
3326 }
3327
381d071f 3328 for (op = i.operands; --op >= 0;)
40fb9820 3329 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3330 {
40fb9820
L		 3331 if (i.types[op].bitfield.reg8)
3332 {
3333 i.suffix = BYTE_MNEM_SUFFIX;
3334 break;
3335 }
3336 else if (i.types[op].bitfield.reg16)
3337 {
3338 i.suffix = WORD_MNEM_SUFFIX;
3339 break;
3340 }
3341 else if (i.types[op].bitfield.reg32)
3342 {
3343 i.suffix = LONG_MNEM_SUFFIX;
3344 break;
3345 }
3346 else if (i.types[op].bitfield.reg64)
3347 {
3348 i.suffix = QWORD_MNEM_SUFFIX;
3349 break;
3350 }
381d071f
L		 3351 }
3352 }
29b0f896
AM		 3353 }
3354 else if (i.suffix == BYTE_MNEM_SUFFIX)
3355 {
3356 if (!check_byte_reg ())
3357 return 0;
3358 }
3359 else if (i.suffix == LONG_MNEM_SUFFIX)
3360 {
3361 if (!check_long_reg ())
3362 return 0;
3363 }
3364 else if (i.suffix == QWORD_MNEM_SUFFIX)
3365 {
3366 if (!check_qword_reg ())
3367 return 0;
3368 }
3369 else if (i.suffix == WORD_MNEM_SUFFIX)
3370 {
3371 if (!check_word_reg ())
3372 return 0;
3373 }
40fb9820 3374 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 3375 /* Do nothing if the instruction is going to ignore the prefix. */
3376 ;
3377 else
3378 abort ();
3379 }
40fb9820 3380 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 3381 && !i.suffix
3382 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 3383 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 3384 {
3385 i.suffix = stackop_size;
3386 }
9306ca4a
JB		 3387 else if (intel_syntax
3388 && !i.suffix
40fb9820
L		 3389 && (i.tm.operand_types[0].bitfield.jumpabsolute
3390 || i.tm.opcode_modifier.jumpbyte
3391 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 3392 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3393 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 3394 {
3395 switch (flag_code)
3396 {
3397 case CODE_64BIT:
40fb9820 3398 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 3399 {
3400 i.suffix = QWORD_MNEM_SUFFIX;
3401 break;
3402 }
3403 case CODE_32BIT:
40fb9820 3404 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 3405 i.suffix = LONG_MNEM_SUFFIX;
3406 break;
3407 case CODE_16BIT:
40fb9820 3408 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 3409 i.suffix = WORD_MNEM_SUFFIX;
3410 break;
3411 }
3412 }
252b5132 3413
9306ca4a 3414 if (!i.suffix)
29b0f896 3415 {
9306ca4a
JB		 3416 if (!intel_syntax)
3417 {
40fb9820 3418 if (i.tm.opcode_modifier.w)
9306ca4a 3419 {
4eed87de
AM		 3420 as_bad (_("no instruction mnemonic suffix given and "
3421 "no register operands; can't size instruction"));
9306ca4a
JB		 3422 return 0;
3423 }
3424 }
3425 else
3426 {
40fb9820
L		 3427 unsigned int suffixes;
3428
3429 suffixes = !i.tm.opcode_modifier.no_bsuf;
3430 if (!i.tm.opcode_modifier.no_wsuf)
3431 suffixes |= 1 << 1;
3432 if (!i.tm.opcode_modifier.no_lsuf)
3433 suffixes |= 1 << 2;
3434 if (!i.tm.opcode_modifier.no_lsuf)
3435 suffixes |= 1 << 3;
3436 if (!i.tm.opcode_modifier.no_ssuf)
3437 suffixes |= 1 << 4;
3438 if (!i.tm.opcode_modifier.no_qsuf)
3439 suffixes |= 1 << 5;
3440
3441 /* There are more than suffix matches. */
3442 if (i.tm.opcode_modifier.w
9306ca4a 3443 || ((suffixes & (suffixes - 1))
40fb9820
L		 3444 && !i.tm.opcode_modifier.defaultsize
3445 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 3446 {
3447 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3448 return 0;
3449 }
3450 }
29b0f896 3451 }
252b5132 3452
9306ca4a
JB		 3453 /* Change the opcode based on the operand size given by i.suffix;
3454 We don't need to change things for byte insns. */
3455
29b0f896
AM		 3456 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
3457 {
3458 /* It's not a byte, select word/dword operation. */
40fb9820 3459 if (i.tm.opcode_modifier.w)
29b0f896 3460 {
40fb9820 3461 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 3462 i.tm.base_opcode |= 8;
3463 else
3464 i.tm.base_opcode |= 1;
3465 }
0f3f3d8b 3466
29b0f896
AM		 3467 /* Now select between word & dword operations via the operand
3468 size prefix, except for instructions that will ignore this
3469 prefix anyway. */
26186d74
L		 3470 if (i.tm.base_opcode == 0x0f01
3471 && (i.tm.extension_opcode == 0xc8
3472 || i.tm.extension_opcode == 0xd8
3473 || i.tm.extension_opcode == 0xda
3474 || i.tm.extension_opcode == 0xdb
3475 || i.tm.extension_opcode == 0xdf))
cb712a9e
L		 3476 {
3477 /* monitor in SSE3 is a very special case. The default size
3478 of AX is the size of mode. The address size override
26186d74
L		 3479 prefix will change the size of AX. It is also true for
3480 invlpga, vmload, vmrun and vmsave in SVME. */
40fb9820
L		 3481 if ((flag_code == CODE_32BIT
3482 && i.op->regs[0].reg_type.bitfield.reg16)
3483 || (flag_code != CODE_32BIT
3484 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 3485 if (!add_prefix (ADDR_PREFIX_OPCODE))
3486 return 0;
3487 }
3488 else if (i.suffix != QWORD_MNEM_SUFFIX
3489 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 3490 && !i.tm.opcode_modifier.ignoresize
3491 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 3492 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3493 || (flag_code == CODE_64BIT
40fb9820 3494 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 3495 {
3496 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3497
40fb9820 3498 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 3499 prefix = ADDR_PREFIX_OPCODE;
252b5132 3500
29b0f896
AM		 3501 if (!add_prefix (prefix))
3502 return 0;
24eab124 3503 }
252b5132 3504
29b0f896
AM		 3505 /* Set mode64 for an operand. */
3506 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3507 && flag_code == CODE_64BIT
40fb9820 3508 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 3509 {
3510 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 3511 need rex64. cmpxchg8b is also a special case. */
3512 if (! (i.operands == 2
3513 && i.tm.base_opcode == 0x90
3514 && i.tm.extension_opcode == None
c6fb90c8
L		 3515 && UINTS_EQUAL (i.types [0], acc64)
3516 && UINTS_EQUAL (i.types [1], acc64))
d9a5e5e5
L		 3517 && ! (i.operands == 1
3518 && i.tm.base_opcode == 0xfc7
3519 && i.tm.extension_opcode == 1
40fb9820
L		 3520 && !operand_type_check (i.types [0], reg)
3521 && operand_type_check (i.types [0], anymem)))
f6bee062 3522 i.rex |= REX_W;
46e883c5 3523 }
3e73aa7c 3524
29b0f896
AM		 3525 /* Size floating point instruction. */
3526 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 3527 if (i.tm.opcode_modifier.floatmf)
543613e9 3528 i.tm.base_opcode ^= 4;
29b0f896 3529 }
7ecd2f8b 3530
29b0f896
AM		 3531 return 1;
3532}
3e73aa7c 3533
29b0f896 3534static int
543613e9 3535check_byte_reg (void)
29b0f896
AM		 3536{
3537 int op;
543613e9 3538
29b0f896
AM		 3539 for (op = i.operands; --op >= 0;)
3540 {
3541 /* If this is an eight bit register, it's OK. If it's the 16 or
3542 32 bit version of an eight bit register, we will just use the
3543 low portion, and that's OK too. */
40fb9820 3544 if (i.types[op].bitfield.reg8)
29b0f896
AM		 3545 continue;
3546
c3ad16c0
L		 3547 /* movzx, movsx, pextrb and pinsrb should not generate this
3548 warning. */
29b0f896
AM		 3549 if (intel_syntax
3550 && (i.tm.base_opcode == 0xfb7
3551 || i.tm.base_opcode == 0xfb6
3552 || i.tm.base_opcode == 0x63
3553 || i.tm.base_opcode == 0xfbe
c3ad16c0
L		 3554 || i.tm.base_opcode == 0xfbf
3555 || i.tm.base_opcode == 0x660f3a14
3556 || i.tm.base_opcode == 0x660f3a20))
29b0f896
AM		 3557 continue;
3558
9344ff29
L		 3559 /* crc32 doesn't generate this warning. */
3560 if (i.tm.base_opcode == 0xf20f38f0)
3561 continue;
3562
40fb9820
L		 3563 if ((i.types[op].bitfield.reg16
3564 || i.types[op].bitfield.reg32
3565 || i.types[op].bitfield.reg64)
3566 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3567 {
3568 /* Prohibit these changes in the 64bit mode, since the
3569 lowering is more complicated. */
3570 if (flag_code == CODE_64BIT
40fb9820 3571 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 3572 {
2ca3ace5
L		 3573 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3574 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3575 i.suffix);
3576 return 0;
3577 }
3578#if REGISTER_WARNINGS
3579 if (!quiet_warnings
40fb9820 3580 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 3581 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3582 register_prefix,
40fb9820 3583 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 3584 ? REGNAM_AL - REGNAM_AX
3585 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3586 register_prefix,
29b0f896
AM		 3587 i.op[op].regs->reg_name,
3588 i.suffix);
3589#endif
3590 continue;
3591 }
3592 /* Any other register is bad. */
40fb9820
L		 3593 if (i.types[op].bitfield.reg16
3594 || i.types[op].bitfield.reg32
3595 || i.types[op].bitfield.reg64
3596 || i.types[op].bitfield.regmmx
3597 || i.types[op].bitfield.regxmm
3598 || i.types[op].bitfield.sreg2
3599 || i.types[op].bitfield.sreg3
3600 || i.types[op].bitfield.control
3601 || i.types[op].bitfield.debug
3602 || i.types[op].bitfield.test
3603 || i.types[op].bitfield.floatreg
3604 || i.types[op].bitfield.floatacc)
29b0f896 3605 {
a540244d
L		 3606 as_bad (_("`%s%s' not allowed with `%s%c'"),
3607 register_prefix,
29b0f896
AM		 3608 i.op[op].regs->reg_name,
3609 i.tm.name,
3610 i.suffix);
3611 return 0;
3612 }
3613 }
3614 return 1;
3615}
3616
3617static int
e3bb37b5 3618check_long_reg (void)
29b0f896
AM		 3619{
3620 int op;
3621
3622 for (op = i.operands; --op >= 0;)
3623 /* Reject eight bit registers, except where the template requires
3624 them. (eg. movzb) */
40fb9820
L		 3625 if (i.types[op].bitfield.reg8
3626 && (i.tm.operand_types[op].bitfield.reg16
3627 || i.tm.operand_types[op].bitfield.reg32
3628 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3629 {
a540244d
L		 3630 as_bad (_("`%s%s' not allowed with `%s%c'"),
3631 register_prefix,
29b0f896
AM		 3632 i.op[op].regs->reg_name,
3633 i.tm.name,
3634 i.suffix);
3635 return 0;
3636 }
3637 /* Warn if the e prefix on a general reg is missing. */
3638 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3639 && i.types[op].bitfield.reg16
3640 && (i.tm.operand_types[op].bitfield.reg32
3641 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3642 {
3643 /* Prohibit these changes in the 64bit mode, since the
3644 lowering is more complicated. */
3645 if (flag_code == CODE_64BIT)
252b5132 3646 {
2ca3ace5
L		 3647 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3648 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3649 i.suffix);
3650 return 0;
252b5132 3651 }
29b0f896
AM		 3652#if REGISTER_WARNINGS
3653 else
a540244d
L		 3654 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3655 register_prefix,
29b0f896 3656 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3657 register_prefix,
29b0f896
AM		 3658 i.op[op].regs->reg_name,
3659 i.suffix);
3660#endif
252b5132 3661 }
29b0f896 3662 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 3663 else if (i.types[op].bitfield.reg64
3664 && (i.tm.operand_types[op].bitfield.reg32
3665 || i.tm.operand_types[op].bitfield.acc))
252b5132 3666 {
34828aad
L		 3667 if (intel_syntax
3668 && i.tm.base_opcode == 0xf30f2d
40fb9820 3669 && !i.types[0].bitfield.regxmm)
34828aad
L		 3670 {
3671 /* cvtss2si converts DWORD memory to Reg64. We want
3672 REX byte. */
3673 i.suffix = QWORD_MNEM_SUFFIX;
3674 }
3675 else
3676 {
3677 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3678 register_prefix, i.op[op].regs->reg_name,
3679 i.suffix);
3680 return 0;
3681 }
29b0f896
AM		 3682 }
3683 return 1;
3684}
252b5132 3685
29b0f896 3686static int
e3bb37b5 3687check_qword_reg (void)
29b0f896
AM		 3688{
3689 int op;
252b5132 3690
29b0f896
AM		 3691 for (op = i.operands; --op >= 0; )
3692 /* Reject eight bit registers, except where the template requires
3693 them. (eg. movzb) */
40fb9820
L		 3694 if (i.types[op].bitfield.reg8
3695 && (i.tm.operand_types[op].bitfield.reg16
3696 || i.tm.operand_types[op].bitfield.reg32
3697 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3698 {
a540244d
L		 3699 as_bad (_("`%s%s' not allowed with `%s%c'"),
3700 register_prefix,
29b0f896
AM		 3701 i.op[op].regs->reg_name,
3702 i.tm.name,
3703 i.suffix);
3704 return 0;
3705 }
3706 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 3707 else if ((i.types[op].bitfield.reg16
3708 || i.types[op].bitfield.reg32)
3709 && (i.tm.operand_types[op].bitfield.reg32
3710 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3711 {
3712 /* Prohibit these changes in the 64bit mode, since the
3713 lowering is more complicated. */
34828aad
L		 3714 if (intel_syntax
3715 && i.tm.base_opcode == 0xf20f2d
40fb9820 3716 && !i.types[0].bitfield.regxmm)
34828aad
L		 3717 {
3718 /* cvtsd2si converts QWORD memory to Reg32. We don't want
3719 REX byte. */
3720 i.suffix = LONG_MNEM_SUFFIX;
3721 }
3722 else
3723 {
3724 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3725 register_prefix, i.op[op].regs->reg_name,
3726 i.suffix);
3727 return 0;
3728 }
252b5132 3729 }
29b0f896
AM		 3730 return 1;
3731}
252b5132 3732
29b0f896 3733static int
e3bb37b5 3734check_word_reg (void)
29b0f896
AM		 3735{
3736 int op;
3737 for (op = i.operands; --op >= 0;)
3738 /* Reject eight bit registers, except where the template requires
3739 them. (eg. movzb) */
40fb9820
L		 3740 if (i.types[op].bitfield.reg8
3741 && (i.tm.operand_types[op].bitfield.reg16
3742 || i.tm.operand_types[op].bitfield.reg32
3743 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3744 {
a540244d
L		 3745 as_bad (_("`%s%s' not allowed with `%s%c'"),
3746 register_prefix,
29b0f896
AM		 3747 i.op[op].regs->reg_name,
3748 i.tm.name,
3749 i.suffix);
3750 return 0;
3751 }
3752 /* Warn if the e prefix on a general reg is present. */
3753 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3754 && i.types[op].bitfield.reg32
3755 && (i.tm.operand_types[op].bitfield.reg16
3756 || i.tm.operand_types[op].bitfield.acc))
252b5132 3757 {
29b0f896
AM		 3758 /* Prohibit these changes in the 64bit mode, since the
3759 lowering is more complicated. */
3760 if (flag_code == CODE_64BIT)
252b5132 3761 {
2ca3ace5
L		 3762 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3763 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3764 i.suffix);
3765 return 0;
252b5132 3766 }
29b0f896
AM		 3767 else
3768#if REGISTER_WARNINGS
a540244d
L		 3769 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3770 register_prefix,
29b0f896 3771 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 3772 register_prefix,
29b0f896
AM		 3773 i.op[op].regs->reg_name,
3774 i.suffix);
3775#endif
3776 }
3777 return 1;
3778}
252b5132 3779
29b0f896 3780static int
40fb9820 3781update_imm (unsigned int j)
29b0f896 3782{
40fb9820
L		 3783 i386_operand_type overlap;
3784
c6fb90c8 3785 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 3786 if ((overlap.bitfield.imm8
3787 || overlap.bitfield.imm8s
3788 || overlap.bitfield.imm16
3789 || overlap.bitfield.imm32
3790 || overlap.bitfield.imm32s
3791 || overlap.bitfield.imm64)
c6fb90c8
L		 3792 && !UINTS_EQUAL (overlap, imm8)
3793 && !UINTS_EQUAL (overlap, imm8s)
3794 && !UINTS_EQUAL (overlap, imm16)
3795 && !UINTS_EQUAL (overlap, imm32)
3796 && !UINTS_EQUAL (overlap, imm32s)
3797 && !UINTS_EQUAL (overlap, imm64))
29b0f896
AM		 3798 {
3799 if (i.suffix)
3800 {
40fb9820
L		 3801 i386_operand_type temp;
3802
c6fb90c8 3803 UINTS_CLEAR (temp);
40fb9820
L		 3804 if (i.suffix == BYTE_MNEM_SUFFIX)
3805 {
3806 temp.bitfield.imm8 = overlap.bitfield.imm8;
3807 temp.bitfield.imm8s = overlap.bitfield.imm8s;
3808 }
3809 else if (i.suffix == WORD_MNEM_SUFFIX)
3810 temp.bitfield.imm16 = overlap.bitfield.imm16;
3811 else if (i.suffix == QWORD_MNEM_SUFFIX)
3812 {
3813 temp.bitfield.imm64 = overlap.bitfield.imm64;
3814 temp.bitfield.imm32s = overlap.bitfield.imm32s;
3815 }
3816 else
3817 temp.bitfield.imm32 = overlap.bitfield.imm32;
3818 overlap = temp;
29b0f896 3819 }
c6fb90c8
L		 3820 else if (UINTS_EQUAL (overlap, imm16_32_32s)
3821 || UINTS_EQUAL (overlap, imm16_32)
3822 || UINTS_EQUAL (overlap, imm16_32s))
29b0f896 3823 {
c6fb90c8 3824 UINTS_CLEAR (overlap);
40fb9820
L		 3825 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3826 overlap.bitfield.imm16 = 1;
3827 else
3828 overlap.bitfield.imm32s = 1;
29b0f896 3829 }
c6fb90c8
L		 3830 if (!UINTS_EQUAL (overlap, imm8)
3831 && !UINTS_EQUAL (overlap, imm8s)
3832 && !UINTS_EQUAL (overlap, imm16)
3833 && !UINTS_EQUAL (overlap, imm32)
3834 && !UINTS_EQUAL (overlap, imm32s)
3835 && !UINTS_EQUAL (overlap, imm64))
29b0f896 3836 {
4eed87de
AM		 3837 as_bad (_("no instruction mnemonic suffix given; "
3838 "can't determine immediate size"));
29b0f896
AM		 3839 return 0;
3840 }
3841 }
40fb9820 3842 i.types[j] = overlap;
29b0f896 3843
40fb9820
L		 3844 return 1;
3845}
3846
3847static int
3848finalize_imm (void)
3849{
3850 unsigned int j;
29b0f896 3851
40fb9820
L		 3852 for (j = 0; j < 2; j++)
3853 if (update_imm (j) == 0)
3854 return 0;
3855
c6fb90c8 3856 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 3857 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 3858
3859 return 1;
3860}
3861
3862static int
e3bb37b5 3863process_operands (void)
29b0f896
AM		 3864{
3865 /* Default segment register this instruction will use for memory
3866 accesses. 0 means unknown. This is only for optimizing out
3867 unnecessary segment overrides. */
3868 const seg_entry *default_seg = 0;
3869
3870 /* The imul $imm, %reg instruction is converted into
3871 imul $imm, %reg, %reg, and the clr %reg instruction
3872 is converted into xor %reg, %reg. */
40fb9820 3873 if (i.tm.opcode_modifier.regkludge)
29b0f896 3874 {
40fb9820 3875 if (i.tm.cpu_flags.bitfield.cpusse4_1)
42903f7f
L		 3876 {
3877 /* The first operand in instruction blendvpd, blendvps and
3878 pblendvb in SSE4.1 is implicit and must be xmm0. */
3879 assert (i.operands == 3
3880 && i.reg_operands >= 2
c6fb90c8 3881 && UINTS_EQUAL (i.types[0], regxmm));
42903f7f
L		 3882 if (i.op[0].regs->reg_num != 0)
3883 {
3884 if (intel_syntax)
3885 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
3886 i.tm.name, register_prefix);
3887 else
3888 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
3889 i.tm.name, register_prefix);
3890 return 0;
3891 }
3892 i.op[0] = i.op[1];
3893 i.op[1] = i.op[2];
3894 i.types[0] = i.types[1];
3895 i.types[1] = i.types[2];
3896 i.operands--;
3897 i.reg_operands--;
3898
3899 /* We need to adjust fields in i.tm since they are used by
3900 build_modrm_byte. */
3901 i.tm.operand_types [0] = i.tm.operand_types [1];
3902 i.tm.operand_types [1] = i.tm.operand_types [2];
3903 i.tm.operands--;
3904 }
3905 else
3906 {
40fb9820
L		 3907 unsigned int first_reg_op;
3908
3909 if (operand_type_check (i.types[0], reg))
3910 first_reg_op = 0;
3911 else
3912 first_reg_op = 1;
42903f7f
L		 3913 /* Pretend we saw the extra register operand. */
3914 assert (i.reg_operands == 1
3915 && i.op[first_reg_op + 1].regs == 0);
3916 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3917 i.types[first_reg_op + 1] = i.types[first_reg_op];
3918 i.operands++;
3919 i.reg_operands++;
3920 }
29b0f896
AM		 3921 }
3922
40fb9820 3923 if (i.tm.opcode_modifier.shortform)
29b0f896 3924 {
40fb9820
L		 3925 if (i.types[0].bitfield.sreg2
3926 || i.types[0].bitfield.sreg3)
29b0f896 3927 {
4eed87de
AM		 3928 if (i.tm.base_opcode == POP_SEG_SHORT
3929 && i.op[0].regs->reg_num == 1)
29b0f896 3930 {
4eed87de
AM		 3931 as_bad (_("you can't `pop %%cs'"));
3932 return 0;
29b0f896 3933 }
4eed87de
AM		 3934 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3935 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 3936 i.rex |= REX_B;
4eed87de
AM		 3937 }
3938 else
3939 {
3940 /* The register or float register operand is in operand 0 or 1. */
40fb9820
L		 3941 unsigned int op;
3942
3943 if (i.types[0].bitfield.floatreg
3944 || operand_type_check (i.types[0], reg))
3945 op = 0;
3946 else
3947 op = 1;
4eed87de
AM		 3948 /* Register goes in low 3 bits of opcode. */
3949 i.tm.base_opcode |= i.op[op].regs->reg_num;
3950 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3951 i.rex |= REX_B;
40fb9820 3952 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 3953 {
4eed87de
AM		 3954 /* Warn about some common errors, but press on regardless.
3955 The first case can be generated by gcc (<= 2.8.1). */
3956 if (i.operands == 2)
3957 {
3958 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 3959 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
3960 register_prefix, i.op[1].regs->reg_name,
3961 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 3962 }
3963 else
3964 {
3965 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 3966 as_warn (_("translating to `%s %s%s'"), i.tm.name,
3967 register_prefix, i.op[0].regs->reg_name);
4eed87de 3968 }
29b0f896
AM		 3969 }
3970 }
3971 }
40fb9820 3972 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 3973 {
3974 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3975 must be put into the modrm byte). Now, we make the modrm and
3976 index base bytes based on all the info we've collected. */
29b0f896
AM		 3977
3978 default_seg = build_modrm_byte ();
3979 }
8a2ed489 3980 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 3981 {
3982 default_seg = &ds;
3983 }
40fb9820 3984 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 3985 {
3986 /* For the string instructions that allow a segment override
3987 on one of their operands, the default segment is ds. */
3988 default_seg = &ds;
3989 }
3990
75178d9d
L		 3991 if (i.tm.base_opcode == 0x8d /* lea */
3992 && i.seg[0]
3993 && !quiet_warnings)
30123838 3994 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3995
3996 /* If a segment was explicitly specified, and the specified segment
3997 is not the default, use an opcode prefix to select it. If we
3998 never figured out what the default segment is, then default_seg
3999 will be zero at this point, and the specified segment prefix will
4000 always be used. */
29b0f896
AM		 4001 if ((i.seg[0]) && (i.seg[0] != default_seg))
4002 {
4003 if (!add_prefix (i.seg[0]->seg_prefix))
4004 return 0;
4005 }
4006 return 1;
4007}
4008
4009static const seg_entry *
e3bb37b5 4010build_modrm_byte (void)
29b0f896
AM		 4011{
4012 const seg_entry *default_seg = 0;
4013
4014 /* i.reg_operands MUST be the number of real register operands;
4015 implicit registers do not count. */
4016 if (i.reg_operands == 2)
4017 {
4018 unsigned int source, dest;
cab737b9
L		 4019
4020 switch (i.operands)
4021 {
4022 case 2:
4023 source = 0;
4024 break;
4025 case 3:
c81128dc
L		 4026 /* When there are 3 operands, one of them may be immediate,
4027 which may be the first or the last operand. Otherwise,
4028 the first operand must be shift count register (cl). */
4029 assert (i.imm_operands == 1
4030 || (i.imm_operands == 0
40fb9820
L		 4031 && i.types[0].bitfield.shiftcount));
4032 if (operand_type_check (i.types[0], imm)
4033 || i.types[0].bitfield.shiftcount)
4034 source = 1;
4035 else
4036 source = 0;
cab737b9
L		 4037 break;
4038 case 4:
4039 /* When there are 4 operands, the first two must be immediate
4040 operands. The source operand will be the 3rd one. */
4041 assert (i.imm_operands == 2
40fb9820
L		 4042 && operand_type_check (i.types[0], imm)
4043 && operand_type_check (i.types[1], imm));
cab737b9
L		 4044 source = 2;
4045 break;
4046 default:
4047 abort ();
4048 }
4049
29b0f896
AM		 4050 dest = source + 1;
4051
4052 i.rm.mode = 3;
4053 /* One of the register operands will be encoded in the i.tm.reg
4054 field, the other in the combined i.tm.mode and i.tm.regmem
4055 fields. If no form of this instruction supports a memory
4056 destination operand, then we assume the source operand may
4057 sometimes be a memory operand and so we need to store the
4058 destination in the i.rm.reg field. */
40fb9820
L		 4059 if (!i.tm.operand_types[dest].bitfield.regmem
4060 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 4061 {
4062 i.rm.reg = i.op[dest].regs->reg_num;
4063 i.rm.regmem = i.op[source].regs->reg_num;
4064 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4065 i.rex |= REX_R;
29b0f896 4066 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4067 i.rex |= REX_B;
29b0f896
AM		 4068 }
4069 else
4070 {
4071 i.rm.reg = i.op[source].regs->reg_num;
4072 i.rm.regmem = i.op[dest].regs->reg_num;
4073 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4074 i.rex |= REX_B;
29b0f896 4075 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4076 i.rex |= REX_R;
29b0f896 4077 }
161a04f6 4078 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 4079 {
40fb9820
L		 4080 if (!i.types[0].bitfield.control
4081 && !i.types[1].bitfield.control)
c4a530c5 4082 abort ();
161a04f6 4083 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 4084 add_prefix (LOCK_PREFIX_OPCODE);
4085 }
29b0f896
AM		 4086 }
4087 else
4088 { /* If it's not 2 reg operands... */
4089 if (i.mem_operands)
4090 {
4091 unsigned int fake_zero_displacement = 0;
99018f42 4092 unsigned int op;
4eed87de 4093
99018f42 4094 for (op = 0; op < i.operands; op++)
40fb9820 4095 if (operand_type_check (i.types[op], anymem))
99018f42
L		 4096 break;
4097 assert (op < i.operands);
29b0f896
AM		 4098
4099 default_seg = &ds;
4100
4101 if (i.base_reg == 0)
4102 {
4103 i.rm.mode = 0;
4104 if (!i.disp_operands)
4105 fake_zero_displacement = 1;
4106 if (i.index_reg == 0)
4107 {
4108 /* Operand is just <disp> */
20f0a1fc 4109 if (flag_code == CODE_64BIT)
29b0f896
AM		 4110 {
4111 /* 64bit mode overwrites the 32bit absolute
4112 addressing by RIP relative addressing and
4113 absolute addressing is encoded by one of the
4114 redundant SIB forms. */
4115 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4116 i.sib.base = NO_BASE_REGISTER;
4117 i.sib.index = NO_INDEX_REGISTER;
fc225355 4118 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 4119 ? disp32s : disp32);
20f0a1fc 4120 }
fc225355
L		 4121 else if ((flag_code == CODE_16BIT)
4122 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 4123 {
4124 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 4125 i.types[op] = disp16;
20f0a1fc
NC		 4126 }
4127 else
4128 {
4129 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 4130 i.types[op] = disp32;
29b0f896
AM		 4131 }
4132 }
4133 else /* !i.base_reg && i.index_reg */
4134 {
4135 i.sib.index = i.index_reg->reg_num;
4136 i.sib.base = NO_BASE_REGISTER;
4137 i.sib.scale = i.log2_scale_factor;
4138 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 4139 i.types[op].bitfield.disp8 = 0;
4140 i.types[op].bitfield.disp16 = 0;
4141 i.types[op].bitfield.disp64 = 0;
29b0f896 4142 if (flag_code != CODE_64BIT)
40fb9820
L		 4143 {
4144 /* Must be 32 bit */
4145 i.types[op].bitfield.disp32 = 1;
4146 i.types[op].bitfield.disp32s = 0;
4147 }
29b0f896 4148 else
40fb9820
L		 4149 {
4150 i.types[op].bitfield.disp32 = 0;
4151 i.types[op].bitfield.disp32s = 1;
4152 }
29b0f896 4153 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4154 i.rex |= REX_X;
29b0f896
AM		 4155 }
4156 }
4157 /* RIP addressing for 64bit mode. */
c6fb90c8 4158 else if (UINTS_EQUAL (i.base_reg->reg_type, baseindex))
29b0f896
AM		 4159 {
4160 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 4161 i.types[op].bitfield.disp8 = 0;
4162 i.types[op].bitfield.disp16 = 0;
4163 i.types[op].bitfield.disp32 = 0;
4164 i.types[op].bitfield.disp32s = 1;
4165 i.types[op].bitfield.disp64 = 0;
71903a11 4166 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 4167 if (! i.disp_operands)
4168 fake_zero_displacement = 1;
29b0f896 4169 }
40fb9820 4170 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 4171 {
4172 switch (i.base_reg->reg_num)
4173 {
4174 case 3: /* (%bx) */
4175 if (i.index_reg == 0)
4176 i.rm.regmem = 7;
4177 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4178 i.rm.regmem = i.index_reg->reg_num - 6;
4179 break;
4180 case 5: /* (%bp) */
4181 default_seg = &ss;
4182 if (i.index_reg == 0)
4183 {
4184 i.rm.regmem = 6;
40fb9820 4185 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 4186 {
4187 /* fake (%bp) into 0(%bp) */
40fb9820 4188 i.types[op].bitfield.disp8 = 1;
252b5132 4189 fake_zero_displacement = 1;
29b0f896
AM		 4190 }
4191 }
4192 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4193 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4194 break;
4195 default: /* (%si) -> 4 or (%di) -> 5 */
4196 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4197 }
4198 i.rm.mode = mode_from_disp_size (i.types[op]);
4199 }
4200 else /* i.base_reg and 32/64 bit mode */
4201 {
4202 if (flag_code == CODE_64BIT
40fb9820
L		 4203 && operand_type_check (i.types[op], disp))
4204 {
4205 i386_operand_type temp;
c6fb90c8 4206 UINTS_CLEAR (temp);
40fb9820
L		 4207 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4208 i.types[op] = temp;
4209 if (i.prefix[ADDR_PREFIX] == 0)
4210 i.types[op].bitfield.disp32s = 1;
4211 else
4212 i.types[op].bitfield.disp32 = 1;
4213 }
20f0a1fc 4214
29b0f896
AM		 4215 i.rm.regmem = i.base_reg->reg_num;
4216 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 4217 i.rex |= REX_B;
29b0f896
AM		 4218 i.sib.base = i.base_reg->reg_num;
4219 /* x86-64 ignores REX prefix bit here to avoid decoder
4220 complications. */
4221 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4222 {
4223 default_seg = &ss;
4224 if (i.disp_operands == 0)
4225 {
4226 fake_zero_displacement = 1;
40fb9820 4227 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 4228 }
4229 }
4230 else if (i.base_reg->reg_num == ESP_REG_NUM)
4231 {
4232 default_seg = &ss;
4233 }
4234 i.sib.scale = i.log2_scale_factor;
4235 if (i.index_reg == 0)
4236 {
4237 /* <disp>(%esp) becomes two byte modrm with no index
4238 register. We've already stored the code for esp
4239 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4240 Any base register besides %esp will not use the
4241 extra modrm byte. */
4242 i.sib.index = NO_INDEX_REGISTER;
4243#if !SCALE1_WHEN_NO_INDEX
4244 /* Another case where we force the second modrm byte. */
4245 if (i.log2_scale_factor)
4246 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 4247#endif
29b0f896
AM		 4248 }
4249 else
4250 {
4251 i.sib.index = i.index_reg->reg_num;
4252 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4253 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4254 i.rex |= REX_X;
29b0f896 4255 }
67a4f2b7
AO		 4256
4257 if (i.disp_operands
4258 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4259 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4260 i.rm.mode = 0;
4261 else
4262 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 4263 }
252b5132 4264
29b0f896
AM		 4265 if (fake_zero_displacement)
4266 {
4267 /* Fakes a zero displacement assuming that i.types[op]
4268 holds the correct displacement size. */
4269 expressionS *exp;
4270
4271 assert (i.op[op].disps == 0);
4272 exp = &disp_expressions[i.disp_operands++];
4273 i.op[op].disps = exp;
4274 exp->X_op = O_constant;
4275 exp->X_add_number = 0;
4276 exp->X_add_symbol = (symbolS *) 0;
4277 exp->X_op_symbol = (symbolS *) 0;
4278 }
4279 }
252b5132 4280
29b0f896
AM		 4281 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4282 (if any) based on i.tm.extension_opcode. Again, we must be
4283 careful to make sure that segment/control/debug/test/MMX
4284 registers are coded into the i.rm.reg field. */
4285 if (i.reg_operands)
4286 {
99018f42
L		 4287 unsigned int op;
4288
4289 for (op = 0; op < i.operands; op++)
40fb9820
L		 4290 if (i.types[op].bitfield.reg8
4291 || i.types[op].bitfield.reg16
4292 || i.types[op].bitfield.reg32
4293 || i.types[op].bitfield.reg64
4294 || i.types[op].bitfield.regmmx
4295 || i.types[op].bitfield.regxmm
4296 || i.types[op].bitfield.sreg2
4297 || i.types[op].bitfield.sreg3
4298 || i.types[op].bitfield.control
4299 || i.types[op].bitfield.debug
4300 || i.types[op].bitfield.test)
99018f42
L		 4301 break;
4302 assert (op < i.operands);
4303
29b0f896
AM		 4304 /* If there is an extension opcode to put here, the register
4305 number must be put into the regmem field. */
4306 if (i.tm.extension_opcode != None)
4307 {
4308 i.rm.regmem = i.op[op].regs->reg_num;
4309 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4310 i.rex |= REX_B;
29b0f896
AM		 4311 }
4312 else
4313 {
4314 i.rm.reg = i.op[op].regs->reg_num;
4315 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4316 i.rex |= REX_R;
29b0f896 4317 }
252b5132 4318
29b0f896
AM		 4319 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4320 must set it to 3 to indicate this is a register operand
4321 in the regmem field. */
4322 if (!i.mem_operands)
4323 i.rm.mode = 3;
4324 }
252b5132 4325
29b0f896
AM		 4326 /* Fill in i.rm.reg field with extension opcode (if any). */
4327 if (i.tm.extension_opcode != None)
4328 i.rm.reg = i.tm.extension_opcode;
4329 }
4330 return default_seg;
4331}
252b5132 4332
29b0f896 4333static void
e3bb37b5 4334output_branch (void)
29b0f896
AM		 4335{
4336 char *p;
4337 int code16;
4338 int prefix;
4339 relax_substateT subtype;
4340 symbolS *sym;
4341 offsetT off;
4342
4343 code16 = 0;
4344 if (flag_code == CODE_16BIT)
4345 code16 = CODE16;
4346
4347 prefix = 0;
4348 if (i.prefix[DATA_PREFIX] != 0)
252b5132 4349 {
29b0f896
AM		 4350 prefix = 1;
4351 i.prefixes -= 1;
4352 code16 ^= CODE16;
252b5132 4353 }
29b0f896
AM		 4354 /* Pentium4 branch hints. */
4355 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4356 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 4357 {
29b0f896
AM		 4358 prefix++;
4359 i.prefixes--;
4360 }
4361 if (i.prefix[REX_PREFIX] != 0)
4362 {
4363 prefix++;
4364 i.prefixes--;
2f66722d
AM		 4365 }
4366
29b0f896
AM		 4367 if (i.prefixes != 0 && !intel_syntax)
4368 as_warn (_("skipping prefixes on this instruction"));
4369
4370 /* It's always a symbol; End frag & setup for relax.
4371 Make sure there is enough room in this frag for the largest
4372 instruction we may generate in md_convert_frag. This is 2
4373 bytes for the opcode and room for the prefix and largest
4374 displacement. */
4375 frag_grow (prefix + 2 + 4);
4376 /* Prefix and 1 opcode byte go in fr_fix. */
4377 p = frag_more (prefix + 1);
4378 if (i.prefix[DATA_PREFIX] != 0)
4379 *p++ = DATA_PREFIX_OPCODE;
4380 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
4381 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
4382 *p++ = i.prefix[SEG_PREFIX];
4383 if (i.prefix[REX_PREFIX] != 0)
4384 *p++ = i.prefix[REX_PREFIX];
4385 *p = i.tm.base_opcode;
4386
4387 if ((unsigned char) *p == JUMP_PC_RELATIVE)
4388 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 4389 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 4390 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
4391 else
4392 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
4393 subtype |= code16;
3e73aa7c 4394
29b0f896
AM		 4395 sym = i.op[0].disps->X_add_symbol;
4396 off = i.op[0].disps->X_add_number;
3e73aa7c 4397
29b0f896
AM		 4398 if (i.op[0].disps->X_op != O_constant
4399 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 4400 {
29b0f896
AM		 4401 /* Handle complex expressions. */
4402 sym = make_expr_symbol (i.op[0].disps);
4403 off = 0;
4404 }
3e73aa7c 4405
29b0f896
AM		 4406 /* 1 possible extra opcode + 4 byte displacement go in var part.
4407 Pass reloc in fr_var. */
4408 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
4409}
3e73aa7c 4410
29b0f896 4411static void
e3bb37b5 4412output_jump (void)
29b0f896
AM		 4413{
4414 char *p;
4415 int size;
3e02c1cc 4416 fixS *fixP;
29b0f896 4417
40fb9820 4418 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 4419 {
4420 /* This is a loop or jecxz type instruction. */
4421 size = 1;
4422 if (i.prefix[ADDR_PREFIX] != 0)
4423 {
4424 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
4425 i.prefixes -= 1;
4426 }
4427 /* Pentium4 branch hints. */
4428 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4429 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4430 {
4431 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
4432 i.prefixes--;
3e73aa7c
JH		 4433 }
4434 }
29b0f896
AM		 4435 else
4436 {
4437 int code16;
3e73aa7c 4438
29b0f896
AM		 4439 code16 = 0;
4440 if (flag_code == CODE_16BIT)
4441 code16 = CODE16;
3e73aa7c 4442
29b0f896
AM		 4443 if (i.prefix[DATA_PREFIX] != 0)
4444 {
4445 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
4446 i.prefixes -= 1;
4447 code16 ^= CODE16;
4448 }
252b5132 4449
29b0f896
AM		 4450 size = 4;
4451 if (code16)
4452 size = 2;
4453 }
9fcc94b6 4454
29b0f896
AM		 4455 if (i.prefix[REX_PREFIX] != 0)
4456 {
4457 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
4458 i.prefixes -= 1;
4459 }
252b5132 4460
29b0f896
AM		 4461 if (i.prefixes != 0 && !intel_syntax)
4462 as_warn (_("skipping prefixes on this instruction"));
e0890092 4463
29b0f896
AM		 4464 p = frag_more (1 + size);
4465 *p++ = i.tm.base_opcode;
e0890092 4466
3e02c1cc
AM		 4467 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4468 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
4469
4470 /* All jumps handled here are signed, but don't use a signed limit
4471 check for 32 and 16 bit jumps as we want to allow wrap around at
4472 4G and 64k respectively. */
4473 if (size == 1)
4474 fixP->fx_signed = 1;
29b0f896 4475}
e0890092 4476
29b0f896 4477static void
e3bb37b5 4478output_interseg_jump (void)
29b0f896
AM		 4479{
4480 char *p;
4481 int size;
4482 int prefix;
4483 int code16;
252b5132 4484
29b0f896
AM		 4485 code16 = 0;
4486 if (flag_code == CODE_16BIT)
4487 code16 = CODE16;
a217f122 4488
29b0f896
AM		 4489 prefix = 0;
4490 if (i.prefix[DATA_PREFIX] != 0)
4491 {
4492 prefix = 1;
4493 i.prefixes -= 1;
4494 code16 ^= CODE16;
4495 }
4496 if (i.prefix[REX_PREFIX] != 0)
4497 {
4498 prefix++;
4499 i.prefixes -= 1;
4500 }
252b5132 4501
29b0f896
AM		 4502 size = 4;
4503 if (code16)
4504 size = 2;
252b5132 4505
29b0f896
AM		 4506 if (i.prefixes != 0 && !intel_syntax)
4507 as_warn (_("skipping prefixes on this instruction"));
252b5132 4508
29b0f896
AM		 4509 /* 1 opcode; 2 segment; offset */
4510 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 4511
29b0f896
AM		 4512 if (i.prefix[DATA_PREFIX] != 0)
4513 *p++ = DATA_PREFIX_OPCODE;
252b5132 4514
29b0f896
AM		 4515 if (i.prefix[REX_PREFIX] != 0)
4516 *p++ = i.prefix[REX_PREFIX];
252b5132 4517
29b0f896
AM		 4518 *p++ = i.tm.base_opcode;
4519 if (i.op[1].imms->X_op == O_constant)
4520 {
4521 offsetT n = i.op[1].imms->X_add_number;
252b5132 4522
29b0f896
AM		 4523 if (size == 2
4524 && !fits_in_unsigned_word (n)
4525 && !fits_in_signed_word (n))
4526 {
4527 as_bad (_("16-bit jump out of range"));
4528 return;
4529 }
4530 md_number_to_chars (p, n, size);
4531 }
4532 else
4533 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4534 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
4535 if (i.op[0].imms->X_op != O_constant)
4536 as_bad (_("can't handle non absolute segment in `%s'"),
4537 i.tm.name);
4538 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
4539}
a217f122 4540
29b0f896 4541static void
e3bb37b5 4542output_insn (void)
29b0f896 4543{
2bbd9c25
JJ		 4544 fragS *insn_start_frag;
4545 offsetT insn_start_off;
4546
29b0f896
AM		 4547 /* Tie dwarf2 debug info to the address at the start of the insn.
4548 We can't do this after the insn has been output as the current
4549 frag may have been closed off. eg. by frag_var. */
4550 dwarf2_emit_insn (0);
4551
2bbd9c25
JJ		 4552 insn_start_frag = frag_now;
4553 insn_start_off = frag_now_fix ();
4554
29b0f896 4555 /* Output jumps. */
40fb9820 4556 if (i.tm.opcode_modifier.jump)
29b0f896 4557 output_branch ();
40fb9820
L		 4558 else if (i.tm.opcode_modifier.jumpbyte
4559 || i.tm.opcode_modifier.jumpdword)
29b0f896 4560 output_jump ();
40fb9820 4561 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 4562 output_interseg_jump ();
4563 else
4564 {
4565 /* Output normal instructions here. */
4566 char *p;
4567 unsigned char *q;
331d2d0d 4568 unsigned int prefix;
40fb9820 4569 int opc_3b;
252b5132 4570
42903f7f 4571 /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and
381d071f
L		 4572 SSE4 instructions have 3 bytes. We may use one more higher
4573 byte to specify a prefix the instruction requires. Exclude
cf557b51
L		 4574 instructions which are in both SSE4.2 and ABM. */
4575 opc_3b = (i.tm.cpu_flags.bitfield.cpussse3
4576 || i.tm.cpu_flags.bitfield.cpusse4_1
4577 || (i.tm.cpu_flags.bitfield.cpusse4_2
4578 && !i.tm.cpu_flags.bitfield.cpuabm));
40fb9820 4579 if (opc_3b)
bc4bd9ab 4580 {
331d2d0d
L		 4581 if (i.tm.base_opcode & 0xff000000)
4582 {
4583 prefix = (i.tm.base_opcode >> 24) & 0xff;
4584 goto check_prefix;
4585 }
4586 }
4587 else if ((i.tm.base_opcode & 0xff0000) != 0)
4588 {
4589 prefix = (i.tm.base_opcode >> 16) & 0xff;
40fb9820 4590 if (i.tm.cpu_flags.bitfield.cpupadlock)
bc4bd9ab 4591 {
64e74474 4592 check_prefix:
bc4bd9ab
MK		 4593 if (prefix != REPE_PREFIX_OPCODE
4594 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
4595 add_prefix (prefix);
4596 }
4597 else
331d2d0d 4598 add_prefix (prefix);
0f10071e 4599 }
252b5132 4600
29b0f896
AM		 4601 /* The prefix bytes. */
4602 for (q = i.prefix;
4603 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
4604 q++)
4605 {
4606 if (*q)
4607 {
4608 p = frag_more (1);
4609 md_number_to_chars (p, (valueT) *q, 1);
4610 }
4611 }
252b5132 4612
29b0f896
AM		 4613 /* Now the opcode; be careful about word order here! */
4614 if (fits_in_unsigned_byte (i.tm.base_opcode))
4615 {
4616 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
4617 }
4618 else
4619 {
40fb9820 4620 if (opc_3b)
331d2d0d
L		 4621 {
4622 p = frag_more (3);
4623 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4624 }
4625 else
4626 p = frag_more (2);
0f10071e 4627
29b0f896
AM		 4628 /* Put out high byte first: can't use md_number_to_chars! */
4629 *p++ = (i.tm.base_opcode >> 8) & 0xff;
4630 *p = i.tm.base_opcode & 0xff;
4631 }
3e73aa7c 4632
29b0f896 4633 /* Now the modrm byte and sib byte (if present). */
40fb9820 4634 if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4635 {
4636 p = frag_more (1);
4637 md_number_to_chars (p,
4638 (valueT) (i.rm.regmem << 0
4639 | i.rm.reg << 3
4640 | i.rm.mode << 6),
4641 1);
4642 /* If i.rm.regmem == ESP (4)
4643 && i.rm.mode != (Register mode)
4644 && not 16 bit
4645 ==> need second modrm byte. */
4646 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
4647 && i.rm.mode != 3
40fb9820 4648 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
29b0f896
AM		 4649 {
4650 p = frag_more (1);
4651 md_number_to_chars (p,
4652 (valueT) (i.sib.base << 0
4653 | i.sib.index << 3
4654 | i.sib.scale << 6),
4655 1);
4656 }
4657 }
3e73aa7c 4658
29b0f896 4659 if (i.disp_operands)
2bbd9c25 4660 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 4661
29b0f896 4662 if (i.imm_operands)
2bbd9c25 4663 output_imm (insn_start_frag, insn_start_off);
29b0f896 4664 }
252b5132 4665
29b0f896
AM		 4666#ifdef DEBUG386
4667 if (flag_debug)
4668 {
7b81dfbb 4669 pi ("" /*line*/, &i);
29b0f896
AM		 4670 }
4671#endif /* DEBUG386 */
4672}
252b5132 4673
e205caa7
L		 4674/* Return the size of the displacement operand N. */
4675
4676static int
4677disp_size (unsigned int n)
4678{
4679 int size = 4;
40fb9820
L		 4680 if (i.types[n].bitfield.disp64)
4681 size = 8;
4682 else if (i.types[n].bitfield.disp8)
4683 size = 1;
4684 else if (i.types[n].bitfield.disp16)
4685 size = 2;
e205caa7
L		 4686 return size;
4687}
4688
4689/* Return the size of the immediate operand N. */
4690
4691static int
4692imm_size (unsigned int n)
4693{
4694 int size = 4;
40fb9820
L		 4695 if (i.types[n].bitfield.imm64)
4696 size = 8;
4697 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
4698 size = 1;
4699 else if (i.types[n].bitfield.imm16)
4700 size = 2;
e205caa7
L		 4701 return size;
4702}
4703
29b0f896 4704static void
64e74474 4705output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4706{
4707 char *p;
4708 unsigned int n;
252b5132 4709
29b0f896
AM		 4710 for (n = 0; n < i.operands; n++)
4711 {
40fb9820 4712 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 4713 {
4714 if (i.op[n].disps->X_op == O_constant)
4715 {
e205caa7 4716 int size = disp_size (n);
29b0f896 4717 offsetT val;
252b5132 4718
29b0f896
AM		 4719 val = offset_in_range (i.op[n].disps->X_add_number,
4720 size);
4721 p = frag_more (size);
4722 md_number_to_chars (p, val, size);
4723 }
4724 else
4725 {
f86103b7 4726 enum bfd_reloc_code_real reloc_type;
e205caa7 4727 int size = disp_size (n);
40fb9820 4728 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 4729 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4730
e205caa7 4731 /* We can't have 8 bit displacement here. */
40fb9820 4732 assert (!i.types[n].bitfield.disp8);
e205caa7 4733
29b0f896
AM		 4734 /* The PC relative address is computed relative
4735 to the instruction boundary, so in case immediate
4736 fields follows, we need to adjust the value. */
4737 if (pcrel && i.imm_operands)
4738 {
29b0f896 4739 unsigned int n1;
e205caa7 4740 int sz = 0;
252b5132 4741
29b0f896 4742 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 4743 if (operand_type_check (i.types[n1], imm))
252b5132 4744 {
e205caa7
L		 4745 /* Only one immediate is allowed for PC
4746 relative address. */
4747 assert (sz == 0);
4748 sz = imm_size (n1);
4749 i.op[n].disps->X_add_number -= sz;
252b5132 4750 }
29b0f896 4751 /* We should find the immediate. */
e205caa7 4752 assert (sz != 0);
29b0f896 4753 }
520dc8e8 4754
29b0f896 4755 p = frag_more (size);
2bbd9c25 4756 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4757 if (GOT_symbol
2bbd9c25 4758 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4759 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4760 || reloc_type == BFD_RELOC_X86_64_32S
4761 || (reloc_type == BFD_RELOC_64
4762 && object_64bit))
d6ab8113
JB		 4763 && (i.op[n].disps->X_op == O_symbol
4764 || (i.op[n].disps->X_op == O_add
4765 && ((symbol_get_value_expression
4766 (i.op[n].disps->X_op_symbol)->X_op)
4767 == O_subtract))))
4768 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4769 {
4770 offsetT add;
4771
4772 if (insn_start_frag == frag_now)
4773 add = (p - frag_now->fr_literal) - insn_start_off;
4774 else
4775 {
4776 fragS *fr;
4777
4778 add = insn_start_frag->fr_fix - insn_start_off;
4779 for (fr = insn_start_frag->fr_next;
4780 fr && fr != frag_now; fr = fr->fr_next)
4781 add += fr->fr_fix;
4782 add += p - frag_now->fr_literal;
4783 }
4784
4fa24527 4785 if (!object_64bit)
7b81dfbb
AJ		 4786 {
4787 reloc_type = BFD_RELOC_386_GOTPC;
4788 i.op[n].imms->X_add_number += add;
4789 }
4790 else if (reloc_type == BFD_RELOC_64)
4791 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4792 else
7b81dfbb
AJ		 4793 /* Don't do the adjustment for x86-64, as there
4794 the pcrel addressing is relative to the _next_
4795 insn, and that is taken care of in other code. */
d6ab8113 4796 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4797 }
062cd5e7 4798 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4799 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4800 }
4801 }
4802 }
4803}
252b5132 4804
29b0f896 4805static void
64e74474 4806output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4807{
4808 char *p;
4809 unsigned int n;
252b5132 4810
29b0f896
AM		 4811 for (n = 0; n < i.operands; n++)
4812 {
40fb9820 4813 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 4814 {
4815 if (i.op[n].imms->X_op == O_constant)
4816 {
e205caa7 4817 int size = imm_size (n);
29b0f896 4818 offsetT val;
b4cac588 4819
29b0f896
AM		 4820 val = offset_in_range (i.op[n].imms->X_add_number,
4821 size);
4822 p = frag_more (size);
4823 md_number_to_chars (p, val, size);
4824 }
4825 else
4826 {
4827 /* Not absolute_section.
4828 Need a 32-bit fixup (don't support 8bit
4829 non-absolute imms). Try to support other
4830 sizes ... */
f86103b7 4831 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 4832 int size = imm_size (n);
4833 int sign;
29b0f896 4834
40fb9820 4835 if (i.types[n].bitfield.imm32s
a7d61044 4836 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 4837 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 4838 sign = 1;
e205caa7
L		 4839 else
4840 sign = 0;
520dc8e8 4841
29b0f896
AM		 4842 p = frag_more (size);
4843 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4844
2bbd9c25
JJ		 4845 /* This is tough to explain. We end up with this one if we
4846 * have operands that look like
4847 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4848 * obtain the absolute address of the GOT, and it is strongly
4849 * preferable from a performance point of view to avoid using
4850 * a runtime relocation for this. The actual sequence of
4851 * instructions often look something like:
4852 *
4853 * call .L66
4854 * .L66:
4855 * popl %ebx
4856 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4857 *
4858 * The call and pop essentially return the absolute address
4859 * of the label .L66 and store it in %ebx. The linker itself
4860 * will ultimately change the first operand of the addl so
4861 * that %ebx points to the GOT, but to keep things simple, the
4862 * .o file must have this operand set so that it generates not
4863 * the absolute address of .L66, but the absolute address of
4864 * itself. This allows the linker itself simply treat a GOTPC
4865 * relocation as asking for a pcrel offset to the GOT to be
4866 * added in, and the addend of the relocation is stored in the
4867 * operand field for the instruction itself.
4868 *
4869 * Our job here is to fix the operand so that it would add
4870 * the correct offset so that %ebx would point to itself. The
4871 * thing that is tricky is that .-.L66 will point to the
4872 * beginning of the instruction, so we need to further modify
4873 * the operand so that it will point to itself. There are
4874 * other cases where you have something like:
4875 *
4876 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4877 *
4878 * and here no correction would be required. Internally in
4879 * the assembler we treat operands of this form as not being
4880 * pcrel since the '.' is explicitly mentioned, and I wonder
4881 * whether it would simplify matters to do it this way. Who
4882 * knows. In earlier versions of the PIC patches, the
4883 * pcrel_adjust field was used to store the correction, but
4884 * since the expression is not pcrel, I felt it would be
4885 * confusing to do it this way. */
4886
d6ab8113 4887 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4888 || reloc_type == BFD_RELOC_X86_64_32S
4889 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4890 && GOT_symbol
4891 && GOT_symbol == i.op[n].imms->X_add_symbol
4892 && (i.op[n].imms->X_op == O_symbol
4893 || (i.op[n].imms->X_op == O_add
4894 && ((symbol_get_value_expression
4895 (i.op[n].imms->X_op_symbol)->X_op)
4896 == O_subtract))))
4897 {
2bbd9c25
JJ		 4898 offsetT add;
4899
4900 if (insn_start_frag == frag_now)
4901 add = (p - frag_now->fr_literal) - insn_start_off;
4902 else
4903 {
4904 fragS *fr;
4905
4906 add = insn_start_frag->fr_fix - insn_start_off;
4907 for (fr = insn_start_frag->fr_next;
4908 fr && fr != frag_now; fr = fr->fr_next)
4909 add += fr->fr_fix;
4910 add += p - frag_now->fr_literal;
4911 }
4912
4fa24527 4913 if (!object_64bit)
d6ab8113 4914 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4915 else if (size == 4)
d6ab8113 4916 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4917 else if (size == 8)
4918 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4919 i.op[n].imms->X_add_number += add;
29b0f896 4920 }
29b0f896
AM		 4921 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4922 i.op[n].imms, 0, reloc_type);
4923 }
4924 }
4925 }
252b5132
RH		 4926}
4927\f
d182319b
JB		 4928/* x86_cons_fix_new is called via the expression parsing code when a
4929 reloc is needed. We use this hook to get the correct .got reloc. */
4930static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4931static int cons_sign = -1;
4932
4933void
e3bb37b5 4934x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 4935 expressionS *exp)
d182319b
JB		 4936{
4937 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4938
4939 got_reloc = NO_RELOC;
4940
4941#ifdef TE_PE
4942 if (exp->X_op == O_secrel)
4943 {
4944 exp->X_op = O_symbol;
4945 r = BFD_RELOC_32_SECREL;
4946 }
4947#endif
4948
4949 fix_new_exp (frag, off, len, exp, 0, r);
4950}
4951
718ddfc0
JB		 4952#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4953# define lex_got(reloc, adjust, types) NULL
4954#else
f3c180ae
AM		 4955/* Parse operands of the form
4956 <symbol>@GOTOFF+<nnn>
4957 and similar .plt or .got references.
4958
4959 If we find one, set up the correct relocation in RELOC and copy the
4960 input string, minus the `@GOTOFF' into a malloc'd buffer for
4961 parsing by the calling routine. Return this buffer, and if ADJUST
4962 is non-null set it to the length of the string we removed from the
4963 input line. Otherwise return NULL. */
4964static char *
3956db08 4965lex_got (enum bfd_reloc_code_real *reloc,
64e74474 4966 int *adjust,
40fb9820 4967 i386_operand_type *types)
f3c180ae 4968{
7b81dfbb
AJ		 4969 /* Some of the relocations depend on the size of what field is to
4970 be relocated. But in our callers i386_immediate and i386_displacement
4971 we don't yet know the operand size (this will be set by insn
4972 matching). Hence we record the word32 relocation here,
4973 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4974 static const struct {
4975 const char *str;
4fa24527 4976 const enum bfd_reloc_code_real rel[2];
40fb9820 4977 const i386_operand_type types64;
f3c180ae 4978 } gotrel[] = {
4eed87de
AM		 4979 { "PLTOFF", { 0,
4980 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 4981 OPERAND_TYPE_IMM64 },
4eed87de
AM		 4982 { "PLT", { BFD_RELOC_386_PLT32,
4983 BFD_RELOC_X86_64_PLT32 },
40fb9820 4984 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 4985 { "GOTPLT", { 0,
4986 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 4987 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 4988 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
4989 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 4990 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 4991 { "GOTPCREL", { 0,
4992 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 4993 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 4994 { "TLSGD", { BFD_RELOC_386_TLS_GD,
4995 BFD_RELOC_X86_64_TLSGD },
40fb9820 4996 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 4997 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
4998 0 },
40fb9820 4999 OPERAND_TYPE_NONE },
4eed87de
AM		 5000 { "TLSLD", { 0,
5001 BFD_RELOC_X86_64_TLSLD },
40fb9820 5002 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5003 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5004 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 5005 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5006 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5007 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 5008 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5009 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5010 0 },
40fb9820 5011 OPERAND_TYPE_NONE },
4eed87de
AM		 5012 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5013 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 5014
5015 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5016 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5017 0 },
40fb9820 5018 OPERAND_TYPE_NONE },
4eed87de
AM		 5019 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5020 0 },
40fb9820 5021 OPERAND_TYPE_NONE },
4eed87de
AM		 5022 { "GOT", { BFD_RELOC_386_GOT32,
5023 BFD_RELOC_X86_64_GOT32 },
40fb9820 5024 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 5025 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5026 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 5027 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5028 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5029 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 5030 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 5031 };
5032 char *cp;
5033 unsigned int j;
5034
718ddfc0
JB		 5035 if (!IS_ELF)
5036 return NULL;
5037
f3c180ae 5038 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 5039 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 5040 return NULL;
5041
5042 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
5043 {
5044 int len;
5045
5046 len = strlen (gotrel[j].str);
28f81592 5047 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 5048 {
4fa24527 5049 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 5050 {
28f81592
AM		 5051 int first, second;
5052 char *tmpbuf, *past_reloc;
f3c180ae 5053
4fa24527 5054 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 5055 if (adjust)
5056 *adjust = len;
f3c180ae 5057
3956db08
JB		 5058 if (types)
5059 {
5060 if (flag_code != CODE_64BIT)
40fb9820
L		 5061 {
5062 types->bitfield.imm32 = 1;
5063 types->bitfield.disp32 = 1;
5064 }
3956db08
JB		 5065 else
5066 *types = gotrel[j].types64;
5067 }
5068
f3c180ae
AM		 5069 if (GOT_symbol == NULL)
5070 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5071
28f81592 5072 /* The length of the first part of our input line. */
f3c180ae 5073 first = cp - input_line_pointer;
28f81592
AM		 5074
5075 /* The second part goes from after the reloc token until
67c11a9b 5076 (and including) an end_of_line char or comma. */
28f81592 5077 past_reloc = cp + 1 + len;
67c11a9b
AM		 5078 cp = past_reloc;
5079 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5080 ++cp;
5081 second = cp + 1 - past_reloc;
28f81592
AM		 5082
5083 /* Allocate and copy string. The trailing NUL shouldn't
5084 be necessary, but be safe. */
5085 tmpbuf = xmalloc (first + second + 2);
f3c180ae 5086 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 5087 if (second != 0 && *past_reloc != ' ')
5088 /* Replace the relocation token with ' ', so that
5089 errors like foo@GOTOFF1 will be detected. */
5090 tmpbuf[first++] = ' ';
5091 memcpy (tmpbuf + first, past_reloc, second);
5092 tmpbuf[first + second] = '\0';
f3c180ae
AM		 5093 return tmpbuf;
5094 }
5095
4fa24527
JB		 5096 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5097 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 5098 return NULL;
5099 }
5100 }
5101
5102 /* Might be a symbol version string. Don't as_bad here. */
5103 return NULL;
5104}
5105
f3c180ae 5106void
e3bb37b5 5107x86_cons (expressionS *exp, int size)
f3c180ae 5108{
4fa24527 5109 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 5110 {
5111 /* Handle @GOTOFF and the like in an expression. */
5112 char *save;
5113 char *gotfree_input_line;
5114 int adjust;
5115
5116 save = input_line_pointer;
3956db08 5117 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 5118 if (gotfree_input_line)
5119 input_line_pointer = gotfree_input_line;
5120
5121 expression (exp);
5122
5123 if (gotfree_input_line)
5124 {
5125 /* expression () has merrily parsed up to the end of line,
5126 or a comma - in the wrong buffer. Transfer how far
5127 input_line_pointer has moved to the right buffer. */
5128 input_line_pointer = (save
5129 + (input_line_pointer - gotfree_input_line)
5130 + adjust);
5131 free (gotfree_input_line);
3992d3b7
AM		 5132 if (exp->X_op == O_constant
5133 || exp->X_op == O_absent
5134 || exp->X_op == O_illegal
5135 || exp->X_op == O_register
5136 || exp->X_op == O_big)
5137 {
5138 char c = *input_line_pointer;
5139 *input_line_pointer = 0;
5140 as_bad (_("missing or invalid expression `%s'"), save);
5141 *input_line_pointer = c;
5142 }
f3c180ae
AM		 5143 }
5144 }
5145 else
5146 expression (exp);
5147}
5148#endif
5149
d182319b 5150static void signed_cons (int size)
6482c264 5151{
d182319b
JB		 5152 if (flag_code == CODE_64BIT)
5153 cons_sign = 1;
5154 cons (size);
5155 cons_sign = -1;
6482c264
NC		 5156}
5157
d182319b 5158#ifdef TE_PE
6482c264
NC		 5159static void
5160pe_directive_secrel (dummy)
5161 int dummy ATTRIBUTE_UNUSED;
5162{
5163 expressionS exp;
5164
5165 do
5166 {
5167 expression (&exp);
5168 if (exp.X_op == O_symbol)
5169 exp.X_op = O_secrel;
5170
5171 emit_expr (&exp, 4);
5172 }
5173 while (*input_line_pointer++ == ',');
5174
5175 input_line_pointer--;
5176 demand_empty_rest_of_line ();
5177}
6482c264
NC		 5178#endif
5179
252b5132 5180static int
70e41ade 5181i386_immediate (char *imm_start)
252b5132
RH		 5182{
5183 char *save_input_line_pointer;
f3c180ae 5184 char *gotfree_input_line;
252b5132 5185 segT exp_seg = 0;
47926f60 5186 expressionS *exp;
40fb9820
L		 5187 i386_operand_type types;
5188
c6fb90c8 5189 UINTS_SET (types, ~0);
252b5132
RH		 5190
5191 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5192 {
31b2323c
L		 5193 as_bad (_("at most %d immediate operands are allowed"),
5194 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 5195 return 0;
5196 }
5197
5198 exp = &im_expressions[i.imm_operands++];
520dc8e8 5199 i.op[this_operand].imms = exp;
252b5132
RH		 5200
5201 if (is_space_char (*imm_start))
5202 ++imm_start;
5203
5204 save_input_line_pointer = input_line_pointer;
5205 input_line_pointer = imm_start;
5206
3956db08 5207 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5208 if (gotfree_input_line)
5209 input_line_pointer = gotfree_input_line;
252b5132
RH		 5210
5211 exp_seg = expression (exp);
5212
83183c0c 5213 SKIP_WHITESPACE ();
252b5132 5214 if (*input_line_pointer)
f3c180ae 5215 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 5216
5217 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 5218 if (gotfree_input_line)
5219 free (gotfree_input_line);
252b5132 5220
3992d3b7
AM		 5221 if (exp->X_op == O_absent
5222 || exp->X_op == O_illegal
5223 || exp->X_op == O_big
5224 || (gotfree_input_line
5225 && (exp->X_op == O_constant
5226 || exp->X_op == O_register)))
252b5132 5227 {
3992d3b7 5228 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 5229 imm_start);
3992d3b7 5230 return 0;
252b5132 5231 }
3e73aa7c 5232 else if (exp->X_op == O_constant)
252b5132 5233 {
47926f60 5234 /* Size it properly later. */
40fb9820 5235 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 5236 /* If BFD64, sign extend val. */
4eed87de
AM		 5237 if (!use_rela_relocations
5238 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5239 exp->X_add_number
5240 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 5241 }
4c63da97 5242#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 5243 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 5244 && exp_seg != absolute_section
47926f60 5245 && exp_seg != text_section
24eab124
AM		 5246 && exp_seg != data_section
5247 && exp_seg != bss_section
5248 && exp_seg != undefined_section
f86103b7 5249 && !bfd_is_com_section (exp_seg))
252b5132 5250 {
d0b47220 5251 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 5252 return 0;
5253 }
5254#endif
bb8f5920
L		 5255 else if (!intel_syntax && exp->X_op == O_register)
5256 {
5257 as_bad (_("illegal immediate register operand %s"), imm_start);
5258 return 0;
5259 }
252b5132
RH		 5260 else
5261 {
5262 /* This is an address. The size of the address will be
24eab124 5263 determined later, depending on destination register,
3e73aa7c 5264 suffix, or the default for the section. */
40fb9820
L		 5265 i.types[this_operand].bitfield.imm8 = 1;
5266 i.types[this_operand].bitfield.imm16 = 1;
5267 i.types[this_operand].bitfield.imm32 = 1;
5268 i.types[this_operand].bitfield.imm32s = 1;
5269 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 5270 i.types[this_operand] = operand_type_and (i.types[this_operand],
5271 types);
252b5132
RH		 5272 }
5273
5274 return 1;
5275}
5276
551c1ca1 5277static char *
e3bb37b5 5278i386_scale (char *scale)
252b5132 5279{
551c1ca1
AM		 5280 offsetT val;
5281 char *save = input_line_pointer;
252b5132 5282
551c1ca1
AM		 5283 input_line_pointer = scale;
5284 val = get_absolute_expression ();
5285
5286 switch (val)
252b5132 5287 {
551c1ca1 5288 case 1:
252b5132
RH		 5289 i.log2_scale_factor = 0;
5290 break;
551c1ca1 5291 case 2:
252b5132
RH		 5292 i.log2_scale_factor = 1;
5293 break;
551c1ca1 5294 case 4:
252b5132
RH		 5295 i.log2_scale_factor = 2;
5296 break;
551c1ca1 5297 case 8:
252b5132
RH		 5298 i.log2_scale_factor = 3;
5299 break;
5300 default:
a724f0f4
JB		 5301 {
5302 char sep = *input_line_pointer;
5303
5304 *input_line_pointer = '\0';
5305 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5306 scale);
5307 *input_line_pointer = sep;
5308 input_line_pointer = save;
5309 return NULL;
5310 }
252b5132 5311 }
29b0f896 5312 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 5313 {
5314 as_warn (_("scale factor of %d without an index register"),
24eab124 5315 1 << i.log2_scale_factor);
252b5132
RH		 5316#if SCALE1_WHEN_NO_INDEX
5317 i.log2_scale_factor = 0;
5318#endif
5319 }
551c1ca1
AM		 5320 scale = input_line_pointer;
5321 input_line_pointer = save;
5322 return scale;
252b5132
RH		 5323}
5324
252b5132 5325static int
e3bb37b5 5326i386_displacement (char *disp_start, char *disp_end)
252b5132 5327{
29b0f896 5328 expressionS *exp;
252b5132
RH		 5329 segT exp_seg = 0;
5330 char *save_input_line_pointer;
f3c180ae 5331 char *gotfree_input_line;
40fb9820
L		 5332 int override;
5333 i386_operand_type bigdisp, types = anydisp;
3992d3b7 5334 int ret;
252b5132 5335
31b2323c
L		 5336 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5337 {
5338 as_bad (_("at most %d displacement operands are allowed"),
5339 MAX_MEMORY_OPERANDS);
5340 return 0;
5341 }
5342
c6fb90c8 5343 UINTS_CLEAR (bigdisp);
40fb9820
L		 5344 if ((i.types[this_operand].bitfield.jumpabsolute)
5345 || (!current_templates->start->opcode_modifier.jump
5346 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 5347 {
40fb9820 5348 bigdisp.bitfield.disp32 = 1;
e05278af 5349 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 5350 if (flag_code == CODE_64BIT)
5351 {
5352 if (!override)
5353 {
5354 bigdisp.bitfield.disp32s = 1;
5355 bigdisp.bitfield.disp64 = 1;
5356 }
5357 }
5358 else if ((flag_code == CODE_16BIT) ^ override)
5359 {
5360 bigdisp.bitfield.disp32 = 0;
5361 bigdisp.bitfield.disp16 = 1;
5362 }
e05278af
JB		 5363 }
5364 else
5365 {
5366 /* For PC-relative branches, the width of the displacement
5367 is dependent upon data size, not address size. */
e05278af 5368 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 5369 if (flag_code == CODE_64BIT)
5370 {
5371 if (override || i.suffix == WORD_MNEM_SUFFIX)
5372 bigdisp.bitfield.disp16 = 1;
5373 else
5374 {
5375 bigdisp.bitfield.disp32 = 1;
5376 bigdisp.bitfield.disp32s = 1;
5377 }
5378 }
5379 else
e05278af
JB		 5380 {
5381 if (!override)
5382 override = (i.suffix == (flag_code != CODE_16BIT
5383 ? WORD_MNEM_SUFFIX
5384 : LONG_MNEM_SUFFIX));
40fb9820
L		 5385 bigdisp.bitfield.disp32 = 1;
5386 if ((flag_code == CODE_16BIT) ^ override)
5387 {
5388 bigdisp.bitfield.disp32 = 0;
5389 bigdisp.bitfield.disp16 = 1;
5390 }
e05278af 5391 }
e05278af 5392 }
c6fb90c8
L		 5393 i.types[this_operand] = operand_type_or (i.types[this_operand],
5394 bigdisp);
252b5132
RH		 5395
5396 exp = &disp_expressions[i.disp_operands];
520dc8e8 5397 i.op[this_operand].disps = exp;
252b5132
RH		 5398 i.disp_operands++;
5399 save_input_line_pointer = input_line_pointer;
5400 input_line_pointer = disp_start;
5401 END_STRING_AND_SAVE (disp_end);
5402
5403#ifndef GCC_ASM_O_HACK
5404#define GCC_ASM_O_HACK 0
5405#endif
5406#if GCC_ASM_O_HACK
5407 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 5408 if (i.types[this_operand].bitfield.baseIndex
24eab124 5409 && displacement_string_end[-1] == '+')
252b5132
RH		 5410 {
5411 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 5412 constraint within gcc asm statements.
5413 For instance:
5414
5415 #define _set_tssldt_desc(n,addr,limit,type) \
5416 __asm__ __volatile__ ( \
5417 "movw %w2,%0\n\t" \
5418 "movw %w1,2+%0\n\t" \
5419 "rorl $16,%1\n\t" \
5420 "movb %b1,4+%0\n\t" \
5421 "movb %4,5+%0\n\t" \
5422 "movb $0,6+%0\n\t" \
5423 "movb %h1,7+%0\n\t" \
5424 "rorl $16,%1" \
5425 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5426
5427 This works great except that the output assembler ends
5428 up looking a bit weird if it turns out that there is
5429 no offset. You end up producing code that looks like:
5430
5431 #APP
5432 movw $235,(%eax)
5433 movw %dx,2+(%eax)
5434 rorl $16,%edx
5435 movb %dl,4+(%eax)
5436 movb $137,5+(%eax)
5437 movb $0,6+(%eax)
5438 movb %dh,7+(%eax)
5439 rorl $16,%edx
5440 #NO_APP
5441
47926f60 5442 So here we provide the missing zero. */
24eab124
AM		 5443
5444 *displacement_string_end = '0';
252b5132
RH		 5445 }
5446#endif
3956db08 5447 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5448 if (gotfree_input_line)
5449 input_line_pointer = gotfree_input_line;
252b5132 5450
24eab124 5451 exp_seg = expression (exp);
252b5132 5452
636c26b0
AM		 5453 SKIP_WHITESPACE ();
5454 if (*input_line_pointer)
5455 as_bad (_("junk `%s' after expression"), input_line_pointer);
5456#if GCC_ASM_O_HACK
5457 RESTORE_END_STRING (disp_end + 1);
5458#endif
636c26b0 5459 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 5460 if (gotfree_input_line)
5461 free (gotfree_input_line);
3992d3b7 5462 ret = 1;
636c26b0 5463
24eab124
AM		 5464 /* We do this to make sure that the section symbol is in
5465 the symbol table. We will ultimately change the relocation
47926f60 5466 to be relative to the beginning of the section. */
1ae12ab7 5467 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 5468 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
5469 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 5470 {
636c26b0 5471 if (exp->X_op != O_symbol)
3992d3b7 5472 goto inv_disp;
636c26b0 5473
e5cb08ac 5474 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 5475 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
5476 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 5477 exp->X_op = O_subtract;
5478 exp->X_op_symbol = GOT_symbol;
1ae12ab7 5479 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 5480 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 5481 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5482 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 5483 else
29b0f896 5484 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 5485 }
252b5132 5486
3992d3b7
AM		 5487 else if (exp->X_op == O_absent
5488 || exp->X_op == O_illegal
5489 || exp->X_op == O_big
5490 || (gotfree_input_line
5491 && (exp->X_op == O_constant
5492 || exp->X_op == O_register)))
2daf4fd8 5493 {
3992d3b7
AM		 5494 inv_disp:
5495 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 5496 disp_start);
3992d3b7 5497 ret = 0;
2daf4fd8
AM		 5498 }
5499
4c63da97 5500#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 5501 else if (exp->X_op != O_constant
5502 && OUTPUT_FLAVOR == bfd_target_aout_flavour
5503 && exp_seg != absolute_section
5504 && exp_seg != text_section
5505 && exp_seg != data_section
5506 && exp_seg != bss_section
5507 && exp_seg != undefined_section
5508 && !bfd_is_com_section (exp_seg))
24eab124 5509 {
d0b47220 5510 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 5511 ret = 0;
24eab124 5512 }
252b5132 5513#endif
3956db08 5514
3992d3b7
AM		 5515 RESTORE_END_STRING (disp_end);
5516
40fb9820
L		 5517 /* Check if this is a displacement only operand. */
5518 bigdisp = i.types[this_operand];
5519 bigdisp.bitfield.disp8 = 0;
5520 bigdisp.bitfield.disp16 = 0;
5521 bigdisp.bitfield.disp32 = 0;
5522 bigdisp.bitfield.disp32s = 0;
5523 bigdisp.bitfield.disp64 = 0;
c6fb90c8
L		 5524 if (UINTS_ALL_ZERO (bigdisp))
5525 i.types[this_operand] = operand_type_and (i.types[this_operand],
5526 types);
3956db08 5527
3992d3b7 5528 return ret;
252b5132
RH		 5529}
5530
eecb386c 5531/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 5532 Return 1 on success, 0 on a failure. */
5533
252b5132 5534static int
e3bb37b5 5535i386_index_check (const char *operand_string)
252b5132 5536{
3e73aa7c 5537 int ok;
24eab124 5538#if INFER_ADDR_PREFIX
eecb386c
AM		 5539 int fudged = 0;
5540
24eab124
AM		 5541 tryprefix:
5542#endif
3e73aa7c 5543 ok = 1;
75178d9d 5544 if (flag_code == CODE_64BIT)
64e74474 5545 {
64e74474 5546 if ((i.base_reg
40fb9820
L		 5547 && ((i.prefix[ADDR_PREFIX] == 0
5548 && !i.base_reg->reg_type.bitfield.reg64)
5549 || (i.prefix[ADDR_PREFIX]
5550 && !i.base_reg->reg_type.bitfield.reg32))
5551 && (i.index_reg
c6fb90c8 5552 || !UINTS_EQUAL (i.base_reg->reg_type, baseindex)))
64e74474 5553 || (i.index_reg
40fb9820
L		 5554 && (!i.index_reg->reg_type.bitfield.baseindex
5555 || (i.prefix[ADDR_PREFIX] == 0
5556 && !i.index_reg->reg_type.bitfield.reg64)
5557 || (i.prefix[ADDR_PREFIX]
5558 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 5559 ok = 0;
3e73aa7c
JH		 5560 }
5561 else
5562 {
5563 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
5564 {
5565 /* 16bit checks. */
5566 if ((i.base_reg
40fb9820
L		 5567 && (!i.base_reg->reg_type.bitfield.reg16
5568 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 5569 || (i.index_reg
40fb9820
L		 5570 && (!i.index_reg->reg_type.bitfield.reg16
5571 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 5572 || !(i.base_reg
5573 && i.base_reg->reg_num < 6
5574 && i.index_reg->reg_num >= 6
5575 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 5576 ok = 0;
5577 }
5578 else
e5cb08ac 5579 {
3e73aa7c
JH		 5580 /* 32bit checks. */
5581 if ((i.base_reg
40fb9820 5582 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 5583 || (i.index_reg
40fb9820
L		 5584 && (!i.index_reg->reg_type.bitfield.reg32
5585 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 5586 ok = 0;
3e73aa7c
JH		 5587 }
5588 }
5589 if (!ok)
24eab124
AM		 5590 {
5591#if INFER_ADDR_PREFIX
20f0a1fc 5592 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 5593 {
5594 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
5595 i.prefixes += 1;
b23bac36
AM		 5596 /* Change the size of any displacement too. At most one of
5597 Disp16 or Disp32 is set.
5598 FIXME. There doesn't seem to be any real need for separate
5599 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 5600 Removing them would probably clean up the code quite a lot. */
4eed87de 5601 if (flag_code != CODE_64BIT
40fb9820
L		 5602 && (i.types[this_operand].bitfield.disp16
5603 || i.types[this_operand].bitfield.disp32))
5604 i.types[this_operand]
c6fb90c8 5605 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 5606 fudged = 1;
24eab124
AM		 5607 goto tryprefix;
5608 }
eecb386c
AM		 5609 if (fudged)
5610 as_bad (_("`%s' is not a valid base/index expression"),
5611 operand_string);
5612 else
c388dee8 5613#endif
eecb386c
AM		 5614 as_bad (_("`%s' is not a valid %s bit base/index expression"),
5615 operand_string,
3e73aa7c 5616 flag_code_names[flag_code]);
24eab124 5617 }
20f0a1fc 5618 return ok;
24eab124 5619}
252b5132 5620
252b5132 5621/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 5622 on error. */
252b5132 5623
252b5132 5624static int
e3bb37b5 5625i386_operand (char *operand_string)
252b5132 5626{
af6bdddf
AM		 5627 const reg_entry *r;
5628 char *end_op;
24eab124 5629 char *op_string = operand_string;
252b5132 5630
24eab124 5631 if (is_space_char (*op_string))
252b5132
RH		 5632 ++op_string;
5633
24eab124 5634 /* We check for an absolute prefix (differentiating,
47926f60 5635 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 5636 if (*op_string == ABSOLUTE_PREFIX)
5637 {
5638 ++op_string;
5639 if (is_space_char (*op_string))
5640 ++op_string;
40fb9820 5641 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 5642 }
252b5132 5643
47926f60 5644 /* Check if operand is a register. */
4d1bb795 5645 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 5646 {
40fb9820
L		 5647 i386_operand_type temp;
5648
24eab124
AM		 5649 /* Check for a segment override by searching for ':' after a
5650 segment register. */
5651 op_string = end_op;
5652 if (is_space_char (*op_string))
5653 ++op_string;
40fb9820
L		 5654 if (*op_string == ':'
5655 && (r->reg_type.bitfield.sreg2
5656 || r->reg_type.bitfield.sreg3))
24eab124
AM		 5657 {
5658 switch (r->reg_num)
5659 {
5660 case 0:
5661 i.seg[i.mem_operands] = &es;
5662 break;
5663 case 1:
5664 i.seg[i.mem_operands] = &cs;
5665 break;
5666 case 2:
5667 i.seg[i.mem_operands] = &ss;
5668 break;
5669 case 3:
5670 i.seg[i.mem_operands] = &ds;
5671 break;
5672 case 4:
5673 i.seg[i.mem_operands] = &fs;
5674 break;
5675 case 5:
5676 i.seg[i.mem_operands] = &gs;
5677 break;
5678 }
252b5132 5679
24eab124 5680 /* Skip the ':' and whitespace. */
252b5132
RH		 5681 ++op_string;
5682 if (is_space_char (*op_string))
24eab124 5683 ++op_string;
252b5132 5684
24eab124
AM		 5685 if (!is_digit_char (*op_string)
5686 && !is_identifier_char (*op_string)
5687 && *op_string != '('
5688 && *op_string != ABSOLUTE_PREFIX)
5689 {
5690 as_bad (_("bad memory operand `%s'"), op_string);
5691 return 0;
5692 }
47926f60 5693 /* Handle case of %es:*foo. */
24eab124
AM		 5694 if (*op_string == ABSOLUTE_PREFIX)
5695 {
5696 ++op_string;
5697 if (is_space_char (*op_string))
5698 ++op_string;
40fb9820 5699 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 5700 }
5701 goto do_memory_reference;
5702 }
5703 if (*op_string)
5704 {
d0b47220 5705 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 5706 return 0;
5707 }
40fb9820
L		 5708 temp = r->reg_type;
5709 temp.bitfield.baseindex = 0;
c6fb90c8
L		 5710 i.types[this_operand] = operand_type_or (i.types[this_operand],
5711 temp);
520dc8e8 5712 i.op[this_operand].regs = r;
24eab124
AM		 5713 i.reg_operands++;
5714 }
af6bdddf
AM		 5715 else if (*op_string == REGISTER_PREFIX)
5716 {
5717 as_bad (_("bad register name `%s'"), op_string);
5718 return 0;
5719 }
24eab124 5720 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 5721 {
24eab124 5722 ++op_string;
40fb9820 5723 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 5724 {
d0b47220 5725 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 5726 return 0;
5727 }
5728 if (!i386_immediate (op_string))
5729 return 0;
5730 }
5731 else if (is_digit_char (*op_string)
5732 || is_identifier_char (*op_string)
e5cb08ac 5733 || *op_string == '(')
24eab124 5734 {
47926f60 5735 /* This is a memory reference of some sort. */
af6bdddf 5736 char *base_string;
252b5132 5737
47926f60 5738 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 5739 char *displacement_string_start;
5740 char *displacement_string_end;
252b5132 5741
24eab124 5742 do_memory_reference:
24eab124 5743 if ((i.mem_operands == 1
40fb9820 5744 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 5745 || i.mem_operands == 2)
5746 {
5747 as_bad (_("too many memory references for `%s'"),
5748 current_templates->start->name);
5749 return 0;
5750 }
252b5132 5751
24eab124
AM		 5752 /* Check for base index form. We detect the base index form by
5753 looking for an ')' at the end of the operand, searching
5754 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5755 after the '('. */
af6bdddf 5756 base_string = op_string + strlen (op_string);
c3332e24 5757
af6bdddf
AM		 5758 --base_string;
5759 if (is_space_char (*base_string))
5760 --base_string;
252b5132 5761
47926f60 5762 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 5763 displacement_string_start = op_string;
5764 displacement_string_end = base_string + 1;
252b5132 5765
24eab124
AM		 5766 if (*base_string == ')')
5767 {
af6bdddf 5768 char *temp_string;
24eab124
AM		 5769 unsigned int parens_balanced = 1;
5770 /* We've already checked that the number of left & right ()'s are
47926f60 5771 equal, so this loop will not be infinite. */
24eab124
AM		 5772 do
5773 {
5774 base_string--;
5775 if (*base_string == ')')
5776 parens_balanced++;
5777 if (*base_string == '(')
5778 parens_balanced--;
5779 }
5780 while (parens_balanced);
c3332e24 5781
af6bdddf 5782 temp_string = base_string;
c3332e24 5783
24eab124 5784 /* Skip past '(' and whitespace. */
252b5132
RH		 5785 ++base_string;
5786 if (is_space_char (*base_string))
24eab124 5787 ++base_string;
252b5132 5788
af6bdddf 5789 if (*base_string == ','
4eed87de
AM		 5790 || ((i.base_reg = parse_register (base_string, &end_op))
5791 != NULL))
252b5132 5792 {
af6bdddf 5793 displacement_string_end = temp_string;
252b5132 5794
40fb9820 5795 i.types[this_operand].bitfield.baseindex = 1;
252b5132 5796
af6bdddf 5797 if (i.base_reg)
24eab124 5798 {
24eab124
AM		 5799 base_string = end_op;
5800 if (is_space_char (*base_string))
5801 ++base_string;
af6bdddf
AM		 5802 }
5803
5804 /* There may be an index reg or scale factor here. */
5805 if (*base_string == ',')
5806 {
5807 ++base_string;
5808 if (is_space_char (*base_string))
5809 ++base_string;
5810
4eed87de
AM		 5811 if ((i.index_reg = parse_register (base_string, &end_op))
5812 != NULL)
24eab124 5813 {
af6bdddf 5814 base_string = end_op;
24eab124
AM		 5815 if (is_space_char (*base_string))
5816 ++base_string;
af6bdddf
AM		 5817 if (*base_string == ',')
5818 {
5819 ++base_string;
5820 if (is_space_char (*base_string))
5821 ++base_string;
5822 }
e5cb08ac 5823 else if (*base_string != ')')
af6bdddf 5824 {
4eed87de
AM		 5825 as_bad (_("expecting `,' or `)' "
5826 "after index register in `%s'"),
af6bdddf
AM		 5827 operand_string);
5828 return 0;
5829 }
24eab124 5830 }
af6bdddf 5831 else if (*base_string == REGISTER_PREFIX)
24eab124 5832 {
af6bdddf 5833 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5834 return 0;
5835 }
252b5132 5836
47926f60 5837 /* Check for scale factor. */
551c1ca1 5838 if (*base_string != ')')
af6bdddf 5839 {
551c1ca1
AM		 5840 char *end_scale = i386_scale (base_string);
5841
5842 if (!end_scale)
af6bdddf 5843 return 0;
24eab124 5844
551c1ca1 5845 base_string = end_scale;
af6bdddf
AM		 5846 if (is_space_char (*base_string))
5847 ++base_string;
5848 if (*base_string != ')')
5849 {
4eed87de
AM		 5850 as_bad (_("expecting `)' "
5851 "after scale factor in `%s'"),
af6bdddf
AM		 5852 operand_string);
5853 return 0;
5854 }
5855 }
5856 else if (!i.index_reg)
24eab124 5857 {
4eed87de
AM		 5858 as_bad (_("expecting index register or scale factor "
5859 "after `,'; got '%c'"),
af6bdddf 5860 *base_string);
24eab124
AM		 5861 return 0;
5862 }
5863 }
af6bdddf 5864 else if (*base_string != ')')
24eab124 5865 {
4eed87de
AM		 5866 as_bad (_("expecting `,' or `)' "
5867 "after base register in `%s'"),
af6bdddf 5868 operand_string);
24eab124
AM		 5869 return 0;
5870 }
c3332e24 5871 }
af6bdddf 5872 else if (*base_string == REGISTER_PREFIX)
c3332e24 5873 {
af6bdddf 5874 as_bad (_("bad register name `%s'"), base_string);
24eab124 5875 return 0;
c3332e24 5876 }
24eab124
AM		 5877 }
5878
5879 /* If there's an expression beginning the operand, parse it,
5880 assuming displacement_string_start and
5881 displacement_string_end are meaningful. */
5882 if (displacement_string_start != displacement_string_end)
5883 {
5884 if (!i386_displacement (displacement_string_start,
5885 displacement_string_end))
5886 return 0;
5887 }
5888
5889 /* Special case for (%dx) while doing input/output op. */
5890 if (i.base_reg
c6fb90c8 5891 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
24eab124
AM		 5892 && i.index_reg == 0
5893 && i.log2_scale_factor == 0
5894 && i.seg[i.mem_operands] == 0
40fb9820 5895 && !operand_type_check (i.types[this_operand], disp))
24eab124 5896 {
c6fb90c8 5897 UINTS_CLEAR (i.types[this_operand]);
40fb9820 5898 i.types[this_operand].bitfield.inoutportreg = 1;
24eab124
AM		 5899 return 1;
5900 }
5901
eecb386c
AM		 5902 if (i386_index_check (operand_string) == 0)
5903 return 0;
24eab124
AM		 5904 i.mem_operands++;
5905 }
5906 else
ce8a8b2f
AM		 5907 {
5908 /* It's not a memory operand; argh! */
24eab124
AM		 5909 as_bad (_("invalid char %s beginning operand %d `%s'"),
5910 output_invalid (*op_string),
5911 this_operand + 1,
5912 op_string);
5913 return 0;
5914 }
47926f60 5915 return 1; /* Normal return. */
252b5132
RH		 5916}
5917\f
ee7fcc42
AM		 5918/* md_estimate_size_before_relax()
5919
5920 Called just before relax() for rs_machine_dependent frags. The x86
5921 assembler uses these frags to handle variable size jump
5922 instructions.
5923
5924 Any symbol that is now undefined will not become defined.
5925 Return the correct fr_subtype in the frag.
5926 Return the initial "guess for variable size of frag" to caller.
5927 The guess is actually the growth beyond the fixed part. Whatever
5928 we do to grow the fixed or variable part contributes to our
5929 returned value. */
5930
252b5132
RH		 5931int
5932md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5933 fragS *fragP;
5934 segT segment;
252b5132 5935{
252b5132 5936 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5937 check for un-relaxable symbols. On an ELF system, we can't relax
5938 an externally visible symbol, because it may be overridden by a
5939 shared library. */
5940 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5941#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5942 || (IS_ELF
31312f95
AM		 5943 && (S_IS_EXTERNAL (fragP->fr_symbol)
5944 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5945#endif
5946 )
252b5132 5947 {
b98ef147
AM		 5948 /* Symbol is undefined in this segment, or we need to keep a
5949 reloc so that weak symbols can be overridden. */
5950 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5951 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5952 unsigned char *opcode;
5953 int old_fr_fix;
f6af82bd 5954
ee7fcc42
AM		 5955 if (fragP->fr_var != NO_RELOC)
5956 reloc_type = fragP->fr_var;
b98ef147 5957 else if (size == 2)
f6af82bd
AM		 5958 reloc_type = BFD_RELOC_16_PCREL;
5959 else
5960 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5961
ee7fcc42
AM		 5962 old_fr_fix = fragP->fr_fix;
5963 opcode = (unsigned char *) fragP->fr_opcode;
5964
fddf5b5b 5965 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5966 {
fddf5b5b
AM		 5967 case UNCOND_JUMP:
5968 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5969 opcode[0] = 0xe9;
252b5132 5970 fragP->fr_fix += size;
062cd5e7
AS		 5971 fix_new (fragP, old_fr_fix, size,
5972 fragP->fr_symbol,
5973 fragP->fr_offset, 1,
5974 reloc_type);
252b5132
RH		 5975 break;
5976
fddf5b5b 5977 case COND_JUMP86:
412167cb
AM		 5978 if (size == 2
5979 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5980 {
5981 /* Negate the condition, and branch past an
5982 unconditional jump. */
5983 opcode[0] ^= 1;
5984 opcode[1] = 3;
5985 /* Insert an unconditional jump. */
5986 opcode[2] = 0xe9;
5987 /* We added two extra opcode bytes, and have a two byte
5988 offset. */
5989 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5990 fix_new (fragP, old_fr_fix + 2, 2,
5991 fragP->fr_symbol,
5992 fragP->fr_offset, 1,
5993 reloc_type);
fddf5b5b
AM		 5994 break;
5995 }
5996 /* Fall through. */
5997
5998 case COND_JUMP:
412167cb
AM		 5999 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6000 {
3e02c1cc
AM		 6001 fixS *fixP;
6002
412167cb 6003 fragP->fr_fix += 1;
3e02c1cc
AM		 6004 fixP = fix_new (fragP, old_fr_fix, 1,
6005 fragP->fr_symbol,
6006 fragP->fr_offset, 1,
6007 BFD_RELOC_8_PCREL);
6008 fixP->fx_signed = 1;
412167cb
AM		 6009 break;
6010 }
93c2a809 6011
24eab124 6012 /* This changes the byte-displacement jump 0x7N
fddf5b5b 6013 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 6014 opcode[1] = opcode[0] + 0x10;
f6af82bd 6015 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 6016 /* We've added an opcode byte. */
6017 fragP->fr_fix += 1 + size;
062cd5e7
AS		 6018 fix_new (fragP, old_fr_fix + 1, size,
6019 fragP->fr_symbol,
6020 fragP->fr_offset, 1,
6021 reloc_type);
252b5132 6022 break;
fddf5b5b
AM		 6023
6024 default:
6025 BAD_CASE (fragP->fr_subtype);
6026 break;
252b5132
RH		 6027 }
6028 frag_wane (fragP);
ee7fcc42 6029 return fragP->fr_fix - old_fr_fix;
252b5132 6030 }
93c2a809 6031
93c2a809
AM		 6032 /* Guess size depending on current relax state. Initially the relax
6033 state will correspond to a short jump and we return 1, because
6034 the variable part of the frag (the branch offset) is one byte
6035 long. However, we can relax a section more than once and in that
6036 case we must either set fr_subtype back to the unrelaxed state,
6037 or return the value for the appropriate branch. */
6038 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 6039}
6040
47926f60
KH		 6041/* Called after relax() is finished.
6042
6043 In: Address of frag.
6044 fr_type == rs_machine_dependent.
6045 fr_subtype is what the address relaxed to.
6046
6047 Out: Any fixSs and constants are set up.
6048 Caller will turn frag into a ".space 0". */
6049
252b5132
RH		 6050void
6051md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 6052 bfd *abfd ATTRIBUTE_UNUSED;
6053 segT sec ATTRIBUTE_UNUSED;
29b0f896 6054 fragS *fragP;
252b5132 6055{
29b0f896 6056 unsigned char *opcode;
252b5132 6057 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 6058 offsetT target_address;
6059 offsetT opcode_address;
252b5132 6060 unsigned int extension = 0;
847f7ad4 6061 offsetT displacement_from_opcode_start;
252b5132
RH		 6062
6063 opcode = (unsigned char *) fragP->fr_opcode;
6064
47926f60 6065 /* Address we want to reach in file space. */
252b5132 6066 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 6067
47926f60 6068 /* Address opcode resides at in file space. */
252b5132
RH		 6069 opcode_address = fragP->fr_address + fragP->fr_fix;
6070
47926f60 6071 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 6072 displacement_from_opcode_start = target_address - opcode_address;
6073
fddf5b5b 6074 if ((fragP->fr_subtype & BIG) == 0)
252b5132 6075 {
47926f60
KH		 6076 /* Don't have to change opcode. */
6077 extension = 1; /* 1 opcode + 1 displacement */
252b5132 6078 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 6079 }
6080 else
6081 {
6082 if (no_cond_jump_promotion
6083 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 6084 as_warn_where (fragP->fr_file, fragP->fr_line,
6085 _("long jump required"));
252b5132 6086
fddf5b5b
AM		 6087 switch (fragP->fr_subtype)
6088 {
6089 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6090 extension = 4; /* 1 opcode + 4 displacement */
6091 opcode[0] = 0xe9;
6092 where_to_put_displacement = &opcode[1];
6093 break;
252b5132 6094
fddf5b5b
AM		 6095 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6096 extension = 2; /* 1 opcode + 2 displacement */
6097 opcode[0] = 0xe9;
6098 where_to_put_displacement = &opcode[1];
6099 break;
252b5132 6100
fddf5b5b
AM		 6101 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6102 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6103 extension = 5; /* 2 opcode + 4 displacement */
6104 opcode[1] = opcode[0] + 0x10;
6105 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6106 where_to_put_displacement = &opcode[2];
6107 break;
252b5132 6108
fddf5b5b
AM		 6109 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6110 extension = 3; /* 2 opcode + 2 displacement */
6111 opcode[1] = opcode[0] + 0x10;
6112 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6113 where_to_put_displacement = &opcode[2];
6114 break;
252b5132 6115
fddf5b5b
AM		 6116 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6117 extension = 4;
6118 opcode[0] ^= 1;
6119 opcode[1] = 3;
6120 opcode[2] = 0xe9;
6121 where_to_put_displacement = &opcode[3];
6122 break;
6123
6124 default:
6125 BAD_CASE (fragP->fr_subtype);
6126 break;
6127 }
252b5132 6128 }
fddf5b5b 6129
7b81dfbb
AJ		 6130 /* If size if less then four we are sure that the operand fits,
6131 but if it's 4, then it could be that the displacement is larger
6132 then -/+ 2GB. */
6133 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6134 && object_64bit
6135 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 6136 + ((addressT) 1 << 31))
6137 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 6138 {
6139 as_bad_where (fragP->fr_file, fragP->fr_line,
6140 _("jump target out of range"));
6141 /* Make us emit 0. */
6142 displacement_from_opcode_start = extension;
6143 }
47926f60 6144 /* Now put displacement after opcode. */
252b5132
RH		 6145 md_number_to_chars ((char *) where_to_put_displacement,
6146 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 6147 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 6148 fragP->fr_fix += extension;
6149}
6150\f
47926f60
KH		 6151/* Size of byte displacement jmp. */
6152int md_short_jump_size = 2;
6153
6154/* Size of dword displacement jmp. */
6155int md_long_jump_size = 5;
252b5132 6156
252b5132
RH		 6157void
6158md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
6159 char *ptr;
6160 addressT from_addr, to_addr;
ab9da554
ILT		 6161 fragS *frag ATTRIBUTE_UNUSED;
6162 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 6163{
847f7ad4 6164 offsetT offset;
252b5132
RH		 6165
6166 offset = to_addr - (from_addr + 2);
47926f60
KH		 6167 /* Opcode for byte-disp jump. */
6168 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 6169 md_number_to_chars (ptr + 1, (valueT) offset, 1);
6170}
6171
6172void
6173md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
6174 char *ptr;
6175 addressT from_addr, to_addr;
a38cf1db
AM		 6176 fragS *frag ATTRIBUTE_UNUSED;
6177 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 6178{
847f7ad4 6179 offsetT offset;
252b5132 6180
a38cf1db
AM		 6181 offset = to_addr - (from_addr + 5);
6182 md_number_to_chars (ptr, (valueT) 0xe9, 1);
6183 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 6184}
6185\f
6186/* Apply a fixup (fixS) to segment data, once it has been determined
6187 by our caller that we have all the info we need to fix it up.
6188
6189 On the 386, immediates, displacements, and data pointers are all in
6190 the same (little-endian) format, so we don't need to care about which
6191 we are handling. */
6192
94f592af 6193void
55cf6793 6194md_apply_fix (fixP, valP, seg)
47926f60
KH		 6195 /* The fix we're to put in. */
6196 fixS *fixP;
47926f60 6197 /* Pointer to the value of the bits. */
c6682705 6198 valueT *valP;
47926f60
KH		 6199 /* Segment fix is from. */
6200 segT seg ATTRIBUTE_UNUSED;
252b5132 6201{
94f592af 6202 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 6203 valueT value = *valP;
252b5132 6204
f86103b7 6205#if !defined (TE_Mach)
93382f6d
AM		 6206 if (fixP->fx_pcrel)
6207 {
6208 switch (fixP->fx_r_type)
6209 {
5865bb77
ILT		 6210 default:
6211 break;
6212
d6ab8113
JB		 6213 case BFD_RELOC_64:
6214 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6215 break;
93382f6d 6216 case BFD_RELOC_32:
ae8887b5 6217 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 6218 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6219 break;
6220 case BFD_RELOC_16:
6221 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6222 break;
6223 case BFD_RELOC_8:
6224 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6225 break;
6226 }
6227 }
252b5132 6228
a161fe53 6229 if (fixP->fx_addsy != NULL
31312f95 6230 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 6231 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 6232 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6233 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6234 && !use_rela_relocations)
252b5132 6235 {
31312f95
AM		 6236 /* This is a hack. There should be a better way to handle this.
6237 This covers for the fact that bfd_install_relocation will
6238 subtract the current location (for partial_inplace, PC relative
6239 relocations); see more below. */
252b5132 6240#ifndef OBJ_AOUT
718ddfc0 6241 if (IS_ELF
252b5132
RH		 6242#ifdef TE_PE
6243 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6244#endif
6245 )
6246 value += fixP->fx_where + fixP->fx_frag->fr_address;
6247#endif
6248#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6249 if (IS_ELF)
252b5132 6250 {
6539b54b 6251 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 6252
6539b54b 6253 if ((sym_seg == seg
2f66722d 6254 || (symbol_section_p (fixP->fx_addsy)
6539b54b 6255 && sym_seg != absolute_section))
ae6063d4 6256 && !generic_force_reloc (fixP))
2f66722d
AM		 6257 {
6258 /* Yes, we add the values in twice. This is because
6539b54b
AM		 6259 bfd_install_relocation subtracts them out again. I think
6260 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 6261 it. FIXME. */
6262 value += fixP->fx_where + fixP->fx_frag->fr_address;
6263 }
252b5132
RH		 6264 }
6265#endif
6266#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 6267 /* For some reason, the PE format does not store a
6268 section address offset for a PC relative symbol. */
6269 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 6270 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 6271 value += md_pcrel_from (fixP);
6272#endif
6273 }
6274
6275 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 6276 and we must not disappoint it. */
252b5132 6277#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6278 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 6279 switch (fixP->fx_r_type)
6280 {
6281 case BFD_RELOC_386_PLT32:
3e73aa7c 6282 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 6283 /* Make the jump instruction point to the address of the operand. At
6284 runtime we merely add the offset to the actual PLT entry. */
6285 value = -4;
6286 break;
31312f95 6287
13ae64f3
JJ		 6288 case BFD_RELOC_386_TLS_GD:
6289 case BFD_RELOC_386_TLS_LDM:
13ae64f3 6290 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6291 case BFD_RELOC_386_TLS_IE:
6292 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 6293 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 6294 case BFD_RELOC_X86_64_TLSGD:
6295 case BFD_RELOC_X86_64_TLSLD:
6296 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 6297 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 6298 value = 0; /* Fully resolved at runtime. No addend. */
6299 /* Fallthrough */
6300 case BFD_RELOC_386_TLS_LE:
6301 case BFD_RELOC_386_TLS_LDO_32:
6302 case BFD_RELOC_386_TLS_LE_32:
6303 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6304 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 6305 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 6306 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 6307 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6308 break;
6309
67a4f2b7
AO		 6310 case BFD_RELOC_386_TLS_DESC_CALL:
6311 case BFD_RELOC_X86_64_TLSDESC_CALL:
6312 value = 0; /* Fully resolved at runtime. No addend. */
6313 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6314 fixP->fx_done = 0;
6315 return;
6316
00f7efb6
JJ		 6317 case BFD_RELOC_386_GOT32:
6318 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 6319 value = 0; /* Fully resolved at runtime. No addend. */
6320 break;
47926f60
KH		 6321
6322 case BFD_RELOC_VTABLE_INHERIT:
6323 case BFD_RELOC_VTABLE_ENTRY:
6324 fixP->fx_done = 0;
94f592af 6325 return;
47926f60
KH		 6326
6327 default:
6328 break;
6329 }
6330#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 6331 *valP = value;
f86103b7 6332#endif /* !defined (TE_Mach) */
3e73aa7c 6333
3e73aa7c 6334 /* Are we finished with this relocation now? */
c6682705 6335 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 6336 fixP->fx_done = 1;
6337 else if (use_rela_relocations)
6338 {
6339 fixP->fx_no_overflow = 1;
062cd5e7
AS		 6340 /* Remember value for tc_gen_reloc. */
6341 fixP->fx_addnumber = value;
3e73aa7c
JH		 6342 value = 0;
6343 }
f86103b7 6344
94f592af 6345 md_number_to_chars (p, value, fixP->fx_size);
252b5132 6346}
252b5132 6347\f
252b5132
RH		 6348#define MAX_LITTLENUMS 6
6349
47926f60
KH		 6350/* Turn the string pointed to by litP into a floating point constant
6351 of type TYPE, and emit the appropriate bytes. The number of
6352 LITTLENUMS emitted is stored in *SIZEP. An error message is
6353 returned, or NULL on OK. */
6354
252b5132
RH		 6355char *
6356md_atof (type, litP, sizeP)
2ab9b79e 6357 int type;
252b5132
RH		 6358 char *litP;
6359 int *sizeP;
6360{
6361 int prec;
6362 LITTLENUM_TYPE words[MAX_LITTLENUMS];
6363 LITTLENUM_TYPE *wordP;
6364 char *t;
6365
6366 switch (type)
6367 {
6368 case 'f':
6369 case 'F':
6370 prec = 2;
6371 break;
6372
6373 case 'd':
6374 case 'D':
6375 prec = 4;
6376 break;
6377
6378 case 'x':
6379 case 'X':
6380 prec = 5;
6381 break;
6382
6383 default:
6384 *sizeP = 0;
6385 return _("Bad call to md_atof ()");
6386 }
6387 t = atof_ieee (input_line_pointer, type, words);
6388 if (t)
6389 input_line_pointer = t;
6390
6391 *sizeP = prec * sizeof (LITTLENUM_TYPE);
6392 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
6393 the bigendian 386. */
6394 for (wordP = words + prec - 1; prec--;)
6395 {
6396 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
6397 litP += sizeof (LITTLENUM_TYPE);
6398 }
6399 return 0;
6400}
6401\f
2d545b82 6402static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 6403
252b5132 6404static char *
e3bb37b5 6405output_invalid (int c)
252b5132 6406{
3882b010 6407 if (ISPRINT (c))
f9f21a03
L		 6408 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6409 "'%c'", c);
252b5132 6410 else
f9f21a03 6411 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 6412 "(0x%x)", (unsigned char) c);
252b5132
RH		 6413 return output_invalid_buf;
6414}
6415
af6bdddf 6416/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 6417
6418static const reg_entry *
4d1bb795 6419parse_real_register (char *reg_string, char **end_op)
252b5132 6420{
af6bdddf
AM		 6421 char *s = reg_string;
6422 char *p;
252b5132
RH		 6423 char reg_name_given[MAX_REG_NAME_SIZE + 1];
6424 const reg_entry *r;
6425
6426 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6427 if (*s == REGISTER_PREFIX)
6428 ++s;
6429
6430 if (is_space_char (*s))
6431 ++s;
6432
6433 p = reg_name_given;
af6bdddf 6434 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 6435 {
6436 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 6437 return (const reg_entry *) NULL;
6438 s++;
252b5132
RH		 6439 }
6440
6588847e
DN		 6441 /* For naked regs, make sure that we are not dealing with an identifier.
6442 This prevents confusing an identifier like `eax_var' with register
6443 `eax'. */
6444 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
6445 return (const reg_entry *) NULL;
6446
af6bdddf 6447 *end_op = s;
252b5132
RH		 6448
6449 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
6450
5f47d35b 6451 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 6452 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 6453 {
5f47d35b
AM		 6454 if (is_space_char (*s))
6455 ++s;
6456 if (*s == '(')
6457 {
af6bdddf 6458 ++s;
5f47d35b
AM		 6459 if (is_space_char (*s))
6460 ++s;
6461 if (*s >= '0' && *s <= '7')
6462 {
db557034 6463 int fpr = *s - '0';
af6bdddf 6464 ++s;
5f47d35b
AM		 6465 if (is_space_char (*s))
6466 ++s;
6467 if (*s == ')')
6468 {
6469 *end_op = s + 1;
db557034
AM		 6470 r = hash_find (reg_hash, "st(0)");
6471 know (r);
6472 return r + fpr;
5f47d35b 6473 }
5f47d35b 6474 }
47926f60 6475 /* We have "%st(" then garbage. */
5f47d35b
AM		 6476 return (const reg_entry *) NULL;
6477 }
6478 }
6479
1ae00879 6480 if (r != NULL
d946b91f 6481 && ((r->reg_flags & (RegRex64 | RegRex))
40fb9820
L		 6482 || r->reg_type.bitfield.reg64)
6483 && (!cpu_arch_flags.bitfield.cpulm
c6fb90c8 6484 || !UINTS_EQUAL (r->reg_type, control))
1ae00879 6485 && flag_code != CODE_64BIT)
20f0a1fc 6486 return (const reg_entry *) NULL;
1ae00879 6487
252b5132
RH		 6488 return r;
6489}
4d1bb795
JB		 6490
6491/* REG_STRING starts *before* REGISTER_PREFIX. */
6492
6493static const reg_entry *
6494parse_register (char *reg_string, char **end_op)
6495{
6496 const reg_entry *r;
6497
6498 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
6499 r = parse_real_register (reg_string, end_op);
6500 else
6501 r = NULL;
6502 if (!r)
6503 {
6504 char *save = input_line_pointer;
6505 char c;
6506 symbolS *symbolP;
6507
6508 input_line_pointer = reg_string;
6509 c = get_symbol_end ();
6510 symbolP = symbol_find (reg_string);
6511 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
6512 {
6513 const expressionS *e = symbol_get_value_expression (symbolP);
6514
6515 know (e->X_op == O_register);
4eed87de 6516 know (e->X_add_number >= 0
c3fe08fa 6517 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 6518 r = i386_regtab + e->X_add_number;
6519 *end_op = input_line_pointer;
6520 }
6521 *input_line_pointer = c;
6522 input_line_pointer = save;
6523 }
6524 return r;
6525}
6526
6527int
6528i386_parse_name (char *name, expressionS *e, char *nextcharP)
6529{
6530 const reg_entry *r;
6531 char *end = input_line_pointer;
6532
6533 *end = *nextcharP;
6534 r = parse_register (name, &input_line_pointer);
6535 if (r && end <= input_line_pointer)
6536 {
6537 *nextcharP = *input_line_pointer;
6538 *input_line_pointer = 0;
6539 e->X_op = O_register;
6540 e->X_add_number = r - i386_regtab;
6541 return 1;
6542 }
6543 input_line_pointer = end;
6544 *end = 0;
6545 return 0;
6546}
6547
6548void
6549md_operand (expressionS *e)
6550{
6551 if (*input_line_pointer == REGISTER_PREFIX)
6552 {
6553 char *end;
6554 const reg_entry *r = parse_real_register (input_line_pointer, &end);
6555
6556 if (r)
6557 {
6558 e->X_op = O_register;
6559 e->X_add_number = r - i386_regtab;
6560 input_line_pointer = end;
6561 }
6562 }
6563}
6564
252b5132 6565\f
4cc782b5 6566#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 6567const char *md_shortopts = "kVQ:sqn";
252b5132 6568#else
12b55ccc 6569const char *md_shortopts = "qn";
252b5132 6570#endif
6e0b89ee 6571
3e73aa7c 6572#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 6573#define OPTION_64 (OPTION_MD_BASE + 1)
6574#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 6575#define OPTION_MARCH (OPTION_MD_BASE + 3)
6576#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 6577
99ad8390
NC		 6578struct option md_longopts[] =
6579{
3e73aa7c 6580 {"32", no_argument, NULL, OPTION_32},
99ad8390 6581#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 6582 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 6583#endif
b3b91714 6584 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 6585 {"march", required_argument, NULL, OPTION_MARCH},
6586 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 6587 {NULL, no_argument, NULL, 0}
6588};
6589size_t md_longopts_size = sizeof (md_longopts);
6590
6591int
9103f4f4 6592md_parse_option (int c, char *arg)
252b5132 6593{
9103f4f4
L		 6594 unsigned int i;
6595
252b5132
RH		 6596 switch (c)
6597 {
12b55ccc
L		 6598 case 'n':
6599 optimize_align_code = 0;
6600 break;
6601
a38cf1db
AM		 6602 case 'q':
6603 quiet_warnings = 1;
252b5132
RH		 6604 break;
6605
6606#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 6607 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6608 should be emitted or not. FIXME: Not implemented. */
6609 case 'Q':
252b5132
RH		 6610 break;
6611
6612 /* -V: SVR4 argument to print version ID. */
6613 case 'V':
6614 print_version_id ();
6615 break;
6616
a38cf1db
AM		 6617 /* -k: Ignore for FreeBSD compatibility. */
6618 case 'k':
252b5132 6619 break;
4cc782b5
ILT		 6620
6621 case 's':
6622 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 6623 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 6624 break;
99ad8390
NC		 6625#endif
6626#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 6627 case OPTION_64:
6628 {
6629 const char **list, **l;
6630
3e73aa7c
JH		 6631 list = bfd_target_list ();
6632 for (l = list; *l != NULL; l++)
8620418b 6633 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 6634 || strcmp (*l, "coff-x86-64") == 0
6635 || strcmp (*l, "pe-x86-64") == 0
6636 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 6637 {
6638 default_arch = "x86_64";
6639 break;
6640 }
3e73aa7c 6641 if (*l == NULL)
6e0b89ee 6642 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 6643 free (list);
6644 }
6645 break;
6646#endif
252b5132 6647
6e0b89ee
AM		 6648 case OPTION_32:
6649 default_arch = "i386";
6650 break;
6651
b3b91714
AM		 6652 case OPTION_DIVIDE:
6653#ifdef SVR4_COMMENT_CHARS
6654 {
6655 char *n, *t;
6656 const char *s;
6657
6658 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
6659 t = n;
6660 for (s = i386_comment_chars; *s != '\0'; s++)
6661 if (*s != '/')
6662 *t++ = *s;
6663 *t = '\0';
6664 i386_comment_chars = n;
6665 }
6666#endif
6667 break;
6668
9103f4f4
L		 6669 case OPTION_MARCH:
6670 if (*arg == '.')
6671 as_fatal (_("Invalid -march= option: `%s'"), arg);
6672 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
6673 {
6674 if (strcmp (arg, cpu_arch [i].name) == 0)
6675 {
ccc9c027 6676 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 6677 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 6678 if (!cpu_arch_tune_set)
6679 {
6680 cpu_arch_tune = cpu_arch_isa;
6681 cpu_arch_tune_flags = cpu_arch_isa_flags;
6682 }
9103f4f4
L		 6683 break;
6684 }
6685 }
6686 if (i >= ARRAY_SIZE (cpu_arch))
6687 as_fatal (_("Invalid -march= option: `%s'"), arg);
6688 break;
6689
6690 case OPTION_MTUNE:
6691 if (*arg == '.')
6692 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6693 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
6694 {
6695 if (strcmp (arg, cpu_arch [i].name) == 0)
6696 {
ccc9c027 6697 cpu_arch_tune_set = 1;
9103f4f4
L		 6698 cpu_arch_tune = cpu_arch [i].type;
6699 cpu_arch_tune_flags = cpu_arch[i].flags;
6700 break;
6701 }
6702 }
6703 if (i >= ARRAY_SIZE (cpu_arch))
6704 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6705 break;
6706
252b5132
RH		 6707 default:
6708 return 0;
6709 }
6710 return 1;
6711}
6712
6713void
6714md_show_usage (stream)
6715 FILE *stream;
6716{
4cc782b5
ILT		 6717#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6718 fprintf (stream, _("\
a38cf1db
AM		 6719 -Q ignored\n\
6720 -V print assembler version number\n\
b3b91714
AM		 6721 -k ignored\n"));
6722#endif
6723 fprintf (stream, _("\
12b55ccc 6724 -n Do not optimize code alignment\n\
b3b91714
AM		 6725 -q quieten some warnings\n"));
6726#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6727 fprintf (stream, _("\
a38cf1db 6728 -s ignored\n"));
b3b91714 6729#endif
751d281c
L		 6730#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6731 fprintf (stream, _("\
6732 --32/--64 generate 32bit/64bit code\n"));
6733#endif
b3b91714
AM		 6734#ifdef SVR4_COMMENT_CHARS
6735 fprintf (stream, _("\
6736 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 6737#else
6738 fprintf (stream, _("\
b3b91714 6739 --divide ignored\n"));
4cc782b5 6740#endif
9103f4f4
L		 6741 fprintf (stream, _("\
6742 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6743 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 6744 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 6745
252b5132
RH		 6746}
6747
3e73aa7c 6748#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 6749 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 6750
6751/* Pick the target format to use. */
6752
47926f60 6753const char *
e3bb37b5 6754i386_target_format (void)
252b5132 6755{
3e73aa7c 6756 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 6757 {
6758 set_code_flag (CODE_64BIT);
c6fb90c8 6759 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 6760 {
6761 cpu_arch_isa_flags.bitfield.cpui186 = 1;
6762 cpu_arch_isa_flags.bitfield.cpui286 = 1;
6763 cpu_arch_isa_flags.bitfield.cpui386 = 1;
6764 cpu_arch_isa_flags.bitfield.cpui486 = 1;
6765 cpu_arch_isa_flags.bitfield.cpui586 = 1;
6766 cpu_arch_isa_flags.bitfield.cpui686 = 1;
6767 cpu_arch_isa_flags.bitfield.cpup4 = 1;
6768 cpu_arch_isa_flags.bitfield.cpummx= 1;
6769 cpu_arch_isa_flags.bitfield.cpummx2 = 1;
6770 cpu_arch_isa_flags.bitfield.cpusse = 1;
6771 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
6772 }
c6fb90c8 6773 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 6774 {
6775 cpu_arch_tune_flags.bitfield.cpui186 = 1;
6776 cpu_arch_tune_flags.bitfield.cpui286 = 1;
6777 cpu_arch_tune_flags.bitfield.cpui386 = 1;
6778 cpu_arch_tune_flags.bitfield.cpui486 = 1;
6779 cpu_arch_tune_flags.bitfield.cpui586 = 1;
6780 cpu_arch_tune_flags.bitfield.cpui686 = 1;
6781 cpu_arch_tune_flags.bitfield.cpup4 = 1;
6782 cpu_arch_tune_flags.bitfield.cpummx= 1;
6783 cpu_arch_tune_flags.bitfield.cpummx2 = 1;
6784 cpu_arch_tune_flags.bitfield.cpusse = 1;
6785 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
6786 }
9103f4f4 6787 }
3e73aa7c 6788 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 6789 {
6790 set_code_flag (CODE_32BIT);
c6fb90c8 6791 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 6792 {
6793 cpu_arch_isa_flags.bitfield.cpui186 = 1;
6794 cpu_arch_isa_flags.bitfield.cpui286 = 1;
6795 cpu_arch_isa_flags.bitfield.cpui386 = 1;
6796 }
c6fb90c8 6797 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 6798 {
6799 cpu_arch_tune_flags.bitfield.cpui186 = 1;
6800 cpu_arch_tune_flags.bitfield.cpui286 = 1;
6801 cpu_arch_tune_flags.bitfield.cpui386 = 1;
6802 }
9103f4f4 6803 }
3e73aa7c
JH		 6804 else
6805 as_fatal (_("Unknown architecture"));
252b5132
RH		 6806 switch (OUTPUT_FLAVOR)
6807 {
872ce6ff
L		 6808#ifdef TE_PEP
6809 case bfd_target_coff_flavour:
6810 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
6811 break;
6812#endif
4c63da97
AM		 6813#ifdef OBJ_MAYBE_AOUT
6814 case bfd_target_aout_flavour:
47926f60 6815 return AOUT_TARGET_FORMAT;
4c63da97
AM		 6816#endif
6817#ifdef OBJ_MAYBE_COFF
252b5132
RH		 6818 case bfd_target_coff_flavour:
6819 return "coff-i386";
4c63da97 6820#endif
3e73aa7c 6821#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 6822 case bfd_target_elf_flavour:
3e73aa7c 6823 {
e5cb08ac 6824 if (flag_code == CODE_64BIT)
4fa24527
JB		 6825 {
6826 object_64bit = 1;
6827 use_rela_relocations = 1;
6828 }
9d7cbccd 6829 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6830 }
4c63da97 6831#endif
252b5132
RH		 6832 default:
6833 abort ();
6834 return NULL;
6835 }
6836}
6837
47926f60 6838#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 6839
6840#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 6841void
6842i386_elf_emit_arch_note (void)
a847613f 6843{
718ddfc0 6844 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 6845 {
6846 char *p;
6847 asection *seg = now_seg;
6848 subsegT subseg = now_subseg;
6849 Elf_Internal_Note i_note;
6850 Elf_External_Note e_note;
6851 asection *note_secp;
6852 int len;
6853
6854 /* Create the .note section. */
6855 note_secp = subseg_new (".note", 0);
6856 bfd_set_section_flags (stdoutput,
6857 note_secp,
6858 SEC_HAS_CONTENTS | SEC_READONLY);
6859
6860 /* Process the arch string. */
6861 len = strlen (cpu_arch_name);
6862
6863 i_note.namesz = len + 1;
6864 i_note.descsz = 0;
6865 i_note.type = NT_ARCH;
6866 p = frag_more (sizeof (e_note.namesz));
6867 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6868 p = frag_more (sizeof (e_note.descsz));
6869 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6870 p = frag_more (sizeof (e_note.type));
6871 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6872 p = frag_more (len + 1);
6873 strcpy (p, cpu_arch_name);
6874
6875 frag_align (2, 0, 0);
6876
6877 subseg_set (seg, subseg);
6878 }
6879}
6880#endif
252b5132 6881\f
252b5132
RH		 6882symbolS *
6883md_undefined_symbol (name)
6884 char *name;
6885{
18dc2407
ILT		 6886 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6887 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6888 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6889 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6890 {
6891 if (!GOT_symbol)
6892 {
6893 if (symbol_find (name))
6894 as_bad (_("GOT already in symbol table"));
6895 GOT_symbol = symbol_new (name, undefined_section,
6896 (valueT) 0, &zero_address_frag);
6897 };
6898 return GOT_symbol;
6899 }
252b5132
RH		 6900 return 0;
6901}
6902
6903/* Round up a section size to the appropriate boundary. */
47926f60 6904
252b5132
RH		 6905valueT
6906md_section_align (segment, size)
ab9da554 6907 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6908 valueT size;
6909{
4c63da97
AM		 6910#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6911 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6912 {
6913 /* For a.out, force the section size to be aligned. If we don't do
6914 this, BFD will align it for us, but it will not write out the
6915 final bytes of the section. This may be a bug in BFD, but it is
6916 easier to fix it here since that is how the other a.out targets
6917 work. */
6918 int align;
6919
6920 align = bfd_get_section_alignment (stdoutput, segment);
6921 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6922 }
252b5132
RH		 6923#endif
6924
6925 return size;
6926}
6927
6928/* On the i386, PC-relative offsets are relative to the start of the
6929 next instruction. That is, the address of the offset, plus its
6930 size, since the offset is always the last part of the insn. */
6931
6932long
e3bb37b5 6933md_pcrel_from (fixS *fixP)
252b5132
RH		 6934{
6935 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6936}
6937
6938#ifndef I386COFF
6939
6940static void
e3bb37b5 6941s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 6942{
29b0f896 6943 int temp;
252b5132 6944
8a75718c
JB		 6945#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6946 if (IS_ELF)
6947 obj_elf_section_change_hook ();
6948#endif
252b5132
RH		 6949 temp = get_absolute_expression ();
6950 subseg_set (bss_section, (subsegT) temp);
6951 demand_empty_rest_of_line ();
6952}
6953
6954#endif
6955
252b5132 6956void
e3bb37b5 6957i386_validate_fix (fixS *fixp)
252b5132
RH		 6958{
6959 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6960 {
23df1078
JH		 6961 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6962 {
4fa24527 6963 if (!object_64bit)
23df1078
JH		 6964 abort ();
6965 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6966 }
6967 else
6968 {
4fa24527 6969 if (!object_64bit)
d6ab8113
JB		 6970 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6971 else
6972 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6973 }
252b5132
RH		 6974 fixp->fx_subsy = 0;
6975 }
6976}
6977
252b5132
RH		 6978arelent *
6979tc_gen_reloc (section, fixp)
ab9da554 6980 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6981 fixS *fixp;
6982{
6983 arelent *rel;
6984 bfd_reloc_code_real_type code;
6985
6986 switch (fixp->fx_r_type)
6987 {
3e73aa7c
JH		 6988 case BFD_RELOC_X86_64_PLT32:
6989 case BFD_RELOC_X86_64_GOT32:
6990 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6991 case BFD_RELOC_386_PLT32:
6992 case BFD_RELOC_386_GOT32:
6993 case BFD_RELOC_386_GOTOFF:
6994 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 6995 case BFD_RELOC_386_TLS_GD:
6996 case BFD_RELOC_386_TLS_LDM:
6997 case BFD_RELOC_386_TLS_LDO_32:
6998 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6999 case BFD_RELOC_386_TLS_IE:
7000 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 7001 case BFD_RELOC_386_TLS_LE_32:
7002 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 7003 case BFD_RELOC_386_TLS_GOTDESC:
7004 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 7005 case BFD_RELOC_X86_64_TLSGD:
7006 case BFD_RELOC_X86_64_TLSLD:
7007 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7008 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 7009 case BFD_RELOC_X86_64_GOTTPOFF:
7010 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 7011 case BFD_RELOC_X86_64_TPOFF64:
7012 case BFD_RELOC_X86_64_GOTOFF64:
7013 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 7014 case BFD_RELOC_X86_64_GOT64:
7015 case BFD_RELOC_X86_64_GOTPCREL64:
7016 case BFD_RELOC_X86_64_GOTPC64:
7017 case BFD_RELOC_X86_64_GOTPLT64:
7018 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 7019 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7020 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 7021 case BFD_RELOC_RVA:
7022 case BFD_RELOC_VTABLE_ENTRY:
7023 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 7024#ifdef TE_PE
7025 case BFD_RELOC_32_SECREL:
7026#endif
252b5132
RH		 7027 code = fixp->fx_r_type;
7028 break;
dbbaec26
L		 7029 case BFD_RELOC_X86_64_32S:
7030 if (!fixp->fx_pcrel)
7031 {
7032 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7033 code = fixp->fx_r_type;
7034 break;
7035 }
252b5132 7036 default:
93382f6d 7037 if (fixp->fx_pcrel)
252b5132 7038 {
93382f6d
AM		 7039 switch (fixp->fx_size)
7040 {
7041 default:
b091f402
AM		 7042 as_bad_where (fixp->fx_file, fixp->fx_line,
7043 _("can not do %d byte pc-relative relocation"),
7044 fixp->fx_size);
93382f6d
AM		 7045 code = BFD_RELOC_32_PCREL;
7046 break;
7047 case 1: code = BFD_RELOC_8_PCREL; break;
7048 case 2: code = BFD_RELOC_16_PCREL; break;
7049 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 7050#ifdef BFD64
7051 case 8: code = BFD_RELOC_64_PCREL; break;
7052#endif
93382f6d
AM		 7053 }
7054 }
7055 else
7056 {
7057 switch (fixp->fx_size)
7058 {
7059 default:
b091f402
AM		 7060 as_bad_where (fixp->fx_file, fixp->fx_line,
7061 _("can not do %d byte relocation"),
7062 fixp->fx_size);
93382f6d
AM		 7063 code = BFD_RELOC_32;
7064 break;
7065 case 1: code = BFD_RELOC_8; break;
7066 case 2: code = BFD_RELOC_16; break;
7067 case 4: code = BFD_RELOC_32; break;
937149dd 7068#ifdef BFD64
3e73aa7c 7069 case 8: code = BFD_RELOC_64; break;
937149dd 7070#endif
93382f6d 7071 }
252b5132
RH		 7072 }
7073 break;
7074 }
252b5132 7075
d182319b
JB		 7076 if ((code == BFD_RELOC_32
7077 || code == BFD_RELOC_32_PCREL
7078 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 7079 && GOT_symbol
7080 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 7081 {
4fa24527 7082 if (!object_64bit)
d6ab8113
JB		 7083 code = BFD_RELOC_386_GOTPC;
7084 else
7085 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 7086 }
7b81dfbb
AJ		 7087 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7088 && GOT_symbol
7089 && fixp->fx_addsy == GOT_symbol)
7090 {
7091 code = BFD_RELOC_X86_64_GOTPC64;
7092 }
252b5132
RH		 7093
7094 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 7095 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7096 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 7097
7098 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 7099
3e73aa7c
JH		 7100 if (!use_rela_relocations)
7101 {
7102 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7103 vtable entry to be used in the relocation's section offset. */
7104 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7105 rel->address = fixp->fx_offset;
252b5132 7106
c6682705 7107 rel->addend = 0;
3e73aa7c
JH		 7108 }
7109 /* Use the rela in 64bit mode. */
252b5132 7110 else
3e73aa7c 7111 {
062cd5e7
AS		 7112 if (!fixp->fx_pcrel)
7113 rel->addend = fixp->fx_offset;
7114 else
7115 switch (code)
7116 {
7117 case BFD_RELOC_X86_64_PLT32:
7118 case BFD_RELOC_X86_64_GOT32:
7119 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 7120 case BFD_RELOC_X86_64_TLSGD:
7121 case BFD_RELOC_X86_64_TLSLD:
7122 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 7123 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7124 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 7125 rel->addend = fixp->fx_offset - fixp->fx_size;
7126 break;
7127 default:
7128 rel->addend = (section->vma
7129 - fixp->fx_size
7130 + fixp->fx_addnumber
7131 + md_pcrel_from (fixp));
7132 break;
7133 }
3e73aa7c
JH		 7134 }
7135
252b5132
RH		 7136 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7137 if (rel->howto == NULL)
7138 {
7139 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 7140 _("cannot represent relocation type %s"),
252b5132
RH		 7141 bfd_get_reloc_code_name (code));
7142 /* Set howto to a garbage value so that we can keep going. */
7143 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7144 assert (rel->howto != NULL);
7145 }
7146
7147 return rel;
7148}
7149
64a0c779
DN		 7150\f
7151/* Parse operands using Intel syntax. This implements a recursive descent
7152 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7153 Programmer's Guide.
7154
7155 FIXME: We do not recognize the full operand grammar defined in the MASM
7156 documentation. In particular, all the structure/union and
7157 high-level macro operands are missing.
7158
7159 Uppercase words are terminals, lower case words are non-terminals.
7160 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7161 bars '|' denote choices. Most grammar productions are implemented in
7162 functions called 'intel_<production>'.
7163
7164 Initial production is 'expr'.
7165
9306ca4a 7166 addOp + | -
64a0c779
DN		 7167
7168 alpha [a-zA-Z]
7169
9306ca4a
JB		 7170 binOp & | AND | \| | OR | ^ | XOR
7171
64a0c779
DN		 7172 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7173
7174 constant digits [[ radixOverride ]]
7175
9306ca4a 7176 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 7177
7178 digits decdigit
b77a7acd
AJ		 7179 | digits decdigit
7180 | digits hexdigit
64a0c779
DN		 7181
7182 decdigit [0-9]
7183
9306ca4a
JB		 7184 e04 e04 addOp e05
7185 | e05
7186
7187 e05 e05 binOp e06
b77a7acd 7188 | e06
64a0c779
DN		 7189
7190 e06 e06 mulOp e09
b77a7acd 7191 | e09
64a0c779
DN		 7192
7193 e09 OFFSET e10
a724f0f4
JB		 7194 | SHORT e10
7195 | + e10
7196 | - e10
9306ca4a
JB		 7197 | ~ e10
7198 | NOT e10
64a0c779
DN		 7199 | e09 PTR e10
7200 | e09 : e10
7201 | e10
7202
7203 e10 e10 [ expr ]
b77a7acd 7204 | e11
64a0c779
DN		 7205
7206 e11 ( expr )
b77a7acd 7207 | [ expr ]
64a0c779
DN		 7208 | constant
7209 | dataType
7210 | id
7211 | $
7212 | register
7213
a724f0f4 7214 => expr expr cmpOp e04
9306ca4a 7215 | e04
64a0c779
DN		 7216
7217 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 7218 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 7219
7220 hexdigit a | b | c | d | e | f
b77a7acd 7221 | A | B | C | D | E | F
64a0c779
DN		 7222
7223 id alpha
b77a7acd 7224 | id alpha
64a0c779
DN		 7225 | id decdigit
7226
9306ca4a 7227 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 7228
7229 quote " | '
7230
7231 register specialRegister
b77a7acd 7232 | gpRegister
64a0c779
DN		 7233 | byteRegister
7234
7235 segmentRegister CS | DS | ES | FS | GS | SS
7236
9306ca4a 7237 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 7238 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 7239 | TR3 | TR4 | TR5 | TR6 | TR7
7240
64a0c779
DN		 7241 We simplify the grammar in obvious places (e.g., register parsing is
7242 done by calling parse_register) and eliminate immediate left recursion
7243 to implement a recursive-descent parser.
7244
a724f0f4
JB		 7245 expr e04 expr'
7246
7247 expr' cmpOp e04 expr'
7248 | Empty
9306ca4a
JB		 7249
7250 e04 e05 e04'
7251
7252 e04' addOp e05 e04'
7253 | Empty
64a0c779
DN		 7254
7255 e05 e06 e05'
7256
9306ca4a 7257 e05' binOp e06 e05'
b77a7acd 7258 | Empty
64a0c779
DN		 7259
7260 e06 e09 e06'
7261
7262 e06' mulOp e09 e06'
b77a7acd 7263 | Empty
64a0c779
DN		 7264
7265 e09 OFFSET e10 e09'
a724f0f4
JB		 7266 | SHORT e10'
7267 | + e10'
7268 | - e10'
7269 | ~ e10'
7270 | NOT e10'
b77a7acd 7271 | e10 e09'
64a0c779
DN		 7272
7273 e09' PTR e10 e09'
b77a7acd 7274 | : e10 e09'
64a0c779
DN		 7275 | Empty
7276
7277 e10 e11 e10'
7278
7279 e10' [ expr ] e10'
b77a7acd 7280 | Empty
64a0c779
DN		 7281
7282 e11 ( expr )
b77a7acd 7283 | [ expr ]
64a0c779
DN		 7284 | BYTE
7285 | WORD
7286 | DWORD
9306ca4a 7287 | FWORD
64a0c779 7288 | QWORD
9306ca4a
JB		 7289 | TBYTE
7290 | OWORD
7291 | XMMWORD
64a0c779
DN		 7292 | .
7293 | $
7294 | register
7295 | id
7296 | constant */
7297
7298/* Parsing structure for the intel syntax parser. Used to implement the
7299 semantic actions for the operand grammar. */
7300struct intel_parser_s
7301 {
7302 char *op_string; /* The string being parsed. */
7303 int got_a_float; /* Whether the operand is a float. */
4a1805b1 7304 int op_modifier; /* Operand modifier. */
64a0c779 7305 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 7306 int in_offset; /* >=1 if parsing operand of offset. */
7307 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 7308 const reg_entry *reg; /* Last register reference found. */
7309 char *disp; /* Displacement string being built. */
a724f0f4 7310 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 7311 };
7312
7313static struct intel_parser_s intel_parser;
7314
7315/* Token structure for parsing intel syntax. */
7316struct intel_token
7317 {
7318 int code; /* Token code. */
7319 const reg_entry *reg; /* Register entry for register tokens. */
7320 char *str; /* String representation. */
7321 };
7322
7323static struct intel_token cur_token, prev_token;
7324
50705ef4
AM		 7325/* Token codes for the intel parser. Since T_SHORT is already used
7326 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 7327#define T_NIL -1
7328#define T_CONST 1
7329#define T_REG 2
7330#define T_BYTE 3
7331#define T_WORD 4
9306ca4a
JB		 7332#define T_DWORD 5
7333#define T_FWORD 6
7334#define T_QWORD 7
7335#define T_TBYTE 8
7336#define T_XMMWORD 9
50705ef4 7337#undef T_SHORT
9306ca4a
JB		 7338#define T_SHORT 10
7339#define T_OFFSET 11
7340#define T_PTR 12
7341#define T_ID 13
7342#define T_SHL 14
7343#define T_SHR 15
64a0c779
DN		 7344
7345/* Prototypes for intel parser functions. */
e3bb37b5
L		 7346static int intel_match_token (int);
7347static void intel_putback_token (void);
7348static void intel_get_token (void);
7349static int intel_expr (void);
7350static int intel_e04 (void);
7351static int intel_e05 (void);
7352static int intel_e06 (void);
7353static int intel_e09 (void);
7354static int intel_e10 (void);
7355static int intel_e11 (void);
64a0c779 7356
64a0c779 7357static int
e3bb37b5 7358i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 7359{
7360 int ret;
7361 char *p;
7362
a724f0f4
JB		 7363 p = intel_parser.op_string = xstrdup (operand_string);
7364 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
7365
7366 for (;;)
64a0c779 7367 {
a724f0f4
JB		 7368 /* Initialize token holders. */
7369 cur_token.code = prev_token.code = T_NIL;
7370 cur_token.reg = prev_token.reg = NULL;
7371 cur_token.str = prev_token.str = NULL;
7372
7373 /* Initialize parser structure. */
7374 intel_parser.got_a_float = got_a_float;
7375 intel_parser.op_modifier = 0;
7376 intel_parser.is_mem = 0;
7377 intel_parser.in_offset = 0;
7378 intel_parser.in_bracket = 0;
7379 intel_parser.reg = NULL;
7380 intel_parser.disp[0] = '\0';
7381 intel_parser.next_operand = NULL;
7382
7383 /* Read the first token and start the parser. */
7384 intel_get_token ();
7385 ret = intel_expr ();
7386
7387 if (!ret)
7388 break;
7389
9306ca4a
JB		 7390 if (cur_token.code != T_NIL)
7391 {
7392 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7393 current_templates->start->name, cur_token.str);
7394 ret = 0;
7395 }
64a0c779
DN		 7396 /* If we found a memory reference, hand it over to i386_displacement
7397 to fill in the rest of the operand fields. */
9306ca4a 7398 else if (intel_parser.is_mem)
64a0c779
DN		 7399 {
7400 if ((i.mem_operands == 1
40fb9820 7401 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 7402 || i.mem_operands == 2)
7403 {
7404 as_bad (_("too many memory references for '%s'"),
7405 current_templates->start->name);
7406 ret = 0;
7407 }
7408 else
7409 {
7410 char *s = intel_parser.disp;
7411 i.mem_operands++;
7412
a724f0f4
JB		 7413 if (!quiet_warnings && intel_parser.is_mem < 0)
7414 /* See the comments in intel_bracket_expr. */
7415 as_warn (_("Treating `%s' as memory reference"), operand_string);
7416
64a0c779
DN		 7417 /* Add the displacement expression. */
7418 if (*s != '\0')
a4622f40
AM		 7419 ret = i386_displacement (s, s + strlen (s));
7420 if (ret)
a724f0f4
JB		 7421 {
7422 /* Swap base and index in 16-bit memory operands like
7423 [si+bx]. Since i386_index_check is also used in AT&T
7424 mode we have to do that here. */
7425 if (i.base_reg
7426 && i.index_reg
40fb9820
L		 7427 && i.base_reg->reg_type.bitfield.reg16
7428 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 7429 && i.base_reg->reg_num >= 6
7430 && i.index_reg->reg_num < 6)
7431 {
7432 const reg_entry *base = i.index_reg;
7433
7434 i.index_reg = i.base_reg;
7435 i.base_reg = base;
7436 }
7437 ret = i386_index_check (operand_string);
7438 }
64a0c779
DN		 7439 }
7440 }
7441
7442 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 7443 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 7444 || intel_parser.reg == NULL)
7445 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 7446
7447 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 7448 ret = 0;
a724f0f4
JB		 7449 if (!ret || !intel_parser.next_operand)
7450 break;
7451 intel_parser.op_string = intel_parser.next_operand;
7452 this_operand = i.operands++;
64a0c779
DN		 7453 }
7454
7455 free (p);
7456 free (intel_parser.disp);
7457
7458 return ret;
7459}
7460
a724f0f4
JB		 7461#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7462
7463/* expr e04 expr'
7464
7465 expr' cmpOp e04 expr'
7466 | Empty */
64a0c779 7467static int
e3bb37b5 7468intel_expr (void)
64a0c779 7469{
a724f0f4
JB		 7470 /* XXX Implement the comparison operators. */
7471 return intel_e04 ();
9306ca4a
JB		 7472}
7473
a724f0f4 7474/* e04 e05 e04'
9306ca4a 7475
a724f0f4 7476 e04' addOp e05 e04'
9306ca4a
JB		 7477 | Empty */
7478static int
e3bb37b5 7479intel_e04 (void)
9306ca4a 7480{
a724f0f4 7481 int nregs = -1;
9306ca4a 7482
a724f0f4 7483 for (;;)
9306ca4a 7484 {
a724f0f4
JB		 7485 if (!intel_e05())
7486 return 0;
9306ca4a 7487
a724f0f4
JB		 7488 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7489 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 7490
a724f0f4
JB		 7491 if (cur_token.code == '+')
7492 nregs = -1;
7493 else if (cur_token.code == '-')
7494 nregs = NUM_ADDRESS_REGS;
7495 else
7496 return 1;
64a0c779 7497
a724f0f4
JB		 7498 strcat (intel_parser.disp, cur_token.str);
7499 intel_match_token (cur_token.code);
7500 }
64a0c779
DN		 7501}
7502
64a0c779
DN		 7503/* e05 e06 e05'
7504
9306ca4a 7505 e05' binOp e06 e05'
64a0c779
DN		 7506 | Empty */
7507static int
e3bb37b5 7508intel_e05 (void)
64a0c779 7509{
a724f0f4 7510 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 7511
a724f0f4 7512 for (;;)
64a0c779 7513 {
a724f0f4
JB		 7514 if (!intel_e06())
7515 return 0;
7516
4eed87de
AM		 7517 if (cur_token.code == '&'
7518 || cur_token.code == '|'
7519 || cur_token.code == '^')
a724f0f4
JB		 7520 {
7521 char str[2];
7522
7523 str[0] = cur_token.code;
7524 str[1] = 0;
7525 strcat (intel_parser.disp, str);
7526 }
7527 else
7528 break;
9306ca4a 7529
64a0c779
DN		 7530 intel_match_token (cur_token.code);
7531
a724f0f4
JB		 7532 if (nregs < 0)
7533 nregs = ~nregs;
64a0c779 7534 }
a724f0f4
JB		 7535 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7536 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
7537 return 1;
4a1805b1 7538}
64a0c779
DN		 7539
7540/* e06 e09 e06'
7541
7542 e06' mulOp e09 e06'
b77a7acd 7543 | Empty */
64a0c779 7544static int
e3bb37b5 7545intel_e06 (void)
64a0c779 7546{
a724f0f4 7547 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 7548
a724f0f4 7549 for (;;)
64a0c779 7550 {
a724f0f4
JB		 7551 if (!intel_e09())
7552 return 0;
9306ca4a 7553
4eed87de
AM		 7554 if (cur_token.code == '*'
7555 || cur_token.code == '/'
7556 || cur_token.code == '%')
a724f0f4
JB		 7557 {
7558 char str[2];
9306ca4a 7559
a724f0f4
JB		 7560 str[0] = cur_token.code;
7561 str[1] = 0;
7562 strcat (intel_parser.disp, str);
7563 }
7564 else if (cur_token.code == T_SHL)
7565 strcat (intel_parser.disp, "<<");
7566 else if (cur_token.code == T_SHR)
7567 strcat (intel_parser.disp, ">>");
7568 else
7569 break;
9306ca4a 7570
64e74474 7571 intel_match_token (cur_token.code);
64a0c779 7572
a724f0f4
JB		 7573 if (nregs < 0)
7574 nregs = ~nregs;
64a0c779 7575 }
a724f0f4
JB		 7576 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7577 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
7578 return 1;
64a0c779
DN		 7579}
7580
a724f0f4
JB		 7581/* e09 OFFSET e09
7582 | SHORT e09
7583 | + e09
7584 | - e09
7585 | ~ e09
7586 | NOT e09
9306ca4a
JB		 7587 | e10 e09'
7588
64a0c779 7589 e09' PTR e10 e09'
b77a7acd 7590 | : e10 e09'
64a0c779
DN		 7591 | Empty */
7592static int
e3bb37b5 7593intel_e09 (void)
64a0c779 7594{
a724f0f4
JB		 7595 int nregs = ~NUM_ADDRESS_REGS;
7596 int in_offset = 0;
7597
7598 for (;;)
64a0c779 7599 {
a724f0f4
JB		 7600 /* Don't consume constants here. */
7601 if (cur_token.code == '+' || cur_token.code == '-')
7602 {
7603 /* Need to look one token ahead - if the next token
7604 is a constant, the current token is its sign. */
7605 int next_code;
7606
7607 intel_match_token (cur_token.code);
7608 next_code = cur_token.code;
7609 intel_putback_token ();
7610 if (next_code == T_CONST)
7611 break;
7612 }
7613
7614 /* e09 OFFSET e09 */
7615 if (cur_token.code == T_OFFSET)
7616 {
7617 if (!in_offset++)
7618 ++intel_parser.in_offset;
7619 }
7620
7621 /* e09 SHORT e09 */
7622 else if (cur_token.code == T_SHORT)
7623 intel_parser.op_modifier |= 1 << T_SHORT;
7624
7625 /* e09 + e09 */
7626 else if (cur_token.code == '+')
7627 strcat (intel_parser.disp, "+");
7628
7629 /* e09 - e09
7630 | ~ e09
7631 | NOT e09 */
7632 else if (cur_token.code == '-' || cur_token.code == '~')
7633 {
7634 char str[2];
64a0c779 7635
a724f0f4
JB		 7636 if (nregs < 0)
7637 nregs = ~nregs;
7638 str[0] = cur_token.code;
7639 str[1] = 0;
7640 strcat (intel_parser.disp, str);
7641 }
7642
7643 /* e09 e10 e09' */
7644 else
7645 break;
7646
7647 intel_match_token (cur_token.code);
64a0c779
DN		 7648 }
7649
a724f0f4 7650 for (;;)
9306ca4a 7651 {
a724f0f4
JB		 7652 if (!intel_e10 ())
7653 return 0;
9306ca4a 7654
a724f0f4
JB		 7655 /* e09' PTR e10 e09' */
7656 if (cur_token.code == T_PTR)
7657 {
7658 char suffix;
9306ca4a 7659
a724f0f4
JB		 7660 if (prev_token.code == T_BYTE)
7661 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 7662
a724f0f4
JB		 7663 else if (prev_token.code == T_WORD)
7664 {
7665 if (current_templates->start->name[0] == 'l'
7666 && current_templates->start->name[2] == 's'
7667 && current_templates->start->name[3] == 0)
7668 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7669 else if (intel_parser.got_a_float == 2) /* "fi..." */
7670 suffix = SHORT_MNEM_SUFFIX;
7671 else
7672 suffix = WORD_MNEM_SUFFIX;
7673 }
64a0c779 7674
a724f0f4
JB		 7675 else if (prev_token.code == T_DWORD)
7676 {
7677 if (current_templates->start->name[0] == 'l'
7678 && current_templates->start->name[2] == 's'
7679 && current_templates->start->name[3] == 0)
7680 suffix = WORD_MNEM_SUFFIX;
7681 else if (flag_code == CODE_16BIT
40fb9820
L		 7682 && (current_templates->start->opcode_modifier.jump
7683 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 7684 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7685 else if (intel_parser.got_a_float == 1) /* "f..." */
7686 suffix = SHORT_MNEM_SUFFIX;
7687 else
7688 suffix = LONG_MNEM_SUFFIX;
7689 }
9306ca4a 7690
a724f0f4
JB		 7691 else if (prev_token.code == T_FWORD)
7692 {
7693 if (current_templates->start->name[0] == 'l'
7694 && current_templates->start->name[2] == 's'
7695 && current_templates->start->name[3] == 0)
7696 suffix = LONG_MNEM_SUFFIX;
7697 else if (!intel_parser.got_a_float)
7698 {
7699 if (flag_code == CODE_16BIT)
7700 add_prefix (DATA_PREFIX_OPCODE);
7701 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7702 }
7703 else
7704 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7705 }
64a0c779 7706
a724f0f4
JB		 7707 else if (prev_token.code == T_QWORD)
7708 {
7709 if (intel_parser.got_a_float == 1) /* "f..." */
7710 suffix = LONG_MNEM_SUFFIX;
7711 else
7712 suffix = QWORD_MNEM_SUFFIX;
7713 }
64a0c779 7714
a724f0f4
JB		 7715 else if (prev_token.code == T_TBYTE)
7716 {
7717 if (intel_parser.got_a_float == 1)
7718 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7719 else
7720 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7721 }
9306ca4a 7722
a724f0f4 7723 else if (prev_token.code == T_XMMWORD)
9306ca4a 7724 {
a724f0f4
JB		 7725 /* XXX ignored for now, but accepted since gcc uses it */
7726 suffix = 0;
9306ca4a 7727 }
64a0c779 7728
f16b83df 7729 else
a724f0f4
JB		 7730 {
7731 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
7732 return 0;
7733 }
7734
435acd52
JB		 7735 /* Operands for jump/call using 'ptr' notation denote absolute
7736 addresses. */
40fb9820
L		 7737 if (current_templates->start->opcode_modifier.jump
7738 || current_templates->start->opcode_modifier.jumpdword)
7739 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 7740
a724f0f4
JB		 7741 if (current_templates->start->base_opcode == 0x8d /* lea */)
7742 ;
7743 else if (!i.suffix)
7744 i.suffix = suffix;
7745 else if (i.suffix != suffix)
7746 {
7747 as_bad (_("Conflicting operand modifiers"));
7748 return 0;
7749 }
64a0c779 7750
9306ca4a
JB		 7751 }
7752
a724f0f4
JB		 7753 /* e09' : e10 e09' */
7754 else if (cur_token.code == ':')
9306ca4a 7755 {
a724f0f4
JB		 7756 if (prev_token.code != T_REG)
7757 {
7758 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7759 segment/group identifier (which we don't have), using comma
7760 as the operand separator there is even less consistent, since
7761 there all branches only have a single operand. */
7762 if (this_operand != 0
7763 || intel_parser.in_offset
7764 || intel_parser.in_bracket
40fb9820
L		 7765 || (!current_templates->start->opcode_modifier.jump
7766 && !current_templates->start->opcode_modifier.jumpdword
7767 && !current_templates->start->opcode_modifier.jumpintersegment
7768 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 7769 return intel_match_token (T_NIL);
7770 /* Remember the start of the 2nd operand and terminate 1st
7771 operand here.
7772 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7773 another expression), but it gets at least the simplest case
7774 (a plain number or symbol on the left side) right. */
7775 intel_parser.next_operand = intel_parser.op_string;
7776 *--intel_parser.op_string = '\0';
7777 return intel_match_token (':');
7778 }
9306ca4a 7779 }
64a0c779 7780
a724f0f4 7781 /* e09' Empty */
64a0c779 7782 else
a724f0f4 7783 break;
64a0c779 7784
a724f0f4
JB		 7785 intel_match_token (cur_token.code);
7786
7787 }
7788
7789 if (in_offset)
7790 {
7791 --intel_parser.in_offset;
7792 if (nregs < 0)
7793 nregs = ~nregs;
7794 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 7795 {
a724f0f4 7796 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 7797 return 0;
7798 }
a724f0f4
JB		 7799 intel_parser.op_modifier |= 1 << T_OFFSET;
7800 }
9306ca4a 7801
a724f0f4
JB		 7802 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7803 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7804 return 1;
7805}
64a0c779 7806
a724f0f4 7807static int
e3bb37b5 7808intel_bracket_expr (void)
a724f0f4
JB		 7809{
7810 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7811 const char *start = intel_parser.op_string;
7812 int len;
7813
7814 if (i.op[this_operand].regs)
7815 return intel_match_token (T_NIL);
7816
7817 intel_match_token ('[');
7818
7819 /* Mark as a memory operand only if it's not already known to be an
7820 offset expression. If it's an offset expression, we need to keep
7821 the brace in. */
7822 if (!intel_parser.in_offset)
7823 {
7824 ++intel_parser.in_bracket;
435acd52
JB		 7825
7826 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 7827 if (current_templates->start->opcode_modifier.jump
7828 || current_templates->start->opcode_modifier.jumpdword)
7829 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 7830
a724f0f4
JB		 7831 /* Unfortunately gas always diverged from MASM in a respect that can't
7832 be easily fixed without risking to break code sequences likely to be
7833 encountered (the testsuite even check for this): MASM doesn't consider
7834 an expression inside brackets unconditionally as a memory reference.
7835 When that is e.g. a constant, an offset expression, or the sum of the
7836 two, this is still taken as a constant load. gas, however, always
7837 treated these as memory references. As a compromise, we'll try to make
7838 offset expressions inside brackets work the MASM way (since that's
7839 less likely to be found in real world code), but make constants alone
7840 continue to work the traditional gas way. In either case, issue a
7841 warning. */
7842 intel_parser.op_modifier &= ~was_offset;
64a0c779 7843 }
a724f0f4 7844 else
64e74474 7845 strcat (intel_parser.disp, "[");
a724f0f4
JB		 7846
7847 /* Add a '+' to the displacement string if necessary. */
7848 if (*intel_parser.disp != '\0'
7849 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7850 strcat (intel_parser.disp, "+");
64a0c779 7851
a724f0f4
JB		 7852 if (intel_expr ()
7853 && (len = intel_parser.op_string - start - 1,
7854 intel_match_token (']')))
64a0c779 7855 {
a724f0f4
JB		 7856 /* Preserve brackets when the operand is an offset expression. */
7857 if (intel_parser.in_offset)
7858 strcat (intel_parser.disp, "]");
7859 else
7860 {
7861 --intel_parser.in_bracket;
7862 if (i.base_reg || i.index_reg)
7863 intel_parser.is_mem = 1;
7864 if (!intel_parser.is_mem)
7865 {
7866 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7867 /* Defer the warning until all of the operand was parsed. */
7868 intel_parser.is_mem = -1;
7869 else if (!quiet_warnings)
4eed87de
AM		 7870 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
7871 len, start, len, start);
a724f0f4
JB		 7872 }
7873 }
7874 intel_parser.op_modifier |= was_offset;
64a0c779 7875
a724f0f4 7876 return 1;
64a0c779 7877 }
a724f0f4 7878 return 0;
64a0c779
DN		 7879}
7880
7881/* e10 e11 e10'
7882
7883 e10' [ expr ] e10'
b77a7acd 7884 | Empty */
64a0c779 7885static int
e3bb37b5 7886intel_e10 (void)
64a0c779 7887{
a724f0f4
JB		 7888 if (!intel_e11 ())
7889 return 0;
64a0c779 7890
a724f0f4 7891 while (cur_token.code == '[')
64a0c779 7892 {
a724f0f4 7893 if (!intel_bracket_expr ())
21d6c4af 7894 return 0;
64a0c779
DN		 7895 }
7896
a724f0f4 7897 return 1;
64a0c779
DN		 7898}
7899
64a0c779 7900/* e11 ( expr )
b77a7acd 7901 | [ expr ]
64a0c779
DN		 7902 | BYTE
7903 | WORD
7904 | DWORD
9306ca4a 7905 | FWORD
64a0c779 7906 | QWORD
9306ca4a
JB		 7907 | TBYTE
7908 | OWORD
7909 | XMMWORD
4a1805b1 7910 | $
64a0c779
DN		 7911 | .
7912 | register
7913 | id
7914 | constant */
7915static int
e3bb37b5 7916intel_e11 (void)
64a0c779 7917{
a724f0f4 7918 switch (cur_token.code)
64a0c779 7919 {
a724f0f4
JB		 7920 /* e11 ( expr ) */
7921 case '(':
64a0c779
DN		 7922 intel_match_token ('(');
7923 strcat (intel_parser.disp, "(");
7924
7925 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7926 {
7927 strcat (intel_parser.disp, ")");
7928 return 1;
7929 }
a724f0f4 7930 return 0;
4a1805b1 7931
a724f0f4
JB		 7932 /* e11 [ expr ] */
7933 case '[':
a724f0f4 7934 return intel_bracket_expr ();
64a0c779 7935
a724f0f4
JB		 7936 /* e11 $
7937 | . */
7938 case '.':
64a0c779
DN		 7939 strcat (intel_parser.disp, cur_token.str);
7940 intel_match_token (cur_token.code);
21d6c4af
DN		 7941
7942 /* Mark as a memory operand only if it's not already known to be an
7943 offset expression. */
a724f0f4 7944 if (!intel_parser.in_offset)
21d6c4af 7945 intel_parser.is_mem = 1;
64a0c779
DN		 7946
7947 return 1;
64a0c779 7948
a724f0f4
JB		 7949 /* e11 register */
7950 case T_REG:
7951 {
7952 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7953
a724f0f4 7954 intel_match_token (T_REG);
64a0c779 7955
a724f0f4
JB		 7956 /* Check for segment change. */
7957 if (cur_token.code == ':')
7958 {
40fb9820
L		 7959 if (!reg->reg_type.bitfield.sreg2
7960 && !reg->reg_type.bitfield.sreg3)
a724f0f4 7961 {
4eed87de
AM		 7962 as_bad (_("`%s' is not a valid segment register"),
7963 reg->reg_name);
a724f0f4
JB		 7964 return 0;
7965 }
7966 else if (i.seg[i.mem_operands])
7967 as_warn (_("Extra segment override ignored"));
7968 else
7969 {
7970 if (!intel_parser.in_offset)
7971 intel_parser.is_mem = 1;
7972 switch (reg->reg_num)
7973 {
7974 case 0:
7975 i.seg[i.mem_operands] = &es;
7976 break;
7977 case 1:
7978 i.seg[i.mem_operands] = &cs;
7979 break;
7980 case 2:
7981 i.seg[i.mem_operands] = &ss;
7982 break;
7983 case 3:
7984 i.seg[i.mem_operands] = &ds;
7985 break;
7986 case 4:
7987 i.seg[i.mem_operands] = &fs;
7988 break;
7989 case 5:
7990 i.seg[i.mem_operands] = &gs;
7991 break;
7992 }
7993 }
7994 }
64a0c779 7995
a724f0f4
JB		 7996 /* Not a segment register. Check for register scaling. */
7997 else if (cur_token.code == '*')
7998 {
7999 if (!intel_parser.in_bracket)
8000 {
8001 as_bad (_("Register scaling only allowed in memory operands"));
8002 return 0;
8003 }
64a0c779 8004
40fb9820 8005 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 8006 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8007 else if (i.index_reg)
8008 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 8009
a724f0f4
JB		 8010 /* What follows must be a valid scale. */
8011 intel_match_token ('*');
8012 i.index_reg = reg;
40fb9820 8013 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 8014
a724f0f4
JB		 8015 /* Set the scale after setting the register (otherwise,
8016 i386_scale will complain) */
8017 if (cur_token.code == '+' || cur_token.code == '-')
8018 {
8019 char *str, sign = cur_token.code;
8020 intel_match_token (cur_token.code);
8021 if (cur_token.code != T_CONST)
8022 {
8023 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8024 cur_token.str);
8025 return 0;
8026 }
8027 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8028 strcpy (str + 1, cur_token.str);
8029 *str = sign;
8030 if (!i386_scale (str))
8031 return 0;
8032 free (str);
8033 }
8034 else if (!i386_scale (cur_token.str))
64a0c779 8035 return 0;
a724f0f4
JB		 8036 intel_match_token (cur_token.code);
8037 }
64a0c779 8038
a724f0f4
JB		 8039 /* No scaling. If this is a memory operand, the register is either a
8040 base register (first occurrence) or an index register (second
8041 occurrence). */
7b0441f6 8042 else if (intel_parser.in_bracket)
a724f0f4 8043 {
64a0c779 8044
a724f0f4
JB		 8045 if (!i.base_reg)
8046 i.base_reg = reg;
8047 else if (!i.index_reg)
8048 i.index_reg = reg;
8049 else
8050 {
8051 as_bad (_("Too many register references in memory operand"));
8052 return 0;
8053 }
64a0c779 8054
40fb9820 8055 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 8056 }
4a1805b1 8057
4d1bb795
JB		 8058 /* It's neither base nor index. */
8059 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 8060 {
40fb9820
L		 8061 i386_operand_type temp = reg->reg_type;
8062 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8063 i.types[this_operand] = operand_type_or (i.types[this_operand],
8064 temp);
a724f0f4
JB		 8065 i.op[this_operand].regs = reg;
8066 i.reg_operands++;
8067 }
8068 else
8069 {
8070 as_bad (_("Invalid use of register"));
8071 return 0;
8072 }
64a0c779 8073
a724f0f4
JB		 8074 /* Since registers are not part of the displacement string (except
8075 when we're parsing offset operands), we may need to remove any
8076 preceding '+' from the displacement string. */
8077 if (*intel_parser.disp != '\0'
8078 && !intel_parser.in_offset)
8079 {
8080 char *s = intel_parser.disp;
8081 s += strlen (s) - 1;
8082 if (*s == '+')
8083 *s = '\0';
8084 }
4a1805b1 8085
a724f0f4
JB		 8086 return 1;
8087 }
8088
8089 /* e11 BYTE
8090 | WORD
8091 | DWORD
8092 | FWORD
8093 | QWORD
8094 | TBYTE
8095 | OWORD
8096 | XMMWORD */
8097 case T_BYTE:
8098 case T_WORD:
8099 case T_DWORD:
8100 case T_FWORD:
8101 case T_QWORD:
8102 case T_TBYTE:
8103 case T_XMMWORD:
8104 intel_match_token (cur_token.code);
64a0c779 8105
a724f0f4
JB		 8106 if (cur_token.code == T_PTR)
8107 return 1;
8108
8109 /* It must have been an identifier. */
8110 intel_putback_token ();
8111 cur_token.code = T_ID;
8112 /* FALLTHRU */
8113
8114 /* e11 id
8115 | constant */
8116 case T_ID:
8117 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 8118 {
8119 symbolS *symbolP;
8120
a724f0f4
JB		 8121 /* The identifier represents a memory reference only if it's not
8122 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 8123 symbolP = symbol_find(cur_token.str);
8124 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8125 intel_parser.is_mem = 1;
8126 }
a724f0f4 8127 /* FALLTHRU */
64a0c779 8128
a724f0f4
JB		 8129 case T_CONST:
8130 case '-':
8131 case '+':
8132 {
8133 char *save_str, sign = 0;
64a0c779 8134
a724f0f4
JB		 8135 /* Allow constants that start with `+' or `-'. */
8136 if (cur_token.code == '-' || cur_token.code == '+')
8137 {
8138 sign = cur_token.code;
8139 intel_match_token (cur_token.code);
8140 if (cur_token.code != T_CONST)
8141 {
8142 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8143 cur_token.str);
8144 return 0;
8145 }
8146 }
64a0c779 8147
a724f0f4
JB		 8148 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8149 strcpy (save_str + !!sign, cur_token.str);
8150 if (sign)
8151 *save_str = sign;
64a0c779 8152
a724f0f4
JB		 8153 /* Get the next token to check for register scaling. */
8154 intel_match_token (cur_token.code);
64a0c779 8155
4eed87de
AM		 8156 /* Check if this constant is a scaling factor for an
8157 index register. */
a724f0f4
JB		 8158 if (cur_token.code == '*')
8159 {
8160 if (intel_match_token ('*') && cur_token.code == T_REG)
8161 {
8162 const reg_entry *reg = cur_token.reg;
8163
8164 if (!intel_parser.in_bracket)
8165 {
4eed87de
AM		 8166 as_bad (_("Register scaling only allowed "
8167 "in memory operands"));
a724f0f4
JB		 8168 return 0;
8169 }
8170
4eed87de
AM		 8171 /* Disallow things like [1*si].
8172 sp and esp are invalid as index. */
40fb9820 8173 if (reg->reg_type.bitfield.reg16)
4eed87de 8174 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 8175 else if (i.index_reg)
4eed87de 8176 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 8177
8178 /* The constant is followed by `* reg', so it must be
8179 a valid scale. */
8180 i.index_reg = reg;
40fb9820 8181 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 8182
8183 /* Set the scale after setting the register (otherwise,
8184 i386_scale will complain) */
8185 if (!i386_scale (save_str))
64a0c779 8186 return 0;
a724f0f4
JB		 8187 intel_match_token (T_REG);
8188
8189 /* Since registers are not part of the displacement
8190 string, we may need to remove any preceding '+' from
8191 the displacement string. */
8192 if (*intel_parser.disp != '\0')
8193 {
8194 char *s = intel_parser.disp;
8195 s += strlen (s) - 1;
8196 if (*s == '+')
8197 *s = '\0';
8198 }
8199
8200 free (save_str);
8201
8202 return 1;
8203 }
64a0c779 8204
a724f0f4
JB		 8205 /* The constant was not used for register scaling. Since we have
8206 already consumed the token following `*' we now need to put it
8207 back in the stream. */
64a0c779 8208 intel_putback_token ();
a724f0f4 8209 }
64a0c779 8210
a724f0f4
JB		 8211 /* Add the constant to the displacement string. */
8212 strcat (intel_parser.disp, save_str);
8213 free (save_str);
64a0c779 8214
a724f0f4
JB		 8215 return 1;
8216 }
64a0c779
DN		 8217 }
8218
64a0c779
DN		 8219 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8220 return 0;
8221}
8222
64a0c779
DN		 8223/* Match the given token against cur_token. If they match, read the next
8224 token from the operand string. */
8225static int
e3bb37b5 8226intel_match_token (int code)
64a0c779
DN		 8227{
8228 if (cur_token.code == code)
8229 {
8230 intel_get_token ();
8231 return 1;
8232 }
8233 else
8234 {
0477af35 8235 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 8236 return 0;
8237 }
8238}
8239
64a0c779
DN		 8240/* Read a new token from intel_parser.op_string and store it in cur_token. */
8241static void
e3bb37b5 8242intel_get_token (void)
64a0c779
DN		 8243{
8244 char *end_op;
8245 const reg_entry *reg;
8246 struct intel_token new_token;
8247
8248 new_token.code = T_NIL;
8249 new_token.reg = NULL;
8250 new_token.str = NULL;
8251
4a1805b1 8252 /* Free the memory allocated to the previous token and move
64a0c779
DN		 8253 cur_token to prev_token. */
8254 if (prev_token.str)
8255 free (prev_token.str);
8256
8257 prev_token = cur_token;
8258
8259 /* Skip whitespace. */
8260 while (is_space_char (*intel_parser.op_string))
8261 intel_parser.op_string++;
8262
8263 /* Return an empty token if we find nothing else on the line. */
8264 if (*intel_parser.op_string == '\0')
8265 {
8266 cur_token = new_token;
8267 return;
8268 }
8269
8270 /* The new token cannot be larger than the remainder of the operand
8271 string. */
a724f0f4 8272 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 8273 new_token.str[0] = '\0';
8274
8275 if (strchr ("0123456789", *intel_parser.op_string))
8276 {
8277 char *p = new_token.str;
8278 char *q = intel_parser.op_string;
8279 new_token.code = T_CONST;
8280
8281 /* Allow any kind of identifier char to encompass floating point and
8282 hexadecimal numbers. */
8283 while (is_identifier_char (*q))
8284 *p++ = *q++;
8285 *p = '\0';
8286
8287 /* Recognize special symbol names [0-9][bf]. */
8288 if (strlen (intel_parser.op_string) == 2
4a1805b1 8289 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 8290 || intel_parser.op_string[1] == 'f'))
8291 new_token.code = T_ID;
8292 }
8293
4d1bb795 8294 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 8295 {
4d1bb795
JB		 8296 size_t len = end_op - intel_parser.op_string;
8297
64a0c779
DN		 8298 new_token.code = T_REG;
8299 new_token.reg = reg;
8300
4d1bb795
JB		 8301 memcpy (new_token.str, intel_parser.op_string, len);
8302 new_token.str[len] = '\0';
64a0c779
DN		 8303 }
8304
8305 else if (is_identifier_char (*intel_parser.op_string))
8306 {
8307 char *p = new_token.str;
8308 char *q = intel_parser.op_string;
8309
8310 /* A '.' or '$' followed by an identifier char is an identifier.
8311 Otherwise, it's operator '.' followed by an expression. */
8312 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
8313 {
9306ca4a
JB		 8314 new_token.code = '.';
8315 new_token.str[0] = '.';
64a0c779
DN		 8316 new_token.str[1] = '\0';
8317 }
8318 else
8319 {
8320 while (is_identifier_char (*q) || *q == '@')
8321 *p++ = *q++;
8322 *p = '\0';
8323
9306ca4a
JB		 8324 if (strcasecmp (new_token.str, "NOT") == 0)
8325 new_token.code = '~';
8326
8327 else if (strcasecmp (new_token.str, "MOD") == 0)
8328 new_token.code = '%';
8329
8330 else if (strcasecmp (new_token.str, "AND") == 0)
8331 new_token.code = '&';
8332
8333 else if (strcasecmp (new_token.str, "OR") == 0)
8334 new_token.code = '|';
8335
8336 else if (strcasecmp (new_token.str, "XOR") == 0)
8337 new_token.code = '^';
8338
8339 else if (strcasecmp (new_token.str, "SHL") == 0)
8340 new_token.code = T_SHL;
8341
8342 else if (strcasecmp (new_token.str, "SHR") == 0)
8343 new_token.code = T_SHR;
8344
8345 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 8346 new_token.code = T_BYTE;
8347
8348 else if (strcasecmp (new_token.str, "WORD") == 0)
8349 new_token.code = T_WORD;
8350
8351 else if (strcasecmp (new_token.str, "DWORD") == 0)
8352 new_token.code = T_DWORD;
8353
9306ca4a
JB		 8354 else if (strcasecmp (new_token.str, "FWORD") == 0)
8355 new_token.code = T_FWORD;
8356
64a0c779
DN		 8357 else if (strcasecmp (new_token.str, "QWORD") == 0)
8358 new_token.code = T_QWORD;
8359
9306ca4a
JB		 8360 else if (strcasecmp (new_token.str, "TBYTE") == 0
8361 /* XXX remove (gcc still uses it) */
8362 || strcasecmp (new_token.str, "XWORD") == 0)
8363 new_token.code = T_TBYTE;
8364
8365 else if (strcasecmp (new_token.str, "XMMWORD") == 0
8366 || strcasecmp (new_token.str, "OWORD") == 0)
8367 new_token.code = T_XMMWORD;
64a0c779
DN		 8368
8369 else if (strcasecmp (new_token.str, "PTR") == 0)
8370 new_token.code = T_PTR;
8371
8372 else if (strcasecmp (new_token.str, "SHORT") == 0)
8373 new_token.code = T_SHORT;
8374
8375 else if (strcasecmp (new_token.str, "OFFSET") == 0)
8376 {
8377 new_token.code = T_OFFSET;
8378
8379 /* ??? This is not mentioned in the MASM grammar but gcc
8380 makes use of it with -mintel-syntax. OFFSET may be
8381 followed by FLAT: */
8382 if (strncasecmp (q, " FLAT:", 6) == 0)
8383 strcat (new_token.str, " FLAT:");
8384 }
8385
8386 /* ??? This is not mentioned in the MASM grammar. */
8387 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 8388 {
8389 new_token.code = T_OFFSET;
8390 if (*q == ':')
8391 strcat (new_token.str, ":");
8392 else
8393 as_bad (_("`:' expected"));
8394 }
64a0c779
DN		 8395
8396 else
8397 new_token.code = T_ID;
8398 }
8399 }
8400
9306ca4a
JB		 8401 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
8402 {
8403 new_token.code = *intel_parser.op_string;
8404 new_token.str[0] = *intel_parser.op_string;
8405 new_token.str[1] = '\0';
8406 }
8407
8408 else if (strchr ("<>", *intel_parser.op_string)
8409 && *intel_parser.op_string == *(intel_parser.op_string + 1))
8410 {
8411 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
8412 new_token.str[0] = *intel_parser.op_string;
8413 new_token.str[1] = *intel_parser.op_string;
8414 new_token.str[2] = '\0';
8415 }
8416
64a0c779 8417 else
0477af35 8418 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 8419
8420 intel_parser.op_string += strlen (new_token.str);
8421 cur_token = new_token;
8422}
8423
64a0c779
DN		 8424/* Put cur_token back into the token stream and make cur_token point to
8425 prev_token. */
8426static void
e3bb37b5 8427intel_putback_token (void)
64a0c779 8428{
a724f0f4
JB		 8429 if (cur_token.code != T_NIL)
8430 {
8431 intel_parser.op_string -= strlen (cur_token.str);
8432 free (cur_token.str);
8433 }
64a0c779 8434 cur_token = prev_token;
4a1805b1 8435
64a0c779
DN		 8436 /* Forget prev_token. */
8437 prev_token.code = T_NIL;
8438 prev_token.reg = NULL;
8439 prev_token.str = NULL;
8440}
54cfded0 8441
a4447b93 8442int
1df69f4f 8443tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 8444{
8445 unsigned int regnum;
8446 unsigned int regnames_count;
089dfecd 8447 static const char *const regnames_32[] =
54cfded0 8448 {
a4447b93
RH		 8449 "eax", "ecx", "edx", "ebx",
8450 "esp", "ebp", "esi", "edi",
089dfecd
JB		 8451 "eip", "eflags", NULL,
8452 "st0", "st1", "st2", "st3",
8453 "st4", "st5", "st6", "st7",
8454 NULL, NULL,
8455 "xmm0", "xmm1", "xmm2", "xmm3",
8456 "xmm4", "xmm5", "xmm6", "xmm7",
8457 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8458 "mm4", "mm5", "mm6", "mm7",
8459 "fcw", "fsw", "mxcsr",
8460 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8461 "tr", "ldtr"
54cfded0 8462 };
089dfecd 8463 static const char *const regnames_64[] =
54cfded0 8464 {
089dfecd
JB		 8465 "rax", "rdx", "rcx", "rbx",
8466 "rsi", "rdi", "rbp", "rsp",
8467 "r8", "r9", "r10", "r11",
54cfded0 8468 "r12", "r13", "r14", "r15",
089dfecd
JB		 8469 "rip",
8470 "xmm0", "xmm1", "xmm2", "xmm3",
8471 "xmm4", "xmm5", "xmm6", "xmm7",
8472 "xmm8", "xmm9", "xmm10", "xmm11",
8473 "xmm12", "xmm13", "xmm14", "xmm15",
8474 "st0", "st1", "st2", "st3",
8475 "st4", "st5", "st6", "st7",
8476 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8477 "mm4", "mm5", "mm6", "mm7",
8478 "rflags",
8479 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8480 "fs.base", "gs.base", NULL, NULL,
8481 "tr", "ldtr",
8482 "mxcsr", "fcw", "fsw"
54cfded0 8483 };
089dfecd 8484 const char *const *regnames;
54cfded0
AM		 8485
8486 if (flag_code == CODE_64BIT)
8487 {
8488 regnames = regnames_64;
0cea6190 8489 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 8490 }
8491 else
8492 {
8493 regnames = regnames_32;
0cea6190 8494 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 8495 }
8496
8497 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 8498 if (regnames[regnum] != NULL
8499 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 8500 return regnum;
8501
54cfded0
AM		 8502 return -1;
8503}
8504
8505void
8506tc_x86_frame_initial_instructions (void)
8507{
a4447b93
RH		 8508 static unsigned int sp_regno;
8509
8510 if (!sp_regno)
8511 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
8512 ? "rsp" : "esp");
8513
8514 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
8515 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8516}
d2b2c203
DJ		 8517
8518int
8519i386_elf_section_type (const char *str, size_t len)
8520{
8521 if (flag_code == CODE_64BIT
8522 && len == sizeof ("unwind") - 1
8523 && strncmp (str, "unwind", 6) == 0)
8524 return SHT_X86_64_UNWIND;
8525
8526 return -1;
8527}
bb41ade5
AM		 8528
8529#ifdef TE_PE
8530void
8531tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8532{
8533 expressionS expr;
8534
8535 expr.X_op = O_secrel;
8536 expr.X_add_symbol = symbol;
8537 expr.X_add_number = 0;
8538 emit_expr (&expr, size);
8539}
8540#endif
3b22753a
L		 8541
8542#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8543/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8544
8545int
8546x86_64_section_letter (int letter, char **ptr_msg)
8547{
8548 if (flag_code == CODE_64BIT)
8549 {
8550 if (letter == 'l')
8551 return SHF_X86_64_LARGE;
8552
8553 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8554 }
3b22753a 8555 else
64e74474 8556 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8557 return -1;
8558}
8559
8560int
8561x86_64_section_word (char *str, size_t len)
8562{
8620418b 8563 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8564 return SHF_X86_64_LARGE;
8565
8566 return -1;
8567}
8568
8569static void
8570handle_large_common (int small ATTRIBUTE_UNUSED)
8571{
8572 if (flag_code != CODE_64BIT)
8573 {
8574 s_comm_internal (0, elf_common_parse);
8575 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8576 }
8577 else
8578 {
8579 static segT lbss_section;
8580 asection *saved_com_section_ptr = elf_com_section_ptr;
8581 asection *saved_bss_section = bss_section;
8582
8583 if (lbss_section == NULL)
8584 {
8585 flagword applicable;
8586 segT seg = now_seg;
8587 subsegT subseg = now_subseg;
8588
8589 /* The .lbss section is for local .largecomm symbols. */
8590 lbss_section = subseg_new (".lbss", 0);
8591 applicable = bfd_applicable_section_flags (stdoutput);
8592 bfd_set_section_flags (stdoutput, lbss_section,
8593 applicable & SEC_ALLOC);
8594 seg_info (lbss_section)->bss = 1;
8595
8596 subseg_set (seg, subseg);
8597 }
8598
8599 elf_com_section_ptr = &_bfd_elf_large_com_section;
8600 bss_section = lbss_section;
8601
8602 s_comm_internal (0, elf_common_parse);
8603
8604 elf_com_section_ptr = saved_com_section_ptr;
8605 bss_section = saved_bss_section;
8606 }
8607}
8608#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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