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2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5dd15031 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
e3bb37b5
L		 58static void set_code_flag (int);
59static void set_16bit_gcc_code_flag (int);
60static void set_intel_syntax (int);
1efbbeb4 61static void set_intel_mnemonic (int);
db51cc60 62static void set_allow_index_reg (int);
e3bb37b5 63static void set_cpu_arch (int);
6482c264 64#ifdef TE_PE
e3bb37b5 65static void pe_directive_secrel (int);
6482c264 66#endif
e3bb37b5
L		 67static void signed_cons (int);
68static char *output_invalid (int c);
a7619375 69static int i386_att_operand (char *);
e3bb37b5
L		 70static int i386_intel_operand (char *, int);
71static const reg_entry *parse_register (char *, char **);
72static char *parse_insn (char *, char *);
73static char *parse_operands (char *, const char *);
74static void swap_operands (void);
4d456e3d 75static void swap_2_operands (int, int);
e3bb37b5
L		 76static void optimize_imm (void);
77static void optimize_disp (void);
78static int match_template (void);
79static int check_string (void);
80static int process_suffix (void);
81static int check_byte_reg (void);
82static int check_long_reg (void);
83static int check_qword_reg (void);
84static int check_word_reg (void);
85static int finalize_imm (void);
85f10a01 86static void process_drex (void);
e3bb37b5
L		 87static int process_operands (void);
88static const seg_entry *build_modrm_byte (void);
89static void output_insn (void);
90static void output_imm (fragS *, offsetT);
91static void output_disp (fragS *, offsetT);
29b0f896 92#ifndef I386COFF
e3bb37b5 93static void s_bss (int);
252b5132 94#endif
17d4e2a2
L		 95#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
96static void handle_large_common (int small ATTRIBUTE_UNUSED);
97#endif
252b5132 98
a847613f 99static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 100
252b5132 101/* 'md_assemble ()' gathers together information and puts it into a
47926f60 102 i386_insn. */
252b5132 103
520dc8e8
AM		 104union i386_op
105 {
106 expressionS *disps;
107 expressionS *imms;
108 const reg_entry *regs;
109 };
110
252b5132
RH		 111struct _i386_insn
112 {
47926f60 113 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 114 template tm;
115
7d5e4556
L		 116 /* SUFFIX holds the instruction size suffix for byte, word, dword
117 or qword, if given. */
252b5132
RH		 118 char suffix;
119
47926f60 120 /* OPERANDS gives the number of given operands. */
252b5132
RH		 121 unsigned int operands;
122
123 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
124 of given register, displacement, memory operands and immediate
47926f60 125 operands. */
252b5132
RH		 126 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
127
128 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 129 use OP[i] for the corresponding operand. */
40fb9820 130 i386_operand_type types[MAX_OPERANDS];
252b5132 131
520dc8e8
AM		 132 /* Displacement expression, immediate expression, or register for each
133 operand. */
134 union i386_op op[MAX_OPERANDS];
252b5132 135
3e73aa7c
JH		 136 /* Flags for operands. */
137 unsigned int flags[MAX_OPERANDS];
138#define Operand_PCrel 1
139
252b5132 140 /* Relocation type for operand */
f86103b7 141 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 142
252b5132
RH		 143 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
144 the base index byte below. */
145 const reg_entry *base_reg;
146 const reg_entry *index_reg;
147 unsigned int log2_scale_factor;
148
149 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 150 explicit segment overrides are given. */
ce8a8b2f 151 const seg_entry *seg[2];
252b5132
RH		 152
153 /* PREFIX holds all the given prefix opcodes (usually null).
154 PREFIXES is the number of prefix opcodes. */
155 unsigned int prefixes;
156 unsigned char prefix[MAX_PREFIXES];
157
158 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 159 addressing modes of this insn are encoded. DREX is the byte
160 added by the SSE5 instructions. */
252b5132
RH		 161
162 modrm_byte rm;
3e73aa7c 163 rex_byte rex;
252b5132 164 sib_byte sib;
85f10a01 165 drex_byte drex;
252b5132
RH		 166 };
167
168typedef struct _i386_insn i386_insn;
169
170/* List of chars besides those in app.c:symbol_chars that can start an
171 operand. Used to prevent the scrubber eating vital white-space. */
32137342 172const char extra_symbol_chars[] = "*%-(["
252b5132 173#ifdef LEX_AT
32137342
NC		 174 "@"
175#endif
176#ifdef LEX_QM
177 "?"
252b5132 178#endif
32137342 179 ;
252b5132 180
29b0f896
AM		 181#if (defined (TE_I386AIX) \
182 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 183 && !defined (TE_GNU) \
29b0f896 184 && !defined (TE_LINUX) \
32137342 185 && !defined (TE_NETWARE) \
29b0f896
AM		 186 && !defined (TE_FreeBSD) \
187 && !defined (TE_NetBSD)))
252b5132 188/* This array holds the chars that always start a comment. If the
b3b91714
AM		 189 pre-processor is disabled, these aren't very useful. The option
190 --divide will remove '/' from this list. */
191const char *i386_comment_chars = "#/";
192#define SVR4_COMMENT_CHARS 1
252b5132 193#define PREFIX_SEPARATOR '\\'
252b5132 194
b3b91714
AM		 195#else
196const char *i386_comment_chars = "#";
197#define PREFIX_SEPARATOR '/'
198#endif
199
252b5132
RH		 200/* This array holds the chars that only start a comment at the beginning of
201 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 202 .line and .file directives will appear in the pre-processed output.
203 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 204 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 205 #NO_APP at the beginning of its output.
206 Also note that comments started like this one will always work if
252b5132 207 '/' isn't otherwise defined. */
b3b91714 208const char line_comment_chars[] = "#/";
252b5132 209
63a0b638 210const char line_separator_chars[] = ";";
252b5132 211
ce8a8b2f
AM		 212/* Chars that can be used to separate mant from exp in floating point
213 nums. */
252b5132
RH		 214const char EXP_CHARS[] = "eE";
215
ce8a8b2f
AM		 216/* Chars that mean this number is a floating point constant
217 As in 0f12.456
218 or 0d1.2345e12. */
252b5132
RH		 219const char FLT_CHARS[] = "fFdDxX";
220
ce8a8b2f 221/* Tables for lexical analysis. */
252b5132
RH		 222static char mnemonic_chars[256];
223static char register_chars[256];
224static char operand_chars[256];
225static char identifier_chars[256];
226static char digit_chars[256];
227
ce8a8b2f 228/* Lexical macros. */
252b5132
RH		 229#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
230#define is_operand_char(x) (operand_chars[(unsigned char) x])
231#define is_register_char(x) (register_chars[(unsigned char) x])
232#define is_space_char(x) ((x) == ' ')
233#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
234#define is_digit_char(x) (digit_chars[(unsigned char) x])
235
0234cb7c 236/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 237static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
238
239/* md_assemble() always leaves the strings it's passed unaltered. To
240 effect this we maintain a stack of saved characters that we've smashed
241 with '\0's (indicating end of strings for various sub-fields of the
47926f60 242 assembler instruction). */
252b5132 243static char save_stack[32];
ce8a8b2f 244static char *save_stack_p;
252b5132
RH		 245#define END_STRING_AND_SAVE(s) \
246 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
247#define RESTORE_END_STRING(s) \
248 do { *(s) = *--save_stack_p; } while (0)
249
47926f60 250/* The instruction we're assembling. */
252b5132
RH		 251static i386_insn i;
252
253/* Possible templates for current insn. */
254static const templates *current_templates;
255
31b2323c
L		 256/* Per instruction expressionS buffers: max displacements & immediates. */
257static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
258static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 259
47926f60
KH		 260/* Current operand we are working on. */
261static int this_operand;
252b5132 262
3e73aa7c
JH		 263/* We support four different modes. FLAG_CODE variable is used to distinguish
264 these. */
265
266enum flag_code {
267 CODE_32BIT,
268 CODE_16BIT,
269 CODE_64BIT };
270
271static enum flag_code flag_code;
4fa24527 272static unsigned int object_64bit;
3e73aa7c
JH		 273static int use_rela_relocations = 0;
274
275/* The names used to print error messages. */
b77a7acd 276static const char *flag_code_names[] =
3e73aa7c
JH		 277 {
278 "32",
279 "16",
280 "64"
281 };
252b5132 282
47926f60
KH		 283/* 1 for intel syntax,
284 0 if att syntax. */
285static int intel_syntax = 0;
252b5132 286
1efbbeb4
L		 287/* 1 for intel mnemonic,
288 0 if att mnemonic. */
289static int intel_mnemonic = !SYSV386_COMPAT;
290
5209009a 291/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 292static int old_gcc = OLDGCC_COMPAT;
293
47926f60
KH		 294/* 1 if register prefix % not required. */
295static int allow_naked_reg = 0;
252b5132 296
ba104c83 297/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 298static int allow_index_reg = 0;
299
2ca3ace5
L		 300/* Register prefix used for error message. */
301static const char *register_prefix = "%";
302
47926f60
KH		 303/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
304 leave, push, and pop instructions so that gcc has the same stack
305 frame as in 32 bit mode. */
306static char stackop_size = '\0';
eecb386c 307
12b55ccc
L		 308/* Non-zero to optimize code alignment. */
309int optimize_align_code = 1;
310
47926f60
KH		 311/* Non-zero to quieten some warnings. */
312static int quiet_warnings = 0;
a38cf1db 313
47926f60
KH		 314/* CPU name. */
315static const char *cpu_arch_name = NULL;
5c6af06e 316static const char *cpu_sub_arch_name = NULL;
a38cf1db 317
47926f60 318/* CPU feature flags. */
40fb9820
L		 319static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
320
ccc9c027
L		 321/* If we have selected a cpu we are generating instructions for. */
322static int cpu_arch_tune_set = 0;
323
9103f4f4
L		 324/* Cpu we are generating instructions for. */
325static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
326
327/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 328static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 329
ccc9c027
L		 330/* CPU instruction set architecture used. */
331static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
332
9103f4f4 333/* CPU feature flags of instruction set architecture used. */
40fb9820 334static i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 335
fddf5b5b
AM		 336/* If set, conditional jumps are not automatically promoted to handle
337 larger than a byte offset. */
338static unsigned int no_cond_jump_promotion = 0;
339
29b0f896 340/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 341static symbolS *GOT_symbol;
29b0f896 342
a4447b93
RH		 343/* The dwarf2 return column, adjusted for 32 or 64 bit. */
344unsigned int x86_dwarf2_return_column;
345
346/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
347int x86_cie_data_alignment;
348
252b5132 349/* Interface to relax_segment.
fddf5b5b
AM		 350 There are 3 major relax states for 386 jump insns because the
351 different types of jumps add different sizes to frags when we're
352 figuring out what sort of jump to choose to reach a given label. */
252b5132 353
47926f60 354/* Types. */
93c2a809
AM		 355#define UNCOND_JUMP 0
356#define COND_JUMP 1
357#define COND_JUMP86 2
fddf5b5b 358
47926f60 359/* Sizes. */
252b5132
RH		 360#define CODE16 1
361#define SMALL 0
29b0f896 362#define SMALL16 (SMALL | CODE16)
252b5132 363#define BIG 2
29b0f896 364#define BIG16 (BIG | CODE16)
252b5132
RH		 365
366#ifndef INLINE
367#ifdef __GNUC__
368#define INLINE __inline__
369#else
370#define INLINE
371#endif
372#endif
373
fddf5b5b
AM		 374#define ENCODE_RELAX_STATE(type, size) \
375 ((relax_substateT) (((type) << 2) | (size)))
376#define TYPE_FROM_RELAX_STATE(s) \
377 ((s) >> 2)
378#define DISP_SIZE_FROM_RELAX_STATE(s) \
379 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 380
381/* This table is used by relax_frag to promote short jumps to long
382 ones where necessary. SMALL (short) jumps may be promoted to BIG
383 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
384 don't allow a short jump in a 32 bit code segment to be promoted to
385 a 16 bit offset jump because it's slower (requires data size
386 prefix), and doesn't work, unless the destination is in the bottom
387 64k of the code segment (The top 16 bits of eip are zeroed). */
388
389const relax_typeS md_relax_table[] =
390{
24eab124
AM		 391 /* The fields are:
392 1) most positive reach of this state,
393 2) most negative reach of this state,
93c2a809 394 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 395 4) which index into the table to try if we can't fit into this one. */
252b5132 396
fddf5b5b 397 /* UNCOND_JUMP states. */
93c2a809
AM		 398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
400 /* dword jmp adds 4 bytes to frag:
401 0 extra opcode bytes, 4 displacement bytes. */
252b5132 402 {0, 0, 4, 0},
93c2a809
AM		 403 /* word jmp adds 2 byte2 to frag:
404 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 405 {0, 0, 2, 0},
406
93c2a809
AM		 407 /* COND_JUMP states. */
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
410 /* dword conditionals adds 5 bytes to frag:
411 1 extra opcode byte, 4 displacement bytes. */
412 {0, 0, 5, 0},
fddf5b5b 413 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 414 1 extra opcode byte, 2 displacement bytes. */
415 {0, 0, 3, 0},
416
417 /* COND_JUMP86 states. */
418 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
419 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
420 /* dword conditionals adds 5 bytes to frag:
421 1 extra opcode byte, 4 displacement bytes. */
422 {0, 0, 5, 0},
423 /* word conditionals add 4 bytes to frag:
424 1 displacement byte and a 3 byte long branch insn. */
425 {0, 0, 4, 0}
252b5132
RH		 426};
427
9103f4f4
L		 428static const arch_entry cpu_arch[] =
429{
430 {"generic32", PROCESSOR_GENERIC32,
40fb9820 431 CPU_GENERIC32_FLAGS },
9103f4f4 432 {"generic64", PROCESSOR_GENERIC64,
40fb9820 433 CPU_GENERIC64_FLAGS },
9103f4f4 434 {"i8086", PROCESSOR_UNKNOWN,
40fb9820 435 CPU_NONE_FLAGS },
9103f4f4 436 {"i186", PROCESSOR_UNKNOWN,
40fb9820 437 CPU_I186_FLAGS },
9103f4f4 438 {"i286", PROCESSOR_UNKNOWN,
40fb9820 439 CPU_I286_FLAGS },
76bc74dc 440 {"i386", PROCESSOR_I386,
40fb9820 441 CPU_I386_FLAGS },
9103f4f4 442 {"i486", PROCESSOR_I486,
40fb9820 443 CPU_I486_FLAGS },
9103f4f4 444 {"i586", PROCESSOR_PENTIUM,
40fb9820 445 CPU_I586_FLAGS },
9103f4f4 446 {"i686", PROCESSOR_PENTIUMPRO,
40fb9820 447 CPU_I686_FLAGS },
9103f4f4 448 {"pentium", PROCESSOR_PENTIUM,
40fb9820 449 CPU_I586_FLAGS },
9103f4f4 450 {"pentiumpro",PROCESSOR_PENTIUMPRO,
40fb9820 451 CPU_I686_FLAGS },
9103f4f4 452 {"pentiumii", PROCESSOR_PENTIUMPRO,
40fb9820 453 CPU_P2_FLAGS },
9103f4f4 454 {"pentiumiii",PROCESSOR_PENTIUMPRO,
40fb9820 455 CPU_P3_FLAGS },
9103f4f4 456 {"pentium4", PROCESSOR_PENTIUM4,
40fb9820 457 CPU_P4_FLAGS },
9103f4f4 458 {"prescott", PROCESSOR_NOCONA,
40fb9820 459 CPU_CORE_FLAGS },
9103f4f4 460 {"nocona", PROCESSOR_NOCONA,
40fb9820 461 CPU_NOCONA_FLAGS },
ef05d495 462 {"yonah", PROCESSOR_CORE,
40fb9820 463 CPU_CORE_FLAGS },
ef05d495 464 {"core", PROCESSOR_CORE,
40fb9820 465 CPU_CORE_FLAGS },
ef05d495 466 {"merom", PROCESSOR_CORE2,
40fb9820 467 CPU_CORE2_FLAGS },
ef05d495 468 {"core2", PROCESSOR_CORE2,
40fb9820 469 CPU_CORE2_FLAGS },
9103f4f4 470 {"k6", PROCESSOR_K6,
40fb9820 471 CPU_K6_FLAGS },
9103f4f4 472 {"k6_2", PROCESSOR_K6,
40fb9820 473 CPU_K6_2_FLAGS },
9103f4f4 474 {"athlon", PROCESSOR_ATHLON,
40fb9820 475 CPU_ATHLON_FLAGS },
9103f4f4 476 {"sledgehammer", PROCESSOR_K8,
40fb9820 477 CPU_K8_FLAGS },
9103f4f4 478 {"opteron", PROCESSOR_K8,
40fb9820 479 CPU_K8_FLAGS },
9103f4f4 480 {"k8", PROCESSOR_K8,
40fb9820 481 CPU_K8_FLAGS },
050dfa73 482 {"amdfam10", PROCESSOR_AMDFAM10,
40fb9820 483 CPU_AMDFAM10_FLAGS },
9103f4f4 484 {".mmx", PROCESSOR_UNKNOWN,
40fb9820 485 CPU_MMX_FLAGS },
9103f4f4 486 {".sse", PROCESSOR_UNKNOWN,
40fb9820 487 CPU_SSE_FLAGS },
9103f4f4 488 {".sse2", PROCESSOR_UNKNOWN,
40fb9820 489 CPU_SSE2_FLAGS },
9103f4f4 490 {".sse3", PROCESSOR_UNKNOWN,
40fb9820 491 CPU_SSE3_FLAGS },
ef05d495 492 {".ssse3", PROCESSOR_UNKNOWN,
40fb9820 493 CPU_SSSE3_FLAGS },
42903f7f 494 {".sse4.1", PROCESSOR_UNKNOWN,
40fb9820 495 CPU_SSE4_1_FLAGS },
381d071f 496 {".sse4.2", PROCESSOR_UNKNOWN,
40fb9820 497 CPU_SSE4_2_FLAGS },
381d071f 498 {".sse4", PROCESSOR_UNKNOWN,
40fb9820 499 CPU_SSE4_2_FLAGS },
9103f4f4 500 {".3dnow", PROCESSOR_UNKNOWN,
40fb9820 501 CPU_3DNOW_FLAGS },
9103f4f4 502 {".3dnowa", PROCESSOR_UNKNOWN,
40fb9820 503 CPU_3DNOWA_FLAGS },
9103f4f4 504 {".padlock", PROCESSOR_UNKNOWN,
40fb9820 505 CPU_PADLOCK_FLAGS },
9103f4f4 506 {".pacifica", PROCESSOR_UNKNOWN,
40fb9820 507 CPU_SVME_FLAGS },
9103f4f4 508 {".svme", PROCESSOR_UNKNOWN,
40fb9820 509 CPU_SVME_FLAGS },
050dfa73 510 {".sse4a", PROCESSOR_UNKNOWN,
40fb9820 511 CPU_SSE4A_FLAGS },
050dfa73 512 {".abm", PROCESSOR_UNKNOWN,
40fb9820 513 CPU_ABM_FLAGS },
85f10a01
MM		 514 {".sse5", PROCESSOR_UNKNOWN,
515 CPU_SSE5_FLAGS },
e413e4e9
AM		 516};
517
29b0f896
AM		 518const pseudo_typeS md_pseudo_table[] =
519{
520#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
521 {"align", s_align_bytes, 0},
522#else
523 {"align", s_align_ptwo, 0},
524#endif
525 {"arch", set_cpu_arch, 0},
526#ifndef I386COFF
527 {"bss", s_bss, 0},
528#endif
529 {"ffloat", float_cons, 'f'},
530 {"dfloat", float_cons, 'd'},
531 {"tfloat", float_cons, 'x'},
532 {"value", cons, 2},
d182319b 533 {"slong", signed_cons, 4},
29b0f896
AM		 534 {"noopt", s_ignore, 0},
535 {"optim", s_ignore, 0},
536 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
537 {"code16", set_code_flag, CODE_16BIT},
538 {"code32", set_code_flag, CODE_32BIT},
539 {"code64", set_code_flag, CODE_64BIT},
540 {"intel_syntax", set_intel_syntax, 1},
541 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 542 {"intel_mnemonic", set_intel_mnemonic, 1},
543 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 544 {"allow_index_reg", set_allow_index_reg, 1},
545 {"disallow_index_reg", set_allow_index_reg, 0},
3b22753a
L		 546#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 {"largecomm", handle_large_common, 0},
07a53e5c 548#else
e3bb37b5 549 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 550 {"loc", dwarf2_directive_loc, 0},
551 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 552#endif
6482c264
NC		 553#ifdef TE_PE
554 {"secrel32", pe_directive_secrel, 0},
555#endif
29b0f896
AM		 556 {0, 0, 0}
557};
558
559/* For interface with expression (). */
560extern char *input_line_pointer;
561
562/* Hash table for instruction mnemonic lookup. */
563static struct hash_control *op_hash;
564
565/* Hash table for register lookup. */
566static struct hash_control *reg_hash;
567\f
252b5132 568void
e3bb37b5 569i386_align_code (fragS *fragP, int count)
252b5132 570{
ce8a8b2f
AM		 571 /* Various efficient no-op patterns for aligning code labels.
572 Note: Don't try to assemble the instructions in the comments.
573 0L and 0w are not legal. */
252b5132
RH		 574 static const char f32_1[] =
575 {0x90}; /* nop */
576 static const char f32_2[] =
ccc9c027 577 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 578 static const char f32_3[] =
579 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
580 static const char f32_4[] =
581 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
582 static const char f32_5[] =
583 {0x90, /* nop */
584 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
585 static const char f32_6[] =
586 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
587 static const char f32_7[] =
588 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
589 static const char f32_8[] =
590 {0x90, /* nop */
591 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
592 static const char f32_9[] =
593 {0x89,0xf6, /* movl %esi,%esi */
594 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
595 static const char f32_10[] =
596 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
597 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
598 static const char f32_11[] =
599 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
600 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
601 static const char f32_12[] =
602 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
603 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
604 static const char f32_13[] =
605 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
606 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
607 static const char f32_14[] =
608 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
609 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 610 static const char f16_3[] =
611 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 612 static const char f16_4[] =
613 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
614 static const char f16_5[] =
615 {0x90, /* nop */
616 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
617 static const char f16_6[] =
618 {0x89,0xf6, /* mov %si,%si */
619 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
620 static const char f16_7[] =
621 {0x8d,0x74,0x00, /* lea 0(%si),%si */
622 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
623 static const char f16_8[] =
624 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
625 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 626 static const char jump_31[] =
627 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
628 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
629 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
630 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 631 static const char *const f32_patt[] = {
632 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 633 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 634 };
635 static const char *const f16_patt[] = {
76bc74dc 636 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 637 };
ccc9c027
L		 638 /* nopl (%[re]ax) */
639 static const char alt_3[] =
640 {0x0f,0x1f,0x00};
641 /* nopl 0(%[re]ax) */
642 static const char alt_4[] =
643 {0x0f,0x1f,0x40,0x00};
644 /* nopl 0(%[re]ax,%[re]ax,1) */
645 static const char alt_5[] =
646 {0x0f,0x1f,0x44,0x00,0x00};
647 /* nopw 0(%[re]ax,%[re]ax,1) */
648 static const char alt_6[] =
649 {0x66,0x0f,0x1f,0x44,0x00,0x00};
650 /* nopl 0L(%[re]ax) */
651 static const char alt_7[] =
652 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
653 /* nopl 0L(%[re]ax,%[re]ax,1) */
654 static const char alt_8[] =
655 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
656 /* nopw 0L(%[re]ax,%[re]ax,1) */
657 static const char alt_9[] =
658 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
659 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
660 static const char alt_10[] =
661 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
662 /* data16
663 nopw %cs:0L(%[re]ax,%[re]ax,1) */
664 static const char alt_long_11[] =
665 {0x66,
666 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
667 /* data16
668 data16
669 nopw %cs:0L(%[re]ax,%[re]ax,1) */
670 static const char alt_long_12[] =
671 {0x66,
672 0x66,
673 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
674 /* data16
675 data16
676 data16
677 nopw %cs:0L(%[re]ax,%[re]ax,1) */
678 static const char alt_long_13[] =
679 {0x66,
680 0x66,
681 0x66,
682 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
683 /* data16
684 data16
685 data16
686 data16
687 nopw %cs:0L(%[re]ax,%[re]ax,1) */
688 static const char alt_long_14[] =
689 {0x66,
690 0x66,
691 0x66,
692 0x66,
693 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
694 /* data16
695 data16
696 data16
697 data16
698 data16
699 nopw %cs:0L(%[re]ax,%[re]ax,1) */
700 static const char alt_long_15[] =
701 {0x66,
702 0x66,
703 0x66,
704 0x66,
705 0x66,
706 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
707 /* nopl 0(%[re]ax,%[re]ax,1)
708 nopw 0(%[re]ax,%[re]ax,1) */
709 static const char alt_short_11[] =
710 {0x0f,0x1f,0x44,0x00,0x00,
711 0x66,0x0f,0x1f,0x44,0x00,0x00};
712 /* nopw 0(%[re]ax,%[re]ax,1)
713 nopw 0(%[re]ax,%[re]ax,1) */
714 static const char alt_short_12[] =
715 {0x66,0x0f,0x1f,0x44,0x00,0x00,
716 0x66,0x0f,0x1f,0x44,0x00,0x00};
717 /* nopw 0(%[re]ax,%[re]ax,1)
718 nopl 0L(%[re]ax) */
719 static const char alt_short_13[] =
720 {0x66,0x0f,0x1f,0x44,0x00,0x00,
721 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
722 /* nopl 0L(%[re]ax)
723 nopl 0L(%[re]ax) */
724 static const char alt_short_14[] =
725 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
726 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
727 /* nopl 0L(%[re]ax)
728 nopl 0L(%[re]ax,%[re]ax,1) */
729 static const char alt_short_15[] =
730 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
731 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
732 static const char *const alt_short_patt[] = {
733 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
734 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
735 alt_short_14, alt_short_15
736 };
737 static const char *const alt_long_patt[] = {
738 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
739 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
740 alt_long_14, alt_long_15
741 };
252b5132 742
76bc74dc
L		 743 /* Only align for at least a positive non-zero boundary. */
744 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 745 return;
3e73aa7c 746
ccc9c027
L		 747 /* We need to decide which NOP sequence to use for 32bit and
748 64bit. When -mtune= is used:
4eed87de 749
76bc74dc
L		 750 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
751 PROCESSOR_GENERIC32, f32_patt will be used.
752 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
753 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
754 alt_long_patt will be used.
755 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
756 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 757
76bc74dc
L		 758 When -mtune= isn't used, alt_long_patt will be used if
759 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
760 be used.
ccc9c027
L		 761
762 When -march= or .arch is used, we can't use anything beyond
763 cpu_arch_isa_flags. */
764
765 if (flag_code == CODE_16BIT)
766 {
ccc9c027 767 if (count > 8)
33fef721 768 {
76bc74dc
L		 769 memcpy (fragP->fr_literal + fragP->fr_fix,
770 jump_31, count);
771 /* Adjust jump offset. */
772 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 773 }
76bc74dc
L		 774 else
775 memcpy (fragP->fr_literal + fragP->fr_fix,
776 f16_patt[count - 1], count);
252b5132 777 }
33fef721 778 else
ccc9c027
L		 779 {
780 const char *const *patt = NULL;
781
782 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
783 {
784 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
785 switch (cpu_arch_tune)
786 {
787 case PROCESSOR_UNKNOWN:
788 /* We use cpu_arch_isa_flags to check if we SHOULD
789 optimize for Cpu686. */
40fb9820 790 if (cpu_arch_isa_flags.bitfield.cpui686)
76bc74dc 791 patt = alt_long_patt;
ccc9c027
L		 792 else
793 patt = f32_patt;
794 break;
ccc9c027
L		 795 case PROCESSOR_PENTIUMPRO:
796 case PROCESSOR_PENTIUM4:
797 case PROCESSOR_NOCONA:
ef05d495 798 case PROCESSOR_CORE:
76bc74dc
L		 799 case PROCESSOR_CORE2:
800 case PROCESSOR_GENERIC64:
801 patt = alt_long_patt;
802 break;
ccc9c027
L		 803 case PROCESSOR_K6:
804 case PROCESSOR_ATHLON:
805 case PROCESSOR_K8:
4eed87de 806 case PROCESSOR_AMDFAM10:
ccc9c027
L		 807 patt = alt_short_patt;
808 break;
76bc74dc 809 case PROCESSOR_I386:
ccc9c027
L		 810 case PROCESSOR_I486:
811 case PROCESSOR_PENTIUM:
812 case PROCESSOR_GENERIC32:
813 patt = f32_patt;
814 break;
4eed87de 815 }
ccc9c027
L		 816 }
817 else
818 {
819 switch (cpu_arch_tune)
820 {
821 case PROCESSOR_UNKNOWN:
822 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
823 PROCESSOR_UNKNOWN. */
824 abort ();
825 break;
826
76bc74dc 827 case PROCESSOR_I386:
ccc9c027
L		 828 case PROCESSOR_I486:
829 case PROCESSOR_PENTIUM:
ccc9c027
L		 830 case PROCESSOR_K6:
831 case PROCESSOR_ATHLON:
832 case PROCESSOR_K8:
4eed87de 833 case PROCESSOR_AMDFAM10:
ccc9c027
L		 834 case PROCESSOR_GENERIC32:
835 /* We use cpu_arch_isa_flags to check if we CAN optimize
836 for Cpu686. */
40fb9820 837 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 838 patt = alt_short_patt;
839 else
840 patt = f32_patt;
841 break;
76bc74dc
L		 842 case PROCESSOR_PENTIUMPRO:
843 case PROCESSOR_PENTIUM4:
844 case PROCESSOR_NOCONA:
845 case PROCESSOR_CORE:
ef05d495 846 case PROCESSOR_CORE2:
40fb9820 847 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 848 patt = alt_long_patt;
849 else
850 patt = f32_patt;
851 break;
852 case PROCESSOR_GENERIC64:
76bc74dc 853 patt = alt_long_patt;
ccc9c027 854 break;
4eed87de 855 }
ccc9c027
L		 856 }
857
76bc74dc
L		 858 if (patt == f32_patt)
859 {
860 /* If the padding is less than 15 bytes, we use the normal
861 ones. Otherwise, we use a jump instruction and adjust
862 its offset. */
863 if (count < 15)
864 memcpy (fragP->fr_literal + fragP->fr_fix,
865 patt[count - 1], count);
866 else
867 {
868 memcpy (fragP->fr_literal + fragP->fr_fix,
869 jump_31, count);
870 /* Adjust jump offset. */
871 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
872 }
873 }
874 else
875 {
876 /* Maximum length of an instruction is 15 byte. If the
877 padding is greater than 15 bytes and we don't use jump,
878 we have to break it into smaller pieces. */
879 int padding = count;
880 while (padding > 15)
881 {
882 padding -= 15;
883 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
884 patt [14], 15);
885 }
886
887 if (padding)
888 memcpy (fragP->fr_literal + fragP->fr_fix,
889 patt [padding - 1], padding);
890 }
ccc9c027 891 }
33fef721 892 fragP->fr_var = count;
252b5132
RH		 893}
894
c6fb90c8
L		 895static INLINE int
896uints_all_zero (const unsigned int *x, unsigned int size)
40fb9820 897{
c6fb90c8
L		 898 switch (size)
899 {
900 case 3:
901 if (x[2])
902 return 0;
903 case 2:
904 if (x[1])
905 return 0;
906 case 1:
907 return !x[0];
908 default:
909 abort ();
910 }
40fb9820
L		 911}
912
c6fb90c8
L		 913static INLINE void
914uints_set (unsigned int *x, unsigned int v, unsigned int size)
40fb9820 915{
c6fb90c8
L		 916 switch (size)
917 {
918 case 3:
919 x[2] = v;
920 case 2:
921 x[1] = v;
922 case 1:
923 x[0] = v;
924 break;
925 default:
926 abort ();
927 }
928}
40fb9820 929
c6fb90c8
L		 930static INLINE int
931uints_equal (const unsigned int *x, const unsigned int *y,
932 unsigned int size)
933{
934 switch (size)
935 {
936 case 3:
937 if (x[2] != y [2])
938 return 0;
939 case 2:
940 if (x[1] != y [1])
941 return 0;
942 case 1:
943 return x[0] == y [0];
944 break;
945 default:
946 abort ();
947 }
948}
40fb9820 949
c6fb90c8
L		 950#define UINTS_ALL_ZERO(x) \
951 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
952#define UINTS_SET(x, v) \
953 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
954#define UINTS_CLEAR(x) \
955 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
956#define UINTS_EQUAL(x, y) \
957 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
958
959static INLINE int
960cpu_flags_check_cpu64 (i386_cpu_flags f)
961{
962 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
963 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 964}
965
c6fb90c8
L		 966static INLINE i386_cpu_flags
967cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 968{
c6fb90c8
L		 969 switch (ARRAY_SIZE (x.array))
970 {
971 case 3:
972 x.array [2] &= y.array [2];
973 case 2:
974 x.array [1] &= y.array [1];
975 case 1:
976 x.array [0] &= y.array [0];
977 break;
978 default:
979 abort ();
980 }
981 return x;
982}
40fb9820 983
c6fb90c8
L		 984static INLINE i386_cpu_flags
985cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 986{
c6fb90c8 987 switch (ARRAY_SIZE (x.array))
40fb9820 988 {
c6fb90c8
L		 989 case 3:
990 x.array [2] |= y.array [2];
991 case 2:
992 x.array [1] |= y.array [1];
993 case 1:
994 x.array [0] |= y.array [0];
40fb9820
L		 995 break;
996 default:
997 abort ();
998 }
40fb9820
L		 999 return x;
1000}
1001
3629bb00
L		 1002/* Return 3 if there is a perfect match, 2 if compatible with 64bit,
1003 1 if compatible with arch, 0 if there is no match. */
1004
40fb9820
L		 1005static int
1006cpu_flags_match (i386_cpu_flags x)
1007{
3629bb00 1008 int overlap = cpu_flags_check_cpu64 (x) ? 2 : 0;
40fb9820
L		 1009
1010 x.bitfield.cpu64 = 0;
1011 x.bitfield.cpuno64 = 0;
1012
3629bb00
L		 1013 if (UINTS_ALL_ZERO (x))
1014 overlap |= 1;
1015 else
1016 {
1017 i386_cpu_flags cpu = cpu_arch_flags;
1018
1019 cpu.bitfield.cpu64 = 0;
1020 cpu.bitfield.cpuno64 = 0;
1021 cpu = cpu_flags_and (x, cpu);
1022 overlap |= UINTS_ALL_ZERO (cpu) ? 0 : 1;
1023 }
1024 return overlap;
40fb9820
L		 1025}
1026
c6fb90c8
L		 1027static INLINE i386_operand_type
1028operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1029{
c6fb90c8
L		 1030 switch (ARRAY_SIZE (x.array))
1031 {
1032 case 3:
1033 x.array [2] &= y.array [2];
1034 case 2:
1035 x.array [1] &= y.array [1];
1036 case 1:
1037 x.array [0] &= y.array [0];
1038 break;
1039 default:
1040 abort ();
1041 }
1042 return x;
40fb9820
L		 1043}
1044
c6fb90c8
L		 1045static INLINE i386_operand_type
1046operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1047{
c6fb90c8 1048 switch (ARRAY_SIZE (x.array))
40fb9820 1049 {
c6fb90c8
L		 1050 case 3:
1051 x.array [2] |= y.array [2];
1052 case 2:
1053 x.array [1] |= y.array [1];
1054 case 1:
1055 x.array [0] |= y.array [0];
40fb9820
L		 1056 break;
1057 default:
1058 abort ();
1059 }
c6fb90c8
L		 1060 return x;
1061}
40fb9820 1062
c6fb90c8
L		 1063static INLINE i386_operand_type
1064operand_type_xor (i386_operand_type x, i386_operand_type y)
1065{
1066 switch (ARRAY_SIZE (x.array))
1067 {
1068 case 3:
1069 x.array [2] ^= y.array [2];
1070 case 2:
1071 x.array [1] ^= y.array [1];
1072 case 1:
1073 x.array [0] ^= y.array [0];
1074 break;
1075 default:
1076 abort ();
1077 }
40fb9820
L		 1078 return x;
1079}
1080
1081static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1082static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1083static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1084static const i386_operand_type reg16_inoutportreg
1085 = OPERAND_TYPE_REG16_INOUTPORTREG;
1086static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1087static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1088static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1089static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1090static const i386_operand_type anydisp
1091 = OPERAND_TYPE_ANYDISP;
40fb9820
L		 1092static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1093static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1094static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1095static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1096static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1097static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1098static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1099static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1100static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1101static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1102
1103enum operand_type
1104{
1105 reg,
40fb9820
L		 1106 imm,
1107 disp,
1108 anymem
1109};
1110
c6fb90c8 1111static INLINE int
40fb9820
L		 1112operand_type_check (i386_operand_type t, enum operand_type c)
1113{
1114 switch (c)
1115 {
1116 case reg:
1117 return (t.bitfield.reg8
1118 || t.bitfield.reg16
1119 || t.bitfield.reg32
1120 || t.bitfield.reg64);
1121
40fb9820
L		 1122 case imm:
1123 return (t.bitfield.imm8
1124 || t.bitfield.imm8s
1125 || t.bitfield.imm16
1126 || t.bitfield.imm32
1127 || t.bitfield.imm32s
1128 || t.bitfield.imm64);
1129
1130 case disp:
1131 return (t.bitfield.disp8
1132 || t.bitfield.disp16
1133 || t.bitfield.disp32
1134 || t.bitfield.disp32s
1135 || t.bitfield.disp64);
1136
1137 case anymem:
1138 return (t.bitfield.disp8
1139 || t.bitfield.disp16
1140 || t.bitfield.disp32
1141 || t.bitfield.disp32s
1142 || t.bitfield.disp64
1143 || t.bitfield.baseindex);
1144
1145 default:
1146 abort ();
1147 }
1148}
1149
5c07affc
L		 1150/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1151 operand J for instruction template T. */
1152
1153static INLINE int
1154match_reg_size (const template *t, unsigned int j)
1155{
1156 return !((i.types[j].bitfield.byte
1157 && !t->operand_types[j].bitfield.byte)
1158 || (i.types[j].bitfield.word
1159 && !t->operand_types[j].bitfield.word)
1160 || (i.types[j].bitfield.dword
1161 && !t->operand_types[j].bitfield.dword)
1162 || (i.types[j].bitfield.qword
1163 && !t->operand_types[j].bitfield.qword));
1164}
1165
1166/* Return 1 if there is no conflict in any size on operand J for
1167 instruction template T. */
1168
1169static INLINE int
1170match_mem_size (const template *t, unsigned int j)
1171{
1172 return (match_reg_size (t, j)
1173 && !((i.types[j].bitfield.unspecified
1174 && !t->operand_types[j].bitfield.unspecified)
1175 || (i.types[j].bitfield.fword
1176 && !t->operand_types[j].bitfield.fword)
1177 || (i.types[j].bitfield.tbyte
1178 && !t->operand_types[j].bitfield.tbyte)
1179 || (i.types[j].bitfield.xmmword
1180 && !t->operand_types[j].bitfield.xmmword)));
1181}
1182
1183/* Return 1 if there is no size conflict on any operands for
1184 instruction template T. */
1185
1186static INLINE int
1187operand_size_match (const template *t)
1188{
1189 unsigned int j;
1190 int match = 1;
1191
1192 /* Don't check jump instructions. */
1193 if (t->opcode_modifier.jump
1194 || t->opcode_modifier.jumpbyte
1195 || t->opcode_modifier.jumpdword
1196 || t->opcode_modifier.jumpintersegment)
1197 return match;
1198
1199 /* Check memory and accumulator operand size. */
1200 for (j = 0; j < i.operands; j++)
1201 {
1202 if (t->operand_types[j].bitfield.anysize)
1203 continue;
1204
1205 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1206 {
1207 match = 0;
1208 break;
1209 }
1210
1211 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1212 {
1213 match = 0;
1214 break;
1215 }
1216 }
1217
1218 if (match
1219 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1220 return match;
1221
1222 /* Check reverse. */
1223 assert (i.operands == 2);
1224
1225 match = 1;
1226 for (j = 0; j < 2; j++)
1227 {
1228 if (t->operand_types[j].bitfield.acc
1229 && !match_reg_size (t, j ? 0 : 1))
1230 {
1231 match = 0;
1232 break;
1233 }
1234
1235 if (i.types[j].bitfield.mem
1236 && !match_mem_size (t, j ? 0 : 1))
1237 {
1238 match = 0;
1239 break;
1240 }
1241 }
1242
1243 return match;
1244}
1245
c6fb90c8 1246static INLINE int
40fb9820
L		 1247operand_type_match (i386_operand_type overlap,
1248 i386_operand_type given)
1249{
1250 i386_operand_type temp = overlap;
1251
1252 temp.bitfield.jumpabsolute = 0;
7d5e4556 1253 temp.bitfield.unspecified = 0;
5c07affc
L		 1254 temp.bitfield.byte = 0;
1255 temp.bitfield.word = 0;
1256 temp.bitfield.dword = 0;
1257 temp.bitfield.fword = 0;
1258 temp.bitfield.qword = 0;
1259 temp.bitfield.tbyte = 0;
1260 temp.bitfield.xmmword = 0;
c6fb90c8 1261 if (UINTS_ALL_ZERO (temp))
40fb9820
L		 1262 return 0;
1263
1264 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1265 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1266}
1267
7d5e4556 1268/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1269 unless the expected operand type register overlap is null.
1270 Note that Acc in a template matches every size of reg. */
1271
c6fb90c8 1272static INLINE int
40fb9820
L		 1273operand_type_register_match (i386_operand_type m0,
1274 i386_operand_type g0,
1275 i386_operand_type t0,
1276 i386_operand_type m1,
1277 i386_operand_type g1,
1278 i386_operand_type t1)
1279{
1280 if (!operand_type_check (g0, reg))
1281 return 1;
1282
1283 if (!operand_type_check (g1, reg))
1284 return 1;
1285
1286 if (g0.bitfield.reg8 == g1.bitfield.reg8
1287 && g0.bitfield.reg16 == g1.bitfield.reg16
1288 && g0.bitfield.reg32 == g1.bitfield.reg32
1289 && g0.bitfield.reg64 == g1.bitfield.reg64)
1290 return 1;
1291
1292 if (m0.bitfield.acc)
1293 {
1294 t0.bitfield.reg8 = 1;
1295 t0.bitfield.reg16 = 1;
1296 t0.bitfield.reg32 = 1;
1297 t0.bitfield.reg64 = 1;
1298 }
1299
1300 if (m1.bitfield.acc)
1301 {
1302 t1.bitfield.reg8 = 1;
1303 t1.bitfield.reg16 = 1;
1304 t1.bitfield.reg32 = 1;
1305 t1.bitfield.reg64 = 1;
1306 }
1307
1308 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1309 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1310 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1311 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1312}
1313
252b5132 1314static INLINE unsigned int
40fb9820 1315mode_from_disp_size (i386_operand_type t)
252b5132 1316{
40fb9820
L		 1317 if (t.bitfield.disp8)
1318 return 1;
1319 else if (t.bitfield.disp16
1320 || t.bitfield.disp32
1321 || t.bitfield.disp32s)
1322 return 2;
1323 else
1324 return 0;
252b5132
RH		 1325}
1326
1327static INLINE int
e3bb37b5 1328fits_in_signed_byte (offsetT num)
252b5132
RH		 1329{
1330 return (num >= -128) && (num <= 127);
47926f60 1331}
252b5132
RH		 1332
1333static INLINE int
e3bb37b5 1334fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1335{
1336 return (num & 0xff) == num;
47926f60 1337}
252b5132
RH		 1338
1339static INLINE int
e3bb37b5 1340fits_in_unsigned_word (offsetT num)
252b5132
RH		 1341{
1342 return (num & 0xffff) == num;
47926f60 1343}
252b5132
RH		 1344
1345static INLINE int
e3bb37b5 1346fits_in_signed_word (offsetT num)
252b5132
RH		 1347{
1348 return (-32768 <= num) && (num <= 32767);
47926f60 1349}
2a962e6d 1350
3e73aa7c 1351static INLINE int
e3bb37b5 1352fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1353{
1354#ifndef BFD64
1355 return 1;
1356#else
1357 return (!(((offsetT) -1 << 31) & num)
1358 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1359#endif
1360} /* fits_in_signed_long() */
2a962e6d 1361
3e73aa7c 1362static INLINE int
e3bb37b5 1363fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1364{
1365#ifndef BFD64
1366 return 1;
1367#else
1368 return (num & (((offsetT) 2 << 31) - 1)) == num;
1369#endif
1370} /* fits_in_unsigned_long() */
252b5132 1371
40fb9820 1372static i386_operand_type
e3bb37b5 1373smallest_imm_type (offsetT num)
252b5132 1374{
40fb9820
L		 1375 i386_operand_type t;
1376
c6fb90c8 1377 UINTS_CLEAR (t);
40fb9820
L		 1378 t.bitfield.imm64 = 1;
1379
1380 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1381 {
1382 /* This code is disabled on the 486 because all the Imm1 forms
1383 in the opcode table are slower on the i486. They're the
1384 versions with the implicitly specified single-position
1385 displacement, which has another syntax if you really want to
1386 use that form. */
40fb9820
L		 1387 t.bitfield.imm1 = 1;
1388 t.bitfield.imm8 = 1;
1389 t.bitfield.imm8s = 1;
1390 t.bitfield.imm16 = 1;
1391 t.bitfield.imm32 = 1;
1392 t.bitfield.imm32s = 1;
1393 }
1394 else if (fits_in_signed_byte (num))
1395 {
1396 t.bitfield.imm8 = 1;
1397 t.bitfield.imm8s = 1;
1398 t.bitfield.imm16 = 1;
1399 t.bitfield.imm32 = 1;
1400 t.bitfield.imm32s = 1;
1401 }
1402 else if (fits_in_unsigned_byte (num))
1403 {
1404 t.bitfield.imm8 = 1;
1405 t.bitfield.imm16 = 1;
1406 t.bitfield.imm32 = 1;
1407 t.bitfield.imm32s = 1;
1408 }
1409 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1410 {
1411 t.bitfield.imm16 = 1;
1412 t.bitfield.imm32 = 1;
1413 t.bitfield.imm32s = 1;
1414 }
1415 else if (fits_in_signed_long (num))
1416 {
1417 t.bitfield.imm32 = 1;
1418 t.bitfield.imm32s = 1;
1419 }
1420 else if (fits_in_unsigned_long (num))
1421 t.bitfield.imm32 = 1;
1422
1423 return t;
47926f60 1424}
252b5132 1425
847f7ad4 1426static offsetT
e3bb37b5 1427offset_in_range (offsetT val, int size)
847f7ad4 1428{
508866be 1429 addressT mask;
ba2adb93 1430
847f7ad4
AM		 1431 switch (size)
1432 {
508866be
L		 1433 case 1: mask = ((addressT) 1 << 8) - 1; break;
1434 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1435 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1436#ifdef BFD64
1437 case 8: mask = ((addressT) 2 << 63) - 1; break;
1438#endif
47926f60 1439 default: abort ();
847f7ad4
AM		 1440 }
1441
ba2adb93 1442 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1443 if (!use_rela_relocations)
1444 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1445 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1446
47926f60 1447 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1448 {
1449 char buf1[40], buf2[40];
1450
1451 sprint_value (buf1, val);
1452 sprint_value (buf2, val & mask);
1453 as_warn (_("%s shortened to %s"), buf1, buf2);
1454 }
1455 return val & mask;
1456}
1457
252b5132
RH		 1458/* Returns 0 if attempting to add a prefix where one from the same
1459 class already exists, 1 if non rep/repne added, 2 if rep/repne
1460 added. */
1461static int
e3bb37b5 1462add_prefix (unsigned int prefix)
252b5132
RH		 1463{
1464 int ret = 1;
b1905489 1465 unsigned int q;
252b5132 1466
29b0f896
AM		 1467 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1468 && flag_code == CODE_64BIT)
b1905489 1469 {
161a04f6
L		 1470 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1471 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1472 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1473 ret = 0;
1474 q = REX_PREFIX;
1475 }
3e73aa7c 1476 else
b1905489
JB		 1477 {
1478 switch (prefix)
1479 {
1480 default:
1481 abort ();
1482
1483 case CS_PREFIX_OPCODE:
1484 case DS_PREFIX_OPCODE:
1485 case ES_PREFIX_OPCODE:
1486 case FS_PREFIX_OPCODE:
1487 case GS_PREFIX_OPCODE:
1488 case SS_PREFIX_OPCODE:
1489 q = SEG_PREFIX;
1490 break;
1491
1492 case REPNE_PREFIX_OPCODE:
1493 case REPE_PREFIX_OPCODE:
1494 ret = 2;
1495 /* fall thru */
1496 case LOCK_PREFIX_OPCODE:
1497 q = LOCKREP_PREFIX;
1498 break;
1499
1500 case FWAIT_OPCODE:
1501 q = WAIT_PREFIX;
1502 break;
1503
1504 case ADDR_PREFIX_OPCODE:
1505 q = ADDR_PREFIX;
1506 break;
1507
1508 case DATA_PREFIX_OPCODE:
1509 q = DATA_PREFIX;
1510 break;
1511 }
1512 if (i.prefix[q] != 0)
1513 ret = 0;
1514 }
252b5132 1515
b1905489 1516 if (ret)
252b5132 1517 {
b1905489
JB		 1518 if (!i.prefix[q])
1519 ++i.prefixes;
1520 i.prefix[q] |= prefix;
252b5132 1521 }
b1905489
JB		 1522 else
1523 as_bad (_("same type of prefix used twice"));
252b5132 1524
252b5132
RH		 1525 return ret;
1526}
1527
1528static void
e3bb37b5 1529set_code_flag (int value)
eecb386c 1530{
3e73aa7c 1531 flag_code = value;
40fb9820
L		 1532 if (flag_code == CODE_64BIT)
1533 {
1534 cpu_arch_flags.bitfield.cpu64 = 1;
1535 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1536 }
1537 else
1538 {
1539 cpu_arch_flags.bitfield.cpu64 = 0;
1540 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1541 }
1542 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1543 {
1544 as_bad (_("64bit mode not supported on this CPU."));
1545 }
40fb9820 1546 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1547 {
1548 as_bad (_("32bit mode not supported on this CPU."));
1549 }
eecb386c
AM		 1550 stackop_size = '\0';
1551}
1552
1553static void
e3bb37b5 1554set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1555{
3e73aa7c 1556 flag_code = new_code_flag;
40fb9820
L		 1557 if (flag_code != CODE_16BIT)
1558 abort ();
1559 cpu_arch_flags.bitfield.cpu64 = 0;
1560 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1561 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1562}
1563
1564static void
e3bb37b5 1565set_intel_syntax (int syntax_flag)
252b5132
RH		 1566{
1567 /* Find out if register prefixing is specified. */
1568 int ask_naked_reg = 0;
1569
1570 SKIP_WHITESPACE ();
29b0f896 1571 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1572 {
1573 char *string = input_line_pointer;
1574 int e = get_symbol_end ();
1575
47926f60 1576 if (strcmp (string, "prefix") == 0)
252b5132 1577 ask_naked_reg = 1;
47926f60 1578 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1579 ask_naked_reg = -1;
1580 else
d0b47220 1581 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1582 *input_line_pointer = e;
1583 }
1584 demand_empty_rest_of_line ();
c3332e24 1585
252b5132
RH		 1586 intel_syntax = syntax_flag;
1587
1588 if (ask_naked_reg == 0)
f86103b7
AM		 1589 allow_naked_reg = (intel_syntax
1590 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1591 else
1592 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1593
e4a3b5a4 1594 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1595 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1596 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1597}
1598
1efbbeb4
L		 1599static void
1600set_intel_mnemonic (int mnemonic_flag)
1601{
e1d4d893 1602 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1603}
1604
db51cc60
L		 1605static void
1606set_allow_index_reg (int flag)
1607{
1608 allow_index_reg = flag;
1609}
1610
e413e4e9 1611static void
e3bb37b5 1612set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1613{
47926f60 1614 SKIP_WHITESPACE ();
e413e4e9 1615
29b0f896 1616 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1617 {
1618 char *string = input_line_pointer;
1619 int e = get_symbol_end ();
9103f4f4 1620 unsigned int i;
40fb9820 1621 i386_cpu_flags flags;
e413e4e9 1622
9103f4f4 1623 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1624 {
1625 if (strcmp (string, cpu_arch[i].name) == 0)
1626 {
5c6af06e
JB		 1627 if (*string != '.')
1628 {
1629 cpu_arch_name = cpu_arch[i].name;
1630 cpu_sub_arch_name = NULL;
40fb9820
L		 1631 cpu_arch_flags = cpu_arch[i].flags;
1632 if (flag_code == CODE_64BIT)
1633 {
1634 cpu_arch_flags.bitfield.cpu64 = 1;
1635 cpu_arch_flags.bitfield.cpuno64 = 0;
1636 }
1637 else
1638 {
1639 cpu_arch_flags.bitfield.cpu64 = 0;
1640 cpu_arch_flags.bitfield.cpuno64 = 1;
1641 }
ccc9c027 1642 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1643 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1644 if (!cpu_arch_tune_set)
1645 {
1646 cpu_arch_tune = cpu_arch_isa;
1647 cpu_arch_tune_flags = cpu_arch_isa_flags;
1648 }
5c6af06e
JB		 1649 break;
1650 }
40fb9820 1651
c6fb90c8
L		 1652 flags = cpu_flags_or (cpu_arch_flags,
1653 cpu_arch[i].flags);
1654 if (!UINTS_EQUAL (flags, cpu_arch_flags))
5c6af06e
JB		 1655 {
1656 cpu_sub_arch_name = cpu_arch[i].name;
40fb9820 1657 cpu_arch_flags = flags;
5c6af06e
JB		 1658 }
1659 *input_line_pointer = e;
1660 demand_empty_rest_of_line ();
1661 return;
e413e4e9
AM		 1662 }
1663 }
9103f4f4 1664 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1665 as_bad (_("no such architecture: `%s'"), string);
1666
1667 *input_line_pointer = e;
1668 }
1669 else
1670 as_bad (_("missing cpu architecture"));
1671
fddf5b5b
AM		 1672 no_cond_jump_promotion = 0;
1673 if (*input_line_pointer == ','
29b0f896 1674 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1675 {
1676 char *string = ++input_line_pointer;
1677 int e = get_symbol_end ();
1678
1679 if (strcmp (string, "nojumps") == 0)
1680 no_cond_jump_promotion = 1;
1681 else if (strcmp (string, "jumps") == 0)
1682 ;
1683 else
1684 as_bad (_("no such architecture modifier: `%s'"), string);
1685
1686 *input_line_pointer = e;
1687 }
1688
e413e4e9
AM		 1689 demand_empty_rest_of_line ();
1690}
1691
b9d79e03
JH		 1692unsigned long
1693i386_mach ()
1694{
1695 if (!strcmp (default_arch, "x86_64"))
1696 return bfd_mach_x86_64;
1697 else if (!strcmp (default_arch, "i386"))
1698 return bfd_mach_i386_i386;
1699 else
1700 as_fatal (_("Unknown architecture"));
1701}
b9d79e03 1702\f
252b5132
RH		 1703void
1704md_begin ()
1705{
1706 const char *hash_err;
1707
47926f60 1708 /* Initialize op_hash hash table. */
252b5132
RH		 1709 op_hash = hash_new ();
1710
1711 {
29b0f896
AM		 1712 const template *optab;
1713 templates *core_optab;
252b5132 1714
47926f60
KH		 1715 /* Setup for loop. */
1716 optab = i386_optab;
252b5132
RH		 1717 core_optab = (templates *) xmalloc (sizeof (templates));
1718 core_optab->start = optab;
1719
1720 while (1)
1721 {
1722 ++optab;
1723 if (optab->name == NULL
1724 || strcmp (optab->name, (optab - 1)->name) != 0)
1725 {
1726 /* different name --> ship out current template list;
47926f60 1727 add to hash table; & begin anew. */
252b5132
RH		 1728 core_optab->end = optab;
1729 hash_err = hash_insert (op_hash,
1730 (optab - 1)->name,
1731 (PTR) core_optab);
1732 if (hash_err)
1733 {
252b5132
RH		 1734 as_fatal (_("Internal Error: Can't hash %s: %s"),
1735 (optab - 1)->name,
1736 hash_err);
1737 }
1738 if (optab->name == NULL)
1739 break;
1740 core_optab = (templates *) xmalloc (sizeof (templates));
1741 core_optab->start = optab;
1742 }
1743 }
1744 }
1745
47926f60 1746 /* Initialize reg_hash hash table. */
252b5132
RH		 1747 reg_hash = hash_new ();
1748 {
29b0f896 1749 const reg_entry *regtab;
c3fe08fa 1750 unsigned int regtab_size = i386_regtab_size;
252b5132 1751
c3fe08fa 1752 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1753 {
1754 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1755 if (hash_err)
3e73aa7c
JH		 1756 as_fatal (_("Internal Error: Can't hash %s: %s"),
1757 regtab->reg_name,
1758 hash_err);
252b5132
RH		 1759 }
1760 }
1761
47926f60 1762 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1763 {
29b0f896
AM		 1764 int c;
1765 char *p;
252b5132
RH		 1766
1767 for (c = 0; c < 256; c++)
1768 {
3882b010 1769 if (ISDIGIT (c))
252b5132
RH		 1770 {
1771 digit_chars[c] = c;
1772 mnemonic_chars[c] = c;
1773 register_chars[c] = c;
1774 operand_chars[c] = c;
1775 }
3882b010 1776 else if (ISLOWER (c))
252b5132
RH		 1777 {
1778 mnemonic_chars[c] = c;
1779 register_chars[c] = c;
1780 operand_chars[c] = c;
1781 }
3882b010 1782 else if (ISUPPER (c))
252b5132 1783 {
3882b010 1784 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1785 register_chars[c] = mnemonic_chars[c];
1786 operand_chars[c] = c;
1787 }
1788
3882b010 1789 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1790 identifier_chars[c] = c;
1791 else if (c >= 128)
1792 {
1793 identifier_chars[c] = c;
1794 operand_chars[c] = c;
1795 }
1796 }
1797
1798#ifdef LEX_AT
1799 identifier_chars['@'] = '@';
32137342
NC		 1800#endif
1801#ifdef LEX_QM
1802 identifier_chars['?'] = '?';
1803 operand_chars['?'] = '?';
252b5132 1804#endif
252b5132 1805 digit_chars['-'] = '-';
791fe849 1806 mnemonic_chars['-'] = '-';
0003779b 1807 mnemonic_chars['.'] = '.';
252b5132
RH		 1808 identifier_chars['_'] = '_';
1809 identifier_chars['.'] = '.';
1810
1811 for (p = operand_special_chars; *p != '\0'; p++)
1812 operand_chars[(unsigned char) *p] = *p;
1813 }
1814
1815#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1816 if (IS_ELF)
252b5132
RH		 1817 {
1818 record_alignment (text_section, 2);
1819 record_alignment (data_section, 2);
1820 record_alignment (bss_section, 2);
1821 }
1822#endif
a4447b93
RH		 1823
1824 if (flag_code == CODE_64BIT)
1825 {
1826 x86_dwarf2_return_column = 16;
1827 x86_cie_data_alignment = -8;
1828 }
1829 else
1830 {
1831 x86_dwarf2_return_column = 8;
1832 x86_cie_data_alignment = -4;
1833 }
252b5132
RH		 1834}
1835
1836void
e3bb37b5 1837i386_print_statistics (FILE *file)
252b5132
RH		 1838{
1839 hash_print_statistics (file, "i386 opcode", op_hash);
1840 hash_print_statistics (file, "i386 register", reg_hash);
1841}
1842\f
252b5132
RH		 1843#ifdef DEBUG386
1844
ce8a8b2f 1845/* Debugging routines for md_assemble. */
e3bb37b5 1846static void pte (template *);
40fb9820 1847static void pt (i386_operand_type);
e3bb37b5
L		 1848static void pe (expressionS *);
1849static void ps (symbolS *);
252b5132
RH		 1850
1851static void
e3bb37b5 1852pi (char *line, i386_insn *x)
252b5132 1853{
09f131f2 1854 unsigned int i;
252b5132
RH		 1855
1856 fprintf (stdout, "%s: template ", line);
1857 pte (&x->tm);
09f131f2
JH		 1858 fprintf (stdout, " address: base %s index %s scale %x\n",
1859 x->base_reg ? x->base_reg->reg_name : "none",
1860 x->index_reg ? x->index_reg->reg_name : "none",
1861 x->log2_scale_factor);
1862 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1863 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1864 fprintf (stdout, " sib: base %x index %x scale %x\n",
1865 x->sib.base, x->sib.index, x->sib.scale);
1866 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 1867 (x->rex & REX_W) != 0,
1868 (x->rex & REX_R) != 0,
1869 (x->rex & REX_X) != 0,
1870 (x->rex & REX_B) != 0);
85f10a01
MM		 1871 fprintf (stdout, " drex: reg %d rex 0x%x\n",
1872 x->drex.reg, x->drex.rex);
252b5132
RH		 1873 for (i = 0; i < x->operands; i++)
1874 {
1875 fprintf (stdout, " #%d: ", i + 1);
1876 pt (x->types[i]);
1877 fprintf (stdout, "\n");
40fb9820
L		 1878 if (x->types[i].bitfield.reg8
1879 || x->types[i].bitfield.reg16
1880 || x->types[i].bitfield.reg32
1881 || x->types[i].bitfield.reg64
1882 || x->types[i].bitfield.regmmx
1883 || x->types[i].bitfield.regxmm
1884 || x->types[i].bitfield.sreg2
1885 || x->types[i].bitfield.sreg3
1886 || x->types[i].bitfield.control
1887 || x->types[i].bitfield.debug
1888 || x->types[i].bitfield.test)
520dc8e8 1889 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 1890 if (operand_type_check (x->types[i], imm))
520dc8e8 1891 pe (x->op[i].imms);
40fb9820 1892 if (operand_type_check (x->types[i], disp))
520dc8e8 1893 pe (x->op[i].disps);
252b5132
RH		 1894 }
1895}
1896
1897static void
e3bb37b5 1898pte (template *t)
252b5132 1899{
09f131f2 1900 unsigned int i;
252b5132 1901 fprintf (stdout, " %d operands ", t->operands);
47926f60 1902 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1903 if (t->extension_opcode != None)
1904 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 1905 if (t->opcode_modifier.d)
252b5132 1906 fprintf (stdout, "D");
40fb9820 1907 if (t->opcode_modifier.w)
252b5132
RH		 1908 fprintf (stdout, "W");
1909 fprintf (stdout, "\n");
1910 for (i = 0; i < t->operands; i++)
1911 {
1912 fprintf (stdout, " #%d type ", i + 1);
1913 pt (t->operand_types[i]);
1914 fprintf (stdout, "\n");
1915 }
1916}
1917
1918static void
e3bb37b5 1919pe (expressionS *e)
252b5132 1920{
24eab124 1921 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1922 fprintf (stdout, " add_number %ld (%lx)\n",
1923 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1924 if (e->X_add_symbol)
1925 {
1926 fprintf (stdout, " add_symbol ");
1927 ps (e->X_add_symbol);
1928 fprintf (stdout, "\n");
1929 }
1930 if (e->X_op_symbol)
1931 {
1932 fprintf (stdout, " op_symbol ");
1933 ps (e->X_op_symbol);
1934 fprintf (stdout, "\n");
1935 }
1936}
1937
1938static void
e3bb37b5 1939ps (symbolS *s)
252b5132
RH		 1940{
1941 fprintf (stdout, "%s type %s%s",
1942 S_GET_NAME (s),
1943 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1944 segment_name (S_GET_SEGMENT (s)));
1945}
1946
7b81dfbb 1947static struct type_name
252b5132 1948 {
40fb9820
L		 1949 i386_operand_type mask;
1950 const char *name;
252b5132 1951 }
7b81dfbb 1952const type_names[] =
252b5132 1953{
40fb9820
L		 1954 { OPERAND_TYPE_REG8, "r8" },
1955 { OPERAND_TYPE_REG16, "r16" },
1956 { OPERAND_TYPE_REG32, "r32" },
1957 { OPERAND_TYPE_REG64, "r64" },
1958 { OPERAND_TYPE_IMM8, "i8" },
1959 { OPERAND_TYPE_IMM8, "i8s" },
1960 { OPERAND_TYPE_IMM16, "i16" },
1961 { OPERAND_TYPE_IMM32, "i32" },
1962 { OPERAND_TYPE_IMM32S, "i32s" },
1963 { OPERAND_TYPE_IMM64, "i64" },
1964 { OPERAND_TYPE_IMM1, "i1" },
1965 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
1966 { OPERAND_TYPE_DISP8, "d8" },
1967 { OPERAND_TYPE_DISP16, "d16" },
1968 { OPERAND_TYPE_DISP32, "d32" },
1969 { OPERAND_TYPE_DISP32S, "d32s" },
1970 { OPERAND_TYPE_DISP64, "d64" },
1971 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
1972 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
1973 { OPERAND_TYPE_CONTROL, "control reg" },
1974 { OPERAND_TYPE_TEST, "test reg" },
1975 { OPERAND_TYPE_DEBUG, "debug reg" },
1976 { OPERAND_TYPE_FLOATREG, "FReg" },
1977 { OPERAND_TYPE_FLOATACC, "FAcc" },
1978 { OPERAND_TYPE_SREG2, "SReg2" },
1979 { OPERAND_TYPE_SREG3, "SReg3" },
1980 { OPERAND_TYPE_ACC, "Acc" },
1981 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
1982 { OPERAND_TYPE_REGMMX, "rMMX" },
1983 { OPERAND_TYPE_REGXMM, "rXMM" },
1984 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 1985};
1986
1987static void
40fb9820 1988pt (i386_operand_type t)
252b5132 1989{
40fb9820 1990 unsigned int j;
c6fb90c8 1991 i386_operand_type a;
252b5132 1992
40fb9820 1993 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 1994 {
1995 a = operand_type_and (t, type_names[j].mask);
1996 if (!UINTS_ALL_ZERO (a))
1997 fprintf (stdout, "%s, ", type_names[j].name);
1998 }
252b5132
RH		 1999 fflush (stdout);
2000}
2001
2002#endif /* DEBUG386 */
2003\f
252b5132 2004static bfd_reloc_code_real_type
3956db08 2005reloc (unsigned int size,
64e74474
AM		 2006 int pcrel,
2007 int sign,
2008 bfd_reloc_code_real_type other)
252b5132 2009{
47926f60 2010 if (other != NO_RELOC)
3956db08
JB		 2011 {
2012 reloc_howto_type *reloc;
2013
2014 if (size == 8)
2015 switch (other)
2016 {
64e74474
AM		 2017 case BFD_RELOC_X86_64_GOT32:
2018 return BFD_RELOC_X86_64_GOT64;
2019 break;
2020 case BFD_RELOC_X86_64_PLTOFF64:
2021 return BFD_RELOC_X86_64_PLTOFF64;
2022 break;
2023 case BFD_RELOC_X86_64_GOTPC32:
2024 other = BFD_RELOC_X86_64_GOTPC64;
2025 break;
2026 case BFD_RELOC_X86_64_GOTPCREL:
2027 other = BFD_RELOC_X86_64_GOTPCREL64;
2028 break;
2029 case BFD_RELOC_X86_64_TPOFF32:
2030 other = BFD_RELOC_X86_64_TPOFF64;
2031 break;
2032 case BFD_RELOC_X86_64_DTPOFF32:
2033 other = BFD_RELOC_X86_64_DTPOFF64;
2034 break;
2035 default:
2036 break;
3956db08 2037 }
e05278af
JB		 2038
2039 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2040 if (size == 4 && flag_code != CODE_64BIT)
2041 sign = -1;
2042
3956db08
JB		 2043 reloc = bfd_reloc_type_lookup (stdoutput, other);
2044 if (!reloc)
2045 as_bad (_("unknown relocation (%u)"), other);
2046 else if (size != bfd_get_reloc_size (reloc))
2047 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2048 bfd_get_reloc_size (reloc),
2049 size);
2050 else if (pcrel && !reloc->pc_relative)
2051 as_bad (_("non-pc-relative relocation for pc-relative field"));
2052 else if ((reloc->complain_on_overflow == complain_overflow_signed
2053 && !sign)
2054 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2055 && sign > 0))
3956db08
JB		 2056 as_bad (_("relocated field and relocation type differ in signedness"));
2057 else
2058 return other;
2059 return NO_RELOC;
2060 }
252b5132
RH		 2061
2062 if (pcrel)
2063 {
3e73aa7c 2064 if (!sign)
3956db08 2065 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2066 switch (size)
2067 {
2068 case 1: return BFD_RELOC_8_PCREL;
2069 case 2: return BFD_RELOC_16_PCREL;
2070 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2071 case 8: return BFD_RELOC_64_PCREL;
252b5132 2072 }
3956db08 2073 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2074 }
2075 else
2076 {
3956db08 2077 if (sign > 0)
e5cb08ac 2078 switch (size)
3e73aa7c
JH		 2079 {
2080 case 4: return BFD_RELOC_X86_64_32S;
2081 }
2082 else
2083 switch (size)
2084 {
2085 case 1: return BFD_RELOC_8;
2086 case 2: return BFD_RELOC_16;
2087 case 4: return BFD_RELOC_32;
2088 case 8: return BFD_RELOC_64;
2089 }
3956db08
JB		 2090 as_bad (_("cannot do %s %u byte relocation"),
2091 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2092 }
2093
bfb32b52 2094 abort ();
252b5132
RH		 2095 return BFD_RELOC_NONE;
2096}
2097
47926f60
KH		 2098/* Here we decide which fixups can be adjusted to make them relative to
2099 the beginning of the section instead of the symbol. Basically we need
2100 to make sure that the dynamic relocations are done correctly, so in
2101 some cases we force the original symbol to be used. */
2102
252b5132 2103int
e3bb37b5 2104tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2105{
6d249963 2106#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2107 if (!IS_ELF)
31312f95
AM		 2108 return 1;
2109
a161fe53
AM		 2110 /* Don't adjust pc-relative references to merge sections in 64-bit
2111 mode. */
2112 if (use_rela_relocations
2113 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2114 && fixP->fx_pcrel)
252b5132 2115 return 0;
31312f95 2116
8d01d9a9
AJ		 2117 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2118 and changed later by validate_fix. */
2119 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2120 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2121 return 0;
2122
ce8a8b2f 2123 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2124 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2125 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2126 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2127 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2128 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2129 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2130 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2131 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2132 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2133 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2134 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2135 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2136 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2137 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2138 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2139 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2140 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2141 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2142 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2143 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2144 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2145 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2146 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2147 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2148 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2149 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2150 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2151 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2152 return 0;
31312f95 2153#endif
252b5132
RH		 2154 return 1;
2155}
252b5132 2156
b4cac588 2157static int
e3bb37b5 2158intel_float_operand (const char *mnemonic)
252b5132 2159{
9306ca4a
JB		 2160 /* Note that the value returned is meaningful only for opcodes with (memory)
2161 operands, hence the code here is free to improperly handle opcodes that
2162 have no operands (for better performance and smaller code). */
2163
2164 if (mnemonic[0] != 'f')
2165 return 0; /* non-math */
2166
2167 switch (mnemonic[1])
2168 {
2169 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2170 the fs segment override prefix not currently handled because no
2171 call path can make opcodes without operands get here */
2172 case 'i':
2173 return 2 /* integer op */;
2174 case 'l':
2175 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2176 return 3; /* fldcw/fldenv */
2177 break;
2178 case 'n':
2179 if (mnemonic[2] != 'o' /* fnop */)
2180 return 3; /* non-waiting control op */
2181 break;
2182 case 'r':
2183 if (mnemonic[2] == 's')
2184 return 3; /* frstor/frstpm */
2185 break;
2186 case 's':
2187 if (mnemonic[2] == 'a')
2188 return 3; /* fsave */
2189 if (mnemonic[2] == 't')
2190 {
2191 switch (mnemonic[3])
2192 {
2193 case 'c': /* fstcw */
2194 case 'd': /* fstdw */
2195 case 'e': /* fstenv */
2196 case 's': /* fsts[gw] */
2197 return 3;
2198 }
2199 }
2200 break;
2201 case 'x':
2202 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2203 return 0; /* fxsave/fxrstor are not really math ops */
2204 break;
2205 }
252b5132 2206
9306ca4a 2207 return 1;
252b5132
RH		 2208}
2209
2210/* This is the guts of the machine-dependent assembler. LINE points to a
2211 machine dependent instruction. This function is supposed to emit
2212 the frags/bytes it assembles to. */
2213
2214void
2215md_assemble (line)
2216 char *line;
2217{
40fb9820 2218 unsigned int j;
252b5132
RH		 2219 char mnemonic[MAX_MNEM_SIZE];
2220
47926f60 2221 /* Initialize globals. */
252b5132
RH		 2222 memset (&i, '\0', sizeof (i));
2223 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2224 i.reloc[j] = NO_RELOC;
252b5132
RH		 2225 memset (disp_expressions, '\0', sizeof (disp_expressions));
2226 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2227 save_stack_p = save_stack;
252b5132
RH		 2228
2229 /* First parse an instruction mnemonic & call i386_operand for the operands.
2230 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2231 start of a (possibly prefixed) mnemonic. */
252b5132 2232
29b0f896
AM		 2233 line = parse_insn (line, mnemonic);
2234 if (line == NULL)
2235 return;
252b5132 2236
29b0f896
AM		 2237 line = parse_operands (line, mnemonic);
2238 if (line == NULL)
2239 return;
252b5132 2240
29b0f896
AM		 2241 /* Now we've parsed the mnemonic into a set of templates, and have the
2242 operands at hand. */
2243
2244 /* All intel opcodes have reversed operands except for "bound" and
2245 "enter". We also don't reverse intersegment "jmp" and "call"
2246 instructions with 2 immediate operands so that the immediate segment
050dfa73 2247 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2248 if (intel_syntax
2249 && i.operands > 1
29b0f896 2250 && (strcmp (mnemonic, "bound") != 0)
30123838 2251 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2252 && !(operand_type_check (i.types[0], imm)
2253 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2254 swap_operands ();
2255
ec56d5c0
JB		 2256 /* The order of the immediates should be reversed
2257 for 2 immediates extrq and insertq instructions */
2258 if (i.imm_operands == 2
2259 && (strcmp (mnemonic, "extrq") == 0
2260 || strcmp (mnemonic, "insertq") == 0))
2261 swap_2_operands (0, 1);
2262
29b0f896
AM		 2263 if (i.imm_operands)
2264 optimize_imm ();
2265
b300c311
L		 2266 /* Don't optimize displacement for movabs since it only takes 64bit
2267 displacement. */
2268 if (i.disp_operands
2269 && (flag_code != CODE_64BIT
2270 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2271 optimize_disp ();
2272
2273 /* Next, we find a template that matches the given insn,
2274 making sure the overlap of the given operands types is consistent
2275 with the template operand types. */
252b5132 2276
29b0f896
AM		 2277 if (!match_template ())
2278 return;
252b5132 2279
cd61ebfe
AM		 2280 if (intel_syntax)
2281 {
cd61ebfe
AM		 2282 /* Zap movzx and movsx suffix. The suffix may have been set from
2283 "word ptr" or "byte ptr" on the source operand, but we'll use
2284 the suffix later to choose the destination register. */
2285 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 2286 {
2287 if (i.reg_operands < 2
2288 && !i.suffix
40fb9820
L		 2289 && (!i.tm.opcode_modifier.no_bsuf
2290 || !i.tm.opcode_modifier.no_wsuf
2291 || !i.tm.opcode_modifier.no_lsuf
2292 || !i.tm.opcode_modifier.no_ssuf
7ce189b3 2293 || !i.tm.opcode_modifier.no_ldsuf
40fb9820 2294 || !i.tm.opcode_modifier.no_qsuf))
9306ca4a
JB		 2295 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2296
2297 i.suffix = 0;
2298 }
cd61ebfe 2299 }
24eab124 2300
40fb9820 2301 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2302 if (!add_prefix (FWAIT_OPCODE))
2303 return;
252b5132 2304
29b0f896 2305 /* Check string instruction segment overrides. */
40fb9820 2306 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2307 {
2308 if (!check_string ())
5dd0794d 2309 return;
29b0f896 2310 }
5dd0794d 2311
29b0f896
AM		 2312 if (!process_suffix ())
2313 return;
e413e4e9 2314
29b0f896
AM		 2315 /* Make still unresolved immediate matches conform to size of immediate
2316 given in i.suffix. */
2317 if (!finalize_imm ())
2318 return;
252b5132 2319
40fb9820 2320 if (i.types[0].bitfield.imm1)
29b0f896 2321 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2322
40fb9820 2323 for (j = 0; j < 3; j++)
c6fb90c8
L		 2324 if (i.types[j].bitfield.inoutportreg
2325 || i.types[j].bitfield.shiftcount
2326 || i.types[j].bitfield.acc
2327 || i.types[j].bitfield.floatacc)
40fb9820
L		 2328 i.reg_operands--;
2329
2330 if (i.tm.opcode_modifier.immext)
29b0f896 2331 {
02fc3089
L		 2332 expressionS *exp;
2333
40fb9820 2334 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
ca164297 2335 {
b7d9ef37 2336 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 2337 operands with an opcode suffix which is coded in the same
2338 place as an 8-bit immediate field would be. Here we check
2339 those operands and remove them afterwards. */
2340 unsigned int x;
2341
a4622f40 2342 for (x = 0; x < i.operands; x++)
ca164297 2343 if (i.op[x].regs->reg_num != x)
a540244d
L		 2344 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2345 register_prefix,
2346 i.op[x].regs->reg_name,
2347 x + 1,
2348 i.tm.name);
ca164297
L		 2349 i.operands = 0;
2350 }
2351
29b0f896
AM		 2352 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2353 opcode suffix which is coded in the same place as an 8-bit
2354 immediate field would be. Here we fake an 8-bit immediate
85f10a01
MM		 2355 operand from the opcode suffix stored in tm.extension_opcode.
2356 SSE5 also uses this encoding, for some of its 3 argument
2357 instructions. */
252b5132 2358
85f10a01
MM		 2359 assert (i.imm_operands == 0
2360 && (i.operands <= 2
2361 || (i.tm.cpu_flags.bitfield.cpusse5
2362 && i.operands <= 3)));
252b5132 2363
29b0f896
AM		 2364 exp = &im_expressions[i.imm_operands++];
2365 i.op[i.operands].imms = exp;
c6fb90c8 2366 UINTS_CLEAR (i.types[i.operands]);
40fb9820
L		 2367 i.types[i.operands].bitfield.imm8 = 1;
2368 i.operands++;
29b0f896
AM		 2369 exp->X_op = O_constant;
2370 exp->X_add_number = i.tm.extension_opcode;
2371 i.tm.extension_opcode = None;
2372 }
252b5132 2373
29b0f896
AM		 2374 /* For insns with operands there are more diddles to do to the opcode. */
2375 if (i.operands)
2376 {
2377 if (!process_operands ())
2378 return;
2379 }
40fb9820 2380 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2381 {
2382 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2383 as_warn (_("translating to `%sp'"), i.tm.name);
2384 }
252b5132 2385
29b0f896
AM		 2386 /* Handle conversion of 'int $3' --> special int3 insn. */
2387 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2388 {
2389 i.tm.base_opcode = INT3_OPCODE;
2390 i.imm_operands = 0;
2391 }
252b5132 2392
40fb9820
L		 2393 if ((i.tm.opcode_modifier.jump
2394 || i.tm.opcode_modifier.jumpbyte
2395 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2396 && i.op[0].disps->X_op == O_constant)
2397 {
2398 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2399 the absolute address given by the constant. Since ix86 jumps and
2400 calls are pc relative, we need to generate a reloc. */
2401 i.op[0].disps->X_add_symbol = &abs_symbol;
2402 i.op[0].disps->X_op = O_symbol;
2403 }
252b5132 2404
40fb9820 2405 if (i.tm.opcode_modifier.rex64)
161a04f6 2406 i.rex |= REX_W;
252b5132 2407
29b0f896
AM		 2408 /* For 8 bit registers we need an empty rex prefix. Also if the
2409 instruction already has a prefix, we need to convert old
2410 registers to new ones. */
773f551c 2411
40fb9820 2412 if ((i.types[0].bitfield.reg8
29b0f896 2413 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2414 || (i.types[1].bitfield.reg8
29b0f896 2415 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2416 || ((i.types[0].bitfield.reg8
2417 || i.types[1].bitfield.reg8)
29b0f896
AM		 2418 && i.rex != 0))
2419 {
2420 int x;
726c5dcd 2421
29b0f896
AM		 2422 i.rex |= REX_OPCODE;
2423 for (x = 0; x < 2; x++)
2424 {
2425 /* Look for 8 bit operand that uses old registers. */
40fb9820 2426 if (i.types[x].bitfield.reg8
29b0f896 2427 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2428 {
29b0f896
AM		 2429 /* In case it is "hi" register, give up. */
2430 if (i.op[x].regs->reg_num > 3)
a540244d 2431 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2432 "instruction requiring REX prefix."),
a540244d 2433 register_prefix, i.op[x].regs->reg_name);
773f551c 2434
29b0f896
AM		 2435 /* Otherwise it is equivalent to the extended register.
2436 Since the encoding doesn't change this is merely
2437 cosmetic cleanup for debug output. */
2438
2439 i.op[x].regs = i.op[x].regs + 8;
773f551c 2440 }
29b0f896
AM		 2441 }
2442 }
773f551c 2443
85f10a01
MM		 2444 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2445 REX prefix. */
2446 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2447 {
2448 i.drex.rex = i.rex;
2449 i.rex = 0;
2450 }
2451 else if (i.rex != 0)
29b0f896
AM		 2452 add_prefix (REX_OPCODE | i.rex);
2453
2454 /* We are ready to output the insn. */
2455 output_insn ();
2456}
2457
2458static char *
e3bb37b5 2459parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2460{
2461 char *l = line;
2462 char *token_start = l;
2463 char *mnem_p;
5c6af06e
JB		 2464 int supported;
2465 const template *t;
29b0f896
AM		 2466
2467 /* Non-zero if we found a prefix only acceptable with string insns. */
2468 const char *expecting_string_instruction = NULL;
45288df1 2469
29b0f896
AM		 2470 while (1)
2471 {
2472 mnem_p = mnemonic;
2473 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2474 {
2475 mnem_p++;
2476 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2477 {
29b0f896
AM		 2478 as_bad (_("no such instruction: `%s'"), token_start);
2479 return NULL;
2480 }
2481 l++;
2482 }
2483 if (!is_space_char (*l)
2484 && *l != END_OF_INSN
e44823cf
JB		 2485 && (intel_syntax
2486 || (*l != PREFIX_SEPARATOR
2487 && *l != ',')))
29b0f896
AM		 2488 {
2489 as_bad (_("invalid character %s in mnemonic"),
2490 output_invalid (*l));
2491 return NULL;
2492 }
2493 if (token_start == l)
2494 {
e44823cf 2495 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2496 as_bad (_("expecting prefix; got nothing"));
2497 else
2498 as_bad (_("expecting mnemonic; got nothing"));
2499 return NULL;
2500 }
45288df1 2501
29b0f896
AM		 2502 /* Look up instruction (or prefix) via hash table. */
2503 current_templates = hash_find (op_hash, mnemonic);
47926f60 2504
29b0f896
AM		 2505 if (*l != END_OF_INSN
2506 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2507 && current_templates
40fb9820 2508 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2509 {
c6fb90c8 2510 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2511 {
2512 as_bad ((flag_code != CODE_64BIT
2513 ? _("`%s' is only supported in 64-bit mode")
2514 : _("`%s' is not supported in 64-bit mode")),
2515 current_templates->start->name);
2516 return NULL;
2517 }
29b0f896
AM		 2518 /* If we are in 16-bit mode, do not allow addr16 or data16.
2519 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2520 if ((current_templates->start->opcode_modifier.size16
2521 || current_templates->start->opcode_modifier.size32)
29b0f896 2522 && flag_code != CODE_64BIT
40fb9820 2523 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2524 ^ (flag_code == CODE_16BIT)))
2525 {
2526 as_bad (_("redundant %s prefix"),
2527 current_templates->start->name);
2528 return NULL;
45288df1 2529 }
29b0f896
AM		 2530 /* Add prefix, checking for repeated prefixes. */
2531 switch (add_prefix (current_templates->start->base_opcode))
2532 {
2533 case 0:
2534 return NULL;
2535 case 2:
2536 expecting_string_instruction = current_templates->start->name;
2537 break;
2538 }
2539 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2540 token_start = ++l;
2541 }
2542 else
2543 break;
2544 }
45288df1 2545
29b0f896
AM		 2546 if (!current_templates)
2547 {
2548 /* See if we can get a match by trimming off a suffix. */
2549 switch (mnem_p[-1])
2550 {
2551 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2552 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2553 i.suffix = SHORT_MNEM_SUFFIX;
2554 else
29b0f896
AM		 2555 case BYTE_MNEM_SUFFIX:
2556 case QWORD_MNEM_SUFFIX:
2557 i.suffix = mnem_p[-1];
2558 mnem_p[-1] = '\0';
2559 current_templates = hash_find (op_hash, mnemonic);
2560 break;
2561 case SHORT_MNEM_SUFFIX:
2562 case LONG_MNEM_SUFFIX:
2563 if (!intel_syntax)
2564 {
2565 i.suffix = mnem_p[-1];
2566 mnem_p[-1] = '\0';
2567 current_templates = hash_find (op_hash, mnemonic);
2568 }
2569 break;
252b5132 2570
29b0f896
AM		 2571 /* Intel Syntax. */
2572 case 'd':
2573 if (intel_syntax)
2574 {
9306ca4a 2575 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2576 i.suffix = SHORT_MNEM_SUFFIX;
2577 else
2578 i.suffix = LONG_MNEM_SUFFIX;
2579 mnem_p[-1] = '\0';
2580 current_templates = hash_find (op_hash, mnemonic);
2581 }
2582 break;
2583 }
2584 if (!current_templates)
2585 {
2586 as_bad (_("no such instruction: `%s'"), token_start);
2587 return NULL;
2588 }
2589 }
252b5132 2590
40fb9820
L		 2591 if (current_templates->start->opcode_modifier.jump
2592 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 2593 {
2594 /* Check for a branch hint. We allow ",pt" and ",pn" for
2595 predict taken and predict not taken respectively.
2596 I'm not sure that branch hints actually do anything on loop
2597 and jcxz insns (JumpByte) for current Pentium4 chips. They
2598 may work in the future and it doesn't hurt to accept them
2599 now. */
2600 if (l[0] == ',' && l[1] == 'p')
2601 {
2602 if (l[2] == 't')
2603 {
2604 if (!add_prefix (DS_PREFIX_OPCODE))
2605 return NULL;
2606 l += 3;
2607 }
2608 else if (l[2] == 'n')
2609 {
2610 if (!add_prefix (CS_PREFIX_OPCODE))
2611 return NULL;
2612 l += 3;
2613 }
2614 }
2615 }
2616 /* Any other comma loses. */
2617 if (*l == ',')
2618 {
2619 as_bad (_("invalid character %s in mnemonic"),
2620 output_invalid (*l));
2621 return NULL;
2622 }
252b5132 2623
29b0f896 2624 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2625 supported = 0;
2626 for (t = current_templates->start; t < current_templates->end; ++t)
2627 {
3629bb00
L		 2628 supported |= cpu_flags_match (t->cpu_flags);
2629 if (supported == 3)
2630 goto skip;
5c6af06e 2631 }
3629bb00 2632
5c6af06e
JB		 2633 if (!(supported & 2))
2634 {
2635 as_bad (flag_code == CODE_64BIT
2636 ? _("`%s' is not supported in 64-bit mode")
2637 : _("`%s' is only supported in 64-bit mode"),
2638 current_templates->start->name);
2639 return NULL;
2640 }
2641 if (!(supported & 1))
29b0f896 2642 {
3629bb00
L		 2643 as_bad (_("`%s' is not supported on `%s%s'"),
2644 current_templates->start->name, cpu_arch_name,
2645 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2646 return NULL;
29b0f896 2647 }
3629bb00
L		 2648
2649skip:
2650 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 2651 && (flag_code != CODE_16BIT))
29b0f896
AM		 2652 {
2653 as_warn (_("use .code16 to ensure correct addressing mode"));
2654 }
252b5132 2655
29b0f896 2656 /* Check for rep/repne without a string instruction. */
f41bbced 2657 if (expecting_string_instruction)
29b0f896 2658 {
f41bbced
JB		 2659 static templates override;
2660
2661 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 2662 if (t->opcode_modifier.isstring)
f41bbced
JB		 2663 break;
2664 if (t >= current_templates->end)
2665 {
2666 as_bad (_("expecting string instruction after `%s'"),
64e74474 2667 expecting_string_instruction);
f41bbced
JB		 2668 return NULL;
2669 }
2670 for (override.start = t; t < current_templates->end; ++t)
40fb9820 2671 if (!t->opcode_modifier.isstring)
f41bbced
JB		 2672 break;
2673 override.end = t;
2674 current_templates = &override;
29b0f896 2675 }
252b5132 2676
29b0f896
AM		 2677 return l;
2678}
252b5132 2679
29b0f896 2680static char *
e3bb37b5 2681parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2682{
2683 char *token_start;
3138f287 2684
29b0f896
AM		 2685 /* 1 if operand is pending after ','. */
2686 unsigned int expecting_operand = 0;
252b5132 2687
29b0f896
AM		 2688 /* Non-zero if operand parens not balanced. */
2689 unsigned int paren_not_balanced;
2690
2691 while (*l != END_OF_INSN)
2692 {
2693 /* Skip optional white space before operand. */
2694 if (is_space_char (*l))
2695 ++l;
2696 if (!is_operand_char (*l) && *l != END_OF_INSN)
2697 {
2698 as_bad (_("invalid character %s before operand %d"),
2699 output_invalid (*l),
2700 i.operands + 1);
2701 return NULL;
2702 }
2703 token_start = l; /* after white space */
2704 paren_not_balanced = 0;
2705 while (paren_not_balanced || *l != ',')
2706 {
2707 if (*l == END_OF_INSN)
2708 {
2709 if (paren_not_balanced)
2710 {
2711 if (!intel_syntax)
2712 as_bad (_("unbalanced parenthesis in operand %d."),
2713 i.operands + 1);
2714 else
2715 as_bad (_("unbalanced brackets in operand %d."),
2716 i.operands + 1);
2717 return NULL;
2718 }
2719 else
2720 break; /* we are done */
2721 }
2722 else if (!is_operand_char (*l) && !is_space_char (*l))
2723 {
2724 as_bad (_("invalid character %s in operand %d"),
2725 output_invalid (*l),
2726 i.operands + 1);
2727 return NULL;
2728 }
2729 if (!intel_syntax)
2730 {
2731 if (*l == '(')
2732 ++paren_not_balanced;
2733 if (*l == ')')
2734 --paren_not_balanced;
2735 }
2736 else
2737 {
2738 if (*l == '[')
2739 ++paren_not_balanced;
2740 if (*l == ']')
2741 --paren_not_balanced;
2742 }
2743 l++;
2744 }
2745 if (l != token_start)
2746 { /* Yes, we've read in another operand. */
2747 unsigned int operand_ok;
2748 this_operand = i.operands++;
7d5e4556 2749 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 2750 if (i.operands > MAX_OPERANDS)
2751 {
2752 as_bad (_("spurious operands; (%d operands/instruction max)"),
2753 MAX_OPERANDS);
2754 return NULL;
2755 }
2756 /* Now parse operand adding info to 'i' as we go along. */
2757 END_STRING_AND_SAVE (l);
2758
2759 if (intel_syntax)
2760 operand_ok =
2761 i386_intel_operand (token_start,
2762 intel_float_operand (mnemonic));
2763 else
a7619375 2764 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 2765
2766 RESTORE_END_STRING (l);
2767 if (!operand_ok)
2768 return NULL;
2769 }
2770 else
2771 {
2772 if (expecting_operand)
2773 {
2774 expecting_operand_after_comma:
2775 as_bad (_("expecting operand after ','; got nothing"));
2776 return NULL;
2777 }
2778 if (*l == ',')
2779 {
2780 as_bad (_("expecting operand before ','; got nothing"));
2781 return NULL;
2782 }
2783 }
7f3f1ea2 2784
29b0f896
AM		 2785 /* Now *l must be either ',' or END_OF_INSN. */
2786 if (*l == ',')
2787 {
2788 if (*++l == END_OF_INSN)
2789 {
2790 /* Just skip it, if it's \n complain. */
2791 goto expecting_operand_after_comma;
2792 }
2793 expecting_operand = 1;
2794 }
2795 }
2796 return l;
2797}
7f3f1ea2 2798
050dfa73 2799static void
4d456e3d 2800swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2801{
2802 union i386_op temp_op;
40fb9820 2803 i386_operand_type temp_type;
050dfa73 2804 enum bfd_reloc_code_real temp_reloc;
4eed87de 2805
050dfa73
MM		 2806 temp_type = i.types[xchg2];
2807 i.types[xchg2] = i.types[xchg1];
2808 i.types[xchg1] = temp_type;
2809 temp_op = i.op[xchg2];
2810 i.op[xchg2] = i.op[xchg1];
2811 i.op[xchg1] = temp_op;
2812 temp_reloc = i.reloc[xchg2];
2813 i.reloc[xchg2] = i.reloc[xchg1];
2814 i.reloc[xchg1] = temp_reloc;
2815}
2816
29b0f896 2817static void
e3bb37b5 2818swap_operands (void)
29b0f896 2819{
b7c61d9a 2820 switch (i.operands)
050dfa73 2821 {
b7c61d9a 2822 case 4:
4d456e3d 2823 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2824 case 3:
2825 case 2:
4d456e3d 2826 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2827 break;
2828 default:
2829 abort ();
29b0f896 2830 }
29b0f896
AM		 2831
2832 if (i.mem_operands == 2)
2833 {
2834 const seg_entry *temp_seg;
2835 temp_seg = i.seg[0];
2836 i.seg[0] = i.seg[1];
2837 i.seg[1] = temp_seg;
2838 }
2839}
252b5132 2840
29b0f896
AM		 2841/* Try to ensure constant immediates are represented in the smallest
2842 opcode possible. */
2843static void
e3bb37b5 2844optimize_imm (void)
29b0f896
AM		 2845{
2846 char guess_suffix = 0;
2847 int op;
252b5132 2848
29b0f896
AM		 2849 if (i.suffix)
2850 guess_suffix = i.suffix;
2851 else if (i.reg_operands)
2852 {
2853 /* Figure out a suffix from the last register operand specified.
2854 We can't do this properly yet, ie. excluding InOutPortReg,
2855 but the following works for instructions with immediates.
2856 In any case, we can't set i.suffix yet. */
2857 for (op = i.operands; --op >= 0;)
40fb9820
L		 2858 if (i.types[op].bitfield.reg8)
2859 {
2860 guess_suffix = BYTE_MNEM_SUFFIX;
2861 break;
2862 }
2863 else if (i.types[op].bitfield.reg16)
252b5132 2864 {
40fb9820
L		 2865 guess_suffix = WORD_MNEM_SUFFIX;
2866 break;
2867 }
2868 else if (i.types[op].bitfield.reg32)
2869 {
2870 guess_suffix = LONG_MNEM_SUFFIX;
2871 break;
2872 }
2873 else if (i.types[op].bitfield.reg64)
2874 {
2875 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 2876 break;
252b5132 2877 }
29b0f896
AM		 2878 }
2879 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2880 guess_suffix = WORD_MNEM_SUFFIX;
2881
2882 for (op = i.operands; --op >= 0;)
40fb9820 2883 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 2884 {
2885 switch (i.op[op].imms->X_op)
252b5132 2886 {
29b0f896
AM		 2887 case O_constant:
2888 /* If a suffix is given, this operand may be shortened. */
2889 switch (guess_suffix)
252b5132 2890 {
29b0f896 2891 case LONG_MNEM_SUFFIX:
40fb9820
L		 2892 i.types[op].bitfield.imm32 = 1;
2893 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2894 break;
2895 case WORD_MNEM_SUFFIX:
40fb9820
L		 2896 i.types[op].bitfield.imm16 = 1;
2897 i.types[op].bitfield.imm32 = 1;
2898 i.types[op].bitfield.imm32s = 1;
2899 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2900 break;
2901 case BYTE_MNEM_SUFFIX:
40fb9820
L		 2902 i.types[op].bitfield.imm8 = 1;
2903 i.types[op].bitfield.imm8s = 1;
2904 i.types[op].bitfield.imm16 = 1;
2905 i.types[op].bitfield.imm32 = 1;
2906 i.types[op].bitfield.imm32s = 1;
2907 i.types[op].bitfield.imm64 = 1;
29b0f896 2908 break;
252b5132 2909 }
252b5132 2910
29b0f896
AM		 2911 /* If this operand is at most 16 bits, convert it
2912 to a signed 16 bit number before trying to see
2913 whether it will fit in an even smaller size.
2914 This allows a 16-bit operand such as $0xffe0 to
2915 be recognised as within Imm8S range. */
40fb9820 2916 if ((i.types[op].bitfield.imm16)
29b0f896 2917 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2918 {
29b0f896
AM		 2919 i.op[op].imms->X_add_number =
2920 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2921 }
40fb9820 2922 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 2923 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2924 == 0))
2925 {
2926 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2927 ^ ((offsetT) 1 << 31))
2928 - ((offsetT) 1 << 31));
2929 }
40fb9820 2930 i.types[op]
c6fb90c8
L		 2931 = operand_type_or (i.types[op],
2932 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 2933
29b0f896
AM		 2934 /* We must avoid matching of Imm32 templates when 64bit
2935 only immediate is available. */
2936 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 2937 i.types[op].bitfield.imm32 = 0;
29b0f896 2938 break;
252b5132 2939
29b0f896
AM		 2940 case O_absent:
2941 case O_register:
2942 abort ();
2943
2944 /* Symbols and expressions. */
2945 default:
9cd96992
JB		 2946 /* Convert symbolic operand to proper sizes for matching, but don't
2947 prevent matching a set of insns that only supports sizes other
2948 than those matching the insn suffix. */
2949 {
40fb9820 2950 i386_operand_type mask, allowed;
9cd96992
JB		 2951 const template *t;
2952
c6fb90c8
L		 2953 UINTS_CLEAR (mask);
2954 UINTS_CLEAR (allowed);
40fb9820 2955
4eed87de
AM		 2956 for (t = current_templates->start;
2957 t < current_templates->end;
2958 ++t)
c6fb90c8
L		 2959 allowed = operand_type_or (allowed,
2960 t->operand_types[op]);
9cd96992
JB		 2961 switch (guess_suffix)
2962 {
2963 case QWORD_MNEM_SUFFIX:
40fb9820
L		 2964 mask.bitfield.imm64 = 1;
2965 mask.bitfield.imm32s = 1;
9cd96992
JB		 2966 break;
2967 case LONG_MNEM_SUFFIX:
40fb9820 2968 mask.bitfield.imm32 = 1;
9cd96992
JB		 2969 break;
2970 case WORD_MNEM_SUFFIX:
40fb9820 2971 mask.bitfield.imm16 = 1;
9cd96992
JB		 2972 break;
2973 case BYTE_MNEM_SUFFIX:
40fb9820 2974 mask.bitfield.imm8 = 1;
9cd96992
JB		 2975 break;
2976 default:
9cd96992
JB		 2977 break;
2978 }
c6fb90c8
L		 2979 allowed = operand_type_and (mask, allowed);
2980 if (!UINTS_ALL_ZERO (allowed))
2981 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 2982 }
29b0f896 2983 break;
252b5132 2984 }
29b0f896
AM		 2985 }
2986}
47926f60 2987
29b0f896
AM		 2988/* Try to use the smallest displacement type too. */
2989static void
e3bb37b5 2990optimize_disp (void)
29b0f896
AM		 2991{
2992 int op;
3e73aa7c 2993
29b0f896 2994 for (op = i.operands; --op >= 0;)
40fb9820 2995 if (operand_type_check (i.types[op], disp))
252b5132 2996 {
b300c311 2997 if (i.op[op].disps->X_op == O_constant)
252b5132 2998 {
b300c311 2999 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3000
40fb9820 3001 if (i.types[op].bitfield.disp16
b300c311
L		 3002 && (disp & ~(offsetT) 0xffff) == 0)
3003 {
3004 /* If this operand is at most 16 bits, convert
3005 to a signed 16 bit number and don't use 64bit
3006 displacement. */
3007 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3008 i.types[op].bitfield.disp64 = 0;
b300c311 3009 }
40fb9820 3010 if (i.types[op].bitfield.disp32
b300c311
L		 3011 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3012 {
3013 /* If this operand is at most 32 bits, convert
3014 to a signed 32 bit number and don't use 64bit
3015 displacement. */
3016 disp &= (((offsetT) 2 << 31) - 1);
3017 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3018 i.types[op].bitfield.disp64 = 0;
b300c311 3019 }
40fb9820 3020 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3021 {
40fb9820
L		 3022 i.types[op].bitfield.disp8 = 0;
3023 i.types[op].bitfield.disp16 = 0;
3024 i.types[op].bitfield.disp32 = 0;
3025 i.types[op].bitfield.disp32s = 0;
3026 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3027 i.op[op].disps = 0;
3028 i.disp_operands--;
3029 }
3030 else if (flag_code == CODE_64BIT)
3031 {
3032 if (fits_in_signed_long (disp))
28a9d8f5 3033 {
40fb9820
L		 3034 i.types[op].bitfield.disp64 = 0;
3035 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3036 }
b300c311 3037 if (fits_in_unsigned_long (disp))
40fb9820 3038 i.types[op].bitfield.disp32 = 1;
b300c311 3039 }
40fb9820
L		 3040 if ((i.types[op].bitfield.disp32
3041 || i.types[op].bitfield.disp32s
3042 || i.types[op].bitfield.disp16)
b300c311 3043 && fits_in_signed_byte (disp))
40fb9820 3044 i.types[op].bitfield.disp8 = 1;
252b5132 3045 }
67a4f2b7
AO		 3046 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3047 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3048 {
3049 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3050 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3051 i.types[op].bitfield.disp8 = 0;
3052 i.types[op].bitfield.disp16 = 0;
3053 i.types[op].bitfield.disp32 = 0;
3054 i.types[op].bitfield.disp32s = 0;
3055 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3056 }
3057 else
b300c311 3058 /* We only support 64bit displacement on constants. */
40fb9820 3059 i.types[op].bitfield.disp64 = 0;
252b5132 3060 }
29b0f896
AM		 3061}
3062
3063static int
e3bb37b5 3064match_template (void)
29b0f896
AM		 3065{
3066 /* Points to template once we've found it. */
3067 const template *t;
40fb9820 3068 i386_operand_type overlap0, overlap1, overlap2, overlap3;
29b0f896 3069 unsigned int found_reverse_match;
40fb9820
L		 3070 i386_opcode_modifier suffix_check;
3071 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3072 int addr_prefix_disp;
a5c311ca 3073 unsigned int j;
3629bb00 3074 unsigned int found_cpu_match;
45664ddb 3075 unsigned int check_register;
29b0f896 3076
f48ff2ae
L		 3077#if MAX_OPERANDS != 4
3078# error "MAX_OPERANDS must be 4."
3079#endif
3080
29b0f896 3081 found_reverse_match = 0;
539e75ad 3082 addr_prefix_disp = -1;
40fb9820
L		 3083
3084 memset (&suffix_check, 0, sizeof (suffix_check));
3085 if (i.suffix == BYTE_MNEM_SUFFIX)
3086 suffix_check.no_bsuf = 1;
3087 else if (i.suffix == WORD_MNEM_SUFFIX)
3088 suffix_check.no_wsuf = 1;
3089 else if (i.suffix == SHORT_MNEM_SUFFIX)
3090 suffix_check.no_ssuf = 1;
3091 else if (i.suffix == LONG_MNEM_SUFFIX)
3092 suffix_check.no_lsuf = 1;
3093 else if (i.suffix == QWORD_MNEM_SUFFIX)
3094 suffix_check.no_qsuf = 1;
3095 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3096 suffix_check.no_ldsuf = 1;
29b0f896 3097
45aa61fe 3098 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3099 {
539e75ad
L		 3100 addr_prefix_disp = -1;
3101
29b0f896
AM		 3102 /* Must have right number of operands. */
3103 if (i.operands != t->operands)
3104 continue;
3105
50aecf8c
L		 3106 /* Check processor support. */
3107 found_cpu_match = cpu_flags_match (t->cpu_flags) == 3;
3108 if (!found_cpu_match)
3109 continue;
3110
e1d4d893
L		 3111 /* Check old gcc support. */
3112 if (!old_gcc && t->opcode_modifier.oldgcc)
3113 continue;
3114
3115 /* Check AT&T mnemonic. */
3116 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3117 continue;
3118
5c07affc
L		 3119 /* Check AT&T syntax Intel syntax. */
3120 if ((intel_syntax && t->opcode_modifier.attsyntax)
3121 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3122 continue;
3123
20592a94 3124 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3125 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3126 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3127 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3128 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3129 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3130 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3131 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3132 continue;
3133
5c07affc 3134 if (!operand_size_match (t))
7d5e4556 3135 continue;
539e75ad 3136
5c07affc
L		 3137 for (j = 0; j < MAX_OPERANDS; j++)
3138 operand_types[j] = t->operand_types[j];
3139
45aa61fe
AM		 3140 /* In general, don't allow 64-bit operands in 32-bit mode. */
3141 if (i.suffix == QWORD_MNEM_SUFFIX
3142 && flag_code != CODE_64BIT
3143 && (intel_syntax
40fb9820 3144 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3145 && !intel_float_operand (t->name))
3146 : intel_float_operand (t->name) != 2)
40fb9820
L		 3147 && ((!operand_types[0].bitfield.regmmx
3148 && !operand_types[0].bitfield.regxmm)
3149 || (!operand_types[t->operands > 1].bitfield.regmmx
3150 && !!operand_types[t->operands > 1].bitfield.regxmm))
45aa61fe
AM		 3151 && (t->base_opcode != 0x0fc7
3152 || t->extension_opcode != 1 /* cmpxchg8b */))
3153 continue;
3154
29b0f896 3155 /* Do not verify operands when there are none. */
50aecf8c 3156 else
29b0f896 3157 {
c6fb90c8 3158 if (!t->operands)
2dbab7d5
L		 3159 /* We've found a match; break out of loop. */
3160 break;
29b0f896 3161 }
252b5132 3162
539e75ad
L		 3163 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3164 into Disp32/Disp16/Disp32 operand. */
3165 if (i.prefix[ADDR_PREFIX] != 0)
3166 {
40fb9820 3167 /* There should be only one Disp operand. */
539e75ad
L		 3168 switch (flag_code)
3169 {
3170 case CODE_16BIT:
40fb9820
L		 3171 for (j = 0; j < MAX_OPERANDS; j++)
3172 {
3173 if (operand_types[j].bitfield.disp16)
3174 {
3175 addr_prefix_disp = j;
3176 operand_types[j].bitfield.disp32 = 1;
3177 operand_types[j].bitfield.disp16 = 0;
3178 break;
3179 }
3180 }
539e75ad
L		 3181 break;
3182 case CODE_32BIT:
40fb9820
L		 3183 for (j = 0; j < MAX_OPERANDS; j++)
3184 {
3185 if (operand_types[j].bitfield.disp32)
3186 {
3187 addr_prefix_disp = j;
3188 operand_types[j].bitfield.disp32 = 0;
3189 operand_types[j].bitfield.disp16 = 1;
3190 break;
3191 }
3192 }
539e75ad
L		 3193 break;
3194 case CODE_64BIT:
40fb9820
L		 3195 for (j = 0; j < MAX_OPERANDS; j++)
3196 {
3197 if (operand_types[j].bitfield.disp64)
3198 {
3199 addr_prefix_disp = j;
3200 operand_types[j].bitfield.disp64 = 0;
3201 operand_types[j].bitfield.disp32 = 1;
3202 break;
3203 }
3204 }
539e75ad
L		 3205 break;
3206 }
539e75ad
L		 3207 }
3208
45664ddb
L		 3209 /* We check register size only if size of operands can be
3210 encoded the canonical way. */
3211 check_register = t->opcode_modifier.w;
c6fb90c8 3212 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3213 switch (t->operands)
3214 {
3215 case 1:
40fb9820 3216 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3217 continue;
3218 break;
3219 case 2:
8b38ad71
L		 3220 /* xchg %eax, %eax is a special case. It is an aliase for nop
3221 only in 32bit mode and we can use opcode 0x90. In 64bit
3222 mode, we can't use 0x90 for xchg %eax, %eax since it should
3223 zero-extend %eax to %rax. */
3224 if (flag_code == CODE_64BIT
3225 && t->base_opcode == 0x90
c6fb90c8
L		 3226 && UINTS_EQUAL (i.types [0], acc32)
3227 && UINTS_EQUAL (i.types [1], acc32))
8b38ad71 3228 continue;
29b0f896 3229 case 3:
f48ff2ae 3230 case 4:
c6fb90c8 3231 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3232 if (!operand_type_match (overlap0, i.types[0])
3233 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3234 || (check_register
3235 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3236 operand_types[0],
3237 overlap1, i.types[1],
3238 operand_types[1])))
29b0f896
AM		 3239 {
3240 /* Check if other direction is valid ... */
40fb9820 3241 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3242 continue;
3243
3244 /* Try reversing direction of operands. */
c6fb90c8
L		 3245 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3246 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3247 if (!operand_type_match (overlap0, i.types[0])
3248 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3249 || (check_register
3250 && !operand_type_register_match (overlap0,
3251 i.types[0],
3252 operand_types[1],
3253 overlap1,
3254 i.types[1],
3255 operand_types[0])))
29b0f896
AM		 3256 {
3257 /* Does not match either direction. */
3258 continue;
3259 }
3260 /* found_reverse_match holds which of D or FloatDR
3261 we've found. */
40fb9820 3262 if (t->opcode_modifier.d)
8a2ed489 3263 found_reverse_match = Opcode_D;
40fb9820 3264 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3265 found_reverse_match = Opcode_FloatD;
3266 else
3267 found_reverse_match = 0;
40fb9820 3268 if (t->opcode_modifier.floatr)
8a2ed489 3269 found_reverse_match |= Opcode_FloatR;
29b0f896 3270 }
f48ff2ae 3271 else
29b0f896 3272 {
f48ff2ae 3273 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3274 switch (t->operands)
3275 {
3276 case 4:
c6fb90c8
L		 3277 overlap3 = operand_type_and (i.types[3],
3278 operand_types[3]);
d1cbb4db 3279 case 3:
c6fb90c8
L		 3280 overlap2 = operand_type_and (i.types[2],
3281 operand_types[2]);
d1cbb4db
L		 3282 break;
3283 }
29b0f896 3284
f48ff2ae
L		 3285 switch (t->operands)
3286 {
3287 case 4:
40fb9820 3288 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3289 || (check_register
3290 && !operand_type_register_match (overlap2,
3291 i.types[2],
3292 operand_types[2],
3293 overlap3,
3294 i.types[3],
3295 operand_types[3])))
f48ff2ae
L		 3296 continue;
3297 case 3:
3298 /* Here we make use of the fact that there are no
3299 reverse match 3 operand instructions, and all 3
3300 operand instructions only need to be checked for
3301 register consistency between operands 2 and 3. */
40fb9820 3302 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3303 || (check_register
3304 && !operand_type_register_match (overlap1,
3305 i.types[1],
3306 operand_types[1],
3307 overlap2,
3308 i.types[2],
3309 operand_types[2])))
f48ff2ae
L		 3310 continue;
3311 break;
3312 }
29b0f896 3313 }
f48ff2ae 3314 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3315 slip through to break. */
3316 }
3629bb00 3317 if (!found_cpu_match)
29b0f896
AM		 3318 {
3319 found_reverse_match = 0;
3320 continue;
3321 }
3322 /* We've found a match; break out of loop. */
3323 break;
3324 }
3325
3326 if (t == current_templates->end)
3327 {
3328 /* We found no match. */
3329 as_bad (_("suffix or operands invalid for `%s'"),
3330 current_templates->start->name);
3331 return 0;
3332 }
252b5132 3333
29b0f896
AM		 3334 if (!quiet_warnings)
3335 {
3336 if (!intel_syntax
40fb9820
L		 3337 && (i.types[0].bitfield.jumpabsolute
3338 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3339 {
3340 as_warn (_("indirect %s without `*'"), t->name);
3341 }
3342
40fb9820
L		 3343 if (t->opcode_modifier.isprefix
3344 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3345 {
3346 /* Warn them that a data or address size prefix doesn't
3347 affect assembly of the next line of code. */
3348 as_warn (_("stand-alone `%s' prefix"), t->name);
3349 }
3350 }
3351
3352 /* Copy the template we found. */
3353 i.tm = *t;
539e75ad
L		 3354
3355 if (addr_prefix_disp != -1)
3356 i.tm.operand_types[addr_prefix_disp]
3357 = operand_types[addr_prefix_disp];
3358
29b0f896
AM		 3359 if (found_reverse_match)
3360 {
3361 /* If we found a reverse match we must alter the opcode
3362 direction bit. found_reverse_match holds bits to change
3363 (different for int & float insns). */
3364
3365 i.tm.base_opcode ^= found_reverse_match;
3366
539e75ad
L		 3367 i.tm.operand_types[0] = operand_types[1];
3368 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3369 }
3370
3371 return 1;
3372}
3373
3374static int
e3bb37b5 3375check_string (void)
29b0f896 3376{
40fb9820
L		 3377 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3378 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3379 {
3380 if (i.seg[0] != NULL && i.seg[0] != &es)
3381 {
3382 as_bad (_("`%s' operand %d must use `%%es' segment"),
3383 i.tm.name,
3384 mem_op + 1);
3385 return 0;
3386 }
3387 /* There's only ever one segment override allowed per instruction.
3388 This instruction possibly has a legal segment override on the
3389 second operand, so copy the segment to where non-string
3390 instructions store it, allowing common code. */
3391 i.seg[0] = i.seg[1];
3392 }
40fb9820 3393 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3394 {
3395 if (i.seg[1] != NULL && i.seg[1] != &es)
3396 {
3397 as_bad (_("`%s' operand %d must use `%%es' segment"),
3398 i.tm.name,
3399 mem_op + 2);
3400 return 0;
3401 }
3402 }
3403 return 1;
3404}
3405
3406static int
543613e9 3407process_suffix (void)
29b0f896
AM		 3408{
3409 /* If matched instruction specifies an explicit instruction mnemonic
3410 suffix, use it. */
40fb9820
L		 3411 if (i.tm.opcode_modifier.size16)
3412 i.suffix = WORD_MNEM_SUFFIX;
3413 else if (i.tm.opcode_modifier.size32)
3414 i.suffix = LONG_MNEM_SUFFIX;
3415 else if (i.tm.opcode_modifier.size64)
3416 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3417 else if (i.reg_operands)
3418 {
3419 /* If there's no instruction mnemonic suffix we try to invent one
3420 based on register operands. */
3421 if (!i.suffix)
3422 {
3423 /* We take i.suffix from the last register operand specified,
3424 Destination register type is more significant than source
381d071f
L		 3425 register type. crc32 in SSE4.2 prefers source register
3426 type. */
3427 if (i.tm.base_opcode == 0xf20f38f1)
3428 {
40fb9820
L		 3429 if (i.types[0].bitfield.reg16)
3430 i.suffix = WORD_MNEM_SUFFIX;
3431 else if (i.types[0].bitfield.reg32)
3432 i.suffix = LONG_MNEM_SUFFIX;
3433 else if (i.types[0].bitfield.reg64)
3434 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3435 }
9344ff29 3436 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3437 {
40fb9820 3438 if (i.types[0].bitfield.reg8)
20592a94
L		 3439 i.suffix = BYTE_MNEM_SUFFIX;
3440 }
381d071f
L		 3441
3442 if (!i.suffix)
3443 {
3444 int op;
3445
20592a94
L		 3446 if (i.tm.base_opcode == 0xf20f38f1
3447 || i.tm.base_opcode == 0xf20f38f0)
3448 {
3449 /* We have to know the operand size for crc32. */
3450 as_bad (_("ambiguous memory operand size for `%s`"),
3451 i.tm.name);
3452 return 0;
3453 }
3454
381d071f 3455 for (op = i.operands; --op >= 0;)
40fb9820 3456 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3457 {
40fb9820
L		 3458 if (i.types[op].bitfield.reg8)
3459 {
3460 i.suffix = BYTE_MNEM_SUFFIX;
3461 break;
3462 }
3463 else if (i.types[op].bitfield.reg16)
3464 {
3465 i.suffix = WORD_MNEM_SUFFIX;
3466 break;
3467 }
3468 else if (i.types[op].bitfield.reg32)
3469 {
3470 i.suffix = LONG_MNEM_SUFFIX;
3471 break;
3472 }
3473 else if (i.types[op].bitfield.reg64)
3474 {
3475 i.suffix = QWORD_MNEM_SUFFIX;
3476 break;
3477 }
381d071f
L		 3478 }
3479 }
29b0f896
AM		 3480 }
3481 else if (i.suffix == BYTE_MNEM_SUFFIX)
3482 {
3483 if (!check_byte_reg ())
3484 return 0;
3485 }
3486 else if (i.suffix == LONG_MNEM_SUFFIX)
3487 {
3488 if (!check_long_reg ())
3489 return 0;
3490 }
3491 else if (i.suffix == QWORD_MNEM_SUFFIX)
3492 {
955e1e6a
L		 3493 if (intel_syntax
3494 && i.tm.opcode_modifier.ignoresize
3495 && i.tm.opcode_modifier.no_qsuf)
3496 i.suffix = 0;
3497 else if (!check_qword_reg ())
29b0f896
AM		 3498 return 0;
3499 }
3500 else if (i.suffix == WORD_MNEM_SUFFIX)
3501 {
3502 if (!check_word_reg ())
3503 return 0;
3504 }
582d5edd
L		 3505 else if (i.suffix == XMMWORD_MNEM_SUFFIX)
3506 {
3507 /* Skip if the instruction has x suffix. match_template
3508 should check if it is a valid suffix. */
3509 }
40fb9820 3510 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 3511 /* Do nothing if the instruction is going to ignore the prefix. */
3512 ;
3513 else
3514 abort ();
3515 }
40fb9820 3516 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 3517 && !i.suffix
3518 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 3519 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 3520 {
3521 i.suffix = stackop_size;
3522 }
9306ca4a
JB		 3523 else if (intel_syntax
3524 && !i.suffix
40fb9820
L		 3525 && (i.tm.operand_types[0].bitfield.jumpabsolute
3526 || i.tm.opcode_modifier.jumpbyte
3527 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 3528 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3529 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 3530 {
3531 switch (flag_code)
3532 {
3533 case CODE_64BIT:
40fb9820 3534 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 3535 {
3536 i.suffix = QWORD_MNEM_SUFFIX;
3537 break;
3538 }
3539 case CODE_32BIT:
40fb9820 3540 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 3541 i.suffix = LONG_MNEM_SUFFIX;
3542 break;
3543 case CODE_16BIT:
40fb9820 3544 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 3545 i.suffix = WORD_MNEM_SUFFIX;
3546 break;
3547 }
3548 }
252b5132 3549
9306ca4a 3550 if (!i.suffix)
29b0f896 3551 {
9306ca4a
JB		 3552 if (!intel_syntax)
3553 {
40fb9820 3554 if (i.tm.opcode_modifier.w)
9306ca4a 3555 {
4eed87de
AM		 3556 as_bad (_("no instruction mnemonic suffix given and "
3557 "no register operands; can't size instruction"));
9306ca4a
JB		 3558 return 0;
3559 }
3560 }
3561 else
3562 {
40fb9820
L		 3563 unsigned int suffixes;
3564
3565 suffixes = !i.tm.opcode_modifier.no_bsuf;
3566 if (!i.tm.opcode_modifier.no_wsuf)
3567 suffixes |= 1 << 1;
3568 if (!i.tm.opcode_modifier.no_lsuf)
3569 suffixes |= 1 << 2;
fc4adea1 3570 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 3571 suffixes |= 1 << 3;
3572 if (!i.tm.opcode_modifier.no_ssuf)
3573 suffixes |= 1 << 4;
3574 if (!i.tm.opcode_modifier.no_qsuf)
3575 suffixes |= 1 << 5;
3576
3577 /* There are more than suffix matches. */
3578 if (i.tm.opcode_modifier.w
9306ca4a 3579 || ((suffixes & (suffixes - 1))
40fb9820
L		 3580 && !i.tm.opcode_modifier.defaultsize
3581 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 3582 {
3583 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3584 return 0;
3585 }
3586 }
29b0f896 3587 }
252b5132 3588
9306ca4a
JB		 3589 /* Change the opcode based on the operand size given by i.suffix;
3590 We don't need to change things for byte insns. */
3591
582d5edd
L		 3592 if (i.suffix
3593 && i.suffix != BYTE_MNEM_SUFFIX
3594 && i.suffix != XMMWORD_MNEM_SUFFIX)
29b0f896
AM		 3595 {
3596 /* It's not a byte, select word/dword operation. */
40fb9820 3597 if (i.tm.opcode_modifier.w)
29b0f896 3598 {
40fb9820 3599 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 3600 i.tm.base_opcode |= 8;
3601 else
3602 i.tm.base_opcode |= 1;
3603 }
0f3f3d8b 3604
29b0f896
AM		 3605 /* Now select between word & dword operations via the operand
3606 size prefix, except for instructions that will ignore this
3607 prefix anyway. */
ca61edf2 3608 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 3609 {
ca61edf2
L		 3610 /* The address size override prefix changes the size of the
3611 first operand. */
40fb9820
L		 3612 if ((flag_code == CODE_32BIT
3613 && i.op->regs[0].reg_type.bitfield.reg16)
3614 || (flag_code != CODE_32BIT
3615 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 3616 if (!add_prefix (ADDR_PREFIX_OPCODE))
3617 return 0;
3618 }
3619 else if (i.suffix != QWORD_MNEM_SUFFIX
3620 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 3621 && !i.tm.opcode_modifier.ignoresize
3622 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 3623 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3624 || (flag_code == CODE_64BIT
40fb9820 3625 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 3626 {
3627 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3628
40fb9820 3629 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 3630 prefix = ADDR_PREFIX_OPCODE;
252b5132 3631
29b0f896
AM		 3632 if (!add_prefix (prefix))
3633 return 0;
24eab124 3634 }
252b5132 3635
29b0f896
AM		 3636 /* Set mode64 for an operand. */
3637 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3638 && flag_code == CODE_64BIT
40fb9820 3639 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 3640 {
3641 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 3642 need rex64. cmpxchg8b is also a special case. */
3643 if (! (i.operands == 2
3644 && i.tm.base_opcode == 0x90
3645 && i.tm.extension_opcode == None
c6fb90c8
L		 3646 && UINTS_EQUAL (i.types [0], acc64)
3647 && UINTS_EQUAL (i.types [1], acc64))
d9a5e5e5
L		 3648 && ! (i.operands == 1
3649 && i.tm.base_opcode == 0xfc7
3650 && i.tm.extension_opcode == 1
40fb9820
L		 3651 && !operand_type_check (i.types [0], reg)
3652 && operand_type_check (i.types [0], anymem)))
f6bee062 3653 i.rex |= REX_W;
46e883c5 3654 }
3e73aa7c 3655
29b0f896
AM		 3656 /* Size floating point instruction. */
3657 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 3658 if (i.tm.opcode_modifier.floatmf)
543613e9 3659 i.tm.base_opcode ^= 4;
29b0f896 3660 }
7ecd2f8b 3661
29b0f896
AM		 3662 return 1;
3663}
3e73aa7c 3664
29b0f896 3665static int
543613e9 3666check_byte_reg (void)
29b0f896
AM		 3667{
3668 int op;
543613e9 3669
29b0f896
AM		 3670 for (op = i.operands; --op >= 0;)
3671 {
3672 /* If this is an eight bit register, it's OK. If it's the 16 or
3673 32 bit version of an eight bit register, we will just use the
3674 low portion, and that's OK too. */
40fb9820 3675 if (i.types[op].bitfield.reg8)
29b0f896
AM		 3676 continue;
3677
ca61edf2
L		 3678 /* Don't generate this warning if not needed. */
3679 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 3680 continue;
3681
9344ff29
L		 3682 /* crc32 doesn't generate this warning. */
3683 if (i.tm.base_opcode == 0xf20f38f0)
3684 continue;
3685
40fb9820
L		 3686 if ((i.types[op].bitfield.reg16
3687 || i.types[op].bitfield.reg32
3688 || i.types[op].bitfield.reg64)
3689 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3690 {
3691 /* Prohibit these changes in the 64bit mode, since the
3692 lowering is more complicated. */
3693 if (flag_code == CODE_64BIT
40fb9820 3694 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 3695 {
2ca3ace5
L		 3696 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3697 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3698 i.suffix);
3699 return 0;
3700 }
3701#if REGISTER_WARNINGS
3702 if (!quiet_warnings
40fb9820 3703 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 3704 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3705 register_prefix,
40fb9820 3706 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 3707 ? REGNAM_AL - REGNAM_AX
3708 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3709 register_prefix,
29b0f896
AM		 3710 i.op[op].regs->reg_name,
3711 i.suffix);
3712#endif
3713 continue;
3714 }
3715 /* Any other register is bad. */
40fb9820
L		 3716 if (i.types[op].bitfield.reg16
3717 || i.types[op].bitfield.reg32
3718 || i.types[op].bitfield.reg64
3719 || i.types[op].bitfield.regmmx
3720 || i.types[op].bitfield.regxmm
3721 || i.types[op].bitfield.sreg2
3722 || i.types[op].bitfield.sreg3
3723 || i.types[op].bitfield.control
3724 || i.types[op].bitfield.debug
3725 || i.types[op].bitfield.test
3726 || i.types[op].bitfield.floatreg
3727 || i.types[op].bitfield.floatacc)
29b0f896 3728 {
a540244d
L		 3729 as_bad (_("`%s%s' not allowed with `%s%c'"),
3730 register_prefix,
29b0f896
AM		 3731 i.op[op].regs->reg_name,
3732 i.tm.name,
3733 i.suffix);
3734 return 0;
3735 }
3736 }
3737 return 1;
3738}
3739
3740static int
e3bb37b5 3741check_long_reg (void)
29b0f896
AM		 3742{
3743 int op;
3744
3745 for (op = i.operands; --op >= 0;)
3746 /* Reject eight bit registers, except where the template requires
3747 them. (eg. movzb) */
40fb9820
L		 3748 if (i.types[op].bitfield.reg8
3749 && (i.tm.operand_types[op].bitfield.reg16
3750 || i.tm.operand_types[op].bitfield.reg32
3751 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3752 {
a540244d
L		 3753 as_bad (_("`%s%s' not allowed with `%s%c'"),
3754 register_prefix,
29b0f896
AM		 3755 i.op[op].regs->reg_name,
3756 i.tm.name,
3757 i.suffix);
3758 return 0;
3759 }
3760 /* Warn if the e prefix on a general reg is missing. */
3761 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3762 && i.types[op].bitfield.reg16
3763 && (i.tm.operand_types[op].bitfield.reg32
3764 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3765 {
3766 /* Prohibit these changes in the 64bit mode, since the
3767 lowering is more complicated. */
3768 if (flag_code == CODE_64BIT)
252b5132 3769 {
2ca3ace5
L		 3770 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3771 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3772 i.suffix);
3773 return 0;
252b5132 3774 }
29b0f896
AM		 3775#if REGISTER_WARNINGS
3776 else
a540244d
L		 3777 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3778 register_prefix,
29b0f896 3779 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3780 register_prefix,
29b0f896
AM		 3781 i.op[op].regs->reg_name,
3782 i.suffix);
3783#endif
252b5132 3784 }
29b0f896 3785 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 3786 else if (i.types[op].bitfield.reg64
3787 && (i.tm.operand_types[op].bitfield.reg32
3788 || i.tm.operand_types[op].bitfield.acc))
252b5132 3789 {
34828aad 3790 if (intel_syntax
ca61edf2 3791 && i.tm.opcode_modifier.toqword
40fb9820 3792 && !i.types[0].bitfield.regxmm)
34828aad 3793 {
ca61edf2 3794 /* Convert to QWORD. We want REX byte. */
34828aad
L		 3795 i.suffix = QWORD_MNEM_SUFFIX;
3796 }
3797 else
3798 {
3799 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3800 register_prefix, i.op[op].regs->reg_name,
3801 i.suffix);
3802 return 0;
3803 }
29b0f896
AM		 3804 }
3805 return 1;
3806}
252b5132 3807
29b0f896 3808static int
e3bb37b5 3809check_qword_reg (void)
29b0f896
AM		 3810{
3811 int op;
252b5132 3812
29b0f896
AM		 3813 for (op = i.operands; --op >= 0; )
3814 /* Reject eight bit registers, except where the template requires
3815 them. (eg. movzb) */
40fb9820
L		 3816 if (i.types[op].bitfield.reg8
3817 && (i.tm.operand_types[op].bitfield.reg16
3818 || i.tm.operand_types[op].bitfield.reg32
3819 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3820 {
a540244d
L		 3821 as_bad (_("`%s%s' not allowed with `%s%c'"),
3822 register_prefix,
29b0f896
AM		 3823 i.op[op].regs->reg_name,
3824 i.tm.name,
3825 i.suffix);
3826 return 0;
3827 }
3828 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 3829 else if ((i.types[op].bitfield.reg16
3830 || i.types[op].bitfield.reg32)
3831 && (i.tm.operand_types[op].bitfield.reg32
3832 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3833 {
3834 /* Prohibit these changes in the 64bit mode, since the
3835 lowering is more complicated. */
34828aad 3836 if (intel_syntax
ca61edf2 3837 && i.tm.opcode_modifier.todword
40fb9820 3838 && !i.types[0].bitfield.regxmm)
34828aad 3839 {
ca61edf2 3840 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 3841 i.suffix = LONG_MNEM_SUFFIX;
3842 }
3843 else
3844 {
3845 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3846 register_prefix, i.op[op].regs->reg_name,
3847 i.suffix);
3848 return 0;
3849 }
252b5132 3850 }
29b0f896
AM		 3851 return 1;
3852}
252b5132 3853
29b0f896 3854static int
e3bb37b5 3855check_word_reg (void)
29b0f896
AM		 3856{
3857 int op;
3858 for (op = i.operands; --op >= 0;)
3859 /* Reject eight bit registers, except where the template requires
3860 them. (eg. movzb) */
40fb9820
L		 3861 if (i.types[op].bitfield.reg8
3862 && (i.tm.operand_types[op].bitfield.reg16
3863 || i.tm.operand_types[op].bitfield.reg32
3864 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3865 {
a540244d
L		 3866 as_bad (_("`%s%s' not allowed with `%s%c'"),
3867 register_prefix,
29b0f896
AM		 3868 i.op[op].regs->reg_name,
3869 i.tm.name,
3870 i.suffix);
3871 return 0;
3872 }
3873 /* Warn if the e prefix on a general reg is present. */
3874 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3875 && i.types[op].bitfield.reg32
3876 && (i.tm.operand_types[op].bitfield.reg16
3877 || i.tm.operand_types[op].bitfield.acc))
252b5132 3878 {
29b0f896
AM		 3879 /* Prohibit these changes in the 64bit mode, since the
3880 lowering is more complicated. */
3881 if (flag_code == CODE_64BIT)
252b5132 3882 {
2ca3ace5
L		 3883 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3884 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3885 i.suffix);
3886 return 0;
252b5132 3887 }
29b0f896
AM		 3888 else
3889#if REGISTER_WARNINGS
a540244d
L		 3890 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3891 register_prefix,
29b0f896 3892 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 3893 register_prefix,
29b0f896
AM		 3894 i.op[op].regs->reg_name,
3895 i.suffix);
3896#endif
3897 }
3898 return 1;
3899}
252b5132 3900
29b0f896 3901static int
40fb9820 3902update_imm (unsigned int j)
29b0f896 3903{
40fb9820
L		 3904 i386_operand_type overlap;
3905
c6fb90c8 3906 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 3907 if ((overlap.bitfield.imm8
3908 || overlap.bitfield.imm8s
3909 || overlap.bitfield.imm16
3910 || overlap.bitfield.imm32
3911 || overlap.bitfield.imm32s
3912 || overlap.bitfield.imm64)
c6fb90c8
L		 3913 && !UINTS_EQUAL (overlap, imm8)
3914 && !UINTS_EQUAL (overlap, imm8s)
3915 && !UINTS_EQUAL (overlap, imm16)
3916 && !UINTS_EQUAL (overlap, imm32)
3917 && !UINTS_EQUAL (overlap, imm32s)
3918 && !UINTS_EQUAL (overlap, imm64))
29b0f896
AM		 3919 {
3920 if (i.suffix)
3921 {
40fb9820
L		 3922 i386_operand_type temp;
3923
c6fb90c8 3924 UINTS_CLEAR (temp);
40fb9820
L		 3925 if (i.suffix == BYTE_MNEM_SUFFIX)
3926 {
3927 temp.bitfield.imm8 = overlap.bitfield.imm8;
3928 temp.bitfield.imm8s = overlap.bitfield.imm8s;
3929 }
3930 else if (i.suffix == WORD_MNEM_SUFFIX)
3931 temp.bitfield.imm16 = overlap.bitfield.imm16;
3932 else if (i.suffix == QWORD_MNEM_SUFFIX)
3933 {
3934 temp.bitfield.imm64 = overlap.bitfield.imm64;
3935 temp.bitfield.imm32s = overlap.bitfield.imm32s;
3936 }
3937 else
3938 temp.bitfield.imm32 = overlap.bitfield.imm32;
3939 overlap = temp;
29b0f896 3940 }
c6fb90c8
L		 3941 else if (UINTS_EQUAL (overlap, imm16_32_32s)
3942 || UINTS_EQUAL (overlap, imm16_32)
3943 || UINTS_EQUAL (overlap, imm16_32s))
29b0f896 3944 {
c6fb90c8 3945 UINTS_CLEAR (overlap);
40fb9820
L		 3946 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3947 overlap.bitfield.imm16 = 1;
3948 else
3949 overlap.bitfield.imm32s = 1;
29b0f896 3950 }
c6fb90c8
L		 3951 if (!UINTS_EQUAL (overlap, imm8)
3952 && !UINTS_EQUAL (overlap, imm8s)
3953 && !UINTS_EQUAL (overlap, imm16)
3954 && !UINTS_EQUAL (overlap, imm32)
3955 && !UINTS_EQUAL (overlap, imm32s)
3956 && !UINTS_EQUAL (overlap, imm64))
29b0f896 3957 {
4eed87de
AM		 3958 as_bad (_("no instruction mnemonic suffix given; "
3959 "can't determine immediate size"));
29b0f896
AM		 3960 return 0;
3961 }
3962 }
40fb9820 3963 i.types[j] = overlap;
29b0f896 3964
40fb9820
L		 3965 return 1;
3966}
3967
3968static int
3969finalize_imm (void)
3970{
3971 unsigned int j;
29b0f896 3972
40fb9820
L		 3973 for (j = 0; j < 2; j++)
3974 if (update_imm (j) == 0)
3975 return 0;
3976
c6fb90c8 3977 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 3978 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 3979
3980 return 1;
3981}
3982
85f10a01
MM		 3983static void
3984process_drex (void)
3985{
5dd15031
JJ		 3986 i.drex.modrm_reg = 0;
3987 i.drex.modrm_regmem = 0;
85f10a01
MM		 3988
3989 /* SSE5 4 operand instructions must have the destination the same as
3990 one of the inputs. Figure out the destination register and cache
3991 it away in the drex field, and remember which fields to use for
3992 the modrm byte. */
3993 if (i.tm.opcode_modifier.drex
3994 && i.tm.opcode_modifier.drexv
3995 && i.operands == 4)
3996 {
3997 i.tm.extension_opcode = None;
3998
3999 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4000 if (i.types[0].bitfield.regxmm != 0
4001 && i.types[1].bitfield.regxmm != 0
4002 && i.types[2].bitfield.regxmm != 0
4003 && i.types[3].bitfield.regxmm != 0
4004 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4005 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4006 {
4007 /* Clear the arguments that are stored in drex. */
4008 UINTS_CLEAR (i.types[0]);
4009 UINTS_CLEAR (i.types[3]);
4010 i.reg_operands -= 2;
4011
4012 /* There are two different ways to encode a 4 operand
4013 instruction with all registers that uses OC1 set to
4014 0 or 1. Favor setting OC1 to 0 since this mimics the
4015 actions of other SSE5 assemblers. Use modrm encoding 2
4016 for register/register. Include the high order bit that
4017 is normally stored in the REX byte in the register
4018 field. */
4019 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4020 i.drex.modrm_reg = 2;
4021 i.drex.modrm_regmem = 1;
4022 i.drex.reg = (i.op[3].regs->reg_num
4023 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4024 }
4025
4026 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4027 else if (i.types[0].bitfield.regxmm != 0
4028 && i.types[1].bitfield.regxmm != 0
4029 && (i.types[2].bitfield.regxmm
4030 || operand_type_check (i.types[2], anymem))
4031 && i.types[3].bitfield.regxmm != 0
4032 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4033 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4034 {
4035 /* clear the arguments that are stored in drex */
4036 UINTS_CLEAR (i.types[0]);
4037 UINTS_CLEAR (i.types[3]);
4038 i.reg_operands -= 2;
4039
4040 /* Specify the modrm encoding for memory addressing. Include
4041 the high order bit that is normally stored in the REX byte
4042 in the register field. */
4043 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4044 i.drex.modrm_reg = 1;
4045 i.drex.modrm_regmem = 2;
4046 i.drex.reg = (i.op[3].regs->reg_num
4047 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4048 }
4049
4050 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4051 else if (i.types[0].bitfield.regxmm != 0
4052 && operand_type_check (i.types[1], anymem) != 0
4053 && i.types[2].bitfield.regxmm != 0
4054 && i.types[3].bitfield.regxmm != 0
4055 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4056 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4057 {
4058 /* Clear the arguments that are stored in drex. */
4059 UINTS_CLEAR (i.types[0]);
4060 UINTS_CLEAR (i.types[3]);
4061 i.reg_operands -= 2;
4062
4063 /* Specify the modrm encoding for memory addressing. Include
4064 the high order bit that is normally stored in the REX byte
4065 in the register field. */
4066 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4067 i.drex.modrm_reg = 2;
4068 i.drex.modrm_regmem = 1;
4069 i.drex.reg = (i.op[3].regs->reg_num
4070 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4071 }
4072
4073 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4074 else if (i.types[0].bitfield.regxmm != 0
4075 && i.types[1].bitfield.regxmm != 0
4076 && i.types[2].bitfield.regxmm != 0
4077 && i.types[3].bitfield.regxmm != 0
4078 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4079 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4080 {
4081 /* clear the arguments that are stored in drex */
4082 UINTS_CLEAR (i.types[2]);
4083 UINTS_CLEAR (i.types[3]);
4084 i.reg_operands -= 2;
4085
4086 /* There are two different ways to encode a 4 operand
4087 instruction with all registers that uses OC1 set to
4088 0 or 1. Favor setting OC1 to 0 since this mimics the
4089 actions of other SSE5 assemblers. Use modrm encoding
4090 2 for register/register. Include the high order bit that
4091 is normally stored in the REX byte in the register
4092 field. */
4093 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4094 i.drex.modrm_reg = 1;
4095 i.drex.modrm_regmem = 0;
4096
4097 /* Remember the register, including the upper bits */
4098 i.drex.reg = (i.op[3].regs->reg_num
4099 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4100 }
4101
4102 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4103 else if (i.types[0].bitfield.regxmm != 0
4104 && (i.types[1].bitfield.regxmm
4105 || operand_type_check (i.types[1], anymem))
4106 && i.types[2].bitfield.regxmm != 0
4107 && i.types[3].bitfield.regxmm != 0
4108 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4109 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4110 {
4111 /* Clear the arguments that are stored in drex. */
4112 UINTS_CLEAR (i.types[2]);
4113 UINTS_CLEAR (i.types[3]);
4114 i.reg_operands -= 2;
4115
4116 /* Specify the modrm encoding and remember the register
4117 including the bits normally stored in the REX byte. */
4118 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4119 i.drex.modrm_reg = 0;
4120 i.drex.modrm_regmem = 1;
4121 i.drex.reg = (i.op[3].regs->reg_num
4122 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4123 }
4124
4125 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4126 else if (operand_type_check (i.types[0], anymem) != 0
4127 && i.types[1].bitfield.regxmm != 0
4128 && i.types[2].bitfield.regxmm != 0
4129 && i.types[3].bitfield.regxmm != 0
4130 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4131 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4132 {
4133 /* clear the arguments that are stored in drex */
4134 UINTS_CLEAR (i.types[2]);
4135 UINTS_CLEAR (i.types[3]);
4136 i.reg_operands -= 2;
4137
4138 /* Specify the modrm encoding and remember the register
4139 including the bits normally stored in the REX byte. */
4140 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4141 i.drex.modrm_reg = 1;
4142 i.drex.modrm_regmem = 0;
4143 i.drex.reg = (i.op[3].regs->reg_num
4144 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4145 }
4146
4147 else
4148 as_bad (_("Incorrect operands for the '%s' instruction"),
4149 i.tm.name);
4150 }
4151
4152 /* SSE5 instructions with the DREX byte where the only memory operand
4153 is in the 2nd argument, and the first and last xmm register must
4154 match, and is encoded in the DREX byte. */
4155 else if (i.tm.opcode_modifier.drex
4156 && !i.tm.opcode_modifier.drexv
4157 && i.operands == 4)
4158 {
4159 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4160 if (i.types[0].bitfield.regxmm != 0
4161 && (i.types[1].bitfield.regxmm
4162 || operand_type_check(i.types[1], anymem))
4163 && i.types[2].bitfield.regxmm != 0
4164 && i.types[3].bitfield.regxmm != 0
4165 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4166 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4167 {
4168 /* clear the arguments that are stored in drex */
4169 UINTS_CLEAR (i.types[0]);
4170 UINTS_CLEAR (i.types[3]);
4171 i.reg_operands -= 2;
4172
4173 /* Specify the modrm encoding and remember the register
4174 including the high bit normally stored in the REX
4175 byte. */
4176 i.drex.modrm_reg = 2;
4177 i.drex.modrm_regmem = 1;
4178 i.drex.reg = (i.op[3].regs->reg_num
4179 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4180 }
4181
4182 else
4183 as_bad (_("Incorrect operands for the '%s' instruction"),
4184 i.tm.name);
4185 }
4186
4187 /* SSE5 3 operand instructions that the result is a register, being
4188 either operand can be a memory operand, using OC0 to note which
4189 one is the memory. */
4190 else if (i.tm.opcode_modifier.drex
4191 && i.tm.opcode_modifier.drexv
4192 && i.operands == 3)
4193 {
4194 i.tm.extension_opcode = None;
4195
4196 /* Case 1: 3 operand insn, src1 = register. */
4197 if (i.types[0].bitfield.regxmm != 0
4198 && i.types[1].bitfield.regxmm != 0
4199 && i.types[2].bitfield.regxmm != 0)
4200 {
4201 /* Clear the arguments that are stored in drex. */
4202 UINTS_CLEAR (i.types[2]);
4203 i.reg_operands--;
4204
4205 /* Specify the modrm encoding and remember the register
4206 including the high bit normally stored in the REX byte. */
4207 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4208 i.drex.modrm_reg = 1;
4209 i.drex.modrm_regmem = 0;
4210 i.drex.reg = (i.op[2].regs->reg_num
4211 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4212 }
4213
4214 /* Case 2: 3 operand insn, src1 = memory. */
4215 else if (operand_type_check (i.types[0], anymem) != 0
4216 && i.types[1].bitfield.regxmm != 0
4217 && i.types[2].bitfield.regxmm != 0)
4218 {
4219 /* Clear the arguments that are stored in drex. */
4220 UINTS_CLEAR (i.types[2]);
4221 i.reg_operands--;
4222
4223 /* Specify the modrm encoding and remember the register
4224 including the high bit normally stored in the REX
4225 byte. */
4226 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4227 i.drex.modrm_reg = 1;
4228 i.drex.modrm_regmem = 0;
4229 i.drex.reg = (i.op[2].regs->reg_num
4230 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4231 }
4232
4233 /* Case 3: 3 operand insn, src2 = memory. */
4234 else if (i.types[0].bitfield.regxmm != 0
4235 && operand_type_check (i.types[1], anymem) != 0
4236 && i.types[2].bitfield.regxmm != 0)
4237 {
4238 /* Clear the arguments that are stored in drex. */
4239 UINTS_CLEAR (i.types[2]);
4240 i.reg_operands--;
4241
4242 /* Specify the modrm encoding and remember the register
4243 including the high bit normally stored in the REX byte. */
4244 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4245 i.drex.modrm_reg = 0;
4246 i.drex.modrm_regmem = 1;
4247 i.drex.reg = (i.op[2].regs->reg_num
4248 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4249 }
4250
4251 else
4252 as_bad (_("Incorrect operands for the '%s' instruction"),
4253 i.tm.name);
4254 }
4255
4256 /* SSE5 4 operand instructions that are the comparison instructions
4257 where the first operand is the immediate value of the comparison
4258 to be done. */
4259 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4260 {
4261 /* Case 1: 4 operand insn, src1 = reg/memory. */
4262 if (operand_type_check (i.types[0], imm) != 0
4263 && (i.types[1].bitfield.regxmm
4264 || operand_type_check (i.types[1], anymem))
4265 && i.types[2].bitfield.regxmm != 0
4266 && i.types[3].bitfield.regxmm != 0)
4267 {
4268 /* clear the arguments that are stored in drex */
4269 UINTS_CLEAR (i.types[3]);
4270 i.reg_operands--;
4271
4272 /* Specify the modrm encoding and remember the register
4273 including the high bit normally stored in the REX byte. */
4274 i.drex.modrm_reg = 2;
4275 i.drex.modrm_regmem = 1;
4276 i.drex.reg = (i.op[3].regs->reg_num
4277 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4278 }
4279
4280 /* Case 2: 3 operand insn with ImmExt that places the
4281 opcode_extension as an immediate argument. This is used for
4282 all of the varients of comparison that supplies the appropriate
4283 value as part of the instruction. */
4284 else if ((i.types[0].bitfield.regxmm
4285 || operand_type_check (i.types[0], anymem))
4286 && i.types[1].bitfield.regxmm != 0
4287 && i.types[2].bitfield.regxmm != 0
4288 && operand_type_check (i.types[3], imm) != 0)
4289 {
4290 /* clear the arguments that are stored in drex */
4291 UINTS_CLEAR (i.types[2]);
4292 i.reg_operands--;
4293
4294 /* Specify the modrm encoding and remember the register
4295 including the high bit normally stored in the REX byte. */
4296 i.drex.modrm_reg = 1;
4297 i.drex.modrm_regmem = 0;
4298 i.drex.reg = (i.op[2].regs->reg_num
4299 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4300 }
4301
4302 else
4303 as_bad (_("Incorrect operands for the '%s' instruction"),
4304 i.tm.name);
4305 }
4306
4307 else if (i.tm.opcode_modifier.drex
4308 || i.tm.opcode_modifier.drexv
4309 || i.tm.opcode_modifier.drexc)
4310 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4311}
4312
29b0f896 4313static int
e3bb37b5 4314process_operands (void)
29b0f896
AM		 4315{
4316 /* Default segment register this instruction will use for memory
4317 accesses. 0 means unknown. This is only for optimizing out
4318 unnecessary segment overrides. */
4319 const seg_entry *default_seg = 0;
4320
85f10a01
MM		 4321 /* Handle all of the DREX munging that SSE5 needs. */
4322 if (i.tm.opcode_modifier.drex
4323 || i.tm.opcode_modifier.drexv
4324 || i.tm.opcode_modifier.drexc)
4325 process_drex ();
4326
e2ec9d29 4327 if (i.tm.opcode_modifier.firstxmm0)
29b0f896 4328 {
9fcfb3d7
L		 4329 unsigned int j;
4330
e2ec9d29
L		 4331 /* The first operand is implicit and must be xmm0. */
4332 assert (i.reg_operands && UINTS_EQUAL (i.types[0], regxmm));
4333 if (i.op[0].regs->reg_num != 0)
4334 {
4335 if (intel_syntax)
4336 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4337 i.tm.name, register_prefix);
4338 else
4339 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4340 i.tm.name, register_prefix);
4341 return 0;
4342 }
9fcfb3d7
L		 4343
4344 for (j = 1; j < i.operands; j++)
4345 {
4346 i.op[j - 1] = i.op[j];
4347 i.types[j - 1] = i.types[j];
4348
4349 /* We need to adjust fields in i.tm since they are used by
4350 build_modrm_byte. */
4351 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4352 }
4353
e2ec9d29
L		 4354 i.operands--;
4355 i.reg_operands--;
e2ec9d29
L		 4356 i.tm.operands--;
4357 }
4358 else if (i.tm.opcode_modifier.regkludge)
4359 {
4360 /* The imul $imm, %reg instruction is converted into
4361 imul $imm, %reg, %reg, and the clr %reg instruction
4362 is converted into xor %reg, %reg. */
4363
4364 unsigned int first_reg_op;
4365
4366 if (operand_type_check (i.types[0], reg))
4367 first_reg_op = 0;
4368 else
4369 first_reg_op = 1;
4370 /* Pretend we saw the extra register operand. */
4371 assert (i.reg_operands == 1
4372 && i.op[first_reg_op + 1].regs == 0);
4373 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4374 i.types[first_reg_op + 1] = i.types[first_reg_op];
4375 i.operands++;
4376 i.reg_operands++;
29b0f896
AM		 4377 }
4378
40fb9820 4379 if (i.tm.opcode_modifier.shortform)
29b0f896 4380 {
40fb9820
L		 4381 if (i.types[0].bitfield.sreg2
4382 || i.types[0].bitfield.sreg3)
29b0f896 4383 {
4eed87de
AM		 4384 if (i.tm.base_opcode == POP_SEG_SHORT
4385 && i.op[0].regs->reg_num == 1)
29b0f896 4386 {
4eed87de
AM		 4387 as_bad (_("you can't `pop %%cs'"));
4388 return 0;
29b0f896 4389 }
4eed87de
AM		 4390 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4391 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4392 i.rex |= REX_B;
4eed87de
AM		 4393 }
4394 else
4395 {
85f10a01
MM		 4396 /* The register or float register operand is in operand
4397 0 or 1. */
40fb9820
L		 4398 unsigned int op;
4399
4400 if (i.types[0].bitfield.floatreg
4401 || operand_type_check (i.types[0], reg))
4402 op = 0;
4403 else
4404 op = 1;
4eed87de
AM		 4405 /* Register goes in low 3 bits of opcode. */
4406 i.tm.base_opcode |= i.op[op].regs->reg_num;
4407 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4408 i.rex |= REX_B;
40fb9820 4409 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4410 {
4eed87de
AM		 4411 /* Warn about some common errors, but press on regardless.
4412 The first case can be generated by gcc (<= 2.8.1). */
4413 if (i.operands == 2)
4414 {
4415 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 4416 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4417 register_prefix, i.op[1].regs->reg_name,
4418 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 4419 }
4420 else
4421 {
4422 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4423 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4424 register_prefix, i.op[0].regs->reg_name);
4eed87de 4425 }
29b0f896
AM		 4426 }
4427 }
4428 }
40fb9820 4429 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4430 {
4431 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4432 must be put into the modrm byte). Now, we make the modrm and
4433 index base bytes based on all the info we've collected. */
29b0f896
AM		 4434
4435 default_seg = build_modrm_byte ();
4436 }
8a2ed489 4437 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4438 {
4439 default_seg = &ds;
4440 }
40fb9820 4441 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4442 {
4443 /* For the string instructions that allow a segment override
4444 on one of their operands, the default segment is ds. */
4445 default_seg = &ds;
4446 }
4447
75178d9d
L		 4448 if (i.tm.base_opcode == 0x8d /* lea */
4449 && i.seg[0]
4450 && !quiet_warnings)
30123838 4451 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4452
4453 /* If a segment was explicitly specified, and the specified segment
4454 is not the default, use an opcode prefix to select it. If we
4455 never figured out what the default segment is, then default_seg
4456 will be zero at this point, and the specified segment prefix will
4457 always be used. */
29b0f896
AM		 4458 if ((i.seg[0]) && (i.seg[0] != default_seg))
4459 {
4460 if (!add_prefix (i.seg[0]->seg_prefix))
4461 return 0;
4462 }
4463 return 1;
4464}
4465
4466static const seg_entry *
e3bb37b5 4467build_modrm_byte (void)
29b0f896
AM		 4468{
4469 const seg_entry *default_seg = 0;
4470
85f10a01
MM		 4471 /* SSE5 4 operand instructions are encoded in such a way that one of
4472 the inputs must match the destination register. Process_drex hides
4473 the 3rd argument in the drex field, so that by the time we get
4474 here, it looks to GAS as if this is a 2 operand instruction. */
4475 if ((i.tm.opcode_modifier.drex
4476 || i.tm.opcode_modifier.drexv
b5016f89 4477 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4478 && i.reg_operands == 2)
4479 {
4480 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4481 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4482
4483 i.rm.reg = reg->reg_num;
4484 i.rm.regmem = regmem->reg_num;
4485 i.rm.mode = 3;
4486 if ((reg->reg_flags & RegRex) != 0)
4487 i.rex |= REX_R;
4488 if ((regmem->reg_flags & RegRex) != 0)
4489 i.rex |= REX_B;
4490 }
4491
29b0f896
AM		 4492 /* i.reg_operands MUST be the number of real register operands;
4493 implicit registers do not count. */
85f10a01 4494 else if (i.reg_operands == 2)
29b0f896
AM		 4495 {
4496 unsigned int source, dest;
cab737b9
L		 4497
4498 switch (i.operands)
4499 {
4500 case 2:
4501 source = 0;
4502 break;
4503 case 3:
c81128dc
L		 4504 /* When there are 3 operands, one of them may be immediate,
4505 which may be the first or the last operand. Otherwise,
4506 the first operand must be shift count register (cl). */
4507 assert (i.imm_operands == 1
4508 || (i.imm_operands == 0
40fb9820
L		 4509 && i.types[0].bitfield.shiftcount));
4510 if (operand_type_check (i.types[0], imm)
4511 || i.types[0].bitfield.shiftcount)
4512 source = 1;
4513 else
4514 source = 0;
cab737b9
L		 4515 break;
4516 case 4:
368d64cc
L		 4517 /* When there are 4 operands, the first two must be 8bit
4518 immediate operands. The source operand will be the 3rd
4519 one. */
cab737b9 4520 assert (i.imm_operands == 2
368d64cc
L		 4521 && i.types[0].bitfield.imm8
4522 && i.types[1].bitfield.imm8);
cab737b9
L		 4523 source = 2;
4524 break;
4525 default:
4526 abort ();
4527 }
4528
29b0f896
AM		 4529 dest = source + 1;
4530
4531 i.rm.mode = 3;
4532 /* One of the register operands will be encoded in the i.tm.reg
4533 field, the other in the combined i.tm.mode and i.tm.regmem
4534 fields. If no form of this instruction supports a memory
4535 destination operand, then we assume the source operand may
4536 sometimes be a memory operand and so we need to store the
4537 destination in the i.rm.reg field. */
40fb9820
L		 4538 if (!i.tm.operand_types[dest].bitfield.regmem
4539 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 4540 {
4541 i.rm.reg = i.op[dest].regs->reg_num;
4542 i.rm.regmem = i.op[source].regs->reg_num;
4543 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4544 i.rex |= REX_R;
29b0f896 4545 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4546 i.rex |= REX_B;
29b0f896
AM		 4547 }
4548 else
4549 {
4550 i.rm.reg = i.op[source].regs->reg_num;
4551 i.rm.regmem = i.op[dest].regs->reg_num;
4552 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4553 i.rex |= REX_B;
29b0f896 4554 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4555 i.rex |= REX_R;
29b0f896 4556 }
161a04f6 4557 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 4558 {
40fb9820
L		 4559 if (!i.types[0].bitfield.control
4560 && !i.types[1].bitfield.control)
c4a530c5 4561 abort ();
161a04f6 4562 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 4563 add_prefix (LOCK_PREFIX_OPCODE);
4564 }
29b0f896
AM		 4565 }
4566 else
4567 { /* If it's not 2 reg operands... */
4568 if (i.mem_operands)
4569 {
4570 unsigned int fake_zero_displacement = 0;
99018f42 4571 unsigned int op;
4eed87de 4572
85f10a01
MM		 4573 /* This has been precalculated for SSE5 instructions
4574 that have a DREX field earlier in process_drex. */
b5016f89
L		 4575 if (i.tm.opcode_modifier.drex
4576 || i.tm.opcode_modifier.drexv
4577 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4578 op = i.drex.modrm_regmem;
4579 else
4580 {
c0209578
L		 4581 for (op = 0; op < i.operands; op++)
4582 if (operand_type_check (i.types[op], anymem))
4583 break;
4584 assert (op < i.operands);
85f10a01 4585 }
29b0f896
AM		 4586
4587 default_seg = &ds;
4588
4589 if (i.base_reg == 0)
4590 {
4591 i.rm.mode = 0;
4592 if (!i.disp_operands)
4593 fake_zero_displacement = 1;
4594 if (i.index_reg == 0)
4595 {
4596 /* Operand is just <disp> */
20f0a1fc 4597 if (flag_code == CODE_64BIT)
29b0f896
AM		 4598 {
4599 /* 64bit mode overwrites the 32bit absolute
4600 addressing by RIP relative addressing and
4601 absolute addressing is encoded by one of the
4602 redundant SIB forms. */
4603 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4604 i.sib.base = NO_BASE_REGISTER;
4605 i.sib.index = NO_INDEX_REGISTER;
fc225355 4606 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 4607 ? disp32s : disp32);
20f0a1fc 4608 }
fc225355
L		 4609 else if ((flag_code == CODE_16BIT)
4610 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 4611 {
4612 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 4613 i.types[op] = disp16;
20f0a1fc
NC		 4614 }
4615 else
4616 {
4617 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 4618 i.types[op] = disp32;
29b0f896
AM		 4619 }
4620 }
4621 else /* !i.base_reg && i.index_reg */
4622 {
db51cc60
L		 4623 if (i.index_reg->reg_num == RegEiz
4624 || i.index_reg->reg_num == RegRiz)
4625 i.sib.index = NO_INDEX_REGISTER;
4626 else
4627 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4628 i.sib.base = NO_BASE_REGISTER;
4629 i.sib.scale = i.log2_scale_factor;
4630 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 4631 i.types[op].bitfield.disp8 = 0;
4632 i.types[op].bitfield.disp16 = 0;
4633 i.types[op].bitfield.disp64 = 0;
29b0f896 4634 if (flag_code != CODE_64BIT)
40fb9820
L		 4635 {
4636 /* Must be 32 bit */
4637 i.types[op].bitfield.disp32 = 1;
4638 i.types[op].bitfield.disp32s = 0;
4639 }
29b0f896 4640 else
40fb9820
L		 4641 {
4642 i.types[op].bitfield.disp32 = 0;
4643 i.types[op].bitfield.disp32s = 1;
4644 }
29b0f896 4645 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4646 i.rex |= REX_X;
29b0f896
AM		 4647 }
4648 }
4649 /* RIP addressing for 64bit mode. */
9a04903e
JB		 4650 else if (i.base_reg->reg_num == RegRip ||
4651 i.base_reg->reg_num == RegEip)
29b0f896
AM		 4652 {
4653 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 4654 i.types[op].bitfield.disp8 = 0;
4655 i.types[op].bitfield.disp16 = 0;
4656 i.types[op].bitfield.disp32 = 0;
4657 i.types[op].bitfield.disp32s = 1;
4658 i.types[op].bitfield.disp64 = 0;
71903a11 4659 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 4660 if (! i.disp_operands)
4661 fake_zero_displacement = 1;
29b0f896 4662 }
40fb9820 4663 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 4664 {
4665 switch (i.base_reg->reg_num)
4666 {
4667 case 3: /* (%bx) */
4668 if (i.index_reg == 0)
4669 i.rm.regmem = 7;
4670 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4671 i.rm.regmem = i.index_reg->reg_num - 6;
4672 break;
4673 case 5: /* (%bp) */
4674 default_seg = &ss;
4675 if (i.index_reg == 0)
4676 {
4677 i.rm.regmem = 6;
40fb9820 4678 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 4679 {
4680 /* fake (%bp) into 0(%bp) */
40fb9820 4681 i.types[op].bitfield.disp8 = 1;
252b5132 4682 fake_zero_displacement = 1;
29b0f896
AM		 4683 }
4684 }
4685 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4686 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4687 break;
4688 default: /* (%si) -> 4 or (%di) -> 5 */
4689 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4690 }
4691 i.rm.mode = mode_from_disp_size (i.types[op]);
4692 }
4693 else /* i.base_reg and 32/64 bit mode */
4694 {
4695 if (flag_code == CODE_64BIT
40fb9820
L		 4696 && operand_type_check (i.types[op], disp))
4697 {
4698 i386_operand_type temp;
c6fb90c8 4699 UINTS_CLEAR (temp);
40fb9820
L		 4700 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4701 i.types[op] = temp;
4702 if (i.prefix[ADDR_PREFIX] == 0)
4703 i.types[op].bitfield.disp32s = 1;
4704 else
4705 i.types[op].bitfield.disp32 = 1;
4706 }
20f0a1fc 4707
29b0f896
AM		 4708 i.rm.regmem = i.base_reg->reg_num;
4709 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 4710 i.rex |= REX_B;
29b0f896
AM		 4711 i.sib.base = i.base_reg->reg_num;
4712 /* x86-64 ignores REX prefix bit here to avoid decoder
4713 complications. */
4714 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4715 {
4716 default_seg = &ss;
4717 if (i.disp_operands == 0)
4718 {
4719 fake_zero_displacement = 1;
40fb9820 4720 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 4721 }
4722 }
4723 else if (i.base_reg->reg_num == ESP_REG_NUM)
4724 {
4725 default_seg = &ss;
4726 }
4727 i.sib.scale = i.log2_scale_factor;
4728 if (i.index_reg == 0)
4729 {
4730 /* <disp>(%esp) becomes two byte modrm with no index
4731 register. We've already stored the code for esp
4732 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4733 Any base register besides %esp will not use the
4734 extra modrm byte. */
4735 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 4736 }
4737 else
4738 {
db51cc60
L		 4739 if (i.index_reg->reg_num == RegEiz
4740 || i.index_reg->reg_num == RegRiz)
4741 i.sib.index = NO_INDEX_REGISTER;
4742 else
4743 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4744 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4745 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4746 i.rex |= REX_X;
29b0f896 4747 }
67a4f2b7
AO		 4748
4749 if (i.disp_operands
4750 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4751 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4752 i.rm.mode = 0;
4753 else
4754 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 4755 }
252b5132 4756
29b0f896
AM		 4757 if (fake_zero_displacement)
4758 {
4759 /* Fakes a zero displacement assuming that i.types[op]
4760 holds the correct displacement size. */
4761 expressionS *exp;
4762
4763 assert (i.op[op].disps == 0);
4764 exp = &disp_expressions[i.disp_operands++];
4765 i.op[op].disps = exp;
4766 exp->X_op = O_constant;
4767 exp->X_add_number = 0;
4768 exp->X_add_symbol = (symbolS *) 0;
4769 exp->X_op_symbol = (symbolS *) 0;
4770 }
4771 }
252b5132 4772
29b0f896
AM		 4773 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4774 (if any) based on i.tm.extension_opcode. Again, we must be
4775 careful to make sure that segment/control/debug/test/MMX
4776 registers are coded into the i.rm.reg field. */
4777 if (i.reg_operands)
4778 {
99018f42
L		 4779 unsigned int op;
4780
85f10a01
MM		 4781 /* This has been precalculated for SSE5 instructions
4782 that have a DREX field earlier in process_drex. */
b5016f89
L		 4783 if (i.tm.opcode_modifier.drex
4784 || i.tm.opcode_modifier.drexv
4785 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4786 {
4787 op = i.drex.modrm_reg;
4788 i.rm.reg = i.op[op].regs->reg_num;
4789 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4790 i.rex |= REX_R;
4791 }
4792 else
4793 {
c0209578
L		 4794 for (op = 0; op < i.operands; op++)
4795 if (i.types[op].bitfield.reg8
4796 || i.types[op].bitfield.reg16
4797 || i.types[op].bitfield.reg32
4798 || i.types[op].bitfield.reg64
4799 || i.types[op].bitfield.regmmx
4800 || i.types[op].bitfield.regxmm
4801 || i.types[op].bitfield.sreg2
4802 || i.types[op].bitfield.sreg3
4803 || i.types[op].bitfield.control
4804 || i.types[op].bitfield.debug
4805 || i.types[op].bitfield.test)
4806 break;
4807
4808 assert (op < i.operands);
99018f42 4809
85f10a01
MM		 4810 /* If there is an extension opcode to put here, the
4811 register number must be put into the regmem field. */
c0209578
L		 4812 if (i.tm.extension_opcode != None)
4813 {
4814 i.rm.regmem = i.op[op].regs->reg_num;
4815 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4816 i.rex |= REX_B;
4817 }
4818 else
4819 {
4820 i.rm.reg = i.op[op].regs->reg_num;
4821 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4822 i.rex |= REX_R;
4823 }
85f10a01 4824 }
252b5132 4825
29b0f896
AM		 4826 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4827 must set it to 3 to indicate this is a register operand
4828 in the regmem field. */
4829 if (!i.mem_operands)
4830 i.rm.mode = 3;
4831 }
252b5132 4832
29b0f896 4833 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 4834 if (i.tm.extension_opcode != None
4835 && !(i.tm.opcode_modifier.drex
4836 || i.tm.opcode_modifier.drexv
4837 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 4838 i.rm.reg = i.tm.extension_opcode;
4839 }
4840 return default_seg;
4841}
252b5132 4842
29b0f896 4843static void
e3bb37b5 4844output_branch (void)
29b0f896
AM		 4845{
4846 char *p;
4847 int code16;
4848 int prefix;
4849 relax_substateT subtype;
4850 symbolS *sym;
4851 offsetT off;
4852
4853 code16 = 0;
4854 if (flag_code == CODE_16BIT)
4855 code16 = CODE16;
4856
4857 prefix = 0;
4858 if (i.prefix[DATA_PREFIX] != 0)
252b5132 4859 {
29b0f896
AM		 4860 prefix = 1;
4861 i.prefixes -= 1;
4862 code16 ^= CODE16;
252b5132 4863 }
29b0f896
AM		 4864 /* Pentium4 branch hints. */
4865 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4866 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 4867 {
29b0f896
AM		 4868 prefix++;
4869 i.prefixes--;
4870 }
4871 if (i.prefix[REX_PREFIX] != 0)
4872 {
4873 prefix++;
4874 i.prefixes--;
2f66722d
AM		 4875 }
4876
29b0f896
AM		 4877 if (i.prefixes != 0 && !intel_syntax)
4878 as_warn (_("skipping prefixes on this instruction"));
4879
4880 /* It's always a symbol; End frag & setup for relax.
4881 Make sure there is enough room in this frag for the largest
4882 instruction we may generate in md_convert_frag. This is 2
4883 bytes for the opcode and room for the prefix and largest
4884 displacement. */
4885 frag_grow (prefix + 2 + 4);
4886 /* Prefix and 1 opcode byte go in fr_fix. */
4887 p = frag_more (prefix + 1);
4888 if (i.prefix[DATA_PREFIX] != 0)
4889 *p++ = DATA_PREFIX_OPCODE;
4890 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
4891 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
4892 *p++ = i.prefix[SEG_PREFIX];
4893 if (i.prefix[REX_PREFIX] != 0)
4894 *p++ = i.prefix[REX_PREFIX];
4895 *p = i.tm.base_opcode;
4896
4897 if ((unsigned char) *p == JUMP_PC_RELATIVE)
4898 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 4899 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 4900 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
4901 else
4902 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
4903 subtype |= code16;
3e73aa7c 4904
29b0f896
AM		 4905 sym = i.op[0].disps->X_add_symbol;
4906 off = i.op[0].disps->X_add_number;
3e73aa7c 4907
29b0f896
AM		 4908 if (i.op[0].disps->X_op != O_constant
4909 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 4910 {
29b0f896
AM		 4911 /* Handle complex expressions. */
4912 sym = make_expr_symbol (i.op[0].disps);
4913 off = 0;
4914 }
3e73aa7c 4915
29b0f896
AM		 4916 /* 1 possible extra opcode + 4 byte displacement go in var part.
4917 Pass reloc in fr_var. */
4918 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
4919}
3e73aa7c 4920
29b0f896 4921static void
e3bb37b5 4922output_jump (void)
29b0f896
AM		 4923{
4924 char *p;
4925 int size;
3e02c1cc 4926 fixS *fixP;
29b0f896 4927
40fb9820 4928 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 4929 {
4930 /* This is a loop or jecxz type instruction. */
4931 size = 1;
4932 if (i.prefix[ADDR_PREFIX] != 0)
4933 {
4934 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
4935 i.prefixes -= 1;
4936 }
4937 /* Pentium4 branch hints. */
4938 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4939 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4940 {
4941 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
4942 i.prefixes--;
3e73aa7c
JH		 4943 }
4944 }
29b0f896
AM		 4945 else
4946 {
4947 int code16;
3e73aa7c 4948
29b0f896
AM		 4949 code16 = 0;
4950 if (flag_code == CODE_16BIT)
4951 code16 = CODE16;
3e73aa7c 4952
29b0f896
AM		 4953 if (i.prefix[DATA_PREFIX] != 0)
4954 {
4955 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
4956 i.prefixes -= 1;
4957 code16 ^= CODE16;
4958 }
252b5132 4959
29b0f896
AM		 4960 size = 4;
4961 if (code16)
4962 size = 2;
4963 }
9fcc94b6 4964
29b0f896
AM		 4965 if (i.prefix[REX_PREFIX] != 0)
4966 {
4967 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
4968 i.prefixes -= 1;
4969 }
252b5132 4970
29b0f896
AM		 4971 if (i.prefixes != 0 && !intel_syntax)
4972 as_warn (_("skipping prefixes on this instruction"));
e0890092 4973
29b0f896
AM		 4974 p = frag_more (1 + size);
4975 *p++ = i.tm.base_opcode;
e0890092 4976
3e02c1cc
AM		 4977 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4978 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
4979
4980 /* All jumps handled here are signed, but don't use a signed limit
4981 check for 32 and 16 bit jumps as we want to allow wrap around at
4982 4G and 64k respectively. */
4983 if (size == 1)
4984 fixP->fx_signed = 1;
29b0f896 4985}
e0890092 4986
29b0f896 4987static void
e3bb37b5 4988output_interseg_jump (void)
29b0f896
AM		 4989{
4990 char *p;
4991 int size;
4992 int prefix;
4993 int code16;
252b5132 4994
29b0f896
AM		 4995 code16 = 0;
4996 if (flag_code == CODE_16BIT)
4997 code16 = CODE16;
a217f122 4998
29b0f896
AM		 4999 prefix = 0;
5000 if (i.prefix[DATA_PREFIX] != 0)
5001 {
5002 prefix = 1;
5003 i.prefixes -= 1;
5004 code16 ^= CODE16;
5005 }
5006 if (i.prefix[REX_PREFIX] != 0)
5007 {
5008 prefix++;
5009 i.prefixes -= 1;
5010 }
252b5132 5011
29b0f896
AM		 5012 size = 4;
5013 if (code16)
5014 size = 2;
252b5132 5015
29b0f896
AM		 5016 if (i.prefixes != 0 && !intel_syntax)
5017 as_warn (_("skipping prefixes on this instruction"));
252b5132 5018
29b0f896
AM		 5019 /* 1 opcode; 2 segment; offset */
5020 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5021
29b0f896
AM		 5022 if (i.prefix[DATA_PREFIX] != 0)
5023 *p++ = DATA_PREFIX_OPCODE;
252b5132 5024
29b0f896
AM		 5025 if (i.prefix[REX_PREFIX] != 0)
5026 *p++ = i.prefix[REX_PREFIX];
252b5132 5027
29b0f896
AM		 5028 *p++ = i.tm.base_opcode;
5029 if (i.op[1].imms->X_op == O_constant)
5030 {
5031 offsetT n = i.op[1].imms->X_add_number;
252b5132 5032
29b0f896
AM		 5033 if (size == 2
5034 && !fits_in_unsigned_word (n)
5035 && !fits_in_signed_word (n))
5036 {
5037 as_bad (_("16-bit jump out of range"));
5038 return;
5039 }
5040 md_number_to_chars (p, n, size);
5041 }
5042 else
5043 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5044 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5045 if (i.op[0].imms->X_op != O_constant)
5046 as_bad (_("can't handle non absolute segment in `%s'"),
5047 i.tm.name);
5048 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5049}
a217f122 5050
29b0f896 5051static void
e3bb37b5 5052output_insn (void)
29b0f896 5053{
2bbd9c25
JJ		 5054 fragS *insn_start_frag;
5055 offsetT insn_start_off;
5056
29b0f896
AM		 5057 /* Tie dwarf2 debug info to the address at the start of the insn.
5058 We can't do this after the insn has been output as the current
5059 frag may have been closed off. eg. by frag_var. */
5060 dwarf2_emit_insn (0);
5061
2bbd9c25
JJ		 5062 insn_start_frag = frag_now;
5063 insn_start_off = frag_now_fix ();
5064
29b0f896 5065 /* Output jumps. */
40fb9820 5066 if (i.tm.opcode_modifier.jump)
29b0f896 5067 output_branch ();
40fb9820
L		 5068 else if (i.tm.opcode_modifier.jumpbyte
5069 || i.tm.opcode_modifier.jumpdword)
29b0f896 5070 output_jump ();
40fb9820 5071 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5072 output_interseg_jump ();
5073 else
5074 {
5075 /* Output normal instructions here. */
5076 char *p;
5077 unsigned char *q;
47465058 5078 unsigned int j;
331d2d0d 5079 unsigned int prefix;
4dffcebc
L		 5080
5081 switch (i.tm.opcode_length)
bc4bd9ab 5082 {
4dffcebc 5083 case 3:
331d2d0d
L		 5084 if (i.tm.base_opcode & 0xff000000)
5085 {
5086 prefix = (i.tm.base_opcode >> 24) & 0xff;
5087 goto check_prefix;
5088 }
4dffcebc
L		 5089 break;
5090 case 2:
5091 if ((i.tm.base_opcode & 0xff0000) != 0)
bc4bd9ab 5092 {
4dffcebc
L		 5093 prefix = (i.tm.base_opcode >> 16) & 0xff;
5094 if (i.tm.cpu_flags.bitfield.cpupadlock)
5095 {
5096check_prefix:
5097 if (prefix != REPE_PREFIX_OPCODE
5098 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5099 add_prefix (prefix);
5100 }
5101 else
bc4bd9ab
MK		 5102 add_prefix (prefix);
5103 }
4dffcebc
L		 5104 break;
5105 case 1:
5106 break;
5107 default:
5108 abort ();
0f10071e 5109 }
252b5132 5110
29b0f896 5111 /* The prefix bytes. */
47465058
L		 5112 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5113 if (*q)
5114 FRAG_APPEND_1_CHAR (*q);
252b5132 5115
29b0f896 5116 /* Now the opcode; be careful about word order here! */
4dffcebc 5117 if (i.tm.opcode_length == 1)
29b0f896
AM		 5118 {
5119 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5120 }
5121 else
5122 {
4dffcebc 5123 switch (i.tm.opcode_length)
331d2d0d 5124 {
4dffcebc 5125 case 3:
331d2d0d
L		 5126 p = frag_more (3);
5127 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5128 break;
5129 case 2:
5130 p = frag_more (2);
5131 break;
5132 default:
5133 abort ();
5134 break;
331d2d0d 5135 }
0f10071e 5136
29b0f896
AM		 5137 /* Put out high byte first: can't use md_number_to_chars! */
5138 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5139 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5140
5141 /* On SSE5, encode the OC1 bit in the DREX field if this
5142 encoding has multiple formats. */
5143 if (i.tm.opcode_modifier.drex
5144 && i.tm.opcode_modifier.drexv
5145 && DREX_OC1 (i.tm.extension_opcode))
5146 *p |= DREX_OC1_MASK;
29b0f896 5147 }
3e73aa7c 5148
29b0f896 5149 /* Now the modrm byte and sib byte (if present). */
40fb9820 5150 if (i.tm.opcode_modifier.modrm)
29b0f896 5151 {
4a3523fa
L		 5152 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5153 | i.rm.reg << 3
5154 | i.rm.mode << 6));
29b0f896
AM		 5155 /* If i.rm.regmem == ESP (4)
5156 && i.rm.mode != (Register mode)
5157 && not 16 bit
5158 ==> need second modrm byte. */
5159 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5160 && i.rm.mode != 3
40fb9820 5161 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5162 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5163 | i.sib.index << 3
5164 | i.sib.scale << 6));
29b0f896 5165 }
3e73aa7c 5166
85f10a01
MM		 5167 /* Write the DREX byte if needed. */
5168 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5169 {
5170 p = frag_more (1);
5171 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5172
5173 /* Encode the OC0 bit if this encoding has multiple
5174 formats. */
5175 if ((i.tm.opcode_modifier.drex
5176 || i.tm.opcode_modifier.drexv)
5177 && DREX_OC0 (i.tm.extension_opcode))
5178 *p |= DREX_OC0_MASK;
5179 }
5180
29b0f896 5181 if (i.disp_operands)
2bbd9c25 5182 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5183
29b0f896 5184 if (i.imm_operands)
2bbd9c25 5185 output_imm (insn_start_frag, insn_start_off);
29b0f896 5186 }
252b5132 5187
29b0f896
AM		 5188#ifdef DEBUG386
5189 if (flag_debug)
5190 {
7b81dfbb 5191 pi ("" /*line*/, &i);
29b0f896
AM		 5192 }
5193#endif /* DEBUG386 */
5194}
252b5132 5195
e205caa7
L		 5196/* Return the size of the displacement operand N. */
5197
5198static int
5199disp_size (unsigned int n)
5200{
5201 int size = 4;
40fb9820
L		 5202 if (i.types[n].bitfield.disp64)
5203 size = 8;
5204 else if (i.types[n].bitfield.disp8)
5205 size = 1;
5206 else if (i.types[n].bitfield.disp16)
5207 size = 2;
e205caa7
L		 5208 return size;
5209}
5210
5211/* Return the size of the immediate operand N. */
5212
5213static int
5214imm_size (unsigned int n)
5215{
5216 int size = 4;
40fb9820
L		 5217 if (i.types[n].bitfield.imm64)
5218 size = 8;
5219 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5220 size = 1;
5221 else if (i.types[n].bitfield.imm16)
5222 size = 2;
e205caa7
L		 5223 return size;
5224}
5225
29b0f896 5226static void
64e74474 5227output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5228{
5229 char *p;
5230 unsigned int n;
252b5132 5231
29b0f896
AM		 5232 for (n = 0; n < i.operands; n++)
5233 {
40fb9820 5234 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5235 {
5236 if (i.op[n].disps->X_op == O_constant)
5237 {
e205caa7 5238 int size = disp_size (n);
29b0f896 5239 offsetT val;
252b5132 5240
29b0f896
AM		 5241 val = offset_in_range (i.op[n].disps->X_add_number,
5242 size);
5243 p = frag_more (size);
5244 md_number_to_chars (p, val, size);
5245 }
5246 else
5247 {
f86103b7 5248 enum bfd_reloc_code_real reloc_type;
e205caa7 5249 int size = disp_size (n);
40fb9820 5250 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5251 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5252
e205caa7 5253 /* We can't have 8 bit displacement here. */
40fb9820 5254 assert (!i.types[n].bitfield.disp8);
e205caa7 5255
29b0f896
AM		 5256 /* The PC relative address is computed relative
5257 to the instruction boundary, so in case immediate
5258 fields follows, we need to adjust the value. */
5259 if (pcrel && i.imm_operands)
5260 {
29b0f896 5261 unsigned int n1;
e205caa7 5262 int sz = 0;
252b5132 5263
29b0f896 5264 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5265 if (operand_type_check (i.types[n1], imm))
252b5132 5266 {
e205caa7
L		 5267 /* Only one immediate is allowed for PC
5268 relative address. */
5269 assert (sz == 0);
5270 sz = imm_size (n1);
5271 i.op[n].disps->X_add_number -= sz;
252b5132 5272 }
29b0f896 5273 /* We should find the immediate. */
e205caa7 5274 assert (sz != 0);
29b0f896 5275 }
520dc8e8 5276
29b0f896 5277 p = frag_more (size);
2bbd9c25 5278 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5279 if (GOT_symbol
2bbd9c25 5280 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5281 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5282 || reloc_type == BFD_RELOC_X86_64_32S
5283 || (reloc_type == BFD_RELOC_64
5284 && object_64bit))
d6ab8113
JB		 5285 && (i.op[n].disps->X_op == O_symbol
5286 || (i.op[n].disps->X_op == O_add
5287 && ((symbol_get_value_expression
5288 (i.op[n].disps->X_op_symbol)->X_op)
5289 == O_subtract))))
5290 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5291 {
5292 offsetT add;
5293
5294 if (insn_start_frag == frag_now)
5295 add = (p - frag_now->fr_literal) - insn_start_off;
5296 else
5297 {
5298 fragS *fr;
5299
5300 add = insn_start_frag->fr_fix - insn_start_off;
5301 for (fr = insn_start_frag->fr_next;
5302 fr && fr != frag_now; fr = fr->fr_next)
5303 add += fr->fr_fix;
5304 add += p - frag_now->fr_literal;
5305 }
5306
4fa24527 5307 if (!object_64bit)
7b81dfbb
AJ		 5308 {
5309 reloc_type = BFD_RELOC_386_GOTPC;
5310 i.op[n].imms->X_add_number += add;
5311 }
5312 else if (reloc_type == BFD_RELOC_64)
5313 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5314 else
7b81dfbb
AJ		 5315 /* Don't do the adjustment for x86-64, as there
5316 the pcrel addressing is relative to the _next_
5317 insn, and that is taken care of in other code. */
d6ab8113 5318 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5319 }
062cd5e7 5320 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5321 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5322 }
5323 }
5324 }
5325}
252b5132 5326
29b0f896 5327static void
64e74474 5328output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5329{
5330 char *p;
5331 unsigned int n;
252b5132 5332
29b0f896
AM		 5333 for (n = 0; n < i.operands; n++)
5334 {
40fb9820 5335 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5336 {
5337 if (i.op[n].imms->X_op == O_constant)
5338 {
e205caa7 5339 int size = imm_size (n);
29b0f896 5340 offsetT val;
b4cac588 5341
29b0f896
AM		 5342 val = offset_in_range (i.op[n].imms->X_add_number,
5343 size);
5344 p = frag_more (size);
5345 md_number_to_chars (p, val, size);
5346 }
5347 else
5348 {
5349 /* Not absolute_section.
5350 Need a 32-bit fixup (don't support 8bit
5351 non-absolute imms). Try to support other
5352 sizes ... */
f86103b7 5353 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5354 int size = imm_size (n);
5355 int sign;
29b0f896 5356
40fb9820 5357 if (i.types[n].bitfield.imm32s
a7d61044 5358 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5359 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5360 sign = 1;
e205caa7
L		 5361 else
5362 sign = 0;
520dc8e8 5363
29b0f896
AM		 5364 p = frag_more (size);
5365 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5366
2bbd9c25
JJ		 5367 /* This is tough to explain. We end up with this one if we
5368 * have operands that look like
5369 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5370 * obtain the absolute address of the GOT, and it is strongly
5371 * preferable from a performance point of view to avoid using
5372 * a runtime relocation for this. The actual sequence of
5373 * instructions often look something like:
5374 *
5375 * call .L66
5376 * .L66:
5377 * popl %ebx
5378 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5379 *
5380 * The call and pop essentially return the absolute address
5381 * of the label .L66 and store it in %ebx. The linker itself
5382 * will ultimately change the first operand of the addl so
5383 * that %ebx points to the GOT, but to keep things simple, the
5384 * .o file must have this operand set so that it generates not
5385 * the absolute address of .L66, but the absolute address of
5386 * itself. This allows the linker itself simply treat a GOTPC
5387 * relocation as asking for a pcrel offset to the GOT to be
5388 * added in, and the addend of the relocation is stored in the
5389 * operand field for the instruction itself.
5390 *
5391 * Our job here is to fix the operand so that it would add
5392 * the correct offset so that %ebx would point to itself. The
5393 * thing that is tricky is that .-.L66 will point to the
5394 * beginning of the instruction, so we need to further modify
5395 * the operand so that it will point to itself. There are
5396 * other cases where you have something like:
5397 *
5398 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5399 *
5400 * and here no correction would be required. Internally in
5401 * the assembler we treat operands of this form as not being
5402 * pcrel since the '.' is explicitly mentioned, and I wonder
5403 * whether it would simplify matters to do it this way. Who
5404 * knows. In earlier versions of the PIC patches, the
5405 * pcrel_adjust field was used to store the correction, but
5406 * since the expression is not pcrel, I felt it would be
5407 * confusing to do it this way. */
5408
d6ab8113 5409 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5410 || reloc_type == BFD_RELOC_X86_64_32S
5411 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 5412 && GOT_symbol
5413 && GOT_symbol == i.op[n].imms->X_add_symbol
5414 && (i.op[n].imms->X_op == O_symbol
5415 || (i.op[n].imms->X_op == O_add
5416 && ((symbol_get_value_expression
5417 (i.op[n].imms->X_op_symbol)->X_op)
5418 == O_subtract))))
5419 {
2bbd9c25
JJ		 5420 offsetT add;
5421
5422 if (insn_start_frag == frag_now)
5423 add = (p - frag_now->fr_literal) - insn_start_off;
5424 else
5425 {
5426 fragS *fr;
5427
5428 add = insn_start_frag->fr_fix - insn_start_off;
5429 for (fr = insn_start_frag->fr_next;
5430 fr && fr != frag_now; fr = fr->fr_next)
5431 add += fr->fr_fix;
5432 add += p - frag_now->fr_literal;
5433 }
5434
4fa24527 5435 if (!object_64bit)
d6ab8113 5436 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 5437 else if (size == 4)
d6ab8113 5438 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 5439 else if (size == 8)
5440 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 5441 i.op[n].imms->X_add_number += add;
29b0f896 5442 }
29b0f896
AM		 5443 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5444 i.op[n].imms, 0, reloc_type);
5445 }
5446 }
5447 }
252b5132
RH		 5448}
5449\f
d182319b
JB		 5450/* x86_cons_fix_new is called via the expression parsing code when a
5451 reloc is needed. We use this hook to get the correct .got reloc. */
5452static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5453static int cons_sign = -1;
5454
5455void
e3bb37b5 5456x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 5457 expressionS *exp)
d182319b
JB		 5458{
5459 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5460
5461 got_reloc = NO_RELOC;
5462
5463#ifdef TE_PE
5464 if (exp->X_op == O_secrel)
5465 {
5466 exp->X_op = O_symbol;
5467 r = BFD_RELOC_32_SECREL;
5468 }
5469#endif
5470
5471 fix_new_exp (frag, off, len, exp, 0, r);
5472}
5473
718ddfc0
JB		 5474#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5475# define lex_got(reloc, adjust, types) NULL
5476#else
f3c180ae
AM		 5477/* Parse operands of the form
5478 <symbol>@GOTOFF+<nnn>
5479 and similar .plt or .got references.
5480
5481 If we find one, set up the correct relocation in RELOC and copy the
5482 input string, minus the `@GOTOFF' into a malloc'd buffer for
5483 parsing by the calling routine. Return this buffer, and if ADJUST
5484 is non-null set it to the length of the string we removed from the
5485 input line. Otherwise return NULL. */
5486static char *
3956db08 5487lex_got (enum bfd_reloc_code_real *reloc,
64e74474 5488 int *adjust,
40fb9820 5489 i386_operand_type *types)
f3c180ae 5490{
7b81dfbb
AJ		 5491 /* Some of the relocations depend on the size of what field is to
5492 be relocated. But in our callers i386_immediate and i386_displacement
5493 we don't yet know the operand size (this will be set by insn
5494 matching). Hence we record the word32 relocation here,
5495 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 5496 static const struct {
5497 const char *str;
4fa24527 5498 const enum bfd_reloc_code_real rel[2];
40fb9820 5499 const i386_operand_type types64;
f3c180ae 5500 } gotrel[] = {
4eed87de
AM		 5501 { "PLTOFF", { 0,
5502 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 5503 OPERAND_TYPE_IMM64 },
4eed87de
AM		 5504 { "PLT", { BFD_RELOC_386_PLT32,
5505 BFD_RELOC_X86_64_PLT32 },
40fb9820 5506 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5507 { "GOTPLT", { 0,
5508 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 5509 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5510 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5511 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 5512 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5513 { "GOTPCREL", { 0,
5514 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 5515 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5516 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5517 BFD_RELOC_X86_64_TLSGD },
40fb9820 5518 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5519 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5520 0 },
40fb9820 5521 OPERAND_TYPE_NONE },
4eed87de
AM		 5522 { "TLSLD", { 0,
5523 BFD_RELOC_X86_64_TLSLD },
40fb9820 5524 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5525 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5526 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 5527 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5528 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5529 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 5530 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5531 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5532 0 },
40fb9820 5533 OPERAND_TYPE_NONE },
4eed87de
AM		 5534 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5535 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 5536
5537 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5538 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5539 0 },
40fb9820 5540 OPERAND_TYPE_NONE },
4eed87de
AM		 5541 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5542 0 },
40fb9820 5543 OPERAND_TYPE_NONE },
4eed87de
AM		 5544 { "GOT", { BFD_RELOC_386_GOT32,
5545 BFD_RELOC_X86_64_GOT32 },
40fb9820 5546 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 5547 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5548 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 5549 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5550 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5551 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 5552 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 5553 };
5554 char *cp;
5555 unsigned int j;
5556
718ddfc0
JB		 5557 if (!IS_ELF)
5558 return NULL;
5559
f3c180ae 5560 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 5561 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 5562 return NULL;
5563
47465058 5564 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 5565 {
5566 int len;
5567
5568 len = strlen (gotrel[j].str);
28f81592 5569 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 5570 {
4fa24527 5571 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 5572 {
28f81592
AM		 5573 int first, second;
5574 char *tmpbuf, *past_reloc;
f3c180ae 5575
4fa24527 5576 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 5577 if (adjust)
5578 *adjust = len;
f3c180ae 5579
3956db08
JB		 5580 if (types)
5581 {
5582 if (flag_code != CODE_64BIT)
40fb9820
L		 5583 {
5584 types->bitfield.imm32 = 1;
5585 types->bitfield.disp32 = 1;
5586 }
3956db08
JB		 5587 else
5588 *types = gotrel[j].types64;
5589 }
5590
f3c180ae
AM		 5591 if (GOT_symbol == NULL)
5592 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5593
28f81592 5594 /* The length of the first part of our input line. */
f3c180ae 5595 first = cp - input_line_pointer;
28f81592
AM		 5596
5597 /* The second part goes from after the reloc token until
67c11a9b 5598 (and including) an end_of_line char or comma. */
28f81592 5599 past_reloc = cp + 1 + len;
67c11a9b
AM		 5600 cp = past_reloc;
5601 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5602 ++cp;
5603 second = cp + 1 - past_reloc;
28f81592
AM		 5604
5605 /* Allocate and copy string. The trailing NUL shouldn't
5606 be necessary, but be safe. */
5607 tmpbuf = xmalloc (first + second + 2);
f3c180ae 5608 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 5609 if (second != 0 && *past_reloc != ' ')
5610 /* Replace the relocation token with ' ', so that
5611 errors like foo@GOTOFF1 will be detected. */
5612 tmpbuf[first++] = ' ';
5613 memcpy (tmpbuf + first, past_reloc, second);
5614 tmpbuf[first + second] = '\0';
f3c180ae
AM		 5615 return tmpbuf;
5616 }
5617
4fa24527
JB		 5618 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5619 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 5620 return NULL;
5621 }
5622 }
5623
5624 /* Might be a symbol version string. Don't as_bad here. */
5625 return NULL;
5626}
5627
f3c180ae 5628void
e3bb37b5 5629x86_cons (expressionS *exp, int size)
f3c180ae 5630{
4fa24527 5631 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 5632 {
5633 /* Handle @GOTOFF and the like in an expression. */
5634 char *save;
5635 char *gotfree_input_line;
5636 int adjust;
5637
5638 save = input_line_pointer;
3956db08 5639 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 5640 if (gotfree_input_line)
5641 input_line_pointer = gotfree_input_line;
5642
5643 expression (exp);
5644
5645 if (gotfree_input_line)
5646 {
5647 /* expression () has merrily parsed up to the end of line,
5648 or a comma - in the wrong buffer. Transfer how far
5649 input_line_pointer has moved to the right buffer. */
5650 input_line_pointer = (save
5651 + (input_line_pointer - gotfree_input_line)
5652 + adjust);
5653 free (gotfree_input_line);
3992d3b7
AM		 5654 if (exp->X_op == O_constant
5655 || exp->X_op == O_absent
5656 || exp->X_op == O_illegal
5657 || exp->X_op == O_register
5658 || exp->X_op == O_big)
5659 {
5660 char c = *input_line_pointer;
5661 *input_line_pointer = 0;
5662 as_bad (_("missing or invalid expression `%s'"), save);
5663 *input_line_pointer = c;
5664 }
f3c180ae
AM		 5665 }
5666 }
5667 else
5668 expression (exp);
5669}
5670#endif
5671
d182319b 5672static void signed_cons (int size)
6482c264 5673{
d182319b
JB		 5674 if (flag_code == CODE_64BIT)
5675 cons_sign = 1;
5676 cons (size);
5677 cons_sign = -1;
6482c264
NC		 5678}
5679
d182319b 5680#ifdef TE_PE
6482c264
NC		 5681static void
5682pe_directive_secrel (dummy)
5683 int dummy ATTRIBUTE_UNUSED;
5684{
5685 expressionS exp;
5686
5687 do
5688 {
5689 expression (&exp);
5690 if (exp.X_op == O_symbol)
5691 exp.X_op = O_secrel;
5692
5693 emit_expr (&exp, 4);
5694 }
5695 while (*input_line_pointer++ == ',');
5696
5697 input_line_pointer--;
5698 demand_empty_rest_of_line ();
5699}
6482c264
NC		 5700#endif
5701
252b5132 5702static int
70e41ade 5703i386_immediate (char *imm_start)
252b5132
RH		 5704{
5705 char *save_input_line_pointer;
f3c180ae 5706 char *gotfree_input_line;
252b5132 5707 segT exp_seg = 0;
47926f60 5708 expressionS *exp;
40fb9820
L		 5709 i386_operand_type types;
5710
c6fb90c8 5711 UINTS_SET (types, ~0);
252b5132
RH		 5712
5713 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5714 {
31b2323c
L		 5715 as_bad (_("at most %d immediate operands are allowed"),
5716 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 5717 return 0;
5718 }
5719
5720 exp = &im_expressions[i.imm_operands++];
520dc8e8 5721 i.op[this_operand].imms = exp;
252b5132
RH		 5722
5723 if (is_space_char (*imm_start))
5724 ++imm_start;
5725
5726 save_input_line_pointer = input_line_pointer;
5727 input_line_pointer = imm_start;
5728
3956db08 5729 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5730 if (gotfree_input_line)
5731 input_line_pointer = gotfree_input_line;
252b5132
RH		 5732
5733 exp_seg = expression (exp);
5734
83183c0c 5735 SKIP_WHITESPACE ();
252b5132 5736 if (*input_line_pointer)
f3c180ae 5737 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 5738
5739 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 5740 if (gotfree_input_line)
5741 free (gotfree_input_line);
252b5132 5742
3992d3b7
AM		 5743 if (exp->X_op == O_absent
5744 || exp->X_op == O_illegal
5745 || exp->X_op == O_big
5746 || (gotfree_input_line
5747 && (exp->X_op == O_constant
5748 || exp->X_op == O_register)))
252b5132 5749 {
3992d3b7 5750 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 5751 imm_start);
3992d3b7 5752 return 0;
252b5132 5753 }
3e73aa7c 5754 else if (exp->X_op == O_constant)
252b5132 5755 {
47926f60 5756 /* Size it properly later. */
40fb9820 5757 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 5758 /* If BFD64, sign extend val. */
4eed87de
AM		 5759 if (!use_rela_relocations
5760 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5761 exp->X_add_number
5762 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 5763 }
4c63da97 5764#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 5765 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 5766 && exp_seg != absolute_section
47926f60 5767 && exp_seg != text_section
24eab124
AM		 5768 && exp_seg != data_section
5769 && exp_seg != bss_section
5770 && exp_seg != undefined_section
f86103b7 5771 && !bfd_is_com_section (exp_seg))
252b5132 5772 {
d0b47220 5773 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 5774 return 0;
5775 }
5776#endif
bb8f5920
L		 5777 else if (!intel_syntax && exp->X_op == O_register)
5778 {
5779 as_bad (_("illegal immediate register operand %s"), imm_start);
5780 return 0;
5781 }
252b5132
RH		 5782 else
5783 {
5784 /* This is an address. The size of the address will be
24eab124 5785 determined later, depending on destination register,
3e73aa7c 5786 suffix, or the default for the section. */
40fb9820
L		 5787 i.types[this_operand].bitfield.imm8 = 1;
5788 i.types[this_operand].bitfield.imm16 = 1;
5789 i.types[this_operand].bitfield.imm32 = 1;
5790 i.types[this_operand].bitfield.imm32s = 1;
5791 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 5792 i.types[this_operand] = operand_type_and (i.types[this_operand],
5793 types);
252b5132
RH		 5794 }
5795
5796 return 1;
5797}
5798
551c1ca1 5799static char *
e3bb37b5 5800i386_scale (char *scale)
252b5132 5801{
551c1ca1
AM		 5802 offsetT val;
5803 char *save = input_line_pointer;
252b5132 5804
551c1ca1
AM		 5805 input_line_pointer = scale;
5806 val = get_absolute_expression ();
5807
5808 switch (val)
252b5132 5809 {
551c1ca1 5810 case 1:
252b5132
RH		 5811 i.log2_scale_factor = 0;
5812 break;
551c1ca1 5813 case 2:
252b5132
RH		 5814 i.log2_scale_factor = 1;
5815 break;
551c1ca1 5816 case 4:
252b5132
RH		 5817 i.log2_scale_factor = 2;
5818 break;
551c1ca1 5819 case 8:
252b5132
RH		 5820 i.log2_scale_factor = 3;
5821 break;
5822 default:
a724f0f4
JB		 5823 {
5824 char sep = *input_line_pointer;
5825
5826 *input_line_pointer = '\0';
5827 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5828 scale);
5829 *input_line_pointer = sep;
5830 input_line_pointer = save;
5831 return NULL;
5832 }
252b5132 5833 }
29b0f896 5834 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 5835 {
5836 as_warn (_("scale factor of %d without an index register"),
24eab124 5837 1 << i.log2_scale_factor);
252b5132 5838 i.log2_scale_factor = 0;
252b5132 5839 }
551c1ca1
AM		 5840 scale = input_line_pointer;
5841 input_line_pointer = save;
5842 return scale;
252b5132
RH		 5843}
5844
252b5132 5845static int
e3bb37b5 5846i386_displacement (char *disp_start, char *disp_end)
252b5132 5847{
29b0f896 5848 expressionS *exp;
252b5132
RH		 5849 segT exp_seg = 0;
5850 char *save_input_line_pointer;
f3c180ae 5851 char *gotfree_input_line;
40fb9820
L		 5852 int override;
5853 i386_operand_type bigdisp, types = anydisp;
3992d3b7 5854 int ret;
252b5132 5855
31b2323c
L		 5856 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5857 {
5858 as_bad (_("at most %d displacement operands are allowed"),
5859 MAX_MEMORY_OPERANDS);
5860 return 0;
5861 }
5862
c6fb90c8 5863 UINTS_CLEAR (bigdisp);
40fb9820
L		 5864 if ((i.types[this_operand].bitfield.jumpabsolute)
5865 || (!current_templates->start->opcode_modifier.jump
5866 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 5867 {
40fb9820 5868 bigdisp.bitfield.disp32 = 1;
e05278af 5869 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 5870 if (flag_code == CODE_64BIT)
5871 {
5872 if (!override)
5873 {
5874 bigdisp.bitfield.disp32s = 1;
5875 bigdisp.bitfield.disp64 = 1;
5876 }
5877 }
5878 else if ((flag_code == CODE_16BIT) ^ override)
5879 {
5880 bigdisp.bitfield.disp32 = 0;
5881 bigdisp.bitfield.disp16 = 1;
5882 }
e05278af
JB		 5883 }
5884 else
5885 {
5886 /* For PC-relative branches, the width of the displacement
5887 is dependent upon data size, not address size. */
e05278af 5888 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 5889 if (flag_code == CODE_64BIT)
5890 {
5891 if (override || i.suffix == WORD_MNEM_SUFFIX)
5892 bigdisp.bitfield.disp16 = 1;
5893 else
5894 {
5895 bigdisp.bitfield.disp32 = 1;
5896 bigdisp.bitfield.disp32s = 1;
5897 }
5898 }
5899 else
e05278af
JB		 5900 {
5901 if (!override)
5902 override = (i.suffix == (flag_code != CODE_16BIT
5903 ? WORD_MNEM_SUFFIX
5904 : LONG_MNEM_SUFFIX));
40fb9820
L		 5905 bigdisp.bitfield.disp32 = 1;
5906 if ((flag_code == CODE_16BIT) ^ override)
5907 {
5908 bigdisp.bitfield.disp32 = 0;
5909 bigdisp.bitfield.disp16 = 1;
5910 }
e05278af 5911 }
e05278af 5912 }
c6fb90c8
L		 5913 i.types[this_operand] = operand_type_or (i.types[this_operand],
5914 bigdisp);
252b5132
RH		 5915
5916 exp = &disp_expressions[i.disp_operands];
520dc8e8 5917 i.op[this_operand].disps = exp;
252b5132
RH		 5918 i.disp_operands++;
5919 save_input_line_pointer = input_line_pointer;
5920 input_line_pointer = disp_start;
5921 END_STRING_AND_SAVE (disp_end);
5922
5923#ifndef GCC_ASM_O_HACK
5924#define GCC_ASM_O_HACK 0
5925#endif
5926#if GCC_ASM_O_HACK
5927 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 5928 if (i.types[this_operand].bitfield.baseIndex
24eab124 5929 && displacement_string_end[-1] == '+')
252b5132
RH		 5930 {
5931 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 5932 constraint within gcc asm statements.
5933 For instance:
5934
5935 #define _set_tssldt_desc(n,addr,limit,type) \
5936 __asm__ __volatile__ ( \
5937 "movw %w2,%0\n\t" \
5938 "movw %w1,2+%0\n\t" \
5939 "rorl $16,%1\n\t" \
5940 "movb %b1,4+%0\n\t" \
5941 "movb %4,5+%0\n\t" \
5942 "movb $0,6+%0\n\t" \
5943 "movb %h1,7+%0\n\t" \
5944 "rorl $16,%1" \
5945 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5946
5947 This works great except that the output assembler ends
5948 up looking a bit weird if it turns out that there is
5949 no offset. You end up producing code that looks like:
5950
5951 #APP
5952 movw $235,(%eax)
5953 movw %dx,2+(%eax)
5954 rorl $16,%edx
5955 movb %dl,4+(%eax)
5956 movb $137,5+(%eax)
5957 movb $0,6+(%eax)
5958 movb %dh,7+(%eax)
5959 rorl $16,%edx
5960 #NO_APP
5961
47926f60 5962 So here we provide the missing zero. */
24eab124
AM		 5963
5964 *displacement_string_end = '0';
252b5132
RH		 5965 }
5966#endif
3956db08 5967 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5968 if (gotfree_input_line)
5969 input_line_pointer = gotfree_input_line;
252b5132 5970
24eab124 5971 exp_seg = expression (exp);
252b5132 5972
636c26b0
AM		 5973 SKIP_WHITESPACE ();
5974 if (*input_line_pointer)
5975 as_bad (_("junk `%s' after expression"), input_line_pointer);
5976#if GCC_ASM_O_HACK
5977 RESTORE_END_STRING (disp_end + 1);
5978#endif
636c26b0 5979 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 5980 if (gotfree_input_line)
5981 free (gotfree_input_line);
3992d3b7 5982 ret = 1;
636c26b0 5983
24eab124
AM		 5984 /* We do this to make sure that the section symbol is in
5985 the symbol table. We will ultimately change the relocation
47926f60 5986 to be relative to the beginning of the section. */
1ae12ab7 5987 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 5988 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
5989 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 5990 {
636c26b0 5991 if (exp->X_op != O_symbol)
3992d3b7 5992 goto inv_disp;
636c26b0 5993
e5cb08ac 5994 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 5995 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
5996 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 5997 exp->X_op = O_subtract;
5998 exp->X_op_symbol = GOT_symbol;
1ae12ab7 5999 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6000 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6001 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6002 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6003 else
29b0f896 6004 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6005 }
252b5132 6006
3992d3b7
AM		 6007 else if (exp->X_op == O_absent
6008 || exp->X_op == O_illegal
6009 || exp->X_op == O_big
6010 || (gotfree_input_line
6011 && (exp->X_op == O_constant
6012 || exp->X_op == O_register)))
2daf4fd8 6013 {
3992d3b7
AM		 6014 inv_disp:
6015 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6016 disp_start);
3992d3b7 6017 ret = 0;
2daf4fd8
AM		 6018 }
6019
4c63da97 6020#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6021 else if (exp->X_op != O_constant
6022 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6023 && exp_seg != absolute_section
6024 && exp_seg != text_section
6025 && exp_seg != data_section
6026 && exp_seg != bss_section
6027 && exp_seg != undefined_section
6028 && !bfd_is_com_section (exp_seg))
24eab124 6029 {
d0b47220 6030 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6031 ret = 0;
24eab124 6032 }
252b5132 6033#endif
3956db08 6034
3992d3b7
AM		 6035 RESTORE_END_STRING (disp_end);
6036
40fb9820
L		 6037 /* Check if this is a displacement only operand. */
6038 bigdisp = i.types[this_operand];
6039 bigdisp.bitfield.disp8 = 0;
6040 bigdisp.bitfield.disp16 = 0;
6041 bigdisp.bitfield.disp32 = 0;
6042 bigdisp.bitfield.disp32s = 0;
6043 bigdisp.bitfield.disp64 = 0;
c6fb90c8
L		 6044 if (UINTS_ALL_ZERO (bigdisp))
6045 i.types[this_operand] = operand_type_and (i.types[this_operand],
6046 types);
3956db08 6047
3992d3b7 6048 return ret;
252b5132
RH		 6049}
6050
eecb386c 6051/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6052 Return 1 on success, 0 on a failure. */
6053
252b5132 6054static int
e3bb37b5 6055i386_index_check (const char *operand_string)
252b5132 6056{
3e73aa7c 6057 int ok;
24eab124 6058#if INFER_ADDR_PREFIX
eecb386c
AM		 6059 int fudged = 0;
6060
24eab124
AM		 6061 tryprefix:
6062#endif
3e73aa7c 6063 ok = 1;
75178d9d 6064 if (flag_code == CODE_64BIT)
64e74474 6065 {
64e74474 6066 if ((i.base_reg
40fb9820
L		 6067 && ((i.prefix[ADDR_PREFIX] == 0
6068 && !i.base_reg->reg_type.bitfield.reg64)
6069 || (i.prefix[ADDR_PREFIX]
6070 && !i.base_reg->reg_type.bitfield.reg32))
6071 && (i.index_reg
9a04903e
JB		 6072 || i.base_reg->reg_num !=
6073 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6074 || (i.index_reg
40fb9820
L		 6075 && (!i.index_reg->reg_type.bitfield.baseindex
6076 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6077 && i.index_reg->reg_num != RegRiz
6078 && !i.index_reg->reg_type.bitfield.reg64
6079 )
40fb9820 6080 || (i.prefix[ADDR_PREFIX]
db51cc60 6081 && i.index_reg->reg_num != RegEiz
40fb9820 6082 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6083 ok = 0;
3e73aa7c
JH		 6084 }
6085 else
6086 {
6087 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6088 {
6089 /* 16bit checks. */
6090 if ((i.base_reg
40fb9820
L		 6091 && (!i.base_reg->reg_type.bitfield.reg16
6092 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6093 || (i.index_reg
40fb9820
L		 6094 && (!i.index_reg->reg_type.bitfield.reg16
6095 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6096 || !(i.base_reg
6097 && i.base_reg->reg_num < 6
6098 && i.index_reg->reg_num >= 6
6099 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6100 ok = 0;
6101 }
6102 else
e5cb08ac 6103 {
3e73aa7c
JH		 6104 /* 32bit checks. */
6105 if ((i.base_reg
40fb9820 6106 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6107 || (i.index_reg
db51cc60
L		 6108 && ((!i.index_reg->reg_type.bitfield.reg32
6109 && i.index_reg->reg_num != RegEiz)
40fb9820 6110 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6111 ok = 0;
3e73aa7c
JH		 6112 }
6113 }
6114 if (!ok)
24eab124
AM		 6115 {
6116#if INFER_ADDR_PREFIX
20f0a1fc 6117 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 6118 {
6119 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6120 i.prefixes += 1;
b23bac36
AM		 6121 /* Change the size of any displacement too. At most one of
6122 Disp16 or Disp32 is set.
6123 FIXME. There doesn't seem to be any real need for separate
6124 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6125 Removing them would probably clean up the code quite a lot. */
4eed87de 6126 if (flag_code != CODE_64BIT
40fb9820
L		 6127 && (i.types[this_operand].bitfield.disp16
6128 || i.types[this_operand].bitfield.disp32))
6129 i.types[this_operand]
c6fb90c8 6130 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6131 fudged = 1;
24eab124
AM		 6132 goto tryprefix;
6133 }
eecb386c
AM		 6134 if (fudged)
6135 as_bad (_("`%s' is not a valid base/index expression"),
6136 operand_string);
6137 else
c388dee8 6138#endif
eecb386c
AM		 6139 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6140 operand_string,
3e73aa7c 6141 flag_code_names[flag_code]);
24eab124 6142 }
20f0a1fc 6143 return ok;
24eab124 6144}
252b5132 6145
252b5132 6146/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 6147 on error. */
252b5132 6148
252b5132 6149static int
a7619375 6150i386_att_operand (char *operand_string)
252b5132 6151{
af6bdddf
AM		 6152 const reg_entry *r;
6153 char *end_op;
24eab124 6154 char *op_string = operand_string;
252b5132 6155
24eab124 6156 if (is_space_char (*op_string))
252b5132
RH		 6157 ++op_string;
6158
24eab124 6159 /* We check for an absolute prefix (differentiating,
47926f60 6160 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6161 if (*op_string == ABSOLUTE_PREFIX)
6162 {
6163 ++op_string;
6164 if (is_space_char (*op_string))
6165 ++op_string;
40fb9820 6166 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6167 }
252b5132 6168
47926f60 6169 /* Check if operand is a register. */
4d1bb795 6170 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6171 {
40fb9820
L		 6172 i386_operand_type temp;
6173
24eab124
AM		 6174 /* Check for a segment override by searching for ':' after a
6175 segment register. */
6176 op_string = end_op;
6177 if (is_space_char (*op_string))
6178 ++op_string;
40fb9820
L		 6179 if (*op_string == ':'
6180 && (r->reg_type.bitfield.sreg2
6181 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6182 {
6183 switch (r->reg_num)
6184 {
6185 case 0:
6186 i.seg[i.mem_operands] = &es;
6187 break;
6188 case 1:
6189 i.seg[i.mem_operands] = &cs;
6190 break;
6191 case 2:
6192 i.seg[i.mem_operands] = &ss;
6193 break;
6194 case 3:
6195 i.seg[i.mem_operands] = &ds;
6196 break;
6197 case 4:
6198 i.seg[i.mem_operands] = &fs;
6199 break;
6200 case 5:
6201 i.seg[i.mem_operands] = &gs;
6202 break;
6203 }
252b5132 6204
24eab124 6205 /* Skip the ':' and whitespace. */
252b5132
RH		 6206 ++op_string;
6207 if (is_space_char (*op_string))
24eab124 6208 ++op_string;
252b5132 6209
24eab124
AM		 6210 if (!is_digit_char (*op_string)
6211 && !is_identifier_char (*op_string)
6212 && *op_string != '('
6213 && *op_string != ABSOLUTE_PREFIX)
6214 {
6215 as_bad (_("bad memory operand `%s'"), op_string);
6216 return 0;
6217 }
47926f60 6218 /* Handle case of %es:*foo. */
24eab124
AM		 6219 if (*op_string == ABSOLUTE_PREFIX)
6220 {
6221 ++op_string;
6222 if (is_space_char (*op_string))
6223 ++op_string;
40fb9820 6224 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6225 }
6226 goto do_memory_reference;
6227 }
6228 if (*op_string)
6229 {
d0b47220 6230 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6231 return 0;
6232 }
40fb9820
L		 6233 temp = r->reg_type;
6234 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6235 i.types[this_operand] = operand_type_or (i.types[this_operand],
6236 temp);
7d5e4556 6237 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 6238 i.op[this_operand].regs = r;
24eab124
AM		 6239 i.reg_operands++;
6240 }
af6bdddf
AM		 6241 else if (*op_string == REGISTER_PREFIX)
6242 {
6243 as_bad (_("bad register name `%s'"), op_string);
6244 return 0;
6245 }
24eab124 6246 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6247 {
24eab124 6248 ++op_string;
40fb9820 6249 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6250 {
d0b47220 6251 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6252 return 0;
6253 }
6254 if (!i386_immediate (op_string))
6255 return 0;
6256 }
6257 else if (is_digit_char (*op_string)
6258 || is_identifier_char (*op_string)
e5cb08ac 6259 || *op_string == '(')
24eab124 6260 {
47926f60 6261 /* This is a memory reference of some sort. */
af6bdddf 6262 char *base_string;
252b5132 6263
47926f60 6264 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 6265 char *displacement_string_start;
6266 char *displacement_string_end;
252b5132 6267
24eab124 6268 do_memory_reference:
24eab124 6269 if ((i.mem_operands == 1
40fb9820 6270 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 6271 || i.mem_operands == 2)
6272 {
6273 as_bad (_("too many memory references for `%s'"),
6274 current_templates->start->name);
6275 return 0;
6276 }
252b5132 6277
24eab124
AM		 6278 /* Check for base index form. We detect the base index form by
6279 looking for an ')' at the end of the operand, searching
6280 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6281 after the '('. */
af6bdddf 6282 base_string = op_string + strlen (op_string);
c3332e24 6283
af6bdddf
AM		 6284 --base_string;
6285 if (is_space_char (*base_string))
6286 --base_string;
252b5132 6287
47926f60 6288 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 6289 displacement_string_start = op_string;
6290 displacement_string_end = base_string + 1;
252b5132 6291
24eab124
AM		 6292 if (*base_string == ')')
6293 {
af6bdddf 6294 char *temp_string;
24eab124
AM		 6295 unsigned int parens_balanced = 1;
6296 /* We've already checked that the number of left & right ()'s are
47926f60 6297 equal, so this loop will not be infinite. */
24eab124
AM		 6298 do
6299 {
6300 base_string--;
6301 if (*base_string == ')')
6302 parens_balanced++;
6303 if (*base_string == '(')
6304 parens_balanced--;
6305 }
6306 while (parens_balanced);
c3332e24 6307
af6bdddf 6308 temp_string = base_string;
c3332e24 6309
24eab124 6310 /* Skip past '(' and whitespace. */
252b5132
RH		 6311 ++base_string;
6312 if (is_space_char (*base_string))
24eab124 6313 ++base_string;
252b5132 6314
af6bdddf 6315 if (*base_string == ','
4eed87de
AM		 6316 || ((i.base_reg = parse_register (base_string, &end_op))
6317 != NULL))
252b5132 6318 {
af6bdddf 6319 displacement_string_end = temp_string;
252b5132 6320
40fb9820 6321 i.types[this_operand].bitfield.baseindex = 1;
252b5132 6322
af6bdddf 6323 if (i.base_reg)
24eab124 6324 {
24eab124
AM		 6325 base_string = end_op;
6326 if (is_space_char (*base_string))
6327 ++base_string;
af6bdddf
AM		 6328 }
6329
6330 /* There may be an index reg or scale factor here. */
6331 if (*base_string == ',')
6332 {
6333 ++base_string;
6334 if (is_space_char (*base_string))
6335 ++base_string;
6336
4eed87de
AM		 6337 if ((i.index_reg = parse_register (base_string, &end_op))
6338 != NULL)
24eab124 6339 {
af6bdddf 6340 base_string = end_op;
24eab124
AM		 6341 if (is_space_char (*base_string))
6342 ++base_string;
af6bdddf
AM		 6343 if (*base_string == ',')
6344 {
6345 ++base_string;
6346 if (is_space_char (*base_string))
6347 ++base_string;
6348 }
e5cb08ac 6349 else if (*base_string != ')')
af6bdddf 6350 {
4eed87de
AM		 6351 as_bad (_("expecting `,' or `)' "
6352 "after index register in `%s'"),
af6bdddf
AM		 6353 operand_string);
6354 return 0;
6355 }
24eab124 6356 }
af6bdddf 6357 else if (*base_string == REGISTER_PREFIX)
24eab124 6358 {
af6bdddf 6359 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 6360 return 0;
6361 }
252b5132 6362
47926f60 6363 /* Check for scale factor. */
551c1ca1 6364 if (*base_string != ')')
af6bdddf 6365 {
551c1ca1
AM		 6366 char *end_scale = i386_scale (base_string);
6367
6368 if (!end_scale)
af6bdddf 6369 return 0;
24eab124 6370
551c1ca1 6371 base_string = end_scale;
af6bdddf
AM		 6372 if (is_space_char (*base_string))
6373 ++base_string;
6374 if (*base_string != ')')
6375 {
4eed87de
AM		 6376 as_bad (_("expecting `)' "
6377 "after scale factor in `%s'"),
af6bdddf
AM		 6378 operand_string);
6379 return 0;
6380 }
6381 }
6382 else if (!i.index_reg)
24eab124 6383 {
4eed87de
AM		 6384 as_bad (_("expecting index register or scale factor "
6385 "after `,'; got '%c'"),
af6bdddf 6386 *base_string);
24eab124
AM		 6387 return 0;
6388 }
6389 }
af6bdddf 6390 else if (*base_string != ')')
24eab124 6391 {
4eed87de
AM		 6392 as_bad (_("expecting `,' or `)' "
6393 "after base register in `%s'"),
af6bdddf 6394 operand_string);
24eab124
AM		 6395 return 0;
6396 }
c3332e24 6397 }
af6bdddf 6398 else if (*base_string == REGISTER_PREFIX)
c3332e24 6399 {
af6bdddf 6400 as_bad (_("bad register name `%s'"), base_string);
24eab124 6401 return 0;
c3332e24 6402 }
24eab124
AM		 6403 }
6404
6405 /* If there's an expression beginning the operand, parse it,
6406 assuming displacement_string_start and
6407 displacement_string_end are meaningful. */
6408 if (displacement_string_start != displacement_string_end)
6409 {
6410 if (!i386_displacement (displacement_string_start,
6411 displacement_string_end))
6412 return 0;
6413 }
6414
6415 /* Special case for (%dx) while doing input/output op. */
6416 if (i.base_reg
c6fb90c8 6417 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
24eab124
AM		 6418 && i.index_reg == 0
6419 && i.log2_scale_factor == 0
6420 && i.seg[i.mem_operands] == 0
40fb9820 6421 && !operand_type_check (i.types[this_operand], disp))
24eab124 6422 {
c6fb90c8 6423 UINTS_CLEAR (i.types[this_operand]);
40fb9820 6424 i.types[this_operand].bitfield.inoutportreg = 1;
24eab124
AM		 6425 return 1;
6426 }
6427
eecb386c
AM		 6428 if (i386_index_check (operand_string) == 0)
6429 return 0;
5c07affc 6430 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 6431 i.mem_operands++;
6432 }
6433 else
ce8a8b2f
AM		 6434 {
6435 /* It's not a memory operand; argh! */
24eab124
AM		 6436 as_bad (_("invalid char %s beginning operand %d `%s'"),
6437 output_invalid (*op_string),
6438 this_operand + 1,
6439 op_string);
6440 return 0;
6441 }
47926f60 6442 return 1; /* Normal return. */
252b5132
RH		 6443}
6444\f
ee7fcc42
AM		 6445/* md_estimate_size_before_relax()
6446
6447 Called just before relax() for rs_machine_dependent frags. The x86
6448 assembler uses these frags to handle variable size jump
6449 instructions.
6450
6451 Any symbol that is now undefined will not become defined.
6452 Return the correct fr_subtype in the frag.
6453 Return the initial "guess for variable size of frag" to caller.
6454 The guess is actually the growth beyond the fixed part. Whatever
6455 we do to grow the fixed or variable part contributes to our
6456 returned value. */
6457
252b5132
RH		 6458int
6459md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 6460 fragS *fragP;
6461 segT segment;
252b5132 6462{
252b5132 6463 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 6464 check for un-relaxable symbols. On an ELF system, we can't relax
6465 an externally visible symbol, because it may be overridden by a
6466 shared library. */
6467 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 6468#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6469 || (IS_ELF
31312f95
AM		 6470 && (S_IS_EXTERNAL (fragP->fr_symbol)
6471 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 6472#endif
6473 )
252b5132 6474 {
b98ef147
AM		 6475 /* Symbol is undefined in this segment, or we need to keep a
6476 reloc so that weak symbols can be overridden. */
6477 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 6478 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 6479 unsigned char *opcode;
6480 int old_fr_fix;
f6af82bd 6481
ee7fcc42
AM		 6482 if (fragP->fr_var != NO_RELOC)
6483 reloc_type = fragP->fr_var;
b98ef147 6484 else if (size == 2)
f6af82bd
AM		 6485 reloc_type = BFD_RELOC_16_PCREL;
6486 else
6487 reloc_type = BFD_RELOC_32_PCREL;
252b5132 6488
ee7fcc42
AM		 6489 old_fr_fix = fragP->fr_fix;
6490 opcode = (unsigned char *) fragP->fr_opcode;
6491
fddf5b5b 6492 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 6493 {
fddf5b5b
AM		 6494 case UNCOND_JUMP:
6495 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 6496 opcode[0] = 0xe9;
252b5132 6497 fragP->fr_fix += size;
062cd5e7
AS		 6498 fix_new (fragP, old_fr_fix, size,
6499 fragP->fr_symbol,
6500 fragP->fr_offset, 1,
6501 reloc_type);
252b5132
RH		 6502 break;
6503
fddf5b5b 6504 case COND_JUMP86:
412167cb
AM		 6505 if (size == 2
6506 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 6507 {
6508 /* Negate the condition, and branch past an
6509 unconditional jump. */
6510 opcode[0] ^= 1;
6511 opcode[1] = 3;
6512 /* Insert an unconditional jump. */
6513 opcode[2] = 0xe9;
6514 /* We added two extra opcode bytes, and have a two byte
6515 offset. */
6516 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 6517 fix_new (fragP, old_fr_fix + 2, 2,
6518 fragP->fr_symbol,
6519 fragP->fr_offset, 1,
6520 reloc_type);
fddf5b5b
AM		 6521 break;
6522 }
6523 /* Fall through. */
6524
6525 case COND_JUMP:
412167cb
AM		 6526 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6527 {
3e02c1cc
AM		 6528 fixS *fixP;
6529
412167cb 6530 fragP->fr_fix += 1;
3e02c1cc
AM		 6531 fixP = fix_new (fragP, old_fr_fix, 1,
6532 fragP->fr_symbol,
6533 fragP->fr_offset, 1,
6534 BFD_RELOC_8_PCREL);
6535 fixP->fx_signed = 1;
412167cb
AM		 6536 break;
6537 }
93c2a809 6538
24eab124 6539 /* This changes the byte-displacement jump 0x7N
fddf5b5b 6540 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 6541 opcode[1] = opcode[0] + 0x10;
f6af82bd 6542 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 6543 /* We've added an opcode byte. */
6544 fragP->fr_fix += 1 + size;
062cd5e7
AS		 6545 fix_new (fragP, old_fr_fix + 1, size,
6546 fragP->fr_symbol,
6547 fragP->fr_offset, 1,
6548 reloc_type);
252b5132 6549 break;
fddf5b5b
AM		 6550
6551 default:
6552 BAD_CASE (fragP->fr_subtype);
6553 break;
252b5132
RH		 6554 }
6555 frag_wane (fragP);
ee7fcc42 6556 return fragP->fr_fix - old_fr_fix;
252b5132 6557 }
93c2a809 6558
93c2a809
AM		 6559 /* Guess size depending on current relax state. Initially the relax
6560 state will correspond to a short jump and we return 1, because
6561 the variable part of the frag (the branch offset) is one byte
6562 long. However, we can relax a section more than once and in that
6563 case we must either set fr_subtype back to the unrelaxed state,
6564 or return the value for the appropriate branch. */
6565 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 6566}
6567
47926f60
KH		 6568/* Called after relax() is finished.
6569
6570 In: Address of frag.
6571 fr_type == rs_machine_dependent.
6572 fr_subtype is what the address relaxed to.
6573
6574 Out: Any fixSs and constants are set up.
6575 Caller will turn frag into a ".space 0". */
6576
252b5132
RH		 6577void
6578md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 6579 bfd *abfd ATTRIBUTE_UNUSED;
6580 segT sec ATTRIBUTE_UNUSED;
29b0f896 6581 fragS *fragP;
252b5132 6582{
29b0f896 6583 unsigned char *opcode;
252b5132 6584 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 6585 offsetT target_address;
6586 offsetT opcode_address;
252b5132 6587 unsigned int extension = 0;
847f7ad4 6588 offsetT displacement_from_opcode_start;
252b5132
RH		 6589
6590 opcode = (unsigned char *) fragP->fr_opcode;
6591
47926f60 6592 /* Address we want to reach in file space. */
252b5132 6593 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 6594
47926f60 6595 /* Address opcode resides at in file space. */
252b5132
RH		 6596 opcode_address = fragP->fr_address + fragP->fr_fix;
6597
47926f60 6598 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 6599 displacement_from_opcode_start = target_address - opcode_address;
6600
fddf5b5b 6601 if ((fragP->fr_subtype & BIG) == 0)
252b5132 6602 {
47926f60
KH		 6603 /* Don't have to change opcode. */
6604 extension = 1; /* 1 opcode + 1 displacement */
252b5132 6605 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 6606 }
6607 else
6608 {
6609 if (no_cond_jump_promotion
6610 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 6611 as_warn_where (fragP->fr_file, fragP->fr_line,
6612 _("long jump required"));
252b5132 6613
fddf5b5b
AM		 6614 switch (fragP->fr_subtype)
6615 {
6616 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6617 extension = 4; /* 1 opcode + 4 displacement */
6618 opcode[0] = 0xe9;
6619 where_to_put_displacement = &opcode[1];
6620 break;
252b5132 6621
fddf5b5b
AM		 6622 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6623 extension = 2; /* 1 opcode + 2 displacement */
6624 opcode[0] = 0xe9;
6625 where_to_put_displacement = &opcode[1];
6626 break;
252b5132 6627
fddf5b5b
AM		 6628 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6629 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6630 extension = 5; /* 2 opcode + 4 displacement */
6631 opcode[1] = opcode[0] + 0x10;
6632 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6633 where_to_put_displacement = &opcode[2];
6634 break;
252b5132 6635
fddf5b5b
AM		 6636 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6637 extension = 3; /* 2 opcode + 2 displacement */
6638 opcode[1] = opcode[0] + 0x10;
6639 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6640 where_to_put_displacement = &opcode[2];
6641 break;
252b5132 6642
fddf5b5b
AM		 6643 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6644 extension = 4;
6645 opcode[0] ^= 1;
6646 opcode[1] = 3;
6647 opcode[2] = 0xe9;
6648 where_to_put_displacement = &opcode[3];
6649 break;
6650
6651 default:
6652 BAD_CASE (fragP->fr_subtype);
6653 break;
6654 }
252b5132 6655 }
fddf5b5b 6656
7b81dfbb
AJ		 6657 /* If size if less then four we are sure that the operand fits,
6658 but if it's 4, then it could be that the displacement is larger
6659 then -/+ 2GB. */
6660 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6661 && object_64bit
6662 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 6663 + ((addressT) 1 << 31))
6664 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 6665 {
6666 as_bad_where (fragP->fr_file, fragP->fr_line,
6667 _("jump target out of range"));
6668 /* Make us emit 0. */
6669 displacement_from_opcode_start = extension;
6670 }
47926f60 6671 /* Now put displacement after opcode. */
252b5132
RH		 6672 md_number_to_chars ((char *) where_to_put_displacement,
6673 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 6674 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 6675 fragP->fr_fix += extension;
6676}
6677\f
252b5132
RH		 6678/* Apply a fixup (fixS) to segment data, once it has been determined
6679 by our caller that we have all the info we need to fix it up.
6680
6681 On the 386, immediates, displacements, and data pointers are all in
6682 the same (little-endian) format, so we don't need to care about which
6683 we are handling. */
6684
94f592af 6685void
55cf6793 6686md_apply_fix (fixP, valP, seg)
47926f60
KH		 6687 /* The fix we're to put in. */
6688 fixS *fixP;
47926f60 6689 /* Pointer to the value of the bits. */
c6682705 6690 valueT *valP;
47926f60
KH		 6691 /* Segment fix is from. */
6692 segT seg ATTRIBUTE_UNUSED;
252b5132 6693{
94f592af 6694 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 6695 valueT value = *valP;
252b5132 6696
f86103b7 6697#if !defined (TE_Mach)
93382f6d
AM		 6698 if (fixP->fx_pcrel)
6699 {
6700 switch (fixP->fx_r_type)
6701 {
5865bb77
ILT		 6702 default:
6703 break;
6704
d6ab8113
JB		 6705 case BFD_RELOC_64:
6706 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6707 break;
93382f6d 6708 case BFD_RELOC_32:
ae8887b5 6709 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 6710 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6711 break;
6712 case BFD_RELOC_16:
6713 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6714 break;
6715 case BFD_RELOC_8:
6716 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6717 break;
6718 }
6719 }
252b5132 6720
a161fe53 6721 if (fixP->fx_addsy != NULL
31312f95 6722 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 6723 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 6724 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6725 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6726 && !use_rela_relocations)
252b5132 6727 {
31312f95
AM		 6728 /* This is a hack. There should be a better way to handle this.
6729 This covers for the fact that bfd_install_relocation will
6730 subtract the current location (for partial_inplace, PC relative
6731 relocations); see more below. */
252b5132 6732#ifndef OBJ_AOUT
718ddfc0 6733 if (IS_ELF
252b5132
RH		 6734#ifdef TE_PE
6735 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6736#endif
6737 )
6738 value += fixP->fx_where + fixP->fx_frag->fr_address;
6739#endif
6740#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6741 if (IS_ELF)
252b5132 6742 {
6539b54b 6743 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 6744
6539b54b 6745 if ((sym_seg == seg
2f66722d 6746 || (symbol_section_p (fixP->fx_addsy)
6539b54b 6747 && sym_seg != absolute_section))
ae6063d4 6748 && !generic_force_reloc (fixP))
2f66722d
AM		 6749 {
6750 /* Yes, we add the values in twice. This is because
6539b54b
AM		 6751 bfd_install_relocation subtracts them out again. I think
6752 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 6753 it. FIXME. */
6754 value += fixP->fx_where + fixP->fx_frag->fr_address;
6755 }
252b5132
RH		 6756 }
6757#endif
6758#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 6759 /* For some reason, the PE format does not store a
6760 section address offset for a PC relative symbol. */
6761 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 6762 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 6763 value += md_pcrel_from (fixP);
6764#endif
6765 }
6766
6767 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 6768 and we must not disappoint it. */
252b5132 6769#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6770 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 6771 switch (fixP->fx_r_type)
6772 {
6773 case BFD_RELOC_386_PLT32:
3e73aa7c 6774 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 6775 /* Make the jump instruction point to the address of the operand. At
6776 runtime we merely add the offset to the actual PLT entry. */
6777 value = -4;
6778 break;
31312f95 6779
13ae64f3
JJ		 6780 case BFD_RELOC_386_TLS_GD:
6781 case BFD_RELOC_386_TLS_LDM:
13ae64f3 6782 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6783 case BFD_RELOC_386_TLS_IE:
6784 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 6785 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 6786 case BFD_RELOC_X86_64_TLSGD:
6787 case BFD_RELOC_X86_64_TLSLD:
6788 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 6789 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 6790 value = 0; /* Fully resolved at runtime. No addend. */
6791 /* Fallthrough */
6792 case BFD_RELOC_386_TLS_LE:
6793 case BFD_RELOC_386_TLS_LDO_32:
6794 case BFD_RELOC_386_TLS_LE_32:
6795 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6796 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 6797 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 6798 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 6799 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6800 break;
6801
67a4f2b7
AO		 6802 case BFD_RELOC_386_TLS_DESC_CALL:
6803 case BFD_RELOC_X86_64_TLSDESC_CALL:
6804 value = 0; /* Fully resolved at runtime. No addend. */
6805 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6806 fixP->fx_done = 0;
6807 return;
6808
00f7efb6
JJ		 6809 case BFD_RELOC_386_GOT32:
6810 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 6811 value = 0; /* Fully resolved at runtime. No addend. */
6812 break;
47926f60
KH		 6813
6814 case BFD_RELOC_VTABLE_INHERIT:
6815 case BFD_RELOC_VTABLE_ENTRY:
6816 fixP->fx_done = 0;
94f592af 6817 return;
47926f60
KH		 6818
6819 default:
6820 break;
6821 }
6822#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 6823 *valP = value;
f86103b7 6824#endif /* !defined (TE_Mach) */
3e73aa7c 6825
3e73aa7c 6826 /* Are we finished with this relocation now? */
c6682705 6827 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 6828 fixP->fx_done = 1;
6829 else if (use_rela_relocations)
6830 {
6831 fixP->fx_no_overflow = 1;
062cd5e7
AS		 6832 /* Remember value for tc_gen_reloc. */
6833 fixP->fx_addnumber = value;
3e73aa7c
JH		 6834 value = 0;
6835 }
f86103b7 6836
94f592af 6837 md_number_to_chars (p, value, fixP->fx_size);
252b5132 6838}
252b5132 6839\f
252b5132 6840char *
499ac353 6841md_atof (int type, char *litP, int *sizeP)
252b5132 6842{
499ac353
NC		 6843 /* This outputs the LITTLENUMs in REVERSE order;
6844 in accord with the bigendian 386. */
6845 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 6846}
6847\f
2d545b82 6848static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 6849
252b5132 6850static char *
e3bb37b5 6851output_invalid (int c)
252b5132 6852{
3882b010 6853 if (ISPRINT (c))
f9f21a03
L		 6854 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6855 "'%c'", c);
252b5132 6856 else
f9f21a03 6857 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 6858 "(0x%x)", (unsigned char) c);
252b5132
RH		 6859 return output_invalid_buf;
6860}
6861
af6bdddf 6862/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 6863
6864static const reg_entry *
4d1bb795 6865parse_real_register (char *reg_string, char **end_op)
252b5132 6866{
af6bdddf
AM		 6867 char *s = reg_string;
6868 char *p;
252b5132
RH		 6869 char reg_name_given[MAX_REG_NAME_SIZE + 1];
6870 const reg_entry *r;
6871
6872 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6873 if (*s == REGISTER_PREFIX)
6874 ++s;
6875
6876 if (is_space_char (*s))
6877 ++s;
6878
6879 p = reg_name_given;
af6bdddf 6880 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 6881 {
6882 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 6883 return (const reg_entry *) NULL;
6884 s++;
252b5132
RH		 6885 }
6886
6588847e
DN		 6887 /* For naked regs, make sure that we are not dealing with an identifier.
6888 This prevents confusing an identifier like `eax_var' with register
6889 `eax'. */
6890 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
6891 return (const reg_entry *) NULL;
6892
af6bdddf 6893 *end_op = s;
252b5132
RH		 6894
6895 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
6896
5f47d35b 6897 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 6898 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 6899 {
5f47d35b
AM		 6900 if (is_space_char (*s))
6901 ++s;
6902 if (*s == '(')
6903 {
af6bdddf 6904 ++s;
5f47d35b
AM		 6905 if (is_space_char (*s))
6906 ++s;
6907 if (*s >= '0' && *s <= '7')
6908 {
db557034 6909 int fpr = *s - '0';
af6bdddf 6910 ++s;
5f47d35b
AM		 6911 if (is_space_char (*s))
6912 ++s;
6913 if (*s == ')')
6914 {
6915 *end_op = s + 1;
db557034
AM		 6916 r = hash_find (reg_hash, "st(0)");
6917 know (r);
6918 return r + fpr;
5f47d35b 6919 }
5f47d35b 6920 }
47926f60 6921 /* We have "%st(" then garbage. */
5f47d35b
AM		 6922 return (const reg_entry *) NULL;
6923 }
6924 }
6925
db51cc60
L		 6926 /* Don't allow fake index register unless allow_index_reg isn't 0. */
6927 if (r != NULL
6928 && !allow_index_reg
6929 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
6930 return (const reg_entry *) NULL;
6931
1ae00879 6932 if (r != NULL
d946b91f 6933 && ((r->reg_flags & (RegRex64 | RegRex))
40fb9820
L		 6934 || r->reg_type.bitfield.reg64)
6935 && (!cpu_arch_flags.bitfield.cpulm
c6fb90c8 6936 || !UINTS_EQUAL (r->reg_type, control))
1ae00879 6937 && flag_code != CODE_64BIT)
20f0a1fc 6938 return (const reg_entry *) NULL;
1ae00879 6939
252b5132
RH		 6940 return r;
6941}
4d1bb795
JB		 6942
6943/* REG_STRING starts *before* REGISTER_PREFIX. */
6944
6945static const reg_entry *
6946parse_register (char *reg_string, char **end_op)
6947{
6948 const reg_entry *r;
6949
6950 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
6951 r = parse_real_register (reg_string, end_op);
6952 else
6953 r = NULL;
6954 if (!r)
6955 {
6956 char *save = input_line_pointer;
6957 char c;
6958 symbolS *symbolP;
6959
6960 input_line_pointer = reg_string;
6961 c = get_symbol_end ();
6962 symbolP = symbol_find (reg_string);
6963 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
6964 {
6965 const expressionS *e = symbol_get_value_expression (symbolP);
6966
6967 know (e->X_op == O_register);
4eed87de 6968 know (e->X_add_number >= 0
c3fe08fa 6969 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 6970 r = i386_regtab + e->X_add_number;
6971 *end_op = input_line_pointer;
6972 }
6973 *input_line_pointer = c;
6974 input_line_pointer = save;
6975 }
6976 return r;
6977}
6978
6979int
6980i386_parse_name (char *name, expressionS *e, char *nextcharP)
6981{
6982 const reg_entry *r;
6983 char *end = input_line_pointer;
6984
6985 *end = *nextcharP;
6986 r = parse_register (name, &input_line_pointer);
6987 if (r && end <= input_line_pointer)
6988 {
6989 *nextcharP = *input_line_pointer;
6990 *input_line_pointer = 0;
6991 e->X_op = O_register;
6992 e->X_add_number = r - i386_regtab;
6993 return 1;
6994 }
6995 input_line_pointer = end;
6996 *end = 0;
6997 return 0;
6998}
6999
7000void
7001md_operand (expressionS *e)
7002{
7003 if (*input_line_pointer == REGISTER_PREFIX)
7004 {
7005 char *end;
7006 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7007
7008 if (r)
7009 {
7010 e->X_op = O_register;
7011 e->X_add_number = r - i386_regtab;
7012 input_line_pointer = end;
7013 }
7014 }
7015}
7016
252b5132 7017\f
4cc782b5 7018#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7019const char *md_shortopts = "kVQ:sqn";
252b5132 7020#else
12b55ccc 7021const char *md_shortopts = "qn";
252b5132 7022#endif
6e0b89ee 7023
3e73aa7c 7024#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7025#define OPTION_64 (OPTION_MD_BASE + 1)
7026#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7027#define OPTION_MARCH (OPTION_MD_BASE + 3)
7028#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7029#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7030#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7031#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7032#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7033#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
b3b91714 7034
99ad8390
NC		 7035struct option md_longopts[] =
7036{
3e73aa7c 7037 {"32", no_argument, NULL, OPTION_32},
99ad8390 7038#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 7039 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7040#endif
b3b91714 7041 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7042 {"march", required_argument, NULL, OPTION_MARCH},
7043 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7044 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7045 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7046 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7047 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7048 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
252b5132
RH		 7049 {NULL, no_argument, NULL, 0}
7050};
7051size_t md_longopts_size = sizeof (md_longopts);
7052
7053int
9103f4f4 7054md_parse_option (int c, char *arg)
252b5132 7055{
9103f4f4
L		 7056 unsigned int i;
7057
252b5132
RH		 7058 switch (c)
7059 {
12b55ccc
L		 7060 case 'n':
7061 optimize_align_code = 0;
7062 break;
7063
a38cf1db
AM		 7064 case 'q':
7065 quiet_warnings = 1;
252b5132
RH		 7066 break;
7067
7068#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7069 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7070 should be emitted or not. FIXME: Not implemented. */
7071 case 'Q':
252b5132
RH		 7072 break;
7073
7074 /* -V: SVR4 argument to print version ID. */
7075 case 'V':
7076 print_version_id ();
7077 break;
7078
a38cf1db
AM		 7079 /* -k: Ignore for FreeBSD compatibility. */
7080 case 'k':
252b5132 7081 break;
4cc782b5
ILT		 7082
7083 case 's':
7084 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7085 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7086 break;
99ad8390
NC		 7087#endif
7088#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 7089 case OPTION_64:
7090 {
7091 const char **list, **l;
7092
3e73aa7c
JH		 7093 list = bfd_target_list ();
7094 for (l = list; *l != NULL; l++)
8620418b 7095 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7096 || strcmp (*l, "coff-x86-64") == 0
7097 || strcmp (*l, "pe-x86-64") == 0
7098 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7099 {
7100 default_arch = "x86_64";
7101 break;
7102 }
3e73aa7c 7103 if (*l == NULL)
6e0b89ee 7104 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7105 free (list);
7106 }
7107 break;
7108#endif
252b5132 7109
6e0b89ee
AM		 7110 case OPTION_32:
7111 default_arch = "i386";
7112 break;
7113
b3b91714
AM		 7114 case OPTION_DIVIDE:
7115#ifdef SVR4_COMMENT_CHARS
7116 {
7117 char *n, *t;
7118 const char *s;
7119
7120 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7121 t = n;
7122 for (s = i386_comment_chars; *s != '\0'; s++)
7123 if (*s != '/')
7124 *t++ = *s;
7125 *t = '\0';
7126 i386_comment_chars = n;
7127 }
7128#endif
7129 break;
7130
9103f4f4
L		 7131 case OPTION_MARCH:
7132 if (*arg == '.')
7133 as_fatal (_("Invalid -march= option: `%s'"), arg);
7134 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7135 {
7136 if (strcmp (arg, cpu_arch [i].name) == 0)
7137 {
ccc9c027 7138 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 7139 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 7140 if (!cpu_arch_tune_set)
7141 {
7142 cpu_arch_tune = cpu_arch_isa;
7143 cpu_arch_tune_flags = cpu_arch_isa_flags;
7144 }
9103f4f4
L		 7145 break;
7146 }
7147 }
7148 if (i >= ARRAY_SIZE (cpu_arch))
7149 as_fatal (_("Invalid -march= option: `%s'"), arg);
7150 break;
7151
7152 case OPTION_MTUNE:
7153 if (*arg == '.')
7154 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7155 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7156 {
7157 if (strcmp (arg, cpu_arch [i].name) == 0)
7158 {
ccc9c027 7159 cpu_arch_tune_set = 1;
9103f4f4
L		 7160 cpu_arch_tune = cpu_arch [i].type;
7161 cpu_arch_tune_flags = cpu_arch[i].flags;
7162 break;
7163 }
7164 }
7165 if (i >= ARRAY_SIZE (cpu_arch))
7166 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7167 break;
7168
1efbbeb4
L		 7169 case OPTION_MMNEMONIC:
7170 if (strcasecmp (arg, "att") == 0)
7171 intel_mnemonic = 0;
7172 else if (strcasecmp (arg, "intel") == 0)
7173 intel_mnemonic = 1;
7174 else
7175 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7176 break;
7177
7178 case OPTION_MSYNTAX:
7179 if (strcasecmp (arg, "att") == 0)
7180 intel_syntax = 0;
7181 else if (strcasecmp (arg, "intel") == 0)
7182 intel_syntax = 1;
7183 else
7184 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7185 break;
7186
7187 case OPTION_MINDEX_REG:
7188 allow_index_reg = 1;
7189 break;
7190
7191 case OPTION_MNAKED_REG:
7192 allow_naked_reg = 1;
7193 break;
7194
7195 case OPTION_MOLD_GCC:
7196 old_gcc = 1;
1efbbeb4
L		 7197 break;
7198
252b5132
RH		 7199 default:
7200 return 0;
7201 }
7202 return 1;
7203}
7204
7205void
7206md_show_usage (stream)
7207 FILE *stream;
7208{
4cc782b5
ILT		 7209#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7210 fprintf (stream, _("\
a38cf1db
AM		 7211 -Q ignored\n\
7212 -V print assembler version number\n\
b3b91714
AM		 7213 -k ignored\n"));
7214#endif
7215 fprintf (stream, _("\
12b55ccc 7216 -n Do not optimize code alignment\n\
b3b91714
AM		 7217 -q quieten some warnings\n"));
7218#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7219 fprintf (stream, _("\
a38cf1db 7220 -s ignored\n"));
b3b91714 7221#endif
751d281c
L		 7222#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7223 fprintf (stream, _("\
7224 --32/--64 generate 32bit/64bit code\n"));
7225#endif
b3b91714
AM		 7226#ifdef SVR4_COMMENT_CHARS
7227 fprintf (stream, _("\
7228 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 7229#else
7230 fprintf (stream, _("\
b3b91714 7231 --divide ignored\n"));
4cc782b5 7232#endif
9103f4f4
L		 7233 fprintf (stream, _("\
7234 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
7235 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 7236 core, core2, k6, athlon, k8, generic32, generic64\n"));
ba104c83
L		 7237 fprintf (stream, _("\
7238 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7239 fprintf (stream, _("\
7240 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7241 fprintf (stream, _("\
7242 -mindex-reg support pseudo index registers\n"));
7243 fprintf (stream, _("\
7244 -mnaked-reg don't require `%%' prefix for registers\n"));
7245 fprintf (stream, _("\
7246 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 7247}
7248
3e73aa7c 7249#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 7250 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 7251
7252/* Pick the target format to use. */
7253
47926f60 7254const char *
e3bb37b5 7255i386_target_format (void)
252b5132 7256{
3e73aa7c 7257 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 7258 {
7259 set_code_flag (CODE_64BIT);
c6fb90c8 7260 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7261 {
7262 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7263 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7264 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7265 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7266 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7267 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7268 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7269 cpu_arch_isa_flags.bitfield.cpummx= 1;
7270 cpu_arch_isa_flags.bitfield.cpummx2 = 1;
7271 cpu_arch_isa_flags.bitfield.cpusse = 1;
7272 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7273 }
c6fb90c8 7274 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7275 {
7276 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7277 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7278 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7279 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7280 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7281 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7282 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7283 cpu_arch_tune_flags.bitfield.cpummx= 1;
7284 cpu_arch_tune_flags.bitfield.cpummx2 = 1;
7285 cpu_arch_tune_flags.bitfield.cpusse = 1;
7286 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7287 }
9103f4f4 7288 }
3e73aa7c 7289 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 7290 {
7291 set_code_flag (CODE_32BIT);
c6fb90c8 7292 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7293 {
7294 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7295 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7296 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7297 }
c6fb90c8 7298 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7299 {
7300 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7301 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7302 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7303 }
9103f4f4 7304 }
3e73aa7c
JH		 7305 else
7306 as_fatal (_("Unknown architecture"));
252b5132
RH		 7307 switch (OUTPUT_FLAVOR)
7308 {
872ce6ff
L		 7309#ifdef TE_PEP
7310 case bfd_target_coff_flavour:
7311 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7312 break;
7313#endif
4c63da97
AM		 7314#ifdef OBJ_MAYBE_AOUT
7315 case bfd_target_aout_flavour:
47926f60 7316 return AOUT_TARGET_FORMAT;
4c63da97
AM		 7317#endif
7318#ifdef OBJ_MAYBE_COFF
252b5132
RH		 7319 case bfd_target_coff_flavour:
7320 return "coff-i386";
4c63da97 7321#endif
3e73aa7c 7322#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 7323 case bfd_target_elf_flavour:
3e73aa7c 7324 {
e5cb08ac 7325 if (flag_code == CODE_64BIT)
4fa24527
JB		 7326 {
7327 object_64bit = 1;
7328 use_rela_relocations = 1;
7329 }
9d7cbccd 7330 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 7331 }
4c63da97 7332#endif
252b5132
RH		 7333 default:
7334 abort ();
7335 return NULL;
7336 }
7337}
7338
47926f60 7339#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 7340
7341#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 7342void
7343i386_elf_emit_arch_note (void)
a847613f 7344{
718ddfc0 7345 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 7346 {
7347 char *p;
7348 asection *seg = now_seg;
7349 subsegT subseg = now_subseg;
7350 Elf_Internal_Note i_note;
7351 Elf_External_Note e_note;
7352 asection *note_secp;
7353 int len;
7354
7355 /* Create the .note section. */
7356 note_secp = subseg_new (".note", 0);
7357 bfd_set_section_flags (stdoutput,
7358 note_secp,
7359 SEC_HAS_CONTENTS | SEC_READONLY);
7360
7361 /* Process the arch string. */
7362 len = strlen (cpu_arch_name);
7363
7364 i_note.namesz = len + 1;
7365 i_note.descsz = 0;
7366 i_note.type = NT_ARCH;
7367 p = frag_more (sizeof (e_note.namesz));
7368 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7369 p = frag_more (sizeof (e_note.descsz));
7370 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7371 p = frag_more (sizeof (e_note.type));
7372 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7373 p = frag_more (len + 1);
7374 strcpy (p, cpu_arch_name);
7375
7376 frag_align (2, 0, 0);
7377
7378 subseg_set (seg, subseg);
7379 }
7380}
7381#endif
252b5132 7382\f
252b5132
RH		 7383symbolS *
7384md_undefined_symbol (name)
7385 char *name;
7386{
18dc2407
ILT		 7387 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7388 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7389 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7390 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 7391 {
7392 if (!GOT_symbol)
7393 {
7394 if (symbol_find (name))
7395 as_bad (_("GOT already in symbol table"));
7396 GOT_symbol = symbol_new (name, undefined_section,
7397 (valueT) 0, &zero_address_frag);
7398 };
7399 return GOT_symbol;
7400 }
252b5132
RH		 7401 return 0;
7402}
7403
7404/* Round up a section size to the appropriate boundary. */
47926f60 7405
252b5132
RH		 7406valueT
7407md_section_align (segment, size)
ab9da554 7408 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7409 valueT size;
7410{
4c63da97
AM		 7411#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7412 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7413 {
7414 /* For a.out, force the section size to be aligned. If we don't do
7415 this, BFD will align it for us, but it will not write out the
7416 final bytes of the section. This may be a bug in BFD, but it is
7417 easier to fix it here since that is how the other a.out targets
7418 work. */
7419 int align;
7420
7421 align = bfd_get_section_alignment (stdoutput, segment);
7422 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7423 }
252b5132
RH		 7424#endif
7425
7426 return size;
7427}
7428
7429/* On the i386, PC-relative offsets are relative to the start of the
7430 next instruction. That is, the address of the offset, plus its
7431 size, since the offset is always the last part of the insn. */
7432
7433long
e3bb37b5 7434md_pcrel_from (fixS *fixP)
252b5132
RH		 7435{
7436 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7437}
7438
7439#ifndef I386COFF
7440
7441static void
e3bb37b5 7442s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 7443{
29b0f896 7444 int temp;
252b5132 7445
8a75718c
JB		 7446#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7447 if (IS_ELF)
7448 obj_elf_section_change_hook ();
7449#endif
252b5132
RH		 7450 temp = get_absolute_expression ();
7451 subseg_set (bss_section, (subsegT) temp);
7452 demand_empty_rest_of_line ();
7453}
7454
7455#endif
7456
252b5132 7457void
e3bb37b5 7458i386_validate_fix (fixS *fixp)
252b5132
RH		 7459{
7460 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7461 {
23df1078
JH		 7462 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7463 {
4fa24527 7464 if (!object_64bit)
23df1078
JH		 7465 abort ();
7466 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7467 }
7468 else
7469 {
4fa24527 7470 if (!object_64bit)
d6ab8113
JB		 7471 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7472 else
7473 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 7474 }
252b5132
RH		 7475 fixp->fx_subsy = 0;
7476 }
7477}
7478
252b5132
RH		 7479arelent *
7480tc_gen_reloc (section, fixp)
ab9da554 7481 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 7482 fixS *fixp;
7483{
7484 arelent *rel;
7485 bfd_reloc_code_real_type code;
7486
7487 switch (fixp->fx_r_type)
7488 {
3e73aa7c
JH		 7489 case BFD_RELOC_X86_64_PLT32:
7490 case BFD_RELOC_X86_64_GOT32:
7491 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 7492 case BFD_RELOC_386_PLT32:
7493 case BFD_RELOC_386_GOT32:
7494 case BFD_RELOC_386_GOTOFF:
7495 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 7496 case BFD_RELOC_386_TLS_GD:
7497 case BFD_RELOC_386_TLS_LDM:
7498 case BFD_RELOC_386_TLS_LDO_32:
7499 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7500 case BFD_RELOC_386_TLS_IE:
7501 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 7502 case BFD_RELOC_386_TLS_LE_32:
7503 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 7504 case BFD_RELOC_386_TLS_GOTDESC:
7505 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 7506 case BFD_RELOC_X86_64_TLSGD:
7507 case BFD_RELOC_X86_64_TLSLD:
7508 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7509 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 7510 case BFD_RELOC_X86_64_GOTTPOFF:
7511 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 7512 case BFD_RELOC_X86_64_TPOFF64:
7513 case BFD_RELOC_X86_64_GOTOFF64:
7514 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 7515 case BFD_RELOC_X86_64_GOT64:
7516 case BFD_RELOC_X86_64_GOTPCREL64:
7517 case BFD_RELOC_X86_64_GOTPC64:
7518 case BFD_RELOC_X86_64_GOTPLT64:
7519 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 7520 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7521 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 7522 case BFD_RELOC_RVA:
7523 case BFD_RELOC_VTABLE_ENTRY:
7524 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 7525#ifdef TE_PE
7526 case BFD_RELOC_32_SECREL:
7527#endif
252b5132
RH		 7528 code = fixp->fx_r_type;
7529 break;
dbbaec26
L		 7530 case BFD_RELOC_X86_64_32S:
7531 if (!fixp->fx_pcrel)
7532 {
7533 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7534 code = fixp->fx_r_type;
7535 break;
7536 }
252b5132 7537 default:
93382f6d 7538 if (fixp->fx_pcrel)
252b5132 7539 {
93382f6d
AM		 7540 switch (fixp->fx_size)
7541 {
7542 default:
b091f402
AM		 7543 as_bad_where (fixp->fx_file, fixp->fx_line,
7544 _("can not do %d byte pc-relative relocation"),
7545 fixp->fx_size);
93382f6d
AM		 7546 code = BFD_RELOC_32_PCREL;
7547 break;
7548 case 1: code = BFD_RELOC_8_PCREL; break;
7549 case 2: code = BFD_RELOC_16_PCREL; break;
7550 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 7551#ifdef BFD64
7552 case 8: code = BFD_RELOC_64_PCREL; break;
7553#endif
93382f6d
AM		 7554 }
7555 }
7556 else
7557 {
7558 switch (fixp->fx_size)
7559 {
7560 default:
b091f402
AM		 7561 as_bad_where (fixp->fx_file, fixp->fx_line,
7562 _("can not do %d byte relocation"),
7563 fixp->fx_size);
93382f6d
AM		 7564 code = BFD_RELOC_32;
7565 break;
7566 case 1: code = BFD_RELOC_8; break;
7567 case 2: code = BFD_RELOC_16; break;
7568 case 4: code = BFD_RELOC_32; break;
937149dd 7569#ifdef BFD64
3e73aa7c 7570 case 8: code = BFD_RELOC_64; break;
937149dd 7571#endif
93382f6d 7572 }
252b5132
RH		 7573 }
7574 break;
7575 }
252b5132 7576
d182319b
JB		 7577 if ((code == BFD_RELOC_32
7578 || code == BFD_RELOC_32_PCREL
7579 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 7580 && GOT_symbol
7581 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 7582 {
4fa24527 7583 if (!object_64bit)
d6ab8113
JB		 7584 code = BFD_RELOC_386_GOTPC;
7585 else
7586 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 7587 }
7b81dfbb
AJ		 7588 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7589 && GOT_symbol
7590 && fixp->fx_addsy == GOT_symbol)
7591 {
7592 code = BFD_RELOC_X86_64_GOTPC64;
7593 }
252b5132
RH		 7594
7595 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 7596 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7597 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 7598
7599 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 7600
3e73aa7c
JH		 7601 if (!use_rela_relocations)
7602 {
7603 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7604 vtable entry to be used in the relocation's section offset. */
7605 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7606 rel->address = fixp->fx_offset;
252b5132 7607
c6682705 7608 rel->addend = 0;
3e73aa7c
JH		 7609 }
7610 /* Use the rela in 64bit mode. */
252b5132 7611 else
3e73aa7c 7612 {
062cd5e7
AS		 7613 if (!fixp->fx_pcrel)
7614 rel->addend = fixp->fx_offset;
7615 else
7616 switch (code)
7617 {
7618 case BFD_RELOC_X86_64_PLT32:
7619 case BFD_RELOC_X86_64_GOT32:
7620 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 7621 case BFD_RELOC_X86_64_TLSGD:
7622 case BFD_RELOC_X86_64_TLSLD:
7623 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 7624 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7625 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 7626 rel->addend = fixp->fx_offset - fixp->fx_size;
7627 break;
7628 default:
7629 rel->addend = (section->vma
7630 - fixp->fx_size
7631 + fixp->fx_addnumber
7632 + md_pcrel_from (fixp));
7633 break;
7634 }
3e73aa7c
JH		 7635 }
7636
252b5132
RH		 7637 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7638 if (rel->howto == NULL)
7639 {
7640 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 7641 _("cannot represent relocation type %s"),
252b5132
RH		 7642 bfd_get_reloc_code_name (code));
7643 /* Set howto to a garbage value so that we can keep going. */
7644 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7645 assert (rel->howto != NULL);
7646 }
7647
7648 return rel;
7649}
7650
64a0c779
DN		 7651\f
7652/* Parse operands using Intel syntax. This implements a recursive descent
7653 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7654 Programmer's Guide.
7655
7656 FIXME: We do not recognize the full operand grammar defined in the MASM
7657 documentation. In particular, all the structure/union and
7658 high-level macro operands are missing.
7659
7660 Uppercase words are terminals, lower case words are non-terminals.
7661 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7662 bars '|' denote choices. Most grammar productions are implemented in
7663 functions called 'intel_<production>'.
7664
7665 Initial production is 'expr'.
7666
9306ca4a 7667 addOp + | -
64a0c779
DN		 7668
7669 alpha [a-zA-Z]
7670
9306ca4a
JB		 7671 binOp & | AND | \| | OR | ^ | XOR
7672
64a0c779
DN		 7673 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7674
7675 constant digits [[ radixOverride ]]
7676
9306ca4a 7677 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 7678
7679 digits decdigit
b77a7acd
AJ		 7680 | digits decdigit
7681 | digits hexdigit
64a0c779
DN		 7682
7683 decdigit [0-9]
7684
9306ca4a
JB		 7685 e04 e04 addOp e05
7686 | e05
7687
7688 e05 e05 binOp e06
b77a7acd 7689 | e06
64a0c779
DN		 7690
7691 e06 e06 mulOp e09
b77a7acd 7692 | e09
64a0c779
DN		 7693
7694 e09 OFFSET e10
a724f0f4
JB		 7695 | SHORT e10
7696 | + e10
7697 | - e10
9306ca4a
JB		 7698 | ~ e10
7699 | NOT e10
64a0c779
DN		 7700 | e09 PTR e10
7701 | e09 : e10
7702 | e10
7703
7704 e10 e10 [ expr ]
b77a7acd 7705 | e11
64a0c779
DN		 7706
7707 e11 ( expr )
b77a7acd 7708 | [ expr ]
64a0c779
DN		 7709 | constant
7710 | dataType
7711 | id
7712 | $
7713 | register
7714
a724f0f4 7715 => expr expr cmpOp e04
9306ca4a 7716 | e04
64a0c779
DN		 7717
7718 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 7719 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 7720
7721 hexdigit a | b | c | d | e | f
b77a7acd 7722 | A | B | C | D | E | F
64a0c779
DN		 7723
7724 id alpha
b77a7acd 7725 | id alpha
64a0c779
DN		 7726 | id decdigit
7727
9306ca4a 7728 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 7729
7730 quote " | '
7731
7732 register specialRegister
b77a7acd 7733 | gpRegister
64a0c779
DN		 7734 | byteRegister
7735
7736 segmentRegister CS | DS | ES | FS | GS | SS
7737
9306ca4a 7738 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 7739 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 7740 | TR3 | TR4 | TR5 | TR6 | TR7
7741
64a0c779
DN		 7742 We simplify the grammar in obvious places (e.g., register parsing is
7743 done by calling parse_register) and eliminate immediate left recursion
7744 to implement a recursive-descent parser.
7745
a724f0f4
JB		 7746 expr e04 expr'
7747
7748 expr' cmpOp e04 expr'
7749 | Empty
9306ca4a
JB		 7750
7751 e04 e05 e04'
7752
7753 e04' addOp e05 e04'
7754 | Empty
64a0c779
DN		 7755
7756 e05 e06 e05'
7757
9306ca4a 7758 e05' binOp e06 e05'
b77a7acd 7759 | Empty
64a0c779
DN		 7760
7761 e06 e09 e06'
7762
7763 e06' mulOp e09 e06'
b77a7acd 7764 | Empty
64a0c779
DN		 7765
7766 e09 OFFSET e10 e09'
a724f0f4
JB		 7767 | SHORT e10'
7768 | + e10'
7769 | - e10'
7770 | ~ e10'
7771 | NOT e10'
b77a7acd 7772 | e10 e09'
64a0c779
DN		 7773
7774 e09' PTR e10 e09'
b77a7acd 7775 | : e10 e09'
64a0c779
DN		 7776 | Empty
7777
7778 e10 e11 e10'
7779
7780 e10' [ expr ] e10'
b77a7acd 7781 | Empty
64a0c779
DN		 7782
7783 e11 ( expr )
b77a7acd 7784 | [ expr ]
64a0c779
DN		 7785 | BYTE
7786 | WORD
7787 | DWORD
9306ca4a 7788 | FWORD
64a0c779 7789 | QWORD
9306ca4a
JB		 7790 | TBYTE
7791 | OWORD
7792 | XMMWORD
64a0c779
DN		 7793 | .
7794 | $
7795 | register
7796 | id
7797 | constant */
7798
7799/* Parsing structure for the intel syntax parser. Used to implement the
7800 semantic actions for the operand grammar. */
7801struct intel_parser_s
7802 {
7803 char *op_string; /* The string being parsed. */
7804 int got_a_float; /* Whether the operand is a float. */
4a1805b1 7805 int op_modifier; /* Operand modifier. */
64a0c779 7806 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 7807 int in_offset; /* >=1 if parsing operand of offset. */
7808 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 7809 const reg_entry *reg; /* Last register reference found. */
7810 char *disp; /* Displacement string being built. */
a724f0f4 7811 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 7812 };
7813
7814static struct intel_parser_s intel_parser;
7815
7816/* Token structure for parsing intel syntax. */
7817struct intel_token
7818 {
7819 int code; /* Token code. */
7820 const reg_entry *reg; /* Register entry for register tokens. */
7821 char *str; /* String representation. */
7822 };
7823
7824static struct intel_token cur_token, prev_token;
7825
50705ef4
AM		 7826/* Token codes for the intel parser. Since T_SHORT is already used
7827 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 7828#define T_NIL -1
7829#define T_CONST 1
7830#define T_REG 2
7831#define T_BYTE 3
7832#define T_WORD 4
9306ca4a
JB		 7833#define T_DWORD 5
7834#define T_FWORD 6
7835#define T_QWORD 7
7836#define T_TBYTE 8
7837#define T_XMMWORD 9
50705ef4 7838#undef T_SHORT
9306ca4a
JB		 7839#define T_SHORT 10
7840#define T_OFFSET 11
7841#define T_PTR 12
7842#define T_ID 13
7843#define T_SHL 14
7844#define T_SHR 15
64a0c779
DN		 7845
7846/* Prototypes for intel parser functions. */
e3bb37b5
L		 7847static int intel_match_token (int);
7848static void intel_putback_token (void);
7849static void intel_get_token (void);
7850static int intel_expr (void);
7851static int intel_e04 (void);
7852static int intel_e05 (void);
7853static int intel_e06 (void);
7854static int intel_e09 (void);
7855static int intel_e10 (void);
7856static int intel_e11 (void);
64a0c779 7857
64a0c779 7858static int
e3bb37b5 7859i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 7860{
7861 int ret;
7862 char *p;
7863
a724f0f4
JB		 7864 p = intel_parser.op_string = xstrdup (operand_string);
7865 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
7866
7867 for (;;)
64a0c779 7868 {
a724f0f4
JB		 7869 /* Initialize token holders. */
7870 cur_token.code = prev_token.code = T_NIL;
7871 cur_token.reg = prev_token.reg = NULL;
7872 cur_token.str = prev_token.str = NULL;
7873
7874 /* Initialize parser structure. */
7875 intel_parser.got_a_float = got_a_float;
7876 intel_parser.op_modifier = 0;
7877 intel_parser.is_mem = 0;
7878 intel_parser.in_offset = 0;
7879 intel_parser.in_bracket = 0;
7880 intel_parser.reg = NULL;
7881 intel_parser.disp[0] = '\0';
7882 intel_parser.next_operand = NULL;
7883
7884 /* Read the first token and start the parser. */
7885 intel_get_token ();
7886 ret = intel_expr ();
7887
7888 if (!ret)
7889 break;
7890
9306ca4a
JB		 7891 if (cur_token.code != T_NIL)
7892 {
7893 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7894 current_templates->start->name, cur_token.str);
7895 ret = 0;
7896 }
64a0c779
DN		 7897 /* If we found a memory reference, hand it over to i386_displacement
7898 to fill in the rest of the operand fields. */
9306ca4a 7899 else if (intel_parser.is_mem)
64a0c779
DN		 7900 {
7901 if ((i.mem_operands == 1
40fb9820 7902 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 7903 || i.mem_operands == 2)
7904 {
7905 as_bad (_("too many memory references for '%s'"),
7906 current_templates->start->name);
7907 ret = 0;
7908 }
7909 else
7910 {
7911 char *s = intel_parser.disp;
5c07affc 7912 i.types[this_operand].bitfield.mem = 1;
64a0c779
DN		 7913 i.mem_operands++;
7914
a724f0f4
JB		 7915 if (!quiet_warnings && intel_parser.is_mem < 0)
7916 /* See the comments in intel_bracket_expr. */
7917 as_warn (_("Treating `%s' as memory reference"), operand_string);
7918
64a0c779
DN		 7919 /* Add the displacement expression. */
7920 if (*s != '\0')
a4622f40
AM		 7921 ret = i386_displacement (s, s + strlen (s));
7922 if (ret)
a724f0f4
JB		 7923 {
7924 /* Swap base and index in 16-bit memory operands like
7925 [si+bx]. Since i386_index_check is also used in AT&T
7926 mode we have to do that here. */
7927 if (i.base_reg
7928 && i.index_reg
40fb9820
L		 7929 && i.base_reg->reg_type.bitfield.reg16
7930 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 7931 && i.base_reg->reg_num >= 6
7932 && i.index_reg->reg_num < 6)
7933 {
7934 const reg_entry *base = i.index_reg;
7935
7936 i.index_reg = i.base_reg;
7937 i.base_reg = base;
7938 }
7939 ret = i386_index_check (operand_string);
7940 }
64a0c779
DN		 7941 }
7942 }
7943
7944 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 7945 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 7946 || intel_parser.reg == NULL)
7947 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 7948
7949 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 7950 ret = 0;
a724f0f4
JB		 7951 if (!ret || !intel_parser.next_operand)
7952 break;
7953 intel_parser.op_string = intel_parser.next_operand;
7954 this_operand = i.operands++;
7d5e4556 7955 i.types[this_operand].bitfield.unspecified = 1;
64a0c779
DN		 7956 }
7957
7958 free (p);
7959 free (intel_parser.disp);
7960
7961 return ret;
7962}
7963
a724f0f4
JB		 7964#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7965
7966/* expr e04 expr'
7967
7968 expr' cmpOp e04 expr'
7969 | Empty */
64a0c779 7970static int
e3bb37b5 7971intel_expr (void)
64a0c779 7972{
a724f0f4
JB		 7973 /* XXX Implement the comparison operators. */
7974 return intel_e04 ();
9306ca4a
JB		 7975}
7976
a724f0f4 7977/* e04 e05 e04'
9306ca4a 7978
a724f0f4 7979 e04' addOp e05 e04'
9306ca4a
JB		 7980 | Empty */
7981static int
e3bb37b5 7982intel_e04 (void)
9306ca4a 7983{
a724f0f4 7984 int nregs = -1;
9306ca4a 7985
a724f0f4 7986 for (;;)
9306ca4a 7987 {
a724f0f4
JB		 7988 if (!intel_e05())
7989 return 0;
9306ca4a 7990
a724f0f4
JB		 7991 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7992 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 7993
a724f0f4
JB		 7994 if (cur_token.code == '+')
7995 nregs = -1;
7996 else if (cur_token.code == '-')
7997 nregs = NUM_ADDRESS_REGS;
7998 else
7999 return 1;
64a0c779 8000
a724f0f4
JB		 8001 strcat (intel_parser.disp, cur_token.str);
8002 intel_match_token (cur_token.code);
8003 }
64a0c779
DN		 8004}
8005
64a0c779
DN		 8006/* e05 e06 e05'
8007
9306ca4a 8008 e05' binOp e06 e05'
64a0c779
DN		 8009 | Empty */
8010static int
e3bb37b5 8011intel_e05 (void)
64a0c779 8012{
a724f0f4 8013 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 8014
a724f0f4 8015 for (;;)
64a0c779 8016 {
a724f0f4
JB		 8017 if (!intel_e06())
8018 return 0;
8019
4eed87de
AM		 8020 if (cur_token.code == '&'
8021 || cur_token.code == '|'
8022 || cur_token.code == '^')
a724f0f4
JB		 8023 {
8024 char str[2];
8025
8026 str[0] = cur_token.code;
8027 str[1] = 0;
8028 strcat (intel_parser.disp, str);
8029 }
8030 else
8031 break;
9306ca4a 8032
64a0c779
DN		 8033 intel_match_token (cur_token.code);
8034
a724f0f4
JB		 8035 if (nregs < 0)
8036 nregs = ~nregs;
64a0c779 8037 }
a724f0f4
JB		 8038 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8039 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
8040 return 1;
4a1805b1 8041}
64a0c779
DN		 8042
8043/* e06 e09 e06'
8044
8045 e06' mulOp e09 e06'
b77a7acd 8046 | Empty */
64a0c779 8047static int
e3bb37b5 8048intel_e06 (void)
64a0c779 8049{
a724f0f4 8050 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 8051
a724f0f4 8052 for (;;)
64a0c779 8053 {
a724f0f4
JB		 8054 if (!intel_e09())
8055 return 0;
9306ca4a 8056
4eed87de
AM		 8057 if (cur_token.code == '*'
8058 || cur_token.code == '/'
8059 || cur_token.code == '%')
a724f0f4
JB		 8060 {
8061 char str[2];
9306ca4a 8062
a724f0f4
JB		 8063 str[0] = cur_token.code;
8064 str[1] = 0;
8065 strcat (intel_parser.disp, str);
8066 }
8067 else if (cur_token.code == T_SHL)
8068 strcat (intel_parser.disp, "<<");
8069 else if (cur_token.code == T_SHR)
8070 strcat (intel_parser.disp, ">>");
8071 else
8072 break;
9306ca4a 8073
64e74474 8074 intel_match_token (cur_token.code);
64a0c779 8075
a724f0f4
JB		 8076 if (nregs < 0)
8077 nregs = ~nregs;
64a0c779 8078 }
a724f0f4
JB		 8079 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8080 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8081 return 1;
64a0c779
DN		 8082}
8083
a724f0f4
JB		 8084/* e09 OFFSET e09
8085 | SHORT e09
8086 | + e09
8087 | - e09
8088 | ~ e09
8089 | NOT e09
9306ca4a
JB		 8090 | e10 e09'
8091
64a0c779 8092 e09' PTR e10 e09'
b77a7acd 8093 | : e10 e09'
64a0c779
DN		 8094 | Empty */
8095static int
e3bb37b5 8096intel_e09 (void)
64a0c779 8097{
a724f0f4
JB		 8098 int nregs = ~NUM_ADDRESS_REGS;
8099 int in_offset = 0;
8100
8101 for (;;)
64a0c779 8102 {
a724f0f4
JB		 8103 /* Don't consume constants here. */
8104 if (cur_token.code == '+' || cur_token.code == '-')
8105 {
8106 /* Need to look one token ahead - if the next token
8107 is a constant, the current token is its sign. */
8108 int next_code;
8109
8110 intel_match_token (cur_token.code);
8111 next_code = cur_token.code;
8112 intel_putback_token ();
8113 if (next_code == T_CONST)
8114 break;
8115 }
8116
8117 /* e09 OFFSET e09 */
8118 if (cur_token.code == T_OFFSET)
8119 {
8120 if (!in_offset++)
8121 ++intel_parser.in_offset;
8122 }
8123
8124 /* e09 SHORT e09 */
8125 else if (cur_token.code == T_SHORT)
8126 intel_parser.op_modifier |= 1 << T_SHORT;
8127
8128 /* e09 + e09 */
8129 else if (cur_token.code == '+')
8130 strcat (intel_parser.disp, "+");
8131
8132 /* e09 - e09
8133 | ~ e09
8134 | NOT e09 */
8135 else if (cur_token.code == '-' || cur_token.code == '~')
8136 {
8137 char str[2];
64a0c779 8138
a724f0f4
JB		 8139 if (nregs < 0)
8140 nregs = ~nregs;
8141 str[0] = cur_token.code;
8142 str[1] = 0;
8143 strcat (intel_parser.disp, str);
8144 }
8145
8146 /* e09 e10 e09' */
8147 else
8148 break;
8149
8150 intel_match_token (cur_token.code);
64a0c779
DN		 8151 }
8152
a724f0f4 8153 for (;;)
9306ca4a 8154 {
a724f0f4
JB		 8155 if (!intel_e10 ())
8156 return 0;
9306ca4a 8157
a724f0f4
JB		 8158 /* e09' PTR e10 e09' */
8159 if (cur_token.code == T_PTR)
8160 {
8161 char suffix;
9306ca4a 8162
a724f0f4 8163 if (prev_token.code == T_BYTE)
7d5e4556
L		 8164 {
8165 suffix = BYTE_MNEM_SUFFIX;
8166 i.types[this_operand].bitfield.byte = 1;
8167 }
9306ca4a 8168
a724f0f4
JB		 8169 else if (prev_token.code == T_WORD)
8170 {
8171 if (current_templates->start->name[0] == 'l'
8172 && current_templates->start->name[2] == 's'
8173 && current_templates->start->name[3] == 0)
8174 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8175 else if (intel_parser.got_a_float == 2) /* "fi..." */
8176 suffix = SHORT_MNEM_SUFFIX;
8177 else
8178 suffix = WORD_MNEM_SUFFIX;
7d5e4556 8179 i.types[this_operand].bitfield.word = 1;
a724f0f4 8180 }
64a0c779 8181
a724f0f4
JB		 8182 else if (prev_token.code == T_DWORD)
8183 {
8184 if (current_templates->start->name[0] == 'l'
8185 && current_templates->start->name[2] == 's'
8186 && current_templates->start->name[3] == 0)
8187 suffix = WORD_MNEM_SUFFIX;
8188 else if (flag_code == CODE_16BIT
40fb9820
L		 8189 && (current_templates->start->opcode_modifier.jump
8190 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 8191 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8192 else if (intel_parser.got_a_float == 1) /* "f..." */
8193 suffix = SHORT_MNEM_SUFFIX;
8194 else
8195 suffix = LONG_MNEM_SUFFIX;
7d5e4556 8196 i.types[this_operand].bitfield.dword = 1;
a724f0f4 8197 }
9306ca4a 8198
a724f0f4
JB		 8199 else if (prev_token.code == T_FWORD)
8200 {
8201 if (current_templates->start->name[0] == 'l'
8202 && current_templates->start->name[2] == 's'
8203 && current_templates->start->name[3] == 0)
8204 suffix = LONG_MNEM_SUFFIX;
8205 else if (!intel_parser.got_a_float)
8206 {
8207 if (flag_code == CODE_16BIT)
8208 add_prefix (DATA_PREFIX_OPCODE);
8209 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8210 }
8211 else
8212 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7d5e4556 8213 i.types[this_operand].bitfield.fword = 1;
a724f0f4 8214 }
64a0c779 8215
a724f0f4
JB		 8216 else if (prev_token.code == T_QWORD)
8217 {
8218 if (intel_parser.got_a_float == 1) /* "f..." */
8219 suffix = LONG_MNEM_SUFFIX;
8220 else
7d5e4556
L		 8221 suffix = QWORD_MNEM_SUFFIX;
8222 i.types[this_operand].bitfield.qword = 1;
a724f0f4 8223 }
64a0c779 8224
a724f0f4
JB		 8225 else if (prev_token.code == T_TBYTE)
8226 {
8227 if (intel_parser.got_a_float == 1)
8228 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8229 else
8230 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8231 }
9306ca4a 8232
a724f0f4 8233 else if (prev_token.code == T_XMMWORD)
9306ca4a 8234 {
582d5edd 8235 suffix = XMMWORD_MNEM_SUFFIX;
7d5e4556 8236 i.types[this_operand].bitfield.xmmword = 1;
9306ca4a 8237 }
64a0c779 8238
f16b83df 8239 else
a724f0f4
JB		 8240 {
8241 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8242 return 0;
8243 }
8244
7d5e4556
L		 8245 i.types[this_operand].bitfield.unspecified = 0;
8246
435acd52
JB		 8247 /* Operands for jump/call using 'ptr' notation denote absolute
8248 addresses. */
40fb9820
L		 8249 if (current_templates->start->opcode_modifier.jump
8250 || current_templates->start->opcode_modifier.jumpdword)
8251 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8252
a724f0f4
JB		 8253 if (current_templates->start->base_opcode == 0x8d /* lea */)
8254 ;
8255 else if (!i.suffix)
8256 i.suffix = suffix;
8257 else if (i.suffix != suffix)
8258 {
8259 as_bad (_("Conflicting operand modifiers"));
8260 return 0;
8261 }
64a0c779 8262
9306ca4a
JB		 8263 }
8264
a724f0f4
JB		 8265 /* e09' : e10 e09' */
8266 else if (cur_token.code == ':')
9306ca4a 8267 {
a724f0f4
JB		 8268 if (prev_token.code != T_REG)
8269 {
8270 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8271 segment/group identifier (which we don't have), using comma
8272 as the operand separator there is even less consistent, since
8273 there all branches only have a single operand. */
8274 if (this_operand != 0
8275 || intel_parser.in_offset
8276 || intel_parser.in_bracket
40fb9820
L		 8277 || (!current_templates->start->opcode_modifier.jump
8278 && !current_templates->start->opcode_modifier.jumpdword
8279 && !current_templates->start->opcode_modifier.jumpintersegment
8280 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 8281 return intel_match_token (T_NIL);
8282 /* Remember the start of the 2nd operand and terminate 1st
8283 operand here.
8284 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8285 another expression), but it gets at least the simplest case
8286 (a plain number or symbol on the left side) right. */
8287 intel_parser.next_operand = intel_parser.op_string;
8288 *--intel_parser.op_string = '\0';
8289 return intel_match_token (':');
8290 }
9306ca4a 8291 }
64a0c779 8292
a724f0f4 8293 /* e09' Empty */
64a0c779 8294 else
a724f0f4 8295 break;
64a0c779 8296
a724f0f4
JB		 8297 intel_match_token (cur_token.code);
8298
8299 }
8300
8301 if (in_offset)
8302 {
8303 --intel_parser.in_offset;
8304 if (nregs < 0)
8305 nregs = ~nregs;
8306 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 8307 {
a724f0f4 8308 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 8309 return 0;
8310 }
a724f0f4
JB		 8311 intel_parser.op_modifier |= 1 << T_OFFSET;
8312 }
9306ca4a 8313
a724f0f4
JB		 8314 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8315 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8316 return 1;
8317}
64a0c779 8318
a724f0f4 8319static int
e3bb37b5 8320intel_bracket_expr (void)
a724f0f4
JB		 8321{
8322 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8323 const char *start = intel_parser.op_string;
8324 int len;
8325
8326 if (i.op[this_operand].regs)
8327 return intel_match_token (T_NIL);
8328
8329 intel_match_token ('[');
8330
8331 /* Mark as a memory operand only if it's not already known to be an
8332 offset expression. If it's an offset expression, we need to keep
8333 the brace in. */
8334 if (!intel_parser.in_offset)
8335 {
8336 ++intel_parser.in_bracket;
435acd52
JB		 8337
8338 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 8339 if (current_templates->start->opcode_modifier.jump
8340 || current_templates->start->opcode_modifier.jumpdword)
8341 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8342
a724f0f4
JB		 8343 /* Unfortunately gas always diverged from MASM in a respect that can't
8344 be easily fixed without risking to break code sequences likely to be
8345 encountered (the testsuite even check for this): MASM doesn't consider
8346 an expression inside brackets unconditionally as a memory reference.
8347 When that is e.g. a constant, an offset expression, or the sum of the
8348 two, this is still taken as a constant load. gas, however, always
8349 treated these as memory references. As a compromise, we'll try to make
8350 offset expressions inside brackets work the MASM way (since that's
8351 less likely to be found in real world code), but make constants alone
8352 continue to work the traditional gas way. In either case, issue a
8353 warning. */
8354 intel_parser.op_modifier &= ~was_offset;
64a0c779 8355 }
a724f0f4 8356 else
64e74474 8357 strcat (intel_parser.disp, "[");
a724f0f4
JB		 8358
8359 /* Add a '+' to the displacement string if necessary. */
8360 if (*intel_parser.disp != '\0'
8361 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8362 strcat (intel_parser.disp, "+");
64a0c779 8363
a724f0f4
JB		 8364 if (intel_expr ()
8365 && (len = intel_parser.op_string - start - 1,
8366 intel_match_token (']')))
64a0c779 8367 {
a724f0f4
JB		 8368 /* Preserve brackets when the operand is an offset expression. */
8369 if (intel_parser.in_offset)
8370 strcat (intel_parser.disp, "]");
8371 else
8372 {
8373 --intel_parser.in_bracket;
8374 if (i.base_reg || i.index_reg)
8375 intel_parser.is_mem = 1;
8376 if (!intel_parser.is_mem)
8377 {
8378 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8379 /* Defer the warning until all of the operand was parsed. */
8380 intel_parser.is_mem = -1;
8381 else if (!quiet_warnings)
4eed87de
AM		 8382 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8383 len, start, len, start);
a724f0f4
JB		 8384 }
8385 }
8386 intel_parser.op_modifier |= was_offset;
64a0c779 8387
a724f0f4 8388 return 1;
64a0c779 8389 }
a724f0f4 8390 return 0;
64a0c779
DN		 8391}
8392
8393/* e10 e11 e10'
8394
8395 e10' [ expr ] e10'
b77a7acd 8396 | Empty */
64a0c779 8397static int
e3bb37b5 8398intel_e10 (void)
64a0c779 8399{
a724f0f4
JB		 8400 if (!intel_e11 ())
8401 return 0;
64a0c779 8402
a724f0f4 8403 while (cur_token.code == '[')
64a0c779 8404 {
a724f0f4 8405 if (!intel_bracket_expr ())
21d6c4af 8406 return 0;
64a0c779
DN		 8407 }
8408
a724f0f4 8409 return 1;
64a0c779
DN		 8410}
8411
64a0c779 8412/* e11 ( expr )
b77a7acd 8413 | [ expr ]
64a0c779
DN		 8414 | BYTE
8415 | WORD
8416 | DWORD
9306ca4a 8417 | FWORD
64a0c779 8418 | QWORD
9306ca4a
JB		 8419 | TBYTE
8420 | OWORD
8421 | XMMWORD
4a1805b1 8422 | $
64a0c779
DN		 8423 | .
8424 | register
8425 | id
8426 | constant */
8427static int
e3bb37b5 8428intel_e11 (void)
64a0c779 8429{
a724f0f4 8430 switch (cur_token.code)
64a0c779 8431 {
a724f0f4
JB		 8432 /* e11 ( expr ) */
8433 case '(':
64a0c779
DN		 8434 intel_match_token ('(');
8435 strcat (intel_parser.disp, "(");
8436
8437 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 8438 {
8439 strcat (intel_parser.disp, ")");
8440 return 1;
8441 }
a724f0f4 8442 return 0;
4a1805b1 8443
a724f0f4
JB		 8444 /* e11 [ expr ] */
8445 case '[':
a724f0f4 8446 return intel_bracket_expr ();
64a0c779 8447
a724f0f4
JB		 8448 /* e11 $
8449 | . */
8450 case '.':
64a0c779
DN		 8451 strcat (intel_parser.disp, cur_token.str);
8452 intel_match_token (cur_token.code);
21d6c4af
DN		 8453
8454 /* Mark as a memory operand only if it's not already known to be an
8455 offset expression. */
a724f0f4 8456 if (!intel_parser.in_offset)
21d6c4af 8457 intel_parser.is_mem = 1;
64a0c779
DN		 8458
8459 return 1;
64a0c779 8460
a724f0f4
JB		 8461 /* e11 register */
8462 case T_REG:
8463 {
8464 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 8465
a724f0f4 8466 intel_match_token (T_REG);
64a0c779 8467
a724f0f4
JB		 8468 /* Check for segment change. */
8469 if (cur_token.code == ':')
8470 {
40fb9820
L		 8471 if (!reg->reg_type.bitfield.sreg2
8472 && !reg->reg_type.bitfield.sreg3)
a724f0f4 8473 {
4eed87de
AM		 8474 as_bad (_("`%s' is not a valid segment register"),
8475 reg->reg_name);
a724f0f4
JB		 8476 return 0;
8477 }
8478 else if (i.seg[i.mem_operands])
8479 as_warn (_("Extra segment override ignored"));
8480 else
8481 {
8482 if (!intel_parser.in_offset)
8483 intel_parser.is_mem = 1;
8484 switch (reg->reg_num)
8485 {
8486 case 0:
8487 i.seg[i.mem_operands] = &es;
8488 break;
8489 case 1:
8490 i.seg[i.mem_operands] = &cs;
8491 break;
8492 case 2:
8493 i.seg[i.mem_operands] = &ss;
8494 break;
8495 case 3:
8496 i.seg[i.mem_operands] = &ds;
8497 break;
8498 case 4:
8499 i.seg[i.mem_operands] = &fs;
8500 break;
8501 case 5:
8502 i.seg[i.mem_operands] = &gs;
8503 break;
8504 }
8505 }
8506 }
64a0c779 8507
a724f0f4
JB		 8508 /* Not a segment register. Check for register scaling. */
8509 else if (cur_token.code == '*')
8510 {
8511 if (!intel_parser.in_bracket)
8512 {
8513 as_bad (_("Register scaling only allowed in memory operands"));
8514 return 0;
8515 }
64a0c779 8516
40fb9820 8517 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 8518 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8519 else if (i.index_reg)
8520 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 8521
a724f0f4
JB		 8522 /* What follows must be a valid scale. */
8523 intel_match_token ('*');
8524 i.index_reg = reg;
40fb9820 8525 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 8526
a724f0f4
JB		 8527 /* Set the scale after setting the register (otherwise,
8528 i386_scale will complain) */
8529 if (cur_token.code == '+' || cur_token.code == '-')
8530 {
8531 char *str, sign = cur_token.code;
8532 intel_match_token (cur_token.code);
8533 if (cur_token.code != T_CONST)
8534 {
8535 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8536 cur_token.str);
8537 return 0;
8538 }
8539 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8540 strcpy (str + 1, cur_token.str);
8541 *str = sign;
8542 if (!i386_scale (str))
8543 return 0;
8544 free (str);
8545 }
8546 else if (!i386_scale (cur_token.str))
64a0c779 8547 return 0;
a724f0f4
JB		 8548 intel_match_token (cur_token.code);
8549 }
64a0c779 8550
a724f0f4
JB		 8551 /* No scaling. If this is a memory operand, the register is either a
8552 base register (first occurrence) or an index register (second
8553 occurrence). */
7b0441f6 8554 else if (intel_parser.in_bracket)
a724f0f4 8555 {
64a0c779 8556
a724f0f4
JB		 8557 if (!i.base_reg)
8558 i.base_reg = reg;
8559 else if (!i.index_reg)
8560 i.index_reg = reg;
8561 else
8562 {
8563 as_bad (_("Too many register references in memory operand"));
8564 return 0;
8565 }
64a0c779 8566
40fb9820 8567 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 8568 }
4a1805b1 8569
4d1bb795
JB		 8570 /* It's neither base nor index. */
8571 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 8572 {
40fb9820
L		 8573 i386_operand_type temp = reg->reg_type;
8574 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8575 i.types[this_operand] = operand_type_or (i.types[this_operand],
8576 temp);
7d5e4556 8577 i.types[this_operand].bitfield.unspecified = 0;
a724f0f4
JB		 8578 i.op[this_operand].regs = reg;
8579 i.reg_operands++;
8580 }
8581 else
8582 {
8583 as_bad (_("Invalid use of register"));
8584 return 0;
8585 }
64a0c779 8586
a724f0f4
JB		 8587 /* Since registers are not part of the displacement string (except
8588 when we're parsing offset operands), we may need to remove any
8589 preceding '+' from the displacement string. */
8590 if (*intel_parser.disp != '\0'
8591 && !intel_parser.in_offset)
8592 {
8593 char *s = intel_parser.disp;
8594 s += strlen (s) - 1;
8595 if (*s == '+')
8596 *s = '\0';
8597 }
4a1805b1 8598
a724f0f4
JB		 8599 return 1;
8600 }
8601
8602 /* e11 BYTE
8603 | WORD
8604 | DWORD
8605 | FWORD
8606 | QWORD
8607 | TBYTE
8608 | OWORD
8609 | XMMWORD */
8610 case T_BYTE:
8611 case T_WORD:
8612 case T_DWORD:
8613 case T_FWORD:
8614 case T_QWORD:
8615 case T_TBYTE:
8616 case T_XMMWORD:
8617 intel_match_token (cur_token.code);
64a0c779 8618
a724f0f4
JB		 8619 if (cur_token.code == T_PTR)
8620 return 1;
8621
8622 /* It must have been an identifier. */
8623 intel_putback_token ();
8624 cur_token.code = T_ID;
8625 /* FALLTHRU */
8626
8627 /* e11 id
8628 | constant */
8629 case T_ID:
8630 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 8631 {
8632 symbolS *symbolP;
8633
a724f0f4
JB		 8634 /* The identifier represents a memory reference only if it's not
8635 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 8636 symbolP = symbol_find(cur_token.str);
8637 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8638 intel_parser.is_mem = 1;
8639 }
a724f0f4 8640 /* FALLTHRU */
64a0c779 8641
a724f0f4
JB		 8642 case T_CONST:
8643 case '-':
8644 case '+':
8645 {
8646 char *save_str, sign = 0;
64a0c779 8647
a724f0f4
JB		 8648 /* Allow constants that start with `+' or `-'. */
8649 if (cur_token.code == '-' || cur_token.code == '+')
8650 {
8651 sign = cur_token.code;
8652 intel_match_token (cur_token.code);
8653 if (cur_token.code != T_CONST)
8654 {
8655 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8656 cur_token.str);
8657 return 0;
8658 }
8659 }
64a0c779 8660
a724f0f4
JB		 8661 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8662 strcpy (save_str + !!sign, cur_token.str);
8663 if (sign)
8664 *save_str = sign;
64a0c779 8665
a724f0f4
JB		 8666 /* Get the next token to check for register scaling. */
8667 intel_match_token (cur_token.code);
64a0c779 8668
4eed87de
AM		 8669 /* Check if this constant is a scaling factor for an
8670 index register. */
a724f0f4
JB		 8671 if (cur_token.code == '*')
8672 {
8673 if (intel_match_token ('*') && cur_token.code == T_REG)
8674 {
8675 const reg_entry *reg = cur_token.reg;
8676
8677 if (!intel_parser.in_bracket)
8678 {
4eed87de
AM		 8679 as_bad (_("Register scaling only allowed "
8680 "in memory operands"));
a724f0f4
JB		 8681 return 0;
8682 }
8683
4eed87de
AM		 8684 /* Disallow things like [1*si].
8685 sp and esp are invalid as index. */
40fb9820 8686 if (reg->reg_type.bitfield.reg16)
4eed87de 8687 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 8688 else if (i.index_reg)
4eed87de 8689 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 8690
8691 /* The constant is followed by `* reg', so it must be
8692 a valid scale. */
8693 i.index_reg = reg;
40fb9820 8694 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 8695
8696 /* Set the scale after setting the register (otherwise,
8697 i386_scale will complain) */
8698 if (!i386_scale (save_str))
64a0c779 8699 return 0;
a724f0f4
JB		 8700 intel_match_token (T_REG);
8701
8702 /* Since registers are not part of the displacement
8703 string, we may need to remove any preceding '+' from
8704 the displacement string. */
8705 if (*intel_parser.disp != '\0')
8706 {
8707 char *s = intel_parser.disp;
8708 s += strlen (s) - 1;
8709 if (*s == '+')
8710 *s = '\0';
8711 }
8712
8713 free (save_str);
8714
8715 return 1;
8716 }
64a0c779 8717
a724f0f4
JB		 8718 /* The constant was not used for register scaling. Since we have
8719 already consumed the token following `*' we now need to put it
8720 back in the stream. */
64a0c779 8721 intel_putback_token ();
a724f0f4 8722 }
64a0c779 8723
a724f0f4
JB		 8724 /* Add the constant to the displacement string. */
8725 strcat (intel_parser.disp, save_str);
8726 free (save_str);
64a0c779 8727
a724f0f4
JB		 8728 return 1;
8729 }
64a0c779
DN		 8730 }
8731
64a0c779
DN		 8732 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8733 return 0;
8734}
8735
64a0c779
DN		 8736/* Match the given token against cur_token. If they match, read the next
8737 token from the operand string. */
8738static int
e3bb37b5 8739intel_match_token (int code)
64a0c779
DN		 8740{
8741 if (cur_token.code == code)
8742 {
8743 intel_get_token ();
8744 return 1;
8745 }
8746 else
8747 {
0477af35 8748 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 8749 return 0;
8750 }
8751}
8752
64a0c779
DN		 8753/* Read a new token from intel_parser.op_string and store it in cur_token. */
8754static void
e3bb37b5 8755intel_get_token (void)
64a0c779
DN		 8756{
8757 char *end_op;
8758 const reg_entry *reg;
8759 struct intel_token new_token;
8760
8761 new_token.code = T_NIL;
8762 new_token.reg = NULL;
8763 new_token.str = NULL;
8764
4a1805b1 8765 /* Free the memory allocated to the previous token and move
64a0c779
DN		 8766 cur_token to prev_token. */
8767 if (prev_token.str)
8768 free (prev_token.str);
8769
8770 prev_token = cur_token;
8771
8772 /* Skip whitespace. */
8773 while (is_space_char (*intel_parser.op_string))
8774 intel_parser.op_string++;
8775
8776 /* Return an empty token if we find nothing else on the line. */
8777 if (*intel_parser.op_string == '\0')
8778 {
8779 cur_token = new_token;
8780 return;
8781 }
8782
8783 /* The new token cannot be larger than the remainder of the operand
8784 string. */
a724f0f4 8785 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 8786 new_token.str[0] = '\0';
8787
8788 if (strchr ("0123456789", *intel_parser.op_string))
8789 {
8790 char *p = new_token.str;
8791 char *q = intel_parser.op_string;
8792 new_token.code = T_CONST;
8793
8794 /* Allow any kind of identifier char to encompass floating point and
8795 hexadecimal numbers. */
8796 while (is_identifier_char (*q))
8797 *p++ = *q++;
8798 *p = '\0';
8799
8800 /* Recognize special symbol names [0-9][bf]. */
8801 if (strlen (intel_parser.op_string) == 2
4a1805b1 8802 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 8803 || intel_parser.op_string[1] == 'f'))
8804 new_token.code = T_ID;
8805 }
8806
4d1bb795 8807 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 8808 {
4d1bb795
JB		 8809 size_t len = end_op - intel_parser.op_string;
8810
64a0c779
DN		 8811 new_token.code = T_REG;
8812 new_token.reg = reg;
8813
4d1bb795
JB		 8814 memcpy (new_token.str, intel_parser.op_string, len);
8815 new_token.str[len] = '\0';
64a0c779
DN		 8816 }
8817
8818 else if (is_identifier_char (*intel_parser.op_string))
8819 {
8820 char *p = new_token.str;
8821 char *q = intel_parser.op_string;
8822
8823 /* A '.' or '$' followed by an identifier char is an identifier.
8824 Otherwise, it's operator '.' followed by an expression. */
8825 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
8826 {
9306ca4a
JB		 8827 new_token.code = '.';
8828 new_token.str[0] = '.';
64a0c779
DN		 8829 new_token.str[1] = '\0';
8830 }
8831 else
8832 {
8833 while (is_identifier_char (*q) || *q == '@')
8834 *p++ = *q++;
8835 *p = '\0';
8836
9306ca4a
JB		 8837 if (strcasecmp (new_token.str, "NOT") == 0)
8838 new_token.code = '~';
8839
8840 else if (strcasecmp (new_token.str, "MOD") == 0)
8841 new_token.code = '%';
8842
8843 else if (strcasecmp (new_token.str, "AND") == 0)
8844 new_token.code = '&';
8845
8846 else if (strcasecmp (new_token.str, "OR") == 0)
8847 new_token.code = '|';
8848
8849 else if (strcasecmp (new_token.str, "XOR") == 0)
8850 new_token.code = '^';
8851
8852 else if (strcasecmp (new_token.str, "SHL") == 0)
8853 new_token.code = T_SHL;
8854
8855 else if (strcasecmp (new_token.str, "SHR") == 0)
8856 new_token.code = T_SHR;
8857
8858 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 8859 new_token.code = T_BYTE;
8860
8861 else if (strcasecmp (new_token.str, "WORD") == 0)
8862 new_token.code = T_WORD;
8863
8864 else if (strcasecmp (new_token.str, "DWORD") == 0)
8865 new_token.code = T_DWORD;
8866
9306ca4a
JB		 8867 else if (strcasecmp (new_token.str, "FWORD") == 0)
8868 new_token.code = T_FWORD;
8869
64a0c779
DN		 8870 else if (strcasecmp (new_token.str, "QWORD") == 0)
8871 new_token.code = T_QWORD;
8872
9306ca4a
JB		 8873 else if (strcasecmp (new_token.str, "TBYTE") == 0
8874 /* XXX remove (gcc still uses it) */
8875 || strcasecmp (new_token.str, "XWORD") == 0)
8876 new_token.code = T_TBYTE;
8877
8878 else if (strcasecmp (new_token.str, "XMMWORD") == 0
8879 || strcasecmp (new_token.str, "OWORD") == 0)
8880 new_token.code = T_XMMWORD;
64a0c779
DN		 8881
8882 else if (strcasecmp (new_token.str, "PTR") == 0)
8883 new_token.code = T_PTR;
8884
8885 else if (strcasecmp (new_token.str, "SHORT") == 0)
8886 new_token.code = T_SHORT;
8887
8888 else if (strcasecmp (new_token.str, "OFFSET") == 0)
8889 {
8890 new_token.code = T_OFFSET;
8891
8892 /* ??? This is not mentioned in the MASM grammar but gcc
8893 makes use of it with -mintel-syntax. OFFSET may be
8894 followed by FLAT: */
8895 if (strncasecmp (q, " FLAT:", 6) == 0)
8896 strcat (new_token.str, " FLAT:");
8897 }
8898
8899 /* ??? This is not mentioned in the MASM grammar. */
8900 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 8901 {
8902 new_token.code = T_OFFSET;
8903 if (*q == ':')
8904 strcat (new_token.str, ":");
8905 else
8906 as_bad (_("`:' expected"));
8907 }
64a0c779
DN		 8908
8909 else
8910 new_token.code = T_ID;
8911 }
8912 }
8913
9306ca4a
JB		 8914 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
8915 {
8916 new_token.code = *intel_parser.op_string;
8917 new_token.str[0] = *intel_parser.op_string;
8918 new_token.str[1] = '\0';
8919 }
8920
8921 else if (strchr ("<>", *intel_parser.op_string)
8922 && *intel_parser.op_string == *(intel_parser.op_string + 1))
8923 {
8924 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
8925 new_token.str[0] = *intel_parser.op_string;
8926 new_token.str[1] = *intel_parser.op_string;
8927 new_token.str[2] = '\0';
8928 }
8929
64a0c779 8930 else
0477af35 8931 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 8932
8933 intel_parser.op_string += strlen (new_token.str);
8934 cur_token = new_token;
8935}
8936
64a0c779
DN		 8937/* Put cur_token back into the token stream and make cur_token point to
8938 prev_token. */
8939static void
e3bb37b5 8940intel_putback_token (void)
64a0c779 8941{
a724f0f4
JB		 8942 if (cur_token.code != T_NIL)
8943 {
8944 intel_parser.op_string -= strlen (cur_token.str);
8945 free (cur_token.str);
8946 }
64a0c779 8947 cur_token = prev_token;
4a1805b1 8948
64a0c779
DN		 8949 /* Forget prev_token. */
8950 prev_token.code = T_NIL;
8951 prev_token.reg = NULL;
8952 prev_token.str = NULL;
8953}
54cfded0 8954
a4447b93 8955int
1df69f4f 8956tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 8957{
8958 unsigned int regnum;
8959 unsigned int regnames_count;
089dfecd 8960 static const char *const regnames_32[] =
54cfded0 8961 {
a4447b93
RH		 8962 "eax", "ecx", "edx", "ebx",
8963 "esp", "ebp", "esi", "edi",
089dfecd
JB		 8964 "eip", "eflags", NULL,
8965 "st0", "st1", "st2", "st3",
8966 "st4", "st5", "st6", "st7",
8967 NULL, NULL,
8968 "xmm0", "xmm1", "xmm2", "xmm3",
8969 "xmm4", "xmm5", "xmm6", "xmm7",
8970 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8971 "mm4", "mm5", "mm6", "mm7",
8972 "fcw", "fsw", "mxcsr",
8973 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8974 "tr", "ldtr"
54cfded0 8975 };
089dfecd 8976 static const char *const regnames_64[] =
54cfded0 8977 {
089dfecd
JB		 8978 "rax", "rdx", "rcx", "rbx",
8979 "rsi", "rdi", "rbp", "rsp",
8980 "r8", "r9", "r10", "r11",
54cfded0 8981 "r12", "r13", "r14", "r15",
089dfecd
JB		 8982 "rip",
8983 "xmm0", "xmm1", "xmm2", "xmm3",
8984 "xmm4", "xmm5", "xmm6", "xmm7",
8985 "xmm8", "xmm9", "xmm10", "xmm11",
8986 "xmm12", "xmm13", "xmm14", "xmm15",
8987 "st0", "st1", "st2", "st3",
8988 "st4", "st5", "st6", "st7",
8989 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8990 "mm4", "mm5", "mm6", "mm7",
8991 "rflags",
8992 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8993 "fs.base", "gs.base", NULL, NULL,
8994 "tr", "ldtr",
8995 "mxcsr", "fcw", "fsw"
54cfded0 8996 };
089dfecd 8997 const char *const *regnames;
54cfded0
AM		 8998
8999 if (flag_code == CODE_64BIT)
9000 {
9001 regnames = regnames_64;
0cea6190 9002 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 9003 }
9004 else
9005 {
9006 regnames = regnames_32;
0cea6190 9007 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 9008 }
9009
9010 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 9011 if (regnames[regnum] != NULL
9012 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 9013 return regnum;
9014
54cfded0
AM		 9015 return -1;
9016}
9017
9018void
9019tc_x86_frame_initial_instructions (void)
9020{
a4447b93
RH		 9021 static unsigned int sp_regno;
9022
9023 if (!sp_regno)
9024 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
9025 ? "rsp" : "esp");
9026
9027 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
9028 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 9029}
d2b2c203
DJ		 9030
9031int
9032i386_elf_section_type (const char *str, size_t len)
9033{
9034 if (flag_code == CODE_64BIT
9035 && len == sizeof ("unwind") - 1
9036 && strncmp (str, "unwind", 6) == 0)
9037 return SHT_X86_64_UNWIND;
9038
9039 return -1;
9040}
bb41ade5
AM		 9041
9042#ifdef TE_PE
9043void
9044tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9045{
9046 expressionS expr;
9047
9048 expr.X_op = O_secrel;
9049 expr.X_add_symbol = symbol;
9050 expr.X_add_number = 0;
9051 emit_expr (&expr, size);
9052}
9053#endif
3b22753a
L		 9054
9055#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9056/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9057
9058int
9059x86_64_section_letter (int letter, char **ptr_msg)
9060{
9061 if (flag_code == CODE_64BIT)
9062 {
9063 if (letter == 'l')
9064 return SHF_X86_64_LARGE;
9065
9066 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9067 }
3b22753a 9068 else
64e74474 9069 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9070 return -1;
9071}
9072
9073int
9074x86_64_section_word (char *str, size_t len)
9075{
8620418b 9076 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9077 return SHF_X86_64_LARGE;
9078
9079 return -1;
9080}
9081
9082static void
9083handle_large_common (int small ATTRIBUTE_UNUSED)
9084{
9085 if (flag_code != CODE_64BIT)
9086 {
9087 s_comm_internal (0, elf_common_parse);
9088 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9089 }
9090 else
9091 {
9092 static segT lbss_section;
9093 asection *saved_com_section_ptr = elf_com_section_ptr;
9094 asection *saved_bss_section = bss_section;
9095
9096 if (lbss_section == NULL)
9097 {
9098 flagword applicable;
9099 segT seg = now_seg;
9100 subsegT subseg = now_subseg;
9101
9102 /* The .lbss section is for local .largecomm symbols. */
9103 lbss_section = subseg_new (".lbss", 0);
9104 applicable = bfd_applicable_section_flags (stdoutput);
9105 bfd_set_section_flags (stdoutput, lbss_section,
9106 applicable & SEC_ALLOC);
9107 seg_info (lbss_section)->bss = 1;
9108
9109 subseg_set (seg, subseg);
9110 }
9111
9112 elf_com_section_ptr = &_bfd_elf_large_com_section;
9113 bss_section = lbss_section;
9114
9115 s_comm_internal (0, elf_common_parse);
9116
9117 elf_com_section_ptr = saved_com_section_ptr;
9118 bss_section = saved_bss_section;
9119 }
9120}
9121#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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