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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
d382c579
TG		 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
4 2012
47926f60 5 Free Software Foundation, Inc.
252b5132
RH		 6
7 This file is part of GAS, the GNU Assembler.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
ec2655a6 11 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 02110-1301, USA. */
252b5132 23
47926f60
KH		 24/* Intel 80386 machine specific gas.
25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 26 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 28 Bugs & suggestions are completely welcome. This is free software.
29 Please help us make it better. */
252b5132 30
252b5132 31#include "as.h"
3882b010 32#include "safe-ctype.h"
252b5132 33#include "subsegs.h"
316e2c05 34#include "dwarf2dbg.h"
54cfded0 35#include "dw2gencfi.h"
d2b2c203 36#include "elf/x86-64.h"
40fb9820 37#include "opcodes/i386-init.h"
252b5132 38
252b5132
RH		 39#ifndef REGISTER_WARNINGS
40#define REGISTER_WARNINGS 1
41#endif
42
c3332e24 43#ifndef INFER_ADDR_PREFIX
eecb386c 44#define INFER_ADDR_PREFIX 1
c3332e24
AM		 45#endif
46
29b0f896
AM		 47#ifndef DEFAULT_ARCH
48#define DEFAULT_ARCH "i386"
246fcdee 49#endif
252b5132 50
edde18a5
AM		 51#ifndef INLINE
52#if __GNUC__ >= 2
53#define INLINE __inline__
54#else
55#define INLINE
56#endif
57#endif
58
6305a203
L		 59/* Prefixes will be emitted in the order defined below.
60 WAIT_PREFIX must be the first prefix since FWAIT is really is an
61 instruction, and so must come before any prefixes.
62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 63 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 64#define WAIT_PREFIX 0
65#define SEG_PREFIX 1
66#define ADDR_PREFIX 2
67#define DATA_PREFIX 3
c32fa91d 68#define REP_PREFIX 4
42164a71 69#define HLE_PREFIX REP_PREFIX
c32fa91d
L		 70#define LOCK_PREFIX 5
71#define REX_PREFIX 6 /* must come last. */
72#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 73
74/* we define the syntax here (modulo base,index,scale syntax) */
75#define REGISTER_PREFIX '%'
76#define IMMEDIATE_PREFIX '$'
77#define ABSOLUTE_PREFIX '*'
78
79/* these are the instruction mnemonic suffixes in AT&T syntax or
80 memory operand size in Intel syntax. */
81#define WORD_MNEM_SUFFIX 'w'
82#define BYTE_MNEM_SUFFIX 'b'
83#define SHORT_MNEM_SUFFIX 's'
84#define LONG_MNEM_SUFFIX 'l'
85#define QWORD_MNEM_SUFFIX 'q'
86#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 87#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 88/* Intel Syntax. Use a non-ascii letter since since it never appears
89 in instructions. */
90#define LONG_DOUBLE_MNEM_SUFFIX '\1'
91
92#define END_OF_INSN '\0'
93
94/*
95 'templates' is for grouping together 'template' structures for opcodes
96 of the same name. This is only used for storing the insns in the grand
97 ole hash table of insns.
98 The templates themselves start at START and range up to (but not including)
99 END.
100 */
101typedef struct
102{
d3ce72d0
NC		 103 const insn_template *start;
104 const insn_template *end;
6305a203
L		 105}
106templates;
107
108/* 386 operand encoding bytes: see 386 book for details of this. */
109typedef struct
110{
111 unsigned int regmem; /* codes register or memory operand */
112 unsigned int reg; /* codes register operand (or extended opcode) */
113 unsigned int mode; /* how to interpret regmem & reg */
114}
115modrm_byte;
116
117/* x86-64 extension prefix. */
118typedef int rex_byte;
119
6305a203
L		 120/* 386 opcode byte to code indirect addressing. */
121typedef struct
122{
123 unsigned base;
124 unsigned index;
125 unsigned scale;
126}
127sib_byte;
128
6305a203
L		 129/* x86 arch names, types and features */
130typedef struct
131{
132 const char *name; /* arch name */
8a2c8fef 133 unsigned int len; /* arch string length */
6305a203
L		 134 enum processor_type type; /* arch type */
135 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 136 unsigned int skip; /* show_arch should skip this. */
22109423 137 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 138}
139arch_entry;
140
78f12dd3 141static void update_code_flag (int, int);
e3bb37b5
L		 142static void set_code_flag (int);
143static void set_16bit_gcc_code_flag (int);
144static void set_intel_syntax (int);
1efbbeb4 145static void set_intel_mnemonic (int);
db51cc60 146static void set_allow_index_reg (int);
cb19c032 147static void set_sse_check (int);
e3bb37b5 148static void set_cpu_arch (int);
6482c264 149#ifdef TE_PE
e3bb37b5 150static void pe_directive_secrel (int);
6482c264 151#endif
e3bb37b5
L		 152static void signed_cons (int);
153static char *output_invalid (int c);
ee86248c
JB		 154static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
155 const char *);
156static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
157 const char *);
a7619375 158static int i386_att_operand (char *);
e3bb37b5 159static int i386_intel_operand (char *, int);
ee86248c
JB		 160static int i386_intel_simplify (expressionS *);
161static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 162static const reg_entry *parse_register (char *, char **);
163static char *parse_insn (char *, char *);
164static char *parse_operands (char *, const char *);
165static void swap_operands (void);
4d456e3d 166static void swap_2_operands (int, int);
e3bb37b5
L		 167static void optimize_imm (void);
168static void optimize_disp (void);
d3ce72d0 169static const insn_template *match_template (void);
e3bb37b5
L		 170static int check_string (void);
171static int process_suffix (void);
172static int check_byte_reg (void);
173static int check_long_reg (void);
174static int check_qword_reg (void);
175static int check_word_reg (void);
176static int finalize_imm (void);
177static int process_operands (void);
178static const seg_entry *build_modrm_byte (void);
179static void output_insn (void);
180static void output_imm (fragS *, offsetT);
181static void output_disp (fragS *, offsetT);
29b0f896 182#ifndef I386COFF
e3bb37b5 183static void s_bss (int);
252b5132 184#endif
17d4e2a2
L		 185#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
186static void handle_large_common (int small ATTRIBUTE_UNUSED);
187#endif
252b5132 188
a847613f 189static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 190
c0f3af97
L		 191/* VEX prefix. */
192typedef struct
193{
194 /* VEX prefix is either 2 byte or 3 byte. */
195 unsigned char bytes[3];
196 unsigned int length;
197 /* Destination or source register specifier. */
198 const reg_entry *register_specifier;
199} vex_prefix;
200
252b5132 201/* 'md_assemble ()' gathers together information and puts it into a
47926f60 202 i386_insn. */
252b5132 203
520dc8e8
AM		 204union i386_op
205 {
206 expressionS *disps;
207 expressionS *imms;
208 const reg_entry *regs;
209 };
210
a65babc9
L		 211enum i386_error
212 {
86e026a4 213 operand_size_mismatch,
a65babc9
L		 214 operand_type_mismatch,
215 register_type_mismatch,
216 number_of_operands_mismatch,
217 invalid_instruction_suffix,
218 bad_imm4,
219 old_gcc_only,
220 unsupported_with_intel_mnemonic,
221 unsupported_syntax,
6c30d220
L		 222 unsupported,
223 invalid_vsib_address,
224 unsupported_vector_index_register
a65babc9
L		 225 };
226
252b5132
RH		 227struct _i386_insn
228 {
47926f60 229 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 230 insn_template tm;
252b5132 231
7d5e4556
L		 232 /* SUFFIX holds the instruction size suffix for byte, word, dword
233 or qword, if given. */
252b5132
RH		 234 char suffix;
235
47926f60 236 /* OPERANDS gives the number of given operands. */
252b5132
RH		 237 unsigned int operands;
238
239 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
240 of given register, displacement, memory operands and immediate
47926f60 241 operands. */
252b5132
RH		 242 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
243
244 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 245 use OP[i] for the corresponding operand. */
40fb9820 246 i386_operand_type types[MAX_OPERANDS];
252b5132 247
520dc8e8
AM		 248 /* Displacement expression, immediate expression, or register for each
249 operand. */
250 union i386_op op[MAX_OPERANDS];
252b5132 251
3e73aa7c
JH		 252 /* Flags for operands. */
253 unsigned int flags[MAX_OPERANDS];
254#define Operand_PCrel 1
255
252b5132 256 /* Relocation type for operand */
f86103b7 257 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 258
252b5132
RH		 259 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
260 the base index byte below. */
261 const reg_entry *base_reg;
262 const reg_entry *index_reg;
263 unsigned int log2_scale_factor;
264
265 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 266 explicit segment overrides are given. */
ce8a8b2f 267 const seg_entry *seg[2];
252b5132
RH		 268
269 /* PREFIX holds all the given prefix opcodes (usually null).
270 PREFIXES is the number of prefix opcodes. */
271 unsigned int prefixes;
272 unsigned char prefix[MAX_PREFIXES];
273
274 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 275 addressing modes of this insn are encoded. */
252b5132 276 modrm_byte rm;
3e73aa7c 277 rex_byte rex;
252b5132 278 sib_byte sib;
c0f3af97 279 vex_prefix vex;
b6169b20
L		 280
281 /* Swap operand in encoding. */
4473e004 282 unsigned int swap_operand;
891edac4 283
a501d77e
L		 284 /* Prefer 8bit or 32bit displacement in encoding. */
285 enum
286 {
287 disp_encoding_default = 0,
288 disp_encoding_8bit,
289 disp_encoding_32bit
290 } disp_encoding;
f8a5c266 291
42164a71
L		 292 /* Have HLE prefix. */
293 unsigned int have_hle;
294
891edac4 295 /* Error message. */
a65babc9 296 enum i386_error error;
252b5132
RH		 297 };
298
299typedef struct _i386_insn i386_insn;
300
301/* List of chars besides those in app.c:symbol_chars that can start an
302 operand. Used to prevent the scrubber eating vital white-space. */
32137342 303const char extra_symbol_chars[] = "*%-(["
252b5132 304#ifdef LEX_AT
32137342
NC		 305 "@"
306#endif
307#ifdef LEX_QM
308 "?"
252b5132 309#endif
32137342 310 ;
252b5132 311
29b0f896
AM		 312#if (defined (TE_I386AIX) \
313 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 314 && !defined (TE_GNU) \
29b0f896 315 && !defined (TE_LINUX) \
8d63c93e
RM		 316 && !defined (TE_NACL) \
317 && !defined (TE_NETWARE) \
29b0f896 318 && !defined (TE_FreeBSD) \
5b806d27 319 && !defined (TE_DragonFly) \
29b0f896 320 && !defined (TE_NetBSD)))
252b5132 321/* This array holds the chars that always start a comment. If the
b3b91714
AM		 322 pre-processor is disabled, these aren't very useful. The option
323 --divide will remove '/' from this list. */
324const char *i386_comment_chars = "#/";
325#define SVR4_COMMENT_CHARS 1
252b5132 326#define PREFIX_SEPARATOR '\\'
252b5132 327
b3b91714
AM		 328#else
329const char *i386_comment_chars = "#";
330#define PREFIX_SEPARATOR '/'
331#endif
332
252b5132
RH		 333/* This array holds the chars that only start a comment at the beginning of
334 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 335 .line and .file directives will appear in the pre-processed output.
336 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 337 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 338 #NO_APP at the beginning of its output.
339 Also note that comments started like this one will always work if
252b5132 340 '/' isn't otherwise defined. */
b3b91714 341const char line_comment_chars[] = "#/";
252b5132 342
63a0b638 343const char line_separator_chars[] = ";";
252b5132 344
ce8a8b2f
AM		 345/* Chars that can be used to separate mant from exp in floating point
346 nums. */
252b5132
RH		 347const char EXP_CHARS[] = "eE";
348
ce8a8b2f
AM		 349/* Chars that mean this number is a floating point constant
350 As in 0f12.456
351 or 0d1.2345e12. */
252b5132
RH		 352const char FLT_CHARS[] = "fFdDxX";
353
ce8a8b2f 354/* Tables for lexical analysis. */
252b5132
RH		 355static char mnemonic_chars[256];
356static char register_chars[256];
357static char operand_chars[256];
358static char identifier_chars[256];
359static char digit_chars[256];
360
ce8a8b2f 361/* Lexical macros. */
252b5132
RH		 362#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
363#define is_operand_char(x) (operand_chars[(unsigned char) x])
364#define is_register_char(x) (register_chars[(unsigned char) x])
365#define is_space_char(x) ((x) == ' ')
366#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
367#define is_digit_char(x) (digit_chars[(unsigned char) x])
368
0234cb7c 369/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 370static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
371
372/* md_assemble() always leaves the strings it's passed unaltered. To
373 effect this we maintain a stack of saved characters that we've smashed
374 with '\0's (indicating end of strings for various sub-fields of the
47926f60 375 assembler instruction). */
252b5132 376static char save_stack[32];
ce8a8b2f 377static char *save_stack_p;
252b5132
RH		 378#define END_STRING_AND_SAVE(s) \
379 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
380#define RESTORE_END_STRING(s) \
381 do { *(s) = *--save_stack_p; } while (0)
382
47926f60 383/* The instruction we're assembling. */
252b5132
RH		 384static i386_insn i;
385
386/* Possible templates for current insn. */
387static const templates *current_templates;
388
31b2323c
L		 389/* Per instruction expressionS buffers: max displacements & immediates. */
390static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
391static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 392
47926f60 393/* Current operand we are working on. */
ee86248c 394static int this_operand = -1;
252b5132 395
3e73aa7c
JH		 396/* We support four different modes. FLAG_CODE variable is used to distinguish
397 these. */
398
399enum flag_code {
400 CODE_32BIT,
401 CODE_16BIT,
402 CODE_64BIT };
403
404static enum flag_code flag_code;
4fa24527 405static unsigned int object_64bit;
862be3fb 406static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 407static int use_rela_relocations = 0;
408
7af8ed2d
NC		 409#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
410 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
411 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
412
351f65ca
L		 413/* The ELF ABI to use. */
414enum x86_elf_abi
415{
416 I386_ABI,
7f56bc95
L		 417 X86_64_ABI,
418 X86_64_X32_ABI
351f65ca
L		 419};
420
421static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 422#endif
351f65ca 423
3e73aa7c 424/* The names used to print error messages. */
b77a7acd 425static const char *flag_code_names[] =
3e73aa7c
JH		 426 {
427 "32",
428 "16",
429 "64"
430 };
252b5132 431
47926f60
KH		 432/* 1 for intel syntax,
433 0 if att syntax. */
434static int intel_syntax = 0;
252b5132 435
1efbbeb4
L		 436/* 1 for intel mnemonic,
437 0 if att mnemonic. */
438static int intel_mnemonic = !SYSV386_COMPAT;
439
5209009a 440/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 441static int old_gcc = OLDGCC_COMPAT;
442
a60de03c
JB		 443/* 1 if pseudo registers are permitted. */
444static int allow_pseudo_reg = 0;
445
47926f60
KH		 446/* 1 if register prefix % not required. */
447static int allow_naked_reg = 0;
252b5132 448
ba104c83 449/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 450static int allow_index_reg = 0;
451
daf50ae7
L		 452static enum
453 {
454 sse_check_none = 0,
455 sse_check_warning,
456 sse_check_error
457 }
458sse_check;
459
2ca3ace5
L		 460/* Register prefix used for error message. */
461static const char *register_prefix = "%";
462
47926f60
KH		 463/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
464 leave, push, and pop instructions so that gcc has the same stack
465 frame as in 32 bit mode. */
466static char stackop_size = '\0';
eecb386c 467
12b55ccc
L		 468/* Non-zero to optimize code alignment. */
469int optimize_align_code = 1;
470
47926f60
KH		 471/* Non-zero to quieten some warnings. */
472static int quiet_warnings = 0;
a38cf1db 473
47926f60
KH		 474/* CPU name. */
475static const char *cpu_arch_name = NULL;
6305a203 476static char *cpu_sub_arch_name = NULL;
a38cf1db 477
47926f60 478/* CPU feature flags. */
40fb9820
L		 479static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
480
ccc9c027
L		 481/* If we have selected a cpu we are generating instructions for. */
482static int cpu_arch_tune_set = 0;
483
9103f4f4 484/* Cpu we are generating instructions for. */
fbf3f584 485enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 486
487/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 488static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 489
ccc9c027 490/* CPU instruction set architecture used. */
fbf3f584 491enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 492
9103f4f4 493/* CPU feature flags of instruction set architecture used. */
fbf3f584 494i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 495
fddf5b5b
AM		 496/* If set, conditional jumps are not automatically promoted to handle
497 larger than a byte offset. */
498static unsigned int no_cond_jump_promotion = 0;
499
c0f3af97
L		 500/* Encode SSE instructions with VEX prefix. */
501static unsigned int sse2avx;
502
539f890d
L		 503/* Encode scalar AVX instructions with specific vector length. */
504static enum
505 {
506 vex128 = 0,
507 vex256
508 } avxscalar;
509
29b0f896 510/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 511static symbolS *GOT_symbol;
29b0f896 512
a4447b93
RH		 513/* The dwarf2 return column, adjusted for 32 or 64 bit. */
514unsigned int x86_dwarf2_return_column;
515
516/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
517int x86_cie_data_alignment;
518
252b5132 519/* Interface to relax_segment.
fddf5b5b
AM		 520 There are 3 major relax states for 386 jump insns because the
521 different types of jumps add different sizes to frags when we're
522 figuring out what sort of jump to choose to reach a given label. */
252b5132 523
47926f60 524/* Types. */
93c2a809
AM		 525#define UNCOND_JUMP 0
526#define COND_JUMP 1
527#define COND_JUMP86 2
fddf5b5b 528
47926f60 529/* Sizes. */
252b5132
RH		 530#define CODE16 1
531#define SMALL 0
29b0f896 532#define SMALL16 (SMALL | CODE16)
252b5132 533#define BIG 2
29b0f896 534#define BIG16 (BIG | CODE16)
252b5132
RH		 535
536#ifndef INLINE
537#ifdef __GNUC__
538#define INLINE __inline__
539#else
540#define INLINE
541#endif
542#endif
543
fddf5b5b
AM		 544#define ENCODE_RELAX_STATE(type, size) \
545 ((relax_substateT) (((type) << 2) | (size)))
546#define TYPE_FROM_RELAX_STATE(s) \
547 ((s) >> 2)
548#define DISP_SIZE_FROM_RELAX_STATE(s) \
549 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 550
551/* This table is used by relax_frag to promote short jumps to long
552 ones where necessary. SMALL (short) jumps may be promoted to BIG
553 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
554 don't allow a short jump in a 32 bit code segment to be promoted to
555 a 16 bit offset jump because it's slower (requires data size
556 prefix), and doesn't work, unless the destination is in the bottom
557 64k of the code segment (The top 16 bits of eip are zeroed). */
558
559const relax_typeS md_relax_table[] =
560{
24eab124
AM		 561 /* The fields are:
562 1) most positive reach of this state,
563 2) most negative reach of this state,
93c2a809 564 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 565 4) which index into the table to try if we can't fit into this one. */
252b5132 566
fddf5b5b 567 /* UNCOND_JUMP states. */
93c2a809
AM		 568 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
569 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
570 /* dword jmp adds 4 bytes to frag:
571 0 extra opcode bytes, 4 displacement bytes. */
252b5132 572 {0, 0, 4, 0},
93c2a809
AM		 573 /* word jmp adds 2 byte2 to frag:
574 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 575 {0, 0, 2, 0},
576
93c2a809
AM		 577 /* COND_JUMP states. */
578 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
579 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
580 /* dword conditionals adds 5 bytes to frag:
581 1 extra opcode byte, 4 displacement bytes. */
582 {0, 0, 5, 0},
fddf5b5b 583 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 584 1 extra opcode byte, 2 displacement bytes. */
585 {0, 0, 3, 0},
586
587 /* COND_JUMP86 states. */
588 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
589 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
590 /* dword conditionals adds 5 bytes to frag:
591 1 extra opcode byte, 4 displacement bytes. */
592 {0, 0, 5, 0},
593 /* word conditionals add 4 bytes to frag:
594 1 displacement byte and a 3 byte long branch insn. */
595 {0, 0, 4, 0}
252b5132
RH		 596};
597
9103f4f4
L		 598static const arch_entry cpu_arch[] =
599{
89507696
JB		 600 /* Do not replace the first two entries - i386_target_format()
601 relies on them being there in this order. */
8a2c8fef 602 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 603 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 604 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 605 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 606 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 607 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 608 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 609 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 610 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 611 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 612 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 613 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 614 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 615 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 616 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 617 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 618 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 619 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 620 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 621 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 622 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 623 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 624 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 625 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 626 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 627 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 628 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 629 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 630 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 631 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 632 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 633 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 634 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 635 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 636 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 637 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 638 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 639 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 640 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 641 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 642 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 643 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 644 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 645 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 646 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
647 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 648 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 649 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 650 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 651 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 652 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 653 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 654 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 655 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 656 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 657 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 658 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 659 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 660 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 661 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 662 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 663 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 664 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 665 CPU_BDVER2_FLAGS, 0, 0 },
8a2c8fef 666 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 667 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 668 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 669 CPU_287_FLAGS, 0, 0 },
8a2c8fef 670 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 671 CPU_387_FLAGS, 0, 0 },
8a2c8fef 672 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 673 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 674 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 675 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 676 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 677 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 678 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 679 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 680 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 681 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 682 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 683 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 684 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 685 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 686 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 687 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 688 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 689 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 690 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 691 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 692 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 693 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 694 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 695 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 696 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
697 CPU_AVX2_FLAGS, 0, 0 },
8a2c8fef 698 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 699 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 700 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 701 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 702 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
703 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 704 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 705 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 706 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 707 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 708 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 709 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 710 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 711 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 712 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 713 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 714 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 715 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 716 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 717 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 718 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 719 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 720 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 721 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 722 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
723 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 724 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 725 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 726 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 727 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 728 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 729 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 730 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 731 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 732 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 733 CPU_MOVBE_FLAGS, 0, 0 },
8a2c8fef 734 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 735 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 736 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
737 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 738 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
739 CPU_HLE_FLAGS, 0, 0 },
740 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
741 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 742 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
743 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 744 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 745 CPU_CLFLUSH_FLAGS, 0, 0 },
746 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
747 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 748 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 749 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 750 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 751 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 752 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 753 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 754 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 755 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 756 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 757 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 758 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 759 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 760 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 761 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 762 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 763 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 764 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 765 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 766 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
767 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 768 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
769 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 770 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
771 CPU_ADX_FLAGS, 0, 0 },
772 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
773 CPU_RDSEED_FLAGS, 0, 0 },
774 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
775 CPU_PRFCHW_FLAGS, 0, 0 },
e413e4e9
AM		 776};
777
704209c0 778#ifdef I386COFF
a6c24e68
NC		 779/* Like s_lcomm_internal in gas/read.c but the alignment string
780 is allowed to be optional. */
781
782static symbolS *
783pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
784{
785 addressT align = 0;
786
787 SKIP_WHITESPACE ();
788
7ab9ffdd 789 if (needs_align
a6c24e68
NC		 790 && *input_line_pointer == ',')
791 {
792 align = parse_align (needs_align - 1);
7ab9ffdd 793
a6c24e68
NC		 794 if (align == (addressT) -1)
795 return NULL;
796 }
797 else
798 {
799 if (size >= 8)
800 align = 3;
801 else if (size >= 4)
802 align = 2;
803 else if (size >= 2)
804 align = 1;
805 else
806 align = 0;
807 }
808
809 bss_alloc (symbolP, size, align);
810 return symbolP;
811}
812
704209c0 813static void
a6c24e68
NC		 814pe_lcomm (int needs_align)
815{
816 s_comm_internal (needs_align * 2, pe_lcomm_internal);
817}
704209c0 818#endif
a6c24e68 819
29b0f896
AM		 820const pseudo_typeS md_pseudo_table[] =
821{
822#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
823 {"align", s_align_bytes, 0},
824#else
825 {"align", s_align_ptwo, 0},
826#endif
827 {"arch", set_cpu_arch, 0},
828#ifndef I386COFF
829 {"bss", s_bss, 0},
a6c24e68
NC		 830#else
831 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 832#endif
833 {"ffloat", float_cons, 'f'},
834 {"dfloat", float_cons, 'd'},
835 {"tfloat", float_cons, 'x'},
836 {"value", cons, 2},
d182319b 837 {"slong", signed_cons, 4},
29b0f896
AM		 838 {"noopt", s_ignore, 0},
839 {"optim", s_ignore, 0},
840 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
841 {"code16", set_code_flag, CODE_16BIT},
842 {"code32", set_code_flag, CODE_32BIT},
843 {"code64", set_code_flag, CODE_64BIT},
844 {"intel_syntax", set_intel_syntax, 1},
845 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 846 {"intel_mnemonic", set_intel_mnemonic, 1},
847 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 848 {"allow_index_reg", set_allow_index_reg, 1},
849 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 850 {"sse_check", set_sse_check, 0},
3b22753a
L		 851#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
852 {"largecomm", handle_large_common, 0},
07a53e5c 853#else
e3bb37b5 854 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 855 {"loc", dwarf2_directive_loc, 0},
856 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 857#endif
6482c264
NC		 858#ifdef TE_PE
859 {"secrel32", pe_directive_secrel, 0},
860#endif
29b0f896
AM		 861 {0, 0, 0}
862};
863
864/* For interface with expression (). */
865extern char *input_line_pointer;
866
867/* Hash table for instruction mnemonic lookup. */
868static struct hash_control *op_hash;
869
870/* Hash table for register lookup. */
871static struct hash_control *reg_hash;
872\f
252b5132 873void
e3bb37b5 874i386_align_code (fragS *fragP, int count)
252b5132 875{
ce8a8b2f
AM		 876 /* Various efficient no-op patterns for aligning code labels.
877 Note: Don't try to assemble the instructions in the comments.
878 0L and 0w are not legal. */
252b5132
RH		 879 static const char f32_1[] =
880 {0x90}; /* nop */
881 static const char f32_2[] =
ccc9c027 882 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 883 static const char f32_3[] =
884 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
885 static const char f32_4[] =
886 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
887 static const char f32_5[] =
888 {0x90, /* nop */
889 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
890 static const char f32_6[] =
891 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
892 static const char f32_7[] =
893 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
894 static const char f32_8[] =
895 {0x90, /* nop */
896 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
897 static const char f32_9[] =
898 {0x89,0xf6, /* movl %esi,%esi */
899 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
900 static const char f32_10[] =
901 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
902 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
903 static const char f32_11[] =
904 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
905 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
906 static const char f32_12[] =
907 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
908 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
909 static const char f32_13[] =
910 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
911 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
912 static const char f32_14[] =
913 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
914 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 915 static const char f16_3[] =
916 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 917 static const char f16_4[] =
918 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
919 static const char f16_5[] =
920 {0x90, /* nop */
921 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
922 static const char f16_6[] =
923 {0x89,0xf6, /* mov %si,%si */
924 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
925 static const char f16_7[] =
926 {0x8d,0x74,0x00, /* lea 0(%si),%si */
927 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
928 static const char f16_8[] =
929 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
930 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 931 static const char jump_31[] =
932 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
933 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
934 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
935 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 936 static const char *const f32_patt[] = {
937 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 938 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 939 };
940 static const char *const f16_patt[] = {
76bc74dc 941 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 942 };
ccc9c027
L		 943 /* nopl (%[re]ax) */
944 static const char alt_3[] =
945 {0x0f,0x1f,0x00};
946 /* nopl 0(%[re]ax) */
947 static const char alt_4[] =
948 {0x0f,0x1f,0x40,0x00};
949 /* nopl 0(%[re]ax,%[re]ax,1) */
950 static const char alt_5[] =
951 {0x0f,0x1f,0x44,0x00,0x00};
952 /* nopw 0(%[re]ax,%[re]ax,1) */
953 static const char alt_6[] =
954 {0x66,0x0f,0x1f,0x44,0x00,0x00};
955 /* nopl 0L(%[re]ax) */
956 static const char alt_7[] =
957 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
958 /* nopl 0L(%[re]ax,%[re]ax,1) */
959 static const char alt_8[] =
960 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
961 /* nopw 0L(%[re]ax,%[re]ax,1) */
962 static const char alt_9[] =
963 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
964 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
965 static const char alt_10[] =
966 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
967 /* data16
968 nopw %cs:0L(%[re]ax,%[re]ax,1) */
969 static const char alt_long_11[] =
970 {0x66,
971 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
972 /* data16
973 data16
974 nopw %cs:0L(%[re]ax,%[re]ax,1) */
975 static const char alt_long_12[] =
976 {0x66,
977 0x66,
978 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
979 /* data16
980 data16
981 data16
982 nopw %cs:0L(%[re]ax,%[re]ax,1) */
983 static const char alt_long_13[] =
984 {0x66,
985 0x66,
986 0x66,
987 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
988 /* data16
989 data16
990 data16
991 data16
992 nopw %cs:0L(%[re]ax,%[re]ax,1) */
993 static const char alt_long_14[] =
994 {0x66,
995 0x66,
996 0x66,
997 0x66,
998 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
999 /* data16
1000 data16
1001 data16
1002 data16
1003 data16
1004 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1005 static const char alt_long_15[] =
1006 {0x66,
1007 0x66,
1008 0x66,
1009 0x66,
1010 0x66,
1011 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1012 /* nopl 0(%[re]ax,%[re]ax,1)
1013 nopw 0(%[re]ax,%[re]ax,1) */
1014 static const char alt_short_11[] =
1015 {0x0f,0x1f,0x44,0x00,0x00,
1016 0x66,0x0f,0x1f,0x44,0x00,0x00};
1017 /* nopw 0(%[re]ax,%[re]ax,1)
1018 nopw 0(%[re]ax,%[re]ax,1) */
1019 static const char alt_short_12[] =
1020 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1021 0x66,0x0f,0x1f,0x44,0x00,0x00};
1022 /* nopw 0(%[re]ax,%[re]ax,1)
1023 nopl 0L(%[re]ax) */
1024 static const char alt_short_13[] =
1025 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1026 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1027 /* nopl 0L(%[re]ax)
1028 nopl 0L(%[re]ax) */
1029 static const char alt_short_14[] =
1030 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1031 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1032 /* nopl 0L(%[re]ax)
1033 nopl 0L(%[re]ax,%[re]ax,1) */
1034 static const char alt_short_15[] =
1035 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1036 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1037 static const char *const alt_short_patt[] = {
1038 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1039 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1040 alt_short_14, alt_short_15
1041 };
1042 static const char *const alt_long_patt[] = {
1043 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1044 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1045 alt_long_14, alt_long_15
1046 };
252b5132 1047
76bc74dc
L		 1048 /* Only align for at least a positive non-zero boundary. */
1049 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1050 return;
3e73aa7c 1051
ccc9c027
L		 1052 /* We need to decide which NOP sequence to use for 32bit and
1053 64bit. When -mtune= is used:
4eed87de 1054
76bc74dc
L		 1055 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1056 PROCESSOR_GENERIC32, f32_patt will be used.
1057 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1058 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1059 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1060 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
8aedb9fe 1061 PROCESSOR_AMDFAM10, and PROCESSOR_BD, alt_short_patt
69dd9865 1062 will be used.
ccc9c027 1063
76bc74dc 1064 When -mtune= isn't used, alt_long_patt will be used if
22109423 1065 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1066 be used.
ccc9c027
L		 1067
1068 When -march= or .arch is used, we can't use anything beyond
1069 cpu_arch_isa_flags. */
1070
1071 if (flag_code == CODE_16BIT)
1072 {
ccc9c027 1073 if (count > 8)
33fef721 1074 {
76bc74dc
L		 1075 memcpy (fragP->fr_literal + fragP->fr_fix,
1076 jump_31, count);
1077 /* Adjust jump offset. */
1078 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1079 }
76bc74dc
L		 1080 else
1081 memcpy (fragP->fr_literal + fragP->fr_fix,
1082 f16_patt[count - 1], count);
252b5132 1083 }
33fef721 1084 else
ccc9c027
L		 1085 {
1086 const char *const *patt = NULL;
1087
fbf3f584 1088 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1089 {
1090 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1091 switch (cpu_arch_tune)
1092 {
1093 case PROCESSOR_UNKNOWN:
1094 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1095 optimize with nops. */
1096 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1097 patt = alt_long_patt;
ccc9c027
L		 1098 else
1099 patt = f32_patt;
1100 break;
ccc9c027
L		 1101 case PROCESSOR_PENTIUM4:
1102 case PROCESSOR_NOCONA:
ef05d495 1103 case PROCESSOR_CORE:
76bc74dc 1104 case PROCESSOR_CORE2:
bd5295b2 1105 case PROCESSOR_COREI7:
3632d14b 1106 case PROCESSOR_L1OM:
7a9068fe 1107 case PROCESSOR_K1OM:
76bc74dc
L		 1108 case PROCESSOR_GENERIC64:
1109 patt = alt_long_patt;
1110 break;
ccc9c027
L		 1111 case PROCESSOR_K6:
1112 case PROCESSOR_ATHLON:
1113 case PROCESSOR_K8:
4eed87de 1114 case PROCESSOR_AMDFAM10:
8aedb9fe 1115 case PROCESSOR_BD:
ccc9c027
L		 1116 patt = alt_short_patt;
1117 break;
76bc74dc 1118 case PROCESSOR_I386:
ccc9c027
L		 1119 case PROCESSOR_I486:
1120 case PROCESSOR_PENTIUM:
2dde1948 1121 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1122 case PROCESSOR_GENERIC32:
1123 patt = f32_patt;
1124 break;
4eed87de 1125 }
ccc9c027
L		 1126 }
1127 else
1128 {
fbf3f584 1129 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1130 {
1131 case PROCESSOR_UNKNOWN:
e6a14101 1132 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1133 PROCESSOR_UNKNOWN. */
1134 abort ();
1135 break;
1136
76bc74dc 1137 case PROCESSOR_I386:
ccc9c027
L		 1138 case PROCESSOR_I486:
1139 case PROCESSOR_PENTIUM:
ccc9c027
L		 1140 case PROCESSOR_K6:
1141 case PROCESSOR_ATHLON:
1142 case PROCESSOR_K8:
4eed87de 1143 case PROCESSOR_AMDFAM10:
8aedb9fe 1144 case PROCESSOR_BD:
ccc9c027
L		 1145 case PROCESSOR_GENERIC32:
1146 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1147 with nops. */
1148 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1149 patt = alt_short_patt;
1150 else
1151 patt = f32_patt;
1152 break;
76bc74dc
L		 1153 case PROCESSOR_PENTIUMPRO:
1154 case PROCESSOR_PENTIUM4:
1155 case PROCESSOR_NOCONA:
1156 case PROCESSOR_CORE:
ef05d495 1157 case PROCESSOR_CORE2:
bd5295b2 1158 case PROCESSOR_COREI7:
3632d14b 1159 case PROCESSOR_L1OM:
7a9068fe 1160 case PROCESSOR_K1OM:
22109423 1161 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1162 patt = alt_long_patt;
1163 else
1164 patt = f32_patt;
1165 break;
1166 case PROCESSOR_GENERIC64:
76bc74dc 1167 patt = alt_long_patt;
ccc9c027 1168 break;
4eed87de 1169 }
ccc9c027
L		 1170 }
1171
76bc74dc
L		 1172 if (patt == f32_patt)
1173 {
1174 /* If the padding is less than 15 bytes, we use the normal
1175 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1176 its offset. */
1177 int limit;
76ba9986 1178
711eedef
L		 1179 /* For 64bit, the limit is 3 bytes. */
1180 if (flag_code == CODE_64BIT
1181 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1182 limit = 3;
1183 else
1184 limit = 15;
1185 if (count < limit)
76bc74dc
L		 1186 memcpy (fragP->fr_literal + fragP->fr_fix,
1187 patt[count - 1], count);
1188 else
1189 {
1190 memcpy (fragP->fr_literal + fragP->fr_fix,
1191 jump_31, count);
1192 /* Adjust jump offset. */
1193 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1194 }
1195 }
1196 else
1197 {
1198 /* Maximum length of an instruction is 15 byte. If the
1199 padding is greater than 15 bytes and we don't use jump,
1200 we have to break it into smaller pieces. */
1201 int padding = count;
1202 while (padding > 15)
1203 {
1204 padding -= 15;
1205 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1206 patt [14], 15);
1207 }
1208
1209 if (padding)
1210 memcpy (fragP->fr_literal + fragP->fr_fix,
1211 patt [padding - 1], padding);
1212 }
ccc9c027 1213 }
33fef721 1214 fragP->fr_var = count;
252b5132
RH		 1215}
1216
c6fb90c8 1217static INLINE int
0dfbf9d7 1218operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1219{
0dfbf9d7 1220 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1221 {
1222 case 3:
0dfbf9d7 1223 if (x->array[2])
c6fb90c8
L		 1224 return 0;
1225 case 2:
0dfbf9d7 1226 if (x->array[1])
c6fb90c8
L		 1227 return 0;
1228 case 1:
0dfbf9d7 1229 return !x->array[0];
c6fb90c8
L		 1230 default:
1231 abort ();
1232 }
40fb9820
L		 1233}
1234
c6fb90c8 1235static INLINE void
0dfbf9d7 1236operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1237{
0dfbf9d7 1238 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1239 {
1240 case 3:
0dfbf9d7 1241 x->array[2] = v;
c6fb90c8 1242 case 2:
0dfbf9d7 1243 x->array[1] = v;
c6fb90c8 1244 case 1:
0dfbf9d7 1245 x->array[0] = v;
c6fb90c8
L		 1246 break;
1247 default:
1248 abort ();
1249 }
1250}
40fb9820 1251
c6fb90c8 1252static INLINE int
0dfbf9d7
L		 1253operand_type_equal (const union i386_operand_type *x,
1254 const union i386_operand_type *y)
c6fb90c8 1255{
0dfbf9d7 1256 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1257 {
1258 case 3:
0dfbf9d7 1259 if (x->array[2] != y->array[2])
c6fb90c8
L		 1260 return 0;
1261 case 2:
0dfbf9d7 1262 if (x->array[1] != y->array[1])
c6fb90c8
L		 1263 return 0;
1264 case 1:
0dfbf9d7 1265 return x->array[0] == y->array[0];
c6fb90c8
L		 1266 break;
1267 default:
1268 abort ();
1269 }
1270}
40fb9820 1271
0dfbf9d7
L		 1272static INLINE int
1273cpu_flags_all_zero (const union i386_cpu_flags *x)
1274{
1275 switch (ARRAY_SIZE(x->array))
1276 {
1277 case 3:
1278 if (x->array[2])
1279 return 0;
1280 case 2:
1281 if (x->array[1])
1282 return 0;
1283 case 1:
1284 return !x->array[0];
1285 default:
1286 abort ();
1287 }
1288}
1289
1290static INLINE void
1291cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1292{
1293 switch (ARRAY_SIZE(x->array))
1294 {
1295 case 3:
1296 x->array[2] = v;
1297 case 2:
1298 x->array[1] = v;
1299 case 1:
1300 x->array[0] = v;
1301 break;
1302 default:
1303 abort ();
1304 }
1305}
1306
1307static INLINE int
1308cpu_flags_equal (const union i386_cpu_flags *x,
1309 const union i386_cpu_flags *y)
1310{
1311 switch (ARRAY_SIZE(x->array))
1312 {
1313 case 3:
1314 if (x->array[2] != y->array[2])
1315 return 0;
1316 case 2:
1317 if (x->array[1] != y->array[1])
1318 return 0;
1319 case 1:
1320 return x->array[0] == y->array[0];
1321 break;
1322 default:
1323 abort ();
1324 }
1325}
c6fb90c8
L		 1326
1327static INLINE int
1328cpu_flags_check_cpu64 (i386_cpu_flags f)
1329{
1330 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1331 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1332}
1333
c6fb90c8
L		 1334static INLINE i386_cpu_flags
1335cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1336{
c6fb90c8
L		 1337 switch (ARRAY_SIZE (x.array))
1338 {
1339 case 3:
1340 x.array [2] &= y.array [2];
1341 case 2:
1342 x.array [1] &= y.array [1];
1343 case 1:
1344 x.array [0] &= y.array [0];
1345 break;
1346 default:
1347 abort ();
1348 }
1349 return x;
1350}
40fb9820 1351
c6fb90c8
L		 1352static INLINE i386_cpu_flags
1353cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1354{
c6fb90c8 1355 switch (ARRAY_SIZE (x.array))
40fb9820 1356 {
c6fb90c8
L		 1357 case 3:
1358 x.array [2] |= y.array [2];
1359 case 2:
1360 x.array [1] |= y.array [1];
1361 case 1:
1362 x.array [0] |= y.array [0];
40fb9820
L		 1363 break;
1364 default:
1365 abort ();
1366 }
40fb9820
L		 1367 return x;
1368}
1369
309d3373
JB		 1370static INLINE i386_cpu_flags
1371cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1372{
1373 switch (ARRAY_SIZE (x.array))
1374 {
1375 case 3:
1376 x.array [2] &= ~y.array [2];
1377 case 2:
1378 x.array [1] &= ~y.array [1];
1379 case 1:
1380 x.array [0] &= ~y.array [0];
1381 break;
1382 default:
1383 abort ();
1384 }
1385 return x;
1386}
1387
c0f3af97
L		 1388#define CPU_FLAGS_ARCH_MATCH 0x1
1389#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1390#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1391#define CPU_FLAGS_PCLMUL_MATCH 0x8
1392#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1393
a5ff0eb2 1394#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1395 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1396 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1397#define CPU_FLAGS_PERFECT_MATCH \
1398 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1399
1400/* Return CPU flags match bits. */
3629bb00 1401
40fb9820 1402static int
d3ce72d0 1403cpu_flags_match (const insn_template *t)
40fb9820 1404{
c0f3af97
L		 1405 i386_cpu_flags x = t->cpu_flags;
1406 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1407
1408 x.bitfield.cpu64 = 0;
1409 x.bitfield.cpuno64 = 0;
1410
0dfbf9d7 1411 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1412 {
1413 /* This instruction is available on all archs. */
1414 match |= CPU_FLAGS_32BIT_MATCH;
1415 }
3629bb00
L		 1416 else
1417 {
c0f3af97 1418 /* This instruction is available only on some archs. */
3629bb00
L		 1419 i386_cpu_flags cpu = cpu_arch_flags;
1420
1421 cpu.bitfield.cpu64 = 0;
1422 cpu.bitfield.cpuno64 = 0;
1423 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1424 if (!cpu_flags_all_zero (&cpu))
1425 {
a5ff0eb2
L		 1426 if (x.bitfield.cpuavx)
1427 {
ce2f5b3c 1428 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1429 if (cpu.bitfield.cpuavx)
1430 {
1431 /* Check SSE2AVX. */
1432 if (!t->opcode_modifier.sse2avx|| sse2avx)
1433 {
1434 match |= (CPU_FLAGS_ARCH_MATCH
1435 | CPU_FLAGS_AVX_MATCH);
1436 /* Check AES. */
1437 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1438 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1439 /* Check PCLMUL. */
1440 if (!x.bitfield.cpupclmul
1441 || cpu.bitfield.cpupclmul)
1442 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1443 }
1444 }
1445 else
1446 match |= CPU_FLAGS_ARCH_MATCH;
1447 }
1448 else
c0f3af97
L		 1449 match |= CPU_FLAGS_32BIT_MATCH;
1450 }
3629bb00 1451 }
c0f3af97 1452 return match;
40fb9820
L		 1453}
1454
c6fb90c8
L		 1455static INLINE i386_operand_type
1456operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1457{
c6fb90c8
L		 1458 switch (ARRAY_SIZE (x.array))
1459 {
1460 case 3:
1461 x.array [2] &= y.array [2];
1462 case 2:
1463 x.array [1] &= y.array [1];
1464 case 1:
1465 x.array [0] &= y.array [0];
1466 break;
1467 default:
1468 abort ();
1469 }
1470 return x;
40fb9820
L		 1471}
1472
c6fb90c8
L		 1473static INLINE i386_operand_type
1474operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1475{
c6fb90c8 1476 switch (ARRAY_SIZE (x.array))
40fb9820 1477 {
c6fb90c8
L		 1478 case 3:
1479 x.array [2] |= y.array [2];
1480 case 2:
1481 x.array [1] |= y.array [1];
1482 case 1:
1483 x.array [0] |= y.array [0];
40fb9820
L		 1484 break;
1485 default:
1486 abort ();
1487 }
c6fb90c8
L		 1488 return x;
1489}
40fb9820 1490
c6fb90c8
L		 1491static INLINE i386_operand_type
1492operand_type_xor (i386_operand_type x, i386_operand_type y)
1493{
1494 switch (ARRAY_SIZE (x.array))
1495 {
1496 case 3:
1497 x.array [2] ^= y.array [2];
1498 case 2:
1499 x.array [1] ^= y.array [1];
1500 case 1:
1501 x.array [0] ^= y.array [0];
1502 break;
1503 default:
1504 abort ();
1505 }
40fb9820
L		 1506 return x;
1507}
1508
1509static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1510static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1511static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1512static const i386_operand_type inoutportreg
1513 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1514static const i386_operand_type reg16_inoutportreg
1515 = OPERAND_TYPE_REG16_INOUTPORTREG;
1516static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1517static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1518static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1519static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1520static const i386_operand_type anydisp
1521 = OPERAND_TYPE_ANYDISP;
40fb9820 1522static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1523static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1524static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1525static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1526static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1527static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1528static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1529static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1530static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1531static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1532static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1533static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1534
1535enum operand_type
1536{
1537 reg,
40fb9820
L		 1538 imm,
1539 disp,
1540 anymem
1541};
1542
c6fb90c8 1543static INLINE int
40fb9820
L		 1544operand_type_check (i386_operand_type t, enum operand_type c)
1545{
1546 switch (c)
1547 {
1548 case reg:
1549 return (t.bitfield.reg8
1550 || t.bitfield.reg16
1551 || t.bitfield.reg32
1552 || t.bitfield.reg64);
1553
40fb9820
L		 1554 case imm:
1555 return (t.bitfield.imm8
1556 || t.bitfield.imm8s
1557 || t.bitfield.imm16
1558 || t.bitfield.imm32
1559 || t.bitfield.imm32s
1560 || t.bitfield.imm64);
1561
1562 case disp:
1563 return (t.bitfield.disp8
1564 || t.bitfield.disp16
1565 || t.bitfield.disp32
1566 || t.bitfield.disp32s
1567 || t.bitfield.disp64);
1568
1569 case anymem:
1570 return (t.bitfield.disp8
1571 || t.bitfield.disp16
1572 || t.bitfield.disp32
1573 || t.bitfield.disp32s
1574 || t.bitfield.disp64
1575 || t.bitfield.baseindex);
1576
1577 default:
1578 abort ();
1579 }
2cfe26b6
AM		 1580
1581 return 0;
40fb9820
L		 1582}
1583
5c07affc
L		 1584/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1585 operand J for instruction template T. */
1586
1587static INLINE int
d3ce72d0 1588match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1589{
1590 return !((i.types[j].bitfield.byte
1591 && !t->operand_types[j].bitfield.byte)
1592 || (i.types[j].bitfield.word
1593 && !t->operand_types[j].bitfield.word)
1594 || (i.types[j].bitfield.dword
1595 && !t->operand_types[j].bitfield.dword)
1596 || (i.types[j].bitfield.qword
1597 && !t->operand_types[j].bitfield.qword));
1598}
1599
1600/* Return 1 if there is no conflict in any size on operand J for
1601 instruction template T. */
1602
1603static INLINE int
d3ce72d0 1604match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1605{
1606 return (match_reg_size (t, j)
1607 && !((i.types[j].bitfield.unspecified
1608 && !t->operand_types[j].bitfield.unspecified)
1609 || (i.types[j].bitfield.fword
1610 && !t->operand_types[j].bitfield.fword)
1611 || (i.types[j].bitfield.tbyte
1612 && !t->operand_types[j].bitfield.tbyte)
1613 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1614 && !t->operand_types[j].bitfield.xmmword)
1615 || (i.types[j].bitfield.ymmword
1616 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1617}
1618
1619/* Return 1 if there is no size conflict on any operands for
1620 instruction template T. */
1621
1622static INLINE int
d3ce72d0 1623operand_size_match (const insn_template *t)
5c07affc
L		 1624{
1625 unsigned int j;
1626 int match = 1;
1627
1628 /* Don't check jump instructions. */
1629 if (t->opcode_modifier.jump
1630 || t->opcode_modifier.jumpbyte
1631 || t->opcode_modifier.jumpdword
1632 || t->opcode_modifier.jumpintersegment)
1633 return match;
1634
1635 /* Check memory and accumulator operand size. */
1636 for (j = 0; j < i.operands; j++)
1637 {
1638 if (t->operand_types[j].bitfield.anysize)
1639 continue;
1640
1641 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1642 {
1643 match = 0;
1644 break;
1645 }
1646
1647 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1648 {
1649 match = 0;
1650 break;
1651 }
1652 }
1653
891edac4 1654 if (match)
5c07affc 1655 return match;
891edac4
L		 1656 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1657 {
1658mismatch:
86e026a4 1659 i.error = operand_size_mismatch;
891edac4
L		 1660 return 0;
1661 }
5c07affc
L		 1662
1663 /* Check reverse. */
9c2799c2 1664 gas_assert (i.operands == 2);
5c07affc
L		 1665
1666 match = 1;
1667 for (j = 0; j < 2; j++)
1668 {
1669 if (t->operand_types[j].bitfield.acc
1670 && !match_reg_size (t, j ? 0 : 1))
891edac4 1671 goto mismatch;
5c07affc
L		 1672
1673 if (i.types[j].bitfield.mem
1674 && !match_mem_size (t, j ? 0 : 1))
891edac4 1675 goto mismatch;
5c07affc
L		 1676 }
1677
1678 return match;
1679}
1680
c6fb90c8 1681static INLINE int
40fb9820
L		 1682operand_type_match (i386_operand_type overlap,
1683 i386_operand_type given)
1684{
1685 i386_operand_type temp = overlap;
1686
1687 temp.bitfield.jumpabsolute = 0;
7d5e4556 1688 temp.bitfield.unspecified = 0;
5c07affc
L		 1689 temp.bitfield.byte = 0;
1690 temp.bitfield.word = 0;
1691 temp.bitfield.dword = 0;
1692 temp.bitfield.fword = 0;
1693 temp.bitfield.qword = 0;
1694 temp.bitfield.tbyte = 0;
1695 temp.bitfield.xmmword = 0;
c0f3af97 1696 temp.bitfield.ymmword = 0;
0dfbf9d7 1697 if (operand_type_all_zero (&temp))
891edac4 1698 goto mismatch;
40fb9820 1699
891edac4
L		 1700 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1701 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1702 return 1;
1703
1704mismatch:
a65babc9 1705 i.error = operand_type_mismatch;
891edac4 1706 return 0;
40fb9820
L		 1707}
1708
7d5e4556 1709/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1710 unless the expected operand type register overlap is null.
1711 Note that Acc in a template matches every size of reg. */
1712
c6fb90c8 1713static INLINE int
40fb9820
L		 1714operand_type_register_match (i386_operand_type m0,
1715 i386_operand_type g0,
1716 i386_operand_type t0,
1717 i386_operand_type m1,
1718 i386_operand_type g1,
1719 i386_operand_type t1)
1720{
1721 if (!operand_type_check (g0, reg))
1722 return 1;
1723
1724 if (!operand_type_check (g1, reg))
1725 return 1;
1726
1727 if (g0.bitfield.reg8 == g1.bitfield.reg8
1728 && g0.bitfield.reg16 == g1.bitfield.reg16
1729 && g0.bitfield.reg32 == g1.bitfield.reg32
1730 && g0.bitfield.reg64 == g1.bitfield.reg64)
1731 return 1;
1732
1733 if (m0.bitfield.acc)
1734 {
1735 t0.bitfield.reg8 = 1;
1736 t0.bitfield.reg16 = 1;
1737 t0.bitfield.reg32 = 1;
1738 t0.bitfield.reg64 = 1;
1739 }
1740
1741 if (m1.bitfield.acc)
1742 {
1743 t1.bitfield.reg8 = 1;
1744 t1.bitfield.reg16 = 1;
1745 t1.bitfield.reg32 = 1;
1746 t1.bitfield.reg64 = 1;
1747 }
1748
891edac4
L		 1749 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1750 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1751 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1752 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1753 return 1;
1754
a65babc9 1755 i.error = register_type_mismatch;
891edac4
L		 1756
1757 return 0;
40fb9820
L		 1758}
1759
252b5132 1760static INLINE unsigned int
40fb9820 1761mode_from_disp_size (i386_operand_type t)
252b5132 1762{
40fb9820
L		 1763 if (t.bitfield.disp8)
1764 return 1;
1765 else if (t.bitfield.disp16
1766 || t.bitfield.disp32
1767 || t.bitfield.disp32s)
1768 return 2;
1769 else
1770 return 0;
252b5132
RH		 1771}
1772
1773static INLINE int
e3bb37b5 1774fits_in_signed_byte (offsetT num)
252b5132
RH		 1775{
1776 return (num >= -128) && (num <= 127);
47926f60 1777}
252b5132
RH		 1778
1779static INLINE int
e3bb37b5 1780fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1781{
1782 return (num & 0xff) == num;
47926f60 1783}
252b5132
RH		 1784
1785static INLINE int
e3bb37b5 1786fits_in_unsigned_word (offsetT num)
252b5132
RH		 1787{
1788 return (num & 0xffff) == num;
47926f60 1789}
252b5132
RH		 1790
1791static INLINE int
e3bb37b5 1792fits_in_signed_word (offsetT num)
252b5132
RH		 1793{
1794 return (-32768 <= num) && (num <= 32767);
47926f60 1795}
2a962e6d 1796
3e73aa7c 1797static INLINE int
e3bb37b5 1798fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1799{
1800#ifndef BFD64
1801 return 1;
1802#else
1803 return (!(((offsetT) -1 << 31) & num)
1804 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1805#endif
1806} /* fits_in_signed_long() */
2a962e6d 1807
3e73aa7c 1808static INLINE int
e3bb37b5 1809fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1810{
1811#ifndef BFD64
1812 return 1;
1813#else
1814 return (num & (((offsetT) 2 << 31) - 1)) == num;
1815#endif
1816} /* fits_in_unsigned_long() */
252b5132 1817
a683cc34
SP		 1818static INLINE int
1819fits_in_imm4 (offsetT num)
1820{
1821 return (num & 0xf) == num;
1822}
1823
40fb9820 1824static i386_operand_type
e3bb37b5 1825smallest_imm_type (offsetT num)
252b5132 1826{
40fb9820 1827 i386_operand_type t;
7ab9ffdd 1828
0dfbf9d7 1829 operand_type_set (&t, 0);
40fb9820
L		 1830 t.bitfield.imm64 = 1;
1831
1832 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1833 {
1834 /* This code is disabled on the 486 because all the Imm1 forms
1835 in the opcode table are slower on the i486. They're the
1836 versions with the implicitly specified single-position
1837 displacement, which has another syntax if you really want to
1838 use that form. */
40fb9820
L		 1839 t.bitfield.imm1 = 1;
1840 t.bitfield.imm8 = 1;
1841 t.bitfield.imm8s = 1;
1842 t.bitfield.imm16 = 1;
1843 t.bitfield.imm32 = 1;
1844 t.bitfield.imm32s = 1;
1845 }
1846 else if (fits_in_signed_byte (num))
1847 {
1848 t.bitfield.imm8 = 1;
1849 t.bitfield.imm8s = 1;
1850 t.bitfield.imm16 = 1;
1851 t.bitfield.imm32 = 1;
1852 t.bitfield.imm32s = 1;
1853 }
1854 else if (fits_in_unsigned_byte (num))
1855 {
1856 t.bitfield.imm8 = 1;
1857 t.bitfield.imm16 = 1;
1858 t.bitfield.imm32 = 1;
1859 t.bitfield.imm32s = 1;
1860 }
1861 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1862 {
1863 t.bitfield.imm16 = 1;
1864 t.bitfield.imm32 = 1;
1865 t.bitfield.imm32s = 1;
1866 }
1867 else if (fits_in_signed_long (num))
1868 {
1869 t.bitfield.imm32 = 1;
1870 t.bitfield.imm32s = 1;
1871 }
1872 else if (fits_in_unsigned_long (num))
1873 t.bitfield.imm32 = 1;
1874
1875 return t;
47926f60 1876}
252b5132 1877
847f7ad4 1878static offsetT
e3bb37b5 1879offset_in_range (offsetT val, int size)
847f7ad4 1880{
508866be 1881 addressT mask;
ba2adb93 1882
847f7ad4
AM		 1883 switch (size)
1884 {
508866be
L		 1885 case 1: mask = ((addressT) 1 << 8) - 1; break;
1886 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1887 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1888#ifdef BFD64
1889 case 8: mask = ((addressT) 2 << 63) - 1; break;
1890#endif
47926f60 1891 default: abort ();
847f7ad4
AM		 1892 }
1893
9de868bf
L		 1894#ifdef BFD64
1895 /* If BFD64, sign extend val for 32bit address mode. */
1896 if (flag_code != CODE_64BIT
1897 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1898 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1899 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1900#endif
ba2adb93 1901
47926f60 1902 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1903 {
1904 char buf1[40], buf2[40];
1905
1906 sprint_value (buf1, val);
1907 sprint_value (buf2, val & mask);
1908 as_warn (_("%s shortened to %s"), buf1, buf2);
1909 }
1910 return val & mask;
1911}
1912
c32fa91d
L		 1913enum PREFIX_GROUP
1914{
1915 PREFIX_EXIST = 0,
1916 PREFIX_LOCK,
1917 PREFIX_REP,
1918 PREFIX_OTHER
1919};
1920
1921/* Returns
1922 a. PREFIX_EXIST if attempting to add a prefix where one from the
1923 same class already exists.
1924 b. PREFIX_LOCK if lock prefix is added.
1925 c. PREFIX_REP if rep/repne prefix is added.
1926 d. PREFIX_OTHER if other prefix is added.
1927 */
1928
1929static enum PREFIX_GROUP
e3bb37b5 1930add_prefix (unsigned int prefix)
252b5132 1931{
c32fa91d 1932 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1933 unsigned int q;
252b5132 1934
29b0f896
AM		 1935 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1936 && flag_code == CODE_64BIT)
b1905489 1937 {
161a04f6
L		 1938 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1939 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1940 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1941 ret = PREFIX_EXIST;
b1905489
JB		 1942 q = REX_PREFIX;
1943 }
3e73aa7c 1944 else
b1905489
JB		 1945 {
1946 switch (prefix)
1947 {
1948 default:
1949 abort ();
1950
1951 case CS_PREFIX_OPCODE:
1952 case DS_PREFIX_OPCODE:
1953 case ES_PREFIX_OPCODE:
1954 case FS_PREFIX_OPCODE:
1955 case GS_PREFIX_OPCODE:
1956 case SS_PREFIX_OPCODE:
1957 q = SEG_PREFIX;
1958 break;
1959
1960 case REPNE_PREFIX_OPCODE:
1961 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1962 q = REP_PREFIX;
1963 ret = PREFIX_REP;
1964 break;
1965
b1905489 1966 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1967 q = LOCK_PREFIX;
1968 ret = PREFIX_LOCK;
b1905489
JB		 1969 break;
1970
1971 case FWAIT_OPCODE:
1972 q = WAIT_PREFIX;
1973 break;
1974
1975 case ADDR_PREFIX_OPCODE:
1976 q = ADDR_PREFIX;
1977 break;
1978
1979 case DATA_PREFIX_OPCODE:
1980 q = DATA_PREFIX;
1981 break;
1982 }
1983 if (i.prefix[q] != 0)
c32fa91d 1984 ret = PREFIX_EXIST;
b1905489 1985 }
252b5132 1986
b1905489 1987 if (ret)
252b5132 1988 {
b1905489
JB		 1989 if (!i.prefix[q])
1990 ++i.prefixes;
1991 i.prefix[q] |= prefix;
252b5132 1992 }
b1905489
JB		 1993 else
1994 as_bad (_("same type of prefix used twice"));
252b5132 1995
252b5132
RH		 1996 return ret;
1997}
1998
1999static void
78f12dd3 2000update_code_flag (int value, int check)
eecb386c 2001{
78f12dd3
L		 2002 PRINTF_LIKE ((*as_error));
2003
1e9cc1c2 2004 flag_code = (enum flag_code) value;
40fb9820
L		 2005 if (flag_code == CODE_64BIT)
2006 {
2007 cpu_arch_flags.bitfield.cpu64 = 1;
2008 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2009 }
2010 else
2011 {
2012 cpu_arch_flags.bitfield.cpu64 = 0;
2013 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2014 }
2015 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2016 {
78f12dd3
L		 2017 if (check)
2018 as_error = as_fatal;
2019 else
2020 as_error = as_bad;
2021 (*as_error) (_("64bit mode not supported on `%s'."),
2022 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2023 }
40fb9820 2024 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2025 {
78f12dd3
L		 2026 if (check)
2027 as_error = as_fatal;
2028 else
2029 as_error = as_bad;
2030 (*as_error) (_("32bit mode not supported on `%s'."),
2031 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2032 }
eecb386c
AM		 2033 stackop_size = '\0';
2034}
2035
78f12dd3
L		 2036static void
2037set_code_flag (int value)
2038{
2039 update_code_flag (value, 0);
2040}
2041
eecb386c 2042static void
e3bb37b5 2043set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2044{
1e9cc1c2 2045 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2046 if (flag_code != CODE_16BIT)
2047 abort ();
2048 cpu_arch_flags.bitfield.cpu64 = 0;
2049 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2050 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2051}
2052
2053static void
e3bb37b5 2054set_intel_syntax (int syntax_flag)
252b5132
RH		 2055{
2056 /* Find out if register prefixing is specified. */
2057 int ask_naked_reg = 0;
2058
2059 SKIP_WHITESPACE ();
29b0f896 2060 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2061 {
2062 char *string = input_line_pointer;
2063 int e = get_symbol_end ();
2064
47926f60 2065 if (strcmp (string, "prefix") == 0)
252b5132 2066 ask_naked_reg = 1;
47926f60 2067 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2068 ask_naked_reg = -1;
2069 else
d0b47220 2070 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2071 *input_line_pointer = e;
2072 }
2073 demand_empty_rest_of_line ();
c3332e24 2074
252b5132
RH		 2075 intel_syntax = syntax_flag;
2076
2077 if (ask_naked_reg == 0)
f86103b7
AM		 2078 allow_naked_reg = (intel_syntax
2079 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2080 else
2081 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2082
ee86248c 2083 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2084
e4a3b5a4 2085 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2086 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2087 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2088}
2089
1efbbeb4
L		 2090static void
2091set_intel_mnemonic (int mnemonic_flag)
2092{
e1d4d893 2093 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2094}
2095
db51cc60
L		 2096static void
2097set_allow_index_reg (int flag)
2098{
2099 allow_index_reg = flag;
2100}
2101
cb19c032
L		 2102static void
2103set_sse_check (int dummy ATTRIBUTE_UNUSED)
2104{
2105 SKIP_WHITESPACE ();
2106
2107 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2108 {
2109 char *string = input_line_pointer;
2110 int e = get_symbol_end ();
2111
2112 if (strcmp (string, "none") == 0)
2113 sse_check = sse_check_none;
2114 else if (strcmp (string, "warning") == 0)
2115 sse_check = sse_check_warning;
2116 else if (strcmp (string, "error") == 0)
2117 sse_check = sse_check_error;
2118 else
2119 as_bad (_("bad argument to sse_check directive."));
2120 *input_line_pointer = e;
2121 }
2122 else
2123 as_bad (_("missing argument for sse_check directive"));
2124
2125 demand_empty_rest_of_line ();
2126}
2127
8a9036a4
L		 2128static void
2129check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2130 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2131{
2132#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2133 static const char *arch;
2134
2135 /* Intel LIOM is only supported on ELF. */
2136 if (!IS_ELF)
2137 return;
2138
2139 if (!arch)
2140 {
2141 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2142 use default_arch. */
2143 arch = cpu_arch_name;
2144 if (!arch)
2145 arch = default_arch;
2146 }
2147
3632d14b 2148 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2149 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2150 || new_flag.bitfield.cpul1om)
8a9036a4 2151 return;
76ba9986 2152
7a9068fe
L		 2153 /* If we are targeting Intel K1OM, we must enable it. */
2154 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2155 || new_flag.bitfield.cpuk1om)
2156 return;
2157
8a9036a4
L		 2158 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2159#endif
2160}
2161
e413e4e9 2162static void
e3bb37b5 2163set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2164{
47926f60 2165 SKIP_WHITESPACE ();
e413e4e9 2166
29b0f896 2167 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2168 {
2169 char *string = input_line_pointer;
2170 int e = get_symbol_end ();
91d6fa6a 2171 unsigned int j;
40fb9820 2172 i386_cpu_flags flags;
e413e4e9 2173
91d6fa6a 2174 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2175 {
91d6fa6a 2176 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2177 {
91d6fa6a 2178 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2179
5c6af06e
JB		 2180 if (*string != '.')
2181 {
91d6fa6a 2182 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2183 cpu_sub_arch_name = NULL;
91d6fa6a 2184 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2185 if (flag_code == CODE_64BIT)
2186 {
2187 cpu_arch_flags.bitfield.cpu64 = 1;
2188 cpu_arch_flags.bitfield.cpuno64 = 0;
2189 }
2190 else
2191 {
2192 cpu_arch_flags.bitfield.cpu64 = 0;
2193 cpu_arch_flags.bitfield.cpuno64 = 1;
2194 }
91d6fa6a
NC		 2195 cpu_arch_isa = cpu_arch[j].type;
2196 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2197 if (!cpu_arch_tune_set)
2198 {
2199 cpu_arch_tune = cpu_arch_isa;
2200 cpu_arch_tune_flags = cpu_arch_isa_flags;
2201 }
5c6af06e
JB		 2202 break;
2203 }
40fb9820 2204
22109423 2205 if (!cpu_arch[j].negated)
309d3373 2206 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2207 cpu_arch[j].flags);
309d3373
JB		 2208 else
2209 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2210 cpu_arch[j].flags);
0dfbf9d7 2211 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2212 {
6305a203
L		 2213 if (cpu_sub_arch_name)
2214 {
2215 char *name = cpu_sub_arch_name;
2216 cpu_sub_arch_name = concat (name,
91d6fa6a 2217 cpu_arch[j].name,
1bf57e9f 2218 (const char *) NULL);
6305a203
L		 2219 free (name);
2220 }
2221 else
91d6fa6a 2222 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2223 cpu_arch_flags = flags;
a586129e 2224 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2225 }
2226 *input_line_pointer = e;
2227 demand_empty_rest_of_line ();
2228 return;
e413e4e9
AM		 2229 }
2230 }
91d6fa6a 2231 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2232 as_bad (_("no such architecture: `%s'"), string);
2233
2234 *input_line_pointer = e;
2235 }
2236 else
2237 as_bad (_("missing cpu architecture"));
2238
fddf5b5b
AM		 2239 no_cond_jump_promotion = 0;
2240 if (*input_line_pointer == ','
29b0f896 2241 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2242 {
2243 char *string = ++input_line_pointer;
2244 int e = get_symbol_end ();
2245
2246 if (strcmp (string, "nojumps") == 0)
2247 no_cond_jump_promotion = 1;
2248 else if (strcmp (string, "jumps") == 0)
2249 ;
2250 else
2251 as_bad (_("no such architecture modifier: `%s'"), string);
2252
2253 *input_line_pointer = e;
2254 }
2255
e413e4e9
AM		 2256 demand_empty_rest_of_line ();
2257}
2258
8a9036a4
L		 2259enum bfd_architecture
2260i386_arch (void)
2261{
3632d14b 2262 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2263 {
2264 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2265 || flag_code != CODE_64BIT)
2266 as_fatal (_("Intel L1OM is 64bit ELF only"));
2267 return bfd_arch_l1om;
2268 }
7a9068fe
L		 2269 else if (cpu_arch_isa == PROCESSOR_K1OM)
2270 {
2271 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2272 || flag_code != CODE_64BIT)
2273 as_fatal (_("Intel K1OM is 64bit ELF only"));
2274 return bfd_arch_k1om;
2275 }
8a9036a4
L		 2276 else
2277 return bfd_arch_i386;
2278}
2279
b9d79e03 2280unsigned long
7016a5d5 2281i386_mach (void)
b9d79e03 2282{
351f65ca 2283 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2284 {
3632d14b 2285 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2286 {
351f65ca
L		 2287 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2288 || default_arch[6] != '\0')
8a9036a4
L		 2289 as_fatal (_("Intel L1OM is 64bit ELF only"));
2290 return bfd_mach_l1om;
2291 }
7a9068fe
L		 2292 else if (cpu_arch_isa == PROCESSOR_K1OM)
2293 {
2294 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2295 || default_arch[6] != '\0')
2296 as_fatal (_("Intel K1OM is 64bit ELF only"));
2297 return bfd_mach_k1om;
2298 }
351f65ca 2299 else if (default_arch[6] == '\0')
8a9036a4 2300 return bfd_mach_x86_64;
351f65ca
L		 2301 else
2302 return bfd_mach_x64_32;
8a9036a4 2303 }
b9d79e03
JH		 2304 else if (!strcmp (default_arch, "i386"))
2305 return bfd_mach_i386_i386;
2306 else
2b5d6a91 2307 as_fatal (_("unknown architecture"));
b9d79e03 2308}
b9d79e03 2309\f
252b5132 2310void
7016a5d5 2311md_begin (void)
252b5132
RH		 2312{
2313 const char *hash_err;
2314
47926f60 2315 /* Initialize op_hash hash table. */
252b5132
RH		 2316 op_hash = hash_new ();
2317
2318 {
d3ce72d0 2319 const insn_template *optab;
29b0f896 2320 templates *core_optab;
252b5132 2321
47926f60
KH		 2322 /* Setup for loop. */
2323 optab = i386_optab;
252b5132
RH		 2324 core_optab = (templates *) xmalloc (sizeof (templates));
2325 core_optab->start = optab;
2326
2327 while (1)
2328 {
2329 ++optab;
2330 if (optab->name == NULL
2331 || strcmp (optab->name, (optab - 1)->name) != 0)
2332 {
2333 /* different name --> ship out current template list;
47926f60 2334 add to hash table; & begin anew. */
252b5132
RH		 2335 core_optab->end = optab;
2336 hash_err = hash_insert (op_hash,
2337 (optab - 1)->name,
5a49b8ac 2338 (void *) core_optab);
252b5132
RH		 2339 if (hash_err)
2340 {
2b5d6a91 2341 as_fatal (_("internal Error: Can't hash %s: %s"),
252b5132
RH		 2342 (optab - 1)->name,
2343 hash_err);
2344 }
2345 if (optab->name == NULL)
2346 break;
2347 core_optab = (templates *) xmalloc (sizeof (templates));
2348 core_optab->start = optab;
2349 }
2350 }
2351 }
2352
47926f60 2353 /* Initialize reg_hash hash table. */
252b5132
RH		 2354 reg_hash = hash_new ();
2355 {
29b0f896 2356 const reg_entry *regtab;
c3fe08fa 2357 unsigned int regtab_size = i386_regtab_size;
252b5132 2358
c3fe08fa 2359 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2360 {
5a49b8ac 2361 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2362 if (hash_err)
2b5d6a91 2363 as_fatal (_("internal Error: Can't hash %s: %s"),
3e73aa7c
JH		 2364 regtab->reg_name,
2365 hash_err);
252b5132
RH		 2366 }
2367 }
2368
47926f60 2369 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2370 {
29b0f896
AM		 2371 int c;
2372 char *p;
252b5132
RH		 2373
2374 for (c = 0; c < 256; c++)
2375 {
3882b010 2376 if (ISDIGIT (c))
252b5132
RH		 2377 {
2378 digit_chars[c] = c;
2379 mnemonic_chars[c] = c;
2380 register_chars[c] = c;
2381 operand_chars[c] = c;
2382 }
3882b010 2383 else if (ISLOWER (c))
252b5132
RH		 2384 {
2385 mnemonic_chars[c] = c;
2386 register_chars[c] = c;
2387 operand_chars[c] = c;
2388 }
3882b010 2389 else if (ISUPPER (c))
252b5132 2390 {
3882b010 2391 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2392 register_chars[c] = mnemonic_chars[c];
2393 operand_chars[c] = c;
2394 }
2395
3882b010 2396 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2397 identifier_chars[c] = c;
2398 else if (c >= 128)
2399 {
2400 identifier_chars[c] = c;
2401 operand_chars[c] = c;
2402 }
2403 }
2404
2405#ifdef LEX_AT
2406 identifier_chars['@'] = '@';
32137342
NC		 2407#endif
2408#ifdef LEX_QM
2409 identifier_chars['?'] = '?';
2410 operand_chars['?'] = '?';
252b5132 2411#endif
252b5132 2412 digit_chars['-'] = '-';
c0f3af97 2413 mnemonic_chars['_'] = '_';
791fe849 2414 mnemonic_chars['-'] = '-';
0003779b 2415 mnemonic_chars['.'] = '.';
252b5132
RH		 2416 identifier_chars['_'] = '_';
2417 identifier_chars['.'] = '.';
2418
2419 for (p = operand_special_chars; *p != '\0'; p++)
2420 operand_chars[(unsigned char) *p] = *p;
2421 }
2422
2423#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2424 if (IS_ELF)
252b5132
RH		 2425 {
2426 record_alignment (text_section, 2);
2427 record_alignment (data_section, 2);
2428 record_alignment (bss_section, 2);
2429 }
2430#endif
a4447b93
RH		 2431
2432 if (flag_code == CODE_64BIT)
2433 {
ca19b261
KT		 2434#if defined (OBJ_COFF) && defined (TE_PE)
2435 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2436 ? 32 : 16);
2437#else
a4447b93 2438 x86_dwarf2_return_column = 16;
ca19b261 2439#endif
61ff971f 2440 x86_cie_data_alignment = -8;
a4447b93
RH		 2441 }
2442 else
2443 {
2444 x86_dwarf2_return_column = 8;
2445 x86_cie_data_alignment = -4;
2446 }
252b5132
RH		 2447}
2448
2449void
e3bb37b5 2450i386_print_statistics (FILE *file)
252b5132
RH		 2451{
2452 hash_print_statistics (file, "i386 opcode", op_hash);
2453 hash_print_statistics (file, "i386 register", reg_hash);
2454}
2455\f
252b5132
RH		 2456#ifdef DEBUG386
2457
ce8a8b2f 2458/* Debugging routines for md_assemble. */
d3ce72d0 2459static void pte (insn_template *);
40fb9820 2460static void pt (i386_operand_type);
e3bb37b5
L		 2461static void pe (expressionS *);
2462static void ps (symbolS *);
252b5132
RH		 2463
2464static void
e3bb37b5 2465pi (char *line, i386_insn *x)
252b5132 2466{
09137c09 2467 unsigned int j;
252b5132
RH		 2468
2469 fprintf (stdout, "%s: template ", line);
2470 pte (&x->tm);
09f131f2
JH		 2471 fprintf (stdout, " address: base %s index %s scale %x\n",
2472 x->base_reg ? x->base_reg->reg_name : "none",
2473 x->index_reg ? x->index_reg->reg_name : "none",
2474 x->log2_scale_factor);
2475 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2476 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2477 fprintf (stdout, " sib: base %x index %x scale %x\n",
2478 x->sib.base, x->sib.index, x->sib.scale);
2479 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2480 (x->rex & REX_W) != 0,
2481 (x->rex & REX_R) != 0,
2482 (x->rex & REX_X) != 0,
2483 (x->rex & REX_B) != 0);
09137c09 2484 for (j = 0; j < x->operands; j++)
252b5132 2485 {
09137c09
SP		 2486 fprintf (stdout, " #%d: ", j + 1);
2487 pt (x->types[j]);
252b5132 2488 fprintf (stdout, "\n");
09137c09
SP		 2489 if (x->types[j].bitfield.reg8
2490 || x->types[j].bitfield.reg16
2491 || x->types[j].bitfield.reg32
2492 || x->types[j].bitfield.reg64
2493 || x->types[j].bitfield.regmmx
2494 || x->types[j].bitfield.regxmm
2495 || x->types[j].bitfield.regymm
2496 || x->types[j].bitfield.sreg2
2497 || x->types[j].bitfield.sreg3
2498 || x->types[j].bitfield.control
2499 || x->types[j].bitfield.debug
2500 || x->types[j].bitfield.test)
2501 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2502 if (operand_type_check (x->types[j], imm))
2503 pe (x->op[j].imms);
2504 if (operand_type_check (x->types[j], disp))
2505 pe (x->op[j].disps);
252b5132
RH		 2506 }
2507}
2508
2509static void
d3ce72d0 2510pte (insn_template *t)
252b5132 2511{
09137c09 2512 unsigned int j;
252b5132 2513 fprintf (stdout, " %d operands ", t->operands);
47926f60 2514 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2515 if (t->extension_opcode != None)
2516 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2517 if (t->opcode_modifier.d)
252b5132 2518 fprintf (stdout, "D");
40fb9820 2519 if (t->opcode_modifier.w)
252b5132
RH		 2520 fprintf (stdout, "W");
2521 fprintf (stdout, "\n");
09137c09 2522 for (j = 0; j < t->operands; j++)
252b5132 2523 {
09137c09
SP		 2524 fprintf (stdout, " #%d type ", j + 1);
2525 pt (t->operand_types[j]);
252b5132
RH		 2526 fprintf (stdout, "\n");
2527 }
2528}
2529
2530static void
e3bb37b5 2531pe (expressionS *e)
252b5132 2532{
24eab124 2533 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2534 fprintf (stdout, " add_number %ld (%lx)\n",
2535 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2536 if (e->X_add_symbol)
2537 {
2538 fprintf (stdout, " add_symbol ");
2539 ps (e->X_add_symbol);
2540 fprintf (stdout, "\n");
2541 }
2542 if (e->X_op_symbol)
2543 {
2544 fprintf (stdout, " op_symbol ");
2545 ps (e->X_op_symbol);
2546 fprintf (stdout, "\n");
2547 }
2548}
2549
2550static void
e3bb37b5 2551ps (symbolS *s)
252b5132
RH		 2552{
2553 fprintf (stdout, "%s type %s%s",
2554 S_GET_NAME (s),
2555 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2556 segment_name (S_GET_SEGMENT (s)));
2557}
2558
7b81dfbb 2559static struct type_name
252b5132 2560 {
40fb9820
L		 2561 i386_operand_type mask;
2562 const char *name;
252b5132 2563 }
7b81dfbb 2564const type_names[] =
252b5132 2565{
40fb9820
L		 2566 { OPERAND_TYPE_REG8, "r8" },
2567 { OPERAND_TYPE_REG16, "r16" },
2568 { OPERAND_TYPE_REG32, "r32" },
2569 { OPERAND_TYPE_REG64, "r64" },
2570 { OPERAND_TYPE_IMM8, "i8" },
2571 { OPERAND_TYPE_IMM8, "i8s" },
2572 { OPERAND_TYPE_IMM16, "i16" },
2573 { OPERAND_TYPE_IMM32, "i32" },
2574 { OPERAND_TYPE_IMM32S, "i32s" },
2575 { OPERAND_TYPE_IMM64, "i64" },
2576 { OPERAND_TYPE_IMM1, "i1" },
2577 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2578 { OPERAND_TYPE_DISP8, "d8" },
2579 { OPERAND_TYPE_DISP16, "d16" },
2580 { OPERAND_TYPE_DISP32, "d32" },
2581 { OPERAND_TYPE_DISP32S, "d32s" },
2582 { OPERAND_TYPE_DISP64, "d64" },
2583 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2584 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2585 { OPERAND_TYPE_CONTROL, "control reg" },
2586 { OPERAND_TYPE_TEST, "test reg" },
2587 { OPERAND_TYPE_DEBUG, "debug reg" },
2588 { OPERAND_TYPE_FLOATREG, "FReg" },
2589 { OPERAND_TYPE_FLOATACC, "FAcc" },
2590 { OPERAND_TYPE_SREG2, "SReg2" },
2591 { OPERAND_TYPE_SREG3, "SReg3" },
2592 { OPERAND_TYPE_ACC, "Acc" },
2593 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2594 { OPERAND_TYPE_REGMMX, "rMMX" },
2595 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2596 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2597 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2598};
2599
2600static void
40fb9820 2601pt (i386_operand_type t)
252b5132 2602{
40fb9820 2603 unsigned int j;
c6fb90c8 2604 i386_operand_type a;
252b5132 2605
40fb9820 2606 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2607 {
2608 a = operand_type_and (t, type_names[j].mask);
0349dc08 2609 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2610 fprintf (stdout, "%s, ", type_names[j].name);
2611 }
252b5132
RH		 2612 fflush (stdout);
2613}
2614
2615#endif /* DEBUG386 */
2616\f
252b5132 2617static bfd_reloc_code_real_type
3956db08 2618reloc (unsigned int size,
64e74474
AM		 2619 int pcrel,
2620 int sign,
2621 bfd_reloc_code_real_type other)
252b5132 2622{
47926f60 2623 if (other != NO_RELOC)
3956db08 2624 {
91d6fa6a 2625 reloc_howto_type *rel;
3956db08
JB		 2626
2627 if (size == 8)
2628 switch (other)
2629 {
64e74474
AM		 2630 case BFD_RELOC_X86_64_GOT32:
2631 return BFD_RELOC_X86_64_GOT64;
2632 break;
2633 case BFD_RELOC_X86_64_PLTOFF64:
2634 return BFD_RELOC_X86_64_PLTOFF64;
2635 break;
2636 case BFD_RELOC_X86_64_GOTPC32:
2637 other = BFD_RELOC_X86_64_GOTPC64;
2638 break;
2639 case BFD_RELOC_X86_64_GOTPCREL:
2640 other = BFD_RELOC_X86_64_GOTPCREL64;
2641 break;
2642 case BFD_RELOC_X86_64_TPOFF32:
2643 other = BFD_RELOC_X86_64_TPOFF64;
2644 break;
2645 case BFD_RELOC_X86_64_DTPOFF32:
2646 other = BFD_RELOC_X86_64_DTPOFF64;
2647 break;
2648 default:
2649 break;
3956db08 2650 }
e05278af
JB		 2651
2652 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2653 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2654 sign = -1;
2655
91d6fa6a
NC		 2656 rel = bfd_reloc_type_lookup (stdoutput, other);
2657 if (!rel)
3956db08 2658 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2659 else if (size != bfd_get_reloc_size (rel))
3956db08 2660 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2661 bfd_get_reloc_size (rel),
3956db08 2662 size);
91d6fa6a 2663 else if (pcrel && !rel->pc_relative)
3956db08 2664 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2665 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2666 && !sign)
91d6fa6a 2667 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2668 && sign > 0))
3956db08
JB		 2669 as_bad (_("relocated field and relocation type differ in signedness"));
2670 else
2671 return other;
2672 return NO_RELOC;
2673 }
252b5132
RH		 2674
2675 if (pcrel)
2676 {
3e73aa7c 2677 if (!sign)
3956db08 2678 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2679 switch (size)
2680 {
2681 case 1: return BFD_RELOC_8_PCREL;
2682 case 2: return BFD_RELOC_16_PCREL;
2683 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2684 case 8: return BFD_RELOC_64_PCREL;
252b5132 2685 }
3956db08 2686 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2687 }
2688 else
2689 {
3956db08 2690 if (sign > 0)
e5cb08ac 2691 switch (size)
3e73aa7c
JH		 2692 {
2693 case 4: return BFD_RELOC_X86_64_32S;
2694 }
2695 else
2696 switch (size)
2697 {
2698 case 1: return BFD_RELOC_8;
2699 case 2: return BFD_RELOC_16;
2700 case 4: return BFD_RELOC_32;
2701 case 8: return BFD_RELOC_64;
2702 }
3956db08
JB		 2703 as_bad (_("cannot do %s %u byte relocation"),
2704 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2705 }
2706
0cc9e1d3 2707 return NO_RELOC;
252b5132
RH		 2708}
2709
47926f60
KH		 2710/* Here we decide which fixups can be adjusted to make them relative to
2711 the beginning of the section instead of the symbol. Basically we need
2712 to make sure that the dynamic relocations are done correctly, so in
2713 some cases we force the original symbol to be used. */
2714
252b5132 2715int
e3bb37b5 2716tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2717{
6d249963 2718#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2719 if (!IS_ELF)
31312f95
AM		 2720 return 1;
2721
a161fe53
AM		 2722 /* Don't adjust pc-relative references to merge sections in 64-bit
2723 mode. */
2724 if (use_rela_relocations
2725 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2726 && fixP->fx_pcrel)
252b5132 2727 return 0;
31312f95 2728
8d01d9a9
AJ		 2729 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2730 and changed later by validate_fix. */
2731 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2732 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2733 return 0;
2734
ce8a8b2f 2735 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2736 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2737 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2738 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2739 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2740 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2741 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2742 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2743 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2744 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2745 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2746 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2747 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2748 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2749 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2750 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2751 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2752 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2753 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2754 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2755 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2756 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2757 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2758 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2759 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2760 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2761 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2762 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2763 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2764 return 0;
31312f95 2765#endif
252b5132
RH		 2766 return 1;
2767}
252b5132 2768
b4cac588 2769static int
e3bb37b5 2770intel_float_operand (const char *mnemonic)
252b5132 2771{
9306ca4a
JB		 2772 /* Note that the value returned is meaningful only for opcodes with (memory)
2773 operands, hence the code here is free to improperly handle opcodes that
2774 have no operands (for better performance and smaller code). */
2775
2776 if (mnemonic[0] != 'f')
2777 return 0; /* non-math */
2778
2779 switch (mnemonic[1])
2780 {
2781 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2782 the fs segment override prefix not currently handled because no
2783 call path can make opcodes without operands get here */
2784 case 'i':
2785 return 2 /* integer op */;
2786 case 'l':
2787 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2788 return 3; /* fldcw/fldenv */
2789 break;
2790 case 'n':
2791 if (mnemonic[2] != 'o' /* fnop */)
2792 return 3; /* non-waiting control op */
2793 break;
2794 case 'r':
2795 if (mnemonic[2] == 's')
2796 return 3; /* frstor/frstpm */
2797 break;
2798 case 's':
2799 if (mnemonic[2] == 'a')
2800 return 3; /* fsave */
2801 if (mnemonic[2] == 't')
2802 {
2803 switch (mnemonic[3])
2804 {
2805 case 'c': /* fstcw */
2806 case 'd': /* fstdw */
2807 case 'e': /* fstenv */
2808 case 's': /* fsts[gw] */
2809 return 3;
2810 }
2811 }
2812 break;
2813 case 'x':
2814 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2815 return 0; /* fxsave/fxrstor are not really math ops */
2816 break;
2817 }
252b5132 2818
9306ca4a 2819 return 1;
252b5132
RH		 2820}
2821
c0f3af97
L		 2822/* Build the VEX prefix. */
2823
2824static void
d3ce72d0 2825build_vex_prefix (const insn_template *t)
c0f3af97
L		 2826{
2827 unsigned int register_specifier;
2828 unsigned int implied_prefix;
2829 unsigned int vector_length;
2830
2831 /* Check register specifier. */
2832 if (i.vex.register_specifier)
2833 {
2834 register_specifier = i.vex.register_specifier->reg_num;
2835 if ((i.vex.register_specifier->reg_flags & RegRex))
2836 register_specifier += 8;
2837 register_specifier = ~register_specifier & 0xf;
2838 }
2839 else
2840 register_specifier = 0xf;
2841
fa99fab2
L		 2842 /* Use 2-byte VEX prefix by swappping destination and source
2843 operand. */
2844 if (!i.swap_operand
2845 && i.operands == i.reg_operands
7f399153 2846 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2847 && i.tm.opcode_modifier.s
2848 && i.rex == REX_B)
2849 {
2850 unsigned int xchg = i.operands - 1;
2851 union i386_op temp_op;
2852 i386_operand_type temp_type;
2853
2854 temp_type = i.types[xchg];
2855 i.types[xchg] = i.types[0];
2856 i.types[0] = temp_type;
2857 temp_op = i.op[xchg];
2858 i.op[xchg] = i.op[0];
2859 i.op[0] = temp_op;
2860
9c2799c2 2861 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2862
2863 i.rex = REX_R;
2864 xchg = i.rm.regmem;
2865 i.rm.regmem = i.rm.reg;
2866 i.rm.reg = xchg;
2867
2868 /* Use the next insn. */
2869 i.tm = t[1];
2870 }
2871
539f890d
L		 2872 if (i.tm.opcode_modifier.vex == VEXScalar)
2873 vector_length = avxscalar;
2874 else
2875 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2876
2877 switch ((i.tm.base_opcode >> 8) & 0xff)
2878 {
2879 case 0:
2880 implied_prefix = 0;
2881 break;
2882 case DATA_PREFIX_OPCODE:
2883 implied_prefix = 1;
2884 break;
2885 case REPE_PREFIX_OPCODE:
2886 implied_prefix = 2;
2887 break;
2888 case REPNE_PREFIX_OPCODE:
2889 implied_prefix = 3;
2890 break;
2891 default:
2892 abort ();
2893 }
2894
2895 /* Use 2-byte VEX prefix if possible. */
7f399153 2896 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 2897 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 2898 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2899 {
2900 /* 2-byte VEX prefix. */
2901 unsigned int r;
2902
2903 i.vex.length = 2;
2904 i.vex.bytes[0] = 0xc5;
2905
2906 /* Check the REX.R bit. */
2907 r = (i.rex & REX_R) ? 0 : 1;
2908 i.vex.bytes[1] = (r << 7
2909 | register_specifier << 3
2910 | vector_length << 2
2911 | implied_prefix);
2912 }
2913 else
2914 {
2915 /* 3-byte VEX prefix. */
2916 unsigned int m, w;
2917
f88c9eb0 2918 i.vex.length = 3;
f88c9eb0 2919
7f399153 2920 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2921 {
7f399153
L		 2922 case VEX0F:
2923 m = 0x1;
80de6e00 2924 i.vex.bytes[0] = 0xc4;
7f399153
L		 2925 break;
2926 case VEX0F38:
2927 m = 0x2;
80de6e00 2928 i.vex.bytes[0] = 0xc4;
7f399153
L		 2929 break;
2930 case VEX0F3A:
2931 m = 0x3;
80de6e00 2932 i.vex.bytes[0] = 0xc4;
7f399153
L		 2933 break;
2934 case XOP08:
5dd85c99
SP		 2935 m = 0x8;
2936 i.vex.bytes[0] = 0x8f;
7f399153
L		 2937 break;
2938 case XOP09:
f88c9eb0
SP		 2939 m = 0x9;
2940 i.vex.bytes[0] = 0x8f;
7f399153
L		 2941 break;
2942 case XOP0A:
f88c9eb0
SP		 2943 m = 0xa;
2944 i.vex.bytes[0] = 0x8f;
7f399153
L		 2945 break;
2946 default:
2947 abort ();
f88c9eb0 2948 }
c0f3af97 2949
c0f3af97
L		 2950 /* The high 3 bits of the second VEX byte are 1's compliment
2951 of RXB bits from REX. */
2952 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2953
2954 /* Check the REX.W bit. */
2955 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 2956 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 2957 {
2958 if (w)
2959 abort ();
2960
1ef99a7b 2961 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 2962 w = 1;
2963 }
2964
2965 i.vex.bytes[2] = (w << 7
2966 | register_specifier << 3
2967 | vector_length << 2
2968 | implied_prefix);
2969 }
2970}
2971
65da13b5
L		 2972static void
2973process_immext (void)
2974{
2975 expressionS *exp;
2976
2977 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2978 {
1fed0ba1
L		 2979 /* SSE3 Instructions have the fixed operands with an opcode
2980 suffix which is coded in the same place as an 8-bit immediate
2981 field would be. Here we check those operands and remove them
2982 afterwards. */
65da13b5
L		 2983 unsigned int x;
2984
2985 for (x = 0; x < i.operands; x++)
2986 if (i.op[x].regs->reg_num != x)
2987 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2988 register_prefix, i.op[x].regs->reg_name, x + 1,
2989 i.tm.name);
2990
2991 i.operands = 0;
65da13b5
L		 2992 }
2993
c0f3af97 2994 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2995 which is coded in the same place as an 8-bit immediate field
2996 would be. Here we fake an 8-bit immediate operand from the
2997 opcode suffix stored in tm.extension_opcode.
2998
c1e679ec 2999 AVX instructions also use this encoding, for some of
c0f3af97 3000 3 argument instructions. */
65da13b5 3001
9c2799c2 3002 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 3003 && (i.operands <= 2
3004 || (i.tm.opcode_modifier.vex
3005 && i.operands <= 4)));
65da13b5
L		 3006
3007 exp = &im_expressions[i.imm_operands++];
3008 i.op[i.operands].imms = exp;
3009 i.types[i.operands] = imm8;
3010 i.operands++;
3011 exp->X_op = O_constant;
3012 exp->X_add_number = i.tm.extension_opcode;
3013 i.tm.extension_opcode = None;
3014}
3015
42164a71
L		 3016
3017static int
3018check_hle (void)
3019{
3020 switch (i.tm.opcode_modifier.hleprefixok)
3021 {
3022 default:
3023 abort ();
82c2def5 3024 case HLEPrefixNone:
42164a71
L		 3025 if (i.prefix[HLE_PREFIX] == XACQUIRE_PREFIX_OPCODE)
3026 as_bad (_("invalid instruction `%s' after `xacquire'"),
3027 i.tm.name);
3028 else
3029 as_bad (_("invalid instruction `%s' after `xrelease'"),
3030 i.tm.name);
3031 return 0;
82c2def5 3032 case HLEPrefixLock:
42164a71
L		 3033 if (i.prefix[LOCK_PREFIX])
3034 return 1;
3035 if (i.prefix[HLE_PREFIX] == XACQUIRE_PREFIX_OPCODE)
3036 as_bad (_("missing `lock' with `xacquire'"));
3037 else
3038 as_bad (_("missing `lock' with `xrelease'"));
3039 return 0;
82c2def5 3040 case HLEPrefixAny:
42164a71 3041 return 1;
82c2def5 3042 case HLEPrefixRelease:
42164a71
L		 3043 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3044 {
3045 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3046 i.tm.name);
3047 return 0;
3048 }
3049 if (i.mem_operands == 0
3050 || !operand_type_check (i.types[i.operands - 1], anymem))
3051 {
3052 as_bad (_("memory destination needed for instruction `%s'"
3053 " after `xrelease'"), i.tm.name);
3054 return 0;
3055 }
3056 return 1;
3057 }
3058}
3059
252b5132
RH		 3060/* This is the guts of the machine-dependent assembler. LINE points to a
3061 machine dependent instruction. This function is supposed to emit
3062 the frags/bytes it assembles to. */
3063
3064void
65da13b5 3065md_assemble (char *line)
252b5132 3066{
40fb9820 3067 unsigned int j;
252b5132 3068 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3069 const insn_template *t;
252b5132 3070
47926f60 3071 /* Initialize globals. */
252b5132
RH		 3072 memset (&i, '\0', sizeof (i));
3073 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3074 i.reloc[j] = NO_RELOC;
252b5132
RH		 3075 memset (disp_expressions, '\0', sizeof (disp_expressions));
3076 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3077 save_stack_p = save_stack;
252b5132
RH		 3078
3079 /* First parse an instruction mnemonic & call i386_operand for the operands.
3080 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3081 start of a (possibly prefixed) mnemonic. */
252b5132 3082
29b0f896
AM		 3083 line = parse_insn (line, mnemonic);
3084 if (line == NULL)
3085 return;
252b5132 3086
29b0f896 3087 line = parse_operands (line, mnemonic);
ee86248c 3088 this_operand = -1;
29b0f896
AM		 3089 if (line == NULL)
3090 return;
252b5132 3091
29b0f896
AM		 3092 /* Now we've parsed the mnemonic into a set of templates, and have the
3093 operands at hand. */
3094
3095 /* All intel opcodes have reversed operands except for "bound" and
3096 "enter". We also don't reverse intersegment "jmp" and "call"
3097 instructions with 2 immediate operands so that the immediate segment
050dfa73 3098 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3099 if (intel_syntax
3100 && i.operands > 1
29b0f896 3101 && (strcmp (mnemonic, "bound") != 0)
30123838 3102 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3103 && !(operand_type_check (i.types[0], imm)
3104 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3105 swap_operands ();
3106
ec56d5c0
JB		 3107 /* The order of the immediates should be reversed
3108 for 2 immediates extrq and insertq instructions */
3109 if (i.imm_operands == 2
3110 && (strcmp (mnemonic, "extrq") == 0
3111 || strcmp (mnemonic, "insertq") == 0))
3112 swap_2_operands (0, 1);
3113
29b0f896
AM		 3114 if (i.imm_operands)
3115 optimize_imm ();
3116
b300c311
L		 3117 /* Don't optimize displacement for movabs since it only takes 64bit
3118 displacement. */
3119 if (i.disp_operands
a501d77e 3120 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3121 && (flag_code != CODE_64BIT
3122 || strcmp (mnemonic, "movabs") != 0))
3123 optimize_disp ();
29b0f896
AM		 3124
3125 /* Next, we find a template that matches the given insn,
3126 making sure the overlap of the given operands types is consistent
3127 with the template operand types. */
252b5132 3128
fa99fab2 3129 if (!(t = match_template ()))
29b0f896 3130 return;
252b5132 3131
daf50ae7 3132 if (sse_check != sse_check_none
81f8a913 3133 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3134 && (i.tm.cpu_flags.bitfield.cpusse
3135 || i.tm.cpu_flags.bitfield.cpusse2
3136 || i.tm.cpu_flags.bitfield.cpusse3
3137 || i.tm.cpu_flags.bitfield.cpussse3
3138 || i.tm.cpu_flags.bitfield.cpusse4_1
3139 || i.tm.cpu_flags.bitfield.cpusse4_2))
3140 {
3141 (sse_check == sse_check_warning
3142 ? as_warn
3143 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3144 }
3145
321fd21e
L		 3146 /* Zap movzx and movsx suffix. The suffix has been set from
3147 "word ptr" or "byte ptr" on the source operand in Intel syntax
3148 or extracted from mnemonic in AT&T syntax. But we'll use
3149 the destination register to choose the suffix for encoding. */
3150 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3151 {
321fd21e
L		 3152 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3153 there is no suffix, the default will be byte extension. */
3154 if (i.reg_operands != 2
3155 && !i.suffix
7ab9ffdd 3156 && intel_syntax)
321fd21e
L		 3157 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3158
3159 i.suffix = 0;
cd61ebfe 3160 }
24eab124 3161
40fb9820 3162 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3163 if (!add_prefix (FWAIT_OPCODE))
3164 return;
252b5132 3165
c1ba0266
L		 3166 /* Check for lock without a lockable instruction. Destination operand
3167 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3168 if (i.prefix[LOCK_PREFIX]
3169 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3170 || i.mem_operands == 0
3171 || (i.tm.base_opcode != 0x86
3172 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3173 {
3174 as_bad (_("expecting lockable instruction after `lock'"));
3175 return;
3176 }
3177
42164a71
L		 3178 /* Check if HLE prefix is OK. */
3179 if (i.have_hle && !check_hle ())
3180 return;
3181
29b0f896 3182 /* Check string instruction segment overrides. */
40fb9820 3183 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3184 {
3185 if (!check_string ())
5dd0794d 3186 return;
fc0763e6 3187 i.disp_operands = 0;
29b0f896 3188 }
5dd0794d 3189
29b0f896
AM		 3190 if (!process_suffix ())
3191 return;
e413e4e9 3192
bc0844ae
L		 3193 /* Update operand types. */
3194 for (j = 0; j < i.operands; j++)
3195 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3196
29b0f896
AM		 3197 /* Make still unresolved immediate matches conform to size of immediate
3198 given in i.suffix. */
3199 if (!finalize_imm ())
3200 return;
252b5132 3201
40fb9820 3202 if (i.types[0].bitfield.imm1)
29b0f896 3203 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3204
9afe6eb8
L		 3205 /* We only need to check those implicit registers for instructions
3206 with 3 operands or less. */
3207 if (i.operands <= 3)
3208 for (j = 0; j < i.operands; j++)
3209 if (i.types[j].bitfield.inoutportreg
3210 || i.types[j].bitfield.shiftcount
3211 || i.types[j].bitfield.acc
3212 || i.types[j].bitfield.floatacc)
3213 i.reg_operands--;
40fb9820 3214
c0f3af97
L		 3215 /* ImmExt should be processed after SSE2AVX. */
3216 if (!i.tm.opcode_modifier.sse2avx
3217 && i.tm.opcode_modifier.immext)
65da13b5 3218 process_immext ();
252b5132 3219
29b0f896
AM		 3220 /* For insns with operands there are more diddles to do to the opcode. */
3221 if (i.operands)
3222 {
3223 if (!process_operands ())
3224 return;
3225 }
40fb9820 3226 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3227 {
3228 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3229 as_warn (_("translating to `%sp'"), i.tm.name);
3230 }
252b5132 3231
c0f3af97 3232 if (i.tm.opcode_modifier.vex)
fa99fab2 3233 build_vex_prefix (t);
c0f3af97 3234
5dd85c99
SP		 3235 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3236 instructions may define INT_OPCODE as well, so avoid this corner
3237 case for those instructions that use MODRM. */
3238 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3239 && !i.tm.opcode_modifier.modrm
3240 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3241 {
3242 i.tm.base_opcode = INT3_OPCODE;
3243 i.imm_operands = 0;
3244 }
252b5132 3245
40fb9820
L		 3246 if ((i.tm.opcode_modifier.jump
3247 || i.tm.opcode_modifier.jumpbyte
3248 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3249 && i.op[0].disps->X_op == O_constant)
3250 {
3251 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3252 the absolute address given by the constant. Since ix86 jumps and
3253 calls are pc relative, we need to generate a reloc. */
3254 i.op[0].disps->X_add_symbol = &abs_symbol;
3255 i.op[0].disps->X_op = O_symbol;
3256 }
252b5132 3257
40fb9820 3258 if (i.tm.opcode_modifier.rex64)
161a04f6 3259 i.rex |= REX_W;
252b5132 3260
29b0f896
AM		 3261 /* For 8 bit registers we need an empty rex prefix. Also if the
3262 instruction already has a prefix, we need to convert old
3263 registers to new ones. */
773f551c 3264
40fb9820 3265 if ((i.types[0].bitfield.reg8
29b0f896 3266 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3267 || (i.types[1].bitfield.reg8
29b0f896 3268 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3269 || ((i.types[0].bitfield.reg8
3270 || i.types[1].bitfield.reg8)
29b0f896
AM		 3271 && i.rex != 0))
3272 {
3273 int x;
726c5dcd 3274
29b0f896
AM		 3275 i.rex |= REX_OPCODE;
3276 for (x = 0; x < 2; x++)
3277 {
3278 /* Look for 8 bit operand that uses old registers. */
40fb9820 3279 if (i.types[x].bitfield.reg8
29b0f896 3280 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3281 {
29b0f896
AM		 3282 /* In case it is "hi" register, give up. */
3283 if (i.op[x].regs->reg_num > 3)
a540244d 3284 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3285 "instruction requiring REX prefix."),
a540244d 3286 register_prefix, i.op[x].regs->reg_name);
773f551c 3287
29b0f896
AM		 3288 /* Otherwise it is equivalent to the extended register.
3289 Since the encoding doesn't change this is merely
3290 cosmetic cleanup for debug output. */
3291
3292 i.op[x].regs = i.op[x].regs + 8;
773f551c 3293 }
29b0f896
AM		 3294 }
3295 }
773f551c 3296
7ab9ffdd 3297 if (i.rex != 0)
29b0f896
AM		 3298 add_prefix (REX_OPCODE | i.rex);
3299
3300 /* We are ready to output the insn. */
3301 output_insn ();
3302}
3303
3304static char *
e3bb37b5 3305parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3306{
3307 char *l = line;
3308 char *token_start = l;
3309 char *mnem_p;
5c6af06e 3310 int supported;
d3ce72d0 3311 const insn_template *t;
b6169b20 3312 char *dot_p = NULL;
29b0f896
AM		 3313
3314 /* Non-zero if we found a prefix only acceptable with string insns. */
3315 const char *expecting_string_instruction = NULL;
45288df1 3316
29b0f896
AM		 3317 while (1)
3318 {
3319 mnem_p = mnemonic;
3320 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3321 {
b6169b20
L		 3322 if (*mnem_p == '.')
3323 dot_p = mnem_p;
29b0f896
AM		 3324 mnem_p++;
3325 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3326 {
29b0f896
AM		 3327 as_bad (_("no such instruction: `%s'"), token_start);
3328 return NULL;
3329 }
3330 l++;
3331 }
3332 if (!is_space_char (*l)
3333 && *l != END_OF_INSN
e44823cf
JB		 3334 && (intel_syntax
3335 || (*l != PREFIX_SEPARATOR
3336 && *l != ',')))
29b0f896
AM		 3337 {
3338 as_bad (_("invalid character %s in mnemonic"),
3339 output_invalid (*l));
3340 return NULL;
3341 }
3342 if (token_start == l)
3343 {
e44823cf 3344 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3345 as_bad (_("expecting prefix; got nothing"));
3346 else
3347 as_bad (_("expecting mnemonic; got nothing"));
3348 return NULL;
3349 }
45288df1 3350
29b0f896 3351 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3352 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3353
29b0f896
AM		 3354 if (*l != END_OF_INSN
3355 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3356 && current_templates
40fb9820 3357 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3358 {
c6fb90c8 3359 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3360 {
3361 as_bad ((flag_code != CODE_64BIT
3362 ? _("`%s' is only supported in 64-bit mode")
3363 : _("`%s' is not supported in 64-bit mode")),
3364 current_templates->start->name);
3365 return NULL;
3366 }
29b0f896
AM		 3367 /* If we are in 16-bit mode, do not allow addr16 or data16.
3368 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3369 if ((current_templates->start->opcode_modifier.size16
3370 || current_templates->start->opcode_modifier.size32)
29b0f896 3371 && flag_code != CODE_64BIT
40fb9820 3372 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3373 ^ (flag_code == CODE_16BIT)))
3374 {
3375 as_bad (_("redundant %s prefix"),
3376 current_templates->start->name);
3377 return NULL;
45288df1 3378 }
29b0f896
AM		 3379 /* Add prefix, checking for repeated prefixes. */
3380 switch (add_prefix (current_templates->start->base_opcode))
3381 {
c32fa91d 3382 case PREFIX_EXIST:
29b0f896 3383 return NULL;
c32fa91d 3384 case PREFIX_REP:
42164a71
L		 3385 if (current_templates->start->cpu_flags.bitfield.cpuhle)
3386 i.have_hle = 1;
3387 else
3388 expecting_string_instruction = current_templates->start->name;
29b0f896 3389 break;
c32fa91d
L		 3390 default:
3391 break;
29b0f896
AM		 3392 }
3393 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3394 token_start = ++l;
3395 }
3396 else
3397 break;
3398 }
45288df1 3399
30a55f88 3400 if (!current_templates)
b6169b20 3401 {
f8a5c266
L		 3402 /* Check if we should swap operand or force 32bit displacement in
3403 encoding. */
30a55f88
L		 3404 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3405 i.swap_operand = 1;
8d63c93e 3406 else if (mnem_p - 3 == dot_p
a501d77e
L		 3407 && dot_p[1] == 'd'
3408 && dot_p[2] == '8')
3409 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3410 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3411 && dot_p[1] == 'd'
3412 && dot_p[2] == '3'
3413 && dot_p[3] == '2')
a501d77e 3414 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3415 else
3416 goto check_suffix;
3417 mnem_p = dot_p;
3418 *dot_p = '\0';
d3ce72d0 3419 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3420 }
3421
29b0f896
AM		 3422 if (!current_templates)
3423 {
b6169b20 3424check_suffix:
29b0f896
AM		 3425 /* See if we can get a match by trimming off a suffix. */
3426 switch (mnem_p[-1])
3427 {
3428 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3429 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3430 i.suffix = SHORT_MNEM_SUFFIX;
3431 else
29b0f896
AM		 3432 case BYTE_MNEM_SUFFIX:
3433 case QWORD_MNEM_SUFFIX:
3434 i.suffix = mnem_p[-1];
3435 mnem_p[-1] = '\0';
d3ce72d0
NC		 3436 current_templates = (const templates *) hash_find (op_hash,
3437 mnemonic);
29b0f896
AM		 3438 break;
3439 case SHORT_MNEM_SUFFIX:
3440 case LONG_MNEM_SUFFIX:
3441 if (!intel_syntax)
3442 {
3443 i.suffix = mnem_p[-1];
3444 mnem_p[-1] = '\0';
d3ce72d0
NC		 3445 current_templates = (const templates *) hash_find (op_hash,
3446 mnemonic);
29b0f896
AM		 3447 }
3448 break;
252b5132 3449
29b0f896
AM		 3450 /* Intel Syntax. */
3451 case 'd':
3452 if (intel_syntax)
3453 {
9306ca4a 3454 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3455 i.suffix = SHORT_MNEM_SUFFIX;
3456 else
3457 i.suffix = LONG_MNEM_SUFFIX;
3458 mnem_p[-1] = '\0';
d3ce72d0
NC		 3459 current_templates = (const templates *) hash_find (op_hash,
3460 mnemonic);
29b0f896
AM		 3461 }
3462 break;
3463 }
3464 if (!current_templates)
3465 {
3466 as_bad (_("no such instruction: `%s'"), token_start);
3467 return NULL;
3468 }
3469 }
252b5132 3470
40fb9820
L		 3471 if (current_templates->start->opcode_modifier.jump
3472 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3473 {
3474 /* Check for a branch hint. We allow ",pt" and ",pn" for
3475 predict taken and predict not taken respectively.
3476 I'm not sure that branch hints actually do anything on loop
3477 and jcxz insns (JumpByte) for current Pentium4 chips. They
3478 may work in the future and it doesn't hurt to accept them
3479 now. */
3480 if (l[0] == ',' && l[1] == 'p')
3481 {
3482 if (l[2] == 't')
3483 {
3484 if (!add_prefix (DS_PREFIX_OPCODE))
3485 return NULL;
3486 l += 3;
3487 }
3488 else if (l[2] == 'n')
3489 {
3490 if (!add_prefix (CS_PREFIX_OPCODE))
3491 return NULL;
3492 l += 3;
3493 }
3494 }
3495 }
3496 /* Any other comma loses. */
3497 if (*l == ',')
3498 {
3499 as_bad (_("invalid character %s in mnemonic"),
3500 output_invalid (*l));
3501 return NULL;
3502 }
252b5132 3503
29b0f896 3504 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3505 supported = 0;
3506 for (t = current_templates->start; t < current_templates->end; ++t)
3507 {
c0f3af97
L		 3508 supported |= cpu_flags_match (t);
3509 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3510 goto skip;
5c6af06e 3511 }
3629bb00 3512
c0f3af97 3513 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3514 {
3515 as_bad (flag_code == CODE_64BIT
3516 ? _("`%s' is not supported in 64-bit mode")
3517 : _("`%s' is only supported in 64-bit mode"),
3518 current_templates->start->name);
3519 return NULL;
3520 }
c0f3af97 3521 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3522 {
3629bb00 3523 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3524 current_templates->start->name,
41aacd83 3525 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3526 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3527 return NULL;
29b0f896 3528 }
3629bb00
L		 3529
3530skip:
3531 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3532 && (flag_code != CODE_16BIT))
29b0f896
AM		 3533 {
3534 as_warn (_("use .code16 to ensure correct addressing mode"));
3535 }
252b5132 3536
29c048b6 3537 /* Check for rep/repne without a string (or other allowed) instruction. */
f41bbced 3538 if (expecting_string_instruction)
29b0f896 3539 {
f41bbced
JB		 3540 static templates override;
3541
3542 for (t = current_templates->start; t < current_templates->end; ++t)
29c048b6 3543 if (t->opcode_modifier.repprefixok)
f41bbced
JB		 3544 break;
3545 if (t >= current_templates->end)
3546 {
3547 as_bad (_("expecting string instruction after `%s'"),
64e74474 3548 expecting_string_instruction);
f41bbced
JB		 3549 return NULL;
3550 }
3551 for (override.start = t; t < current_templates->end; ++t)
29c048b6 3552 if (!t->opcode_modifier.repprefixok)
f41bbced
JB		 3553 break;
3554 override.end = t;
3555 current_templates = &override;
29b0f896 3556 }
252b5132 3557
29b0f896
AM		 3558 return l;
3559}
252b5132 3560
29b0f896 3561static char *
e3bb37b5 3562parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3563{
3564 char *token_start;
3138f287 3565
29b0f896
AM		 3566 /* 1 if operand is pending after ','. */
3567 unsigned int expecting_operand = 0;
252b5132 3568
29b0f896
AM		 3569 /* Non-zero if operand parens not balanced. */
3570 unsigned int paren_not_balanced;
3571
3572 while (*l != END_OF_INSN)
3573 {
3574 /* Skip optional white space before operand. */
3575 if (is_space_char (*l))
3576 ++l;
3577 if (!is_operand_char (*l) && *l != END_OF_INSN)
3578 {
3579 as_bad (_("invalid character %s before operand %d"),
3580 output_invalid (*l),
3581 i.operands + 1);
3582 return NULL;
3583 }
3584 token_start = l; /* after white space */
3585 paren_not_balanced = 0;
3586 while (paren_not_balanced || *l != ',')
3587 {
3588 if (*l == END_OF_INSN)
3589 {
3590 if (paren_not_balanced)
3591 {
3592 if (!intel_syntax)
3593 as_bad (_("unbalanced parenthesis in operand %d."),
3594 i.operands + 1);
3595 else
3596 as_bad (_("unbalanced brackets in operand %d."),
3597 i.operands + 1);
3598 return NULL;
3599 }
3600 else
3601 break; /* we are done */
3602 }
3603 else if (!is_operand_char (*l) && !is_space_char (*l))
3604 {
3605 as_bad (_("invalid character %s in operand %d"),
3606 output_invalid (*l),
3607 i.operands + 1);
3608 return NULL;
3609 }
3610 if (!intel_syntax)
3611 {
3612 if (*l == '(')
3613 ++paren_not_balanced;
3614 if (*l == ')')
3615 --paren_not_balanced;
3616 }
3617 else
3618 {
3619 if (*l == '[')
3620 ++paren_not_balanced;
3621 if (*l == ']')
3622 --paren_not_balanced;
3623 }
3624 l++;
3625 }
3626 if (l != token_start)
3627 { /* Yes, we've read in another operand. */
3628 unsigned int operand_ok;
3629 this_operand = i.operands++;
7d5e4556 3630 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3631 if (i.operands > MAX_OPERANDS)
3632 {
3633 as_bad (_("spurious operands; (%d operands/instruction max)"),
3634 MAX_OPERANDS);
3635 return NULL;
3636 }
3637 /* Now parse operand adding info to 'i' as we go along. */
3638 END_STRING_AND_SAVE (l);
3639
3640 if (intel_syntax)
3641 operand_ok =
3642 i386_intel_operand (token_start,
3643 intel_float_operand (mnemonic));
3644 else
a7619375 3645 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3646
3647 RESTORE_END_STRING (l);
3648 if (!operand_ok)
3649 return NULL;
3650 }
3651 else
3652 {
3653 if (expecting_operand)
3654 {
3655 expecting_operand_after_comma:
3656 as_bad (_("expecting operand after ','; got nothing"));
3657 return NULL;
3658 }
3659 if (*l == ',')
3660 {
3661 as_bad (_("expecting operand before ','; got nothing"));
3662 return NULL;
3663 }
3664 }
7f3f1ea2 3665
29b0f896
AM		 3666 /* Now *l must be either ',' or END_OF_INSN. */
3667 if (*l == ',')
3668 {
3669 if (*++l == END_OF_INSN)
3670 {
3671 /* Just skip it, if it's \n complain. */
3672 goto expecting_operand_after_comma;
3673 }
3674 expecting_operand = 1;
3675 }
3676 }
3677 return l;
3678}
7f3f1ea2 3679
050dfa73 3680static void
4d456e3d 3681swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3682{
3683 union i386_op temp_op;
40fb9820 3684 i386_operand_type temp_type;
050dfa73 3685 enum bfd_reloc_code_real temp_reloc;
4eed87de 3686
050dfa73
MM		 3687 temp_type = i.types[xchg2];
3688 i.types[xchg2] = i.types[xchg1];
3689 i.types[xchg1] = temp_type;
3690 temp_op = i.op[xchg2];
3691 i.op[xchg2] = i.op[xchg1];
3692 i.op[xchg1] = temp_op;
3693 temp_reloc = i.reloc[xchg2];
3694 i.reloc[xchg2] = i.reloc[xchg1];
3695 i.reloc[xchg1] = temp_reloc;
3696}
3697
29b0f896 3698static void
e3bb37b5 3699swap_operands (void)
29b0f896 3700{
b7c61d9a 3701 switch (i.operands)
050dfa73 3702 {
c0f3af97 3703 case 5:
b7c61d9a 3704 case 4:
4d456e3d 3705 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3706 case 3:
3707 case 2:
4d456e3d 3708 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3709 break;
3710 default:
3711 abort ();
29b0f896 3712 }
29b0f896
AM		 3713
3714 if (i.mem_operands == 2)
3715 {
3716 const seg_entry *temp_seg;
3717 temp_seg = i.seg[0];
3718 i.seg[0] = i.seg[1];
3719 i.seg[1] = temp_seg;
3720 }
3721}
252b5132 3722
29b0f896
AM		 3723/* Try to ensure constant immediates are represented in the smallest
3724 opcode possible. */
3725static void
e3bb37b5 3726optimize_imm (void)
29b0f896
AM		 3727{
3728 char guess_suffix = 0;
3729 int op;
252b5132 3730
29b0f896
AM		 3731 if (i.suffix)
3732 guess_suffix = i.suffix;
3733 else if (i.reg_operands)
3734 {
3735 /* Figure out a suffix from the last register operand specified.
3736 We can't do this properly yet, ie. excluding InOutPortReg,
3737 but the following works for instructions with immediates.
3738 In any case, we can't set i.suffix yet. */
3739 for (op = i.operands; --op >= 0;)
40fb9820 3740 if (i.types[op].bitfield.reg8)
7ab9ffdd 3741 {
40fb9820
L		 3742 guess_suffix = BYTE_MNEM_SUFFIX;
3743 break;
3744 }
3745 else if (i.types[op].bitfield.reg16)
252b5132 3746 {
40fb9820
L		 3747 guess_suffix = WORD_MNEM_SUFFIX;
3748 break;
3749 }
3750 else if (i.types[op].bitfield.reg32)
3751 {
3752 guess_suffix = LONG_MNEM_SUFFIX;
3753 break;
3754 }
3755 else if (i.types[op].bitfield.reg64)
3756 {
3757 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3758 break;
252b5132 3759 }
29b0f896
AM		 3760 }
3761 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3762 guess_suffix = WORD_MNEM_SUFFIX;
3763
3764 for (op = i.operands; --op >= 0;)
40fb9820 3765 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3766 {
3767 switch (i.op[op].imms->X_op)
252b5132 3768 {
29b0f896
AM		 3769 case O_constant:
3770 /* If a suffix is given, this operand may be shortened. */
3771 switch (guess_suffix)
252b5132 3772 {
29b0f896 3773 case LONG_MNEM_SUFFIX:
40fb9820
L		 3774 i.types[op].bitfield.imm32 = 1;
3775 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3776 break;
3777 case WORD_MNEM_SUFFIX:
40fb9820
L		 3778 i.types[op].bitfield.imm16 = 1;
3779 i.types[op].bitfield.imm32 = 1;
3780 i.types[op].bitfield.imm32s = 1;
3781 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3782 break;
3783 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3784 i.types[op].bitfield.imm8 = 1;
3785 i.types[op].bitfield.imm8s = 1;
3786 i.types[op].bitfield.imm16 = 1;
3787 i.types[op].bitfield.imm32 = 1;
3788 i.types[op].bitfield.imm32s = 1;
3789 i.types[op].bitfield.imm64 = 1;
29b0f896 3790 break;
252b5132 3791 }
252b5132 3792
29b0f896
AM		 3793 /* If this operand is at most 16 bits, convert it
3794 to a signed 16 bit number before trying to see
3795 whether it will fit in an even smaller size.
3796 This allows a 16-bit operand such as $0xffe0 to
3797 be recognised as within Imm8S range. */
40fb9820 3798 if ((i.types[op].bitfield.imm16)
29b0f896 3799 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3800 {
29b0f896
AM		 3801 i.op[op].imms->X_add_number =
3802 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3803 }
40fb9820 3804 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3805 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3806 == 0))
3807 {
3808 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3809 ^ ((offsetT) 1 << 31))
3810 - ((offsetT) 1 << 31));
3811 }
40fb9820 3812 i.types[op]
c6fb90c8
L		 3813 = operand_type_or (i.types[op],
3814 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3815
29b0f896
AM		 3816 /* We must avoid matching of Imm32 templates when 64bit
3817 only immediate is available. */
3818 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3819 i.types[op].bitfield.imm32 = 0;
29b0f896 3820 break;
252b5132 3821
29b0f896
AM		 3822 case O_absent:
3823 case O_register:
3824 abort ();
3825
3826 /* Symbols and expressions. */
3827 default:
9cd96992
JB		 3828 /* Convert symbolic operand to proper sizes for matching, but don't
3829 prevent matching a set of insns that only supports sizes other
3830 than those matching the insn suffix. */
3831 {
40fb9820 3832 i386_operand_type mask, allowed;
d3ce72d0 3833 const insn_template *t;
9cd96992 3834
0dfbf9d7
L		 3835 operand_type_set (&mask, 0);
3836 operand_type_set (&allowed, 0);
40fb9820 3837
4eed87de
AM		 3838 for (t = current_templates->start;
3839 t < current_templates->end;
3840 ++t)
c6fb90c8
L		 3841 allowed = operand_type_or (allowed,
3842 t->operand_types[op]);
9cd96992
JB		 3843 switch (guess_suffix)
3844 {
3845 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3846 mask.bitfield.imm64 = 1;
3847 mask.bitfield.imm32s = 1;
9cd96992
JB		 3848 break;
3849 case LONG_MNEM_SUFFIX:
40fb9820 3850 mask.bitfield.imm32 = 1;
9cd96992
JB		 3851 break;
3852 case WORD_MNEM_SUFFIX:
40fb9820 3853 mask.bitfield.imm16 = 1;
9cd96992
JB		 3854 break;
3855 case BYTE_MNEM_SUFFIX:
40fb9820 3856 mask.bitfield.imm8 = 1;
9cd96992
JB		 3857 break;
3858 default:
9cd96992
JB		 3859 break;
3860 }
c6fb90c8 3861 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3862 if (!operand_type_all_zero (&allowed))
c6fb90c8 3863 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3864 }
29b0f896 3865 break;
252b5132 3866 }
29b0f896
AM		 3867 }
3868}
47926f60 3869
29b0f896
AM		 3870/* Try to use the smallest displacement type too. */
3871static void
e3bb37b5 3872optimize_disp (void)
29b0f896
AM		 3873{
3874 int op;
3e73aa7c 3875
29b0f896 3876 for (op = i.operands; --op >= 0;)
40fb9820 3877 if (operand_type_check (i.types[op], disp))
252b5132 3878 {
b300c311 3879 if (i.op[op].disps->X_op == O_constant)
252b5132 3880 {
91d6fa6a 3881 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3882
40fb9820 3883 if (i.types[op].bitfield.disp16
91d6fa6a 3884 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3885 {
3886 /* If this operand is at most 16 bits, convert
3887 to a signed 16 bit number and don't use 64bit
3888 displacement. */
91d6fa6a 3889 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3890 i.types[op].bitfield.disp64 = 0;
b300c311 3891 }
40fb9820 3892 if (i.types[op].bitfield.disp32
91d6fa6a 3893 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3894 {
3895 /* If this operand is at most 32 bits, convert
3896 to a signed 32 bit number and don't use 64bit
3897 displacement. */
91d6fa6a
NC		 3898 op_disp &= (((offsetT) 2 << 31) - 1);
3899 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3900 i.types[op].bitfield.disp64 = 0;
b300c311 3901 }
91d6fa6a 3902 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3903 {
40fb9820
L		 3904 i.types[op].bitfield.disp8 = 0;
3905 i.types[op].bitfield.disp16 = 0;
3906 i.types[op].bitfield.disp32 = 0;
3907 i.types[op].bitfield.disp32s = 0;
3908 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3909 i.op[op].disps = 0;
3910 i.disp_operands--;
3911 }
3912 else if (flag_code == CODE_64BIT)
3913 {
91d6fa6a 3914 if (fits_in_signed_long (op_disp))
28a9d8f5 3915 {
40fb9820
L		 3916 i.types[op].bitfield.disp64 = 0;
3917 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3918 }
0e1147d9 3919 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3920 && fits_in_unsigned_long (op_disp))
40fb9820 3921 i.types[op].bitfield.disp32 = 1;
b300c311 3922 }
40fb9820
L		 3923 if ((i.types[op].bitfield.disp32
3924 || i.types[op].bitfield.disp32s
3925 || i.types[op].bitfield.disp16)
91d6fa6a 3926 && fits_in_signed_byte (op_disp))
40fb9820 3927 i.types[op].bitfield.disp8 = 1;
252b5132 3928 }
67a4f2b7
AO		 3929 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3930 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3931 {
3932 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3933 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3934 i.types[op].bitfield.disp8 = 0;
3935 i.types[op].bitfield.disp16 = 0;
3936 i.types[op].bitfield.disp32 = 0;
3937 i.types[op].bitfield.disp32s = 0;
3938 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3939 }
3940 else
b300c311 3941 /* We only support 64bit displacement on constants. */
40fb9820 3942 i.types[op].bitfield.disp64 = 0;
252b5132 3943 }
29b0f896
AM		 3944}
3945
6c30d220
L		 3946/* Check if operands are valid for the instruction. */
3947
3948static int
3949check_VecOperands (const insn_template *t)
3950{
3951 /* Without VSIB byte, we can't have a vector register for index. */
3952 if (!t->opcode_modifier.vecsib
3953 && i.index_reg
3954 && (i.index_reg->reg_type.bitfield.regxmm
3955 || i.index_reg->reg_type.bitfield.regymm))
3956 {
3957 i.error = unsupported_vector_index_register;
3958 return 1;
3959 }
3960
3961 /* For VSIB byte, we need a vector register for index and no PC
3962 relative addressing is allowed. */
3963 if (t->opcode_modifier.vecsib
3964 && (!i.index_reg
3965 || !((t->opcode_modifier.vecsib == VecSIB128
3966 && i.index_reg->reg_type.bitfield.regxmm)
3967 || (t->opcode_modifier.vecsib == VecSIB256
3968 && i.index_reg->reg_type.bitfield.regymm))
3969 || (i.base_reg && i.base_reg->reg_num == RegRip)))
3970 {
3971 i.error = invalid_vsib_address;
3972 return 1;
3973 }
3974
3975 return 0;
3976}
3977
43f3e2ee 3978/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 3979 operand types. */
3980
3981static int
3982VEX_check_operands (const insn_template *t)
3983{
3984 if (!t->opcode_modifier.vex)
3985 return 0;
3986
3987 /* Only check VEX_Imm4, which must be the first operand. */
3988 if (t->operand_types[0].bitfield.vec_imm4)
3989 {
3990 if (i.op[0].imms->X_op != O_constant
3991 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 3992 {
a65babc9 3993 i.error = bad_imm4;
891edac4
L		 3994 return 1;
3995 }
a683cc34
SP		 3996
3997 /* Turn off Imm8 so that update_imm won't complain. */
3998 i.types[0] = vec_imm4;
3999 }
4000
4001 return 0;
4002}
4003
d3ce72d0 4004static const insn_template *
e3bb37b5 4005match_template (void)
29b0f896
AM		 4006{
4007 /* Points to template once we've found it. */
d3ce72d0 4008 const insn_template *t;
40fb9820 4009 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4010 i386_operand_type overlap4;
29b0f896 4011 unsigned int found_reverse_match;
40fb9820
L		 4012 i386_opcode_modifier suffix_check;
4013 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4014 int addr_prefix_disp;
a5c311ca 4015 unsigned int j;
3629bb00 4016 unsigned int found_cpu_match;
45664ddb 4017 unsigned int check_register;
5614d22c 4018 enum i386_error specific_error = 0;
29b0f896 4019
c0f3af97
L		 4020#if MAX_OPERANDS != 5
4021# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4022#endif
4023
29b0f896 4024 found_reverse_match = 0;
539e75ad 4025 addr_prefix_disp = -1;
40fb9820
L		 4026
4027 memset (&suffix_check, 0, sizeof (suffix_check));
4028 if (i.suffix == BYTE_MNEM_SUFFIX)
4029 suffix_check.no_bsuf = 1;
4030 else if (i.suffix == WORD_MNEM_SUFFIX)
4031 suffix_check.no_wsuf = 1;
4032 else if (i.suffix == SHORT_MNEM_SUFFIX)
4033 suffix_check.no_ssuf = 1;
4034 else if (i.suffix == LONG_MNEM_SUFFIX)
4035 suffix_check.no_lsuf = 1;
4036 else if (i.suffix == QWORD_MNEM_SUFFIX)
4037 suffix_check.no_qsuf = 1;
4038 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4039 suffix_check.no_ldsuf = 1;
29b0f896 4040
01559ecc
L		 4041 /* Must have right number of operands. */
4042 i.error = number_of_operands_mismatch;
4043
45aa61fe 4044 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4045 {
539e75ad
L		 4046 addr_prefix_disp = -1;
4047
29b0f896
AM		 4048 if (i.operands != t->operands)
4049 continue;
4050
50aecf8c 4051 /* Check processor support. */
a65babc9 4052 i.error = unsupported;
c0f3af97
L		 4053 found_cpu_match = (cpu_flags_match (t)
4054 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4055 if (!found_cpu_match)
4056 continue;
4057
e1d4d893 4058 /* Check old gcc support. */
a65babc9 4059 i.error = old_gcc_only;
e1d4d893
L		 4060 if (!old_gcc && t->opcode_modifier.oldgcc)
4061 continue;
4062
4063 /* Check AT&T mnemonic. */
a65babc9 4064 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4065 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4066 continue;
4067
891edac4 4068 /* Check AT&T/Intel syntax. */
a65babc9 4069 i.error = unsupported_syntax;
5c07affc
L		 4070 if ((intel_syntax && t->opcode_modifier.attsyntax)
4071 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4072 continue;
4073
20592a94 4074 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4075 i.error = invalid_instruction_suffix;
567e4e96
L		 4076 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4077 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4078 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4079 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4080 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4081 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4082 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4083 continue;
4084
5c07affc 4085 if (!operand_size_match (t))
7d5e4556 4086 continue;
539e75ad 4087
5c07affc
L		 4088 for (j = 0; j < MAX_OPERANDS; j++)
4089 operand_types[j] = t->operand_types[j];
4090
45aa61fe
AM		 4091 /* In general, don't allow 64-bit operands in 32-bit mode. */
4092 if (i.suffix == QWORD_MNEM_SUFFIX
4093 && flag_code != CODE_64BIT
4094 && (intel_syntax
40fb9820 4095 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4096 && !intel_float_operand (t->name))
4097 : intel_float_operand (t->name) != 2)
40fb9820 4098 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 4099 && !operand_types[0].bitfield.regxmm
4100 && !operand_types[0].bitfield.regymm)
40fb9820 4101 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 4102 && !!operand_types[t->operands > 1].bitfield.regxmm
4103 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 4104 && (t->base_opcode != 0x0fc7
4105 || t->extension_opcode != 1 /* cmpxchg8b */))
4106 continue;
4107
192dc9c6
JB		 4108 /* In general, don't allow 32-bit operands on pre-386. */
4109 else if (i.suffix == LONG_MNEM_SUFFIX
4110 && !cpu_arch_flags.bitfield.cpui386
4111 && (intel_syntax
4112 ? (!t->opcode_modifier.ignoresize
4113 && !intel_float_operand (t->name))
4114 : intel_float_operand (t->name) != 2)
4115 && ((!operand_types[0].bitfield.regmmx
4116 && !operand_types[0].bitfield.regxmm)
4117 || (!operand_types[t->operands > 1].bitfield.regmmx
4118 && !!operand_types[t->operands > 1].bitfield.regxmm)))
4119 continue;
4120
29b0f896 4121 /* Do not verify operands when there are none. */
50aecf8c 4122 else
29b0f896 4123 {
c6fb90c8 4124 if (!t->operands)
2dbab7d5
L		 4125 /* We've found a match; break out of loop. */
4126 break;
29b0f896 4127 }
252b5132 4128
539e75ad
L		 4129 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4130 into Disp32/Disp16/Disp32 operand. */
4131 if (i.prefix[ADDR_PREFIX] != 0)
4132 {
40fb9820 4133 /* There should be only one Disp operand. */
539e75ad
L		 4134 switch (flag_code)
4135 {
4136 case CODE_16BIT:
40fb9820
L		 4137 for (j = 0; j < MAX_OPERANDS; j++)
4138 {
4139 if (operand_types[j].bitfield.disp16)
4140 {
4141 addr_prefix_disp = j;
4142 operand_types[j].bitfield.disp32 = 1;
4143 operand_types[j].bitfield.disp16 = 0;
4144 break;
4145 }
4146 }
539e75ad
L		 4147 break;
4148 case CODE_32BIT:
40fb9820
L		 4149 for (j = 0; j < MAX_OPERANDS; j++)
4150 {
4151 if (operand_types[j].bitfield.disp32)
4152 {
4153 addr_prefix_disp = j;
4154 operand_types[j].bitfield.disp32 = 0;
4155 operand_types[j].bitfield.disp16 = 1;
4156 break;
4157 }
4158 }
539e75ad
L		 4159 break;
4160 case CODE_64BIT:
40fb9820
L		 4161 for (j = 0; j < MAX_OPERANDS; j++)
4162 {
4163 if (operand_types[j].bitfield.disp64)
4164 {
4165 addr_prefix_disp = j;
4166 operand_types[j].bitfield.disp64 = 0;
4167 operand_types[j].bitfield.disp32 = 1;
4168 break;
4169 }
4170 }
539e75ad
L		 4171 break;
4172 }
539e75ad
L		 4173 }
4174
56ffb741
L		 4175 /* We check register size if needed. */
4176 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4177 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4178 switch (t->operands)
4179 {
4180 case 1:
40fb9820 4181 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4182 continue;
4183 break;
4184 case 2:
8b38ad71
L		 4185 /* xchg %eax, %eax is a special case. It is an aliase for nop
4186 only in 32bit mode and we can use opcode 0x90. In 64bit
4187 mode, we can't use 0x90 for xchg %eax, %eax since it should
4188 zero-extend %eax to %rax. */
4189 if (flag_code == CODE_64BIT
4190 && t->base_opcode == 0x90
0dfbf9d7
L		 4191 && operand_type_equal (&i.types [0], &acc32)
4192 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4193 continue;
b6169b20
L		 4194 if (i.swap_operand)
4195 {
4196 /* If we swap operand in encoding, we either match
4197 the next one or reverse direction of operands. */
4198 if (t->opcode_modifier.s)
4199 continue;
4200 else if (t->opcode_modifier.d)
4201 goto check_reverse;
4202 }
4203
29b0f896 4204 case 3:
fa99fab2
L		 4205 /* If we swap operand in encoding, we match the next one. */
4206 if (i.swap_operand && t->opcode_modifier.s)
4207 continue;
f48ff2ae 4208 case 4:
c0f3af97 4209 case 5:
c6fb90c8 4210 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4211 if (!operand_type_match (overlap0, i.types[0])
4212 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4213 || (check_register
4214 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4215 operand_types[0],
4216 overlap1, i.types[1],
4217 operand_types[1])))
29b0f896
AM		 4218 {
4219 /* Check if other direction is valid ... */
40fb9820 4220 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4221 continue;
4222
b6169b20 4223check_reverse:
29b0f896 4224 /* Try reversing direction of operands. */
c6fb90c8
L		 4225 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4226 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4227 if (!operand_type_match (overlap0, i.types[0])
4228 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4229 || (check_register
4230 && !operand_type_register_match (overlap0,
4231 i.types[0],
4232 operand_types[1],
4233 overlap1,
4234 i.types[1],
4235 operand_types[0])))
29b0f896
AM		 4236 {
4237 /* Does not match either direction. */
4238 continue;
4239 }
4240 /* found_reverse_match holds which of D or FloatDR
4241 we've found. */
40fb9820 4242 if (t->opcode_modifier.d)
8a2ed489 4243 found_reverse_match = Opcode_D;
40fb9820 4244 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4245 found_reverse_match = Opcode_FloatD;
4246 else
4247 found_reverse_match = 0;
40fb9820 4248 if (t->opcode_modifier.floatr)
8a2ed489 4249 found_reverse_match |= Opcode_FloatR;
29b0f896 4250 }
f48ff2ae 4251 else
29b0f896 4252 {
f48ff2ae 4253 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4254 switch (t->operands)
4255 {
c0f3af97
L		 4256 case 5:
4257 overlap4 = operand_type_and (i.types[4],
4258 operand_types[4]);
d1cbb4db 4259 case 4:
c6fb90c8
L		 4260 overlap3 = operand_type_and (i.types[3],
4261 operand_types[3]);
d1cbb4db 4262 case 3:
c6fb90c8
L		 4263 overlap2 = operand_type_and (i.types[2],
4264 operand_types[2]);
d1cbb4db
L		 4265 break;
4266 }
29b0f896 4267
f48ff2ae
L		 4268 switch (t->operands)
4269 {
c0f3af97
L		 4270 case 5:
4271 if (!operand_type_match (overlap4, i.types[4])
4272 || !operand_type_register_match (overlap3,
4273 i.types[3],
4274 operand_types[3],
4275 overlap4,
4276 i.types[4],
4277 operand_types[4]))
4278 continue;
f48ff2ae 4279 case 4:
40fb9820 4280 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4281 || (check_register
4282 && !operand_type_register_match (overlap2,
4283 i.types[2],
4284 operand_types[2],
4285 overlap3,
4286 i.types[3],
4287 operand_types[3])))
f48ff2ae
L		 4288 continue;
4289 case 3:
4290 /* Here we make use of the fact that there are no
4291 reverse match 3 operand instructions, and all 3
4292 operand instructions only need to be checked for
4293 register consistency between operands 2 and 3. */
40fb9820 4294 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4295 || (check_register
4296 && !operand_type_register_match (overlap1,
4297 i.types[1],
4298 operand_types[1],
4299 overlap2,
4300 i.types[2],
4301 operand_types[2])))
f48ff2ae
L		 4302 continue;
4303 break;
4304 }
29b0f896 4305 }
f48ff2ae 4306 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4307 slip through to break. */
4308 }
3629bb00 4309 if (!found_cpu_match)
29b0f896
AM		 4310 {
4311 found_reverse_match = 0;
4312 continue;
4313 }
c0f3af97 4314
5614d22c
JB		 4315 /* Check if vector and VEX operands are valid. */
4316 if (check_VecOperands (t) || VEX_check_operands (t))
4317 {
4318 specific_error = i.error;
4319 continue;
4320 }
a683cc34 4321
29b0f896
AM		 4322 /* We've found a match; break out of loop. */
4323 break;
4324 }
4325
4326 if (t == current_templates->end)
4327 {
4328 /* We found no match. */
a65babc9 4329 const char *err_msg;
5614d22c 4330 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4331 {
4332 default:
4333 abort ();
86e026a4 4334 case operand_size_mismatch:
a65babc9
L		 4335 err_msg = _("operand size mismatch");
4336 break;
4337 case operand_type_mismatch:
4338 err_msg = _("operand type mismatch");
4339 break;
4340 case register_type_mismatch:
4341 err_msg = _("register type mismatch");
4342 break;
4343 case number_of_operands_mismatch:
4344 err_msg = _("number of operands mismatch");
4345 break;
4346 case invalid_instruction_suffix:
4347 err_msg = _("invalid instruction suffix");
4348 break;
4349 case bad_imm4:
4a2608e3 4350 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4351 break;
4352 case old_gcc_only:
4353 err_msg = _("only supported with old gcc");
4354 break;
4355 case unsupported_with_intel_mnemonic:
4356 err_msg = _("unsupported with Intel mnemonic");
4357 break;
4358 case unsupported_syntax:
4359 err_msg = _("unsupported syntax");
4360 break;
4361 case unsupported:
35262a23 4362 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4363 current_templates->start->name);
4364 return NULL;
6c30d220
L		 4365 case invalid_vsib_address:
4366 err_msg = _("invalid VSIB address");
4367 break;
4368 case unsupported_vector_index_register:
4369 err_msg = _("unsupported vector index register");
4370 break;
a65babc9
L		 4371 }
4372 as_bad (_("%s for `%s'"), err_msg,
891edac4 4373 current_templates->start->name);
fa99fab2 4374 return NULL;
29b0f896 4375 }
252b5132 4376
29b0f896
AM		 4377 if (!quiet_warnings)
4378 {
4379 if (!intel_syntax
40fb9820
L		 4380 && (i.types[0].bitfield.jumpabsolute
4381 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4382 {
4383 as_warn (_("indirect %s without `*'"), t->name);
4384 }
4385
40fb9820
L		 4386 if (t->opcode_modifier.isprefix
4387 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4388 {
4389 /* Warn them that a data or address size prefix doesn't
4390 affect assembly of the next line of code. */
4391 as_warn (_("stand-alone `%s' prefix"), t->name);
4392 }
4393 }
4394
4395 /* Copy the template we found. */
4396 i.tm = *t;
539e75ad
L		 4397
4398 if (addr_prefix_disp != -1)
4399 i.tm.operand_types[addr_prefix_disp]
4400 = operand_types[addr_prefix_disp];
4401
29b0f896
AM		 4402 if (found_reverse_match)
4403 {
4404 /* If we found a reverse match we must alter the opcode
4405 direction bit. found_reverse_match holds bits to change
4406 (different for int & float insns). */
4407
4408 i.tm.base_opcode ^= found_reverse_match;
4409
539e75ad
L		 4410 i.tm.operand_types[0] = operand_types[1];
4411 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4412 }
4413
fa99fab2 4414 return t;
29b0f896
AM		 4415}
4416
4417static int
e3bb37b5 4418check_string (void)
29b0f896 4419{
40fb9820
L		 4420 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4421 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4422 {
4423 if (i.seg[0] != NULL && i.seg[0] != &es)
4424 {
a87af027 4425 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4426 i.tm.name,
a87af027
JB		 4427 mem_op + 1,
4428 register_prefix);
29b0f896
AM		 4429 return 0;
4430 }
4431 /* There's only ever one segment override allowed per instruction.
4432 This instruction possibly has a legal segment override on the
4433 second operand, so copy the segment to where non-string
4434 instructions store it, allowing common code. */
4435 i.seg[0] = i.seg[1];
4436 }
40fb9820 4437 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4438 {
4439 if (i.seg[1] != NULL && i.seg[1] != &es)
4440 {
a87af027 4441 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4442 i.tm.name,
a87af027
JB		 4443 mem_op + 2,
4444 register_prefix);
29b0f896
AM		 4445 return 0;
4446 }
4447 }
4448 return 1;
4449}
4450
4451static int
543613e9 4452process_suffix (void)
29b0f896
AM		 4453{
4454 /* If matched instruction specifies an explicit instruction mnemonic
4455 suffix, use it. */
40fb9820
L		 4456 if (i.tm.opcode_modifier.size16)
4457 i.suffix = WORD_MNEM_SUFFIX;
4458 else if (i.tm.opcode_modifier.size32)
4459 i.suffix = LONG_MNEM_SUFFIX;
4460 else if (i.tm.opcode_modifier.size64)
4461 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4462 else if (i.reg_operands)
4463 {
4464 /* If there's no instruction mnemonic suffix we try to invent one
4465 based on register operands. */
4466 if (!i.suffix)
4467 {
4468 /* We take i.suffix from the last register operand specified,
4469 Destination register type is more significant than source
381d071f
L		 4470 register type. crc32 in SSE4.2 prefers source register
4471 type. */
4472 if (i.tm.base_opcode == 0xf20f38f1)
4473 {
40fb9820
L		 4474 if (i.types[0].bitfield.reg16)
4475 i.suffix = WORD_MNEM_SUFFIX;
4476 else if (i.types[0].bitfield.reg32)
4477 i.suffix = LONG_MNEM_SUFFIX;
4478 else if (i.types[0].bitfield.reg64)
4479 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4480 }
9344ff29 4481 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4482 {
40fb9820 4483 if (i.types[0].bitfield.reg8)
20592a94
L		 4484 i.suffix = BYTE_MNEM_SUFFIX;
4485 }
381d071f
L		 4486
4487 if (!i.suffix)
4488 {
4489 int op;
4490
20592a94
L		 4491 if (i.tm.base_opcode == 0xf20f38f1
4492 || i.tm.base_opcode == 0xf20f38f0)
4493 {
4494 /* We have to know the operand size for crc32. */
4495 as_bad (_("ambiguous memory operand size for `%s`"),
4496 i.tm.name);
4497 return 0;
4498 }
4499
381d071f 4500 for (op = i.operands; --op >= 0;)
40fb9820 4501 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4502 {
40fb9820
L		 4503 if (i.types[op].bitfield.reg8)
4504 {
4505 i.suffix = BYTE_MNEM_SUFFIX;
4506 break;
4507 }
4508 else if (i.types[op].bitfield.reg16)
4509 {
4510 i.suffix = WORD_MNEM_SUFFIX;
4511 break;
4512 }
4513 else if (i.types[op].bitfield.reg32)
4514 {
4515 i.suffix = LONG_MNEM_SUFFIX;
4516 break;
4517 }
4518 else if (i.types[op].bitfield.reg64)
4519 {
4520 i.suffix = QWORD_MNEM_SUFFIX;
4521 break;
4522 }
381d071f
L		 4523 }
4524 }
29b0f896
AM		 4525 }
4526 else if (i.suffix == BYTE_MNEM_SUFFIX)
4527 {
2eb952a4
L		 4528 if (intel_syntax
4529 && i.tm.opcode_modifier.ignoresize
4530 && i.tm.opcode_modifier.no_bsuf)
4531 i.suffix = 0;
4532 else if (!check_byte_reg ())
29b0f896
AM		 4533 return 0;
4534 }
4535 else if (i.suffix == LONG_MNEM_SUFFIX)
4536 {
2eb952a4
L		 4537 if (intel_syntax
4538 && i.tm.opcode_modifier.ignoresize
4539 && i.tm.opcode_modifier.no_lsuf)
4540 i.suffix = 0;
4541 else if (!check_long_reg ())
29b0f896
AM		 4542 return 0;
4543 }
4544 else if (i.suffix == QWORD_MNEM_SUFFIX)
4545 {
955e1e6a
L		 4546 if (intel_syntax
4547 && i.tm.opcode_modifier.ignoresize
4548 && i.tm.opcode_modifier.no_qsuf)
4549 i.suffix = 0;
4550 else if (!check_qword_reg ())
29b0f896
AM		 4551 return 0;
4552 }
4553 else if (i.suffix == WORD_MNEM_SUFFIX)
4554 {
2eb952a4
L		 4555 if (intel_syntax
4556 && i.tm.opcode_modifier.ignoresize
4557 && i.tm.opcode_modifier.no_wsuf)
4558 i.suffix = 0;
4559 else if (!check_word_reg ())
29b0f896
AM		 4560 return 0;
4561 }
c0f3af97
L		 4562 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4563 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4564 {
c0f3af97 4565 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4566 should check if it is a valid suffix. */
4567 }
40fb9820 4568 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4569 /* Do nothing if the instruction is going to ignore the prefix. */
4570 ;
4571 else
4572 abort ();
4573 }
40fb9820 4574 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4575 && !i.suffix
4576 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4577 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4578 {
4579 i.suffix = stackop_size;
4580 }
9306ca4a
JB		 4581 else if (intel_syntax
4582 && !i.suffix
40fb9820
L		 4583 && (i.tm.operand_types[0].bitfield.jumpabsolute
4584 || i.tm.opcode_modifier.jumpbyte
4585 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4586 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4587 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4588 {
4589 switch (flag_code)
4590 {
4591 case CODE_64BIT:
40fb9820 4592 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4593 {
4594 i.suffix = QWORD_MNEM_SUFFIX;
4595 break;
4596 }
4597 case CODE_32BIT:
40fb9820 4598 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4599 i.suffix = LONG_MNEM_SUFFIX;
4600 break;
4601 case CODE_16BIT:
40fb9820 4602 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4603 i.suffix = WORD_MNEM_SUFFIX;
4604 break;
4605 }
4606 }
252b5132 4607
9306ca4a 4608 if (!i.suffix)
29b0f896 4609 {
9306ca4a
JB		 4610 if (!intel_syntax)
4611 {
40fb9820 4612 if (i.tm.opcode_modifier.w)
9306ca4a 4613 {
4eed87de
AM		 4614 as_bad (_("no instruction mnemonic suffix given and "
4615 "no register operands; can't size instruction"));
9306ca4a
JB		 4616 return 0;
4617 }
4618 }
4619 else
4620 {
40fb9820 4621 unsigned int suffixes;
7ab9ffdd 4622
40fb9820
L		 4623 suffixes = !i.tm.opcode_modifier.no_bsuf;
4624 if (!i.tm.opcode_modifier.no_wsuf)
4625 suffixes |= 1 << 1;
4626 if (!i.tm.opcode_modifier.no_lsuf)
4627 suffixes |= 1 << 2;
fc4adea1 4628 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4629 suffixes |= 1 << 3;
4630 if (!i.tm.opcode_modifier.no_ssuf)
4631 suffixes |= 1 << 4;
4632 if (!i.tm.opcode_modifier.no_qsuf)
4633 suffixes |= 1 << 5;
4634
4635 /* There are more than suffix matches. */
4636 if (i.tm.opcode_modifier.w
9306ca4a 4637 || ((suffixes & (suffixes - 1))
40fb9820
L		 4638 && !i.tm.opcode_modifier.defaultsize
4639 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4640 {
4641 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4642 return 0;
4643 }
4644 }
29b0f896 4645 }
252b5132 4646
9306ca4a
JB		 4647 /* Change the opcode based on the operand size given by i.suffix;
4648 We don't need to change things for byte insns. */
4649
582d5edd
L		 4650 if (i.suffix
4651 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4652 && i.suffix != XMMWORD_MNEM_SUFFIX
4653 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4654 {
4655 /* It's not a byte, select word/dword operation. */
40fb9820 4656 if (i.tm.opcode_modifier.w)
29b0f896 4657 {
40fb9820 4658 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4659 i.tm.base_opcode |= 8;
4660 else
4661 i.tm.base_opcode |= 1;
4662 }
0f3f3d8b 4663
29b0f896
AM		 4664 /* Now select between word & dword operations via the operand
4665 size prefix, except for instructions that will ignore this
4666 prefix anyway. */
ca61edf2 4667 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4668 {
ca61edf2
L		 4669 /* The address size override prefix changes the size of the
4670 first operand. */
40fb9820
L		 4671 if ((flag_code == CODE_32BIT
4672 && i.op->regs[0].reg_type.bitfield.reg16)
4673 || (flag_code != CODE_32BIT
4674 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4675 if (!add_prefix (ADDR_PREFIX_OPCODE))
4676 return 0;
4677 }
4678 else if (i.suffix != QWORD_MNEM_SUFFIX
4679 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4680 && !i.tm.opcode_modifier.ignoresize
4681 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4682 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4683 || (flag_code == CODE_64BIT
40fb9820 4684 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4685 {
4686 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4687
40fb9820 4688 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4689 prefix = ADDR_PREFIX_OPCODE;
252b5132 4690
29b0f896
AM		 4691 if (!add_prefix (prefix))
4692 return 0;
24eab124 4693 }
252b5132 4694
29b0f896
AM		 4695 /* Set mode64 for an operand. */
4696 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4697 && flag_code == CODE_64BIT
40fb9820 4698 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4699 {
4700 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4701 need rex64. cmpxchg8b is also a special case. */
4702 if (! (i.operands == 2
4703 && i.tm.base_opcode == 0x90
4704 && i.tm.extension_opcode == None
0dfbf9d7
L		 4705 && operand_type_equal (&i.types [0], &acc64)
4706 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4707 && ! (i.operands == 1
4708 && i.tm.base_opcode == 0xfc7
4709 && i.tm.extension_opcode == 1
40fb9820
L		 4710 && !operand_type_check (i.types [0], reg)
4711 && operand_type_check (i.types [0], anymem)))
f6bee062 4712 i.rex |= REX_W;
46e883c5 4713 }
3e73aa7c 4714
29b0f896
AM		 4715 /* Size floating point instruction. */
4716 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4717 if (i.tm.opcode_modifier.floatmf)
543613e9 4718 i.tm.base_opcode ^= 4;
29b0f896 4719 }
7ecd2f8b 4720
29b0f896
AM		 4721 return 1;
4722}
3e73aa7c 4723
29b0f896 4724static int
543613e9 4725check_byte_reg (void)
29b0f896
AM		 4726{
4727 int op;
543613e9 4728
29b0f896
AM		 4729 for (op = i.operands; --op >= 0;)
4730 {
4731 /* If this is an eight bit register, it's OK. If it's the 16 or
4732 32 bit version of an eight bit register, we will just use the
4733 low portion, and that's OK too. */
40fb9820 4734 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4735 continue;
4736
5a819eb9
JB		 4737 /* I/O port address operands are OK too. */
4738 if (i.tm.operand_types[op].bitfield.inoutportreg)
4739 continue;
4740
9344ff29
L		 4741 /* crc32 doesn't generate this warning. */
4742 if (i.tm.base_opcode == 0xf20f38f0)
4743 continue;
4744
40fb9820
L		 4745 if ((i.types[op].bitfield.reg16
4746 || i.types[op].bitfield.reg32
4747 || i.types[op].bitfield.reg64)
5a819eb9
JB		 4748 && i.op[op].regs->reg_num < 4
4749 /* Prohibit these changes in 64bit mode, since the lowering
4750 would be more complicated. */
4751 && flag_code != CODE_64BIT)
29b0f896 4752 {
29b0f896 4753#if REGISTER_WARNINGS
5a819eb9 4754 if (!quiet_warnings)
a540244d
L		 4755 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4756 register_prefix,
40fb9820 4757 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4758 ? REGNAM_AL - REGNAM_AX
4759 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4760 register_prefix,
29b0f896
AM		 4761 i.op[op].regs->reg_name,
4762 i.suffix);
4763#endif
4764 continue;
4765 }
4766 /* Any other register is bad. */
40fb9820
L		 4767 if (i.types[op].bitfield.reg16
4768 || i.types[op].bitfield.reg32
4769 || i.types[op].bitfield.reg64
4770 || i.types[op].bitfield.regmmx
4771 || i.types[op].bitfield.regxmm
c0f3af97 4772 || i.types[op].bitfield.regymm
40fb9820
L		 4773 || i.types[op].bitfield.sreg2
4774 || i.types[op].bitfield.sreg3
4775 || i.types[op].bitfield.control
4776 || i.types[op].bitfield.debug
4777 || i.types[op].bitfield.test
4778 || i.types[op].bitfield.floatreg
4779 || i.types[op].bitfield.floatacc)
29b0f896 4780 {
a540244d
L		 4781 as_bad (_("`%s%s' not allowed with `%s%c'"),
4782 register_prefix,
29b0f896
AM		 4783 i.op[op].regs->reg_name,
4784 i.tm.name,
4785 i.suffix);
4786 return 0;
4787 }
4788 }
4789 return 1;
4790}
4791
4792static int
e3bb37b5 4793check_long_reg (void)
29b0f896
AM		 4794{
4795 int op;
4796
4797 for (op = i.operands; --op >= 0;)
4798 /* Reject eight bit registers, except where the template requires
4799 them. (eg. movzb) */
40fb9820
L		 4800 if (i.types[op].bitfield.reg8
4801 && (i.tm.operand_types[op].bitfield.reg16
4802 || i.tm.operand_types[op].bitfield.reg32
4803 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4804 {
a540244d
L		 4805 as_bad (_("`%s%s' not allowed with `%s%c'"),
4806 register_prefix,
29b0f896
AM		 4807 i.op[op].regs->reg_name,
4808 i.tm.name,
4809 i.suffix);
4810 return 0;
4811 }
4812 /* Warn if the e prefix on a general reg is missing. */
4813 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4814 && i.types[op].bitfield.reg16
4815 && (i.tm.operand_types[op].bitfield.reg32
4816 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4817 {
4818 /* Prohibit these changes in the 64bit mode, since the
4819 lowering is more complicated. */
4820 if (flag_code == CODE_64BIT)
252b5132 4821 {
2b5d6a91 4822 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 4823 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4824 i.suffix);
4825 return 0;
252b5132 4826 }
29b0f896
AM		 4827#if REGISTER_WARNINGS
4828 else
a540244d
L		 4829 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4830 register_prefix,
29b0f896 4831 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4832 register_prefix,
29b0f896
AM		 4833 i.op[op].regs->reg_name,
4834 i.suffix);
4835#endif
252b5132 4836 }
29b0f896 4837 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4838 else if (i.types[op].bitfield.reg64
4839 && (i.tm.operand_types[op].bitfield.reg32
4840 || i.tm.operand_types[op].bitfield.acc))
252b5132 4841 {
34828aad 4842 if (intel_syntax
ca61edf2 4843 && i.tm.opcode_modifier.toqword
40fb9820 4844 && !i.types[0].bitfield.regxmm)
34828aad 4845 {
ca61edf2 4846 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4847 i.suffix = QWORD_MNEM_SUFFIX;
4848 }
4849 else
4850 {
2b5d6a91 4851 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 4852 register_prefix, i.op[op].regs->reg_name,
4853 i.suffix);
4854 return 0;
4855 }
29b0f896
AM		 4856 }
4857 return 1;
4858}
252b5132 4859
29b0f896 4860static int
e3bb37b5 4861check_qword_reg (void)
29b0f896
AM		 4862{
4863 int op;
252b5132 4864
29b0f896
AM		 4865 for (op = i.operands; --op >= 0; )
4866 /* Reject eight bit registers, except where the template requires
4867 them. (eg. movzb) */
40fb9820
L		 4868 if (i.types[op].bitfield.reg8
4869 && (i.tm.operand_types[op].bitfield.reg16
4870 || i.tm.operand_types[op].bitfield.reg32
4871 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4872 {
a540244d
L		 4873 as_bad (_("`%s%s' not allowed with `%s%c'"),
4874 register_prefix,
29b0f896
AM		 4875 i.op[op].regs->reg_name,
4876 i.tm.name,
4877 i.suffix);
4878 return 0;
4879 }
4880 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4881 else if ((i.types[op].bitfield.reg16
4882 || i.types[op].bitfield.reg32)
4883 && (i.tm.operand_types[op].bitfield.reg32
4884 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4885 {
4886 /* Prohibit these changes in the 64bit mode, since the
4887 lowering is more complicated. */
34828aad 4888 if (intel_syntax
ca61edf2 4889 && i.tm.opcode_modifier.todword
40fb9820 4890 && !i.types[0].bitfield.regxmm)
34828aad 4891 {
ca61edf2 4892 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4893 i.suffix = LONG_MNEM_SUFFIX;
4894 }
4895 else
4896 {
2b5d6a91 4897 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 4898 register_prefix, i.op[op].regs->reg_name,
4899 i.suffix);
4900 return 0;
4901 }
252b5132 4902 }
29b0f896
AM		 4903 return 1;
4904}
252b5132 4905
29b0f896 4906static int
e3bb37b5 4907check_word_reg (void)
29b0f896
AM		 4908{
4909 int op;
4910 for (op = i.operands; --op >= 0;)
4911 /* Reject eight bit registers, except where the template requires
4912 them. (eg. movzb) */
40fb9820
L		 4913 if (i.types[op].bitfield.reg8
4914 && (i.tm.operand_types[op].bitfield.reg16
4915 || i.tm.operand_types[op].bitfield.reg32
4916 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4917 {
a540244d
L		 4918 as_bad (_("`%s%s' not allowed with `%s%c'"),
4919 register_prefix,
29b0f896
AM		 4920 i.op[op].regs->reg_name,
4921 i.tm.name,
4922 i.suffix);
4923 return 0;
4924 }
4925 /* Warn if the e prefix on a general reg is present. */
4926 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4927 && i.types[op].bitfield.reg32
4928 && (i.tm.operand_types[op].bitfield.reg16
4929 || i.tm.operand_types[op].bitfield.acc))
252b5132 4930 {
29b0f896
AM		 4931 /* Prohibit these changes in the 64bit mode, since the
4932 lowering is more complicated. */
4933 if (flag_code == CODE_64BIT)
252b5132 4934 {
2b5d6a91 4935 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 4936 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4937 i.suffix);
4938 return 0;
252b5132 4939 }
29b0f896
AM		 4940 else
4941#if REGISTER_WARNINGS
a540244d
L		 4942 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4943 register_prefix,
29b0f896 4944 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4945 register_prefix,
29b0f896
AM		 4946 i.op[op].regs->reg_name,
4947 i.suffix);
4948#endif
4949 }
4950 return 1;
4951}
252b5132 4952
29b0f896 4953static int
40fb9820 4954update_imm (unsigned int j)
29b0f896 4955{
bc0844ae 4956 i386_operand_type overlap = i.types[j];
40fb9820
L		 4957 if ((overlap.bitfield.imm8
4958 || overlap.bitfield.imm8s
4959 || overlap.bitfield.imm16
4960 || overlap.bitfield.imm32
4961 || overlap.bitfield.imm32s
4962 || overlap.bitfield.imm64)
0dfbf9d7
L		 4963 && !operand_type_equal (&overlap, &imm8)
4964 && !operand_type_equal (&overlap, &imm8s)
4965 && !operand_type_equal (&overlap, &imm16)
4966 && !operand_type_equal (&overlap, &imm32)
4967 && !operand_type_equal (&overlap, &imm32s)
4968 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4969 {
4970 if (i.suffix)
4971 {
40fb9820
L		 4972 i386_operand_type temp;
4973
0dfbf9d7 4974 operand_type_set (&temp, 0);
7ab9ffdd 4975 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4976 {
4977 temp.bitfield.imm8 = overlap.bitfield.imm8;
4978 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4979 }
4980 else if (i.suffix == WORD_MNEM_SUFFIX)
4981 temp.bitfield.imm16 = overlap.bitfield.imm16;
4982 else if (i.suffix == QWORD_MNEM_SUFFIX)
4983 {
4984 temp.bitfield.imm64 = overlap.bitfield.imm64;
4985 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4986 }
4987 else
4988 temp.bitfield.imm32 = overlap.bitfield.imm32;
4989 overlap = temp;
29b0f896 4990 }
0dfbf9d7
L		 4991 else if (operand_type_equal (&overlap, &imm16_32_32s)
4992 || operand_type_equal (&overlap, &imm16_32)
4993 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4994 {
40fb9820 4995 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4996 overlap = imm16;
40fb9820 4997 else
65da13b5 4998 overlap = imm32s;
29b0f896 4999 }
0dfbf9d7
L		 5000 if (!operand_type_equal (&overlap, &imm8)
5001 && !operand_type_equal (&overlap, &imm8s)
5002 && !operand_type_equal (&overlap, &imm16)
5003 && !operand_type_equal (&overlap, &imm32)
5004 && !operand_type_equal (&overlap, &imm32s)
5005 && !operand_type_equal (&overlap, &imm64))
29b0f896 5006 {
4eed87de
AM		 5007 as_bad (_("no instruction mnemonic suffix given; "
5008 "can't determine immediate size"));
29b0f896
AM		 5009 return 0;
5010 }
5011 }
40fb9820 5012 i.types[j] = overlap;
29b0f896 5013
40fb9820
L		 5014 return 1;
5015}
5016
5017static int
5018finalize_imm (void)
5019{
bc0844ae 5020 unsigned int j, n;
29b0f896 5021
bc0844ae
L		 5022 /* Update the first 2 immediate operands. */
5023 n = i.operands > 2 ? 2 : i.operands;
5024 if (n)
5025 {
5026 for (j = 0; j < n; j++)
5027 if (update_imm (j) == 0)
5028 return 0;
40fb9820 5029
bc0844ae
L		 5030 /* The 3rd operand can't be immediate operand. */
5031 gas_assert (operand_type_check (i.types[2], imm) == 0);
5032 }
29b0f896
AM		 5033
5034 return 1;
5035}
5036
c0f3af97
L		 5037static int
5038bad_implicit_operand (int xmm)
5039{
91d6fa6a
NC		 5040 const char *ireg = xmm ? "xmm0" : "ymm0";
5041
c0f3af97
L		 5042 if (intel_syntax)
5043 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5044 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5045 else
5046 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5047 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5048 return 0;
5049}
5050
29b0f896 5051static int
e3bb37b5 5052process_operands (void)
29b0f896
AM		 5053{
5054 /* Default segment register this instruction will use for memory
5055 accesses. 0 means unknown. This is only for optimizing out
5056 unnecessary segment overrides. */
5057 const seg_entry *default_seg = 0;
5058
2426c15f 5059 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5060 {
91d6fa6a
NC		 5061 unsigned int dupl = i.operands;
5062 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5063 unsigned int j;
5064
c0f3af97 5065 /* The destination must be an xmm register. */
9c2799c2 5066 gas_assert (i.reg_operands
91d6fa6a 5067 && MAX_OPERANDS > dupl
7ab9ffdd 5068 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5069
5070 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5071 {
c0f3af97 5072 /* The first operand is implicit and must be xmm0. */
9c2799c2 5073 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 5074 if (i.op[0].regs->reg_num != 0)
5075 return bad_implicit_operand (1);
5076
8cd7925b 5077 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5078 {
5079 /* Keep xmm0 for instructions with VEX prefix and 3
5080 sources. */
5081 goto duplicate;
5082 }
e2ec9d29 5083 else
c0f3af97
L		 5084 {
5085 /* We remove the first xmm0 and keep the number of
5086 operands unchanged, which in fact duplicates the
5087 destination. */
5088 for (j = 1; j < i.operands; j++)
5089 {
5090 i.op[j - 1] = i.op[j];
5091 i.types[j - 1] = i.types[j];
5092 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5093 }
5094 }
5095 }
5096 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5097 {
91d6fa6a 5098 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5099 && (i.tm.opcode_modifier.vexsources
5100 == VEX3SOURCES));
c0f3af97
L		 5101
5102 /* Add the implicit xmm0 for instructions with VEX prefix
5103 and 3 sources. */
5104 for (j = i.operands; j > 0; j--)
5105 {
5106 i.op[j] = i.op[j - 1];
5107 i.types[j] = i.types[j - 1];
5108 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5109 }
5110 i.op[0].regs
5111 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5112 i.types[0] = regxmm;
c0f3af97
L		 5113 i.tm.operand_types[0] = regxmm;
5114
5115 i.operands += 2;
5116 i.reg_operands += 2;
5117 i.tm.operands += 2;
5118
91d6fa6a 5119 dupl++;
c0f3af97 5120 dest++;
91d6fa6a
NC		 5121 i.op[dupl] = i.op[dest];
5122 i.types[dupl] = i.types[dest];
5123 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5124 }
c0f3af97
L		 5125 else
5126 {
5127duplicate:
5128 i.operands++;
5129 i.reg_operands++;
5130 i.tm.operands++;
5131
91d6fa6a
NC		 5132 i.op[dupl] = i.op[dest];
5133 i.types[dupl] = i.types[dest];
5134 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5135 }
5136
5137 if (i.tm.opcode_modifier.immext)
5138 process_immext ();
5139 }
5140 else if (i.tm.opcode_modifier.firstxmm0)
5141 {
5142 unsigned int j;
5143
5144 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 5145 gas_assert (i.reg_operands
7ab9ffdd
L		 5146 && (operand_type_equal (&i.types[0], &regxmm)
5147 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 5148 if (i.op[0].regs->reg_num != 0)
5149 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5150
5151 for (j = 1; j < i.operands; j++)
5152 {
5153 i.op[j - 1] = i.op[j];
5154 i.types[j - 1] = i.types[j];
5155
5156 /* We need to adjust fields in i.tm since they are used by
5157 build_modrm_byte. */
5158 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5159 }
5160
e2ec9d29
L		 5161 i.operands--;
5162 i.reg_operands--;
e2ec9d29
L		 5163 i.tm.operands--;
5164 }
5165 else if (i.tm.opcode_modifier.regkludge)
5166 {
5167 /* The imul $imm, %reg instruction is converted into
5168 imul $imm, %reg, %reg, and the clr %reg instruction
5169 is converted into xor %reg, %reg. */
5170
5171 unsigned int first_reg_op;
5172
5173 if (operand_type_check (i.types[0], reg))
5174 first_reg_op = 0;
5175 else
5176 first_reg_op = 1;
5177 /* Pretend we saw the extra register operand. */
9c2799c2 5178 gas_assert (i.reg_operands == 1
7ab9ffdd 5179 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5180 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5181 i.types[first_reg_op + 1] = i.types[first_reg_op];
5182 i.operands++;
5183 i.reg_operands++;
29b0f896
AM		 5184 }
5185
40fb9820 5186 if (i.tm.opcode_modifier.shortform)
29b0f896 5187 {
40fb9820
L		 5188 if (i.types[0].bitfield.sreg2
5189 || i.types[0].bitfield.sreg3)
29b0f896 5190 {
4eed87de
AM		 5191 if (i.tm.base_opcode == POP_SEG_SHORT
5192 && i.op[0].regs->reg_num == 1)
29b0f896 5193 {
a87af027 5194 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5195 return 0;
29b0f896 5196 }
4eed87de
AM		 5197 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5198 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5199 i.rex |= REX_B;
4eed87de
AM		 5200 }
5201 else
5202 {
7ab9ffdd 5203 /* The register or float register operand is in operand
85f10a01 5204 0 or 1. */
40fb9820 5205 unsigned int op;
7ab9ffdd
L		 5206
5207 if (i.types[0].bitfield.floatreg
5208 || operand_type_check (i.types[0], reg))
5209 op = 0;
5210 else
5211 op = 1;
4eed87de
AM		 5212 /* Register goes in low 3 bits of opcode. */
5213 i.tm.base_opcode |= i.op[op].regs->reg_num;
5214 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5215 i.rex |= REX_B;
40fb9820 5216 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5217 {
4eed87de
AM		 5218 /* Warn about some common errors, but press on regardless.
5219 The first case can be generated by gcc (<= 2.8.1). */
5220 if (i.operands == 2)
5221 {
5222 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5223 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5224 register_prefix, i.op[!intel_syntax].regs->reg_name,
5225 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5226 }
5227 else
5228 {
5229 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5230 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5231 register_prefix, i.op[0].regs->reg_name);
4eed87de 5232 }
29b0f896
AM		 5233 }
5234 }
5235 }
40fb9820 5236 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5237 {
5238 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5239 must be put into the modrm byte). Now, we make the modrm and
5240 index base bytes based on all the info we've collected. */
29b0f896
AM		 5241
5242 default_seg = build_modrm_byte ();
5243 }
8a2ed489 5244 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5245 {
5246 default_seg = &ds;
5247 }
40fb9820 5248 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5249 {
5250 /* For the string instructions that allow a segment override
5251 on one of their operands, the default segment is ds. */
5252 default_seg = &ds;
5253 }
5254
75178d9d
L		 5255 if (i.tm.base_opcode == 0x8d /* lea */
5256 && i.seg[0]
5257 && !quiet_warnings)
30123838 5258 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5259
5260 /* If a segment was explicitly specified, and the specified segment
5261 is not the default, use an opcode prefix to select it. If we
5262 never figured out what the default segment is, then default_seg
5263 will be zero at this point, and the specified segment prefix will
5264 always be used. */
29b0f896
AM		 5265 if ((i.seg[0]) && (i.seg[0] != default_seg))
5266 {
5267 if (!add_prefix (i.seg[0]->seg_prefix))
5268 return 0;
5269 }
5270 return 1;
5271}
5272
5273static const seg_entry *
e3bb37b5 5274build_modrm_byte (void)
29b0f896
AM		 5275{
5276 const seg_entry *default_seg = 0;
c0f3af97 5277 unsigned int source, dest;
8cd7925b 5278 int vex_3_sources;
c0f3af97
L		 5279
5280 /* The first operand of instructions with VEX prefix and 3 sources
5281 must be VEX_Imm4. */
8cd7925b 5282 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5283 if (vex_3_sources)
5284 {
91d6fa6a 5285 unsigned int nds, reg_slot;
4c2c6516 5286 expressionS *exp;
c0f3af97 5287
922d8de8 5288 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5289 && i.tm.opcode_modifier.immext)
5290 {
5291 dest = i.operands - 2;
5292 gas_assert (dest == 3);
5293 }
922d8de8 5294 else
a683cc34 5295 dest = i.operands - 1;
c0f3af97 5296 nds = dest - 1;
922d8de8 5297
a683cc34
SP		 5298 /* There are 2 kinds of instructions:
5299 1. 5 operands: 4 register operands or 3 register operands
5300 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5301 VexW0 or VexW1. The destination must be either XMM or YMM
5302 register.
5303 2. 4 operands: 4 register operands or 3 register operands
5304 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5305 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5306 || (i.reg_operands == 3 && i.mem_operands == 1))
5307 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5308 && (i.tm.opcode_modifier.veximmext
5309 || (i.imm_operands == 1
5310 && i.types[0].bitfield.vec_imm4
5311 && (i.tm.opcode_modifier.vexw == VEXW0
5312 || i.tm.opcode_modifier.vexw == VEXW1)
5313 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5314 || operand_type_equal (&i.tm.operand_types[dest], &regymm)))));
5315
5316 if (i.imm_operands == 0)
5317 {
5318 /* When there is no immediate operand, generate an 8bit
5319 immediate operand to encode the first operand. */
5320 exp = &im_expressions[i.imm_operands++];
5321 i.op[i.operands].imms = exp;
5322 i.types[i.operands] = imm8;
5323 i.operands++;
5324 /* If VexW1 is set, the first operand is the source and
5325 the second operand is encoded in the immediate operand. */
5326 if (i.tm.opcode_modifier.vexw == VEXW1)
5327 {
5328 source = 0;
5329 reg_slot = 1;
5330 }
5331 else
5332 {
5333 source = 1;
5334 reg_slot = 0;
5335 }
5336
5337 /* FMA swaps REG and NDS. */
5338 if (i.tm.cpu_flags.bitfield.cpufma)
5339 {
5340 unsigned int tmp;
5341 tmp = reg_slot;
5342 reg_slot = nds;
5343 nds = tmp;
5344 }
5345
24981e7b
L		 5346 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5347 &regxmm)
a683cc34
SP		 5348 || operand_type_equal (&i.tm.operand_types[reg_slot],
5349 &regymm));
5350 exp->X_op = O_constant;
5351 exp->X_add_number
5352 = ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5353 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5354 << 4);
a683cc34 5355 }
922d8de8 5356 else
a683cc34
SP		 5357 {
5358 unsigned int imm_slot;
5359
5360 if (i.tm.opcode_modifier.vexw == VEXW0)
5361 {
5362 /* If VexW0 is set, the third operand is the source and
5363 the second operand is encoded in the immediate
5364 operand. */
5365 source = 2;
5366 reg_slot = 1;
5367 }
5368 else
5369 {
5370 /* VexW1 is set, the second operand is the source and
5371 the third operand is encoded in the immediate
5372 operand. */
5373 source = 1;
5374 reg_slot = 2;
5375 }
5376
5377 if (i.tm.opcode_modifier.immext)
5378 {
5379 /* When ImmExt is set, the immdiate byte is the last
5380 operand. */
5381 imm_slot = i.operands - 1;
5382 source--;
5383 reg_slot--;
5384 }
5385 else
5386 {
5387 imm_slot = 0;
5388
5389 /* Turn on Imm8 so that output_imm will generate it. */
5390 i.types[imm_slot].bitfield.imm8 = 1;
5391 }
5392
24981e7b
L		 5393 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5394 &regxmm)
5395 || operand_type_equal (&i.tm.operand_types[reg_slot],
5396 &regymm));
a683cc34
SP		 5397 i.op[imm_slot].imms->X_add_number
5398 |= ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5399 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5400 << 4);
a683cc34
SP		 5401 }
5402
5403 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5404 || operand_type_equal (&i.tm.operand_types[nds],
5405 &regymm));
dae39acc 5406 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5407 }
5408 else
5409 source = dest = 0;
29b0f896
AM		 5410
5411 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5412 implicit registers do not count. If there are 3 register
5413 operands, it must be a instruction with VexNDS. For a
5414 instruction with VexNDD, the destination register is encoded
5415 in VEX prefix. If there are 4 register operands, it must be
5416 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5417 if (i.mem_operands == 0
5418 && ((i.reg_operands == 2
2426c15f 5419 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5420 || (i.reg_operands == 3
2426c15f 5421 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5422 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5423 {
cab737b9
L		 5424 switch (i.operands)
5425 {
5426 case 2:
5427 source = 0;
5428 break;
5429 case 3:
c81128dc
L		 5430 /* When there are 3 operands, one of them may be immediate,
5431 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5432 the first operand must be shift count register (cl) or it
5433 is an instruction with VexNDS. */
9c2799c2 5434 gas_assert (i.imm_operands == 1
7ab9ffdd 5435 || (i.imm_operands == 0
2426c15f 5436 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 5437 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5438 if (operand_type_check (i.types[0], imm)
5439 || i.types[0].bitfield.shiftcount)
5440 source = 1;
5441 else
5442 source = 0;
cab737b9
L		 5443 break;
5444 case 4:
368d64cc
L		 5445 /* When there are 4 operands, the first two must be 8bit
5446 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5447 one.
5448
5449 For instructions with VexNDS, if the first operand
5450 an imm8, the source operand is the 2nd one. If the last
5451 operand is imm8, the source operand is the first one. */
9c2799c2 5452 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5453 && i.types[0].bitfield.imm8
5454 && i.types[1].bitfield.imm8)
2426c15f 5455 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 5456 && i.imm_operands == 1
5457 && (i.types[0].bitfield.imm8
5458 || i.types[i.operands - 1].bitfield.imm8)));
9f2670f2
L		 5459 if (i.imm_operands == 2)
5460 source = 2;
5461 else
c0f3af97
L		 5462 {
5463 if (i.types[0].bitfield.imm8)
5464 source = 1;
5465 else
5466 source = 0;
5467 }
c0f3af97
L		 5468 break;
5469 case 5:
cab737b9
L		 5470 break;
5471 default:
5472 abort ();
5473 }
5474
c0f3af97
L		 5475 if (!vex_3_sources)
5476 {
5477 dest = source + 1;
5478
2426c15f 5479 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5480 {
5481 /* For instructions with VexNDS, the register-only
f12dc422
L		 5482 source operand must be 32/64bit integer, XMM or
5483 YMM register. It is encoded in VEX prefix. We
5484 need to clear RegMem bit before calling
5485 operand_type_equal. */
5486
5487 i386_operand_type op;
5488 unsigned int vvvv;
5489
5490 /* Check register-only source operand when two source
5491 operands are swapped. */
5492 if (!i.tm.operand_types[source].bitfield.baseindex
5493 && i.tm.operand_types[dest].bitfield.baseindex)
5494 {
5495 vvvv = source;
5496 source = dest;
5497 }
5498 else
5499 vvvv = dest;
5500
5501 op = i.tm.operand_types[vvvv];
fa99fab2 5502 op.bitfield.regmem = 0;
c0f3af97 5503 if ((dest + 1) >= i.operands
f12dc422
L		 5504 || (op.bitfield.reg32 != 1
5505 && !op.bitfield.reg64 != 1
5506 && !operand_type_equal (&op, &regxmm)
fa99fab2 5507 && !operand_type_equal (&op, &regymm)))
c0f3af97 5508 abort ();
f12dc422 5509 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 5510 dest++;
5511 }
5512 }
29b0f896
AM		 5513
5514 i.rm.mode = 3;
5515 /* One of the register operands will be encoded in the i.tm.reg
5516 field, the other in the combined i.tm.mode and i.tm.regmem
5517 fields. If no form of this instruction supports a memory
5518 destination operand, then we assume the source operand may
5519 sometimes be a memory operand and so we need to store the
5520 destination in the i.rm.reg field. */
40fb9820
L		 5521 if (!i.tm.operand_types[dest].bitfield.regmem
5522 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5523 {
5524 i.rm.reg = i.op[dest].regs->reg_num;
5525 i.rm.regmem = i.op[source].regs->reg_num;
5526 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5527 i.rex |= REX_R;
29b0f896 5528 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5529 i.rex |= REX_B;
29b0f896
AM		 5530 }
5531 else
5532 {
5533 i.rm.reg = i.op[source].regs->reg_num;
5534 i.rm.regmem = i.op[dest].regs->reg_num;
5535 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5536 i.rex |= REX_B;
29b0f896 5537 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5538 i.rex |= REX_R;
29b0f896 5539 }
161a04f6 5540 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5541 {
40fb9820
L		 5542 if (!i.types[0].bitfield.control
5543 && !i.types[1].bitfield.control)
c4a530c5 5544 abort ();
161a04f6 5545 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5546 add_prefix (LOCK_PREFIX_OPCODE);
5547 }
29b0f896
AM		 5548 }
5549 else
5550 { /* If it's not 2 reg operands... */
c0f3af97
L		 5551 unsigned int mem;
5552
29b0f896
AM		 5553 if (i.mem_operands)
5554 {
5555 unsigned int fake_zero_displacement = 0;
99018f42 5556 unsigned int op;
4eed87de 5557
7ab9ffdd
L		 5558 for (op = 0; op < i.operands; op++)
5559 if (operand_type_check (i.types[op], anymem))
5560 break;
7ab9ffdd 5561 gas_assert (op < i.operands);
29b0f896 5562
6c30d220
L		 5563 if (i.tm.opcode_modifier.vecsib)
5564 {
5565 if (i.index_reg->reg_num == RegEiz
5566 || i.index_reg->reg_num == RegRiz)
5567 abort ();
5568
5569 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5570 if (!i.base_reg)
5571 {
5572 i.sib.base = NO_BASE_REGISTER;
5573 i.sib.scale = i.log2_scale_factor;
5574 i.types[op].bitfield.disp8 = 0;
5575 i.types[op].bitfield.disp16 = 0;
5576 i.types[op].bitfield.disp64 = 0;
5577 if (flag_code != CODE_64BIT)
5578 {
5579 /* Must be 32 bit */
5580 i.types[op].bitfield.disp32 = 1;
5581 i.types[op].bitfield.disp32s = 0;
5582 }
5583 else
5584 {
5585 i.types[op].bitfield.disp32 = 0;
5586 i.types[op].bitfield.disp32s = 1;
5587 }
5588 }
5589 i.sib.index = i.index_reg->reg_num;
5590 if ((i.index_reg->reg_flags & RegRex) != 0)
5591 i.rex |= REX_X;
5592 }
5593
29b0f896
AM		 5594 default_seg = &ds;
5595
5596 if (i.base_reg == 0)
5597 {
5598 i.rm.mode = 0;
5599 if (!i.disp_operands)
6c30d220
L		 5600 {
5601 fake_zero_displacement = 1;
5602 /* Instructions with VSIB byte need 32bit displacement
5603 if there is no base register. */
5604 if (i.tm.opcode_modifier.vecsib)
5605 i.types[op].bitfield.disp32 = 1;
5606 }
29b0f896
AM		 5607 if (i.index_reg == 0)
5608 {
6c30d220 5609 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 5610 /* Operand is just <disp> */
20f0a1fc 5611 if (flag_code == CODE_64BIT)
29b0f896
AM		 5612 {
5613 /* 64bit mode overwrites the 32bit absolute
5614 addressing by RIP relative addressing and
5615 absolute addressing is encoded by one of the
5616 redundant SIB forms. */
5617 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5618 i.sib.base = NO_BASE_REGISTER;
5619 i.sib.index = NO_INDEX_REGISTER;
fc225355 5620 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5621 ? disp32s : disp32);
20f0a1fc 5622 }
fc225355
L		 5623 else if ((flag_code == CODE_16BIT)
5624 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5625 {
5626 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5627 i.types[op] = disp16;
20f0a1fc
NC		 5628 }
5629 else
5630 {
5631 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5632 i.types[op] = disp32;
29b0f896
AM		 5633 }
5634 }
6c30d220 5635 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 5636 {
6c30d220 5637 /* !i.base_reg && i.index_reg */
db51cc60
L		 5638 if (i.index_reg->reg_num == RegEiz
5639 || i.index_reg->reg_num == RegRiz)
5640 i.sib.index = NO_INDEX_REGISTER;
5641 else
5642 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5643 i.sib.base = NO_BASE_REGISTER;
5644 i.sib.scale = i.log2_scale_factor;
5645 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5646 i.types[op].bitfield.disp8 = 0;
5647 i.types[op].bitfield.disp16 = 0;
5648 i.types[op].bitfield.disp64 = 0;
29b0f896 5649 if (flag_code != CODE_64BIT)
40fb9820
L		 5650 {
5651 /* Must be 32 bit */
5652 i.types[op].bitfield.disp32 = 1;
5653 i.types[op].bitfield.disp32s = 0;
5654 }
29b0f896 5655 else
40fb9820
L		 5656 {
5657 i.types[op].bitfield.disp32 = 0;
5658 i.types[op].bitfield.disp32s = 1;
5659 }
29b0f896 5660 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5661 i.rex |= REX_X;
29b0f896
AM		 5662 }
5663 }
5664 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5665 else if (i.base_reg->reg_num == RegRip ||
5666 i.base_reg->reg_num == RegEip)
29b0f896 5667 {
6c30d220 5668 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 5669 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5670 i.types[op].bitfield.disp8 = 0;
5671 i.types[op].bitfield.disp16 = 0;
5672 i.types[op].bitfield.disp32 = 0;
5673 i.types[op].bitfield.disp32s = 1;
5674 i.types[op].bitfield.disp64 = 0;
71903a11 5675 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5676 if (! i.disp_operands)
5677 fake_zero_displacement = 1;
29b0f896 5678 }
40fb9820 5679 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 5680 {
6c30d220 5681 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 5682 switch (i.base_reg->reg_num)
5683 {
5684 case 3: /* (%bx) */
5685 if (i.index_reg == 0)
5686 i.rm.regmem = 7;
5687 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5688 i.rm.regmem = i.index_reg->reg_num - 6;
5689 break;
5690 case 5: /* (%bp) */
5691 default_seg = &ss;
5692 if (i.index_reg == 0)
5693 {
5694 i.rm.regmem = 6;
40fb9820 5695 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5696 {
5697 /* fake (%bp) into 0(%bp) */
40fb9820 5698 i.types[op].bitfield.disp8 = 1;
252b5132 5699 fake_zero_displacement = 1;
29b0f896
AM		 5700 }
5701 }
5702 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5703 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5704 break;
5705 default: /* (%si) -> 4 or (%di) -> 5 */
5706 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5707 }
5708 i.rm.mode = mode_from_disp_size (i.types[op]);
5709 }
5710 else /* i.base_reg and 32/64 bit mode */
5711 {
5712 if (flag_code == CODE_64BIT
40fb9820
L		 5713 && operand_type_check (i.types[op], disp))
5714 {
5715 i386_operand_type temp;
0dfbf9d7 5716 operand_type_set (&temp, 0);
40fb9820
L		 5717 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5718 i.types[op] = temp;
5719 if (i.prefix[ADDR_PREFIX] == 0)
5720 i.types[op].bitfield.disp32s = 1;
5721 else
5722 i.types[op].bitfield.disp32 = 1;
5723 }
20f0a1fc 5724
6c30d220
L		 5725 if (!i.tm.opcode_modifier.vecsib)
5726 i.rm.regmem = i.base_reg->reg_num;
29b0f896 5727 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5728 i.rex |= REX_B;
29b0f896
AM		 5729 i.sib.base = i.base_reg->reg_num;
5730 /* x86-64 ignores REX prefix bit here to avoid decoder
5731 complications. */
5732 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5733 {
5734 default_seg = &ss;
5735 if (i.disp_operands == 0)
5736 {
5737 fake_zero_displacement = 1;
40fb9820 5738 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5739 }
5740 }
5741 else if (i.base_reg->reg_num == ESP_REG_NUM)
5742 {
5743 default_seg = &ss;
5744 }
5745 i.sib.scale = i.log2_scale_factor;
5746 if (i.index_reg == 0)
5747 {
6c30d220 5748 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 5749 /* <disp>(%esp) becomes two byte modrm with no index
5750 register. We've already stored the code for esp
5751 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5752 Any base register besides %esp will not use the
5753 extra modrm byte. */
5754 i.sib.index = NO_INDEX_REGISTER;
29b0f896 5755 }
6c30d220 5756 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 5757 {
db51cc60
L		 5758 if (i.index_reg->reg_num == RegEiz
5759 || i.index_reg->reg_num == RegRiz)
5760 i.sib.index = NO_INDEX_REGISTER;
5761 else
5762 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5763 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5764 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5765 i.rex |= REX_X;
29b0f896 5766 }
67a4f2b7
AO		 5767
5768 if (i.disp_operands
5769 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5770 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5771 i.rm.mode = 0;
5772 else
a501d77e
L		 5773 {
5774 if (!fake_zero_displacement
5775 && !i.disp_operands
5776 && i.disp_encoding)
5777 {
5778 fake_zero_displacement = 1;
5779 if (i.disp_encoding == disp_encoding_8bit)
5780 i.types[op].bitfield.disp8 = 1;
5781 else
5782 i.types[op].bitfield.disp32 = 1;
5783 }
5784 i.rm.mode = mode_from_disp_size (i.types[op]);
5785 }
29b0f896 5786 }
252b5132 5787
29b0f896
AM		 5788 if (fake_zero_displacement)
5789 {
5790 /* Fakes a zero displacement assuming that i.types[op]
5791 holds the correct displacement size. */
5792 expressionS *exp;
5793
9c2799c2 5794 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5795 exp = &disp_expressions[i.disp_operands++];
5796 i.op[op].disps = exp;
5797 exp->X_op = O_constant;
5798 exp->X_add_number = 0;
5799 exp->X_add_symbol = (symbolS *) 0;
5800 exp->X_op_symbol = (symbolS *) 0;
5801 }
c0f3af97
L		 5802
5803 mem = op;
29b0f896 5804 }
c0f3af97
L		 5805 else
5806 mem = ~0;
252b5132 5807
8c43a48b 5808 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5809 {
5810 if (operand_type_check (i.types[0], imm))
5811 i.vex.register_specifier = NULL;
5812 else
5813 {
5814 /* VEX.vvvv encodes one of the sources when the first
5815 operand is not an immediate. */
1ef99a7b 5816 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5817 i.vex.register_specifier = i.op[0].regs;
5818 else
5819 i.vex.register_specifier = i.op[1].regs;
5820 }
5821
5822 /* Destination is a XMM register encoded in the ModRM.reg
5823 and VEX.R bit. */
5824 i.rm.reg = i.op[2].regs->reg_num;
5825 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5826 i.rex |= REX_R;
5827
5828 /* ModRM.rm and VEX.B encodes the other source. */
5829 if (!i.mem_operands)
5830 {
5831 i.rm.mode = 3;
5832
1ef99a7b 5833 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5834 i.rm.regmem = i.op[1].regs->reg_num;
5835 else
5836 i.rm.regmem = i.op[0].regs->reg_num;
5837
5838 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5839 i.rex |= REX_B;
5840 }
5841 }
2426c15f 5842 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 5843 {
5844 i.vex.register_specifier = i.op[2].regs;
5845 if (!i.mem_operands)
5846 {
5847 i.rm.mode = 3;
5848 i.rm.regmem = i.op[1].regs->reg_num;
5849 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5850 i.rex |= REX_B;
5851 }
5852 }
29b0f896
AM		 5853 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5854 (if any) based on i.tm.extension_opcode. Again, we must be
5855 careful to make sure that segment/control/debug/test/MMX
5856 registers are coded into the i.rm.reg field. */
f88c9eb0 5857 else if (i.reg_operands)
29b0f896 5858 {
99018f42 5859 unsigned int op;
7ab9ffdd
L		 5860 unsigned int vex_reg = ~0;
5861
5862 for (op = 0; op < i.operands; op++)
5863 if (i.types[op].bitfield.reg8
5864 || i.types[op].bitfield.reg16
5865 || i.types[op].bitfield.reg32
5866 || i.types[op].bitfield.reg64
5867 || i.types[op].bitfield.regmmx
5868 || i.types[op].bitfield.regxmm
5869 || i.types[op].bitfield.regymm
5870 || i.types[op].bitfield.sreg2
5871 || i.types[op].bitfield.sreg3
5872 || i.types[op].bitfield.control
5873 || i.types[op].bitfield.debug
5874 || i.types[op].bitfield.test)
5875 break;
c0209578 5876
7ab9ffdd
L		 5877 if (vex_3_sources)
5878 op = dest;
2426c15f 5879 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 5880 {
5881 /* For instructions with VexNDS, the register-only
5882 source operand is encoded in VEX prefix. */
5883 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5884
7ab9ffdd 5885 if (op > mem)
c0f3af97 5886 {
7ab9ffdd
L		 5887 vex_reg = op++;
5888 gas_assert (op < i.operands);
c0f3af97
L		 5889 }
5890 else
c0f3af97 5891 {
f12dc422
L		 5892 /* Check register-only source operand when two source
5893 operands are swapped. */
5894 if (!i.tm.operand_types[op].bitfield.baseindex
5895 && i.tm.operand_types[op + 1].bitfield.baseindex)
5896 {
5897 vex_reg = op;
5898 op += 2;
5899 gas_assert (mem == (vex_reg + 1)
5900 && op < i.operands);
5901 }
5902 else
5903 {
5904 vex_reg = op + 1;
5905 gas_assert (vex_reg < i.operands);
5906 }
c0f3af97 5907 }
7ab9ffdd 5908 }
2426c15f 5909 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 5910 {
f12dc422 5911 /* For instructions with VexNDD, the register destination
7ab9ffdd 5912 is encoded in VEX prefix. */
f12dc422
L		 5913 if (i.mem_operands == 0)
5914 {
5915 /* There is no memory operand. */
5916 gas_assert ((op + 2) == i.operands);
5917 vex_reg = op + 1;
5918 }
5919 else
8d63c93e 5920 {
f12dc422
L		 5921 /* There are only 2 operands. */
5922 gas_assert (op < 2 && i.operands == 2);
5923 vex_reg = 1;
5924 }
7ab9ffdd
L		 5925 }
5926 else
5927 gas_assert (op < i.operands);
99018f42 5928
7ab9ffdd
L		 5929 if (vex_reg != (unsigned int) ~0)
5930 {
f12dc422 5931 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 5932
f12dc422
L		 5933 if (type->bitfield.reg32 != 1
5934 && type->bitfield.reg64 != 1
5935 && !operand_type_equal (type, &regxmm)
5936 && !operand_type_equal (type, &regymm))
7ab9ffdd 5937 abort ();
f88c9eb0 5938
7ab9ffdd
L		 5939 i.vex.register_specifier = i.op[vex_reg].regs;
5940 }
5941
1b9f0c97
L		 5942 /* Don't set OP operand twice. */
5943 if (vex_reg != op)
7ab9ffdd 5944 {
1b9f0c97
L		 5945 /* If there is an extension opcode to put here, the
5946 register number must be put into the regmem field. */
5947 if (i.tm.extension_opcode != None)
5948 {
5949 i.rm.regmem = i.op[op].regs->reg_num;
5950 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5951 i.rex |= REX_B;
5952 }
5953 else
5954 {
5955 i.rm.reg = i.op[op].regs->reg_num;
5956 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5957 i.rex |= REX_R;
5958 }
7ab9ffdd 5959 }
252b5132 5960
29b0f896
AM		 5961 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5962 must set it to 3 to indicate this is a register operand
5963 in the regmem field. */
5964 if (!i.mem_operands)
5965 i.rm.mode = 3;
5966 }
252b5132 5967
29b0f896 5968 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5969 if (i.tm.extension_opcode != None)
29b0f896
AM		 5970 i.rm.reg = i.tm.extension_opcode;
5971 }
5972 return default_seg;
5973}
252b5132 5974
29b0f896 5975static void
e3bb37b5 5976output_branch (void)
29b0f896
AM		 5977{
5978 char *p;
f8a5c266 5979 int size;
29b0f896
AM		 5980 int code16;
5981 int prefix;
5982 relax_substateT subtype;
5983 symbolS *sym;
5984 offsetT off;
5985
f8a5c266 5986 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 5987 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 5988
5989 prefix = 0;
5990 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5991 {
29b0f896
AM		 5992 prefix = 1;
5993 i.prefixes -= 1;
5994 code16 ^= CODE16;
252b5132 5995 }
29b0f896
AM		 5996 /* Pentium4 branch hints. */
5997 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5998 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5999 {
29b0f896
AM		 6000 prefix++;
6001 i.prefixes--;
6002 }
6003 if (i.prefix[REX_PREFIX] != 0)
6004 {
6005 prefix++;
6006 i.prefixes--;
2f66722d
AM		 6007 }
6008
29b0f896
AM		 6009 if (i.prefixes != 0 && !intel_syntax)
6010 as_warn (_("skipping prefixes on this instruction"));
6011
6012 /* It's always a symbol; End frag & setup for relax.
6013 Make sure there is enough room in this frag for the largest
6014 instruction we may generate in md_convert_frag. This is 2
6015 bytes for the opcode and room for the prefix and largest
6016 displacement. */
6017 frag_grow (prefix + 2 + 4);
6018 /* Prefix and 1 opcode byte go in fr_fix. */
6019 p = frag_more (prefix + 1);
6020 if (i.prefix[DATA_PREFIX] != 0)
6021 *p++ = DATA_PREFIX_OPCODE;
6022 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6023 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6024 *p++ = i.prefix[SEG_PREFIX];
6025 if (i.prefix[REX_PREFIX] != 0)
6026 *p++ = i.prefix[REX_PREFIX];
6027 *p = i.tm.base_opcode;
6028
6029 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6030 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6031 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6032 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6033 else
f8a5c266 6034 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6035 subtype |= code16;
3e73aa7c 6036
29b0f896
AM		 6037 sym = i.op[0].disps->X_add_symbol;
6038 off = i.op[0].disps->X_add_number;
3e73aa7c 6039
29b0f896
AM		 6040 if (i.op[0].disps->X_op != O_constant
6041 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6042 {
29b0f896
AM		 6043 /* Handle complex expressions. */
6044 sym = make_expr_symbol (i.op[0].disps);
6045 off = 0;
6046 }
3e73aa7c 6047
29b0f896
AM		 6048 /* 1 possible extra opcode + 4 byte displacement go in var part.
6049 Pass reloc in fr_var. */
6050 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
6051}
3e73aa7c 6052
29b0f896 6053static void
e3bb37b5 6054output_jump (void)
29b0f896
AM		 6055{
6056 char *p;
6057 int size;
3e02c1cc 6058 fixS *fixP;
29b0f896 6059
40fb9820 6060 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6061 {
6062 /* This is a loop or jecxz type instruction. */
6063 size = 1;
6064 if (i.prefix[ADDR_PREFIX] != 0)
6065 {
6066 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6067 i.prefixes -= 1;
6068 }
6069 /* Pentium4 branch hints. */
6070 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6071 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6072 {
6073 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6074 i.prefixes--;
3e73aa7c
JH		 6075 }
6076 }
29b0f896
AM		 6077 else
6078 {
6079 int code16;
3e73aa7c 6080
29b0f896
AM		 6081 code16 = 0;
6082 if (flag_code == CODE_16BIT)
6083 code16 = CODE16;
3e73aa7c 6084
29b0f896
AM		 6085 if (i.prefix[DATA_PREFIX] != 0)
6086 {
6087 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6088 i.prefixes -= 1;
6089 code16 ^= CODE16;
6090 }
252b5132 6091
29b0f896
AM		 6092 size = 4;
6093 if (code16)
6094 size = 2;
6095 }
9fcc94b6 6096
29b0f896
AM		 6097 if (i.prefix[REX_PREFIX] != 0)
6098 {
6099 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6100 i.prefixes -= 1;
6101 }
252b5132 6102
29b0f896
AM		 6103 if (i.prefixes != 0 && !intel_syntax)
6104 as_warn (_("skipping prefixes on this instruction"));
e0890092 6105
42164a71
L		 6106 p = frag_more (i.tm.opcode_length + size);
6107 switch (i.tm.opcode_length)
6108 {
6109 case 2:
6110 *p++ = i.tm.base_opcode >> 8;
6111 case 1:
6112 *p++ = i.tm.base_opcode;
6113 break;
6114 default:
6115 abort ();
6116 }
e0890092 6117
3e02c1cc
AM		 6118 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6119 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
6120
6121 /* All jumps handled here are signed, but don't use a signed limit
6122 check for 32 and 16 bit jumps as we want to allow wrap around at
6123 4G and 64k respectively. */
6124 if (size == 1)
6125 fixP->fx_signed = 1;
29b0f896 6126}
e0890092 6127
29b0f896 6128static void
e3bb37b5 6129output_interseg_jump (void)
29b0f896
AM		 6130{
6131 char *p;
6132 int size;
6133 int prefix;
6134 int code16;
252b5132 6135
29b0f896
AM		 6136 code16 = 0;
6137 if (flag_code == CODE_16BIT)
6138 code16 = CODE16;
a217f122 6139
29b0f896
AM		 6140 prefix = 0;
6141 if (i.prefix[DATA_PREFIX] != 0)
6142 {
6143 prefix = 1;
6144 i.prefixes -= 1;
6145 code16 ^= CODE16;
6146 }
6147 if (i.prefix[REX_PREFIX] != 0)
6148 {
6149 prefix++;
6150 i.prefixes -= 1;
6151 }
252b5132 6152
29b0f896
AM		 6153 size = 4;
6154 if (code16)
6155 size = 2;
252b5132 6156
29b0f896
AM		 6157 if (i.prefixes != 0 && !intel_syntax)
6158 as_warn (_("skipping prefixes on this instruction"));
252b5132 6159
29b0f896
AM		 6160 /* 1 opcode; 2 segment; offset */
6161 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6162
29b0f896
AM		 6163 if (i.prefix[DATA_PREFIX] != 0)
6164 *p++ = DATA_PREFIX_OPCODE;
252b5132 6165
29b0f896
AM		 6166 if (i.prefix[REX_PREFIX] != 0)
6167 *p++ = i.prefix[REX_PREFIX];
252b5132 6168
29b0f896
AM		 6169 *p++ = i.tm.base_opcode;
6170 if (i.op[1].imms->X_op == O_constant)
6171 {
6172 offsetT n = i.op[1].imms->X_add_number;
252b5132 6173
29b0f896
AM		 6174 if (size == 2
6175 && !fits_in_unsigned_word (n)
6176 && !fits_in_signed_word (n))
6177 {
6178 as_bad (_("16-bit jump out of range"));
6179 return;
6180 }
6181 md_number_to_chars (p, n, size);
6182 }
6183 else
6184 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6185 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
6186 if (i.op[0].imms->X_op != O_constant)
6187 as_bad (_("can't handle non absolute segment in `%s'"),
6188 i.tm.name);
6189 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6190}
a217f122 6191
29b0f896 6192static void
e3bb37b5 6193output_insn (void)
29b0f896 6194{
2bbd9c25
JJ		 6195 fragS *insn_start_frag;
6196 offsetT insn_start_off;
6197
29b0f896
AM		 6198 /* Tie dwarf2 debug info to the address at the start of the insn.
6199 We can't do this after the insn has been output as the current
6200 frag may have been closed off. eg. by frag_var. */
6201 dwarf2_emit_insn (0);
6202
2bbd9c25
JJ		 6203 insn_start_frag = frag_now;
6204 insn_start_off = frag_now_fix ();
6205
29b0f896 6206 /* Output jumps. */
40fb9820 6207 if (i.tm.opcode_modifier.jump)
29b0f896 6208 output_branch ();
40fb9820
L		 6209 else if (i.tm.opcode_modifier.jumpbyte
6210 || i.tm.opcode_modifier.jumpdword)
29b0f896 6211 output_jump ();
40fb9820 6212 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6213 output_interseg_jump ();
6214 else
6215 {
6216 /* Output normal instructions here. */
6217 char *p;
6218 unsigned char *q;
47465058 6219 unsigned int j;
331d2d0d 6220 unsigned int prefix;
4dffcebc 6221
c0f3af97 6222 /* Since the VEX prefix contains the implicit prefix, we don't
89e71f5c 6223 need the explicit prefix. */
c0f3af97 6224 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 6225 {
c0f3af97 6226 switch (i.tm.opcode_length)
bc4bd9ab 6227 {
c0f3af97
L		 6228 case 3:
6229 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6230 {
c0f3af97
L		 6231 prefix = (i.tm.base_opcode >> 24) & 0xff;
6232 goto check_prefix;
6233 }
6234 break;
6235 case 2:
6236 if ((i.tm.base_opcode & 0xff0000) != 0)
6237 {
6238 prefix = (i.tm.base_opcode >> 16) & 0xff;
6239 if (i.tm.cpu_flags.bitfield.cpupadlock)
6240 {
4dffcebc 6241check_prefix:
c0f3af97 6242 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6243 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6244 != REPE_PREFIX_OPCODE))
6245 add_prefix (prefix);
6246 }
6247 else
4dffcebc
L		 6248 add_prefix (prefix);
6249 }
c0f3af97
L		 6250 break;
6251 case 1:
6252 break;
6253 default:
6254 abort ();
bc4bd9ab 6255 }
c0f3af97
L		 6256
6257 /* The prefix bytes. */
6258 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6259 if (*q)
6260 FRAG_APPEND_1_CHAR (*q);
0f10071e 6261 }
ae5c1c7b 6262 else
c0f3af97
L		 6263 {
6264 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6265 if (*q)
6266 switch (j)
6267 {
6268 case REX_PREFIX:
6269 /* REX byte is encoded in VEX prefix. */
6270 break;
6271 case SEG_PREFIX:
6272 case ADDR_PREFIX:
6273 FRAG_APPEND_1_CHAR (*q);
6274 break;
6275 default:
6276 /* There should be no other prefixes for instructions
6277 with VEX prefix. */
6278 abort ();
6279 }
6280
6281 /* Now the VEX prefix. */
6282 p = frag_more (i.vex.length);
6283 for (j = 0; j < i.vex.length; j++)
6284 p[j] = i.vex.bytes[j];
6285 }
252b5132 6286
29b0f896 6287 /* Now the opcode; be careful about word order here! */
4dffcebc 6288 if (i.tm.opcode_length == 1)
29b0f896
AM		 6289 {
6290 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
6291 }
6292 else
6293 {
4dffcebc 6294 switch (i.tm.opcode_length)
331d2d0d 6295 {
4dffcebc 6296 case 3:
331d2d0d
L		 6297 p = frag_more (3);
6298 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 6299 break;
6300 case 2:
6301 p = frag_more (2);
6302 break;
6303 default:
6304 abort ();
6305 break;
331d2d0d 6306 }
0f10071e 6307
29b0f896
AM		 6308 /* Put out high byte first: can't use md_number_to_chars! */
6309 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6310 *p = i.tm.base_opcode & 0xff;
6311 }
3e73aa7c 6312
29b0f896 6313 /* Now the modrm byte and sib byte (if present). */
40fb9820 6314 if (i.tm.opcode_modifier.modrm)
29b0f896 6315 {
4a3523fa
L		 6316 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6317 | i.rm.reg << 3
6318 | i.rm.mode << 6));
29b0f896
AM		 6319 /* If i.rm.regmem == ESP (4)
6320 && i.rm.mode != (Register mode)
6321 && not 16 bit
6322 ==> need second modrm byte. */
6323 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
6324 && i.rm.mode != 3
40fb9820 6325 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 6326 FRAG_APPEND_1_CHAR ((i.sib.base << 0
6327 | i.sib.index << 3
6328 | i.sib.scale << 6));
29b0f896 6329 }
3e73aa7c 6330
29b0f896 6331 if (i.disp_operands)
2bbd9c25 6332 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6333
29b0f896 6334 if (i.imm_operands)
2bbd9c25 6335 output_imm (insn_start_frag, insn_start_off);
29b0f896 6336 }
252b5132 6337
29b0f896
AM		 6338#ifdef DEBUG386
6339 if (flag_debug)
6340 {
7b81dfbb 6341 pi ("" /*line*/, &i);
29b0f896
AM		 6342 }
6343#endif /* DEBUG386 */
6344}
252b5132 6345
e205caa7
L		 6346/* Return the size of the displacement operand N. */
6347
6348static int
6349disp_size (unsigned int n)
6350{
6351 int size = 4;
40fb9820
L		 6352 if (i.types[n].bitfield.disp64)
6353 size = 8;
6354 else if (i.types[n].bitfield.disp8)
6355 size = 1;
6356 else if (i.types[n].bitfield.disp16)
6357 size = 2;
e205caa7
L		 6358 return size;
6359}
6360
6361/* Return the size of the immediate operand N. */
6362
6363static int
6364imm_size (unsigned int n)
6365{
6366 int size = 4;
40fb9820
L		 6367 if (i.types[n].bitfield.imm64)
6368 size = 8;
6369 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6370 size = 1;
6371 else if (i.types[n].bitfield.imm16)
6372 size = 2;
e205caa7
L		 6373 return size;
6374}
6375
29b0f896 6376static void
64e74474 6377output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6378{
6379 char *p;
6380 unsigned int n;
252b5132 6381
29b0f896
AM		 6382 for (n = 0; n < i.operands; n++)
6383 {
40fb9820 6384 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6385 {
6386 if (i.op[n].disps->X_op == O_constant)
6387 {
e205caa7 6388 int size = disp_size (n);
29b0f896 6389 offsetT val;
252b5132 6390
29b0f896
AM		 6391 val = offset_in_range (i.op[n].disps->X_add_number,
6392 size);
6393 p = frag_more (size);
6394 md_number_to_chars (p, val, size);
6395 }
6396 else
6397 {
f86103b7 6398 enum bfd_reloc_code_real reloc_type;
e205caa7 6399 int size = disp_size (n);
40fb9820 6400 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6401 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6402
e205caa7 6403 /* We can't have 8 bit displacement here. */
9c2799c2 6404 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 6405
29b0f896
AM		 6406 /* The PC relative address is computed relative
6407 to the instruction boundary, so in case immediate
6408 fields follows, we need to adjust the value. */
6409 if (pcrel && i.imm_operands)
6410 {
29b0f896 6411 unsigned int n1;
e205caa7 6412 int sz = 0;
252b5132 6413
29b0f896 6414 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6415 if (operand_type_check (i.types[n1], imm))
252b5132 6416 {
e205caa7
L		 6417 /* Only one immediate is allowed for PC
6418 relative address. */
9c2799c2 6419 gas_assert (sz == 0);
e205caa7
L		 6420 sz = imm_size (n1);
6421 i.op[n].disps->X_add_number -= sz;
252b5132 6422 }
29b0f896 6423 /* We should find the immediate. */
9c2799c2 6424 gas_assert (sz != 0);
29b0f896 6425 }
520dc8e8 6426
29b0f896 6427 p = frag_more (size);
2bbd9c25 6428 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6429 if (GOT_symbol
2bbd9c25 6430 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6431 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6432 || reloc_type == BFD_RELOC_X86_64_32S
6433 || (reloc_type == BFD_RELOC_64
6434 && object_64bit))
d6ab8113
JB		 6435 && (i.op[n].disps->X_op == O_symbol
6436 || (i.op[n].disps->X_op == O_add
6437 && ((symbol_get_value_expression
6438 (i.op[n].disps->X_op_symbol)->X_op)
6439 == O_subtract))))
6440 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6441 {
6442 offsetT add;
6443
6444 if (insn_start_frag == frag_now)
6445 add = (p - frag_now->fr_literal) - insn_start_off;
6446 else
6447 {
6448 fragS *fr;
6449
6450 add = insn_start_frag->fr_fix - insn_start_off;
6451 for (fr = insn_start_frag->fr_next;
6452 fr && fr != frag_now; fr = fr->fr_next)
6453 add += fr->fr_fix;
6454 add += p - frag_now->fr_literal;
6455 }
6456
4fa24527 6457 if (!object_64bit)
7b81dfbb
AJ		 6458 {
6459 reloc_type = BFD_RELOC_386_GOTPC;
6460 i.op[n].imms->X_add_number += add;
6461 }
6462 else if (reloc_type == BFD_RELOC_64)
6463 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6464 else
7b81dfbb
AJ		 6465 /* Don't do the adjustment for x86-64, as there
6466 the pcrel addressing is relative to the _next_
6467 insn, and that is taken care of in other code. */
d6ab8113 6468 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6469 }
062cd5e7 6470 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6471 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6472 }
6473 }
6474 }
6475}
252b5132 6476
29b0f896 6477static void
64e74474 6478output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6479{
6480 char *p;
6481 unsigned int n;
252b5132 6482
29b0f896
AM		 6483 for (n = 0; n < i.operands; n++)
6484 {
40fb9820 6485 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6486 {
6487 if (i.op[n].imms->X_op == O_constant)
6488 {
e205caa7 6489 int size = imm_size (n);
29b0f896 6490 offsetT val;
b4cac588 6491
29b0f896
AM		 6492 val = offset_in_range (i.op[n].imms->X_add_number,
6493 size);
6494 p = frag_more (size);
6495 md_number_to_chars (p, val, size);
6496 }
6497 else
6498 {
6499 /* Not absolute_section.
6500 Need a 32-bit fixup (don't support 8bit
6501 non-absolute imms). Try to support other
6502 sizes ... */
f86103b7 6503 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6504 int size = imm_size (n);
6505 int sign;
29b0f896 6506
40fb9820 6507 if (i.types[n].bitfield.imm32s
a7d61044 6508 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6509 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6510 sign = 1;
e205caa7
L		 6511 else
6512 sign = 0;
520dc8e8 6513
29b0f896
AM		 6514 p = frag_more (size);
6515 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6516
2bbd9c25
JJ		 6517 /* This is tough to explain. We end up with this one if we
6518 * have operands that look like
6519 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6520 * obtain the absolute address of the GOT, and it is strongly
6521 * preferable from a performance point of view to avoid using
6522 * a runtime relocation for this. The actual sequence of
6523 * instructions often look something like:
6524 *
6525 * call .L66
6526 * .L66:
6527 * popl %ebx
6528 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6529 *
6530 * The call and pop essentially return the absolute address
6531 * of the label .L66 and store it in %ebx. The linker itself
6532 * will ultimately change the first operand of the addl so
6533 * that %ebx points to the GOT, but to keep things simple, the
6534 * .o file must have this operand set so that it generates not
6535 * the absolute address of .L66, but the absolute address of
6536 * itself. This allows the linker itself simply treat a GOTPC
6537 * relocation as asking for a pcrel offset to the GOT to be
6538 * added in, and the addend of the relocation is stored in the
6539 * operand field for the instruction itself.
6540 *
6541 * Our job here is to fix the operand so that it would add
6542 * the correct offset so that %ebx would point to itself. The
6543 * thing that is tricky is that .-.L66 will point to the
6544 * beginning of the instruction, so we need to further modify
6545 * the operand so that it will point to itself. There are
6546 * other cases where you have something like:
6547 *
6548 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6549 *
6550 * and here no correction would be required. Internally in
6551 * the assembler we treat operands of this form as not being
6552 * pcrel since the '.' is explicitly mentioned, and I wonder
6553 * whether it would simplify matters to do it this way. Who
6554 * knows. In earlier versions of the PIC patches, the
6555 * pcrel_adjust field was used to store the correction, but
6556 * since the expression is not pcrel, I felt it would be
6557 * confusing to do it this way. */
6558
d6ab8113 6559 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6560 || reloc_type == BFD_RELOC_X86_64_32S
6561 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6562 && GOT_symbol
6563 && GOT_symbol == i.op[n].imms->X_add_symbol
6564 && (i.op[n].imms->X_op == O_symbol
6565 || (i.op[n].imms->X_op == O_add
6566 && ((symbol_get_value_expression
6567 (i.op[n].imms->X_op_symbol)->X_op)
6568 == O_subtract))))
6569 {
2bbd9c25
JJ		 6570 offsetT add;
6571
6572 if (insn_start_frag == frag_now)
6573 add = (p - frag_now->fr_literal) - insn_start_off;
6574 else
6575 {
6576 fragS *fr;
6577
6578 add = insn_start_frag->fr_fix - insn_start_off;
6579 for (fr = insn_start_frag->fr_next;
6580 fr && fr != frag_now; fr = fr->fr_next)
6581 add += fr->fr_fix;
6582 add += p - frag_now->fr_literal;
6583 }
6584
4fa24527 6585 if (!object_64bit)
d6ab8113 6586 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6587 else if (size == 4)
d6ab8113 6588 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6589 else if (size == 8)
6590 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6591 i.op[n].imms->X_add_number += add;
29b0f896 6592 }
29b0f896
AM		 6593 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6594 i.op[n].imms, 0, reloc_type);
6595 }
6596 }
6597 }
252b5132
RH		 6598}
6599\f
d182319b
JB		 6600/* x86_cons_fix_new is called via the expression parsing code when a
6601 reloc is needed. We use this hook to get the correct .got reloc. */
6602static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6603static int cons_sign = -1;
6604
6605void
e3bb37b5 6606x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6607 expressionS *exp)
d182319b
JB		 6608{
6609 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6610
6611 got_reloc = NO_RELOC;
6612
6613#ifdef TE_PE
6614 if (exp->X_op == O_secrel)
6615 {
6616 exp->X_op = O_symbol;
6617 r = BFD_RELOC_32_SECREL;
6618 }
6619#endif
6620
6621 fix_new_exp (frag, off, len, exp, 0, r);
6622}
6623
357d1bd8
L		 6624/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
6625 purpose of the `.dc.a' internal pseudo-op. */
6626
6627int
6628x86_address_bytes (void)
6629{
6630 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
6631 return 4;
6632 return stdoutput->arch_info->bits_per_address / 8;
6633}
6634
d382c579
TG		 6635#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
6636 || defined (LEX_AT)
718ddfc0
JB		 6637# define lex_got(reloc, adjust, types) NULL
6638#else
f3c180ae
AM		 6639/* Parse operands of the form
6640 <symbol>@GOTOFF+<nnn>
6641 and similar .plt or .got references.
6642
6643 If we find one, set up the correct relocation in RELOC and copy the
6644 input string, minus the `@GOTOFF' into a malloc'd buffer for
6645 parsing by the calling routine. Return this buffer, and if ADJUST
6646 is non-null set it to the length of the string we removed from the
6647 input line. Otherwise return NULL. */
6648static char *
91d6fa6a 6649lex_got (enum bfd_reloc_code_real *rel,
64e74474 6650 int *adjust,
40fb9820 6651 i386_operand_type *types)
f3c180ae 6652{
7b81dfbb
AJ		 6653 /* Some of the relocations depend on the size of what field is to
6654 be relocated. But in our callers i386_immediate and i386_displacement
6655 we don't yet know the operand size (this will be set by insn
6656 matching). Hence we record the word32 relocation here,
6657 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6658 static const struct {
6659 const char *str;
cff8d58a 6660 int len;
4fa24527 6661 const enum bfd_reloc_code_real rel[2];
40fb9820 6662 const i386_operand_type types64;
f3c180ae 6663 } gotrel[] = {
cff8d58a
L		 6664 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
6665 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6666 OPERAND_TYPE_IMM64 },
cff8d58a
L		 6667 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
6668 BFD_RELOC_X86_64_PLT32 },
40fb9820 6669 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6670 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
6671 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6672 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6673 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
6674 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6675 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6676 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
6677 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6678 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6679 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
6680 BFD_RELOC_X86_64_TLSGD },
40fb9820 6681 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6682 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
6683 _dummy_first_bfd_reloc_code_real },
40fb9820 6684 OPERAND_TYPE_NONE },
cff8d58a
L		 6685 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
6686 BFD_RELOC_X86_64_TLSLD },
40fb9820 6687 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6688 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
6689 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6690 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6691 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
6692 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6693 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6694 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
6695 _dummy_first_bfd_reloc_code_real },
40fb9820 6696 OPERAND_TYPE_NONE },
cff8d58a
L		 6697 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
6698 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 6699 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6700 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
6701 _dummy_first_bfd_reloc_code_real },
40fb9820 6702 OPERAND_TYPE_NONE },
cff8d58a
L		 6703 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
6704 _dummy_first_bfd_reloc_code_real },
40fb9820 6705 OPERAND_TYPE_NONE },
cff8d58a
L		 6706 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
6707 BFD_RELOC_X86_64_GOT32 },
40fb9820 6708 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 6709 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
6710 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6711 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6712 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
6713 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6714 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6715 };
6716 char *cp;
6717 unsigned int j;
6718
d382c579 6719#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 6720 if (!IS_ELF)
6721 return NULL;
d382c579 6722#endif
718ddfc0 6723
f3c180ae 6724 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6725 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6726 return NULL;
6727
47465058 6728 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 6729 {
cff8d58a 6730 int len = gotrel[j].len;
28f81592 6731 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6732 {
4fa24527 6733 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6734 {
28f81592
AM		 6735 int first, second;
6736 char *tmpbuf, *past_reloc;
f3c180ae 6737
91d6fa6a 6738 *rel = gotrel[j].rel[object_64bit];
28f81592
AM		 6739 if (adjust)
6740 *adjust = len;
f3c180ae 6741
3956db08
JB		 6742 if (types)
6743 {
6744 if (flag_code != CODE_64BIT)
40fb9820
L		 6745 {
6746 types->bitfield.imm32 = 1;
6747 types->bitfield.disp32 = 1;
6748 }
3956db08
JB		 6749 else
6750 *types = gotrel[j].types64;
6751 }
6752
f3c180ae
AM		 6753 if (GOT_symbol == NULL)
6754 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6755
28f81592 6756 /* The length of the first part of our input line. */
f3c180ae 6757 first = cp - input_line_pointer;
28f81592
AM		 6758
6759 /* The second part goes from after the reloc token until
67c11a9b 6760 (and including) an end_of_line char or comma. */
28f81592 6761 past_reloc = cp + 1 + len;
67c11a9b
AM		 6762 cp = past_reloc;
6763 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6764 ++cp;
6765 second = cp + 1 - past_reloc;
28f81592
AM		 6766
6767 /* Allocate and copy string. The trailing NUL shouldn't
6768 be necessary, but be safe. */
1e9cc1c2 6769 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6770 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6771 if (second != 0 && *past_reloc != ' ')
6772 /* Replace the relocation token with ' ', so that
6773 errors like foo@GOTOFF1 will be detected. */
6774 tmpbuf[first++] = ' ';
6775 memcpy (tmpbuf + first, past_reloc, second);
6776 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6777 return tmpbuf;
6778 }
6779
4fa24527
JB		 6780 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6781 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6782 return NULL;
6783 }
6784 }
6785
6786 /* Might be a symbol version string. Don't as_bad here. */
6787 return NULL;
6788}
4e4f7c87 6789#endif
f3c180ae 6790
f3c180ae 6791void
e3bb37b5 6792x86_cons (expressionS *exp, int size)
f3c180ae 6793{
ee86248c
JB		 6794 intel_syntax = -intel_syntax;
6795
3c7b9c2c 6796 exp->X_md = 0;
4fa24527 6797 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6798 {
6799 /* Handle @GOTOFF and the like in an expression. */
6800 char *save;
6801 char *gotfree_input_line;
4a57f2cf 6802 int adjust = 0;
f3c180ae
AM		 6803
6804 save = input_line_pointer;
3956db08 6805 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6806 if (gotfree_input_line)
6807 input_line_pointer = gotfree_input_line;
6808
6809 expression (exp);
6810
6811 if (gotfree_input_line)
6812 {
6813 /* expression () has merrily parsed up to the end of line,
6814 or a comma - in the wrong buffer. Transfer how far
6815 input_line_pointer has moved to the right buffer. */
6816 input_line_pointer = (save
6817 + (input_line_pointer - gotfree_input_line)
6818 + adjust);
6819 free (gotfree_input_line);
3992d3b7
AM		 6820 if (exp->X_op == O_constant
6821 || exp->X_op == O_absent
6822 || exp->X_op == O_illegal
0398aac5 6823 || exp->X_op == O_register
3992d3b7
AM		 6824 || exp->X_op == O_big)
6825 {
6826 char c = *input_line_pointer;
6827 *input_line_pointer = 0;
6828 as_bad (_("missing or invalid expression `%s'"), save);
6829 *input_line_pointer = c;
6830 }
f3c180ae
AM		 6831 }
6832 }
6833 else
6834 expression (exp);
ee86248c
JB		 6835
6836 intel_syntax = -intel_syntax;
6837
6838 if (intel_syntax)
6839 i386_intel_simplify (exp);
f3c180ae 6840}
f3c180ae 6841
9f32dd5b
L		 6842static void
6843signed_cons (int size)
6482c264 6844{
d182319b
JB		 6845 if (flag_code == CODE_64BIT)
6846 cons_sign = 1;
6847 cons (size);
6848 cons_sign = -1;
6482c264
NC		 6849}
6850
d182319b 6851#ifdef TE_PE
6482c264 6852static void
7016a5d5 6853pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 6854{
6855 expressionS exp;
6856
6857 do
6858 {
6859 expression (&exp);
6860 if (exp.X_op == O_symbol)
6861 exp.X_op = O_secrel;
6862
6863 emit_expr (&exp, 4);
6864 }
6865 while (*input_line_pointer++ == ',');
6866
6867 input_line_pointer--;
6868 demand_empty_rest_of_line ();
6869}
6482c264
NC		 6870#endif
6871
252b5132 6872static int
70e41ade 6873i386_immediate (char *imm_start)
252b5132
RH		 6874{
6875 char *save_input_line_pointer;
f3c180ae 6876 char *gotfree_input_line;
252b5132 6877 segT exp_seg = 0;
47926f60 6878 expressionS *exp;
40fb9820
L		 6879 i386_operand_type types;
6880
0dfbf9d7 6881 operand_type_set (&types, ~0);
252b5132
RH		 6882
6883 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6884 {
31b2323c
L		 6885 as_bad (_("at most %d immediate operands are allowed"),
6886 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6887 return 0;
6888 }
6889
6890 exp = &im_expressions[i.imm_operands++];
520dc8e8 6891 i.op[this_operand].imms = exp;
252b5132
RH		 6892
6893 if (is_space_char (*imm_start))
6894 ++imm_start;
6895
6896 save_input_line_pointer = input_line_pointer;
6897 input_line_pointer = imm_start;
6898
3956db08 6899 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6900 if (gotfree_input_line)
6901 input_line_pointer = gotfree_input_line;
252b5132
RH		 6902
6903 exp_seg = expression (exp);
6904
83183c0c 6905 SKIP_WHITESPACE ();
252b5132 6906 if (*input_line_pointer)
f3c180ae 6907 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6908
6909 input_line_pointer = save_input_line_pointer;
f3c180ae 6910 if (gotfree_input_line)
ee86248c
JB		 6911 {
6912 free (gotfree_input_line);
6913
6914 if (exp->X_op == O_constant || exp->X_op == O_register)
6915 exp->X_op = O_illegal;
6916 }
6917
6918 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6919}
252b5132 6920
ee86248c
JB		 6921static int
6922i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6923 i386_operand_type types, const char *imm_start)
6924{
6925 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6926 {
313c53d1
L		 6927 if (imm_start)
6928 as_bad (_("missing or invalid immediate expression `%s'"),
6929 imm_start);
3992d3b7 6930 return 0;
252b5132 6931 }
3e73aa7c 6932 else if (exp->X_op == O_constant)
252b5132 6933 {
47926f60 6934 /* Size it properly later. */
40fb9820 6935 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 6936 /* If not 64bit, sign extend val. */
6937 if (flag_code != CODE_64BIT
4eed87de
AM		 6938 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6939 exp->X_add_number
6940 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6941 }
4c63da97 6942#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6943 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6944 && exp_seg != absolute_section
47926f60 6945 && exp_seg != text_section
24eab124
AM		 6946 && exp_seg != data_section
6947 && exp_seg != bss_section
6948 && exp_seg != undefined_section
f86103b7 6949 && !bfd_is_com_section (exp_seg))
252b5132 6950 {
d0b47220 6951 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6952 return 0;
6953 }
6954#endif
bb8f5920
L		 6955 else if (!intel_syntax && exp->X_op == O_register)
6956 {
313c53d1
L		 6957 if (imm_start)
6958 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 6959 return 0;
6960 }
252b5132
RH		 6961 else
6962 {
6963 /* This is an address. The size of the address will be
24eab124 6964 determined later, depending on destination register,
3e73aa7c 6965 suffix, or the default for the section. */
40fb9820
L		 6966 i.types[this_operand].bitfield.imm8 = 1;
6967 i.types[this_operand].bitfield.imm16 = 1;
6968 i.types[this_operand].bitfield.imm32 = 1;
6969 i.types[this_operand].bitfield.imm32s = 1;
6970 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6971 i.types[this_operand] = operand_type_and (i.types[this_operand],
6972 types);
252b5132
RH		 6973 }
6974
6975 return 1;
6976}
6977
551c1ca1 6978static char *
e3bb37b5 6979i386_scale (char *scale)
252b5132 6980{
551c1ca1
AM		 6981 offsetT val;
6982 char *save = input_line_pointer;
252b5132 6983
551c1ca1
AM		 6984 input_line_pointer = scale;
6985 val = get_absolute_expression ();
6986
6987 switch (val)
252b5132 6988 {
551c1ca1 6989 case 1:
252b5132
RH		 6990 i.log2_scale_factor = 0;
6991 break;
551c1ca1 6992 case 2:
252b5132
RH		 6993 i.log2_scale_factor = 1;
6994 break;
551c1ca1 6995 case 4:
252b5132
RH		 6996 i.log2_scale_factor = 2;
6997 break;
551c1ca1 6998 case 8:
252b5132
RH		 6999 i.log2_scale_factor = 3;
7000 break;
7001 default:
a724f0f4
JB		 7002 {
7003 char sep = *input_line_pointer;
7004
7005 *input_line_pointer = '\0';
7006 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7007 scale);
7008 *input_line_pointer = sep;
7009 input_line_pointer = save;
7010 return NULL;
7011 }
252b5132 7012 }
29b0f896 7013 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 7014 {
7015 as_warn (_("scale factor of %d without an index register"),
24eab124 7016 1 << i.log2_scale_factor);
252b5132 7017 i.log2_scale_factor = 0;
252b5132 7018 }
551c1ca1
AM		 7019 scale = input_line_pointer;
7020 input_line_pointer = save;
7021 return scale;
252b5132
RH		 7022}
7023
252b5132 7024static int
e3bb37b5 7025i386_displacement (char *disp_start, char *disp_end)
252b5132 7026{
29b0f896 7027 expressionS *exp;
252b5132
RH		 7028 segT exp_seg = 0;
7029 char *save_input_line_pointer;
f3c180ae 7030 char *gotfree_input_line;
40fb9820
L		 7031 int override;
7032 i386_operand_type bigdisp, types = anydisp;
3992d3b7 7033 int ret;
252b5132 7034
31b2323c
L		 7035 if (i.disp_operands == MAX_MEMORY_OPERANDS)
7036 {
7037 as_bad (_("at most %d displacement operands are allowed"),
7038 MAX_MEMORY_OPERANDS);
7039 return 0;
7040 }
7041
0dfbf9d7 7042 operand_type_set (&bigdisp, 0);
40fb9820
L		 7043 if ((i.types[this_operand].bitfield.jumpabsolute)
7044 || (!current_templates->start->opcode_modifier.jump
7045 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 7046 {
40fb9820 7047 bigdisp.bitfield.disp32 = 1;
e05278af 7048 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 7049 if (flag_code == CODE_64BIT)
7050 {
7051 if (!override)
7052 {
7053 bigdisp.bitfield.disp32s = 1;
7054 bigdisp.bitfield.disp64 = 1;
7055 }
7056 }
7057 else if ((flag_code == CODE_16BIT) ^ override)
7058 {
7059 bigdisp.bitfield.disp32 = 0;
7060 bigdisp.bitfield.disp16 = 1;
7061 }
e05278af
JB		 7062 }
7063 else
7064 {
7065 /* For PC-relative branches, the width of the displacement
7066 is dependent upon data size, not address size. */
e05278af 7067 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 7068 if (flag_code == CODE_64BIT)
7069 {
7070 if (override || i.suffix == WORD_MNEM_SUFFIX)
7071 bigdisp.bitfield.disp16 = 1;
7072 else
7073 {
7074 bigdisp.bitfield.disp32 = 1;
7075 bigdisp.bitfield.disp32s = 1;
7076 }
7077 }
7078 else
e05278af
JB		 7079 {
7080 if (!override)
7081 override = (i.suffix == (flag_code != CODE_16BIT
7082 ? WORD_MNEM_SUFFIX
7083 : LONG_MNEM_SUFFIX));
40fb9820
L		 7084 bigdisp.bitfield.disp32 = 1;
7085 if ((flag_code == CODE_16BIT) ^ override)
7086 {
7087 bigdisp.bitfield.disp32 = 0;
7088 bigdisp.bitfield.disp16 = 1;
7089 }
e05278af 7090 }
e05278af 7091 }
c6fb90c8
L		 7092 i.types[this_operand] = operand_type_or (i.types[this_operand],
7093 bigdisp);
252b5132
RH		 7094
7095 exp = &disp_expressions[i.disp_operands];
520dc8e8 7096 i.op[this_operand].disps = exp;
252b5132
RH		 7097 i.disp_operands++;
7098 save_input_line_pointer = input_line_pointer;
7099 input_line_pointer = disp_start;
7100 END_STRING_AND_SAVE (disp_end);
7101
7102#ifndef GCC_ASM_O_HACK
7103#define GCC_ASM_O_HACK 0
7104#endif
7105#if GCC_ASM_O_HACK
7106 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 7107 if (i.types[this_operand].bitfield.baseIndex
24eab124 7108 && displacement_string_end[-1] == '+')
252b5132
RH		 7109 {
7110 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 7111 constraint within gcc asm statements.
7112 For instance:
7113
7114 #define _set_tssldt_desc(n,addr,limit,type) \
7115 __asm__ __volatile__ ( \
7116 "movw %w2,%0\n\t" \
7117 "movw %w1,2+%0\n\t" \
7118 "rorl $16,%1\n\t" \
7119 "movb %b1,4+%0\n\t" \
7120 "movb %4,5+%0\n\t" \
7121 "movb $0,6+%0\n\t" \
7122 "movb %h1,7+%0\n\t" \
7123 "rorl $16,%1" \
7124 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
7125
7126 This works great except that the output assembler ends
7127 up looking a bit weird if it turns out that there is
7128 no offset. You end up producing code that looks like:
7129
7130 #APP
7131 movw $235,(%eax)
7132 movw %dx,2+(%eax)
7133 rorl $16,%edx
7134 movb %dl,4+(%eax)
7135 movb $137,5+(%eax)
7136 movb $0,6+(%eax)
7137 movb %dh,7+(%eax)
7138 rorl $16,%edx
7139 #NO_APP
7140
47926f60 7141 So here we provide the missing zero. */
24eab124
AM		 7142
7143 *displacement_string_end = '0';
252b5132
RH		 7144 }
7145#endif
3956db08 7146 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7147 if (gotfree_input_line)
7148 input_line_pointer = gotfree_input_line;
252b5132 7149
24eab124 7150 exp_seg = expression (exp);
252b5132 7151
636c26b0
AM		 7152 SKIP_WHITESPACE ();
7153 if (*input_line_pointer)
7154 as_bad (_("junk `%s' after expression"), input_line_pointer);
7155#if GCC_ASM_O_HACK
7156 RESTORE_END_STRING (disp_end + 1);
7157#endif
636c26b0 7158 input_line_pointer = save_input_line_pointer;
636c26b0 7159 if (gotfree_input_line)
ee86248c
JB		 7160 {
7161 free (gotfree_input_line);
7162
7163 if (exp->X_op == O_constant || exp->X_op == O_register)
7164 exp->X_op = O_illegal;
7165 }
7166
7167 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
7168
7169 RESTORE_END_STRING (disp_end);
7170
7171 return ret;
7172}
7173
7174static int
7175i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7176 i386_operand_type types, const char *disp_start)
7177{
7178 i386_operand_type bigdisp;
7179 int ret = 1;
636c26b0 7180
24eab124
AM		 7181 /* We do this to make sure that the section symbol is in
7182 the symbol table. We will ultimately change the relocation
47926f60 7183 to be relative to the beginning of the section. */
1ae12ab7 7184 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 7185 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
7186 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 7187 {
636c26b0 7188 if (exp->X_op != O_symbol)
3992d3b7 7189 goto inv_disp;
636c26b0 7190
e5cb08ac 7191 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 7192 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
7193 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 7194 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 7195 exp->X_op = O_subtract;
7196 exp->X_op_symbol = GOT_symbol;
1ae12ab7 7197 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 7198 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 7199 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
7200 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 7201 else
29b0f896 7202 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 7203 }
252b5132 7204
3992d3b7
AM		 7205 else if (exp->X_op == O_absent
7206 || exp->X_op == O_illegal
ee86248c 7207 || exp->X_op == O_big)
2daf4fd8 7208 {
3992d3b7
AM		 7209 inv_disp:
7210 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 7211 disp_start);
3992d3b7 7212 ret = 0;
2daf4fd8
AM		 7213 }
7214
0e1147d9
L		 7215 else if (flag_code == CODE_64BIT
7216 && !i.prefix[ADDR_PREFIX]
7217 && exp->X_op == O_constant)
7218 {
7219 /* Since displacement is signed extended to 64bit, don't allow
7220 disp32 and turn off disp32s if they are out of range. */
7221 i.types[this_operand].bitfield.disp32 = 0;
7222 if (!fits_in_signed_long (exp->X_add_number))
7223 {
7224 i.types[this_operand].bitfield.disp32s = 0;
7225 if (i.types[this_operand].bitfield.baseindex)
7226 {
7227 as_bad (_("0x%lx out range of signed 32bit displacement"),
7228 (long) exp->X_add_number);
7229 ret = 0;
7230 }
7231 }
7232 }
7233
4c63da97 7234#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 7235 else if (exp->X_op != O_constant
7236 && OUTPUT_FLAVOR == bfd_target_aout_flavour
7237 && exp_seg != absolute_section
7238 && exp_seg != text_section
7239 && exp_seg != data_section
7240 && exp_seg != bss_section
7241 && exp_seg != undefined_section
7242 && !bfd_is_com_section (exp_seg))
24eab124 7243 {
d0b47220 7244 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 7245 ret = 0;
24eab124 7246 }
252b5132 7247#endif
3956db08 7248
40fb9820
L		 7249 /* Check if this is a displacement only operand. */
7250 bigdisp = i.types[this_operand];
7251 bigdisp.bitfield.disp8 = 0;
7252 bigdisp.bitfield.disp16 = 0;
7253 bigdisp.bitfield.disp32 = 0;
7254 bigdisp.bitfield.disp32s = 0;
7255 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 7256 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 7257 i.types[this_operand] = operand_type_and (i.types[this_operand],
7258 types);
3956db08 7259
3992d3b7 7260 return ret;
252b5132
RH		 7261}
7262
eecb386c 7263/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 7264 Return 1 on success, 0 on a failure. */
7265
252b5132 7266static int
e3bb37b5 7267i386_index_check (const char *operand_string)
252b5132 7268{
3e73aa7c 7269 int ok;
fc0763e6 7270 const char *kind = "base/index";
24eab124 7271#if INFER_ADDR_PREFIX
eecb386c
AM		 7272 int fudged = 0;
7273
24eab124
AM		 7274 tryprefix:
7275#endif
3e73aa7c 7276 ok = 1;
fc0763e6
JB		 7277 if (current_templates->start->opcode_modifier.isstring
7278 && !current_templates->start->opcode_modifier.immext
7279 && (current_templates->end[-1].opcode_modifier.isstring
7280 || i.mem_operands))
7281 {
7282 /* Memory operands of string insns are special in that they only allow
7283 a single register (rDI, rSI, or rBX) as their memory address. */
7284 unsigned int expected;
7285
7286 kind = "string address";
7287
7288 if (current_templates->start->opcode_modifier.w)
7289 {
7290 i386_operand_type type = current_templates->end[-1].operand_types[0];
7291
7292 if (!type.bitfield.baseindex
7293 || ((!i.mem_operands != !intel_syntax)
7294 && current_templates->end[-1].operand_types[1]
7295 .bitfield.baseindex))
7296 type = current_templates->end[-1].operand_types[1];
7297 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
7298 }
7299 else
7300 expected = 3 /* rBX */;
7301
7302 if (!i.base_reg || i.index_reg
7303 || operand_type_check (i.types[this_operand], disp))
7304 ok = -1;
7305 else if (!(flag_code == CODE_64BIT
7306 ? i.prefix[ADDR_PREFIX]
7307 ? i.base_reg->reg_type.bitfield.reg32
7308 : i.base_reg->reg_type.bitfield.reg64
7309 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7310 ? i.base_reg->reg_type.bitfield.reg32
7311 : i.base_reg->reg_type.bitfield.reg16))
7312 ok = 0;
7313 else if (i.base_reg->reg_num != expected)
7314 ok = -1;
7315
7316 if (ok < 0)
7317 {
7318 unsigned int j;
7319
7320 for (j = 0; j < i386_regtab_size; ++j)
7321 if ((flag_code == CODE_64BIT
7322 ? i.prefix[ADDR_PREFIX]
7323 ? i386_regtab[j].reg_type.bitfield.reg32
7324 : i386_regtab[j].reg_type.bitfield.reg64
7325 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7326 ? i386_regtab[j].reg_type.bitfield.reg32
7327 : i386_regtab[j].reg_type.bitfield.reg16)
7328 && i386_regtab[j].reg_num == expected)
7329 break;
9c2799c2 7330 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 7331 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7332 operand_string,
7333 intel_syntax ? '[' : '(',
7334 register_prefix,
7335 i386_regtab[j].reg_name,
7336 intel_syntax ? ']' : ')');
7337 ok = 1;
7338 }
7339 }
7340 else if (flag_code == CODE_64BIT)
64e74474 7341 {
64e74474 7342 if ((i.base_reg
40fb9820
L		 7343 && ((i.prefix[ADDR_PREFIX] == 0
7344 && !i.base_reg->reg_type.bitfield.reg64)
7345 || (i.prefix[ADDR_PREFIX]
7346 && !i.base_reg->reg_type.bitfield.reg32))
7347 && (i.index_reg
9a04903e
JB		 7348 || i.base_reg->reg_num !=
7349 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 7350 || (i.index_reg
6c30d220
L		 7351 && !(i.index_reg->reg_type.bitfield.regxmm
7352 || i.index_reg->reg_type.bitfield.regymm)
40fb9820
L		 7353 && (!i.index_reg->reg_type.bitfield.baseindex
7354 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 7355 && i.index_reg->reg_num != RegRiz
7356 && !i.index_reg->reg_type.bitfield.reg64
7357 )
40fb9820 7358 || (i.prefix[ADDR_PREFIX]
db51cc60 7359 && i.index_reg->reg_num != RegEiz
40fb9820 7360 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 7361 ok = 0;
3e73aa7c
JH		 7362 }
7363 else
7364 {
7365 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
7366 {
7367 /* 16bit checks. */
7368 if ((i.base_reg
40fb9820
L		 7369 && (!i.base_reg->reg_type.bitfield.reg16
7370 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 7371 || (i.index_reg
40fb9820
L		 7372 && (!i.index_reg->reg_type.bitfield.reg16
7373 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 7374 || !(i.base_reg
7375 && i.base_reg->reg_num < 6
7376 && i.index_reg->reg_num >= 6
7377 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 7378 ok = 0;
7379 }
7380 else
e5cb08ac 7381 {
3e73aa7c
JH		 7382 /* 32bit checks. */
7383 if ((i.base_reg
40fb9820 7384 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7385 || (i.index_reg
6c30d220
L		 7386 && !i.index_reg->reg_type.bitfield.regxmm
7387 && !i.index_reg->reg_type.bitfield.regymm
db51cc60
L		 7388 && ((!i.index_reg->reg_type.bitfield.reg32
7389 && i.index_reg->reg_num != RegEiz)
40fb9820 7390 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7391 ok = 0;
3e73aa7c
JH		 7392 }
7393 }
7394 if (!ok)
24eab124
AM		 7395 {
7396#if INFER_ADDR_PREFIX
fc0763e6 7397 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7398 {
7399 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7400 i.prefixes += 1;
b23bac36
AM		 7401 /* Change the size of any displacement too. At most one of
7402 Disp16 or Disp32 is set.
7403 FIXME. There doesn't seem to be any real need for separate
7404 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7405 Removing them would probably clean up the code quite a lot. */
4eed87de 7406 if (flag_code != CODE_64BIT
40fb9820
L		 7407 && (i.types[this_operand].bitfield.disp16
7408 || i.types[this_operand].bitfield.disp32))
7409 i.types[this_operand]
c6fb90c8 7410 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7411 fudged = 1;
24eab124
AM		 7412 goto tryprefix;
7413 }
eecb386c 7414 if (fudged)
fc0763e6
JB		 7415 as_bad (_("`%s' is not a valid %s expression"),
7416 operand_string,
7417 kind);
eecb386c 7418 else
c388dee8 7419#endif
fc0763e6 7420 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7421 operand_string,
fc0763e6
JB		 7422 flag_code_names[i.prefix[ADDR_PREFIX]
7423 ? flag_code == CODE_32BIT
7424 ? CODE_16BIT
7425 : CODE_32BIT
7426 : flag_code],
7427 kind);
24eab124 7428 }
20f0a1fc 7429 return ok;
24eab124 7430}
252b5132 7431
fc0763e6 7432/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7433 on error. */
252b5132 7434
252b5132 7435static int
a7619375 7436i386_att_operand (char *operand_string)
252b5132 7437{
af6bdddf
AM		 7438 const reg_entry *r;
7439 char *end_op;
24eab124 7440 char *op_string = operand_string;
252b5132 7441
24eab124 7442 if (is_space_char (*op_string))
252b5132
RH		 7443 ++op_string;
7444
24eab124 7445 /* We check for an absolute prefix (differentiating,
47926f60 7446 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7447 if (*op_string == ABSOLUTE_PREFIX)
7448 {
7449 ++op_string;
7450 if (is_space_char (*op_string))
7451 ++op_string;
40fb9820 7452 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7453 }
252b5132 7454
47926f60 7455 /* Check if operand is a register. */
4d1bb795 7456 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7457 {
40fb9820
L		 7458 i386_operand_type temp;
7459
24eab124
AM		 7460 /* Check for a segment override by searching for ':' after a
7461 segment register. */
7462 op_string = end_op;
7463 if (is_space_char (*op_string))
7464 ++op_string;
40fb9820
L		 7465 if (*op_string == ':'
7466 && (r->reg_type.bitfield.sreg2
7467 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7468 {
7469 switch (r->reg_num)
7470 {
7471 case 0:
7472 i.seg[i.mem_operands] = &es;
7473 break;
7474 case 1:
7475 i.seg[i.mem_operands] = &cs;
7476 break;
7477 case 2:
7478 i.seg[i.mem_operands] = &ss;
7479 break;
7480 case 3:
7481 i.seg[i.mem_operands] = &ds;
7482 break;
7483 case 4:
7484 i.seg[i.mem_operands] = &fs;
7485 break;
7486 case 5:
7487 i.seg[i.mem_operands] = &gs;
7488 break;
7489 }
252b5132 7490
24eab124 7491 /* Skip the ':' and whitespace. */
252b5132
RH		 7492 ++op_string;
7493 if (is_space_char (*op_string))
24eab124 7494 ++op_string;
252b5132 7495
24eab124
AM		 7496 if (!is_digit_char (*op_string)
7497 && !is_identifier_char (*op_string)
7498 && *op_string != '('
7499 && *op_string != ABSOLUTE_PREFIX)
7500 {
7501 as_bad (_("bad memory operand `%s'"), op_string);
7502 return 0;
7503 }
47926f60 7504 /* Handle case of %es:*foo. */
24eab124
AM		 7505 if (*op_string == ABSOLUTE_PREFIX)
7506 {
7507 ++op_string;
7508 if (is_space_char (*op_string))
7509 ++op_string;
40fb9820 7510 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7511 }
7512 goto do_memory_reference;
7513 }
7514 if (*op_string)
7515 {
d0b47220 7516 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7517 return 0;
7518 }
40fb9820
L		 7519 temp = r->reg_type;
7520 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7521 i.types[this_operand] = operand_type_or (i.types[this_operand],
7522 temp);
7d5e4556 7523 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7524 i.op[this_operand].regs = r;
24eab124
AM		 7525 i.reg_operands++;
7526 }
af6bdddf
AM		 7527 else if (*op_string == REGISTER_PREFIX)
7528 {
7529 as_bad (_("bad register name `%s'"), op_string);
7530 return 0;
7531 }
24eab124 7532 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7533 {
24eab124 7534 ++op_string;
40fb9820 7535 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7536 {
d0b47220 7537 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7538 return 0;
7539 }
7540 if (!i386_immediate (op_string))
7541 return 0;
7542 }
7543 else if (is_digit_char (*op_string)
7544 || is_identifier_char (*op_string)
e5cb08ac 7545 || *op_string == '(')
24eab124 7546 {
47926f60 7547 /* This is a memory reference of some sort. */
af6bdddf 7548 char *base_string;
252b5132 7549
47926f60 7550 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7551 char *displacement_string_start;
7552 char *displacement_string_end;
252b5132 7553
24eab124 7554 do_memory_reference:
24eab124 7555 if ((i.mem_operands == 1
40fb9820 7556 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7557 || i.mem_operands == 2)
7558 {
7559 as_bad (_("too many memory references for `%s'"),
7560 current_templates->start->name);
7561 return 0;
7562 }
252b5132 7563
24eab124
AM		 7564 /* Check for base index form. We detect the base index form by
7565 looking for an ')' at the end of the operand, searching
7566 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7567 after the '('. */
af6bdddf 7568 base_string = op_string + strlen (op_string);
c3332e24 7569
af6bdddf
AM		 7570 --base_string;
7571 if (is_space_char (*base_string))
7572 --base_string;
252b5132 7573
47926f60 7574 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7575 displacement_string_start = op_string;
7576 displacement_string_end = base_string + 1;
252b5132 7577
24eab124
AM		 7578 if (*base_string == ')')
7579 {
af6bdddf 7580 char *temp_string;
24eab124
AM		 7581 unsigned int parens_balanced = 1;
7582 /* We've already checked that the number of left & right ()'s are
47926f60 7583 equal, so this loop will not be infinite. */
24eab124
AM		 7584 do
7585 {
7586 base_string--;
7587 if (*base_string == ')')
7588 parens_balanced++;
7589 if (*base_string == '(')
7590 parens_balanced--;
7591 }
7592 while (parens_balanced);
c3332e24 7593
af6bdddf 7594 temp_string = base_string;
c3332e24 7595
24eab124 7596 /* Skip past '(' and whitespace. */
252b5132
RH		 7597 ++base_string;
7598 if (is_space_char (*base_string))
24eab124 7599 ++base_string;
252b5132 7600
af6bdddf 7601 if (*base_string == ','
4eed87de
AM		 7602 || ((i.base_reg = parse_register (base_string, &end_op))
7603 != NULL))
252b5132 7604 {
af6bdddf 7605 displacement_string_end = temp_string;
252b5132 7606
40fb9820 7607 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7608
af6bdddf 7609 if (i.base_reg)
24eab124 7610 {
24eab124
AM		 7611 base_string = end_op;
7612 if (is_space_char (*base_string))
7613 ++base_string;
af6bdddf
AM		 7614 }
7615
7616 /* There may be an index reg or scale factor here. */
7617 if (*base_string == ',')
7618 {
7619 ++base_string;
7620 if (is_space_char (*base_string))
7621 ++base_string;
7622
4eed87de
AM		 7623 if ((i.index_reg = parse_register (base_string, &end_op))
7624 != NULL)
24eab124 7625 {
af6bdddf 7626 base_string = end_op;
24eab124
AM		 7627 if (is_space_char (*base_string))
7628 ++base_string;
af6bdddf
AM		 7629 if (*base_string == ',')
7630 {
7631 ++base_string;
7632 if (is_space_char (*base_string))
7633 ++base_string;
7634 }
e5cb08ac 7635 else if (*base_string != ')')
af6bdddf 7636 {
4eed87de
AM		 7637 as_bad (_("expecting `,' or `)' "
7638 "after index register in `%s'"),
af6bdddf
AM		 7639 operand_string);
7640 return 0;
7641 }
24eab124 7642 }
af6bdddf 7643 else if (*base_string == REGISTER_PREFIX)
24eab124 7644 {
af6bdddf 7645 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7646 return 0;
7647 }
252b5132 7648
47926f60 7649 /* Check for scale factor. */
551c1ca1 7650 if (*base_string != ')')
af6bdddf 7651 {
551c1ca1
AM		 7652 char *end_scale = i386_scale (base_string);
7653
7654 if (!end_scale)
af6bdddf 7655 return 0;
24eab124 7656
551c1ca1 7657 base_string = end_scale;
af6bdddf
AM		 7658 if (is_space_char (*base_string))
7659 ++base_string;
7660 if (*base_string != ')')
7661 {
4eed87de
AM		 7662 as_bad (_("expecting `)' "
7663 "after scale factor in `%s'"),
af6bdddf
AM		 7664 operand_string);
7665 return 0;
7666 }
7667 }
7668 else if (!i.index_reg)
24eab124 7669 {
4eed87de
AM		 7670 as_bad (_("expecting index register or scale factor "
7671 "after `,'; got '%c'"),
af6bdddf 7672 *base_string);
24eab124
AM		 7673 return 0;
7674 }
7675 }
af6bdddf 7676 else if (*base_string != ')')
24eab124 7677 {
4eed87de
AM		 7678 as_bad (_("expecting `,' or `)' "
7679 "after base register in `%s'"),
af6bdddf 7680 operand_string);
24eab124
AM		 7681 return 0;
7682 }
c3332e24 7683 }
af6bdddf 7684 else if (*base_string == REGISTER_PREFIX)
c3332e24 7685 {
af6bdddf 7686 as_bad (_("bad register name `%s'"), base_string);
24eab124 7687 return 0;
c3332e24 7688 }
24eab124
AM		 7689 }
7690
7691 /* If there's an expression beginning the operand, parse it,
7692 assuming displacement_string_start and
7693 displacement_string_end are meaningful. */
7694 if (displacement_string_start != displacement_string_end)
7695 {
7696 if (!i386_displacement (displacement_string_start,
7697 displacement_string_end))
7698 return 0;
7699 }
7700
7701 /* Special case for (%dx) while doing input/output op. */
7702 if (i.base_reg
0dfbf9d7
L		 7703 && operand_type_equal (&i.base_reg->reg_type,
7704 &reg16_inoutportreg)
24eab124
AM		 7705 && i.index_reg == 0
7706 && i.log2_scale_factor == 0
7707 && i.seg[i.mem_operands] == 0
40fb9820 7708 && !operand_type_check (i.types[this_operand], disp))
24eab124 7709 {
65da13b5 7710 i.types[this_operand] = inoutportreg;
24eab124
AM		 7711 return 1;
7712 }
7713
eecb386c
AM		 7714 if (i386_index_check (operand_string) == 0)
7715 return 0;
5c07affc 7716 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7717 i.mem_operands++;
7718 }
7719 else
ce8a8b2f
AM		 7720 {
7721 /* It's not a memory operand; argh! */
24eab124
AM		 7722 as_bad (_("invalid char %s beginning operand %d `%s'"),
7723 output_invalid (*op_string),
7724 this_operand + 1,
7725 op_string);
7726 return 0;
7727 }
47926f60 7728 return 1; /* Normal return. */
252b5132
RH		 7729}
7730\f
fa94de6b
RM		 7731/* Calculate the maximum variable size (i.e., excluding fr_fix)
7732 that an rs_machine_dependent frag may reach. */
7733
7734unsigned int
7735i386_frag_max_var (fragS *frag)
7736{
7737 /* The only relaxable frags are for jumps.
7738 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
7739 gas_assert (frag->fr_type == rs_machine_dependent);
7740 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
7741}
7742
ee7fcc42
AM		 7743/* md_estimate_size_before_relax()
7744
7745 Called just before relax() for rs_machine_dependent frags. The x86
7746 assembler uses these frags to handle variable size jump
7747 instructions.
7748
7749 Any symbol that is now undefined will not become defined.
7750 Return the correct fr_subtype in the frag.
7751 Return the initial "guess for variable size of frag" to caller.
7752 The guess is actually the growth beyond the fixed part. Whatever
7753 we do to grow the fixed or variable part contributes to our
7754 returned value. */
7755
252b5132 7756int
7016a5d5 7757md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 7758{
252b5132 7759 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7760 check for un-relaxable symbols. On an ELF system, we can't relax
7761 an externally visible symbol, because it may be overridden by a
7762 shared library. */
7763 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7764#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7765 || (IS_ELF
31312f95 7766 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7767 || S_IS_WEAK (fragP->fr_symbol)
7768 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7769 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7770#endif
7771#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7772 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7773 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7774#endif
7775 )
252b5132 7776 {
b98ef147
AM		 7777 /* Symbol is undefined in this segment, or we need to keep a
7778 reloc so that weak symbols can be overridden. */
7779 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7780 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7781 unsigned char *opcode;
7782 int old_fr_fix;
f6af82bd 7783
ee7fcc42 7784 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7785 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7786 else if (size == 2)
f6af82bd
AM		 7787 reloc_type = BFD_RELOC_16_PCREL;
7788 else
7789 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7790
ee7fcc42
AM		 7791 old_fr_fix = fragP->fr_fix;
7792 opcode = (unsigned char *) fragP->fr_opcode;
7793
fddf5b5b 7794 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7795 {
fddf5b5b
AM		 7796 case UNCOND_JUMP:
7797 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7798 opcode[0] = 0xe9;
252b5132 7799 fragP->fr_fix += size;
062cd5e7
AS		 7800 fix_new (fragP, old_fr_fix, size,
7801 fragP->fr_symbol,
7802 fragP->fr_offset, 1,
7803 reloc_type);
252b5132
RH		 7804 break;
7805
fddf5b5b 7806 case COND_JUMP86:
412167cb
AM		 7807 if (size == 2
7808 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7809 {
7810 /* Negate the condition, and branch past an
7811 unconditional jump. */
7812 opcode[0] ^= 1;
7813 opcode[1] = 3;
7814 /* Insert an unconditional jump. */
7815 opcode[2] = 0xe9;
7816 /* We added two extra opcode bytes, and have a two byte
7817 offset. */
7818 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7819 fix_new (fragP, old_fr_fix + 2, 2,
7820 fragP->fr_symbol,
7821 fragP->fr_offset, 1,
7822 reloc_type);
fddf5b5b
AM		 7823 break;
7824 }
7825 /* Fall through. */
7826
7827 case COND_JUMP:
412167cb
AM		 7828 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7829 {
3e02c1cc
AM		 7830 fixS *fixP;
7831
412167cb 7832 fragP->fr_fix += 1;
3e02c1cc
AM		 7833 fixP = fix_new (fragP, old_fr_fix, 1,
7834 fragP->fr_symbol,
7835 fragP->fr_offset, 1,
7836 BFD_RELOC_8_PCREL);
7837 fixP->fx_signed = 1;
412167cb
AM		 7838 break;
7839 }
93c2a809 7840
24eab124 7841 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7842 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7843 opcode[1] = opcode[0] + 0x10;
f6af82bd 7844 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7845 /* We've added an opcode byte. */
7846 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7847 fix_new (fragP, old_fr_fix + 1, size,
7848 fragP->fr_symbol,
7849 fragP->fr_offset, 1,
7850 reloc_type);
252b5132 7851 break;
fddf5b5b
AM		 7852
7853 default:
7854 BAD_CASE (fragP->fr_subtype);
7855 break;
252b5132
RH		 7856 }
7857 frag_wane (fragP);
ee7fcc42 7858 return fragP->fr_fix - old_fr_fix;
252b5132 7859 }
93c2a809 7860
93c2a809
AM		 7861 /* Guess size depending on current relax state. Initially the relax
7862 state will correspond to a short jump and we return 1, because
7863 the variable part of the frag (the branch offset) is one byte
7864 long. However, we can relax a section more than once and in that
7865 case we must either set fr_subtype back to the unrelaxed state,
7866 or return the value for the appropriate branch. */
7867 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7868}
7869
47926f60
KH		 7870/* Called after relax() is finished.
7871
7872 In: Address of frag.
7873 fr_type == rs_machine_dependent.
7874 fr_subtype is what the address relaxed to.
7875
7876 Out: Any fixSs and constants are set up.
7877 Caller will turn frag into a ".space 0". */
7878
252b5132 7879void
7016a5d5
TG		 7880md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
7881 fragS *fragP)
252b5132 7882{
29b0f896 7883 unsigned char *opcode;
252b5132 7884 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7885 offsetT target_address;
7886 offsetT opcode_address;
252b5132 7887 unsigned int extension = 0;
847f7ad4 7888 offsetT displacement_from_opcode_start;
252b5132
RH		 7889
7890 opcode = (unsigned char *) fragP->fr_opcode;
7891
47926f60 7892 /* Address we want to reach in file space. */
252b5132 7893 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7894
47926f60 7895 /* Address opcode resides at in file space. */
252b5132
RH		 7896 opcode_address = fragP->fr_address + fragP->fr_fix;
7897
47926f60 7898 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7899 displacement_from_opcode_start = target_address - opcode_address;
7900
fddf5b5b 7901 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7902 {
47926f60
KH		 7903 /* Don't have to change opcode. */
7904 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7905 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7906 }
7907 else
7908 {
7909 if (no_cond_jump_promotion
7910 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7911 as_warn_where (fragP->fr_file, fragP->fr_line,
7912 _("long jump required"));
252b5132 7913
fddf5b5b
AM		 7914 switch (fragP->fr_subtype)
7915 {
7916 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7917 extension = 4; /* 1 opcode + 4 displacement */
7918 opcode[0] = 0xe9;
7919 where_to_put_displacement = &opcode[1];
7920 break;
252b5132 7921
fddf5b5b
AM		 7922 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7923 extension = 2; /* 1 opcode + 2 displacement */
7924 opcode[0] = 0xe9;
7925 where_to_put_displacement = &opcode[1];
7926 break;
252b5132 7927
fddf5b5b
AM		 7928 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7929 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7930 extension = 5; /* 2 opcode + 4 displacement */
7931 opcode[1] = opcode[0] + 0x10;
7932 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7933 where_to_put_displacement = &opcode[2];
7934 break;
252b5132 7935
fddf5b5b
AM		 7936 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7937 extension = 3; /* 2 opcode + 2 displacement */
7938 opcode[1] = opcode[0] + 0x10;
7939 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7940 where_to_put_displacement = &opcode[2];
7941 break;
252b5132 7942
fddf5b5b
AM		 7943 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7944 extension = 4;
7945 opcode[0] ^= 1;
7946 opcode[1] = 3;
7947 opcode[2] = 0xe9;
7948 where_to_put_displacement = &opcode[3];
7949 break;
7950
7951 default:
7952 BAD_CASE (fragP->fr_subtype);
7953 break;
7954 }
252b5132 7955 }
fddf5b5b 7956
7b81dfbb
AJ		 7957 /* If size if less then four we are sure that the operand fits,
7958 but if it's 4, then it could be that the displacement is larger
7959 then -/+ 2GB. */
7960 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7961 && object_64bit
7962 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7963 + ((addressT) 1 << 31))
7964 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7965 {
7966 as_bad_where (fragP->fr_file, fragP->fr_line,
7967 _("jump target out of range"));
7968 /* Make us emit 0. */
7969 displacement_from_opcode_start = extension;
7970 }
47926f60 7971 /* Now put displacement after opcode. */
252b5132
RH		 7972 md_number_to_chars ((char *) where_to_put_displacement,
7973 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7974 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7975 fragP->fr_fix += extension;
7976}
7977\f
7016a5d5 7978/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 7979 by our caller that we have all the info we need to fix it up.
7980
7016a5d5
TG		 7981 Parameter valP is the pointer to the value of the bits.
7982
252b5132
RH		 7983 On the 386, immediates, displacements, and data pointers are all in
7984 the same (little-endian) format, so we don't need to care about which
7985 we are handling. */
7986
94f592af 7987void
7016a5d5 7988md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 7989{
94f592af 7990 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7991 valueT value = *valP;
252b5132 7992
f86103b7 7993#if !defined (TE_Mach)
93382f6d
AM		 7994 if (fixP->fx_pcrel)
7995 {
7996 switch (fixP->fx_r_type)
7997 {
5865bb77
ILT		 7998 default:
7999 break;
8000
d6ab8113
JB		 8001 case BFD_RELOC_64:
8002 fixP->fx_r_type = BFD_RELOC_64_PCREL;
8003 break;
93382f6d 8004 case BFD_RELOC_32:
ae8887b5 8005 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 8006 fixP->fx_r_type = BFD_RELOC_32_PCREL;
8007 break;
8008 case BFD_RELOC_16:
8009 fixP->fx_r_type = BFD_RELOC_16_PCREL;
8010 break;
8011 case BFD_RELOC_8:
8012 fixP->fx_r_type = BFD_RELOC_8_PCREL;
8013 break;
8014 }
8015 }
252b5132 8016
a161fe53 8017 if (fixP->fx_addsy != NULL
31312f95 8018 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 8019 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 8020 || fixP->fx_r_type == BFD_RELOC_16_PCREL
8021 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
8022 && !use_rela_relocations)
252b5132 8023 {
31312f95
AM		 8024 /* This is a hack. There should be a better way to handle this.
8025 This covers for the fact that bfd_install_relocation will
8026 subtract the current location (for partial_inplace, PC relative
8027 relocations); see more below. */
252b5132 8028#ifndef OBJ_AOUT
718ddfc0 8029 if (IS_ELF
252b5132
RH		 8030#ifdef TE_PE
8031 || OUTPUT_FLAVOR == bfd_target_coff_flavour
8032#endif
8033 )
8034 value += fixP->fx_where + fixP->fx_frag->fr_address;
8035#endif
8036#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8037 if (IS_ELF)
252b5132 8038 {
6539b54b 8039 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 8040
6539b54b 8041 if ((sym_seg == seg
2f66722d 8042 || (symbol_section_p (fixP->fx_addsy)
6539b54b 8043 && sym_seg != absolute_section))
af65af87 8044 && !generic_force_reloc (fixP))
2f66722d
AM		 8045 {
8046 /* Yes, we add the values in twice. This is because
6539b54b
AM		 8047 bfd_install_relocation subtracts them out again. I think
8048 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 8049 it. FIXME. */
8050 value += fixP->fx_where + fixP->fx_frag->fr_address;
8051 }
252b5132
RH		 8052 }
8053#endif
8054#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 8055 /* For some reason, the PE format does not store a
8056 section address offset for a PC relative symbol. */
8057 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 8058 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 8059 value += md_pcrel_from (fixP);
8060#endif
8061 }
fbeb56a4
DK		 8062#if defined (OBJ_COFF) && defined (TE_PE)
8063 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
8064 {
8065 value -= S_GET_VALUE (fixP->fx_addsy);
8066 }
8067#endif
252b5132
RH		 8068
8069 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 8070 and we must not disappoint it. */
252b5132 8071#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8072 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 8073 switch (fixP->fx_r_type)
8074 {
8075 case BFD_RELOC_386_PLT32:
3e73aa7c 8076 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 8077 /* Make the jump instruction point to the address of the operand. At
8078 runtime we merely add the offset to the actual PLT entry. */
8079 value = -4;
8080 break;
31312f95 8081
13ae64f3
JJ		 8082 case BFD_RELOC_386_TLS_GD:
8083 case BFD_RELOC_386_TLS_LDM:
13ae64f3 8084 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8085 case BFD_RELOC_386_TLS_IE:
8086 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 8087 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 8088 case BFD_RELOC_X86_64_TLSGD:
8089 case BFD_RELOC_X86_64_TLSLD:
8090 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 8091 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 8092 value = 0; /* Fully resolved at runtime. No addend. */
8093 /* Fallthrough */
8094 case BFD_RELOC_386_TLS_LE:
8095 case BFD_RELOC_386_TLS_LDO_32:
8096 case BFD_RELOC_386_TLS_LE_32:
8097 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8098 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 8099 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 8100 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 8101 S_SET_THREAD_LOCAL (fixP->fx_addsy);
8102 break;
8103
67a4f2b7
AO		 8104 case BFD_RELOC_386_TLS_DESC_CALL:
8105 case BFD_RELOC_X86_64_TLSDESC_CALL:
8106 value = 0; /* Fully resolved at runtime. No addend. */
8107 S_SET_THREAD_LOCAL (fixP->fx_addsy);
8108 fixP->fx_done = 0;
8109 return;
8110
00f7efb6
JJ		 8111 case BFD_RELOC_386_GOT32:
8112 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 8113 value = 0; /* Fully resolved at runtime. No addend. */
8114 break;
47926f60
KH		 8115
8116 case BFD_RELOC_VTABLE_INHERIT:
8117 case BFD_RELOC_VTABLE_ENTRY:
8118 fixP->fx_done = 0;
94f592af 8119 return;
47926f60
KH		 8120
8121 default:
8122 break;
8123 }
8124#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 8125 *valP = value;
f86103b7 8126#endif /* !defined (TE_Mach) */
3e73aa7c 8127
3e73aa7c 8128 /* Are we finished with this relocation now? */
c6682705 8129 if (fixP->fx_addsy == NULL)
3e73aa7c 8130 fixP->fx_done = 1;
fbeb56a4
DK		 8131#if defined (OBJ_COFF) && defined (TE_PE)
8132 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
8133 {
8134 fixP->fx_done = 0;
8135 /* Remember value for tc_gen_reloc. */
8136 fixP->fx_addnumber = value;
8137 /* Clear out the frag for now. */
8138 value = 0;
8139 }
8140#endif
3e73aa7c
JH		 8141 else if (use_rela_relocations)
8142 {
8143 fixP->fx_no_overflow = 1;
062cd5e7
AS		 8144 /* Remember value for tc_gen_reloc. */
8145 fixP->fx_addnumber = value;
3e73aa7c
JH		 8146 value = 0;
8147 }
f86103b7 8148
94f592af 8149 md_number_to_chars (p, value, fixP->fx_size);
252b5132 8150}
252b5132 8151\f
252b5132 8152char *
499ac353 8153md_atof (int type, char *litP, int *sizeP)
252b5132 8154{
499ac353
NC		 8155 /* This outputs the LITTLENUMs in REVERSE order;
8156 in accord with the bigendian 386. */
8157 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 8158}
8159\f
2d545b82 8160static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 8161
252b5132 8162static char *
e3bb37b5 8163output_invalid (int c)
252b5132 8164{
3882b010 8165 if (ISPRINT (c))
f9f21a03
L		 8166 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
8167 "'%c'", c);
252b5132 8168 else
f9f21a03 8169 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 8170 "(0x%x)", (unsigned char) c);
252b5132
RH		 8171 return output_invalid_buf;
8172}
8173
af6bdddf 8174/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 8175
8176static const reg_entry *
4d1bb795 8177parse_real_register (char *reg_string, char **end_op)
252b5132 8178{
af6bdddf
AM		 8179 char *s = reg_string;
8180 char *p;
252b5132
RH		 8181 char reg_name_given[MAX_REG_NAME_SIZE + 1];
8182 const reg_entry *r;
8183
8184 /* Skip possible REGISTER_PREFIX and possible whitespace. */
8185 if (*s == REGISTER_PREFIX)
8186 ++s;
8187
8188 if (is_space_char (*s))
8189 ++s;
8190
8191 p = reg_name_given;
af6bdddf 8192 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 8193 {
8194 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 8195 return (const reg_entry *) NULL;
8196 s++;
252b5132
RH		 8197 }
8198
6588847e
DN		 8199 /* For naked regs, make sure that we are not dealing with an identifier.
8200 This prevents confusing an identifier like `eax_var' with register
8201 `eax'. */
8202 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
8203 return (const reg_entry *) NULL;
8204
af6bdddf 8205 *end_op = s;
252b5132
RH		 8206
8207 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
8208
5f47d35b 8209 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 8210 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 8211 {
5f47d35b
AM		 8212 if (is_space_char (*s))
8213 ++s;
8214 if (*s == '(')
8215 {
af6bdddf 8216 ++s;
5f47d35b
AM		 8217 if (is_space_char (*s))
8218 ++s;
8219 if (*s >= '0' && *s <= '7')
8220 {
db557034 8221 int fpr = *s - '0';
af6bdddf 8222 ++s;
5f47d35b
AM		 8223 if (is_space_char (*s))
8224 ++s;
8225 if (*s == ')')
8226 {
8227 *end_op = s + 1;
1e9cc1c2 8228 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 8229 know (r);
8230 return r + fpr;
5f47d35b 8231 }
5f47d35b 8232 }
47926f60 8233 /* We have "%st(" then garbage. */
5f47d35b
AM		 8234 return (const reg_entry *) NULL;
8235 }
8236 }
8237
a60de03c
JB		 8238 if (r == NULL || allow_pseudo_reg)
8239 return r;
8240
0dfbf9d7 8241 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 8242 return (const reg_entry *) NULL;
8243
192dc9c6
JB		 8244 if ((r->reg_type.bitfield.reg32
8245 || r->reg_type.bitfield.sreg3
8246 || r->reg_type.bitfield.control
8247 || r->reg_type.bitfield.debug
8248 || r->reg_type.bitfield.test)
8249 && !cpu_arch_flags.bitfield.cpui386)
8250 return (const reg_entry *) NULL;
8251
309d3373
JB		 8252 if (r->reg_type.bitfield.floatreg
8253 && !cpu_arch_flags.bitfield.cpu8087
8254 && !cpu_arch_flags.bitfield.cpu287
8255 && !cpu_arch_flags.bitfield.cpu387)
8256 return (const reg_entry *) NULL;
8257
192dc9c6
JB		 8258 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
8259 return (const reg_entry *) NULL;
8260
8261 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
8262 return (const reg_entry *) NULL;
8263
40f12533
L		 8264 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
8265 return (const reg_entry *) NULL;
8266
db51cc60 8267 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 8268 if (!allow_index_reg
db51cc60
L		 8269 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
8270 return (const reg_entry *) NULL;
8271
a60de03c
JB		 8272 if (((r->reg_flags & (RegRex64 | RegRex))
8273 || r->reg_type.bitfield.reg64)
40fb9820 8274 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 8275 || !operand_type_equal (&r->reg_type, &control))
1ae00879 8276 && flag_code != CODE_64BIT)
20f0a1fc 8277 return (const reg_entry *) NULL;
1ae00879 8278
b7240065
JB		 8279 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
8280 return (const reg_entry *) NULL;
8281
252b5132
RH		 8282 return r;
8283}
4d1bb795
JB		 8284
8285/* REG_STRING starts *before* REGISTER_PREFIX. */
8286
8287static const reg_entry *
8288parse_register (char *reg_string, char **end_op)
8289{
8290 const reg_entry *r;
8291
8292 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
8293 r = parse_real_register (reg_string, end_op);
8294 else
8295 r = NULL;
8296 if (!r)
8297 {
8298 char *save = input_line_pointer;
8299 char c;
8300 symbolS *symbolP;
8301
8302 input_line_pointer = reg_string;
8303 c = get_symbol_end ();
8304 symbolP = symbol_find (reg_string);
8305 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
8306 {
8307 const expressionS *e = symbol_get_value_expression (symbolP);
8308
0398aac5 8309 know (e->X_op == O_register);
4eed87de 8310 know (e->X_add_number >= 0
c3fe08fa 8311 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 8312 r = i386_regtab + e->X_add_number;
8313 *end_op = input_line_pointer;
8314 }
8315 *input_line_pointer = c;
8316 input_line_pointer = save;
8317 }
8318 return r;
8319}
8320
8321int
8322i386_parse_name (char *name, expressionS *e, char *nextcharP)
8323{
8324 const reg_entry *r;
8325 char *end = input_line_pointer;
8326
8327 *end = *nextcharP;
8328 r = parse_register (name, &input_line_pointer);
8329 if (r && end <= input_line_pointer)
8330 {
8331 *nextcharP = *input_line_pointer;
8332 *input_line_pointer = 0;
8333 e->X_op = O_register;
8334 e->X_add_number = r - i386_regtab;
8335 return 1;
8336 }
8337 input_line_pointer = end;
8338 *end = 0;
ee86248c 8339 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 8340}
8341
8342void
8343md_operand (expressionS *e)
8344{
ee86248c
JB		 8345 char *end;
8346 const reg_entry *r;
4d1bb795 8347
ee86248c
JB		 8348 switch (*input_line_pointer)
8349 {
8350 case REGISTER_PREFIX:
8351 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 8352 if (r)
8353 {
8354 e->X_op = O_register;
8355 e->X_add_number = r - i386_regtab;
8356 input_line_pointer = end;
8357 }
ee86248c
JB		 8358 break;
8359
8360 case '[':
9c2799c2 8361 gas_assert (intel_syntax);
ee86248c
JB		 8362 end = input_line_pointer++;
8363 expression (e);
8364 if (*input_line_pointer == ']')
8365 {
8366 ++input_line_pointer;
8367 e->X_op_symbol = make_expr_symbol (e);
8368 e->X_add_symbol = NULL;
8369 e->X_add_number = 0;
8370 e->X_op = O_index;
8371 }
8372 else
8373 {
8374 e->X_op = O_absent;
8375 input_line_pointer = end;
8376 }
8377 break;
4d1bb795
JB		 8378 }
8379}
8380
252b5132 8381\f
4cc782b5 8382#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 8383const char *md_shortopts = "kVQ:sqn";
252b5132 8384#else
12b55ccc 8385const char *md_shortopts = "qn";
252b5132 8386#endif
6e0b89ee 8387
3e73aa7c 8388#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 8389#define OPTION_64 (OPTION_MD_BASE + 1)
8390#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 8391#define OPTION_MARCH (OPTION_MD_BASE + 3)
8392#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 8393#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8394#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8395#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8396#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8397#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 8398#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 8399#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
40a9833c 8400#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
570561f7 8401#define OPTION_X32 (OPTION_MD_BASE + 13)
b3b91714 8402
99ad8390
NC		 8403struct option md_longopts[] =
8404{
3e73aa7c 8405 {"32", no_argument, NULL, OPTION_32},
321098a5 8406#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 8407 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 8408 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 8409#endif
8410#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 8411 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 8412#endif
b3b91714 8413 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 8414 {"march", required_argument, NULL, OPTION_MARCH},
8415 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 8416 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
8417 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
8418 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
8419 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
8420 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 8421 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 8422 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
539f890d 8423 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
252b5132
RH		 8424 {NULL, no_argument, NULL, 0}
8425};
8426size_t md_longopts_size = sizeof (md_longopts);
8427
8428int
9103f4f4 8429md_parse_option (int c, char *arg)
252b5132 8430{
91d6fa6a 8431 unsigned int j;
6305a203 8432 char *arch, *next;
9103f4f4 8433
252b5132
RH		 8434 switch (c)
8435 {
12b55ccc
L		 8436 case 'n':
8437 optimize_align_code = 0;
8438 break;
8439
a38cf1db
AM		 8440 case 'q':
8441 quiet_warnings = 1;
252b5132
RH		 8442 break;
8443
8444#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8445 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8446 should be emitted or not. FIXME: Not implemented. */
8447 case 'Q':
252b5132
RH		 8448 break;
8449
8450 /* -V: SVR4 argument to print version ID. */
8451 case 'V':
8452 print_version_id ();
8453 break;
8454
a38cf1db
AM		 8455 /* -k: Ignore for FreeBSD compatibility. */
8456 case 'k':
252b5132 8457 break;
4cc782b5
ILT		 8458
8459 case 's':
8460 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8461 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8462 break;
99ad8390 8463#endif
321098a5 8464#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 8465 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 8466 case OPTION_64:
8467 {
8468 const char **list, **l;
8469
3e73aa7c
JH		 8470 list = bfd_target_list ();
8471 for (l = list; *l != NULL; l++)
8620418b 8472 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8473 || strcmp (*l, "coff-x86-64") == 0
8474 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 8475 || strcmp (*l, "pei-x86-64") == 0
8476 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 8477 {
8478 default_arch = "x86_64";
8479 break;
8480 }
3e73aa7c 8481 if (*l == NULL)
2b5d6a91 8482 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 8483 free (list);
8484 }
8485 break;
8486#endif
252b5132 8487
351f65ca 8488#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 8489 case OPTION_X32:
351f65ca
L		 8490 if (IS_ELF)
8491 {
8492 const char **list, **l;
8493
8494 list = bfd_target_list ();
8495 for (l = list; *l != NULL; l++)
8496 if (CONST_STRNEQ (*l, "elf32-x86-64"))
8497 {
8498 default_arch = "x86_64:32";
8499 break;
8500 }
8501 if (*l == NULL)
2b5d6a91 8502 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 8503 free (list);
8504 }
8505 else
8506 as_fatal (_("32bit x86_64 is only supported for ELF"));
8507 break;
8508#endif
8509
6e0b89ee
AM		 8510 case OPTION_32:
8511 default_arch = "i386";
8512 break;
8513
b3b91714
AM		 8514 case OPTION_DIVIDE:
8515#ifdef SVR4_COMMENT_CHARS
8516 {
8517 char *n, *t;
8518 const char *s;
8519
8520 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8521 t = n;
8522 for (s = i386_comment_chars; *s != '\0'; s++)
8523 if (*s != '/')
8524 *t++ = *s;
8525 *t = '\0';
8526 i386_comment_chars = n;
8527 }
8528#endif
8529 break;
8530
9103f4f4 8531 case OPTION_MARCH:
6305a203
L		 8532 arch = xstrdup (arg);
8533 do
9103f4f4 8534 {
6305a203 8535 if (*arch == '.')
2b5d6a91 8536 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 8537 next = strchr (arch, '+');
8538 if (next)
8539 *next++ = '\0';
91d6fa6a 8540 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8541 {
91d6fa6a 8542 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 8543 {
6305a203 8544 /* Processor. */
1ded5609
JB		 8545 if (! cpu_arch[j].flags.bitfield.cpui386)
8546 continue;
8547
91d6fa6a 8548 cpu_arch_name = cpu_arch[j].name;
6305a203 8549 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 8550 cpu_arch_flags = cpu_arch[j].flags;
8551 cpu_arch_isa = cpu_arch[j].type;
8552 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 8553 if (!cpu_arch_tune_set)
8554 {
8555 cpu_arch_tune = cpu_arch_isa;
8556 cpu_arch_tune_flags = cpu_arch_isa_flags;
8557 }
8558 break;
8559 }
91d6fa6a
NC		 8560 else if (*cpu_arch [j].name == '.'
8561 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 8562 {
8563 /* ISA entension. */
8564 i386_cpu_flags flags;
309d3373 8565
49021df2 8566 if (!cpu_arch[j].negated)
309d3373 8567 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 8568 cpu_arch[j].flags);
309d3373
JB		 8569 else
8570 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 8571 cpu_arch[j].flags);
0dfbf9d7 8572 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8573 {
8574 if (cpu_sub_arch_name)
8575 {
8576 char *name = cpu_sub_arch_name;
8577 cpu_sub_arch_name = concat (name,
91d6fa6a 8578 cpu_arch[j].name,
1bf57e9f 8579 (const char *) NULL);
6305a203
L		 8580 free (name);
8581 }
8582 else
91d6fa6a 8583 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 8584 cpu_arch_flags = flags;
a586129e 8585 cpu_arch_isa_flags = flags;
6305a203
L		 8586 }
8587 break;
ccc9c027 8588 }
9103f4f4 8589 }
6305a203 8590
91d6fa6a 8591 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 8592 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 8593
8594 arch = next;
9103f4f4 8595 }
6305a203 8596 while (next != NULL );
9103f4f4
L		 8597 break;
8598
8599 case OPTION_MTUNE:
8600 if (*arg == '.')
2b5d6a91 8601 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 8602 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8603 {
91d6fa6a 8604 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8605 {
ccc9c027 8606 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8607 cpu_arch_tune = cpu_arch [j].type;
8608 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8609 break;
8610 }
8611 }
91d6fa6a 8612 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 8613 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 8614 break;
8615
1efbbeb4
L		 8616 case OPTION_MMNEMONIC:
8617 if (strcasecmp (arg, "att") == 0)
8618 intel_mnemonic = 0;
8619 else if (strcasecmp (arg, "intel") == 0)
8620 intel_mnemonic = 1;
8621 else
2b5d6a91 8622 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 8623 break;
8624
8625 case OPTION_MSYNTAX:
8626 if (strcasecmp (arg, "att") == 0)
8627 intel_syntax = 0;
8628 else if (strcasecmp (arg, "intel") == 0)
8629 intel_syntax = 1;
8630 else
2b5d6a91 8631 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 8632 break;
8633
8634 case OPTION_MINDEX_REG:
8635 allow_index_reg = 1;
8636 break;
8637
8638 case OPTION_MNAKED_REG:
8639 allow_naked_reg = 1;
8640 break;
8641
8642 case OPTION_MOLD_GCC:
8643 old_gcc = 1;
1efbbeb4
L		 8644 break;
8645
c0f3af97
L		 8646 case OPTION_MSSE2AVX:
8647 sse2avx = 1;
8648 break;
8649
daf50ae7
L		 8650 case OPTION_MSSE_CHECK:
8651 if (strcasecmp (arg, "error") == 0)
8652 sse_check = sse_check_error;
8653 else if (strcasecmp (arg, "warning") == 0)
8654 sse_check = sse_check_warning;
8655 else if (strcasecmp (arg, "none") == 0)
8656 sse_check = sse_check_none;
8657 else
2b5d6a91 8658 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 8659 break;
8660
539f890d
L		 8661 case OPTION_MAVXSCALAR:
8662 if (strcasecmp (arg, "128") == 0)
8663 avxscalar = vex128;
8664 else if (strcasecmp (arg, "256") == 0)
8665 avxscalar = vex256;
8666 else
2b5d6a91 8667 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 8668 break;
8669
252b5132
RH		 8670 default:
8671 return 0;
8672 }
8673 return 1;
8674}
8675
8a2c8fef
L		 8676#define MESSAGE_TEMPLATE \
8677" "
8678
8679static void
1ded5609 8680show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 8681{
8682 static char message[] = MESSAGE_TEMPLATE;
8683 char *start = message + 27;
8684 char *p;
8685 int size = sizeof (MESSAGE_TEMPLATE);
8686 int left;
8687 const char *name;
8688 int len;
8689 unsigned int j;
8690
8691 p = start;
8692 left = size - (start - message);
8693 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8694 {
8695 /* Should it be skipped? */
8696 if (cpu_arch [j].skip)
8697 continue;
8698
8699 name = cpu_arch [j].name;
8700 len = cpu_arch [j].len;
8701 if (*name == '.')
8702 {
8703 /* It is an extension. Skip if we aren't asked to show it. */
8704 if (ext)
8705 {
8706 name++;
8707 len--;
8708 }
8709 else
8710 continue;
8711 }
8712 else if (ext)
8713 {
8714 /* It is an processor. Skip if we show only extension. */
8715 continue;
8716 }
1ded5609
JB		 8717 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
8718 {
8719 /* It is an impossible processor - skip. */
8720 continue;
8721 }
8a2c8fef
L		 8722
8723 /* Reserve 2 spaces for ", " or ",\0" */
8724 left -= len + 2;
8725
8726 /* Check if there is any room. */
8727 if (left >= 0)
8728 {
8729 if (p != start)
8730 {
8731 *p++ = ',';
8732 *p++ = ' ';
8733 }
8734 p = mempcpy (p, name, len);
8735 }
8736 else
8737 {
8738 /* Output the current message now and start a new one. */
8739 *p++ = ',';
8740 *p = '\0';
8741 fprintf (stream, "%s\n", message);
8742 p = start;
8743 left = size - (start - message) - len - 2;
8d63c93e 8744
8a2c8fef
L		 8745 gas_assert (left >= 0);
8746
8747 p = mempcpy (p, name, len);
8748 }
8749 }
8750
8751 *p = '\0';
8752 fprintf (stream, "%s\n", message);
8753}
8754
252b5132 8755void
8a2c8fef 8756md_show_usage (FILE *stream)
252b5132 8757{
4cc782b5
ILT		 8758#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8759 fprintf (stream, _("\
a38cf1db
AM		 8760 -Q ignored\n\
8761 -V print assembler version number\n\
b3b91714
AM		 8762 -k ignored\n"));
8763#endif
8764 fprintf (stream, _("\
12b55ccc 8765 -n Do not optimize code alignment\n\
b3b91714
AM		 8766 -q quieten some warnings\n"));
8767#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8768 fprintf (stream, _("\
a38cf1db 8769 -s ignored\n"));
b3b91714 8770#endif
321098a5
L		 8771#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8772 || defined (TE_PE) || defined (TE_PEP))
751d281c 8773 fprintf (stream, _("\
570561f7 8774 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 8775#endif
b3b91714
AM		 8776#ifdef SVR4_COMMENT_CHARS
8777 fprintf (stream, _("\
8778 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8779#else
8780 fprintf (stream, _("\
b3b91714 8781 --divide ignored\n"));
4cc782b5 8782#endif
9103f4f4 8783 fprintf (stream, _("\
6305a203 8784 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 8785 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 8786 show_arch (stream, 0, 1);
8a2c8fef
L		 8787 fprintf (stream, _("\
8788 EXTENSION is combination of:\n"));
1ded5609 8789 show_arch (stream, 1, 0);
6305a203 8790 fprintf (stream, _("\
8a2c8fef 8791 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 8792 show_arch (stream, 0, 0);
ba104c83 8793 fprintf (stream, _("\
c0f3af97
L		 8794 -msse2avx encode SSE instructions with VEX prefix\n"));
8795 fprintf (stream, _("\
daf50ae7
L		 8796 -msse-check=[none|error|warning]\n\
8797 check SSE instructions\n"));
8798 fprintf (stream, _("\
539f890d
L		 8799 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8800 length\n"));
8801 fprintf (stream, _("\
ba104c83
L		 8802 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8803 fprintf (stream, _("\
8804 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8805 fprintf (stream, _("\
8806 -mindex-reg support pseudo index registers\n"));
8807 fprintf (stream, _("\
8808 -mnaked-reg don't require `%%' prefix for registers\n"));
8809 fprintf (stream, _("\
8810 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8811}
8812
3e73aa7c 8813#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8814 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8815 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8816
8817/* Pick the target format to use. */
8818
47926f60 8819const char *
e3bb37b5 8820i386_target_format (void)
252b5132 8821{
351f65ca
L		 8822 if (!strncmp (default_arch, "x86_64", 6))
8823 {
8824 update_code_flag (CODE_64BIT, 1);
8825 if (default_arch[6] == '\0')
7f56bc95 8826 x86_elf_abi = X86_64_ABI;
351f65ca 8827 else
7f56bc95 8828 x86_elf_abi = X86_64_X32_ABI;
351f65ca 8829 }
3e73aa7c 8830 else if (!strcmp (default_arch, "i386"))
78f12dd3 8831 update_code_flag (CODE_32BIT, 1);
3e73aa7c 8832 else
2b5d6a91 8833 as_fatal (_("unknown architecture"));
89507696
JB		 8834
8835 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
8836 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8837 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
8838 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8839
252b5132
RH		 8840 switch (OUTPUT_FLAVOR)
8841 {
9384f2ff 8842#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8843 case bfd_target_aout_flavour:
47926f60 8844 return AOUT_TARGET_FORMAT;
4c63da97 8845#endif
9384f2ff
AM		 8846#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8847# if defined (TE_PE) || defined (TE_PEP)
8848 case bfd_target_coff_flavour:
8849 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8850# elif defined (TE_GO32)
0561d57c
JK		 8851 case bfd_target_coff_flavour:
8852 return "coff-go32";
9384f2ff 8853# else
252b5132
RH		 8854 case bfd_target_coff_flavour:
8855 return "coff-i386";
9384f2ff 8856# endif
4c63da97 8857#endif
3e73aa7c 8858#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8859 case bfd_target_elf_flavour:
3e73aa7c 8860 {
351f65ca
L		 8861 const char *format;
8862
8863 switch (x86_elf_abi)
4fa24527 8864 {
351f65ca
L		 8865 default:
8866 format = ELF_TARGET_FORMAT;
8867 break;
7f56bc95 8868 case X86_64_ABI:
351f65ca 8869 use_rela_relocations = 1;
4fa24527 8870 object_64bit = 1;
351f65ca
L		 8871 format = ELF_TARGET_FORMAT64;
8872 break;
7f56bc95 8873 case X86_64_X32_ABI:
4fa24527 8874 use_rela_relocations = 1;
351f65ca 8875 object_64bit = 1;
862be3fb 8876 disallow_64bit_reloc = 1;
351f65ca
L		 8877 format = ELF_TARGET_FORMAT32;
8878 break;
4fa24527 8879 }
3632d14b 8880 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 8881 {
7f56bc95 8882 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 8883 as_fatal (_("Intel L1OM is 64bit only"));
8884 return ELF_TARGET_L1OM_FORMAT;
8885 }
7a9068fe
L		 8886 if (cpu_arch_isa == PROCESSOR_K1OM)
8887 {
8888 if (x86_elf_abi != X86_64_ABI)
8889 as_fatal (_("Intel K1OM is 64bit only"));
8890 return ELF_TARGET_K1OM_FORMAT;
8891 }
8a9036a4 8892 else
351f65ca 8893 return format;
3e73aa7c 8894 }
e57f8c65
TG		 8895#endif
8896#if defined (OBJ_MACH_O)
8897 case bfd_target_mach_o_flavour:
d382c579
TG		 8898 if (flag_code == CODE_64BIT)
8899 {
8900 use_rela_relocations = 1;
8901 object_64bit = 1;
8902 return "mach-o-x86-64";
8903 }
8904 else
8905 return "mach-o-i386";
4c63da97 8906#endif
252b5132
RH		 8907 default:
8908 abort ();
8909 return NULL;
8910 }
8911}
8912
47926f60 8913#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8914
8915#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8916void
8917i386_elf_emit_arch_note (void)
a847613f 8918{
718ddfc0 8919 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8920 {
8921 char *p;
8922 asection *seg = now_seg;
8923 subsegT subseg = now_subseg;
8924 Elf_Internal_Note i_note;
8925 Elf_External_Note e_note;
8926 asection *note_secp;
8927 int len;
8928
8929 /* Create the .note section. */
8930 note_secp = subseg_new (".note", 0);
8931 bfd_set_section_flags (stdoutput,
8932 note_secp,
8933 SEC_HAS_CONTENTS | SEC_READONLY);
8934
8935 /* Process the arch string. */
8936 len = strlen (cpu_arch_name);
8937
8938 i_note.namesz = len + 1;
8939 i_note.descsz = 0;
8940 i_note.type = NT_ARCH;
8941 p = frag_more (sizeof (e_note.namesz));
8942 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8943 p = frag_more (sizeof (e_note.descsz));
8944 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8945 p = frag_more (sizeof (e_note.type));
8946 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8947 p = frag_more (len + 1);
8948 strcpy (p, cpu_arch_name);
8949
8950 frag_align (2, 0, 0);
8951
8952 subseg_set (seg, subseg);
8953 }
8954}
8955#endif
252b5132 8956\f
252b5132 8957symbolS *
7016a5d5 8958md_undefined_symbol (char *name)
252b5132 8959{
18dc2407
ILT		 8960 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8961 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8962 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8963 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8964 {
8965 if (!GOT_symbol)
8966 {
8967 if (symbol_find (name))
8968 as_bad (_("GOT already in symbol table"));
8969 GOT_symbol = symbol_new (name, undefined_section,
8970 (valueT) 0, &zero_address_frag);
8971 };
8972 return GOT_symbol;
8973 }
252b5132
RH		 8974 return 0;
8975}
8976
8977/* Round up a section size to the appropriate boundary. */
47926f60 8978
252b5132 8979valueT
7016a5d5 8980md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 8981{
4c63da97
AM		 8982#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8983 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8984 {
8985 /* For a.out, force the section size to be aligned. If we don't do
8986 this, BFD will align it for us, but it will not write out the
8987 final bytes of the section. This may be a bug in BFD, but it is
8988 easier to fix it here since that is how the other a.out targets
8989 work. */
8990 int align;
8991
8992 align = bfd_get_section_alignment (stdoutput, segment);
8993 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8994 }
252b5132
RH		 8995#endif
8996
8997 return size;
8998}
8999
9000/* On the i386, PC-relative offsets are relative to the start of the
9001 next instruction. That is, the address of the offset, plus its
9002 size, since the offset is always the last part of the insn. */
9003
9004long
e3bb37b5 9005md_pcrel_from (fixS *fixP)
252b5132
RH		 9006{
9007 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
9008}
9009
9010#ifndef I386COFF
9011
9012static void
e3bb37b5 9013s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 9014{
29b0f896 9015 int temp;
252b5132 9016
8a75718c
JB		 9017#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9018 if (IS_ELF)
9019 obj_elf_section_change_hook ();
9020#endif
252b5132
RH		 9021 temp = get_absolute_expression ();
9022 subseg_set (bss_section, (subsegT) temp);
9023 demand_empty_rest_of_line ();
9024}
9025
9026#endif
9027
252b5132 9028void
e3bb37b5 9029i386_validate_fix (fixS *fixp)
252b5132
RH		 9030{
9031 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
9032 {
23df1078
JH		 9033 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
9034 {
4fa24527 9035 if (!object_64bit)
23df1078
JH		 9036 abort ();
9037 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
9038 }
9039 else
9040 {
4fa24527 9041 if (!object_64bit)
d6ab8113
JB		 9042 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
9043 else
9044 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 9045 }
252b5132
RH		 9046 fixp->fx_subsy = 0;
9047 }
9048}
9049
252b5132 9050arelent *
7016a5d5 9051tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 9052{
9053 arelent *rel;
9054 bfd_reloc_code_real_type code;
9055
9056 switch (fixp->fx_r_type)
9057 {
3e73aa7c
JH		 9058 case BFD_RELOC_X86_64_PLT32:
9059 case BFD_RELOC_X86_64_GOT32:
9060 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 9061 case BFD_RELOC_386_PLT32:
9062 case BFD_RELOC_386_GOT32:
9063 case BFD_RELOC_386_GOTOFF:
9064 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 9065 case BFD_RELOC_386_TLS_GD:
9066 case BFD_RELOC_386_TLS_LDM:
9067 case BFD_RELOC_386_TLS_LDO_32:
9068 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9069 case BFD_RELOC_386_TLS_IE:
9070 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 9071 case BFD_RELOC_386_TLS_LE_32:
9072 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 9073 case BFD_RELOC_386_TLS_GOTDESC:
9074 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 9075 case BFD_RELOC_X86_64_TLSGD:
9076 case BFD_RELOC_X86_64_TLSLD:
9077 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9078 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 9079 case BFD_RELOC_X86_64_GOTTPOFF:
9080 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 9081 case BFD_RELOC_X86_64_TPOFF64:
9082 case BFD_RELOC_X86_64_GOTOFF64:
9083 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 9084 case BFD_RELOC_X86_64_GOT64:
9085 case BFD_RELOC_X86_64_GOTPCREL64:
9086 case BFD_RELOC_X86_64_GOTPC64:
9087 case BFD_RELOC_X86_64_GOTPLT64:
9088 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 9089 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9090 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 9091 case BFD_RELOC_RVA:
9092 case BFD_RELOC_VTABLE_ENTRY:
9093 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 9094#ifdef TE_PE
9095 case BFD_RELOC_32_SECREL:
9096#endif
252b5132
RH		 9097 code = fixp->fx_r_type;
9098 break;
dbbaec26
L		 9099 case BFD_RELOC_X86_64_32S:
9100 if (!fixp->fx_pcrel)
9101 {
9102 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
9103 code = fixp->fx_r_type;
9104 break;
9105 }
252b5132 9106 default:
93382f6d 9107 if (fixp->fx_pcrel)
252b5132 9108 {
93382f6d
AM		 9109 switch (fixp->fx_size)
9110 {
9111 default:
b091f402
AM		 9112 as_bad_where (fixp->fx_file, fixp->fx_line,
9113 _("can not do %d byte pc-relative relocation"),
9114 fixp->fx_size);
93382f6d
AM		 9115 code = BFD_RELOC_32_PCREL;
9116 break;
9117 case 1: code = BFD_RELOC_8_PCREL; break;
9118 case 2: code = BFD_RELOC_16_PCREL; break;
9119 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 9120#ifdef BFD64
9121 case 8: code = BFD_RELOC_64_PCREL; break;
9122#endif
93382f6d
AM		 9123 }
9124 }
9125 else
9126 {
9127 switch (fixp->fx_size)
9128 {
9129 default:
b091f402
AM		 9130 as_bad_where (fixp->fx_file, fixp->fx_line,
9131 _("can not do %d byte relocation"),
9132 fixp->fx_size);
93382f6d
AM		 9133 code = BFD_RELOC_32;
9134 break;
9135 case 1: code = BFD_RELOC_8; break;
9136 case 2: code = BFD_RELOC_16; break;
9137 case 4: code = BFD_RELOC_32; break;
937149dd 9138#ifdef BFD64
3e73aa7c 9139 case 8: code = BFD_RELOC_64; break;
937149dd 9140#endif
93382f6d 9141 }
252b5132
RH		 9142 }
9143 break;
9144 }
252b5132 9145
d182319b
JB		 9146 if ((code == BFD_RELOC_32
9147 || code == BFD_RELOC_32_PCREL
9148 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 9149 && GOT_symbol
9150 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 9151 {
4fa24527 9152 if (!object_64bit)
d6ab8113
JB		 9153 code = BFD_RELOC_386_GOTPC;
9154 else
9155 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 9156 }
7b81dfbb
AJ		 9157 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
9158 && GOT_symbol
9159 && fixp->fx_addsy == GOT_symbol)
9160 {
9161 code = BFD_RELOC_X86_64_GOTPC64;
9162 }
252b5132
RH		 9163
9164 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 9165 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
9166 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 9167
9168 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 9169
3e73aa7c
JH		 9170 if (!use_rela_relocations)
9171 {
9172 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
9173 vtable entry to be used in the relocation's section offset. */
9174 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
9175 rel->address = fixp->fx_offset;
fbeb56a4
DK		 9176#if defined (OBJ_COFF) && defined (TE_PE)
9177 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
9178 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
9179 else
9180#endif
c6682705 9181 rel->addend = 0;
3e73aa7c
JH		 9182 }
9183 /* Use the rela in 64bit mode. */
252b5132 9184 else
3e73aa7c 9185 {
862be3fb
L		 9186 if (disallow_64bit_reloc)
9187 switch (code)
9188 {
862be3fb
L		 9189 case BFD_RELOC_X86_64_DTPOFF64:
9190 case BFD_RELOC_X86_64_TPOFF64:
9191 case BFD_RELOC_64_PCREL:
9192 case BFD_RELOC_X86_64_GOTOFF64:
9193 case BFD_RELOC_X86_64_GOT64:
9194 case BFD_RELOC_X86_64_GOTPCREL64:
9195 case BFD_RELOC_X86_64_GOTPC64:
9196 case BFD_RELOC_X86_64_GOTPLT64:
9197 case BFD_RELOC_X86_64_PLTOFF64:
9198 as_bad_where (fixp->fx_file, fixp->fx_line,
9199 _("cannot represent relocation type %s in x32 mode"),
9200 bfd_get_reloc_code_name (code));
9201 break;
9202 default:
9203 break;
9204 }
9205
062cd5e7
AS		 9206 if (!fixp->fx_pcrel)
9207 rel->addend = fixp->fx_offset;
9208 else
9209 switch (code)
9210 {
9211 case BFD_RELOC_X86_64_PLT32:
9212 case BFD_RELOC_X86_64_GOT32:
9213 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 9214 case BFD_RELOC_X86_64_TLSGD:
9215 case BFD_RELOC_X86_64_TLSLD:
9216 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 9217 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9218 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 9219 rel->addend = fixp->fx_offset - fixp->fx_size;
9220 break;
9221 default:
9222 rel->addend = (section->vma
9223 - fixp->fx_size
9224 + fixp->fx_addnumber
9225 + md_pcrel_from (fixp));
9226 break;
9227 }
3e73aa7c
JH		 9228 }
9229
252b5132
RH		 9230 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
9231 if (rel->howto == NULL)
9232 {
9233 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 9234 _("cannot represent relocation type %s"),
252b5132
RH		 9235 bfd_get_reloc_code_name (code));
9236 /* Set howto to a garbage value so that we can keep going. */
9237 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 9238 gas_assert (rel->howto != NULL);
252b5132
RH		 9239 }
9240
9241 return rel;
9242}
9243
ee86248c 9244#include "tc-i386-intel.c"
54cfded0 9245
a60de03c
JB		 9246void
9247tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 9248{
a60de03c
JB		 9249 int saved_naked_reg;
9250 char saved_register_dot;
54cfded0 9251
a60de03c
JB		 9252 saved_naked_reg = allow_naked_reg;
9253 allow_naked_reg = 1;
9254 saved_register_dot = register_chars['.'];
9255 register_chars['.'] = '.';
9256 allow_pseudo_reg = 1;
9257 expression_and_evaluate (exp);
9258 allow_pseudo_reg = 0;
9259 register_chars['.'] = saved_register_dot;
9260 allow_naked_reg = saved_naked_reg;
9261
e96d56a1 9262 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 9263 {
a60de03c
JB		 9264 if ((addressT) exp->X_add_number < i386_regtab_size)
9265 {
9266 exp->X_op = O_constant;
9267 exp->X_add_number = i386_regtab[exp->X_add_number]
9268 .dw2_regnum[flag_code >> 1];
9269 }
9270 else
9271 exp->X_op = O_illegal;
54cfded0 9272 }
54cfded0
AM		 9273}
9274
9275void
9276tc_x86_frame_initial_instructions (void)
9277{
a60de03c
JB		 9278 static unsigned int sp_regno[2];
9279
9280 if (!sp_regno[flag_code >> 1])
9281 {
9282 char *saved_input = input_line_pointer;
9283 char sp[][4] = {"esp", "rsp"};
9284 expressionS exp;
a4447b93 9285
a60de03c
JB		 9286 input_line_pointer = sp[flag_code >> 1];
9287 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 9288 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 9289 sp_regno[flag_code >> 1] = exp.X_add_number;
9290 input_line_pointer = saved_input;
9291 }
a4447b93 9292
61ff971f
L		 9293 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
9294 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 9295}
d2b2c203 9296
d7921315
L		 9297int
9298x86_dwarf2_addr_size (void)
9299{
9300#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9301 if (x86_elf_abi == X86_64_X32_ABI)
9302 return 4;
9303#endif
9304 return bfd_arch_bits_per_address (stdoutput) / 8;
9305}
9306
d2b2c203
DJ		 9307int
9308i386_elf_section_type (const char *str, size_t len)
9309{
9310 if (flag_code == CODE_64BIT
9311 && len == sizeof ("unwind") - 1
9312 && strncmp (str, "unwind", 6) == 0)
9313 return SHT_X86_64_UNWIND;
9314
9315 return -1;
9316}
bb41ade5 9317
ad5fec3b
EB		 9318#ifdef TE_SOLARIS
9319void
9320i386_solaris_fix_up_eh_frame (segT sec)
9321{
9322 if (flag_code == CODE_64BIT)
9323 elf_section_type (sec) = SHT_X86_64_UNWIND;
9324}
9325#endif
9326
bb41ade5
AM		 9327#ifdef TE_PE
9328void
9329tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9330{
91d6fa6a 9331 expressionS exp;
bb41ade5 9332
91d6fa6a
NC		 9333 exp.X_op = O_secrel;
9334 exp.X_add_symbol = symbol;
9335 exp.X_add_number = 0;
9336 emit_expr (&exp, size);
bb41ade5
AM		 9337}
9338#endif
3b22753a
L		 9339
9340#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9341/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9342
01e1a5bc 9343bfd_vma
3b22753a
L		 9344x86_64_section_letter (int letter, char **ptr_msg)
9345{
9346 if (flag_code == CODE_64BIT)
9347 {
9348 if (letter == 'l')
9349 return SHF_X86_64_LARGE;
9350
8f3bae45 9351 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9352 }
3b22753a 9353 else
8f3bae45 9354 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9355 return -1;
9356}
9357
01e1a5bc 9358bfd_vma
3b22753a
L		 9359x86_64_section_word (char *str, size_t len)
9360{
8620418b 9361 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9362 return SHF_X86_64_LARGE;
9363
9364 return -1;
9365}
9366
9367static void
9368handle_large_common (int small ATTRIBUTE_UNUSED)
9369{
9370 if (flag_code != CODE_64BIT)
9371 {
9372 s_comm_internal (0, elf_common_parse);
9373 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9374 }
9375 else
9376 {
9377 static segT lbss_section;
9378 asection *saved_com_section_ptr = elf_com_section_ptr;
9379 asection *saved_bss_section = bss_section;
9380
9381 if (lbss_section == NULL)
9382 {
9383 flagword applicable;
9384 segT seg = now_seg;
9385 subsegT subseg = now_subseg;
9386
9387 /* The .lbss section is for local .largecomm symbols. */
9388 lbss_section = subseg_new (".lbss", 0);
9389 applicable = bfd_applicable_section_flags (stdoutput);
9390 bfd_set_section_flags (stdoutput, lbss_section,
9391 applicable & SEC_ALLOC);
9392 seg_info (lbss_section)->bss = 1;
9393
9394 subseg_set (seg, subseg);
9395 }
9396
9397 elf_com_section_ptr = &_bfd_elf_large_com_section;
9398 bss_section = lbss_section;
9399
9400 s_comm_internal (0, elf_common_parse);
9401
9402 elf_com_section_ptr = saved_com_section_ptr;
9403 bss_section = saved_bss_section;
9404 }
9405}
9406#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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