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Default e_machine to EM_IAMCU for i?86-*-elfiamcu
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
b90efa5b 2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
89e7505f
L		 36#ifdef TE_LINUX
37/* Default to compress debug sections for Linux. */
151411f8
L		 38enum compressed_debug_section_type flag_compress_debug
39 = COMPRESS_DEBUG_ZLIB;
89e7505f
L		 40#endif
41
252b5132
RH		 42#ifndef REGISTER_WARNINGS
43#define REGISTER_WARNINGS 1
44#endif
45
c3332e24 46#ifndef INFER_ADDR_PREFIX
eecb386c 47#define INFER_ADDR_PREFIX 1
c3332e24
AM		 48#endif
49
29b0f896
AM		 50#ifndef DEFAULT_ARCH
51#define DEFAULT_ARCH "i386"
246fcdee 52#endif
252b5132 53
edde18a5
AM		 54#ifndef INLINE
55#if __GNUC__ >= 2
56#define INLINE __inline__
57#else
58#define INLINE
59#endif
60#endif
61
6305a203
L		 62/* Prefixes will be emitted in the order defined below.
63 WAIT_PREFIX must be the first prefix since FWAIT is really is an
64 instruction, and so must come before any prefixes.
65 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 66 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 67#define WAIT_PREFIX 0
68#define SEG_PREFIX 1
69#define ADDR_PREFIX 2
70#define DATA_PREFIX 3
c32fa91d 71#define REP_PREFIX 4
42164a71 72#define HLE_PREFIX REP_PREFIX
7e8b059b 73#define BND_PREFIX REP_PREFIX
c32fa91d
L		 74#define LOCK_PREFIX 5
75#define REX_PREFIX 6 /* must come last. */
76#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 77
78/* we define the syntax here (modulo base,index,scale syntax) */
79#define REGISTER_PREFIX '%'
80#define IMMEDIATE_PREFIX '$'
81#define ABSOLUTE_PREFIX '*'
82
83/* these are the instruction mnemonic suffixes in AT&T syntax or
84 memory operand size in Intel syntax. */
85#define WORD_MNEM_SUFFIX 'w'
86#define BYTE_MNEM_SUFFIX 'b'
87#define SHORT_MNEM_SUFFIX 's'
88#define LONG_MNEM_SUFFIX 'l'
89#define QWORD_MNEM_SUFFIX 'q'
90#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 91#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 92#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 93/* Intel Syntax. Use a non-ascii letter since since it never appears
94 in instructions. */
95#define LONG_DOUBLE_MNEM_SUFFIX '\1'
96
97#define END_OF_INSN '\0'
98
99/*
100 'templates' is for grouping together 'template' structures for opcodes
101 of the same name. This is only used for storing the insns in the grand
102 ole hash table of insns.
103 The templates themselves start at START and range up to (but not including)
104 END.
105 */
106typedef struct
107{
d3ce72d0
NC		 108 const insn_template *start;
109 const insn_template *end;
6305a203
L		 110}
111templates;
112
113/* 386 operand encoding bytes: see 386 book for details of this. */
114typedef struct
115{
116 unsigned int regmem; /* codes register or memory operand */
117 unsigned int reg; /* codes register operand (or extended opcode) */
118 unsigned int mode; /* how to interpret regmem & reg */
119}
120modrm_byte;
121
122/* x86-64 extension prefix. */
123typedef int rex_byte;
124
6305a203
L		 125/* 386 opcode byte to code indirect addressing. */
126typedef struct
127{
128 unsigned base;
129 unsigned index;
130 unsigned scale;
131}
132sib_byte;
133
6305a203
L		 134/* x86 arch names, types and features */
135typedef struct
136{
137 const char *name; /* arch name */
8a2c8fef 138 unsigned int len; /* arch string length */
6305a203
L		 139 enum processor_type type; /* arch type */
140 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 141 unsigned int skip; /* show_arch should skip this. */
22109423 142 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 143}
144arch_entry;
145
78f12dd3 146static void update_code_flag (int, int);
e3bb37b5
L		 147static void set_code_flag (int);
148static void set_16bit_gcc_code_flag (int);
149static void set_intel_syntax (int);
1efbbeb4 150static void set_intel_mnemonic (int);
db51cc60 151static void set_allow_index_reg (int);
7bab8ab5 152static void set_check (int);
e3bb37b5 153static void set_cpu_arch (int);
6482c264 154#ifdef TE_PE
e3bb37b5 155static void pe_directive_secrel (int);
6482c264 156#endif
e3bb37b5
L		 157static void signed_cons (int);
158static char *output_invalid (int c);
ee86248c
JB		 159static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
160 const char *);
161static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
162 const char *);
a7619375 163static int i386_att_operand (char *);
e3bb37b5 164static int i386_intel_operand (char *, int);
ee86248c
JB		 165static int i386_intel_simplify (expressionS *);
166static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 167static const reg_entry *parse_register (char *, char **);
168static char *parse_insn (char *, char *);
169static char *parse_operands (char *, const char *);
170static void swap_operands (void);
4d456e3d 171static void swap_2_operands (int, int);
e3bb37b5
L		 172static void optimize_imm (void);
173static void optimize_disp (void);
d3ce72d0 174static const insn_template *match_template (void);
e3bb37b5
L		 175static int check_string (void);
176static int process_suffix (void);
177static int check_byte_reg (void);
178static int check_long_reg (void);
179static int check_qword_reg (void);
180static int check_word_reg (void);
181static int finalize_imm (void);
182static int process_operands (void);
183static const seg_entry *build_modrm_byte (void);
184static void output_insn (void);
185static void output_imm (fragS *, offsetT);
186static void output_disp (fragS *, offsetT);
29b0f896 187#ifndef I386COFF
e3bb37b5 188static void s_bss (int);
252b5132 189#endif
17d4e2a2
L		 190#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
191static void handle_large_common (int small ATTRIBUTE_UNUSED);
192#endif
252b5132 193
a847613f 194static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 195
43234a1e
L		 196/* This struct describes rounding control and SAE in the instruction. */
197struct RC_Operation
198{
199 enum rc_type
200 {
201 rne = 0,
202 rd,
203 ru,
204 rz,
205 saeonly
206 } type;
207 int operand;
208};
209
210static struct RC_Operation rc_op;
211
212/* The struct describes masking, applied to OPERAND in the instruction.
213 MASK is a pointer to the corresponding mask register. ZEROING tells
214 whether merging or zeroing mask is used. */
215struct Mask_Operation
216{
217 const reg_entry *mask;
218 unsigned int zeroing;
219 /* The operand where this operation is associated. */
220 int operand;
221};
222
223static struct Mask_Operation mask_op;
224
225/* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 broadcast factor. */
227struct Broadcast_Operation
228{
229 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
230 int type;
231
232 /* Index of broadcasted operand. */
233 int operand;
234};
235
236static struct Broadcast_Operation broadcast_op;
237
c0f3af97
L		 238/* VEX prefix. */
239typedef struct
240{
43234a1e
L		 241 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
242 unsigned char bytes[4];
c0f3af97
L		 243 unsigned int length;
244 /* Destination or source register specifier. */
245 const reg_entry *register_specifier;
246} vex_prefix;
247
252b5132 248/* 'md_assemble ()' gathers together information and puts it into a
47926f60 249 i386_insn. */
252b5132 250
520dc8e8
AM		 251union i386_op
252 {
253 expressionS *disps;
254 expressionS *imms;
255 const reg_entry *regs;
256 };
257
a65babc9
L		 258enum i386_error
259 {
86e026a4 260 operand_size_mismatch,
a65babc9
L		 261 operand_type_mismatch,
262 register_type_mismatch,
263 number_of_operands_mismatch,
264 invalid_instruction_suffix,
265 bad_imm4,
266 old_gcc_only,
267 unsupported_with_intel_mnemonic,
268 unsupported_syntax,
6c30d220
L		 269 unsupported,
270 invalid_vsib_address,
7bab8ab5 271 invalid_vector_register_set,
43234a1e
L		 272 unsupported_vector_index_register,
273 unsupported_broadcast,
274 broadcast_not_on_src_operand,
275 broadcast_needed,
276 unsupported_masking,
277 mask_not_on_destination,
278 no_default_mask,
279 unsupported_rc_sae,
280 rc_sae_operand_not_last_imm,
281 invalid_register_operand,
282 try_vector_disp8
a65babc9
L		 283 };
284
252b5132
RH		 285struct _i386_insn
286 {
47926f60 287 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 288 insn_template tm;
252b5132 289
7d5e4556
L		 290 /* SUFFIX holds the instruction size suffix for byte, word, dword
291 or qword, if given. */
252b5132
RH		 292 char suffix;
293
47926f60 294 /* OPERANDS gives the number of given operands. */
252b5132
RH		 295 unsigned int operands;
296
297 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
298 of given register, displacement, memory operands and immediate
47926f60 299 operands. */
252b5132
RH		 300 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
301
302 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 303 use OP[i] for the corresponding operand. */
40fb9820 304 i386_operand_type types[MAX_OPERANDS];
252b5132 305
520dc8e8
AM		 306 /* Displacement expression, immediate expression, or register for each
307 operand. */
308 union i386_op op[MAX_OPERANDS];
252b5132 309
3e73aa7c
JH		 310 /* Flags for operands. */
311 unsigned int flags[MAX_OPERANDS];
312#define Operand_PCrel 1
313
252b5132 314 /* Relocation type for operand */
f86103b7 315 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 316
252b5132
RH		 317 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
318 the base index byte below. */
319 const reg_entry *base_reg;
320 const reg_entry *index_reg;
321 unsigned int log2_scale_factor;
322
323 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 324 explicit segment overrides are given. */
ce8a8b2f 325 const seg_entry *seg[2];
252b5132
RH		 326
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
331
332 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 333 addressing modes of this insn are encoded. */
252b5132 334 modrm_byte rm;
3e73aa7c 335 rex_byte rex;
43234a1e 336 rex_byte vrex;
252b5132 337 sib_byte sib;
c0f3af97 338 vex_prefix vex;
b6169b20 339
43234a1e
L		 340 /* Masking attributes. */
341 struct Mask_Operation *mask;
342
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
345
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
348
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
351
b6169b20 352 /* Swap operand in encoding. */
4473e004 353 unsigned int swap_operand;
891edac4 354
a501d77e
L		 355 /* Prefer 8bit or 32bit displacement in encoding. */
356 enum
357 {
358 disp_encoding_default = 0,
359 disp_encoding_8bit,
360 disp_encoding_32bit
361 } disp_encoding;
f8a5c266 362
d5de92cf
L		 363 /* REP prefix. */
364 const char *rep_prefix;
365
165de32a
L		 366 /* HLE prefix. */
367 const char *hle_prefix;
42164a71 368
7e8b059b
L		 369 /* Have BND prefix. */
370 const char *bnd_prefix;
371
43234a1e
L		 372 /* Need VREX to support upper 16 registers. */
373 int need_vrex;
374
891edac4 375 /* Error message. */
a65babc9 376 enum i386_error error;
252b5132
RH		 377 };
378
379typedef struct _i386_insn i386_insn;
380
43234a1e
L		 381/* Link RC type with corresponding string, that'll be looked for in
382 asm. */
383struct RC_name
384{
385 enum rc_type type;
386 const char *name;
387 unsigned int len;
388};
389
390static const struct RC_name RC_NamesTable[] =
391{
392 { rne, STRING_COMMA_LEN ("rn-sae") },
393 { rd, STRING_COMMA_LEN ("rd-sae") },
394 { ru, STRING_COMMA_LEN ("ru-sae") },
395 { rz, STRING_COMMA_LEN ("rz-sae") },
396 { saeonly, STRING_COMMA_LEN ("sae") },
397};
398
252b5132
RH		 399/* List of chars besides those in app.c:symbol_chars that can start an
400 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 401const char extra_symbol_chars[] = "*%-([{"
252b5132 402#ifdef LEX_AT
32137342
NC		 403 "@"
404#endif
405#ifdef LEX_QM
406 "?"
252b5132 407#endif
32137342 408 ;
252b5132 409
29b0f896
AM		 410#if (defined (TE_I386AIX) \
411 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 412 && !defined (TE_GNU) \
29b0f896 413 && !defined (TE_LINUX) \
8d63c93e
RM		 414 && !defined (TE_NACL) \
415 && !defined (TE_NETWARE) \
29b0f896 416 && !defined (TE_FreeBSD) \
5b806d27 417 && !defined (TE_DragonFly) \
29b0f896 418 && !defined (TE_NetBSD)))
252b5132 419/* This array holds the chars that always start a comment. If the
b3b91714
AM		 420 pre-processor is disabled, these aren't very useful. The option
421 --divide will remove '/' from this list. */
422const char *i386_comment_chars = "#/";
423#define SVR4_COMMENT_CHARS 1
252b5132 424#define PREFIX_SEPARATOR '\\'
252b5132 425
b3b91714
AM		 426#else
427const char *i386_comment_chars = "#";
428#define PREFIX_SEPARATOR '/'
429#endif
430
252b5132
RH		 431/* This array holds the chars that only start a comment at the beginning of
432 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 433 .line and .file directives will appear in the pre-processed output.
434 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 435 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 436 #NO_APP at the beginning of its output.
437 Also note that comments started like this one will always work if
252b5132 438 '/' isn't otherwise defined. */
b3b91714 439const char line_comment_chars[] = "#/";
252b5132 440
63a0b638 441const char line_separator_chars[] = ";";
252b5132 442
ce8a8b2f
AM		 443/* Chars that can be used to separate mant from exp in floating point
444 nums. */
252b5132
RH		 445const char EXP_CHARS[] = "eE";
446
ce8a8b2f
AM		 447/* Chars that mean this number is a floating point constant
448 As in 0f12.456
449 or 0d1.2345e12. */
252b5132
RH		 450const char FLT_CHARS[] = "fFdDxX";
451
ce8a8b2f 452/* Tables for lexical analysis. */
252b5132
RH		 453static char mnemonic_chars[256];
454static char register_chars[256];
455static char operand_chars[256];
456static char identifier_chars[256];
457static char digit_chars[256];
458
ce8a8b2f 459/* Lexical macros. */
252b5132
RH		 460#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
461#define is_operand_char(x) (operand_chars[(unsigned char) x])
462#define is_register_char(x) (register_chars[(unsigned char) x])
463#define is_space_char(x) ((x) == ' ')
464#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
465#define is_digit_char(x) (digit_chars[(unsigned char) x])
466
0234cb7c 467/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 468static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
469
470/* md_assemble() always leaves the strings it's passed unaltered. To
471 effect this we maintain a stack of saved characters that we've smashed
472 with '\0's (indicating end of strings for various sub-fields of the
47926f60 473 assembler instruction). */
252b5132 474static char save_stack[32];
ce8a8b2f 475static char *save_stack_p;
252b5132
RH		 476#define END_STRING_AND_SAVE(s) \
477 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
478#define RESTORE_END_STRING(s) \
479 do { *(s) = *--save_stack_p; } while (0)
480
47926f60 481/* The instruction we're assembling. */
252b5132
RH		 482static i386_insn i;
483
484/* Possible templates for current insn. */
485static const templates *current_templates;
486
31b2323c
L		 487/* Per instruction expressionS buffers: max displacements & immediates. */
488static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
489static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 490
47926f60 491/* Current operand we are working on. */
ee86248c 492static int this_operand = -1;
252b5132 493
3e73aa7c
JH		 494/* We support four different modes. FLAG_CODE variable is used to distinguish
495 these. */
496
497enum flag_code {
498 CODE_32BIT,
499 CODE_16BIT,
500 CODE_64BIT };
501
502static enum flag_code flag_code;
4fa24527 503static unsigned int object_64bit;
862be3fb 504static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 505static int use_rela_relocations = 0;
506
7af8ed2d
NC		 507#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
508 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
509 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
510
351f65ca
L		 511/* The ELF ABI to use. */
512enum x86_elf_abi
513{
514 I386_ABI,
7f56bc95
L		 515 X86_64_ABI,
516 X86_64_X32_ABI
351f65ca
L		 517};
518
519static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 520#endif
351f65ca 521
167ad85b
TG		 522#if defined (TE_PE) || defined (TE_PEP)
523/* Use big object file format. */
524static int use_big_obj = 0;
525#endif
526
573cc2e5
L		 527#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
528/* 1 if not generating code for a shared library. */
529static int no_shared = 0;
530#endif
531
47926f60
KH		 532/* 1 for intel syntax,
533 0 if att syntax. */
534static int intel_syntax = 0;
252b5132 535
1efbbeb4
L		 536/* 1 for intel mnemonic,
537 0 if att mnemonic. */
538static int intel_mnemonic = !SYSV386_COMPAT;
539
5209009a 540/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 541static int old_gcc = OLDGCC_COMPAT;
542
a60de03c
JB		 543/* 1 if pseudo registers are permitted. */
544static int allow_pseudo_reg = 0;
545
47926f60
KH		 546/* 1 if register prefix % not required. */
547static int allow_naked_reg = 0;
252b5132 548
7e8b059b
L		 549/* 1 if the assembler should add BND prefix for all control-tranferring
550 instructions supporting it, even if this prefix wasn't specified
551 explicitly. */
552static int add_bnd_prefix = 0;
553
ba104c83 554/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 555static int allow_index_reg = 0;
556
d022bddd
IT		 557/* 1 if the assembler should ignore LOCK prefix, even if it was
558 specified explicitly. */
559static int omit_lock_prefix = 0;
560
7bab8ab5 561static enum check_kind
daf50ae7 562 {
7bab8ab5
JB		 563 check_none = 0,
564 check_warning,
565 check_error
daf50ae7 566 }
7bab8ab5 567sse_check, operand_check = check_warning;
daf50ae7 568
2ca3ace5
L		 569/* Register prefix used for error message. */
570static const char *register_prefix = "%";
571
47926f60
KH		 572/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
573 leave, push, and pop instructions so that gcc has the same stack
574 frame as in 32 bit mode. */
575static char stackop_size = '\0';
eecb386c 576
12b55ccc
L		 577/* Non-zero to optimize code alignment. */
578int optimize_align_code = 1;
579
47926f60
KH		 580/* Non-zero to quieten some warnings. */
581static int quiet_warnings = 0;
a38cf1db 582
47926f60
KH		 583/* CPU name. */
584static const char *cpu_arch_name = NULL;
6305a203 585static char *cpu_sub_arch_name = NULL;
a38cf1db 586
47926f60 587/* CPU feature flags. */
40fb9820
L		 588static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
589
ccc9c027
L		 590/* If we have selected a cpu we are generating instructions for. */
591static int cpu_arch_tune_set = 0;
592
9103f4f4 593/* Cpu we are generating instructions for. */
fbf3f584 594enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 595
596/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 597static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 598
ccc9c027 599/* CPU instruction set architecture used. */
fbf3f584 600enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 601
9103f4f4 602/* CPU feature flags of instruction set architecture used. */
fbf3f584 603i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 604
fddf5b5b
AM		 605/* If set, conditional jumps are not automatically promoted to handle
606 larger than a byte offset. */
607static unsigned int no_cond_jump_promotion = 0;
608
c0f3af97
L		 609/* Encode SSE instructions with VEX prefix. */
610static unsigned int sse2avx;
611
539f890d
L		 612/* Encode scalar AVX instructions with specific vector length. */
613static enum
614 {
615 vex128 = 0,
616 vex256
617 } avxscalar;
618
43234a1e
L		 619/* Encode scalar EVEX LIG instructions with specific vector length. */
620static enum
621 {
622 evexl128 = 0,
623 evexl256,
624 evexl512
625 } evexlig;
626
627/* Encode EVEX WIG instructions with specific evex.w. */
628static enum
629 {
630 evexw0 = 0,
631 evexw1
632 } evexwig;
633
d3d3c6db
IT		 634/* Value to encode in EVEX RC bits, for SAE-only instructions. */
635static enum rc_type evexrcig = rne;
636
29b0f896 637/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 638static symbolS *GOT_symbol;
29b0f896 639
a4447b93
RH		 640/* The dwarf2 return column, adjusted for 32 or 64 bit. */
641unsigned int x86_dwarf2_return_column;
642
643/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
644int x86_cie_data_alignment;
645
252b5132 646/* Interface to relax_segment.
fddf5b5b
AM		 647 There are 3 major relax states for 386 jump insns because the
648 different types of jumps add different sizes to frags when we're
649 figuring out what sort of jump to choose to reach a given label. */
252b5132 650
47926f60 651/* Types. */
93c2a809
AM		 652#define UNCOND_JUMP 0
653#define COND_JUMP 1
654#define COND_JUMP86 2
fddf5b5b 655
47926f60 656/* Sizes. */
252b5132
RH		 657#define CODE16 1
658#define SMALL 0
29b0f896 659#define SMALL16 (SMALL | CODE16)
252b5132 660#define BIG 2
29b0f896 661#define BIG16 (BIG | CODE16)
252b5132
RH		 662
663#ifndef INLINE
664#ifdef __GNUC__
665#define INLINE __inline__
666#else
667#define INLINE
668#endif
669#endif
670
fddf5b5b
AM		 671#define ENCODE_RELAX_STATE(type, size) \
672 ((relax_substateT) (((type) << 2) | (size)))
673#define TYPE_FROM_RELAX_STATE(s) \
674 ((s) >> 2)
675#define DISP_SIZE_FROM_RELAX_STATE(s) \
676 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 677
678/* This table is used by relax_frag to promote short jumps to long
679 ones where necessary. SMALL (short) jumps may be promoted to BIG
680 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
681 don't allow a short jump in a 32 bit code segment to be promoted to
682 a 16 bit offset jump because it's slower (requires data size
683 prefix), and doesn't work, unless the destination is in the bottom
684 64k of the code segment (The top 16 bits of eip are zeroed). */
685
686const relax_typeS md_relax_table[] =
687{
24eab124
AM		 688 /* The fields are:
689 1) most positive reach of this state,
690 2) most negative reach of this state,
93c2a809 691 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 692 4) which index into the table to try if we can't fit into this one. */
252b5132 693
fddf5b5b 694 /* UNCOND_JUMP states. */
93c2a809
AM		 695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
696 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
697 /* dword jmp adds 4 bytes to frag:
698 0 extra opcode bytes, 4 displacement bytes. */
252b5132 699 {0, 0, 4, 0},
93c2a809
AM		 700 /* word jmp adds 2 byte2 to frag:
701 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 702 {0, 0, 2, 0},
703
93c2a809
AM		 704 /* COND_JUMP states. */
705 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
706 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
707 /* dword conditionals adds 5 bytes to frag:
708 1 extra opcode byte, 4 displacement bytes. */
709 {0, 0, 5, 0},
fddf5b5b 710 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 711 1 extra opcode byte, 2 displacement bytes. */
712 {0, 0, 3, 0},
713
714 /* COND_JUMP86 states. */
715 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
716 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
717 /* dword conditionals adds 5 bytes to frag:
718 1 extra opcode byte, 4 displacement bytes. */
719 {0, 0, 5, 0},
720 /* word conditionals add 4 bytes to frag:
721 1 displacement byte and a 3 byte long branch insn. */
722 {0, 0, 4, 0}
252b5132
RH		 723};
724
9103f4f4
L		 725static const arch_entry cpu_arch[] =
726{
89507696
JB		 727 /* Do not replace the first two entries - i386_target_format()
728 relies on them being there in this order. */
8a2c8fef 729 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 730 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 731 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 732 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 733 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 734 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 735 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 736 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 737 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 738 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 739 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 740 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 741 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 742 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 743 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 744 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 745 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 746 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 747 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 748 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 749 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 750 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 751 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 752 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 753 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 754 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 755 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 756 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 757 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 758 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 759 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 760 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 761 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 762 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 764 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 766 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 767 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 768 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 769 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 770 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 771 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 772 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 773 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
774 CPU_K1OM_FLAGS, 0, 0 },
81486035
L		 775 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
776 CPU_IAMCU_FLAGS, 0, 0 },
8a2c8fef 777 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 778 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 779 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 780 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 781 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 782 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 783 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 784 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 785 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 786 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 787 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 788 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 789 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 790 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 791 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 792 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 793 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 794 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 795 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
796 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 797 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
798 CPU_BDVER4_FLAGS, 0, 0 },
029f3522
GG		 799 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
800 CPU_ZNVER1_FLAGS, 0, 0 },
7b458c12
L		 801 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
802 CPU_BTVER1_FLAGS, 0, 0 },
803 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
804 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 805 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 806 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 807 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 808 CPU_287_FLAGS, 0, 0 },
8a2c8fef 809 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 810 CPU_387_FLAGS, 0, 0 },
8a2c8fef 811 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 812 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 813 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 814 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 815 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 816 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 817 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 818 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 819 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 820 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 821 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 822 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 823 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 824 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 825 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 826 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 827 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 828 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 829 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 830 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 831 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 832 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 833 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 834 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 835 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
836 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 837 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
838 CPU_AVX512F_FLAGS, 0, 0 },
839 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
840 CPU_AVX512CD_FLAGS, 0, 0 },
841 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
842 CPU_AVX512ER_FLAGS, 0, 0 },
843 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
844 CPU_AVX512PF_FLAGS, 0, 0 },
1dfc6506
L		 845 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
846 CPU_AVX512DQ_FLAGS, 0, 0 },
847 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
848 CPU_AVX512BW_FLAGS, 0, 0 },
849 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
850 CPU_AVX512VL_FLAGS, 0, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 852 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 853 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 854 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 855 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
856 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 857 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 858 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 859 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 860 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 861 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 862 CPU_XSAVEOPT_FLAGS, 0, 0 },
1dfc6506
L		 863 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
864 CPU_XSAVEC_FLAGS, 0, 0 },
865 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
866 CPU_XSAVES_FLAGS, 0, 0 },
8a2c8fef 867 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 868 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 869 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 870 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 871 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 872 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 873 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 874 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 875 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 876 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 877 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 878 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 879 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
880 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 881 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 882 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 884 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 885 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 886 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 887 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 888 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 889 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 890 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 891 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
892 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 893 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 894 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 895 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
896 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 897 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
898 CPU_HLE_FLAGS, 0, 0 },
899 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
900 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 901 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
902 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 903 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 904 CPU_CLFLUSH_FLAGS, 0, 0 },
905 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
906 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 907 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 908 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 909 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 910 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 911 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 912 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 913 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 914 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 915 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 916 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 917 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 918 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 919 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 920 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 921 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 922 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 923 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 924 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 925 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
926 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 927 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
928 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 929 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
930 CPU_ADX_FLAGS, 0, 0 },
931 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
932 CPU_RDSEED_FLAGS, 0, 0 },
933 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
934 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 935 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
936 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 937 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
938 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 939 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
940 CPU_SHA_FLAGS, 0, 0 },
963f3586
IT		 941 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
942 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
dcf893b5
IT		 943 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
944 CPU_PREFETCHWT1_FLAGS, 0, 0 },
2cf200a4
IT		 945 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
946 CPU_SE1_FLAGS, 0, 0 },
c5e7287a
IT		 947 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
948 CPU_CLWB_FLAGS, 0, 0 },
9d8596f0
IT		 949 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
950 CPU_PCOMMIT_FLAGS, 0, 0 },
2cc1b5aa
IT		 951 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
952 CPU_AVX512IFMA_FLAGS, 0, 0 },
14f195c9
IT		 953 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
954 CPU_AVX512VBMI_FLAGS, 0, 0 },
029f3522
GG		 955 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
956 CPU_CLZERO_FLAGS, 0, 0 },
e413e4e9
AM		 957};
958
704209c0 959#ifdef I386COFF
a6c24e68
NC		 960/* Like s_lcomm_internal in gas/read.c but the alignment string
961 is allowed to be optional. */
962
963static symbolS *
964pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
965{
966 addressT align = 0;
967
968 SKIP_WHITESPACE ();
969
7ab9ffdd 970 if (needs_align
a6c24e68
NC		 971 && *input_line_pointer == ',')
972 {
973 align = parse_align (needs_align - 1);
7ab9ffdd 974
a6c24e68
NC		 975 if (align == (addressT) -1)
976 return NULL;
977 }
978 else
979 {
980 if (size >= 8)
981 align = 3;
982 else if (size >= 4)
983 align = 2;
984 else if (size >= 2)
985 align = 1;
986 else
987 align = 0;
988 }
989
990 bss_alloc (symbolP, size, align);
991 return symbolP;
992}
993
704209c0 994static void
a6c24e68
NC		 995pe_lcomm (int needs_align)
996{
997 s_comm_internal (needs_align * 2, pe_lcomm_internal);
998}
704209c0 999#endif
a6c24e68 1000
29b0f896
AM		 1001const pseudo_typeS md_pseudo_table[] =
1002{
1003#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1004 {"align", s_align_bytes, 0},
1005#else
1006 {"align", s_align_ptwo, 0},
1007#endif
1008 {"arch", set_cpu_arch, 0},
1009#ifndef I386COFF
1010 {"bss", s_bss, 0},
a6c24e68
NC		 1011#else
1012 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1013#endif
1014 {"ffloat", float_cons, 'f'},
1015 {"dfloat", float_cons, 'd'},
1016 {"tfloat", float_cons, 'x'},
1017 {"value", cons, 2},
d182319b 1018 {"slong", signed_cons, 4},
29b0f896
AM		 1019 {"noopt", s_ignore, 0},
1020 {"optim", s_ignore, 0},
1021 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1022 {"code16", set_code_flag, CODE_16BIT},
1023 {"code32", set_code_flag, CODE_32BIT},
1024 {"code64", set_code_flag, CODE_64BIT},
1025 {"intel_syntax", set_intel_syntax, 1},
1026 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1027 {"intel_mnemonic", set_intel_mnemonic, 1},
1028 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1029 {"allow_index_reg", set_allow_index_reg, 1},
1030 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1031 {"sse_check", set_check, 0},
1032 {"operand_check", set_check, 1},
3b22753a
L		 1033#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1034 {"largecomm", handle_large_common, 0},
07a53e5c 1035#else
e3bb37b5 1036 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1037 {"loc", dwarf2_directive_loc, 0},
1038 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1039#endif
6482c264
NC		 1040#ifdef TE_PE
1041 {"secrel32", pe_directive_secrel, 0},
1042#endif
29b0f896
AM		 1043 {0, 0, 0}
1044};
1045
1046/* For interface with expression (). */
1047extern char *input_line_pointer;
1048
1049/* Hash table for instruction mnemonic lookup. */
1050static struct hash_control *op_hash;
1051
1052/* Hash table for register lookup. */
1053static struct hash_control *reg_hash;
1054\f
252b5132 1055void
e3bb37b5 1056i386_align_code (fragS *fragP, int count)
252b5132 1057{
ce8a8b2f
AM		 1058 /* Various efficient no-op patterns for aligning code labels.
1059 Note: Don't try to assemble the instructions in the comments.
1060 0L and 0w are not legal. */
252b5132
RH		 1061 static const char f32_1[] =
1062 {0x90}; /* nop */
1063 static const char f32_2[] =
ccc9c027 1064 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1065 static const char f32_3[] =
1066 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1067 static const char f32_4[] =
1068 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1069 static const char f32_5[] =
1070 {0x90, /* nop */
1071 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1072 static const char f32_6[] =
1073 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1074 static const char f32_7[] =
1075 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1076 static const char f32_8[] =
1077 {0x90, /* nop */
1078 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1079 static const char f32_9[] =
1080 {0x89,0xf6, /* movl %esi,%esi */
1081 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1082 static const char f32_10[] =
1083 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1084 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1085 static const char f32_11[] =
1086 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1087 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1088 static const char f32_12[] =
1089 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1090 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1091 static const char f32_13[] =
1092 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1093 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1094 static const char f32_14[] =
1095 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1096 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1097 static const char f16_3[] =
1098 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1099 static const char f16_4[] =
1100 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1101 static const char f16_5[] =
1102 {0x90, /* nop */
1103 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1104 static const char f16_6[] =
1105 {0x89,0xf6, /* mov %si,%si */
1106 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1107 static const char f16_7[] =
1108 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1109 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1110 static const char f16_8[] =
1111 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1112 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1113 static const char jump_31[] =
1114 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1115 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1116 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1117 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1118 static const char *const f32_patt[] = {
1119 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1120 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1121 };
1122 static const char *const f16_patt[] = {
76bc74dc 1123 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1124 };
ccc9c027
L		 1125 /* nopl (%[re]ax) */
1126 static const char alt_3[] =
1127 {0x0f,0x1f,0x00};
1128 /* nopl 0(%[re]ax) */
1129 static const char alt_4[] =
1130 {0x0f,0x1f,0x40,0x00};
1131 /* nopl 0(%[re]ax,%[re]ax,1) */
1132 static const char alt_5[] =
1133 {0x0f,0x1f,0x44,0x00,0x00};
1134 /* nopw 0(%[re]ax,%[re]ax,1) */
1135 static const char alt_6[] =
1136 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1137 /* nopl 0L(%[re]ax) */
1138 static const char alt_7[] =
1139 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1140 /* nopl 0L(%[re]ax,%[re]ax,1) */
1141 static const char alt_8[] =
1142 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1143 /* nopw 0L(%[re]ax,%[re]ax,1) */
1144 static const char alt_9[] =
1145 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1146 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1147 static const char alt_10[] =
1148 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
80b8656c 1149 static const char *const alt_patt[] = {
ccc9c027 1150 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1151 alt_9, alt_10
ccc9c027 1152 };
252b5132 1153
76bc74dc
L		 1154 /* Only align for at least a positive non-zero boundary. */
1155 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1156 return;
3e73aa7c 1157
ccc9c027
L		 1158 /* We need to decide which NOP sequence to use for 32bit and
1159 64bit. When -mtune= is used:
4eed87de 1160
76bc74dc
L		 1161 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1162 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1163 2. For the rest, alt_patt will be used.
1164
1165 When -mtune= isn't used, alt_patt will be used if
22109423 1166 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1167 be used.
ccc9c027
L		 1168
1169 When -march= or .arch is used, we can't use anything beyond
1170 cpu_arch_isa_flags. */
1171
1172 if (flag_code == CODE_16BIT)
1173 {
ccc9c027 1174 if (count > 8)
33fef721 1175 {
76bc74dc
L		 1176 memcpy (fragP->fr_literal + fragP->fr_fix,
1177 jump_31, count);
1178 /* Adjust jump offset. */
1179 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1180 }
76bc74dc
L		 1181 else
1182 memcpy (fragP->fr_literal + fragP->fr_fix,
1183 f16_patt[count - 1], count);
252b5132 1184 }
33fef721 1185 else
ccc9c027
L		 1186 {
1187 const char *const *patt = NULL;
1188
fbf3f584 1189 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1190 {
1191 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1192 switch (cpu_arch_tune)
1193 {
1194 case PROCESSOR_UNKNOWN:
1195 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1196 optimize with nops. */
1197 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1198 patt = alt_patt;
ccc9c027
L		 1199 else
1200 patt = f32_patt;
1201 break;
ccc9c027
L		 1202 case PROCESSOR_PENTIUM4:
1203 case PROCESSOR_NOCONA:
ef05d495 1204 case PROCESSOR_CORE:
76bc74dc 1205 case PROCESSOR_CORE2:
bd5295b2 1206 case PROCESSOR_COREI7:
3632d14b 1207 case PROCESSOR_L1OM:
7a9068fe 1208 case PROCESSOR_K1OM:
76bc74dc 1209 case PROCESSOR_GENERIC64:
ccc9c027
L		 1210 case PROCESSOR_K6:
1211 case PROCESSOR_ATHLON:
1212 case PROCESSOR_K8:
4eed87de 1213 case PROCESSOR_AMDFAM10:
8aedb9fe 1214 case PROCESSOR_BD:
029f3522 1215 case PROCESSOR_ZNVER:
7b458c12 1216 case PROCESSOR_BT:
80b8656c 1217 patt = alt_patt;
ccc9c027 1218 break;
76bc74dc 1219 case PROCESSOR_I386:
ccc9c027
L		 1220 case PROCESSOR_I486:
1221 case PROCESSOR_PENTIUM:
2dde1948 1222 case PROCESSOR_PENTIUMPRO:
81486035 1223 case PROCESSOR_IAMCU:
ccc9c027
L		 1224 case PROCESSOR_GENERIC32:
1225 patt = f32_patt;
1226 break;
4eed87de 1227 }
ccc9c027
L		 1228 }
1229 else
1230 {
fbf3f584 1231 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1232 {
1233 case PROCESSOR_UNKNOWN:
e6a14101 1234 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1235 PROCESSOR_UNKNOWN. */
1236 abort ();
1237 break;
1238
76bc74dc 1239 case PROCESSOR_I386:
ccc9c027
L		 1240 case PROCESSOR_I486:
1241 case PROCESSOR_PENTIUM:
81486035 1242 case PROCESSOR_IAMCU:
ccc9c027
L		 1243 case PROCESSOR_K6:
1244 case PROCESSOR_ATHLON:
1245 case PROCESSOR_K8:
4eed87de 1246 case PROCESSOR_AMDFAM10:
8aedb9fe 1247 case PROCESSOR_BD:
029f3522 1248 case PROCESSOR_ZNVER:
7b458c12 1249 case PROCESSOR_BT:
ccc9c027
L		 1250 case PROCESSOR_GENERIC32:
1251 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1252 with nops. */
1253 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1254 patt = alt_patt;
ccc9c027
L		 1255 else
1256 patt = f32_patt;
1257 break;
76bc74dc
L		 1258 case PROCESSOR_PENTIUMPRO:
1259 case PROCESSOR_PENTIUM4:
1260 case PROCESSOR_NOCONA:
1261 case PROCESSOR_CORE:
ef05d495 1262 case PROCESSOR_CORE2:
bd5295b2 1263 case PROCESSOR_COREI7:
3632d14b 1264 case PROCESSOR_L1OM:
7a9068fe 1265 case PROCESSOR_K1OM:
22109423 1266 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1267 patt = alt_patt;
ccc9c027
L		 1268 else
1269 patt = f32_patt;
1270 break;
1271 case PROCESSOR_GENERIC64:
80b8656c 1272 patt = alt_patt;
ccc9c027 1273 break;
4eed87de 1274 }
ccc9c027
L		 1275 }
1276
76bc74dc
L		 1277 if (patt == f32_patt)
1278 {
1279 /* If the padding is less than 15 bytes, we use the normal
1280 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1281 its offset. */
1282 int limit;
76ba9986 1283
711eedef
L		 1284 /* For 64bit, the limit is 3 bytes. */
1285 if (flag_code == CODE_64BIT
1286 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1287 limit = 3;
1288 else
1289 limit = 15;
1290 if (count < limit)
76bc74dc
L		 1291 memcpy (fragP->fr_literal + fragP->fr_fix,
1292 patt[count - 1], count);
1293 else
1294 {
1295 memcpy (fragP->fr_literal + fragP->fr_fix,
1296 jump_31, count);
1297 /* Adjust jump offset. */
1298 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1299 }
1300 }
1301 else
1302 {
80b8656c
L		 1303 /* Maximum length of an instruction is 10 byte. If the
1304 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1305 we have to break it into smaller pieces. */
1306 int padding = count;
80b8656c 1307 while (padding > 10)
76bc74dc 1308 {
80b8656c 1309 padding -= 10;
76bc74dc 1310 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1311 patt [9], 10);
76bc74dc
L		 1312 }
1313
1314 if (padding)
1315 memcpy (fragP->fr_literal + fragP->fr_fix,
1316 patt [padding - 1], padding);
1317 }
ccc9c027 1318 }
33fef721 1319 fragP->fr_var = count;
252b5132
RH		 1320}
1321
c6fb90c8 1322static INLINE int
0dfbf9d7 1323operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1324{
0dfbf9d7 1325 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1326 {
1327 case 3:
0dfbf9d7 1328 if (x->array[2])
c6fb90c8
L		 1329 return 0;
1330 case 2:
0dfbf9d7 1331 if (x->array[1])
c6fb90c8
L		 1332 return 0;
1333 case 1:
0dfbf9d7 1334 return !x->array[0];
c6fb90c8
L		 1335 default:
1336 abort ();
1337 }
40fb9820
L		 1338}
1339
c6fb90c8 1340static INLINE void
0dfbf9d7 1341operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1342{
0dfbf9d7 1343 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1344 {
1345 case 3:
0dfbf9d7 1346 x->array[2] = v;
c6fb90c8 1347 case 2:
0dfbf9d7 1348 x->array[1] = v;
c6fb90c8 1349 case 1:
0dfbf9d7 1350 x->array[0] = v;
c6fb90c8
L		 1351 break;
1352 default:
1353 abort ();
1354 }
1355}
40fb9820 1356
c6fb90c8 1357static INLINE int
0dfbf9d7
L		 1358operand_type_equal (const union i386_operand_type *x,
1359 const union i386_operand_type *y)
c6fb90c8 1360{
0dfbf9d7 1361 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1362 {
1363 case 3:
0dfbf9d7 1364 if (x->array[2] != y->array[2])
c6fb90c8
L		 1365 return 0;
1366 case 2:
0dfbf9d7 1367 if (x->array[1] != y->array[1])
c6fb90c8
L		 1368 return 0;
1369 case 1:
0dfbf9d7 1370 return x->array[0] == y->array[0];
c6fb90c8
L		 1371 break;
1372 default:
1373 abort ();
1374 }
1375}
40fb9820 1376
0dfbf9d7
L		 1377static INLINE int
1378cpu_flags_all_zero (const union i386_cpu_flags *x)
1379{
1380 switch (ARRAY_SIZE(x->array))
1381 {
1382 case 3:
1383 if (x->array[2])
1384 return 0;
1385 case 2:
1386 if (x->array[1])
1387 return 0;
1388 case 1:
1389 return !x->array[0];
1390 default:
1391 abort ();
1392 }
1393}
1394
0dfbf9d7
L		 1395static INLINE int
1396cpu_flags_equal (const union i386_cpu_flags *x,
1397 const union i386_cpu_flags *y)
1398{
1399 switch (ARRAY_SIZE(x->array))
1400 {
1401 case 3:
1402 if (x->array[2] != y->array[2])
1403 return 0;
1404 case 2:
1405 if (x->array[1] != y->array[1])
1406 return 0;
1407 case 1:
1408 return x->array[0] == y->array[0];
1409 break;
1410 default:
1411 abort ();
1412 }
1413}
c6fb90c8
L		 1414
1415static INLINE int
1416cpu_flags_check_cpu64 (i386_cpu_flags f)
1417{
1418 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1419 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1420}
1421
c6fb90c8
L		 1422static INLINE i386_cpu_flags
1423cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1424{
c6fb90c8
L		 1425 switch (ARRAY_SIZE (x.array))
1426 {
1427 case 3:
1428 x.array [2] &= y.array [2];
1429 case 2:
1430 x.array [1] &= y.array [1];
1431 case 1:
1432 x.array [0] &= y.array [0];
1433 break;
1434 default:
1435 abort ();
1436 }
1437 return x;
1438}
40fb9820 1439
c6fb90c8
L		 1440static INLINE i386_cpu_flags
1441cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1442{
c6fb90c8 1443 switch (ARRAY_SIZE (x.array))
40fb9820 1444 {
c6fb90c8
L		 1445 case 3:
1446 x.array [2] |= y.array [2];
1447 case 2:
1448 x.array [1] |= y.array [1];
1449 case 1:
1450 x.array [0] |= y.array [0];
40fb9820
L		 1451 break;
1452 default:
1453 abort ();
1454 }
40fb9820
L		 1455 return x;
1456}
1457
309d3373
JB		 1458static INLINE i386_cpu_flags
1459cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1460{
1461 switch (ARRAY_SIZE (x.array))
1462 {
1463 case 3:
1464 x.array [2] &= ~y.array [2];
1465 case 2:
1466 x.array [1] &= ~y.array [1];
1467 case 1:
1468 x.array [0] &= ~y.array [0];
1469 break;
1470 default:
1471 abort ();
1472 }
1473 return x;
1474}
1475
81486035
L		 1476static int
1477valid_iamcu_cpu_flags (const i386_cpu_flags *flags)
1478{
1479 if (cpu_arch_isa == PROCESSOR_IAMCU)
1480 {
1481 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_COMPAT_FLAGS;
1482 i386_cpu_flags compat_flags;
1483 compat_flags = cpu_flags_and_not (*flags, iamcu_flags);
1484 return cpu_flags_all_zero (&compat_flags);
1485 }
1486 else
1487 return 1;
1488}
1489
c0f3af97
L		 1490#define CPU_FLAGS_ARCH_MATCH 0x1
1491#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1492#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1493#define CPU_FLAGS_PCLMUL_MATCH 0x8
1494#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1495
a5ff0eb2 1496#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1497 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1498 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1499#define CPU_FLAGS_PERFECT_MATCH \
1500 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1501
1502/* Return CPU flags match bits. */
3629bb00 1503
40fb9820 1504static int
d3ce72d0 1505cpu_flags_match (const insn_template *t)
40fb9820 1506{
c0f3af97
L		 1507 i386_cpu_flags x = t->cpu_flags;
1508 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1509
1510 x.bitfield.cpu64 = 0;
1511 x.bitfield.cpuno64 = 0;
1512
0dfbf9d7 1513 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1514 {
1515 /* This instruction is available on all archs. */
1516 match |= CPU_FLAGS_32BIT_MATCH;
1517 }
3629bb00
L		 1518 else
1519 {
c0f3af97 1520 /* This instruction is available only on some archs. */
3629bb00
L		 1521 i386_cpu_flags cpu = cpu_arch_flags;
1522
1523 cpu.bitfield.cpu64 = 0;
1524 cpu.bitfield.cpuno64 = 0;
1525 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1526 if (!cpu_flags_all_zero (&cpu))
1527 {
a5ff0eb2
L		 1528 if (x.bitfield.cpuavx)
1529 {
ce2f5b3c 1530 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1531 if (cpu.bitfield.cpuavx)
1532 {
1533 /* Check SSE2AVX. */
1534 if (!t->opcode_modifier.sse2avx|| sse2avx)
1535 {
1536 match |= (CPU_FLAGS_ARCH_MATCH
1537 | CPU_FLAGS_AVX_MATCH);
1538 /* Check AES. */
1539 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1540 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1541 /* Check PCLMUL. */
1542 if (!x.bitfield.cpupclmul
1543 || cpu.bitfield.cpupclmul)
1544 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1545 }
1546 }
1547 else
1548 match |= CPU_FLAGS_ARCH_MATCH;
1549 }
1550 else
c0f3af97
L		 1551 match |= CPU_FLAGS_32BIT_MATCH;
1552 }
3629bb00 1553 }
c0f3af97 1554 return match;
40fb9820
L		 1555}
1556
c6fb90c8
L		 1557static INLINE i386_operand_type
1558operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1559{
c6fb90c8
L		 1560 switch (ARRAY_SIZE (x.array))
1561 {
1562 case 3:
1563 x.array [2] &= y.array [2];
1564 case 2:
1565 x.array [1] &= y.array [1];
1566 case 1:
1567 x.array [0] &= y.array [0];
1568 break;
1569 default:
1570 abort ();
1571 }
1572 return x;
40fb9820
L		 1573}
1574
c6fb90c8
L		 1575static INLINE i386_operand_type
1576operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1577{
c6fb90c8 1578 switch (ARRAY_SIZE (x.array))
40fb9820 1579 {
c6fb90c8
L		 1580 case 3:
1581 x.array [2] |= y.array [2];
1582 case 2:
1583 x.array [1] |= y.array [1];
1584 case 1:
1585 x.array [0] |= y.array [0];
40fb9820
L		 1586 break;
1587 default:
1588 abort ();
1589 }
c6fb90c8
L		 1590 return x;
1591}
40fb9820 1592
c6fb90c8
L		 1593static INLINE i386_operand_type
1594operand_type_xor (i386_operand_type x, i386_operand_type y)
1595{
1596 switch (ARRAY_SIZE (x.array))
1597 {
1598 case 3:
1599 x.array [2] ^= y.array [2];
1600 case 2:
1601 x.array [1] ^= y.array [1];
1602 case 1:
1603 x.array [0] ^= y.array [0];
1604 break;
1605 default:
1606 abort ();
1607 }
40fb9820
L		 1608 return x;
1609}
1610
1611static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1612static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1613static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1614static const i386_operand_type inoutportreg
1615 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1616static const i386_operand_type reg16_inoutportreg
1617 = OPERAND_TYPE_REG16_INOUTPORTREG;
1618static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1619static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1620static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1621static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1622static const i386_operand_type anydisp
1623 = OPERAND_TYPE_ANYDISP;
40fb9820 1624static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1625static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1626static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1627static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1628static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1629static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1630static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1631static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1632static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1633static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1634static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1635static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1636static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1637static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1638
1639enum operand_type
1640{
1641 reg,
40fb9820
L		 1642 imm,
1643 disp,
1644 anymem
1645};
1646
c6fb90c8 1647static INLINE int
40fb9820
L		 1648operand_type_check (i386_operand_type t, enum operand_type c)
1649{
1650 switch (c)
1651 {
1652 case reg:
1653 return (t.bitfield.reg8
1654 || t.bitfield.reg16
1655 || t.bitfield.reg32
1656 || t.bitfield.reg64);
1657
40fb9820
L		 1658 case imm:
1659 return (t.bitfield.imm8
1660 || t.bitfield.imm8s
1661 || t.bitfield.imm16
1662 || t.bitfield.imm32
1663 || t.bitfield.imm32s
1664 || t.bitfield.imm64);
1665
1666 case disp:
1667 return (t.bitfield.disp8
1668 || t.bitfield.disp16
1669 || t.bitfield.disp32
1670 || t.bitfield.disp32s
1671 || t.bitfield.disp64);
1672
1673 case anymem:
1674 return (t.bitfield.disp8
1675 || t.bitfield.disp16
1676 || t.bitfield.disp32
1677 || t.bitfield.disp32s
1678 || t.bitfield.disp64
1679 || t.bitfield.baseindex);
1680
1681 default:
1682 abort ();
1683 }
2cfe26b6
AM		 1684
1685 return 0;
40fb9820
L		 1686}
1687
5c07affc
L		 1688/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1689 operand J for instruction template T. */
1690
1691static INLINE int
d3ce72d0 1692match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1693{
1694 return !((i.types[j].bitfield.byte
1695 && !t->operand_types[j].bitfield.byte)
1696 || (i.types[j].bitfield.word
1697 && !t->operand_types[j].bitfield.word)
1698 || (i.types[j].bitfield.dword
1699 && !t->operand_types[j].bitfield.dword)
1700 || (i.types[j].bitfield.qword
1701 && !t->operand_types[j].bitfield.qword));
1702}
1703
1704/* Return 1 if there is no conflict in any size on operand J for
1705 instruction template T. */
1706
1707static INLINE int
d3ce72d0 1708match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1709{
1710 return (match_reg_size (t, j)
1711 && !((i.types[j].bitfield.unspecified
af508cb9 1712 && !i.broadcast
5c07affc
L		 1713 && !t->operand_types[j].bitfield.unspecified)
1714 || (i.types[j].bitfield.fword
1715 && !t->operand_types[j].bitfield.fword)
1716 || (i.types[j].bitfield.tbyte
1717 && !t->operand_types[j].bitfield.tbyte)
1718 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1719 && !t->operand_types[j].bitfield.xmmword)
1720 || (i.types[j].bitfield.ymmword
43234a1e
L		 1721 && !t->operand_types[j].bitfield.ymmword)
1722 || (i.types[j].bitfield.zmmword
1723 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1724}
1725
1726/* Return 1 if there is no size conflict on any operands for
1727 instruction template T. */
1728
1729static INLINE int
d3ce72d0 1730operand_size_match (const insn_template *t)
5c07affc
L		 1731{
1732 unsigned int j;
1733 int match = 1;
1734
1735 /* Don't check jump instructions. */
1736 if (t->opcode_modifier.jump
1737 || t->opcode_modifier.jumpbyte
1738 || t->opcode_modifier.jumpdword
1739 || t->opcode_modifier.jumpintersegment)
1740 return match;
1741
1742 /* Check memory and accumulator operand size. */
1743 for (j = 0; j < i.operands; j++)
1744 {
1745 if (t->operand_types[j].bitfield.anysize)
1746 continue;
1747
1748 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1749 {
1750 match = 0;
1751 break;
1752 }
1753
1754 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1755 {
1756 match = 0;
1757 break;
1758 }
1759 }
1760
891edac4 1761 if (match)
5c07affc 1762 return match;
891edac4
L		 1763 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1764 {
1765mismatch:
86e026a4 1766 i.error = operand_size_mismatch;
891edac4
L		 1767 return 0;
1768 }
5c07affc
L		 1769
1770 /* Check reverse. */
9c2799c2 1771 gas_assert (i.operands == 2);
5c07affc
L		 1772
1773 match = 1;
1774 for (j = 0; j < 2; j++)
1775 {
1776 if (t->operand_types[j].bitfield.acc
1777 && !match_reg_size (t, j ? 0 : 1))
891edac4 1778 goto mismatch;
5c07affc
L		 1779
1780 if (i.types[j].bitfield.mem
1781 && !match_mem_size (t, j ? 0 : 1))
891edac4 1782 goto mismatch;
5c07affc
L		 1783 }
1784
1785 return match;
1786}
1787
c6fb90c8 1788static INLINE int
40fb9820
L		 1789operand_type_match (i386_operand_type overlap,
1790 i386_operand_type given)
1791{
1792 i386_operand_type temp = overlap;
1793
1794 temp.bitfield.jumpabsolute = 0;
7d5e4556 1795 temp.bitfield.unspecified = 0;
5c07affc
L		 1796 temp.bitfield.byte = 0;
1797 temp.bitfield.word = 0;
1798 temp.bitfield.dword = 0;
1799 temp.bitfield.fword = 0;
1800 temp.bitfield.qword = 0;
1801 temp.bitfield.tbyte = 0;
1802 temp.bitfield.xmmword = 0;
c0f3af97 1803 temp.bitfield.ymmword = 0;
43234a1e 1804 temp.bitfield.zmmword = 0;
0dfbf9d7 1805 if (operand_type_all_zero (&temp))
891edac4 1806 goto mismatch;
40fb9820 1807
891edac4
L		 1808 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1809 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1810 return 1;
1811
1812mismatch:
a65babc9 1813 i.error = operand_type_mismatch;
891edac4 1814 return 0;
40fb9820
L		 1815}
1816
7d5e4556 1817/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1818 unless the expected operand type register overlap is null.
1819 Note that Acc in a template matches every size of reg. */
1820
c6fb90c8 1821static INLINE int
40fb9820
L		 1822operand_type_register_match (i386_operand_type m0,
1823 i386_operand_type g0,
1824 i386_operand_type t0,
1825 i386_operand_type m1,
1826 i386_operand_type g1,
1827 i386_operand_type t1)
1828{
1829 if (!operand_type_check (g0, reg))
1830 return 1;
1831
1832 if (!operand_type_check (g1, reg))
1833 return 1;
1834
1835 if (g0.bitfield.reg8 == g1.bitfield.reg8
1836 && g0.bitfield.reg16 == g1.bitfield.reg16
1837 && g0.bitfield.reg32 == g1.bitfield.reg32
1838 && g0.bitfield.reg64 == g1.bitfield.reg64)
1839 return 1;
1840
1841 if (m0.bitfield.acc)
1842 {
1843 t0.bitfield.reg8 = 1;
1844 t0.bitfield.reg16 = 1;
1845 t0.bitfield.reg32 = 1;
1846 t0.bitfield.reg64 = 1;
1847 }
1848
1849 if (m1.bitfield.acc)
1850 {
1851 t1.bitfield.reg8 = 1;
1852 t1.bitfield.reg16 = 1;
1853 t1.bitfield.reg32 = 1;
1854 t1.bitfield.reg64 = 1;
1855 }
1856
891edac4
L		 1857 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1858 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1859 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1860 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1861 return 1;
1862
a65babc9 1863 i.error = register_type_mismatch;
891edac4
L		 1864
1865 return 0;
40fb9820
L		 1866}
1867
4c692bc7
JB		 1868static INLINE unsigned int
1869register_number (const reg_entry *r)
1870{
1871 unsigned int nr = r->reg_num;
1872
1873 if (r->reg_flags & RegRex)
1874 nr += 8;
1875
1876 return nr;
1877}
1878
252b5132 1879static INLINE unsigned int
40fb9820 1880mode_from_disp_size (i386_operand_type t)
252b5132 1881{
43234a1e 1882 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1883 return 1;
1884 else if (t.bitfield.disp16
1885 || t.bitfield.disp32
1886 || t.bitfield.disp32s)
1887 return 2;
1888 else
1889 return 0;
252b5132
RH		 1890}
1891
1892static INLINE int
65879393 1893fits_in_signed_byte (addressT num)
252b5132 1894{
65879393 1895 return num + 0x80 <= 0xff;
47926f60 1896}
252b5132
RH		 1897
1898static INLINE int
65879393 1899fits_in_unsigned_byte (addressT num)
252b5132 1900{
65879393 1901 return num <= 0xff;
47926f60 1902}
252b5132
RH		 1903
1904static INLINE int
65879393 1905fits_in_unsigned_word (addressT num)
252b5132 1906{
65879393 1907 return num <= 0xffff;
47926f60 1908}
252b5132
RH		 1909
1910static INLINE int
65879393 1911fits_in_signed_word (addressT num)
252b5132 1912{
65879393 1913 return num + 0x8000 <= 0xffff;
47926f60 1914}
2a962e6d 1915
3e73aa7c 1916static INLINE int
65879393 1917fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1918{
1919#ifndef BFD64
1920 return 1;
1921#else
65879393 1922 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1923#endif
1924} /* fits_in_signed_long() */
2a962e6d 1925
3e73aa7c 1926static INLINE int
65879393 1927fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1928{
1929#ifndef BFD64
1930 return 1;
1931#else
65879393 1932 return num <= 0xffffffff;
3e73aa7c
JH		 1933#endif
1934} /* fits_in_unsigned_long() */
252b5132 1935
43234a1e
L		 1936static INLINE int
1937fits_in_vec_disp8 (offsetT num)
1938{
1939 int shift = i.memshift;
1940 unsigned int mask;
1941
1942 if (shift == -1)
1943 abort ();
1944
1945 mask = (1 << shift) - 1;
1946
1947 /* Return 0 if NUM isn't properly aligned. */
1948 if ((num & mask))
1949 return 0;
1950
1951 /* Check if NUM will fit in 8bit after shift. */
1952 return fits_in_signed_byte (num >> shift);
1953}
1954
a683cc34
SP		 1955static INLINE int
1956fits_in_imm4 (offsetT num)
1957{
1958 return (num & 0xf) == num;
1959}
1960
40fb9820 1961static i386_operand_type
e3bb37b5 1962smallest_imm_type (offsetT num)
252b5132 1963{
40fb9820 1964 i386_operand_type t;
7ab9ffdd 1965
0dfbf9d7 1966 operand_type_set (&t, 0);
40fb9820
L		 1967 t.bitfield.imm64 = 1;
1968
1969 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1970 {
1971 /* This code is disabled on the 486 because all the Imm1 forms
1972 in the opcode table are slower on the i486. They're the
1973 versions with the implicitly specified single-position
1974 displacement, which has another syntax if you really want to
1975 use that form. */
40fb9820
L		 1976 t.bitfield.imm1 = 1;
1977 t.bitfield.imm8 = 1;
1978 t.bitfield.imm8s = 1;
1979 t.bitfield.imm16 = 1;
1980 t.bitfield.imm32 = 1;
1981 t.bitfield.imm32s = 1;
1982 }
1983 else if (fits_in_signed_byte (num))
1984 {
1985 t.bitfield.imm8 = 1;
1986 t.bitfield.imm8s = 1;
1987 t.bitfield.imm16 = 1;
1988 t.bitfield.imm32 = 1;
1989 t.bitfield.imm32s = 1;
1990 }
1991 else if (fits_in_unsigned_byte (num))
1992 {
1993 t.bitfield.imm8 = 1;
1994 t.bitfield.imm16 = 1;
1995 t.bitfield.imm32 = 1;
1996 t.bitfield.imm32s = 1;
1997 }
1998 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1999 {
2000 t.bitfield.imm16 = 1;
2001 t.bitfield.imm32 = 1;
2002 t.bitfield.imm32s = 1;
2003 }
2004 else if (fits_in_signed_long (num))
2005 {
2006 t.bitfield.imm32 = 1;
2007 t.bitfield.imm32s = 1;
2008 }
2009 else if (fits_in_unsigned_long (num))
2010 t.bitfield.imm32 = 1;
2011
2012 return t;
47926f60 2013}
252b5132 2014
847f7ad4 2015static offsetT
e3bb37b5 2016offset_in_range (offsetT val, int size)
847f7ad4 2017{
508866be 2018 addressT mask;
ba2adb93 2019
847f7ad4
AM		 2020 switch (size)
2021 {
508866be
L		 2022 case 1: mask = ((addressT) 1 << 8) - 1; break;
2023 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2024 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2025#ifdef BFD64
2026 case 8: mask = ((addressT) 2 << 63) - 1; break;
2027#endif
47926f60 2028 default: abort ();
847f7ad4
AM		 2029 }
2030
9de868bf
L		 2031#ifdef BFD64
2032 /* If BFD64, sign extend val for 32bit address mode. */
2033 if (flag_code != CODE_64BIT
2034 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2035 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2036 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2037#endif
ba2adb93 2038
47926f60 2039 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2040 {
2041 char buf1[40], buf2[40];
2042
2043 sprint_value (buf1, val);
2044 sprint_value (buf2, val & mask);
2045 as_warn (_("%s shortened to %s"), buf1, buf2);
2046 }
2047 return val & mask;
2048}
2049
c32fa91d
L		 2050enum PREFIX_GROUP
2051{
2052 PREFIX_EXIST = 0,
2053 PREFIX_LOCK,
2054 PREFIX_REP,
2055 PREFIX_OTHER
2056};
2057
2058/* Returns
2059 a. PREFIX_EXIST if attempting to add a prefix where one from the
2060 same class already exists.
2061 b. PREFIX_LOCK if lock prefix is added.
2062 c. PREFIX_REP if rep/repne prefix is added.
2063 d. PREFIX_OTHER if other prefix is added.
2064 */
2065
2066static enum PREFIX_GROUP
e3bb37b5 2067add_prefix (unsigned int prefix)
252b5132 2068{
c32fa91d 2069 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2070 unsigned int q;
252b5132 2071
29b0f896
AM		 2072 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2073 && flag_code == CODE_64BIT)
b1905489 2074 {
161a04f6
L		 2075 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2076 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2077 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2078 ret = PREFIX_EXIST;
b1905489
JB		 2079 q = REX_PREFIX;
2080 }
3e73aa7c 2081 else
b1905489
JB		 2082 {
2083 switch (prefix)
2084 {
2085 default:
2086 abort ();
2087
2088 case CS_PREFIX_OPCODE:
2089 case DS_PREFIX_OPCODE:
2090 case ES_PREFIX_OPCODE:
2091 case FS_PREFIX_OPCODE:
2092 case GS_PREFIX_OPCODE:
2093 case SS_PREFIX_OPCODE:
2094 q = SEG_PREFIX;
2095 break;
2096
2097 case REPNE_PREFIX_OPCODE:
2098 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2099 q = REP_PREFIX;
2100 ret = PREFIX_REP;
2101 break;
2102
b1905489 2103 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2104 q = LOCK_PREFIX;
2105 ret = PREFIX_LOCK;
b1905489
JB		 2106 break;
2107
2108 case FWAIT_OPCODE:
2109 q = WAIT_PREFIX;
2110 break;
2111
2112 case ADDR_PREFIX_OPCODE:
2113 q = ADDR_PREFIX;
2114 break;
2115
2116 case DATA_PREFIX_OPCODE:
2117 q = DATA_PREFIX;
2118 break;
2119 }
2120 if (i.prefix[q] != 0)
c32fa91d 2121 ret = PREFIX_EXIST;
b1905489 2122 }
252b5132 2123
b1905489 2124 if (ret)
252b5132 2125 {
b1905489
JB		 2126 if (!i.prefix[q])
2127 ++i.prefixes;
2128 i.prefix[q] |= prefix;
252b5132 2129 }
b1905489
JB		 2130 else
2131 as_bad (_("same type of prefix used twice"));
252b5132 2132
252b5132
RH		 2133 return ret;
2134}
2135
2136static void
78f12dd3 2137update_code_flag (int value, int check)
eecb386c 2138{
78f12dd3
L		 2139 PRINTF_LIKE ((*as_error));
2140
1e9cc1c2 2141 flag_code = (enum flag_code) value;
40fb9820
L		 2142 if (flag_code == CODE_64BIT)
2143 {
2144 cpu_arch_flags.bitfield.cpu64 = 1;
2145 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2146 }
2147 else
2148 {
2149 cpu_arch_flags.bitfield.cpu64 = 0;
2150 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2151 }
2152 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2153 {
78f12dd3
L		 2154 if (check)
2155 as_error = as_fatal;
2156 else
2157 as_error = as_bad;
2158 (*as_error) (_("64bit mode not supported on `%s'."),
2159 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2160 }
40fb9820 2161 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2162 {
78f12dd3
L		 2163 if (check)
2164 as_error = as_fatal;
2165 else
2166 as_error = as_bad;
2167 (*as_error) (_("32bit mode not supported on `%s'."),
2168 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2169 }
eecb386c
AM		 2170 stackop_size = '\0';
2171}
2172
78f12dd3
L		 2173static void
2174set_code_flag (int value)
2175{
2176 update_code_flag (value, 0);
2177}
2178
eecb386c 2179static void
e3bb37b5 2180set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2181{
1e9cc1c2 2182 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2183 if (flag_code != CODE_16BIT)
2184 abort ();
2185 cpu_arch_flags.bitfield.cpu64 = 0;
2186 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2187 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2188}
2189
2190static void
e3bb37b5 2191set_intel_syntax (int syntax_flag)
252b5132
RH		 2192{
2193 /* Find out if register prefixing is specified. */
2194 int ask_naked_reg = 0;
2195
2196 SKIP_WHITESPACE ();
29b0f896 2197 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2198 {
2199 char *string = input_line_pointer;
2200 int e = get_symbol_end ();
2201
47926f60 2202 if (strcmp (string, "prefix") == 0)
252b5132 2203 ask_naked_reg = 1;
47926f60 2204 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2205 ask_naked_reg = -1;
2206 else
d0b47220 2207 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2208 *input_line_pointer = e;
2209 }
2210 demand_empty_rest_of_line ();
c3332e24 2211
252b5132
RH		 2212 intel_syntax = syntax_flag;
2213
2214 if (ask_naked_reg == 0)
f86103b7
AM		 2215 allow_naked_reg = (intel_syntax
2216 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2217 else
2218 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2219
ee86248c 2220 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2221
e4a3b5a4 2222 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2223 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2224 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2225}
2226
1efbbeb4
L		 2227static void
2228set_intel_mnemonic (int mnemonic_flag)
2229{
e1d4d893 2230 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2231}
2232
db51cc60
L		 2233static void
2234set_allow_index_reg (int flag)
2235{
2236 allow_index_reg = flag;
2237}
2238
cb19c032 2239static void
7bab8ab5 2240set_check (int what)
cb19c032 2241{
7bab8ab5
JB		 2242 enum check_kind *kind;
2243 const char *str;
2244
2245 if (what)
2246 {
2247 kind = &operand_check;
2248 str = "operand";
2249 }
2250 else
2251 {
2252 kind = &sse_check;
2253 str = "sse";
2254 }
2255
cb19c032
L		 2256 SKIP_WHITESPACE ();
2257
2258 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2259 {
2260 char *string = input_line_pointer;
2261 int e = get_symbol_end ();
2262
2263 if (strcmp (string, "none") == 0)
7bab8ab5 2264 *kind = check_none;
cb19c032 2265 else if (strcmp (string, "warning") == 0)
7bab8ab5 2266 *kind = check_warning;
cb19c032 2267 else if (strcmp (string, "error") == 0)
7bab8ab5 2268 *kind = check_error;
cb19c032 2269 else
7bab8ab5 2270 as_bad (_("bad argument to %s_check directive."), str);
cb19c032
L		 2271 *input_line_pointer = e;
2272 }
2273 else
7bab8ab5 2274 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2275
2276 demand_empty_rest_of_line ();
2277}
2278
8a9036a4
L		 2279static void
2280check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2281 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2282{
2283#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2284 static const char *arch;
2285
2286 /* Intel LIOM is only supported on ELF. */
2287 if (!IS_ELF)
2288 return;
2289
2290 if (!arch)
2291 {
2292 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2293 use default_arch. */
2294 arch = cpu_arch_name;
2295 if (!arch)
2296 arch = default_arch;
2297 }
2298
81486035
L		 2299 /* If we are targeting Intel MCU, we must enable it. */
2300 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2301 || new_flag.bitfield.cpuiamcu)
2302 return;
2303
3632d14b 2304 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2305 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2306 || new_flag.bitfield.cpul1om)
8a9036a4 2307 return;
76ba9986 2308
7a9068fe
L		 2309 /* If we are targeting Intel K1OM, we must enable it. */
2310 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2311 || new_flag.bitfield.cpuk1om)
2312 return;
2313
8a9036a4
L		 2314 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2315#endif
2316}
2317
e413e4e9 2318static void
e3bb37b5 2319set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2320{
47926f60 2321 SKIP_WHITESPACE ();
e413e4e9 2322
29b0f896 2323 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2324 {
2325 char *string = input_line_pointer;
2326 int e = get_symbol_end ();
91d6fa6a 2327 unsigned int j;
40fb9820 2328 i386_cpu_flags flags;
e413e4e9 2329
91d6fa6a 2330 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2331 {
91d6fa6a 2332 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2333 {
91d6fa6a 2334 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2335
5c6af06e
JB		 2336 if (*string != '.')
2337 {
91d6fa6a 2338 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2339 cpu_sub_arch_name = NULL;
91d6fa6a 2340 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2341 if (flag_code == CODE_64BIT)
2342 {
2343 cpu_arch_flags.bitfield.cpu64 = 1;
2344 cpu_arch_flags.bitfield.cpuno64 = 0;
2345 }
2346 else
2347 {
2348 cpu_arch_flags.bitfield.cpu64 = 0;
2349 cpu_arch_flags.bitfield.cpuno64 = 1;
2350 }
91d6fa6a
NC		 2351 cpu_arch_isa = cpu_arch[j].type;
2352 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2353 if (!cpu_arch_tune_set)
2354 {
2355 cpu_arch_tune = cpu_arch_isa;
2356 cpu_arch_tune_flags = cpu_arch_isa_flags;
2357 }
5c6af06e
JB		 2358 break;
2359 }
40fb9820 2360
22109423 2361 if (!cpu_arch[j].negated)
309d3373 2362 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2363 cpu_arch[j].flags);
309d3373
JB		 2364 else
2365 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2366 cpu_arch[j].flags);
81486035
L		 2367
2368 if (!valid_iamcu_cpu_flags (&flags))
2369 as_fatal (_("`%s' isn't valid for Intel MCU"),
2370 cpu_arch[j].name);
2371 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2372 {
6305a203
L		 2373 if (cpu_sub_arch_name)
2374 {
2375 char *name = cpu_sub_arch_name;
2376 cpu_sub_arch_name = concat (name,
91d6fa6a 2377 cpu_arch[j].name,
1bf57e9f 2378 (const char *) NULL);
6305a203
L		 2379 free (name);
2380 }
2381 else
91d6fa6a 2382 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2383 cpu_arch_flags = flags;
a586129e 2384 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2385 }
2386 *input_line_pointer = e;
2387 demand_empty_rest_of_line ();
2388 return;
e413e4e9
AM		 2389 }
2390 }
91d6fa6a 2391 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2392 as_bad (_("no such architecture: `%s'"), string);
2393
2394 *input_line_pointer = e;
2395 }
2396 else
2397 as_bad (_("missing cpu architecture"));
2398
fddf5b5b
AM		 2399 no_cond_jump_promotion = 0;
2400 if (*input_line_pointer == ','
29b0f896 2401 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2402 {
2403 char *string = ++input_line_pointer;
2404 int e = get_symbol_end ();
2405
2406 if (strcmp (string, "nojumps") == 0)
2407 no_cond_jump_promotion = 1;
2408 else if (strcmp (string, "jumps") == 0)
2409 ;
2410 else
2411 as_bad (_("no such architecture modifier: `%s'"), string);
2412
2413 *input_line_pointer = e;
2414 }
2415
e413e4e9
AM		 2416 demand_empty_rest_of_line ();
2417}
2418
8a9036a4
L		 2419enum bfd_architecture
2420i386_arch (void)
2421{
3632d14b 2422 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2423 {
2424 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2425 || flag_code != CODE_64BIT)
2426 as_fatal (_("Intel L1OM is 64bit ELF only"));
2427 return bfd_arch_l1om;
2428 }
7a9068fe
L		 2429 else if (cpu_arch_isa == PROCESSOR_K1OM)
2430 {
2431 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2432 || flag_code != CODE_64BIT)
2433 as_fatal (_("Intel K1OM is 64bit ELF only"));
2434 return bfd_arch_k1om;
2435 }
81486035
L		 2436 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2437 {
2438 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2439 || flag_code == CODE_64BIT)
2440 as_fatal (_("Intel MCU is 32bit ELF only"));
2441 return bfd_arch_iamcu;
2442 }
8a9036a4
L		 2443 else
2444 return bfd_arch_i386;
2445}
2446
b9d79e03 2447unsigned long
7016a5d5 2448i386_mach (void)
b9d79e03 2449{
351f65ca 2450 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2451 {
3632d14b 2452 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2453 {
351f65ca
L		 2454 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2455 || default_arch[6] != '\0')
8a9036a4
L		 2456 as_fatal (_("Intel L1OM is 64bit ELF only"));
2457 return bfd_mach_l1om;
2458 }
7a9068fe
L		 2459 else if (cpu_arch_isa == PROCESSOR_K1OM)
2460 {
2461 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2462 || default_arch[6] != '\0')
2463 as_fatal (_("Intel K1OM is 64bit ELF only"));
2464 return bfd_mach_k1om;
2465 }
351f65ca 2466 else if (default_arch[6] == '\0')
8a9036a4 2467 return bfd_mach_x86_64;
351f65ca
L		 2468 else
2469 return bfd_mach_x64_32;
8a9036a4 2470 }
5197d474
L		 2471 else if (!strcmp (default_arch, "i386")
2472 || !strcmp (default_arch, "iamcu"))
81486035
L		 2473 {
2474 if (cpu_arch_isa == PROCESSOR_IAMCU)
2475 {
2476 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2477 as_fatal (_("Intel MCU is 32bit ELF only"));
2478 return bfd_mach_i386_iamcu;
2479 }
2480 else
2481 return bfd_mach_i386_i386;
2482 }
b9d79e03 2483 else
2b5d6a91 2484 as_fatal (_("unknown architecture"));
b9d79e03 2485}
b9d79e03 2486\f
252b5132 2487void
7016a5d5 2488md_begin (void)
252b5132
RH		 2489{
2490 const char *hash_err;
2491
47926f60 2492 /* Initialize op_hash hash table. */
252b5132
RH		 2493 op_hash = hash_new ();
2494
2495 {
d3ce72d0 2496 const insn_template *optab;
29b0f896 2497 templates *core_optab;
252b5132 2498
47926f60
KH		 2499 /* Setup for loop. */
2500 optab = i386_optab;
252b5132
RH		 2501 core_optab = (templates *) xmalloc (sizeof (templates));
2502 core_optab->start = optab;
2503
2504 while (1)
2505 {
2506 ++optab;
2507 if (optab->name == NULL
2508 || strcmp (optab->name, (optab - 1)->name) != 0)
2509 {
2510 /* different name --> ship out current template list;
47926f60 2511 add to hash table; & begin anew. */
252b5132
RH		 2512 core_optab->end = optab;
2513 hash_err = hash_insert (op_hash,
2514 (optab - 1)->name,
5a49b8ac 2515 (void *) core_optab);
252b5132
RH		 2516 if (hash_err)
2517 {
b37df7c4 2518 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2519 (optab - 1)->name,
2520 hash_err);
2521 }
2522 if (optab->name == NULL)
2523 break;
2524 core_optab = (templates *) xmalloc (sizeof (templates));
2525 core_optab->start = optab;
2526 }
2527 }
2528 }
2529
47926f60 2530 /* Initialize reg_hash hash table. */
252b5132
RH		 2531 reg_hash = hash_new ();
2532 {
29b0f896 2533 const reg_entry *regtab;
c3fe08fa 2534 unsigned int regtab_size = i386_regtab_size;
252b5132 2535
c3fe08fa 2536 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2537 {
5a49b8ac 2538 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2539 if (hash_err)
b37df7c4 2540 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2541 regtab->reg_name,
2542 hash_err);
252b5132
RH		 2543 }
2544 }
2545
47926f60 2546 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2547 {
29b0f896
AM		 2548 int c;
2549 char *p;
252b5132
RH		 2550
2551 for (c = 0; c < 256; c++)
2552 {
3882b010 2553 if (ISDIGIT (c))
252b5132
RH		 2554 {
2555 digit_chars[c] = c;
2556 mnemonic_chars[c] = c;
2557 register_chars[c] = c;
2558 operand_chars[c] = c;
2559 }
3882b010 2560 else if (ISLOWER (c))
252b5132
RH		 2561 {
2562 mnemonic_chars[c] = c;
2563 register_chars[c] = c;
2564 operand_chars[c] = c;
2565 }
3882b010 2566 else if (ISUPPER (c))
252b5132 2567 {
3882b010 2568 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2569 register_chars[c] = mnemonic_chars[c];
2570 operand_chars[c] = c;
2571 }
43234a1e
L		 2572 else if (c == '{' || c == '}')
2573 operand_chars[c] = c;
252b5132 2574
3882b010 2575 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2576 identifier_chars[c] = c;
2577 else if (c >= 128)
2578 {
2579 identifier_chars[c] = c;
2580 operand_chars[c] = c;
2581 }
2582 }
2583
2584#ifdef LEX_AT
2585 identifier_chars['@'] = '@';
32137342
NC		 2586#endif
2587#ifdef LEX_QM
2588 identifier_chars['?'] = '?';
2589 operand_chars['?'] = '?';
252b5132 2590#endif
252b5132 2591 digit_chars['-'] = '-';
c0f3af97 2592 mnemonic_chars['_'] = '_';
791fe849 2593 mnemonic_chars['-'] = '-';
0003779b 2594 mnemonic_chars['.'] = '.';
252b5132
RH		 2595 identifier_chars['_'] = '_';
2596 identifier_chars['.'] = '.';
2597
2598 for (p = operand_special_chars; *p != '\0'; p++)
2599 operand_chars[(unsigned char) *p] = *p;
2600 }
2601
a4447b93
RH		 2602 if (flag_code == CODE_64BIT)
2603 {
ca19b261
KT		 2604#if defined (OBJ_COFF) && defined (TE_PE)
2605 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2606 ? 32 : 16);
2607#else
a4447b93 2608 x86_dwarf2_return_column = 16;
ca19b261 2609#endif
61ff971f 2610 x86_cie_data_alignment = -8;
a4447b93
RH		 2611 }
2612 else
2613 {
2614 x86_dwarf2_return_column = 8;
2615 x86_cie_data_alignment = -4;
2616 }
252b5132
RH		 2617}
2618
2619void
e3bb37b5 2620i386_print_statistics (FILE *file)
252b5132
RH		 2621{
2622 hash_print_statistics (file, "i386 opcode", op_hash);
2623 hash_print_statistics (file, "i386 register", reg_hash);
2624}
2625\f
252b5132
RH		 2626#ifdef DEBUG386
2627
ce8a8b2f 2628/* Debugging routines for md_assemble. */
d3ce72d0 2629static void pte (insn_template *);
40fb9820 2630static void pt (i386_operand_type);
e3bb37b5
L		 2631static void pe (expressionS *);
2632static void ps (symbolS *);
252b5132
RH		 2633
2634static void
e3bb37b5 2635pi (char *line, i386_insn *x)
252b5132 2636{
09137c09 2637 unsigned int j;
252b5132
RH		 2638
2639 fprintf (stdout, "%s: template ", line);
2640 pte (&x->tm);
09f131f2
JH		 2641 fprintf (stdout, " address: base %s index %s scale %x\n",
2642 x->base_reg ? x->base_reg->reg_name : "none",
2643 x->index_reg ? x->index_reg->reg_name : "none",
2644 x->log2_scale_factor);
2645 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2646 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2647 fprintf (stdout, " sib: base %x index %x scale %x\n",
2648 x->sib.base, x->sib.index, x->sib.scale);
2649 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2650 (x->rex & REX_W) != 0,
2651 (x->rex & REX_R) != 0,
2652 (x->rex & REX_X) != 0,
2653 (x->rex & REX_B) != 0);
09137c09 2654 for (j = 0; j < x->operands; j++)
252b5132 2655 {
09137c09
SP		 2656 fprintf (stdout, " #%d: ", j + 1);
2657 pt (x->types[j]);
252b5132 2658 fprintf (stdout, "\n");
09137c09
SP		 2659 if (x->types[j].bitfield.reg8
2660 || x->types[j].bitfield.reg16
2661 || x->types[j].bitfield.reg32
2662 || x->types[j].bitfield.reg64
2663 || x->types[j].bitfield.regmmx
2664 || x->types[j].bitfield.regxmm
2665 || x->types[j].bitfield.regymm
43234a1e 2666 || x->types[j].bitfield.regzmm
09137c09
SP		 2667 || x->types[j].bitfield.sreg2
2668 || x->types[j].bitfield.sreg3
2669 || x->types[j].bitfield.control
2670 || x->types[j].bitfield.debug
2671 || x->types[j].bitfield.test)
2672 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2673 if (operand_type_check (x->types[j], imm))
2674 pe (x->op[j].imms);
2675 if (operand_type_check (x->types[j], disp))
2676 pe (x->op[j].disps);
252b5132
RH		 2677 }
2678}
2679
2680static void
d3ce72d0 2681pte (insn_template *t)
252b5132 2682{
09137c09 2683 unsigned int j;
252b5132 2684 fprintf (stdout, " %d operands ", t->operands);
47926f60 2685 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2686 if (t->extension_opcode != None)
2687 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2688 if (t->opcode_modifier.d)
252b5132 2689 fprintf (stdout, "D");
40fb9820 2690 if (t->opcode_modifier.w)
252b5132
RH		 2691 fprintf (stdout, "W");
2692 fprintf (stdout, "\n");
09137c09 2693 for (j = 0; j < t->operands; j++)
252b5132 2694 {
09137c09
SP		 2695 fprintf (stdout, " #%d type ", j + 1);
2696 pt (t->operand_types[j]);
252b5132
RH		 2697 fprintf (stdout, "\n");
2698 }
2699}
2700
2701static void
e3bb37b5 2702pe (expressionS *e)
252b5132 2703{
24eab124 2704 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2705 fprintf (stdout, " add_number %ld (%lx)\n",
2706 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2707 if (e->X_add_symbol)
2708 {
2709 fprintf (stdout, " add_symbol ");
2710 ps (e->X_add_symbol);
2711 fprintf (stdout, "\n");
2712 }
2713 if (e->X_op_symbol)
2714 {
2715 fprintf (stdout, " op_symbol ");
2716 ps (e->X_op_symbol);
2717 fprintf (stdout, "\n");
2718 }
2719}
2720
2721static void
e3bb37b5 2722ps (symbolS *s)
252b5132
RH		 2723{
2724 fprintf (stdout, "%s type %s%s",
2725 S_GET_NAME (s),
2726 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2727 segment_name (S_GET_SEGMENT (s)));
2728}
2729
7b81dfbb 2730static struct type_name
252b5132 2731 {
40fb9820
L		 2732 i386_operand_type mask;
2733 const char *name;
252b5132 2734 }
7b81dfbb 2735const type_names[] =
252b5132 2736{
40fb9820
L		 2737 { OPERAND_TYPE_REG8, "r8" },
2738 { OPERAND_TYPE_REG16, "r16" },
2739 { OPERAND_TYPE_REG32, "r32" },
2740 { OPERAND_TYPE_REG64, "r64" },
2741 { OPERAND_TYPE_IMM8, "i8" },
2742 { OPERAND_TYPE_IMM8, "i8s" },
2743 { OPERAND_TYPE_IMM16, "i16" },
2744 { OPERAND_TYPE_IMM32, "i32" },
2745 { OPERAND_TYPE_IMM32S, "i32s" },
2746 { OPERAND_TYPE_IMM64, "i64" },
2747 { OPERAND_TYPE_IMM1, "i1" },
2748 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2749 { OPERAND_TYPE_DISP8, "d8" },
2750 { OPERAND_TYPE_DISP16, "d16" },
2751 { OPERAND_TYPE_DISP32, "d32" },
2752 { OPERAND_TYPE_DISP32S, "d32s" },
2753 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2754 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2755 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2756 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2757 { OPERAND_TYPE_CONTROL, "control reg" },
2758 { OPERAND_TYPE_TEST, "test reg" },
2759 { OPERAND_TYPE_DEBUG, "debug reg" },
2760 { OPERAND_TYPE_FLOATREG, "FReg" },
2761 { OPERAND_TYPE_FLOATACC, "FAcc" },
2762 { OPERAND_TYPE_SREG2, "SReg2" },
2763 { OPERAND_TYPE_SREG3, "SReg3" },
2764 { OPERAND_TYPE_ACC, "Acc" },
2765 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2766 { OPERAND_TYPE_REGMMX, "rMMX" },
2767 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2768 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2769 { OPERAND_TYPE_REGZMM, "rZMM" },
2770 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2771 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2772};
2773
2774static void
40fb9820 2775pt (i386_operand_type t)
252b5132 2776{
40fb9820 2777 unsigned int j;
c6fb90c8 2778 i386_operand_type a;
252b5132 2779
40fb9820 2780 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2781 {
2782 a = operand_type_and (t, type_names[j].mask);
0349dc08 2783 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2784 fprintf (stdout, "%s, ", type_names[j].name);
2785 }
252b5132
RH		 2786 fflush (stdout);
2787}
2788
2789#endif /* DEBUG386 */
2790\f
252b5132 2791static bfd_reloc_code_real_type
3956db08 2792reloc (unsigned int size,
64e74474
AM		 2793 int pcrel,
2794 int sign,
2795 bfd_reloc_code_real_type other)
252b5132 2796{
47926f60 2797 if (other != NO_RELOC)
3956db08 2798 {
91d6fa6a 2799 reloc_howto_type *rel;
3956db08
JB		 2800
2801 if (size == 8)
2802 switch (other)
2803 {
64e74474
AM		 2804 case BFD_RELOC_X86_64_GOT32:
2805 return BFD_RELOC_X86_64_GOT64;
2806 break;
553d1284
L		 2807 case BFD_RELOC_X86_64_GOTPLT64:
2808 return BFD_RELOC_X86_64_GOTPLT64;
2809 break;
64e74474
AM		 2810 case BFD_RELOC_X86_64_PLTOFF64:
2811 return BFD_RELOC_X86_64_PLTOFF64;
2812 break;
2813 case BFD_RELOC_X86_64_GOTPC32:
2814 other = BFD_RELOC_X86_64_GOTPC64;
2815 break;
2816 case BFD_RELOC_X86_64_GOTPCREL:
2817 other = BFD_RELOC_X86_64_GOTPCREL64;
2818 break;
2819 case BFD_RELOC_X86_64_TPOFF32:
2820 other = BFD_RELOC_X86_64_TPOFF64;
2821 break;
2822 case BFD_RELOC_X86_64_DTPOFF32:
2823 other = BFD_RELOC_X86_64_DTPOFF64;
2824 break;
2825 default:
2826 break;
3956db08 2827 }
e05278af 2828
8ce3d284 2829#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2830 if (other == BFD_RELOC_SIZE32)
2831 {
2832 if (size == 8)
1ab668bf 2833 other = BFD_RELOC_SIZE64;
8fd4256d 2834 if (pcrel)
1ab668bf
AM		 2835 {
2836 as_bad (_("there are no pc-relative size relocations"));
2837 return NO_RELOC;
2838 }
8fd4256d 2839 }
8ce3d284 2840#endif
8fd4256d 2841
e05278af 2842 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2843 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2844 sign = -1;
2845
91d6fa6a
NC		 2846 rel = bfd_reloc_type_lookup (stdoutput, other);
2847 if (!rel)
3956db08 2848 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2849 else if (size != bfd_get_reloc_size (rel))
3956db08 2850 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2851 bfd_get_reloc_size (rel),
3956db08 2852 size);
91d6fa6a 2853 else if (pcrel && !rel->pc_relative)
3956db08 2854 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2855 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2856 && !sign)
91d6fa6a 2857 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2858 && sign > 0))
3956db08
JB		 2859 as_bad (_("relocated field and relocation type differ in signedness"));
2860 else
2861 return other;
2862 return NO_RELOC;
2863 }
252b5132
RH		 2864
2865 if (pcrel)
2866 {
3e73aa7c 2867 if (!sign)
3956db08 2868 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2869 switch (size)
2870 {
2871 case 1: return BFD_RELOC_8_PCREL;
2872 case 2: return BFD_RELOC_16_PCREL;
d258b828 2873 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2874 case 8: return BFD_RELOC_64_PCREL;
252b5132 2875 }
3956db08 2876 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2877 }
2878 else
2879 {
3956db08 2880 if (sign > 0)
e5cb08ac 2881 switch (size)
3e73aa7c
JH		 2882 {
2883 case 4: return BFD_RELOC_X86_64_32S;
2884 }
2885 else
2886 switch (size)
2887 {
2888 case 1: return BFD_RELOC_8;
2889 case 2: return BFD_RELOC_16;
2890 case 4: return BFD_RELOC_32;
2891 case 8: return BFD_RELOC_64;
2892 }
3956db08
JB		 2893 as_bad (_("cannot do %s %u byte relocation"),
2894 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2895 }
2896
0cc9e1d3 2897 return NO_RELOC;
252b5132
RH		 2898}
2899
47926f60
KH		 2900/* Here we decide which fixups can be adjusted to make them relative to
2901 the beginning of the section instead of the symbol. Basically we need
2902 to make sure that the dynamic relocations are done correctly, so in
2903 some cases we force the original symbol to be used. */
2904
252b5132 2905int
e3bb37b5 2906tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2907{
6d249963 2908#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2909 if (!IS_ELF)
31312f95
AM		 2910 return 1;
2911
a161fe53
AM		 2912 /* Don't adjust pc-relative references to merge sections in 64-bit
2913 mode. */
2914 if (use_rela_relocations
2915 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2916 && fixP->fx_pcrel)
252b5132 2917 return 0;
31312f95 2918
8d01d9a9
AJ		 2919 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2920 and changed later by validate_fix. */
2921 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2922 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2923 return 0;
2924
8fd4256d
L		 2925 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2926 for size relocations. */
2927 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2928 || fixP->fx_r_type == BFD_RELOC_SIZE64
2929 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2930 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2931 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2932 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2933 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2934 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2935 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2936 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2937 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2938 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2939 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2940 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2941 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2942 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2943 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2944 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2945 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2946 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2947 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2948 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2949 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2950 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2951 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2952 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2953 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2954 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2955 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2956 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2957 return 0;
31312f95 2958#endif
252b5132
RH		 2959 return 1;
2960}
252b5132 2961
b4cac588 2962static int
e3bb37b5 2963intel_float_operand (const char *mnemonic)
252b5132 2964{
9306ca4a
JB		 2965 /* Note that the value returned is meaningful only for opcodes with (memory)
2966 operands, hence the code here is free to improperly handle opcodes that
2967 have no operands (for better performance and smaller code). */
2968
2969 if (mnemonic[0] != 'f')
2970 return 0; /* non-math */
2971
2972 switch (mnemonic[1])
2973 {
2974 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2975 the fs segment override prefix not currently handled because no
2976 call path can make opcodes without operands get here */
2977 case 'i':
2978 return 2 /* integer op */;
2979 case 'l':
2980 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2981 return 3; /* fldcw/fldenv */
2982 break;
2983 case 'n':
2984 if (mnemonic[2] != 'o' /* fnop */)
2985 return 3; /* non-waiting control op */
2986 break;
2987 case 'r':
2988 if (mnemonic[2] == 's')
2989 return 3; /* frstor/frstpm */
2990 break;
2991 case 's':
2992 if (mnemonic[2] == 'a')
2993 return 3; /* fsave */
2994 if (mnemonic[2] == 't')
2995 {
2996 switch (mnemonic[3])
2997 {
2998 case 'c': /* fstcw */
2999 case 'd': /* fstdw */
3000 case 'e': /* fstenv */
3001 case 's': /* fsts[gw] */
3002 return 3;
3003 }
3004 }
3005 break;
3006 case 'x':
3007 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3008 return 0; /* fxsave/fxrstor are not really math ops */
3009 break;
3010 }
252b5132 3011
9306ca4a 3012 return 1;
252b5132
RH		 3013}
3014
c0f3af97
L		 3015/* Build the VEX prefix. */
3016
3017static void
d3ce72d0 3018build_vex_prefix (const insn_template *t)
c0f3af97
L		 3019{
3020 unsigned int register_specifier;
3021 unsigned int implied_prefix;
3022 unsigned int vector_length;
3023
3024 /* Check register specifier. */
3025 if (i.vex.register_specifier)
43234a1e
L		 3026 {
3027 register_specifier =
3028 ~register_number (i.vex.register_specifier) & 0xf;
3029 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3030 }
c0f3af97
L		 3031 else
3032 register_specifier = 0xf;
3033
fa99fab2
L		 3034 /* Use 2-byte VEX prefix by swappping destination and source
3035 operand. */
3036 if (!i.swap_operand
3037 && i.operands == i.reg_operands
7f399153 3038 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3039 && i.tm.opcode_modifier.s
3040 && i.rex == REX_B)
3041 {
3042 unsigned int xchg = i.operands - 1;
3043 union i386_op temp_op;
3044 i386_operand_type temp_type;
3045
3046 temp_type = i.types[xchg];
3047 i.types[xchg] = i.types[0];
3048 i.types[0] = temp_type;
3049 temp_op = i.op[xchg];
3050 i.op[xchg] = i.op[0];
3051 i.op[0] = temp_op;
3052
9c2799c2 3053 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3054
3055 i.rex = REX_R;
3056 xchg = i.rm.regmem;
3057 i.rm.regmem = i.rm.reg;
3058 i.rm.reg = xchg;
3059
3060 /* Use the next insn. */
3061 i.tm = t[1];
3062 }
3063
539f890d
L		 3064 if (i.tm.opcode_modifier.vex == VEXScalar)
3065 vector_length = avxscalar;
3066 else
3067 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3068
3069 switch ((i.tm.base_opcode >> 8) & 0xff)
3070 {
3071 case 0:
3072 implied_prefix = 0;
3073 break;
3074 case DATA_PREFIX_OPCODE:
3075 implied_prefix = 1;
3076 break;
3077 case REPE_PREFIX_OPCODE:
3078 implied_prefix = 2;
3079 break;
3080 case REPNE_PREFIX_OPCODE:
3081 implied_prefix = 3;
3082 break;
3083 default:
3084 abort ();
3085 }
3086
3087 /* Use 2-byte VEX prefix if possible. */
7f399153 3088 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3089 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3090 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3091 {
3092 /* 2-byte VEX prefix. */
3093 unsigned int r;
3094
3095 i.vex.length = 2;
3096 i.vex.bytes[0] = 0xc5;
3097
3098 /* Check the REX.R bit. */
3099 r = (i.rex & REX_R) ? 0 : 1;
3100 i.vex.bytes[1] = (r << 7
3101 | register_specifier << 3
3102 | vector_length << 2
3103 | implied_prefix);
3104 }
3105 else
3106 {
3107 /* 3-byte VEX prefix. */
3108 unsigned int m, w;
3109
f88c9eb0 3110 i.vex.length = 3;
f88c9eb0 3111
7f399153 3112 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3113 {
7f399153
L		 3114 case VEX0F:
3115 m = 0x1;
80de6e00 3116 i.vex.bytes[0] = 0xc4;
7f399153
L		 3117 break;
3118 case VEX0F38:
3119 m = 0x2;
80de6e00 3120 i.vex.bytes[0] = 0xc4;
7f399153
L		 3121 break;
3122 case VEX0F3A:
3123 m = 0x3;
80de6e00 3124 i.vex.bytes[0] = 0xc4;
7f399153
L		 3125 break;
3126 case XOP08:
5dd85c99
SP		 3127 m = 0x8;
3128 i.vex.bytes[0] = 0x8f;
7f399153
L		 3129 break;
3130 case XOP09:
f88c9eb0
SP		 3131 m = 0x9;
3132 i.vex.bytes[0] = 0x8f;
7f399153
L		 3133 break;
3134 case XOP0A:
f88c9eb0
SP		 3135 m = 0xa;
3136 i.vex.bytes[0] = 0x8f;
7f399153
L		 3137 break;
3138 default:
3139 abort ();
f88c9eb0 3140 }
c0f3af97 3141
c0f3af97
L		 3142 /* The high 3 bits of the second VEX byte are 1's compliment
3143 of RXB bits from REX. */
3144 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3145
3146 /* Check the REX.W bit. */
3147 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3148 if (i.tm.opcode_modifier.vexw == VEXW1)
3149 w = 1;
c0f3af97
L		 3150
3151 i.vex.bytes[2] = (w << 7
3152 | register_specifier << 3
3153 | vector_length << 2
3154 | implied_prefix);
3155 }
3156}
3157
43234a1e
L		 3158/* Build the EVEX prefix. */
3159
3160static void
3161build_evex_prefix (void)
3162{
3163 unsigned int register_specifier;
3164 unsigned int implied_prefix;
3165 unsigned int m, w;
3166 rex_byte vrex_used = 0;
3167
3168 /* Check register specifier. */
3169 if (i.vex.register_specifier)
3170 {
3171 gas_assert ((i.vrex & REX_X) == 0);
3172
3173 register_specifier = i.vex.register_specifier->reg_num;
3174 if ((i.vex.register_specifier->reg_flags & RegRex))
3175 register_specifier += 8;
3176 /* The upper 16 registers are encoded in the fourth byte of the
3177 EVEX prefix. */
3178 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3179 i.vex.bytes[3] = 0x8;
3180 register_specifier = ~register_specifier & 0xf;
3181 }
3182 else
3183 {
3184 register_specifier = 0xf;
3185
3186 /* Encode upper 16 vector index register in the fourth byte of
3187 the EVEX prefix. */
3188 if (!(i.vrex & REX_X))
3189 i.vex.bytes[3] = 0x8;
3190 else
3191 vrex_used |= REX_X;
3192 }
3193
3194 switch ((i.tm.base_opcode >> 8) & 0xff)
3195 {
3196 case 0:
3197 implied_prefix = 0;
3198 break;
3199 case DATA_PREFIX_OPCODE:
3200 implied_prefix = 1;
3201 break;
3202 case REPE_PREFIX_OPCODE:
3203 implied_prefix = 2;
3204 break;
3205 case REPNE_PREFIX_OPCODE:
3206 implied_prefix = 3;
3207 break;
3208 default:
3209 abort ();
3210 }
3211
3212 /* 4 byte EVEX prefix. */
3213 i.vex.length = 4;
3214 i.vex.bytes[0] = 0x62;
3215
3216 /* mmmm bits. */
3217 switch (i.tm.opcode_modifier.vexopcode)
3218 {
3219 case VEX0F:
3220 m = 1;
3221 break;
3222 case VEX0F38:
3223 m = 2;
3224 break;
3225 case VEX0F3A:
3226 m = 3;
3227 break;
3228 default:
3229 abort ();
3230 break;
3231 }
3232
3233 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3234 bits from REX. */
3235 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3236
3237 /* The fifth bit of the second EVEX byte is 1's compliment of the
3238 REX_R bit in VREX. */
3239 if (!(i.vrex & REX_R))
3240 i.vex.bytes[1] |= 0x10;
3241 else
3242 vrex_used |= REX_R;
3243
3244 if ((i.reg_operands + i.imm_operands) == i.operands)
3245 {
3246 /* When all operands are registers, the REX_X bit in REX is not
3247 used. We reuse it to encode the upper 16 registers, which is
3248 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3249 as 1's compliment. */
3250 if ((i.vrex & REX_B))
3251 {
3252 vrex_used |= REX_B;
3253 i.vex.bytes[1] &= ~0x40;
3254 }
3255 }
3256
3257 /* EVEX instructions shouldn't need the REX prefix. */
3258 i.vrex &= ~vrex_used;
3259 gas_assert (i.vrex == 0);
3260
3261 /* Check the REX.W bit. */
3262 w = (i.rex & REX_W) ? 1 : 0;
3263 if (i.tm.opcode_modifier.vexw)
3264 {
3265 if (i.tm.opcode_modifier.vexw == VEXW1)
3266 w = 1;
3267 }
3268 /* If w is not set it means we are dealing with WIG instruction. */
3269 else if (!w)
3270 {
3271 if (evexwig == evexw1)
3272 w = 1;
3273 }
3274
3275 /* Encode the U bit. */
3276 implied_prefix |= 0x4;
3277
3278 /* The third byte of the EVEX prefix. */
3279 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3280
3281 /* The fourth byte of the EVEX prefix. */
3282 /* The zeroing-masking bit. */
3283 if (i.mask && i.mask->zeroing)
3284 i.vex.bytes[3] |= 0x80;
3285
3286 /* Don't always set the broadcast bit if there is no RC. */
3287 if (!i.rounding)
3288 {
3289 /* Encode the vector length. */
3290 unsigned int vec_length;
3291
3292 switch (i.tm.opcode_modifier.evex)
3293 {
3294 case EVEXLIG: /* LL' is ignored */
3295 vec_length = evexlig << 5;
3296 break;
3297 case EVEX128:
3298 vec_length = 0 << 5;
3299 break;
3300 case EVEX256:
3301 vec_length = 1 << 5;
3302 break;
3303 case EVEX512:
3304 vec_length = 2 << 5;
3305 break;
3306 default:
3307 abort ();
3308 break;
3309 }
3310 i.vex.bytes[3] |= vec_length;
3311 /* Encode the broadcast bit. */
3312 if (i.broadcast)
3313 i.vex.bytes[3] |= 0x10;
3314 }
3315 else
3316 {
3317 if (i.rounding->type != saeonly)
3318 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3319 else
d3d3c6db 3320 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3321 }
3322
3323 if (i.mask && i.mask->mask)
3324 i.vex.bytes[3] |= i.mask->mask->reg_num;
3325}
3326
65da13b5
L		 3327static void
3328process_immext (void)
3329{
3330 expressionS *exp;
3331
4c692bc7
JB		 3332 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3333 && i.operands > 0)
65da13b5 3334 {
4c692bc7
JB		 3335 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3336 with an opcode suffix which is coded in the same place as an
3337 8-bit immediate field would be.
3338 Here we check those operands and remove them afterwards. */
65da13b5
L		 3339 unsigned int x;
3340
3341 for (x = 0; x < i.operands; x++)
4c692bc7 3342 if (register_number (i.op[x].regs) != x)
65da13b5 3343 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3344 register_prefix, i.op[x].regs->reg_name, x + 1,
3345 i.tm.name);
3346
3347 i.operands = 0;
65da13b5
L		 3348 }
3349
c0f3af97 3350 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3351 which is coded in the same place as an 8-bit immediate field
3352 would be. Here we fake an 8-bit immediate operand from the
3353 opcode suffix stored in tm.extension_opcode.
3354
c1e679ec 3355 AVX instructions also use this encoding, for some of
c0f3af97 3356 3 argument instructions. */
65da13b5 3357
43234a1e 3358 gas_assert (i.imm_operands <= 1
7ab9ffdd 3359 && (i.operands <= 2
43234a1e
L		 3360 || ((i.tm.opcode_modifier.vex
3361 || i.tm.opcode_modifier.evex)
7ab9ffdd 3362 && i.operands <= 4)));
65da13b5
L		 3363
3364 exp = &im_expressions[i.imm_operands++];
3365 i.op[i.operands].imms = exp;
3366 i.types[i.operands] = imm8;
3367 i.operands++;
3368 exp->X_op = O_constant;
3369 exp->X_add_number = i.tm.extension_opcode;
3370 i.tm.extension_opcode = None;
3371}
3372
42164a71
L		 3373
3374static int
3375check_hle (void)
3376{
3377 switch (i.tm.opcode_modifier.hleprefixok)
3378 {
3379 default:
3380 abort ();
82c2def5 3381 case HLEPrefixNone:
165de32a
L		 3382 as_bad (_("invalid instruction `%s' after `%s'"),
3383 i.tm.name, i.hle_prefix);
42164a71 3384 return 0;
82c2def5 3385 case HLEPrefixLock:
42164a71
L		 3386 if (i.prefix[LOCK_PREFIX])
3387 return 1;
165de32a 3388 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3389 return 0;
82c2def5 3390 case HLEPrefixAny:
42164a71 3391 return 1;
82c2def5 3392 case HLEPrefixRelease:
42164a71
L		 3393 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3394 {
3395 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3396 i.tm.name);
3397 return 0;
3398 }
3399 if (i.mem_operands == 0
3400 || !operand_type_check (i.types[i.operands - 1], anymem))
3401 {
3402 as_bad (_("memory destination needed for instruction `%s'"
3403 " after `xrelease'"), i.tm.name);
3404 return 0;
3405 }
3406 return 1;
3407 }
3408}
3409
252b5132
RH		 3410/* This is the guts of the machine-dependent assembler. LINE points to a
3411 machine dependent instruction. This function is supposed to emit
3412 the frags/bytes it assembles to. */
3413
3414void
65da13b5 3415md_assemble (char *line)
252b5132 3416{
40fb9820 3417 unsigned int j;
252b5132 3418 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3419 const insn_template *t;
252b5132 3420
47926f60 3421 /* Initialize globals. */
252b5132
RH		 3422 memset (&i, '\0', sizeof (i));
3423 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3424 i.reloc[j] = NO_RELOC;
252b5132
RH		 3425 memset (disp_expressions, '\0', sizeof (disp_expressions));
3426 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3427 save_stack_p = save_stack;
252b5132
RH		 3428
3429 /* First parse an instruction mnemonic & call i386_operand for the operands.
3430 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3431 start of a (possibly prefixed) mnemonic. */
252b5132 3432
29b0f896
AM		 3433 line = parse_insn (line, mnemonic);
3434 if (line == NULL)
3435 return;
252b5132 3436
29b0f896 3437 line = parse_operands (line, mnemonic);
ee86248c 3438 this_operand = -1;
29b0f896
AM		 3439 if (line == NULL)
3440 return;
252b5132 3441
29b0f896
AM		 3442 /* Now we've parsed the mnemonic into a set of templates, and have the
3443 operands at hand. */
3444
3445 /* All intel opcodes have reversed operands except for "bound" and
3446 "enter". We also don't reverse intersegment "jmp" and "call"
3447 instructions with 2 immediate operands so that the immediate segment
050dfa73 3448 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3449 if (intel_syntax
3450 && i.operands > 1
29b0f896 3451 && (strcmp (mnemonic, "bound") != 0)
30123838 3452 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3453 && !(operand_type_check (i.types[0], imm)
3454 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3455 swap_operands ();
3456
ec56d5c0
JB		 3457 /* The order of the immediates should be reversed
3458 for 2 immediates extrq and insertq instructions */
3459 if (i.imm_operands == 2
3460 && (strcmp (mnemonic, "extrq") == 0
3461 || strcmp (mnemonic, "insertq") == 0))
3462 swap_2_operands (0, 1);
3463
29b0f896
AM		 3464 if (i.imm_operands)
3465 optimize_imm ();
3466
b300c311
L		 3467 /* Don't optimize displacement for movabs since it only takes 64bit
3468 displacement. */
3469 if (i.disp_operands
a501d77e 3470 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3471 && (flag_code != CODE_64BIT
3472 || strcmp (mnemonic, "movabs") != 0))
3473 optimize_disp ();
29b0f896
AM		 3474
3475 /* Next, we find a template that matches the given insn,
3476 making sure the overlap of the given operands types is consistent
3477 with the template operand types. */
252b5132 3478
fa99fab2 3479 if (!(t = match_template ()))
29b0f896 3480 return;
252b5132 3481
7bab8ab5 3482 if (sse_check != check_none
81f8a913 3483 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3484 && (i.tm.cpu_flags.bitfield.cpusse
3485 || i.tm.cpu_flags.bitfield.cpusse2
3486 || i.tm.cpu_flags.bitfield.cpusse3
3487 || i.tm.cpu_flags.bitfield.cpussse3
3488 || i.tm.cpu_flags.bitfield.cpusse4_1
3489 || i.tm.cpu_flags.bitfield.cpusse4_2))
3490 {
7bab8ab5 3491 (sse_check == check_warning
daf50ae7
L		 3492 ? as_warn
3493 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3494 }
3495
321fd21e
L		 3496 /* Zap movzx and movsx suffix. The suffix has been set from
3497 "word ptr" or "byte ptr" on the source operand in Intel syntax
3498 or extracted from mnemonic in AT&T syntax. But we'll use
3499 the destination register to choose the suffix for encoding. */
3500 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3501 {
321fd21e
L		 3502 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3503 there is no suffix, the default will be byte extension. */
3504 if (i.reg_operands != 2
3505 && !i.suffix
7ab9ffdd 3506 && intel_syntax)
321fd21e
L		 3507 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3508
3509 i.suffix = 0;
cd61ebfe 3510 }
24eab124 3511
40fb9820 3512 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3513 if (!add_prefix (FWAIT_OPCODE))
3514 return;
252b5132 3515
d5de92cf
L		 3516 /* Check if REP prefix is OK. */
3517 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3518 {
3519 as_bad (_("invalid instruction `%s' after `%s'"),
3520 i.tm.name, i.rep_prefix);
3521 return;
3522 }
3523
c1ba0266
L		 3524 /* Check for lock without a lockable instruction. Destination operand
3525 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3526 if (i.prefix[LOCK_PREFIX]
3527 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3528 || i.mem_operands == 0
3529 || (i.tm.base_opcode != 0x86
3530 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3531 {
3532 as_bad (_("expecting lockable instruction after `lock'"));
3533 return;
3534 }
3535
42164a71 3536 /* Check if HLE prefix is OK. */
165de32a 3537 if (i.hle_prefix && !check_hle ())
42164a71
L		 3538 return;
3539
7e8b059b
L		 3540 /* Check BND prefix. */
3541 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3542 as_bad (_("expecting valid branch instruction after `bnd'"));
3543
3544 if (i.tm.cpu_flags.bitfield.cpumpx
3545 && flag_code == CODE_64BIT
3546 && i.prefix[ADDR_PREFIX])
3547 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3548
3549 /* Insert BND prefix. */
3550 if (add_bnd_prefix
3551 && i.tm.opcode_modifier.bndprefixok
3552 && !i.prefix[BND_PREFIX])
3553 add_prefix (BND_PREFIX_OPCODE);
3554
29b0f896 3555 /* Check string instruction segment overrides. */
40fb9820 3556 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3557 {
3558 if (!check_string ())
5dd0794d 3559 return;
fc0763e6 3560 i.disp_operands = 0;
29b0f896 3561 }
5dd0794d 3562
29b0f896
AM		 3563 if (!process_suffix ())
3564 return;
e413e4e9 3565
bc0844ae
L		 3566 /* Update operand types. */
3567 for (j = 0; j < i.operands; j++)
3568 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3569
29b0f896
AM		 3570 /* Make still unresolved immediate matches conform to size of immediate
3571 given in i.suffix. */
3572 if (!finalize_imm ())
3573 return;
252b5132 3574
40fb9820 3575 if (i.types[0].bitfield.imm1)
29b0f896 3576 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3577
9afe6eb8
L		 3578 /* We only need to check those implicit registers for instructions
3579 with 3 operands or less. */
3580 if (i.operands <= 3)
3581 for (j = 0; j < i.operands; j++)
3582 if (i.types[j].bitfield.inoutportreg
3583 || i.types[j].bitfield.shiftcount
3584 || i.types[j].bitfield.acc
3585 || i.types[j].bitfield.floatacc)
3586 i.reg_operands--;
40fb9820 3587
c0f3af97
L		 3588 /* ImmExt should be processed after SSE2AVX. */
3589 if (!i.tm.opcode_modifier.sse2avx
3590 && i.tm.opcode_modifier.immext)
65da13b5 3591 process_immext ();
252b5132 3592
29b0f896
AM		 3593 /* For insns with operands there are more diddles to do to the opcode. */
3594 if (i.operands)
3595 {
3596 if (!process_operands ())
3597 return;
3598 }
40fb9820 3599 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3600 {
3601 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3602 as_warn (_("translating to `%sp'"), i.tm.name);
3603 }
252b5132 3604
9e5e5283
L		 3605 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3606 {
3607 if (flag_code == CODE_16BIT)
3608 {
3609 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3610 i.tm.name);
3611 return;
3612 }
c0f3af97 3613
9e5e5283
L		 3614 if (i.tm.opcode_modifier.vex)
3615 build_vex_prefix (t);
3616 else
3617 build_evex_prefix ();
3618 }
43234a1e 3619
5dd85c99
SP		 3620 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3621 instructions may define INT_OPCODE as well, so avoid this corner
3622 case for those instructions that use MODRM. */
3623 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3624 && !i.tm.opcode_modifier.modrm
3625 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3626 {
3627 i.tm.base_opcode = INT3_OPCODE;
3628 i.imm_operands = 0;
3629 }
252b5132 3630
40fb9820
L		 3631 if ((i.tm.opcode_modifier.jump
3632 || i.tm.opcode_modifier.jumpbyte
3633 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3634 && i.op[0].disps->X_op == O_constant)
3635 {
3636 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3637 the absolute address given by the constant. Since ix86 jumps and
3638 calls are pc relative, we need to generate a reloc. */
3639 i.op[0].disps->X_add_symbol = &abs_symbol;
3640 i.op[0].disps->X_op = O_symbol;
3641 }
252b5132 3642
40fb9820 3643 if (i.tm.opcode_modifier.rex64)
161a04f6 3644 i.rex |= REX_W;
252b5132 3645
29b0f896
AM		 3646 /* For 8 bit registers we need an empty rex prefix. Also if the
3647 instruction already has a prefix, we need to convert old
3648 registers to new ones. */
773f551c 3649
40fb9820 3650 if ((i.types[0].bitfield.reg8
29b0f896 3651 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3652 || (i.types[1].bitfield.reg8
29b0f896 3653 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3654 || ((i.types[0].bitfield.reg8
3655 || i.types[1].bitfield.reg8)
29b0f896
AM		 3656 && i.rex != 0))
3657 {
3658 int x;
726c5dcd 3659
29b0f896
AM		 3660 i.rex |= REX_OPCODE;
3661 for (x = 0; x < 2; x++)
3662 {
3663 /* Look for 8 bit operand that uses old registers. */
40fb9820 3664 if (i.types[x].bitfield.reg8
29b0f896 3665 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3666 {
29b0f896
AM		 3667 /* In case it is "hi" register, give up. */
3668 if (i.op[x].regs->reg_num > 3)
a540244d 3669 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3670 "instruction requiring REX prefix."),
a540244d 3671 register_prefix, i.op[x].regs->reg_name);
773f551c 3672
29b0f896
AM		 3673 /* Otherwise it is equivalent to the extended register.
3674 Since the encoding doesn't change this is merely
3675 cosmetic cleanup for debug output. */
3676
3677 i.op[x].regs = i.op[x].regs + 8;
773f551c 3678 }
29b0f896
AM		 3679 }
3680 }
773f551c 3681
7ab9ffdd 3682 if (i.rex != 0)
29b0f896
AM		 3683 add_prefix (REX_OPCODE | i.rex);
3684
3685 /* We are ready to output the insn. */
3686 output_insn ();
3687}
3688
3689static char *
e3bb37b5 3690parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3691{
3692 char *l = line;
3693 char *token_start = l;
3694 char *mnem_p;
5c6af06e 3695 int supported;
d3ce72d0 3696 const insn_template *t;
b6169b20 3697 char *dot_p = NULL;
29b0f896 3698
29b0f896
AM		 3699 while (1)
3700 {
3701 mnem_p = mnemonic;
3702 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3703 {
b6169b20
L		 3704 if (*mnem_p == '.')
3705 dot_p = mnem_p;
29b0f896
AM		 3706 mnem_p++;
3707 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3708 {
29b0f896
AM		 3709 as_bad (_("no such instruction: `%s'"), token_start);
3710 return NULL;
3711 }
3712 l++;
3713 }
3714 if (!is_space_char (*l)
3715 && *l != END_OF_INSN
e44823cf
JB		 3716 && (intel_syntax
3717 || (*l != PREFIX_SEPARATOR
3718 && *l != ',')))
29b0f896
AM		 3719 {
3720 as_bad (_("invalid character %s in mnemonic"),
3721 output_invalid (*l));
3722 return NULL;
3723 }
3724 if (token_start == l)
3725 {
e44823cf 3726 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3727 as_bad (_("expecting prefix; got nothing"));
3728 else
3729 as_bad (_("expecting mnemonic; got nothing"));
3730 return NULL;
3731 }
45288df1 3732
29b0f896 3733 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3734 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3735
29b0f896
AM		 3736 if (*l != END_OF_INSN
3737 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3738 && current_templates
40fb9820 3739 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3740 {
c6fb90c8 3741 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3742 {
3743 as_bad ((flag_code != CODE_64BIT
3744 ? _("`%s' is only supported in 64-bit mode")
3745 : _("`%s' is not supported in 64-bit mode")),
3746 current_templates->start->name);
3747 return NULL;
3748 }
29b0f896
AM		 3749 /* If we are in 16-bit mode, do not allow addr16 or data16.
3750 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3751 if ((current_templates->start->opcode_modifier.size16
3752 || current_templates->start->opcode_modifier.size32)
29b0f896 3753 && flag_code != CODE_64BIT
40fb9820 3754 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3755 ^ (flag_code == CODE_16BIT)))
3756 {
3757 as_bad (_("redundant %s prefix"),
3758 current_templates->start->name);
3759 return NULL;
45288df1 3760 }
29b0f896
AM		 3761 /* Add prefix, checking for repeated prefixes. */
3762 switch (add_prefix (current_templates->start->base_opcode))
3763 {
c32fa91d 3764 case PREFIX_EXIST:
29b0f896 3765 return NULL;
c32fa91d 3766 case PREFIX_REP:
42164a71 3767 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3768 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3769 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3770 i.bnd_prefix = current_templates->start->name;
42164a71 3771 else
d5de92cf 3772 i.rep_prefix = current_templates->start->name;
29b0f896 3773 break;
c32fa91d
L		 3774 default:
3775 break;
29b0f896
AM		 3776 }
3777 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3778 token_start = ++l;
3779 }
3780 else
3781 break;
3782 }
45288df1 3783
30a55f88 3784 if (!current_templates)
b6169b20 3785 {
f8a5c266
L		 3786 /* Check if we should swap operand or force 32bit displacement in
3787 encoding. */
30a55f88
L		 3788 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3789 i.swap_operand = 1;
8d63c93e 3790 else if (mnem_p - 3 == dot_p
a501d77e
L		 3791 && dot_p[1] == 'd'
3792 && dot_p[2] == '8')
3793 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3794 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3795 && dot_p[1] == 'd'
3796 && dot_p[2] == '3'
3797 && dot_p[3] == '2')
a501d77e 3798 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3799 else
3800 goto check_suffix;
3801 mnem_p = dot_p;
3802 *dot_p = '\0';
d3ce72d0 3803 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3804 }
3805
29b0f896
AM		 3806 if (!current_templates)
3807 {
b6169b20 3808check_suffix:
29b0f896
AM		 3809 /* See if we can get a match by trimming off a suffix. */
3810 switch (mnem_p[-1])
3811 {
3812 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3813 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3814 i.suffix = SHORT_MNEM_SUFFIX;
3815 else
29b0f896
AM		 3816 case BYTE_MNEM_SUFFIX:
3817 case QWORD_MNEM_SUFFIX:
3818 i.suffix = mnem_p[-1];
3819 mnem_p[-1] = '\0';
d3ce72d0
NC		 3820 current_templates = (const templates *) hash_find (op_hash,
3821 mnemonic);
29b0f896
AM		 3822 break;
3823 case SHORT_MNEM_SUFFIX:
3824 case LONG_MNEM_SUFFIX:
3825 if (!intel_syntax)
3826 {
3827 i.suffix = mnem_p[-1];
3828 mnem_p[-1] = '\0';
d3ce72d0
NC		 3829 current_templates = (const templates *) hash_find (op_hash,
3830 mnemonic);
29b0f896
AM		 3831 }
3832 break;
252b5132 3833
29b0f896
AM		 3834 /* Intel Syntax. */
3835 case 'd':
3836 if (intel_syntax)
3837 {
9306ca4a 3838 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3839 i.suffix = SHORT_MNEM_SUFFIX;
3840 else
3841 i.suffix = LONG_MNEM_SUFFIX;
3842 mnem_p[-1] = '\0';
d3ce72d0
NC		 3843 current_templates = (const templates *) hash_find (op_hash,
3844 mnemonic);
29b0f896
AM		 3845 }
3846 break;
3847 }
3848 if (!current_templates)
3849 {
3850 as_bad (_("no such instruction: `%s'"), token_start);
3851 return NULL;
3852 }
3853 }
252b5132 3854
40fb9820
L		 3855 if (current_templates->start->opcode_modifier.jump
3856 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3857 {
3858 /* Check for a branch hint. We allow ",pt" and ",pn" for
3859 predict taken and predict not taken respectively.
3860 I'm not sure that branch hints actually do anything on loop
3861 and jcxz insns (JumpByte) for current Pentium4 chips. They
3862 may work in the future and it doesn't hurt to accept them
3863 now. */
3864 if (l[0] == ',' && l[1] == 'p')
3865 {
3866 if (l[2] == 't')
3867 {
3868 if (!add_prefix (DS_PREFIX_OPCODE))
3869 return NULL;
3870 l += 3;
3871 }
3872 else if (l[2] == 'n')
3873 {
3874 if (!add_prefix (CS_PREFIX_OPCODE))
3875 return NULL;
3876 l += 3;
3877 }
3878 }
3879 }
3880 /* Any other comma loses. */
3881 if (*l == ',')
3882 {
3883 as_bad (_("invalid character %s in mnemonic"),
3884 output_invalid (*l));
3885 return NULL;
3886 }
252b5132 3887
29b0f896 3888 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3889 supported = 0;
3890 for (t = current_templates->start; t < current_templates->end; ++t)
3891 {
c0f3af97
L		 3892 supported |= cpu_flags_match (t);
3893 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3894 goto skip;
5c6af06e 3895 }
3629bb00 3896
c0f3af97 3897 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3898 {
3899 as_bad (flag_code == CODE_64BIT
3900 ? _("`%s' is not supported in 64-bit mode")
3901 : _("`%s' is only supported in 64-bit mode"),
3902 current_templates->start->name);
3903 return NULL;
3904 }
c0f3af97 3905 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3906 {
3629bb00 3907 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3908 current_templates->start->name,
41aacd83 3909 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3910 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3911 return NULL;
29b0f896 3912 }
3629bb00
L		 3913
3914skip:
3915 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3916 && (flag_code != CODE_16BIT))
29b0f896
AM		 3917 {
3918 as_warn (_("use .code16 to ensure correct addressing mode"));
3919 }
252b5132 3920
29b0f896
AM		 3921 return l;
3922}
252b5132 3923
29b0f896 3924static char *
e3bb37b5 3925parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3926{
3927 char *token_start;
3138f287 3928
29b0f896
AM		 3929 /* 1 if operand is pending after ','. */
3930 unsigned int expecting_operand = 0;
252b5132 3931
29b0f896
AM		 3932 /* Non-zero if operand parens not balanced. */
3933 unsigned int paren_not_balanced;
3934
3935 while (*l != END_OF_INSN)
3936 {
3937 /* Skip optional white space before operand. */
3938 if (is_space_char (*l))
3939 ++l;
3940 if (!is_operand_char (*l) && *l != END_OF_INSN)
3941 {
3942 as_bad (_("invalid character %s before operand %d"),
3943 output_invalid (*l),
3944 i.operands + 1);
3945 return NULL;
3946 }
3947 token_start = l; /* after white space */
3948 paren_not_balanced = 0;
3949 while (paren_not_balanced || *l != ',')
3950 {
3951 if (*l == END_OF_INSN)
3952 {
3953 if (paren_not_balanced)
3954 {
3955 if (!intel_syntax)
3956 as_bad (_("unbalanced parenthesis in operand %d."),
3957 i.operands + 1);
3958 else
3959 as_bad (_("unbalanced brackets in operand %d."),
3960 i.operands + 1);
3961 return NULL;
3962 }
3963 else
3964 break; /* we are done */
3965 }
3966 else if (!is_operand_char (*l) && !is_space_char (*l))
3967 {
3968 as_bad (_("invalid character %s in operand %d"),
3969 output_invalid (*l),
3970 i.operands + 1);
3971 return NULL;
3972 }
3973 if (!intel_syntax)
3974 {
3975 if (*l == '(')
3976 ++paren_not_balanced;
3977 if (*l == ')')
3978 --paren_not_balanced;
3979 }
3980 else
3981 {
3982 if (*l == '[')
3983 ++paren_not_balanced;
3984 if (*l == ']')
3985 --paren_not_balanced;
3986 }
3987 l++;
3988 }
3989 if (l != token_start)
3990 { /* Yes, we've read in another operand. */
3991 unsigned int operand_ok;
3992 this_operand = i.operands++;
7d5e4556 3993 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3994 if (i.operands > MAX_OPERANDS)
3995 {
3996 as_bad (_("spurious operands; (%d operands/instruction max)"),
3997 MAX_OPERANDS);
3998 return NULL;
3999 }
4000 /* Now parse operand adding info to 'i' as we go along. */
4001 END_STRING_AND_SAVE (l);
4002
4003 if (intel_syntax)
4004 operand_ok =
4005 i386_intel_operand (token_start,
4006 intel_float_operand (mnemonic));
4007 else
a7619375 4008 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4009
4010 RESTORE_END_STRING (l);
4011 if (!operand_ok)
4012 return NULL;
4013 }
4014 else
4015 {
4016 if (expecting_operand)
4017 {
4018 expecting_operand_after_comma:
4019 as_bad (_("expecting operand after ','; got nothing"));
4020 return NULL;
4021 }
4022 if (*l == ',')
4023 {
4024 as_bad (_("expecting operand before ','; got nothing"));
4025 return NULL;
4026 }
4027 }
7f3f1ea2 4028
29b0f896
AM		 4029 /* Now *l must be either ',' or END_OF_INSN. */
4030 if (*l == ',')
4031 {
4032 if (*++l == END_OF_INSN)
4033 {
4034 /* Just skip it, if it's \n complain. */
4035 goto expecting_operand_after_comma;
4036 }
4037 expecting_operand = 1;
4038 }
4039 }
4040 return l;
4041}
7f3f1ea2 4042
050dfa73 4043static void
4d456e3d 4044swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4045{
4046 union i386_op temp_op;
40fb9820 4047 i386_operand_type temp_type;
050dfa73 4048 enum bfd_reloc_code_real temp_reloc;
4eed87de 4049
050dfa73
MM		 4050 temp_type = i.types[xchg2];
4051 i.types[xchg2] = i.types[xchg1];
4052 i.types[xchg1] = temp_type;
4053 temp_op = i.op[xchg2];
4054 i.op[xchg2] = i.op[xchg1];
4055 i.op[xchg1] = temp_op;
4056 temp_reloc = i.reloc[xchg2];
4057 i.reloc[xchg2] = i.reloc[xchg1];
4058 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4059
4060 if (i.mask)
4061 {
4062 if (i.mask->operand == xchg1)
4063 i.mask->operand = xchg2;
4064 else if (i.mask->operand == xchg2)
4065 i.mask->operand = xchg1;
4066 }
4067 if (i.broadcast)
4068 {
4069 if (i.broadcast->operand == xchg1)
4070 i.broadcast->operand = xchg2;
4071 else if (i.broadcast->operand == xchg2)
4072 i.broadcast->operand = xchg1;
4073 }
4074 if (i.rounding)
4075 {
4076 if (i.rounding->operand == xchg1)
4077 i.rounding->operand = xchg2;
4078 else if (i.rounding->operand == xchg2)
4079 i.rounding->operand = xchg1;
4080 }
050dfa73
MM		 4081}
4082
29b0f896 4083static void
e3bb37b5 4084swap_operands (void)
29b0f896 4085{
b7c61d9a 4086 switch (i.operands)
050dfa73 4087 {
c0f3af97 4088 case 5:
b7c61d9a 4089 case 4:
4d456e3d 4090 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4091 case 3:
4092 case 2:
4d456e3d 4093 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4094 break;
4095 default:
4096 abort ();
29b0f896 4097 }
29b0f896
AM		 4098
4099 if (i.mem_operands == 2)
4100 {
4101 const seg_entry *temp_seg;
4102 temp_seg = i.seg[0];
4103 i.seg[0] = i.seg[1];
4104 i.seg[1] = temp_seg;
4105 }
4106}
252b5132 4107
29b0f896
AM		 4108/* Try to ensure constant immediates are represented in the smallest
4109 opcode possible. */
4110static void
e3bb37b5 4111optimize_imm (void)
29b0f896
AM		 4112{
4113 char guess_suffix = 0;
4114 int op;
252b5132 4115
29b0f896
AM		 4116 if (i.suffix)
4117 guess_suffix = i.suffix;
4118 else if (i.reg_operands)
4119 {
4120 /* Figure out a suffix from the last register operand specified.
4121 We can't do this properly yet, ie. excluding InOutPortReg,
4122 but the following works for instructions with immediates.
4123 In any case, we can't set i.suffix yet. */
4124 for (op = i.operands; --op >= 0;)
40fb9820 4125 if (i.types[op].bitfield.reg8)
7ab9ffdd 4126 {
40fb9820
L		 4127 guess_suffix = BYTE_MNEM_SUFFIX;
4128 break;
4129 }
4130 else if (i.types[op].bitfield.reg16)
252b5132 4131 {
40fb9820
L		 4132 guess_suffix = WORD_MNEM_SUFFIX;
4133 break;
4134 }
4135 else if (i.types[op].bitfield.reg32)
4136 {
4137 guess_suffix = LONG_MNEM_SUFFIX;
4138 break;
4139 }
4140 else if (i.types[op].bitfield.reg64)
4141 {
4142 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4143 break;
252b5132 4144 }
29b0f896
AM		 4145 }
4146 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4147 guess_suffix = WORD_MNEM_SUFFIX;
4148
4149 for (op = i.operands; --op >= 0;)
40fb9820 4150 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4151 {
4152 switch (i.op[op].imms->X_op)
252b5132 4153 {
29b0f896
AM		 4154 case O_constant:
4155 /* If a suffix is given, this operand may be shortened. */
4156 switch (guess_suffix)
252b5132 4157 {
29b0f896 4158 case LONG_MNEM_SUFFIX:
40fb9820
L		 4159 i.types[op].bitfield.imm32 = 1;
4160 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4161 break;
4162 case WORD_MNEM_SUFFIX:
40fb9820
L		 4163 i.types[op].bitfield.imm16 = 1;
4164 i.types[op].bitfield.imm32 = 1;
4165 i.types[op].bitfield.imm32s = 1;
4166 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4167 break;
4168 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4169 i.types[op].bitfield.imm8 = 1;
4170 i.types[op].bitfield.imm8s = 1;
4171 i.types[op].bitfield.imm16 = 1;
4172 i.types[op].bitfield.imm32 = 1;
4173 i.types[op].bitfield.imm32s = 1;
4174 i.types[op].bitfield.imm64 = 1;
29b0f896 4175 break;
252b5132 4176 }
252b5132 4177
29b0f896
AM		 4178 /* If this operand is at most 16 bits, convert it
4179 to a signed 16 bit number before trying to see
4180 whether it will fit in an even smaller size.
4181 This allows a 16-bit operand such as $0xffe0 to
4182 be recognised as within Imm8S range. */
40fb9820 4183 if ((i.types[op].bitfield.imm16)
29b0f896 4184 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4185 {
29b0f896
AM		 4186 i.op[op].imms->X_add_number =
4187 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4188 }
40fb9820 4189 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4190 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4191 == 0))
4192 {
4193 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4194 ^ ((offsetT) 1 << 31))
4195 - ((offsetT) 1 << 31));
4196 }
40fb9820 4197 i.types[op]
c6fb90c8
L		 4198 = operand_type_or (i.types[op],
4199 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4200
29b0f896
AM		 4201 /* We must avoid matching of Imm32 templates when 64bit
4202 only immediate is available. */
4203 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4204 i.types[op].bitfield.imm32 = 0;
29b0f896 4205 break;
252b5132 4206
29b0f896
AM		 4207 case O_absent:
4208 case O_register:
4209 abort ();
4210
4211 /* Symbols and expressions. */
4212 default:
9cd96992
JB		 4213 /* Convert symbolic operand to proper sizes for matching, but don't
4214 prevent matching a set of insns that only supports sizes other
4215 than those matching the insn suffix. */
4216 {
40fb9820 4217 i386_operand_type mask, allowed;
d3ce72d0 4218 const insn_template *t;
9cd96992 4219
0dfbf9d7
L		 4220 operand_type_set (&mask, 0);
4221 operand_type_set (&allowed, 0);
40fb9820 4222
4eed87de
AM		 4223 for (t = current_templates->start;
4224 t < current_templates->end;
4225 ++t)
c6fb90c8
L		 4226 allowed = operand_type_or (allowed,
4227 t->operand_types[op]);
9cd96992
JB		 4228 switch (guess_suffix)
4229 {
4230 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4231 mask.bitfield.imm64 = 1;
4232 mask.bitfield.imm32s = 1;
9cd96992
JB		 4233 break;
4234 case LONG_MNEM_SUFFIX:
40fb9820 4235 mask.bitfield.imm32 = 1;
9cd96992
JB		 4236 break;
4237 case WORD_MNEM_SUFFIX:
40fb9820 4238 mask.bitfield.imm16 = 1;
9cd96992
JB		 4239 break;
4240 case BYTE_MNEM_SUFFIX:
40fb9820 4241 mask.bitfield.imm8 = 1;
9cd96992
JB		 4242 break;
4243 default:
9cd96992
JB		 4244 break;
4245 }
c6fb90c8 4246 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4247 if (!operand_type_all_zero (&allowed))
c6fb90c8 4248 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4249 }
29b0f896 4250 break;
252b5132 4251 }
29b0f896
AM		 4252 }
4253}
47926f60 4254
29b0f896
AM		 4255/* Try to use the smallest displacement type too. */
4256static void
e3bb37b5 4257optimize_disp (void)
29b0f896
AM		 4258{
4259 int op;
3e73aa7c 4260
29b0f896 4261 for (op = i.operands; --op >= 0;)
40fb9820 4262 if (operand_type_check (i.types[op], disp))
252b5132 4263 {
b300c311 4264 if (i.op[op].disps->X_op == O_constant)
252b5132 4265 {
91d6fa6a 4266 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4267
40fb9820 4268 if (i.types[op].bitfield.disp16
91d6fa6a 4269 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4270 {
4271 /* If this operand is at most 16 bits, convert
4272 to a signed 16 bit number and don't use 64bit
4273 displacement. */
91d6fa6a 4274 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4275 i.types[op].bitfield.disp64 = 0;
b300c311 4276 }
40fb9820 4277 if (i.types[op].bitfield.disp32
91d6fa6a 4278 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4279 {
4280 /* If this operand is at most 32 bits, convert
4281 to a signed 32 bit number and don't use 64bit
4282 displacement. */
91d6fa6a
NC		 4283 op_disp &= (((offsetT) 2 << 31) - 1);
4284 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4285 i.types[op].bitfield.disp64 = 0;
b300c311 4286 }
91d6fa6a 4287 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4288 {
40fb9820
L		 4289 i.types[op].bitfield.disp8 = 0;
4290 i.types[op].bitfield.disp16 = 0;
4291 i.types[op].bitfield.disp32 = 0;
4292 i.types[op].bitfield.disp32s = 0;
4293 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4294 i.op[op].disps = 0;
4295 i.disp_operands--;
4296 }
4297 else if (flag_code == CODE_64BIT)
4298 {
91d6fa6a 4299 if (fits_in_signed_long (op_disp))
28a9d8f5 4300 {
40fb9820
L		 4301 i.types[op].bitfield.disp64 = 0;
4302 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4303 }
0e1147d9 4304 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4305 && fits_in_unsigned_long (op_disp))
40fb9820 4306 i.types[op].bitfield.disp32 = 1;
b300c311 4307 }
40fb9820
L		 4308 if ((i.types[op].bitfield.disp32
4309 || i.types[op].bitfield.disp32s
4310 || i.types[op].bitfield.disp16)
91d6fa6a 4311 && fits_in_signed_byte (op_disp))
40fb9820 4312 i.types[op].bitfield.disp8 = 1;
252b5132 4313 }
67a4f2b7
AO		 4314 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4315 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4316 {
4317 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4318 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4319 i.types[op].bitfield.disp8 = 0;
4320 i.types[op].bitfield.disp16 = 0;
4321 i.types[op].bitfield.disp32 = 0;
4322 i.types[op].bitfield.disp32s = 0;
4323 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4324 }
4325 else
b300c311 4326 /* We only support 64bit displacement on constants. */
40fb9820 4327 i.types[op].bitfield.disp64 = 0;
252b5132 4328 }
29b0f896
AM		 4329}
4330
6c30d220
L		 4331/* Check if operands are valid for the instruction. */
4332
4333static int
4334check_VecOperands (const insn_template *t)
4335{
43234a1e
L		 4336 unsigned int op;
4337
6c30d220
L		 4338 /* Without VSIB byte, we can't have a vector register for index. */
4339 if (!t->opcode_modifier.vecsib
4340 && i.index_reg
4341 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4342 || i.index_reg->reg_type.bitfield.regymm
4343 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4344 {
4345 i.error = unsupported_vector_index_register;
4346 return 1;
4347 }
4348
ad8ecc81
MZ		 4349 /* Check if default mask is allowed. */
4350 if (t->opcode_modifier.nodefmask
4351 && (!i.mask || i.mask->mask->reg_num == 0))
4352 {
4353 i.error = no_default_mask;
4354 return 1;
4355 }
4356
7bab8ab5
JB		 4357 /* For VSIB byte, we need a vector register for index, and all vector
4358 registers must be distinct. */
4359 if (t->opcode_modifier.vecsib)
4360 {
4361 if (!i.index_reg
6c30d220
L		 4362 || !((t->opcode_modifier.vecsib == VecSIB128
4363 && i.index_reg->reg_type.bitfield.regxmm)
4364 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4365 && i.index_reg->reg_type.bitfield.regymm)
4366 || (t->opcode_modifier.vecsib == VecSIB512
4367 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4368 {
4369 i.error = invalid_vsib_address;
4370 return 1;
4371 }
4372
43234a1e
L		 4373 gas_assert (i.reg_operands == 2 || i.mask);
4374 if (i.reg_operands == 2 && !i.mask)
4375 {
4376 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4377 || i.types[0].bitfield.regymm);
43234a1e 4378 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4379 || i.types[2].bitfield.regymm);
43234a1e
L		 4380 if (operand_check == check_none)
4381 return 0;
4382 if (register_number (i.op[0].regs)
4383 != register_number (i.index_reg)
4384 && register_number (i.op[2].regs)
4385 != register_number (i.index_reg)
4386 && register_number (i.op[0].regs)
4387 != register_number (i.op[2].regs))
4388 return 0;
4389 if (operand_check == check_error)
4390 {
4391 i.error = invalid_vector_register_set;
4392 return 1;
4393 }
4394 as_warn (_("mask, index, and destination registers should be distinct"));
4395 }
8444f82a
MZ		 4396 else if (i.reg_operands == 1 && i.mask)
4397 {
4398 if ((i.types[1].bitfield.regymm
4399 || i.types[1].bitfield.regzmm)
4400 && (register_number (i.op[1].regs)
4401 == register_number (i.index_reg)))
4402 {
4403 if (operand_check == check_error)
4404 {
4405 i.error = invalid_vector_register_set;
4406 return 1;
4407 }
4408 if (operand_check != check_none)
4409 as_warn (_("index and destination registers should be distinct"));
4410 }
4411 }
43234a1e 4412 }
7bab8ab5 4413
43234a1e
L		 4414 /* Check if broadcast is supported by the instruction and is applied
4415 to the memory operand. */
4416 if (i.broadcast)
4417 {
4418 int broadcasted_opnd_size;
4419
4420 /* Check if specified broadcast is supported in this instruction,
4421 and it's applied to memory operand of DWORD or QWORD type,
4422 depending on VecESize. */
4423 if (i.broadcast->type != t->opcode_modifier.broadcast
4424 || !i.types[i.broadcast->operand].bitfield.mem
4425 || (t->opcode_modifier.vecesize == 0
4426 && !i.types[i.broadcast->operand].bitfield.dword
4427 && !i.types[i.broadcast->operand].bitfield.unspecified)
4428 || (t->opcode_modifier.vecesize == 1
4429 && !i.types[i.broadcast->operand].bitfield.qword
4430 && !i.types[i.broadcast->operand].bitfield.unspecified))
4431 goto bad_broadcast;
4432
4433 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4434 if (i.broadcast->type == BROADCAST_1TO16)
4435 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4436 else if (i.broadcast->type == BROADCAST_1TO8)
4437 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4438 else if (i.broadcast->type == BROADCAST_1TO4)
4439 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4440 else if (i.broadcast->type == BROADCAST_1TO2)
4441 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4442 else
4443 goto bad_broadcast;
4444
4445 if ((broadcasted_opnd_size == 256
4446 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4447 || (broadcasted_opnd_size == 512
4448 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4449 {
4450 bad_broadcast:
4451 i.error = unsupported_broadcast;
4452 return 1;
4453 }
4454 }
4455 /* If broadcast is supported in this instruction, we need to check if
4456 operand of one-element size isn't specified without broadcast. */
4457 else if (t->opcode_modifier.broadcast && i.mem_operands)
4458 {
4459 /* Find memory operand. */
4460 for (op = 0; op < i.operands; op++)
4461 if (operand_type_check (i.types[op], anymem))
4462 break;
4463 gas_assert (op < i.operands);
4464 /* Check size of the memory operand. */
4465 if ((t->opcode_modifier.vecesize == 0
4466 && i.types[op].bitfield.dword)
4467 || (t->opcode_modifier.vecesize == 1
4468 && i.types[op].bitfield.qword))
4469 {
4470 i.error = broadcast_needed;
4471 return 1;
4472 }
4473 }
4474
4475 /* Check if requested masking is supported. */
4476 if (i.mask
4477 && (!t->opcode_modifier.masking
4478 || (i.mask->zeroing
4479 && t->opcode_modifier.masking == MERGING_MASKING)))
4480 {
4481 i.error = unsupported_masking;
4482 return 1;
4483 }
4484
4485 /* Check if masking is applied to dest operand. */
4486 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4487 {
4488 i.error = mask_not_on_destination;
4489 return 1;
4490 }
4491
43234a1e
L		 4492 /* Check RC/SAE. */
4493 if (i.rounding)
4494 {
4495 if ((i.rounding->type != saeonly
4496 && !t->opcode_modifier.staticrounding)
4497 || (i.rounding->type == saeonly
4498 && (t->opcode_modifier.staticrounding
4499 || !t->opcode_modifier.sae)))
4500 {
4501 i.error = unsupported_rc_sae;
4502 return 1;
4503 }
4504 /* If the instruction has several immediate operands and one of
4505 them is rounding, the rounding operand should be the last
4506 immediate operand. */
4507 if (i.imm_operands > 1
4508 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4509 {
43234a1e 4510 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4511 return 1;
4512 }
6c30d220
L		 4513 }
4514
43234a1e
L		 4515 /* Check vector Disp8 operand. */
4516 if (t->opcode_modifier.disp8memshift)
4517 {
4518 if (i.broadcast)
4519 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4520 else
4521 i.memshift = t->opcode_modifier.disp8memshift;
4522
4523 for (op = 0; op < i.operands; op++)
4524 if (operand_type_check (i.types[op], disp)
4525 && i.op[op].disps->X_op == O_constant)
4526 {
4527 offsetT value = i.op[op].disps->X_add_number;
4528 int vec_disp8_ok = fits_in_vec_disp8 (value);
4529 if (t->operand_types [op].bitfield.vec_disp8)
4530 {
4531 if (vec_disp8_ok)
4532 i.types[op].bitfield.vec_disp8 = 1;
4533 else
4534 {
4535 /* Vector insn can only have Vec_Disp8/Disp32 in
4536 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4537 mode. */
4538 i.types[op].bitfield.disp8 = 0;
4539 if (flag_code != CODE_16BIT)
4540 i.types[op].bitfield.disp16 = 0;
4541 }
4542 }
4543 else if (flag_code != CODE_16BIT)
4544 {
4545 /* One form of this instruction supports vector Disp8.
4546 Try vector Disp8 if we need to use Disp32. */
4547 if (vec_disp8_ok && !fits_in_signed_byte (value))
4548 {
4549 i.error = try_vector_disp8;
4550 return 1;
4551 }
4552 }
4553 }
4554 }
4555 else
4556 i.memshift = -1;
4557
6c30d220
L		 4558 return 0;
4559}
4560
43f3e2ee 4561/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4562 operand types. */
4563
4564static int
4565VEX_check_operands (const insn_template *t)
4566{
43234a1e
L		 4567 /* VREX is only valid with EVEX prefix. */
4568 if (i.need_vrex && !t->opcode_modifier.evex)
4569 {
4570 i.error = invalid_register_operand;
4571 return 1;
4572 }
4573
a683cc34
SP		 4574 if (!t->opcode_modifier.vex)
4575 return 0;
4576
4577 /* Only check VEX_Imm4, which must be the first operand. */
4578 if (t->operand_types[0].bitfield.vec_imm4)
4579 {
4580 if (i.op[0].imms->X_op != O_constant
4581 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4582 {
a65babc9 4583 i.error = bad_imm4;
891edac4
L		 4584 return 1;
4585 }
a683cc34
SP		 4586
4587 /* Turn off Imm8 so that update_imm won't complain. */
4588 i.types[0] = vec_imm4;
4589 }
4590
4591 return 0;
4592}
4593
d3ce72d0 4594static const insn_template *
e3bb37b5 4595match_template (void)
29b0f896
AM		 4596{
4597 /* Points to template once we've found it. */
d3ce72d0 4598 const insn_template *t;
40fb9820 4599 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4600 i386_operand_type overlap4;
29b0f896 4601 unsigned int found_reverse_match;
40fb9820
L		 4602 i386_opcode_modifier suffix_check;
4603 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4604 int addr_prefix_disp;
a5c311ca 4605 unsigned int j;
3629bb00 4606 unsigned int found_cpu_match;
45664ddb 4607 unsigned int check_register;
5614d22c 4608 enum i386_error specific_error = 0;
29b0f896 4609
c0f3af97
L		 4610#if MAX_OPERANDS != 5
4611# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4612#endif
4613
29b0f896 4614 found_reverse_match = 0;
539e75ad 4615 addr_prefix_disp = -1;
40fb9820
L		 4616
4617 memset (&suffix_check, 0, sizeof (suffix_check));
4618 if (i.suffix == BYTE_MNEM_SUFFIX)
4619 suffix_check.no_bsuf = 1;
4620 else if (i.suffix == WORD_MNEM_SUFFIX)
4621 suffix_check.no_wsuf = 1;
4622 else if (i.suffix == SHORT_MNEM_SUFFIX)
4623 suffix_check.no_ssuf = 1;
4624 else if (i.suffix == LONG_MNEM_SUFFIX)
4625 suffix_check.no_lsuf = 1;
4626 else if (i.suffix == QWORD_MNEM_SUFFIX)
4627 suffix_check.no_qsuf = 1;
4628 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4629 suffix_check.no_ldsuf = 1;
29b0f896 4630
01559ecc
L		 4631 /* Must have right number of operands. */
4632 i.error = number_of_operands_mismatch;
4633
45aa61fe 4634 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4635 {
539e75ad
L		 4636 addr_prefix_disp = -1;
4637
29b0f896
AM		 4638 if (i.operands != t->operands)
4639 continue;
4640
50aecf8c 4641 /* Check processor support. */
a65babc9 4642 i.error = unsupported;
c0f3af97
L		 4643 found_cpu_match = (cpu_flags_match (t)
4644 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4645 if (!found_cpu_match)
4646 continue;
4647
e1d4d893 4648 /* Check old gcc support. */
a65babc9 4649 i.error = old_gcc_only;
e1d4d893
L		 4650 if (!old_gcc && t->opcode_modifier.oldgcc)
4651 continue;
4652
4653 /* Check AT&T mnemonic. */
a65babc9 4654 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4655 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4656 continue;
4657
891edac4 4658 /* Check AT&T/Intel syntax. */
a65babc9 4659 i.error = unsupported_syntax;
5c07affc
L		 4660 if ((intel_syntax && t->opcode_modifier.attsyntax)
4661 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4662 continue;
4663
20592a94 4664 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4665 i.error = invalid_instruction_suffix;
567e4e96
L		 4666 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4667 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4668 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4669 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4670 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4671 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4672 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4673 continue;
4674
5c07affc 4675 if (!operand_size_match (t))
7d5e4556 4676 continue;
539e75ad 4677
5c07affc
L		 4678 for (j = 0; j < MAX_OPERANDS; j++)
4679 operand_types[j] = t->operand_types[j];
4680
45aa61fe
AM		 4681 /* In general, don't allow 64-bit operands in 32-bit mode. */
4682 if (i.suffix == QWORD_MNEM_SUFFIX
4683 && flag_code != CODE_64BIT
4684 && (intel_syntax
40fb9820 4685 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4686 && !intel_float_operand (t->name))
4687 : intel_float_operand (t->name) != 2)
40fb9820 4688 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4689 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4690 && !operand_types[0].bitfield.regymm
4691 && !operand_types[0].bitfield.regzmm)
40fb9820 4692 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4693 && operand_types[t->operands > 1].bitfield.regxmm
4694 && operand_types[t->operands > 1].bitfield.regymm
4695 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4696 && (t->base_opcode != 0x0fc7
4697 || t->extension_opcode != 1 /* cmpxchg8b */))
4698 continue;
4699
192dc9c6
JB		 4700 /* In general, don't allow 32-bit operands on pre-386. */
4701 else if (i.suffix == LONG_MNEM_SUFFIX
4702 && !cpu_arch_flags.bitfield.cpui386
4703 && (intel_syntax
4704 ? (!t->opcode_modifier.ignoresize
4705 && !intel_float_operand (t->name))
4706 : intel_float_operand (t->name) != 2)
4707 && ((!operand_types[0].bitfield.regmmx
4708 && !operand_types[0].bitfield.regxmm)
4709 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4710 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4711 continue;
4712
29b0f896 4713 /* Do not verify operands when there are none. */
50aecf8c 4714 else
29b0f896 4715 {
c6fb90c8 4716 if (!t->operands)
2dbab7d5
L		 4717 /* We've found a match; break out of loop. */
4718 break;
29b0f896 4719 }
252b5132 4720
539e75ad
L		 4721 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4722 into Disp32/Disp16/Disp32 operand. */
4723 if (i.prefix[ADDR_PREFIX] != 0)
4724 {
40fb9820 4725 /* There should be only one Disp operand. */
539e75ad
L		 4726 switch (flag_code)
4727 {
4728 case CODE_16BIT:
40fb9820
L		 4729 for (j = 0; j < MAX_OPERANDS; j++)
4730 {
4731 if (operand_types[j].bitfield.disp16)
4732 {
4733 addr_prefix_disp = j;
4734 operand_types[j].bitfield.disp32 = 1;
4735 operand_types[j].bitfield.disp16 = 0;
4736 break;
4737 }
4738 }
539e75ad
L		 4739 break;
4740 case CODE_32BIT:
40fb9820
L		 4741 for (j = 0; j < MAX_OPERANDS; j++)
4742 {
4743 if (operand_types[j].bitfield.disp32)
4744 {
4745 addr_prefix_disp = j;
4746 operand_types[j].bitfield.disp32 = 0;
4747 operand_types[j].bitfield.disp16 = 1;
4748 break;
4749 }
4750 }
539e75ad
L		 4751 break;
4752 case CODE_64BIT:
40fb9820
L		 4753 for (j = 0; j < MAX_OPERANDS; j++)
4754 {
4755 if (operand_types[j].bitfield.disp64)
4756 {
4757 addr_prefix_disp = j;
4758 operand_types[j].bitfield.disp64 = 0;
4759 operand_types[j].bitfield.disp32 = 1;
4760 break;
4761 }
4762 }
539e75ad
L		 4763 break;
4764 }
539e75ad
L		 4765 }
4766
56ffb741
L		 4767 /* We check register size if needed. */
4768 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4769 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4770 switch (t->operands)
4771 {
4772 case 1:
40fb9820 4773 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4774 continue;
4775 break;
4776 case 2:
8b38ad71
L		 4777 /* xchg %eax, %eax is a special case. It is an aliase for nop
4778 only in 32bit mode and we can use opcode 0x90. In 64bit
4779 mode, we can't use 0x90 for xchg %eax, %eax since it should
4780 zero-extend %eax to %rax. */
4781 if (flag_code == CODE_64BIT
4782 && t->base_opcode == 0x90
0dfbf9d7
L		 4783 && operand_type_equal (&i.types [0], &acc32)
4784 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4785 continue;
b6169b20
L		 4786 if (i.swap_operand)
4787 {
4788 /* If we swap operand in encoding, we either match
4789 the next one or reverse direction of operands. */
4790 if (t->opcode_modifier.s)
4791 continue;
4792 else if (t->opcode_modifier.d)
4793 goto check_reverse;
4794 }
4795
29b0f896 4796 case 3:
fa99fab2
L		 4797 /* If we swap operand in encoding, we match the next one. */
4798 if (i.swap_operand && t->opcode_modifier.s)
4799 continue;
f48ff2ae 4800 case 4:
c0f3af97 4801 case 5:
c6fb90c8 4802 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4803 if (!operand_type_match (overlap0, i.types[0])
4804 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4805 || (check_register
4806 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4807 operand_types[0],
4808 overlap1, i.types[1],
4809 operand_types[1])))
29b0f896
AM		 4810 {
4811 /* Check if other direction is valid ... */
40fb9820 4812 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4813 continue;
4814
b6169b20 4815check_reverse:
29b0f896 4816 /* Try reversing direction of operands. */
c6fb90c8
L		 4817 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4818 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4819 if (!operand_type_match (overlap0, i.types[0])
4820 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4821 || (check_register
4822 && !operand_type_register_match (overlap0,
4823 i.types[0],
4824 operand_types[1],
4825 overlap1,
4826 i.types[1],
4827 operand_types[0])))
29b0f896
AM		 4828 {
4829 /* Does not match either direction. */
4830 continue;
4831 }
4832 /* found_reverse_match holds which of D or FloatDR
4833 we've found. */
40fb9820 4834 if (t->opcode_modifier.d)
8a2ed489 4835 found_reverse_match = Opcode_D;
40fb9820 4836 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4837 found_reverse_match = Opcode_FloatD;
4838 else
4839 found_reverse_match = 0;
40fb9820 4840 if (t->opcode_modifier.floatr)
8a2ed489 4841 found_reverse_match |= Opcode_FloatR;
29b0f896 4842 }
f48ff2ae 4843 else
29b0f896 4844 {
f48ff2ae 4845 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4846 switch (t->operands)
4847 {
c0f3af97
L		 4848 case 5:
4849 overlap4 = operand_type_and (i.types[4],
4850 operand_types[4]);
d1cbb4db 4851 case 4:
c6fb90c8
L		 4852 overlap3 = operand_type_and (i.types[3],
4853 operand_types[3]);
d1cbb4db 4854 case 3:
c6fb90c8
L		 4855 overlap2 = operand_type_and (i.types[2],
4856 operand_types[2]);
d1cbb4db
L		 4857 break;
4858 }
29b0f896 4859
f48ff2ae
L		 4860 switch (t->operands)
4861 {
c0f3af97
L		 4862 case 5:
4863 if (!operand_type_match (overlap4, i.types[4])
4864 || !operand_type_register_match (overlap3,
4865 i.types[3],
4866 operand_types[3],
4867 overlap4,
4868 i.types[4],
4869 operand_types[4]))
4870 continue;
f48ff2ae 4871 case 4:
40fb9820 4872 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4873 || (check_register
4874 && !operand_type_register_match (overlap2,
4875 i.types[2],
4876 operand_types[2],
4877 overlap3,
4878 i.types[3],
4879 operand_types[3])))
f48ff2ae
L		 4880 continue;
4881 case 3:
4882 /* Here we make use of the fact that there are no
4883 reverse match 3 operand instructions, and all 3
4884 operand instructions only need to be checked for
4885 register consistency between operands 2 and 3. */
40fb9820 4886 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4887 || (check_register
4888 && !operand_type_register_match (overlap1,
4889 i.types[1],
4890 operand_types[1],
4891 overlap2,
4892 i.types[2],
4893 operand_types[2])))
f48ff2ae
L		 4894 continue;
4895 break;
4896 }
29b0f896 4897 }
f48ff2ae 4898 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4899 slip through to break. */
4900 }
3629bb00 4901 if (!found_cpu_match)
29b0f896
AM		 4902 {
4903 found_reverse_match = 0;
4904 continue;
4905 }
c0f3af97 4906
5614d22c
JB		 4907 /* Check if vector and VEX operands are valid. */
4908 if (check_VecOperands (t) || VEX_check_operands (t))
4909 {
4910 specific_error = i.error;
4911 continue;
4912 }
a683cc34 4913
29b0f896
AM		 4914 /* We've found a match; break out of loop. */
4915 break;
4916 }
4917
4918 if (t == current_templates->end)
4919 {
4920 /* We found no match. */
a65babc9 4921 const char *err_msg;
5614d22c 4922 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4923 {
4924 default:
4925 abort ();
86e026a4 4926 case operand_size_mismatch:
a65babc9
L		 4927 err_msg = _("operand size mismatch");
4928 break;
4929 case operand_type_mismatch:
4930 err_msg = _("operand type mismatch");
4931 break;
4932 case register_type_mismatch:
4933 err_msg = _("register type mismatch");
4934 break;
4935 case number_of_operands_mismatch:
4936 err_msg = _("number of operands mismatch");
4937 break;
4938 case invalid_instruction_suffix:
4939 err_msg = _("invalid instruction suffix");
4940 break;
4941 case bad_imm4:
4a2608e3 4942 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4943 break;
4944 case old_gcc_only:
4945 err_msg = _("only supported with old gcc");
4946 break;
4947 case unsupported_with_intel_mnemonic:
4948 err_msg = _("unsupported with Intel mnemonic");
4949 break;
4950 case unsupported_syntax:
4951 err_msg = _("unsupported syntax");
4952 break;
4953 case unsupported:
35262a23 4954 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4955 current_templates->start->name);
4956 return NULL;
6c30d220
L		 4957 case invalid_vsib_address:
4958 err_msg = _("invalid VSIB address");
4959 break;
7bab8ab5
JB		 4960 case invalid_vector_register_set:
4961 err_msg = _("mask, index, and destination registers must be distinct");
4962 break;
6c30d220
L		 4963 case unsupported_vector_index_register:
4964 err_msg = _("unsupported vector index register");
4965 break;
43234a1e
L		 4966 case unsupported_broadcast:
4967 err_msg = _("unsupported broadcast");
4968 break;
4969 case broadcast_not_on_src_operand:
4970 err_msg = _("broadcast not on source memory operand");
4971 break;
4972 case broadcast_needed:
4973 err_msg = _("broadcast is needed for operand of such type");
4974 break;
4975 case unsupported_masking:
4976 err_msg = _("unsupported masking");
4977 break;
4978 case mask_not_on_destination:
4979 err_msg = _("mask not on destination operand");
4980 break;
4981 case no_default_mask:
4982 err_msg = _("default mask isn't allowed");
4983 break;
4984 case unsupported_rc_sae:
4985 err_msg = _("unsupported static rounding/sae");
4986 break;
4987 case rc_sae_operand_not_last_imm:
4988 if (intel_syntax)
4989 err_msg = _("RC/SAE operand must precede immediate operands");
4990 else
4991 err_msg = _("RC/SAE operand must follow immediate operands");
4992 break;
4993 case invalid_register_operand:
4994 err_msg = _("invalid register operand");
4995 break;
a65babc9
L		 4996 }
4997 as_bad (_("%s for `%s'"), err_msg,
891edac4 4998 current_templates->start->name);
fa99fab2 4999 return NULL;
29b0f896 5000 }
252b5132 5001
29b0f896
AM		 5002 if (!quiet_warnings)
5003 {
5004 if (!intel_syntax
40fb9820
L		 5005 && (i.types[0].bitfield.jumpabsolute
5006 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5007 {
5008 as_warn (_("indirect %s without `*'"), t->name);
5009 }
5010
40fb9820
L		 5011 if (t->opcode_modifier.isprefix
5012 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5013 {
5014 /* Warn them that a data or address size prefix doesn't
5015 affect assembly of the next line of code. */
5016 as_warn (_("stand-alone `%s' prefix"), t->name);
5017 }
5018 }
5019
5020 /* Copy the template we found. */
5021 i.tm = *t;
539e75ad
L		 5022
5023 if (addr_prefix_disp != -1)
5024 i.tm.operand_types[addr_prefix_disp]
5025 = operand_types[addr_prefix_disp];
5026
29b0f896
AM		 5027 if (found_reverse_match)
5028 {
5029 /* If we found a reverse match we must alter the opcode
5030 direction bit. found_reverse_match holds bits to change
5031 (different for int & float insns). */
5032
5033 i.tm.base_opcode ^= found_reverse_match;
5034
539e75ad
L		 5035 i.tm.operand_types[0] = operand_types[1];
5036 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5037 }
5038
fa99fab2 5039 return t;
29b0f896
AM		 5040}
5041
5042static int
e3bb37b5 5043check_string (void)
29b0f896 5044{
40fb9820
L		 5045 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5046 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5047 {
5048 if (i.seg[0] != NULL && i.seg[0] != &es)
5049 {
a87af027 5050 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5051 i.tm.name,
a87af027
JB		 5052 mem_op + 1,
5053 register_prefix);
29b0f896
AM		 5054 return 0;
5055 }
5056 /* There's only ever one segment override allowed per instruction.
5057 This instruction possibly has a legal segment override on the
5058 second operand, so copy the segment to where non-string
5059 instructions store it, allowing common code. */
5060 i.seg[0] = i.seg[1];
5061 }
40fb9820 5062 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5063 {
5064 if (i.seg[1] != NULL && i.seg[1] != &es)
5065 {
a87af027 5066 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5067 i.tm.name,
a87af027
JB		 5068 mem_op + 2,
5069 register_prefix);
29b0f896
AM		 5070 return 0;
5071 }
5072 }
5073 return 1;
5074}
5075
5076static int
543613e9 5077process_suffix (void)
29b0f896
AM		 5078{
5079 /* If matched instruction specifies an explicit instruction mnemonic
5080 suffix, use it. */
40fb9820
L		 5081 if (i.tm.opcode_modifier.size16)
5082 i.suffix = WORD_MNEM_SUFFIX;
5083 else if (i.tm.opcode_modifier.size32)
5084 i.suffix = LONG_MNEM_SUFFIX;
5085 else if (i.tm.opcode_modifier.size64)
5086 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5087 else if (i.reg_operands)
5088 {
5089 /* If there's no instruction mnemonic suffix we try to invent one
5090 based on register operands. */
5091 if (!i.suffix)
5092 {
5093 /* We take i.suffix from the last register operand specified,
5094 Destination register type is more significant than source
381d071f
L		 5095 register type. crc32 in SSE4.2 prefers source register
5096 type. */
5097 if (i.tm.base_opcode == 0xf20f38f1)
5098 {
40fb9820
L		 5099 if (i.types[0].bitfield.reg16)
5100 i.suffix = WORD_MNEM_SUFFIX;
5101 else if (i.types[0].bitfield.reg32)
5102 i.suffix = LONG_MNEM_SUFFIX;
5103 else if (i.types[0].bitfield.reg64)
5104 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5105 }
9344ff29 5106 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5107 {
40fb9820 5108 if (i.types[0].bitfield.reg8)
20592a94
L		 5109 i.suffix = BYTE_MNEM_SUFFIX;
5110 }
381d071f
L		 5111
5112 if (!i.suffix)
5113 {
5114 int op;
5115
20592a94
L		 5116 if (i.tm.base_opcode == 0xf20f38f1
5117 || i.tm.base_opcode == 0xf20f38f0)
5118 {
5119 /* We have to know the operand size for crc32. */
5120 as_bad (_("ambiguous memory operand size for `%s`"),
5121 i.tm.name);
5122 return 0;
5123 }
5124
381d071f 5125 for (op = i.operands; --op >= 0;)
40fb9820 5126 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5127 {
40fb9820
L		 5128 if (i.types[op].bitfield.reg8)
5129 {
5130 i.suffix = BYTE_MNEM_SUFFIX;
5131 break;
5132 }
5133 else if (i.types[op].bitfield.reg16)
5134 {
5135 i.suffix = WORD_MNEM_SUFFIX;
5136 break;
5137 }
5138 else if (i.types[op].bitfield.reg32)
5139 {
5140 i.suffix = LONG_MNEM_SUFFIX;
5141 break;
5142 }
5143 else if (i.types[op].bitfield.reg64)
5144 {
5145 i.suffix = QWORD_MNEM_SUFFIX;
5146 break;
5147 }
381d071f
L		 5148 }
5149 }
29b0f896
AM		 5150 }
5151 else if (i.suffix == BYTE_MNEM_SUFFIX)
5152 {
2eb952a4
L		 5153 if (intel_syntax
5154 && i.tm.opcode_modifier.ignoresize
5155 && i.tm.opcode_modifier.no_bsuf)
5156 i.suffix = 0;
5157 else if (!check_byte_reg ())
29b0f896
AM		 5158 return 0;
5159 }
5160 else if (i.suffix == LONG_MNEM_SUFFIX)
5161 {
2eb952a4
L		 5162 if (intel_syntax
5163 && i.tm.opcode_modifier.ignoresize
5164 && i.tm.opcode_modifier.no_lsuf)
5165 i.suffix = 0;
5166 else if (!check_long_reg ())
29b0f896
AM		 5167 return 0;
5168 }
5169 else if (i.suffix == QWORD_MNEM_SUFFIX)
5170 {
955e1e6a
L		 5171 if (intel_syntax
5172 && i.tm.opcode_modifier.ignoresize
5173 && i.tm.opcode_modifier.no_qsuf)
5174 i.suffix = 0;
5175 else if (!check_qword_reg ())
29b0f896
AM		 5176 return 0;
5177 }
5178 else if (i.suffix == WORD_MNEM_SUFFIX)
5179 {
2eb952a4
L		 5180 if (intel_syntax
5181 && i.tm.opcode_modifier.ignoresize
5182 && i.tm.opcode_modifier.no_wsuf)
5183 i.suffix = 0;
5184 else if (!check_word_reg ())
29b0f896
AM		 5185 return 0;
5186 }
c0f3af97 5187 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5188 || i.suffix == YMMWORD_MNEM_SUFFIX
5189 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5190 {
43234a1e 5191 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5192 should check if it is a valid suffix. */
5193 }
40fb9820 5194 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5195 /* Do nothing if the instruction is going to ignore the prefix. */
5196 ;
5197 else
5198 abort ();
5199 }
40fb9820 5200 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5201 && !i.suffix
5202 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5203 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5204 {
5205 i.suffix = stackop_size;
5206 }
9306ca4a
JB		 5207 else if (intel_syntax
5208 && !i.suffix
40fb9820
L		 5209 && (i.tm.operand_types[0].bitfield.jumpabsolute
5210 || i.tm.opcode_modifier.jumpbyte
5211 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5212 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5213 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5214 {
5215 switch (flag_code)
5216 {
5217 case CODE_64BIT:
40fb9820 5218 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5219 {
5220 i.suffix = QWORD_MNEM_SUFFIX;
5221 break;
5222 }
5223 case CODE_32BIT:
40fb9820 5224 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5225 i.suffix = LONG_MNEM_SUFFIX;
5226 break;
5227 case CODE_16BIT:
40fb9820 5228 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5229 i.suffix = WORD_MNEM_SUFFIX;
5230 break;
5231 }
5232 }
252b5132 5233
9306ca4a 5234 if (!i.suffix)
29b0f896 5235 {
9306ca4a
JB		 5236 if (!intel_syntax)
5237 {
40fb9820 5238 if (i.tm.opcode_modifier.w)
9306ca4a 5239 {
4eed87de
AM		 5240 as_bad (_("no instruction mnemonic suffix given and "
5241 "no register operands; can't size instruction"));
9306ca4a
JB		 5242 return 0;
5243 }
5244 }
5245 else
5246 {
40fb9820 5247 unsigned int suffixes;
7ab9ffdd 5248
40fb9820
L		 5249 suffixes = !i.tm.opcode_modifier.no_bsuf;
5250 if (!i.tm.opcode_modifier.no_wsuf)
5251 suffixes |= 1 << 1;
5252 if (!i.tm.opcode_modifier.no_lsuf)
5253 suffixes |= 1 << 2;
fc4adea1 5254 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5255 suffixes |= 1 << 3;
5256 if (!i.tm.opcode_modifier.no_ssuf)
5257 suffixes |= 1 << 4;
5258 if (!i.tm.opcode_modifier.no_qsuf)
5259 suffixes |= 1 << 5;
5260
5261 /* There are more than suffix matches. */
5262 if (i.tm.opcode_modifier.w
9306ca4a 5263 || ((suffixes & (suffixes - 1))
40fb9820
L		 5264 && !i.tm.opcode_modifier.defaultsize
5265 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5266 {
5267 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5268 return 0;
5269 }
5270 }
29b0f896 5271 }
252b5132 5272
9306ca4a
JB		 5273 /* Change the opcode based on the operand size given by i.suffix;
5274 We don't need to change things for byte insns. */
5275
582d5edd
L		 5276 if (i.suffix
5277 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5278 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5279 && i.suffix != YMMWORD_MNEM_SUFFIX
5280 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5281 {
5282 /* It's not a byte, select word/dword operation. */
40fb9820 5283 if (i.tm.opcode_modifier.w)
29b0f896 5284 {
40fb9820 5285 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5286 i.tm.base_opcode |= 8;
5287 else
5288 i.tm.base_opcode |= 1;
5289 }
0f3f3d8b 5290
29b0f896
AM		 5291 /* Now select between word & dword operations via the operand
5292 size prefix, except for instructions that will ignore this
5293 prefix anyway. */
ca61edf2 5294 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5295 {
ca61edf2
L		 5296 /* The address size override prefix changes the size of the
5297 first operand. */
40fb9820
L		 5298 if ((flag_code == CODE_32BIT
5299 && i.op->regs[0].reg_type.bitfield.reg16)
5300 || (flag_code != CODE_32BIT
5301 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5302 if (!add_prefix (ADDR_PREFIX_OPCODE))
5303 return 0;
5304 }
5305 else if (i.suffix != QWORD_MNEM_SUFFIX
5306 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5307 && !i.tm.opcode_modifier.ignoresize
5308 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5309 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5310 || (flag_code == CODE_64BIT
40fb9820 5311 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5312 {
5313 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5314
40fb9820 5315 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5316 prefix = ADDR_PREFIX_OPCODE;
252b5132 5317
29b0f896
AM		 5318 if (!add_prefix (prefix))
5319 return 0;
24eab124 5320 }
252b5132 5321
29b0f896
AM		 5322 /* Set mode64 for an operand. */
5323 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5324 && flag_code == CODE_64BIT
40fb9820 5325 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5326 {
5327 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5328 need rex64. cmpxchg8b is also a special case. */
5329 if (! (i.operands == 2
5330 && i.tm.base_opcode == 0x90
5331 && i.tm.extension_opcode == None
0dfbf9d7
L		 5332 && operand_type_equal (&i.types [0], &acc64)
5333 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5334 && ! (i.operands == 1
5335 && i.tm.base_opcode == 0xfc7
5336 && i.tm.extension_opcode == 1
40fb9820
L		 5337 && !operand_type_check (i.types [0], reg)
5338 && operand_type_check (i.types [0], anymem)))
f6bee062 5339 i.rex |= REX_W;
46e883c5 5340 }
3e73aa7c 5341
29b0f896
AM		 5342 /* Size floating point instruction. */
5343 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5344 if (i.tm.opcode_modifier.floatmf)
543613e9 5345 i.tm.base_opcode ^= 4;
29b0f896 5346 }
7ecd2f8b 5347
29b0f896
AM		 5348 return 1;
5349}
3e73aa7c 5350
29b0f896 5351static int
543613e9 5352check_byte_reg (void)
29b0f896
AM		 5353{
5354 int op;
543613e9 5355
29b0f896
AM		 5356 for (op = i.operands; --op >= 0;)
5357 {
5358 /* If this is an eight bit register, it's OK. If it's the 16 or
5359 32 bit version of an eight bit register, we will just use the
5360 low portion, and that's OK too. */
40fb9820 5361 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5362 continue;
5363
5a819eb9
JB		 5364 /* I/O port address operands are OK too. */
5365 if (i.tm.operand_types[op].bitfield.inoutportreg)
5366 continue;
5367
9344ff29
L		 5368 /* crc32 doesn't generate this warning. */
5369 if (i.tm.base_opcode == 0xf20f38f0)
5370 continue;
5371
40fb9820
L		 5372 if ((i.types[op].bitfield.reg16
5373 || i.types[op].bitfield.reg32
5374 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5375 && i.op[op].regs->reg_num < 4
5376 /* Prohibit these changes in 64bit mode, since the lowering
5377 would be more complicated. */
5378 && flag_code != CODE_64BIT)
29b0f896 5379 {
29b0f896 5380#if REGISTER_WARNINGS
5a819eb9 5381 if (!quiet_warnings)
a540244d
L		 5382 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5383 register_prefix,
40fb9820 5384 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5385 ? REGNAM_AL - REGNAM_AX
5386 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5387 register_prefix,
29b0f896
AM		 5388 i.op[op].regs->reg_name,
5389 i.suffix);
5390#endif
5391 continue;
5392 }
5393 /* Any other register is bad. */
40fb9820
L		 5394 if (i.types[op].bitfield.reg16
5395 || i.types[op].bitfield.reg32
5396 || i.types[op].bitfield.reg64
5397 || i.types[op].bitfield.regmmx
5398 || i.types[op].bitfield.regxmm
c0f3af97 5399 || i.types[op].bitfield.regymm
43234a1e 5400 || i.types[op].bitfield.regzmm
40fb9820
L		 5401 || i.types[op].bitfield.sreg2
5402 || i.types[op].bitfield.sreg3
5403 || i.types[op].bitfield.control
5404 || i.types[op].bitfield.debug
5405 || i.types[op].bitfield.test
5406 || i.types[op].bitfield.floatreg
5407 || i.types[op].bitfield.floatacc)
29b0f896 5408 {
a540244d
L		 5409 as_bad (_("`%s%s' not allowed with `%s%c'"),
5410 register_prefix,
29b0f896
AM		 5411 i.op[op].regs->reg_name,
5412 i.tm.name,
5413 i.suffix);
5414 return 0;
5415 }
5416 }
5417 return 1;
5418}
5419
5420static int
e3bb37b5 5421check_long_reg (void)
29b0f896
AM		 5422{
5423 int op;
5424
5425 for (op = i.operands; --op >= 0;)
5426 /* Reject eight bit registers, except where the template requires
5427 them. (eg. movzb) */
40fb9820
L		 5428 if (i.types[op].bitfield.reg8
5429 && (i.tm.operand_types[op].bitfield.reg16
5430 || i.tm.operand_types[op].bitfield.reg32
5431 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5432 {
a540244d
L		 5433 as_bad (_("`%s%s' not allowed with `%s%c'"),
5434 register_prefix,
29b0f896
AM		 5435 i.op[op].regs->reg_name,
5436 i.tm.name,
5437 i.suffix);
5438 return 0;
5439 }
e4630f71 5440 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5441 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5442 && i.types[op].bitfield.reg16
5443 && (i.tm.operand_types[op].bitfield.reg32
5444 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5445 {
5446 /* Prohibit these changes in the 64bit mode, since the
5447 lowering is more complicated. */
5448 if (flag_code == CODE_64BIT)
252b5132 5449 {
2b5d6a91 5450 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5451 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5452 i.suffix);
5453 return 0;
252b5132 5454 }
29b0f896 5455#if REGISTER_WARNINGS
cecf1424
JB		 5456 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5457 register_prefix,
5458 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5459 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5460#endif
252b5132 5461 }
e4630f71 5462 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5463 else if (i.types[op].bitfield.reg64
5464 && (i.tm.operand_types[op].bitfield.reg32
5465 || i.tm.operand_types[op].bitfield.acc))
252b5132 5466 {
34828aad 5467 if (intel_syntax
ca61edf2 5468 && i.tm.opcode_modifier.toqword
40fb9820 5469 && !i.types[0].bitfield.regxmm)
34828aad 5470 {
ca61edf2 5471 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5472 i.suffix = QWORD_MNEM_SUFFIX;
5473 }
5474 else
5475 {
2b5d6a91 5476 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5477 register_prefix, i.op[op].regs->reg_name,
5478 i.suffix);
5479 return 0;
5480 }
29b0f896
AM		 5481 }
5482 return 1;
5483}
252b5132 5484
29b0f896 5485static int
e3bb37b5 5486check_qword_reg (void)
29b0f896
AM		 5487{
5488 int op;
252b5132 5489
29b0f896
AM		 5490 for (op = i.operands; --op >= 0; )
5491 /* Reject eight bit registers, except where the template requires
5492 them. (eg. movzb) */
40fb9820
L		 5493 if (i.types[op].bitfield.reg8
5494 && (i.tm.operand_types[op].bitfield.reg16
5495 || i.tm.operand_types[op].bitfield.reg32
5496 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5497 {
a540244d
L		 5498 as_bad (_("`%s%s' not allowed with `%s%c'"),
5499 register_prefix,
29b0f896
AM		 5500 i.op[op].regs->reg_name,
5501 i.tm.name,
5502 i.suffix);
5503 return 0;
5504 }
e4630f71 5505 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5506 else if ((i.types[op].bitfield.reg16
5507 || i.types[op].bitfield.reg32)
5508 && (i.tm.operand_types[op].bitfield.reg32
5509 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5510 {
5511 /* Prohibit these changes in the 64bit mode, since the
5512 lowering is more complicated. */
34828aad 5513 if (intel_syntax
ca61edf2 5514 && i.tm.opcode_modifier.todword
40fb9820 5515 && !i.types[0].bitfield.regxmm)
34828aad 5516 {
ca61edf2 5517 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5518 i.suffix = LONG_MNEM_SUFFIX;
5519 }
5520 else
5521 {
2b5d6a91 5522 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5523 register_prefix, i.op[op].regs->reg_name,
5524 i.suffix);
5525 return 0;
5526 }
252b5132 5527 }
29b0f896
AM		 5528 return 1;
5529}
252b5132 5530
29b0f896 5531static int
e3bb37b5 5532check_word_reg (void)
29b0f896
AM		 5533{
5534 int op;
5535 for (op = i.operands; --op >= 0;)
5536 /* Reject eight bit registers, except where the template requires
5537 them. (eg. movzb) */
40fb9820
L		 5538 if (i.types[op].bitfield.reg8
5539 && (i.tm.operand_types[op].bitfield.reg16
5540 || i.tm.operand_types[op].bitfield.reg32
5541 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5542 {
a540244d
L		 5543 as_bad (_("`%s%s' not allowed with `%s%c'"),
5544 register_prefix,
29b0f896
AM		 5545 i.op[op].regs->reg_name,
5546 i.tm.name,
5547 i.suffix);
5548 return 0;
5549 }
e4630f71 5550 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5551 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5552 && (i.types[op].bitfield.reg32
5553 || i.types[op].bitfield.reg64)
40fb9820
L		 5554 && (i.tm.operand_types[op].bitfield.reg16
5555 || i.tm.operand_types[op].bitfield.acc))
252b5132 5556 {
29b0f896
AM		 5557 /* Prohibit these changes in the 64bit mode, since the
5558 lowering is more complicated. */
5559 if (flag_code == CODE_64BIT)
252b5132 5560 {
2b5d6a91 5561 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5562 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5563 i.suffix);
5564 return 0;
252b5132 5565 }
29b0f896 5566#if REGISTER_WARNINGS
cecf1424
JB		 5567 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5568 register_prefix,
5569 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5570 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5571#endif
5572 }
5573 return 1;
5574}
252b5132 5575
29b0f896 5576static int
40fb9820 5577update_imm (unsigned int j)
29b0f896 5578{
bc0844ae 5579 i386_operand_type overlap = i.types[j];
40fb9820
L		 5580 if ((overlap.bitfield.imm8
5581 || overlap.bitfield.imm8s
5582 || overlap.bitfield.imm16
5583 || overlap.bitfield.imm32
5584 || overlap.bitfield.imm32s
5585 || overlap.bitfield.imm64)
0dfbf9d7
L		 5586 && !operand_type_equal (&overlap, &imm8)
5587 && !operand_type_equal (&overlap, &imm8s)
5588 && !operand_type_equal (&overlap, &imm16)
5589 && !operand_type_equal (&overlap, &imm32)
5590 && !operand_type_equal (&overlap, &imm32s)
5591 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5592 {
5593 if (i.suffix)
5594 {
40fb9820
L		 5595 i386_operand_type temp;
5596
0dfbf9d7 5597 operand_type_set (&temp, 0);
7ab9ffdd 5598 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5599 {
5600 temp.bitfield.imm8 = overlap.bitfield.imm8;
5601 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5602 }
5603 else if (i.suffix == WORD_MNEM_SUFFIX)
5604 temp.bitfield.imm16 = overlap.bitfield.imm16;
5605 else if (i.suffix == QWORD_MNEM_SUFFIX)
5606 {
5607 temp.bitfield.imm64 = overlap.bitfield.imm64;
5608 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5609 }
5610 else
5611 temp.bitfield.imm32 = overlap.bitfield.imm32;
5612 overlap = temp;
29b0f896 5613 }
0dfbf9d7
L		 5614 else if (operand_type_equal (&overlap, &imm16_32_32s)
5615 || operand_type_equal (&overlap, &imm16_32)
5616 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5617 {
40fb9820 5618 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5619 overlap = imm16;
40fb9820 5620 else
65da13b5 5621 overlap = imm32s;
29b0f896 5622 }
0dfbf9d7
L		 5623 if (!operand_type_equal (&overlap, &imm8)
5624 && !operand_type_equal (&overlap, &imm8s)
5625 && !operand_type_equal (&overlap, &imm16)
5626 && !operand_type_equal (&overlap, &imm32)
5627 && !operand_type_equal (&overlap, &imm32s)
5628 && !operand_type_equal (&overlap, &imm64))
29b0f896 5629 {
4eed87de
AM		 5630 as_bad (_("no instruction mnemonic suffix given; "
5631 "can't determine immediate size"));
29b0f896
AM		 5632 return 0;
5633 }
5634 }
40fb9820 5635 i.types[j] = overlap;
29b0f896 5636
40fb9820
L		 5637 return 1;
5638}
5639
5640static int
5641finalize_imm (void)
5642{
bc0844ae 5643 unsigned int j, n;
29b0f896 5644
bc0844ae
L		 5645 /* Update the first 2 immediate operands. */
5646 n = i.operands > 2 ? 2 : i.operands;
5647 if (n)
5648 {
5649 for (j = 0; j < n; j++)
5650 if (update_imm (j) == 0)
5651 return 0;
40fb9820 5652
bc0844ae
L		 5653 /* The 3rd operand can't be immediate operand. */
5654 gas_assert (operand_type_check (i.types[2], imm) == 0);
5655 }
29b0f896
AM		 5656
5657 return 1;
5658}
5659
c0f3af97
L		 5660static int
5661bad_implicit_operand (int xmm)
5662{
91d6fa6a
NC		 5663 const char *ireg = xmm ? "xmm0" : "ymm0";
5664
c0f3af97
L		 5665 if (intel_syntax)
5666 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5667 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5668 else
5669 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5670 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5671 return 0;
5672}
5673
29b0f896 5674static int
e3bb37b5 5675process_operands (void)
29b0f896
AM		 5676{
5677 /* Default segment register this instruction will use for memory
5678 accesses. 0 means unknown. This is only for optimizing out
5679 unnecessary segment overrides. */
5680 const seg_entry *default_seg = 0;
5681
2426c15f 5682 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5683 {
91d6fa6a
NC		 5684 unsigned int dupl = i.operands;
5685 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5686 unsigned int j;
5687
c0f3af97 5688 /* The destination must be an xmm register. */
9c2799c2 5689 gas_assert (i.reg_operands
91d6fa6a 5690 && MAX_OPERANDS > dupl
7ab9ffdd 5691 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5692
5693 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5694 {
c0f3af97 5695 /* The first operand is implicit and must be xmm0. */
9c2799c2 5696 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5697 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5698 return bad_implicit_operand (1);
5699
8cd7925b 5700 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5701 {
5702 /* Keep xmm0 for instructions with VEX prefix and 3
5703 sources. */
5704 goto duplicate;
5705 }
e2ec9d29 5706 else
c0f3af97
L		 5707 {
5708 /* We remove the first xmm0 and keep the number of
5709 operands unchanged, which in fact duplicates the
5710 destination. */
5711 for (j = 1; j < i.operands; j++)
5712 {
5713 i.op[j - 1] = i.op[j];
5714 i.types[j - 1] = i.types[j];
5715 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5716 }
5717 }
5718 }
5719 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5720 {
91d6fa6a 5721 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5722 && (i.tm.opcode_modifier.vexsources
5723 == VEX3SOURCES));
c0f3af97
L		 5724
5725 /* Add the implicit xmm0 for instructions with VEX prefix
5726 and 3 sources. */
5727 for (j = i.operands; j > 0; j--)
5728 {
5729 i.op[j] = i.op[j - 1];
5730 i.types[j] = i.types[j - 1];
5731 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5732 }
5733 i.op[0].regs
5734 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5735 i.types[0] = regxmm;
c0f3af97
L		 5736 i.tm.operand_types[0] = regxmm;
5737
5738 i.operands += 2;
5739 i.reg_operands += 2;
5740 i.tm.operands += 2;
5741
91d6fa6a 5742 dupl++;
c0f3af97 5743 dest++;
91d6fa6a
NC		 5744 i.op[dupl] = i.op[dest];
5745 i.types[dupl] = i.types[dest];
5746 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5747 }
c0f3af97
L		 5748 else
5749 {
5750duplicate:
5751 i.operands++;
5752 i.reg_operands++;
5753 i.tm.operands++;
5754
91d6fa6a
NC		 5755 i.op[dupl] = i.op[dest];
5756 i.types[dupl] = i.types[dest];
5757 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5758 }
5759
5760 if (i.tm.opcode_modifier.immext)
5761 process_immext ();
5762 }
5763 else if (i.tm.opcode_modifier.firstxmm0)
5764 {
5765 unsigned int j;
5766
43234a1e 5767 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5768 gas_assert (i.reg_operands
7ab9ffdd 5769 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5770 || operand_type_equal (&i.types[0], &regymm)
5771 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5772 if (register_number (i.op[0].regs) != 0)
c0f3af97 5773 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5774
5775 for (j = 1; j < i.operands; j++)
5776 {
5777 i.op[j - 1] = i.op[j];
5778 i.types[j - 1] = i.types[j];
5779
5780 /* We need to adjust fields in i.tm since they are used by
5781 build_modrm_byte. */
5782 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5783 }
5784
e2ec9d29
L		 5785 i.operands--;
5786 i.reg_operands--;
e2ec9d29
L		 5787 i.tm.operands--;
5788 }
5789 else if (i.tm.opcode_modifier.regkludge)
5790 {
5791 /* The imul $imm, %reg instruction is converted into
5792 imul $imm, %reg, %reg, and the clr %reg instruction
5793 is converted into xor %reg, %reg. */
5794
5795 unsigned int first_reg_op;
5796
5797 if (operand_type_check (i.types[0], reg))
5798 first_reg_op = 0;
5799 else
5800 first_reg_op = 1;
5801 /* Pretend we saw the extra register operand. */
9c2799c2 5802 gas_assert (i.reg_operands == 1
7ab9ffdd 5803 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5804 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5805 i.types[first_reg_op + 1] = i.types[first_reg_op];
5806 i.operands++;
5807 i.reg_operands++;
29b0f896
AM		 5808 }
5809
40fb9820 5810 if (i.tm.opcode_modifier.shortform)
29b0f896 5811 {
40fb9820
L		 5812 if (i.types[0].bitfield.sreg2
5813 || i.types[0].bitfield.sreg3)
29b0f896 5814 {
4eed87de
AM		 5815 if (i.tm.base_opcode == POP_SEG_SHORT
5816 && i.op[0].regs->reg_num == 1)
29b0f896 5817 {
a87af027 5818 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5819 return 0;
29b0f896 5820 }
4eed87de
AM		 5821 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5822 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5823 i.rex |= REX_B;
4eed87de
AM		 5824 }
5825 else
5826 {
7ab9ffdd 5827 /* The register or float register operand is in operand
85f10a01 5828 0 or 1. */
40fb9820 5829 unsigned int op;
7ab9ffdd
L		 5830
5831 if (i.types[0].bitfield.floatreg
5832 || operand_type_check (i.types[0], reg))
5833 op = 0;
5834 else
5835 op = 1;
4eed87de
AM		 5836 /* Register goes in low 3 bits of opcode. */
5837 i.tm.base_opcode |= i.op[op].regs->reg_num;
5838 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5839 i.rex |= REX_B;
40fb9820 5840 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5841 {
4eed87de
AM		 5842 /* Warn about some common errors, but press on regardless.
5843 The first case can be generated by gcc (<= 2.8.1). */
5844 if (i.operands == 2)
5845 {
5846 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5847 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5848 register_prefix, i.op[!intel_syntax].regs->reg_name,
5849 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5850 }
5851 else
5852 {
5853 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5854 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5855 register_prefix, i.op[0].regs->reg_name);
4eed87de 5856 }
29b0f896
AM		 5857 }
5858 }
5859 }
40fb9820 5860 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5861 {
5862 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5863 must be put into the modrm byte). Now, we make the modrm and
5864 index base bytes based on all the info we've collected. */
29b0f896
AM		 5865
5866 default_seg = build_modrm_byte ();
5867 }
8a2ed489 5868 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5869 {
5870 default_seg = &ds;
5871 }
40fb9820 5872 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5873 {
5874 /* For the string instructions that allow a segment override
5875 on one of their operands, the default segment is ds. */
5876 default_seg = &ds;
5877 }
5878
75178d9d
L		 5879 if (i.tm.base_opcode == 0x8d /* lea */
5880 && i.seg[0]
5881 && !quiet_warnings)
30123838 5882 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5883
5884 /* If a segment was explicitly specified, and the specified segment
5885 is not the default, use an opcode prefix to select it. If we
5886 never figured out what the default segment is, then default_seg
5887 will be zero at this point, and the specified segment prefix will
5888 always be used. */
29b0f896
AM		 5889 if ((i.seg[0]) && (i.seg[0] != default_seg))
5890 {
5891 if (!add_prefix (i.seg[0]->seg_prefix))
5892 return 0;
5893 }
5894 return 1;
5895}
5896
5897static const seg_entry *
e3bb37b5 5898build_modrm_byte (void)
29b0f896
AM		 5899{
5900 const seg_entry *default_seg = 0;
c0f3af97 5901 unsigned int source, dest;
8cd7925b 5902 int vex_3_sources;
c0f3af97
L		 5903
5904 /* The first operand of instructions with VEX prefix and 3 sources
5905 must be VEX_Imm4. */
8cd7925b 5906 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5907 if (vex_3_sources)
5908 {
91d6fa6a 5909 unsigned int nds, reg_slot;
4c2c6516 5910 expressionS *exp;
c0f3af97 5911
922d8de8 5912 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5913 && i.tm.opcode_modifier.immext)
5914 {
5915 dest = i.operands - 2;
5916 gas_assert (dest == 3);
5917 }
922d8de8 5918 else
a683cc34 5919 dest = i.operands - 1;
c0f3af97 5920 nds = dest - 1;
922d8de8 5921
a683cc34
SP		 5922 /* There are 2 kinds of instructions:
5923 1. 5 operands: 4 register operands or 3 register operands
5924 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5925 VexW0 or VexW1. The destination must be either XMM, YMM or
5926 ZMM register.
a683cc34
SP		 5927 2. 4 operands: 4 register operands or 3 register operands
5928 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5929 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5930 || (i.reg_operands == 3 && i.mem_operands == 1))
5931 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5932 && (i.tm.opcode_modifier.veximmext
5933 || (i.imm_operands == 1
5934 && i.types[0].bitfield.vec_imm4
5935 && (i.tm.opcode_modifier.vexw == VEXW0
5936 || i.tm.opcode_modifier.vexw == VEXW1)
5937 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5938 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5939 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5940
5941 if (i.imm_operands == 0)
5942 {
5943 /* When there is no immediate operand, generate an 8bit
5944 immediate operand to encode the first operand. */
5945 exp = &im_expressions[i.imm_operands++];
5946 i.op[i.operands].imms = exp;
5947 i.types[i.operands] = imm8;
5948 i.operands++;
5949 /* If VexW1 is set, the first operand is the source and
5950 the second operand is encoded in the immediate operand. */
5951 if (i.tm.opcode_modifier.vexw == VEXW1)
5952 {
5953 source = 0;
5954 reg_slot = 1;
5955 }
5956 else
5957 {
5958 source = 1;
5959 reg_slot = 0;
5960 }
5961
5962 /* FMA swaps REG and NDS. */
5963 if (i.tm.cpu_flags.bitfield.cpufma)
5964 {
5965 unsigned int tmp;
5966 tmp = reg_slot;
5967 reg_slot = nds;
5968 nds = tmp;
5969 }
5970
24981e7b
L		 5971 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5972 &regxmm)
a683cc34 5973 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 5974 &regymm)
5975 || operand_type_equal (&i.tm.operand_types[reg_slot],
5976 &regzmm));
a683cc34 5977 exp->X_op = O_constant;
4c692bc7 5978 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 5979 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
5980 }
922d8de8 5981 else
a683cc34
SP		 5982 {
5983 unsigned int imm_slot;
5984
5985 if (i.tm.opcode_modifier.vexw == VEXW0)
5986 {
5987 /* If VexW0 is set, the third operand is the source and
5988 the second operand is encoded in the immediate
5989 operand. */
5990 source = 2;
5991 reg_slot = 1;
5992 }
5993 else
5994 {
5995 /* VexW1 is set, the second operand is the source and
5996 the third operand is encoded in the immediate
5997 operand. */
5998 source = 1;
5999 reg_slot = 2;
6000 }
6001
6002 if (i.tm.opcode_modifier.immext)
6003 {
6004 /* When ImmExt is set, the immdiate byte is the last
6005 operand. */
6006 imm_slot = i.operands - 1;
6007 source--;
6008 reg_slot--;
6009 }
6010 else
6011 {
6012 imm_slot = 0;
6013
6014 /* Turn on Imm8 so that output_imm will generate it. */
6015 i.types[imm_slot].bitfield.imm8 = 1;
6016 }
6017
24981e7b
L		 6018 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6019 &regxmm)
6020 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6021 &regymm)
6022 || operand_type_equal (&i.tm.operand_types[reg_slot],
6023 &regzmm));
a683cc34 6024 i.op[imm_slot].imms->X_add_number
4c692bc7 6025 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6026 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6027 }
6028
6029 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6030 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6031 &regymm)
6032 || operand_type_equal (&i.tm.operand_types[nds],
6033 &regzmm));
dae39acc 6034 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6035 }
6036 else
6037 source = dest = 0;
29b0f896
AM		 6038
6039 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6040 implicit registers do not count. If there are 3 register
6041 operands, it must be a instruction with VexNDS. For a
6042 instruction with VexNDD, the destination register is encoded
6043 in VEX prefix. If there are 4 register operands, it must be
6044 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6045 if (i.mem_operands == 0
6046 && ((i.reg_operands == 2
2426c15f 6047 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6048 || (i.reg_operands == 3
2426c15f 6049 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6050 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6051 {
cab737b9
L		 6052 switch (i.operands)
6053 {
6054 case 2:
6055 source = 0;
6056 break;
6057 case 3:
c81128dc
L		 6058 /* When there are 3 operands, one of them may be immediate,
6059 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6060 the first operand must be shift count register (cl) or it
6061 is an instruction with VexNDS. */
9c2799c2 6062 gas_assert (i.imm_operands == 1
7ab9ffdd 6063 || (i.imm_operands == 0
2426c15f 6064 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6065 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6066 if (operand_type_check (i.types[0], imm)
6067 || i.types[0].bitfield.shiftcount)
6068 source = 1;
6069 else
6070 source = 0;
cab737b9
L		 6071 break;
6072 case 4:
368d64cc
L		 6073 /* When there are 4 operands, the first two must be 8bit
6074 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6075 one.
6076
6077 For instructions with VexNDS, if the first operand
6078 an imm8, the source operand is the 2nd one. If the last
6079 operand is imm8, the source operand is the first one. */
9c2799c2 6080 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6081 && i.types[0].bitfield.imm8
6082 && i.types[1].bitfield.imm8)
2426c15f 6083 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6084 && i.imm_operands == 1
6085 && (i.types[0].bitfield.imm8
43234a1e
L		 6086 || i.types[i.operands - 1].bitfield.imm8
6087 || i.rounding)));
9f2670f2
L		 6088 if (i.imm_operands == 2)
6089 source = 2;
6090 else
c0f3af97
L		 6091 {
6092 if (i.types[0].bitfield.imm8)
6093 source = 1;
6094 else
6095 source = 0;
6096 }
c0f3af97
L		 6097 break;
6098 case 5:
43234a1e
L		 6099 if (i.tm.opcode_modifier.evex)
6100 {
6101 /* For EVEX instructions, when there are 5 operands, the
6102 first one must be immediate operand. If the second one
6103 is immediate operand, the source operand is the 3th
6104 one. If the last one is immediate operand, the source
6105 operand is the 2nd one. */
6106 gas_assert (i.imm_operands == 2
6107 && i.tm.opcode_modifier.sae
6108 && operand_type_check (i.types[0], imm));
6109 if (operand_type_check (i.types[1], imm))
6110 source = 2;
6111 else if (operand_type_check (i.types[4], imm))
6112 source = 1;
6113 else
6114 abort ();
6115 }
cab737b9
L		 6116 break;
6117 default:
6118 abort ();
6119 }
6120
c0f3af97
L		 6121 if (!vex_3_sources)
6122 {
6123 dest = source + 1;
6124
43234a1e
L		 6125 /* RC/SAE operand could be between DEST and SRC. That happens
6126 when one operand is GPR and the other one is XMM/YMM/ZMM
6127 register. */
6128 if (i.rounding && i.rounding->operand == (int) dest)
6129 dest++;
6130
2426c15f 6131 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6132 {
43234a1e
L		 6133 /* For instructions with VexNDS, the register-only source
6134 operand must be 32/64bit integer, XMM, YMM or ZMM
6135 register. It is encoded in VEX prefix. We need to
6136 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6137
6138 i386_operand_type op;
6139 unsigned int vvvv;
6140
6141 /* Check register-only source operand when two source
6142 operands are swapped. */
6143 if (!i.tm.operand_types[source].bitfield.baseindex
6144 && i.tm.operand_types[dest].bitfield.baseindex)
6145 {
6146 vvvv = source;
6147 source = dest;
6148 }
6149 else
6150 vvvv = dest;
6151
6152 op = i.tm.operand_types[vvvv];
fa99fab2 6153 op.bitfield.regmem = 0;
c0f3af97 6154 if ((dest + 1) >= i.operands
ac4eb736
AM		 6155 || (!op.bitfield.reg32
6156 && op.bitfield.reg64
f12dc422 6157 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6158 && !operand_type_equal (&op, &regymm)
6159 && !operand_type_equal (&op, &regzmm)
6160 && !operand_type_equal (&op, &regmask)))
c0f3af97 6161 abort ();
f12dc422 6162 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6163 dest++;
6164 }
6165 }
29b0f896
AM		 6166
6167 i.rm.mode = 3;
6168 /* One of the register operands will be encoded in the i.tm.reg
6169 field, the other in the combined i.tm.mode and i.tm.regmem
6170 fields. If no form of this instruction supports a memory
6171 destination operand, then we assume the source operand may
6172 sometimes be a memory operand and so we need to store the
6173 destination in the i.rm.reg field. */
40fb9820
L		 6174 if (!i.tm.operand_types[dest].bitfield.regmem
6175 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6176 {
6177 i.rm.reg = i.op[dest].regs->reg_num;
6178 i.rm.regmem = i.op[source].regs->reg_num;
6179 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6180 i.rex |= REX_R;
43234a1e
L		 6181 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6182 i.vrex |= REX_R;
29b0f896 6183 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6184 i.rex |= REX_B;
43234a1e
L		 6185 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6186 i.vrex |= REX_B;
29b0f896
AM		 6187 }
6188 else
6189 {
6190 i.rm.reg = i.op[source].regs->reg_num;
6191 i.rm.regmem = i.op[dest].regs->reg_num;
6192 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6193 i.rex |= REX_B;
43234a1e
L		 6194 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6195 i.vrex |= REX_B;
29b0f896 6196 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6197 i.rex |= REX_R;
43234a1e
L		 6198 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6199 i.vrex |= REX_R;
29b0f896 6200 }
161a04f6 6201 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6202 {
40fb9820
L		 6203 if (!i.types[0].bitfield.control
6204 && !i.types[1].bitfield.control)
c4a530c5 6205 abort ();
161a04f6 6206 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6207 add_prefix (LOCK_PREFIX_OPCODE);
6208 }
29b0f896
AM		 6209 }
6210 else
6211 { /* If it's not 2 reg operands... */
c0f3af97
L		 6212 unsigned int mem;
6213
29b0f896
AM		 6214 if (i.mem_operands)
6215 {
6216 unsigned int fake_zero_displacement = 0;
99018f42 6217 unsigned int op;
4eed87de 6218
7ab9ffdd
L		 6219 for (op = 0; op < i.operands; op++)
6220 if (operand_type_check (i.types[op], anymem))
6221 break;
7ab9ffdd 6222 gas_assert (op < i.operands);
29b0f896 6223
6c30d220
L		 6224 if (i.tm.opcode_modifier.vecsib)
6225 {
6226 if (i.index_reg->reg_num == RegEiz
6227 || i.index_reg->reg_num == RegRiz)
6228 abort ();
6229
6230 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6231 if (!i.base_reg)
6232 {
6233 i.sib.base = NO_BASE_REGISTER;
6234 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6235 /* No Vec_Disp8 if there is no base. */
6236 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6237 i.types[op].bitfield.disp8 = 0;
6238 i.types[op].bitfield.disp16 = 0;
6239 i.types[op].bitfield.disp64 = 0;
6240 if (flag_code != CODE_64BIT)
6241 {
6242 /* Must be 32 bit */
6243 i.types[op].bitfield.disp32 = 1;
6244 i.types[op].bitfield.disp32s = 0;
6245 }
6246 else
6247 {
6248 i.types[op].bitfield.disp32 = 0;
6249 i.types[op].bitfield.disp32s = 1;
6250 }
6251 }
6252 i.sib.index = i.index_reg->reg_num;
6253 if ((i.index_reg->reg_flags & RegRex) != 0)
6254 i.rex |= REX_X;
43234a1e
L		 6255 if ((i.index_reg->reg_flags & RegVRex) != 0)
6256 i.vrex |= REX_X;
6c30d220
L		 6257 }
6258
29b0f896
AM		 6259 default_seg = &ds;
6260
6261 if (i.base_reg == 0)
6262 {
6263 i.rm.mode = 0;
6264 if (!i.disp_operands)
6c30d220
L		 6265 {
6266 fake_zero_displacement = 1;
6267 /* Instructions with VSIB byte need 32bit displacement
6268 if there is no base register. */
6269 if (i.tm.opcode_modifier.vecsib)
6270 i.types[op].bitfield.disp32 = 1;
6271 }
29b0f896
AM		 6272 if (i.index_reg == 0)
6273 {
6c30d220 6274 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6275 /* Operand is just <disp> */
20f0a1fc 6276 if (flag_code == CODE_64BIT)
29b0f896
AM		 6277 {
6278 /* 64bit mode overwrites the 32bit absolute
6279 addressing by RIP relative addressing and
6280 absolute addressing is encoded by one of the
6281 redundant SIB forms. */
6282 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6283 i.sib.base = NO_BASE_REGISTER;
6284 i.sib.index = NO_INDEX_REGISTER;
fc225355 6285 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6286 ? disp32s : disp32);
20f0a1fc 6287 }
fc225355
L		 6288 else if ((flag_code == CODE_16BIT)
6289 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6290 {
6291 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6292 i.types[op] = disp16;
20f0a1fc
NC		 6293 }
6294 else
6295 {
6296 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6297 i.types[op] = disp32;
29b0f896
AM		 6298 }
6299 }
6c30d220 6300 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6301 {
6c30d220 6302 /* !i.base_reg && i.index_reg */
db51cc60
L		 6303 if (i.index_reg->reg_num == RegEiz
6304 || i.index_reg->reg_num == RegRiz)
6305 i.sib.index = NO_INDEX_REGISTER;
6306 else
6307 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6308 i.sib.base = NO_BASE_REGISTER;
6309 i.sib.scale = i.log2_scale_factor;
6310 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6311 /* No Vec_Disp8 if there is no base. */
6312 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6313 i.types[op].bitfield.disp8 = 0;
6314 i.types[op].bitfield.disp16 = 0;
6315 i.types[op].bitfield.disp64 = 0;
29b0f896 6316 if (flag_code != CODE_64BIT)
40fb9820
L		 6317 {
6318 /* Must be 32 bit */
6319 i.types[op].bitfield.disp32 = 1;
6320 i.types[op].bitfield.disp32s = 0;
6321 }
29b0f896 6322 else
40fb9820
L		 6323 {
6324 i.types[op].bitfield.disp32 = 0;
6325 i.types[op].bitfield.disp32s = 1;
6326 }
29b0f896 6327 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6328 i.rex |= REX_X;
29b0f896
AM		 6329 }
6330 }
6331 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6332 else if (i.base_reg->reg_num == RegRip ||
6333 i.base_reg->reg_num == RegEip)
29b0f896 6334 {
6c30d220 6335 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6336 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6337 i.types[op].bitfield.disp8 = 0;
6338 i.types[op].bitfield.disp16 = 0;
6339 i.types[op].bitfield.disp32 = 0;
6340 i.types[op].bitfield.disp32s = 1;
6341 i.types[op].bitfield.disp64 = 0;
43234a1e 6342 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6343 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6344 if (! i.disp_operands)
6345 fake_zero_displacement = 1;
29b0f896 6346 }
40fb9820 6347 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6348 {
6c30d220 6349 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6350 switch (i.base_reg->reg_num)
6351 {
6352 case 3: /* (%bx) */
6353 if (i.index_reg == 0)
6354 i.rm.regmem = 7;
6355 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6356 i.rm.regmem = i.index_reg->reg_num - 6;
6357 break;
6358 case 5: /* (%bp) */
6359 default_seg = &ss;
6360 if (i.index_reg == 0)
6361 {
6362 i.rm.regmem = 6;
40fb9820 6363 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6364 {
6365 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6366 if (i.tm.operand_types[op].bitfield.vec_disp8)
6367 i.types[op].bitfield.vec_disp8 = 1;
6368 else
6369 i.types[op].bitfield.disp8 = 1;
252b5132 6370 fake_zero_displacement = 1;
29b0f896
AM		 6371 }
6372 }
6373 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6374 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6375 break;
6376 default: /* (%si) -> 4 or (%di) -> 5 */
6377 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6378 }
6379 i.rm.mode = mode_from_disp_size (i.types[op]);
6380 }
6381 else /* i.base_reg and 32/64 bit mode */
6382 {
6383 if (flag_code == CODE_64BIT
40fb9820
L		 6384 && operand_type_check (i.types[op], disp))
6385 {
6386 i386_operand_type temp;
0dfbf9d7 6387 operand_type_set (&temp, 0);
40fb9820 6388 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6389 temp.bitfield.vec_disp8
6390 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6391 i.types[op] = temp;
6392 if (i.prefix[ADDR_PREFIX] == 0)
6393 i.types[op].bitfield.disp32s = 1;
6394 else
6395 i.types[op].bitfield.disp32 = 1;
6396 }
20f0a1fc 6397
6c30d220
L		 6398 if (!i.tm.opcode_modifier.vecsib)
6399 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6400 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6401 i.rex |= REX_B;
29b0f896
AM		 6402 i.sib.base = i.base_reg->reg_num;
6403 /* x86-64 ignores REX prefix bit here to avoid decoder
6404 complications. */
848930b2
JB		 6405 if (!(i.base_reg->reg_flags & RegRex)
6406 && (i.base_reg->reg_num == EBP_REG_NUM
6407 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6408 default_seg = &ss;
848930b2 6409 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6410 {
848930b2 6411 fake_zero_displacement = 1;
43234a1e
L		 6412 if (i.tm.operand_types [op].bitfield.vec_disp8)
6413 i.types[op].bitfield.vec_disp8 = 1;
6414 else
6415 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6416 }
6417 i.sib.scale = i.log2_scale_factor;
6418 if (i.index_reg == 0)
6419 {
6c30d220 6420 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6421 /* <disp>(%esp) becomes two byte modrm with no index
6422 register. We've already stored the code for esp
6423 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6424 Any base register besides %esp will not use the
6425 extra modrm byte. */
6426 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6427 }
6c30d220 6428 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6429 {
db51cc60
L		 6430 if (i.index_reg->reg_num == RegEiz
6431 || i.index_reg->reg_num == RegRiz)
6432 i.sib.index = NO_INDEX_REGISTER;
6433 else
6434 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6435 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6436 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6437 i.rex |= REX_X;
29b0f896 6438 }
67a4f2b7
AO		 6439
6440 if (i.disp_operands
6441 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6442 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6443 i.rm.mode = 0;
6444 else
a501d77e
L		 6445 {
6446 if (!fake_zero_displacement
6447 && !i.disp_operands
6448 && i.disp_encoding)
6449 {
6450 fake_zero_displacement = 1;
6451 if (i.disp_encoding == disp_encoding_8bit)
6452 i.types[op].bitfield.disp8 = 1;
6453 else
6454 i.types[op].bitfield.disp32 = 1;
6455 }
6456 i.rm.mode = mode_from_disp_size (i.types[op]);
6457 }
29b0f896 6458 }
252b5132 6459
29b0f896
AM		 6460 if (fake_zero_displacement)
6461 {
6462 /* Fakes a zero displacement assuming that i.types[op]
6463 holds the correct displacement size. */
6464 expressionS *exp;
6465
9c2799c2 6466 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6467 exp = &disp_expressions[i.disp_operands++];
6468 i.op[op].disps = exp;
6469 exp->X_op = O_constant;
6470 exp->X_add_number = 0;
6471 exp->X_add_symbol = (symbolS *) 0;
6472 exp->X_op_symbol = (symbolS *) 0;
6473 }
c0f3af97
L		 6474
6475 mem = op;
29b0f896 6476 }
c0f3af97
L		 6477 else
6478 mem = ~0;
252b5132 6479
8c43a48b 6480 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6481 {
6482 if (operand_type_check (i.types[0], imm))
6483 i.vex.register_specifier = NULL;
6484 else
6485 {
6486 /* VEX.vvvv encodes one of the sources when the first
6487 operand is not an immediate. */
1ef99a7b 6488 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6489 i.vex.register_specifier = i.op[0].regs;
6490 else
6491 i.vex.register_specifier = i.op[1].regs;
6492 }
6493
6494 /* Destination is a XMM register encoded in the ModRM.reg
6495 and VEX.R bit. */
6496 i.rm.reg = i.op[2].regs->reg_num;
6497 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6498 i.rex |= REX_R;
6499
6500 /* ModRM.rm and VEX.B encodes the other source. */
6501 if (!i.mem_operands)
6502 {
6503 i.rm.mode = 3;
6504
1ef99a7b 6505 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6506 i.rm.regmem = i.op[1].regs->reg_num;
6507 else
6508 i.rm.regmem = i.op[0].regs->reg_num;
6509
6510 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6511 i.rex |= REX_B;
6512 }
6513 }
2426c15f 6514 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6515 {
6516 i.vex.register_specifier = i.op[2].regs;
6517 if (!i.mem_operands)
6518 {
6519 i.rm.mode = 3;
6520 i.rm.regmem = i.op[1].regs->reg_num;
6521 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6522 i.rex |= REX_B;
6523 }
6524 }
29b0f896
AM		 6525 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6526 (if any) based on i.tm.extension_opcode. Again, we must be
6527 careful to make sure that segment/control/debug/test/MMX
6528 registers are coded into the i.rm.reg field. */
f88c9eb0 6529 else if (i.reg_operands)
29b0f896 6530 {
99018f42 6531 unsigned int op;
7ab9ffdd
L		 6532 unsigned int vex_reg = ~0;
6533
6534 for (op = 0; op < i.operands; op++)
6535 if (i.types[op].bitfield.reg8
6536 || i.types[op].bitfield.reg16
6537 || i.types[op].bitfield.reg32
6538 || i.types[op].bitfield.reg64
6539 || i.types[op].bitfield.regmmx
6540 || i.types[op].bitfield.regxmm
6541 || i.types[op].bitfield.regymm
7e8b059b 6542 || i.types[op].bitfield.regbnd
43234a1e
L		 6543 || i.types[op].bitfield.regzmm
6544 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6545 || i.types[op].bitfield.sreg2
6546 || i.types[op].bitfield.sreg3
6547 || i.types[op].bitfield.control
6548 || i.types[op].bitfield.debug
6549 || i.types[op].bitfield.test)
6550 break;
c0209578 6551
7ab9ffdd
L		 6552 if (vex_3_sources)
6553 op = dest;
2426c15f 6554 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6555 {
6556 /* For instructions with VexNDS, the register-only
6557 source operand is encoded in VEX prefix. */
6558 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6559
7ab9ffdd 6560 if (op > mem)
c0f3af97 6561 {
7ab9ffdd
L		 6562 vex_reg = op++;
6563 gas_assert (op < i.operands);
c0f3af97
L		 6564 }
6565 else
c0f3af97 6566 {
f12dc422
L		 6567 /* Check register-only source operand when two source
6568 operands are swapped. */
6569 if (!i.tm.operand_types[op].bitfield.baseindex
6570 && i.tm.operand_types[op + 1].bitfield.baseindex)
6571 {
6572 vex_reg = op;
6573 op += 2;
6574 gas_assert (mem == (vex_reg + 1)
6575 && op < i.operands);
6576 }
6577 else
6578 {
6579 vex_reg = op + 1;
6580 gas_assert (vex_reg < i.operands);
6581 }
c0f3af97 6582 }
7ab9ffdd 6583 }
2426c15f 6584 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6585 {
f12dc422 6586 /* For instructions with VexNDD, the register destination
7ab9ffdd 6587 is encoded in VEX prefix. */
f12dc422
L		 6588 if (i.mem_operands == 0)
6589 {
6590 /* There is no memory operand. */
6591 gas_assert ((op + 2) == i.operands);
6592 vex_reg = op + 1;
6593 }
6594 else
8d63c93e 6595 {
f12dc422
L		 6596 /* There are only 2 operands. */
6597 gas_assert (op < 2 && i.operands == 2);
6598 vex_reg = 1;
6599 }
7ab9ffdd
L		 6600 }
6601 else
6602 gas_assert (op < i.operands);
99018f42 6603
7ab9ffdd
L		 6604 if (vex_reg != (unsigned int) ~0)
6605 {
f12dc422 6606 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6607
f12dc422
L		 6608 if (type->bitfield.reg32 != 1
6609 && type->bitfield.reg64 != 1
6610 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6611 && !operand_type_equal (type, &regymm)
6612 && !operand_type_equal (type, &regzmm)
6613 && !operand_type_equal (type, &regmask))
7ab9ffdd 6614 abort ();
f88c9eb0 6615
7ab9ffdd
L		 6616 i.vex.register_specifier = i.op[vex_reg].regs;
6617 }
6618
1b9f0c97
L		 6619 /* Don't set OP operand twice. */
6620 if (vex_reg != op)
7ab9ffdd 6621 {
1b9f0c97
L		 6622 /* If there is an extension opcode to put here, the
6623 register number must be put into the regmem field. */
6624 if (i.tm.extension_opcode != None)
6625 {
6626 i.rm.regmem = i.op[op].regs->reg_num;
6627 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6628 i.rex |= REX_B;
43234a1e
L		 6629 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6630 i.vrex |= REX_B;
1b9f0c97
L		 6631 }
6632 else
6633 {
6634 i.rm.reg = i.op[op].regs->reg_num;
6635 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6636 i.rex |= REX_R;
43234a1e
L		 6637 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6638 i.vrex |= REX_R;
1b9f0c97 6639 }
7ab9ffdd 6640 }
252b5132 6641
29b0f896
AM		 6642 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6643 must set it to 3 to indicate this is a register operand
6644 in the regmem field. */
6645 if (!i.mem_operands)
6646 i.rm.mode = 3;
6647 }
252b5132 6648
29b0f896 6649 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6650 if (i.tm.extension_opcode != None)
29b0f896
AM		 6651 i.rm.reg = i.tm.extension_opcode;
6652 }
6653 return default_seg;
6654}
252b5132 6655
29b0f896 6656static void
e3bb37b5 6657output_branch (void)
29b0f896
AM		 6658{
6659 char *p;
f8a5c266 6660 int size;
29b0f896
AM		 6661 int code16;
6662 int prefix;
6663 relax_substateT subtype;
6664 symbolS *sym;
6665 offsetT off;
6666
f8a5c266 6667 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6668 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6669
6670 prefix = 0;
6671 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6672 {
29b0f896
AM		 6673 prefix = 1;
6674 i.prefixes -= 1;
6675 code16 ^= CODE16;
252b5132 6676 }
29b0f896
AM		 6677 /* Pentium4 branch hints. */
6678 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6679 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6680 {
29b0f896
AM		 6681 prefix++;
6682 i.prefixes--;
6683 }
6684 if (i.prefix[REX_PREFIX] != 0)
6685 {
6686 prefix++;
6687 i.prefixes--;
2f66722d
AM		 6688 }
6689
7e8b059b
L		 6690 /* BND prefixed jump. */
6691 if (i.prefix[BND_PREFIX] != 0)
6692 {
6693 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6694 i.prefixes -= 1;
6695 }
6696
29b0f896
AM		 6697 if (i.prefixes != 0 && !intel_syntax)
6698 as_warn (_("skipping prefixes on this instruction"));
6699
6700 /* It's always a symbol; End frag & setup for relax.
6701 Make sure there is enough room in this frag for the largest
6702 instruction we may generate in md_convert_frag. This is 2
6703 bytes for the opcode and room for the prefix and largest
6704 displacement. */
6705 frag_grow (prefix + 2 + 4);
6706 /* Prefix and 1 opcode byte go in fr_fix. */
6707 p = frag_more (prefix + 1);
6708 if (i.prefix[DATA_PREFIX] != 0)
6709 *p++ = DATA_PREFIX_OPCODE;
6710 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6711 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6712 *p++ = i.prefix[SEG_PREFIX];
6713 if (i.prefix[REX_PREFIX] != 0)
6714 *p++ = i.prefix[REX_PREFIX];
6715 *p = i.tm.base_opcode;
6716
6717 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6718 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6719 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6720 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6721 else
f8a5c266 6722 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6723 subtype |= code16;
3e73aa7c 6724
29b0f896
AM		 6725 sym = i.op[0].disps->X_add_symbol;
6726 off = i.op[0].disps->X_add_number;
3e73aa7c 6727
29b0f896
AM		 6728 if (i.op[0].disps->X_op != O_constant
6729 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6730 {
29b0f896
AM		 6731 /* Handle complex expressions. */
6732 sym = make_expr_symbol (i.op[0].disps);
6733 off = 0;
6734 }
3e73aa7c 6735
29b0f896
AM		 6736 /* 1 possible extra opcode + 4 byte displacement go in var part.
6737 Pass reloc in fr_var. */
d258b828 6738 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 6739}
3e73aa7c 6740
29b0f896 6741static void
e3bb37b5 6742output_jump (void)
29b0f896
AM		 6743{
6744 char *p;
6745 int size;
3e02c1cc 6746 fixS *fixP;
29b0f896 6747
40fb9820 6748 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6749 {
6750 /* This is a loop or jecxz type instruction. */
6751 size = 1;
6752 if (i.prefix[ADDR_PREFIX] != 0)
6753 {
6754 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6755 i.prefixes -= 1;
6756 }
6757 /* Pentium4 branch hints. */
6758 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6759 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6760 {
6761 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6762 i.prefixes--;
3e73aa7c
JH		 6763 }
6764 }
29b0f896
AM		 6765 else
6766 {
6767 int code16;
3e73aa7c 6768
29b0f896
AM		 6769 code16 = 0;
6770 if (flag_code == CODE_16BIT)
6771 code16 = CODE16;
3e73aa7c 6772
29b0f896
AM		 6773 if (i.prefix[DATA_PREFIX] != 0)
6774 {
6775 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6776 i.prefixes -= 1;
6777 code16 ^= CODE16;
6778 }
252b5132 6779
29b0f896
AM		 6780 size = 4;
6781 if (code16)
6782 size = 2;
6783 }
9fcc94b6 6784
29b0f896
AM		 6785 if (i.prefix[REX_PREFIX] != 0)
6786 {
6787 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6788 i.prefixes -= 1;
6789 }
252b5132 6790
7e8b059b
L		 6791 /* BND prefixed jump. */
6792 if (i.prefix[BND_PREFIX] != 0)
6793 {
6794 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6795 i.prefixes -= 1;
6796 }
6797
29b0f896
AM		 6798 if (i.prefixes != 0 && !intel_syntax)
6799 as_warn (_("skipping prefixes on this instruction"));
e0890092 6800
42164a71
L		 6801 p = frag_more (i.tm.opcode_length + size);
6802 switch (i.tm.opcode_length)
6803 {
6804 case 2:
6805 *p++ = i.tm.base_opcode >> 8;
6806 case 1:
6807 *p++ = i.tm.base_opcode;
6808 break;
6809 default:
6810 abort ();
6811 }
e0890092 6812
3e02c1cc 6813 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6814 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 6815
6816 /* All jumps handled here are signed, but don't use a signed limit
6817 check for 32 and 16 bit jumps as we want to allow wrap around at
6818 4G and 64k respectively. */
6819 if (size == 1)
6820 fixP->fx_signed = 1;
29b0f896 6821}
e0890092 6822
29b0f896 6823static void
e3bb37b5 6824output_interseg_jump (void)
29b0f896
AM		 6825{
6826 char *p;
6827 int size;
6828 int prefix;
6829 int code16;
252b5132 6830
29b0f896
AM		 6831 code16 = 0;
6832 if (flag_code == CODE_16BIT)
6833 code16 = CODE16;
a217f122 6834
29b0f896
AM		 6835 prefix = 0;
6836 if (i.prefix[DATA_PREFIX] != 0)
6837 {
6838 prefix = 1;
6839 i.prefixes -= 1;
6840 code16 ^= CODE16;
6841 }
6842 if (i.prefix[REX_PREFIX] != 0)
6843 {
6844 prefix++;
6845 i.prefixes -= 1;
6846 }
252b5132 6847
29b0f896
AM		 6848 size = 4;
6849 if (code16)
6850 size = 2;
252b5132 6851
29b0f896
AM		 6852 if (i.prefixes != 0 && !intel_syntax)
6853 as_warn (_("skipping prefixes on this instruction"));
252b5132 6854
29b0f896
AM		 6855 /* 1 opcode; 2 segment; offset */
6856 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6857
29b0f896
AM		 6858 if (i.prefix[DATA_PREFIX] != 0)
6859 *p++ = DATA_PREFIX_OPCODE;
252b5132 6860
29b0f896
AM		 6861 if (i.prefix[REX_PREFIX] != 0)
6862 *p++ = i.prefix[REX_PREFIX];
252b5132 6863
29b0f896
AM		 6864 *p++ = i.tm.base_opcode;
6865 if (i.op[1].imms->X_op == O_constant)
6866 {
6867 offsetT n = i.op[1].imms->X_add_number;
252b5132 6868
29b0f896
AM		 6869 if (size == 2
6870 && !fits_in_unsigned_word (n)
6871 && !fits_in_signed_word (n))
6872 {
6873 as_bad (_("16-bit jump out of range"));
6874 return;
6875 }
6876 md_number_to_chars (p, n, size);
6877 }
6878 else
6879 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6880 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 6881 if (i.op[0].imms->X_op != O_constant)
6882 as_bad (_("can't handle non absolute segment in `%s'"),
6883 i.tm.name);
6884 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6885}
a217f122 6886
29b0f896 6887static void
e3bb37b5 6888output_insn (void)
29b0f896 6889{
2bbd9c25
JJ		 6890 fragS *insn_start_frag;
6891 offsetT insn_start_off;
6892
29b0f896
AM		 6893 /* Tie dwarf2 debug info to the address at the start of the insn.
6894 We can't do this after the insn has been output as the current
6895 frag may have been closed off. eg. by frag_var. */
6896 dwarf2_emit_insn (0);
6897
2bbd9c25
JJ		 6898 insn_start_frag = frag_now;
6899 insn_start_off = frag_now_fix ();
6900
29b0f896 6901 /* Output jumps. */
40fb9820 6902 if (i.tm.opcode_modifier.jump)
29b0f896 6903 output_branch ();
40fb9820
L		 6904 else if (i.tm.opcode_modifier.jumpbyte
6905 || i.tm.opcode_modifier.jumpdword)
29b0f896 6906 output_jump ();
40fb9820 6907 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6908 output_interseg_jump ();
6909 else
6910 {
6911 /* Output normal instructions here. */
6912 char *p;
6913 unsigned char *q;
47465058 6914 unsigned int j;
331d2d0d 6915 unsigned int prefix;
4dffcebc 6916
d022bddd
IT		 6917 /* Some processors fail on LOCK prefix. This options makes
6918 assembler ignore LOCK prefix and serves as a workaround. */
6919 if (omit_lock_prefix)
6920 {
6921 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
6922 return;
6923 i.prefix[LOCK_PREFIX] = 0;
6924 }
6925
43234a1e
L		 6926 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6927 don't need the explicit prefix. */
6928 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6929 {
c0f3af97 6930 switch (i.tm.opcode_length)
bc4bd9ab 6931 {
c0f3af97
L		 6932 case 3:
6933 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6934 {
c0f3af97
L		 6935 prefix = (i.tm.base_opcode >> 24) & 0xff;
6936 goto check_prefix;
6937 }
6938 break;
6939 case 2:
6940 if ((i.tm.base_opcode & 0xff0000) != 0)
6941 {
6942 prefix = (i.tm.base_opcode >> 16) & 0xff;
6943 if (i.tm.cpu_flags.bitfield.cpupadlock)
6944 {
4dffcebc 6945check_prefix:
c0f3af97 6946 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6947 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6948 != REPE_PREFIX_OPCODE))
6949 add_prefix (prefix);
6950 }
6951 else
4dffcebc
L		 6952 add_prefix (prefix);
6953 }
c0f3af97
L		 6954 break;
6955 case 1:
6956 break;
6957 default:
6958 abort ();
bc4bd9ab 6959 }
c0f3af97 6960
6d19a37a 6961#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 6962 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
6963 R_X86_64_GOTTPOFF relocation so that linker can safely
6964 perform IE->LE optimization. */
6965 if (x86_elf_abi == X86_64_X32_ABI
6966 && i.operands == 2
6967 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
6968 && i.prefix[REX_PREFIX] == 0)
6969 add_prefix (REX_OPCODE);
6d19a37a 6970#endif
cf61b747 6971
c0f3af97
L		 6972 /* The prefix bytes. */
6973 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6974 if (*q)
6975 FRAG_APPEND_1_CHAR (*q);
0f10071e 6976 }
ae5c1c7b 6977 else
c0f3af97
L		 6978 {
6979 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6980 if (*q)
6981 switch (j)
6982 {
6983 case REX_PREFIX:
6984 /* REX byte is encoded in VEX prefix. */
6985 break;
6986 case SEG_PREFIX:
6987 case ADDR_PREFIX:
6988 FRAG_APPEND_1_CHAR (*q);
6989 break;
6990 default:
6991 /* There should be no other prefixes for instructions
6992 with VEX prefix. */
6993 abort ();
6994 }
6995
43234a1e
L		 6996 /* For EVEX instructions i.vrex should become 0 after
6997 build_evex_prefix. For VEX instructions upper 16 registers
6998 aren't available, so VREX should be 0. */
6999 if (i.vrex)
7000 abort ();
c0f3af97
L		 7001 /* Now the VEX prefix. */
7002 p = frag_more (i.vex.length);
7003 for (j = 0; j < i.vex.length; j++)
7004 p[j] = i.vex.bytes[j];
7005 }
252b5132 7006
29b0f896 7007 /* Now the opcode; be careful about word order here! */
4dffcebc 7008 if (i.tm.opcode_length == 1)
29b0f896
AM		 7009 {
7010 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7011 }
7012 else
7013 {
4dffcebc 7014 switch (i.tm.opcode_length)
331d2d0d 7015 {
43234a1e
L		 7016 case 4:
7017 p = frag_more (4);
7018 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7019 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7020 break;
4dffcebc 7021 case 3:
331d2d0d
L		 7022 p = frag_more (3);
7023 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7024 break;
7025 case 2:
7026 p = frag_more (2);
7027 break;
7028 default:
7029 abort ();
7030 break;
331d2d0d 7031 }
0f10071e 7032
29b0f896
AM		 7033 /* Put out high byte first: can't use md_number_to_chars! */
7034 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7035 *p = i.tm.base_opcode & 0xff;
7036 }
3e73aa7c 7037
29b0f896 7038 /* Now the modrm byte and sib byte (if present). */
40fb9820 7039 if (i.tm.opcode_modifier.modrm)
29b0f896 7040 {
4a3523fa
L		 7041 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7042 | i.rm.reg << 3
7043 | i.rm.mode << 6));
29b0f896
AM		 7044 /* If i.rm.regmem == ESP (4)
7045 && i.rm.mode != (Register mode)
7046 && not 16 bit
7047 ==> need second modrm byte. */
7048 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7049 && i.rm.mode != 3
40fb9820 7050 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7051 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7052 | i.sib.index << 3
7053 | i.sib.scale << 6));
29b0f896 7054 }
3e73aa7c 7055
29b0f896 7056 if (i.disp_operands)
2bbd9c25 7057 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7058
29b0f896 7059 if (i.imm_operands)
2bbd9c25 7060 output_imm (insn_start_frag, insn_start_off);
29b0f896 7061 }
252b5132 7062
29b0f896
AM		 7063#ifdef DEBUG386
7064 if (flag_debug)
7065 {
7b81dfbb 7066 pi ("" /*line*/, &i);
29b0f896
AM		 7067 }
7068#endif /* DEBUG386 */
7069}
252b5132 7070
e205caa7
L		 7071/* Return the size of the displacement operand N. */
7072
7073static int
7074disp_size (unsigned int n)
7075{
7076 int size = 4;
43234a1e
L		 7077
7078 /* Vec_Disp8 has to be 8bit. */
7079 if (i.types[n].bitfield.vec_disp8)
7080 size = 1;
7081 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7082 size = 8;
7083 else if (i.types[n].bitfield.disp8)
7084 size = 1;
7085 else if (i.types[n].bitfield.disp16)
7086 size = 2;
e205caa7
L		 7087 return size;
7088}
7089
7090/* Return the size of the immediate operand N. */
7091
7092static int
7093imm_size (unsigned int n)
7094{
7095 int size = 4;
40fb9820
L		 7096 if (i.types[n].bitfield.imm64)
7097 size = 8;
7098 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7099 size = 1;
7100 else if (i.types[n].bitfield.imm16)
7101 size = 2;
e205caa7
L		 7102 return size;
7103}
7104
29b0f896 7105static void
64e74474 7106output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7107{
7108 char *p;
7109 unsigned int n;
252b5132 7110
29b0f896
AM		 7111 for (n = 0; n < i.operands; n++)
7112 {
43234a1e
L		 7113 if (i.types[n].bitfield.vec_disp8
7114 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7115 {
7116 if (i.op[n].disps->X_op == O_constant)
7117 {
e205caa7 7118 int size = disp_size (n);
43234a1e 7119 offsetT val = i.op[n].disps->X_add_number;
252b5132 7120
43234a1e
L		 7121 if (i.types[n].bitfield.vec_disp8)
7122 val >>= i.memshift;
7123 val = offset_in_range (val, size);
29b0f896
AM		 7124 p = frag_more (size);
7125 md_number_to_chars (p, val, size);
7126 }
7127 else
7128 {
f86103b7 7129 enum bfd_reloc_code_real reloc_type;
e205caa7 7130 int size = disp_size (n);
40fb9820 7131 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 7132 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7133
e205caa7 7134 /* We can't have 8 bit displacement here. */
9c2799c2 7135 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7136
29b0f896
AM		 7137 /* The PC relative address is computed relative
7138 to the instruction boundary, so in case immediate
7139 fields follows, we need to adjust the value. */
7140 if (pcrel && i.imm_operands)
7141 {
29b0f896 7142 unsigned int n1;
e205caa7 7143 int sz = 0;
252b5132 7144
29b0f896 7145 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7146 if (operand_type_check (i.types[n1], imm))
252b5132 7147 {
e205caa7
L		 7148 /* Only one immediate is allowed for PC
7149 relative address. */
9c2799c2 7150 gas_assert (sz == 0);
e205caa7
L		 7151 sz = imm_size (n1);
7152 i.op[n].disps->X_add_number -= sz;
252b5132 7153 }
29b0f896 7154 /* We should find the immediate. */
9c2799c2 7155 gas_assert (sz != 0);
29b0f896 7156 }
520dc8e8 7157
29b0f896 7158 p = frag_more (size);
d258b828 7159 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7160 if (GOT_symbol
2bbd9c25 7161 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7162 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7163 || reloc_type == BFD_RELOC_X86_64_32S
7164 || (reloc_type == BFD_RELOC_64
7165 && object_64bit))
d6ab8113
JB		 7166 && (i.op[n].disps->X_op == O_symbol
7167 || (i.op[n].disps->X_op == O_add
7168 && ((symbol_get_value_expression
7169 (i.op[n].disps->X_op_symbol)->X_op)
7170 == O_subtract))))
7171 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7172 {
7173 offsetT add;
7174
7175 if (insn_start_frag == frag_now)
7176 add = (p - frag_now->fr_literal) - insn_start_off;
7177 else
7178 {
7179 fragS *fr;
7180
7181 add = insn_start_frag->fr_fix - insn_start_off;
7182 for (fr = insn_start_frag->fr_next;
7183 fr && fr != frag_now; fr = fr->fr_next)
7184 add += fr->fr_fix;
7185 add += p - frag_now->fr_literal;
7186 }
7187
4fa24527 7188 if (!object_64bit)
7b81dfbb
AJ		 7189 {
7190 reloc_type = BFD_RELOC_386_GOTPC;
7191 i.op[n].imms->X_add_number += add;
7192 }
7193 else if (reloc_type == BFD_RELOC_64)
7194 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7195 else
7b81dfbb
AJ		 7196 /* Don't do the adjustment for x86-64, as there
7197 the pcrel addressing is relative to the _next_
7198 insn, and that is taken care of in other code. */
d6ab8113 7199 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7200 }
062cd5e7 7201 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 7202 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 7203 }
7204 }
7205 }
7206}
252b5132 7207
29b0f896 7208static void
64e74474 7209output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7210{
7211 char *p;
7212 unsigned int n;
252b5132 7213
29b0f896
AM		 7214 for (n = 0; n < i.operands; n++)
7215 {
43234a1e
L		 7216 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7217 if (i.rounding && (int) n == i.rounding->operand)
7218 continue;
7219
40fb9820 7220 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7221 {
7222 if (i.op[n].imms->X_op == O_constant)
7223 {
e205caa7 7224 int size = imm_size (n);
29b0f896 7225 offsetT val;
b4cac588 7226
29b0f896
AM		 7227 val = offset_in_range (i.op[n].imms->X_add_number,
7228 size);
7229 p = frag_more (size);
7230 md_number_to_chars (p, val, size);
7231 }
7232 else
7233 {
7234 /* Not absolute_section.
7235 Need a 32-bit fixup (don't support 8bit
7236 non-absolute imms). Try to support other
7237 sizes ... */
f86103b7 7238 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7239 int size = imm_size (n);
7240 int sign;
29b0f896 7241
40fb9820 7242 if (i.types[n].bitfield.imm32s
a7d61044 7243 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7244 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7245 sign = 1;
e205caa7
L		 7246 else
7247 sign = 0;
520dc8e8 7248
29b0f896 7249 p = frag_more (size);
d258b828 7250 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7251
2bbd9c25
JJ		 7252 /* This is tough to explain. We end up with this one if we
7253 * have operands that look like
7254 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7255 * obtain the absolute address of the GOT, and it is strongly
7256 * preferable from a performance point of view to avoid using
7257 * a runtime relocation for this. The actual sequence of
7258 * instructions often look something like:
7259 *
7260 * call .L66
7261 * .L66:
7262 * popl %ebx
7263 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7264 *
7265 * The call and pop essentially return the absolute address
7266 * of the label .L66 and store it in %ebx. The linker itself
7267 * will ultimately change the first operand of the addl so
7268 * that %ebx points to the GOT, but to keep things simple, the
7269 * .o file must have this operand set so that it generates not
7270 * the absolute address of .L66, but the absolute address of
7271 * itself. This allows the linker itself simply treat a GOTPC
7272 * relocation as asking for a pcrel offset to the GOT to be
7273 * added in, and the addend of the relocation is stored in the
7274 * operand field for the instruction itself.
7275 *
7276 * Our job here is to fix the operand so that it would add
7277 * the correct offset so that %ebx would point to itself. The
7278 * thing that is tricky is that .-.L66 will point to the
7279 * beginning of the instruction, so we need to further modify
7280 * the operand so that it will point to itself. There are
7281 * other cases where you have something like:
7282 *
7283 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7284 *
7285 * and here no correction would be required. Internally in
7286 * the assembler we treat operands of this form as not being
7287 * pcrel since the '.' is explicitly mentioned, and I wonder
7288 * whether it would simplify matters to do it this way. Who
7289 * knows. In earlier versions of the PIC patches, the
7290 * pcrel_adjust field was used to store the correction, but
7291 * since the expression is not pcrel, I felt it would be
7292 * confusing to do it this way. */
7293
d6ab8113 7294 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7295 || reloc_type == BFD_RELOC_X86_64_32S
7296 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7297 && GOT_symbol
7298 && GOT_symbol == i.op[n].imms->X_add_symbol
7299 && (i.op[n].imms->X_op == O_symbol
7300 || (i.op[n].imms->X_op == O_add
7301 && ((symbol_get_value_expression
7302 (i.op[n].imms->X_op_symbol)->X_op)
7303 == O_subtract))))
7304 {
2bbd9c25
JJ		 7305 offsetT add;
7306
7307 if (insn_start_frag == frag_now)
7308 add = (p - frag_now->fr_literal) - insn_start_off;
7309 else
7310 {
7311 fragS *fr;
7312
7313 add = insn_start_frag->fr_fix - insn_start_off;
7314 for (fr = insn_start_frag->fr_next;
7315 fr && fr != frag_now; fr = fr->fr_next)
7316 add += fr->fr_fix;
7317 add += p - frag_now->fr_literal;
7318 }
7319
4fa24527 7320 if (!object_64bit)
d6ab8113 7321 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7322 else if (size == 4)
d6ab8113 7323 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7324 else if (size == 8)
7325 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7326 i.op[n].imms->X_add_number += add;
29b0f896 7327 }
29b0f896
AM		 7328 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7329 i.op[n].imms, 0, reloc_type);
7330 }
7331 }
7332 }
252b5132
RH		 7333}
7334\f
d182319b
JB		 7335/* x86_cons_fix_new is called via the expression parsing code when a
7336 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7337static int cons_sign = -1;
7338
7339void
e3bb37b5 7340x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7341 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7342{
d258b828 7343 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7344
7345#ifdef TE_PE
7346 if (exp->X_op == O_secrel)
7347 {
7348 exp->X_op = O_symbol;
7349 r = BFD_RELOC_32_SECREL;
7350 }
7351#endif
7352
7353 fix_new_exp (frag, off, len, exp, 0, r);
7354}
7355
357d1bd8
L		 7356/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7357 purpose of the `.dc.a' internal pseudo-op. */
7358
7359int
7360x86_address_bytes (void)
7361{
7362 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7363 return 4;
7364 return stdoutput->arch_info->bits_per_address / 8;
7365}
7366
d382c579
TG		 7367#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7368 || defined (LEX_AT)
d258b828 7369# define lex_got(reloc, adjust, types) NULL
718ddfc0 7370#else
f3c180ae
AM		 7371/* Parse operands of the form
7372 <symbol>@GOTOFF+<nnn>
7373 and similar .plt or .got references.
7374
7375 If we find one, set up the correct relocation in RELOC and copy the
7376 input string, minus the `@GOTOFF' into a malloc'd buffer for
7377 parsing by the calling routine. Return this buffer, and if ADJUST
7378 is non-null set it to the length of the string we removed from the
7379 input line. Otherwise return NULL. */
7380static char *
91d6fa6a 7381lex_got (enum bfd_reloc_code_real *rel,
64e74474 7382 int *adjust,
d258b828 7383 i386_operand_type *types)
f3c180ae 7384{
7b81dfbb
AJ		 7385 /* Some of the relocations depend on the size of what field is to
7386 be relocated. But in our callers i386_immediate and i386_displacement
7387 we don't yet know the operand size (this will be set by insn
7388 matching). Hence we record the word32 relocation here,
7389 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7390 static const struct {
7391 const char *str;
cff8d58a 7392 int len;
4fa24527 7393 const enum bfd_reloc_code_real rel[2];
40fb9820 7394 const i386_operand_type types64;
f3c180ae 7395 } gotrel[] = {
8ce3d284 7396#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7397 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7398 BFD_RELOC_SIZE32 },
7399 OPERAND_TYPE_IMM32_64 },
8ce3d284 7400#endif
cff8d58a
L		 7401 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7402 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7403 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7404 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7405 BFD_RELOC_X86_64_PLT32 },
40fb9820 7406 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7407 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7408 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7409 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7410 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7411 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7412 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7413 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7414 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7415 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7416 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7417 BFD_RELOC_X86_64_TLSGD },
40fb9820 7418 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7419 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7420 _dummy_first_bfd_reloc_code_real },
40fb9820 7421 OPERAND_TYPE_NONE },
cff8d58a
L		 7422 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7423 BFD_RELOC_X86_64_TLSLD },
40fb9820 7424 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7425 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7426 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7427 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7428 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7429 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7430 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7431 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7432 _dummy_first_bfd_reloc_code_real },
40fb9820 7433 OPERAND_TYPE_NONE },
cff8d58a
L		 7434 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7435 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7436 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7437 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7438 _dummy_first_bfd_reloc_code_real },
40fb9820 7439 OPERAND_TYPE_NONE },
cff8d58a
L		 7440 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7441 _dummy_first_bfd_reloc_code_real },
40fb9820 7442 OPERAND_TYPE_NONE },
cff8d58a
L		 7443 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7444 BFD_RELOC_X86_64_GOT32 },
40fb9820 7445 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7446 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7447 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7448 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7449 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7450 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7451 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7452 };
7453 char *cp;
7454 unsigned int j;
7455
d382c579 7456#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7457 if (!IS_ELF)
7458 return NULL;
d382c579 7459#endif
718ddfc0 7460
f3c180ae 7461 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7462 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7463 return NULL;
7464
47465058 7465 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7466 {
cff8d58a 7467 int len = gotrel[j].len;
28f81592 7468 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7469 {
4fa24527 7470 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7471 {
28f81592
AM		 7472 int first, second;
7473 char *tmpbuf, *past_reloc;
f3c180ae 7474
91d6fa6a 7475 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7476
3956db08
JB		 7477 if (types)
7478 {
7479 if (flag_code != CODE_64BIT)
40fb9820
L		 7480 {
7481 types->bitfield.imm32 = 1;
7482 types->bitfield.disp32 = 1;
7483 }
3956db08
JB		 7484 else
7485 *types = gotrel[j].types64;
7486 }
7487
8fd4256d 7488 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7489 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7490
28f81592 7491 /* The length of the first part of our input line. */
f3c180ae 7492 first = cp - input_line_pointer;
28f81592
AM		 7493
7494 /* The second part goes from after the reloc token until
67c11a9b 7495 (and including) an end_of_line char or comma. */
28f81592 7496 past_reloc = cp + 1 + len;
67c11a9b
AM		 7497 cp = past_reloc;
7498 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7499 ++cp;
7500 second = cp + 1 - past_reloc;
28f81592
AM		 7501
7502 /* Allocate and copy string. The trailing NUL shouldn't
7503 be necessary, but be safe. */
1e9cc1c2 7504 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7505 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7506 if (second != 0 && *past_reloc != ' ')
7507 /* Replace the relocation token with ' ', so that
7508 errors like foo@GOTOFF1 will be detected. */
7509 tmpbuf[first++] = ' ';
af89796a
L		 7510 else
7511 /* Increment length by 1 if the relocation token is
7512 removed. */
7513 len++;
7514 if (adjust)
7515 *adjust = len;
0787a12d
AM		 7516 memcpy (tmpbuf + first, past_reloc, second);
7517 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7518 return tmpbuf;
7519 }
7520
4fa24527
JB		 7521 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7522 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7523 return NULL;
7524 }
7525 }
7526
7527 /* Might be a symbol version string. Don't as_bad here. */
7528 return NULL;
7529}
4e4f7c87 7530#endif
f3c180ae 7531
a988325c
NC		 7532#ifdef TE_PE
7533#ifdef lex_got
7534#undef lex_got
7535#endif
7536/* Parse operands of the form
7537 <symbol>@SECREL32+<nnn>
7538
7539 If we find one, set up the correct relocation in RELOC and copy the
7540 input string, minus the `@SECREL32' into a malloc'd buffer for
7541 parsing by the calling routine. Return this buffer, and if ADJUST
7542 is non-null set it to the length of the string we removed from the
34bca508
L		 7543 input line. Otherwise return NULL.
7544
a988325c
NC		 7545 This function is copied from the ELF version above adjusted for PE targets. */
7546
7547static char *
7548lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7549 int *adjust ATTRIBUTE_UNUSED,
d258b828 7550 i386_operand_type *types)
a988325c
NC		 7551{
7552 static const struct
7553 {
7554 const char *str;
7555 int len;
7556 const enum bfd_reloc_code_real rel[2];
7557 const i386_operand_type types64;
7558 }
7559 gotrel[] =
7560 {
7561 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7562 BFD_RELOC_32_SECREL },
7563 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7564 };
7565
7566 char *cp;
7567 unsigned j;
7568
7569 for (cp = input_line_pointer; *cp != '@'; cp++)
7570 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7571 return NULL;
7572
7573 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7574 {
7575 int len = gotrel[j].len;
7576
7577 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7578 {
7579 if (gotrel[j].rel[object_64bit] != 0)
7580 {
7581 int first, second;
7582 char *tmpbuf, *past_reloc;
7583
7584 *rel = gotrel[j].rel[object_64bit];
7585 if (adjust)
7586 *adjust = len;
7587
7588 if (types)
7589 {
7590 if (flag_code != CODE_64BIT)
7591 {
7592 types->bitfield.imm32 = 1;
7593 types->bitfield.disp32 = 1;
7594 }
7595 else
7596 *types = gotrel[j].types64;
7597 }
7598
7599 /* The length of the first part of our input line. */
7600 first = cp - input_line_pointer;
7601
7602 /* The second part goes from after the reloc token until
7603 (and including) an end_of_line char or comma. */
7604 past_reloc = cp + 1 + len;
7605 cp = past_reloc;
7606 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7607 ++cp;
7608 second = cp + 1 - past_reloc;
7609
7610 /* Allocate and copy string. The trailing NUL shouldn't
7611 be necessary, but be safe. */
7612 tmpbuf = (char *) xmalloc (first + second + 2);
7613 memcpy (tmpbuf, input_line_pointer, first);
7614 if (second != 0 && *past_reloc != ' ')
7615 /* Replace the relocation token with ' ', so that
7616 errors like foo@SECLREL321 will be detected. */
7617 tmpbuf[first++] = ' ';
7618 memcpy (tmpbuf + first, past_reloc, second);
7619 tmpbuf[first + second] = '\0';
7620 return tmpbuf;
7621 }
7622
7623 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7624 gotrel[j].str, 1 << (5 + object_64bit));
7625 return NULL;
7626 }
7627 }
7628
7629 /* Might be a symbol version string. Don't as_bad here. */
7630 return NULL;
7631}
7632
7633#endif /* TE_PE */
7634
62ebcb5c 7635bfd_reloc_code_real_type
e3bb37b5 7636x86_cons (expressionS *exp, int size)
f3c180ae 7637{
62ebcb5c
AM		 7638 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7639
ee86248c
JB		 7640 intel_syntax = -intel_syntax;
7641
3c7b9c2c 7642 exp->X_md = 0;
4fa24527 7643 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7644 {
7645 /* Handle @GOTOFF and the like in an expression. */
7646 char *save;
7647 char *gotfree_input_line;
4a57f2cf 7648 int adjust = 0;
f3c180ae
AM		 7649
7650 save = input_line_pointer;
d258b828 7651 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7652 if (gotfree_input_line)
7653 input_line_pointer = gotfree_input_line;
7654
7655 expression (exp);
7656
7657 if (gotfree_input_line)
7658 {
7659 /* expression () has merrily parsed up to the end of line,
7660 or a comma - in the wrong buffer. Transfer how far
7661 input_line_pointer has moved to the right buffer. */
7662 input_line_pointer = (save
7663 + (input_line_pointer - gotfree_input_line)
7664 + adjust);
7665 free (gotfree_input_line);
3992d3b7
AM		 7666 if (exp->X_op == O_constant
7667 || exp->X_op == O_absent
7668 || exp->X_op == O_illegal
0398aac5 7669 || exp->X_op == O_register
3992d3b7
AM		 7670 || exp->X_op == O_big)
7671 {
7672 char c = *input_line_pointer;
7673 *input_line_pointer = 0;
7674 as_bad (_("missing or invalid expression `%s'"), save);
7675 *input_line_pointer = c;
7676 }
f3c180ae
AM		 7677 }
7678 }
7679 else
7680 expression (exp);
ee86248c
JB		 7681
7682 intel_syntax = -intel_syntax;
7683
7684 if (intel_syntax)
7685 i386_intel_simplify (exp);
62ebcb5c
AM		 7686
7687 return got_reloc;
f3c180ae 7688}
f3c180ae 7689
9f32dd5b
L		 7690static void
7691signed_cons (int size)
6482c264 7692{
d182319b
JB		 7693 if (flag_code == CODE_64BIT)
7694 cons_sign = 1;
7695 cons (size);
7696 cons_sign = -1;
6482c264
NC		 7697}
7698
d182319b 7699#ifdef TE_PE
6482c264 7700static void
7016a5d5 7701pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7702{
7703 expressionS exp;
7704
7705 do
7706 {
7707 expression (&exp);
7708 if (exp.X_op == O_symbol)
7709 exp.X_op = O_secrel;
7710
7711 emit_expr (&exp, 4);
7712 }
7713 while (*input_line_pointer++ == ',');
7714
7715 input_line_pointer--;
7716 demand_empty_rest_of_line ();
7717}
6482c264
NC		 7718#endif
7719
43234a1e
L		 7720/* Handle Vector operations. */
7721
7722static char *
7723check_VecOperations (char *op_string, char *op_end)
7724{
7725 const reg_entry *mask;
7726 const char *saved;
7727 char *end_op;
7728
7729 while (*op_string
7730 && (op_end == NULL || op_string < op_end))
7731 {
7732 saved = op_string;
7733 if (*op_string == '{')
7734 {
7735 op_string++;
7736
7737 /* Check broadcasts. */
7738 if (strncmp (op_string, "1to", 3) == 0)
7739 {
7740 int bcst_type;
7741
7742 if (i.broadcast)
7743 goto duplicated_vec_op;
7744
7745 op_string += 3;
7746 if (*op_string == '8')
7747 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7748 else if (*op_string == '4')
7749 bcst_type = BROADCAST_1TO4;
7750 else if (*op_string == '2')
7751 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7752 else if (*op_string == '1'
7753 && *(op_string+1) == '6')
7754 {
7755 bcst_type = BROADCAST_1TO16;
7756 op_string++;
7757 }
7758 else
7759 {
7760 as_bad (_("Unsupported broadcast: `%s'"), saved);
7761 return NULL;
7762 }
7763 op_string++;
7764
7765 broadcast_op.type = bcst_type;
7766 broadcast_op.operand = this_operand;
7767 i.broadcast = &broadcast_op;
7768 }
7769 /* Check masking operation. */
7770 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7771 {
7772 /* k0 can't be used for write mask. */
7773 if (mask->reg_num == 0)
7774 {
7775 as_bad (_("`%s' can't be used for write mask"),
7776 op_string);
7777 return NULL;
7778 }
7779
7780 if (!i.mask)
7781 {
7782 mask_op.mask = mask;
7783 mask_op.zeroing = 0;
7784 mask_op.operand = this_operand;
7785 i.mask = &mask_op;
7786 }
7787 else
7788 {
7789 if (i.mask->mask)
7790 goto duplicated_vec_op;
7791
7792 i.mask->mask = mask;
7793
7794 /* Only "{z}" is allowed here. No need to check
7795 zeroing mask explicitly. */
7796 if (i.mask->operand != this_operand)
7797 {
7798 as_bad (_("invalid write mask `%s'"), saved);
7799 return NULL;
7800 }
7801 }
7802
7803 op_string = end_op;
7804 }
7805 /* Check zeroing-flag for masking operation. */
7806 else if (*op_string == 'z')
7807 {
7808 if (!i.mask)
7809 {
7810 mask_op.mask = NULL;
7811 mask_op.zeroing = 1;
7812 mask_op.operand = this_operand;
7813 i.mask = &mask_op;
7814 }
7815 else
7816 {
7817 if (i.mask->zeroing)
7818 {
7819 duplicated_vec_op:
7820 as_bad (_("duplicated `%s'"), saved);
7821 return NULL;
7822 }
7823
7824 i.mask->zeroing = 1;
7825
7826 /* Only "{%k}" is allowed here. No need to check mask
7827 register explicitly. */
7828 if (i.mask->operand != this_operand)
7829 {
7830 as_bad (_("invalid zeroing-masking `%s'"),
7831 saved);
7832 return NULL;
7833 }
7834 }
7835
7836 op_string++;
7837 }
7838 else
7839 goto unknown_vec_op;
7840
7841 if (*op_string != '}')
7842 {
7843 as_bad (_("missing `}' in `%s'"), saved);
7844 return NULL;
7845 }
7846 op_string++;
7847 continue;
7848 }
7849 unknown_vec_op:
7850 /* We don't know this one. */
7851 as_bad (_("unknown vector operation: `%s'"), saved);
7852 return NULL;
7853 }
7854
7855 return op_string;
7856}
7857
252b5132 7858static int
70e41ade 7859i386_immediate (char *imm_start)
252b5132
RH		 7860{
7861 char *save_input_line_pointer;
f3c180ae 7862 char *gotfree_input_line;
252b5132 7863 segT exp_seg = 0;
47926f60 7864 expressionS *exp;
40fb9820
L		 7865 i386_operand_type types;
7866
0dfbf9d7 7867 operand_type_set (&types, ~0);
252b5132
RH		 7868
7869 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7870 {
31b2323c
L		 7871 as_bad (_("at most %d immediate operands are allowed"),
7872 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7873 return 0;
7874 }
7875
7876 exp = &im_expressions[i.imm_operands++];
520dc8e8 7877 i.op[this_operand].imms = exp;
252b5132
RH		 7878
7879 if (is_space_char (*imm_start))
7880 ++imm_start;
7881
7882 save_input_line_pointer = input_line_pointer;
7883 input_line_pointer = imm_start;
7884
d258b828 7885 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7886 if (gotfree_input_line)
7887 input_line_pointer = gotfree_input_line;
252b5132
RH		 7888
7889 exp_seg = expression (exp);
7890
83183c0c 7891 SKIP_WHITESPACE ();
43234a1e
L		 7892
7893 /* Handle vector operations. */
7894 if (*input_line_pointer == '{')
7895 {
7896 input_line_pointer = check_VecOperations (input_line_pointer,
7897 NULL);
7898 if (input_line_pointer == NULL)
7899 return 0;
7900 }
7901
252b5132 7902 if (*input_line_pointer)
f3c180ae 7903 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7904
7905 input_line_pointer = save_input_line_pointer;
f3c180ae 7906 if (gotfree_input_line)
ee86248c
JB		 7907 {
7908 free (gotfree_input_line);
7909
7910 if (exp->X_op == O_constant || exp->X_op == O_register)
7911 exp->X_op = O_illegal;
7912 }
7913
7914 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7915}
252b5132 7916
ee86248c
JB		 7917static int
7918i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7919 i386_operand_type types, const char *imm_start)
7920{
7921 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7922 {
313c53d1
L		 7923 if (imm_start)
7924 as_bad (_("missing or invalid immediate expression `%s'"),
7925 imm_start);
3992d3b7 7926 return 0;
252b5132 7927 }
3e73aa7c 7928 else if (exp->X_op == O_constant)
252b5132 7929 {
47926f60 7930 /* Size it properly later. */
40fb9820 7931 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7932 /* If not 64bit, sign extend val. */
7933 if (flag_code != CODE_64BIT
4eed87de
AM		 7934 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7935 exp->X_add_number
7936 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7937 }
4c63da97 7938#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7939 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7940 && exp_seg != absolute_section
47926f60 7941 && exp_seg != text_section
24eab124
AM		 7942 && exp_seg != data_section
7943 && exp_seg != bss_section
7944 && exp_seg != undefined_section
f86103b7 7945 && !bfd_is_com_section (exp_seg))
252b5132 7946 {
d0b47220 7947 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 7948 return 0;
7949 }
7950#endif
a841bdf5 7951 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 7952 {
313c53d1
L		 7953 if (imm_start)
7954 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 7955 return 0;
7956 }
252b5132
RH		 7957 else
7958 {
7959 /* This is an address. The size of the address will be
24eab124 7960 determined later, depending on destination register,
3e73aa7c 7961 suffix, or the default for the section. */
40fb9820
L		 7962 i.types[this_operand].bitfield.imm8 = 1;
7963 i.types[this_operand].bitfield.imm16 = 1;
7964 i.types[this_operand].bitfield.imm32 = 1;
7965 i.types[this_operand].bitfield.imm32s = 1;
7966 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 7967 i.types[this_operand] = operand_type_and (i.types[this_operand],
7968 types);
252b5132
RH		 7969 }
7970
7971 return 1;
7972}
7973
551c1ca1 7974static char *
e3bb37b5 7975i386_scale (char *scale)
252b5132 7976{
551c1ca1
AM		 7977 offsetT val;
7978 char *save = input_line_pointer;
252b5132 7979
551c1ca1
AM		 7980 input_line_pointer = scale;
7981 val = get_absolute_expression ();
7982
7983 switch (val)
252b5132 7984 {
551c1ca1 7985 case 1:
252b5132
RH		 7986 i.log2_scale_factor = 0;
7987 break;
551c1ca1 7988 case 2:
252b5132
RH		 7989 i.log2_scale_factor = 1;
7990 break;
551c1ca1 7991 case 4:
252b5132
RH		 7992 i.log2_scale_factor = 2;
7993 break;
551c1ca1 7994 case 8:
252b5132
RH		 7995 i.log2_scale_factor = 3;
7996 break;
7997 default:
a724f0f4
JB		 7998 {
7999 char sep = *input_line_pointer;
8000
8001 *input_line_pointer = '\0';
8002 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8003 scale);
8004 *input_line_pointer = sep;
8005 input_line_pointer = save;
8006 return NULL;
8007 }
252b5132 8008 }
29b0f896 8009 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8010 {
8011 as_warn (_("scale factor of %d without an index register"),
24eab124 8012 1 << i.log2_scale_factor);
252b5132 8013 i.log2_scale_factor = 0;
252b5132 8014 }
551c1ca1
AM		 8015 scale = input_line_pointer;
8016 input_line_pointer = save;
8017 return scale;
252b5132
RH		 8018}
8019
252b5132 8020static int
e3bb37b5 8021i386_displacement (char *disp_start, char *disp_end)
252b5132 8022{
29b0f896 8023 expressionS *exp;
252b5132
RH		 8024 segT exp_seg = 0;
8025 char *save_input_line_pointer;
f3c180ae 8026 char *gotfree_input_line;
40fb9820
L		 8027 int override;
8028 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8029 int ret;
252b5132 8030
31b2323c
L		 8031 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8032 {
8033 as_bad (_("at most %d displacement operands are allowed"),
8034 MAX_MEMORY_OPERANDS);
8035 return 0;
8036 }
8037
0dfbf9d7 8038 operand_type_set (&bigdisp, 0);
40fb9820
L		 8039 if ((i.types[this_operand].bitfield.jumpabsolute)
8040 || (!current_templates->start->opcode_modifier.jump
8041 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8042 {
40fb9820 8043 bigdisp.bitfield.disp32 = 1;
e05278af 8044 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8045 if (flag_code == CODE_64BIT)
8046 {
8047 if (!override)
8048 {
8049 bigdisp.bitfield.disp32s = 1;
8050 bigdisp.bitfield.disp64 = 1;
8051 }
8052 }
8053 else if ((flag_code == CODE_16BIT) ^ override)
8054 {
8055 bigdisp.bitfield.disp32 = 0;
8056 bigdisp.bitfield.disp16 = 1;
8057 }
e05278af
JB		 8058 }
8059 else
8060 {
8061 /* For PC-relative branches, the width of the displacement
8062 is dependent upon data size, not address size. */
e05278af 8063 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8064 if (flag_code == CODE_64BIT)
8065 {
8066 if (override || i.suffix == WORD_MNEM_SUFFIX)
8067 bigdisp.bitfield.disp16 = 1;
8068 else
8069 {
8070 bigdisp.bitfield.disp32 = 1;
8071 bigdisp.bitfield.disp32s = 1;
8072 }
8073 }
8074 else
e05278af
JB		 8075 {
8076 if (!override)
8077 override = (i.suffix == (flag_code != CODE_16BIT
8078 ? WORD_MNEM_SUFFIX
8079 : LONG_MNEM_SUFFIX));
40fb9820
L		 8080 bigdisp.bitfield.disp32 = 1;
8081 if ((flag_code == CODE_16BIT) ^ override)
8082 {
8083 bigdisp.bitfield.disp32 = 0;
8084 bigdisp.bitfield.disp16 = 1;
8085 }
e05278af 8086 }
e05278af 8087 }
c6fb90c8
L		 8088 i.types[this_operand] = operand_type_or (i.types[this_operand],
8089 bigdisp);
252b5132
RH		 8090
8091 exp = &disp_expressions[i.disp_operands];
520dc8e8 8092 i.op[this_operand].disps = exp;
252b5132
RH		 8093 i.disp_operands++;
8094 save_input_line_pointer = input_line_pointer;
8095 input_line_pointer = disp_start;
8096 END_STRING_AND_SAVE (disp_end);
8097
8098#ifndef GCC_ASM_O_HACK
8099#define GCC_ASM_O_HACK 0
8100#endif
8101#if GCC_ASM_O_HACK
8102 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8103 if (i.types[this_operand].bitfield.baseIndex
24eab124 8104 && displacement_string_end[-1] == '+')
252b5132
RH		 8105 {
8106 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8107 constraint within gcc asm statements.
8108 For instance:
8109
8110 #define _set_tssldt_desc(n,addr,limit,type) \
8111 __asm__ __volatile__ ( \
8112 "movw %w2,%0\n\t" \
8113 "movw %w1,2+%0\n\t" \
8114 "rorl $16,%1\n\t" \
8115 "movb %b1,4+%0\n\t" \
8116 "movb %4,5+%0\n\t" \
8117 "movb $0,6+%0\n\t" \
8118 "movb %h1,7+%0\n\t" \
8119 "rorl $16,%1" \
8120 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8121
8122 This works great except that the output assembler ends
8123 up looking a bit weird if it turns out that there is
8124 no offset. You end up producing code that looks like:
8125
8126 #APP
8127 movw $235,(%eax)
8128 movw %dx,2+(%eax)
8129 rorl $16,%edx
8130 movb %dl,4+(%eax)
8131 movb $137,5+(%eax)
8132 movb $0,6+(%eax)
8133 movb %dh,7+(%eax)
8134 rorl $16,%edx
8135 #NO_APP
8136
47926f60 8137 So here we provide the missing zero. */
24eab124
AM		 8138
8139 *displacement_string_end = '0';
252b5132
RH		 8140 }
8141#endif
d258b828 8142 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8143 if (gotfree_input_line)
8144 input_line_pointer = gotfree_input_line;
252b5132 8145
24eab124 8146 exp_seg = expression (exp);
252b5132 8147
636c26b0
AM		 8148 SKIP_WHITESPACE ();
8149 if (*input_line_pointer)
8150 as_bad (_("junk `%s' after expression"), input_line_pointer);
8151#if GCC_ASM_O_HACK
8152 RESTORE_END_STRING (disp_end + 1);
8153#endif
636c26b0 8154 input_line_pointer = save_input_line_pointer;
636c26b0 8155 if (gotfree_input_line)
ee86248c
JB		 8156 {
8157 free (gotfree_input_line);
8158
8159 if (exp->X_op == O_constant || exp->X_op == O_register)
8160 exp->X_op = O_illegal;
8161 }
8162
8163 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8164
8165 RESTORE_END_STRING (disp_end);
8166
8167 return ret;
8168}
8169
8170static int
8171i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8172 i386_operand_type types, const char *disp_start)
8173{
8174 i386_operand_type bigdisp;
8175 int ret = 1;
636c26b0 8176
24eab124
AM		 8177 /* We do this to make sure that the section symbol is in
8178 the symbol table. We will ultimately change the relocation
47926f60 8179 to be relative to the beginning of the section. */
1ae12ab7 8180 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8181 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8182 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8183 {
636c26b0 8184 if (exp->X_op != O_symbol)
3992d3b7 8185 goto inv_disp;
636c26b0 8186
e5cb08ac 8187 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8188 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8189 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8190 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8191 exp->X_op = O_subtract;
8192 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8193 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8194 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8195 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8196 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8197 else
29b0f896 8198 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8199 }
252b5132 8200
3992d3b7
AM		 8201 else if (exp->X_op == O_absent
8202 || exp->X_op == O_illegal
ee86248c 8203 || exp->X_op == O_big)
2daf4fd8 8204 {
3992d3b7
AM		 8205 inv_disp:
8206 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8207 disp_start);
3992d3b7 8208 ret = 0;
2daf4fd8
AM		 8209 }
8210
0e1147d9
L		 8211 else if (flag_code == CODE_64BIT
8212 && !i.prefix[ADDR_PREFIX]
8213 && exp->X_op == O_constant)
8214 {
8215 /* Since displacement is signed extended to 64bit, don't allow
8216 disp32 and turn off disp32s if they are out of range. */
8217 i.types[this_operand].bitfield.disp32 = 0;
8218 if (!fits_in_signed_long (exp->X_add_number))
8219 {
8220 i.types[this_operand].bitfield.disp32s = 0;
8221 if (i.types[this_operand].bitfield.baseindex)
8222 {
8223 as_bad (_("0x%lx out range of signed 32bit displacement"),
8224 (long) exp->X_add_number);
8225 ret = 0;
8226 }
8227 }
8228 }
8229
4c63da97 8230#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8231 else if (exp->X_op != O_constant
8232 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8233 && exp_seg != absolute_section
8234 && exp_seg != text_section
8235 && exp_seg != data_section
8236 && exp_seg != bss_section
8237 && exp_seg != undefined_section
8238 && !bfd_is_com_section (exp_seg))
24eab124 8239 {
d0b47220 8240 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8241 ret = 0;
24eab124 8242 }
252b5132 8243#endif
3956db08 8244
40fb9820
L		 8245 /* Check if this is a displacement only operand. */
8246 bigdisp = i.types[this_operand];
8247 bigdisp.bitfield.disp8 = 0;
8248 bigdisp.bitfield.disp16 = 0;
8249 bigdisp.bitfield.disp32 = 0;
8250 bigdisp.bitfield.disp32s = 0;
8251 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8252 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8253 i.types[this_operand] = operand_type_and (i.types[this_operand],
8254 types);
3956db08 8255
3992d3b7 8256 return ret;
252b5132
RH		 8257}
8258
eecb386c 8259/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8260 Return 1 on success, 0 on a failure. */
8261
252b5132 8262static int
e3bb37b5 8263i386_index_check (const char *operand_string)
252b5132 8264{
fc0763e6 8265 const char *kind = "base/index";
be05d201
L		 8266 enum flag_code addr_mode;
8267
8268 if (i.prefix[ADDR_PREFIX])
8269 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8270 else
8271 {
8272 addr_mode = flag_code;
8273
24eab124 8274#if INFER_ADDR_PREFIX
be05d201
L		 8275 if (i.mem_operands == 0)
8276 {
8277 /* Infer address prefix from the first memory operand. */
8278 const reg_entry *addr_reg = i.base_reg;
8279
8280 if (addr_reg == NULL)
8281 addr_reg = i.index_reg;
eecb386c 8282
be05d201
L		 8283 if (addr_reg)
8284 {
8285 if (addr_reg->reg_num == RegEip
8286 || addr_reg->reg_num == RegEiz
8287 || addr_reg->reg_type.bitfield.reg32)
8288 addr_mode = CODE_32BIT;
8289 else if (flag_code != CODE_64BIT
8290 && addr_reg->reg_type.bitfield.reg16)
8291 addr_mode = CODE_16BIT;
8292
8293 if (addr_mode != flag_code)
8294 {
8295 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8296 i.prefixes += 1;
8297 /* Change the size of any displacement too. At most one
8298 of Disp16 or Disp32 is set.
8299 FIXME. There doesn't seem to be any real need for
8300 separate Disp16 and Disp32 flags. The same goes for
8301 Imm16 and Imm32. Removing them would probably clean
8302 up the code quite a lot. */
8303 if (flag_code != CODE_64BIT
8304 && (i.types[this_operand].bitfield.disp16
8305 || i.types[this_operand].bitfield.disp32))
8306 i.types[this_operand]
8307 = operand_type_xor (i.types[this_operand], disp16_32);
8308 }
8309 }
8310 }
24eab124 8311#endif
be05d201
L		 8312 }
8313
fc0763e6
JB		 8314 if (current_templates->start->opcode_modifier.isstring
8315 && !current_templates->start->opcode_modifier.immext
8316 && (current_templates->end[-1].opcode_modifier.isstring
8317 || i.mem_operands))
8318 {
8319 /* Memory operands of string insns are special in that they only allow
8320 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8321 const reg_entry *expected_reg;
8322 static const char *di_si[][2] =
8323 {
8324 { "esi", "edi" },
8325 { "si", "di" },
8326 { "rsi", "rdi" }
8327 };
8328 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8329
8330 kind = "string address";
8331
8332 if (current_templates->start->opcode_modifier.w)
8333 {
8334 i386_operand_type type = current_templates->end[-1].operand_types[0];
8335
8336 if (!type.bitfield.baseindex
8337 || ((!i.mem_operands != !intel_syntax)
8338 && current_templates->end[-1].operand_types[1]
8339 .bitfield.baseindex))
8340 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8341 expected_reg = hash_find (reg_hash,
8342 di_si[addr_mode][type.bitfield.esseg]);
8343
fc0763e6
JB		 8344 }
8345 else
be05d201 8346 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8347
be05d201
L		 8348 if (i.base_reg != expected_reg
8349 || i.index_reg
fc0763e6 8350 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8351 {
be05d201
L		 8352 /* The second memory operand must have the same size as
8353 the first one. */
8354 if (i.mem_operands
8355 && i.base_reg
8356 && !((addr_mode == CODE_64BIT
8357 && i.base_reg->reg_type.bitfield.reg64)
8358 || (addr_mode == CODE_32BIT
8359 ? i.base_reg->reg_type.bitfield.reg32
8360 : i.base_reg->reg_type.bitfield.reg16)))
8361 goto bad_address;
8362
fc0763e6
JB		 8363 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8364 operand_string,
8365 intel_syntax ? '[' : '(',
8366 register_prefix,
be05d201 8367 expected_reg->reg_name,
fc0763e6 8368 intel_syntax ? ']' : ')');
be05d201 8369 return 1;
fc0763e6 8370 }
be05d201
L		 8371 else
8372 return 1;
8373
8374bad_address:
8375 as_bad (_("`%s' is not a valid %s expression"),
8376 operand_string, kind);
8377 return 0;
3e73aa7c
JH		 8378 }
8379 else
8380 {
be05d201
L		 8381 if (addr_mode != CODE_16BIT)
8382 {
8383 /* 32-bit/64-bit checks. */
8384 if ((i.base_reg
8385 && (addr_mode == CODE_64BIT
8386 ? !i.base_reg->reg_type.bitfield.reg64
8387 : !i.base_reg->reg_type.bitfield.reg32)
8388 && (i.index_reg
8389 || (i.base_reg->reg_num
8390 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8391 || (i.index_reg
8392 && !i.index_reg->reg_type.bitfield.regxmm
8393 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8394 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8395 && ((addr_mode == CODE_64BIT
8396 ? !(i.index_reg->reg_type.bitfield.reg64
8397 || i.index_reg->reg_num == RegRiz)
8398 : !(i.index_reg->reg_type.bitfield.reg32
8399 || i.index_reg->reg_num == RegEiz))
8400 || !i.index_reg->reg_type.bitfield.baseindex)))
8401 goto bad_address;
8402 }
8403 else
3e73aa7c 8404 {
be05d201 8405 /* 16-bit checks. */
3e73aa7c 8406 if ((i.base_reg
40fb9820
L		 8407 && (!i.base_reg->reg_type.bitfield.reg16
8408 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8409 || (i.index_reg
40fb9820
L		 8410 && (!i.index_reg->reg_type.bitfield.reg16
8411 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8412 || !(i.base_reg
8413 && i.base_reg->reg_num < 6
8414 && i.index_reg->reg_num >= 6
8415 && i.log2_scale_factor == 0))))
be05d201 8416 goto bad_address;
3e73aa7c
JH		 8417 }
8418 }
be05d201 8419 return 1;
24eab124 8420}
252b5132 8421
43234a1e
L		 8422/* Handle vector immediates. */
8423
8424static int
8425RC_SAE_immediate (const char *imm_start)
8426{
8427 unsigned int match_found, j;
8428 const char *pstr = imm_start;
8429 expressionS *exp;
8430
8431 if (*pstr != '{')
8432 return 0;
8433
8434 pstr++;
8435 match_found = 0;
8436 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8437 {
8438 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8439 {
8440 if (!i.rounding)
8441 {
8442 rc_op.type = RC_NamesTable[j].type;
8443 rc_op.operand = this_operand;
8444 i.rounding = &rc_op;
8445 }
8446 else
8447 {
8448 as_bad (_("duplicated `%s'"), imm_start);
8449 return 0;
8450 }
8451 pstr += RC_NamesTable[j].len;
8452 match_found = 1;
8453 break;
8454 }
8455 }
8456 if (!match_found)
8457 return 0;
8458
8459 if (*pstr++ != '}')
8460 {
8461 as_bad (_("Missing '}': '%s'"), imm_start);
8462 return 0;
8463 }
8464 /* RC/SAE immediate string should contain nothing more. */;
8465 if (*pstr != 0)
8466 {
8467 as_bad (_("Junk after '}': '%s'"), imm_start);
8468 return 0;
8469 }
8470
8471 exp = &im_expressions[i.imm_operands++];
8472 i.op[this_operand].imms = exp;
8473
8474 exp->X_op = O_constant;
8475 exp->X_add_number = 0;
8476 exp->X_add_symbol = (symbolS *) 0;
8477 exp->X_op_symbol = (symbolS *) 0;
8478
8479 i.types[this_operand].bitfield.imm8 = 1;
8480 return 1;
8481}
8482
fc0763e6 8483/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8484 on error. */
252b5132 8485
252b5132 8486static int
a7619375 8487i386_att_operand (char *operand_string)
252b5132 8488{
af6bdddf
AM		 8489 const reg_entry *r;
8490 char *end_op;
24eab124 8491 char *op_string = operand_string;
252b5132 8492
24eab124 8493 if (is_space_char (*op_string))
252b5132
RH		 8494 ++op_string;
8495
24eab124 8496 /* We check for an absolute prefix (differentiating,
47926f60 8497 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8498 if (*op_string == ABSOLUTE_PREFIX)
8499 {
8500 ++op_string;
8501 if (is_space_char (*op_string))
8502 ++op_string;
40fb9820 8503 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8504 }
252b5132 8505
47926f60 8506 /* Check if operand is a register. */
4d1bb795 8507 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8508 {
40fb9820
L		 8509 i386_operand_type temp;
8510
24eab124
AM		 8511 /* Check for a segment override by searching for ':' after a
8512 segment register. */
8513 op_string = end_op;
8514 if (is_space_char (*op_string))
8515 ++op_string;
40fb9820
L		 8516 if (*op_string == ':'
8517 && (r->reg_type.bitfield.sreg2
8518 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8519 {
8520 switch (r->reg_num)
8521 {
8522 case 0:
8523 i.seg[i.mem_operands] = &es;
8524 break;
8525 case 1:
8526 i.seg[i.mem_operands] = &cs;
8527 break;
8528 case 2:
8529 i.seg[i.mem_operands] = &ss;
8530 break;
8531 case 3:
8532 i.seg[i.mem_operands] = &ds;
8533 break;
8534 case 4:
8535 i.seg[i.mem_operands] = &fs;
8536 break;
8537 case 5:
8538 i.seg[i.mem_operands] = &gs;
8539 break;
8540 }
252b5132 8541
24eab124 8542 /* Skip the ':' and whitespace. */
252b5132
RH		 8543 ++op_string;
8544 if (is_space_char (*op_string))
24eab124 8545 ++op_string;
252b5132 8546
24eab124
AM		 8547 if (!is_digit_char (*op_string)
8548 && !is_identifier_char (*op_string)
8549 && *op_string != '('
8550 && *op_string != ABSOLUTE_PREFIX)
8551 {
8552 as_bad (_("bad memory operand `%s'"), op_string);
8553 return 0;
8554 }
47926f60 8555 /* Handle case of %es:*foo. */
24eab124
AM		 8556 if (*op_string == ABSOLUTE_PREFIX)
8557 {
8558 ++op_string;
8559 if (is_space_char (*op_string))
8560 ++op_string;
40fb9820 8561 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8562 }
8563 goto do_memory_reference;
8564 }
43234a1e
L		 8565
8566 /* Handle vector operations. */
8567 if (*op_string == '{')
8568 {
8569 op_string = check_VecOperations (op_string, NULL);
8570 if (op_string == NULL)
8571 return 0;
8572 }
8573
24eab124
AM		 8574 if (*op_string)
8575 {
d0b47220 8576 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8577 return 0;
8578 }
40fb9820
L		 8579 temp = r->reg_type;
8580 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8581 i.types[this_operand] = operand_type_or (i.types[this_operand],
8582 temp);
7d5e4556 8583 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8584 i.op[this_operand].regs = r;
24eab124
AM		 8585 i.reg_operands++;
8586 }
af6bdddf
AM		 8587 else if (*op_string == REGISTER_PREFIX)
8588 {
8589 as_bad (_("bad register name `%s'"), op_string);
8590 return 0;
8591 }
24eab124 8592 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8593 {
24eab124 8594 ++op_string;
40fb9820 8595 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8596 {
d0b47220 8597 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8598 return 0;
8599 }
8600 if (!i386_immediate (op_string))
8601 return 0;
8602 }
43234a1e
L		 8603 else if (RC_SAE_immediate (operand_string))
8604 {
8605 /* If it is a RC or SAE immediate, do nothing. */
8606 ;
8607 }
24eab124
AM		 8608 else if (is_digit_char (*op_string)
8609 || is_identifier_char (*op_string)
e5cb08ac 8610 || *op_string == '(')
24eab124 8611 {
47926f60 8612 /* This is a memory reference of some sort. */
af6bdddf 8613 char *base_string;
252b5132 8614
47926f60 8615 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8616 char *displacement_string_start;
8617 char *displacement_string_end;
43234a1e 8618 char *vop_start;
252b5132 8619
24eab124 8620 do_memory_reference:
24eab124 8621 if ((i.mem_operands == 1
40fb9820 8622 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8623 || i.mem_operands == 2)
8624 {
8625 as_bad (_("too many memory references for `%s'"),
8626 current_templates->start->name);
8627 return 0;
8628 }
252b5132 8629
24eab124
AM		 8630 /* Check for base index form. We detect the base index form by
8631 looking for an ')' at the end of the operand, searching
8632 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8633 after the '('. */
af6bdddf 8634 base_string = op_string + strlen (op_string);
c3332e24 8635
43234a1e
L		 8636 /* Handle vector operations. */
8637 vop_start = strchr (op_string, '{');
8638 if (vop_start && vop_start < base_string)
8639 {
8640 if (check_VecOperations (vop_start, base_string) == NULL)
8641 return 0;
8642 base_string = vop_start;
8643 }
8644
af6bdddf
AM		 8645 --base_string;
8646 if (is_space_char (*base_string))
8647 --base_string;
252b5132 8648
47926f60 8649 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8650 displacement_string_start = op_string;
8651 displacement_string_end = base_string + 1;
252b5132 8652
24eab124
AM		 8653 if (*base_string == ')')
8654 {
af6bdddf 8655 char *temp_string;
24eab124
AM		 8656 unsigned int parens_balanced = 1;
8657 /* We've already checked that the number of left & right ()'s are
47926f60 8658 equal, so this loop will not be infinite. */
24eab124
AM		 8659 do
8660 {
8661 base_string--;
8662 if (*base_string == ')')
8663 parens_balanced++;
8664 if (*base_string == '(')
8665 parens_balanced--;
8666 }
8667 while (parens_balanced);
c3332e24 8668
af6bdddf 8669 temp_string = base_string;
c3332e24 8670
24eab124 8671 /* Skip past '(' and whitespace. */
252b5132
RH		 8672 ++base_string;
8673 if (is_space_char (*base_string))
24eab124 8674 ++base_string;
252b5132 8675
af6bdddf 8676 if (*base_string == ','
4eed87de
AM		 8677 || ((i.base_reg = parse_register (base_string, &end_op))
8678 != NULL))
252b5132 8679 {
af6bdddf 8680 displacement_string_end = temp_string;
252b5132 8681
40fb9820 8682 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8683
af6bdddf 8684 if (i.base_reg)
24eab124 8685 {
24eab124
AM		 8686 base_string = end_op;
8687 if (is_space_char (*base_string))
8688 ++base_string;
af6bdddf
AM		 8689 }
8690
8691 /* There may be an index reg or scale factor here. */
8692 if (*base_string == ',')
8693 {
8694 ++base_string;
8695 if (is_space_char (*base_string))
8696 ++base_string;
8697
4eed87de
AM		 8698 if ((i.index_reg = parse_register (base_string, &end_op))
8699 != NULL)
24eab124 8700 {
af6bdddf 8701 base_string = end_op;
24eab124
AM		 8702 if (is_space_char (*base_string))
8703 ++base_string;
af6bdddf
AM		 8704 if (*base_string == ',')
8705 {
8706 ++base_string;
8707 if (is_space_char (*base_string))
8708 ++base_string;
8709 }
e5cb08ac 8710 else if (*base_string != ')')
af6bdddf 8711 {
4eed87de
AM		 8712 as_bad (_("expecting `,' or `)' "
8713 "after index register in `%s'"),
af6bdddf
AM		 8714 operand_string);
8715 return 0;
8716 }
24eab124 8717 }
af6bdddf 8718 else if (*base_string == REGISTER_PREFIX)
24eab124 8719 {
f76bf5e0
L		 8720 end_op = strchr (base_string, ',');
8721 if (end_op)
8722 *end_op = '\0';
af6bdddf 8723 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8724 return 0;
8725 }
252b5132 8726
47926f60 8727 /* Check for scale factor. */
551c1ca1 8728 if (*base_string != ')')
af6bdddf 8729 {
551c1ca1
AM		 8730 char *end_scale = i386_scale (base_string);
8731
8732 if (!end_scale)
af6bdddf 8733 return 0;
24eab124 8734
551c1ca1 8735 base_string = end_scale;
af6bdddf
AM		 8736 if (is_space_char (*base_string))
8737 ++base_string;
8738 if (*base_string != ')')
8739 {
4eed87de
AM		 8740 as_bad (_("expecting `)' "
8741 "after scale factor in `%s'"),
af6bdddf
AM		 8742 operand_string);
8743 return 0;
8744 }
8745 }
8746 else if (!i.index_reg)
24eab124 8747 {
4eed87de
AM		 8748 as_bad (_("expecting index register or scale factor "
8749 "after `,'; got '%c'"),
af6bdddf 8750 *base_string);
24eab124
AM		 8751 return 0;
8752 }
8753 }
af6bdddf 8754 else if (*base_string != ')')
24eab124 8755 {
4eed87de
AM		 8756 as_bad (_("expecting `,' or `)' "
8757 "after base register in `%s'"),
af6bdddf 8758 operand_string);
24eab124
AM		 8759 return 0;
8760 }
c3332e24 8761 }
af6bdddf 8762 else if (*base_string == REGISTER_PREFIX)
c3332e24 8763 {
f76bf5e0
L		 8764 end_op = strchr (base_string, ',');
8765 if (end_op)
8766 *end_op = '\0';
af6bdddf 8767 as_bad (_("bad register name `%s'"), base_string);
24eab124 8768 return 0;
c3332e24 8769 }
24eab124
AM		 8770 }
8771
8772 /* If there's an expression beginning the operand, parse it,
8773 assuming displacement_string_start and
8774 displacement_string_end are meaningful. */
8775 if (displacement_string_start != displacement_string_end)
8776 {
8777 if (!i386_displacement (displacement_string_start,
8778 displacement_string_end))
8779 return 0;
8780 }
8781
8782 /* Special case for (%dx) while doing input/output op. */
8783 if (i.base_reg
0dfbf9d7
L		 8784 && operand_type_equal (&i.base_reg->reg_type,
8785 &reg16_inoutportreg)
24eab124
AM		 8786 && i.index_reg == 0
8787 && i.log2_scale_factor == 0
8788 && i.seg[i.mem_operands] == 0
40fb9820 8789 && !operand_type_check (i.types[this_operand], disp))
24eab124 8790 {
65da13b5 8791 i.types[this_operand] = inoutportreg;
24eab124
AM		 8792 return 1;
8793 }
8794
eecb386c
AM		 8795 if (i386_index_check (operand_string) == 0)
8796 return 0;
5c07affc 8797 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8798 i.mem_operands++;
8799 }
8800 else
ce8a8b2f
AM		 8801 {
8802 /* It's not a memory operand; argh! */
24eab124
AM		 8803 as_bad (_("invalid char %s beginning operand %d `%s'"),
8804 output_invalid (*op_string),
8805 this_operand + 1,
8806 op_string);
8807 return 0;
8808 }
47926f60 8809 return 1; /* Normal return. */
252b5132
RH		 8810}
8811\f
fa94de6b
RM		 8812/* Calculate the maximum variable size (i.e., excluding fr_fix)
8813 that an rs_machine_dependent frag may reach. */
8814
8815unsigned int
8816i386_frag_max_var (fragS *frag)
8817{
8818 /* The only relaxable frags are for jumps.
8819 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8820 gas_assert (frag->fr_type == rs_machine_dependent);
8821 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8822}
8823
b084df0b
L		 8824#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8825static int
8826elf_symbol_resolved_in_segment_p (symbolS *fr_symbol)
8827{
8828 /* STT_GNU_IFUNC symbol must go through PLT. */
8829 if ((symbol_get_bfdsym (fr_symbol)->flags
8830 & BSF_GNU_INDIRECT_FUNCTION) != 0)
8831 return 0;
8832
8833 if (!S_IS_EXTERNAL (fr_symbol))
8834 /* Symbol may be weak or local. */
8835 return !S_IS_WEAK (fr_symbol);
8836
573cc2e5
L		 8837 /* Non-weak symbols won't be preempted. */
8838 if (no_shared)
8839 return 1;
8840
b084df0b
L		 8841 /* Global symbols with default visibility in a shared library may be
8842 preempted by another definition. */
8843 return ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT;
8844}
8845#endif
8846
ee7fcc42
AM		 8847/* md_estimate_size_before_relax()
8848
8849 Called just before relax() for rs_machine_dependent frags. The x86
8850 assembler uses these frags to handle variable size jump
8851 instructions.
8852
8853 Any symbol that is now undefined will not become defined.
8854 Return the correct fr_subtype in the frag.
8855 Return the initial "guess for variable size of frag" to caller.
8856 The guess is actually the growth beyond the fixed part. Whatever
8857 we do to grow the fixed or variable part contributes to our
8858 returned value. */
8859
252b5132 8860int
7016a5d5 8861md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8862{
252b5132 8863 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8864 check for un-relaxable symbols. On an ELF system, we can't relax
8865 an externally visible symbol, because it may be overridden by a
8866 shared library. */
8867 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8868#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8869 || (IS_ELF
b084df0b 8870 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol))
fbeb56a4
DK		 8871#endif
8872#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8873 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8874 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8875#endif
8876 )
252b5132 8877 {
b98ef147
AM		 8878 /* Symbol is undefined in this segment, or we need to keep a
8879 reloc so that weak symbols can be overridden. */
8880 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8881 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8882 unsigned char *opcode;
8883 int old_fr_fix;
f6af82bd 8884
ee7fcc42 8885 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8886 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8887 else if (size == 2)
f6af82bd
AM		 8888 reloc_type = BFD_RELOC_16_PCREL;
8889 else
8890 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8891
ee7fcc42
AM		 8892 old_fr_fix = fragP->fr_fix;
8893 opcode = (unsigned char *) fragP->fr_opcode;
8894
fddf5b5b 8895 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8896 {
fddf5b5b
AM		 8897 case UNCOND_JUMP:
8898 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8899 opcode[0] = 0xe9;
252b5132 8900 fragP->fr_fix += size;
062cd5e7
AS		 8901 fix_new (fragP, old_fr_fix, size,
8902 fragP->fr_symbol,
8903 fragP->fr_offset, 1,
8904 reloc_type);
252b5132
RH		 8905 break;
8906
fddf5b5b 8907 case COND_JUMP86:
412167cb
AM		 8908 if (size == 2
8909 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8910 {
8911 /* Negate the condition, and branch past an
8912 unconditional jump. */
8913 opcode[0] ^= 1;
8914 opcode[1] = 3;
8915 /* Insert an unconditional jump. */
8916 opcode[2] = 0xe9;
8917 /* We added two extra opcode bytes, and have a two byte
8918 offset. */
8919 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8920 fix_new (fragP, old_fr_fix + 2, 2,
8921 fragP->fr_symbol,
8922 fragP->fr_offset, 1,
8923 reloc_type);
fddf5b5b
AM		 8924 break;
8925 }
8926 /* Fall through. */
8927
8928 case COND_JUMP:
412167cb
AM		 8929 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8930 {
3e02c1cc
AM		 8931 fixS *fixP;
8932
412167cb 8933 fragP->fr_fix += 1;
3e02c1cc
AM		 8934 fixP = fix_new (fragP, old_fr_fix, 1,
8935 fragP->fr_symbol,
8936 fragP->fr_offset, 1,
8937 BFD_RELOC_8_PCREL);
8938 fixP->fx_signed = 1;
412167cb
AM		 8939 break;
8940 }
93c2a809 8941
24eab124 8942 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8943 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8944 opcode[1] = opcode[0] + 0x10;
f6af82bd 8945 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8946 /* We've added an opcode byte. */
8947 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8948 fix_new (fragP, old_fr_fix + 1, size,
8949 fragP->fr_symbol,
8950 fragP->fr_offset, 1,
8951 reloc_type);
252b5132 8952 break;
fddf5b5b
AM		 8953
8954 default:
8955 BAD_CASE (fragP->fr_subtype);
8956 break;
252b5132
RH		 8957 }
8958 frag_wane (fragP);
ee7fcc42 8959 return fragP->fr_fix - old_fr_fix;
252b5132 8960 }
93c2a809 8961
93c2a809
AM		 8962 /* Guess size depending on current relax state. Initially the relax
8963 state will correspond to a short jump and we return 1, because
8964 the variable part of the frag (the branch offset) is one byte
8965 long. However, we can relax a section more than once and in that
8966 case we must either set fr_subtype back to the unrelaxed state,
8967 or return the value for the appropriate branch. */
8968 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 8969}
8970
47926f60
KH		 8971/* Called after relax() is finished.
8972
8973 In: Address of frag.
8974 fr_type == rs_machine_dependent.
8975 fr_subtype is what the address relaxed to.
8976
8977 Out: Any fixSs and constants are set up.
8978 Caller will turn frag into a ".space 0". */
8979
252b5132 8980void
7016a5d5
TG		 8981md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
8982 fragS *fragP)
252b5132 8983{
29b0f896 8984 unsigned char *opcode;
252b5132 8985 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 8986 offsetT target_address;
8987 offsetT opcode_address;
252b5132 8988 unsigned int extension = 0;
847f7ad4 8989 offsetT displacement_from_opcode_start;
252b5132
RH		 8990
8991 opcode = (unsigned char *) fragP->fr_opcode;
8992
47926f60 8993 /* Address we want to reach in file space. */
252b5132 8994 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 8995
47926f60 8996 /* Address opcode resides at in file space. */
252b5132
RH		 8997 opcode_address = fragP->fr_address + fragP->fr_fix;
8998
47926f60 8999 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9000 displacement_from_opcode_start = target_address - opcode_address;
9001
fddf5b5b 9002 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9003 {
47926f60
KH		 9004 /* Don't have to change opcode. */
9005 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9006 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9007 }
9008 else
9009 {
9010 if (no_cond_jump_promotion
9011 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9012 as_warn_where (fragP->fr_file, fragP->fr_line,
9013 _("long jump required"));
252b5132 9014
fddf5b5b
AM		 9015 switch (fragP->fr_subtype)
9016 {
9017 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9018 extension = 4; /* 1 opcode + 4 displacement */
9019 opcode[0] = 0xe9;
9020 where_to_put_displacement = &opcode[1];
9021 break;
252b5132 9022
fddf5b5b
AM		 9023 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9024 extension = 2; /* 1 opcode + 2 displacement */
9025 opcode[0] = 0xe9;
9026 where_to_put_displacement = &opcode[1];
9027 break;
252b5132 9028
fddf5b5b
AM		 9029 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9030 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9031 extension = 5; /* 2 opcode + 4 displacement */
9032 opcode[1] = opcode[0] + 0x10;
9033 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9034 where_to_put_displacement = &opcode[2];
9035 break;
252b5132 9036
fddf5b5b
AM		 9037 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9038 extension = 3; /* 2 opcode + 2 displacement */
9039 opcode[1] = opcode[0] + 0x10;
9040 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9041 where_to_put_displacement = &opcode[2];
9042 break;
252b5132 9043
fddf5b5b
AM		 9044 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9045 extension = 4;
9046 opcode[0] ^= 1;
9047 opcode[1] = 3;
9048 opcode[2] = 0xe9;
9049 where_to_put_displacement = &opcode[3];
9050 break;
9051
9052 default:
9053 BAD_CASE (fragP->fr_subtype);
9054 break;
9055 }
252b5132 9056 }
fddf5b5b 9057
7b81dfbb
AJ		 9058 /* If size if less then four we are sure that the operand fits,
9059 but if it's 4, then it could be that the displacement is larger
9060 then -/+ 2GB. */
9061 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9062 && object_64bit
9063 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9064 + ((addressT) 1 << 31))
9065 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9066 {
9067 as_bad_where (fragP->fr_file, fragP->fr_line,
9068 _("jump target out of range"));
9069 /* Make us emit 0. */
9070 displacement_from_opcode_start = extension;
9071 }
47926f60 9072 /* Now put displacement after opcode. */
252b5132
RH		 9073 md_number_to_chars ((char *) where_to_put_displacement,
9074 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9075 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9076 fragP->fr_fix += extension;
9077}
9078\f
7016a5d5 9079/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9080 by our caller that we have all the info we need to fix it up.
9081
7016a5d5
TG		 9082 Parameter valP is the pointer to the value of the bits.
9083
252b5132
RH		 9084 On the 386, immediates, displacements, and data pointers are all in
9085 the same (little-endian) format, so we don't need to care about which
9086 we are handling. */
9087
94f592af 9088void
7016a5d5 9089md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9090{
94f592af 9091 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9092 valueT value = *valP;
252b5132 9093
f86103b7 9094#if !defined (TE_Mach)
93382f6d
AM		 9095 if (fixP->fx_pcrel)
9096 {
9097 switch (fixP->fx_r_type)
9098 {
5865bb77
ILT		 9099 default:
9100 break;
9101
d6ab8113
JB		 9102 case BFD_RELOC_64:
9103 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9104 break;
93382f6d 9105 case BFD_RELOC_32:
ae8887b5 9106 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9107 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9108 break;
9109 case BFD_RELOC_16:
9110 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9111 break;
9112 case BFD_RELOC_8:
9113 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9114 break;
9115 }
9116 }
252b5132 9117
a161fe53 9118 if (fixP->fx_addsy != NULL
31312f95 9119 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9120 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9121 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9122 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9123 && !use_rela_relocations)
252b5132 9124 {
31312f95
AM		 9125 /* This is a hack. There should be a better way to handle this.
9126 This covers for the fact that bfd_install_relocation will
9127 subtract the current location (for partial_inplace, PC relative
9128 relocations); see more below. */
252b5132 9129#ifndef OBJ_AOUT
718ddfc0 9130 if (IS_ELF
252b5132
RH		 9131#ifdef TE_PE
9132 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9133#endif
9134 )
9135 value += fixP->fx_where + fixP->fx_frag->fr_address;
9136#endif
9137#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9138 if (IS_ELF)
252b5132 9139 {
6539b54b 9140 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9141
6539b54b 9142 if ((sym_seg == seg
2f66722d 9143 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9144 && sym_seg != absolute_section))
af65af87 9145 && !generic_force_reloc (fixP))
2f66722d
AM		 9146 {
9147 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9148 bfd_install_relocation subtracts them out again. I think
9149 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9150 it. FIXME. */
9151 value += fixP->fx_where + fixP->fx_frag->fr_address;
9152 }
252b5132
RH		 9153 }
9154#endif
9155#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9156 /* For some reason, the PE format does not store a
9157 section address offset for a PC relative symbol. */
9158 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9159 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9160 value += md_pcrel_from (fixP);
9161#endif
9162 }
fbeb56a4 9163#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9164 if (fixP->fx_addsy != NULL
9165 && S_IS_WEAK (fixP->fx_addsy)
9166 /* PR 16858: Do not modify weak function references. */
9167 && ! fixP->fx_pcrel)
fbeb56a4 9168 {
296a8689
NC		 9169#if !defined (TE_PEP)
9170 /* For x86 PE weak function symbols are neither PC-relative
9171 nor do they set S_IS_FUNCTION. So the only reliable way
9172 to detect them is to check the flags of their containing
9173 section. */
9174 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9175 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9176 ;
9177 else
9178#endif
fbeb56a4
DK		 9179 value -= S_GET_VALUE (fixP->fx_addsy);
9180 }
9181#endif
252b5132
RH		 9182
9183 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9184 and we must not disappoint it. */
252b5132 9185#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9186 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9187 switch (fixP->fx_r_type)
9188 {
9189 case BFD_RELOC_386_PLT32:
3e73aa7c 9190 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9191 /* Make the jump instruction point to the address of the operand. At
9192 runtime we merely add the offset to the actual PLT entry. */
9193 value = -4;
9194 break;
31312f95 9195
13ae64f3
JJ		 9196 case BFD_RELOC_386_TLS_GD:
9197 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9198 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9199 case BFD_RELOC_386_TLS_IE:
9200 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9201 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9202 case BFD_RELOC_X86_64_TLSGD:
9203 case BFD_RELOC_X86_64_TLSLD:
9204 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9205 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9206 value = 0; /* Fully resolved at runtime. No addend. */
9207 /* Fallthrough */
9208 case BFD_RELOC_386_TLS_LE:
9209 case BFD_RELOC_386_TLS_LDO_32:
9210 case BFD_RELOC_386_TLS_LE_32:
9211 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9212 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9213 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9214 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9215 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9216 break;
9217
67a4f2b7
AO		 9218 case BFD_RELOC_386_TLS_DESC_CALL:
9219 case BFD_RELOC_X86_64_TLSDESC_CALL:
9220 value = 0; /* Fully resolved at runtime. No addend. */
9221 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9222 fixP->fx_done = 0;
9223 return;
9224
00f7efb6
JJ		 9225 case BFD_RELOC_386_GOT32:
9226 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9227 value = 0; /* Fully resolved at runtime. No addend. */
9228 break;
47926f60
KH		 9229
9230 case BFD_RELOC_VTABLE_INHERIT:
9231 case BFD_RELOC_VTABLE_ENTRY:
9232 fixP->fx_done = 0;
94f592af 9233 return;
47926f60
KH		 9234
9235 default:
9236 break;
9237 }
9238#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9239 *valP = value;
f86103b7 9240#endif /* !defined (TE_Mach) */
3e73aa7c 9241
3e73aa7c 9242 /* Are we finished with this relocation now? */
c6682705 9243 if (fixP->fx_addsy == NULL)
3e73aa7c 9244 fixP->fx_done = 1;
fbeb56a4
DK		 9245#if defined (OBJ_COFF) && defined (TE_PE)
9246 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9247 {
9248 fixP->fx_done = 0;
9249 /* Remember value for tc_gen_reloc. */
9250 fixP->fx_addnumber = value;
9251 /* Clear out the frag for now. */
9252 value = 0;
9253 }
9254#endif
3e73aa7c
JH		 9255 else if (use_rela_relocations)
9256 {
9257 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9258 /* Remember value for tc_gen_reloc. */
9259 fixP->fx_addnumber = value;
3e73aa7c
JH		 9260 value = 0;
9261 }
f86103b7 9262
94f592af 9263 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9264}
252b5132 9265\f
252b5132 9266char *
499ac353 9267md_atof (int type, char *litP, int *sizeP)
252b5132 9268{
499ac353
NC		 9269 /* This outputs the LITTLENUMs in REVERSE order;
9270 in accord with the bigendian 386. */
9271 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9272}
9273\f
2d545b82 9274static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9275
252b5132 9276static char *
e3bb37b5 9277output_invalid (int c)
252b5132 9278{
3882b010 9279 if (ISPRINT (c))
f9f21a03
L		 9280 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9281 "'%c'", c);
252b5132 9282 else
f9f21a03 9283 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9284 "(0x%x)", (unsigned char) c);
252b5132
RH		 9285 return output_invalid_buf;
9286}
9287
af6bdddf 9288/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9289
9290static const reg_entry *
4d1bb795 9291parse_real_register (char *reg_string, char **end_op)
252b5132 9292{
af6bdddf
AM		 9293 char *s = reg_string;
9294 char *p;
252b5132
RH		 9295 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9296 const reg_entry *r;
9297
9298 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9299 if (*s == REGISTER_PREFIX)
9300 ++s;
9301
9302 if (is_space_char (*s))
9303 ++s;
9304
9305 p = reg_name_given;
af6bdddf 9306 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9307 {
9308 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9309 return (const reg_entry *) NULL;
9310 s++;
252b5132
RH		 9311 }
9312
6588847e
DN		 9313 /* For naked regs, make sure that we are not dealing with an identifier.
9314 This prevents confusing an identifier like `eax_var' with register
9315 `eax'. */
9316 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9317 return (const reg_entry *) NULL;
9318
af6bdddf 9319 *end_op = s;
252b5132
RH		 9320
9321 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9322
5f47d35b 9323 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9324 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9325 {
5f47d35b
AM		 9326 if (is_space_char (*s))
9327 ++s;
9328 if (*s == '(')
9329 {
af6bdddf 9330 ++s;
5f47d35b
AM		 9331 if (is_space_char (*s))
9332 ++s;
9333 if (*s >= '0' && *s <= '7')
9334 {
db557034 9335 int fpr = *s - '0';
af6bdddf 9336 ++s;
5f47d35b
AM		 9337 if (is_space_char (*s))
9338 ++s;
9339 if (*s == ')')
9340 {
9341 *end_op = s + 1;
1e9cc1c2 9342 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9343 know (r);
9344 return r + fpr;
5f47d35b 9345 }
5f47d35b 9346 }
47926f60 9347 /* We have "%st(" then garbage. */
5f47d35b
AM		 9348 return (const reg_entry *) NULL;
9349 }
9350 }
9351
a60de03c
JB		 9352 if (r == NULL || allow_pseudo_reg)
9353 return r;
9354
0dfbf9d7 9355 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9356 return (const reg_entry *) NULL;
9357
192dc9c6
JB		 9358 if ((r->reg_type.bitfield.reg32
9359 || r->reg_type.bitfield.sreg3
9360 || r->reg_type.bitfield.control
9361 || r->reg_type.bitfield.debug
9362 || r->reg_type.bitfield.test)
9363 && !cpu_arch_flags.bitfield.cpui386)
9364 return (const reg_entry *) NULL;
9365
309d3373
JB		 9366 if (r->reg_type.bitfield.floatreg
9367 && !cpu_arch_flags.bitfield.cpu8087
9368 && !cpu_arch_flags.bitfield.cpu287
9369 && !cpu_arch_flags.bitfield.cpu387)
9370 return (const reg_entry *) NULL;
9371
192dc9c6
JB		 9372 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9373 return (const reg_entry *) NULL;
9374
9375 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9376 return (const reg_entry *) NULL;
9377
40f12533
L		 9378 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9379 return (const reg_entry *) NULL;
9380
43234a1e
L		 9381 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9382 && !cpu_arch_flags.bitfield.cpuavx512f)
9383 return (const reg_entry *) NULL;
9384
db51cc60 9385 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9386 if (!allow_index_reg
db51cc60
L		 9387 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9388 return (const reg_entry *) NULL;
9389
43234a1e
L		 9390 /* Upper 16 vector register is only available with VREX in 64bit
9391 mode. */
9392 if ((r->reg_flags & RegVRex))
9393 {
9394 if (!cpu_arch_flags.bitfield.cpuvrex
9395 || flag_code != CODE_64BIT)
9396 return (const reg_entry *) NULL;
9397
9398 i.need_vrex = 1;
9399 }
9400
a60de03c
JB		 9401 if (((r->reg_flags & (RegRex64 | RegRex))
9402 || r->reg_type.bitfield.reg64)
40fb9820 9403 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9404 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9405 && flag_code != CODE_64BIT)
20f0a1fc 9406 return (const reg_entry *) NULL;
1ae00879 9407
b7240065
JB		 9408 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9409 return (const reg_entry *) NULL;
9410
252b5132
RH		 9411 return r;
9412}
4d1bb795
JB		 9413
9414/* REG_STRING starts *before* REGISTER_PREFIX. */
9415
9416static const reg_entry *
9417parse_register (char *reg_string, char **end_op)
9418{
9419 const reg_entry *r;
9420
9421 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9422 r = parse_real_register (reg_string, end_op);
9423 else
9424 r = NULL;
9425 if (!r)
9426 {
9427 char *save = input_line_pointer;
9428 char c;
9429 symbolS *symbolP;
9430
9431 input_line_pointer = reg_string;
9432 c = get_symbol_end ();
9433 symbolP = symbol_find (reg_string);
9434 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9435 {
9436 const expressionS *e = symbol_get_value_expression (symbolP);
9437
0398aac5 9438 know (e->X_op == O_register);
4eed87de 9439 know (e->X_add_number >= 0
c3fe08fa 9440 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9441 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9442 if ((r->reg_flags & RegVRex))
9443 i.need_vrex = 1;
4d1bb795
JB		 9444 *end_op = input_line_pointer;
9445 }
9446 *input_line_pointer = c;
9447 input_line_pointer = save;
9448 }
9449 return r;
9450}
9451
9452int
9453i386_parse_name (char *name, expressionS *e, char *nextcharP)
9454{
9455 const reg_entry *r;
9456 char *end = input_line_pointer;
9457
9458 *end = *nextcharP;
9459 r = parse_register (name, &input_line_pointer);
9460 if (r && end <= input_line_pointer)
9461 {
9462 *nextcharP = *input_line_pointer;
9463 *input_line_pointer = 0;
9464 e->X_op = O_register;
9465 e->X_add_number = r - i386_regtab;
9466 return 1;
9467 }
9468 input_line_pointer = end;
9469 *end = 0;
ee86248c 9470 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9471}
9472
9473void
9474md_operand (expressionS *e)
9475{
ee86248c
JB		 9476 char *end;
9477 const reg_entry *r;
4d1bb795 9478
ee86248c
JB		 9479 switch (*input_line_pointer)
9480 {
9481 case REGISTER_PREFIX:
9482 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9483 if (r)
9484 {
9485 e->X_op = O_register;
9486 e->X_add_number = r - i386_regtab;
9487 input_line_pointer = end;
9488 }
ee86248c
JB		 9489 break;
9490
9491 case '[':
9c2799c2 9492 gas_assert (intel_syntax);
ee86248c
JB		 9493 end = input_line_pointer++;
9494 expression (e);
9495 if (*input_line_pointer == ']')
9496 {
9497 ++input_line_pointer;
9498 e->X_op_symbol = make_expr_symbol (e);
9499 e->X_add_symbol = NULL;
9500 e->X_add_number = 0;
9501 e->X_op = O_index;
9502 }
9503 else
9504 {
9505 e->X_op = O_absent;
9506 input_line_pointer = end;
9507 }
9508 break;
4d1bb795
JB		 9509 }
9510}
9511
252b5132 9512\f
4cc782b5 9513#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9514const char *md_shortopts = "kVQ:sqn";
252b5132 9515#else
12b55ccc 9516const char *md_shortopts = "qn";
252b5132 9517#endif
6e0b89ee 9518
3e73aa7c 9519#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9520#define OPTION_64 (OPTION_MD_BASE + 1)
9521#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9522#define OPTION_MARCH (OPTION_MD_BASE + 3)
9523#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9524#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9525#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9526#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9527#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9528#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9529#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9530#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9531#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9532#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9533#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9534#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9535#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9536#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9537#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
a5094208 9538#define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9539#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
573cc2e5 9540#define OPTION_MNO_SHARED (OPTION_MD_BASE + 21)
b3b91714 9541
99ad8390
NC		 9542struct option md_longopts[] =
9543{
3e73aa7c 9544 {"32", no_argument, NULL, OPTION_32},
321098a5 9545#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9546 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9547 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9548#endif
9549#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9550 {"x32", no_argument, NULL, OPTION_X32},
573cc2e5 9551 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
6e0b89ee 9552#endif
b3b91714 9553 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9554 {"march", required_argument, NULL, OPTION_MARCH},
9555 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9556 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9557 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9558 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9559 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9560 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9561 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9562 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9563 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9564 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9565 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9566 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9567 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9568# if defined (TE_PE) || defined (TE_PEP)
9569 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9570#endif
a5094208 9571 {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX},
d3d3c6db 9572 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
252b5132
RH		 9573 {NULL, no_argument, NULL, 0}
9574};
9575size_t md_longopts_size = sizeof (md_longopts);
9576
9577int
9103f4f4 9578md_parse_option (int c, char *arg)
252b5132 9579{
91d6fa6a 9580 unsigned int j;
6305a203 9581 char *arch, *next;
9103f4f4 9582
252b5132
RH		 9583 switch (c)
9584 {
12b55ccc
L		 9585 case 'n':
9586 optimize_align_code = 0;
9587 break;
9588
a38cf1db
AM		 9589 case 'q':
9590 quiet_warnings = 1;
252b5132
RH		 9591 break;
9592
9593#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9594 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9595 should be emitted or not. FIXME: Not implemented. */
9596 case 'Q':
252b5132
RH		 9597 break;
9598
9599 /* -V: SVR4 argument to print version ID. */
9600 case 'V':
9601 print_version_id ();
9602 break;
9603
a38cf1db
AM		 9604 /* -k: Ignore for FreeBSD compatibility. */
9605 case 'k':
252b5132 9606 break;
4cc782b5
ILT		 9607
9608 case 's':
9609 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9610 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9611 break;
573cc2e5
L		 9612
9613 case OPTION_MNO_SHARED:
9614 no_shared = 1;
9615 break;
99ad8390 9616#endif
321098a5 9617#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9618 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9619 case OPTION_64:
9620 {
9621 const char **list, **l;
9622
3e73aa7c
JH		 9623 list = bfd_target_list ();
9624 for (l = list; *l != NULL; l++)
8620418b 9625 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9626 || strcmp (*l, "coff-x86-64") == 0
9627 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9628 || strcmp (*l, "pei-x86-64") == 0
9629 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9630 {
9631 default_arch = "x86_64";
9632 break;
9633 }
3e73aa7c 9634 if (*l == NULL)
2b5d6a91 9635 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9636 free (list);
9637 }
9638 break;
9639#endif
252b5132 9640
351f65ca 9641#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9642 case OPTION_X32:
351f65ca
L		 9643 if (IS_ELF)
9644 {
9645 const char **list, **l;
9646
9647 list = bfd_target_list ();
9648 for (l = list; *l != NULL; l++)
9649 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9650 {
9651 default_arch = "x86_64:32";
9652 break;
9653 }
9654 if (*l == NULL)
2b5d6a91 9655 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9656 free (list);
9657 }
9658 else
9659 as_fatal (_("32bit x86_64 is only supported for ELF"));
9660 break;
9661#endif
9662
6e0b89ee
AM		 9663 case OPTION_32:
9664 default_arch = "i386";
9665 break;
9666
b3b91714
AM		 9667 case OPTION_DIVIDE:
9668#ifdef SVR4_COMMENT_CHARS
9669 {
9670 char *n, *t;
9671 const char *s;
9672
9673 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9674 t = n;
9675 for (s = i386_comment_chars; *s != '\0'; s++)
9676 if (*s != '/')
9677 *t++ = *s;
9678 *t = '\0';
9679 i386_comment_chars = n;
9680 }
9681#endif
9682 break;
9683
9103f4f4 9684 case OPTION_MARCH:
6305a203
L		 9685 arch = xstrdup (arg);
9686 do
9103f4f4 9687 {
6305a203 9688 if (*arch == '.')
2b5d6a91 9689 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9690 next = strchr (arch, '+');
9691 if (next)
9692 *next++ = '\0';
91d6fa6a 9693 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9694 {
91d6fa6a 9695 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9696 {
6305a203 9697 /* Processor. */
1ded5609
JB		 9698 if (! cpu_arch[j].flags.bitfield.cpui386)
9699 continue;
9700
91d6fa6a 9701 cpu_arch_name = cpu_arch[j].name;
6305a203 9702 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9703 cpu_arch_flags = cpu_arch[j].flags;
9704 cpu_arch_isa = cpu_arch[j].type;
9705 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9706 if (!cpu_arch_tune_set)
9707 {
9708 cpu_arch_tune = cpu_arch_isa;
9709 cpu_arch_tune_flags = cpu_arch_isa_flags;
9710 }
9711 break;
9712 }
91d6fa6a
NC		 9713 else if (*cpu_arch [j].name == '.'
9714 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9715 {
9716 /* ISA entension. */
9717 i386_cpu_flags flags;
309d3373 9718
49021df2 9719 if (!cpu_arch[j].negated)
309d3373 9720 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9721 cpu_arch[j].flags);
309d3373
JB		 9722 else
9723 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9724 cpu_arch[j].flags);
81486035
L		 9725
9726 if (!valid_iamcu_cpu_flags (&flags))
9727 as_fatal (_("`%s' isn't valid for Intel MCU"), arch);
9728 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9729 {
9730 if (cpu_sub_arch_name)
9731 {
9732 char *name = cpu_sub_arch_name;
9733 cpu_sub_arch_name = concat (name,
91d6fa6a 9734 cpu_arch[j].name,
1bf57e9f 9735 (const char *) NULL);
6305a203
L		 9736 free (name);
9737 }
9738 else
91d6fa6a 9739 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9740 cpu_arch_flags = flags;
a586129e 9741 cpu_arch_isa_flags = flags;
6305a203
L		 9742 }
9743 break;
ccc9c027 9744 }
9103f4f4 9745 }
6305a203 9746
91d6fa6a 9747 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9748 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9749
9750 arch = next;
9103f4f4 9751 }
6305a203 9752 while (next != NULL );
9103f4f4
L		 9753 break;
9754
9755 case OPTION_MTUNE:
9756 if (*arg == '.')
2b5d6a91 9757 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9758 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9759 {
91d6fa6a 9760 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9761 {
ccc9c027 9762 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9763 cpu_arch_tune = cpu_arch [j].type;
9764 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9765 break;
9766 }
9767 }
91d6fa6a 9768 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9769 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9770 break;
9771
1efbbeb4
L		 9772 case OPTION_MMNEMONIC:
9773 if (strcasecmp (arg, "att") == 0)
9774 intel_mnemonic = 0;
9775 else if (strcasecmp (arg, "intel") == 0)
9776 intel_mnemonic = 1;
9777 else
2b5d6a91 9778 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9779 break;
9780
9781 case OPTION_MSYNTAX:
9782 if (strcasecmp (arg, "att") == 0)
9783 intel_syntax = 0;
9784 else if (strcasecmp (arg, "intel") == 0)
9785 intel_syntax = 1;
9786 else
2b5d6a91 9787 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9788 break;
9789
9790 case OPTION_MINDEX_REG:
9791 allow_index_reg = 1;
9792 break;
9793
9794 case OPTION_MNAKED_REG:
9795 allow_naked_reg = 1;
9796 break;
9797
9798 case OPTION_MOLD_GCC:
9799 old_gcc = 1;
1efbbeb4
L		 9800 break;
9801
c0f3af97
L		 9802 case OPTION_MSSE2AVX:
9803 sse2avx = 1;
9804 break;
9805
daf50ae7
L		 9806 case OPTION_MSSE_CHECK:
9807 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9808 sse_check = check_error;
daf50ae7 9809 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9810 sse_check = check_warning;
daf50ae7 9811 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9812 sse_check = check_none;
daf50ae7 9813 else
2b5d6a91 9814 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9815 break;
9816
7bab8ab5
JB		 9817 case OPTION_MOPERAND_CHECK:
9818 if (strcasecmp (arg, "error") == 0)
9819 operand_check = check_error;
9820 else if (strcasecmp (arg, "warning") == 0)
9821 operand_check = check_warning;
9822 else if (strcasecmp (arg, "none") == 0)
9823 operand_check = check_none;
9824 else
9825 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9826 break;
9827
539f890d
L		 9828 case OPTION_MAVXSCALAR:
9829 if (strcasecmp (arg, "128") == 0)
9830 avxscalar = vex128;
9831 else if (strcasecmp (arg, "256") == 0)
9832 avxscalar = vex256;
9833 else
2b5d6a91 9834 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9835 break;
9836
7e8b059b
L		 9837 case OPTION_MADD_BND_PREFIX:
9838 add_bnd_prefix = 1;
9839 break;
9840
43234a1e
L		 9841 case OPTION_MEVEXLIG:
9842 if (strcmp (arg, "128") == 0)
9843 evexlig = evexl128;
9844 else if (strcmp (arg, "256") == 0)
9845 evexlig = evexl256;
9846 else if (strcmp (arg, "512") == 0)
9847 evexlig = evexl512;
9848 else
9849 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9850 break;
9851
d3d3c6db
IT		 9852 case OPTION_MEVEXRCIG:
9853 if (strcmp (arg, "rne") == 0)
9854 evexrcig = rne;
9855 else if (strcmp (arg, "rd") == 0)
9856 evexrcig = rd;
9857 else if (strcmp (arg, "ru") == 0)
9858 evexrcig = ru;
9859 else if (strcmp (arg, "rz") == 0)
9860 evexrcig = rz;
9861 else
9862 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
9863 break;
9864
43234a1e
L		 9865 case OPTION_MEVEXWIG:
9866 if (strcmp (arg, "0") == 0)
9867 evexwig = evexw0;
9868 else if (strcmp (arg, "1") == 0)
9869 evexwig = evexw1;
9870 else
9871 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9872 break;
9873
167ad85b
TG		 9874# if defined (TE_PE) || defined (TE_PEP)
9875 case OPTION_MBIG_OBJ:
9876 use_big_obj = 1;
9877 break;
9878#endif
9879
a5094208 9880 case OPTION_OMIT_LOCK_PREFIX:
d022bddd
IT		 9881 if (strcasecmp (arg, "yes") == 0)
9882 omit_lock_prefix = 1;
9883 else if (strcasecmp (arg, "no") == 0)
9884 omit_lock_prefix = 0;
9885 else
9886 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
9887 break;
9888
252b5132
RH		 9889 default:
9890 return 0;
9891 }
9892 return 1;
9893}
9894
8a2c8fef
L		 9895#define MESSAGE_TEMPLATE \
9896" "
9897
9898static void
1ded5609 9899show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9900{
9901 static char message[] = MESSAGE_TEMPLATE;
9902 char *start = message + 27;
9903 char *p;
9904 int size = sizeof (MESSAGE_TEMPLATE);
9905 int left;
9906 const char *name;
9907 int len;
9908 unsigned int j;
9909
9910 p = start;
9911 left = size - (start - message);
9912 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9913 {
9914 /* Should it be skipped? */
9915 if (cpu_arch [j].skip)
9916 continue;
9917
9918 name = cpu_arch [j].name;
9919 len = cpu_arch [j].len;
9920 if (*name == '.')
9921 {
9922 /* It is an extension. Skip if we aren't asked to show it. */
9923 if (ext)
9924 {
9925 name++;
9926 len--;
9927 }
9928 else
9929 continue;
9930 }
9931 else if (ext)
9932 {
9933 /* It is an processor. Skip if we show only extension. */
9934 continue;
9935 }
1ded5609
JB		 9936 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9937 {
9938 /* It is an impossible processor - skip. */
9939 continue;
9940 }
8a2c8fef
L		 9941
9942 /* Reserve 2 spaces for ", " or ",\0" */
9943 left -= len + 2;
9944
9945 /* Check if there is any room. */
9946 if (left >= 0)
9947 {
9948 if (p != start)
9949 {
9950 *p++ = ',';
9951 *p++ = ' ';
9952 }
9953 p = mempcpy (p, name, len);
9954 }
9955 else
9956 {
9957 /* Output the current message now and start a new one. */
9958 *p++ = ',';
9959 *p = '\0';
9960 fprintf (stream, "%s\n", message);
9961 p = start;
9962 left = size - (start - message) - len - 2;
8d63c93e 9963
8a2c8fef
L		 9964 gas_assert (left >= 0);
9965
9966 p = mempcpy (p, name, len);
9967 }
9968 }
9969
9970 *p = '\0';
9971 fprintf (stream, "%s\n", message);
9972}
9973
252b5132 9974void
8a2c8fef 9975md_show_usage (FILE *stream)
252b5132 9976{
4cc782b5
ILT		 9977#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9978 fprintf (stream, _("\
a38cf1db
AM		 9979 -Q ignored\n\
9980 -V print assembler version number\n\
b3b91714
AM		 9981 -k ignored\n"));
9982#endif
9983 fprintf (stream, _("\
12b55ccc 9984 -n Do not optimize code alignment\n\
b3b91714
AM		 9985 -q quieten some warnings\n"));
9986#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9987 fprintf (stream, _("\
a38cf1db 9988 -s ignored\n"));
b3b91714 9989#endif
321098a5
L		 9990#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9991 || defined (TE_PE) || defined (TE_PEP))
751d281c 9992 fprintf (stream, _("\
570561f7 9993 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 9994#endif
b3b91714
AM		 9995#ifdef SVR4_COMMENT_CHARS
9996 fprintf (stream, _("\
9997 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 9998#else
9999 fprintf (stream, _("\
b3b91714 10000 --divide ignored\n"));
4cc782b5 10001#endif
9103f4f4 10002 fprintf (stream, _("\
6305a203 10003 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10004 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10005 show_arch (stream, 0, 1);
8a2c8fef
L		 10006 fprintf (stream, _("\
10007 EXTENSION is combination of:\n"));
1ded5609 10008 show_arch (stream, 1, 0);
6305a203 10009 fprintf (stream, _("\
8a2c8fef 10010 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10011 show_arch (stream, 0, 0);
ba104c83 10012 fprintf (stream, _("\
c0f3af97
L		 10013 -msse2avx encode SSE instructions with VEX prefix\n"));
10014 fprintf (stream, _("\
daf50ae7
L		 10015 -msse-check=[none|error|warning]\n\
10016 check SSE instructions\n"));
10017 fprintf (stream, _("\
7bab8ab5
JB		 10018 -moperand-check=[none|error|warning]\n\
10019 check operand combinations for validity\n"));
10020 fprintf (stream, _("\
539f890d
L		 10021 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10022 length\n"));
10023 fprintf (stream, _("\
43234a1e
L		 10024 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10025 length\n"));
10026 fprintf (stream, _("\
10027 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10028 for EVEX.W bit ignored instructions\n"));
10029 fprintf (stream, _("\
d3d3c6db
IT		 10030 -mevexrcig=[rne|rd|ru|rz]\n\
10031 encode EVEX instructions with specific EVEX.RC value\n\
10032 for SAE-only ignored instructions\n"));
10033 fprintf (stream, _("\
ba104c83
L		 10034 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10035 fprintf (stream, _("\
10036 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10037 fprintf (stream, _("\
10038 -mindex-reg support pseudo index registers\n"));
10039 fprintf (stream, _("\
10040 -mnaked-reg don't require `%%' prefix for registers\n"));
10041 fprintf (stream, _("\
10042 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10043 fprintf (stream, _("\
10044 -madd-bnd-prefix add BND prefix for all valid branches\n"));
573cc2e5
L		 10045 fprintf (stream, _("\
10046 -mno-shared enable branch optimization for non shared code\n"));
167ad85b
TG		 10047# if defined (TE_PE) || defined (TE_PEP)
10048 fprintf (stream, _("\
10049 -mbig-obj generate big object files\n"));
10050#endif
d022bddd
IT		 10051 fprintf (stream, _("\
10052 -momit-lock-prefix=[no|yes]\n\
10053 strip all lock prefixes\n"));
252b5132
RH		 10054}
10055
3e73aa7c 10056#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10057 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10058 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10059
10060/* Pick the target format to use. */
10061
47926f60 10062const char *
e3bb37b5 10063i386_target_format (void)
252b5132 10064{
351f65ca
L		 10065 if (!strncmp (default_arch, "x86_64", 6))
10066 {
10067 update_code_flag (CODE_64BIT, 1);
10068 if (default_arch[6] == '\0')
7f56bc95 10069 x86_elf_abi = X86_64_ABI;
351f65ca 10070 else
7f56bc95 10071 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10072 }
3e73aa7c 10073 else if (!strcmp (default_arch, "i386"))
78f12dd3 10074 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10075 else if (!strcmp (default_arch, "iamcu"))
10076 {
10077 update_code_flag (CODE_32BIT, 1);
10078 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10079 {
10080 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10081 cpu_arch_name = "iamcu";
10082 cpu_sub_arch_name = NULL;
10083 cpu_arch_flags = iamcu_flags;
10084 cpu_arch_isa = PROCESSOR_IAMCU;
10085 cpu_arch_isa_flags = iamcu_flags;
10086 if (!cpu_arch_tune_set)
10087 {
10088 cpu_arch_tune = cpu_arch_isa;
10089 cpu_arch_tune_flags = cpu_arch_isa_flags;
10090 }
10091 }
10092 else
10093 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10094 cpu_arch_name);
10095 }
3e73aa7c 10096 else
2b5d6a91 10097 as_fatal (_("unknown architecture"));
89507696
JB		 10098
10099 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10100 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10101 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10102 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10103
252b5132
RH		 10104 switch (OUTPUT_FLAVOR)
10105 {
9384f2ff 10106#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10107 case bfd_target_aout_flavour:
47926f60 10108 return AOUT_TARGET_FORMAT;
4c63da97 10109#endif
9384f2ff
AM		 10110#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10111# if defined (TE_PE) || defined (TE_PEP)
10112 case bfd_target_coff_flavour:
167ad85b
TG		 10113 if (flag_code == CODE_64BIT)
10114 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10115 else
10116 return "pe-i386";
9384f2ff 10117# elif defined (TE_GO32)
0561d57c
JK		 10118 case bfd_target_coff_flavour:
10119 return "coff-go32";
9384f2ff 10120# else
252b5132
RH		 10121 case bfd_target_coff_flavour:
10122 return "coff-i386";
9384f2ff 10123# endif
4c63da97 10124#endif
3e73aa7c 10125#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10126 case bfd_target_elf_flavour:
3e73aa7c 10127 {
351f65ca
L		 10128 const char *format;
10129
10130 switch (x86_elf_abi)
4fa24527 10131 {
351f65ca
L		 10132 default:
10133 format = ELF_TARGET_FORMAT;
10134 break;
7f56bc95 10135 case X86_64_ABI:
351f65ca 10136 use_rela_relocations = 1;
4fa24527 10137 object_64bit = 1;
351f65ca
L		 10138 format = ELF_TARGET_FORMAT64;
10139 break;
7f56bc95 10140 case X86_64_X32_ABI:
4fa24527 10141 use_rela_relocations = 1;
351f65ca 10142 object_64bit = 1;
862be3fb 10143 disallow_64bit_reloc = 1;
351f65ca
L		 10144 format = ELF_TARGET_FORMAT32;
10145 break;
4fa24527 10146 }
3632d14b 10147 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10148 {
7f56bc95 10149 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10150 as_fatal (_("Intel L1OM is 64bit only"));
10151 return ELF_TARGET_L1OM_FORMAT;
10152 }
b49f93f6 10153 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10154 {
10155 if (x86_elf_abi != X86_64_ABI)
10156 as_fatal (_("Intel K1OM is 64bit only"));
10157 return ELF_TARGET_K1OM_FORMAT;
10158 }
81486035
L		 10159 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10160 {
10161 if (x86_elf_abi != I386_ABI)
10162 as_fatal (_("Intel MCU is 32bit only"));
10163 return ELF_TARGET_IAMCU_FORMAT;
10164 }
8a9036a4 10165 else
351f65ca 10166 return format;
3e73aa7c 10167 }
e57f8c65
TG		 10168#endif
10169#if defined (OBJ_MACH_O)
10170 case bfd_target_mach_o_flavour:
d382c579
TG		 10171 if (flag_code == CODE_64BIT)
10172 {
10173 use_rela_relocations = 1;
10174 object_64bit = 1;
10175 return "mach-o-x86-64";
10176 }
10177 else
10178 return "mach-o-i386";
4c63da97 10179#endif
252b5132
RH		 10180 default:
10181 abort ();
10182 return NULL;
10183 }
10184}
10185
47926f60 10186#endif /* OBJ_MAYBE_ more than one */
252b5132 10187\f
252b5132 10188symbolS *
7016a5d5 10189md_undefined_symbol (char *name)
252b5132 10190{
18dc2407
ILT		 10191 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10192 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10193 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10194 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10195 {
10196 if (!GOT_symbol)
10197 {
10198 if (symbol_find (name))
10199 as_bad (_("GOT already in symbol table"));
10200 GOT_symbol = symbol_new (name, undefined_section,
10201 (valueT) 0, &zero_address_frag);
10202 };
10203 return GOT_symbol;
10204 }
252b5132
RH		 10205 return 0;
10206}
10207
10208/* Round up a section size to the appropriate boundary. */
47926f60 10209
252b5132 10210valueT
7016a5d5 10211md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10212{
4c63da97
AM		 10213#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10214 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10215 {
10216 /* For a.out, force the section size to be aligned. If we don't do
10217 this, BFD will align it for us, but it will not write out the
10218 final bytes of the section. This may be a bug in BFD, but it is
10219 easier to fix it here since that is how the other a.out targets
10220 work. */
10221 int align;
10222
10223 align = bfd_get_section_alignment (stdoutput, segment);
10224 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10225 }
252b5132
RH		 10226#endif
10227
10228 return size;
10229}
10230
10231/* On the i386, PC-relative offsets are relative to the start of the
10232 next instruction. That is, the address of the offset, plus its
10233 size, since the offset is always the last part of the insn. */
10234
10235long
e3bb37b5 10236md_pcrel_from (fixS *fixP)
252b5132
RH		 10237{
10238 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10239}
10240
10241#ifndef I386COFF
10242
10243static void
e3bb37b5 10244s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10245{
29b0f896 10246 int temp;
252b5132 10247
8a75718c
JB		 10248#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10249 if (IS_ELF)
10250 obj_elf_section_change_hook ();
10251#endif
252b5132
RH		 10252 temp = get_absolute_expression ();
10253 subseg_set (bss_section, (subsegT) temp);
10254 demand_empty_rest_of_line ();
10255}
10256
10257#endif
10258
252b5132 10259void
e3bb37b5 10260i386_validate_fix (fixS *fixp)
252b5132
RH		 10261{
10262 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10263 {
23df1078
JH		 10264 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10265 {
4fa24527 10266 if (!object_64bit)
23df1078
JH		 10267 abort ();
10268 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10269 }
10270 else
10271 {
4fa24527 10272 if (!object_64bit)
d6ab8113
JB		 10273 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10274 else
10275 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 10276 }
252b5132
RH		 10277 fixp->fx_subsy = 0;
10278 }
10279}
10280
252b5132 10281arelent *
7016a5d5 10282tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10283{
10284 arelent *rel;
10285 bfd_reloc_code_real_type code;
10286
10287 switch (fixp->fx_r_type)
10288 {
8ce3d284 10289#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10290 case BFD_RELOC_SIZE32:
10291 case BFD_RELOC_SIZE64:
10292 if (S_IS_DEFINED (fixp->fx_addsy)
10293 && !S_IS_EXTERNAL (fixp->fx_addsy))
10294 {
10295 /* Resolve size relocation against local symbol to size of
10296 the symbol plus addend. */
10297 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10298 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10299 && !fits_in_unsigned_long (value))
10300 as_bad_where (fixp->fx_file, fixp->fx_line,
10301 _("symbol size computation overflow"));
10302 fixp->fx_addsy = NULL;
10303 fixp->fx_subsy = NULL;
10304 md_apply_fix (fixp, (valueT *) &value, NULL);
10305 return NULL;
10306 }
8ce3d284 10307#endif
8fd4256d 10308
3e73aa7c
JH		 10309 case BFD_RELOC_X86_64_PLT32:
10310 case BFD_RELOC_X86_64_GOT32:
10311 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 10312 case BFD_RELOC_386_PLT32:
10313 case BFD_RELOC_386_GOT32:
10314 case BFD_RELOC_386_GOTOFF:
10315 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10316 case BFD_RELOC_386_TLS_GD:
10317 case BFD_RELOC_386_TLS_LDM:
10318 case BFD_RELOC_386_TLS_LDO_32:
10319 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10320 case BFD_RELOC_386_TLS_IE:
10321 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10322 case BFD_RELOC_386_TLS_LE_32:
10323 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10324 case BFD_RELOC_386_TLS_GOTDESC:
10325 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10326 case BFD_RELOC_X86_64_TLSGD:
10327 case BFD_RELOC_X86_64_TLSLD:
10328 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10329 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10330 case BFD_RELOC_X86_64_GOTTPOFF:
10331 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10332 case BFD_RELOC_X86_64_TPOFF64:
10333 case BFD_RELOC_X86_64_GOTOFF64:
10334 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10335 case BFD_RELOC_X86_64_GOT64:
10336 case BFD_RELOC_X86_64_GOTPCREL64:
10337 case BFD_RELOC_X86_64_GOTPC64:
10338 case BFD_RELOC_X86_64_GOTPLT64:
10339 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10340 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10341 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10342 case BFD_RELOC_RVA:
10343 case BFD_RELOC_VTABLE_ENTRY:
10344 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10345#ifdef TE_PE
10346 case BFD_RELOC_32_SECREL:
10347#endif
252b5132
RH		 10348 code = fixp->fx_r_type;
10349 break;
dbbaec26
L		 10350 case BFD_RELOC_X86_64_32S:
10351 if (!fixp->fx_pcrel)
10352 {
10353 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10354 code = fixp->fx_r_type;
10355 break;
10356 }
252b5132 10357 default:
93382f6d 10358 if (fixp->fx_pcrel)
252b5132 10359 {
93382f6d
AM		 10360 switch (fixp->fx_size)
10361 {
10362 default:
b091f402
AM		 10363 as_bad_where (fixp->fx_file, fixp->fx_line,
10364 _("can not do %d byte pc-relative relocation"),
10365 fixp->fx_size);
93382f6d
AM		 10366 code = BFD_RELOC_32_PCREL;
10367 break;
10368 case 1: code = BFD_RELOC_8_PCREL; break;
10369 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10370 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10371#ifdef BFD64
10372 case 8: code = BFD_RELOC_64_PCREL; break;
10373#endif
93382f6d
AM		 10374 }
10375 }
10376 else
10377 {
10378 switch (fixp->fx_size)
10379 {
10380 default:
b091f402
AM		 10381 as_bad_where (fixp->fx_file, fixp->fx_line,
10382 _("can not do %d byte relocation"),
10383 fixp->fx_size);
93382f6d
AM		 10384 code = BFD_RELOC_32;
10385 break;
10386 case 1: code = BFD_RELOC_8; break;
10387 case 2: code = BFD_RELOC_16; break;
10388 case 4: code = BFD_RELOC_32; break;
937149dd 10389#ifdef BFD64
3e73aa7c 10390 case 8: code = BFD_RELOC_64; break;
937149dd 10391#endif
93382f6d 10392 }
252b5132
RH		 10393 }
10394 break;
10395 }
252b5132 10396
d182319b
JB		 10397 if ((code == BFD_RELOC_32
10398 || code == BFD_RELOC_32_PCREL
10399 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10400 && GOT_symbol
10401 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10402 {
4fa24527 10403 if (!object_64bit)
d6ab8113
JB		 10404 code = BFD_RELOC_386_GOTPC;
10405 else
10406 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10407 }
7b81dfbb
AJ		 10408 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10409 && GOT_symbol
10410 && fixp->fx_addsy == GOT_symbol)
10411 {
10412 code = BFD_RELOC_X86_64_GOTPC64;
10413 }
252b5132
RH		 10414
10415 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10416 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10417 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10418
10419 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10420
3e73aa7c
JH		 10421 if (!use_rela_relocations)
10422 {
10423 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10424 vtable entry to be used in the relocation's section offset. */
10425 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10426 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10427#if defined (OBJ_COFF) && defined (TE_PE)
10428 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10429 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10430 else
10431#endif
c6682705 10432 rel->addend = 0;
3e73aa7c
JH		 10433 }
10434 /* Use the rela in 64bit mode. */
252b5132 10435 else
3e73aa7c 10436 {
862be3fb
L		 10437 if (disallow_64bit_reloc)
10438 switch (code)
10439 {
862be3fb
L		 10440 case BFD_RELOC_X86_64_DTPOFF64:
10441 case BFD_RELOC_X86_64_TPOFF64:
10442 case BFD_RELOC_64_PCREL:
10443 case BFD_RELOC_X86_64_GOTOFF64:
10444 case BFD_RELOC_X86_64_GOT64:
10445 case BFD_RELOC_X86_64_GOTPCREL64:
10446 case BFD_RELOC_X86_64_GOTPC64:
10447 case BFD_RELOC_X86_64_GOTPLT64:
10448 case BFD_RELOC_X86_64_PLTOFF64:
10449 as_bad_where (fixp->fx_file, fixp->fx_line,
10450 _("cannot represent relocation type %s in x32 mode"),
10451 bfd_get_reloc_code_name (code));
10452 break;
10453 default:
10454 break;
10455 }
10456
062cd5e7
AS		 10457 if (!fixp->fx_pcrel)
10458 rel->addend = fixp->fx_offset;
10459 else
10460 switch (code)
10461 {
10462 case BFD_RELOC_X86_64_PLT32:
10463 case BFD_RELOC_X86_64_GOT32:
10464 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 10465 case BFD_RELOC_X86_64_TLSGD:
10466 case BFD_RELOC_X86_64_TLSLD:
10467 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10468 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10469 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10470 rel->addend = fixp->fx_offset - fixp->fx_size;
10471 break;
10472 default:
10473 rel->addend = (section->vma
10474 - fixp->fx_size
10475 + fixp->fx_addnumber
10476 + md_pcrel_from (fixp));
10477 break;
10478 }
3e73aa7c
JH		 10479 }
10480
252b5132
RH		 10481 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10482 if (rel->howto == NULL)
10483 {
10484 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10485 _("cannot represent relocation type %s"),
252b5132
RH		 10486 bfd_get_reloc_code_name (code));
10487 /* Set howto to a garbage value so that we can keep going. */
10488 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10489 gas_assert (rel->howto != NULL);
252b5132
RH		 10490 }
10491
10492 return rel;
10493}
10494
ee86248c 10495#include "tc-i386-intel.c"
54cfded0 10496
a60de03c
JB		 10497void
10498tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10499{
a60de03c
JB		 10500 int saved_naked_reg;
10501 char saved_register_dot;
54cfded0 10502
a60de03c
JB		 10503 saved_naked_reg = allow_naked_reg;
10504 allow_naked_reg = 1;
10505 saved_register_dot = register_chars['.'];
10506 register_chars['.'] = '.';
10507 allow_pseudo_reg = 1;
10508 expression_and_evaluate (exp);
10509 allow_pseudo_reg = 0;
10510 register_chars['.'] = saved_register_dot;
10511 allow_naked_reg = saved_naked_reg;
10512
e96d56a1 10513 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10514 {
a60de03c
JB		 10515 if ((addressT) exp->X_add_number < i386_regtab_size)
10516 {
10517 exp->X_op = O_constant;
10518 exp->X_add_number = i386_regtab[exp->X_add_number]
10519 .dw2_regnum[flag_code >> 1];
10520 }
10521 else
10522 exp->X_op = O_illegal;
54cfded0 10523 }
54cfded0
AM		 10524}
10525
10526void
10527tc_x86_frame_initial_instructions (void)
10528{
a60de03c
JB		 10529 static unsigned int sp_regno[2];
10530
10531 if (!sp_regno[flag_code >> 1])
10532 {
10533 char *saved_input = input_line_pointer;
10534 char sp[][4] = {"esp", "rsp"};
10535 expressionS exp;
a4447b93 10536
a60de03c
JB		 10537 input_line_pointer = sp[flag_code >> 1];
10538 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10539 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10540 sp_regno[flag_code >> 1] = exp.X_add_number;
10541 input_line_pointer = saved_input;
10542 }
a4447b93 10543
61ff971f
L		 10544 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10545 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10546}
d2b2c203 10547
d7921315
L		 10548int
10549x86_dwarf2_addr_size (void)
10550{
10551#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10552 if (x86_elf_abi == X86_64_X32_ABI)
10553 return 4;
10554#endif
10555 return bfd_arch_bits_per_address (stdoutput) / 8;
10556}
10557
d2b2c203
DJ		 10558int
10559i386_elf_section_type (const char *str, size_t len)
10560{
10561 if (flag_code == CODE_64BIT
10562 && len == sizeof ("unwind") - 1
10563 && strncmp (str, "unwind", 6) == 0)
10564 return SHT_X86_64_UNWIND;
10565
10566 return -1;
10567}
bb41ade5 10568
ad5fec3b
EB		 10569#ifdef TE_SOLARIS
10570void
10571i386_solaris_fix_up_eh_frame (segT sec)
10572{
10573 if (flag_code == CODE_64BIT)
10574 elf_section_type (sec) = SHT_X86_64_UNWIND;
10575}
10576#endif
10577
bb41ade5
AM		 10578#ifdef TE_PE
10579void
10580tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10581{
91d6fa6a 10582 expressionS exp;
bb41ade5 10583
91d6fa6a
NC		 10584 exp.X_op = O_secrel;
10585 exp.X_add_symbol = symbol;
10586 exp.X_add_number = 0;
10587 emit_expr (&exp, size);
bb41ade5
AM		 10588}
10589#endif
3b22753a
L		 10590
10591#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10592/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10593
01e1a5bc 10594bfd_vma
3b22753a
L		 10595x86_64_section_letter (int letter, char **ptr_msg)
10596{
10597 if (flag_code == CODE_64BIT)
10598 {
10599 if (letter == 'l')
10600 return SHF_X86_64_LARGE;
10601
8f3bae45 10602 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10603 }
3b22753a 10604 else
8f3bae45 10605 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10606 return -1;
10607}
10608
01e1a5bc 10609bfd_vma
3b22753a
L		 10610x86_64_section_word (char *str, size_t len)
10611{
8620418b 10612 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10613 return SHF_X86_64_LARGE;
10614
10615 return -1;
10616}
10617
10618static void
10619handle_large_common (int small ATTRIBUTE_UNUSED)
10620{
10621 if (flag_code != CODE_64BIT)
10622 {
10623 s_comm_internal (0, elf_common_parse);
10624 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10625 }
10626 else
10627 {
10628 static segT lbss_section;
10629 asection *saved_com_section_ptr = elf_com_section_ptr;
10630 asection *saved_bss_section = bss_section;
10631
10632 if (lbss_section == NULL)
10633 {
10634 flagword applicable;
10635 segT seg = now_seg;
10636 subsegT subseg = now_subseg;
10637
10638 /* The .lbss section is for local .largecomm symbols. */
10639 lbss_section = subseg_new (".lbss", 0);
10640 applicable = bfd_applicable_section_flags (stdoutput);
10641 bfd_set_section_flags (stdoutput, lbss_section,
10642 applicable & SEC_ALLOC);
10643 seg_info (lbss_section)->bss = 1;
10644
10645 subseg_set (seg, subseg);
10646 }
10647
10648 elf_com_section_ptr = &_bfd_elf_large_com_section;
10649 bss_section = lbss_section;
10650
10651 s_comm_internal (0, elf_common_parse);
10652
10653 elf_com_section_ptr = saved_com_section_ptr;
10654 bss_section = saved_bss_section;
10655 }
10656}
10657#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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