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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0bfee649 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
c32fa91d 62 REP_PREFIX, LOCK_PREFIX. */
6305a203
L		 63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
c32fa91d
L		 67#define REP_PREFIX 4
68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 86/* Intel Syntax. Use a non-ascii letter since since it never appears
87 in instructions. */
88#define LONG_DOUBLE_MNEM_SUFFIX '\1'
89
90#define END_OF_INSN '\0'
91
92/*
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
97 END.
98 */
99typedef struct
100{
d3ce72d0
NC		 101 const insn_template *start;
102 const insn_template *end;
6305a203
L		 103}
104templates;
105
106/* 386 operand encoding bytes: see 386 book for details of this. */
107typedef struct
108{
109 unsigned int regmem; /* codes register or memory operand */
110 unsigned int reg; /* codes register operand (or extended opcode) */
111 unsigned int mode; /* how to interpret regmem & reg */
112}
113modrm_byte;
114
115/* x86-64 extension prefix. */
116typedef int rex_byte;
117
6305a203
L		 118/* 386 opcode byte to code indirect addressing. */
119typedef struct
120{
121 unsigned base;
122 unsigned index;
123 unsigned scale;
124}
125sib_byte;
126
6305a203
L		 127/* x86 arch names, types and features */
128typedef struct
129{
130 const char *name; /* arch name */
8a2c8fef 131 unsigned int len; /* arch string length */
6305a203
L		 132 enum processor_type type; /* arch type */
133 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 134 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 135}
136arch_entry;
137
e3bb37b5
L		 138static void set_code_flag (int);
139static void set_16bit_gcc_code_flag (int);
140static void set_intel_syntax (int);
1efbbeb4 141static void set_intel_mnemonic (int);
db51cc60 142static void set_allow_index_reg (int);
cb19c032 143static void set_sse_check (int);
e3bb37b5 144static void set_cpu_arch (int);
6482c264 145#ifdef TE_PE
e3bb37b5 146static void pe_directive_secrel (int);
6482c264 147#endif
e3bb37b5
L		 148static void signed_cons (int);
149static char *output_invalid (int c);
ee86248c
JB		 150static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
151 const char *);
152static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
153 const char *);
a7619375 154static int i386_att_operand (char *);
e3bb37b5 155static int i386_intel_operand (char *, int);
ee86248c
JB		 156static int i386_intel_simplify (expressionS *);
157static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 158static const reg_entry *parse_register (char *, char **);
159static char *parse_insn (char *, char *);
160static char *parse_operands (char *, const char *);
161static void swap_operands (void);
4d456e3d 162static void swap_2_operands (int, int);
e3bb37b5
L		 163static void optimize_imm (void);
164static void optimize_disp (void);
d3ce72d0 165static const insn_template *match_template (void);
e3bb37b5
L		 166static int check_string (void);
167static int process_suffix (void);
168static int check_byte_reg (void);
169static int check_long_reg (void);
170static int check_qword_reg (void);
171static int check_word_reg (void);
172static int finalize_imm (void);
173static int process_operands (void);
174static const seg_entry *build_modrm_byte (void);
175static void output_insn (void);
176static void output_imm (fragS *, offsetT);
177static void output_disp (fragS *, offsetT);
29b0f896 178#ifndef I386COFF
e3bb37b5 179static void s_bss (int);
252b5132 180#endif
17d4e2a2
L		 181#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
182static void handle_large_common (int small ATTRIBUTE_UNUSED);
183#endif
252b5132 184
a847613f 185static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 186
c0f3af97
L		 187/* VEX prefix. */
188typedef struct
189{
190 /* VEX prefix is either 2 byte or 3 byte. */
191 unsigned char bytes[3];
192 unsigned int length;
193 /* Destination or source register specifier. */
194 const reg_entry *register_specifier;
195} vex_prefix;
196
252b5132 197/* 'md_assemble ()' gathers together information and puts it into a
47926f60 198 i386_insn. */
252b5132 199
520dc8e8
AM		 200union i386_op
201 {
202 expressionS *disps;
203 expressionS *imms;
204 const reg_entry *regs;
205 };
206
252b5132
RH		 207struct _i386_insn
208 {
47926f60 209 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 210 insn_template tm;
252b5132 211
7d5e4556
L		 212 /* SUFFIX holds the instruction size suffix for byte, word, dword
213 or qword, if given. */
252b5132
RH		 214 char suffix;
215
47926f60 216 /* OPERANDS gives the number of given operands. */
252b5132
RH		 217 unsigned int operands;
218
219 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
220 of given register, displacement, memory operands and immediate
47926f60 221 operands. */
252b5132
RH		 222 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
223
224 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 225 use OP[i] for the corresponding operand. */
40fb9820 226 i386_operand_type types[MAX_OPERANDS];
252b5132 227
520dc8e8
AM		 228 /* Displacement expression, immediate expression, or register for each
229 operand. */
230 union i386_op op[MAX_OPERANDS];
252b5132 231
3e73aa7c
JH		 232 /* Flags for operands. */
233 unsigned int flags[MAX_OPERANDS];
234#define Operand_PCrel 1
235
252b5132 236 /* Relocation type for operand */
f86103b7 237 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 238
252b5132
RH		 239 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
240 the base index byte below. */
241 const reg_entry *base_reg;
242 const reg_entry *index_reg;
243 unsigned int log2_scale_factor;
244
245 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 246 explicit segment overrides are given. */
ce8a8b2f 247 const seg_entry *seg[2];
252b5132
RH		 248
249 /* PREFIX holds all the given prefix opcodes (usually null).
250 PREFIXES is the number of prefix opcodes. */
251 unsigned int prefixes;
252 unsigned char prefix[MAX_PREFIXES];
253
254 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 255 addressing modes of this insn are encoded. */
252b5132 256 modrm_byte rm;
3e73aa7c 257 rex_byte rex;
252b5132 258 sib_byte sib;
c0f3af97 259 vex_prefix vex;
b6169b20
L		 260
261 /* Swap operand in encoding. */
4473e004 262 unsigned int swap_operand;
252b5132
RH		 263 };
264
265typedef struct _i386_insn i386_insn;
266
267/* List of chars besides those in app.c:symbol_chars that can start an
268 operand. Used to prevent the scrubber eating vital white-space. */
32137342 269const char extra_symbol_chars[] = "*%-(["
252b5132 270#ifdef LEX_AT
32137342
NC		 271 "@"
272#endif
273#ifdef LEX_QM
274 "?"
252b5132 275#endif
32137342 276 ;
252b5132 277
29b0f896
AM		 278#if (defined (TE_I386AIX) \
279 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 280 && !defined (TE_GNU) \
29b0f896 281 && !defined (TE_LINUX) \
32137342 282 && !defined (TE_NETWARE) \
29b0f896
AM		 283 && !defined (TE_FreeBSD) \
284 && !defined (TE_NetBSD)))
252b5132 285/* This array holds the chars that always start a comment. If the
b3b91714
AM		 286 pre-processor is disabled, these aren't very useful. The option
287 --divide will remove '/' from this list. */
288const char *i386_comment_chars = "#/";
289#define SVR4_COMMENT_CHARS 1
252b5132 290#define PREFIX_SEPARATOR '\\'
252b5132 291
b3b91714
AM		 292#else
293const char *i386_comment_chars = "#";
294#define PREFIX_SEPARATOR '/'
295#endif
296
252b5132
RH		 297/* This array holds the chars that only start a comment at the beginning of
298 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 299 .line and .file directives will appear in the pre-processed output.
300 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 301 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 302 #NO_APP at the beginning of its output.
303 Also note that comments started like this one will always work if
252b5132 304 '/' isn't otherwise defined. */
b3b91714 305const char line_comment_chars[] = "#/";
252b5132 306
63a0b638 307const char line_separator_chars[] = ";";
252b5132 308
ce8a8b2f
AM		 309/* Chars that can be used to separate mant from exp in floating point
310 nums. */
252b5132
RH		 311const char EXP_CHARS[] = "eE";
312
ce8a8b2f
AM		 313/* Chars that mean this number is a floating point constant
314 As in 0f12.456
315 or 0d1.2345e12. */
252b5132
RH		 316const char FLT_CHARS[] = "fFdDxX";
317
ce8a8b2f 318/* Tables for lexical analysis. */
252b5132
RH		 319static char mnemonic_chars[256];
320static char register_chars[256];
321static char operand_chars[256];
322static char identifier_chars[256];
323static char digit_chars[256];
324
ce8a8b2f 325/* Lexical macros. */
252b5132
RH		 326#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
327#define is_operand_char(x) (operand_chars[(unsigned char) x])
328#define is_register_char(x) (register_chars[(unsigned char) x])
329#define is_space_char(x) ((x) == ' ')
330#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
331#define is_digit_char(x) (digit_chars[(unsigned char) x])
332
0234cb7c 333/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 334static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
335
336/* md_assemble() always leaves the strings it's passed unaltered. To
337 effect this we maintain a stack of saved characters that we've smashed
338 with '\0's (indicating end of strings for various sub-fields of the
47926f60 339 assembler instruction). */
252b5132 340static char save_stack[32];
ce8a8b2f 341static char *save_stack_p;
252b5132
RH		 342#define END_STRING_AND_SAVE(s) \
343 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
344#define RESTORE_END_STRING(s) \
345 do { *(s) = *--save_stack_p; } while (0)
346
47926f60 347/* The instruction we're assembling. */
252b5132
RH		 348static i386_insn i;
349
350/* Possible templates for current insn. */
351static const templates *current_templates;
352
31b2323c
L		 353/* Per instruction expressionS buffers: max displacements & immediates. */
354static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
355static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 356
47926f60 357/* Current operand we are working on. */
ee86248c 358static int this_operand = -1;
252b5132 359
3e73aa7c
JH		 360/* We support four different modes. FLAG_CODE variable is used to distinguish
361 these. */
362
363enum flag_code {
364 CODE_32BIT,
365 CODE_16BIT,
366 CODE_64BIT };
367
368static enum flag_code flag_code;
4fa24527 369static unsigned int object_64bit;
3e73aa7c
JH		 370static int use_rela_relocations = 0;
371
372/* The names used to print error messages. */
b77a7acd 373static const char *flag_code_names[] =
3e73aa7c
JH		 374 {
375 "32",
376 "16",
377 "64"
378 };
252b5132 379
47926f60
KH		 380/* 1 for intel syntax,
381 0 if att syntax. */
382static int intel_syntax = 0;
252b5132 383
1efbbeb4
L		 384/* 1 for intel mnemonic,
385 0 if att mnemonic. */
386static int intel_mnemonic = !SYSV386_COMPAT;
387
5209009a 388/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 389static int old_gcc = OLDGCC_COMPAT;
390
a60de03c
JB		 391/* 1 if pseudo registers are permitted. */
392static int allow_pseudo_reg = 0;
393
47926f60
KH		 394/* 1 if register prefix % not required. */
395static int allow_naked_reg = 0;
252b5132 396
ba104c83 397/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 398static int allow_index_reg = 0;
399
daf50ae7
L		 400static enum
401 {
402 sse_check_none = 0,
403 sse_check_warning,
404 sse_check_error
405 }
406sse_check;
407
2ca3ace5
L		 408/* Register prefix used for error message. */
409static const char *register_prefix = "%";
410
47926f60
KH		 411/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
412 leave, push, and pop instructions so that gcc has the same stack
413 frame as in 32 bit mode. */
414static char stackop_size = '\0';
eecb386c 415
12b55ccc
L		 416/* Non-zero to optimize code alignment. */
417int optimize_align_code = 1;
418
47926f60
KH		 419/* Non-zero to quieten some warnings. */
420static int quiet_warnings = 0;
a38cf1db 421
47926f60
KH		 422/* CPU name. */
423static const char *cpu_arch_name = NULL;
6305a203 424static char *cpu_sub_arch_name = NULL;
a38cf1db 425
47926f60 426/* CPU feature flags. */
40fb9820
L		 427static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
428
ccc9c027
L		 429/* If we have selected a cpu we are generating instructions for. */
430static int cpu_arch_tune_set = 0;
431
9103f4f4 432/* Cpu we are generating instructions for. */
fbf3f584 433enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 434
435/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 436static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 437
ccc9c027 438/* CPU instruction set architecture used. */
fbf3f584 439enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 440
9103f4f4 441/* CPU feature flags of instruction set architecture used. */
fbf3f584 442i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 443
fddf5b5b
AM		 444/* If set, conditional jumps are not automatically promoted to handle
445 larger than a byte offset. */
446static unsigned int no_cond_jump_promotion = 0;
447
c0f3af97
L		 448/* Encode SSE instructions with VEX prefix. */
449static unsigned int sse2avx;
450
29b0f896 451/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 452static symbolS *GOT_symbol;
29b0f896 453
a4447b93
RH		 454/* The dwarf2 return column, adjusted for 32 or 64 bit. */
455unsigned int x86_dwarf2_return_column;
456
457/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
458int x86_cie_data_alignment;
459
252b5132 460/* Interface to relax_segment.
fddf5b5b
AM		 461 There are 3 major relax states for 386 jump insns because the
462 different types of jumps add different sizes to frags when we're
463 figuring out what sort of jump to choose to reach a given label. */
252b5132 464
47926f60 465/* Types. */
93c2a809
AM		 466#define UNCOND_JUMP 0
467#define COND_JUMP 1
468#define COND_JUMP86 2
fddf5b5b 469
47926f60 470/* Sizes. */
252b5132
RH		 471#define CODE16 1
472#define SMALL 0
29b0f896 473#define SMALL16 (SMALL | CODE16)
252b5132 474#define BIG 2
29b0f896 475#define BIG16 (BIG | CODE16)
252b5132
RH		 476
477#ifndef INLINE
478#ifdef __GNUC__
479#define INLINE __inline__
480#else
481#define INLINE
482#endif
483#endif
484
fddf5b5b
AM		 485#define ENCODE_RELAX_STATE(type, size) \
486 ((relax_substateT) (((type) << 2) | (size)))
487#define TYPE_FROM_RELAX_STATE(s) \
488 ((s) >> 2)
489#define DISP_SIZE_FROM_RELAX_STATE(s) \
490 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 491
492/* This table is used by relax_frag to promote short jumps to long
493 ones where necessary. SMALL (short) jumps may be promoted to BIG
494 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
495 don't allow a short jump in a 32 bit code segment to be promoted to
496 a 16 bit offset jump because it's slower (requires data size
497 prefix), and doesn't work, unless the destination is in the bottom
498 64k of the code segment (The top 16 bits of eip are zeroed). */
499
500const relax_typeS md_relax_table[] =
501{
24eab124
AM		 502 /* The fields are:
503 1) most positive reach of this state,
504 2) most negative reach of this state,
93c2a809 505 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 506 4) which index into the table to try if we can't fit into this one. */
252b5132 507
fddf5b5b 508 /* UNCOND_JUMP states. */
93c2a809
AM		 509 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
510 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
511 /* dword jmp adds 4 bytes to frag:
512 0 extra opcode bytes, 4 displacement bytes. */
252b5132 513 {0, 0, 4, 0},
93c2a809
AM		 514 /* word jmp adds 2 byte2 to frag:
515 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 516 {0, 0, 2, 0},
517
93c2a809
AM		 518 /* COND_JUMP states. */
519 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
520 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
521 /* dword conditionals adds 5 bytes to frag:
522 1 extra opcode byte, 4 displacement bytes. */
523 {0, 0, 5, 0},
fddf5b5b 524 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 525 1 extra opcode byte, 2 displacement bytes. */
526 {0, 0, 3, 0},
527
528 /* COND_JUMP86 states. */
529 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
530 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
531 /* dword conditionals adds 5 bytes to frag:
532 1 extra opcode byte, 4 displacement bytes. */
533 {0, 0, 5, 0},
534 /* word conditionals add 4 bytes to frag:
535 1 displacement byte and a 3 byte long branch insn. */
536 {0, 0, 4, 0}
252b5132
RH		 537};
538
9103f4f4
L		 539static const arch_entry cpu_arch[] =
540{
8a2c8fef
L		 541 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
542 CPU_GENERIC32_FLAGS, 0 },
543 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
544 CPU_GENERIC64_FLAGS, 0 },
545 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
546 CPU_NONE_FLAGS, 0 },
547 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
548 CPU_I186_FLAGS, 0 },
549 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
550 CPU_I286_FLAGS, 0 },
551 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
552 CPU_I386_FLAGS, 0 },
553 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
554 CPU_I486_FLAGS, 0 },
555 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
556 CPU_I586_FLAGS, 0 },
557 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
558 CPU_I686_FLAGS, 0 },
559 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
560 CPU_I586_FLAGS, 0 },
561 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
562 CPU_I686_FLAGS, 0 },
563 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
564 CPU_P2_FLAGS, 0 },
565 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
566 CPU_P3_FLAGS, 0 },
567 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
568 CPU_P4_FLAGS, 0 },
569 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
570 CPU_CORE_FLAGS, 0 },
571 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
572 CPU_NOCONA_FLAGS, 0 },
573 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
574 CPU_CORE_FLAGS, 1 },
575 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
576 CPU_CORE_FLAGS, 0 },
577 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
578 CPU_CORE2_FLAGS, 1 },
579 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
580 CPU_CORE2_FLAGS, 0 },
581 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
582 CPU_COREI7_FLAGS, 0 },
583 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
584 CPU_L1OM_FLAGS, 0 },
585 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
586 CPU_K6_FLAGS, 0 },
587 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
588 CPU_K6_2_FLAGS, 0 },
589 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
590 CPU_ATHLON_FLAGS, 0 },
591 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
592 CPU_K8_FLAGS, 1 },
593 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
594 CPU_K8_FLAGS, 0 },
595 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
596 CPU_K8_FLAGS, 0 },
597 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
598 CPU_AMDFAM10_FLAGS, 0 },
69dd9865
SP		 599 { STRING_COMMA_LEN ("amdfam15"), PROCESSOR_AMDFAM15,
600 CPU_AMDFAM15_FLAGS, 0 },
8a2c8fef
L		 601 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
602 CPU_8087_FLAGS, 0 },
603 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
604 CPU_287_FLAGS, 0 },
605 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
606 CPU_387_FLAGS, 0 },
607 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
608 CPU_ANY87_FLAGS, 0 },
609 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
610 CPU_MMX_FLAGS, 0 },
611 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
612 CPU_3DNOWA_FLAGS, 0 },
613 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
614 CPU_SSE_FLAGS, 0 },
615 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
616 CPU_SSE2_FLAGS, 0 },
617 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
618 CPU_SSE3_FLAGS, 0 },
619 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
620 CPU_SSSE3_FLAGS, 0 },
621 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
622 CPU_SSE4_1_FLAGS, 0 },
623 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
624 CPU_SSE4_2_FLAGS, 0 },
625 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
626 CPU_SSE4_2_FLAGS, 0 },
627 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
628 CPU_ANY_SSE_FLAGS, 0 },
629 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
630 CPU_AVX_FLAGS, 0 },
631 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
632 CPU_ANY_AVX_FLAGS, 0 },
633 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
634 CPU_VMX_FLAGS, 0 },
635 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
636 CPU_SMX_FLAGS, 0 },
637 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
638 CPU_XSAVE_FLAGS, 0 },
639 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
640 CPU_AES_FLAGS, 0 },
641 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
642 CPU_PCLMUL_FLAGS, 0 },
643 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
644 CPU_PCLMUL_FLAGS, 1 },
645 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
646 CPU_FMA_FLAGS, 0 },
647 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
648 CPU_FMA4_FLAGS, 0 },
649 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
650 CPU_XOP_FLAGS, 0 },
651 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
652 CPU_LWP_FLAGS, 0 },
653 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
654 CPU_MOVBE_FLAGS, 0 },
655 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
656 CPU_EPT_FLAGS, 0 },
657 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
658 CPU_CLFLUSH_FLAGS, 0 },
659 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
660 CPU_SYSCALL_FLAGS, 0 },
661 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
662 CPU_RDTSCP_FLAGS, 0 },
663 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
664 CPU_3DNOW_FLAGS, 0 },
665 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
666 CPU_3DNOWA_FLAGS, 0 },
667 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
668 CPU_PADLOCK_FLAGS, 0 },
669 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
670 CPU_SVME_FLAGS, 1 },
671 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
672 CPU_SVME_FLAGS, 0 },
673 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
674 CPU_SSE4A_FLAGS, 0 },
675 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
676 CPU_ABM_FLAGS, 0 },
e413e4e9
AM		 677};
678
704209c0 679#ifdef I386COFF
a6c24e68
NC		 680/* Like s_lcomm_internal in gas/read.c but the alignment string
681 is allowed to be optional. */
682
683static symbolS *
684pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
685{
686 addressT align = 0;
687
688 SKIP_WHITESPACE ();
689
7ab9ffdd 690 if (needs_align
a6c24e68
NC		 691 && *input_line_pointer == ',')
692 {
693 align = parse_align (needs_align - 1);
7ab9ffdd 694
a6c24e68
NC		 695 if (align == (addressT) -1)
696 return NULL;
697 }
698 else
699 {
700 if (size >= 8)
701 align = 3;
702 else if (size >= 4)
703 align = 2;
704 else if (size >= 2)
705 align = 1;
706 else
707 align = 0;
708 }
709
710 bss_alloc (symbolP, size, align);
711 return symbolP;
712}
713
704209c0 714static void
a6c24e68
NC		 715pe_lcomm (int needs_align)
716{
717 s_comm_internal (needs_align * 2, pe_lcomm_internal);
718}
704209c0 719#endif
a6c24e68 720
29b0f896
AM		 721const pseudo_typeS md_pseudo_table[] =
722{
723#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
724 {"align", s_align_bytes, 0},
725#else
726 {"align", s_align_ptwo, 0},
727#endif
728 {"arch", set_cpu_arch, 0},
729#ifndef I386COFF
730 {"bss", s_bss, 0},
a6c24e68
NC		 731#else
732 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 733#endif
734 {"ffloat", float_cons, 'f'},
735 {"dfloat", float_cons, 'd'},
736 {"tfloat", float_cons, 'x'},
737 {"value", cons, 2},
d182319b 738 {"slong", signed_cons, 4},
29b0f896
AM		 739 {"noopt", s_ignore, 0},
740 {"optim", s_ignore, 0},
741 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
742 {"code16", set_code_flag, CODE_16BIT},
743 {"code32", set_code_flag, CODE_32BIT},
744 {"code64", set_code_flag, CODE_64BIT},
745 {"intel_syntax", set_intel_syntax, 1},
746 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 747 {"intel_mnemonic", set_intel_mnemonic, 1},
748 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 749 {"allow_index_reg", set_allow_index_reg, 1},
750 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 751 {"sse_check", set_sse_check, 0},
3b22753a
L		 752#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
753 {"largecomm", handle_large_common, 0},
07a53e5c 754#else
e3bb37b5 755 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 756 {"loc", dwarf2_directive_loc, 0},
757 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 758#endif
6482c264
NC		 759#ifdef TE_PE
760 {"secrel32", pe_directive_secrel, 0},
761#endif
29b0f896
AM		 762 {0, 0, 0}
763};
764
765/* For interface with expression (). */
766extern char *input_line_pointer;
767
768/* Hash table for instruction mnemonic lookup. */
769static struct hash_control *op_hash;
770
771/* Hash table for register lookup. */
772static struct hash_control *reg_hash;
773\f
252b5132 774void
e3bb37b5 775i386_align_code (fragS *fragP, int count)
252b5132 776{
ce8a8b2f
AM		 777 /* Various efficient no-op patterns for aligning code labels.
778 Note: Don't try to assemble the instructions in the comments.
779 0L and 0w are not legal. */
252b5132
RH		 780 static const char f32_1[] =
781 {0x90}; /* nop */
782 static const char f32_2[] =
ccc9c027 783 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 784 static const char f32_3[] =
785 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
786 static const char f32_4[] =
787 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
788 static const char f32_5[] =
789 {0x90, /* nop */
790 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
791 static const char f32_6[] =
792 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
793 static const char f32_7[] =
794 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
795 static const char f32_8[] =
796 {0x90, /* nop */
797 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
798 static const char f32_9[] =
799 {0x89,0xf6, /* movl %esi,%esi */
800 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
801 static const char f32_10[] =
802 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
803 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
804 static const char f32_11[] =
805 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
806 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
807 static const char f32_12[] =
808 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
809 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
810 static const char f32_13[] =
811 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
812 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
813 static const char f32_14[] =
814 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
815 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 816 static const char f16_3[] =
817 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 818 static const char f16_4[] =
819 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
820 static const char f16_5[] =
821 {0x90, /* nop */
822 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
823 static const char f16_6[] =
824 {0x89,0xf6, /* mov %si,%si */
825 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
826 static const char f16_7[] =
827 {0x8d,0x74,0x00, /* lea 0(%si),%si */
828 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
829 static const char f16_8[] =
830 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
831 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 832 static const char jump_31[] =
833 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
834 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
835 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
836 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 837 static const char *const f32_patt[] = {
838 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 839 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 840 };
841 static const char *const f16_patt[] = {
76bc74dc 842 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 843 };
ccc9c027
L		 844 /* nopl (%[re]ax) */
845 static const char alt_3[] =
846 {0x0f,0x1f,0x00};
847 /* nopl 0(%[re]ax) */
848 static const char alt_4[] =
849 {0x0f,0x1f,0x40,0x00};
850 /* nopl 0(%[re]ax,%[re]ax,1) */
851 static const char alt_5[] =
852 {0x0f,0x1f,0x44,0x00,0x00};
853 /* nopw 0(%[re]ax,%[re]ax,1) */
854 static const char alt_6[] =
855 {0x66,0x0f,0x1f,0x44,0x00,0x00};
856 /* nopl 0L(%[re]ax) */
857 static const char alt_7[] =
858 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
859 /* nopl 0L(%[re]ax,%[re]ax,1) */
860 static const char alt_8[] =
861 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
862 /* nopw 0L(%[re]ax,%[re]ax,1) */
863 static const char alt_9[] =
864 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
865 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
866 static const char alt_10[] =
867 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
868 /* data16
869 nopw %cs:0L(%[re]ax,%[re]ax,1) */
870 static const char alt_long_11[] =
871 {0x66,
872 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
873 /* data16
874 data16
875 nopw %cs:0L(%[re]ax,%[re]ax,1) */
876 static const char alt_long_12[] =
877 {0x66,
878 0x66,
879 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
880 /* data16
881 data16
882 data16
883 nopw %cs:0L(%[re]ax,%[re]ax,1) */
884 static const char alt_long_13[] =
885 {0x66,
886 0x66,
887 0x66,
888 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
889 /* data16
890 data16
891 data16
892 data16
893 nopw %cs:0L(%[re]ax,%[re]ax,1) */
894 static const char alt_long_14[] =
895 {0x66,
896 0x66,
897 0x66,
898 0x66,
899 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
900 /* data16
901 data16
902 data16
903 data16
904 data16
905 nopw %cs:0L(%[re]ax,%[re]ax,1) */
906 static const char alt_long_15[] =
907 {0x66,
908 0x66,
909 0x66,
910 0x66,
911 0x66,
912 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
913 /* nopl 0(%[re]ax,%[re]ax,1)
914 nopw 0(%[re]ax,%[re]ax,1) */
915 static const char alt_short_11[] =
916 {0x0f,0x1f,0x44,0x00,0x00,
917 0x66,0x0f,0x1f,0x44,0x00,0x00};
918 /* nopw 0(%[re]ax,%[re]ax,1)
919 nopw 0(%[re]ax,%[re]ax,1) */
920 static const char alt_short_12[] =
921 {0x66,0x0f,0x1f,0x44,0x00,0x00,
922 0x66,0x0f,0x1f,0x44,0x00,0x00};
923 /* nopw 0(%[re]ax,%[re]ax,1)
924 nopl 0L(%[re]ax) */
925 static const char alt_short_13[] =
926 {0x66,0x0f,0x1f,0x44,0x00,0x00,
927 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
928 /* nopl 0L(%[re]ax)
929 nopl 0L(%[re]ax) */
930 static const char alt_short_14[] =
931 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
932 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
933 /* nopl 0L(%[re]ax)
934 nopl 0L(%[re]ax,%[re]ax,1) */
935 static const char alt_short_15[] =
936 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
937 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
938 static const char *const alt_short_patt[] = {
939 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
940 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
941 alt_short_14, alt_short_15
942 };
943 static const char *const alt_long_patt[] = {
944 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
945 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
946 alt_long_14, alt_long_15
947 };
252b5132 948
76bc74dc
L		 949 /* Only align for at least a positive non-zero boundary. */
950 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 951 return;
3e73aa7c 952
ccc9c027
L		 953 /* We need to decide which NOP sequence to use for 32bit and
954 64bit. When -mtune= is used:
4eed87de 955
76bc74dc
L		 956 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
957 PROCESSOR_GENERIC32, f32_patt will be used.
958 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 959 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
960 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 961 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
69dd9865
SP		 962 PROCESSOR_AMDFAM10, and PROCESSOR_AMDFAM15, alt_short_patt
963 will be used.
ccc9c027 964
76bc74dc
L		 965 When -mtune= isn't used, alt_long_patt will be used if
966 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
967 be used.
ccc9c027
L		 968
969 When -march= or .arch is used, we can't use anything beyond
970 cpu_arch_isa_flags. */
971
972 if (flag_code == CODE_16BIT)
973 {
ccc9c027 974 if (count > 8)
33fef721 975 {
76bc74dc
L		 976 memcpy (fragP->fr_literal + fragP->fr_fix,
977 jump_31, count);
978 /* Adjust jump offset. */
979 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 980 }
76bc74dc
L		 981 else
982 memcpy (fragP->fr_literal + fragP->fr_fix,
983 f16_patt[count - 1], count);
252b5132 984 }
33fef721 985 else
ccc9c027
L		 986 {
987 const char *const *patt = NULL;
988
fbf3f584 989 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 990 {
991 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
992 switch (cpu_arch_tune)
993 {
994 case PROCESSOR_UNKNOWN:
995 /* We use cpu_arch_isa_flags to check if we SHOULD
996 optimize for Cpu686. */
fbf3f584 997 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
76bc74dc 998 patt = alt_long_patt;
ccc9c027
L		 999 else
1000 patt = f32_patt;
1001 break;
ccc9c027
L		 1002 case PROCESSOR_PENTIUMPRO:
1003 case PROCESSOR_PENTIUM4:
1004 case PROCESSOR_NOCONA:
ef05d495 1005 case PROCESSOR_CORE:
76bc74dc 1006 case PROCESSOR_CORE2:
bd5295b2 1007 case PROCESSOR_COREI7:
3632d14b 1008 case PROCESSOR_L1OM:
76bc74dc
L		 1009 case PROCESSOR_GENERIC64:
1010 patt = alt_long_patt;
1011 break;
ccc9c027
L		 1012 case PROCESSOR_K6:
1013 case PROCESSOR_ATHLON:
1014 case PROCESSOR_K8:
4eed87de 1015 case PROCESSOR_AMDFAM10:
69dd9865 1016 case PROCESSOR_AMDFAM15:
ccc9c027
L		 1017 patt = alt_short_patt;
1018 break;
76bc74dc 1019 case PROCESSOR_I386:
ccc9c027
L		 1020 case PROCESSOR_I486:
1021 case PROCESSOR_PENTIUM:
1022 case PROCESSOR_GENERIC32:
1023 patt = f32_patt;
1024 break;
4eed87de 1025 }
ccc9c027
L		 1026 }
1027 else
1028 {
fbf3f584 1029 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1030 {
1031 case PROCESSOR_UNKNOWN:
e6a14101 1032 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1033 PROCESSOR_UNKNOWN. */
1034 abort ();
1035 break;
1036
76bc74dc 1037 case PROCESSOR_I386:
ccc9c027
L		 1038 case PROCESSOR_I486:
1039 case PROCESSOR_PENTIUM:
ccc9c027
L		 1040 case PROCESSOR_K6:
1041 case PROCESSOR_ATHLON:
1042 case PROCESSOR_K8:
4eed87de 1043 case PROCESSOR_AMDFAM10:
69dd9865 1044 case PROCESSOR_AMDFAM15:
ccc9c027
L		 1045 case PROCESSOR_GENERIC32:
1046 /* We use cpu_arch_isa_flags to check if we CAN optimize
1047 for Cpu686. */
fbf3f584 1048 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1049 patt = alt_short_patt;
1050 else
1051 patt = f32_patt;
1052 break;
76bc74dc
L		 1053 case PROCESSOR_PENTIUMPRO:
1054 case PROCESSOR_PENTIUM4:
1055 case PROCESSOR_NOCONA:
1056 case PROCESSOR_CORE:
ef05d495 1057 case PROCESSOR_CORE2:
bd5295b2 1058 case PROCESSOR_COREI7:
3632d14b 1059 case PROCESSOR_L1OM:
fbf3f584 1060 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1061 patt = alt_long_patt;
1062 else
1063 patt = f32_patt;
1064 break;
1065 case PROCESSOR_GENERIC64:
76bc74dc 1066 patt = alt_long_patt;
ccc9c027 1067 break;
4eed87de 1068 }
ccc9c027
L		 1069 }
1070
76bc74dc
L		 1071 if (patt == f32_patt)
1072 {
1073 /* If the padding is less than 15 bytes, we use the normal
1074 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1075 its offset. */
1076 int limit;
76ba9986 1077
711eedef
L		 1078 /* For 64bit, the limit is 3 bytes. */
1079 if (flag_code == CODE_64BIT
1080 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1081 limit = 3;
1082 else
1083 limit = 15;
1084 if (count < limit)
76bc74dc
L		 1085 memcpy (fragP->fr_literal + fragP->fr_fix,
1086 patt[count - 1], count);
1087 else
1088 {
1089 memcpy (fragP->fr_literal + fragP->fr_fix,
1090 jump_31, count);
1091 /* Adjust jump offset. */
1092 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1093 }
1094 }
1095 else
1096 {
1097 /* Maximum length of an instruction is 15 byte. If the
1098 padding is greater than 15 bytes and we don't use jump,
1099 we have to break it into smaller pieces. */
1100 int padding = count;
1101 while (padding > 15)
1102 {
1103 padding -= 15;
1104 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1105 patt [14], 15);
1106 }
1107
1108 if (padding)
1109 memcpy (fragP->fr_literal + fragP->fr_fix,
1110 patt [padding - 1], padding);
1111 }
ccc9c027 1112 }
33fef721 1113 fragP->fr_var = count;
252b5132
RH		 1114}
1115
c6fb90c8 1116static INLINE int
0dfbf9d7 1117operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1118{
0dfbf9d7 1119 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1120 {
1121 case 3:
0dfbf9d7 1122 if (x->array[2])
c6fb90c8
L		 1123 return 0;
1124 case 2:
0dfbf9d7 1125 if (x->array[1])
c6fb90c8
L		 1126 return 0;
1127 case 1:
0dfbf9d7 1128 return !x->array[0];
c6fb90c8
L		 1129 default:
1130 abort ();
1131 }
40fb9820
L		 1132}
1133
c6fb90c8 1134static INLINE void
0dfbf9d7 1135operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1136{
0dfbf9d7 1137 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1138 {
1139 case 3:
0dfbf9d7 1140 x->array[2] = v;
c6fb90c8 1141 case 2:
0dfbf9d7 1142 x->array[1] = v;
c6fb90c8 1143 case 1:
0dfbf9d7 1144 x->array[0] = v;
c6fb90c8
L		 1145 break;
1146 default:
1147 abort ();
1148 }
1149}
40fb9820 1150
c6fb90c8 1151static INLINE int
0dfbf9d7
L		 1152operand_type_equal (const union i386_operand_type *x,
1153 const union i386_operand_type *y)
c6fb90c8 1154{
0dfbf9d7 1155 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1156 {
1157 case 3:
0dfbf9d7 1158 if (x->array[2] != y->array[2])
c6fb90c8
L		 1159 return 0;
1160 case 2:
0dfbf9d7 1161 if (x->array[1] != y->array[1])
c6fb90c8
L		 1162 return 0;
1163 case 1:
0dfbf9d7 1164 return x->array[0] == y->array[0];
c6fb90c8
L		 1165 break;
1166 default:
1167 abort ();
1168 }
1169}
40fb9820 1170
0dfbf9d7
L		 1171static INLINE int
1172cpu_flags_all_zero (const union i386_cpu_flags *x)
1173{
1174 switch (ARRAY_SIZE(x->array))
1175 {
1176 case 3:
1177 if (x->array[2])
1178 return 0;
1179 case 2:
1180 if (x->array[1])
1181 return 0;
1182 case 1:
1183 return !x->array[0];
1184 default:
1185 abort ();
1186 }
1187}
1188
1189static INLINE void
1190cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1191{
1192 switch (ARRAY_SIZE(x->array))
1193 {
1194 case 3:
1195 x->array[2] = v;
1196 case 2:
1197 x->array[1] = v;
1198 case 1:
1199 x->array[0] = v;
1200 break;
1201 default:
1202 abort ();
1203 }
1204}
1205
1206static INLINE int
1207cpu_flags_equal (const union i386_cpu_flags *x,
1208 const union i386_cpu_flags *y)
1209{
1210 switch (ARRAY_SIZE(x->array))
1211 {
1212 case 3:
1213 if (x->array[2] != y->array[2])
1214 return 0;
1215 case 2:
1216 if (x->array[1] != y->array[1])
1217 return 0;
1218 case 1:
1219 return x->array[0] == y->array[0];
1220 break;
1221 default:
1222 abort ();
1223 }
1224}
c6fb90c8
L		 1225
1226static INLINE int
1227cpu_flags_check_cpu64 (i386_cpu_flags f)
1228{
1229 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1230 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1231}
1232
c6fb90c8
L		 1233static INLINE i386_cpu_flags
1234cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1235{
c6fb90c8
L		 1236 switch (ARRAY_SIZE (x.array))
1237 {
1238 case 3:
1239 x.array [2] &= y.array [2];
1240 case 2:
1241 x.array [1] &= y.array [1];
1242 case 1:
1243 x.array [0] &= y.array [0];
1244 break;
1245 default:
1246 abort ();
1247 }
1248 return x;
1249}
40fb9820 1250
c6fb90c8
L		 1251static INLINE i386_cpu_flags
1252cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1253{
c6fb90c8 1254 switch (ARRAY_SIZE (x.array))
40fb9820 1255 {
c6fb90c8
L		 1256 case 3:
1257 x.array [2] |= y.array [2];
1258 case 2:
1259 x.array [1] |= y.array [1];
1260 case 1:
1261 x.array [0] |= y.array [0];
40fb9820
L		 1262 break;
1263 default:
1264 abort ();
1265 }
40fb9820
L		 1266 return x;
1267}
1268
309d3373
JB		 1269static INLINE i386_cpu_flags
1270cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1271{
1272 switch (ARRAY_SIZE (x.array))
1273 {
1274 case 3:
1275 x.array [2] &= ~y.array [2];
1276 case 2:
1277 x.array [1] &= ~y.array [1];
1278 case 1:
1279 x.array [0] &= ~y.array [0];
1280 break;
1281 default:
1282 abort ();
1283 }
1284 return x;
1285}
1286
c0f3af97
L		 1287#define CPU_FLAGS_ARCH_MATCH 0x1
1288#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1289#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1290#define CPU_FLAGS_PCLMUL_MATCH 0x8
1291#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1292
a5ff0eb2 1293#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1294 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1295 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1296#define CPU_FLAGS_PERFECT_MATCH \
1297 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1298
1299/* Return CPU flags match bits. */
3629bb00 1300
40fb9820 1301static int
d3ce72d0 1302cpu_flags_match (const insn_template *t)
40fb9820 1303{
c0f3af97
L		 1304 i386_cpu_flags x = t->cpu_flags;
1305 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1306
1307 x.bitfield.cpu64 = 0;
1308 x.bitfield.cpuno64 = 0;
1309
0dfbf9d7 1310 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1311 {
1312 /* This instruction is available on all archs. */
1313 match |= CPU_FLAGS_32BIT_MATCH;
1314 }
3629bb00
L		 1315 else
1316 {
c0f3af97 1317 /* This instruction is available only on some archs. */
3629bb00
L		 1318 i386_cpu_flags cpu = cpu_arch_flags;
1319
1320 cpu.bitfield.cpu64 = 0;
1321 cpu.bitfield.cpuno64 = 0;
1322 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1323 if (!cpu_flags_all_zero (&cpu))
1324 {
a5ff0eb2
L		 1325 if (x.bitfield.cpuavx)
1326 {
ce2f5b3c 1327 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1328 if (cpu.bitfield.cpuavx)
1329 {
1330 /* Check SSE2AVX. */
1331 if (!t->opcode_modifier.sse2avx|| sse2avx)
1332 {
1333 match |= (CPU_FLAGS_ARCH_MATCH
1334 | CPU_FLAGS_AVX_MATCH);
1335 /* Check AES. */
1336 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1337 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1338 /* Check PCLMUL. */
1339 if (!x.bitfield.cpupclmul
1340 || cpu.bitfield.cpupclmul)
1341 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1342 }
1343 }
1344 else
1345 match |= CPU_FLAGS_ARCH_MATCH;
1346 }
1347 else
c0f3af97
L		 1348 match |= CPU_FLAGS_32BIT_MATCH;
1349 }
3629bb00 1350 }
c0f3af97 1351 return match;
40fb9820
L		 1352}
1353
c6fb90c8
L		 1354static INLINE i386_operand_type
1355operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1356{
c6fb90c8
L		 1357 switch (ARRAY_SIZE (x.array))
1358 {
1359 case 3:
1360 x.array [2] &= y.array [2];
1361 case 2:
1362 x.array [1] &= y.array [1];
1363 case 1:
1364 x.array [0] &= y.array [0];
1365 break;
1366 default:
1367 abort ();
1368 }
1369 return x;
40fb9820
L		 1370}
1371
c6fb90c8
L		 1372static INLINE i386_operand_type
1373operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1374{
c6fb90c8 1375 switch (ARRAY_SIZE (x.array))
40fb9820 1376 {
c6fb90c8
L		 1377 case 3:
1378 x.array [2] |= y.array [2];
1379 case 2:
1380 x.array [1] |= y.array [1];
1381 case 1:
1382 x.array [0] |= y.array [0];
40fb9820
L		 1383 break;
1384 default:
1385 abort ();
1386 }
c6fb90c8
L		 1387 return x;
1388}
40fb9820 1389
c6fb90c8
L		 1390static INLINE i386_operand_type
1391operand_type_xor (i386_operand_type x, i386_operand_type y)
1392{
1393 switch (ARRAY_SIZE (x.array))
1394 {
1395 case 3:
1396 x.array [2] ^= y.array [2];
1397 case 2:
1398 x.array [1] ^= y.array [1];
1399 case 1:
1400 x.array [0] ^= y.array [0];
1401 break;
1402 default:
1403 abort ();
1404 }
40fb9820
L		 1405 return x;
1406}
1407
1408static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1409static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1410static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1411static const i386_operand_type inoutportreg
1412 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1413static const i386_operand_type reg16_inoutportreg
1414 = OPERAND_TYPE_REG16_INOUTPORTREG;
1415static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1416static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1417static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1418static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1419static const i386_operand_type anydisp
1420 = OPERAND_TYPE_ANYDISP;
40fb9820 1421static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1422static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1423static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1424static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1425static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1426static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1427static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1428static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1429static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1430static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1431static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1432
1433enum operand_type
1434{
1435 reg,
40fb9820
L		 1436 imm,
1437 disp,
1438 anymem
1439};
1440
c6fb90c8 1441static INLINE int
40fb9820
L		 1442operand_type_check (i386_operand_type t, enum operand_type c)
1443{
1444 switch (c)
1445 {
1446 case reg:
1447 return (t.bitfield.reg8
1448 || t.bitfield.reg16
1449 || t.bitfield.reg32
1450 || t.bitfield.reg64);
1451
40fb9820
L		 1452 case imm:
1453 return (t.bitfield.imm8
1454 || t.bitfield.imm8s
1455 || t.bitfield.imm16
1456 || t.bitfield.imm32
1457 || t.bitfield.imm32s
1458 || t.bitfield.imm64);
1459
1460 case disp:
1461 return (t.bitfield.disp8
1462 || t.bitfield.disp16
1463 || t.bitfield.disp32
1464 || t.bitfield.disp32s
1465 || t.bitfield.disp64);
1466
1467 case anymem:
1468 return (t.bitfield.disp8
1469 || t.bitfield.disp16
1470 || t.bitfield.disp32
1471 || t.bitfield.disp32s
1472 || t.bitfield.disp64
1473 || t.bitfield.baseindex);
1474
1475 default:
1476 abort ();
1477 }
2cfe26b6
AM		 1478
1479 return 0;
40fb9820
L		 1480}
1481
5c07affc
L		 1482/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1483 operand J for instruction template T. */
1484
1485static INLINE int
d3ce72d0 1486match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1487{
1488 return !((i.types[j].bitfield.byte
1489 && !t->operand_types[j].bitfield.byte)
1490 || (i.types[j].bitfield.word
1491 && !t->operand_types[j].bitfield.word)
1492 || (i.types[j].bitfield.dword
1493 && !t->operand_types[j].bitfield.dword)
1494 || (i.types[j].bitfield.qword
1495 && !t->operand_types[j].bitfield.qword));
1496}
1497
1498/* Return 1 if there is no conflict in any size on operand J for
1499 instruction template T. */
1500
1501static INLINE int
d3ce72d0 1502match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1503{
1504 return (match_reg_size (t, j)
1505 && !((i.types[j].bitfield.unspecified
1506 && !t->operand_types[j].bitfield.unspecified)
1507 || (i.types[j].bitfield.fword
1508 && !t->operand_types[j].bitfield.fword)
1509 || (i.types[j].bitfield.tbyte
1510 && !t->operand_types[j].bitfield.tbyte)
1511 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1512 && !t->operand_types[j].bitfield.xmmword)
1513 || (i.types[j].bitfield.ymmword
1514 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1515}
1516
1517/* Return 1 if there is no size conflict on any operands for
1518 instruction template T. */
1519
1520static INLINE int
d3ce72d0 1521operand_size_match (const insn_template *t)
5c07affc
L		 1522{
1523 unsigned int j;
1524 int match = 1;
1525
1526 /* Don't check jump instructions. */
1527 if (t->opcode_modifier.jump
1528 || t->opcode_modifier.jumpbyte
1529 || t->opcode_modifier.jumpdword
1530 || t->opcode_modifier.jumpintersegment)
1531 return match;
1532
1533 /* Check memory and accumulator operand size. */
1534 for (j = 0; j < i.operands; j++)
1535 {
1536 if (t->operand_types[j].bitfield.anysize)
1537 continue;
1538
1539 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1540 {
1541 match = 0;
1542 break;
1543 }
1544
1545 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1546 {
1547 match = 0;
1548 break;
1549 }
1550 }
1551
1552 if (match
1553 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1554 return match;
1555
1556 /* Check reverse. */
9c2799c2 1557 gas_assert (i.operands == 2);
5c07affc
L		 1558
1559 match = 1;
1560 for (j = 0; j < 2; j++)
1561 {
1562 if (t->operand_types[j].bitfield.acc
1563 && !match_reg_size (t, j ? 0 : 1))
1564 {
1565 match = 0;
1566 break;
1567 }
1568
1569 if (i.types[j].bitfield.mem
1570 && !match_mem_size (t, j ? 0 : 1))
1571 {
1572 match = 0;
1573 break;
1574 }
1575 }
1576
1577 return match;
1578}
1579
c6fb90c8 1580static INLINE int
40fb9820
L		 1581operand_type_match (i386_operand_type overlap,
1582 i386_operand_type given)
1583{
1584 i386_operand_type temp = overlap;
1585
1586 temp.bitfield.jumpabsolute = 0;
7d5e4556 1587 temp.bitfield.unspecified = 0;
5c07affc
L		 1588 temp.bitfield.byte = 0;
1589 temp.bitfield.word = 0;
1590 temp.bitfield.dword = 0;
1591 temp.bitfield.fword = 0;
1592 temp.bitfield.qword = 0;
1593 temp.bitfield.tbyte = 0;
1594 temp.bitfield.xmmword = 0;
c0f3af97 1595 temp.bitfield.ymmword = 0;
0dfbf9d7 1596 if (operand_type_all_zero (&temp))
40fb9820
L		 1597 return 0;
1598
1599 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1600 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1601}
1602
7d5e4556 1603/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1604 unless the expected operand type register overlap is null.
1605 Note that Acc in a template matches every size of reg. */
1606
c6fb90c8 1607static INLINE int
40fb9820
L		 1608operand_type_register_match (i386_operand_type m0,
1609 i386_operand_type g0,
1610 i386_operand_type t0,
1611 i386_operand_type m1,
1612 i386_operand_type g1,
1613 i386_operand_type t1)
1614{
1615 if (!operand_type_check (g0, reg))
1616 return 1;
1617
1618 if (!operand_type_check (g1, reg))
1619 return 1;
1620
1621 if (g0.bitfield.reg8 == g1.bitfield.reg8
1622 && g0.bitfield.reg16 == g1.bitfield.reg16
1623 && g0.bitfield.reg32 == g1.bitfield.reg32
1624 && g0.bitfield.reg64 == g1.bitfield.reg64)
1625 return 1;
1626
1627 if (m0.bitfield.acc)
1628 {
1629 t0.bitfield.reg8 = 1;
1630 t0.bitfield.reg16 = 1;
1631 t0.bitfield.reg32 = 1;
1632 t0.bitfield.reg64 = 1;
1633 }
1634
1635 if (m1.bitfield.acc)
1636 {
1637 t1.bitfield.reg8 = 1;
1638 t1.bitfield.reg16 = 1;
1639 t1.bitfield.reg32 = 1;
1640 t1.bitfield.reg64 = 1;
1641 }
1642
1643 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1644 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1645 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1646 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1647}
1648
252b5132 1649static INLINE unsigned int
40fb9820 1650mode_from_disp_size (i386_operand_type t)
252b5132 1651{
40fb9820
L		 1652 if (t.bitfield.disp8)
1653 return 1;
1654 else if (t.bitfield.disp16
1655 || t.bitfield.disp32
1656 || t.bitfield.disp32s)
1657 return 2;
1658 else
1659 return 0;
252b5132
RH		 1660}
1661
1662static INLINE int
e3bb37b5 1663fits_in_signed_byte (offsetT num)
252b5132
RH		 1664{
1665 return (num >= -128) && (num <= 127);
47926f60 1666}
252b5132
RH		 1667
1668static INLINE int
e3bb37b5 1669fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1670{
1671 return (num & 0xff) == num;
47926f60 1672}
252b5132
RH		 1673
1674static INLINE int
e3bb37b5 1675fits_in_unsigned_word (offsetT num)
252b5132
RH		 1676{
1677 return (num & 0xffff) == num;
47926f60 1678}
252b5132
RH		 1679
1680static INLINE int
e3bb37b5 1681fits_in_signed_word (offsetT num)
252b5132
RH		 1682{
1683 return (-32768 <= num) && (num <= 32767);
47926f60 1684}
2a962e6d 1685
3e73aa7c 1686static INLINE int
e3bb37b5 1687fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1688{
1689#ifndef BFD64
1690 return 1;
1691#else
1692 return (!(((offsetT) -1 << 31) & num)
1693 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1694#endif
1695} /* fits_in_signed_long() */
2a962e6d 1696
3e73aa7c 1697static INLINE int
e3bb37b5 1698fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1699{
1700#ifndef BFD64
1701 return 1;
1702#else
1703 return (num & (((offsetT) 2 << 31) - 1)) == num;
1704#endif
1705} /* fits_in_unsigned_long() */
252b5132 1706
40fb9820 1707static i386_operand_type
e3bb37b5 1708smallest_imm_type (offsetT num)
252b5132 1709{
40fb9820 1710 i386_operand_type t;
7ab9ffdd 1711
0dfbf9d7 1712 operand_type_set (&t, 0);
40fb9820
L		 1713 t.bitfield.imm64 = 1;
1714
1715 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1716 {
1717 /* This code is disabled on the 486 because all the Imm1 forms
1718 in the opcode table are slower on the i486. They're the
1719 versions with the implicitly specified single-position
1720 displacement, which has another syntax if you really want to
1721 use that form. */
40fb9820
L		 1722 t.bitfield.imm1 = 1;
1723 t.bitfield.imm8 = 1;
1724 t.bitfield.imm8s = 1;
1725 t.bitfield.imm16 = 1;
1726 t.bitfield.imm32 = 1;
1727 t.bitfield.imm32s = 1;
1728 }
1729 else if (fits_in_signed_byte (num))
1730 {
1731 t.bitfield.imm8 = 1;
1732 t.bitfield.imm8s = 1;
1733 t.bitfield.imm16 = 1;
1734 t.bitfield.imm32 = 1;
1735 t.bitfield.imm32s = 1;
1736 }
1737 else if (fits_in_unsigned_byte (num))
1738 {
1739 t.bitfield.imm8 = 1;
1740 t.bitfield.imm16 = 1;
1741 t.bitfield.imm32 = 1;
1742 t.bitfield.imm32s = 1;
1743 }
1744 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1745 {
1746 t.bitfield.imm16 = 1;
1747 t.bitfield.imm32 = 1;
1748 t.bitfield.imm32s = 1;
1749 }
1750 else if (fits_in_signed_long (num))
1751 {
1752 t.bitfield.imm32 = 1;
1753 t.bitfield.imm32s = 1;
1754 }
1755 else if (fits_in_unsigned_long (num))
1756 t.bitfield.imm32 = 1;
1757
1758 return t;
47926f60 1759}
252b5132 1760
847f7ad4 1761static offsetT
e3bb37b5 1762offset_in_range (offsetT val, int size)
847f7ad4 1763{
508866be 1764 addressT mask;
ba2adb93 1765
847f7ad4
AM		 1766 switch (size)
1767 {
508866be
L		 1768 case 1: mask = ((addressT) 1 << 8) - 1; break;
1769 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1770 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1771#ifdef BFD64
1772 case 8: mask = ((addressT) 2 << 63) - 1; break;
1773#endif
47926f60 1774 default: abort ();
847f7ad4
AM		 1775 }
1776
9de868bf
L		 1777#ifdef BFD64
1778 /* If BFD64, sign extend val for 32bit address mode. */
1779 if (flag_code != CODE_64BIT
1780 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1781 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1782 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1783#endif
ba2adb93 1784
47926f60 1785 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1786 {
1787 char buf1[40], buf2[40];
1788
1789 sprint_value (buf1, val);
1790 sprint_value (buf2, val & mask);
1791 as_warn (_("%s shortened to %s"), buf1, buf2);
1792 }
1793 return val & mask;
1794}
1795
c32fa91d
L		 1796enum PREFIX_GROUP
1797{
1798 PREFIX_EXIST = 0,
1799 PREFIX_LOCK,
1800 PREFIX_REP,
1801 PREFIX_OTHER
1802};
1803
1804/* Returns
1805 a. PREFIX_EXIST if attempting to add a prefix where one from the
1806 same class already exists.
1807 b. PREFIX_LOCK if lock prefix is added.
1808 c. PREFIX_REP if rep/repne prefix is added.
1809 d. PREFIX_OTHER if other prefix is added.
1810 */
1811
1812static enum PREFIX_GROUP
e3bb37b5 1813add_prefix (unsigned int prefix)
252b5132 1814{
c32fa91d 1815 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1816 unsigned int q;
252b5132 1817
29b0f896
AM		 1818 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1819 && flag_code == CODE_64BIT)
b1905489 1820 {
161a04f6
L		 1821 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1822 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1823 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1824 ret = PREFIX_EXIST;
b1905489
JB		 1825 q = REX_PREFIX;
1826 }
3e73aa7c 1827 else
b1905489
JB		 1828 {
1829 switch (prefix)
1830 {
1831 default:
1832 abort ();
1833
1834 case CS_PREFIX_OPCODE:
1835 case DS_PREFIX_OPCODE:
1836 case ES_PREFIX_OPCODE:
1837 case FS_PREFIX_OPCODE:
1838 case GS_PREFIX_OPCODE:
1839 case SS_PREFIX_OPCODE:
1840 q = SEG_PREFIX;
1841 break;
1842
1843 case REPNE_PREFIX_OPCODE:
1844 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1845 q = REP_PREFIX;
1846 ret = PREFIX_REP;
1847 break;
1848
b1905489 1849 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1850 q = LOCK_PREFIX;
1851 ret = PREFIX_LOCK;
b1905489
JB		 1852 break;
1853
1854 case FWAIT_OPCODE:
1855 q = WAIT_PREFIX;
1856 break;
1857
1858 case ADDR_PREFIX_OPCODE:
1859 q = ADDR_PREFIX;
1860 break;
1861
1862 case DATA_PREFIX_OPCODE:
1863 q = DATA_PREFIX;
1864 break;
1865 }
1866 if (i.prefix[q] != 0)
c32fa91d 1867 ret = PREFIX_EXIST;
b1905489 1868 }
252b5132 1869
b1905489 1870 if (ret)
252b5132 1871 {
b1905489
JB		 1872 if (!i.prefix[q])
1873 ++i.prefixes;
1874 i.prefix[q] |= prefix;
252b5132 1875 }
b1905489
JB		 1876 else
1877 as_bad (_("same type of prefix used twice"));
252b5132 1878
252b5132
RH		 1879 return ret;
1880}
1881
1882static void
e3bb37b5 1883set_code_flag (int value)
eecb386c 1884{
1e9cc1c2 1885 flag_code = (enum flag_code) value;
40fb9820
L		 1886 if (flag_code == CODE_64BIT)
1887 {
1888 cpu_arch_flags.bitfield.cpu64 = 1;
1889 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1890 }
1891 else
1892 {
1893 cpu_arch_flags.bitfield.cpu64 = 0;
1894 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1895 }
1896 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1897 {
1898 as_bad (_("64bit mode not supported on this CPU."));
1899 }
40fb9820 1900 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1901 {
1902 as_bad (_("32bit mode not supported on this CPU."));
1903 }
eecb386c
AM		 1904 stackop_size = '\0';
1905}
1906
1907static void
e3bb37b5 1908set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1909{
1e9cc1c2 1910 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 1911 if (flag_code != CODE_16BIT)
1912 abort ();
1913 cpu_arch_flags.bitfield.cpu64 = 0;
1914 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1915 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1916}
1917
1918static void
e3bb37b5 1919set_intel_syntax (int syntax_flag)
252b5132
RH		 1920{
1921 /* Find out if register prefixing is specified. */
1922 int ask_naked_reg = 0;
1923
1924 SKIP_WHITESPACE ();
29b0f896 1925 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1926 {
1927 char *string = input_line_pointer;
1928 int e = get_symbol_end ();
1929
47926f60 1930 if (strcmp (string, "prefix") == 0)
252b5132 1931 ask_naked_reg = 1;
47926f60 1932 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1933 ask_naked_reg = -1;
1934 else
d0b47220 1935 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1936 *input_line_pointer = e;
1937 }
1938 demand_empty_rest_of_line ();
c3332e24 1939
252b5132
RH		 1940 intel_syntax = syntax_flag;
1941
1942 if (ask_naked_reg == 0)
f86103b7
AM		 1943 allow_naked_reg = (intel_syntax
1944 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1945 else
1946 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1947
ee86248c 1948 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 1949
e4a3b5a4 1950 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1951 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1952 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1953}
1954
1efbbeb4
L		 1955static void
1956set_intel_mnemonic (int mnemonic_flag)
1957{
e1d4d893 1958 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1959}
1960
db51cc60
L		 1961static void
1962set_allow_index_reg (int flag)
1963{
1964 allow_index_reg = flag;
1965}
1966
cb19c032
L		 1967static void
1968set_sse_check (int dummy ATTRIBUTE_UNUSED)
1969{
1970 SKIP_WHITESPACE ();
1971
1972 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1973 {
1974 char *string = input_line_pointer;
1975 int e = get_symbol_end ();
1976
1977 if (strcmp (string, "none") == 0)
1978 sse_check = sse_check_none;
1979 else if (strcmp (string, "warning") == 0)
1980 sse_check = sse_check_warning;
1981 else if (strcmp (string, "error") == 0)
1982 sse_check = sse_check_error;
1983 else
1984 as_bad (_("bad argument to sse_check directive."));
1985 *input_line_pointer = e;
1986 }
1987 else
1988 as_bad (_("missing argument for sse_check directive"));
1989
1990 demand_empty_rest_of_line ();
1991}
1992
8a9036a4
L		 1993static void
1994check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 1995 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 1996{
1997#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1998 static const char *arch;
1999
2000 /* Intel LIOM is only supported on ELF. */
2001 if (!IS_ELF)
2002 return;
2003
2004 if (!arch)
2005 {
2006 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2007 use default_arch. */
2008 arch = cpu_arch_name;
2009 if (!arch)
2010 arch = default_arch;
2011 }
2012
3632d14b 2013 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2014 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2015 || new_flag.bitfield.cpul1om)
8a9036a4 2016 return;
76ba9986 2017
8a9036a4
L		 2018 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2019#endif
2020}
2021
e413e4e9 2022static void
e3bb37b5 2023set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2024{
47926f60 2025 SKIP_WHITESPACE ();
e413e4e9 2026
29b0f896 2027 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2028 {
2029 char *string = input_line_pointer;
2030 int e = get_symbol_end ();
91d6fa6a 2031 unsigned int j;
40fb9820 2032 i386_cpu_flags flags;
e413e4e9 2033
91d6fa6a 2034 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2035 {
91d6fa6a 2036 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2037 {
91d6fa6a 2038 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2039
5c6af06e
JB		 2040 if (*string != '.')
2041 {
91d6fa6a 2042 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2043 cpu_sub_arch_name = NULL;
91d6fa6a 2044 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2045 if (flag_code == CODE_64BIT)
2046 {
2047 cpu_arch_flags.bitfield.cpu64 = 1;
2048 cpu_arch_flags.bitfield.cpuno64 = 0;
2049 }
2050 else
2051 {
2052 cpu_arch_flags.bitfield.cpu64 = 0;
2053 cpu_arch_flags.bitfield.cpuno64 = 1;
2054 }
91d6fa6a
NC		 2055 cpu_arch_isa = cpu_arch[j].type;
2056 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2057 if (!cpu_arch_tune_set)
2058 {
2059 cpu_arch_tune = cpu_arch_isa;
2060 cpu_arch_tune_flags = cpu_arch_isa_flags;
2061 }
5c6af06e
JB		 2062 break;
2063 }
40fb9820 2064
309d3373
JB		 2065 if (strncmp (string + 1, "no", 2))
2066 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2067 cpu_arch[j].flags);
309d3373
JB		 2068 else
2069 flags = cpu_flags_and_not (cpu_arch_flags,
91d6fa6a 2070 cpu_arch[j].flags);
0dfbf9d7 2071 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2072 {
6305a203
L		 2073 if (cpu_sub_arch_name)
2074 {
2075 char *name = cpu_sub_arch_name;
2076 cpu_sub_arch_name = concat (name,
91d6fa6a 2077 cpu_arch[j].name,
1bf57e9f 2078 (const char *) NULL);
6305a203
L		 2079 free (name);
2080 }
2081 else
91d6fa6a 2082 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2083 cpu_arch_flags = flags;
5c6af06e
JB		 2084 }
2085 *input_line_pointer = e;
2086 demand_empty_rest_of_line ();
2087 return;
e413e4e9
AM		 2088 }
2089 }
91d6fa6a 2090 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2091 as_bad (_("no such architecture: `%s'"), string);
2092
2093 *input_line_pointer = e;
2094 }
2095 else
2096 as_bad (_("missing cpu architecture"));
2097
fddf5b5b
AM		 2098 no_cond_jump_promotion = 0;
2099 if (*input_line_pointer == ','
29b0f896 2100 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2101 {
2102 char *string = ++input_line_pointer;
2103 int e = get_symbol_end ();
2104
2105 if (strcmp (string, "nojumps") == 0)
2106 no_cond_jump_promotion = 1;
2107 else if (strcmp (string, "jumps") == 0)
2108 ;
2109 else
2110 as_bad (_("no such architecture modifier: `%s'"), string);
2111
2112 *input_line_pointer = e;
2113 }
2114
e413e4e9
AM		 2115 demand_empty_rest_of_line ();
2116}
2117
8a9036a4
L		 2118enum bfd_architecture
2119i386_arch (void)
2120{
3632d14b 2121 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2122 {
2123 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2124 || flag_code != CODE_64BIT)
2125 as_fatal (_("Intel L1OM is 64bit ELF only"));
2126 return bfd_arch_l1om;
2127 }
2128 else
2129 return bfd_arch_i386;
2130}
2131
b9d79e03
JH		 2132unsigned long
2133i386_mach ()
2134{
2135 if (!strcmp (default_arch, "x86_64"))
8a9036a4 2136 {
3632d14b 2137 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2138 {
2139 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2140 as_fatal (_("Intel L1OM is 64bit ELF only"));
2141 return bfd_mach_l1om;
2142 }
2143 else
2144 return bfd_mach_x86_64;
2145 }
b9d79e03
JH		 2146 else if (!strcmp (default_arch, "i386"))
2147 return bfd_mach_i386_i386;
2148 else
2149 as_fatal (_("Unknown architecture"));
2150}
b9d79e03 2151\f
252b5132
RH		 2152void
2153md_begin ()
2154{
2155 const char *hash_err;
2156
47926f60 2157 /* Initialize op_hash hash table. */
252b5132
RH		 2158 op_hash = hash_new ();
2159
2160 {
d3ce72d0 2161 const insn_template *optab;
29b0f896 2162 templates *core_optab;
252b5132 2163
47926f60
KH		 2164 /* Setup for loop. */
2165 optab = i386_optab;
252b5132
RH		 2166 core_optab = (templates *) xmalloc (sizeof (templates));
2167 core_optab->start = optab;
2168
2169 while (1)
2170 {
2171 ++optab;
2172 if (optab->name == NULL
2173 || strcmp (optab->name, (optab - 1)->name) != 0)
2174 {
2175 /* different name --> ship out current template list;
47926f60 2176 add to hash table; & begin anew. */
252b5132
RH		 2177 core_optab->end = optab;
2178 hash_err = hash_insert (op_hash,
2179 (optab - 1)->name,
5a49b8ac 2180 (void *) core_optab);
252b5132
RH		 2181 if (hash_err)
2182 {
252b5132
RH		 2183 as_fatal (_("Internal Error: Can't hash %s: %s"),
2184 (optab - 1)->name,
2185 hash_err);
2186 }
2187 if (optab->name == NULL)
2188 break;
2189 core_optab = (templates *) xmalloc (sizeof (templates));
2190 core_optab->start = optab;
2191 }
2192 }
2193 }
2194
47926f60 2195 /* Initialize reg_hash hash table. */
252b5132
RH		 2196 reg_hash = hash_new ();
2197 {
29b0f896 2198 const reg_entry *regtab;
c3fe08fa 2199 unsigned int regtab_size = i386_regtab_size;
252b5132 2200
c3fe08fa 2201 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2202 {
5a49b8ac 2203 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2204 if (hash_err)
3e73aa7c
JH		 2205 as_fatal (_("Internal Error: Can't hash %s: %s"),
2206 regtab->reg_name,
2207 hash_err);
252b5132
RH		 2208 }
2209 }
2210
47926f60 2211 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2212 {
29b0f896
AM		 2213 int c;
2214 char *p;
252b5132
RH		 2215
2216 for (c = 0; c < 256; c++)
2217 {
3882b010 2218 if (ISDIGIT (c))
252b5132
RH		 2219 {
2220 digit_chars[c] = c;
2221 mnemonic_chars[c] = c;
2222 register_chars[c] = c;
2223 operand_chars[c] = c;
2224 }
3882b010 2225 else if (ISLOWER (c))
252b5132
RH		 2226 {
2227 mnemonic_chars[c] = c;
2228 register_chars[c] = c;
2229 operand_chars[c] = c;
2230 }
3882b010 2231 else if (ISUPPER (c))
252b5132 2232 {
3882b010 2233 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2234 register_chars[c] = mnemonic_chars[c];
2235 operand_chars[c] = c;
2236 }
2237
3882b010 2238 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2239 identifier_chars[c] = c;
2240 else if (c >= 128)
2241 {
2242 identifier_chars[c] = c;
2243 operand_chars[c] = c;
2244 }
2245 }
2246
2247#ifdef LEX_AT
2248 identifier_chars['@'] = '@';
32137342
NC		 2249#endif
2250#ifdef LEX_QM
2251 identifier_chars['?'] = '?';
2252 operand_chars['?'] = '?';
252b5132 2253#endif
252b5132 2254 digit_chars['-'] = '-';
c0f3af97 2255 mnemonic_chars['_'] = '_';
791fe849 2256 mnemonic_chars['-'] = '-';
0003779b 2257 mnemonic_chars['.'] = '.';
252b5132
RH		 2258 identifier_chars['_'] = '_';
2259 identifier_chars['.'] = '.';
2260
2261 for (p = operand_special_chars; *p != '\0'; p++)
2262 operand_chars[(unsigned char) *p] = *p;
2263 }
2264
2265#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2266 if (IS_ELF)
252b5132
RH		 2267 {
2268 record_alignment (text_section, 2);
2269 record_alignment (data_section, 2);
2270 record_alignment (bss_section, 2);
2271 }
2272#endif
a4447b93
RH		 2273
2274 if (flag_code == CODE_64BIT)
2275 {
2276 x86_dwarf2_return_column = 16;
2277 x86_cie_data_alignment = -8;
2278 }
2279 else
2280 {
2281 x86_dwarf2_return_column = 8;
2282 x86_cie_data_alignment = -4;
2283 }
252b5132
RH		 2284}
2285
2286void
e3bb37b5 2287i386_print_statistics (FILE *file)
252b5132
RH		 2288{
2289 hash_print_statistics (file, "i386 opcode", op_hash);
2290 hash_print_statistics (file, "i386 register", reg_hash);
2291}
2292\f
252b5132
RH		 2293#ifdef DEBUG386
2294
ce8a8b2f 2295/* Debugging routines for md_assemble. */
d3ce72d0 2296static void pte (insn_template *);
40fb9820 2297static void pt (i386_operand_type);
e3bb37b5
L		 2298static void pe (expressionS *);
2299static void ps (symbolS *);
252b5132
RH		 2300
2301static void
e3bb37b5 2302pi (char *line, i386_insn *x)
252b5132 2303{
09f131f2 2304 unsigned int i;
252b5132
RH		 2305
2306 fprintf (stdout, "%s: template ", line);
2307 pte (&x->tm);
09f131f2
JH		 2308 fprintf (stdout, " address: base %s index %s scale %x\n",
2309 x->base_reg ? x->base_reg->reg_name : "none",
2310 x->index_reg ? x->index_reg->reg_name : "none",
2311 x->log2_scale_factor);
2312 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2313 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2314 fprintf (stdout, " sib: base %x index %x scale %x\n",
2315 x->sib.base, x->sib.index, x->sib.scale);
2316 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2317 (x->rex & REX_W) != 0,
2318 (x->rex & REX_R) != 0,
2319 (x->rex & REX_X) != 0,
2320 (x->rex & REX_B) != 0);
252b5132
RH		 2321 for (i = 0; i < x->operands; i++)
2322 {
2323 fprintf (stdout, " #%d: ", i + 1);
2324 pt (x->types[i]);
2325 fprintf (stdout, "\n");
40fb9820
L		 2326 if (x->types[i].bitfield.reg8
2327 || x->types[i].bitfield.reg16
2328 || x->types[i].bitfield.reg32
2329 || x->types[i].bitfield.reg64
2330 || x->types[i].bitfield.regmmx
2331 || x->types[i].bitfield.regxmm
c0f3af97 2332 || x->types[i].bitfield.regymm
40fb9820
L		 2333 || x->types[i].bitfield.sreg2
2334 || x->types[i].bitfield.sreg3
2335 || x->types[i].bitfield.control
2336 || x->types[i].bitfield.debug
2337 || x->types[i].bitfield.test)
520dc8e8 2338 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2339 if (operand_type_check (x->types[i], imm))
520dc8e8 2340 pe (x->op[i].imms);
40fb9820 2341 if (operand_type_check (x->types[i], disp))
520dc8e8 2342 pe (x->op[i].disps);
252b5132
RH		 2343 }
2344}
2345
2346static void
d3ce72d0 2347pte (insn_template *t)
252b5132 2348{
09f131f2 2349 unsigned int i;
252b5132 2350 fprintf (stdout, " %d operands ", t->operands);
47926f60 2351 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2352 if (t->extension_opcode != None)
2353 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2354 if (t->opcode_modifier.d)
252b5132 2355 fprintf (stdout, "D");
40fb9820 2356 if (t->opcode_modifier.w)
252b5132
RH		 2357 fprintf (stdout, "W");
2358 fprintf (stdout, "\n");
2359 for (i = 0; i < t->operands; i++)
2360 {
2361 fprintf (stdout, " #%d type ", i + 1);
2362 pt (t->operand_types[i]);
2363 fprintf (stdout, "\n");
2364 }
2365}
2366
2367static void
e3bb37b5 2368pe (expressionS *e)
252b5132 2369{
24eab124 2370 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2371 fprintf (stdout, " add_number %ld (%lx)\n",
2372 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2373 if (e->X_add_symbol)
2374 {
2375 fprintf (stdout, " add_symbol ");
2376 ps (e->X_add_symbol);
2377 fprintf (stdout, "\n");
2378 }
2379 if (e->X_op_symbol)
2380 {
2381 fprintf (stdout, " op_symbol ");
2382 ps (e->X_op_symbol);
2383 fprintf (stdout, "\n");
2384 }
2385}
2386
2387static void
e3bb37b5 2388ps (symbolS *s)
252b5132
RH		 2389{
2390 fprintf (stdout, "%s type %s%s",
2391 S_GET_NAME (s),
2392 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2393 segment_name (S_GET_SEGMENT (s)));
2394}
2395
7b81dfbb 2396static struct type_name
252b5132 2397 {
40fb9820
L		 2398 i386_operand_type mask;
2399 const char *name;
252b5132 2400 }
7b81dfbb 2401const type_names[] =
252b5132 2402{
40fb9820
L		 2403 { OPERAND_TYPE_REG8, "r8" },
2404 { OPERAND_TYPE_REG16, "r16" },
2405 { OPERAND_TYPE_REG32, "r32" },
2406 { OPERAND_TYPE_REG64, "r64" },
2407 { OPERAND_TYPE_IMM8, "i8" },
2408 { OPERAND_TYPE_IMM8, "i8s" },
2409 { OPERAND_TYPE_IMM16, "i16" },
2410 { OPERAND_TYPE_IMM32, "i32" },
2411 { OPERAND_TYPE_IMM32S, "i32s" },
2412 { OPERAND_TYPE_IMM64, "i64" },
2413 { OPERAND_TYPE_IMM1, "i1" },
2414 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2415 { OPERAND_TYPE_DISP8, "d8" },
2416 { OPERAND_TYPE_DISP16, "d16" },
2417 { OPERAND_TYPE_DISP32, "d32" },
2418 { OPERAND_TYPE_DISP32S, "d32s" },
2419 { OPERAND_TYPE_DISP64, "d64" },
2420 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2421 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2422 { OPERAND_TYPE_CONTROL, "control reg" },
2423 { OPERAND_TYPE_TEST, "test reg" },
2424 { OPERAND_TYPE_DEBUG, "debug reg" },
2425 { OPERAND_TYPE_FLOATREG, "FReg" },
2426 { OPERAND_TYPE_FLOATACC, "FAcc" },
2427 { OPERAND_TYPE_SREG2, "SReg2" },
2428 { OPERAND_TYPE_SREG3, "SReg3" },
2429 { OPERAND_TYPE_ACC, "Acc" },
2430 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2431 { OPERAND_TYPE_REGMMX, "rMMX" },
2432 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2433 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2434 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2435};
2436
2437static void
40fb9820 2438pt (i386_operand_type t)
252b5132 2439{
40fb9820 2440 unsigned int j;
c6fb90c8 2441 i386_operand_type a;
252b5132 2442
40fb9820 2443 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2444 {
2445 a = operand_type_and (t, type_names[j].mask);
0349dc08 2446 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2447 fprintf (stdout, "%s, ", type_names[j].name);
2448 }
252b5132
RH		 2449 fflush (stdout);
2450}
2451
2452#endif /* DEBUG386 */
2453\f
252b5132 2454static bfd_reloc_code_real_type
3956db08 2455reloc (unsigned int size,
64e74474
AM		 2456 int pcrel,
2457 int sign,
2458 bfd_reloc_code_real_type other)
252b5132 2459{
47926f60 2460 if (other != NO_RELOC)
3956db08 2461 {
91d6fa6a 2462 reloc_howto_type *rel;
3956db08
JB		 2463
2464 if (size == 8)
2465 switch (other)
2466 {
64e74474
AM		 2467 case BFD_RELOC_X86_64_GOT32:
2468 return BFD_RELOC_X86_64_GOT64;
2469 break;
2470 case BFD_RELOC_X86_64_PLTOFF64:
2471 return BFD_RELOC_X86_64_PLTOFF64;
2472 break;
2473 case BFD_RELOC_X86_64_GOTPC32:
2474 other = BFD_RELOC_X86_64_GOTPC64;
2475 break;
2476 case BFD_RELOC_X86_64_GOTPCREL:
2477 other = BFD_RELOC_X86_64_GOTPCREL64;
2478 break;
2479 case BFD_RELOC_X86_64_TPOFF32:
2480 other = BFD_RELOC_X86_64_TPOFF64;
2481 break;
2482 case BFD_RELOC_X86_64_DTPOFF32:
2483 other = BFD_RELOC_X86_64_DTPOFF64;
2484 break;
2485 default:
2486 break;
3956db08 2487 }
e05278af
JB		 2488
2489 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2490 if (size == 4 && flag_code != CODE_64BIT)
2491 sign = -1;
2492
91d6fa6a
NC		 2493 rel = bfd_reloc_type_lookup (stdoutput, other);
2494 if (!rel)
3956db08 2495 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2496 else if (size != bfd_get_reloc_size (rel))
3956db08 2497 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2498 bfd_get_reloc_size (rel),
3956db08 2499 size);
91d6fa6a 2500 else if (pcrel && !rel->pc_relative)
3956db08 2501 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2502 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2503 && !sign)
91d6fa6a 2504 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2505 && sign > 0))
3956db08
JB		 2506 as_bad (_("relocated field and relocation type differ in signedness"));
2507 else
2508 return other;
2509 return NO_RELOC;
2510 }
252b5132
RH		 2511
2512 if (pcrel)
2513 {
3e73aa7c 2514 if (!sign)
3956db08 2515 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2516 switch (size)
2517 {
2518 case 1: return BFD_RELOC_8_PCREL;
2519 case 2: return BFD_RELOC_16_PCREL;
2520 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2521 case 8: return BFD_RELOC_64_PCREL;
252b5132 2522 }
3956db08 2523 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2524 }
2525 else
2526 {
3956db08 2527 if (sign > 0)
e5cb08ac 2528 switch (size)
3e73aa7c
JH		 2529 {
2530 case 4: return BFD_RELOC_X86_64_32S;
2531 }
2532 else
2533 switch (size)
2534 {
2535 case 1: return BFD_RELOC_8;
2536 case 2: return BFD_RELOC_16;
2537 case 4: return BFD_RELOC_32;
2538 case 8: return BFD_RELOC_64;
2539 }
3956db08
JB		 2540 as_bad (_("cannot do %s %u byte relocation"),
2541 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2542 }
2543
0cc9e1d3 2544 return NO_RELOC;
252b5132
RH		 2545}
2546
47926f60
KH		 2547/* Here we decide which fixups can be adjusted to make them relative to
2548 the beginning of the section instead of the symbol. Basically we need
2549 to make sure that the dynamic relocations are done correctly, so in
2550 some cases we force the original symbol to be used. */
2551
252b5132 2552int
e3bb37b5 2553tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2554{
6d249963 2555#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2556 if (!IS_ELF)
31312f95
AM		 2557 return 1;
2558
a161fe53
AM		 2559 /* Don't adjust pc-relative references to merge sections in 64-bit
2560 mode. */
2561 if (use_rela_relocations
2562 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2563 && fixP->fx_pcrel)
252b5132 2564 return 0;
31312f95 2565
8d01d9a9
AJ		 2566 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2567 and changed later by validate_fix. */
2568 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2569 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2570 return 0;
2571
ce8a8b2f 2572 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2573 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2574 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2575 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2576 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2577 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2578 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2579 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2580 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2581 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2582 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2583 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2584 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2585 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2586 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2587 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2588 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2589 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2590 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2591 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2592 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2593 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2594 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2595 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2596 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2597 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2598 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2599 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2600 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2601 return 0;
31312f95 2602#endif
252b5132
RH		 2603 return 1;
2604}
252b5132 2605
b4cac588 2606static int
e3bb37b5 2607intel_float_operand (const char *mnemonic)
252b5132 2608{
9306ca4a
JB		 2609 /* Note that the value returned is meaningful only for opcodes with (memory)
2610 operands, hence the code here is free to improperly handle opcodes that
2611 have no operands (for better performance and smaller code). */
2612
2613 if (mnemonic[0] != 'f')
2614 return 0; /* non-math */
2615
2616 switch (mnemonic[1])
2617 {
2618 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2619 the fs segment override prefix not currently handled because no
2620 call path can make opcodes without operands get here */
2621 case 'i':
2622 return 2 /* integer op */;
2623 case 'l':
2624 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2625 return 3; /* fldcw/fldenv */
2626 break;
2627 case 'n':
2628 if (mnemonic[2] != 'o' /* fnop */)
2629 return 3; /* non-waiting control op */
2630 break;
2631 case 'r':
2632 if (mnemonic[2] == 's')
2633 return 3; /* frstor/frstpm */
2634 break;
2635 case 's':
2636 if (mnemonic[2] == 'a')
2637 return 3; /* fsave */
2638 if (mnemonic[2] == 't')
2639 {
2640 switch (mnemonic[3])
2641 {
2642 case 'c': /* fstcw */
2643 case 'd': /* fstdw */
2644 case 'e': /* fstenv */
2645 case 's': /* fsts[gw] */
2646 return 3;
2647 }
2648 }
2649 break;
2650 case 'x':
2651 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2652 return 0; /* fxsave/fxrstor are not really math ops */
2653 break;
2654 }
252b5132 2655
9306ca4a 2656 return 1;
252b5132
RH		 2657}
2658
c0f3af97
L		 2659/* Build the VEX prefix. */
2660
2661static void
d3ce72d0 2662build_vex_prefix (const insn_template *t)
c0f3af97
L		 2663{
2664 unsigned int register_specifier;
2665 unsigned int implied_prefix;
2666 unsigned int vector_length;
2667
2668 /* Check register specifier. */
2669 if (i.vex.register_specifier)
2670 {
2671 register_specifier = i.vex.register_specifier->reg_num;
2672 if ((i.vex.register_specifier->reg_flags & RegRex))
2673 register_specifier += 8;
2674 register_specifier = ~register_specifier & 0xf;
2675 }
2676 else
2677 register_specifier = 0xf;
2678
fa99fab2
L		 2679 /* Use 2-byte VEX prefix by swappping destination and source
2680 operand. */
2681 if (!i.swap_operand
2682 && i.operands == i.reg_operands
7f399153 2683 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2684 && i.tm.opcode_modifier.s
2685 && i.rex == REX_B)
2686 {
2687 unsigned int xchg = i.operands - 1;
2688 union i386_op temp_op;
2689 i386_operand_type temp_type;
2690
2691 temp_type = i.types[xchg];
2692 i.types[xchg] = i.types[0];
2693 i.types[0] = temp_type;
2694 temp_op = i.op[xchg];
2695 i.op[xchg] = i.op[0];
2696 i.op[0] = temp_op;
2697
9c2799c2 2698 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2699
2700 i.rex = REX_R;
2701 xchg = i.rm.regmem;
2702 i.rm.regmem = i.rm.reg;
2703 i.rm.reg = xchg;
2704
2705 /* Use the next insn. */
2706 i.tm = t[1];
2707 }
2708
e3c58833 2709 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2710
2711 switch ((i.tm.base_opcode >> 8) & 0xff)
2712 {
2713 case 0:
2714 implied_prefix = 0;
2715 break;
2716 case DATA_PREFIX_OPCODE:
2717 implied_prefix = 1;
2718 break;
2719 case REPE_PREFIX_OPCODE:
2720 implied_prefix = 2;
2721 break;
2722 case REPNE_PREFIX_OPCODE:
2723 implied_prefix = 3;
2724 break;
2725 default:
2726 abort ();
2727 }
2728
2729 /* Use 2-byte VEX prefix if possible. */
7f399153 2730 if (i.tm.opcode_modifier.vexopcode == VEX0F
c0f3af97
L		 2731 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2732 {
2733 /* 2-byte VEX prefix. */
2734 unsigned int r;
2735
2736 i.vex.length = 2;
2737 i.vex.bytes[0] = 0xc5;
2738
2739 /* Check the REX.R bit. */
2740 r = (i.rex & REX_R) ? 0 : 1;
2741 i.vex.bytes[1] = (r << 7
2742 | register_specifier << 3
2743 | vector_length << 2
2744 | implied_prefix);
2745 }
2746 else
2747 {
2748 /* 3-byte VEX prefix. */
2749 unsigned int m, w;
2750
f88c9eb0
SP		 2751 i.vex.length = 3;
2752 i.vex.bytes[0] = 0xc4;
2753
7f399153 2754 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2755 {
7f399153
L		 2756 case VEX0F:
2757 m = 0x1;
2758 break;
2759 case VEX0F38:
2760 m = 0x2;
2761 break;
2762 case VEX0F3A:
2763 m = 0x3;
2764 break;
2765 case XOP08:
5dd85c99
SP		 2766 m = 0x8;
2767 i.vex.bytes[0] = 0x8f;
7f399153
L		 2768 break;
2769 case XOP09:
f88c9eb0
SP		 2770 m = 0x9;
2771 i.vex.bytes[0] = 0x8f;
7f399153
L		 2772 break;
2773 case XOP0A:
f88c9eb0
SP		 2774 m = 0xa;
2775 i.vex.bytes[0] = 0x8f;
7f399153
L		 2776 break;
2777 default:
2778 abort ();
f88c9eb0 2779 }
c0f3af97 2780
c0f3af97
L		 2781 /* The high 3 bits of the second VEX byte are 1's compliment
2782 of RXB bits from REX. */
2783 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2784
2785 /* Check the REX.W bit. */
2786 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 2787 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 2788 {
2789 if (w)
2790 abort ();
2791
1ef99a7b 2792 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 2793 w = 1;
2794 }
2795
2796 i.vex.bytes[2] = (w << 7
2797 | register_specifier << 3
2798 | vector_length << 2
2799 | implied_prefix);
2800 }
2801}
2802
65da13b5
L		 2803static void
2804process_immext (void)
2805{
2806 expressionS *exp;
2807
2808 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2809 {
1fed0ba1
L		 2810 /* SSE3 Instructions have the fixed operands with an opcode
2811 suffix which is coded in the same place as an 8-bit immediate
2812 field would be. Here we check those operands and remove them
2813 afterwards. */
65da13b5
L		 2814 unsigned int x;
2815
2816 for (x = 0; x < i.operands; x++)
2817 if (i.op[x].regs->reg_num != x)
2818 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2819 register_prefix, i.op[x].regs->reg_name, x + 1,
2820 i.tm.name);
2821
2822 i.operands = 0;
65da13b5
L		 2823 }
2824
c0f3af97 2825 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2826 which is coded in the same place as an 8-bit immediate field
2827 would be. Here we fake an 8-bit immediate operand from the
2828 opcode suffix stored in tm.extension_opcode.
2829
c1e679ec 2830 AVX instructions also use this encoding, for some of
c0f3af97 2831 3 argument instructions. */
65da13b5 2832
9c2799c2 2833 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2834 && (i.operands <= 2
2835 || (i.tm.opcode_modifier.vex
2836 && i.operands <= 4)));
65da13b5
L		 2837
2838 exp = &im_expressions[i.imm_operands++];
2839 i.op[i.operands].imms = exp;
2840 i.types[i.operands] = imm8;
2841 i.operands++;
2842 exp->X_op = O_constant;
2843 exp->X_add_number = i.tm.extension_opcode;
2844 i.tm.extension_opcode = None;
2845}
2846
252b5132
RH		 2847/* This is the guts of the machine-dependent assembler. LINE points to a
2848 machine dependent instruction. This function is supposed to emit
2849 the frags/bytes it assembles to. */
2850
2851void
65da13b5 2852md_assemble (char *line)
252b5132 2853{
40fb9820 2854 unsigned int j;
252b5132 2855 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 2856 const insn_template *t;
252b5132 2857
47926f60 2858 /* Initialize globals. */
252b5132
RH		 2859 memset (&i, '\0', sizeof (i));
2860 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2861 i.reloc[j] = NO_RELOC;
252b5132
RH		 2862 memset (disp_expressions, '\0', sizeof (disp_expressions));
2863 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2864 save_stack_p = save_stack;
252b5132
RH		 2865
2866 /* First parse an instruction mnemonic & call i386_operand for the operands.
2867 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2868 start of a (possibly prefixed) mnemonic. */
252b5132 2869
29b0f896
AM		 2870 line = parse_insn (line, mnemonic);
2871 if (line == NULL)
2872 return;
252b5132 2873
29b0f896 2874 line = parse_operands (line, mnemonic);
ee86248c 2875 this_operand = -1;
29b0f896
AM		 2876 if (line == NULL)
2877 return;
252b5132 2878
29b0f896
AM		 2879 /* Now we've parsed the mnemonic into a set of templates, and have the
2880 operands at hand. */
2881
2882 /* All intel opcodes have reversed operands except for "bound" and
2883 "enter". We also don't reverse intersegment "jmp" and "call"
2884 instructions with 2 immediate operands so that the immediate segment
050dfa73 2885 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2886 if (intel_syntax
2887 && i.operands > 1
29b0f896 2888 && (strcmp (mnemonic, "bound") != 0)
30123838 2889 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2890 && !(operand_type_check (i.types[0], imm)
2891 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2892 swap_operands ();
2893
ec56d5c0
JB		 2894 /* The order of the immediates should be reversed
2895 for 2 immediates extrq and insertq instructions */
2896 if (i.imm_operands == 2
2897 && (strcmp (mnemonic, "extrq") == 0
2898 || strcmp (mnemonic, "insertq") == 0))
2899 swap_2_operands (0, 1);
2900
29b0f896
AM		 2901 if (i.imm_operands)
2902 optimize_imm ();
2903
b300c311
L		 2904 /* Don't optimize displacement for movabs since it only takes 64bit
2905 displacement. */
2906 if (i.disp_operands
2907 && (flag_code != CODE_64BIT
2908 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2909 optimize_disp ();
2910
2911 /* Next, we find a template that matches the given insn,
2912 making sure the overlap of the given operands types is consistent
2913 with the template operand types. */
252b5132 2914
fa99fab2 2915 if (!(t = match_template ()))
29b0f896 2916 return;
252b5132 2917
daf50ae7 2918 if (sse_check != sse_check_none
81f8a913 2919 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2920 && (i.tm.cpu_flags.bitfield.cpusse
2921 || i.tm.cpu_flags.bitfield.cpusse2
2922 || i.tm.cpu_flags.bitfield.cpusse3
2923 || i.tm.cpu_flags.bitfield.cpussse3
2924 || i.tm.cpu_flags.bitfield.cpusse4_1
2925 || i.tm.cpu_flags.bitfield.cpusse4_2))
2926 {
2927 (sse_check == sse_check_warning
2928 ? as_warn
2929 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2930 }
2931
321fd21e
L		 2932 /* Zap movzx and movsx suffix. The suffix has been set from
2933 "word ptr" or "byte ptr" on the source operand in Intel syntax
2934 or extracted from mnemonic in AT&T syntax. But we'll use
2935 the destination register to choose the suffix for encoding. */
2936 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2937 {
321fd21e
L		 2938 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2939 there is no suffix, the default will be byte extension. */
2940 if (i.reg_operands != 2
2941 && !i.suffix
7ab9ffdd 2942 && intel_syntax)
321fd21e
L		 2943 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2944
2945 i.suffix = 0;
cd61ebfe 2946 }
24eab124 2947
40fb9820 2948 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2949 if (!add_prefix (FWAIT_OPCODE))
2950 return;
252b5132 2951
c1ba0266
L		 2952 /* Check for lock without a lockable instruction. Destination operand
2953 must be memory unless it is xchg (0x86). */
c32fa91d
L		 2954 if (i.prefix[LOCK_PREFIX]
2955 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 2956 || i.mem_operands == 0
2957 || (i.tm.base_opcode != 0x86
2958 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 2959 {
2960 as_bad (_("expecting lockable instruction after `lock'"));
2961 return;
2962 }
2963
29b0f896 2964 /* Check string instruction segment overrides. */
40fb9820 2965 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2966 {
2967 if (!check_string ())
5dd0794d 2968 return;
fc0763e6 2969 i.disp_operands = 0;
29b0f896 2970 }
5dd0794d 2971
29b0f896
AM		 2972 if (!process_suffix ())
2973 return;
e413e4e9 2974
bc0844ae
L		 2975 /* Update operand types. */
2976 for (j = 0; j < i.operands; j++)
2977 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
2978
29b0f896
AM		 2979 /* Make still unresolved immediate matches conform to size of immediate
2980 given in i.suffix. */
2981 if (!finalize_imm ())
2982 return;
252b5132 2983
40fb9820 2984 if (i.types[0].bitfield.imm1)
29b0f896 2985 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2986
9afe6eb8
L		 2987 /* We only need to check those implicit registers for instructions
2988 with 3 operands or less. */
2989 if (i.operands <= 3)
2990 for (j = 0; j < i.operands; j++)
2991 if (i.types[j].bitfield.inoutportreg
2992 || i.types[j].bitfield.shiftcount
2993 || i.types[j].bitfield.acc
2994 || i.types[j].bitfield.floatacc)
2995 i.reg_operands--;
40fb9820 2996
c0f3af97
L		 2997 /* ImmExt should be processed after SSE2AVX. */
2998 if (!i.tm.opcode_modifier.sse2avx
2999 && i.tm.opcode_modifier.immext)
65da13b5 3000 process_immext ();
252b5132 3001
29b0f896
AM		 3002 /* For insns with operands there are more diddles to do to the opcode. */
3003 if (i.operands)
3004 {
3005 if (!process_operands ())
3006 return;
3007 }
40fb9820 3008 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3009 {
3010 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3011 as_warn (_("translating to `%sp'"), i.tm.name);
3012 }
252b5132 3013
c0f3af97 3014 if (i.tm.opcode_modifier.vex)
fa99fab2 3015 build_vex_prefix (t);
c0f3af97 3016
5dd85c99
SP		 3017 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3018 instructions may define INT_OPCODE as well, so avoid this corner
3019 case for those instructions that use MODRM. */
3020 if (i.tm.base_opcode == INT_OPCODE
3021 && i.op[0].imms->X_add_number == 3
3022 && !i.tm.opcode_modifier.modrm)
29b0f896
AM		 3023 {
3024 i.tm.base_opcode = INT3_OPCODE;
3025 i.imm_operands = 0;
3026 }
252b5132 3027
40fb9820
L		 3028 if ((i.tm.opcode_modifier.jump
3029 || i.tm.opcode_modifier.jumpbyte
3030 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3031 && i.op[0].disps->X_op == O_constant)
3032 {
3033 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3034 the absolute address given by the constant. Since ix86 jumps and
3035 calls are pc relative, we need to generate a reloc. */
3036 i.op[0].disps->X_add_symbol = &abs_symbol;
3037 i.op[0].disps->X_op = O_symbol;
3038 }
252b5132 3039
40fb9820 3040 if (i.tm.opcode_modifier.rex64)
161a04f6 3041 i.rex |= REX_W;
252b5132 3042
29b0f896
AM		 3043 /* For 8 bit registers we need an empty rex prefix. Also if the
3044 instruction already has a prefix, we need to convert old
3045 registers to new ones. */
773f551c 3046
40fb9820 3047 if ((i.types[0].bitfield.reg8
29b0f896 3048 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3049 || (i.types[1].bitfield.reg8
29b0f896 3050 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3051 || ((i.types[0].bitfield.reg8
3052 || i.types[1].bitfield.reg8)
29b0f896
AM		 3053 && i.rex != 0))
3054 {
3055 int x;
726c5dcd 3056
29b0f896
AM		 3057 i.rex |= REX_OPCODE;
3058 for (x = 0; x < 2; x++)
3059 {
3060 /* Look for 8 bit operand that uses old registers. */
40fb9820 3061 if (i.types[x].bitfield.reg8
29b0f896 3062 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3063 {
29b0f896
AM		 3064 /* In case it is "hi" register, give up. */
3065 if (i.op[x].regs->reg_num > 3)
a540244d 3066 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3067 "instruction requiring REX prefix."),
a540244d 3068 register_prefix, i.op[x].regs->reg_name);
773f551c 3069
29b0f896
AM		 3070 /* Otherwise it is equivalent to the extended register.
3071 Since the encoding doesn't change this is merely
3072 cosmetic cleanup for debug output. */
3073
3074 i.op[x].regs = i.op[x].regs + 8;
773f551c 3075 }
29b0f896
AM		 3076 }
3077 }
773f551c 3078
7ab9ffdd 3079 if (i.rex != 0)
29b0f896
AM		 3080 add_prefix (REX_OPCODE | i.rex);
3081
3082 /* We are ready to output the insn. */
3083 output_insn ();
3084}
3085
3086static char *
e3bb37b5 3087parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3088{
3089 char *l = line;
3090 char *token_start = l;
3091 char *mnem_p;
5c6af06e 3092 int supported;
d3ce72d0 3093 const insn_template *t;
b6169b20 3094 char *dot_p = NULL;
29b0f896
AM		 3095
3096 /* Non-zero if we found a prefix only acceptable with string insns. */
3097 const char *expecting_string_instruction = NULL;
45288df1 3098
29b0f896
AM		 3099 while (1)
3100 {
3101 mnem_p = mnemonic;
3102 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3103 {
b6169b20
L		 3104 if (*mnem_p == '.')
3105 dot_p = mnem_p;
29b0f896
AM		 3106 mnem_p++;
3107 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3108 {
29b0f896
AM		 3109 as_bad (_("no such instruction: `%s'"), token_start);
3110 return NULL;
3111 }
3112 l++;
3113 }
3114 if (!is_space_char (*l)
3115 && *l != END_OF_INSN
e44823cf
JB		 3116 && (intel_syntax
3117 || (*l != PREFIX_SEPARATOR
3118 && *l != ',')))
29b0f896
AM		 3119 {
3120 as_bad (_("invalid character %s in mnemonic"),
3121 output_invalid (*l));
3122 return NULL;
3123 }
3124 if (token_start == l)
3125 {
e44823cf 3126 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3127 as_bad (_("expecting prefix; got nothing"));
3128 else
3129 as_bad (_("expecting mnemonic; got nothing"));
3130 return NULL;
3131 }
45288df1 3132
29b0f896 3133 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3134 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3135
29b0f896
AM		 3136 if (*l != END_OF_INSN
3137 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3138 && current_templates
40fb9820 3139 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3140 {
c6fb90c8 3141 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3142 {
3143 as_bad ((flag_code != CODE_64BIT
3144 ? _("`%s' is only supported in 64-bit mode")
3145 : _("`%s' is not supported in 64-bit mode")),
3146 current_templates->start->name);
3147 return NULL;
3148 }
29b0f896
AM		 3149 /* If we are in 16-bit mode, do not allow addr16 or data16.
3150 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3151 if ((current_templates->start->opcode_modifier.size16
3152 || current_templates->start->opcode_modifier.size32)
29b0f896 3153 && flag_code != CODE_64BIT
40fb9820 3154 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3155 ^ (flag_code == CODE_16BIT)))
3156 {
3157 as_bad (_("redundant %s prefix"),
3158 current_templates->start->name);
3159 return NULL;
45288df1 3160 }
29b0f896
AM		 3161 /* Add prefix, checking for repeated prefixes. */
3162 switch (add_prefix (current_templates->start->base_opcode))
3163 {
c32fa91d 3164 case PREFIX_EXIST:
29b0f896 3165 return NULL;
c32fa91d 3166 case PREFIX_REP:
29b0f896
AM		 3167 expecting_string_instruction = current_templates->start->name;
3168 break;
c32fa91d
L		 3169 default:
3170 break;
29b0f896
AM		 3171 }
3172 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3173 token_start = ++l;
3174 }
3175 else
3176 break;
3177 }
45288df1 3178
30a55f88 3179 if (!current_templates)
b6169b20 3180 {
30a55f88
L		 3181 /* Check if we should swap operand in encoding. */
3182 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3183 i.swap_operand = 1;
3184 else
3185 goto check_suffix;
3186 mnem_p = dot_p;
3187 *dot_p = '\0';
d3ce72d0 3188 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3189 }
3190
29b0f896
AM		 3191 if (!current_templates)
3192 {
b6169b20 3193check_suffix:
29b0f896
AM		 3194 /* See if we can get a match by trimming off a suffix. */
3195 switch (mnem_p[-1])
3196 {
3197 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3198 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3199 i.suffix = SHORT_MNEM_SUFFIX;
3200 else
29b0f896
AM		 3201 case BYTE_MNEM_SUFFIX:
3202 case QWORD_MNEM_SUFFIX:
3203 i.suffix = mnem_p[-1];
3204 mnem_p[-1] = '\0';
d3ce72d0
NC		 3205 current_templates = (const templates *) hash_find (op_hash,
3206 mnemonic);
29b0f896
AM		 3207 break;
3208 case SHORT_MNEM_SUFFIX:
3209 case LONG_MNEM_SUFFIX:
3210 if (!intel_syntax)
3211 {
3212 i.suffix = mnem_p[-1];
3213 mnem_p[-1] = '\0';
d3ce72d0
NC		 3214 current_templates = (const templates *) hash_find (op_hash,
3215 mnemonic);
29b0f896
AM		 3216 }
3217 break;
252b5132 3218
29b0f896
AM		 3219 /* Intel Syntax. */
3220 case 'd':
3221 if (intel_syntax)
3222 {
9306ca4a 3223 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3224 i.suffix = SHORT_MNEM_SUFFIX;
3225 else
3226 i.suffix = LONG_MNEM_SUFFIX;
3227 mnem_p[-1] = '\0';
d3ce72d0
NC		 3228 current_templates = (const templates *) hash_find (op_hash,
3229 mnemonic);
29b0f896
AM		 3230 }
3231 break;
3232 }
3233 if (!current_templates)
3234 {
3235 as_bad (_("no such instruction: `%s'"), token_start);
3236 return NULL;
3237 }
3238 }
252b5132 3239
40fb9820
L		 3240 if (current_templates->start->opcode_modifier.jump
3241 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3242 {
3243 /* Check for a branch hint. We allow ",pt" and ",pn" for
3244 predict taken and predict not taken respectively.
3245 I'm not sure that branch hints actually do anything on loop
3246 and jcxz insns (JumpByte) for current Pentium4 chips. They
3247 may work in the future and it doesn't hurt to accept them
3248 now. */
3249 if (l[0] == ',' && l[1] == 'p')
3250 {
3251 if (l[2] == 't')
3252 {
3253 if (!add_prefix (DS_PREFIX_OPCODE))
3254 return NULL;
3255 l += 3;
3256 }
3257 else if (l[2] == 'n')
3258 {
3259 if (!add_prefix (CS_PREFIX_OPCODE))
3260 return NULL;
3261 l += 3;
3262 }
3263 }
3264 }
3265 /* Any other comma loses. */
3266 if (*l == ',')
3267 {
3268 as_bad (_("invalid character %s in mnemonic"),
3269 output_invalid (*l));
3270 return NULL;
3271 }
252b5132 3272
29b0f896 3273 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3274 supported = 0;
3275 for (t = current_templates->start; t < current_templates->end; ++t)
3276 {
c0f3af97
L		 3277 supported |= cpu_flags_match (t);
3278 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3279 goto skip;
5c6af06e 3280 }
3629bb00 3281
c0f3af97 3282 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3283 {
3284 as_bad (flag_code == CODE_64BIT
3285 ? _("`%s' is not supported in 64-bit mode")
3286 : _("`%s' is only supported in 64-bit mode"),
3287 current_templates->start->name);
3288 return NULL;
3289 }
c0f3af97 3290 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3291 {
3629bb00 3292 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3293 current_templates->start->name,
41aacd83 3294 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3295 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3296 return NULL;
29b0f896 3297 }
3629bb00
L		 3298
3299skip:
3300 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3301 && (flag_code != CODE_16BIT))
29b0f896
AM		 3302 {
3303 as_warn (_("use .code16 to ensure correct addressing mode"));
3304 }
252b5132 3305
29b0f896 3306 /* Check for rep/repne without a string instruction. */
f41bbced 3307 if (expecting_string_instruction)
29b0f896 3308 {
f41bbced
JB		 3309 static templates override;
3310
3311 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3312 if (t->opcode_modifier.isstring)
f41bbced
JB		 3313 break;
3314 if (t >= current_templates->end)
3315 {
3316 as_bad (_("expecting string instruction after `%s'"),
64e74474 3317 expecting_string_instruction);
f41bbced
JB		 3318 return NULL;
3319 }
3320 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3321 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3322 break;
3323 override.end = t;
3324 current_templates = &override;
29b0f896 3325 }
252b5132 3326
29b0f896
AM		 3327 return l;
3328}
252b5132 3329
29b0f896 3330static char *
e3bb37b5 3331parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3332{
3333 char *token_start;
3138f287 3334
29b0f896
AM		 3335 /* 1 if operand is pending after ','. */
3336 unsigned int expecting_operand = 0;
252b5132 3337
29b0f896
AM		 3338 /* Non-zero if operand parens not balanced. */
3339 unsigned int paren_not_balanced;
3340
3341 while (*l != END_OF_INSN)
3342 {
3343 /* Skip optional white space before operand. */
3344 if (is_space_char (*l))
3345 ++l;
3346 if (!is_operand_char (*l) && *l != END_OF_INSN)
3347 {
3348 as_bad (_("invalid character %s before operand %d"),
3349 output_invalid (*l),
3350 i.operands + 1);
3351 return NULL;
3352 }
3353 token_start = l; /* after white space */
3354 paren_not_balanced = 0;
3355 while (paren_not_balanced || *l != ',')
3356 {
3357 if (*l == END_OF_INSN)
3358 {
3359 if (paren_not_balanced)
3360 {
3361 if (!intel_syntax)
3362 as_bad (_("unbalanced parenthesis in operand %d."),
3363 i.operands + 1);
3364 else
3365 as_bad (_("unbalanced brackets in operand %d."),
3366 i.operands + 1);
3367 return NULL;
3368 }
3369 else
3370 break; /* we are done */
3371 }
3372 else if (!is_operand_char (*l) && !is_space_char (*l))
3373 {
3374 as_bad (_("invalid character %s in operand %d"),
3375 output_invalid (*l),
3376 i.operands + 1);
3377 return NULL;
3378 }
3379 if (!intel_syntax)
3380 {
3381 if (*l == '(')
3382 ++paren_not_balanced;
3383 if (*l == ')')
3384 --paren_not_balanced;
3385 }
3386 else
3387 {
3388 if (*l == '[')
3389 ++paren_not_balanced;
3390 if (*l == ']')
3391 --paren_not_balanced;
3392 }
3393 l++;
3394 }
3395 if (l != token_start)
3396 { /* Yes, we've read in another operand. */
3397 unsigned int operand_ok;
3398 this_operand = i.operands++;
7d5e4556 3399 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3400 if (i.operands > MAX_OPERANDS)
3401 {
3402 as_bad (_("spurious operands; (%d operands/instruction max)"),
3403 MAX_OPERANDS);
3404 return NULL;
3405 }
3406 /* Now parse operand adding info to 'i' as we go along. */
3407 END_STRING_AND_SAVE (l);
3408
3409 if (intel_syntax)
3410 operand_ok =
3411 i386_intel_operand (token_start,
3412 intel_float_operand (mnemonic));
3413 else
a7619375 3414 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3415
3416 RESTORE_END_STRING (l);
3417 if (!operand_ok)
3418 return NULL;
3419 }
3420 else
3421 {
3422 if (expecting_operand)
3423 {
3424 expecting_operand_after_comma:
3425 as_bad (_("expecting operand after ','; got nothing"));
3426 return NULL;
3427 }
3428 if (*l == ',')
3429 {
3430 as_bad (_("expecting operand before ','; got nothing"));
3431 return NULL;
3432 }
3433 }
7f3f1ea2 3434
29b0f896
AM		 3435 /* Now *l must be either ',' or END_OF_INSN. */
3436 if (*l == ',')
3437 {
3438 if (*++l == END_OF_INSN)
3439 {
3440 /* Just skip it, if it's \n complain. */
3441 goto expecting_operand_after_comma;
3442 }
3443 expecting_operand = 1;
3444 }
3445 }
3446 return l;
3447}
7f3f1ea2 3448
050dfa73 3449static void
4d456e3d 3450swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3451{
3452 union i386_op temp_op;
40fb9820 3453 i386_operand_type temp_type;
050dfa73 3454 enum bfd_reloc_code_real temp_reloc;
4eed87de 3455
050dfa73
MM		 3456 temp_type = i.types[xchg2];
3457 i.types[xchg2] = i.types[xchg1];
3458 i.types[xchg1] = temp_type;
3459 temp_op = i.op[xchg2];
3460 i.op[xchg2] = i.op[xchg1];
3461 i.op[xchg1] = temp_op;
3462 temp_reloc = i.reloc[xchg2];
3463 i.reloc[xchg2] = i.reloc[xchg1];
3464 i.reloc[xchg1] = temp_reloc;
3465}
3466
29b0f896 3467static void
e3bb37b5 3468swap_operands (void)
29b0f896 3469{
b7c61d9a 3470 switch (i.operands)
050dfa73 3471 {
c0f3af97 3472 case 5:
b7c61d9a 3473 case 4:
4d456e3d 3474 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3475 case 3:
3476 case 2:
4d456e3d 3477 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3478 break;
3479 default:
3480 abort ();
29b0f896 3481 }
29b0f896
AM		 3482
3483 if (i.mem_operands == 2)
3484 {
3485 const seg_entry *temp_seg;
3486 temp_seg = i.seg[0];
3487 i.seg[0] = i.seg[1];
3488 i.seg[1] = temp_seg;
3489 }
3490}
252b5132 3491
29b0f896
AM		 3492/* Try to ensure constant immediates are represented in the smallest
3493 opcode possible. */
3494static void
e3bb37b5 3495optimize_imm (void)
29b0f896
AM		 3496{
3497 char guess_suffix = 0;
3498 int op;
252b5132 3499
29b0f896
AM		 3500 if (i.suffix)
3501 guess_suffix = i.suffix;
3502 else if (i.reg_operands)
3503 {
3504 /* Figure out a suffix from the last register operand specified.
3505 We can't do this properly yet, ie. excluding InOutPortReg,
3506 but the following works for instructions with immediates.
3507 In any case, we can't set i.suffix yet. */
3508 for (op = i.operands; --op >= 0;)
40fb9820 3509 if (i.types[op].bitfield.reg8)
7ab9ffdd 3510 {
40fb9820
L		 3511 guess_suffix = BYTE_MNEM_SUFFIX;
3512 break;
3513 }
3514 else if (i.types[op].bitfield.reg16)
252b5132 3515 {
40fb9820
L		 3516 guess_suffix = WORD_MNEM_SUFFIX;
3517 break;
3518 }
3519 else if (i.types[op].bitfield.reg32)
3520 {
3521 guess_suffix = LONG_MNEM_SUFFIX;
3522 break;
3523 }
3524 else if (i.types[op].bitfield.reg64)
3525 {
3526 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3527 break;
252b5132 3528 }
29b0f896
AM		 3529 }
3530 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3531 guess_suffix = WORD_MNEM_SUFFIX;
3532
3533 for (op = i.operands; --op >= 0;)
40fb9820 3534 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3535 {
3536 switch (i.op[op].imms->X_op)
252b5132 3537 {
29b0f896
AM		 3538 case O_constant:
3539 /* If a suffix is given, this operand may be shortened. */
3540 switch (guess_suffix)
252b5132 3541 {
29b0f896 3542 case LONG_MNEM_SUFFIX:
40fb9820
L		 3543 i.types[op].bitfield.imm32 = 1;
3544 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3545 break;
3546 case WORD_MNEM_SUFFIX:
40fb9820
L		 3547 i.types[op].bitfield.imm16 = 1;
3548 i.types[op].bitfield.imm32 = 1;
3549 i.types[op].bitfield.imm32s = 1;
3550 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3551 break;
3552 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3553 i.types[op].bitfield.imm8 = 1;
3554 i.types[op].bitfield.imm8s = 1;
3555 i.types[op].bitfield.imm16 = 1;
3556 i.types[op].bitfield.imm32 = 1;
3557 i.types[op].bitfield.imm32s = 1;
3558 i.types[op].bitfield.imm64 = 1;
29b0f896 3559 break;
252b5132 3560 }
252b5132 3561
29b0f896
AM		 3562 /* If this operand is at most 16 bits, convert it
3563 to a signed 16 bit number before trying to see
3564 whether it will fit in an even smaller size.
3565 This allows a 16-bit operand such as $0xffe0 to
3566 be recognised as within Imm8S range. */
40fb9820 3567 if ((i.types[op].bitfield.imm16)
29b0f896 3568 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3569 {
29b0f896
AM		 3570 i.op[op].imms->X_add_number =
3571 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3572 }
40fb9820 3573 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3574 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3575 == 0))
3576 {
3577 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3578 ^ ((offsetT) 1 << 31))
3579 - ((offsetT) 1 << 31));
3580 }
40fb9820 3581 i.types[op]
c6fb90c8
L		 3582 = operand_type_or (i.types[op],
3583 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3584
29b0f896
AM		 3585 /* We must avoid matching of Imm32 templates when 64bit
3586 only immediate is available. */
3587 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3588 i.types[op].bitfield.imm32 = 0;
29b0f896 3589 break;
252b5132 3590
29b0f896
AM		 3591 case O_absent:
3592 case O_register:
3593 abort ();
3594
3595 /* Symbols and expressions. */
3596 default:
9cd96992
JB		 3597 /* Convert symbolic operand to proper sizes for matching, but don't
3598 prevent matching a set of insns that only supports sizes other
3599 than those matching the insn suffix. */
3600 {
40fb9820 3601 i386_operand_type mask, allowed;
d3ce72d0 3602 const insn_template *t;
9cd96992 3603
0dfbf9d7
L		 3604 operand_type_set (&mask, 0);
3605 operand_type_set (&allowed, 0);
40fb9820 3606
4eed87de
AM		 3607 for (t = current_templates->start;
3608 t < current_templates->end;
3609 ++t)
c6fb90c8
L		 3610 allowed = operand_type_or (allowed,
3611 t->operand_types[op]);
9cd96992
JB		 3612 switch (guess_suffix)
3613 {
3614 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3615 mask.bitfield.imm64 = 1;
3616 mask.bitfield.imm32s = 1;
9cd96992
JB		 3617 break;
3618 case LONG_MNEM_SUFFIX:
40fb9820 3619 mask.bitfield.imm32 = 1;
9cd96992
JB		 3620 break;
3621 case WORD_MNEM_SUFFIX:
40fb9820 3622 mask.bitfield.imm16 = 1;
9cd96992
JB		 3623 break;
3624 case BYTE_MNEM_SUFFIX:
40fb9820 3625 mask.bitfield.imm8 = 1;
9cd96992
JB		 3626 break;
3627 default:
9cd96992
JB		 3628 break;
3629 }
c6fb90c8 3630 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3631 if (!operand_type_all_zero (&allowed))
c6fb90c8 3632 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3633 }
29b0f896 3634 break;
252b5132 3635 }
29b0f896
AM		 3636 }
3637}
47926f60 3638
29b0f896
AM		 3639/* Try to use the smallest displacement type too. */
3640static void
e3bb37b5 3641optimize_disp (void)
29b0f896
AM		 3642{
3643 int op;
3e73aa7c 3644
29b0f896 3645 for (op = i.operands; --op >= 0;)
40fb9820 3646 if (operand_type_check (i.types[op], disp))
252b5132 3647 {
b300c311 3648 if (i.op[op].disps->X_op == O_constant)
252b5132 3649 {
91d6fa6a 3650 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3651
40fb9820 3652 if (i.types[op].bitfield.disp16
91d6fa6a 3653 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3654 {
3655 /* If this operand is at most 16 bits, convert
3656 to a signed 16 bit number and don't use 64bit
3657 displacement. */
91d6fa6a 3658 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3659 i.types[op].bitfield.disp64 = 0;
b300c311 3660 }
40fb9820 3661 if (i.types[op].bitfield.disp32
91d6fa6a 3662 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3663 {
3664 /* If this operand is at most 32 bits, convert
3665 to a signed 32 bit number and don't use 64bit
3666 displacement. */
91d6fa6a
NC		 3667 op_disp &= (((offsetT) 2 << 31) - 1);
3668 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3669 i.types[op].bitfield.disp64 = 0;
b300c311 3670 }
91d6fa6a 3671 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3672 {
40fb9820
L		 3673 i.types[op].bitfield.disp8 = 0;
3674 i.types[op].bitfield.disp16 = 0;
3675 i.types[op].bitfield.disp32 = 0;
3676 i.types[op].bitfield.disp32s = 0;
3677 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3678 i.op[op].disps = 0;
3679 i.disp_operands--;
3680 }
3681 else if (flag_code == CODE_64BIT)
3682 {
91d6fa6a 3683 if (fits_in_signed_long (op_disp))
28a9d8f5 3684 {
40fb9820
L		 3685 i.types[op].bitfield.disp64 = 0;
3686 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3687 }
0e1147d9 3688 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3689 && fits_in_unsigned_long (op_disp))
40fb9820 3690 i.types[op].bitfield.disp32 = 1;
b300c311 3691 }
40fb9820
L		 3692 if ((i.types[op].bitfield.disp32
3693 || i.types[op].bitfield.disp32s
3694 || i.types[op].bitfield.disp16)
91d6fa6a 3695 && fits_in_signed_byte (op_disp))
40fb9820 3696 i.types[op].bitfield.disp8 = 1;
252b5132 3697 }
67a4f2b7
AO		 3698 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3699 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3700 {
3701 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3702 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3703 i.types[op].bitfield.disp8 = 0;
3704 i.types[op].bitfield.disp16 = 0;
3705 i.types[op].bitfield.disp32 = 0;
3706 i.types[op].bitfield.disp32s = 0;
3707 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3708 }
3709 else
b300c311 3710 /* We only support 64bit displacement on constants. */
40fb9820 3711 i.types[op].bitfield.disp64 = 0;
252b5132 3712 }
29b0f896
AM		 3713}
3714
d3ce72d0 3715static const insn_template *
e3bb37b5 3716match_template (void)
29b0f896
AM		 3717{
3718 /* Points to template once we've found it. */
d3ce72d0 3719 const insn_template *t;
40fb9820 3720 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3721 i386_operand_type overlap4;
29b0f896 3722 unsigned int found_reverse_match;
40fb9820
L		 3723 i386_opcode_modifier suffix_check;
3724 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3725 int addr_prefix_disp;
a5c311ca 3726 unsigned int j;
3629bb00 3727 unsigned int found_cpu_match;
45664ddb 3728 unsigned int check_register;
29b0f896 3729
c0f3af97
L		 3730#if MAX_OPERANDS != 5
3731# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3732#endif
3733
29b0f896 3734 found_reverse_match = 0;
539e75ad 3735 addr_prefix_disp = -1;
40fb9820
L		 3736
3737 memset (&suffix_check, 0, sizeof (suffix_check));
3738 if (i.suffix == BYTE_MNEM_SUFFIX)
3739 suffix_check.no_bsuf = 1;
3740 else if (i.suffix == WORD_MNEM_SUFFIX)
3741 suffix_check.no_wsuf = 1;
3742 else if (i.suffix == SHORT_MNEM_SUFFIX)
3743 suffix_check.no_ssuf = 1;
3744 else if (i.suffix == LONG_MNEM_SUFFIX)
3745 suffix_check.no_lsuf = 1;
3746 else if (i.suffix == QWORD_MNEM_SUFFIX)
3747 suffix_check.no_qsuf = 1;
3748 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3749 suffix_check.no_ldsuf = 1;
29b0f896 3750
45aa61fe 3751 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3752 {
539e75ad
L		 3753 addr_prefix_disp = -1;
3754
29b0f896
AM		 3755 /* Must have right number of operands. */
3756 if (i.operands != t->operands)
3757 continue;
3758
50aecf8c 3759 /* Check processor support. */
c0f3af97
L		 3760 found_cpu_match = (cpu_flags_match (t)
3761 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3762 if (!found_cpu_match)
3763 continue;
3764
e1d4d893
L		 3765 /* Check old gcc support. */
3766 if (!old_gcc && t->opcode_modifier.oldgcc)
3767 continue;
3768
3769 /* Check AT&T mnemonic. */
3770 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3771 continue;
3772
5c07affc
L		 3773 /* Check AT&T syntax Intel syntax. */
3774 if ((intel_syntax && t->opcode_modifier.attsyntax)
3775 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3776 continue;
3777
20592a94 3778 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3779 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3780 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3781 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3782 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3783 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3784 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3785 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3786 continue;
3787
5c07affc 3788 if (!operand_size_match (t))
7d5e4556 3789 continue;
539e75ad 3790
5c07affc
L		 3791 for (j = 0; j < MAX_OPERANDS; j++)
3792 operand_types[j] = t->operand_types[j];
3793
45aa61fe
AM		 3794 /* In general, don't allow 64-bit operands in 32-bit mode. */
3795 if (i.suffix == QWORD_MNEM_SUFFIX
3796 && flag_code != CODE_64BIT
3797 && (intel_syntax
40fb9820 3798 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3799 && !intel_float_operand (t->name))
3800 : intel_float_operand (t->name) != 2)
40fb9820 3801 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3802 && !operand_types[0].bitfield.regxmm
3803 && !operand_types[0].bitfield.regymm)
40fb9820 3804 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3805 && !!operand_types[t->operands > 1].bitfield.regxmm
3806 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3807 && (t->base_opcode != 0x0fc7
3808 || t->extension_opcode != 1 /* cmpxchg8b */))
3809 continue;
3810
192dc9c6
JB		 3811 /* In general, don't allow 32-bit operands on pre-386. */
3812 else if (i.suffix == LONG_MNEM_SUFFIX
3813 && !cpu_arch_flags.bitfield.cpui386
3814 && (intel_syntax
3815 ? (!t->opcode_modifier.ignoresize
3816 && !intel_float_operand (t->name))
3817 : intel_float_operand (t->name) != 2)
3818 && ((!operand_types[0].bitfield.regmmx
3819 && !operand_types[0].bitfield.regxmm)
3820 || (!operand_types[t->operands > 1].bitfield.regmmx
3821 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3822 continue;
3823
29b0f896 3824 /* Do not verify operands when there are none. */
50aecf8c 3825 else
29b0f896 3826 {
c6fb90c8 3827 if (!t->operands)
2dbab7d5
L		 3828 /* We've found a match; break out of loop. */
3829 break;
29b0f896 3830 }
252b5132 3831
539e75ad
L		 3832 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3833 into Disp32/Disp16/Disp32 operand. */
3834 if (i.prefix[ADDR_PREFIX] != 0)
3835 {
40fb9820 3836 /* There should be only one Disp operand. */
539e75ad
L		 3837 switch (flag_code)
3838 {
3839 case CODE_16BIT:
40fb9820
L		 3840 for (j = 0; j < MAX_OPERANDS; j++)
3841 {
3842 if (operand_types[j].bitfield.disp16)
3843 {
3844 addr_prefix_disp = j;
3845 operand_types[j].bitfield.disp32 = 1;
3846 operand_types[j].bitfield.disp16 = 0;
3847 break;
3848 }
3849 }
539e75ad
L		 3850 break;
3851 case CODE_32BIT:
40fb9820
L		 3852 for (j = 0; j < MAX_OPERANDS; j++)
3853 {
3854 if (operand_types[j].bitfield.disp32)
3855 {
3856 addr_prefix_disp = j;
3857 operand_types[j].bitfield.disp32 = 0;
3858 operand_types[j].bitfield.disp16 = 1;
3859 break;
3860 }
3861 }
539e75ad
L		 3862 break;
3863 case CODE_64BIT:
40fb9820
L		 3864 for (j = 0; j < MAX_OPERANDS; j++)
3865 {
3866 if (operand_types[j].bitfield.disp64)
3867 {
3868 addr_prefix_disp = j;
3869 operand_types[j].bitfield.disp64 = 0;
3870 operand_types[j].bitfield.disp32 = 1;
3871 break;
3872 }
3873 }
539e75ad
L		 3874 break;
3875 }
539e75ad
L		 3876 }
3877
45664ddb
L		 3878 /* We check register size only if size of operands can be
3879 encoded the canonical way. */
3880 check_register = t->opcode_modifier.w;
c6fb90c8 3881 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3882 switch (t->operands)
3883 {
3884 case 1:
40fb9820 3885 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3886 continue;
3887 break;
3888 case 2:
8b38ad71
L		 3889 /* xchg %eax, %eax is a special case. It is an aliase for nop
3890 only in 32bit mode and we can use opcode 0x90. In 64bit
3891 mode, we can't use 0x90 for xchg %eax, %eax since it should
3892 zero-extend %eax to %rax. */
3893 if (flag_code == CODE_64BIT
3894 && t->base_opcode == 0x90
0dfbf9d7
L		 3895 && operand_type_equal (&i.types [0], &acc32)
3896 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3897 continue;
b6169b20
L		 3898 if (i.swap_operand)
3899 {
3900 /* If we swap operand in encoding, we either match
3901 the next one or reverse direction of operands. */
3902 if (t->opcode_modifier.s)
3903 continue;
3904 else if (t->opcode_modifier.d)
3905 goto check_reverse;
3906 }
3907
29b0f896 3908 case 3:
fa99fab2
L		 3909 /* If we swap operand in encoding, we match the next one. */
3910 if (i.swap_operand && t->opcode_modifier.s)
3911 continue;
f48ff2ae 3912 case 4:
c0f3af97 3913 case 5:
c6fb90c8 3914 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3915 if (!operand_type_match (overlap0, i.types[0])
3916 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3917 || (check_register
3918 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3919 operand_types[0],
3920 overlap1, i.types[1],
3921 operand_types[1])))
29b0f896
AM		 3922 {
3923 /* Check if other direction is valid ... */
40fb9820 3924 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3925 continue;
3926
b6169b20 3927check_reverse:
29b0f896 3928 /* Try reversing direction of operands. */
c6fb90c8
L		 3929 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3930 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3931 if (!operand_type_match (overlap0, i.types[0])
3932 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3933 || (check_register
3934 && !operand_type_register_match (overlap0,
3935 i.types[0],
3936 operand_types[1],
3937 overlap1,
3938 i.types[1],
3939 operand_types[0])))
29b0f896
AM		 3940 {
3941 /* Does not match either direction. */
3942 continue;
3943 }
3944 /* found_reverse_match holds which of D or FloatDR
3945 we've found. */
40fb9820 3946 if (t->opcode_modifier.d)
8a2ed489 3947 found_reverse_match = Opcode_D;
40fb9820 3948 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3949 found_reverse_match = Opcode_FloatD;
3950 else
3951 found_reverse_match = 0;
40fb9820 3952 if (t->opcode_modifier.floatr)
8a2ed489 3953 found_reverse_match |= Opcode_FloatR;
29b0f896 3954 }
f48ff2ae 3955 else
29b0f896 3956 {
f48ff2ae 3957 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3958 switch (t->operands)
3959 {
c0f3af97
L		 3960 case 5:
3961 overlap4 = operand_type_and (i.types[4],
3962 operand_types[4]);
d1cbb4db 3963 case 4:
c6fb90c8
L		 3964 overlap3 = operand_type_and (i.types[3],
3965 operand_types[3]);
d1cbb4db 3966 case 3:
c6fb90c8
L		 3967 overlap2 = operand_type_and (i.types[2],
3968 operand_types[2]);
d1cbb4db
L		 3969 break;
3970 }
29b0f896 3971
f48ff2ae
L		 3972 switch (t->operands)
3973 {
c0f3af97
L		 3974 case 5:
3975 if (!operand_type_match (overlap4, i.types[4])
3976 || !operand_type_register_match (overlap3,
3977 i.types[3],
3978 operand_types[3],
3979 overlap4,
3980 i.types[4],
3981 operand_types[4]))
3982 continue;
f48ff2ae 3983 case 4:
40fb9820 3984 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3985 || (check_register
3986 && !operand_type_register_match (overlap2,
3987 i.types[2],
3988 operand_types[2],
3989 overlap3,
3990 i.types[3],
3991 operand_types[3])))
f48ff2ae
L		 3992 continue;
3993 case 3:
3994 /* Here we make use of the fact that there are no
3995 reverse match 3 operand instructions, and all 3
3996 operand instructions only need to be checked for
3997 register consistency between operands 2 and 3. */
40fb9820 3998 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3999 || (check_register
4000 && !operand_type_register_match (overlap1,
4001 i.types[1],
4002 operand_types[1],
4003 overlap2,
4004 i.types[2],
4005 operand_types[2])))
f48ff2ae
L		 4006 continue;
4007 break;
4008 }
29b0f896 4009 }
f48ff2ae 4010 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4011 slip through to break. */
4012 }
3629bb00 4013 if (!found_cpu_match)
29b0f896
AM		 4014 {
4015 found_reverse_match = 0;
4016 continue;
4017 }
c0f3af97 4018
29b0f896
AM		 4019 /* We've found a match; break out of loop. */
4020 break;
4021 }
4022
4023 if (t == current_templates->end)
4024 {
4025 /* We found no match. */
95f283e8
L		 4026 if (intel_syntax)
4027 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
4028 current_templates->start->name);
4029 else
4030 as_bad (_("suffix or operands invalid for `%s'"),
4031 current_templates->start->name);
fa99fab2 4032 return NULL;
29b0f896 4033 }
252b5132 4034
29b0f896
AM		 4035 if (!quiet_warnings)
4036 {
4037 if (!intel_syntax
40fb9820
L		 4038 && (i.types[0].bitfield.jumpabsolute
4039 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4040 {
4041 as_warn (_("indirect %s without `*'"), t->name);
4042 }
4043
40fb9820
L		 4044 if (t->opcode_modifier.isprefix
4045 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4046 {
4047 /* Warn them that a data or address size prefix doesn't
4048 affect assembly of the next line of code. */
4049 as_warn (_("stand-alone `%s' prefix"), t->name);
4050 }
4051 }
4052
4053 /* Copy the template we found. */
4054 i.tm = *t;
539e75ad
L		 4055
4056 if (addr_prefix_disp != -1)
4057 i.tm.operand_types[addr_prefix_disp]
4058 = operand_types[addr_prefix_disp];
4059
29b0f896
AM		 4060 if (found_reverse_match)
4061 {
4062 /* If we found a reverse match we must alter the opcode
4063 direction bit. found_reverse_match holds bits to change
4064 (different for int & float insns). */
4065
4066 i.tm.base_opcode ^= found_reverse_match;
4067
539e75ad
L		 4068 i.tm.operand_types[0] = operand_types[1];
4069 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4070 }
4071
fa99fab2 4072 return t;
29b0f896
AM		 4073}
4074
4075static int
e3bb37b5 4076check_string (void)
29b0f896 4077{
40fb9820
L		 4078 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4079 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4080 {
4081 if (i.seg[0] != NULL && i.seg[0] != &es)
4082 {
a87af027 4083 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4084 i.tm.name,
a87af027
JB		 4085 mem_op + 1,
4086 register_prefix);
29b0f896
AM		 4087 return 0;
4088 }
4089 /* There's only ever one segment override allowed per instruction.
4090 This instruction possibly has a legal segment override on the
4091 second operand, so copy the segment to where non-string
4092 instructions store it, allowing common code. */
4093 i.seg[0] = i.seg[1];
4094 }
40fb9820 4095 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4096 {
4097 if (i.seg[1] != NULL && i.seg[1] != &es)
4098 {
a87af027 4099 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4100 i.tm.name,
a87af027
JB		 4101 mem_op + 2,
4102 register_prefix);
29b0f896
AM		 4103 return 0;
4104 }
4105 }
4106 return 1;
4107}
4108
4109static int
543613e9 4110process_suffix (void)
29b0f896
AM		 4111{
4112 /* If matched instruction specifies an explicit instruction mnemonic
4113 suffix, use it. */
40fb9820
L		 4114 if (i.tm.opcode_modifier.size16)
4115 i.suffix = WORD_MNEM_SUFFIX;
4116 else if (i.tm.opcode_modifier.size32)
4117 i.suffix = LONG_MNEM_SUFFIX;
4118 else if (i.tm.opcode_modifier.size64)
4119 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4120 else if (i.reg_operands)
4121 {
4122 /* If there's no instruction mnemonic suffix we try to invent one
4123 based on register operands. */
4124 if (!i.suffix)
4125 {
4126 /* We take i.suffix from the last register operand specified,
4127 Destination register type is more significant than source
381d071f
L		 4128 register type. crc32 in SSE4.2 prefers source register
4129 type. */
4130 if (i.tm.base_opcode == 0xf20f38f1)
4131 {
40fb9820
L		 4132 if (i.types[0].bitfield.reg16)
4133 i.suffix = WORD_MNEM_SUFFIX;
4134 else if (i.types[0].bitfield.reg32)
4135 i.suffix = LONG_MNEM_SUFFIX;
4136 else if (i.types[0].bitfield.reg64)
4137 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4138 }
9344ff29 4139 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4140 {
40fb9820 4141 if (i.types[0].bitfield.reg8)
20592a94
L		 4142 i.suffix = BYTE_MNEM_SUFFIX;
4143 }
381d071f
L		 4144
4145 if (!i.suffix)
4146 {
4147 int op;
4148
20592a94
L		 4149 if (i.tm.base_opcode == 0xf20f38f1
4150 || i.tm.base_opcode == 0xf20f38f0)
4151 {
4152 /* We have to know the operand size for crc32. */
4153 as_bad (_("ambiguous memory operand size for `%s`"),
4154 i.tm.name);
4155 return 0;
4156 }
4157
381d071f 4158 for (op = i.operands; --op >= 0;)
40fb9820 4159 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4160 {
40fb9820
L		 4161 if (i.types[op].bitfield.reg8)
4162 {
4163 i.suffix = BYTE_MNEM_SUFFIX;
4164 break;
4165 }
4166 else if (i.types[op].bitfield.reg16)
4167 {
4168 i.suffix = WORD_MNEM_SUFFIX;
4169 break;
4170 }
4171 else if (i.types[op].bitfield.reg32)
4172 {
4173 i.suffix = LONG_MNEM_SUFFIX;
4174 break;
4175 }
4176 else if (i.types[op].bitfield.reg64)
4177 {
4178 i.suffix = QWORD_MNEM_SUFFIX;
4179 break;
4180 }
381d071f
L		 4181 }
4182 }
29b0f896
AM		 4183 }
4184 else if (i.suffix == BYTE_MNEM_SUFFIX)
4185 {
2eb952a4
L		 4186 if (intel_syntax
4187 && i.tm.opcode_modifier.ignoresize
4188 && i.tm.opcode_modifier.no_bsuf)
4189 i.suffix = 0;
4190 else if (!check_byte_reg ())
29b0f896
AM		 4191 return 0;
4192 }
4193 else if (i.suffix == LONG_MNEM_SUFFIX)
4194 {
2eb952a4
L		 4195 if (intel_syntax
4196 && i.tm.opcode_modifier.ignoresize
4197 && i.tm.opcode_modifier.no_lsuf)
4198 i.suffix = 0;
4199 else if (!check_long_reg ())
29b0f896
AM		 4200 return 0;
4201 }
4202 else if (i.suffix == QWORD_MNEM_SUFFIX)
4203 {
955e1e6a
L		 4204 if (intel_syntax
4205 && i.tm.opcode_modifier.ignoresize
4206 && i.tm.opcode_modifier.no_qsuf)
4207 i.suffix = 0;
4208 else if (!check_qword_reg ())
29b0f896
AM		 4209 return 0;
4210 }
4211 else if (i.suffix == WORD_MNEM_SUFFIX)
4212 {
2eb952a4
L		 4213 if (intel_syntax
4214 && i.tm.opcode_modifier.ignoresize
4215 && i.tm.opcode_modifier.no_wsuf)
4216 i.suffix = 0;
4217 else if (!check_word_reg ())
29b0f896
AM		 4218 return 0;
4219 }
c0f3af97
L		 4220 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4221 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4222 {
c0f3af97 4223 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4224 should check if it is a valid suffix. */
4225 }
40fb9820 4226 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4227 /* Do nothing if the instruction is going to ignore the prefix. */
4228 ;
4229 else
4230 abort ();
4231 }
40fb9820 4232 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4233 && !i.suffix
4234 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4235 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4236 {
4237 i.suffix = stackop_size;
4238 }
9306ca4a
JB		 4239 else if (intel_syntax
4240 && !i.suffix
40fb9820
L		 4241 && (i.tm.operand_types[0].bitfield.jumpabsolute
4242 || i.tm.opcode_modifier.jumpbyte
4243 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4244 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4245 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4246 {
4247 switch (flag_code)
4248 {
4249 case CODE_64BIT:
40fb9820 4250 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4251 {
4252 i.suffix = QWORD_MNEM_SUFFIX;
4253 break;
4254 }
4255 case CODE_32BIT:
40fb9820 4256 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4257 i.suffix = LONG_MNEM_SUFFIX;
4258 break;
4259 case CODE_16BIT:
40fb9820 4260 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4261 i.suffix = WORD_MNEM_SUFFIX;
4262 break;
4263 }
4264 }
252b5132 4265
9306ca4a 4266 if (!i.suffix)
29b0f896 4267 {
9306ca4a
JB		 4268 if (!intel_syntax)
4269 {
40fb9820 4270 if (i.tm.opcode_modifier.w)
9306ca4a 4271 {
4eed87de
AM		 4272 as_bad (_("no instruction mnemonic suffix given and "
4273 "no register operands; can't size instruction"));
9306ca4a
JB		 4274 return 0;
4275 }
4276 }
4277 else
4278 {
40fb9820 4279 unsigned int suffixes;
7ab9ffdd 4280
40fb9820
L		 4281 suffixes = !i.tm.opcode_modifier.no_bsuf;
4282 if (!i.tm.opcode_modifier.no_wsuf)
4283 suffixes |= 1 << 1;
4284 if (!i.tm.opcode_modifier.no_lsuf)
4285 suffixes |= 1 << 2;
fc4adea1 4286 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4287 suffixes |= 1 << 3;
4288 if (!i.tm.opcode_modifier.no_ssuf)
4289 suffixes |= 1 << 4;
4290 if (!i.tm.opcode_modifier.no_qsuf)
4291 suffixes |= 1 << 5;
4292
4293 /* There are more than suffix matches. */
4294 if (i.tm.opcode_modifier.w
9306ca4a 4295 || ((suffixes & (suffixes - 1))
40fb9820
L		 4296 && !i.tm.opcode_modifier.defaultsize
4297 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4298 {
4299 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4300 return 0;
4301 }
4302 }
29b0f896 4303 }
252b5132 4304
9306ca4a
JB		 4305 /* Change the opcode based on the operand size given by i.suffix;
4306 We don't need to change things for byte insns. */
4307
582d5edd
L		 4308 if (i.suffix
4309 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4310 && i.suffix != XMMWORD_MNEM_SUFFIX
4311 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4312 {
4313 /* It's not a byte, select word/dword operation. */
40fb9820 4314 if (i.tm.opcode_modifier.w)
29b0f896 4315 {
40fb9820 4316 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4317 i.tm.base_opcode |= 8;
4318 else
4319 i.tm.base_opcode |= 1;
4320 }
0f3f3d8b 4321
29b0f896
AM		 4322 /* Now select between word & dword operations via the operand
4323 size prefix, except for instructions that will ignore this
4324 prefix anyway. */
ca61edf2 4325 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4326 {
ca61edf2
L		 4327 /* The address size override prefix changes the size of the
4328 first operand. */
40fb9820
L		 4329 if ((flag_code == CODE_32BIT
4330 && i.op->regs[0].reg_type.bitfield.reg16)
4331 || (flag_code != CODE_32BIT
4332 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4333 if (!add_prefix (ADDR_PREFIX_OPCODE))
4334 return 0;
4335 }
4336 else if (i.suffix != QWORD_MNEM_SUFFIX
4337 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4338 && !i.tm.opcode_modifier.ignoresize
4339 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4340 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4341 || (flag_code == CODE_64BIT
40fb9820 4342 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4343 {
4344 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4345
40fb9820 4346 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4347 prefix = ADDR_PREFIX_OPCODE;
252b5132 4348
29b0f896
AM		 4349 if (!add_prefix (prefix))
4350 return 0;
24eab124 4351 }
252b5132 4352
29b0f896
AM		 4353 /* Set mode64 for an operand. */
4354 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4355 && flag_code == CODE_64BIT
40fb9820 4356 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4357 {
4358 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4359 need rex64. cmpxchg8b is also a special case. */
4360 if (! (i.operands == 2
4361 && i.tm.base_opcode == 0x90
4362 && i.tm.extension_opcode == None
0dfbf9d7
L		 4363 && operand_type_equal (&i.types [0], &acc64)
4364 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4365 && ! (i.operands == 1
4366 && i.tm.base_opcode == 0xfc7
4367 && i.tm.extension_opcode == 1
40fb9820
L		 4368 && !operand_type_check (i.types [0], reg)
4369 && operand_type_check (i.types [0], anymem)))
f6bee062 4370 i.rex |= REX_W;
46e883c5 4371 }
3e73aa7c 4372
29b0f896
AM		 4373 /* Size floating point instruction. */
4374 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4375 if (i.tm.opcode_modifier.floatmf)
543613e9 4376 i.tm.base_opcode ^= 4;
29b0f896 4377 }
7ecd2f8b 4378
29b0f896
AM		 4379 return 1;
4380}
3e73aa7c 4381
29b0f896 4382static int
543613e9 4383check_byte_reg (void)
29b0f896
AM		 4384{
4385 int op;
543613e9 4386
29b0f896
AM		 4387 for (op = i.operands; --op >= 0;)
4388 {
4389 /* If this is an eight bit register, it's OK. If it's the 16 or
4390 32 bit version of an eight bit register, we will just use the
4391 low portion, and that's OK too. */
40fb9820 4392 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4393 continue;
4394
9344ff29
L		 4395 /* crc32 doesn't generate this warning. */
4396 if (i.tm.base_opcode == 0xf20f38f0)
4397 continue;
4398
40fb9820
L		 4399 if ((i.types[op].bitfield.reg16
4400 || i.types[op].bitfield.reg32
4401 || i.types[op].bitfield.reg64)
4402 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4403 {
4404 /* Prohibit these changes in the 64bit mode, since the
4405 lowering is more complicated. */
4406 if (flag_code == CODE_64BIT
40fb9820 4407 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4408 {
2ca3ace5
L		 4409 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4410 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4411 i.suffix);
4412 return 0;
4413 }
4414#if REGISTER_WARNINGS
4415 if (!quiet_warnings
40fb9820 4416 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4417 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4418 register_prefix,
40fb9820 4419 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4420 ? REGNAM_AL - REGNAM_AX
4421 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4422 register_prefix,
29b0f896
AM		 4423 i.op[op].regs->reg_name,
4424 i.suffix);
4425#endif
4426 continue;
4427 }
4428 /* Any other register is bad. */
40fb9820
L		 4429 if (i.types[op].bitfield.reg16
4430 || i.types[op].bitfield.reg32
4431 || i.types[op].bitfield.reg64
4432 || i.types[op].bitfield.regmmx
4433 || i.types[op].bitfield.regxmm
c0f3af97 4434 || i.types[op].bitfield.regymm
40fb9820
L		 4435 || i.types[op].bitfield.sreg2
4436 || i.types[op].bitfield.sreg3
4437 || i.types[op].bitfield.control
4438 || i.types[op].bitfield.debug
4439 || i.types[op].bitfield.test
4440 || i.types[op].bitfield.floatreg
4441 || i.types[op].bitfield.floatacc)
29b0f896 4442 {
a540244d
L		 4443 as_bad (_("`%s%s' not allowed with `%s%c'"),
4444 register_prefix,
29b0f896
AM		 4445 i.op[op].regs->reg_name,
4446 i.tm.name,
4447 i.suffix);
4448 return 0;
4449 }
4450 }
4451 return 1;
4452}
4453
4454static int
e3bb37b5 4455check_long_reg (void)
29b0f896
AM		 4456{
4457 int op;
4458
4459 for (op = i.operands; --op >= 0;)
4460 /* Reject eight bit registers, except where the template requires
4461 them. (eg. movzb) */
40fb9820
L		 4462 if (i.types[op].bitfield.reg8
4463 && (i.tm.operand_types[op].bitfield.reg16
4464 || i.tm.operand_types[op].bitfield.reg32
4465 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4466 {
a540244d
L		 4467 as_bad (_("`%s%s' not allowed with `%s%c'"),
4468 register_prefix,
29b0f896
AM		 4469 i.op[op].regs->reg_name,
4470 i.tm.name,
4471 i.suffix);
4472 return 0;
4473 }
4474 /* Warn if the e prefix on a general reg is missing. */
4475 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4476 && i.types[op].bitfield.reg16
4477 && (i.tm.operand_types[op].bitfield.reg32
4478 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4479 {
4480 /* Prohibit these changes in the 64bit mode, since the
4481 lowering is more complicated. */
4482 if (flag_code == CODE_64BIT)
252b5132 4483 {
2ca3ace5
L		 4484 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4485 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4486 i.suffix);
4487 return 0;
252b5132 4488 }
29b0f896
AM		 4489#if REGISTER_WARNINGS
4490 else
a540244d
L		 4491 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4492 register_prefix,
29b0f896 4493 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4494 register_prefix,
29b0f896
AM		 4495 i.op[op].regs->reg_name,
4496 i.suffix);
4497#endif
252b5132 4498 }
29b0f896 4499 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4500 else if (i.types[op].bitfield.reg64
4501 && (i.tm.operand_types[op].bitfield.reg32
4502 || i.tm.operand_types[op].bitfield.acc))
252b5132 4503 {
34828aad 4504 if (intel_syntax
ca61edf2 4505 && i.tm.opcode_modifier.toqword
40fb9820 4506 && !i.types[0].bitfield.regxmm)
34828aad 4507 {
ca61edf2 4508 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4509 i.suffix = QWORD_MNEM_SUFFIX;
4510 }
4511 else
4512 {
4513 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4514 register_prefix, i.op[op].regs->reg_name,
4515 i.suffix);
4516 return 0;
4517 }
29b0f896
AM		 4518 }
4519 return 1;
4520}
252b5132 4521
29b0f896 4522static int
e3bb37b5 4523check_qword_reg (void)
29b0f896
AM		 4524{
4525 int op;
252b5132 4526
29b0f896
AM		 4527 for (op = i.operands; --op >= 0; )
4528 /* Reject eight bit registers, except where the template requires
4529 them. (eg. movzb) */
40fb9820
L		 4530 if (i.types[op].bitfield.reg8
4531 && (i.tm.operand_types[op].bitfield.reg16
4532 || i.tm.operand_types[op].bitfield.reg32
4533 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4534 {
a540244d
L		 4535 as_bad (_("`%s%s' not allowed with `%s%c'"),
4536 register_prefix,
29b0f896
AM		 4537 i.op[op].regs->reg_name,
4538 i.tm.name,
4539 i.suffix);
4540 return 0;
4541 }
4542 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4543 else if ((i.types[op].bitfield.reg16
4544 || i.types[op].bitfield.reg32)
4545 && (i.tm.operand_types[op].bitfield.reg32
4546 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4547 {
4548 /* Prohibit these changes in the 64bit mode, since the
4549 lowering is more complicated. */
34828aad 4550 if (intel_syntax
ca61edf2 4551 && i.tm.opcode_modifier.todword
40fb9820 4552 && !i.types[0].bitfield.regxmm)
34828aad 4553 {
ca61edf2 4554 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4555 i.suffix = LONG_MNEM_SUFFIX;
4556 }
4557 else
4558 {
4559 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4560 register_prefix, i.op[op].regs->reg_name,
4561 i.suffix);
4562 return 0;
4563 }
252b5132 4564 }
29b0f896
AM		 4565 return 1;
4566}
252b5132 4567
29b0f896 4568static int
e3bb37b5 4569check_word_reg (void)
29b0f896
AM		 4570{
4571 int op;
4572 for (op = i.operands; --op >= 0;)
4573 /* Reject eight bit registers, except where the template requires
4574 them. (eg. movzb) */
40fb9820
L		 4575 if (i.types[op].bitfield.reg8
4576 && (i.tm.operand_types[op].bitfield.reg16
4577 || i.tm.operand_types[op].bitfield.reg32
4578 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4579 {
a540244d
L		 4580 as_bad (_("`%s%s' not allowed with `%s%c'"),
4581 register_prefix,
29b0f896
AM		 4582 i.op[op].regs->reg_name,
4583 i.tm.name,
4584 i.suffix);
4585 return 0;
4586 }
4587 /* Warn if the e prefix on a general reg is present. */
4588 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4589 && i.types[op].bitfield.reg32
4590 && (i.tm.operand_types[op].bitfield.reg16
4591 || i.tm.operand_types[op].bitfield.acc))
252b5132 4592 {
29b0f896
AM		 4593 /* Prohibit these changes in the 64bit mode, since the
4594 lowering is more complicated. */
4595 if (flag_code == CODE_64BIT)
252b5132 4596 {
2ca3ace5
L		 4597 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4598 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4599 i.suffix);
4600 return 0;
252b5132 4601 }
29b0f896
AM		 4602 else
4603#if REGISTER_WARNINGS
a540244d
L		 4604 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4605 register_prefix,
29b0f896 4606 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4607 register_prefix,
29b0f896
AM		 4608 i.op[op].regs->reg_name,
4609 i.suffix);
4610#endif
4611 }
4612 return 1;
4613}
252b5132 4614
29b0f896 4615static int
40fb9820 4616update_imm (unsigned int j)
29b0f896 4617{
bc0844ae 4618 i386_operand_type overlap = i.types[j];
40fb9820
L		 4619 if ((overlap.bitfield.imm8
4620 || overlap.bitfield.imm8s
4621 || overlap.bitfield.imm16
4622 || overlap.bitfield.imm32
4623 || overlap.bitfield.imm32s
4624 || overlap.bitfield.imm64)
0dfbf9d7
L		 4625 && !operand_type_equal (&overlap, &imm8)
4626 && !operand_type_equal (&overlap, &imm8s)
4627 && !operand_type_equal (&overlap, &imm16)
4628 && !operand_type_equal (&overlap, &imm32)
4629 && !operand_type_equal (&overlap, &imm32s)
4630 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4631 {
4632 if (i.suffix)
4633 {
40fb9820
L		 4634 i386_operand_type temp;
4635
0dfbf9d7 4636 operand_type_set (&temp, 0);
7ab9ffdd 4637 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4638 {
4639 temp.bitfield.imm8 = overlap.bitfield.imm8;
4640 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4641 }
4642 else if (i.suffix == WORD_MNEM_SUFFIX)
4643 temp.bitfield.imm16 = overlap.bitfield.imm16;
4644 else if (i.suffix == QWORD_MNEM_SUFFIX)
4645 {
4646 temp.bitfield.imm64 = overlap.bitfield.imm64;
4647 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4648 }
4649 else
4650 temp.bitfield.imm32 = overlap.bitfield.imm32;
4651 overlap = temp;
29b0f896 4652 }
0dfbf9d7
L		 4653 else if (operand_type_equal (&overlap, &imm16_32_32s)
4654 || operand_type_equal (&overlap, &imm16_32)
4655 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4656 {
40fb9820 4657 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4658 overlap = imm16;
40fb9820 4659 else
65da13b5 4660 overlap = imm32s;
29b0f896 4661 }
0dfbf9d7
L		 4662 if (!operand_type_equal (&overlap, &imm8)
4663 && !operand_type_equal (&overlap, &imm8s)
4664 && !operand_type_equal (&overlap, &imm16)
4665 && !operand_type_equal (&overlap, &imm32)
4666 && !operand_type_equal (&overlap, &imm32s)
4667 && !operand_type_equal (&overlap, &imm64))
29b0f896 4668 {
4eed87de
AM		 4669 as_bad (_("no instruction mnemonic suffix given; "
4670 "can't determine immediate size"));
29b0f896
AM		 4671 return 0;
4672 }
4673 }
40fb9820 4674 i.types[j] = overlap;
29b0f896 4675
40fb9820
L		 4676 return 1;
4677}
4678
4679static int
4680finalize_imm (void)
4681{
bc0844ae 4682 unsigned int j, n;
29b0f896 4683
bc0844ae
L		 4684 /* Update the first 2 immediate operands. */
4685 n = i.operands > 2 ? 2 : i.operands;
4686 if (n)
4687 {
4688 for (j = 0; j < n; j++)
4689 if (update_imm (j) == 0)
4690 return 0;
40fb9820 4691
bc0844ae
L		 4692 /* The 3rd operand can't be immediate operand. */
4693 gas_assert (operand_type_check (i.types[2], imm) == 0);
4694 }
29b0f896
AM		 4695
4696 return 1;
4697}
4698
c0f3af97
L		 4699static int
4700bad_implicit_operand (int xmm)
4701{
91d6fa6a
NC		 4702 const char *ireg = xmm ? "xmm0" : "ymm0";
4703
c0f3af97
L		 4704 if (intel_syntax)
4705 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 4706 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4707 else
4708 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 4709 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4710 return 0;
4711}
4712
29b0f896 4713static int
e3bb37b5 4714process_operands (void)
29b0f896
AM		 4715{
4716 /* Default segment register this instruction will use for memory
4717 accesses. 0 means unknown. This is only for optimizing out
4718 unnecessary segment overrides. */
4719 const seg_entry *default_seg = 0;
4720
2426c15f 4721 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 4722 {
91d6fa6a
NC		 4723 unsigned int dupl = i.operands;
4724 unsigned int dest = dupl - 1;
9fcfb3d7
L		 4725 unsigned int j;
4726
c0f3af97 4727 /* The destination must be an xmm register. */
9c2799c2 4728 gas_assert (i.reg_operands
91d6fa6a 4729 && MAX_OPERANDS > dupl
7ab9ffdd 4730 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4731
4732 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4733 {
c0f3af97 4734 /* The first operand is implicit and must be xmm0. */
9c2799c2 4735 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4736 if (i.op[0].regs->reg_num != 0)
4737 return bad_implicit_operand (1);
4738
8cd7925b 4739 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 4740 {
4741 /* Keep xmm0 for instructions with VEX prefix and 3
4742 sources. */
4743 goto duplicate;
4744 }
e2ec9d29 4745 else
c0f3af97
L		 4746 {
4747 /* We remove the first xmm0 and keep the number of
4748 operands unchanged, which in fact duplicates the
4749 destination. */
4750 for (j = 1; j < i.operands; j++)
4751 {
4752 i.op[j - 1] = i.op[j];
4753 i.types[j - 1] = i.types[j];
4754 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4755 }
4756 }
4757 }
4758 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 4759 {
91d6fa6a 4760 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 4761 && (i.tm.opcode_modifier.vexsources
4762 == VEX3SOURCES));
c0f3af97
L		 4763
4764 /* Add the implicit xmm0 for instructions with VEX prefix
4765 and 3 sources. */
4766 for (j = i.operands; j > 0; j--)
4767 {
4768 i.op[j] = i.op[j - 1];
4769 i.types[j] = i.types[j - 1];
4770 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4771 }
4772 i.op[0].regs
4773 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 4774 i.types[0] = regxmm;
c0f3af97
L		 4775 i.tm.operand_types[0] = regxmm;
4776
4777 i.operands += 2;
4778 i.reg_operands += 2;
4779 i.tm.operands += 2;
4780
91d6fa6a 4781 dupl++;
c0f3af97 4782 dest++;
91d6fa6a
NC		 4783 i.op[dupl] = i.op[dest];
4784 i.types[dupl] = i.types[dest];
4785 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 4786 }
c0f3af97
L		 4787 else
4788 {
4789duplicate:
4790 i.operands++;
4791 i.reg_operands++;
4792 i.tm.operands++;
4793
91d6fa6a
NC		 4794 i.op[dupl] = i.op[dest];
4795 i.types[dupl] = i.types[dest];
4796 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 4797 }
4798
4799 if (i.tm.opcode_modifier.immext)
4800 process_immext ();
4801 }
4802 else if (i.tm.opcode_modifier.firstxmm0)
4803 {
4804 unsigned int j;
4805
4806 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 4807 gas_assert (i.reg_operands
7ab9ffdd
L		 4808 && (operand_type_equal (&i.types[0], &regxmm)
4809 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 4810 if (i.op[0].regs->reg_num != 0)
4811 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4812
4813 for (j = 1; j < i.operands; j++)
4814 {
4815 i.op[j - 1] = i.op[j];
4816 i.types[j - 1] = i.types[j];
4817
4818 /* We need to adjust fields in i.tm since they are used by
4819 build_modrm_byte. */
4820 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4821 }
4822
e2ec9d29
L		 4823 i.operands--;
4824 i.reg_operands--;
e2ec9d29
L		 4825 i.tm.operands--;
4826 }
4827 else if (i.tm.opcode_modifier.regkludge)
4828 {
4829 /* The imul $imm, %reg instruction is converted into
4830 imul $imm, %reg, %reg, and the clr %reg instruction
4831 is converted into xor %reg, %reg. */
4832
4833 unsigned int first_reg_op;
4834
4835 if (operand_type_check (i.types[0], reg))
4836 first_reg_op = 0;
4837 else
4838 first_reg_op = 1;
4839 /* Pretend we saw the extra register operand. */
9c2799c2 4840 gas_assert (i.reg_operands == 1
7ab9ffdd 4841 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 4842 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4843 i.types[first_reg_op + 1] = i.types[first_reg_op];
4844 i.operands++;
4845 i.reg_operands++;
29b0f896
AM		 4846 }
4847
40fb9820 4848 if (i.tm.opcode_modifier.shortform)
29b0f896 4849 {
40fb9820
L		 4850 if (i.types[0].bitfield.sreg2
4851 || i.types[0].bitfield.sreg3)
29b0f896 4852 {
4eed87de
AM		 4853 if (i.tm.base_opcode == POP_SEG_SHORT
4854 && i.op[0].regs->reg_num == 1)
29b0f896 4855 {
a87af027 4856 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 4857 return 0;
29b0f896 4858 }
4eed87de
AM		 4859 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4860 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4861 i.rex |= REX_B;
4eed87de
AM		 4862 }
4863 else
4864 {
7ab9ffdd 4865 /* The register or float register operand is in operand
85f10a01 4866 0 or 1. */
40fb9820 4867 unsigned int op;
7ab9ffdd
L		 4868
4869 if (i.types[0].bitfield.floatreg
4870 || operand_type_check (i.types[0], reg))
4871 op = 0;
4872 else
4873 op = 1;
4eed87de
AM		 4874 /* Register goes in low 3 bits of opcode. */
4875 i.tm.base_opcode |= i.op[op].regs->reg_num;
4876 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4877 i.rex |= REX_B;
40fb9820 4878 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4879 {
4eed87de
AM		 4880 /* Warn about some common errors, but press on regardless.
4881 The first case can be generated by gcc (<= 2.8.1). */
4882 if (i.operands == 2)
4883 {
4884 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 4885 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 4886 register_prefix, i.op[!intel_syntax].regs->reg_name,
4887 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 4888 }
4889 else
4890 {
4891 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4892 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4893 register_prefix, i.op[0].regs->reg_name);
4eed87de 4894 }
29b0f896
AM		 4895 }
4896 }
4897 }
40fb9820 4898 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4899 {
4900 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4901 must be put into the modrm byte). Now, we make the modrm and
4902 index base bytes based on all the info we've collected. */
29b0f896
AM		 4903
4904 default_seg = build_modrm_byte ();
4905 }
8a2ed489 4906 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4907 {
4908 default_seg = &ds;
4909 }
40fb9820 4910 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4911 {
4912 /* For the string instructions that allow a segment override
4913 on one of their operands, the default segment is ds. */
4914 default_seg = &ds;
4915 }
4916
75178d9d
L		 4917 if (i.tm.base_opcode == 0x8d /* lea */
4918 && i.seg[0]
4919 && !quiet_warnings)
30123838 4920 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4921
4922 /* If a segment was explicitly specified, and the specified segment
4923 is not the default, use an opcode prefix to select it. If we
4924 never figured out what the default segment is, then default_seg
4925 will be zero at this point, and the specified segment prefix will
4926 always be used. */
29b0f896
AM		 4927 if ((i.seg[0]) && (i.seg[0] != default_seg))
4928 {
4929 if (!add_prefix (i.seg[0]->seg_prefix))
4930 return 0;
4931 }
4932 return 1;
4933}
4934
4935static const seg_entry *
e3bb37b5 4936build_modrm_byte (void)
29b0f896
AM		 4937{
4938 const seg_entry *default_seg = 0;
c0f3af97 4939 unsigned int source, dest;
8cd7925b 4940 int vex_3_sources;
c0f3af97
L		 4941
4942 /* The first operand of instructions with VEX prefix and 3 sources
4943 must be VEX_Imm4. */
8cd7925b 4944 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 4945 if (vex_3_sources)
4946 {
91d6fa6a 4947 unsigned int nds, reg_slot;
4c2c6516 4948 expressionS *exp;
c0f3af97 4949
922d8de8
DR		 4950 if (i.tm.opcode_modifier.veximmext
4951 && i.tm.opcode_modifier.immext)
4952 {
4953 dest = i.operands - 2;
4954 gas_assert (dest == 3);
4955 }
4956 else
91d6fa6a 4957 dest = i.operands - 1;
c0f3af97 4958 nds = dest - 1;
922d8de8 4959
76ba9986
L		 4960 /* This instruction must have 4 register operands
4961 or 3 register operands plus 1 memory operand.
922d8de8
DR		 4962 It must have VexNDS and VexImmExt. */
4963 gas_assert ((i.reg_operands == 4
7ab9ffdd 4964 || (i.reg_operands == 3 && i.mem_operands == 1))
2426c15f 4965 && i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 4966 && i.tm.opcode_modifier.veximmext
922d8de8
DR		 4967 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
4968 || operand_type_equal (&i.tm.operand_types[dest], &regymm)));
c0f3af97 4969
0bfee649
L		 4970 /* Generate an 8bit immediate operand to encode the register
4971 operand. */
4c2c6516 4972 exp = &im_expressions[i.imm_operands++];
0bfee649
L		 4973 i.op[i.operands].imms = exp;
4974 i.types[i.operands] = imm8;
4975 i.operands++;
922d8de8
DR		 4976 /* If VexW1 is set, the first operand is the source and
4977 the second operand is encoded in the immediate operand. */
1ef99a7b 4978 if (i.tm.opcode_modifier.vexw == VEXW1)
922d8de8
DR		 4979 {
4980 source = 0;
91d6fa6a 4981 reg_slot = 1;
922d8de8
DR		 4982 }
4983 else
4984 {
4985 source = 1;
91d6fa6a 4986 reg_slot = 0;
76ba9986 4987 }
91d6fa6a
NC		 4988 gas_assert ((operand_type_equal (&i.tm.operand_types[reg_slot], &regxmm)
4989 || operand_type_equal (&i.tm.operand_types[reg_slot],
76ba9986 4990 &regymm))
922d8de8 4991 && (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
76ba9986 4992 || operand_type_equal (&i.tm.operand_types[nds],
922d8de8 4993 &regymm)));
0bfee649
L		 4994 exp->X_op = O_constant;
4995 exp->X_add_number
91d6fa6a
NC		 4996 = ((i.op[reg_slot].regs->reg_num
4997 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
dae39acc 4998 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 4999 }
5000 else
5001 source = dest = 0;
29b0f896
AM		 5002
5003 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5004 implicit registers do not count. If there are 3 register
5005 operands, it must be a instruction with VexNDS. For a
5006 instruction with VexNDD, the destination register is encoded
5007 in VEX prefix. If there are 4 register operands, it must be
5008 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5009 if (i.mem_operands == 0
5010 && ((i.reg_operands == 2
2426c15f 5011 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5012 || (i.reg_operands == 3
2426c15f 5013 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5014 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5015 {
cab737b9
L		 5016 switch (i.operands)
5017 {
5018 case 2:
5019 source = 0;
5020 break;
5021 case 3:
c81128dc
L		 5022 /* When there are 3 operands, one of them may be immediate,
5023 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5024 the first operand must be shift count register (cl) or it
5025 is an instruction with VexNDS. */
9c2799c2 5026 gas_assert (i.imm_operands == 1
7ab9ffdd 5027 || (i.imm_operands == 0
2426c15f 5028 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 5029 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5030 if (operand_type_check (i.types[0], imm)
5031 || i.types[0].bitfield.shiftcount)
5032 source = 1;
5033 else
5034 source = 0;
cab737b9
L		 5035 break;
5036 case 4:
368d64cc
L		 5037 /* When there are 4 operands, the first two must be 8bit
5038 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5039 one.
5040
5041 For instructions with VexNDS, if the first operand
5042 an imm8, the source operand is the 2nd one. If the last
5043 operand is imm8, the source operand is the first one. */
9c2799c2 5044 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5045 && i.types[0].bitfield.imm8
5046 && i.types[1].bitfield.imm8)
2426c15f 5047 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 5048 && i.imm_operands == 1
5049 && (i.types[0].bitfield.imm8
5050 || i.types[i.operands - 1].bitfield.imm8)));
2426c15f 5051 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5052 {
5053 if (i.types[0].bitfield.imm8)
5054 source = 1;
5055 else
5056 source = 0;
5057 }
5058 else
5059 source = 2;
5060 break;
5061 case 5:
cab737b9
L		 5062 break;
5063 default:
5064 abort ();
5065 }
5066
c0f3af97
L		 5067 if (!vex_3_sources)
5068 {
5069 dest = source + 1;
5070
2426c15f 5071 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5072 {
5073 /* For instructions with VexNDS, the register-only
5074 source operand must be XMM or YMM register. It is
fa99fab2
L		 5075 encoded in VEX prefix. We need to clear RegMem bit
5076 before calling operand_type_equal. */
5077 i386_operand_type op = i.tm.operand_types[dest];
5078 op.bitfield.regmem = 0;
c0f3af97 5079 if ((dest + 1) >= i.operands
fa99fab2
L		 5080 || (!operand_type_equal (&op, &regxmm)
5081 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 5082 abort ();
5083 i.vex.register_specifier = i.op[dest].regs;
5084 dest++;
5085 }
5086 }
29b0f896
AM		 5087
5088 i.rm.mode = 3;
5089 /* One of the register operands will be encoded in the i.tm.reg
5090 field, the other in the combined i.tm.mode and i.tm.regmem
5091 fields. If no form of this instruction supports a memory
5092 destination operand, then we assume the source operand may
5093 sometimes be a memory operand and so we need to store the
5094 destination in the i.rm.reg field. */
40fb9820
L		 5095 if (!i.tm.operand_types[dest].bitfield.regmem
5096 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5097 {
5098 i.rm.reg = i.op[dest].regs->reg_num;
5099 i.rm.regmem = i.op[source].regs->reg_num;
5100 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5101 i.rex |= REX_R;
29b0f896 5102 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5103 i.rex |= REX_B;
29b0f896
AM		 5104 }
5105 else
5106 {
5107 i.rm.reg = i.op[source].regs->reg_num;
5108 i.rm.regmem = i.op[dest].regs->reg_num;
5109 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5110 i.rex |= REX_B;
29b0f896 5111 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5112 i.rex |= REX_R;
29b0f896 5113 }
161a04f6 5114 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5115 {
40fb9820
L		 5116 if (!i.types[0].bitfield.control
5117 && !i.types[1].bitfield.control)
c4a530c5 5118 abort ();
161a04f6 5119 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5120 add_prefix (LOCK_PREFIX_OPCODE);
5121 }
29b0f896
AM		 5122 }
5123 else
5124 { /* If it's not 2 reg operands... */
c0f3af97
L		 5125 unsigned int mem;
5126
29b0f896
AM		 5127 if (i.mem_operands)
5128 {
5129 unsigned int fake_zero_displacement = 0;
99018f42 5130 unsigned int op;
4eed87de 5131
7ab9ffdd
L		 5132 for (op = 0; op < i.operands; op++)
5133 if (operand_type_check (i.types[op], anymem))
5134 break;
7ab9ffdd 5135 gas_assert (op < i.operands);
29b0f896
AM		 5136
5137 default_seg = &ds;
5138
5139 if (i.base_reg == 0)
5140 {
5141 i.rm.mode = 0;
5142 if (!i.disp_operands)
5143 fake_zero_displacement = 1;
5144 if (i.index_reg == 0)
5145 {
5146 /* Operand is just <disp> */
20f0a1fc 5147 if (flag_code == CODE_64BIT)
29b0f896
AM		 5148 {
5149 /* 64bit mode overwrites the 32bit absolute
5150 addressing by RIP relative addressing and
5151 absolute addressing is encoded by one of the
5152 redundant SIB forms. */
5153 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5154 i.sib.base = NO_BASE_REGISTER;
5155 i.sib.index = NO_INDEX_REGISTER;
fc225355 5156 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5157 ? disp32s : disp32);
20f0a1fc 5158 }
fc225355
L		 5159 else if ((flag_code == CODE_16BIT)
5160 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5161 {
5162 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5163 i.types[op] = disp16;
20f0a1fc
NC		 5164 }
5165 else
5166 {
5167 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5168 i.types[op] = disp32;
29b0f896
AM		 5169 }
5170 }
5171 else /* !i.base_reg && i.index_reg */
5172 {
db51cc60
L		 5173 if (i.index_reg->reg_num == RegEiz
5174 || i.index_reg->reg_num == RegRiz)
5175 i.sib.index = NO_INDEX_REGISTER;
5176 else
5177 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5178 i.sib.base = NO_BASE_REGISTER;
5179 i.sib.scale = i.log2_scale_factor;
5180 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5181 i.types[op].bitfield.disp8 = 0;
5182 i.types[op].bitfield.disp16 = 0;
5183 i.types[op].bitfield.disp64 = 0;
29b0f896 5184 if (flag_code != CODE_64BIT)
40fb9820
L		 5185 {
5186 /* Must be 32 bit */
5187 i.types[op].bitfield.disp32 = 1;
5188 i.types[op].bitfield.disp32s = 0;
5189 }
29b0f896 5190 else
40fb9820
L		 5191 {
5192 i.types[op].bitfield.disp32 = 0;
5193 i.types[op].bitfield.disp32s = 1;
5194 }
29b0f896 5195 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5196 i.rex |= REX_X;
29b0f896
AM		 5197 }
5198 }
5199 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5200 else if (i.base_reg->reg_num == RegRip ||
5201 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5202 {
5203 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5204 i.types[op].bitfield.disp8 = 0;
5205 i.types[op].bitfield.disp16 = 0;
5206 i.types[op].bitfield.disp32 = 0;
5207 i.types[op].bitfield.disp32s = 1;
5208 i.types[op].bitfield.disp64 = 0;
71903a11 5209 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5210 if (! i.disp_operands)
5211 fake_zero_displacement = 1;
29b0f896 5212 }
40fb9820 5213 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5214 {
5215 switch (i.base_reg->reg_num)
5216 {
5217 case 3: /* (%bx) */
5218 if (i.index_reg == 0)
5219 i.rm.regmem = 7;
5220 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5221 i.rm.regmem = i.index_reg->reg_num - 6;
5222 break;
5223 case 5: /* (%bp) */
5224 default_seg = &ss;
5225 if (i.index_reg == 0)
5226 {
5227 i.rm.regmem = 6;
40fb9820 5228 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5229 {
5230 /* fake (%bp) into 0(%bp) */
40fb9820 5231 i.types[op].bitfield.disp8 = 1;
252b5132 5232 fake_zero_displacement = 1;
29b0f896
AM		 5233 }
5234 }
5235 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5236 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5237 break;
5238 default: /* (%si) -> 4 or (%di) -> 5 */
5239 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5240 }
5241 i.rm.mode = mode_from_disp_size (i.types[op]);
5242 }
5243 else /* i.base_reg and 32/64 bit mode */
5244 {
5245 if (flag_code == CODE_64BIT
40fb9820
L		 5246 && operand_type_check (i.types[op], disp))
5247 {
5248 i386_operand_type temp;
0dfbf9d7 5249 operand_type_set (&temp, 0);
40fb9820
L		 5250 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5251 i.types[op] = temp;
5252 if (i.prefix[ADDR_PREFIX] == 0)
5253 i.types[op].bitfield.disp32s = 1;
5254 else
5255 i.types[op].bitfield.disp32 = 1;
5256 }
20f0a1fc 5257
29b0f896
AM		 5258 i.rm.regmem = i.base_reg->reg_num;
5259 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5260 i.rex |= REX_B;
29b0f896
AM		 5261 i.sib.base = i.base_reg->reg_num;
5262 /* x86-64 ignores REX prefix bit here to avoid decoder
5263 complications. */
5264 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5265 {
5266 default_seg = &ss;
5267 if (i.disp_operands == 0)
5268 {
5269 fake_zero_displacement = 1;
40fb9820 5270 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5271 }
5272 }
5273 else if (i.base_reg->reg_num == ESP_REG_NUM)
5274 {
5275 default_seg = &ss;
5276 }
5277 i.sib.scale = i.log2_scale_factor;
5278 if (i.index_reg == 0)
5279 {
5280 /* <disp>(%esp) becomes two byte modrm with no index
5281 register. We've already stored the code for esp
5282 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5283 Any base register besides %esp will not use the
5284 extra modrm byte. */
5285 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5286 }
5287 else
5288 {
db51cc60
L		 5289 if (i.index_reg->reg_num == RegEiz
5290 || i.index_reg->reg_num == RegRiz)
5291 i.sib.index = NO_INDEX_REGISTER;
5292 else
5293 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5294 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5295 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5296 i.rex |= REX_X;
29b0f896 5297 }
67a4f2b7
AO		 5298
5299 if (i.disp_operands
5300 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5301 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5302 i.rm.mode = 0;
5303 else
5304 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5305 }
252b5132 5306
29b0f896
AM		 5307 if (fake_zero_displacement)
5308 {
5309 /* Fakes a zero displacement assuming that i.types[op]
5310 holds the correct displacement size. */
5311 expressionS *exp;
5312
9c2799c2 5313 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5314 exp = &disp_expressions[i.disp_operands++];
5315 i.op[op].disps = exp;
5316 exp->X_op = O_constant;
5317 exp->X_add_number = 0;
5318 exp->X_add_symbol = (symbolS *) 0;
5319 exp->X_op_symbol = (symbolS *) 0;
5320 }
c0f3af97
L		 5321
5322 mem = op;
29b0f896 5323 }
c0f3af97
L		 5324 else
5325 mem = ~0;
252b5132 5326
8c43a48b 5327 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5328 {
5329 if (operand_type_check (i.types[0], imm))
5330 i.vex.register_specifier = NULL;
5331 else
5332 {
5333 /* VEX.vvvv encodes one of the sources when the first
5334 operand is not an immediate. */
1ef99a7b 5335 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5336 i.vex.register_specifier = i.op[0].regs;
5337 else
5338 i.vex.register_specifier = i.op[1].regs;
5339 }
5340
5341 /* Destination is a XMM register encoded in the ModRM.reg
5342 and VEX.R bit. */
5343 i.rm.reg = i.op[2].regs->reg_num;
5344 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5345 i.rex |= REX_R;
5346
5347 /* ModRM.rm and VEX.B encodes the other source. */
5348 if (!i.mem_operands)
5349 {
5350 i.rm.mode = 3;
5351
1ef99a7b 5352 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5353 i.rm.regmem = i.op[1].regs->reg_num;
5354 else
5355 i.rm.regmem = i.op[0].regs->reg_num;
5356
5357 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5358 i.rex |= REX_B;
5359 }
5360 }
2426c15f 5361 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 5362 {
5363 i.vex.register_specifier = i.op[2].regs;
5364 if (!i.mem_operands)
5365 {
5366 i.rm.mode = 3;
5367 i.rm.regmem = i.op[1].regs->reg_num;
5368 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5369 i.rex |= REX_B;
5370 }
5371 }
29b0f896
AM		 5372 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5373 (if any) based on i.tm.extension_opcode. Again, we must be
5374 careful to make sure that segment/control/debug/test/MMX
5375 registers are coded into the i.rm.reg field. */
f88c9eb0 5376 else if (i.reg_operands)
29b0f896 5377 {
99018f42 5378 unsigned int op;
7ab9ffdd
L		 5379 unsigned int vex_reg = ~0;
5380
5381 for (op = 0; op < i.operands; op++)
5382 if (i.types[op].bitfield.reg8
5383 || i.types[op].bitfield.reg16
5384 || i.types[op].bitfield.reg32
5385 || i.types[op].bitfield.reg64
5386 || i.types[op].bitfield.regmmx
5387 || i.types[op].bitfield.regxmm
5388 || i.types[op].bitfield.regymm
5389 || i.types[op].bitfield.sreg2
5390 || i.types[op].bitfield.sreg3
5391 || i.types[op].bitfield.control
5392 || i.types[op].bitfield.debug
5393 || i.types[op].bitfield.test)
5394 break;
c0209578 5395
7ab9ffdd
L		 5396 if (vex_3_sources)
5397 op = dest;
2426c15f 5398 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 5399 {
5400 /* For instructions with VexNDS, the register-only
5401 source operand is encoded in VEX prefix. */
5402 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5403
7ab9ffdd 5404 if (op > mem)
c0f3af97 5405 {
7ab9ffdd
L		 5406 vex_reg = op++;
5407 gas_assert (op < i.operands);
c0f3af97
L		 5408 }
5409 else
c0f3af97 5410 {
7ab9ffdd
L		 5411 vex_reg = op + 1;
5412 gas_assert (vex_reg < i.operands);
c0f3af97 5413 }
7ab9ffdd 5414 }
2426c15f 5415 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd
L		 5416 {
5417 /* For instructions with VexNDD, there should be
5418 no memory operand and the register destination
5419 is encoded in VEX prefix. */
5420 gas_assert (i.mem_operands == 0
5421 && (op + 2) == i.operands);
5422 vex_reg = op + 1;
5423 }
5424 else
5425 gas_assert (op < i.operands);
99018f42 5426
7ab9ffdd
L		 5427 if (vex_reg != (unsigned int) ~0)
5428 {
5429 gas_assert (i.reg_operands == 2);
5430
5431 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
76ba9986 5432 &regxmm)
7ab9ffdd
L		 5433 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5434 &regymm))
5435 abort ();
f88c9eb0 5436
7ab9ffdd
L		 5437 i.vex.register_specifier = i.op[vex_reg].regs;
5438 }
5439
1b9f0c97
L		 5440 /* Don't set OP operand twice. */
5441 if (vex_reg != op)
7ab9ffdd 5442 {
1b9f0c97
L		 5443 /* If there is an extension opcode to put here, the
5444 register number must be put into the regmem field. */
5445 if (i.tm.extension_opcode != None)
5446 {
5447 i.rm.regmem = i.op[op].regs->reg_num;
5448 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5449 i.rex |= REX_B;
5450 }
5451 else
5452 {
5453 i.rm.reg = i.op[op].regs->reg_num;
5454 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5455 i.rex |= REX_R;
5456 }
7ab9ffdd 5457 }
252b5132 5458
29b0f896
AM		 5459 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5460 must set it to 3 to indicate this is a register operand
5461 in the regmem field. */
5462 if (!i.mem_operands)
5463 i.rm.mode = 3;
5464 }
252b5132 5465
29b0f896 5466 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5467 if (i.tm.extension_opcode != None)
29b0f896
AM		 5468 i.rm.reg = i.tm.extension_opcode;
5469 }
5470 return default_seg;
5471}
252b5132 5472
29b0f896 5473static void
e3bb37b5 5474output_branch (void)
29b0f896
AM		 5475{
5476 char *p;
5477 int code16;
5478 int prefix;
5479 relax_substateT subtype;
5480 symbolS *sym;
5481 offsetT off;
5482
5483 code16 = 0;
5484 if (flag_code == CODE_16BIT)
5485 code16 = CODE16;
5486
5487 prefix = 0;
5488 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5489 {
29b0f896
AM		 5490 prefix = 1;
5491 i.prefixes -= 1;
5492 code16 ^= CODE16;
252b5132 5493 }
29b0f896
AM		 5494 /* Pentium4 branch hints. */
5495 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5496 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5497 {
29b0f896
AM		 5498 prefix++;
5499 i.prefixes--;
5500 }
5501 if (i.prefix[REX_PREFIX] != 0)
5502 {
5503 prefix++;
5504 i.prefixes--;
2f66722d
AM		 5505 }
5506
29b0f896
AM		 5507 if (i.prefixes != 0 && !intel_syntax)
5508 as_warn (_("skipping prefixes on this instruction"));
5509
5510 /* It's always a symbol; End frag & setup for relax.
5511 Make sure there is enough room in this frag for the largest
5512 instruction we may generate in md_convert_frag. This is 2
5513 bytes for the opcode and room for the prefix and largest
5514 displacement. */
5515 frag_grow (prefix + 2 + 4);
5516 /* Prefix and 1 opcode byte go in fr_fix. */
5517 p = frag_more (prefix + 1);
5518 if (i.prefix[DATA_PREFIX] != 0)
5519 *p++ = DATA_PREFIX_OPCODE;
5520 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5521 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5522 *p++ = i.prefix[SEG_PREFIX];
5523 if (i.prefix[REX_PREFIX] != 0)
5524 *p++ = i.prefix[REX_PREFIX];
5525 *p = i.tm.base_opcode;
5526
5527 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5528 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5529 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5530 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5531 else
5532 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5533 subtype |= code16;
3e73aa7c 5534
29b0f896
AM		 5535 sym = i.op[0].disps->X_add_symbol;
5536 off = i.op[0].disps->X_add_number;
3e73aa7c 5537
29b0f896
AM		 5538 if (i.op[0].disps->X_op != O_constant
5539 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5540 {
29b0f896
AM		 5541 /* Handle complex expressions. */
5542 sym = make_expr_symbol (i.op[0].disps);
5543 off = 0;
5544 }
3e73aa7c 5545
29b0f896
AM		 5546 /* 1 possible extra opcode + 4 byte displacement go in var part.
5547 Pass reloc in fr_var. */
5548 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5549}
3e73aa7c 5550
29b0f896 5551static void
e3bb37b5 5552output_jump (void)
29b0f896
AM		 5553{
5554 char *p;
5555 int size;
3e02c1cc 5556 fixS *fixP;
29b0f896 5557
40fb9820 5558 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5559 {
5560 /* This is a loop or jecxz type instruction. */
5561 size = 1;
5562 if (i.prefix[ADDR_PREFIX] != 0)
5563 {
5564 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5565 i.prefixes -= 1;
5566 }
5567 /* Pentium4 branch hints. */
5568 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5569 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5570 {
5571 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5572 i.prefixes--;
3e73aa7c
JH		 5573 }
5574 }
29b0f896
AM		 5575 else
5576 {
5577 int code16;
3e73aa7c 5578
29b0f896
AM		 5579 code16 = 0;
5580 if (flag_code == CODE_16BIT)
5581 code16 = CODE16;
3e73aa7c 5582
29b0f896
AM		 5583 if (i.prefix[DATA_PREFIX] != 0)
5584 {
5585 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5586 i.prefixes -= 1;
5587 code16 ^= CODE16;
5588 }
252b5132 5589
29b0f896
AM		 5590 size = 4;
5591 if (code16)
5592 size = 2;
5593 }
9fcc94b6 5594
29b0f896
AM		 5595 if (i.prefix[REX_PREFIX] != 0)
5596 {
5597 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5598 i.prefixes -= 1;
5599 }
252b5132 5600
29b0f896
AM		 5601 if (i.prefixes != 0 && !intel_syntax)
5602 as_warn (_("skipping prefixes on this instruction"));
e0890092 5603
29b0f896
AM		 5604 p = frag_more (1 + size);
5605 *p++ = i.tm.base_opcode;
e0890092 5606
3e02c1cc
AM		 5607 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5608 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5609
5610 /* All jumps handled here are signed, but don't use a signed limit
5611 check for 32 and 16 bit jumps as we want to allow wrap around at
5612 4G and 64k respectively. */
5613 if (size == 1)
5614 fixP->fx_signed = 1;
29b0f896 5615}
e0890092 5616
29b0f896 5617static void
e3bb37b5 5618output_interseg_jump (void)
29b0f896
AM		 5619{
5620 char *p;
5621 int size;
5622 int prefix;
5623 int code16;
252b5132 5624
29b0f896
AM		 5625 code16 = 0;
5626 if (flag_code == CODE_16BIT)
5627 code16 = CODE16;
a217f122 5628
29b0f896
AM		 5629 prefix = 0;
5630 if (i.prefix[DATA_PREFIX] != 0)
5631 {
5632 prefix = 1;
5633 i.prefixes -= 1;
5634 code16 ^= CODE16;
5635 }
5636 if (i.prefix[REX_PREFIX] != 0)
5637 {
5638 prefix++;
5639 i.prefixes -= 1;
5640 }
252b5132 5641
29b0f896
AM		 5642 size = 4;
5643 if (code16)
5644 size = 2;
252b5132 5645
29b0f896
AM		 5646 if (i.prefixes != 0 && !intel_syntax)
5647 as_warn (_("skipping prefixes on this instruction"));
252b5132 5648
29b0f896
AM		 5649 /* 1 opcode; 2 segment; offset */
5650 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5651
29b0f896
AM		 5652 if (i.prefix[DATA_PREFIX] != 0)
5653 *p++ = DATA_PREFIX_OPCODE;
252b5132 5654
29b0f896
AM		 5655 if (i.prefix[REX_PREFIX] != 0)
5656 *p++ = i.prefix[REX_PREFIX];
252b5132 5657
29b0f896
AM		 5658 *p++ = i.tm.base_opcode;
5659 if (i.op[1].imms->X_op == O_constant)
5660 {
5661 offsetT n = i.op[1].imms->X_add_number;
252b5132 5662
29b0f896
AM		 5663 if (size == 2
5664 && !fits_in_unsigned_word (n)
5665 && !fits_in_signed_word (n))
5666 {
5667 as_bad (_("16-bit jump out of range"));
5668 return;
5669 }
5670 md_number_to_chars (p, n, size);
5671 }
5672 else
5673 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5674 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5675 if (i.op[0].imms->X_op != O_constant)
5676 as_bad (_("can't handle non absolute segment in `%s'"),
5677 i.tm.name);
5678 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5679}
a217f122 5680
29b0f896 5681static void
e3bb37b5 5682output_insn (void)
29b0f896 5683{
2bbd9c25
JJ		 5684 fragS *insn_start_frag;
5685 offsetT insn_start_off;
5686
29b0f896
AM		 5687 /* Tie dwarf2 debug info to the address at the start of the insn.
5688 We can't do this after the insn has been output as the current
5689 frag may have been closed off. eg. by frag_var. */
5690 dwarf2_emit_insn (0);
5691
2bbd9c25
JJ		 5692 insn_start_frag = frag_now;
5693 insn_start_off = frag_now_fix ();
5694
29b0f896 5695 /* Output jumps. */
40fb9820 5696 if (i.tm.opcode_modifier.jump)
29b0f896 5697 output_branch ();
40fb9820
L		 5698 else if (i.tm.opcode_modifier.jumpbyte
5699 || i.tm.opcode_modifier.jumpdword)
29b0f896 5700 output_jump ();
40fb9820 5701 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5702 output_interseg_jump ();
5703 else
5704 {
5705 /* Output normal instructions here. */
5706 char *p;
5707 unsigned char *q;
47465058 5708 unsigned int j;
331d2d0d 5709 unsigned int prefix;
4dffcebc 5710
c0f3af97
L		 5711 /* Since the VEX prefix contains the implicit prefix, we don't
5712 need the explicit prefix. */
5713 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5714 {
c0f3af97 5715 switch (i.tm.opcode_length)
bc4bd9ab 5716 {
c0f3af97
L		 5717 case 3:
5718 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5719 {
c0f3af97
L		 5720 prefix = (i.tm.base_opcode >> 24) & 0xff;
5721 goto check_prefix;
5722 }
5723 break;
5724 case 2:
5725 if ((i.tm.base_opcode & 0xff0000) != 0)
5726 {
5727 prefix = (i.tm.base_opcode >> 16) & 0xff;
5728 if (i.tm.cpu_flags.bitfield.cpupadlock)
5729 {
4dffcebc 5730check_prefix:
c0f3af97 5731 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 5732 || (i.prefix[REP_PREFIX]
c0f3af97
L		 5733 != REPE_PREFIX_OPCODE))
5734 add_prefix (prefix);
5735 }
5736 else
4dffcebc
L		 5737 add_prefix (prefix);
5738 }
c0f3af97
L		 5739 break;
5740 case 1:
5741 break;
5742 default:
5743 abort ();
bc4bd9ab 5744 }
c0f3af97
L		 5745
5746 /* The prefix bytes. */
5747 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5748 if (*q)
5749 FRAG_APPEND_1_CHAR (*q);
0f10071e 5750 }
252b5132 5751
c0f3af97
L		 5752 if (i.tm.opcode_modifier.vex)
5753 {
5754 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5755 if (*q)
5756 switch (j)
5757 {
5758 case REX_PREFIX:
5759 /* REX byte is encoded in VEX prefix. */
5760 break;
5761 case SEG_PREFIX:
5762 case ADDR_PREFIX:
5763 FRAG_APPEND_1_CHAR (*q);
5764 break;
5765 default:
5766 /* There should be no other prefixes for instructions
5767 with VEX prefix. */
5768 abort ();
5769 }
5770
5771 /* Now the VEX prefix. */
5772 p = frag_more (i.vex.length);
5773 for (j = 0; j < i.vex.length; j++)
5774 p[j] = i.vex.bytes[j];
5775 }
252b5132 5776
29b0f896 5777 /* Now the opcode; be careful about word order here! */
4dffcebc 5778 if (i.tm.opcode_length == 1)
29b0f896
AM		 5779 {
5780 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5781 }
5782 else
5783 {
4dffcebc 5784 switch (i.tm.opcode_length)
331d2d0d 5785 {
4dffcebc 5786 case 3:
331d2d0d
L		 5787 p = frag_more (3);
5788 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5789 break;
5790 case 2:
5791 p = frag_more (2);
5792 break;
5793 default:
5794 abort ();
5795 break;
331d2d0d 5796 }
0f10071e 5797
29b0f896
AM		 5798 /* Put out high byte first: can't use md_number_to_chars! */
5799 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5800 *p = i.tm.base_opcode & 0xff;
5801 }
3e73aa7c 5802
29b0f896 5803 /* Now the modrm byte and sib byte (if present). */
40fb9820 5804 if (i.tm.opcode_modifier.modrm)
29b0f896 5805 {
4a3523fa
L		 5806 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5807 | i.rm.reg << 3
5808 | i.rm.mode << 6));
29b0f896
AM		 5809 /* If i.rm.regmem == ESP (4)
5810 && i.rm.mode != (Register mode)
5811 && not 16 bit
5812 ==> need second modrm byte. */
5813 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5814 && i.rm.mode != 3
40fb9820 5815 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5816 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5817 | i.sib.index << 3
5818 | i.sib.scale << 6));
29b0f896 5819 }
3e73aa7c 5820
29b0f896 5821 if (i.disp_operands)
2bbd9c25 5822 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5823
29b0f896 5824 if (i.imm_operands)
2bbd9c25 5825 output_imm (insn_start_frag, insn_start_off);
29b0f896 5826 }
252b5132 5827
29b0f896
AM		 5828#ifdef DEBUG386
5829 if (flag_debug)
5830 {
7b81dfbb 5831 pi ("" /*line*/, &i);
29b0f896
AM		 5832 }
5833#endif /* DEBUG386 */
5834}
252b5132 5835
e205caa7
L		 5836/* Return the size of the displacement operand N. */
5837
5838static int
5839disp_size (unsigned int n)
5840{
5841 int size = 4;
40fb9820
L		 5842 if (i.types[n].bitfield.disp64)
5843 size = 8;
5844 else if (i.types[n].bitfield.disp8)
5845 size = 1;
5846 else if (i.types[n].bitfield.disp16)
5847 size = 2;
e205caa7
L		 5848 return size;
5849}
5850
5851/* Return the size of the immediate operand N. */
5852
5853static int
5854imm_size (unsigned int n)
5855{
5856 int size = 4;
40fb9820
L		 5857 if (i.types[n].bitfield.imm64)
5858 size = 8;
5859 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5860 size = 1;
5861 else if (i.types[n].bitfield.imm16)
5862 size = 2;
e205caa7
L		 5863 return size;
5864}
5865
29b0f896 5866static void
64e74474 5867output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5868{
5869 char *p;
5870 unsigned int n;
252b5132 5871
29b0f896
AM		 5872 for (n = 0; n < i.operands; n++)
5873 {
40fb9820 5874 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5875 {
5876 if (i.op[n].disps->X_op == O_constant)
5877 {
e205caa7 5878 int size = disp_size (n);
29b0f896 5879 offsetT val;
252b5132 5880
29b0f896
AM		 5881 val = offset_in_range (i.op[n].disps->X_add_number,
5882 size);
5883 p = frag_more (size);
5884 md_number_to_chars (p, val, size);
5885 }
5886 else
5887 {
f86103b7 5888 enum bfd_reloc_code_real reloc_type;
e205caa7 5889 int size = disp_size (n);
40fb9820 5890 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5891 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5892
e205caa7 5893 /* We can't have 8 bit displacement here. */
9c2799c2 5894 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 5895
29b0f896
AM		 5896 /* The PC relative address is computed relative
5897 to the instruction boundary, so in case immediate
5898 fields follows, we need to adjust the value. */
5899 if (pcrel && i.imm_operands)
5900 {
29b0f896 5901 unsigned int n1;
e205caa7 5902 int sz = 0;
252b5132 5903
29b0f896 5904 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5905 if (operand_type_check (i.types[n1], imm))
252b5132 5906 {
e205caa7
L		 5907 /* Only one immediate is allowed for PC
5908 relative address. */
9c2799c2 5909 gas_assert (sz == 0);
e205caa7
L		 5910 sz = imm_size (n1);
5911 i.op[n].disps->X_add_number -= sz;
252b5132 5912 }
29b0f896 5913 /* We should find the immediate. */
9c2799c2 5914 gas_assert (sz != 0);
29b0f896 5915 }
520dc8e8 5916
29b0f896 5917 p = frag_more (size);
2bbd9c25 5918 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5919 if (GOT_symbol
2bbd9c25 5920 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5921 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5922 || reloc_type == BFD_RELOC_X86_64_32S
5923 || (reloc_type == BFD_RELOC_64
5924 && object_64bit))
d6ab8113
JB		 5925 && (i.op[n].disps->X_op == O_symbol
5926 || (i.op[n].disps->X_op == O_add
5927 && ((symbol_get_value_expression
5928 (i.op[n].disps->X_op_symbol)->X_op)
5929 == O_subtract))))
5930 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5931 {
5932 offsetT add;
5933
5934 if (insn_start_frag == frag_now)
5935 add = (p - frag_now->fr_literal) - insn_start_off;
5936 else
5937 {
5938 fragS *fr;
5939
5940 add = insn_start_frag->fr_fix - insn_start_off;
5941 for (fr = insn_start_frag->fr_next;
5942 fr && fr != frag_now; fr = fr->fr_next)
5943 add += fr->fr_fix;
5944 add += p - frag_now->fr_literal;
5945 }
5946
4fa24527 5947 if (!object_64bit)
7b81dfbb
AJ		 5948 {
5949 reloc_type = BFD_RELOC_386_GOTPC;
5950 i.op[n].imms->X_add_number += add;
5951 }
5952 else if (reloc_type == BFD_RELOC_64)
5953 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5954 else
7b81dfbb
AJ		 5955 /* Don't do the adjustment for x86-64, as there
5956 the pcrel addressing is relative to the _next_
5957 insn, and that is taken care of in other code. */
d6ab8113 5958 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5959 }
062cd5e7 5960 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5961 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5962 }
5963 }
5964 }
5965}
252b5132 5966
29b0f896 5967static void
64e74474 5968output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5969{
5970 char *p;
5971 unsigned int n;
252b5132 5972
29b0f896
AM		 5973 for (n = 0; n < i.operands; n++)
5974 {
40fb9820 5975 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5976 {
5977 if (i.op[n].imms->X_op == O_constant)
5978 {
e205caa7 5979 int size = imm_size (n);
29b0f896 5980 offsetT val;
b4cac588 5981
29b0f896
AM		 5982 val = offset_in_range (i.op[n].imms->X_add_number,
5983 size);
5984 p = frag_more (size);
5985 md_number_to_chars (p, val, size);
5986 }
5987 else
5988 {
5989 /* Not absolute_section.
5990 Need a 32-bit fixup (don't support 8bit
5991 non-absolute imms). Try to support other
5992 sizes ... */
f86103b7 5993 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5994 int size = imm_size (n);
5995 int sign;
29b0f896 5996
40fb9820 5997 if (i.types[n].bitfield.imm32s
a7d61044 5998 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5999 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6000 sign = 1;
e205caa7
L		 6001 else
6002 sign = 0;
520dc8e8 6003
29b0f896
AM		 6004 p = frag_more (size);
6005 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6006
2bbd9c25
JJ		 6007 /* This is tough to explain. We end up with this one if we
6008 * have operands that look like
6009 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6010 * obtain the absolute address of the GOT, and it is strongly
6011 * preferable from a performance point of view to avoid using
6012 * a runtime relocation for this. The actual sequence of
6013 * instructions often look something like:
6014 *
6015 * call .L66
6016 * .L66:
6017 * popl %ebx
6018 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6019 *
6020 * The call and pop essentially return the absolute address
6021 * of the label .L66 and store it in %ebx. The linker itself
6022 * will ultimately change the first operand of the addl so
6023 * that %ebx points to the GOT, but to keep things simple, the
6024 * .o file must have this operand set so that it generates not
6025 * the absolute address of .L66, but the absolute address of
6026 * itself. This allows the linker itself simply treat a GOTPC
6027 * relocation as asking for a pcrel offset to the GOT to be
6028 * added in, and the addend of the relocation is stored in the
6029 * operand field for the instruction itself.
6030 *
6031 * Our job here is to fix the operand so that it would add
6032 * the correct offset so that %ebx would point to itself. The
6033 * thing that is tricky is that .-.L66 will point to the
6034 * beginning of the instruction, so we need to further modify
6035 * the operand so that it will point to itself. There are
6036 * other cases where you have something like:
6037 *
6038 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6039 *
6040 * and here no correction would be required. Internally in
6041 * the assembler we treat operands of this form as not being
6042 * pcrel since the '.' is explicitly mentioned, and I wonder
6043 * whether it would simplify matters to do it this way. Who
6044 * knows. In earlier versions of the PIC patches, the
6045 * pcrel_adjust field was used to store the correction, but
6046 * since the expression is not pcrel, I felt it would be
6047 * confusing to do it this way. */
6048
d6ab8113 6049 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6050 || reloc_type == BFD_RELOC_X86_64_32S
6051 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6052 && GOT_symbol
6053 && GOT_symbol == i.op[n].imms->X_add_symbol
6054 && (i.op[n].imms->X_op == O_symbol
6055 || (i.op[n].imms->X_op == O_add
6056 && ((symbol_get_value_expression
6057 (i.op[n].imms->X_op_symbol)->X_op)
6058 == O_subtract))))
6059 {
2bbd9c25
JJ		 6060 offsetT add;
6061
6062 if (insn_start_frag == frag_now)
6063 add = (p - frag_now->fr_literal) - insn_start_off;
6064 else
6065 {
6066 fragS *fr;
6067
6068 add = insn_start_frag->fr_fix - insn_start_off;
6069 for (fr = insn_start_frag->fr_next;
6070 fr && fr != frag_now; fr = fr->fr_next)
6071 add += fr->fr_fix;
6072 add += p - frag_now->fr_literal;
6073 }
6074
4fa24527 6075 if (!object_64bit)
d6ab8113 6076 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6077 else if (size == 4)
d6ab8113 6078 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6079 else if (size == 8)
6080 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6081 i.op[n].imms->X_add_number += add;
29b0f896 6082 }
29b0f896
AM		 6083 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6084 i.op[n].imms, 0, reloc_type);
6085 }
6086 }
6087 }
252b5132
RH		 6088}
6089\f
d182319b
JB		 6090/* x86_cons_fix_new is called via the expression parsing code when a
6091 reloc is needed. We use this hook to get the correct .got reloc. */
6092static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6093static int cons_sign = -1;
6094
6095void
e3bb37b5 6096x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6097 expressionS *exp)
d182319b
JB		 6098{
6099 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6100
6101 got_reloc = NO_RELOC;
6102
6103#ifdef TE_PE
6104 if (exp->X_op == O_secrel)
6105 {
6106 exp->X_op = O_symbol;
6107 r = BFD_RELOC_32_SECREL;
6108 }
6109#endif
6110
6111 fix_new_exp (frag, off, len, exp, 0, r);
6112}
6113
718ddfc0
JB		 6114#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6115# define lex_got(reloc, adjust, types) NULL
6116#else
f3c180ae
AM		 6117/* Parse operands of the form
6118 <symbol>@GOTOFF+<nnn>
6119 and similar .plt or .got references.
6120
6121 If we find one, set up the correct relocation in RELOC and copy the
6122 input string, minus the `@GOTOFF' into a malloc'd buffer for
6123 parsing by the calling routine. Return this buffer, and if ADJUST
6124 is non-null set it to the length of the string we removed from the
6125 input line. Otherwise return NULL. */
6126static char *
91d6fa6a 6127lex_got (enum bfd_reloc_code_real *rel,
64e74474 6128 int *adjust,
40fb9820 6129 i386_operand_type *types)
f3c180ae 6130{
7b81dfbb
AJ		 6131 /* Some of the relocations depend on the size of what field is to
6132 be relocated. But in our callers i386_immediate and i386_displacement
6133 we don't yet know the operand size (this will be set by insn
6134 matching). Hence we record the word32 relocation here,
6135 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6136 static const struct {
6137 const char *str;
4fa24527 6138 const enum bfd_reloc_code_real rel[2];
40fb9820 6139 const i386_operand_type types64;
f3c180ae 6140 } gotrel[] = {
1e9cc1c2 6141 { "PLTOFF", { _dummy_first_bfd_reloc_code_real,
4eed87de 6142 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6143 OPERAND_TYPE_IMM64 },
4eed87de
AM		 6144 { "PLT", { BFD_RELOC_386_PLT32,
6145 BFD_RELOC_X86_64_PLT32 },
40fb9820 6146 OPERAND_TYPE_IMM32_32S_DISP32 },
1e9cc1c2 6147 { "GOTPLT", { _dummy_first_bfd_reloc_code_real,
4eed87de 6148 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6149 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6150 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
6151 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6152 OPERAND_TYPE_IMM64_DISP64 },
1e9cc1c2 6153 { "GOTPCREL", { _dummy_first_bfd_reloc_code_real,
4eed87de 6154 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6155 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6156 { "TLSGD", { BFD_RELOC_386_TLS_GD,
6157 BFD_RELOC_X86_64_TLSGD },
40fb9820 6158 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de 6159 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
1e9cc1c2 6160 _dummy_first_bfd_reloc_code_real },
40fb9820 6161 OPERAND_TYPE_NONE },
1e9cc1c2 6162 { "TLSLD", { _dummy_first_bfd_reloc_code_real,
4eed87de 6163 BFD_RELOC_X86_64_TLSLD },
40fb9820 6164 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6165 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
6166 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6167 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6168 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
6169 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6170 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de 6171 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
1e9cc1c2 6172 _dummy_first_bfd_reloc_code_real },
40fb9820 6173 OPERAND_TYPE_NONE },
4eed87de
AM		 6174 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
6175 BFD_RELOC_X86_64_DTPOFF32 },
7ab9ffdd 6176
40fb9820 6177 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de 6178 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
1e9cc1c2 6179 _dummy_first_bfd_reloc_code_real },
40fb9820 6180 OPERAND_TYPE_NONE },
4eed87de 6181 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
1e9cc1c2 6182 _dummy_first_bfd_reloc_code_real },
40fb9820 6183 OPERAND_TYPE_NONE },
4eed87de
AM		 6184 { "GOT", { BFD_RELOC_386_GOT32,
6185 BFD_RELOC_X86_64_GOT32 },
40fb9820 6186 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 6187 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
6188 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6189 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6190 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
6191 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6192 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6193 };
6194 char *cp;
6195 unsigned int j;
6196
718ddfc0
JB		 6197 if (!IS_ELF)
6198 return NULL;
6199
f3c180ae 6200 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6201 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6202 return NULL;
6203
47465058 6204 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 6205 {
6206 int len;
6207
6208 len = strlen (gotrel[j].str);
28f81592 6209 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6210 {
4fa24527 6211 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6212 {
28f81592
AM		 6213 int first, second;
6214 char *tmpbuf, *past_reloc;
f3c180ae 6215
91d6fa6a 6216 *rel = gotrel[j].rel[object_64bit];
28f81592
AM		 6217 if (adjust)
6218 *adjust = len;
f3c180ae 6219
3956db08
JB		 6220 if (types)
6221 {
6222 if (flag_code != CODE_64BIT)
40fb9820
L		 6223 {
6224 types->bitfield.imm32 = 1;
6225 types->bitfield.disp32 = 1;
6226 }
3956db08
JB		 6227 else
6228 *types = gotrel[j].types64;
6229 }
6230
f3c180ae
AM		 6231 if (GOT_symbol == NULL)
6232 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6233
28f81592 6234 /* The length of the first part of our input line. */
f3c180ae 6235 first = cp - input_line_pointer;
28f81592
AM		 6236
6237 /* The second part goes from after the reloc token until
67c11a9b 6238 (and including) an end_of_line char or comma. */
28f81592 6239 past_reloc = cp + 1 + len;
67c11a9b
AM		 6240 cp = past_reloc;
6241 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6242 ++cp;
6243 second = cp + 1 - past_reloc;
28f81592
AM		 6244
6245 /* Allocate and copy string. The trailing NUL shouldn't
6246 be necessary, but be safe. */
1e9cc1c2 6247 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6248 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6249 if (second != 0 && *past_reloc != ' ')
6250 /* Replace the relocation token with ' ', so that
6251 errors like foo@GOTOFF1 will be detected. */
6252 tmpbuf[first++] = ' ';
6253 memcpy (tmpbuf + first, past_reloc, second);
6254 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6255 return tmpbuf;
6256 }
6257
4fa24527
JB		 6258 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6259 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6260 return NULL;
6261 }
6262 }
6263
6264 /* Might be a symbol version string. Don't as_bad here. */
6265 return NULL;
6266}
6267
f3c180ae 6268void
e3bb37b5 6269x86_cons (expressionS *exp, int size)
f3c180ae 6270{
ee86248c
JB		 6271 intel_syntax = -intel_syntax;
6272
4fa24527 6273 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6274 {
6275 /* Handle @GOTOFF and the like in an expression. */
6276 char *save;
6277 char *gotfree_input_line;
6278 int adjust;
6279
6280 save = input_line_pointer;
3956db08 6281 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6282 if (gotfree_input_line)
6283 input_line_pointer = gotfree_input_line;
6284
6285 expression (exp);
6286
6287 if (gotfree_input_line)
6288 {
6289 /* expression () has merrily parsed up to the end of line,
6290 or a comma - in the wrong buffer. Transfer how far
6291 input_line_pointer has moved to the right buffer. */
6292 input_line_pointer = (save
6293 + (input_line_pointer - gotfree_input_line)
6294 + adjust);
6295 free (gotfree_input_line);
3992d3b7
AM		 6296 if (exp->X_op == O_constant
6297 || exp->X_op == O_absent
6298 || exp->X_op == O_illegal
6299 || exp->X_op == O_register
6300 || exp->X_op == O_big)
6301 {
6302 char c = *input_line_pointer;
6303 *input_line_pointer = 0;
6304 as_bad (_("missing or invalid expression `%s'"), save);
6305 *input_line_pointer = c;
6306 }
f3c180ae
AM		 6307 }
6308 }
6309 else
6310 expression (exp);
ee86248c
JB		 6311
6312 intel_syntax = -intel_syntax;
6313
6314 if (intel_syntax)
6315 i386_intel_simplify (exp);
f3c180ae
AM		 6316}
6317#endif
6318
9f32dd5b
L		 6319static void
6320signed_cons (int size)
6482c264 6321{
d182319b
JB		 6322 if (flag_code == CODE_64BIT)
6323 cons_sign = 1;
6324 cons (size);
6325 cons_sign = -1;
6482c264
NC		 6326}
6327
d182319b 6328#ifdef TE_PE
6482c264
NC		 6329static void
6330pe_directive_secrel (dummy)
6331 int dummy ATTRIBUTE_UNUSED;
6332{
6333 expressionS exp;
6334
6335 do
6336 {
6337 expression (&exp);
6338 if (exp.X_op == O_symbol)
6339 exp.X_op = O_secrel;
6340
6341 emit_expr (&exp, 4);
6342 }
6343 while (*input_line_pointer++ == ',');
6344
6345 input_line_pointer--;
6346 demand_empty_rest_of_line ();
6347}
6482c264
NC		 6348#endif
6349
252b5132 6350static int
70e41ade 6351i386_immediate (char *imm_start)
252b5132
RH		 6352{
6353 char *save_input_line_pointer;
f3c180ae 6354 char *gotfree_input_line;
252b5132 6355 segT exp_seg = 0;
47926f60 6356 expressionS *exp;
40fb9820
L		 6357 i386_operand_type types;
6358
0dfbf9d7 6359 operand_type_set (&types, ~0);
252b5132
RH		 6360
6361 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6362 {
31b2323c
L		 6363 as_bad (_("at most %d immediate operands are allowed"),
6364 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6365 return 0;
6366 }
6367
6368 exp = &im_expressions[i.imm_operands++];
520dc8e8 6369 i.op[this_operand].imms = exp;
252b5132
RH		 6370
6371 if (is_space_char (*imm_start))
6372 ++imm_start;
6373
6374 save_input_line_pointer = input_line_pointer;
6375 input_line_pointer = imm_start;
6376
3956db08 6377 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6378 if (gotfree_input_line)
6379 input_line_pointer = gotfree_input_line;
252b5132
RH		 6380
6381 exp_seg = expression (exp);
6382
83183c0c 6383 SKIP_WHITESPACE ();
252b5132 6384 if (*input_line_pointer)
f3c180ae 6385 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6386
6387 input_line_pointer = save_input_line_pointer;
f3c180ae 6388 if (gotfree_input_line)
ee86248c
JB		 6389 {
6390 free (gotfree_input_line);
6391
6392 if (exp->X_op == O_constant || exp->X_op == O_register)
6393 exp->X_op = O_illegal;
6394 }
6395
6396 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6397}
252b5132 6398
ee86248c
JB		 6399static int
6400i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6401 i386_operand_type types, const char *imm_start)
6402{
6403 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6404 {
313c53d1
L		 6405 if (imm_start)
6406 as_bad (_("missing or invalid immediate expression `%s'"),
6407 imm_start);
3992d3b7 6408 return 0;
252b5132 6409 }
3e73aa7c 6410 else if (exp->X_op == O_constant)
252b5132 6411 {
47926f60 6412 /* Size it properly later. */
40fb9820 6413 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6414 /* If BFD64, sign extend val. */
4eed87de
AM		 6415 if (!use_rela_relocations
6416 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6417 exp->X_add_number
6418 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6419 }
4c63da97 6420#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6421 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6422 && exp_seg != absolute_section
47926f60 6423 && exp_seg != text_section
24eab124
AM		 6424 && exp_seg != data_section
6425 && exp_seg != bss_section
6426 && exp_seg != undefined_section
f86103b7 6427 && !bfd_is_com_section (exp_seg))
252b5132 6428 {
d0b47220 6429 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6430 return 0;
6431 }
6432#endif
bb8f5920
L		 6433 else if (!intel_syntax && exp->X_op == O_register)
6434 {
313c53d1
L		 6435 if (imm_start)
6436 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 6437 return 0;
6438 }
252b5132
RH		 6439 else
6440 {
6441 /* This is an address. The size of the address will be
24eab124 6442 determined later, depending on destination register,
3e73aa7c 6443 suffix, or the default for the section. */
40fb9820
L		 6444 i.types[this_operand].bitfield.imm8 = 1;
6445 i.types[this_operand].bitfield.imm16 = 1;
6446 i.types[this_operand].bitfield.imm32 = 1;
6447 i.types[this_operand].bitfield.imm32s = 1;
6448 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6449 i.types[this_operand] = operand_type_and (i.types[this_operand],
6450 types);
252b5132
RH		 6451 }
6452
6453 return 1;
6454}
6455
551c1ca1 6456static char *
e3bb37b5 6457i386_scale (char *scale)
252b5132 6458{
551c1ca1
AM		 6459 offsetT val;
6460 char *save = input_line_pointer;
252b5132 6461
551c1ca1
AM		 6462 input_line_pointer = scale;
6463 val = get_absolute_expression ();
6464
6465 switch (val)
252b5132 6466 {
551c1ca1 6467 case 1:
252b5132
RH		 6468 i.log2_scale_factor = 0;
6469 break;
551c1ca1 6470 case 2:
252b5132
RH		 6471 i.log2_scale_factor = 1;
6472 break;
551c1ca1 6473 case 4:
252b5132
RH		 6474 i.log2_scale_factor = 2;
6475 break;
551c1ca1 6476 case 8:
252b5132
RH		 6477 i.log2_scale_factor = 3;
6478 break;
6479 default:
a724f0f4
JB		 6480 {
6481 char sep = *input_line_pointer;
6482
6483 *input_line_pointer = '\0';
6484 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6485 scale);
6486 *input_line_pointer = sep;
6487 input_line_pointer = save;
6488 return NULL;
6489 }
252b5132 6490 }
29b0f896 6491 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6492 {
6493 as_warn (_("scale factor of %d without an index register"),
24eab124 6494 1 << i.log2_scale_factor);
252b5132 6495 i.log2_scale_factor = 0;
252b5132 6496 }
551c1ca1
AM		 6497 scale = input_line_pointer;
6498 input_line_pointer = save;
6499 return scale;
252b5132
RH		 6500}
6501
252b5132 6502static int
e3bb37b5 6503i386_displacement (char *disp_start, char *disp_end)
252b5132 6504{
29b0f896 6505 expressionS *exp;
252b5132
RH		 6506 segT exp_seg = 0;
6507 char *save_input_line_pointer;
f3c180ae 6508 char *gotfree_input_line;
40fb9820
L		 6509 int override;
6510 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6511 int ret;
252b5132 6512
31b2323c
L		 6513 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6514 {
6515 as_bad (_("at most %d displacement operands are allowed"),
6516 MAX_MEMORY_OPERANDS);
6517 return 0;
6518 }
6519
0dfbf9d7 6520 operand_type_set (&bigdisp, 0);
40fb9820
L		 6521 if ((i.types[this_operand].bitfield.jumpabsolute)
6522 || (!current_templates->start->opcode_modifier.jump
6523 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6524 {
40fb9820 6525 bigdisp.bitfield.disp32 = 1;
e05278af 6526 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6527 if (flag_code == CODE_64BIT)
6528 {
6529 if (!override)
6530 {
6531 bigdisp.bitfield.disp32s = 1;
6532 bigdisp.bitfield.disp64 = 1;
6533 }
6534 }
6535 else if ((flag_code == CODE_16BIT) ^ override)
6536 {
6537 bigdisp.bitfield.disp32 = 0;
6538 bigdisp.bitfield.disp16 = 1;
6539 }
e05278af
JB		 6540 }
6541 else
6542 {
6543 /* For PC-relative branches, the width of the displacement
6544 is dependent upon data size, not address size. */
e05278af 6545 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6546 if (flag_code == CODE_64BIT)
6547 {
6548 if (override || i.suffix == WORD_MNEM_SUFFIX)
6549 bigdisp.bitfield.disp16 = 1;
6550 else
6551 {
6552 bigdisp.bitfield.disp32 = 1;
6553 bigdisp.bitfield.disp32s = 1;
6554 }
6555 }
6556 else
e05278af
JB		 6557 {
6558 if (!override)
6559 override = (i.suffix == (flag_code != CODE_16BIT
6560 ? WORD_MNEM_SUFFIX
6561 : LONG_MNEM_SUFFIX));
40fb9820
L		 6562 bigdisp.bitfield.disp32 = 1;
6563 if ((flag_code == CODE_16BIT) ^ override)
6564 {
6565 bigdisp.bitfield.disp32 = 0;
6566 bigdisp.bitfield.disp16 = 1;
6567 }
e05278af 6568 }
e05278af 6569 }
c6fb90c8
L		 6570 i.types[this_operand] = operand_type_or (i.types[this_operand],
6571 bigdisp);
252b5132
RH		 6572
6573 exp = &disp_expressions[i.disp_operands];
520dc8e8 6574 i.op[this_operand].disps = exp;
252b5132
RH		 6575 i.disp_operands++;
6576 save_input_line_pointer = input_line_pointer;
6577 input_line_pointer = disp_start;
6578 END_STRING_AND_SAVE (disp_end);
6579
6580#ifndef GCC_ASM_O_HACK
6581#define GCC_ASM_O_HACK 0
6582#endif
6583#if GCC_ASM_O_HACK
6584 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6585 if (i.types[this_operand].bitfield.baseIndex
24eab124 6586 && displacement_string_end[-1] == '+')
252b5132
RH		 6587 {
6588 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6589 constraint within gcc asm statements.
6590 For instance:
6591
6592 #define _set_tssldt_desc(n,addr,limit,type) \
6593 __asm__ __volatile__ ( \
6594 "movw %w2,%0\n\t" \
6595 "movw %w1,2+%0\n\t" \
6596 "rorl $16,%1\n\t" \
6597 "movb %b1,4+%0\n\t" \
6598 "movb %4,5+%0\n\t" \
6599 "movb $0,6+%0\n\t" \
6600 "movb %h1,7+%0\n\t" \
6601 "rorl $16,%1" \
6602 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6603
6604 This works great except that the output assembler ends
6605 up looking a bit weird if it turns out that there is
6606 no offset. You end up producing code that looks like:
6607
6608 #APP
6609 movw $235,(%eax)
6610 movw %dx,2+(%eax)
6611 rorl $16,%edx
6612 movb %dl,4+(%eax)
6613 movb $137,5+(%eax)
6614 movb $0,6+(%eax)
6615 movb %dh,7+(%eax)
6616 rorl $16,%edx
6617 #NO_APP
6618
47926f60 6619 So here we provide the missing zero. */
24eab124
AM		 6620
6621 *displacement_string_end = '0';
252b5132
RH		 6622 }
6623#endif
3956db08 6624 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6625 if (gotfree_input_line)
6626 input_line_pointer = gotfree_input_line;
252b5132 6627
24eab124 6628 exp_seg = expression (exp);
252b5132 6629
636c26b0
AM		 6630 SKIP_WHITESPACE ();
6631 if (*input_line_pointer)
6632 as_bad (_("junk `%s' after expression"), input_line_pointer);
6633#if GCC_ASM_O_HACK
6634 RESTORE_END_STRING (disp_end + 1);
6635#endif
636c26b0 6636 input_line_pointer = save_input_line_pointer;
636c26b0 6637 if (gotfree_input_line)
ee86248c
JB		 6638 {
6639 free (gotfree_input_line);
6640
6641 if (exp->X_op == O_constant || exp->X_op == O_register)
6642 exp->X_op = O_illegal;
6643 }
6644
6645 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6646
6647 RESTORE_END_STRING (disp_end);
6648
6649 return ret;
6650}
6651
6652static int
6653i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6654 i386_operand_type types, const char *disp_start)
6655{
6656 i386_operand_type bigdisp;
6657 int ret = 1;
636c26b0 6658
24eab124
AM		 6659 /* We do this to make sure that the section symbol is in
6660 the symbol table. We will ultimately change the relocation
47926f60 6661 to be relative to the beginning of the section. */
1ae12ab7 6662 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6663 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6664 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6665 {
636c26b0 6666 if (exp->X_op != O_symbol)
3992d3b7 6667 goto inv_disp;
636c26b0 6668
e5cb08ac 6669 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6670 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6671 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6672 exp->X_op = O_subtract;
6673 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6674 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6675 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6676 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6677 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6678 else
29b0f896 6679 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6680 }
252b5132 6681
3992d3b7
AM		 6682 else if (exp->X_op == O_absent
6683 || exp->X_op == O_illegal
ee86248c 6684 || exp->X_op == O_big)
2daf4fd8 6685 {
3992d3b7
AM		 6686 inv_disp:
6687 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6688 disp_start);
3992d3b7 6689 ret = 0;
2daf4fd8
AM		 6690 }
6691
0e1147d9
L		 6692 else if (flag_code == CODE_64BIT
6693 && !i.prefix[ADDR_PREFIX]
6694 && exp->X_op == O_constant)
6695 {
6696 /* Since displacement is signed extended to 64bit, don't allow
6697 disp32 and turn off disp32s if they are out of range. */
6698 i.types[this_operand].bitfield.disp32 = 0;
6699 if (!fits_in_signed_long (exp->X_add_number))
6700 {
6701 i.types[this_operand].bitfield.disp32s = 0;
6702 if (i.types[this_operand].bitfield.baseindex)
6703 {
6704 as_bad (_("0x%lx out range of signed 32bit displacement"),
6705 (long) exp->X_add_number);
6706 ret = 0;
6707 }
6708 }
6709 }
6710
4c63da97 6711#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6712 else if (exp->X_op != O_constant
6713 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6714 && exp_seg != absolute_section
6715 && exp_seg != text_section
6716 && exp_seg != data_section
6717 && exp_seg != bss_section
6718 && exp_seg != undefined_section
6719 && !bfd_is_com_section (exp_seg))
24eab124 6720 {
d0b47220 6721 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6722 ret = 0;
24eab124 6723 }
252b5132 6724#endif
3956db08 6725
40fb9820
L		 6726 /* Check if this is a displacement only operand. */
6727 bigdisp = i.types[this_operand];
6728 bigdisp.bitfield.disp8 = 0;
6729 bigdisp.bitfield.disp16 = 0;
6730 bigdisp.bitfield.disp32 = 0;
6731 bigdisp.bitfield.disp32s = 0;
6732 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6733 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6734 i.types[this_operand] = operand_type_and (i.types[this_operand],
6735 types);
3956db08 6736
3992d3b7 6737 return ret;
252b5132
RH		 6738}
6739
eecb386c 6740/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6741 Return 1 on success, 0 on a failure. */
6742
252b5132 6743static int
e3bb37b5 6744i386_index_check (const char *operand_string)
252b5132 6745{
3e73aa7c 6746 int ok;
fc0763e6 6747 const char *kind = "base/index";
24eab124 6748#if INFER_ADDR_PREFIX
eecb386c
AM		 6749 int fudged = 0;
6750
24eab124
AM		 6751 tryprefix:
6752#endif
3e73aa7c 6753 ok = 1;
fc0763e6
JB		 6754 if (current_templates->start->opcode_modifier.isstring
6755 && !current_templates->start->opcode_modifier.immext
6756 && (current_templates->end[-1].opcode_modifier.isstring
6757 || i.mem_operands))
6758 {
6759 /* Memory operands of string insns are special in that they only allow
6760 a single register (rDI, rSI, or rBX) as their memory address. */
6761 unsigned int expected;
6762
6763 kind = "string address";
6764
6765 if (current_templates->start->opcode_modifier.w)
6766 {
6767 i386_operand_type type = current_templates->end[-1].operand_types[0];
6768
6769 if (!type.bitfield.baseindex
6770 || ((!i.mem_operands != !intel_syntax)
6771 && current_templates->end[-1].operand_types[1]
6772 .bitfield.baseindex))
6773 type = current_templates->end[-1].operand_types[1];
6774 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6775 }
6776 else
6777 expected = 3 /* rBX */;
6778
6779 if (!i.base_reg || i.index_reg
6780 || operand_type_check (i.types[this_operand], disp))
6781 ok = -1;
6782 else if (!(flag_code == CODE_64BIT
6783 ? i.prefix[ADDR_PREFIX]
6784 ? i.base_reg->reg_type.bitfield.reg32
6785 : i.base_reg->reg_type.bitfield.reg64
6786 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6787 ? i.base_reg->reg_type.bitfield.reg32
6788 : i.base_reg->reg_type.bitfield.reg16))
6789 ok = 0;
6790 else if (i.base_reg->reg_num != expected)
6791 ok = -1;
6792
6793 if (ok < 0)
6794 {
6795 unsigned int j;
6796
6797 for (j = 0; j < i386_regtab_size; ++j)
6798 if ((flag_code == CODE_64BIT
6799 ? i.prefix[ADDR_PREFIX]
6800 ? i386_regtab[j].reg_type.bitfield.reg32
6801 : i386_regtab[j].reg_type.bitfield.reg64
6802 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6803 ? i386_regtab[j].reg_type.bitfield.reg32
6804 : i386_regtab[j].reg_type.bitfield.reg16)
6805 && i386_regtab[j].reg_num == expected)
6806 break;
9c2799c2 6807 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 6808 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6809 operand_string,
6810 intel_syntax ? '[' : '(',
6811 register_prefix,
6812 i386_regtab[j].reg_name,
6813 intel_syntax ? ']' : ')');
6814 ok = 1;
6815 }
6816 }
6817 else if (flag_code == CODE_64BIT)
64e74474 6818 {
64e74474 6819 if ((i.base_reg
40fb9820
L		 6820 && ((i.prefix[ADDR_PREFIX] == 0
6821 && !i.base_reg->reg_type.bitfield.reg64)
6822 || (i.prefix[ADDR_PREFIX]
6823 && !i.base_reg->reg_type.bitfield.reg32))
6824 && (i.index_reg
9a04903e
JB		 6825 || i.base_reg->reg_num !=
6826 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6827 || (i.index_reg
40fb9820
L		 6828 && (!i.index_reg->reg_type.bitfield.baseindex
6829 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6830 && i.index_reg->reg_num != RegRiz
6831 && !i.index_reg->reg_type.bitfield.reg64
6832 )
40fb9820 6833 || (i.prefix[ADDR_PREFIX]
db51cc60 6834 && i.index_reg->reg_num != RegEiz
40fb9820 6835 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6836 ok = 0;
3e73aa7c
JH		 6837 }
6838 else
6839 {
6840 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6841 {
6842 /* 16bit checks. */
6843 if ((i.base_reg
40fb9820
L		 6844 && (!i.base_reg->reg_type.bitfield.reg16
6845 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6846 || (i.index_reg
40fb9820
L		 6847 && (!i.index_reg->reg_type.bitfield.reg16
6848 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6849 || !(i.base_reg
6850 && i.base_reg->reg_num < 6
6851 && i.index_reg->reg_num >= 6
6852 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6853 ok = 0;
6854 }
6855 else
e5cb08ac 6856 {
3e73aa7c
JH		 6857 /* 32bit checks. */
6858 if ((i.base_reg
40fb9820 6859 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6860 || (i.index_reg
db51cc60
L		 6861 && ((!i.index_reg->reg_type.bitfield.reg32
6862 && i.index_reg->reg_num != RegEiz)
40fb9820 6863 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6864 ok = 0;
3e73aa7c
JH		 6865 }
6866 }
6867 if (!ok)
24eab124
AM		 6868 {
6869#if INFER_ADDR_PREFIX
fc0763e6 6870 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 6871 {
6872 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6873 i.prefixes += 1;
b23bac36
AM		 6874 /* Change the size of any displacement too. At most one of
6875 Disp16 or Disp32 is set.
6876 FIXME. There doesn't seem to be any real need for separate
6877 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6878 Removing them would probably clean up the code quite a lot. */
4eed87de 6879 if (flag_code != CODE_64BIT
40fb9820
L		 6880 && (i.types[this_operand].bitfield.disp16
6881 || i.types[this_operand].bitfield.disp32))
6882 i.types[this_operand]
c6fb90c8 6883 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6884 fudged = 1;
24eab124
AM		 6885 goto tryprefix;
6886 }
eecb386c 6887 if (fudged)
fc0763e6
JB		 6888 as_bad (_("`%s' is not a valid %s expression"),
6889 operand_string,
6890 kind);
eecb386c 6891 else
c388dee8 6892#endif
fc0763e6 6893 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 6894 operand_string,
fc0763e6
JB		 6895 flag_code_names[i.prefix[ADDR_PREFIX]
6896 ? flag_code == CODE_32BIT
6897 ? CODE_16BIT
6898 : CODE_32BIT
6899 : flag_code],
6900 kind);
24eab124 6901 }
20f0a1fc 6902 return ok;
24eab124 6903}
252b5132 6904
fc0763e6 6905/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 6906 on error. */
252b5132 6907
252b5132 6908static int
a7619375 6909i386_att_operand (char *operand_string)
252b5132 6910{
af6bdddf
AM		 6911 const reg_entry *r;
6912 char *end_op;
24eab124 6913 char *op_string = operand_string;
252b5132 6914
24eab124 6915 if (is_space_char (*op_string))
252b5132
RH		 6916 ++op_string;
6917
24eab124 6918 /* We check for an absolute prefix (differentiating,
47926f60 6919 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6920 if (*op_string == ABSOLUTE_PREFIX)
6921 {
6922 ++op_string;
6923 if (is_space_char (*op_string))
6924 ++op_string;
40fb9820 6925 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6926 }
252b5132 6927
47926f60 6928 /* Check if operand is a register. */
4d1bb795 6929 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6930 {
40fb9820
L		 6931 i386_operand_type temp;
6932
24eab124
AM		 6933 /* Check for a segment override by searching for ':' after a
6934 segment register. */
6935 op_string = end_op;
6936 if (is_space_char (*op_string))
6937 ++op_string;
40fb9820
L		 6938 if (*op_string == ':'
6939 && (r->reg_type.bitfield.sreg2
6940 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6941 {
6942 switch (r->reg_num)
6943 {
6944 case 0:
6945 i.seg[i.mem_operands] = &es;
6946 break;
6947 case 1:
6948 i.seg[i.mem_operands] = &cs;
6949 break;
6950 case 2:
6951 i.seg[i.mem_operands] = &ss;
6952 break;
6953 case 3:
6954 i.seg[i.mem_operands] = &ds;
6955 break;
6956 case 4:
6957 i.seg[i.mem_operands] = &fs;
6958 break;
6959 case 5:
6960 i.seg[i.mem_operands] = &gs;
6961 break;
6962 }
252b5132 6963
24eab124 6964 /* Skip the ':' and whitespace. */
252b5132
RH		 6965 ++op_string;
6966 if (is_space_char (*op_string))
24eab124 6967 ++op_string;
252b5132 6968
24eab124
AM		 6969 if (!is_digit_char (*op_string)
6970 && !is_identifier_char (*op_string)
6971 && *op_string != '('
6972 && *op_string != ABSOLUTE_PREFIX)
6973 {
6974 as_bad (_("bad memory operand `%s'"), op_string);
6975 return 0;
6976 }
47926f60 6977 /* Handle case of %es:*foo. */
24eab124
AM		 6978 if (*op_string == ABSOLUTE_PREFIX)
6979 {
6980 ++op_string;
6981 if (is_space_char (*op_string))
6982 ++op_string;
40fb9820 6983 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6984 }
6985 goto do_memory_reference;
6986 }
6987 if (*op_string)
6988 {
d0b47220 6989 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6990 return 0;
6991 }
40fb9820
L		 6992 temp = r->reg_type;
6993 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6994 i.types[this_operand] = operand_type_or (i.types[this_operand],
6995 temp);
7d5e4556 6996 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 6997 i.op[this_operand].regs = r;
24eab124
AM		 6998 i.reg_operands++;
6999 }
af6bdddf
AM		 7000 else if (*op_string == REGISTER_PREFIX)
7001 {
7002 as_bad (_("bad register name `%s'"), op_string);
7003 return 0;
7004 }
24eab124 7005 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7006 {
24eab124 7007 ++op_string;
40fb9820 7008 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7009 {
d0b47220 7010 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7011 return 0;
7012 }
7013 if (!i386_immediate (op_string))
7014 return 0;
7015 }
7016 else if (is_digit_char (*op_string)
7017 || is_identifier_char (*op_string)
e5cb08ac 7018 || *op_string == '(')
24eab124 7019 {
47926f60 7020 /* This is a memory reference of some sort. */
af6bdddf 7021 char *base_string;
252b5132 7022
47926f60 7023 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7024 char *displacement_string_start;
7025 char *displacement_string_end;
252b5132 7026
24eab124 7027 do_memory_reference:
24eab124 7028 if ((i.mem_operands == 1
40fb9820 7029 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7030 || i.mem_operands == 2)
7031 {
7032 as_bad (_("too many memory references for `%s'"),
7033 current_templates->start->name);
7034 return 0;
7035 }
252b5132 7036
24eab124
AM		 7037 /* Check for base index form. We detect the base index form by
7038 looking for an ')' at the end of the operand, searching
7039 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7040 after the '('. */
af6bdddf 7041 base_string = op_string + strlen (op_string);
c3332e24 7042
af6bdddf
AM		 7043 --base_string;
7044 if (is_space_char (*base_string))
7045 --base_string;
252b5132 7046
47926f60 7047 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7048 displacement_string_start = op_string;
7049 displacement_string_end = base_string + 1;
252b5132 7050
24eab124
AM		 7051 if (*base_string == ')')
7052 {
af6bdddf 7053 char *temp_string;
24eab124
AM		 7054 unsigned int parens_balanced = 1;
7055 /* We've already checked that the number of left & right ()'s are
47926f60 7056 equal, so this loop will not be infinite. */
24eab124
AM		 7057 do
7058 {
7059 base_string--;
7060 if (*base_string == ')')
7061 parens_balanced++;
7062 if (*base_string == '(')
7063 parens_balanced--;
7064 }
7065 while (parens_balanced);
c3332e24 7066
af6bdddf 7067 temp_string = base_string;
c3332e24 7068
24eab124 7069 /* Skip past '(' and whitespace. */
252b5132
RH		 7070 ++base_string;
7071 if (is_space_char (*base_string))
24eab124 7072 ++base_string;
252b5132 7073
af6bdddf 7074 if (*base_string == ','
4eed87de
AM		 7075 || ((i.base_reg = parse_register (base_string, &end_op))
7076 != NULL))
252b5132 7077 {
af6bdddf 7078 displacement_string_end = temp_string;
252b5132 7079
40fb9820 7080 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7081
af6bdddf 7082 if (i.base_reg)
24eab124 7083 {
24eab124
AM		 7084 base_string = end_op;
7085 if (is_space_char (*base_string))
7086 ++base_string;
af6bdddf
AM		 7087 }
7088
7089 /* There may be an index reg or scale factor here. */
7090 if (*base_string == ',')
7091 {
7092 ++base_string;
7093 if (is_space_char (*base_string))
7094 ++base_string;
7095
4eed87de
AM		 7096 if ((i.index_reg = parse_register (base_string, &end_op))
7097 != NULL)
24eab124 7098 {
af6bdddf 7099 base_string = end_op;
24eab124
AM		 7100 if (is_space_char (*base_string))
7101 ++base_string;
af6bdddf
AM		 7102 if (*base_string == ',')
7103 {
7104 ++base_string;
7105 if (is_space_char (*base_string))
7106 ++base_string;
7107 }
e5cb08ac 7108 else if (*base_string != ')')
af6bdddf 7109 {
4eed87de
AM		 7110 as_bad (_("expecting `,' or `)' "
7111 "after index register in `%s'"),
af6bdddf
AM		 7112 operand_string);
7113 return 0;
7114 }
24eab124 7115 }
af6bdddf 7116 else if (*base_string == REGISTER_PREFIX)
24eab124 7117 {
af6bdddf 7118 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7119 return 0;
7120 }
252b5132 7121
47926f60 7122 /* Check for scale factor. */
551c1ca1 7123 if (*base_string != ')')
af6bdddf 7124 {
551c1ca1
AM		 7125 char *end_scale = i386_scale (base_string);
7126
7127 if (!end_scale)
af6bdddf 7128 return 0;
24eab124 7129
551c1ca1 7130 base_string = end_scale;
af6bdddf
AM		 7131 if (is_space_char (*base_string))
7132 ++base_string;
7133 if (*base_string != ')')
7134 {
4eed87de
AM		 7135 as_bad (_("expecting `)' "
7136 "after scale factor in `%s'"),
af6bdddf
AM		 7137 operand_string);
7138 return 0;
7139 }
7140 }
7141 else if (!i.index_reg)
24eab124 7142 {
4eed87de
AM		 7143 as_bad (_("expecting index register or scale factor "
7144 "after `,'; got '%c'"),
af6bdddf 7145 *base_string);
24eab124
AM		 7146 return 0;
7147 }
7148 }
af6bdddf 7149 else if (*base_string != ')')
24eab124 7150 {
4eed87de
AM		 7151 as_bad (_("expecting `,' or `)' "
7152 "after base register in `%s'"),
af6bdddf 7153 operand_string);
24eab124
AM		 7154 return 0;
7155 }
c3332e24 7156 }
af6bdddf 7157 else if (*base_string == REGISTER_PREFIX)
c3332e24 7158 {
af6bdddf 7159 as_bad (_("bad register name `%s'"), base_string);
24eab124 7160 return 0;
c3332e24 7161 }
24eab124
AM		 7162 }
7163
7164 /* If there's an expression beginning the operand, parse it,
7165 assuming displacement_string_start and
7166 displacement_string_end are meaningful. */
7167 if (displacement_string_start != displacement_string_end)
7168 {
7169 if (!i386_displacement (displacement_string_start,
7170 displacement_string_end))
7171 return 0;
7172 }
7173
7174 /* Special case for (%dx) while doing input/output op. */
7175 if (i.base_reg
0dfbf9d7
L		 7176 && operand_type_equal (&i.base_reg->reg_type,
7177 &reg16_inoutportreg)
24eab124
AM		 7178 && i.index_reg == 0
7179 && i.log2_scale_factor == 0
7180 && i.seg[i.mem_operands] == 0
40fb9820 7181 && !operand_type_check (i.types[this_operand], disp))
24eab124 7182 {
65da13b5 7183 i.types[this_operand] = inoutportreg;
24eab124
AM		 7184 return 1;
7185 }
7186
eecb386c
AM		 7187 if (i386_index_check (operand_string) == 0)
7188 return 0;
5c07affc 7189 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7190 i.mem_operands++;
7191 }
7192 else
ce8a8b2f
AM		 7193 {
7194 /* It's not a memory operand; argh! */
24eab124
AM		 7195 as_bad (_("invalid char %s beginning operand %d `%s'"),
7196 output_invalid (*op_string),
7197 this_operand + 1,
7198 op_string);
7199 return 0;
7200 }
47926f60 7201 return 1; /* Normal return. */
252b5132
RH		 7202}
7203\f
ee7fcc42
AM		 7204/* md_estimate_size_before_relax()
7205
7206 Called just before relax() for rs_machine_dependent frags. The x86
7207 assembler uses these frags to handle variable size jump
7208 instructions.
7209
7210 Any symbol that is now undefined will not become defined.
7211 Return the correct fr_subtype in the frag.
7212 Return the initial "guess for variable size of frag" to caller.
7213 The guess is actually the growth beyond the fixed part. Whatever
7214 we do to grow the fixed or variable part contributes to our
7215 returned value. */
7216
252b5132
RH		 7217int
7218md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7219 fragS *fragP;
7220 segT segment;
252b5132 7221{
252b5132 7222 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7223 check for un-relaxable symbols. On an ELF system, we can't relax
7224 an externally visible symbol, because it may be overridden by a
7225 shared library. */
7226 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7227#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7228 || (IS_ELF
31312f95 7229 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7230 || S_IS_WEAK (fragP->fr_symbol)
7231 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7232 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7233#endif
7234#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7235 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7236 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7237#endif
7238 )
252b5132 7239 {
b98ef147
AM		 7240 /* Symbol is undefined in this segment, or we need to keep a
7241 reloc so that weak symbols can be overridden. */
7242 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7243 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7244 unsigned char *opcode;
7245 int old_fr_fix;
f6af82bd 7246
ee7fcc42 7247 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7248 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7249 else if (size == 2)
f6af82bd
AM		 7250 reloc_type = BFD_RELOC_16_PCREL;
7251 else
7252 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7253
ee7fcc42
AM		 7254 old_fr_fix = fragP->fr_fix;
7255 opcode = (unsigned char *) fragP->fr_opcode;
7256
fddf5b5b 7257 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7258 {
fddf5b5b
AM		 7259 case UNCOND_JUMP:
7260 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7261 opcode[0] = 0xe9;
252b5132 7262 fragP->fr_fix += size;
062cd5e7
AS		 7263 fix_new (fragP, old_fr_fix, size,
7264 fragP->fr_symbol,
7265 fragP->fr_offset, 1,
7266 reloc_type);
252b5132
RH		 7267 break;
7268
fddf5b5b 7269 case COND_JUMP86:
412167cb
AM		 7270 if (size == 2
7271 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7272 {
7273 /* Negate the condition, and branch past an
7274 unconditional jump. */
7275 opcode[0] ^= 1;
7276 opcode[1] = 3;
7277 /* Insert an unconditional jump. */
7278 opcode[2] = 0xe9;
7279 /* We added two extra opcode bytes, and have a two byte
7280 offset. */
7281 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7282 fix_new (fragP, old_fr_fix + 2, 2,
7283 fragP->fr_symbol,
7284 fragP->fr_offset, 1,
7285 reloc_type);
fddf5b5b
AM		 7286 break;
7287 }
7288 /* Fall through. */
7289
7290 case COND_JUMP:
412167cb
AM		 7291 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7292 {
3e02c1cc
AM		 7293 fixS *fixP;
7294
412167cb 7295 fragP->fr_fix += 1;
3e02c1cc
AM		 7296 fixP = fix_new (fragP, old_fr_fix, 1,
7297 fragP->fr_symbol,
7298 fragP->fr_offset, 1,
7299 BFD_RELOC_8_PCREL);
7300 fixP->fx_signed = 1;
412167cb
AM		 7301 break;
7302 }
93c2a809 7303
24eab124 7304 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7305 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7306 opcode[1] = opcode[0] + 0x10;
f6af82bd 7307 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7308 /* We've added an opcode byte. */
7309 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7310 fix_new (fragP, old_fr_fix + 1, size,
7311 fragP->fr_symbol,
7312 fragP->fr_offset, 1,
7313 reloc_type);
252b5132 7314 break;
fddf5b5b
AM		 7315
7316 default:
7317 BAD_CASE (fragP->fr_subtype);
7318 break;
252b5132
RH		 7319 }
7320 frag_wane (fragP);
ee7fcc42 7321 return fragP->fr_fix - old_fr_fix;
252b5132 7322 }
93c2a809 7323
93c2a809
AM		 7324 /* Guess size depending on current relax state. Initially the relax
7325 state will correspond to a short jump and we return 1, because
7326 the variable part of the frag (the branch offset) is one byte
7327 long. However, we can relax a section more than once and in that
7328 case we must either set fr_subtype back to the unrelaxed state,
7329 or return the value for the appropriate branch. */
7330 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7331}
7332
47926f60
KH		 7333/* Called after relax() is finished.
7334
7335 In: Address of frag.
7336 fr_type == rs_machine_dependent.
7337 fr_subtype is what the address relaxed to.
7338
7339 Out: Any fixSs and constants are set up.
7340 Caller will turn frag into a ".space 0". */
7341
252b5132
RH		 7342void
7343md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7344 bfd *abfd ATTRIBUTE_UNUSED;
7345 segT sec ATTRIBUTE_UNUSED;
29b0f896 7346 fragS *fragP;
252b5132 7347{
29b0f896 7348 unsigned char *opcode;
252b5132 7349 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7350 offsetT target_address;
7351 offsetT opcode_address;
252b5132 7352 unsigned int extension = 0;
847f7ad4 7353 offsetT displacement_from_opcode_start;
252b5132
RH		 7354
7355 opcode = (unsigned char *) fragP->fr_opcode;
7356
47926f60 7357 /* Address we want to reach in file space. */
252b5132 7358 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7359
47926f60 7360 /* Address opcode resides at in file space. */
252b5132
RH		 7361 opcode_address = fragP->fr_address + fragP->fr_fix;
7362
47926f60 7363 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7364 displacement_from_opcode_start = target_address - opcode_address;
7365
fddf5b5b 7366 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7367 {
47926f60
KH		 7368 /* Don't have to change opcode. */
7369 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7370 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7371 }
7372 else
7373 {
7374 if (no_cond_jump_promotion
7375 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7376 as_warn_where (fragP->fr_file, fragP->fr_line,
7377 _("long jump required"));
252b5132 7378
fddf5b5b
AM		 7379 switch (fragP->fr_subtype)
7380 {
7381 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7382 extension = 4; /* 1 opcode + 4 displacement */
7383 opcode[0] = 0xe9;
7384 where_to_put_displacement = &opcode[1];
7385 break;
252b5132 7386
fddf5b5b
AM		 7387 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7388 extension = 2; /* 1 opcode + 2 displacement */
7389 opcode[0] = 0xe9;
7390 where_to_put_displacement = &opcode[1];
7391 break;
252b5132 7392
fddf5b5b
AM		 7393 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7394 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7395 extension = 5; /* 2 opcode + 4 displacement */
7396 opcode[1] = opcode[0] + 0x10;
7397 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7398 where_to_put_displacement = &opcode[2];
7399 break;
252b5132 7400
fddf5b5b
AM		 7401 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7402 extension = 3; /* 2 opcode + 2 displacement */
7403 opcode[1] = opcode[0] + 0x10;
7404 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7405 where_to_put_displacement = &opcode[2];
7406 break;
252b5132 7407
fddf5b5b
AM		 7408 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7409 extension = 4;
7410 opcode[0] ^= 1;
7411 opcode[1] = 3;
7412 opcode[2] = 0xe9;
7413 where_to_put_displacement = &opcode[3];
7414 break;
7415
7416 default:
7417 BAD_CASE (fragP->fr_subtype);
7418 break;
7419 }
252b5132 7420 }
fddf5b5b 7421
7b81dfbb
AJ		 7422 /* If size if less then four we are sure that the operand fits,
7423 but if it's 4, then it could be that the displacement is larger
7424 then -/+ 2GB. */
7425 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7426 && object_64bit
7427 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7428 + ((addressT) 1 << 31))
7429 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7430 {
7431 as_bad_where (fragP->fr_file, fragP->fr_line,
7432 _("jump target out of range"));
7433 /* Make us emit 0. */
7434 displacement_from_opcode_start = extension;
7435 }
47926f60 7436 /* Now put displacement after opcode. */
252b5132
RH		 7437 md_number_to_chars ((char *) where_to_put_displacement,
7438 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7439 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7440 fragP->fr_fix += extension;
7441}
7442\f
252b5132
RH		 7443/* Apply a fixup (fixS) to segment data, once it has been determined
7444 by our caller that we have all the info we need to fix it up.
7445
7446 On the 386, immediates, displacements, and data pointers are all in
7447 the same (little-endian) format, so we don't need to care about which
7448 we are handling. */
7449
94f592af 7450void
55cf6793 7451md_apply_fix (fixP, valP, seg)
47926f60
KH		 7452 /* The fix we're to put in. */
7453 fixS *fixP;
47926f60 7454 /* Pointer to the value of the bits. */
c6682705 7455 valueT *valP;
47926f60
KH		 7456 /* Segment fix is from. */
7457 segT seg ATTRIBUTE_UNUSED;
252b5132 7458{
94f592af 7459 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7460 valueT value = *valP;
252b5132 7461
f86103b7 7462#if !defined (TE_Mach)
93382f6d
AM		 7463 if (fixP->fx_pcrel)
7464 {
7465 switch (fixP->fx_r_type)
7466 {
5865bb77
ILT		 7467 default:
7468 break;
7469
d6ab8113
JB		 7470 case BFD_RELOC_64:
7471 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7472 break;
93382f6d 7473 case BFD_RELOC_32:
ae8887b5 7474 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7475 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7476 break;
7477 case BFD_RELOC_16:
7478 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7479 break;
7480 case BFD_RELOC_8:
7481 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7482 break;
7483 }
7484 }
252b5132 7485
a161fe53 7486 if (fixP->fx_addsy != NULL
31312f95 7487 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7488 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7489 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7490 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7491 && !use_rela_relocations)
252b5132 7492 {
31312f95
AM		 7493 /* This is a hack. There should be a better way to handle this.
7494 This covers for the fact that bfd_install_relocation will
7495 subtract the current location (for partial_inplace, PC relative
7496 relocations); see more below. */
252b5132 7497#ifndef OBJ_AOUT
718ddfc0 7498 if (IS_ELF
252b5132
RH		 7499#ifdef TE_PE
7500 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7501#endif
7502 )
7503 value += fixP->fx_where + fixP->fx_frag->fr_address;
7504#endif
7505#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7506 if (IS_ELF)
252b5132 7507 {
6539b54b 7508 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7509
6539b54b 7510 if ((sym_seg == seg
2f66722d 7511 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7512 && sym_seg != absolute_section))
af65af87 7513 && !generic_force_reloc (fixP))
2f66722d
AM		 7514 {
7515 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7516 bfd_install_relocation subtracts them out again. I think
7517 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7518 it. FIXME. */
7519 value += fixP->fx_where + fixP->fx_frag->fr_address;
7520 }
252b5132
RH		 7521 }
7522#endif
7523#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7524 /* For some reason, the PE format does not store a
7525 section address offset for a PC relative symbol. */
7526 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7527 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7528 value += md_pcrel_from (fixP);
7529#endif
7530 }
fbeb56a4
DK		 7531#if defined (OBJ_COFF) && defined (TE_PE)
7532 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7533 {
7534 value -= S_GET_VALUE (fixP->fx_addsy);
7535 }
7536#endif
252b5132
RH		 7537
7538 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7539 and we must not disappoint it. */
252b5132 7540#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7541 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7542 switch (fixP->fx_r_type)
7543 {
7544 case BFD_RELOC_386_PLT32:
3e73aa7c 7545 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7546 /* Make the jump instruction point to the address of the operand. At
7547 runtime we merely add the offset to the actual PLT entry. */
7548 value = -4;
7549 break;
31312f95 7550
13ae64f3
JJ		 7551 case BFD_RELOC_386_TLS_GD:
7552 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7553 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7554 case BFD_RELOC_386_TLS_IE:
7555 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7556 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7557 case BFD_RELOC_X86_64_TLSGD:
7558 case BFD_RELOC_X86_64_TLSLD:
7559 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7560 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7561 value = 0; /* Fully resolved at runtime. No addend. */
7562 /* Fallthrough */
7563 case BFD_RELOC_386_TLS_LE:
7564 case BFD_RELOC_386_TLS_LDO_32:
7565 case BFD_RELOC_386_TLS_LE_32:
7566 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7567 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7568 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7569 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7570 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7571 break;
7572
67a4f2b7
AO		 7573 case BFD_RELOC_386_TLS_DESC_CALL:
7574 case BFD_RELOC_X86_64_TLSDESC_CALL:
7575 value = 0; /* Fully resolved at runtime. No addend. */
7576 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7577 fixP->fx_done = 0;
7578 return;
7579
00f7efb6
JJ		 7580 case BFD_RELOC_386_GOT32:
7581 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7582 value = 0; /* Fully resolved at runtime. No addend. */
7583 break;
47926f60
KH		 7584
7585 case BFD_RELOC_VTABLE_INHERIT:
7586 case BFD_RELOC_VTABLE_ENTRY:
7587 fixP->fx_done = 0;
94f592af 7588 return;
47926f60
KH		 7589
7590 default:
7591 break;
7592 }
7593#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7594 *valP = value;
f86103b7 7595#endif /* !defined (TE_Mach) */
3e73aa7c 7596
3e73aa7c 7597 /* Are we finished with this relocation now? */
c6682705 7598 if (fixP->fx_addsy == NULL)
3e73aa7c 7599 fixP->fx_done = 1;
fbeb56a4
DK		 7600#if defined (OBJ_COFF) && defined (TE_PE)
7601 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7602 {
7603 fixP->fx_done = 0;
7604 /* Remember value for tc_gen_reloc. */
7605 fixP->fx_addnumber = value;
7606 /* Clear out the frag for now. */
7607 value = 0;
7608 }
7609#endif
3e73aa7c
JH		 7610 else if (use_rela_relocations)
7611 {
7612 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7613 /* Remember value for tc_gen_reloc. */
7614 fixP->fx_addnumber = value;
3e73aa7c
JH		 7615 value = 0;
7616 }
f86103b7 7617
94f592af 7618 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7619}
252b5132 7620\f
252b5132 7621char *
499ac353 7622md_atof (int type, char *litP, int *sizeP)
252b5132 7623{
499ac353
NC		 7624 /* This outputs the LITTLENUMs in REVERSE order;
7625 in accord with the bigendian 386. */
7626 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7627}
7628\f
2d545b82 7629static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7630
252b5132 7631static char *
e3bb37b5 7632output_invalid (int c)
252b5132 7633{
3882b010 7634 if (ISPRINT (c))
f9f21a03
L		 7635 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7636 "'%c'", c);
252b5132 7637 else
f9f21a03 7638 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7639 "(0x%x)", (unsigned char) c);
252b5132
RH		 7640 return output_invalid_buf;
7641}
7642
af6bdddf 7643/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7644
7645static const reg_entry *
4d1bb795 7646parse_real_register (char *reg_string, char **end_op)
252b5132 7647{
af6bdddf
AM		 7648 char *s = reg_string;
7649 char *p;
252b5132
RH		 7650 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7651 const reg_entry *r;
7652
7653 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7654 if (*s == REGISTER_PREFIX)
7655 ++s;
7656
7657 if (is_space_char (*s))
7658 ++s;
7659
7660 p = reg_name_given;
af6bdddf 7661 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7662 {
7663 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7664 return (const reg_entry *) NULL;
7665 s++;
252b5132
RH		 7666 }
7667
6588847e
DN		 7668 /* For naked regs, make sure that we are not dealing with an identifier.
7669 This prevents confusing an identifier like `eax_var' with register
7670 `eax'. */
7671 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7672 return (const reg_entry *) NULL;
7673
af6bdddf 7674 *end_op = s;
252b5132
RH		 7675
7676 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7677
5f47d35b 7678 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7679 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7680 {
5f47d35b
AM		 7681 if (is_space_char (*s))
7682 ++s;
7683 if (*s == '(')
7684 {
af6bdddf 7685 ++s;
5f47d35b
AM		 7686 if (is_space_char (*s))
7687 ++s;
7688 if (*s >= '0' && *s <= '7')
7689 {
db557034 7690 int fpr = *s - '0';
af6bdddf 7691 ++s;
5f47d35b
AM		 7692 if (is_space_char (*s))
7693 ++s;
7694 if (*s == ')')
7695 {
7696 *end_op = s + 1;
1e9cc1c2 7697 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 7698 know (r);
7699 return r + fpr;
5f47d35b 7700 }
5f47d35b 7701 }
47926f60 7702 /* We have "%st(" then garbage. */
5f47d35b
AM		 7703 return (const reg_entry *) NULL;
7704 }
7705 }
7706
a60de03c
JB		 7707 if (r == NULL || allow_pseudo_reg)
7708 return r;
7709
0dfbf9d7 7710 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7711 return (const reg_entry *) NULL;
7712
192dc9c6
JB		 7713 if ((r->reg_type.bitfield.reg32
7714 || r->reg_type.bitfield.sreg3
7715 || r->reg_type.bitfield.control
7716 || r->reg_type.bitfield.debug
7717 || r->reg_type.bitfield.test)
7718 && !cpu_arch_flags.bitfield.cpui386)
7719 return (const reg_entry *) NULL;
7720
309d3373
JB		 7721 if (r->reg_type.bitfield.floatreg
7722 && !cpu_arch_flags.bitfield.cpu8087
7723 && !cpu_arch_flags.bitfield.cpu287
7724 && !cpu_arch_flags.bitfield.cpu387)
7725 return (const reg_entry *) NULL;
7726
192dc9c6
JB		 7727 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7728 return (const reg_entry *) NULL;
7729
7730 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7731 return (const reg_entry *) NULL;
7732
40f12533
L		 7733 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7734 return (const reg_entry *) NULL;
7735
db51cc60 7736 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7737 if (!allow_index_reg
db51cc60
L		 7738 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7739 return (const reg_entry *) NULL;
7740
a60de03c
JB		 7741 if (((r->reg_flags & (RegRex64 | RegRex))
7742 || r->reg_type.bitfield.reg64)
40fb9820 7743 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7744 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7745 && flag_code != CODE_64BIT)
20f0a1fc 7746 return (const reg_entry *) NULL;
1ae00879 7747
b7240065
JB		 7748 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7749 return (const reg_entry *) NULL;
7750
252b5132
RH		 7751 return r;
7752}
4d1bb795
JB		 7753
7754/* REG_STRING starts *before* REGISTER_PREFIX. */
7755
7756static const reg_entry *
7757parse_register (char *reg_string, char **end_op)
7758{
7759 const reg_entry *r;
7760
7761 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7762 r = parse_real_register (reg_string, end_op);
7763 else
7764 r = NULL;
7765 if (!r)
7766 {
7767 char *save = input_line_pointer;
7768 char c;
7769 symbolS *symbolP;
7770
7771 input_line_pointer = reg_string;
7772 c = get_symbol_end ();
7773 symbolP = symbol_find (reg_string);
7774 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7775 {
7776 const expressionS *e = symbol_get_value_expression (symbolP);
7777
7778 know (e->X_op == O_register);
4eed87de 7779 know (e->X_add_number >= 0
c3fe08fa 7780 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7781 r = i386_regtab + e->X_add_number;
7782 *end_op = input_line_pointer;
7783 }
7784 *input_line_pointer = c;
7785 input_line_pointer = save;
7786 }
7787 return r;
7788}
7789
7790int
7791i386_parse_name (char *name, expressionS *e, char *nextcharP)
7792{
7793 const reg_entry *r;
7794 char *end = input_line_pointer;
7795
7796 *end = *nextcharP;
7797 r = parse_register (name, &input_line_pointer);
7798 if (r && end <= input_line_pointer)
7799 {
7800 *nextcharP = *input_line_pointer;
7801 *input_line_pointer = 0;
7802 e->X_op = O_register;
7803 e->X_add_number = r - i386_regtab;
7804 return 1;
7805 }
7806 input_line_pointer = end;
7807 *end = 0;
ee86248c 7808 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 7809}
7810
7811void
7812md_operand (expressionS *e)
7813{
ee86248c
JB		 7814 char *end;
7815 const reg_entry *r;
4d1bb795 7816
ee86248c
JB		 7817 switch (*input_line_pointer)
7818 {
7819 case REGISTER_PREFIX:
7820 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 7821 if (r)
7822 {
7823 e->X_op = O_register;
7824 e->X_add_number = r - i386_regtab;
7825 input_line_pointer = end;
7826 }
ee86248c
JB		 7827 break;
7828
7829 case '[':
9c2799c2 7830 gas_assert (intel_syntax);
ee86248c
JB		 7831 end = input_line_pointer++;
7832 expression (e);
7833 if (*input_line_pointer == ']')
7834 {
7835 ++input_line_pointer;
7836 e->X_op_symbol = make_expr_symbol (e);
7837 e->X_add_symbol = NULL;
7838 e->X_add_number = 0;
7839 e->X_op = O_index;
7840 }
7841 else
7842 {
7843 e->X_op = O_absent;
7844 input_line_pointer = end;
7845 }
7846 break;
4d1bb795
JB		 7847 }
7848}
7849
252b5132 7850\f
4cc782b5 7851#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7852const char *md_shortopts = "kVQ:sqn";
252b5132 7853#else
12b55ccc 7854const char *md_shortopts = "qn";
252b5132 7855#endif
6e0b89ee 7856
3e73aa7c 7857#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7858#define OPTION_64 (OPTION_MD_BASE + 1)
7859#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7860#define OPTION_MARCH (OPTION_MD_BASE + 3)
7861#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7862#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7863#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7864#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7865#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7866#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 7867#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 7868#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
b3b91714 7869
99ad8390
NC		 7870struct option md_longopts[] =
7871{
3e73aa7c 7872 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 7873#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7874 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 7875 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7876#endif
b3b91714 7877 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7878 {"march", required_argument, NULL, OPTION_MARCH},
7879 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7880 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7881 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7882 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7883 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7884 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 7885 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 7886 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
252b5132
RH		 7887 {NULL, no_argument, NULL, 0}
7888};
7889size_t md_longopts_size = sizeof (md_longopts);
7890
7891int
9103f4f4 7892md_parse_option (int c, char *arg)
252b5132 7893{
91d6fa6a 7894 unsigned int j;
6305a203 7895 char *arch, *next;
9103f4f4 7896
252b5132
RH		 7897 switch (c)
7898 {
12b55ccc
L		 7899 case 'n':
7900 optimize_align_code = 0;
7901 break;
7902
a38cf1db
AM		 7903 case 'q':
7904 quiet_warnings = 1;
252b5132
RH		 7905 break;
7906
7907#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7908 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7909 should be emitted or not. FIXME: Not implemented. */
7910 case 'Q':
252b5132
RH		 7911 break;
7912
7913 /* -V: SVR4 argument to print version ID. */
7914 case 'V':
7915 print_version_id ();
7916 break;
7917
a38cf1db
AM		 7918 /* -k: Ignore for FreeBSD compatibility. */
7919 case 'k':
252b5132 7920 break;
4cc782b5
ILT		 7921
7922 case 's':
7923 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7924 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7925 break;
99ad8390 7926#endif
321098a5
L		 7927#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7928 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 7929 case OPTION_64:
7930 {
7931 const char **list, **l;
7932
3e73aa7c
JH		 7933 list = bfd_target_list ();
7934 for (l = list; *l != NULL; l++)
8620418b 7935 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7936 || strcmp (*l, "coff-x86-64") == 0
7937 || strcmp (*l, "pe-x86-64") == 0
7938 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7939 {
7940 default_arch = "x86_64";
7941 break;
7942 }
3e73aa7c 7943 if (*l == NULL)
6e0b89ee 7944 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7945 free (list);
7946 }
7947 break;
7948#endif
252b5132 7949
6e0b89ee
AM		 7950 case OPTION_32:
7951 default_arch = "i386";
7952 break;
7953
b3b91714
AM		 7954 case OPTION_DIVIDE:
7955#ifdef SVR4_COMMENT_CHARS
7956 {
7957 char *n, *t;
7958 const char *s;
7959
7960 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7961 t = n;
7962 for (s = i386_comment_chars; *s != '\0'; s++)
7963 if (*s != '/')
7964 *t++ = *s;
7965 *t = '\0';
7966 i386_comment_chars = n;
7967 }
7968#endif
7969 break;
7970
9103f4f4 7971 case OPTION_MARCH:
6305a203
L		 7972 arch = xstrdup (arg);
7973 do
9103f4f4 7974 {
6305a203
L		 7975 if (*arch == '.')
7976 as_fatal (_("Invalid -march= option: `%s'"), arg);
7977 next = strchr (arch, '+');
7978 if (next)
7979 *next++ = '\0';
91d6fa6a 7980 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 7981 {
91d6fa6a 7982 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 7983 {
6305a203 7984 /* Processor. */
91d6fa6a 7985 cpu_arch_name = cpu_arch[j].name;
6305a203 7986 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 7987 cpu_arch_flags = cpu_arch[j].flags;
7988 cpu_arch_isa = cpu_arch[j].type;
7989 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 7990 if (!cpu_arch_tune_set)
7991 {
7992 cpu_arch_tune = cpu_arch_isa;
7993 cpu_arch_tune_flags = cpu_arch_isa_flags;
7994 }
7995 break;
7996 }
91d6fa6a
NC		 7997 else if (*cpu_arch [j].name == '.'
7998 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 7999 {
8000 /* ISA entension. */
8001 i386_cpu_flags flags;
309d3373
JB		 8002
8003 if (strncmp (arch, "no", 2))
8004 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 8005 cpu_arch[j].flags);
309d3373
JB		 8006 else
8007 flags = cpu_flags_and_not (cpu_arch_flags,
91d6fa6a 8008 cpu_arch[j].flags);
0dfbf9d7 8009 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8010 {
8011 if (cpu_sub_arch_name)
8012 {
8013 char *name = cpu_sub_arch_name;
8014 cpu_sub_arch_name = concat (name,
91d6fa6a 8015 cpu_arch[j].name,
1bf57e9f 8016 (const char *) NULL);
6305a203
L		 8017 free (name);
8018 }
8019 else
91d6fa6a 8020 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203
L		 8021 cpu_arch_flags = flags;
8022 }
8023 break;
ccc9c027 8024 }
9103f4f4 8025 }
6305a203 8026
91d6fa6a 8027 if (j >= ARRAY_SIZE (cpu_arch))
6305a203
L		 8028 as_fatal (_("Invalid -march= option: `%s'"), arg);
8029
8030 arch = next;
9103f4f4 8031 }
6305a203 8032 while (next != NULL );
9103f4f4
L		 8033 break;
8034
8035 case OPTION_MTUNE:
8036 if (*arg == '.')
8037 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
91d6fa6a 8038 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8039 {
91d6fa6a 8040 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8041 {
ccc9c027 8042 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8043 cpu_arch_tune = cpu_arch [j].type;
8044 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8045 break;
8046 }
8047 }
91d6fa6a 8048 if (j >= ARRAY_SIZE (cpu_arch))
9103f4f4
L		 8049 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8050 break;
8051
1efbbeb4
L		 8052 case OPTION_MMNEMONIC:
8053 if (strcasecmp (arg, "att") == 0)
8054 intel_mnemonic = 0;
8055 else if (strcasecmp (arg, "intel") == 0)
8056 intel_mnemonic = 1;
8057 else
8058 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8059 break;
8060
8061 case OPTION_MSYNTAX:
8062 if (strcasecmp (arg, "att") == 0)
8063 intel_syntax = 0;
8064 else if (strcasecmp (arg, "intel") == 0)
8065 intel_syntax = 1;
8066 else
8067 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8068 break;
8069
8070 case OPTION_MINDEX_REG:
8071 allow_index_reg = 1;
8072 break;
8073
8074 case OPTION_MNAKED_REG:
8075 allow_naked_reg = 1;
8076 break;
8077
8078 case OPTION_MOLD_GCC:
8079 old_gcc = 1;
1efbbeb4
L		 8080 break;
8081
c0f3af97
L		 8082 case OPTION_MSSE2AVX:
8083 sse2avx = 1;
8084 break;
8085
daf50ae7
L		 8086 case OPTION_MSSE_CHECK:
8087 if (strcasecmp (arg, "error") == 0)
8088 sse_check = sse_check_error;
8089 else if (strcasecmp (arg, "warning") == 0)
8090 sse_check = sse_check_warning;
8091 else if (strcasecmp (arg, "none") == 0)
8092 sse_check = sse_check_none;
8093 else
8094 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8095 break;
8096
252b5132
RH		 8097 default:
8098 return 0;
8099 }
8100 return 1;
8101}
8102
8a2c8fef
L		 8103#define MESSAGE_TEMPLATE \
8104" "
8105
8106static void
8107show_arch (FILE *stream, int ext)
8108{
8109 static char message[] = MESSAGE_TEMPLATE;
8110 char *start = message + 27;
8111 char *p;
8112 int size = sizeof (MESSAGE_TEMPLATE);
8113 int left;
8114 const char *name;
8115 int len;
8116 unsigned int j;
8117
8118 p = start;
8119 left = size - (start - message);
8120 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8121 {
8122 /* Should it be skipped? */
8123 if (cpu_arch [j].skip)
8124 continue;
8125
8126 name = cpu_arch [j].name;
8127 len = cpu_arch [j].len;
8128 if (*name == '.')
8129 {
8130 /* It is an extension. Skip if we aren't asked to show it. */
8131 if (ext)
8132 {
8133 name++;
8134 len--;
8135 }
8136 else
8137 continue;
8138 }
8139 else if (ext)
8140 {
8141 /* It is an processor. Skip if we show only extension. */
8142 continue;
8143 }
8144
8145 /* Reserve 2 spaces for ", " or ",\0" */
8146 left -= len + 2;
8147
8148 /* Check if there is any room. */
8149 if (left >= 0)
8150 {
8151 if (p != start)
8152 {
8153 *p++ = ',';
8154 *p++ = ' ';
8155 }
8156 p = mempcpy (p, name, len);
8157 }
8158 else
8159 {
8160 /* Output the current message now and start a new one. */
8161 *p++ = ',';
8162 *p = '\0';
8163 fprintf (stream, "%s\n", message);
8164 p = start;
8165 left = size - (start - message) - len - 2;
8166
8167 gas_assert (left >= 0);
8168
8169 p = mempcpy (p, name, len);
8170 }
8171 }
8172
8173 *p = '\0';
8174 fprintf (stream, "%s\n", message);
8175}
8176
252b5132 8177void
8a2c8fef 8178md_show_usage (FILE *stream)
252b5132 8179{
4cc782b5
ILT		 8180#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8181 fprintf (stream, _("\
a38cf1db
AM		 8182 -Q ignored\n\
8183 -V print assembler version number\n\
b3b91714
AM		 8184 -k ignored\n"));
8185#endif
8186 fprintf (stream, _("\
12b55ccc 8187 -n Do not optimize code alignment\n\
b3b91714
AM		 8188 -q quieten some warnings\n"));
8189#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8190 fprintf (stream, _("\
a38cf1db 8191 -s ignored\n"));
b3b91714 8192#endif
321098a5
L		 8193#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8194 || defined (TE_PE) || defined (TE_PEP))
751d281c
L		 8195 fprintf (stream, _("\
8196 --32/--64 generate 32bit/64bit code\n"));
8197#endif
b3b91714
AM		 8198#ifdef SVR4_COMMENT_CHARS
8199 fprintf (stream, _("\
8200 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8201#else
8202 fprintf (stream, _("\
b3b91714 8203 --divide ignored\n"));
4cc782b5 8204#endif
9103f4f4 8205 fprintf (stream, _("\
6305a203 8206 -march=CPU[,+EXTENSION...]\n\
8a2c8fef
L		 8207 generate code for CPU and EXTENSION, CPU is one of:\n"));
8208 show_arch (stream, 0);
8209 fprintf (stream, _("\
8210 EXTENSION is combination of:\n"));
8211 show_arch (stream, 1);
6305a203 8212 fprintf (stream, _("\
8a2c8fef
L		 8213 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8214 show_arch (stream, 0);
ba104c83 8215 fprintf (stream, _("\
c0f3af97
L		 8216 -msse2avx encode SSE instructions with VEX prefix\n"));
8217 fprintf (stream, _("\
daf50ae7
L		 8218 -msse-check=[none|error|warning]\n\
8219 check SSE instructions\n"));
8220 fprintf (stream, _("\
ba104c83
L		 8221 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8222 fprintf (stream, _("\
8223 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8224 fprintf (stream, _("\
8225 -mindex-reg support pseudo index registers\n"));
8226 fprintf (stream, _("\
8227 -mnaked-reg don't require `%%' prefix for registers\n"));
8228 fprintf (stream, _("\
8229 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8230}
8231
3e73aa7c 8232#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8233 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8234 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8235
8236/* Pick the target format to use. */
8237
47926f60 8238const char *
e3bb37b5 8239i386_target_format (void)
252b5132 8240{
3e73aa7c 8241 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 8242 {
8243 set_code_flag (CODE_64BIT);
0dfbf9d7 8244 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8245 {
8246 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8247 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8248 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8249 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8250 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8251 cpu_arch_isa_flags.bitfield.cpui686 = 1;
bd5295b2 8252 cpu_arch_isa_flags.bitfield.cpuclflush = 1;
40fb9820 8253 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 8254 cpu_arch_isa_flags.bitfield.cpusse = 1;
8255 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
711eedef 8256 cpu_arch_isa_flags.bitfield.cpulm = 1;
40fb9820 8257 }
0dfbf9d7 8258 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8259 {
8260 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8261 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8262 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8263 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8264 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8265 cpu_arch_tune_flags.bitfield.cpui686 = 1;
bd5295b2 8266 cpu_arch_tune_flags.bitfield.cpuclflush = 1;
40fb9820 8267 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 8268 cpu_arch_tune_flags.bitfield.cpusse = 1;
8269 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8270 }
9103f4f4 8271 }
3e73aa7c 8272 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 8273 {
8274 set_code_flag (CODE_32BIT);
0dfbf9d7 8275 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8276 {
8277 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8278 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8279 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8280 }
0dfbf9d7 8281 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8282 {
8283 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8284 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8285 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8286 }
9103f4f4 8287 }
3e73aa7c
JH		 8288 else
8289 as_fatal (_("Unknown architecture"));
252b5132
RH		 8290 switch (OUTPUT_FLAVOR)
8291 {
9384f2ff 8292#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8293 case bfd_target_aout_flavour:
47926f60 8294 return AOUT_TARGET_FORMAT;
4c63da97 8295#endif
9384f2ff
AM		 8296#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8297# if defined (TE_PE) || defined (TE_PEP)
8298 case bfd_target_coff_flavour:
8299 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8300# elif defined (TE_GO32)
0561d57c
JK		 8301 case bfd_target_coff_flavour:
8302 return "coff-go32";
9384f2ff 8303# else
252b5132
RH		 8304 case bfd_target_coff_flavour:
8305 return "coff-i386";
9384f2ff 8306# endif
4c63da97 8307#endif
3e73aa7c 8308#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8309 case bfd_target_elf_flavour:
3e73aa7c 8310 {
e5cb08ac 8311 if (flag_code == CODE_64BIT)
4fa24527
JB		 8312 {
8313 object_64bit = 1;
8314 use_rela_relocations = 1;
8315 }
3632d14b 8316 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 8317 {
8318 if (flag_code != CODE_64BIT)
8319 as_fatal (_("Intel L1OM is 64bit only"));
8320 return ELF_TARGET_L1OM_FORMAT;
8321 }
8322 else
8323 return (flag_code == CODE_64BIT
8324 ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT);
3e73aa7c 8325 }
e57f8c65
TG		 8326#endif
8327#if defined (OBJ_MACH_O)
8328 case bfd_target_mach_o_flavour:
8329 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 8330#endif
252b5132
RH		 8331 default:
8332 abort ();
8333 return NULL;
8334 }
8335}
8336
47926f60 8337#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8338
8339#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8340void
8341i386_elf_emit_arch_note (void)
a847613f 8342{
718ddfc0 8343 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8344 {
8345 char *p;
8346 asection *seg = now_seg;
8347 subsegT subseg = now_subseg;
8348 Elf_Internal_Note i_note;
8349 Elf_External_Note e_note;
8350 asection *note_secp;
8351 int len;
8352
8353 /* Create the .note section. */
8354 note_secp = subseg_new (".note", 0);
8355 bfd_set_section_flags (stdoutput,
8356 note_secp,
8357 SEC_HAS_CONTENTS | SEC_READONLY);
8358
8359 /* Process the arch string. */
8360 len = strlen (cpu_arch_name);
8361
8362 i_note.namesz = len + 1;
8363 i_note.descsz = 0;
8364 i_note.type = NT_ARCH;
8365 p = frag_more (sizeof (e_note.namesz));
8366 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8367 p = frag_more (sizeof (e_note.descsz));
8368 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8369 p = frag_more (sizeof (e_note.type));
8370 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8371 p = frag_more (len + 1);
8372 strcpy (p, cpu_arch_name);
8373
8374 frag_align (2, 0, 0);
8375
8376 subseg_set (seg, subseg);
8377 }
8378}
8379#endif
252b5132 8380\f
252b5132
RH		 8381symbolS *
8382md_undefined_symbol (name)
8383 char *name;
8384{
18dc2407
ILT		 8385 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8386 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8387 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8388 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8389 {
8390 if (!GOT_symbol)
8391 {
8392 if (symbol_find (name))
8393 as_bad (_("GOT already in symbol table"));
8394 GOT_symbol = symbol_new (name, undefined_section,
8395 (valueT) 0, &zero_address_frag);
8396 };
8397 return GOT_symbol;
8398 }
252b5132
RH		 8399 return 0;
8400}
8401
8402/* Round up a section size to the appropriate boundary. */
47926f60 8403
252b5132
RH		 8404valueT
8405md_section_align (segment, size)
ab9da554 8406 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8407 valueT size;
8408{
4c63da97
AM		 8409#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8410 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8411 {
8412 /* For a.out, force the section size to be aligned. If we don't do
8413 this, BFD will align it for us, but it will not write out the
8414 final bytes of the section. This may be a bug in BFD, but it is
8415 easier to fix it here since that is how the other a.out targets
8416 work. */
8417 int align;
8418
8419 align = bfd_get_section_alignment (stdoutput, segment);
8420 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8421 }
252b5132
RH		 8422#endif
8423
8424 return size;
8425}
8426
8427/* On the i386, PC-relative offsets are relative to the start of the
8428 next instruction. That is, the address of the offset, plus its
8429 size, since the offset is always the last part of the insn. */
8430
8431long
e3bb37b5 8432md_pcrel_from (fixS *fixP)
252b5132
RH		 8433{
8434 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8435}
8436
8437#ifndef I386COFF
8438
8439static void
e3bb37b5 8440s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8441{
29b0f896 8442 int temp;
252b5132 8443
8a75718c
JB		 8444#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8445 if (IS_ELF)
8446 obj_elf_section_change_hook ();
8447#endif
252b5132
RH		 8448 temp = get_absolute_expression ();
8449 subseg_set (bss_section, (subsegT) temp);
8450 demand_empty_rest_of_line ();
8451}
8452
8453#endif
8454
252b5132 8455void
e3bb37b5 8456i386_validate_fix (fixS *fixp)
252b5132
RH		 8457{
8458 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8459 {
23df1078
JH		 8460 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8461 {
4fa24527 8462 if (!object_64bit)
23df1078
JH		 8463 abort ();
8464 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8465 }
8466 else
8467 {
4fa24527 8468 if (!object_64bit)
d6ab8113
JB		 8469 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8470 else
8471 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8472 }
252b5132
RH		 8473 fixp->fx_subsy = 0;
8474 }
8475}
8476
252b5132
RH		 8477arelent *
8478tc_gen_reloc (section, fixp)
ab9da554 8479 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8480 fixS *fixp;
8481{
8482 arelent *rel;
8483 bfd_reloc_code_real_type code;
8484
8485 switch (fixp->fx_r_type)
8486 {
3e73aa7c
JH		 8487 case BFD_RELOC_X86_64_PLT32:
8488 case BFD_RELOC_X86_64_GOT32:
8489 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8490 case BFD_RELOC_386_PLT32:
8491 case BFD_RELOC_386_GOT32:
8492 case BFD_RELOC_386_GOTOFF:
8493 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8494 case BFD_RELOC_386_TLS_GD:
8495 case BFD_RELOC_386_TLS_LDM:
8496 case BFD_RELOC_386_TLS_LDO_32:
8497 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8498 case BFD_RELOC_386_TLS_IE:
8499 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8500 case BFD_RELOC_386_TLS_LE_32:
8501 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8502 case BFD_RELOC_386_TLS_GOTDESC:
8503 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8504 case BFD_RELOC_X86_64_TLSGD:
8505 case BFD_RELOC_X86_64_TLSLD:
8506 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8507 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8508 case BFD_RELOC_X86_64_GOTTPOFF:
8509 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8510 case BFD_RELOC_X86_64_TPOFF64:
8511 case BFD_RELOC_X86_64_GOTOFF64:
8512 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8513 case BFD_RELOC_X86_64_GOT64:
8514 case BFD_RELOC_X86_64_GOTPCREL64:
8515 case BFD_RELOC_X86_64_GOTPC64:
8516 case BFD_RELOC_X86_64_GOTPLT64:
8517 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8518 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8519 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8520 case BFD_RELOC_RVA:
8521 case BFD_RELOC_VTABLE_ENTRY:
8522 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8523#ifdef TE_PE
8524 case BFD_RELOC_32_SECREL:
8525#endif
252b5132
RH		 8526 code = fixp->fx_r_type;
8527 break;
dbbaec26
L		 8528 case BFD_RELOC_X86_64_32S:
8529 if (!fixp->fx_pcrel)
8530 {
8531 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8532 code = fixp->fx_r_type;
8533 break;
8534 }
252b5132 8535 default:
93382f6d 8536 if (fixp->fx_pcrel)
252b5132 8537 {
93382f6d
AM		 8538 switch (fixp->fx_size)
8539 {
8540 default:
b091f402
AM		 8541 as_bad_where (fixp->fx_file, fixp->fx_line,
8542 _("can not do %d byte pc-relative relocation"),
8543 fixp->fx_size);
93382f6d
AM		 8544 code = BFD_RELOC_32_PCREL;
8545 break;
8546 case 1: code = BFD_RELOC_8_PCREL; break;
8547 case 2: code = BFD_RELOC_16_PCREL; break;
8548 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8549#ifdef BFD64
8550 case 8: code = BFD_RELOC_64_PCREL; break;
8551#endif
93382f6d
AM		 8552 }
8553 }
8554 else
8555 {
8556 switch (fixp->fx_size)
8557 {
8558 default:
b091f402
AM		 8559 as_bad_where (fixp->fx_file, fixp->fx_line,
8560 _("can not do %d byte relocation"),
8561 fixp->fx_size);
93382f6d
AM		 8562 code = BFD_RELOC_32;
8563 break;
8564 case 1: code = BFD_RELOC_8; break;
8565 case 2: code = BFD_RELOC_16; break;
8566 case 4: code = BFD_RELOC_32; break;
937149dd 8567#ifdef BFD64
3e73aa7c 8568 case 8: code = BFD_RELOC_64; break;
937149dd 8569#endif
93382f6d 8570 }
252b5132
RH		 8571 }
8572 break;
8573 }
252b5132 8574
d182319b
JB		 8575 if ((code == BFD_RELOC_32
8576 || code == BFD_RELOC_32_PCREL
8577 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8578 && GOT_symbol
8579 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8580 {
4fa24527 8581 if (!object_64bit)
d6ab8113
JB		 8582 code = BFD_RELOC_386_GOTPC;
8583 else
8584 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8585 }
7b81dfbb
AJ		 8586 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8587 && GOT_symbol
8588 && fixp->fx_addsy == GOT_symbol)
8589 {
8590 code = BFD_RELOC_X86_64_GOTPC64;
8591 }
252b5132
RH		 8592
8593 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8594 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8595 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8596
8597 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8598
3e73aa7c
JH		 8599 if (!use_rela_relocations)
8600 {
8601 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8602 vtable entry to be used in the relocation's section offset. */
8603 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8604 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8605#if defined (OBJ_COFF) && defined (TE_PE)
8606 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8607 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8608 else
8609#endif
c6682705 8610 rel->addend = 0;
3e73aa7c
JH		 8611 }
8612 /* Use the rela in 64bit mode. */
252b5132 8613 else
3e73aa7c 8614 {
062cd5e7
AS		 8615 if (!fixp->fx_pcrel)
8616 rel->addend = fixp->fx_offset;
8617 else
8618 switch (code)
8619 {
8620 case BFD_RELOC_X86_64_PLT32:
8621 case BFD_RELOC_X86_64_GOT32:
8622 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8623 case BFD_RELOC_X86_64_TLSGD:
8624 case BFD_RELOC_X86_64_TLSLD:
8625 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8626 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8627 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8628 rel->addend = fixp->fx_offset - fixp->fx_size;
8629 break;
8630 default:
8631 rel->addend = (section->vma
8632 - fixp->fx_size
8633 + fixp->fx_addnumber
8634 + md_pcrel_from (fixp));
8635 break;
8636 }
3e73aa7c
JH		 8637 }
8638
252b5132
RH		 8639 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8640 if (rel->howto == NULL)
8641 {
8642 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8643 _("cannot represent relocation type %s"),
252b5132
RH		 8644 bfd_get_reloc_code_name (code));
8645 /* Set howto to a garbage value so that we can keep going. */
8646 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 8647 gas_assert (rel->howto != NULL);
252b5132
RH		 8648 }
8649
8650 return rel;
8651}
8652
ee86248c 8653#include "tc-i386-intel.c"
54cfded0 8654
a60de03c
JB		 8655void
8656tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 8657{
a60de03c
JB		 8658 int saved_naked_reg;
8659 char saved_register_dot;
54cfded0 8660
a60de03c
JB		 8661 saved_naked_reg = allow_naked_reg;
8662 allow_naked_reg = 1;
8663 saved_register_dot = register_chars['.'];
8664 register_chars['.'] = '.';
8665 allow_pseudo_reg = 1;
8666 expression_and_evaluate (exp);
8667 allow_pseudo_reg = 0;
8668 register_chars['.'] = saved_register_dot;
8669 allow_naked_reg = saved_naked_reg;
8670
8671 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 8672 {
a60de03c
JB		 8673 if ((addressT) exp->X_add_number < i386_regtab_size)
8674 {
8675 exp->X_op = O_constant;
8676 exp->X_add_number = i386_regtab[exp->X_add_number]
8677 .dw2_regnum[flag_code >> 1];
8678 }
8679 else
8680 exp->X_op = O_illegal;
54cfded0 8681 }
54cfded0
AM		 8682}
8683
8684void
8685tc_x86_frame_initial_instructions (void)
8686{
a60de03c
JB		 8687 static unsigned int sp_regno[2];
8688
8689 if (!sp_regno[flag_code >> 1])
8690 {
8691 char *saved_input = input_line_pointer;
8692 char sp[][4] = {"esp", "rsp"};
8693 expressionS exp;
a4447b93 8694
a60de03c
JB		 8695 input_line_pointer = sp[flag_code >> 1];
8696 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 8697 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 8698 sp_regno[flag_code >> 1] = exp.X_add_number;
8699 input_line_pointer = saved_input;
8700 }
a4447b93 8701
a60de03c 8702 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 8703 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8704}
d2b2c203
DJ		 8705
8706int
8707i386_elf_section_type (const char *str, size_t len)
8708{
8709 if (flag_code == CODE_64BIT
8710 && len == sizeof ("unwind") - 1
8711 && strncmp (str, "unwind", 6) == 0)
8712 return SHT_X86_64_UNWIND;
8713
8714 return -1;
8715}
bb41ade5 8716
ad5fec3b
EB		 8717#ifdef TE_SOLARIS
8718void
8719i386_solaris_fix_up_eh_frame (segT sec)
8720{
8721 if (flag_code == CODE_64BIT)
8722 elf_section_type (sec) = SHT_X86_64_UNWIND;
8723}
8724#endif
8725
bb41ade5
AM		 8726#ifdef TE_PE
8727void
8728tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8729{
91d6fa6a 8730 expressionS exp;
bb41ade5 8731
91d6fa6a
NC		 8732 exp.X_op = O_secrel;
8733 exp.X_add_symbol = symbol;
8734 exp.X_add_number = 0;
8735 emit_expr (&exp, size);
bb41ade5
AM		 8736}
8737#endif
3b22753a
L		 8738
8739#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8740/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8741
01e1a5bc 8742bfd_vma
3b22753a
L		 8743x86_64_section_letter (int letter, char **ptr_msg)
8744{
8745 if (flag_code == CODE_64BIT)
8746 {
8747 if (letter == 'l')
8748 return SHF_X86_64_LARGE;
8749
8750 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8751 }
3b22753a 8752 else
64e74474 8753 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8754 return -1;
8755}
8756
01e1a5bc 8757bfd_vma
3b22753a
L		 8758x86_64_section_word (char *str, size_t len)
8759{
8620418b 8760 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8761 return SHF_X86_64_LARGE;
8762
8763 return -1;
8764}
8765
8766static void
8767handle_large_common (int small ATTRIBUTE_UNUSED)
8768{
8769 if (flag_code != CODE_64BIT)
8770 {
8771 s_comm_internal (0, elf_common_parse);
8772 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8773 }
8774 else
8775 {
8776 static segT lbss_section;
8777 asection *saved_com_section_ptr = elf_com_section_ptr;
8778 asection *saved_bss_section = bss_section;
8779
8780 if (lbss_section == NULL)
8781 {
8782 flagword applicable;
8783 segT seg = now_seg;
8784 subsegT subseg = now_subseg;
8785
8786 /* The .lbss section is for local .largecomm symbols. */
8787 lbss_section = subseg_new (".lbss", 0);
8788 applicable = bfd_applicable_section_flags (stdoutput);
8789 bfd_set_section_flags (stdoutput, lbss_section,
8790 applicable & SEC_ALLOC);
8791 seg_info (lbss_section)->bss = 1;
8792
8793 subseg_set (seg, subseg);
8794 }
8795
8796 elf_com_section_ptr = &_bfd_elf_large_com_section;
8797 bss_section = lbss_section;
8798
8799 s_comm_internal (0, elf_common_parse);
8800
8801 elf_com_section_ptr = saved_com_section_ptr;
8802 bss_section = saved_bss_section;
8803 }
8804}
8805#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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