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Improve performance of large restore commands
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
d382c579
TG		 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
4 2012
47926f60 5 Free Software Foundation, Inc.
252b5132
RH		 6
7 This file is part of GAS, the GNU Assembler.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
ec2655a6 11 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 02110-1301, USA. */
252b5132 23
47926f60
KH		 24/* Intel 80386 machine specific gas.
25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 26 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 28 Bugs & suggestions are completely welcome. This is free software.
29 Please help us make it better. */
252b5132 30
252b5132 31#include "as.h"
3882b010 32#include "safe-ctype.h"
252b5132 33#include "subsegs.h"
316e2c05 34#include "dwarf2dbg.h"
54cfded0 35#include "dw2gencfi.h"
d2b2c203 36#include "elf/x86-64.h"
40fb9820 37#include "opcodes/i386-init.h"
252b5132 38
252b5132
RH		 39#ifndef REGISTER_WARNINGS
40#define REGISTER_WARNINGS 1
41#endif
42
c3332e24 43#ifndef INFER_ADDR_PREFIX
eecb386c 44#define INFER_ADDR_PREFIX 1
c3332e24
AM		 45#endif
46
29b0f896
AM		 47#ifndef DEFAULT_ARCH
48#define DEFAULT_ARCH "i386"
246fcdee 49#endif
252b5132 50
edde18a5
AM		 51#ifndef INLINE
52#if __GNUC__ >= 2
53#define INLINE __inline__
54#else
55#define INLINE
56#endif
57#endif
58
6305a203
L		 59/* Prefixes will be emitted in the order defined below.
60 WAIT_PREFIX must be the first prefix since FWAIT is really is an
61 instruction, and so must come before any prefixes.
62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 63 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 64#define WAIT_PREFIX 0
65#define SEG_PREFIX 1
66#define ADDR_PREFIX 2
67#define DATA_PREFIX 3
c32fa91d 68#define REP_PREFIX 4
42164a71 69#define HLE_PREFIX REP_PREFIX
7e8b059b 70#define BND_PREFIX REP_PREFIX
c32fa91d
L		 71#define LOCK_PREFIX 5
72#define REX_PREFIX 6 /* must come last. */
73#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 74
75/* we define the syntax here (modulo base,index,scale syntax) */
76#define REGISTER_PREFIX '%'
77#define IMMEDIATE_PREFIX '$'
78#define ABSOLUTE_PREFIX '*'
79
80/* these are the instruction mnemonic suffixes in AT&T syntax or
81 memory operand size in Intel syntax. */
82#define WORD_MNEM_SUFFIX 'w'
83#define BYTE_MNEM_SUFFIX 'b'
84#define SHORT_MNEM_SUFFIX 's'
85#define LONG_MNEM_SUFFIX 'l'
86#define QWORD_MNEM_SUFFIX 'q'
87#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 88#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 89#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 90/* Intel Syntax. Use a non-ascii letter since since it never appears
91 in instructions. */
92#define LONG_DOUBLE_MNEM_SUFFIX '\1'
93
94#define END_OF_INSN '\0'
95
96/*
97 'templates' is for grouping together 'template' structures for opcodes
98 of the same name. This is only used for storing the insns in the grand
99 ole hash table of insns.
100 The templates themselves start at START and range up to (but not including)
101 END.
102 */
103typedef struct
104{
d3ce72d0
NC		 105 const insn_template *start;
106 const insn_template *end;
6305a203
L		 107}
108templates;
109
110/* 386 operand encoding bytes: see 386 book for details of this. */
111typedef struct
112{
113 unsigned int regmem; /* codes register or memory operand */
114 unsigned int reg; /* codes register operand (or extended opcode) */
115 unsigned int mode; /* how to interpret regmem & reg */
116}
117modrm_byte;
118
119/* x86-64 extension prefix. */
120typedef int rex_byte;
121
6305a203
L		 122/* 386 opcode byte to code indirect addressing. */
123typedef struct
124{
125 unsigned base;
126 unsigned index;
127 unsigned scale;
128}
129sib_byte;
130
6305a203
L		 131/* x86 arch names, types and features */
132typedef struct
133{
134 const char *name; /* arch name */
8a2c8fef 135 unsigned int len; /* arch string length */
6305a203
L		 136 enum processor_type type; /* arch type */
137 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 138 unsigned int skip; /* show_arch should skip this. */
22109423 139 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 140}
141arch_entry;
142
78f12dd3 143static void update_code_flag (int, int);
e3bb37b5
L		 144static void set_code_flag (int);
145static void set_16bit_gcc_code_flag (int);
146static void set_intel_syntax (int);
1efbbeb4 147static void set_intel_mnemonic (int);
db51cc60 148static void set_allow_index_reg (int);
7bab8ab5 149static void set_check (int);
e3bb37b5 150static void set_cpu_arch (int);
6482c264 151#ifdef TE_PE
e3bb37b5 152static void pe_directive_secrel (int);
6482c264 153#endif
e3bb37b5
L		 154static void signed_cons (int);
155static char *output_invalid (int c);
ee86248c
JB		 156static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
157 const char *);
158static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
159 const char *);
a7619375 160static int i386_att_operand (char *);
e3bb37b5 161static int i386_intel_operand (char *, int);
ee86248c
JB		 162static int i386_intel_simplify (expressionS *);
163static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 164static const reg_entry *parse_register (char *, char **);
165static char *parse_insn (char *, char *);
166static char *parse_operands (char *, const char *);
167static void swap_operands (void);
4d456e3d 168static void swap_2_operands (int, int);
e3bb37b5
L		 169static void optimize_imm (void);
170static void optimize_disp (void);
d3ce72d0 171static const insn_template *match_template (void);
e3bb37b5
L		 172static int check_string (void);
173static int process_suffix (void);
174static int check_byte_reg (void);
175static int check_long_reg (void);
176static int check_qword_reg (void);
177static int check_word_reg (void);
178static int finalize_imm (void);
179static int process_operands (void);
180static const seg_entry *build_modrm_byte (void);
181static void output_insn (void);
182static void output_imm (fragS *, offsetT);
183static void output_disp (fragS *, offsetT);
29b0f896 184#ifndef I386COFF
e3bb37b5 185static void s_bss (int);
252b5132 186#endif
17d4e2a2
L		 187#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
188static void handle_large_common (int small ATTRIBUTE_UNUSED);
189#endif
252b5132 190
a847613f 191static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 192
43234a1e
L		 193/* This struct describes rounding control and SAE in the instruction. */
194struct RC_Operation
195{
196 enum rc_type
197 {
198 rne = 0,
199 rd,
200 ru,
201 rz,
202 saeonly
203 } type;
204 int operand;
205};
206
207static struct RC_Operation rc_op;
208
209/* The struct describes masking, applied to OPERAND in the instruction.
210 MASK is a pointer to the corresponding mask register. ZEROING tells
211 whether merging or zeroing mask is used. */
212struct Mask_Operation
213{
214 const reg_entry *mask;
215 unsigned int zeroing;
216 /* The operand where this operation is associated. */
217 int operand;
218};
219
220static struct Mask_Operation mask_op;
221
222/* The struct describes broadcasting, applied to OPERAND. FACTOR is
223 broadcast factor. */
224struct Broadcast_Operation
225{
226 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
227 int type;
228
229 /* Index of broadcasted operand. */
230 int operand;
231};
232
233static struct Broadcast_Operation broadcast_op;
234
c0f3af97
L		 235/* VEX prefix. */
236typedef struct
237{
43234a1e
L		 238 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
239 unsigned char bytes[4];
c0f3af97
L		 240 unsigned int length;
241 /* Destination or source register specifier. */
242 const reg_entry *register_specifier;
243} vex_prefix;
244
252b5132 245/* 'md_assemble ()' gathers together information and puts it into a
47926f60 246 i386_insn. */
252b5132 247
520dc8e8
AM		 248union i386_op
249 {
250 expressionS *disps;
251 expressionS *imms;
252 const reg_entry *regs;
253 };
254
a65babc9
L		 255enum i386_error
256 {
86e026a4 257 operand_size_mismatch,
a65babc9
L		 258 operand_type_mismatch,
259 register_type_mismatch,
260 number_of_operands_mismatch,
261 invalid_instruction_suffix,
262 bad_imm4,
263 old_gcc_only,
264 unsupported_with_intel_mnemonic,
265 unsupported_syntax,
6c30d220
L		 266 unsupported,
267 invalid_vsib_address,
7bab8ab5 268 invalid_vector_register_set,
43234a1e
L		 269 unsupported_vector_index_register,
270 unsupported_broadcast,
271 broadcast_not_on_src_operand,
272 broadcast_needed,
273 unsupported_masking,
274 mask_not_on_destination,
275 no_default_mask,
276 unsupported_rc_sae,
277 rc_sae_operand_not_last_imm,
278 invalid_register_operand,
279 try_vector_disp8
a65babc9
L		 280 };
281
252b5132
RH		 282struct _i386_insn
283 {
47926f60 284 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 285 insn_template tm;
252b5132 286
7d5e4556
L		 287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
252b5132
RH		 289 char suffix;
290
47926f60 291 /* OPERANDS gives the number of given operands. */
252b5132
RH		 292 unsigned int operands;
293
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
47926f60 296 operands. */
252b5132
RH		 297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
298
299 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 300 use OP[i] for the corresponding operand. */
40fb9820 301 i386_operand_type types[MAX_OPERANDS];
252b5132 302
520dc8e8
AM		 303 /* Displacement expression, immediate expression, or register for each
304 operand. */
305 union i386_op op[MAX_OPERANDS];
252b5132 306
3e73aa7c
JH		 307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309#define Operand_PCrel 1
310
252b5132 311 /* Relocation type for operand */
f86103b7 312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 313
252b5132
RH		 314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
319
320 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 321 explicit segment overrides are given. */
ce8a8b2f 322 const seg_entry *seg[2];
252b5132
RH		 323
324 /* PREFIX holds all the given prefix opcodes (usually null).
325 PREFIXES is the number of prefix opcodes. */
326 unsigned int prefixes;
327 unsigned char prefix[MAX_PREFIXES];
328
329 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 330 addressing modes of this insn are encoded. */
252b5132 331 modrm_byte rm;
3e73aa7c 332 rex_byte rex;
43234a1e 333 rex_byte vrex;
252b5132 334 sib_byte sib;
c0f3af97 335 vex_prefix vex;
b6169b20 336
43234a1e
L		 337 /* Masking attributes. */
338 struct Mask_Operation *mask;
339
340 /* Rounding control and SAE attributes. */
341 struct RC_Operation *rounding;
342
343 /* Broadcasting attributes. */
344 struct Broadcast_Operation *broadcast;
345
346 /* Compressed disp8*N attribute. */
347 unsigned int memshift;
348
b6169b20 349 /* Swap operand in encoding. */
4473e004 350 unsigned int swap_operand;
891edac4 351
a501d77e
L		 352 /* Prefer 8bit or 32bit displacement in encoding. */
353 enum
354 {
355 disp_encoding_default = 0,
356 disp_encoding_8bit,
357 disp_encoding_32bit
358 } disp_encoding;
f8a5c266 359
d5de92cf
L		 360 /* REP prefix. */
361 const char *rep_prefix;
362
165de32a
L		 363 /* HLE prefix. */
364 const char *hle_prefix;
42164a71 365
7e8b059b
L		 366 /* Have BND prefix. */
367 const char *bnd_prefix;
368
43234a1e
L		 369 /* Need VREX to support upper 16 registers. */
370 int need_vrex;
371
891edac4 372 /* Error message. */
a65babc9 373 enum i386_error error;
252b5132
RH		 374 };
375
376typedef struct _i386_insn i386_insn;
377
43234a1e
L		 378/* Link RC type with corresponding string, that'll be looked for in
379 asm. */
380struct RC_name
381{
382 enum rc_type type;
383 const char *name;
384 unsigned int len;
385};
386
387static const struct RC_name RC_NamesTable[] =
388{
389 { rne, STRING_COMMA_LEN ("rn-sae") },
390 { rd, STRING_COMMA_LEN ("rd-sae") },
391 { ru, STRING_COMMA_LEN ("ru-sae") },
392 { rz, STRING_COMMA_LEN ("rz-sae") },
393 { saeonly, STRING_COMMA_LEN ("sae") },
394};
395
252b5132
RH		 396/* List of chars besides those in app.c:symbol_chars that can start an
397 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 398const char extra_symbol_chars[] = "*%-([{"
252b5132 399#ifdef LEX_AT
32137342
NC		 400 "@"
401#endif
402#ifdef LEX_QM
403 "?"
252b5132 404#endif
32137342 405 ;
252b5132 406
29b0f896
AM		 407#if (defined (TE_I386AIX) \
408 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 409 && !defined (TE_GNU) \
29b0f896 410 && !defined (TE_LINUX) \
8d63c93e
RM		 411 && !defined (TE_NACL) \
412 && !defined (TE_NETWARE) \
29b0f896 413 && !defined (TE_FreeBSD) \
5b806d27 414 && !defined (TE_DragonFly) \
29b0f896 415 && !defined (TE_NetBSD)))
252b5132 416/* This array holds the chars that always start a comment. If the
b3b91714
AM		 417 pre-processor is disabled, these aren't very useful. The option
418 --divide will remove '/' from this list. */
419const char *i386_comment_chars = "#/";
420#define SVR4_COMMENT_CHARS 1
252b5132 421#define PREFIX_SEPARATOR '\\'
252b5132 422
b3b91714
AM		 423#else
424const char *i386_comment_chars = "#";
425#define PREFIX_SEPARATOR '/'
426#endif
427
252b5132
RH		 428/* This array holds the chars that only start a comment at the beginning of
429 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 430 .line and .file directives will appear in the pre-processed output.
431 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 432 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 433 #NO_APP at the beginning of its output.
434 Also note that comments started like this one will always work if
252b5132 435 '/' isn't otherwise defined. */
b3b91714 436const char line_comment_chars[] = "#/";
252b5132 437
63a0b638 438const char line_separator_chars[] = ";";
252b5132 439
ce8a8b2f
AM		 440/* Chars that can be used to separate mant from exp in floating point
441 nums. */
252b5132
RH		 442const char EXP_CHARS[] = "eE";
443
ce8a8b2f
AM		 444/* Chars that mean this number is a floating point constant
445 As in 0f12.456
446 or 0d1.2345e12. */
252b5132
RH		 447const char FLT_CHARS[] = "fFdDxX";
448
ce8a8b2f 449/* Tables for lexical analysis. */
252b5132
RH		 450static char mnemonic_chars[256];
451static char register_chars[256];
452static char operand_chars[256];
453static char identifier_chars[256];
454static char digit_chars[256];
455
ce8a8b2f 456/* Lexical macros. */
252b5132
RH		 457#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
458#define is_operand_char(x) (operand_chars[(unsigned char) x])
459#define is_register_char(x) (register_chars[(unsigned char) x])
460#define is_space_char(x) ((x) == ' ')
461#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
462#define is_digit_char(x) (digit_chars[(unsigned char) x])
463
0234cb7c 464/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 465static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
466
467/* md_assemble() always leaves the strings it's passed unaltered. To
468 effect this we maintain a stack of saved characters that we've smashed
469 with '\0's (indicating end of strings for various sub-fields of the
47926f60 470 assembler instruction). */
252b5132 471static char save_stack[32];
ce8a8b2f 472static char *save_stack_p;
252b5132
RH		 473#define END_STRING_AND_SAVE(s) \
474 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
475#define RESTORE_END_STRING(s) \
476 do { *(s) = *--save_stack_p; } while (0)
477
47926f60 478/* The instruction we're assembling. */
252b5132
RH		 479static i386_insn i;
480
481/* Possible templates for current insn. */
482static const templates *current_templates;
483
31b2323c
L		 484/* Per instruction expressionS buffers: max displacements & immediates. */
485static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
486static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 487
47926f60 488/* Current operand we are working on. */
ee86248c 489static int this_operand = -1;
252b5132 490
3e73aa7c
JH		 491/* We support four different modes. FLAG_CODE variable is used to distinguish
492 these. */
493
494enum flag_code {
495 CODE_32BIT,
496 CODE_16BIT,
497 CODE_64BIT };
498
499static enum flag_code flag_code;
4fa24527 500static unsigned int object_64bit;
862be3fb 501static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 502static int use_rela_relocations = 0;
503
7af8ed2d
NC		 504#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
505 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
506 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
507
351f65ca
L		 508/* The ELF ABI to use. */
509enum x86_elf_abi
510{
511 I386_ABI,
7f56bc95
L		 512 X86_64_ABI,
513 X86_64_X32_ABI
351f65ca
L		 514};
515
516static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 517#endif
351f65ca 518
47926f60
KH		 519/* 1 for intel syntax,
520 0 if att syntax. */
521static int intel_syntax = 0;
252b5132 522
1efbbeb4
L		 523/* 1 for intel mnemonic,
524 0 if att mnemonic. */
525static int intel_mnemonic = !SYSV386_COMPAT;
526
5209009a 527/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 528static int old_gcc = OLDGCC_COMPAT;
529
a60de03c
JB		 530/* 1 if pseudo registers are permitted. */
531static int allow_pseudo_reg = 0;
532
47926f60
KH		 533/* 1 if register prefix % not required. */
534static int allow_naked_reg = 0;
252b5132 535
7e8b059b
L		 536/* 1 if the assembler should add BND prefix for all control-tranferring
537 instructions supporting it, even if this prefix wasn't specified
538 explicitly. */
539static int add_bnd_prefix = 0;
540
ba104c83 541/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 542static int allow_index_reg = 0;
543
7bab8ab5 544static enum check_kind
daf50ae7 545 {
7bab8ab5
JB		 546 check_none = 0,
547 check_warning,
548 check_error
daf50ae7 549 }
7bab8ab5 550sse_check, operand_check = check_warning;
daf50ae7 551
2ca3ace5
L		 552/* Register prefix used for error message. */
553static const char *register_prefix = "%";
554
47926f60
KH		 555/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
556 leave, push, and pop instructions so that gcc has the same stack
557 frame as in 32 bit mode. */
558static char stackop_size = '\0';
eecb386c 559
12b55ccc
L		 560/* Non-zero to optimize code alignment. */
561int optimize_align_code = 1;
562
47926f60
KH		 563/* Non-zero to quieten some warnings. */
564static int quiet_warnings = 0;
a38cf1db 565
47926f60
KH		 566/* CPU name. */
567static const char *cpu_arch_name = NULL;
6305a203 568static char *cpu_sub_arch_name = NULL;
a38cf1db 569
47926f60 570/* CPU feature flags. */
40fb9820
L		 571static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
572
ccc9c027
L		 573/* If we have selected a cpu we are generating instructions for. */
574static int cpu_arch_tune_set = 0;
575
9103f4f4 576/* Cpu we are generating instructions for. */
fbf3f584 577enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 578
579/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 580static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 581
ccc9c027 582/* CPU instruction set architecture used. */
fbf3f584 583enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 584
9103f4f4 585/* CPU feature flags of instruction set architecture used. */
fbf3f584 586i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 587
fddf5b5b
AM		 588/* If set, conditional jumps are not automatically promoted to handle
589 larger than a byte offset. */
590static unsigned int no_cond_jump_promotion = 0;
591
c0f3af97
L		 592/* Encode SSE instructions with VEX prefix. */
593static unsigned int sse2avx;
594
539f890d
L		 595/* Encode scalar AVX instructions with specific vector length. */
596static enum
597 {
598 vex128 = 0,
599 vex256
600 } avxscalar;
601
43234a1e
L		 602/* Encode scalar EVEX LIG instructions with specific vector length. */
603static enum
604 {
605 evexl128 = 0,
606 evexl256,
607 evexl512
608 } evexlig;
609
610/* Encode EVEX WIG instructions with specific evex.w. */
611static enum
612 {
613 evexw0 = 0,
614 evexw1
615 } evexwig;
616
29b0f896 617/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 618static symbolS *GOT_symbol;
29b0f896 619
a4447b93
RH		 620/* The dwarf2 return column, adjusted for 32 or 64 bit. */
621unsigned int x86_dwarf2_return_column;
622
623/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
624int x86_cie_data_alignment;
625
252b5132 626/* Interface to relax_segment.
fddf5b5b
AM		 627 There are 3 major relax states for 386 jump insns because the
628 different types of jumps add different sizes to frags when we're
629 figuring out what sort of jump to choose to reach a given label. */
252b5132 630
47926f60 631/* Types. */
93c2a809
AM		 632#define UNCOND_JUMP 0
633#define COND_JUMP 1
634#define COND_JUMP86 2
fddf5b5b 635
47926f60 636/* Sizes. */
252b5132
RH		 637#define CODE16 1
638#define SMALL 0
29b0f896 639#define SMALL16 (SMALL | CODE16)
252b5132 640#define BIG 2
29b0f896 641#define BIG16 (BIG | CODE16)
252b5132
RH		 642
643#ifndef INLINE
644#ifdef __GNUC__
645#define INLINE __inline__
646#else
647#define INLINE
648#endif
649#endif
650
fddf5b5b
AM		 651#define ENCODE_RELAX_STATE(type, size) \
652 ((relax_substateT) (((type) << 2) | (size)))
653#define TYPE_FROM_RELAX_STATE(s) \
654 ((s) >> 2)
655#define DISP_SIZE_FROM_RELAX_STATE(s) \
656 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 657
658/* This table is used by relax_frag to promote short jumps to long
659 ones where necessary. SMALL (short) jumps may be promoted to BIG
660 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
661 don't allow a short jump in a 32 bit code segment to be promoted to
662 a 16 bit offset jump because it's slower (requires data size
663 prefix), and doesn't work, unless the destination is in the bottom
664 64k of the code segment (The top 16 bits of eip are zeroed). */
665
666const relax_typeS md_relax_table[] =
667{
24eab124
AM		 668 /* The fields are:
669 1) most positive reach of this state,
670 2) most negative reach of this state,
93c2a809 671 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 672 4) which index into the table to try if we can't fit into this one. */
252b5132 673
fddf5b5b 674 /* UNCOND_JUMP states. */
93c2a809
AM		 675 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
676 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
677 /* dword jmp adds 4 bytes to frag:
678 0 extra opcode bytes, 4 displacement bytes. */
252b5132 679 {0, 0, 4, 0},
93c2a809
AM		 680 /* word jmp adds 2 byte2 to frag:
681 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 682 {0, 0, 2, 0},
683
93c2a809
AM		 684 /* COND_JUMP states. */
685 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
686 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
687 /* dword conditionals adds 5 bytes to frag:
688 1 extra opcode byte, 4 displacement bytes. */
689 {0, 0, 5, 0},
fddf5b5b 690 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 691 1 extra opcode byte, 2 displacement bytes. */
692 {0, 0, 3, 0},
693
694 /* COND_JUMP86 states. */
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
696 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
697 /* dword conditionals adds 5 bytes to frag:
698 1 extra opcode byte, 4 displacement bytes. */
699 {0, 0, 5, 0},
700 /* word conditionals add 4 bytes to frag:
701 1 displacement byte and a 3 byte long branch insn. */
702 {0, 0, 4, 0}
252b5132
RH		 703};
704
9103f4f4
L		 705static const arch_entry cpu_arch[] =
706{
89507696
JB		 707 /* Do not replace the first two entries - i386_target_format()
708 relies on them being there in this order. */
8a2c8fef 709 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 710 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 711 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 712 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 713 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 714 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 715 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 716 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 717 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 718 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 719 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 720 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 721 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 722 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 723 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 724 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 725 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 726 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 727 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 728 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 729 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 730 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 731 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 732 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 733 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 734 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 735 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 736 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 737 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 738 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 739 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 740 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 741 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 742 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 743 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 744 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 745 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 746 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 747 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 748 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 749 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 750 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 751 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 752 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 753 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
754 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 755 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 756 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 757 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 758 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 759 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 760 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 761 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 762 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 764 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 766 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 767 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 768 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 769 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 770 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 771 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 772 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 773 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
774 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 775 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
776 CPU_BDVER4_FLAGS, 0, 0 },
7b458c12
L		 777 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
778 CPU_BTVER1_FLAGS, 0, 0 },
779 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
780 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 781 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 782 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 783 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 784 CPU_287_FLAGS, 0, 0 },
8a2c8fef 785 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 786 CPU_387_FLAGS, 0, 0 },
8a2c8fef 787 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 788 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 789 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 790 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 791 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 792 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 793 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 794 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 795 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 796 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 797 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 798 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 799 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 800 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 801 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 802 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 803 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 804 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 805 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 806 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 807 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 808 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 809 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 810 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 811 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
812 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 813 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
814 CPU_AVX512F_FLAGS, 0, 0 },
815 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
816 CPU_AVX512CD_FLAGS, 0, 0 },
817 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
818 CPU_AVX512ER_FLAGS, 0, 0 },
819 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
820 CPU_AVX512PF_FLAGS, 0, 0 },
8a2c8fef 821 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 822 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 823 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 824 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 825 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
826 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 827 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 828 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 829 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 830 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 831 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 832 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 833 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 834 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 835 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 836 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 837 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 838 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 839 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 840 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 841 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 842 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 843 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 844 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 845 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
846 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 847 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 848 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 849 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 850 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 852 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 853 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 854 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 855 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 856 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 857 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
858 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 859 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 860 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 861 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
862 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 863 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
864 CPU_HLE_FLAGS, 0, 0 },
865 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
866 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 867 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
868 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 869 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 870 CPU_CLFLUSH_FLAGS, 0, 0 },
871 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
872 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 873 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 874 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 875 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 876 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 877 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 878 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 880 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 881 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 882 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 884 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 885 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 886 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 887 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 888 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 889 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 890 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 891 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
892 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 893 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
894 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 895 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
896 CPU_ADX_FLAGS, 0, 0 },
897 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
898 CPU_RDSEED_FLAGS, 0, 0 },
899 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
900 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 901 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
902 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 903 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
904 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 905 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
906 CPU_SHA_FLAGS, 0, 0 },
e413e4e9
AM		 907};
908
704209c0 909#ifdef I386COFF
a6c24e68
NC		 910/* Like s_lcomm_internal in gas/read.c but the alignment string
911 is allowed to be optional. */
912
913static symbolS *
914pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
915{
916 addressT align = 0;
917
918 SKIP_WHITESPACE ();
919
7ab9ffdd 920 if (needs_align
a6c24e68
NC		 921 && *input_line_pointer == ',')
922 {
923 align = parse_align (needs_align - 1);
7ab9ffdd 924
a6c24e68
NC		 925 if (align == (addressT) -1)
926 return NULL;
927 }
928 else
929 {
930 if (size >= 8)
931 align = 3;
932 else if (size >= 4)
933 align = 2;
934 else if (size >= 2)
935 align = 1;
936 else
937 align = 0;
938 }
939
940 bss_alloc (symbolP, size, align);
941 return symbolP;
942}
943
704209c0 944static void
a6c24e68
NC		 945pe_lcomm (int needs_align)
946{
947 s_comm_internal (needs_align * 2, pe_lcomm_internal);
948}
704209c0 949#endif
a6c24e68 950
29b0f896
AM		 951const pseudo_typeS md_pseudo_table[] =
952{
953#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
954 {"align", s_align_bytes, 0},
955#else
956 {"align", s_align_ptwo, 0},
957#endif
958 {"arch", set_cpu_arch, 0},
959#ifndef I386COFF
960 {"bss", s_bss, 0},
a6c24e68
NC		 961#else
962 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 963#endif
964 {"ffloat", float_cons, 'f'},
965 {"dfloat", float_cons, 'd'},
966 {"tfloat", float_cons, 'x'},
967 {"value", cons, 2},
d182319b 968 {"slong", signed_cons, 4},
29b0f896
AM		 969 {"noopt", s_ignore, 0},
970 {"optim", s_ignore, 0},
971 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
972 {"code16", set_code_flag, CODE_16BIT},
973 {"code32", set_code_flag, CODE_32BIT},
974 {"code64", set_code_flag, CODE_64BIT},
975 {"intel_syntax", set_intel_syntax, 1},
976 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 977 {"intel_mnemonic", set_intel_mnemonic, 1},
978 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 979 {"allow_index_reg", set_allow_index_reg, 1},
980 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 981 {"sse_check", set_check, 0},
982 {"operand_check", set_check, 1},
3b22753a
L		 983#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
984 {"largecomm", handle_large_common, 0},
07a53e5c 985#else
e3bb37b5 986 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 987 {"loc", dwarf2_directive_loc, 0},
988 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 989#endif
6482c264
NC		 990#ifdef TE_PE
991 {"secrel32", pe_directive_secrel, 0},
992#endif
29b0f896
AM		 993 {0, 0, 0}
994};
995
996/* For interface with expression (). */
997extern char *input_line_pointer;
998
999/* Hash table for instruction mnemonic lookup. */
1000static struct hash_control *op_hash;
1001
1002/* Hash table for register lookup. */
1003static struct hash_control *reg_hash;
1004\f
252b5132 1005void
e3bb37b5 1006i386_align_code (fragS *fragP, int count)
252b5132 1007{
ce8a8b2f
AM		 1008 /* Various efficient no-op patterns for aligning code labels.
1009 Note: Don't try to assemble the instructions in the comments.
1010 0L and 0w are not legal. */
252b5132
RH		 1011 static const char f32_1[] =
1012 {0x90}; /* nop */
1013 static const char f32_2[] =
ccc9c027 1014 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1015 static const char f32_3[] =
1016 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1017 static const char f32_4[] =
1018 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1019 static const char f32_5[] =
1020 {0x90, /* nop */
1021 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1022 static const char f32_6[] =
1023 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1024 static const char f32_7[] =
1025 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1026 static const char f32_8[] =
1027 {0x90, /* nop */
1028 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1029 static const char f32_9[] =
1030 {0x89,0xf6, /* movl %esi,%esi */
1031 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1032 static const char f32_10[] =
1033 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1034 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1035 static const char f32_11[] =
1036 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1037 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1038 static const char f32_12[] =
1039 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1040 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1041 static const char f32_13[] =
1042 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1043 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1044 static const char f32_14[] =
1045 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1046 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1047 static const char f16_3[] =
1048 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1049 static const char f16_4[] =
1050 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1051 static const char f16_5[] =
1052 {0x90, /* nop */
1053 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1054 static const char f16_6[] =
1055 {0x89,0xf6, /* mov %si,%si */
1056 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1057 static const char f16_7[] =
1058 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1059 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1060 static const char f16_8[] =
1061 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1062 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1063 static const char jump_31[] =
1064 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1065 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1066 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1067 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1068 static const char *const f32_patt[] = {
1069 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1070 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1071 };
1072 static const char *const f16_patt[] = {
76bc74dc 1073 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1074 };
ccc9c027
L		 1075 /* nopl (%[re]ax) */
1076 static const char alt_3[] =
1077 {0x0f,0x1f,0x00};
1078 /* nopl 0(%[re]ax) */
1079 static const char alt_4[] =
1080 {0x0f,0x1f,0x40,0x00};
1081 /* nopl 0(%[re]ax,%[re]ax,1) */
1082 static const char alt_5[] =
1083 {0x0f,0x1f,0x44,0x00,0x00};
1084 /* nopw 0(%[re]ax,%[re]ax,1) */
1085 static const char alt_6[] =
1086 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1087 /* nopl 0L(%[re]ax) */
1088 static const char alt_7[] =
1089 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1090 /* nopl 0L(%[re]ax,%[re]ax,1) */
1091 static const char alt_8[] =
1092 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1093 /* nopw 0L(%[re]ax,%[re]ax,1) */
1094 static const char alt_9[] =
1095 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1096 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1097 static const char alt_10[] =
1098 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1099 /* data16
1100 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1101 static const char alt_long_11[] =
1102 {0x66,
1103 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1104 /* data16
1105 data16
1106 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1107 static const char alt_long_12[] =
1108 {0x66,
1109 0x66,
1110 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1111 /* data16
1112 data16
1113 data16
1114 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1115 static const char alt_long_13[] =
1116 {0x66,
1117 0x66,
1118 0x66,
1119 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1120 /* data16
1121 data16
1122 data16
1123 data16
1124 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1125 static const char alt_long_14[] =
1126 {0x66,
1127 0x66,
1128 0x66,
1129 0x66,
1130 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1131 /* data16
1132 data16
1133 data16
1134 data16
1135 data16
1136 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1137 static const char alt_long_15[] =
1138 {0x66,
1139 0x66,
1140 0x66,
1141 0x66,
1142 0x66,
1143 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1144 /* nopl 0(%[re]ax,%[re]ax,1)
1145 nopw 0(%[re]ax,%[re]ax,1) */
1146 static const char alt_short_11[] =
1147 {0x0f,0x1f,0x44,0x00,0x00,
1148 0x66,0x0f,0x1f,0x44,0x00,0x00};
1149 /* nopw 0(%[re]ax,%[re]ax,1)
1150 nopw 0(%[re]ax,%[re]ax,1) */
1151 static const char alt_short_12[] =
1152 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1153 0x66,0x0f,0x1f,0x44,0x00,0x00};
1154 /* nopw 0(%[re]ax,%[re]ax,1)
1155 nopl 0L(%[re]ax) */
1156 static const char alt_short_13[] =
1157 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1158 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1159 /* nopl 0L(%[re]ax)
1160 nopl 0L(%[re]ax) */
1161 static const char alt_short_14[] =
1162 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1163 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1164 /* nopl 0L(%[re]ax)
1165 nopl 0L(%[re]ax,%[re]ax,1) */
1166 static const char alt_short_15[] =
1167 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1168 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1169 static const char *const alt_short_patt[] = {
1170 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1171 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1172 alt_short_14, alt_short_15
1173 };
1174 static const char *const alt_long_patt[] = {
1175 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1176 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1177 alt_long_14, alt_long_15
1178 };
252b5132 1179
76bc74dc
L		 1180 /* Only align for at least a positive non-zero boundary. */
1181 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1182 return;
3e73aa7c 1183
ccc9c027
L		 1184 /* We need to decide which NOP sequence to use for 32bit and
1185 64bit. When -mtune= is used:
4eed87de 1186
76bc74dc
L		 1187 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1188 PROCESSOR_GENERIC32, f32_patt will be used.
1189 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1190 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1191 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1192 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
7b458c12 1193 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
69dd9865 1194 will be used.
ccc9c027 1195
76bc74dc 1196 When -mtune= isn't used, alt_long_patt will be used if
22109423 1197 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1198 be used.
ccc9c027
L		 1199
1200 When -march= or .arch is used, we can't use anything beyond
1201 cpu_arch_isa_flags. */
1202
1203 if (flag_code == CODE_16BIT)
1204 {
ccc9c027 1205 if (count > 8)
33fef721 1206 {
76bc74dc
L		 1207 memcpy (fragP->fr_literal + fragP->fr_fix,
1208 jump_31, count);
1209 /* Adjust jump offset. */
1210 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1211 }
76bc74dc
L		 1212 else
1213 memcpy (fragP->fr_literal + fragP->fr_fix,
1214 f16_patt[count - 1], count);
252b5132 1215 }
33fef721 1216 else
ccc9c027
L		 1217 {
1218 const char *const *patt = NULL;
1219
fbf3f584 1220 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1221 {
1222 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1223 switch (cpu_arch_tune)
1224 {
1225 case PROCESSOR_UNKNOWN:
1226 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1227 optimize with nops. */
1228 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1229 patt = alt_long_patt;
ccc9c027
L		 1230 else
1231 patt = f32_patt;
1232 break;
ccc9c027
L		 1233 case PROCESSOR_PENTIUM4:
1234 case PROCESSOR_NOCONA:
ef05d495 1235 case PROCESSOR_CORE:
76bc74dc 1236 case PROCESSOR_CORE2:
bd5295b2 1237 case PROCESSOR_COREI7:
3632d14b 1238 case PROCESSOR_L1OM:
7a9068fe 1239 case PROCESSOR_K1OM:
76bc74dc
L		 1240 case PROCESSOR_GENERIC64:
1241 patt = alt_long_patt;
1242 break;
ccc9c027
L		 1243 case PROCESSOR_K6:
1244 case PROCESSOR_ATHLON:
1245 case PROCESSOR_K8:
4eed87de 1246 case PROCESSOR_AMDFAM10:
8aedb9fe 1247 case PROCESSOR_BD:
7b458c12 1248 case PROCESSOR_BT:
ccc9c027
L		 1249 patt = alt_short_patt;
1250 break;
76bc74dc 1251 case PROCESSOR_I386:
ccc9c027
L		 1252 case PROCESSOR_I486:
1253 case PROCESSOR_PENTIUM:
2dde1948 1254 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1255 case PROCESSOR_GENERIC32:
1256 patt = f32_patt;
1257 break;
4eed87de 1258 }
ccc9c027
L		 1259 }
1260 else
1261 {
fbf3f584 1262 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1263 {
1264 case PROCESSOR_UNKNOWN:
e6a14101 1265 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1266 PROCESSOR_UNKNOWN. */
1267 abort ();
1268 break;
1269
76bc74dc 1270 case PROCESSOR_I386:
ccc9c027
L		 1271 case PROCESSOR_I486:
1272 case PROCESSOR_PENTIUM:
ccc9c027
L		 1273 case PROCESSOR_K6:
1274 case PROCESSOR_ATHLON:
1275 case PROCESSOR_K8:
4eed87de 1276 case PROCESSOR_AMDFAM10:
8aedb9fe 1277 case PROCESSOR_BD:
7b458c12 1278 case PROCESSOR_BT:
ccc9c027
L		 1279 case PROCESSOR_GENERIC32:
1280 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1281 with nops. */
1282 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1283 patt = alt_short_patt;
1284 else
1285 patt = f32_patt;
1286 break;
76bc74dc
L		 1287 case PROCESSOR_PENTIUMPRO:
1288 case PROCESSOR_PENTIUM4:
1289 case PROCESSOR_NOCONA:
1290 case PROCESSOR_CORE:
ef05d495 1291 case PROCESSOR_CORE2:
bd5295b2 1292 case PROCESSOR_COREI7:
3632d14b 1293 case PROCESSOR_L1OM:
7a9068fe 1294 case PROCESSOR_K1OM:
22109423 1295 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1296 patt = alt_long_patt;
1297 else
1298 patt = f32_patt;
1299 break;
1300 case PROCESSOR_GENERIC64:
76bc74dc 1301 patt = alt_long_patt;
ccc9c027 1302 break;
4eed87de 1303 }
ccc9c027
L		 1304 }
1305
76bc74dc
L		 1306 if (patt == f32_patt)
1307 {
1308 /* If the padding is less than 15 bytes, we use the normal
1309 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1310 its offset. */
1311 int limit;
76ba9986 1312
711eedef
L		 1313 /* For 64bit, the limit is 3 bytes. */
1314 if (flag_code == CODE_64BIT
1315 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1316 limit = 3;
1317 else
1318 limit = 15;
1319 if (count < limit)
76bc74dc
L		 1320 memcpy (fragP->fr_literal + fragP->fr_fix,
1321 patt[count - 1], count);
1322 else
1323 {
1324 memcpy (fragP->fr_literal + fragP->fr_fix,
1325 jump_31, count);
1326 /* Adjust jump offset. */
1327 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1328 }
1329 }
1330 else
1331 {
1332 /* Maximum length of an instruction is 15 byte. If the
1333 padding is greater than 15 bytes and we don't use jump,
1334 we have to break it into smaller pieces. */
1335 int padding = count;
1336 while (padding > 15)
1337 {
1338 padding -= 15;
1339 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1340 patt [14], 15);
1341 }
1342
1343 if (padding)
1344 memcpy (fragP->fr_literal + fragP->fr_fix,
1345 patt [padding - 1], padding);
1346 }
ccc9c027 1347 }
33fef721 1348 fragP->fr_var = count;
252b5132
RH		 1349}
1350
c6fb90c8 1351static INLINE int
0dfbf9d7 1352operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1353{
0dfbf9d7 1354 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1355 {
1356 case 3:
0dfbf9d7 1357 if (x->array[2])
c6fb90c8
L		 1358 return 0;
1359 case 2:
0dfbf9d7 1360 if (x->array[1])
c6fb90c8
L		 1361 return 0;
1362 case 1:
0dfbf9d7 1363 return !x->array[0];
c6fb90c8
L		 1364 default:
1365 abort ();
1366 }
40fb9820
L		 1367}
1368
c6fb90c8 1369static INLINE void
0dfbf9d7 1370operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1371{
0dfbf9d7 1372 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1373 {
1374 case 3:
0dfbf9d7 1375 x->array[2] = v;
c6fb90c8 1376 case 2:
0dfbf9d7 1377 x->array[1] = v;
c6fb90c8 1378 case 1:
0dfbf9d7 1379 x->array[0] = v;
c6fb90c8
L		 1380 break;
1381 default:
1382 abort ();
1383 }
1384}
40fb9820 1385
c6fb90c8 1386static INLINE int
0dfbf9d7
L		 1387operand_type_equal (const union i386_operand_type *x,
1388 const union i386_operand_type *y)
c6fb90c8 1389{
0dfbf9d7 1390 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1391 {
1392 case 3:
0dfbf9d7 1393 if (x->array[2] != y->array[2])
c6fb90c8
L		 1394 return 0;
1395 case 2:
0dfbf9d7 1396 if (x->array[1] != y->array[1])
c6fb90c8
L		 1397 return 0;
1398 case 1:
0dfbf9d7 1399 return x->array[0] == y->array[0];
c6fb90c8
L		 1400 break;
1401 default:
1402 abort ();
1403 }
1404}
40fb9820 1405
0dfbf9d7
L		 1406static INLINE int
1407cpu_flags_all_zero (const union i386_cpu_flags *x)
1408{
1409 switch (ARRAY_SIZE(x->array))
1410 {
1411 case 3:
1412 if (x->array[2])
1413 return 0;
1414 case 2:
1415 if (x->array[1])
1416 return 0;
1417 case 1:
1418 return !x->array[0];
1419 default:
1420 abort ();
1421 }
1422}
1423
1424static INLINE void
1425cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1426{
1427 switch (ARRAY_SIZE(x->array))
1428 {
1429 case 3:
1430 x->array[2] = v;
1431 case 2:
1432 x->array[1] = v;
1433 case 1:
1434 x->array[0] = v;
1435 break;
1436 default:
1437 abort ();
1438 }
1439}
1440
1441static INLINE int
1442cpu_flags_equal (const union i386_cpu_flags *x,
1443 const union i386_cpu_flags *y)
1444{
1445 switch (ARRAY_SIZE(x->array))
1446 {
1447 case 3:
1448 if (x->array[2] != y->array[2])
1449 return 0;
1450 case 2:
1451 if (x->array[1] != y->array[1])
1452 return 0;
1453 case 1:
1454 return x->array[0] == y->array[0];
1455 break;
1456 default:
1457 abort ();
1458 }
1459}
c6fb90c8
L		 1460
1461static INLINE int
1462cpu_flags_check_cpu64 (i386_cpu_flags f)
1463{
1464 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1465 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1466}
1467
c6fb90c8
L		 1468static INLINE i386_cpu_flags
1469cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1470{
c6fb90c8
L		 1471 switch (ARRAY_SIZE (x.array))
1472 {
1473 case 3:
1474 x.array [2] &= y.array [2];
1475 case 2:
1476 x.array [1] &= y.array [1];
1477 case 1:
1478 x.array [0] &= y.array [0];
1479 break;
1480 default:
1481 abort ();
1482 }
1483 return x;
1484}
40fb9820 1485
c6fb90c8
L		 1486static INLINE i386_cpu_flags
1487cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1488{
c6fb90c8 1489 switch (ARRAY_SIZE (x.array))
40fb9820 1490 {
c6fb90c8
L		 1491 case 3:
1492 x.array [2] |= y.array [2];
1493 case 2:
1494 x.array [1] |= y.array [1];
1495 case 1:
1496 x.array [0] |= y.array [0];
40fb9820
L		 1497 break;
1498 default:
1499 abort ();
1500 }
40fb9820
L		 1501 return x;
1502}
1503
309d3373
JB		 1504static INLINE i386_cpu_flags
1505cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1506{
1507 switch (ARRAY_SIZE (x.array))
1508 {
1509 case 3:
1510 x.array [2] &= ~y.array [2];
1511 case 2:
1512 x.array [1] &= ~y.array [1];
1513 case 1:
1514 x.array [0] &= ~y.array [0];
1515 break;
1516 default:
1517 abort ();
1518 }
1519 return x;
1520}
1521
c0f3af97
L		 1522#define CPU_FLAGS_ARCH_MATCH 0x1
1523#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1524#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1525#define CPU_FLAGS_PCLMUL_MATCH 0x8
1526#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1527
a5ff0eb2 1528#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1529 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1530 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1531#define CPU_FLAGS_PERFECT_MATCH \
1532 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1533
1534/* Return CPU flags match bits. */
3629bb00 1535
40fb9820 1536static int
d3ce72d0 1537cpu_flags_match (const insn_template *t)
40fb9820 1538{
c0f3af97
L		 1539 i386_cpu_flags x = t->cpu_flags;
1540 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1541
1542 x.bitfield.cpu64 = 0;
1543 x.bitfield.cpuno64 = 0;
1544
0dfbf9d7 1545 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1546 {
1547 /* This instruction is available on all archs. */
1548 match |= CPU_FLAGS_32BIT_MATCH;
1549 }
3629bb00
L		 1550 else
1551 {
c0f3af97 1552 /* This instruction is available only on some archs. */
3629bb00
L		 1553 i386_cpu_flags cpu = cpu_arch_flags;
1554
1555 cpu.bitfield.cpu64 = 0;
1556 cpu.bitfield.cpuno64 = 0;
1557 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1558 if (!cpu_flags_all_zero (&cpu))
1559 {
a5ff0eb2
L		 1560 if (x.bitfield.cpuavx)
1561 {
ce2f5b3c 1562 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1563 if (cpu.bitfield.cpuavx)
1564 {
1565 /* Check SSE2AVX. */
1566 if (!t->opcode_modifier.sse2avx|| sse2avx)
1567 {
1568 match |= (CPU_FLAGS_ARCH_MATCH
1569 | CPU_FLAGS_AVX_MATCH);
1570 /* Check AES. */
1571 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1572 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1573 /* Check PCLMUL. */
1574 if (!x.bitfield.cpupclmul
1575 || cpu.bitfield.cpupclmul)
1576 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1577 }
1578 }
1579 else
1580 match |= CPU_FLAGS_ARCH_MATCH;
1581 }
1582 else
c0f3af97
L		 1583 match |= CPU_FLAGS_32BIT_MATCH;
1584 }
3629bb00 1585 }
c0f3af97 1586 return match;
40fb9820
L		 1587}
1588
c6fb90c8
L		 1589static INLINE i386_operand_type
1590operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1591{
c6fb90c8
L		 1592 switch (ARRAY_SIZE (x.array))
1593 {
1594 case 3:
1595 x.array [2] &= y.array [2];
1596 case 2:
1597 x.array [1] &= y.array [1];
1598 case 1:
1599 x.array [0] &= y.array [0];
1600 break;
1601 default:
1602 abort ();
1603 }
1604 return x;
40fb9820
L		 1605}
1606
c6fb90c8
L		 1607static INLINE i386_operand_type
1608operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1609{
c6fb90c8 1610 switch (ARRAY_SIZE (x.array))
40fb9820 1611 {
c6fb90c8
L		 1612 case 3:
1613 x.array [2] |= y.array [2];
1614 case 2:
1615 x.array [1] |= y.array [1];
1616 case 1:
1617 x.array [0] |= y.array [0];
40fb9820
L		 1618 break;
1619 default:
1620 abort ();
1621 }
c6fb90c8
L		 1622 return x;
1623}
40fb9820 1624
c6fb90c8
L		 1625static INLINE i386_operand_type
1626operand_type_xor (i386_operand_type x, i386_operand_type y)
1627{
1628 switch (ARRAY_SIZE (x.array))
1629 {
1630 case 3:
1631 x.array [2] ^= y.array [2];
1632 case 2:
1633 x.array [1] ^= y.array [1];
1634 case 1:
1635 x.array [0] ^= y.array [0];
1636 break;
1637 default:
1638 abort ();
1639 }
40fb9820
L		 1640 return x;
1641}
1642
1643static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1644static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1645static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1646static const i386_operand_type inoutportreg
1647 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1648static const i386_operand_type reg16_inoutportreg
1649 = OPERAND_TYPE_REG16_INOUTPORTREG;
1650static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1651static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1652static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1653static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1654static const i386_operand_type anydisp
1655 = OPERAND_TYPE_ANYDISP;
40fb9820 1656static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1657static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1658static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1659static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1660static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1661static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1662static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1663static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1664static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1665static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1666static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1667static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1668static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1669static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
7e8b059b 1670static const i386_operand_type regbnd = OPERAND_TYPE_REGBND;
43234a1e 1671static const i386_operand_type vec_disp8 = OPERAND_TYPE_VEC_DISP8;
40fb9820
L		 1672
1673enum operand_type
1674{
1675 reg,
40fb9820
L		 1676 imm,
1677 disp,
1678 anymem
1679};
1680
c6fb90c8 1681static INLINE int
40fb9820
L		 1682operand_type_check (i386_operand_type t, enum operand_type c)
1683{
1684 switch (c)
1685 {
1686 case reg:
1687 return (t.bitfield.reg8
1688 || t.bitfield.reg16
1689 || t.bitfield.reg32
1690 || t.bitfield.reg64);
1691
40fb9820
L		 1692 case imm:
1693 return (t.bitfield.imm8
1694 || t.bitfield.imm8s
1695 || t.bitfield.imm16
1696 || t.bitfield.imm32
1697 || t.bitfield.imm32s
1698 || t.bitfield.imm64);
1699
1700 case disp:
1701 return (t.bitfield.disp8
1702 || t.bitfield.disp16
1703 || t.bitfield.disp32
1704 || t.bitfield.disp32s
1705 || t.bitfield.disp64);
1706
1707 case anymem:
1708 return (t.bitfield.disp8
1709 || t.bitfield.disp16
1710 || t.bitfield.disp32
1711 || t.bitfield.disp32s
1712 || t.bitfield.disp64
1713 || t.bitfield.baseindex);
1714
1715 default:
1716 abort ();
1717 }
2cfe26b6
AM		 1718
1719 return 0;
40fb9820
L		 1720}
1721
5c07affc
L		 1722/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1723 operand J for instruction template T. */
1724
1725static INLINE int
d3ce72d0 1726match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1727{
1728 return !((i.types[j].bitfield.byte
1729 && !t->operand_types[j].bitfield.byte)
1730 || (i.types[j].bitfield.word
1731 && !t->operand_types[j].bitfield.word)
1732 || (i.types[j].bitfield.dword
1733 && !t->operand_types[j].bitfield.dword)
1734 || (i.types[j].bitfield.qword
1735 && !t->operand_types[j].bitfield.qword));
1736}
1737
1738/* Return 1 if there is no conflict in any size on operand J for
1739 instruction template T. */
1740
1741static INLINE int
d3ce72d0 1742match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1743{
1744 return (match_reg_size (t, j)
1745 && !((i.types[j].bitfield.unspecified
1746 && !t->operand_types[j].bitfield.unspecified)
1747 || (i.types[j].bitfield.fword
1748 && !t->operand_types[j].bitfield.fword)
1749 || (i.types[j].bitfield.tbyte
1750 && !t->operand_types[j].bitfield.tbyte)
1751 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1752 && !t->operand_types[j].bitfield.xmmword)
1753 || (i.types[j].bitfield.ymmword
43234a1e
L		 1754 && !t->operand_types[j].bitfield.ymmword)
1755 || (i.types[j].bitfield.zmmword
1756 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1757}
1758
1759/* Return 1 if there is no size conflict on any operands for
1760 instruction template T. */
1761
1762static INLINE int
d3ce72d0 1763operand_size_match (const insn_template *t)
5c07affc
L		 1764{
1765 unsigned int j;
1766 int match = 1;
1767
1768 /* Don't check jump instructions. */
1769 if (t->opcode_modifier.jump
1770 || t->opcode_modifier.jumpbyte
1771 || t->opcode_modifier.jumpdword
1772 || t->opcode_modifier.jumpintersegment)
1773 return match;
1774
1775 /* Check memory and accumulator operand size. */
1776 for (j = 0; j < i.operands; j++)
1777 {
1778 if (t->operand_types[j].bitfield.anysize)
1779 continue;
1780
1781 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1782 {
1783 match = 0;
1784 break;
1785 }
1786
1787 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1788 {
1789 match = 0;
1790 break;
1791 }
1792 }
1793
891edac4 1794 if (match)
5c07affc 1795 return match;
891edac4
L		 1796 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1797 {
1798mismatch:
86e026a4 1799 i.error = operand_size_mismatch;
891edac4
L		 1800 return 0;
1801 }
5c07affc
L		 1802
1803 /* Check reverse. */
9c2799c2 1804 gas_assert (i.operands == 2);
5c07affc
L		 1805
1806 match = 1;
1807 for (j = 0; j < 2; j++)
1808 {
1809 if (t->operand_types[j].bitfield.acc
1810 && !match_reg_size (t, j ? 0 : 1))
891edac4 1811 goto mismatch;
5c07affc
L		 1812
1813 if (i.types[j].bitfield.mem
1814 && !match_mem_size (t, j ? 0 : 1))
891edac4 1815 goto mismatch;
5c07affc
L		 1816 }
1817
1818 return match;
1819}
1820
c6fb90c8 1821static INLINE int
40fb9820
L		 1822operand_type_match (i386_operand_type overlap,
1823 i386_operand_type given)
1824{
1825 i386_operand_type temp = overlap;
1826
1827 temp.bitfield.jumpabsolute = 0;
7d5e4556 1828 temp.bitfield.unspecified = 0;
5c07affc
L		 1829 temp.bitfield.byte = 0;
1830 temp.bitfield.word = 0;
1831 temp.bitfield.dword = 0;
1832 temp.bitfield.fword = 0;
1833 temp.bitfield.qword = 0;
1834 temp.bitfield.tbyte = 0;
1835 temp.bitfield.xmmword = 0;
c0f3af97 1836 temp.bitfield.ymmword = 0;
43234a1e 1837 temp.bitfield.zmmword = 0;
0dfbf9d7 1838 if (operand_type_all_zero (&temp))
891edac4 1839 goto mismatch;
40fb9820 1840
891edac4
L		 1841 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1842 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1843 return 1;
1844
1845mismatch:
a65babc9 1846 i.error = operand_type_mismatch;
891edac4 1847 return 0;
40fb9820
L		 1848}
1849
7d5e4556 1850/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1851 unless the expected operand type register overlap is null.
1852 Note that Acc in a template matches every size of reg. */
1853
c6fb90c8 1854static INLINE int
40fb9820
L		 1855operand_type_register_match (i386_operand_type m0,
1856 i386_operand_type g0,
1857 i386_operand_type t0,
1858 i386_operand_type m1,
1859 i386_operand_type g1,
1860 i386_operand_type t1)
1861{
1862 if (!operand_type_check (g0, reg))
1863 return 1;
1864
1865 if (!operand_type_check (g1, reg))
1866 return 1;
1867
1868 if (g0.bitfield.reg8 == g1.bitfield.reg8
1869 && g0.bitfield.reg16 == g1.bitfield.reg16
1870 && g0.bitfield.reg32 == g1.bitfield.reg32
1871 && g0.bitfield.reg64 == g1.bitfield.reg64)
1872 return 1;
1873
1874 if (m0.bitfield.acc)
1875 {
1876 t0.bitfield.reg8 = 1;
1877 t0.bitfield.reg16 = 1;
1878 t0.bitfield.reg32 = 1;
1879 t0.bitfield.reg64 = 1;
1880 }
1881
1882 if (m1.bitfield.acc)
1883 {
1884 t1.bitfield.reg8 = 1;
1885 t1.bitfield.reg16 = 1;
1886 t1.bitfield.reg32 = 1;
1887 t1.bitfield.reg64 = 1;
1888 }
1889
891edac4
L		 1890 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1891 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1892 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1893 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1894 return 1;
1895
a65babc9 1896 i.error = register_type_mismatch;
891edac4
L		 1897
1898 return 0;
40fb9820
L		 1899}
1900
4c692bc7
JB		 1901static INLINE unsigned int
1902register_number (const reg_entry *r)
1903{
1904 unsigned int nr = r->reg_num;
1905
1906 if (r->reg_flags & RegRex)
1907 nr += 8;
1908
1909 return nr;
1910}
1911
252b5132 1912static INLINE unsigned int
40fb9820 1913mode_from_disp_size (i386_operand_type t)
252b5132 1914{
43234a1e 1915 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1916 return 1;
1917 else if (t.bitfield.disp16
1918 || t.bitfield.disp32
1919 || t.bitfield.disp32s)
1920 return 2;
1921 else
1922 return 0;
252b5132
RH		 1923}
1924
1925static INLINE int
e3bb37b5 1926fits_in_signed_byte (offsetT num)
252b5132
RH		 1927{
1928 return (num >= -128) && (num <= 127);
47926f60 1929}
252b5132
RH		 1930
1931static INLINE int
e3bb37b5 1932fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1933{
1934 return (num & 0xff) == num;
47926f60 1935}
252b5132
RH		 1936
1937static INLINE int
e3bb37b5 1938fits_in_unsigned_word (offsetT num)
252b5132
RH		 1939{
1940 return (num & 0xffff) == num;
47926f60 1941}
252b5132
RH		 1942
1943static INLINE int
e3bb37b5 1944fits_in_signed_word (offsetT num)
252b5132
RH		 1945{
1946 return (-32768 <= num) && (num <= 32767);
47926f60 1947}
2a962e6d 1948
3e73aa7c 1949static INLINE int
e3bb37b5 1950fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1951{
1952#ifndef BFD64
1953 return 1;
1954#else
1955 return (!(((offsetT) -1 << 31) & num)
1956 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1957#endif
1958} /* fits_in_signed_long() */
2a962e6d 1959
3e73aa7c 1960static INLINE int
e3bb37b5 1961fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1962{
1963#ifndef BFD64
1964 return 1;
1965#else
1966 return (num & (((offsetT) 2 << 31) - 1)) == num;
1967#endif
1968} /* fits_in_unsigned_long() */
252b5132 1969
43234a1e
L		 1970static INLINE int
1971fits_in_vec_disp8 (offsetT num)
1972{
1973 int shift = i.memshift;
1974 unsigned int mask;
1975
1976 if (shift == -1)
1977 abort ();
1978
1979 mask = (1 << shift) - 1;
1980
1981 /* Return 0 if NUM isn't properly aligned. */
1982 if ((num & mask))
1983 return 0;
1984
1985 /* Check if NUM will fit in 8bit after shift. */
1986 return fits_in_signed_byte (num >> shift);
1987}
1988
a683cc34
SP		 1989static INLINE int
1990fits_in_imm4 (offsetT num)
1991{
1992 return (num & 0xf) == num;
1993}
1994
40fb9820 1995static i386_operand_type
e3bb37b5 1996smallest_imm_type (offsetT num)
252b5132 1997{
40fb9820 1998 i386_operand_type t;
7ab9ffdd 1999
0dfbf9d7 2000 operand_type_set (&t, 0);
40fb9820
L		 2001 t.bitfield.imm64 = 1;
2002
2003 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2004 {
2005 /* This code is disabled on the 486 because all the Imm1 forms
2006 in the opcode table are slower on the i486. They're the
2007 versions with the implicitly specified single-position
2008 displacement, which has another syntax if you really want to
2009 use that form. */
40fb9820
L		 2010 t.bitfield.imm1 = 1;
2011 t.bitfield.imm8 = 1;
2012 t.bitfield.imm8s = 1;
2013 t.bitfield.imm16 = 1;
2014 t.bitfield.imm32 = 1;
2015 t.bitfield.imm32s = 1;
2016 }
2017 else if (fits_in_signed_byte (num))
2018 {
2019 t.bitfield.imm8 = 1;
2020 t.bitfield.imm8s = 1;
2021 t.bitfield.imm16 = 1;
2022 t.bitfield.imm32 = 1;
2023 t.bitfield.imm32s = 1;
2024 }
2025 else if (fits_in_unsigned_byte (num))
2026 {
2027 t.bitfield.imm8 = 1;
2028 t.bitfield.imm16 = 1;
2029 t.bitfield.imm32 = 1;
2030 t.bitfield.imm32s = 1;
2031 }
2032 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2033 {
2034 t.bitfield.imm16 = 1;
2035 t.bitfield.imm32 = 1;
2036 t.bitfield.imm32s = 1;
2037 }
2038 else if (fits_in_signed_long (num))
2039 {
2040 t.bitfield.imm32 = 1;
2041 t.bitfield.imm32s = 1;
2042 }
2043 else if (fits_in_unsigned_long (num))
2044 t.bitfield.imm32 = 1;
2045
2046 return t;
47926f60 2047}
252b5132 2048
847f7ad4 2049static offsetT
e3bb37b5 2050offset_in_range (offsetT val, int size)
847f7ad4 2051{
508866be 2052 addressT mask;
ba2adb93 2053
847f7ad4
AM		 2054 switch (size)
2055 {
508866be
L		 2056 case 1: mask = ((addressT) 1 << 8) - 1; break;
2057 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2058 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2059#ifdef BFD64
2060 case 8: mask = ((addressT) 2 << 63) - 1; break;
2061#endif
47926f60 2062 default: abort ();
847f7ad4
AM		 2063 }
2064
9de868bf
L		 2065#ifdef BFD64
2066 /* If BFD64, sign extend val for 32bit address mode. */
2067 if (flag_code != CODE_64BIT
2068 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2069 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2070 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2071#endif
ba2adb93 2072
47926f60 2073 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2074 {
2075 char buf1[40], buf2[40];
2076
2077 sprint_value (buf1, val);
2078 sprint_value (buf2, val & mask);
2079 as_warn (_("%s shortened to %s"), buf1, buf2);
2080 }
2081 return val & mask;
2082}
2083
c32fa91d
L		 2084enum PREFIX_GROUP
2085{
2086 PREFIX_EXIST = 0,
2087 PREFIX_LOCK,
2088 PREFIX_REP,
2089 PREFIX_OTHER
2090};
2091
2092/* Returns
2093 a. PREFIX_EXIST if attempting to add a prefix where one from the
2094 same class already exists.
2095 b. PREFIX_LOCK if lock prefix is added.
2096 c. PREFIX_REP if rep/repne prefix is added.
2097 d. PREFIX_OTHER if other prefix is added.
2098 */
2099
2100static enum PREFIX_GROUP
e3bb37b5 2101add_prefix (unsigned int prefix)
252b5132 2102{
c32fa91d 2103 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2104 unsigned int q;
252b5132 2105
29b0f896
AM		 2106 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2107 && flag_code == CODE_64BIT)
b1905489 2108 {
161a04f6
L		 2109 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2110 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2111 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2112 ret = PREFIX_EXIST;
b1905489
JB		 2113 q = REX_PREFIX;
2114 }
3e73aa7c 2115 else
b1905489
JB		 2116 {
2117 switch (prefix)
2118 {
2119 default:
2120 abort ();
2121
2122 case CS_PREFIX_OPCODE:
2123 case DS_PREFIX_OPCODE:
2124 case ES_PREFIX_OPCODE:
2125 case FS_PREFIX_OPCODE:
2126 case GS_PREFIX_OPCODE:
2127 case SS_PREFIX_OPCODE:
2128 q = SEG_PREFIX;
2129 break;
2130
2131 case REPNE_PREFIX_OPCODE:
2132 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2133 q = REP_PREFIX;
2134 ret = PREFIX_REP;
2135 break;
2136
b1905489 2137 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2138 q = LOCK_PREFIX;
2139 ret = PREFIX_LOCK;
b1905489
JB		 2140 break;
2141
2142 case FWAIT_OPCODE:
2143 q = WAIT_PREFIX;
2144 break;
2145
2146 case ADDR_PREFIX_OPCODE:
2147 q = ADDR_PREFIX;
2148 break;
2149
2150 case DATA_PREFIX_OPCODE:
2151 q = DATA_PREFIX;
2152 break;
2153 }
2154 if (i.prefix[q] != 0)
c32fa91d 2155 ret = PREFIX_EXIST;
b1905489 2156 }
252b5132 2157
b1905489 2158 if (ret)
252b5132 2159 {
b1905489
JB		 2160 if (!i.prefix[q])
2161 ++i.prefixes;
2162 i.prefix[q] |= prefix;
252b5132 2163 }
b1905489
JB		 2164 else
2165 as_bad (_("same type of prefix used twice"));
252b5132 2166
252b5132
RH		 2167 return ret;
2168}
2169
2170static void
78f12dd3 2171update_code_flag (int value, int check)
eecb386c 2172{
78f12dd3
L		 2173 PRINTF_LIKE ((*as_error));
2174
1e9cc1c2 2175 flag_code = (enum flag_code) value;
40fb9820
L		 2176 if (flag_code == CODE_64BIT)
2177 {
2178 cpu_arch_flags.bitfield.cpu64 = 1;
2179 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2180 }
2181 else
2182 {
2183 cpu_arch_flags.bitfield.cpu64 = 0;
2184 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2185 }
2186 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2187 {
78f12dd3
L		 2188 if (check)
2189 as_error = as_fatal;
2190 else
2191 as_error = as_bad;
2192 (*as_error) (_("64bit mode not supported on `%s'."),
2193 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2194 }
40fb9820 2195 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2196 {
78f12dd3
L		 2197 if (check)
2198 as_error = as_fatal;
2199 else
2200 as_error = as_bad;
2201 (*as_error) (_("32bit mode not supported on `%s'."),
2202 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2203 }
eecb386c
AM		 2204 stackop_size = '\0';
2205}
2206
78f12dd3
L		 2207static void
2208set_code_flag (int value)
2209{
2210 update_code_flag (value, 0);
2211}
2212
eecb386c 2213static void
e3bb37b5 2214set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2215{
1e9cc1c2 2216 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2217 if (flag_code != CODE_16BIT)
2218 abort ();
2219 cpu_arch_flags.bitfield.cpu64 = 0;
2220 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2221 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2222}
2223
2224static void
e3bb37b5 2225set_intel_syntax (int syntax_flag)
252b5132
RH		 2226{
2227 /* Find out if register prefixing is specified. */
2228 int ask_naked_reg = 0;
2229
2230 SKIP_WHITESPACE ();
29b0f896 2231 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2232 {
2233 char *string = input_line_pointer;
2234 int e = get_symbol_end ();
2235
47926f60 2236 if (strcmp (string, "prefix") == 0)
252b5132 2237 ask_naked_reg = 1;
47926f60 2238 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2239 ask_naked_reg = -1;
2240 else
d0b47220 2241 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2242 *input_line_pointer = e;
2243 }
2244 demand_empty_rest_of_line ();
c3332e24 2245
252b5132
RH		 2246 intel_syntax = syntax_flag;
2247
2248 if (ask_naked_reg == 0)
f86103b7
AM		 2249 allow_naked_reg = (intel_syntax
2250 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2251 else
2252 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2253
ee86248c 2254 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2255
e4a3b5a4 2256 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2257 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2258 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2259}
2260
1efbbeb4
L		 2261static void
2262set_intel_mnemonic (int mnemonic_flag)
2263{
e1d4d893 2264 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2265}
2266
db51cc60
L		 2267static void
2268set_allow_index_reg (int flag)
2269{
2270 allow_index_reg = flag;
2271}
2272
cb19c032 2273static void
7bab8ab5 2274set_check (int what)
cb19c032 2275{
7bab8ab5
JB		 2276 enum check_kind *kind;
2277 const char *str;
2278
2279 if (what)
2280 {
2281 kind = &operand_check;
2282 str = "operand";
2283 }
2284 else
2285 {
2286 kind = &sse_check;
2287 str = "sse";
2288 }
2289
cb19c032
L		 2290 SKIP_WHITESPACE ();
2291
2292 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2293 {
2294 char *string = input_line_pointer;
2295 int e = get_symbol_end ();
2296
2297 if (strcmp (string, "none") == 0)
7bab8ab5 2298 *kind = check_none;
cb19c032 2299 else if (strcmp (string, "warning") == 0)
7bab8ab5 2300 *kind = check_warning;
cb19c032 2301 else if (strcmp (string, "error") == 0)
7bab8ab5 2302 *kind = check_error;
cb19c032 2303 else
7bab8ab5 2304 as_bad (_("bad argument to %s_check directive."), str);
cb19c032
L		 2305 *input_line_pointer = e;
2306 }
2307 else
7bab8ab5 2308 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2309
2310 demand_empty_rest_of_line ();
2311}
2312
8a9036a4
L		 2313static void
2314check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2315 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2316{
2317#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2318 static const char *arch;
2319
2320 /* Intel LIOM is only supported on ELF. */
2321 if (!IS_ELF)
2322 return;
2323
2324 if (!arch)
2325 {
2326 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2327 use default_arch. */
2328 arch = cpu_arch_name;
2329 if (!arch)
2330 arch = default_arch;
2331 }
2332
3632d14b 2333 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2334 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2335 || new_flag.bitfield.cpul1om)
8a9036a4 2336 return;
76ba9986 2337
7a9068fe
L		 2338 /* If we are targeting Intel K1OM, we must enable it. */
2339 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2340 || new_flag.bitfield.cpuk1om)
2341 return;
2342
8a9036a4
L		 2343 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2344#endif
2345}
2346
e413e4e9 2347static void
e3bb37b5 2348set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2349{
47926f60 2350 SKIP_WHITESPACE ();
e413e4e9 2351
29b0f896 2352 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2353 {
2354 char *string = input_line_pointer;
2355 int e = get_symbol_end ();
91d6fa6a 2356 unsigned int j;
40fb9820 2357 i386_cpu_flags flags;
e413e4e9 2358
91d6fa6a 2359 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2360 {
91d6fa6a 2361 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2362 {
91d6fa6a 2363 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2364
5c6af06e
JB		 2365 if (*string != '.')
2366 {
91d6fa6a 2367 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2368 cpu_sub_arch_name = NULL;
91d6fa6a 2369 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2370 if (flag_code == CODE_64BIT)
2371 {
2372 cpu_arch_flags.bitfield.cpu64 = 1;
2373 cpu_arch_flags.bitfield.cpuno64 = 0;
2374 }
2375 else
2376 {
2377 cpu_arch_flags.bitfield.cpu64 = 0;
2378 cpu_arch_flags.bitfield.cpuno64 = 1;
2379 }
91d6fa6a
NC		 2380 cpu_arch_isa = cpu_arch[j].type;
2381 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2382 if (!cpu_arch_tune_set)
2383 {
2384 cpu_arch_tune = cpu_arch_isa;
2385 cpu_arch_tune_flags = cpu_arch_isa_flags;
2386 }
5c6af06e
JB		 2387 break;
2388 }
40fb9820 2389
22109423 2390 if (!cpu_arch[j].negated)
309d3373 2391 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2392 cpu_arch[j].flags);
309d3373
JB		 2393 else
2394 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2395 cpu_arch[j].flags);
0dfbf9d7 2396 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2397 {
6305a203
L		 2398 if (cpu_sub_arch_name)
2399 {
2400 char *name = cpu_sub_arch_name;
2401 cpu_sub_arch_name = concat (name,
91d6fa6a 2402 cpu_arch[j].name,
1bf57e9f 2403 (const char *) NULL);
6305a203
L		 2404 free (name);
2405 }
2406 else
91d6fa6a 2407 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2408 cpu_arch_flags = flags;
a586129e 2409 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2410 }
2411 *input_line_pointer = e;
2412 demand_empty_rest_of_line ();
2413 return;
e413e4e9
AM		 2414 }
2415 }
91d6fa6a 2416 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2417 as_bad (_("no such architecture: `%s'"), string);
2418
2419 *input_line_pointer = e;
2420 }
2421 else
2422 as_bad (_("missing cpu architecture"));
2423
fddf5b5b
AM		 2424 no_cond_jump_promotion = 0;
2425 if (*input_line_pointer == ','
29b0f896 2426 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2427 {
2428 char *string = ++input_line_pointer;
2429 int e = get_symbol_end ();
2430
2431 if (strcmp (string, "nojumps") == 0)
2432 no_cond_jump_promotion = 1;
2433 else if (strcmp (string, "jumps") == 0)
2434 ;
2435 else
2436 as_bad (_("no such architecture modifier: `%s'"), string);
2437
2438 *input_line_pointer = e;
2439 }
2440
e413e4e9
AM		 2441 demand_empty_rest_of_line ();
2442}
2443
8a9036a4
L		 2444enum bfd_architecture
2445i386_arch (void)
2446{
3632d14b 2447 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2448 {
2449 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2450 || flag_code != CODE_64BIT)
2451 as_fatal (_("Intel L1OM is 64bit ELF only"));
2452 return bfd_arch_l1om;
2453 }
7a9068fe
L		 2454 else if (cpu_arch_isa == PROCESSOR_K1OM)
2455 {
2456 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2457 || flag_code != CODE_64BIT)
2458 as_fatal (_("Intel K1OM is 64bit ELF only"));
2459 return bfd_arch_k1om;
2460 }
8a9036a4
L		 2461 else
2462 return bfd_arch_i386;
2463}
2464
b9d79e03 2465unsigned long
7016a5d5 2466i386_mach (void)
b9d79e03 2467{
351f65ca 2468 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2469 {
3632d14b 2470 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2471 {
351f65ca
L		 2472 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2473 || default_arch[6] != '\0')
8a9036a4
L		 2474 as_fatal (_("Intel L1OM is 64bit ELF only"));
2475 return bfd_mach_l1om;
2476 }
7a9068fe
L		 2477 else if (cpu_arch_isa == PROCESSOR_K1OM)
2478 {
2479 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2480 || default_arch[6] != '\0')
2481 as_fatal (_("Intel K1OM is 64bit ELF only"));
2482 return bfd_mach_k1om;
2483 }
351f65ca 2484 else if (default_arch[6] == '\0')
8a9036a4 2485 return bfd_mach_x86_64;
351f65ca
L		 2486 else
2487 return bfd_mach_x64_32;
8a9036a4 2488 }
b9d79e03
JH		 2489 else if (!strcmp (default_arch, "i386"))
2490 return bfd_mach_i386_i386;
2491 else
2b5d6a91 2492 as_fatal (_("unknown architecture"));
b9d79e03 2493}
b9d79e03 2494\f
252b5132 2495void
7016a5d5 2496md_begin (void)
252b5132
RH		 2497{
2498 const char *hash_err;
2499
47926f60 2500 /* Initialize op_hash hash table. */
252b5132
RH		 2501 op_hash = hash_new ();
2502
2503 {
d3ce72d0 2504 const insn_template *optab;
29b0f896 2505 templates *core_optab;
252b5132 2506
47926f60
KH		 2507 /* Setup for loop. */
2508 optab = i386_optab;
252b5132
RH		 2509 core_optab = (templates *) xmalloc (sizeof (templates));
2510 core_optab->start = optab;
2511
2512 while (1)
2513 {
2514 ++optab;
2515 if (optab->name == NULL
2516 || strcmp (optab->name, (optab - 1)->name) != 0)
2517 {
2518 /* different name --> ship out current template list;
47926f60 2519 add to hash table; & begin anew. */
252b5132
RH		 2520 core_optab->end = optab;
2521 hash_err = hash_insert (op_hash,
2522 (optab - 1)->name,
5a49b8ac 2523 (void *) core_optab);
252b5132
RH		 2524 if (hash_err)
2525 {
b37df7c4 2526 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2527 (optab - 1)->name,
2528 hash_err);
2529 }
2530 if (optab->name == NULL)
2531 break;
2532 core_optab = (templates *) xmalloc (sizeof (templates));
2533 core_optab->start = optab;
2534 }
2535 }
2536 }
2537
47926f60 2538 /* Initialize reg_hash hash table. */
252b5132
RH		 2539 reg_hash = hash_new ();
2540 {
29b0f896 2541 const reg_entry *regtab;
c3fe08fa 2542 unsigned int regtab_size = i386_regtab_size;
252b5132 2543
c3fe08fa 2544 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2545 {
5a49b8ac 2546 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2547 if (hash_err)
b37df7c4 2548 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2549 regtab->reg_name,
2550 hash_err);
252b5132
RH		 2551 }
2552 }
2553
47926f60 2554 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2555 {
29b0f896
AM		 2556 int c;
2557 char *p;
252b5132
RH		 2558
2559 for (c = 0; c < 256; c++)
2560 {
3882b010 2561 if (ISDIGIT (c))
252b5132
RH		 2562 {
2563 digit_chars[c] = c;
2564 mnemonic_chars[c] = c;
2565 register_chars[c] = c;
2566 operand_chars[c] = c;
2567 }
3882b010 2568 else if (ISLOWER (c))
252b5132
RH		 2569 {
2570 mnemonic_chars[c] = c;
2571 register_chars[c] = c;
2572 operand_chars[c] = c;
2573 }
3882b010 2574 else if (ISUPPER (c))
252b5132 2575 {
3882b010 2576 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2577 register_chars[c] = mnemonic_chars[c];
2578 operand_chars[c] = c;
2579 }
43234a1e
L		 2580 else if (c == '{' || c == '}')
2581 operand_chars[c] = c;
252b5132 2582
3882b010 2583 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2584 identifier_chars[c] = c;
2585 else if (c >= 128)
2586 {
2587 identifier_chars[c] = c;
2588 operand_chars[c] = c;
2589 }
2590 }
2591
2592#ifdef LEX_AT
2593 identifier_chars['@'] = '@';
32137342
NC		 2594#endif
2595#ifdef LEX_QM
2596 identifier_chars['?'] = '?';
2597 operand_chars['?'] = '?';
252b5132 2598#endif
252b5132 2599 digit_chars['-'] = '-';
c0f3af97 2600 mnemonic_chars['_'] = '_';
791fe849 2601 mnemonic_chars['-'] = '-';
0003779b 2602 mnemonic_chars['.'] = '.';
252b5132
RH		 2603 identifier_chars['_'] = '_';
2604 identifier_chars['.'] = '.';
2605
2606 for (p = operand_special_chars; *p != '\0'; p++)
2607 operand_chars[(unsigned char) *p] = *p;
2608 }
2609
a4447b93
RH		 2610 if (flag_code == CODE_64BIT)
2611 {
ca19b261
KT		 2612#if defined (OBJ_COFF) && defined (TE_PE)
2613 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2614 ? 32 : 16);
2615#else
a4447b93 2616 x86_dwarf2_return_column = 16;
ca19b261 2617#endif
61ff971f 2618 x86_cie_data_alignment = -8;
a4447b93
RH		 2619 }
2620 else
2621 {
2622 x86_dwarf2_return_column = 8;
2623 x86_cie_data_alignment = -4;
2624 }
252b5132
RH		 2625}
2626
2627void
e3bb37b5 2628i386_print_statistics (FILE *file)
252b5132
RH		 2629{
2630 hash_print_statistics (file, "i386 opcode", op_hash);
2631 hash_print_statistics (file, "i386 register", reg_hash);
2632}
2633\f
252b5132
RH		 2634#ifdef DEBUG386
2635
ce8a8b2f 2636/* Debugging routines for md_assemble. */
d3ce72d0 2637static void pte (insn_template *);
40fb9820 2638static void pt (i386_operand_type);
e3bb37b5
L		 2639static void pe (expressionS *);
2640static void ps (symbolS *);
252b5132
RH		 2641
2642static void
e3bb37b5 2643pi (char *line, i386_insn *x)
252b5132 2644{
09137c09 2645 unsigned int j;
252b5132
RH		 2646
2647 fprintf (stdout, "%s: template ", line);
2648 pte (&x->tm);
09f131f2
JH		 2649 fprintf (stdout, " address: base %s index %s scale %x\n",
2650 x->base_reg ? x->base_reg->reg_name : "none",
2651 x->index_reg ? x->index_reg->reg_name : "none",
2652 x->log2_scale_factor);
2653 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2654 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2655 fprintf (stdout, " sib: base %x index %x scale %x\n",
2656 x->sib.base, x->sib.index, x->sib.scale);
2657 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2658 (x->rex & REX_W) != 0,
2659 (x->rex & REX_R) != 0,
2660 (x->rex & REX_X) != 0,
2661 (x->rex & REX_B) != 0);
09137c09 2662 for (j = 0; j < x->operands; j++)
252b5132 2663 {
09137c09
SP		 2664 fprintf (stdout, " #%d: ", j + 1);
2665 pt (x->types[j]);
252b5132 2666 fprintf (stdout, "\n");
09137c09
SP		 2667 if (x->types[j].bitfield.reg8
2668 || x->types[j].bitfield.reg16
2669 || x->types[j].bitfield.reg32
2670 || x->types[j].bitfield.reg64
2671 || x->types[j].bitfield.regmmx
2672 || x->types[j].bitfield.regxmm
2673 || x->types[j].bitfield.regymm
43234a1e 2674 || x->types[j].bitfield.regzmm
09137c09
SP		 2675 || x->types[j].bitfield.sreg2
2676 || x->types[j].bitfield.sreg3
2677 || x->types[j].bitfield.control
2678 || x->types[j].bitfield.debug
2679 || x->types[j].bitfield.test)
2680 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2681 if (operand_type_check (x->types[j], imm))
2682 pe (x->op[j].imms);
2683 if (operand_type_check (x->types[j], disp))
2684 pe (x->op[j].disps);
252b5132
RH		 2685 }
2686}
2687
2688static void
d3ce72d0 2689pte (insn_template *t)
252b5132 2690{
09137c09 2691 unsigned int j;
252b5132 2692 fprintf (stdout, " %d operands ", t->operands);
47926f60 2693 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2694 if (t->extension_opcode != None)
2695 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2696 if (t->opcode_modifier.d)
252b5132 2697 fprintf (stdout, "D");
40fb9820 2698 if (t->opcode_modifier.w)
252b5132
RH		 2699 fprintf (stdout, "W");
2700 fprintf (stdout, "\n");
09137c09 2701 for (j = 0; j < t->operands; j++)
252b5132 2702 {
09137c09
SP		 2703 fprintf (stdout, " #%d type ", j + 1);
2704 pt (t->operand_types[j]);
252b5132
RH		 2705 fprintf (stdout, "\n");
2706 }
2707}
2708
2709static void
e3bb37b5 2710pe (expressionS *e)
252b5132 2711{
24eab124 2712 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2713 fprintf (stdout, " add_number %ld (%lx)\n",
2714 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2715 if (e->X_add_symbol)
2716 {
2717 fprintf (stdout, " add_symbol ");
2718 ps (e->X_add_symbol);
2719 fprintf (stdout, "\n");
2720 }
2721 if (e->X_op_symbol)
2722 {
2723 fprintf (stdout, " op_symbol ");
2724 ps (e->X_op_symbol);
2725 fprintf (stdout, "\n");
2726 }
2727}
2728
2729static void
e3bb37b5 2730ps (symbolS *s)
252b5132
RH		 2731{
2732 fprintf (stdout, "%s type %s%s",
2733 S_GET_NAME (s),
2734 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2735 segment_name (S_GET_SEGMENT (s)));
2736}
2737
7b81dfbb 2738static struct type_name
252b5132 2739 {
40fb9820
L		 2740 i386_operand_type mask;
2741 const char *name;
252b5132 2742 }
7b81dfbb 2743const type_names[] =
252b5132 2744{
40fb9820
L		 2745 { OPERAND_TYPE_REG8, "r8" },
2746 { OPERAND_TYPE_REG16, "r16" },
2747 { OPERAND_TYPE_REG32, "r32" },
2748 { OPERAND_TYPE_REG64, "r64" },
2749 { OPERAND_TYPE_IMM8, "i8" },
2750 { OPERAND_TYPE_IMM8, "i8s" },
2751 { OPERAND_TYPE_IMM16, "i16" },
2752 { OPERAND_TYPE_IMM32, "i32" },
2753 { OPERAND_TYPE_IMM32S, "i32s" },
2754 { OPERAND_TYPE_IMM64, "i64" },
2755 { OPERAND_TYPE_IMM1, "i1" },
2756 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2757 { OPERAND_TYPE_DISP8, "d8" },
2758 { OPERAND_TYPE_DISP16, "d16" },
2759 { OPERAND_TYPE_DISP32, "d32" },
2760 { OPERAND_TYPE_DISP32S, "d32s" },
2761 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2762 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2763 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2764 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2765 { OPERAND_TYPE_CONTROL, "control reg" },
2766 { OPERAND_TYPE_TEST, "test reg" },
2767 { OPERAND_TYPE_DEBUG, "debug reg" },
2768 { OPERAND_TYPE_FLOATREG, "FReg" },
2769 { OPERAND_TYPE_FLOATACC, "FAcc" },
2770 { OPERAND_TYPE_SREG2, "SReg2" },
2771 { OPERAND_TYPE_SREG3, "SReg3" },
2772 { OPERAND_TYPE_ACC, "Acc" },
2773 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2774 { OPERAND_TYPE_REGMMX, "rMMX" },
2775 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2776 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2777 { OPERAND_TYPE_REGZMM, "rZMM" },
2778 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2779 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2780};
2781
2782static void
40fb9820 2783pt (i386_operand_type t)
252b5132 2784{
40fb9820 2785 unsigned int j;
c6fb90c8 2786 i386_operand_type a;
252b5132 2787
40fb9820 2788 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2789 {
2790 a = operand_type_and (t, type_names[j].mask);
0349dc08 2791 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2792 fprintf (stdout, "%s, ", type_names[j].name);
2793 }
252b5132
RH		 2794 fflush (stdout);
2795}
2796
2797#endif /* DEBUG386 */
2798\f
252b5132 2799static bfd_reloc_code_real_type
3956db08 2800reloc (unsigned int size,
64e74474
AM		 2801 int pcrel,
2802 int sign,
2803 bfd_reloc_code_real_type other)
252b5132 2804{
47926f60 2805 if (other != NO_RELOC)
3956db08 2806 {
91d6fa6a 2807 reloc_howto_type *rel;
3956db08
JB		 2808
2809 if (size == 8)
2810 switch (other)
2811 {
64e74474
AM		 2812 case BFD_RELOC_X86_64_GOT32:
2813 return BFD_RELOC_X86_64_GOT64;
2814 break;
2815 case BFD_RELOC_X86_64_PLTOFF64:
2816 return BFD_RELOC_X86_64_PLTOFF64;
2817 break;
2818 case BFD_RELOC_X86_64_GOTPC32:
2819 other = BFD_RELOC_X86_64_GOTPC64;
2820 break;
2821 case BFD_RELOC_X86_64_GOTPCREL:
2822 other = BFD_RELOC_X86_64_GOTPCREL64;
2823 break;
2824 case BFD_RELOC_X86_64_TPOFF32:
2825 other = BFD_RELOC_X86_64_TPOFF64;
2826 break;
2827 case BFD_RELOC_X86_64_DTPOFF32:
2828 other = BFD_RELOC_X86_64_DTPOFF64;
2829 break;
2830 default:
2831 break;
3956db08 2832 }
e05278af 2833
8ce3d284 2834#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2835 if (other == BFD_RELOC_SIZE32)
2836 {
2837 if (size == 8)
2838 return BFD_RELOC_SIZE64;
2839 if (pcrel)
2840 as_bad (_("there are no pc-relative size relocations"));
2841 }
8ce3d284 2842#endif
8fd4256d 2843
e05278af 2844 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2845 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2846 sign = -1;
2847
91d6fa6a
NC		 2848 rel = bfd_reloc_type_lookup (stdoutput, other);
2849 if (!rel)
3956db08 2850 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2851 else if (size != bfd_get_reloc_size (rel))
3956db08 2852 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2853 bfd_get_reloc_size (rel),
3956db08 2854 size);
91d6fa6a 2855 else if (pcrel && !rel->pc_relative)
3956db08 2856 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2857 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2858 && !sign)
91d6fa6a 2859 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2860 && sign > 0))
3956db08
JB		 2861 as_bad (_("relocated field and relocation type differ in signedness"));
2862 else
2863 return other;
2864 return NO_RELOC;
2865 }
252b5132
RH		 2866
2867 if (pcrel)
2868 {
3e73aa7c 2869 if (!sign)
3956db08 2870 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2871 switch (size)
2872 {
2873 case 1: return BFD_RELOC_8_PCREL;
2874 case 2: return BFD_RELOC_16_PCREL;
2875 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2876 case 8: return BFD_RELOC_64_PCREL;
252b5132 2877 }
3956db08 2878 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2879 }
2880 else
2881 {
3956db08 2882 if (sign > 0)
e5cb08ac 2883 switch (size)
3e73aa7c
JH		 2884 {
2885 case 4: return BFD_RELOC_X86_64_32S;
2886 }
2887 else
2888 switch (size)
2889 {
2890 case 1: return BFD_RELOC_8;
2891 case 2: return BFD_RELOC_16;
2892 case 4: return BFD_RELOC_32;
2893 case 8: return BFD_RELOC_64;
2894 }
3956db08
JB		 2895 as_bad (_("cannot do %s %u byte relocation"),
2896 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2897 }
2898
0cc9e1d3 2899 return NO_RELOC;
252b5132
RH		 2900}
2901
47926f60
KH		 2902/* Here we decide which fixups can be adjusted to make them relative to
2903 the beginning of the section instead of the symbol. Basically we need
2904 to make sure that the dynamic relocations are done correctly, so in
2905 some cases we force the original symbol to be used. */
2906
252b5132 2907int
e3bb37b5 2908tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2909{
6d249963 2910#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2911 if (!IS_ELF)
31312f95
AM		 2912 return 1;
2913
a161fe53
AM		 2914 /* Don't adjust pc-relative references to merge sections in 64-bit
2915 mode. */
2916 if (use_rela_relocations
2917 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2918 && fixP->fx_pcrel)
252b5132 2919 return 0;
31312f95 2920
8d01d9a9
AJ		 2921 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2922 and changed later by validate_fix. */
2923 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2924 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2925 return 0;
2926
8fd4256d
L		 2927 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2928 for size relocations. */
2929 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2930 || fixP->fx_r_type == BFD_RELOC_SIZE64
2931 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2932 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2933 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2934 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2935 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2936 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2937 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2938 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2939 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2940 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2941 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2942 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2943 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2944 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2945 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2946 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2947 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2948 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2949 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2950 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2951 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2952 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2953 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2954 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2955 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2956 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2957 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2958 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2959 return 0;
31312f95 2960#endif
252b5132
RH		 2961 return 1;
2962}
252b5132 2963
b4cac588 2964static int
e3bb37b5 2965intel_float_operand (const char *mnemonic)
252b5132 2966{
9306ca4a
JB		 2967 /* Note that the value returned is meaningful only for opcodes with (memory)
2968 operands, hence the code here is free to improperly handle opcodes that
2969 have no operands (for better performance and smaller code). */
2970
2971 if (mnemonic[0] != 'f')
2972 return 0; /* non-math */
2973
2974 switch (mnemonic[1])
2975 {
2976 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2977 the fs segment override prefix not currently handled because no
2978 call path can make opcodes without operands get here */
2979 case 'i':
2980 return 2 /* integer op */;
2981 case 'l':
2982 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2983 return 3; /* fldcw/fldenv */
2984 break;
2985 case 'n':
2986 if (mnemonic[2] != 'o' /* fnop */)
2987 return 3; /* non-waiting control op */
2988 break;
2989 case 'r':
2990 if (mnemonic[2] == 's')
2991 return 3; /* frstor/frstpm */
2992 break;
2993 case 's':
2994 if (mnemonic[2] == 'a')
2995 return 3; /* fsave */
2996 if (mnemonic[2] == 't')
2997 {
2998 switch (mnemonic[3])
2999 {
3000 case 'c': /* fstcw */
3001 case 'd': /* fstdw */
3002 case 'e': /* fstenv */
3003 case 's': /* fsts[gw] */
3004 return 3;
3005 }
3006 }
3007 break;
3008 case 'x':
3009 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3010 return 0; /* fxsave/fxrstor are not really math ops */
3011 break;
3012 }
252b5132 3013
9306ca4a 3014 return 1;
252b5132
RH		 3015}
3016
c0f3af97
L		 3017/* Build the VEX prefix. */
3018
3019static void
d3ce72d0 3020build_vex_prefix (const insn_template *t)
c0f3af97
L		 3021{
3022 unsigned int register_specifier;
3023 unsigned int implied_prefix;
3024 unsigned int vector_length;
3025
3026 /* Check register specifier. */
3027 if (i.vex.register_specifier)
43234a1e
L		 3028 {
3029 register_specifier =
3030 ~register_number (i.vex.register_specifier) & 0xf;
3031 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3032 }
c0f3af97
L		 3033 else
3034 register_specifier = 0xf;
3035
fa99fab2
L		 3036 /* Use 2-byte VEX prefix by swappping destination and source
3037 operand. */
3038 if (!i.swap_operand
3039 && i.operands == i.reg_operands
7f399153 3040 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3041 && i.tm.opcode_modifier.s
3042 && i.rex == REX_B)
3043 {
3044 unsigned int xchg = i.operands - 1;
3045 union i386_op temp_op;
3046 i386_operand_type temp_type;
3047
3048 temp_type = i.types[xchg];
3049 i.types[xchg] = i.types[0];
3050 i.types[0] = temp_type;
3051 temp_op = i.op[xchg];
3052 i.op[xchg] = i.op[0];
3053 i.op[0] = temp_op;
3054
9c2799c2 3055 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3056
3057 i.rex = REX_R;
3058 xchg = i.rm.regmem;
3059 i.rm.regmem = i.rm.reg;
3060 i.rm.reg = xchg;
3061
3062 /* Use the next insn. */
3063 i.tm = t[1];
3064 }
3065
539f890d
L		 3066 if (i.tm.opcode_modifier.vex == VEXScalar)
3067 vector_length = avxscalar;
3068 else
3069 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3070
3071 switch ((i.tm.base_opcode >> 8) & 0xff)
3072 {
3073 case 0:
3074 implied_prefix = 0;
3075 break;
3076 case DATA_PREFIX_OPCODE:
3077 implied_prefix = 1;
3078 break;
3079 case REPE_PREFIX_OPCODE:
3080 implied_prefix = 2;
3081 break;
3082 case REPNE_PREFIX_OPCODE:
3083 implied_prefix = 3;
3084 break;
3085 default:
3086 abort ();
3087 }
3088
3089 /* Use 2-byte VEX prefix if possible. */
7f399153 3090 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3091 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3092 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3093 {
3094 /* 2-byte VEX prefix. */
3095 unsigned int r;
3096
3097 i.vex.length = 2;
3098 i.vex.bytes[0] = 0xc5;
3099
3100 /* Check the REX.R bit. */
3101 r = (i.rex & REX_R) ? 0 : 1;
3102 i.vex.bytes[1] = (r << 7
3103 | register_specifier << 3
3104 | vector_length << 2
3105 | implied_prefix);
3106 }
3107 else
3108 {
3109 /* 3-byte VEX prefix. */
3110 unsigned int m, w;
3111
f88c9eb0 3112 i.vex.length = 3;
f88c9eb0 3113
7f399153 3114 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3115 {
7f399153
L		 3116 case VEX0F:
3117 m = 0x1;
80de6e00 3118 i.vex.bytes[0] = 0xc4;
7f399153
L		 3119 break;
3120 case VEX0F38:
3121 m = 0x2;
80de6e00 3122 i.vex.bytes[0] = 0xc4;
7f399153
L		 3123 break;
3124 case VEX0F3A:
3125 m = 0x3;
80de6e00 3126 i.vex.bytes[0] = 0xc4;
7f399153
L		 3127 break;
3128 case XOP08:
5dd85c99
SP		 3129 m = 0x8;
3130 i.vex.bytes[0] = 0x8f;
7f399153
L		 3131 break;
3132 case XOP09:
f88c9eb0
SP		 3133 m = 0x9;
3134 i.vex.bytes[0] = 0x8f;
7f399153
L		 3135 break;
3136 case XOP0A:
f88c9eb0
SP		 3137 m = 0xa;
3138 i.vex.bytes[0] = 0x8f;
7f399153
L		 3139 break;
3140 default:
3141 abort ();
f88c9eb0 3142 }
c0f3af97 3143
c0f3af97
L		 3144 /* The high 3 bits of the second VEX byte are 1's compliment
3145 of RXB bits from REX. */
3146 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3147
3148 /* Check the REX.W bit. */
3149 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 3150 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 3151 {
3152 if (w)
3153 abort ();
3154
1ef99a7b 3155 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 3156 w = 1;
3157 }
3158
3159 i.vex.bytes[2] = (w << 7
3160 | register_specifier << 3
3161 | vector_length << 2
3162 | implied_prefix);
3163 }
3164}
3165
43234a1e
L		 3166/* Build the EVEX prefix. */
3167
3168static void
3169build_evex_prefix (void)
3170{
3171 unsigned int register_specifier;
3172 unsigned int implied_prefix;
3173 unsigned int m, w;
3174 rex_byte vrex_used = 0;
3175
3176 /* Check register specifier. */
3177 if (i.vex.register_specifier)
3178 {
3179 gas_assert ((i.vrex & REX_X) == 0);
3180
3181 register_specifier = i.vex.register_specifier->reg_num;
3182 if ((i.vex.register_specifier->reg_flags & RegRex))
3183 register_specifier += 8;
3184 /* The upper 16 registers are encoded in the fourth byte of the
3185 EVEX prefix. */
3186 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3187 i.vex.bytes[3] = 0x8;
3188 register_specifier = ~register_specifier & 0xf;
3189 }
3190 else
3191 {
3192 register_specifier = 0xf;
3193
3194 /* Encode upper 16 vector index register in the fourth byte of
3195 the EVEX prefix. */
3196 if (!(i.vrex & REX_X))
3197 i.vex.bytes[3] = 0x8;
3198 else
3199 vrex_used |= REX_X;
3200 }
3201
3202 switch ((i.tm.base_opcode >> 8) & 0xff)
3203 {
3204 case 0:
3205 implied_prefix = 0;
3206 break;
3207 case DATA_PREFIX_OPCODE:
3208 implied_prefix = 1;
3209 break;
3210 case REPE_PREFIX_OPCODE:
3211 implied_prefix = 2;
3212 break;
3213 case REPNE_PREFIX_OPCODE:
3214 implied_prefix = 3;
3215 break;
3216 default:
3217 abort ();
3218 }
3219
3220 /* 4 byte EVEX prefix. */
3221 i.vex.length = 4;
3222 i.vex.bytes[0] = 0x62;
3223
3224 /* mmmm bits. */
3225 switch (i.tm.opcode_modifier.vexopcode)
3226 {
3227 case VEX0F:
3228 m = 1;
3229 break;
3230 case VEX0F38:
3231 m = 2;
3232 break;
3233 case VEX0F3A:
3234 m = 3;
3235 break;
3236 default:
3237 abort ();
3238 break;
3239 }
3240
3241 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3242 bits from REX. */
3243 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3244
3245 /* The fifth bit of the second EVEX byte is 1's compliment of the
3246 REX_R bit in VREX. */
3247 if (!(i.vrex & REX_R))
3248 i.vex.bytes[1] |= 0x10;
3249 else
3250 vrex_used |= REX_R;
3251
3252 if ((i.reg_operands + i.imm_operands) == i.operands)
3253 {
3254 /* When all operands are registers, the REX_X bit in REX is not
3255 used. We reuse it to encode the upper 16 registers, which is
3256 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3257 as 1's compliment. */
3258 if ((i.vrex & REX_B))
3259 {
3260 vrex_used |= REX_B;
3261 i.vex.bytes[1] &= ~0x40;
3262 }
3263 }
3264
3265 /* EVEX instructions shouldn't need the REX prefix. */
3266 i.vrex &= ~vrex_used;
3267 gas_assert (i.vrex == 0);
3268
3269 /* Check the REX.W bit. */
3270 w = (i.rex & REX_W) ? 1 : 0;
3271 if (i.tm.opcode_modifier.vexw)
3272 {
3273 if (i.tm.opcode_modifier.vexw == VEXW1)
3274 w = 1;
3275 }
3276 /* If w is not set it means we are dealing with WIG instruction. */
3277 else if (!w)
3278 {
3279 if (evexwig == evexw1)
3280 w = 1;
3281 }
3282
3283 /* Encode the U bit. */
3284 implied_prefix |= 0x4;
3285
3286 /* The third byte of the EVEX prefix. */
3287 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3288
3289 /* The fourth byte of the EVEX prefix. */
3290 /* The zeroing-masking bit. */
3291 if (i.mask && i.mask->zeroing)
3292 i.vex.bytes[3] |= 0x80;
3293
3294 /* Don't always set the broadcast bit if there is no RC. */
3295 if (!i.rounding)
3296 {
3297 /* Encode the vector length. */
3298 unsigned int vec_length;
3299
3300 switch (i.tm.opcode_modifier.evex)
3301 {
3302 case EVEXLIG: /* LL' is ignored */
3303 vec_length = evexlig << 5;
3304 break;
3305 case EVEX128:
3306 vec_length = 0 << 5;
3307 break;
3308 case EVEX256:
3309 vec_length = 1 << 5;
3310 break;
3311 case EVEX512:
3312 vec_length = 2 << 5;
3313 break;
3314 default:
3315 abort ();
3316 break;
3317 }
3318 i.vex.bytes[3] |= vec_length;
3319 /* Encode the broadcast bit. */
3320 if (i.broadcast)
3321 i.vex.bytes[3] |= 0x10;
3322 }
3323 else
3324 {
3325 if (i.rounding->type != saeonly)
3326 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3327 else
3328 i.vex.bytes[3] |= 0x10;
3329 }
3330
3331 if (i.mask && i.mask->mask)
3332 i.vex.bytes[3] |= i.mask->mask->reg_num;
3333}
3334
65da13b5
L		 3335static void
3336process_immext (void)
3337{
3338 expressionS *exp;
3339
4c692bc7
JB		 3340 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3341 && i.operands > 0)
65da13b5 3342 {
4c692bc7
JB		 3343 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3344 with an opcode suffix which is coded in the same place as an
3345 8-bit immediate field would be.
3346 Here we check those operands and remove them afterwards. */
65da13b5
L		 3347 unsigned int x;
3348
3349 for (x = 0; x < i.operands; x++)
4c692bc7 3350 if (register_number (i.op[x].regs) != x)
65da13b5 3351 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3352 register_prefix, i.op[x].regs->reg_name, x + 1,
3353 i.tm.name);
3354
3355 i.operands = 0;
65da13b5
L		 3356 }
3357
c0f3af97 3358 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3359 which is coded in the same place as an 8-bit immediate field
3360 would be. Here we fake an 8-bit immediate operand from the
3361 opcode suffix stored in tm.extension_opcode.
3362
c1e679ec 3363 AVX instructions also use this encoding, for some of
c0f3af97 3364 3 argument instructions. */
65da13b5 3365
43234a1e 3366 gas_assert (i.imm_operands <= 1
7ab9ffdd 3367 && (i.operands <= 2
43234a1e
L		 3368 || ((i.tm.opcode_modifier.vex
3369 || i.tm.opcode_modifier.evex)
7ab9ffdd 3370 && i.operands <= 4)));
65da13b5
L		 3371
3372 exp = &im_expressions[i.imm_operands++];
3373 i.op[i.operands].imms = exp;
3374 i.types[i.operands] = imm8;
3375 i.operands++;
3376 exp->X_op = O_constant;
3377 exp->X_add_number = i.tm.extension_opcode;
3378 i.tm.extension_opcode = None;
3379}
3380
42164a71
L		 3381
3382static int
3383check_hle (void)
3384{
3385 switch (i.tm.opcode_modifier.hleprefixok)
3386 {
3387 default:
3388 abort ();
82c2def5 3389 case HLEPrefixNone:
165de32a
L		 3390 as_bad (_("invalid instruction `%s' after `%s'"),
3391 i.tm.name, i.hle_prefix);
42164a71 3392 return 0;
82c2def5 3393 case HLEPrefixLock:
42164a71
L		 3394 if (i.prefix[LOCK_PREFIX])
3395 return 1;
165de32a 3396 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3397 return 0;
82c2def5 3398 case HLEPrefixAny:
42164a71 3399 return 1;
82c2def5 3400 case HLEPrefixRelease:
42164a71
L		 3401 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3402 {
3403 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3404 i.tm.name);
3405 return 0;
3406 }
3407 if (i.mem_operands == 0
3408 || !operand_type_check (i.types[i.operands - 1], anymem))
3409 {
3410 as_bad (_("memory destination needed for instruction `%s'"
3411 " after `xrelease'"), i.tm.name);
3412 return 0;
3413 }
3414 return 1;
3415 }
3416}
3417
252b5132
RH		 3418/* This is the guts of the machine-dependent assembler. LINE points to a
3419 machine dependent instruction. This function is supposed to emit
3420 the frags/bytes it assembles to. */
3421
3422void
65da13b5 3423md_assemble (char *line)
252b5132 3424{
40fb9820 3425 unsigned int j;
252b5132 3426 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3427 const insn_template *t;
252b5132 3428
47926f60 3429 /* Initialize globals. */
252b5132
RH		 3430 memset (&i, '\0', sizeof (i));
3431 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3432 i.reloc[j] = NO_RELOC;
252b5132
RH		 3433 memset (disp_expressions, '\0', sizeof (disp_expressions));
3434 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3435 save_stack_p = save_stack;
252b5132
RH		 3436
3437 /* First parse an instruction mnemonic & call i386_operand for the operands.
3438 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3439 start of a (possibly prefixed) mnemonic. */
252b5132 3440
29b0f896
AM		 3441 line = parse_insn (line, mnemonic);
3442 if (line == NULL)
3443 return;
252b5132 3444
29b0f896 3445 line = parse_operands (line, mnemonic);
ee86248c 3446 this_operand = -1;
29b0f896
AM		 3447 if (line == NULL)
3448 return;
252b5132 3449
29b0f896
AM		 3450 /* Now we've parsed the mnemonic into a set of templates, and have the
3451 operands at hand. */
3452
3453 /* All intel opcodes have reversed operands except for "bound" and
3454 "enter". We also don't reverse intersegment "jmp" and "call"
3455 instructions with 2 immediate operands so that the immediate segment
050dfa73 3456 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3457 if (intel_syntax
3458 && i.operands > 1
29b0f896 3459 && (strcmp (mnemonic, "bound") != 0)
30123838 3460 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3461 && !(operand_type_check (i.types[0], imm)
3462 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3463 swap_operands ();
3464
ec56d5c0
JB		 3465 /* The order of the immediates should be reversed
3466 for 2 immediates extrq and insertq instructions */
3467 if (i.imm_operands == 2
3468 && (strcmp (mnemonic, "extrq") == 0
3469 || strcmp (mnemonic, "insertq") == 0))
3470 swap_2_operands (0, 1);
3471
29b0f896
AM		 3472 if (i.imm_operands)
3473 optimize_imm ();
3474
b300c311
L		 3475 /* Don't optimize displacement for movabs since it only takes 64bit
3476 displacement. */
3477 if (i.disp_operands
a501d77e 3478 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3479 && (flag_code != CODE_64BIT
3480 || strcmp (mnemonic, "movabs") != 0))
3481 optimize_disp ();
29b0f896
AM		 3482
3483 /* Next, we find a template that matches the given insn,
3484 making sure the overlap of the given operands types is consistent
3485 with the template operand types. */
252b5132 3486
fa99fab2 3487 if (!(t = match_template ()))
29b0f896 3488 return;
252b5132 3489
7bab8ab5 3490 if (sse_check != check_none
81f8a913 3491 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3492 && (i.tm.cpu_flags.bitfield.cpusse
3493 || i.tm.cpu_flags.bitfield.cpusse2
3494 || i.tm.cpu_flags.bitfield.cpusse3
3495 || i.tm.cpu_flags.bitfield.cpussse3
3496 || i.tm.cpu_flags.bitfield.cpusse4_1
3497 || i.tm.cpu_flags.bitfield.cpusse4_2))
3498 {
7bab8ab5 3499 (sse_check == check_warning
daf50ae7
L		 3500 ? as_warn
3501 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3502 }
3503
321fd21e
L		 3504 /* Zap movzx and movsx suffix. The suffix has been set from
3505 "word ptr" or "byte ptr" on the source operand in Intel syntax
3506 or extracted from mnemonic in AT&T syntax. But we'll use
3507 the destination register to choose the suffix for encoding. */
3508 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3509 {
321fd21e
L		 3510 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3511 there is no suffix, the default will be byte extension. */
3512 if (i.reg_operands != 2
3513 && !i.suffix
7ab9ffdd 3514 && intel_syntax)
321fd21e
L		 3515 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3516
3517 i.suffix = 0;
cd61ebfe 3518 }
24eab124 3519
40fb9820 3520 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3521 if (!add_prefix (FWAIT_OPCODE))
3522 return;
252b5132 3523
d5de92cf
L		 3524 /* Check if REP prefix is OK. */
3525 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3526 {
3527 as_bad (_("invalid instruction `%s' after `%s'"),
3528 i.tm.name, i.rep_prefix);
3529 return;
3530 }
3531
c1ba0266
L		 3532 /* Check for lock without a lockable instruction. Destination operand
3533 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3534 if (i.prefix[LOCK_PREFIX]
3535 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3536 || i.mem_operands == 0
3537 || (i.tm.base_opcode != 0x86
3538 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3539 {
3540 as_bad (_("expecting lockable instruction after `lock'"));
3541 return;
3542 }
3543
42164a71 3544 /* Check if HLE prefix is OK. */
165de32a 3545 if (i.hle_prefix && !check_hle ())
42164a71
L		 3546 return;
3547
7e8b059b
L		 3548 /* Check BND prefix. */
3549 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3550 as_bad (_("expecting valid branch instruction after `bnd'"));
3551
3552 if (i.tm.cpu_flags.bitfield.cpumpx
3553 && flag_code == CODE_64BIT
3554 && i.prefix[ADDR_PREFIX])
3555 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3556
3557 /* Insert BND prefix. */
3558 if (add_bnd_prefix
3559 && i.tm.opcode_modifier.bndprefixok
3560 && !i.prefix[BND_PREFIX])
3561 add_prefix (BND_PREFIX_OPCODE);
3562
29b0f896 3563 /* Check string instruction segment overrides. */
40fb9820 3564 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3565 {
3566 if (!check_string ())
5dd0794d 3567 return;
fc0763e6 3568 i.disp_operands = 0;
29b0f896 3569 }
5dd0794d 3570
29b0f896
AM		 3571 if (!process_suffix ())
3572 return;
e413e4e9 3573
bc0844ae
L		 3574 /* Update operand types. */
3575 for (j = 0; j < i.operands; j++)
3576 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3577
29b0f896
AM		 3578 /* Make still unresolved immediate matches conform to size of immediate
3579 given in i.suffix. */
3580 if (!finalize_imm ())
3581 return;
252b5132 3582
40fb9820 3583 if (i.types[0].bitfield.imm1)
29b0f896 3584 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3585
9afe6eb8
L		 3586 /* We only need to check those implicit registers for instructions
3587 with 3 operands or less. */
3588 if (i.operands <= 3)
3589 for (j = 0; j < i.operands; j++)
3590 if (i.types[j].bitfield.inoutportreg
3591 || i.types[j].bitfield.shiftcount
3592 || i.types[j].bitfield.acc
3593 || i.types[j].bitfield.floatacc)
3594 i.reg_operands--;
40fb9820 3595
c0f3af97
L		 3596 /* ImmExt should be processed after SSE2AVX. */
3597 if (!i.tm.opcode_modifier.sse2avx
3598 && i.tm.opcode_modifier.immext)
65da13b5 3599 process_immext ();
252b5132 3600
29b0f896
AM		 3601 /* For insns with operands there are more diddles to do to the opcode. */
3602 if (i.operands)
3603 {
3604 if (!process_operands ())
3605 return;
3606 }
40fb9820 3607 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3608 {
3609 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3610 as_warn (_("translating to `%sp'"), i.tm.name);
3611 }
252b5132 3612
c0f3af97 3613 if (i.tm.opcode_modifier.vex)
fa99fab2 3614 build_vex_prefix (t);
c0f3af97 3615
43234a1e
L		 3616 if (i.tm.opcode_modifier.evex)
3617 build_evex_prefix ();
3618
5dd85c99
SP		 3619 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3620 instructions may define INT_OPCODE as well, so avoid this corner
3621 case for those instructions that use MODRM. */
3622 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3623 && !i.tm.opcode_modifier.modrm
3624 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3625 {
3626 i.tm.base_opcode = INT3_OPCODE;
3627 i.imm_operands = 0;
3628 }
252b5132 3629
40fb9820
L		 3630 if ((i.tm.opcode_modifier.jump
3631 || i.tm.opcode_modifier.jumpbyte
3632 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3633 && i.op[0].disps->X_op == O_constant)
3634 {
3635 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3636 the absolute address given by the constant. Since ix86 jumps and
3637 calls are pc relative, we need to generate a reloc. */
3638 i.op[0].disps->X_add_symbol = &abs_symbol;
3639 i.op[0].disps->X_op = O_symbol;
3640 }
252b5132 3641
40fb9820 3642 if (i.tm.opcode_modifier.rex64)
161a04f6 3643 i.rex |= REX_W;
252b5132 3644
29b0f896
AM		 3645 /* For 8 bit registers we need an empty rex prefix. Also if the
3646 instruction already has a prefix, we need to convert old
3647 registers to new ones. */
773f551c 3648
40fb9820 3649 if ((i.types[0].bitfield.reg8
29b0f896 3650 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3651 || (i.types[1].bitfield.reg8
29b0f896 3652 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3653 || ((i.types[0].bitfield.reg8
3654 || i.types[1].bitfield.reg8)
29b0f896
AM		 3655 && i.rex != 0))
3656 {
3657 int x;
726c5dcd 3658
29b0f896
AM		 3659 i.rex |= REX_OPCODE;
3660 for (x = 0; x < 2; x++)
3661 {
3662 /* Look for 8 bit operand that uses old registers. */
40fb9820 3663 if (i.types[x].bitfield.reg8
29b0f896 3664 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3665 {
29b0f896
AM		 3666 /* In case it is "hi" register, give up. */
3667 if (i.op[x].regs->reg_num > 3)
a540244d 3668 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3669 "instruction requiring REX prefix."),
a540244d 3670 register_prefix, i.op[x].regs->reg_name);
773f551c 3671
29b0f896
AM		 3672 /* Otherwise it is equivalent to the extended register.
3673 Since the encoding doesn't change this is merely
3674 cosmetic cleanup for debug output. */
3675
3676 i.op[x].regs = i.op[x].regs + 8;
773f551c 3677 }
29b0f896
AM		 3678 }
3679 }
773f551c 3680
7ab9ffdd 3681 if (i.rex != 0)
29b0f896
AM		 3682 add_prefix (REX_OPCODE | i.rex);
3683
3684 /* We are ready to output the insn. */
3685 output_insn ();
3686}
3687
3688static char *
e3bb37b5 3689parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3690{
3691 char *l = line;
3692 char *token_start = l;
3693 char *mnem_p;
5c6af06e 3694 int supported;
d3ce72d0 3695 const insn_template *t;
b6169b20 3696 char *dot_p = NULL;
29b0f896 3697
29b0f896
AM		 3698 while (1)
3699 {
3700 mnem_p = mnemonic;
3701 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3702 {
b6169b20
L		 3703 if (*mnem_p == '.')
3704 dot_p = mnem_p;
29b0f896
AM		 3705 mnem_p++;
3706 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3707 {
29b0f896
AM		 3708 as_bad (_("no such instruction: `%s'"), token_start);
3709 return NULL;
3710 }
3711 l++;
3712 }
3713 if (!is_space_char (*l)
3714 && *l != END_OF_INSN
e44823cf
JB		 3715 && (intel_syntax
3716 || (*l != PREFIX_SEPARATOR
3717 && *l != ',')))
29b0f896
AM		 3718 {
3719 as_bad (_("invalid character %s in mnemonic"),
3720 output_invalid (*l));
3721 return NULL;
3722 }
3723 if (token_start == l)
3724 {
e44823cf 3725 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3726 as_bad (_("expecting prefix; got nothing"));
3727 else
3728 as_bad (_("expecting mnemonic; got nothing"));
3729 return NULL;
3730 }
45288df1 3731
29b0f896 3732 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3733 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3734
29b0f896
AM		 3735 if (*l != END_OF_INSN
3736 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3737 && current_templates
40fb9820 3738 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3739 {
c6fb90c8 3740 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3741 {
3742 as_bad ((flag_code != CODE_64BIT
3743 ? _("`%s' is only supported in 64-bit mode")
3744 : _("`%s' is not supported in 64-bit mode")),
3745 current_templates->start->name);
3746 return NULL;
3747 }
29b0f896
AM		 3748 /* If we are in 16-bit mode, do not allow addr16 or data16.
3749 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3750 if ((current_templates->start->opcode_modifier.size16
3751 || current_templates->start->opcode_modifier.size32)
29b0f896 3752 && flag_code != CODE_64BIT
40fb9820 3753 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3754 ^ (flag_code == CODE_16BIT)))
3755 {
3756 as_bad (_("redundant %s prefix"),
3757 current_templates->start->name);
3758 return NULL;
45288df1 3759 }
29b0f896
AM		 3760 /* Add prefix, checking for repeated prefixes. */
3761 switch (add_prefix (current_templates->start->base_opcode))
3762 {
c32fa91d 3763 case PREFIX_EXIST:
29b0f896 3764 return NULL;
c32fa91d 3765 case PREFIX_REP:
42164a71 3766 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3767 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3768 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3769 i.bnd_prefix = current_templates->start->name;
42164a71 3770 else
d5de92cf 3771 i.rep_prefix = current_templates->start->name;
29b0f896 3772 break;
c32fa91d
L		 3773 default:
3774 break;
29b0f896
AM		 3775 }
3776 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3777 token_start = ++l;
3778 }
3779 else
3780 break;
3781 }
45288df1 3782
30a55f88 3783 if (!current_templates)
b6169b20 3784 {
f8a5c266
L		 3785 /* Check if we should swap operand or force 32bit displacement in
3786 encoding. */
30a55f88
L		 3787 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3788 i.swap_operand = 1;
8d63c93e 3789 else if (mnem_p - 3 == dot_p
a501d77e
L		 3790 && dot_p[1] == 'd'
3791 && dot_p[2] == '8')
3792 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3793 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3794 && dot_p[1] == 'd'
3795 && dot_p[2] == '3'
3796 && dot_p[3] == '2')
a501d77e 3797 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3798 else
3799 goto check_suffix;
3800 mnem_p = dot_p;
3801 *dot_p = '\0';
d3ce72d0 3802 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3803 }
3804
29b0f896
AM		 3805 if (!current_templates)
3806 {
b6169b20 3807check_suffix:
29b0f896
AM		 3808 /* See if we can get a match by trimming off a suffix. */
3809 switch (mnem_p[-1])
3810 {
3811 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3812 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3813 i.suffix = SHORT_MNEM_SUFFIX;
3814 else
29b0f896
AM		 3815 case BYTE_MNEM_SUFFIX:
3816 case QWORD_MNEM_SUFFIX:
3817 i.suffix = mnem_p[-1];
3818 mnem_p[-1] = '\0';
d3ce72d0
NC		 3819 current_templates = (const templates *) hash_find (op_hash,
3820 mnemonic);
29b0f896
AM		 3821 break;
3822 case SHORT_MNEM_SUFFIX:
3823 case LONG_MNEM_SUFFIX:
3824 if (!intel_syntax)
3825 {
3826 i.suffix = mnem_p[-1];
3827 mnem_p[-1] = '\0';
d3ce72d0
NC		 3828 current_templates = (const templates *) hash_find (op_hash,
3829 mnemonic);
29b0f896
AM		 3830 }
3831 break;
252b5132 3832
29b0f896
AM		 3833 /* Intel Syntax. */
3834 case 'd':
3835 if (intel_syntax)
3836 {
9306ca4a 3837 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3838 i.suffix = SHORT_MNEM_SUFFIX;
3839 else
3840 i.suffix = LONG_MNEM_SUFFIX;
3841 mnem_p[-1] = '\0';
d3ce72d0
NC		 3842 current_templates = (const templates *) hash_find (op_hash,
3843 mnemonic);
29b0f896
AM		 3844 }
3845 break;
3846 }
3847 if (!current_templates)
3848 {
3849 as_bad (_("no such instruction: `%s'"), token_start);
3850 return NULL;
3851 }
3852 }
252b5132 3853
40fb9820
L		 3854 if (current_templates->start->opcode_modifier.jump
3855 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3856 {
3857 /* Check for a branch hint. We allow ",pt" and ",pn" for
3858 predict taken and predict not taken respectively.
3859 I'm not sure that branch hints actually do anything on loop
3860 and jcxz insns (JumpByte) for current Pentium4 chips. They
3861 may work in the future and it doesn't hurt to accept them
3862 now. */
3863 if (l[0] == ',' && l[1] == 'p')
3864 {
3865 if (l[2] == 't')
3866 {
3867 if (!add_prefix (DS_PREFIX_OPCODE))
3868 return NULL;
3869 l += 3;
3870 }
3871 else if (l[2] == 'n')
3872 {
3873 if (!add_prefix (CS_PREFIX_OPCODE))
3874 return NULL;
3875 l += 3;
3876 }
3877 }
3878 }
3879 /* Any other comma loses. */
3880 if (*l == ',')
3881 {
3882 as_bad (_("invalid character %s in mnemonic"),
3883 output_invalid (*l));
3884 return NULL;
3885 }
252b5132 3886
29b0f896 3887 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3888 supported = 0;
3889 for (t = current_templates->start; t < current_templates->end; ++t)
3890 {
c0f3af97
L		 3891 supported |= cpu_flags_match (t);
3892 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3893 goto skip;
5c6af06e 3894 }
3629bb00 3895
c0f3af97 3896 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3897 {
3898 as_bad (flag_code == CODE_64BIT
3899 ? _("`%s' is not supported in 64-bit mode")
3900 : _("`%s' is only supported in 64-bit mode"),
3901 current_templates->start->name);
3902 return NULL;
3903 }
c0f3af97 3904 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3905 {
3629bb00 3906 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3907 current_templates->start->name,
41aacd83 3908 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3909 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3910 return NULL;
29b0f896 3911 }
3629bb00
L		 3912
3913skip:
3914 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3915 && (flag_code != CODE_16BIT))
29b0f896
AM		 3916 {
3917 as_warn (_("use .code16 to ensure correct addressing mode"));
3918 }
252b5132 3919
29b0f896
AM		 3920 return l;
3921}
252b5132 3922
29b0f896 3923static char *
e3bb37b5 3924parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3925{
3926 char *token_start;
3138f287 3927
29b0f896
AM		 3928 /* 1 if operand is pending after ','. */
3929 unsigned int expecting_operand = 0;
252b5132 3930
29b0f896
AM		 3931 /* Non-zero if operand parens not balanced. */
3932 unsigned int paren_not_balanced;
3933
3934 while (*l != END_OF_INSN)
3935 {
3936 /* Skip optional white space before operand. */
3937 if (is_space_char (*l))
3938 ++l;
3939 if (!is_operand_char (*l) && *l != END_OF_INSN)
3940 {
3941 as_bad (_("invalid character %s before operand %d"),
3942 output_invalid (*l),
3943 i.operands + 1);
3944 return NULL;
3945 }
3946 token_start = l; /* after white space */
3947 paren_not_balanced = 0;
3948 while (paren_not_balanced || *l != ',')
3949 {
3950 if (*l == END_OF_INSN)
3951 {
3952 if (paren_not_balanced)
3953 {
3954 if (!intel_syntax)
3955 as_bad (_("unbalanced parenthesis in operand %d."),
3956 i.operands + 1);
3957 else
3958 as_bad (_("unbalanced brackets in operand %d."),
3959 i.operands + 1);
3960 return NULL;
3961 }
3962 else
3963 break; /* we are done */
3964 }
3965 else if (!is_operand_char (*l) && !is_space_char (*l))
3966 {
3967 as_bad (_("invalid character %s in operand %d"),
3968 output_invalid (*l),
3969 i.operands + 1);
3970 return NULL;
3971 }
3972 if (!intel_syntax)
3973 {
3974 if (*l == '(')
3975 ++paren_not_balanced;
3976 if (*l == ')')
3977 --paren_not_balanced;
3978 }
3979 else
3980 {
3981 if (*l == '[')
3982 ++paren_not_balanced;
3983 if (*l == ']')
3984 --paren_not_balanced;
3985 }
3986 l++;
3987 }
3988 if (l != token_start)
3989 { /* Yes, we've read in another operand. */
3990 unsigned int operand_ok;
3991 this_operand = i.operands++;
7d5e4556 3992 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3993 if (i.operands > MAX_OPERANDS)
3994 {
3995 as_bad (_("spurious operands; (%d operands/instruction max)"),
3996 MAX_OPERANDS);
3997 return NULL;
3998 }
3999 /* Now parse operand adding info to 'i' as we go along. */
4000 END_STRING_AND_SAVE (l);
4001
4002 if (intel_syntax)
4003 operand_ok =
4004 i386_intel_operand (token_start,
4005 intel_float_operand (mnemonic));
4006 else
a7619375 4007 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4008
4009 RESTORE_END_STRING (l);
4010 if (!operand_ok)
4011 return NULL;
4012 }
4013 else
4014 {
4015 if (expecting_operand)
4016 {
4017 expecting_operand_after_comma:
4018 as_bad (_("expecting operand after ','; got nothing"));
4019 return NULL;
4020 }
4021 if (*l == ',')
4022 {
4023 as_bad (_("expecting operand before ','; got nothing"));
4024 return NULL;
4025 }
4026 }
7f3f1ea2 4027
29b0f896
AM		 4028 /* Now *l must be either ',' or END_OF_INSN. */
4029 if (*l == ',')
4030 {
4031 if (*++l == END_OF_INSN)
4032 {
4033 /* Just skip it, if it's \n complain. */
4034 goto expecting_operand_after_comma;
4035 }
4036 expecting_operand = 1;
4037 }
4038 }
4039 return l;
4040}
7f3f1ea2 4041
050dfa73 4042static void
4d456e3d 4043swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4044{
4045 union i386_op temp_op;
40fb9820 4046 i386_operand_type temp_type;
050dfa73 4047 enum bfd_reloc_code_real temp_reloc;
4eed87de 4048
050dfa73
MM		 4049 temp_type = i.types[xchg2];
4050 i.types[xchg2] = i.types[xchg1];
4051 i.types[xchg1] = temp_type;
4052 temp_op = i.op[xchg2];
4053 i.op[xchg2] = i.op[xchg1];
4054 i.op[xchg1] = temp_op;
4055 temp_reloc = i.reloc[xchg2];
4056 i.reloc[xchg2] = i.reloc[xchg1];
4057 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4058
4059 if (i.mask)
4060 {
4061 if (i.mask->operand == xchg1)
4062 i.mask->operand = xchg2;
4063 else if (i.mask->operand == xchg2)
4064 i.mask->operand = xchg1;
4065 }
4066 if (i.broadcast)
4067 {
4068 if (i.broadcast->operand == xchg1)
4069 i.broadcast->operand = xchg2;
4070 else if (i.broadcast->operand == xchg2)
4071 i.broadcast->operand = xchg1;
4072 }
4073 if (i.rounding)
4074 {
4075 if (i.rounding->operand == xchg1)
4076 i.rounding->operand = xchg2;
4077 else if (i.rounding->operand == xchg2)
4078 i.rounding->operand = xchg1;
4079 }
050dfa73
MM		 4080}
4081
29b0f896 4082static void
e3bb37b5 4083swap_operands (void)
29b0f896 4084{
b7c61d9a 4085 switch (i.operands)
050dfa73 4086 {
c0f3af97 4087 case 5:
b7c61d9a 4088 case 4:
4d456e3d 4089 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4090 case 3:
4091 case 2:
4d456e3d 4092 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4093 break;
4094 default:
4095 abort ();
29b0f896 4096 }
29b0f896
AM		 4097
4098 if (i.mem_operands == 2)
4099 {
4100 const seg_entry *temp_seg;
4101 temp_seg = i.seg[0];
4102 i.seg[0] = i.seg[1];
4103 i.seg[1] = temp_seg;
4104 }
4105}
252b5132 4106
29b0f896
AM		 4107/* Try to ensure constant immediates are represented in the smallest
4108 opcode possible. */
4109static void
e3bb37b5 4110optimize_imm (void)
29b0f896
AM		 4111{
4112 char guess_suffix = 0;
4113 int op;
252b5132 4114
29b0f896
AM		 4115 if (i.suffix)
4116 guess_suffix = i.suffix;
4117 else if (i.reg_operands)
4118 {
4119 /* Figure out a suffix from the last register operand specified.
4120 We can't do this properly yet, ie. excluding InOutPortReg,
4121 but the following works for instructions with immediates.
4122 In any case, we can't set i.suffix yet. */
4123 for (op = i.operands; --op >= 0;)
40fb9820 4124 if (i.types[op].bitfield.reg8)
7ab9ffdd 4125 {
40fb9820
L		 4126 guess_suffix = BYTE_MNEM_SUFFIX;
4127 break;
4128 }
4129 else if (i.types[op].bitfield.reg16)
252b5132 4130 {
40fb9820
L		 4131 guess_suffix = WORD_MNEM_SUFFIX;
4132 break;
4133 }
4134 else if (i.types[op].bitfield.reg32)
4135 {
4136 guess_suffix = LONG_MNEM_SUFFIX;
4137 break;
4138 }
4139 else if (i.types[op].bitfield.reg64)
4140 {
4141 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4142 break;
252b5132 4143 }
29b0f896
AM		 4144 }
4145 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4146 guess_suffix = WORD_MNEM_SUFFIX;
4147
4148 for (op = i.operands; --op >= 0;)
40fb9820 4149 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4150 {
4151 switch (i.op[op].imms->X_op)
252b5132 4152 {
29b0f896
AM		 4153 case O_constant:
4154 /* If a suffix is given, this operand may be shortened. */
4155 switch (guess_suffix)
252b5132 4156 {
29b0f896 4157 case LONG_MNEM_SUFFIX:
40fb9820
L		 4158 i.types[op].bitfield.imm32 = 1;
4159 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4160 break;
4161 case WORD_MNEM_SUFFIX:
40fb9820
L		 4162 i.types[op].bitfield.imm16 = 1;
4163 i.types[op].bitfield.imm32 = 1;
4164 i.types[op].bitfield.imm32s = 1;
4165 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4166 break;
4167 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4168 i.types[op].bitfield.imm8 = 1;
4169 i.types[op].bitfield.imm8s = 1;
4170 i.types[op].bitfield.imm16 = 1;
4171 i.types[op].bitfield.imm32 = 1;
4172 i.types[op].bitfield.imm32s = 1;
4173 i.types[op].bitfield.imm64 = 1;
29b0f896 4174 break;
252b5132 4175 }
252b5132 4176
29b0f896
AM		 4177 /* If this operand is at most 16 bits, convert it
4178 to a signed 16 bit number before trying to see
4179 whether it will fit in an even smaller size.
4180 This allows a 16-bit operand such as $0xffe0 to
4181 be recognised as within Imm8S range. */
40fb9820 4182 if ((i.types[op].bitfield.imm16)
29b0f896 4183 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4184 {
29b0f896
AM		 4185 i.op[op].imms->X_add_number =
4186 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4187 }
40fb9820 4188 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4189 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4190 == 0))
4191 {
4192 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4193 ^ ((offsetT) 1 << 31))
4194 - ((offsetT) 1 << 31));
4195 }
40fb9820 4196 i.types[op]
c6fb90c8
L		 4197 = operand_type_or (i.types[op],
4198 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4199
29b0f896
AM		 4200 /* We must avoid matching of Imm32 templates when 64bit
4201 only immediate is available. */
4202 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4203 i.types[op].bitfield.imm32 = 0;
29b0f896 4204 break;
252b5132 4205
29b0f896
AM		 4206 case O_absent:
4207 case O_register:
4208 abort ();
4209
4210 /* Symbols and expressions. */
4211 default:
9cd96992
JB		 4212 /* Convert symbolic operand to proper sizes for matching, but don't
4213 prevent matching a set of insns that only supports sizes other
4214 than those matching the insn suffix. */
4215 {
40fb9820 4216 i386_operand_type mask, allowed;
d3ce72d0 4217 const insn_template *t;
9cd96992 4218
0dfbf9d7
L		 4219 operand_type_set (&mask, 0);
4220 operand_type_set (&allowed, 0);
40fb9820 4221
4eed87de
AM		 4222 for (t = current_templates->start;
4223 t < current_templates->end;
4224 ++t)
c6fb90c8
L		 4225 allowed = operand_type_or (allowed,
4226 t->operand_types[op]);
9cd96992
JB		 4227 switch (guess_suffix)
4228 {
4229 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4230 mask.bitfield.imm64 = 1;
4231 mask.bitfield.imm32s = 1;
9cd96992
JB		 4232 break;
4233 case LONG_MNEM_SUFFIX:
40fb9820 4234 mask.bitfield.imm32 = 1;
9cd96992
JB		 4235 break;
4236 case WORD_MNEM_SUFFIX:
40fb9820 4237 mask.bitfield.imm16 = 1;
9cd96992
JB		 4238 break;
4239 case BYTE_MNEM_SUFFIX:
40fb9820 4240 mask.bitfield.imm8 = 1;
9cd96992
JB		 4241 break;
4242 default:
9cd96992
JB		 4243 break;
4244 }
c6fb90c8 4245 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4246 if (!operand_type_all_zero (&allowed))
c6fb90c8 4247 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4248 }
29b0f896 4249 break;
252b5132 4250 }
29b0f896
AM		 4251 }
4252}
47926f60 4253
29b0f896
AM		 4254/* Try to use the smallest displacement type too. */
4255static void
e3bb37b5 4256optimize_disp (void)
29b0f896
AM		 4257{
4258 int op;
3e73aa7c 4259
29b0f896 4260 for (op = i.operands; --op >= 0;)
40fb9820 4261 if (operand_type_check (i.types[op], disp))
252b5132 4262 {
b300c311 4263 if (i.op[op].disps->X_op == O_constant)
252b5132 4264 {
91d6fa6a 4265 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4266
40fb9820 4267 if (i.types[op].bitfield.disp16
91d6fa6a 4268 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4269 {
4270 /* If this operand is at most 16 bits, convert
4271 to a signed 16 bit number and don't use 64bit
4272 displacement. */
91d6fa6a 4273 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4274 i.types[op].bitfield.disp64 = 0;
b300c311 4275 }
40fb9820 4276 if (i.types[op].bitfield.disp32
91d6fa6a 4277 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4278 {
4279 /* If this operand is at most 32 bits, convert
4280 to a signed 32 bit number and don't use 64bit
4281 displacement. */
91d6fa6a
NC		 4282 op_disp &= (((offsetT) 2 << 31) - 1);
4283 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4284 i.types[op].bitfield.disp64 = 0;
b300c311 4285 }
91d6fa6a 4286 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4287 {
40fb9820
L		 4288 i.types[op].bitfield.disp8 = 0;
4289 i.types[op].bitfield.disp16 = 0;
4290 i.types[op].bitfield.disp32 = 0;
4291 i.types[op].bitfield.disp32s = 0;
4292 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4293 i.op[op].disps = 0;
4294 i.disp_operands--;
4295 }
4296 else if (flag_code == CODE_64BIT)
4297 {
91d6fa6a 4298 if (fits_in_signed_long (op_disp))
28a9d8f5 4299 {
40fb9820
L		 4300 i.types[op].bitfield.disp64 = 0;
4301 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4302 }
0e1147d9 4303 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4304 && fits_in_unsigned_long (op_disp))
40fb9820 4305 i.types[op].bitfield.disp32 = 1;
b300c311 4306 }
40fb9820
L		 4307 if ((i.types[op].bitfield.disp32
4308 || i.types[op].bitfield.disp32s
4309 || i.types[op].bitfield.disp16)
91d6fa6a 4310 && fits_in_signed_byte (op_disp))
40fb9820 4311 i.types[op].bitfield.disp8 = 1;
252b5132 4312 }
67a4f2b7
AO		 4313 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4314 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4315 {
4316 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4317 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4318 i.types[op].bitfield.disp8 = 0;
4319 i.types[op].bitfield.disp16 = 0;
4320 i.types[op].bitfield.disp32 = 0;
4321 i.types[op].bitfield.disp32s = 0;
4322 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4323 }
4324 else
b300c311 4325 /* We only support 64bit displacement on constants. */
40fb9820 4326 i.types[op].bitfield.disp64 = 0;
252b5132 4327 }
29b0f896
AM		 4328}
4329
6c30d220
L		 4330/* Check if operands are valid for the instruction. */
4331
4332static int
4333check_VecOperands (const insn_template *t)
4334{
43234a1e
L		 4335 unsigned int op;
4336
6c30d220
L		 4337 /* Without VSIB byte, we can't have a vector register for index. */
4338 if (!t->opcode_modifier.vecsib
4339 && i.index_reg
4340 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4341 || i.index_reg->reg_type.bitfield.regymm
4342 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4343 {
4344 i.error = unsupported_vector_index_register;
4345 return 1;
4346 }
4347
7bab8ab5
JB		 4348 /* For VSIB byte, we need a vector register for index, and all vector
4349 registers must be distinct. */
4350 if (t->opcode_modifier.vecsib)
4351 {
4352 if (!i.index_reg
6c30d220
L		 4353 || !((t->opcode_modifier.vecsib == VecSIB128
4354 && i.index_reg->reg_type.bitfield.regxmm)
4355 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4356 && i.index_reg->reg_type.bitfield.regymm)
4357 || (t->opcode_modifier.vecsib == VecSIB512
4358 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4359 {
4360 i.error = invalid_vsib_address;
4361 return 1;
4362 }
4363
43234a1e
L		 4364 gas_assert (i.reg_operands == 2 || i.mask);
4365 if (i.reg_operands == 2 && !i.mask)
4366 {
4367 gas_assert (i.types[0].bitfield.regxmm
4368 || i.types[0].bitfield.regymm
4369 || i.types[0].bitfield.regzmm);
4370 gas_assert (i.types[2].bitfield.regxmm
4371 || i.types[2].bitfield.regymm
4372 || i.types[2].bitfield.regzmm);
4373 if (operand_check == check_none)
4374 return 0;
4375 if (register_number (i.op[0].regs)
4376 != register_number (i.index_reg)
4377 && register_number (i.op[2].regs)
4378 != register_number (i.index_reg)
4379 && register_number (i.op[0].regs)
4380 != register_number (i.op[2].regs))
4381 return 0;
4382 if (operand_check == check_error)
4383 {
4384 i.error = invalid_vector_register_set;
4385 return 1;
4386 }
4387 as_warn (_("mask, index, and destination registers should be distinct"));
4388 }
4389 }
7bab8ab5 4390
43234a1e
L		 4391 /* Check if broadcast is supported by the instruction and is applied
4392 to the memory operand. */
4393 if (i.broadcast)
4394 {
4395 int broadcasted_opnd_size;
4396
4397 /* Check if specified broadcast is supported in this instruction,
4398 and it's applied to memory operand of DWORD or QWORD type,
4399 depending on VecESize. */
4400 if (i.broadcast->type != t->opcode_modifier.broadcast
4401 || !i.types[i.broadcast->operand].bitfield.mem
4402 || (t->opcode_modifier.vecesize == 0
4403 && !i.types[i.broadcast->operand].bitfield.dword
4404 && !i.types[i.broadcast->operand].bitfield.unspecified)
4405 || (t->opcode_modifier.vecesize == 1
4406 && !i.types[i.broadcast->operand].bitfield.qword
4407 && !i.types[i.broadcast->operand].bitfield.unspecified))
4408 goto bad_broadcast;
4409
4410 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4411 if (i.broadcast->type == BROADCAST_1TO16)
4412 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4413 else if (i.broadcast->type == BROADCAST_1TO8)
4414 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
4415 else
4416 goto bad_broadcast;
4417
4418 if ((broadcasted_opnd_size == 256
4419 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4420 || (broadcasted_opnd_size == 512
4421 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4422 {
4423 bad_broadcast:
4424 i.error = unsupported_broadcast;
4425 return 1;
4426 }
4427 }
4428 /* If broadcast is supported in this instruction, we need to check if
4429 operand of one-element size isn't specified without broadcast. */
4430 else if (t->opcode_modifier.broadcast && i.mem_operands)
4431 {
4432 /* Find memory operand. */
4433 for (op = 0; op < i.operands; op++)
4434 if (operand_type_check (i.types[op], anymem))
4435 break;
4436 gas_assert (op < i.operands);
4437 /* Check size of the memory operand. */
4438 if ((t->opcode_modifier.vecesize == 0
4439 && i.types[op].bitfield.dword)
4440 || (t->opcode_modifier.vecesize == 1
4441 && i.types[op].bitfield.qword))
4442 {
4443 i.error = broadcast_needed;
4444 return 1;
4445 }
4446 }
4447
4448 /* Check if requested masking is supported. */
4449 if (i.mask
4450 && (!t->opcode_modifier.masking
4451 || (i.mask->zeroing
4452 && t->opcode_modifier.masking == MERGING_MASKING)))
4453 {
4454 i.error = unsupported_masking;
4455 return 1;
4456 }
4457
4458 /* Check if masking is applied to dest operand. */
4459 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4460 {
4461 i.error = mask_not_on_destination;
4462 return 1;
4463 }
4464
4465 /* Check if default mask is allowed. */
4466 if (t->opcode_modifier.nodefmask
4467 && (!i.mask || i.mask->mask->reg_num == 0))
4468 {
4469 i.error = no_default_mask;
4470 return 1;
4471 }
4472
4473 /* Check RC/SAE. */
4474 if (i.rounding)
4475 {
4476 if ((i.rounding->type != saeonly
4477 && !t->opcode_modifier.staticrounding)
4478 || (i.rounding->type == saeonly
4479 && (t->opcode_modifier.staticrounding
4480 || !t->opcode_modifier.sae)))
4481 {
4482 i.error = unsupported_rc_sae;
4483 return 1;
4484 }
4485 /* If the instruction has several immediate operands and one of
4486 them is rounding, the rounding operand should be the last
4487 immediate operand. */
4488 if (i.imm_operands > 1
4489 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4490 {
43234a1e 4491 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4492 return 1;
4493 }
6c30d220
L		 4494 }
4495
43234a1e
L		 4496 /* Check vector Disp8 operand. */
4497 if (t->opcode_modifier.disp8memshift)
4498 {
4499 if (i.broadcast)
4500 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4501 else
4502 i.memshift = t->opcode_modifier.disp8memshift;
4503
4504 for (op = 0; op < i.operands; op++)
4505 if (operand_type_check (i.types[op], disp)
4506 && i.op[op].disps->X_op == O_constant)
4507 {
4508 offsetT value = i.op[op].disps->X_add_number;
4509 int vec_disp8_ok = fits_in_vec_disp8 (value);
4510 if (t->operand_types [op].bitfield.vec_disp8)
4511 {
4512 if (vec_disp8_ok)
4513 i.types[op].bitfield.vec_disp8 = 1;
4514 else
4515 {
4516 /* Vector insn can only have Vec_Disp8/Disp32 in
4517 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4518 mode. */
4519 i.types[op].bitfield.disp8 = 0;
4520 if (flag_code != CODE_16BIT)
4521 i.types[op].bitfield.disp16 = 0;
4522 }
4523 }
4524 else if (flag_code != CODE_16BIT)
4525 {
4526 /* One form of this instruction supports vector Disp8.
4527 Try vector Disp8 if we need to use Disp32. */
4528 if (vec_disp8_ok && !fits_in_signed_byte (value))
4529 {
4530 i.error = try_vector_disp8;
4531 return 1;
4532 }
4533 }
4534 }
4535 }
4536 else
4537 i.memshift = -1;
4538
6c30d220
L		 4539 return 0;
4540}
4541
43f3e2ee 4542/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4543 operand types. */
4544
4545static int
4546VEX_check_operands (const insn_template *t)
4547{
43234a1e
L		 4548 /* VREX is only valid with EVEX prefix. */
4549 if (i.need_vrex && !t->opcode_modifier.evex)
4550 {
4551 i.error = invalid_register_operand;
4552 return 1;
4553 }
4554
a683cc34
SP		 4555 if (!t->opcode_modifier.vex)
4556 return 0;
4557
4558 /* Only check VEX_Imm4, which must be the first operand. */
4559 if (t->operand_types[0].bitfield.vec_imm4)
4560 {
4561 if (i.op[0].imms->X_op != O_constant
4562 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4563 {
a65babc9 4564 i.error = bad_imm4;
891edac4
L		 4565 return 1;
4566 }
a683cc34
SP		 4567
4568 /* Turn off Imm8 so that update_imm won't complain. */
4569 i.types[0] = vec_imm4;
4570 }
4571
4572 return 0;
4573}
4574
d3ce72d0 4575static const insn_template *
e3bb37b5 4576match_template (void)
29b0f896
AM		 4577{
4578 /* Points to template once we've found it. */
d3ce72d0 4579 const insn_template *t;
40fb9820 4580 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4581 i386_operand_type overlap4;
29b0f896 4582 unsigned int found_reverse_match;
40fb9820
L		 4583 i386_opcode_modifier suffix_check;
4584 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4585 int addr_prefix_disp;
a5c311ca 4586 unsigned int j;
3629bb00 4587 unsigned int found_cpu_match;
45664ddb 4588 unsigned int check_register;
5614d22c 4589 enum i386_error specific_error = 0;
29b0f896 4590
c0f3af97
L		 4591#if MAX_OPERANDS != 5
4592# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4593#endif
4594
29b0f896 4595 found_reverse_match = 0;
539e75ad 4596 addr_prefix_disp = -1;
40fb9820
L		 4597
4598 memset (&suffix_check, 0, sizeof (suffix_check));
4599 if (i.suffix == BYTE_MNEM_SUFFIX)
4600 suffix_check.no_bsuf = 1;
4601 else if (i.suffix == WORD_MNEM_SUFFIX)
4602 suffix_check.no_wsuf = 1;
4603 else if (i.suffix == SHORT_MNEM_SUFFIX)
4604 suffix_check.no_ssuf = 1;
4605 else if (i.suffix == LONG_MNEM_SUFFIX)
4606 suffix_check.no_lsuf = 1;
4607 else if (i.suffix == QWORD_MNEM_SUFFIX)
4608 suffix_check.no_qsuf = 1;
4609 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4610 suffix_check.no_ldsuf = 1;
29b0f896 4611
01559ecc
L		 4612 /* Must have right number of operands. */
4613 i.error = number_of_operands_mismatch;
4614
45aa61fe 4615 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4616 {
539e75ad
L		 4617 addr_prefix_disp = -1;
4618
29b0f896
AM		 4619 if (i.operands != t->operands)
4620 continue;
4621
50aecf8c 4622 /* Check processor support. */
a65babc9 4623 i.error = unsupported;
c0f3af97
L		 4624 found_cpu_match = (cpu_flags_match (t)
4625 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4626 if (!found_cpu_match)
4627 continue;
4628
e1d4d893 4629 /* Check old gcc support. */
a65babc9 4630 i.error = old_gcc_only;
e1d4d893
L		 4631 if (!old_gcc && t->opcode_modifier.oldgcc)
4632 continue;
4633
4634 /* Check AT&T mnemonic. */
a65babc9 4635 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4636 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4637 continue;
4638
891edac4 4639 /* Check AT&T/Intel syntax. */
a65babc9 4640 i.error = unsupported_syntax;
5c07affc
L		 4641 if ((intel_syntax && t->opcode_modifier.attsyntax)
4642 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4643 continue;
4644
20592a94 4645 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4646 i.error = invalid_instruction_suffix;
567e4e96
L		 4647 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4648 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4649 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4650 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4651 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4652 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4653 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4654 continue;
4655
5c07affc 4656 if (!operand_size_match (t))
7d5e4556 4657 continue;
539e75ad 4658
5c07affc
L		 4659 for (j = 0; j < MAX_OPERANDS; j++)
4660 operand_types[j] = t->operand_types[j];
4661
45aa61fe
AM		 4662 /* In general, don't allow 64-bit operands in 32-bit mode. */
4663 if (i.suffix == QWORD_MNEM_SUFFIX
4664 && flag_code != CODE_64BIT
4665 && (intel_syntax
40fb9820 4666 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4667 && !intel_float_operand (t->name))
4668 : intel_float_operand (t->name) != 2)
40fb9820 4669 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4670 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4671 && !operand_types[0].bitfield.regymm
4672 && !operand_types[0].bitfield.regzmm)
40fb9820 4673 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97 4674 && !!operand_types[t->operands > 1].bitfield.regxmm
43234a1e
L		 4675 && !!operand_types[t->operands > 1].bitfield.regymm
4676 && !!operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4677 && (t->base_opcode != 0x0fc7
4678 || t->extension_opcode != 1 /* cmpxchg8b */))
4679 continue;
4680
192dc9c6
JB		 4681 /* In general, don't allow 32-bit operands on pre-386. */
4682 else if (i.suffix == LONG_MNEM_SUFFIX
4683 && !cpu_arch_flags.bitfield.cpui386
4684 && (intel_syntax
4685 ? (!t->opcode_modifier.ignoresize
4686 && !intel_float_operand (t->name))
4687 : intel_float_operand (t->name) != 2)
4688 && ((!operand_types[0].bitfield.regmmx
4689 && !operand_types[0].bitfield.regxmm)
4690 || (!operand_types[t->operands > 1].bitfield.regmmx
4691 && !!operand_types[t->operands > 1].bitfield.regxmm)))
4692 continue;
4693
29b0f896 4694 /* Do not verify operands when there are none. */
50aecf8c 4695 else
29b0f896 4696 {
c6fb90c8 4697 if (!t->operands)
2dbab7d5
L		 4698 /* We've found a match; break out of loop. */
4699 break;
29b0f896 4700 }
252b5132 4701
539e75ad
L		 4702 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4703 into Disp32/Disp16/Disp32 operand. */
4704 if (i.prefix[ADDR_PREFIX] != 0)
4705 {
40fb9820 4706 /* There should be only one Disp operand. */
539e75ad
L		 4707 switch (flag_code)
4708 {
4709 case CODE_16BIT:
40fb9820
L		 4710 for (j = 0; j < MAX_OPERANDS; j++)
4711 {
4712 if (operand_types[j].bitfield.disp16)
4713 {
4714 addr_prefix_disp = j;
4715 operand_types[j].bitfield.disp32 = 1;
4716 operand_types[j].bitfield.disp16 = 0;
4717 break;
4718 }
4719 }
539e75ad
L		 4720 break;
4721 case CODE_32BIT:
40fb9820
L		 4722 for (j = 0; j < MAX_OPERANDS; j++)
4723 {
4724 if (operand_types[j].bitfield.disp32)
4725 {
4726 addr_prefix_disp = j;
4727 operand_types[j].bitfield.disp32 = 0;
4728 operand_types[j].bitfield.disp16 = 1;
4729 break;
4730 }
4731 }
539e75ad
L		 4732 break;
4733 case CODE_64BIT:
40fb9820
L		 4734 for (j = 0; j < MAX_OPERANDS; j++)
4735 {
4736 if (operand_types[j].bitfield.disp64)
4737 {
4738 addr_prefix_disp = j;
4739 operand_types[j].bitfield.disp64 = 0;
4740 operand_types[j].bitfield.disp32 = 1;
4741 break;
4742 }
4743 }
539e75ad
L		 4744 break;
4745 }
539e75ad
L		 4746 }
4747
56ffb741
L		 4748 /* We check register size if needed. */
4749 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4750 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4751 switch (t->operands)
4752 {
4753 case 1:
40fb9820 4754 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4755 continue;
4756 break;
4757 case 2:
8b38ad71
L		 4758 /* xchg %eax, %eax is a special case. It is an aliase for nop
4759 only in 32bit mode and we can use opcode 0x90. In 64bit
4760 mode, we can't use 0x90 for xchg %eax, %eax since it should
4761 zero-extend %eax to %rax. */
4762 if (flag_code == CODE_64BIT
4763 && t->base_opcode == 0x90
0dfbf9d7
L		 4764 && operand_type_equal (&i.types [0], &acc32)
4765 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4766 continue;
b6169b20
L		 4767 if (i.swap_operand)
4768 {
4769 /* If we swap operand in encoding, we either match
4770 the next one or reverse direction of operands. */
4771 if (t->opcode_modifier.s)
4772 continue;
4773 else if (t->opcode_modifier.d)
4774 goto check_reverse;
4775 }
4776
29b0f896 4777 case 3:
fa99fab2
L		 4778 /* If we swap operand in encoding, we match the next one. */
4779 if (i.swap_operand && t->opcode_modifier.s)
4780 continue;
f48ff2ae 4781 case 4:
c0f3af97 4782 case 5:
c6fb90c8 4783 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4784 if (!operand_type_match (overlap0, i.types[0])
4785 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4786 || (check_register
4787 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4788 operand_types[0],
4789 overlap1, i.types[1],
4790 operand_types[1])))
29b0f896
AM		 4791 {
4792 /* Check if other direction is valid ... */
40fb9820 4793 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4794 continue;
4795
b6169b20 4796check_reverse:
29b0f896 4797 /* Try reversing direction of operands. */
c6fb90c8
L		 4798 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4799 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4800 if (!operand_type_match (overlap0, i.types[0])
4801 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4802 || (check_register
4803 && !operand_type_register_match (overlap0,
4804 i.types[0],
4805 operand_types[1],
4806 overlap1,
4807 i.types[1],
4808 operand_types[0])))
29b0f896
AM		 4809 {
4810 /* Does not match either direction. */
4811 continue;
4812 }
4813 /* found_reverse_match holds which of D or FloatDR
4814 we've found. */
40fb9820 4815 if (t->opcode_modifier.d)
8a2ed489 4816 found_reverse_match = Opcode_D;
40fb9820 4817 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4818 found_reverse_match = Opcode_FloatD;
4819 else
4820 found_reverse_match = 0;
40fb9820 4821 if (t->opcode_modifier.floatr)
8a2ed489 4822 found_reverse_match |= Opcode_FloatR;
29b0f896 4823 }
f48ff2ae 4824 else
29b0f896 4825 {
f48ff2ae 4826 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4827 switch (t->operands)
4828 {
c0f3af97
L		 4829 case 5:
4830 overlap4 = operand_type_and (i.types[4],
4831 operand_types[4]);
d1cbb4db 4832 case 4:
c6fb90c8
L		 4833 overlap3 = operand_type_and (i.types[3],
4834 operand_types[3]);
d1cbb4db 4835 case 3:
c6fb90c8
L		 4836 overlap2 = operand_type_and (i.types[2],
4837 operand_types[2]);
d1cbb4db
L		 4838 break;
4839 }
29b0f896 4840
f48ff2ae
L		 4841 switch (t->operands)
4842 {
c0f3af97
L		 4843 case 5:
4844 if (!operand_type_match (overlap4, i.types[4])
4845 || !operand_type_register_match (overlap3,
4846 i.types[3],
4847 operand_types[3],
4848 overlap4,
4849 i.types[4],
4850 operand_types[4]))
4851 continue;
f48ff2ae 4852 case 4:
40fb9820 4853 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4854 || (check_register
4855 && !operand_type_register_match (overlap2,
4856 i.types[2],
4857 operand_types[2],
4858 overlap3,
4859 i.types[3],
4860 operand_types[3])))
f48ff2ae
L		 4861 continue;
4862 case 3:
4863 /* Here we make use of the fact that there are no
4864 reverse match 3 operand instructions, and all 3
4865 operand instructions only need to be checked for
4866 register consistency between operands 2 and 3. */
40fb9820 4867 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4868 || (check_register
4869 && !operand_type_register_match (overlap1,
4870 i.types[1],
4871 operand_types[1],
4872 overlap2,
4873 i.types[2],
4874 operand_types[2])))
f48ff2ae
L		 4875 continue;
4876 break;
4877 }
29b0f896 4878 }
f48ff2ae 4879 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4880 slip through to break. */
4881 }
3629bb00 4882 if (!found_cpu_match)
29b0f896
AM		 4883 {
4884 found_reverse_match = 0;
4885 continue;
4886 }
c0f3af97 4887
5614d22c
JB		 4888 /* Check if vector and VEX operands are valid. */
4889 if (check_VecOperands (t) || VEX_check_operands (t))
4890 {
4891 specific_error = i.error;
4892 continue;
4893 }
a683cc34 4894
29b0f896
AM		 4895 /* We've found a match; break out of loop. */
4896 break;
4897 }
4898
4899 if (t == current_templates->end)
4900 {
4901 /* We found no match. */
a65babc9 4902 const char *err_msg;
5614d22c 4903 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4904 {
4905 default:
4906 abort ();
86e026a4 4907 case operand_size_mismatch:
a65babc9
L		 4908 err_msg = _("operand size mismatch");
4909 break;
4910 case operand_type_mismatch:
4911 err_msg = _("operand type mismatch");
4912 break;
4913 case register_type_mismatch:
4914 err_msg = _("register type mismatch");
4915 break;
4916 case number_of_operands_mismatch:
4917 err_msg = _("number of operands mismatch");
4918 break;
4919 case invalid_instruction_suffix:
4920 err_msg = _("invalid instruction suffix");
4921 break;
4922 case bad_imm4:
4a2608e3 4923 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4924 break;
4925 case old_gcc_only:
4926 err_msg = _("only supported with old gcc");
4927 break;
4928 case unsupported_with_intel_mnemonic:
4929 err_msg = _("unsupported with Intel mnemonic");
4930 break;
4931 case unsupported_syntax:
4932 err_msg = _("unsupported syntax");
4933 break;
4934 case unsupported:
35262a23 4935 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4936 current_templates->start->name);
4937 return NULL;
6c30d220
L		 4938 case invalid_vsib_address:
4939 err_msg = _("invalid VSIB address");
4940 break;
7bab8ab5
JB		 4941 case invalid_vector_register_set:
4942 err_msg = _("mask, index, and destination registers must be distinct");
4943 break;
6c30d220
L		 4944 case unsupported_vector_index_register:
4945 err_msg = _("unsupported vector index register");
4946 break;
43234a1e
L		 4947 case unsupported_broadcast:
4948 err_msg = _("unsupported broadcast");
4949 break;
4950 case broadcast_not_on_src_operand:
4951 err_msg = _("broadcast not on source memory operand");
4952 break;
4953 case broadcast_needed:
4954 err_msg = _("broadcast is needed for operand of such type");
4955 break;
4956 case unsupported_masking:
4957 err_msg = _("unsupported masking");
4958 break;
4959 case mask_not_on_destination:
4960 err_msg = _("mask not on destination operand");
4961 break;
4962 case no_default_mask:
4963 err_msg = _("default mask isn't allowed");
4964 break;
4965 case unsupported_rc_sae:
4966 err_msg = _("unsupported static rounding/sae");
4967 break;
4968 case rc_sae_operand_not_last_imm:
4969 if (intel_syntax)
4970 err_msg = _("RC/SAE operand must precede immediate operands");
4971 else
4972 err_msg = _("RC/SAE operand must follow immediate operands");
4973 break;
4974 case invalid_register_operand:
4975 err_msg = _("invalid register operand");
4976 break;
a65babc9
L		 4977 }
4978 as_bad (_("%s for `%s'"), err_msg,
891edac4 4979 current_templates->start->name);
fa99fab2 4980 return NULL;
29b0f896 4981 }
252b5132 4982
29b0f896
AM		 4983 if (!quiet_warnings)
4984 {
4985 if (!intel_syntax
40fb9820
L		 4986 && (i.types[0].bitfield.jumpabsolute
4987 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4988 {
4989 as_warn (_("indirect %s without `*'"), t->name);
4990 }
4991
40fb9820
L		 4992 if (t->opcode_modifier.isprefix
4993 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4994 {
4995 /* Warn them that a data or address size prefix doesn't
4996 affect assembly of the next line of code. */
4997 as_warn (_("stand-alone `%s' prefix"), t->name);
4998 }
4999 }
5000
5001 /* Copy the template we found. */
5002 i.tm = *t;
539e75ad
L		 5003
5004 if (addr_prefix_disp != -1)
5005 i.tm.operand_types[addr_prefix_disp]
5006 = operand_types[addr_prefix_disp];
5007
29b0f896
AM		 5008 if (found_reverse_match)
5009 {
5010 /* If we found a reverse match we must alter the opcode
5011 direction bit. found_reverse_match holds bits to change
5012 (different for int & float insns). */
5013
5014 i.tm.base_opcode ^= found_reverse_match;
5015
539e75ad
L		 5016 i.tm.operand_types[0] = operand_types[1];
5017 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5018 }
5019
fa99fab2 5020 return t;
29b0f896
AM		 5021}
5022
5023static int
e3bb37b5 5024check_string (void)
29b0f896 5025{
40fb9820
L		 5026 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5027 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5028 {
5029 if (i.seg[0] != NULL && i.seg[0] != &es)
5030 {
a87af027 5031 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5032 i.tm.name,
a87af027
JB		 5033 mem_op + 1,
5034 register_prefix);
29b0f896
AM		 5035 return 0;
5036 }
5037 /* There's only ever one segment override allowed per instruction.
5038 This instruction possibly has a legal segment override on the
5039 second operand, so copy the segment to where non-string
5040 instructions store it, allowing common code. */
5041 i.seg[0] = i.seg[1];
5042 }
40fb9820 5043 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5044 {
5045 if (i.seg[1] != NULL && i.seg[1] != &es)
5046 {
a87af027 5047 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5048 i.tm.name,
a87af027
JB		 5049 mem_op + 2,
5050 register_prefix);
29b0f896
AM		 5051 return 0;
5052 }
5053 }
5054 return 1;
5055}
5056
5057static int
543613e9 5058process_suffix (void)
29b0f896
AM		 5059{
5060 /* If matched instruction specifies an explicit instruction mnemonic
5061 suffix, use it. */
40fb9820
L		 5062 if (i.tm.opcode_modifier.size16)
5063 i.suffix = WORD_MNEM_SUFFIX;
5064 else if (i.tm.opcode_modifier.size32)
5065 i.suffix = LONG_MNEM_SUFFIX;
5066 else if (i.tm.opcode_modifier.size64)
5067 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5068 else if (i.reg_operands)
5069 {
5070 /* If there's no instruction mnemonic suffix we try to invent one
5071 based on register operands. */
5072 if (!i.suffix)
5073 {
5074 /* We take i.suffix from the last register operand specified,
5075 Destination register type is more significant than source
381d071f
L		 5076 register type. crc32 in SSE4.2 prefers source register
5077 type. */
5078 if (i.tm.base_opcode == 0xf20f38f1)
5079 {
40fb9820
L		 5080 if (i.types[0].bitfield.reg16)
5081 i.suffix = WORD_MNEM_SUFFIX;
5082 else if (i.types[0].bitfield.reg32)
5083 i.suffix = LONG_MNEM_SUFFIX;
5084 else if (i.types[0].bitfield.reg64)
5085 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5086 }
9344ff29 5087 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5088 {
40fb9820 5089 if (i.types[0].bitfield.reg8)
20592a94
L		 5090 i.suffix = BYTE_MNEM_SUFFIX;
5091 }
381d071f
L		 5092
5093 if (!i.suffix)
5094 {
5095 int op;
5096
20592a94
L		 5097 if (i.tm.base_opcode == 0xf20f38f1
5098 || i.tm.base_opcode == 0xf20f38f0)
5099 {
5100 /* We have to know the operand size for crc32. */
5101 as_bad (_("ambiguous memory operand size for `%s`"),
5102 i.tm.name);
5103 return 0;
5104 }
5105
381d071f 5106 for (op = i.operands; --op >= 0;)
40fb9820 5107 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5108 {
40fb9820
L		 5109 if (i.types[op].bitfield.reg8)
5110 {
5111 i.suffix = BYTE_MNEM_SUFFIX;
5112 break;
5113 }
5114 else if (i.types[op].bitfield.reg16)
5115 {
5116 i.suffix = WORD_MNEM_SUFFIX;
5117 break;
5118 }
5119 else if (i.types[op].bitfield.reg32)
5120 {
5121 i.suffix = LONG_MNEM_SUFFIX;
5122 break;
5123 }
5124 else if (i.types[op].bitfield.reg64)
5125 {
5126 i.suffix = QWORD_MNEM_SUFFIX;
5127 break;
5128 }
381d071f
L		 5129 }
5130 }
29b0f896
AM		 5131 }
5132 else if (i.suffix == BYTE_MNEM_SUFFIX)
5133 {
2eb952a4
L		 5134 if (intel_syntax
5135 && i.tm.opcode_modifier.ignoresize
5136 && i.tm.opcode_modifier.no_bsuf)
5137 i.suffix = 0;
5138 else if (!check_byte_reg ())
29b0f896
AM		 5139 return 0;
5140 }
5141 else if (i.suffix == LONG_MNEM_SUFFIX)
5142 {
2eb952a4
L		 5143 if (intel_syntax
5144 && i.tm.opcode_modifier.ignoresize
5145 && i.tm.opcode_modifier.no_lsuf)
5146 i.suffix = 0;
5147 else if (!check_long_reg ())
29b0f896
AM		 5148 return 0;
5149 }
5150 else if (i.suffix == QWORD_MNEM_SUFFIX)
5151 {
955e1e6a
L		 5152 if (intel_syntax
5153 && i.tm.opcode_modifier.ignoresize
5154 && i.tm.opcode_modifier.no_qsuf)
5155 i.suffix = 0;
5156 else if (!check_qword_reg ())
29b0f896
AM		 5157 return 0;
5158 }
5159 else if (i.suffix == WORD_MNEM_SUFFIX)
5160 {
2eb952a4
L		 5161 if (intel_syntax
5162 && i.tm.opcode_modifier.ignoresize
5163 && i.tm.opcode_modifier.no_wsuf)
5164 i.suffix = 0;
5165 else if (!check_word_reg ())
29b0f896
AM		 5166 return 0;
5167 }
c0f3af97 5168 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5169 || i.suffix == YMMWORD_MNEM_SUFFIX
5170 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5171 {
43234a1e 5172 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5173 should check if it is a valid suffix. */
5174 }
40fb9820 5175 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5176 /* Do nothing if the instruction is going to ignore the prefix. */
5177 ;
5178 else
5179 abort ();
5180 }
40fb9820 5181 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5182 && !i.suffix
5183 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5184 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5185 {
5186 i.suffix = stackop_size;
5187 }
9306ca4a
JB		 5188 else if (intel_syntax
5189 && !i.suffix
40fb9820
L		 5190 && (i.tm.operand_types[0].bitfield.jumpabsolute
5191 || i.tm.opcode_modifier.jumpbyte
5192 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5193 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5194 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5195 {
5196 switch (flag_code)
5197 {
5198 case CODE_64BIT:
40fb9820 5199 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5200 {
5201 i.suffix = QWORD_MNEM_SUFFIX;
5202 break;
5203 }
5204 case CODE_32BIT:
40fb9820 5205 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5206 i.suffix = LONG_MNEM_SUFFIX;
5207 break;
5208 case CODE_16BIT:
40fb9820 5209 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5210 i.suffix = WORD_MNEM_SUFFIX;
5211 break;
5212 }
5213 }
252b5132 5214
9306ca4a 5215 if (!i.suffix)
29b0f896 5216 {
9306ca4a
JB		 5217 if (!intel_syntax)
5218 {
40fb9820 5219 if (i.tm.opcode_modifier.w)
9306ca4a 5220 {
4eed87de
AM		 5221 as_bad (_("no instruction mnemonic suffix given and "
5222 "no register operands; can't size instruction"));
9306ca4a
JB		 5223 return 0;
5224 }
5225 }
5226 else
5227 {
40fb9820 5228 unsigned int suffixes;
7ab9ffdd 5229
40fb9820
L		 5230 suffixes = !i.tm.opcode_modifier.no_bsuf;
5231 if (!i.tm.opcode_modifier.no_wsuf)
5232 suffixes |= 1 << 1;
5233 if (!i.tm.opcode_modifier.no_lsuf)
5234 suffixes |= 1 << 2;
fc4adea1 5235 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5236 suffixes |= 1 << 3;
5237 if (!i.tm.opcode_modifier.no_ssuf)
5238 suffixes |= 1 << 4;
5239 if (!i.tm.opcode_modifier.no_qsuf)
5240 suffixes |= 1 << 5;
5241
5242 /* There are more than suffix matches. */
5243 if (i.tm.opcode_modifier.w
9306ca4a 5244 || ((suffixes & (suffixes - 1))
40fb9820
L		 5245 && !i.tm.opcode_modifier.defaultsize
5246 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5247 {
5248 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5249 return 0;
5250 }
5251 }
29b0f896 5252 }
252b5132 5253
9306ca4a
JB		 5254 /* Change the opcode based on the operand size given by i.suffix;
5255 We don't need to change things for byte insns. */
5256
582d5edd
L		 5257 if (i.suffix
5258 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5259 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5260 && i.suffix != YMMWORD_MNEM_SUFFIX
5261 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5262 {
5263 /* It's not a byte, select word/dword operation. */
40fb9820 5264 if (i.tm.opcode_modifier.w)
29b0f896 5265 {
40fb9820 5266 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5267 i.tm.base_opcode |= 8;
5268 else
5269 i.tm.base_opcode |= 1;
5270 }
0f3f3d8b 5271
29b0f896
AM		 5272 /* Now select between word & dword operations via the operand
5273 size prefix, except for instructions that will ignore this
5274 prefix anyway. */
ca61edf2 5275 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5276 {
ca61edf2
L		 5277 /* The address size override prefix changes the size of the
5278 first operand. */
40fb9820
L		 5279 if ((flag_code == CODE_32BIT
5280 && i.op->regs[0].reg_type.bitfield.reg16)
5281 || (flag_code != CODE_32BIT
5282 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5283 if (!add_prefix (ADDR_PREFIX_OPCODE))
5284 return 0;
5285 }
5286 else if (i.suffix != QWORD_MNEM_SUFFIX
5287 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5288 && !i.tm.opcode_modifier.ignoresize
5289 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5290 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5291 || (flag_code == CODE_64BIT
40fb9820 5292 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5293 {
5294 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5295
40fb9820 5296 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5297 prefix = ADDR_PREFIX_OPCODE;
252b5132 5298
29b0f896
AM		 5299 if (!add_prefix (prefix))
5300 return 0;
24eab124 5301 }
252b5132 5302
29b0f896
AM		 5303 /* Set mode64 for an operand. */
5304 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5305 && flag_code == CODE_64BIT
40fb9820 5306 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5307 {
5308 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5309 need rex64. cmpxchg8b is also a special case. */
5310 if (! (i.operands == 2
5311 && i.tm.base_opcode == 0x90
5312 && i.tm.extension_opcode == None
0dfbf9d7
L		 5313 && operand_type_equal (&i.types [0], &acc64)
5314 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5315 && ! (i.operands == 1
5316 && i.tm.base_opcode == 0xfc7
5317 && i.tm.extension_opcode == 1
40fb9820
L		 5318 && !operand_type_check (i.types [0], reg)
5319 && operand_type_check (i.types [0], anymem)))
f6bee062 5320 i.rex |= REX_W;
46e883c5 5321 }
3e73aa7c 5322
29b0f896
AM		 5323 /* Size floating point instruction. */
5324 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5325 if (i.tm.opcode_modifier.floatmf)
543613e9 5326 i.tm.base_opcode ^= 4;
29b0f896 5327 }
7ecd2f8b 5328
29b0f896
AM		 5329 return 1;
5330}
3e73aa7c 5331
29b0f896 5332static int
543613e9 5333check_byte_reg (void)
29b0f896
AM		 5334{
5335 int op;
543613e9 5336
29b0f896
AM		 5337 for (op = i.operands; --op >= 0;)
5338 {
5339 /* If this is an eight bit register, it's OK. If it's the 16 or
5340 32 bit version of an eight bit register, we will just use the
5341 low portion, and that's OK too. */
40fb9820 5342 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5343 continue;
5344
5a819eb9
JB		 5345 /* I/O port address operands are OK too. */
5346 if (i.tm.operand_types[op].bitfield.inoutportreg)
5347 continue;
5348
9344ff29
L		 5349 /* crc32 doesn't generate this warning. */
5350 if (i.tm.base_opcode == 0xf20f38f0)
5351 continue;
5352
40fb9820
L		 5353 if ((i.types[op].bitfield.reg16
5354 || i.types[op].bitfield.reg32
5355 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5356 && i.op[op].regs->reg_num < 4
5357 /* Prohibit these changes in 64bit mode, since the lowering
5358 would be more complicated. */
5359 && flag_code != CODE_64BIT)
29b0f896 5360 {
29b0f896 5361#if REGISTER_WARNINGS
5a819eb9 5362 if (!quiet_warnings)
a540244d
L		 5363 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5364 register_prefix,
40fb9820 5365 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5366 ? REGNAM_AL - REGNAM_AX
5367 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5368 register_prefix,
29b0f896
AM		 5369 i.op[op].regs->reg_name,
5370 i.suffix);
5371#endif
5372 continue;
5373 }
5374 /* Any other register is bad. */
40fb9820
L		 5375 if (i.types[op].bitfield.reg16
5376 || i.types[op].bitfield.reg32
5377 || i.types[op].bitfield.reg64
5378 || i.types[op].bitfield.regmmx
5379 || i.types[op].bitfield.regxmm
c0f3af97 5380 || i.types[op].bitfield.regymm
43234a1e 5381 || i.types[op].bitfield.regzmm
40fb9820
L		 5382 || i.types[op].bitfield.sreg2
5383 || i.types[op].bitfield.sreg3
5384 || i.types[op].bitfield.control
5385 || i.types[op].bitfield.debug
5386 || i.types[op].bitfield.test
5387 || i.types[op].bitfield.floatreg
5388 || i.types[op].bitfield.floatacc)
29b0f896 5389 {
a540244d
L		 5390 as_bad (_("`%s%s' not allowed with `%s%c'"),
5391 register_prefix,
29b0f896
AM		 5392 i.op[op].regs->reg_name,
5393 i.tm.name,
5394 i.suffix);
5395 return 0;
5396 }
5397 }
5398 return 1;
5399}
5400
5401static int
e3bb37b5 5402check_long_reg (void)
29b0f896
AM		 5403{
5404 int op;
5405
5406 for (op = i.operands; --op >= 0;)
5407 /* Reject eight bit registers, except where the template requires
5408 them. (eg. movzb) */
40fb9820
L		 5409 if (i.types[op].bitfield.reg8
5410 && (i.tm.operand_types[op].bitfield.reg16
5411 || i.tm.operand_types[op].bitfield.reg32
5412 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5413 {
a540244d
L		 5414 as_bad (_("`%s%s' not allowed with `%s%c'"),
5415 register_prefix,
29b0f896
AM		 5416 i.op[op].regs->reg_name,
5417 i.tm.name,
5418 i.suffix);
5419 return 0;
5420 }
5421 /* Warn if the e prefix on a general reg is missing. */
5422 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5423 && i.types[op].bitfield.reg16
5424 && (i.tm.operand_types[op].bitfield.reg32
5425 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5426 {
5427 /* Prohibit these changes in the 64bit mode, since the
5428 lowering is more complicated. */
5429 if (flag_code == CODE_64BIT)
252b5132 5430 {
2b5d6a91 5431 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5432 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5433 i.suffix);
5434 return 0;
252b5132 5435 }
29b0f896 5436#if REGISTER_WARNINGS
cecf1424
JB		 5437 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5438 register_prefix,
5439 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5440 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5441#endif
252b5132 5442 }
29b0f896 5443 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5444 else if (i.types[op].bitfield.reg64
5445 && (i.tm.operand_types[op].bitfield.reg32
5446 || i.tm.operand_types[op].bitfield.acc))
252b5132 5447 {
34828aad 5448 if (intel_syntax
ca61edf2 5449 && i.tm.opcode_modifier.toqword
40fb9820 5450 && !i.types[0].bitfield.regxmm)
34828aad 5451 {
ca61edf2 5452 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5453 i.suffix = QWORD_MNEM_SUFFIX;
5454 }
5455 else
5456 {
2b5d6a91 5457 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5458 register_prefix, i.op[op].regs->reg_name,
5459 i.suffix);
5460 return 0;
5461 }
29b0f896
AM		 5462 }
5463 return 1;
5464}
252b5132 5465
29b0f896 5466static int
e3bb37b5 5467check_qword_reg (void)
29b0f896
AM		 5468{
5469 int op;
252b5132 5470
29b0f896
AM		 5471 for (op = i.operands; --op >= 0; )
5472 /* Reject eight bit registers, except where the template requires
5473 them. (eg. movzb) */
40fb9820
L		 5474 if (i.types[op].bitfield.reg8
5475 && (i.tm.operand_types[op].bitfield.reg16
5476 || i.tm.operand_types[op].bitfield.reg32
5477 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5478 {
a540244d
L		 5479 as_bad (_("`%s%s' not allowed with `%s%c'"),
5480 register_prefix,
29b0f896
AM		 5481 i.op[op].regs->reg_name,
5482 i.tm.name,
5483 i.suffix);
5484 return 0;
5485 }
5486 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 5487 else if ((i.types[op].bitfield.reg16
5488 || i.types[op].bitfield.reg32)
5489 && (i.tm.operand_types[op].bitfield.reg32
5490 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5491 {
5492 /* Prohibit these changes in the 64bit mode, since the
5493 lowering is more complicated. */
34828aad 5494 if (intel_syntax
ca61edf2 5495 && i.tm.opcode_modifier.todword
40fb9820 5496 && !i.types[0].bitfield.regxmm)
34828aad 5497 {
ca61edf2 5498 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5499 i.suffix = LONG_MNEM_SUFFIX;
5500 }
5501 else
5502 {
2b5d6a91 5503 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5504 register_prefix, i.op[op].regs->reg_name,
5505 i.suffix);
5506 return 0;
5507 }
252b5132 5508 }
29b0f896
AM		 5509 return 1;
5510}
252b5132 5511
29b0f896 5512static int
e3bb37b5 5513check_word_reg (void)
29b0f896
AM		 5514{
5515 int op;
5516 for (op = i.operands; --op >= 0;)
5517 /* Reject eight bit registers, except where the template requires
5518 them. (eg. movzb) */
40fb9820
L		 5519 if (i.types[op].bitfield.reg8
5520 && (i.tm.operand_types[op].bitfield.reg16
5521 || i.tm.operand_types[op].bitfield.reg32
5522 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5523 {
a540244d
L		 5524 as_bad (_("`%s%s' not allowed with `%s%c'"),
5525 register_prefix,
29b0f896
AM		 5526 i.op[op].regs->reg_name,
5527 i.tm.name,
5528 i.suffix);
5529 return 0;
5530 }
5531 /* Warn if the e prefix on a general reg is present. */
5532 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5533 && i.types[op].bitfield.reg32
5534 && (i.tm.operand_types[op].bitfield.reg16
5535 || i.tm.operand_types[op].bitfield.acc))
252b5132 5536 {
29b0f896
AM		 5537 /* Prohibit these changes in the 64bit mode, since the
5538 lowering is more complicated. */
5539 if (flag_code == CODE_64BIT)
252b5132 5540 {
2b5d6a91 5541 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5542 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5543 i.suffix);
5544 return 0;
252b5132 5545 }
29b0f896 5546#if REGISTER_WARNINGS
cecf1424
JB		 5547 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5548 register_prefix,
5549 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5550 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5551#endif
5552 }
5553 return 1;
5554}
252b5132 5555
29b0f896 5556static int
40fb9820 5557update_imm (unsigned int j)
29b0f896 5558{
bc0844ae 5559 i386_operand_type overlap = i.types[j];
40fb9820
L		 5560 if ((overlap.bitfield.imm8
5561 || overlap.bitfield.imm8s
5562 || overlap.bitfield.imm16
5563 || overlap.bitfield.imm32
5564 || overlap.bitfield.imm32s
5565 || overlap.bitfield.imm64)
0dfbf9d7
L		 5566 && !operand_type_equal (&overlap, &imm8)
5567 && !operand_type_equal (&overlap, &imm8s)
5568 && !operand_type_equal (&overlap, &imm16)
5569 && !operand_type_equal (&overlap, &imm32)
5570 && !operand_type_equal (&overlap, &imm32s)
5571 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5572 {
5573 if (i.suffix)
5574 {
40fb9820
L		 5575 i386_operand_type temp;
5576
0dfbf9d7 5577 operand_type_set (&temp, 0);
7ab9ffdd 5578 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5579 {
5580 temp.bitfield.imm8 = overlap.bitfield.imm8;
5581 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5582 }
5583 else if (i.suffix == WORD_MNEM_SUFFIX)
5584 temp.bitfield.imm16 = overlap.bitfield.imm16;
5585 else if (i.suffix == QWORD_MNEM_SUFFIX)
5586 {
5587 temp.bitfield.imm64 = overlap.bitfield.imm64;
5588 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5589 }
5590 else
5591 temp.bitfield.imm32 = overlap.bitfield.imm32;
5592 overlap = temp;
29b0f896 5593 }
0dfbf9d7
L		 5594 else if (operand_type_equal (&overlap, &imm16_32_32s)
5595 || operand_type_equal (&overlap, &imm16_32)
5596 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5597 {
40fb9820 5598 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5599 overlap = imm16;
40fb9820 5600 else
65da13b5 5601 overlap = imm32s;
29b0f896 5602 }
0dfbf9d7
L		 5603 if (!operand_type_equal (&overlap, &imm8)
5604 && !operand_type_equal (&overlap, &imm8s)
5605 && !operand_type_equal (&overlap, &imm16)
5606 && !operand_type_equal (&overlap, &imm32)
5607 && !operand_type_equal (&overlap, &imm32s)
5608 && !operand_type_equal (&overlap, &imm64))
29b0f896 5609 {
4eed87de
AM		 5610 as_bad (_("no instruction mnemonic suffix given; "
5611 "can't determine immediate size"));
29b0f896
AM		 5612 return 0;
5613 }
5614 }
40fb9820 5615 i.types[j] = overlap;
29b0f896 5616
40fb9820
L		 5617 return 1;
5618}
5619
5620static int
5621finalize_imm (void)
5622{
bc0844ae 5623 unsigned int j, n;
29b0f896 5624
bc0844ae
L		 5625 /* Update the first 2 immediate operands. */
5626 n = i.operands > 2 ? 2 : i.operands;
5627 if (n)
5628 {
5629 for (j = 0; j < n; j++)
5630 if (update_imm (j) == 0)
5631 return 0;
40fb9820 5632
bc0844ae
L		 5633 /* The 3rd operand can't be immediate operand. */
5634 gas_assert (operand_type_check (i.types[2], imm) == 0);
5635 }
29b0f896
AM		 5636
5637 return 1;
5638}
5639
c0f3af97
L		 5640static int
5641bad_implicit_operand (int xmm)
5642{
91d6fa6a
NC		 5643 const char *ireg = xmm ? "xmm0" : "ymm0";
5644
c0f3af97
L		 5645 if (intel_syntax)
5646 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5647 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5648 else
5649 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5650 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5651 return 0;
5652}
5653
29b0f896 5654static int
e3bb37b5 5655process_operands (void)
29b0f896
AM		 5656{
5657 /* Default segment register this instruction will use for memory
5658 accesses. 0 means unknown. This is only for optimizing out
5659 unnecessary segment overrides. */
5660 const seg_entry *default_seg = 0;
5661
2426c15f 5662 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5663 {
91d6fa6a
NC		 5664 unsigned int dupl = i.operands;
5665 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5666 unsigned int j;
5667
c0f3af97 5668 /* The destination must be an xmm register. */
9c2799c2 5669 gas_assert (i.reg_operands
91d6fa6a 5670 && MAX_OPERANDS > dupl
7ab9ffdd 5671 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5672
5673 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5674 {
c0f3af97 5675 /* The first operand is implicit and must be xmm0. */
9c2799c2 5676 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5677 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5678 return bad_implicit_operand (1);
5679
8cd7925b 5680 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5681 {
5682 /* Keep xmm0 for instructions with VEX prefix and 3
5683 sources. */
5684 goto duplicate;
5685 }
e2ec9d29 5686 else
c0f3af97
L		 5687 {
5688 /* We remove the first xmm0 and keep the number of
5689 operands unchanged, which in fact duplicates the
5690 destination. */
5691 for (j = 1; j < i.operands; j++)
5692 {
5693 i.op[j - 1] = i.op[j];
5694 i.types[j - 1] = i.types[j];
5695 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5696 }
5697 }
5698 }
5699 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5700 {
91d6fa6a 5701 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5702 && (i.tm.opcode_modifier.vexsources
5703 == VEX3SOURCES));
c0f3af97
L		 5704
5705 /* Add the implicit xmm0 for instructions with VEX prefix
5706 and 3 sources. */
5707 for (j = i.operands; j > 0; j--)
5708 {
5709 i.op[j] = i.op[j - 1];
5710 i.types[j] = i.types[j - 1];
5711 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5712 }
5713 i.op[0].regs
5714 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5715 i.types[0] = regxmm;
c0f3af97
L		 5716 i.tm.operand_types[0] = regxmm;
5717
5718 i.operands += 2;
5719 i.reg_operands += 2;
5720 i.tm.operands += 2;
5721
91d6fa6a 5722 dupl++;
c0f3af97 5723 dest++;
91d6fa6a
NC		 5724 i.op[dupl] = i.op[dest];
5725 i.types[dupl] = i.types[dest];
5726 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5727 }
c0f3af97
L		 5728 else
5729 {
5730duplicate:
5731 i.operands++;
5732 i.reg_operands++;
5733 i.tm.operands++;
5734
91d6fa6a
NC		 5735 i.op[dupl] = i.op[dest];
5736 i.types[dupl] = i.types[dest];
5737 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5738 }
5739
5740 if (i.tm.opcode_modifier.immext)
5741 process_immext ();
5742 }
5743 else if (i.tm.opcode_modifier.firstxmm0)
5744 {
5745 unsigned int j;
5746
43234a1e 5747 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5748 gas_assert (i.reg_operands
7ab9ffdd 5749 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5750 || operand_type_equal (&i.types[0], &regymm)
5751 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5752 if (register_number (i.op[0].regs) != 0)
c0f3af97 5753 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5754
5755 for (j = 1; j < i.operands; j++)
5756 {
5757 i.op[j - 1] = i.op[j];
5758 i.types[j - 1] = i.types[j];
5759
5760 /* We need to adjust fields in i.tm since they are used by
5761 build_modrm_byte. */
5762 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5763 }
5764
e2ec9d29
L		 5765 i.operands--;
5766 i.reg_operands--;
e2ec9d29
L		 5767 i.tm.operands--;
5768 }
5769 else if (i.tm.opcode_modifier.regkludge)
5770 {
5771 /* The imul $imm, %reg instruction is converted into
5772 imul $imm, %reg, %reg, and the clr %reg instruction
5773 is converted into xor %reg, %reg. */
5774
5775 unsigned int first_reg_op;
5776
5777 if (operand_type_check (i.types[0], reg))
5778 first_reg_op = 0;
5779 else
5780 first_reg_op = 1;
5781 /* Pretend we saw the extra register operand. */
9c2799c2 5782 gas_assert (i.reg_operands == 1
7ab9ffdd 5783 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5784 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5785 i.types[first_reg_op + 1] = i.types[first_reg_op];
5786 i.operands++;
5787 i.reg_operands++;
29b0f896
AM		 5788 }
5789
40fb9820 5790 if (i.tm.opcode_modifier.shortform)
29b0f896 5791 {
40fb9820
L		 5792 if (i.types[0].bitfield.sreg2
5793 || i.types[0].bitfield.sreg3)
29b0f896 5794 {
4eed87de
AM		 5795 if (i.tm.base_opcode == POP_SEG_SHORT
5796 && i.op[0].regs->reg_num == 1)
29b0f896 5797 {
a87af027 5798 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5799 return 0;
29b0f896 5800 }
4eed87de
AM		 5801 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5802 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5803 i.rex |= REX_B;
4eed87de
AM		 5804 }
5805 else
5806 {
7ab9ffdd 5807 /* The register or float register operand is in operand
85f10a01 5808 0 or 1. */
40fb9820 5809 unsigned int op;
7ab9ffdd
L		 5810
5811 if (i.types[0].bitfield.floatreg
5812 || operand_type_check (i.types[0], reg))
5813 op = 0;
5814 else
5815 op = 1;
4eed87de
AM		 5816 /* Register goes in low 3 bits of opcode. */
5817 i.tm.base_opcode |= i.op[op].regs->reg_num;
5818 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5819 i.rex |= REX_B;
40fb9820 5820 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5821 {
4eed87de
AM		 5822 /* Warn about some common errors, but press on regardless.
5823 The first case can be generated by gcc (<= 2.8.1). */
5824 if (i.operands == 2)
5825 {
5826 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5827 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5828 register_prefix, i.op[!intel_syntax].regs->reg_name,
5829 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5830 }
5831 else
5832 {
5833 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5834 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5835 register_prefix, i.op[0].regs->reg_name);
4eed87de 5836 }
29b0f896
AM		 5837 }
5838 }
5839 }
40fb9820 5840 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5841 {
5842 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5843 must be put into the modrm byte). Now, we make the modrm and
5844 index base bytes based on all the info we've collected. */
29b0f896
AM		 5845
5846 default_seg = build_modrm_byte ();
5847 }
8a2ed489 5848 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5849 {
5850 default_seg = &ds;
5851 }
40fb9820 5852 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5853 {
5854 /* For the string instructions that allow a segment override
5855 on one of their operands, the default segment is ds. */
5856 default_seg = &ds;
5857 }
5858
75178d9d
L		 5859 if (i.tm.base_opcode == 0x8d /* lea */
5860 && i.seg[0]
5861 && !quiet_warnings)
30123838 5862 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5863
5864 /* If a segment was explicitly specified, and the specified segment
5865 is not the default, use an opcode prefix to select it. If we
5866 never figured out what the default segment is, then default_seg
5867 will be zero at this point, and the specified segment prefix will
5868 always be used. */
29b0f896
AM		 5869 if ((i.seg[0]) && (i.seg[0] != default_seg))
5870 {
5871 if (!add_prefix (i.seg[0]->seg_prefix))
5872 return 0;
5873 }
5874 return 1;
5875}
5876
5877static const seg_entry *
e3bb37b5 5878build_modrm_byte (void)
29b0f896
AM		 5879{
5880 const seg_entry *default_seg = 0;
c0f3af97 5881 unsigned int source, dest;
8cd7925b 5882 int vex_3_sources;
c0f3af97
L		 5883
5884 /* The first operand of instructions with VEX prefix and 3 sources
5885 must be VEX_Imm4. */
8cd7925b 5886 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5887 if (vex_3_sources)
5888 {
91d6fa6a 5889 unsigned int nds, reg_slot;
4c2c6516 5890 expressionS *exp;
c0f3af97 5891
922d8de8 5892 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5893 && i.tm.opcode_modifier.immext)
5894 {
5895 dest = i.operands - 2;
5896 gas_assert (dest == 3);
5897 }
922d8de8 5898 else
a683cc34 5899 dest = i.operands - 1;
c0f3af97 5900 nds = dest - 1;
922d8de8 5901
a683cc34
SP		 5902 /* There are 2 kinds of instructions:
5903 1. 5 operands: 4 register operands or 3 register operands
5904 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5905 VexW0 or VexW1. The destination must be either XMM, YMM or
5906 ZMM register.
a683cc34
SP		 5907 2. 4 operands: 4 register operands or 3 register operands
5908 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5909 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5910 || (i.reg_operands == 3 && i.mem_operands == 1))
5911 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5912 && (i.tm.opcode_modifier.veximmext
5913 || (i.imm_operands == 1
5914 && i.types[0].bitfield.vec_imm4
5915 && (i.tm.opcode_modifier.vexw == VEXW0
5916 || i.tm.opcode_modifier.vexw == VEXW1)
5917 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5918 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5919 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5920
5921 if (i.imm_operands == 0)
5922 {
5923 /* When there is no immediate operand, generate an 8bit
5924 immediate operand to encode the first operand. */
5925 exp = &im_expressions[i.imm_operands++];
5926 i.op[i.operands].imms = exp;
5927 i.types[i.operands] = imm8;
5928 i.operands++;
5929 /* If VexW1 is set, the first operand is the source and
5930 the second operand is encoded in the immediate operand. */
5931 if (i.tm.opcode_modifier.vexw == VEXW1)
5932 {
5933 source = 0;
5934 reg_slot = 1;
5935 }
5936 else
5937 {
5938 source = 1;
5939 reg_slot = 0;
5940 }
5941
5942 /* FMA swaps REG and NDS. */
5943 if (i.tm.cpu_flags.bitfield.cpufma)
5944 {
5945 unsigned int tmp;
5946 tmp = reg_slot;
5947 reg_slot = nds;
5948 nds = tmp;
5949 }
5950
24981e7b
L		 5951 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5952 &regxmm)
a683cc34 5953 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 5954 &regymm)
5955 || operand_type_equal (&i.tm.operand_types[reg_slot],
5956 &regzmm));
a683cc34 5957 exp->X_op = O_constant;
4c692bc7 5958 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 5959 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
5960 }
922d8de8 5961 else
a683cc34
SP		 5962 {
5963 unsigned int imm_slot;
5964
5965 if (i.tm.opcode_modifier.vexw == VEXW0)
5966 {
5967 /* If VexW0 is set, the third operand is the source and
5968 the second operand is encoded in the immediate
5969 operand. */
5970 source = 2;
5971 reg_slot = 1;
5972 }
5973 else
5974 {
5975 /* VexW1 is set, the second operand is the source and
5976 the third operand is encoded in the immediate
5977 operand. */
5978 source = 1;
5979 reg_slot = 2;
5980 }
5981
5982 if (i.tm.opcode_modifier.immext)
5983 {
5984 /* When ImmExt is set, the immdiate byte is the last
5985 operand. */
5986 imm_slot = i.operands - 1;
5987 source--;
5988 reg_slot--;
5989 }
5990 else
5991 {
5992 imm_slot = 0;
5993
5994 /* Turn on Imm8 so that output_imm will generate it. */
5995 i.types[imm_slot].bitfield.imm8 = 1;
5996 }
5997
24981e7b
L		 5998 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5999 &regxmm)
6000 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6001 &regymm)
6002 || operand_type_equal (&i.tm.operand_types[reg_slot],
6003 &regzmm));
a683cc34 6004 i.op[imm_slot].imms->X_add_number
4c692bc7 6005 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6006 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6007 }
6008
6009 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6010 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6011 &regymm)
6012 || operand_type_equal (&i.tm.operand_types[nds],
6013 &regzmm));
dae39acc 6014 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6015 }
6016 else
6017 source = dest = 0;
29b0f896
AM		 6018
6019 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6020 implicit registers do not count. If there are 3 register
6021 operands, it must be a instruction with VexNDS. For a
6022 instruction with VexNDD, the destination register is encoded
6023 in VEX prefix. If there are 4 register operands, it must be
6024 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6025 if (i.mem_operands == 0
6026 && ((i.reg_operands == 2
2426c15f 6027 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6028 || (i.reg_operands == 3
2426c15f 6029 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6030 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6031 {
cab737b9
L		 6032 switch (i.operands)
6033 {
6034 case 2:
6035 source = 0;
6036 break;
6037 case 3:
c81128dc
L		 6038 /* When there are 3 operands, one of them may be immediate,
6039 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6040 the first operand must be shift count register (cl) or it
6041 is an instruction with VexNDS. */
9c2799c2 6042 gas_assert (i.imm_operands == 1
7ab9ffdd 6043 || (i.imm_operands == 0
2426c15f 6044 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6045 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6046 if (operand_type_check (i.types[0], imm)
6047 || i.types[0].bitfield.shiftcount)
6048 source = 1;
6049 else
6050 source = 0;
cab737b9
L		 6051 break;
6052 case 4:
368d64cc
L		 6053 /* When there are 4 operands, the first two must be 8bit
6054 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6055 one.
6056
6057 For instructions with VexNDS, if the first operand
6058 an imm8, the source operand is the 2nd one. If the last
6059 operand is imm8, the source operand is the first one. */
9c2799c2 6060 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6061 && i.types[0].bitfield.imm8
6062 && i.types[1].bitfield.imm8)
2426c15f 6063 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6064 && i.imm_operands == 1
6065 && (i.types[0].bitfield.imm8
43234a1e
L		 6066 || i.types[i.operands - 1].bitfield.imm8
6067 || i.rounding)));
9f2670f2
L		 6068 if (i.imm_operands == 2)
6069 source = 2;
6070 else
c0f3af97
L		 6071 {
6072 if (i.types[0].bitfield.imm8)
6073 source = 1;
6074 else
6075 source = 0;
6076 }
c0f3af97
L		 6077 break;
6078 case 5:
43234a1e
L		 6079 if (i.tm.opcode_modifier.evex)
6080 {
6081 /* For EVEX instructions, when there are 5 operands, the
6082 first one must be immediate operand. If the second one
6083 is immediate operand, the source operand is the 3th
6084 one. If the last one is immediate operand, the source
6085 operand is the 2nd one. */
6086 gas_assert (i.imm_operands == 2
6087 && i.tm.opcode_modifier.sae
6088 && operand_type_check (i.types[0], imm));
6089 if (operand_type_check (i.types[1], imm))
6090 source = 2;
6091 else if (operand_type_check (i.types[4], imm))
6092 source = 1;
6093 else
6094 abort ();
6095 }
cab737b9
L		 6096 break;
6097 default:
6098 abort ();
6099 }
6100
c0f3af97
L		 6101 if (!vex_3_sources)
6102 {
6103 dest = source + 1;
6104
43234a1e
L		 6105 /* RC/SAE operand could be between DEST and SRC. That happens
6106 when one operand is GPR and the other one is XMM/YMM/ZMM
6107 register. */
6108 if (i.rounding && i.rounding->operand == (int) dest)
6109 dest++;
6110
2426c15f 6111 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6112 {
43234a1e
L		 6113 /* For instructions with VexNDS, the register-only source
6114 operand must be 32/64bit integer, XMM, YMM or ZMM
6115 register. It is encoded in VEX prefix. We need to
6116 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6117
6118 i386_operand_type op;
6119 unsigned int vvvv;
6120
6121 /* Check register-only source operand when two source
6122 operands are swapped. */
6123 if (!i.tm.operand_types[source].bitfield.baseindex
6124 && i.tm.operand_types[dest].bitfield.baseindex)
6125 {
6126 vvvv = source;
6127 source = dest;
6128 }
6129 else
6130 vvvv = dest;
6131
6132 op = i.tm.operand_types[vvvv];
fa99fab2 6133 op.bitfield.regmem = 0;
c0f3af97 6134 if ((dest + 1) >= i.operands
f12dc422
L		 6135 || (op.bitfield.reg32 != 1
6136 && !op.bitfield.reg64 != 1
6137 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6138 && !operand_type_equal (&op, &regymm)
6139 && !operand_type_equal (&op, &regzmm)
6140 && !operand_type_equal (&op, &regmask)))
c0f3af97 6141 abort ();
f12dc422 6142 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6143 dest++;
6144 }
6145 }
29b0f896
AM		 6146
6147 i.rm.mode = 3;
6148 /* One of the register operands will be encoded in the i.tm.reg
6149 field, the other in the combined i.tm.mode and i.tm.regmem
6150 fields. If no form of this instruction supports a memory
6151 destination operand, then we assume the source operand may
6152 sometimes be a memory operand and so we need to store the
6153 destination in the i.rm.reg field. */
40fb9820
L		 6154 if (!i.tm.operand_types[dest].bitfield.regmem
6155 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6156 {
6157 i.rm.reg = i.op[dest].regs->reg_num;
6158 i.rm.regmem = i.op[source].regs->reg_num;
6159 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6160 i.rex |= REX_R;
43234a1e
L		 6161 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6162 i.vrex |= REX_R;
29b0f896 6163 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6164 i.rex |= REX_B;
43234a1e
L		 6165 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6166 i.vrex |= REX_B;
29b0f896
AM		 6167 }
6168 else
6169 {
6170 i.rm.reg = i.op[source].regs->reg_num;
6171 i.rm.regmem = i.op[dest].regs->reg_num;
6172 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6173 i.rex |= REX_B;
43234a1e
L		 6174 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6175 i.vrex |= REX_B;
29b0f896 6176 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6177 i.rex |= REX_R;
43234a1e
L		 6178 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6179 i.vrex |= REX_R;
29b0f896 6180 }
161a04f6 6181 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6182 {
40fb9820
L		 6183 if (!i.types[0].bitfield.control
6184 && !i.types[1].bitfield.control)
c4a530c5 6185 abort ();
161a04f6 6186 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6187 add_prefix (LOCK_PREFIX_OPCODE);
6188 }
29b0f896
AM		 6189 }
6190 else
6191 { /* If it's not 2 reg operands... */
c0f3af97
L		 6192 unsigned int mem;
6193
29b0f896
AM		 6194 if (i.mem_operands)
6195 {
6196 unsigned int fake_zero_displacement = 0;
99018f42 6197 unsigned int op;
4eed87de 6198
7ab9ffdd
L		 6199 for (op = 0; op < i.operands; op++)
6200 if (operand_type_check (i.types[op], anymem))
6201 break;
7ab9ffdd 6202 gas_assert (op < i.operands);
29b0f896 6203
6c30d220
L		 6204 if (i.tm.opcode_modifier.vecsib)
6205 {
6206 if (i.index_reg->reg_num == RegEiz
6207 || i.index_reg->reg_num == RegRiz)
6208 abort ();
6209
6210 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6211 if (!i.base_reg)
6212 {
6213 i.sib.base = NO_BASE_REGISTER;
6214 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6215 /* No Vec_Disp8 if there is no base. */
6216 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6217 i.types[op].bitfield.disp8 = 0;
6218 i.types[op].bitfield.disp16 = 0;
6219 i.types[op].bitfield.disp64 = 0;
6220 if (flag_code != CODE_64BIT)
6221 {
6222 /* Must be 32 bit */
6223 i.types[op].bitfield.disp32 = 1;
6224 i.types[op].bitfield.disp32s = 0;
6225 }
6226 else
6227 {
6228 i.types[op].bitfield.disp32 = 0;
6229 i.types[op].bitfield.disp32s = 1;
6230 }
6231 }
6232 i.sib.index = i.index_reg->reg_num;
6233 if ((i.index_reg->reg_flags & RegRex) != 0)
6234 i.rex |= REX_X;
43234a1e
L		 6235 if ((i.index_reg->reg_flags & RegVRex) != 0)
6236 i.vrex |= REX_X;
6c30d220
L		 6237 }
6238
29b0f896
AM		 6239 default_seg = &ds;
6240
6241 if (i.base_reg == 0)
6242 {
6243 i.rm.mode = 0;
6244 if (!i.disp_operands)
6c30d220
L		 6245 {
6246 fake_zero_displacement = 1;
6247 /* Instructions with VSIB byte need 32bit displacement
6248 if there is no base register. */
6249 if (i.tm.opcode_modifier.vecsib)
6250 i.types[op].bitfield.disp32 = 1;
6251 }
29b0f896
AM		 6252 if (i.index_reg == 0)
6253 {
6c30d220 6254 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6255 /* Operand is just <disp> */
20f0a1fc 6256 if (flag_code == CODE_64BIT)
29b0f896
AM		 6257 {
6258 /* 64bit mode overwrites the 32bit absolute
6259 addressing by RIP relative addressing and
6260 absolute addressing is encoded by one of the
6261 redundant SIB forms. */
6262 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6263 i.sib.base = NO_BASE_REGISTER;
6264 i.sib.index = NO_INDEX_REGISTER;
fc225355 6265 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6266 ? disp32s : disp32);
20f0a1fc 6267 }
fc225355
L		 6268 else if ((flag_code == CODE_16BIT)
6269 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6270 {
6271 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6272 i.types[op] = disp16;
20f0a1fc
NC		 6273 }
6274 else
6275 {
6276 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6277 i.types[op] = disp32;
29b0f896
AM		 6278 }
6279 }
6c30d220 6280 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6281 {
6c30d220 6282 /* !i.base_reg && i.index_reg */
db51cc60
L		 6283 if (i.index_reg->reg_num == RegEiz
6284 || i.index_reg->reg_num == RegRiz)
6285 i.sib.index = NO_INDEX_REGISTER;
6286 else
6287 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6288 i.sib.base = NO_BASE_REGISTER;
6289 i.sib.scale = i.log2_scale_factor;
6290 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6291 /* No Vec_Disp8 if there is no base. */
6292 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6293 i.types[op].bitfield.disp8 = 0;
6294 i.types[op].bitfield.disp16 = 0;
6295 i.types[op].bitfield.disp64 = 0;
29b0f896 6296 if (flag_code != CODE_64BIT)
40fb9820
L		 6297 {
6298 /* Must be 32 bit */
6299 i.types[op].bitfield.disp32 = 1;
6300 i.types[op].bitfield.disp32s = 0;
6301 }
29b0f896 6302 else
40fb9820
L		 6303 {
6304 i.types[op].bitfield.disp32 = 0;
6305 i.types[op].bitfield.disp32s = 1;
6306 }
29b0f896 6307 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6308 i.rex |= REX_X;
29b0f896
AM		 6309 }
6310 }
6311 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6312 else if (i.base_reg->reg_num == RegRip ||
6313 i.base_reg->reg_num == RegEip)
29b0f896 6314 {
6c30d220 6315 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6316 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6317 i.types[op].bitfield.disp8 = 0;
6318 i.types[op].bitfield.disp16 = 0;
6319 i.types[op].bitfield.disp32 = 0;
6320 i.types[op].bitfield.disp32s = 1;
6321 i.types[op].bitfield.disp64 = 0;
43234a1e 6322 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6323 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6324 if (! i.disp_operands)
6325 fake_zero_displacement = 1;
29b0f896 6326 }
40fb9820 6327 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6328 {
6c30d220 6329 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6330 switch (i.base_reg->reg_num)
6331 {
6332 case 3: /* (%bx) */
6333 if (i.index_reg == 0)
6334 i.rm.regmem = 7;
6335 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6336 i.rm.regmem = i.index_reg->reg_num - 6;
6337 break;
6338 case 5: /* (%bp) */
6339 default_seg = &ss;
6340 if (i.index_reg == 0)
6341 {
6342 i.rm.regmem = 6;
40fb9820 6343 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6344 {
6345 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6346 if (i.tm.operand_types[op].bitfield.vec_disp8)
6347 i.types[op].bitfield.vec_disp8 = 1;
6348 else
6349 i.types[op].bitfield.disp8 = 1;
252b5132 6350 fake_zero_displacement = 1;
29b0f896
AM		 6351 }
6352 }
6353 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6354 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6355 break;
6356 default: /* (%si) -> 4 or (%di) -> 5 */
6357 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6358 }
6359 i.rm.mode = mode_from_disp_size (i.types[op]);
6360 }
6361 else /* i.base_reg and 32/64 bit mode */
6362 {
6363 if (flag_code == CODE_64BIT
40fb9820
L		 6364 && operand_type_check (i.types[op], disp))
6365 {
6366 i386_operand_type temp;
0dfbf9d7 6367 operand_type_set (&temp, 0);
40fb9820 6368 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6369 temp.bitfield.vec_disp8
6370 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6371 i.types[op] = temp;
6372 if (i.prefix[ADDR_PREFIX] == 0)
6373 i.types[op].bitfield.disp32s = 1;
6374 else
6375 i.types[op].bitfield.disp32 = 1;
6376 }
20f0a1fc 6377
6c30d220
L		 6378 if (!i.tm.opcode_modifier.vecsib)
6379 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6380 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6381 i.rex |= REX_B;
29b0f896
AM		 6382 i.sib.base = i.base_reg->reg_num;
6383 /* x86-64 ignores REX prefix bit here to avoid decoder
6384 complications. */
848930b2
JB		 6385 if (!(i.base_reg->reg_flags & RegRex)
6386 && (i.base_reg->reg_num == EBP_REG_NUM
6387 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6388 default_seg = &ss;
848930b2 6389 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6390 {
848930b2 6391 fake_zero_displacement = 1;
43234a1e
L		 6392 if (i.tm.operand_types [op].bitfield.vec_disp8)
6393 i.types[op].bitfield.vec_disp8 = 1;
6394 else
6395 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6396 }
6397 i.sib.scale = i.log2_scale_factor;
6398 if (i.index_reg == 0)
6399 {
6c30d220 6400 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6401 /* <disp>(%esp) becomes two byte modrm with no index
6402 register. We've already stored the code for esp
6403 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6404 Any base register besides %esp will not use the
6405 extra modrm byte. */
6406 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6407 }
6c30d220 6408 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6409 {
db51cc60
L		 6410 if (i.index_reg->reg_num == RegEiz
6411 || i.index_reg->reg_num == RegRiz)
6412 i.sib.index = NO_INDEX_REGISTER;
6413 else
6414 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6415 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6416 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6417 i.rex |= REX_X;
29b0f896 6418 }
67a4f2b7
AO		 6419
6420 if (i.disp_operands
6421 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6422 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6423 i.rm.mode = 0;
6424 else
a501d77e
L		 6425 {
6426 if (!fake_zero_displacement
6427 && !i.disp_operands
6428 && i.disp_encoding)
6429 {
6430 fake_zero_displacement = 1;
6431 if (i.disp_encoding == disp_encoding_8bit)
6432 i.types[op].bitfield.disp8 = 1;
6433 else
6434 i.types[op].bitfield.disp32 = 1;
6435 }
6436 i.rm.mode = mode_from_disp_size (i.types[op]);
6437 }
29b0f896 6438 }
252b5132 6439
29b0f896
AM		 6440 if (fake_zero_displacement)
6441 {
6442 /* Fakes a zero displacement assuming that i.types[op]
6443 holds the correct displacement size. */
6444 expressionS *exp;
6445
9c2799c2 6446 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6447 exp = &disp_expressions[i.disp_operands++];
6448 i.op[op].disps = exp;
6449 exp->X_op = O_constant;
6450 exp->X_add_number = 0;
6451 exp->X_add_symbol = (symbolS *) 0;
6452 exp->X_op_symbol = (symbolS *) 0;
6453 }
c0f3af97
L		 6454
6455 mem = op;
29b0f896 6456 }
c0f3af97
L		 6457 else
6458 mem = ~0;
252b5132 6459
8c43a48b 6460 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6461 {
6462 if (operand_type_check (i.types[0], imm))
6463 i.vex.register_specifier = NULL;
6464 else
6465 {
6466 /* VEX.vvvv encodes one of the sources when the first
6467 operand is not an immediate. */
1ef99a7b 6468 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6469 i.vex.register_specifier = i.op[0].regs;
6470 else
6471 i.vex.register_specifier = i.op[1].regs;
6472 }
6473
6474 /* Destination is a XMM register encoded in the ModRM.reg
6475 and VEX.R bit. */
6476 i.rm.reg = i.op[2].regs->reg_num;
6477 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6478 i.rex |= REX_R;
6479
6480 /* ModRM.rm and VEX.B encodes the other source. */
6481 if (!i.mem_operands)
6482 {
6483 i.rm.mode = 3;
6484
1ef99a7b 6485 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6486 i.rm.regmem = i.op[1].regs->reg_num;
6487 else
6488 i.rm.regmem = i.op[0].regs->reg_num;
6489
6490 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6491 i.rex |= REX_B;
6492 }
6493 }
2426c15f 6494 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6495 {
6496 i.vex.register_specifier = i.op[2].regs;
6497 if (!i.mem_operands)
6498 {
6499 i.rm.mode = 3;
6500 i.rm.regmem = i.op[1].regs->reg_num;
6501 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6502 i.rex |= REX_B;
6503 }
6504 }
29b0f896
AM		 6505 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6506 (if any) based on i.tm.extension_opcode. Again, we must be
6507 careful to make sure that segment/control/debug/test/MMX
6508 registers are coded into the i.rm.reg field. */
f88c9eb0 6509 else if (i.reg_operands)
29b0f896 6510 {
99018f42 6511 unsigned int op;
7ab9ffdd
L		 6512 unsigned int vex_reg = ~0;
6513
6514 for (op = 0; op < i.operands; op++)
6515 if (i.types[op].bitfield.reg8
6516 || i.types[op].bitfield.reg16
6517 || i.types[op].bitfield.reg32
6518 || i.types[op].bitfield.reg64
6519 || i.types[op].bitfield.regmmx
6520 || i.types[op].bitfield.regxmm
6521 || i.types[op].bitfield.regymm
7e8b059b 6522 || i.types[op].bitfield.regbnd
43234a1e
L		 6523 || i.types[op].bitfield.regzmm
6524 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6525 || i.types[op].bitfield.sreg2
6526 || i.types[op].bitfield.sreg3
6527 || i.types[op].bitfield.control
6528 || i.types[op].bitfield.debug
6529 || i.types[op].bitfield.test)
6530 break;
c0209578 6531
7ab9ffdd
L		 6532 if (vex_3_sources)
6533 op = dest;
2426c15f 6534 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6535 {
6536 /* For instructions with VexNDS, the register-only
6537 source operand is encoded in VEX prefix. */
6538 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6539
7ab9ffdd 6540 if (op > mem)
c0f3af97 6541 {
7ab9ffdd
L		 6542 vex_reg = op++;
6543 gas_assert (op < i.operands);
c0f3af97
L		 6544 }
6545 else
c0f3af97 6546 {
f12dc422
L		 6547 /* Check register-only source operand when two source
6548 operands are swapped. */
6549 if (!i.tm.operand_types[op].bitfield.baseindex
6550 && i.tm.operand_types[op + 1].bitfield.baseindex)
6551 {
6552 vex_reg = op;
6553 op += 2;
6554 gas_assert (mem == (vex_reg + 1)
6555 && op < i.operands);
6556 }
6557 else
6558 {
6559 vex_reg = op + 1;
6560 gas_assert (vex_reg < i.operands);
6561 }
c0f3af97 6562 }
7ab9ffdd 6563 }
2426c15f 6564 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6565 {
f12dc422 6566 /* For instructions with VexNDD, the register destination
7ab9ffdd 6567 is encoded in VEX prefix. */
f12dc422
L		 6568 if (i.mem_operands == 0)
6569 {
6570 /* There is no memory operand. */
6571 gas_assert ((op + 2) == i.operands);
6572 vex_reg = op + 1;
6573 }
6574 else
8d63c93e 6575 {
f12dc422
L		 6576 /* There are only 2 operands. */
6577 gas_assert (op < 2 && i.operands == 2);
6578 vex_reg = 1;
6579 }
7ab9ffdd
L		 6580 }
6581 else
6582 gas_assert (op < i.operands);
99018f42 6583
7ab9ffdd
L		 6584 if (vex_reg != (unsigned int) ~0)
6585 {
f12dc422 6586 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6587
f12dc422
L		 6588 if (type->bitfield.reg32 != 1
6589 && type->bitfield.reg64 != 1
6590 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6591 && !operand_type_equal (type, &regymm)
6592 && !operand_type_equal (type, &regzmm)
6593 && !operand_type_equal (type, &regmask))
7ab9ffdd 6594 abort ();
f88c9eb0 6595
7ab9ffdd
L		 6596 i.vex.register_specifier = i.op[vex_reg].regs;
6597 }
6598
1b9f0c97
L		 6599 /* Don't set OP operand twice. */
6600 if (vex_reg != op)
7ab9ffdd 6601 {
1b9f0c97
L		 6602 /* If there is an extension opcode to put here, the
6603 register number must be put into the regmem field. */
6604 if (i.tm.extension_opcode != None)
6605 {
6606 i.rm.regmem = i.op[op].regs->reg_num;
6607 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6608 i.rex |= REX_B;
43234a1e
L		 6609 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6610 i.vrex |= REX_B;
1b9f0c97
L		 6611 }
6612 else
6613 {
6614 i.rm.reg = i.op[op].regs->reg_num;
6615 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6616 i.rex |= REX_R;
43234a1e
L		 6617 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6618 i.vrex |= REX_R;
1b9f0c97 6619 }
7ab9ffdd 6620 }
252b5132 6621
29b0f896
AM		 6622 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6623 must set it to 3 to indicate this is a register operand
6624 in the regmem field. */
6625 if (!i.mem_operands)
6626 i.rm.mode = 3;
6627 }
252b5132 6628
29b0f896 6629 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6630 if (i.tm.extension_opcode != None)
29b0f896
AM		 6631 i.rm.reg = i.tm.extension_opcode;
6632 }
6633 return default_seg;
6634}
252b5132 6635
29b0f896 6636static void
e3bb37b5 6637output_branch (void)
29b0f896
AM		 6638{
6639 char *p;
f8a5c266 6640 int size;
29b0f896
AM		 6641 int code16;
6642 int prefix;
6643 relax_substateT subtype;
6644 symbolS *sym;
6645 offsetT off;
6646
f8a5c266 6647 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6648 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6649
6650 prefix = 0;
6651 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6652 {
29b0f896
AM		 6653 prefix = 1;
6654 i.prefixes -= 1;
6655 code16 ^= CODE16;
252b5132 6656 }
29b0f896
AM		 6657 /* Pentium4 branch hints. */
6658 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6659 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6660 {
29b0f896
AM		 6661 prefix++;
6662 i.prefixes--;
6663 }
6664 if (i.prefix[REX_PREFIX] != 0)
6665 {
6666 prefix++;
6667 i.prefixes--;
2f66722d
AM		 6668 }
6669
7e8b059b
L		 6670 /* BND prefixed jump. */
6671 if (i.prefix[BND_PREFIX] != 0)
6672 {
6673 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6674 i.prefixes -= 1;
6675 }
6676
29b0f896
AM		 6677 if (i.prefixes != 0 && !intel_syntax)
6678 as_warn (_("skipping prefixes on this instruction"));
6679
6680 /* It's always a symbol; End frag & setup for relax.
6681 Make sure there is enough room in this frag for the largest
6682 instruction we may generate in md_convert_frag. This is 2
6683 bytes for the opcode and room for the prefix and largest
6684 displacement. */
6685 frag_grow (prefix + 2 + 4);
6686 /* Prefix and 1 opcode byte go in fr_fix. */
6687 p = frag_more (prefix + 1);
6688 if (i.prefix[DATA_PREFIX] != 0)
6689 *p++ = DATA_PREFIX_OPCODE;
6690 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6691 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6692 *p++ = i.prefix[SEG_PREFIX];
6693 if (i.prefix[REX_PREFIX] != 0)
6694 *p++ = i.prefix[REX_PREFIX];
6695 *p = i.tm.base_opcode;
6696
6697 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6698 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6699 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6700 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6701 else
f8a5c266 6702 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6703 subtype |= code16;
3e73aa7c 6704
29b0f896
AM		 6705 sym = i.op[0].disps->X_add_symbol;
6706 off = i.op[0].disps->X_add_number;
3e73aa7c 6707
29b0f896
AM		 6708 if (i.op[0].disps->X_op != O_constant
6709 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6710 {
29b0f896
AM		 6711 /* Handle complex expressions. */
6712 sym = make_expr_symbol (i.op[0].disps);
6713 off = 0;
6714 }
3e73aa7c 6715
29b0f896
AM		 6716 /* 1 possible extra opcode + 4 byte displacement go in var part.
6717 Pass reloc in fr_var. */
6718 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
6719}
3e73aa7c 6720
29b0f896 6721static void
e3bb37b5 6722output_jump (void)
29b0f896
AM		 6723{
6724 char *p;
6725 int size;
3e02c1cc 6726 fixS *fixP;
29b0f896 6727
40fb9820 6728 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6729 {
6730 /* This is a loop or jecxz type instruction. */
6731 size = 1;
6732 if (i.prefix[ADDR_PREFIX] != 0)
6733 {
6734 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6735 i.prefixes -= 1;
6736 }
6737 /* Pentium4 branch hints. */
6738 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6739 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6740 {
6741 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6742 i.prefixes--;
3e73aa7c
JH		 6743 }
6744 }
29b0f896
AM		 6745 else
6746 {
6747 int code16;
3e73aa7c 6748
29b0f896
AM		 6749 code16 = 0;
6750 if (flag_code == CODE_16BIT)
6751 code16 = CODE16;
3e73aa7c 6752
29b0f896
AM		 6753 if (i.prefix[DATA_PREFIX] != 0)
6754 {
6755 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6756 i.prefixes -= 1;
6757 code16 ^= CODE16;
6758 }
252b5132 6759
29b0f896
AM		 6760 size = 4;
6761 if (code16)
6762 size = 2;
6763 }
9fcc94b6 6764
29b0f896
AM		 6765 if (i.prefix[REX_PREFIX] != 0)
6766 {
6767 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6768 i.prefixes -= 1;
6769 }
252b5132 6770
7e8b059b
L		 6771 /* BND prefixed jump. */
6772 if (i.prefix[BND_PREFIX] != 0)
6773 {
6774 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6775 i.prefixes -= 1;
6776 }
6777
29b0f896
AM		 6778 if (i.prefixes != 0 && !intel_syntax)
6779 as_warn (_("skipping prefixes on this instruction"));
e0890092 6780
42164a71
L		 6781 p = frag_more (i.tm.opcode_length + size);
6782 switch (i.tm.opcode_length)
6783 {
6784 case 2:
6785 *p++ = i.tm.base_opcode >> 8;
6786 case 1:
6787 *p++ = i.tm.base_opcode;
6788 break;
6789 default:
6790 abort ();
6791 }
e0890092 6792
3e02c1cc
AM		 6793 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6794 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
6795
6796 /* All jumps handled here are signed, but don't use a signed limit
6797 check for 32 and 16 bit jumps as we want to allow wrap around at
6798 4G and 64k respectively. */
6799 if (size == 1)
6800 fixP->fx_signed = 1;
29b0f896 6801}
e0890092 6802
29b0f896 6803static void
e3bb37b5 6804output_interseg_jump (void)
29b0f896
AM		 6805{
6806 char *p;
6807 int size;
6808 int prefix;
6809 int code16;
252b5132 6810
29b0f896
AM		 6811 code16 = 0;
6812 if (flag_code == CODE_16BIT)
6813 code16 = CODE16;
a217f122 6814
29b0f896
AM		 6815 prefix = 0;
6816 if (i.prefix[DATA_PREFIX] != 0)
6817 {
6818 prefix = 1;
6819 i.prefixes -= 1;
6820 code16 ^= CODE16;
6821 }
6822 if (i.prefix[REX_PREFIX] != 0)
6823 {
6824 prefix++;
6825 i.prefixes -= 1;
6826 }
252b5132 6827
29b0f896
AM		 6828 size = 4;
6829 if (code16)
6830 size = 2;
252b5132 6831
29b0f896
AM		 6832 if (i.prefixes != 0 && !intel_syntax)
6833 as_warn (_("skipping prefixes on this instruction"));
252b5132 6834
29b0f896
AM		 6835 /* 1 opcode; 2 segment; offset */
6836 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6837
29b0f896
AM		 6838 if (i.prefix[DATA_PREFIX] != 0)
6839 *p++ = DATA_PREFIX_OPCODE;
252b5132 6840
29b0f896
AM		 6841 if (i.prefix[REX_PREFIX] != 0)
6842 *p++ = i.prefix[REX_PREFIX];
252b5132 6843
29b0f896
AM		 6844 *p++ = i.tm.base_opcode;
6845 if (i.op[1].imms->X_op == O_constant)
6846 {
6847 offsetT n = i.op[1].imms->X_add_number;
252b5132 6848
29b0f896
AM		 6849 if (size == 2
6850 && !fits_in_unsigned_word (n)
6851 && !fits_in_signed_word (n))
6852 {
6853 as_bad (_("16-bit jump out of range"));
6854 return;
6855 }
6856 md_number_to_chars (p, n, size);
6857 }
6858 else
6859 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6860 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
6861 if (i.op[0].imms->X_op != O_constant)
6862 as_bad (_("can't handle non absolute segment in `%s'"),
6863 i.tm.name);
6864 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6865}
a217f122 6866
29b0f896 6867static void
e3bb37b5 6868output_insn (void)
29b0f896 6869{
2bbd9c25
JJ		 6870 fragS *insn_start_frag;
6871 offsetT insn_start_off;
6872
29b0f896
AM		 6873 /* Tie dwarf2 debug info to the address at the start of the insn.
6874 We can't do this after the insn has been output as the current
6875 frag may have been closed off. eg. by frag_var. */
6876 dwarf2_emit_insn (0);
6877
2bbd9c25
JJ		 6878 insn_start_frag = frag_now;
6879 insn_start_off = frag_now_fix ();
6880
29b0f896 6881 /* Output jumps. */
40fb9820 6882 if (i.tm.opcode_modifier.jump)
29b0f896 6883 output_branch ();
40fb9820
L		 6884 else if (i.tm.opcode_modifier.jumpbyte
6885 || i.tm.opcode_modifier.jumpdword)
29b0f896 6886 output_jump ();
40fb9820 6887 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6888 output_interseg_jump ();
6889 else
6890 {
6891 /* Output normal instructions here. */
6892 char *p;
6893 unsigned char *q;
47465058 6894 unsigned int j;
331d2d0d 6895 unsigned int prefix;
4dffcebc 6896
43234a1e
L		 6897 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6898 don't need the explicit prefix. */
6899 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6900 {
c0f3af97 6901 switch (i.tm.opcode_length)
bc4bd9ab 6902 {
c0f3af97
L		 6903 case 3:
6904 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6905 {
c0f3af97
L		 6906 prefix = (i.tm.base_opcode >> 24) & 0xff;
6907 goto check_prefix;
6908 }
6909 break;
6910 case 2:
6911 if ((i.tm.base_opcode & 0xff0000) != 0)
6912 {
6913 prefix = (i.tm.base_opcode >> 16) & 0xff;
6914 if (i.tm.cpu_flags.bitfield.cpupadlock)
6915 {
4dffcebc 6916check_prefix:
c0f3af97 6917 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6918 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6919 != REPE_PREFIX_OPCODE))
6920 add_prefix (prefix);
6921 }
6922 else
4dffcebc
L		 6923 add_prefix (prefix);
6924 }
c0f3af97
L		 6925 break;
6926 case 1:
6927 break;
6928 default:
6929 abort ();
bc4bd9ab 6930 }
c0f3af97
L		 6931
6932 /* The prefix bytes. */
6933 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6934 if (*q)
6935 FRAG_APPEND_1_CHAR (*q);
0f10071e 6936 }
ae5c1c7b 6937 else
c0f3af97
L		 6938 {
6939 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6940 if (*q)
6941 switch (j)
6942 {
6943 case REX_PREFIX:
6944 /* REX byte is encoded in VEX prefix. */
6945 break;
6946 case SEG_PREFIX:
6947 case ADDR_PREFIX:
6948 FRAG_APPEND_1_CHAR (*q);
6949 break;
6950 default:
6951 /* There should be no other prefixes for instructions
6952 with VEX prefix. */
6953 abort ();
6954 }
6955
43234a1e
L		 6956 /* For EVEX instructions i.vrex should become 0 after
6957 build_evex_prefix. For VEX instructions upper 16 registers
6958 aren't available, so VREX should be 0. */
6959 if (i.vrex)
6960 abort ();
c0f3af97
L		 6961 /* Now the VEX prefix. */
6962 p = frag_more (i.vex.length);
6963 for (j = 0; j < i.vex.length; j++)
6964 p[j] = i.vex.bytes[j];
6965 }
252b5132 6966
29b0f896 6967 /* Now the opcode; be careful about word order here! */
4dffcebc 6968 if (i.tm.opcode_length == 1)
29b0f896
AM		 6969 {
6970 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
6971 }
6972 else
6973 {
4dffcebc 6974 switch (i.tm.opcode_length)
331d2d0d 6975 {
43234a1e
L		 6976 case 4:
6977 p = frag_more (4);
6978 *p++ = (i.tm.base_opcode >> 24) & 0xff;
6979 *p++ = (i.tm.base_opcode >> 16) & 0xff;
6980 break;
4dffcebc 6981 case 3:
331d2d0d
L		 6982 p = frag_more (3);
6983 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 6984 break;
6985 case 2:
6986 p = frag_more (2);
6987 break;
6988 default:
6989 abort ();
6990 break;
331d2d0d 6991 }
0f10071e 6992
29b0f896
AM		 6993 /* Put out high byte first: can't use md_number_to_chars! */
6994 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6995 *p = i.tm.base_opcode & 0xff;
6996 }
3e73aa7c 6997
29b0f896 6998 /* Now the modrm byte and sib byte (if present). */
40fb9820 6999 if (i.tm.opcode_modifier.modrm)
29b0f896 7000 {
4a3523fa
L		 7001 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7002 | i.rm.reg << 3
7003 | i.rm.mode << 6));
29b0f896
AM		 7004 /* If i.rm.regmem == ESP (4)
7005 && i.rm.mode != (Register mode)
7006 && not 16 bit
7007 ==> need second modrm byte. */
7008 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7009 && i.rm.mode != 3
40fb9820 7010 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7011 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7012 | i.sib.index << 3
7013 | i.sib.scale << 6));
29b0f896 7014 }
3e73aa7c 7015
29b0f896 7016 if (i.disp_operands)
2bbd9c25 7017 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7018
29b0f896 7019 if (i.imm_operands)
2bbd9c25 7020 output_imm (insn_start_frag, insn_start_off);
29b0f896 7021 }
252b5132 7022
29b0f896
AM		 7023#ifdef DEBUG386
7024 if (flag_debug)
7025 {
7b81dfbb 7026 pi ("" /*line*/, &i);
29b0f896
AM		 7027 }
7028#endif /* DEBUG386 */
7029}
252b5132 7030
e205caa7
L		 7031/* Return the size of the displacement operand N. */
7032
7033static int
7034disp_size (unsigned int n)
7035{
7036 int size = 4;
43234a1e
L		 7037
7038 /* Vec_Disp8 has to be 8bit. */
7039 if (i.types[n].bitfield.vec_disp8)
7040 size = 1;
7041 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7042 size = 8;
7043 else if (i.types[n].bitfield.disp8)
7044 size = 1;
7045 else if (i.types[n].bitfield.disp16)
7046 size = 2;
e205caa7
L		 7047 return size;
7048}
7049
7050/* Return the size of the immediate operand N. */
7051
7052static int
7053imm_size (unsigned int n)
7054{
7055 int size = 4;
40fb9820
L		 7056 if (i.types[n].bitfield.imm64)
7057 size = 8;
7058 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7059 size = 1;
7060 else if (i.types[n].bitfield.imm16)
7061 size = 2;
e205caa7
L		 7062 return size;
7063}
7064
29b0f896 7065static void
64e74474 7066output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7067{
7068 char *p;
7069 unsigned int n;
252b5132 7070
29b0f896
AM		 7071 for (n = 0; n < i.operands; n++)
7072 {
43234a1e
L		 7073 if (i.types[n].bitfield.vec_disp8
7074 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7075 {
7076 if (i.op[n].disps->X_op == O_constant)
7077 {
e205caa7 7078 int size = disp_size (n);
43234a1e 7079 offsetT val = i.op[n].disps->X_add_number;
252b5132 7080
43234a1e
L		 7081 if (i.types[n].bitfield.vec_disp8)
7082 val >>= i.memshift;
7083 val = offset_in_range (val, size);
29b0f896
AM		 7084 p = frag_more (size);
7085 md_number_to_chars (p, val, size);
7086 }
7087 else
7088 {
f86103b7 7089 enum bfd_reloc_code_real reloc_type;
e205caa7 7090 int size = disp_size (n);
40fb9820 7091 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 7092 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7093
e205caa7 7094 /* We can't have 8 bit displacement here. */
9c2799c2 7095 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7096
29b0f896
AM		 7097 /* The PC relative address is computed relative
7098 to the instruction boundary, so in case immediate
7099 fields follows, we need to adjust the value. */
7100 if (pcrel && i.imm_operands)
7101 {
29b0f896 7102 unsigned int n1;
e205caa7 7103 int sz = 0;
252b5132 7104
29b0f896 7105 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7106 if (operand_type_check (i.types[n1], imm))
252b5132 7107 {
e205caa7
L		 7108 /* Only one immediate is allowed for PC
7109 relative address. */
9c2799c2 7110 gas_assert (sz == 0);
e205caa7
L		 7111 sz = imm_size (n1);
7112 i.op[n].disps->X_add_number -= sz;
252b5132 7113 }
29b0f896 7114 /* We should find the immediate. */
9c2799c2 7115 gas_assert (sz != 0);
29b0f896 7116 }
520dc8e8 7117
29b0f896 7118 p = frag_more (size);
2bbd9c25 7119 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7120 if (GOT_symbol
2bbd9c25 7121 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7122 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7123 || reloc_type == BFD_RELOC_X86_64_32S
7124 || (reloc_type == BFD_RELOC_64
7125 && object_64bit))
d6ab8113
JB		 7126 && (i.op[n].disps->X_op == O_symbol
7127 || (i.op[n].disps->X_op == O_add
7128 && ((symbol_get_value_expression
7129 (i.op[n].disps->X_op_symbol)->X_op)
7130 == O_subtract))))
7131 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7132 {
7133 offsetT add;
7134
7135 if (insn_start_frag == frag_now)
7136 add = (p - frag_now->fr_literal) - insn_start_off;
7137 else
7138 {
7139 fragS *fr;
7140
7141 add = insn_start_frag->fr_fix - insn_start_off;
7142 for (fr = insn_start_frag->fr_next;
7143 fr && fr != frag_now; fr = fr->fr_next)
7144 add += fr->fr_fix;
7145 add += p - frag_now->fr_literal;
7146 }
7147
4fa24527 7148 if (!object_64bit)
7b81dfbb
AJ		 7149 {
7150 reloc_type = BFD_RELOC_386_GOTPC;
7151 i.op[n].imms->X_add_number += add;
7152 }
7153 else if (reloc_type == BFD_RELOC_64)
7154 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7155 else
7b81dfbb
AJ		 7156 /* Don't do the adjustment for x86-64, as there
7157 the pcrel addressing is relative to the _next_
7158 insn, and that is taken care of in other code. */
d6ab8113 7159 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7160 }
062cd5e7 7161 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 7162 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 7163 }
7164 }
7165 }
7166}
252b5132 7167
29b0f896 7168static void
64e74474 7169output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7170{
7171 char *p;
7172 unsigned int n;
252b5132 7173
29b0f896
AM		 7174 for (n = 0; n < i.operands; n++)
7175 {
43234a1e
L		 7176 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7177 if (i.rounding && (int) n == i.rounding->operand)
7178 continue;
7179
40fb9820 7180 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7181 {
7182 if (i.op[n].imms->X_op == O_constant)
7183 {
e205caa7 7184 int size = imm_size (n);
29b0f896 7185 offsetT val;
b4cac588 7186
29b0f896
AM		 7187 val = offset_in_range (i.op[n].imms->X_add_number,
7188 size);
7189 p = frag_more (size);
7190 md_number_to_chars (p, val, size);
7191 }
7192 else
7193 {
7194 /* Not absolute_section.
7195 Need a 32-bit fixup (don't support 8bit
7196 non-absolute imms). Try to support other
7197 sizes ... */
f86103b7 7198 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7199 int size = imm_size (n);
7200 int sign;
29b0f896 7201
40fb9820 7202 if (i.types[n].bitfield.imm32s
a7d61044 7203 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7204 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7205 sign = 1;
e205caa7
L		 7206 else
7207 sign = 0;
520dc8e8 7208
29b0f896
AM		 7209 p = frag_more (size);
7210 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7211
2bbd9c25
JJ		 7212 /* This is tough to explain. We end up with this one if we
7213 * have operands that look like
7214 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7215 * obtain the absolute address of the GOT, and it is strongly
7216 * preferable from a performance point of view to avoid using
7217 * a runtime relocation for this. The actual sequence of
7218 * instructions often look something like:
7219 *
7220 * call .L66
7221 * .L66:
7222 * popl %ebx
7223 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7224 *
7225 * The call and pop essentially return the absolute address
7226 * of the label .L66 and store it in %ebx. The linker itself
7227 * will ultimately change the first operand of the addl so
7228 * that %ebx points to the GOT, but to keep things simple, the
7229 * .o file must have this operand set so that it generates not
7230 * the absolute address of .L66, but the absolute address of
7231 * itself. This allows the linker itself simply treat a GOTPC
7232 * relocation as asking for a pcrel offset to the GOT to be
7233 * added in, and the addend of the relocation is stored in the
7234 * operand field for the instruction itself.
7235 *
7236 * Our job here is to fix the operand so that it would add
7237 * the correct offset so that %ebx would point to itself. The
7238 * thing that is tricky is that .-.L66 will point to the
7239 * beginning of the instruction, so we need to further modify
7240 * the operand so that it will point to itself. There are
7241 * other cases where you have something like:
7242 *
7243 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7244 *
7245 * and here no correction would be required. Internally in
7246 * the assembler we treat operands of this form as not being
7247 * pcrel since the '.' is explicitly mentioned, and I wonder
7248 * whether it would simplify matters to do it this way. Who
7249 * knows. In earlier versions of the PIC patches, the
7250 * pcrel_adjust field was used to store the correction, but
7251 * since the expression is not pcrel, I felt it would be
7252 * confusing to do it this way. */
7253
d6ab8113 7254 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7255 || reloc_type == BFD_RELOC_X86_64_32S
7256 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7257 && GOT_symbol
7258 && GOT_symbol == i.op[n].imms->X_add_symbol
7259 && (i.op[n].imms->X_op == O_symbol
7260 || (i.op[n].imms->X_op == O_add
7261 && ((symbol_get_value_expression
7262 (i.op[n].imms->X_op_symbol)->X_op)
7263 == O_subtract))))
7264 {
2bbd9c25
JJ		 7265 offsetT add;
7266
7267 if (insn_start_frag == frag_now)
7268 add = (p - frag_now->fr_literal) - insn_start_off;
7269 else
7270 {
7271 fragS *fr;
7272
7273 add = insn_start_frag->fr_fix - insn_start_off;
7274 for (fr = insn_start_frag->fr_next;
7275 fr && fr != frag_now; fr = fr->fr_next)
7276 add += fr->fr_fix;
7277 add += p - frag_now->fr_literal;
7278 }
7279
4fa24527 7280 if (!object_64bit)
d6ab8113 7281 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7282 else if (size == 4)
d6ab8113 7283 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7284 else if (size == 8)
7285 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7286 i.op[n].imms->X_add_number += add;
29b0f896 7287 }
29b0f896
AM		 7288 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7289 i.op[n].imms, 0, reloc_type);
7290 }
7291 }
7292 }
252b5132
RH		 7293}
7294\f
d182319b
JB		 7295/* x86_cons_fix_new is called via the expression parsing code when a
7296 reloc is needed. We use this hook to get the correct .got reloc. */
7297static enum bfd_reloc_code_real got_reloc = NO_RELOC;
7298static int cons_sign = -1;
7299
7300void
e3bb37b5 7301x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 7302 expressionS *exp)
d182319b
JB		 7303{
7304 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
7305
7306 got_reloc = NO_RELOC;
7307
7308#ifdef TE_PE
7309 if (exp->X_op == O_secrel)
7310 {
7311 exp->X_op = O_symbol;
7312 r = BFD_RELOC_32_SECREL;
7313 }
7314#endif
7315
7316 fix_new_exp (frag, off, len, exp, 0, r);
7317}
7318
357d1bd8
L		 7319/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7320 purpose of the `.dc.a' internal pseudo-op. */
7321
7322int
7323x86_address_bytes (void)
7324{
7325 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7326 return 4;
7327 return stdoutput->arch_info->bits_per_address / 8;
7328}
7329
d382c579
TG		 7330#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7331 || defined (LEX_AT)
718ddfc0
JB		 7332# define lex_got(reloc, adjust, types) NULL
7333#else
f3c180ae
AM		 7334/* Parse operands of the form
7335 <symbol>@GOTOFF+<nnn>
7336 and similar .plt or .got references.
7337
7338 If we find one, set up the correct relocation in RELOC and copy the
7339 input string, minus the `@GOTOFF' into a malloc'd buffer for
7340 parsing by the calling routine. Return this buffer, and if ADJUST
7341 is non-null set it to the length of the string we removed from the
7342 input line. Otherwise return NULL. */
7343static char *
91d6fa6a 7344lex_got (enum bfd_reloc_code_real *rel,
64e74474 7345 int *adjust,
40fb9820 7346 i386_operand_type *types)
f3c180ae 7347{
7b81dfbb
AJ		 7348 /* Some of the relocations depend on the size of what field is to
7349 be relocated. But in our callers i386_immediate and i386_displacement
7350 we don't yet know the operand size (this will be set by insn
7351 matching). Hence we record the word32 relocation here,
7352 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7353 static const struct {
7354 const char *str;
cff8d58a 7355 int len;
4fa24527 7356 const enum bfd_reloc_code_real rel[2];
40fb9820 7357 const i386_operand_type types64;
f3c180ae 7358 } gotrel[] = {
8ce3d284 7359#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7360 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7361 BFD_RELOC_SIZE32 },
7362 OPERAND_TYPE_IMM32_64 },
8ce3d284 7363#endif
cff8d58a
L		 7364 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7365 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7366 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7367 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7368 BFD_RELOC_X86_64_PLT32 },
40fb9820 7369 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7370 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7371 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7372 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7373 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7374 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7375 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7376 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7377 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7378 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7379 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7380 BFD_RELOC_X86_64_TLSGD },
40fb9820 7381 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7382 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7383 _dummy_first_bfd_reloc_code_real },
40fb9820 7384 OPERAND_TYPE_NONE },
cff8d58a
L		 7385 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7386 BFD_RELOC_X86_64_TLSLD },
40fb9820 7387 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7388 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7389 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7390 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7391 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7392 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7393 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7394 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7395 _dummy_first_bfd_reloc_code_real },
40fb9820 7396 OPERAND_TYPE_NONE },
cff8d58a
L		 7397 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7398 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7399 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7400 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7401 _dummy_first_bfd_reloc_code_real },
40fb9820 7402 OPERAND_TYPE_NONE },
cff8d58a
L		 7403 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7404 _dummy_first_bfd_reloc_code_real },
40fb9820 7405 OPERAND_TYPE_NONE },
cff8d58a
L		 7406 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7407 BFD_RELOC_X86_64_GOT32 },
40fb9820 7408 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7409 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7410 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7411 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7412 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7413 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7414 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7415 };
7416 char *cp;
7417 unsigned int j;
7418
d382c579 7419#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7420 if (!IS_ELF)
7421 return NULL;
d382c579 7422#endif
718ddfc0 7423
f3c180ae 7424 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7425 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7426 return NULL;
7427
47465058 7428 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7429 {
cff8d58a 7430 int len = gotrel[j].len;
28f81592 7431 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7432 {
4fa24527 7433 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7434 {
28f81592
AM		 7435 int first, second;
7436 char *tmpbuf, *past_reloc;
f3c180ae 7437
91d6fa6a 7438 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7439
3956db08
JB		 7440 if (types)
7441 {
7442 if (flag_code != CODE_64BIT)
40fb9820
L		 7443 {
7444 types->bitfield.imm32 = 1;
7445 types->bitfield.disp32 = 1;
7446 }
3956db08
JB		 7447 else
7448 *types = gotrel[j].types64;
7449 }
7450
8fd4256d 7451 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7452 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7453
28f81592 7454 /* The length of the first part of our input line. */
f3c180ae 7455 first = cp - input_line_pointer;
28f81592
AM		 7456
7457 /* The second part goes from after the reloc token until
67c11a9b 7458 (and including) an end_of_line char or comma. */
28f81592 7459 past_reloc = cp + 1 + len;
67c11a9b
AM		 7460 cp = past_reloc;
7461 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7462 ++cp;
7463 second = cp + 1 - past_reloc;
28f81592
AM		 7464
7465 /* Allocate and copy string. The trailing NUL shouldn't
7466 be necessary, but be safe. */
1e9cc1c2 7467 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7468 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7469 if (second != 0 && *past_reloc != ' ')
7470 /* Replace the relocation token with ' ', so that
7471 errors like foo@GOTOFF1 will be detected. */
7472 tmpbuf[first++] = ' ';
af89796a
L		 7473 else
7474 /* Increment length by 1 if the relocation token is
7475 removed. */
7476 len++;
7477 if (adjust)
7478 *adjust = len;
0787a12d
AM		 7479 memcpy (tmpbuf + first, past_reloc, second);
7480 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7481 return tmpbuf;
7482 }
7483
4fa24527
JB		 7484 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7485 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7486 return NULL;
7487 }
7488 }
7489
7490 /* Might be a symbol version string. Don't as_bad here. */
7491 return NULL;
7492}
4e4f7c87 7493#endif
f3c180ae 7494
a988325c
NC		 7495#ifdef TE_PE
7496#ifdef lex_got
7497#undef lex_got
7498#endif
7499/* Parse operands of the form
7500 <symbol>@SECREL32+<nnn>
7501
7502 If we find one, set up the correct relocation in RELOC and copy the
7503 input string, minus the `@SECREL32' into a malloc'd buffer for
7504 parsing by the calling routine. Return this buffer, and if ADJUST
7505 is non-null set it to the length of the string we removed from the
34bca508
L		 7506 input line. Otherwise return NULL.
7507
a988325c
NC		 7508 This function is copied from the ELF version above adjusted for PE targets. */
7509
7510static char *
7511lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7512 int *adjust ATTRIBUTE_UNUSED,
7513 i386_operand_type *types ATTRIBUTE_UNUSED)
7514{
7515 static const struct
7516 {
7517 const char *str;
7518 int len;
7519 const enum bfd_reloc_code_real rel[2];
7520 const i386_operand_type types64;
7521 }
7522 gotrel[] =
7523 {
7524 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7525 BFD_RELOC_32_SECREL },
7526 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7527 };
7528
7529 char *cp;
7530 unsigned j;
7531
7532 for (cp = input_line_pointer; *cp != '@'; cp++)
7533 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7534 return NULL;
7535
7536 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7537 {
7538 int len = gotrel[j].len;
7539
7540 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7541 {
7542 if (gotrel[j].rel[object_64bit] != 0)
7543 {
7544 int first, second;
7545 char *tmpbuf, *past_reloc;
7546
7547 *rel = gotrel[j].rel[object_64bit];
7548 if (adjust)
7549 *adjust = len;
7550
7551 if (types)
7552 {
7553 if (flag_code != CODE_64BIT)
7554 {
7555 types->bitfield.imm32 = 1;
7556 types->bitfield.disp32 = 1;
7557 }
7558 else
7559 *types = gotrel[j].types64;
7560 }
7561
7562 /* The length of the first part of our input line. */
7563 first = cp - input_line_pointer;
7564
7565 /* The second part goes from after the reloc token until
7566 (and including) an end_of_line char or comma. */
7567 past_reloc = cp + 1 + len;
7568 cp = past_reloc;
7569 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7570 ++cp;
7571 second = cp + 1 - past_reloc;
7572
7573 /* Allocate and copy string. The trailing NUL shouldn't
7574 be necessary, but be safe. */
7575 tmpbuf = (char *) xmalloc (first + second + 2);
7576 memcpy (tmpbuf, input_line_pointer, first);
7577 if (second != 0 && *past_reloc != ' ')
7578 /* Replace the relocation token with ' ', so that
7579 errors like foo@SECLREL321 will be detected. */
7580 tmpbuf[first++] = ' ';
7581 memcpy (tmpbuf + first, past_reloc, second);
7582 tmpbuf[first + second] = '\0';
7583 return tmpbuf;
7584 }
7585
7586 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7587 gotrel[j].str, 1 << (5 + object_64bit));
7588 return NULL;
7589 }
7590 }
7591
7592 /* Might be a symbol version string. Don't as_bad here. */
7593 return NULL;
7594}
7595
7596#endif /* TE_PE */
7597
f3c180ae 7598void
e3bb37b5 7599x86_cons (expressionS *exp, int size)
f3c180ae 7600{
ee86248c
JB		 7601 intel_syntax = -intel_syntax;
7602
3c7b9c2c 7603 exp->X_md = 0;
4fa24527 7604 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7605 {
7606 /* Handle @GOTOFF and the like in an expression. */
7607 char *save;
7608 char *gotfree_input_line;
4a57f2cf 7609 int adjust = 0;
f3c180ae
AM		 7610
7611 save = input_line_pointer;
3956db08 7612 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7613 if (gotfree_input_line)
7614 input_line_pointer = gotfree_input_line;
7615
7616 expression (exp);
7617
7618 if (gotfree_input_line)
7619 {
7620 /* expression () has merrily parsed up to the end of line,
7621 or a comma - in the wrong buffer. Transfer how far
7622 input_line_pointer has moved to the right buffer. */
7623 input_line_pointer = (save
7624 + (input_line_pointer - gotfree_input_line)
7625 + adjust);
7626 free (gotfree_input_line);
3992d3b7
AM		 7627 if (exp->X_op == O_constant
7628 || exp->X_op == O_absent
7629 || exp->X_op == O_illegal
0398aac5 7630 || exp->X_op == O_register
3992d3b7
AM		 7631 || exp->X_op == O_big)
7632 {
7633 char c = *input_line_pointer;
7634 *input_line_pointer = 0;
7635 as_bad (_("missing or invalid expression `%s'"), save);
7636 *input_line_pointer = c;
7637 }
f3c180ae
AM		 7638 }
7639 }
7640 else
7641 expression (exp);
ee86248c
JB		 7642
7643 intel_syntax = -intel_syntax;
7644
7645 if (intel_syntax)
7646 i386_intel_simplify (exp);
f3c180ae 7647}
f3c180ae 7648
9f32dd5b
L		 7649static void
7650signed_cons (int size)
6482c264 7651{
d182319b
JB		 7652 if (flag_code == CODE_64BIT)
7653 cons_sign = 1;
7654 cons (size);
7655 cons_sign = -1;
6482c264
NC		 7656}
7657
d182319b 7658#ifdef TE_PE
6482c264 7659static void
7016a5d5 7660pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7661{
7662 expressionS exp;
7663
7664 do
7665 {
7666 expression (&exp);
7667 if (exp.X_op == O_symbol)
7668 exp.X_op = O_secrel;
7669
7670 emit_expr (&exp, 4);
7671 }
7672 while (*input_line_pointer++ == ',');
7673
7674 input_line_pointer--;
7675 demand_empty_rest_of_line ();
7676}
6482c264
NC		 7677#endif
7678
43234a1e
L		 7679/* Handle Vector operations. */
7680
7681static char *
7682check_VecOperations (char *op_string, char *op_end)
7683{
7684 const reg_entry *mask;
7685 const char *saved;
7686 char *end_op;
7687
7688 while (*op_string
7689 && (op_end == NULL || op_string < op_end))
7690 {
7691 saved = op_string;
7692 if (*op_string == '{')
7693 {
7694 op_string++;
7695
7696 /* Check broadcasts. */
7697 if (strncmp (op_string, "1to", 3) == 0)
7698 {
7699 int bcst_type;
7700
7701 if (i.broadcast)
7702 goto duplicated_vec_op;
7703
7704 op_string += 3;
7705 if (*op_string == '8')
7706 bcst_type = BROADCAST_1TO8;
7707 else if (*op_string == '1'
7708 && *(op_string+1) == '6')
7709 {
7710 bcst_type = BROADCAST_1TO16;
7711 op_string++;
7712 }
7713 else
7714 {
7715 as_bad (_("Unsupported broadcast: `%s'"), saved);
7716 return NULL;
7717 }
7718 op_string++;
7719
7720 broadcast_op.type = bcst_type;
7721 broadcast_op.operand = this_operand;
7722 i.broadcast = &broadcast_op;
7723 }
7724 /* Check masking operation. */
7725 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7726 {
7727 /* k0 can't be used for write mask. */
7728 if (mask->reg_num == 0)
7729 {
7730 as_bad (_("`%s' can't be used for write mask"),
7731 op_string);
7732 return NULL;
7733 }
7734
7735 if (!i.mask)
7736 {
7737 mask_op.mask = mask;
7738 mask_op.zeroing = 0;
7739 mask_op.operand = this_operand;
7740 i.mask = &mask_op;
7741 }
7742 else
7743 {
7744 if (i.mask->mask)
7745 goto duplicated_vec_op;
7746
7747 i.mask->mask = mask;
7748
7749 /* Only "{z}" is allowed here. No need to check
7750 zeroing mask explicitly. */
7751 if (i.mask->operand != this_operand)
7752 {
7753 as_bad (_("invalid write mask `%s'"), saved);
7754 return NULL;
7755 }
7756 }
7757
7758 op_string = end_op;
7759 }
7760 /* Check zeroing-flag for masking operation. */
7761 else if (*op_string == 'z')
7762 {
7763 if (!i.mask)
7764 {
7765 mask_op.mask = NULL;
7766 mask_op.zeroing = 1;
7767 mask_op.operand = this_operand;
7768 i.mask = &mask_op;
7769 }
7770 else
7771 {
7772 if (i.mask->zeroing)
7773 {
7774 duplicated_vec_op:
7775 as_bad (_("duplicated `%s'"), saved);
7776 return NULL;
7777 }
7778
7779 i.mask->zeroing = 1;
7780
7781 /* Only "{%k}" is allowed here. No need to check mask
7782 register explicitly. */
7783 if (i.mask->operand != this_operand)
7784 {
7785 as_bad (_("invalid zeroing-masking `%s'"),
7786 saved);
7787 return NULL;
7788 }
7789 }
7790
7791 op_string++;
7792 }
7793 else
7794 goto unknown_vec_op;
7795
7796 if (*op_string != '}')
7797 {
7798 as_bad (_("missing `}' in `%s'"), saved);
7799 return NULL;
7800 }
7801 op_string++;
7802 continue;
7803 }
7804 unknown_vec_op:
7805 /* We don't know this one. */
7806 as_bad (_("unknown vector operation: `%s'"), saved);
7807 return NULL;
7808 }
7809
7810 return op_string;
7811}
7812
252b5132 7813static int
70e41ade 7814i386_immediate (char *imm_start)
252b5132
RH		 7815{
7816 char *save_input_line_pointer;
f3c180ae 7817 char *gotfree_input_line;
252b5132 7818 segT exp_seg = 0;
47926f60 7819 expressionS *exp;
40fb9820
L		 7820 i386_operand_type types;
7821
0dfbf9d7 7822 operand_type_set (&types, ~0);
252b5132
RH		 7823
7824 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7825 {
31b2323c
L		 7826 as_bad (_("at most %d immediate operands are allowed"),
7827 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7828 return 0;
7829 }
7830
7831 exp = &im_expressions[i.imm_operands++];
520dc8e8 7832 i.op[this_operand].imms = exp;
252b5132
RH		 7833
7834 if (is_space_char (*imm_start))
7835 ++imm_start;
7836
7837 save_input_line_pointer = input_line_pointer;
7838 input_line_pointer = imm_start;
7839
3956db08 7840 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7841 if (gotfree_input_line)
7842 input_line_pointer = gotfree_input_line;
252b5132
RH		 7843
7844 exp_seg = expression (exp);
7845
83183c0c 7846 SKIP_WHITESPACE ();
43234a1e
L		 7847
7848 /* Handle vector operations. */
7849 if (*input_line_pointer == '{')
7850 {
7851 input_line_pointer = check_VecOperations (input_line_pointer,
7852 NULL);
7853 if (input_line_pointer == NULL)
7854 return 0;
7855 }
7856
252b5132 7857 if (*input_line_pointer)
f3c180ae 7858 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7859
7860 input_line_pointer = save_input_line_pointer;
f3c180ae 7861 if (gotfree_input_line)
ee86248c
JB		 7862 {
7863 free (gotfree_input_line);
7864
7865 if (exp->X_op == O_constant || exp->X_op == O_register)
7866 exp->X_op = O_illegal;
7867 }
7868
7869 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7870}
252b5132 7871
ee86248c
JB		 7872static int
7873i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7874 i386_operand_type types, const char *imm_start)
7875{
7876 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7877 {
313c53d1
L		 7878 if (imm_start)
7879 as_bad (_("missing or invalid immediate expression `%s'"),
7880 imm_start);
3992d3b7 7881 return 0;
252b5132 7882 }
3e73aa7c 7883 else if (exp->X_op == O_constant)
252b5132 7884 {
47926f60 7885 /* Size it properly later. */
40fb9820 7886 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7887 /* If not 64bit, sign extend val. */
7888 if (flag_code != CODE_64BIT
4eed87de
AM		 7889 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7890 exp->X_add_number
7891 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7892 }
4c63da97 7893#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7894 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7895 && exp_seg != absolute_section
47926f60 7896 && exp_seg != text_section
24eab124
AM		 7897 && exp_seg != data_section
7898 && exp_seg != bss_section
7899 && exp_seg != undefined_section
f86103b7 7900 && !bfd_is_com_section (exp_seg))
252b5132 7901 {
d0b47220 7902 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 7903 return 0;
7904 }
7905#endif
bb8f5920
L		 7906 else if (!intel_syntax && exp->X_op == O_register)
7907 {
313c53d1
L		 7908 if (imm_start)
7909 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 7910 return 0;
7911 }
252b5132
RH		 7912 else
7913 {
7914 /* This is an address. The size of the address will be
24eab124 7915 determined later, depending on destination register,
3e73aa7c 7916 suffix, or the default for the section. */
40fb9820
L		 7917 i.types[this_operand].bitfield.imm8 = 1;
7918 i.types[this_operand].bitfield.imm16 = 1;
7919 i.types[this_operand].bitfield.imm32 = 1;
7920 i.types[this_operand].bitfield.imm32s = 1;
7921 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 7922 i.types[this_operand] = operand_type_and (i.types[this_operand],
7923 types);
252b5132
RH		 7924 }
7925
7926 return 1;
7927}
7928
551c1ca1 7929static char *
e3bb37b5 7930i386_scale (char *scale)
252b5132 7931{
551c1ca1
AM		 7932 offsetT val;
7933 char *save = input_line_pointer;
252b5132 7934
551c1ca1
AM		 7935 input_line_pointer = scale;
7936 val = get_absolute_expression ();
7937
7938 switch (val)
252b5132 7939 {
551c1ca1 7940 case 1:
252b5132
RH		 7941 i.log2_scale_factor = 0;
7942 break;
551c1ca1 7943 case 2:
252b5132
RH		 7944 i.log2_scale_factor = 1;
7945 break;
551c1ca1 7946 case 4:
252b5132
RH		 7947 i.log2_scale_factor = 2;
7948 break;
551c1ca1 7949 case 8:
252b5132
RH		 7950 i.log2_scale_factor = 3;
7951 break;
7952 default:
a724f0f4
JB		 7953 {
7954 char sep = *input_line_pointer;
7955
7956 *input_line_pointer = '\0';
7957 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7958 scale);
7959 *input_line_pointer = sep;
7960 input_line_pointer = save;
7961 return NULL;
7962 }
252b5132 7963 }
29b0f896 7964 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 7965 {
7966 as_warn (_("scale factor of %d without an index register"),
24eab124 7967 1 << i.log2_scale_factor);
252b5132 7968 i.log2_scale_factor = 0;
252b5132 7969 }
551c1ca1
AM		 7970 scale = input_line_pointer;
7971 input_line_pointer = save;
7972 return scale;
252b5132
RH		 7973}
7974
252b5132 7975static int
e3bb37b5 7976i386_displacement (char *disp_start, char *disp_end)
252b5132 7977{
29b0f896 7978 expressionS *exp;
252b5132
RH		 7979 segT exp_seg = 0;
7980 char *save_input_line_pointer;
f3c180ae 7981 char *gotfree_input_line;
40fb9820
L		 7982 int override;
7983 i386_operand_type bigdisp, types = anydisp;
3992d3b7 7984 int ret;
252b5132 7985
31b2323c
L		 7986 if (i.disp_operands == MAX_MEMORY_OPERANDS)
7987 {
7988 as_bad (_("at most %d displacement operands are allowed"),
7989 MAX_MEMORY_OPERANDS);
7990 return 0;
7991 }
7992
0dfbf9d7 7993 operand_type_set (&bigdisp, 0);
40fb9820
L		 7994 if ((i.types[this_operand].bitfield.jumpabsolute)
7995 || (!current_templates->start->opcode_modifier.jump
7996 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 7997 {
40fb9820 7998 bigdisp.bitfield.disp32 = 1;
e05278af 7999 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8000 if (flag_code == CODE_64BIT)
8001 {
8002 if (!override)
8003 {
8004 bigdisp.bitfield.disp32s = 1;
8005 bigdisp.bitfield.disp64 = 1;
8006 }
8007 }
8008 else if ((flag_code == CODE_16BIT) ^ override)
8009 {
8010 bigdisp.bitfield.disp32 = 0;
8011 bigdisp.bitfield.disp16 = 1;
8012 }
e05278af
JB		 8013 }
8014 else
8015 {
8016 /* For PC-relative branches, the width of the displacement
8017 is dependent upon data size, not address size. */
e05278af 8018 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8019 if (flag_code == CODE_64BIT)
8020 {
8021 if (override || i.suffix == WORD_MNEM_SUFFIX)
8022 bigdisp.bitfield.disp16 = 1;
8023 else
8024 {
8025 bigdisp.bitfield.disp32 = 1;
8026 bigdisp.bitfield.disp32s = 1;
8027 }
8028 }
8029 else
e05278af
JB		 8030 {
8031 if (!override)
8032 override = (i.suffix == (flag_code != CODE_16BIT
8033 ? WORD_MNEM_SUFFIX
8034 : LONG_MNEM_SUFFIX));
40fb9820
L		 8035 bigdisp.bitfield.disp32 = 1;
8036 if ((flag_code == CODE_16BIT) ^ override)
8037 {
8038 bigdisp.bitfield.disp32 = 0;
8039 bigdisp.bitfield.disp16 = 1;
8040 }
e05278af 8041 }
e05278af 8042 }
c6fb90c8
L		 8043 i.types[this_operand] = operand_type_or (i.types[this_operand],
8044 bigdisp);
252b5132
RH		 8045
8046 exp = &disp_expressions[i.disp_operands];
520dc8e8 8047 i.op[this_operand].disps = exp;
252b5132
RH		 8048 i.disp_operands++;
8049 save_input_line_pointer = input_line_pointer;
8050 input_line_pointer = disp_start;
8051 END_STRING_AND_SAVE (disp_end);
8052
8053#ifndef GCC_ASM_O_HACK
8054#define GCC_ASM_O_HACK 0
8055#endif
8056#if GCC_ASM_O_HACK
8057 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8058 if (i.types[this_operand].bitfield.baseIndex
24eab124 8059 && displacement_string_end[-1] == '+')
252b5132
RH		 8060 {
8061 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8062 constraint within gcc asm statements.
8063 For instance:
8064
8065 #define _set_tssldt_desc(n,addr,limit,type) \
8066 __asm__ __volatile__ ( \
8067 "movw %w2,%0\n\t" \
8068 "movw %w1,2+%0\n\t" \
8069 "rorl $16,%1\n\t" \
8070 "movb %b1,4+%0\n\t" \
8071 "movb %4,5+%0\n\t" \
8072 "movb $0,6+%0\n\t" \
8073 "movb %h1,7+%0\n\t" \
8074 "rorl $16,%1" \
8075 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8076
8077 This works great except that the output assembler ends
8078 up looking a bit weird if it turns out that there is
8079 no offset. You end up producing code that looks like:
8080
8081 #APP
8082 movw $235,(%eax)
8083 movw %dx,2+(%eax)
8084 rorl $16,%edx
8085 movb %dl,4+(%eax)
8086 movb $137,5+(%eax)
8087 movb $0,6+(%eax)
8088 movb %dh,7+(%eax)
8089 rorl $16,%edx
8090 #NO_APP
8091
47926f60 8092 So here we provide the missing zero. */
24eab124
AM		 8093
8094 *displacement_string_end = '0';
252b5132
RH		 8095 }
8096#endif
3956db08 8097 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8098 if (gotfree_input_line)
8099 input_line_pointer = gotfree_input_line;
252b5132 8100
24eab124 8101 exp_seg = expression (exp);
252b5132 8102
636c26b0
AM		 8103 SKIP_WHITESPACE ();
8104 if (*input_line_pointer)
8105 as_bad (_("junk `%s' after expression"), input_line_pointer);
8106#if GCC_ASM_O_HACK
8107 RESTORE_END_STRING (disp_end + 1);
8108#endif
636c26b0 8109 input_line_pointer = save_input_line_pointer;
636c26b0 8110 if (gotfree_input_line)
ee86248c
JB		 8111 {
8112 free (gotfree_input_line);
8113
8114 if (exp->X_op == O_constant || exp->X_op == O_register)
8115 exp->X_op = O_illegal;
8116 }
8117
8118 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8119
8120 RESTORE_END_STRING (disp_end);
8121
8122 return ret;
8123}
8124
8125static int
8126i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8127 i386_operand_type types, const char *disp_start)
8128{
8129 i386_operand_type bigdisp;
8130 int ret = 1;
636c26b0 8131
24eab124
AM		 8132 /* We do this to make sure that the section symbol is in
8133 the symbol table. We will ultimately change the relocation
47926f60 8134 to be relative to the beginning of the section. */
1ae12ab7 8135 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8136 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8137 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8138 {
636c26b0 8139 if (exp->X_op != O_symbol)
3992d3b7 8140 goto inv_disp;
636c26b0 8141
e5cb08ac 8142 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8143 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8144 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8145 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8146 exp->X_op = O_subtract;
8147 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8148 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8149 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8150 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8151 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8152 else
29b0f896 8153 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8154 }
252b5132 8155
3992d3b7
AM		 8156 else if (exp->X_op == O_absent
8157 || exp->X_op == O_illegal
ee86248c 8158 || exp->X_op == O_big)
2daf4fd8 8159 {
3992d3b7
AM		 8160 inv_disp:
8161 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8162 disp_start);
3992d3b7 8163 ret = 0;
2daf4fd8
AM		 8164 }
8165
0e1147d9
L		 8166 else if (flag_code == CODE_64BIT
8167 && !i.prefix[ADDR_PREFIX]
8168 && exp->X_op == O_constant)
8169 {
8170 /* Since displacement is signed extended to 64bit, don't allow
8171 disp32 and turn off disp32s if they are out of range. */
8172 i.types[this_operand].bitfield.disp32 = 0;
8173 if (!fits_in_signed_long (exp->X_add_number))
8174 {
8175 i.types[this_operand].bitfield.disp32s = 0;
8176 if (i.types[this_operand].bitfield.baseindex)
8177 {
8178 as_bad (_("0x%lx out range of signed 32bit displacement"),
8179 (long) exp->X_add_number);
8180 ret = 0;
8181 }
8182 }
8183 }
8184
4c63da97 8185#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8186 else if (exp->X_op != O_constant
8187 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8188 && exp_seg != absolute_section
8189 && exp_seg != text_section
8190 && exp_seg != data_section
8191 && exp_seg != bss_section
8192 && exp_seg != undefined_section
8193 && !bfd_is_com_section (exp_seg))
24eab124 8194 {
d0b47220 8195 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8196 ret = 0;
24eab124 8197 }
252b5132 8198#endif
3956db08 8199
40fb9820
L		 8200 /* Check if this is a displacement only operand. */
8201 bigdisp = i.types[this_operand];
8202 bigdisp.bitfield.disp8 = 0;
8203 bigdisp.bitfield.disp16 = 0;
8204 bigdisp.bitfield.disp32 = 0;
8205 bigdisp.bitfield.disp32s = 0;
8206 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8207 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8208 i.types[this_operand] = operand_type_and (i.types[this_operand],
8209 types);
3956db08 8210
3992d3b7 8211 return ret;
252b5132
RH		 8212}
8213
eecb386c 8214/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8215 Return 1 on success, 0 on a failure. */
8216
252b5132 8217static int
e3bb37b5 8218i386_index_check (const char *operand_string)
252b5132 8219{
fc0763e6 8220 const char *kind = "base/index";
be05d201
L		 8221 enum flag_code addr_mode;
8222
8223 if (i.prefix[ADDR_PREFIX])
8224 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8225 else
8226 {
8227 addr_mode = flag_code;
8228
24eab124 8229#if INFER_ADDR_PREFIX
be05d201
L		 8230 if (i.mem_operands == 0)
8231 {
8232 /* Infer address prefix from the first memory operand. */
8233 const reg_entry *addr_reg = i.base_reg;
8234
8235 if (addr_reg == NULL)
8236 addr_reg = i.index_reg;
eecb386c 8237
be05d201
L		 8238 if (addr_reg)
8239 {
8240 if (addr_reg->reg_num == RegEip
8241 || addr_reg->reg_num == RegEiz
8242 || addr_reg->reg_type.bitfield.reg32)
8243 addr_mode = CODE_32BIT;
8244 else if (flag_code != CODE_64BIT
8245 && addr_reg->reg_type.bitfield.reg16)
8246 addr_mode = CODE_16BIT;
8247
8248 if (addr_mode != flag_code)
8249 {
8250 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8251 i.prefixes += 1;
8252 /* Change the size of any displacement too. At most one
8253 of Disp16 or Disp32 is set.
8254 FIXME. There doesn't seem to be any real need for
8255 separate Disp16 and Disp32 flags. The same goes for
8256 Imm16 and Imm32. Removing them would probably clean
8257 up the code quite a lot. */
8258 if (flag_code != CODE_64BIT
8259 && (i.types[this_operand].bitfield.disp16
8260 || i.types[this_operand].bitfield.disp32))
8261 i.types[this_operand]
8262 = operand_type_xor (i.types[this_operand], disp16_32);
8263 }
8264 }
8265 }
24eab124 8266#endif
be05d201
L		 8267 }
8268
fc0763e6
JB		 8269 if (current_templates->start->opcode_modifier.isstring
8270 && !current_templates->start->opcode_modifier.immext
8271 && (current_templates->end[-1].opcode_modifier.isstring
8272 || i.mem_operands))
8273 {
8274 /* Memory operands of string insns are special in that they only allow
8275 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8276 const reg_entry *expected_reg;
8277 static const char *di_si[][2] =
8278 {
8279 { "esi", "edi" },
8280 { "si", "di" },
8281 { "rsi", "rdi" }
8282 };
8283 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8284
8285 kind = "string address";
8286
8287 if (current_templates->start->opcode_modifier.w)
8288 {
8289 i386_operand_type type = current_templates->end[-1].operand_types[0];
8290
8291 if (!type.bitfield.baseindex
8292 || ((!i.mem_operands != !intel_syntax)
8293 && current_templates->end[-1].operand_types[1]
8294 .bitfield.baseindex))
8295 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8296 expected_reg = hash_find (reg_hash,
8297 di_si[addr_mode][type.bitfield.esseg]);
8298
fc0763e6
JB		 8299 }
8300 else
be05d201 8301 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8302
be05d201
L		 8303 if (i.base_reg != expected_reg
8304 || i.index_reg
fc0763e6 8305 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8306 {
be05d201
L		 8307 /* The second memory operand must have the same size as
8308 the first one. */
8309 if (i.mem_operands
8310 && i.base_reg
8311 && !((addr_mode == CODE_64BIT
8312 && i.base_reg->reg_type.bitfield.reg64)
8313 || (addr_mode == CODE_32BIT
8314 ? i.base_reg->reg_type.bitfield.reg32
8315 : i.base_reg->reg_type.bitfield.reg16)))
8316 goto bad_address;
8317
fc0763e6
JB		 8318 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8319 operand_string,
8320 intel_syntax ? '[' : '(',
8321 register_prefix,
be05d201 8322 expected_reg->reg_name,
fc0763e6 8323 intel_syntax ? ']' : ')');
be05d201 8324 return 1;
fc0763e6 8325 }
be05d201
L		 8326 else
8327 return 1;
8328
8329bad_address:
8330 as_bad (_("`%s' is not a valid %s expression"),
8331 operand_string, kind);
8332 return 0;
3e73aa7c
JH		 8333 }
8334 else
8335 {
be05d201
L		 8336 if (addr_mode != CODE_16BIT)
8337 {
8338 /* 32-bit/64-bit checks. */
8339 if ((i.base_reg
8340 && (addr_mode == CODE_64BIT
8341 ? !i.base_reg->reg_type.bitfield.reg64
8342 : !i.base_reg->reg_type.bitfield.reg32)
8343 && (i.index_reg
8344 || (i.base_reg->reg_num
8345 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8346 || (i.index_reg
8347 && !i.index_reg->reg_type.bitfield.regxmm
8348 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8349 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8350 && ((addr_mode == CODE_64BIT
8351 ? !(i.index_reg->reg_type.bitfield.reg64
8352 || i.index_reg->reg_num == RegRiz)
8353 : !(i.index_reg->reg_type.bitfield.reg32
8354 || i.index_reg->reg_num == RegEiz))
8355 || !i.index_reg->reg_type.bitfield.baseindex)))
8356 goto bad_address;
8357 }
8358 else
3e73aa7c 8359 {
be05d201 8360 /* 16-bit checks. */
3e73aa7c 8361 if ((i.base_reg
40fb9820
L		 8362 && (!i.base_reg->reg_type.bitfield.reg16
8363 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8364 || (i.index_reg
40fb9820
L		 8365 && (!i.index_reg->reg_type.bitfield.reg16
8366 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8367 || !(i.base_reg
8368 && i.base_reg->reg_num < 6
8369 && i.index_reg->reg_num >= 6
8370 && i.log2_scale_factor == 0))))
be05d201 8371 goto bad_address;
3e73aa7c
JH		 8372 }
8373 }
be05d201 8374 return 1;
24eab124 8375}
252b5132 8376
43234a1e
L		 8377/* Handle vector immediates. */
8378
8379static int
8380RC_SAE_immediate (const char *imm_start)
8381{
8382 unsigned int match_found, j;
8383 const char *pstr = imm_start;
8384 expressionS *exp;
8385
8386 if (*pstr != '{')
8387 return 0;
8388
8389 pstr++;
8390 match_found = 0;
8391 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8392 {
8393 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8394 {
8395 if (!i.rounding)
8396 {
8397 rc_op.type = RC_NamesTable[j].type;
8398 rc_op.operand = this_operand;
8399 i.rounding = &rc_op;
8400 }
8401 else
8402 {
8403 as_bad (_("duplicated `%s'"), imm_start);
8404 return 0;
8405 }
8406 pstr += RC_NamesTable[j].len;
8407 match_found = 1;
8408 break;
8409 }
8410 }
8411 if (!match_found)
8412 return 0;
8413
8414 if (*pstr++ != '}')
8415 {
8416 as_bad (_("Missing '}': '%s'"), imm_start);
8417 return 0;
8418 }
8419 /* RC/SAE immediate string should contain nothing more. */;
8420 if (*pstr != 0)
8421 {
8422 as_bad (_("Junk after '}': '%s'"), imm_start);
8423 return 0;
8424 }
8425
8426 exp = &im_expressions[i.imm_operands++];
8427 i.op[this_operand].imms = exp;
8428
8429 exp->X_op = O_constant;
8430 exp->X_add_number = 0;
8431 exp->X_add_symbol = (symbolS *) 0;
8432 exp->X_op_symbol = (symbolS *) 0;
8433
8434 i.types[this_operand].bitfield.imm8 = 1;
8435 return 1;
8436}
8437
fc0763e6 8438/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8439 on error. */
252b5132 8440
252b5132 8441static int
a7619375 8442i386_att_operand (char *operand_string)
252b5132 8443{
af6bdddf
AM		 8444 const reg_entry *r;
8445 char *end_op;
24eab124 8446 char *op_string = operand_string;
252b5132 8447
24eab124 8448 if (is_space_char (*op_string))
252b5132
RH		 8449 ++op_string;
8450
24eab124 8451 /* We check for an absolute prefix (differentiating,
47926f60 8452 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8453 if (*op_string == ABSOLUTE_PREFIX)
8454 {
8455 ++op_string;
8456 if (is_space_char (*op_string))
8457 ++op_string;
40fb9820 8458 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8459 }
252b5132 8460
47926f60 8461 /* Check if operand is a register. */
4d1bb795 8462 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8463 {
40fb9820
L		 8464 i386_operand_type temp;
8465
24eab124
AM		 8466 /* Check for a segment override by searching for ':' after a
8467 segment register. */
8468 op_string = end_op;
8469 if (is_space_char (*op_string))
8470 ++op_string;
40fb9820
L		 8471 if (*op_string == ':'
8472 && (r->reg_type.bitfield.sreg2
8473 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8474 {
8475 switch (r->reg_num)
8476 {
8477 case 0:
8478 i.seg[i.mem_operands] = &es;
8479 break;
8480 case 1:
8481 i.seg[i.mem_operands] = &cs;
8482 break;
8483 case 2:
8484 i.seg[i.mem_operands] = &ss;
8485 break;
8486 case 3:
8487 i.seg[i.mem_operands] = &ds;
8488 break;
8489 case 4:
8490 i.seg[i.mem_operands] = &fs;
8491 break;
8492 case 5:
8493 i.seg[i.mem_operands] = &gs;
8494 break;
8495 }
252b5132 8496
24eab124 8497 /* Skip the ':' and whitespace. */
252b5132
RH		 8498 ++op_string;
8499 if (is_space_char (*op_string))
24eab124 8500 ++op_string;
252b5132 8501
24eab124
AM		 8502 if (!is_digit_char (*op_string)
8503 && !is_identifier_char (*op_string)
8504 && *op_string != '('
8505 && *op_string != ABSOLUTE_PREFIX)
8506 {
8507 as_bad (_("bad memory operand `%s'"), op_string);
8508 return 0;
8509 }
47926f60 8510 /* Handle case of %es:*foo. */
24eab124
AM		 8511 if (*op_string == ABSOLUTE_PREFIX)
8512 {
8513 ++op_string;
8514 if (is_space_char (*op_string))
8515 ++op_string;
40fb9820 8516 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8517 }
8518 goto do_memory_reference;
8519 }
43234a1e
L		 8520
8521 /* Handle vector operations. */
8522 if (*op_string == '{')
8523 {
8524 op_string = check_VecOperations (op_string, NULL);
8525 if (op_string == NULL)
8526 return 0;
8527 }
8528
24eab124
AM		 8529 if (*op_string)
8530 {
d0b47220 8531 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8532 return 0;
8533 }
40fb9820
L		 8534 temp = r->reg_type;
8535 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8536 i.types[this_operand] = operand_type_or (i.types[this_operand],
8537 temp);
7d5e4556 8538 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8539 i.op[this_operand].regs = r;
24eab124
AM		 8540 i.reg_operands++;
8541 }
af6bdddf
AM		 8542 else if (*op_string == REGISTER_PREFIX)
8543 {
8544 as_bad (_("bad register name `%s'"), op_string);
8545 return 0;
8546 }
24eab124 8547 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8548 {
24eab124 8549 ++op_string;
40fb9820 8550 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8551 {
d0b47220 8552 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8553 return 0;
8554 }
8555 if (!i386_immediate (op_string))
8556 return 0;
8557 }
43234a1e
L		 8558 else if (RC_SAE_immediate (operand_string))
8559 {
8560 /* If it is a RC or SAE immediate, do nothing. */
8561 ;
8562 }
24eab124
AM		 8563 else if (is_digit_char (*op_string)
8564 || is_identifier_char (*op_string)
e5cb08ac 8565 || *op_string == '(')
24eab124 8566 {
47926f60 8567 /* This is a memory reference of some sort. */
af6bdddf 8568 char *base_string;
252b5132 8569
47926f60 8570 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8571 char *displacement_string_start;
8572 char *displacement_string_end;
43234a1e 8573 char *vop_start;
252b5132 8574
24eab124 8575 do_memory_reference:
24eab124 8576 if ((i.mem_operands == 1
40fb9820 8577 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8578 || i.mem_operands == 2)
8579 {
8580 as_bad (_("too many memory references for `%s'"),
8581 current_templates->start->name);
8582 return 0;
8583 }
252b5132 8584
24eab124
AM		 8585 /* Check for base index form. We detect the base index form by
8586 looking for an ')' at the end of the operand, searching
8587 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8588 after the '('. */
af6bdddf 8589 base_string = op_string + strlen (op_string);
c3332e24 8590
43234a1e
L		 8591 /* Handle vector operations. */
8592 vop_start = strchr (op_string, '{');
8593 if (vop_start && vop_start < base_string)
8594 {
8595 if (check_VecOperations (vop_start, base_string) == NULL)
8596 return 0;
8597 base_string = vop_start;
8598 }
8599
af6bdddf
AM		 8600 --base_string;
8601 if (is_space_char (*base_string))
8602 --base_string;
252b5132 8603
47926f60 8604 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8605 displacement_string_start = op_string;
8606 displacement_string_end = base_string + 1;
252b5132 8607
24eab124
AM		 8608 if (*base_string == ')')
8609 {
af6bdddf 8610 char *temp_string;
24eab124
AM		 8611 unsigned int parens_balanced = 1;
8612 /* We've already checked that the number of left & right ()'s are
47926f60 8613 equal, so this loop will not be infinite. */
24eab124
AM		 8614 do
8615 {
8616 base_string--;
8617 if (*base_string == ')')
8618 parens_balanced++;
8619 if (*base_string == '(')
8620 parens_balanced--;
8621 }
8622 while (parens_balanced);
c3332e24 8623
af6bdddf 8624 temp_string = base_string;
c3332e24 8625
24eab124 8626 /* Skip past '(' and whitespace. */
252b5132
RH		 8627 ++base_string;
8628 if (is_space_char (*base_string))
24eab124 8629 ++base_string;
252b5132 8630
af6bdddf 8631 if (*base_string == ','
4eed87de
AM		 8632 || ((i.base_reg = parse_register (base_string, &end_op))
8633 != NULL))
252b5132 8634 {
af6bdddf 8635 displacement_string_end = temp_string;
252b5132 8636
40fb9820 8637 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8638
af6bdddf 8639 if (i.base_reg)
24eab124 8640 {
24eab124
AM		 8641 base_string = end_op;
8642 if (is_space_char (*base_string))
8643 ++base_string;
af6bdddf
AM		 8644 }
8645
8646 /* There may be an index reg or scale factor here. */
8647 if (*base_string == ',')
8648 {
8649 ++base_string;
8650 if (is_space_char (*base_string))
8651 ++base_string;
8652
4eed87de
AM		 8653 if ((i.index_reg = parse_register (base_string, &end_op))
8654 != NULL)
24eab124 8655 {
af6bdddf 8656 base_string = end_op;
24eab124
AM		 8657 if (is_space_char (*base_string))
8658 ++base_string;
af6bdddf
AM		 8659 if (*base_string == ',')
8660 {
8661 ++base_string;
8662 if (is_space_char (*base_string))
8663 ++base_string;
8664 }
e5cb08ac 8665 else if (*base_string != ')')
af6bdddf 8666 {
4eed87de
AM		 8667 as_bad (_("expecting `,' or `)' "
8668 "after index register in `%s'"),
af6bdddf
AM		 8669 operand_string);
8670 return 0;
8671 }
24eab124 8672 }
af6bdddf 8673 else if (*base_string == REGISTER_PREFIX)
24eab124 8674 {
f76bf5e0
L		 8675 end_op = strchr (base_string, ',');
8676 if (end_op)
8677 *end_op = '\0';
af6bdddf 8678 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8679 return 0;
8680 }
252b5132 8681
47926f60 8682 /* Check for scale factor. */
551c1ca1 8683 if (*base_string != ')')
af6bdddf 8684 {
551c1ca1
AM		 8685 char *end_scale = i386_scale (base_string);
8686
8687 if (!end_scale)
af6bdddf 8688 return 0;
24eab124 8689
551c1ca1 8690 base_string = end_scale;
af6bdddf
AM		 8691 if (is_space_char (*base_string))
8692 ++base_string;
8693 if (*base_string != ')')
8694 {
4eed87de
AM		 8695 as_bad (_("expecting `)' "
8696 "after scale factor in `%s'"),
af6bdddf
AM		 8697 operand_string);
8698 return 0;
8699 }
8700 }
8701 else if (!i.index_reg)
24eab124 8702 {
4eed87de
AM		 8703 as_bad (_("expecting index register or scale factor "
8704 "after `,'; got '%c'"),
af6bdddf 8705 *base_string);
24eab124
AM		 8706 return 0;
8707 }
8708 }
af6bdddf 8709 else if (*base_string != ')')
24eab124 8710 {
4eed87de
AM		 8711 as_bad (_("expecting `,' or `)' "
8712 "after base register in `%s'"),
af6bdddf 8713 operand_string);
24eab124
AM		 8714 return 0;
8715 }
c3332e24 8716 }
af6bdddf 8717 else if (*base_string == REGISTER_PREFIX)
c3332e24 8718 {
f76bf5e0
L		 8719 end_op = strchr (base_string, ',');
8720 if (end_op)
8721 *end_op = '\0';
af6bdddf 8722 as_bad (_("bad register name `%s'"), base_string);
24eab124 8723 return 0;
c3332e24 8724 }
24eab124
AM		 8725 }
8726
8727 /* If there's an expression beginning the operand, parse it,
8728 assuming displacement_string_start and
8729 displacement_string_end are meaningful. */
8730 if (displacement_string_start != displacement_string_end)
8731 {
8732 if (!i386_displacement (displacement_string_start,
8733 displacement_string_end))
8734 return 0;
8735 }
8736
8737 /* Special case for (%dx) while doing input/output op. */
8738 if (i.base_reg
0dfbf9d7
L		 8739 && operand_type_equal (&i.base_reg->reg_type,
8740 &reg16_inoutportreg)
24eab124
AM		 8741 && i.index_reg == 0
8742 && i.log2_scale_factor == 0
8743 && i.seg[i.mem_operands] == 0
40fb9820 8744 && !operand_type_check (i.types[this_operand], disp))
24eab124 8745 {
65da13b5 8746 i.types[this_operand] = inoutportreg;
24eab124
AM		 8747 return 1;
8748 }
8749
eecb386c
AM		 8750 if (i386_index_check (operand_string) == 0)
8751 return 0;
5c07affc 8752 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8753 i.mem_operands++;
8754 }
8755 else
ce8a8b2f
AM		 8756 {
8757 /* It's not a memory operand; argh! */
24eab124
AM		 8758 as_bad (_("invalid char %s beginning operand %d `%s'"),
8759 output_invalid (*op_string),
8760 this_operand + 1,
8761 op_string);
8762 return 0;
8763 }
47926f60 8764 return 1; /* Normal return. */
252b5132
RH		 8765}
8766\f
fa94de6b
RM		 8767/* Calculate the maximum variable size (i.e., excluding fr_fix)
8768 that an rs_machine_dependent frag may reach. */
8769
8770unsigned int
8771i386_frag_max_var (fragS *frag)
8772{
8773 /* The only relaxable frags are for jumps.
8774 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8775 gas_assert (frag->fr_type == rs_machine_dependent);
8776 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8777}
8778
ee7fcc42
AM		 8779/* md_estimate_size_before_relax()
8780
8781 Called just before relax() for rs_machine_dependent frags. The x86
8782 assembler uses these frags to handle variable size jump
8783 instructions.
8784
8785 Any symbol that is now undefined will not become defined.
8786 Return the correct fr_subtype in the frag.
8787 Return the initial "guess for variable size of frag" to caller.
8788 The guess is actually the growth beyond the fixed part. Whatever
8789 we do to grow the fixed or variable part contributes to our
8790 returned value. */
8791
252b5132 8792int
7016a5d5 8793md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8794{
252b5132 8795 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8796 check for un-relaxable symbols. On an ELF system, we can't relax
8797 an externally visible symbol, because it may be overridden by a
8798 shared library. */
8799 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8800#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8801 || (IS_ELF
31312f95 8802 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 8803 || S_IS_WEAK (fragP->fr_symbol)
8804 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
8805 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 8806#endif
8807#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8808 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8809 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8810#endif
8811 )
252b5132 8812 {
b98ef147
AM		 8813 /* Symbol is undefined in this segment, or we need to keep a
8814 reloc so that weak symbols can be overridden. */
8815 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8816 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8817 unsigned char *opcode;
8818 int old_fr_fix;
f6af82bd 8819
ee7fcc42 8820 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8821 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8822 else if (size == 2)
f6af82bd
AM		 8823 reloc_type = BFD_RELOC_16_PCREL;
8824 else
8825 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8826
ee7fcc42
AM		 8827 old_fr_fix = fragP->fr_fix;
8828 opcode = (unsigned char *) fragP->fr_opcode;
8829
fddf5b5b 8830 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8831 {
fddf5b5b
AM		 8832 case UNCOND_JUMP:
8833 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8834 opcode[0] = 0xe9;
252b5132 8835 fragP->fr_fix += size;
062cd5e7
AS		 8836 fix_new (fragP, old_fr_fix, size,
8837 fragP->fr_symbol,
8838 fragP->fr_offset, 1,
8839 reloc_type);
252b5132
RH		 8840 break;
8841
fddf5b5b 8842 case COND_JUMP86:
412167cb
AM		 8843 if (size == 2
8844 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8845 {
8846 /* Negate the condition, and branch past an
8847 unconditional jump. */
8848 opcode[0] ^= 1;
8849 opcode[1] = 3;
8850 /* Insert an unconditional jump. */
8851 opcode[2] = 0xe9;
8852 /* We added two extra opcode bytes, and have a two byte
8853 offset. */
8854 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8855 fix_new (fragP, old_fr_fix + 2, 2,
8856 fragP->fr_symbol,
8857 fragP->fr_offset, 1,
8858 reloc_type);
fddf5b5b
AM		 8859 break;
8860 }
8861 /* Fall through. */
8862
8863 case COND_JUMP:
412167cb
AM		 8864 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8865 {
3e02c1cc
AM		 8866 fixS *fixP;
8867
412167cb 8868 fragP->fr_fix += 1;
3e02c1cc
AM		 8869 fixP = fix_new (fragP, old_fr_fix, 1,
8870 fragP->fr_symbol,
8871 fragP->fr_offset, 1,
8872 BFD_RELOC_8_PCREL);
8873 fixP->fx_signed = 1;
412167cb
AM		 8874 break;
8875 }
93c2a809 8876
24eab124 8877 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8878 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8879 opcode[1] = opcode[0] + 0x10;
f6af82bd 8880 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8881 /* We've added an opcode byte. */
8882 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8883 fix_new (fragP, old_fr_fix + 1, size,
8884 fragP->fr_symbol,
8885 fragP->fr_offset, 1,
8886 reloc_type);
252b5132 8887 break;
fddf5b5b
AM		 8888
8889 default:
8890 BAD_CASE (fragP->fr_subtype);
8891 break;
252b5132
RH		 8892 }
8893 frag_wane (fragP);
ee7fcc42 8894 return fragP->fr_fix - old_fr_fix;
252b5132 8895 }
93c2a809 8896
93c2a809
AM		 8897 /* Guess size depending on current relax state. Initially the relax
8898 state will correspond to a short jump and we return 1, because
8899 the variable part of the frag (the branch offset) is one byte
8900 long. However, we can relax a section more than once and in that
8901 case we must either set fr_subtype back to the unrelaxed state,
8902 or return the value for the appropriate branch. */
8903 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 8904}
8905
47926f60
KH		 8906/* Called after relax() is finished.
8907
8908 In: Address of frag.
8909 fr_type == rs_machine_dependent.
8910 fr_subtype is what the address relaxed to.
8911
8912 Out: Any fixSs and constants are set up.
8913 Caller will turn frag into a ".space 0". */
8914
252b5132 8915void
7016a5d5
TG		 8916md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
8917 fragS *fragP)
252b5132 8918{
29b0f896 8919 unsigned char *opcode;
252b5132 8920 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 8921 offsetT target_address;
8922 offsetT opcode_address;
252b5132 8923 unsigned int extension = 0;
847f7ad4 8924 offsetT displacement_from_opcode_start;
252b5132
RH		 8925
8926 opcode = (unsigned char *) fragP->fr_opcode;
8927
47926f60 8928 /* Address we want to reach in file space. */
252b5132 8929 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 8930
47926f60 8931 /* Address opcode resides at in file space. */
252b5132
RH		 8932 opcode_address = fragP->fr_address + fragP->fr_fix;
8933
47926f60 8934 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 8935 displacement_from_opcode_start = target_address - opcode_address;
8936
fddf5b5b 8937 if ((fragP->fr_subtype & BIG) == 0)
252b5132 8938 {
47926f60
KH		 8939 /* Don't have to change opcode. */
8940 extension = 1; /* 1 opcode + 1 displacement */
252b5132 8941 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 8942 }
8943 else
8944 {
8945 if (no_cond_jump_promotion
8946 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 8947 as_warn_where (fragP->fr_file, fragP->fr_line,
8948 _("long jump required"));
252b5132 8949
fddf5b5b
AM		 8950 switch (fragP->fr_subtype)
8951 {
8952 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
8953 extension = 4; /* 1 opcode + 4 displacement */
8954 opcode[0] = 0xe9;
8955 where_to_put_displacement = &opcode[1];
8956 break;
252b5132 8957
fddf5b5b
AM		 8958 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
8959 extension = 2; /* 1 opcode + 2 displacement */
8960 opcode[0] = 0xe9;
8961 where_to_put_displacement = &opcode[1];
8962 break;
252b5132 8963
fddf5b5b
AM		 8964 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
8965 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
8966 extension = 5; /* 2 opcode + 4 displacement */
8967 opcode[1] = opcode[0] + 0x10;
8968 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8969 where_to_put_displacement = &opcode[2];
8970 break;
252b5132 8971
fddf5b5b
AM		 8972 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
8973 extension = 3; /* 2 opcode + 2 displacement */
8974 opcode[1] = opcode[0] + 0x10;
8975 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8976 where_to_put_displacement = &opcode[2];
8977 break;
252b5132 8978
fddf5b5b
AM		 8979 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
8980 extension = 4;
8981 opcode[0] ^= 1;
8982 opcode[1] = 3;
8983 opcode[2] = 0xe9;
8984 where_to_put_displacement = &opcode[3];
8985 break;
8986
8987 default:
8988 BAD_CASE (fragP->fr_subtype);
8989 break;
8990 }
252b5132 8991 }
fddf5b5b 8992
7b81dfbb
AJ		 8993 /* If size if less then four we are sure that the operand fits,
8994 but if it's 4, then it could be that the displacement is larger
8995 then -/+ 2GB. */
8996 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
8997 && object_64bit
8998 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 8999 + ((addressT) 1 << 31))
9000 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9001 {
9002 as_bad_where (fragP->fr_file, fragP->fr_line,
9003 _("jump target out of range"));
9004 /* Make us emit 0. */
9005 displacement_from_opcode_start = extension;
9006 }
47926f60 9007 /* Now put displacement after opcode. */
252b5132
RH		 9008 md_number_to_chars ((char *) where_to_put_displacement,
9009 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9010 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9011 fragP->fr_fix += extension;
9012}
9013\f
7016a5d5 9014/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9015 by our caller that we have all the info we need to fix it up.
9016
7016a5d5
TG		 9017 Parameter valP is the pointer to the value of the bits.
9018
252b5132
RH		 9019 On the 386, immediates, displacements, and data pointers are all in
9020 the same (little-endian) format, so we don't need to care about which
9021 we are handling. */
9022
94f592af 9023void
7016a5d5 9024md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9025{
94f592af 9026 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9027 valueT value = *valP;
252b5132 9028
f86103b7 9029#if !defined (TE_Mach)
93382f6d
AM		 9030 if (fixP->fx_pcrel)
9031 {
9032 switch (fixP->fx_r_type)
9033 {
5865bb77
ILT		 9034 default:
9035 break;
9036
d6ab8113
JB		 9037 case BFD_RELOC_64:
9038 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9039 break;
93382f6d 9040 case BFD_RELOC_32:
ae8887b5 9041 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9042 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9043 break;
9044 case BFD_RELOC_16:
9045 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9046 break;
9047 case BFD_RELOC_8:
9048 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9049 break;
9050 }
9051 }
252b5132 9052
a161fe53 9053 if (fixP->fx_addsy != NULL
31312f95 9054 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9055 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 9056 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9057 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9058 && !use_rela_relocations)
252b5132 9059 {
31312f95
AM		 9060 /* This is a hack. There should be a better way to handle this.
9061 This covers for the fact that bfd_install_relocation will
9062 subtract the current location (for partial_inplace, PC relative
9063 relocations); see more below. */
252b5132 9064#ifndef OBJ_AOUT
718ddfc0 9065 if (IS_ELF
252b5132
RH		 9066#ifdef TE_PE
9067 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9068#endif
9069 )
9070 value += fixP->fx_where + fixP->fx_frag->fr_address;
9071#endif
9072#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9073 if (IS_ELF)
252b5132 9074 {
6539b54b 9075 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9076
6539b54b 9077 if ((sym_seg == seg
2f66722d 9078 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9079 && sym_seg != absolute_section))
af65af87 9080 && !generic_force_reloc (fixP))
2f66722d
AM		 9081 {
9082 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9083 bfd_install_relocation subtracts them out again. I think
9084 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9085 it. FIXME. */
9086 value += fixP->fx_where + fixP->fx_frag->fr_address;
9087 }
252b5132
RH		 9088 }
9089#endif
9090#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9091 /* For some reason, the PE format does not store a
9092 section address offset for a PC relative symbol. */
9093 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9094 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9095 value += md_pcrel_from (fixP);
9096#endif
9097 }
fbeb56a4
DK		 9098#if defined (OBJ_COFF) && defined (TE_PE)
9099 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9100 {
9101 value -= S_GET_VALUE (fixP->fx_addsy);
9102 }
9103#endif
252b5132
RH		 9104
9105 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9106 and we must not disappoint it. */
252b5132 9107#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9108 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9109 switch (fixP->fx_r_type)
9110 {
9111 case BFD_RELOC_386_PLT32:
3e73aa7c 9112 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9113 /* Make the jump instruction point to the address of the operand. At
9114 runtime we merely add the offset to the actual PLT entry. */
9115 value = -4;
9116 break;
31312f95 9117
13ae64f3
JJ		 9118 case BFD_RELOC_386_TLS_GD:
9119 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9120 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9121 case BFD_RELOC_386_TLS_IE:
9122 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9123 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9124 case BFD_RELOC_X86_64_TLSGD:
9125 case BFD_RELOC_X86_64_TLSLD:
9126 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9127 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9128 value = 0; /* Fully resolved at runtime. No addend. */
9129 /* Fallthrough */
9130 case BFD_RELOC_386_TLS_LE:
9131 case BFD_RELOC_386_TLS_LDO_32:
9132 case BFD_RELOC_386_TLS_LE_32:
9133 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9134 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9135 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9136 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9137 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9138 break;
9139
67a4f2b7
AO		 9140 case BFD_RELOC_386_TLS_DESC_CALL:
9141 case BFD_RELOC_X86_64_TLSDESC_CALL:
9142 value = 0; /* Fully resolved at runtime. No addend. */
9143 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9144 fixP->fx_done = 0;
9145 return;
9146
00f7efb6
JJ		 9147 case BFD_RELOC_386_GOT32:
9148 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9149 value = 0; /* Fully resolved at runtime. No addend. */
9150 break;
47926f60
KH		 9151
9152 case BFD_RELOC_VTABLE_INHERIT:
9153 case BFD_RELOC_VTABLE_ENTRY:
9154 fixP->fx_done = 0;
94f592af 9155 return;
47926f60
KH		 9156
9157 default:
9158 break;
9159 }
9160#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9161 *valP = value;
f86103b7 9162#endif /* !defined (TE_Mach) */
3e73aa7c 9163
3e73aa7c 9164 /* Are we finished with this relocation now? */
c6682705 9165 if (fixP->fx_addsy == NULL)
3e73aa7c 9166 fixP->fx_done = 1;
fbeb56a4
DK		 9167#if defined (OBJ_COFF) && defined (TE_PE)
9168 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9169 {
9170 fixP->fx_done = 0;
9171 /* Remember value for tc_gen_reloc. */
9172 fixP->fx_addnumber = value;
9173 /* Clear out the frag for now. */
9174 value = 0;
9175 }
9176#endif
3e73aa7c
JH		 9177 else if (use_rela_relocations)
9178 {
9179 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9180 /* Remember value for tc_gen_reloc. */
9181 fixP->fx_addnumber = value;
3e73aa7c
JH		 9182 value = 0;
9183 }
f86103b7 9184
94f592af 9185 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9186}
252b5132 9187\f
252b5132 9188char *
499ac353 9189md_atof (int type, char *litP, int *sizeP)
252b5132 9190{
499ac353
NC		 9191 /* This outputs the LITTLENUMs in REVERSE order;
9192 in accord with the bigendian 386. */
9193 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9194}
9195\f
2d545b82 9196static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9197
252b5132 9198static char *
e3bb37b5 9199output_invalid (int c)
252b5132 9200{
3882b010 9201 if (ISPRINT (c))
f9f21a03
L		 9202 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9203 "'%c'", c);
252b5132 9204 else
f9f21a03 9205 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9206 "(0x%x)", (unsigned char) c);
252b5132
RH		 9207 return output_invalid_buf;
9208}
9209
af6bdddf 9210/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9211
9212static const reg_entry *
4d1bb795 9213parse_real_register (char *reg_string, char **end_op)
252b5132 9214{
af6bdddf
AM		 9215 char *s = reg_string;
9216 char *p;
252b5132
RH		 9217 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9218 const reg_entry *r;
9219
9220 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9221 if (*s == REGISTER_PREFIX)
9222 ++s;
9223
9224 if (is_space_char (*s))
9225 ++s;
9226
9227 p = reg_name_given;
af6bdddf 9228 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9229 {
9230 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9231 return (const reg_entry *) NULL;
9232 s++;
252b5132
RH		 9233 }
9234
6588847e
DN		 9235 /* For naked regs, make sure that we are not dealing with an identifier.
9236 This prevents confusing an identifier like `eax_var' with register
9237 `eax'. */
9238 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9239 return (const reg_entry *) NULL;
9240
af6bdddf 9241 *end_op = s;
252b5132
RH		 9242
9243 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9244
5f47d35b 9245 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9246 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9247 {
5f47d35b
AM		 9248 if (is_space_char (*s))
9249 ++s;
9250 if (*s == '(')
9251 {
af6bdddf 9252 ++s;
5f47d35b
AM		 9253 if (is_space_char (*s))
9254 ++s;
9255 if (*s >= '0' && *s <= '7')
9256 {
db557034 9257 int fpr = *s - '0';
af6bdddf 9258 ++s;
5f47d35b
AM		 9259 if (is_space_char (*s))
9260 ++s;
9261 if (*s == ')')
9262 {
9263 *end_op = s + 1;
1e9cc1c2 9264 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9265 know (r);
9266 return r + fpr;
5f47d35b 9267 }
5f47d35b 9268 }
47926f60 9269 /* We have "%st(" then garbage. */
5f47d35b
AM		 9270 return (const reg_entry *) NULL;
9271 }
9272 }
9273
a60de03c
JB		 9274 if (r == NULL || allow_pseudo_reg)
9275 return r;
9276
0dfbf9d7 9277 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9278 return (const reg_entry *) NULL;
9279
192dc9c6
JB		 9280 if ((r->reg_type.bitfield.reg32
9281 || r->reg_type.bitfield.sreg3
9282 || r->reg_type.bitfield.control
9283 || r->reg_type.bitfield.debug
9284 || r->reg_type.bitfield.test)
9285 && !cpu_arch_flags.bitfield.cpui386)
9286 return (const reg_entry *) NULL;
9287
309d3373
JB		 9288 if (r->reg_type.bitfield.floatreg
9289 && !cpu_arch_flags.bitfield.cpu8087
9290 && !cpu_arch_flags.bitfield.cpu287
9291 && !cpu_arch_flags.bitfield.cpu387)
9292 return (const reg_entry *) NULL;
9293
192dc9c6
JB		 9294 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9295 return (const reg_entry *) NULL;
9296
9297 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9298 return (const reg_entry *) NULL;
9299
40f12533
L		 9300 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9301 return (const reg_entry *) NULL;
9302
43234a1e
L		 9303 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9304 && !cpu_arch_flags.bitfield.cpuavx512f)
9305 return (const reg_entry *) NULL;
9306
db51cc60 9307 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9308 if (!allow_index_reg
db51cc60
L		 9309 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9310 return (const reg_entry *) NULL;
9311
43234a1e
L		 9312 /* Upper 16 vector register is only available with VREX in 64bit
9313 mode. */
9314 if ((r->reg_flags & RegVRex))
9315 {
9316 if (!cpu_arch_flags.bitfield.cpuvrex
9317 || flag_code != CODE_64BIT)
9318 return (const reg_entry *) NULL;
9319
9320 i.need_vrex = 1;
9321 }
9322
a60de03c
JB		 9323 if (((r->reg_flags & (RegRex64 | RegRex))
9324 || r->reg_type.bitfield.reg64)
40fb9820 9325 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9326 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9327 && flag_code != CODE_64BIT)
20f0a1fc 9328 return (const reg_entry *) NULL;
1ae00879 9329
b7240065
JB		 9330 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9331 return (const reg_entry *) NULL;
9332
252b5132
RH		 9333 return r;
9334}
4d1bb795
JB		 9335
9336/* REG_STRING starts *before* REGISTER_PREFIX. */
9337
9338static const reg_entry *
9339parse_register (char *reg_string, char **end_op)
9340{
9341 const reg_entry *r;
9342
9343 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9344 r = parse_real_register (reg_string, end_op);
9345 else
9346 r = NULL;
9347 if (!r)
9348 {
9349 char *save = input_line_pointer;
9350 char c;
9351 symbolS *symbolP;
9352
9353 input_line_pointer = reg_string;
9354 c = get_symbol_end ();
9355 symbolP = symbol_find (reg_string);
9356 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9357 {
9358 const expressionS *e = symbol_get_value_expression (symbolP);
9359
0398aac5 9360 know (e->X_op == O_register);
4eed87de 9361 know (e->X_add_number >= 0
c3fe08fa 9362 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 9363 r = i386_regtab + e->X_add_number;
9364 *end_op = input_line_pointer;
9365 }
9366 *input_line_pointer = c;
9367 input_line_pointer = save;
9368 }
9369 return r;
9370}
9371
9372int
9373i386_parse_name (char *name, expressionS *e, char *nextcharP)
9374{
9375 const reg_entry *r;
9376 char *end = input_line_pointer;
9377
9378 *end = *nextcharP;
9379 r = parse_register (name, &input_line_pointer);
9380 if (r && end <= input_line_pointer)
9381 {
9382 *nextcharP = *input_line_pointer;
9383 *input_line_pointer = 0;
9384 e->X_op = O_register;
9385 e->X_add_number = r - i386_regtab;
9386 return 1;
9387 }
9388 input_line_pointer = end;
9389 *end = 0;
ee86248c 9390 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9391}
9392
9393void
9394md_operand (expressionS *e)
9395{
ee86248c
JB		 9396 char *end;
9397 const reg_entry *r;
4d1bb795 9398
ee86248c
JB		 9399 switch (*input_line_pointer)
9400 {
9401 case REGISTER_PREFIX:
9402 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9403 if (r)
9404 {
9405 e->X_op = O_register;
9406 e->X_add_number = r - i386_regtab;
9407 input_line_pointer = end;
9408 }
ee86248c
JB		 9409 break;
9410
9411 case '[':
9c2799c2 9412 gas_assert (intel_syntax);
ee86248c
JB		 9413 end = input_line_pointer++;
9414 expression (e);
9415 if (*input_line_pointer == ']')
9416 {
9417 ++input_line_pointer;
9418 e->X_op_symbol = make_expr_symbol (e);
9419 e->X_add_symbol = NULL;
9420 e->X_add_number = 0;
9421 e->X_op = O_index;
9422 }
9423 else
9424 {
9425 e->X_op = O_absent;
9426 input_line_pointer = end;
9427 }
9428 break;
4d1bb795
JB		 9429 }
9430}
9431
252b5132 9432\f
4cc782b5 9433#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9434const char *md_shortopts = "kVQ:sqn";
252b5132 9435#else
12b55ccc 9436const char *md_shortopts = "qn";
252b5132 9437#endif
6e0b89ee 9438
3e73aa7c 9439#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9440#define OPTION_64 (OPTION_MD_BASE + 1)
9441#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9442#define OPTION_MARCH (OPTION_MD_BASE + 3)
9443#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9444#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9445#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9446#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9447#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9448#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9449#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9450#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9451#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9452#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9453#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9454#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9455#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9456#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
b3b91714 9457
99ad8390
NC		 9458struct option md_longopts[] =
9459{
3e73aa7c 9460 {"32", no_argument, NULL, OPTION_32},
321098a5 9461#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9462 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9463 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9464#endif
9465#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9466 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 9467#endif
b3b91714 9468 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9469 {"march", required_argument, NULL, OPTION_MARCH},
9470 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9471 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9472 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9473 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9474 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9475 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9476 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9477 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9478 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9479 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9480 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9481 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9482 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
252b5132
RH		 9483 {NULL, no_argument, NULL, 0}
9484};
9485size_t md_longopts_size = sizeof (md_longopts);
9486
9487int
9103f4f4 9488md_parse_option (int c, char *arg)
252b5132 9489{
91d6fa6a 9490 unsigned int j;
6305a203 9491 char *arch, *next;
9103f4f4 9492
252b5132
RH		 9493 switch (c)
9494 {
12b55ccc
L		 9495 case 'n':
9496 optimize_align_code = 0;
9497 break;
9498
a38cf1db
AM		 9499 case 'q':
9500 quiet_warnings = 1;
252b5132
RH		 9501 break;
9502
9503#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9504 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9505 should be emitted or not. FIXME: Not implemented. */
9506 case 'Q':
252b5132
RH		 9507 break;
9508
9509 /* -V: SVR4 argument to print version ID. */
9510 case 'V':
9511 print_version_id ();
9512 break;
9513
a38cf1db
AM		 9514 /* -k: Ignore for FreeBSD compatibility. */
9515 case 'k':
252b5132 9516 break;
4cc782b5
ILT		 9517
9518 case 's':
9519 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9520 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9521 break;
99ad8390 9522#endif
321098a5 9523#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9524 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9525 case OPTION_64:
9526 {
9527 const char **list, **l;
9528
3e73aa7c
JH		 9529 list = bfd_target_list ();
9530 for (l = list; *l != NULL; l++)
8620418b 9531 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9532 || strcmp (*l, "coff-x86-64") == 0
9533 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9534 || strcmp (*l, "pei-x86-64") == 0
9535 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9536 {
9537 default_arch = "x86_64";
9538 break;
9539 }
3e73aa7c 9540 if (*l == NULL)
2b5d6a91 9541 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9542 free (list);
9543 }
9544 break;
9545#endif
252b5132 9546
351f65ca 9547#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9548 case OPTION_X32:
351f65ca
L		 9549 if (IS_ELF)
9550 {
9551 const char **list, **l;
9552
9553 list = bfd_target_list ();
9554 for (l = list; *l != NULL; l++)
9555 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9556 {
9557 default_arch = "x86_64:32";
9558 break;
9559 }
9560 if (*l == NULL)
2b5d6a91 9561 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9562 free (list);
9563 }
9564 else
9565 as_fatal (_("32bit x86_64 is only supported for ELF"));
9566 break;
9567#endif
9568
6e0b89ee
AM		 9569 case OPTION_32:
9570 default_arch = "i386";
9571 break;
9572
b3b91714
AM		 9573 case OPTION_DIVIDE:
9574#ifdef SVR4_COMMENT_CHARS
9575 {
9576 char *n, *t;
9577 const char *s;
9578
9579 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9580 t = n;
9581 for (s = i386_comment_chars; *s != '\0'; s++)
9582 if (*s != '/')
9583 *t++ = *s;
9584 *t = '\0';
9585 i386_comment_chars = n;
9586 }
9587#endif
9588 break;
9589
9103f4f4 9590 case OPTION_MARCH:
6305a203
L		 9591 arch = xstrdup (arg);
9592 do
9103f4f4 9593 {
6305a203 9594 if (*arch == '.')
2b5d6a91 9595 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9596 next = strchr (arch, '+');
9597 if (next)
9598 *next++ = '\0';
91d6fa6a 9599 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9600 {
91d6fa6a 9601 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9602 {
6305a203 9603 /* Processor. */
1ded5609
JB		 9604 if (! cpu_arch[j].flags.bitfield.cpui386)
9605 continue;
9606
91d6fa6a 9607 cpu_arch_name = cpu_arch[j].name;
6305a203 9608 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9609 cpu_arch_flags = cpu_arch[j].flags;
9610 cpu_arch_isa = cpu_arch[j].type;
9611 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9612 if (!cpu_arch_tune_set)
9613 {
9614 cpu_arch_tune = cpu_arch_isa;
9615 cpu_arch_tune_flags = cpu_arch_isa_flags;
9616 }
9617 break;
9618 }
91d6fa6a
NC		 9619 else if (*cpu_arch [j].name == '.'
9620 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9621 {
9622 /* ISA entension. */
9623 i386_cpu_flags flags;
309d3373 9624
49021df2 9625 if (!cpu_arch[j].negated)
309d3373 9626 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9627 cpu_arch[j].flags);
309d3373
JB		 9628 else
9629 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9630 cpu_arch[j].flags);
0dfbf9d7 9631 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9632 {
9633 if (cpu_sub_arch_name)
9634 {
9635 char *name = cpu_sub_arch_name;
9636 cpu_sub_arch_name = concat (name,
91d6fa6a 9637 cpu_arch[j].name,
1bf57e9f 9638 (const char *) NULL);
6305a203
L		 9639 free (name);
9640 }
9641 else
91d6fa6a 9642 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9643 cpu_arch_flags = flags;
a586129e 9644 cpu_arch_isa_flags = flags;
6305a203
L		 9645 }
9646 break;
ccc9c027 9647 }
9103f4f4 9648 }
6305a203 9649
91d6fa6a 9650 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9651 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9652
9653 arch = next;
9103f4f4 9654 }
6305a203 9655 while (next != NULL );
9103f4f4
L		 9656 break;
9657
9658 case OPTION_MTUNE:
9659 if (*arg == '.')
2b5d6a91 9660 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9661 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9662 {
91d6fa6a 9663 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9664 {
ccc9c027 9665 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9666 cpu_arch_tune = cpu_arch [j].type;
9667 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9668 break;
9669 }
9670 }
91d6fa6a 9671 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9672 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9673 break;
9674
1efbbeb4
L		 9675 case OPTION_MMNEMONIC:
9676 if (strcasecmp (arg, "att") == 0)
9677 intel_mnemonic = 0;
9678 else if (strcasecmp (arg, "intel") == 0)
9679 intel_mnemonic = 1;
9680 else
2b5d6a91 9681 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9682 break;
9683
9684 case OPTION_MSYNTAX:
9685 if (strcasecmp (arg, "att") == 0)
9686 intel_syntax = 0;
9687 else if (strcasecmp (arg, "intel") == 0)
9688 intel_syntax = 1;
9689 else
2b5d6a91 9690 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9691 break;
9692
9693 case OPTION_MINDEX_REG:
9694 allow_index_reg = 1;
9695 break;
9696
9697 case OPTION_MNAKED_REG:
9698 allow_naked_reg = 1;
9699 break;
9700
9701 case OPTION_MOLD_GCC:
9702 old_gcc = 1;
1efbbeb4
L		 9703 break;
9704
c0f3af97
L		 9705 case OPTION_MSSE2AVX:
9706 sse2avx = 1;
9707 break;
9708
daf50ae7
L		 9709 case OPTION_MSSE_CHECK:
9710 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9711 sse_check = check_error;
daf50ae7 9712 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9713 sse_check = check_warning;
daf50ae7 9714 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9715 sse_check = check_none;
daf50ae7 9716 else
2b5d6a91 9717 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9718 break;
9719
7bab8ab5
JB		 9720 case OPTION_MOPERAND_CHECK:
9721 if (strcasecmp (arg, "error") == 0)
9722 operand_check = check_error;
9723 else if (strcasecmp (arg, "warning") == 0)
9724 operand_check = check_warning;
9725 else if (strcasecmp (arg, "none") == 0)
9726 operand_check = check_none;
9727 else
9728 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9729 break;
9730
539f890d
L		 9731 case OPTION_MAVXSCALAR:
9732 if (strcasecmp (arg, "128") == 0)
9733 avxscalar = vex128;
9734 else if (strcasecmp (arg, "256") == 0)
9735 avxscalar = vex256;
9736 else
2b5d6a91 9737 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9738 break;
9739
7e8b059b
L		 9740 case OPTION_MADD_BND_PREFIX:
9741 add_bnd_prefix = 1;
9742 break;
9743
43234a1e
L		 9744 case OPTION_MEVEXLIG:
9745 if (strcmp (arg, "128") == 0)
9746 evexlig = evexl128;
9747 else if (strcmp (arg, "256") == 0)
9748 evexlig = evexl256;
9749 else if (strcmp (arg, "512") == 0)
9750 evexlig = evexl512;
9751 else
9752 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9753 break;
9754
9755 case OPTION_MEVEXWIG:
9756 if (strcmp (arg, "0") == 0)
9757 evexwig = evexw0;
9758 else if (strcmp (arg, "1") == 0)
9759 evexwig = evexw1;
9760 else
9761 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9762 break;
9763
252b5132
RH		 9764 default:
9765 return 0;
9766 }
9767 return 1;
9768}
9769
8a2c8fef
L		 9770#define MESSAGE_TEMPLATE \
9771" "
9772
9773static void
1ded5609 9774show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9775{
9776 static char message[] = MESSAGE_TEMPLATE;
9777 char *start = message + 27;
9778 char *p;
9779 int size = sizeof (MESSAGE_TEMPLATE);
9780 int left;
9781 const char *name;
9782 int len;
9783 unsigned int j;
9784
9785 p = start;
9786 left = size - (start - message);
9787 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9788 {
9789 /* Should it be skipped? */
9790 if (cpu_arch [j].skip)
9791 continue;
9792
9793 name = cpu_arch [j].name;
9794 len = cpu_arch [j].len;
9795 if (*name == '.')
9796 {
9797 /* It is an extension. Skip if we aren't asked to show it. */
9798 if (ext)
9799 {
9800 name++;
9801 len--;
9802 }
9803 else
9804 continue;
9805 }
9806 else if (ext)
9807 {
9808 /* It is an processor. Skip if we show only extension. */
9809 continue;
9810 }
1ded5609
JB		 9811 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9812 {
9813 /* It is an impossible processor - skip. */
9814 continue;
9815 }
8a2c8fef
L		 9816
9817 /* Reserve 2 spaces for ", " or ",\0" */
9818 left -= len + 2;
9819
9820 /* Check if there is any room. */
9821 if (left >= 0)
9822 {
9823 if (p != start)
9824 {
9825 *p++ = ',';
9826 *p++ = ' ';
9827 }
9828 p = mempcpy (p, name, len);
9829 }
9830 else
9831 {
9832 /* Output the current message now and start a new one. */
9833 *p++ = ',';
9834 *p = '\0';
9835 fprintf (stream, "%s\n", message);
9836 p = start;
9837 left = size - (start - message) - len - 2;
8d63c93e 9838
8a2c8fef
L		 9839 gas_assert (left >= 0);
9840
9841 p = mempcpy (p, name, len);
9842 }
9843 }
9844
9845 *p = '\0';
9846 fprintf (stream, "%s\n", message);
9847}
9848
252b5132 9849void
8a2c8fef 9850md_show_usage (FILE *stream)
252b5132 9851{
4cc782b5
ILT		 9852#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9853 fprintf (stream, _("\
a38cf1db
AM		 9854 -Q ignored\n\
9855 -V print assembler version number\n\
b3b91714
AM		 9856 -k ignored\n"));
9857#endif
9858 fprintf (stream, _("\
12b55ccc 9859 -n Do not optimize code alignment\n\
b3b91714
AM		 9860 -q quieten some warnings\n"));
9861#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9862 fprintf (stream, _("\
a38cf1db 9863 -s ignored\n"));
b3b91714 9864#endif
321098a5
L		 9865#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9866 || defined (TE_PE) || defined (TE_PEP))
751d281c 9867 fprintf (stream, _("\
570561f7 9868 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 9869#endif
b3b91714
AM		 9870#ifdef SVR4_COMMENT_CHARS
9871 fprintf (stream, _("\
9872 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 9873#else
9874 fprintf (stream, _("\
b3b91714 9875 --divide ignored\n"));
4cc782b5 9876#endif
9103f4f4 9877 fprintf (stream, _("\
6305a203 9878 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 9879 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 9880 show_arch (stream, 0, 1);
8a2c8fef
L		 9881 fprintf (stream, _("\
9882 EXTENSION is combination of:\n"));
1ded5609 9883 show_arch (stream, 1, 0);
6305a203 9884 fprintf (stream, _("\
8a2c8fef 9885 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 9886 show_arch (stream, 0, 0);
ba104c83 9887 fprintf (stream, _("\
c0f3af97
L		 9888 -msse2avx encode SSE instructions with VEX prefix\n"));
9889 fprintf (stream, _("\
daf50ae7
L		 9890 -msse-check=[none|error|warning]\n\
9891 check SSE instructions\n"));
9892 fprintf (stream, _("\
7bab8ab5
JB		 9893 -moperand-check=[none|error|warning]\n\
9894 check operand combinations for validity\n"));
9895 fprintf (stream, _("\
539f890d
L		 9896 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9897 length\n"));
9898 fprintf (stream, _("\
43234a1e
L		 9899 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
9900 length\n"));
9901 fprintf (stream, _("\
9902 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
9903 for EVEX.W bit ignored instructions\n"));
9904 fprintf (stream, _("\
ba104c83
L		 9905 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9906 fprintf (stream, _("\
9907 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9908 fprintf (stream, _("\
9909 -mindex-reg support pseudo index registers\n"));
9910 fprintf (stream, _("\
9911 -mnaked-reg don't require `%%' prefix for registers\n"));
9912 fprintf (stream, _("\
9913 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 9914 fprintf (stream, _("\
9915 -madd-bnd-prefix add BND prefix for all valid branches\n"));
252b5132
RH		 9916}
9917
3e73aa7c 9918#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 9919 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 9920 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 9921
9922/* Pick the target format to use. */
9923
47926f60 9924const char *
e3bb37b5 9925i386_target_format (void)
252b5132 9926{
351f65ca
L		 9927 if (!strncmp (default_arch, "x86_64", 6))
9928 {
9929 update_code_flag (CODE_64BIT, 1);
9930 if (default_arch[6] == '\0')
7f56bc95 9931 x86_elf_abi = X86_64_ABI;
351f65ca 9932 else
7f56bc95 9933 x86_elf_abi = X86_64_X32_ABI;
351f65ca 9934 }
3e73aa7c 9935 else if (!strcmp (default_arch, "i386"))
78f12dd3 9936 update_code_flag (CODE_32BIT, 1);
3e73aa7c 9937 else
2b5d6a91 9938 as_fatal (_("unknown architecture"));
89507696
JB		 9939
9940 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
9941 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
9942 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
9943 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
9944
252b5132
RH		 9945 switch (OUTPUT_FLAVOR)
9946 {
9384f2ff 9947#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 9948 case bfd_target_aout_flavour:
47926f60 9949 return AOUT_TARGET_FORMAT;
4c63da97 9950#endif
9384f2ff
AM		 9951#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
9952# if defined (TE_PE) || defined (TE_PEP)
9953 case bfd_target_coff_flavour:
9954 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
9955# elif defined (TE_GO32)
0561d57c
JK		 9956 case bfd_target_coff_flavour:
9957 return "coff-go32";
9384f2ff 9958# else
252b5132
RH		 9959 case bfd_target_coff_flavour:
9960 return "coff-i386";
9384f2ff 9961# endif
4c63da97 9962#endif
3e73aa7c 9963#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 9964 case bfd_target_elf_flavour:
3e73aa7c 9965 {
351f65ca
L		 9966 const char *format;
9967
9968 switch (x86_elf_abi)
4fa24527 9969 {
351f65ca
L		 9970 default:
9971 format = ELF_TARGET_FORMAT;
9972 break;
7f56bc95 9973 case X86_64_ABI:
351f65ca 9974 use_rela_relocations = 1;
4fa24527 9975 object_64bit = 1;
351f65ca
L		 9976 format = ELF_TARGET_FORMAT64;
9977 break;
7f56bc95 9978 case X86_64_X32_ABI:
4fa24527 9979 use_rela_relocations = 1;
351f65ca 9980 object_64bit = 1;
862be3fb 9981 disallow_64bit_reloc = 1;
351f65ca
L		 9982 format = ELF_TARGET_FORMAT32;
9983 break;
4fa24527 9984 }
3632d14b 9985 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 9986 {
7f56bc95 9987 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 9988 as_fatal (_("Intel L1OM is 64bit only"));
9989 return ELF_TARGET_L1OM_FORMAT;
9990 }
7a9068fe
L		 9991 if (cpu_arch_isa == PROCESSOR_K1OM)
9992 {
9993 if (x86_elf_abi != X86_64_ABI)
9994 as_fatal (_("Intel K1OM is 64bit only"));
9995 return ELF_TARGET_K1OM_FORMAT;
9996 }
8a9036a4 9997 else
351f65ca 9998 return format;
3e73aa7c 9999 }
e57f8c65
TG		 10000#endif
10001#if defined (OBJ_MACH_O)
10002 case bfd_target_mach_o_flavour:
d382c579
TG		 10003 if (flag_code == CODE_64BIT)
10004 {
10005 use_rela_relocations = 1;
10006 object_64bit = 1;
10007 return "mach-o-x86-64";
10008 }
10009 else
10010 return "mach-o-i386";
4c63da97 10011#endif
252b5132
RH		 10012 default:
10013 abort ();
10014 return NULL;
10015 }
10016}
10017
47926f60 10018#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 10019
10020#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 10021void
10022i386_elf_emit_arch_note (void)
a847613f 10023{
718ddfc0 10024 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 10025 {
10026 char *p;
10027 asection *seg = now_seg;
10028 subsegT subseg = now_subseg;
10029 Elf_Internal_Note i_note;
10030 Elf_External_Note e_note;
10031 asection *note_secp;
10032 int len;
10033
10034 /* Create the .note section. */
10035 note_secp = subseg_new (".note", 0);
10036 bfd_set_section_flags (stdoutput,
10037 note_secp,
10038 SEC_HAS_CONTENTS | SEC_READONLY);
10039
10040 /* Process the arch string. */
10041 len = strlen (cpu_arch_name);
10042
10043 i_note.namesz = len + 1;
10044 i_note.descsz = 0;
10045 i_note.type = NT_ARCH;
10046 p = frag_more (sizeof (e_note.namesz));
10047 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
10048 p = frag_more (sizeof (e_note.descsz));
10049 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
10050 p = frag_more (sizeof (e_note.type));
10051 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
10052 p = frag_more (len + 1);
10053 strcpy (p, cpu_arch_name);
10054
10055 frag_align (2, 0, 0);
10056
10057 subseg_set (seg, subseg);
10058 }
10059}
10060#endif
252b5132 10061\f
252b5132 10062symbolS *
7016a5d5 10063md_undefined_symbol (char *name)
252b5132 10064{
18dc2407
ILT		 10065 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10066 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10067 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10068 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10069 {
10070 if (!GOT_symbol)
10071 {
10072 if (symbol_find (name))
10073 as_bad (_("GOT already in symbol table"));
10074 GOT_symbol = symbol_new (name, undefined_section,
10075 (valueT) 0, &zero_address_frag);
10076 };
10077 return GOT_symbol;
10078 }
252b5132
RH		 10079 return 0;
10080}
10081
10082/* Round up a section size to the appropriate boundary. */
47926f60 10083
252b5132 10084valueT
7016a5d5 10085md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10086{
4c63da97
AM		 10087#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10088 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10089 {
10090 /* For a.out, force the section size to be aligned. If we don't do
10091 this, BFD will align it for us, but it will not write out the
10092 final bytes of the section. This may be a bug in BFD, but it is
10093 easier to fix it here since that is how the other a.out targets
10094 work. */
10095 int align;
10096
10097 align = bfd_get_section_alignment (stdoutput, segment);
10098 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10099 }
252b5132
RH		 10100#endif
10101
10102 return size;
10103}
10104
10105/* On the i386, PC-relative offsets are relative to the start of the
10106 next instruction. That is, the address of the offset, plus its
10107 size, since the offset is always the last part of the insn. */
10108
10109long
e3bb37b5 10110md_pcrel_from (fixS *fixP)
252b5132
RH		 10111{
10112 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10113}
10114
10115#ifndef I386COFF
10116
10117static void
e3bb37b5 10118s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10119{
29b0f896 10120 int temp;
252b5132 10121
8a75718c
JB		 10122#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10123 if (IS_ELF)
10124 obj_elf_section_change_hook ();
10125#endif
252b5132
RH		 10126 temp = get_absolute_expression ();
10127 subseg_set (bss_section, (subsegT) temp);
10128 demand_empty_rest_of_line ();
10129}
10130
10131#endif
10132
252b5132 10133void
e3bb37b5 10134i386_validate_fix (fixS *fixp)
252b5132
RH		 10135{
10136 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10137 {
23df1078
JH		 10138 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10139 {
4fa24527 10140 if (!object_64bit)
23df1078
JH		 10141 abort ();
10142 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10143 }
10144 else
10145 {
4fa24527 10146 if (!object_64bit)
d6ab8113
JB		 10147 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10148 else
10149 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 10150 }
252b5132
RH		 10151 fixp->fx_subsy = 0;
10152 }
10153}
10154
252b5132 10155arelent *
7016a5d5 10156tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10157{
10158 arelent *rel;
10159 bfd_reloc_code_real_type code;
10160
10161 switch (fixp->fx_r_type)
10162 {
8ce3d284 10163#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10164 case BFD_RELOC_SIZE32:
10165 case BFD_RELOC_SIZE64:
10166 if (S_IS_DEFINED (fixp->fx_addsy)
10167 && !S_IS_EXTERNAL (fixp->fx_addsy))
10168 {
10169 /* Resolve size relocation against local symbol to size of
10170 the symbol plus addend. */
10171 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10172 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10173 && !fits_in_unsigned_long (value))
10174 as_bad_where (fixp->fx_file, fixp->fx_line,
10175 _("symbol size computation overflow"));
10176 fixp->fx_addsy = NULL;
10177 fixp->fx_subsy = NULL;
10178 md_apply_fix (fixp, (valueT *) &value, NULL);
10179 return NULL;
10180 }
8ce3d284 10181#endif
8fd4256d 10182
3e73aa7c
JH		 10183 case BFD_RELOC_X86_64_PLT32:
10184 case BFD_RELOC_X86_64_GOT32:
10185 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 10186 case BFD_RELOC_386_PLT32:
10187 case BFD_RELOC_386_GOT32:
10188 case BFD_RELOC_386_GOTOFF:
10189 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10190 case BFD_RELOC_386_TLS_GD:
10191 case BFD_RELOC_386_TLS_LDM:
10192 case BFD_RELOC_386_TLS_LDO_32:
10193 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10194 case BFD_RELOC_386_TLS_IE:
10195 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10196 case BFD_RELOC_386_TLS_LE_32:
10197 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10198 case BFD_RELOC_386_TLS_GOTDESC:
10199 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10200 case BFD_RELOC_X86_64_TLSGD:
10201 case BFD_RELOC_X86_64_TLSLD:
10202 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10203 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10204 case BFD_RELOC_X86_64_GOTTPOFF:
10205 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10206 case BFD_RELOC_X86_64_TPOFF64:
10207 case BFD_RELOC_X86_64_GOTOFF64:
10208 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10209 case BFD_RELOC_X86_64_GOT64:
10210 case BFD_RELOC_X86_64_GOTPCREL64:
10211 case BFD_RELOC_X86_64_GOTPC64:
10212 case BFD_RELOC_X86_64_GOTPLT64:
10213 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10214 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10215 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10216 case BFD_RELOC_RVA:
10217 case BFD_RELOC_VTABLE_ENTRY:
10218 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10219#ifdef TE_PE
10220 case BFD_RELOC_32_SECREL:
10221#endif
252b5132
RH		 10222 code = fixp->fx_r_type;
10223 break;
dbbaec26
L		 10224 case BFD_RELOC_X86_64_32S:
10225 if (!fixp->fx_pcrel)
10226 {
10227 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10228 code = fixp->fx_r_type;
10229 break;
10230 }
252b5132 10231 default:
93382f6d 10232 if (fixp->fx_pcrel)
252b5132 10233 {
93382f6d
AM		 10234 switch (fixp->fx_size)
10235 {
10236 default:
b091f402
AM		 10237 as_bad_where (fixp->fx_file, fixp->fx_line,
10238 _("can not do %d byte pc-relative relocation"),
10239 fixp->fx_size);
93382f6d
AM		 10240 code = BFD_RELOC_32_PCREL;
10241 break;
10242 case 1: code = BFD_RELOC_8_PCREL; break;
10243 case 2: code = BFD_RELOC_16_PCREL; break;
10244 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10245#ifdef BFD64
10246 case 8: code = BFD_RELOC_64_PCREL; break;
10247#endif
93382f6d
AM		 10248 }
10249 }
10250 else
10251 {
10252 switch (fixp->fx_size)
10253 {
10254 default:
b091f402
AM		 10255 as_bad_where (fixp->fx_file, fixp->fx_line,
10256 _("can not do %d byte relocation"),
10257 fixp->fx_size);
93382f6d
AM		 10258 code = BFD_RELOC_32;
10259 break;
10260 case 1: code = BFD_RELOC_8; break;
10261 case 2: code = BFD_RELOC_16; break;
10262 case 4: code = BFD_RELOC_32; break;
937149dd 10263#ifdef BFD64
3e73aa7c 10264 case 8: code = BFD_RELOC_64; break;
937149dd 10265#endif
93382f6d 10266 }
252b5132
RH		 10267 }
10268 break;
10269 }
252b5132 10270
d182319b
JB		 10271 if ((code == BFD_RELOC_32
10272 || code == BFD_RELOC_32_PCREL
10273 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10274 && GOT_symbol
10275 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10276 {
4fa24527 10277 if (!object_64bit)
d6ab8113
JB		 10278 code = BFD_RELOC_386_GOTPC;
10279 else
10280 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10281 }
7b81dfbb
AJ		 10282 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10283 && GOT_symbol
10284 && fixp->fx_addsy == GOT_symbol)
10285 {
10286 code = BFD_RELOC_X86_64_GOTPC64;
10287 }
252b5132
RH		 10288
10289 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10290 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10291 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10292
10293 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10294
3e73aa7c
JH		 10295 if (!use_rela_relocations)
10296 {
10297 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10298 vtable entry to be used in the relocation's section offset. */
10299 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10300 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10301#if defined (OBJ_COFF) && defined (TE_PE)
10302 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10303 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10304 else
10305#endif
c6682705 10306 rel->addend = 0;
3e73aa7c
JH		 10307 }
10308 /* Use the rela in 64bit mode. */
252b5132 10309 else
3e73aa7c 10310 {
862be3fb
L		 10311 if (disallow_64bit_reloc)
10312 switch (code)
10313 {
862be3fb
L		 10314 case BFD_RELOC_X86_64_DTPOFF64:
10315 case BFD_RELOC_X86_64_TPOFF64:
10316 case BFD_RELOC_64_PCREL:
10317 case BFD_RELOC_X86_64_GOTOFF64:
10318 case BFD_RELOC_X86_64_GOT64:
10319 case BFD_RELOC_X86_64_GOTPCREL64:
10320 case BFD_RELOC_X86_64_GOTPC64:
10321 case BFD_RELOC_X86_64_GOTPLT64:
10322 case BFD_RELOC_X86_64_PLTOFF64:
10323 as_bad_where (fixp->fx_file, fixp->fx_line,
10324 _("cannot represent relocation type %s in x32 mode"),
10325 bfd_get_reloc_code_name (code));
10326 break;
10327 default:
10328 break;
10329 }
10330
062cd5e7
AS		 10331 if (!fixp->fx_pcrel)
10332 rel->addend = fixp->fx_offset;
10333 else
10334 switch (code)
10335 {
10336 case BFD_RELOC_X86_64_PLT32:
10337 case BFD_RELOC_X86_64_GOT32:
10338 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 10339 case BFD_RELOC_X86_64_TLSGD:
10340 case BFD_RELOC_X86_64_TLSLD:
10341 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10342 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10343 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10344 rel->addend = fixp->fx_offset - fixp->fx_size;
10345 break;
10346 default:
10347 rel->addend = (section->vma
10348 - fixp->fx_size
10349 + fixp->fx_addnumber
10350 + md_pcrel_from (fixp));
10351 break;
10352 }
3e73aa7c
JH		 10353 }
10354
252b5132
RH		 10355 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10356 if (rel->howto == NULL)
10357 {
10358 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10359 _("cannot represent relocation type %s"),
252b5132
RH		 10360 bfd_get_reloc_code_name (code));
10361 /* Set howto to a garbage value so that we can keep going. */
10362 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10363 gas_assert (rel->howto != NULL);
252b5132
RH		 10364 }
10365
10366 return rel;
10367}
10368
ee86248c 10369#include "tc-i386-intel.c"
54cfded0 10370
a60de03c
JB		 10371void
10372tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10373{
a60de03c
JB		 10374 int saved_naked_reg;
10375 char saved_register_dot;
54cfded0 10376
a60de03c
JB		 10377 saved_naked_reg = allow_naked_reg;
10378 allow_naked_reg = 1;
10379 saved_register_dot = register_chars['.'];
10380 register_chars['.'] = '.';
10381 allow_pseudo_reg = 1;
10382 expression_and_evaluate (exp);
10383 allow_pseudo_reg = 0;
10384 register_chars['.'] = saved_register_dot;
10385 allow_naked_reg = saved_naked_reg;
10386
e96d56a1 10387 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10388 {
a60de03c
JB		 10389 if ((addressT) exp->X_add_number < i386_regtab_size)
10390 {
10391 exp->X_op = O_constant;
10392 exp->X_add_number = i386_regtab[exp->X_add_number]
10393 .dw2_regnum[flag_code >> 1];
10394 }
10395 else
10396 exp->X_op = O_illegal;
54cfded0 10397 }
54cfded0
AM		 10398}
10399
10400void
10401tc_x86_frame_initial_instructions (void)
10402{
a60de03c
JB		 10403 static unsigned int sp_regno[2];
10404
10405 if (!sp_regno[flag_code >> 1])
10406 {
10407 char *saved_input = input_line_pointer;
10408 char sp[][4] = {"esp", "rsp"};
10409 expressionS exp;
a4447b93 10410
a60de03c
JB		 10411 input_line_pointer = sp[flag_code >> 1];
10412 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10413 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10414 sp_regno[flag_code >> 1] = exp.X_add_number;
10415 input_line_pointer = saved_input;
10416 }
a4447b93 10417
61ff971f
L		 10418 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10419 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10420}
d2b2c203 10421
d7921315
L		 10422int
10423x86_dwarf2_addr_size (void)
10424{
10425#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10426 if (x86_elf_abi == X86_64_X32_ABI)
10427 return 4;
10428#endif
10429 return bfd_arch_bits_per_address (stdoutput) / 8;
10430}
10431
d2b2c203
DJ		 10432int
10433i386_elf_section_type (const char *str, size_t len)
10434{
10435 if (flag_code == CODE_64BIT
10436 && len == sizeof ("unwind") - 1
10437 && strncmp (str, "unwind", 6) == 0)
10438 return SHT_X86_64_UNWIND;
10439
10440 return -1;
10441}
bb41ade5 10442
ad5fec3b
EB		 10443#ifdef TE_SOLARIS
10444void
10445i386_solaris_fix_up_eh_frame (segT sec)
10446{
10447 if (flag_code == CODE_64BIT)
10448 elf_section_type (sec) = SHT_X86_64_UNWIND;
10449}
10450#endif
10451
bb41ade5
AM		 10452#ifdef TE_PE
10453void
10454tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10455{
91d6fa6a 10456 expressionS exp;
bb41ade5 10457
91d6fa6a
NC		 10458 exp.X_op = O_secrel;
10459 exp.X_add_symbol = symbol;
10460 exp.X_add_number = 0;
10461 emit_expr (&exp, size);
bb41ade5
AM		 10462}
10463#endif
3b22753a
L		 10464
10465#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10466/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10467
01e1a5bc 10468bfd_vma
3b22753a
L		 10469x86_64_section_letter (int letter, char **ptr_msg)
10470{
10471 if (flag_code == CODE_64BIT)
10472 {
10473 if (letter == 'l')
10474 return SHF_X86_64_LARGE;
10475
8f3bae45 10476 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10477 }
3b22753a 10478 else
8f3bae45 10479 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10480 return -1;
10481}
10482
01e1a5bc 10483bfd_vma
3b22753a
L		 10484x86_64_section_word (char *str, size_t len)
10485{
8620418b 10486 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10487 return SHF_X86_64_LARGE;
10488
10489 return -1;
10490}
10491
10492static void
10493handle_large_common (int small ATTRIBUTE_UNUSED)
10494{
10495 if (flag_code != CODE_64BIT)
10496 {
10497 s_comm_internal (0, elf_common_parse);
10498 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10499 }
10500 else
10501 {
10502 static segT lbss_section;
10503 asection *saved_com_section_ptr = elf_com_section_ptr;
10504 asection *saved_bss_section = bss_section;
10505
10506 if (lbss_section == NULL)
10507 {
10508 flagword applicable;
10509 segT seg = now_seg;
10510 subsegT subseg = now_subseg;
10511
10512 /* The .lbss section is for local .largecomm symbols. */
10513 lbss_section = subseg_new (".lbss", 0);
10514 applicable = bfd_applicable_section_flags (stdoutput);
10515 bfd_set_section_flags (stdoutput, lbss_section,
10516 applicable & SEC_ALLOC);
10517 seg_info (lbss_section)->bss = 1;
10518
10519 subseg_set (seg, subseg);
10520 }
10521
10522 elf_com_section_ptr = &_bfd_elf_large_com_section;
10523 bss_section = lbss_section;
10524
10525 s_comm_internal (0, elf_common_parse);
10526
10527 elf_com_section_ptr = saved_com_section_ptr;
10528 bss_section = saved_bss_section;
10529 }
10530}
10531#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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