projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* spu-tdep.c (spu_get_longjmp_target): New function.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0bfee649 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 LOCKREP_PREFIX. */
63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
67#define LOCKREP_PREFIX 4
68#define REX_PREFIX 5 /* must come last. */
69#define MAX_PREFIXES 6 /* max prefixes per opcode */
70
71/* we define the syntax here (modulo base,index,scale syntax) */
72#define REGISTER_PREFIX '%'
73#define IMMEDIATE_PREFIX '$'
74#define ABSOLUTE_PREFIX '*'
75
76/* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78#define WORD_MNEM_SUFFIX 'w'
79#define BYTE_MNEM_SUFFIX 'b'
80#define SHORT_MNEM_SUFFIX 's'
81#define LONG_MNEM_SUFFIX 'l'
82#define QWORD_MNEM_SUFFIX 'q'
83#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 84#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 85/* Intel Syntax. Use a non-ascii letter since since it never appears
86 in instructions. */
87#define LONG_DOUBLE_MNEM_SUFFIX '\1'
88
89#define END_OF_INSN '\0'
90
91/*
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
96 END.
97 */
98typedef struct
99{
100 const template *start;
101 const template *end;
102}
103templates;
104
105/* 386 operand encoding bytes: see 386 book for details of this. */
106typedef struct
107{
108 unsigned int regmem; /* codes register or memory operand */
109 unsigned int reg; /* codes register operand (or extended opcode) */
110 unsigned int mode; /* how to interpret regmem & reg */
111}
112modrm_byte;
113
114/* x86-64 extension prefix. */
115typedef int rex_byte;
116
6305a203
L		 117/* 386 opcode byte to code indirect addressing. */
118typedef struct
119{
120 unsigned base;
121 unsigned index;
122 unsigned scale;
123}
124sib_byte;
125
6305a203
L		 126/* x86 arch names, types and features */
127typedef struct
128{
129 const char *name; /* arch name */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132}
133arch_entry;
134
e3bb37b5
L		 135static void set_code_flag (int);
136static void set_16bit_gcc_code_flag (int);
137static void set_intel_syntax (int);
1efbbeb4 138static void set_intel_mnemonic (int);
db51cc60 139static void set_allow_index_reg (int);
cb19c032 140static void set_sse_check (int);
e3bb37b5 141static void set_cpu_arch (int);
6482c264 142#ifdef TE_PE
e3bb37b5 143static void pe_directive_secrel (int);
6482c264 144#endif
e3bb37b5
L		 145static void signed_cons (int);
146static char *output_invalid (int c);
ee86248c
JB		 147static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
148 const char *);
149static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
150 const char *);
a7619375 151static int i386_att_operand (char *);
e3bb37b5 152static int i386_intel_operand (char *, int);
ee86248c
JB		 153static int i386_intel_simplify (expressionS *);
154static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 155static const reg_entry *parse_register (char *, char **);
156static char *parse_insn (char *, char *);
157static char *parse_operands (char *, const char *);
158static void swap_operands (void);
4d456e3d 159static void swap_2_operands (int, int);
e3bb37b5
L		 160static void optimize_imm (void);
161static void optimize_disp (void);
fa99fab2 162static const template *match_template (void);
e3bb37b5
L		 163static int check_string (void);
164static int process_suffix (void);
165static int check_byte_reg (void);
166static int check_long_reg (void);
167static int check_qword_reg (void);
168static int check_word_reg (void);
169static int finalize_imm (void);
170static int process_operands (void);
171static const seg_entry *build_modrm_byte (void);
172static void output_insn (void);
173static void output_imm (fragS *, offsetT);
174static void output_disp (fragS *, offsetT);
29b0f896 175#ifndef I386COFF
e3bb37b5 176static void s_bss (int);
252b5132 177#endif
17d4e2a2
L		 178#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
179static void handle_large_common (int small ATTRIBUTE_UNUSED);
180#endif
252b5132 181
a847613f 182static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 183
c0f3af97
L		 184/* VEX prefix. */
185typedef struct
186{
187 /* VEX prefix is either 2 byte or 3 byte. */
188 unsigned char bytes[3];
189 unsigned int length;
190 /* Destination or source register specifier. */
191 const reg_entry *register_specifier;
192} vex_prefix;
193
252b5132 194/* 'md_assemble ()' gathers together information and puts it into a
47926f60 195 i386_insn. */
252b5132 196
520dc8e8
AM		 197union i386_op
198 {
199 expressionS *disps;
200 expressionS *imms;
201 const reg_entry *regs;
202 };
203
252b5132
RH		 204struct _i386_insn
205 {
47926f60 206 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 207 template tm;
208
7d5e4556
L		 209 /* SUFFIX holds the instruction size suffix for byte, word, dword
210 or qword, if given. */
252b5132
RH		 211 char suffix;
212
47926f60 213 /* OPERANDS gives the number of given operands. */
252b5132
RH		 214 unsigned int operands;
215
216 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
217 of given register, displacement, memory operands and immediate
47926f60 218 operands. */
252b5132
RH		 219 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
220
221 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 222 use OP[i] for the corresponding operand. */
40fb9820 223 i386_operand_type types[MAX_OPERANDS];
252b5132 224
520dc8e8
AM		 225 /* Displacement expression, immediate expression, or register for each
226 operand. */
227 union i386_op op[MAX_OPERANDS];
252b5132 228
3e73aa7c
JH		 229 /* Flags for operands. */
230 unsigned int flags[MAX_OPERANDS];
231#define Operand_PCrel 1
232
252b5132 233 /* Relocation type for operand */
f86103b7 234 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 235
252b5132
RH		 236 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
237 the base index byte below. */
238 const reg_entry *base_reg;
239 const reg_entry *index_reg;
240 unsigned int log2_scale_factor;
241
242 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 243 explicit segment overrides are given. */
ce8a8b2f 244 const seg_entry *seg[2];
252b5132
RH		 245
246 /* PREFIX holds all the given prefix opcodes (usually null).
247 PREFIXES is the number of prefix opcodes. */
248 unsigned int prefixes;
249 unsigned char prefix[MAX_PREFIXES];
250
251 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 252 addressing modes of this insn are encoded. */
252b5132 253 modrm_byte rm;
3e73aa7c 254 rex_byte rex;
252b5132 255 sib_byte sib;
c0f3af97 256 vex_prefix vex;
b6169b20
L		 257
258 /* Swap operand in encoding. */
259 unsigned int swap_operand : 1;
252b5132
RH		 260 };
261
262typedef struct _i386_insn i386_insn;
263
264/* List of chars besides those in app.c:symbol_chars that can start an
265 operand. Used to prevent the scrubber eating vital white-space. */
32137342 266const char extra_symbol_chars[] = "*%-(["
252b5132 267#ifdef LEX_AT
32137342
NC		 268 "@"
269#endif
270#ifdef LEX_QM
271 "?"
252b5132 272#endif
32137342 273 ;
252b5132 274
29b0f896
AM		 275#if (defined (TE_I386AIX) \
276 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 277 && !defined (TE_GNU) \
29b0f896 278 && !defined (TE_LINUX) \
32137342 279 && !defined (TE_NETWARE) \
29b0f896
AM		 280 && !defined (TE_FreeBSD) \
281 && !defined (TE_NetBSD)))
252b5132 282/* This array holds the chars that always start a comment. If the
b3b91714
AM		 283 pre-processor is disabled, these aren't very useful. The option
284 --divide will remove '/' from this list. */
285const char *i386_comment_chars = "#/";
286#define SVR4_COMMENT_CHARS 1
252b5132 287#define PREFIX_SEPARATOR '\\'
252b5132 288
b3b91714
AM		 289#else
290const char *i386_comment_chars = "#";
291#define PREFIX_SEPARATOR '/'
292#endif
293
252b5132
RH		 294/* This array holds the chars that only start a comment at the beginning of
295 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 296 .line and .file directives will appear in the pre-processed output.
297 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 298 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 299 #NO_APP at the beginning of its output.
300 Also note that comments started like this one will always work if
252b5132 301 '/' isn't otherwise defined. */
b3b91714 302const char line_comment_chars[] = "#/";
252b5132 303
63a0b638 304const char line_separator_chars[] = ";";
252b5132 305
ce8a8b2f
AM		 306/* Chars that can be used to separate mant from exp in floating point
307 nums. */
252b5132
RH		 308const char EXP_CHARS[] = "eE";
309
ce8a8b2f
AM		 310/* Chars that mean this number is a floating point constant
311 As in 0f12.456
312 or 0d1.2345e12. */
252b5132
RH		 313const char FLT_CHARS[] = "fFdDxX";
314
ce8a8b2f 315/* Tables for lexical analysis. */
252b5132
RH		 316static char mnemonic_chars[256];
317static char register_chars[256];
318static char operand_chars[256];
319static char identifier_chars[256];
320static char digit_chars[256];
321
ce8a8b2f 322/* Lexical macros. */
252b5132
RH		 323#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
324#define is_operand_char(x) (operand_chars[(unsigned char) x])
325#define is_register_char(x) (register_chars[(unsigned char) x])
326#define is_space_char(x) ((x) == ' ')
327#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
328#define is_digit_char(x) (digit_chars[(unsigned char) x])
329
0234cb7c 330/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 331static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
332
333/* md_assemble() always leaves the strings it's passed unaltered. To
334 effect this we maintain a stack of saved characters that we've smashed
335 with '\0's (indicating end of strings for various sub-fields of the
47926f60 336 assembler instruction). */
252b5132 337static char save_stack[32];
ce8a8b2f 338static char *save_stack_p;
252b5132
RH		 339#define END_STRING_AND_SAVE(s) \
340 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
341#define RESTORE_END_STRING(s) \
342 do { *(s) = *--save_stack_p; } while (0)
343
47926f60 344/* The instruction we're assembling. */
252b5132
RH		 345static i386_insn i;
346
347/* Possible templates for current insn. */
348static const templates *current_templates;
349
31b2323c
L		 350/* Per instruction expressionS buffers: max displacements & immediates. */
351static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
352static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 353
47926f60 354/* Current operand we are working on. */
ee86248c 355static int this_operand = -1;
252b5132 356
3e73aa7c
JH		 357/* We support four different modes. FLAG_CODE variable is used to distinguish
358 these. */
359
360enum flag_code {
361 CODE_32BIT,
362 CODE_16BIT,
363 CODE_64BIT };
364
365static enum flag_code flag_code;
4fa24527 366static unsigned int object_64bit;
3e73aa7c
JH		 367static int use_rela_relocations = 0;
368
369/* The names used to print error messages. */
b77a7acd 370static const char *flag_code_names[] =
3e73aa7c
JH		 371 {
372 "32",
373 "16",
374 "64"
375 };
252b5132 376
47926f60
KH		 377/* 1 for intel syntax,
378 0 if att syntax. */
379static int intel_syntax = 0;
252b5132 380
1efbbeb4
L		 381/* 1 for intel mnemonic,
382 0 if att mnemonic. */
383static int intel_mnemonic = !SYSV386_COMPAT;
384
5209009a 385/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 386static int old_gcc = OLDGCC_COMPAT;
387
a60de03c
JB		 388/* 1 if pseudo registers are permitted. */
389static int allow_pseudo_reg = 0;
390
47926f60
KH		 391/* 1 if register prefix % not required. */
392static int allow_naked_reg = 0;
252b5132 393
ba104c83 394/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 395static int allow_index_reg = 0;
396
daf50ae7
L		 397static enum
398 {
399 sse_check_none = 0,
400 sse_check_warning,
401 sse_check_error
402 }
403sse_check;
404
2ca3ace5
L		 405/* Register prefix used for error message. */
406static const char *register_prefix = "%";
407
47926f60
KH		 408/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
409 leave, push, and pop instructions so that gcc has the same stack
410 frame as in 32 bit mode. */
411static char stackop_size = '\0';
eecb386c 412
12b55ccc
L		 413/* Non-zero to optimize code alignment. */
414int optimize_align_code = 1;
415
47926f60
KH		 416/* Non-zero to quieten some warnings. */
417static int quiet_warnings = 0;
a38cf1db 418
47926f60
KH		 419/* CPU name. */
420static const char *cpu_arch_name = NULL;
6305a203 421static char *cpu_sub_arch_name = NULL;
a38cf1db 422
47926f60 423/* CPU feature flags. */
40fb9820
L		 424static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
425
ccc9c027
L		 426/* If we have selected a cpu we are generating instructions for. */
427static int cpu_arch_tune_set = 0;
428
9103f4f4 429/* Cpu we are generating instructions for. */
fbf3f584 430enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 431
432/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 433static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 434
ccc9c027 435/* CPU instruction set architecture used. */
fbf3f584 436enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 437
9103f4f4 438/* CPU feature flags of instruction set architecture used. */
fbf3f584 439i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 440
fddf5b5b
AM		 441/* If set, conditional jumps are not automatically promoted to handle
442 larger than a byte offset. */
443static unsigned int no_cond_jump_promotion = 0;
444
c0f3af97
L		 445/* Encode SSE instructions with VEX prefix. */
446static unsigned int sse2avx;
447
29b0f896 448/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 449static symbolS *GOT_symbol;
29b0f896 450
a4447b93
RH		 451/* The dwarf2 return column, adjusted for 32 or 64 bit. */
452unsigned int x86_dwarf2_return_column;
453
454/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
455int x86_cie_data_alignment;
456
252b5132 457/* Interface to relax_segment.
fddf5b5b
AM		 458 There are 3 major relax states for 386 jump insns because the
459 different types of jumps add different sizes to frags when we're
460 figuring out what sort of jump to choose to reach a given label. */
252b5132 461
47926f60 462/* Types. */
93c2a809
AM		 463#define UNCOND_JUMP 0
464#define COND_JUMP 1
465#define COND_JUMP86 2
fddf5b5b 466
47926f60 467/* Sizes. */
252b5132
RH		 468#define CODE16 1
469#define SMALL 0
29b0f896 470#define SMALL16 (SMALL | CODE16)
252b5132 471#define BIG 2
29b0f896 472#define BIG16 (BIG | CODE16)
252b5132
RH		 473
474#ifndef INLINE
475#ifdef __GNUC__
476#define INLINE __inline__
477#else
478#define INLINE
479#endif
480#endif
481
fddf5b5b
AM		 482#define ENCODE_RELAX_STATE(type, size) \
483 ((relax_substateT) (((type) << 2) | (size)))
484#define TYPE_FROM_RELAX_STATE(s) \
485 ((s) >> 2)
486#define DISP_SIZE_FROM_RELAX_STATE(s) \
487 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 488
489/* This table is used by relax_frag to promote short jumps to long
490 ones where necessary. SMALL (short) jumps may be promoted to BIG
491 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
492 don't allow a short jump in a 32 bit code segment to be promoted to
493 a 16 bit offset jump because it's slower (requires data size
494 prefix), and doesn't work, unless the destination is in the bottom
495 64k of the code segment (The top 16 bits of eip are zeroed). */
496
497const relax_typeS md_relax_table[] =
498{
24eab124
AM		 499 /* The fields are:
500 1) most positive reach of this state,
501 2) most negative reach of this state,
93c2a809 502 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 503 4) which index into the table to try if we can't fit into this one. */
252b5132 504
fddf5b5b 505 /* UNCOND_JUMP states. */
93c2a809
AM		 506 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
507 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
508 /* dword jmp adds 4 bytes to frag:
509 0 extra opcode bytes, 4 displacement bytes. */
252b5132 510 {0, 0, 4, 0},
93c2a809
AM		 511 /* word jmp adds 2 byte2 to frag:
512 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 513 {0, 0, 2, 0},
514
93c2a809
AM		 515 /* COND_JUMP states. */
516 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
518 /* dword conditionals adds 5 bytes to frag:
519 1 extra opcode byte, 4 displacement bytes. */
520 {0, 0, 5, 0},
fddf5b5b 521 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 522 1 extra opcode byte, 2 displacement bytes. */
523 {0, 0, 3, 0},
524
525 /* COND_JUMP86 states. */
526 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
528 /* dword conditionals adds 5 bytes to frag:
529 1 extra opcode byte, 4 displacement bytes. */
530 {0, 0, 5, 0},
531 /* word conditionals add 4 bytes to frag:
532 1 displacement byte and a 3 byte long branch insn. */
533 {0, 0, 4, 0}
252b5132
RH		 534};
535
9103f4f4
L		 536static const arch_entry cpu_arch[] =
537{
6305a203
L		 538 { "generic32", PROCESSOR_GENERIC32,
539 CPU_GENERIC32_FLAGS },
540 { "generic64", PROCESSOR_GENERIC64,
541 CPU_GENERIC64_FLAGS },
542 { "i8086", PROCESSOR_UNKNOWN,
543 CPU_NONE_FLAGS },
544 { "i186", PROCESSOR_UNKNOWN,
545 CPU_I186_FLAGS },
546 { "i286", PROCESSOR_UNKNOWN,
547 CPU_I286_FLAGS },
548 { "i386", PROCESSOR_I386,
549 CPU_I386_FLAGS },
550 { "i486", PROCESSOR_I486,
551 CPU_I486_FLAGS },
552 { "i586", PROCESSOR_PENTIUM,
553 CPU_I586_FLAGS },
554 { "i686", PROCESSOR_PENTIUMPRO,
555 CPU_I686_FLAGS },
556 { "pentium", PROCESSOR_PENTIUM,
557 CPU_I586_FLAGS },
558 { "pentiumpro", PROCESSOR_PENTIUMPRO,
559 CPU_I686_FLAGS },
560 { "pentiumii", PROCESSOR_PENTIUMPRO,
561 CPU_P2_FLAGS },
562 { "pentiumiii",PROCESSOR_PENTIUMPRO,
563 CPU_P3_FLAGS },
564 { "pentium4", PROCESSOR_PENTIUM4,
565 CPU_P4_FLAGS },
566 { "prescott", PROCESSOR_NOCONA,
567 CPU_CORE_FLAGS },
568 { "nocona", PROCESSOR_NOCONA,
569 CPU_NOCONA_FLAGS },
570 { "yonah", PROCESSOR_CORE,
571 CPU_CORE_FLAGS },
572 { "core", PROCESSOR_CORE,
573 CPU_CORE_FLAGS },
574 { "merom", PROCESSOR_CORE2,
575 CPU_CORE2_FLAGS },
576 { "core2", PROCESSOR_CORE2,
577 CPU_CORE2_FLAGS },
bd5295b2
L		 578 { "corei7", PROCESSOR_COREI7,
579 CPU_COREI7_FLAGS },
6305a203
L		 580 { "k6", PROCESSOR_K6,
581 CPU_K6_FLAGS },
582 { "k6_2", PROCESSOR_K6,
583 CPU_K6_2_FLAGS },
584 { "athlon", PROCESSOR_ATHLON,
585 CPU_ATHLON_FLAGS },
586 { "sledgehammer", PROCESSOR_K8,
587 CPU_K8_FLAGS },
588 { "opteron", PROCESSOR_K8,
589 CPU_K8_FLAGS },
590 { "k8", PROCESSOR_K8,
591 CPU_K8_FLAGS },
592 { "amdfam10", PROCESSOR_AMDFAM10,
593 CPU_AMDFAM10_FLAGS },
594 { ".mmx", PROCESSOR_UNKNOWN,
595 CPU_MMX_FLAGS },
596 { ".sse", PROCESSOR_UNKNOWN,
597 CPU_SSE_FLAGS },
598 { ".sse2", PROCESSOR_UNKNOWN,
599 CPU_SSE2_FLAGS },
600 { ".sse3", PROCESSOR_UNKNOWN,
601 CPU_SSE3_FLAGS },
602 { ".ssse3", PROCESSOR_UNKNOWN,
603 CPU_SSSE3_FLAGS },
604 { ".sse4.1", PROCESSOR_UNKNOWN,
605 CPU_SSE4_1_FLAGS },
606 { ".sse4.2", PROCESSOR_UNKNOWN,
607 CPU_SSE4_2_FLAGS },
608 { ".sse4", PROCESSOR_UNKNOWN,
609 CPU_SSE4_2_FLAGS },
c0f3af97
L		 610 { ".avx", PROCESSOR_UNKNOWN,
611 CPU_AVX_FLAGS },
6305a203
L		 612 { ".vmx", PROCESSOR_UNKNOWN,
613 CPU_VMX_FLAGS },
614 { ".smx", PROCESSOR_UNKNOWN,
615 CPU_SMX_FLAGS },
f03fe4c1
L		 616 { ".xsave", PROCESSOR_UNKNOWN,
617 CPU_XSAVE_FLAGS },
c0f3af97
L		 618 { ".aes", PROCESSOR_UNKNOWN,
619 CPU_AES_FLAGS },
594ab6a3
L		 620 { ".pclmul", PROCESSOR_UNKNOWN,
621 CPU_PCLMUL_FLAGS },
c0f3af97 622 { ".clmul", PROCESSOR_UNKNOWN,
594ab6a3 623 CPU_PCLMUL_FLAGS },
c0f3af97
L		 624 { ".fma", PROCESSOR_UNKNOWN,
625 CPU_FMA_FLAGS },
f1f8f695
L		 626 { ".movbe", PROCESSOR_UNKNOWN,
627 CPU_MOVBE_FLAGS },
628 { ".ept", PROCESSOR_UNKNOWN,
629 CPU_EPT_FLAGS },
bd5295b2
L		 630 { ".clflush", PROCESSOR_UNKNOWN,
631 CPU_CLFLUSH_FLAGS },
632 { ".syscall", PROCESSOR_UNKNOWN,
633 CPU_SYSCALL_FLAGS },
1b7f3fb0
L		 634 { ".rdtscp", PROCESSOR_UNKNOWN,
635 CPU_RDTSCP_FLAGS },
6305a203
L		 636 { ".3dnow", PROCESSOR_UNKNOWN,
637 CPU_3DNOW_FLAGS },
638 { ".3dnowa", PROCESSOR_UNKNOWN,
639 CPU_3DNOWA_FLAGS },
640 { ".padlock", PROCESSOR_UNKNOWN,
641 CPU_PADLOCK_FLAGS },
642 { ".pacifica", PROCESSOR_UNKNOWN,
643 CPU_SVME_FLAGS },
644 { ".svme", PROCESSOR_UNKNOWN,
645 CPU_SVME_FLAGS },
646 { ".sse4a", PROCESSOR_UNKNOWN,
647 CPU_SSE4A_FLAGS },
648 { ".abm", PROCESSOR_UNKNOWN,
649 CPU_ABM_FLAGS },
e413e4e9
AM		 650};
651
704209c0 652#ifdef I386COFF
a6c24e68
NC		 653/* Like s_lcomm_internal in gas/read.c but the alignment string
654 is allowed to be optional. */
655
656static symbolS *
657pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
658{
659 addressT align = 0;
660
661 SKIP_WHITESPACE ();
662
663 if (needs_align
664 && *input_line_pointer == ',')
665 {
666 align = parse_align (needs_align - 1);
667
668 if (align == (addressT) -1)
669 return NULL;
670 }
671 else
672 {
673 if (size >= 8)
674 align = 3;
675 else if (size >= 4)
676 align = 2;
677 else if (size >= 2)
678 align = 1;
679 else
680 align = 0;
681 }
682
683 bss_alloc (symbolP, size, align);
684 return symbolP;
685}
686
704209c0 687static void
a6c24e68
NC		 688pe_lcomm (int needs_align)
689{
690 s_comm_internal (needs_align * 2, pe_lcomm_internal);
691}
704209c0 692#endif
a6c24e68 693
29b0f896
AM		 694const pseudo_typeS md_pseudo_table[] =
695{
696#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
697 {"align", s_align_bytes, 0},
698#else
699 {"align", s_align_ptwo, 0},
700#endif
701 {"arch", set_cpu_arch, 0},
702#ifndef I386COFF
703 {"bss", s_bss, 0},
a6c24e68
NC		 704#else
705 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 706#endif
707 {"ffloat", float_cons, 'f'},
708 {"dfloat", float_cons, 'd'},
709 {"tfloat", float_cons, 'x'},
710 {"value", cons, 2},
d182319b 711 {"slong", signed_cons, 4},
29b0f896
AM		 712 {"noopt", s_ignore, 0},
713 {"optim", s_ignore, 0},
714 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
715 {"code16", set_code_flag, CODE_16BIT},
716 {"code32", set_code_flag, CODE_32BIT},
717 {"code64", set_code_flag, CODE_64BIT},
718 {"intel_syntax", set_intel_syntax, 1},
719 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 720 {"intel_mnemonic", set_intel_mnemonic, 1},
721 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 722 {"allow_index_reg", set_allow_index_reg, 1},
723 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 724 {"sse_check", set_sse_check, 0},
3b22753a
L		 725#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
726 {"largecomm", handle_large_common, 0},
07a53e5c 727#else
e3bb37b5 728 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 729 {"loc", dwarf2_directive_loc, 0},
730 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 731#endif
6482c264
NC		 732#ifdef TE_PE
733 {"secrel32", pe_directive_secrel, 0},
734#endif
29b0f896
AM		 735 {0, 0, 0}
736};
737
738/* For interface with expression (). */
739extern char *input_line_pointer;
740
741/* Hash table for instruction mnemonic lookup. */
742static struct hash_control *op_hash;
743
744/* Hash table for register lookup. */
745static struct hash_control *reg_hash;
746\f
252b5132 747void
e3bb37b5 748i386_align_code (fragS *fragP, int count)
252b5132 749{
ce8a8b2f
AM		 750 /* Various efficient no-op patterns for aligning code labels.
751 Note: Don't try to assemble the instructions in the comments.
752 0L and 0w are not legal. */
252b5132
RH		 753 static const char f32_1[] =
754 {0x90}; /* nop */
755 static const char f32_2[] =
ccc9c027 756 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 757 static const char f32_3[] =
758 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
759 static const char f32_4[] =
760 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
761 static const char f32_5[] =
762 {0x90, /* nop */
763 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
764 static const char f32_6[] =
765 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
766 static const char f32_7[] =
767 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
768 static const char f32_8[] =
769 {0x90, /* nop */
770 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
771 static const char f32_9[] =
772 {0x89,0xf6, /* movl %esi,%esi */
773 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
774 static const char f32_10[] =
775 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
776 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
777 static const char f32_11[] =
778 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
779 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
780 static const char f32_12[] =
781 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
782 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
783 static const char f32_13[] =
784 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
785 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
786 static const char f32_14[] =
787 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
788 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 789 static const char f16_3[] =
790 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 791 static const char f16_4[] =
792 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
793 static const char f16_5[] =
794 {0x90, /* nop */
795 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
796 static const char f16_6[] =
797 {0x89,0xf6, /* mov %si,%si */
798 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
799 static const char f16_7[] =
800 {0x8d,0x74,0x00, /* lea 0(%si),%si */
801 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
802 static const char f16_8[] =
803 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
804 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 805 static const char jump_31[] =
806 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
807 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
808 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
809 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 810 static const char *const f32_patt[] = {
811 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 812 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 813 };
814 static const char *const f16_patt[] = {
76bc74dc 815 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 816 };
ccc9c027
L		 817 /* nopl (%[re]ax) */
818 static const char alt_3[] =
819 {0x0f,0x1f,0x00};
820 /* nopl 0(%[re]ax) */
821 static const char alt_4[] =
822 {0x0f,0x1f,0x40,0x00};
823 /* nopl 0(%[re]ax,%[re]ax,1) */
824 static const char alt_5[] =
825 {0x0f,0x1f,0x44,0x00,0x00};
826 /* nopw 0(%[re]ax,%[re]ax,1) */
827 static const char alt_6[] =
828 {0x66,0x0f,0x1f,0x44,0x00,0x00};
829 /* nopl 0L(%[re]ax) */
830 static const char alt_7[] =
831 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
832 /* nopl 0L(%[re]ax,%[re]ax,1) */
833 static const char alt_8[] =
834 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
835 /* nopw 0L(%[re]ax,%[re]ax,1) */
836 static const char alt_9[] =
837 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
838 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
839 static const char alt_10[] =
840 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
841 /* data16
842 nopw %cs:0L(%[re]ax,%[re]ax,1) */
843 static const char alt_long_11[] =
844 {0x66,
845 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
846 /* data16
847 data16
848 nopw %cs:0L(%[re]ax,%[re]ax,1) */
849 static const char alt_long_12[] =
850 {0x66,
851 0x66,
852 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
853 /* data16
854 data16
855 data16
856 nopw %cs:0L(%[re]ax,%[re]ax,1) */
857 static const char alt_long_13[] =
858 {0x66,
859 0x66,
860 0x66,
861 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
862 /* data16
863 data16
864 data16
865 data16
866 nopw %cs:0L(%[re]ax,%[re]ax,1) */
867 static const char alt_long_14[] =
868 {0x66,
869 0x66,
870 0x66,
871 0x66,
872 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
873 /* data16
874 data16
875 data16
876 data16
877 data16
878 nopw %cs:0L(%[re]ax,%[re]ax,1) */
879 static const char alt_long_15[] =
880 {0x66,
881 0x66,
882 0x66,
883 0x66,
884 0x66,
885 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
886 /* nopl 0(%[re]ax,%[re]ax,1)
887 nopw 0(%[re]ax,%[re]ax,1) */
888 static const char alt_short_11[] =
889 {0x0f,0x1f,0x44,0x00,0x00,
890 0x66,0x0f,0x1f,0x44,0x00,0x00};
891 /* nopw 0(%[re]ax,%[re]ax,1)
892 nopw 0(%[re]ax,%[re]ax,1) */
893 static const char alt_short_12[] =
894 {0x66,0x0f,0x1f,0x44,0x00,0x00,
895 0x66,0x0f,0x1f,0x44,0x00,0x00};
896 /* nopw 0(%[re]ax,%[re]ax,1)
897 nopl 0L(%[re]ax) */
898 static const char alt_short_13[] =
899 {0x66,0x0f,0x1f,0x44,0x00,0x00,
900 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
901 /* nopl 0L(%[re]ax)
902 nopl 0L(%[re]ax) */
903 static const char alt_short_14[] =
904 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
905 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
906 /* nopl 0L(%[re]ax)
907 nopl 0L(%[re]ax,%[re]ax,1) */
908 static const char alt_short_15[] =
909 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
910 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
911 static const char *const alt_short_patt[] = {
912 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
913 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
914 alt_short_14, alt_short_15
915 };
916 static const char *const alt_long_patt[] = {
917 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
918 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
919 alt_long_14, alt_long_15
920 };
252b5132 921
76bc74dc
L		 922 /* Only align for at least a positive non-zero boundary. */
923 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 924 return;
3e73aa7c 925
ccc9c027
L		 926 /* We need to decide which NOP sequence to use for 32bit and
927 64bit. When -mtune= is used:
4eed87de 928
76bc74dc
L		 929 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
930 PROCESSOR_GENERIC32, f32_patt will be used.
931 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 932 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
933 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc
L		 934 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
935 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 936
76bc74dc
L		 937 When -mtune= isn't used, alt_long_patt will be used if
938 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
939 be used.
ccc9c027
L		 940
941 When -march= or .arch is used, we can't use anything beyond
942 cpu_arch_isa_flags. */
943
944 if (flag_code == CODE_16BIT)
945 {
ccc9c027 946 if (count > 8)
33fef721 947 {
76bc74dc
L		 948 memcpy (fragP->fr_literal + fragP->fr_fix,
949 jump_31, count);
950 /* Adjust jump offset. */
951 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 952 }
76bc74dc
L		 953 else
954 memcpy (fragP->fr_literal + fragP->fr_fix,
955 f16_patt[count - 1], count);
252b5132 956 }
33fef721 957 else
ccc9c027
L		 958 {
959 const char *const *patt = NULL;
960
fbf3f584 961 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 962 {
963 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
964 switch (cpu_arch_tune)
965 {
966 case PROCESSOR_UNKNOWN:
967 /* We use cpu_arch_isa_flags to check if we SHOULD
968 optimize for Cpu686. */
fbf3f584 969 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
76bc74dc 970 patt = alt_long_patt;
ccc9c027
L		 971 else
972 patt = f32_patt;
973 break;
ccc9c027
L		 974 case PROCESSOR_PENTIUMPRO:
975 case PROCESSOR_PENTIUM4:
976 case PROCESSOR_NOCONA:
ef05d495 977 case PROCESSOR_CORE:
76bc74dc 978 case PROCESSOR_CORE2:
bd5295b2 979 case PROCESSOR_COREI7:
76bc74dc
L		 980 case PROCESSOR_GENERIC64:
981 patt = alt_long_patt;
982 break;
ccc9c027
L		 983 case PROCESSOR_K6:
984 case PROCESSOR_ATHLON:
985 case PROCESSOR_K8:
4eed87de 986 case PROCESSOR_AMDFAM10:
ccc9c027
L		 987 patt = alt_short_patt;
988 break;
76bc74dc 989 case PROCESSOR_I386:
ccc9c027
L		 990 case PROCESSOR_I486:
991 case PROCESSOR_PENTIUM:
992 case PROCESSOR_GENERIC32:
993 patt = f32_patt;
994 break;
4eed87de 995 }
ccc9c027
L		 996 }
997 else
998 {
fbf3f584 999 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1000 {
1001 case PROCESSOR_UNKNOWN:
e6a14101 1002 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1003 PROCESSOR_UNKNOWN. */
1004 abort ();
1005 break;
1006
76bc74dc 1007 case PROCESSOR_I386:
ccc9c027
L		 1008 case PROCESSOR_I486:
1009 case PROCESSOR_PENTIUM:
ccc9c027
L		 1010 case PROCESSOR_K6:
1011 case PROCESSOR_ATHLON:
1012 case PROCESSOR_K8:
4eed87de 1013 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1014 case PROCESSOR_GENERIC32:
1015 /* We use cpu_arch_isa_flags to check if we CAN optimize
1016 for Cpu686. */
fbf3f584 1017 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1018 patt = alt_short_patt;
1019 else
1020 patt = f32_patt;
1021 break;
76bc74dc
L		 1022 case PROCESSOR_PENTIUMPRO:
1023 case PROCESSOR_PENTIUM4:
1024 case PROCESSOR_NOCONA:
1025 case PROCESSOR_CORE:
ef05d495 1026 case PROCESSOR_CORE2:
bd5295b2 1027 case PROCESSOR_COREI7:
fbf3f584 1028 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1029 patt = alt_long_patt;
1030 else
1031 patt = f32_patt;
1032 break;
1033 case PROCESSOR_GENERIC64:
76bc74dc 1034 patt = alt_long_patt;
ccc9c027 1035 break;
4eed87de 1036 }
ccc9c027
L		 1037 }
1038
76bc74dc
L		 1039 if (patt == f32_patt)
1040 {
1041 /* If the padding is less than 15 bytes, we use the normal
1042 ones. Otherwise, we use a jump instruction and adjust
1043 its offset. */
1044 if (count < 15)
1045 memcpy (fragP->fr_literal + fragP->fr_fix,
1046 patt[count - 1], count);
1047 else
1048 {
1049 memcpy (fragP->fr_literal + fragP->fr_fix,
1050 jump_31, count);
1051 /* Adjust jump offset. */
1052 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1053 }
1054 }
1055 else
1056 {
1057 /* Maximum length of an instruction is 15 byte. If the
1058 padding is greater than 15 bytes and we don't use jump,
1059 we have to break it into smaller pieces. */
1060 int padding = count;
1061 while (padding > 15)
1062 {
1063 padding -= 15;
1064 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1065 patt [14], 15);
1066 }
1067
1068 if (padding)
1069 memcpy (fragP->fr_literal + fragP->fr_fix,
1070 patt [padding - 1], padding);
1071 }
ccc9c027 1072 }
33fef721 1073 fragP->fr_var = count;
252b5132
RH		 1074}
1075
c6fb90c8 1076static INLINE int
0dfbf9d7 1077operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1078{
0dfbf9d7 1079 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1080 {
1081 case 3:
0dfbf9d7 1082 if (x->array[2])
c6fb90c8
L		 1083 return 0;
1084 case 2:
0dfbf9d7 1085 if (x->array[1])
c6fb90c8
L		 1086 return 0;
1087 case 1:
0dfbf9d7 1088 return !x->array[0];
c6fb90c8
L		 1089 default:
1090 abort ();
1091 }
40fb9820
L		 1092}
1093
c6fb90c8 1094static INLINE void
0dfbf9d7 1095operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1096{
0dfbf9d7 1097 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1098 {
1099 case 3:
0dfbf9d7 1100 x->array[2] = v;
c6fb90c8 1101 case 2:
0dfbf9d7 1102 x->array[1] = v;
c6fb90c8 1103 case 1:
0dfbf9d7 1104 x->array[0] = v;
c6fb90c8
L		 1105 break;
1106 default:
1107 abort ();
1108 }
1109}
40fb9820 1110
c6fb90c8 1111static INLINE int
0dfbf9d7
L		 1112operand_type_equal (const union i386_operand_type *x,
1113 const union i386_operand_type *y)
c6fb90c8 1114{
0dfbf9d7 1115 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1116 {
1117 case 3:
0dfbf9d7 1118 if (x->array[2] != y->array[2])
c6fb90c8
L		 1119 return 0;
1120 case 2:
0dfbf9d7 1121 if (x->array[1] != y->array[1])
c6fb90c8
L		 1122 return 0;
1123 case 1:
0dfbf9d7 1124 return x->array[0] == y->array[0];
c6fb90c8
L		 1125 break;
1126 default:
1127 abort ();
1128 }
1129}
40fb9820 1130
0dfbf9d7
L		 1131static INLINE int
1132cpu_flags_all_zero (const union i386_cpu_flags *x)
1133{
1134 switch (ARRAY_SIZE(x->array))
1135 {
1136 case 3:
1137 if (x->array[2])
1138 return 0;
1139 case 2:
1140 if (x->array[1])
1141 return 0;
1142 case 1:
1143 return !x->array[0];
1144 default:
1145 abort ();
1146 }
1147}
1148
1149static INLINE void
1150cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1151{
1152 switch (ARRAY_SIZE(x->array))
1153 {
1154 case 3:
1155 x->array[2] = v;
1156 case 2:
1157 x->array[1] = v;
1158 case 1:
1159 x->array[0] = v;
1160 break;
1161 default:
1162 abort ();
1163 }
1164}
1165
1166static INLINE int
1167cpu_flags_equal (const union i386_cpu_flags *x,
1168 const union i386_cpu_flags *y)
1169{
1170 switch (ARRAY_SIZE(x->array))
1171 {
1172 case 3:
1173 if (x->array[2] != y->array[2])
1174 return 0;
1175 case 2:
1176 if (x->array[1] != y->array[1])
1177 return 0;
1178 case 1:
1179 return x->array[0] == y->array[0];
1180 break;
1181 default:
1182 abort ();
1183 }
1184}
c6fb90c8
L		 1185
1186static INLINE int
1187cpu_flags_check_cpu64 (i386_cpu_flags f)
1188{
1189 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1190 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1191}
1192
c6fb90c8
L		 1193static INLINE i386_cpu_flags
1194cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1195{
c6fb90c8
L		 1196 switch (ARRAY_SIZE (x.array))
1197 {
1198 case 3:
1199 x.array [2] &= y.array [2];
1200 case 2:
1201 x.array [1] &= y.array [1];
1202 case 1:
1203 x.array [0] &= y.array [0];
1204 break;
1205 default:
1206 abort ();
1207 }
1208 return x;
1209}
40fb9820 1210
c6fb90c8
L		 1211static INLINE i386_cpu_flags
1212cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1213{
c6fb90c8 1214 switch (ARRAY_SIZE (x.array))
40fb9820 1215 {
c6fb90c8
L		 1216 case 3:
1217 x.array [2] |= y.array [2];
1218 case 2:
1219 x.array [1] |= y.array [1];
1220 case 1:
1221 x.array [0] |= y.array [0];
40fb9820
L		 1222 break;
1223 default:
1224 abort ();
1225 }
40fb9820
L		 1226 return x;
1227}
1228
c0f3af97
L		 1229#define CPU_FLAGS_ARCH_MATCH 0x1
1230#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1231#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1232#define CPU_FLAGS_PCLMUL_MATCH 0x8
1233#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1234
a5ff0eb2 1235#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1236 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1237 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1238#define CPU_FLAGS_PERFECT_MATCH \
1239 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1240
1241/* Return CPU flags match bits. */
3629bb00 1242
40fb9820 1243static int
c0f3af97 1244cpu_flags_match (const template *t)
40fb9820 1245{
c0f3af97
L		 1246 i386_cpu_flags x = t->cpu_flags;
1247 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1248
1249 x.bitfield.cpu64 = 0;
1250 x.bitfield.cpuno64 = 0;
1251
0dfbf9d7 1252 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1253 {
1254 /* This instruction is available on all archs. */
1255 match |= CPU_FLAGS_32BIT_MATCH;
1256 }
3629bb00
L		 1257 else
1258 {
c0f3af97 1259 /* This instruction is available only on some archs. */
3629bb00
L		 1260 i386_cpu_flags cpu = cpu_arch_flags;
1261
1262 cpu.bitfield.cpu64 = 0;
1263 cpu.bitfield.cpuno64 = 0;
1264 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1265 if (!cpu_flags_all_zero (&cpu))
1266 {
a5ff0eb2
L		 1267 if (x.bitfield.cpuavx)
1268 {
ce2f5b3c 1269 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1270 if (cpu.bitfield.cpuavx)
1271 {
1272 /* Check SSE2AVX. */
1273 if (!t->opcode_modifier.sse2avx|| sse2avx)
1274 {
1275 match |= (CPU_FLAGS_ARCH_MATCH
1276 | CPU_FLAGS_AVX_MATCH);
1277 /* Check AES. */
1278 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1279 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1280 /* Check PCLMUL. */
1281 if (!x.bitfield.cpupclmul
1282 || cpu.bitfield.cpupclmul)
1283 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1284 }
1285 }
1286 else
1287 match |= CPU_FLAGS_ARCH_MATCH;
1288 }
1289 else
c0f3af97
L		 1290 match |= CPU_FLAGS_32BIT_MATCH;
1291 }
3629bb00 1292 }
c0f3af97 1293 return match;
40fb9820
L		 1294}
1295
c6fb90c8
L		 1296static INLINE i386_operand_type
1297operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1298{
c6fb90c8
L		 1299 switch (ARRAY_SIZE (x.array))
1300 {
1301 case 3:
1302 x.array [2] &= y.array [2];
1303 case 2:
1304 x.array [1] &= y.array [1];
1305 case 1:
1306 x.array [0] &= y.array [0];
1307 break;
1308 default:
1309 abort ();
1310 }
1311 return x;
40fb9820
L		 1312}
1313
c6fb90c8
L		 1314static INLINE i386_operand_type
1315operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1316{
c6fb90c8 1317 switch (ARRAY_SIZE (x.array))
40fb9820 1318 {
c6fb90c8
L		 1319 case 3:
1320 x.array [2] |= y.array [2];
1321 case 2:
1322 x.array [1] |= y.array [1];
1323 case 1:
1324 x.array [0] |= y.array [0];
40fb9820
L		 1325 break;
1326 default:
1327 abort ();
1328 }
c6fb90c8
L		 1329 return x;
1330}
40fb9820 1331
c6fb90c8
L		 1332static INLINE i386_operand_type
1333operand_type_xor (i386_operand_type x, i386_operand_type y)
1334{
1335 switch (ARRAY_SIZE (x.array))
1336 {
1337 case 3:
1338 x.array [2] ^= y.array [2];
1339 case 2:
1340 x.array [1] ^= y.array [1];
1341 case 1:
1342 x.array [0] ^= y.array [0];
1343 break;
1344 default:
1345 abort ();
1346 }
40fb9820
L		 1347 return x;
1348}
1349
1350static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1351static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1352static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1353static const i386_operand_type inoutportreg
1354 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1355static const i386_operand_type reg16_inoutportreg
1356 = OPERAND_TYPE_REG16_INOUTPORTREG;
1357static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1358static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1359static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1360static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1361static const i386_operand_type anydisp
1362 = OPERAND_TYPE_ANYDISP;
40fb9820 1363static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1364static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1365static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1366static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1367static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1368static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1369static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1370static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1371static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1372static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1373static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1374
1375enum operand_type
1376{
1377 reg,
40fb9820
L		 1378 imm,
1379 disp,
1380 anymem
1381};
1382
c6fb90c8 1383static INLINE int
40fb9820
L		 1384operand_type_check (i386_operand_type t, enum operand_type c)
1385{
1386 switch (c)
1387 {
1388 case reg:
1389 return (t.bitfield.reg8
1390 || t.bitfield.reg16
1391 || t.bitfield.reg32
1392 || t.bitfield.reg64);
1393
40fb9820
L		 1394 case imm:
1395 return (t.bitfield.imm8
1396 || t.bitfield.imm8s
1397 || t.bitfield.imm16
1398 || t.bitfield.imm32
1399 || t.bitfield.imm32s
1400 || t.bitfield.imm64);
1401
1402 case disp:
1403 return (t.bitfield.disp8
1404 || t.bitfield.disp16
1405 || t.bitfield.disp32
1406 || t.bitfield.disp32s
1407 || t.bitfield.disp64);
1408
1409 case anymem:
1410 return (t.bitfield.disp8
1411 || t.bitfield.disp16
1412 || t.bitfield.disp32
1413 || t.bitfield.disp32s
1414 || t.bitfield.disp64
1415 || t.bitfield.baseindex);
1416
1417 default:
1418 abort ();
1419 }
2cfe26b6
AM		 1420
1421 return 0;
40fb9820
L		 1422}
1423
5c07affc
L		 1424/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1425 operand J for instruction template T. */
1426
1427static INLINE int
1428match_reg_size (const template *t, unsigned int j)
1429{
1430 return !((i.types[j].bitfield.byte
1431 && !t->operand_types[j].bitfield.byte)
1432 || (i.types[j].bitfield.word
1433 && !t->operand_types[j].bitfield.word)
1434 || (i.types[j].bitfield.dword
1435 && !t->operand_types[j].bitfield.dword)
1436 || (i.types[j].bitfield.qword
1437 && !t->operand_types[j].bitfield.qword));
1438}
1439
1440/* Return 1 if there is no conflict in any size on operand J for
1441 instruction template T. */
1442
1443static INLINE int
1444match_mem_size (const template *t, unsigned int j)
1445{
1446 return (match_reg_size (t, j)
1447 && !((i.types[j].bitfield.unspecified
1448 && !t->operand_types[j].bitfield.unspecified)
1449 || (i.types[j].bitfield.fword
1450 && !t->operand_types[j].bitfield.fword)
1451 || (i.types[j].bitfield.tbyte
1452 && !t->operand_types[j].bitfield.tbyte)
1453 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1454 && !t->operand_types[j].bitfield.xmmword)
1455 || (i.types[j].bitfield.ymmword
1456 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1457}
1458
1459/* Return 1 if there is no size conflict on any operands for
1460 instruction template T. */
1461
1462static INLINE int
1463operand_size_match (const template *t)
1464{
1465 unsigned int j;
1466 int match = 1;
1467
1468 /* Don't check jump instructions. */
1469 if (t->opcode_modifier.jump
1470 || t->opcode_modifier.jumpbyte
1471 || t->opcode_modifier.jumpdword
1472 || t->opcode_modifier.jumpintersegment)
1473 return match;
1474
1475 /* Check memory and accumulator operand size. */
1476 for (j = 0; j < i.operands; j++)
1477 {
1478 if (t->operand_types[j].bitfield.anysize)
1479 continue;
1480
1481 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1482 {
1483 match = 0;
1484 break;
1485 }
1486
1487 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1488 {
1489 match = 0;
1490 break;
1491 }
1492 }
1493
1494 if (match
1495 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1496 return match;
1497
1498 /* Check reverse. */
1499 assert (i.operands == 2);
1500
1501 match = 1;
1502 for (j = 0; j < 2; j++)
1503 {
1504 if (t->operand_types[j].bitfield.acc
1505 && !match_reg_size (t, j ? 0 : 1))
1506 {
1507 match = 0;
1508 break;
1509 }
1510
1511 if (i.types[j].bitfield.mem
1512 && !match_mem_size (t, j ? 0 : 1))
1513 {
1514 match = 0;
1515 break;
1516 }
1517 }
1518
1519 return match;
1520}
1521
c6fb90c8 1522static INLINE int
40fb9820
L		 1523operand_type_match (i386_operand_type overlap,
1524 i386_operand_type given)
1525{
1526 i386_operand_type temp = overlap;
1527
1528 temp.bitfield.jumpabsolute = 0;
7d5e4556 1529 temp.bitfield.unspecified = 0;
5c07affc
L		 1530 temp.bitfield.byte = 0;
1531 temp.bitfield.word = 0;
1532 temp.bitfield.dword = 0;
1533 temp.bitfield.fword = 0;
1534 temp.bitfield.qword = 0;
1535 temp.bitfield.tbyte = 0;
1536 temp.bitfield.xmmword = 0;
c0f3af97 1537 temp.bitfield.ymmword = 0;
0dfbf9d7 1538 if (operand_type_all_zero (&temp))
40fb9820
L		 1539 return 0;
1540
1541 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1542 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1543}
1544
7d5e4556 1545/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1546 unless the expected operand type register overlap is null.
1547 Note that Acc in a template matches every size of reg. */
1548
c6fb90c8 1549static INLINE int
40fb9820
L		 1550operand_type_register_match (i386_operand_type m0,
1551 i386_operand_type g0,
1552 i386_operand_type t0,
1553 i386_operand_type m1,
1554 i386_operand_type g1,
1555 i386_operand_type t1)
1556{
1557 if (!operand_type_check (g0, reg))
1558 return 1;
1559
1560 if (!operand_type_check (g1, reg))
1561 return 1;
1562
1563 if (g0.bitfield.reg8 == g1.bitfield.reg8
1564 && g0.bitfield.reg16 == g1.bitfield.reg16
1565 && g0.bitfield.reg32 == g1.bitfield.reg32
1566 && g0.bitfield.reg64 == g1.bitfield.reg64)
1567 return 1;
1568
1569 if (m0.bitfield.acc)
1570 {
1571 t0.bitfield.reg8 = 1;
1572 t0.bitfield.reg16 = 1;
1573 t0.bitfield.reg32 = 1;
1574 t0.bitfield.reg64 = 1;
1575 }
1576
1577 if (m1.bitfield.acc)
1578 {
1579 t1.bitfield.reg8 = 1;
1580 t1.bitfield.reg16 = 1;
1581 t1.bitfield.reg32 = 1;
1582 t1.bitfield.reg64 = 1;
1583 }
1584
1585 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1586 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1587 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1588 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1589}
1590
252b5132 1591static INLINE unsigned int
40fb9820 1592mode_from_disp_size (i386_operand_type t)
252b5132 1593{
40fb9820
L		 1594 if (t.bitfield.disp8)
1595 return 1;
1596 else if (t.bitfield.disp16
1597 || t.bitfield.disp32
1598 || t.bitfield.disp32s)
1599 return 2;
1600 else
1601 return 0;
252b5132
RH		 1602}
1603
1604static INLINE int
e3bb37b5 1605fits_in_signed_byte (offsetT num)
252b5132
RH		 1606{
1607 return (num >= -128) && (num <= 127);
47926f60 1608}
252b5132
RH		 1609
1610static INLINE int
e3bb37b5 1611fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1612{
1613 return (num & 0xff) == num;
47926f60 1614}
252b5132
RH		 1615
1616static INLINE int
e3bb37b5 1617fits_in_unsigned_word (offsetT num)
252b5132
RH		 1618{
1619 return (num & 0xffff) == num;
47926f60 1620}
252b5132
RH		 1621
1622static INLINE int
e3bb37b5 1623fits_in_signed_word (offsetT num)
252b5132
RH		 1624{
1625 return (-32768 <= num) && (num <= 32767);
47926f60 1626}
2a962e6d 1627
3e73aa7c 1628static INLINE int
e3bb37b5 1629fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1630{
1631#ifndef BFD64
1632 return 1;
1633#else
1634 return (!(((offsetT) -1 << 31) & num)
1635 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1636#endif
1637} /* fits_in_signed_long() */
2a962e6d 1638
3e73aa7c 1639static INLINE int
e3bb37b5 1640fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1641{
1642#ifndef BFD64
1643 return 1;
1644#else
1645 return (num & (((offsetT) 2 << 31) - 1)) == num;
1646#endif
1647} /* fits_in_unsigned_long() */
252b5132 1648
40fb9820 1649static i386_operand_type
e3bb37b5 1650smallest_imm_type (offsetT num)
252b5132 1651{
40fb9820
L		 1652 i386_operand_type t;
1653
0dfbf9d7 1654 operand_type_set (&t, 0);
40fb9820
L		 1655 t.bitfield.imm64 = 1;
1656
1657 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1658 {
1659 /* This code is disabled on the 486 because all the Imm1 forms
1660 in the opcode table are slower on the i486. They're the
1661 versions with the implicitly specified single-position
1662 displacement, which has another syntax if you really want to
1663 use that form. */
40fb9820
L		 1664 t.bitfield.imm1 = 1;
1665 t.bitfield.imm8 = 1;
1666 t.bitfield.imm8s = 1;
1667 t.bitfield.imm16 = 1;
1668 t.bitfield.imm32 = 1;
1669 t.bitfield.imm32s = 1;
1670 }
1671 else if (fits_in_signed_byte (num))
1672 {
1673 t.bitfield.imm8 = 1;
1674 t.bitfield.imm8s = 1;
1675 t.bitfield.imm16 = 1;
1676 t.bitfield.imm32 = 1;
1677 t.bitfield.imm32s = 1;
1678 }
1679 else if (fits_in_unsigned_byte (num))
1680 {
1681 t.bitfield.imm8 = 1;
1682 t.bitfield.imm16 = 1;
1683 t.bitfield.imm32 = 1;
1684 t.bitfield.imm32s = 1;
1685 }
1686 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1687 {
1688 t.bitfield.imm16 = 1;
1689 t.bitfield.imm32 = 1;
1690 t.bitfield.imm32s = 1;
1691 }
1692 else if (fits_in_signed_long (num))
1693 {
1694 t.bitfield.imm32 = 1;
1695 t.bitfield.imm32s = 1;
1696 }
1697 else if (fits_in_unsigned_long (num))
1698 t.bitfield.imm32 = 1;
1699
1700 return t;
47926f60 1701}
252b5132 1702
847f7ad4 1703static offsetT
e3bb37b5 1704offset_in_range (offsetT val, int size)
847f7ad4 1705{
508866be 1706 addressT mask;
ba2adb93 1707
847f7ad4
AM		 1708 switch (size)
1709 {
508866be
L		 1710 case 1: mask = ((addressT) 1 << 8) - 1; break;
1711 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1712 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1713#ifdef BFD64
1714 case 8: mask = ((addressT) 2 << 63) - 1; break;
1715#endif
47926f60 1716 default: abort ();
847f7ad4
AM		 1717 }
1718
ba2adb93 1719 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1720 if (!use_rela_relocations)
1721 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1722 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1723
47926f60 1724 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1725 {
1726 char buf1[40], buf2[40];
1727
1728 sprint_value (buf1, val);
1729 sprint_value (buf2, val & mask);
1730 as_warn (_("%s shortened to %s"), buf1, buf2);
1731 }
1732 return val & mask;
1733}
1734
252b5132
RH		 1735/* Returns 0 if attempting to add a prefix where one from the same
1736 class already exists, 1 if non rep/repne added, 2 if rep/repne
1737 added. */
1738static int
e3bb37b5 1739add_prefix (unsigned int prefix)
252b5132
RH		 1740{
1741 int ret = 1;
b1905489 1742 unsigned int q;
252b5132 1743
29b0f896
AM		 1744 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1745 && flag_code == CODE_64BIT)
b1905489 1746 {
161a04f6
L		 1747 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1748 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1749 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1750 ret = 0;
1751 q = REX_PREFIX;
1752 }
3e73aa7c 1753 else
b1905489
JB		 1754 {
1755 switch (prefix)
1756 {
1757 default:
1758 abort ();
1759
1760 case CS_PREFIX_OPCODE:
1761 case DS_PREFIX_OPCODE:
1762 case ES_PREFIX_OPCODE:
1763 case FS_PREFIX_OPCODE:
1764 case GS_PREFIX_OPCODE:
1765 case SS_PREFIX_OPCODE:
1766 q = SEG_PREFIX;
1767 break;
1768
1769 case REPNE_PREFIX_OPCODE:
1770 case REPE_PREFIX_OPCODE:
1771 ret = 2;
1772 /* fall thru */
1773 case LOCK_PREFIX_OPCODE:
1774 q = LOCKREP_PREFIX;
1775 break;
1776
1777 case FWAIT_OPCODE:
1778 q = WAIT_PREFIX;
1779 break;
1780
1781 case ADDR_PREFIX_OPCODE:
1782 q = ADDR_PREFIX;
1783 break;
1784
1785 case DATA_PREFIX_OPCODE:
1786 q = DATA_PREFIX;
1787 break;
1788 }
1789 if (i.prefix[q] != 0)
1790 ret = 0;
1791 }
252b5132 1792
b1905489 1793 if (ret)
252b5132 1794 {
b1905489
JB		 1795 if (!i.prefix[q])
1796 ++i.prefixes;
1797 i.prefix[q] |= prefix;
252b5132 1798 }
b1905489
JB		 1799 else
1800 as_bad (_("same type of prefix used twice"));
252b5132 1801
252b5132
RH		 1802 return ret;
1803}
1804
1805static void
e3bb37b5 1806set_code_flag (int value)
eecb386c 1807{
3e73aa7c 1808 flag_code = value;
40fb9820
L		 1809 if (flag_code == CODE_64BIT)
1810 {
1811 cpu_arch_flags.bitfield.cpu64 = 1;
1812 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1813 }
1814 else
1815 {
1816 cpu_arch_flags.bitfield.cpu64 = 0;
1817 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1818 }
1819 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1820 {
1821 as_bad (_("64bit mode not supported on this CPU."));
1822 }
40fb9820 1823 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1824 {
1825 as_bad (_("32bit mode not supported on this CPU."));
1826 }
eecb386c
AM		 1827 stackop_size = '\0';
1828}
1829
1830static void
e3bb37b5 1831set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1832{
3e73aa7c 1833 flag_code = new_code_flag;
40fb9820
L		 1834 if (flag_code != CODE_16BIT)
1835 abort ();
1836 cpu_arch_flags.bitfield.cpu64 = 0;
1837 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1838 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1839}
1840
1841static void
e3bb37b5 1842set_intel_syntax (int syntax_flag)
252b5132
RH		 1843{
1844 /* Find out if register prefixing is specified. */
1845 int ask_naked_reg = 0;
1846
1847 SKIP_WHITESPACE ();
29b0f896 1848 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1849 {
1850 char *string = input_line_pointer;
1851 int e = get_symbol_end ();
1852
47926f60 1853 if (strcmp (string, "prefix") == 0)
252b5132 1854 ask_naked_reg = 1;
47926f60 1855 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1856 ask_naked_reg = -1;
1857 else
d0b47220 1858 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1859 *input_line_pointer = e;
1860 }
1861 demand_empty_rest_of_line ();
c3332e24 1862
252b5132
RH		 1863 intel_syntax = syntax_flag;
1864
1865 if (ask_naked_reg == 0)
f86103b7
AM		 1866 allow_naked_reg = (intel_syntax
1867 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1868 else
1869 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1870
ee86248c
JB		 1871 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
1872
e4a3b5a4 1873 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1874 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1875 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1876}
1877
1efbbeb4
L		 1878static void
1879set_intel_mnemonic (int mnemonic_flag)
1880{
e1d4d893 1881 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1882}
1883
db51cc60
L		 1884static void
1885set_allow_index_reg (int flag)
1886{
1887 allow_index_reg = flag;
1888}
1889
cb19c032
L		 1890static void
1891set_sse_check (int dummy ATTRIBUTE_UNUSED)
1892{
1893 SKIP_WHITESPACE ();
1894
1895 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1896 {
1897 char *string = input_line_pointer;
1898 int e = get_symbol_end ();
1899
1900 if (strcmp (string, "none") == 0)
1901 sse_check = sse_check_none;
1902 else if (strcmp (string, "warning") == 0)
1903 sse_check = sse_check_warning;
1904 else if (strcmp (string, "error") == 0)
1905 sse_check = sse_check_error;
1906 else
1907 as_bad (_("bad argument to sse_check directive."));
1908 *input_line_pointer = e;
1909 }
1910 else
1911 as_bad (_("missing argument for sse_check directive"));
1912
1913 demand_empty_rest_of_line ();
1914}
1915
e413e4e9 1916static void
e3bb37b5 1917set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1918{
47926f60 1919 SKIP_WHITESPACE ();
e413e4e9 1920
29b0f896 1921 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1922 {
1923 char *string = input_line_pointer;
1924 int e = get_symbol_end ();
9103f4f4 1925 unsigned int i;
40fb9820 1926 i386_cpu_flags flags;
e413e4e9 1927
9103f4f4 1928 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1929 {
1930 if (strcmp (string, cpu_arch[i].name) == 0)
1931 {
5c6af06e
JB		 1932 if (*string != '.')
1933 {
1934 cpu_arch_name = cpu_arch[i].name;
1935 cpu_sub_arch_name = NULL;
40fb9820
L		 1936 cpu_arch_flags = cpu_arch[i].flags;
1937 if (flag_code == CODE_64BIT)
1938 {
1939 cpu_arch_flags.bitfield.cpu64 = 1;
1940 cpu_arch_flags.bitfield.cpuno64 = 0;
1941 }
1942 else
1943 {
1944 cpu_arch_flags.bitfield.cpu64 = 0;
1945 cpu_arch_flags.bitfield.cpuno64 = 1;
1946 }
ccc9c027 1947 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1948 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1949 if (!cpu_arch_tune_set)
1950 {
1951 cpu_arch_tune = cpu_arch_isa;
1952 cpu_arch_tune_flags = cpu_arch_isa_flags;
1953 }
5c6af06e
JB		 1954 break;
1955 }
40fb9820 1956
c6fb90c8
L		 1957 flags = cpu_flags_or (cpu_arch_flags,
1958 cpu_arch[i].flags);
0dfbf9d7 1959 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 1960 {
6305a203
L		 1961 if (cpu_sub_arch_name)
1962 {
1963 char *name = cpu_sub_arch_name;
1964 cpu_sub_arch_name = concat (name,
1965 cpu_arch[i].name,
1bf57e9f 1966 (const char *) NULL);
6305a203
L		 1967 free (name);
1968 }
1969 else
1970 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 1971 cpu_arch_flags = flags;
5c6af06e
JB		 1972 }
1973 *input_line_pointer = e;
1974 demand_empty_rest_of_line ();
1975 return;
e413e4e9
AM		 1976 }
1977 }
9103f4f4 1978 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1979 as_bad (_("no such architecture: `%s'"), string);
1980
1981 *input_line_pointer = e;
1982 }
1983 else
1984 as_bad (_("missing cpu architecture"));
1985
fddf5b5b
AM		 1986 no_cond_jump_promotion = 0;
1987 if (*input_line_pointer == ','
29b0f896 1988 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1989 {
1990 char *string = ++input_line_pointer;
1991 int e = get_symbol_end ();
1992
1993 if (strcmp (string, "nojumps") == 0)
1994 no_cond_jump_promotion = 1;
1995 else if (strcmp (string, "jumps") == 0)
1996 ;
1997 else
1998 as_bad (_("no such architecture modifier: `%s'"), string);
1999
2000 *input_line_pointer = e;
2001 }
2002
e413e4e9
AM		 2003 demand_empty_rest_of_line ();
2004}
2005
b9d79e03
JH		 2006unsigned long
2007i386_mach ()
2008{
2009 if (!strcmp (default_arch, "x86_64"))
2010 return bfd_mach_x86_64;
2011 else if (!strcmp (default_arch, "i386"))
2012 return bfd_mach_i386_i386;
2013 else
2014 as_fatal (_("Unknown architecture"));
2015}
b9d79e03 2016\f
252b5132
RH		 2017void
2018md_begin ()
2019{
2020 const char *hash_err;
2021
47926f60 2022 /* Initialize op_hash hash table. */
252b5132
RH		 2023 op_hash = hash_new ();
2024
2025 {
29b0f896
AM		 2026 const template *optab;
2027 templates *core_optab;
252b5132 2028
47926f60
KH		 2029 /* Setup for loop. */
2030 optab = i386_optab;
252b5132
RH		 2031 core_optab = (templates *) xmalloc (sizeof (templates));
2032 core_optab->start = optab;
2033
2034 while (1)
2035 {
2036 ++optab;
2037 if (optab->name == NULL
2038 || strcmp (optab->name, (optab - 1)->name) != 0)
2039 {
2040 /* different name --> ship out current template list;
47926f60 2041 add to hash table; & begin anew. */
252b5132
RH		 2042 core_optab->end = optab;
2043 hash_err = hash_insert (op_hash,
2044 (optab - 1)->name,
5a49b8ac 2045 (void *) core_optab);
252b5132
RH		 2046 if (hash_err)
2047 {
252b5132
RH		 2048 as_fatal (_("Internal Error: Can't hash %s: %s"),
2049 (optab - 1)->name,
2050 hash_err);
2051 }
2052 if (optab->name == NULL)
2053 break;
2054 core_optab = (templates *) xmalloc (sizeof (templates));
2055 core_optab->start = optab;
2056 }
2057 }
2058 }
2059
47926f60 2060 /* Initialize reg_hash hash table. */
252b5132
RH		 2061 reg_hash = hash_new ();
2062 {
29b0f896 2063 const reg_entry *regtab;
c3fe08fa 2064 unsigned int regtab_size = i386_regtab_size;
252b5132 2065
c3fe08fa 2066 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2067 {
5a49b8ac 2068 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2069 if (hash_err)
3e73aa7c
JH		 2070 as_fatal (_("Internal Error: Can't hash %s: %s"),
2071 regtab->reg_name,
2072 hash_err);
252b5132
RH		 2073 }
2074 }
2075
47926f60 2076 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2077 {
29b0f896
AM		 2078 int c;
2079 char *p;
252b5132
RH		 2080
2081 for (c = 0; c < 256; c++)
2082 {
3882b010 2083 if (ISDIGIT (c))
252b5132
RH		 2084 {
2085 digit_chars[c] = c;
2086 mnemonic_chars[c] = c;
2087 register_chars[c] = c;
2088 operand_chars[c] = c;
2089 }
3882b010 2090 else if (ISLOWER (c))
252b5132
RH		 2091 {
2092 mnemonic_chars[c] = c;
2093 register_chars[c] = c;
2094 operand_chars[c] = c;
2095 }
3882b010 2096 else if (ISUPPER (c))
252b5132 2097 {
3882b010 2098 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2099 register_chars[c] = mnemonic_chars[c];
2100 operand_chars[c] = c;
2101 }
2102
3882b010 2103 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2104 identifier_chars[c] = c;
2105 else if (c >= 128)
2106 {
2107 identifier_chars[c] = c;
2108 operand_chars[c] = c;
2109 }
2110 }
2111
2112#ifdef LEX_AT
2113 identifier_chars['@'] = '@';
32137342
NC		 2114#endif
2115#ifdef LEX_QM
2116 identifier_chars['?'] = '?';
2117 operand_chars['?'] = '?';
252b5132 2118#endif
252b5132 2119 digit_chars['-'] = '-';
c0f3af97 2120 mnemonic_chars['_'] = '_';
791fe849 2121 mnemonic_chars['-'] = '-';
0003779b 2122 mnemonic_chars['.'] = '.';
252b5132
RH		 2123 identifier_chars['_'] = '_';
2124 identifier_chars['.'] = '.';
2125
2126 for (p = operand_special_chars; *p != '\0'; p++)
2127 operand_chars[(unsigned char) *p] = *p;
2128 }
2129
2130#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2131 if (IS_ELF)
252b5132
RH		 2132 {
2133 record_alignment (text_section, 2);
2134 record_alignment (data_section, 2);
2135 record_alignment (bss_section, 2);
2136 }
2137#endif
a4447b93
RH		 2138
2139 if (flag_code == CODE_64BIT)
2140 {
2141 x86_dwarf2_return_column = 16;
2142 x86_cie_data_alignment = -8;
2143 }
2144 else
2145 {
2146 x86_dwarf2_return_column = 8;
2147 x86_cie_data_alignment = -4;
2148 }
252b5132
RH		 2149}
2150
2151void
e3bb37b5 2152i386_print_statistics (FILE *file)
252b5132
RH		 2153{
2154 hash_print_statistics (file, "i386 opcode", op_hash);
2155 hash_print_statistics (file, "i386 register", reg_hash);
2156}
2157\f
252b5132
RH		 2158#ifdef DEBUG386
2159
ce8a8b2f 2160/* Debugging routines for md_assemble. */
e3bb37b5 2161static void pte (template *);
40fb9820 2162static void pt (i386_operand_type);
e3bb37b5
L		 2163static void pe (expressionS *);
2164static void ps (symbolS *);
252b5132
RH		 2165
2166static void
e3bb37b5 2167pi (char *line, i386_insn *x)
252b5132 2168{
09f131f2 2169 unsigned int i;
252b5132
RH		 2170
2171 fprintf (stdout, "%s: template ", line);
2172 pte (&x->tm);
09f131f2
JH		 2173 fprintf (stdout, " address: base %s index %s scale %x\n",
2174 x->base_reg ? x->base_reg->reg_name : "none",
2175 x->index_reg ? x->index_reg->reg_name : "none",
2176 x->log2_scale_factor);
2177 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2178 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2179 fprintf (stdout, " sib: base %x index %x scale %x\n",
2180 x->sib.base, x->sib.index, x->sib.scale);
2181 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2182 (x->rex & REX_W) != 0,
2183 (x->rex & REX_R) != 0,
2184 (x->rex & REX_X) != 0,
2185 (x->rex & REX_B) != 0);
252b5132
RH		 2186 for (i = 0; i < x->operands; i++)
2187 {
2188 fprintf (stdout, " #%d: ", i + 1);
2189 pt (x->types[i]);
2190 fprintf (stdout, "\n");
40fb9820
L		 2191 if (x->types[i].bitfield.reg8
2192 || x->types[i].bitfield.reg16
2193 || x->types[i].bitfield.reg32
2194 || x->types[i].bitfield.reg64
2195 || x->types[i].bitfield.regmmx
2196 || x->types[i].bitfield.regxmm
c0f3af97 2197 || x->types[i].bitfield.regymm
40fb9820
L		 2198 || x->types[i].bitfield.sreg2
2199 || x->types[i].bitfield.sreg3
2200 || x->types[i].bitfield.control
2201 || x->types[i].bitfield.debug
2202 || x->types[i].bitfield.test)
520dc8e8 2203 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2204 if (operand_type_check (x->types[i], imm))
520dc8e8 2205 pe (x->op[i].imms);
40fb9820 2206 if (operand_type_check (x->types[i], disp))
520dc8e8 2207 pe (x->op[i].disps);
252b5132
RH		 2208 }
2209}
2210
2211static void
e3bb37b5 2212pte (template *t)
252b5132 2213{
09f131f2 2214 unsigned int i;
252b5132 2215 fprintf (stdout, " %d operands ", t->operands);
47926f60 2216 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2217 if (t->extension_opcode != None)
2218 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2219 if (t->opcode_modifier.d)
252b5132 2220 fprintf (stdout, "D");
40fb9820 2221 if (t->opcode_modifier.w)
252b5132
RH		 2222 fprintf (stdout, "W");
2223 fprintf (stdout, "\n");
2224 for (i = 0; i < t->operands; i++)
2225 {
2226 fprintf (stdout, " #%d type ", i + 1);
2227 pt (t->operand_types[i]);
2228 fprintf (stdout, "\n");
2229 }
2230}
2231
2232static void
e3bb37b5 2233pe (expressionS *e)
252b5132 2234{
24eab124 2235 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2236 fprintf (stdout, " add_number %ld (%lx)\n",
2237 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2238 if (e->X_add_symbol)
2239 {
2240 fprintf (stdout, " add_symbol ");
2241 ps (e->X_add_symbol);
2242 fprintf (stdout, "\n");
2243 }
2244 if (e->X_op_symbol)
2245 {
2246 fprintf (stdout, " op_symbol ");
2247 ps (e->X_op_symbol);
2248 fprintf (stdout, "\n");
2249 }
2250}
2251
2252static void
e3bb37b5 2253ps (symbolS *s)
252b5132
RH		 2254{
2255 fprintf (stdout, "%s type %s%s",
2256 S_GET_NAME (s),
2257 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2258 segment_name (S_GET_SEGMENT (s)));
2259}
2260
7b81dfbb 2261static struct type_name
252b5132 2262 {
40fb9820
L		 2263 i386_operand_type mask;
2264 const char *name;
252b5132 2265 }
7b81dfbb 2266const type_names[] =
252b5132 2267{
40fb9820
L		 2268 { OPERAND_TYPE_REG8, "r8" },
2269 { OPERAND_TYPE_REG16, "r16" },
2270 { OPERAND_TYPE_REG32, "r32" },
2271 { OPERAND_TYPE_REG64, "r64" },
2272 { OPERAND_TYPE_IMM8, "i8" },
2273 { OPERAND_TYPE_IMM8, "i8s" },
2274 { OPERAND_TYPE_IMM16, "i16" },
2275 { OPERAND_TYPE_IMM32, "i32" },
2276 { OPERAND_TYPE_IMM32S, "i32s" },
2277 { OPERAND_TYPE_IMM64, "i64" },
2278 { OPERAND_TYPE_IMM1, "i1" },
2279 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2280 { OPERAND_TYPE_DISP8, "d8" },
2281 { OPERAND_TYPE_DISP16, "d16" },
2282 { OPERAND_TYPE_DISP32, "d32" },
2283 { OPERAND_TYPE_DISP32S, "d32s" },
2284 { OPERAND_TYPE_DISP64, "d64" },
2285 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2286 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2287 { OPERAND_TYPE_CONTROL, "control reg" },
2288 { OPERAND_TYPE_TEST, "test reg" },
2289 { OPERAND_TYPE_DEBUG, "debug reg" },
2290 { OPERAND_TYPE_FLOATREG, "FReg" },
2291 { OPERAND_TYPE_FLOATACC, "FAcc" },
2292 { OPERAND_TYPE_SREG2, "SReg2" },
2293 { OPERAND_TYPE_SREG3, "SReg3" },
2294 { OPERAND_TYPE_ACC, "Acc" },
2295 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2296 { OPERAND_TYPE_REGMMX, "rMMX" },
2297 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2298 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2299 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2300};
2301
2302static void
40fb9820 2303pt (i386_operand_type t)
252b5132 2304{
40fb9820 2305 unsigned int j;
c6fb90c8 2306 i386_operand_type a;
252b5132 2307
40fb9820 2308 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2309 {
2310 a = operand_type_and (t, type_names[j].mask);
0349dc08 2311 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2312 fprintf (stdout, "%s, ", type_names[j].name);
2313 }
252b5132
RH		 2314 fflush (stdout);
2315}
2316
2317#endif /* DEBUG386 */
2318\f
252b5132 2319static bfd_reloc_code_real_type
3956db08 2320reloc (unsigned int size,
64e74474
AM		 2321 int pcrel,
2322 int sign,
2323 bfd_reloc_code_real_type other)
252b5132 2324{
47926f60 2325 if (other != NO_RELOC)
3956db08
JB		 2326 {
2327 reloc_howto_type *reloc;
2328
2329 if (size == 8)
2330 switch (other)
2331 {
64e74474
AM		 2332 case BFD_RELOC_X86_64_GOT32:
2333 return BFD_RELOC_X86_64_GOT64;
2334 break;
2335 case BFD_RELOC_X86_64_PLTOFF64:
2336 return BFD_RELOC_X86_64_PLTOFF64;
2337 break;
2338 case BFD_RELOC_X86_64_GOTPC32:
2339 other = BFD_RELOC_X86_64_GOTPC64;
2340 break;
2341 case BFD_RELOC_X86_64_GOTPCREL:
2342 other = BFD_RELOC_X86_64_GOTPCREL64;
2343 break;
2344 case BFD_RELOC_X86_64_TPOFF32:
2345 other = BFD_RELOC_X86_64_TPOFF64;
2346 break;
2347 case BFD_RELOC_X86_64_DTPOFF32:
2348 other = BFD_RELOC_X86_64_DTPOFF64;
2349 break;
2350 default:
2351 break;
3956db08 2352 }
e05278af
JB		 2353
2354 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2355 if (size == 4 && flag_code != CODE_64BIT)
2356 sign = -1;
2357
3956db08
JB		 2358 reloc = bfd_reloc_type_lookup (stdoutput, other);
2359 if (!reloc)
2360 as_bad (_("unknown relocation (%u)"), other);
2361 else if (size != bfd_get_reloc_size (reloc))
2362 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2363 bfd_get_reloc_size (reloc),
2364 size);
2365 else if (pcrel && !reloc->pc_relative)
2366 as_bad (_("non-pc-relative relocation for pc-relative field"));
2367 else if ((reloc->complain_on_overflow == complain_overflow_signed
2368 && !sign)
2369 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2370 && sign > 0))
3956db08
JB		 2371 as_bad (_("relocated field and relocation type differ in signedness"));
2372 else
2373 return other;
2374 return NO_RELOC;
2375 }
252b5132
RH		 2376
2377 if (pcrel)
2378 {
3e73aa7c 2379 if (!sign)
3956db08 2380 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2381 switch (size)
2382 {
2383 case 1: return BFD_RELOC_8_PCREL;
2384 case 2: return BFD_RELOC_16_PCREL;
2385 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2386 case 8: return BFD_RELOC_64_PCREL;
252b5132 2387 }
3956db08 2388 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2389 }
2390 else
2391 {
3956db08 2392 if (sign > 0)
e5cb08ac 2393 switch (size)
3e73aa7c
JH		 2394 {
2395 case 4: return BFD_RELOC_X86_64_32S;
2396 }
2397 else
2398 switch (size)
2399 {
2400 case 1: return BFD_RELOC_8;
2401 case 2: return BFD_RELOC_16;
2402 case 4: return BFD_RELOC_32;
2403 case 8: return BFD_RELOC_64;
2404 }
3956db08
JB		 2405 as_bad (_("cannot do %s %u byte relocation"),
2406 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2407 }
2408
0cc9e1d3 2409 return NO_RELOC;
252b5132
RH		 2410}
2411
47926f60
KH		 2412/* Here we decide which fixups can be adjusted to make them relative to
2413 the beginning of the section instead of the symbol. Basically we need
2414 to make sure that the dynamic relocations are done correctly, so in
2415 some cases we force the original symbol to be used. */
2416
252b5132 2417int
e3bb37b5 2418tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2419{
6d249963 2420#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2421 if (!IS_ELF)
31312f95
AM		 2422 return 1;
2423
a161fe53
AM		 2424 /* Don't adjust pc-relative references to merge sections in 64-bit
2425 mode. */
2426 if (use_rela_relocations
2427 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2428 && fixP->fx_pcrel)
252b5132 2429 return 0;
31312f95 2430
8d01d9a9
AJ		 2431 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2432 and changed later by validate_fix. */
2433 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2434 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2435 return 0;
2436
ce8a8b2f 2437 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2438 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2439 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2440 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2441 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2442 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2443 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2444 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2445 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2446 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2447 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2448 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2449 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2450 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2451 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2452 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2453 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2454 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2455 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2456 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2457 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2458 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2459 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2460 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2461 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2462 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2463 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2464 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2465 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2466 return 0;
d8045f23
NC		 2467
2468 if (fixP->fx_addsy != NULL
2469 && symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_GNU_INDIRECT_FUNCTION)
2470 return 0;
31312f95 2471#endif
252b5132
RH		 2472 return 1;
2473}
252b5132 2474
b4cac588 2475static int
e3bb37b5 2476intel_float_operand (const char *mnemonic)
252b5132 2477{
9306ca4a
JB		 2478 /* Note that the value returned is meaningful only for opcodes with (memory)
2479 operands, hence the code here is free to improperly handle opcodes that
2480 have no operands (for better performance and smaller code). */
2481
2482 if (mnemonic[0] != 'f')
2483 return 0; /* non-math */
2484
2485 switch (mnemonic[1])
2486 {
2487 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2488 the fs segment override prefix not currently handled because no
2489 call path can make opcodes without operands get here */
2490 case 'i':
2491 return 2 /* integer op */;
2492 case 'l':
2493 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2494 return 3; /* fldcw/fldenv */
2495 break;
2496 case 'n':
2497 if (mnemonic[2] != 'o' /* fnop */)
2498 return 3; /* non-waiting control op */
2499 break;
2500 case 'r':
2501 if (mnemonic[2] == 's')
2502 return 3; /* frstor/frstpm */
2503 break;
2504 case 's':
2505 if (mnemonic[2] == 'a')
2506 return 3; /* fsave */
2507 if (mnemonic[2] == 't')
2508 {
2509 switch (mnemonic[3])
2510 {
2511 case 'c': /* fstcw */
2512 case 'd': /* fstdw */
2513 case 'e': /* fstenv */
2514 case 's': /* fsts[gw] */
2515 return 3;
2516 }
2517 }
2518 break;
2519 case 'x':
2520 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2521 return 0; /* fxsave/fxrstor are not really math ops */
2522 break;
2523 }
252b5132 2524
9306ca4a 2525 return 1;
252b5132
RH		 2526}
2527
c0f3af97
L		 2528/* Build the VEX prefix. */
2529
2530static void
fa99fab2 2531build_vex_prefix (const template *t)
c0f3af97
L		 2532{
2533 unsigned int register_specifier;
2534 unsigned int implied_prefix;
2535 unsigned int vector_length;
2536
2537 /* Check register specifier. */
2538 if (i.vex.register_specifier)
2539 {
2540 register_specifier = i.vex.register_specifier->reg_num;
2541 if ((i.vex.register_specifier->reg_flags & RegRex))
2542 register_specifier += 8;
2543 register_specifier = ~register_specifier & 0xf;
2544 }
2545 else
2546 register_specifier = 0xf;
2547
fa99fab2
L		 2548 /* Use 2-byte VEX prefix by swappping destination and source
2549 operand. */
2550 if (!i.swap_operand
2551 && i.operands == i.reg_operands
2552 && i.tm.opcode_modifier.vex0f
2553 && i.tm.opcode_modifier.s
2554 && i.rex == REX_B)
2555 {
2556 unsigned int xchg = i.operands - 1;
2557 union i386_op temp_op;
2558 i386_operand_type temp_type;
2559
2560 temp_type = i.types[xchg];
2561 i.types[xchg] = i.types[0];
2562 i.types[0] = temp_type;
2563 temp_op = i.op[xchg];
2564 i.op[xchg] = i.op[0];
2565 i.op[0] = temp_op;
2566
2567 assert (i.rm.mode == 3);
2568
2569 i.rex = REX_R;
2570 xchg = i.rm.regmem;
2571 i.rm.regmem = i.rm.reg;
2572 i.rm.reg = xchg;
2573
2574 /* Use the next insn. */
2575 i.tm = t[1];
2576 }
2577
c0f3af97
L		 2578 vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0;
2579
2580 switch ((i.tm.base_opcode >> 8) & 0xff)
2581 {
2582 case 0:
2583 implied_prefix = 0;
2584 break;
2585 case DATA_PREFIX_OPCODE:
2586 implied_prefix = 1;
2587 break;
2588 case REPE_PREFIX_OPCODE:
2589 implied_prefix = 2;
2590 break;
2591 case REPNE_PREFIX_OPCODE:
2592 implied_prefix = 3;
2593 break;
2594 default:
2595 abort ();
2596 }
2597
2598 /* Use 2-byte VEX prefix if possible. */
2599 if (i.tm.opcode_modifier.vex0f
2600 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2601 {
2602 /* 2-byte VEX prefix. */
2603 unsigned int r;
2604
2605 i.vex.length = 2;
2606 i.vex.bytes[0] = 0xc5;
2607
2608 /* Check the REX.R bit. */
2609 r = (i.rex & REX_R) ? 0 : 1;
2610 i.vex.bytes[1] = (r << 7
2611 | register_specifier << 3
2612 | vector_length << 2
2613 | implied_prefix);
2614 }
2615 else
2616 {
2617 /* 3-byte VEX prefix. */
2618 unsigned int m, w;
2619
2620 if (i.tm.opcode_modifier.vex0f)
2621 m = 0x1;
2622 else if (i.tm.opcode_modifier.vex0f38)
2623 m = 0x2;
2624 else if (i.tm.opcode_modifier.vex0f3a)
2625 m = 0x3;
2626 else
2627 abort ();
2628
2629 i.vex.length = 3;
2630 i.vex.bytes[0] = 0xc4;
2631
2632 /* The high 3 bits of the second VEX byte are 1's compliment
2633 of RXB bits from REX. */
2634 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2635
2636 /* Check the REX.W bit. */
2637 w = (i.rex & REX_W) ? 1 : 0;
2638 if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1)
2639 {
2640 if (w)
2641 abort ();
2642
2643 if (i.tm.opcode_modifier.vexw1)
2644 w = 1;
2645 }
2646
2647 i.vex.bytes[2] = (w << 7
2648 | register_specifier << 3
2649 | vector_length << 2
2650 | implied_prefix);
2651 }
2652}
2653
65da13b5
L		 2654static void
2655process_immext (void)
2656{
2657 expressionS *exp;
2658
2659 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2660 {
1fed0ba1
L		 2661 /* SSE3 Instructions have the fixed operands with an opcode
2662 suffix which is coded in the same place as an 8-bit immediate
2663 field would be. Here we check those operands and remove them
2664 afterwards. */
65da13b5
L		 2665 unsigned int x;
2666
2667 for (x = 0; x < i.operands; x++)
2668 if (i.op[x].regs->reg_num != x)
2669 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2670 register_prefix, i.op[x].regs->reg_name, x + 1,
2671 i.tm.name);
2672
2673 i.operands = 0;
65da13b5
L		 2674 }
2675
c0f3af97 2676 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2677 which is coded in the same place as an 8-bit immediate field
2678 would be. Here we fake an 8-bit immediate operand from the
2679 opcode suffix stored in tm.extension_opcode.
2680
c1e679ec 2681 AVX instructions also use this encoding, for some of
c0f3af97 2682 3 argument instructions. */
65da13b5
L		 2683
2684 assert (i.imm_operands == 0
2685 && (i.operands <= 2
c0f3af97
L		 2686 || (i.tm.opcode_modifier.vex
2687 && i.operands <= 4)));
65da13b5
L		 2688
2689 exp = &im_expressions[i.imm_operands++];
2690 i.op[i.operands].imms = exp;
2691 i.types[i.operands] = imm8;
2692 i.operands++;
2693 exp->X_op = O_constant;
2694 exp->X_add_number = i.tm.extension_opcode;
2695 i.tm.extension_opcode = None;
2696}
2697
252b5132
RH		 2698/* This is the guts of the machine-dependent assembler. LINE points to a
2699 machine dependent instruction. This function is supposed to emit
2700 the frags/bytes it assembles to. */
2701
2702void
65da13b5 2703md_assemble (char *line)
252b5132 2704{
40fb9820 2705 unsigned int j;
252b5132 2706 char mnemonic[MAX_MNEM_SIZE];
fa99fab2 2707 const template *t;
252b5132 2708
47926f60 2709 /* Initialize globals. */
252b5132
RH		 2710 memset (&i, '\0', sizeof (i));
2711 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2712 i.reloc[j] = NO_RELOC;
252b5132
RH		 2713 memset (disp_expressions, '\0', sizeof (disp_expressions));
2714 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2715 save_stack_p = save_stack;
252b5132
RH		 2716
2717 /* First parse an instruction mnemonic & call i386_operand for the operands.
2718 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2719 start of a (possibly prefixed) mnemonic. */
252b5132 2720
29b0f896
AM		 2721 line = parse_insn (line, mnemonic);
2722 if (line == NULL)
2723 return;
252b5132 2724
29b0f896 2725 line = parse_operands (line, mnemonic);
ee86248c 2726 this_operand = -1;
29b0f896
AM		 2727 if (line == NULL)
2728 return;
252b5132 2729
29b0f896
AM		 2730 /* Now we've parsed the mnemonic into a set of templates, and have the
2731 operands at hand. */
2732
2733 /* All intel opcodes have reversed operands except for "bound" and
2734 "enter". We also don't reverse intersegment "jmp" and "call"
2735 instructions with 2 immediate operands so that the immediate segment
050dfa73 2736 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2737 if (intel_syntax
2738 && i.operands > 1
29b0f896 2739 && (strcmp (mnemonic, "bound") != 0)
30123838 2740 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2741 && !(operand_type_check (i.types[0], imm)
2742 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2743 swap_operands ();
2744
ec56d5c0
JB		 2745 /* The order of the immediates should be reversed
2746 for 2 immediates extrq and insertq instructions */
2747 if (i.imm_operands == 2
2748 && (strcmp (mnemonic, "extrq") == 0
2749 || strcmp (mnemonic, "insertq") == 0))
2750 swap_2_operands (0, 1);
2751
29b0f896
AM		 2752 if (i.imm_operands)
2753 optimize_imm ();
2754
b300c311
L		 2755 /* Don't optimize displacement for movabs since it only takes 64bit
2756 displacement. */
2757 if (i.disp_operands
2758 && (flag_code != CODE_64BIT
2759 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2760 optimize_disp ();
2761
2762 /* Next, we find a template that matches the given insn,
2763 making sure the overlap of the given operands types is consistent
2764 with the template operand types. */
252b5132 2765
fa99fab2 2766 if (!(t = match_template ()))
29b0f896 2767 return;
252b5132 2768
daf50ae7 2769 if (sse_check != sse_check_none
81f8a913 2770 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2771 && (i.tm.cpu_flags.bitfield.cpusse
2772 || i.tm.cpu_flags.bitfield.cpusse2
2773 || i.tm.cpu_flags.bitfield.cpusse3
2774 || i.tm.cpu_flags.bitfield.cpussse3
2775 || i.tm.cpu_flags.bitfield.cpusse4_1
2776 || i.tm.cpu_flags.bitfield.cpusse4_2))
2777 {
2778 (sse_check == sse_check_warning
2779 ? as_warn
2780 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2781 }
2782
321fd21e
L		 2783 /* Zap movzx and movsx suffix. The suffix has been set from
2784 "word ptr" or "byte ptr" on the source operand in Intel syntax
2785 or extracted from mnemonic in AT&T syntax. But we'll use
2786 the destination register to choose the suffix for encoding. */
2787 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2788 {
321fd21e
L		 2789 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2790 there is no suffix, the default will be byte extension. */
2791 if (i.reg_operands != 2
2792 && !i.suffix
2793 && intel_syntax)
2794 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2795
2796 i.suffix = 0;
cd61ebfe 2797 }
24eab124 2798
40fb9820 2799 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2800 if (!add_prefix (FWAIT_OPCODE))
2801 return;
252b5132 2802
29b0f896 2803 /* Check string instruction segment overrides. */
40fb9820 2804 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2805 {
2806 if (!check_string ())
5dd0794d 2807 return;
fc0763e6 2808 i.disp_operands = 0;
29b0f896 2809 }
5dd0794d 2810
29b0f896
AM		 2811 if (!process_suffix ())
2812 return;
e413e4e9 2813
29b0f896
AM		 2814 /* Make still unresolved immediate matches conform to size of immediate
2815 given in i.suffix. */
2816 if (!finalize_imm ())
2817 return;
252b5132 2818
40fb9820 2819 if (i.types[0].bitfield.imm1)
29b0f896 2820 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2821
40fb9820 2822 for (j = 0; j < 3; j++)
c6fb90c8
L		 2823 if (i.types[j].bitfield.inoutportreg
2824 || i.types[j].bitfield.shiftcount
2825 || i.types[j].bitfield.acc
2826 || i.types[j].bitfield.floatacc)
40fb9820
L		 2827 i.reg_operands--;
2828
c0f3af97
L		 2829 /* ImmExt should be processed after SSE2AVX. */
2830 if (!i.tm.opcode_modifier.sse2avx
2831 && i.tm.opcode_modifier.immext)
65da13b5 2832 process_immext ();
252b5132 2833
29b0f896
AM		 2834 /* For insns with operands there are more diddles to do to the opcode. */
2835 if (i.operands)
2836 {
2837 if (!process_operands ())
2838 return;
2839 }
40fb9820 2840 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2841 {
2842 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2843 as_warn (_("translating to `%sp'"), i.tm.name);
2844 }
252b5132 2845
c0f3af97 2846 if (i.tm.opcode_modifier.vex)
fa99fab2 2847 build_vex_prefix (t);
c0f3af97 2848
29b0f896
AM		 2849 /* Handle conversion of 'int $3' --> special int3 insn. */
2850 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2851 {
2852 i.tm.base_opcode = INT3_OPCODE;
2853 i.imm_operands = 0;
2854 }
252b5132 2855
40fb9820
L		 2856 if ((i.tm.opcode_modifier.jump
2857 || i.tm.opcode_modifier.jumpbyte
2858 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2859 && i.op[0].disps->X_op == O_constant)
2860 {
2861 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2862 the absolute address given by the constant. Since ix86 jumps and
2863 calls are pc relative, we need to generate a reloc. */
2864 i.op[0].disps->X_add_symbol = &abs_symbol;
2865 i.op[0].disps->X_op = O_symbol;
2866 }
252b5132 2867
40fb9820 2868 if (i.tm.opcode_modifier.rex64)
161a04f6 2869 i.rex |= REX_W;
252b5132 2870
29b0f896
AM		 2871 /* For 8 bit registers we need an empty rex prefix. Also if the
2872 instruction already has a prefix, we need to convert old
2873 registers to new ones. */
773f551c 2874
40fb9820 2875 if ((i.types[0].bitfield.reg8
29b0f896 2876 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2877 || (i.types[1].bitfield.reg8
29b0f896 2878 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2879 || ((i.types[0].bitfield.reg8
2880 || i.types[1].bitfield.reg8)
29b0f896
AM		 2881 && i.rex != 0))
2882 {
2883 int x;
726c5dcd 2884
29b0f896
AM		 2885 i.rex |= REX_OPCODE;
2886 for (x = 0; x < 2; x++)
2887 {
2888 /* Look for 8 bit operand that uses old registers. */
40fb9820 2889 if (i.types[x].bitfield.reg8
29b0f896 2890 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2891 {
29b0f896
AM		 2892 /* In case it is "hi" register, give up. */
2893 if (i.op[x].regs->reg_num > 3)
a540244d 2894 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2895 "instruction requiring REX prefix."),
a540244d 2896 register_prefix, i.op[x].regs->reg_name);
773f551c 2897
29b0f896
AM		 2898 /* Otherwise it is equivalent to the extended register.
2899 Since the encoding doesn't change this is merely
2900 cosmetic cleanup for debug output. */
2901
2902 i.op[x].regs = i.op[x].regs + 8;
773f551c 2903 }
29b0f896
AM		 2904 }
2905 }
773f551c 2906
c1e679ec 2907if (i.rex != 0)
29b0f896
AM		 2908 add_prefix (REX_OPCODE | i.rex);
2909
2910 /* We are ready to output the insn. */
2911 output_insn ();
2912}
2913
2914static char *
e3bb37b5 2915parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2916{
2917 char *l = line;
2918 char *token_start = l;
2919 char *mnem_p;
5c6af06e
JB		 2920 int supported;
2921 const template *t;
b6169b20 2922 char *dot_p = NULL;
29b0f896
AM		 2923
2924 /* Non-zero if we found a prefix only acceptable with string insns. */
2925 const char *expecting_string_instruction = NULL;
45288df1 2926
29b0f896
AM		 2927 while (1)
2928 {
2929 mnem_p = mnemonic;
2930 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2931 {
b6169b20
L		 2932 if (*mnem_p == '.')
2933 dot_p = mnem_p;
29b0f896
AM		 2934 mnem_p++;
2935 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2936 {
29b0f896
AM		 2937 as_bad (_("no such instruction: `%s'"), token_start);
2938 return NULL;
2939 }
2940 l++;
2941 }
2942 if (!is_space_char (*l)
2943 && *l != END_OF_INSN
e44823cf
JB		 2944 && (intel_syntax
2945 || (*l != PREFIX_SEPARATOR
2946 && *l != ',')))
29b0f896
AM		 2947 {
2948 as_bad (_("invalid character %s in mnemonic"),
2949 output_invalid (*l));
2950 return NULL;
2951 }
2952 if (token_start == l)
2953 {
e44823cf 2954 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2955 as_bad (_("expecting prefix; got nothing"));
2956 else
2957 as_bad (_("expecting mnemonic; got nothing"));
2958 return NULL;
2959 }
45288df1 2960
29b0f896
AM		 2961 /* Look up instruction (or prefix) via hash table. */
2962 current_templates = hash_find (op_hash, mnemonic);
47926f60 2963
29b0f896
AM		 2964 if (*l != END_OF_INSN
2965 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2966 && current_templates
40fb9820 2967 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2968 {
c6fb90c8 2969 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2970 {
2971 as_bad ((flag_code != CODE_64BIT
2972 ? _("`%s' is only supported in 64-bit mode")
2973 : _("`%s' is not supported in 64-bit mode")),
2974 current_templates->start->name);
2975 return NULL;
2976 }
29b0f896
AM		 2977 /* If we are in 16-bit mode, do not allow addr16 or data16.
2978 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2979 if ((current_templates->start->opcode_modifier.size16
2980 || current_templates->start->opcode_modifier.size32)
29b0f896 2981 && flag_code != CODE_64BIT
40fb9820 2982 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2983 ^ (flag_code == CODE_16BIT)))
2984 {
2985 as_bad (_("redundant %s prefix"),
2986 current_templates->start->name);
2987 return NULL;
45288df1 2988 }
29b0f896
AM		 2989 /* Add prefix, checking for repeated prefixes. */
2990 switch (add_prefix (current_templates->start->base_opcode))
2991 {
2992 case 0:
2993 return NULL;
2994 case 2:
2995 expecting_string_instruction = current_templates->start->name;
2996 break;
2997 }
2998 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2999 token_start = ++l;
3000 }
3001 else
3002 break;
3003 }
45288df1 3004
30a55f88 3005 if (!current_templates)
b6169b20 3006 {
30a55f88
L		 3007 /* Check if we should swap operand in encoding. */
3008 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3009 i.swap_operand = 1;
3010 else
3011 goto check_suffix;
3012 mnem_p = dot_p;
3013 *dot_p = '\0';
3014 current_templates = hash_find (op_hash, mnemonic);
b6169b20
L		 3015 }
3016
29b0f896
AM		 3017 if (!current_templates)
3018 {
b6169b20 3019check_suffix:
29b0f896
AM		 3020 /* See if we can get a match by trimming off a suffix. */
3021 switch (mnem_p[-1])
3022 {
3023 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3024 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3025 i.suffix = SHORT_MNEM_SUFFIX;
3026 else
29b0f896
AM		 3027 case BYTE_MNEM_SUFFIX:
3028 case QWORD_MNEM_SUFFIX:
3029 i.suffix = mnem_p[-1];
3030 mnem_p[-1] = '\0';
3031 current_templates = hash_find (op_hash, mnemonic);
3032 break;
3033 case SHORT_MNEM_SUFFIX:
3034 case LONG_MNEM_SUFFIX:
3035 if (!intel_syntax)
3036 {
3037 i.suffix = mnem_p[-1];
3038 mnem_p[-1] = '\0';
3039 current_templates = hash_find (op_hash, mnemonic);
3040 }
3041 break;
252b5132 3042
29b0f896
AM		 3043 /* Intel Syntax. */
3044 case 'd':
3045 if (intel_syntax)
3046 {
9306ca4a 3047 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3048 i.suffix = SHORT_MNEM_SUFFIX;
3049 else
3050 i.suffix = LONG_MNEM_SUFFIX;
3051 mnem_p[-1] = '\0';
3052 current_templates = hash_find (op_hash, mnemonic);
3053 }
3054 break;
3055 }
3056 if (!current_templates)
3057 {
3058 as_bad (_("no such instruction: `%s'"), token_start);
3059 return NULL;
3060 }
3061 }
252b5132 3062
40fb9820
L		 3063 if (current_templates->start->opcode_modifier.jump
3064 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3065 {
3066 /* Check for a branch hint. We allow ",pt" and ",pn" for
3067 predict taken and predict not taken respectively.
3068 I'm not sure that branch hints actually do anything on loop
3069 and jcxz insns (JumpByte) for current Pentium4 chips. They
3070 may work in the future and it doesn't hurt to accept them
3071 now. */
3072 if (l[0] == ',' && l[1] == 'p')
3073 {
3074 if (l[2] == 't')
3075 {
3076 if (!add_prefix (DS_PREFIX_OPCODE))
3077 return NULL;
3078 l += 3;
3079 }
3080 else if (l[2] == 'n')
3081 {
3082 if (!add_prefix (CS_PREFIX_OPCODE))
3083 return NULL;
3084 l += 3;
3085 }
3086 }
3087 }
3088 /* Any other comma loses. */
3089 if (*l == ',')
3090 {
3091 as_bad (_("invalid character %s in mnemonic"),
3092 output_invalid (*l));
3093 return NULL;
3094 }
252b5132 3095
29b0f896 3096 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3097 supported = 0;
3098 for (t = current_templates->start; t < current_templates->end; ++t)
3099 {
c0f3af97
L		 3100 supported |= cpu_flags_match (t);
3101 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3102 goto skip;
5c6af06e 3103 }
3629bb00 3104
c0f3af97 3105 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3106 {
3107 as_bad (flag_code == CODE_64BIT
3108 ? _("`%s' is not supported in 64-bit mode")
3109 : _("`%s' is only supported in 64-bit mode"),
3110 current_templates->start->name);
3111 return NULL;
3112 }
c0f3af97 3113 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3114 {
3629bb00 3115 as_bad (_("`%s' is not supported on `%s%s'"),
41aacd83
L		 3116 current_templates->start->name,
3117 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3118 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3119 return NULL;
29b0f896 3120 }
3629bb00
L		 3121
3122skip:
3123 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3124 && (flag_code != CODE_16BIT))
29b0f896
AM		 3125 {
3126 as_warn (_("use .code16 to ensure correct addressing mode"));
3127 }
252b5132 3128
29b0f896 3129 /* Check for rep/repne without a string instruction. */
f41bbced 3130 if (expecting_string_instruction)
29b0f896 3131 {
f41bbced
JB		 3132 static templates override;
3133
3134 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3135 if (t->opcode_modifier.isstring)
f41bbced
JB		 3136 break;
3137 if (t >= current_templates->end)
3138 {
3139 as_bad (_("expecting string instruction after `%s'"),
64e74474 3140 expecting_string_instruction);
f41bbced
JB		 3141 return NULL;
3142 }
3143 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3144 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3145 break;
3146 override.end = t;
3147 current_templates = &override;
29b0f896 3148 }
252b5132 3149
29b0f896
AM		 3150 return l;
3151}
252b5132 3152
29b0f896 3153static char *
e3bb37b5 3154parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3155{
3156 char *token_start;
3138f287 3157
29b0f896
AM		 3158 /* 1 if operand is pending after ','. */
3159 unsigned int expecting_operand = 0;
252b5132 3160
29b0f896
AM		 3161 /* Non-zero if operand parens not balanced. */
3162 unsigned int paren_not_balanced;
3163
3164 while (*l != END_OF_INSN)
3165 {
3166 /* Skip optional white space before operand. */
3167 if (is_space_char (*l))
3168 ++l;
3169 if (!is_operand_char (*l) && *l != END_OF_INSN)
3170 {
3171 as_bad (_("invalid character %s before operand %d"),
3172 output_invalid (*l),
3173 i.operands + 1);
3174 return NULL;
3175 }
3176 token_start = l; /* after white space */
3177 paren_not_balanced = 0;
3178 while (paren_not_balanced || *l != ',')
3179 {
3180 if (*l == END_OF_INSN)
3181 {
3182 if (paren_not_balanced)
3183 {
3184 if (!intel_syntax)
3185 as_bad (_("unbalanced parenthesis in operand %d."),
3186 i.operands + 1);
3187 else
3188 as_bad (_("unbalanced brackets in operand %d."),
3189 i.operands + 1);
3190 return NULL;
3191 }
3192 else
3193 break; /* we are done */
3194 }
3195 else if (!is_operand_char (*l) && !is_space_char (*l))
3196 {
3197 as_bad (_("invalid character %s in operand %d"),
3198 output_invalid (*l),
3199 i.operands + 1);
3200 return NULL;
3201 }
3202 if (!intel_syntax)
3203 {
3204 if (*l == '(')
3205 ++paren_not_balanced;
3206 if (*l == ')')
3207 --paren_not_balanced;
3208 }
3209 else
3210 {
3211 if (*l == '[')
3212 ++paren_not_balanced;
3213 if (*l == ']')
3214 --paren_not_balanced;
3215 }
3216 l++;
3217 }
3218 if (l != token_start)
3219 { /* Yes, we've read in another operand. */
3220 unsigned int operand_ok;
3221 this_operand = i.operands++;
7d5e4556 3222 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3223 if (i.operands > MAX_OPERANDS)
3224 {
3225 as_bad (_("spurious operands; (%d operands/instruction max)"),
3226 MAX_OPERANDS);
3227 return NULL;
3228 }
3229 /* Now parse operand adding info to 'i' as we go along. */
3230 END_STRING_AND_SAVE (l);
3231
3232 if (intel_syntax)
3233 operand_ok =
3234 i386_intel_operand (token_start,
3235 intel_float_operand (mnemonic));
3236 else
a7619375 3237 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3238
3239 RESTORE_END_STRING (l);
3240 if (!operand_ok)
3241 return NULL;
3242 }
3243 else
3244 {
3245 if (expecting_operand)
3246 {
3247 expecting_operand_after_comma:
3248 as_bad (_("expecting operand after ','; got nothing"));
3249 return NULL;
3250 }
3251 if (*l == ',')
3252 {
3253 as_bad (_("expecting operand before ','; got nothing"));
3254 return NULL;
3255 }
3256 }
7f3f1ea2 3257
29b0f896
AM		 3258 /* Now *l must be either ',' or END_OF_INSN. */
3259 if (*l == ',')
3260 {
3261 if (*++l == END_OF_INSN)
3262 {
3263 /* Just skip it, if it's \n complain. */
3264 goto expecting_operand_after_comma;
3265 }
3266 expecting_operand = 1;
3267 }
3268 }
3269 return l;
3270}
7f3f1ea2 3271
050dfa73 3272static void
4d456e3d 3273swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3274{
3275 union i386_op temp_op;
40fb9820 3276 i386_operand_type temp_type;
050dfa73 3277 enum bfd_reloc_code_real temp_reloc;
4eed87de 3278
050dfa73
MM		 3279 temp_type = i.types[xchg2];
3280 i.types[xchg2] = i.types[xchg1];
3281 i.types[xchg1] = temp_type;
3282 temp_op = i.op[xchg2];
3283 i.op[xchg2] = i.op[xchg1];
3284 i.op[xchg1] = temp_op;
3285 temp_reloc = i.reloc[xchg2];
3286 i.reloc[xchg2] = i.reloc[xchg1];
3287 i.reloc[xchg1] = temp_reloc;
3288}
3289
29b0f896 3290static void
e3bb37b5 3291swap_operands (void)
29b0f896 3292{
b7c61d9a 3293 switch (i.operands)
050dfa73 3294 {
c0f3af97 3295 case 5:
b7c61d9a 3296 case 4:
4d456e3d 3297 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3298 case 3:
3299 case 2:
4d456e3d 3300 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3301 break;
3302 default:
3303 abort ();
29b0f896 3304 }
29b0f896
AM		 3305
3306 if (i.mem_operands == 2)
3307 {
3308 const seg_entry *temp_seg;
3309 temp_seg = i.seg[0];
3310 i.seg[0] = i.seg[1];
3311 i.seg[1] = temp_seg;
3312 }
3313}
252b5132 3314
29b0f896
AM		 3315/* Try to ensure constant immediates are represented in the smallest
3316 opcode possible. */
3317static void
e3bb37b5 3318optimize_imm (void)
29b0f896
AM		 3319{
3320 char guess_suffix = 0;
3321 int op;
252b5132 3322
29b0f896
AM		 3323 if (i.suffix)
3324 guess_suffix = i.suffix;
3325 else if (i.reg_operands)
3326 {
3327 /* Figure out a suffix from the last register operand specified.
3328 We can't do this properly yet, ie. excluding InOutPortReg,
3329 but the following works for instructions with immediates.
3330 In any case, we can't set i.suffix yet. */
3331 for (op = i.operands; --op >= 0;)
40fb9820
L		 3332 if (i.types[op].bitfield.reg8)
3333 {
3334 guess_suffix = BYTE_MNEM_SUFFIX;
3335 break;
3336 }
3337 else if (i.types[op].bitfield.reg16)
252b5132 3338 {
40fb9820
L		 3339 guess_suffix = WORD_MNEM_SUFFIX;
3340 break;
3341 }
3342 else if (i.types[op].bitfield.reg32)
3343 {
3344 guess_suffix = LONG_MNEM_SUFFIX;
3345 break;
3346 }
3347 else if (i.types[op].bitfield.reg64)
3348 {
3349 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3350 break;
252b5132 3351 }
29b0f896
AM		 3352 }
3353 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3354 guess_suffix = WORD_MNEM_SUFFIX;
3355
3356 for (op = i.operands; --op >= 0;)
40fb9820 3357 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3358 {
3359 switch (i.op[op].imms->X_op)
252b5132 3360 {
29b0f896
AM		 3361 case O_constant:
3362 /* If a suffix is given, this operand may be shortened. */
3363 switch (guess_suffix)
252b5132 3364 {
29b0f896 3365 case LONG_MNEM_SUFFIX:
40fb9820
L		 3366 i.types[op].bitfield.imm32 = 1;
3367 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3368 break;
3369 case WORD_MNEM_SUFFIX:
40fb9820
L		 3370 i.types[op].bitfield.imm16 = 1;
3371 i.types[op].bitfield.imm32 = 1;
3372 i.types[op].bitfield.imm32s = 1;
3373 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3374 break;
3375 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3376 i.types[op].bitfield.imm8 = 1;
3377 i.types[op].bitfield.imm8s = 1;
3378 i.types[op].bitfield.imm16 = 1;
3379 i.types[op].bitfield.imm32 = 1;
3380 i.types[op].bitfield.imm32s = 1;
3381 i.types[op].bitfield.imm64 = 1;
29b0f896 3382 break;
252b5132 3383 }
252b5132 3384
29b0f896
AM		 3385 /* If this operand is at most 16 bits, convert it
3386 to a signed 16 bit number before trying to see
3387 whether it will fit in an even smaller size.
3388 This allows a 16-bit operand such as $0xffe0 to
3389 be recognised as within Imm8S range. */
40fb9820 3390 if ((i.types[op].bitfield.imm16)
29b0f896 3391 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3392 {
29b0f896
AM		 3393 i.op[op].imms->X_add_number =
3394 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3395 }
40fb9820 3396 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3397 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3398 == 0))
3399 {
3400 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3401 ^ ((offsetT) 1 << 31))
3402 - ((offsetT) 1 << 31));
3403 }
40fb9820 3404 i.types[op]
c6fb90c8
L		 3405 = operand_type_or (i.types[op],
3406 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3407
29b0f896
AM		 3408 /* We must avoid matching of Imm32 templates when 64bit
3409 only immediate is available. */
3410 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3411 i.types[op].bitfield.imm32 = 0;
29b0f896 3412 break;
252b5132 3413
29b0f896
AM		 3414 case O_absent:
3415 case O_register:
3416 abort ();
3417
3418 /* Symbols and expressions. */
3419 default:
9cd96992
JB		 3420 /* Convert symbolic operand to proper sizes for matching, but don't
3421 prevent matching a set of insns that only supports sizes other
3422 than those matching the insn suffix. */
3423 {
40fb9820 3424 i386_operand_type mask, allowed;
9cd96992
JB		 3425 const template *t;
3426
0dfbf9d7
L		 3427 operand_type_set (&mask, 0);
3428 operand_type_set (&allowed, 0);
40fb9820 3429
4eed87de
AM		 3430 for (t = current_templates->start;
3431 t < current_templates->end;
3432 ++t)
c6fb90c8
L		 3433 allowed = operand_type_or (allowed,
3434 t->operand_types[op]);
9cd96992
JB		 3435 switch (guess_suffix)
3436 {
3437 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3438 mask.bitfield.imm64 = 1;
3439 mask.bitfield.imm32s = 1;
9cd96992
JB		 3440 break;
3441 case LONG_MNEM_SUFFIX:
40fb9820 3442 mask.bitfield.imm32 = 1;
9cd96992
JB		 3443 break;
3444 case WORD_MNEM_SUFFIX:
40fb9820 3445 mask.bitfield.imm16 = 1;
9cd96992
JB		 3446 break;
3447 case BYTE_MNEM_SUFFIX:
40fb9820 3448 mask.bitfield.imm8 = 1;
9cd96992
JB		 3449 break;
3450 default:
9cd96992
JB		 3451 break;
3452 }
c6fb90c8 3453 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3454 if (!operand_type_all_zero (&allowed))
c6fb90c8 3455 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3456 }
29b0f896 3457 break;
252b5132 3458 }
29b0f896
AM		 3459 }
3460}
47926f60 3461
29b0f896
AM		 3462/* Try to use the smallest displacement type too. */
3463static void
e3bb37b5 3464optimize_disp (void)
29b0f896
AM		 3465{
3466 int op;
3e73aa7c 3467
29b0f896 3468 for (op = i.operands; --op >= 0;)
40fb9820 3469 if (operand_type_check (i.types[op], disp))
252b5132 3470 {
b300c311 3471 if (i.op[op].disps->X_op == O_constant)
252b5132 3472 {
b300c311 3473 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3474
40fb9820 3475 if (i.types[op].bitfield.disp16
b300c311
L		 3476 && (disp & ~(offsetT) 0xffff) == 0)
3477 {
3478 /* If this operand is at most 16 bits, convert
3479 to a signed 16 bit number and don't use 64bit
3480 displacement. */
3481 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3482 i.types[op].bitfield.disp64 = 0;
b300c311 3483 }
40fb9820 3484 if (i.types[op].bitfield.disp32
b300c311
L		 3485 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3486 {
3487 /* If this operand is at most 32 bits, convert
3488 to a signed 32 bit number and don't use 64bit
3489 displacement. */
3490 disp &= (((offsetT) 2 << 31) - 1);
3491 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3492 i.types[op].bitfield.disp64 = 0;
b300c311 3493 }
40fb9820 3494 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3495 {
40fb9820
L		 3496 i.types[op].bitfield.disp8 = 0;
3497 i.types[op].bitfield.disp16 = 0;
3498 i.types[op].bitfield.disp32 = 0;
3499 i.types[op].bitfield.disp32s = 0;
3500 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3501 i.op[op].disps = 0;
3502 i.disp_operands--;
3503 }
3504 else if (flag_code == CODE_64BIT)
3505 {
3506 if (fits_in_signed_long (disp))
28a9d8f5 3507 {
40fb9820
L		 3508 i.types[op].bitfield.disp64 = 0;
3509 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3510 }
b300c311 3511 if (fits_in_unsigned_long (disp))
40fb9820 3512 i.types[op].bitfield.disp32 = 1;
b300c311 3513 }
40fb9820
L		 3514 if ((i.types[op].bitfield.disp32
3515 || i.types[op].bitfield.disp32s
3516 || i.types[op].bitfield.disp16)
b300c311 3517 && fits_in_signed_byte (disp))
40fb9820 3518 i.types[op].bitfield.disp8 = 1;
252b5132 3519 }
67a4f2b7
AO		 3520 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3521 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3522 {
3523 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3524 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3525 i.types[op].bitfield.disp8 = 0;
3526 i.types[op].bitfield.disp16 = 0;
3527 i.types[op].bitfield.disp32 = 0;
3528 i.types[op].bitfield.disp32s = 0;
3529 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3530 }
3531 else
b300c311 3532 /* We only support 64bit displacement on constants. */
40fb9820 3533 i.types[op].bitfield.disp64 = 0;
252b5132 3534 }
29b0f896
AM		 3535}
3536
fa99fab2 3537static const template *
e3bb37b5 3538match_template (void)
29b0f896
AM		 3539{
3540 /* Points to template once we've found it. */
3541 const template *t;
40fb9820 3542 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3543 i386_operand_type overlap4;
29b0f896 3544 unsigned int found_reverse_match;
40fb9820
L		 3545 i386_opcode_modifier suffix_check;
3546 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3547 int addr_prefix_disp;
a5c311ca 3548 unsigned int j;
3629bb00 3549 unsigned int found_cpu_match;
45664ddb 3550 unsigned int check_register;
29b0f896 3551
c0f3af97
L		 3552#if MAX_OPERANDS != 5
3553# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3554#endif
3555
29b0f896 3556 found_reverse_match = 0;
539e75ad 3557 addr_prefix_disp = -1;
40fb9820
L		 3558
3559 memset (&suffix_check, 0, sizeof (suffix_check));
3560 if (i.suffix == BYTE_MNEM_SUFFIX)
3561 suffix_check.no_bsuf = 1;
3562 else if (i.suffix == WORD_MNEM_SUFFIX)
3563 suffix_check.no_wsuf = 1;
3564 else if (i.suffix == SHORT_MNEM_SUFFIX)
3565 suffix_check.no_ssuf = 1;
3566 else if (i.suffix == LONG_MNEM_SUFFIX)
3567 suffix_check.no_lsuf = 1;
3568 else if (i.suffix == QWORD_MNEM_SUFFIX)
3569 suffix_check.no_qsuf = 1;
3570 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3571 suffix_check.no_ldsuf = 1;
29b0f896 3572
45aa61fe 3573 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3574 {
539e75ad
L		 3575 addr_prefix_disp = -1;
3576
29b0f896
AM		 3577 /* Must have right number of operands. */
3578 if (i.operands != t->operands)
3579 continue;
3580
50aecf8c 3581 /* Check processor support. */
c0f3af97
L		 3582 found_cpu_match = (cpu_flags_match (t)
3583 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3584 if (!found_cpu_match)
3585 continue;
3586
e1d4d893
L		 3587 /* Check old gcc support. */
3588 if (!old_gcc && t->opcode_modifier.oldgcc)
3589 continue;
3590
3591 /* Check AT&T mnemonic. */
3592 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3593 continue;
3594
5c07affc
L		 3595 /* Check AT&T syntax Intel syntax. */
3596 if ((intel_syntax && t->opcode_modifier.attsyntax)
3597 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3598 continue;
3599
20592a94 3600 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3601 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3602 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3603 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3604 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3605 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3606 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3607 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3608 continue;
3609
5c07affc 3610 if (!operand_size_match (t))
7d5e4556 3611 continue;
539e75ad 3612
5c07affc
L		 3613 for (j = 0; j < MAX_OPERANDS; j++)
3614 operand_types[j] = t->operand_types[j];
3615
45aa61fe
AM		 3616 /* In general, don't allow 64-bit operands in 32-bit mode. */
3617 if (i.suffix == QWORD_MNEM_SUFFIX
3618 && flag_code != CODE_64BIT
3619 && (intel_syntax
40fb9820 3620 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3621 && !intel_float_operand (t->name))
3622 : intel_float_operand (t->name) != 2)
40fb9820 3623 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3624 && !operand_types[0].bitfield.regxmm
3625 && !operand_types[0].bitfield.regymm)
40fb9820 3626 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3627 && !!operand_types[t->operands > 1].bitfield.regxmm
3628 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3629 && (t->base_opcode != 0x0fc7
3630 || t->extension_opcode != 1 /* cmpxchg8b */))
3631 continue;
3632
192dc9c6
JB		 3633 /* In general, don't allow 32-bit operands on pre-386. */
3634 else if (i.suffix == LONG_MNEM_SUFFIX
3635 && !cpu_arch_flags.bitfield.cpui386
3636 && (intel_syntax
3637 ? (!t->opcode_modifier.ignoresize
3638 && !intel_float_operand (t->name))
3639 : intel_float_operand (t->name) != 2)
3640 && ((!operand_types[0].bitfield.regmmx
3641 && !operand_types[0].bitfield.regxmm)
3642 || (!operand_types[t->operands > 1].bitfield.regmmx
3643 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3644 continue;
3645
29b0f896 3646 /* Do not verify operands when there are none. */
50aecf8c 3647 else
29b0f896 3648 {
c6fb90c8 3649 if (!t->operands)
2dbab7d5
L		 3650 /* We've found a match; break out of loop. */
3651 break;
29b0f896 3652 }
252b5132 3653
539e75ad
L		 3654 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3655 into Disp32/Disp16/Disp32 operand. */
3656 if (i.prefix[ADDR_PREFIX] != 0)
3657 {
40fb9820 3658 /* There should be only one Disp operand. */
539e75ad
L		 3659 switch (flag_code)
3660 {
3661 case CODE_16BIT:
40fb9820
L		 3662 for (j = 0; j < MAX_OPERANDS; j++)
3663 {
3664 if (operand_types[j].bitfield.disp16)
3665 {
3666 addr_prefix_disp = j;
3667 operand_types[j].bitfield.disp32 = 1;
3668 operand_types[j].bitfield.disp16 = 0;
3669 break;
3670 }
3671 }
539e75ad
L		 3672 break;
3673 case CODE_32BIT:
40fb9820
L		 3674 for (j = 0; j < MAX_OPERANDS; j++)
3675 {
3676 if (operand_types[j].bitfield.disp32)
3677 {
3678 addr_prefix_disp = j;
3679 operand_types[j].bitfield.disp32 = 0;
3680 operand_types[j].bitfield.disp16 = 1;
3681 break;
3682 }
3683 }
539e75ad
L		 3684 break;
3685 case CODE_64BIT:
40fb9820
L		 3686 for (j = 0; j < MAX_OPERANDS; j++)
3687 {
3688 if (operand_types[j].bitfield.disp64)
3689 {
3690 addr_prefix_disp = j;
3691 operand_types[j].bitfield.disp64 = 0;
3692 operand_types[j].bitfield.disp32 = 1;
3693 break;
3694 }
3695 }
539e75ad
L		 3696 break;
3697 }
539e75ad
L		 3698 }
3699
45664ddb
L		 3700 /* We check register size only if size of operands can be
3701 encoded the canonical way. */
3702 check_register = t->opcode_modifier.w;
c6fb90c8 3703 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3704 switch (t->operands)
3705 {
3706 case 1:
40fb9820 3707 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3708 continue;
3709 break;
3710 case 2:
8b38ad71
L		 3711 /* xchg %eax, %eax is a special case. It is an aliase for nop
3712 only in 32bit mode and we can use opcode 0x90. In 64bit
3713 mode, we can't use 0x90 for xchg %eax, %eax since it should
3714 zero-extend %eax to %rax. */
3715 if (flag_code == CODE_64BIT
3716 && t->base_opcode == 0x90
0dfbf9d7
L		 3717 && operand_type_equal (&i.types [0], &acc32)
3718 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3719 continue;
b6169b20
L		 3720 if (i.swap_operand)
3721 {
3722 /* If we swap operand in encoding, we either match
3723 the next one or reverse direction of operands. */
3724 if (t->opcode_modifier.s)
3725 continue;
3726 else if (t->opcode_modifier.d)
3727 goto check_reverse;
3728 }
3729
29b0f896 3730 case 3:
fa99fab2
L		 3731 /* If we swap operand in encoding, we match the next one. */
3732 if (i.swap_operand && t->opcode_modifier.s)
3733 continue;
f48ff2ae 3734 case 4:
c0f3af97 3735 case 5:
c6fb90c8 3736 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3737 if (!operand_type_match (overlap0, i.types[0])
3738 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3739 || (check_register
3740 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3741 operand_types[0],
3742 overlap1, i.types[1],
3743 operand_types[1])))
29b0f896
AM		 3744 {
3745 /* Check if other direction is valid ... */
40fb9820 3746 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3747 continue;
3748
b6169b20 3749check_reverse:
29b0f896 3750 /* Try reversing direction of operands. */
c6fb90c8
L		 3751 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3752 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3753 if (!operand_type_match (overlap0, i.types[0])
3754 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3755 || (check_register
3756 && !operand_type_register_match (overlap0,
3757 i.types[0],
3758 operand_types[1],
3759 overlap1,
3760 i.types[1],
3761 operand_types[0])))
29b0f896
AM		 3762 {
3763 /* Does not match either direction. */
3764 continue;
3765 }
3766 /* found_reverse_match holds which of D or FloatDR
3767 we've found. */
40fb9820 3768 if (t->opcode_modifier.d)
8a2ed489 3769 found_reverse_match = Opcode_D;
40fb9820 3770 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3771 found_reverse_match = Opcode_FloatD;
3772 else
3773 found_reverse_match = 0;
40fb9820 3774 if (t->opcode_modifier.floatr)
8a2ed489 3775 found_reverse_match |= Opcode_FloatR;
29b0f896 3776 }
f48ff2ae 3777 else
29b0f896 3778 {
f48ff2ae 3779 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3780 switch (t->operands)
3781 {
c0f3af97
L		 3782 case 5:
3783 overlap4 = operand_type_and (i.types[4],
3784 operand_types[4]);
d1cbb4db 3785 case 4:
c6fb90c8
L		 3786 overlap3 = operand_type_and (i.types[3],
3787 operand_types[3]);
d1cbb4db 3788 case 3:
c6fb90c8
L		 3789 overlap2 = operand_type_and (i.types[2],
3790 operand_types[2]);
d1cbb4db
L		 3791 break;
3792 }
29b0f896 3793
f48ff2ae
L		 3794 switch (t->operands)
3795 {
c0f3af97
L		 3796 case 5:
3797 if (!operand_type_match (overlap4, i.types[4])
3798 || !operand_type_register_match (overlap3,
3799 i.types[3],
3800 operand_types[3],
3801 overlap4,
3802 i.types[4],
3803 operand_types[4]))
3804 continue;
f48ff2ae 3805 case 4:
40fb9820 3806 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3807 || (check_register
3808 && !operand_type_register_match (overlap2,
3809 i.types[2],
3810 operand_types[2],
3811 overlap3,
3812 i.types[3],
3813 operand_types[3])))
f48ff2ae
L		 3814 continue;
3815 case 3:
3816 /* Here we make use of the fact that there are no
3817 reverse match 3 operand instructions, and all 3
3818 operand instructions only need to be checked for
3819 register consistency between operands 2 and 3. */
40fb9820 3820 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3821 || (check_register
3822 && !operand_type_register_match (overlap1,
3823 i.types[1],
3824 operand_types[1],
3825 overlap2,
3826 i.types[2],
3827 operand_types[2])))
f48ff2ae
L		 3828 continue;
3829 break;
3830 }
29b0f896 3831 }
f48ff2ae 3832 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3833 slip through to break. */
3834 }
3629bb00 3835 if (!found_cpu_match)
29b0f896
AM		 3836 {
3837 found_reverse_match = 0;
3838 continue;
3839 }
c0f3af97 3840
29b0f896
AM		 3841 /* We've found a match; break out of loop. */
3842 break;
3843 }
3844
3845 if (t == current_templates->end)
3846 {
3847 /* We found no match. */
95f283e8
L		 3848 if (intel_syntax)
3849 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3850 current_templates->start->name);
3851 else
3852 as_bad (_("suffix or operands invalid for `%s'"),
3853 current_templates->start->name);
fa99fab2 3854 return NULL;
29b0f896 3855 }
252b5132 3856
29b0f896
AM		 3857 if (!quiet_warnings)
3858 {
3859 if (!intel_syntax
40fb9820
L		 3860 && (i.types[0].bitfield.jumpabsolute
3861 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3862 {
3863 as_warn (_("indirect %s without `*'"), t->name);
3864 }
3865
40fb9820
L		 3866 if (t->opcode_modifier.isprefix
3867 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3868 {
3869 /* Warn them that a data or address size prefix doesn't
3870 affect assembly of the next line of code. */
3871 as_warn (_("stand-alone `%s' prefix"), t->name);
3872 }
3873 }
3874
3875 /* Copy the template we found. */
3876 i.tm = *t;
539e75ad
L		 3877
3878 if (addr_prefix_disp != -1)
3879 i.tm.operand_types[addr_prefix_disp]
3880 = operand_types[addr_prefix_disp];
3881
29b0f896
AM		 3882 if (found_reverse_match)
3883 {
3884 /* If we found a reverse match we must alter the opcode
3885 direction bit. found_reverse_match holds bits to change
3886 (different for int & float insns). */
3887
3888 i.tm.base_opcode ^= found_reverse_match;
3889
539e75ad
L		 3890 i.tm.operand_types[0] = operand_types[1];
3891 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3892 }
3893
fa99fab2 3894 return t;
29b0f896
AM		 3895}
3896
3897static int
e3bb37b5 3898check_string (void)
29b0f896 3899{
40fb9820
L		 3900 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3901 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3902 {
3903 if (i.seg[0] != NULL && i.seg[0] != &es)
3904 {
a87af027 3905 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 3906 i.tm.name,
a87af027
JB		 3907 mem_op + 1,
3908 register_prefix);
29b0f896
AM		 3909 return 0;
3910 }
3911 /* There's only ever one segment override allowed per instruction.
3912 This instruction possibly has a legal segment override on the
3913 second operand, so copy the segment to where non-string
3914 instructions store it, allowing common code. */
3915 i.seg[0] = i.seg[1];
3916 }
40fb9820 3917 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3918 {
3919 if (i.seg[1] != NULL && i.seg[1] != &es)
3920 {
a87af027 3921 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 3922 i.tm.name,
a87af027
JB		 3923 mem_op + 2,
3924 register_prefix);
29b0f896
AM		 3925 return 0;
3926 }
3927 }
3928 return 1;
3929}
3930
3931static int
543613e9 3932process_suffix (void)
29b0f896
AM		 3933{
3934 /* If matched instruction specifies an explicit instruction mnemonic
3935 suffix, use it. */
40fb9820
L		 3936 if (i.tm.opcode_modifier.size16)
3937 i.suffix = WORD_MNEM_SUFFIX;
3938 else if (i.tm.opcode_modifier.size32)
3939 i.suffix = LONG_MNEM_SUFFIX;
3940 else if (i.tm.opcode_modifier.size64)
3941 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3942 else if (i.reg_operands)
3943 {
3944 /* If there's no instruction mnemonic suffix we try to invent one
3945 based on register operands. */
3946 if (!i.suffix)
3947 {
3948 /* We take i.suffix from the last register operand specified,
3949 Destination register type is more significant than source
381d071f
L		 3950 register type. crc32 in SSE4.2 prefers source register
3951 type. */
3952 if (i.tm.base_opcode == 0xf20f38f1)
3953 {
40fb9820
L		 3954 if (i.types[0].bitfield.reg16)
3955 i.suffix = WORD_MNEM_SUFFIX;
3956 else if (i.types[0].bitfield.reg32)
3957 i.suffix = LONG_MNEM_SUFFIX;
3958 else if (i.types[0].bitfield.reg64)
3959 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3960 }
9344ff29 3961 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3962 {
40fb9820 3963 if (i.types[0].bitfield.reg8)
20592a94
L		 3964 i.suffix = BYTE_MNEM_SUFFIX;
3965 }
381d071f
L		 3966
3967 if (!i.suffix)
3968 {
3969 int op;
3970
20592a94
L		 3971 if (i.tm.base_opcode == 0xf20f38f1
3972 || i.tm.base_opcode == 0xf20f38f0)
3973 {
3974 /* We have to know the operand size for crc32. */
3975 as_bad (_("ambiguous memory operand size for `%s`"),
3976 i.tm.name);
3977 return 0;
3978 }
3979
381d071f 3980 for (op = i.operands; --op >= 0;)
40fb9820 3981 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3982 {
40fb9820
L		 3983 if (i.types[op].bitfield.reg8)
3984 {
3985 i.suffix = BYTE_MNEM_SUFFIX;
3986 break;
3987 }
3988 else if (i.types[op].bitfield.reg16)
3989 {
3990 i.suffix = WORD_MNEM_SUFFIX;
3991 break;
3992 }
3993 else if (i.types[op].bitfield.reg32)
3994 {
3995 i.suffix = LONG_MNEM_SUFFIX;
3996 break;
3997 }
3998 else if (i.types[op].bitfield.reg64)
3999 {
4000 i.suffix = QWORD_MNEM_SUFFIX;
4001 break;
4002 }
381d071f
L		 4003 }
4004 }
29b0f896
AM		 4005 }
4006 else if (i.suffix == BYTE_MNEM_SUFFIX)
4007 {
4008 if (!check_byte_reg ())
4009 return 0;
4010 }
4011 else if (i.suffix == LONG_MNEM_SUFFIX)
4012 {
4013 if (!check_long_reg ())
4014 return 0;
4015 }
4016 else if (i.suffix == QWORD_MNEM_SUFFIX)
4017 {
955e1e6a
L		 4018 if (intel_syntax
4019 && i.tm.opcode_modifier.ignoresize
4020 && i.tm.opcode_modifier.no_qsuf)
4021 i.suffix = 0;
4022 else if (!check_qword_reg ())
29b0f896
AM		 4023 return 0;
4024 }
4025 else if (i.suffix == WORD_MNEM_SUFFIX)
4026 {
4027 if (!check_word_reg ())
4028 return 0;
4029 }
c0f3af97
L		 4030 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4031 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4032 {
c0f3af97 4033 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4034 should check if it is a valid suffix. */
4035 }
40fb9820 4036 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4037 /* Do nothing if the instruction is going to ignore the prefix. */
4038 ;
4039 else
4040 abort ();
4041 }
40fb9820 4042 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4043 && !i.suffix
4044 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4045 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4046 {
4047 i.suffix = stackop_size;
4048 }
9306ca4a
JB		 4049 else if (intel_syntax
4050 && !i.suffix
40fb9820
L		 4051 && (i.tm.operand_types[0].bitfield.jumpabsolute
4052 || i.tm.opcode_modifier.jumpbyte
4053 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4054 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4055 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4056 {
4057 switch (flag_code)
4058 {
4059 case CODE_64BIT:
40fb9820 4060 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4061 {
4062 i.suffix = QWORD_MNEM_SUFFIX;
4063 break;
4064 }
4065 case CODE_32BIT:
40fb9820 4066 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4067 i.suffix = LONG_MNEM_SUFFIX;
4068 break;
4069 case CODE_16BIT:
40fb9820 4070 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4071 i.suffix = WORD_MNEM_SUFFIX;
4072 break;
4073 }
4074 }
252b5132 4075
9306ca4a 4076 if (!i.suffix)
29b0f896 4077 {
9306ca4a
JB		 4078 if (!intel_syntax)
4079 {
40fb9820 4080 if (i.tm.opcode_modifier.w)
9306ca4a 4081 {
4eed87de
AM		 4082 as_bad (_("no instruction mnemonic suffix given and "
4083 "no register operands; can't size instruction"));
9306ca4a
JB		 4084 return 0;
4085 }
4086 }
4087 else
4088 {
40fb9820
L		 4089 unsigned int suffixes;
4090
4091 suffixes = !i.tm.opcode_modifier.no_bsuf;
4092 if (!i.tm.opcode_modifier.no_wsuf)
4093 suffixes |= 1 << 1;
4094 if (!i.tm.opcode_modifier.no_lsuf)
4095 suffixes |= 1 << 2;
fc4adea1 4096 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4097 suffixes |= 1 << 3;
4098 if (!i.tm.opcode_modifier.no_ssuf)
4099 suffixes |= 1 << 4;
4100 if (!i.tm.opcode_modifier.no_qsuf)
4101 suffixes |= 1 << 5;
4102
4103 /* There are more than suffix matches. */
4104 if (i.tm.opcode_modifier.w
9306ca4a 4105 || ((suffixes & (suffixes - 1))
40fb9820
L		 4106 && !i.tm.opcode_modifier.defaultsize
4107 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4108 {
4109 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4110 return 0;
4111 }
4112 }
29b0f896 4113 }
252b5132 4114
9306ca4a
JB		 4115 /* Change the opcode based on the operand size given by i.suffix;
4116 We don't need to change things for byte insns. */
4117
582d5edd
L		 4118 if (i.suffix
4119 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4120 && i.suffix != XMMWORD_MNEM_SUFFIX
4121 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4122 {
4123 /* It's not a byte, select word/dword operation. */
40fb9820 4124 if (i.tm.opcode_modifier.w)
29b0f896 4125 {
40fb9820 4126 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4127 i.tm.base_opcode |= 8;
4128 else
4129 i.tm.base_opcode |= 1;
4130 }
0f3f3d8b 4131
29b0f896
AM		 4132 /* Now select between word & dword operations via the operand
4133 size prefix, except for instructions that will ignore this
4134 prefix anyway. */
ca61edf2 4135 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4136 {
ca61edf2
L		 4137 /* The address size override prefix changes the size of the
4138 first operand. */
40fb9820
L		 4139 if ((flag_code == CODE_32BIT
4140 && i.op->regs[0].reg_type.bitfield.reg16)
4141 || (flag_code != CODE_32BIT
4142 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4143 if (!add_prefix (ADDR_PREFIX_OPCODE))
4144 return 0;
4145 }
4146 else if (i.suffix != QWORD_MNEM_SUFFIX
4147 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4148 && !i.tm.opcode_modifier.ignoresize
4149 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4150 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4151 || (flag_code == CODE_64BIT
40fb9820 4152 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4153 {
4154 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4155
40fb9820 4156 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4157 prefix = ADDR_PREFIX_OPCODE;
252b5132 4158
29b0f896
AM		 4159 if (!add_prefix (prefix))
4160 return 0;
24eab124 4161 }
252b5132 4162
29b0f896
AM		 4163 /* Set mode64 for an operand. */
4164 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4165 && flag_code == CODE_64BIT
40fb9820 4166 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4167 {
4168 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4169 need rex64. cmpxchg8b is also a special case. */
4170 if (! (i.operands == 2
4171 && i.tm.base_opcode == 0x90
4172 && i.tm.extension_opcode == None
0dfbf9d7
L		 4173 && operand_type_equal (&i.types [0], &acc64)
4174 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4175 && ! (i.operands == 1
4176 && i.tm.base_opcode == 0xfc7
4177 && i.tm.extension_opcode == 1
40fb9820
L		 4178 && !operand_type_check (i.types [0], reg)
4179 && operand_type_check (i.types [0], anymem)))
f6bee062 4180 i.rex |= REX_W;
46e883c5 4181 }
3e73aa7c 4182
29b0f896
AM		 4183 /* Size floating point instruction. */
4184 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4185 if (i.tm.opcode_modifier.floatmf)
543613e9 4186 i.tm.base_opcode ^= 4;
29b0f896 4187 }
7ecd2f8b 4188
29b0f896
AM		 4189 return 1;
4190}
3e73aa7c 4191
29b0f896 4192static int
543613e9 4193check_byte_reg (void)
29b0f896
AM		 4194{
4195 int op;
543613e9 4196
29b0f896
AM		 4197 for (op = i.operands; --op >= 0;)
4198 {
4199 /* If this is an eight bit register, it's OK. If it's the 16 or
4200 32 bit version of an eight bit register, we will just use the
4201 low portion, and that's OK too. */
40fb9820 4202 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4203 continue;
4204
ca61edf2
L		 4205 /* Don't generate this warning if not needed. */
4206 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 4207 continue;
4208
9344ff29
L		 4209 /* crc32 doesn't generate this warning. */
4210 if (i.tm.base_opcode == 0xf20f38f0)
4211 continue;
4212
40fb9820
L		 4213 if ((i.types[op].bitfield.reg16
4214 || i.types[op].bitfield.reg32
4215 || i.types[op].bitfield.reg64)
4216 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4217 {
4218 /* Prohibit these changes in the 64bit mode, since the
4219 lowering is more complicated. */
4220 if (flag_code == CODE_64BIT
40fb9820 4221 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4222 {
2ca3ace5
L		 4223 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4224 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4225 i.suffix);
4226 return 0;
4227 }
4228#if REGISTER_WARNINGS
4229 if (!quiet_warnings
40fb9820 4230 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4231 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4232 register_prefix,
40fb9820 4233 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4234 ? REGNAM_AL - REGNAM_AX
4235 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4236 register_prefix,
29b0f896
AM		 4237 i.op[op].regs->reg_name,
4238 i.suffix);
4239#endif
4240 continue;
4241 }
4242 /* Any other register is bad. */
40fb9820
L		 4243 if (i.types[op].bitfield.reg16
4244 || i.types[op].bitfield.reg32
4245 || i.types[op].bitfield.reg64
4246 || i.types[op].bitfield.regmmx
4247 || i.types[op].bitfield.regxmm
c0f3af97 4248 || i.types[op].bitfield.regymm
40fb9820
L		 4249 || i.types[op].bitfield.sreg2
4250 || i.types[op].bitfield.sreg3
4251 || i.types[op].bitfield.control
4252 || i.types[op].bitfield.debug
4253 || i.types[op].bitfield.test
4254 || i.types[op].bitfield.floatreg
4255 || i.types[op].bitfield.floatacc)
29b0f896 4256 {
a540244d
L		 4257 as_bad (_("`%s%s' not allowed with `%s%c'"),
4258 register_prefix,
29b0f896
AM		 4259 i.op[op].regs->reg_name,
4260 i.tm.name,
4261 i.suffix);
4262 return 0;
4263 }
4264 }
4265 return 1;
4266}
4267
4268static int
e3bb37b5 4269check_long_reg (void)
29b0f896
AM		 4270{
4271 int op;
4272
4273 for (op = i.operands; --op >= 0;)
4274 /* Reject eight bit registers, except where the template requires
4275 them. (eg. movzb) */
40fb9820
L		 4276 if (i.types[op].bitfield.reg8
4277 && (i.tm.operand_types[op].bitfield.reg16
4278 || i.tm.operand_types[op].bitfield.reg32
4279 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4280 {
a540244d
L		 4281 as_bad (_("`%s%s' not allowed with `%s%c'"),
4282 register_prefix,
29b0f896
AM		 4283 i.op[op].regs->reg_name,
4284 i.tm.name,
4285 i.suffix);
4286 return 0;
4287 }
4288 /* Warn if the e prefix on a general reg is missing. */
4289 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4290 && i.types[op].bitfield.reg16
4291 && (i.tm.operand_types[op].bitfield.reg32
4292 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4293 {
4294 /* Prohibit these changes in the 64bit mode, since the
4295 lowering is more complicated. */
4296 if (flag_code == CODE_64BIT)
252b5132 4297 {
2ca3ace5
L		 4298 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4299 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4300 i.suffix);
4301 return 0;
252b5132 4302 }
29b0f896
AM		 4303#if REGISTER_WARNINGS
4304 else
a540244d
L		 4305 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4306 register_prefix,
29b0f896 4307 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4308 register_prefix,
29b0f896
AM		 4309 i.op[op].regs->reg_name,
4310 i.suffix);
4311#endif
252b5132 4312 }
29b0f896 4313 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4314 else if (i.types[op].bitfield.reg64
4315 && (i.tm.operand_types[op].bitfield.reg32
4316 || i.tm.operand_types[op].bitfield.acc))
252b5132 4317 {
34828aad 4318 if (intel_syntax
ca61edf2 4319 && i.tm.opcode_modifier.toqword
40fb9820 4320 && !i.types[0].bitfield.regxmm)
34828aad 4321 {
ca61edf2 4322 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4323 i.suffix = QWORD_MNEM_SUFFIX;
4324 }
4325 else
4326 {
4327 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4328 register_prefix, i.op[op].regs->reg_name,
4329 i.suffix);
4330 return 0;
4331 }
29b0f896
AM		 4332 }
4333 return 1;
4334}
252b5132 4335
29b0f896 4336static int
e3bb37b5 4337check_qword_reg (void)
29b0f896
AM		 4338{
4339 int op;
252b5132 4340
29b0f896
AM		 4341 for (op = i.operands; --op >= 0; )
4342 /* Reject eight bit registers, except where the template requires
4343 them. (eg. movzb) */
40fb9820
L		 4344 if (i.types[op].bitfield.reg8
4345 && (i.tm.operand_types[op].bitfield.reg16
4346 || i.tm.operand_types[op].bitfield.reg32
4347 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4348 {
a540244d
L		 4349 as_bad (_("`%s%s' not allowed with `%s%c'"),
4350 register_prefix,
29b0f896
AM		 4351 i.op[op].regs->reg_name,
4352 i.tm.name,
4353 i.suffix);
4354 return 0;
4355 }
4356 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4357 else if ((i.types[op].bitfield.reg16
4358 || i.types[op].bitfield.reg32)
4359 && (i.tm.operand_types[op].bitfield.reg32
4360 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4361 {
4362 /* Prohibit these changes in the 64bit mode, since the
4363 lowering is more complicated. */
34828aad 4364 if (intel_syntax
ca61edf2 4365 && i.tm.opcode_modifier.todword
40fb9820 4366 && !i.types[0].bitfield.regxmm)
34828aad 4367 {
ca61edf2 4368 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4369 i.suffix = LONG_MNEM_SUFFIX;
4370 }
4371 else
4372 {
4373 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4374 register_prefix, i.op[op].regs->reg_name,
4375 i.suffix);
4376 return 0;
4377 }
252b5132 4378 }
29b0f896
AM		 4379 return 1;
4380}
252b5132 4381
29b0f896 4382static int
e3bb37b5 4383check_word_reg (void)
29b0f896
AM		 4384{
4385 int op;
4386 for (op = i.operands; --op >= 0;)
4387 /* Reject eight bit registers, except where the template requires
4388 them. (eg. movzb) */
40fb9820
L		 4389 if (i.types[op].bitfield.reg8
4390 && (i.tm.operand_types[op].bitfield.reg16
4391 || i.tm.operand_types[op].bitfield.reg32
4392 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4393 {
a540244d
L		 4394 as_bad (_("`%s%s' not allowed with `%s%c'"),
4395 register_prefix,
29b0f896
AM		 4396 i.op[op].regs->reg_name,
4397 i.tm.name,
4398 i.suffix);
4399 return 0;
4400 }
4401 /* Warn if the e prefix on a general reg is present. */
4402 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4403 && i.types[op].bitfield.reg32
4404 && (i.tm.operand_types[op].bitfield.reg16
4405 || i.tm.operand_types[op].bitfield.acc))
252b5132 4406 {
29b0f896
AM		 4407 /* Prohibit these changes in the 64bit mode, since the
4408 lowering is more complicated. */
4409 if (flag_code == CODE_64BIT)
252b5132 4410 {
2ca3ace5
L		 4411 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4412 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4413 i.suffix);
4414 return 0;
252b5132 4415 }
29b0f896
AM		 4416 else
4417#if REGISTER_WARNINGS
a540244d
L		 4418 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4419 register_prefix,
29b0f896 4420 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4421 register_prefix,
29b0f896
AM		 4422 i.op[op].regs->reg_name,
4423 i.suffix);
4424#endif
4425 }
4426 return 1;
4427}
252b5132 4428
29b0f896 4429static int
40fb9820 4430update_imm (unsigned int j)
29b0f896 4431{
40fb9820
L		 4432 i386_operand_type overlap;
4433
c6fb90c8 4434 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 4435 if ((overlap.bitfield.imm8
4436 || overlap.bitfield.imm8s
4437 || overlap.bitfield.imm16
4438 || overlap.bitfield.imm32
4439 || overlap.bitfield.imm32s
4440 || overlap.bitfield.imm64)
0dfbf9d7
L		 4441 && !operand_type_equal (&overlap, &imm8)
4442 && !operand_type_equal (&overlap, &imm8s)
4443 && !operand_type_equal (&overlap, &imm16)
4444 && !operand_type_equal (&overlap, &imm32)
4445 && !operand_type_equal (&overlap, &imm32s)
4446 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4447 {
4448 if (i.suffix)
4449 {
40fb9820
L		 4450 i386_operand_type temp;
4451
0dfbf9d7 4452 operand_type_set (&temp, 0);
40fb9820
L		 4453 if (i.suffix == BYTE_MNEM_SUFFIX)
4454 {
4455 temp.bitfield.imm8 = overlap.bitfield.imm8;
4456 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4457 }
4458 else if (i.suffix == WORD_MNEM_SUFFIX)
4459 temp.bitfield.imm16 = overlap.bitfield.imm16;
4460 else if (i.suffix == QWORD_MNEM_SUFFIX)
4461 {
4462 temp.bitfield.imm64 = overlap.bitfield.imm64;
4463 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4464 }
4465 else
4466 temp.bitfield.imm32 = overlap.bitfield.imm32;
4467 overlap = temp;
29b0f896 4468 }
0dfbf9d7
L		 4469 else if (operand_type_equal (&overlap, &imm16_32_32s)
4470 || operand_type_equal (&overlap, &imm16_32)
4471 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4472 {
40fb9820 4473 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4474 overlap = imm16;
40fb9820 4475 else
65da13b5 4476 overlap = imm32s;
29b0f896 4477 }
0dfbf9d7
L		 4478 if (!operand_type_equal (&overlap, &imm8)
4479 && !operand_type_equal (&overlap, &imm8s)
4480 && !operand_type_equal (&overlap, &imm16)
4481 && !operand_type_equal (&overlap, &imm32)
4482 && !operand_type_equal (&overlap, &imm32s)
4483 && !operand_type_equal (&overlap, &imm64))
29b0f896 4484 {
4eed87de
AM		 4485 as_bad (_("no instruction mnemonic suffix given; "
4486 "can't determine immediate size"));
29b0f896
AM		 4487 return 0;
4488 }
4489 }
40fb9820 4490 i.types[j] = overlap;
29b0f896 4491
40fb9820
L		 4492 return 1;
4493}
4494
4495static int
4496finalize_imm (void)
4497{
4498 unsigned int j;
29b0f896 4499
40fb9820
L		 4500 for (j = 0; j < 2; j++)
4501 if (update_imm (j) == 0)
4502 return 0;
4503
c6fb90c8 4504 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 4505 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 4506
4507 return 1;
4508}
4509
c0f3af97
L		 4510static int
4511bad_implicit_operand (int xmm)
4512{
4513 const char *reg = xmm ? "xmm0" : "ymm0";
4514 if (intel_syntax)
4515 as_bad (_("the last operand of `%s' must be `%s%s'"),
4516 i.tm.name, register_prefix, reg);
4517 else
4518 as_bad (_("the first operand of `%s' must be `%s%s'"),
4519 i.tm.name, register_prefix, reg);
4520 return 0;
4521}
4522
29b0f896 4523static int
e3bb37b5 4524process_operands (void)
29b0f896
AM		 4525{
4526 /* Default segment register this instruction will use for memory
4527 accesses. 0 means unknown. This is only for optimizing out
4528 unnecessary segment overrides. */
4529 const seg_entry *default_seg = 0;
4530
c0f3af97
L		 4531 if (i.tm.opcode_modifier.sse2avx
4532 && (i.tm.opcode_modifier.vexnds
4533 || i.tm.opcode_modifier.vexndd))
29b0f896 4534 {
c0f3af97
L		 4535 unsigned int dup = i.operands;
4536 unsigned int dest = dup - 1;
9fcfb3d7
L		 4537 unsigned int j;
4538
c0f3af97 4539 /* The destination must be an xmm register. */
0dfbf9d7 4540 assert (i.reg_operands
c0f3af97
L		 4541 && MAX_OPERANDS > dup
4542 && operand_type_equal (&i.types[dest], &regxmm));
4543
4544 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4545 {
c0f3af97
L		 4546 /* The first operand is implicit and must be xmm0. */
4547 assert (operand_type_equal (&i.types[0], &regxmm));
4548 if (i.op[0].regs->reg_num != 0)
4549 return bad_implicit_operand (1);
4550
4551 if (i.tm.opcode_modifier.vex3sources)
4552 {
4553 /* Keep xmm0 for instructions with VEX prefix and 3
4554 sources. */
4555 goto duplicate;
4556 }
e2ec9d29 4557 else
c0f3af97
L		 4558 {
4559 /* We remove the first xmm0 and keep the number of
4560 operands unchanged, which in fact duplicates the
4561 destination. */
4562 for (j = 1; j < i.operands; j++)
4563 {
4564 i.op[j - 1] = i.op[j];
4565 i.types[j - 1] = i.types[j];
4566 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4567 }
4568 }
4569 }
4570 else if (i.tm.opcode_modifier.implicit1stxmm0)
4571 {
4572 assert ((MAX_OPERANDS - 1) > dup
4573 && i.tm.opcode_modifier.vex3sources);
4574
4575 /* Add the implicit xmm0 for instructions with VEX prefix
4576 and 3 sources. */
4577 for (j = i.operands; j > 0; j--)
4578 {
4579 i.op[j] = i.op[j - 1];
4580 i.types[j] = i.types[j - 1];
4581 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4582 }
4583 i.op[0].regs
4584 = (const reg_entry *) hash_find (reg_hash, "xmm0");
4585 i.types[0] = regxmm;
4586 i.tm.operand_types[0] = regxmm;
4587
4588 i.operands += 2;
4589 i.reg_operands += 2;
4590 i.tm.operands += 2;
4591
4592 dup++;
4593 dest++;
4594 i.op[dup] = i.op[dest];
4595 i.types[dup] = i.types[dest];
4596 i.tm.operand_types[dup] = i.tm.operand_types[dest];
e2ec9d29 4597 }
c0f3af97
L		 4598 else
4599 {
4600duplicate:
4601 i.operands++;
4602 i.reg_operands++;
4603 i.tm.operands++;
4604
4605 i.op[dup] = i.op[dest];
4606 i.types[dup] = i.types[dest];
4607 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4608 }
4609
4610 if (i.tm.opcode_modifier.immext)
4611 process_immext ();
4612 }
4613 else if (i.tm.opcode_modifier.firstxmm0)
4614 {
4615 unsigned int j;
4616
4617 /* The first operand is implicit and must be xmm0/ymm0. */
4618 assert (i.reg_operands
4619 && (operand_type_equal (&i.types[0], &regxmm)
4620 || operand_type_equal (&i.types[0], &regymm)));
4621 if (i.op[0].regs->reg_num != 0)
4622 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4623
4624 for (j = 1; j < i.operands; j++)
4625 {
4626 i.op[j - 1] = i.op[j];
4627 i.types[j - 1] = i.types[j];
4628
4629 /* We need to adjust fields in i.tm since they are used by
4630 build_modrm_byte. */
4631 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4632 }
4633
e2ec9d29
L		 4634 i.operands--;
4635 i.reg_operands--;
e2ec9d29
L		 4636 i.tm.operands--;
4637 }
4638 else if (i.tm.opcode_modifier.regkludge)
4639 {
4640 /* The imul $imm, %reg instruction is converted into
4641 imul $imm, %reg, %reg, and the clr %reg instruction
4642 is converted into xor %reg, %reg. */
4643
4644 unsigned int first_reg_op;
4645
4646 if (operand_type_check (i.types[0], reg))
4647 first_reg_op = 0;
4648 else
4649 first_reg_op = 1;
4650 /* Pretend we saw the extra register operand. */
4651 assert (i.reg_operands == 1
4652 && i.op[first_reg_op + 1].regs == 0);
4653 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4654 i.types[first_reg_op + 1] = i.types[first_reg_op];
4655 i.operands++;
4656 i.reg_operands++;
29b0f896
AM		 4657 }
4658
40fb9820 4659 if (i.tm.opcode_modifier.shortform)
29b0f896 4660 {
40fb9820
L		 4661 if (i.types[0].bitfield.sreg2
4662 || i.types[0].bitfield.sreg3)
29b0f896 4663 {
4eed87de
AM		 4664 if (i.tm.base_opcode == POP_SEG_SHORT
4665 && i.op[0].regs->reg_num == 1)
29b0f896 4666 {
a87af027 4667 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 4668 return 0;
29b0f896 4669 }
4eed87de
AM		 4670 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4671 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4672 i.rex |= REX_B;
4eed87de
AM		 4673 }
4674 else
4675 {
85f10a01
MM		 4676 /* The register or float register operand is in operand
4677 0 or 1. */
40fb9820
L		 4678 unsigned int op;
4679
4680 if (i.types[0].bitfield.floatreg
4681 || operand_type_check (i.types[0], reg))
4682 op = 0;
4683 else
4684 op = 1;
4eed87de
AM		 4685 /* Register goes in low 3 bits of opcode. */
4686 i.tm.base_opcode |= i.op[op].regs->reg_num;
4687 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4688 i.rex |= REX_B;
40fb9820 4689 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4690 {
4eed87de
AM		 4691 /* Warn about some common errors, but press on regardless.
4692 The first case can be generated by gcc (<= 2.8.1). */
4693 if (i.operands == 2)
4694 {
4695 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 4696 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 4697 register_prefix, i.op[!intel_syntax].regs->reg_name,
4698 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 4699 }
4700 else
4701 {
4702 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4703 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4704 register_prefix, i.op[0].regs->reg_name);
4eed87de 4705 }
29b0f896
AM		 4706 }
4707 }
4708 }
40fb9820 4709 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4710 {
4711 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4712 must be put into the modrm byte). Now, we make the modrm and
4713 index base bytes based on all the info we've collected. */
29b0f896
AM		 4714
4715 default_seg = build_modrm_byte ();
4716 }
8a2ed489 4717 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4718 {
4719 default_seg = &ds;
4720 }
40fb9820 4721 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4722 {
4723 /* For the string instructions that allow a segment override
4724 on one of their operands, the default segment is ds. */
4725 default_seg = &ds;
4726 }
4727
75178d9d
L		 4728 if (i.tm.base_opcode == 0x8d /* lea */
4729 && i.seg[0]
4730 && !quiet_warnings)
30123838 4731 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4732
4733 /* If a segment was explicitly specified, and the specified segment
4734 is not the default, use an opcode prefix to select it. If we
4735 never figured out what the default segment is, then default_seg
4736 will be zero at this point, and the specified segment prefix will
4737 always be used. */
29b0f896
AM		 4738 if ((i.seg[0]) && (i.seg[0] != default_seg))
4739 {
4740 if (!add_prefix (i.seg[0]->seg_prefix))
4741 return 0;
4742 }
4743 return 1;
4744}
4745
4746static const seg_entry *
e3bb37b5 4747build_modrm_byte (void)
29b0f896
AM		 4748{
4749 const seg_entry *default_seg = 0;
c0f3af97
L		 4750 unsigned int source, dest;
4751 int vex_3_sources;
4752
4753 /* The first operand of instructions with VEX prefix and 3 sources
4754 must be VEX_Imm4. */
4755 vex_3_sources = i.tm.opcode_modifier.vex3sources;
4756 if (vex_3_sources)
4757 {
4758 unsigned int nds, reg;
4759
0bfee649 4760 dest = i.operands - 1;
c0f3af97 4761 nds = dest - 1;
0bfee649
L		 4762 source = 1;
4763 reg = 0;
4764
4765 /* This instruction must have 4 operands: 4 register operands
4766 or 3 register operands plus 1 memory operand. It must have
4767 VexNDS and VexImmExt. */
4768 assert (i.operands == 4
4769 && (i.reg_operands == 4
4770 || (i.reg_operands == 3 && i.mem_operands == 1))
4771 && i.tm.opcode_modifier.vexnds
4772 && i.tm.opcode_modifier.veximmext
4773 && (operand_type_equal (&i.tm.operand_types[dest],
4774 &regxmm)
4775 || operand_type_equal (&i.tm.operand_types[dest],
4776 &regymm))
4777 && (operand_type_equal (&i.tm.operand_types[nds],
4778 &regxmm)
4779 || operand_type_equal (&i.tm.operand_types[nds],
4780 &regymm))
4781 && (operand_type_equal (&i.tm.operand_types[reg],
4782 &regxmm)
c0f3af97 4783 || operand_type_equal (&i.tm.operand_types[reg],
0bfee649 4784 &regymm)));
c0f3af97 4785
0bfee649
L		 4786 /* Generate an 8bit immediate operand to encode the register
4787 operand. */
4788 expressionS *exp = &im_expressions[i.imm_operands++];
4789 i.op[i.operands].imms = exp;
4790 i.types[i.operands] = imm8;
4791 i.operands++;
4792 exp->X_op = O_constant;
4793 exp->X_add_number
4794 = ((i.op[0].regs->reg_num
4795 + ((i.op[0].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
dae39acc 4796
dae39acc 4797 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 4798 }
4799 else
4800 source = dest = 0;
29b0f896
AM		 4801
4802 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 4803 implicit registers do not count. If there are 3 register
4804 operands, it must be a instruction with VexNDS. For a
4805 instruction with VexNDD, the destination register is encoded
4806 in VEX prefix. If there are 4 register operands, it must be
4807 a instruction with VEX prefix and 3 sources. */
c1e679ec 4808 if (i.mem_operands == 0
c0f3af97
L		 4809 && ((i.reg_operands == 2
4810 && !i.tm.opcode_modifier.vexndd)
4811 || (i.reg_operands == 3
4812 && i.tm.opcode_modifier.vexnds)
4813 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 4814 {
cab737b9
L		 4815 switch (i.operands)
4816 {
4817 case 2:
4818 source = 0;
4819 break;
4820 case 3:
c81128dc
L		 4821 /* When there are 3 operands, one of them may be immediate,
4822 which may be the first or the last operand. Otherwise,
c0f3af97
L		 4823 the first operand must be shift count register (cl) or it
4824 is an instruction with VexNDS. */
c81128dc
L		 4825 assert (i.imm_operands == 1
4826 || (i.imm_operands == 0
c0f3af97
L		 4827 && (i.tm.opcode_modifier.vexnds
4828 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 4829 if (operand_type_check (i.types[0], imm)
4830 || i.types[0].bitfield.shiftcount)
4831 source = 1;
4832 else
4833 source = 0;
cab737b9
L		 4834 break;
4835 case 4:
368d64cc
L		 4836 /* When there are 4 operands, the first two must be 8bit
4837 immediate operands. The source operand will be the 3rd
c0f3af97
L		 4838 one.
4839
4840 For instructions with VexNDS, if the first operand
4841 an imm8, the source operand is the 2nd one. If the last
4842 operand is imm8, the source operand is the first one. */
4843 assert ((i.imm_operands == 2
4844 && i.types[0].bitfield.imm8
4845 && i.types[1].bitfield.imm8)
4846 || (i.tm.opcode_modifier.vexnds
4847 && i.imm_operands == 1
4848 && (i.types[0].bitfield.imm8
4849 || i.types[i.operands - 1].bitfield.imm8)));
4850 if (i.tm.opcode_modifier.vexnds)
4851 {
4852 if (i.types[0].bitfield.imm8)
4853 source = 1;
4854 else
4855 source = 0;
4856 }
4857 else
4858 source = 2;
4859 break;
4860 case 5:
cab737b9
L		 4861 break;
4862 default:
4863 abort ();
4864 }
4865
c0f3af97
L		 4866 if (!vex_3_sources)
4867 {
4868 dest = source + 1;
4869
4870 if (i.tm.opcode_modifier.vexnds)
4871 {
4872 /* For instructions with VexNDS, the register-only
4873 source operand must be XMM or YMM register. It is
fa99fab2
L		 4874 encoded in VEX prefix. We need to clear RegMem bit
4875 before calling operand_type_equal. */
4876 i386_operand_type op = i.tm.operand_types[dest];
4877 op.bitfield.regmem = 0;
c0f3af97 4878 if ((dest + 1) >= i.operands
fa99fab2
L		 4879 || (!operand_type_equal (&op, &regxmm)
4880 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 4881 abort ();
4882 i.vex.register_specifier = i.op[dest].regs;
4883 dest++;
4884 }
4885 }
29b0f896
AM		 4886
4887 i.rm.mode = 3;
4888 /* One of the register operands will be encoded in the i.tm.reg
4889 field, the other in the combined i.tm.mode and i.tm.regmem
4890 fields. If no form of this instruction supports a memory
4891 destination operand, then we assume the source operand may
4892 sometimes be a memory operand and so we need to store the
4893 destination in the i.rm.reg field. */
40fb9820
L		 4894 if (!i.tm.operand_types[dest].bitfield.regmem
4895 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 4896 {
4897 i.rm.reg = i.op[dest].regs->reg_num;
4898 i.rm.regmem = i.op[source].regs->reg_num;
4899 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4900 i.rex |= REX_R;
29b0f896 4901 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4902 i.rex |= REX_B;
29b0f896
AM		 4903 }
4904 else
4905 {
4906 i.rm.reg = i.op[source].regs->reg_num;
4907 i.rm.regmem = i.op[dest].regs->reg_num;
4908 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4909 i.rex |= REX_B;
29b0f896 4910 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4911 i.rex |= REX_R;
29b0f896 4912 }
161a04f6 4913 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 4914 {
40fb9820
L		 4915 if (!i.types[0].bitfield.control
4916 && !i.types[1].bitfield.control)
c4a530c5 4917 abort ();
161a04f6 4918 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 4919 add_prefix (LOCK_PREFIX_OPCODE);
4920 }
29b0f896
AM		 4921 }
4922 else
4923 { /* If it's not 2 reg operands... */
c0f3af97
L		 4924 unsigned int mem;
4925
29b0f896
AM		 4926 if (i.mem_operands)
4927 {
4928 unsigned int fake_zero_displacement = 0;
99018f42 4929 unsigned int op;
4eed87de 4930
c0209578
L		 4931 for (op = 0; op < i.operands; op++)
4932 if (operand_type_check (i.types[op], anymem))
4933 break;
4934 assert (op < i.operands);
29b0f896
AM		 4935
4936 default_seg = &ds;
4937
4938 if (i.base_reg == 0)
4939 {
4940 i.rm.mode = 0;
4941 if (!i.disp_operands)
4942 fake_zero_displacement = 1;
4943 if (i.index_reg == 0)
4944 {
4945 /* Operand is just <disp> */
20f0a1fc 4946 if (flag_code == CODE_64BIT)
29b0f896
AM		 4947 {
4948 /* 64bit mode overwrites the 32bit absolute
4949 addressing by RIP relative addressing and
4950 absolute addressing is encoded by one of the
4951 redundant SIB forms. */
4952 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4953 i.sib.base = NO_BASE_REGISTER;
4954 i.sib.index = NO_INDEX_REGISTER;
fc225355 4955 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 4956 ? disp32s : disp32);
20f0a1fc 4957 }
fc225355
L		 4958 else if ((flag_code == CODE_16BIT)
4959 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 4960 {
4961 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 4962 i.types[op] = disp16;
20f0a1fc
NC		 4963 }
4964 else
4965 {
4966 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 4967 i.types[op] = disp32;
29b0f896
AM		 4968 }
4969 }
4970 else /* !i.base_reg && i.index_reg */
4971 {
db51cc60
L		 4972 if (i.index_reg->reg_num == RegEiz
4973 || i.index_reg->reg_num == RegRiz)
4974 i.sib.index = NO_INDEX_REGISTER;
4975 else
4976 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4977 i.sib.base = NO_BASE_REGISTER;
4978 i.sib.scale = i.log2_scale_factor;
4979 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 4980 i.types[op].bitfield.disp8 = 0;
4981 i.types[op].bitfield.disp16 = 0;
4982 i.types[op].bitfield.disp64 = 0;
29b0f896 4983 if (flag_code != CODE_64BIT)
40fb9820
L		 4984 {
4985 /* Must be 32 bit */
4986 i.types[op].bitfield.disp32 = 1;
4987 i.types[op].bitfield.disp32s = 0;
4988 }
29b0f896 4989 else
40fb9820
L		 4990 {
4991 i.types[op].bitfield.disp32 = 0;
4992 i.types[op].bitfield.disp32s = 1;
4993 }
29b0f896 4994 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4995 i.rex |= REX_X;
29b0f896
AM		 4996 }
4997 }
4998 /* RIP addressing for 64bit mode. */
9a04903e
JB		 4999 else if (i.base_reg->reg_num == RegRip ||
5000 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5001 {
5002 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5003 i.types[op].bitfield.disp8 = 0;
5004 i.types[op].bitfield.disp16 = 0;
5005 i.types[op].bitfield.disp32 = 0;
5006 i.types[op].bitfield.disp32s = 1;
5007 i.types[op].bitfield.disp64 = 0;
71903a11 5008 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5009 if (! i.disp_operands)
5010 fake_zero_displacement = 1;
29b0f896 5011 }
40fb9820 5012 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5013 {
5014 switch (i.base_reg->reg_num)
5015 {
5016 case 3: /* (%bx) */
5017 if (i.index_reg == 0)
5018 i.rm.regmem = 7;
5019 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5020 i.rm.regmem = i.index_reg->reg_num - 6;
5021 break;
5022 case 5: /* (%bp) */
5023 default_seg = &ss;
5024 if (i.index_reg == 0)
5025 {
5026 i.rm.regmem = 6;
40fb9820 5027 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5028 {
5029 /* fake (%bp) into 0(%bp) */
40fb9820 5030 i.types[op].bitfield.disp8 = 1;
252b5132 5031 fake_zero_displacement = 1;
29b0f896
AM		 5032 }
5033 }
5034 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5035 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5036 break;
5037 default: /* (%si) -> 4 or (%di) -> 5 */
5038 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5039 }
5040 i.rm.mode = mode_from_disp_size (i.types[op]);
5041 }
5042 else /* i.base_reg and 32/64 bit mode */
5043 {
5044 if (flag_code == CODE_64BIT
40fb9820
L		 5045 && operand_type_check (i.types[op], disp))
5046 {
5047 i386_operand_type temp;
0dfbf9d7 5048 operand_type_set (&temp, 0);
40fb9820
L		 5049 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5050 i.types[op] = temp;
5051 if (i.prefix[ADDR_PREFIX] == 0)
5052 i.types[op].bitfield.disp32s = 1;
5053 else
5054 i.types[op].bitfield.disp32 = 1;
5055 }
20f0a1fc 5056
29b0f896
AM		 5057 i.rm.regmem = i.base_reg->reg_num;
5058 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5059 i.rex |= REX_B;
29b0f896
AM		 5060 i.sib.base = i.base_reg->reg_num;
5061 /* x86-64 ignores REX prefix bit here to avoid decoder
5062 complications. */
5063 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5064 {
5065 default_seg = &ss;
5066 if (i.disp_operands == 0)
5067 {
5068 fake_zero_displacement = 1;
40fb9820 5069 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5070 }
5071 }
5072 else if (i.base_reg->reg_num == ESP_REG_NUM)
5073 {
5074 default_seg = &ss;
5075 }
5076 i.sib.scale = i.log2_scale_factor;
5077 if (i.index_reg == 0)
5078 {
5079 /* <disp>(%esp) becomes two byte modrm with no index
5080 register. We've already stored the code for esp
5081 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5082 Any base register besides %esp will not use the
5083 extra modrm byte. */
5084 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5085 }
5086 else
5087 {
db51cc60
L		 5088 if (i.index_reg->reg_num == RegEiz
5089 || i.index_reg->reg_num == RegRiz)
5090 i.sib.index = NO_INDEX_REGISTER;
5091 else
5092 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5093 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5094 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5095 i.rex |= REX_X;
29b0f896 5096 }
67a4f2b7
AO		 5097
5098 if (i.disp_operands
5099 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5100 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5101 i.rm.mode = 0;
5102 else
5103 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5104 }
252b5132 5105
29b0f896
AM		 5106 if (fake_zero_displacement)
5107 {
5108 /* Fakes a zero displacement assuming that i.types[op]
5109 holds the correct displacement size. */
5110 expressionS *exp;
5111
5112 assert (i.op[op].disps == 0);
5113 exp = &disp_expressions[i.disp_operands++];
5114 i.op[op].disps = exp;
5115 exp->X_op = O_constant;
5116 exp->X_add_number = 0;
5117 exp->X_add_symbol = (symbolS *) 0;
5118 exp->X_op_symbol = (symbolS *) 0;
5119 }
c0f3af97
L		 5120
5121 mem = op;
29b0f896 5122 }
c0f3af97
L		 5123 else
5124 mem = ~0;
252b5132 5125
29b0f896
AM		 5126 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5127 (if any) based on i.tm.extension_opcode. Again, we must be
5128 careful to make sure that segment/control/debug/test/MMX
5129 registers are coded into the i.rm.reg field. */
5130 if (i.reg_operands)
5131 {
99018f42 5132 unsigned int op;
c0f3af97
L		 5133 unsigned int vex_reg = ~0;
5134
c0209578
L		 5135 for (op = 0; op < i.operands; op++)
5136 if (i.types[op].bitfield.reg8
5137 || i.types[op].bitfield.reg16
5138 || i.types[op].bitfield.reg32
5139 || i.types[op].bitfield.reg64
5140 || i.types[op].bitfield.regmmx
5141 || i.types[op].bitfield.regxmm
c0f3af97 5142 || i.types[op].bitfield.regymm
c0209578
L		 5143 || i.types[op].bitfield.sreg2
5144 || i.types[op].bitfield.sreg3
5145 || i.types[op].bitfield.control
5146 || i.types[op].bitfield.debug
5147 || i.types[op].bitfield.test)
5148 break;
5149
c0f3af97
L		 5150 if (vex_3_sources)
5151 op = dest;
5152 else if (i.tm.opcode_modifier.vexnds)
5153 {
5154 /* For instructions with VexNDS, the register-only
5155 source operand is encoded in VEX prefix. */
5156 assert (mem != (unsigned int) ~0);
5157
5158 if (op > mem)
5159 {
5160 vex_reg = op++;
5161 assert (op < i.operands);
5162 }
5163 else
5164 {
5165 vex_reg = op + 1;
5166 assert (vex_reg < i.operands);
5167 }
5168 }
5169 else if (i.tm.opcode_modifier.vexndd)
5170 {
5171 /* For instructions with VexNDD, there should be
5172 no memory operand and the register destination
5173 is encoded in VEX prefix. */
5174 assert (i.mem_operands == 0
5175 && (op + 2) == i.operands);
5176 vex_reg = op + 1;
5177 }
5178 else
5179 assert (op < i.operands);
5180
5181 if (vex_reg != (unsigned int) ~0)
5182 {
5183 assert (i.reg_operands == 2);
5184
5185 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
5186 & regxmm)
5187 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5188 &regymm))
5189 abort ();
5190 i.vex.register_specifier = i.op[vex_reg].regs;
5191 }
99018f42 5192
85f10a01
MM		 5193 /* If there is an extension opcode to put here, the
5194 register number must be put into the regmem field. */
c0209578
L		 5195 if (i.tm.extension_opcode != None)
5196 {
5197 i.rm.regmem = i.op[op].regs->reg_num;
5198 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5199 i.rex |= REX_B;
5200 }
5201 else
5202 {
5203 i.rm.reg = i.op[op].regs->reg_num;
5204 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5205 i.rex |= REX_R;
5206 }
252b5132 5207
29b0f896
AM		 5208 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5209 must set it to 3 to indicate this is a register operand
5210 in the regmem field. */
5211 if (!i.mem_operands)
5212 i.rm.mode = 3;
5213 }
252b5132 5214
29b0f896 5215 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5216 if (i.tm.extension_opcode != None)
29b0f896
AM		 5217 i.rm.reg = i.tm.extension_opcode;
5218 }
5219 return default_seg;
5220}
252b5132 5221
29b0f896 5222static void
e3bb37b5 5223output_branch (void)
29b0f896
AM		 5224{
5225 char *p;
5226 int code16;
5227 int prefix;
5228 relax_substateT subtype;
5229 symbolS *sym;
5230 offsetT off;
5231
5232 code16 = 0;
5233 if (flag_code == CODE_16BIT)
5234 code16 = CODE16;
5235
5236 prefix = 0;
5237 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5238 {
29b0f896
AM		 5239 prefix = 1;
5240 i.prefixes -= 1;
5241 code16 ^= CODE16;
252b5132 5242 }
29b0f896
AM		 5243 /* Pentium4 branch hints. */
5244 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5245 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5246 {
29b0f896
AM		 5247 prefix++;
5248 i.prefixes--;
5249 }
5250 if (i.prefix[REX_PREFIX] != 0)
5251 {
5252 prefix++;
5253 i.prefixes--;
2f66722d
AM		 5254 }
5255
29b0f896
AM		 5256 if (i.prefixes != 0 && !intel_syntax)
5257 as_warn (_("skipping prefixes on this instruction"));
5258
5259 /* It's always a symbol; End frag & setup for relax.
5260 Make sure there is enough room in this frag for the largest
5261 instruction we may generate in md_convert_frag. This is 2
5262 bytes for the opcode and room for the prefix and largest
5263 displacement. */
5264 frag_grow (prefix + 2 + 4);
5265 /* Prefix and 1 opcode byte go in fr_fix. */
5266 p = frag_more (prefix + 1);
5267 if (i.prefix[DATA_PREFIX] != 0)
5268 *p++ = DATA_PREFIX_OPCODE;
5269 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5270 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5271 *p++ = i.prefix[SEG_PREFIX];
5272 if (i.prefix[REX_PREFIX] != 0)
5273 *p++ = i.prefix[REX_PREFIX];
5274 *p = i.tm.base_opcode;
5275
5276 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5277 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5278 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5279 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5280 else
5281 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5282 subtype |= code16;
3e73aa7c 5283
29b0f896
AM		 5284 sym = i.op[0].disps->X_add_symbol;
5285 off = i.op[0].disps->X_add_number;
3e73aa7c 5286
29b0f896
AM		 5287 if (i.op[0].disps->X_op != O_constant
5288 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5289 {
29b0f896
AM		 5290 /* Handle complex expressions. */
5291 sym = make_expr_symbol (i.op[0].disps);
5292 off = 0;
5293 }
3e73aa7c 5294
29b0f896
AM		 5295 /* 1 possible extra opcode + 4 byte displacement go in var part.
5296 Pass reloc in fr_var. */
5297 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5298}
3e73aa7c 5299
29b0f896 5300static void
e3bb37b5 5301output_jump (void)
29b0f896
AM		 5302{
5303 char *p;
5304 int size;
3e02c1cc 5305 fixS *fixP;
29b0f896 5306
40fb9820 5307 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5308 {
5309 /* This is a loop or jecxz type instruction. */
5310 size = 1;
5311 if (i.prefix[ADDR_PREFIX] != 0)
5312 {
5313 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5314 i.prefixes -= 1;
5315 }
5316 /* Pentium4 branch hints. */
5317 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5318 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5319 {
5320 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5321 i.prefixes--;
3e73aa7c
JH		 5322 }
5323 }
29b0f896
AM		 5324 else
5325 {
5326 int code16;
3e73aa7c 5327
29b0f896
AM		 5328 code16 = 0;
5329 if (flag_code == CODE_16BIT)
5330 code16 = CODE16;
3e73aa7c 5331
29b0f896
AM		 5332 if (i.prefix[DATA_PREFIX] != 0)
5333 {
5334 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5335 i.prefixes -= 1;
5336 code16 ^= CODE16;
5337 }
252b5132 5338
29b0f896
AM		 5339 size = 4;
5340 if (code16)
5341 size = 2;
5342 }
9fcc94b6 5343
29b0f896
AM		 5344 if (i.prefix[REX_PREFIX] != 0)
5345 {
5346 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5347 i.prefixes -= 1;
5348 }
252b5132 5349
29b0f896
AM		 5350 if (i.prefixes != 0 && !intel_syntax)
5351 as_warn (_("skipping prefixes on this instruction"));
e0890092 5352
29b0f896
AM		 5353 p = frag_more (1 + size);
5354 *p++ = i.tm.base_opcode;
e0890092 5355
3e02c1cc
AM		 5356 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5357 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5358
5359 /* All jumps handled here are signed, but don't use a signed limit
5360 check for 32 and 16 bit jumps as we want to allow wrap around at
5361 4G and 64k respectively. */
5362 if (size == 1)
5363 fixP->fx_signed = 1;
29b0f896 5364}
e0890092 5365
29b0f896 5366static void
e3bb37b5 5367output_interseg_jump (void)
29b0f896
AM		 5368{
5369 char *p;
5370 int size;
5371 int prefix;
5372 int code16;
252b5132 5373
29b0f896
AM		 5374 code16 = 0;
5375 if (flag_code == CODE_16BIT)
5376 code16 = CODE16;
a217f122 5377
29b0f896
AM		 5378 prefix = 0;
5379 if (i.prefix[DATA_PREFIX] != 0)
5380 {
5381 prefix = 1;
5382 i.prefixes -= 1;
5383 code16 ^= CODE16;
5384 }
5385 if (i.prefix[REX_PREFIX] != 0)
5386 {
5387 prefix++;
5388 i.prefixes -= 1;
5389 }
252b5132 5390
29b0f896
AM		 5391 size = 4;
5392 if (code16)
5393 size = 2;
252b5132 5394
29b0f896
AM		 5395 if (i.prefixes != 0 && !intel_syntax)
5396 as_warn (_("skipping prefixes on this instruction"));
252b5132 5397
29b0f896
AM		 5398 /* 1 opcode; 2 segment; offset */
5399 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5400
29b0f896
AM		 5401 if (i.prefix[DATA_PREFIX] != 0)
5402 *p++ = DATA_PREFIX_OPCODE;
252b5132 5403
29b0f896
AM		 5404 if (i.prefix[REX_PREFIX] != 0)
5405 *p++ = i.prefix[REX_PREFIX];
252b5132 5406
29b0f896
AM		 5407 *p++ = i.tm.base_opcode;
5408 if (i.op[1].imms->X_op == O_constant)
5409 {
5410 offsetT n = i.op[1].imms->X_add_number;
252b5132 5411
29b0f896
AM		 5412 if (size == 2
5413 && !fits_in_unsigned_word (n)
5414 && !fits_in_signed_word (n))
5415 {
5416 as_bad (_("16-bit jump out of range"));
5417 return;
5418 }
5419 md_number_to_chars (p, n, size);
5420 }
5421 else
5422 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5423 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5424 if (i.op[0].imms->X_op != O_constant)
5425 as_bad (_("can't handle non absolute segment in `%s'"),
5426 i.tm.name);
5427 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5428}
a217f122 5429
29b0f896 5430static void
e3bb37b5 5431output_insn (void)
29b0f896 5432{
2bbd9c25
JJ		 5433 fragS *insn_start_frag;
5434 offsetT insn_start_off;
5435
29b0f896
AM		 5436 /* Tie dwarf2 debug info to the address at the start of the insn.
5437 We can't do this after the insn has been output as the current
5438 frag may have been closed off. eg. by frag_var. */
5439 dwarf2_emit_insn (0);
5440
2bbd9c25
JJ		 5441 insn_start_frag = frag_now;
5442 insn_start_off = frag_now_fix ();
5443
29b0f896 5444 /* Output jumps. */
40fb9820 5445 if (i.tm.opcode_modifier.jump)
29b0f896 5446 output_branch ();
40fb9820
L		 5447 else if (i.tm.opcode_modifier.jumpbyte
5448 || i.tm.opcode_modifier.jumpdword)
29b0f896 5449 output_jump ();
40fb9820 5450 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5451 output_interseg_jump ();
5452 else
5453 {
5454 /* Output normal instructions here. */
5455 char *p;
5456 unsigned char *q;
47465058 5457 unsigned int j;
331d2d0d 5458 unsigned int prefix;
4dffcebc 5459
c0f3af97
L		 5460 /* Since the VEX prefix contains the implicit prefix, we don't
5461 need the explicit prefix. */
5462 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5463 {
c0f3af97 5464 switch (i.tm.opcode_length)
bc4bd9ab 5465 {
c0f3af97
L		 5466 case 3:
5467 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5468 {
c0f3af97
L		 5469 prefix = (i.tm.base_opcode >> 24) & 0xff;
5470 goto check_prefix;
5471 }
5472 break;
5473 case 2:
5474 if ((i.tm.base_opcode & 0xff0000) != 0)
5475 {
5476 prefix = (i.tm.base_opcode >> 16) & 0xff;
5477 if (i.tm.cpu_flags.bitfield.cpupadlock)
5478 {
4dffcebc 5479check_prefix:
c0f3af97
L		 5480 if (prefix != REPE_PREFIX_OPCODE
5481 || (i.prefix[LOCKREP_PREFIX]
5482 != REPE_PREFIX_OPCODE))
5483 add_prefix (prefix);
5484 }
5485 else
4dffcebc
L		 5486 add_prefix (prefix);
5487 }
c0f3af97
L		 5488 break;
5489 case 1:
5490 break;
5491 default:
5492 abort ();
bc4bd9ab 5493 }
c0f3af97
L		 5494
5495 /* The prefix bytes. */
5496 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5497 if (*q)
5498 FRAG_APPEND_1_CHAR (*q);
0f10071e 5499 }
252b5132 5500
c0f3af97
L		 5501 if (i.tm.opcode_modifier.vex)
5502 {
5503 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5504 if (*q)
5505 switch (j)
5506 {
5507 case REX_PREFIX:
5508 /* REX byte is encoded in VEX prefix. */
5509 break;
5510 case SEG_PREFIX:
5511 case ADDR_PREFIX:
5512 FRAG_APPEND_1_CHAR (*q);
5513 break;
5514 default:
5515 /* There should be no other prefixes for instructions
5516 with VEX prefix. */
5517 abort ();
5518 }
5519
5520 /* Now the VEX prefix. */
5521 p = frag_more (i.vex.length);
5522 for (j = 0; j < i.vex.length; j++)
5523 p[j] = i.vex.bytes[j];
5524 }
252b5132 5525
29b0f896 5526 /* Now the opcode; be careful about word order here! */
4dffcebc 5527 if (i.tm.opcode_length == 1)
29b0f896
AM		 5528 {
5529 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5530 }
5531 else
5532 {
4dffcebc 5533 switch (i.tm.opcode_length)
331d2d0d 5534 {
4dffcebc 5535 case 3:
331d2d0d
L		 5536 p = frag_more (3);
5537 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5538 break;
5539 case 2:
5540 p = frag_more (2);
5541 break;
5542 default:
5543 abort ();
5544 break;
331d2d0d 5545 }
0f10071e 5546
29b0f896
AM		 5547 /* Put out high byte first: can't use md_number_to_chars! */
5548 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5549 *p = i.tm.base_opcode & 0xff;
5550 }
3e73aa7c 5551
29b0f896 5552 /* Now the modrm byte and sib byte (if present). */
40fb9820 5553 if (i.tm.opcode_modifier.modrm)
29b0f896 5554 {
4a3523fa
L		 5555 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5556 | i.rm.reg << 3
5557 | i.rm.mode << 6));
29b0f896
AM		 5558 /* If i.rm.regmem == ESP (4)
5559 && i.rm.mode != (Register mode)
5560 && not 16 bit
5561 ==> need second modrm byte. */
5562 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5563 && i.rm.mode != 3
40fb9820 5564 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5565 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5566 | i.sib.index << 3
5567 | i.sib.scale << 6));
29b0f896 5568 }
3e73aa7c 5569
29b0f896 5570 if (i.disp_operands)
2bbd9c25 5571 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5572
29b0f896 5573 if (i.imm_operands)
2bbd9c25 5574 output_imm (insn_start_frag, insn_start_off);
29b0f896 5575 }
252b5132 5576
29b0f896
AM		 5577#ifdef DEBUG386
5578 if (flag_debug)
5579 {
7b81dfbb 5580 pi ("" /*line*/, &i);
29b0f896
AM		 5581 }
5582#endif /* DEBUG386 */
5583}
252b5132 5584
e205caa7
L		 5585/* Return the size of the displacement operand N. */
5586
5587static int
5588disp_size (unsigned int n)
5589{
5590 int size = 4;
40fb9820
L		 5591 if (i.types[n].bitfield.disp64)
5592 size = 8;
5593 else if (i.types[n].bitfield.disp8)
5594 size = 1;
5595 else if (i.types[n].bitfield.disp16)
5596 size = 2;
e205caa7
L		 5597 return size;
5598}
5599
5600/* Return the size of the immediate operand N. */
5601
5602static int
5603imm_size (unsigned int n)
5604{
5605 int size = 4;
40fb9820
L		 5606 if (i.types[n].bitfield.imm64)
5607 size = 8;
5608 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5609 size = 1;
5610 else if (i.types[n].bitfield.imm16)
5611 size = 2;
e205caa7
L		 5612 return size;
5613}
5614
29b0f896 5615static void
64e74474 5616output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5617{
5618 char *p;
5619 unsigned int n;
252b5132 5620
29b0f896
AM		 5621 for (n = 0; n < i.operands; n++)
5622 {
40fb9820 5623 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5624 {
5625 if (i.op[n].disps->X_op == O_constant)
5626 {
e205caa7 5627 int size = disp_size (n);
29b0f896 5628 offsetT val;
252b5132 5629
29b0f896
AM		 5630 val = offset_in_range (i.op[n].disps->X_add_number,
5631 size);
5632 p = frag_more (size);
5633 md_number_to_chars (p, val, size);
5634 }
5635 else
5636 {
f86103b7 5637 enum bfd_reloc_code_real reloc_type;
e205caa7 5638 int size = disp_size (n);
40fb9820 5639 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5640 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5641
e205caa7 5642 /* We can't have 8 bit displacement here. */
40fb9820 5643 assert (!i.types[n].bitfield.disp8);
e205caa7 5644
29b0f896
AM		 5645 /* The PC relative address is computed relative
5646 to the instruction boundary, so in case immediate
5647 fields follows, we need to adjust the value. */
5648 if (pcrel && i.imm_operands)
5649 {
29b0f896 5650 unsigned int n1;
e205caa7 5651 int sz = 0;
252b5132 5652
29b0f896 5653 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5654 if (operand_type_check (i.types[n1], imm))
252b5132 5655 {
e205caa7
L		 5656 /* Only one immediate is allowed for PC
5657 relative address. */
5658 assert (sz == 0);
5659 sz = imm_size (n1);
5660 i.op[n].disps->X_add_number -= sz;
252b5132 5661 }
29b0f896 5662 /* We should find the immediate. */
e205caa7 5663 assert (sz != 0);
29b0f896 5664 }
520dc8e8 5665
29b0f896 5666 p = frag_more (size);
2bbd9c25 5667 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5668 if (GOT_symbol
2bbd9c25 5669 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5670 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5671 || reloc_type == BFD_RELOC_X86_64_32S
5672 || (reloc_type == BFD_RELOC_64
5673 && object_64bit))
d6ab8113
JB		 5674 && (i.op[n].disps->X_op == O_symbol
5675 || (i.op[n].disps->X_op == O_add
5676 && ((symbol_get_value_expression
5677 (i.op[n].disps->X_op_symbol)->X_op)
5678 == O_subtract))))
5679 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5680 {
5681 offsetT add;
5682
5683 if (insn_start_frag == frag_now)
5684 add = (p - frag_now->fr_literal) - insn_start_off;
5685 else
5686 {
5687 fragS *fr;
5688
5689 add = insn_start_frag->fr_fix - insn_start_off;
5690 for (fr = insn_start_frag->fr_next;
5691 fr && fr != frag_now; fr = fr->fr_next)
5692 add += fr->fr_fix;
5693 add += p - frag_now->fr_literal;
5694 }
5695
4fa24527 5696 if (!object_64bit)
7b81dfbb
AJ		 5697 {
5698 reloc_type = BFD_RELOC_386_GOTPC;
5699 i.op[n].imms->X_add_number += add;
5700 }
5701 else if (reloc_type == BFD_RELOC_64)
5702 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5703 else
7b81dfbb
AJ		 5704 /* Don't do the adjustment for x86-64, as there
5705 the pcrel addressing is relative to the _next_
5706 insn, and that is taken care of in other code. */
d6ab8113 5707 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5708 }
062cd5e7 5709 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5710 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5711 }
5712 }
5713 }
5714}
252b5132 5715
29b0f896 5716static void
64e74474 5717output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5718{
5719 char *p;
5720 unsigned int n;
252b5132 5721
29b0f896
AM		 5722 for (n = 0; n < i.operands; n++)
5723 {
40fb9820 5724 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5725 {
5726 if (i.op[n].imms->X_op == O_constant)
5727 {
e205caa7 5728 int size = imm_size (n);
29b0f896 5729 offsetT val;
b4cac588 5730
29b0f896
AM		 5731 val = offset_in_range (i.op[n].imms->X_add_number,
5732 size);
5733 p = frag_more (size);
5734 md_number_to_chars (p, val, size);
5735 }
5736 else
5737 {
5738 /* Not absolute_section.
5739 Need a 32-bit fixup (don't support 8bit
5740 non-absolute imms). Try to support other
5741 sizes ... */
f86103b7 5742 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5743 int size = imm_size (n);
5744 int sign;
29b0f896 5745
40fb9820 5746 if (i.types[n].bitfield.imm32s
a7d61044 5747 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5748 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5749 sign = 1;
e205caa7
L		 5750 else
5751 sign = 0;
520dc8e8 5752
29b0f896
AM		 5753 p = frag_more (size);
5754 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5755
2bbd9c25
JJ		 5756 /* This is tough to explain. We end up with this one if we
5757 * have operands that look like
5758 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5759 * obtain the absolute address of the GOT, and it is strongly
5760 * preferable from a performance point of view to avoid using
5761 * a runtime relocation for this. The actual sequence of
5762 * instructions often look something like:
5763 *
5764 * call .L66
5765 * .L66:
5766 * popl %ebx
5767 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5768 *
5769 * The call and pop essentially return the absolute address
5770 * of the label .L66 and store it in %ebx. The linker itself
5771 * will ultimately change the first operand of the addl so
5772 * that %ebx points to the GOT, but to keep things simple, the
5773 * .o file must have this operand set so that it generates not
5774 * the absolute address of .L66, but the absolute address of
5775 * itself. This allows the linker itself simply treat a GOTPC
5776 * relocation as asking for a pcrel offset to the GOT to be
5777 * added in, and the addend of the relocation is stored in the
5778 * operand field for the instruction itself.
5779 *
5780 * Our job here is to fix the operand so that it would add
5781 * the correct offset so that %ebx would point to itself. The
5782 * thing that is tricky is that .-.L66 will point to the
5783 * beginning of the instruction, so we need to further modify
5784 * the operand so that it will point to itself. There are
5785 * other cases where you have something like:
5786 *
5787 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5788 *
5789 * and here no correction would be required. Internally in
5790 * the assembler we treat operands of this form as not being
5791 * pcrel since the '.' is explicitly mentioned, and I wonder
5792 * whether it would simplify matters to do it this way. Who
5793 * knows. In earlier versions of the PIC patches, the
5794 * pcrel_adjust field was used to store the correction, but
5795 * since the expression is not pcrel, I felt it would be
5796 * confusing to do it this way. */
5797
d6ab8113 5798 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5799 || reloc_type == BFD_RELOC_X86_64_32S
5800 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 5801 && GOT_symbol
5802 && GOT_symbol == i.op[n].imms->X_add_symbol
5803 && (i.op[n].imms->X_op == O_symbol
5804 || (i.op[n].imms->X_op == O_add
5805 && ((symbol_get_value_expression
5806 (i.op[n].imms->X_op_symbol)->X_op)
5807 == O_subtract))))
5808 {
2bbd9c25
JJ		 5809 offsetT add;
5810
5811 if (insn_start_frag == frag_now)
5812 add = (p - frag_now->fr_literal) - insn_start_off;
5813 else
5814 {
5815 fragS *fr;
5816
5817 add = insn_start_frag->fr_fix - insn_start_off;
5818 for (fr = insn_start_frag->fr_next;
5819 fr && fr != frag_now; fr = fr->fr_next)
5820 add += fr->fr_fix;
5821 add += p - frag_now->fr_literal;
5822 }
5823
4fa24527 5824 if (!object_64bit)
d6ab8113 5825 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 5826 else if (size == 4)
d6ab8113 5827 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 5828 else if (size == 8)
5829 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 5830 i.op[n].imms->X_add_number += add;
29b0f896 5831 }
29b0f896
AM		 5832 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5833 i.op[n].imms, 0, reloc_type);
5834 }
5835 }
5836 }
252b5132
RH		 5837}
5838\f
d182319b
JB		 5839/* x86_cons_fix_new is called via the expression parsing code when a
5840 reloc is needed. We use this hook to get the correct .got reloc. */
5841static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5842static int cons_sign = -1;
5843
5844void
e3bb37b5 5845x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 5846 expressionS *exp)
d182319b
JB		 5847{
5848 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5849
5850 got_reloc = NO_RELOC;
5851
5852#ifdef TE_PE
5853 if (exp->X_op == O_secrel)
5854 {
5855 exp->X_op = O_symbol;
5856 r = BFD_RELOC_32_SECREL;
5857 }
5858#endif
5859
5860 fix_new_exp (frag, off, len, exp, 0, r);
5861}
5862
718ddfc0
JB		 5863#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5864# define lex_got(reloc, adjust, types) NULL
5865#else
f3c180ae
AM		 5866/* Parse operands of the form
5867 <symbol>@GOTOFF+<nnn>
5868 and similar .plt or .got references.
5869
5870 If we find one, set up the correct relocation in RELOC and copy the
5871 input string, minus the `@GOTOFF' into a malloc'd buffer for
5872 parsing by the calling routine. Return this buffer, and if ADJUST
5873 is non-null set it to the length of the string we removed from the
5874 input line. Otherwise return NULL. */
5875static char *
3956db08 5876lex_got (enum bfd_reloc_code_real *reloc,
64e74474 5877 int *adjust,
40fb9820 5878 i386_operand_type *types)
f3c180ae 5879{
7b81dfbb
AJ		 5880 /* Some of the relocations depend on the size of what field is to
5881 be relocated. But in our callers i386_immediate and i386_displacement
5882 we don't yet know the operand size (this will be set by insn
5883 matching). Hence we record the word32 relocation here,
5884 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 5885 static const struct {
5886 const char *str;
4fa24527 5887 const enum bfd_reloc_code_real rel[2];
40fb9820 5888 const i386_operand_type types64;
f3c180ae 5889 } gotrel[] = {
4eed87de
AM		 5890 { "PLTOFF", { 0,
5891 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 5892 OPERAND_TYPE_IMM64 },
4eed87de
AM		 5893 { "PLT", { BFD_RELOC_386_PLT32,
5894 BFD_RELOC_X86_64_PLT32 },
40fb9820 5895 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5896 { "GOTPLT", { 0,
5897 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 5898 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5899 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5900 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 5901 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5902 { "GOTPCREL", { 0,
5903 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 5904 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5905 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5906 BFD_RELOC_X86_64_TLSGD },
40fb9820 5907 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5908 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5909 0 },
40fb9820 5910 OPERAND_TYPE_NONE },
4eed87de
AM		 5911 { "TLSLD", { 0,
5912 BFD_RELOC_X86_64_TLSLD },
40fb9820 5913 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5914 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5915 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 5916 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5917 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5918 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 5919 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5920 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5921 0 },
40fb9820 5922 OPERAND_TYPE_NONE },
4eed87de
AM		 5923 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5924 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 5925
5926 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5927 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5928 0 },
40fb9820 5929 OPERAND_TYPE_NONE },
4eed87de
AM		 5930 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5931 0 },
40fb9820 5932 OPERAND_TYPE_NONE },
4eed87de
AM		 5933 { "GOT", { BFD_RELOC_386_GOT32,
5934 BFD_RELOC_X86_64_GOT32 },
40fb9820 5935 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 5936 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5937 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 5938 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5939 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5940 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 5941 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 5942 };
5943 char *cp;
5944 unsigned int j;
5945
718ddfc0
JB		 5946 if (!IS_ELF)
5947 return NULL;
5948
f3c180ae 5949 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 5950 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 5951 return NULL;
5952
47465058 5953 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 5954 {
5955 int len;
5956
5957 len = strlen (gotrel[j].str);
28f81592 5958 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 5959 {
4fa24527 5960 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 5961 {
28f81592
AM		 5962 int first, second;
5963 char *tmpbuf, *past_reloc;
f3c180ae 5964
4fa24527 5965 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 5966 if (adjust)
5967 *adjust = len;
f3c180ae 5968
3956db08
JB		 5969 if (types)
5970 {
5971 if (flag_code != CODE_64BIT)
40fb9820
L		 5972 {
5973 types->bitfield.imm32 = 1;
5974 types->bitfield.disp32 = 1;
5975 }
3956db08
JB		 5976 else
5977 *types = gotrel[j].types64;
5978 }
5979
f3c180ae
AM		 5980 if (GOT_symbol == NULL)
5981 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5982
28f81592 5983 /* The length of the first part of our input line. */
f3c180ae 5984 first = cp - input_line_pointer;
28f81592
AM		 5985
5986 /* The second part goes from after the reloc token until
67c11a9b 5987 (and including) an end_of_line char or comma. */
28f81592 5988 past_reloc = cp + 1 + len;
67c11a9b
AM		 5989 cp = past_reloc;
5990 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5991 ++cp;
5992 second = cp + 1 - past_reloc;
28f81592
AM		 5993
5994 /* Allocate and copy string. The trailing NUL shouldn't
5995 be necessary, but be safe. */
5996 tmpbuf = xmalloc (first + second + 2);
f3c180ae 5997 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 5998 if (second != 0 && *past_reloc != ' ')
5999 /* Replace the relocation token with ' ', so that
6000 errors like foo@GOTOFF1 will be detected. */
6001 tmpbuf[first++] = ' ';
6002 memcpy (tmpbuf + first, past_reloc, second);
6003 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6004 return tmpbuf;
6005 }
6006
4fa24527
JB		 6007 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6008 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6009 return NULL;
6010 }
6011 }
6012
6013 /* Might be a symbol version string. Don't as_bad here. */
6014 return NULL;
6015}
6016
f3c180ae 6017void
e3bb37b5 6018x86_cons (expressionS *exp, int size)
f3c180ae 6019{
ee86248c
JB		 6020 intel_syntax = -intel_syntax;
6021
4fa24527 6022 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6023 {
6024 /* Handle @GOTOFF and the like in an expression. */
6025 char *save;
6026 char *gotfree_input_line;
6027 int adjust;
6028
6029 save = input_line_pointer;
3956db08 6030 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6031 if (gotfree_input_line)
6032 input_line_pointer = gotfree_input_line;
6033
6034 expression (exp);
6035
6036 if (gotfree_input_line)
6037 {
6038 /* expression () has merrily parsed up to the end of line,
6039 or a comma - in the wrong buffer. Transfer how far
6040 input_line_pointer has moved to the right buffer. */
6041 input_line_pointer = (save
6042 + (input_line_pointer - gotfree_input_line)
6043 + adjust);
6044 free (gotfree_input_line);
3992d3b7
AM		 6045 if (exp->X_op == O_constant
6046 || exp->X_op == O_absent
6047 || exp->X_op == O_illegal
6048 || exp->X_op == O_register
6049 || exp->X_op == O_big)
6050 {
6051 char c = *input_line_pointer;
6052 *input_line_pointer = 0;
6053 as_bad (_("missing or invalid expression `%s'"), save);
6054 *input_line_pointer = c;
6055 }
f3c180ae
AM		 6056 }
6057 }
6058 else
6059 expression (exp);
ee86248c
JB		 6060
6061 intel_syntax = -intel_syntax;
6062
6063 if (intel_syntax)
6064 i386_intel_simplify (exp);
f3c180ae
AM		 6065}
6066#endif
6067
d182319b 6068static void signed_cons (int size)
6482c264 6069{
d182319b
JB		 6070 if (flag_code == CODE_64BIT)
6071 cons_sign = 1;
6072 cons (size);
6073 cons_sign = -1;
6482c264
NC		 6074}
6075
d182319b 6076#ifdef TE_PE
6482c264
NC		 6077static void
6078pe_directive_secrel (dummy)
6079 int dummy ATTRIBUTE_UNUSED;
6080{
6081 expressionS exp;
6082
6083 do
6084 {
6085 expression (&exp);
6086 if (exp.X_op == O_symbol)
6087 exp.X_op = O_secrel;
6088
6089 emit_expr (&exp, 4);
6090 }
6091 while (*input_line_pointer++ == ',');
6092
6093 input_line_pointer--;
6094 demand_empty_rest_of_line ();
6095}
6482c264
NC		 6096#endif
6097
252b5132 6098static int
70e41ade 6099i386_immediate (char *imm_start)
252b5132
RH		 6100{
6101 char *save_input_line_pointer;
f3c180ae 6102 char *gotfree_input_line;
252b5132 6103 segT exp_seg = 0;
47926f60 6104 expressionS *exp;
40fb9820
L		 6105 i386_operand_type types;
6106
0dfbf9d7 6107 operand_type_set (&types, ~0);
252b5132
RH		 6108
6109 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6110 {
31b2323c
L		 6111 as_bad (_("at most %d immediate operands are allowed"),
6112 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6113 return 0;
6114 }
6115
6116 exp = &im_expressions[i.imm_operands++];
520dc8e8 6117 i.op[this_operand].imms = exp;
252b5132
RH		 6118
6119 if (is_space_char (*imm_start))
6120 ++imm_start;
6121
6122 save_input_line_pointer = input_line_pointer;
6123 input_line_pointer = imm_start;
6124
3956db08 6125 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6126 if (gotfree_input_line)
6127 input_line_pointer = gotfree_input_line;
252b5132
RH		 6128
6129 exp_seg = expression (exp);
6130
83183c0c 6131 SKIP_WHITESPACE ();
252b5132 6132 if (*input_line_pointer)
f3c180ae 6133 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6134
6135 input_line_pointer = save_input_line_pointer;
f3c180ae 6136 if (gotfree_input_line)
ee86248c
JB		 6137 {
6138 free (gotfree_input_line);
6139
6140 if (exp->X_op == O_constant || exp->X_op == O_register)
6141 exp->X_op = O_illegal;
6142 }
6143
6144 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6145}
252b5132 6146
ee86248c
JB		 6147static int
6148i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6149 i386_operand_type types, const char *imm_start)
6150{
6151 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6152 {
3992d3b7 6153 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 6154 imm_start);
3992d3b7 6155 return 0;
252b5132 6156 }
3e73aa7c 6157 else if (exp->X_op == O_constant)
252b5132 6158 {
47926f60 6159 /* Size it properly later. */
40fb9820 6160 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6161 /* If BFD64, sign extend val. */
4eed87de
AM		 6162 if (!use_rela_relocations
6163 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6164 exp->X_add_number
6165 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6166 }
4c63da97 6167#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6168 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6169 && exp_seg != absolute_section
47926f60 6170 && exp_seg != text_section
24eab124
AM		 6171 && exp_seg != data_section
6172 && exp_seg != bss_section
6173 && exp_seg != undefined_section
f86103b7 6174 && !bfd_is_com_section (exp_seg))
252b5132 6175 {
d0b47220 6176 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6177 return 0;
6178 }
6179#endif
bb8f5920
L		 6180 else if (!intel_syntax && exp->X_op == O_register)
6181 {
6182 as_bad (_("illegal immediate register operand %s"), imm_start);
6183 return 0;
6184 }
252b5132
RH		 6185 else
6186 {
6187 /* This is an address. The size of the address will be
24eab124 6188 determined later, depending on destination register,
3e73aa7c 6189 suffix, or the default for the section. */
40fb9820
L		 6190 i.types[this_operand].bitfield.imm8 = 1;
6191 i.types[this_operand].bitfield.imm16 = 1;
6192 i.types[this_operand].bitfield.imm32 = 1;
6193 i.types[this_operand].bitfield.imm32s = 1;
6194 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6195 i.types[this_operand] = operand_type_and (i.types[this_operand],
6196 types);
252b5132
RH		 6197 }
6198
6199 return 1;
6200}
6201
551c1ca1 6202static char *
e3bb37b5 6203i386_scale (char *scale)
252b5132 6204{
551c1ca1
AM		 6205 offsetT val;
6206 char *save = input_line_pointer;
252b5132 6207
551c1ca1
AM		 6208 input_line_pointer = scale;
6209 val = get_absolute_expression ();
6210
6211 switch (val)
252b5132 6212 {
551c1ca1 6213 case 1:
252b5132
RH		 6214 i.log2_scale_factor = 0;
6215 break;
551c1ca1 6216 case 2:
252b5132
RH		 6217 i.log2_scale_factor = 1;
6218 break;
551c1ca1 6219 case 4:
252b5132
RH		 6220 i.log2_scale_factor = 2;
6221 break;
551c1ca1 6222 case 8:
252b5132
RH		 6223 i.log2_scale_factor = 3;
6224 break;
6225 default:
a724f0f4
JB		 6226 {
6227 char sep = *input_line_pointer;
6228
6229 *input_line_pointer = '\0';
6230 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6231 scale);
6232 *input_line_pointer = sep;
6233 input_line_pointer = save;
6234 return NULL;
6235 }
252b5132 6236 }
29b0f896 6237 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6238 {
6239 as_warn (_("scale factor of %d without an index register"),
24eab124 6240 1 << i.log2_scale_factor);
252b5132 6241 i.log2_scale_factor = 0;
252b5132 6242 }
551c1ca1
AM		 6243 scale = input_line_pointer;
6244 input_line_pointer = save;
6245 return scale;
252b5132
RH		 6246}
6247
252b5132 6248static int
e3bb37b5 6249i386_displacement (char *disp_start, char *disp_end)
252b5132 6250{
29b0f896 6251 expressionS *exp;
252b5132
RH		 6252 segT exp_seg = 0;
6253 char *save_input_line_pointer;
f3c180ae 6254 char *gotfree_input_line;
40fb9820
L		 6255 int override;
6256 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6257 int ret;
252b5132 6258
31b2323c
L		 6259 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6260 {
6261 as_bad (_("at most %d displacement operands are allowed"),
6262 MAX_MEMORY_OPERANDS);
6263 return 0;
6264 }
6265
0dfbf9d7 6266 operand_type_set (&bigdisp, 0);
40fb9820
L		 6267 if ((i.types[this_operand].bitfield.jumpabsolute)
6268 || (!current_templates->start->opcode_modifier.jump
6269 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6270 {
40fb9820 6271 bigdisp.bitfield.disp32 = 1;
e05278af 6272 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6273 if (flag_code == CODE_64BIT)
6274 {
6275 if (!override)
6276 {
6277 bigdisp.bitfield.disp32s = 1;
6278 bigdisp.bitfield.disp64 = 1;
6279 }
6280 }
6281 else if ((flag_code == CODE_16BIT) ^ override)
6282 {
6283 bigdisp.bitfield.disp32 = 0;
6284 bigdisp.bitfield.disp16 = 1;
6285 }
e05278af
JB		 6286 }
6287 else
6288 {
6289 /* For PC-relative branches, the width of the displacement
6290 is dependent upon data size, not address size. */
e05278af 6291 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6292 if (flag_code == CODE_64BIT)
6293 {
6294 if (override || i.suffix == WORD_MNEM_SUFFIX)
6295 bigdisp.bitfield.disp16 = 1;
6296 else
6297 {
6298 bigdisp.bitfield.disp32 = 1;
6299 bigdisp.bitfield.disp32s = 1;
6300 }
6301 }
6302 else
e05278af
JB		 6303 {
6304 if (!override)
6305 override = (i.suffix == (flag_code != CODE_16BIT
6306 ? WORD_MNEM_SUFFIX
6307 : LONG_MNEM_SUFFIX));
40fb9820
L		 6308 bigdisp.bitfield.disp32 = 1;
6309 if ((flag_code == CODE_16BIT) ^ override)
6310 {
6311 bigdisp.bitfield.disp32 = 0;
6312 bigdisp.bitfield.disp16 = 1;
6313 }
e05278af 6314 }
e05278af 6315 }
c6fb90c8
L		 6316 i.types[this_operand] = operand_type_or (i.types[this_operand],
6317 bigdisp);
252b5132
RH		 6318
6319 exp = &disp_expressions[i.disp_operands];
520dc8e8 6320 i.op[this_operand].disps = exp;
252b5132
RH		 6321 i.disp_operands++;
6322 save_input_line_pointer = input_line_pointer;
6323 input_line_pointer = disp_start;
6324 END_STRING_AND_SAVE (disp_end);
6325
6326#ifndef GCC_ASM_O_HACK
6327#define GCC_ASM_O_HACK 0
6328#endif
6329#if GCC_ASM_O_HACK
6330 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6331 if (i.types[this_operand].bitfield.baseIndex
24eab124 6332 && displacement_string_end[-1] == '+')
252b5132
RH		 6333 {
6334 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6335 constraint within gcc asm statements.
6336 For instance:
6337
6338 #define _set_tssldt_desc(n,addr,limit,type) \
6339 __asm__ __volatile__ ( \
6340 "movw %w2,%0\n\t" \
6341 "movw %w1,2+%0\n\t" \
6342 "rorl $16,%1\n\t" \
6343 "movb %b1,4+%0\n\t" \
6344 "movb %4,5+%0\n\t" \
6345 "movb $0,6+%0\n\t" \
6346 "movb %h1,7+%0\n\t" \
6347 "rorl $16,%1" \
6348 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6349
6350 This works great except that the output assembler ends
6351 up looking a bit weird if it turns out that there is
6352 no offset. You end up producing code that looks like:
6353
6354 #APP
6355 movw $235,(%eax)
6356 movw %dx,2+(%eax)
6357 rorl $16,%edx
6358 movb %dl,4+(%eax)
6359 movb $137,5+(%eax)
6360 movb $0,6+(%eax)
6361 movb %dh,7+(%eax)
6362 rorl $16,%edx
6363 #NO_APP
6364
47926f60 6365 So here we provide the missing zero. */
24eab124
AM		 6366
6367 *displacement_string_end = '0';
252b5132
RH		 6368 }
6369#endif
3956db08 6370 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6371 if (gotfree_input_line)
6372 input_line_pointer = gotfree_input_line;
252b5132 6373
24eab124 6374 exp_seg = expression (exp);
252b5132 6375
636c26b0
AM		 6376 SKIP_WHITESPACE ();
6377 if (*input_line_pointer)
6378 as_bad (_("junk `%s' after expression"), input_line_pointer);
6379#if GCC_ASM_O_HACK
6380 RESTORE_END_STRING (disp_end + 1);
6381#endif
636c26b0 6382 input_line_pointer = save_input_line_pointer;
636c26b0 6383 if (gotfree_input_line)
ee86248c
JB		 6384 {
6385 free (gotfree_input_line);
6386
6387 if (exp->X_op == O_constant || exp->X_op == O_register)
6388 exp->X_op = O_illegal;
6389 }
6390
6391 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6392
6393 RESTORE_END_STRING (disp_end);
6394
6395 return ret;
6396}
6397
6398static int
6399i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6400 i386_operand_type types, const char *disp_start)
6401{
6402 i386_operand_type bigdisp;
6403 int ret = 1;
636c26b0 6404
24eab124
AM		 6405 /* We do this to make sure that the section symbol is in
6406 the symbol table. We will ultimately change the relocation
47926f60 6407 to be relative to the beginning of the section. */
1ae12ab7 6408 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6409 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6410 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6411 {
636c26b0 6412 if (exp->X_op != O_symbol)
3992d3b7 6413 goto inv_disp;
636c26b0 6414
e5cb08ac 6415 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6416 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6417 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6418 exp->X_op = O_subtract;
6419 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6420 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6421 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6422 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6423 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6424 else
29b0f896 6425 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6426 }
252b5132 6427
3992d3b7
AM		 6428 else if (exp->X_op == O_absent
6429 || exp->X_op == O_illegal
ee86248c 6430 || exp->X_op == O_big)
2daf4fd8 6431 {
3992d3b7
AM		 6432 inv_disp:
6433 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6434 disp_start);
3992d3b7 6435 ret = 0;
2daf4fd8
AM		 6436 }
6437
4c63da97 6438#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6439 else if (exp->X_op != O_constant
6440 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6441 && exp_seg != absolute_section
6442 && exp_seg != text_section
6443 && exp_seg != data_section
6444 && exp_seg != bss_section
6445 && exp_seg != undefined_section
6446 && !bfd_is_com_section (exp_seg))
24eab124 6447 {
d0b47220 6448 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6449 ret = 0;
24eab124 6450 }
252b5132 6451#endif
3956db08 6452
40fb9820
L		 6453 /* Check if this is a displacement only operand. */
6454 bigdisp = i.types[this_operand];
6455 bigdisp.bitfield.disp8 = 0;
6456 bigdisp.bitfield.disp16 = 0;
6457 bigdisp.bitfield.disp32 = 0;
6458 bigdisp.bitfield.disp32s = 0;
6459 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6460 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6461 i.types[this_operand] = operand_type_and (i.types[this_operand],
6462 types);
3956db08 6463
3992d3b7 6464 return ret;
252b5132
RH		 6465}
6466
eecb386c 6467/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6468 Return 1 on success, 0 on a failure. */
6469
252b5132 6470static int
e3bb37b5 6471i386_index_check (const char *operand_string)
252b5132 6472{
3e73aa7c 6473 int ok;
fc0763e6 6474 const char *kind = "base/index";
24eab124 6475#if INFER_ADDR_PREFIX
eecb386c
AM		 6476 int fudged = 0;
6477
24eab124
AM		 6478 tryprefix:
6479#endif
3e73aa7c 6480 ok = 1;
fc0763e6
JB		 6481 if (current_templates->start->opcode_modifier.isstring
6482 && !current_templates->start->opcode_modifier.immext
6483 && (current_templates->end[-1].opcode_modifier.isstring
6484 || i.mem_operands))
6485 {
6486 /* Memory operands of string insns are special in that they only allow
6487 a single register (rDI, rSI, or rBX) as their memory address. */
6488 unsigned int expected;
6489
6490 kind = "string address";
6491
6492 if (current_templates->start->opcode_modifier.w)
6493 {
6494 i386_operand_type type = current_templates->end[-1].operand_types[0];
6495
6496 if (!type.bitfield.baseindex
6497 || ((!i.mem_operands != !intel_syntax)
6498 && current_templates->end[-1].operand_types[1]
6499 .bitfield.baseindex))
6500 type = current_templates->end[-1].operand_types[1];
6501 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6502 }
6503 else
6504 expected = 3 /* rBX */;
6505
6506 if (!i.base_reg || i.index_reg
6507 || operand_type_check (i.types[this_operand], disp))
6508 ok = -1;
6509 else if (!(flag_code == CODE_64BIT
6510 ? i.prefix[ADDR_PREFIX]
6511 ? i.base_reg->reg_type.bitfield.reg32
6512 : i.base_reg->reg_type.bitfield.reg64
6513 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6514 ? i.base_reg->reg_type.bitfield.reg32
6515 : i.base_reg->reg_type.bitfield.reg16))
6516 ok = 0;
6517 else if (i.base_reg->reg_num != expected)
6518 ok = -1;
6519
6520 if (ok < 0)
6521 {
6522 unsigned int j;
6523
6524 for (j = 0; j < i386_regtab_size; ++j)
6525 if ((flag_code == CODE_64BIT
6526 ? i.prefix[ADDR_PREFIX]
6527 ? i386_regtab[j].reg_type.bitfield.reg32
6528 : i386_regtab[j].reg_type.bitfield.reg64
6529 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6530 ? i386_regtab[j].reg_type.bitfield.reg32
6531 : i386_regtab[j].reg_type.bitfield.reg16)
6532 && i386_regtab[j].reg_num == expected)
6533 break;
6534 assert (j < i386_regtab_size);
6535 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6536 operand_string,
6537 intel_syntax ? '[' : '(',
6538 register_prefix,
6539 i386_regtab[j].reg_name,
6540 intel_syntax ? ']' : ')');
6541 ok = 1;
6542 }
6543 }
6544 else if (flag_code == CODE_64BIT)
64e74474 6545 {
64e74474 6546 if ((i.base_reg
40fb9820
L		 6547 && ((i.prefix[ADDR_PREFIX] == 0
6548 && !i.base_reg->reg_type.bitfield.reg64)
6549 || (i.prefix[ADDR_PREFIX]
6550 && !i.base_reg->reg_type.bitfield.reg32))
6551 && (i.index_reg
9a04903e
JB		 6552 || i.base_reg->reg_num !=
6553 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6554 || (i.index_reg
40fb9820
L		 6555 && (!i.index_reg->reg_type.bitfield.baseindex
6556 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6557 && i.index_reg->reg_num != RegRiz
6558 && !i.index_reg->reg_type.bitfield.reg64
6559 )
40fb9820 6560 || (i.prefix[ADDR_PREFIX]
db51cc60 6561 && i.index_reg->reg_num != RegEiz
40fb9820 6562 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6563 ok = 0;
3e73aa7c
JH		 6564 }
6565 else
6566 {
6567 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6568 {
6569 /* 16bit checks. */
6570 if ((i.base_reg
40fb9820
L		 6571 && (!i.base_reg->reg_type.bitfield.reg16
6572 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6573 || (i.index_reg
40fb9820
L		 6574 && (!i.index_reg->reg_type.bitfield.reg16
6575 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6576 || !(i.base_reg
6577 && i.base_reg->reg_num < 6
6578 && i.index_reg->reg_num >= 6
6579 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6580 ok = 0;
6581 }
6582 else
e5cb08ac 6583 {
3e73aa7c
JH		 6584 /* 32bit checks. */
6585 if ((i.base_reg
40fb9820 6586 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6587 || (i.index_reg
db51cc60
L		 6588 && ((!i.index_reg->reg_type.bitfield.reg32
6589 && i.index_reg->reg_num != RegEiz)
40fb9820 6590 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6591 ok = 0;
3e73aa7c
JH		 6592 }
6593 }
6594 if (!ok)
24eab124
AM		 6595 {
6596#if INFER_ADDR_PREFIX
fc0763e6 6597 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 6598 {
6599 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6600 i.prefixes += 1;
b23bac36
AM		 6601 /* Change the size of any displacement too. At most one of
6602 Disp16 or Disp32 is set.
6603 FIXME. There doesn't seem to be any real need for separate
6604 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6605 Removing them would probably clean up the code quite a lot. */
4eed87de 6606 if (flag_code != CODE_64BIT
40fb9820
L		 6607 && (i.types[this_operand].bitfield.disp16
6608 || i.types[this_operand].bitfield.disp32))
6609 i.types[this_operand]
c6fb90c8 6610 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6611 fudged = 1;
24eab124
AM		 6612 goto tryprefix;
6613 }
eecb386c 6614 if (fudged)
fc0763e6
JB		 6615 as_bad (_("`%s' is not a valid %s expression"),
6616 operand_string,
6617 kind);
eecb386c 6618 else
c388dee8 6619#endif
fc0763e6 6620 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 6621 operand_string,
fc0763e6
JB		 6622 flag_code_names[i.prefix[ADDR_PREFIX]
6623 ? flag_code == CODE_32BIT
6624 ? CODE_16BIT
6625 : CODE_32BIT
6626 : flag_code],
6627 kind);
24eab124 6628 }
20f0a1fc 6629 return ok;
24eab124 6630}
252b5132 6631
fc0763e6 6632/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 6633 on error. */
252b5132 6634
252b5132 6635static int
a7619375 6636i386_att_operand (char *operand_string)
252b5132 6637{
af6bdddf
AM		 6638 const reg_entry *r;
6639 char *end_op;
24eab124 6640 char *op_string = operand_string;
252b5132 6641
24eab124 6642 if (is_space_char (*op_string))
252b5132
RH		 6643 ++op_string;
6644
24eab124 6645 /* We check for an absolute prefix (differentiating,
47926f60 6646 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6647 if (*op_string == ABSOLUTE_PREFIX)
6648 {
6649 ++op_string;
6650 if (is_space_char (*op_string))
6651 ++op_string;
40fb9820 6652 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6653 }
252b5132 6654
47926f60 6655 /* Check if operand is a register. */
4d1bb795 6656 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6657 {
40fb9820
L		 6658 i386_operand_type temp;
6659
24eab124
AM		 6660 /* Check for a segment override by searching for ':' after a
6661 segment register. */
6662 op_string = end_op;
6663 if (is_space_char (*op_string))
6664 ++op_string;
40fb9820
L		 6665 if (*op_string == ':'
6666 && (r->reg_type.bitfield.sreg2
6667 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6668 {
6669 switch (r->reg_num)
6670 {
6671 case 0:
6672 i.seg[i.mem_operands] = &es;
6673 break;
6674 case 1:
6675 i.seg[i.mem_operands] = &cs;
6676 break;
6677 case 2:
6678 i.seg[i.mem_operands] = &ss;
6679 break;
6680 case 3:
6681 i.seg[i.mem_operands] = &ds;
6682 break;
6683 case 4:
6684 i.seg[i.mem_operands] = &fs;
6685 break;
6686 case 5:
6687 i.seg[i.mem_operands] = &gs;
6688 break;
6689 }
252b5132 6690
24eab124 6691 /* Skip the ':' and whitespace. */
252b5132
RH		 6692 ++op_string;
6693 if (is_space_char (*op_string))
24eab124 6694 ++op_string;
252b5132 6695
24eab124
AM		 6696 if (!is_digit_char (*op_string)
6697 && !is_identifier_char (*op_string)
6698 && *op_string != '('
6699 && *op_string != ABSOLUTE_PREFIX)
6700 {
6701 as_bad (_("bad memory operand `%s'"), op_string);
6702 return 0;
6703 }
47926f60 6704 /* Handle case of %es:*foo. */
24eab124
AM		 6705 if (*op_string == ABSOLUTE_PREFIX)
6706 {
6707 ++op_string;
6708 if (is_space_char (*op_string))
6709 ++op_string;
40fb9820 6710 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6711 }
6712 goto do_memory_reference;
6713 }
6714 if (*op_string)
6715 {
d0b47220 6716 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6717 return 0;
6718 }
40fb9820
L		 6719 temp = r->reg_type;
6720 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6721 i.types[this_operand] = operand_type_or (i.types[this_operand],
6722 temp);
7d5e4556 6723 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 6724 i.op[this_operand].regs = r;
24eab124
AM		 6725 i.reg_operands++;
6726 }
af6bdddf
AM		 6727 else if (*op_string == REGISTER_PREFIX)
6728 {
6729 as_bad (_("bad register name `%s'"), op_string);
6730 return 0;
6731 }
24eab124 6732 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6733 {
24eab124 6734 ++op_string;
40fb9820 6735 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6736 {
d0b47220 6737 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6738 return 0;
6739 }
6740 if (!i386_immediate (op_string))
6741 return 0;
6742 }
6743 else if (is_digit_char (*op_string)
6744 || is_identifier_char (*op_string)
e5cb08ac 6745 || *op_string == '(')
24eab124 6746 {
47926f60 6747 /* This is a memory reference of some sort. */
af6bdddf 6748 char *base_string;
252b5132 6749
47926f60 6750 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 6751 char *displacement_string_start;
6752 char *displacement_string_end;
252b5132 6753
24eab124 6754 do_memory_reference:
24eab124 6755 if ((i.mem_operands == 1
40fb9820 6756 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 6757 || i.mem_operands == 2)
6758 {
6759 as_bad (_("too many memory references for `%s'"),
6760 current_templates->start->name);
6761 return 0;
6762 }
252b5132 6763
24eab124
AM		 6764 /* Check for base index form. We detect the base index form by
6765 looking for an ')' at the end of the operand, searching
6766 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6767 after the '('. */
af6bdddf 6768 base_string = op_string + strlen (op_string);
c3332e24 6769
af6bdddf
AM		 6770 --base_string;
6771 if (is_space_char (*base_string))
6772 --base_string;
252b5132 6773
47926f60 6774 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 6775 displacement_string_start = op_string;
6776 displacement_string_end = base_string + 1;
252b5132 6777
24eab124
AM		 6778 if (*base_string == ')')
6779 {
af6bdddf 6780 char *temp_string;
24eab124
AM		 6781 unsigned int parens_balanced = 1;
6782 /* We've already checked that the number of left & right ()'s are
47926f60 6783 equal, so this loop will not be infinite. */
24eab124
AM		 6784 do
6785 {
6786 base_string--;
6787 if (*base_string == ')')
6788 parens_balanced++;
6789 if (*base_string == '(')
6790 parens_balanced--;
6791 }
6792 while (parens_balanced);
c3332e24 6793
af6bdddf 6794 temp_string = base_string;
c3332e24 6795
24eab124 6796 /* Skip past '(' and whitespace. */
252b5132
RH		 6797 ++base_string;
6798 if (is_space_char (*base_string))
24eab124 6799 ++base_string;
252b5132 6800
af6bdddf 6801 if (*base_string == ','
4eed87de
AM		 6802 || ((i.base_reg = parse_register (base_string, &end_op))
6803 != NULL))
252b5132 6804 {
af6bdddf 6805 displacement_string_end = temp_string;
252b5132 6806
40fb9820 6807 i.types[this_operand].bitfield.baseindex = 1;
252b5132 6808
af6bdddf 6809 if (i.base_reg)
24eab124 6810 {
24eab124
AM		 6811 base_string = end_op;
6812 if (is_space_char (*base_string))
6813 ++base_string;
af6bdddf
AM		 6814 }
6815
6816 /* There may be an index reg or scale factor here. */
6817 if (*base_string == ',')
6818 {
6819 ++base_string;
6820 if (is_space_char (*base_string))
6821 ++base_string;
6822
4eed87de
AM		 6823 if ((i.index_reg = parse_register (base_string, &end_op))
6824 != NULL)
24eab124 6825 {
af6bdddf 6826 base_string = end_op;
24eab124
AM		 6827 if (is_space_char (*base_string))
6828 ++base_string;
af6bdddf
AM		 6829 if (*base_string == ',')
6830 {
6831 ++base_string;
6832 if (is_space_char (*base_string))
6833 ++base_string;
6834 }
e5cb08ac 6835 else if (*base_string != ')')
af6bdddf 6836 {
4eed87de
AM		 6837 as_bad (_("expecting `,' or `)' "
6838 "after index register in `%s'"),
af6bdddf
AM		 6839 operand_string);
6840 return 0;
6841 }
24eab124 6842 }
af6bdddf 6843 else if (*base_string == REGISTER_PREFIX)
24eab124 6844 {
af6bdddf 6845 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 6846 return 0;
6847 }
252b5132 6848
47926f60 6849 /* Check for scale factor. */
551c1ca1 6850 if (*base_string != ')')
af6bdddf 6851 {
551c1ca1
AM		 6852 char *end_scale = i386_scale (base_string);
6853
6854 if (!end_scale)
af6bdddf 6855 return 0;
24eab124 6856
551c1ca1 6857 base_string = end_scale;
af6bdddf
AM		 6858 if (is_space_char (*base_string))
6859 ++base_string;
6860 if (*base_string != ')')
6861 {
4eed87de
AM		 6862 as_bad (_("expecting `)' "
6863 "after scale factor in `%s'"),
af6bdddf
AM		 6864 operand_string);
6865 return 0;
6866 }
6867 }
6868 else if (!i.index_reg)
24eab124 6869 {
4eed87de
AM		 6870 as_bad (_("expecting index register or scale factor "
6871 "after `,'; got '%c'"),
af6bdddf 6872 *base_string);
24eab124
AM		 6873 return 0;
6874 }
6875 }
af6bdddf 6876 else if (*base_string != ')')
24eab124 6877 {
4eed87de
AM		 6878 as_bad (_("expecting `,' or `)' "
6879 "after base register in `%s'"),
af6bdddf 6880 operand_string);
24eab124
AM		 6881 return 0;
6882 }
c3332e24 6883 }
af6bdddf 6884 else if (*base_string == REGISTER_PREFIX)
c3332e24 6885 {
af6bdddf 6886 as_bad (_("bad register name `%s'"), base_string);
24eab124 6887 return 0;
c3332e24 6888 }
24eab124
AM		 6889 }
6890
6891 /* If there's an expression beginning the operand, parse it,
6892 assuming displacement_string_start and
6893 displacement_string_end are meaningful. */
6894 if (displacement_string_start != displacement_string_end)
6895 {
6896 if (!i386_displacement (displacement_string_start,
6897 displacement_string_end))
6898 return 0;
6899 }
6900
6901 /* Special case for (%dx) while doing input/output op. */
6902 if (i.base_reg
0dfbf9d7
L		 6903 && operand_type_equal (&i.base_reg->reg_type,
6904 &reg16_inoutportreg)
24eab124
AM		 6905 && i.index_reg == 0
6906 && i.log2_scale_factor == 0
6907 && i.seg[i.mem_operands] == 0
40fb9820 6908 && !operand_type_check (i.types[this_operand], disp))
24eab124 6909 {
65da13b5 6910 i.types[this_operand] = inoutportreg;
24eab124
AM		 6911 return 1;
6912 }
6913
eecb386c
AM		 6914 if (i386_index_check (operand_string) == 0)
6915 return 0;
5c07affc 6916 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 6917 i.mem_operands++;
6918 }
6919 else
ce8a8b2f
AM		 6920 {
6921 /* It's not a memory operand; argh! */
24eab124
AM		 6922 as_bad (_("invalid char %s beginning operand %d `%s'"),
6923 output_invalid (*op_string),
6924 this_operand + 1,
6925 op_string);
6926 return 0;
6927 }
47926f60 6928 return 1; /* Normal return. */
252b5132
RH		 6929}
6930\f
ee7fcc42
AM		 6931/* md_estimate_size_before_relax()
6932
6933 Called just before relax() for rs_machine_dependent frags. The x86
6934 assembler uses these frags to handle variable size jump
6935 instructions.
6936
6937 Any symbol that is now undefined will not become defined.
6938 Return the correct fr_subtype in the frag.
6939 Return the initial "guess for variable size of frag" to caller.
6940 The guess is actually the growth beyond the fixed part. Whatever
6941 we do to grow the fixed or variable part contributes to our
6942 returned value. */
6943
252b5132
RH		 6944int
6945md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 6946 fragS *fragP;
6947 segT segment;
252b5132 6948{
252b5132 6949 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 6950 check for un-relaxable symbols. On an ELF system, we can't relax
6951 an externally visible symbol, because it may be overridden by a
6952 shared library. */
6953 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 6954#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6955 || (IS_ELF
31312f95
AM		 6956 && (S_IS_EXTERNAL (fragP->fr_symbol)
6957 || S_IS_WEAK (fragP->fr_symbol)))
fbeb56a4
DK		 6958#endif
6959#if defined (OBJ_COFF) && defined (TE_PE)
6960 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
6961 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 6962#endif
6963 )
252b5132 6964 {
b98ef147
AM		 6965 /* Symbol is undefined in this segment, or we need to keep a
6966 reloc so that weak symbols can be overridden. */
6967 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 6968 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 6969 unsigned char *opcode;
6970 int old_fr_fix;
f6af82bd 6971
ee7fcc42
AM		 6972 if (fragP->fr_var != NO_RELOC)
6973 reloc_type = fragP->fr_var;
b98ef147 6974 else if (size == 2)
f6af82bd
AM		 6975 reloc_type = BFD_RELOC_16_PCREL;
6976 else
6977 reloc_type = BFD_RELOC_32_PCREL;
252b5132 6978
ee7fcc42
AM		 6979 old_fr_fix = fragP->fr_fix;
6980 opcode = (unsigned char *) fragP->fr_opcode;
6981
fddf5b5b 6982 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 6983 {
fddf5b5b
AM		 6984 case UNCOND_JUMP:
6985 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 6986 opcode[0] = 0xe9;
252b5132 6987 fragP->fr_fix += size;
062cd5e7
AS		 6988 fix_new (fragP, old_fr_fix, size,
6989 fragP->fr_symbol,
6990 fragP->fr_offset, 1,
6991 reloc_type);
252b5132
RH		 6992 break;
6993
fddf5b5b 6994 case COND_JUMP86:
412167cb
AM		 6995 if (size == 2
6996 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 6997 {
6998 /* Negate the condition, and branch past an
6999 unconditional jump. */
7000 opcode[0] ^= 1;
7001 opcode[1] = 3;
7002 /* Insert an unconditional jump. */
7003 opcode[2] = 0xe9;
7004 /* We added two extra opcode bytes, and have a two byte
7005 offset. */
7006 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7007 fix_new (fragP, old_fr_fix + 2, 2,
7008 fragP->fr_symbol,
7009 fragP->fr_offset, 1,
7010 reloc_type);
fddf5b5b
AM		 7011 break;
7012 }
7013 /* Fall through. */
7014
7015 case COND_JUMP:
412167cb
AM		 7016 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7017 {
3e02c1cc
AM		 7018 fixS *fixP;
7019
412167cb 7020 fragP->fr_fix += 1;
3e02c1cc
AM		 7021 fixP = fix_new (fragP, old_fr_fix, 1,
7022 fragP->fr_symbol,
7023 fragP->fr_offset, 1,
7024 BFD_RELOC_8_PCREL);
7025 fixP->fx_signed = 1;
412167cb
AM		 7026 break;
7027 }
93c2a809 7028
24eab124 7029 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7030 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7031 opcode[1] = opcode[0] + 0x10;
f6af82bd 7032 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7033 /* We've added an opcode byte. */
7034 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7035 fix_new (fragP, old_fr_fix + 1, size,
7036 fragP->fr_symbol,
7037 fragP->fr_offset, 1,
7038 reloc_type);
252b5132 7039 break;
fddf5b5b
AM		 7040
7041 default:
7042 BAD_CASE (fragP->fr_subtype);
7043 break;
252b5132
RH		 7044 }
7045 frag_wane (fragP);
ee7fcc42 7046 return fragP->fr_fix - old_fr_fix;
252b5132 7047 }
93c2a809 7048
93c2a809
AM		 7049 /* Guess size depending on current relax state. Initially the relax
7050 state will correspond to a short jump and we return 1, because
7051 the variable part of the frag (the branch offset) is one byte
7052 long. However, we can relax a section more than once and in that
7053 case we must either set fr_subtype back to the unrelaxed state,
7054 or return the value for the appropriate branch. */
7055 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7056}
7057
47926f60
KH		 7058/* Called after relax() is finished.
7059
7060 In: Address of frag.
7061 fr_type == rs_machine_dependent.
7062 fr_subtype is what the address relaxed to.
7063
7064 Out: Any fixSs and constants are set up.
7065 Caller will turn frag into a ".space 0". */
7066
252b5132
RH		 7067void
7068md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7069 bfd *abfd ATTRIBUTE_UNUSED;
7070 segT sec ATTRIBUTE_UNUSED;
29b0f896 7071 fragS *fragP;
252b5132 7072{
29b0f896 7073 unsigned char *opcode;
252b5132 7074 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7075 offsetT target_address;
7076 offsetT opcode_address;
252b5132 7077 unsigned int extension = 0;
847f7ad4 7078 offsetT displacement_from_opcode_start;
252b5132
RH		 7079
7080 opcode = (unsigned char *) fragP->fr_opcode;
7081
47926f60 7082 /* Address we want to reach in file space. */
252b5132 7083 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7084
47926f60 7085 /* Address opcode resides at in file space. */
252b5132
RH		 7086 opcode_address = fragP->fr_address + fragP->fr_fix;
7087
47926f60 7088 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7089 displacement_from_opcode_start = target_address - opcode_address;
7090
fddf5b5b 7091 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7092 {
47926f60
KH		 7093 /* Don't have to change opcode. */
7094 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7095 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7096 }
7097 else
7098 {
7099 if (no_cond_jump_promotion
7100 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7101 as_warn_where (fragP->fr_file, fragP->fr_line,
7102 _("long jump required"));
252b5132 7103
fddf5b5b
AM		 7104 switch (fragP->fr_subtype)
7105 {
7106 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7107 extension = 4; /* 1 opcode + 4 displacement */
7108 opcode[0] = 0xe9;
7109 where_to_put_displacement = &opcode[1];
7110 break;
252b5132 7111
fddf5b5b
AM		 7112 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7113 extension = 2; /* 1 opcode + 2 displacement */
7114 opcode[0] = 0xe9;
7115 where_to_put_displacement = &opcode[1];
7116 break;
252b5132 7117
fddf5b5b
AM		 7118 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7119 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7120 extension = 5; /* 2 opcode + 4 displacement */
7121 opcode[1] = opcode[0] + 0x10;
7122 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7123 where_to_put_displacement = &opcode[2];
7124 break;
252b5132 7125
fddf5b5b
AM		 7126 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7127 extension = 3; /* 2 opcode + 2 displacement */
7128 opcode[1] = opcode[0] + 0x10;
7129 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7130 where_to_put_displacement = &opcode[2];
7131 break;
252b5132 7132
fddf5b5b
AM		 7133 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7134 extension = 4;
7135 opcode[0] ^= 1;
7136 opcode[1] = 3;
7137 opcode[2] = 0xe9;
7138 where_to_put_displacement = &opcode[3];
7139 break;
7140
7141 default:
7142 BAD_CASE (fragP->fr_subtype);
7143 break;
7144 }
252b5132 7145 }
fddf5b5b 7146
7b81dfbb
AJ		 7147 /* If size if less then four we are sure that the operand fits,
7148 but if it's 4, then it could be that the displacement is larger
7149 then -/+ 2GB. */
7150 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7151 && object_64bit
7152 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7153 + ((addressT) 1 << 31))
7154 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7155 {
7156 as_bad_where (fragP->fr_file, fragP->fr_line,
7157 _("jump target out of range"));
7158 /* Make us emit 0. */
7159 displacement_from_opcode_start = extension;
7160 }
47926f60 7161 /* Now put displacement after opcode. */
252b5132
RH		 7162 md_number_to_chars ((char *) where_to_put_displacement,
7163 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7164 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7165 fragP->fr_fix += extension;
7166}
7167\f
252b5132
RH		 7168/* Apply a fixup (fixS) to segment data, once it has been determined
7169 by our caller that we have all the info we need to fix it up.
7170
7171 On the 386, immediates, displacements, and data pointers are all in
7172 the same (little-endian) format, so we don't need to care about which
7173 we are handling. */
7174
94f592af 7175void
55cf6793 7176md_apply_fix (fixP, valP, seg)
47926f60
KH		 7177 /* The fix we're to put in. */
7178 fixS *fixP;
47926f60 7179 /* Pointer to the value of the bits. */
c6682705 7180 valueT *valP;
47926f60
KH		 7181 /* Segment fix is from. */
7182 segT seg ATTRIBUTE_UNUSED;
252b5132 7183{
94f592af 7184 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7185 valueT value = *valP;
252b5132 7186
f86103b7 7187#if !defined (TE_Mach)
93382f6d
AM		 7188 if (fixP->fx_pcrel)
7189 {
7190 switch (fixP->fx_r_type)
7191 {
5865bb77
ILT		 7192 default:
7193 break;
7194
d6ab8113
JB		 7195 case BFD_RELOC_64:
7196 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7197 break;
93382f6d 7198 case BFD_RELOC_32:
ae8887b5 7199 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7200 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7201 break;
7202 case BFD_RELOC_16:
7203 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7204 break;
7205 case BFD_RELOC_8:
7206 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7207 break;
7208 }
7209 }
252b5132 7210
a161fe53 7211 if (fixP->fx_addsy != NULL
31312f95 7212 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7213 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7214 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7215 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7216 && !use_rela_relocations)
252b5132 7217 {
31312f95
AM		 7218 /* This is a hack. There should be a better way to handle this.
7219 This covers for the fact that bfd_install_relocation will
7220 subtract the current location (for partial_inplace, PC relative
7221 relocations); see more below. */
252b5132 7222#ifndef OBJ_AOUT
718ddfc0 7223 if (IS_ELF
252b5132
RH		 7224#ifdef TE_PE
7225 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7226#endif
7227 )
7228 value += fixP->fx_where + fixP->fx_frag->fr_address;
7229#endif
7230#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7231 if (IS_ELF)
252b5132 7232 {
6539b54b 7233 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7234
6539b54b 7235 if ((sym_seg == seg
2f66722d 7236 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7237 && sym_seg != absolute_section))
c25bc9fc 7238 && !TC_FORCE_RELOCATION (fixP))
2f66722d
AM		 7239 {
7240 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7241 bfd_install_relocation subtracts them out again. I think
7242 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7243 it. FIXME. */
7244 value += fixP->fx_where + fixP->fx_frag->fr_address;
7245 }
252b5132
RH		 7246 }
7247#endif
7248#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7249 /* For some reason, the PE format does not store a
7250 section address offset for a PC relative symbol. */
7251 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7252 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7253 value += md_pcrel_from (fixP);
7254#endif
7255 }
fbeb56a4
DK		 7256#if defined (OBJ_COFF) && defined (TE_PE)
7257 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7258 {
7259 value -= S_GET_VALUE (fixP->fx_addsy);
7260 }
7261#endif
252b5132
RH		 7262
7263 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7264 and we must not disappoint it. */
252b5132 7265#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7266 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7267 switch (fixP->fx_r_type)
7268 {
7269 case BFD_RELOC_386_PLT32:
3e73aa7c 7270 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7271 /* Make the jump instruction point to the address of the operand. At
7272 runtime we merely add the offset to the actual PLT entry. */
7273 value = -4;
7274 break;
31312f95 7275
13ae64f3
JJ		 7276 case BFD_RELOC_386_TLS_GD:
7277 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7278 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7279 case BFD_RELOC_386_TLS_IE:
7280 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7281 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7282 case BFD_RELOC_X86_64_TLSGD:
7283 case BFD_RELOC_X86_64_TLSLD:
7284 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7285 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7286 value = 0; /* Fully resolved at runtime. No addend. */
7287 /* Fallthrough */
7288 case BFD_RELOC_386_TLS_LE:
7289 case BFD_RELOC_386_TLS_LDO_32:
7290 case BFD_RELOC_386_TLS_LE_32:
7291 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7292 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7293 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7294 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7295 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7296 break;
7297
67a4f2b7
AO		 7298 case BFD_RELOC_386_TLS_DESC_CALL:
7299 case BFD_RELOC_X86_64_TLSDESC_CALL:
7300 value = 0; /* Fully resolved at runtime. No addend. */
7301 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7302 fixP->fx_done = 0;
7303 return;
7304
00f7efb6
JJ		 7305 case BFD_RELOC_386_GOT32:
7306 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7307 value = 0; /* Fully resolved at runtime. No addend. */
7308 break;
47926f60
KH		 7309
7310 case BFD_RELOC_VTABLE_INHERIT:
7311 case BFD_RELOC_VTABLE_ENTRY:
7312 fixP->fx_done = 0;
94f592af 7313 return;
47926f60
KH		 7314
7315 default:
7316 break;
7317 }
7318#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7319 *valP = value;
f86103b7 7320#endif /* !defined (TE_Mach) */
3e73aa7c 7321
3e73aa7c 7322 /* Are we finished with this relocation now? */
c6682705 7323 if (fixP->fx_addsy == NULL)
3e73aa7c 7324 fixP->fx_done = 1;
fbeb56a4
DK		 7325#if defined (OBJ_COFF) && defined (TE_PE)
7326 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7327 {
7328 fixP->fx_done = 0;
7329 /* Remember value for tc_gen_reloc. */
7330 fixP->fx_addnumber = value;
7331 /* Clear out the frag for now. */
7332 value = 0;
7333 }
7334#endif
3e73aa7c
JH		 7335 else if (use_rela_relocations)
7336 {
7337 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7338 /* Remember value for tc_gen_reloc. */
7339 fixP->fx_addnumber = value;
3e73aa7c
JH		 7340 value = 0;
7341 }
f86103b7 7342
94f592af 7343 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7344}
252b5132 7345\f
252b5132 7346char *
499ac353 7347md_atof (int type, char *litP, int *sizeP)
252b5132 7348{
499ac353
NC		 7349 /* This outputs the LITTLENUMs in REVERSE order;
7350 in accord with the bigendian 386. */
7351 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7352}
7353\f
2d545b82 7354static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7355
252b5132 7356static char *
e3bb37b5 7357output_invalid (int c)
252b5132 7358{
3882b010 7359 if (ISPRINT (c))
f9f21a03
L		 7360 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7361 "'%c'", c);
252b5132 7362 else
f9f21a03 7363 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7364 "(0x%x)", (unsigned char) c);
252b5132
RH		 7365 return output_invalid_buf;
7366}
7367
af6bdddf 7368/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7369
7370static const reg_entry *
4d1bb795 7371parse_real_register (char *reg_string, char **end_op)
252b5132 7372{
af6bdddf
AM		 7373 char *s = reg_string;
7374 char *p;
252b5132
RH		 7375 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7376 const reg_entry *r;
7377
7378 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7379 if (*s == REGISTER_PREFIX)
7380 ++s;
7381
7382 if (is_space_char (*s))
7383 ++s;
7384
7385 p = reg_name_given;
af6bdddf 7386 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7387 {
7388 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7389 return (const reg_entry *) NULL;
7390 s++;
252b5132
RH		 7391 }
7392
6588847e
DN		 7393 /* For naked regs, make sure that we are not dealing with an identifier.
7394 This prevents confusing an identifier like `eax_var' with register
7395 `eax'. */
7396 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7397 return (const reg_entry *) NULL;
7398
af6bdddf 7399 *end_op = s;
252b5132
RH		 7400
7401 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7402
5f47d35b 7403 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7404 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7405 {
5f47d35b
AM		 7406 if (is_space_char (*s))
7407 ++s;
7408 if (*s == '(')
7409 {
af6bdddf 7410 ++s;
5f47d35b
AM		 7411 if (is_space_char (*s))
7412 ++s;
7413 if (*s >= '0' && *s <= '7')
7414 {
db557034 7415 int fpr = *s - '0';
af6bdddf 7416 ++s;
5f47d35b
AM		 7417 if (is_space_char (*s))
7418 ++s;
7419 if (*s == ')')
7420 {
7421 *end_op = s + 1;
db557034
AM		 7422 r = hash_find (reg_hash, "st(0)");
7423 know (r);
7424 return r + fpr;
5f47d35b 7425 }
5f47d35b 7426 }
47926f60 7427 /* We have "%st(" then garbage. */
5f47d35b
AM		 7428 return (const reg_entry *) NULL;
7429 }
7430 }
7431
a60de03c
JB		 7432 if (r == NULL || allow_pseudo_reg)
7433 return r;
7434
0dfbf9d7 7435 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7436 return (const reg_entry *) NULL;
7437
192dc9c6
JB		 7438 if ((r->reg_type.bitfield.reg32
7439 || r->reg_type.bitfield.sreg3
7440 || r->reg_type.bitfield.control
7441 || r->reg_type.bitfield.debug
7442 || r->reg_type.bitfield.test)
7443 && !cpu_arch_flags.bitfield.cpui386)
7444 return (const reg_entry *) NULL;
7445
7446 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7447 return (const reg_entry *) NULL;
7448
7449 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7450 return (const reg_entry *) NULL;
7451
40f12533
L		 7452 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7453 return (const reg_entry *) NULL;
7454
db51cc60 7455 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7456 if (!allow_index_reg
db51cc60
L		 7457 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7458 return (const reg_entry *) NULL;
7459
a60de03c
JB		 7460 if (((r->reg_flags & (RegRex64 | RegRex))
7461 || r->reg_type.bitfield.reg64)
40fb9820 7462 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7463 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7464 && flag_code != CODE_64BIT)
20f0a1fc 7465 return (const reg_entry *) NULL;
1ae00879 7466
b7240065
JB		 7467 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7468 return (const reg_entry *) NULL;
7469
252b5132
RH		 7470 return r;
7471}
4d1bb795
JB		 7472
7473/* REG_STRING starts *before* REGISTER_PREFIX. */
7474
7475static const reg_entry *
7476parse_register (char *reg_string, char **end_op)
7477{
7478 const reg_entry *r;
7479
7480 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7481 r = parse_real_register (reg_string, end_op);
7482 else
7483 r = NULL;
7484 if (!r)
7485 {
7486 char *save = input_line_pointer;
7487 char c;
7488 symbolS *symbolP;
7489
7490 input_line_pointer = reg_string;
7491 c = get_symbol_end ();
7492 symbolP = symbol_find (reg_string);
7493 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7494 {
7495 const expressionS *e = symbol_get_value_expression (symbolP);
7496
7497 know (e->X_op == O_register);
4eed87de 7498 know (e->X_add_number >= 0
c3fe08fa 7499 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7500 r = i386_regtab + e->X_add_number;
7501 *end_op = input_line_pointer;
7502 }
7503 *input_line_pointer = c;
7504 input_line_pointer = save;
7505 }
7506 return r;
7507}
7508
7509int
7510i386_parse_name (char *name, expressionS *e, char *nextcharP)
7511{
7512 const reg_entry *r;
7513 char *end = input_line_pointer;
7514
7515 *end = *nextcharP;
7516 r = parse_register (name, &input_line_pointer);
7517 if (r && end <= input_line_pointer)
7518 {
7519 *nextcharP = *input_line_pointer;
7520 *input_line_pointer = 0;
7521 e->X_op = O_register;
7522 e->X_add_number = r - i386_regtab;
7523 return 1;
7524 }
7525 input_line_pointer = end;
7526 *end = 0;
ee86248c 7527 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 7528}
7529
7530void
7531md_operand (expressionS *e)
7532{
ee86248c
JB		 7533 char *end;
7534 const reg_entry *r;
4d1bb795 7535
ee86248c
JB		 7536 switch (*input_line_pointer)
7537 {
7538 case REGISTER_PREFIX:
7539 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 7540 if (r)
7541 {
7542 e->X_op = O_register;
7543 e->X_add_number = r - i386_regtab;
7544 input_line_pointer = end;
7545 }
ee86248c
JB		 7546 break;
7547
7548 case '[':
7549 assert (intel_syntax);
7550 end = input_line_pointer++;
7551 expression (e);
7552 if (*input_line_pointer == ']')
7553 {
7554 ++input_line_pointer;
7555 e->X_op_symbol = make_expr_symbol (e);
7556 e->X_add_symbol = NULL;
7557 e->X_add_number = 0;
7558 e->X_op = O_index;
7559 }
7560 else
7561 {
7562 e->X_op = O_absent;
7563 input_line_pointer = end;
7564 }
7565 break;
4d1bb795
JB		 7566 }
7567}
7568
252b5132 7569\f
4cc782b5 7570#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7571const char *md_shortopts = "kVQ:sqn";
252b5132 7572#else
12b55ccc 7573const char *md_shortopts = "qn";
252b5132 7574#endif
6e0b89ee 7575
3e73aa7c 7576#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7577#define OPTION_64 (OPTION_MD_BASE + 1)
7578#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7579#define OPTION_MARCH (OPTION_MD_BASE + 3)
7580#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7581#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7582#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7583#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7584#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7585#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 7586#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 7587#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
b3b91714 7588
99ad8390
NC		 7589struct option md_longopts[] =
7590{
3e73aa7c 7591 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 7592#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7593 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 7594 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7595#endif
b3b91714 7596 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7597 {"march", required_argument, NULL, OPTION_MARCH},
7598 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7599 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7600 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7601 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7602 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7603 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 7604 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 7605 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
252b5132
RH		 7606 {NULL, no_argument, NULL, 0}
7607};
7608size_t md_longopts_size = sizeof (md_longopts);
7609
7610int
9103f4f4 7611md_parse_option (int c, char *arg)
252b5132 7612{
9103f4f4 7613 unsigned int i;
6305a203 7614 char *arch, *next;
9103f4f4 7615
252b5132
RH		 7616 switch (c)
7617 {
12b55ccc
L		 7618 case 'n':
7619 optimize_align_code = 0;
7620 break;
7621
a38cf1db
AM		 7622 case 'q':
7623 quiet_warnings = 1;
252b5132
RH		 7624 break;
7625
7626#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7627 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7628 should be emitted or not. FIXME: Not implemented. */
7629 case 'Q':
252b5132
RH		 7630 break;
7631
7632 /* -V: SVR4 argument to print version ID. */
7633 case 'V':
7634 print_version_id ();
7635 break;
7636
a38cf1db
AM		 7637 /* -k: Ignore for FreeBSD compatibility. */
7638 case 'k':
252b5132 7639 break;
4cc782b5
ILT		 7640
7641 case 's':
7642 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7643 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7644 break;
99ad8390 7645#endif
321098a5
L		 7646#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7647 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 7648 case OPTION_64:
7649 {
7650 const char **list, **l;
7651
3e73aa7c
JH		 7652 list = bfd_target_list ();
7653 for (l = list; *l != NULL; l++)
8620418b 7654 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7655 || strcmp (*l, "coff-x86-64") == 0
7656 || strcmp (*l, "pe-x86-64") == 0
7657 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7658 {
7659 default_arch = "x86_64";
7660 break;
7661 }
3e73aa7c 7662 if (*l == NULL)
6e0b89ee 7663 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7664 free (list);
7665 }
7666 break;
7667#endif
252b5132 7668
6e0b89ee
AM		 7669 case OPTION_32:
7670 default_arch = "i386";
7671 break;
7672
b3b91714
AM		 7673 case OPTION_DIVIDE:
7674#ifdef SVR4_COMMENT_CHARS
7675 {
7676 char *n, *t;
7677 const char *s;
7678
7679 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7680 t = n;
7681 for (s = i386_comment_chars; *s != '\0'; s++)
7682 if (*s != '/')
7683 *t++ = *s;
7684 *t = '\0';
7685 i386_comment_chars = n;
7686 }
7687#endif
7688 break;
7689
9103f4f4 7690 case OPTION_MARCH:
6305a203
L		 7691 arch = xstrdup (arg);
7692 do
9103f4f4 7693 {
6305a203
L		 7694 if (*arch == '.')
7695 as_fatal (_("Invalid -march= option: `%s'"), arg);
7696 next = strchr (arch, '+');
7697 if (next)
7698 *next++ = '\0';
7699 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 7700 {
6305a203 7701 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 7702 {
6305a203
L		 7703 /* Processor. */
7704 cpu_arch_name = cpu_arch[i].name;
7705 cpu_sub_arch_name = NULL;
7706 cpu_arch_flags = cpu_arch[i].flags;
7707 cpu_arch_isa = cpu_arch[i].type;
7708 cpu_arch_isa_flags = cpu_arch[i].flags;
7709 if (!cpu_arch_tune_set)
7710 {
7711 cpu_arch_tune = cpu_arch_isa;
7712 cpu_arch_tune_flags = cpu_arch_isa_flags;
7713 }
7714 break;
7715 }
7716 else if (*cpu_arch [i].name == '.'
7717 && strcmp (arch, cpu_arch [i].name + 1) == 0)
7718 {
7719 /* ISA entension. */
7720 i386_cpu_flags flags;
7721 flags = cpu_flags_or (cpu_arch_flags,
7722 cpu_arch[i].flags);
0dfbf9d7 7723 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 7724 {
7725 if (cpu_sub_arch_name)
7726 {
7727 char *name = cpu_sub_arch_name;
7728 cpu_sub_arch_name = concat (name,
7729 cpu_arch[i].name,
1bf57e9f 7730 (const char *) NULL);
6305a203
L		 7731 free (name);
7732 }
7733 else
7734 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
7735 cpu_arch_flags = flags;
7736 }
7737 break;
ccc9c027 7738 }
9103f4f4 7739 }
6305a203
L		 7740
7741 if (i >= ARRAY_SIZE (cpu_arch))
7742 as_fatal (_("Invalid -march= option: `%s'"), arg);
7743
7744 arch = next;
9103f4f4 7745 }
6305a203 7746 while (next != NULL );
9103f4f4
L		 7747 break;
7748
7749 case OPTION_MTUNE:
7750 if (*arg == '.')
7751 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7752 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7753 {
7754 if (strcmp (arg, cpu_arch [i].name) == 0)
7755 {
ccc9c027 7756 cpu_arch_tune_set = 1;
9103f4f4
L		 7757 cpu_arch_tune = cpu_arch [i].type;
7758 cpu_arch_tune_flags = cpu_arch[i].flags;
7759 break;
7760 }
7761 }
7762 if (i >= ARRAY_SIZE (cpu_arch))
7763 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7764 break;
7765
1efbbeb4
L		 7766 case OPTION_MMNEMONIC:
7767 if (strcasecmp (arg, "att") == 0)
7768 intel_mnemonic = 0;
7769 else if (strcasecmp (arg, "intel") == 0)
7770 intel_mnemonic = 1;
7771 else
7772 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7773 break;
7774
7775 case OPTION_MSYNTAX:
7776 if (strcasecmp (arg, "att") == 0)
7777 intel_syntax = 0;
7778 else if (strcasecmp (arg, "intel") == 0)
7779 intel_syntax = 1;
7780 else
7781 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7782 break;
7783
7784 case OPTION_MINDEX_REG:
7785 allow_index_reg = 1;
7786 break;
7787
7788 case OPTION_MNAKED_REG:
7789 allow_naked_reg = 1;
7790 break;
7791
7792 case OPTION_MOLD_GCC:
7793 old_gcc = 1;
1efbbeb4
L		 7794 break;
7795
c0f3af97
L		 7796 case OPTION_MSSE2AVX:
7797 sse2avx = 1;
7798 break;
7799
daf50ae7
L		 7800 case OPTION_MSSE_CHECK:
7801 if (strcasecmp (arg, "error") == 0)
7802 sse_check = sse_check_error;
7803 else if (strcasecmp (arg, "warning") == 0)
7804 sse_check = sse_check_warning;
7805 else if (strcasecmp (arg, "none") == 0)
7806 sse_check = sse_check_none;
7807 else
7808 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
7809 break;
7810
252b5132
RH		 7811 default:
7812 return 0;
7813 }
7814 return 1;
7815}
7816
7817void
7818md_show_usage (stream)
7819 FILE *stream;
7820{
4cc782b5
ILT		 7821#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7822 fprintf (stream, _("\
a38cf1db
AM		 7823 -Q ignored\n\
7824 -V print assembler version number\n\
b3b91714
AM		 7825 -k ignored\n"));
7826#endif
7827 fprintf (stream, _("\
12b55ccc 7828 -n Do not optimize code alignment\n\
b3b91714
AM		 7829 -q quieten some warnings\n"));
7830#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7831 fprintf (stream, _("\
a38cf1db 7832 -s ignored\n"));
b3b91714 7833#endif
321098a5
L		 7834#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7835 || defined (TE_PE) || defined (TE_PEP))
751d281c
L		 7836 fprintf (stream, _("\
7837 --32/--64 generate 32bit/64bit code\n"));
7838#endif
b3b91714
AM		 7839#ifdef SVR4_COMMENT_CHARS
7840 fprintf (stream, _("\
7841 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 7842#else
7843 fprintf (stream, _("\
b3b91714 7844 --divide ignored\n"));
4cc782b5 7845#endif
9103f4f4 7846 fprintf (stream, _("\
6305a203
L		 7847 -march=CPU[,+EXTENSION...]\n\
7848 generate code for CPU and EXTENSION, CPU is one of:\n\
2cb4f3d5
L		 7849 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7850 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
bd5295b2 7851 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
2cb4f3d5 7852 generic32, generic64\n\
599121aa
L		 7853 EXTENSION is combination of:\n\
7854 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
f1f8f695 7855 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
bd5295b2 7856 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
c1e679ec 7857 svme, abm, padlock\n"));
6305a203 7858 fprintf (stream, _("\
2cb4f3d5
L		 7859 -mtune=CPU optimize for CPU, CPU is one of:\n\
7860 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7861 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
bd5295b2 7862 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
2cb4f3d5 7863 generic32, generic64\n"));
ba104c83 7864 fprintf (stream, _("\
c0f3af97
L		 7865 -msse2avx encode SSE instructions with VEX prefix\n"));
7866 fprintf (stream, _("\
daf50ae7
L		 7867 -msse-check=[none|error|warning]\n\
7868 check SSE instructions\n"));
7869 fprintf (stream, _("\
ba104c83
L		 7870 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7871 fprintf (stream, _("\
7872 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7873 fprintf (stream, _("\
7874 -mindex-reg support pseudo index registers\n"));
7875 fprintf (stream, _("\
7876 -mnaked-reg don't require `%%' prefix for registers\n"));
7877 fprintf (stream, _("\
7878 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 7879}
7880
3e73aa7c 7881#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5
L		 7882 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7883 || defined (TE_PE) || defined (TE_PEP))
252b5132
RH		 7884
7885/* Pick the target format to use. */
7886
47926f60 7887const char *
e3bb37b5 7888i386_target_format (void)
252b5132 7889{
3e73aa7c 7890 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 7891 {
7892 set_code_flag (CODE_64BIT);
0dfbf9d7 7893 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 7894 {
7895 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7896 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7897 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7898 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7899 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7900 cpu_arch_isa_flags.bitfield.cpui686 = 1;
bd5295b2 7901 cpu_arch_isa_flags.bitfield.cpuclflush = 1;
40fb9820 7902 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 7903 cpu_arch_isa_flags.bitfield.cpusse = 1;
7904 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7905 }
0dfbf9d7 7906 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 7907 {
7908 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7909 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7910 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7911 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7912 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7913 cpu_arch_tune_flags.bitfield.cpui686 = 1;
bd5295b2 7914 cpu_arch_tune_flags.bitfield.cpuclflush = 1;
40fb9820 7915 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 7916 cpu_arch_tune_flags.bitfield.cpusse = 1;
7917 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7918 }
9103f4f4 7919 }
3e73aa7c 7920 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 7921 {
7922 set_code_flag (CODE_32BIT);
0dfbf9d7 7923 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 7924 {
7925 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7926 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7927 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7928 }
0dfbf9d7 7929 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 7930 {
7931 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7932 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7933 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7934 }
9103f4f4 7935 }
3e73aa7c
JH		 7936 else
7937 as_fatal (_("Unknown architecture"));
252b5132
RH		 7938 switch (OUTPUT_FLAVOR)
7939 {
321098a5 7940#if defined (TE_PE) || defined (TE_PEP)
872ce6ff 7941 case bfd_target_coff_flavour:
321098a5 7942 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
872ce6ff 7943#endif
4c63da97
AM		 7944#ifdef OBJ_MAYBE_AOUT
7945 case bfd_target_aout_flavour:
47926f60 7946 return AOUT_TARGET_FORMAT;
4c63da97
AM		 7947#endif
7948#ifdef OBJ_MAYBE_COFF
252b5132
RH		 7949 case bfd_target_coff_flavour:
7950 return "coff-i386";
4c63da97 7951#endif
3e73aa7c 7952#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 7953 case bfd_target_elf_flavour:
3e73aa7c 7954 {
e5cb08ac 7955 if (flag_code == CODE_64BIT)
4fa24527
JB		 7956 {
7957 object_64bit = 1;
7958 use_rela_relocations = 1;
7959 }
9d7cbccd 7960 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 7961 }
4c63da97 7962#endif
252b5132
RH		 7963 default:
7964 abort ();
7965 return NULL;
7966 }
7967}
7968
47926f60 7969#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 7970
7971#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 7972void
7973i386_elf_emit_arch_note (void)
a847613f 7974{
718ddfc0 7975 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 7976 {
7977 char *p;
7978 asection *seg = now_seg;
7979 subsegT subseg = now_subseg;
7980 Elf_Internal_Note i_note;
7981 Elf_External_Note e_note;
7982 asection *note_secp;
7983 int len;
7984
7985 /* Create the .note section. */
7986 note_secp = subseg_new (".note", 0);
7987 bfd_set_section_flags (stdoutput,
7988 note_secp,
7989 SEC_HAS_CONTENTS | SEC_READONLY);
7990
7991 /* Process the arch string. */
7992 len = strlen (cpu_arch_name);
7993
7994 i_note.namesz = len + 1;
7995 i_note.descsz = 0;
7996 i_note.type = NT_ARCH;
7997 p = frag_more (sizeof (e_note.namesz));
7998 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7999 p = frag_more (sizeof (e_note.descsz));
8000 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8001 p = frag_more (sizeof (e_note.type));
8002 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8003 p = frag_more (len + 1);
8004 strcpy (p, cpu_arch_name);
8005
8006 frag_align (2, 0, 0);
8007
8008 subseg_set (seg, subseg);
8009 }
8010}
8011#endif
252b5132 8012\f
252b5132
RH		 8013symbolS *
8014md_undefined_symbol (name)
8015 char *name;
8016{
18dc2407
ILT		 8017 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8018 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8019 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8020 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8021 {
8022 if (!GOT_symbol)
8023 {
8024 if (symbol_find (name))
8025 as_bad (_("GOT already in symbol table"));
8026 GOT_symbol = symbol_new (name, undefined_section,
8027 (valueT) 0, &zero_address_frag);
8028 };
8029 return GOT_symbol;
8030 }
252b5132
RH		 8031 return 0;
8032}
8033
8034/* Round up a section size to the appropriate boundary. */
47926f60 8035
252b5132
RH		 8036valueT
8037md_section_align (segment, size)
ab9da554 8038 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8039 valueT size;
8040{
4c63da97
AM		 8041#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8042 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8043 {
8044 /* For a.out, force the section size to be aligned. If we don't do
8045 this, BFD will align it for us, but it will not write out the
8046 final bytes of the section. This may be a bug in BFD, but it is
8047 easier to fix it here since that is how the other a.out targets
8048 work. */
8049 int align;
8050
8051 align = bfd_get_section_alignment (stdoutput, segment);
8052 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8053 }
252b5132
RH		 8054#endif
8055
8056 return size;
8057}
8058
8059/* On the i386, PC-relative offsets are relative to the start of the
8060 next instruction. That is, the address of the offset, plus its
8061 size, since the offset is always the last part of the insn. */
8062
8063long
e3bb37b5 8064md_pcrel_from (fixS *fixP)
252b5132
RH		 8065{
8066 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8067}
8068
8069#ifndef I386COFF
8070
8071static void
e3bb37b5 8072s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8073{
29b0f896 8074 int temp;
252b5132 8075
8a75718c
JB		 8076#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8077 if (IS_ELF)
8078 obj_elf_section_change_hook ();
8079#endif
252b5132
RH		 8080 temp = get_absolute_expression ();
8081 subseg_set (bss_section, (subsegT) temp);
8082 demand_empty_rest_of_line ();
8083}
8084
8085#endif
8086
252b5132 8087void
e3bb37b5 8088i386_validate_fix (fixS *fixp)
252b5132
RH		 8089{
8090 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8091 {
23df1078
JH		 8092 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8093 {
4fa24527 8094 if (!object_64bit)
23df1078
JH		 8095 abort ();
8096 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8097 }
8098 else
8099 {
4fa24527 8100 if (!object_64bit)
d6ab8113
JB		 8101 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8102 else
8103 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8104 }
252b5132
RH		 8105 fixp->fx_subsy = 0;
8106 }
8107}
8108
252b5132
RH		 8109arelent *
8110tc_gen_reloc (section, fixp)
ab9da554 8111 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8112 fixS *fixp;
8113{
8114 arelent *rel;
8115 bfd_reloc_code_real_type code;
8116
8117 switch (fixp->fx_r_type)
8118 {
3e73aa7c
JH		 8119 case BFD_RELOC_X86_64_PLT32:
8120 case BFD_RELOC_X86_64_GOT32:
8121 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8122 case BFD_RELOC_386_PLT32:
8123 case BFD_RELOC_386_GOT32:
8124 case BFD_RELOC_386_GOTOFF:
8125 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8126 case BFD_RELOC_386_TLS_GD:
8127 case BFD_RELOC_386_TLS_LDM:
8128 case BFD_RELOC_386_TLS_LDO_32:
8129 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8130 case BFD_RELOC_386_TLS_IE:
8131 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8132 case BFD_RELOC_386_TLS_LE_32:
8133 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8134 case BFD_RELOC_386_TLS_GOTDESC:
8135 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8136 case BFD_RELOC_X86_64_TLSGD:
8137 case BFD_RELOC_X86_64_TLSLD:
8138 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8139 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8140 case BFD_RELOC_X86_64_GOTTPOFF:
8141 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8142 case BFD_RELOC_X86_64_TPOFF64:
8143 case BFD_RELOC_X86_64_GOTOFF64:
8144 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8145 case BFD_RELOC_X86_64_GOT64:
8146 case BFD_RELOC_X86_64_GOTPCREL64:
8147 case BFD_RELOC_X86_64_GOTPC64:
8148 case BFD_RELOC_X86_64_GOTPLT64:
8149 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8150 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8151 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8152 case BFD_RELOC_RVA:
8153 case BFD_RELOC_VTABLE_ENTRY:
8154 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8155#ifdef TE_PE
8156 case BFD_RELOC_32_SECREL:
8157#endif
252b5132
RH		 8158 code = fixp->fx_r_type;
8159 break;
dbbaec26
L		 8160 case BFD_RELOC_X86_64_32S:
8161 if (!fixp->fx_pcrel)
8162 {
8163 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8164 code = fixp->fx_r_type;
8165 break;
8166 }
252b5132 8167 default:
93382f6d 8168 if (fixp->fx_pcrel)
252b5132 8169 {
93382f6d
AM		 8170 switch (fixp->fx_size)
8171 {
8172 default:
b091f402
AM		 8173 as_bad_where (fixp->fx_file, fixp->fx_line,
8174 _("can not do %d byte pc-relative relocation"),
8175 fixp->fx_size);
93382f6d
AM		 8176 code = BFD_RELOC_32_PCREL;
8177 break;
8178 case 1: code = BFD_RELOC_8_PCREL; break;
8179 case 2: code = BFD_RELOC_16_PCREL; break;
8180 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8181#ifdef BFD64
8182 case 8: code = BFD_RELOC_64_PCREL; break;
8183#endif
93382f6d
AM		 8184 }
8185 }
8186 else
8187 {
8188 switch (fixp->fx_size)
8189 {
8190 default:
b091f402
AM		 8191 as_bad_where (fixp->fx_file, fixp->fx_line,
8192 _("can not do %d byte relocation"),
8193 fixp->fx_size);
93382f6d
AM		 8194 code = BFD_RELOC_32;
8195 break;
8196 case 1: code = BFD_RELOC_8; break;
8197 case 2: code = BFD_RELOC_16; break;
8198 case 4: code = BFD_RELOC_32; break;
937149dd 8199#ifdef BFD64
3e73aa7c 8200 case 8: code = BFD_RELOC_64; break;
937149dd 8201#endif
93382f6d 8202 }
252b5132
RH		 8203 }
8204 break;
8205 }
252b5132 8206
d182319b
JB		 8207 if ((code == BFD_RELOC_32
8208 || code == BFD_RELOC_32_PCREL
8209 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8210 && GOT_symbol
8211 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8212 {
4fa24527 8213 if (!object_64bit)
d6ab8113
JB		 8214 code = BFD_RELOC_386_GOTPC;
8215 else
8216 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8217 }
7b81dfbb
AJ		 8218 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8219 && GOT_symbol
8220 && fixp->fx_addsy == GOT_symbol)
8221 {
8222 code = BFD_RELOC_X86_64_GOTPC64;
8223 }
252b5132
RH		 8224
8225 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8226 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8227 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8228
8229 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8230
3e73aa7c
JH		 8231 if (!use_rela_relocations)
8232 {
8233 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8234 vtable entry to be used in the relocation's section offset. */
8235 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8236 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8237#if defined (OBJ_COFF) && defined (TE_PE)
8238 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8239 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8240 else
8241#endif
c6682705 8242 rel->addend = 0;
3e73aa7c
JH		 8243 }
8244 /* Use the rela in 64bit mode. */
252b5132 8245 else
3e73aa7c 8246 {
062cd5e7
AS		 8247 if (!fixp->fx_pcrel)
8248 rel->addend = fixp->fx_offset;
8249 else
8250 switch (code)
8251 {
8252 case BFD_RELOC_X86_64_PLT32:
8253 case BFD_RELOC_X86_64_GOT32:
8254 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8255 case BFD_RELOC_X86_64_TLSGD:
8256 case BFD_RELOC_X86_64_TLSLD:
8257 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8258 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8259 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8260 rel->addend = fixp->fx_offset - fixp->fx_size;
8261 break;
8262 default:
8263 rel->addend = (section->vma
8264 - fixp->fx_size
8265 + fixp->fx_addnumber
8266 + md_pcrel_from (fixp));
8267 break;
8268 }
3e73aa7c
JH		 8269 }
8270
252b5132
RH		 8271 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8272 if (rel->howto == NULL)
8273 {
8274 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8275 _("cannot represent relocation type %s"),
252b5132
RH		 8276 bfd_get_reloc_code_name (code));
8277 /* Set howto to a garbage value so that we can keep going. */
8278 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
8279 assert (rel->howto != NULL);
8280 }
8281
8282 return rel;
8283}
8284
ee86248c 8285#include "tc-i386-intel.c"
54cfded0 8286
a60de03c
JB		 8287void
8288tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 8289{
a60de03c
JB		 8290 int saved_naked_reg;
8291 char saved_register_dot;
54cfded0 8292
a60de03c
JB		 8293 saved_naked_reg = allow_naked_reg;
8294 allow_naked_reg = 1;
8295 saved_register_dot = register_chars['.'];
8296 register_chars['.'] = '.';
8297 allow_pseudo_reg = 1;
8298 expression_and_evaluate (exp);
8299 allow_pseudo_reg = 0;
8300 register_chars['.'] = saved_register_dot;
8301 allow_naked_reg = saved_naked_reg;
8302
8303 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 8304 {
a60de03c
JB		 8305 if ((addressT) exp->X_add_number < i386_regtab_size)
8306 {
8307 exp->X_op = O_constant;
8308 exp->X_add_number = i386_regtab[exp->X_add_number]
8309 .dw2_regnum[flag_code >> 1];
8310 }
8311 else
8312 exp->X_op = O_illegal;
54cfded0 8313 }
54cfded0
AM		 8314}
8315
8316void
8317tc_x86_frame_initial_instructions (void)
8318{
a60de03c
JB		 8319 static unsigned int sp_regno[2];
8320
8321 if (!sp_regno[flag_code >> 1])
8322 {
8323 char *saved_input = input_line_pointer;
8324 char sp[][4] = {"esp", "rsp"};
8325 expressionS exp;
a4447b93 8326
a60de03c
JB		 8327 input_line_pointer = sp[flag_code >> 1];
8328 tc_x86_parse_to_dw2regnum (&exp);
8329 assert (exp.X_op == O_constant);
8330 sp_regno[flag_code >> 1] = exp.X_add_number;
8331 input_line_pointer = saved_input;
8332 }
a4447b93 8333
a60de03c 8334 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 8335 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8336}
d2b2c203
DJ		 8337
8338int
8339i386_elf_section_type (const char *str, size_t len)
8340{
8341 if (flag_code == CODE_64BIT
8342 && len == sizeof ("unwind") - 1
8343 && strncmp (str, "unwind", 6) == 0)
8344 return SHT_X86_64_UNWIND;
8345
8346 return -1;
8347}
bb41ade5 8348
ad5fec3b
EB		 8349#ifdef TE_SOLARIS
8350void
8351i386_solaris_fix_up_eh_frame (segT sec)
8352{
8353 if (flag_code == CODE_64BIT)
8354 elf_section_type (sec) = SHT_X86_64_UNWIND;
8355}
8356#endif
8357
bb41ade5
AM		 8358#ifdef TE_PE
8359void
8360tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8361{
8362 expressionS expr;
8363
8364 expr.X_op = O_secrel;
8365 expr.X_add_symbol = symbol;
8366 expr.X_add_number = 0;
8367 emit_expr (&expr, size);
8368}
8369#endif
3b22753a
L		 8370
8371#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8372/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8373
01e1a5bc 8374bfd_vma
3b22753a
L		 8375x86_64_section_letter (int letter, char **ptr_msg)
8376{
8377 if (flag_code == CODE_64BIT)
8378 {
8379 if (letter == 'l')
8380 return SHF_X86_64_LARGE;
8381
8382 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8383 }
3b22753a 8384 else
64e74474 8385 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8386 return -1;
8387}
8388
01e1a5bc 8389bfd_vma
3b22753a
L		 8390x86_64_section_word (char *str, size_t len)
8391{
8620418b 8392 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8393 return SHF_X86_64_LARGE;
8394
8395 return -1;
8396}
8397
8398static void
8399handle_large_common (int small ATTRIBUTE_UNUSED)
8400{
8401 if (flag_code != CODE_64BIT)
8402 {
8403 s_comm_internal (0, elf_common_parse);
8404 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8405 }
8406 else
8407 {
8408 static segT lbss_section;
8409 asection *saved_com_section_ptr = elf_com_section_ptr;
8410 asection *saved_bss_section = bss_section;
8411
8412 if (lbss_section == NULL)
8413 {
8414 flagword applicable;
8415 segT seg = now_seg;
8416 subsegT subseg = now_subseg;
8417
8418 /* The .lbss section is for local .largecomm symbols. */
8419 lbss_section = subseg_new (".lbss", 0);
8420 applicable = bfd_applicable_section_flags (stdoutput);
8421 bfd_set_section_flags (stdoutput, lbss_section,
8422 applicable & SEC_ALLOC);
8423 seg_info (lbss_section)->bss = 1;
8424
8425 subseg_set (seg, subseg);
8426 }
8427
8428 elf_com_section_ptr = &_bfd_elf_large_com_section;
8429 bss_section = lbss_section;
8430
8431 s_comm_internal (0, elf_common_parse);
8432
8433 elf_com_section_ptr = saved_com_section_ptr;
8434 bss_section = saved_bss_section;
8435 }
8436}
8437#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
This page took 2.327391 seconds and 4 git commands to generate.