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* scripttempl/elfxtensa.sc: Merge changes from elf.sc.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4dc85607 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
252b5132 36
252b5132
RH		 37#ifndef REGISTER_WARNINGS
38#define REGISTER_WARNINGS 1
39#endif
40
c3332e24 41#ifndef INFER_ADDR_PREFIX
eecb386c 42#define INFER_ADDR_PREFIX 1
c3332e24
AM		 43#endif
44
252b5132
RH		 45#ifndef SCALE1_WHEN_NO_INDEX
46/* Specifying a scale factor besides 1 when there is no index is
47 futile. eg. `mov (%ebx,2),%al' does exactly the same as
48 `mov (%ebx),%al'. To slavishly follow what the programmer
49 specified, set SCALE1_WHEN_NO_INDEX to 0. */
50#define SCALE1_WHEN_NO_INDEX 1
51#endif
52
29b0f896
AM		 53#ifndef DEFAULT_ARCH
54#define DEFAULT_ARCH "i386"
246fcdee 55#endif
252b5132 56
edde18a5
AM		 57#ifndef INLINE
58#if __GNUC__ >= 2
59#define INLINE __inline__
60#else
61#define INLINE
62#endif
63#endif
64
e3bb37b5
L		 65static void set_code_flag (int);
66static void set_16bit_gcc_code_flag (int);
67static void set_intel_syntax (int);
68static void set_cpu_arch (int);
6482c264 69#ifdef TE_PE
e3bb37b5 70static void pe_directive_secrel (int);
6482c264 71#endif
e3bb37b5
L		 72static void signed_cons (int);
73static char *output_invalid (int c);
74static int i386_operand (char *);
75static int i386_intel_operand (char *, int);
76static const reg_entry *parse_register (char *, char **);
77static char *parse_insn (char *, char *);
78static char *parse_operands (char *, const char *);
79static void swap_operands (void);
4d456e3d 80static void swap_2_operands (int, int);
e3bb37b5
L		 81static void optimize_imm (void);
82static void optimize_disp (void);
83static int match_template (void);
84static int check_string (void);
85static int process_suffix (void);
86static int check_byte_reg (void);
87static int check_long_reg (void);
88static int check_qword_reg (void);
89static int check_word_reg (void);
90static int finalize_imm (void);
91static int process_operands (void);
92static const seg_entry *build_modrm_byte (void);
93static void output_insn (void);
94static void output_imm (fragS *, offsetT);
95static void output_disp (fragS *, offsetT);
29b0f896 96#ifndef I386COFF
e3bb37b5 97static void s_bss (int);
252b5132 98#endif
17d4e2a2
L		 99#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
100static void handle_large_common (int small ATTRIBUTE_UNUSED);
101#endif
252b5132 102
a847613f 103static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 104
252b5132 105/* 'md_assemble ()' gathers together information and puts it into a
47926f60 106 i386_insn. */
252b5132 107
520dc8e8
AM		 108union i386_op
109 {
110 expressionS *disps;
111 expressionS *imms;
112 const reg_entry *regs;
113 };
114
252b5132
RH		 115struct _i386_insn
116 {
47926f60 117 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 118 template tm;
119
120 /* SUFFIX holds the instruction mnemonic suffix if given.
121 (e.g. 'l' for 'movl') */
122 char suffix;
123
47926f60 124 /* OPERANDS gives the number of given operands. */
252b5132
RH		 125 unsigned int operands;
126
127 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
128 of given register, displacement, memory operands and immediate
47926f60 129 operands. */
252b5132
RH		 130 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
131
132 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 133 use OP[i] for the corresponding operand. */
252b5132
RH		 134 unsigned int types[MAX_OPERANDS];
135
520dc8e8
AM		 136 /* Displacement expression, immediate expression, or register for each
137 operand. */
138 union i386_op op[MAX_OPERANDS];
252b5132 139
3e73aa7c
JH		 140 /* Flags for operands. */
141 unsigned int flags[MAX_OPERANDS];
142#define Operand_PCrel 1
143
252b5132 144 /* Relocation type for operand */
f86103b7 145 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 146
252b5132
RH		 147 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
148 the base index byte below. */
149 const reg_entry *base_reg;
150 const reg_entry *index_reg;
151 unsigned int log2_scale_factor;
152
153 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 154 explicit segment overrides are given. */
ce8a8b2f 155 const seg_entry *seg[2];
252b5132
RH		 156
157 /* PREFIX holds all the given prefix opcodes (usually null).
158 PREFIXES is the number of prefix opcodes. */
159 unsigned int prefixes;
160 unsigned char prefix[MAX_PREFIXES];
161
162 /* RM and SIB are the modrm byte and the sib byte where the
163 addressing modes of this insn are encoded. */
164
165 modrm_byte rm;
3e73aa7c 166 rex_byte rex;
252b5132
RH		 167 sib_byte sib;
168 };
169
170typedef struct _i386_insn i386_insn;
171
172/* List of chars besides those in app.c:symbol_chars that can start an
173 operand. Used to prevent the scrubber eating vital white-space. */
32137342 174const char extra_symbol_chars[] = "*%-(["
252b5132 175#ifdef LEX_AT
32137342
NC		 176 "@"
177#endif
178#ifdef LEX_QM
179 "?"
252b5132 180#endif
32137342 181 ;
252b5132 182
29b0f896
AM		 183#if (defined (TE_I386AIX) \
184 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 185 && !defined (TE_GNU) \
29b0f896 186 && !defined (TE_LINUX) \
32137342 187 && !defined (TE_NETWARE) \
29b0f896
AM		 188 && !defined (TE_FreeBSD) \
189 && !defined (TE_NetBSD)))
252b5132 190/* This array holds the chars that always start a comment. If the
b3b91714
AM		 191 pre-processor is disabled, these aren't very useful. The option
192 --divide will remove '/' from this list. */
193const char *i386_comment_chars = "#/";
194#define SVR4_COMMENT_CHARS 1
252b5132 195#define PREFIX_SEPARATOR '\\'
252b5132 196
b3b91714
AM		 197#else
198const char *i386_comment_chars = "#";
199#define PREFIX_SEPARATOR '/'
200#endif
201
252b5132
RH		 202/* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 204 .line and .file directives will appear in the pre-processed output.
205 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 206 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 207 #NO_APP at the beginning of its output.
208 Also note that comments started like this one will always work if
252b5132 209 '/' isn't otherwise defined. */
b3b91714 210const char line_comment_chars[] = "#/";
252b5132 211
63a0b638 212const char line_separator_chars[] = ";";
252b5132 213
ce8a8b2f
AM		 214/* Chars that can be used to separate mant from exp in floating point
215 nums. */
252b5132
RH		 216const char EXP_CHARS[] = "eE";
217
ce8a8b2f
AM		 218/* Chars that mean this number is a floating point constant
219 As in 0f12.456
220 or 0d1.2345e12. */
252b5132
RH		 221const char FLT_CHARS[] = "fFdDxX";
222
ce8a8b2f 223/* Tables for lexical analysis. */
252b5132
RH		 224static char mnemonic_chars[256];
225static char register_chars[256];
226static char operand_chars[256];
227static char identifier_chars[256];
228static char digit_chars[256];
229
ce8a8b2f 230/* Lexical macros. */
252b5132
RH		 231#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
232#define is_operand_char(x) (operand_chars[(unsigned char) x])
233#define is_register_char(x) (register_chars[(unsigned char) x])
234#define is_space_char(x) ((x) == ' ')
235#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
236#define is_digit_char(x) (digit_chars[(unsigned char) x])
237
0234cb7c 238/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 239static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
240
241/* md_assemble() always leaves the strings it's passed unaltered. To
242 effect this we maintain a stack of saved characters that we've smashed
243 with '\0's (indicating end of strings for various sub-fields of the
47926f60 244 assembler instruction). */
252b5132 245static char save_stack[32];
ce8a8b2f 246static char *save_stack_p;
252b5132
RH		 247#define END_STRING_AND_SAVE(s) \
248 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
249#define RESTORE_END_STRING(s) \
250 do { *(s) = *--save_stack_p; } while (0)
251
47926f60 252/* The instruction we're assembling. */
252b5132
RH		 253static i386_insn i;
254
255/* Possible templates for current insn. */
256static const templates *current_templates;
257
31b2323c
L		 258/* Per instruction expressionS buffers: max displacements & immediates. */
259static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
260static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 261
47926f60
KH		 262/* Current operand we are working on. */
263static int this_operand;
252b5132 264
3e73aa7c
JH		 265/* We support four different modes. FLAG_CODE variable is used to distinguish
266 these. */
267
268enum flag_code {
269 CODE_32BIT,
270 CODE_16BIT,
271 CODE_64BIT };
f3c180ae 272#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 273
274static enum flag_code flag_code;
4fa24527 275static unsigned int object_64bit;
3e73aa7c
JH		 276static int use_rela_relocations = 0;
277
278/* The names used to print error messages. */
b77a7acd 279static const char *flag_code_names[] =
3e73aa7c
JH		 280 {
281 "32",
282 "16",
283 "64"
284 };
252b5132 285
47926f60
KH		 286/* 1 for intel syntax,
287 0 if att syntax. */
288static int intel_syntax = 0;
252b5132 289
47926f60
KH		 290/* 1 if register prefix % not required. */
291static int allow_naked_reg = 0;
252b5132 292
2ca3ace5
L		 293/* Register prefix used for error message. */
294static const char *register_prefix = "%";
295
47926f60
KH		 296/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
297 leave, push, and pop instructions so that gcc has the same stack
298 frame as in 32 bit mode. */
299static char stackop_size = '\0';
eecb386c 300
12b55ccc
L		 301/* Non-zero to optimize code alignment. */
302int optimize_align_code = 1;
303
47926f60
KH		 304/* Non-zero to quieten some warnings. */
305static int quiet_warnings = 0;
a38cf1db 306
47926f60
KH		 307/* CPU name. */
308static const char *cpu_arch_name = NULL;
5c6af06e 309static const char *cpu_sub_arch_name = NULL;
a38cf1db 310
47926f60 311/* CPU feature flags. */
29b0f896 312static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 313
ccc9c027
L		 314/* If we have selected a cpu we are generating instructions for. */
315static int cpu_arch_tune_set = 0;
316
9103f4f4
L		 317/* Cpu we are generating instructions for. */
318static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
319
320/* CPU feature flags of cpu we are generating instructions for. */
321static unsigned int cpu_arch_tune_flags = 0;
322
ccc9c027
L		 323/* CPU instruction set architecture used. */
324static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
325
9103f4f4
L		 326/* CPU feature flags of instruction set architecture used. */
327static unsigned int cpu_arch_isa_flags = 0;
328
fddf5b5b
AM		 329/* If set, conditional jumps are not automatically promoted to handle
330 larger than a byte offset. */
331static unsigned int no_cond_jump_promotion = 0;
332
29b0f896 333/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 334static symbolS *GOT_symbol;
29b0f896 335
a4447b93
RH		 336/* The dwarf2 return column, adjusted for 32 or 64 bit. */
337unsigned int x86_dwarf2_return_column;
338
339/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
340int x86_cie_data_alignment;
341
252b5132 342/* Interface to relax_segment.
fddf5b5b
AM		 343 There are 3 major relax states for 386 jump insns because the
344 different types of jumps add different sizes to frags when we're
345 figuring out what sort of jump to choose to reach a given label. */
252b5132 346
47926f60 347/* Types. */
93c2a809
AM		 348#define UNCOND_JUMP 0
349#define COND_JUMP 1
350#define COND_JUMP86 2
fddf5b5b 351
47926f60 352/* Sizes. */
252b5132
RH		 353#define CODE16 1
354#define SMALL 0
29b0f896 355#define SMALL16 (SMALL | CODE16)
252b5132 356#define BIG 2
29b0f896 357#define BIG16 (BIG | CODE16)
252b5132
RH		 358
359#ifndef INLINE
360#ifdef __GNUC__
361#define INLINE __inline__
362#else
363#define INLINE
364#endif
365#endif
366
fddf5b5b
AM		 367#define ENCODE_RELAX_STATE(type, size) \
368 ((relax_substateT) (((type) << 2) | (size)))
369#define TYPE_FROM_RELAX_STATE(s) \
370 ((s) >> 2)
371#define DISP_SIZE_FROM_RELAX_STATE(s) \
372 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 373
374/* This table is used by relax_frag to promote short jumps to long
375 ones where necessary. SMALL (short) jumps may be promoted to BIG
376 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
377 don't allow a short jump in a 32 bit code segment to be promoted to
378 a 16 bit offset jump because it's slower (requires data size
379 prefix), and doesn't work, unless the destination is in the bottom
380 64k of the code segment (The top 16 bits of eip are zeroed). */
381
382const relax_typeS md_relax_table[] =
383{
24eab124
AM		 384 /* The fields are:
385 1) most positive reach of this state,
386 2) most negative reach of this state,
93c2a809 387 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 388 4) which index into the table to try if we can't fit into this one. */
252b5132 389
fddf5b5b 390 /* UNCOND_JUMP states. */
93c2a809
AM		 391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
393 /* dword jmp adds 4 bytes to frag:
394 0 extra opcode bytes, 4 displacement bytes. */
252b5132 395 {0, 0, 4, 0},
93c2a809
AM		 396 /* word jmp adds 2 byte2 to frag:
397 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 398 {0, 0, 2, 0},
399
93c2a809
AM		 400 /* COND_JUMP states. */
401 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
403 /* dword conditionals adds 5 bytes to frag:
404 1 extra opcode byte, 4 displacement bytes. */
405 {0, 0, 5, 0},
fddf5b5b 406 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 407 1 extra opcode byte, 2 displacement bytes. */
408 {0, 0, 3, 0},
409
410 /* COND_JUMP86 states. */
411 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
413 /* dword conditionals adds 5 bytes to frag:
414 1 extra opcode byte, 4 displacement bytes. */
415 {0, 0, 5, 0},
416 /* word conditionals add 4 bytes to frag:
417 1 displacement byte and a 3 byte long branch insn. */
418 {0, 0, 4, 0}
252b5132
RH		 419};
420
9103f4f4
L		 421static const arch_entry cpu_arch[] =
422{
423 {"generic32", PROCESSOR_GENERIC32,
d32cad65 424 Cpu186|Cpu286|Cpu386},
9103f4f4 425 {"generic64", PROCESSOR_GENERIC64,
d32cad65 426 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 427 |CpuMMX2|CpuSSE|CpuSSE2},
428 {"i8086", PROCESSOR_UNKNOWN,
d32cad65 429 0},
9103f4f4 430 {"i186", PROCESSOR_UNKNOWN,
d32cad65 431 Cpu186},
9103f4f4 432 {"i286", PROCESSOR_UNKNOWN,
d32cad65 433 Cpu186|Cpu286},
9103f4f4 434 {"i386", PROCESSOR_GENERIC32,
d32cad65 435 Cpu186|Cpu286|Cpu386},
9103f4f4 436 {"i486", PROCESSOR_I486,
d32cad65 437 Cpu186|Cpu286|Cpu386|Cpu486},
9103f4f4 438 {"i586", PROCESSOR_PENTIUM,
d32cad65 439 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 440 {"i686", PROCESSOR_PENTIUMPRO,
d32cad65 441 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 442 {"pentium", PROCESSOR_PENTIUM,
d32cad65 443 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 444 {"pentiumpro",PROCESSOR_PENTIUMPRO,
d32cad65 445 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 446 {"pentiumii", PROCESSOR_PENTIUMPRO,
d32cad65 447 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
9103f4f4 448 {"pentiumiii",PROCESSOR_PENTIUMPRO,
d32cad65 449 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
9103f4f4 450 {"pentium4", PROCESSOR_PENTIUM4,
d32cad65 451 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 452 |CpuMMX2|CpuSSE|CpuSSE2},
453 {"prescott", PROCESSOR_NOCONA,
d32cad65 454 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 455 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
456 {"nocona", PROCESSOR_NOCONA,
d32cad65 457 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 458 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 459 {"yonah", PROCESSOR_CORE,
d32cad65 460 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 461 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 462 {"core", PROCESSOR_CORE,
d32cad65 463 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
ef05d495
L		 464 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
465 {"merom", PROCESSOR_CORE2,
466 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
467 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
468 {"core2", PROCESSOR_CORE2,
469 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
470 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4 471 {"k6", PROCESSOR_K6,
d32cad65 472 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
9103f4f4 473 {"k6_2", PROCESSOR_K6,
d32cad65 474 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
9103f4f4 475 {"athlon", PROCESSOR_ATHLON,
d32cad65 476 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 477 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
478 {"sledgehammer", PROCESSOR_K8,
d32cad65 479 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 480 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
481 {"opteron", PROCESSOR_K8,
d32cad65 482 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 483 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
484 {"k8", PROCESSOR_K8,
d32cad65 485 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4 486 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
050dfa73 487 {"amdfam10", PROCESSOR_AMDFAM10,
d32cad65
L		 488 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
489 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
490 |CpuABM},
9103f4f4
L		 491 {".mmx", PROCESSOR_UNKNOWN,
492 CpuMMX},
493 {".sse", PROCESSOR_UNKNOWN,
494 CpuMMX|CpuMMX2|CpuSSE},
495 {".sse2", PROCESSOR_UNKNOWN,
496 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
497 {".sse3", PROCESSOR_UNKNOWN,
498 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495
L		 499 {".ssse3", PROCESSOR_UNKNOWN,
500 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
42903f7f
L		 501 {".sse4.1", PROCESSOR_UNKNOWN,
502 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1},
381d071f
L		 503 {".sse4.2", PROCESSOR_UNKNOWN,
504 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4},
505 {".sse4", PROCESSOR_UNKNOWN,
506 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4},
9103f4f4
L		 507 {".3dnow", PROCESSOR_UNKNOWN,
508 CpuMMX|Cpu3dnow},
509 {".3dnowa", PROCESSOR_UNKNOWN,
510 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
511 {".padlock", PROCESSOR_UNKNOWN,
512 CpuPadLock},
513 {".pacifica", PROCESSOR_UNKNOWN,
514 CpuSVME},
515 {".svme", PROCESSOR_UNKNOWN,
050dfa73
MM		 516 CpuSVME},
517 {".sse4a", PROCESSOR_UNKNOWN,
518 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
519 {".abm", PROCESSOR_UNKNOWN,
520 CpuABM}
e413e4e9
AM		 521};
522
29b0f896
AM		 523const pseudo_typeS md_pseudo_table[] =
524{
525#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
526 {"align", s_align_bytes, 0},
527#else
528 {"align", s_align_ptwo, 0},
529#endif
530 {"arch", set_cpu_arch, 0},
531#ifndef I386COFF
532 {"bss", s_bss, 0},
533#endif
534 {"ffloat", float_cons, 'f'},
535 {"dfloat", float_cons, 'd'},
536 {"tfloat", float_cons, 'x'},
537 {"value", cons, 2},
d182319b 538 {"slong", signed_cons, 4},
29b0f896
AM		 539 {"noopt", s_ignore, 0},
540 {"optim", s_ignore, 0},
541 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
542 {"code16", set_code_flag, CODE_16BIT},
543 {"code32", set_code_flag, CODE_32BIT},
544 {"code64", set_code_flag, CODE_64BIT},
545 {"intel_syntax", set_intel_syntax, 1},
546 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 547#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
548 {"largecomm", handle_large_common, 0},
07a53e5c 549#else
e3bb37b5 550 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 551 {"loc", dwarf2_directive_loc, 0},
552 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 553#endif
6482c264
NC		 554#ifdef TE_PE
555 {"secrel32", pe_directive_secrel, 0},
556#endif
29b0f896
AM		 557 {0, 0, 0}
558};
559
560/* For interface with expression (). */
561extern char *input_line_pointer;
562
563/* Hash table for instruction mnemonic lookup. */
564static struct hash_control *op_hash;
565
566/* Hash table for register lookup. */
567static struct hash_control *reg_hash;
568\f
252b5132 569void
e3bb37b5 570i386_align_code (fragS *fragP, int count)
252b5132 571{
ce8a8b2f
AM		 572 /* Various efficient no-op patterns for aligning code labels.
573 Note: Don't try to assemble the instructions in the comments.
574 0L and 0w are not legal. */
252b5132
RH		 575 static const char f32_1[] =
576 {0x90}; /* nop */
577 static const char f32_2[] =
ccc9c027 578 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 579 static const char f32_3[] =
580 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
581 static const char f32_4[] =
582 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
583 static const char f32_5[] =
584 {0x90, /* nop */
585 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
586 static const char f32_6[] =
587 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
588 static const char f32_7[] =
589 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
590 static const char f32_8[] =
591 {0x90, /* nop */
592 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
593 static const char f32_9[] =
594 {0x89,0xf6, /* movl %esi,%esi */
595 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
596 static const char f32_10[] =
597 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
598 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
599 static const char f32_11[] =
600 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
601 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
602 static const char f32_12[] =
603 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
604 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
605 static const char f32_13[] =
606 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
607 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
608 static const char f32_14[] =
609 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
610 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
611 static const char f32_15[] =
612 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
613 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 614 static const char f16_3[] =
615 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 616 static const char f16_4[] =
617 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
618 static const char f16_5[] =
619 {0x90, /* nop */
620 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
621 static const char f16_6[] =
622 {0x89,0xf6, /* mov %si,%si */
623 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
624 static const char f16_7[] =
625 {0x8d,0x74,0x00, /* lea 0(%si),%si */
626 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
627 static const char f16_8[] =
628 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
629 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
630 static const char *const f32_patt[] = {
631 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
632 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
633 };
634 static const char *const f16_patt[] = {
c3332e24 635 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 636 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
637 };
ccc9c027
L		 638 /* nopl (%[re]ax) */
639 static const char alt_3[] =
640 {0x0f,0x1f,0x00};
641 /* nopl 0(%[re]ax) */
642 static const char alt_4[] =
643 {0x0f,0x1f,0x40,0x00};
644 /* nopl 0(%[re]ax,%[re]ax,1) */
645 static const char alt_5[] =
646 {0x0f,0x1f,0x44,0x00,0x00};
647 /* nopw 0(%[re]ax,%[re]ax,1) */
648 static const char alt_6[] =
649 {0x66,0x0f,0x1f,0x44,0x00,0x00};
650 /* nopl 0L(%[re]ax) */
651 static const char alt_7[] =
652 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
653 /* nopl 0L(%[re]ax,%[re]ax,1) */
654 static const char alt_8[] =
655 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
656 /* nopw 0L(%[re]ax,%[re]ax,1) */
657 static const char alt_9[] =
658 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
659 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
660 static const char alt_10[] =
661 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
662 /* data16
663 nopw %cs:0L(%[re]ax,%[re]ax,1) */
664 static const char alt_long_11[] =
665 {0x66,
666 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
667 /* data16
668 data16
669 nopw %cs:0L(%[re]ax,%[re]ax,1) */
670 static const char alt_long_12[] =
671 {0x66,
672 0x66,
673 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
674 /* data16
675 data16
676 data16
677 nopw %cs:0L(%[re]ax,%[re]ax,1) */
678 static const char alt_long_13[] =
679 {0x66,
680 0x66,
681 0x66,
682 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
683 /* data16
684 data16
685 data16
686 data16
687 nopw %cs:0L(%[re]ax,%[re]ax,1) */
688 static const char alt_long_14[] =
689 {0x66,
690 0x66,
691 0x66,
692 0x66,
693 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
694 /* data16
695 data16
696 data16
697 data16
698 data16
699 nopw %cs:0L(%[re]ax,%[re]ax,1) */
700 static const char alt_long_15[] =
701 {0x66,
702 0x66,
703 0x66,
704 0x66,
705 0x66,
706 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
707 /* nopl 0(%[re]ax,%[re]ax,1)
708 nopw 0(%[re]ax,%[re]ax,1) */
709 static const char alt_short_11[] =
710 {0x0f,0x1f,0x44,0x00,0x00,
711 0x66,0x0f,0x1f,0x44,0x00,0x00};
712 /* nopw 0(%[re]ax,%[re]ax,1)
713 nopw 0(%[re]ax,%[re]ax,1) */
714 static const char alt_short_12[] =
715 {0x66,0x0f,0x1f,0x44,0x00,0x00,
716 0x66,0x0f,0x1f,0x44,0x00,0x00};
717 /* nopw 0(%[re]ax,%[re]ax,1)
718 nopl 0L(%[re]ax) */
719 static const char alt_short_13[] =
720 {0x66,0x0f,0x1f,0x44,0x00,0x00,
721 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
722 /* nopl 0L(%[re]ax)
723 nopl 0L(%[re]ax) */
724 static const char alt_short_14[] =
725 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
726 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
727 /* nopl 0L(%[re]ax)
728 nopl 0L(%[re]ax,%[re]ax,1) */
729 static const char alt_short_15[] =
730 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
731 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
732 static const char *const alt_short_patt[] = {
733 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
734 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
735 alt_short_14, alt_short_15
736 };
737 static const char *const alt_long_patt[] = {
738 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
739 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
740 alt_long_14, alt_long_15
741 };
252b5132 742
33fef721
JH		 743 if (count <= 0 || count > 15)
744 return;
3e73aa7c 745
ccc9c027
L		 746 /* We need to decide which NOP sequence to use for 32bit and
747 64bit. When -mtune= is used:
4eed87de 748
ccc9c027
L		 749 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
750 f32_patt will be used.
4eed87de
AM		 751 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with
752 0x66 prefix will be used.
ef05d495 753 3. For PROCESSOR_CORE2, alt_long_patt will be used.
ccc9c027 754 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
ef05d495 755 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
ccc9c027
L		 756 and PROCESSOR_GENERIC64, alt_short_patt will be used.
757
758 When -mtune= isn't used, alt_short_patt will be used if
759 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
760
761 When -march= or .arch is used, we can't use anything beyond
762 cpu_arch_isa_flags. */
763
764 if (flag_code == CODE_16BIT)
765 {
766 memcpy (fragP->fr_literal + fragP->fr_fix,
767 f16_patt[count - 1], count);
768 if (count > 8)
769 /* Adjust jump offset. */
770 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
771 }
772 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
252b5132 773 {
33fef721
JH		 774 int i;
775 int nnops = (count + 3) / 4;
776 int len = count / nnops;
777 int remains = count - nnops * len;
778 int pos = 0;
779
ccc9c027 780 /* The recommended way to pad 64bit code is to use NOPs preceded
4eed87de 781 by maximally four 0x66 prefixes. Balance the size of nops. */
33fef721 782 for (i = 0; i < remains; i++)
252b5132 783 {
33fef721
JH		 784 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
785 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
786 pos += len + 1;
787 }
788 for (; i < nnops; i++)
789 {
790 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
791 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
792 pos += len;
252b5132 793 }
252b5132 794 }
33fef721 795 else
ccc9c027
L		 796 {
797 const char *const *patt = NULL;
798
799 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
800 {
801 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
802 switch (cpu_arch_tune)
803 {
804 case PROCESSOR_UNKNOWN:
805 /* We use cpu_arch_isa_flags to check if we SHOULD
806 optimize for Cpu686. */
807 if ((cpu_arch_isa_flags & Cpu686) != 0)
808 patt = alt_short_patt;
809 else
810 patt = f32_patt;
811 break;
ef05d495 812 case PROCESSOR_CORE2:
ccc9c027
L		 813 patt = alt_long_patt;
814 break;
815 case PROCESSOR_PENTIUMPRO:
816 case PROCESSOR_PENTIUM4:
817 case PROCESSOR_NOCONA:
ef05d495 818 case PROCESSOR_CORE:
ccc9c027
L		 819 case PROCESSOR_K6:
820 case PROCESSOR_ATHLON:
821 case PROCESSOR_K8:
822 case PROCESSOR_GENERIC64:
4eed87de 823 case PROCESSOR_AMDFAM10:
ccc9c027
L		 824 patt = alt_short_patt;
825 break;
826 case PROCESSOR_I486:
827 case PROCESSOR_PENTIUM:
828 case PROCESSOR_GENERIC32:
829 patt = f32_patt;
830 break;
4eed87de 831 }
ccc9c027
L		 832 }
833 else
834 {
835 switch (cpu_arch_tune)
836 {
837 case PROCESSOR_UNKNOWN:
838 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
839 PROCESSOR_UNKNOWN. */
840 abort ();
841 break;
842
843 case PROCESSOR_I486:
844 case PROCESSOR_PENTIUM:
845 case PROCESSOR_PENTIUMPRO:
846 case PROCESSOR_PENTIUM4:
847 case PROCESSOR_NOCONA:
ef05d495 848 case PROCESSOR_CORE:
ccc9c027
L		 849 case PROCESSOR_K6:
850 case PROCESSOR_ATHLON:
851 case PROCESSOR_K8:
4eed87de 852 case PROCESSOR_AMDFAM10:
ccc9c027
L		 853 case PROCESSOR_GENERIC32:
854 /* We use cpu_arch_isa_flags to check if we CAN optimize
855 for Cpu686. */
856 if ((cpu_arch_isa_flags & Cpu686) != 0)
857 patt = alt_short_patt;
858 else
859 patt = f32_patt;
860 break;
ef05d495 861 case PROCESSOR_CORE2:
ccc9c027
L		 862 if ((cpu_arch_isa_flags & Cpu686) != 0)
863 patt = alt_long_patt;
864 else
865 patt = f32_patt;
866 break;
867 case PROCESSOR_GENERIC64:
868 patt = alt_short_patt;
869 break;
4eed87de 870 }
ccc9c027
L		 871 }
872
33fef721 873 memcpy (fragP->fr_literal + fragP->fr_fix,
ccc9c027
L		 874 patt[count - 1], count);
875 }
33fef721 876 fragP->fr_var = count;
252b5132
RH		 877}
878
252b5132 879static INLINE unsigned int
e3bb37b5 880mode_from_disp_size (unsigned int t)
252b5132 881{
3e73aa7c 882 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 883}
884
885static INLINE int
e3bb37b5 886fits_in_signed_byte (offsetT num)
252b5132
RH		 887{
888 return (num >= -128) && (num <= 127);
47926f60 889}
252b5132
RH		 890
891static INLINE int
e3bb37b5 892fits_in_unsigned_byte (offsetT num)
252b5132
RH		 893{
894 return (num & 0xff) == num;
47926f60 895}
252b5132
RH		 896
897static INLINE int
e3bb37b5 898fits_in_unsigned_word (offsetT num)
252b5132
RH		 899{
900 return (num & 0xffff) == num;
47926f60 901}
252b5132
RH		 902
903static INLINE int
e3bb37b5 904fits_in_signed_word (offsetT num)
252b5132
RH		 905{
906 return (-32768 <= num) && (num <= 32767);
47926f60 907}
2a962e6d 908
3e73aa7c 909static INLINE int
e3bb37b5 910fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 911{
912#ifndef BFD64
913 return 1;
914#else
915 return (!(((offsetT) -1 << 31) & num)
916 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
917#endif
918} /* fits_in_signed_long() */
2a962e6d 919
3e73aa7c 920static INLINE int
e3bb37b5 921fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 922{
923#ifndef BFD64
924 return 1;
925#else
926 return (num & (((offsetT) 2 << 31) - 1)) == num;
927#endif
928} /* fits_in_unsigned_long() */
252b5132 929
1509aa9a 930static unsigned int
e3bb37b5 931smallest_imm_type (offsetT num)
252b5132 932{
d32cad65 933 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 934 {
935 /* This code is disabled on the 486 because all the Imm1 forms
936 in the opcode table are slower on the i486. They're the
937 versions with the implicitly specified single-position
938 displacement, which has another syntax if you really want to
939 use that form. */
940 if (num == 1)
3e73aa7c 941 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 942 }
252b5132 943 return (fits_in_signed_byte (num)
3e73aa7c 944 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 945 : fits_in_unsigned_byte (num)
3e73aa7c 946 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 947 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 948 ? (Imm16 | Imm32 | Imm32S | Imm64)
949 : fits_in_signed_long (num)
950 ? (Imm32 | Imm32S | Imm64)
951 : fits_in_unsigned_long (num)
952 ? (Imm32 | Imm64)
953 : Imm64);
47926f60 954}
252b5132 955
847f7ad4 956static offsetT
e3bb37b5 957offset_in_range (offsetT val, int size)
847f7ad4 958{
508866be 959 addressT mask;
ba2adb93 960
847f7ad4
AM		 961 switch (size)
962 {
508866be
L		 963 case 1: mask = ((addressT) 1 << 8) - 1; break;
964 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 965 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 966#ifdef BFD64
967 case 8: mask = ((addressT) 2 << 63) - 1; break;
968#endif
47926f60 969 default: abort ();
847f7ad4
AM		 970 }
971
ba2adb93 972 /* If BFD64, sign extend val. */
3e73aa7c
JH		 973 if (!use_rela_relocations)
974 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
975 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 976
47926f60 977 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 978 {
979 char buf1[40], buf2[40];
980
981 sprint_value (buf1, val);
982 sprint_value (buf2, val & mask);
983 as_warn (_("%s shortened to %s"), buf1, buf2);
984 }
985 return val & mask;
986}
987
252b5132
RH		 988/* Returns 0 if attempting to add a prefix where one from the same
989 class already exists, 1 if non rep/repne added, 2 if rep/repne
990 added. */
991static int
e3bb37b5 992add_prefix (unsigned int prefix)
252b5132
RH		 993{
994 int ret = 1;
b1905489 995 unsigned int q;
252b5132 996
29b0f896
AM		 997 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
998 && flag_code == CODE_64BIT)
b1905489 999 {
161a04f6
L		 1000 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1001 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1002 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1003 ret = 0;
1004 q = REX_PREFIX;
1005 }
3e73aa7c 1006 else
b1905489
JB		 1007 {
1008 switch (prefix)
1009 {
1010 default:
1011 abort ();
1012
1013 case CS_PREFIX_OPCODE:
1014 case DS_PREFIX_OPCODE:
1015 case ES_PREFIX_OPCODE:
1016 case FS_PREFIX_OPCODE:
1017 case GS_PREFIX_OPCODE:
1018 case SS_PREFIX_OPCODE:
1019 q = SEG_PREFIX;
1020 break;
1021
1022 case REPNE_PREFIX_OPCODE:
1023 case REPE_PREFIX_OPCODE:
1024 ret = 2;
1025 /* fall thru */
1026 case LOCK_PREFIX_OPCODE:
1027 q = LOCKREP_PREFIX;
1028 break;
1029
1030 case FWAIT_OPCODE:
1031 q = WAIT_PREFIX;
1032 break;
1033
1034 case ADDR_PREFIX_OPCODE:
1035 q = ADDR_PREFIX;
1036 break;
1037
1038 case DATA_PREFIX_OPCODE:
1039 q = DATA_PREFIX;
1040 break;
1041 }
1042 if (i.prefix[q] != 0)
1043 ret = 0;
1044 }
252b5132 1045
b1905489 1046 if (ret)
252b5132 1047 {
b1905489
JB		 1048 if (!i.prefix[q])
1049 ++i.prefixes;
1050 i.prefix[q] |= prefix;
252b5132 1051 }
b1905489
JB		 1052 else
1053 as_bad (_("same type of prefix used twice"));
252b5132 1054
252b5132
RH		 1055 return ret;
1056}
1057
1058static void
e3bb37b5 1059set_code_flag (int value)
eecb386c 1060{
3e73aa7c
JH		 1061 flag_code = value;
1062 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1063 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1064 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1065 {
1066 as_bad (_("64bit mode not supported on this CPU."));
1067 }
1068 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1069 {
1070 as_bad (_("32bit mode not supported on this CPU."));
1071 }
eecb386c
AM		 1072 stackop_size = '\0';
1073}
1074
1075static void
e3bb37b5 1076set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1077{
3e73aa7c
JH		 1078 flag_code = new_code_flag;
1079 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1080 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 1081 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1082}
1083
1084static void
e3bb37b5 1085set_intel_syntax (int syntax_flag)
252b5132
RH		 1086{
1087 /* Find out if register prefixing is specified. */
1088 int ask_naked_reg = 0;
1089
1090 SKIP_WHITESPACE ();
29b0f896 1091 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1092 {
1093 char *string = input_line_pointer;
1094 int e = get_symbol_end ();
1095
47926f60 1096 if (strcmp (string, "prefix") == 0)
252b5132 1097 ask_naked_reg = 1;
47926f60 1098 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1099 ask_naked_reg = -1;
1100 else
d0b47220 1101 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1102 *input_line_pointer = e;
1103 }
1104 demand_empty_rest_of_line ();
c3332e24 1105
252b5132
RH		 1106 intel_syntax = syntax_flag;
1107
1108 if (ask_naked_reg == 0)
f86103b7
AM		 1109 allow_naked_reg = (intel_syntax
1110 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1111 else
1112 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1113
e4a3b5a4 1114 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1115 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1116 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1117}
1118
e413e4e9 1119static void
e3bb37b5 1120set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1121{
47926f60 1122 SKIP_WHITESPACE ();
e413e4e9 1123
29b0f896 1124 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1125 {
1126 char *string = input_line_pointer;
1127 int e = get_symbol_end ();
9103f4f4 1128 unsigned int i;
e413e4e9 1129
9103f4f4 1130 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1131 {
1132 if (strcmp (string, cpu_arch[i].name) == 0)
1133 {
5c6af06e
JB		 1134 if (*string != '.')
1135 {
1136 cpu_arch_name = cpu_arch[i].name;
1137 cpu_sub_arch_name = NULL;
1138 cpu_arch_flags = (cpu_arch[i].flags
4eed87de
AM		 1139 | (flag_code == CODE_64BIT
1140 ? Cpu64 : CpuNo64));
ccc9c027 1141 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1142 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1143 if (!cpu_arch_tune_set)
1144 {
1145 cpu_arch_tune = cpu_arch_isa;
1146 cpu_arch_tune_flags = cpu_arch_isa_flags;
1147 }
5c6af06e
JB		 1148 break;
1149 }
1150 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1151 {
1152 cpu_sub_arch_name = cpu_arch[i].name;
1153 cpu_arch_flags |= cpu_arch[i].flags;
1154 }
1155 *input_line_pointer = e;
1156 demand_empty_rest_of_line ();
1157 return;
e413e4e9
AM		 1158 }
1159 }
9103f4f4 1160 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1161 as_bad (_("no such architecture: `%s'"), string);
1162
1163 *input_line_pointer = e;
1164 }
1165 else
1166 as_bad (_("missing cpu architecture"));
1167
fddf5b5b
AM		 1168 no_cond_jump_promotion = 0;
1169 if (*input_line_pointer == ','
29b0f896 1170 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1171 {
1172 char *string = ++input_line_pointer;
1173 int e = get_symbol_end ();
1174
1175 if (strcmp (string, "nojumps") == 0)
1176 no_cond_jump_promotion = 1;
1177 else if (strcmp (string, "jumps") == 0)
1178 ;
1179 else
1180 as_bad (_("no such architecture modifier: `%s'"), string);
1181
1182 *input_line_pointer = e;
1183 }
1184
e413e4e9
AM		 1185 demand_empty_rest_of_line ();
1186}
1187
b9d79e03
JH		 1188unsigned long
1189i386_mach ()
1190{
1191 if (!strcmp (default_arch, "x86_64"))
1192 return bfd_mach_x86_64;
1193 else if (!strcmp (default_arch, "i386"))
1194 return bfd_mach_i386_i386;
1195 else
1196 as_fatal (_("Unknown architecture"));
1197}
b9d79e03 1198\f
252b5132
RH		 1199void
1200md_begin ()
1201{
1202 const char *hash_err;
1203
47926f60 1204 /* Initialize op_hash hash table. */
252b5132
RH		 1205 op_hash = hash_new ();
1206
1207 {
29b0f896
AM		 1208 const template *optab;
1209 templates *core_optab;
252b5132 1210
47926f60
KH		 1211 /* Setup for loop. */
1212 optab = i386_optab;
252b5132
RH		 1213 core_optab = (templates *) xmalloc (sizeof (templates));
1214 core_optab->start = optab;
1215
1216 while (1)
1217 {
1218 ++optab;
1219 if (optab->name == NULL
1220 || strcmp (optab->name, (optab - 1)->name) != 0)
1221 {
1222 /* different name --> ship out current template list;
47926f60 1223 add to hash table; & begin anew. */
252b5132
RH		 1224 core_optab->end = optab;
1225 hash_err = hash_insert (op_hash,
1226 (optab - 1)->name,
1227 (PTR) core_optab);
1228 if (hash_err)
1229 {
252b5132
RH		 1230 as_fatal (_("Internal Error: Can't hash %s: %s"),
1231 (optab - 1)->name,
1232 hash_err);
1233 }
1234 if (optab->name == NULL)
1235 break;
1236 core_optab = (templates *) xmalloc (sizeof (templates));
1237 core_optab->start = optab;
1238 }
1239 }
1240 }
1241
47926f60 1242 /* Initialize reg_hash hash table. */
252b5132
RH		 1243 reg_hash = hash_new ();
1244 {
29b0f896 1245 const reg_entry *regtab;
c3fe08fa 1246 unsigned int regtab_size = i386_regtab_size;
252b5132 1247
c3fe08fa 1248 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1249 {
1250 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1251 if (hash_err)
3e73aa7c
JH		 1252 as_fatal (_("Internal Error: Can't hash %s: %s"),
1253 regtab->reg_name,
1254 hash_err);
252b5132
RH		 1255 }
1256 }
1257
47926f60 1258 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1259 {
29b0f896
AM		 1260 int c;
1261 char *p;
252b5132
RH		 1262
1263 for (c = 0; c < 256; c++)
1264 {
3882b010 1265 if (ISDIGIT (c))
252b5132
RH		 1266 {
1267 digit_chars[c] = c;
1268 mnemonic_chars[c] = c;
1269 register_chars[c] = c;
1270 operand_chars[c] = c;
1271 }
3882b010 1272 else if (ISLOWER (c))
252b5132
RH		 1273 {
1274 mnemonic_chars[c] = c;
1275 register_chars[c] = c;
1276 operand_chars[c] = c;
1277 }
3882b010 1278 else if (ISUPPER (c))
252b5132 1279 {
3882b010 1280 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1281 register_chars[c] = mnemonic_chars[c];
1282 operand_chars[c] = c;
1283 }
1284
3882b010 1285 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1286 identifier_chars[c] = c;
1287 else if (c >= 128)
1288 {
1289 identifier_chars[c] = c;
1290 operand_chars[c] = c;
1291 }
1292 }
1293
1294#ifdef LEX_AT
1295 identifier_chars['@'] = '@';
32137342
NC		 1296#endif
1297#ifdef LEX_QM
1298 identifier_chars['?'] = '?';
1299 operand_chars['?'] = '?';
252b5132 1300#endif
252b5132 1301 digit_chars['-'] = '-';
791fe849 1302 mnemonic_chars['-'] = '-';
0003779b 1303 mnemonic_chars['.'] = '.';
252b5132
RH		 1304 identifier_chars['_'] = '_';
1305 identifier_chars['.'] = '.';
1306
1307 for (p = operand_special_chars; *p != '\0'; p++)
1308 operand_chars[(unsigned char) *p] = *p;
1309 }
1310
1311#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1312 if (IS_ELF)
252b5132
RH		 1313 {
1314 record_alignment (text_section, 2);
1315 record_alignment (data_section, 2);
1316 record_alignment (bss_section, 2);
1317 }
1318#endif
a4447b93
RH		 1319
1320 if (flag_code == CODE_64BIT)
1321 {
1322 x86_dwarf2_return_column = 16;
1323 x86_cie_data_alignment = -8;
1324 }
1325 else
1326 {
1327 x86_dwarf2_return_column = 8;
1328 x86_cie_data_alignment = -4;
1329 }
252b5132
RH		 1330}
1331
1332void
e3bb37b5 1333i386_print_statistics (FILE *file)
252b5132
RH		 1334{
1335 hash_print_statistics (file, "i386 opcode", op_hash);
1336 hash_print_statistics (file, "i386 register", reg_hash);
1337}
1338\f
252b5132
RH		 1339#ifdef DEBUG386
1340
ce8a8b2f 1341/* Debugging routines for md_assemble. */
e3bb37b5
L		 1342static void pte (template *);
1343static void pt (unsigned int);
1344static void pe (expressionS *);
1345static void ps (symbolS *);
252b5132
RH		 1346
1347static void
e3bb37b5 1348pi (char *line, i386_insn *x)
252b5132 1349{
09f131f2 1350 unsigned int i;
252b5132
RH		 1351
1352 fprintf (stdout, "%s: template ", line);
1353 pte (&x->tm);
09f131f2
JH		 1354 fprintf (stdout, " address: base %s index %s scale %x\n",
1355 x->base_reg ? x->base_reg->reg_name : "none",
1356 x->index_reg ? x->index_reg->reg_name : "none",
1357 x->log2_scale_factor);
1358 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1359 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1360 fprintf (stdout, " sib: base %x index %x scale %x\n",
1361 x->sib.base, x->sib.index, x->sib.scale);
1362 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 1363 (x->rex & REX_W) != 0,
1364 (x->rex & REX_R) != 0,
1365 (x->rex & REX_X) != 0,
1366 (x->rex & REX_B) != 0);
252b5132
RH		 1367 for (i = 0; i < x->operands; i++)
1368 {
1369 fprintf (stdout, " #%d: ", i + 1);
1370 pt (x->types[i]);
1371 fprintf (stdout, "\n");
1372 if (x->types[i]
3f4438ab 1373 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1374 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1375 if (x->types[i] & Imm)
520dc8e8 1376 pe (x->op[i].imms);
252b5132 1377 if (x->types[i] & Disp)
520dc8e8 1378 pe (x->op[i].disps);
252b5132
RH		 1379 }
1380}
1381
1382static void
e3bb37b5 1383pte (template *t)
252b5132 1384{
09f131f2 1385 unsigned int i;
252b5132 1386 fprintf (stdout, " %d operands ", t->operands);
47926f60 1387 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1388 if (t->extension_opcode != None)
1389 fprintf (stdout, "ext %x ", t->extension_opcode);
1390 if (t->opcode_modifier & D)
1391 fprintf (stdout, "D");
1392 if (t->opcode_modifier & W)
1393 fprintf (stdout, "W");
1394 fprintf (stdout, "\n");
1395 for (i = 0; i < t->operands; i++)
1396 {
1397 fprintf (stdout, " #%d type ", i + 1);
1398 pt (t->operand_types[i]);
1399 fprintf (stdout, "\n");
1400 }
1401}
1402
1403static void
e3bb37b5 1404pe (expressionS *e)
252b5132 1405{
24eab124 1406 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1407 fprintf (stdout, " add_number %ld (%lx)\n",
1408 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1409 if (e->X_add_symbol)
1410 {
1411 fprintf (stdout, " add_symbol ");
1412 ps (e->X_add_symbol);
1413 fprintf (stdout, "\n");
1414 }
1415 if (e->X_op_symbol)
1416 {
1417 fprintf (stdout, " op_symbol ");
1418 ps (e->X_op_symbol);
1419 fprintf (stdout, "\n");
1420 }
1421}
1422
1423static void
e3bb37b5 1424ps (symbolS *s)
252b5132
RH		 1425{
1426 fprintf (stdout, "%s type %s%s",
1427 S_GET_NAME (s),
1428 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1429 segment_name (S_GET_SEGMENT (s)));
1430}
1431
7b81dfbb 1432static struct type_name
252b5132
RH		 1433 {
1434 unsigned int mask;
1435 char *tname;
1436 }
7b81dfbb 1437const type_names[] =
252b5132
RH		 1438{
1439 { Reg8, "r8" },
1440 { Reg16, "r16" },
1441 { Reg32, "r32" },
09f131f2 1442 { Reg64, "r64" },
252b5132
RH		 1443 { Imm8, "i8" },
1444 { Imm8S, "i8s" },
1445 { Imm16, "i16" },
1446 { Imm32, "i32" },
09f131f2
JH		 1447 { Imm32S, "i32s" },
1448 { Imm64, "i64" },
252b5132
RH		 1449 { Imm1, "i1" },
1450 { BaseIndex, "BaseIndex" },
1451 { Disp8, "d8" },
1452 { Disp16, "d16" },
1453 { Disp32, "d32" },
09f131f2
JH		 1454 { Disp32S, "d32s" },
1455 { Disp64, "d64" },
252b5132
RH		 1456 { InOutPortReg, "InOutPortReg" },
1457 { ShiftCount, "ShiftCount" },
1458 { Control, "control reg" },
1459 { Test, "test reg" },
1460 { Debug, "debug reg" },
1461 { FloatReg, "FReg" },
1462 { FloatAcc, "FAcc" },
1463 { SReg2, "SReg2" },
1464 { SReg3, "SReg3" },
1465 { Acc, "Acc" },
1466 { JumpAbsolute, "Jump Absolute" },
1467 { RegMMX, "rMMX" },
3f4438ab 1468 { RegXMM, "rXMM" },
252b5132
RH		 1469 { EsSeg, "es" },
1470 { 0, "" }
1471};
1472
1473static void
1474pt (t)
1475 unsigned int t;
1476{
29b0f896 1477 const struct type_name *ty;
252b5132 1478
09f131f2
JH		 1479 for (ty = type_names; ty->mask; ty++)
1480 if (t & ty->mask)
1481 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1482 fflush (stdout);
1483}
1484
1485#endif /* DEBUG386 */
1486\f
252b5132 1487static bfd_reloc_code_real_type
3956db08 1488reloc (unsigned int size,
64e74474
AM		 1489 int pcrel,
1490 int sign,
1491 bfd_reloc_code_real_type other)
252b5132 1492{
47926f60 1493 if (other != NO_RELOC)
3956db08
JB		 1494 {
1495 reloc_howto_type *reloc;
1496
1497 if (size == 8)
1498 switch (other)
1499 {
64e74474
AM		 1500 case BFD_RELOC_X86_64_GOT32:
1501 return BFD_RELOC_X86_64_GOT64;
1502 break;
1503 case BFD_RELOC_X86_64_PLTOFF64:
1504 return BFD_RELOC_X86_64_PLTOFF64;
1505 break;
1506 case BFD_RELOC_X86_64_GOTPC32:
1507 other = BFD_RELOC_X86_64_GOTPC64;
1508 break;
1509 case BFD_RELOC_X86_64_GOTPCREL:
1510 other = BFD_RELOC_X86_64_GOTPCREL64;
1511 break;
1512 case BFD_RELOC_X86_64_TPOFF32:
1513 other = BFD_RELOC_X86_64_TPOFF64;
1514 break;
1515 case BFD_RELOC_X86_64_DTPOFF32:
1516 other = BFD_RELOC_X86_64_DTPOFF64;
1517 break;
1518 default:
1519 break;
3956db08 1520 }
e05278af
JB		 1521
1522 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1523 if (size == 4 && flag_code != CODE_64BIT)
1524 sign = -1;
1525
3956db08
JB		 1526 reloc = bfd_reloc_type_lookup (stdoutput, other);
1527 if (!reloc)
1528 as_bad (_("unknown relocation (%u)"), other);
1529 else if (size != bfd_get_reloc_size (reloc))
1530 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1531 bfd_get_reloc_size (reloc),
1532 size);
1533 else if (pcrel && !reloc->pc_relative)
1534 as_bad (_("non-pc-relative relocation for pc-relative field"));
1535 else if ((reloc->complain_on_overflow == complain_overflow_signed
1536 && !sign)
1537 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1538 && sign > 0))
3956db08
JB		 1539 as_bad (_("relocated field and relocation type differ in signedness"));
1540 else
1541 return other;
1542 return NO_RELOC;
1543 }
252b5132
RH		 1544
1545 if (pcrel)
1546 {
3e73aa7c 1547 if (!sign)
3956db08 1548 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1549 switch (size)
1550 {
1551 case 1: return BFD_RELOC_8_PCREL;
1552 case 2: return BFD_RELOC_16_PCREL;
1553 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1554 case 8: return BFD_RELOC_64_PCREL;
252b5132 1555 }
3956db08 1556 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1557 }
1558 else
1559 {
3956db08 1560 if (sign > 0)
e5cb08ac 1561 switch (size)
3e73aa7c
JH		 1562 {
1563 case 4: return BFD_RELOC_X86_64_32S;
1564 }
1565 else
1566 switch (size)
1567 {
1568 case 1: return BFD_RELOC_8;
1569 case 2: return BFD_RELOC_16;
1570 case 4: return BFD_RELOC_32;
1571 case 8: return BFD_RELOC_64;
1572 }
3956db08
JB		 1573 as_bad (_("cannot do %s %u byte relocation"),
1574 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1575 }
1576
bfb32b52 1577 abort ();
252b5132
RH		 1578 return BFD_RELOC_NONE;
1579}
1580
47926f60
KH		 1581/* Here we decide which fixups can be adjusted to make them relative to
1582 the beginning of the section instead of the symbol. Basically we need
1583 to make sure that the dynamic relocations are done correctly, so in
1584 some cases we force the original symbol to be used. */
1585
252b5132 1586int
e3bb37b5 1587tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 1588{
6d249963 1589#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1590 if (!IS_ELF)
31312f95
AM		 1591 return 1;
1592
a161fe53
AM		 1593 /* Don't adjust pc-relative references to merge sections in 64-bit
1594 mode. */
1595 if (use_rela_relocations
1596 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1597 && fixP->fx_pcrel)
252b5132 1598 return 0;
31312f95 1599
8d01d9a9
AJ		 1600 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1601 and changed later by validate_fix. */
1602 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1603 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1604 return 0;
1605
ce8a8b2f 1606 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1607 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1608 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1609 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1610 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1611 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1612 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1613 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1614 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1615 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1616 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1617 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1618 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1619 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1620 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1621 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1622 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1623 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1624 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1625 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1626 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1627 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1628 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1629 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1630 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1631 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1632 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1633 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1634 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1635 return 0;
31312f95 1636#endif
252b5132
RH		 1637 return 1;
1638}
252b5132 1639
b4cac588 1640static int
e3bb37b5 1641intel_float_operand (const char *mnemonic)
252b5132 1642{
9306ca4a
JB		 1643 /* Note that the value returned is meaningful only for opcodes with (memory)
1644 operands, hence the code here is free to improperly handle opcodes that
1645 have no operands (for better performance and smaller code). */
1646
1647 if (mnemonic[0] != 'f')
1648 return 0; /* non-math */
1649
1650 switch (mnemonic[1])
1651 {
1652 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1653 the fs segment override prefix not currently handled because no
1654 call path can make opcodes without operands get here */
1655 case 'i':
1656 return 2 /* integer op */;
1657 case 'l':
1658 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1659 return 3; /* fldcw/fldenv */
1660 break;
1661 case 'n':
1662 if (mnemonic[2] != 'o' /* fnop */)
1663 return 3; /* non-waiting control op */
1664 break;
1665 case 'r':
1666 if (mnemonic[2] == 's')
1667 return 3; /* frstor/frstpm */
1668 break;
1669 case 's':
1670 if (mnemonic[2] == 'a')
1671 return 3; /* fsave */
1672 if (mnemonic[2] == 't')
1673 {
1674 switch (mnemonic[3])
1675 {
1676 case 'c': /* fstcw */
1677 case 'd': /* fstdw */
1678 case 'e': /* fstenv */
1679 case 's': /* fsts[gw] */
1680 return 3;
1681 }
1682 }
1683 break;
1684 case 'x':
1685 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1686 return 0; /* fxsave/fxrstor are not really math ops */
1687 break;
1688 }
252b5132 1689
9306ca4a 1690 return 1;
252b5132
RH		 1691}
1692
1693/* This is the guts of the machine-dependent assembler. LINE points to a
1694 machine dependent instruction. This function is supposed to emit
1695 the frags/bytes it assembles to. */
1696
1697void
1698md_assemble (line)
1699 char *line;
1700{
252b5132 1701 int j;
252b5132
RH		 1702 char mnemonic[MAX_MNEM_SIZE];
1703
47926f60 1704 /* Initialize globals. */
252b5132
RH		 1705 memset (&i, '\0', sizeof (i));
1706 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1707 i.reloc[j] = NO_RELOC;
252b5132
RH		 1708 memset (disp_expressions, '\0', sizeof (disp_expressions));
1709 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1710 save_stack_p = save_stack;
252b5132
RH		 1711
1712 /* First parse an instruction mnemonic & call i386_operand for the operands.
1713 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1714 start of a (possibly prefixed) mnemonic. */
252b5132 1715
29b0f896
AM		 1716 line = parse_insn (line, mnemonic);
1717 if (line == NULL)
1718 return;
252b5132 1719
29b0f896
AM		 1720 line = parse_operands (line, mnemonic);
1721 if (line == NULL)
1722 return;
252b5132 1723
4eed87de 1724 /* The order of the immediates should be reversed
050dfa73 1725 for 2 immediates extrq and insertq instructions */
4d456e3d
L		 1726 if ((i.imm_operands == 2)
1727 && ((strcmp (mnemonic, "extrq") == 0)
1728 || (strcmp (mnemonic, "insertq") == 0)))
050dfa73 1729 {
4eed87de
AM		 1730 swap_2_operands (0, 1);
1731 /* "extrq" and insertq" are the only two instructions whose operands
050dfa73
MM		 1732 have to be reversed even though they have two immediate operands.
1733 */
1734 if (intel_syntax)
1735 swap_operands ();
1736 }
1737
29b0f896
AM		 1738 /* Now we've parsed the mnemonic into a set of templates, and have the
1739 operands at hand. */
1740
1741 /* All intel opcodes have reversed operands except for "bound" and
1742 "enter". We also don't reverse intersegment "jmp" and "call"
1743 instructions with 2 immediate operands so that the immediate segment
050dfa73 1744 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 1745 if (intel_syntax
1746 && i.operands > 1
29b0f896 1747 && (strcmp (mnemonic, "bound") != 0)
30123838 1748 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1749 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1750 swap_operands ();
1751
1752 if (i.imm_operands)
1753 optimize_imm ();
1754
b300c311
L		 1755 /* Don't optimize displacement for movabs since it only takes 64bit
1756 displacement. */
1757 if (i.disp_operands
1758 && (flag_code != CODE_64BIT
1759 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1760 optimize_disp ();
1761
1762 /* Next, we find a template that matches the given insn,
1763 making sure the overlap of the given operands types is consistent
1764 with the template operand types. */
252b5132 1765
29b0f896
AM		 1766 if (!match_template ())
1767 return;
252b5132 1768
cd61ebfe
AM		 1769 if (intel_syntax)
1770 {
1771 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1772 if (SYSV386_COMPAT
1773 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
8a2ed489 1774 i.tm.base_opcode ^= Opcode_FloatR;
cd61ebfe
AM		 1775
1776 /* Zap movzx and movsx suffix. The suffix may have been set from
1777 "word ptr" or "byte ptr" on the source operand, but we'll use
1778 the suffix later to choose the destination register. */
1779 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1780 {
1781 if (i.reg_operands < 2
1782 && !i.suffix
1783 && (~i.tm.opcode_modifier
1784 & (No_bSuf
1785 | No_wSuf
1786 | No_lSuf
1787 | No_sSuf
1788 | No_xSuf
1789 | No_qSuf)))
1790 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1791
1792 i.suffix = 0;
1793 }
cd61ebfe 1794 }
24eab124 1795
29b0f896
AM		 1796 if (i.tm.opcode_modifier & FWait)
1797 if (!add_prefix (FWAIT_OPCODE))
1798 return;
252b5132 1799
29b0f896
AM		 1800 /* Check string instruction segment overrides. */
1801 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1802 {
1803 if (!check_string ())
5dd0794d 1804 return;
29b0f896 1805 }
5dd0794d 1806
29b0f896
AM		 1807 if (!process_suffix ())
1808 return;
e413e4e9 1809
29b0f896
AM		 1810 /* Make still unresolved immediate matches conform to size of immediate
1811 given in i.suffix. */
1812 if (!finalize_imm ())
1813 return;
252b5132 1814
29b0f896
AM		 1815 if (i.types[0] & Imm1)
1816 i.imm_operands = 0; /* kludge for shift insns. */
1817 if (i.types[0] & ImplicitRegister)
1818 i.reg_operands--;
1819 if (i.types[1] & ImplicitRegister)
1820 i.reg_operands--;
1821 if (i.types[2] & ImplicitRegister)
1822 i.reg_operands--;
252b5132 1823
29b0f896
AM		 1824 if (i.tm.opcode_modifier & ImmExt)
1825 {
02fc3089
L		 1826 expressionS *exp;
1827
b7d9ef37 1828 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
ca164297 1829 {
b7d9ef37 1830 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 1831 operands with an opcode suffix which is coded in the same
1832 place as an 8-bit immediate field would be. Here we check
1833 those operands and remove them afterwards. */
1834 unsigned int x;
1835
a4622f40 1836 for (x = 0; x < i.operands; x++)
ca164297 1837 if (i.op[x].regs->reg_num != x)
a540244d
L		 1838 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1839 register_prefix,
1840 i.op[x].regs->reg_name,
1841 x + 1,
1842 i.tm.name);
ca164297
L		 1843 i.operands = 0;
1844 }
1845
29b0f896
AM		 1846 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1847 opcode suffix which is coded in the same place as an 8-bit
1848 immediate field would be. Here we fake an 8-bit immediate
1849 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1850
29b0f896 1851 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1852
29b0f896
AM		 1853 exp = &im_expressions[i.imm_operands++];
1854 i.op[i.operands].imms = exp;
1855 i.types[i.operands++] = Imm8;
1856 exp->X_op = O_constant;
1857 exp->X_add_number = i.tm.extension_opcode;
1858 i.tm.extension_opcode = None;
1859 }
252b5132 1860
29b0f896
AM		 1861 /* For insns with operands there are more diddles to do to the opcode. */
1862 if (i.operands)
1863 {
1864 if (!process_operands ())
1865 return;
1866 }
1867 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1868 {
1869 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1870 as_warn (_("translating to `%sp'"), i.tm.name);
1871 }
252b5132 1872
29b0f896
AM		 1873 /* Handle conversion of 'int $3' --> special int3 insn. */
1874 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1875 {
1876 i.tm.base_opcode = INT3_OPCODE;
1877 i.imm_operands = 0;
1878 }
252b5132 1879
29b0f896
AM		 1880 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1881 && i.op[0].disps->X_op == O_constant)
1882 {
1883 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1884 the absolute address given by the constant. Since ix86 jumps and
1885 calls are pc relative, we need to generate a reloc. */
1886 i.op[0].disps->X_add_symbol = &abs_symbol;
1887 i.op[0].disps->X_op = O_symbol;
1888 }
252b5132 1889
29b0f896 1890 if ((i.tm.opcode_modifier & Rex64) != 0)
161a04f6 1891 i.rex |= REX_W;
252b5132 1892
29b0f896
AM		 1893 /* For 8 bit registers we need an empty rex prefix. Also if the
1894 instruction already has a prefix, we need to convert old
1895 registers to new ones. */
773f551c 1896
29b0f896
AM		 1897 if (((i.types[0] & Reg8) != 0
1898 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1899 || ((i.types[1] & Reg8) != 0
1900 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1901 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1902 && i.rex != 0))
1903 {
1904 int x;
726c5dcd 1905
29b0f896
AM		 1906 i.rex |= REX_OPCODE;
1907 for (x = 0; x < 2; x++)
1908 {
1909 /* Look for 8 bit operand that uses old registers. */
1910 if ((i.types[x] & Reg8) != 0
1911 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1912 {
29b0f896
AM		 1913 /* In case it is "hi" register, give up. */
1914 if (i.op[x].regs->reg_num > 3)
a540244d 1915 as_bad (_("can't encode register '%s%s' in an "
4eed87de 1916 "instruction requiring REX prefix."),
a540244d 1917 register_prefix, i.op[x].regs->reg_name);
773f551c 1918
29b0f896
AM		 1919 /* Otherwise it is equivalent to the extended register.
1920 Since the encoding doesn't change this is merely
1921 cosmetic cleanup for debug output. */
1922
1923 i.op[x].regs = i.op[x].regs + 8;
773f551c 1924 }
29b0f896
AM		 1925 }
1926 }
773f551c 1927
29b0f896
AM		 1928 if (i.rex != 0)
1929 add_prefix (REX_OPCODE | i.rex);
1930
1931 /* We are ready to output the insn. */
1932 output_insn ();
1933}
1934
1935static char *
e3bb37b5 1936parse_insn (char *line, char *mnemonic)
29b0f896
AM		 1937{
1938 char *l = line;
1939 char *token_start = l;
1940 char *mnem_p;
5c6af06e
JB		 1941 int supported;
1942 const template *t;
29b0f896
AM		 1943
1944 /* Non-zero if we found a prefix only acceptable with string insns. */
1945 const char *expecting_string_instruction = NULL;
45288df1 1946
29b0f896
AM		 1947 while (1)
1948 {
1949 mnem_p = mnemonic;
1950 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1951 {
1952 mnem_p++;
1953 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1954 {
29b0f896
AM		 1955 as_bad (_("no such instruction: `%s'"), token_start);
1956 return NULL;
1957 }
1958 l++;
1959 }
1960 if (!is_space_char (*l)
1961 && *l != END_OF_INSN
e44823cf
JB		 1962 && (intel_syntax
1963 || (*l != PREFIX_SEPARATOR
1964 && *l != ',')))
29b0f896
AM		 1965 {
1966 as_bad (_("invalid character %s in mnemonic"),
1967 output_invalid (*l));
1968 return NULL;
1969 }
1970 if (token_start == l)
1971 {
e44823cf 1972 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1973 as_bad (_("expecting prefix; got nothing"));
1974 else
1975 as_bad (_("expecting mnemonic; got nothing"));
1976 return NULL;
1977 }
45288df1 1978
29b0f896
AM		 1979 /* Look up instruction (or prefix) via hash table. */
1980 current_templates = hash_find (op_hash, mnemonic);
47926f60 1981
29b0f896
AM		 1982 if (*l != END_OF_INSN
1983 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1984 && current_templates
1985 && (current_templates->start->opcode_modifier & IsPrefix))
1986 {
2dd88dca
JB		 1987 if (current_templates->start->cpu_flags
1988 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1989 {
1990 as_bad ((flag_code != CODE_64BIT
1991 ? _("`%s' is only supported in 64-bit mode")
1992 : _("`%s' is not supported in 64-bit mode")),
1993 current_templates->start->name);
1994 return NULL;
1995 }
29b0f896
AM		 1996 /* If we are in 16-bit mode, do not allow addr16 or data16.
1997 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1998 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1999 && flag_code != CODE_64BIT
2000 && (((current_templates->start->opcode_modifier & Size32) != 0)
2001 ^ (flag_code == CODE_16BIT)))
2002 {
2003 as_bad (_("redundant %s prefix"),
2004 current_templates->start->name);
2005 return NULL;
45288df1 2006 }
29b0f896
AM		 2007 /* Add prefix, checking for repeated prefixes. */
2008 switch (add_prefix (current_templates->start->base_opcode))
2009 {
2010 case 0:
2011 return NULL;
2012 case 2:
2013 expecting_string_instruction = current_templates->start->name;
2014 break;
2015 }
2016 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2017 token_start = ++l;
2018 }
2019 else
2020 break;
2021 }
45288df1 2022
29b0f896
AM		 2023 if (!current_templates)
2024 {
2025 /* See if we can get a match by trimming off a suffix. */
2026 switch (mnem_p[-1])
2027 {
2028 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2029 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2030 i.suffix = SHORT_MNEM_SUFFIX;
2031 else
29b0f896
AM		 2032 case BYTE_MNEM_SUFFIX:
2033 case QWORD_MNEM_SUFFIX:
2034 i.suffix = mnem_p[-1];
2035 mnem_p[-1] = '\0';
2036 current_templates = hash_find (op_hash, mnemonic);
2037 break;
2038 case SHORT_MNEM_SUFFIX:
2039 case LONG_MNEM_SUFFIX:
2040 if (!intel_syntax)
2041 {
2042 i.suffix = mnem_p[-1];
2043 mnem_p[-1] = '\0';
2044 current_templates = hash_find (op_hash, mnemonic);
2045 }
2046 break;
252b5132 2047
29b0f896
AM		 2048 /* Intel Syntax. */
2049 case 'd':
2050 if (intel_syntax)
2051 {
9306ca4a 2052 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2053 i.suffix = SHORT_MNEM_SUFFIX;
2054 else
2055 i.suffix = LONG_MNEM_SUFFIX;
2056 mnem_p[-1] = '\0';
2057 current_templates = hash_find (op_hash, mnemonic);
2058 }
2059 break;
2060 }
2061 if (!current_templates)
2062 {
2063 as_bad (_("no such instruction: `%s'"), token_start);
2064 return NULL;
2065 }
2066 }
252b5132 2067
29b0f896
AM		 2068 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2069 {
2070 /* Check for a branch hint. We allow ",pt" and ",pn" for
2071 predict taken and predict not taken respectively.
2072 I'm not sure that branch hints actually do anything on loop
2073 and jcxz insns (JumpByte) for current Pentium4 chips. They
2074 may work in the future and it doesn't hurt to accept them
2075 now. */
2076 if (l[0] == ',' && l[1] == 'p')
2077 {
2078 if (l[2] == 't')
2079 {
2080 if (!add_prefix (DS_PREFIX_OPCODE))
2081 return NULL;
2082 l += 3;
2083 }
2084 else if (l[2] == 'n')
2085 {
2086 if (!add_prefix (CS_PREFIX_OPCODE))
2087 return NULL;
2088 l += 3;
2089 }
2090 }
2091 }
2092 /* Any other comma loses. */
2093 if (*l == ',')
2094 {
2095 as_bad (_("invalid character %s in mnemonic"),
2096 output_invalid (*l));
2097 return NULL;
2098 }
252b5132 2099
29b0f896 2100 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2101 supported = 0;
2102 for (t = current_templates->start; t < current_templates->end; ++t)
2103 {
2104 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2105 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 2106 supported |= 1;
5c6af06e 2107 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 2108 supported |= 2;
5c6af06e
JB		 2109 }
2110 if (!(supported & 2))
2111 {
2112 as_bad (flag_code == CODE_64BIT
2113 ? _("`%s' is not supported in 64-bit mode")
2114 : _("`%s' is only supported in 64-bit mode"),
2115 current_templates->start->name);
2116 return NULL;
2117 }
2118 if (!(supported & 1))
29b0f896 2119 {
5c6af06e
JB		 2120 as_warn (_("`%s' is not supported on `%s%s'"),
2121 current_templates->start->name,
2122 cpu_arch_name,
2123 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 2124 }
2125 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2126 {
2127 as_warn (_("use .code16 to ensure correct addressing mode"));
2128 }
252b5132 2129
29b0f896 2130 /* Check for rep/repne without a string instruction. */
f41bbced 2131 if (expecting_string_instruction)
29b0f896 2132 {
f41bbced
JB		 2133 static templates override;
2134
2135 for (t = current_templates->start; t < current_templates->end; ++t)
2136 if (t->opcode_modifier & IsString)
2137 break;
2138 if (t >= current_templates->end)
2139 {
2140 as_bad (_("expecting string instruction after `%s'"),
64e74474 2141 expecting_string_instruction);
f41bbced
JB		 2142 return NULL;
2143 }
2144 for (override.start = t; t < current_templates->end; ++t)
2145 if (!(t->opcode_modifier & IsString))
2146 break;
2147 override.end = t;
2148 current_templates = &override;
29b0f896 2149 }
252b5132 2150
29b0f896
AM		 2151 return l;
2152}
252b5132 2153
29b0f896 2154static char *
e3bb37b5 2155parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2156{
2157 char *token_start;
3138f287 2158
29b0f896
AM		 2159 /* 1 if operand is pending after ','. */
2160 unsigned int expecting_operand = 0;
252b5132 2161
29b0f896
AM		 2162 /* Non-zero if operand parens not balanced. */
2163 unsigned int paren_not_balanced;
2164
2165 while (*l != END_OF_INSN)
2166 {
2167 /* Skip optional white space before operand. */
2168 if (is_space_char (*l))
2169 ++l;
2170 if (!is_operand_char (*l) && *l != END_OF_INSN)
2171 {
2172 as_bad (_("invalid character %s before operand %d"),
2173 output_invalid (*l),
2174 i.operands + 1);
2175 return NULL;
2176 }
2177 token_start = l; /* after white space */
2178 paren_not_balanced = 0;
2179 while (paren_not_balanced || *l != ',')
2180 {
2181 if (*l == END_OF_INSN)
2182 {
2183 if (paren_not_balanced)
2184 {
2185 if (!intel_syntax)
2186 as_bad (_("unbalanced parenthesis in operand %d."),
2187 i.operands + 1);
2188 else
2189 as_bad (_("unbalanced brackets in operand %d."),
2190 i.operands + 1);
2191 return NULL;
2192 }
2193 else
2194 break; /* we are done */
2195 }
2196 else if (!is_operand_char (*l) && !is_space_char (*l))
2197 {
2198 as_bad (_("invalid character %s in operand %d"),
2199 output_invalid (*l),
2200 i.operands + 1);
2201 return NULL;
2202 }
2203 if (!intel_syntax)
2204 {
2205 if (*l == '(')
2206 ++paren_not_balanced;
2207 if (*l == ')')
2208 --paren_not_balanced;
2209 }
2210 else
2211 {
2212 if (*l == '[')
2213 ++paren_not_balanced;
2214 if (*l == ']')
2215 --paren_not_balanced;
2216 }
2217 l++;
2218 }
2219 if (l != token_start)
2220 { /* Yes, we've read in another operand. */
2221 unsigned int operand_ok;
2222 this_operand = i.operands++;
2223 if (i.operands > MAX_OPERANDS)
2224 {
2225 as_bad (_("spurious operands; (%d operands/instruction max)"),
2226 MAX_OPERANDS);
2227 return NULL;
2228 }
2229 /* Now parse operand adding info to 'i' as we go along. */
2230 END_STRING_AND_SAVE (l);
2231
2232 if (intel_syntax)
2233 operand_ok =
2234 i386_intel_operand (token_start,
2235 intel_float_operand (mnemonic));
2236 else
2237 operand_ok = i386_operand (token_start);
2238
2239 RESTORE_END_STRING (l);
2240 if (!operand_ok)
2241 return NULL;
2242 }
2243 else
2244 {
2245 if (expecting_operand)
2246 {
2247 expecting_operand_after_comma:
2248 as_bad (_("expecting operand after ','; got nothing"));
2249 return NULL;
2250 }
2251 if (*l == ',')
2252 {
2253 as_bad (_("expecting operand before ','; got nothing"));
2254 return NULL;
2255 }
2256 }
7f3f1ea2 2257
29b0f896
AM		 2258 /* Now *l must be either ',' or END_OF_INSN. */
2259 if (*l == ',')
2260 {
2261 if (*++l == END_OF_INSN)
2262 {
2263 /* Just skip it, if it's \n complain. */
2264 goto expecting_operand_after_comma;
2265 }
2266 expecting_operand = 1;
2267 }
2268 }
2269 return l;
2270}
7f3f1ea2 2271
050dfa73 2272static void
4d456e3d 2273swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2274{
2275 union i386_op temp_op;
2276 unsigned int temp_type;
2277 enum bfd_reloc_code_real temp_reloc;
4eed87de 2278
050dfa73
MM		 2279 temp_type = i.types[xchg2];
2280 i.types[xchg2] = i.types[xchg1];
2281 i.types[xchg1] = temp_type;
2282 temp_op = i.op[xchg2];
2283 i.op[xchg2] = i.op[xchg1];
2284 i.op[xchg1] = temp_op;
2285 temp_reloc = i.reloc[xchg2];
2286 i.reloc[xchg2] = i.reloc[xchg1];
2287 i.reloc[xchg1] = temp_reloc;
2288}
2289
29b0f896 2290static void
e3bb37b5 2291swap_operands (void)
29b0f896 2292{
b7c61d9a 2293 switch (i.operands)
050dfa73 2294 {
b7c61d9a 2295 case 4:
4d456e3d 2296 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2297 case 3:
2298 case 2:
4d456e3d 2299 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2300 break;
2301 default:
2302 abort ();
29b0f896 2303 }
29b0f896
AM		 2304
2305 if (i.mem_operands == 2)
2306 {
2307 const seg_entry *temp_seg;
2308 temp_seg = i.seg[0];
2309 i.seg[0] = i.seg[1];
2310 i.seg[1] = temp_seg;
2311 }
2312}
252b5132 2313
29b0f896
AM		 2314/* Try to ensure constant immediates are represented in the smallest
2315 opcode possible. */
2316static void
e3bb37b5 2317optimize_imm (void)
29b0f896
AM		 2318{
2319 char guess_suffix = 0;
2320 int op;
252b5132 2321
29b0f896
AM		 2322 if (i.suffix)
2323 guess_suffix = i.suffix;
2324 else if (i.reg_operands)
2325 {
2326 /* Figure out a suffix from the last register operand specified.
2327 We can't do this properly yet, ie. excluding InOutPortReg,
2328 but the following works for instructions with immediates.
2329 In any case, we can't set i.suffix yet. */
2330 for (op = i.operands; --op >= 0;)
2331 if (i.types[op] & Reg)
252b5132 2332 {
29b0f896
AM		 2333 if (i.types[op] & Reg8)
2334 guess_suffix = BYTE_MNEM_SUFFIX;
2335 else if (i.types[op] & Reg16)
2336 guess_suffix = WORD_MNEM_SUFFIX;
2337 else if (i.types[op] & Reg32)
2338 guess_suffix = LONG_MNEM_SUFFIX;
2339 else if (i.types[op] & Reg64)
2340 guess_suffix = QWORD_MNEM_SUFFIX;
2341 break;
252b5132 2342 }
29b0f896
AM		 2343 }
2344 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2345 guess_suffix = WORD_MNEM_SUFFIX;
2346
2347 for (op = i.operands; --op >= 0;)
2348 if (i.types[op] & Imm)
2349 {
2350 switch (i.op[op].imms->X_op)
252b5132 2351 {
29b0f896
AM		 2352 case O_constant:
2353 /* If a suffix is given, this operand may be shortened. */
2354 switch (guess_suffix)
252b5132 2355 {
29b0f896
AM		 2356 case LONG_MNEM_SUFFIX:
2357 i.types[op] |= Imm32 | Imm64;
2358 break;
2359 case WORD_MNEM_SUFFIX:
2360 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2361 break;
2362 case BYTE_MNEM_SUFFIX:
2363 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2364 break;
252b5132 2365 }
252b5132 2366
29b0f896
AM		 2367 /* If this operand is at most 16 bits, convert it
2368 to a signed 16 bit number before trying to see
2369 whether it will fit in an even smaller size.
2370 This allows a 16-bit operand such as $0xffe0 to
2371 be recognised as within Imm8S range. */
2372 if ((i.types[op] & Imm16)
2373 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2374 {
29b0f896
AM		 2375 i.op[op].imms->X_add_number =
2376 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2377 }
2378 if ((i.types[op] & Imm32)
2379 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2380 == 0))
2381 {
2382 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2383 ^ ((offsetT) 1 << 31))
2384 - ((offsetT) 1 << 31));
2385 }
2386 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2387
29b0f896
AM		 2388 /* We must avoid matching of Imm32 templates when 64bit
2389 only immediate is available. */
2390 if (guess_suffix == QWORD_MNEM_SUFFIX)
2391 i.types[op] &= ~Imm32;
2392 break;
252b5132 2393
29b0f896
AM		 2394 case O_absent:
2395 case O_register:
2396 abort ();
2397
2398 /* Symbols and expressions. */
2399 default:
9cd96992
JB		 2400 /* Convert symbolic operand to proper sizes for matching, but don't
2401 prevent matching a set of insns that only supports sizes other
2402 than those matching the insn suffix. */
2403 {
2404 unsigned int mask, allowed = 0;
2405 const template *t;
2406
4eed87de
AM		 2407 for (t = current_templates->start;
2408 t < current_templates->end;
2409 ++t)
2410 allowed |= t->operand_types[op];
9cd96992
JB		 2411 switch (guess_suffix)
2412 {
2413 case QWORD_MNEM_SUFFIX:
2414 mask = Imm64 | Imm32S;
2415 break;
2416 case LONG_MNEM_SUFFIX:
2417 mask = Imm32;
2418 break;
2419 case WORD_MNEM_SUFFIX:
2420 mask = Imm16;
2421 break;
2422 case BYTE_MNEM_SUFFIX:
2423 mask = Imm8;
2424 break;
2425 default:
2426 mask = 0;
2427 break;
2428 }
64e74474
AM		 2429 if (mask & allowed)
2430 i.types[op] &= mask;
9cd96992 2431 }
29b0f896 2432 break;
252b5132 2433 }
29b0f896
AM		 2434 }
2435}
47926f60 2436
29b0f896
AM		 2437/* Try to use the smallest displacement type too. */
2438static void
e3bb37b5 2439optimize_disp (void)
29b0f896
AM		 2440{
2441 int op;
3e73aa7c 2442
29b0f896 2443 for (op = i.operands; --op >= 0;)
b300c311 2444 if (i.types[op] & Disp)
252b5132 2445 {
b300c311 2446 if (i.op[op].disps->X_op == O_constant)
252b5132 2447 {
b300c311 2448 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2449
b300c311
L		 2450 if ((i.types[op] & Disp16)
2451 && (disp & ~(offsetT) 0xffff) == 0)
2452 {
2453 /* If this operand is at most 16 bits, convert
2454 to a signed 16 bit number and don't use 64bit
2455 displacement. */
2456 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2457 i.types[op] &= ~Disp64;
2458 }
2459 if ((i.types[op] & Disp32)
2460 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2461 {
2462 /* If this operand is at most 32 bits, convert
2463 to a signed 32 bit number and don't use 64bit
2464 displacement. */
2465 disp &= (((offsetT) 2 << 31) - 1);
2466 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2467 i.types[op] &= ~Disp64;
2468 }
2469 if (!disp && (i.types[op] & BaseIndex))
2470 {
2471 i.types[op] &= ~Disp;
2472 i.op[op].disps = 0;
2473 i.disp_operands--;
2474 }
2475 else if (flag_code == CODE_64BIT)
2476 {
2477 if (fits_in_signed_long (disp))
28a9d8f5
L		 2478 {
2479 i.types[op] &= ~Disp64;
2480 i.types[op] |= Disp32S;
2481 }
b300c311
L		 2482 if (fits_in_unsigned_long (disp))
2483 i.types[op] |= Disp32;
2484 }
2485 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2486 && fits_in_signed_byte (disp))
2487 i.types[op] |= Disp8;
252b5132 2488 }
67a4f2b7
AO		 2489 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2490 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2491 {
2492 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2493 i.op[op].disps, 0, i.reloc[op]);
2494 i.types[op] &= ~Disp;
2495 }
2496 else
b300c311
L		 2497 /* We only support 64bit displacement on constants. */
2498 i.types[op] &= ~Disp64;
252b5132 2499 }
29b0f896
AM		 2500}
2501
2502static int
e3bb37b5 2503match_template (void)
29b0f896
AM		 2504{
2505 /* Points to template once we've found it. */
2506 const template *t;
f48ff2ae 2507 unsigned int overlap0, overlap1, overlap2, overlap3;
29b0f896
AM		 2508 unsigned int found_reverse_match;
2509 int suffix_check;
f48ff2ae 2510 unsigned int operand_types [MAX_OPERANDS];
539e75ad 2511 int addr_prefix_disp;
a5c311ca 2512 unsigned int j;
29b0f896 2513
f48ff2ae
L		 2514#if MAX_OPERANDS != 4
2515# error "MAX_OPERANDS must be 4."
2516#endif
2517
29b0f896
AM		 2518#define MATCH(overlap, given, template) \
2519 ((overlap & ~JumpAbsolute) \
2520 && (((given) & (BaseIndex | JumpAbsolute)) \
2521 == ((overlap) & (BaseIndex | JumpAbsolute))))
2522
2523 /* If given types r0 and r1 are registers they must be of the same type
2524 unless the expected operand type register overlap is null.
2525 Note that Acc in a template matches every size of reg. */
2526#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2527 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2528 || ((g0) & Reg) == ((g1) & Reg) \
2529 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2530
2531 overlap0 = 0;
2532 overlap1 = 0;
2533 overlap2 = 0;
f48ff2ae 2534 overlap3 = 0;
29b0f896 2535 found_reverse_match = 0;
a5c311ca
L		 2536 for (j = 0; j < MAX_OPERANDS; j++)
2537 operand_types [j] = 0;
539e75ad 2538 addr_prefix_disp = -1;
29b0f896
AM		 2539 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2540 ? No_bSuf
2541 : (i.suffix == WORD_MNEM_SUFFIX
2542 ? No_wSuf
2543 : (i.suffix == SHORT_MNEM_SUFFIX
2544 ? No_sSuf
2545 : (i.suffix == LONG_MNEM_SUFFIX
2546 ? No_lSuf
2547 : (i.suffix == QWORD_MNEM_SUFFIX
2548 ? No_qSuf
2549 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2550 ? No_xSuf : 0))))));
2551
45aa61fe 2552 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2553 {
539e75ad
L		 2554 addr_prefix_disp = -1;
2555
29b0f896
AM		 2556 /* Must have right number of operands. */
2557 if (i.operands != t->operands)
2558 continue;
2559
9344ff29
L		 2560 /* Check the suffix, except for some instructions in intel mode.
2561 We do want to check suffix for crc32 even in intel mode. */
29b0f896
AM		 2562 if ((t->opcode_modifier & suffix_check)
2563 && !(intel_syntax
9344ff29 2564 && t->base_opcode != 0xf20f38f1
9306ca4a 2565 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2566 continue;
2567
a5c311ca
L		 2568 for (j = 0; j < MAX_OPERANDS; j++)
2569 operand_types [j] = t->operand_types [j];
539e75ad 2570
45aa61fe
AM		 2571 /* In general, don't allow 64-bit operands in 32-bit mode. */
2572 if (i.suffix == QWORD_MNEM_SUFFIX
2573 && flag_code != CODE_64BIT
2574 && (intel_syntax
2575 ? (!(t->opcode_modifier & IgnoreSize)
2576 && !intel_float_operand (t->name))
2577 : intel_float_operand (t->name) != 2)
539e75ad
L		 2578 && (!(operand_types[0] & (RegMMX | RegXMM))
2579 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
45aa61fe
AM		 2580 && (t->base_opcode != 0x0fc7
2581 || t->extension_opcode != 1 /* cmpxchg8b */))
2582 continue;
2583
29b0f896
AM		 2584 /* Do not verify operands when there are none. */
2585 else if (!t->operands)
2586 {
2587 if (t->cpu_flags & ~cpu_arch_flags)
2588 continue;
2589 /* We've found a match; break out of loop. */
2590 break;
2591 }
252b5132 2592
539e75ad
L		 2593 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2594 into Disp32/Disp16/Disp32 operand. */
2595 if (i.prefix[ADDR_PREFIX] != 0)
2596 {
a5c311ca 2597 unsigned int DispOn = 0, DispOff = 0;
539e75ad
L		 2598
2599 switch (flag_code)
2600 {
2601 case CODE_16BIT:
2602 DispOn = Disp32;
2603 DispOff = Disp16;
2604 break;
2605 case CODE_32BIT:
2606 DispOn = Disp16;
2607 DispOff = Disp32;
2608 break;
2609 case CODE_64BIT:
2610 DispOn = Disp32;
2611 DispOff = Disp64;
2612 break;
2613 }
2614
f48ff2ae 2615 for (j = 0; j < MAX_OPERANDS; j++)
539e75ad
L		 2616 {
2617 /* There should be only one Disp operand. */
2618 if ((operand_types[j] & DispOff))
2619 {
2620 addr_prefix_disp = j;
2621 operand_types[j] |= DispOn;
2622 operand_types[j] &= ~DispOff;
2623 break;
2624 }
2625 }
2626 }
2627
2628 overlap0 = i.types[0] & operand_types[0];
29b0f896
AM		 2629 switch (t->operands)
2630 {
2631 case 1:
539e75ad 2632 if (!MATCH (overlap0, i.types[0], operand_types[0]))
29b0f896
AM		 2633 continue;
2634 break;
2635 case 2:
8b38ad71
L		 2636 /* xchg %eax, %eax is a special case. It is an aliase for nop
2637 only in 32bit mode and we can use opcode 0x90. In 64bit
2638 mode, we can't use 0x90 for xchg %eax, %eax since it should
2639 zero-extend %eax to %rax. */
2640 if (flag_code == CODE_64BIT
2641 && t->base_opcode == 0x90
2642 && i.types [0] == (Acc | Reg32)
2643 && i.types [1] == (Acc | Reg32))
2644 continue;
29b0f896 2645 case 3:
f48ff2ae 2646 case 4:
539e75ad
L		 2647 overlap1 = i.types[1] & operand_types[1];
2648 if (!MATCH (overlap0, i.types[0], operand_types[0])
2649 || !MATCH (overlap1, i.types[1], operand_types[1])
cb712a9e 2650 /* monitor in SSE3 is a very special case. The first
708587a4 2651 register and the second register may have different
381d071f 2652 sizes. The same applies to crc32 in SSE4.2. */
cb712a9e
L		 2653 || !((t->base_opcode == 0x0f01
2654 && t->extension_opcode == 0xc8)
381d071f 2655 || t->base_opcode == 0xf20f38f1
cb712a9e 2656 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2657 operand_types[0],
cb712a9e 2658 overlap1, i.types[1],
539e75ad 2659 operand_types[1])))
29b0f896
AM		 2660 {
2661 /* Check if other direction is valid ... */
2662 if ((t->opcode_modifier & (D | FloatD)) == 0)
2663 continue;
2664
2665 /* Try reversing direction of operands. */
539e75ad
L		 2666 overlap0 = i.types[0] & operand_types[1];
2667 overlap1 = i.types[1] & operand_types[0];
2668 if (!MATCH (overlap0, i.types[0], operand_types[1])
2669 || !MATCH (overlap1, i.types[1], operand_types[0])
29b0f896 2670 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2671 operand_types[1],
29b0f896 2672 overlap1, i.types[1],
539e75ad 2673 operand_types[0]))
29b0f896
AM		 2674 {
2675 /* Does not match either direction. */
2676 continue;
2677 }
2678 /* found_reverse_match holds which of D or FloatDR
2679 we've found. */
8a2ed489
L		 2680 if ((t->opcode_modifier & D))
2681 found_reverse_match = Opcode_D;
2682 else if ((t->opcode_modifier & FloatD))
2683 found_reverse_match = Opcode_FloatD;
2684 else
2685 found_reverse_match = 0;
2686 if ((t->opcode_modifier & FloatR))
2687 found_reverse_match |= Opcode_FloatR;
29b0f896 2688 }
f48ff2ae 2689 else
29b0f896 2690 {
f48ff2ae 2691 /* Found a forward 2 operand match here. */
d1cbb4db
L		 2692 switch (t->operands)
2693 {
2694 case 4:
2695 overlap3 = i.types[3] & operand_types[3];
2696 case 3:
2697 overlap2 = i.types[2] & operand_types[2];
2698 break;
2699 }
29b0f896 2700
f48ff2ae
L		 2701 switch (t->operands)
2702 {
2703 case 4:
2704 if (!MATCH (overlap3, i.types[3], operand_types[3])
2705 || !CONSISTENT_REGISTER_MATCH (overlap2,
2706 i.types[2],
2707 operand_types[2],
2708 overlap3,
2709 i.types[3],
2710 operand_types[3]))
2711 continue;
2712 case 3:
2713 /* Here we make use of the fact that there are no
2714 reverse match 3 operand instructions, and all 3
2715 operand instructions only need to be checked for
2716 register consistency between operands 2 and 3. */
2717 if (!MATCH (overlap2, i.types[2], operand_types[2])
2718 || !CONSISTENT_REGISTER_MATCH (overlap1,
2719 i.types[1],
2720 operand_types[1],
2721 overlap2,
2722 i.types[2],
2723 operand_types[2]))
2724 continue;
2725 break;
2726 }
29b0f896 2727 }
f48ff2ae 2728 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 2729 slip through to break. */
2730 }
2731 if (t->cpu_flags & ~cpu_arch_flags)
2732 {
2733 found_reverse_match = 0;
2734 continue;
2735 }
2736 /* We've found a match; break out of loop. */
2737 break;
2738 }
2739
2740 if (t == current_templates->end)
2741 {
2742 /* We found no match. */
2743 as_bad (_("suffix or operands invalid for `%s'"),
2744 current_templates->start->name);
2745 return 0;
2746 }
252b5132 2747
29b0f896
AM		 2748 if (!quiet_warnings)
2749 {
2750 if (!intel_syntax
2751 && ((i.types[0] & JumpAbsolute)
539e75ad 2752 != (operand_types[0] & JumpAbsolute)))
29b0f896
AM		 2753 {
2754 as_warn (_("indirect %s without `*'"), t->name);
2755 }
2756
2757 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2758 == (IsPrefix | IgnoreSize))
2759 {
2760 /* Warn them that a data or address size prefix doesn't
2761 affect assembly of the next line of code. */
2762 as_warn (_("stand-alone `%s' prefix"), t->name);
2763 }
2764 }
2765
2766 /* Copy the template we found. */
2767 i.tm = *t;
539e75ad
L		 2768
2769 if (addr_prefix_disp != -1)
2770 i.tm.operand_types[addr_prefix_disp]
2771 = operand_types[addr_prefix_disp];
2772
29b0f896
AM		 2773 if (found_reverse_match)
2774 {
2775 /* If we found a reverse match we must alter the opcode
2776 direction bit. found_reverse_match holds bits to change
2777 (different for int & float insns). */
2778
2779 i.tm.base_opcode ^= found_reverse_match;
2780
539e75ad
L		 2781 i.tm.operand_types[0] = operand_types[1];
2782 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 2783 }
2784
2785 return 1;
2786}
2787
2788static int
e3bb37b5 2789check_string (void)
29b0f896
AM		 2790{
2791 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2792 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2793 {
2794 if (i.seg[0] != NULL && i.seg[0] != &es)
2795 {
2796 as_bad (_("`%s' operand %d must use `%%es' segment"),
2797 i.tm.name,
2798 mem_op + 1);
2799 return 0;
2800 }
2801 /* There's only ever one segment override allowed per instruction.
2802 This instruction possibly has a legal segment override on the
2803 second operand, so copy the segment to where non-string
2804 instructions store it, allowing common code. */
2805 i.seg[0] = i.seg[1];
2806 }
2807 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2808 {
2809 if (i.seg[1] != NULL && i.seg[1] != &es)
2810 {
2811 as_bad (_("`%s' operand %d must use `%%es' segment"),
2812 i.tm.name,
2813 mem_op + 2);
2814 return 0;
2815 }
2816 }
2817 return 1;
2818}
2819
2820static int
543613e9 2821process_suffix (void)
29b0f896
AM		 2822{
2823 /* If matched instruction specifies an explicit instruction mnemonic
2824 suffix, use it. */
2825 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2826 {
2827 if (i.tm.opcode_modifier & Size16)
2828 i.suffix = WORD_MNEM_SUFFIX;
2829 else if (i.tm.opcode_modifier & Size64)
2830 i.suffix = QWORD_MNEM_SUFFIX;
2831 else
2832 i.suffix = LONG_MNEM_SUFFIX;
2833 }
2834 else if (i.reg_operands)
2835 {
2836 /* If there's no instruction mnemonic suffix we try to invent one
2837 based on register operands. */
2838 if (!i.suffix)
2839 {
2840 /* We take i.suffix from the last register operand specified,
2841 Destination register type is more significant than source
381d071f
L		 2842 register type. crc32 in SSE4.2 prefers source register
2843 type. */
2844 if (i.tm.base_opcode == 0xf20f38f1)
2845 {
2846 if ((i.types[0] & Reg))
2847 i.suffix = ((i.types[0] & Reg16) ? WORD_MNEM_SUFFIX :
29b0f896 2848 LONG_MNEM_SUFFIX);
381d071f 2849 }
9344ff29
L		 2850 else if (i.tm.base_opcode == 0xf20f38f0)
2851 i.suffix = BYTE_MNEM_SUFFIX;
381d071f
L		 2852
2853 if (!i.suffix)
2854 {
2855 int op;
2856
2857 for (op = i.operands; --op >= 0;)
2858 if ((i.types[op] & Reg)
2859 && !(i.tm.operand_types[op] & InOutPortReg))
2860 {
2861 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2862 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2863 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2864 LONG_MNEM_SUFFIX);
2865 break;
2866 }
2867 }
29b0f896
AM		 2868 }
2869 else if (i.suffix == BYTE_MNEM_SUFFIX)
2870 {
2871 if (!check_byte_reg ())
2872 return 0;
2873 }
2874 else if (i.suffix == LONG_MNEM_SUFFIX)
2875 {
2876 if (!check_long_reg ())
2877 return 0;
2878 }
2879 else if (i.suffix == QWORD_MNEM_SUFFIX)
2880 {
2881 if (!check_qword_reg ())
2882 return 0;
2883 }
2884 else if (i.suffix == WORD_MNEM_SUFFIX)
2885 {
2886 if (!check_word_reg ())
2887 return 0;
2888 }
2889 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2890 /* Do nothing if the instruction is going to ignore the prefix. */
2891 ;
2892 else
2893 abort ();
2894 }
9306ca4a
JB		 2895 else if ((i.tm.opcode_modifier & DefaultSize)
2896 && !i.suffix
2897 /* exclude fldenv/frstor/fsave/fstenv */
2898 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2899 {
2900 i.suffix = stackop_size;
2901 }
9306ca4a
JB		 2902 else if (intel_syntax
2903 && !i.suffix
2904 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2905 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2906 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2907 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2908 {
2909 switch (flag_code)
2910 {
2911 case CODE_64BIT:
2912 if (!(i.tm.opcode_modifier & No_qSuf))
2913 {
2914 i.suffix = QWORD_MNEM_SUFFIX;
2915 break;
2916 }
2917 case CODE_32BIT:
2918 if (!(i.tm.opcode_modifier & No_lSuf))
2919 i.suffix = LONG_MNEM_SUFFIX;
2920 break;
2921 case CODE_16BIT:
2922 if (!(i.tm.opcode_modifier & No_wSuf))
2923 i.suffix = WORD_MNEM_SUFFIX;
2924 break;
2925 }
2926 }
252b5132 2927
9306ca4a 2928 if (!i.suffix)
29b0f896 2929 {
9306ca4a
JB		 2930 if (!intel_syntax)
2931 {
2932 if (i.tm.opcode_modifier & W)
2933 {
4eed87de
AM		 2934 as_bad (_("no instruction mnemonic suffix given and "
2935 "no register operands; can't size instruction"));
9306ca4a
JB		 2936 return 0;
2937 }
2938 }
2939 else
2940 {
64e74474
AM		 2941 unsigned int suffixes = (~i.tm.opcode_modifier
2942 & (No_bSuf
2943 | No_wSuf
2944 | No_lSuf
2945 | No_sSuf
2946 | No_xSuf
2947 | No_qSuf));
9306ca4a
JB		 2948
2949 if ((i.tm.opcode_modifier & W)
2950 || ((suffixes & (suffixes - 1))
2951 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2952 {
2953 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2954 return 0;
2955 }
2956 }
29b0f896 2957 }
252b5132 2958
9306ca4a
JB		 2959 /* Change the opcode based on the operand size given by i.suffix;
2960 We don't need to change things for byte insns. */
2961
29b0f896
AM		 2962 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2963 {
2964 /* It's not a byte, select word/dword operation. */
2965 if (i.tm.opcode_modifier & W)
2966 {
2967 if (i.tm.opcode_modifier & ShortForm)
2968 i.tm.base_opcode |= 8;
2969 else
2970 i.tm.base_opcode |= 1;
2971 }
0f3f3d8b 2972
29b0f896
AM		 2973 /* Now select between word & dword operations via the operand
2974 size prefix, except for instructions that will ignore this
2975 prefix anyway. */
cb712a9e
L		 2976 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2977 {
2978 /* monitor in SSE3 is a very special case. The default size
2979 of AX is the size of mode. The address size override
2980 prefix will change the size of AX. */
2981 if (i.op->regs[0].reg_type &
2982 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2983 if (!add_prefix (ADDR_PREFIX_OPCODE))
2984 return 0;
2985 }
2986 else if (i.suffix != QWORD_MNEM_SUFFIX
2987 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2988 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2989 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2990 || (flag_code == CODE_64BIT
2991 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2992 {
2993 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2994
29b0f896
AM		 2995 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2996 prefix = ADDR_PREFIX_OPCODE;
252b5132 2997
29b0f896
AM		 2998 if (!add_prefix (prefix))
2999 return 0;
24eab124 3000 }
252b5132 3001
29b0f896
AM		 3002 /* Set mode64 for an operand. */
3003 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3004 && flag_code == CODE_64BIT
29b0f896 3005 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L		 3006 {
3007 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3008 need rex64. */
3009 if (i.operands != 2
3010 || i.types [0] != (Acc | Reg64)
3011 || i.types [1] != (Acc | Reg64)
13a1e313 3012 || i.tm.base_opcode != 0x90)
f6bee062 3013 i.rex |= REX_W;
46e883c5 3014 }
3e73aa7c 3015
29b0f896
AM		 3016 /* Size floating point instruction. */
3017 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 3018 if (i.tm.opcode_modifier & FloatMF)
3019 i.tm.base_opcode ^= 4;
29b0f896 3020 }
7ecd2f8b 3021
29b0f896
AM		 3022 return 1;
3023}
3e73aa7c 3024
29b0f896 3025static int
543613e9 3026check_byte_reg (void)
29b0f896
AM		 3027{
3028 int op;
543613e9 3029
29b0f896
AM		 3030 for (op = i.operands; --op >= 0;)
3031 {
3032 /* If this is an eight bit register, it's OK. If it's the 16 or
3033 32 bit version of an eight bit register, we will just use the
3034 low portion, and that's OK too. */
3035 if (i.types[op] & Reg8)
3036 continue;
3037
3038 /* movzx and movsx should not generate this warning. */
3039 if (intel_syntax
3040 && (i.tm.base_opcode == 0xfb7
3041 || i.tm.base_opcode == 0xfb6
3042 || i.tm.base_opcode == 0x63
3043 || i.tm.base_opcode == 0xfbe
3044 || i.tm.base_opcode == 0xfbf))
3045 continue;
3046
9344ff29
L		 3047 /* crc32 doesn't generate this warning. */
3048 if (i.tm.base_opcode == 0xf20f38f0)
3049 continue;
3050
65ec77d2 3051 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3052 {
3053 /* Prohibit these changes in the 64bit mode, since the
3054 lowering is more complicated. */
3055 if (flag_code == CODE_64BIT
3056 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3057 {
2ca3ace5
L		 3058 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3059 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3060 i.suffix);
3061 return 0;
3062 }
3063#if REGISTER_WARNINGS
3064 if (!quiet_warnings
3065 && (i.tm.operand_types[op] & InOutPortReg) == 0)
a540244d
L		 3066 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3067 register_prefix,
29b0f896
AM		 3068 (i.op[op].regs + (i.types[op] & Reg16
3069 ? REGNAM_AL - REGNAM_AX
3070 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3071 register_prefix,
29b0f896
AM		 3072 i.op[op].regs->reg_name,
3073 i.suffix);
3074#endif
3075 continue;
3076 }
3077 /* Any other register is bad. */
3078 if (i.types[op] & (Reg | RegMMX | RegXMM
3079 | SReg2 | SReg3
3080 | Control | Debug | Test
3081 | FloatReg | FloatAcc))
3082 {
a540244d
L		 3083 as_bad (_("`%s%s' not allowed with `%s%c'"),
3084 register_prefix,
29b0f896
AM		 3085 i.op[op].regs->reg_name,
3086 i.tm.name,
3087 i.suffix);
3088 return 0;
3089 }
3090 }
3091 return 1;
3092}
3093
3094static int
e3bb37b5 3095check_long_reg (void)
29b0f896
AM		 3096{
3097 int op;
3098
3099 for (op = i.operands; --op >= 0;)
3100 /* Reject eight bit registers, except where the template requires
3101 them. (eg. movzb) */
3102 if ((i.types[op] & Reg8) != 0
3103 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3104 {
a540244d
L		 3105 as_bad (_("`%s%s' not allowed with `%s%c'"),
3106 register_prefix,
29b0f896
AM		 3107 i.op[op].regs->reg_name,
3108 i.tm.name,
3109 i.suffix);
3110 return 0;
3111 }
3112 /* Warn if the e prefix on a general reg is missing. */
3113 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3114 && (i.types[op] & Reg16) != 0
3115 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3116 {
3117 /* Prohibit these changes in the 64bit mode, since the
3118 lowering is more complicated. */
3119 if (flag_code == CODE_64BIT)
252b5132 3120 {
2ca3ace5
L		 3121 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3122 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3123 i.suffix);
3124 return 0;
252b5132 3125 }
29b0f896
AM		 3126#if REGISTER_WARNINGS
3127 else
a540244d
L		 3128 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3129 register_prefix,
29b0f896 3130 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3131 register_prefix,
29b0f896
AM		 3132 i.op[op].regs->reg_name,
3133 i.suffix);
3134#endif
252b5132 3135 }
29b0f896
AM		 3136 /* Warn if the r prefix on a general reg is missing. */
3137 else if ((i.types[op] & Reg64) != 0
3138 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 3139 {
2ca3ace5
L		 3140 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3141 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3142 i.suffix);
3143 return 0;
3144 }
3145 return 1;
3146}
252b5132 3147
29b0f896 3148static int
e3bb37b5 3149check_qword_reg (void)
29b0f896
AM		 3150{
3151 int op;
252b5132 3152
29b0f896
AM		 3153 for (op = i.operands; --op >= 0; )
3154 /* Reject eight bit registers, except where the template requires
3155 them. (eg. movzb) */
3156 if ((i.types[op] & Reg8) != 0
3157 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3158 {
a540244d
L		 3159 as_bad (_("`%s%s' not allowed with `%s%c'"),
3160 register_prefix,
29b0f896
AM		 3161 i.op[op].regs->reg_name,
3162 i.tm.name,
3163 i.suffix);
3164 return 0;
3165 }
3166 /* Warn if the e prefix on a general reg is missing. */
3167 else if (((i.types[op] & Reg16) != 0
3168 || (i.types[op] & Reg32) != 0)
3169 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3170 {
3171 /* Prohibit these changes in the 64bit mode, since the
3172 lowering is more complicated. */
2ca3ace5
L		 3173 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3174 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3175 i.suffix);
3176 return 0;
252b5132 3177 }
29b0f896
AM		 3178 return 1;
3179}
252b5132 3180
29b0f896 3181static int
e3bb37b5 3182check_word_reg (void)
29b0f896
AM		 3183{
3184 int op;
3185 for (op = i.operands; --op >= 0;)
3186 /* Reject eight bit registers, except where the template requires
3187 them. (eg. movzb) */
3188 if ((i.types[op] & Reg8) != 0
3189 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3190 {
a540244d
L		 3191 as_bad (_("`%s%s' not allowed with `%s%c'"),
3192 register_prefix,
29b0f896
AM		 3193 i.op[op].regs->reg_name,
3194 i.tm.name,
3195 i.suffix);
3196 return 0;
3197 }
3198 /* Warn if the e prefix on a general reg is present. */
3199 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3200 && (i.types[op] & Reg32) != 0
3201 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 3202 {
29b0f896
AM		 3203 /* Prohibit these changes in the 64bit mode, since the
3204 lowering is more complicated. */
3205 if (flag_code == CODE_64BIT)
252b5132 3206 {
2ca3ace5
L		 3207 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3208 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3209 i.suffix);
3210 return 0;
252b5132 3211 }
29b0f896
AM		 3212 else
3213#if REGISTER_WARNINGS
a540244d
L		 3214 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3215 register_prefix,
29b0f896 3216 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 3217 register_prefix,
29b0f896
AM		 3218 i.op[op].regs->reg_name,
3219 i.suffix);
3220#endif
3221 }
3222 return 1;
3223}
252b5132 3224
29b0f896 3225static int
e3bb37b5 3226finalize_imm (void)
29b0f896
AM		 3227{
3228 unsigned int overlap0, overlap1, overlap2;
3229
3230 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 3231 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 3232 && overlap0 != Imm8 && overlap0 != Imm8S
3233 && overlap0 != Imm16 && overlap0 != Imm32S
3234 && overlap0 != Imm32 && overlap0 != Imm64)
3235 {
3236 if (i.suffix)
3237 {
3238 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3239 ? Imm8 | Imm8S
3240 : (i.suffix == WORD_MNEM_SUFFIX
3241 ? Imm16
3242 : (i.suffix == QWORD_MNEM_SUFFIX
3243 ? Imm64 | Imm32S
3244 : Imm32)));
3245 }
3246 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3247 || overlap0 == (Imm16 | Imm32)
3248 || overlap0 == (Imm16 | Imm32S))
3249 {
3250 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3251 ? Imm16 : Imm32S);
3252 }
3253 if (overlap0 != Imm8 && overlap0 != Imm8S
3254 && overlap0 != Imm16 && overlap0 != Imm32S
3255 && overlap0 != Imm32 && overlap0 != Imm64)
3256 {
4eed87de
AM		 3257 as_bad (_("no instruction mnemonic suffix given; "
3258 "can't determine immediate size"));
29b0f896
AM		 3259 return 0;
3260 }
3261 }
3262 i.types[0] = overlap0;
3263
3264 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 3265 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 3266 && overlap1 != Imm8 && overlap1 != Imm8S
3267 && overlap1 != Imm16 && overlap1 != Imm32S
3268 && overlap1 != Imm32 && overlap1 != Imm64)
3269 {
3270 if (i.suffix)
3271 {
3272 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3273 ? Imm8 | Imm8S
3274 : (i.suffix == WORD_MNEM_SUFFIX
3275 ? Imm16
3276 : (i.suffix == QWORD_MNEM_SUFFIX
3277 ? Imm64 | Imm32S
3278 : Imm32)));
3279 }
3280 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3281 || overlap1 == (Imm16 | Imm32)
3282 || overlap1 == (Imm16 | Imm32S))
3283 {
3284 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3285 ? Imm16 : Imm32S);
3286 }
3287 if (overlap1 != Imm8 && overlap1 != Imm8S
3288 && overlap1 != Imm16 && overlap1 != Imm32S
3289 && overlap1 != Imm32 && overlap1 != Imm64)
3290 {
4eed87de
AM		 3291 as_bad (_("no instruction mnemonic suffix given; "
3292 "can't determine immediate size %x %c"),
3293 overlap1, i.suffix);
29b0f896
AM		 3294 return 0;
3295 }
3296 }
3297 i.types[1] = overlap1;
3298
3299 overlap2 = i.types[2] & i.tm.operand_types[2];
3300 assert ((overlap2 & Imm) == 0);
3301 i.types[2] = overlap2;
3302
3303 return 1;
3304}
3305
3306static int
e3bb37b5 3307process_operands (void)
29b0f896
AM		 3308{
3309 /* Default segment register this instruction will use for memory
3310 accesses. 0 means unknown. This is only for optimizing out
3311 unnecessary segment overrides. */
3312 const seg_entry *default_seg = 0;
3313
3314 /* The imul $imm, %reg instruction is converted into
3315 imul $imm, %reg, %reg, and the clr %reg instruction
3316 is converted into xor %reg, %reg. */
3317 if (i.tm.opcode_modifier & regKludge)
3318 {
42903f7f
L		 3319 if ((i.tm.cpu_flags & CpuSSE4_1))
3320 {
3321 /* The first operand in instruction blendvpd, blendvps and
3322 pblendvb in SSE4.1 is implicit and must be xmm0. */
3323 assert (i.operands == 3
3324 && i.reg_operands >= 2
3325 && i.types[0] == RegXMM);
3326 if (i.op[0].regs->reg_num != 0)
3327 {
3328 if (intel_syntax)
3329 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
3330 i.tm.name, register_prefix);
3331 else
3332 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
3333 i.tm.name, register_prefix);
3334 return 0;
3335 }
3336 i.op[0] = i.op[1];
3337 i.op[1] = i.op[2];
3338 i.types[0] = i.types[1];
3339 i.types[1] = i.types[2];
3340 i.operands--;
3341 i.reg_operands--;
3342
3343 /* We need to adjust fields in i.tm since they are used by
3344 build_modrm_byte. */
3345 i.tm.operand_types [0] = i.tm.operand_types [1];
3346 i.tm.operand_types [1] = i.tm.operand_types [2];
3347 i.tm.operands--;
3348 }
3349 else
3350 {
3351 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3352 /* Pretend we saw the extra register operand. */
3353 assert (i.reg_operands == 1
3354 && i.op[first_reg_op + 1].regs == 0);
3355 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3356 i.types[first_reg_op + 1] = i.types[first_reg_op];
3357 i.operands++;
3358 i.reg_operands++;
3359 }
29b0f896
AM		 3360 }
3361
3362 if (i.tm.opcode_modifier & ShortForm)
3363 {
4eed87de 3364 if (i.types[0] & (SReg2 | SReg3))
29b0f896 3365 {
4eed87de
AM		 3366 if (i.tm.base_opcode == POP_SEG_SHORT
3367 && i.op[0].regs->reg_num == 1)
29b0f896 3368 {
4eed87de
AM		 3369 as_bad (_("you can't `pop %%cs'"));
3370 return 0;
29b0f896 3371 }
4eed87de
AM		 3372 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3373 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 3374 i.rex |= REX_B;
4eed87de
AM		 3375 }
3376 else
3377 {
3378 /* The register or float register operand is in operand 0 or 1. */
3379 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3380 /* Register goes in low 3 bits of opcode. */
3381 i.tm.base_opcode |= i.op[op].regs->reg_num;
3382 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3383 i.rex |= REX_B;
4eed87de 3384 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
29b0f896 3385 {
4eed87de
AM		 3386 /* Warn about some common errors, but press on regardless.
3387 The first case can be generated by gcc (<= 2.8.1). */
3388 if (i.operands == 2)
3389 {
3390 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 3391 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
3392 register_prefix, i.op[1].regs->reg_name,
3393 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 3394 }
3395 else
3396 {
3397 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 3398 as_warn (_("translating to `%s %s%s'"), i.tm.name,
3399 register_prefix, i.op[0].regs->reg_name);
4eed87de 3400 }
29b0f896
AM		 3401 }
3402 }
3403 }
3404 else if (i.tm.opcode_modifier & Modrm)
3405 {
3406 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3407 must be put into the modrm byte). Now, we make the modrm and
3408 index base bytes based on all the info we've collected. */
29b0f896
AM		 3409
3410 default_seg = build_modrm_byte ();
3411 }
8a2ed489 3412 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 3413 {
3414 default_seg = &ds;
3415 }
3416 else if ((i.tm.opcode_modifier & IsString) != 0)
3417 {
3418 /* For the string instructions that allow a segment override
3419 on one of their operands, the default segment is ds. */
3420 default_seg = &ds;
3421 }
3422
30123838
JB		 3423 if ((i.tm.base_opcode == 0x8d /* lea */
3424 || (i.tm.cpu_flags & CpuSVME))
3425 && i.seg[0] && !quiet_warnings)
3426 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3427
3428 /* If a segment was explicitly specified, and the specified segment
3429 is not the default, use an opcode prefix to select it. If we
3430 never figured out what the default segment is, then default_seg
3431 will be zero at this point, and the specified segment prefix will
3432 always be used. */
29b0f896
AM		 3433 if ((i.seg[0]) && (i.seg[0] != default_seg))
3434 {
3435 if (!add_prefix (i.seg[0]->seg_prefix))
3436 return 0;
3437 }
3438 return 1;
3439}
3440
3441static const seg_entry *
e3bb37b5 3442build_modrm_byte (void)
29b0f896
AM		 3443{
3444 const seg_entry *default_seg = 0;
3445
3446 /* i.reg_operands MUST be the number of real register operands;
3447 implicit registers do not count. */
3448 if (i.reg_operands == 2)
3449 {
3450 unsigned int source, dest;
cab737b9
L		 3451
3452 switch (i.operands)
3453 {
3454 case 2:
3455 source = 0;
3456 break;
3457 case 3:
c81128dc
L		 3458 /* When there are 3 operands, one of them may be immediate,
3459 which may be the first or the last operand. Otherwise,
3460 the first operand must be shift count register (cl). */
3461 assert (i.imm_operands == 1
3462 || (i.imm_operands == 0
3463 && (i.types[0] & ShiftCount)));
3464 source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0;
cab737b9
L		 3465 break;
3466 case 4:
3467 /* When there are 4 operands, the first two must be immediate
3468 operands. The source operand will be the 3rd one. */
3469 assert (i.imm_operands == 2
3470 && (i.types[0] & Imm)
3471 && (i.types[1] & Imm));
3472 source = 2;
3473 break;
3474 default:
3475 abort ();
3476 }
3477
29b0f896
AM		 3478 dest = source + 1;
3479
3480 i.rm.mode = 3;
3481 /* One of the register operands will be encoded in the i.tm.reg
3482 field, the other in the combined i.tm.mode and i.tm.regmem
3483 fields. If no form of this instruction supports a memory
3484 destination operand, then we assume the source operand may
3485 sometimes be a memory operand and so we need to store the
3486 destination in the i.rm.reg field. */
e72cf3ec 3487 if ((i.tm.operand_types[dest] & (AnyMem | RegMem)) == 0)
29b0f896
AM		 3488 {
3489 i.rm.reg = i.op[dest].regs->reg_num;
3490 i.rm.regmem = i.op[source].regs->reg_num;
3491 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 3492 i.rex |= REX_R;
29b0f896 3493 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 3494 i.rex |= REX_B;
29b0f896
AM		 3495 }
3496 else
3497 {
3498 i.rm.reg = i.op[source].regs->reg_num;
3499 i.rm.regmem = i.op[dest].regs->reg_num;
3500 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 3501 i.rex |= REX_B;
29b0f896 3502 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 3503 i.rex |= REX_R;
29b0f896 3504 }
161a04f6 3505 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5
JB		 3506 {
3507 if (!((i.types[0] | i.types[1]) & Control))
3508 abort ();
161a04f6 3509 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 3510 add_prefix (LOCK_PREFIX_OPCODE);
3511 }
29b0f896
AM		 3512 }
3513 else
3514 { /* If it's not 2 reg operands... */
3515 if (i.mem_operands)
3516 {
3517 unsigned int fake_zero_displacement = 0;
99018f42 3518 unsigned int op;
4eed87de 3519
99018f42
L		 3520 for (op = 0; op < i.operands; op++)
3521 if ((i.types[op] & AnyMem))
3522 break;
3523 assert (op < i.operands);
29b0f896
AM		 3524
3525 default_seg = &ds;
3526
3527 if (i.base_reg == 0)
3528 {
3529 i.rm.mode = 0;
3530 if (!i.disp_operands)
3531 fake_zero_displacement = 1;
3532 if (i.index_reg == 0)
3533 {
3534 /* Operand is just <disp> */
20f0a1fc 3535 if (flag_code == CODE_64BIT)
29b0f896
AM		 3536 {
3537 /* 64bit mode overwrites the 32bit absolute
3538 addressing by RIP relative addressing and
3539 absolute addressing is encoded by one of the
3540 redundant SIB forms. */
3541 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3542 i.sib.base = NO_BASE_REGISTER;
3543 i.sib.index = NO_INDEX_REGISTER;
fc225355
L		 3544 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3545 ? Disp32S : Disp32);
20f0a1fc 3546 }
fc225355
L		 3547 else if ((flag_code == CODE_16BIT)
3548 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 3549 {
3550 i.rm.regmem = NO_BASE_REGISTER_16;
3551 i.types[op] = Disp16;
3552 }
3553 else
3554 {
3555 i.rm.regmem = NO_BASE_REGISTER;
3556 i.types[op] = Disp32;
29b0f896
AM		 3557 }
3558 }
3559 else /* !i.base_reg && i.index_reg */
3560 {
3561 i.sib.index = i.index_reg->reg_num;
3562 i.sib.base = NO_BASE_REGISTER;
3563 i.sib.scale = i.log2_scale_factor;
3564 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3565 i.types[op] &= ~Disp;
3566 if (flag_code != CODE_64BIT)
3567 i.types[op] |= Disp32; /* Must be 32 bit */
3568 else
3569 i.types[op] |= Disp32S;
3570 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 3571 i.rex |= REX_X;
29b0f896
AM		 3572 }
3573 }
3574 /* RIP addressing for 64bit mode. */
3575 else if (i.base_reg->reg_type == BaseIndex)
3576 {
3577 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3578 i.types[op] &= ~ Disp;
29b0f896 3579 i.types[op] |= Disp32S;
71903a11 3580 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 3581 if (! i.disp_operands)
3582 fake_zero_displacement = 1;
29b0f896
AM		 3583 }
3584 else if (i.base_reg->reg_type & Reg16)
3585 {
3586 switch (i.base_reg->reg_num)
3587 {
3588 case 3: /* (%bx) */
3589 if (i.index_reg == 0)
3590 i.rm.regmem = 7;
3591 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3592 i.rm.regmem = i.index_reg->reg_num - 6;
3593 break;
3594 case 5: /* (%bp) */
3595 default_seg = &ss;
3596 if (i.index_reg == 0)
3597 {
3598 i.rm.regmem = 6;
3599 if ((i.types[op] & Disp) == 0)
3600 {
3601 /* fake (%bp) into 0(%bp) */
3602 i.types[op] |= Disp8;
252b5132 3603 fake_zero_displacement = 1;
29b0f896
AM		 3604 }
3605 }
3606 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3607 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3608 break;
3609 default: /* (%si) -> 4 or (%di) -> 5 */
3610 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3611 }
3612 i.rm.mode = mode_from_disp_size (i.types[op]);
3613 }
3614 else /* i.base_reg and 32/64 bit mode */
3615 {
3616 if (flag_code == CODE_64BIT
3617 && (i.types[op] & Disp))
fc225355
L		 3618 i.types[op] = ((i.types[op] & Disp8)
3619 | (i.prefix[ADDR_PREFIX] == 0
3620 ? Disp32S : Disp32));
20f0a1fc 3621
29b0f896
AM		 3622 i.rm.regmem = i.base_reg->reg_num;
3623 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 3624 i.rex |= REX_B;
29b0f896
AM		 3625 i.sib.base = i.base_reg->reg_num;
3626 /* x86-64 ignores REX prefix bit here to avoid decoder
3627 complications. */
3628 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3629 {
3630 default_seg = &ss;
3631 if (i.disp_operands == 0)
3632 {
3633 fake_zero_displacement = 1;
3634 i.types[op] |= Disp8;
3635 }
3636 }
3637 else if (i.base_reg->reg_num == ESP_REG_NUM)
3638 {
3639 default_seg = &ss;
3640 }
3641 i.sib.scale = i.log2_scale_factor;
3642 if (i.index_reg == 0)
3643 {
3644 /* <disp>(%esp) becomes two byte modrm with no index
3645 register. We've already stored the code for esp
3646 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3647 Any base register besides %esp will not use the
3648 extra modrm byte. */
3649 i.sib.index = NO_INDEX_REGISTER;
3650#if !SCALE1_WHEN_NO_INDEX
3651 /* Another case where we force the second modrm byte. */
3652 if (i.log2_scale_factor)
3653 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3654#endif
29b0f896
AM		 3655 }
3656 else
3657 {
3658 i.sib.index = i.index_reg->reg_num;
3659 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3660 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 3661 i.rex |= REX_X;
29b0f896 3662 }
67a4f2b7
AO		 3663
3664 if (i.disp_operands
3665 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3666 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3667 i.rm.mode = 0;
3668 else
3669 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3670 }
252b5132 3671
29b0f896
AM		 3672 if (fake_zero_displacement)
3673 {
3674 /* Fakes a zero displacement assuming that i.types[op]
3675 holds the correct displacement size. */
3676 expressionS *exp;
3677
3678 assert (i.op[op].disps == 0);
3679 exp = &disp_expressions[i.disp_operands++];
3680 i.op[op].disps = exp;
3681 exp->X_op = O_constant;
3682 exp->X_add_number = 0;
3683 exp->X_add_symbol = (symbolS *) 0;
3684 exp->X_op_symbol = (symbolS *) 0;
3685 }
3686 }
252b5132 3687
29b0f896
AM		 3688 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3689 (if any) based on i.tm.extension_opcode. Again, we must be
3690 careful to make sure that segment/control/debug/test/MMX
3691 registers are coded into the i.rm.reg field. */
3692 if (i.reg_operands)
3693 {
99018f42
L		 3694 unsigned int op;
3695
3696 for (op = 0; op < i.operands; op++)
3697 if ((i.types[op] & (Reg | RegMMX | RegXMM
3698 | SReg2 | SReg3
3699 | Control | Debug | Test)))
3700 break;
3701 assert (op < i.operands);
3702
29b0f896
AM		 3703 /* If there is an extension opcode to put here, the register
3704 number must be put into the regmem field. */
3705 if (i.tm.extension_opcode != None)
3706 {
3707 i.rm.regmem = i.op[op].regs->reg_num;
3708 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3709 i.rex |= REX_B;
29b0f896
AM		 3710 }
3711 else
3712 {
3713 i.rm.reg = i.op[op].regs->reg_num;
3714 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3715 i.rex |= REX_R;
29b0f896 3716 }
252b5132 3717
29b0f896
AM		 3718 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3719 must set it to 3 to indicate this is a register operand
3720 in the regmem field. */
3721 if (!i.mem_operands)
3722 i.rm.mode = 3;
3723 }
252b5132 3724
29b0f896
AM		 3725 /* Fill in i.rm.reg field with extension opcode (if any). */
3726 if (i.tm.extension_opcode != None)
3727 i.rm.reg = i.tm.extension_opcode;
3728 }
3729 return default_seg;
3730}
252b5132 3731
29b0f896 3732static void
e3bb37b5 3733output_branch (void)
29b0f896
AM		 3734{
3735 char *p;
3736 int code16;
3737 int prefix;
3738 relax_substateT subtype;
3739 symbolS *sym;
3740 offsetT off;
3741
3742 code16 = 0;
3743 if (flag_code == CODE_16BIT)
3744 code16 = CODE16;
3745
3746 prefix = 0;
3747 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3748 {
29b0f896
AM		 3749 prefix = 1;
3750 i.prefixes -= 1;
3751 code16 ^= CODE16;
252b5132 3752 }
29b0f896
AM		 3753 /* Pentium4 branch hints. */
3754 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3755 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3756 {
29b0f896
AM		 3757 prefix++;
3758 i.prefixes--;
3759 }
3760 if (i.prefix[REX_PREFIX] != 0)
3761 {
3762 prefix++;
3763 i.prefixes--;
2f66722d
AM		 3764 }
3765
29b0f896
AM		 3766 if (i.prefixes != 0 && !intel_syntax)
3767 as_warn (_("skipping prefixes on this instruction"));
3768
3769 /* It's always a symbol; End frag & setup for relax.
3770 Make sure there is enough room in this frag for the largest
3771 instruction we may generate in md_convert_frag. This is 2
3772 bytes for the opcode and room for the prefix and largest
3773 displacement. */
3774 frag_grow (prefix + 2 + 4);
3775 /* Prefix and 1 opcode byte go in fr_fix. */
3776 p = frag_more (prefix + 1);
3777 if (i.prefix[DATA_PREFIX] != 0)
3778 *p++ = DATA_PREFIX_OPCODE;
3779 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3780 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3781 *p++ = i.prefix[SEG_PREFIX];
3782 if (i.prefix[REX_PREFIX] != 0)
3783 *p++ = i.prefix[REX_PREFIX];
3784 *p = i.tm.base_opcode;
3785
3786 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3787 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3788 else if ((cpu_arch_flags & Cpu386) != 0)
3789 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3790 else
3791 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3792 subtype |= code16;
3e73aa7c 3793
29b0f896
AM		 3794 sym = i.op[0].disps->X_add_symbol;
3795 off = i.op[0].disps->X_add_number;
3e73aa7c 3796
29b0f896
AM		 3797 if (i.op[0].disps->X_op != O_constant
3798 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3799 {
29b0f896
AM		 3800 /* Handle complex expressions. */
3801 sym = make_expr_symbol (i.op[0].disps);
3802 off = 0;
3803 }
3e73aa7c 3804
29b0f896
AM		 3805 /* 1 possible extra opcode + 4 byte displacement go in var part.
3806 Pass reloc in fr_var. */
3807 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3808}
3e73aa7c 3809
29b0f896 3810static void
e3bb37b5 3811output_jump (void)
29b0f896
AM		 3812{
3813 char *p;
3814 int size;
3e02c1cc 3815 fixS *fixP;
29b0f896
AM		 3816
3817 if (i.tm.opcode_modifier & JumpByte)
3818 {
3819 /* This is a loop or jecxz type instruction. */
3820 size = 1;
3821 if (i.prefix[ADDR_PREFIX] != 0)
3822 {
3823 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3824 i.prefixes -= 1;
3825 }
3826 /* Pentium4 branch hints. */
3827 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3828 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3829 {
3830 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3831 i.prefixes--;
3e73aa7c
JH		 3832 }
3833 }
29b0f896
AM		 3834 else
3835 {
3836 int code16;
3e73aa7c 3837
29b0f896
AM		 3838 code16 = 0;
3839 if (flag_code == CODE_16BIT)
3840 code16 = CODE16;
3e73aa7c 3841
29b0f896
AM		 3842 if (i.prefix[DATA_PREFIX] != 0)
3843 {
3844 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3845 i.prefixes -= 1;
3846 code16 ^= CODE16;
3847 }
252b5132 3848
29b0f896
AM		 3849 size = 4;
3850 if (code16)
3851 size = 2;
3852 }
9fcc94b6 3853
29b0f896
AM		 3854 if (i.prefix[REX_PREFIX] != 0)
3855 {
3856 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3857 i.prefixes -= 1;
3858 }
252b5132 3859
29b0f896
AM		 3860 if (i.prefixes != 0 && !intel_syntax)
3861 as_warn (_("skipping prefixes on this instruction"));
e0890092 3862
29b0f896
AM		 3863 p = frag_more (1 + size);
3864 *p++ = i.tm.base_opcode;
e0890092 3865
3e02c1cc
AM		 3866 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3867 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3868
3869 /* All jumps handled here are signed, but don't use a signed limit
3870 check for 32 and 16 bit jumps as we want to allow wrap around at
3871 4G and 64k respectively. */
3872 if (size == 1)
3873 fixP->fx_signed = 1;
29b0f896 3874}
e0890092 3875
29b0f896 3876static void
e3bb37b5 3877output_interseg_jump (void)
29b0f896
AM		 3878{
3879 char *p;
3880 int size;
3881 int prefix;
3882 int code16;
252b5132 3883
29b0f896
AM		 3884 code16 = 0;
3885 if (flag_code == CODE_16BIT)
3886 code16 = CODE16;
a217f122 3887
29b0f896
AM		 3888 prefix = 0;
3889 if (i.prefix[DATA_PREFIX] != 0)
3890 {
3891 prefix = 1;
3892 i.prefixes -= 1;
3893 code16 ^= CODE16;
3894 }
3895 if (i.prefix[REX_PREFIX] != 0)
3896 {
3897 prefix++;
3898 i.prefixes -= 1;
3899 }
252b5132 3900
29b0f896
AM		 3901 size = 4;
3902 if (code16)
3903 size = 2;
252b5132 3904
29b0f896
AM		 3905 if (i.prefixes != 0 && !intel_syntax)
3906 as_warn (_("skipping prefixes on this instruction"));
252b5132 3907
29b0f896
AM		 3908 /* 1 opcode; 2 segment; offset */
3909 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3910
29b0f896
AM		 3911 if (i.prefix[DATA_PREFIX] != 0)
3912 *p++ = DATA_PREFIX_OPCODE;
252b5132 3913
29b0f896
AM		 3914 if (i.prefix[REX_PREFIX] != 0)
3915 *p++ = i.prefix[REX_PREFIX];
252b5132 3916
29b0f896
AM		 3917 *p++ = i.tm.base_opcode;
3918 if (i.op[1].imms->X_op == O_constant)
3919 {
3920 offsetT n = i.op[1].imms->X_add_number;
252b5132 3921
29b0f896
AM		 3922 if (size == 2
3923 && !fits_in_unsigned_word (n)
3924 && !fits_in_signed_word (n))
3925 {
3926 as_bad (_("16-bit jump out of range"));
3927 return;
3928 }
3929 md_number_to_chars (p, n, size);
3930 }
3931 else
3932 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3933 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3934 if (i.op[0].imms->X_op != O_constant)
3935 as_bad (_("can't handle non absolute segment in `%s'"),
3936 i.tm.name);
3937 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3938}
a217f122 3939
29b0f896 3940static void
e3bb37b5 3941output_insn (void)
29b0f896 3942{
2bbd9c25
JJ		 3943 fragS *insn_start_frag;
3944 offsetT insn_start_off;
3945
29b0f896
AM		 3946 /* Tie dwarf2 debug info to the address at the start of the insn.
3947 We can't do this after the insn has been output as the current
3948 frag may have been closed off. eg. by frag_var. */
3949 dwarf2_emit_insn (0);
3950
2bbd9c25
JJ		 3951 insn_start_frag = frag_now;
3952 insn_start_off = frag_now_fix ();
3953
29b0f896
AM		 3954 /* Output jumps. */
3955 if (i.tm.opcode_modifier & Jump)
3956 output_branch ();
3957 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3958 output_jump ();
3959 else if (i.tm.opcode_modifier & JumpInterSegment)
3960 output_interseg_jump ();
3961 else
3962 {
3963 /* Output normal instructions here. */
3964 char *p;
3965 unsigned char *q;
331d2d0d 3966 unsigned int prefix;
252b5132 3967
42903f7f 3968 /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and
381d071f
L		 3969 SSE4 instructions have 3 bytes. We may use one more higher
3970 byte to specify a prefix the instruction requires. Exclude
3971 instructions which are in both SSE4 and ABM. */
3972 if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4)) != 0
3973 && (i.tm.cpu_flags & CpuABM) == 0)
bc4bd9ab 3974 {
331d2d0d
L		 3975 if (i.tm.base_opcode & 0xff000000)
3976 {
3977 prefix = (i.tm.base_opcode >> 24) & 0xff;
3978 goto check_prefix;
3979 }
3980 }
3981 else if ((i.tm.base_opcode & 0xff0000) != 0)
3982 {
3983 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 3984 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3985 {
64e74474 3986 check_prefix:
bc4bd9ab
MK		 3987 if (prefix != REPE_PREFIX_OPCODE
3988 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3989 add_prefix (prefix);
3990 }
3991 else
331d2d0d 3992 add_prefix (prefix);
0f10071e 3993 }
252b5132 3994
29b0f896
AM		 3995 /* The prefix bytes. */
3996 for (q = i.prefix;
3997 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3998 q++)
3999 {
4000 if (*q)
4001 {
4002 p = frag_more (1);
4003 md_number_to_chars (p, (valueT) *q, 1);
4004 }
4005 }
252b5132 4006
29b0f896
AM		 4007 /* Now the opcode; be careful about word order here! */
4008 if (fits_in_unsigned_byte (i.tm.base_opcode))
4009 {
4010 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
4011 }
4012 else
4013 {
381d071f
L		 4014 if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4)) != 0
4015 && (i.tm.cpu_flags & CpuABM) == 0)
331d2d0d
L		 4016 {
4017 p = frag_more (3);
4018 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4019 }
4020 else
4021 p = frag_more (2);
0f10071e 4022
29b0f896
AM		 4023 /* Put out high byte first: can't use md_number_to_chars! */
4024 *p++ = (i.tm.base_opcode >> 8) & 0xff;
4025 *p = i.tm.base_opcode & 0xff;
4026 }
3e73aa7c 4027
29b0f896
AM		 4028 /* Now the modrm byte and sib byte (if present). */
4029 if (i.tm.opcode_modifier & Modrm)
4030 {
4031 p = frag_more (1);
4032 md_number_to_chars (p,
4033 (valueT) (i.rm.regmem << 0
4034 | i.rm.reg << 3
4035 | i.rm.mode << 6),
4036 1);
4037 /* If i.rm.regmem == ESP (4)
4038 && i.rm.mode != (Register mode)
4039 && not 16 bit
4040 ==> need second modrm byte. */
4041 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
4042 && i.rm.mode != 3
4043 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
4044 {
4045 p = frag_more (1);
4046 md_number_to_chars (p,
4047 (valueT) (i.sib.base << 0
4048 | i.sib.index << 3
4049 | i.sib.scale << 6),
4050 1);
4051 }
4052 }
3e73aa7c 4053
29b0f896 4054 if (i.disp_operands)
2bbd9c25 4055 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 4056
29b0f896 4057 if (i.imm_operands)
2bbd9c25 4058 output_imm (insn_start_frag, insn_start_off);
29b0f896 4059 }
252b5132 4060
29b0f896
AM		 4061#ifdef DEBUG386
4062 if (flag_debug)
4063 {
7b81dfbb 4064 pi ("" /*line*/, &i);
29b0f896
AM		 4065 }
4066#endif /* DEBUG386 */
4067}
252b5132 4068
29b0f896 4069static void
64e74474 4070output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4071{
4072 char *p;
4073 unsigned int n;
252b5132 4074
29b0f896
AM		 4075 for (n = 0; n < i.operands; n++)
4076 {
4077 if (i.types[n] & Disp)
4078 {
4079 if (i.op[n].disps->X_op == O_constant)
4080 {
4081 int size;
4082 offsetT val;
252b5132 4083
29b0f896
AM		 4084 size = 4;
4085 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4086 {
4087 size = 2;
4088 if (i.types[n] & Disp8)
4089 size = 1;
4090 if (i.types[n] & Disp64)
4091 size = 8;
4092 }
4093 val = offset_in_range (i.op[n].disps->X_add_number,
4094 size);
4095 p = frag_more (size);
4096 md_number_to_chars (p, val, size);
4097 }
4098 else
4099 {
f86103b7 4100 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4101 int size = 4;
4102 int sign = 0;
4103 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4104
4105 /* The PC relative address is computed relative
4106 to the instruction boundary, so in case immediate
4107 fields follows, we need to adjust the value. */
4108 if (pcrel && i.imm_operands)
4109 {
4110 int imm_size = 4;
4111 unsigned int n1;
252b5132 4112
29b0f896
AM		 4113 for (n1 = 0; n1 < i.operands; n1++)
4114 if (i.types[n1] & Imm)
252b5132 4115 {
29b0f896 4116 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 4117 {
29b0f896
AM		 4118 imm_size = 2;
4119 if (i.types[n1] & (Imm8 | Imm8S))
4120 imm_size = 1;
4121 if (i.types[n1] & Imm64)
4122 imm_size = 8;
252b5132 4123 }
29b0f896 4124 break;
252b5132 4125 }
29b0f896
AM		 4126 /* We should find the immediate. */
4127 if (n1 == i.operands)
4128 abort ();
4129 i.op[n].disps->X_add_number -= imm_size;
4130 }
520dc8e8 4131
29b0f896
AM		 4132 if (i.types[n] & Disp32S)
4133 sign = 1;
3e73aa7c 4134
29b0f896
AM		 4135 if (i.types[n] & (Disp16 | Disp64))
4136 {
4137 size = 2;
4138 if (i.types[n] & Disp64)
4139 size = 8;
4140 }
520dc8e8 4141
29b0f896 4142 p = frag_more (size);
2bbd9c25 4143 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4144 if (GOT_symbol
2bbd9c25 4145 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4146 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4147 || reloc_type == BFD_RELOC_X86_64_32S
4148 || (reloc_type == BFD_RELOC_64
4149 && object_64bit))
d6ab8113
JB		 4150 && (i.op[n].disps->X_op == O_symbol
4151 || (i.op[n].disps->X_op == O_add
4152 && ((symbol_get_value_expression
4153 (i.op[n].disps->X_op_symbol)->X_op)
4154 == O_subtract))))
4155 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4156 {
4157 offsetT add;
4158
4159 if (insn_start_frag == frag_now)
4160 add = (p - frag_now->fr_literal) - insn_start_off;
4161 else
4162 {
4163 fragS *fr;
4164
4165 add = insn_start_frag->fr_fix - insn_start_off;
4166 for (fr = insn_start_frag->fr_next;
4167 fr && fr != frag_now; fr = fr->fr_next)
4168 add += fr->fr_fix;
4169 add += p - frag_now->fr_literal;
4170 }
4171
4fa24527 4172 if (!object_64bit)
7b81dfbb
AJ		 4173 {
4174 reloc_type = BFD_RELOC_386_GOTPC;
4175 i.op[n].imms->X_add_number += add;
4176 }
4177 else if (reloc_type == BFD_RELOC_64)
4178 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4179 else
7b81dfbb
AJ		 4180 /* Don't do the adjustment for x86-64, as there
4181 the pcrel addressing is relative to the _next_
4182 insn, and that is taken care of in other code. */
d6ab8113 4183 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4184 }
062cd5e7 4185 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4186 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4187 }
4188 }
4189 }
4190}
252b5132 4191
29b0f896 4192static void
64e74474 4193output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4194{
4195 char *p;
4196 unsigned int n;
252b5132 4197
29b0f896
AM		 4198 for (n = 0; n < i.operands; n++)
4199 {
4200 if (i.types[n] & Imm)
4201 {
4202 if (i.op[n].imms->X_op == O_constant)
4203 {
4204 int size;
4205 offsetT val;
b4cac588 4206
29b0f896
AM		 4207 size = 4;
4208 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4209 {
4210 size = 2;
4211 if (i.types[n] & (Imm8 | Imm8S))
4212 size = 1;
4213 else if (i.types[n] & Imm64)
4214 size = 8;
4215 }
4216 val = offset_in_range (i.op[n].imms->X_add_number,
4217 size);
4218 p = frag_more (size);
4219 md_number_to_chars (p, val, size);
4220 }
4221 else
4222 {
4223 /* Not absolute_section.
4224 Need a 32-bit fixup (don't support 8bit
4225 non-absolute imms). Try to support other
4226 sizes ... */
f86103b7 4227 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4228 int size = 4;
4229 int sign = 0;
4230
4231 if ((i.types[n] & (Imm32S))
a7d61044
JB		 4232 && (i.suffix == QWORD_MNEM_SUFFIX
4233 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 4234 sign = 1;
4235 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4236 {
4237 size = 2;
4238 if (i.types[n] & (Imm8 | Imm8S))
4239 size = 1;
4240 if (i.types[n] & Imm64)
4241 size = 8;
4242 }
520dc8e8 4243
29b0f896
AM		 4244 p = frag_more (size);
4245 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4246
2bbd9c25
JJ		 4247 /* This is tough to explain. We end up with this one if we
4248 * have operands that look like
4249 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4250 * obtain the absolute address of the GOT, and it is strongly
4251 * preferable from a performance point of view to avoid using
4252 * a runtime relocation for this. The actual sequence of
4253 * instructions often look something like:
4254 *
4255 * call .L66
4256 * .L66:
4257 * popl %ebx
4258 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4259 *
4260 * The call and pop essentially return the absolute address
4261 * of the label .L66 and store it in %ebx. The linker itself
4262 * will ultimately change the first operand of the addl so
4263 * that %ebx points to the GOT, but to keep things simple, the
4264 * .o file must have this operand set so that it generates not
4265 * the absolute address of .L66, but the absolute address of
4266 * itself. This allows the linker itself simply treat a GOTPC
4267 * relocation as asking for a pcrel offset to the GOT to be
4268 * added in, and the addend of the relocation is stored in the
4269 * operand field for the instruction itself.
4270 *
4271 * Our job here is to fix the operand so that it would add
4272 * the correct offset so that %ebx would point to itself. The
4273 * thing that is tricky is that .-.L66 will point to the
4274 * beginning of the instruction, so we need to further modify
4275 * the operand so that it will point to itself. There are
4276 * other cases where you have something like:
4277 *
4278 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4279 *
4280 * and here no correction would be required. Internally in
4281 * the assembler we treat operands of this form as not being
4282 * pcrel since the '.' is explicitly mentioned, and I wonder
4283 * whether it would simplify matters to do it this way. Who
4284 * knows. In earlier versions of the PIC patches, the
4285 * pcrel_adjust field was used to store the correction, but
4286 * since the expression is not pcrel, I felt it would be
4287 * confusing to do it this way. */
4288
d6ab8113 4289 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4290 || reloc_type == BFD_RELOC_X86_64_32S
4291 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4292 && GOT_symbol
4293 && GOT_symbol == i.op[n].imms->X_add_symbol
4294 && (i.op[n].imms->X_op == O_symbol
4295 || (i.op[n].imms->X_op == O_add
4296 && ((symbol_get_value_expression
4297 (i.op[n].imms->X_op_symbol)->X_op)
4298 == O_subtract))))
4299 {
2bbd9c25
JJ		 4300 offsetT add;
4301
4302 if (insn_start_frag == frag_now)
4303 add = (p - frag_now->fr_literal) - insn_start_off;
4304 else
4305 {
4306 fragS *fr;
4307
4308 add = insn_start_frag->fr_fix - insn_start_off;
4309 for (fr = insn_start_frag->fr_next;
4310 fr && fr != frag_now; fr = fr->fr_next)
4311 add += fr->fr_fix;
4312 add += p - frag_now->fr_literal;
4313 }
4314
4fa24527 4315 if (!object_64bit)
d6ab8113 4316 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4317 else if (size == 4)
d6ab8113 4318 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4319 else if (size == 8)
4320 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4321 i.op[n].imms->X_add_number += add;
29b0f896 4322 }
29b0f896
AM		 4323 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4324 i.op[n].imms, 0, reloc_type);
4325 }
4326 }
4327 }
252b5132
RH		 4328}
4329\f
d182319b
JB		 4330/* x86_cons_fix_new is called via the expression parsing code when a
4331 reloc is needed. We use this hook to get the correct .got reloc. */
4332static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4333static int cons_sign = -1;
4334
4335void
e3bb37b5 4336x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 4337 expressionS *exp)
d182319b
JB		 4338{
4339 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4340
4341 got_reloc = NO_RELOC;
4342
4343#ifdef TE_PE
4344 if (exp->X_op == O_secrel)
4345 {
4346 exp->X_op = O_symbol;
4347 r = BFD_RELOC_32_SECREL;
4348 }
4349#endif
4350
4351 fix_new_exp (frag, off, len, exp, 0, r);
4352}
4353
718ddfc0
JB		 4354#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4355# define lex_got(reloc, adjust, types) NULL
4356#else
f3c180ae
AM		 4357/* Parse operands of the form
4358 <symbol>@GOTOFF+<nnn>
4359 and similar .plt or .got references.
4360
4361 If we find one, set up the correct relocation in RELOC and copy the
4362 input string, minus the `@GOTOFF' into a malloc'd buffer for
4363 parsing by the calling routine. Return this buffer, and if ADJUST
4364 is non-null set it to the length of the string we removed from the
4365 input line. Otherwise return NULL. */
4366static char *
3956db08 4367lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 4368 int *adjust,
4369 unsigned int *types)
f3c180ae 4370{
7b81dfbb
AJ		 4371 /* Some of the relocations depend on the size of what field is to
4372 be relocated. But in our callers i386_immediate and i386_displacement
4373 we don't yet know the operand size (this will be set by insn
4374 matching). Hence we record the word32 relocation here,
4375 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4376 static const struct {
4377 const char *str;
4fa24527 4378 const enum bfd_reloc_code_real rel[2];
3956db08 4379 const unsigned int types64;
f3c180ae 4380 } gotrel[] = {
4eed87de
AM		 4381 { "PLTOFF", { 0,
4382 BFD_RELOC_X86_64_PLTOFF64 },
4383 Imm64 },
4384 { "PLT", { BFD_RELOC_386_PLT32,
4385 BFD_RELOC_X86_64_PLT32 },
4386 Imm32 | Imm32S | Disp32 },
4387 { "GOTPLT", { 0,
4388 BFD_RELOC_X86_64_GOTPLT64 },
4389 Imm64 | Disp64 },
4390 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
4391 BFD_RELOC_X86_64_GOTOFF64 },
4392 Imm64 | Disp64 },
4393 { "GOTPCREL", { 0,
4394 BFD_RELOC_X86_64_GOTPCREL },
4395 Imm32 | Imm32S | Disp32 },
4396 { "TLSGD", { BFD_RELOC_386_TLS_GD,
4397 BFD_RELOC_X86_64_TLSGD },
4398 Imm32 | Imm32S | Disp32 },
4399 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
4400 0 },
4401 0 },
4402 { "TLSLD", { 0,
4403 BFD_RELOC_X86_64_TLSLD },
4404 Imm32 | Imm32S | Disp32 },
4405 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
4406 BFD_RELOC_X86_64_GOTTPOFF },
4407 Imm32 | Imm32S | Disp32 },
4408 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
4409 BFD_RELOC_X86_64_TPOFF32 },
4410 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4411 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
4412 0 },
4413 0 },
4414 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
4415 BFD_RELOC_X86_64_DTPOFF32 },
4416 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4417 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
4418 0 },
4419 0 },
4420 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
4421 0 },
4422 0 },
4423 { "GOT", { BFD_RELOC_386_GOT32,
4424 BFD_RELOC_X86_64_GOT32 },
4425 Imm32 | Imm32S | Disp32 | Imm64 },
4426 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
4427 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
4428 Imm32 | Imm32S | Disp32 },
4429 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
4430 BFD_RELOC_X86_64_TLSDESC_CALL },
4431 Imm32 | Imm32S | Disp32 }
f3c180ae
AM		 4432 };
4433 char *cp;
4434 unsigned int j;
4435
718ddfc0
JB		 4436 if (!IS_ELF)
4437 return NULL;
4438
f3c180ae
AM		 4439 for (cp = input_line_pointer; *cp != '@'; cp++)
4440 if (is_end_of_line[(unsigned char) *cp])
4441 return NULL;
4442
4443 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4444 {
4445 int len;
4446
4447 len = strlen (gotrel[j].str);
28f81592 4448 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4449 {
4fa24527 4450 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4451 {
28f81592
AM		 4452 int first, second;
4453 char *tmpbuf, *past_reloc;
f3c180ae 4454
4fa24527 4455 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 4456 if (adjust)
4457 *adjust = len;
f3c180ae 4458
3956db08
JB		 4459 if (types)
4460 {
4461 if (flag_code != CODE_64BIT)
4eed87de 4462 *types = Imm32 | Disp32;
3956db08
JB		 4463 else
4464 *types = gotrel[j].types64;
4465 }
4466
f3c180ae
AM		 4467 if (GOT_symbol == NULL)
4468 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4469
4470 /* Replace the relocation token with ' ', so that
4471 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 4472
4473 /* The length of the first part of our input line. */
f3c180ae 4474 first = cp - input_line_pointer;
28f81592
AM		 4475
4476 /* The second part goes from after the reloc token until
4477 (and including) an end_of_line char. Don't use strlen
4478 here as the end_of_line char may not be a NUL. */
4479 past_reloc = cp + 1 + len;
4480 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4481 ;
4482 second = cp - past_reloc;
4483
4484 /* Allocate and copy string. The trailing NUL shouldn't
4485 be necessary, but be safe. */
4486 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 4487 memcpy (tmpbuf, input_line_pointer, first);
4488 tmpbuf[first] = ' ';
28f81592
AM		 4489 memcpy (tmpbuf + first + 1, past_reloc, second);
4490 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 4491 return tmpbuf;
4492 }
4493
4fa24527
JB		 4494 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4495 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 4496 return NULL;
4497 }
4498 }
4499
4500 /* Might be a symbol version string. Don't as_bad here. */
4501 return NULL;
4502}
4503
f3c180ae 4504void
e3bb37b5 4505x86_cons (expressionS *exp, int size)
f3c180ae 4506{
4fa24527 4507 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 4508 {
4509 /* Handle @GOTOFF and the like in an expression. */
4510 char *save;
4511 char *gotfree_input_line;
4512 int adjust;
4513
4514 save = input_line_pointer;
3956db08 4515 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4516 if (gotfree_input_line)
4517 input_line_pointer = gotfree_input_line;
4518
4519 expression (exp);
4520
4521 if (gotfree_input_line)
4522 {
4523 /* expression () has merrily parsed up to the end of line,
4524 or a comma - in the wrong buffer. Transfer how far
4525 input_line_pointer has moved to the right buffer. */
4526 input_line_pointer = (save
4527 + (input_line_pointer - gotfree_input_line)
4528 + adjust);
4529 free (gotfree_input_line);
4530 }
4531 }
4532 else
4533 expression (exp);
4534}
4535#endif
4536
d182319b 4537static void signed_cons (int size)
6482c264 4538{
d182319b
JB		 4539 if (flag_code == CODE_64BIT)
4540 cons_sign = 1;
4541 cons (size);
4542 cons_sign = -1;
6482c264
NC		 4543}
4544
d182319b 4545#ifdef TE_PE
6482c264
NC		 4546static void
4547pe_directive_secrel (dummy)
4548 int dummy ATTRIBUTE_UNUSED;
4549{
4550 expressionS exp;
4551
4552 do
4553 {
4554 expression (&exp);
4555 if (exp.X_op == O_symbol)
4556 exp.X_op = O_secrel;
4557
4558 emit_expr (&exp, 4);
4559 }
4560 while (*input_line_pointer++ == ',');
4561
4562 input_line_pointer--;
4563 demand_empty_rest_of_line ();
4564}
6482c264
NC		 4565#endif
4566
252b5132 4567static int
70e41ade 4568i386_immediate (char *imm_start)
252b5132
RH		 4569{
4570 char *save_input_line_pointer;
f3c180ae 4571 char *gotfree_input_line;
252b5132 4572 segT exp_seg = 0;
47926f60 4573 expressionS *exp;
3956db08 4574 unsigned int types = ~0U;
252b5132
RH		 4575
4576 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4577 {
31b2323c
L		 4578 as_bad (_("at most %d immediate operands are allowed"),
4579 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 4580 return 0;
4581 }
4582
4583 exp = &im_expressions[i.imm_operands++];
520dc8e8 4584 i.op[this_operand].imms = exp;
252b5132
RH		 4585
4586 if (is_space_char (*imm_start))
4587 ++imm_start;
4588
4589 save_input_line_pointer = input_line_pointer;
4590 input_line_pointer = imm_start;
4591
3956db08 4592 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4593 if (gotfree_input_line)
4594 input_line_pointer = gotfree_input_line;
252b5132
RH		 4595
4596 exp_seg = expression (exp);
4597
83183c0c 4598 SKIP_WHITESPACE ();
252b5132 4599 if (*input_line_pointer)
f3c180ae 4600 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4601
4602 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4603 if (gotfree_input_line)
4604 free (gotfree_input_line);
252b5132 4605
2daf4fd8 4606 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4607 {
47926f60 4608 /* Missing or bad expr becomes absolute 0. */
d0b47220 4609 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4610 imm_start);
252b5132
RH		 4611 exp->X_op = O_constant;
4612 exp->X_add_number = 0;
4613 exp->X_add_symbol = (symbolS *) 0;
4614 exp->X_op_symbol = (symbolS *) 0;
252b5132 4615 }
3e73aa7c 4616 else if (exp->X_op == O_constant)
252b5132 4617 {
47926f60 4618 /* Size it properly later. */
3e73aa7c
JH		 4619 i.types[this_operand] |= Imm64;
4620 /* If BFD64, sign extend val. */
4eed87de
AM		 4621 if (!use_rela_relocations
4622 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4623 exp->X_add_number
4624 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4625 }
4c63da97 4626#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4627 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4628 && exp_seg != absolute_section
47926f60 4629 && exp_seg != text_section
24eab124
AM		 4630 && exp_seg != data_section
4631 && exp_seg != bss_section
4632 && exp_seg != undefined_section
f86103b7 4633 && !bfd_is_com_section (exp_seg))
252b5132 4634 {
d0b47220 4635 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4636 return 0;
4637 }
4638#endif
bb8f5920
L		 4639 else if (!intel_syntax && exp->X_op == O_register)
4640 {
4641 as_bad (_("illegal immediate register operand %s"), imm_start);
4642 return 0;
4643 }
252b5132
RH		 4644 else
4645 {
4646 /* This is an address. The size of the address will be
24eab124 4647 determined later, depending on destination register,
3e73aa7c
JH		 4648 suffix, or the default for the section. */
4649 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4650 i.types[this_operand] &= types;
252b5132
RH		 4651 }
4652
4653 return 1;
4654}
4655
551c1ca1 4656static char *
e3bb37b5 4657i386_scale (char *scale)
252b5132 4658{
551c1ca1
AM		 4659 offsetT val;
4660 char *save = input_line_pointer;
252b5132 4661
551c1ca1
AM		 4662 input_line_pointer = scale;
4663 val = get_absolute_expression ();
4664
4665 switch (val)
252b5132 4666 {
551c1ca1 4667 case 1:
252b5132
RH		 4668 i.log2_scale_factor = 0;
4669 break;
551c1ca1 4670 case 2:
252b5132
RH		 4671 i.log2_scale_factor = 1;
4672 break;
551c1ca1 4673 case 4:
252b5132
RH		 4674 i.log2_scale_factor = 2;
4675 break;
551c1ca1 4676 case 8:
252b5132
RH		 4677 i.log2_scale_factor = 3;
4678 break;
4679 default:
a724f0f4
JB		 4680 {
4681 char sep = *input_line_pointer;
4682
4683 *input_line_pointer = '\0';
4684 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4685 scale);
4686 *input_line_pointer = sep;
4687 input_line_pointer = save;
4688 return NULL;
4689 }
252b5132 4690 }
29b0f896 4691 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4692 {
4693 as_warn (_("scale factor of %d without an index register"),
24eab124 4694 1 << i.log2_scale_factor);
252b5132
RH		 4695#if SCALE1_WHEN_NO_INDEX
4696 i.log2_scale_factor = 0;
4697#endif
4698 }
551c1ca1
AM		 4699 scale = input_line_pointer;
4700 input_line_pointer = save;
4701 return scale;
252b5132
RH		 4702}
4703
252b5132 4704static int
e3bb37b5 4705i386_displacement (char *disp_start, char *disp_end)
252b5132 4706{
29b0f896 4707 expressionS *exp;
252b5132
RH		 4708 segT exp_seg = 0;
4709 char *save_input_line_pointer;
f3c180ae 4710 char *gotfree_input_line;
e05278af 4711 int bigdisp, override;
3956db08 4712 unsigned int types = Disp;
252b5132 4713
31b2323c
L		 4714 if (i.disp_operands == MAX_MEMORY_OPERANDS)
4715 {
4716 as_bad (_("at most %d displacement operands are allowed"),
4717 MAX_MEMORY_OPERANDS);
4718 return 0;
4719 }
4720
e05278af
JB		 4721 if ((i.types[this_operand] & JumpAbsolute)
4722 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4723 {
4724 bigdisp = Disp32;
4725 override = (i.prefix[ADDR_PREFIX] != 0);
4726 }
4727 else
4728 {
4729 /* For PC-relative branches, the width of the displacement
4730 is dependent upon data size, not address size. */
4731 bigdisp = 0;
4732 override = (i.prefix[DATA_PREFIX] != 0);
4733 }
3e73aa7c 4734 if (flag_code == CODE_64BIT)
7ecd2f8b 4735 {
e05278af 4736 if (!bigdisp)
64e74474
AM		 4737 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4738 ? Disp16
4739 : Disp32S | Disp32);
e05278af 4740 else if (!override)
3956db08 4741 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4742 }
e05278af
JB		 4743 else
4744 {
4745 if (!bigdisp)
4746 {
4747 if (!override)
4748 override = (i.suffix == (flag_code != CODE_16BIT
4749 ? WORD_MNEM_SUFFIX
4750 : LONG_MNEM_SUFFIX));
4751 bigdisp = Disp32;
4752 }
4753 if ((flag_code == CODE_16BIT) ^ override)
4754 bigdisp = Disp16;
4755 }
252b5132
RH		 4756 i.types[this_operand] |= bigdisp;
4757
4758 exp = &disp_expressions[i.disp_operands];
520dc8e8 4759 i.op[this_operand].disps = exp;
252b5132
RH		 4760 i.disp_operands++;
4761 save_input_line_pointer = input_line_pointer;
4762 input_line_pointer = disp_start;
4763 END_STRING_AND_SAVE (disp_end);
4764
4765#ifndef GCC_ASM_O_HACK
4766#define GCC_ASM_O_HACK 0
4767#endif
4768#if GCC_ASM_O_HACK
4769 END_STRING_AND_SAVE (disp_end + 1);
4770 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4771 && displacement_string_end[-1] == '+')
252b5132
RH		 4772 {
4773 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4774 constraint within gcc asm statements.
4775 For instance:
4776
4777 #define _set_tssldt_desc(n,addr,limit,type) \
4778 __asm__ __volatile__ ( \
4779 "movw %w2,%0\n\t" \
4780 "movw %w1,2+%0\n\t" \
4781 "rorl $16,%1\n\t" \
4782 "movb %b1,4+%0\n\t" \
4783 "movb %4,5+%0\n\t" \
4784 "movb $0,6+%0\n\t" \
4785 "movb %h1,7+%0\n\t" \
4786 "rorl $16,%1" \
4787 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4788
4789 This works great except that the output assembler ends
4790 up looking a bit weird if it turns out that there is
4791 no offset. You end up producing code that looks like:
4792
4793 #APP
4794 movw $235,(%eax)
4795 movw %dx,2+(%eax)
4796 rorl $16,%edx
4797 movb %dl,4+(%eax)
4798 movb $137,5+(%eax)
4799 movb $0,6+(%eax)
4800 movb %dh,7+(%eax)
4801 rorl $16,%edx
4802 #NO_APP
4803
47926f60 4804 So here we provide the missing zero. */
24eab124
AM		 4805
4806 *displacement_string_end = '0';
252b5132
RH		 4807 }
4808#endif
3956db08 4809 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4810 if (gotfree_input_line)
4811 input_line_pointer = gotfree_input_line;
252b5132 4812
24eab124 4813 exp_seg = expression (exp);
252b5132 4814
636c26b0
AM		 4815 SKIP_WHITESPACE ();
4816 if (*input_line_pointer)
4817 as_bad (_("junk `%s' after expression"), input_line_pointer);
4818#if GCC_ASM_O_HACK
4819 RESTORE_END_STRING (disp_end + 1);
4820#endif
4821 RESTORE_END_STRING (disp_end);
4822 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4823 if (gotfree_input_line)
4824 free (gotfree_input_line);
636c26b0 4825
24eab124
AM		 4826 /* We do this to make sure that the section symbol is in
4827 the symbol table. We will ultimately change the relocation
47926f60 4828 to be relative to the beginning of the section. */
1ae12ab7 4829 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4830 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4831 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4832 {
636c26b0
AM		 4833 if (exp->X_op != O_symbol)
4834 {
4835 as_bad (_("bad expression used with @%s"),
4836 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4837 ? "GOTPCREL"
4838 : "GOTOFF"));
4839 return 0;
4840 }
4841
e5cb08ac 4842 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4843 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4844 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4845 exp->X_op = O_subtract;
4846 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4847 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4848 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4849 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4850 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4851 else
29b0f896 4852 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4853 }
252b5132 4854
2daf4fd8
AM		 4855 if (exp->X_op == O_absent || exp->X_op == O_big)
4856 {
47926f60 4857 /* Missing or bad expr becomes absolute 0. */
d0b47220 4858 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4859 disp_start);
4860 exp->X_op = O_constant;
4861 exp->X_add_number = 0;
4862 exp->X_add_symbol = (symbolS *) 0;
4863 exp->X_op_symbol = (symbolS *) 0;
4864 }
4865
4c63da97 4866#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4867 if (exp->X_op != O_constant
45288df1 4868 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4869 && exp_seg != absolute_section
45288df1
AM		 4870 && exp_seg != text_section
4871 && exp_seg != data_section
4872 && exp_seg != bss_section
31312f95 4873 && exp_seg != undefined_section
f86103b7 4874 && !bfd_is_com_section (exp_seg))
24eab124 4875 {
d0b47220 4876 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4877 return 0;
4878 }
252b5132 4879#endif
3956db08
JB		 4880
4881 if (!(i.types[this_operand] & ~Disp))
4882 i.types[this_operand] &= types;
4883
252b5132
RH		 4884 return 1;
4885}
4886
eecb386c 4887/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4888 Return 1 on success, 0 on a failure. */
4889
252b5132 4890static int
e3bb37b5 4891i386_index_check (const char *operand_string)
252b5132 4892{
3e73aa7c 4893 int ok;
24eab124 4894#if INFER_ADDR_PREFIX
eecb386c
AM		 4895 int fudged = 0;
4896
24eab124
AM		 4897 tryprefix:
4898#endif
3e73aa7c 4899 ok = 1;
30123838
JB		 4900 if ((current_templates->start->cpu_flags & CpuSVME)
4901 && current_templates->end[-1].operand_types[0] == AnyMem)
4902 {
4903 /* Memory operands of SVME insns are special in that they only allow
4904 rAX as their memory address and ignore any segment override. */
4905 unsigned RegXX;
4906
4907 /* SKINIT is even more restrictive: it always requires EAX. */
4908 if (strcmp (current_templates->start->name, "skinit") == 0)
4909 RegXX = Reg32;
4910 else if (flag_code == CODE_64BIT)
4911 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4912 else
64e74474
AM		 4913 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4914 ? Reg16
4915 : Reg32);
30123838
JB		 4916 if (!i.base_reg
4917 || !(i.base_reg->reg_type & Acc)
4918 || !(i.base_reg->reg_type & RegXX)
4919 || i.index_reg
4920 || (i.types[0] & Disp))
4921 ok = 0;
4922 }
4923 else if (flag_code == CODE_64BIT)
64e74474
AM		 4924 {
4925 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4926
4927 if ((i.base_reg
4928 && ((i.base_reg->reg_type & RegXX) == 0)
4929 && (i.base_reg->reg_type != BaseIndex
4930 || i.index_reg))
4931 || (i.index_reg
4932 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4933 != (RegXX | BaseIndex))))
4934 ok = 0;
3e73aa7c
JH		 4935 }
4936 else
4937 {
4938 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4939 {
4940 /* 16bit checks. */
4941 if ((i.base_reg
29b0f896
AM		 4942 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4943 != (Reg16 | BaseIndex)))
3e73aa7c 4944 || (i.index_reg
29b0f896
AM		 4945 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4946 != (Reg16 | BaseIndex))
4947 || !(i.base_reg
4948 && i.base_reg->reg_num < 6
4949 && i.index_reg->reg_num >= 6
4950 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4951 ok = 0;
4952 }
4953 else
e5cb08ac 4954 {
3e73aa7c
JH		 4955 /* 32bit checks. */
4956 if ((i.base_reg
4957 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4958 || (i.index_reg
29b0f896
AM		 4959 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4960 != (Reg32 | BaseIndex))))
e5cb08ac 4961 ok = 0;
3e73aa7c
JH		 4962 }
4963 }
4964 if (!ok)
24eab124
AM		 4965 {
4966#if INFER_ADDR_PREFIX
20f0a1fc 4967 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4968 {
4969 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4970 i.prefixes += 1;
b23bac36
AM		 4971 /* Change the size of any displacement too. At most one of
4972 Disp16 or Disp32 is set.
4973 FIXME. There doesn't seem to be any real need for separate
4974 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4975 Removing them would probably clean up the code quite a lot. */
4eed87de
AM		 4976 if (flag_code != CODE_64BIT
4977 && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 4978 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4979 fudged = 1;
24eab124
AM		 4980 goto tryprefix;
4981 }
eecb386c
AM		 4982 if (fudged)
4983 as_bad (_("`%s' is not a valid base/index expression"),
4984 operand_string);
4985 else
c388dee8 4986#endif
eecb386c
AM		 4987 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4988 operand_string,
3e73aa7c 4989 flag_code_names[flag_code]);
24eab124 4990 }
20f0a1fc 4991 return ok;
24eab124 4992}
252b5132 4993
252b5132 4994/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4995 on error. */
252b5132 4996
252b5132 4997static int
e3bb37b5 4998i386_operand (char *operand_string)
252b5132 4999{
af6bdddf
AM		 5000 const reg_entry *r;
5001 char *end_op;
24eab124 5002 char *op_string = operand_string;
252b5132 5003
24eab124 5004 if (is_space_char (*op_string))
252b5132
RH		 5005 ++op_string;
5006
24eab124 5007 /* We check for an absolute prefix (differentiating,
47926f60 5008 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 5009 if (*op_string == ABSOLUTE_PREFIX)
5010 {
5011 ++op_string;
5012 if (is_space_char (*op_string))
5013 ++op_string;
5014 i.types[this_operand] |= JumpAbsolute;
5015 }
252b5132 5016
47926f60 5017 /* Check if operand is a register. */
4d1bb795 5018 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 5019 {
24eab124
AM		 5020 /* Check for a segment override by searching for ':' after a
5021 segment register. */
5022 op_string = end_op;
5023 if (is_space_char (*op_string))
5024 ++op_string;
5025 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
5026 {
5027 switch (r->reg_num)
5028 {
5029 case 0:
5030 i.seg[i.mem_operands] = &es;
5031 break;
5032 case 1:
5033 i.seg[i.mem_operands] = &cs;
5034 break;
5035 case 2:
5036 i.seg[i.mem_operands] = &ss;
5037 break;
5038 case 3:
5039 i.seg[i.mem_operands] = &ds;
5040 break;
5041 case 4:
5042 i.seg[i.mem_operands] = &fs;
5043 break;
5044 case 5:
5045 i.seg[i.mem_operands] = &gs;
5046 break;
5047 }
252b5132 5048
24eab124 5049 /* Skip the ':' and whitespace. */
252b5132
RH		 5050 ++op_string;
5051 if (is_space_char (*op_string))
24eab124 5052 ++op_string;
252b5132 5053
24eab124
AM		 5054 if (!is_digit_char (*op_string)
5055 && !is_identifier_char (*op_string)
5056 && *op_string != '('
5057 && *op_string != ABSOLUTE_PREFIX)
5058 {
5059 as_bad (_("bad memory operand `%s'"), op_string);
5060 return 0;
5061 }
47926f60 5062 /* Handle case of %es:*foo. */
24eab124
AM		 5063 if (*op_string == ABSOLUTE_PREFIX)
5064 {
5065 ++op_string;
5066 if (is_space_char (*op_string))
5067 ++op_string;
5068 i.types[this_operand] |= JumpAbsolute;
5069 }
5070 goto do_memory_reference;
5071 }
5072 if (*op_string)
5073 {
d0b47220 5074 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 5075 return 0;
5076 }
5077 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 5078 i.op[this_operand].regs = r;
24eab124
AM		 5079 i.reg_operands++;
5080 }
af6bdddf
AM		 5081 else if (*op_string == REGISTER_PREFIX)
5082 {
5083 as_bad (_("bad register name `%s'"), op_string);
5084 return 0;
5085 }
24eab124 5086 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 5087 {
24eab124
AM		 5088 ++op_string;
5089 if (i.types[this_operand] & JumpAbsolute)
5090 {
d0b47220 5091 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 5092 return 0;
5093 }
5094 if (!i386_immediate (op_string))
5095 return 0;
5096 }
5097 else if (is_digit_char (*op_string)
5098 || is_identifier_char (*op_string)
e5cb08ac 5099 || *op_string == '(')
24eab124 5100 {
47926f60 5101 /* This is a memory reference of some sort. */
af6bdddf 5102 char *base_string;
252b5132 5103
47926f60 5104 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 5105 char *displacement_string_start;
5106 char *displacement_string_end;
252b5132 5107
24eab124 5108 do_memory_reference:
24eab124
AM		 5109 if ((i.mem_operands == 1
5110 && (current_templates->start->opcode_modifier & IsString) == 0)
5111 || i.mem_operands == 2)
5112 {
5113 as_bad (_("too many memory references for `%s'"),
5114 current_templates->start->name);
5115 return 0;
5116 }
252b5132 5117
24eab124
AM		 5118 /* Check for base index form. We detect the base index form by
5119 looking for an ')' at the end of the operand, searching
5120 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5121 after the '('. */
af6bdddf 5122 base_string = op_string + strlen (op_string);
c3332e24 5123
af6bdddf
AM		 5124 --base_string;
5125 if (is_space_char (*base_string))
5126 --base_string;
252b5132 5127
47926f60 5128 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 5129 displacement_string_start = op_string;
5130 displacement_string_end = base_string + 1;
252b5132 5131
24eab124
AM		 5132 if (*base_string == ')')
5133 {
af6bdddf 5134 char *temp_string;
24eab124
AM		 5135 unsigned int parens_balanced = 1;
5136 /* We've already checked that the number of left & right ()'s are
47926f60 5137 equal, so this loop will not be infinite. */
24eab124
AM		 5138 do
5139 {
5140 base_string--;
5141 if (*base_string == ')')
5142 parens_balanced++;
5143 if (*base_string == '(')
5144 parens_balanced--;
5145 }
5146 while (parens_balanced);
c3332e24 5147
af6bdddf 5148 temp_string = base_string;
c3332e24 5149
24eab124 5150 /* Skip past '(' and whitespace. */
252b5132
RH		 5151 ++base_string;
5152 if (is_space_char (*base_string))
24eab124 5153 ++base_string;
252b5132 5154
af6bdddf 5155 if (*base_string == ','
4eed87de
AM		 5156 || ((i.base_reg = parse_register (base_string, &end_op))
5157 != NULL))
252b5132 5158 {
af6bdddf 5159 displacement_string_end = temp_string;
252b5132 5160
af6bdddf 5161 i.types[this_operand] |= BaseIndex;
252b5132 5162
af6bdddf 5163 if (i.base_reg)
24eab124 5164 {
24eab124
AM		 5165 base_string = end_op;
5166 if (is_space_char (*base_string))
5167 ++base_string;
af6bdddf
AM		 5168 }
5169
5170 /* There may be an index reg or scale factor here. */
5171 if (*base_string == ',')
5172 {
5173 ++base_string;
5174 if (is_space_char (*base_string))
5175 ++base_string;
5176
4eed87de
AM		 5177 if ((i.index_reg = parse_register (base_string, &end_op))
5178 != NULL)
24eab124 5179 {
af6bdddf 5180 base_string = end_op;
24eab124
AM		 5181 if (is_space_char (*base_string))
5182 ++base_string;
af6bdddf
AM		 5183 if (*base_string == ',')
5184 {
5185 ++base_string;
5186 if (is_space_char (*base_string))
5187 ++base_string;
5188 }
e5cb08ac 5189 else if (*base_string != ')')
af6bdddf 5190 {
4eed87de
AM		 5191 as_bad (_("expecting `,' or `)' "
5192 "after index register in `%s'"),
af6bdddf
AM		 5193 operand_string);
5194 return 0;
5195 }
24eab124 5196 }
af6bdddf 5197 else if (*base_string == REGISTER_PREFIX)
24eab124 5198 {
af6bdddf 5199 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5200 return 0;
5201 }
252b5132 5202
47926f60 5203 /* Check for scale factor. */
551c1ca1 5204 if (*base_string != ')')
af6bdddf 5205 {
551c1ca1
AM		 5206 char *end_scale = i386_scale (base_string);
5207
5208 if (!end_scale)
af6bdddf 5209 return 0;
24eab124 5210
551c1ca1 5211 base_string = end_scale;
af6bdddf
AM		 5212 if (is_space_char (*base_string))
5213 ++base_string;
5214 if (*base_string != ')')
5215 {
4eed87de
AM		 5216 as_bad (_("expecting `)' "
5217 "after scale factor in `%s'"),
af6bdddf
AM		 5218 operand_string);
5219 return 0;
5220 }
5221 }
5222 else if (!i.index_reg)
24eab124 5223 {
4eed87de
AM		 5224 as_bad (_("expecting index register or scale factor "
5225 "after `,'; got '%c'"),
af6bdddf 5226 *base_string);
24eab124
AM		 5227 return 0;
5228 }
5229 }
af6bdddf 5230 else if (*base_string != ')')
24eab124 5231 {
4eed87de
AM		 5232 as_bad (_("expecting `,' or `)' "
5233 "after base register in `%s'"),
af6bdddf 5234 operand_string);
24eab124
AM		 5235 return 0;
5236 }
c3332e24 5237 }
af6bdddf 5238 else if (*base_string == REGISTER_PREFIX)
c3332e24 5239 {
af6bdddf 5240 as_bad (_("bad register name `%s'"), base_string);
24eab124 5241 return 0;
c3332e24 5242 }
24eab124
AM		 5243 }
5244
5245 /* If there's an expression beginning the operand, parse it,
5246 assuming displacement_string_start and
5247 displacement_string_end are meaningful. */
5248 if (displacement_string_start != displacement_string_end)
5249 {
5250 if (!i386_displacement (displacement_string_start,
5251 displacement_string_end))
5252 return 0;
5253 }
5254
5255 /* Special case for (%dx) while doing input/output op. */
5256 if (i.base_reg
5257 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5258 && i.index_reg == 0
5259 && i.log2_scale_factor == 0
5260 && i.seg[i.mem_operands] == 0
5261 && (i.types[this_operand] & Disp) == 0)
5262 {
5263 i.types[this_operand] = InOutPortReg;
5264 return 1;
5265 }
5266
eecb386c
AM		 5267 if (i386_index_check (operand_string) == 0)
5268 return 0;
24eab124
AM		 5269 i.mem_operands++;
5270 }
5271 else
ce8a8b2f
AM		 5272 {
5273 /* It's not a memory operand; argh! */
24eab124
AM		 5274 as_bad (_("invalid char %s beginning operand %d `%s'"),
5275 output_invalid (*op_string),
5276 this_operand + 1,
5277 op_string);
5278 return 0;
5279 }
47926f60 5280 return 1; /* Normal return. */
252b5132
RH		 5281}
5282\f
ee7fcc42
AM		 5283/* md_estimate_size_before_relax()
5284
5285 Called just before relax() for rs_machine_dependent frags. The x86
5286 assembler uses these frags to handle variable size jump
5287 instructions.
5288
5289 Any symbol that is now undefined will not become defined.
5290 Return the correct fr_subtype in the frag.
5291 Return the initial "guess for variable size of frag" to caller.
5292 The guess is actually the growth beyond the fixed part. Whatever
5293 we do to grow the fixed or variable part contributes to our
5294 returned value. */
5295
252b5132
RH		 5296int
5297md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5298 fragS *fragP;
5299 segT segment;
252b5132 5300{
252b5132 5301 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5302 check for un-relaxable symbols. On an ELF system, we can't relax
5303 an externally visible symbol, because it may be overridden by a
5304 shared library. */
5305 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5306#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5307 || (IS_ELF
31312f95
AM		 5308 && (S_IS_EXTERNAL (fragP->fr_symbol)
5309 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5310#endif
5311 )
252b5132 5312 {
b98ef147
AM		 5313 /* Symbol is undefined in this segment, or we need to keep a
5314 reloc so that weak symbols can be overridden. */
5315 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5316 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5317 unsigned char *opcode;
5318 int old_fr_fix;
f6af82bd 5319
ee7fcc42
AM		 5320 if (fragP->fr_var != NO_RELOC)
5321 reloc_type = fragP->fr_var;
b98ef147 5322 else if (size == 2)
f6af82bd
AM		 5323 reloc_type = BFD_RELOC_16_PCREL;
5324 else
5325 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5326
ee7fcc42
AM		 5327 old_fr_fix = fragP->fr_fix;
5328 opcode = (unsigned char *) fragP->fr_opcode;
5329
fddf5b5b 5330 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5331 {
fddf5b5b
AM		 5332 case UNCOND_JUMP:
5333 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5334 opcode[0] = 0xe9;
252b5132 5335 fragP->fr_fix += size;
062cd5e7
AS		 5336 fix_new (fragP, old_fr_fix, size,
5337 fragP->fr_symbol,
5338 fragP->fr_offset, 1,
5339 reloc_type);
252b5132
RH		 5340 break;
5341
fddf5b5b 5342 case COND_JUMP86:
412167cb
AM		 5343 if (size == 2
5344 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5345 {
5346 /* Negate the condition, and branch past an
5347 unconditional jump. */
5348 opcode[0] ^= 1;
5349 opcode[1] = 3;
5350 /* Insert an unconditional jump. */
5351 opcode[2] = 0xe9;
5352 /* We added two extra opcode bytes, and have a two byte
5353 offset. */
5354 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5355 fix_new (fragP, old_fr_fix + 2, 2,
5356 fragP->fr_symbol,
5357 fragP->fr_offset, 1,
5358 reloc_type);
fddf5b5b
AM		 5359 break;
5360 }
5361 /* Fall through. */
5362
5363 case COND_JUMP:
412167cb
AM		 5364 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5365 {
3e02c1cc
AM		 5366 fixS *fixP;
5367
412167cb 5368 fragP->fr_fix += 1;
3e02c1cc
AM		 5369 fixP = fix_new (fragP, old_fr_fix, 1,
5370 fragP->fr_symbol,
5371 fragP->fr_offset, 1,
5372 BFD_RELOC_8_PCREL);
5373 fixP->fx_signed = 1;
412167cb
AM		 5374 break;
5375 }
93c2a809 5376
24eab124 5377 /* This changes the byte-displacement jump 0x7N
fddf5b5b 5378 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 5379 opcode[1] = opcode[0] + 0x10;
f6af82bd 5380 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 5381 /* We've added an opcode byte. */
5382 fragP->fr_fix += 1 + size;
062cd5e7
AS		 5383 fix_new (fragP, old_fr_fix + 1, size,
5384 fragP->fr_symbol,
5385 fragP->fr_offset, 1,
5386 reloc_type);
252b5132 5387 break;
fddf5b5b
AM		 5388
5389 default:
5390 BAD_CASE (fragP->fr_subtype);
5391 break;
252b5132
RH		 5392 }
5393 frag_wane (fragP);
ee7fcc42 5394 return fragP->fr_fix - old_fr_fix;
252b5132 5395 }
93c2a809 5396
93c2a809
AM		 5397 /* Guess size depending on current relax state. Initially the relax
5398 state will correspond to a short jump and we return 1, because
5399 the variable part of the frag (the branch offset) is one byte
5400 long. However, we can relax a section more than once and in that
5401 case we must either set fr_subtype back to the unrelaxed state,
5402 or return the value for the appropriate branch. */
5403 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 5404}
5405
47926f60
KH		 5406/* Called after relax() is finished.
5407
5408 In: Address of frag.
5409 fr_type == rs_machine_dependent.
5410 fr_subtype is what the address relaxed to.
5411
5412 Out: Any fixSs and constants are set up.
5413 Caller will turn frag into a ".space 0". */
5414
252b5132
RH		 5415void
5416md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 5417 bfd *abfd ATTRIBUTE_UNUSED;
5418 segT sec ATTRIBUTE_UNUSED;
29b0f896 5419 fragS *fragP;
252b5132 5420{
29b0f896 5421 unsigned char *opcode;
252b5132 5422 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 5423 offsetT target_address;
5424 offsetT opcode_address;
252b5132 5425 unsigned int extension = 0;
847f7ad4 5426 offsetT displacement_from_opcode_start;
252b5132
RH		 5427
5428 opcode = (unsigned char *) fragP->fr_opcode;
5429
47926f60 5430 /* Address we want to reach in file space. */
252b5132 5431 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 5432
47926f60 5433 /* Address opcode resides at in file space. */
252b5132
RH		 5434 opcode_address = fragP->fr_address + fragP->fr_fix;
5435
47926f60 5436 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 5437 displacement_from_opcode_start = target_address - opcode_address;
5438
fddf5b5b 5439 if ((fragP->fr_subtype & BIG) == 0)
252b5132 5440 {
47926f60
KH		 5441 /* Don't have to change opcode. */
5442 extension = 1; /* 1 opcode + 1 displacement */
252b5132 5443 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 5444 }
5445 else
5446 {
5447 if (no_cond_jump_promotion
5448 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 5449 as_warn_where (fragP->fr_file, fragP->fr_line,
5450 _("long jump required"));
252b5132 5451
fddf5b5b
AM		 5452 switch (fragP->fr_subtype)
5453 {
5454 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5455 extension = 4; /* 1 opcode + 4 displacement */
5456 opcode[0] = 0xe9;
5457 where_to_put_displacement = &opcode[1];
5458 break;
252b5132 5459
fddf5b5b
AM		 5460 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5461 extension = 2; /* 1 opcode + 2 displacement */
5462 opcode[0] = 0xe9;
5463 where_to_put_displacement = &opcode[1];
5464 break;
252b5132 5465
fddf5b5b
AM		 5466 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5467 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5468 extension = 5; /* 2 opcode + 4 displacement */
5469 opcode[1] = opcode[0] + 0x10;
5470 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5471 where_to_put_displacement = &opcode[2];
5472 break;
252b5132 5473
fddf5b5b
AM		 5474 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5475 extension = 3; /* 2 opcode + 2 displacement */
5476 opcode[1] = opcode[0] + 0x10;
5477 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5478 where_to_put_displacement = &opcode[2];
5479 break;
252b5132 5480
fddf5b5b
AM		 5481 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5482 extension = 4;
5483 opcode[0] ^= 1;
5484 opcode[1] = 3;
5485 opcode[2] = 0xe9;
5486 where_to_put_displacement = &opcode[3];
5487 break;
5488
5489 default:
5490 BAD_CASE (fragP->fr_subtype);
5491 break;
5492 }
252b5132 5493 }
fddf5b5b 5494
7b81dfbb
AJ		 5495 /* If size if less then four we are sure that the operand fits,
5496 but if it's 4, then it could be that the displacement is larger
5497 then -/+ 2GB. */
5498 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5499 && object_64bit
5500 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 5501 + ((addressT) 1 << 31))
5502 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 5503 {
5504 as_bad_where (fragP->fr_file, fragP->fr_line,
5505 _("jump target out of range"));
5506 /* Make us emit 0. */
5507 displacement_from_opcode_start = extension;
5508 }
47926f60 5509 /* Now put displacement after opcode. */
252b5132
RH		 5510 md_number_to_chars ((char *) where_to_put_displacement,
5511 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5512 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5513 fragP->fr_fix += extension;
5514}
5515\f
47926f60
KH		 5516/* Size of byte displacement jmp. */
5517int md_short_jump_size = 2;
5518
5519/* Size of dword displacement jmp. */
5520int md_long_jump_size = 5;
252b5132 5521
252b5132
RH		 5522void
5523md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5524 char *ptr;
5525 addressT from_addr, to_addr;
ab9da554
ILT		 5526 fragS *frag ATTRIBUTE_UNUSED;
5527 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5528{
847f7ad4 5529 offsetT offset;
252b5132
RH		 5530
5531 offset = to_addr - (from_addr + 2);
47926f60
KH		 5532 /* Opcode for byte-disp jump. */
5533 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5534 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5535}
5536
5537void
5538md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5539 char *ptr;
5540 addressT from_addr, to_addr;
a38cf1db
AM		 5541 fragS *frag ATTRIBUTE_UNUSED;
5542 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5543{
847f7ad4 5544 offsetT offset;
252b5132 5545
a38cf1db
AM		 5546 offset = to_addr - (from_addr + 5);
5547 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5548 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5549}
5550\f
5551/* Apply a fixup (fixS) to segment data, once it has been determined
5552 by our caller that we have all the info we need to fix it up.
5553
5554 On the 386, immediates, displacements, and data pointers are all in
5555 the same (little-endian) format, so we don't need to care about which
5556 we are handling. */
5557
94f592af 5558void
55cf6793 5559md_apply_fix (fixP, valP, seg)
47926f60
KH		 5560 /* The fix we're to put in. */
5561 fixS *fixP;
47926f60 5562 /* Pointer to the value of the bits. */
c6682705 5563 valueT *valP;
47926f60
KH		 5564 /* Segment fix is from. */
5565 segT seg ATTRIBUTE_UNUSED;
252b5132 5566{
94f592af 5567 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5568 valueT value = *valP;
252b5132 5569
f86103b7 5570#if !defined (TE_Mach)
93382f6d
AM		 5571 if (fixP->fx_pcrel)
5572 {
5573 switch (fixP->fx_r_type)
5574 {
5865bb77
ILT		 5575 default:
5576 break;
5577
d6ab8113
JB		 5578 case BFD_RELOC_64:
5579 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5580 break;
93382f6d 5581 case BFD_RELOC_32:
ae8887b5 5582 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5583 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5584 break;
5585 case BFD_RELOC_16:
5586 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5587 break;
5588 case BFD_RELOC_8:
5589 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5590 break;
5591 }
5592 }
252b5132 5593
a161fe53 5594 if (fixP->fx_addsy != NULL
31312f95 5595 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5596 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5597 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5598 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5599 && !use_rela_relocations)
252b5132 5600 {
31312f95
AM		 5601 /* This is a hack. There should be a better way to handle this.
5602 This covers for the fact that bfd_install_relocation will
5603 subtract the current location (for partial_inplace, PC relative
5604 relocations); see more below. */
252b5132 5605#ifndef OBJ_AOUT
718ddfc0 5606 if (IS_ELF
252b5132
RH		 5607#ifdef TE_PE
5608 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5609#endif
5610 )
5611 value += fixP->fx_where + fixP->fx_frag->fr_address;
5612#endif
5613#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5614 if (IS_ELF)
252b5132 5615 {
6539b54b 5616 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5617
6539b54b 5618 if ((sym_seg == seg
2f66722d 5619 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5620 && sym_seg != absolute_section))
ae6063d4 5621 && !generic_force_reloc (fixP))
2f66722d
AM		 5622 {
5623 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5624 bfd_install_relocation subtracts them out again. I think
5625 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5626 it. FIXME. */
5627 value += fixP->fx_where + fixP->fx_frag->fr_address;
5628 }
252b5132
RH		 5629 }
5630#endif
5631#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5632 /* For some reason, the PE format does not store a
5633 section address offset for a PC relative symbol. */
5634 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5635 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5636 value += md_pcrel_from (fixP);
5637#endif
5638 }
5639
5640 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5641 and we must not disappoint it. */
252b5132 5642#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5643 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5644 switch (fixP->fx_r_type)
5645 {
5646 case BFD_RELOC_386_PLT32:
3e73aa7c 5647 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5648 /* Make the jump instruction point to the address of the operand. At
5649 runtime we merely add the offset to the actual PLT entry. */
5650 value = -4;
5651 break;
31312f95 5652
13ae64f3
JJ		 5653 case BFD_RELOC_386_TLS_GD:
5654 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5655 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5656 case BFD_RELOC_386_TLS_IE:
5657 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5658 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5659 case BFD_RELOC_X86_64_TLSGD:
5660 case BFD_RELOC_X86_64_TLSLD:
5661 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5662 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5663 value = 0; /* Fully resolved at runtime. No addend. */
5664 /* Fallthrough */
5665 case BFD_RELOC_386_TLS_LE:
5666 case BFD_RELOC_386_TLS_LDO_32:
5667 case BFD_RELOC_386_TLS_LE_32:
5668 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5669 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5670 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5671 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5672 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5673 break;
5674
67a4f2b7
AO		 5675 case BFD_RELOC_386_TLS_DESC_CALL:
5676 case BFD_RELOC_X86_64_TLSDESC_CALL:
5677 value = 0; /* Fully resolved at runtime. No addend. */
5678 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5679 fixP->fx_done = 0;
5680 return;
5681
00f7efb6
JJ		 5682 case BFD_RELOC_386_GOT32:
5683 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5684 value = 0; /* Fully resolved at runtime. No addend. */
5685 break;
47926f60
KH		 5686
5687 case BFD_RELOC_VTABLE_INHERIT:
5688 case BFD_RELOC_VTABLE_ENTRY:
5689 fixP->fx_done = 0;
94f592af 5690 return;
47926f60
KH		 5691
5692 default:
5693 break;
5694 }
5695#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5696 *valP = value;
f86103b7 5697#endif /* !defined (TE_Mach) */
3e73aa7c 5698
3e73aa7c 5699 /* Are we finished with this relocation now? */
c6682705 5700 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5701 fixP->fx_done = 1;
5702 else if (use_rela_relocations)
5703 {
5704 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5705 /* Remember value for tc_gen_reloc. */
5706 fixP->fx_addnumber = value;
3e73aa7c
JH		 5707 value = 0;
5708 }
f86103b7 5709
94f592af 5710 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5711}
252b5132 5712\f
252b5132
RH		 5713#define MAX_LITTLENUMS 6
5714
47926f60
KH		 5715/* Turn the string pointed to by litP into a floating point constant
5716 of type TYPE, and emit the appropriate bytes. The number of
5717 LITTLENUMS emitted is stored in *SIZEP. An error message is
5718 returned, or NULL on OK. */
5719
252b5132
RH		 5720char *
5721md_atof (type, litP, sizeP)
2ab9b79e 5722 int type;
252b5132
RH		 5723 char *litP;
5724 int *sizeP;
5725{
5726 int prec;
5727 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5728 LITTLENUM_TYPE *wordP;
5729 char *t;
5730
5731 switch (type)
5732 {
5733 case 'f':
5734 case 'F':
5735 prec = 2;
5736 break;
5737
5738 case 'd':
5739 case 'D':
5740 prec = 4;
5741 break;
5742
5743 case 'x':
5744 case 'X':
5745 prec = 5;
5746 break;
5747
5748 default:
5749 *sizeP = 0;
5750 return _("Bad call to md_atof ()");
5751 }
5752 t = atof_ieee (input_line_pointer, type, words);
5753 if (t)
5754 input_line_pointer = t;
5755
5756 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5757 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5758 the bigendian 386. */
5759 for (wordP = words + prec - 1; prec--;)
5760 {
5761 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5762 litP += sizeof (LITTLENUM_TYPE);
5763 }
5764 return 0;
5765}
5766\f
2d545b82 5767static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5768
252b5132 5769static char *
e3bb37b5 5770output_invalid (int c)
252b5132 5771{
3882b010 5772 if (ISPRINT (c))
f9f21a03
L		 5773 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5774 "'%c'", c);
252b5132 5775 else
f9f21a03 5776 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5777 "(0x%x)", (unsigned char) c);
252b5132
RH		 5778 return output_invalid_buf;
5779}
5780
af6bdddf 5781/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5782
5783static const reg_entry *
4d1bb795 5784parse_real_register (char *reg_string, char **end_op)
252b5132 5785{
af6bdddf
AM		 5786 char *s = reg_string;
5787 char *p;
252b5132
RH		 5788 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5789 const reg_entry *r;
5790
5791 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5792 if (*s == REGISTER_PREFIX)
5793 ++s;
5794
5795 if (is_space_char (*s))
5796 ++s;
5797
5798 p = reg_name_given;
af6bdddf 5799 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5800 {
5801 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5802 return (const reg_entry *) NULL;
5803 s++;
252b5132
RH		 5804 }
5805
6588847e
DN		 5806 /* For naked regs, make sure that we are not dealing with an identifier.
5807 This prevents confusing an identifier like `eax_var' with register
5808 `eax'. */
5809 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5810 return (const reg_entry *) NULL;
5811
af6bdddf 5812 *end_op = s;
252b5132
RH		 5813
5814 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5815
5f47d35b 5816 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5817 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5818 {
5f47d35b
AM		 5819 if (is_space_char (*s))
5820 ++s;
5821 if (*s == '(')
5822 {
af6bdddf 5823 ++s;
5f47d35b
AM		 5824 if (is_space_char (*s))
5825 ++s;
5826 if (*s >= '0' && *s <= '7')
5827 {
db557034 5828 int fpr = *s - '0';
af6bdddf 5829 ++s;
5f47d35b
AM		 5830 if (is_space_char (*s))
5831 ++s;
5832 if (*s == ')')
5833 {
5834 *end_op = s + 1;
db557034
AM		 5835 r = hash_find (reg_hash, "st(0)");
5836 know (r);
5837 return r + fpr;
5f47d35b 5838 }
5f47d35b 5839 }
47926f60 5840 /* We have "%st(" then garbage. */
5f47d35b
AM		 5841 return (const reg_entry *) NULL;
5842 }
5843 }
5844
1ae00879 5845 if (r != NULL
20f0a1fc 5846 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5847 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5848 && flag_code != CODE_64BIT)
20f0a1fc 5849 return (const reg_entry *) NULL;
1ae00879 5850
252b5132
RH		 5851 return r;
5852}
4d1bb795
JB		 5853
5854/* REG_STRING starts *before* REGISTER_PREFIX. */
5855
5856static const reg_entry *
5857parse_register (char *reg_string, char **end_op)
5858{
5859 const reg_entry *r;
5860
5861 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5862 r = parse_real_register (reg_string, end_op);
5863 else
5864 r = NULL;
5865 if (!r)
5866 {
5867 char *save = input_line_pointer;
5868 char c;
5869 symbolS *symbolP;
5870
5871 input_line_pointer = reg_string;
5872 c = get_symbol_end ();
5873 symbolP = symbol_find (reg_string);
5874 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5875 {
5876 const expressionS *e = symbol_get_value_expression (symbolP);
5877
5878 know (e->X_op == O_register);
4eed87de 5879 know (e->X_add_number >= 0
c3fe08fa 5880 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 5881 r = i386_regtab + e->X_add_number;
5882 *end_op = input_line_pointer;
5883 }
5884 *input_line_pointer = c;
5885 input_line_pointer = save;
5886 }
5887 return r;
5888}
5889
5890int
5891i386_parse_name (char *name, expressionS *e, char *nextcharP)
5892{
5893 const reg_entry *r;
5894 char *end = input_line_pointer;
5895
5896 *end = *nextcharP;
5897 r = parse_register (name, &input_line_pointer);
5898 if (r && end <= input_line_pointer)
5899 {
5900 *nextcharP = *input_line_pointer;
5901 *input_line_pointer = 0;
5902 e->X_op = O_register;
5903 e->X_add_number = r - i386_regtab;
5904 return 1;
5905 }
5906 input_line_pointer = end;
5907 *end = 0;
5908 return 0;
5909}
5910
5911void
5912md_operand (expressionS *e)
5913{
5914 if (*input_line_pointer == REGISTER_PREFIX)
5915 {
5916 char *end;
5917 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5918
5919 if (r)
5920 {
5921 e->X_op = O_register;
5922 e->X_add_number = r - i386_regtab;
5923 input_line_pointer = end;
5924 }
5925 }
5926}
5927
252b5132 5928\f
4cc782b5 5929#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5930const char *md_shortopts = "kVQ:sqn";
252b5132 5931#else
12b55ccc 5932const char *md_shortopts = "qn";
252b5132 5933#endif
6e0b89ee 5934
3e73aa7c 5935#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5936#define OPTION_64 (OPTION_MD_BASE + 1)
5937#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 5938#define OPTION_MARCH (OPTION_MD_BASE + 3)
5939#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 5940
99ad8390
NC		 5941struct option md_longopts[] =
5942{
3e73aa7c 5943 {"32", no_argument, NULL, OPTION_32},
99ad8390 5944#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 5945 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5946#endif
b3b91714 5947 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 5948 {"march", required_argument, NULL, OPTION_MARCH},
5949 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 5950 {NULL, no_argument, NULL, 0}
5951};
5952size_t md_longopts_size = sizeof (md_longopts);
5953
5954int
9103f4f4 5955md_parse_option (int c, char *arg)
252b5132 5956{
9103f4f4
L		 5957 unsigned int i;
5958
252b5132
RH		 5959 switch (c)
5960 {
12b55ccc
L		 5961 case 'n':
5962 optimize_align_code = 0;
5963 break;
5964
a38cf1db
AM		 5965 case 'q':
5966 quiet_warnings = 1;
252b5132
RH		 5967 break;
5968
5969#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5970 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5971 should be emitted or not. FIXME: Not implemented. */
5972 case 'Q':
252b5132
RH		 5973 break;
5974
5975 /* -V: SVR4 argument to print version ID. */
5976 case 'V':
5977 print_version_id ();
5978 break;
5979
a38cf1db
AM		 5980 /* -k: Ignore for FreeBSD compatibility. */
5981 case 'k':
252b5132 5982 break;
4cc782b5
ILT		 5983
5984 case 's':
5985 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5986 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5987 break;
99ad8390
NC		 5988#endif
5989#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 5990 case OPTION_64:
5991 {
5992 const char **list, **l;
5993
3e73aa7c
JH		 5994 list = bfd_target_list ();
5995 for (l = list; *l != NULL; l++)
8620418b 5996 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 5997 || strcmp (*l, "coff-x86-64") == 0
5998 || strcmp (*l, "pe-x86-64") == 0
5999 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 6000 {
6001 default_arch = "x86_64";
6002 break;
6003 }
3e73aa7c 6004 if (*l == NULL)
6e0b89ee 6005 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 6006 free (list);
6007 }
6008 break;
6009#endif
252b5132 6010
6e0b89ee
AM		 6011 case OPTION_32:
6012 default_arch = "i386";
6013 break;
6014
b3b91714
AM		 6015 case OPTION_DIVIDE:
6016#ifdef SVR4_COMMENT_CHARS
6017 {
6018 char *n, *t;
6019 const char *s;
6020
6021 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
6022 t = n;
6023 for (s = i386_comment_chars; *s != '\0'; s++)
6024 if (*s != '/')
6025 *t++ = *s;
6026 *t = '\0';
6027 i386_comment_chars = n;
6028 }
6029#endif
6030 break;
6031
9103f4f4
L		 6032 case OPTION_MARCH:
6033 if (*arg == '.')
6034 as_fatal (_("Invalid -march= option: `%s'"), arg);
6035 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
6036 {
6037 if (strcmp (arg, cpu_arch [i].name) == 0)
6038 {
ccc9c027 6039 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 6040 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 6041 if (!cpu_arch_tune_set)
6042 {
6043 cpu_arch_tune = cpu_arch_isa;
6044 cpu_arch_tune_flags = cpu_arch_isa_flags;
6045 }
9103f4f4
L		 6046 break;
6047 }
6048 }
6049 if (i >= ARRAY_SIZE (cpu_arch))
6050 as_fatal (_("Invalid -march= option: `%s'"), arg);
6051 break;
6052
6053 case OPTION_MTUNE:
6054 if (*arg == '.')
6055 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6056 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
6057 {
6058 if (strcmp (arg, cpu_arch [i].name) == 0)
6059 {
ccc9c027 6060 cpu_arch_tune_set = 1;
9103f4f4
L		 6061 cpu_arch_tune = cpu_arch [i].type;
6062 cpu_arch_tune_flags = cpu_arch[i].flags;
6063 break;
6064 }
6065 }
6066 if (i >= ARRAY_SIZE (cpu_arch))
6067 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6068 break;
6069
252b5132
RH		 6070 default:
6071 return 0;
6072 }
6073 return 1;
6074}
6075
6076void
6077md_show_usage (stream)
6078 FILE *stream;
6079{
4cc782b5
ILT		 6080#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6081 fprintf (stream, _("\
a38cf1db
AM		 6082 -Q ignored\n\
6083 -V print assembler version number\n\
b3b91714
AM		 6084 -k ignored\n"));
6085#endif
6086 fprintf (stream, _("\
12b55ccc 6087 -n Do not optimize code alignment\n\
b3b91714
AM		 6088 -q quieten some warnings\n"));
6089#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6090 fprintf (stream, _("\
a38cf1db 6091 -s ignored\n"));
b3b91714 6092#endif
751d281c
L		 6093#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6094 fprintf (stream, _("\
6095 --32/--64 generate 32bit/64bit code\n"));
6096#endif
b3b91714
AM		 6097#ifdef SVR4_COMMENT_CHARS
6098 fprintf (stream, _("\
6099 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 6100#else
6101 fprintf (stream, _("\
b3b91714 6102 --divide ignored\n"));
4cc782b5 6103#endif
9103f4f4
L		 6104 fprintf (stream, _("\
6105 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6106 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 6107 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 6108
252b5132
RH		 6109}
6110
99ad8390
NC		 6111#if defined(TE_PEP)
6112const char *
6113x86_64_target_format (void)
6114{
6115 if (strcmp (default_arch, "x86_64") == 0)
6116 {
6117 set_code_flag (CODE_64BIT);
6118 return COFF_TARGET_FORMAT;
6119 }
6120 else if (strcmp (default_arch, "i386") == 0)
6121 {
6122 set_code_flag (CODE_32BIT);
6123 return "coff-i386";
6124 }
6125
6126 as_fatal (_("Unknown architecture"));
6127 return NULL;
6128}
6129#endif
6130
3e73aa7c
JH		 6131#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6132 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 6133
6134/* Pick the target format to use. */
6135
47926f60 6136const char *
e3bb37b5 6137i386_target_format (void)
252b5132 6138{
3e73aa7c 6139 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 6140 {
6141 set_code_flag (CODE_64BIT);
6142 if (cpu_arch_isa_flags == 0)
d32cad65 6143 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
9103f4f4
L		 6144 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6145 |CpuSSE|CpuSSE2;
ccc9c027 6146 if (cpu_arch_tune_flags == 0)
d32cad65 6147 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
ccc9c027
L		 6148 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6149 |CpuSSE|CpuSSE2;
9103f4f4 6150 }
3e73aa7c 6151 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 6152 {
6153 set_code_flag (CODE_32BIT);
6154 if (cpu_arch_isa_flags == 0)
d32cad65 6155 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
ccc9c027 6156 if (cpu_arch_tune_flags == 0)
d32cad65 6157 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
9103f4f4 6158 }
3e73aa7c
JH		 6159 else
6160 as_fatal (_("Unknown architecture"));
252b5132
RH		 6161 switch (OUTPUT_FLAVOR)
6162 {
4c63da97
AM		 6163#ifdef OBJ_MAYBE_AOUT
6164 case bfd_target_aout_flavour:
47926f60 6165 return AOUT_TARGET_FORMAT;
4c63da97
AM		 6166#endif
6167#ifdef OBJ_MAYBE_COFF
252b5132
RH		 6168 case bfd_target_coff_flavour:
6169 return "coff-i386";
4c63da97 6170#endif
3e73aa7c 6171#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 6172 case bfd_target_elf_flavour:
3e73aa7c 6173 {
e5cb08ac 6174 if (flag_code == CODE_64BIT)
4fa24527
JB		 6175 {
6176 object_64bit = 1;
6177 use_rela_relocations = 1;
6178 }
9d7cbccd 6179 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6180 }
4c63da97 6181#endif
252b5132
RH		 6182 default:
6183 abort ();
6184 return NULL;
6185 }
6186}
6187
47926f60 6188#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 6189
6190#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 6191void
6192i386_elf_emit_arch_note (void)
a847613f 6193{
718ddfc0 6194 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 6195 {
6196 char *p;
6197 asection *seg = now_seg;
6198 subsegT subseg = now_subseg;
6199 Elf_Internal_Note i_note;
6200 Elf_External_Note e_note;
6201 asection *note_secp;
6202 int len;
6203
6204 /* Create the .note section. */
6205 note_secp = subseg_new (".note", 0);
6206 bfd_set_section_flags (stdoutput,
6207 note_secp,
6208 SEC_HAS_CONTENTS | SEC_READONLY);
6209
6210 /* Process the arch string. */
6211 len = strlen (cpu_arch_name);
6212
6213 i_note.namesz = len + 1;
6214 i_note.descsz = 0;
6215 i_note.type = NT_ARCH;
6216 p = frag_more (sizeof (e_note.namesz));
6217 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6218 p = frag_more (sizeof (e_note.descsz));
6219 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6220 p = frag_more (sizeof (e_note.type));
6221 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6222 p = frag_more (len + 1);
6223 strcpy (p, cpu_arch_name);
6224
6225 frag_align (2, 0, 0);
6226
6227 subseg_set (seg, subseg);
6228 }
6229}
6230#endif
252b5132 6231\f
252b5132
RH		 6232symbolS *
6233md_undefined_symbol (name)
6234 char *name;
6235{
18dc2407
ILT		 6236 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6237 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6238 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6239 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6240 {
6241 if (!GOT_symbol)
6242 {
6243 if (symbol_find (name))
6244 as_bad (_("GOT already in symbol table"));
6245 GOT_symbol = symbol_new (name, undefined_section,
6246 (valueT) 0, &zero_address_frag);
6247 };
6248 return GOT_symbol;
6249 }
252b5132
RH		 6250 return 0;
6251}
6252
6253/* Round up a section size to the appropriate boundary. */
47926f60 6254
252b5132
RH		 6255valueT
6256md_section_align (segment, size)
ab9da554 6257 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6258 valueT size;
6259{
4c63da97
AM		 6260#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6261 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6262 {
6263 /* For a.out, force the section size to be aligned. If we don't do
6264 this, BFD will align it for us, but it will not write out the
6265 final bytes of the section. This may be a bug in BFD, but it is
6266 easier to fix it here since that is how the other a.out targets
6267 work. */
6268 int align;
6269
6270 align = bfd_get_section_alignment (stdoutput, segment);
6271 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6272 }
252b5132
RH		 6273#endif
6274
6275 return size;
6276}
6277
6278/* On the i386, PC-relative offsets are relative to the start of the
6279 next instruction. That is, the address of the offset, plus its
6280 size, since the offset is always the last part of the insn. */
6281
6282long
e3bb37b5 6283md_pcrel_from (fixS *fixP)
252b5132
RH		 6284{
6285 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6286}
6287
6288#ifndef I386COFF
6289
6290static void
e3bb37b5 6291s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 6292{
29b0f896 6293 int temp;
252b5132 6294
8a75718c
JB		 6295#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6296 if (IS_ELF)
6297 obj_elf_section_change_hook ();
6298#endif
252b5132
RH		 6299 temp = get_absolute_expression ();
6300 subseg_set (bss_section, (subsegT) temp);
6301 demand_empty_rest_of_line ();
6302}
6303
6304#endif
6305
252b5132 6306void
e3bb37b5 6307i386_validate_fix (fixS *fixp)
252b5132
RH		 6308{
6309 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6310 {
23df1078
JH		 6311 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6312 {
4fa24527 6313 if (!object_64bit)
23df1078
JH		 6314 abort ();
6315 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6316 }
6317 else
6318 {
4fa24527 6319 if (!object_64bit)
d6ab8113
JB		 6320 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6321 else
6322 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6323 }
252b5132
RH		 6324 fixp->fx_subsy = 0;
6325 }
6326}
6327
252b5132
RH		 6328arelent *
6329tc_gen_reloc (section, fixp)
ab9da554 6330 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6331 fixS *fixp;
6332{
6333 arelent *rel;
6334 bfd_reloc_code_real_type code;
6335
6336 switch (fixp->fx_r_type)
6337 {
3e73aa7c
JH		 6338 case BFD_RELOC_X86_64_PLT32:
6339 case BFD_RELOC_X86_64_GOT32:
6340 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6341 case BFD_RELOC_386_PLT32:
6342 case BFD_RELOC_386_GOT32:
6343 case BFD_RELOC_386_GOTOFF:
6344 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 6345 case BFD_RELOC_386_TLS_GD:
6346 case BFD_RELOC_386_TLS_LDM:
6347 case BFD_RELOC_386_TLS_LDO_32:
6348 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6349 case BFD_RELOC_386_TLS_IE:
6350 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 6351 case BFD_RELOC_386_TLS_LE_32:
6352 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 6353 case BFD_RELOC_386_TLS_GOTDESC:
6354 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 6355 case BFD_RELOC_X86_64_TLSGD:
6356 case BFD_RELOC_X86_64_TLSLD:
6357 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6358 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 6359 case BFD_RELOC_X86_64_GOTTPOFF:
6360 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 6361 case BFD_RELOC_X86_64_TPOFF64:
6362 case BFD_RELOC_X86_64_GOTOFF64:
6363 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 6364 case BFD_RELOC_X86_64_GOT64:
6365 case BFD_RELOC_X86_64_GOTPCREL64:
6366 case BFD_RELOC_X86_64_GOTPC64:
6367 case BFD_RELOC_X86_64_GOTPLT64:
6368 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 6369 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6370 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 6371 case BFD_RELOC_RVA:
6372 case BFD_RELOC_VTABLE_ENTRY:
6373 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 6374#ifdef TE_PE
6375 case BFD_RELOC_32_SECREL:
6376#endif
252b5132
RH		 6377 code = fixp->fx_r_type;
6378 break;
dbbaec26
L		 6379 case BFD_RELOC_X86_64_32S:
6380 if (!fixp->fx_pcrel)
6381 {
6382 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6383 code = fixp->fx_r_type;
6384 break;
6385 }
252b5132 6386 default:
93382f6d 6387 if (fixp->fx_pcrel)
252b5132 6388 {
93382f6d
AM		 6389 switch (fixp->fx_size)
6390 {
6391 default:
b091f402
AM		 6392 as_bad_where (fixp->fx_file, fixp->fx_line,
6393 _("can not do %d byte pc-relative relocation"),
6394 fixp->fx_size);
93382f6d
AM		 6395 code = BFD_RELOC_32_PCREL;
6396 break;
6397 case 1: code = BFD_RELOC_8_PCREL; break;
6398 case 2: code = BFD_RELOC_16_PCREL; break;
6399 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 6400#ifdef BFD64
6401 case 8: code = BFD_RELOC_64_PCREL; break;
6402#endif
93382f6d
AM		 6403 }
6404 }
6405 else
6406 {
6407 switch (fixp->fx_size)
6408 {
6409 default:
b091f402
AM		 6410 as_bad_where (fixp->fx_file, fixp->fx_line,
6411 _("can not do %d byte relocation"),
6412 fixp->fx_size);
93382f6d
AM		 6413 code = BFD_RELOC_32;
6414 break;
6415 case 1: code = BFD_RELOC_8; break;
6416 case 2: code = BFD_RELOC_16; break;
6417 case 4: code = BFD_RELOC_32; break;
937149dd 6418#ifdef BFD64
3e73aa7c 6419 case 8: code = BFD_RELOC_64; break;
937149dd 6420#endif
93382f6d 6421 }
252b5132
RH		 6422 }
6423 break;
6424 }
252b5132 6425
d182319b
JB		 6426 if ((code == BFD_RELOC_32
6427 || code == BFD_RELOC_32_PCREL
6428 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 6429 && GOT_symbol
6430 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 6431 {
4fa24527 6432 if (!object_64bit)
d6ab8113
JB		 6433 code = BFD_RELOC_386_GOTPC;
6434 else
6435 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 6436 }
7b81dfbb
AJ		 6437 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6438 && GOT_symbol
6439 && fixp->fx_addsy == GOT_symbol)
6440 {
6441 code = BFD_RELOC_X86_64_GOTPC64;
6442 }
252b5132
RH		 6443
6444 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 6445 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6446 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 6447
6448 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 6449
3e73aa7c
JH		 6450 if (!use_rela_relocations)
6451 {
6452 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6453 vtable entry to be used in the relocation's section offset. */
6454 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6455 rel->address = fixp->fx_offset;
252b5132 6456
c6682705 6457 rel->addend = 0;
3e73aa7c
JH		 6458 }
6459 /* Use the rela in 64bit mode. */
252b5132 6460 else
3e73aa7c 6461 {
062cd5e7
AS		 6462 if (!fixp->fx_pcrel)
6463 rel->addend = fixp->fx_offset;
6464 else
6465 switch (code)
6466 {
6467 case BFD_RELOC_X86_64_PLT32:
6468 case BFD_RELOC_X86_64_GOT32:
6469 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 6470 case BFD_RELOC_X86_64_TLSGD:
6471 case BFD_RELOC_X86_64_TLSLD:
6472 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 6473 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6474 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 6475 rel->addend = fixp->fx_offset - fixp->fx_size;
6476 break;
6477 default:
6478 rel->addend = (section->vma
6479 - fixp->fx_size
6480 + fixp->fx_addnumber
6481 + md_pcrel_from (fixp));
6482 break;
6483 }
3e73aa7c
JH		 6484 }
6485
252b5132
RH		 6486 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6487 if (rel->howto == NULL)
6488 {
6489 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 6490 _("cannot represent relocation type %s"),
252b5132
RH		 6491 bfd_get_reloc_code_name (code));
6492 /* Set howto to a garbage value so that we can keep going. */
6493 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6494 assert (rel->howto != NULL);
6495 }
6496
6497 return rel;
6498}
6499
64a0c779
DN		 6500\f
6501/* Parse operands using Intel syntax. This implements a recursive descent
6502 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6503 Programmer's Guide.
6504
6505 FIXME: We do not recognize the full operand grammar defined in the MASM
6506 documentation. In particular, all the structure/union and
6507 high-level macro operands are missing.
6508
6509 Uppercase words are terminals, lower case words are non-terminals.
6510 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6511 bars '|' denote choices. Most grammar productions are implemented in
6512 functions called 'intel_<production>'.
6513
6514 Initial production is 'expr'.
6515
9306ca4a 6516 addOp + | -
64a0c779
DN		 6517
6518 alpha [a-zA-Z]
6519
9306ca4a
JB		 6520 binOp & | AND | \| | OR | ^ | XOR
6521
64a0c779
DN		 6522 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6523
6524 constant digits [[ radixOverride ]]
6525
9306ca4a 6526 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 6527
6528 digits decdigit
b77a7acd
AJ		 6529 | digits decdigit
6530 | digits hexdigit
64a0c779
DN		 6531
6532 decdigit [0-9]
6533
9306ca4a
JB		 6534 e04 e04 addOp e05
6535 | e05
6536
6537 e05 e05 binOp e06
b77a7acd 6538 | e06
64a0c779
DN		 6539
6540 e06 e06 mulOp e09
b77a7acd 6541 | e09
64a0c779
DN		 6542
6543 e09 OFFSET e10
a724f0f4
JB		 6544 | SHORT e10
6545 | + e10
6546 | - e10
9306ca4a
JB		 6547 | ~ e10
6548 | NOT e10
64a0c779
DN		 6549 | e09 PTR e10
6550 | e09 : e10
6551 | e10
6552
6553 e10 e10 [ expr ]
b77a7acd 6554 | e11
64a0c779
DN		 6555
6556 e11 ( expr )
b77a7acd 6557 | [ expr ]
64a0c779
DN		 6558 | constant
6559 | dataType
6560 | id
6561 | $
6562 | register
6563
a724f0f4 6564 => expr expr cmpOp e04
9306ca4a 6565 | e04
64a0c779
DN		 6566
6567 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 6568 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 6569
6570 hexdigit a | b | c | d | e | f
b77a7acd 6571 | A | B | C | D | E | F
64a0c779
DN		 6572
6573 id alpha
b77a7acd 6574 | id alpha
64a0c779
DN		 6575 | id decdigit
6576
9306ca4a 6577 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 6578
6579 quote " | '
6580
6581 register specialRegister
b77a7acd 6582 | gpRegister
64a0c779
DN		 6583 | byteRegister
6584
6585 segmentRegister CS | DS | ES | FS | GS | SS
6586
9306ca4a 6587 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 6588 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 6589 | TR3 | TR4 | TR5 | TR6 | TR7
6590
64a0c779
DN		 6591 We simplify the grammar in obvious places (e.g., register parsing is
6592 done by calling parse_register) and eliminate immediate left recursion
6593 to implement a recursive-descent parser.
6594
a724f0f4
JB		 6595 expr e04 expr'
6596
6597 expr' cmpOp e04 expr'
6598 | Empty
9306ca4a
JB		 6599
6600 e04 e05 e04'
6601
6602 e04' addOp e05 e04'
6603 | Empty
64a0c779
DN		 6604
6605 e05 e06 e05'
6606
9306ca4a 6607 e05' binOp e06 e05'
b77a7acd 6608 | Empty
64a0c779
DN		 6609
6610 e06 e09 e06'
6611
6612 e06' mulOp e09 e06'
b77a7acd 6613 | Empty
64a0c779
DN		 6614
6615 e09 OFFSET e10 e09'
a724f0f4
JB		 6616 | SHORT e10'
6617 | + e10'
6618 | - e10'
6619 | ~ e10'
6620 | NOT e10'
b77a7acd 6621 | e10 e09'
64a0c779
DN		 6622
6623 e09' PTR e10 e09'
b77a7acd 6624 | : e10 e09'
64a0c779
DN		 6625 | Empty
6626
6627 e10 e11 e10'
6628
6629 e10' [ expr ] e10'
b77a7acd 6630 | Empty
64a0c779
DN		 6631
6632 e11 ( expr )
b77a7acd 6633 | [ expr ]
64a0c779
DN		 6634 | BYTE
6635 | WORD
6636 | DWORD
9306ca4a 6637 | FWORD
64a0c779 6638 | QWORD
9306ca4a
JB		 6639 | TBYTE
6640 | OWORD
6641 | XMMWORD
64a0c779
DN		 6642 | .
6643 | $
6644 | register
6645 | id
6646 | constant */
6647
6648/* Parsing structure for the intel syntax parser. Used to implement the
6649 semantic actions for the operand grammar. */
6650struct intel_parser_s
6651 {
6652 char *op_string; /* The string being parsed. */
6653 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6654 int op_modifier; /* Operand modifier. */
64a0c779 6655 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 6656 int in_offset; /* >=1 if parsing operand of offset. */
6657 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6658 const reg_entry *reg; /* Last register reference found. */
6659 char *disp; /* Displacement string being built. */
a724f0f4 6660 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6661 };
6662
6663static struct intel_parser_s intel_parser;
6664
6665/* Token structure for parsing intel syntax. */
6666struct intel_token
6667 {
6668 int code; /* Token code. */
6669 const reg_entry *reg; /* Register entry for register tokens. */
6670 char *str; /* String representation. */
6671 };
6672
6673static struct intel_token cur_token, prev_token;
6674
50705ef4
AM		 6675/* Token codes for the intel parser. Since T_SHORT is already used
6676 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6677#define T_NIL -1
6678#define T_CONST 1
6679#define T_REG 2
6680#define T_BYTE 3
6681#define T_WORD 4
9306ca4a
JB		 6682#define T_DWORD 5
6683#define T_FWORD 6
6684#define T_QWORD 7
6685#define T_TBYTE 8
6686#define T_XMMWORD 9
50705ef4 6687#undef T_SHORT
9306ca4a
JB		 6688#define T_SHORT 10
6689#define T_OFFSET 11
6690#define T_PTR 12
6691#define T_ID 13
6692#define T_SHL 14
6693#define T_SHR 15
64a0c779
DN		 6694
6695/* Prototypes for intel parser functions. */
e3bb37b5
L		 6696static int intel_match_token (int);
6697static void intel_putback_token (void);
6698static void intel_get_token (void);
6699static int intel_expr (void);
6700static int intel_e04 (void);
6701static int intel_e05 (void);
6702static int intel_e06 (void);
6703static int intel_e09 (void);
6704static int intel_e10 (void);
6705static int intel_e11 (void);
64a0c779 6706
64a0c779 6707static int
e3bb37b5 6708i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 6709{
6710 int ret;
6711 char *p;
6712
a724f0f4
JB		 6713 p = intel_parser.op_string = xstrdup (operand_string);
6714 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6715
6716 for (;;)
64a0c779 6717 {
a724f0f4
JB		 6718 /* Initialize token holders. */
6719 cur_token.code = prev_token.code = T_NIL;
6720 cur_token.reg = prev_token.reg = NULL;
6721 cur_token.str = prev_token.str = NULL;
6722
6723 /* Initialize parser structure. */
6724 intel_parser.got_a_float = got_a_float;
6725 intel_parser.op_modifier = 0;
6726 intel_parser.is_mem = 0;
6727 intel_parser.in_offset = 0;
6728 intel_parser.in_bracket = 0;
6729 intel_parser.reg = NULL;
6730 intel_parser.disp[0] = '\0';
6731 intel_parser.next_operand = NULL;
6732
6733 /* Read the first token and start the parser. */
6734 intel_get_token ();
6735 ret = intel_expr ();
6736
6737 if (!ret)
6738 break;
6739
9306ca4a
JB		 6740 if (cur_token.code != T_NIL)
6741 {
6742 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6743 current_templates->start->name, cur_token.str);
6744 ret = 0;
6745 }
64a0c779
DN		 6746 /* If we found a memory reference, hand it over to i386_displacement
6747 to fill in the rest of the operand fields. */
9306ca4a 6748 else if (intel_parser.is_mem)
64a0c779
DN		 6749 {
6750 if ((i.mem_operands == 1
6751 && (current_templates->start->opcode_modifier & IsString) == 0)
6752 || i.mem_operands == 2)
6753 {
6754 as_bad (_("too many memory references for '%s'"),
6755 current_templates->start->name);
6756 ret = 0;
6757 }
6758 else
6759 {
6760 char *s = intel_parser.disp;
6761 i.mem_operands++;
6762
a724f0f4
JB		 6763 if (!quiet_warnings && intel_parser.is_mem < 0)
6764 /* See the comments in intel_bracket_expr. */
6765 as_warn (_("Treating `%s' as memory reference"), operand_string);
6766
64a0c779
DN		 6767 /* Add the displacement expression. */
6768 if (*s != '\0')
a4622f40
AM		 6769 ret = i386_displacement (s, s + strlen (s));
6770 if (ret)
a724f0f4
JB		 6771 {
6772 /* Swap base and index in 16-bit memory operands like
6773 [si+bx]. Since i386_index_check is also used in AT&T
6774 mode we have to do that here. */
6775 if (i.base_reg
6776 && i.index_reg
6777 && (i.base_reg->reg_type & Reg16)
6778 && (i.index_reg->reg_type & Reg16)
6779 && i.base_reg->reg_num >= 6
6780 && i.index_reg->reg_num < 6)
6781 {
6782 const reg_entry *base = i.index_reg;
6783
6784 i.index_reg = i.base_reg;
6785 i.base_reg = base;
6786 }
6787 ret = i386_index_check (operand_string);
6788 }
64a0c779
DN		 6789 }
6790 }
6791
6792 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6793 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6794 || intel_parser.reg == NULL)
6795 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6796
6797 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 6798 ret = 0;
a724f0f4
JB		 6799 if (!ret || !intel_parser.next_operand)
6800 break;
6801 intel_parser.op_string = intel_parser.next_operand;
6802 this_operand = i.operands++;
64a0c779
DN		 6803 }
6804
6805 free (p);
6806 free (intel_parser.disp);
6807
6808 return ret;
6809}
6810
a724f0f4
JB		 6811#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6812
6813/* expr e04 expr'
6814
6815 expr' cmpOp e04 expr'
6816 | Empty */
64a0c779 6817static int
e3bb37b5 6818intel_expr (void)
64a0c779 6819{
a724f0f4
JB		 6820 /* XXX Implement the comparison operators. */
6821 return intel_e04 ();
9306ca4a
JB		 6822}
6823
a724f0f4 6824/* e04 e05 e04'
9306ca4a 6825
a724f0f4 6826 e04' addOp e05 e04'
9306ca4a
JB		 6827 | Empty */
6828static int
e3bb37b5 6829intel_e04 (void)
9306ca4a 6830{
a724f0f4 6831 int nregs = -1;
9306ca4a 6832
a724f0f4 6833 for (;;)
9306ca4a 6834 {
a724f0f4
JB		 6835 if (!intel_e05())
6836 return 0;
9306ca4a 6837
a724f0f4
JB		 6838 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6839 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6840
a724f0f4
JB		 6841 if (cur_token.code == '+')
6842 nregs = -1;
6843 else if (cur_token.code == '-')
6844 nregs = NUM_ADDRESS_REGS;
6845 else
6846 return 1;
64a0c779 6847
a724f0f4
JB		 6848 strcat (intel_parser.disp, cur_token.str);
6849 intel_match_token (cur_token.code);
6850 }
64a0c779
DN		 6851}
6852
64a0c779
DN		 6853/* e05 e06 e05'
6854
9306ca4a 6855 e05' binOp e06 e05'
64a0c779
DN		 6856 | Empty */
6857static int
e3bb37b5 6858intel_e05 (void)
64a0c779 6859{
a724f0f4 6860 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6861
a724f0f4 6862 for (;;)
64a0c779 6863 {
a724f0f4
JB		 6864 if (!intel_e06())
6865 return 0;
6866
4eed87de
AM		 6867 if (cur_token.code == '&'
6868 || cur_token.code == '|'
6869 || cur_token.code == '^')
a724f0f4
JB		 6870 {
6871 char str[2];
6872
6873 str[0] = cur_token.code;
6874 str[1] = 0;
6875 strcat (intel_parser.disp, str);
6876 }
6877 else
6878 break;
9306ca4a 6879
64a0c779
DN		 6880 intel_match_token (cur_token.code);
6881
a724f0f4
JB		 6882 if (nregs < 0)
6883 nregs = ~nregs;
64a0c779 6884 }
a724f0f4
JB		 6885 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6886 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6887 return 1;
4a1805b1 6888}
64a0c779
DN		 6889
6890/* e06 e09 e06'
6891
6892 e06' mulOp e09 e06'
b77a7acd 6893 | Empty */
64a0c779 6894static int
e3bb37b5 6895intel_e06 (void)
64a0c779 6896{
a724f0f4 6897 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6898
a724f0f4 6899 for (;;)
64a0c779 6900 {
a724f0f4
JB		 6901 if (!intel_e09())
6902 return 0;
9306ca4a 6903
4eed87de
AM		 6904 if (cur_token.code == '*'
6905 || cur_token.code == '/'
6906 || cur_token.code == '%')
a724f0f4
JB		 6907 {
6908 char str[2];
9306ca4a 6909
a724f0f4
JB		 6910 str[0] = cur_token.code;
6911 str[1] = 0;
6912 strcat (intel_parser.disp, str);
6913 }
6914 else if (cur_token.code == T_SHL)
6915 strcat (intel_parser.disp, "<<");
6916 else if (cur_token.code == T_SHR)
6917 strcat (intel_parser.disp, ">>");
6918 else
6919 break;
9306ca4a 6920
64e74474 6921 intel_match_token (cur_token.code);
64a0c779 6922
a724f0f4
JB		 6923 if (nregs < 0)
6924 nregs = ~nregs;
64a0c779 6925 }
a724f0f4
JB		 6926 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6927 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6928 return 1;
64a0c779
DN		 6929}
6930
a724f0f4
JB		 6931/* e09 OFFSET e09
6932 | SHORT e09
6933 | + e09
6934 | - e09
6935 | ~ e09
6936 | NOT e09
9306ca4a
JB		 6937 | e10 e09'
6938
64a0c779 6939 e09' PTR e10 e09'
b77a7acd 6940 | : e10 e09'
64a0c779
DN		 6941 | Empty */
6942static int
e3bb37b5 6943intel_e09 (void)
64a0c779 6944{
a724f0f4
JB		 6945 int nregs = ~NUM_ADDRESS_REGS;
6946 int in_offset = 0;
6947
6948 for (;;)
64a0c779 6949 {
a724f0f4
JB		 6950 /* Don't consume constants here. */
6951 if (cur_token.code == '+' || cur_token.code == '-')
6952 {
6953 /* Need to look one token ahead - if the next token
6954 is a constant, the current token is its sign. */
6955 int next_code;
6956
6957 intel_match_token (cur_token.code);
6958 next_code = cur_token.code;
6959 intel_putback_token ();
6960 if (next_code == T_CONST)
6961 break;
6962 }
6963
6964 /* e09 OFFSET e09 */
6965 if (cur_token.code == T_OFFSET)
6966 {
6967 if (!in_offset++)
6968 ++intel_parser.in_offset;
6969 }
6970
6971 /* e09 SHORT e09 */
6972 else if (cur_token.code == T_SHORT)
6973 intel_parser.op_modifier |= 1 << T_SHORT;
6974
6975 /* e09 + e09 */
6976 else if (cur_token.code == '+')
6977 strcat (intel_parser.disp, "+");
6978
6979 /* e09 - e09
6980 | ~ e09
6981 | NOT e09 */
6982 else if (cur_token.code == '-' || cur_token.code == '~')
6983 {
6984 char str[2];
64a0c779 6985
a724f0f4
JB		 6986 if (nregs < 0)
6987 nregs = ~nregs;
6988 str[0] = cur_token.code;
6989 str[1] = 0;
6990 strcat (intel_parser.disp, str);
6991 }
6992
6993 /* e09 e10 e09' */
6994 else
6995 break;
6996
6997 intel_match_token (cur_token.code);
64a0c779
DN		 6998 }
6999
a724f0f4 7000 for (;;)
9306ca4a 7001 {
a724f0f4
JB		 7002 if (!intel_e10 ())
7003 return 0;
9306ca4a 7004
a724f0f4
JB		 7005 /* e09' PTR e10 e09' */
7006 if (cur_token.code == T_PTR)
7007 {
7008 char suffix;
9306ca4a 7009
a724f0f4
JB		 7010 if (prev_token.code == T_BYTE)
7011 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 7012
a724f0f4
JB		 7013 else if (prev_token.code == T_WORD)
7014 {
7015 if (current_templates->start->name[0] == 'l'
7016 && current_templates->start->name[2] == 's'
7017 && current_templates->start->name[3] == 0)
7018 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7019 else if (intel_parser.got_a_float == 2) /* "fi..." */
7020 suffix = SHORT_MNEM_SUFFIX;
7021 else
7022 suffix = WORD_MNEM_SUFFIX;
7023 }
64a0c779 7024
a724f0f4
JB		 7025 else if (prev_token.code == T_DWORD)
7026 {
7027 if (current_templates->start->name[0] == 'l'
7028 && current_templates->start->name[2] == 's'
7029 && current_templates->start->name[3] == 0)
7030 suffix = WORD_MNEM_SUFFIX;
7031 else if (flag_code == CODE_16BIT
7032 && (current_templates->start->opcode_modifier
435acd52 7033 & (Jump | JumpDword)))
a724f0f4
JB		 7034 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7035 else if (intel_parser.got_a_float == 1) /* "f..." */
7036 suffix = SHORT_MNEM_SUFFIX;
7037 else
7038 suffix = LONG_MNEM_SUFFIX;
7039 }
9306ca4a 7040
a724f0f4
JB		 7041 else if (prev_token.code == T_FWORD)
7042 {
7043 if (current_templates->start->name[0] == 'l'
7044 && current_templates->start->name[2] == 's'
7045 && current_templates->start->name[3] == 0)
7046 suffix = LONG_MNEM_SUFFIX;
7047 else if (!intel_parser.got_a_float)
7048 {
7049 if (flag_code == CODE_16BIT)
7050 add_prefix (DATA_PREFIX_OPCODE);
7051 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7052 }
7053 else
7054 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7055 }
64a0c779 7056
a724f0f4
JB		 7057 else if (prev_token.code == T_QWORD)
7058 {
7059 if (intel_parser.got_a_float == 1) /* "f..." */
7060 suffix = LONG_MNEM_SUFFIX;
7061 else
7062 suffix = QWORD_MNEM_SUFFIX;
7063 }
64a0c779 7064
a724f0f4
JB		 7065 else if (prev_token.code == T_TBYTE)
7066 {
7067 if (intel_parser.got_a_float == 1)
7068 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7069 else
7070 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7071 }
9306ca4a 7072
a724f0f4 7073 else if (prev_token.code == T_XMMWORD)
9306ca4a 7074 {
a724f0f4
JB		 7075 /* XXX ignored for now, but accepted since gcc uses it */
7076 suffix = 0;
9306ca4a 7077 }
64a0c779 7078
f16b83df 7079 else
a724f0f4
JB		 7080 {
7081 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
7082 return 0;
7083 }
7084
435acd52
JB		 7085 /* Operands for jump/call using 'ptr' notation denote absolute
7086 addresses. */
7087 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7088 i.types[this_operand] |= JumpAbsolute;
7089
a724f0f4
JB		 7090 if (current_templates->start->base_opcode == 0x8d /* lea */)
7091 ;
7092 else if (!i.suffix)
7093 i.suffix = suffix;
7094 else if (i.suffix != suffix)
7095 {
7096 as_bad (_("Conflicting operand modifiers"));
7097 return 0;
7098 }
64a0c779 7099
9306ca4a
JB		 7100 }
7101
a724f0f4
JB		 7102 /* e09' : e10 e09' */
7103 else if (cur_token.code == ':')
9306ca4a 7104 {
a724f0f4
JB		 7105 if (prev_token.code != T_REG)
7106 {
7107 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7108 segment/group identifier (which we don't have), using comma
7109 as the operand separator there is even less consistent, since
7110 there all branches only have a single operand. */
7111 if (this_operand != 0
7112 || intel_parser.in_offset
7113 || intel_parser.in_bracket
7114 || (!(current_templates->start->opcode_modifier
7115 & (Jump|JumpDword|JumpInterSegment))
7116 && !(current_templates->start->operand_types[0]
7117 & JumpAbsolute)))
7118 return intel_match_token (T_NIL);
7119 /* Remember the start of the 2nd operand and terminate 1st
7120 operand here.
7121 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7122 another expression), but it gets at least the simplest case
7123 (a plain number or symbol on the left side) right. */
7124 intel_parser.next_operand = intel_parser.op_string;
7125 *--intel_parser.op_string = '\0';
7126 return intel_match_token (':');
7127 }
9306ca4a 7128 }
64a0c779 7129
a724f0f4 7130 /* e09' Empty */
64a0c779 7131 else
a724f0f4 7132 break;
64a0c779 7133
a724f0f4
JB		 7134 intel_match_token (cur_token.code);
7135
7136 }
7137
7138 if (in_offset)
7139 {
7140 --intel_parser.in_offset;
7141 if (nregs < 0)
7142 nregs = ~nregs;
7143 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 7144 {
a724f0f4 7145 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 7146 return 0;
7147 }
a724f0f4
JB		 7148 intel_parser.op_modifier |= 1 << T_OFFSET;
7149 }
9306ca4a 7150
a724f0f4
JB		 7151 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7152 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7153 return 1;
7154}
64a0c779 7155
a724f0f4 7156static int
e3bb37b5 7157intel_bracket_expr (void)
a724f0f4
JB		 7158{
7159 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7160 const char *start = intel_parser.op_string;
7161 int len;
7162
7163 if (i.op[this_operand].regs)
7164 return intel_match_token (T_NIL);
7165
7166 intel_match_token ('[');
7167
7168 /* Mark as a memory operand only if it's not already known to be an
7169 offset expression. If it's an offset expression, we need to keep
7170 the brace in. */
7171 if (!intel_parser.in_offset)
7172 {
7173 ++intel_parser.in_bracket;
435acd52
JB		 7174
7175 /* Operands for jump/call inside brackets denote absolute addresses. */
7176 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7177 i.types[this_operand] |= JumpAbsolute;
7178
a724f0f4
JB		 7179 /* Unfortunately gas always diverged from MASM in a respect that can't
7180 be easily fixed without risking to break code sequences likely to be
7181 encountered (the testsuite even check for this): MASM doesn't consider
7182 an expression inside brackets unconditionally as a memory reference.
7183 When that is e.g. a constant, an offset expression, or the sum of the
7184 two, this is still taken as a constant load. gas, however, always
7185 treated these as memory references. As a compromise, we'll try to make
7186 offset expressions inside brackets work the MASM way (since that's
7187 less likely to be found in real world code), but make constants alone
7188 continue to work the traditional gas way. In either case, issue a
7189 warning. */
7190 intel_parser.op_modifier &= ~was_offset;
64a0c779 7191 }
a724f0f4 7192 else
64e74474 7193 strcat (intel_parser.disp, "[");
a724f0f4
JB		 7194
7195 /* Add a '+' to the displacement string if necessary. */
7196 if (*intel_parser.disp != '\0'
7197 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7198 strcat (intel_parser.disp, "+");
64a0c779 7199
a724f0f4
JB		 7200 if (intel_expr ()
7201 && (len = intel_parser.op_string - start - 1,
7202 intel_match_token (']')))
64a0c779 7203 {
a724f0f4
JB		 7204 /* Preserve brackets when the operand is an offset expression. */
7205 if (intel_parser.in_offset)
7206 strcat (intel_parser.disp, "]");
7207 else
7208 {
7209 --intel_parser.in_bracket;
7210 if (i.base_reg || i.index_reg)
7211 intel_parser.is_mem = 1;
7212 if (!intel_parser.is_mem)
7213 {
7214 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7215 /* Defer the warning until all of the operand was parsed. */
7216 intel_parser.is_mem = -1;
7217 else if (!quiet_warnings)
4eed87de
AM		 7218 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
7219 len, start, len, start);
a724f0f4
JB		 7220 }
7221 }
7222 intel_parser.op_modifier |= was_offset;
64a0c779 7223
a724f0f4 7224 return 1;
64a0c779 7225 }
a724f0f4 7226 return 0;
64a0c779
DN		 7227}
7228
7229/* e10 e11 e10'
7230
7231 e10' [ expr ] e10'
b77a7acd 7232 | Empty */
64a0c779 7233static int
e3bb37b5 7234intel_e10 (void)
64a0c779 7235{
a724f0f4
JB		 7236 if (!intel_e11 ())
7237 return 0;
64a0c779 7238
a724f0f4 7239 while (cur_token.code == '[')
64a0c779 7240 {
a724f0f4 7241 if (!intel_bracket_expr ())
21d6c4af 7242 return 0;
64a0c779
DN		 7243 }
7244
a724f0f4 7245 return 1;
64a0c779
DN		 7246}
7247
64a0c779 7248/* e11 ( expr )
b77a7acd 7249 | [ expr ]
64a0c779
DN		 7250 | BYTE
7251 | WORD
7252 | DWORD
9306ca4a 7253 | FWORD
64a0c779 7254 | QWORD
9306ca4a
JB		 7255 | TBYTE
7256 | OWORD
7257 | XMMWORD
4a1805b1 7258 | $
64a0c779
DN		 7259 | .
7260 | register
7261 | id
7262 | constant */
7263static int
e3bb37b5 7264intel_e11 (void)
64a0c779 7265{
a724f0f4 7266 switch (cur_token.code)
64a0c779 7267 {
a724f0f4
JB		 7268 /* e11 ( expr ) */
7269 case '(':
64a0c779
DN		 7270 intel_match_token ('(');
7271 strcat (intel_parser.disp, "(");
7272
7273 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7274 {
7275 strcat (intel_parser.disp, ")");
7276 return 1;
7277 }
a724f0f4 7278 return 0;
4a1805b1 7279
a724f0f4
JB		 7280 /* e11 [ expr ] */
7281 case '[':
a724f0f4 7282 return intel_bracket_expr ();
64a0c779 7283
a724f0f4
JB		 7284 /* e11 $
7285 | . */
7286 case '.':
64a0c779
DN		 7287 strcat (intel_parser.disp, cur_token.str);
7288 intel_match_token (cur_token.code);
21d6c4af
DN		 7289
7290 /* Mark as a memory operand only if it's not already known to be an
7291 offset expression. */
a724f0f4 7292 if (!intel_parser.in_offset)
21d6c4af 7293 intel_parser.is_mem = 1;
64a0c779
DN		 7294
7295 return 1;
64a0c779 7296
a724f0f4
JB		 7297 /* e11 register */
7298 case T_REG:
7299 {
7300 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7301
a724f0f4 7302 intel_match_token (T_REG);
64a0c779 7303
a724f0f4
JB		 7304 /* Check for segment change. */
7305 if (cur_token.code == ':')
7306 {
7307 if (!(reg->reg_type & (SReg2 | SReg3)))
7308 {
4eed87de
AM		 7309 as_bad (_("`%s' is not a valid segment register"),
7310 reg->reg_name);
a724f0f4
JB		 7311 return 0;
7312 }
7313 else if (i.seg[i.mem_operands])
7314 as_warn (_("Extra segment override ignored"));
7315 else
7316 {
7317 if (!intel_parser.in_offset)
7318 intel_parser.is_mem = 1;
7319 switch (reg->reg_num)
7320 {
7321 case 0:
7322 i.seg[i.mem_operands] = &es;
7323 break;
7324 case 1:
7325 i.seg[i.mem_operands] = &cs;
7326 break;
7327 case 2:
7328 i.seg[i.mem_operands] = &ss;
7329 break;
7330 case 3:
7331 i.seg[i.mem_operands] = &ds;
7332 break;
7333 case 4:
7334 i.seg[i.mem_operands] = &fs;
7335 break;
7336 case 5:
7337 i.seg[i.mem_operands] = &gs;
7338 break;
7339 }
7340 }
7341 }
64a0c779 7342
a724f0f4
JB		 7343 /* Not a segment register. Check for register scaling. */
7344 else if (cur_token.code == '*')
7345 {
7346 if (!intel_parser.in_bracket)
7347 {
7348 as_bad (_("Register scaling only allowed in memory operands"));
7349 return 0;
7350 }
64a0c779 7351
a724f0f4
JB		 7352 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7353 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7354 else if (i.index_reg)
7355 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 7356
a724f0f4
JB		 7357 /* What follows must be a valid scale. */
7358 intel_match_token ('*');
7359 i.index_reg = reg;
7360 i.types[this_operand] |= BaseIndex;
64a0c779 7361
a724f0f4
JB		 7362 /* Set the scale after setting the register (otherwise,
7363 i386_scale will complain) */
7364 if (cur_token.code == '+' || cur_token.code == '-')
7365 {
7366 char *str, sign = cur_token.code;
7367 intel_match_token (cur_token.code);
7368 if (cur_token.code != T_CONST)
7369 {
7370 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7371 cur_token.str);
7372 return 0;
7373 }
7374 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7375 strcpy (str + 1, cur_token.str);
7376 *str = sign;
7377 if (!i386_scale (str))
7378 return 0;
7379 free (str);
7380 }
7381 else if (!i386_scale (cur_token.str))
64a0c779 7382 return 0;
a724f0f4
JB		 7383 intel_match_token (cur_token.code);
7384 }
64a0c779 7385
a724f0f4
JB		 7386 /* No scaling. If this is a memory operand, the register is either a
7387 base register (first occurrence) or an index register (second
7388 occurrence). */
7b0441f6 7389 else if (intel_parser.in_bracket)
a724f0f4 7390 {
64a0c779 7391
a724f0f4
JB		 7392 if (!i.base_reg)
7393 i.base_reg = reg;
7394 else if (!i.index_reg)
7395 i.index_reg = reg;
7396 else
7397 {
7398 as_bad (_("Too many register references in memory operand"));
7399 return 0;
7400 }
64a0c779 7401
a724f0f4
JB		 7402 i.types[this_operand] |= BaseIndex;
7403 }
4a1805b1 7404
4d1bb795
JB		 7405 /* It's neither base nor index. */
7406 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 7407 {
7408 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7409 i.op[this_operand].regs = reg;
7410 i.reg_operands++;
7411 }
7412 else
7413 {
7414 as_bad (_("Invalid use of register"));
7415 return 0;
7416 }
64a0c779 7417
a724f0f4
JB		 7418 /* Since registers are not part of the displacement string (except
7419 when we're parsing offset operands), we may need to remove any
7420 preceding '+' from the displacement string. */
7421 if (*intel_parser.disp != '\0'
7422 && !intel_parser.in_offset)
7423 {
7424 char *s = intel_parser.disp;
7425 s += strlen (s) - 1;
7426 if (*s == '+')
7427 *s = '\0';
7428 }
4a1805b1 7429
a724f0f4
JB		 7430 return 1;
7431 }
7432
7433 /* e11 BYTE
7434 | WORD
7435 | DWORD
7436 | FWORD
7437 | QWORD
7438 | TBYTE
7439 | OWORD
7440 | XMMWORD */
7441 case T_BYTE:
7442 case T_WORD:
7443 case T_DWORD:
7444 case T_FWORD:
7445 case T_QWORD:
7446 case T_TBYTE:
7447 case T_XMMWORD:
7448 intel_match_token (cur_token.code);
64a0c779 7449
a724f0f4
JB		 7450 if (cur_token.code == T_PTR)
7451 return 1;
7452
7453 /* It must have been an identifier. */
7454 intel_putback_token ();
7455 cur_token.code = T_ID;
7456 /* FALLTHRU */
7457
7458 /* e11 id
7459 | constant */
7460 case T_ID:
7461 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 7462 {
7463 symbolS *symbolP;
7464
a724f0f4
JB		 7465 /* The identifier represents a memory reference only if it's not
7466 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 7467 symbolP = symbol_find(cur_token.str);
7468 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7469 intel_parser.is_mem = 1;
7470 }
a724f0f4 7471 /* FALLTHRU */
64a0c779 7472
a724f0f4
JB		 7473 case T_CONST:
7474 case '-':
7475 case '+':
7476 {
7477 char *save_str, sign = 0;
64a0c779 7478
a724f0f4
JB		 7479 /* Allow constants that start with `+' or `-'. */
7480 if (cur_token.code == '-' || cur_token.code == '+')
7481 {
7482 sign = cur_token.code;
7483 intel_match_token (cur_token.code);
7484 if (cur_token.code != T_CONST)
7485 {
7486 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7487 cur_token.str);
7488 return 0;
7489 }
7490 }
64a0c779 7491
a724f0f4
JB		 7492 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7493 strcpy (save_str + !!sign, cur_token.str);
7494 if (sign)
7495 *save_str = sign;
64a0c779 7496
a724f0f4
JB		 7497 /* Get the next token to check for register scaling. */
7498 intel_match_token (cur_token.code);
64a0c779 7499
4eed87de
AM		 7500 /* Check if this constant is a scaling factor for an
7501 index register. */
a724f0f4
JB		 7502 if (cur_token.code == '*')
7503 {
7504 if (intel_match_token ('*') && cur_token.code == T_REG)
7505 {
7506 const reg_entry *reg = cur_token.reg;
7507
7508 if (!intel_parser.in_bracket)
7509 {
4eed87de
AM		 7510 as_bad (_("Register scaling only allowed "
7511 "in memory operands"));
a724f0f4
JB		 7512 return 0;
7513 }
7514
4eed87de
AM		 7515 /* Disallow things like [1*si].
7516 sp and esp are invalid as index. */
7517 if (reg->reg_type & Reg16)
7518 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 7519 else if (i.index_reg)
4eed87de 7520 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 7521
7522 /* The constant is followed by `* reg', so it must be
7523 a valid scale. */
7524 i.index_reg = reg;
7525 i.types[this_operand] |= BaseIndex;
7526
7527 /* Set the scale after setting the register (otherwise,
7528 i386_scale will complain) */
7529 if (!i386_scale (save_str))
64a0c779 7530 return 0;
a724f0f4
JB		 7531 intel_match_token (T_REG);
7532
7533 /* Since registers are not part of the displacement
7534 string, we may need to remove any preceding '+' from
7535 the displacement string. */
7536 if (*intel_parser.disp != '\0')
7537 {
7538 char *s = intel_parser.disp;
7539 s += strlen (s) - 1;
7540 if (*s == '+')
7541 *s = '\0';
7542 }
7543
7544 free (save_str);
7545
7546 return 1;
7547 }
64a0c779 7548
a724f0f4
JB		 7549 /* The constant was not used for register scaling. Since we have
7550 already consumed the token following `*' we now need to put it
7551 back in the stream. */
64a0c779 7552 intel_putback_token ();
a724f0f4 7553 }
64a0c779 7554
a724f0f4
JB		 7555 /* Add the constant to the displacement string. */
7556 strcat (intel_parser.disp, save_str);
7557 free (save_str);
64a0c779 7558
a724f0f4
JB		 7559 return 1;
7560 }
64a0c779
DN		 7561 }
7562
64a0c779
DN		 7563 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7564 return 0;
7565}
7566
64a0c779
DN		 7567/* Match the given token against cur_token. If they match, read the next
7568 token from the operand string. */
7569static int
e3bb37b5 7570intel_match_token (int code)
64a0c779
DN		 7571{
7572 if (cur_token.code == code)
7573 {
7574 intel_get_token ();
7575 return 1;
7576 }
7577 else
7578 {
0477af35 7579 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 7580 return 0;
7581 }
7582}
7583
64a0c779
DN		 7584/* Read a new token from intel_parser.op_string and store it in cur_token. */
7585static void
e3bb37b5 7586intel_get_token (void)
64a0c779
DN		 7587{
7588 char *end_op;
7589 const reg_entry *reg;
7590 struct intel_token new_token;
7591
7592 new_token.code = T_NIL;
7593 new_token.reg = NULL;
7594 new_token.str = NULL;
7595
4a1805b1 7596 /* Free the memory allocated to the previous token and move
64a0c779
DN		 7597 cur_token to prev_token. */
7598 if (prev_token.str)
7599 free (prev_token.str);
7600
7601 prev_token = cur_token;
7602
7603 /* Skip whitespace. */
7604 while (is_space_char (*intel_parser.op_string))
7605 intel_parser.op_string++;
7606
7607 /* Return an empty token if we find nothing else on the line. */
7608 if (*intel_parser.op_string == '\0')
7609 {
7610 cur_token = new_token;
7611 return;
7612 }
7613
7614 /* The new token cannot be larger than the remainder of the operand
7615 string. */
a724f0f4 7616 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7617 new_token.str[0] = '\0';
7618
7619 if (strchr ("0123456789", *intel_parser.op_string))
7620 {
7621 char *p = new_token.str;
7622 char *q = intel_parser.op_string;
7623 new_token.code = T_CONST;
7624
7625 /* Allow any kind of identifier char to encompass floating point and
7626 hexadecimal numbers. */
7627 while (is_identifier_char (*q))
7628 *p++ = *q++;
7629 *p = '\0';
7630
7631 /* Recognize special symbol names [0-9][bf]. */
7632 if (strlen (intel_parser.op_string) == 2
4a1805b1 7633 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7634 || intel_parser.op_string[1] == 'f'))
7635 new_token.code = T_ID;
7636 }
7637
4d1bb795 7638 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7639 {
4d1bb795
JB		 7640 size_t len = end_op - intel_parser.op_string;
7641
64a0c779
DN		 7642 new_token.code = T_REG;
7643 new_token.reg = reg;
7644
4d1bb795
JB		 7645 memcpy (new_token.str, intel_parser.op_string, len);
7646 new_token.str[len] = '\0';
64a0c779
DN		 7647 }
7648
7649 else if (is_identifier_char (*intel_parser.op_string))
7650 {
7651 char *p = new_token.str;
7652 char *q = intel_parser.op_string;
7653
7654 /* A '.' or '$' followed by an identifier char is an identifier.
7655 Otherwise, it's operator '.' followed by an expression. */
7656 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7657 {
9306ca4a
JB		 7658 new_token.code = '.';
7659 new_token.str[0] = '.';
64a0c779
DN		 7660 new_token.str[1] = '\0';
7661 }
7662 else
7663 {
7664 while (is_identifier_char (*q) || *q == '@')
7665 *p++ = *q++;
7666 *p = '\0';
7667
9306ca4a
JB		 7668 if (strcasecmp (new_token.str, "NOT") == 0)
7669 new_token.code = '~';
7670
7671 else if (strcasecmp (new_token.str, "MOD") == 0)
7672 new_token.code = '%';
7673
7674 else if (strcasecmp (new_token.str, "AND") == 0)
7675 new_token.code = '&';
7676
7677 else if (strcasecmp (new_token.str, "OR") == 0)
7678 new_token.code = '|';
7679
7680 else if (strcasecmp (new_token.str, "XOR") == 0)
7681 new_token.code = '^';
7682
7683 else if (strcasecmp (new_token.str, "SHL") == 0)
7684 new_token.code = T_SHL;
7685
7686 else if (strcasecmp (new_token.str, "SHR") == 0)
7687 new_token.code = T_SHR;
7688
7689 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7690 new_token.code = T_BYTE;
7691
7692 else if (strcasecmp (new_token.str, "WORD") == 0)
7693 new_token.code = T_WORD;
7694
7695 else if (strcasecmp (new_token.str, "DWORD") == 0)
7696 new_token.code = T_DWORD;
7697
9306ca4a
JB		 7698 else if (strcasecmp (new_token.str, "FWORD") == 0)
7699 new_token.code = T_FWORD;
7700
64a0c779
DN		 7701 else if (strcasecmp (new_token.str, "QWORD") == 0)
7702 new_token.code = T_QWORD;
7703
9306ca4a
JB		 7704 else if (strcasecmp (new_token.str, "TBYTE") == 0
7705 /* XXX remove (gcc still uses it) */
7706 || strcasecmp (new_token.str, "XWORD") == 0)
7707 new_token.code = T_TBYTE;
7708
7709 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7710 || strcasecmp (new_token.str, "OWORD") == 0)
7711 new_token.code = T_XMMWORD;
64a0c779
DN		 7712
7713 else if (strcasecmp (new_token.str, "PTR") == 0)
7714 new_token.code = T_PTR;
7715
7716 else if (strcasecmp (new_token.str, "SHORT") == 0)
7717 new_token.code = T_SHORT;
7718
7719 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7720 {
7721 new_token.code = T_OFFSET;
7722
7723 /* ??? This is not mentioned in the MASM grammar but gcc
7724 makes use of it with -mintel-syntax. OFFSET may be
7725 followed by FLAT: */
7726 if (strncasecmp (q, " FLAT:", 6) == 0)
7727 strcat (new_token.str, " FLAT:");
7728 }
7729
7730 /* ??? This is not mentioned in the MASM grammar. */
7731 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7732 {
7733 new_token.code = T_OFFSET;
7734 if (*q == ':')
7735 strcat (new_token.str, ":");
7736 else
7737 as_bad (_("`:' expected"));
7738 }
64a0c779
DN		 7739
7740 else
7741 new_token.code = T_ID;
7742 }
7743 }
7744
9306ca4a
JB		 7745 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7746 {
7747 new_token.code = *intel_parser.op_string;
7748 new_token.str[0] = *intel_parser.op_string;
7749 new_token.str[1] = '\0';
7750 }
7751
7752 else if (strchr ("<>", *intel_parser.op_string)
7753 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7754 {
7755 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7756 new_token.str[0] = *intel_parser.op_string;
7757 new_token.str[1] = *intel_parser.op_string;
7758 new_token.str[2] = '\0';
7759 }
7760
64a0c779 7761 else
0477af35 7762 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7763
7764 intel_parser.op_string += strlen (new_token.str);
7765 cur_token = new_token;
7766}
7767
64a0c779
DN		 7768/* Put cur_token back into the token stream and make cur_token point to
7769 prev_token. */
7770static void
e3bb37b5 7771intel_putback_token (void)
64a0c779 7772{
a724f0f4
JB		 7773 if (cur_token.code != T_NIL)
7774 {
7775 intel_parser.op_string -= strlen (cur_token.str);
7776 free (cur_token.str);
7777 }
64a0c779 7778 cur_token = prev_token;
4a1805b1 7779
64a0c779
DN		 7780 /* Forget prev_token. */
7781 prev_token.code = T_NIL;
7782 prev_token.reg = NULL;
7783 prev_token.str = NULL;
7784}
54cfded0 7785
a4447b93 7786int
1df69f4f 7787tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 7788{
7789 unsigned int regnum;
7790 unsigned int regnames_count;
089dfecd 7791 static const char *const regnames_32[] =
54cfded0 7792 {
a4447b93
RH		 7793 "eax", "ecx", "edx", "ebx",
7794 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7795 "eip", "eflags", NULL,
7796 "st0", "st1", "st2", "st3",
7797 "st4", "st5", "st6", "st7",
7798 NULL, NULL,
7799 "xmm0", "xmm1", "xmm2", "xmm3",
7800 "xmm4", "xmm5", "xmm6", "xmm7",
7801 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7802 "mm4", "mm5", "mm6", "mm7",
7803 "fcw", "fsw", "mxcsr",
7804 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7805 "tr", "ldtr"
54cfded0 7806 };
089dfecd 7807 static const char *const regnames_64[] =
54cfded0 7808 {
089dfecd
JB		 7809 "rax", "rdx", "rcx", "rbx",
7810 "rsi", "rdi", "rbp", "rsp",
7811 "r8", "r9", "r10", "r11",
54cfded0 7812 "r12", "r13", "r14", "r15",
089dfecd
JB		 7813 "rip",
7814 "xmm0", "xmm1", "xmm2", "xmm3",
7815 "xmm4", "xmm5", "xmm6", "xmm7",
7816 "xmm8", "xmm9", "xmm10", "xmm11",
7817 "xmm12", "xmm13", "xmm14", "xmm15",
7818 "st0", "st1", "st2", "st3",
7819 "st4", "st5", "st6", "st7",
7820 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7821 "mm4", "mm5", "mm6", "mm7",
7822 "rflags",
7823 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7824 "fs.base", "gs.base", NULL, NULL,
7825 "tr", "ldtr",
7826 "mxcsr", "fcw", "fsw"
54cfded0 7827 };
089dfecd 7828 const char *const *regnames;
54cfded0
AM		 7829
7830 if (flag_code == CODE_64BIT)
7831 {
7832 regnames = regnames_64;
0cea6190 7833 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7834 }
7835 else
7836 {
7837 regnames = regnames_32;
0cea6190 7838 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7839 }
7840
7841 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7842 if (regnames[regnum] != NULL
7843 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7844 return regnum;
7845
54cfded0
AM		 7846 return -1;
7847}
7848
7849void
7850tc_x86_frame_initial_instructions (void)
7851{
a4447b93
RH		 7852 static unsigned int sp_regno;
7853
7854 if (!sp_regno)
7855 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7856 ? "rsp" : "esp");
7857
7858 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7859 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7860}
d2b2c203
DJ		 7861
7862int
7863i386_elf_section_type (const char *str, size_t len)
7864{
7865 if (flag_code == CODE_64BIT
7866 && len == sizeof ("unwind") - 1
7867 && strncmp (str, "unwind", 6) == 0)
7868 return SHT_X86_64_UNWIND;
7869
7870 return -1;
7871}
bb41ade5
AM		 7872
7873#ifdef TE_PE
7874void
7875tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7876{
7877 expressionS expr;
7878
7879 expr.X_op = O_secrel;
7880 expr.X_add_symbol = symbol;
7881 expr.X_add_number = 0;
7882 emit_expr (&expr, size);
7883}
7884#endif
3b22753a
L		 7885
7886#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7887/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7888
7889int
7890x86_64_section_letter (int letter, char **ptr_msg)
7891{
7892 if (flag_code == CODE_64BIT)
7893 {
7894 if (letter == 'l')
7895 return SHF_X86_64_LARGE;
7896
7897 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7898 }
3b22753a 7899 else
64e74474 7900 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7901 return -1;
7902}
7903
7904int
7905x86_64_section_word (char *str, size_t len)
7906{
8620418b 7907 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 7908 return SHF_X86_64_LARGE;
7909
7910 return -1;
7911}
7912
7913static void
7914handle_large_common (int small ATTRIBUTE_UNUSED)
7915{
7916 if (flag_code != CODE_64BIT)
7917 {
7918 s_comm_internal (0, elf_common_parse);
7919 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7920 }
7921 else
7922 {
7923 static segT lbss_section;
7924 asection *saved_com_section_ptr = elf_com_section_ptr;
7925 asection *saved_bss_section = bss_section;
7926
7927 if (lbss_section == NULL)
7928 {
7929 flagword applicable;
7930 segT seg = now_seg;
7931 subsegT subseg = now_subseg;
7932
7933 /* The .lbss section is for local .largecomm symbols. */
7934 lbss_section = subseg_new (".lbss", 0);
7935 applicable = bfd_applicable_section_flags (stdoutput);
7936 bfd_set_section_flags (stdoutput, lbss_section,
7937 applicable & SEC_ALLOC);
7938 seg_info (lbss_section)->bss = 1;
7939
7940 subseg_set (seg, subseg);
7941 }
7942
7943 elf_com_section_ptr = &_bfd_elf_large_com_section;
7944 bss_section = lbss_section;
7945
7946 s_comm_internal (0, elf_common_parse);
7947
7948 elf_com_section_ptr = saved_com_section_ptr;
7949 bss_section = saved_bss_section;
7950 }
7951}
7952#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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