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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4dc85607 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
e3bb37b5
L		 66static void set_code_flag (int);
67static void set_16bit_gcc_code_flag (int);
68static void set_intel_syntax (int);
69static void set_cpu_arch (int);
6482c264 70#ifdef TE_PE
e3bb37b5 71static void pe_directive_secrel (int);
6482c264 72#endif
e3bb37b5
L		 73static void signed_cons (int);
74static char *output_invalid (int c);
75static int i386_operand (char *);
76static int i386_intel_operand (char *, int);
77static const reg_entry *parse_register (char *, char **);
78static char *parse_insn (char *, char *);
79static char *parse_operands (char *, const char *);
80static void swap_operands (void);
81static void swap_imm_operands (void);
82static void optimize_imm (void);
83static void optimize_disp (void);
84static int match_template (void);
85static int check_string (void);
86static int process_suffix (void);
87static int check_byte_reg (void);
88static int check_long_reg (void);
89static int check_qword_reg (void);
90static int check_word_reg (void);
91static int finalize_imm (void);
92static int process_operands (void);
93static const seg_entry *build_modrm_byte (void);
94static void output_insn (void);
95static void output_imm (fragS *, offsetT);
96static void output_disp (fragS *, offsetT);
29b0f896 97#ifndef I386COFF
e3bb37b5 98static void s_bss (int);
252b5132 99#endif
17d4e2a2
L		 100#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
101static void handle_large_common (int small ATTRIBUTE_UNUSED);
102#endif
252b5132 103
a847613f 104static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 105
252b5132 106/* 'md_assemble ()' gathers together information and puts it into a
47926f60 107 i386_insn. */
252b5132 108
520dc8e8
AM		 109union i386_op
110 {
111 expressionS *disps;
112 expressionS *imms;
113 const reg_entry *regs;
114 };
115
252b5132
RH		 116struct _i386_insn
117 {
47926f60 118 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 119 template tm;
120
121 /* SUFFIX holds the instruction mnemonic suffix if given.
122 (e.g. 'l' for 'movl') */
123 char suffix;
124
47926f60 125 /* OPERANDS gives the number of given operands. */
252b5132
RH		 126 unsigned int operands;
127
128 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
129 of given register, displacement, memory operands and immediate
47926f60 130 operands. */
252b5132
RH		 131 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
132
133 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 134 use OP[i] for the corresponding operand. */
252b5132
RH		 135 unsigned int types[MAX_OPERANDS];
136
520dc8e8
AM		 137 /* Displacement expression, immediate expression, or register for each
138 operand. */
139 union i386_op op[MAX_OPERANDS];
252b5132 140
3e73aa7c
JH		 141 /* Flags for operands. */
142 unsigned int flags[MAX_OPERANDS];
143#define Operand_PCrel 1
144
252b5132 145 /* Relocation type for operand */
f86103b7 146 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 147
252b5132
RH		 148 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
149 the base index byte below. */
150 const reg_entry *base_reg;
151 const reg_entry *index_reg;
152 unsigned int log2_scale_factor;
153
154 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 155 explicit segment overrides are given. */
ce8a8b2f 156 const seg_entry *seg[2];
252b5132
RH		 157
158 /* PREFIX holds all the given prefix opcodes (usually null).
159 PREFIXES is the number of prefix opcodes. */
160 unsigned int prefixes;
161 unsigned char prefix[MAX_PREFIXES];
162
163 /* RM and SIB are the modrm byte and the sib byte where the
164 addressing modes of this insn are encoded. */
165
166 modrm_byte rm;
3e73aa7c 167 rex_byte rex;
252b5132
RH		 168 sib_byte sib;
169 };
170
171typedef struct _i386_insn i386_insn;
172
173/* List of chars besides those in app.c:symbol_chars that can start an
174 operand. Used to prevent the scrubber eating vital white-space. */
32137342 175const char extra_symbol_chars[] = "*%-(["
252b5132 176#ifdef LEX_AT
32137342
NC		 177 "@"
178#endif
179#ifdef LEX_QM
180 "?"
252b5132 181#endif
32137342 182 ;
252b5132 183
29b0f896
AM		 184#if (defined (TE_I386AIX) \
185 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 186 && !defined (TE_GNU) \
29b0f896 187 && !defined (TE_LINUX) \
32137342 188 && !defined (TE_NETWARE) \
29b0f896
AM		 189 && !defined (TE_FreeBSD) \
190 && !defined (TE_NetBSD)))
252b5132 191/* This array holds the chars that always start a comment. If the
b3b91714
AM		 192 pre-processor is disabled, these aren't very useful. The option
193 --divide will remove '/' from this list. */
194const char *i386_comment_chars = "#/";
195#define SVR4_COMMENT_CHARS 1
252b5132 196#define PREFIX_SEPARATOR '\\'
252b5132 197
b3b91714
AM		 198#else
199const char *i386_comment_chars = "#";
200#define PREFIX_SEPARATOR '/'
201#endif
202
252b5132
RH		 203/* This array holds the chars that only start a comment at the beginning of
204 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 205 .line and .file directives will appear in the pre-processed output.
206 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 207 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 208 #NO_APP at the beginning of its output.
209 Also note that comments started like this one will always work if
252b5132 210 '/' isn't otherwise defined. */
b3b91714 211const char line_comment_chars[] = "#/";
252b5132 212
63a0b638 213const char line_separator_chars[] = ";";
252b5132 214
ce8a8b2f
AM		 215/* Chars that can be used to separate mant from exp in floating point
216 nums. */
252b5132
RH		 217const char EXP_CHARS[] = "eE";
218
ce8a8b2f
AM		 219/* Chars that mean this number is a floating point constant
220 As in 0f12.456
221 or 0d1.2345e12. */
252b5132
RH		 222const char FLT_CHARS[] = "fFdDxX";
223
ce8a8b2f 224/* Tables for lexical analysis. */
252b5132
RH		 225static char mnemonic_chars[256];
226static char register_chars[256];
227static char operand_chars[256];
228static char identifier_chars[256];
229static char digit_chars[256];
230
ce8a8b2f 231/* Lexical macros. */
252b5132
RH		 232#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
233#define is_operand_char(x) (operand_chars[(unsigned char) x])
234#define is_register_char(x) (register_chars[(unsigned char) x])
235#define is_space_char(x) ((x) == ' ')
236#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
237#define is_digit_char(x) (digit_chars[(unsigned char) x])
238
0234cb7c 239/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 240static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
241
242/* md_assemble() always leaves the strings it's passed unaltered. To
243 effect this we maintain a stack of saved characters that we've smashed
244 with '\0's (indicating end of strings for various sub-fields of the
47926f60 245 assembler instruction). */
252b5132 246static char save_stack[32];
ce8a8b2f 247static char *save_stack_p;
252b5132
RH		 248#define END_STRING_AND_SAVE(s) \
249 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
250#define RESTORE_END_STRING(s) \
251 do { *(s) = *--save_stack_p; } while (0)
252
47926f60 253/* The instruction we're assembling. */
252b5132
RH		 254static i386_insn i;
255
256/* Possible templates for current insn. */
257static const templates *current_templates;
258
31b2323c
L		 259/* Per instruction expressionS buffers: max displacements & immediates. */
260static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
261static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 262
47926f60
KH		 263/* Current operand we are working on. */
264static int this_operand;
252b5132 265
3e73aa7c
JH		 266/* We support four different modes. FLAG_CODE variable is used to distinguish
267 these. */
268
269enum flag_code {
270 CODE_32BIT,
271 CODE_16BIT,
272 CODE_64BIT };
f3c180ae 273#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 274
275static enum flag_code flag_code;
4fa24527 276static unsigned int object_64bit;
3e73aa7c
JH		 277static int use_rela_relocations = 0;
278
279/* The names used to print error messages. */
b77a7acd 280static const char *flag_code_names[] =
3e73aa7c
JH		 281 {
282 "32",
283 "16",
284 "64"
285 };
252b5132 286
47926f60
KH		 287/* 1 for intel syntax,
288 0 if att syntax. */
289static int intel_syntax = 0;
252b5132 290
47926f60
KH		 291/* 1 if register prefix % not required. */
292static int allow_naked_reg = 0;
252b5132 293
2ca3ace5
L		 294/* Register prefix used for error message. */
295static const char *register_prefix = "%";
296
47926f60
KH		 297/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
298 leave, push, and pop instructions so that gcc has the same stack
299 frame as in 32 bit mode. */
300static char stackop_size = '\0';
eecb386c 301
12b55ccc
L		 302/* Non-zero to optimize code alignment. */
303int optimize_align_code = 1;
304
47926f60
KH		 305/* Non-zero to quieten some warnings. */
306static int quiet_warnings = 0;
a38cf1db 307
47926f60
KH		 308/* CPU name. */
309static const char *cpu_arch_name = NULL;
5c6af06e 310static const char *cpu_sub_arch_name = NULL;
a38cf1db 311
47926f60 312/* CPU feature flags. */
29b0f896 313static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 314
ccc9c027
L		 315/* If we have selected a cpu we are generating instructions for. */
316static int cpu_arch_tune_set = 0;
317
9103f4f4
L		 318/* Cpu we are generating instructions for. */
319static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
320
321/* CPU feature flags of cpu we are generating instructions for. */
322static unsigned int cpu_arch_tune_flags = 0;
323
ccc9c027
L		 324/* CPU instruction set architecture used. */
325static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
326
9103f4f4
L		 327/* CPU feature flags of instruction set architecture used. */
328static unsigned int cpu_arch_isa_flags = 0;
329
fddf5b5b
AM		 330/* If set, conditional jumps are not automatically promoted to handle
331 larger than a byte offset. */
332static unsigned int no_cond_jump_promotion = 0;
333
29b0f896 334/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 335static symbolS *GOT_symbol;
29b0f896 336
a4447b93
RH		 337/* The dwarf2 return column, adjusted for 32 or 64 bit. */
338unsigned int x86_dwarf2_return_column;
339
340/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
341int x86_cie_data_alignment;
342
252b5132 343/* Interface to relax_segment.
fddf5b5b
AM		 344 There are 3 major relax states for 386 jump insns because the
345 different types of jumps add different sizes to frags when we're
346 figuring out what sort of jump to choose to reach a given label. */
252b5132 347
47926f60 348/* Types. */
93c2a809
AM		 349#define UNCOND_JUMP 0
350#define COND_JUMP 1
351#define COND_JUMP86 2
fddf5b5b 352
47926f60 353/* Sizes. */
252b5132
RH		 354#define CODE16 1
355#define SMALL 0
29b0f896 356#define SMALL16 (SMALL | CODE16)
252b5132 357#define BIG 2
29b0f896 358#define BIG16 (BIG | CODE16)
252b5132
RH		 359
360#ifndef INLINE
361#ifdef __GNUC__
362#define INLINE __inline__
363#else
364#define INLINE
365#endif
366#endif
367
fddf5b5b
AM		 368#define ENCODE_RELAX_STATE(type, size) \
369 ((relax_substateT) (((type) << 2) | (size)))
370#define TYPE_FROM_RELAX_STATE(s) \
371 ((s) >> 2)
372#define DISP_SIZE_FROM_RELAX_STATE(s) \
373 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 374
375/* This table is used by relax_frag to promote short jumps to long
376 ones where necessary. SMALL (short) jumps may be promoted to BIG
377 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
378 don't allow a short jump in a 32 bit code segment to be promoted to
379 a 16 bit offset jump because it's slower (requires data size
380 prefix), and doesn't work, unless the destination is in the bottom
381 64k of the code segment (The top 16 bits of eip are zeroed). */
382
383const relax_typeS md_relax_table[] =
384{
24eab124
AM		 385 /* The fields are:
386 1) most positive reach of this state,
387 2) most negative reach of this state,
93c2a809 388 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 389 4) which index into the table to try if we can't fit into this one. */
252b5132 390
fddf5b5b 391 /* UNCOND_JUMP states. */
93c2a809
AM		 392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
393 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
394 /* dword jmp adds 4 bytes to frag:
395 0 extra opcode bytes, 4 displacement bytes. */
252b5132 396 {0, 0, 4, 0},
93c2a809
AM		 397 /* word jmp adds 2 byte2 to frag:
398 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 399 {0, 0, 2, 0},
400
93c2a809
AM		 401 /* COND_JUMP states. */
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
403 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
404 /* dword conditionals adds 5 bytes to frag:
405 1 extra opcode byte, 4 displacement bytes. */
406 {0, 0, 5, 0},
fddf5b5b 407 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 408 1 extra opcode byte, 2 displacement bytes. */
409 {0, 0, 3, 0},
410
411 /* COND_JUMP86 states. */
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
413 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
414 /* dword conditionals adds 5 bytes to frag:
415 1 extra opcode byte, 4 displacement bytes. */
416 {0, 0, 5, 0},
417 /* word conditionals add 4 bytes to frag:
418 1 displacement byte and a 3 byte long branch insn. */
419 {0, 0, 4, 0}
252b5132
RH		 420};
421
9103f4f4
L		 422static const arch_entry cpu_arch[] =
423{
424 {"generic32", PROCESSOR_GENERIC32,
d32cad65 425 Cpu186|Cpu286|Cpu386},
9103f4f4 426 {"generic64", PROCESSOR_GENERIC64,
d32cad65 427 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 428 |CpuMMX2|CpuSSE|CpuSSE2},
429 {"i8086", PROCESSOR_UNKNOWN,
d32cad65 430 0},
9103f4f4 431 {"i186", PROCESSOR_UNKNOWN,
d32cad65 432 Cpu186},
9103f4f4 433 {"i286", PROCESSOR_UNKNOWN,
d32cad65 434 Cpu186|Cpu286},
9103f4f4 435 {"i386", PROCESSOR_GENERIC32,
d32cad65 436 Cpu186|Cpu286|Cpu386},
9103f4f4 437 {"i486", PROCESSOR_I486,
d32cad65 438 Cpu186|Cpu286|Cpu386|Cpu486},
9103f4f4 439 {"i586", PROCESSOR_PENTIUM,
d32cad65 440 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 441 {"i686", PROCESSOR_PENTIUMPRO,
d32cad65 442 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 443 {"pentium", PROCESSOR_PENTIUM,
d32cad65 444 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 445 {"pentiumpro",PROCESSOR_PENTIUMPRO,
d32cad65 446 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 447 {"pentiumii", PROCESSOR_PENTIUMPRO,
d32cad65 448 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
9103f4f4 449 {"pentiumiii",PROCESSOR_PENTIUMPRO,
d32cad65 450 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
9103f4f4 451 {"pentium4", PROCESSOR_PENTIUM4,
d32cad65 452 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 453 |CpuMMX2|CpuSSE|CpuSSE2},
454 {"prescott", PROCESSOR_NOCONA,
d32cad65 455 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 456 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
457 {"nocona", PROCESSOR_NOCONA,
d32cad65 458 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 459 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 460 {"yonah", PROCESSOR_CORE,
d32cad65 461 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 462 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 463 {"core", PROCESSOR_CORE,
d32cad65 464 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
ef05d495
L		 465 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
466 {"merom", PROCESSOR_CORE2,
467 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
468 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
469 {"core2", PROCESSOR_CORE2,
470 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
471 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4 472 {"k6", PROCESSOR_K6,
d32cad65 473 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
9103f4f4 474 {"k6_2", PROCESSOR_K6,
d32cad65 475 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
9103f4f4 476 {"athlon", PROCESSOR_ATHLON,
d32cad65 477 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 478 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
479 {"sledgehammer", PROCESSOR_K8,
d32cad65 480 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 481 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
482 {"opteron", PROCESSOR_K8,
d32cad65 483 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 484 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
485 {"k8", PROCESSOR_K8,
d32cad65 486 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4 487 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
050dfa73 488 {"amdfam10", PROCESSOR_AMDFAM10,
d32cad65
L		 489 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
490 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
491 |CpuABM},
9103f4f4
L		 492 {".mmx", PROCESSOR_UNKNOWN,
493 CpuMMX},
494 {".sse", PROCESSOR_UNKNOWN,
495 CpuMMX|CpuMMX2|CpuSSE},
496 {".sse2", PROCESSOR_UNKNOWN,
497 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
498 {".sse3", PROCESSOR_UNKNOWN,
499 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495
L		 500 {".ssse3", PROCESSOR_UNKNOWN,
501 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4
L		 502 {".3dnow", PROCESSOR_UNKNOWN,
503 CpuMMX|Cpu3dnow},
504 {".3dnowa", PROCESSOR_UNKNOWN,
505 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
506 {".padlock", PROCESSOR_UNKNOWN,
507 CpuPadLock},
508 {".pacifica", PROCESSOR_UNKNOWN,
509 CpuSVME},
510 {".svme", PROCESSOR_UNKNOWN,
050dfa73
MM		 511 CpuSVME},
512 {".sse4a", PROCESSOR_UNKNOWN,
513 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
514 {".abm", PROCESSOR_UNKNOWN,
515 CpuABM}
e413e4e9
AM		 516};
517
29b0f896
AM		 518const pseudo_typeS md_pseudo_table[] =
519{
520#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
521 {"align", s_align_bytes, 0},
522#else
523 {"align", s_align_ptwo, 0},
524#endif
525 {"arch", set_cpu_arch, 0},
526#ifndef I386COFF
527 {"bss", s_bss, 0},
528#endif
529 {"ffloat", float_cons, 'f'},
530 {"dfloat", float_cons, 'd'},
531 {"tfloat", float_cons, 'x'},
532 {"value", cons, 2},
d182319b 533 {"slong", signed_cons, 4},
29b0f896
AM		 534 {"noopt", s_ignore, 0},
535 {"optim", s_ignore, 0},
536 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
537 {"code16", set_code_flag, CODE_16BIT},
538 {"code32", set_code_flag, CODE_32BIT},
539 {"code64", set_code_flag, CODE_64BIT},
540 {"intel_syntax", set_intel_syntax, 1},
541 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 542#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
543 {"largecomm", handle_large_common, 0},
07a53e5c 544#else
e3bb37b5 545 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 546 {"loc", dwarf2_directive_loc, 0},
547 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 548#endif
6482c264
NC		 549#ifdef TE_PE
550 {"secrel32", pe_directive_secrel, 0},
551#endif
29b0f896
AM		 552 {0, 0, 0}
553};
554
555/* For interface with expression (). */
556extern char *input_line_pointer;
557
558/* Hash table for instruction mnemonic lookup. */
559static struct hash_control *op_hash;
560
561/* Hash table for register lookup. */
562static struct hash_control *reg_hash;
563\f
252b5132 564void
e3bb37b5 565i386_align_code (fragS *fragP, int count)
252b5132 566{
ce8a8b2f
AM		 567 /* Various efficient no-op patterns for aligning code labels.
568 Note: Don't try to assemble the instructions in the comments.
569 0L and 0w are not legal. */
252b5132
RH		 570 static const char f32_1[] =
571 {0x90}; /* nop */
572 static const char f32_2[] =
ccc9c027 573 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 574 static const char f32_3[] =
575 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
576 static const char f32_4[] =
577 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
578 static const char f32_5[] =
579 {0x90, /* nop */
580 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
581 static const char f32_6[] =
582 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
583 static const char f32_7[] =
584 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
585 static const char f32_8[] =
586 {0x90, /* nop */
587 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
588 static const char f32_9[] =
589 {0x89,0xf6, /* movl %esi,%esi */
590 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
591 static const char f32_10[] =
592 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
593 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
594 static const char f32_11[] =
595 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
596 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
597 static const char f32_12[] =
598 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
599 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
600 static const char f32_13[] =
601 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
602 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
603 static const char f32_14[] =
604 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
605 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
606 static const char f32_15[] =
607 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
608 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 609 static const char f16_3[] =
610 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 611 static const char f16_4[] =
612 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
613 static const char f16_5[] =
614 {0x90, /* nop */
615 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
616 static const char f16_6[] =
617 {0x89,0xf6, /* mov %si,%si */
618 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
619 static const char f16_7[] =
620 {0x8d,0x74,0x00, /* lea 0(%si),%si */
621 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
622 static const char f16_8[] =
623 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
624 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
625 static const char *const f32_patt[] = {
626 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
627 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
628 };
629 static const char *const f16_patt[] = {
c3332e24 630 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 631 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
632 };
ccc9c027
L		 633 /* nopl (%[re]ax) */
634 static const char alt_3[] =
635 {0x0f,0x1f,0x00};
636 /* nopl 0(%[re]ax) */
637 static const char alt_4[] =
638 {0x0f,0x1f,0x40,0x00};
639 /* nopl 0(%[re]ax,%[re]ax,1) */
640 static const char alt_5[] =
641 {0x0f,0x1f,0x44,0x00,0x00};
642 /* nopw 0(%[re]ax,%[re]ax,1) */
643 static const char alt_6[] =
644 {0x66,0x0f,0x1f,0x44,0x00,0x00};
645 /* nopl 0L(%[re]ax) */
646 static const char alt_7[] =
647 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
648 /* nopl 0L(%[re]ax,%[re]ax,1) */
649 static const char alt_8[] =
650 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
651 /* nopw 0L(%[re]ax,%[re]ax,1) */
652 static const char alt_9[] =
653 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
654 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
655 static const char alt_10[] =
656 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
657 /* data16
658 nopw %cs:0L(%[re]ax,%[re]ax,1) */
659 static const char alt_long_11[] =
660 {0x66,
661 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
662 /* data16
663 data16
664 nopw %cs:0L(%[re]ax,%[re]ax,1) */
665 static const char alt_long_12[] =
666 {0x66,
667 0x66,
668 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
669 /* data16
670 data16
671 data16
672 nopw %cs:0L(%[re]ax,%[re]ax,1) */
673 static const char alt_long_13[] =
674 {0x66,
675 0x66,
676 0x66,
677 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
678 /* data16
679 data16
680 data16
681 data16
682 nopw %cs:0L(%[re]ax,%[re]ax,1) */
683 static const char alt_long_14[] =
684 {0x66,
685 0x66,
686 0x66,
687 0x66,
688 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
689 /* data16
690 data16
691 data16
692 data16
693 data16
694 nopw %cs:0L(%[re]ax,%[re]ax,1) */
695 static const char alt_long_15[] =
696 {0x66,
697 0x66,
698 0x66,
699 0x66,
700 0x66,
701 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
702 /* nopl 0(%[re]ax,%[re]ax,1)
703 nopw 0(%[re]ax,%[re]ax,1) */
704 static const char alt_short_11[] =
705 {0x0f,0x1f,0x44,0x00,0x00,
706 0x66,0x0f,0x1f,0x44,0x00,0x00};
707 /* nopw 0(%[re]ax,%[re]ax,1)
708 nopw 0(%[re]ax,%[re]ax,1) */
709 static const char alt_short_12[] =
710 {0x66,0x0f,0x1f,0x44,0x00,0x00,
711 0x66,0x0f,0x1f,0x44,0x00,0x00};
712 /* nopw 0(%[re]ax,%[re]ax,1)
713 nopl 0L(%[re]ax) */
714 static const char alt_short_13[] =
715 {0x66,0x0f,0x1f,0x44,0x00,0x00,
716 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
717 /* nopl 0L(%[re]ax)
718 nopl 0L(%[re]ax) */
719 static const char alt_short_14[] =
720 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
721 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
722 /* nopl 0L(%[re]ax)
723 nopl 0L(%[re]ax,%[re]ax,1) */
724 static const char alt_short_15[] =
725 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
726 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
727 static const char *const alt_short_patt[] = {
728 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
729 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
730 alt_short_14, alt_short_15
731 };
732 static const char *const alt_long_patt[] = {
733 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
734 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
735 alt_long_14, alt_long_15
736 };
252b5132 737
33fef721
JH		 738 if (count <= 0 || count > 15)
739 return;
3e73aa7c 740
ccc9c027
L		 741 /* We need to decide which NOP sequence to use for 32bit and
742 64bit. When -mtune= is used:
743
744 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
745 f32_patt will be used.
050dfa73 746 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with 0x66 prefix will be used.
ef05d495 747 3. For PROCESSOR_CORE2, alt_long_patt will be used.
ccc9c027 748 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
ef05d495 749 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
ccc9c027
L		 750 and PROCESSOR_GENERIC64, alt_short_patt will be used.
751
752 When -mtune= isn't used, alt_short_patt will be used if
753 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
754
755 When -march= or .arch is used, we can't use anything beyond
756 cpu_arch_isa_flags. */
757
758 if (flag_code == CODE_16BIT)
759 {
760 memcpy (fragP->fr_literal + fragP->fr_fix,
761 f16_patt[count - 1], count);
762 if (count > 8)
763 /* Adjust jump offset. */
764 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
765 }
766 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
252b5132 767 {
33fef721
JH		 768 int i;
769 int nnops = (count + 3) / 4;
770 int len = count / nnops;
771 int remains = count - nnops * len;
772 int pos = 0;
773
ccc9c027
L		 774 /* The recommended way to pad 64bit code is to use NOPs preceded
775 by maximally four 0x66 prefixes. Balance the size of nops. */
33fef721 776 for (i = 0; i < remains; i++)
252b5132 777 {
33fef721
JH		 778 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
779 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
780 pos += len + 1;
781 }
782 for (; i < nnops; i++)
783 {
784 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
785 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
786 pos += len;
252b5132 787 }
252b5132 788 }
33fef721 789 else
ccc9c027
L		 790 {
791 const char *const *patt = NULL;
792
793 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
794 {
795 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
796 switch (cpu_arch_tune)
797 {
798 case PROCESSOR_UNKNOWN:
799 /* We use cpu_arch_isa_flags to check if we SHOULD
800 optimize for Cpu686. */
801 if ((cpu_arch_isa_flags & Cpu686) != 0)
802 patt = alt_short_patt;
803 else
804 patt = f32_patt;
805 break;
ef05d495 806 case PROCESSOR_CORE2:
ccc9c027
L		 807 patt = alt_long_patt;
808 break;
809 case PROCESSOR_PENTIUMPRO:
810 case PROCESSOR_PENTIUM4:
811 case PROCESSOR_NOCONA:
ef05d495 812 case PROCESSOR_CORE:
ccc9c027
L		 813 case PROCESSOR_K6:
814 case PROCESSOR_ATHLON:
815 case PROCESSOR_K8:
816 case PROCESSOR_GENERIC64:
050dfa73 817 case PROCESSOR_AMDFAM10:
ccc9c027
L		 818 patt = alt_short_patt;
819 break;
820 case PROCESSOR_I486:
821 case PROCESSOR_PENTIUM:
822 case PROCESSOR_GENERIC32:
823 patt = f32_patt;
824 break;
825 }
826 }
827 else
828 {
829 switch (cpu_arch_tune)
830 {
831 case PROCESSOR_UNKNOWN:
832 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
833 PROCESSOR_UNKNOWN. */
834 abort ();
835 break;
836
837 case PROCESSOR_I486:
838 case PROCESSOR_PENTIUM:
839 case PROCESSOR_PENTIUMPRO:
840 case PROCESSOR_PENTIUM4:
841 case PROCESSOR_NOCONA:
ef05d495 842 case PROCESSOR_CORE:
ccc9c027
L		 843 case PROCESSOR_K6:
844 case PROCESSOR_ATHLON:
845 case PROCESSOR_K8:
050dfa73 846 case PROCESSOR_AMDFAM10:
ccc9c027
L		 847 case PROCESSOR_GENERIC32:
848 /* We use cpu_arch_isa_flags to check if we CAN optimize
849 for Cpu686. */
850 if ((cpu_arch_isa_flags & Cpu686) != 0)
851 patt = alt_short_patt;
852 else
853 patt = f32_patt;
854 break;
ef05d495 855 case PROCESSOR_CORE2:
ccc9c027
L		 856 if ((cpu_arch_isa_flags & Cpu686) != 0)
857 patt = alt_long_patt;
858 else
859 patt = f32_patt;
860 break;
861 case PROCESSOR_GENERIC64:
862 patt = alt_short_patt;
863 break;
864 }
865 }
866
33fef721 867 memcpy (fragP->fr_literal + fragP->fr_fix,
ccc9c027
L		 868 patt[count - 1], count);
869 }
33fef721 870 fragP->fr_var = count;
252b5132
RH		 871}
872
252b5132 873static INLINE unsigned int
e3bb37b5 874mode_from_disp_size (unsigned int t)
252b5132 875{
3e73aa7c 876 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 877}
878
879static INLINE int
e3bb37b5 880fits_in_signed_byte (offsetT num)
252b5132
RH		 881{
882 return (num >= -128) && (num <= 127);
47926f60 883}
252b5132
RH		 884
885static INLINE int
e3bb37b5 886fits_in_unsigned_byte (offsetT num)
252b5132
RH		 887{
888 return (num & 0xff) == num;
47926f60 889}
252b5132
RH		 890
891static INLINE int
e3bb37b5 892fits_in_unsigned_word (offsetT num)
252b5132
RH		 893{
894 return (num & 0xffff) == num;
47926f60 895}
252b5132
RH		 896
897static INLINE int
e3bb37b5 898fits_in_signed_word (offsetT num)
252b5132
RH		 899{
900 return (-32768 <= num) && (num <= 32767);
47926f60 901}
2a962e6d 902
3e73aa7c 903static INLINE int
e3bb37b5 904fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 905{
906#ifndef BFD64
907 return 1;
908#else
909 return (!(((offsetT) -1 << 31) & num)
910 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
911#endif
912} /* fits_in_signed_long() */
2a962e6d 913
3e73aa7c 914static INLINE int
e3bb37b5 915fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 916{
917#ifndef BFD64
918 return 1;
919#else
920 return (num & (((offsetT) 2 << 31) - 1)) == num;
921#endif
922} /* fits_in_unsigned_long() */
252b5132 923
1509aa9a 924static unsigned int
e3bb37b5 925smallest_imm_type (offsetT num)
252b5132 926{
d32cad65 927 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 928 {
929 /* This code is disabled on the 486 because all the Imm1 forms
930 in the opcode table are slower on the i486. They're the
931 versions with the implicitly specified single-position
932 displacement, which has another syntax if you really want to
933 use that form. */
934 if (num == 1)
3e73aa7c 935 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 936 }
252b5132 937 return (fits_in_signed_byte (num)
3e73aa7c 938 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 939 : fits_in_unsigned_byte (num)
3e73aa7c 940 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 941 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 942 ? (Imm16 | Imm32 | Imm32S | Imm64)
943 : fits_in_signed_long (num)
944 ? (Imm32 | Imm32S | Imm64)
945 : fits_in_unsigned_long (num)
946 ? (Imm32 | Imm64)
947 : Imm64);
47926f60 948}
252b5132 949
847f7ad4 950static offsetT
e3bb37b5 951offset_in_range (offsetT val, int size)
847f7ad4 952{
508866be 953 addressT mask;
ba2adb93 954
847f7ad4
AM		 955 switch (size)
956 {
508866be
L		 957 case 1: mask = ((addressT) 1 << 8) - 1; break;
958 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 959 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 960#ifdef BFD64
961 case 8: mask = ((addressT) 2 << 63) - 1; break;
962#endif
47926f60 963 default: abort ();
847f7ad4
AM		 964 }
965
ba2adb93 966 /* If BFD64, sign extend val. */
3e73aa7c
JH		 967 if (!use_rela_relocations)
968 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
969 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 970
47926f60 971 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 972 {
973 char buf1[40], buf2[40];
974
975 sprint_value (buf1, val);
976 sprint_value (buf2, val & mask);
977 as_warn (_("%s shortened to %s"), buf1, buf2);
978 }
979 return val & mask;
980}
981
252b5132
RH		 982/* Returns 0 if attempting to add a prefix where one from the same
983 class already exists, 1 if non rep/repne added, 2 if rep/repne
984 added. */
985static int
e3bb37b5 986add_prefix (unsigned int prefix)
252b5132
RH		 987{
988 int ret = 1;
b1905489 989 unsigned int q;
252b5132 990
29b0f896
AM		 991 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
992 && flag_code == CODE_64BIT)
b1905489
JB		 993 {
994 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
995 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
996 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
997 ret = 0;
998 q = REX_PREFIX;
999 }
3e73aa7c 1000 else
b1905489
JB		 1001 {
1002 switch (prefix)
1003 {
1004 default:
1005 abort ();
1006
1007 case CS_PREFIX_OPCODE:
1008 case DS_PREFIX_OPCODE:
1009 case ES_PREFIX_OPCODE:
1010 case FS_PREFIX_OPCODE:
1011 case GS_PREFIX_OPCODE:
1012 case SS_PREFIX_OPCODE:
1013 q = SEG_PREFIX;
1014 break;
1015
1016 case REPNE_PREFIX_OPCODE:
1017 case REPE_PREFIX_OPCODE:
1018 ret = 2;
1019 /* fall thru */
1020 case LOCK_PREFIX_OPCODE:
1021 q = LOCKREP_PREFIX;
1022 break;
1023
1024 case FWAIT_OPCODE:
1025 q = WAIT_PREFIX;
1026 break;
1027
1028 case ADDR_PREFIX_OPCODE:
1029 q = ADDR_PREFIX;
1030 break;
1031
1032 case DATA_PREFIX_OPCODE:
1033 q = DATA_PREFIX;
1034 break;
1035 }
1036 if (i.prefix[q] != 0)
1037 ret = 0;
1038 }
252b5132 1039
b1905489 1040 if (ret)
252b5132 1041 {
b1905489
JB		 1042 if (!i.prefix[q])
1043 ++i.prefixes;
1044 i.prefix[q] |= prefix;
252b5132 1045 }
b1905489
JB		 1046 else
1047 as_bad (_("same type of prefix used twice"));
252b5132 1048
252b5132
RH		 1049 return ret;
1050}
1051
1052static void
e3bb37b5 1053set_code_flag (int value)
eecb386c 1054{
3e73aa7c
JH		 1055 flag_code = value;
1056 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1057 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1058 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1059 {
1060 as_bad (_("64bit mode not supported on this CPU."));
1061 }
1062 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1063 {
1064 as_bad (_("32bit mode not supported on this CPU."));
1065 }
eecb386c
AM		 1066 stackop_size = '\0';
1067}
1068
1069static void
e3bb37b5 1070set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1071{
3e73aa7c
JH		 1072 flag_code = new_code_flag;
1073 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1074 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 1075 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1076}
1077
1078static void
e3bb37b5 1079set_intel_syntax (int syntax_flag)
252b5132
RH		 1080{
1081 /* Find out if register prefixing is specified. */
1082 int ask_naked_reg = 0;
1083
1084 SKIP_WHITESPACE ();
29b0f896 1085 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1086 {
1087 char *string = input_line_pointer;
1088 int e = get_symbol_end ();
1089
47926f60 1090 if (strcmp (string, "prefix") == 0)
252b5132 1091 ask_naked_reg = 1;
47926f60 1092 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1093 ask_naked_reg = -1;
1094 else
d0b47220 1095 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1096 *input_line_pointer = e;
1097 }
1098 demand_empty_rest_of_line ();
c3332e24 1099
252b5132
RH		 1100 intel_syntax = syntax_flag;
1101
1102 if (ask_naked_reg == 0)
f86103b7
AM		 1103 allow_naked_reg = (intel_syntax
1104 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1105 else
1106 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1107
e4a3b5a4 1108 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1109 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1110 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1111}
1112
e413e4e9 1113static void
e3bb37b5 1114set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1115{
47926f60 1116 SKIP_WHITESPACE ();
e413e4e9 1117
29b0f896 1118 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1119 {
1120 char *string = input_line_pointer;
1121 int e = get_symbol_end ();
9103f4f4 1122 unsigned int i;
e413e4e9 1123
9103f4f4 1124 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1125 {
1126 if (strcmp (string, cpu_arch[i].name) == 0)
1127 {
5c6af06e
JB		 1128 if (*string != '.')
1129 {
1130 cpu_arch_name = cpu_arch[i].name;
1131 cpu_sub_arch_name = NULL;
1132 cpu_arch_flags = (cpu_arch[i].flags
1133 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
ccc9c027 1134 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1135 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1136 if (!cpu_arch_tune_set)
1137 {
1138 cpu_arch_tune = cpu_arch_isa;
1139 cpu_arch_tune_flags = cpu_arch_isa_flags;
1140 }
5c6af06e
JB		 1141 break;
1142 }
1143 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1144 {
1145 cpu_sub_arch_name = cpu_arch[i].name;
1146 cpu_arch_flags |= cpu_arch[i].flags;
1147 }
1148 *input_line_pointer = e;
1149 demand_empty_rest_of_line ();
1150 return;
e413e4e9
AM		 1151 }
1152 }
9103f4f4 1153 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1154 as_bad (_("no such architecture: `%s'"), string);
1155
1156 *input_line_pointer = e;
1157 }
1158 else
1159 as_bad (_("missing cpu architecture"));
1160
fddf5b5b
AM		 1161 no_cond_jump_promotion = 0;
1162 if (*input_line_pointer == ','
29b0f896 1163 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1164 {
1165 char *string = ++input_line_pointer;
1166 int e = get_symbol_end ();
1167
1168 if (strcmp (string, "nojumps") == 0)
1169 no_cond_jump_promotion = 1;
1170 else if (strcmp (string, "jumps") == 0)
1171 ;
1172 else
1173 as_bad (_("no such architecture modifier: `%s'"), string);
1174
1175 *input_line_pointer = e;
1176 }
1177
e413e4e9
AM		 1178 demand_empty_rest_of_line ();
1179}
1180
b9d79e03
JH		 1181unsigned long
1182i386_mach ()
1183{
1184 if (!strcmp (default_arch, "x86_64"))
1185 return bfd_mach_x86_64;
1186 else if (!strcmp (default_arch, "i386"))
1187 return bfd_mach_i386_i386;
1188 else
1189 as_fatal (_("Unknown architecture"));
1190}
b9d79e03 1191\f
252b5132
RH		 1192void
1193md_begin ()
1194{
1195 const char *hash_err;
1196
47926f60 1197 /* Initialize op_hash hash table. */
252b5132
RH		 1198 op_hash = hash_new ();
1199
1200 {
29b0f896
AM		 1201 const template *optab;
1202 templates *core_optab;
252b5132 1203
47926f60
KH		 1204 /* Setup for loop. */
1205 optab = i386_optab;
252b5132
RH		 1206 core_optab = (templates *) xmalloc (sizeof (templates));
1207 core_optab->start = optab;
1208
1209 while (1)
1210 {
1211 ++optab;
1212 if (optab->name == NULL
1213 || strcmp (optab->name, (optab - 1)->name) != 0)
1214 {
1215 /* different name --> ship out current template list;
47926f60 1216 add to hash table; & begin anew. */
252b5132
RH		 1217 core_optab->end = optab;
1218 hash_err = hash_insert (op_hash,
1219 (optab - 1)->name,
1220 (PTR) core_optab);
1221 if (hash_err)
1222 {
252b5132
RH		 1223 as_fatal (_("Internal Error: Can't hash %s: %s"),
1224 (optab - 1)->name,
1225 hash_err);
1226 }
1227 if (optab->name == NULL)
1228 break;
1229 core_optab = (templates *) xmalloc (sizeof (templates));
1230 core_optab->start = optab;
1231 }
1232 }
1233 }
1234
47926f60 1235 /* Initialize reg_hash hash table. */
252b5132
RH		 1236 reg_hash = hash_new ();
1237 {
29b0f896 1238 const reg_entry *regtab;
252b5132
RH		 1239
1240 for (regtab = i386_regtab;
1241 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
1242 regtab++)
1243 {
1244 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1245 if (hash_err)
3e73aa7c
JH		 1246 as_fatal (_("Internal Error: Can't hash %s: %s"),
1247 regtab->reg_name,
1248 hash_err);
252b5132
RH		 1249 }
1250 }
1251
47926f60 1252 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1253 {
29b0f896
AM		 1254 int c;
1255 char *p;
252b5132
RH		 1256
1257 for (c = 0; c < 256; c++)
1258 {
3882b010 1259 if (ISDIGIT (c))
252b5132
RH		 1260 {
1261 digit_chars[c] = c;
1262 mnemonic_chars[c] = c;
1263 register_chars[c] = c;
1264 operand_chars[c] = c;
1265 }
3882b010 1266 else if (ISLOWER (c))
252b5132
RH		 1267 {
1268 mnemonic_chars[c] = c;
1269 register_chars[c] = c;
1270 operand_chars[c] = c;
1271 }
3882b010 1272 else if (ISUPPER (c))
252b5132 1273 {
3882b010 1274 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1275 register_chars[c] = mnemonic_chars[c];
1276 operand_chars[c] = c;
1277 }
1278
3882b010 1279 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1280 identifier_chars[c] = c;
1281 else if (c >= 128)
1282 {
1283 identifier_chars[c] = c;
1284 operand_chars[c] = c;
1285 }
1286 }
1287
1288#ifdef LEX_AT
1289 identifier_chars['@'] = '@';
32137342
NC		 1290#endif
1291#ifdef LEX_QM
1292 identifier_chars['?'] = '?';
1293 operand_chars['?'] = '?';
252b5132 1294#endif
252b5132 1295 digit_chars['-'] = '-';
791fe849 1296 mnemonic_chars['-'] = '-';
252b5132
RH		 1297 identifier_chars['_'] = '_';
1298 identifier_chars['.'] = '.';
1299
1300 for (p = operand_special_chars; *p != '\0'; p++)
1301 operand_chars[(unsigned char) *p] = *p;
1302 }
1303
1304#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1305 if (IS_ELF)
252b5132
RH		 1306 {
1307 record_alignment (text_section, 2);
1308 record_alignment (data_section, 2);
1309 record_alignment (bss_section, 2);
1310 }
1311#endif
a4447b93
RH		 1312
1313 if (flag_code == CODE_64BIT)
1314 {
1315 x86_dwarf2_return_column = 16;
1316 x86_cie_data_alignment = -8;
1317 }
1318 else
1319 {
1320 x86_dwarf2_return_column = 8;
1321 x86_cie_data_alignment = -4;
1322 }
252b5132
RH		 1323}
1324
1325void
e3bb37b5 1326i386_print_statistics (FILE *file)
252b5132
RH		 1327{
1328 hash_print_statistics (file, "i386 opcode", op_hash);
1329 hash_print_statistics (file, "i386 register", reg_hash);
1330}
1331\f
252b5132
RH		 1332#ifdef DEBUG386
1333
ce8a8b2f 1334/* Debugging routines for md_assemble. */
e3bb37b5
L		 1335static void pte (template *);
1336static void pt (unsigned int);
1337static void pe (expressionS *);
1338static void ps (symbolS *);
252b5132
RH		 1339
1340static void
e3bb37b5 1341pi (char *line, i386_insn *x)
252b5132 1342{
09f131f2 1343 unsigned int i;
252b5132
RH		 1344
1345 fprintf (stdout, "%s: template ", line);
1346 pte (&x->tm);
09f131f2
JH		 1347 fprintf (stdout, " address: base %s index %s scale %x\n",
1348 x->base_reg ? x->base_reg->reg_name : "none",
1349 x->index_reg ? x->index_reg->reg_name : "none",
1350 x->log2_scale_factor);
1351 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1352 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1353 fprintf (stdout, " sib: base %x index %x scale %x\n",
1354 x->sib.base, x->sib.index, x->sib.scale);
1355 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1356 (x->rex & REX_MODE64) != 0,
1357 (x->rex & REX_EXTX) != 0,
1358 (x->rex & REX_EXTY) != 0,
1359 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1360 for (i = 0; i < x->operands; i++)
1361 {
1362 fprintf (stdout, " #%d: ", i + 1);
1363 pt (x->types[i]);
1364 fprintf (stdout, "\n");
1365 if (x->types[i]
3f4438ab 1366 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1367 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1368 if (x->types[i] & Imm)
520dc8e8 1369 pe (x->op[i].imms);
252b5132 1370 if (x->types[i] & Disp)
520dc8e8 1371 pe (x->op[i].disps);
252b5132
RH		 1372 }
1373}
1374
1375static void
e3bb37b5 1376pte (template *t)
252b5132 1377{
09f131f2 1378 unsigned int i;
252b5132 1379 fprintf (stdout, " %d operands ", t->operands);
47926f60 1380 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1381 if (t->extension_opcode != None)
1382 fprintf (stdout, "ext %x ", t->extension_opcode);
1383 if (t->opcode_modifier & D)
1384 fprintf (stdout, "D");
1385 if (t->opcode_modifier & W)
1386 fprintf (stdout, "W");
1387 fprintf (stdout, "\n");
1388 for (i = 0; i < t->operands; i++)
1389 {
1390 fprintf (stdout, " #%d type ", i + 1);
1391 pt (t->operand_types[i]);
1392 fprintf (stdout, "\n");
1393 }
1394}
1395
1396static void
e3bb37b5 1397pe (expressionS *e)
252b5132 1398{
24eab124 1399 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1400 fprintf (stdout, " add_number %ld (%lx)\n",
1401 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1402 if (e->X_add_symbol)
1403 {
1404 fprintf (stdout, " add_symbol ");
1405 ps (e->X_add_symbol);
1406 fprintf (stdout, "\n");
1407 }
1408 if (e->X_op_symbol)
1409 {
1410 fprintf (stdout, " op_symbol ");
1411 ps (e->X_op_symbol);
1412 fprintf (stdout, "\n");
1413 }
1414}
1415
1416static void
e3bb37b5 1417ps (symbolS *s)
252b5132
RH		 1418{
1419 fprintf (stdout, "%s type %s%s",
1420 S_GET_NAME (s),
1421 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1422 segment_name (S_GET_SEGMENT (s)));
1423}
1424
7b81dfbb 1425static struct type_name
252b5132
RH		 1426 {
1427 unsigned int mask;
1428 char *tname;
1429 }
7b81dfbb 1430const type_names[] =
252b5132
RH		 1431{
1432 { Reg8, "r8" },
1433 { Reg16, "r16" },
1434 { Reg32, "r32" },
09f131f2 1435 { Reg64, "r64" },
252b5132
RH		 1436 { Imm8, "i8" },
1437 { Imm8S, "i8s" },
1438 { Imm16, "i16" },
1439 { Imm32, "i32" },
09f131f2
JH		 1440 { Imm32S, "i32s" },
1441 { Imm64, "i64" },
252b5132
RH		 1442 { Imm1, "i1" },
1443 { BaseIndex, "BaseIndex" },
1444 { Disp8, "d8" },
1445 { Disp16, "d16" },
1446 { Disp32, "d32" },
09f131f2
JH		 1447 { Disp32S, "d32s" },
1448 { Disp64, "d64" },
252b5132
RH		 1449 { InOutPortReg, "InOutPortReg" },
1450 { ShiftCount, "ShiftCount" },
1451 { Control, "control reg" },
1452 { Test, "test reg" },
1453 { Debug, "debug reg" },
1454 { FloatReg, "FReg" },
1455 { FloatAcc, "FAcc" },
1456 { SReg2, "SReg2" },
1457 { SReg3, "SReg3" },
1458 { Acc, "Acc" },
1459 { JumpAbsolute, "Jump Absolute" },
1460 { RegMMX, "rMMX" },
3f4438ab 1461 { RegXMM, "rXMM" },
252b5132
RH		 1462 { EsSeg, "es" },
1463 { 0, "" }
1464};
1465
1466static void
1467pt (t)
1468 unsigned int t;
1469{
29b0f896 1470 const struct type_name *ty;
252b5132 1471
09f131f2
JH		 1472 for (ty = type_names; ty->mask; ty++)
1473 if (t & ty->mask)
1474 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1475 fflush (stdout);
1476}
1477
1478#endif /* DEBUG386 */
1479\f
252b5132 1480static bfd_reloc_code_real_type
3956db08 1481reloc (unsigned int size,
64e74474
AM		 1482 int pcrel,
1483 int sign,
1484 bfd_reloc_code_real_type other)
252b5132 1485{
47926f60 1486 if (other != NO_RELOC)
3956db08
JB		 1487 {
1488 reloc_howto_type *reloc;
1489
1490 if (size == 8)
1491 switch (other)
1492 {
64e74474
AM		 1493 case BFD_RELOC_X86_64_GOT32:
1494 return BFD_RELOC_X86_64_GOT64;
1495 break;
1496 case BFD_RELOC_X86_64_PLTOFF64:
1497 return BFD_RELOC_X86_64_PLTOFF64;
1498 break;
1499 case BFD_RELOC_X86_64_GOTPC32:
1500 other = BFD_RELOC_X86_64_GOTPC64;
1501 break;
1502 case BFD_RELOC_X86_64_GOTPCREL:
1503 other = BFD_RELOC_X86_64_GOTPCREL64;
1504 break;
1505 case BFD_RELOC_X86_64_TPOFF32:
1506 other = BFD_RELOC_X86_64_TPOFF64;
1507 break;
1508 case BFD_RELOC_X86_64_DTPOFF32:
1509 other = BFD_RELOC_X86_64_DTPOFF64;
1510 break;
1511 default:
1512 break;
3956db08 1513 }
e05278af
JB		 1514
1515 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1516 if (size == 4 && flag_code != CODE_64BIT)
1517 sign = -1;
1518
3956db08
JB		 1519 reloc = bfd_reloc_type_lookup (stdoutput, other);
1520 if (!reloc)
1521 as_bad (_("unknown relocation (%u)"), other);
1522 else if (size != bfd_get_reloc_size (reloc))
1523 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1524 bfd_get_reloc_size (reloc),
1525 size);
1526 else if (pcrel && !reloc->pc_relative)
1527 as_bad (_("non-pc-relative relocation for pc-relative field"));
1528 else if ((reloc->complain_on_overflow == complain_overflow_signed
1529 && !sign)
1530 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1531 && sign > 0))
3956db08
JB		 1532 as_bad (_("relocated field and relocation type differ in signedness"));
1533 else
1534 return other;
1535 return NO_RELOC;
1536 }
252b5132
RH		 1537
1538 if (pcrel)
1539 {
3e73aa7c 1540 if (!sign)
3956db08 1541 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1542 switch (size)
1543 {
1544 case 1: return BFD_RELOC_8_PCREL;
1545 case 2: return BFD_RELOC_16_PCREL;
1546 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1547 case 8: return BFD_RELOC_64_PCREL;
252b5132 1548 }
3956db08 1549 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1550 }
1551 else
1552 {
3956db08 1553 if (sign > 0)
e5cb08ac 1554 switch (size)
3e73aa7c
JH		 1555 {
1556 case 4: return BFD_RELOC_X86_64_32S;
1557 }
1558 else
1559 switch (size)
1560 {
1561 case 1: return BFD_RELOC_8;
1562 case 2: return BFD_RELOC_16;
1563 case 4: return BFD_RELOC_32;
1564 case 8: return BFD_RELOC_64;
1565 }
3956db08
JB		 1566 as_bad (_("cannot do %s %u byte relocation"),
1567 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1568 }
1569
bfb32b52 1570 abort ();
252b5132
RH		 1571 return BFD_RELOC_NONE;
1572}
1573
47926f60
KH		 1574/* Here we decide which fixups can be adjusted to make them relative to
1575 the beginning of the section instead of the symbol. Basically we need
1576 to make sure that the dynamic relocations are done correctly, so in
1577 some cases we force the original symbol to be used. */
1578
252b5132 1579int
e3bb37b5 1580tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 1581{
6d249963 1582#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1583 if (!IS_ELF)
31312f95
AM		 1584 return 1;
1585
a161fe53
AM		 1586 /* Don't adjust pc-relative references to merge sections in 64-bit
1587 mode. */
1588 if (use_rela_relocations
1589 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1590 && fixP->fx_pcrel)
252b5132 1591 return 0;
31312f95 1592
8d01d9a9
AJ		 1593 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1594 and changed later by validate_fix. */
1595 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1596 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1597 return 0;
1598
ce8a8b2f 1599 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1600 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1601 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1602 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1603 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1604 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1605 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1606 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1607 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1608 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1609 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1610 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1611 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1612 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1613 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1614 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1615 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1616 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1617 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1618 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1619 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1620 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1621 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1622 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1623 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1624 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1625 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1626 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1627 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1628 return 0;
31312f95 1629#endif
252b5132
RH		 1630 return 1;
1631}
252b5132 1632
b4cac588 1633static int
e3bb37b5 1634intel_float_operand (const char *mnemonic)
252b5132 1635{
9306ca4a
JB		 1636 /* Note that the value returned is meaningful only for opcodes with (memory)
1637 operands, hence the code here is free to improperly handle opcodes that
1638 have no operands (for better performance and smaller code). */
1639
1640 if (mnemonic[0] != 'f')
1641 return 0; /* non-math */
1642
1643 switch (mnemonic[1])
1644 {
1645 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1646 the fs segment override prefix not currently handled because no
1647 call path can make opcodes without operands get here */
1648 case 'i':
1649 return 2 /* integer op */;
1650 case 'l':
1651 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1652 return 3; /* fldcw/fldenv */
1653 break;
1654 case 'n':
1655 if (mnemonic[2] != 'o' /* fnop */)
1656 return 3; /* non-waiting control op */
1657 break;
1658 case 'r':
1659 if (mnemonic[2] == 's')
1660 return 3; /* frstor/frstpm */
1661 break;
1662 case 's':
1663 if (mnemonic[2] == 'a')
1664 return 3; /* fsave */
1665 if (mnemonic[2] == 't')
1666 {
1667 switch (mnemonic[3])
1668 {
1669 case 'c': /* fstcw */
1670 case 'd': /* fstdw */
1671 case 'e': /* fstenv */
1672 case 's': /* fsts[gw] */
1673 return 3;
1674 }
1675 }
1676 break;
1677 case 'x':
1678 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1679 return 0; /* fxsave/fxrstor are not really math ops */
1680 break;
1681 }
252b5132 1682
9306ca4a 1683 return 1;
252b5132
RH		 1684}
1685
1686/* This is the guts of the machine-dependent assembler. LINE points to a
1687 machine dependent instruction. This function is supposed to emit
1688 the frags/bytes it assembles to. */
1689
1690void
1691md_assemble (line)
1692 char *line;
1693{
252b5132 1694 int j;
252b5132
RH		 1695 char mnemonic[MAX_MNEM_SIZE];
1696
47926f60 1697 /* Initialize globals. */
252b5132
RH		 1698 memset (&i, '\0', sizeof (i));
1699 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1700 i.reloc[j] = NO_RELOC;
252b5132
RH		 1701 memset (disp_expressions, '\0', sizeof (disp_expressions));
1702 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1703 save_stack_p = save_stack;
252b5132
RH		 1704
1705 /* First parse an instruction mnemonic & call i386_operand for the operands.
1706 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1707 start of a (possibly prefixed) mnemonic. */
252b5132 1708
29b0f896
AM		 1709 line = parse_insn (line, mnemonic);
1710 if (line == NULL)
1711 return;
252b5132 1712
29b0f896
AM		 1713 line = parse_operands (line, mnemonic);
1714 if (line == NULL)
1715 return;
252b5132 1716
050dfa73
MM		 1717 /* The order of the immediates should be reversed
1718 for 2 immediates extrq and insertq instructions */
1719 if ((i.imm_operands == 2) &&
1720 ((strcmp (mnemonic, "extrq") == 0)
1721 || (strcmp (mnemonic, "insertq") == 0)))
1722 {
1723 swap_imm_operands ();
1724 /* "extrq" and insertq" are the only two instructions whose operands
1725 have to be reversed even though they have two immediate operands.
1726 */
1727 if (intel_syntax)
1728 swap_operands ();
1729 }
1730
29b0f896
AM		 1731 /* Now we've parsed the mnemonic into a set of templates, and have the
1732 operands at hand. */
1733
1734 /* All intel opcodes have reversed operands except for "bound" and
1735 "enter". We also don't reverse intersegment "jmp" and "call"
1736 instructions with 2 immediate operands so that the immediate segment
050dfa73 1737 precedes the offset, as it does when in AT&T mode. */
29b0f896
AM		 1738 if (intel_syntax && i.operands > 1
1739 && (strcmp (mnemonic, "bound") != 0)
30123838 1740 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1741 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1742 swap_operands ();
1743
1744 if (i.imm_operands)
1745 optimize_imm ();
1746
b300c311
L		 1747 /* Don't optimize displacement for movabs since it only takes 64bit
1748 displacement. */
1749 if (i.disp_operands
1750 && (flag_code != CODE_64BIT
1751 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1752 optimize_disp ();
1753
1754 /* Next, we find a template that matches the given insn,
1755 making sure the overlap of the given operands types is consistent
1756 with the template operand types. */
252b5132 1757
29b0f896
AM		 1758 if (!match_template ())
1759 return;
252b5132 1760
cd61ebfe
AM		 1761 if (intel_syntax)
1762 {
1763 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1764 if (SYSV386_COMPAT
1765 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1766 i.tm.base_opcode ^= FloatR;
1767
1768 /* Zap movzx and movsx suffix. The suffix may have been set from
1769 "word ptr" or "byte ptr" on the source operand, but we'll use
1770 the suffix later to choose the destination register. */
1771 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1772 {
1773 if (i.reg_operands < 2
1774 && !i.suffix
1775 && (~i.tm.opcode_modifier
1776 & (No_bSuf
1777 | No_wSuf
1778 | No_lSuf
1779 | No_sSuf
1780 | No_xSuf
1781 | No_qSuf)))
1782 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1783
1784 i.suffix = 0;
1785 }
cd61ebfe 1786 }
24eab124 1787
29b0f896
AM		 1788 if (i.tm.opcode_modifier & FWait)
1789 if (!add_prefix (FWAIT_OPCODE))
1790 return;
252b5132 1791
29b0f896
AM		 1792 /* Check string instruction segment overrides. */
1793 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1794 {
1795 if (!check_string ())
5dd0794d 1796 return;
29b0f896 1797 }
5dd0794d 1798
29b0f896
AM		 1799 if (!process_suffix ())
1800 return;
e413e4e9 1801
29b0f896
AM		 1802 /* Make still unresolved immediate matches conform to size of immediate
1803 given in i.suffix. */
1804 if (!finalize_imm ())
1805 return;
252b5132 1806
29b0f896
AM		 1807 if (i.types[0] & Imm1)
1808 i.imm_operands = 0; /* kludge for shift insns. */
1809 if (i.types[0] & ImplicitRegister)
1810 i.reg_operands--;
1811 if (i.types[1] & ImplicitRegister)
1812 i.reg_operands--;
1813 if (i.types[2] & ImplicitRegister)
1814 i.reg_operands--;
252b5132 1815
29b0f896
AM		 1816 if (i.tm.opcode_modifier & ImmExt)
1817 {
02fc3089
L		 1818 expressionS *exp;
1819
b7d9ef37 1820 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
ca164297 1821 {
b7d9ef37 1822 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 1823 operands with an opcode suffix which is coded in the same
1824 place as an 8-bit immediate field would be. Here we check
1825 those operands and remove them afterwards. */
1826 unsigned int x;
1827
a4622f40 1828 for (x = 0; x < i.operands; x++)
ca164297
L		 1829 if (i.op[x].regs->reg_num != x)
1830 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
64e74474 1831 i.op[x].regs->reg_name, x + 1, i.tm.name);
ca164297
L		 1832 i.operands = 0;
1833 }
1834
29b0f896
AM		 1835 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1836 opcode suffix which is coded in the same place as an 8-bit
1837 immediate field would be. Here we fake an 8-bit immediate
1838 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1839
29b0f896 1840 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1841
29b0f896
AM		 1842 exp = &im_expressions[i.imm_operands++];
1843 i.op[i.operands].imms = exp;
1844 i.types[i.operands++] = Imm8;
1845 exp->X_op = O_constant;
1846 exp->X_add_number = i.tm.extension_opcode;
1847 i.tm.extension_opcode = None;
1848 }
252b5132 1849
29b0f896
AM		 1850 /* For insns with operands there are more diddles to do to the opcode. */
1851 if (i.operands)
1852 {
1853 if (!process_operands ())
1854 return;
1855 }
1856 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1857 {
1858 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1859 as_warn (_("translating to `%sp'"), i.tm.name);
1860 }
252b5132 1861
29b0f896
AM		 1862 /* Handle conversion of 'int $3' --> special int3 insn. */
1863 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1864 {
1865 i.tm.base_opcode = INT3_OPCODE;
1866 i.imm_operands = 0;
1867 }
252b5132 1868
29b0f896
AM		 1869 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1870 && i.op[0].disps->X_op == O_constant)
1871 {
1872 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1873 the absolute address given by the constant. Since ix86 jumps and
1874 calls are pc relative, we need to generate a reloc. */
1875 i.op[0].disps->X_add_symbol = &abs_symbol;
1876 i.op[0].disps->X_op = O_symbol;
1877 }
252b5132 1878
29b0f896
AM		 1879 if ((i.tm.opcode_modifier & Rex64) != 0)
1880 i.rex |= REX_MODE64;
252b5132 1881
29b0f896
AM		 1882 /* For 8 bit registers we need an empty rex prefix. Also if the
1883 instruction already has a prefix, we need to convert old
1884 registers to new ones. */
773f551c 1885
29b0f896
AM		 1886 if (((i.types[0] & Reg8) != 0
1887 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1888 || ((i.types[1] & Reg8) != 0
1889 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1890 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1891 && i.rex != 0))
1892 {
1893 int x;
726c5dcd 1894
29b0f896
AM		 1895 i.rex |= REX_OPCODE;
1896 for (x = 0; x < 2; x++)
1897 {
1898 /* Look for 8 bit operand that uses old registers. */
1899 if ((i.types[x] & Reg8) != 0
1900 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1901 {
29b0f896
AM		 1902 /* In case it is "hi" register, give up. */
1903 if (i.op[x].regs->reg_num > 3)
0477af35 1904 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1905 i.op[x].regs->reg_name);
773f551c 1906
29b0f896
AM		 1907 /* Otherwise it is equivalent to the extended register.
1908 Since the encoding doesn't change this is merely
1909 cosmetic cleanup for debug output. */
1910
1911 i.op[x].regs = i.op[x].regs + 8;
773f551c 1912 }
29b0f896
AM		 1913 }
1914 }
773f551c 1915
29b0f896
AM		 1916 if (i.rex != 0)
1917 add_prefix (REX_OPCODE | i.rex);
1918
1919 /* We are ready to output the insn. */
1920 output_insn ();
1921}
1922
1923static char *
e3bb37b5 1924parse_insn (char *line, char *mnemonic)
29b0f896
AM		 1925{
1926 char *l = line;
1927 char *token_start = l;
1928 char *mnem_p;
5c6af06e
JB		 1929 int supported;
1930 const template *t;
29b0f896
AM		 1931
1932 /* Non-zero if we found a prefix only acceptable with string insns. */
1933 const char *expecting_string_instruction = NULL;
45288df1 1934
29b0f896
AM		 1935 while (1)
1936 {
1937 mnem_p = mnemonic;
1938 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1939 {
1940 mnem_p++;
1941 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1942 {
29b0f896
AM		 1943 as_bad (_("no such instruction: `%s'"), token_start);
1944 return NULL;
1945 }
1946 l++;
1947 }
1948 if (!is_space_char (*l)
1949 && *l != END_OF_INSN
e44823cf
JB		 1950 && (intel_syntax
1951 || (*l != PREFIX_SEPARATOR
1952 && *l != ',')))
29b0f896
AM		 1953 {
1954 as_bad (_("invalid character %s in mnemonic"),
1955 output_invalid (*l));
1956 return NULL;
1957 }
1958 if (token_start == l)
1959 {
e44823cf 1960 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1961 as_bad (_("expecting prefix; got nothing"));
1962 else
1963 as_bad (_("expecting mnemonic; got nothing"));
1964 return NULL;
1965 }
45288df1 1966
29b0f896
AM		 1967 /* Look up instruction (or prefix) via hash table. */
1968 current_templates = hash_find (op_hash, mnemonic);
47926f60 1969
29b0f896
AM		 1970 if (*l != END_OF_INSN
1971 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1972 && current_templates
1973 && (current_templates->start->opcode_modifier & IsPrefix))
1974 {
2dd88dca
JB		 1975 if (current_templates->start->cpu_flags
1976 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1977 {
1978 as_bad ((flag_code != CODE_64BIT
1979 ? _("`%s' is only supported in 64-bit mode")
1980 : _("`%s' is not supported in 64-bit mode")),
1981 current_templates->start->name);
1982 return NULL;
1983 }
29b0f896
AM		 1984 /* If we are in 16-bit mode, do not allow addr16 or data16.
1985 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1986 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1987 && flag_code != CODE_64BIT
1988 && (((current_templates->start->opcode_modifier & Size32) != 0)
1989 ^ (flag_code == CODE_16BIT)))
1990 {
1991 as_bad (_("redundant %s prefix"),
1992 current_templates->start->name);
1993 return NULL;
45288df1 1994 }
29b0f896
AM		 1995 /* Add prefix, checking for repeated prefixes. */
1996 switch (add_prefix (current_templates->start->base_opcode))
1997 {
1998 case 0:
1999 return NULL;
2000 case 2:
2001 expecting_string_instruction = current_templates->start->name;
2002 break;
2003 }
2004 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2005 token_start = ++l;
2006 }
2007 else
2008 break;
2009 }
45288df1 2010
29b0f896
AM		 2011 if (!current_templates)
2012 {
2013 /* See if we can get a match by trimming off a suffix. */
2014 switch (mnem_p[-1])
2015 {
2016 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2017 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2018 i.suffix = SHORT_MNEM_SUFFIX;
2019 else
29b0f896
AM		 2020 case BYTE_MNEM_SUFFIX:
2021 case QWORD_MNEM_SUFFIX:
2022 i.suffix = mnem_p[-1];
2023 mnem_p[-1] = '\0';
2024 current_templates = hash_find (op_hash, mnemonic);
2025 break;
2026 case SHORT_MNEM_SUFFIX:
2027 case LONG_MNEM_SUFFIX:
2028 if (!intel_syntax)
2029 {
2030 i.suffix = mnem_p[-1];
2031 mnem_p[-1] = '\0';
2032 current_templates = hash_find (op_hash, mnemonic);
2033 }
2034 break;
252b5132 2035
29b0f896
AM		 2036 /* Intel Syntax. */
2037 case 'd':
2038 if (intel_syntax)
2039 {
9306ca4a 2040 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2041 i.suffix = SHORT_MNEM_SUFFIX;
2042 else
2043 i.suffix = LONG_MNEM_SUFFIX;
2044 mnem_p[-1] = '\0';
2045 current_templates = hash_find (op_hash, mnemonic);
2046 }
2047 break;
2048 }
2049 if (!current_templates)
2050 {
2051 as_bad (_("no such instruction: `%s'"), token_start);
2052 return NULL;
2053 }
2054 }
252b5132 2055
29b0f896
AM		 2056 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2057 {
2058 /* Check for a branch hint. We allow ",pt" and ",pn" for
2059 predict taken and predict not taken respectively.
2060 I'm not sure that branch hints actually do anything on loop
2061 and jcxz insns (JumpByte) for current Pentium4 chips. They
2062 may work in the future and it doesn't hurt to accept them
2063 now. */
2064 if (l[0] == ',' && l[1] == 'p')
2065 {
2066 if (l[2] == 't')
2067 {
2068 if (!add_prefix (DS_PREFIX_OPCODE))
2069 return NULL;
2070 l += 3;
2071 }
2072 else if (l[2] == 'n')
2073 {
2074 if (!add_prefix (CS_PREFIX_OPCODE))
2075 return NULL;
2076 l += 3;
2077 }
2078 }
2079 }
2080 /* Any other comma loses. */
2081 if (*l == ',')
2082 {
2083 as_bad (_("invalid character %s in mnemonic"),
2084 output_invalid (*l));
2085 return NULL;
2086 }
252b5132 2087
29b0f896 2088 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2089 supported = 0;
2090 for (t = current_templates->start; t < current_templates->end; ++t)
2091 {
2092 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2093 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 2094 supported |= 1;
5c6af06e 2095 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 2096 supported |= 2;
5c6af06e
JB		 2097 }
2098 if (!(supported & 2))
2099 {
2100 as_bad (flag_code == CODE_64BIT
2101 ? _("`%s' is not supported in 64-bit mode")
2102 : _("`%s' is only supported in 64-bit mode"),
2103 current_templates->start->name);
2104 return NULL;
2105 }
2106 if (!(supported & 1))
29b0f896 2107 {
5c6af06e
JB		 2108 as_warn (_("`%s' is not supported on `%s%s'"),
2109 current_templates->start->name,
2110 cpu_arch_name,
2111 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 2112 }
2113 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2114 {
2115 as_warn (_("use .code16 to ensure correct addressing mode"));
2116 }
252b5132 2117
29b0f896 2118 /* Check for rep/repne without a string instruction. */
f41bbced 2119 if (expecting_string_instruction)
29b0f896 2120 {
f41bbced
JB		 2121 static templates override;
2122
2123 for (t = current_templates->start; t < current_templates->end; ++t)
2124 if (t->opcode_modifier & IsString)
2125 break;
2126 if (t >= current_templates->end)
2127 {
2128 as_bad (_("expecting string instruction after `%s'"),
64e74474 2129 expecting_string_instruction);
f41bbced
JB		 2130 return NULL;
2131 }
2132 for (override.start = t; t < current_templates->end; ++t)
2133 if (!(t->opcode_modifier & IsString))
2134 break;
2135 override.end = t;
2136 current_templates = &override;
29b0f896 2137 }
252b5132 2138
29b0f896
AM		 2139 return l;
2140}
252b5132 2141
29b0f896 2142static char *
e3bb37b5 2143parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2144{
2145 char *token_start;
3138f287 2146
29b0f896
AM		 2147 /* 1 if operand is pending after ','. */
2148 unsigned int expecting_operand = 0;
252b5132 2149
29b0f896
AM		 2150 /* Non-zero if operand parens not balanced. */
2151 unsigned int paren_not_balanced;
2152
2153 while (*l != END_OF_INSN)
2154 {
2155 /* Skip optional white space before operand. */
2156 if (is_space_char (*l))
2157 ++l;
2158 if (!is_operand_char (*l) && *l != END_OF_INSN)
2159 {
2160 as_bad (_("invalid character %s before operand %d"),
2161 output_invalid (*l),
2162 i.operands + 1);
2163 return NULL;
2164 }
2165 token_start = l; /* after white space */
2166 paren_not_balanced = 0;
2167 while (paren_not_balanced || *l != ',')
2168 {
2169 if (*l == END_OF_INSN)
2170 {
2171 if (paren_not_balanced)
2172 {
2173 if (!intel_syntax)
2174 as_bad (_("unbalanced parenthesis in operand %d."),
2175 i.operands + 1);
2176 else
2177 as_bad (_("unbalanced brackets in operand %d."),
2178 i.operands + 1);
2179 return NULL;
2180 }
2181 else
2182 break; /* we are done */
2183 }
2184 else if (!is_operand_char (*l) && !is_space_char (*l))
2185 {
2186 as_bad (_("invalid character %s in operand %d"),
2187 output_invalid (*l),
2188 i.operands + 1);
2189 return NULL;
2190 }
2191 if (!intel_syntax)
2192 {
2193 if (*l == '(')
2194 ++paren_not_balanced;
2195 if (*l == ')')
2196 --paren_not_balanced;
2197 }
2198 else
2199 {
2200 if (*l == '[')
2201 ++paren_not_balanced;
2202 if (*l == ']')
2203 --paren_not_balanced;
2204 }
2205 l++;
2206 }
2207 if (l != token_start)
2208 { /* Yes, we've read in another operand. */
2209 unsigned int operand_ok;
2210 this_operand = i.operands++;
2211 if (i.operands > MAX_OPERANDS)
2212 {
2213 as_bad (_("spurious operands; (%d operands/instruction max)"),
2214 MAX_OPERANDS);
2215 return NULL;
2216 }
2217 /* Now parse operand adding info to 'i' as we go along. */
2218 END_STRING_AND_SAVE (l);
2219
2220 if (intel_syntax)
2221 operand_ok =
2222 i386_intel_operand (token_start,
2223 intel_float_operand (mnemonic));
2224 else
2225 operand_ok = i386_operand (token_start);
2226
2227 RESTORE_END_STRING (l);
2228 if (!operand_ok)
2229 return NULL;
2230 }
2231 else
2232 {
2233 if (expecting_operand)
2234 {
2235 expecting_operand_after_comma:
2236 as_bad (_("expecting operand after ','; got nothing"));
2237 return NULL;
2238 }
2239 if (*l == ',')
2240 {
2241 as_bad (_("expecting operand before ','; got nothing"));
2242 return NULL;
2243 }
2244 }
7f3f1ea2 2245
29b0f896
AM		 2246 /* Now *l must be either ',' or END_OF_INSN. */
2247 if (*l == ',')
2248 {
2249 if (*++l == END_OF_INSN)
2250 {
2251 /* Just skip it, if it's \n complain. */
2252 goto expecting_operand_after_comma;
2253 }
2254 expecting_operand = 1;
2255 }
2256 }
2257 return l;
2258}
7f3f1ea2 2259
050dfa73 2260static void
e3bb37b5 2261swap_imm_operands (void)
050dfa73
MM		 2262{
2263 union i386_op temp_op;
2264 unsigned int temp_type;
2265 enum bfd_reloc_code_real temp_reloc;
2266 int xchg1 = 0;
2267 int xchg2 = 1;
2268
2269 temp_type = i.types[xchg2];
2270 i.types[xchg2] = i.types[xchg1];
2271 i.types[xchg1] = temp_type;
2272 temp_op = i.op[xchg2];
2273 i.op[xchg2] = i.op[xchg1];
2274 i.op[xchg1] = temp_op;
2275 temp_reloc = i.reloc[xchg2];
2276 i.reloc[xchg2] = i.reloc[xchg1];
2277 i.reloc[xchg1] = temp_reloc;
2278}
2279
2280
29b0f896 2281static void
e3bb37b5 2282swap_operands (void)
29b0f896
AM		 2283{
2284 union i386_op temp_op;
2285 unsigned int temp_type;
f86103b7 2286 enum bfd_reloc_code_real temp_reloc;
b7c61d9a 2287 int xchg1, xchg2;
252b5132 2288
b7c61d9a 2289 switch (i.operands)
050dfa73 2290 {
b7c61d9a
L		 2291 case 4:
2292 xchg1 = 1;
2293 xchg2 = i.operands - 2;
050dfa73
MM		 2294 temp_type = i.types[xchg2];
2295 i.types[xchg2] = i.types[xchg1];
2296 i.types[xchg1] = temp_type;
2297 temp_op = i.op[xchg2];
2298 i.op[xchg2] = i.op[xchg1];
2299 i.op[xchg1] = temp_op;
2300 temp_reloc = i.reloc[xchg2];
2301 i.reloc[xchg2] = i.reloc[xchg1];
2302 i.reloc[xchg1] = temp_reloc;
b7c61d9a
L		 2303 case 3:
2304 case 2:
29b0f896 2305 xchg1 = 0;
b7c61d9a
L		 2306 xchg2 = i.operands - 1;
2307 temp_type = i.types[xchg2];
2308 i.types[xchg2] = i.types[xchg1];
2309 i.types[xchg1] = temp_type;
2310 temp_op = i.op[xchg2];
2311 i.op[xchg2] = i.op[xchg1];
2312 i.op[xchg1] = temp_op;
2313 temp_reloc = i.reloc[xchg2];
2314 i.reloc[xchg2] = i.reloc[xchg1];
2315 i.reloc[xchg1] = temp_reloc;
2316 break;
2317 default:
2318 abort ();
29b0f896 2319 }
29b0f896
AM		 2320
2321 if (i.mem_operands == 2)
2322 {
2323 const seg_entry *temp_seg;
2324 temp_seg = i.seg[0];
2325 i.seg[0] = i.seg[1];
2326 i.seg[1] = temp_seg;
2327 }
2328}
252b5132 2329
29b0f896
AM		 2330/* Try to ensure constant immediates are represented in the smallest
2331 opcode possible. */
2332static void
e3bb37b5 2333optimize_imm (void)
29b0f896
AM		 2334{
2335 char guess_suffix = 0;
2336 int op;
252b5132 2337
29b0f896
AM		 2338 if (i.suffix)
2339 guess_suffix = i.suffix;
2340 else if (i.reg_operands)
2341 {
2342 /* Figure out a suffix from the last register operand specified.
2343 We can't do this properly yet, ie. excluding InOutPortReg,
2344 but the following works for instructions with immediates.
2345 In any case, we can't set i.suffix yet. */
2346 for (op = i.operands; --op >= 0;)
2347 if (i.types[op] & Reg)
252b5132 2348 {
29b0f896
AM		 2349 if (i.types[op] & Reg8)
2350 guess_suffix = BYTE_MNEM_SUFFIX;
2351 else if (i.types[op] & Reg16)
2352 guess_suffix = WORD_MNEM_SUFFIX;
2353 else if (i.types[op] & Reg32)
2354 guess_suffix = LONG_MNEM_SUFFIX;
2355 else if (i.types[op] & Reg64)
2356 guess_suffix = QWORD_MNEM_SUFFIX;
2357 break;
252b5132 2358 }
29b0f896
AM		 2359 }
2360 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2361 guess_suffix = WORD_MNEM_SUFFIX;
2362
2363 for (op = i.operands; --op >= 0;)
2364 if (i.types[op] & Imm)
2365 {
2366 switch (i.op[op].imms->X_op)
252b5132 2367 {
29b0f896
AM		 2368 case O_constant:
2369 /* If a suffix is given, this operand may be shortened. */
2370 switch (guess_suffix)
252b5132 2371 {
29b0f896
AM		 2372 case LONG_MNEM_SUFFIX:
2373 i.types[op] |= Imm32 | Imm64;
2374 break;
2375 case WORD_MNEM_SUFFIX:
2376 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2377 break;
2378 case BYTE_MNEM_SUFFIX:
2379 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2380 break;
252b5132 2381 }
252b5132 2382
29b0f896
AM		 2383 /* If this operand is at most 16 bits, convert it
2384 to a signed 16 bit number before trying to see
2385 whether it will fit in an even smaller size.
2386 This allows a 16-bit operand such as $0xffe0 to
2387 be recognised as within Imm8S range. */
2388 if ((i.types[op] & Imm16)
2389 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2390 {
29b0f896
AM		 2391 i.op[op].imms->X_add_number =
2392 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2393 }
2394 if ((i.types[op] & Imm32)
2395 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2396 == 0))
2397 {
2398 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2399 ^ ((offsetT) 1 << 31))
2400 - ((offsetT) 1 << 31));
2401 }
2402 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2403
29b0f896
AM		 2404 /* We must avoid matching of Imm32 templates when 64bit
2405 only immediate is available. */
2406 if (guess_suffix == QWORD_MNEM_SUFFIX)
2407 i.types[op] &= ~Imm32;
2408 break;
252b5132 2409
29b0f896
AM		 2410 case O_absent:
2411 case O_register:
2412 abort ();
2413
2414 /* Symbols and expressions. */
2415 default:
9cd96992
JB		 2416 /* Convert symbolic operand to proper sizes for matching, but don't
2417 prevent matching a set of insns that only supports sizes other
2418 than those matching the insn suffix. */
2419 {
2420 unsigned int mask, allowed = 0;
2421 const template *t;
2422
2423 for (t = current_templates->start; t < current_templates->end; ++t)
2424 allowed |= t->operand_types[op];
2425 switch (guess_suffix)
2426 {
2427 case QWORD_MNEM_SUFFIX:
2428 mask = Imm64 | Imm32S;
2429 break;
2430 case LONG_MNEM_SUFFIX:
2431 mask = Imm32;
2432 break;
2433 case WORD_MNEM_SUFFIX:
2434 mask = Imm16;
2435 break;
2436 case BYTE_MNEM_SUFFIX:
2437 mask = Imm8;
2438 break;
2439 default:
2440 mask = 0;
2441 break;
2442 }
64e74474
AM		 2443 if (mask & allowed)
2444 i.types[op] &= mask;
9cd96992 2445 }
29b0f896 2446 break;
252b5132 2447 }
29b0f896
AM		 2448 }
2449}
47926f60 2450
29b0f896
AM		 2451/* Try to use the smallest displacement type too. */
2452static void
e3bb37b5 2453optimize_disp (void)
29b0f896
AM		 2454{
2455 int op;
3e73aa7c 2456
29b0f896 2457 for (op = i.operands; --op >= 0;)
b300c311 2458 if (i.types[op] & Disp)
252b5132 2459 {
b300c311 2460 if (i.op[op].disps->X_op == O_constant)
252b5132 2461 {
b300c311 2462 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2463
b300c311
L		 2464 if ((i.types[op] & Disp16)
2465 && (disp & ~(offsetT) 0xffff) == 0)
2466 {
2467 /* If this operand is at most 16 bits, convert
2468 to a signed 16 bit number and don't use 64bit
2469 displacement. */
2470 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2471 i.types[op] &= ~Disp64;
2472 }
2473 if ((i.types[op] & Disp32)
2474 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2475 {
2476 /* If this operand is at most 32 bits, convert
2477 to a signed 32 bit number and don't use 64bit
2478 displacement. */
2479 disp &= (((offsetT) 2 << 31) - 1);
2480 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2481 i.types[op] &= ~Disp64;
2482 }
2483 if (!disp && (i.types[op] & BaseIndex))
2484 {
2485 i.types[op] &= ~Disp;
2486 i.op[op].disps = 0;
2487 i.disp_operands--;
2488 }
2489 else if (flag_code == CODE_64BIT)
2490 {
2491 if (fits_in_signed_long (disp))
28a9d8f5
L		 2492 {
2493 i.types[op] &= ~Disp64;
2494 i.types[op] |= Disp32S;
2495 }
b300c311
L		 2496 if (fits_in_unsigned_long (disp))
2497 i.types[op] |= Disp32;
2498 }
2499 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2500 && fits_in_signed_byte (disp))
2501 i.types[op] |= Disp8;
252b5132 2502 }
67a4f2b7
AO		 2503 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2504 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2505 {
2506 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2507 i.op[op].disps, 0, i.reloc[op]);
2508 i.types[op] &= ~Disp;
2509 }
2510 else
b300c311
L		 2511 /* We only support 64bit displacement on constants. */
2512 i.types[op] &= ~Disp64;
252b5132 2513 }
29b0f896
AM		 2514}
2515
2516static int
e3bb37b5 2517match_template (void)
29b0f896
AM		 2518{
2519 /* Points to template once we've found it. */
2520 const template *t;
f48ff2ae 2521 unsigned int overlap0, overlap1, overlap2, overlap3;
29b0f896
AM		 2522 unsigned int found_reverse_match;
2523 int suffix_check;
f48ff2ae 2524 unsigned int operand_types [MAX_OPERANDS];
539e75ad 2525 int addr_prefix_disp;
a5c311ca 2526 unsigned int j;
29b0f896 2527
f48ff2ae
L		 2528#if MAX_OPERANDS != 4
2529# error "MAX_OPERANDS must be 4."
2530#endif
2531
29b0f896
AM		 2532#define MATCH(overlap, given, template) \
2533 ((overlap & ~JumpAbsolute) \
2534 && (((given) & (BaseIndex | JumpAbsolute)) \
2535 == ((overlap) & (BaseIndex | JumpAbsolute))))
2536
2537 /* If given types r0 and r1 are registers they must be of the same type
2538 unless the expected operand type register overlap is null.
2539 Note that Acc in a template matches every size of reg. */
2540#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2541 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2542 || ((g0) & Reg) == ((g1) & Reg) \
2543 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2544
2545 overlap0 = 0;
2546 overlap1 = 0;
2547 overlap2 = 0;
f48ff2ae 2548 overlap3 = 0;
29b0f896 2549 found_reverse_match = 0;
a5c311ca
L		 2550 for (j = 0; j < MAX_OPERANDS; j++)
2551 operand_types [j] = 0;
539e75ad 2552 addr_prefix_disp = -1;
29b0f896
AM		 2553 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2554 ? No_bSuf
2555 : (i.suffix == WORD_MNEM_SUFFIX
2556 ? No_wSuf
2557 : (i.suffix == SHORT_MNEM_SUFFIX
2558 ? No_sSuf
2559 : (i.suffix == LONG_MNEM_SUFFIX
2560 ? No_lSuf
2561 : (i.suffix == QWORD_MNEM_SUFFIX
2562 ? No_qSuf
2563 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2564 ? No_xSuf : 0))))));
2565
45aa61fe 2566 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2567 {
539e75ad
L		 2568 addr_prefix_disp = -1;
2569
29b0f896
AM		 2570 /* Must have right number of operands. */
2571 if (i.operands != t->operands)
2572 continue;
2573
2574 /* Check the suffix, except for some instructions in intel mode. */
2575 if ((t->opcode_modifier & suffix_check)
2576 && !(intel_syntax
9306ca4a 2577 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2578 continue;
2579
a5c311ca
L		 2580 for (j = 0; j < MAX_OPERANDS; j++)
2581 operand_types [j] = t->operand_types [j];
539e75ad 2582
45aa61fe
AM		 2583 /* In general, don't allow 64-bit operands in 32-bit mode. */
2584 if (i.suffix == QWORD_MNEM_SUFFIX
2585 && flag_code != CODE_64BIT
2586 && (intel_syntax
2587 ? (!(t->opcode_modifier & IgnoreSize)
2588 && !intel_float_operand (t->name))
2589 : intel_float_operand (t->name) != 2)
539e75ad
L		 2590 && (!(operand_types[0] & (RegMMX | RegXMM))
2591 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
45aa61fe
AM		 2592 && (t->base_opcode != 0x0fc7
2593 || t->extension_opcode != 1 /* cmpxchg8b */))
2594 continue;
2595
29b0f896
AM		 2596 /* Do not verify operands when there are none. */
2597 else if (!t->operands)
2598 {
2599 if (t->cpu_flags & ~cpu_arch_flags)
2600 continue;
2601 /* We've found a match; break out of loop. */
2602 break;
2603 }
252b5132 2604
539e75ad
L		 2605 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2606 into Disp32/Disp16/Disp32 operand. */
2607 if (i.prefix[ADDR_PREFIX] != 0)
2608 {
a5c311ca 2609 unsigned int DispOn = 0, DispOff = 0;
539e75ad
L		 2610
2611 switch (flag_code)
2612 {
2613 case CODE_16BIT:
2614 DispOn = Disp32;
2615 DispOff = Disp16;
2616 break;
2617 case CODE_32BIT:
2618 DispOn = Disp16;
2619 DispOff = Disp32;
2620 break;
2621 case CODE_64BIT:
2622 DispOn = Disp32;
2623 DispOff = Disp64;
2624 break;
2625 }
2626
f48ff2ae 2627 for (j = 0; j < MAX_OPERANDS; j++)
539e75ad
L		 2628 {
2629 /* There should be only one Disp operand. */
2630 if ((operand_types[j] & DispOff))
2631 {
2632 addr_prefix_disp = j;
2633 operand_types[j] |= DispOn;
2634 operand_types[j] &= ~DispOff;
2635 break;
2636 }
2637 }
2638 }
2639
2640 overlap0 = i.types[0] & operand_types[0];
29b0f896
AM		 2641 switch (t->operands)
2642 {
2643 case 1:
539e75ad 2644 if (!MATCH (overlap0, i.types[0], operand_types[0]))
29b0f896
AM		 2645 continue;
2646 break;
2647 case 2:
2648 case 3:
f48ff2ae 2649 case 4:
539e75ad
L		 2650 overlap1 = i.types[1] & operand_types[1];
2651 if (!MATCH (overlap0, i.types[0], operand_types[0])
2652 || !MATCH (overlap1, i.types[1], operand_types[1])
cb712a9e 2653 /* monitor in SSE3 is a very special case. The first
708587a4 2654 register and the second register may have different
cb712a9e
L		 2655 sizes. */
2656 || !((t->base_opcode == 0x0f01
2657 && t->extension_opcode == 0xc8)
2658 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2659 operand_types[0],
cb712a9e 2660 overlap1, i.types[1],
539e75ad 2661 operand_types[1])))
29b0f896
AM		 2662 {
2663 /* Check if other direction is valid ... */
2664 if ((t->opcode_modifier & (D | FloatD)) == 0)
2665 continue;
2666
2667 /* Try reversing direction of operands. */
539e75ad
L		 2668 overlap0 = i.types[0] & operand_types[1];
2669 overlap1 = i.types[1] & operand_types[0];
2670 if (!MATCH (overlap0, i.types[0], operand_types[1])
2671 || !MATCH (overlap1, i.types[1], operand_types[0])
29b0f896 2672 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2673 operand_types[1],
29b0f896 2674 overlap1, i.types[1],
539e75ad 2675 operand_types[0]))
29b0f896
AM		 2676 {
2677 /* Does not match either direction. */
2678 continue;
2679 }
2680 /* found_reverse_match holds which of D or FloatDR
2681 we've found. */
2682 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2683 }
f48ff2ae 2684 else
29b0f896 2685 {
f48ff2ae 2686 /* Found a forward 2 operand match here. */
d1cbb4db
L		 2687 switch (t->operands)
2688 {
2689 case 4:
2690 overlap3 = i.types[3] & operand_types[3];
2691 case 3:
2692 overlap2 = i.types[2] & operand_types[2];
2693 break;
2694 }
29b0f896 2695
f48ff2ae
L		 2696 switch (t->operands)
2697 {
2698 case 4:
2699 if (!MATCH (overlap3, i.types[3], operand_types[3])
2700 || !CONSISTENT_REGISTER_MATCH (overlap2,
2701 i.types[2],
2702 operand_types[2],
2703 overlap3,
2704 i.types[3],
2705 operand_types[3]))
2706 continue;
2707 case 3:
2708 /* Here we make use of the fact that there are no
2709 reverse match 3 operand instructions, and all 3
2710 operand instructions only need to be checked for
2711 register consistency between operands 2 and 3. */
2712 if (!MATCH (overlap2, i.types[2], operand_types[2])
2713 || !CONSISTENT_REGISTER_MATCH (overlap1,
2714 i.types[1],
2715 operand_types[1],
2716 overlap2,
2717 i.types[2],
2718 operand_types[2]))
2719 continue;
2720 break;
2721 }
29b0f896 2722 }
f48ff2ae 2723 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 2724 slip through to break. */
2725 }
2726 if (t->cpu_flags & ~cpu_arch_flags)
2727 {
2728 found_reverse_match = 0;
2729 continue;
2730 }
2731 /* We've found a match; break out of loop. */
2732 break;
2733 }
2734
2735 if (t == current_templates->end)
2736 {
2737 /* We found no match. */
2738 as_bad (_("suffix or operands invalid for `%s'"),
2739 current_templates->start->name);
2740 return 0;
2741 }
252b5132 2742
29b0f896
AM		 2743 if (!quiet_warnings)
2744 {
2745 if (!intel_syntax
2746 && ((i.types[0] & JumpAbsolute)
539e75ad 2747 != (operand_types[0] & JumpAbsolute)))
29b0f896
AM		 2748 {
2749 as_warn (_("indirect %s without `*'"), t->name);
2750 }
2751
2752 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2753 == (IsPrefix | IgnoreSize))
2754 {
2755 /* Warn them that a data or address size prefix doesn't
2756 affect assembly of the next line of code. */
2757 as_warn (_("stand-alone `%s' prefix"), t->name);
2758 }
2759 }
2760
2761 /* Copy the template we found. */
2762 i.tm = *t;
539e75ad
L		 2763
2764 if (addr_prefix_disp != -1)
2765 i.tm.operand_types[addr_prefix_disp]
2766 = operand_types[addr_prefix_disp];
2767
29b0f896
AM		 2768 if (found_reverse_match)
2769 {
2770 /* If we found a reverse match we must alter the opcode
2771 direction bit. found_reverse_match holds bits to change
2772 (different for int & float insns). */
2773
2774 i.tm.base_opcode ^= found_reverse_match;
2775
539e75ad
L		 2776 i.tm.operand_types[0] = operand_types[1];
2777 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 2778 }
2779
2780 return 1;
2781}
2782
2783static int
e3bb37b5 2784check_string (void)
29b0f896
AM		 2785{
2786 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2787 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2788 {
2789 if (i.seg[0] != NULL && i.seg[0] != &es)
2790 {
2791 as_bad (_("`%s' operand %d must use `%%es' segment"),
2792 i.tm.name,
2793 mem_op + 1);
2794 return 0;
2795 }
2796 /* There's only ever one segment override allowed per instruction.
2797 This instruction possibly has a legal segment override on the
2798 second operand, so copy the segment to where non-string
2799 instructions store it, allowing common code. */
2800 i.seg[0] = i.seg[1];
2801 }
2802 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2803 {
2804 if (i.seg[1] != NULL && i.seg[1] != &es)
2805 {
2806 as_bad (_("`%s' operand %d must use `%%es' segment"),
2807 i.tm.name,
2808 mem_op + 2);
2809 return 0;
2810 }
2811 }
2812 return 1;
2813}
2814
2815static int
543613e9 2816process_suffix (void)
29b0f896
AM		 2817{
2818 /* If matched instruction specifies an explicit instruction mnemonic
2819 suffix, use it. */
2820 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2821 {
2822 if (i.tm.opcode_modifier & Size16)
2823 i.suffix = WORD_MNEM_SUFFIX;
2824 else if (i.tm.opcode_modifier & Size64)
2825 i.suffix = QWORD_MNEM_SUFFIX;
2826 else
2827 i.suffix = LONG_MNEM_SUFFIX;
2828 }
2829 else if (i.reg_operands)
2830 {
2831 /* If there's no instruction mnemonic suffix we try to invent one
2832 based on register operands. */
2833 if (!i.suffix)
2834 {
2835 /* We take i.suffix from the last register operand specified,
2836 Destination register type is more significant than source
2837 register type. */
2838 int op;
543613e9 2839
29b0f896
AM		 2840 for (op = i.operands; --op >= 0;)
2841 if ((i.types[op] & Reg)
2842 && !(i.tm.operand_types[op] & InOutPortReg))
2843 {
2844 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2845 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2846 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2847 LONG_MNEM_SUFFIX);
2848 break;
2849 }
2850 }
2851 else if (i.suffix == BYTE_MNEM_SUFFIX)
2852 {
2853 if (!check_byte_reg ())
2854 return 0;
2855 }
2856 else if (i.suffix == LONG_MNEM_SUFFIX)
2857 {
2858 if (!check_long_reg ())
2859 return 0;
2860 }
2861 else if (i.suffix == QWORD_MNEM_SUFFIX)
2862 {
2863 if (!check_qword_reg ())
2864 return 0;
2865 }
2866 else if (i.suffix == WORD_MNEM_SUFFIX)
2867 {
2868 if (!check_word_reg ())
2869 return 0;
2870 }
2871 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2872 /* Do nothing if the instruction is going to ignore the prefix. */
2873 ;
2874 else
2875 abort ();
2876 }
9306ca4a
JB		 2877 else if ((i.tm.opcode_modifier & DefaultSize)
2878 && !i.suffix
2879 /* exclude fldenv/frstor/fsave/fstenv */
2880 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2881 {
2882 i.suffix = stackop_size;
2883 }
9306ca4a
JB		 2884 else if (intel_syntax
2885 && !i.suffix
2886 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2887 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2888 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2889 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2890 {
2891 switch (flag_code)
2892 {
2893 case CODE_64BIT:
2894 if (!(i.tm.opcode_modifier & No_qSuf))
2895 {
2896 i.suffix = QWORD_MNEM_SUFFIX;
2897 break;
2898 }
2899 case CODE_32BIT:
2900 if (!(i.tm.opcode_modifier & No_lSuf))
2901 i.suffix = LONG_MNEM_SUFFIX;
2902 break;
2903 case CODE_16BIT:
2904 if (!(i.tm.opcode_modifier & No_wSuf))
2905 i.suffix = WORD_MNEM_SUFFIX;
2906 break;
2907 }
2908 }
252b5132 2909
9306ca4a 2910 if (!i.suffix)
29b0f896 2911 {
9306ca4a
JB		 2912 if (!intel_syntax)
2913 {
2914 if (i.tm.opcode_modifier & W)
2915 {
2916 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2917 return 0;
2918 }
2919 }
2920 else
2921 {
64e74474
AM		 2922 unsigned int suffixes = (~i.tm.opcode_modifier
2923 & (No_bSuf
2924 | No_wSuf
2925 | No_lSuf
2926 | No_sSuf
2927 | No_xSuf
2928 | No_qSuf));
9306ca4a
JB		 2929
2930 if ((i.tm.opcode_modifier & W)
2931 || ((suffixes & (suffixes - 1))
2932 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2933 {
2934 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2935 return 0;
2936 }
2937 }
29b0f896 2938 }
252b5132 2939
9306ca4a
JB		 2940 /* Change the opcode based on the operand size given by i.suffix;
2941 We don't need to change things for byte insns. */
2942
29b0f896
AM		 2943 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2944 {
2945 /* It's not a byte, select word/dword operation. */
2946 if (i.tm.opcode_modifier & W)
2947 {
2948 if (i.tm.opcode_modifier & ShortForm)
2949 i.tm.base_opcode |= 8;
2950 else
2951 i.tm.base_opcode |= 1;
2952 }
0f3f3d8b 2953
29b0f896
AM		 2954 /* Now select between word & dword operations via the operand
2955 size prefix, except for instructions that will ignore this
2956 prefix anyway. */
cb712a9e
L		 2957 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2958 {
2959 /* monitor in SSE3 is a very special case. The default size
2960 of AX is the size of mode. The address size override
2961 prefix will change the size of AX. */
2962 if (i.op->regs[0].reg_type &
2963 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2964 if (!add_prefix (ADDR_PREFIX_OPCODE))
2965 return 0;
2966 }
2967 else if (i.suffix != QWORD_MNEM_SUFFIX
2968 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2969 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2970 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2971 || (flag_code == CODE_64BIT
2972 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2973 {
2974 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2975
29b0f896
AM		 2976 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2977 prefix = ADDR_PREFIX_OPCODE;
252b5132 2978
29b0f896
AM		 2979 if (!add_prefix (prefix))
2980 return 0;
24eab124 2981 }
252b5132 2982
29b0f896
AM		 2983 /* Set mode64 for an operand. */
2984 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2985 && flag_code == CODE_64BIT
29b0f896 2986 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L		 2987 {
2988 /* Special case for xchg %rax,%rax. It is NOP and doesn't
2989 need rex64. */
2990 if (i.operands != 2
2991 || i.types [0] != (Acc | Reg64)
2992 || i.types [1] != (Acc | Reg64)
2993 || strcmp (i.tm.name, "xchg") != 0)
2994 i.rex |= REX_MODE64;
2995 }
3e73aa7c 2996
29b0f896
AM		 2997 /* Size floating point instruction. */
2998 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 2999 if (i.tm.opcode_modifier & FloatMF)
3000 i.tm.base_opcode ^= 4;
29b0f896 3001 }
7ecd2f8b 3002
29b0f896
AM		 3003 return 1;
3004}
3e73aa7c 3005
29b0f896 3006static int
543613e9 3007check_byte_reg (void)
29b0f896
AM		 3008{
3009 int op;
543613e9 3010
29b0f896
AM		 3011 for (op = i.operands; --op >= 0;)
3012 {
3013 /* If this is an eight bit register, it's OK. If it's the 16 or
3014 32 bit version of an eight bit register, we will just use the
3015 low portion, and that's OK too. */
3016 if (i.types[op] & Reg8)
3017 continue;
3018
3019 /* movzx and movsx should not generate this warning. */
3020 if (intel_syntax
3021 && (i.tm.base_opcode == 0xfb7
3022 || i.tm.base_opcode == 0xfb6
3023 || i.tm.base_opcode == 0x63
3024 || i.tm.base_opcode == 0xfbe
3025 || i.tm.base_opcode == 0xfbf))
3026 continue;
3027
65ec77d2 3028 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3029 {
3030 /* Prohibit these changes in the 64bit mode, since the
3031 lowering is more complicated. */
3032 if (flag_code == CODE_64BIT
3033 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3034 {
2ca3ace5
L		 3035 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3036 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3037 i.suffix);
3038 return 0;
3039 }
3040#if REGISTER_WARNINGS
3041 if (!quiet_warnings
3042 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3043 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3044 (i.op[op].regs + (i.types[op] & Reg16
3045 ? REGNAM_AL - REGNAM_AX
3046 : REGNAM_AL - REGNAM_EAX))->reg_name,
3047 i.op[op].regs->reg_name,
3048 i.suffix);
3049#endif
3050 continue;
3051 }
3052 /* Any other register is bad. */
3053 if (i.types[op] & (Reg | RegMMX | RegXMM
3054 | SReg2 | SReg3
3055 | Control | Debug | Test
3056 | FloatReg | FloatAcc))
3057 {
3058 as_bad (_("`%%%s' not allowed with `%s%c'"),
3059 i.op[op].regs->reg_name,
3060 i.tm.name,
3061 i.suffix);
3062 return 0;
3063 }
3064 }
3065 return 1;
3066}
3067
3068static int
e3bb37b5 3069check_long_reg (void)
29b0f896
AM		 3070{
3071 int op;
3072
3073 for (op = i.operands; --op >= 0;)
3074 /* Reject eight bit registers, except where the template requires
3075 them. (eg. movzb) */
3076 if ((i.types[op] & Reg8) != 0
3077 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3078 {
3079 as_bad (_("`%%%s' not allowed with `%s%c'"),
3080 i.op[op].regs->reg_name,
3081 i.tm.name,
3082 i.suffix);
3083 return 0;
3084 }
3085 /* Warn if the e prefix on a general reg is missing. */
3086 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3087 && (i.types[op] & Reg16) != 0
3088 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3089 {
3090 /* Prohibit these changes in the 64bit mode, since the
3091 lowering is more complicated. */
3092 if (flag_code == CODE_64BIT)
252b5132 3093 {
2ca3ace5
L		 3094 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3095 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3096 i.suffix);
3097 return 0;
252b5132 3098 }
29b0f896
AM		 3099#if REGISTER_WARNINGS
3100 else
3101 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3102 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3103 i.op[op].regs->reg_name,
3104 i.suffix);
3105#endif
252b5132 3106 }
29b0f896
AM		 3107 /* Warn if the r prefix on a general reg is missing. */
3108 else if ((i.types[op] & Reg64) != 0
3109 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 3110 {
2ca3ace5
L		 3111 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3112 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3113 i.suffix);
3114 return 0;
3115 }
3116 return 1;
3117}
252b5132 3118
29b0f896 3119static int
e3bb37b5 3120check_qword_reg (void)
29b0f896
AM		 3121{
3122 int op;
252b5132 3123
29b0f896
AM		 3124 for (op = i.operands; --op >= 0; )
3125 /* Reject eight bit registers, except where the template requires
3126 them. (eg. movzb) */
3127 if ((i.types[op] & Reg8) != 0
3128 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3129 {
3130 as_bad (_("`%%%s' not allowed with `%s%c'"),
3131 i.op[op].regs->reg_name,
3132 i.tm.name,
3133 i.suffix);
3134 return 0;
3135 }
3136 /* Warn if the e prefix on a general reg is missing. */
3137 else if (((i.types[op] & Reg16) != 0
3138 || (i.types[op] & Reg32) != 0)
3139 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3140 {
3141 /* Prohibit these changes in the 64bit mode, since the
3142 lowering is more complicated. */
2ca3ace5
L		 3143 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3144 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3145 i.suffix);
3146 return 0;
252b5132 3147 }
29b0f896
AM		 3148 return 1;
3149}
252b5132 3150
29b0f896 3151static int
e3bb37b5 3152check_word_reg (void)
29b0f896
AM		 3153{
3154 int op;
3155 for (op = i.operands; --op >= 0;)
3156 /* Reject eight bit registers, except where the template requires
3157 them. (eg. movzb) */
3158 if ((i.types[op] & Reg8) != 0
3159 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3160 {
3161 as_bad (_("`%%%s' not allowed with `%s%c'"),
3162 i.op[op].regs->reg_name,
3163 i.tm.name,
3164 i.suffix);
3165 return 0;
3166 }
3167 /* Warn if the e prefix on a general reg is present. */
3168 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3169 && (i.types[op] & Reg32) != 0
3170 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 3171 {
29b0f896
AM		 3172 /* Prohibit these changes in the 64bit mode, since the
3173 lowering is more complicated. */
3174 if (flag_code == CODE_64BIT)
252b5132 3175 {
2ca3ace5
L		 3176 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3177 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3178 i.suffix);
3179 return 0;
252b5132 3180 }
29b0f896
AM		 3181 else
3182#if REGISTER_WARNINGS
3183 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3184 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3185 i.op[op].regs->reg_name,
3186 i.suffix);
3187#endif
3188 }
3189 return 1;
3190}
252b5132 3191
29b0f896 3192static int
e3bb37b5 3193finalize_imm (void)
29b0f896
AM		 3194{
3195 unsigned int overlap0, overlap1, overlap2;
3196
3197 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 3198 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 3199 && overlap0 != Imm8 && overlap0 != Imm8S
3200 && overlap0 != Imm16 && overlap0 != Imm32S
3201 && overlap0 != Imm32 && overlap0 != Imm64)
3202 {
3203 if (i.suffix)
3204 {
3205 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3206 ? Imm8 | Imm8S
3207 : (i.suffix == WORD_MNEM_SUFFIX
3208 ? Imm16
3209 : (i.suffix == QWORD_MNEM_SUFFIX
3210 ? Imm64 | Imm32S
3211 : Imm32)));
3212 }
3213 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3214 || overlap0 == (Imm16 | Imm32)
3215 || overlap0 == (Imm16 | Imm32S))
3216 {
3217 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3218 ? Imm16 : Imm32S);
3219 }
3220 if (overlap0 != Imm8 && overlap0 != Imm8S
3221 && overlap0 != Imm16 && overlap0 != Imm32S
3222 && overlap0 != Imm32 && overlap0 != Imm64)
3223 {
3224 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
3225 return 0;
3226 }
3227 }
3228 i.types[0] = overlap0;
3229
3230 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 3231 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 3232 && overlap1 != Imm8 && overlap1 != Imm8S
3233 && overlap1 != Imm16 && overlap1 != Imm32S
3234 && overlap1 != Imm32 && overlap1 != Imm64)
3235 {
3236 if (i.suffix)
3237 {
3238 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3239 ? Imm8 | Imm8S
3240 : (i.suffix == WORD_MNEM_SUFFIX
3241 ? Imm16
3242 : (i.suffix == QWORD_MNEM_SUFFIX
3243 ? Imm64 | Imm32S
3244 : Imm32)));
3245 }
3246 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3247 || overlap1 == (Imm16 | Imm32)
3248 || overlap1 == (Imm16 | Imm32S))
3249 {
3250 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3251 ? Imm16 : Imm32S);
3252 }
3253 if (overlap1 != Imm8 && overlap1 != Imm8S
3254 && overlap1 != Imm16 && overlap1 != Imm32S
3255 && overlap1 != Imm32 && overlap1 != Imm64)
3256 {
3257 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
3258 return 0;
3259 }
3260 }
3261 i.types[1] = overlap1;
3262
3263 overlap2 = i.types[2] & i.tm.operand_types[2];
3264 assert ((overlap2 & Imm) == 0);
3265 i.types[2] = overlap2;
3266
3267 return 1;
3268}
3269
3270static int
e3bb37b5 3271process_operands (void)
29b0f896
AM		 3272{
3273 /* Default segment register this instruction will use for memory
3274 accesses. 0 means unknown. This is only for optimizing out
3275 unnecessary segment overrides. */
3276 const seg_entry *default_seg = 0;
3277
3278 /* The imul $imm, %reg instruction is converted into
3279 imul $imm, %reg, %reg, and the clr %reg instruction
3280 is converted into xor %reg, %reg. */
3281 if (i.tm.opcode_modifier & regKludge)
3282 {
3283 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3284 /* Pretend we saw the extra register operand. */
cab737b9
L		 3285 assert (i.reg_operands == 1
3286 && i.op[first_reg_op + 1].regs == 0);
29b0f896
AM		 3287 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3288 i.types[first_reg_op + 1] = i.types[first_reg_op];
cab737b9
L		 3289 i.operands++;
3290 i.reg_operands++;
29b0f896
AM		 3291 }
3292
3293 if (i.tm.opcode_modifier & ShortForm)
3294 {
3295 /* The register or float register operand is in operand 0 or 1. */
3296 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3297 /* Register goes in low 3 bits of opcode. */
3298 i.tm.base_opcode |= i.op[op].regs->reg_num;
3299 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3300 i.rex |= REX_EXTZ;
3301 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
3302 {
3303 /* Warn about some common errors, but press on regardless.
3304 The first case can be generated by gcc (<= 2.8.1). */
3305 if (i.operands == 2)
3306 {
3307 /* Reversed arguments on faddp, fsubp, etc. */
3308 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3309 i.op[1].regs->reg_name,
3310 i.op[0].regs->reg_name);
3311 }
3312 else
3313 {
3314 /* Extraneous `l' suffix on fp insn. */
3315 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3316 i.op[0].regs->reg_name);
3317 }
3318 }
3319 }
3320 else if (i.tm.opcode_modifier & Modrm)
3321 {
3322 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3323 must be put into the modrm byte). Now, we make the modrm and
3324 index base bytes based on all the info we've collected. */
29b0f896
AM		 3325
3326 default_seg = build_modrm_byte ();
3327 }
3328 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
3329 {
3330 if (i.tm.base_opcode == POP_SEG_SHORT
3331 && i.op[0].regs->reg_num == 1)
3332 {
3333 as_bad (_("you can't `pop %%cs'"));
3334 return 0;
3335 }
3336 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3337 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3338 i.rex |= REX_EXTZ;
3339 }
3340 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
3341 {
3342 default_seg = &ds;
3343 }
3344 else if ((i.tm.opcode_modifier & IsString) != 0)
3345 {
3346 /* For the string instructions that allow a segment override
3347 on one of their operands, the default segment is ds. */
3348 default_seg = &ds;
3349 }
3350
30123838
JB		 3351 if ((i.tm.base_opcode == 0x8d /* lea */
3352 || (i.tm.cpu_flags & CpuSVME))
3353 && i.seg[0] && !quiet_warnings)
3354 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3355
3356 /* If a segment was explicitly specified, and the specified segment
3357 is not the default, use an opcode prefix to select it. If we
3358 never figured out what the default segment is, then default_seg
3359 will be zero at this point, and the specified segment prefix will
3360 always be used. */
29b0f896
AM		 3361 if ((i.seg[0]) && (i.seg[0] != default_seg))
3362 {
3363 if (!add_prefix (i.seg[0]->seg_prefix))
3364 return 0;
3365 }
3366 return 1;
3367}
3368
3369static const seg_entry *
e3bb37b5 3370build_modrm_byte (void)
29b0f896
AM		 3371{
3372 const seg_entry *default_seg = 0;
3373
3374 /* i.reg_operands MUST be the number of real register operands;
3375 implicit registers do not count. */
3376 if (i.reg_operands == 2)
3377 {
3378 unsigned int source, dest;
cab737b9
L		 3379
3380 switch (i.operands)
3381 {
3382 case 2:
3383 source = 0;
3384 break;
3385 case 3:
c81128dc
L		 3386 /* When there are 3 operands, one of them may be immediate,
3387 which may be the first or the last operand. Otherwise,
3388 the first operand must be shift count register (cl). */
3389 assert (i.imm_operands == 1
3390 || (i.imm_operands == 0
3391 && (i.types[0] & ShiftCount)));
3392 source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0;
cab737b9
L		 3393 break;
3394 case 4:
3395 /* When there are 4 operands, the first two must be immediate
3396 operands. The source operand will be the 3rd one. */
3397 assert (i.imm_operands == 2
3398 && (i.types[0] & Imm)
3399 && (i.types[1] & Imm));
3400 source = 2;
3401 break;
3402 default:
3403 abort ();
3404 }
3405
29b0f896
AM		 3406 dest = source + 1;
3407
3408 i.rm.mode = 3;
3409 /* One of the register operands will be encoded in the i.tm.reg
3410 field, the other in the combined i.tm.mode and i.tm.regmem
3411 fields. If no form of this instruction supports a memory
3412 destination operand, then we assume the source operand may
3413 sometimes be a memory operand and so we need to store the
3414 destination in the i.rm.reg field. */
3415 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3416 {
3417 i.rm.reg = i.op[dest].regs->reg_num;
3418 i.rm.regmem = i.op[source].regs->reg_num;
3419 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3420 i.rex |= REX_EXTX;
3421 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3422 i.rex |= REX_EXTZ;
3423 }
3424 else
3425 {
3426 i.rm.reg = i.op[source].regs->reg_num;
3427 i.rm.regmem = i.op[dest].regs->reg_num;
3428 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3429 i.rex |= REX_EXTZ;
3430 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3431 i.rex |= REX_EXTX;
3432 }
c4a530c5
JB		 3433 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3434 {
3435 if (!((i.types[0] | i.types[1]) & Control))
3436 abort ();
3437 i.rex &= ~(REX_EXTX | REX_EXTZ);
3438 add_prefix (LOCK_PREFIX_OPCODE);
3439 }
29b0f896
AM		 3440 }
3441 else
3442 { /* If it's not 2 reg operands... */
3443 if (i.mem_operands)
3444 {
3445 unsigned int fake_zero_displacement = 0;
3446 unsigned int op = ((i.types[0] & AnyMem)
3447 ? 0
3448 : (i.types[1] & AnyMem) ? 1 : 2);
3449
3450 default_seg = &ds;
3451
3452 if (i.base_reg == 0)
3453 {
3454 i.rm.mode = 0;
3455 if (!i.disp_operands)
3456 fake_zero_displacement = 1;
3457 if (i.index_reg == 0)
3458 {
3459 /* Operand is just <disp> */
20f0a1fc 3460 if (flag_code == CODE_64BIT)
29b0f896
AM		 3461 {
3462 /* 64bit mode overwrites the 32bit absolute
3463 addressing by RIP relative addressing and
3464 absolute addressing is encoded by one of the
3465 redundant SIB forms. */
3466 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3467 i.sib.base = NO_BASE_REGISTER;
3468 i.sib.index = NO_INDEX_REGISTER;
fc225355
L		 3469 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3470 ? Disp32S : Disp32);
20f0a1fc 3471 }
fc225355
L		 3472 else if ((flag_code == CODE_16BIT)
3473 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 3474 {
3475 i.rm.regmem = NO_BASE_REGISTER_16;
3476 i.types[op] = Disp16;
3477 }
3478 else
3479 {
3480 i.rm.regmem = NO_BASE_REGISTER;
3481 i.types[op] = Disp32;
29b0f896
AM		 3482 }
3483 }
3484 else /* !i.base_reg && i.index_reg */
3485 {
3486 i.sib.index = i.index_reg->reg_num;
3487 i.sib.base = NO_BASE_REGISTER;
3488 i.sib.scale = i.log2_scale_factor;
3489 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3490 i.types[op] &= ~Disp;
3491 if (flag_code != CODE_64BIT)
3492 i.types[op] |= Disp32; /* Must be 32 bit */
3493 else
3494 i.types[op] |= Disp32S;
3495 if ((i.index_reg->reg_flags & RegRex) != 0)
3496 i.rex |= REX_EXTY;
3497 }
3498 }
3499 /* RIP addressing for 64bit mode. */
3500 else if (i.base_reg->reg_type == BaseIndex)
3501 {
3502 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3503 i.types[op] &= ~ Disp;
29b0f896 3504 i.types[op] |= Disp32S;
71903a11 3505 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 3506 if (! i.disp_operands)
3507 fake_zero_displacement = 1;
29b0f896
AM		 3508 }
3509 else if (i.base_reg->reg_type & Reg16)
3510 {
3511 switch (i.base_reg->reg_num)
3512 {
3513 case 3: /* (%bx) */
3514 if (i.index_reg == 0)
3515 i.rm.regmem = 7;
3516 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3517 i.rm.regmem = i.index_reg->reg_num - 6;
3518 break;
3519 case 5: /* (%bp) */
3520 default_seg = &ss;
3521 if (i.index_reg == 0)
3522 {
3523 i.rm.regmem = 6;
3524 if ((i.types[op] & Disp) == 0)
3525 {
3526 /* fake (%bp) into 0(%bp) */
3527 i.types[op] |= Disp8;
252b5132 3528 fake_zero_displacement = 1;
29b0f896
AM		 3529 }
3530 }
3531 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3532 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3533 break;
3534 default: /* (%si) -> 4 or (%di) -> 5 */
3535 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3536 }
3537 i.rm.mode = mode_from_disp_size (i.types[op]);
3538 }
3539 else /* i.base_reg and 32/64 bit mode */
3540 {
3541 if (flag_code == CODE_64BIT
3542 && (i.types[op] & Disp))
fc225355
L		 3543 i.types[op] = ((i.types[op] & Disp8)
3544 | (i.prefix[ADDR_PREFIX] == 0
3545 ? Disp32S : Disp32));
20f0a1fc 3546
29b0f896
AM		 3547 i.rm.regmem = i.base_reg->reg_num;
3548 if ((i.base_reg->reg_flags & RegRex) != 0)
3549 i.rex |= REX_EXTZ;
3550 i.sib.base = i.base_reg->reg_num;
3551 /* x86-64 ignores REX prefix bit here to avoid decoder
3552 complications. */
3553 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3554 {
3555 default_seg = &ss;
3556 if (i.disp_operands == 0)
3557 {
3558 fake_zero_displacement = 1;
3559 i.types[op] |= Disp8;
3560 }
3561 }
3562 else if (i.base_reg->reg_num == ESP_REG_NUM)
3563 {
3564 default_seg = &ss;
3565 }
3566 i.sib.scale = i.log2_scale_factor;
3567 if (i.index_reg == 0)
3568 {
3569 /* <disp>(%esp) becomes two byte modrm with no index
3570 register. We've already stored the code for esp
3571 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3572 Any base register besides %esp will not use the
3573 extra modrm byte. */
3574 i.sib.index = NO_INDEX_REGISTER;
3575#if !SCALE1_WHEN_NO_INDEX
3576 /* Another case where we force the second modrm byte. */
3577 if (i.log2_scale_factor)
3578 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3579#endif
29b0f896
AM		 3580 }
3581 else
3582 {
3583 i.sib.index = i.index_reg->reg_num;
3584 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3585 if ((i.index_reg->reg_flags & RegRex) != 0)
3586 i.rex |= REX_EXTY;
3587 }
67a4f2b7
AO		 3588
3589 if (i.disp_operands
3590 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3591 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3592 i.rm.mode = 0;
3593 else
3594 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3595 }
252b5132 3596
29b0f896
AM		 3597 if (fake_zero_displacement)
3598 {
3599 /* Fakes a zero displacement assuming that i.types[op]
3600 holds the correct displacement size. */
3601 expressionS *exp;
3602
3603 assert (i.op[op].disps == 0);
3604 exp = &disp_expressions[i.disp_operands++];
3605 i.op[op].disps = exp;
3606 exp->X_op = O_constant;
3607 exp->X_add_number = 0;
3608 exp->X_add_symbol = (symbolS *) 0;
3609 exp->X_op_symbol = (symbolS *) 0;
3610 }
3611 }
252b5132 3612
29b0f896
AM		 3613 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3614 (if any) based on i.tm.extension_opcode. Again, we must be
3615 careful to make sure that segment/control/debug/test/MMX
3616 registers are coded into the i.rm.reg field. */
3617 if (i.reg_operands)
3618 {
3619 unsigned int op =
3620 ((i.types[0]
3621 & (Reg | RegMMX | RegXMM
3622 | SReg2 | SReg3
3623 | Control | Debug | Test))
3624 ? 0
3625 : ((i.types[1]
3626 & (Reg | RegMMX | RegXMM
3627 | SReg2 | SReg3
3628 | Control | Debug | Test))
3629 ? 1
3630 : 2));
3631 /* If there is an extension opcode to put here, the register
3632 number must be put into the regmem field. */
3633 if (i.tm.extension_opcode != None)
3634 {
3635 i.rm.regmem = i.op[op].regs->reg_num;
3636 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3637 i.rex |= REX_EXTZ;
3638 }
3639 else
3640 {
3641 i.rm.reg = i.op[op].regs->reg_num;
3642 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3643 i.rex |= REX_EXTX;
3644 }
252b5132 3645
29b0f896
AM		 3646 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3647 must set it to 3 to indicate this is a register operand
3648 in the regmem field. */
3649 if (!i.mem_operands)
3650 i.rm.mode = 3;
3651 }
252b5132 3652
29b0f896
AM		 3653 /* Fill in i.rm.reg field with extension opcode (if any). */
3654 if (i.tm.extension_opcode != None)
3655 i.rm.reg = i.tm.extension_opcode;
3656 }
3657 return default_seg;
3658}
252b5132 3659
29b0f896 3660static void
e3bb37b5 3661output_branch (void)
29b0f896
AM		 3662{
3663 char *p;
3664 int code16;
3665 int prefix;
3666 relax_substateT subtype;
3667 symbolS *sym;
3668 offsetT off;
3669
3670 code16 = 0;
3671 if (flag_code == CODE_16BIT)
3672 code16 = CODE16;
3673
3674 prefix = 0;
3675 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3676 {
29b0f896
AM		 3677 prefix = 1;
3678 i.prefixes -= 1;
3679 code16 ^= CODE16;
252b5132 3680 }
29b0f896
AM		 3681 /* Pentium4 branch hints. */
3682 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3683 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3684 {
29b0f896
AM		 3685 prefix++;
3686 i.prefixes--;
3687 }
3688 if (i.prefix[REX_PREFIX] != 0)
3689 {
3690 prefix++;
3691 i.prefixes--;
2f66722d
AM		 3692 }
3693
29b0f896
AM		 3694 if (i.prefixes != 0 && !intel_syntax)
3695 as_warn (_("skipping prefixes on this instruction"));
3696
3697 /* It's always a symbol; End frag & setup for relax.
3698 Make sure there is enough room in this frag for the largest
3699 instruction we may generate in md_convert_frag. This is 2
3700 bytes for the opcode and room for the prefix and largest
3701 displacement. */
3702 frag_grow (prefix + 2 + 4);
3703 /* Prefix and 1 opcode byte go in fr_fix. */
3704 p = frag_more (prefix + 1);
3705 if (i.prefix[DATA_PREFIX] != 0)
3706 *p++ = DATA_PREFIX_OPCODE;
3707 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3708 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3709 *p++ = i.prefix[SEG_PREFIX];
3710 if (i.prefix[REX_PREFIX] != 0)
3711 *p++ = i.prefix[REX_PREFIX];
3712 *p = i.tm.base_opcode;
3713
3714 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3715 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3716 else if ((cpu_arch_flags & Cpu386) != 0)
3717 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3718 else
3719 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3720 subtype |= code16;
3e73aa7c 3721
29b0f896
AM		 3722 sym = i.op[0].disps->X_add_symbol;
3723 off = i.op[0].disps->X_add_number;
3e73aa7c 3724
29b0f896
AM		 3725 if (i.op[0].disps->X_op != O_constant
3726 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3727 {
29b0f896
AM		 3728 /* Handle complex expressions. */
3729 sym = make_expr_symbol (i.op[0].disps);
3730 off = 0;
3731 }
3e73aa7c 3732
29b0f896
AM		 3733 /* 1 possible extra opcode + 4 byte displacement go in var part.
3734 Pass reloc in fr_var. */
3735 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3736}
3e73aa7c 3737
29b0f896 3738static void
e3bb37b5 3739output_jump (void)
29b0f896
AM		 3740{
3741 char *p;
3742 int size;
3e02c1cc 3743 fixS *fixP;
29b0f896
AM		 3744
3745 if (i.tm.opcode_modifier & JumpByte)
3746 {
3747 /* This is a loop or jecxz type instruction. */
3748 size = 1;
3749 if (i.prefix[ADDR_PREFIX] != 0)
3750 {
3751 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3752 i.prefixes -= 1;
3753 }
3754 /* Pentium4 branch hints. */
3755 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3756 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3757 {
3758 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3759 i.prefixes--;
3e73aa7c
JH		 3760 }
3761 }
29b0f896
AM		 3762 else
3763 {
3764 int code16;
3e73aa7c 3765
29b0f896
AM		 3766 code16 = 0;
3767 if (flag_code == CODE_16BIT)
3768 code16 = CODE16;
3e73aa7c 3769
29b0f896
AM		 3770 if (i.prefix[DATA_PREFIX] != 0)
3771 {
3772 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3773 i.prefixes -= 1;
3774 code16 ^= CODE16;
3775 }
252b5132 3776
29b0f896
AM		 3777 size = 4;
3778 if (code16)
3779 size = 2;
3780 }
9fcc94b6 3781
29b0f896
AM		 3782 if (i.prefix[REX_PREFIX] != 0)
3783 {
3784 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3785 i.prefixes -= 1;
3786 }
252b5132 3787
29b0f896
AM		 3788 if (i.prefixes != 0 && !intel_syntax)
3789 as_warn (_("skipping prefixes on this instruction"));
e0890092 3790
29b0f896
AM		 3791 p = frag_more (1 + size);
3792 *p++ = i.tm.base_opcode;
e0890092 3793
3e02c1cc
AM		 3794 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3795 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3796
3797 /* All jumps handled here are signed, but don't use a signed limit
3798 check for 32 and 16 bit jumps as we want to allow wrap around at
3799 4G and 64k respectively. */
3800 if (size == 1)
3801 fixP->fx_signed = 1;
29b0f896 3802}
e0890092 3803
29b0f896 3804static void
e3bb37b5 3805output_interseg_jump (void)
29b0f896
AM		 3806{
3807 char *p;
3808 int size;
3809 int prefix;
3810 int code16;
252b5132 3811
29b0f896
AM		 3812 code16 = 0;
3813 if (flag_code == CODE_16BIT)
3814 code16 = CODE16;
a217f122 3815
29b0f896
AM		 3816 prefix = 0;
3817 if (i.prefix[DATA_PREFIX] != 0)
3818 {
3819 prefix = 1;
3820 i.prefixes -= 1;
3821 code16 ^= CODE16;
3822 }
3823 if (i.prefix[REX_PREFIX] != 0)
3824 {
3825 prefix++;
3826 i.prefixes -= 1;
3827 }
252b5132 3828
29b0f896
AM		 3829 size = 4;
3830 if (code16)
3831 size = 2;
252b5132 3832
29b0f896
AM		 3833 if (i.prefixes != 0 && !intel_syntax)
3834 as_warn (_("skipping prefixes on this instruction"));
252b5132 3835
29b0f896
AM		 3836 /* 1 opcode; 2 segment; offset */
3837 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3838
29b0f896
AM		 3839 if (i.prefix[DATA_PREFIX] != 0)
3840 *p++ = DATA_PREFIX_OPCODE;
252b5132 3841
29b0f896
AM		 3842 if (i.prefix[REX_PREFIX] != 0)
3843 *p++ = i.prefix[REX_PREFIX];
252b5132 3844
29b0f896
AM		 3845 *p++ = i.tm.base_opcode;
3846 if (i.op[1].imms->X_op == O_constant)
3847 {
3848 offsetT n = i.op[1].imms->X_add_number;
252b5132 3849
29b0f896
AM		 3850 if (size == 2
3851 && !fits_in_unsigned_word (n)
3852 && !fits_in_signed_word (n))
3853 {
3854 as_bad (_("16-bit jump out of range"));
3855 return;
3856 }
3857 md_number_to_chars (p, n, size);
3858 }
3859 else
3860 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3861 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3862 if (i.op[0].imms->X_op != O_constant)
3863 as_bad (_("can't handle non absolute segment in `%s'"),
3864 i.tm.name);
3865 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3866}
a217f122 3867
29b0f896 3868static void
e3bb37b5 3869output_insn (void)
29b0f896 3870{
2bbd9c25
JJ		 3871 fragS *insn_start_frag;
3872 offsetT insn_start_off;
3873
29b0f896
AM		 3874 /* Tie dwarf2 debug info to the address at the start of the insn.
3875 We can't do this after the insn has been output as the current
3876 frag may have been closed off. eg. by frag_var. */
3877 dwarf2_emit_insn (0);
3878
2bbd9c25
JJ		 3879 insn_start_frag = frag_now;
3880 insn_start_off = frag_now_fix ();
3881
29b0f896
AM		 3882 /* Output jumps. */
3883 if (i.tm.opcode_modifier & Jump)
3884 output_branch ();
3885 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3886 output_jump ();
3887 else if (i.tm.opcode_modifier & JumpInterSegment)
3888 output_interseg_jump ();
3889 else
3890 {
3891 /* Output normal instructions here. */
3892 char *p;
3893 unsigned char *q;
331d2d0d 3894 unsigned int prefix;
252b5132 3895
ef05d495
L		 3896 /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
3897 Streaming SIMD extensions 3 Instructions have 3 bytes. We may
3898 use one more higher byte to specify a prefix the instruction
3899 requires. */
3900 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
bc4bd9ab 3901 {
331d2d0d
L		 3902 if (i.tm.base_opcode & 0xff000000)
3903 {
3904 prefix = (i.tm.base_opcode >> 24) & 0xff;
3905 goto check_prefix;
3906 }
3907 }
3908 else if ((i.tm.base_opcode & 0xff0000) != 0)
3909 {
3910 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 3911 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3912 {
64e74474 3913 check_prefix:
bc4bd9ab
MK		 3914 if (prefix != REPE_PREFIX_OPCODE
3915 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3916 add_prefix (prefix);
3917 }
3918 else
331d2d0d 3919 add_prefix (prefix);
0f10071e 3920 }
252b5132 3921
29b0f896
AM		 3922 /* The prefix bytes. */
3923 for (q = i.prefix;
3924 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3925 q++)
3926 {
3927 if (*q)
3928 {
3929 p = frag_more (1);
3930 md_number_to_chars (p, (valueT) *q, 1);
3931 }
3932 }
252b5132 3933
29b0f896
AM		 3934 /* Now the opcode; be careful about word order here! */
3935 if (fits_in_unsigned_byte (i.tm.base_opcode))
3936 {
3937 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3938 }
3939 else
3940 {
ef05d495 3941 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
331d2d0d
L		 3942 {
3943 p = frag_more (3);
3944 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3945 }
3946 else
3947 p = frag_more (2);
0f10071e 3948
29b0f896
AM		 3949 /* Put out high byte first: can't use md_number_to_chars! */
3950 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3951 *p = i.tm.base_opcode & 0xff;
3952 }
3e73aa7c 3953
29b0f896
AM		 3954 /* Now the modrm byte and sib byte (if present). */
3955 if (i.tm.opcode_modifier & Modrm)
3956 {
3957 p = frag_more (1);
3958 md_number_to_chars (p,
3959 (valueT) (i.rm.regmem << 0
3960 | i.rm.reg << 3
3961 | i.rm.mode << 6),
3962 1);
3963 /* If i.rm.regmem == ESP (4)
3964 && i.rm.mode != (Register mode)
3965 && not 16 bit
3966 ==> need second modrm byte. */
3967 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3968 && i.rm.mode != 3
3969 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3970 {
3971 p = frag_more (1);
3972 md_number_to_chars (p,
3973 (valueT) (i.sib.base << 0
3974 | i.sib.index << 3
3975 | i.sib.scale << 6),
3976 1);
3977 }
3978 }
3e73aa7c 3979
29b0f896 3980 if (i.disp_operands)
2bbd9c25 3981 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3982
29b0f896 3983 if (i.imm_operands)
2bbd9c25 3984 output_imm (insn_start_frag, insn_start_off);
29b0f896 3985 }
252b5132 3986
29b0f896
AM		 3987#ifdef DEBUG386
3988 if (flag_debug)
3989 {
7b81dfbb 3990 pi ("" /*line*/, &i);
29b0f896
AM		 3991 }
3992#endif /* DEBUG386 */
3993}
252b5132 3994
29b0f896 3995static void
64e74474 3996output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 3997{
3998 char *p;
3999 unsigned int n;
252b5132 4000
29b0f896
AM		 4001 for (n = 0; n < i.operands; n++)
4002 {
4003 if (i.types[n] & Disp)
4004 {
4005 if (i.op[n].disps->X_op == O_constant)
4006 {
4007 int size;
4008 offsetT val;
252b5132 4009
29b0f896
AM		 4010 size = 4;
4011 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4012 {
4013 size = 2;
4014 if (i.types[n] & Disp8)
4015 size = 1;
4016 if (i.types[n] & Disp64)
4017 size = 8;
4018 }
4019 val = offset_in_range (i.op[n].disps->X_add_number,
4020 size);
4021 p = frag_more (size);
4022 md_number_to_chars (p, val, size);
4023 }
4024 else
4025 {
f86103b7 4026 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4027 int size = 4;
4028 int sign = 0;
4029 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4030
4031 /* The PC relative address is computed relative
4032 to the instruction boundary, so in case immediate
4033 fields follows, we need to adjust the value. */
4034 if (pcrel && i.imm_operands)
4035 {
4036 int imm_size = 4;
4037 unsigned int n1;
252b5132 4038
29b0f896
AM		 4039 for (n1 = 0; n1 < i.operands; n1++)
4040 if (i.types[n1] & Imm)
252b5132 4041 {
29b0f896 4042 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 4043 {
29b0f896
AM		 4044 imm_size = 2;
4045 if (i.types[n1] & (Imm8 | Imm8S))
4046 imm_size = 1;
4047 if (i.types[n1] & Imm64)
4048 imm_size = 8;
252b5132 4049 }
29b0f896 4050 break;
252b5132 4051 }
29b0f896
AM		 4052 /* We should find the immediate. */
4053 if (n1 == i.operands)
4054 abort ();
4055 i.op[n].disps->X_add_number -= imm_size;
4056 }
520dc8e8 4057
29b0f896
AM		 4058 if (i.types[n] & Disp32S)
4059 sign = 1;
3e73aa7c 4060
29b0f896
AM		 4061 if (i.types[n] & (Disp16 | Disp64))
4062 {
4063 size = 2;
4064 if (i.types[n] & Disp64)
4065 size = 8;
4066 }
520dc8e8 4067
29b0f896 4068 p = frag_more (size);
2bbd9c25 4069 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4070 if (GOT_symbol
2bbd9c25 4071 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4072 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4073 || reloc_type == BFD_RELOC_X86_64_32S
4074 || (reloc_type == BFD_RELOC_64
4075 && object_64bit))
d6ab8113
JB		 4076 && (i.op[n].disps->X_op == O_symbol
4077 || (i.op[n].disps->X_op == O_add
4078 && ((symbol_get_value_expression
4079 (i.op[n].disps->X_op_symbol)->X_op)
4080 == O_subtract))))
4081 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4082 {
4083 offsetT add;
4084
4085 if (insn_start_frag == frag_now)
4086 add = (p - frag_now->fr_literal) - insn_start_off;
4087 else
4088 {
4089 fragS *fr;
4090
4091 add = insn_start_frag->fr_fix - insn_start_off;
4092 for (fr = insn_start_frag->fr_next;
4093 fr && fr != frag_now; fr = fr->fr_next)
4094 add += fr->fr_fix;
4095 add += p - frag_now->fr_literal;
4096 }
4097
4fa24527 4098 if (!object_64bit)
7b81dfbb
AJ		 4099 {
4100 reloc_type = BFD_RELOC_386_GOTPC;
4101 i.op[n].imms->X_add_number += add;
4102 }
4103 else if (reloc_type == BFD_RELOC_64)
4104 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4105 else
7b81dfbb
AJ		 4106 /* Don't do the adjustment for x86-64, as there
4107 the pcrel addressing is relative to the _next_
4108 insn, and that is taken care of in other code. */
d6ab8113 4109 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4110 }
062cd5e7 4111 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4112 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4113 }
4114 }
4115 }
4116}
252b5132 4117
29b0f896 4118static void
64e74474 4119output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4120{
4121 char *p;
4122 unsigned int n;
252b5132 4123
29b0f896
AM		 4124 for (n = 0; n < i.operands; n++)
4125 {
4126 if (i.types[n] & Imm)
4127 {
4128 if (i.op[n].imms->X_op == O_constant)
4129 {
4130 int size;
4131 offsetT val;
b4cac588 4132
29b0f896
AM		 4133 size = 4;
4134 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4135 {
4136 size = 2;
4137 if (i.types[n] & (Imm8 | Imm8S))
4138 size = 1;
4139 else if (i.types[n] & Imm64)
4140 size = 8;
4141 }
4142 val = offset_in_range (i.op[n].imms->X_add_number,
4143 size);
4144 p = frag_more (size);
4145 md_number_to_chars (p, val, size);
4146 }
4147 else
4148 {
4149 /* Not absolute_section.
4150 Need a 32-bit fixup (don't support 8bit
4151 non-absolute imms). Try to support other
4152 sizes ... */
f86103b7 4153 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4154 int size = 4;
4155 int sign = 0;
4156
4157 if ((i.types[n] & (Imm32S))
a7d61044
JB		 4158 && (i.suffix == QWORD_MNEM_SUFFIX
4159 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 4160 sign = 1;
4161 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4162 {
4163 size = 2;
4164 if (i.types[n] & (Imm8 | Imm8S))
4165 size = 1;
4166 if (i.types[n] & Imm64)
4167 size = 8;
4168 }
520dc8e8 4169
29b0f896
AM		 4170 p = frag_more (size);
4171 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4172
2bbd9c25
JJ		 4173 /* This is tough to explain. We end up with this one if we
4174 * have operands that look like
4175 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4176 * obtain the absolute address of the GOT, and it is strongly
4177 * preferable from a performance point of view to avoid using
4178 * a runtime relocation for this. The actual sequence of
4179 * instructions often look something like:
4180 *
4181 * call .L66
4182 * .L66:
4183 * popl %ebx
4184 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4185 *
4186 * The call and pop essentially return the absolute address
4187 * of the label .L66 and store it in %ebx. The linker itself
4188 * will ultimately change the first operand of the addl so
4189 * that %ebx points to the GOT, but to keep things simple, the
4190 * .o file must have this operand set so that it generates not
4191 * the absolute address of .L66, but the absolute address of
4192 * itself. This allows the linker itself simply treat a GOTPC
4193 * relocation as asking for a pcrel offset to the GOT to be
4194 * added in, and the addend of the relocation is stored in the
4195 * operand field for the instruction itself.
4196 *
4197 * Our job here is to fix the operand so that it would add
4198 * the correct offset so that %ebx would point to itself. The
4199 * thing that is tricky is that .-.L66 will point to the
4200 * beginning of the instruction, so we need to further modify
4201 * the operand so that it will point to itself. There are
4202 * other cases where you have something like:
4203 *
4204 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4205 *
4206 * and here no correction would be required. Internally in
4207 * the assembler we treat operands of this form as not being
4208 * pcrel since the '.' is explicitly mentioned, and I wonder
4209 * whether it would simplify matters to do it this way. Who
4210 * knows. In earlier versions of the PIC patches, the
4211 * pcrel_adjust field was used to store the correction, but
4212 * since the expression is not pcrel, I felt it would be
4213 * confusing to do it this way. */
4214
d6ab8113 4215 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4216 || reloc_type == BFD_RELOC_X86_64_32S
4217 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4218 && GOT_symbol
4219 && GOT_symbol == i.op[n].imms->X_add_symbol
4220 && (i.op[n].imms->X_op == O_symbol
4221 || (i.op[n].imms->X_op == O_add
4222 && ((symbol_get_value_expression
4223 (i.op[n].imms->X_op_symbol)->X_op)
4224 == O_subtract))))
4225 {
2bbd9c25
JJ		 4226 offsetT add;
4227
4228 if (insn_start_frag == frag_now)
4229 add = (p - frag_now->fr_literal) - insn_start_off;
4230 else
4231 {
4232 fragS *fr;
4233
4234 add = insn_start_frag->fr_fix - insn_start_off;
4235 for (fr = insn_start_frag->fr_next;
4236 fr && fr != frag_now; fr = fr->fr_next)
4237 add += fr->fr_fix;
4238 add += p - frag_now->fr_literal;
4239 }
4240
4fa24527 4241 if (!object_64bit)
d6ab8113 4242 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4243 else if (size == 4)
d6ab8113 4244 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4245 else if (size == 8)
4246 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4247 i.op[n].imms->X_add_number += add;
29b0f896 4248 }
29b0f896
AM		 4249 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4250 i.op[n].imms, 0, reloc_type);
4251 }
4252 }
4253 }
252b5132
RH		 4254}
4255\f
d182319b
JB		 4256/* x86_cons_fix_new is called via the expression parsing code when a
4257 reloc is needed. We use this hook to get the correct .got reloc. */
4258static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4259static int cons_sign = -1;
4260
4261void
e3bb37b5 4262x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 4263 expressionS *exp)
d182319b
JB		 4264{
4265 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4266
4267 got_reloc = NO_RELOC;
4268
4269#ifdef TE_PE
4270 if (exp->X_op == O_secrel)
4271 {
4272 exp->X_op = O_symbol;
4273 r = BFD_RELOC_32_SECREL;
4274 }
4275#endif
4276
4277 fix_new_exp (frag, off, len, exp, 0, r);
4278}
4279
718ddfc0
JB		 4280#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4281# define lex_got(reloc, adjust, types) NULL
4282#else
f3c180ae
AM		 4283/* Parse operands of the form
4284 <symbol>@GOTOFF+<nnn>
4285 and similar .plt or .got references.
4286
4287 If we find one, set up the correct relocation in RELOC and copy the
4288 input string, minus the `@GOTOFF' into a malloc'd buffer for
4289 parsing by the calling routine. Return this buffer, and if ADJUST
4290 is non-null set it to the length of the string we removed from the
4291 input line. Otherwise return NULL. */
4292static char *
3956db08 4293lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 4294 int *adjust,
4295 unsigned int *types)
f3c180ae 4296{
7b81dfbb
AJ		 4297 /* Some of the relocations depend on the size of what field is to
4298 be relocated. But in our callers i386_immediate and i386_displacement
4299 we don't yet know the operand size (this will be set by insn
4300 matching). Hence we record the word32 relocation here,
4301 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4302 static const struct {
4303 const char *str;
4fa24527 4304 const enum bfd_reloc_code_real rel[2];
3956db08 4305 const unsigned int types64;
f3c180ae 4306 } gotrel[] = {
7b81dfbb 4307 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
4fa24527 4308 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
7b81dfbb 4309 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
4fa24527
JB		 4310 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
4311 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
4312 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
4313 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
4314 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
4315 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
4316 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4317 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
4318 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4319 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
4320 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
7b81dfbb 4321 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 },
67a4f2b7
AO		 4322 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
4323 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 4324 };
4325 char *cp;
4326 unsigned int j;
4327
718ddfc0
JB		 4328 if (!IS_ELF)
4329 return NULL;
4330
f3c180ae
AM		 4331 for (cp = input_line_pointer; *cp != '@'; cp++)
4332 if (is_end_of_line[(unsigned char) *cp])
4333 return NULL;
4334
4335 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4336 {
4337 int len;
4338
4339 len = strlen (gotrel[j].str);
28f81592 4340 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4341 {
4fa24527 4342 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4343 {
28f81592
AM		 4344 int first, second;
4345 char *tmpbuf, *past_reloc;
f3c180ae 4346
4fa24527 4347 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 4348 if (adjust)
4349 *adjust = len;
f3c180ae 4350
3956db08
JB		 4351 if (types)
4352 {
4353 if (flag_code != CODE_64BIT)
4354 *types = Imm32|Disp32;
4355 else
4356 *types = gotrel[j].types64;
4357 }
4358
f3c180ae
AM		 4359 if (GOT_symbol == NULL)
4360 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4361
4362 /* Replace the relocation token with ' ', so that
4363 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 4364
4365 /* The length of the first part of our input line. */
f3c180ae 4366 first = cp - input_line_pointer;
28f81592
AM		 4367
4368 /* The second part goes from after the reloc token until
4369 (and including) an end_of_line char. Don't use strlen
4370 here as the end_of_line char may not be a NUL. */
4371 past_reloc = cp + 1 + len;
4372 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4373 ;
4374 second = cp - past_reloc;
4375
4376 /* Allocate and copy string. The trailing NUL shouldn't
4377 be necessary, but be safe. */
4378 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 4379 memcpy (tmpbuf, input_line_pointer, first);
4380 tmpbuf[first] = ' ';
28f81592
AM		 4381 memcpy (tmpbuf + first + 1, past_reloc, second);
4382 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 4383 return tmpbuf;
4384 }
4385
4fa24527
JB		 4386 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4387 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 4388 return NULL;
4389 }
4390 }
4391
4392 /* Might be a symbol version string. Don't as_bad here. */
4393 return NULL;
4394}
4395
f3c180ae 4396void
e3bb37b5 4397x86_cons (expressionS *exp, int size)
f3c180ae 4398{
4fa24527 4399 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 4400 {
4401 /* Handle @GOTOFF and the like in an expression. */
4402 char *save;
4403 char *gotfree_input_line;
4404 int adjust;
4405
4406 save = input_line_pointer;
3956db08 4407 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4408 if (gotfree_input_line)
4409 input_line_pointer = gotfree_input_line;
4410
4411 expression (exp);
4412
4413 if (gotfree_input_line)
4414 {
4415 /* expression () has merrily parsed up to the end of line,
4416 or a comma - in the wrong buffer. Transfer how far
4417 input_line_pointer has moved to the right buffer. */
4418 input_line_pointer = (save
4419 + (input_line_pointer - gotfree_input_line)
4420 + adjust);
4421 free (gotfree_input_line);
4422 }
4423 }
4424 else
4425 expression (exp);
4426}
4427#endif
4428
d182319b 4429static void signed_cons (int size)
6482c264 4430{
d182319b
JB		 4431 if (flag_code == CODE_64BIT)
4432 cons_sign = 1;
4433 cons (size);
4434 cons_sign = -1;
6482c264
NC		 4435}
4436
d182319b 4437#ifdef TE_PE
6482c264
NC		 4438static void
4439pe_directive_secrel (dummy)
4440 int dummy ATTRIBUTE_UNUSED;
4441{
4442 expressionS exp;
4443
4444 do
4445 {
4446 expression (&exp);
4447 if (exp.X_op == O_symbol)
4448 exp.X_op = O_secrel;
4449
4450 emit_expr (&exp, 4);
4451 }
4452 while (*input_line_pointer++ == ',');
4453
4454 input_line_pointer--;
4455 demand_empty_rest_of_line ();
4456}
6482c264
NC		 4457#endif
4458
252b5132 4459static int
70e41ade 4460i386_immediate (char *imm_start)
252b5132
RH		 4461{
4462 char *save_input_line_pointer;
f3c180ae 4463 char *gotfree_input_line;
252b5132 4464 segT exp_seg = 0;
47926f60 4465 expressionS *exp;
3956db08 4466 unsigned int types = ~0U;
252b5132
RH		 4467
4468 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4469 {
31b2323c
L		 4470 as_bad (_("at most %d immediate operands are allowed"),
4471 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 4472 return 0;
4473 }
4474
4475 exp = &im_expressions[i.imm_operands++];
520dc8e8 4476 i.op[this_operand].imms = exp;
252b5132
RH		 4477
4478 if (is_space_char (*imm_start))
4479 ++imm_start;
4480
4481 save_input_line_pointer = input_line_pointer;
4482 input_line_pointer = imm_start;
4483
3956db08 4484 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4485 if (gotfree_input_line)
4486 input_line_pointer = gotfree_input_line;
252b5132
RH		 4487
4488 exp_seg = expression (exp);
4489
83183c0c 4490 SKIP_WHITESPACE ();
252b5132 4491 if (*input_line_pointer)
f3c180ae 4492 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4493
4494 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4495 if (gotfree_input_line)
4496 free (gotfree_input_line);
252b5132 4497
2daf4fd8 4498 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4499 {
47926f60 4500 /* Missing or bad expr becomes absolute 0. */
d0b47220 4501 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4502 imm_start);
252b5132
RH		 4503 exp->X_op = O_constant;
4504 exp->X_add_number = 0;
4505 exp->X_add_symbol = (symbolS *) 0;
4506 exp->X_op_symbol = (symbolS *) 0;
252b5132 4507 }
3e73aa7c 4508 else if (exp->X_op == O_constant)
252b5132 4509 {
47926f60 4510 /* Size it properly later. */
3e73aa7c
JH		 4511 i.types[this_operand] |= Imm64;
4512 /* If BFD64, sign extend val. */
4513 if (!use_rela_relocations)
4514 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4515 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4516 }
4c63da97 4517#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4518 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4519 && exp_seg != absolute_section
47926f60 4520 && exp_seg != text_section
24eab124
AM		 4521 && exp_seg != data_section
4522 && exp_seg != bss_section
4523 && exp_seg != undefined_section
f86103b7 4524 && !bfd_is_com_section (exp_seg))
252b5132 4525 {
d0b47220 4526 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4527 return 0;
4528 }
4529#endif
bb8f5920
L		 4530 else if (!intel_syntax && exp->X_op == O_register)
4531 {
4532 as_bad (_("illegal immediate register operand %s"), imm_start);
4533 return 0;
4534 }
252b5132
RH		 4535 else
4536 {
4537 /* This is an address. The size of the address will be
24eab124 4538 determined later, depending on destination register,
3e73aa7c
JH		 4539 suffix, or the default for the section. */
4540 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4541 i.types[this_operand] &= types;
252b5132
RH		 4542 }
4543
4544 return 1;
4545}
4546
551c1ca1 4547static char *
e3bb37b5 4548i386_scale (char *scale)
252b5132 4549{
551c1ca1
AM		 4550 offsetT val;
4551 char *save = input_line_pointer;
252b5132 4552
551c1ca1
AM		 4553 input_line_pointer = scale;
4554 val = get_absolute_expression ();
4555
4556 switch (val)
252b5132 4557 {
551c1ca1 4558 case 1:
252b5132
RH		 4559 i.log2_scale_factor = 0;
4560 break;
551c1ca1 4561 case 2:
252b5132
RH		 4562 i.log2_scale_factor = 1;
4563 break;
551c1ca1 4564 case 4:
252b5132
RH		 4565 i.log2_scale_factor = 2;
4566 break;
551c1ca1 4567 case 8:
252b5132
RH		 4568 i.log2_scale_factor = 3;
4569 break;
4570 default:
a724f0f4
JB		 4571 {
4572 char sep = *input_line_pointer;
4573
4574 *input_line_pointer = '\0';
4575 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4576 scale);
4577 *input_line_pointer = sep;
4578 input_line_pointer = save;
4579 return NULL;
4580 }
252b5132 4581 }
29b0f896 4582 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4583 {
4584 as_warn (_("scale factor of %d without an index register"),
24eab124 4585 1 << i.log2_scale_factor);
252b5132
RH		 4586#if SCALE1_WHEN_NO_INDEX
4587 i.log2_scale_factor = 0;
4588#endif
4589 }
551c1ca1
AM		 4590 scale = input_line_pointer;
4591 input_line_pointer = save;
4592 return scale;
252b5132
RH		 4593}
4594
252b5132 4595static int
e3bb37b5 4596i386_displacement (char *disp_start, char *disp_end)
252b5132 4597{
29b0f896 4598 expressionS *exp;
252b5132
RH		 4599 segT exp_seg = 0;
4600 char *save_input_line_pointer;
f3c180ae 4601 char *gotfree_input_line;
e05278af 4602 int bigdisp, override;
3956db08 4603 unsigned int types = Disp;
252b5132 4604
31b2323c
L		 4605 if (i.disp_operands == MAX_MEMORY_OPERANDS)
4606 {
4607 as_bad (_("at most %d displacement operands are allowed"),
4608 MAX_MEMORY_OPERANDS);
4609 return 0;
4610 }
4611
e05278af
JB		 4612 if ((i.types[this_operand] & JumpAbsolute)
4613 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4614 {
4615 bigdisp = Disp32;
4616 override = (i.prefix[ADDR_PREFIX] != 0);
4617 }
4618 else
4619 {
4620 /* For PC-relative branches, the width of the displacement
4621 is dependent upon data size, not address size. */
4622 bigdisp = 0;
4623 override = (i.prefix[DATA_PREFIX] != 0);
4624 }
3e73aa7c 4625 if (flag_code == CODE_64BIT)
7ecd2f8b 4626 {
e05278af 4627 if (!bigdisp)
64e74474
AM		 4628 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4629 ? Disp16
4630 : Disp32S | Disp32);
e05278af 4631 else if (!override)
3956db08 4632 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4633 }
e05278af
JB		 4634 else
4635 {
4636 if (!bigdisp)
4637 {
4638 if (!override)
4639 override = (i.suffix == (flag_code != CODE_16BIT
4640 ? WORD_MNEM_SUFFIX
4641 : LONG_MNEM_SUFFIX));
4642 bigdisp = Disp32;
4643 }
4644 if ((flag_code == CODE_16BIT) ^ override)
4645 bigdisp = Disp16;
4646 }
252b5132
RH		 4647 i.types[this_operand] |= bigdisp;
4648
4649 exp = &disp_expressions[i.disp_operands];
520dc8e8 4650 i.op[this_operand].disps = exp;
252b5132
RH		 4651 i.disp_operands++;
4652 save_input_line_pointer = input_line_pointer;
4653 input_line_pointer = disp_start;
4654 END_STRING_AND_SAVE (disp_end);
4655
4656#ifndef GCC_ASM_O_HACK
4657#define GCC_ASM_O_HACK 0
4658#endif
4659#if GCC_ASM_O_HACK
4660 END_STRING_AND_SAVE (disp_end + 1);
4661 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4662 && displacement_string_end[-1] == '+')
252b5132
RH		 4663 {
4664 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4665 constraint within gcc asm statements.
4666 For instance:
4667
4668 #define _set_tssldt_desc(n,addr,limit,type) \
4669 __asm__ __volatile__ ( \
4670 "movw %w2,%0\n\t" \
4671 "movw %w1,2+%0\n\t" \
4672 "rorl $16,%1\n\t" \
4673 "movb %b1,4+%0\n\t" \
4674 "movb %4,5+%0\n\t" \
4675 "movb $0,6+%0\n\t" \
4676 "movb %h1,7+%0\n\t" \
4677 "rorl $16,%1" \
4678 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4679
4680 This works great except that the output assembler ends
4681 up looking a bit weird if it turns out that there is
4682 no offset. You end up producing code that looks like:
4683
4684 #APP
4685 movw $235,(%eax)
4686 movw %dx,2+(%eax)
4687 rorl $16,%edx
4688 movb %dl,4+(%eax)
4689 movb $137,5+(%eax)
4690 movb $0,6+(%eax)
4691 movb %dh,7+(%eax)
4692 rorl $16,%edx
4693 #NO_APP
4694
47926f60 4695 So here we provide the missing zero. */
24eab124
AM		 4696
4697 *displacement_string_end = '0';
252b5132
RH		 4698 }
4699#endif
3956db08 4700 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4701 if (gotfree_input_line)
4702 input_line_pointer = gotfree_input_line;
252b5132 4703
24eab124 4704 exp_seg = expression (exp);
252b5132 4705
636c26b0
AM		 4706 SKIP_WHITESPACE ();
4707 if (*input_line_pointer)
4708 as_bad (_("junk `%s' after expression"), input_line_pointer);
4709#if GCC_ASM_O_HACK
4710 RESTORE_END_STRING (disp_end + 1);
4711#endif
4712 RESTORE_END_STRING (disp_end);
4713 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4714 if (gotfree_input_line)
4715 free (gotfree_input_line);
636c26b0 4716
24eab124
AM		 4717 /* We do this to make sure that the section symbol is in
4718 the symbol table. We will ultimately change the relocation
47926f60 4719 to be relative to the beginning of the section. */
1ae12ab7 4720 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4721 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4722 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4723 {
636c26b0
AM		 4724 if (exp->X_op != O_symbol)
4725 {
4726 as_bad (_("bad expression used with @%s"),
4727 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4728 ? "GOTPCREL"
4729 : "GOTOFF"));
4730 return 0;
4731 }
4732
e5cb08ac 4733 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4734 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4735 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4736 exp->X_op = O_subtract;
4737 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4738 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4739 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4740 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4741 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4742 else
29b0f896 4743 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4744 }
252b5132 4745
2daf4fd8
AM		 4746 if (exp->X_op == O_absent || exp->X_op == O_big)
4747 {
47926f60 4748 /* Missing or bad expr becomes absolute 0. */
d0b47220 4749 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4750 disp_start);
4751 exp->X_op = O_constant;
4752 exp->X_add_number = 0;
4753 exp->X_add_symbol = (symbolS *) 0;
4754 exp->X_op_symbol = (symbolS *) 0;
4755 }
4756
4c63da97 4757#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4758 if (exp->X_op != O_constant
45288df1 4759 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4760 && exp_seg != absolute_section
45288df1
AM		 4761 && exp_seg != text_section
4762 && exp_seg != data_section
4763 && exp_seg != bss_section
31312f95 4764 && exp_seg != undefined_section
f86103b7 4765 && !bfd_is_com_section (exp_seg))
24eab124 4766 {
d0b47220 4767 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4768 return 0;
4769 }
252b5132 4770#endif
3956db08
JB		 4771
4772 if (!(i.types[this_operand] & ~Disp))
4773 i.types[this_operand] &= types;
4774
252b5132
RH		 4775 return 1;
4776}
4777
eecb386c 4778/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4779 Return 1 on success, 0 on a failure. */
4780
252b5132 4781static int
e3bb37b5 4782i386_index_check (const char *operand_string)
252b5132 4783{
3e73aa7c 4784 int ok;
24eab124 4785#if INFER_ADDR_PREFIX
eecb386c
AM		 4786 int fudged = 0;
4787
24eab124
AM		 4788 tryprefix:
4789#endif
3e73aa7c 4790 ok = 1;
30123838
JB		 4791 if ((current_templates->start->cpu_flags & CpuSVME)
4792 && current_templates->end[-1].operand_types[0] == AnyMem)
4793 {
4794 /* Memory operands of SVME insns are special in that they only allow
4795 rAX as their memory address and ignore any segment override. */
4796 unsigned RegXX;
4797
4798 /* SKINIT is even more restrictive: it always requires EAX. */
4799 if (strcmp (current_templates->start->name, "skinit") == 0)
4800 RegXX = Reg32;
4801 else if (flag_code == CODE_64BIT)
4802 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4803 else
64e74474
AM		 4804 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4805 ? Reg16
4806 : Reg32);
30123838
JB		 4807 if (!i.base_reg
4808 || !(i.base_reg->reg_type & Acc)
4809 || !(i.base_reg->reg_type & RegXX)
4810 || i.index_reg
4811 || (i.types[0] & Disp))
4812 ok = 0;
4813 }
4814 else if (flag_code == CODE_64BIT)
64e74474
AM		 4815 {
4816 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4817
4818 if ((i.base_reg
4819 && ((i.base_reg->reg_type & RegXX) == 0)
4820 && (i.base_reg->reg_type != BaseIndex
4821 || i.index_reg))
4822 || (i.index_reg
4823 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4824 != (RegXX | BaseIndex))))
4825 ok = 0;
3e73aa7c
JH		 4826 }
4827 else
4828 {
4829 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4830 {
4831 /* 16bit checks. */
4832 if ((i.base_reg
29b0f896
AM		 4833 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4834 != (Reg16 | BaseIndex)))
3e73aa7c 4835 || (i.index_reg
29b0f896
AM		 4836 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4837 != (Reg16 | BaseIndex))
4838 || !(i.base_reg
4839 && i.base_reg->reg_num < 6
4840 && i.index_reg->reg_num >= 6
4841 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4842 ok = 0;
4843 }
4844 else
e5cb08ac 4845 {
3e73aa7c
JH		 4846 /* 32bit checks. */
4847 if ((i.base_reg
4848 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4849 || (i.index_reg
29b0f896
AM		 4850 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4851 != (Reg32 | BaseIndex))))
e5cb08ac 4852 ok = 0;
3e73aa7c
JH		 4853 }
4854 }
4855 if (!ok)
24eab124
AM		 4856 {
4857#if INFER_ADDR_PREFIX
20f0a1fc 4858 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4859 {
4860 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4861 i.prefixes += 1;
b23bac36
AM		 4862 /* Change the size of any displacement too. At most one of
4863 Disp16 or Disp32 is set.
4864 FIXME. There doesn't seem to be any real need for separate
4865 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4866 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4867 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 4868 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4869 fudged = 1;
24eab124
AM		 4870 goto tryprefix;
4871 }
eecb386c
AM		 4872 if (fudged)
4873 as_bad (_("`%s' is not a valid base/index expression"),
4874 operand_string);
4875 else
c388dee8 4876#endif
eecb386c
AM		 4877 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4878 operand_string,
3e73aa7c 4879 flag_code_names[flag_code]);
24eab124 4880 }
20f0a1fc 4881 return ok;
24eab124 4882}
252b5132 4883
252b5132 4884/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4885 on error. */
252b5132 4886
252b5132 4887static int
e3bb37b5 4888i386_operand (char *operand_string)
252b5132 4889{
af6bdddf
AM		 4890 const reg_entry *r;
4891 char *end_op;
24eab124 4892 char *op_string = operand_string;
252b5132 4893
24eab124 4894 if (is_space_char (*op_string))
252b5132
RH		 4895 ++op_string;
4896
24eab124 4897 /* We check for an absolute prefix (differentiating,
47926f60 4898 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4899 if (*op_string == ABSOLUTE_PREFIX)
4900 {
4901 ++op_string;
4902 if (is_space_char (*op_string))
4903 ++op_string;
4904 i.types[this_operand] |= JumpAbsolute;
4905 }
252b5132 4906
47926f60 4907 /* Check if operand is a register. */
4d1bb795 4908 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 4909 {
24eab124
AM		 4910 /* Check for a segment override by searching for ':' after a
4911 segment register. */
4912 op_string = end_op;
4913 if (is_space_char (*op_string))
4914 ++op_string;
4915 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4916 {
4917 switch (r->reg_num)
4918 {
4919 case 0:
4920 i.seg[i.mem_operands] = &es;
4921 break;
4922 case 1:
4923 i.seg[i.mem_operands] = &cs;
4924 break;
4925 case 2:
4926 i.seg[i.mem_operands] = &ss;
4927 break;
4928 case 3:
4929 i.seg[i.mem_operands] = &ds;
4930 break;
4931 case 4:
4932 i.seg[i.mem_operands] = &fs;
4933 break;
4934 case 5:
4935 i.seg[i.mem_operands] = &gs;
4936 break;
4937 }
252b5132 4938
24eab124 4939 /* Skip the ':' and whitespace. */
252b5132
RH		 4940 ++op_string;
4941 if (is_space_char (*op_string))
24eab124 4942 ++op_string;
252b5132 4943
24eab124
AM		 4944 if (!is_digit_char (*op_string)
4945 && !is_identifier_char (*op_string)
4946 && *op_string != '('
4947 && *op_string != ABSOLUTE_PREFIX)
4948 {
4949 as_bad (_("bad memory operand `%s'"), op_string);
4950 return 0;
4951 }
47926f60 4952 /* Handle case of %es:*foo. */
24eab124
AM		 4953 if (*op_string == ABSOLUTE_PREFIX)
4954 {
4955 ++op_string;
4956 if (is_space_char (*op_string))
4957 ++op_string;
4958 i.types[this_operand] |= JumpAbsolute;
4959 }
4960 goto do_memory_reference;
4961 }
4962 if (*op_string)
4963 {
d0b47220 4964 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4965 return 0;
4966 }
4967 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4968 i.op[this_operand].regs = r;
24eab124
AM		 4969 i.reg_operands++;
4970 }
af6bdddf
AM		 4971 else if (*op_string == REGISTER_PREFIX)
4972 {
4973 as_bad (_("bad register name `%s'"), op_string);
4974 return 0;
4975 }
24eab124 4976 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4977 {
24eab124
AM		 4978 ++op_string;
4979 if (i.types[this_operand] & JumpAbsolute)
4980 {
d0b47220 4981 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4982 return 0;
4983 }
4984 if (!i386_immediate (op_string))
4985 return 0;
4986 }
4987 else if (is_digit_char (*op_string)
4988 || is_identifier_char (*op_string)
e5cb08ac 4989 || *op_string == '(')
24eab124 4990 {
47926f60 4991 /* This is a memory reference of some sort. */
af6bdddf 4992 char *base_string;
252b5132 4993
47926f60 4994 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4995 char *displacement_string_start;
4996 char *displacement_string_end;
252b5132 4997
24eab124 4998 do_memory_reference:
24eab124
AM		 4999 if ((i.mem_operands == 1
5000 && (current_templates->start->opcode_modifier & IsString) == 0)
5001 || i.mem_operands == 2)
5002 {
5003 as_bad (_("too many memory references for `%s'"),
5004 current_templates->start->name);
5005 return 0;
5006 }
252b5132 5007
24eab124
AM		 5008 /* Check for base index form. We detect the base index form by
5009 looking for an ')' at the end of the operand, searching
5010 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5011 after the '('. */
af6bdddf 5012 base_string = op_string + strlen (op_string);
c3332e24 5013
af6bdddf
AM		 5014 --base_string;
5015 if (is_space_char (*base_string))
5016 --base_string;
252b5132 5017
47926f60 5018 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 5019 displacement_string_start = op_string;
5020 displacement_string_end = base_string + 1;
252b5132 5021
24eab124
AM		 5022 if (*base_string == ')')
5023 {
af6bdddf 5024 char *temp_string;
24eab124
AM		 5025 unsigned int parens_balanced = 1;
5026 /* We've already checked that the number of left & right ()'s are
47926f60 5027 equal, so this loop will not be infinite. */
24eab124
AM		 5028 do
5029 {
5030 base_string--;
5031 if (*base_string == ')')
5032 parens_balanced++;
5033 if (*base_string == '(')
5034 parens_balanced--;
5035 }
5036 while (parens_balanced);
c3332e24 5037
af6bdddf 5038 temp_string = base_string;
c3332e24 5039
24eab124 5040 /* Skip past '(' and whitespace. */
252b5132
RH		 5041 ++base_string;
5042 if (is_space_char (*base_string))
24eab124 5043 ++base_string;
252b5132 5044
af6bdddf 5045 if (*base_string == ','
4d1bb795 5046 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 5047 {
af6bdddf 5048 displacement_string_end = temp_string;
252b5132 5049
af6bdddf 5050 i.types[this_operand] |= BaseIndex;
252b5132 5051
af6bdddf 5052 if (i.base_reg)
24eab124 5053 {
24eab124
AM		 5054 base_string = end_op;
5055 if (is_space_char (*base_string))
5056 ++base_string;
af6bdddf
AM		 5057 }
5058
5059 /* There may be an index reg or scale factor here. */
5060 if (*base_string == ',')
5061 {
5062 ++base_string;
5063 if (is_space_char (*base_string))
5064 ++base_string;
5065
4d1bb795 5066 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 5067 {
af6bdddf 5068 base_string = end_op;
24eab124
AM		 5069 if (is_space_char (*base_string))
5070 ++base_string;
af6bdddf
AM		 5071 if (*base_string == ',')
5072 {
5073 ++base_string;
5074 if (is_space_char (*base_string))
5075 ++base_string;
5076 }
e5cb08ac 5077 else if (*base_string != ')')
af6bdddf
AM		 5078 {
5079 as_bad (_("expecting `,' or `)' after index register in `%s'"),
5080 operand_string);
5081 return 0;
5082 }
24eab124 5083 }
af6bdddf 5084 else if (*base_string == REGISTER_PREFIX)
24eab124 5085 {
af6bdddf 5086 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5087 return 0;
5088 }
252b5132 5089
47926f60 5090 /* Check for scale factor. */
551c1ca1 5091 if (*base_string != ')')
af6bdddf 5092 {
551c1ca1
AM		 5093 char *end_scale = i386_scale (base_string);
5094
5095 if (!end_scale)
af6bdddf 5096 return 0;
24eab124 5097
551c1ca1 5098 base_string = end_scale;
af6bdddf
AM		 5099 if (is_space_char (*base_string))
5100 ++base_string;
5101 if (*base_string != ')')
5102 {
5103 as_bad (_("expecting `)' after scale factor in `%s'"),
5104 operand_string);
5105 return 0;
5106 }
5107 }
5108 else if (!i.index_reg)
24eab124 5109 {
af6bdddf
AM		 5110 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
5111 *base_string);
24eab124
AM		 5112 return 0;
5113 }
5114 }
af6bdddf 5115 else if (*base_string != ')')
24eab124 5116 {
af6bdddf
AM		 5117 as_bad (_("expecting `,' or `)' after base register in `%s'"),
5118 operand_string);
24eab124
AM		 5119 return 0;
5120 }
c3332e24 5121 }
af6bdddf 5122 else if (*base_string == REGISTER_PREFIX)
c3332e24 5123 {
af6bdddf 5124 as_bad (_("bad register name `%s'"), base_string);
24eab124 5125 return 0;
c3332e24 5126 }
24eab124
AM		 5127 }
5128
5129 /* If there's an expression beginning the operand, parse it,
5130 assuming displacement_string_start and
5131 displacement_string_end are meaningful. */
5132 if (displacement_string_start != displacement_string_end)
5133 {
5134 if (!i386_displacement (displacement_string_start,
5135 displacement_string_end))
5136 return 0;
5137 }
5138
5139 /* Special case for (%dx) while doing input/output op. */
5140 if (i.base_reg
5141 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5142 && i.index_reg == 0
5143 && i.log2_scale_factor == 0
5144 && i.seg[i.mem_operands] == 0
5145 && (i.types[this_operand] & Disp) == 0)
5146 {
5147 i.types[this_operand] = InOutPortReg;
5148 return 1;
5149 }
5150
eecb386c
AM		 5151 if (i386_index_check (operand_string) == 0)
5152 return 0;
24eab124
AM		 5153 i.mem_operands++;
5154 }
5155 else
ce8a8b2f
AM		 5156 {
5157 /* It's not a memory operand; argh! */
24eab124
AM		 5158 as_bad (_("invalid char %s beginning operand %d `%s'"),
5159 output_invalid (*op_string),
5160 this_operand + 1,
5161 op_string);
5162 return 0;
5163 }
47926f60 5164 return 1; /* Normal return. */
252b5132
RH		 5165}
5166\f
ee7fcc42
AM		 5167/* md_estimate_size_before_relax()
5168
5169 Called just before relax() for rs_machine_dependent frags. The x86
5170 assembler uses these frags to handle variable size jump
5171 instructions.
5172
5173 Any symbol that is now undefined will not become defined.
5174 Return the correct fr_subtype in the frag.
5175 Return the initial "guess for variable size of frag" to caller.
5176 The guess is actually the growth beyond the fixed part. Whatever
5177 we do to grow the fixed or variable part contributes to our
5178 returned value. */
5179
252b5132
RH		 5180int
5181md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5182 fragS *fragP;
5183 segT segment;
252b5132 5184{
252b5132 5185 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5186 check for un-relaxable symbols. On an ELF system, we can't relax
5187 an externally visible symbol, because it may be overridden by a
5188 shared library. */
5189 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5190#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5191 || (IS_ELF
31312f95
AM		 5192 && (S_IS_EXTERNAL (fragP->fr_symbol)
5193 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5194#endif
5195 )
252b5132 5196 {
b98ef147
AM		 5197 /* Symbol is undefined in this segment, or we need to keep a
5198 reloc so that weak symbols can be overridden. */
5199 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5200 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5201 unsigned char *opcode;
5202 int old_fr_fix;
f6af82bd 5203
ee7fcc42
AM		 5204 if (fragP->fr_var != NO_RELOC)
5205 reloc_type = fragP->fr_var;
b98ef147 5206 else if (size == 2)
f6af82bd
AM		 5207 reloc_type = BFD_RELOC_16_PCREL;
5208 else
5209 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5210
ee7fcc42
AM		 5211 old_fr_fix = fragP->fr_fix;
5212 opcode = (unsigned char *) fragP->fr_opcode;
5213
fddf5b5b 5214 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5215 {
fddf5b5b
AM		 5216 case UNCOND_JUMP:
5217 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5218 opcode[0] = 0xe9;
252b5132 5219 fragP->fr_fix += size;
062cd5e7
AS		 5220 fix_new (fragP, old_fr_fix, size,
5221 fragP->fr_symbol,
5222 fragP->fr_offset, 1,
5223 reloc_type);
252b5132
RH		 5224 break;
5225
fddf5b5b 5226 case COND_JUMP86:
412167cb
AM		 5227 if (size == 2
5228 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5229 {
5230 /* Negate the condition, and branch past an
5231 unconditional jump. */
5232 opcode[0] ^= 1;
5233 opcode[1] = 3;
5234 /* Insert an unconditional jump. */
5235 opcode[2] = 0xe9;
5236 /* We added two extra opcode bytes, and have a two byte
5237 offset. */
5238 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5239 fix_new (fragP, old_fr_fix + 2, 2,
5240 fragP->fr_symbol,
5241 fragP->fr_offset, 1,
5242 reloc_type);
fddf5b5b
AM		 5243 break;
5244 }
5245 /* Fall through. */
5246
5247 case COND_JUMP:
412167cb
AM		 5248 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5249 {
3e02c1cc
AM		 5250 fixS *fixP;
5251
412167cb 5252 fragP->fr_fix += 1;
3e02c1cc
AM		 5253 fixP = fix_new (fragP, old_fr_fix, 1,
5254 fragP->fr_symbol,
5255 fragP->fr_offset, 1,
5256 BFD_RELOC_8_PCREL);
5257 fixP->fx_signed = 1;
412167cb
AM		 5258 break;
5259 }
93c2a809 5260
24eab124 5261 /* This changes the byte-displacement jump 0x7N
fddf5b5b 5262 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 5263 opcode[1] = opcode[0] + 0x10;
f6af82bd 5264 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 5265 /* We've added an opcode byte. */
5266 fragP->fr_fix += 1 + size;
062cd5e7
AS		 5267 fix_new (fragP, old_fr_fix + 1, size,
5268 fragP->fr_symbol,
5269 fragP->fr_offset, 1,
5270 reloc_type);
252b5132 5271 break;
fddf5b5b
AM		 5272
5273 default:
5274 BAD_CASE (fragP->fr_subtype);
5275 break;
252b5132
RH		 5276 }
5277 frag_wane (fragP);
ee7fcc42 5278 return fragP->fr_fix - old_fr_fix;
252b5132 5279 }
93c2a809 5280
93c2a809
AM		 5281 /* Guess size depending on current relax state. Initially the relax
5282 state will correspond to a short jump and we return 1, because
5283 the variable part of the frag (the branch offset) is one byte
5284 long. However, we can relax a section more than once and in that
5285 case we must either set fr_subtype back to the unrelaxed state,
5286 or return the value for the appropriate branch. */
5287 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 5288}
5289
47926f60
KH		 5290/* Called after relax() is finished.
5291
5292 In: Address of frag.
5293 fr_type == rs_machine_dependent.
5294 fr_subtype is what the address relaxed to.
5295
5296 Out: Any fixSs and constants are set up.
5297 Caller will turn frag into a ".space 0". */
5298
252b5132
RH		 5299void
5300md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 5301 bfd *abfd ATTRIBUTE_UNUSED;
5302 segT sec ATTRIBUTE_UNUSED;
29b0f896 5303 fragS *fragP;
252b5132 5304{
29b0f896 5305 unsigned char *opcode;
252b5132 5306 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 5307 offsetT target_address;
5308 offsetT opcode_address;
252b5132 5309 unsigned int extension = 0;
847f7ad4 5310 offsetT displacement_from_opcode_start;
252b5132
RH		 5311
5312 opcode = (unsigned char *) fragP->fr_opcode;
5313
47926f60 5314 /* Address we want to reach in file space. */
252b5132 5315 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 5316
47926f60 5317 /* Address opcode resides at in file space. */
252b5132
RH		 5318 opcode_address = fragP->fr_address + fragP->fr_fix;
5319
47926f60 5320 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 5321 displacement_from_opcode_start = target_address - opcode_address;
5322
fddf5b5b 5323 if ((fragP->fr_subtype & BIG) == 0)
252b5132 5324 {
47926f60
KH		 5325 /* Don't have to change opcode. */
5326 extension = 1; /* 1 opcode + 1 displacement */
252b5132 5327 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 5328 }
5329 else
5330 {
5331 if (no_cond_jump_promotion
5332 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
5333 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 5334
fddf5b5b
AM		 5335 switch (fragP->fr_subtype)
5336 {
5337 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5338 extension = 4; /* 1 opcode + 4 displacement */
5339 opcode[0] = 0xe9;
5340 where_to_put_displacement = &opcode[1];
5341 break;
252b5132 5342
fddf5b5b
AM		 5343 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5344 extension = 2; /* 1 opcode + 2 displacement */
5345 opcode[0] = 0xe9;
5346 where_to_put_displacement = &opcode[1];
5347 break;
252b5132 5348
fddf5b5b
AM		 5349 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5350 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5351 extension = 5; /* 2 opcode + 4 displacement */
5352 opcode[1] = opcode[0] + 0x10;
5353 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5354 where_to_put_displacement = &opcode[2];
5355 break;
252b5132 5356
fddf5b5b
AM		 5357 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5358 extension = 3; /* 2 opcode + 2 displacement */
5359 opcode[1] = opcode[0] + 0x10;
5360 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5361 where_to_put_displacement = &opcode[2];
5362 break;
252b5132 5363
fddf5b5b
AM		 5364 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5365 extension = 4;
5366 opcode[0] ^= 1;
5367 opcode[1] = 3;
5368 opcode[2] = 0xe9;
5369 where_to_put_displacement = &opcode[3];
5370 break;
5371
5372 default:
5373 BAD_CASE (fragP->fr_subtype);
5374 break;
5375 }
252b5132 5376 }
fddf5b5b 5377
7b81dfbb
AJ		 5378 /* If size if less then four we are sure that the operand fits,
5379 but if it's 4, then it could be that the displacement is larger
5380 then -/+ 2GB. */
5381 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5382 && object_64bit
5383 && ((addressT) (displacement_from_opcode_start - extension
5384 + ((addressT) 1 << 31))
5385 > (((addressT) 2 << 31) - 1)))
5386 {
5387 as_bad_where (fragP->fr_file, fragP->fr_line,
5388 _("jump target out of range"));
5389 /* Make us emit 0. */
5390 displacement_from_opcode_start = extension;
5391 }
47926f60 5392 /* Now put displacement after opcode. */
252b5132
RH		 5393 md_number_to_chars ((char *) where_to_put_displacement,
5394 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5395 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5396 fragP->fr_fix += extension;
5397}
5398\f
47926f60
KH		 5399/* Size of byte displacement jmp. */
5400int md_short_jump_size = 2;
5401
5402/* Size of dword displacement jmp. */
5403int md_long_jump_size = 5;
252b5132 5404
252b5132
RH		 5405void
5406md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5407 char *ptr;
5408 addressT from_addr, to_addr;
ab9da554
ILT		 5409 fragS *frag ATTRIBUTE_UNUSED;
5410 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5411{
847f7ad4 5412 offsetT offset;
252b5132
RH		 5413
5414 offset = to_addr - (from_addr + 2);
47926f60
KH		 5415 /* Opcode for byte-disp jump. */
5416 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5417 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5418}
5419
5420void
5421md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5422 char *ptr;
5423 addressT from_addr, to_addr;
a38cf1db
AM		 5424 fragS *frag ATTRIBUTE_UNUSED;
5425 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5426{
847f7ad4 5427 offsetT offset;
252b5132 5428
a38cf1db
AM		 5429 offset = to_addr - (from_addr + 5);
5430 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5431 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5432}
5433\f
5434/* Apply a fixup (fixS) to segment data, once it has been determined
5435 by our caller that we have all the info we need to fix it up.
5436
5437 On the 386, immediates, displacements, and data pointers are all in
5438 the same (little-endian) format, so we don't need to care about which
5439 we are handling. */
5440
94f592af 5441void
55cf6793 5442md_apply_fix (fixP, valP, seg)
47926f60
KH		 5443 /* The fix we're to put in. */
5444 fixS *fixP;
47926f60 5445 /* Pointer to the value of the bits. */
c6682705 5446 valueT *valP;
47926f60
KH		 5447 /* Segment fix is from. */
5448 segT seg ATTRIBUTE_UNUSED;
252b5132 5449{
94f592af 5450 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5451 valueT value = *valP;
252b5132 5452
f86103b7 5453#if !defined (TE_Mach)
93382f6d
AM		 5454 if (fixP->fx_pcrel)
5455 {
5456 switch (fixP->fx_r_type)
5457 {
5865bb77
ILT		 5458 default:
5459 break;
5460
d6ab8113
JB		 5461 case BFD_RELOC_64:
5462 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5463 break;
93382f6d 5464 case BFD_RELOC_32:
ae8887b5 5465 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5466 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5467 break;
5468 case BFD_RELOC_16:
5469 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5470 break;
5471 case BFD_RELOC_8:
5472 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5473 break;
5474 }
5475 }
252b5132 5476
a161fe53 5477 if (fixP->fx_addsy != NULL
31312f95 5478 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5479 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5480 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5481 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5482 && !use_rela_relocations)
252b5132 5483 {
31312f95
AM		 5484 /* This is a hack. There should be a better way to handle this.
5485 This covers for the fact that bfd_install_relocation will
5486 subtract the current location (for partial_inplace, PC relative
5487 relocations); see more below. */
252b5132 5488#ifndef OBJ_AOUT
718ddfc0 5489 if (IS_ELF
252b5132
RH		 5490#ifdef TE_PE
5491 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5492#endif
5493 )
5494 value += fixP->fx_where + fixP->fx_frag->fr_address;
5495#endif
5496#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5497 if (IS_ELF)
252b5132 5498 {
6539b54b 5499 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5500
6539b54b 5501 if ((sym_seg == seg
2f66722d 5502 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5503 && sym_seg != absolute_section))
ae6063d4 5504 && !generic_force_reloc (fixP))
2f66722d
AM		 5505 {
5506 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5507 bfd_install_relocation subtracts them out again. I think
5508 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5509 it. FIXME. */
5510 value += fixP->fx_where + fixP->fx_frag->fr_address;
5511 }
252b5132
RH		 5512 }
5513#endif
5514#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5515 /* For some reason, the PE format does not store a
5516 section address offset for a PC relative symbol. */
5517 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5518 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5519 value += md_pcrel_from (fixP);
5520#endif
5521 }
5522
5523 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5524 and we must not disappoint it. */
252b5132 5525#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5526 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5527 switch (fixP->fx_r_type)
5528 {
5529 case BFD_RELOC_386_PLT32:
3e73aa7c 5530 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5531 /* Make the jump instruction point to the address of the operand. At
5532 runtime we merely add the offset to the actual PLT entry. */
5533 value = -4;
5534 break;
31312f95 5535
13ae64f3
JJ		 5536 case BFD_RELOC_386_TLS_GD:
5537 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5538 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5539 case BFD_RELOC_386_TLS_IE:
5540 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5541 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5542 case BFD_RELOC_X86_64_TLSGD:
5543 case BFD_RELOC_X86_64_TLSLD:
5544 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5545 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5546 value = 0; /* Fully resolved at runtime. No addend. */
5547 /* Fallthrough */
5548 case BFD_RELOC_386_TLS_LE:
5549 case BFD_RELOC_386_TLS_LDO_32:
5550 case BFD_RELOC_386_TLS_LE_32:
5551 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5552 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5553 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5554 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5555 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5556 break;
5557
67a4f2b7
AO		 5558 case BFD_RELOC_386_TLS_DESC_CALL:
5559 case BFD_RELOC_X86_64_TLSDESC_CALL:
5560 value = 0; /* Fully resolved at runtime. No addend. */
5561 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5562 fixP->fx_done = 0;
5563 return;
5564
00f7efb6
JJ		 5565 case BFD_RELOC_386_GOT32:
5566 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5567 value = 0; /* Fully resolved at runtime. No addend. */
5568 break;
47926f60
KH		 5569
5570 case BFD_RELOC_VTABLE_INHERIT:
5571 case BFD_RELOC_VTABLE_ENTRY:
5572 fixP->fx_done = 0;
94f592af 5573 return;
47926f60
KH		 5574
5575 default:
5576 break;
5577 }
5578#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5579 *valP = value;
f86103b7 5580#endif /* !defined (TE_Mach) */
3e73aa7c 5581
3e73aa7c 5582 /* Are we finished with this relocation now? */
c6682705 5583 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5584 fixP->fx_done = 1;
5585 else if (use_rela_relocations)
5586 {
5587 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5588 /* Remember value for tc_gen_reloc. */
5589 fixP->fx_addnumber = value;
3e73aa7c
JH		 5590 value = 0;
5591 }
f86103b7 5592
94f592af 5593 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5594}
252b5132 5595\f
252b5132
RH		 5596#define MAX_LITTLENUMS 6
5597
47926f60
KH		 5598/* Turn the string pointed to by litP into a floating point constant
5599 of type TYPE, and emit the appropriate bytes. The number of
5600 LITTLENUMS emitted is stored in *SIZEP. An error message is
5601 returned, or NULL on OK. */
5602
252b5132
RH		 5603char *
5604md_atof (type, litP, sizeP)
2ab9b79e 5605 int type;
252b5132
RH		 5606 char *litP;
5607 int *sizeP;
5608{
5609 int prec;
5610 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5611 LITTLENUM_TYPE *wordP;
5612 char *t;
5613
5614 switch (type)
5615 {
5616 case 'f':
5617 case 'F':
5618 prec = 2;
5619 break;
5620
5621 case 'd':
5622 case 'D':
5623 prec = 4;
5624 break;
5625
5626 case 'x':
5627 case 'X':
5628 prec = 5;
5629 break;
5630
5631 default:
5632 *sizeP = 0;
5633 return _("Bad call to md_atof ()");
5634 }
5635 t = atof_ieee (input_line_pointer, type, words);
5636 if (t)
5637 input_line_pointer = t;
5638
5639 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5640 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5641 the bigendian 386. */
5642 for (wordP = words + prec - 1; prec--;)
5643 {
5644 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5645 litP += sizeof (LITTLENUM_TYPE);
5646 }
5647 return 0;
5648}
5649\f
2d545b82 5650static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5651
252b5132 5652static char *
e3bb37b5 5653output_invalid (int c)
252b5132 5654{
3882b010 5655 if (ISPRINT (c))
f9f21a03
L		 5656 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5657 "'%c'", c);
252b5132 5658 else
f9f21a03 5659 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5660 "(0x%x)", (unsigned char) c);
252b5132
RH		 5661 return output_invalid_buf;
5662}
5663
af6bdddf 5664/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5665
5666static const reg_entry *
4d1bb795 5667parse_real_register (char *reg_string, char **end_op)
252b5132 5668{
af6bdddf
AM		 5669 char *s = reg_string;
5670 char *p;
252b5132
RH		 5671 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5672 const reg_entry *r;
5673
5674 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5675 if (*s == REGISTER_PREFIX)
5676 ++s;
5677
5678 if (is_space_char (*s))
5679 ++s;
5680
5681 p = reg_name_given;
af6bdddf 5682 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5683 {
5684 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5685 return (const reg_entry *) NULL;
5686 s++;
252b5132
RH		 5687 }
5688
6588847e
DN		 5689 /* For naked regs, make sure that we are not dealing with an identifier.
5690 This prevents confusing an identifier like `eax_var' with register
5691 `eax'. */
5692 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5693 return (const reg_entry *) NULL;
5694
af6bdddf 5695 *end_op = s;
252b5132
RH		 5696
5697 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5698
5f47d35b 5699 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5700 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5701 {
5f47d35b
AM		 5702 if (is_space_char (*s))
5703 ++s;
5704 if (*s == '(')
5705 {
af6bdddf 5706 ++s;
5f47d35b
AM		 5707 if (is_space_char (*s))
5708 ++s;
5709 if (*s >= '0' && *s <= '7')
5710 {
5711 r = &i386_float_regtab[*s - '0'];
af6bdddf 5712 ++s;
5f47d35b
AM		 5713 if (is_space_char (*s))
5714 ++s;
5715 if (*s == ')')
5716 {
5717 *end_op = s + 1;
5718 return r;
5719 }
5f47d35b 5720 }
47926f60 5721 /* We have "%st(" then garbage. */
5f47d35b
AM		 5722 return (const reg_entry *) NULL;
5723 }
5724 }
5725
1ae00879 5726 if (r != NULL
20f0a1fc 5727 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5728 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5729 && flag_code != CODE_64BIT)
20f0a1fc 5730 return (const reg_entry *) NULL;
1ae00879 5731
252b5132
RH		 5732 return r;
5733}
4d1bb795
JB		 5734
5735/* REG_STRING starts *before* REGISTER_PREFIX. */
5736
5737static const reg_entry *
5738parse_register (char *reg_string, char **end_op)
5739{
5740 const reg_entry *r;
5741
5742 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5743 r = parse_real_register (reg_string, end_op);
5744 else
5745 r = NULL;
5746 if (!r)
5747 {
5748 char *save = input_line_pointer;
5749 char c;
5750 symbolS *symbolP;
5751
5752 input_line_pointer = reg_string;
5753 c = get_symbol_end ();
5754 symbolP = symbol_find (reg_string);
5755 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5756 {
5757 const expressionS *e = symbol_get_value_expression (symbolP);
5758
5759 know (e->X_op == O_register);
5760 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5761 r = i386_regtab + e->X_add_number;
5762 *end_op = input_line_pointer;
5763 }
5764 *input_line_pointer = c;
5765 input_line_pointer = save;
5766 }
5767 return r;
5768}
5769
5770int
5771i386_parse_name (char *name, expressionS *e, char *nextcharP)
5772{
5773 const reg_entry *r;
5774 char *end = input_line_pointer;
5775
5776 *end = *nextcharP;
5777 r = parse_register (name, &input_line_pointer);
5778 if (r && end <= input_line_pointer)
5779 {
5780 *nextcharP = *input_line_pointer;
5781 *input_line_pointer = 0;
5782 e->X_op = O_register;
5783 e->X_add_number = r - i386_regtab;
5784 return 1;
5785 }
5786 input_line_pointer = end;
5787 *end = 0;
5788 return 0;
5789}
5790
5791void
5792md_operand (expressionS *e)
5793{
5794 if (*input_line_pointer == REGISTER_PREFIX)
5795 {
5796 char *end;
5797 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5798
5799 if (r)
5800 {
5801 e->X_op = O_register;
5802 e->X_add_number = r - i386_regtab;
5803 input_line_pointer = end;
5804 }
5805 }
5806}
5807
252b5132 5808\f
4cc782b5 5809#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5810const char *md_shortopts = "kVQ:sqn";
252b5132 5811#else
12b55ccc 5812const char *md_shortopts = "qn";
252b5132 5813#endif
6e0b89ee 5814
3e73aa7c 5815#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5816#define OPTION_64 (OPTION_MD_BASE + 1)
5817#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 5818#define OPTION_MARCH (OPTION_MD_BASE + 3)
5819#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 5820
99ad8390
NC		 5821struct option md_longopts[] =
5822{
3e73aa7c 5823 {"32", no_argument, NULL, OPTION_32},
99ad8390 5824#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 5825 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5826#endif
b3b91714 5827 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 5828 {"march", required_argument, NULL, OPTION_MARCH},
5829 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 5830 {NULL, no_argument, NULL, 0}
5831};
5832size_t md_longopts_size = sizeof (md_longopts);
5833
5834int
9103f4f4 5835md_parse_option (int c, char *arg)
252b5132 5836{
9103f4f4
L		 5837 unsigned int i;
5838
252b5132
RH		 5839 switch (c)
5840 {
12b55ccc
L		 5841 case 'n':
5842 optimize_align_code = 0;
5843 break;
5844
a38cf1db
AM		 5845 case 'q':
5846 quiet_warnings = 1;
252b5132
RH		 5847 break;
5848
5849#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5850 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5851 should be emitted or not. FIXME: Not implemented. */
5852 case 'Q':
252b5132
RH		 5853 break;
5854
5855 /* -V: SVR4 argument to print version ID. */
5856 case 'V':
5857 print_version_id ();
5858 break;
5859
a38cf1db
AM		 5860 /* -k: Ignore for FreeBSD compatibility. */
5861 case 'k':
252b5132 5862 break;
4cc782b5
ILT		 5863
5864 case 's':
5865 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5866 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5867 break;
99ad8390
NC		 5868#endif
5869#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 5870 case OPTION_64:
5871 {
5872 const char **list, **l;
5873
3e73aa7c
JH		 5874 list = bfd_target_list ();
5875 for (l = list; *l != NULL; l++)
8620418b 5876 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 5877 || strcmp (*l, "coff-x86-64") == 0
5878 || strcmp (*l, "pe-x86-64") == 0
5879 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 5880 {
5881 default_arch = "x86_64";
5882 break;
5883 }
3e73aa7c 5884 if (*l == NULL)
6e0b89ee 5885 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5886 free (list);
5887 }
5888 break;
5889#endif
252b5132 5890
6e0b89ee
AM		 5891 case OPTION_32:
5892 default_arch = "i386";
5893 break;
5894
b3b91714
AM		 5895 case OPTION_DIVIDE:
5896#ifdef SVR4_COMMENT_CHARS
5897 {
5898 char *n, *t;
5899 const char *s;
5900
5901 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5902 t = n;
5903 for (s = i386_comment_chars; *s != '\0'; s++)
5904 if (*s != '/')
5905 *t++ = *s;
5906 *t = '\0';
5907 i386_comment_chars = n;
5908 }
5909#endif
5910 break;
5911
9103f4f4
L		 5912 case OPTION_MARCH:
5913 if (*arg == '.')
5914 as_fatal (_("Invalid -march= option: `%s'"), arg);
5915 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5916 {
5917 if (strcmp (arg, cpu_arch [i].name) == 0)
5918 {
ccc9c027 5919 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 5920 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 5921 if (!cpu_arch_tune_set)
5922 {
5923 cpu_arch_tune = cpu_arch_isa;
5924 cpu_arch_tune_flags = cpu_arch_isa_flags;
5925 }
9103f4f4
L		 5926 break;
5927 }
5928 }
5929 if (i >= ARRAY_SIZE (cpu_arch))
5930 as_fatal (_("Invalid -march= option: `%s'"), arg);
5931 break;
5932
5933 case OPTION_MTUNE:
5934 if (*arg == '.')
5935 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5936 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5937 {
5938 if (strcmp (arg, cpu_arch [i].name) == 0)
5939 {
ccc9c027 5940 cpu_arch_tune_set = 1;
9103f4f4
L		 5941 cpu_arch_tune = cpu_arch [i].type;
5942 cpu_arch_tune_flags = cpu_arch[i].flags;
5943 break;
5944 }
5945 }
5946 if (i >= ARRAY_SIZE (cpu_arch))
5947 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5948 break;
5949
252b5132
RH		 5950 default:
5951 return 0;
5952 }
5953 return 1;
5954}
5955
5956void
5957md_show_usage (stream)
5958 FILE *stream;
5959{
4cc782b5
ILT		 5960#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5961 fprintf (stream, _("\
a38cf1db
AM		 5962 -Q ignored\n\
5963 -V print assembler version number\n\
b3b91714
AM		 5964 -k ignored\n"));
5965#endif
5966 fprintf (stream, _("\
12b55ccc 5967 -n Do not optimize code alignment\n\
b3b91714
AM		 5968 -q quieten some warnings\n"));
5969#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5970 fprintf (stream, _("\
a38cf1db 5971 -s ignored\n"));
b3b91714 5972#endif
751d281c
L		 5973#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5974 fprintf (stream, _("\
5975 --32/--64 generate 32bit/64bit code\n"));
5976#endif
b3b91714
AM		 5977#ifdef SVR4_COMMENT_CHARS
5978 fprintf (stream, _("\
5979 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 5980#else
5981 fprintf (stream, _("\
b3b91714 5982 --divide ignored\n"));
4cc782b5 5983#endif
9103f4f4
L		 5984 fprintf (stream, _("\
5985 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
5986 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
ef05d495 5987 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 5988
252b5132
RH		 5989}
5990
99ad8390
NC		 5991#if defined(TE_PEP)
5992const char *
5993x86_64_target_format (void)
5994{
5995 if (strcmp (default_arch, "x86_64") == 0)
5996 {
5997 set_code_flag (CODE_64BIT);
5998 return COFF_TARGET_FORMAT;
5999 }
6000 else if (strcmp (default_arch, "i386") == 0)
6001 {
6002 set_code_flag (CODE_32BIT);
6003 return "coff-i386";
6004 }
6005
6006 as_fatal (_("Unknown architecture"));
6007 return NULL;
6008}
6009#endif
6010
3e73aa7c
JH		 6011#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6012 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 6013
6014/* Pick the target format to use. */
6015
47926f60 6016const char *
e3bb37b5 6017i386_target_format (void)
252b5132 6018{
3e73aa7c 6019 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 6020 {
6021 set_code_flag (CODE_64BIT);
6022 if (cpu_arch_isa_flags == 0)
d32cad65 6023 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
9103f4f4
L		 6024 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6025 |CpuSSE|CpuSSE2;
ccc9c027 6026 if (cpu_arch_tune_flags == 0)
d32cad65 6027 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
ccc9c027
L		 6028 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6029 |CpuSSE|CpuSSE2;
9103f4f4 6030 }
3e73aa7c 6031 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 6032 {
6033 set_code_flag (CODE_32BIT);
6034 if (cpu_arch_isa_flags == 0)
d32cad65 6035 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
ccc9c027 6036 if (cpu_arch_tune_flags == 0)
d32cad65 6037 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
9103f4f4 6038 }
3e73aa7c
JH		 6039 else
6040 as_fatal (_("Unknown architecture"));
252b5132
RH		 6041 switch (OUTPUT_FLAVOR)
6042 {
4c63da97
AM		 6043#ifdef OBJ_MAYBE_AOUT
6044 case bfd_target_aout_flavour:
47926f60 6045 return AOUT_TARGET_FORMAT;
4c63da97
AM		 6046#endif
6047#ifdef OBJ_MAYBE_COFF
252b5132
RH		 6048 case bfd_target_coff_flavour:
6049 return "coff-i386";
4c63da97 6050#endif
3e73aa7c 6051#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 6052 case bfd_target_elf_flavour:
3e73aa7c 6053 {
e5cb08ac 6054 if (flag_code == CODE_64BIT)
4fa24527
JB		 6055 {
6056 object_64bit = 1;
6057 use_rela_relocations = 1;
6058 }
9d7cbccd 6059 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6060 }
4c63da97 6061#endif
252b5132
RH		 6062 default:
6063 abort ();
6064 return NULL;
6065 }
6066}
6067
47926f60 6068#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 6069
6070#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 6071void
6072i386_elf_emit_arch_note (void)
a847613f 6073{
718ddfc0 6074 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 6075 {
6076 char *p;
6077 asection *seg = now_seg;
6078 subsegT subseg = now_subseg;
6079 Elf_Internal_Note i_note;
6080 Elf_External_Note e_note;
6081 asection *note_secp;
6082 int len;
6083
6084 /* Create the .note section. */
6085 note_secp = subseg_new (".note", 0);
6086 bfd_set_section_flags (stdoutput,
6087 note_secp,
6088 SEC_HAS_CONTENTS | SEC_READONLY);
6089
6090 /* Process the arch string. */
6091 len = strlen (cpu_arch_name);
6092
6093 i_note.namesz = len + 1;
6094 i_note.descsz = 0;
6095 i_note.type = NT_ARCH;
6096 p = frag_more (sizeof (e_note.namesz));
6097 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6098 p = frag_more (sizeof (e_note.descsz));
6099 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6100 p = frag_more (sizeof (e_note.type));
6101 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6102 p = frag_more (len + 1);
6103 strcpy (p, cpu_arch_name);
6104
6105 frag_align (2, 0, 0);
6106
6107 subseg_set (seg, subseg);
6108 }
6109}
6110#endif
252b5132 6111\f
252b5132
RH		 6112symbolS *
6113md_undefined_symbol (name)
6114 char *name;
6115{
18dc2407
ILT		 6116 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6117 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6118 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6119 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6120 {
6121 if (!GOT_symbol)
6122 {
6123 if (symbol_find (name))
6124 as_bad (_("GOT already in symbol table"));
6125 GOT_symbol = symbol_new (name, undefined_section,
6126 (valueT) 0, &zero_address_frag);
6127 };
6128 return GOT_symbol;
6129 }
252b5132
RH		 6130 return 0;
6131}
6132
6133/* Round up a section size to the appropriate boundary. */
47926f60 6134
252b5132
RH		 6135valueT
6136md_section_align (segment, size)
ab9da554 6137 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6138 valueT size;
6139{
4c63da97
AM		 6140#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6141 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6142 {
6143 /* For a.out, force the section size to be aligned. If we don't do
6144 this, BFD will align it for us, but it will not write out the
6145 final bytes of the section. This may be a bug in BFD, but it is
6146 easier to fix it here since that is how the other a.out targets
6147 work. */
6148 int align;
6149
6150 align = bfd_get_section_alignment (stdoutput, segment);
6151 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6152 }
252b5132
RH		 6153#endif
6154
6155 return size;
6156}
6157
6158/* On the i386, PC-relative offsets are relative to the start of the
6159 next instruction. That is, the address of the offset, plus its
6160 size, since the offset is always the last part of the insn. */
6161
6162long
e3bb37b5 6163md_pcrel_from (fixS *fixP)
252b5132
RH		 6164{
6165 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6166}
6167
6168#ifndef I386COFF
6169
6170static void
e3bb37b5 6171s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 6172{
29b0f896 6173 int temp;
252b5132 6174
8a75718c
JB		 6175#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6176 if (IS_ELF)
6177 obj_elf_section_change_hook ();
6178#endif
252b5132
RH		 6179 temp = get_absolute_expression ();
6180 subseg_set (bss_section, (subsegT) temp);
6181 demand_empty_rest_of_line ();
6182}
6183
6184#endif
6185
252b5132 6186void
e3bb37b5 6187i386_validate_fix (fixS *fixp)
252b5132
RH		 6188{
6189 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6190 {
23df1078
JH		 6191 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6192 {
4fa24527 6193 if (!object_64bit)
23df1078
JH		 6194 abort ();
6195 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6196 }
6197 else
6198 {
4fa24527 6199 if (!object_64bit)
d6ab8113
JB		 6200 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6201 else
6202 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6203 }
252b5132
RH		 6204 fixp->fx_subsy = 0;
6205 }
6206}
6207
252b5132
RH		 6208arelent *
6209tc_gen_reloc (section, fixp)
ab9da554 6210 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6211 fixS *fixp;
6212{
6213 arelent *rel;
6214 bfd_reloc_code_real_type code;
6215
6216 switch (fixp->fx_r_type)
6217 {
3e73aa7c
JH		 6218 case BFD_RELOC_X86_64_PLT32:
6219 case BFD_RELOC_X86_64_GOT32:
6220 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6221 case BFD_RELOC_386_PLT32:
6222 case BFD_RELOC_386_GOT32:
6223 case BFD_RELOC_386_GOTOFF:
6224 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 6225 case BFD_RELOC_386_TLS_GD:
6226 case BFD_RELOC_386_TLS_LDM:
6227 case BFD_RELOC_386_TLS_LDO_32:
6228 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6229 case BFD_RELOC_386_TLS_IE:
6230 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 6231 case BFD_RELOC_386_TLS_LE_32:
6232 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 6233 case BFD_RELOC_386_TLS_GOTDESC:
6234 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 6235 case BFD_RELOC_X86_64_TLSGD:
6236 case BFD_RELOC_X86_64_TLSLD:
6237 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6238 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 6239 case BFD_RELOC_X86_64_GOTTPOFF:
6240 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 6241 case BFD_RELOC_X86_64_TPOFF64:
6242 case BFD_RELOC_X86_64_GOTOFF64:
6243 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 6244 case BFD_RELOC_X86_64_GOT64:
6245 case BFD_RELOC_X86_64_GOTPCREL64:
6246 case BFD_RELOC_X86_64_GOTPC64:
6247 case BFD_RELOC_X86_64_GOTPLT64:
6248 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 6249 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6250 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 6251 case BFD_RELOC_RVA:
6252 case BFD_RELOC_VTABLE_ENTRY:
6253 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 6254#ifdef TE_PE
6255 case BFD_RELOC_32_SECREL:
6256#endif
252b5132
RH		 6257 code = fixp->fx_r_type;
6258 break;
dbbaec26
L		 6259 case BFD_RELOC_X86_64_32S:
6260 if (!fixp->fx_pcrel)
6261 {
6262 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6263 code = fixp->fx_r_type;
6264 break;
6265 }
252b5132 6266 default:
93382f6d 6267 if (fixp->fx_pcrel)
252b5132 6268 {
93382f6d
AM		 6269 switch (fixp->fx_size)
6270 {
6271 default:
b091f402
AM		 6272 as_bad_where (fixp->fx_file, fixp->fx_line,
6273 _("can not do %d byte pc-relative relocation"),
6274 fixp->fx_size);
93382f6d
AM		 6275 code = BFD_RELOC_32_PCREL;
6276 break;
6277 case 1: code = BFD_RELOC_8_PCREL; break;
6278 case 2: code = BFD_RELOC_16_PCREL; break;
6279 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 6280#ifdef BFD64
6281 case 8: code = BFD_RELOC_64_PCREL; break;
6282#endif
93382f6d
AM		 6283 }
6284 }
6285 else
6286 {
6287 switch (fixp->fx_size)
6288 {
6289 default:
b091f402
AM		 6290 as_bad_where (fixp->fx_file, fixp->fx_line,
6291 _("can not do %d byte relocation"),
6292 fixp->fx_size);
93382f6d
AM		 6293 code = BFD_RELOC_32;
6294 break;
6295 case 1: code = BFD_RELOC_8; break;
6296 case 2: code = BFD_RELOC_16; break;
6297 case 4: code = BFD_RELOC_32; break;
937149dd 6298#ifdef BFD64
3e73aa7c 6299 case 8: code = BFD_RELOC_64; break;
937149dd 6300#endif
93382f6d 6301 }
252b5132
RH		 6302 }
6303 break;
6304 }
252b5132 6305
d182319b
JB		 6306 if ((code == BFD_RELOC_32
6307 || code == BFD_RELOC_32_PCREL
6308 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 6309 && GOT_symbol
6310 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 6311 {
4fa24527 6312 if (!object_64bit)
d6ab8113
JB		 6313 code = BFD_RELOC_386_GOTPC;
6314 else
6315 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 6316 }
7b81dfbb
AJ		 6317 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6318 && GOT_symbol
6319 && fixp->fx_addsy == GOT_symbol)
6320 {
6321 code = BFD_RELOC_X86_64_GOTPC64;
6322 }
252b5132
RH		 6323
6324 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 6325 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6326 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 6327
6328 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 6329
3e73aa7c
JH		 6330 if (!use_rela_relocations)
6331 {
6332 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6333 vtable entry to be used in the relocation's section offset. */
6334 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6335 rel->address = fixp->fx_offset;
252b5132 6336
c6682705 6337 rel->addend = 0;
3e73aa7c
JH		 6338 }
6339 /* Use the rela in 64bit mode. */
252b5132 6340 else
3e73aa7c 6341 {
062cd5e7
AS		 6342 if (!fixp->fx_pcrel)
6343 rel->addend = fixp->fx_offset;
6344 else
6345 switch (code)
6346 {
6347 case BFD_RELOC_X86_64_PLT32:
6348 case BFD_RELOC_X86_64_GOT32:
6349 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 6350 case BFD_RELOC_X86_64_TLSGD:
6351 case BFD_RELOC_X86_64_TLSLD:
6352 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 6353 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6354 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 6355 rel->addend = fixp->fx_offset - fixp->fx_size;
6356 break;
6357 default:
6358 rel->addend = (section->vma
6359 - fixp->fx_size
6360 + fixp->fx_addnumber
6361 + md_pcrel_from (fixp));
6362 break;
6363 }
3e73aa7c
JH		 6364 }
6365
252b5132
RH		 6366 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6367 if (rel->howto == NULL)
6368 {
6369 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 6370 _("cannot represent relocation type %s"),
252b5132
RH		 6371 bfd_get_reloc_code_name (code));
6372 /* Set howto to a garbage value so that we can keep going. */
6373 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6374 assert (rel->howto != NULL);
6375 }
6376
6377 return rel;
6378}
6379
64a0c779
DN		 6380\f
6381/* Parse operands using Intel syntax. This implements a recursive descent
6382 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6383 Programmer's Guide.
6384
6385 FIXME: We do not recognize the full operand grammar defined in the MASM
6386 documentation. In particular, all the structure/union and
6387 high-level macro operands are missing.
6388
6389 Uppercase words are terminals, lower case words are non-terminals.
6390 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6391 bars '|' denote choices. Most grammar productions are implemented in
6392 functions called 'intel_<production>'.
6393
6394 Initial production is 'expr'.
6395
9306ca4a 6396 addOp + | -
64a0c779
DN		 6397
6398 alpha [a-zA-Z]
6399
9306ca4a
JB		 6400 binOp & | AND | \| | OR | ^ | XOR
6401
64a0c779
DN		 6402 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6403
6404 constant digits [[ radixOverride ]]
6405
9306ca4a 6406 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 6407
6408 digits decdigit
b77a7acd
AJ		 6409 | digits decdigit
6410 | digits hexdigit
64a0c779
DN		 6411
6412 decdigit [0-9]
6413
9306ca4a
JB		 6414 e04 e04 addOp e05
6415 | e05
6416
6417 e05 e05 binOp e06
b77a7acd 6418 | e06
64a0c779
DN		 6419
6420 e06 e06 mulOp e09
b77a7acd 6421 | e09
64a0c779
DN		 6422
6423 e09 OFFSET e10
a724f0f4
JB		 6424 | SHORT e10
6425 | + e10
6426 | - e10
9306ca4a
JB		 6427 | ~ e10
6428 | NOT e10
64a0c779
DN		 6429 | e09 PTR e10
6430 | e09 : e10
6431 | e10
6432
6433 e10 e10 [ expr ]
b77a7acd 6434 | e11
64a0c779
DN		 6435
6436 e11 ( expr )
b77a7acd 6437 | [ expr ]
64a0c779
DN		 6438 | constant
6439 | dataType
6440 | id
6441 | $
6442 | register
6443
a724f0f4 6444 => expr expr cmpOp e04
9306ca4a 6445 | e04
64a0c779
DN		 6446
6447 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 6448 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 6449
6450 hexdigit a | b | c | d | e | f
b77a7acd 6451 | A | B | C | D | E | F
64a0c779
DN		 6452
6453 id alpha
b77a7acd 6454 | id alpha
64a0c779
DN		 6455 | id decdigit
6456
9306ca4a 6457 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 6458
6459 quote " | '
6460
6461 register specialRegister
b77a7acd 6462 | gpRegister
64a0c779
DN		 6463 | byteRegister
6464
6465 segmentRegister CS | DS | ES | FS | GS | SS
6466
9306ca4a 6467 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 6468 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 6469 | TR3 | TR4 | TR5 | TR6 | TR7
6470
64a0c779
DN		 6471 We simplify the grammar in obvious places (e.g., register parsing is
6472 done by calling parse_register) and eliminate immediate left recursion
6473 to implement a recursive-descent parser.
6474
a724f0f4
JB		 6475 expr e04 expr'
6476
6477 expr' cmpOp e04 expr'
6478 | Empty
9306ca4a
JB		 6479
6480 e04 e05 e04'
6481
6482 e04' addOp e05 e04'
6483 | Empty
64a0c779
DN		 6484
6485 e05 e06 e05'
6486
9306ca4a 6487 e05' binOp e06 e05'
b77a7acd 6488 | Empty
64a0c779
DN		 6489
6490 e06 e09 e06'
6491
6492 e06' mulOp e09 e06'
b77a7acd 6493 | Empty
64a0c779
DN		 6494
6495 e09 OFFSET e10 e09'
a724f0f4
JB		 6496 | SHORT e10'
6497 | + e10'
6498 | - e10'
6499 | ~ e10'
6500 | NOT e10'
b77a7acd 6501 | e10 e09'
64a0c779
DN		 6502
6503 e09' PTR e10 e09'
b77a7acd 6504 | : e10 e09'
64a0c779
DN		 6505 | Empty
6506
6507 e10 e11 e10'
6508
6509 e10' [ expr ] e10'
b77a7acd 6510 | Empty
64a0c779
DN		 6511
6512 e11 ( expr )
b77a7acd 6513 | [ expr ]
64a0c779
DN		 6514 | BYTE
6515 | WORD
6516 | DWORD
9306ca4a 6517 | FWORD
64a0c779 6518 | QWORD
9306ca4a
JB		 6519 | TBYTE
6520 | OWORD
6521 | XMMWORD
64a0c779
DN		 6522 | .
6523 | $
6524 | register
6525 | id
6526 | constant */
6527
6528/* Parsing structure for the intel syntax parser. Used to implement the
6529 semantic actions for the operand grammar. */
6530struct intel_parser_s
6531 {
6532 char *op_string; /* The string being parsed. */
6533 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6534 int op_modifier; /* Operand modifier. */
64a0c779 6535 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 6536 int in_offset; /* >=1 if parsing operand of offset. */
6537 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6538 const reg_entry *reg; /* Last register reference found. */
6539 char *disp; /* Displacement string being built. */
a724f0f4 6540 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6541 };
6542
6543static struct intel_parser_s intel_parser;
6544
6545/* Token structure for parsing intel syntax. */
6546struct intel_token
6547 {
6548 int code; /* Token code. */
6549 const reg_entry *reg; /* Register entry for register tokens. */
6550 char *str; /* String representation. */
6551 };
6552
6553static struct intel_token cur_token, prev_token;
6554
50705ef4
AM		 6555/* Token codes for the intel parser. Since T_SHORT is already used
6556 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6557#define T_NIL -1
6558#define T_CONST 1
6559#define T_REG 2
6560#define T_BYTE 3
6561#define T_WORD 4
9306ca4a
JB		 6562#define T_DWORD 5
6563#define T_FWORD 6
6564#define T_QWORD 7
6565#define T_TBYTE 8
6566#define T_XMMWORD 9
50705ef4 6567#undef T_SHORT
9306ca4a
JB		 6568#define T_SHORT 10
6569#define T_OFFSET 11
6570#define T_PTR 12
6571#define T_ID 13
6572#define T_SHL 14
6573#define T_SHR 15
64a0c779
DN		 6574
6575/* Prototypes for intel parser functions. */
e3bb37b5
L		 6576static int intel_match_token (int);
6577static void intel_putback_token (void);
6578static void intel_get_token (void);
6579static int intel_expr (void);
6580static int intel_e04 (void);
6581static int intel_e05 (void);
6582static int intel_e06 (void);
6583static int intel_e09 (void);
6584static int intel_e10 (void);
6585static int intel_e11 (void);
64a0c779 6586
64a0c779 6587static int
e3bb37b5 6588i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 6589{
6590 int ret;
6591 char *p;
6592
a724f0f4
JB		 6593 p = intel_parser.op_string = xstrdup (operand_string);
6594 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6595
6596 for (;;)
64a0c779 6597 {
a724f0f4
JB		 6598 /* Initialize token holders. */
6599 cur_token.code = prev_token.code = T_NIL;
6600 cur_token.reg = prev_token.reg = NULL;
6601 cur_token.str = prev_token.str = NULL;
6602
6603 /* Initialize parser structure. */
6604 intel_parser.got_a_float = got_a_float;
6605 intel_parser.op_modifier = 0;
6606 intel_parser.is_mem = 0;
6607 intel_parser.in_offset = 0;
6608 intel_parser.in_bracket = 0;
6609 intel_parser.reg = NULL;
6610 intel_parser.disp[0] = '\0';
6611 intel_parser.next_operand = NULL;
6612
6613 /* Read the first token and start the parser. */
6614 intel_get_token ();
6615 ret = intel_expr ();
6616
6617 if (!ret)
6618 break;
6619
9306ca4a
JB		 6620 if (cur_token.code != T_NIL)
6621 {
6622 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6623 current_templates->start->name, cur_token.str);
6624 ret = 0;
6625 }
64a0c779
DN		 6626 /* If we found a memory reference, hand it over to i386_displacement
6627 to fill in the rest of the operand fields. */
9306ca4a 6628 else if (intel_parser.is_mem)
64a0c779
DN		 6629 {
6630 if ((i.mem_operands == 1
6631 && (current_templates->start->opcode_modifier & IsString) == 0)
6632 || i.mem_operands == 2)
6633 {
6634 as_bad (_("too many memory references for '%s'"),
6635 current_templates->start->name);
6636 ret = 0;
6637 }
6638 else
6639 {
6640 char *s = intel_parser.disp;
6641 i.mem_operands++;
6642
a724f0f4
JB		 6643 if (!quiet_warnings && intel_parser.is_mem < 0)
6644 /* See the comments in intel_bracket_expr. */
6645 as_warn (_("Treating `%s' as memory reference"), operand_string);
6646
64a0c779
DN		 6647 /* Add the displacement expression. */
6648 if (*s != '\0')
a4622f40
AM		 6649 ret = i386_displacement (s, s + strlen (s));
6650 if (ret)
a724f0f4
JB		 6651 {
6652 /* Swap base and index in 16-bit memory operands like
6653 [si+bx]. Since i386_index_check is also used in AT&T
6654 mode we have to do that here. */
6655 if (i.base_reg
6656 && i.index_reg
6657 && (i.base_reg->reg_type & Reg16)
6658 && (i.index_reg->reg_type & Reg16)
6659 && i.base_reg->reg_num >= 6
6660 && i.index_reg->reg_num < 6)
6661 {
6662 const reg_entry *base = i.index_reg;
6663
6664 i.index_reg = i.base_reg;
6665 i.base_reg = base;
6666 }
6667 ret = i386_index_check (operand_string);
6668 }
64a0c779
DN		 6669 }
6670 }
6671
6672 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6673 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6674 || intel_parser.reg == NULL)
6675 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6676
6677 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6678 ret = 0;
6679 if (!ret || !intel_parser.next_operand)
6680 break;
6681 intel_parser.op_string = intel_parser.next_operand;
6682 this_operand = i.operands++;
64a0c779
DN		 6683 }
6684
6685 free (p);
6686 free (intel_parser.disp);
6687
6688 return ret;
6689}
6690
a724f0f4
JB		 6691#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6692
6693/* expr e04 expr'
6694
6695 expr' cmpOp e04 expr'
6696 | Empty */
64a0c779 6697static int
e3bb37b5 6698intel_expr (void)
64a0c779 6699{
a724f0f4
JB		 6700 /* XXX Implement the comparison operators. */
6701 return intel_e04 ();
9306ca4a
JB		 6702}
6703
a724f0f4 6704/* e04 e05 e04'
9306ca4a 6705
a724f0f4 6706 e04' addOp e05 e04'
9306ca4a
JB		 6707 | Empty */
6708static int
e3bb37b5 6709intel_e04 (void)
9306ca4a 6710{
a724f0f4 6711 int nregs = -1;
9306ca4a 6712
a724f0f4 6713 for (;;)
9306ca4a 6714 {
a724f0f4
JB		 6715 if (!intel_e05())
6716 return 0;
9306ca4a 6717
a724f0f4
JB		 6718 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6719 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6720
a724f0f4
JB		 6721 if (cur_token.code == '+')
6722 nregs = -1;
6723 else if (cur_token.code == '-')
6724 nregs = NUM_ADDRESS_REGS;
6725 else
6726 return 1;
64a0c779 6727
a724f0f4
JB		 6728 strcat (intel_parser.disp, cur_token.str);
6729 intel_match_token (cur_token.code);
6730 }
64a0c779
DN		 6731}
6732
64a0c779
DN		 6733/* e05 e06 e05'
6734
9306ca4a 6735 e05' binOp e06 e05'
64a0c779
DN		 6736 | Empty */
6737static int
e3bb37b5 6738intel_e05 (void)
64a0c779 6739{
a724f0f4 6740 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6741
a724f0f4 6742 for (;;)
64a0c779 6743 {
a724f0f4
JB		 6744 if (!intel_e06())
6745 return 0;
6746
6747 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6748 {
6749 char str[2];
6750
6751 str[0] = cur_token.code;
6752 str[1] = 0;
6753 strcat (intel_parser.disp, str);
6754 }
6755 else
6756 break;
9306ca4a 6757
64a0c779
DN		 6758 intel_match_token (cur_token.code);
6759
a724f0f4
JB		 6760 if (nregs < 0)
6761 nregs = ~nregs;
64a0c779 6762 }
a724f0f4
JB		 6763 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6764 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6765 return 1;
4a1805b1 6766}
64a0c779
DN		 6767
6768/* e06 e09 e06'
6769
6770 e06' mulOp e09 e06'
b77a7acd 6771 | Empty */
64a0c779 6772static int
e3bb37b5 6773intel_e06 (void)
64a0c779 6774{
a724f0f4 6775 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6776
a724f0f4 6777 for (;;)
64a0c779 6778 {
a724f0f4
JB		 6779 if (!intel_e09())
6780 return 0;
9306ca4a 6781
a724f0f4
JB		 6782 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6783 {
6784 char str[2];
9306ca4a 6785
a724f0f4
JB		 6786 str[0] = cur_token.code;
6787 str[1] = 0;
6788 strcat (intel_parser.disp, str);
6789 }
6790 else if (cur_token.code == T_SHL)
6791 strcat (intel_parser.disp, "<<");
6792 else if (cur_token.code == T_SHR)
6793 strcat (intel_parser.disp, ">>");
6794 else
6795 break;
9306ca4a 6796
64e74474 6797 intel_match_token (cur_token.code);
64a0c779 6798
a724f0f4
JB		 6799 if (nregs < 0)
6800 nregs = ~nregs;
64a0c779 6801 }
a724f0f4
JB		 6802 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6803 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6804 return 1;
64a0c779
DN		 6805}
6806
a724f0f4
JB		 6807/* e09 OFFSET e09
6808 | SHORT e09
6809 | + e09
6810 | - e09
6811 | ~ e09
6812 | NOT e09
9306ca4a
JB		 6813 | e10 e09'
6814
64a0c779 6815 e09' PTR e10 e09'
b77a7acd 6816 | : e10 e09'
64a0c779
DN		 6817 | Empty */
6818static int
e3bb37b5 6819intel_e09 (void)
64a0c779 6820{
a724f0f4
JB		 6821 int nregs = ~NUM_ADDRESS_REGS;
6822 int in_offset = 0;
6823
6824 for (;;)
64a0c779 6825 {
a724f0f4
JB		 6826 /* Don't consume constants here. */
6827 if (cur_token.code == '+' || cur_token.code == '-')
6828 {
6829 /* Need to look one token ahead - if the next token
6830 is a constant, the current token is its sign. */
6831 int next_code;
6832
6833 intel_match_token (cur_token.code);
6834 next_code = cur_token.code;
6835 intel_putback_token ();
6836 if (next_code == T_CONST)
6837 break;
6838 }
6839
6840 /* e09 OFFSET e09 */
6841 if (cur_token.code == T_OFFSET)
6842 {
6843 if (!in_offset++)
6844 ++intel_parser.in_offset;
6845 }
6846
6847 /* e09 SHORT e09 */
6848 else if (cur_token.code == T_SHORT)
6849 intel_parser.op_modifier |= 1 << T_SHORT;
6850
6851 /* e09 + e09 */
6852 else if (cur_token.code == '+')
6853 strcat (intel_parser.disp, "+");
6854
6855 /* e09 - e09
6856 | ~ e09
6857 | NOT e09 */
6858 else if (cur_token.code == '-' || cur_token.code == '~')
6859 {
6860 char str[2];
64a0c779 6861
a724f0f4
JB		 6862 if (nregs < 0)
6863 nregs = ~nregs;
6864 str[0] = cur_token.code;
6865 str[1] = 0;
6866 strcat (intel_parser.disp, str);
6867 }
6868
6869 /* e09 e10 e09' */
6870 else
6871 break;
6872
6873 intel_match_token (cur_token.code);
64a0c779
DN		 6874 }
6875
a724f0f4 6876 for (;;)
9306ca4a 6877 {
a724f0f4
JB		 6878 if (!intel_e10 ())
6879 return 0;
9306ca4a 6880
a724f0f4
JB		 6881 /* e09' PTR e10 e09' */
6882 if (cur_token.code == T_PTR)
6883 {
6884 char suffix;
9306ca4a 6885
a724f0f4
JB		 6886 if (prev_token.code == T_BYTE)
6887 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6888
a724f0f4
JB		 6889 else if (prev_token.code == T_WORD)
6890 {
6891 if (current_templates->start->name[0] == 'l'
6892 && current_templates->start->name[2] == 's'
6893 && current_templates->start->name[3] == 0)
6894 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6895 else if (intel_parser.got_a_float == 2) /* "fi..." */
6896 suffix = SHORT_MNEM_SUFFIX;
6897 else
6898 suffix = WORD_MNEM_SUFFIX;
6899 }
64a0c779 6900
a724f0f4
JB		 6901 else if (prev_token.code == T_DWORD)
6902 {
6903 if (current_templates->start->name[0] == 'l'
6904 && current_templates->start->name[2] == 's'
6905 && current_templates->start->name[3] == 0)
6906 suffix = WORD_MNEM_SUFFIX;
6907 else if (flag_code == CODE_16BIT
6908 && (current_templates->start->opcode_modifier
435acd52 6909 & (Jump | JumpDword)))
a724f0f4
JB		 6910 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6911 else if (intel_parser.got_a_float == 1) /* "f..." */
6912 suffix = SHORT_MNEM_SUFFIX;
6913 else
6914 suffix = LONG_MNEM_SUFFIX;
6915 }
9306ca4a 6916
a724f0f4
JB		 6917 else if (prev_token.code == T_FWORD)
6918 {
6919 if (current_templates->start->name[0] == 'l'
6920 && current_templates->start->name[2] == 's'
6921 && current_templates->start->name[3] == 0)
6922 suffix = LONG_MNEM_SUFFIX;
6923 else if (!intel_parser.got_a_float)
6924 {
6925 if (flag_code == CODE_16BIT)
6926 add_prefix (DATA_PREFIX_OPCODE);
6927 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6928 }
6929 else
6930 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6931 }
64a0c779 6932
a724f0f4
JB		 6933 else if (prev_token.code == T_QWORD)
6934 {
6935 if (intel_parser.got_a_float == 1) /* "f..." */
6936 suffix = LONG_MNEM_SUFFIX;
6937 else
6938 suffix = QWORD_MNEM_SUFFIX;
6939 }
64a0c779 6940
a724f0f4
JB		 6941 else if (prev_token.code == T_TBYTE)
6942 {
6943 if (intel_parser.got_a_float == 1)
6944 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6945 else
6946 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6947 }
9306ca4a 6948
a724f0f4 6949 else if (prev_token.code == T_XMMWORD)
9306ca4a 6950 {
a724f0f4
JB		 6951 /* XXX ignored for now, but accepted since gcc uses it */
6952 suffix = 0;
9306ca4a 6953 }
64a0c779 6954
f16b83df 6955 else
a724f0f4
JB		 6956 {
6957 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6958 return 0;
6959 }
6960
435acd52
JB		 6961 /* Operands for jump/call using 'ptr' notation denote absolute
6962 addresses. */
6963 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6964 i.types[this_operand] |= JumpAbsolute;
6965
a724f0f4
JB		 6966 if (current_templates->start->base_opcode == 0x8d /* lea */)
6967 ;
6968 else if (!i.suffix)
6969 i.suffix = suffix;
6970 else if (i.suffix != suffix)
6971 {
6972 as_bad (_("Conflicting operand modifiers"));
6973 return 0;
6974 }
64a0c779 6975
9306ca4a
JB		 6976 }
6977
a724f0f4
JB		 6978 /* e09' : e10 e09' */
6979 else if (cur_token.code == ':')
9306ca4a 6980 {
a724f0f4
JB		 6981 if (prev_token.code != T_REG)
6982 {
6983 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6984 segment/group identifier (which we don't have), using comma
6985 as the operand separator there is even less consistent, since
6986 there all branches only have a single operand. */
6987 if (this_operand != 0
6988 || intel_parser.in_offset
6989 || intel_parser.in_bracket
6990 || (!(current_templates->start->opcode_modifier
6991 & (Jump|JumpDword|JumpInterSegment))
6992 && !(current_templates->start->operand_types[0]
6993 & JumpAbsolute)))
6994 return intel_match_token (T_NIL);
6995 /* Remember the start of the 2nd operand and terminate 1st
6996 operand here.
6997 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6998 another expression), but it gets at least the simplest case
6999 (a plain number or symbol on the left side) right. */
7000 intel_parser.next_operand = intel_parser.op_string;
7001 *--intel_parser.op_string = '\0';
7002 return intel_match_token (':');
7003 }
9306ca4a 7004 }
64a0c779 7005
a724f0f4 7006 /* e09' Empty */
64a0c779 7007 else
a724f0f4 7008 break;
64a0c779 7009
a724f0f4
JB		 7010 intel_match_token (cur_token.code);
7011
7012 }
7013
7014 if (in_offset)
7015 {
7016 --intel_parser.in_offset;
7017 if (nregs < 0)
7018 nregs = ~nregs;
7019 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 7020 {
a724f0f4 7021 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 7022 return 0;
7023 }
a724f0f4
JB		 7024 intel_parser.op_modifier |= 1 << T_OFFSET;
7025 }
9306ca4a 7026
a724f0f4
JB		 7027 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7028 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7029 return 1;
7030}
64a0c779 7031
a724f0f4 7032static int
e3bb37b5 7033intel_bracket_expr (void)
a724f0f4
JB		 7034{
7035 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7036 const char *start = intel_parser.op_string;
7037 int len;
7038
7039 if (i.op[this_operand].regs)
7040 return intel_match_token (T_NIL);
7041
7042 intel_match_token ('[');
7043
7044 /* Mark as a memory operand only if it's not already known to be an
7045 offset expression. If it's an offset expression, we need to keep
7046 the brace in. */
7047 if (!intel_parser.in_offset)
7048 {
7049 ++intel_parser.in_bracket;
435acd52
JB		 7050
7051 /* Operands for jump/call inside brackets denote absolute addresses. */
7052 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7053 i.types[this_operand] |= JumpAbsolute;
7054
a724f0f4
JB		 7055 /* Unfortunately gas always diverged from MASM in a respect that can't
7056 be easily fixed without risking to break code sequences likely to be
7057 encountered (the testsuite even check for this): MASM doesn't consider
7058 an expression inside brackets unconditionally as a memory reference.
7059 When that is e.g. a constant, an offset expression, or the sum of the
7060 two, this is still taken as a constant load. gas, however, always
7061 treated these as memory references. As a compromise, we'll try to make
7062 offset expressions inside brackets work the MASM way (since that's
7063 less likely to be found in real world code), but make constants alone
7064 continue to work the traditional gas way. In either case, issue a
7065 warning. */
7066 intel_parser.op_modifier &= ~was_offset;
64a0c779 7067 }
a724f0f4 7068 else
64e74474 7069 strcat (intel_parser.disp, "[");
a724f0f4
JB		 7070
7071 /* Add a '+' to the displacement string if necessary. */
7072 if (*intel_parser.disp != '\0'
7073 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7074 strcat (intel_parser.disp, "+");
64a0c779 7075
a724f0f4
JB		 7076 if (intel_expr ()
7077 && (len = intel_parser.op_string - start - 1,
7078 intel_match_token (']')))
64a0c779 7079 {
a724f0f4
JB		 7080 /* Preserve brackets when the operand is an offset expression. */
7081 if (intel_parser.in_offset)
7082 strcat (intel_parser.disp, "]");
7083 else
7084 {
7085 --intel_parser.in_bracket;
7086 if (i.base_reg || i.index_reg)
7087 intel_parser.is_mem = 1;
7088 if (!intel_parser.is_mem)
7089 {
7090 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7091 /* Defer the warning until all of the operand was parsed. */
7092 intel_parser.is_mem = -1;
7093 else if (!quiet_warnings)
7094 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
7095 }
7096 }
7097 intel_parser.op_modifier |= was_offset;
64a0c779 7098
a724f0f4 7099 return 1;
64a0c779 7100 }
a724f0f4 7101 return 0;
64a0c779
DN		 7102}
7103
7104/* e10 e11 e10'
7105
7106 e10' [ expr ] e10'
b77a7acd 7107 | Empty */
64a0c779 7108static int
e3bb37b5 7109intel_e10 (void)
64a0c779 7110{
a724f0f4
JB		 7111 if (!intel_e11 ())
7112 return 0;
64a0c779 7113
a724f0f4 7114 while (cur_token.code == '[')
64a0c779 7115 {
a724f0f4 7116 if (!intel_bracket_expr ())
21d6c4af 7117 return 0;
64a0c779
DN		 7118 }
7119
a724f0f4 7120 return 1;
64a0c779
DN		 7121}
7122
64a0c779 7123/* e11 ( expr )
b77a7acd 7124 | [ expr ]
64a0c779
DN		 7125 | BYTE
7126 | WORD
7127 | DWORD
9306ca4a 7128 | FWORD
64a0c779 7129 | QWORD
9306ca4a
JB		 7130 | TBYTE
7131 | OWORD
7132 | XMMWORD
4a1805b1 7133 | $
64a0c779
DN		 7134 | .
7135 | register
7136 | id
7137 | constant */
7138static int
e3bb37b5 7139intel_e11 (void)
64a0c779 7140{
a724f0f4 7141 switch (cur_token.code)
64a0c779 7142 {
a724f0f4
JB		 7143 /* e11 ( expr ) */
7144 case '(':
64a0c779
DN		 7145 intel_match_token ('(');
7146 strcat (intel_parser.disp, "(");
7147
7148 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7149 {
7150 strcat (intel_parser.disp, ")");
7151 return 1;
7152 }
a724f0f4 7153 return 0;
4a1805b1 7154
a724f0f4
JB		 7155 /* e11 [ expr ] */
7156 case '[':
a724f0f4 7157 return intel_bracket_expr ();
64a0c779 7158
a724f0f4
JB		 7159 /* e11 $
7160 | . */
7161 case '.':
64a0c779
DN		 7162 strcat (intel_parser.disp, cur_token.str);
7163 intel_match_token (cur_token.code);
21d6c4af
DN		 7164
7165 /* Mark as a memory operand only if it's not already known to be an
7166 offset expression. */
a724f0f4 7167 if (!intel_parser.in_offset)
21d6c4af 7168 intel_parser.is_mem = 1;
64a0c779
DN		 7169
7170 return 1;
64a0c779 7171
a724f0f4
JB		 7172 /* e11 register */
7173 case T_REG:
7174 {
7175 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7176
a724f0f4 7177 intel_match_token (T_REG);
64a0c779 7178
a724f0f4
JB		 7179 /* Check for segment change. */
7180 if (cur_token.code == ':')
7181 {
7182 if (!(reg->reg_type & (SReg2 | SReg3)))
7183 {
7184 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
7185 return 0;
7186 }
7187 else if (i.seg[i.mem_operands])
7188 as_warn (_("Extra segment override ignored"));
7189 else
7190 {
7191 if (!intel_parser.in_offset)
7192 intel_parser.is_mem = 1;
7193 switch (reg->reg_num)
7194 {
7195 case 0:
7196 i.seg[i.mem_operands] = &es;
7197 break;
7198 case 1:
7199 i.seg[i.mem_operands] = &cs;
7200 break;
7201 case 2:
7202 i.seg[i.mem_operands] = &ss;
7203 break;
7204 case 3:
7205 i.seg[i.mem_operands] = &ds;
7206 break;
7207 case 4:
7208 i.seg[i.mem_operands] = &fs;
7209 break;
7210 case 5:
7211 i.seg[i.mem_operands] = &gs;
7212 break;
7213 }
7214 }
7215 }
64a0c779 7216
a724f0f4
JB		 7217 /* Not a segment register. Check for register scaling. */
7218 else if (cur_token.code == '*')
7219 {
7220 if (!intel_parser.in_bracket)
7221 {
7222 as_bad (_("Register scaling only allowed in memory operands"));
7223 return 0;
7224 }
64a0c779 7225
a724f0f4
JB		 7226 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7227 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7228 else if (i.index_reg)
7229 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 7230
a724f0f4
JB		 7231 /* What follows must be a valid scale. */
7232 intel_match_token ('*');
7233 i.index_reg = reg;
7234 i.types[this_operand] |= BaseIndex;
64a0c779 7235
a724f0f4
JB		 7236 /* Set the scale after setting the register (otherwise,
7237 i386_scale will complain) */
7238 if (cur_token.code == '+' || cur_token.code == '-')
7239 {
7240 char *str, sign = cur_token.code;
7241 intel_match_token (cur_token.code);
7242 if (cur_token.code != T_CONST)
7243 {
7244 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7245 cur_token.str);
7246 return 0;
7247 }
7248 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7249 strcpy (str + 1, cur_token.str);
7250 *str = sign;
7251 if (!i386_scale (str))
7252 return 0;
7253 free (str);
7254 }
7255 else if (!i386_scale (cur_token.str))
64a0c779 7256 return 0;
a724f0f4
JB		 7257 intel_match_token (cur_token.code);
7258 }
64a0c779 7259
a724f0f4
JB		 7260 /* No scaling. If this is a memory operand, the register is either a
7261 base register (first occurrence) or an index register (second
7262 occurrence). */
7b0441f6 7263 else if (intel_parser.in_bracket)
a724f0f4 7264 {
64a0c779 7265
a724f0f4
JB		 7266 if (!i.base_reg)
7267 i.base_reg = reg;
7268 else if (!i.index_reg)
7269 i.index_reg = reg;
7270 else
7271 {
7272 as_bad (_("Too many register references in memory operand"));
7273 return 0;
7274 }
64a0c779 7275
a724f0f4
JB		 7276 i.types[this_operand] |= BaseIndex;
7277 }
4a1805b1 7278
4d1bb795
JB		 7279 /* It's neither base nor index. */
7280 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 7281 {
7282 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7283 i.op[this_operand].regs = reg;
7284 i.reg_operands++;
7285 }
7286 else
7287 {
7288 as_bad (_("Invalid use of register"));
7289 return 0;
7290 }
64a0c779 7291
a724f0f4
JB		 7292 /* Since registers are not part of the displacement string (except
7293 when we're parsing offset operands), we may need to remove any
7294 preceding '+' from the displacement string. */
7295 if (*intel_parser.disp != '\0'
7296 && !intel_parser.in_offset)
7297 {
7298 char *s = intel_parser.disp;
7299 s += strlen (s) - 1;
7300 if (*s == '+')
7301 *s = '\0';
7302 }
4a1805b1 7303
a724f0f4
JB		 7304 return 1;
7305 }
7306
7307 /* e11 BYTE
7308 | WORD
7309 | DWORD
7310 | FWORD
7311 | QWORD
7312 | TBYTE
7313 | OWORD
7314 | XMMWORD */
7315 case T_BYTE:
7316 case T_WORD:
7317 case T_DWORD:
7318 case T_FWORD:
7319 case T_QWORD:
7320 case T_TBYTE:
7321 case T_XMMWORD:
7322 intel_match_token (cur_token.code);
64a0c779 7323
a724f0f4
JB		 7324 if (cur_token.code == T_PTR)
7325 return 1;
7326
7327 /* It must have been an identifier. */
7328 intel_putback_token ();
7329 cur_token.code = T_ID;
7330 /* FALLTHRU */
7331
7332 /* e11 id
7333 | constant */
7334 case T_ID:
7335 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 7336 {
7337 symbolS *symbolP;
7338
a724f0f4
JB		 7339 /* The identifier represents a memory reference only if it's not
7340 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 7341 symbolP = symbol_find(cur_token.str);
7342 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7343 intel_parser.is_mem = 1;
7344 }
a724f0f4 7345 /* FALLTHRU */
64a0c779 7346
a724f0f4
JB		 7347 case T_CONST:
7348 case '-':
7349 case '+':
7350 {
7351 char *save_str, sign = 0;
64a0c779 7352
a724f0f4
JB		 7353 /* Allow constants that start with `+' or `-'. */
7354 if (cur_token.code == '-' || cur_token.code == '+')
7355 {
7356 sign = cur_token.code;
7357 intel_match_token (cur_token.code);
7358 if (cur_token.code != T_CONST)
7359 {
7360 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7361 cur_token.str);
7362 return 0;
7363 }
7364 }
64a0c779 7365
a724f0f4
JB		 7366 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7367 strcpy (save_str + !!sign, cur_token.str);
7368 if (sign)
7369 *save_str = sign;
64a0c779 7370
a724f0f4
JB		 7371 /* Get the next token to check for register scaling. */
7372 intel_match_token (cur_token.code);
64a0c779 7373
a724f0f4
JB		 7374 /* Check if this constant is a scaling factor for an index register. */
7375 if (cur_token.code == '*')
7376 {
7377 if (intel_match_token ('*') && cur_token.code == T_REG)
7378 {
7379 const reg_entry *reg = cur_token.reg;
7380
7381 if (!intel_parser.in_bracket)
7382 {
7383 as_bad (_("Register scaling only allowed in memory operands"));
7384 return 0;
7385 }
7386
7387 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
7388 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7389 else if (i.index_reg)
7390 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7391
7392 /* The constant is followed by `* reg', so it must be
7393 a valid scale. */
7394 i.index_reg = reg;
7395 i.types[this_operand] |= BaseIndex;
7396
7397 /* Set the scale after setting the register (otherwise,
7398 i386_scale will complain) */
7399 if (!i386_scale (save_str))
64a0c779 7400 return 0;
a724f0f4
JB		 7401 intel_match_token (T_REG);
7402
7403 /* Since registers are not part of the displacement
7404 string, we may need to remove any preceding '+' from
7405 the displacement string. */
7406 if (*intel_parser.disp != '\0')
7407 {
7408 char *s = intel_parser.disp;
7409 s += strlen (s) - 1;
7410 if (*s == '+')
7411 *s = '\0';
7412 }
7413
7414 free (save_str);
7415
7416 return 1;
7417 }
64a0c779 7418
a724f0f4
JB		 7419 /* The constant was not used for register scaling. Since we have
7420 already consumed the token following `*' we now need to put it
7421 back in the stream. */
64a0c779 7422 intel_putback_token ();
a724f0f4 7423 }
64a0c779 7424
a724f0f4
JB		 7425 /* Add the constant to the displacement string. */
7426 strcat (intel_parser.disp, save_str);
7427 free (save_str);
64a0c779 7428
a724f0f4
JB		 7429 return 1;
7430 }
64a0c779
DN		 7431 }
7432
64a0c779
DN		 7433 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7434 return 0;
7435}
7436
64a0c779
DN		 7437/* Match the given token against cur_token. If they match, read the next
7438 token from the operand string. */
7439static int
e3bb37b5 7440intel_match_token (int code)
64a0c779
DN		 7441{
7442 if (cur_token.code == code)
7443 {
7444 intel_get_token ();
7445 return 1;
7446 }
7447 else
7448 {
0477af35 7449 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 7450 return 0;
7451 }
7452}
7453
64a0c779
DN		 7454/* Read a new token from intel_parser.op_string and store it in cur_token. */
7455static void
e3bb37b5 7456intel_get_token (void)
64a0c779
DN		 7457{
7458 char *end_op;
7459 const reg_entry *reg;
7460 struct intel_token new_token;
7461
7462 new_token.code = T_NIL;
7463 new_token.reg = NULL;
7464 new_token.str = NULL;
7465
4a1805b1 7466 /* Free the memory allocated to the previous token and move
64a0c779
DN		 7467 cur_token to prev_token. */
7468 if (prev_token.str)
7469 free (prev_token.str);
7470
7471 prev_token = cur_token;
7472
7473 /* Skip whitespace. */
7474 while (is_space_char (*intel_parser.op_string))
7475 intel_parser.op_string++;
7476
7477 /* Return an empty token if we find nothing else on the line. */
7478 if (*intel_parser.op_string == '\0')
7479 {
7480 cur_token = new_token;
7481 return;
7482 }
7483
7484 /* The new token cannot be larger than the remainder of the operand
7485 string. */
a724f0f4 7486 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7487 new_token.str[0] = '\0';
7488
7489 if (strchr ("0123456789", *intel_parser.op_string))
7490 {
7491 char *p = new_token.str;
7492 char *q = intel_parser.op_string;
7493 new_token.code = T_CONST;
7494
7495 /* Allow any kind of identifier char to encompass floating point and
7496 hexadecimal numbers. */
7497 while (is_identifier_char (*q))
7498 *p++ = *q++;
7499 *p = '\0';
7500
7501 /* Recognize special symbol names [0-9][bf]. */
7502 if (strlen (intel_parser.op_string) == 2
4a1805b1 7503 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7504 || intel_parser.op_string[1] == 'f'))
7505 new_token.code = T_ID;
7506 }
7507
4d1bb795 7508 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7509 {
4d1bb795
JB		 7510 size_t len = end_op - intel_parser.op_string;
7511
64a0c779
DN		 7512 new_token.code = T_REG;
7513 new_token.reg = reg;
7514
4d1bb795
JB		 7515 memcpy (new_token.str, intel_parser.op_string, len);
7516 new_token.str[len] = '\0';
64a0c779
DN		 7517 }
7518
7519 else if (is_identifier_char (*intel_parser.op_string))
7520 {
7521 char *p = new_token.str;
7522 char *q = intel_parser.op_string;
7523
7524 /* A '.' or '$' followed by an identifier char is an identifier.
7525 Otherwise, it's operator '.' followed by an expression. */
7526 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7527 {
9306ca4a
JB		 7528 new_token.code = '.';
7529 new_token.str[0] = '.';
64a0c779
DN		 7530 new_token.str[1] = '\0';
7531 }
7532 else
7533 {
7534 while (is_identifier_char (*q) || *q == '@')
7535 *p++ = *q++;
7536 *p = '\0';
7537
9306ca4a
JB		 7538 if (strcasecmp (new_token.str, "NOT") == 0)
7539 new_token.code = '~';
7540
7541 else if (strcasecmp (new_token.str, "MOD") == 0)
7542 new_token.code = '%';
7543
7544 else if (strcasecmp (new_token.str, "AND") == 0)
7545 new_token.code = '&';
7546
7547 else if (strcasecmp (new_token.str, "OR") == 0)
7548 new_token.code = '|';
7549
7550 else if (strcasecmp (new_token.str, "XOR") == 0)
7551 new_token.code = '^';
7552
7553 else if (strcasecmp (new_token.str, "SHL") == 0)
7554 new_token.code = T_SHL;
7555
7556 else if (strcasecmp (new_token.str, "SHR") == 0)
7557 new_token.code = T_SHR;
7558
7559 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7560 new_token.code = T_BYTE;
7561
7562 else if (strcasecmp (new_token.str, "WORD") == 0)
7563 new_token.code = T_WORD;
7564
7565 else if (strcasecmp (new_token.str, "DWORD") == 0)
7566 new_token.code = T_DWORD;
7567
9306ca4a
JB		 7568 else if (strcasecmp (new_token.str, "FWORD") == 0)
7569 new_token.code = T_FWORD;
7570
64a0c779
DN		 7571 else if (strcasecmp (new_token.str, "QWORD") == 0)
7572 new_token.code = T_QWORD;
7573
9306ca4a
JB		 7574 else if (strcasecmp (new_token.str, "TBYTE") == 0
7575 /* XXX remove (gcc still uses it) */
7576 || strcasecmp (new_token.str, "XWORD") == 0)
7577 new_token.code = T_TBYTE;
7578
7579 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7580 || strcasecmp (new_token.str, "OWORD") == 0)
7581 new_token.code = T_XMMWORD;
64a0c779
DN		 7582
7583 else if (strcasecmp (new_token.str, "PTR") == 0)
7584 new_token.code = T_PTR;
7585
7586 else if (strcasecmp (new_token.str, "SHORT") == 0)
7587 new_token.code = T_SHORT;
7588
7589 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7590 {
7591 new_token.code = T_OFFSET;
7592
7593 /* ??? This is not mentioned in the MASM grammar but gcc
7594 makes use of it with -mintel-syntax. OFFSET may be
7595 followed by FLAT: */
7596 if (strncasecmp (q, " FLAT:", 6) == 0)
7597 strcat (new_token.str, " FLAT:");
7598 }
7599
7600 /* ??? This is not mentioned in the MASM grammar. */
7601 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7602 {
7603 new_token.code = T_OFFSET;
7604 if (*q == ':')
7605 strcat (new_token.str, ":");
7606 else
7607 as_bad (_("`:' expected"));
7608 }
64a0c779
DN		 7609
7610 else
7611 new_token.code = T_ID;
7612 }
7613 }
7614
9306ca4a
JB		 7615 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7616 {
7617 new_token.code = *intel_parser.op_string;
7618 new_token.str[0] = *intel_parser.op_string;
7619 new_token.str[1] = '\0';
7620 }
7621
7622 else if (strchr ("<>", *intel_parser.op_string)
7623 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7624 {
7625 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7626 new_token.str[0] = *intel_parser.op_string;
7627 new_token.str[1] = *intel_parser.op_string;
7628 new_token.str[2] = '\0';
7629 }
7630
64a0c779 7631 else
0477af35 7632 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7633
7634 intel_parser.op_string += strlen (new_token.str);
7635 cur_token = new_token;
7636}
7637
64a0c779
DN		 7638/* Put cur_token back into the token stream and make cur_token point to
7639 prev_token. */
7640static void
e3bb37b5 7641intel_putback_token (void)
64a0c779 7642{
a724f0f4
JB		 7643 if (cur_token.code != T_NIL)
7644 {
7645 intel_parser.op_string -= strlen (cur_token.str);
7646 free (cur_token.str);
7647 }
64a0c779 7648 cur_token = prev_token;
4a1805b1 7649
64a0c779
DN		 7650 /* Forget prev_token. */
7651 prev_token.code = T_NIL;
7652 prev_token.reg = NULL;
7653 prev_token.str = NULL;
7654}
54cfded0 7655
a4447b93 7656int
1df69f4f 7657tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 7658{
7659 unsigned int regnum;
7660 unsigned int regnames_count;
089dfecd 7661 static const char *const regnames_32[] =
54cfded0 7662 {
a4447b93
RH		 7663 "eax", "ecx", "edx", "ebx",
7664 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7665 "eip", "eflags", NULL,
7666 "st0", "st1", "st2", "st3",
7667 "st4", "st5", "st6", "st7",
7668 NULL, NULL,
7669 "xmm0", "xmm1", "xmm2", "xmm3",
7670 "xmm4", "xmm5", "xmm6", "xmm7",
7671 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7672 "mm4", "mm5", "mm6", "mm7",
7673 "fcw", "fsw", "mxcsr",
7674 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7675 "tr", "ldtr"
54cfded0 7676 };
089dfecd 7677 static const char *const regnames_64[] =
54cfded0 7678 {
089dfecd
JB		 7679 "rax", "rdx", "rcx", "rbx",
7680 "rsi", "rdi", "rbp", "rsp",
7681 "r8", "r9", "r10", "r11",
54cfded0 7682 "r12", "r13", "r14", "r15",
089dfecd
JB		 7683 "rip",
7684 "xmm0", "xmm1", "xmm2", "xmm3",
7685 "xmm4", "xmm5", "xmm6", "xmm7",
7686 "xmm8", "xmm9", "xmm10", "xmm11",
7687 "xmm12", "xmm13", "xmm14", "xmm15",
7688 "st0", "st1", "st2", "st3",
7689 "st4", "st5", "st6", "st7",
7690 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7691 "mm4", "mm5", "mm6", "mm7",
7692 "rflags",
7693 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7694 "fs.base", "gs.base", NULL, NULL,
7695 "tr", "ldtr",
7696 "mxcsr", "fcw", "fsw"
54cfded0 7697 };
089dfecd 7698 const char *const *regnames;
54cfded0
AM		 7699
7700 if (flag_code == CODE_64BIT)
7701 {
7702 regnames = regnames_64;
0cea6190 7703 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7704 }
7705 else
7706 {
7707 regnames = regnames_32;
0cea6190 7708 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7709 }
7710
7711 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7712 if (regnames[regnum] != NULL
7713 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7714 return regnum;
7715
54cfded0
AM		 7716 return -1;
7717}
7718
7719void
7720tc_x86_frame_initial_instructions (void)
7721{
a4447b93
RH		 7722 static unsigned int sp_regno;
7723
7724 if (!sp_regno)
7725 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7726 ? "rsp" : "esp");
7727
7728 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7729 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7730}
d2b2c203
DJ		 7731
7732int
7733i386_elf_section_type (const char *str, size_t len)
7734{
7735 if (flag_code == CODE_64BIT
7736 && len == sizeof ("unwind") - 1
7737 && strncmp (str, "unwind", 6) == 0)
7738 return SHT_X86_64_UNWIND;
7739
7740 return -1;
7741}
bb41ade5
AM		 7742
7743#ifdef TE_PE
7744void
7745tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7746{
7747 expressionS expr;
7748
7749 expr.X_op = O_secrel;
7750 expr.X_add_symbol = symbol;
7751 expr.X_add_number = 0;
7752 emit_expr (&expr, size);
7753}
7754#endif
3b22753a
L		 7755
7756#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7757/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7758
7759int
7760x86_64_section_letter (int letter, char **ptr_msg)
7761{
7762 if (flag_code == CODE_64BIT)
7763 {
7764 if (letter == 'l')
7765 return SHF_X86_64_LARGE;
7766
7767 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7768 }
3b22753a 7769 else
64e74474 7770 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7771 return -1;
7772}
7773
7774int
7775x86_64_section_word (char *str, size_t len)
7776{
8620418b 7777 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 7778 return SHF_X86_64_LARGE;
7779
7780 return -1;
7781}
7782
7783static void
7784handle_large_common (int small ATTRIBUTE_UNUSED)
7785{
7786 if (flag_code != CODE_64BIT)
7787 {
7788 s_comm_internal (0, elf_common_parse);
7789 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7790 }
7791 else
7792 {
7793 static segT lbss_section;
7794 asection *saved_com_section_ptr = elf_com_section_ptr;
7795 asection *saved_bss_section = bss_section;
7796
7797 if (lbss_section == NULL)
7798 {
7799 flagword applicable;
7800 segT seg = now_seg;
7801 subsegT subseg = now_subseg;
7802
7803 /* The .lbss section is for local .largecomm symbols. */
7804 lbss_section = subseg_new (".lbss", 0);
7805 applicable = bfd_applicable_section_flags (stdoutput);
7806 bfd_set_section_flags (stdoutput, lbss_section,
7807 applicable & SEC_ALLOC);
7808 seg_info (lbss_section)->bss = 1;
7809
7810 subseg_set (seg, subseg);
7811 }
7812
7813 elf_com_section_ptr = &_bfd_elf_large_com_section;
7814 bss_section = lbss_section;
7815
7816 s_comm_internal (0, elf_common_parse);
7817
7818 elf_com_section_ptr = saved_com_section_ptr;
7819 bss_section = saved_bss_section;
7820 }
7821}
7822#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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