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* elf32-arm.c (arm_map_one_stub): Declare variables at beginning
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5dd15031 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 LOCKREP_PREFIX. */
63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
67#define LOCKREP_PREFIX 4
68#define REX_PREFIX 5 /* must come last. */
69#define MAX_PREFIXES 6 /* max prefixes per opcode */
70
71/* we define the syntax here (modulo base,index,scale syntax) */
72#define REGISTER_PREFIX '%'
73#define IMMEDIATE_PREFIX '$'
74#define ABSOLUTE_PREFIX '*'
75
76/* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78#define WORD_MNEM_SUFFIX 'w'
79#define BYTE_MNEM_SUFFIX 'b'
80#define SHORT_MNEM_SUFFIX 's'
81#define LONG_MNEM_SUFFIX 'l'
82#define QWORD_MNEM_SUFFIX 'q'
83#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 84#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 85/* Intel Syntax. Use a non-ascii letter since since it never appears
86 in instructions. */
87#define LONG_DOUBLE_MNEM_SUFFIX '\1'
88
89#define END_OF_INSN '\0'
90
91/*
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
96 END.
97 */
98typedef struct
99{
100 const template *start;
101 const template *end;
102}
103templates;
104
105/* 386 operand encoding bytes: see 386 book for details of this. */
106typedef struct
107{
108 unsigned int regmem; /* codes register or memory operand */
109 unsigned int reg; /* codes register operand (or extended opcode) */
110 unsigned int mode; /* how to interpret regmem & reg */
111}
112modrm_byte;
113
114/* x86-64 extension prefix. */
115typedef int rex_byte;
116
117/* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120#define DREX_OC0(x) (((x) & 1) != 0)
121#define DREX_OC1(x) (((x) & 2) != 0)
122
123#define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124#define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
125
126/* OC mappings */
127#define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128#define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129#define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130#define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
131
132#define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133#define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
134
135/* Information needed to create the DREX byte in SSE5 instructions. */
136typedef struct
137{
138 unsigned int reg; /* register */
139 unsigned int rex; /* REX flags */
140 unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
142} drex_byte;
143
144/* 386 opcode byte to code indirect addressing. */
145typedef struct
146{
147 unsigned base;
148 unsigned index;
149 unsigned scale;
150}
151sib_byte;
152
153enum processor_type
154{
155 PROCESSOR_UNKNOWN,
156 PROCESSOR_I386,
157 PROCESSOR_I486,
158 PROCESSOR_PENTIUM,
159 PROCESSOR_PENTIUMPRO,
160 PROCESSOR_PENTIUM4,
161 PROCESSOR_NOCONA,
162 PROCESSOR_CORE,
163 PROCESSOR_CORE2,
164 PROCESSOR_K6,
165 PROCESSOR_ATHLON,
166 PROCESSOR_K8,
167 PROCESSOR_GENERIC32,
168 PROCESSOR_GENERIC64,
169 PROCESSOR_AMDFAM10
170};
171
172/* x86 arch names, types and features */
173typedef struct
174{
175 const char *name; /* arch name */
176 enum processor_type type; /* arch type */
177 i386_cpu_flags flags; /* cpu feature flags */
178}
179arch_entry;
180
e3bb37b5
L		 181static void set_code_flag (int);
182static void set_16bit_gcc_code_flag (int);
183static void set_intel_syntax (int);
1efbbeb4 184static void set_intel_mnemonic (int);
db51cc60 185static void set_allow_index_reg (int);
cb19c032 186static void set_sse_check (int);
e3bb37b5 187static void set_cpu_arch (int);
6482c264 188#ifdef TE_PE
e3bb37b5 189static void pe_directive_secrel (int);
6482c264 190#endif
e3bb37b5
L		 191static void signed_cons (int);
192static char *output_invalid (int c);
a7619375 193static int i386_att_operand (char *);
e3bb37b5
L		 194static int i386_intel_operand (char *, int);
195static const reg_entry *parse_register (char *, char **);
196static char *parse_insn (char *, char *);
197static char *parse_operands (char *, const char *);
198static void swap_operands (void);
4d456e3d 199static void swap_2_operands (int, int);
e3bb37b5
L		 200static void optimize_imm (void);
201static void optimize_disp (void);
202static int match_template (void);
203static int check_string (void);
204static int process_suffix (void);
205static int check_byte_reg (void);
206static int check_long_reg (void);
207static int check_qword_reg (void);
208static int check_word_reg (void);
209static int finalize_imm (void);
85f10a01 210static void process_drex (void);
e3bb37b5
L		 211static int process_operands (void);
212static const seg_entry *build_modrm_byte (void);
213static void output_insn (void);
214static void output_imm (fragS *, offsetT);
215static void output_disp (fragS *, offsetT);
29b0f896 216#ifndef I386COFF
e3bb37b5 217static void s_bss (int);
252b5132 218#endif
17d4e2a2
L		 219#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
220static void handle_large_common (int small ATTRIBUTE_UNUSED);
221#endif
252b5132 222
a847613f 223static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 224
c0f3af97
L		 225/* VEX prefix. */
226typedef struct
227{
228 /* VEX prefix is either 2 byte or 3 byte. */
229 unsigned char bytes[3];
230 unsigned int length;
231 /* Destination or source register specifier. */
232 const reg_entry *register_specifier;
233} vex_prefix;
234
252b5132 235/* 'md_assemble ()' gathers together information and puts it into a
47926f60 236 i386_insn. */
252b5132 237
520dc8e8
AM		 238union i386_op
239 {
240 expressionS *disps;
241 expressionS *imms;
242 const reg_entry *regs;
243 };
244
252b5132
RH		 245struct _i386_insn
246 {
47926f60 247 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 248 template tm;
249
7d5e4556
L		 250 /* SUFFIX holds the instruction size suffix for byte, word, dword
251 or qword, if given. */
252b5132
RH		 252 char suffix;
253
47926f60 254 /* OPERANDS gives the number of given operands. */
252b5132
RH		 255 unsigned int operands;
256
257 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
258 of given register, displacement, memory operands and immediate
47926f60 259 operands. */
252b5132
RH		 260 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
261
262 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 263 use OP[i] for the corresponding operand. */
40fb9820 264 i386_operand_type types[MAX_OPERANDS];
252b5132 265
520dc8e8
AM		 266 /* Displacement expression, immediate expression, or register for each
267 operand. */
268 union i386_op op[MAX_OPERANDS];
252b5132 269
3e73aa7c
JH		 270 /* Flags for operands. */
271 unsigned int flags[MAX_OPERANDS];
272#define Operand_PCrel 1
273
252b5132 274 /* Relocation type for operand */
f86103b7 275 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 276
252b5132
RH		 277 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
278 the base index byte below. */
279 const reg_entry *base_reg;
280 const reg_entry *index_reg;
281 unsigned int log2_scale_factor;
282
283 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 284 explicit segment overrides are given. */
ce8a8b2f 285 const seg_entry *seg[2];
252b5132
RH		 286
287 /* PREFIX holds all the given prefix opcodes (usually null).
288 PREFIXES is the number of prefix opcodes. */
289 unsigned int prefixes;
290 unsigned char prefix[MAX_PREFIXES];
291
292 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 293 addressing modes of this insn are encoded. DREX is the byte
294 added by the SSE5 instructions. */
252b5132
RH		 295
296 modrm_byte rm;
3e73aa7c 297 rex_byte rex;
252b5132 298 sib_byte sib;
85f10a01 299 drex_byte drex;
c0f3af97 300 vex_prefix vex;
252b5132
RH		 301 };
302
303typedef struct _i386_insn i386_insn;
304
305/* List of chars besides those in app.c:symbol_chars that can start an
306 operand. Used to prevent the scrubber eating vital white-space. */
32137342 307const char extra_symbol_chars[] = "*%-(["
252b5132 308#ifdef LEX_AT
32137342
NC		 309 "@"
310#endif
311#ifdef LEX_QM
312 "?"
252b5132 313#endif
32137342 314 ;
252b5132 315
29b0f896
AM		 316#if (defined (TE_I386AIX) \
317 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 318 && !defined (TE_GNU) \
29b0f896 319 && !defined (TE_LINUX) \
32137342 320 && !defined (TE_NETWARE) \
29b0f896
AM		 321 && !defined (TE_FreeBSD) \
322 && !defined (TE_NetBSD)))
252b5132 323/* This array holds the chars that always start a comment. If the
b3b91714
AM		 324 pre-processor is disabled, these aren't very useful. The option
325 --divide will remove '/' from this list. */
326const char *i386_comment_chars = "#/";
327#define SVR4_COMMENT_CHARS 1
252b5132 328#define PREFIX_SEPARATOR '\\'
252b5132 329
b3b91714
AM		 330#else
331const char *i386_comment_chars = "#";
332#define PREFIX_SEPARATOR '/'
333#endif
334
252b5132
RH		 335/* This array holds the chars that only start a comment at the beginning of
336 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 337 .line and .file directives will appear in the pre-processed output.
338 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 339 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 340 #NO_APP at the beginning of its output.
341 Also note that comments started like this one will always work if
252b5132 342 '/' isn't otherwise defined. */
b3b91714 343const char line_comment_chars[] = "#/";
252b5132 344
63a0b638 345const char line_separator_chars[] = ";";
252b5132 346
ce8a8b2f
AM		 347/* Chars that can be used to separate mant from exp in floating point
348 nums. */
252b5132
RH		 349const char EXP_CHARS[] = "eE";
350
ce8a8b2f
AM		 351/* Chars that mean this number is a floating point constant
352 As in 0f12.456
353 or 0d1.2345e12. */
252b5132
RH		 354const char FLT_CHARS[] = "fFdDxX";
355
ce8a8b2f 356/* Tables for lexical analysis. */
252b5132
RH		 357static char mnemonic_chars[256];
358static char register_chars[256];
359static char operand_chars[256];
360static char identifier_chars[256];
361static char digit_chars[256];
362
ce8a8b2f 363/* Lexical macros. */
252b5132
RH		 364#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
365#define is_operand_char(x) (operand_chars[(unsigned char) x])
366#define is_register_char(x) (register_chars[(unsigned char) x])
367#define is_space_char(x) ((x) == ' ')
368#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
369#define is_digit_char(x) (digit_chars[(unsigned char) x])
370
0234cb7c 371/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 372static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
373
374/* md_assemble() always leaves the strings it's passed unaltered. To
375 effect this we maintain a stack of saved characters that we've smashed
376 with '\0's (indicating end of strings for various sub-fields of the
47926f60 377 assembler instruction). */
252b5132 378static char save_stack[32];
ce8a8b2f 379static char *save_stack_p;
252b5132
RH		 380#define END_STRING_AND_SAVE(s) \
381 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
382#define RESTORE_END_STRING(s) \
383 do { *(s) = *--save_stack_p; } while (0)
384
47926f60 385/* The instruction we're assembling. */
252b5132
RH		 386static i386_insn i;
387
388/* Possible templates for current insn. */
389static const templates *current_templates;
390
31b2323c
L		 391/* Per instruction expressionS buffers: max displacements & immediates. */
392static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
393static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 394
47926f60
KH		 395/* Current operand we are working on. */
396static int this_operand;
252b5132 397
3e73aa7c
JH		 398/* We support four different modes. FLAG_CODE variable is used to distinguish
399 these. */
400
401enum flag_code {
402 CODE_32BIT,
403 CODE_16BIT,
404 CODE_64BIT };
405
406static enum flag_code flag_code;
4fa24527 407static unsigned int object_64bit;
3e73aa7c
JH		 408static int use_rela_relocations = 0;
409
410/* The names used to print error messages. */
b77a7acd 411static const char *flag_code_names[] =
3e73aa7c
JH		 412 {
413 "32",
414 "16",
415 "64"
416 };
252b5132 417
47926f60
KH		 418/* 1 for intel syntax,
419 0 if att syntax. */
420static int intel_syntax = 0;
252b5132 421
1efbbeb4
L		 422/* 1 for intel mnemonic,
423 0 if att mnemonic. */
424static int intel_mnemonic = !SYSV386_COMPAT;
425
5209009a 426/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 427static int old_gcc = OLDGCC_COMPAT;
428
a60de03c
JB		 429/* 1 if pseudo registers are permitted. */
430static int allow_pseudo_reg = 0;
431
47926f60
KH		 432/* 1 if register prefix % not required. */
433static int allow_naked_reg = 0;
252b5132 434
ba104c83 435/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 436static int allow_index_reg = 0;
437
daf50ae7
L		 438static enum
439 {
440 sse_check_none = 0,
441 sse_check_warning,
442 sse_check_error
443 }
444sse_check;
445
2ca3ace5
L		 446/* Register prefix used for error message. */
447static const char *register_prefix = "%";
448
47926f60
KH		 449/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
450 leave, push, and pop instructions so that gcc has the same stack
451 frame as in 32 bit mode. */
452static char stackop_size = '\0';
eecb386c 453
12b55ccc
L		 454/* Non-zero to optimize code alignment. */
455int optimize_align_code = 1;
456
47926f60
KH		 457/* Non-zero to quieten some warnings. */
458static int quiet_warnings = 0;
a38cf1db 459
47926f60
KH		 460/* CPU name. */
461static const char *cpu_arch_name = NULL;
6305a203 462static char *cpu_sub_arch_name = NULL;
a38cf1db 463
47926f60 464/* CPU feature flags. */
40fb9820
L		 465static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
466
ccc9c027
L		 467/* If we have selected a cpu we are generating instructions for. */
468static int cpu_arch_tune_set = 0;
469
9103f4f4
L		 470/* Cpu we are generating instructions for. */
471static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
472
473/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 474static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 475
ccc9c027
L		 476/* CPU instruction set architecture used. */
477static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
478
9103f4f4 479/* CPU feature flags of instruction set architecture used. */
40fb9820 480static i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 481
fddf5b5b
AM		 482/* If set, conditional jumps are not automatically promoted to handle
483 larger than a byte offset. */
484static unsigned int no_cond_jump_promotion = 0;
485
c0f3af97
L		 486/* Encode SSE instructions with VEX prefix. */
487static unsigned int sse2avx;
488
29b0f896 489/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 490static symbolS *GOT_symbol;
29b0f896 491
a4447b93
RH		 492/* The dwarf2 return column, adjusted for 32 or 64 bit. */
493unsigned int x86_dwarf2_return_column;
494
495/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
496int x86_cie_data_alignment;
497
252b5132 498/* Interface to relax_segment.
fddf5b5b
AM		 499 There are 3 major relax states for 386 jump insns because the
500 different types of jumps add different sizes to frags when we're
501 figuring out what sort of jump to choose to reach a given label. */
252b5132 502
47926f60 503/* Types. */
93c2a809
AM		 504#define UNCOND_JUMP 0
505#define COND_JUMP 1
506#define COND_JUMP86 2
fddf5b5b 507
47926f60 508/* Sizes. */
252b5132
RH		 509#define CODE16 1
510#define SMALL 0
29b0f896 511#define SMALL16 (SMALL | CODE16)
252b5132 512#define BIG 2
29b0f896 513#define BIG16 (BIG | CODE16)
252b5132
RH		 514
515#ifndef INLINE
516#ifdef __GNUC__
517#define INLINE __inline__
518#else
519#define INLINE
520#endif
521#endif
522
fddf5b5b
AM		 523#define ENCODE_RELAX_STATE(type, size) \
524 ((relax_substateT) (((type) << 2) | (size)))
525#define TYPE_FROM_RELAX_STATE(s) \
526 ((s) >> 2)
527#define DISP_SIZE_FROM_RELAX_STATE(s) \
528 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 529
530/* This table is used by relax_frag to promote short jumps to long
531 ones where necessary. SMALL (short) jumps may be promoted to BIG
532 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
533 don't allow a short jump in a 32 bit code segment to be promoted to
534 a 16 bit offset jump because it's slower (requires data size
535 prefix), and doesn't work, unless the destination is in the bottom
536 64k of the code segment (The top 16 bits of eip are zeroed). */
537
538const relax_typeS md_relax_table[] =
539{
24eab124
AM		 540 /* The fields are:
541 1) most positive reach of this state,
542 2) most negative reach of this state,
93c2a809 543 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 544 4) which index into the table to try if we can't fit into this one. */
252b5132 545
fddf5b5b 546 /* UNCOND_JUMP states. */
93c2a809
AM		 547 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
548 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
549 /* dword jmp adds 4 bytes to frag:
550 0 extra opcode bytes, 4 displacement bytes. */
252b5132 551 {0, 0, 4, 0},
93c2a809
AM		 552 /* word jmp adds 2 byte2 to frag:
553 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 554 {0, 0, 2, 0},
555
93c2a809
AM		 556 /* COND_JUMP states. */
557 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
558 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
559 /* dword conditionals adds 5 bytes to frag:
560 1 extra opcode byte, 4 displacement bytes. */
561 {0, 0, 5, 0},
fddf5b5b 562 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 563 1 extra opcode byte, 2 displacement bytes. */
564 {0, 0, 3, 0},
565
566 /* COND_JUMP86 states. */
567 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
568 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
569 /* dword conditionals adds 5 bytes to frag:
570 1 extra opcode byte, 4 displacement bytes. */
571 {0, 0, 5, 0},
572 /* word conditionals add 4 bytes to frag:
573 1 displacement byte and a 3 byte long branch insn. */
574 {0, 0, 4, 0}
252b5132
RH		 575};
576
9103f4f4
L		 577static const arch_entry cpu_arch[] =
578{
6305a203
L		 579 { "generic32", PROCESSOR_GENERIC32,
580 CPU_GENERIC32_FLAGS },
581 { "generic64", PROCESSOR_GENERIC64,
582 CPU_GENERIC64_FLAGS },
583 { "i8086", PROCESSOR_UNKNOWN,
584 CPU_NONE_FLAGS },
585 { "i186", PROCESSOR_UNKNOWN,
586 CPU_I186_FLAGS },
587 { "i286", PROCESSOR_UNKNOWN,
588 CPU_I286_FLAGS },
589 { "i386", PROCESSOR_I386,
590 CPU_I386_FLAGS },
591 { "i486", PROCESSOR_I486,
592 CPU_I486_FLAGS },
593 { "i586", PROCESSOR_PENTIUM,
594 CPU_I586_FLAGS },
595 { "i686", PROCESSOR_PENTIUMPRO,
596 CPU_I686_FLAGS },
597 { "pentium", PROCESSOR_PENTIUM,
598 CPU_I586_FLAGS },
599 { "pentiumpro", PROCESSOR_PENTIUMPRO,
600 CPU_I686_FLAGS },
601 { "pentiumii", PROCESSOR_PENTIUMPRO,
602 CPU_P2_FLAGS },
603 { "pentiumiii",PROCESSOR_PENTIUMPRO,
604 CPU_P3_FLAGS },
605 { "pentium4", PROCESSOR_PENTIUM4,
606 CPU_P4_FLAGS },
607 { "prescott", PROCESSOR_NOCONA,
608 CPU_CORE_FLAGS },
609 { "nocona", PROCESSOR_NOCONA,
610 CPU_NOCONA_FLAGS },
611 { "yonah", PROCESSOR_CORE,
612 CPU_CORE_FLAGS },
613 { "core", PROCESSOR_CORE,
614 CPU_CORE_FLAGS },
615 { "merom", PROCESSOR_CORE2,
616 CPU_CORE2_FLAGS },
617 { "core2", PROCESSOR_CORE2,
618 CPU_CORE2_FLAGS },
619 { "k6", PROCESSOR_K6,
620 CPU_K6_FLAGS },
621 { "k6_2", PROCESSOR_K6,
622 CPU_K6_2_FLAGS },
623 { "athlon", PROCESSOR_ATHLON,
624 CPU_ATHLON_FLAGS },
625 { "sledgehammer", PROCESSOR_K8,
626 CPU_K8_FLAGS },
627 { "opteron", PROCESSOR_K8,
628 CPU_K8_FLAGS },
629 { "k8", PROCESSOR_K8,
630 CPU_K8_FLAGS },
631 { "amdfam10", PROCESSOR_AMDFAM10,
632 CPU_AMDFAM10_FLAGS },
633 { ".mmx", PROCESSOR_UNKNOWN,
634 CPU_MMX_FLAGS },
635 { ".sse", PROCESSOR_UNKNOWN,
636 CPU_SSE_FLAGS },
637 { ".sse2", PROCESSOR_UNKNOWN,
638 CPU_SSE2_FLAGS },
639 { ".sse3", PROCESSOR_UNKNOWN,
640 CPU_SSE3_FLAGS },
641 { ".ssse3", PROCESSOR_UNKNOWN,
642 CPU_SSSE3_FLAGS },
643 { ".sse4.1", PROCESSOR_UNKNOWN,
644 CPU_SSE4_1_FLAGS },
645 { ".sse4.2", PROCESSOR_UNKNOWN,
646 CPU_SSE4_2_FLAGS },
647 { ".sse4", PROCESSOR_UNKNOWN,
648 CPU_SSE4_2_FLAGS },
c0f3af97
L		 649 { ".avx", PROCESSOR_UNKNOWN,
650 CPU_AVX_FLAGS },
6305a203
L		 651 { ".vmx", PROCESSOR_UNKNOWN,
652 CPU_VMX_FLAGS },
653 { ".smx", PROCESSOR_UNKNOWN,
654 CPU_SMX_FLAGS },
f03fe4c1
L		 655 { ".xsave", PROCESSOR_UNKNOWN,
656 CPU_XSAVE_FLAGS },
c0f3af97
L		 657 { ".aes", PROCESSOR_UNKNOWN,
658 CPU_AES_FLAGS },
594ab6a3
L		 659 { ".pclmul", PROCESSOR_UNKNOWN,
660 CPU_PCLMUL_FLAGS },
c0f3af97 661 { ".clmul", PROCESSOR_UNKNOWN,
594ab6a3 662 CPU_PCLMUL_FLAGS },
c0f3af97
L		 663 { ".fma", PROCESSOR_UNKNOWN,
664 CPU_FMA_FLAGS },
f1f8f695
L		 665 { ".movbe", PROCESSOR_UNKNOWN,
666 CPU_MOVBE_FLAGS },
667 { ".ept", PROCESSOR_UNKNOWN,
668 CPU_EPT_FLAGS },
6305a203
L		 669 { ".3dnow", PROCESSOR_UNKNOWN,
670 CPU_3DNOW_FLAGS },
671 { ".3dnowa", PROCESSOR_UNKNOWN,
672 CPU_3DNOWA_FLAGS },
673 { ".padlock", PROCESSOR_UNKNOWN,
674 CPU_PADLOCK_FLAGS },
675 { ".pacifica", PROCESSOR_UNKNOWN,
676 CPU_SVME_FLAGS },
677 { ".svme", PROCESSOR_UNKNOWN,
678 CPU_SVME_FLAGS },
679 { ".sse4a", PROCESSOR_UNKNOWN,
680 CPU_SSE4A_FLAGS },
681 { ".abm", PROCESSOR_UNKNOWN,
682 CPU_ABM_FLAGS },
683 { ".sse5", PROCESSOR_UNKNOWN,
684 CPU_SSE5_FLAGS },
e413e4e9
AM		 685};
686
29b0f896
AM		 687const pseudo_typeS md_pseudo_table[] =
688{
689#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
690 {"align", s_align_bytes, 0},
691#else
692 {"align", s_align_ptwo, 0},
693#endif
694 {"arch", set_cpu_arch, 0},
695#ifndef I386COFF
696 {"bss", s_bss, 0},
697#endif
698 {"ffloat", float_cons, 'f'},
699 {"dfloat", float_cons, 'd'},
700 {"tfloat", float_cons, 'x'},
701 {"value", cons, 2},
d182319b 702 {"slong", signed_cons, 4},
29b0f896
AM		 703 {"noopt", s_ignore, 0},
704 {"optim", s_ignore, 0},
705 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
706 {"code16", set_code_flag, CODE_16BIT},
707 {"code32", set_code_flag, CODE_32BIT},
708 {"code64", set_code_flag, CODE_64BIT},
709 {"intel_syntax", set_intel_syntax, 1},
710 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 711 {"intel_mnemonic", set_intel_mnemonic, 1},
712 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 713 {"allow_index_reg", set_allow_index_reg, 1},
714 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 715 {"sse_check", set_sse_check, 0},
3b22753a
L		 716#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
717 {"largecomm", handle_large_common, 0},
07a53e5c 718#else
e3bb37b5 719 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 720 {"loc", dwarf2_directive_loc, 0},
721 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 722#endif
6482c264
NC		 723#ifdef TE_PE
724 {"secrel32", pe_directive_secrel, 0},
725#endif
29b0f896
AM		 726 {0, 0, 0}
727};
728
729/* For interface with expression (). */
730extern char *input_line_pointer;
731
732/* Hash table for instruction mnemonic lookup. */
733static struct hash_control *op_hash;
734
735/* Hash table for register lookup. */
736static struct hash_control *reg_hash;
737\f
252b5132 738void
e3bb37b5 739i386_align_code (fragS *fragP, int count)
252b5132 740{
ce8a8b2f
AM		 741 /* Various efficient no-op patterns for aligning code labels.
742 Note: Don't try to assemble the instructions in the comments.
743 0L and 0w are not legal. */
252b5132
RH		 744 static const char f32_1[] =
745 {0x90}; /* nop */
746 static const char f32_2[] =
ccc9c027 747 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 748 static const char f32_3[] =
749 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
750 static const char f32_4[] =
751 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
752 static const char f32_5[] =
753 {0x90, /* nop */
754 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
755 static const char f32_6[] =
756 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
757 static const char f32_7[] =
758 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
759 static const char f32_8[] =
760 {0x90, /* nop */
761 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
762 static const char f32_9[] =
763 {0x89,0xf6, /* movl %esi,%esi */
764 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
765 static const char f32_10[] =
766 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
767 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
768 static const char f32_11[] =
769 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
770 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
771 static const char f32_12[] =
772 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
773 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
774 static const char f32_13[] =
775 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
776 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
777 static const char f32_14[] =
778 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
779 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 780 static const char f16_3[] =
781 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 782 static const char f16_4[] =
783 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
784 static const char f16_5[] =
785 {0x90, /* nop */
786 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
787 static const char f16_6[] =
788 {0x89,0xf6, /* mov %si,%si */
789 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
790 static const char f16_7[] =
791 {0x8d,0x74,0x00, /* lea 0(%si),%si */
792 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
793 static const char f16_8[] =
794 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
795 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 796 static const char jump_31[] =
797 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
798 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
799 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
800 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 801 static const char *const f32_patt[] = {
802 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 803 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 804 };
805 static const char *const f16_patt[] = {
76bc74dc 806 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 807 };
ccc9c027
L		 808 /* nopl (%[re]ax) */
809 static const char alt_3[] =
810 {0x0f,0x1f,0x00};
811 /* nopl 0(%[re]ax) */
812 static const char alt_4[] =
813 {0x0f,0x1f,0x40,0x00};
814 /* nopl 0(%[re]ax,%[re]ax,1) */
815 static const char alt_5[] =
816 {0x0f,0x1f,0x44,0x00,0x00};
817 /* nopw 0(%[re]ax,%[re]ax,1) */
818 static const char alt_6[] =
819 {0x66,0x0f,0x1f,0x44,0x00,0x00};
820 /* nopl 0L(%[re]ax) */
821 static const char alt_7[] =
822 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
823 /* nopl 0L(%[re]ax,%[re]ax,1) */
824 static const char alt_8[] =
825 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
826 /* nopw 0L(%[re]ax,%[re]ax,1) */
827 static const char alt_9[] =
828 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
829 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
830 static const char alt_10[] =
831 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
832 /* data16
833 nopw %cs:0L(%[re]ax,%[re]ax,1) */
834 static const char alt_long_11[] =
835 {0x66,
836 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
837 /* data16
838 data16
839 nopw %cs:0L(%[re]ax,%[re]ax,1) */
840 static const char alt_long_12[] =
841 {0x66,
842 0x66,
843 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
844 /* data16
845 data16
846 data16
847 nopw %cs:0L(%[re]ax,%[re]ax,1) */
848 static const char alt_long_13[] =
849 {0x66,
850 0x66,
851 0x66,
852 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
853 /* data16
854 data16
855 data16
856 data16
857 nopw %cs:0L(%[re]ax,%[re]ax,1) */
858 static const char alt_long_14[] =
859 {0x66,
860 0x66,
861 0x66,
862 0x66,
863 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
864 /* data16
865 data16
866 data16
867 data16
868 data16
869 nopw %cs:0L(%[re]ax,%[re]ax,1) */
870 static const char alt_long_15[] =
871 {0x66,
872 0x66,
873 0x66,
874 0x66,
875 0x66,
876 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
877 /* nopl 0(%[re]ax,%[re]ax,1)
878 nopw 0(%[re]ax,%[re]ax,1) */
879 static const char alt_short_11[] =
880 {0x0f,0x1f,0x44,0x00,0x00,
881 0x66,0x0f,0x1f,0x44,0x00,0x00};
882 /* nopw 0(%[re]ax,%[re]ax,1)
883 nopw 0(%[re]ax,%[re]ax,1) */
884 static const char alt_short_12[] =
885 {0x66,0x0f,0x1f,0x44,0x00,0x00,
886 0x66,0x0f,0x1f,0x44,0x00,0x00};
887 /* nopw 0(%[re]ax,%[re]ax,1)
888 nopl 0L(%[re]ax) */
889 static const char alt_short_13[] =
890 {0x66,0x0f,0x1f,0x44,0x00,0x00,
891 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
892 /* nopl 0L(%[re]ax)
893 nopl 0L(%[re]ax) */
894 static const char alt_short_14[] =
895 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
896 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
897 /* nopl 0L(%[re]ax)
898 nopl 0L(%[re]ax,%[re]ax,1) */
899 static const char alt_short_15[] =
900 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
901 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
902 static const char *const alt_short_patt[] = {
903 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
904 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
905 alt_short_14, alt_short_15
906 };
907 static const char *const alt_long_patt[] = {
908 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
909 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
910 alt_long_14, alt_long_15
911 };
252b5132 912
76bc74dc
L		 913 /* Only align for at least a positive non-zero boundary. */
914 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 915 return;
3e73aa7c 916
ccc9c027
L		 917 /* We need to decide which NOP sequence to use for 32bit and
918 64bit. When -mtune= is used:
4eed87de 919
76bc74dc
L		 920 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
921 PROCESSOR_GENERIC32, f32_patt will be used.
922 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
923 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
924 alt_long_patt will be used.
925 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
926 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 927
76bc74dc
L		 928 When -mtune= isn't used, alt_long_patt will be used if
929 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
930 be used.
ccc9c027
L		 931
932 When -march= or .arch is used, we can't use anything beyond
933 cpu_arch_isa_flags. */
934
935 if (flag_code == CODE_16BIT)
936 {
ccc9c027 937 if (count > 8)
33fef721 938 {
76bc74dc
L		 939 memcpy (fragP->fr_literal + fragP->fr_fix,
940 jump_31, count);
941 /* Adjust jump offset. */
942 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 943 }
76bc74dc
L		 944 else
945 memcpy (fragP->fr_literal + fragP->fr_fix,
946 f16_patt[count - 1], count);
252b5132 947 }
33fef721 948 else
ccc9c027
L		 949 {
950 const char *const *patt = NULL;
951
952 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
953 {
954 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
955 switch (cpu_arch_tune)
956 {
957 case PROCESSOR_UNKNOWN:
958 /* We use cpu_arch_isa_flags to check if we SHOULD
959 optimize for Cpu686. */
40fb9820 960 if (cpu_arch_isa_flags.bitfield.cpui686)
76bc74dc 961 patt = alt_long_patt;
ccc9c027
L		 962 else
963 patt = f32_patt;
964 break;
ccc9c027
L		 965 case PROCESSOR_PENTIUMPRO:
966 case PROCESSOR_PENTIUM4:
967 case PROCESSOR_NOCONA:
ef05d495 968 case PROCESSOR_CORE:
76bc74dc
L		 969 case PROCESSOR_CORE2:
970 case PROCESSOR_GENERIC64:
971 patt = alt_long_patt;
972 break;
ccc9c027
L		 973 case PROCESSOR_K6:
974 case PROCESSOR_ATHLON:
975 case PROCESSOR_K8:
4eed87de 976 case PROCESSOR_AMDFAM10:
ccc9c027
L		 977 patt = alt_short_patt;
978 break;
76bc74dc 979 case PROCESSOR_I386:
ccc9c027
L		 980 case PROCESSOR_I486:
981 case PROCESSOR_PENTIUM:
982 case PROCESSOR_GENERIC32:
983 patt = f32_patt;
984 break;
4eed87de 985 }
ccc9c027
L		 986 }
987 else
988 {
989 switch (cpu_arch_tune)
990 {
991 case PROCESSOR_UNKNOWN:
992 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
993 PROCESSOR_UNKNOWN. */
994 abort ();
995 break;
996
76bc74dc 997 case PROCESSOR_I386:
ccc9c027
L		 998 case PROCESSOR_I486:
999 case PROCESSOR_PENTIUM:
ccc9c027
L		 1000 case PROCESSOR_K6:
1001 case PROCESSOR_ATHLON:
1002 case PROCESSOR_K8:
4eed87de 1003 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1004 case PROCESSOR_GENERIC32:
1005 /* We use cpu_arch_isa_flags to check if we CAN optimize
1006 for Cpu686. */
40fb9820 1007 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 1008 patt = alt_short_patt;
1009 else
1010 patt = f32_patt;
1011 break;
76bc74dc
L		 1012 case PROCESSOR_PENTIUMPRO:
1013 case PROCESSOR_PENTIUM4:
1014 case PROCESSOR_NOCONA:
1015 case PROCESSOR_CORE:
ef05d495 1016 case PROCESSOR_CORE2:
40fb9820 1017 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 1018 patt = alt_long_patt;
1019 else
1020 patt = f32_patt;
1021 break;
1022 case PROCESSOR_GENERIC64:
76bc74dc 1023 patt = alt_long_patt;
ccc9c027 1024 break;
4eed87de 1025 }
ccc9c027
L		 1026 }
1027
76bc74dc
L		 1028 if (patt == f32_patt)
1029 {
1030 /* If the padding is less than 15 bytes, we use the normal
1031 ones. Otherwise, we use a jump instruction and adjust
1032 its offset. */
1033 if (count < 15)
1034 memcpy (fragP->fr_literal + fragP->fr_fix,
1035 patt[count - 1], count);
1036 else
1037 {
1038 memcpy (fragP->fr_literal + fragP->fr_fix,
1039 jump_31, count);
1040 /* Adjust jump offset. */
1041 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1042 }
1043 }
1044 else
1045 {
1046 /* Maximum length of an instruction is 15 byte. If the
1047 padding is greater than 15 bytes and we don't use jump,
1048 we have to break it into smaller pieces. */
1049 int padding = count;
1050 while (padding > 15)
1051 {
1052 padding -= 15;
1053 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1054 patt [14], 15);
1055 }
1056
1057 if (padding)
1058 memcpy (fragP->fr_literal + fragP->fr_fix,
1059 patt [padding - 1], padding);
1060 }
ccc9c027 1061 }
33fef721 1062 fragP->fr_var = count;
252b5132
RH		 1063}
1064
c6fb90c8 1065static INLINE int
0dfbf9d7 1066operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1067{
0dfbf9d7 1068 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1069 {
1070 case 3:
0dfbf9d7 1071 if (x->array[2])
c6fb90c8
L		 1072 return 0;
1073 case 2:
0dfbf9d7 1074 if (x->array[1])
c6fb90c8
L		 1075 return 0;
1076 case 1:
0dfbf9d7 1077 return !x->array[0];
c6fb90c8
L		 1078 default:
1079 abort ();
1080 }
40fb9820
L		 1081}
1082
c6fb90c8 1083static INLINE void
0dfbf9d7 1084operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1085{
0dfbf9d7 1086 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1087 {
1088 case 3:
0dfbf9d7 1089 x->array[2] = v;
c6fb90c8 1090 case 2:
0dfbf9d7 1091 x->array[1] = v;
c6fb90c8 1092 case 1:
0dfbf9d7 1093 x->array[0] = v;
c6fb90c8
L		 1094 break;
1095 default:
1096 abort ();
1097 }
1098}
40fb9820 1099
c6fb90c8 1100static INLINE int
0dfbf9d7
L		 1101operand_type_equal (const union i386_operand_type *x,
1102 const union i386_operand_type *y)
c6fb90c8 1103{
0dfbf9d7 1104 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1105 {
1106 case 3:
0dfbf9d7 1107 if (x->array[2] != y->array[2])
c6fb90c8
L		 1108 return 0;
1109 case 2:
0dfbf9d7 1110 if (x->array[1] != y->array[1])
c6fb90c8
L		 1111 return 0;
1112 case 1:
0dfbf9d7 1113 return x->array[0] == y->array[0];
c6fb90c8
L		 1114 break;
1115 default:
1116 abort ();
1117 }
1118}
40fb9820 1119
0dfbf9d7
L		 1120static INLINE int
1121cpu_flags_all_zero (const union i386_cpu_flags *x)
1122{
1123 switch (ARRAY_SIZE(x->array))
1124 {
1125 case 3:
1126 if (x->array[2])
1127 return 0;
1128 case 2:
1129 if (x->array[1])
1130 return 0;
1131 case 1:
1132 return !x->array[0];
1133 default:
1134 abort ();
1135 }
1136}
1137
1138static INLINE void
1139cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1140{
1141 switch (ARRAY_SIZE(x->array))
1142 {
1143 case 3:
1144 x->array[2] = v;
1145 case 2:
1146 x->array[1] = v;
1147 case 1:
1148 x->array[0] = v;
1149 break;
1150 default:
1151 abort ();
1152 }
1153}
1154
1155static INLINE int
1156cpu_flags_equal (const union i386_cpu_flags *x,
1157 const union i386_cpu_flags *y)
1158{
1159 switch (ARRAY_SIZE(x->array))
1160 {
1161 case 3:
1162 if (x->array[2] != y->array[2])
1163 return 0;
1164 case 2:
1165 if (x->array[1] != y->array[1])
1166 return 0;
1167 case 1:
1168 return x->array[0] == y->array[0];
1169 break;
1170 default:
1171 abort ();
1172 }
1173}
c6fb90c8
L		 1174
1175static INLINE int
1176cpu_flags_check_cpu64 (i386_cpu_flags f)
1177{
1178 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1179 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1180}
1181
c6fb90c8
L		 1182static INLINE i386_cpu_flags
1183cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1184{
c6fb90c8
L		 1185 switch (ARRAY_SIZE (x.array))
1186 {
1187 case 3:
1188 x.array [2] &= y.array [2];
1189 case 2:
1190 x.array [1] &= y.array [1];
1191 case 1:
1192 x.array [0] &= y.array [0];
1193 break;
1194 default:
1195 abort ();
1196 }
1197 return x;
1198}
40fb9820 1199
c6fb90c8
L		 1200static INLINE i386_cpu_flags
1201cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1202{
c6fb90c8 1203 switch (ARRAY_SIZE (x.array))
40fb9820 1204 {
c6fb90c8
L		 1205 case 3:
1206 x.array [2] |= y.array [2];
1207 case 2:
1208 x.array [1] |= y.array [1];
1209 case 1:
1210 x.array [0] |= y.array [0];
40fb9820
L		 1211 break;
1212 default:
1213 abort ();
1214 }
40fb9820
L		 1215 return x;
1216}
1217
c0f3af97
L		 1218#define CPU_FLAGS_ARCH_MATCH 0x1
1219#define CPU_FLAGS_64BIT_MATCH 0x2
1220
1221#define CPU_FLAGS_32BIT_MATCH CPU_FLAGS_ARCH_MATCH
1222#define CPU_FLAGS_PERFECT_MATCH \
1223 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1224
1225/* Return CPU flags match bits. */
3629bb00 1226
40fb9820 1227static int
c0f3af97 1228cpu_flags_match (const template *t)
40fb9820 1229{
c0f3af97
L		 1230 i386_cpu_flags x = t->cpu_flags;
1231 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1232
1233 x.bitfield.cpu64 = 0;
1234 x.bitfield.cpuno64 = 0;
1235
0dfbf9d7 1236 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1237 {
1238 /* This instruction is available on all archs. */
1239 match |= CPU_FLAGS_32BIT_MATCH;
1240 }
3629bb00
L		 1241 else
1242 {
c0f3af97 1243 /* This instruction is available only on some archs. */
3629bb00
L		 1244 i386_cpu_flags cpu = cpu_arch_flags;
1245
1246 cpu.bitfield.cpu64 = 0;
1247 cpu.bitfield.cpuno64 = 0;
1248 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1249 if (!cpu_flags_all_zero (&cpu))
1250 {
1251 /* Check SSE2AVX */
1252 if (!t->opcode_modifier.sse2avx || sse2avx)
1253 match |= CPU_FLAGS_32BIT_MATCH;
1254 }
3629bb00 1255 }
c0f3af97 1256 return match;
40fb9820
L		 1257}
1258
c6fb90c8
L		 1259static INLINE i386_operand_type
1260operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1261{
c6fb90c8
L		 1262 switch (ARRAY_SIZE (x.array))
1263 {
1264 case 3:
1265 x.array [2] &= y.array [2];
1266 case 2:
1267 x.array [1] &= y.array [1];
1268 case 1:
1269 x.array [0] &= y.array [0];
1270 break;
1271 default:
1272 abort ();
1273 }
1274 return x;
40fb9820
L		 1275}
1276
c6fb90c8
L		 1277static INLINE i386_operand_type
1278operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1279{
c6fb90c8 1280 switch (ARRAY_SIZE (x.array))
40fb9820 1281 {
c6fb90c8
L		 1282 case 3:
1283 x.array [2] |= y.array [2];
1284 case 2:
1285 x.array [1] |= y.array [1];
1286 case 1:
1287 x.array [0] |= y.array [0];
40fb9820
L		 1288 break;
1289 default:
1290 abort ();
1291 }
c6fb90c8
L		 1292 return x;
1293}
40fb9820 1294
c6fb90c8
L		 1295static INLINE i386_operand_type
1296operand_type_xor (i386_operand_type x, i386_operand_type y)
1297{
1298 switch (ARRAY_SIZE (x.array))
1299 {
1300 case 3:
1301 x.array [2] ^= y.array [2];
1302 case 2:
1303 x.array [1] ^= y.array [1];
1304 case 1:
1305 x.array [0] ^= y.array [0];
1306 break;
1307 default:
1308 abort ();
1309 }
40fb9820
L		 1310 return x;
1311}
1312
1313static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1314static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1315static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1316static const i386_operand_type inoutportreg
1317 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1318static const i386_operand_type reg16_inoutportreg
1319 = OPERAND_TYPE_REG16_INOUTPORTREG;
1320static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1321static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1322static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1323static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1324static const i386_operand_type anydisp
1325 = OPERAND_TYPE_ANYDISP;
40fb9820 1326static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1327static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1328static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1329static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1330static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1331static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1332static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1333static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1334static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1335static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1336static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
c0f3af97 1337static const i386_operand_type vex_imm4 = OPERAND_TYPE_VEX_IMM4;
40fb9820
L		 1338
1339enum operand_type
1340{
1341 reg,
40fb9820
L		 1342 imm,
1343 disp,
1344 anymem
1345};
1346
c6fb90c8 1347static INLINE int
40fb9820
L		 1348operand_type_check (i386_operand_type t, enum operand_type c)
1349{
1350 switch (c)
1351 {
1352 case reg:
1353 return (t.bitfield.reg8
1354 || t.bitfield.reg16
1355 || t.bitfield.reg32
1356 || t.bitfield.reg64);
1357
40fb9820
L		 1358 case imm:
1359 return (t.bitfield.imm8
1360 || t.bitfield.imm8s
1361 || t.bitfield.imm16
1362 || t.bitfield.imm32
1363 || t.bitfield.imm32s
1364 || t.bitfield.imm64);
1365
1366 case disp:
1367 return (t.bitfield.disp8
1368 || t.bitfield.disp16
1369 || t.bitfield.disp32
1370 || t.bitfield.disp32s
1371 || t.bitfield.disp64);
1372
1373 case anymem:
1374 return (t.bitfield.disp8
1375 || t.bitfield.disp16
1376 || t.bitfield.disp32
1377 || t.bitfield.disp32s
1378 || t.bitfield.disp64
1379 || t.bitfield.baseindex);
1380
1381 default:
1382 abort ();
1383 }
1384}
1385
5c07affc
L		 1386/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1387 operand J for instruction template T. */
1388
1389static INLINE int
1390match_reg_size (const template *t, unsigned int j)
1391{
1392 return !((i.types[j].bitfield.byte
1393 && !t->operand_types[j].bitfield.byte)
1394 || (i.types[j].bitfield.word
1395 && !t->operand_types[j].bitfield.word)
1396 || (i.types[j].bitfield.dword
1397 && !t->operand_types[j].bitfield.dword)
1398 || (i.types[j].bitfield.qword
1399 && !t->operand_types[j].bitfield.qword));
1400}
1401
1402/* Return 1 if there is no conflict in any size on operand J for
1403 instruction template T. */
1404
1405static INLINE int
1406match_mem_size (const template *t, unsigned int j)
1407{
1408 return (match_reg_size (t, j)
1409 && !((i.types[j].bitfield.unspecified
1410 && !t->operand_types[j].bitfield.unspecified)
1411 || (i.types[j].bitfield.fword
1412 && !t->operand_types[j].bitfield.fword)
1413 || (i.types[j].bitfield.tbyte
1414 && !t->operand_types[j].bitfield.tbyte)
1415 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1416 && !t->operand_types[j].bitfield.xmmword)
1417 || (i.types[j].bitfield.ymmword
1418 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1419}
1420
1421/* Return 1 if there is no size conflict on any operands for
1422 instruction template T. */
1423
1424static INLINE int
1425operand_size_match (const template *t)
1426{
1427 unsigned int j;
1428 int match = 1;
1429
1430 /* Don't check jump instructions. */
1431 if (t->opcode_modifier.jump
1432 || t->opcode_modifier.jumpbyte
1433 || t->opcode_modifier.jumpdword
1434 || t->opcode_modifier.jumpintersegment)
1435 return match;
1436
1437 /* Check memory and accumulator operand size. */
1438 for (j = 0; j < i.operands; j++)
1439 {
1440 if (t->operand_types[j].bitfield.anysize)
1441 continue;
1442
1443 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1444 {
1445 match = 0;
1446 break;
1447 }
1448
1449 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1450 {
1451 match = 0;
1452 break;
1453 }
1454 }
1455
1456 if (match
1457 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1458 return match;
1459
1460 /* Check reverse. */
1461 assert (i.operands == 2);
1462
1463 match = 1;
1464 for (j = 0; j < 2; j++)
1465 {
1466 if (t->operand_types[j].bitfield.acc
1467 && !match_reg_size (t, j ? 0 : 1))
1468 {
1469 match = 0;
1470 break;
1471 }
1472
1473 if (i.types[j].bitfield.mem
1474 && !match_mem_size (t, j ? 0 : 1))
1475 {
1476 match = 0;
1477 break;
1478 }
1479 }
1480
1481 return match;
1482}
1483
c6fb90c8 1484static INLINE int
40fb9820
L		 1485operand_type_match (i386_operand_type overlap,
1486 i386_operand_type given)
1487{
1488 i386_operand_type temp = overlap;
1489
1490 temp.bitfield.jumpabsolute = 0;
7d5e4556 1491 temp.bitfield.unspecified = 0;
5c07affc
L		 1492 temp.bitfield.byte = 0;
1493 temp.bitfield.word = 0;
1494 temp.bitfield.dword = 0;
1495 temp.bitfield.fword = 0;
1496 temp.bitfield.qword = 0;
1497 temp.bitfield.tbyte = 0;
1498 temp.bitfield.xmmword = 0;
c0f3af97 1499 temp.bitfield.ymmword = 0;
0dfbf9d7 1500 if (operand_type_all_zero (&temp))
40fb9820
L		 1501 return 0;
1502
1503 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1504 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1505}
1506
7d5e4556 1507/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1508 unless the expected operand type register overlap is null.
1509 Note that Acc in a template matches every size of reg. */
1510
c6fb90c8 1511static INLINE int
40fb9820
L		 1512operand_type_register_match (i386_operand_type m0,
1513 i386_operand_type g0,
1514 i386_operand_type t0,
1515 i386_operand_type m1,
1516 i386_operand_type g1,
1517 i386_operand_type t1)
1518{
1519 if (!operand_type_check (g0, reg))
1520 return 1;
1521
1522 if (!operand_type_check (g1, reg))
1523 return 1;
1524
1525 if (g0.bitfield.reg8 == g1.bitfield.reg8
1526 && g0.bitfield.reg16 == g1.bitfield.reg16
1527 && g0.bitfield.reg32 == g1.bitfield.reg32
1528 && g0.bitfield.reg64 == g1.bitfield.reg64)
1529 return 1;
1530
1531 if (m0.bitfield.acc)
1532 {
1533 t0.bitfield.reg8 = 1;
1534 t0.bitfield.reg16 = 1;
1535 t0.bitfield.reg32 = 1;
1536 t0.bitfield.reg64 = 1;
1537 }
1538
1539 if (m1.bitfield.acc)
1540 {
1541 t1.bitfield.reg8 = 1;
1542 t1.bitfield.reg16 = 1;
1543 t1.bitfield.reg32 = 1;
1544 t1.bitfield.reg64 = 1;
1545 }
1546
1547 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1548 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1549 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1550 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1551}
1552
252b5132 1553static INLINE unsigned int
40fb9820 1554mode_from_disp_size (i386_operand_type t)
252b5132 1555{
40fb9820
L		 1556 if (t.bitfield.disp8)
1557 return 1;
1558 else if (t.bitfield.disp16
1559 || t.bitfield.disp32
1560 || t.bitfield.disp32s)
1561 return 2;
1562 else
1563 return 0;
252b5132
RH		 1564}
1565
1566static INLINE int
e3bb37b5 1567fits_in_signed_byte (offsetT num)
252b5132
RH		 1568{
1569 return (num >= -128) && (num <= 127);
47926f60 1570}
252b5132
RH		 1571
1572static INLINE int
e3bb37b5 1573fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1574{
1575 return (num & 0xff) == num;
47926f60 1576}
252b5132
RH		 1577
1578static INLINE int
e3bb37b5 1579fits_in_unsigned_word (offsetT num)
252b5132
RH		 1580{
1581 return (num & 0xffff) == num;
47926f60 1582}
252b5132
RH		 1583
1584static INLINE int
e3bb37b5 1585fits_in_signed_word (offsetT num)
252b5132
RH		 1586{
1587 return (-32768 <= num) && (num <= 32767);
47926f60 1588}
2a962e6d 1589
3e73aa7c 1590static INLINE int
e3bb37b5 1591fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1592{
1593#ifndef BFD64
1594 return 1;
1595#else
1596 return (!(((offsetT) -1 << 31) & num)
1597 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1598#endif
1599} /* fits_in_signed_long() */
2a962e6d 1600
3e73aa7c 1601static INLINE int
e3bb37b5 1602fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1603{
1604#ifndef BFD64
1605 return 1;
1606#else
1607 return (num & (((offsetT) 2 << 31) - 1)) == num;
1608#endif
1609} /* fits_in_unsigned_long() */
252b5132 1610
c0f3af97
L		 1611static INLINE int
1612fits_in_imm4 (offsetT num)
1613{
1614 return (num & 0xf) == num;
1615}
1616
40fb9820 1617static i386_operand_type
e3bb37b5 1618smallest_imm_type (offsetT num)
252b5132 1619{
40fb9820
L		 1620 i386_operand_type t;
1621
0dfbf9d7 1622 operand_type_set (&t, 0);
40fb9820
L		 1623 t.bitfield.imm64 = 1;
1624
1625 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1626 {
1627 /* This code is disabled on the 486 because all the Imm1 forms
1628 in the opcode table are slower on the i486. They're the
1629 versions with the implicitly specified single-position
1630 displacement, which has another syntax if you really want to
1631 use that form. */
40fb9820
L		 1632 t.bitfield.imm1 = 1;
1633 t.bitfield.imm8 = 1;
1634 t.bitfield.imm8s = 1;
1635 t.bitfield.imm16 = 1;
1636 t.bitfield.imm32 = 1;
1637 t.bitfield.imm32s = 1;
1638 }
1639 else if (fits_in_signed_byte (num))
1640 {
1641 t.bitfield.imm8 = 1;
1642 t.bitfield.imm8s = 1;
1643 t.bitfield.imm16 = 1;
1644 t.bitfield.imm32 = 1;
1645 t.bitfield.imm32s = 1;
1646 }
1647 else if (fits_in_unsigned_byte (num))
1648 {
1649 t.bitfield.imm8 = 1;
1650 t.bitfield.imm16 = 1;
1651 t.bitfield.imm32 = 1;
1652 t.bitfield.imm32s = 1;
1653 }
1654 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1655 {
1656 t.bitfield.imm16 = 1;
1657 t.bitfield.imm32 = 1;
1658 t.bitfield.imm32s = 1;
1659 }
1660 else if (fits_in_signed_long (num))
1661 {
1662 t.bitfield.imm32 = 1;
1663 t.bitfield.imm32s = 1;
1664 }
1665 else if (fits_in_unsigned_long (num))
1666 t.bitfield.imm32 = 1;
1667
1668 return t;
47926f60 1669}
252b5132 1670
847f7ad4 1671static offsetT
e3bb37b5 1672offset_in_range (offsetT val, int size)
847f7ad4 1673{
508866be 1674 addressT mask;
ba2adb93 1675
847f7ad4
AM		 1676 switch (size)
1677 {
508866be
L		 1678 case 1: mask = ((addressT) 1 << 8) - 1; break;
1679 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1680 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1681#ifdef BFD64
1682 case 8: mask = ((addressT) 2 << 63) - 1; break;
1683#endif
47926f60 1684 default: abort ();
847f7ad4
AM		 1685 }
1686
ba2adb93 1687 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1688 if (!use_rela_relocations)
1689 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1690 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1691
47926f60 1692 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1693 {
1694 char buf1[40], buf2[40];
1695
1696 sprint_value (buf1, val);
1697 sprint_value (buf2, val & mask);
1698 as_warn (_("%s shortened to %s"), buf1, buf2);
1699 }
1700 return val & mask;
1701}
1702
252b5132
RH		 1703/* Returns 0 if attempting to add a prefix where one from the same
1704 class already exists, 1 if non rep/repne added, 2 if rep/repne
1705 added. */
1706static int
e3bb37b5 1707add_prefix (unsigned int prefix)
252b5132
RH		 1708{
1709 int ret = 1;
b1905489 1710 unsigned int q;
252b5132 1711
29b0f896
AM		 1712 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1713 && flag_code == CODE_64BIT)
b1905489 1714 {
161a04f6
L		 1715 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1716 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1717 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1718 ret = 0;
1719 q = REX_PREFIX;
1720 }
3e73aa7c 1721 else
b1905489
JB		 1722 {
1723 switch (prefix)
1724 {
1725 default:
1726 abort ();
1727
1728 case CS_PREFIX_OPCODE:
1729 case DS_PREFIX_OPCODE:
1730 case ES_PREFIX_OPCODE:
1731 case FS_PREFIX_OPCODE:
1732 case GS_PREFIX_OPCODE:
1733 case SS_PREFIX_OPCODE:
1734 q = SEG_PREFIX;
1735 break;
1736
1737 case REPNE_PREFIX_OPCODE:
1738 case REPE_PREFIX_OPCODE:
1739 ret = 2;
1740 /* fall thru */
1741 case LOCK_PREFIX_OPCODE:
1742 q = LOCKREP_PREFIX;
1743 break;
1744
1745 case FWAIT_OPCODE:
1746 q = WAIT_PREFIX;
1747 break;
1748
1749 case ADDR_PREFIX_OPCODE:
1750 q = ADDR_PREFIX;
1751 break;
1752
1753 case DATA_PREFIX_OPCODE:
1754 q = DATA_PREFIX;
1755 break;
1756 }
1757 if (i.prefix[q] != 0)
1758 ret = 0;
1759 }
252b5132 1760
b1905489 1761 if (ret)
252b5132 1762 {
b1905489
JB		 1763 if (!i.prefix[q])
1764 ++i.prefixes;
1765 i.prefix[q] |= prefix;
252b5132 1766 }
b1905489
JB		 1767 else
1768 as_bad (_("same type of prefix used twice"));
252b5132 1769
252b5132
RH		 1770 return ret;
1771}
1772
1773static void
e3bb37b5 1774set_code_flag (int value)
eecb386c 1775{
3e73aa7c 1776 flag_code = value;
40fb9820
L		 1777 if (flag_code == CODE_64BIT)
1778 {
1779 cpu_arch_flags.bitfield.cpu64 = 1;
1780 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1781 }
1782 else
1783 {
1784 cpu_arch_flags.bitfield.cpu64 = 0;
1785 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1786 }
1787 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1788 {
1789 as_bad (_("64bit mode not supported on this CPU."));
1790 }
40fb9820 1791 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1792 {
1793 as_bad (_("32bit mode not supported on this CPU."));
1794 }
eecb386c
AM		 1795 stackop_size = '\0';
1796}
1797
1798static void
e3bb37b5 1799set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1800{
3e73aa7c 1801 flag_code = new_code_flag;
40fb9820
L		 1802 if (flag_code != CODE_16BIT)
1803 abort ();
1804 cpu_arch_flags.bitfield.cpu64 = 0;
1805 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1806 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1807}
1808
1809static void
e3bb37b5 1810set_intel_syntax (int syntax_flag)
252b5132
RH		 1811{
1812 /* Find out if register prefixing is specified. */
1813 int ask_naked_reg = 0;
1814
1815 SKIP_WHITESPACE ();
29b0f896 1816 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1817 {
1818 char *string = input_line_pointer;
1819 int e = get_symbol_end ();
1820
47926f60 1821 if (strcmp (string, "prefix") == 0)
252b5132 1822 ask_naked_reg = 1;
47926f60 1823 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1824 ask_naked_reg = -1;
1825 else
d0b47220 1826 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1827 *input_line_pointer = e;
1828 }
1829 demand_empty_rest_of_line ();
c3332e24 1830
252b5132
RH		 1831 intel_syntax = syntax_flag;
1832
1833 if (ask_naked_reg == 0)
f86103b7
AM		 1834 allow_naked_reg = (intel_syntax
1835 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1836 else
1837 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1838
e4a3b5a4 1839 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1840 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1841 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1842}
1843
1efbbeb4
L		 1844static void
1845set_intel_mnemonic (int mnemonic_flag)
1846{
e1d4d893 1847 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1848}
1849
db51cc60
L		 1850static void
1851set_allow_index_reg (int flag)
1852{
1853 allow_index_reg = flag;
1854}
1855
cb19c032
L		 1856static void
1857set_sse_check (int dummy ATTRIBUTE_UNUSED)
1858{
1859 SKIP_WHITESPACE ();
1860
1861 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1862 {
1863 char *string = input_line_pointer;
1864 int e = get_symbol_end ();
1865
1866 if (strcmp (string, "none") == 0)
1867 sse_check = sse_check_none;
1868 else if (strcmp (string, "warning") == 0)
1869 sse_check = sse_check_warning;
1870 else if (strcmp (string, "error") == 0)
1871 sse_check = sse_check_error;
1872 else
1873 as_bad (_("bad argument to sse_check directive."));
1874 *input_line_pointer = e;
1875 }
1876 else
1877 as_bad (_("missing argument for sse_check directive"));
1878
1879 demand_empty_rest_of_line ();
1880}
1881
e413e4e9 1882static void
e3bb37b5 1883set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1884{
47926f60 1885 SKIP_WHITESPACE ();
e413e4e9 1886
29b0f896 1887 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1888 {
1889 char *string = input_line_pointer;
1890 int e = get_symbol_end ();
9103f4f4 1891 unsigned int i;
40fb9820 1892 i386_cpu_flags flags;
e413e4e9 1893
9103f4f4 1894 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1895 {
1896 if (strcmp (string, cpu_arch[i].name) == 0)
1897 {
5c6af06e
JB		 1898 if (*string != '.')
1899 {
1900 cpu_arch_name = cpu_arch[i].name;
1901 cpu_sub_arch_name = NULL;
40fb9820
L		 1902 cpu_arch_flags = cpu_arch[i].flags;
1903 if (flag_code == CODE_64BIT)
1904 {
1905 cpu_arch_flags.bitfield.cpu64 = 1;
1906 cpu_arch_flags.bitfield.cpuno64 = 0;
1907 }
1908 else
1909 {
1910 cpu_arch_flags.bitfield.cpu64 = 0;
1911 cpu_arch_flags.bitfield.cpuno64 = 1;
1912 }
ccc9c027 1913 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1914 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1915 if (!cpu_arch_tune_set)
1916 {
1917 cpu_arch_tune = cpu_arch_isa;
1918 cpu_arch_tune_flags = cpu_arch_isa_flags;
1919 }
5c6af06e
JB		 1920 break;
1921 }
40fb9820 1922
c6fb90c8
L		 1923 flags = cpu_flags_or (cpu_arch_flags,
1924 cpu_arch[i].flags);
0dfbf9d7 1925 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 1926 {
6305a203
L		 1927 if (cpu_sub_arch_name)
1928 {
1929 char *name = cpu_sub_arch_name;
1930 cpu_sub_arch_name = concat (name,
1931 cpu_arch[i].name,
1bf57e9f 1932 (const char *) NULL);
6305a203
L		 1933 free (name);
1934 }
1935 else
1936 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 1937 cpu_arch_flags = flags;
5c6af06e
JB		 1938 }
1939 *input_line_pointer = e;
1940 demand_empty_rest_of_line ();
1941 return;
e413e4e9
AM		 1942 }
1943 }
9103f4f4 1944 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1945 as_bad (_("no such architecture: `%s'"), string);
1946
1947 *input_line_pointer = e;
1948 }
1949 else
1950 as_bad (_("missing cpu architecture"));
1951
fddf5b5b
AM		 1952 no_cond_jump_promotion = 0;
1953 if (*input_line_pointer == ','
29b0f896 1954 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1955 {
1956 char *string = ++input_line_pointer;
1957 int e = get_symbol_end ();
1958
1959 if (strcmp (string, "nojumps") == 0)
1960 no_cond_jump_promotion = 1;
1961 else if (strcmp (string, "jumps") == 0)
1962 ;
1963 else
1964 as_bad (_("no such architecture modifier: `%s'"), string);
1965
1966 *input_line_pointer = e;
1967 }
1968
e413e4e9
AM		 1969 demand_empty_rest_of_line ();
1970}
1971
b9d79e03
JH		 1972unsigned long
1973i386_mach ()
1974{
1975 if (!strcmp (default_arch, "x86_64"))
1976 return bfd_mach_x86_64;
1977 else if (!strcmp (default_arch, "i386"))
1978 return bfd_mach_i386_i386;
1979 else
1980 as_fatal (_("Unknown architecture"));
1981}
b9d79e03 1982\f
252b5132
RH		 1983void
1984md_begin ()
1985{
1986 const char *hash_err;
1987
47926f60 1988 /* Initialize op_hash hash table. */
252b5132
RH		 1989 op_hash = hash_new ();
1990
1991 {
29b0f896
AM		 1992 const template *optab;
1993 templates *core_optab;
252b5132 1994
47926f60
KH		 1995 /* Setup for loop. */
1996 optab = i386_optab;
252b5132
RH		 1997 core_optab = (templates *) xmalloc (sizeof (templates));
1998 core_optab->start = optab;
1999
2000 while (1)
2001 {
2002 ++optab;
2003 if (optab->name == NULL
2004 || strcmp (optab->name, (optab - 1)->name) != 0)
2005 {
2006 /* different name --> ship out current template list;
47926f60 2007 add to hash table; & begin anew. */
252b5132
RH		 2008 core_optab->end = optab;
2009 hash_err = hash_insert (op_hash,
2010 (optab - 1)->name,
2011 (PTR) core_optab);
2012 if (hash_err)
2013 {
252b5132
RH		 2014 as_fatal (_("Internal Error: Can't hash %s: %s"),
2015 (optab - 1)->name,
2016 hash_err);
2017 }
2018 if (optab->name == NULL)
2019 break;
2020 core_optab = (templates *) xmalloc (sizeof (templates));
2021 core_optab->start = optab;
2022 }
2023 }
2024 }
2025
47926f60 2026 /* Initialize reg_hash hash table. */
252b5132
RH		 2027 reg_hash = hash_new ();
2028 {
29b0f896 2029 const reg_entry *regtab;
c3fe08fa 2030 unsigned int regtab_size = i386_regtab_size;
252b5132 2031
c3fe08fa 2032 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 2033 {
2034 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
2035 if (hash_err)
3e73aa7c
JH		 2036 as_fatal (_("Internal Error: Can't hash %s: %s"),
2037 regtab->reg_name,
2038 hash_err);
252b5132
RH		 2039 }
2040 }
2041
47926f60 2042 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2043 {
29b0f896
AM		 2044 int c;
2045 char *p;
252b5132
RH		 2046
2047 for (c = 0; c < 256; c++)
2048 {
3882b010 2049 if (ISDIGIT (c))
252b5132
RH		 2050 {
2051 digit_chars[c] = c;
2052 mnemonic_chars[c] = c;
2053 register_chars[c] = c;
2054 operand_chars[c] = c;
2055 }
3882b010 2056 else if (ISLOWER (c))
252b5132
RH		 2057 {
2058 mnemonic_chars[c] = c;
2059 register_chars[c] = c;
2060 operand_chars[c] = c;
2061 }
3882b010 2062 else if (ISUPPER (c))
252b5132 2063 {
3882b010 2064 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2065 register_chars[c] = mnemonic_chars[c];
2066 operand_chars[c] = c;
2067 }
2068
3882b010 2069 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2070 identifier_chars[c] = c;
2071 else if (c >= 128)
2072 {
2073 identifier_chars[c] = c;
2074 operand_chars[c] = c;
2075 }
2076 }
2077
2078#ifdef LEX_AT
2079 identifier_chars['@'] = '@';
32137342
NC		 2080#endif
2081#ifdef LEX_QM
2082 identifier_chars['?'] = '?';
2083 operand_chars['?'] = '?';
252b5132 2084#endif
252b5132 2085 digit_chars['-'] = '-';
c0f3af97 2086 mnemonic_chars['_'] = '_';
791fe849 2087 mnemonic_chars['-'] = '-';
0003779b 2088 mnemonic_chars['.'] = '.';
252b5132
RH		 2089 identifier_chars['_'] = '_';
2090 identifier_chars['.'] = '.';
2091
2092 for (p = operand_special_chars; *p != '\0'; p++)
2093 operand_chars[(unsigned char) *p] = *p;
2094 }
2095
2096#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2097 if (IS_ELF)
252b5132
RH		 2098 {
2099 record_alignment (text_section, 2);
2100 record_alignment (data_section, 2);
2101 record_alignment (bss_section, 2);
2102 }
2103#endif
a4447b93
RH		 2104
2105 if (flag_code == CODE_64BIT)
2106 {
2107 x86_dwarf2_return_column = 16;
2108 x86_cie_data_alignment = -8;
2109 }
2110 else
2111 {
2112 x86_dwarf2_return_column = 8;
2113 x86_cie_data_alignment = -4;
2114 }
252b5132
RH		 2115}
2116
2117void
e3bb37b5 2118i386_print_statistics (FILE *file)
252b5132
RH		 2119{
2120 hash_print_statistics (file, "i386 opcode", op_hash);
2121 hash_print_statistics (file, "i386 register", reg_hash);
2122}
2123\f
252b5132
RH		 2124#ifdef DEBUG386
2125
ce8a8b2f 2126/* Debugging routines for md_assemble. */
e3bb37b5 2127static void pte (template *);
40fb9820 2128static void pt (i386_operand_type);
e3bb37b5
L		 2129static void pe (expressionS *);
2130static void ps (symbolS *);
252b5132
RH		 2131
2132static void
e3bb37b5 2133pi (char *line, i386_insn *x)
252b5132 2134{
09f131f2 2135 unsigned int i;
252b5132
RH		 2136
2137 fprintf (stdout, "%s: template ", line);
2138 pte (&x->tm);
09f131f2
JH		 2139 fprintf (stdout, " address: base %s index %s scale %x\n",
2140 x->base_reg ? x->base_reg->reg_name : "none",
2141 x->index_reg ? x->index_reg->reg_name : "none",
2142 x->log2_scale_factor);
2143 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2144 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2145 fprintf (stdout, " sib: base %x index %x scale %x\n",
2146 x->sib.base, x->sib.index, x->sib.scale);
2147 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2148 (x->rex & REX_W) != 0,
2149 (x->rex & REX_R) != 0,
2150 (x->rex & REX_X) != 0,
2151 (x->rex & REX_B) != 0);
85f10a01
MM		 2152 fprintf (stdout, " drex: reg %d rex 0x%x\n",
2153 x->drex.reg, x->drex.rex);
252b5132
RH		 2154 for (i = 0; i < x->operands; i++)
2155 {
2156 fprintf (stdout, " #%d: ", i + 1);
2157 pt (x->types[i]);
2158 fprintf (stdout, "\n");
40fb9820
L		 2159 if (x->types[i].bitfield.reg8
2160 || x->types[i].bitfield.reg16
2161 || x->types[i].bitfield.reg32
2162 || x->types[i].bitfield.reg64
2163 || x->types[i].bitfield.regmmx
2164 || x->types[i].bitfield.regxmm
c0f3af97 2165 || x->types[i].bitfield.regymm
40fb9820
L		 2166 || x->types[i].bitfield.sreg2
2167 || x->types[i].bitfield.sreg3
2168 || x->types[i].bitfield.control
2169 || x->types[i].bitfield.debug
2170 || x->types[i].bitfield.test)
520dc8e8 2171 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2172 if (operand_type_check (x->types[i], imm))
520dc8e8 2173 pe (x->op[i].imms);
40fb9820 2174 if (operand_type_check (x->types[i], disp))
520dc8e8 2175 pe (x->op[i].disps);
252b5132
RH		 2176 }
2177}
2178
2179static void
e3bb37b5 2180pte (template *t)
252b5132 2181{
09f131f2 2182 unsigned int i;
252b5132 2183 fprintf (stdout, " %d operands ", t->operands);
47926f60 2184 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2185 if (t->extension_opcode != None)
2186 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2187 if (t->opcode_modifier.d)
252b5132 2188 fprintf (stdout, "D");
40fb9820 2189 if (t->opcode_modifier.w)
252b5132
RH		 2190 fprintf (stdout, "W");
2191 fprintf (stdout, "\n");
2192 for (i = 0; i < t->operands; i++)
2193 {
2194 fprintf (stdout, " #%d type ", i + 1);
2195 pt (t->operand_types[i]);
2196 fprintf (stdout, "\n");
2197 }
2198}
2199
2200static void
e3bb37b5 2201pe (expressionS *e)
252b5132 2202{
24eab124 2203 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2204 fprintf (stdout, " add_number %ld (%lx)\n",
2205 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2206 if (e->X_add_symbol)
2207 {
2208 fprintf (stdout, " add_symbol ");
2209 ps (e->X_add_symbol);
2210 fprintf (stdout, "\n");
2211 }
2212 if (e->X_op_symbol)
2213 {
2214 fprintf (stdout, " op_symbol ");
2215 ps (e->X_op_symbol);
2216 fprintf (stdout, "\n");
2217 }
2218}
2219
2220static void
e3bb37b5 2221ps (symbolS *s)
252b5132
RH		 2222{
2223 fprintf (stdout, "%s type %s%s",
2224 S_GET_NAME (s),
2225 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2226 segment_name (S_GET_SEGMENT (s)));
2227}
2228
7b81dfbb 2229static struct type_name
252b5132 2230 {
40fb9820
L		 2231 i386_operand_type mask;
2232 const char *name;
252b5132 2233 }
7b81dfbb 2234const type_names[] =
252b5132 2235{
40fb9820
L		 2236 { OPERAND_TYPE_REG8, "r8" },
2237 { OPERAND_TYPE_REG16, "r16" },
2238 { OPERAND_TYPE_REG32, "r32" },
2239 { OPERAND_TYPE_REG64, "r64" },
2240 { OPERAND_TYPE_IMM8, "i8" },
2241 { OPERAND_TYPE_IMM8, "i8s" },
2242 { OPERAND_TYPE_IMM16, "i16" },
2243 { OPERAND_TYPE_IMM32, "i32" },
2244 { OPERAND_TYPE_IMM32S, "i32s" },
2245 { OPERAND_TYPE_IMM64, "i64" },
2246 { OPERAND_TYPE_IMM1, "i1" },
2247 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2248 { OPERAND_TYPE_DISP8, "d8" },
2249 { OPERAND_TYPE_DISP16, "d16" },
2250 { OPERAND_TYPE_DISP32, "d32" },
2251 { OPERAND_TYPE_DISP32S, "d32s" },
2252 { OPERAND_TYPE_DISP64, "d64" },
2253 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2254 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2255 { OPERAND_TYPE_CONTROL, "control reg" },
2256 { OPERAND_TYPE_TEST, "test reg" },
2257 { OPERAND_TYPE_DEBUG, "debug reg" },
2258 { OPERAND_TYPE_FLOATREG, "FReg" },
2259 { OPERAND_TYPE_FLOATACC, "FAcc" },
2260 { OPERAND_TYPE_SREG2, "SReg2" },
2261 { OPERAND_TYPE_SREG3, "SReg3" },
2262 { OPERAND_TYPE_ACC, "Acc" },
2263 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2264 { OPERAND_TYPE_REGMMX, "rMMX" },
2265 { OPERAND_TYPE_REGXMM, "rXMM" },
2266 { OPERAND_TYPE_ESSEG, "es" },
c0f3af97 2267 { OPERAND_TYPE_VEX_IMM4, "VEX i4" },
252b5132
RH		 2268};
2269
2270static void
40fb9820 2271pt (i386_operand_type t)
252b5132 2272{
40fb9820 2273 unsigned int j;
c6fb90c8 2274 i386_operand_type a;
252b5132 2275
40fb9820 2276 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2277 {
2278 a = operand_type_and (t, type_names[j].mask);
2279 if (!UINTS_ALL_ZERO (a))
2280 fprintf (stdout, "%s, ", type_names[j].name);
2281 }
252b5132
RH		 2282 fflush (stdout);
2283}
2284
2285#endif /* DEBUG386 */
2286\f
252b5132 2287static bfd_reloc_code_real_type
3956db08 2288reloc (unsigned int size,
64e74474
AM		 2289 int pcrel,
2290 int sign,
2291 bfd_reloc_code_real_type other)
252b5132 2292{
47926f60 2293 if (other != NO_RELOC)
3956db08
JB		 2294 {
2295 reloc_howto_type *reloc;
2296
2297 if (size == 8)
2298 switch (other)
2299 {
64e74474
AM		 2300 case BFD_RELOC_X86_64_GOT32:
2301 return BFD_RELOC_X86_64_GOT64;
2302 break;
2303 case BFD_RELOC_X86_64_PLTOFF64:
2304 return BFD_RELOC_X86_64_PLTOFF64;
2305 break;
2306 case BFD_RELOC_X86_64_GOTPC32:
2307 other = BFD_RELOC_X86_64_GOTPC64;
2308 break;
2309 case BFD_RELOC_X86_64_GOTPCREL:
2310 other = BFD_RELOC_X86_64_GOTPCREL64;
2311 break;
2312 case BFD_RELOC_X86_64_TPOFF32:
2313 other = BFD_RELOC_X86_64_TPOFF64;
2314 break;
2315 case BFD_RELOC_X86_64_DTPOFF32:
2316 other = BFD_RELOC_X86_64_DTPOFF64;
2317 break;
2318 default:
2319 break;
3956db08 2320 }
e05278af
JB		 2321
2322 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2323 if (size == 4 && flag_code != CODE_64BIT)
2324 sign = -1;
2325
3956db08
JB		 2326 reloc = bfd_reloc_type_lookup (stdoutput, other);
2327 if (!reloc)
2328 as_bad (_("unknown relocation (%u)"), other);
2329 else if (size != bfd_get_reloc_size (reloc))
2330 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2331 bfd_get_reloc_size (reloc),
2332 size);
2333 else if (pcrel && !reloc->pc_relative)
2334 as_bad (_("non-pc-relative relocation for pc-relative field"));
2335 else if ((reloc->complain_on_overflow == complain_overflow_signed
2336 && !sign)
2337 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2338 && sign > 0))
3956db08
JB		 2339 as_bad (_("relocated field and relocation type differ in signedness"));
2340 else
2341 return other;
2342 return NO_RELOC;
2343 }
252b5132
RH		 2344
2345 if (pcrel)
2346 {
3e73aa7c 2347 if (!sign)
3956db08 2348 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2349 switch (size)
2350 {
2351 case 1: return BFD_RELOC_8_PCREL;
2352 case 2: return BFD_RELOC_16_PCREL;
2353 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2354 case 8: return BFD_RELOC_64_PCREL;
252b5132 2355 }
3956db08 2356 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2357 }
2358 else
2359 {
3956db08 2360 if (sign > 0)
e5cb08ac 2361 switch (size)
3e73aa7c
JH		 2362 {
2363 case 4: return BFD_RELOC_X86_64_32S;
2364 }
2365 else
2366 switch (size)
2367 {
2368 case 1: return BFD_RELOC_8;
2369 case 2: return BFD_RELOC_16;
2370 case 4: return BFD_RELOC_32;
2371 case 8: return BFD_RELOC_64;
2372 }
3956db08
JB		 2373 as_bad (_("cannot do %s %u byte relocation"),
2374 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2375 }
2376
bfb32b52 2377 abort ();
252b5132
RH		 2378 return BFD_RELOC_NONE;
2379}
2380
47926f60
KH		 2381/* Here we decide which fixups can be adjusted to make them relative to
2382 the beginning of the section instead of the symbol. Basically we need
2383 to make sure that the dynamic relocations are done correctly, so in
2384 some cases we force the original symbol to be used. */
2385
252b5132 2386int
e3bb37b5 2387tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2388{
6d249963 2389#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2390 if (!IS_ELF)
31312f95
AM		 2391 return 1;
2392
a161fe53
AM		 2393 /* Don't adjust pc-relative references to merge sections in 64-bit
2394 mode. */
2395 if (use_rela_relocations
2396 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2397 && fixP->fx_pcrel)
252b5132 2398 return 0;
31312f95 2399
8d01d9a9
AJ		 2400 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2401 and changed later by validate_fix. */
2402 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2403 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2404 return 0;
2405
ce8a8b2f 2406 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2407 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2408 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2409 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2410 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2411 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2412 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2413 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2414 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2415 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2416 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2417 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2418 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2419 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2420 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2421 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2422 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2423 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2424 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2425 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2426 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2427 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2428 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2429 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2430 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2431 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2432 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2433 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2434 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2435 return 0;
31312f95 2436#endif
252b5132
RH		 2437 return 1;
2438}
252b5132 2439
b4cac588 2440static int
e3bb37b5 2441intel_float_operand (const char *mnemonic)
252b5132 2442{
9306ca4a
JB		 2443 /* Note that the value returned is meaningful only for opcodes with (memory)
2444 operands, hence the code here is free to improperly handle opcodes that
2445 have no operands (for better performance and smaller code). */
2446
2447 if (mnemonic[0] != 'f')
2448 return 0; /* non-math */
2449
2450 switch (mnemonic[1])
2451 {
2452 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2453 the fs segment override prefix not currently handled because no
2454 call path can make opcodes without operands get here */
2455 case 'i':
2456 return 2 /* integer op */;
2457 case 'l':
2458 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2459 return 3; /* fldcw/fldenv */
2460 break;
2461 case 'n':
2462 if (mnemonic[2] != 'o' /* fnop */)
2463 return 3; /* non-waiting control op */
2464 break;
2465 case 'r':
2466 if (mnemonic[2] == 's')
2467 return 3; /* frstor/frstpm */
2468 break;
2469 case 's':
2470 if (mnemonic[2] == 'a')
2471 return 3; /* fsave */
2472 if (mnemonic[2] == 't')
2473 {
2474 switch (mnemonic[3])
2475 {
2476 case 'c': /* fstcw */
2477 case 'd': /* fstdw */
2478 case 'e': /* fstenv */
2479 case 's': /* fsts[gw] */
2480 return 3;
2481 }
2482 }
2483 break;
2484 case 'x':
2485 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2486 return 0; /* fxsave/fxrstor are not really math ops */
2487 break;
2488 }
252b5132 2489
9306ca4a 2490 return 1;
252b5132
RH		 2491}
2492
c0f3af97
L		 2493/* Build the VEX prefix. */
2494
2495static void
2496build_vex_prefix (void)
2497{
2498 unsigned int register_specifier;
2499 unsigned int implied_prefix;
2500 unsigned int vector_length;
2501
2502 /* Check register specifier. */
2503 if (i.vex.register_specifier)
2504 {
2505 register_specifier = i.vex.register_specifier->reg_num;
2506 if ((i.vex.register_specifier->reg_flags & RegRex))
2507 register_specifier += 8;
2508 register_specifier = ~register_specifier & 0xf;
2509 }
2510 else
2511 register_specifier = 0xf;
2512
2513 vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0;
2514
2515 switch ((i.tm.base_opcode >> 8) & 0xff)
2516 {
2517 case 0:
2518 implied_prefix = 0;
2519 break;
2520 case DATA_PREFIX_OPCODE:
2521 implied_prefix = 1;
2522 break;
2523 case REPE_PREFIX_OPCODE:
2524 implied_prefix = 2;
2525 break;
2526 case REPNE_PREFIX_OPCODE:
2527 implied_prefix = 3;
2528 break;
2529 default:
2530 abort ();
2531 }
2532
2533 /* Use 2-byte VEX prefix if possible. */
2534 if (i.tm.opcode_modifier.vex0f
2535 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2536 {
2537 /* 2-byte VEX prefix. */
2538 unsigned int r;
2539
2540 i.vex.length = 2;
2541 i.vex.bytes[0] = 0xc5;
2542
2543 /* Check the REX.R bit. */
2544 r = (i.rex & REX_R) ? 0 : 1;
2545 i.vex.bytes[1] = (r << 7
2546 | register_specifier << 3
2547 | vector_length << 2
2548 | implied_prefix);
2549 }
2550 else
2551 {
2552 /* 3-byte VEX prefix. */
2553 unsigned int m, w;
2554
2555 if (i.tm.opcode_modifier.vex0f)
2556 m = 0x1;
2557 else if (i.tm.opcode_modifier.vex0f38)
2558 m = 0x2;
2559 else if (i.tm.opcode_modifier.vex0f3a)
2560 m = 0x3;
2561 else
2562 abort ();
2563
2564 i.vex.length = 3;
2565 i.vex.bytes[0] = 0xc4;
2566
2567 /* The high 3 bits of the second VEX byte are 1's compliment
2568 of RXB bits from REX. */
2569 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2570
2571 /* Check the REX.W bit. */
2572 w = (i.rex & REX_W) ? 1 : 0;
2573 if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1)
2574 {
2575 if (w)
2576 abort ();
2577
2578 if (i.tm.opcode_modifier.vexw1)
2579 w = 1;
2580 }
2581
2582 i.vex.bytes[2] = (w << 7
2583 | register_specifier << 3
2584 | vector_length << 2
2585 | implied_prefix);
2586 }
2587}
2588
65da13b5
L		 2589static void
2590process_immext (void)
2591{
2592 expressionS *exp;
2593
2594 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2595 {
1fed0ba1
L		 2596 /* SSE3 Instructions have the fixed operands with an opcode
2597 suffix which is coded in the same place as an 8-bit immediate
2598 field would be. Here we check those operands and remove them
2599 afterwards. */
65da13b5
L		 2600 unsigned int x;
2601
2602 for (x = 0; x < i.operands; x++)
2603 if (i.op[x].regs->reg_num != x)
2604 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2605 register_prefix, i.op[x].regs->reg_name, x + 1,
2606 i.tm.name);
2607
2608 i.operands = 0;
65da13b5
L		 2609 }
2610
c0f3af97 2611 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2612 which is coded in the same place as an 8-bit immediate field
2613 would be. Here we fake an 8-bit immediate operand from the
2614 opcode suffix stored in tm.extension_opcode.
2615
c0f3af97
L		 2616 SSE5 and AVX instructions also use this encoding, for some of
2617 3 argument instructions. */
65da13b5
L		 2618
2619 assert (i.imm_operands == 0
2620 && (i.operands <= 2
2621 || (i.tm.cpu_flags.bitfield.cpusse5
c0f3af97
L		 2622 && i.operands <= 3)
2623 || (i.tm.opcode_modifier.vex
2624 && i.operands <= 4)));
65da13b5
L		 2625
2626 exp = &im_expressions[i.imm_operands++];
2627 i.op[i.operands].imms = exp;
2628 i.types[i.operands] = imm8;
2629 i.operands++;
2630 exp->X_op = O_constant;
2631 exp->X_add_number = i.tm.extension_opcode;
2632 i.tm.extension_opcode = None;
2633}
2634
252b5132
RH		 2635/* This is the guts of the machine-dependent assembler. LINE points to a
2636 machine dependent instruction. This function is supposed to emit
2637 the frags/bytes it assembles to. */
2638
2639void
65da13b5 2640md_assemble (char *line)
252b5132 2641{
40fb9820 2642 unsigned int j;
252b5132
RH		 2643 char mnemonic[MAX_MNEM_SIZE];
2644
47926f60 2645 /* Initialize globals. */
252b5132
RH		 2646 memset (&i, '\0', sizeof (i));
2647 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2648 i.reloc[j] = NO_RELOC;
252b5132
RH		 2649 memset (disp_expressions, '\0', sizeof (disp_expressions));
2650 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2651 save_stack_p = save_stack;
252b5132
RH		 2652
2653 /* First parse an instruction mnemonic & call i386_operand for the operands.
2654 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2655 start of a (possibly prefixed) mnemonic. */
252b5132 2656
29b0f896
AM		 2657 line = parse_insn (line, mnemonic);
2658 if (line == NULL)
2659 return;
252b5132 2660
29b0f896
AM		 2661 line = parse_operands (line, mnemonic);
2662 if (line == NULL)
2663 return;
252b5132 2664
29b0f896
AM		 2665 /* Now we've parsed the mnemonic into a set of templates, and have the
2666 operands at hand. */
2667
2668 /* All intel opcodes have reversed operands except for "bound" and
2669 "enter". We also don't reverse intersegment "jmp" and "call"
2670 instructions with 2 immediate operands so that the immediate segment
050dfa73 2671 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2672 if (intel_syntax
2673 && i.operands > 1
29b0f896 2674 && (strcmp (mnemonic, "bound") != 0)
30123838 2675 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2676 && !(operand_type_check (i.types[0], imm)
2677 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2678 swap_operands ();
2679
ec56d5c0
JB		 2680 /* The order of the immediates should be reversed
2681 for 2 immediates extrq and insertq instructions */
2682 if (i.imm_operands == 2
2683 && (strcmp (mnemonic, "extrq") == 0
2684 || strcmp (mnemonic, "insertq") == 0))
2685 swap_2_operands (0, 1);
2686
29b0f896
AM		 2687 if (i.imm_operands)
2688 optimize_imm ();
2689
b300c311
L		 2690 /* Don't optimize displacement for movabs since it only takes 64bit
2691 displacement. */
2692 if (i.disp_operands
2693 && (flag_code != CODE_64BIT
2694 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2695 optimize_disp ();
2696
2697 /* Next, we find a template that matches the given insn,
2698 making sure the overlap of the given operands types is consistent
2699 with the template operand types. */
252b5132 2700
29b0f896
AM		 2701 if (!match_template ())
2702 return;
252b5132 2703
daf50ae7 2704 if (sse_check != sse_check_none
81f8a913 2705 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2706 && (i.tm.cpu_flags.bitfield.cpusse
2707 || i.tm.cpu_flags.bitfield.cpusse2
2708 || i.tm.cpu_flags.bitfield.cpusse3
2709 || i.tm.cpu_flags.bitfield.cpussse3
2710 || i.tm.cpu_flags.bitfield.cpusse4_1
2711 || i.tm.cpu_flags.bitfield.cpusse4_2))
2712 {
2713 (sse_check == sse_check_warning
2714 ? as_warn
2715 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2716 }
2717
321fd21e
L		 2718 /* Zap movzx and movsx suffix. The suffix has been set from
2719 "word ptr" or "byte ptr" on the source operand in Intel syntax
2720 or extracted from mnemonic in AT&T syntax. But we'll use
2721 the destination register to choose the suffix for encoding. */
2722 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2723 {
321fd21e
L		 2724 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2725 there is no suffix, the default will be byte extension. */
2726 if (i.reg_operands != 2
2727 && !i.suffix
2728 && intel_syntax)
2729 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2730
2731 i.suffix = 0;
cd61ebfe 2732 }
24eab124 2733
40fb9820 2734 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2735 if (!add_prefix (FWAIT_OPCODE))
2736 return;
252b5132 2737
29b0f896 2738 /* Check string instruction segment overrides. */
40fb9820 2739 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2740 {
2741 if (!check_string ())
5dd0794d 2742 return;
29b0f896 2743 }
5dd0794d 2744
29b0f896
AM		 2745 if (!process_suffix ())
2746 return;
e413e4e9 2747
29b0f896
AM		 2748 /* Make still unresolved immediate matches conform to size of immediate
2749 given in i.suffix. */
2750 if (!finalize_imm ())
2751 return;
252b5132 2752
40fb9820 2753 if (i.types[0].bitfield.imm1)
29b0f896 2754 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2755
40fb9820 2756 for (j = 0; j < 3; j++)
c6fb90c8
L		 2757 if (i.types[j].bitfield.inoutportreg
2758 || i.types[j].bitfield.shiftcount
2759 || i.types[j].bitfield.acc
2760 || i.types[j].bitfield.floatacc)
40fb9820
L		 2761 i.reg_operands--;
2762
c0f3af97
L		 2763 /* ImmExt should be processed after SSE2AVX. */
2764 if (!i.tm.opcode_modifier.sse2avx
2765 && i.tm.opcode_modifier.immext)
65da13b5 2766 process_immext ();
252b5132 2767
29b0f896
AM		 2768 /* For insns with operands there are more diddles to do to the opcode. */
2769 if (i.operands)
2770 {
2771 if (!process_operands ())
2772 return;
2773 }
40fb9820 2774 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2775 {
2776 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2777 as_warn (_("translating to `%sp'"), i.tm.name);
2778 }
252b5132 2779
c0f3af97
L		 2780 if (i.tm.opcode_modifier.vex)
2781 build_vex_prefix ();
2782
29b0f896
AM		 2783 /* Handle conversion of 'int $3' --> special int3 insn. */
2784 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2785 {
2786 i.tm.base_opcode = INT3_OPCODE;
2787 i.imm_operands = 0;
2788 }
252b5132 2789
40fb9820
L		 2790 if ((i.tm.opcode_modifier.jump
2791 || i.tm.opcode_modifier.jumpbyte
2792 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2793 && i.op[0].disps->X_op == O_constant)
2794 {
2795 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2796 the absolute address given by the constant. Since ix86 jumps and
2797 calls are pc relative, we need to generate a reloc. */
2798 i.op[0].disps->X_add_symbol = &abs_symbol;
2799 i.op[0].disps->X_op = O_symbol;
2800 }
252b5132 2801
40fb9820 2802 if (i.tm.opcode_modifier.rex64)
161a04f6 2803 i.rex |= REX_W;
252b5132 2804
29b0f896
AM		 2805 /* For 8 bit registers we need an empty rex prefix. Also if the
2806 instruction already has a prefix, we need to convert old
2807 registers to new ones. */
773f551c 2808
40fb9820 2809 if ((i.types[0].bitfield.reg8
29b0f896 2810 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2811 || (i.types[1].bitfield.reg8
29b0f896 2812 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2813 || ((i.types[0].bitfield.reg8
2814 || i.types[1].bitfield.reg8)
29b0f896
AM		 2815 && i.rex != 0))
2816 {
2817 int x;
726c5dcd 2818
29b0f896
AM		 2819 i.rex |= REX_OPCODE;
2820 for (x = 0; x < 2; x++)
2821 {
2822 /* Look for 8 bit operand that uses old registers. */
40fb9820 2823 if (i.types[x].bitfield.reg8
29b0f896 2824 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2825 {
29b0f896
AM		 2826 /* In case it is "hi" register, give up. */
2827 if (i.op[x].regs->reg_num > 3)
a540244d 2828 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2829 "instruction requiring REX prefix."),
a540244d 2830 register_prefix, i.op[x].regs->reg_name);
773f551c 2831
29b0f896
AM		 2832 /* Otherwise it is equivalent to the extended register.
2833 Since the encoding doesn't change this is merely
2834 cosmetic cleanup for debug output. */
2835
2836 i.op[x].regs = i.op[x].regs + 8;
773f551c 2837 }
29b0f896
AM		 2838 }
2839 }
773f551c 2840
85f10a01
MM		 2841 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2842 REX prefix. */
2843 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2844 {
2845 i.drex.rex = i.rex;
2846 i.rex = 0;
2847 }
2848 else if (i.rex != 0)
29b0f896
AM		 2849 add_prefix (REX_OPCODE | i.rex);
2850
2851 /* We are ready to output the insn. */
2852 output_insn ();
2853}
2854
2855static char *
e3bb37b5 2856parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2857{
2858 char *l = line;
2859 char *token_start = l;
2860 char *mnem_p;
5c6af06e
JB		 2861 int supported;
2862 const template *t;
29b0f896
AM		 2863
2864 /* Non-zero if we found a prefix only acceptable with string insns. */
2865 const char *expecting_string_instruction = NULL;
45288df1 2866
29b0f896
AM		 2867 while (1)
2868 {
2869 mnem_p = mnemonic;
2870 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2871 {
2872 mnem_p++;
2873 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2874 {
29b0f896
AM		 2875 as_bad (_("no such instruction: `%s'"), token_start);
2876 return NULL;
2877 }
2878 l++;
2879 }
2880 if (!is_space_char (*l)
2881 && *l != END_OF_INSN
e44823cf
JB		 2882 && (intel_syntax
2883 || (*l != PREFIX_SEPARATOR
2884 && *l != ',')))
29b0f896
AM		 2885 {
2886 as_bad (_("invalid character %s in mnemonic"),
2887 output_invalid (*l));
2888 return NULL;
2889 }
2890 if (token_start == l)
2891 {
e44823cf 2892 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2893 as_bad (_("expecting prefix; got nothing"));
2894 else
2895 as_bad (_("expecting mnemonic; got nothing"));
2896 return NULL;
2897 }
45288df1 2898
29b0f896
AM		 2899 /* Look up instruction (or prefix) via hash table. */
2900 current_templates = hash_find (op_hash, mnemonic);
47926f60 2901
29b0f896
AM		 2902 if (*l != END_OF_INSN
2903 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2904 && current_templates
40fb9820 2905 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2906 {
c6fb90c8 2907 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2908 {
2909 as_bad ((flag_code != CODE_64BIT
2910 ? _("`%s' is only supported in 64-bit mode")
2911 : _("`%s' is not supported in 64-bit mode")),
2912 current_templates->start->name);
2913 return NULL;
2914 }
29b0f896
AM		 2915 /* If we are in 16-bit mode, do not allow addr16 or data16.
2916 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2917 if ((current_templates->start->opcode_modifier.size16
2918 || current_templates->start->opcode_modifier.size32)
29b0f896 2919 && flag_code != CODE_64BIT
40fb9820 2920 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2921 ^ (flag_code == CODE_16BIT)))
2922 {
2923 as_bad (_("redundant %s prefix"),
2924 current_templates->start->name);
2925 return NULL;
45288df1 2926 }
29b0f896
AM		 2927 /* Add prefix, checking for repeated prefixes. */
2928 switch (add_prefix (current_templates->start->base_opcode))
2929 {
2930 case 0:
2931 return NULL;
2932 case 2:
2933 expecting_string_instruction = current_templates->start->name;
2934 break;
2935 }
2936 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2937 token_start = ++l;
2938 }
2939 else
2940 break;
2941 }
45288df1 2942
29b0f896
AM		 2943 if (!current_templates)
2944 {
2945 /* See if we can get a match by trimming off a suffix. */
2946 switch (mnem_p[-1])
2947 {
2948 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2949 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2950 i.suffix = SHORT_MNEM_SUFFIX;
2951 else
29b0f896
AM		 2952 case BYTE_MNEM_SUFFIX:
2953 case QWORD_MNEM_SUFFIX:
2954 i.suffix = mnem_p[-1];
2955 mnem_p[-1] = '\0';
2956 current_templates = hash_find (op_hash, mnemonic);
2957 break;
2958 case SHORT_MNEM_SUFFIX:
2959 case LONG_MNEM_SUFFIX:
2960 if (!intel_syntax)
2961 {
2962 i.suffix = mnem_p[-1];
2963 mnem_p[-1] = '\0';
2964 current_templates = hash_find (op_hash, mnemonic);
2965 }
2966 break;
252b5132 2967
29b0f896
AM		 2968 /* Intel Syntax. */
2969 case 'd':
2970 if (intel_syntax)
2971 {
9306ca4a 2972 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2973 i.suffix = SHORT_MNEM_SUFFIX;
2974 else
2975 i.suffix = LONG_MNEM_SUFFIX;
2976 mnem_p[-1] = '\0';
2977 current_templates = hash_find (op_hash, mnemonic);
2978 }
2979 break;
2980 }
2981 if (!current_templates)
2982 {
2983 as_bad (_("no such instruction: `%s'"), token_start);
2984 return NULL;
2985 }
2986 }
252b5132 2987
40fb9820
L		 2988 if (current_templates->start->opcode_modifier.jump
2989 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 2990 {
2991 /* Check for a branch hint. We allow ",pt" and ",pn" for
2992 predict taken and predict not taken respectively.
2993 I'm not sure that branch hints actually do anything on loop
2994 and jcxz insns (JumpByte) for current Pentium4 chips. They
2995 may work in the future and it doesn't hurt to accept them
2996 now. */
2997 if (l[0] == ',' && l[1] == 'p')
2998 {
2999 if (l[2] == 't')
3000 {
3001 if (!add_prefix (DS_PREFIX_OPCODE))
3002 return NULL;
3003 l += 3;
3004 }
3005 else if (l[2] == 'n')
3006 {
3007 if (!add_prefix (CS_PREFIX_OPCODE))
3008 return NULL;
3009 l += 3;
3010 }
3011 }
3012 }
3013 /* Any other comma loses. */
3014 if (*l == ',')
3015 {
3016 as_bad (_("invalid character %s in mnemonic"),
3017 output_invalid (*l));
3018 return NULL;
3019 }
252b5132 3020
29b0f896 3021 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3022 supported = 0;
3023 for (t = current_templates->start; t < current_templates->end; ++t)
3024 {
c0f3af97
L		 3025 supported |= cpu_flags_match (t);
3026 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3027 goto skip;
5c6af06e 3028 }
3629bb00 3029
c0f3af97 3030 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3031 {
3032 as_bad (flag_code == CODE_64BIT
3033 ? _("`%s' is not supported in 64-bit mode")
3034 : _("`%s' is only supported in 64-bit mode"),
3035 current_templates->start->name);
3036 return NULL;
3037 }
c0f3af97 3038 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3039 {
3629bb00
L		 3040 as_bad (_("`%s' is not supported on `%s%s'"),
3041 current_templates->start->name, cpu_arch_name,
3042 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3043 return NULL;
29b0f896 3044 }
3629bb00
L		 3045
3046skip:
3047 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3048 && (flag_code != CODE_16BIT))
29b0f896
AM		 3049 {
3050 as_warn (_("use .code16 to ensure correct addressing mode"));
3051 }
252b5132 3052
29b0f896 3053 /* Check for rep/repne without a string instruction. */
f41bbced 3054 if (expecting_string_instruction)
29b0f896 3055 {
f41bbced
JB		 3056 static templates override;
3057
3058 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3059 if (t->opcode_modifier.isstring)
f41bbced
JB		 3060 break;
3061 if (t >= current_templates->end)
3062 {
3063 as_bad (_("expecting string instruction after `%s'"),
64e74474 3064 expecting_string_instruction);
f41bbced
JB		 3065 return NULL;
3066 }
3067 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3068 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3069 break;
3070 override.end = t;
3071 current_templates = &override;
29b0f896 3072 }
252b5132 3073
29b0f896
AM		 3074 return l;
3075}
252b5132 3076
29b0f896 3077static char *
e3bb37b5 3078parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3079{
3080 char *token_start;
3138f287 3081
29b0f896
AM		 3082 /* 1 if operand is pending after ','. */
3083 unsigned int expecting_operand = 0;
252b5132 3084
29b0f896
AM		 3085 /* Non-zero if operand parens not balanced. */
3086 unsigned int paren_not_balanced;
3087
3088 while (*l != END_OF_INSN)
3089 {
3090 /* Skip optional white space before operand. */
3091 if (is_space_char (*l))
3092 ++l;
3093 if (!is_operand_char (*l) && *l != END_OF_INSN)
3094 {
3095 as_bad (_("invalid character %s before operand %d"),
3096 output_invalid (*l),
3097 i.operands + 1);
3098 return NULL;
3099 }
3100 token_start = l; /* after white space */
3101 paren_not_balanced = 0;
3102 while (paren_not_balanced || *l != ',')
3103 {
3104 if (*l == END_OF_INSN)
3105 {
3106 if (paren_not_balanced)
3107 {
3108 if (!intel_syntax)
3109 as_bad (_("unbalanced parenthesis in operand %d."),
3110 i.operands + 1);
3111 else
3112 as_bad (_("unbalanced brackets in operand %d."),
3113 i.operands + 1);
3114 return NULL;
3115 }
3116 else
3117 break; /* we are done */
3118 }
3119 else if (!is_operand_char (*l) && !is_space_char (*l))
3120 {
3121 as_bad (_("invalid character %s in operand %d"),
3122 output_invalid (*l),
3123 i.operands + 1);
3124 return NULL;
3125 }
3126 if (!intel_syntax)
3127 {
3128 if (*l == '(')
3129 ++paren_not_balanced;
3130 if (*l == ')')
3131 --paren_not_balanced;
3132 }
3133 else
3134 {
3135 if (*l == '[')
3136 ++paren_not_balanced;
3137 if (*l == ']')
3138 --paren_not_balanced;
3139 }
3140 l++;
3141 }
3142 if (l != token_start)
3143 { /* Yes, we've read in another operand. */
3144 unsigned int operand_ok;
3145 this_operand = i.operands++;
7d5e4556 3146 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3147 if (i.operands > MAX_OPERANDS)
3148 {
3149 as_bad (_("spurious operands; (%d operands/instruction max)"),
3150 MAX_OPERANDS);
3151 return NULL;
3152 }
3153 /* Now parse operand adding info to 'i' as we go along. */
3154 END_STRING_AND_SAVE (l);
3155
3156 if (intel_syntax)
3157 operand_ok =
3158 i386_intel_operand (token_start,
3159 intel_float_operand (mnemonic));
3160 else
a7619375 3161 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3162
3163 RESTORE_END_STRING (l);
3164 if (!operand_ok)
3165 return NULL;
3166 }
3167 else
3168 {
3169 if (expecting_operand)
3170 {
3171 expecting_operand_after_comma:
3172 as_bad (_("expecting operand after ','; got nothing"));
3173 return NULL;
3174 }
3175 if (*l == ',')
3176 {
3177 as_bad (_("expecting operand before ','; got nothing"));
3178 return NULL;
3179 }
3180 }
7f3f1ea2 3181
29b0f896
AM		 3182 /* Now *l must be either ',' or END_OF_INSN. */
3183 if (*l == ',')
3184 {
3185 if (*++l == END_OF_INSN)
3186 {
3187 /* Just skip it, if it's \n complain. */
3188 goto expecting_operand_after_comma;
3189 }
3190 expecting_operand = 1;
3191 }
3192 }
3193 return l;
3194}
7f3f1ea2 3195
050dfa73 3196static void
4d456e3d 3197swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3198{
3199 union i386_op temp_op;
40fb9820 3200 i386_operand_type temp_type;
050dfa73 3201 enum bfd_reloc_code_real temp_reloc;
4eed87de 3202
050dfa73
MM		 3203 temp_type = i.types[xchg2];
3204 i.types[xchg2] = i.types[xchg1];
3205 i.types[xchg1] = temp_type;
3206 temp_op = i.op[xchg2];
3207 i.op[xchg2] = i.op[xchg1];
3208 i.op[xchg1] = temp_op;
3209 temp_reloc = i.reloc[xchg2];
3210 i.reloc[xchg2] = i.reloc[xchg1];
3211 i.reloc[xchg1] = temp_reloc;
3212}
3213
29b0f896 3214static void
e3bb37b5 3215swap_operands (void)
29b0f896 3216{
b7c61d9a 3217 switch (i.operands)
050dfa73 3218 {
c0f3af97 3219 case 5:
b7c61d9a 3220 case 4:
4d456e3d 3221 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3222 case 3:
3223 case 2:
4d456e3d 3224 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3225 break;
3226 default:
3227 abort ();
29b0f896 3228 }
29b0f896
AM		 3229
3230 if (i.mem_operands == 2)
3231 {
3232 const seg_entry *temp_seg;
3233 temp_seg = i.seg[0];
3234 i.seg[0] = i.seg[1];
3235 i.seg[1] = temp_seg;
3236 }
3237}
252b5132 3238
29b0f896
AM		 3239/* Try to ensure constant immediates are represented in the smallest
3240 opcode possible. */
3241static void
e3bb37b5 3242optimize_imm (void)
29b0f896
AM		 3243{
3244 char guess_suffix = 0;
3245 int op;
252b5132 3246
29b0f896
AM		 3247 if (i.suffix)
3248 guess_suffix = i.suffix;
3249 else if (i.reg_operands)
3250 {
3251 /* Figure out a suffix from the last register operand specified.
3252 We can't do this properly yet, ie. excluding InOutPortReg,
3253 but the following works for instructions with immediates.
3254 In any case, we can't set i.suffix yet. */
3255 for (op = i.operands; --op >= 0;)
40fb9820
L		 3256 if (i.types[op].bitfield.reg8)
3257 {
3258 guess_suffix = BYTE_MNEM_SUFFIX;
3259 break;
3260 }
3261 else if (i.types[op].bitfield.reg16)
252b5132 3262 {
40fb9820
L		 3263 guess_suffix = WORD_MNEM_SUFFIX;
3264 break;
3265 }
3266 else if (i.types[op].bitfield.reg32)
3267 {
3268 guess_suffix = LONG_MNEM_SUFFIX;
3269 break;
3270 }
3271 else if (i.types[op].bitfield.reg64)
3272 {
3273 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3274 break;
252b5132 3275 }
29b0f896
AM		 3276 }
3277 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3278 guess_suffix = WORD_MNEM_SUFFIX;
3279
3280 for (op = i.operands; --op >= 0;)
40fb9820 3281 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3282 {
3283 switch (i.op[op].imms->X_op)
252b5132 3284 {
29b0f896
AM		 3285 case O_constant:
3286 /* If a suffix is given, this operand may be shortened. */
3287 switch (guess_suffix)
252b5132 3288 {
29b0f896 3289 case LONG_MNEM_SUFFIX:
40fb9820
L		 3290 i.types[op].bitfield.imm32 = 1;
3291 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3292 break;
3293 case WORD_MNEM_SUFFIX:
40fb9820
L		 3294 i.types[op].bitfield.imm16 = 1;
3295 i.types[op].bitfield.imm32 = 1;
3296 i.types[op].bitfield.imm32s = 1;
3297 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3298 break;
3299 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3300 i.types[op].bitfield.imm8 = 1;
3301 i.types[op].bitfield.imm8s = 1;
3302 i.types[op].bitfield.imm16 = 1;
3303 i.types[op].bitfield.imm32 = 1;
3304 i.types[op].bitfield.imm32s = 1;
3305 i.types[op].bitfield.imm64 = 1;
29b0f896 3306 break;
252b5132 3307 }
252b5132 3308
29b0f896
AM		 3309 /* If this operand is at most 16 bits, convert it
3310 to a signed 16 bit number before trying to see
3311 whether it will fit in an even smaller size.
3312 This allows a 16-bit operand such as $0xffe0 to
3313 be recognised as within Imm8S range. */
40fb9820 3314 if ((i.types[op].bitfield.imm16)
29b0f896 3315 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3316 {
29b0f896
AM		 3317 i.op[op].imms->X_add_number =
3318 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3319 }
40fb9820 3320 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3321 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3322 == 0))
3323 {
3324 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3325 ^ ((offsetT) 1 << 31))
3326 - ((offsetT) 1 << 31));
3327 }
40fb9820 3328 i.types[op]
c6fb90c8
L		 3329 = operand_type_or (i.types[op],
3330 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3331
29b0f896
AM		 3332 /* We must avoid matching of Imm32 templates when 64bit
3333 only immediate is available. */
3334 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3335 i.types[op].bitfield.imm32 = 0;
29b0f896 3336 break;
252b5132 3337
29b0f896
AM		 3338 case O_absent:
3339 case O_register:
3340 abort ();
3341
3342 /* Symbols and expressions. */
3343 default:
9cd96992
JB		 3344 /* Convert symbolic operand to proper sizes for matching, but don't
3345 prevent matching a set of insns that only supports sizes other
3346 than those matching the insn suffix. */
3347 {
40fb9820 3348 i386_operand_type mask, allowed;
9cd96992
JB		 3349 const template *t;
3350
0dfbf9d7
L		 3351 operand_type_set (&mask, 0);
3352 operand_type_set (&allowed, 0);
40fb9820 3353
4eed87de
AM		 3354 for (t = current_templates->start;
3355 t < current_templates->end;
3356 ++t)
c6fb90c8
L		 3357 allowed = operand_type_or (allowed,
3358 t->operand_types[op]);
9cd96992
JB		 3359 switch (guess_suffix)
3360 {
3361 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3362 mask.bitfield.imm64 = 1;
3363 mask.bitfield.imm32s = 1;
9cd96992
JB		 3364 break;
3365 case LONG_MNEM_SUFFIX:
40fb9820 3366 mask.bitfield.imm32 = 1;
9cd96992
JB		 3367 break;
3368 case WORD_MNEM_SUFFIX:
40fb9820 3369 mask.bitfield.imm16 = 1;
9cd96992
JB		 3370 break;
3371 case BYTE_MNEM_SUFFIX:
40fb9820 3372 mask.bitfield.imm8 = 1;
9cd96992
JB		 3373 break;
3374 default:
9cd96992
JB		 3375 break;
3376 }
c6fb90c8 3377 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3378 if (!operand_type_all_zero (&allowed))
c6fb90c8 3379 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3380 }
29b0f896 3381 break;
252b5132 3382 }
29b0f896
AM		 3383 }
3384}
47926f60 3385
29b0f896
AM		 3386/* Try to use the smallest displacement type too. */
3387static void
e3bb37b5 3388optimize_disp (void)
29b0f896
AM		 3389{
3390 int op;
3e73aa7c 3391
29b0f896 3392 for (op = i.operands; --op >= 0;)
40fb9820 3393 if (operand_type_check (i.types[op], disp))
252b5132 3394 {
b300c311 3395 if (i.op[op].disps->X_op == O_constant)
252b5132 3396 {
b300c311 3397 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3398
40fb9820 3399 if (i.types[op].bitfield.disp16
b300c311
L		 3400 && (disp & ~(offsetT) 0xffff) == 0)
3401 {
3402 /* If this operand is at most 16 bits, convert
3403 to a signed 16 bit number and don't use 64bit
3404 displacement. */
3405 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3406 i.types[op].bitfield.disp64 = 0;
b300c311 3407 }
40fb9820 3408 if (i.types[op].bitfield.disp32
b300c311
L		 3409 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3410 {
3411 /* If this operand is at most 32 bits, convert
3412 to a signed 32 bit number and don't use 64bit
3413 displacement. */
3414 disp &= (((offsetT) 2 << 31) - 1);
3415 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3416 i.types[op].bitfield.disp64 = 0;
b300c311 3417 }
40fb9820 3418 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3419 {
40fb9820
L		 3420 i.types[op].bitfield.disp8 = 0;
3421 i.types[op].bitfield.disp16 = 0;
3422 i.types[op].bitfield.disp32 = 0;
3423 i.types[op].bitfield.disp32s = 0;
3424 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3425 i.op[op].disps = 0;
3426 i.disp_operands--;
3427 }
3428 else if (flag_code == CODE_64BIT)
3429 {
3430 if (fits_in_signed_long (disp))
28a9d8f5 3431 {
40fb9820
L		 3432 i.types[op].bitfield.disp64 = 0;
3433 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3434 }
b300c311 3435 if (fits_in_unsigned_long (disp))
40fb9820 3436 i.types[op].bitfield.disp32 = 1;
b300c311 3437 }
40fb9820
L		 3438 if ((i.types[op].bitfield.disp32
3439 || i.types[op].bitfield.disp32s
3440 || i.types[op].bitfield.disp16)
b300c311 3441 && fits_in_signed_byte (disp))
40fb9820 3442 i.types[op].bitfield.disp8 = 1;
252b5132 3443 }
67a4f2b7
AO		 3444 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3445 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3446 {
3447 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3448 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3449 i.types[op].bitfield.disp8 = 0;
3450 i.types[op].bitfield.disp16 = 0;
3451 i.types[op].bitfield.disp32 = 0;
3452 i.types[op].bitfield.disp32s = 0;
3453 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3454 }
3455 else
b300c311 3456 /* We only support 64bit displacement on constants. */
40fb9820 3457 i.types[op].bitfield.disp64 = 0;
252b5132 3458 }
29b0f896
AM		 3459}
3460
c0f3af97
L		 3461/* Check if operands are valid for the instrucrtion. Update VEX
3462 operand types. */
3463
3464static int
3465VEX_check_operands (const template *t)
3466{
3467 if (!t->opcode_modifier.vex)
3468 return 0;
3469
3470 /* Only check VEX_Imm4, which must be the first operand. */
3471 if (t->operand_types[0].bitfield.vex_imm4)
3472 {
3473 if (i.op[0].imms->X_op != O_constant
3474 || !fits_in_imm4 (i.op[0].imms->X_add_number))
3475 return 1;
3476
3477 /* Turn off Imm8 so that update_imm won't complain. */
3478 i.types[0] = vex_imm4;
3479 }
3480
3481 return 0;
3482}
3483
29b0f896 3484static int
e3bb37b5 3485match_template (void)
29b0f896
AM		 3486{
3487 /* Points to template once we've found it. */
3488 const template *t;
40fb9820 3489 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3490 i386_operand_type overlap4;
29b0f896 3491 unsigned int found_reverse_match;
40fb9820
L		 3492 i386_opcode_modifier suffix_check;
3493 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3494 int addr_prefix_disp;
a5c311ca 3495 unsigned int j;
3629bb00 3496 unsigned int found_cpu_match;
45664ddb 3497 unsigned int check_register;
29b0f896 3498
c0f3af97
L		 3499#if MAX_OPERANDS != 5
3500# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3501#endif
3502
29b0f896 3503 found_reverse_match = 0;
539e75ad 3504 addr_prefix_disp = -1;
40fb9820
L		 3505
3506 memset (&suffix_check, 0, sizeof (suffix_check));
3507 if (i.suffix == BYTE_MNEM_SUFFIX)
3508 suffix_check.no_bsuf = 1;
3509 else if (i.suffix == WORD_MNEM_SUFFIX)
3510 suffix_check.no_wsuf = 1;
3511 else if (i.suffix == SHORT_MNEM_SUFFIX)
3512 suffix_check.no_ssuf = 1;
3513 else if (i.suffix == LONG_MNEM_SUFFIX)
3514 suffix_check.no_lsuf = 1;
3515 else if (i.suffix == QWORD_MNEM_SUFFIX)
3516 suffix_check.no_qsuf = 1;
3517 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3518 suffix_check.no_ldsuf = 1;
29b0f896 3519
45aa61fe 3520 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3521 {
539e75ad
L		 3522 addr_prefix_disp = -1;
3523
29b0f896
AM		 3524 /* Must have right number of operands. */
3525 if (i.operands != t->operands)
3526 continue;
3527
50aecf8c 3528 /* Check processor support. */
c0f3af97
L		 3529 found_cpu_match = (cpu_flags_match (t)
3530 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3531 if (!found_cpu_match)
3532 continue;
3533
e1d4d893
L		 3534 /* Check old gcc support. */
3535 if (!old_gcc && t->opcode_modifier.oldgcc)
3536 continue;
3537
3538 /* Check AT&T mnemonic. */
3539 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3540 continue;
3541
5c07affc
L		 3542 /* Check AT&T syntax Intel syntax. */
3543 if ((intel_syntax && t->opcode_modifier.attsyntax)
3544 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3545 continue;
3546
20592a94 3547 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3548 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3549 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3550 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3551 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3552 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3553 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3554 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3555 continue;
3556
5c07affc 3557 if (!operand_size_match (t))
7d5e4556 3558 continue;
539e75ad 3559
5c07affc
L		 3560 for (j = 0; j < MAX_OPERANDS; j++)
3561 operand_types[j] = t->operand_types[j];
3562
45aa61fe
AM		 3563 /* In general, don't allow 64-bit operands in 32-bit mode. */
3564 if (i.suffix == QWORD_MNEM_SUFFIX
3565 && flag_code != CODE_64BIT
3566 && (intel_syntax
40fb9820 3567 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3568 && !intel_float_operand (t->name))
3569 : intel_float_operand (t->name) != 2)
40fb9820 3570 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3571 && !operand_types[0].bitfield.regxmm
3572 && !operand_types[0].bitfield.regymm)
40fb9820 3573 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3574 && !!operand_types[t->operands > 1].bitfield.regxmm
3575 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3576 && (t->base_opcode != 0x0fc7
3577 || t->extension_opcode != 1 /* cmpxchg8b */))
3578 continue;
3579
192dc9c6
JB		 3580 /* In general, don't allow 32-bit operands on pre-386. */
3581 else if (i.suffix == LONG_MNEM_SUFFIX
3582 && !cpu_arch_flags.bitfield.cpui386
3583 && (intel_syntax
3584 ? (!t->opcode_modifier.ignoresize
3585 && !intel_float_operand (t->name))
3586 : intel_float_operand (t->name) != 2)
3587 && ((!operand_types[0].bitfield.regmmx
3588 && !operand_types[0].bitfield.regxmm)
3589 || (!operand_types[t->operands > 1].bitfield.regmmx
3590 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3591 continue;
3592
29b0f896 3593 /* Do not verify operands when there are none. */
50aecf8c 3594 else
29b0f896 3595 {
c6fb90c8 3596 if (!t->operands)
2dbab7d5
L		 3597 /* We've found a match; break out of loop. */
3598 break;
29b0f896 3599 }
252b5132 3600
539e75ad
L		 3601 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3602 into Disp32/Disp16/Disp32 operand. */
3603 if (i.prefix[ADDR_PREFIX] != 0)
3604 {
40fb9820 3605 /* There should be only one Disp operand. */
539e75ad
L		 3606 switch (flag_code)
3607 {
3608 case CODE_16BIT:
40fb9820
L		 3609 for (j = 0; j < MAX_OPERANDS; j++)
3610 {
3611 if (operand_types[j].bitfield.disp16)
3612 {
3613 addr_prefix_disp = j;
3614 operand_types[j].bitfield.disp32 = 1;
3615 operand_types[j].bitfield.disp16 = 0;
3616 break;
3617 }
3618 }
539e75ad
L		 3619 break;
3620 case CODE_32BIT:
40fb9820
L		 3621 for (j = 0; j < MAX_OPERANDS; j++)
3622 {
3623 if (operand_types[j].bitfield.disp32)
3624 {
3625 addr_prefix_disp = j;
3626 operand_types[j].bitfield.disp32 = 0;
3627 operand_types[j].bitfield.disp16 = 1;
3628 break;
3629 }
3630 }
539e75ad
L		 3631 break;
3632 case CODE_64BIT:
40fb9820
L		 3633 for (j = 0; j < MAX_OPERANDS; j++)
3634 {
3635 if (operand_types[j].bitfield.disp64)
3636 {
3637 addr_prefix_disp = j;
3638 operand_types[j].bitfield.disp64 = 0;
3639 operand_types[j].bitfield.disp32 = 1;
3640 break;
3641 }
3642 }
539e75ad
L		 3643 break;
3644 }
539e75ad
L		 3645 }
3646
45664ddb
L		 3647 /* We check register size only if size of operands can be
3648 encoded the canonical way. */
3649 check_register = t->opcode_modifier.w;
c6fb90c8 3650 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3651 switch (t->operands)
3652 {
3653 case 1:
40fb9820 3654 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3655 continue;
3656 break;
3657 case 2:
8b38ad71
L		 3658 /* xchg %eax, %eax is a special case. It is an aliase for nop
3659 only in 32bit mode and we can use opcode 0x90. In 64bit
3660 mode, we can't use 0x90 for xchg %eax, %eax since it should
3661 zero-extend %eax to %rax. */
3662 if (flag_code == CODE_64BIT
3663 && t->base_opcode == 0x90
0dfbf9d7
L		 3664 && operand_type_equal (&i.types [0], &acc32)
3665 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3666 continue;
29b0f896 3667 case 3:
f48ff2ae 3668 case 4:
c0f3af97 3669 case 5:
c6fb90c8 3670 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3671 if (!operand_type_match (overlap0, i.types[0])
3672 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3673 || (check_register
3674 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3675 operand_types[0],
3676 overlap1, i.types[1],
3677 operand_types[1])))
29b0f896
AM		 3678 {
3679 /* Check if other direction is valid ... */
40fb9820 3680 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3681 continue;
3682
3683 /* Try reversing direction of operands. */
c6fb90c8
L		 3684 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3685 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3686 if (!operand_type_match (overlap0, i.types[0])
3687 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3688 || (check_register
3689 && !operand_type_register_match (overlap0,
3690 i.types[0],
3691 operand_types[1],
3692 overlap1,
3693 i.types[1],
3694 operand_types[0])))
29b0f896
AM		 3695 {
3696 /* Does not match either direction. */
3697 continue;
3698 }
3699 /* found_reverse_match holds which of D or FloatDR
3700 we've found. */
40fb9820 3701 if (t->opcode_modifier.d)
8a2ed489 3702 found_reverse_match = Opcode_D;
40fb9820 3703 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3704 found_reverse_match = Opcode_FloatD;
3705 else
3706 found_reverse_match = 0;
40fb9820 3707 if (t->opcode_modifier.floatr)
8a2ed489 3708 found_reverse_match |= Opcode_FloatR;
29b0f896 3709 }
f48ff2ae 3710 else
29b0f896 3711 {
f48ff2ae 3712 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3713 switch (t->operands)
3714 {
c0f3af97
L		 3715 case 5:
3716 overlap4 = operand_type_and (i.types[4],
3717 operand_types[4]);
d1cbb4db 3718 case 4:
c6fb90c8
L		 3719 overlap3 = operand_type_and (i.types[3],
3720 operand_types[3]);
d1cbb4db 3721 case 3:
c6fb90c8
L		 3722 overlap2 = operand_type_and (i.types[2],
3723 operand_types[2]);
d1cbb4db
L		 3724 break;
3725 }
29b0f896 3726
f48ff2ae
L		 3727 switch (t->operands)
3728 {
c0f3af97
L		 3729 case 5:
3730 if (!operand_type_match (overlap4, i.types[4])
3731 || !operand_type_register_match (overlap3,
3732 i.types[3],
3733 operand_types[3],
3734 overlap4,
3735 i.types[4],
3736 operand_types[4]))
3737 continue;
f48ff2ae 3738 case 4:
40fb9820 3739 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3740 || (check_register
3741 && !operand_type_register_match (overlap2,
3742 i.types[2],
3743 operand_types[2],
3744 overlap3,
3745 i.types[3],
3746 operand_types[3])))
f48ff2ae
L		 3747 continue;
3748 case 3:
3749 /* Here we make use of the fact that there are no
3750 reverse match 3 operand instructions, and all 3
3751 operand instructions only need to be checked for
3752 register consistency between operands 2 and 3. */
40fb9820 3753 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3754 || (check_register
3755 && !operand_type_register_match (overlap1,
3756 i.types[1],
3757 operand_types[1],
3758 overlap2,
3759 i.types[2],
3760 operand_types[2])))
f48ff2ae
L		 3761 continue;
3762 break;
3763 }
29b0f896 3764 }
f48ff2ae 3765 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3766 slip through to break. */
3767 }
3629bb00 3768 if (!found_cpu_match)
29b0f896
AM		 3769 {
3770 found_reverse_match = 0;
3771 continue;
3772 }
c0f3af97
L		 3773
3774 /* Check if VEX operands are valid. */
3775 if (VEX_check_operands (t))
3776 continue;
3777
29b0f896
AM		 3778 /* We've found a match; break out of loop. */
3779 break;
3780 }
3781
3782 if (t == current_templates->end)
3783 {
3784 /* We found no match. */
95f283e8
L		 3785 if (intel_syntax)
3786 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3787 current_templates->start->name);
3788 else
3789 as_bad (_("suffix or operands invalid for `%s'"),
3790 current_templates->start->name);
29b0f896
AM		 3791 return 0;
3792 }
252b5132 3793
29b0f896
AM		 3794 if (!quiet_warnings)
3795 {
3796 if (!intel_syntax
40fb9820
L		 3797 && (i.types[0].bitfield.jumpabsolute
3798 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3799 {
3800 as_warn (_("indirect %s without `*'"), t->name);
3801 }
3802
40fb9820
L		 3803 if (t->opcode_modifier.isprefix
3804 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3805 {
3806 /* Warn them that a data or address size prefix doesn't
3807 affect assembly of the next line of code. */
3808 as_warn (_("stand-alone `%s' prefix"), t->name);
3809 }
3810 }
3811
3812 /* Copy the template we found. */
3813 i.tm = *t;
539e75ad
L		 3814
3815 if (addr_prefix_disp != -1)
3816 i.tm.operand_types[addr_prefix_disp]
3817 = operand_types[addr_prefix_disp];
3818
29b0f896
AM		 3819 if (found_reverse_match)
3820 {
3821 /* If we found a reverse match we must alter the opcode
3822 direction bit. found_reverse_match holds bits to change
3823 (different for int & float insns). */
3824
3825 i.tm.base_opcode ^= found_reverse_match;
3826
539e75ad
L		 3827 i.tm.operand_types[0] = operand_types[1];
3828 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3829 }
3830
3831 return 1;
3832}
3833
3834static int
e3bb37b5 3835check_string (void)
29b0f896 3836{
40fb9820
L		 3837 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3838 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3839 {
3840 if (i.seg[0] != NULL && i.seg[0] != &es)
3841 {
3842 as_bad (_("`%s' operand %d must use `%%es' segment"),
3843 i.tm.name,
3844 mem_op + 1);
3845 return 0;
3846 }
3847 /* There's only ever one segment override allowed per instruction.
3848 This instruction possibly has a legal segment override on the
3849 second operand, so copy the segment to where non-string
3850 instructions store it, allowing common code. */
3851 i.seg[0] = i.seg[1];
3852 }
40fb9820 3853 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3854 {
3855 if (i.seg[1] != NULL && i.seg[1] != &es)
3856 {
3857 as_bad (_("`%s' operand %d must use `%%es' segment"),
3858 i.tm.name,
3859 mem_op + 2);
3860 return 0;
3861 }
3862 }
3863 return 1;
3864}
3865
3866static int
543613e9 3867process_suffix (void)
29b0f896
AM		 3868{
3869 /* If matched instruction specifies an explicit instruction mnemonic
3870 suffix, use it. */
40fb9820
L		 3871 if (i.tm.opcode_modifier.size16)
3872 i.suffix = WORD_MNEM_SUFFIX;
3873 else if (i.tm.opcode_modifier.size32)
3874 i.suffix = LONG_MNEM_SUFFIX;
3875 else if (i.tm.opcode_modifier.size64)
3876 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3877 else if (i.reg_operands)
3878 {
3879 /* If there's no instruction mnemonic suffix we try to invent one
3880 based on register operands. */
3881 if (!i.suffix)
3882 {
3883 /* We take i.suffix from the last register operand specified,
3884 Destination register type is more significant than source
381d071f
L		 3885 register type. crc32 in SSE4.2 prefers source register
3886 type. */
3887 if (i.tm.base_opcode == 0xf20f38f1)
3888 {
40fb9820
L		 3889 if (i.types[0].bitfield.reg16)
3890 i.suffix = WORD_MNEM_SUFFIX;
3891 else if (i.types[0].bitfield.reg32)
3892 i.suffix = LONG_MNEM_SUFFIX;
3893 else if (i.types[0].bitfield.reg64)
3894 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3895 }
9344ff29 3896 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3897 {
40fb9820 3898 if (i.types[0].bitfield.reg8)
20592a94
L		 3899 i.suffix = BYTE_MNEM_SUFFIX;
3900 }
381d071f
L		 3901
3902 if (!i.suffix)
3903 {
3904 int op;
3905
20592a94
L		 3906 if (i.tm.base_opcode == 0xf20f38f1
3907 || i.tm.base_opcode == 0xf20f38f0)
3908 {
3909 /* We have to know the operand size for crc32. */
3910 as_bad (_("ambiguous memory operand size for `%s`"),
3911 i.tm.name);
3912 return 0;
3913 }
3914
381d071f 3915 for (op = i.operands; --op >= 0;)
40fb9820 3916 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3917 {
40fb9820
L		 3918 if (i.types[op].bitfield.reg8)
3919 {
3920 i.suffix = BYTE_MNEM_SUFFIX;
3921 break;
3922 }
3923 else if (i.types[op].bitfield.reg16)
3924 {
3925 i.suffix = WORD_MNEM_SUFFIX;
3926 break;
3927 }
3928 else if (i.types[op].bitfield.reg32)
3929 {
3930 i.suffix = LONG_MNEM_SUFFIX;
3931 break;
3932 }
3933 else if (i.types[op].bitfield.reg64)
3934 {
3935 i.suffix = QWORD_MNEM_SUFFIX;
3936 break;
3937 }
381d071f
L		 3938 }
3939 }
29b0f896
AM		 3940 }
3941 else if (i.suffix == BYTE_MNEM_SUFFIX)
3942 {
3943 if (!check_byte_reg ())
3944 return 0;
3945 }
3946 else if (i.suffix == LONG_MNEM_SUFFIX)
3947 {
3948 if (!check_long_reg ())
3949 return 0;
3950 }
3951 else if (i.suffix == QWORD_MNEM_SUFFIX)
3952 {
955e1e6a
L		 3953 if (intel_syntax
3954 && i.tm.opcode_modifier.ignoresize
3955 && i.tm.opcode_modifier.no_qsuf)
3956 i.suffix = 0;
3957 else if (!check_qword_reg ())
29b0f896
AM		 3958 return 0;
3959 }
3960 else if (i.suffix == WORD_MNEM_SUFFIX)
3961 {
3962 if (!check_word_reg ())
3963 return 0;
3964 }
c0f3af97
L		 3965 else if (i.suffix == XMMWORD_MNEM_SUFFIX
3966 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 3967 {
c0f3af97 3968 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 3969 should check if it is a valid suffix. */
3970 }
40fb9820 3971 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 3972 /* Do nothing if the instruction is going to ignore the prefix. */
3973 ;
3974 else
3975 abort ();
3976 }
40fb9820 3977 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 3978 && !i.suffix
3979 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 3980 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 3981 {
3982 i.suffix = stackop_size;
3983 }
9306ca4a
JB		 3984 else if (intel_syntax
3985 && !i.suffix
40fb9820
L		 3986 && (i.tm.operand_types[0].bitfield.jumpabsolute
3987 || i.tm.opcode_modifier.jumpbyte
3988 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 3989 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3990 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 3991 {
3992 switch (flag_code)
3993 {
3994 case CODE_64BIT:
40fb9820 3995 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 3996 {
3997 i.suffix = QWORD_MNEM_SUFFIX;
3998 break;
3999 }
4000 case CODE_32BIT:
40fb9820 4001 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4002 i.suffix = LONG_MNEM_SUFFIX;
4003 break;
4004 case CODE_16BIT:
40fb9820 4005 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4006 i.suffix = WORD_MNEM_SUFFIX;
4007 break;
4008 }
4009 }
252b5132 4010
9306ca4a 4011 if (!i.suffix)
29b0f896 4012 {
9306ca4a
JB		 4013 if (!intel_syntax)
4014 {
40fb9820 4015 if (i.tm.opcode_modifier.w)
9306ca4a 4016 {
4eed87de
AM		 4017 as_bad (_("no instruction mnemonic suffix given and "
4018 "no register operands; can't size instruction"));
9306ca4a
JB		 4019 return 0;
4020 }
4021 }
4022 else
4023 {
40fb9820
L		 4024 unsigned int suffixes;
4025
4026 suffixes = !i.tm.opcode_modifier.no_bsuf;
4027 if (!i.tm.opcode_modifier.no_wsuf)
4028 suffixes |= 1 << 1;
4029 if (!i.tm.opcode_modifier.no_lsuf)
4030 suffixes |= 1 << 2;
fc4adea1 4031 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4032 suffixes |= 1 << 3;
4033 if (!i.tm.opcode_modifier.no_ssuf)
4034 suffixes |= 1 << 4;
4035 if (!i.tm.opcode_modifier.no_qsuf)
4036 suffixes |= 1 << 5;
4037
4038 /* There are more than suffix matches. */
4039 if (i.tm.opcode_modifier.w
9306ca4a 4040 || ((suffixes & (suffixes - 1))
40fb9820
L		 4041 && !i.tm.opcode_modifier.defaultsize
4042 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4043 {
4044 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4045 return 0;
4046 }
4047 }
29b0f896 4048 }
252b5132 4049
9306ca4a
JB		 4050 /* Change the opcode based on the operand size given by i.suffix;
4051 We don't need to change things for byte insns. */
4052
582d5edd
L		 4053 if (i.suffix
4054 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4055 && i.suffix != XMMWORD_MNEM_SUFFIX
4056 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4057 {
4058 /* It's not a byte, select word/dword operation. */
40fb9820 4059 if (i.tm.opcode_modifier.w)
29b0f896 4060 {
40fb9820 4061 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4062 i.tm.base_opcode |= 8;
4063 else
4064 i.tm.base_opcode |= 1;
4065 }
0f3f3d8b 4066
29b0f896
AM		 4067 /* Now select between word & dword operations via the operand
4068 size prefix, except for instructions that will ignore this
4069 prefix anyway. */
ca61edf2 4070 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4071 {
ca61edf2
L		 4072 /* The address size override prefix changes the size of the
4073 first operand. */
40fb9820
L		 4074 if ((flag_code == CODE_32BIT
4075 && i.op->regs[0].reg_type.bitfield.reg16)
4076 || (flag_code != CODE_32BIT
4077 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4078 if (!add_prefix (ADDR_PREFIX_OPCODE))
4079 return 0;
4080 }
4081 else if (i.suffix != QWORD_MNEM_SUFFIX
4082 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4083 && !i.tm.opcode_modifier.ignoresize
4084 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4085 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4086 || (flag_code == CODE_64BIT
40fb9820 4087 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4088 {
4089 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4090
40fb9820 4091 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4092 prefix = ADDR_PREFIX_OPCODE;
252b5132 4093
29b0f896
AM		 4094 if (!add_prefix (prefix))
4095 return 0;
24eab124 4096 }
252b5132 4097
29b0f896
AM		 4098 /* Set mode64 for an operand. */
4099 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4100 && flag_code == CODE_64BIT
40fb9820 4101 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4102 {
4103 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4104 need rex64. cmpxchg8b is also a special case. */
4105 if (! (i.operands == 2
4106 && i.tm.base_opcode == 0x90
4107 && i.tm.extension_opcode == None
0dfbf9d7
L		 4108 && operand_type_equal (&i.types [0], &acc64)
4109 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4110 && ! (i.operands == 1
4111 && i.tm.base_opcode == 0xfc7
4112 && i.tm.extension_opcode == 1
40fb9820
L		 4113 && !operand_type_check (i.types [0], reg)
4114 && operand_type_check (i.types [0], anymem)))
f6bee062 4115 i.rex |= REX_W;
46e883c5 4116 }
3e73aa7c 4117
29b0f896
AM		 4118 /* Size floating point instruction. */
4119 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4120 if (i.tm.opcode_modifier.floatmf)
543613e9 4121 i.tm.base_opcode ^= 4;
29b0f896 4122 }
7ecd2f8b 4123
29b0f896
AM		 4124 return 1;
4125}
3e73aa7c 4126
29b0f896 4127static int
543613e9 4128check_byte_reg (void)
29b0f896
AM		 4129{
4130 int op;
543613e9 4131
29b0f896
AM		 4132 for (op = i.operands; --op >= 0;)
4133 {
4134 /* If this is an eight bit register, it's OK. If it's the 16 or
4135 32 bit version of an eight bit register, we will just use the
4136 low portion, and that's OK too. */
40fb9820 4137 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4138 continue;
4139
ca61edf2
L		 4140 /* Don't generate this warning if not needed. */
4141 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 4142 continue;
4143
9344ff29
L		 4144 /* crc32 doesn't generate this warning. */
4145 if (i.tm.base_opcode == 0xf20f38f0)
4146 continue;
4147
40fb9820
L		 4148 if ((i.types[op].bitfield.reg16
4149 || i.types[op].bitfield.reg32
4150 || i.types[op].bitfield.reg64)
4151 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4152 {
4153 /* Prohibit these changes in the 64bit mode, since the
4154 lowering is more complicated. */
4155 if (flag_code == CODE_64BIT
40fb9820 4156 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4157 {
2ca3ace5
L		 4158 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4159 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4160 i.suffix);
4161 return 0;
4162 }
4163#if REGISTER_WARNINGS
4164 if (!quiet_warnings
40fb9820 4165 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4166 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4167 register_prefix,
40fb9820 4168 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4169 ? REGNAM_AL - REGNAM_AX
4170 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4171 register_prefix,
29b0f896
AM		 4172 i.op[op].regs->reg_name,
4173 i.suffix);
4174#endif
4175 continue;
4176 }
4177 /* Any other register is bad. */
40fb9820
L		 4178 if (i.types[op].bitfield.reg16
4179 || i.types[op].bitfield.reg32
4180 || i.types[op].bitfield.reg64
4181 || i.types[op].bitfield.regmmx
4182 || i.types[op].bitfield.regxmm
c0f3af97 4183 || i.types[op].bitfield.regymm
40fb9820
L		 4184 || i.types[op].bitfield.sreg2
4185 || i.types[op].bitfield.sreg3
4186 || i.types[op].bitfield.control
4187 || i.types[op].bitfield.debug
4188 || i.types[op].bitfield.test
4189 || i.types[op].bitfield.floatreg
4190 || i.types[op].bitfield.floatacc)
29b0f896 4191 {
a540244d
L		 4192 as_bad (_("`%s%s' not allowed with `%s%c'"),
4193 register_prefix,
29b0f896
AM		 4194 i.op[op].regs->reg_name,
4195 i.tm.name,
4196 i.suffix);
4197 return 0;
4198 }
4199 }
4200 return 1;
4201}
4202
4203static int
e3bb37b5 4204check_long_reg (void)
29b0f896
AM		 4205{
4206 int op;
4207
4208 for (op = i.operands; --op >= 0;)
4209 /* Reject eight bit registers, except where the template requires
4210 them. (eg. movzb) */
40fb9820
L		 4211 if (i.types[op].bitfield.reg8
4212 && (i.tm.operand_types[op].bitfield.reg16
4213 || i.tm.operand_types[op].bitfield.reg32
4214 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4215 {
a540244d
L		 4216 as_bad (_("`%s%s' not allowed with `%s%c'"),
4217 register_prefix,
29b0f896
AM		 4218 i.op[op].regs->reg_name,
4219 i.tm.name,
4220 i.suffix);
4221 return 0;
4222 }
4223 /* Warn if the e prefix on a general reg is missing. */
4224 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4225 && i.types[op].bitfield.reg16
4226 && (i.tm.operand_types[op].bitfield.reg32
4227 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4228 {
4229 /* Prohibit these changes in the 64bit mode, since the
4230 lowering is more complicated. */
4231 if (flag_code == CODE_64BIT)
252b5132 4232 {
2ca3ace5
L		 4233 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4234 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4235 i.suffix);
4236 return 0;
252b5132 4237 }
29b0f896
AM		 4238#if REGISTER_WARNINGS
4239 else
a540244d
L		 4240 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4241 register_prefix,
29b0f896 4242 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4243 register_prefix,
29b0f896
AM		 4244 i.op[op].regs->reg_name,
4245 i.suffix);
4246#endif
252b5132 4247 }
29b0f896 4248 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4249 else if (i.types[op].bitfield.reg64
4250 && (i.tm.operand_types[op].bitfield.reg32
4251 || i.tm.operand_types[op].bitfield.acc))
252b5132 4252 {
34828aad 4253 if (intel_syntax
ca61edf2 4254 && i.tm.opcode_modifier.toqword
40fb9820 4255 && !i.types[0].bitfield.regxmm)
34828aad 4256 {
ca61edf2 4257 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4258 i.suffix = QWORD_MNEM_SUFFIX;
4259 }
4260 else
4261 {
4262 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4263 register_prefix, i.op[op].regs->reg_name,
4264 i.suffix);
4265 return 0;
4266 }
29b0f896
AM		 4267 }
4268 return 1;
4269}
252b5132 4270
29b0f896 4271static int
e3bb37b5 4272check_qword_reg (void)
29b0f896
AM		 4273{
4274 int op;
252b5132 4275
29b0f896
AM		 4276 for (op = i.operands; --op >= 0; )
4277 /* Reject eight bit registers, except where the template requires
4278 them. (eg. movzb) */
40fb9820
L		 4279 if (i.types[op].bitfield.reg8
4280 && (i.tm.operand_types[op].bitfield.reg16
4281 || i.tm.operand_types[op].bitfield.reg32
4282 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4283 {
a540244d
L		 4284 as_bad (_("`%s%s' not allowed with `%s%c'"),
4285 register_prefix,
29b0f896
AM		 4286 i.op[op].regs->reg_name,
4287 i.tm.name,
4288 i.suffix);
4289 return 0;
4290 }
4291 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4292 else if ((i.types[op].bitfield.reg16
4293 || i.types[op].bitfield.reg32)
4294 && (i.tm.operand_types[op].bitfield.reg32
4295 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4296 {
4297 /* Prohibit these changes in the 64bit mode, since the
4298 lowering is more complicated. */
34828aad 4299 if (intel_syntax
ca61edf2 4300 && i.tm.opcode_modifier.todword
40fb9820 4301 && !i.types[0].bitfield.regxmm)
34828aad 4302 {
ca61edf2 4303 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4304 i.suffix = LONG_MNEM_SUFFIX;
4305 }
4306 else
4307 {
4308 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4309 register_prefix, i.op[op].regs->reg_name,
4310 i.suffix);
4311 return 0;
4312 }
252b5132 4313 }
29b0f896
AM		 4314 return 1;
4315}
252b5132 4316
29b0f896 4317static int
e3bb37b5 4318check_word_reg (void)
29b0f896
AM		 4319{
4320 int op;
4321 for (op = i.operands; --op >= 0;)
4322 /* Reject eight bit registers, except where the template requires
4323 them. (eg. movzb) */
40fb9820
L		 4324 if (i.types[op].bitfield.reg8
4325 && (i.tm.operand_types[op].bitfield.reg16
4326 || i.tm.operand_types[op].bitfield.reg32
4327 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4328 {
a540244d
L		 4329 as_bad (_("`%s%s' not allowed with `%s%c'"),
4330 register_prefix,
29b0f896
AM		 4331 i.op[op].regs->reg_name,
4332 i.tm.name,
4333 i.suffix);
4334 return 0;
4335 }
4336 /* Warn if the e prefix on a general reg is present. */
4337 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4338 && i.types[op].bitfield.reg32
4339 && (i.tm.operand_types[op].bitfield.reg16
4340 || i.tm.operand_types[op].bitfield.acc))
252b5132 4341 {
29b0f896
AM		 4342 /* Prohibit these changes in the 64bit mode, since the
4343 lowering is more complicated. */
4344 if (flag_code == CODE_64BIT)
252b5132 4345 {
2ca3ace5
L		 4346 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4347 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4348 i.suffix);
4349 return 0;
252b5132 4350 }
29b0f896
AM		 4351 else
4352#if REGISTER_WARNINGS
a540244d
L		 4353 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4354 register_prefix,
29b0f896 4355 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4356 register_prefix,
29b0f896
AM		 4357 i.op[op].regs->reg_name,
4358 i.suffix);
4359#endif
4360 }
4361 return 1;
4362}
252b5132 4363
29b0f896 4364static int
40fb9820 4365update_imm (unsigned int j)
29b0f896 4366{
40fb9820
L		 4367 i386_operand_type overlap;
4368
c6fb90c8 4369 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 4370 if ((overlap.bitfield.imm8
4371 || overlap.bitfield.imm8s
4372 || overlap.bitfield.imm16
4373 || overlap.bitfield.imm32
4374 || overlap.bitfield.imm32s
4375 || overlap.bitfield.imm64)
0dfbf9d7
L		 4376 && !operand_type_equal (&overlap, &imm8)
4377 && !operand_type_equal (&overlap, &imm8s)
4378 && !operand_type_equal (&overlap, &imm16)
4379 && !operand_type_equal (&overlap, &imm32)
4380 && !operand_type_equal (&overlap, &imm32s)
4381 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4382 {
4383 if (i.suffix)
4384 {
40fb9820
L		 4385 i386_operand_type temp;
4386
0dfbf9d7 4387 operand_type_set (&temp, 0);
40fb9820
L		 4388 if (i.suffix == BYTE_MNEM_SUFFIX)
4389 {
4390 temp.bitfield.imm8 = overlap.bitfield.imm8;
4391 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4392 }
4393 else if (i.suffix == WORD_MNEM_SUFFIX)
4394 temp.bitfield.imm16 = overlap.bitfield.imm16;
4395 else if (i.suffix == QWORD_MNEM_SUFFIX)
4396 {
4397 temp.bitfield.imm64 = overlap.bitfield.imm64;
4398 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4399 }
4400 else
4401 temp.bitfield.imm32 = overlap.bitfield.imm32;
4402 overlap = temp;
29b0f896 4403 }
0dfbf9d7
L		 4404 else if (operand_type_equal (&overlap, &imm16_32_32s)
4405 || operand_type_equal (&overlap, &imm16_32)
4406 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4407 {
40fb9820 4408 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4409 overlap = imm16;
40fb9820 4410 else
65da13b5 4411 overlap = imm32s;
29b0f896 4412 }
0dfbf9d7
L		 4413 if (!operand_type_equal (&overlap, &imm8)
4414 && !operand_type_equal (&overlap, &imm8s)
4415 && !operand_type_equal (&overlap, &imm16)
4416 && !operand_type_equal (&overlap, &imm32)
4417 && !operand_type_equal (&overlap, &imm32s)
4418 && !operand_type_equal (&overlap, &imm64))
29b0f896 4419 {
4eed87de
AM		 4420 as_bad (_("no instruction mnemonic suffix given; "
4421 "can't determine immediate size"));
29b0f896
AM		 4422 return 0;
4423 }
4424 }
40fb9820 4425 i.types[j] = overlap;
29b0f896 4426
40fb9820
L		 4427 return 1;
4428}
4429
4430static int
4431finalize_imm (void)
4432{
4433 unsigned int j;
29b0f896 4434
40fb9820
L		 4435 for (j = 0; j < 2; j++)
4436 if (update_imm (j) == 0)
4437 return 0;
4438
c6fb90c8 4439 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 4440 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 4441
4442 return 1;
4443}
4444
85f10a01
MM		 4445static void
4446process_drex (void)
4447{
5dd15031
JJ		 4448 i.drex.modrm_reg = 0;
4449 i.drex.modrm_regmem = 0;
85f10a01
MM		 4450
4451 /* SSE5 4 operand instructions must have the destination the same as
4452 one of the inputs. Figure out the destination register and cache
4453 it away in the drex field, and remember which fields to use for
4454 the modrm byte. */
4455 if (i.tm.opcode_modifier.drex
4456 && i.tm.opcode_modifier.drexv
4457 && i.operands == 4)
4458 {
4459 i.tm.extension_opcode = None;
4460
4461 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4462 if (i.types[0].bitfield.regxmm != 0
4463 && i.types[1].bitfield.regxmm != 0
4464 && i.types[2].bitfield.regxmm != 0
4465 && i.types[3].bitfield.regxmm != 0
4466 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4467 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4468 {
4469 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4470 operand_type_set (&i.types[0], 0);
4471 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4472 i.reg_operands -= 2;
4473
4474 /* There are two different ways to encode a 4 operand
4475 instruction with all registers that uses OC1 set to
4476 0 or 1. Favor setting OC1 to 0 since this mimics the
4477 actions of other SSE5 assemblers. Use modrm encoding 2
4478 for register/register. Include the high order bit that
4479 is normally stored in the REX byte in the register
4480 field. */
4481 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4482 i.drex.modrm_reg = 2;
4483 i.drex.modrm_regmem = 1;
4484 i.drex.reg = (i.op[3].regs->reg_num
4485 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4486 }
4487
4488 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4489 else if (i.types[0].bitfield.regxmm != 0
4490 && i.types[1].bitfield.regxmm != 0
4491 && (i.types[2].bitfield.regxmm
4492 || operand_type_check (i.types[2], anymem))
4493 && i.types[3].bitfield.regxmm != 0
4494 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4495 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4496 {
4497 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4498 operand_type_set (&i.types[0], 0);
4499 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4500 i.reg_operands -= 2;
4501
4502 /* Specify the modrm encoding for memory addressing. Include
4503 the high order bit that is normally stored in the REX byte
4504 in the register field. */
4505 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4506 i.drex.modrm_reg = 1;
4507 i.drex.modrm_regmem = 2;
4508 i.drex.reg = (i.op[3].regs->reg_num
4509 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4510 }
4511
4512 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4513 else if (i.types[0].bitfield.regxmm != 0
4514 && operand_type_check (i.types[1], anymem) != 0
4515 && i.types[2].bitfield.regxmm != 0
4516 && i.types[3].bitfield.regxmm != 0
4517 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4518 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4519 {
4520 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4521 operand_type_set (&i.types[0], 0);
4522 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4523 i.reg_operands -= 2;
4524
4525 /* Specify the modrm encoding for memory addressing. Include
4526 the high order bit that is normally stored in the REX byte
4527 in the register field. */
4528 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4529 i.drex.modrm_reg = 2;
4530 i.drex.modrm_regmem = 1;
4531 i.drex.reg = (i.op[3].regs->reg_num
4532 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4533 }
4534
4535 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4536 else if (i.types[0].bitfield.regxmm != 0
4537 && i.types[1].bitfield.regxmm != 0
4538 && i.types[2].bitfield.regxmm != 0
4539 && i.types[3].bitfield.regxmm != 0
4540 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4541 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4542 {
4543 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4544 operand_type_set (&i.types[2], 0);
4545 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4546 i.reg_operands -= 2;
4547
4548 /* There are two different ways to encode a 4 operand
4549 instruction with all registers that uses OC1 set to
4550 0 or 1. Favor setting OC1 to 0 since this mimics the
4551 actions of other SSE5 assemblers. Use modrm encoding
4552 2 for register/register. Include the high order bit that
4553 is normally stored in the REX byte in the register
4554 field. */
4555 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4556 i.drex.modrm_reg = 1;
4557 i.drex.modrm_regmem = 0;
4558
4559 /* Remember the register, including the upper bits */
4560 i.drex.reg = (i.op[3].regs->reg_num
4561 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4562 }
4563
4564 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4565 else if (i.types[0].bitfield.regxmm != 0
4566 && (i.types[1].bitfield.regxmm
4567 || operand_type_check (i.types[1], anymem))
4568 && i.types[2].bitfield.regxmm != 0
4569 && i.types[3].bitfield.regxmm != 0
4570 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4571 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4572 {
4573 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4574 operand_type_set (&i.types[2], 0);
4575 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4576 i.reg_operands -= 2;
4577
4578 /* Specify the modrm encoding and remember the register
4579 including the bits normally stored in the REX byte. */
4580 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4581 i.drex.modrm_reg = 0;
4582 i.drex.modrm_regmem = 1;
4583 i.drex.reg = (i.op[3].regs->reg_num
4584 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4585 }
4586
4587 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4588 else if (operand_type_check (i.types[0], anymem) != 0
4589 && i.types[1].bitfield.regxmm != 0
4590 && i.types[2].bitfield.regxmm != 0
4591 && i.types[3].bitfield.regxmm != 0
4592 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4593 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4594 {
4595 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4596 operand_type_set (&i.types[2], 0);
4597 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4598 i.reg_operands -= 2;
4599
4600 /* Specify the modrm encoding and remember the register
4601 including the bits normally stored in the REX byte. */
4602 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4603 i.drex.modrm_reg = 1;
4604 i.drex.modrm_regmem = 0;
4605 i.drex.reg = (i.op[3].regs->reg_num
4606 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4607 }
4608
4609 else
4610 as_bad (_("Incorrect operands for the '%s' instruction"),
4611 i.tm.name);
4612 }
4613
4614 /* SSE5 instructions with the DREX byte where the only memory operand
4615 is in the 2nd argument, and the first and last xmm register must
4616 match, and is encoded in the DREX byte. */
4617 else if (i.tm.opcode_modifier.drex
4618 && !i.tm.opcode_modifier.drexv
4619 && i.operands == 4)
4620 {
4621 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4622 if (i.types[0].bitfield.regxmm != 0
4623 && (i.types[1].bitfield.regxmm
4624 || operand_type_check(i.types[1], anymem))
4625 && i.types[2].bitfield.regxmm != 0
4626 && i.types[3].bitfield.regxmm != 0
4627 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4628 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4629 {
4630 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4631 operand_type_set (&i.types[0], 0);
4632 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4633 i.reg_operands -= 2;
4634
4635 /* Specify the modrm encoding and remember the register
4636 including the high bit normally stored in the REX
4637 byte. */
4638 i.drex.modrm_reg = 2;
4639 i.drex.modrm_regmem = 1;
4640 i.drex.reg = (i.op[3].regs->reg_num
4641 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4642 }
4643
4644 else
4645 as_bad (_("Incorrect operands for the '%s' instruction"),
4646 i.tm.name);
4647 }
4648
4649 /* SSE5 3 operand instructions that the result is a register, being
4650 either operand can be a memory operand, using OC0 to note which
4651 one is the memory. */
4652 else if (i.tm.opcode_modifier.drex
4653 && i.tm.opcode_modifier.drexv
4654 && i.operands == 3)
4655 {
4656 i.tm.extension_opcode = None;
4657
4658 /* Case 1: 3 operand insn, src1 = register. */
4659 if (i.types[0].bitfield.regxmm != 0
4660 && i.types[1].bitfield.regxmm != 0
4661 && i.types[2].bitfield.regxmm != 0)
4662 {
4663 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4664 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4665 i.reg_operands--;
4666
4667 /* Specify the modrm encoding and remember the register
4668 including the high bit normally stored in the REX byte. */
4669 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4670 i.drex.modrm_reg = 1;
4671 i.drex.modrm_regmem = 0;
4672 i.drex.reg = (i.op[2].regs->reg_num
4673 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4674 }
4675
4676 /* Case 2: 3 operand insn, src1 = memory. */
4677 else if (operand_type_check (i.types[0], anymem) != 0
4678 && i.types[1].bitfield.regxmm != 0
4679 && i.types[2].bitfield.regxmm != 0)
4680 {
4681 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4682 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4683 i.reg_operands--;
4684
4685 /* Specify the modrm encoding and remember the register
4686 including the high bit normally stored in the REX
4687 byte. */
4688 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4689 i.drex.modrm_reg = 1;
4690 i.drex.modrm_regmem = 0;
4691 i.drex.reg = (i.op[2].regs->reg_num
4692 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4693 }
4694
4695 /* Case 3: 3 operand insn, src2 = memory. */
4696 else if (i.types[0].bitfield.regxmm != 0
4697 && operand_type_check (i.types[1], anymem) != 0
4698 && i.types[2].bitfield.regxmm != 0)
4699 {
4700 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4701 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4702 i.reg_operands--;
4703
4704 /* Specify the modrm encoding and remember the register
4705 including the high bit normally stored in the REX byte. */
4706 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4707 i.drex.modrm_reg = 0;
4708 i.drex.modrm_regmem = 1;
4709 i.drex.reg = (i.op[2].regs->reg_num
4710 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4711 }
4712
4713 else
4714 as_bad (_("Incorrect operands for the '%s' instruction"),
4715 i.tm.name);
4716 }
4717
4718 /* SSE5 4 operand instructions that are the comparison instructions
4719 where the first operand is the immediate value of the comparison
4720 to be done. */
4721 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4722 {
4723 /* Case 1: 4 operand insn, src1 = reg/memory. */
4724 if (operand_type_check (i.types[0], imm) != 0
4725 && (i.types[1].bitfield.regxmm
4726 || operand_type_check (i.types[1], anymem))
4727 && i.types[2].bitfield.regxmm != 0
4728 && i.types[3].bitfield.regxmm != 0)
4729 {
4730 /* clear the arguments that are stored in drex */
0dfbf9d7 4731 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4732 i.reg_operands--;
4733
4734 /* Specify the modrm encoding and remember the register
4735 including the high bit normally stored in the REX byte. */
4736 i.drex.modrm_reg = 2;
4737 i.drex.modrm_regmem = 1;
4738 i.drex.reg = (i.op[3].regs->reg_num
4739 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4740 }
4741
4742 /* Case 2: 3 operand insn with ImmExt that places the
4743 opcode_extension as an immediate argument. This is used for
4744 all of the varients of comparison that supplies the appropriate
4745 value as part of the instruction. */
4746 else if ((i.types[0].bitfield.regxmm
4747 || operand_type_check (i.types[0], anymem))
4748 && i.types[1].bitfield.regxmm != 0
4749 && i.types[2].bitfield.regxmm != 0
4750 && operand_type_check (i.types[3], imm) != 0)
4751 {
4752 /* clear the arguments that are stored in drex */
0dfbf9d7 4753 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4754 i.reg_operands--;
4755
4756 /* Specify the modrm encoding and remember the register
4757 including the high bit normally stored in the REX byte. */
4758 i.drex.modrm_reg = 1;
4759 i.drex.modrm_regmem = 0;
4760 i.drex.reg = (i.op[2].regs->reg_num
4761 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4762 }
4763
4764 else
4765 as_bad (_("Incorrect operands for the '%s' instruction"),
4766 i.tm.name);
4767 }
4768
4769 else if (i.tm.opcode_modifier.drex
4770 || i.tm.opcode_modifier.drexv
4771 || i.tm.opcode_modifier.drexc)
4772 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4773}
4774
c0f3af97
L		 4775static int
4776bad_implicit_operand (int xmm)
4777{
4778 const char *reg = xmm ? "xmm0" : "ymm0";
4779 if (intel_syntax)
4780 as_bad (_("the last operand of `%s' must be `%s%s'"),
4781 i.tm.name, register_prefix, reg);
4782 else
4783 as_bad (_("the first operand of `%s' must be `%s%s'"),
4784 i.tm.name, register_prefix, reg);
4785 return 0;
4786}
4787
29b0f896 4788static int
e3bb37b5 4789process_operands (void)
29b0f896
AM		 4790{
4791 /* Default segment register this instruction will use for memory
4792 accesses. 0 means unknown. This is only for optimizing out
4793 unnecessary segment overrides. */
4794 const seg_entry *default_seg = 0;
4795
85f10a01
MM		 4796 /* Handle all of the DREX munging that SSE5 needs. */
4797 if (i.tm.opcode_modifier.drex
4798 || i.tm.opcode_modifier.drexv
4799 || i.tm.opcode_modifier.drexc)
4800 process_drex ();
4801
c0f3af97
L		 4802 if (i.tm.opcode_modifier.sse2avx
4803 && (i.tm.opcode_modifier.vexnds
4804 || i.tm.opcode_modifier.vexndd))
29b0f896 4805 {
c0f3af97
L		 4806 unsigned int dup = i.operands;
4807 unsigned int dest = dup - 1;
9fcfb3d7
L		 4808 unsigned int j;
4809
c0f3af97 4810 /* The destination must be an xmm register. */
0dfbf9d7 4811 assert (i.reg_operands
c0f3af97
L		 4812 && MAX_OPERANDS > dup
4813 && operand_type_equal (&i.types[dest], &regxmm));
4814
4815 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4816 {
c0f3af97
L		 4817 /* The first operand is implicit and must be xmm0. */
4818 assert (operand_type_equal (&i.types[0], &regxmm));
4819 if (i.op[0].regs->reg_num != 0)
4820 return bad_implicit_operand (1);
4821
4822 if (i.tm.opcode_modifier.vex3sources)
4823 {
4824 /* Keep xmm0 for instructions with VEX prefix and 3
4825 sources. */
4826 goto duplicate;
4827 }
e2ec9d29 4828 else
c0f3af97
L		 4829 {
4830 /* We remove the first xmm0 and keep the number of
4831 operands unchanged, which in fact duplicates the
4832 destination. */
4833 for (j = 1; j < i.operands; j++)
4834 {
4835 i.op[j - 1] = i.op[j];
4836 i.types[j - 1] = i.types[j];
4837 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4838 }
4839 }
4840 }
4841 else if (i.tm.opcode_modifier.implicit1stxmm0)
4842 {
4843 assert ((MAX_OPERANDS - 1) > dup
4844 && i.tm.opcode_modifier.vex3sources);
4845
4846 /* Add the implicit xmm0 for instructions with VEX prefix
4847 and 3 sources. */
4848 for (j = i.operands; j > 0; j--)
4849 {
4850 i.op[j] = i.op[j - 1];
4851 i.types[j] = i.types[j - 1];
4852 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4853 }
4854 i.op[0].regs
4855 = (const reg_entry *) hash_find (reg_hash, "xmm0");
4856 i.types[0] = regxmm;
4857 i.tm.operand_types[0] = regxmm;
4858
4859 i.operands += 2;
4860 i.reg_operands += 2;
4861 i.tm.operands += 2;
4862
4863 dup++;
4864 dest++;
4865 i.op[dup] = i.op[dest];
4866 i.types[dup] = i.types[dest];
4867 i.tm.operand_types[dup] = i.tm.operand_types[dest];
e2ec9d29 4868 }
c0f3af97
L		 4869 else
4870 {
4871duplicate:
4872 i.operands++;
4873 i.reg_operands++;
4874 i.tm.operands++;
4875
4876 i.op[dup] = i.op[dest];
4877 i.types[dup] = i.types[dest];
4878 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4879 }
4880
4881 if (i.tm.opcode_modifier.immext)
4882 process_immext ();
4883 }
4884 else if (i.tm.opcode_modifier.firstxmm0)
4885 {
4886 unsigned int j;
4887
4888 /* The first operand is implicit and must be xmm0/ymm0. */
4889 assert (i.reg_operands
4890 && (operand_type_equal (&i.types[0], &regxmm)
4891 || operand_type_equal (&i.types[0], &regymm)));
4892 if (i.op[0].regs->reg_num != 0)
4893 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4894
4895 for (j = 1; j < i.operands; j++)
4896 {
4897 i.op[j - 1] = i.op[j];
4898 i.types[j - 1] = i.types[j];
4899
4900 /* We need to adjust fields in i.tm since they are used by
4901 build_modrm_byte. */
4902 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4903 }
4904
e2ec9d29
L		 4905 i.operands--;
4906 i.reg_operands--;
e2ec9d29
L		 4907 i.tm.operands--;
4908 }
4909 else if (i.tm.opcode_modifier.regkludge)
4910 {
4911 /* The imul $imm, %reg instruction is converted into
4912 imul $imm, %reg, %reg, and the clr %reg instruction
4913 is converted into xor %reg, %reg. */
4914
4915 unsigned int first_reg_op;
4916
4917 if (operand_type_check (i.types[0], reg))
4918 first_reg_op = 0;
4919 else
4920 first_reg_op = 1;
4921 /* Pretend we saw the extra register operand. */
4922 assert (i.reg_operands == 1
4923 && i.op[first_reg_op + 1].regs == 0);
4924 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4925 i.types[first_reg_op + 1] = i.types[first_reg_op];
4926 i.operands++;
4927 i.reg_operands++;
29b0f896
AM		 4928 }
4929
40fb9820 4930 if (i.tm.opcode_modifier.shortform)
29b0f896 4931 {
40fb9820
L		 4932 if (i.types[0].bitfield.sreg2
4933 || i.types[0].bitfield.sreg3)
29b0f896 4934 {
4eed87de
AM		 4935 if (i.tm.base_opcode == POP_SEG_SHORT
4936 && i.op[0].regs->reg_num == 1)
29b0f896 4937 {
4eed87de
AM		 4938 as_bad (_("you can't `pop %%cs'"));
4939 return 0;
29b0f896 4940 }
4eed87de
AM		 4941 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4942 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4943 i.rex |= REX_B;
4eed87de
AM		 4944 }
4945 else
4946 {
85f10a01
MM		 4947 /* The register or float register operand is in operand
4948 0 or 1. */
40fb9820
L		 4949 unsigned int op;
4950
4951 if (i.types[0].bitfield.floatreg
4952 || operand_type_check (i.types[0], reg))
4953 op = 0;
4954 else
4955 op = 1;
4eed87de
AM		 4956 /* Register goes in low 3 bits of opcode. */
4957 i.tm.base_opcode |= i.op[op].regs->reg_num;
4958 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4959 i.rex |= REX_B;
40fb9820 4960 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4961 {
4eed87de
AM		 4962 /* Warn about some common errors, but press on regardless.
4963 The first case can be generated by gcc (<= 2.8.1). */
4964 if (i.operands == 2)
4965 {
4966 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 4967 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4968 register_prefix, i.op[1].regs->reg_name,
4969 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 4970 }
4971 else
4972 {
4973 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4974 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4975 register_prefix, i.op[0].regs->reg_name);
4eed87de 4976 }
29b0f896
AM		 4977 }
4978 }
4979 }
40fb9820 4980 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4981 {
4982 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4983 must be put into the modrm byte). Now, we make the modrm and
4984 index base bytes based on all the info we've collected. */
29b0f896
AM		 4985
4986 default_seg = build_modrm_byte ();
4987 }
8a2ed489 4988 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4989 {
4990 default_seg = &ds;
4991 }
40fb9820 4992 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4993 {
4994 /* For the string instructions that allow a segment override
4995 on one of their operands, the default segment is ds. */
4996 default_seg = &ds;
4997 }
4998
75178d9d
L		 4999 if (i.tm.base_opcode == 0x8d /* lea */
5000 && i.seg[0]
5001 && !quiet_warnings)
30123838 5002 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5003
5004 /* If a segment was explicitly specified, and the specified segment
5005 is not the default, use an opcode prefix to select it. If we
5006 never figured out what the default segment is, then default_seg
5007 will be zero at this point, and the specified segment prefix will
5008 always be used. */
29b0f896
AM		 5009 if ((i.seg[0]) && (i.seg[0] != default_seg))
5010 {
5011 if (!add_prefix (i.seg[0]->seg_prefix))
5012 return 0;
5013 }
5014 return 1;
5015}
5016
5017static const seg_entry *
e3bb37b5 5018build_modrm_byte (void)
29b0f896
AM		 5019{
5020 const seg_entry *default_seg = 0;
c0f3af97
L		 5021 unsigned int source, dest;
5022 int vex_3_sources;
5023
5024 /* The first operand of instructions with VEX prefix and 3 sources
5025 must be VEX_Imm4. */
5026 vex_3_sources = i.tm.opcode_modifier.vex3sources;
5027 if (vex_3_sources)
5028 {
5029 unsigned int nds, reg;
5030
5031 if (i.tm.opcode_modifier.veximmext
5032 && i.tm.opcode_modifier.immext)
5033 {
5034 dest = i.operands - 2;
5035 assert (dest == 3);
5036 }
5037 else
5038 dest = i.operands - 1;
5039 nds = dest - 1;
5040
5041 /* There are 2 kinds of instructions:
dae39acc 5042 1. 5 operands: one immediate operand and 4 register
c0f3af97
L		 5043 operands or 3 register operands plus 1 memory operand.
5044 It must have VexNDS and VexW0 or VexW1. The destination
5045 must be either XMM or YMM register.
5046 2. 4 operands: 4 register operands or 3 register operands
5047 plus 1 memory operand. It must have VexNDS and VexImmExt. */
5048 if (!((i.reg_operands == 4
5049 || (i.reg_operands == 3 && i.mem_operands == 1))
5050 && i.tm.opcode_modifier.vexnds
5051 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5052 || operand_type_equal (&i.tm.operand_types[dest], &regymm))
c0f3af97
L		 5053 && ((dest == 4
5054 && i.imm_operands == 1
5055 && i.types[0].bitfield.vex_imm4
5056 && (i.tm.opcode_modifier.vexw0
5057 || i.tm.opcode_modifier.vexw1))
5058 || (dest == 3
5059 && (i.imm_operands == 0
5060 || (i.imm_operands == 1
5061 && i.tm.opcode_modifier.immext))
5062 && i.tm.opcode_modifier.veximmext))))
5063 abort ();
5064
c0f3af97
L		 5065 if (i.imm_operands == 0)
5066 {
5067 /* When there is no immediate operand, generate an 8bit
5068 immediate operand to encode the first operand. */
5069 expressionS *exp = &im_expressions[i.imm_operands++];
5070 i.op[i.operands].imms = exp;
5071 i.types[i.operands] = imm8;
5072 i.operands++;
5073 /* If VexW1 is set, the first operand is the source and
5074 the second operand is encoded in the immediate operand. */
5075 if (i.tm.opcode_modifier.vexw1)
5076 {
5077 source = 0;
5078 reg = 1;
5079 }
5080 else
5081 {
5082 source = 1;
5083 reg = 0;
5084 }
dae39acc
L		 5085
5086 /* FMA swaps REG and NDS. */
5087 if (i.tm.cpu_flags.bitfield.cpufma)
5088 {
5089 unsigned int tmp;
5090 tmp = reg;
5091 reg = nds;
5092 nds = tmp;
5093 }
5094
c0f3af97
L		 5095 assert (operand_type_equal (&i.tm.operand_types[reg], &regxmm)
5096 || operand_type_equal (&i.tm.operand_types[reg],
5097 &regymm));
5098 exp->X_op = O_constant;
5099 exp->X_add_number
5100 = ((i.op[reg].regs->reg_num
5101 + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
5102 }
5103 else
5104 {
5105 unsigned int imm;
5106
5107 if (i.tm.opcode_modifier.vexw0)
5108 {
5109 /* If VexW0 is set, the third operand is the source and
5110 the second operand is encoded in the immediate
5111 operand. */
5112 source = 2;
5113 reg = 1;
5114 }
5115 else
5116 {
5117 /* VexW1 is set, the second operand is the source and
5118 the third operand is encoded in the immediate
5119 operand. */
5120 source = 1;
5121 reg = 2;
5122 }
5123
5124 if (i.tm.opcode_modifier.immext)
5125 {
5126 /* When ImmExt is set, the immdiate byte is the last
5127 operand. */
5128 imm = i.operands - 1;
5129 source--;
5130 reg--;
5131 }
5132 else
5133 {
5134 imm = 0;
5135
5136 /* Turn on Imm8 so that output_imm will generate it. */
5137 i.types[imm].bitfield.imm8 = 1;
5138 }
5139
5140 assert (operand_type_equal (&i.tm.operand_types[reg], &regxmm)
5141 || operand_type_equal (&i.tm.operand_types[reg],
5142 &regymm));
5143 i.op[imm].imms->X_add_number
5144 |= ((i.op[reg].regs->reg_num
5145 + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
5146 }
dae39acc
L		 5147
5148 assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5149 || operand_type_equal (&i.tm.operand_types[nds], &regymm));
5150 i.vex.register_specifier = i.op[nds].regs;
5151
c0f3af97
L		 5152 }
5153 else
5154 source = dest = 0;
29b0f896 5155
85f10a01
MM		 5156 /* SSE5 4 operand instructions are encoded in such a way that one of
5157 the inputs must match the destination register. Process_drex hides
5158 the 3rd argument in the drex field, so that by the time we get
5159 here, it looks to GAS as if this is a 2 operand instruction. */
5160 if ((i.tm.opcode_modifier.drex
5161 || i.tm.opcode_modifier.drexv
b5016f89 5162 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5163 && i.reg_operands == 2)
5164 {
5165 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
5166 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
5167
5168 i.rm.reg = reg->reg_num;
5169 i.rm.regmem = regmem->reg_num;
5170 i.rm.mode = 3;
5171 if ((reg->reg_flags & RegRex) != 0)
5172 i.rex |= REX_R;
5173 if ((regmem->reg_flags & RegRex) != 0)
5174 i.rex |= REX_B;
5175 }
5176
29b0f896 5177 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5178 implicit registers do not count. If there are 3 register
5179 operands, it must be a instruction with VexNDS. For a
5180 instruction with VexNDD, the destination register is encoded
5181 in VEX prefix. If there are 4 register operands, it must be
5182 a instruction with VEX prefix and 3 sources. */
5183 else if (i.mem_operands == 0
5184 && ((i.reg_operands == 2
5185 && !i.tm.opcode_modifier.vexndd)
5186 || (i.reg_operands == 3
5187 && i.tm.opcode_modifier.vexnds)
5188 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5189 {
cab737b9
L		 5190 switch (i.operands)
5191 {
5192 case 2:
5193 source = 0;
5194 break;
5195 case 3:
c81128dc
L		 5196 /* When there are 3 operands, one of them may be immediate,
5197 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5198 the first operand must be shift count register (cl) or it
5199 is an instruction with VexNDS. */
c81128dc
L		 5200 assert (i.imm_operands == 1
5201 || (i.imm_operands == 0
c0f3af97
L		 5202 && (i.tm.opcode_modifier.vexnds
5203 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5204 if (operand_type_check (i.types[0], imm)
5205 || i.types[0].bitfield.shiftcount)
5206 source = 1;
5207 else
5208 source = 0;
cab737b9
L		 5209 break;
5210 case 4:
368d64cc
L		 5211 /* When there are 4 operands, the first two must be 8bit
5212 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5213 one.
5214
5215 For instructions with VexNDS, if the first operand
5216 an imm8, the source operand is the 2nd one. If the last
5217 operand is imm8, the source operand is the first one. */
5218 assert ((i.imm_operands == 2
5219 && i.types[0].bitfield.imm8
5220 && i.types[1].bitfield.imm8)
5221 || (i.tm.opcode_modifier.vexnds
5222 && i.imm_operands == 1
5223 && (i.types[0].bitfield.imm8
5224 || i.types[i.operands - 1].bitfield.imm8)));
5225 if (i.tm.opcode_modifier.vexnds)
5226 {
5227 if (i.types[0].bitfield.imm8)
5228 source = 1;
5229 else
5230 source = 0;
5231 }
5232 else
5233 source = 2;
5234 break;
5235 case 5:
cab737b9
L		 5236 break;
5237 default:
5238 abort ();
5239 }
5240
c0f3af97
L		 5241 if (!vex_3_sources)
5242 {
5243 dest = source + 1;
5244
5245 if (i.tm.opcode_modifier.vexnds)
5246 {
5247 /* For instructions with VexNDS, the register-only
5248 source operand must be XMM or YMM register. It is
5249 encoded in VEX prefix. */
5250 if ((dest + 1) >= i.operands
5251 || (!operand_type_equal (&i.tm.operand_types[dest],
5252 &regxmm)
5253 && !operand_type_equal (&i.tm.operand_types[dest],
5254 &regymm)))
5255 abort ();
5256 i.vex.register_specifier = i.op[dest].regs;
5257 dest++;
5258 }
5259 }
29b0f896
AM		 5260
5261 i.rm.mode = 3;
5262 /* One of the register operands will be encoded in the i.tm.reg
5263 field, the other in the combined i.tm.mode and i.tm.regmem
5264 fields. If no form of this instruction supports a memory
5265 destination operand, then we assume the source operand may
5266 sometimes be a memory operand and so we need to store the
5267 destination in the i.rm.reg field. */
40fb9820
L		 5268 if (!i.tm.operand_types[dest].bitfield.regmem
5269 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5270 {
5271 i.rm.reg = i.op[dest].regs->reg_num;
5272 i.rm.regmem = i.op[source].regs->reg_num;
5273 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5274 i.rex |= REX_R;
29b0f896 5275 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5276 i.rex |= REX_B;
29b0f896
AM		 5277 }
5278 else
5279 {
5280 i.rm.reg = i.op[source].regs->reg_num;
5281 i.rm.regmem = i.op[dest].regs->reg_num;
5282 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5283 i.rex |= REX_B;
29b0f896 5284 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5285 i.rex |= REX_R;
29b0f896 5286 }
161a04f6 5287 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5288 {
40fb9820
L		 5289 if (!i.types[0].bitfield.control
5290 && !i.types[1].bitfield.control)
c4a530c5 5291 abort ();
161a04f6 5292 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5293 add_prefix (LOCK_PREFIX_OPCODE);
5294 }
29b0f896
AM		 5295 }
5296 else
5297 { /* If it's not 2 reg operands... */
c0f3af97
L		 5298 unsigned int mem;
5299
29b0f896
AM		 5300 if (i.mem_operands)
5301 {
5302 unsigned int fake_zero_displacement = 0;
99018f42 5303 unsigned int op;
4eed87de 5304
85f10a01
MM		 5305 /* This has been precalculated for SSE5 instructions
5306 that have a DREX field earlier in process_drex. */
b5016f89
L		 5307 if (i.tm.opcode_modifier.drex
5308 || i.tm.opcode_modifier.drexv
5309 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5310 op = i.drex.modrm_regmem;
5311 else
5312 {
c0209578
L		 5313 for (op = 0; op < i.operands; op++)
5314 if (operand_type_check (i.types[op], anymem))
5315 break;
5316 assert (op < i.operands);
85f10a01 5317 }
29b0f896
AM		 5318
5319 default_seg = &ds;
5320
5321 if (i.base_reg == 0)
5322 {
5323 i.rm.mode = 0;
5324 if (!i.disp_operands)
5325 fake_zero_displacement = 1;
5326 if (i.index_reg == 0)
5327 {
5328 /* Operand is just <disp> */
20f0a1fc 5329 if (flag_code == CODE_64BIT)
29b0f896
AM		 5330 {
5331 /* 64bit mode overwrites the 32bit absolute
5332 addressing by RIP relative addressing and
5333 absolute addressing is encoded by one of the
5334 redundant SIB forms. */
5335 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5336 i.sib.base = NO_BASE_REGISTER;
5337 i.sib.index = NO_INDEX_REGISTER;
fc225355 5338 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5339 ? disp32s : disp32);
20f0a1fc 5340 }
fc225355
L		 5341 else if ((flag_code == CODE_16BIT)
5342 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5343 {
5344 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5345 i.types[op] = disp16;
20f0a1fc
NC		 5346 }
5347 else
5348 {
5349 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5350 i.types[op] = disp32;
29b0f896
AM		 5351 }
5352 }
5353 else /* !i.base_reg && i.index_reg */
5354 {
db51cc60
L		 5355 if (i.index_reg->reg_num == RegEiz
5356 || i.index_reg->reg_num == RegRiz)
5357 i.sib.index = NO_INDEX_REGISTER;
5358 else
5359 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5360 i.sib.base = NO_BASE_REGISTER;
5361 i.sib.scale = i.log2_scale_factor;
5362 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5363 i.types[op].bitfield.disp8 = 0;
5364 i.types[op].bitfield.disp16 = 0;
5365 i.types[op].bitfield.disp64 = 0;
29b0f896 5366 if (flag_code != CODE_64BIT)
40fb9820
L		 5367 {
5368 /* Must be 32 bit */
5369 i.types[op].bitfield.disp32 = 1;
5370 i.types[op].bitfield.disp32s = 0;
5371 }
29b0f896 5372 else
40fb9820
L		 5373 {
5374 i.types[op].bitfield.disp32 = 0;
5375 i.types[op].bitfield.disp32s = 1;
5376 }
29b0f896 5377 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5378 i.rex |= REX_X;
29b0f896
AM		 5379 }
5380 }
5381 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5382 else if (i.base_reg->reg_num == RegRip ||
5383 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5384 {
5385 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5386 i.types[op].bitfield.disp8 = 0;
5387 i.types[op].bitfield.disp16 = 0;
5388 i.types[op].bitfield.disp32 = 0;
5389 i.types[op].bitfield.disp32s = 1;
5390 i.types[op].bitfield.disp64 = 0;
71903a11 5391 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5392 if (! i.disp_operands)
5393 fake_zero_displacement = 1;
29b0f896 5394 }
40fb9820 5395 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5396 {
5397 switch (i.base_reg->reg_num)
5398 {
5399 case 3: /* (%bx) */
5400 if (i.index_reg == 0)
5401 i.rm.regmem = 7;
5402 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5403 i.rm.regmem = i.index_reg->reg_num - 6;
5404 break;
5405 case 5: /* (%bp) */
5406 default_seg = &ss;
5407 if (i.index_reg == 0)
5408 {
5409 i.rm.regmem = 6;
40fb9820 5410 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5411 {
5412 /* fake (%bp) into 0(%bp) */
40fb9820 5413 i.types[op].bitfield.disp8 = 1;
252b5132 5414 fake_zero_displacement = 1;
29b0f896
AM		 5415 }
5416 }
5417 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5418 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5419 break;
5420 default: /* (%si) -> 4 or (%di) -> 5 */
5421 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5422 }
5423 i.rm.mode = mode_from_disp_size (i.types[op]);
5424 }
5425 else /* i.base_reg and 32/64 bit mode */
5426 {
5427 if (flag_code == CODE_64BIT
40fb9820
L		 5428 && operand_type_check (i.types[op], disp))
5429 {
5430 i386_operand_type temp;
0dfbf9d7 5431 operand_type_set (&temp, 0);
40fb9820
L		 5432 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5433 i.types[op] = temp;
5434 if (i.prefix[ADDR_PREFIX] == 0)
5435 i.types[op].bitfield.disp32s = 1;
5436 else
5437 i.types[op].bitfield.disp32 = 1;
5438 }
20f0a1fc 5439
29b0f896
AM		 5440 i.rm.regmem = i.base_reg->reg_num;
5441 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5442 i.rex |= REX_B;
29b0f896
AM		 5443 i.sib.base = i.base_reg->reg_num;
5444 /* x86-64 ignores REX prefix bit here to avoid decoder
5445 complications. */
5446 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5447 {
5448 default_seg = &ss;
5449 if (i.disp_operands == 0)
5450 {
5451 fake_zero_displacement = 1;
40fb9820 5452 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5453 }
5454 }
5455 else if (i.base_reg->reg_num == ESP_REG_NUM)
5456 {
5457 default_seg = &ss;
5458 }
5459 i.sib.scale = i.log2_scale_factor;
5460 if (i.index_reg == 0)
5461 {
5462 /* <disp>(%esp) becomes two byte modrm with no index
5463 register. We've already stored the code for esp
5464 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5465 Any base register besides %esp will not use the
5466 extra modrm byte. */
5467 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5468 }
5469 else
5470 {
db51cc60
L		 5471 if (i.index_reg->reg_num == RegEiz
5472 || i.index_reg->reg_num == RegRiz)
5473 i.sib.index = NO_INDEX_REGISTER;
5474 else
5475 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5476 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5477 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5478 i.rex |= REX_X;
29b0f896 5479 }
67a4f2b7
AO		 5480
5481 if (i.disp_operands
5482 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5483 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5484 i.rm.mode = 0;
5485 else
5486 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5487 }
252b5132 5488
29b0f896
AM		 5489 if (fake_zero_displacement)
5490 {
5491 /* Fakes a zero displacement assuming that i.types[op]
5492 holds the correct displacement size. */
5493 expressionS *exp;
5494
5495 assert (i.op[op].disps == 0);
5496 exp = &disp_expressions[i.disp_operands++];
5497 i.op[op].disps = exp;
5498 exp->X_op = O_constant;
5499 exp->X_add_number = 0;
5500 exp->X_add_symbol = (symbolS *) 0;
5501 exp->X_op_symbol = (symbolS *) 0;
5502 }
c0f3af97
L		 5503
5504 mem = op;
29b0f896 5505 }
c0f3af97
L		 5506 else
5507 mem = ~0;
252b5132 5508
29b0f896
AM		 5509 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5510 (if any) based on i.tm.extension_opcode. Again, we must be
5511 careful to make sure that segment/control/debug/test/MMX
5512 registers are coded into the i.rm.reg field. */
5513 if (i.reg_operands)
5514 {
99018f42
L		 5515 unsigned int op;
5516
85f10a01
MM		 5517 /* This has been precalculated for SSE5 instructions
5518 that have a DREX field earlier in process_drex. */
b5016f89
L		 5519 if (i.tm.opcode_modifier.drex
5520 || i.tm.opcode_modifier.drexv
5521 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5522 {
5523 op = i.drex.modrm_reg;
5524 i.rm.reg = i.op[op].regs->reg_num;
5525 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5526 i.rex |= REX_R;
5527 }
5528 else
5529 {
c0f3af97
L		 5530 unsigned int vex_reg = ~0;
5531
c0209578
L		 5532 for (op = 0; op < i.operands; op++)
5533 if (i.types[op].bitfield.reg8
5534 || i.types[op].bitfield.reg16
5535 || i.types[op].bitfield.reg32
5536 || i.types[op].bitfield.reg64
5537 || i.types[op].bitfield.regmmx
5538 || i.types[op].bitfield.regxmm
c0f3af97 5539 || i.types[op].bitfield.regymm
c0209578
L		 5540 || i.types[op].bitfield.sreg2
5541 || i.types[op].bitfield.sreg3
5542 || i.types[op].bitfield.control
5543 || i.types[op].bitfield.debug
5544 || i.types[op].bitfield.test)
5545 break;
5546
c0f3af97
L		 5547 if (vex_3_sources)
5548 op = dest;
5549 else if (i.tm.opcode_modifier.vexnds)
5550 {
5551 /* For instructions with VexNDS, the register-only
5552 source operand is encoded in VEX prefix. */
5553 assert (mem != (unsigned int) ~0);
5554
5555 if (op > mem)
5556 {
5557 vex_reg = op++;
5558 assert (op < i.operands);
5559 }
5560 else
5561 {
5562 vex_reg = op + 1;
5563 assert (vex_reg < i.operands);
5564 }
5565 }
5566 else if (i.tm.opcode_modifier.vexndd)
5567 {
5568 /* For instructions with VexNDD, there should be
5569 no memory operand and the register destination
5570 is encoded in VEX prefix. */
5571 assert (i.mem_operands == 0
5572 && (op + 2) == i.operands);
5573 vex_reg = op + 1;
5574 }
5575 else
5576 assert (op < i.operands);
5577
5578 if (vex_reg != (unsigned int) ~0)
5579 {
5580 assert (i.reg_operands == 2);
5581
5582 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
5583 & regxmm)
5584 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5585 &regymm))
5586 abort ();
5587 i.vex.register_specifier = i.op[vex_reg].regs;
5588 }
99018f42 5589
85f10a01
MM		 5590 /* If there is an extension opcode to put here, the
5591 register number must be put into the regmem field. */
c0209578
L		 5592 if (i.tm.extension_opcode != None)
5593 {
5594 i.rm.regmem = i.op[op].regs->reg_num;
5595 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5596 i.rex |= REX_B;
5597 }
5598 else
5599 {
5600 i.rm.reg = i.op[op].regs->reg_num;
5601 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5602 i.rex |= REX_R;
5603 }
85f10a01 5604 }
252b5132 5605
29b0f896
AM		 5606 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5607 must set it to 3 to indicate this is a register operand
5608 in the regmem field. */
5609 if (!i.mem_operands)
5610 i.rm.mode = 3;
5611 }
252b5132 5612
29b0f896 5613 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 5614 if (i.tm.extension_opcode != None
5615 && !(i.tm.opcode_modifier.drex
5616 || i.tm.opcode_modifier.drexv
5617 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 5618 i.rm.reg = i.tm.extension_opcode;
5619 }
5620 return default_seg;
5621}
252b5132 5622
29b0f896 5623static void
e3bb37b5 5624output_branch (void)
29b0f896
AM		 5625{
5626 char *p;
5627 int code16;
5628 int prefix;
5629 relax_substateT subtype;
5630 symbolS *sym;
5631 offsetT off;
5632
5633 code16 = 0;
5634 if (flag_code == CODE_16BIT)
5635 code16 = CODE16;
5636
5637 prefix = 0;
5638 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5639 {
29b0f896
AM		 5640 prefix = 1;
5641 i.prefixes -= 1;
5642 code16 ^= CODE16;
252b5132 5643 }
29b0f896
AM		 5644 /* Pentium4 branch hints. */
5645 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5646 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5647 {
29b0f896
AM		 5648 prefix++;
5649 i.prefixes--;
5650 }
5651 if (i.prefix[REX_PREFIX] != 0)
5652 {
5653 prefix++;
5654 i.prefixes--;
2f66722d
AM		 5655 }
5656
29b0f896
AM		 5657 if (i.prefixes != 0 && !intel_syntax)
5658 as_warn (_("skipping prefixes on this instruction"));
5659
5660 /* It's always a symbol; End frag & setup for relax.
5661 Make sure there is enough room in this frag for the largest
5662 instruction we may generate in md_convert_frag. This is 2
5663 bytes for the opcode and room for the prefix and largest
5664 displacement. */
5665 frag_grow (prefix + 2 + 4);
5666 /* Prefix and 1 opcode byte go in fr_fix. */
5667 p = frag_more (prefix + 1);
5668 if (i.prefix[DATA_PREFIX] != 0)
5669 *p++ = DATA_PREFIX_OPCODE;
5670 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5671 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5672 *p++ = i.prefix[SEG_PREFIX];
5673 if (i.prefix[REX_PREFIX] != 0)
5674 *p++ = i.prefix[REX_PREFIX];
5675 *p = i.tm.base_opcode;
5676
5677 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5678 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5679 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5680 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5681 else
5682 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5683 subtype |= code16;
3e73aa7c 5684
29b0f896
AM		 5685 sym = i.op[0].disps->X_add_symbol;
5686 off = i.op[0].disps->X_add_number;
3e73aa7c 5687
29b0f896
AM		 5688 if (i.op[0].disps->X_op != O_constant
5689 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5690 {
29b0f896
AM		 5691 /* Handle complex expressions. */
5692 sym = make_expr_symbol (i.op[0].disps);
5693 off = 0;
5694 }
3e73aa7c 5695
29b0f896
AM		 5696 /* 1 possible extra opcode + 4 byte displacement go in var part.
5697 Pass reloc in fr_var. */
5698 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5699}
3e73aa7c 5700
29b0f896 5701static void
e3bb37b5 5702output_jump (void)
29b0f896
AM		 5703{
5704 char *p;
5705 int size;
3e02c1cc 5706 fixS *fixP;
29b0f896 5707
40fb9820 5708 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5709 {
5710 /* This is a loop or jecxz type instruction. */
5711 size = 1;
5712 if (i.prefix[ADDR_PREFIX] != 0)
5713 {
5714 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5715 i.prefixes -= 1;
5716 }
5717 /* Pentium4 branch hints. */
5718 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5719 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5720 {
5721 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5722 i.prefixes--;
3e73aa7c
JH		 5723 }
5724 }
29b0f896
AM		 5725 else
5726 {
5727 int code16;
3e73aa7c 5728
29b0f896
AM		 5729 code16 = 0;
5730 if (flag_code == CODE_16BIT)
5731 code16 = CODE16;
3e73aa7c 5732
29b0f896
AM		 5733 if (i.prefix[DATA_PREFIX] != 0)
5734 {
5735 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5736 i.prefixes -= 1;
5737 code16 ^= CODE16;
5738 }
252b5132 5739
29b0f896
AM		 5740 size = 4;
5741 if (code16)
5742 size = 2;
5743 }
9fcc94b6 5744
29b0f896
AM		 5745 if (i.prefix[REX_PREFIX] != 0)
5746 {
5747 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5748 i.prefixes -= 1;
5749 }
252b5132 5750
29b0f896
AM		 5751 if (i.prefixes != 0 && !intel_syntax)
5752 as_warn (_("skipping prefixes on this instruction"));
e0890092 5753
29b0f896
AM		 5754 p = frag_more (1 + size);
5755 *p++ = i.tm.base_opcode;
e0890092 5756
3e02c1cc
AM		 5757 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5758 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5759
5760 /* All jumps handled here are signed, but don't use a signed limit
5761 check for 32 and 16 bit jumps as we want to allow wrap around at
5762 4G and 64k respectively. */
5763 if (size == 1)
5764 fixP->fx_signed = 1;
29b0f896 5765}
e0890092 5766
29b0f896 5767static void
e3bb37b5 5768output_interseg_jump (void)
29b0f896
AM		 5769{
5770 char *p;
5771 int size;
5772 int prefix;
5773 int code16;
252b5132 5774
29b0f896
AM		 5775 code16 = 0;
5776 if (flag_code == CODE_16BIT)
5777 code16 = CODE16;
a217f122 5778
29b0f896
AM		 5779 prefix = 0;
5780 if (i.prefix[DATA_PREFIX] != 0)
5781 {
5782 prefix = 1;
5783 i.prefixes -= 1;
5784 code16 ^= CODE16;
5785 }
5786 if (i.prefix[REX_PREFIX] != 0)
5787 {
5788 prefix++;
5789 i.prefixes -= 1;
5790 }
252b5132 5791
29b0f896
AM		 5792 size = 4;
5793 if (code16)
5794 size = 2;
252b5132 5795
29b0f896
AM		 5796 if (i.prefixes != 0 && !intel_syntax)
5797 as_warn (_("skipping prefixes on this instruction"));
252b5132 5798
29b0f896
AM		 5799 /* 1 opcode; 2 segment; offset */
5800 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5801
29b0f896
AM		 5802 if (i.prefix[DATA_PREFIX] != 0)
5803 *p++ = DATA_PREFIX_OPCODE;
252b5132 5804
29b0f896
AM		 5805 if (i.prefix[REX_PREFIX] != 0)
5806 *p++ = i.prefix[REX_PREFIX];
252b5132 5807
29b0f896
AM		 5808 *p++ = i.tm.base_opcode;
5809 if (i.op[1].imms->X_op == O_constant)
5810 {
5811 offsetT n = i.op[1].imms->X_add_number;
252b5132 5812
29b0f896
AM		 5813 if (size == 2
5814 && !fits_in_unsigned_word (n)
5815 && !fits_in_signed_word (n))
5816 {
5817 as_bad (_("16-bit jump out of range"));
5818 return;
5819 }
5820 md_number_to_chars (p, n, size);
5821 }
5822 else
5823 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5824 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5825 if (i.op[0].imms->X_op != O_constant)
5826 as_bad (_("can't handle non absolute segment in `%s'"),
5827 i.tm.name);
5828 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5829}
a217f122 5830
29b0f896 5831static void
e3bb37b5 5832output_insn (void)
29b0f896 5833{
2bbd9c25
JJ		 5834 fragS *insn_start_frag;
5835 offsetT insn_start_off;
5836
29b0f896
AM		 5837 /* Tie dwarf2 debug info to the address at the start of the insn.
5838 We can't do this after the insn has been output as the current
5839 frag may have been closed off. eg. by frag_var. */
5840 dwarf2_emit_insn (0);
5841
2bbd9c25
JJ		 5842 insn_start_frag = frag_now;
5843 insn_start_off = frag_now_fix ();
5844
29b0f896 5845 /* Output jumps. */
40fb9820 5846 if (i.tm.opcode_modifier.jump)
29b0f896 5847 output_branch ();
40fb9820
L		 5848 else if (i.tm.opcode_modifier.jumpbyte
5849 || i.tm.opcode_modifier.jumpdword)
29b0f896 5850 output_jump ();
40fb9820 5851 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5852 output_interseg_jump ();
5853 else
5854 {
5855 /* Output normal instructions here. */
5856 char *p;
5857 unsigned char *q;
47465058 5858 unsigned int j;
331d2d0d 5859 unsigned int prefix;
4dffcebc 5860
c0f3af97
L		 5861 /* Since the VEX prefix contains the implicit prefix, we don't
5862 need the explicit prefix. */
5863 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5864 {
c0f3af97 5865 switch (i.tm.opcode_length)
bc4bd9ab 5866 {
c0f3af97
L		 5867 case 3:
5868 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5869 {
c0f3af97
L		 5870 prefix = (i.tm.base_opcode >> 24) & 0xff;
5871 goto check_prefix;
5872 }
5873 break;
5874 case 2:
5875 if ((i.tm.base_opcode & 0xff0000) != 0)
5876 {
5877 prefix = (i.tm.base_opcode >> 16) & 0xff;
5878 if (i.tm.cpu_flags.bitfield.cpupadlock)
5879 {
4dffcebc 5880check_prefix:
c0f3af97
L		 5881 if (prefix != REPE_PREFIX_OPCODE
5882 || (i.prefix[LOCKREP_PREFIX]
5883 != REPE_PREFIX_OPCODE))
5884 add_prefix (prefix);
5885 }
5886 else
4dffcebc
L		 5887 add_prefix (prefix);
5888 }
c0f3af97
L		 5889 break;
5890 case 1:
5891 break;
5892 default:
5893 abort ();
bc4bd9ab 5894 }
c0f3af97
L		 5895
5896 /* The prefix bytes. */
5897 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5898 if (*q)
5899 FRAG_APPEND_1_CHAR (*q);
0f10071e 5900 }
252b5132 5901
c0f3af97
L		 5902 if (i.tm.opcode_modifier.vex)
5903 {
5904 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5905 if (*q)
5906 switch (j)
5907 {
5908 case REX_PREFIX:
5909 /* REX byte is encoded in VEX prefix. */
5910 break;
5911 case SEG_PREFIX:
5912 case ADDR_PREFIX:
5913 FRAG_APPEND_1_CHAR (*q);
5914 break;
5915 default:
5916 /* There should be no other prefixes for instructions
5917 with VEX prefix. */
5918 abort ();
5919 }
5920
5921 /* Now the VEX prefix. */
5922 p = frag_more (i.vex.length);
5923 for (j = 0; j < i.vex.length; j++)
5924 p[j] = i.vex.bytes[j];
5925 }
252b5132 5926
29b0f896 5927 /* Now the opcode; be careful about word order here! */
4dffcebc 5928 if (i.tm.opcode_length == 1)
29b0f896
AM		 5929 {
5930 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5931 }
5932 else
5933 {
4dffcebc 5934 switch (i.tm.opcode_length)
331d2d0d 5935 {
4dffcebc 5936 case 3:
331d2d0d
L		 5937 p = frag_more (3);
5938 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5939 break;
5940 case 2:
5941 p = frag_more (2);
5942 break;
5943 default:
5944 abort ();
5945 break;
331d2d0d 5946 }
0f10071e 5947
29b0f896
AM		 5948 /* Put out high byte first: can't use md_number_to_chars! */
5949 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5950 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5951
5952 /* On SSE5, encode the OC1 bit in the DREX field if this
5953 encoding has multiple formats. */
5954 if (i.tm.opcode_modifier.drex
5955 && i.tm.opcode_modifier.drexv
5956 && DREX_OC1 (i.tm.extension_opcode))
5957 *p |= DREX_OC1_MASK;
29b0f896 5958 }
3e73aa7c 5959
29b0f896 5960 /* Now the modrm byte and sib byte (if present). */
40fb9820 5961 if (i.tm.opcode_modifier.modrm)
29b0f896 5962 {
4a3523fa
L		 5963 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5964 | i.rm.reg << 3
5965 | i.rm.mode << 6));
29b0f896
AM		 5966 /* If i.rm.regmem == ESP (4)
5967 && i.rm.mode != (Register mode)
5968 && not 16 bit
5969 ==> need second modrm byte. */
5970 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5971 && i.rm.mode != 3
40fb9820 5972 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5973 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5974 | i.sib.index << 3
5975 | i.sib.scale << 6));
29b0f896 5976 }
3e73aa7c 5977
85f10a01
MM		 5978 /* Write the DREX byte if needed. */
5979 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5980 {
5981 p = frag_more (1);
5982 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5983
5984 /* Encode the OC0 bit if this encoding has multiple
5985 formats. */
5986 if ((i.tm.opcode_modifier.drex
5987 || i.tm.opcode_modifier.drexv)
5988 && DREX_OC0 (i.tm.extension_opcode))
5989 *p |= DREX_OC0_MASK;
5990 }
5991
29b0f896 5992 if (i.disp_operands)
2bbd9c25 5993 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5994
29b0f896 5995 if (i.imm_operands)
2bbd9c25 5996 output_imm (insn_start_frag, insn_start_off);
29b0f896 5997 }
252b5132 5998
29b0f896
AM		 5999#ifdef DEBUG386
6000 if (flag_debug)
6001 {
7b81dfbb 6002 pi ("" /*line*/, &i);
29b0f896
AM		 6003 }
6004#endif /* DEBUG386 */
6005}
252b5132 6006
e205caa7
L		 6007/* Return the size of the displacement operand N. */
6008
6009static int
6010disp_size (unsigned int n)
6011{
6012 int size = 4;
40fb9820
L		 6013 if (i.types[n].bitfield.disp64)
6014 size = 8;
6015 else if (i.types[n].bitfield.disp8)
6016 size = 1;
6017 else if (i.types[n].bitfield.disp16)
6018 size = 2;
e205caa7
L		 6019 return size;
6020}
6021
6022/* Return the size of the immediate operand N. */
6023
6024static int
6025imm_size (unsigned int n)
6026{
6027 int size = 4;
40fb9820
L		 6028 if (i.types[n].bitfield.imm64)
6029 size = 8;
6030 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6031 size = 1;
6032 else if (i.types[n].bitfield.imm16)
6033 size = 2;
e205caa7
L		 6034 return size;
6035}
6036
29b0f896 6037static void
64e74474 6038output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6039{
6040 char *p;
6041 unsigned int n;
252b5132 6042
29b0f896
AM		 6043 for (n = 0; n < i.operands; n++)
6044 {
40fb9820 6045 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6046 {
6047 if (i.op[n].disps->X_op == O_constant)
6048 {
e205caa7 6049 int size = disp_size (n);
29b0f896 6050 offsetT val;
252b5132 6051
29b0f896
AM		 6052 val = offset_in_range (i.op[n].disps->X_add_number,
6053 size);
6054 p = frag_more (size);
6055 md_number_to_chars (p, val, size);
6056 }
6057 else
6058 {
f86103b7 6059 enum bfd_reloc_code_real reloc_type;
e205caa7 6060 int size = disp_size (n);
40fb9820 6061 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6062 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6063
e205caa7 6064 /* We can't have 8 bit displacement here. */
40fb9820 6065 assert (!i.types[n].bitfield.disp8);
e205caa7 6066
29b0f896
AM		 6067 /* The PC relative address is computed relative
6068 to the instruction boundary, so in case immediate
6069 fields follows, we need to adjust the value. */
6070 if (pcrel && i.imm_operands)
6071 {
29b0f896 6072 unsigned int n1;
e205caa7 6073 int sz = 0;
252b5132 6074
29b0f896 6075 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6076 if (operand_type_check (i.types[n1], imm))
252b5132 6077 {
e205caa7
L		 6078 /* Only one immediate is allowed for PC
6079 relative address. */
6080 assert (sz == 0);
6081 sz = imm_size (n1);
6082 i.op[n].disps->X_add_number -= sz;
252b5132 6083 }
29b0f896 6084 /* We should find the immediate. */
e205caa7 6085 assert (sz != 0);
29b0f896 6086 }
520dc8e8 6087
29b0f896 6088 p = frag_more (size);
2bbd9c25 6089 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6090 if (GOT_symbol
2bbd9c25 6091 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6092 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6093 || reloc_type == BFD_RELOC_X86_64_32S
6094 || (reloc_type == BFD_RELOC_64
6095 && object_64bit))
d6ab8113
JB		 6096 && (i.op[n].disps->X_op == O_symbol
6097 || (i.op[n].disps->X_op == O_add
6098 && ((symbol_get_value_expression
6099 (i.op[n].disps->X_op_symbol)->X_op)
6100 == O_subtract))))
6101 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6102 {
6103 offsetT add;
6104
6105 if (insn_start_frag == frag_now)
6106 add = (p - frag_now->fr_literal) - insn_start_off;
6107 else
6108 {
6109 fragS *fr;
6110
6111 add = insn_start_frag->fr_fix - insn_start_off;
6112 for (fr = insn_start_frag->fr_next;
6113 fr && fr != frag_now; fr = fr->fr_next)
6114 add += fr->fr_fix;
6115 add += p - frag_now->fr_literal;
6116 }
6117
4fa24527 6118 if (!object_64bit)
7b81dfbb
AJ		 6119 {
6120 reloc_type = BFD_RELOC_386_GOTPC;
6121 i.op[n].imms->X_add_number += add;
6122 }
6123 else if (reloc_type == BFD_RELOC_64)
6124 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6125 else
7b81dfbb
AJ		 6126 /* Don't do the adjustment for x86-64, as there
6127 the pcrel addressing is relative to the _next_
6128 insn, and that is taken care of in other code. */
d6ab8113 6129 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6130 }
062cd5e7 6131 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6132 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6133 }
6134 }
6135 }
6136}
252b5132 6137
29b0f896 6138static void
64e74474 6139output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6140{
6141 char *p;
6142 unsigned int n;
252b5132 6143
29b0f896
AM		 6144 for (n = 0; n < i.operands; n++)
6145 {
40fb9820 6146 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6147 {
6148 if (i.op[n].imms->X_op == O_constant)
6149 {
e205caa7 6150 int size = imm_size (n);
29b0f896 6151 offsetT val;
b4cac588 6152
29b0f896
AM		 6153 val = offset_in_range (i.op[n].imms->X_add_number,
6154 size);
6155 p = frag_more (size);
6156 md_number_to_chars (p, val, size);
6157 }
6158 else
6159 {
6160 /* Not absolute_section.
6161 Need a 32-bit fixup (don't support 8bit
6162 non-absolute imms). Try to support other
6163 sizes ... */
f86103b7 6164 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6165 int size = imm_size (n);
6166 int sign;
29b0f896 6167
40fb9820 6168 if (i.types[n].bitfield.imm32s
a7d61044 6169 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6170 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6171 sign = 1;
e205caa7
L		 6172 else
6173 sign = 0;
520dc8e8 6174
29b0f896
AM		 6175 p = frag_more (size);
6176 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6177
2bbd9c25
JJ		 6178 /* This is tough to explain. We end up with this one if we
6179 * have operands that look like
6180 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6181 * obtain the absolute address of the GOT, and it is strongly
6182 * preferable from a performance point of view to avoid using
6183 * a runtime relocation for this. The actual sequence of
6184 * instructions often look something like:
6185 *
6186 * call .L66
6187 * .L66:
6188 * popl %ebx
6189 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6190 *
6191 * The call and pop essentially return the absolute address
6192 * of the label .L66 and store it in %ebx. The linker itself
6193 * will ultimately change the first operand of the addl so
6194 * that %ebx points to the GOT, but to keep things simple, the
6195 * .o file must have this operand set so that it generates not
6196 * the absolute address of .L66, but the absolute address of
6197 * itself. This allows the linker itself simply treat a GOTPC
6198 * relocation as asking for a pcrel offset to the GOT to be
6199 * added in, and the addend of the relocation is stored in the
6200 * operand field for the instruction itself.
6201 *
6202 * Our job here is to fix the operand so that it would add
6203 * the correct offset so that %ebx would point to itself. The
6204 * thing that is tricky is that .-.L66 will point to the
6205 * beginning of the instruction, so we need to further modify
6206 * the operand so that it will point to itself. There are
6207 * other cases where you have something like:
6208 *
6209 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6210 *
6211 * and here no correction would be required. Internally in
6212 * the assembler we treat operands of this form as not being
6213 * pcrel since the '.' is explicitly mentioned, and I wonder
6214 * whether it would simplify matters to do it this way. Who
6215 * knows. In earlier versions of the PIC patches, the
6216 * pcrel_adjust field was used to store the correction, but
6217 * since the expression is not pcrel, I felt it would be
6218 * confusing to do it this way. */
6219
d6ab8113 6220 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6221 || reloc_type == BFD_RELOC_X86_64_32S
6222 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6223 && GOT_symbol
6224 && GOT_symbol == i.op[n].imms->X_add_symbol
6225 && (i.op[n].imms->X_op == O_symbol
6226 || (i.op[n].imms->X_op == O_add
6227 && ((symbol_get_value_expression
6228 (i.op[n].imms->X_op_symbol)->X_op)
6229 == O_subtract))))
6230 {
2bbd9c25
JJ		 6231 offsetT add;
6232
6233 if (insn_start_frag == frag_now)
6234 add = (p - frag_now->fr_literal) - insn_start_off;
6235 else
6236 {
6237 fragS *fr;
6238
6239 add = insn_start_frag->fr_fix - insn_start_off;
6240 for (fr = insn_start_frag->fr_next;
6241 fr && fr != frag_now; fr = fr->fr_next)
6242 add += fr->fr_fix;
6243 add += p - frag_now->fr_literal;
6244 }
6245
4fa24527 6246 if (!object_64bit)
d6ab8113 6247 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6248 else if (size == 4)
d6ab8113 6249 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6250 else if (size == 8)
6251 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6252 i.op[n].imms->X_add_number += add;
29b0f896 6253 }
29b0f896
AM		 6254 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6255 i.op[n].imms, 0, reloc_type);
6256 }
6257 }
6258 }
252b5132
RH		 6259}
6260\f
d182319b
JB		 6261/* x86_cons_fix_new is called via the expression parsing code when a
6262 reloc is needed. We use this hook to get the correct .got reloc. */
6263static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6264static int cons_sign = -1;
6265
6266void
e3bb37b5 6267x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6268 expressionS *exp)
d182319b
JB		 6269{
6270 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6271
6272 got_reloc = NO_RELOC;
6273
6274#ifdef TE_PE
6275 if (exp->X_op == O_secrel)
6276 {
6277 exp->X_op = O_symbol;
6278 r = BFD_RELOC_32_SECREL;
6279 }
6280#endif
6281
6282 fix_new_exp (frag, off, len, exp, 0, r);
6283}
6284
718ddfc0
JB		 6285#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6286# define lex_got(reloc, adjust, types) NULL
6287#else
f3c180ae
AM		 6288/* Parse operands of the form
6289 <symbol>@GOTOFF+<nnn>
6290 and similar .plt or .got references.
6291
6292 If we find one, set up the correct relocation in RELOC and copy the
6293 input string, minus the `@GOTOFF' into a malloc'd buffer for
6294 parsing by the calling routine. Return this buffer, and if ADJUST
6295 is non-null set it to the length of the string we removed from the
6296 input line. Otherwise return NULL. */
6297static char *
3956db08 6298lex_got (enum bfd_reloc_code_real *reloc,
64e74474 6299 int *adjust,
40fb9820 6300 i386_operand_type *types)
f3c180ae 6301{
7b81dfbb
AJ		 6302 /* Some of the relocations depend on the size of what field is to
6303 be relocated. But in our callers i386_immediate and i386_displacement
6304 we don't yet know the operand size (this will be set by insn
6305 matching). Hence we record the word32 relocation here,
6306 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6307 static const struct {
6308 const char *str;
4fa24527 6309 const enum bfd_reloc_code_real rel[2];
40fb9820 6310 const i386_operand_type types64;
f3c180ae 6311 } gotrel[] = {
4eed87de
AM		 6312 { "PLTOFF", { 0,
6313 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6314 OPERAND_TYPE_IMM64 },
4eed87de
AM		 6315 { "PLT", { BFD_RELOC_386_PLT32,
6316 BFD_RELOC_X86_64_PLT32 },
40fb9820 6317 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6318 { "GOTPLT", { 0,
6319 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6320 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6321 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
6322 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6323 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6324 { "GOTPCREL", { 0,
6325 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6326 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6327 { "TLSGD", { BFD_RELOC_386_TLS_GD,
6328 BFD_RELOC_X86_64_TLSGD },
40fb9820 6329 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6330 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
6331 0 },
40fb9820 6332 OPERAND_TYPE_NONE },
4eed87de
AM		 6333 { "TLSLD", { 0,
6334 BFD_RELOC_X86_64_TLSLD },
40fb9820 6335 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6336 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
6337 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6338 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6339 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
6340 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6341 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 6342 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
6343 0 },
40fb9820 6344 OPERAND_TYPE_NONE },
4eed87de
AM		 6345 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
6346 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 6347
6348 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 6349 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
6350 0 },
40fb9820 6351 OPERAND_TYPE_NONE },
4eed87de
AM		 6352 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
6353 0 },
40fb9820 6354 OPERAND_TYPE_NONE },
4eed87de
AM		 6355 { "GOT", { BFD_RELOC_386_GOT32,
6356 BFD_RELOC_X86_64_GOT32 },
40fb9820 6357 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 6358 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
6359 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6360 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6361 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
6362 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6363 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6364 };
6365 char *cp;
6366 unsigned int j;
6367
718ddfc0
JB		 6368 if (!IS_ELF)
6369 return NULL;
6370
f3c180ae 6371 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6372 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6373 return NULL;
6374
47465058 6375 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 6376 {
6377 int len;
6378
6379 len = strlen (gotrel[j].str);
28f81592 6380 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6381 {
4fa24527 6382 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6383 {
28f81592
AM		 6384 int first, second;
6385 char *tmpbuf, *past_reloc;
f3c180ae 6386
4fa24527 6387 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 6388 if (adjust)
6389 *adjust = len;
f3c180ae 6390
3956db08
JB		 6391 if (types)
6392 {
6393 if (flag_code != CODE_64BIT)
40fb9820
L		 6394 {
6395 types->bitfield.imm32 = 1;
6396 types->bitfield.disp32 = 1;
6397 }
3956db08
JB		 6398 else
6399 *types = gotrel[j].types64;
6400 }
6401
f3c180ae
AM		 6402 if (GOT_symbol == NULL)
6403 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6404
28f81592 6405 /* The length of the first part of our input line. */
f3c180ae 6406 first = cp - input_line_pointer;
28f81592
AM		 6407
6408 /* The second part goes from after the reloc token until
67c11a9b 6409 (and including) an end_of_line char or comma. */
28f81592 6410 past_reloc = cp + 1 + len;
67c11a9b
AM		 6411 cp = past_reloc;
6412 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6413 ++cp;
6414 second = cp + 1 - past_reloc;
28f81592
AM		 6415
6416 /* Allocate and copy string. The trailing NUL shouldn't
6417 be necessary, but be safe. */
6418 tmpbuf = xmalloc (first + second + 2);
f3c180ae 6419 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6420 if (second != 0 && *past_reloc != ' ')
6421 /* Replace the relocation token with ' ', so that
6422 errors like foo@GOTOFF1 will be detected. */
6423 tmpbuf[first++] = ' ';
6424 memcpy (tmpbuf + first, past_reloc, second);
6425 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6426 return tmpbuf;
6427 }
6428
4fa24527
JB		 6429 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6430 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6431 return NULL;
6432 }
6433 }
6434
6435 /* Might be a symbol version string. Don't as_bad here. */
6436 return NULL;
6437}
6438
f3c180ae 6439void
e3bb37b5 6440x86_cons (expressionS *exp, int size)
f3c180ae 6441{
4fa24527 6442 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6443 {
6444 /* Handle @GOTOFF and the like in an expression. */
6445 char *save;
6446 char *gotfree_input_line;
6447 int adjust;
6448
6449 save = input_line_pointer;
3956db08 6450 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6451 if (gotfree_input_line)
6452 input_line_pointer = gotfree_input_line;
6453
6454 expression (exp);
6455
6456 if (gotfree_input_line)
6457 {
6458 /* expression () has merrily parsed up to the end of line,
6459 or a comma - in the wrong buffer. Transfer how far
6460 input_line_pointer has moved to the right buffer. */
6461 input_line_pointer = (save
6462 + (input_line_pointer - gotfree_input_line)
6463 + adjust);
6464 free (gotfree_input_line);
3992d3b7
AM		 6465 if (exp->X_op == O_constant
6466 || exp->X_op == O_absent
6467 || exp->X_op == O_illegal
6468 || exp->X_op == O_register
6469 || exp->X_op == O_big)
6470 {
6471 char c = *input_line_pointer;
6472 *input_line_pointer = 0;
6473 as_bad (_("missing or invalid expression `%s'"), save);
6474 *input_line_pointer = c;
6475 }
f3c180ae
AM		 6476 }
6477 }
6478 else
6479 expression (exp);
6480}
6481#endif
6482
d182319b 6483static void signed_cons (int size)
6482c264 6484{
d182319b
JB		 6485 if (flag_code == CODE_64BIT)
6486 cons_sign = 1;
6487 cons (size);
6488 cons_sign = -1;
6482c264
NC		 6489}
6490
d182319b 6491#ifdef TE_PE
6482c264
NC		 6492static void
6493pe_directive_secrel (dummy)
6494 int dummy ATTRIBUTE_UNUSED;
6495{
6496 expressionS exp;
6497
6498 do
6499 {
6500 expression (&exp);
6501 if (exp.X_op == O_symbol)
6502 exp.X_op = O_secrel;
6503
6504 emit_expr (&exp, 4);
6505 }
6506 while (*input_line_pointer++ == ',');
6507
6508 input_line_pointer--;
6509 demand_empty_rest_of_line ();
6510}
6482c264
NC		 6511#endif
6512
252b5132 6513static int
70e41ade 6514i386_immediate (char *imm_start)
252b5132
RH		 6515{
6516 char *save_input_line_pointer;
f3c180ae 6517 char *gotfree_input_line;
252b5132 6518 segT exp_seg = 0;
47926f60 6519 expressionS *exp;
40fb9820
L		 6520 i386_operand_type types;
6521
0dfbf9d7 6522 operand_type_set (&types, ~0);
252b5132
RH		 6523
6524 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6525 {
31b2323c
L		 6526 as_bad (_("at most %d immediate operands are allowed"),
6527 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6528 return 0;
6529 }
6530
6531 exp = &im_expressions[i.imm_operands++];
520dc8e8 6532 i.op[this_operand].imms = exp;
252b5132
RH		 6533
6534 if (is_space_char (*imm_start))
6535 ++imm_start;
6536
6537 save_input_line_pointer = input_line_pointer;
6538 input_line_pointer = imm_start;
6539
3956db08 6540 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6541 if (gotfree_input_line)
6542 input_line_pointer = gotfree_input_line;
252b5132
RH		 6543
6544 exp_seg = expression (exp);
6545
83183c0c 6546 SKIP_WHITESPACE ();
252b5132 6547 if (*input_line_pointer)
f3c180ae 6548 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6549
6550 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 6551 if (gotfree_input_line)
6552 free (gotfree_input_line);
252b5132 6553
3992d3b7
AM		 6554 if (exp->X_op == O_absent
6555 || exp->X_op == O_illegal
6556 || exp->X_op == O_big
6557 || (gotfree_input_line
6558 && (exp->X_op == O_constant
6559 || exp->X_op == O_register)))
252b5132 6560 {
3992d3b7 6561 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 6562 imm_start);
3992d3b7 6563 return 0;
252b5132 6564 }
3e73aa7c 6565 else if (exp->X_op == O_constant)
252b5132 6566 {
47926f60 6567 /* Size it properly later. */
40fb9820 6568 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6569 /* If BFD64, sign extend val. */
4eed87de
AM		 6570 if (!use_rela_relocations
6571 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6572 exp->X_add_number
6573 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6574 }
4c63da97 6575#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6576 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6577 && exp_seg != absolute_section
47926f60 6578 && exp_seg != text_section
24eab124
AM		 6579 && exp_seg != data_section
6580 && exp_seg != bss_section
6581 && exp_seg != undefined_section
f86103b7 6582 && !bfd_is_com_section (exp_seg))
252b5132 6583 {
d0b47220 6584 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6585 return 0;
6586 }
6587#endif
bb8f5920
L		 6588 else if (!intel_syntax && exp->X_op == O_register)
6589 {
6590 as_bad (_("illegal immediate register operand %s"), imm_start);
6591 return 0;
6592 }
252b5132
RH		 6593 else
6594 {
6595 /* This is an address. The size of the address will be
24eab124 6596 determined later, depending on destination register,
3e73aa7c 6597 suffix, or the default for the section. */
40fb9820
L		 6598 i.types[this_operand].bitfield.imm8 = 1;
6599 i.types[this_operand].bitfield.imm16 = 1;
6600 i.types[this_operand].bitfield.imm32 = 1;
6601 i.types[this_operand].bitfield.imm32s = 1;
6602 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6603 i.types[this_operand] = operand_type_and (i.types[this_operand],
6604 types);
252b5132
RH		 6605 }
6606
6607 return 1;
6608}
6609
551c1ca1 6610static char *
e3bb37b5 6611i386_scale (char *scale)
252b5132 6612{
551c1ca1
AM		 6613 offsetT val;
6614 char *save = input_line_pointer;
252b5132 6615
551c1ca1
AM		 6616 input_line_pointer = scale;
6617 val = get_absolute_expression ();
6618
6619 switch (val)
252b5132 6620 {
551c1ca1 6621 case 1:
252b5132
RH		 6622 i.log2_scale_factor = 0;
6623 break;
551c1ca1 6624 case 2:
252b5132
RH		 6625 i.log2_scale_factor = 1;
6626 break;
551c1ca1 6627 case 4:
252b5132
RH		 6628 i.log2_scale_factor = 2;
6629 break;
551c1ca1 6630 case 8:
252b5132
RH		 6631 i.log2_scale_factor = 3;
6632 break;
6633 default:
a724f0f4
JB		 6634 {
6635 char sep = *input_line_pointer;
6636
6637 *input_line_pointer = '\0';
6638 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6639 scale);
6640 *input_line_pointer = sep;
6641 input_line_pointer = save;
6642 return NULL;
6643 }
252b5132 6644 }
29b0f896 6645 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6646 {
6647 as_warn (_("scale factor of %d without an index register"),
24eab124 6648 1 << i.log2_scale_factor);
252b5132 6649 i.log2_scale_factor = 0;
252b5132 6650 }
551c1ca1
AM		 6651 scale = input_line_pointer;
6652 input_line_pointer = save;
6653 return scale;
252b5132
RH		 6654}
6655
252b5132 6656static int
e3bb37b5 6657i386_displacement (char *disp_start, char *disp_end)
252b5132 6658{
29b0f896 6659 expressionS *exp;
252b5132
RH		 6660 segT exp_seg = 0;
6661 char *save_input_line_pointer;
f3c180ae 6662 char *gotfree_input_line;
40fb9820
L		 6663 int override;
6664 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6665 int ret;
252b5132 6666
31b2323c
L		 6667 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6668 {
6669 as_bad (_("at most %d displacement operands are allowed"),
6670 MAX_MEMORY_OPERANDS);
6671 return 0;
6672 }
6673
0dfbf9d7 6674 operand_type_set (&bigdisp, 0);
40fb9820
L		 6675 if ((i.types[this_operand].bitfield.jumpabsolute)
6676 || (!current_templates->start->opcode_modifier.jump
6677 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6678 {
40fb9820 6679 bigdisp.bitfield.disp32 = 1;
e05278af 6680 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6681 if (flag_code == CODE_64BIT)
6682 {
6683 if (!override)
6684 {
6685 bigdisp.bitfield.disp32s = 1;
6686 bigdisp.bitfield.disp64 = 1;
6687 }
6688 }
6689 else if ((flag_code == CODE_16BIT) ^ override)
6690 {
6691 bigdisp.bitfield.disp32 = 0;
6692 bigdisp.bitfield.disp16 = 1;
6693 }
e05278af
JB		 6694 }
6695 else
6696 {
6697 /* For PC-relative branches, the width of the displacement
6698 is dependent upon data size, not address size. */
e05278af 6699 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6700 if (flag_code == CODE_64BIT)
6701 {
6702 if (override || i.suffix == WORD_MNEM_SUFFIX)
6703 bigdisp.bitfield.disp16 = 1;
6704 else
6705 {
6706 bigdisp.bitfield.disp32 = 1;
6707 bigdisp.bitfield.disp32s = 1;
6708 }
6709 }
6710 else
e05278af
JB		 6711 {
6712 if (!override)
6713 override = (i.suffix == (flag_code != CODE_16BIT
6714 ? WORD_MNEM_SUFFIX
6715 : LONG_MNEM_SUFFIX));
40fb9820
L		 6716 bigdisp.bitfield.disp32 = 1;
6717 if ((flag_code == CODE_16BIT) ^ override)
6718 {
6719 bigdisp.bitfield.disp32 = 0;
6720 bigdisp.bitfield.disp16 = 1;
6721 }
e05278af 6722 }
e05278af 6723 }
c6fb90c8
L		 6724 i.types[this_operand] = operand_type_or (i.types[this_operand],
6725 bigdisp);
252b5132
RH		 6726
6727 exp = &disp_expressions[i.disp_operands];
520dc8e8 6728 i.op[this_operand].disps = exp;
252b5132
RH		 6729 i.disp_operands++;
6730 save_input_line_pointer = input_line_pointer;
6731 input_line_pointer = disp_start;
6732 END_STRING_AND_SAVE (disp_end);
6733
6734#ifndef GCC_ASM_O_HACK
6735#define GCC_ASM_O_HACK 0
6736#endif
6737#if GCC_ASM_O_HACK
6738 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6739 if (i.types[this_operand].bitfield.baseIndex
24eab124 6740 && displacement_string_end[-1] == '+')
252b5132
RH		 6741 {
6742 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6743 constraint within gcc asm statements.
6744 For instance:
6745
6746 #define _set_tssldt_desc(n,addr,limit,type) \
6747 __asm__ __volatile__ ( \
6748 "movw %w2,%0\n\t" \
6749 "movw %w1,2+%0\n\t" \
6750 "rorl $16,%1\n\t" \
6751 "movb %b1,4+%0\n\t" \
6752 "movb %4,5+%0\n\t" \
6753 "movb $0,6+%0\n\t" \
6754 "movb %h1,7+%0\n\t" \
6755 "rorl $16,%1" \
6756 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6757
6758 This works great except that the output assembler ends
6759 up looking a bit weird if it turns out that there is
6760 no offset. You end up producing code that looks like:
6761
6762 #APP
6763 movw $235,(%eax)
6764 movw %dx,2+(%eax)
6765 rorl $16,%edx
6766 movb %dl,4+(%eax)
6767 movb $137,5+(%eax)
6768 movb $0,6+(%eax)
6769 movb %dh,7+(%eax)
6770 rorl $16,%edx
6771 #NO_APP
6772
47926f60 6773 So here we provide the missing zero. */
24eab124
AM		 6774
6775 *displacement_string_end = '0';
252b5132
RH		 6776 }
6777#endif
3956db08 6778 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6779 if (gotfree_input_line)
6780 input_line_pointer = gotfree_input_line;
252b5132 6781
24eab124 6782 exp_seg = expression (exp);
252b5132 6783
636c26b0
AM		 6784 SKIP_WHITESPACE ();
6785 if (*input_line_pointer)
6786 as_bad (_("junk `%s' after expression"), input_line_pointer);
6787#if GCC_ASM_O_HACK
6788 RESTORE_END_STRING (disp_end + 1);
6789#endif
636c26b0 6790 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 6791 if (gotfree_input_line)
6792 free (gotfree_input_line);
3992d3b7 6793 ret = 1;
636c26b0 6794
24eab124
AM		 6795 /* We do this to make sure that the section symbol is in
6796 the symbol table. We will ultimately change the relocation
47926f60 6797 to be relative to the beginning of the section. */
1ae12ab7 6798 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6799 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6800 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6801 {
636c26b0 6802 if (exp->X_op != O_symbol)
3992d3b7 6803 goto inv_disp;
636c26b0 6804
e5cb08ac 6805 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6806 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6807 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6808 exp->X_op = O_subtract;
6809 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6810 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6811 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6812 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6813 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6814 else
29b0f896 6815 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6816 }
252b5132 6817
3992d3b7
AM		 6818 else if (exp->X_op == O_absent
6819 || exp->X_op == O_illegal
6820 || exp->X_op == O_big
6821 || (gotfree_input_line
6822 && (exp->X_op == O_constant
6823 || exp->X_op == O_register)))
2daf4fd8 6824 {
3992d3b7
AM		 6825 inv_disp:
6826 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6827 disp_start);
3992d3b7 6828 ret = 0;
2daf4fd8
AM		 6829 }
6830
4c63da97 6831#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6832 else if (exp->X_op != O_constant
6833 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6834 && exp_seg != absolute_section
6835 && exp_seg != text_section
6836 && exp_seg != data_section
6837 && exp_seg != bss_section
6838 && exp_seg != undefined_section
6839 && !bfd_is_com_section (exp_seg))
24eab124 6840 {
d0b47220 6841 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6842 ret = 0;
24eab124 6843 }
252b5132 6844#endif
3956db08 6845
3992d3b7
AM		 6846 RESTORE_END_STRING (disp_end);
6847
40fb9820
L		 6848 /* Check if this is a displacement only operand. */
6849 bigdisp = i.types[this_operand];
6850 bigdisp.bitfield.disp8 = 0;
6851 bigdisp.bitfield.disp16 = 0;
6852 bigdisp.bitfield.disp32 = 0;
6853 bigdisp.bitfield.disp32s = 0;
6854 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6855 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6856 i.types[this_operand] = operand_type_and (i.types[this_operand],
6857 types);
3956db08 6858
3992d3b7 6859 return ret;
252b5132
RH		 6860}
6861
eecb386c 6862/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6863 Return 1 on success, 0 on a failure. */
6864
252b5132 6865static int
e3bb37b5 6866i386_index_check (const char *operand_string)
252b5132 6867{
3e73aa7c 6868 int ok;
24eab124 6869#if INFER_ADDR_PREFIX
eecb386c
AM		 6870 int fudged = 0;
6871
24eab124
AM		 6872 tryprefix:
6873#endif
3e73aa7c 6874 ok = 1;
75178d9d 6875 if (flag_code == CODE_64BIT)
64e74474 6876 {
64e74474 6877 if ((i.base_reg
40fb9820
L		 6878 && ((i.prefix[ADDR_PREFIX] == 0
6879 && !i.base_reg->reg_type.bitfield.reg64)
6880 || (i.prefix[ADDR_PREFIX]
6881 && !i.base_reg->reg_type.bitfield.reg32))
6882 && (i.index_reg
9a04903e
JB		 6883 || i.base_reg->reg_num !=
6884 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6885 || (i.index_reg
40fb9820
L		 6886 && (!i.index_reg->reg_type.bitfield.baseindex
6887 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6888 && i.index_reg->reg_num != RegRiz
6889 && !i.index_reg->reg_type.bitfield.reg64
6890 )
40fb9820 6891 || (i.prefix[ADDR_PREFIX]
db51cc60 6892 && i.index_reg->reg_num != RegEiz
40fb9820 6893 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6894 ok = 0;
3e73aa7c
JH		 6895 }
6896 else
6897 {
6898 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6899 {
6900 /* 16bit checks. */
6901 if ((i.base_reg
40fb9820
L		 6902 && (!i.base_reg->reg_type.bitfield.reg16
6903 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6904 || (i.index_reg
40fb9820
L		 6905 && (!i.index_reg->reg_type.bitfield.reg16
6906 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6907 || !(i.base_reg
6908 && i.base_reg->reg_num < 6
6909 && i.index_reg->reg_num >= 6
6910 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6911 ok = 0;
6912 }
6913 else
e5cb08ac 6914 {
3e73aa7c
JH		 6915 /* 32bit checks. */
6916 if ((i.base_reg
40fb9820 6917 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6918 || (i.index_reg
db51cc60
L		 6919 && ((!i.index_reg->reg_type.bitfield.reg32
6920 && i.index_reg->reg_num != RegEiz)
40fb9820 6921 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6922 ok = 0;
3e73aa7c
JH		 6923 }
6924 }
6925 if (!ok)
24eab124
AM		 6926 {
6927#if INFER_ADDR_PREFIX
20f0a1fc 6928 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 6929 {
6930 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6931 i.prefixes += 1;
b23bac36
AM		 6932 /* Change the size of any displacement too. At most one of
6933 Disp16 or Disp32 is set.
6934 FIXME. There doesn't seem to be any real need for separate
6935 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6936 Removing them would probably clean up the code quite a lot. */
4eed87de 6937 if (flag_code != CODE_64BIT
40fb9820
L		 6938 && (i.types[this_operand].bitfield.disp16
6939 || i.types[this_operand].bitfield.disp32))
6940 i.types[this_operand]
c6fb90c8 6941 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6942 fudged = 1;
24eab124
AM		 6943 goto tryprefix;
6944 }
eecb386c
AM		 6945 if (fudged)
6946 as_bad (_("`%s' is not a valid base/index expression"),
6947 operand_string);
6948 else
c388dee8 6949#endif
eecb386c
AM		 6950 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6951 operand_string,
3e73aa7c 6952 flag_code_names[flag_code]);
24eab124 6953 }
20f0a1fc 6954 return ok;
24eab124 6955}
252b5132 6956
252b5132 6957/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 6958 on error. */
252b5132 6959
252b5132 6960static int
a7619375 6961i386_att_operand (char *operand_string)
252b5132 6962{
af6bdddf
AM		 6963 const reg_entry *r;
6964 char *end_op;
24eab124 6965 char *op_string = operand_string;
252b5132 6966
24eab124 6967 if (is_space_char (*op_string))
252b5132
RH		 6968 ++op_string;
6969
24eab124 6970 /* We check for an absolute prefix (differentiating,
47926f60 6971 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6972 if (*op_string == ABSOLUTE_PREFIX)
6973 {
6974 ++op_string;
6975 if (is_space_char (*op_string))
6976 ++op_string;
40fb9820 6977 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6978 }
252b5132 6979
47926f60 6980 /* Check if operand is a register. */
4d1bb795 6981 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6982 {
40fb9820
L		 6983 i386_operand_type temp;
6984
24eab124
AM		 6985 /* Check for a segment override by searching for ':' after a
6986 segment register. */
6987 op_string = end_op;
6988 if (is_space_char (*op_string))
6989 ++op_string;
40fb9820
L		 6990 if (*op_string == ':'
6991 && (r->reg_type.bitfield.sreg2
6992 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6993 {
6994 switch (r->reg_num)
6995 {
6996 case 0:
6997 i.seg[i.mem_operands] = &es;
6998 break;
6999 case 1:
7000 i.seg[i.mem_operands] = &cs;
7001 break;
7002 case 2:
7003 i.seg[i.mem_operands] = &ss;
7004 break;
7005 case 3:
7006 i.seg[i.mem_operands] = &ds;
7007 break;
7008 case 4:
7009 i.seg[i.mem_operands] = &fs;
7010 break;
7011 case 5:
7012 i.seg[i.mem_operands] = &gs;
7013 break;
7014 }
252b5132 7015
24eab124 7016 /* Skip the ':' and whitespace. */
252b5132
RH		 7017 ++op_string;
7018 if (is_space_char (*op_string))
24eab124 7019 ++op_string;
252b5132 7020
24eab124
AM		 7021 if (!is_digit_char (*op_string)
7022 && !is_identifier_char (*op_string)
7023 && *op_string != '('
7024 && *op_string != ABSOLUTE_PREFIX)
7025 {
7026 as_bad (_("bad memory operand `%s'"), op_string);
7027 return 0;
7028 }
47926f60 7029 /* Handle case of %es:*foo. */
24eab124
AM		 7030 if (*op_string == ABSOLUTE_PREFIX)
7031 {
7032 ++op_string;
7033 if (is_space_char (*op_string))
7034 ++op_string;
40fb9820 7035 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7036 }
7037 goto do_memory_reference;
7038 }
7039 if (*op_string)
7040 {
d0b47220 7041 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7042 return 0;
7043 }
40fb9820
L		 7044 temp = r->reg_type;
7045 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7046 i.types[this_operand] = operand_type_or (i.types[this_operand],
7047 temp);
7d5e4556 7048 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7049 i.op[this_operand].regs = r;
24eab124
AM		 7050 i.reg_operands++;
7051 }
af6bdddf
AM		 7052 else if (*op_string == REGISTER_PREFIX)
7053 {
7054 as_bad (_("bad register name `%s'"), op_string);
7055 return 0;
7056 }
24eab124 7057 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7058 {
24eab124 7059 ++op_string;
40fb9820 7060 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7061 {
d0b47220 7062 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7063 return 0;
7064 }
7065 if (!i386_immediate (op_string))
7066 return 0;
7067 }
7068 else if (is_digit_char (*op_string)
7069 || is_identifier_char (*op_string)
e5cb08ac 7070 || *op_string == '(')
24eab124 7071 {
47926f60 7072 /* This is a memory reference of some sort. */
af6bdddf 7073 char *base_string;
252b5132 7074
47926f60 7075 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7076 char *displacement_string_start;
7077 char *displacement_string_end;
252b5132 7078
24eab124 7079 do_memory_reference:
24eab124 7080 if ((i.mem_operands == 1
40fb9820 7081 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7082 || i.mem_operands == 2)
7083 {
7084 as_bad (_("too many memory references for `%s'"),
7085 current_templates->start->name);
7086 return 0;
7087 }
252b5132 7088
24eab124
AM		 7089 /* Check for base index form. We detect the base index form by
7090 looking for an ')' at the end of the operand, searching
7091 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7092 after the '('. */
af6bdddf 7093 base_string = op_string + strlen (op_string);
c3332e24 7094
af6bdddf
AM		 7095 --base_string;
7096 if (is_space_char (*base_string))
7097 --base_string;
252b5132 7098
47926f60 7099 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7100 displacement_string_start = op_string;
7101 displacement_string_end = base_string + 1;
252b5132 7102
24eab124
AM		 7103 if (*base_string == ')')
7104 {
af6bdddf 7105 char *temp_string;
24eab124
AM		 7106 unsigned int parens_balanced = 1;
7107 /* We've already checked that the number of left & right ()'s are
47926f60 7108 equal, so this loop will not be infinite. */
24eab124
AM		 7109 do
7110 {
7111 base_string--;
7112 if (*base_string == ')')
7113 parens_balanced++;
7114 if (*base_string == '(')
7115 parens_balanced--;
7116 }
7117 while (parens_balanced);
c3332e24 7118
af6bdddf 7119 temp_string = base_string;
c3332e24 7120
24eab124 7121 /* Skip past '(' and whitespace. */
252b5132
RH		 7122 ++base_string;
7123 if (is_space_char (*base_string))
24eab124 7124 ++base_string;
252b5132 7125
af6bdddf 7126 if (*base_string == ','
4eed87de
AM		 7127 || ((i.base_reg = parse_register (base_string, &end_op))
7128 != NULL))
252b5132 7129 {
af6bdddf 7130 displacement_string_end = temp_string;
252b5132 7131
40fb9820 7132 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7133
af6bdddf 7134 if (i.base_reg)
24eab124 7135 {
24eab124
AM		 7136 base_string = end_op;
7137 if (is_space_char (*base_string))
7138 ++base_string;
af6bdddf
AM		 7139 }
7140
7141 /* There may be an index reg or scale factor here. */
7142 if (*base_string == ',')
7143 {
7144 ++base_string;
7145 if (is_space_char (*base_string))
7146 ++base_string;
7147
4eed87de
AM		 7148 if ((i.index_reg = parse_register (base_string, &end_op))
7149 != NULL)
24eab124 7150 {
af6bdddf 7151 base_string = end_op;
24eab124
AM		 7152 if (is_space_char (*base_string))
7153 ++base_string;
af6bdddf
AM		 7154 if (*base_string == ',')
7155 {
7156 ++base_string;
7157 if (is_space_char (*base_string))
7158 ++base_string;
7159 }
e5cb08ac 7160 else if (*base_string != ')')
af6bdddf 7161 {
4eed87de
AM		 7162 as_bad (_("expecting `,' or `)' "
7163 "after index register in `%s'"),
af6bdddf
AM		 7164 operand_string);
7165 return 0;
7166 }
24eab124 7167 }
af6bdddf 7168 else if (*base_string == REGISTER_PREFIX)
24eab124 7169 {
af6bdddf 7170 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7171 return 0;
7172 }
252b5132 7173
47926f60 7174 /* Check for scale factor. */
551c1ca1 7175 if (*base_string != ')')
af6bdddf 7176 {
551c1ca1
AM		 7177 char *end_scale = i386_scale (base_string);
7178
7179 if (!end_scale)
af6bdddf 7180 return 0;
24eab124 7181
551c1ca1 7182 base_string = end_scale;
af6bdddf
AM		 7183 if (is_space_char (*base_string))
7184 ++base_string;
7185 if (*base_string != ')')
7186 {
4eed87de
AM		 7187 as_bad (_("expecting `)' "
7188 "after scale factor in `%s'"),
af6bdddf
AM		 7189 operand_string);
7190 return 0;
7191 }
7192 }
7193 else if (!i.index_reg)
24eab124 7194 {
4eed87de
AM		 7195 as_bad (_("expecting index register or scale factor "
7196 "after `,'; got '%c'"),
af6bdddf 7197 *base_string);
24eab124
AM		 7198 return 0;
7199 }
7200 }
af6bdddf 7201 else if (*base_string != ')')
24eab124 7202 {
4eed87de
AM		 7203 as_bad (_("expecting `,' or `)' "
7204 "after base register in `%s'"),
af6bdddf 7205 operand_string);
24eab124
AM		 7206 return 0;
7207 }
c3332e24 7208 }
af6bdddf 7209 else if (*base_string == REGISTER_PREFIX)
c3332e24 7210 {
af6bdddf 7211 as_bad (_("bad register name `%s'"), base_string);
24eab124 7212 return 0;
c3332e24 7213 }
24eab124
AM		 7214 }
7215
7216 /* If there's an expression beginning the operand, parse it,
7217 assuming displacement_string_start and
7218 displacement_string_end are meaningful. */
7219 if (displacement_string_start != displacement_string_end)
7220 {
7221 if (!i386_displacement (displacement_string_start,
7222 displacement_string_end))
7223 return 0;
7224 }
7225
7226 /* Special case for (%dx) while doing input/output op. */
7227 if (i.base_reg
0dfbf9d7
L		 7228 && operand_type_equal (&i.base_reg->reg_type,
7229 &reg16_inoutportreg)
24eab124
AM		 7230 && i.index_reg == 0
7231 && i.log2_scale_factor == 0
7232 && i.seg[i.mem_operands] == 0
40fb9820 7233 && !operand_type_check (i.types[this_operand], disp))
24eab124 7234 {
65da13b5 7235 i.types[this_operand] = inoutportreg;
24eab124
AM		 7236 return 1;
7237 }
7238
eecb386c
AM		 7239 if (i386_index_check (operand_string) == 0)
7240 return 0;
5c07affc 7241 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7242 i.mem_operands++;
7243 }
7244 else
ce8a8b2f
AM		 7245 {
7246 /* It's not a memory operand; argh! */
24eab124
AM		 7247 as_bad (_("invalid char %s beginning operand %d `%s'"),
7248 output_invalid (*op_string),
7249 this_operand + 1,
7250 op_string);
7251 return 0;
7252 }
47926f60 7253 return 1; /* Normal return. */
252b5132
RH		 7254}
7255\f
ee7fcc42
AM		 7256/* md_estimate_size_before_relax()
7257
7258 Called just before relax() for rs_machine_dependent frags. The x86
7259 assembler uses these frags to handle variable size jump
7260 instructions.
7261
7262 Any symbol that is now undefined will not become defined.
7263 Return the correct fr_subtype in the frag.
7264 Return the initial "guess for variable size of frag" to caller.
7265 The guess is actually the growth beyond the fixed part. Whatever
7266 we do to grow the fixed or variable part contributes to our
7267 returned value. */
7268
252b5132
RH		 7269int
7270md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7271 fragS *fragP;
7272 segT segment;
252b5132 7273{
252b5132 7274 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7275 check for un-relaxable symbols. On an ELF system, we can't relax
7276 an externally visible symbol, because it may be overridden by a
7277 shared library. */
7278 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7279#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7280 || (IS_ELF
31312f95
AM		 7281 && (S_IS_EXTERNAL (fragP->fr_symbol)
7282 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 7283#endif
7284 )
252b5132 7285 {
b98ef147
AM		 7286 /* Symbol is undefined in this segment, or we need to keep a
7287 reloc so that weak symbols can be overridden. */
7288 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7289 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7290 unsigned char *opcode;
7291 int old_fr_fix;
f6af82bd 7292
ee7fcc42
AM		 7293 if (fragP->fr_var != NO_RELOC)
7294 reloc_type = fragP->fr_var;
b98ef147 7295 else if (size == 2)
f6af82bd
AM		 7296 reloc_type = BFD_RELOC_16_PCREL;
7297 else
7298 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7299
ee7fcc42
AM		 7300 old_fr_fix = fragP->fr_fix;
7301 opcode = (unsigned char *) fragP->fr_opcode;
7302
fddf5b5b 7303 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7304 {
fddf5b5b
AM		 7305 case UNCOND_JUMP:
7306 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7307 opcode[0] = 0xe9;
252b5132 7308 fragP->fr_fix += size;
062cd5e7
AS		 7309 fix_new (fragP, old_fr_fix, size,
7310 fragP->fr_symbol,
7311 fragP->fr_offset, 1,
7312 reloc_type);
252b5132
RH		 7313 break;
7314
fddf5b5b 7315 case COND_JUMP86:
412167cb
AM		 7316 if (size == 2
7317 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7318 {
7319 /* Negate the condition, and branch past an
7320 unconditional jump. */
7321 opcode[0] ^= 1;
7322 opcode[1] = 3;
7323 /* Insert an unconditional jump. */
7324 opcode[2] = 0xe9;
7325 /* We added two extra opcode bytes, and have a two byte
7326 offset. */
7327 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7328 fix_new (fragP, old_fr_fix + 2, 2,
7329 fragP->fr_symbol,
7330 fragP->fr_offset, 1,
7331 reloc_type);
fddf5b5b
AM		 7332 break;
7333 }
7334 /* Fall through. */
7335
7336 case COND_JUMP:
412167cb
AM		 7337 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7338 {
3e02c1cc
AM		 7339 fixS *fixP;
7340
412167cb 7341 fragP->fr_fix += 1;
3e02c1cc
AM		 7342 fixP = fix_new (fragP, old_fr_fix, 1,
7343 fragP->fr_symbol,
7344 fragP->fr_offset, 1,
7345 BFD_RELOC_8_PCREL);
7346 fixP->fx_signed = 1;
412167cb
AM		 7347 break;
7348 }
93c2a809 7349
24eab124 7350 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7351 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7352 opcode[1] = opcode[0] + 0x10;
f6af82bd 7353 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7354 /* We've added an opcode byte. */
7355 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7356 fix_new (fragP, old_fr_fix + 1, size,
7357 fragP->fr_symbol,
7358 fragP->fr_offset, 1,
7359 reloc_type);
252b5132 7360 break;
fddf5b5b
AM		 7361
7362 default:
7363 BAD_CASE (fragP->fr_subtype);
7364 break;
252b5132
RH		 7365 }
7366 frag_wane (fragP);
ee7fcc42 7367 return fragP->fr_fix - old_fr_fix;
252b5132 7368 }
93c2a809 7369
93c2a809
AM		 7370 /* Guess size depending on current relax state. Initially the relax
7371 state will correspond to a short jump and we return 1, because
7372 the variable part of the frag (the branch offset) is one byte
7373 long. However, we can relax a section more than once and in that
7374 case we must either set fr_subtype back to the unrelaxed state,
7375 or return the value for the appropriate branch. */
7376 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7377}
7378
47926f60
KH		 7379/* Called after relax() is finished.
7380
7381 In: Address of frag.
7382 fr_type == rs_machine_dependent.
7383 fr_subtype is what the address relaxed to.
7384
7385 Out: Any fixSs and constants are set up.
7386 Caller will turn frag into a ".space 0". */
7387
252b5132
RH		 7388void
7389md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7390 bfd *abfd ATTRIBUTE_UNUSED;
7391 segT sec ATTRIBUTE_UNUSED;
29b0f896 7392 fragS *fragP;
252b5132 7393{
29b0f896 7394 unsigned char *opcode;
252b5132 7395 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7396 offsetT target_address;
7397 offsetT opcode_address;
252b5132 7398 unsigned int extension = 0;
847f7ad4 7399 offsetT displacement_from_opcode_start;
252b5132
RH		 7400
7401 opcode = (unsigned char *) fragP->fr_opcode;
7402
47926f60 7403 /* Address we want to reach in file space. */
252b5132 7404 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7405
47926f60 7406 /* Address opcode resides at in file space. */
252b5132
RH		 7407 opcode_address = fragP->fr_address + fragP->fr_fix;
7408
47926f60 7409 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7410 displacement_from_opcode_start = target_address - opcode_address;
7411
fddf5b5b 7412 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7413 {
47926f60
KH		 7414 /* Don't have to change opcode. */
7415 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7416 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7417 }
7418 else
7419 {
7420 if (no_cond_jump_promotion
7421 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7422 as_warn_where (fragP->fr_file, fragP->fr_line,
7423 _("long jump required"));
252b5132 7424
fddf5b5b
AM		 7425 switch (fragP->fr_subtype)
7426 {
7427 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7428 extension = 4; /* 1 opcode + 4 displacement */
7429 opcode[0] = 0xe9;
7430 where_to_put_displacement = &opcode[1];
7431 break;
252b5132 7432
fddf5b5b
AM		 7433 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7434 extension = 2; /* 1 opcode + 2 displacement */
7435 opcode[0] = 0xe9;
7436 where_to_put_displacement = &opcode[1];
7437 break;
252b5132 7438
fddf5b5b
AM		 7439 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7440 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7441 extension = 5; /* 2 opcode + 4 displacement */
7442 opcode[1] = opcode[0] + 0x10;
7443 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7444 where_to_put_displacement = &opcode[2];
7445 break;
252b5132 7446
fddf5b5b
AM		 7447 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7448 extension = 3; /* 2 opcode + 2 displacement */
7449 opcode[1] = opcode[0] + 0x10;
7450 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7451 where_to_put_displacement = &opcode[2];
7452 break;
252b5132 7453
fddf5b5b
AM		 7454 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7455 extension = 4;
7456 opcode[0] ^= 1;
7457 opcode[1] = 3;
7458 opcode[2] = 0xe9;
7459 where_to_put_displacement = &opcode[3];
7460 break;
7461
7462 default:
7463 BAD_CASE (fragP->fr_subtype);
7464 break;
7465 }
252b5132 7466 }
fddf5b5b 7467
7b81dfbb
AJ		 7468 /* If size if less then four we are sure that the operand fits,
7469 but if it's 4, then it could be that the displacement is larger
7470 then -/+ 2GB. */
7471 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7472 && object_64bit
7473 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7474 + ((addressT) 1 << 31))
7475 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7476 {
7477 as_bad_where (fragP->fr_file, fragP->fr_line,
7478 _("jump target out of range"));
7479 /* Make us emit 0. */
7480 displacement_from_opcode_start = extension;
7481 }
47926f60 7482 /* Now put displacement after opcode. */
252b5132
RH		 7483 md_number_to_chars ((char *) where_to_put_displacement,
7484 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7485 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7486 fragP->fr_fix += extension;
7487}
7488\f
252b5132
RH		 7489/* Apply a fixup (fixS) to segment data, once it has been determined
7490 by our caller that we have all the info we need to fix it up.
7491
7492 On the 386, immediates, displacements, and data pointers are all in
7493 the same (little-endian) format, so we don't need to care about which
7494 we are handling. */
7495
94f592af 7496void
55cf6793 7497md_apply_fix (fixP, valP, seg)
47926f60
KH		 7498 /* The fix we're to put in. */
7499 fixS *fixP;
47926f60 7500 /* Pointer to the value of the bits. */
c6682705 7501 valueT *valP;
47926f60
KH		 7502 /* Segment fix is from. */
7503 segT seg ATTRIBUTE_UNUSED;
252b5132 7504{
94f592af 7505 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7506 valueT value = *valP;
252b5132 7507
f86103b7 7508#if !defined (TE_Mach)
93382f6d
AM		 7509 if (fixP->fx_pcrel)
7510 {
7511 switch (fixP->fx_r_type)
7512 {
5865bb77
ILT		 7513 default:
7514 break;
7515
d6ab8113
JB		 7516 case BFD_RELOC_64:
7517 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7518 break;
93382f6d 7519 case BFD_RELOC_32:
ae8887b5 7520 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7521 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7522 break;
7523 case BFD_RELOC_16:
7524 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7525 break;
7526 case BFD_RELOC_8:
7527 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7528 break;
7529 }
7530 }
252b5132 7531
a161fe53 7532 if (fixP->fx_addsy != NULL
31312f95 7533 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7534 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7535 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7536 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7537 && !use_rela_relocations)
252b5132 7538 {
31312f95
AM		 7539 /* This is a hack. There should be a better way to handle this.
7540 This covers for the fact that bfd_install_relocation will
7541 subtract the current location (for partial_inplace, PC relative
7542 relocations); see more below. */
252b5132 7543#ifndef OBJ_AOUT
718ddfc0 7544 if (IS_ELF
252b5132
RH		 7545#ifdef TE_PE
7546 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7547#endif
7548 )
7549 value += fixP->fx_where + fixP->fx_frag->fr_address;
7550#endif
7551#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7552 if (IS_ELF)
252b5132 7553 {
6539b54b 7554 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7555
6539b54b 7556 if ((sym_seg == seg
2f66722d 7557 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7558 && sym_seg != absolute_section))
ae6063d4 7559 && !generic_force_reloc (fixP))
2f66722d
AM		 7560 {
7561 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7562 bfd_install_relocation subtracts them out again. I think
7563 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7564 it. FIXME. */
7565 value += fixP->fx_where + fixP->fx_frag->fr_address;
7566 }
252b5132
RH		 7567 }
7568#endif
7569#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7570 /* For some reason, the PE format does not store a
7571 section address offset for a PC relative symbol. */
7572 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7573 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7574 value += md_pcrel_from (fixP);
7575#endif
7576 }
7577
7578 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7579 and we must not disappoint it. */
252b5132 7580#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7581 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7582 switch (fixP->fx_r_type)
7583 {
7584 case BFD_RELOC_386_PLT32:
3e73aa7c 7585 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7586 /* Make the jump instruction point to the address of the operand. At
7587 runtime we merely add the offset to the actual PLT entry. */
7588 value = -4;
7589 break;
31312f95 7590
13ae64f3
JJ		 7591 case BFD_RELOC_386_TLS_GD:
7592 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7593 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7594 case BFD_RELOC_386_TLS_IE:
7595 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7596 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7597 case BFD_RELOC_X86_64_TLSGD:
7598 case BFD_RELOC_X86_64_TLSLD:
7599 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7600 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7601 value = 0; /* Fully resolved at runtime. No addend. */
7602 /* Fallthrough */
7603 case BFD_RELOC_386_TLS_LE:
7604 case BFD_RELOC_386_TLS_LDO_32:
7605 case BFD_RELOC_386_TLS_LE_32:
7606 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7607 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7608 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7609 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7610 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7611 break;
7612
67a4f2b7
AO		 7613 case BFD_RELOC_386_TLS_DESC_CALL:
7614 case BFD_RELOC_X86_64_TLSDESC_CALL:
7615 value = 0; /* Fully resolved at runtime. No addend. */
7616 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7617 fixP->fx_done = 0;
7618 return;
7619
00f7efb6
JJ		 7620 case BFD_RELOC_386_GOT32:
7621 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7622 value = 0; /* Fully resolved at runtime. No addend. */
7623 break;
47926f60
KH		 7624
7625 case BFD_RELOC_VTABLE_INHERIT:
7626 case BFD_RELOC_VTABLE_ENTRY:
7627 fixP->fx_done = 0;
94f592af 7628 return;
47926f60
KH		 7629
7630 default:
7631 break;
7632 }
7633#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7634 *valP = value;
f86103b7 7635#endif /* !defined (TE_Mach) */
3e73aa7c 7636
3e73aa7c 7637 /* Are we finished with this relocation now? */
c6682705 7638 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 7639 fixP->fx_done = 1;
7640 else if (use_rela_relocations)
7641 {
7642 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7643 /* Remember value for tc_gen_reloc. */
7644 fixP->fx_addnumber = value;
3e73aa7c
JH		 7645 value = 0;
7646 }
f86103b7 7647
94f592af 7648 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7649}
252b5132 7650\f
252b5132 7651char *
499ac353 7652md_atof (int type, char *litP, int *sizeP)
252b5132 7653{
499ac353
NC		 7654 /* This outputs the LITTLENUMs in REVERSE order;
7655 in accord with the bigendian 386. */
7656 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7657}
7658\f
2d545b82 7659static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7660
252b5132 7661static char *
e3bb37b5 7662output_invalid (int c)
252b5132 7663{
3882b010 7664 if (ISPRINT (c))
f9f21a03
L		 7665 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7666 "'%c'", c);
252b5132 7667 else
f9f21a03 7668 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7669 "(0x%x)", (unsigned char) c);
252b5132
RH		 7670 return output_invalid_buf;
7671}
7672
af6bdddf 7673/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7674
7675static const reg_entry *
4d1bb795 7676parse_real_register (char *reg_string, char **end_op)
252b5132 7677{
af6bdddf
AM		 7678 char *s = reg_string;
7679 char *p;
252b5132
RH		 7680 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7681 const reg_entry *r;
7682
7683 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7684 if (*s == REGISTER_PREFIX)
7685 ++s;
7686
7687 if (is_space_char (*s))
7688 ++s;
7689
7690 p = reg_name_given;
af6bdddf 7691 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7692 {
7693 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7694 return (const reg_entry *) NULL;
7695 s++;
252b5132
RH		 7696 }
7697
6588847e
DN		 7698 /* For naked regs, make sure that we are not dealing with an identifier.
7699 This prevents confusing an identifier like `eax_var' with register
7700 `eax'. */
7701 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7702 return (const reg_entry *) NULL;
7703
af6bdddf 7704 *end_op = s;
252b5132
RH		 7705
7706 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7707
5f47d35b 7708 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7709 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7710 {
5f47d35b
AM		 7711 if (is_space_char (*s))
7712 ++s;
7713 if (*s == '(')
7714 {
af6bdddf 7715 ++s;
5f47d35b
AM		 7716 if (is_space_char (*s))
7717 ++s;
7718 if (*s >= '0' && *s <= '7')
7719 {
db557034 7720 int fpr = *s - '0';
af6bdddf 7721 ++s;
5f47d35b
AM		 7722 if (is_space_char (*s))
7723 ++s;
7724 if (*s == ')')
7725 {
7726 *end_op = s + 1;
db557034
AM		 7727 r = hash_find (reg_hash, "st(0)");
7728 know (r);
7729 return r + fpr;
5f47d35b 7730 }
5f47d35b 7731 }
47926f60 7732 /* We have "%st(" then garbage. */
5f47d35b
AM		 7733 return (const reg_entry *) NULL;
7734 }
7735 }
7736
a60de03c
JB		 7737 if (r == NULL || allow_pseudo_reg)
7738 return r;
7739
0dfbf9d7 7740 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7741 return (const reg_entry *) NULL;
7742
192dc9c6
JB		 7743 if ((r->reg_type.bitfield.reg32
7744 || r->reg_type.bitfield.sreg3
7745 || r->reg_type.bitfield.control
7746 || r->reg_type.bitfield.debug
7747 || r->reg_type.bitfield.test)
7748 && !cpu_arch_flags.bitfield.cpui386)
7749 return (const reg_entry *) NULL;
7750
7751 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7752 return (const reg_entry *) NULL;
7753
7754 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7755 return (const reg_entry *) NULL;
7756
40f12533
L		 7757 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7758 return (const reg_entry *) NULL;
7759
db51cc60 7760 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7761 if (!allow_index_reg
db51cc60
L		 7762 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7763 return (const reg_entry *) NULL;
7764
a60de03c
JB		 7765 if (((r->reg_flags & (RegRex64 | RegRex))
7766 || r->reg_type.bitfield.reg64)
40fb9820 7767 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7768 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7769 && flag_code != CODE_64BIT)
20f0a1fc 7770 return (const reg_entry *) NULL;
1ae00879 7771
b7240065
JB		 7772 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7773 return (const reg_entry *) NULL;
7774
252b5132
RH		 7775 return r;
7776}
4d1bb795
JB		 7777
7778/* REG_STRING starts *before* REGISTER_PREFIX. */
7779
7780static const reg_entry *
7781parse_register (char *reg_string, char **end_op)
7782{
7783 const reg_entry *r;
7784
7785 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7786 r = parse_real_register (reg_string, end_op);
7787 else
7788 r = NULL;
7789 if (!r)
7790 {
7791 char *save = input_line_pointer;
7792 char c;
7793 symbolS *symbolP;
7794
7795 input_line_pointer = reg_string;
7796 c = get_symbol_end ();
7797 symbolP = symbol_find (reg_string);
7798 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7799 {
7800 const expressionS *e = symbol_get_value_expression (symbolP);
7801
7802 know (e->X_op == O_register);
4eed87de 7803 know (e->X_add_number >= 0
c3fe08fa 7804 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7805 r = i386_regtab + e->X_add_number;
7806 *end_op = input_line_pointer;
7807 }
7808 *input_line_pointer = c;
7809 input_line_pointer = save;
7810 }
7811 return r;
7812}
7813
7814int
7815i386_parse_name (char *name, expressionS *e, char *nextcharP)
7816{
7817 const reg_entry *r;
7818 char *end = input_line_pointer;
7819
7820 *end = *nextcharP;
7821 r = parse_register (name, &input_line_pointer);
7822 if (r && end <= input_line_pointer)
7823 {
7824 *nextcharP = *input_line_pointer;
7825 *input_line_pointer = 0;
7826 e->X_op = O_register;
7827 e->X_add_number = r - i386_regtab;
7828 return 1;
7829 }
7830 input_line_pointer = end;
7831 *end = 0;
7832 return 0;
7833}
7834
7835void
7836md_operand (expressionS *e)
7837{
7838 if (*input_line_pointer == REGISTER_PREFIX)
7839 {
7840 char *end;
7841 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7842
7843 if (r)
7844 {
7845 e->X_op = O_register;
7846 e->X_add_number = r - i386_regtab;
7847 input_line_pointer = end;
7848 }
7849 }
7850}
7851
252b5132 7852\f
4cc782b5 7853#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7854const char *md_shortopts = "kVQ:sqn";
252b5132 7855#else
12b55ccc 7856const char *md_shortopts = "qn";
252b5132 7857#endif
6e0b89ee 7858
3e73aa7c 7859#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7860#define OPTION_64 (OPTION_MD_BASE + 1)
7861#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7862#define OPTION_MARCH (OPTION_MD_BASE + 3)
7863#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7864#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7865#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7866#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7867#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7868#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 7869#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 7870#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
b3b91714 7871
99ad8390
NC		 7872struct option md_longopts[] =
7873{
3e73aa7c 7874 {"32", no_argument, NULL, OPTION_32},
99ad8390 7875#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 7876 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7877#endif
b3b91714 7878 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7879 {"march", required_argument, NULL, OPTION_MARCH},
7880 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7881 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7882 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7883 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7884 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7885 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 7886 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 7887 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
252b5132
RH		 7888 {NULL, no_argument, NULL, 0}
7889};
7890size_t md_longopts_size = sizeof (md_longopts);
7891
7892int
9103f4f4 7893md_parse_option (int c, char *arg)
252b5132 7894{
9103f4f4 7895 unsigned int i;
6305a203 7896 char *arch, *next;
9103f4f4 7897
252b5132
RH		 7898 switch (c)
7899 {
12b55ccc
L		 7900 case 'n':
7901 optimize_align_code = 0;
7902 break;
7903
a38cf1db
AM		 7904 case 'q':
7905 quiet_warnings = 1;
252b5132
RH		 7906 break;
7907
7908#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7909 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7910 should be emitted or not. FIXME: Not implemented. */
7911 case 'Q':
252b5132
RH		 7912 break;
7913
7914 /* -V: SVR4 argument to print version ID. */
7915 case 'V':
7916 print_version_id ();
7917 break;
7918
a38cf1db
AM		 7919 /* -k: Ignore for FreeBSD compatibility. */
7920 case 'k':
252b5132 7921 break;
4cc782b5
ILT		 7922
7923 case 's':
7924 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7925 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7926 break;
99ad8390
NC		 7927#endif
7928#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 7929 case OPTION_64:
7930 {
7931 const char **list, **l;
7932
3e73aa7c
JH		 7933 list = bfd_target_list ();
7934 for (l = list; *l != NULL; l++)
8620418b 7935 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7936 || strcmp (*l, "coff-x86-64") == 0
7937 || strcmp (*l, "pe-x86-64") == 0
7938 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7939 {
7940 default_arch = "x86_64";
7941 break;
7942 }
3e73aa7c 7943 if (*l == NULL)
6e0b89ee 7944 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7945 free (list);
7946 }
7947 break;
7948#endif
252b5132 7949
6e0b89ee
AM		 7950 case OPTION_32:
7951 default_arch = "i386";
7952 break;
7953
b3b91714
AM		 7954 case OPTION_DIVIDE:
7955#ifdef SVR4_COMMENT_CHARS
7956 {
7957 char *n, *t;
7958 const char *s;
7959
7960 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7961 t = n;
7962 for (s = i386_comment_chars; *s != '\0'; s++)
7963 if (*s != '/')
7964 *t++ = *s;
7965 *t = '\0';
7966 i386_comment_chars = n;
7967 }
7968#endif
7969 break;
7970
9103f4f4 7971 case OPTION_MARCH:
6305a203
L		 7972 arch = xstrdup (arg);
7973 do
9103f4f4 7974 {
6305a203
L		 7975 if (*arch == '.')
7976 as_fatal (_("Invalid -march= option: `%s'"), arg);
7977 next = strchr (arch, '+');
7978 if (next)
7979 *next++ = '\0';
7980 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 7981 {
6305a203 7982 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 7983 {
6305a203
L		 7984 /* Processor. */
7985 cpu_arch_name = cpu_arch[i].name;
7986 cpu_sub_arch_name = NULL;
7987 cpu_arch_flags = cpu_arch[i].flags;
7988 cpu_arch_isa = cpu_arch[i].type;
7989 cpu_arch_isa_flags = cpu_arch[i].flags;
7990 if (!cpu_arch_tune_set)
7991 {
7992 cpu_arch_tune = cpu_arch_isa;
7993 cpu_arch_tune_flags = cpu_arch_isa_flags;
7994 }
7995 break;
7996 }
7997 else if (*cpu_arch [i].name == '.'
7998 && strcmp (arch, cpu_arch [i].name + 1) == 0)
7999 {
8000 /* ISA entension. */
8001 i386_cpu_flags flags;
8002 flags = cpu_flags_or (cpu_arch_flags,
8003 cpu_arch[i].flags);
0dfbf9d7 8004 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8005 {
8006 if (cpu_sub_arch_name)
8007 {
8008 char *name = cpu_sub_arch_name;
8009 cpu_sub_arch_name = concat (name,
8010 cpu_arch[i].name,
1bf57e9f 8011 (const char *) NULL);
6305a203
L		 8012 free (name);
8013 }
8014 else
8015 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
8016 cpu_arch_flags = flags;
8017 }
8018 break;
ccc9c027 8019 }
9103f4f4 8020 }
6305a203
L		 8021
8022 if (i >= ARRAY_SIZE (cpu_arch))
8023 as_fatal (_("Invalid -march= option: `%s'"), arg);
8024
8025 arch = next;
9103f4f4 8026 }
6305a203 8027 while (next != NULL );
9103f4f4
L		 8028 break;
8029
8030 case OPTION_MTUNE:
8031 if (*arg == '.')
8032 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8033 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
8034 {
8035 if (strcmp (arg, cpu_arch [i].name) == 0)
8036 {
ccc9c027 8037 cpu_arch_tune_set = 1;
9103f4f4
L		 8038 cpu_arch_tune = cpu_arch [i].type;
8039 cpu_arch_tune_flags = cpu_arch[i].flags;
8040 break;
8041 }
8042 }
8043 if (i >= ARRAY_SIZE (cpu_arch))
8044 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8045 break;
8046
1efbbeb4
L		 8047 case OPTION_MMNEMONIC:
8048 if (strcasecmp (arg, "att") == 0)
8049 intel_mnemonic = 0;
8050 else if (strcasecmp (arg, "intel") == 0)
8051 intel_mnemonic = 1;
8052 else
8053 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8054 break;
8055
8056 case OPTION_MSYNTAX:
8057 if (strcasecmp (arg, "att") == 0)
8058 intel_syntax = 0;
8059 else if (strcasecmp (arg, "intel") == 0)
8060 intel_syntax = 1;
8061 else
8062 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8063 break;
8064
8065 case OPTION_MINDEX_REG:
8066 allow_index_reg = 1;
8067 break;
8068
8069 case OPTION_MNAKED_REG:
8070 allow_naked_reg = 1;
8071 break;
8072
8073 case OPTION_MOLD_GCC:
8074 old_gcc = 1;
1efbbeb4
L		 8075 break;
8076
c0f3af97
L		 8077 case OPTION_MSSE2AVX:
8078 sse2avx = 1;
8079 break;
8080
daf50ae7
L		 8081 case OPTION_MSSE_CHECK:
8082 if (strcasecmp (arg, "error") == 0)
8083 sse_check = sse_check_error;
8084 else if (strcasecmp (arg, "warning") == 0)
8085 sse_check = sse_check_warning;
8086 else if (strcasecmp (arg, "none") == 0)
8087 sse_check = sse_check_none;
8088 else
8089 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8090 break;
8091
252b5132
RH		 8092 default:
8093 return 0;
8094 }
8095 return 1;
8096}
8097
8098void
8099md_show_usage (stream)
8100 FILE *stream;
8101{
4cc782b5
ILT		 8102#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8103 fprintf (stream, _("\
a38cf1db
AM		 8104 -Q ignored\n\
8105 -V print assembler version number\n\
b3b91714
AM		 8106 -k ignored\n"));
8107#endif
8108 fprintf (stream, _("\
12b55ccc 8109 -n Do not optimize code alignment\n\
b3b91714
AM		 8110 -q quieten some warnings\n"));
8111#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8112 fprintf (stream, _("\
a38cf1db 8113 -s ignored\n"));
b3b91714 8114#endif
751d281c
L		 8115#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8116 fprintf (stream, _("\
8117 --32/--64 generate 32bit/64bit code\n"));
8118#endif
b3b91714
AM		 8119#ifdef SVR4_COMMENT_CHARS
8120 fprintf (stream, _("\
8121 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8122#else
8123 fprintf (stream, _("\
b3b91714 8124 --divide ignored\n"));
4cc782b5 8125#endif
9103f4f4 8126 fprintf (stream, _("\
6305a203
L		 8127 -march=CPU[,+EXTENSION...]\n\
8128 generate code for CPU and EXTENSION, CPU is one of:\n\
2cb4f3d5
L		 8129 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8130 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8131 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8132 generic32, generic64\n\
599121aa
L		 8133 EXTENSION is combination of:\n\
8134 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
f1f8f695
L		 8135 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8136 3dnow, 3dnowa, sse4a, sse5, svme, abm, padlock\n"));
6305a203 8137 fprintf (stream, _("\
2cb4f3d5
L		 8138 -mtune=CPU optimize for CPU, CPU is one of:\n\
8139 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8140 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8141 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8142 generic32, generic64\n"));
ba104c83 8143 fprintf (stream, _("\
c0f3af97
L		 8144 -msse2avx encode SSE instructions with VEX prefix\n"));
8145 fprintf (stream, _("\
daf50ae7
L		 8146 -msse-check=[none|error|warning]\n\
8147 check SSE instructions\n"));
8148 fprintf (stream, _("\
ba104c83
L		 8149 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8150 fprintf (stream, _("\
8151 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8152 fprintf (stream, _("\
8153 -mindex-reg support pseudo index registers\n"));
8154 fprintf (stream, _("\
8155 -mnaked-reg don't require `%%' prefix for registers\n"));
8156 fprintf (stream, _("\
8157 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8158}
8159
3e73aa7c 8160#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 8161 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 8162
8163/* Pick the target format to use. */
8164
47926f60 8165const char *
e3bb37b5 8166i386_target_format (void)
252b5132 8167{
3e73aa7c 8168 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 8169 {
8170 set_code_flag (CODE_64BIT);
0dfbf9d7 8171 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8172 {
8173 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8174 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8175 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8176 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8177 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8178 cpu_arch_isa_flags.bitfield.cpui686 = 1;
8179 cpu_arch_isa_flags.bitfield.cpup4 = 1;
8180 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 8181 cpu_arch_isa_flags.bitfield.cpusse = 1;
8182 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
8183 }
0dfbf9d7 8184 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8185 {
8186 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8187 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8188 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8189 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8190 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8191 cpu_arch_tune_flags.bitfield.cpui686 = 1;
8192 cpu_arch_tune_flags.bitfield.cpup4 = 1;
8193 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 8194 cpu_arch_tune_flags.bitfield.cpusse = 1;
8195 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8196 }
9103f4f4 8197 }
3e73aa7c 8198 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 8199 {
8200 set_code_flag (CODE_32BIT);
0dfbf9d7 8201 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8202 {
8203 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8204 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8205 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8206 }
0dfbf9d7 8207 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8208 {
8209 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8210 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8211 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8212 }
9103f4f4 8213 }
3e73aa7c
JH		 8214 else
8215 as_fatal (_("Unknown architecture"));
252b5132
RH		 8216 switch (OUTPUT_FLAVOR)
8217 {
872ce6ff
L		 8218#ifdef TE_PEP
8219 case bfd_target_coff_flavour:
8220 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
8221 break;
8222#endif
4c63da97
AM		 8223#ifdef OBJ_MAYBE_AOUT
8224 case bfd_target_aout_flavour:
47926f60 8225 return AOUT_TARGET_FORMAT;
4c63da97
AM		 8226#endif
8227#ifdef OBJ_MAYBE_COFF
252b5132
RH		 8228 case bfd_target_coff_flavour:
8229 return "coff-i386";
4c63da97 8230#endif
3e73aa7c 8231#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8232 case bfd_target_elf_flavour:
3e73aa7c 8233 {
e5cb08ac 8234 if (flag_code == CODE_64BIT)
4fa24527
JB		 8235 {
8236 object_64bit = 1;
8237 use_rela_relocations = 1;
8238 }
9d7cbccd 8239 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 8240 }
4c63da97 8241#endif
252b5132
RH		 8242 default:
8243 abort ();
8244 return NULL;
8245 }
8246}
8247
47926f60 8248#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8249
8250#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8251void
8252i386_elf_emit_arch_note (void)
a847613f 8253{
718ddfc0 8254 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8255 {
8256 char *p;
8257 asection *seg = now_seg;
8258 subsegT subseg = now_subseg;
8259 Elf_Internal_Note i_note;
8260 Elf_External_Note e_note;
8261 asection *note_secp;
8262 int len;
8263
8264 /* Create the .note section. */
8265 note_secp = subseg_new (".note", 0);
8266 bfd_set_section_flags (stdoutput,
8267 note_secp,
8268 SEC_HAS_CONTENTS | SEC_READONLY);
8269
8270 /* Process the arch string. */
8271 len = strlen (cpu_arch_name);
8272
8273 i_note.namesz = len + 1;
8274 i_note.descsz = 0;
8275 i_note.type = NT_ARCH;
8276 p = frag_more (sizeof (e_note.namesz));
8277 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8278 p = frag_more (sizeof (e_note.descsz));
8279 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8280 p = frag_more (sizeof (e_note.type));
8281 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8282 p = frag_more (len + 1);
8283 strcpy (p, cpu_arch_name);
8284
8285 frag_align (2, 0, 0);
8286
8287 subseg_set (seg, subseg);
8288 }
8289}
8290#endif
252b5132 8291\f
252b5132
RH		 8292symbolS *
8293md_undefined_symbol (name)
8294 char *name;
8295{
18dc2407
ILT		 8296 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8297 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8298 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8299 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8300 {
8301 if (!GOT_symbol)
8302 {
8303 if (symbol_find (name))
8304 as_bad (_("GOT already in symbol table"));
8305 GOT_symbol = symbol_new (name, undefined_section,
8306 (valueT) 0, &zero_address_frag);
8307 };
8308 return GOT_symbol;
8309 }
252b5132
RH		 8310 return 0;
8311}
8312
8313/* Round up a section size to the appropriate boundary. */
47926f60 8314
252b5132
RH		 8315valueT
8316md_section_align (segment, size)
ab9da554 8317 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8318 valueT size;
8319{
4c63da97
AM		 8320#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8321 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8322 {
8323 /* For a.out, force the section size to be aligned. If we don't do
8324 this, BFD will align it for us, but it will not write out the
8325 final bytes of the section. This may be a bug in BFD, but it is
8326 easier to fix it here since that is how the other a.out targets
8327 work. */
8328 int align;
8329
8330 align = bfd_get_section_alignment (stdoutput, segment);
8331 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8332 }
252b5132
RH		 8333#endif
8334
8335 return size;
8336}
8337
8338/* On the i386, PC-relative offsets are relative to the start of the
8339 next instruction. That is, the address of the offset, plus its
8340 size, since the offset is always the last part of the insn. */
8341
8342long
e3bb37b5 8343md_pcrel_from (fixS *fixP)
252b5132
RH		 8344{
8345 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8346}
8347
8348#ifndef I386COFF
8349
8350static void
e3bb37b5 8351s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8352{
29b0f896 8353 int temp;
252b5132 8354
8a75718c
JB		 8355#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8356 if (IS_ELF)
8357 obj_elf_section_change_hook ();
8358#endif
252b5132
RH		 8359 temp = get_absolute_expression ();
8360 subseg_set (bss_section, (subsegT) temp);
8361 demand_empty_rest_of_line ();
8362}
8363
8364#endif
8365
252b5132 8366void
e3bb37b5 8367i386_validate_fix (fixS *fixp)
252b5132
RH		 8368{
8369 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8370 {
23df1078
JH		 8371 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8372 {
4fa24527 8373 if (!object_64bit)
23df1078
JH		 8374 abort ();
8375 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8376 }
8377 else
8378 {
4fa24527 8379 if (!object_64bit)
d6ab8113
JB		 8380 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8381 else
8382 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8383 }
252b5132
RH		 8384 fixp->fx_subsy = 0;
8385 }
8386}
8387
252b5132
RH		 8388arelent *
8389tc_gen_reloc (section, fixp)
ab9da554 8390 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8391 fixS *fixp;
8392{
8393 arelent *rel;
8394 bfd_reloc_code_real_type code;
8395
8396 switch (fixp->fx_r_type)
8397 {
3e73aa7c
JH		 8398 case BFD_RELOC_X86_64_PLT32:
8399 case BFD_RELOC_X86_64_GOT32:
8400 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8401 case BFD_RELOC_386_PLT32:
8402 case BFD_RELOC_386_GOT32:
8403 case BFD_RELOC_386_GOTOFF:
8404 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8405 case BFD_RELOC_386_TLS_GD:
8406 case BFD_RELOC_386_TLS_LDM:
8407 case BFD_RELOC_386_TLS_LDO_32:
8408 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8409 case BFD_RELOC_386_TLS_IE:
8410 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8411 case BFD_RELOC_386_TLS_LE_32:
8412 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8413 case BFD_RELOC_386_TLS_GOTDESC:
8414 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8415 case BFD_RELOC_X86_64_TLSGD:
8416 case BFD_RELOC_X86_64_TLSLD:
8417 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8418 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8419 case BFD_RELOC_X86_64_GOTTPOFF:
8420 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8421 case BFD_RELOC_X86_64_TPOFF64:
8422 case BFD_RELOC_X86_64_GOTOFF64:
8423 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8424 case BFD_RELOC_X86_64_GOT64:
8425 case BFD_RELOC_X86_64_GOTPCREL64:
8426 case BFD_RELOC_X86_64_GOTPC64:
8427 case BFD_RELOC_X86_64_GOTPLT64:
8428 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8429 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8430 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8431 case BFD_RELOC_RVA:
8432 case BFD_RELOC_VTABLE_ENTRY:
8433 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8434#ifdef TE_PE
8435 case BFD_RELOC_32_SECREL:
8436#endif
252b5132
RH		 8437 code = fixp->fx_r_type;
8438 break;
dbbaec26
L		 8439 case BFD_RELOC_X86_64_32S:
8440 if (!fixp->fx_pcrel)
8441 {
8442 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8443 code = fixp->fx_r_type;
8444 break;
8445 }
252b5132 8446 default:
93382f6d 8447 if (fixp->fx_pcrel)
252b5132 8448 {
93382f6d
AM		 8449 switch (fixp->fx_size)
8450 {
8451 default:
b091f402
AM		 8452 as_bad_where (fixp->fx_file, fixp->fx_line,
8453 _("can not do %d byte pc-relative relocation"),
8454 fixp->fx_size);
93382f6d
AM		 8455 code = BFD_RELOC_32_PCREL;
8456 break;
8457 case 1: code = BFD_RELOC_8_PCREL; break;
8458 case 2: code = BFD_RELOC_16_PCREL; break;
8459 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8460#ifdef BFD64
8461 case 8: code = BFD_RELOC_64_PCREL; break;
8462#endif
93382f6d
AM		 8463 }
8464 }
8465 else
8466 {
8467 switch (fixp->fx_size)
8468 {
8469 default:
b091f402
AM		 8470 as_bad_where (fixp->fx_file, fixp->fx_line,
8471 _("can not do %d byte relocation"),
8472 fixp->fx_size);
93382f6d
AM		 8473 code = BFD_RELOC_32;
8474 break;
8475 case 1: code = BFD_RELOC_8; break;
8476 case 2: code = BFD_RELOC_16; break;
8477 case 4: code = BFD_RELOC_32; break;
937149dd 8478#ifdef BFD64
3e73aa7c 8479 case 8: code = BFD_RELOC_64; break;
937149dd 8480#endif
93382f6d 8481 }
252b5132
RH		 8482 }
8483 break;
8484 }
252b5132 8485
d182319b
JB		 8486 if ((code == BFD_RELOC_32
8487 || code == BFD_RELOC_32_PCREL
8488 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8489 && GOT_symbol
8490 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8491 {
4fa24527 8492 if (!object_64bit)
d6ab8113
JB		 8493 code = BFD_RELOC_386_GOTPC;
8494 else
8495 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8496 }
7b81dfbb
AJ		 8497 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8498 && GOT_symbol
8499 && fixp->fx_addsy == GOT_symbol)
8500 {
8501 code = BFD_RELOC_X86_64_GOTPC64;
8502 }
252b5132
RH		 8503
8504 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8505 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8506 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8507
8508 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8509
3e73aa7c
JH		 8510 if (!use_rela_relocations)
8511 {
8512 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8513 vtable entry to be used in the relocation's section offset. */
8514 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8515 rel->address = fixp->fx_offset;
252b5132 8516
c6682705 8517 rel->addend = 0;
3e73aa7c
JH		 8518 }
8519 /* Use the rela in 64bit mode. */
252b5132 8520 else
3e73aa7c 8521 {
062cd5e7
AS		 8522 if (!fixp->fx_pcrel)
8523 rel->addend = fixp->fx_offset;
8524 else
8525 switch (code)
8526 {
8527 case BFD_RELOC_X86_64_PLT32:
8528 case BFD_RELOC_X86_64_GOT32:
8529 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8530 case BFD_RELOC_X86_64_TLSGD:
8531 case BFD_RELOC_X86_64_TLSLD:
8532 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8533 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8534 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8535 rel->addend = fixp->fx_offset - fixp->fx_size;
8536 break;
8537 default:
8538 rel->addend = (section->vma
8539 - fixp->fx_size
8540 + fixp->fx_addnumber
8541 + md_pcrel_from (fixp));
8542 break;
8543 }
3e73aa7c
JH		 8544 }
8545
252b5132
RH		 8546 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8547 if (rel->howto == NULL)
8548 {
8549 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8550 _("cannot represent relocation type %s"),
252b5132
RH		 8551 bfd_get_reloc_code_name (code));
8552 /* Set howto to a garbage value so that we can keep going. */
8553 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
8554 assert (rel->howto != NULL);
8555 }
8556
8557 return rel;
8558}
8559
64a0c779
DN		 8560\f
8561/* Parse operands using Intel syntax. This implements a recursive descent
8562 parser based on the BNF grammar published in Appendix B of the MASM 6.1
8563 Programmer's Guide.
8564
8565 FIXME: We do not recognize the full operand grammar defined in the MASM
8566 documentation. In particular, all the structure/union and
8567 high-level macro operands are missing.
8568
8569 Uppercase words are terminals, lower case words are non-terminals.
8570 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8571 bars '|' denote choices. Most grammar productions are implemented in
8572 functions called 'intel_<production>'.
8573
8574 Initial production is 'expr'.
8575
9306ca4a 8576 addOp + | -
64a0c779
DN		 8577
8578 alpha [a-zA-Z]
8579
9306ca4a
JB		 8580 binOp & | AND | \| | OR | ^ | XOR
8581
64a0c779
DN		 8582 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
8583
8584 constant digits [[ radixOverride ]]
8585
c0f3af97 8586 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
64a0c779
DN		 8587
8588 digits decdigit
b77a7acd
AJ		 8589 | digits decdigit
8590 | digits hexdigit
64a0c779
DN		 8591
8592 decdigit [0-9]
8593
9306ca4a
JB		 8594 e04 e04 addOp e05
8595 | e05
8596
8597 e05 e05 binOp e06
b77a7acd 8598 | e06
64a0c779
DN		 8599
8600 e06 e06 mulOp e09
b77a7acd 8601 | e09
64a0c779
DN		 8602
8603 e09 OFFSET e10
a724f0f4
JB		 8604 | SHORT e10
8605 | + e10
8606 | - e10
9306ca4a
JB		 8607 | ~ e10
8608 | NOT e10
64a0c779
DN		 8609 | e09 PTR e10
8610 | e09 : e10
8611 | e10
8612
8613 e10 e10 [ expr ]
b77a7acd 8614 | e11
64a0c779
DN		 8615
8616 e11 ( expr )
b77a7acd 8617 | [ expr ]
64a0c779
DN		 8618 | constant
8619 | dataType
8620 | id
8621 | $
8622 | register
8623
a724f0f4 8624 => expr expr cmpOp e04
9306ca4a 8625 | e04
64a0c779
DN		 8626
8627 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 8628 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 8629
8630 hexdigit a | b | c | d | e | f
b77a7acd 8631 | A | B | C | D | E | F
64a0c779
DN		 8632
8633 id alpha
b77a7acd 8634 | id alpha
64a0c779
DN		 8635 | id decdigit
8636
9306ca4a 8637 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 8638
8639 quote " | '
8640
8641 register specialRegister
b77a7acd 8642 | gpRegister
64a0c779
DN		 8643 | byteRegister
8644
8645 segmentRegister CS | DS | ES | FS | GS | SS
8646
9306ca4a 8647 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 8648 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 8649 | TR3 | TR4 | TR5 | TR6 | TR7
8650
64a0c779
DN		 8651 We simplify the grammar in obvious places (e.g., register parsing is
8652 done by calling parse_register) and eliminate immediate left recursion
8653 to implement a recursive-descent parser.
8654
a724f0f4
JB		 8655 expr e04 expr'
8656
8657 expr' cmpOp e04 expr'
8658 | Empty
9306ca4a
JB		 8659
8660 e04 e05 e04'
8661
8662 e04' addOp e05 e04'
8663 | Empty
64a0c779
DN		 8664
8665 e05 e06 e05'
8666
9306ca4a 8667 e05' binOp e06 e05'
b77a7acd 8668 | Empty
64a0c779
DN		 8669
8670 e06 e09 e06'
8671
8672 e06' mulOp e09 e06'
b77a7acd 8673 | Empty
64a0c779
DN		 8674
8675 e09 OFFSET e10 e09'
a724f0f4
JB		 8676 | SHORT e10'
8677 | + e10'
8678 | - e10'
8679 | ~ e10'
8680 | NOT e10'
b77a7acd 8681 | e10 e09'
64a0c779
DN		 8682
8683 e09' PTR e10 e09'
b77a7acd 8684 | : e10 e09'
64a0c779
DN		 8685 | Empty
8686
8687 e10 e11 e10'
8688
8689 e10' [ expr ] e10'
b77a7acd 8690 | Empty
64a0c779
DN		 8691
8692 e11 ( expr )
b77a7acd 8693 | [ expr ]
64a0c779
DN		 8694 | BYTE
8695 | WORD
8696 | DWORD
9306ca4a 8697 | FWORD
64a0c779 8698 | QWORD
9306ca4a
JB		 8699 | TBYTE
8700 | OWORD
8701 | XMMWORD
c0f3af97 8702 | YMMWORD
64a0c779
DN		 8703 | .
8704 | $
8705 | register
8706 | id
8707 | constant */
8708
8709/* Parsing structure for the intel syntax parser. Used to implement the
8710 semantic actions for the operand grammar. */
8711struct intel_parser_s
8712 {
8713 char *op_string; /* The string being parsed. */
8714 int got_a_float; /* Whether the operand is a float. */
4a1805b1 8715 int op_modifier; /* Operand modifier. */
64a0c779 8716 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 8717 int in_offset; /* >=1 if parsing operand of offset. */
8718 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 8719 const reg_entry *reg; /* Last register reference found. */
8720 char *disp; /* Displacement string being built. */
a724f0f4 8721 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 8722 };
8723
8724static struct intel_parser_s intel_parser;
8725
8726/* Token structure for parsing intel syntax. */
8727struct intel_token
8728 {
8729 int code; /* Token code. */
8730 const reg_entry *reg; /* Register entry for register tokens. */
8731 char *str; /* String representation. */
8732 };
8733
8734static struct intel_token cur_token, prev_token;
8735
50705ef4
AM		 8736/* Token codes for the intel parser. Since T_SHORT is already used
8737 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 8738#define T_NIL -1
8739#define T_CONST 1
8740#define T_REG 2
8741#define T_BYTE 3
8742#define T_WORD 4
9306ca4a
JB		 8743#define T_DWORD 5
8744#define T_FWORD 6
8745#define T_QWORD 7
8746#define T_TBYTE 8
8747#define T_XMMWORD 9
50705ef4 8748#undef T_SHORT
9306ca4a
JB		 8749#define T_SHORT 10
8750#define T_OFFSET 11
8751#define T_PTR 12
8752#define T_ID 13
8753#define T_SHL 14
8754#define T_SHR 15
c0f3af97 8755#define T_YMMWORD 16
64a0c779
DN		 8756
8757/* Prototypes for intel parser functions. */
e3bb37b5
L		 8758static int intel_match_token (int);
8759static void intel_putback_token (void);
8760static void intel_get_token (void);
8761static int intel_expr (void);
8762static int intel_e04 (void);
8763static int intel_e05 (void);
8764static int intel_e06 (void);
8765static int intel_e09 (void);
8766static int intel_e10 (void);
8767static int intel_e11 (void);
64a0c779 8768
64a0c779 8769static int
e3bb37b5 8770i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 8771{
8772 int ret;
8773 char *p;
8774
a724f0f4
JB		 8775 p = intel_parser.op_string = xstrdup (operand_string);
8776 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
8777
8778 for (;;)
64a0c779 8779 {
a724f0f4
JB		 8780 /* Initialize token holders. */
8781 cur_token.code = prev_token.code = T_NIL;
8782 cur_token.reg = prev_token.reg = NULL;
8783 cur_token.str = prev_token.str = NULL;
8784
8785 /* Initialize parser structure. */
8786 intel_parser.got_a_float = got_a_float;
8787 intel_parser.op_modifier = 0;
8788 intel_parser.is_mem = 0;
8789 intel_parser.in_offset = 0;
8790 intel_parser.in_bracket = 0;
8791 intel_parser.reg = NULL;
8792 intel_parser.disp[0] = '\0';
8793 intel_parser.next_operand = NULL;
8794
8795 /* Read the first token and start the parser. */
8796 intel_get_token ();
8797 ret = intel_expr ();
8798
8799 if (!ret)
8800 break;
8801
9306ca4a
JB		 8802 if (cur_token.code != T_NIL)
8803 {
8804 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8805 current_templates->start->name, cur_token.str);
8806 ret = 0;
8807 }
64a0c779
DN		 8808 /* If we found a memory reference, hand it over to i386_displacement
8809 to fill in the rest of the operand fields. */
9306ca4a 8810 else if (intel_parser.is_mem)
64a0c779
DN		 8811 {
8812 if ((i.mem_operands == 1
40fb9820 8813 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 8814 || i.mem_operands == 2)
8815 {
8816 as_bad (_("too many memory references for '%s'"),
8817 current_templates->start->name);
8818 ret = 0;
8819 }
8820 else
8821 {
8822 char *s = intel_parser.disp;
5c07affc 8823 i.types[this_operand].bitfield.mem = 1;
64a0c779
DN		 8824 i.mem_operands++;
8825
a724f0f4
JB		 8826 if (!quiet_warnings && intel_parser.is_mem < 0)
8827 /* See the comments in intel_bracket_expr. */
8828 as_warn (_("Treating `%s' as memory reference"), operand_string);
8829
64a0c779
DN		 8830 /* Add the displacement expression. */
8831 if (*s != '\0')
a4622f40
AM		 8832 ret = i386_displacement (s, s + strlen (s));
8833 if (ret)
a724f0f4
JB		 8834 {
8835 /* Swap base and index in 16-bit memory operands like
8836 [si+bx]. Since i386_index_check is also used in AT&T
8837 mode we have to do that here. */
8838 if (i.base_reg
8839 && i.index_reg
40fb9820
L		 8840 && i.base_reg->reg_type.bitfield.reg16
8841 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 8842 && i.base_reg->reg_num >= 6
8843 && i.index_reg->reg_num < 6)
8844 {
8845 const reg_entry *base = i.index_reg;
8846
8847 i.index_reg = i.base_reg;
8848 i.base_reg = base;
8849 }
8850 ret = i386_index_check (operand_string);
8851 }
64a0c779
DN		 8852 }
8853 }
8854
8855 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 8856 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779 8857 || intel_parser.reg == NULL)
b7240065
JB		 8858 {
8859 if (i.mem_operands < 2 && i.seg[i.mem_operands])
8860 {
8861 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8862 as_warn (_("Segment override ignored"));
8863 i.seg[i.mem_operands] = NULL;
8864 }
8865 ret = i386_immediate (intel_parser.disp);
8866 }
a724f0f4
JB		 8867
8868 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 8869 ret = 0;
a724f0f4
JB		 8870 if (!ret || !intel_parser.next_operand)
8871 break;
8872 intel_parser.op_string = intel_parser.next_operand;
8873 this_operand = i.operands++;
7d5e4556 8874 i.types[this_operand].bitfield.unspecified = 1;
64a0c779
DN		 8875 }
8876
8877 free (p);
8878 free (intel_parser.disp);
8879
8880 return ret;
8881}
8882
a724f0f4
JB		 8883#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8884
8885/* expr e04 expr'
8886
8887 expr' cmpOp e04 expr'
8888 | Empty */
64a0c779 8889static int
e3bb37b5 8890intel_expr (void)
64a0c779 8891{
a724f0f4
JB		 8892 /* XXX Implement the comparison operators. */
8893 return intel_e04 ();
9306ca4a
JB		 8894}
8895
a724f0f4 8896/* e04 e05 e04'
9306ca4a 8897
a724f0f4 8898 e04' addOp e05 e04'
9306ca4a
JB		 8899 | Empty */
8900static int
e3bb37b5 8901intel_e04 (void)
9306ca4a 8902{
a724f0f4 8903 int nregs = -1;
9306ca4a 8904
a724f0f4 8905 for (;;)
9306ca4a 8906 {
a724f0f4
JB		 8907 if (!intel_e05())
8908 return 0;
9306ca4a 8909
a724f0f4
JB		 8910 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8911 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 8912
a724f0f4
JB		 8913 if (cur_token.code == '+')
8914 nregs = -1;
8915 else if (cur_token.code == '-')
8916 nregs = NUM_ADDRESS_REGS;
8917 else
8918 return 1;
64a0c779 8919
a724f0f4
JB		 8920 strcat (intel_parser.disp, cur_token.str);
8921 intel_match_token (cur_token.code);
8922 }
64a0c779
DN		 8923}
8924
64a0c779
DN		 8925/* e05 e06 e05'
8926
9306ca4a 8927 e05' binOp e06 e05'
64a0c779
DN		 8928 | Empty */
8929static int
e3bb37b5 8930intel_e05 (void)
64a0c779 8931{
a724f0f4 8932 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 8933
a724f0f4 8934 for (;;)
64a0c779 8935 {
a724f0f4
JB		 8936 if (!intel_e06())
8937 return 0;
8938
4eed87de
AM		 8939 if (cur_token.code == '&'
8940 || cur_token.code == '|'
8941 || cur_token.code == '^')
a724f0f4
JB		 8942 {
8943 char str[2];
8944
8945 str[0] = cur_token.code;
8946 str[1] = 0;
8947 strcat (intel_parser.disp, str);
8948 }
8949 else
8950 break;
9306ca4a 8951
64a0c779
DN		 8952 intel_match_token (cur_token.code);
8953
a724f0f4
JB		 8954 if (nregs < 0)
8955 nregs = ~nregs;
64a0c779 8956 }
a724f0f4
JB		 8957 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8958 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
8959 return 1;
4a1805b1 8960}
64a0c779
DN		 8961
8962/* e06 e09 e06'
8963
8964 e06' mulOp e09 e06'
b77a7acd 8965 | Empty */
64a0c779 8966static int
e3bb37b5 8967intel_e06 (void)
64a0c779 8968{
a724f0f4 8969 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 8970
a724f0f4 8971 for (;;)
64a0c779 8972 {
a724f0f4
JB		 8973 if (!intel_e09())
8974 return 0;
9306ca4a 8975
4eed87de
AM		 8976 if (cur_token.code == '*'
8977 || cur_token.code == '/'
8978 || cur_token.code == '%')
a724f0f4
JB		 8979 {
8980 char str[2];
9306ca4a 8981
a724f0f4
JB		 8982 str[0] = cur_token.code;
8983 str[1] = 0;
8984 strcat (intel_parser.disp, str);
8985 }
8986 else if (cur_token.code == T_SHL)
8987 strcat (intel_parser.disp, "<<");
8988 else if (cur_token.code == T_SHR)
8989 strcat (intel_parser.disp, ">>");
8990 else
8991 break;
9306ca4a 8992
64e74474 8993 intel_match_token (cur_token.code);
64a0c779 8994
a724f0f4
JB		 8995 if (nregs < 0)
8996 nregs = ~nregs;
64a0c779 8997 }
a724f0f4
JB		 8998 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8999 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
9000 return 1;
64a0c779
DN		 9001}
9002
a724f0f4
JB		 9003/* e09 OFFSET e09
9004 | SHORT e09
9005 | + e09
9006 | - e09
9007 | ~ e09
9008 | NOT e09
9306ca4a
JB		 9009 | e10 e09'
9010
64a0c779 9011 e09' PTR e10 e09'
b77a7acd 9012 | : e10 e09'
64a0c779
DN		 9013 | Empty */
9014static int
e3bb37b5 9015intel_e09 (void)
64a0c779 9016{
a724f0f4
JB		 9017 int nregs = ~NUM_ADDRESS_REGS;
9018 int in_offset = 0;
9019
9020 for (;;)
64a0c779 9021 {
a724f0f4
JB		 9022 /* Don't consume constants here. */
9023 if (cur_token.code == '+' || cur_token.code == '-')
9024 {
9025 /* Need to look one token ahead - if the next token
9026 is a constant, the current token is its sign. */
9027 int next_code;
9028
9029 intel_match_token (cur_token.code);
9030 next_code = cur_token.code;
9031 intel_putback_token ();
9032 if (next_code == T_CONST)
9033 break;
9034 }
9035
9036 /* e09 OFFSET e09 */
9037 if (cur_token.code == T_OFFSET)
9038 {
9039 if (!in_offset++)
9040 ++intel_parser.in_offset;
9041 }
9042
9043 /* e09 SHORT e09 */
9044 else if (cur_token.code == T_SHORT)
9045 intel_parser.op_modifier |= 1 << T_SHORT;
9046
9047 /* e09 + e09 */
9048 else if (cur_token.code == '+')
9049 strcat (intel_parser.disp, "+");
9050
9051 /* e09 - e09
9052 | ~ e09
9053 | NOT e09 */
9054 else if (cur_token.code == '-' || cur_token.code == '~')
9055 {
9056 char str[2];
64a0c779 9057
a724f0f4
JB		 9058 if (nregs < 0)
9059 nregs = ~nregs;
9060 str[0] = cur_token.code;
9061 str[1] = 0;
9062 strcat (intel_parser.disp, str);
9063 }
9064
9065 /* e09 e10 e09' */
9066 else
9067 break;
9068
9069 intel_match_token (cur_token.code);
64a0c779
DN		 9070 }
9071
a724f0f4 9072 for (;;)
9306ca4a 9073 {
a724f0f4
JB		 9074 if (!intel_e10 ())
9075 return 0;
9306ca4a 9076
a724f0f4
JB		 9077 /* e09' PTR e10 e09' */
9078 if (cur_token.code == T_PTR)
9079 {
9080 char suffix;
9306ca4a 9081
a724f0f4 9082 if (prev_token.code == T_BYTE)
7d5e4556
L		 9083 {
9084 suffix = BYTE_MNEM_SUFFIX;
9085 i.types[this_operand].bitfield.byte = 1;
9086 }
9306ca4a 9087
a724f0f4
JB		 9088 else if (prev_token.code == T_WORD)
9089 {
34b772a6
JB		 9090 if ((current_templates->start->name[0] == 'l'
9091 && current_templates->start->name[2] == 's'
9092 && current_templates->start->name[3] == 0)
9093 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 9094 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9095 else if (intel_parser.got_a_float == 2) /* "fi..." */
9096 suffix = SHORT_MNEM_SUFFIX;
9097 else
9098 suffix = WORD_MNEM_SUFFIX;
7d5e4556 9099 i.types[this_operand].bitfield.word = 1;
a724f0f4 9100 }
64a0c779 9101
a724f0f4
JB		 9102 else if (prev_token.code == T_DWORD)
9103 {
34b772a6
JB		 9104 if ((current_templates->start->name[0] == 'l'
9105 && current_templates->start->name[2] == 's'
9106 && current_templates->start->name[3] == 0)
9107 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 9108 suffix = WORD_MNEM_SUFFIX;
9109 else if (flag_code == CODE_16BIT
40fb9820
L		 9110 && (current_templates->start->opcode_modifier.jump
9111 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 9112 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9113 else if (intel_parser.got_a_float == 1) /* "f..." */
9114 suffix = SHORT_MNEM_SUFFIX;
9115 else
9116 suffix = LONG_MNEM_SUFFIX;
7d5e4556 9117 i.types[this_operand].bitfield.dword = 1;
a724f0f4 9118 }
9306ca4a 9119
a724f0f4
JB		 9120 else if (prev_token.code == T_FWORD)
9121 {
9122 if (current_templates->start->name[0] == 'l'
9123 && current_templates->start->name[2] == 's'
9124 && current_templates->start->name[3] == 0)
9125 suffix = LONG_MNEM_SUFFIX;
9126 else if (!intel_parser.got_a_float)
9127 {
9128 if (flag_code == CODE_16BIT)
9129 add_prefix (DATA_PREFIX_OPCODE);
9130 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9131 }
9132 else
9133 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7d5e4556 9134 i.types[this_operand].bitfield.fword = 1;
a724f0f4 9135 }
64a0c779 9136
a724f0f4
JB		 9137 else if (prev_token.code == T_QWORD)
9138 {
34b772a6
JB		 9139 if (current_templates->start->base_opcode == 0x62 /* bound */
9140 || intel_parser.got_a_float == 1) /* "f..." */
a724f0f4
JB		 9141 suffix = LONG_MNEM_SUFFIX;
9142 else
34b772a6 9143 suffix = QWORD_MNEM_SUFFIX;
7d5e4556 9144 i.types[this_operand].bitfield.qword = 1;
a724f0f4 9145 }
64a0c779 9146
a724f0f4
JB		 9147 else if (prev_token.code == T_TBYTE)
9148 {
9149 if (intel_parser.got_a_float == 1)
9150 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9151 else
9152 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9153 }
9306ca4a 9154
a724f0f4 9155 else if (prev_token.code == T_XMMWORD)
9306ca4a 9156 {
582d5edd 9157 suffix = XMMWORD_MNEM_SUFFIX;
7d5e4556 9158 i.types[this_operand].bitfield.xmmword = 1;
9306ca4a 9159 }
64a0c779 9160
c0f3af97
L		 9161 else if (prev_token.code == T_YMMWORD)
9162 {
9163 suffix = YMMWORD_MNEM_SUFFIX;
9164 i.types[this_operand].bitfield.ymmword = 1;
9165 }
9166
f16b83df 9167 else
a724f0f4
JB		 9168 {
9169 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
9170 return 0;
9171 }
9172
7d5e4556
L		 9173 i.types[this_operand].bitfield.unspecified = 0;
9174
435acd52
JB		 9175 /* Operands for jump/call using 'ptr' notation denote absolute
9176 addresses. */
40fb9820
L		 9177 if (current_templates->start->opcode_modifier.jump
9178 || current_templates->start->opcode_modifier.jumpdword)
9179 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 9180
a724f0f4
JB		 9181 if (current_templates->start->base_opcode == 0x8d /* lea */)
9182 ;
9183 else if (!i.suffix)
9184 i.suffix = suffix;
9185 else if (i.suffix != suffix)
9186 {
9187 as_bad (_("Conflicting operand modifiers"));
9188 return 0;
9189 }
64a0c779 9190
9306ca4a
JB		 9191 }
9192
a724f0f4
JB		 9193 /* e09' : e10 e09' */
9194 else if (cur_token.code == ':')
9306ca4a 9195 {
a724f0f4
JB		 9196 if (prev_token.code != T_REG)
9197 {
9198 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9199 segment/group identifier (which we don't have), using comma
9200 as the operand separator there is even less consistent, since
9201 there all branches only have a single operand. */
9202 if (this_operand != 0
9203 || intel_parser.in_offset
9204 || intel_parser.in_bracket
40fb9820
L		 9205 || (!current_templates->start->opcode_modifier.jump
9206 && !current_templates->start->opcode_modifier.jumpdword
9207 && !current_templates->start->opcode_modifier.jumpintersegment
9208 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 9209 return intel_match_token (T_NIL);
9210 /* Remember the start of the 2nd operand and terminate 1st
9211 operand here.
9212 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9213 another expression), but it gets at least the simplest case
9214 (a plain number or symbol on the left side) right. */
9215 intel_parser.next_operand = intel_parser.op_string;
9216 *--intel_parser.op_string = '\0';
9217 return intel_match_token (':');
9218 }
9306ca4a 9219 }
64a0c779 9220
a724f0f4 9221 /* e09' Empty */
64a0c779 9222 else
a724f0f4 9223 break;
64a0c779 9224
a724f0f4
JB		 9225 intel_match_token (cur_token.code);
9226
9227 }
9228
9229 if (in_offset)
9230 {
9231 --intel_parser.in_offset;
9232 if (nregs < 0)
9233 nregs = ~nregs;
9234 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 9235 {
a724f0f4 9236 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 9237 return 0;
9238 }
a724f0f4
JB		 9239 intel_parser.op_modifier |= 1 << T_OFFSET;
9240 }
9306ca4a 9241
a724f0f4
JB		 9242 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9243 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
9244 return 1;
9245}
64a0c779 9246
a724f0f4 9247static int
e3bb37b5 9248intel_bracket_expr (void)
a724f0f4
JB		 9249{
9250 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
9251 const char *start = intel_parser.op_string;
9252 int len;
9253
9254 if (i.op[this_operand].regs)
9255 return intel_match_token (T_NIL);
9256
9257 intel_match_token ('[');
9258
9259 /* Mark as a memory operand only if it's not already known to be an
9260 offset expression. If it's an offset expression, we need to keep
9261 the brace in. */
9262 if (!intel_parser.in_offset)
9263 {
9264 ++intel_parser.in_bracket;
435acd52
JB		 9265
9266 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 9267 if (current_templates->start->opcode_modifier.jump
9268 || current_templates->start->opcode_modifier.jumpdword)
9269 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 9270
a724f0f4
JB		 9271 /* Unfortunately gas always diverged from MASM in a respect that can't
9272 be easily fixed without risking to break code sequences likely to be
9273 encountered (the testsuite even check for this): MASM doesn't consider
9274 an expression inside brackets unconditionally as a memory reference.
9275 When that is e.g. a constant, an offset expression, or the sum of the
9276 two, this is still taken as a constant load. gas, however, always
9277 treated these as memory references. As a compromise, we'll try to make
9278 offset expressions inside brackets work the MASM way (since that's
9279 less likely to be found in real world code), but make constants alone
9280 continue to work the traditional gas way. In either case, issue a
9281 warning. */
9282 intel_parser.op_modifier &= ~was_offset;
64a0c779 9283 }
a724f0f4 9284 else
64e74474 9285 strcat (intel_parser.disp, "[");
a724f0f4
JB		 9286
9287 /* Add a '+' to the displacement string if necessary. */
9288 if (*intel_parser.disp != '\0'
9289 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
9290 strcat (intel_parser.disp, "+");
64a0c779 9291
a724f0f4
JB		 9292 if (intel_expr ()
9293 && (len = intel_parser.op_string - start - 1,
9294 intel_match_token (']')))
64a0c779 9295 {
a724f0f4
JB		 9296 /* Preserve brackets when the operand is an offset expression. */
9297 if (intel_parser.in_offset)
9298 strcat (intel_parser.disp, "]");
9299 else
9300 {
9301 --intel_parser.in_bracket;
9302 if (i.base_reg || i.index_reg)
9303 intel_parser.is_mem = 1;
9304 if (!intel_parser.is_mem)
9305 {
9306 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
9307 /* Defer the warning until all of the operand was parsed. */
9308 intel_parser.is_mem = -1;
9309 else if (!quiet_warnings)
4eed87de
AM		 9310 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9311 len, start, len, start);
a724f0f4
JB		 9312 }
9313 }
9314 intel_parser.op_modifier |= was_offset;
64a0c779 9315
a724f0f4 9316 return 1;
64a0c779 9317 }
a724f0f4 9318 return 0;
64a0c779
DN		 9319}
9320
9321/* e10 e11 e10'
9322
9323 e10' [ expr ] e10'
b77a7acd 9324 | Empty */
64a0c779 9325static int
e3bb37b5 9326intel_e10 (void)
64a0c779 9327{
a724f0f4
JB		 9328 if (!intel_e11 ())
9329 return 0;
64a0c779 9330
a724f0f4 9331 while (cur_token.code == '[')
64a0c779 9332 {
a724f0f4 9333 if (!intel_bracket_expr ())
21d6c4af 9334 return 0;
64a0c779
DN		 9335 }
9336
a724f0f4 9337 return 1;
64a0c779
DN		 9338}
9339
64a0c779 9340/* e11 ( expr )
b77a7acd 9341 | [ expr ]
64a0c779
DN		 9342 | BYTE
9343 | WORD
9344 | DWORD
9306ca4a 9345 | FWORD
64a0c779 9346 | QWORD
9306ca4a
JB		 9347 | TBYTE
9348 | OWORD
9349 | XMMWORD
c0f3af97 9350 | YMMWORD
4a1805b1 9351 | $
64a0c779
DN		 9352 | .
9353 | register
9354 | id
9355 | constant */
9356static int
e3bb37b5 9357intel_e11 (void)
64a0c779 9358{
a724f0f4 9359 switch (cur_token.code)
64a0c779 9360 {
a724f0f4
JB		 9361 /* e11 ( expr ) */
9362 case '(':
64a0c779
DN		 9363 intel_match_token ('(');
9364 strcat (intel_parser.disp, "(");
9365
9366 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 9367 {
9368 strcat (intel_parser.disp, ")");
9369 return 1;
9370 }
a724f0f4 9371 return 0;
4a1805b1 9372
a724f0f4
JB		 9373 /* e11 [ expr ] */
9374 case '[':
a724f0f4 9375 return intel_bracket_expr ();
64a0c779 9376
a724f0f4
JB		 9377 /* e11 $
9378 | . */
9379 case '.':
64a0c779
DN		 9380 strcat (intel_parser.disp, cur_token.str);
9381 intel_match_token (cur_token.code);
21d6c4af
DN		 9382
9383 /* Mark as a memory operand only if it's not already known to be an
9384 offset expression. */
a724f0f4 9385 if (!intel_parser.in_offset)
21d6c4af 9386 intel_parser.is_mem = 1;
64a0c779
DN		 9387
9388 return 1;
64a0c779 9389
a724f0f4
JB		 9390 /* e11 register */
9391 case T_REG:
9392 {
9393 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 9394
a724f0f4 9395 intel_match_token (T_REG);
64a0c779 9396
a724f0f4
JB		 9397 /* Check for segment change. */
9398 if (cur_token.code == ':')
9399 {
40fb9820
L		 9400 if (!reg->reg_type.bitfield.sreg2
9401 && !reg->reg_type.bitfield.sreg3)
a724f0f4 9402 {
4eed87de
AM		 9403 as_bad (_("`%s' is not a valid segment register"),
9404 reg->reg_name);
a724f0f4
JB		 9405 return 0;
9406 }
b7240065
JB		 9407 else if (i.mem_operands >= 2)
9408 as_warn (_("Segment override ignored"));
a724f0f4
JB		 9409 else if (i.seg[i.mem_operands])
9410 as_warn (_("Extra segment override ignored"));
9411 else
9412 {
9413 if (!intel_parser.in_offset)
9414 intel_parser.is_mem = 1;
9415 switch (reg->reg_num)
9416 {
9417 case 0:
9418 i.seg[i.mem_operands] = &es;
9419 break;
9420 case 1:
9421 i.seg[i.mem_operands] = &cs;
9422 break;
9423 case 2:
9424 i.seg[i.mem_operands] = &ss;
9425 break;
9426 case 3:
9427 i.seg[i.mem_operands] = &ds;
9428 break;
9429 case 4:
9430 i.seg[i.mem_operands] = &fs;
9431 break;
9432 case 5:
9433 i.seg[i.mem_operands] = &gs;
9434 break;
9435 }
9436 }
9437 }
64a0c779 9438
b7240065
JB		 9439 else if (reg->reg_type.bitfield.sreg3 && reg->reg_num == RegFlat)
9440 {
9441 as_bad (_("cannot use `FLAT' here"));
9442 return 0;
9443 }
9444
a724f0f4
JB		 9445 /* Not a segment register. Check for register scaling. */
9446 else if (cur_token.code == '*')
9447 {
9448 if (!intel_parser.in_bracket)
9449 {
9450 as_bad (_("Register scaling only allowed in memory operands"));
9451 return 0;
9452 }
64a0c779 9453
40fb9820 9454 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 9455 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
9456 else if (i.index_reg)
9457 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 9458
a724f0f4
JB		 9459 /* What follows must be a valid scale. */
9460 intel_match_token ('*');
9461 i.index_reg = reg;
40fb9820 9462 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 9463
a724f0f4
JB		 9464 /* Set the scale after setting the register (otherwise,
9465 i386_scale will complain) */
9466 if (cur_token.code == '+' || cur_token.code == '-')
9467 {
9468 char *str, sign = cur_token.code;
9469 intel_match_token (cur_token.code);
9470 if (cur_token.code != T_CONST)
9471 {
9472 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9473 cur_token.str);
9474 return 0;
9475 }
9476 str = (char *) xmalloc (strlen (cur_token.str) + 2);
9477 strcpy (str + 1, cur_token.str);
9478 *str = sign;
9479 if (!i386_scale (str))
9480 return 0;
9481 free (str);
9482 }
9483 else if (!i386_scale (cur_token.str))
64a0c779 9484 return 0;
a724f0f4
JB		 9485 intel_match_token (cur_token.code);
9486 }
64a0c779 9487
a724f0f4
JB		 9488 /* No scaling. If this is a memory operand, the register is either a
9489 base register (first occurrence) or an index register (second
9490 occurrence). */
7b0441f6 9491 else if (intel_parser.in_bracket)
a724f0f4 9492 {
64a0c779 9493
a724f0f4
JB		 9494 if (!i.base_reg)
9495 i.base_reg = reg;
9496 else if (!i.index_reg)
9497 i.index_reg = reg;
9498 else
9499 {
9500 as_bad (_("Too many register references in memory operand"));
9501 return 0;
9502 }
64a0c779 9503
40fb9820 9504 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 9505 }
4a1805b1 9506
4d1bb795
JB		 9507 /* It's neither base nor index. */
9508 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 9509 {
40fb9820
L		 9510 i386_operand_type temp = reg->reg_type;
9511 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9512 i.types[this_operand] = operand_type_or (i.types[this_operand],
9513 temp);
7d5e4556 9514 i.types[this_operand].bitfield.unspecified = 0;
a724f0f4
JB		 9515 i.op[this_operand].regs = reg;
9516 i.reg_operands++;
9517 }
9518 else
9519 {
9520 as_bad (_("Invalid use of register"));
9521 return 0;
9522 }
64a0c779 9523
a724f0f4
JB		 9524 /* Since registers are not part of the displacement string (except
9525 when we're parsing offset operands), we may need to remove any
9526 preceding '+' from the displacement string. */
9527 if (*intel_parser.disp != '\0'
9528 && !intel_parser.in_offset)
9529 {
9530 char *s = intel_parser.disp;
9531 s += strlen (s) - 1;
9532 if (*s == '+')
9533 *s = '\0';
9534 }
4a1805b1 9535
a724f0f4
JB		 9536 return 1;
9537 }
9538
9539 /* e11 BYTE
9540 | WORD
9541 | DWORD
9542 | FWORD
9543 | QWORD
9544 | TBYTE
9545 | OWORD
c0f3af97
L		 9546 | XMMWORD
9547 | YMMWORD */
a724f0f4
JB		 9548 case T_BYTE:
9549 case T_WORD:
9550 case T_DWORD:
9551 case T_FWORD:
9552 case T_QWORD:
9553 case T_TBYTE:
9554 case T_XMMWORD:
c0f3af97 9555 case T_YMMWORD:
a724f0f4 9556 intel_match_token (cur_token.code);
64a0c779 9557
a724f0f4
JB		 9558 if (cur_token.code == T_PTR)
9559 return 1;
9560
9561 /* It must have been an identifier. */
9562 intel_putback_token ();
9563 cur_token.code = T_ID;
9564 /* FALLTHRU */
9565
9566 /* e11 id
9567 | constant */
9568 case T_ID:
9569 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 9570 {
9571 symbolS *symbolP;
9572
a724f0f4
JB		 9573 /* The identifier represents a memory reference only if it's not
9574 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 9575 symbolP = symbol_find(cur_token.str);
9576 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
9577 intel_parser.is_mem = 1;
9578 }
a724f0f4 9579 /* FALLTHRU */
64a0c779 9580
a724f0f4
JB		 9581 case T_CONST:
9582 case '-':
9583 case '+':
9584 {
9585 char *save_str, sign = 0;
64a0c779 9586
a724f0f4
JB		 9587 /* Allow constants that start with `+' or `-'. */
9588 if (cur_token.code == '-' || cur_token.code == '+')
9589 {
9590 sign = cur_token.code;
9591 intel_match_token (cur_token.code);
9592 if (cur_token.code != T_CONST)
9593 {
9594 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9595 cur_token.str);
9596 return 0;
9597 }
9598 }
64a0c779 9599
a724f0f4
JB		 9600 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
9601 strcpy (save_str + !!sign, cur_token.str);
9602 if (sign)
9603 *save_str = sign;
64a0c779 9604
a724f0f4
JB		 9605 /* Get the next token to check for register scaling. */
9606 intel_match_token (cur_token.code);
64a0c779 9607
4eed87de
AM		 9608 /* Check if this constant is a scaling factor for an
9609 index register. */
a724f0f4
JB		 9610 if (cur_token.code == '*')
9611 {
9612 if (intel_match_token ('*') && cur_token.code == T_REG)
9613 {
9614 const reg_entry *reg = cur_token.reg;
9615
9616 if (!intel_parser.in_bracket)
9617 {
4eed87de
AM		 9618 as_bad (_("Register scaling only allowed "
9619 "in memory operands"));
a724f0f4
JB		 9620 return 0;
9621 }
9622
4eed87de
AM		 9623 /* Disallow things like [1*si].
9624 sp and esp are invalid as index. */
40fb9820 9625 if (reg->reg_type.bitfield.reg16)
4eed87de 9626 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 9627 else if (i.index_reg)
4eed87de 9628 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 9629
9630 /* The constant is followed by `* reg', so it must be
9631 a valid scale. */
9632 i.index_reg = reg;
40fb9820 9633 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 9634
9635 /* Set the scale after setting the register (otherwise,
9636 i386_scale will complain) */
9637 if (!i386_scale (save_str))
64a0c779 9638 return 0;
a724f0f4
JB		 9639 intel_match_token (T_REG);
9640
9641 /* Since registers are not part of the displacement
9642 string, we may need to remove any preceding '+' from
9643 the displacement string. */
9644 if (*intel_parser.disp != '\0')
9645 {
9646 char *s = intel_parser.disp;
9647 s += strlen (s) - 1;
9648 if (*s == '+')
9649 *s = '\0';
9650 }
9651
9652 free (save_str);
9653
9654 return 1;
9655 }
64a0c779 9656
a724f0f4
JB		 9657 /* The constant was not used for register scaling. Since we have
9658 already consumed the token following `*' we now need to put it
9659 back in the stream. */
64a0c779 9660 intel_putback_token ();
a724f0f4 9661 }
64a0c779 9662
a724f0f4
JB		 9663 /* Add the constant to the displacement string. */
9664 strcat (intel_parser.disp, save_str);
9665 free (save_str);
64a0c779 9666
a724f0f4
JB		 9667 return 1;
9668 }
64a0c779
DN		 9669 }
9670
64a0c779
DN		 9671 as_bad (_("Unrecognized token '%s'"), cur_token.str);
9672 return 0;
9673}
9674
64a0c779
DN		 9675/* Match the given token against cur_token. If they match, read the next
9676 token from the operand string. */
9677static int
e3bb37b5 9678intel_match_token (int code)
64a0c779
DN		 9679{
9680 if (cur_token.code == code)
9681 {
9682 intel_get_token ();
9683 return 1;
9684 }
9685 else
9686 {
0477af35 9687 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 9688 return 0;
9689 }
9690}
9691
64a0c779
DN		 9692/* Read a new token from intel_parser.op_string and store it in cur_token. */
9693static void
e3bb37b5 9694intel_get_token (void)
64a0c779
DN		 9695{
9696 char *end_op;
9697 const reg_entry *reg;
9698 struct intel_token new_token;
9699
9700 new_token.code = T_NIL;
9701 new_token.reg = NULL;
9702 new_token.str = NULL;
9703
4a1805b1 9704 /* Free the memory allocated to the previous token and move
64a0c779
DN		 9705 cur_token to prev_token. */
9706 if (prev_token.str)
9707 free (prev_token.str);
9708
9709 prev_token = cur_token;
9710
9711 /* Skip whitespace. */
9712 while (is_space_char (*intel_parser.op_string))
9713 intel_parser.op_string++;
9714
9715 /* Return an empty token if we find nothing else on the line. */
9716 if (*intel_parser.op_string == '\0')
9717 {
9718 cur_token = new_token;
9719 return;
9720 }
9721
9722 /* The new token cannot be larger than the remainder of the operand
9723 string. */
a724f0f4 9724 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 9725 new_token.str[0] = '\0';
9726
9727 if (strchr ("0123456789", *intel_parser.op_string))
9728 {
9729 char *p = new_token.str;
9730 char *q = intel_parser.op_string;
9731 new_token.code = T_CONST;
9732
9733 /* Allow any kind of identifier char to encompass floating point and
9734 hexadecimal numbers. */
9735 while (is_identifier_char (*q))
9736 *p++ = *q++;
9737 *p = '\0';
9738
9739 /* Recognize special symbol names [0-9][bf]. */
9740 if (strlen (intel_parser.op_string) == 2
4a1805b1 9741 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 9742 || intel_parser.op_string[1] == 'f'))
9743 new_token.code = T_ID;
9744 }
9745
4d1bb795 9746 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 9747 {
4d1bb795
JB		 9748 size_t len = end_op - intel_parser.op_string;
9749
64a0c779
DN		 9750 new_token.code = T_REG;
9751 new_token.reg = reg;
9752
4d1bb795
JB		 9753 memcpy (new_token.str, intel_parser.op_string, len);
9754 new_token.str[len] = '\0';
64a0c779
DN		 9755 }
9756
9757 else if (is_identifier_char (*intel_parser.op_string))
9758 {
9759 char *p = new_token.str;
9760 char *q = intel_parser.op_string;
9761
9762 /* A '.' or '$' followed by an identifier char is an identifier.
9763 Otherwise, it's operator '.' followed by an expression. */
9764 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
9765 {
9306ca4a
JB		 9766 new_token.code = '.';
9767 new_token.str[0] = '.';
64a0c779
DN		 9768 new_token.str[1] = '\0';
9769 }
9770 else
9771 {
9772 while (is_identifier_char (*q) || *q == '@')
9773 *p++ = *q++;
9774 *p = '\0';
9775
9306ca4a
JB		 9776 if (strcasecmp (new_token.str, "NOT") == 0)
9777 new_token.code = '~';
9778
9779 else if (strcasecmp (new_token.str, "MOD") == 0)
9780 new_token.code = '%';
9781
9782 else if (strcasecmp (new_token.str, "AND") == 0)
9783 new_token.code = '&';
9784
9785 else if (strcasecmp (new_token.str, "OR") == 0)
9786 new_token.code = '|';
9787
9788 else if (strcasecmp (new_token.str, "XOR") == 0)
9789 new_token.code = '^';
9790
9791 else if (strcasecmp (new_token.str, "SHL") == 0)
9792 new_token.code = T_SHL;
9793
9794 else if (strcasecmp (new_token.str, "SHR") == 0)
9795 new_token.code = T_SHR;
9796
9797 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 9798 new_token.code = T_BYTE;
9799
9800 else if (strcasecmp (new_token.str, "WORD") == 0)
9801 new_token.code = T_WORD;
9802
9803 else if (strcasecmp (new_token.str, "DWORD") == 0)
9804 new_token.code = T_DWORD;
9805
9306ca4a
JB		 9806 else if (strcasecmp (new_token.str, "FWORD") == 0)
9807 new_token.code = T_FWORD;
9808
64a0c779
DN		 9809 else if (strcasecmp (new_token.str, "QWORD") == 0)
9810 new_token.code = T_QWORD;
9811
9306ca4a
JB		 9812 else if (strcasecmp (new_token.str, "TBYTE") == 0
9813 /* XXX remove (gcc still uses it) */
9814 || strcasecmp (new_token.str, "XWORD") == 0)
9815 new_token.code = T_TBYTE;
9816
9817 else if (strcasecmp (new_token.str, "XMMWORD") == 0
9818 || strcasecmp (new_token.str, "OWORD") == 0)
9819 new_token.code = T_XMMWORD;
64a0c779 9820
c0f3af97
L		 9821 else if (strcasecmp (new_token.str, "YMMWORD") == 0)
9822 new_token.code = T_YMMWORD;
9823
64a0c779
DN		 9824 else if (strcasecmp (new_token.str, "PTR") == 0)
9825 new_token.code = T_PTR;
9826
9827 else if (strcasecmp (new_token.str, "SHORT") == 0)
9828 new_token.code = T_SHORT;
9829
9830 else if (strcasecmp (new_token.str, "OFFSET") == 0)
9831 {
9832 new_token.code = T_OFFSET;
9833
9834 /* ??? This is not mentioned in the MASM grammar but gcc
9835 makes use of it with -mintel-syntax. OFFSET may be
9836 followed by FLAT: */
9837 if (strncasecmp (q, " FLAT:", 6) == 0)
9838 strcat (new_token.str, " FLAT:");
9839 }
9840
64a0c779
DN		 9841 else
9842 new_token.code = T_ID;
9843 }
9844 }
9845
9306ca4a
JB		 9846 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
9847 {
9848 new_token.code = *intel_parser.op_string;
9849 new_token.str[0] = *intel_parser.op_string;
9850 new_token.str[1] = '\0';
9851 }
9852
9853 else if (strchr ("<>", *intel_parser.op_string)
9854 && *intel_parser.op_string == *(intel_parser.op_string + 1))
9855 {
9856 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
9857 new_token.str[0] = *intel_parser.op_string;
9858 new_token.str[1] = *intel_parser.op_string;
9859 new_token.str[2] = '\0';
9860 }
9861
64a0c779 9862 else
0477af35 9863 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 9864
9865 intel_parser.op_string += strlen (new_token.str);
9866 cur_token = new_token;
9867}
9868
64a0c779
DN		 9869/* Put cur_token back into the token stream and make cur_token point to
9870 prev_token. */
9871static void
e3bb37b5 9872intel_putback_token (void)
64a0c779 9873{
a724f0f4
JB		 9874 if (cur_token.code != T_NIL)
9875 {
9876 intel_parser.op_string -= strlen (cur_token.str);
9877 free (cur_token.str);
9878 }
64a0c779 9879 cur_token = prev_token;
4a1805b1 9880
64a0c779
DN		 9881 /* Forget prev_token. */
9882 prev_token.code = T_NIL;
9883 prev_token.reg = NULL;
9884 prev_token.str = NULL;
9885}
54cfded0 9886
a60de03c
JB		 9887void
9888tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 9889{
a60de03c
JB		 9890 int saved_naked_reg;
9891 char saved_register_dot;
54cfded0 9892
a60de03c
JB		 9893 saved_naked_reg = allow_naked_reg;
9894 allow_naked_reg = 1;
9895 saved_register_dot = register_chars['.'];
9896 register_chars['.'] = '.';
9897 allow_pseudo_reg = 1;
9898 expression_and_evaluate (exp);
9899 allow_pseudo_reg = 0;
9900 register_chars['.'] = saved_register_dot;
9901 allow_naked_reg = saved_naked_reg;
9902
9903 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 9904 {
a60de03c
JB		 9905 if ((addressT) exp->X_add_number < i386_regtab_size)
9906 {
9907 exp->X_op = O_constant;
9908 exp->X_add_number = i386_regtab[exp->X_add_number]
9909 .dw2_regnum[flag_code >> 1];
9910 }
9911 else
9912 exp->X_op = O_illegal;
54cfded0 9913 }
54cfded0
AM		 9914}
9915
9916void
9917tc_x86_frame_initial_instructions (void)
9918{
a60de03c
JB		 9919 static unsigned int sp_regno[2];
9920
9921 if (!sp_regno[flag_code >> 1])
9922 {
9923 char *saved_input = input_line_pointer;
9924 char sp[][4] = {"esp", "rsp"};
9925 expressionS exp;
a4447b93 9926
a60de03c
JB		 9927 input_line_pointer = sp[flag_code >> 1];
9928 tc_x86_parse_to_dw2regnum (&exp);
9929 assert (exp.X_op == O_constant);
9930 sp_regno[flag_code >> 1] = exp.X_add_number;
9931 input_line_pointer = saved_input;
9932 }
a4447b93 9933
a60de03c 9934 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 9935 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 9936}
d2b2c203
DJ		 9937
9938int
9939i386_elf_section_type (const char *str, size_t len)
9940{
9941 if (flag_code == CODE_64BIT
9942 && len == sizeof ("unwind") - 1
9943 && strncmp (str, "unwind", 6) == 0)
9944 return SHT_X86_64_UNWIND;
9945
9946 return -1;
9947}
bb41ade5
AM		 9948
9949#ifdef TE_PE
9950void
9951tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9952{
9953 expressionS expr;
9954
9955 expr.X_op = O_secrel;
9956 expr.X_add_symbol = symbol;
9957 expr.X_add_number = 0;
9958 emit_expr (&expr, size);
9959}
9960#endif
3b22753a
L		 9961
9962#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9963/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9964
9965int
9966x86_64_section_letter (int letter, char **ptr_msg)
9967{
9968 if (flag_code == CODE_64BIT)
9969 {
9970 if (letter == 'l')
9971 return SHF_X86_64_LARGE;
9972
9973 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9974 }
3b22753a 9975 else
64e74474 9976 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9977 return -1;
9978}
9979
9980int
9981x86_64_section_word (char *str, size_t len)
9982{
8620418b 9983 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9984 return SHF_X86_64_LARGE;
9985
9986 return -1;
9987}
9988
9989static void
9990handle_large_common (int small ATTRIBUTE_UNUSED)
9991{
9992 if (flag_code != CODE_64BIT)
9993 {
9994 s_comm_internal (0, elf_common_parse);
9995 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9996 }
9997 else
9998 {
9999 static segT lbss_section;
10000 asection *saved_com_section_ptr = elf_com_section_ptr;
10001 asection *saved_bss_section = bss_section;
10002
10003 if (lbss_section == NULL)
10004 {
10005 flagword applicable;
10006 segT seg = now_seg;
10007 subsegT subseg = now_subseg;
10008
10009 /* The .lbss section is for local .largecomm symbols. */
10010 lbss_section = subseg_new (".lbss", 0);
10011 applicable = bfd_applicable_section_flags (stdoutput);
10012 bfd_set_section_flags (stdoutput, lbss_section,
10013 applicable & SEC_ALLOC);
10014 seg_info (lbss_section)->bss = 1;
10015
10016 subseg_set (seg, subseg);
10017 }
10018
10019 elf_com_section_ptr = &_bfd_elf_large_com_section;
10020 bss_section = lbss_section;
10021
10022 s_comm_internal (0, elf_common_parse);
10023
10024 elf_com_section_ptr = saved_com_section_ptr;
10025 bss_section = saved_bss_section;
10026 }
10027}
10028#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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