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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
4b95cf5c 2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
22109423 136 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 137}
138arch_entry;
139
78f12dd3 140static void update_code_flag (int, int);
e3bb37b5
L		 141static void set_code_flag (int);
142static void set_16bit_gcc_code_flag (int);
143static void set_intel_syntax (int);
1efbbeb4 144static void set_intel_mnemonic (int);
db51cc60 145static void set_allow_index_reg (int);
7bab8ab5 146static void set_check (int);
e3bb37b5 147static void set_cpu_arch (int);
6482c264 148#ifdef TE_PE
e3bb37b5 149static void pe_directive_secrel (int);
6482c264 150#endif
e3bb37b5
L		 151static void signed_cons (int);
152static char *output_invalid (int c);
ee86248c
JB		 153static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
154 const char *);
155static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
156 const char *);
a7619375 157static int i386_att_operand (char *);
e3bb37b5 158static int i386_intel_operand (char *, int);
ee86248c
JB		 159static int i386_intel_simplify (expressionS *);
160static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 161static const reg_entry *parse_register (char *, char **);
162static char *parse_insn (char *, char *);
163static char *parse_operands (char *, const char *);
164static void swap_operands (void);
4d456e3d 165static void swap_2_operands (int, int);
e3bb37b5
L		 166static void optimize_imm (void);
167static void optimize_disp (void);
d3ce72d0 168static const insn_template *match_template (void);
e3bb37b5
L		 169static int check_string (void);
170static int process_suffix (void);
171static int check_byte_reg (void);
172static int check_long_reg (void);
173static int check_qword_reg (void);
174static int check_word_reg (void);
175static int finalize_imm (void);
176static int process_operands (void);
177static const seg_entry *build_modrm_byte (void);
178static void output_insn (void);
179static void output_imm (fragS *, offsetT);
180static void output_disp (fragS *, offsetT);
29b0f896 181#ifndef I386COFF
e3bb37b5 182static void s_bss (int);
252b5132 183#endif
17d4e2a2
L		 184#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185static void handle_large_common (int small ATTRIBUTE_UNUSED);
186#endif
252b5132 187
a847613f 188static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 189
43234a1e
L		 190/* This struct describes rounding control and SAE in the instruction. */
191struct RC_Operation
192{
193 enum rc_type
194 {
195 rne = 0,
196 rd,
197 ru,
198 rz,
199 saeonly
200 } type;
201 int operand;
202};
203
204static struct RC_Operation rc_op;
205
206/* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209struct Mask_Operation
210{
211 const reg_entry *mask;
212 unsigned int zeroing;
213 /* The operand where this operation is associated. */
214 int operand;
215};
216
217static struct Mask_Operation mask_op;
218
219/* The struct describes broadcasting, applied to OPERAND. FACTOR is
220 broadcast factor. */
221struct Broadcast_Operation
222{
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
224 int type;
225
226 /* Index of broadcasted operand. */
227 int operand;
228};
229
230static struct Broadcast_Operation broadcast_op;
231
c0f3af97
L		 232/* VEX prefix. */
233typedef struct
234{
43234a1e
L		 235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes[4];
c0f3af97
L		 237 unsigned int length;
238 /* Destination or source register specifier. */
239 const reg_entry *register_specifier;
240} vex_prefix;
241
252b5132 242/* 'md_assemble ()' gathers together information and puts it into a
47926f60 243 i386_insn. */
252b5132 244
520dc8e8
AM		 245union i386_op
246 {
247 expressionS *disps;
248 expressionS *imms;
249 const reg_entry *regs;
250 };
251
a65babc9
L		 252enum i386_error
253 {
86e026a4 254 operand_size_mismatch,
a65babc9
L		 255 operand_type_mismatch,
256 register_type_mismatch,
257 number_of_operands_mismatch,
258 invalid_instruction_suffix,
259 bad_imm4,
260 old_gcc_only,
261 unsupported_with_intel_mnemonic,
262 unsupported_syntax,
6c30d220
L		 263 unsupported,
264 invalid_vsib_address,
7bab8ab5 265 invalid_vector_register_set,
43234a1e
L		 266 unsupported_vector_index_register,
267 unsupported_broadcast,
268 broadcast_not_on_src_operand,
269 broadcast_needed,
270 unsupported_masking,
271 mask_not_on_destination,
272 no_default_mask,
273 unsupported_rc_sae,
274 rc_sae_operand_not_last_imm,
275 invalid_register_operand,
276 try_vector_disp8
a65babc9
L		 277 };
278
252b5132
RH		 279struct _i386_insn
280 {
47926f60 281 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 282 insn_template tm;
252b5132 283
7d5e4556
L		 284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
252b5132
RH		 286 char suffix;
287
47926f60 288 /* OPERANDS gives the number of given operands. */
252b5132
RH		 289 unsigned int operands;
290
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
47926f60 293 operands. */
252b5132
RH		 294 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
295
296 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 297 use OP[i] for the corresponding operand. */
40fb9820 298 i386_operand_type types[MAX_OPERANDS];
252b5132 299
520dc8e8
AM		 300 /* Displacement expression, immediate expression, or register for each
301 operand. */
302 union i386_op op[MAX_OPERANDS];
252b5132 303
3e73aa7c
JH		 304 /* Flags for operands. */
305 unsigned int flags[MAX_OPERANDS];
306#define Operand_PCrel 1
307
252b5132 308 /* Relocation type for operand */
f86103b7 309 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 310
252b5132
RH		 311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry *base_reg;
314 const reg_entry *index_reg;
315 unsigned int log2_scale_factor;
316
317 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 318 explicit segment overrides are given. */
ce8a8b2f 319 const seg_entry *seg[2];
252b5132
RH		 320
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes;
324 unsigned char prefix[MAX_PREFIXES];
325
326 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 327 addressing modes of this insn are encoded. */
252b5132 328 modrm_byte rm;
3e73aa7c 329 rex_byte rex;
43234a1e 330 rex_byte vrex;
252b5132 331 sib_byte sib;
c0f3af97 332 vex_prefix vex;
b6169b20 333
43234a1e
L		 334 /* Masking attributes. */
335 struct Mask_Operation *mask;
336
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation *rounding;
339
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation *broadcast;
342
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift;
345
b6169b20 346 /* Swap operand in encoding. */
4473e004 347 unsigned int swap_operand;
891edac4 348
a501d77e
L		 349 /* Prefer 8bit or 32bit displacement in encoding. */
350 enum
351 {
352 disp_encoding_default = 0,
353 disp_encoding_8bit,
354 disp_encoding_32bit
355 } disp_encoding;
f8a5c266 356
d5de92cf
L		 357 /* REP prefix. */
358 const char *rep_prefix;
359
165de32a
L		 360 /* HLE prefix. */
361 const char *hle_prefix;
42164a71 362
7e8b059b
L		 363 /* Have BND prefix. */
364 const char *bnd_prefix;
365
43234a1e
L		 366 /* Need VREX to support upper 16 registers. */
367 int need_vrex;
368
891edac4 369 /* Error message. */
a65babc9 370 enum i386_error error;
252b5132
RH		 371 };
372
373typedef struct _i386_insn i386_insn;
374
43234a1e
L		 375/* Link RC type with corresponding string, that'll be looked for in
376 asm. */
377struct RC_name
378{
379 enum rc_type type;
380 const char *name;
381 unsigned int len;
382};
383
384static const struct RC_name RC_NamesTable[] =
385{
386 { rne, STRING_COMMA_LEN ("rn-sae") },
387 { rd, STRING_COMMA_LEN ("rd-sae") },
388 { ru, STRING_COMMA_LEN ("ru-sae") },
389 { rz, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly, STRING_COMMA_LEN ("sae") },
391};
392
252b5132
RH		 393/* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 395const char extra_symbol_chars[] = "*%-([{"
252b5132 396#ifdef LEX_AT
32137342
NC		 397 "@"
398#endif
399#ifdef LEX_QM
400 "?"
252b5132 401#endif
32137342 402 ;
252b5132 403
29b0f896
AM		 404#if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 406 && !defined (TE_GNU) \
29b0f896 407 && !defined (TE_LINUX) \
8d63c93e
RM		 408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
29b0f896 410 && !defined (TE_FreeBSD) \
5b806d27 411 && !defined (TE_DragonFly) \
29b0f896 412 && !defined (TE_NetBSD)))
252b5132 413/* This array holds the chars that always start a comment. If the
b3b91714
AM		 414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416const char *i386_comment_chars = "#/";
417#define SVR4_COMMENT_CHARS 1
252b5132 418#define PREFIX_SEPARATOR '\\'
252b5132 419
b3b91714
AM		 420#else
421const char *i386_comment_chars = "#";
422#define PREFIX_SEPARATOR '/'
423#endif
424
252b5132
RH		 425/* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 429 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
252b5132 432 '/' isn't otherwise defined. */
b3b91714 433const char line_comment_chars[] = "#/";
252b5132 434
63a0b638 435const char line_separator_chars[] = ";";
252b5132 436
ce8a8b2f
AM		 437/* Chars that can be used to separate mant from exp in floating point
438 nums. */
252b5132
RH		 439const char EXP_CHARS[] = "eE";
440
ce8a8b2f
AM		 441/* Chars that mean this number is a floating point constant
442 As in 0f12.456
443 or 0d1.2345e12. */
252b5132
RH		 444const char FLT_CHARS[] = "fFdDxX";
445
ce8a8b2f 446/* Tables for lexical analysis. */
252b5132
RH		 447static char mnemonic_chars[256];
448static char register_chars[256];
449static char operand_chars[256];
450static char identifier_chars[256];
451static char digit_chars[256];
452
ce8a8b2f 453/* Lexical macros. */
252b5132
RH		 454#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455#define is_operand_char(x) (operand_chars[(unsigned char) x])
456#define is_register_char(x) (register_chars[(unsigned char) x])
457#define is_space_char(x) ((x) == ' ')
458#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459#define is_digit_char(x) (digit_chars[(unsigned char) x])
460
0234cb7c 461/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 462static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
463
464/* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
47926f60 467 assembler instruction). */
252b5132 468static char save_stack[32];
ce8a8b2f 469static char *save_stack_p;
252b5132
RH		 470#define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472#define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
474
47926f60 475/* The instruction we're assembling. */
252b5132
RH		 476static i386_insn i;
477
478/* Possible templates for current insn. */
479static const templates *current_templates;
480
31b2323c
L		 481/* Per instruction expressionS buffers: max displacements & immediates. */
482static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
483static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 484
47926f60 485/* Current operand we are working on. */
ee86248c 486static int this_operand = -1;
252b5132 487
3e73aa7c
JH		 488/* We support four different modes. FLAG_CODE variable is used to distinguish
489 these. */
490
491enum flag_code {
492 CODE_32BIT,
493 CODE_16BIT,
494 CODE_64BIT };
495
496static enum flag_code flag_code;
4fa24527 497static unsigned int object_64bit;
862be3fb 498static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 499static int use_rela_relocations = 0;
500
7af8ed2d
NC		 501#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
504
351f65ca
L		 505/* The ELF ABI to use. */
506enum x86_elf_abi
507{
508 I386_ABI,
7f56bc95
L		 509 X86_64_ABI,
510 X86_64_X32_ABI
351f65ca
L		 511};
512
513static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 514#endif
351f65ca 515
167ad85b
TG		 516#if defined (TE_PE) || defined (TE_PEP)
517/* Use big object file format. */
518static int use_big_obj = 0;
519#endif
520
47926f60
KH		 521/* 1 for intel syntax,
522 0 if att syntax. */
523static int intel_syntax = 0;
252b5132 524
1efbbeb4
L		 525/* 1 for intel mnemonic,
526 0 if att mnemonic. */
527static int intel_mnemonic = !SYSV386_COMPAT;
528
5209009a 529/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 530static int old_gcc = OLDGCC_COMPAT;
531
a60de03c
JB		 532/* 1 if pseudo registers are permitted. */
533static int allow_pseudo_reg = 0;
534
47926f60
KH		 535/* 1 if register prefix % not required. */
536static int allow_naked_reg = 0;
252b5132 537
7e8b059b
L		 538/* 1 if the assembler should add BND prefix for all control-tranferring
539 instructions supporting it, even if this prefix wasn't specified
540 explicitly. */
541static int add_bnd_prefix = 0;
542
ba104c83 543/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 544static int allow_index_reg = 0;
545
d022bddd
IT		 546/* 1 if the assembler should ignore LOCK prefix, even if it was
547 specified explicitly. */
548static int omit_lock_prefix = 0;
549
7bab8ab5 550static enum check_kind
daf50ae7 551 {
7bab8ab5
JB		 552 check_none = 0,
553 check_warning,
554 check_error
daf50ae7 555 }
7bab8ab5 556sse_check, operand_check = check_warning;
daf50ae7 557
2ca3ace5
L		 558/* Register prefix used for error message. */
559static const char *register_prefix = "%";
560
47926f60
KH		 561/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
562 leave, push, and pop instructions so that gcc has the same stack
563 frame as in 32 bit mode. */
564static char stackop_size = '\0';
eecb386c 565
12b55ccc
L		 566/* Non-zero to optimize code alignment. */
567int optimize_align_code = 1;
568
47926f60
KH		 569/* Non-zero to quieten some warnings. */
570static int quiet_warnings = 0;
a38cf1db 571
47926f60
KH		 572/* CPU name. */
573static const char *cpu_arch_name = NULL;
6305a203 574static char *cpu_sub_arch_name = NULL;
a38cf1db 575
47926f60 576/* CPU feature flags. */
40fb9820
L		 577static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
578
ccc9c027
L		 579/* If we have selected a cpu we are generating instructions for. */
580static int cpu_arch_tune_set = 0;
581
9103f4f4 582/* Cpu we are generating instructions for. */
fbf3f584 583enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 584
585/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 586static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 587
ccc9c027 588/* CPU instruction set architecture used. */
fbf3f584 589enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 590
9103f4f4 591/* CPU feature flags of instruction set architecture used. */
fbf3f584 592i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 593
fddf5b5b
AM		 594/* If set, conditional jumps are not automatically promoted to handle
595 larger than a byte offset. */
596static unsigned int no_cond_jump_promotion = 0;
597
c0f3af97
L		 598/* Encode SSE instructions with VEX prefix. */
599static unsigned int sse2avx;
600
539f890d
L		 601/* Encode scalar AVX instructions with specific vector length. */
602static enum
603 {
604 vex128 = 0,
605 vex256
606 } avxscalar;
607
43234a1e
L		 608/* Encode scalar EVEX LIG instructions with specific vector length. */
609static enum
610 {
611 evexl128 = 0,
612 evexl256,
613 evexl512
614 } evexlig;
615
616/* Encode EVEX WIG instructions with specific evex.w. */
617static enum
618 {
619 evexw0 = 0,
620 evexw1
621 } evexwig;
622
d3d3c6db
IT		 623/* Value to encode in EVEX RC bits, for SAE-only instructions. */
624static enum rc_type evexrcig = rne;
625
29b0f896 626/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 627static symbolS *GOT_symbol;
29b0f896 628
a4447b93
RH		 629/* The dwarf2 return column, adjusted for 32 or 64 bit. */
630unsigned int x86_dwarf2_return_column;
631
632/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
633int x86_cie_data_alignment;
634
252b5132 635/* Interface to relax_segment.
fddf5b5b
AM		 636 There are 3 major relax states for 386 jump insns because the
637 different types of jumps add different sizes to frags when we're
638 figuring out what sort of jump to choose to reach a given label. */
252b5132 639
47926f60 640/* Types. */
93c2a809
AM		 641#define UNCOND_JUMP 0
642#define COND_JUMP 1
643#define COND_JUMP86 2
fddf5b5b 644
47926f60 645/* Sizes. */
252b5132
RH		 646#define CODE16 1
647#define SMALL 0
29b0f896 648#define SMALL16 (SMALL | CODE16)
252b5132 649#define BIG 2
29b0f896 650#define BIG16 (BIG | CODE16)
252b5132
RH		 651
652#ifndef INLINE
653#ifdef __GNUC__
654#define INLINE __inline__
655#else
656#define INLINE
657#endif
658#endif
659
fddf5b5b
AM		 660#define ENCODE_RELAX_STATE(type, size) \
661 ((relax_substateT) (((type) << 2) | (size)))
662#define TYPE_FROM_RELAX_STATE(s) \
663 ((s) >> 2)
664#define DISP_SIZE_FROM_RELAX_STATE(s) \
665 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 666
667/* This table is used by relax_frag to promote short jumps to long
668 ones where necessary. SMALL (short) jumps may be promoted to BIG
669 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
670 don't allow a short jump in a 32 bit code segment to be promoted to
671 a 16 bit offset jump because it's slower (requires data size
672 prefix), and doesn't work, unless the destination is in the bottom
673 64k of the code segment (The top 16 bits of eip are zeroed). */
674
675const relax_typeS md_relax_table[] =
676{
24eab124
AM		 677 /* The fields are:
678 1) most positive reach of this state,
679 2) most negative reach of this state,
93c2a809 680 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 681 4) which index into the table to try if we can't fit into this one. */
252b5132 682
fddf5b5b 683 /* UNCOND_JUMP states. */
93c2a809
AM		 684 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
685 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
686 /* dword jmp adds 4 bytes to frag:
687 0 extra opcode bytes, 4 displacement bytes. */
252b5132 688 {0, 0, 4, 0},
93c2a809
AM		 689 /* word jmp adds 2 byte2 to frag:
690 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 691 {0, 0, 2, 0},
692
93c2a809
AM		 693 /* COND_JUMP states. */
694 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
696 /* dword conditionals adds 5 bytes to frag:
697 1 extra opcode byte, 4 displacement bytes. */
698 {0, 0, 5, 0},
fddf5b5b 699 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 700 1 extra opcode byte, 2 displacement bytes. */
701 {0, 0, 3, 0},
702
703 /* COND_JUMP86 states. */
704 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
705 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
706 /* dword conditionals adds 5 bytes to frag:
707 1 extra opcode byte, 4 displacement bytes. */
708 {0, 0, 5, 0},
709 /* word conditionals add 4 bytes to frag:
710 1 displacement byte and a 3 byte long branch insn. */
711 {0, 0, 4, 0}
252b5132
RH		 712};
713
9103f4f4
L		 714static const arch_entry cpu_arch[] =
715{
89507696
JB		 716 /* Do not replace the first two entries - i386_target_format()
717 relies on them being there in this order. */
8a2c8fef 718 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 719 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 720 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 721 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 722 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 723 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 724 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 725 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 726 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 727 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 728 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 729 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 730 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 731 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 732 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 733 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 734 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 735 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 736 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 737 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 738 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 739 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 740 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 741 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 742 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 743 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 744 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 745 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 746 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 747 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 748 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 749 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 750 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 751 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 752 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 753 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 754 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 755 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 756 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 757 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 758 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 759 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 760 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 761 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 762 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
763 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 764 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 765 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 766 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 767 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 768 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 769 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 770 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 771 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 772 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 773 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 774 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 775 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 776 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 777 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 778 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 779 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 780 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 781 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 782 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
783 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 784 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
785 CPU_BDVER4_FLAGS, 0, 0 },
7b458c12
L		 786 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
787 CPU_BTVER1_FLAGS, 0, 0 },
788 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
789 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 790 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 791 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 792 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 793 CPU_287_FLAGS, 0, 0 },
8a2c8fef 794 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 795 CPU_387_FLAGS, 0, 0 },
8a2c8fef 796 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 797 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 798 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 799 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 800 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 801 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 802 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 803 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 804 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 805 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 806 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 807 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 808 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 809 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 810 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 811 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 812 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 813 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 814 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 815 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 816 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 817 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 818 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 819 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 820 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
821 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 822 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
823 CPU_AVX512F_FLAGS, 0, 0 },
824 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
825 CPU_AVX512CD_FLAGS, 0, 0 },
826 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
827 CPU_AVX512ER_FLAGS, 0, 0 },
828 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
829 CPU_AVX512PF_FLAGS, 0, 0 },
1dfc6506
L		 830 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
831 CPU_AVX512DQ_FLAGS, 0, 0 },
832 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
833 CPU_AVX512BW_FLAGS, 0, 0 },
834 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
835 CPU_AVX512VL_FLAGS, 0, 0 },
8a2c8fef 836 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 837 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 838 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 839 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 840 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
841 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 842 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 843 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 844 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 845 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 846 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 847 CPU_XSAVEOPT_FLAGS, 0, 0 },
1dfc6506
L		 848 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
849 CPU_XSAVEC_FLAGS, 0, 0 },
850 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
851 CPU_XSAVES_FLAGS, 0, 0 },
8a2c8fef 852 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 853 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 854 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 855 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 856 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 857 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 858 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 859 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 860 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 861 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 862 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 863 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 864 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
865 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 866 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 867 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 868 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 869 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 870 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 871 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 872 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 873 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 874 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 875 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 876 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
877 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 878 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 879 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 880 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
881 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 882 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
883 CPU_HLE_FLAGS, 0, 0 },
884 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
885 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 886 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
887 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 888 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 889 CPU_CLFLUSH_FLAGS, 0, 0 },
890 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
891 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 892 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 893 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 894 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 895 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 896 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 897 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 898 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 899 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 900 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 901 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 902 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 903 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 904 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 905 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 906 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 907 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 908 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 909 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 910 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
911 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 912 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
913 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 914 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
915 CPU_ADX_FLAGS, 0, 0 },
916 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
917 CPU_RDSEED_FLAGS, 0, 0 },
918 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
919 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 920 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
921 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 922 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
923 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 924 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
925 CPU_SHA_FLAGS, 0, 0 },
963f3586
IT		 926 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
927 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
dcf893b5
IT		 928 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
929 CPU_PREFETCHWT1_FLAGS, 0, 0 },
2cf200a4
IT		 930 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
931 CPU_SE1_FLAGS, 0, 0 },
c5e7287a
IT		 932 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
933 CPU_CLWB_FLAGS, 0, 0 },
9d8596f0
IT		 934 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
935 CPU_PCOMMIT_FLAGS, 0, 0 },
e413e4e9
AM		 936};
937
704209c0 938#ifdef I386COFF
a6c24e68
NC		 939/* Like s_lcomm_internal in gas/read.c but the alignment string
940 is allowed to be optional. */
941
942static symbolS *
943pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
944{
945 addressT align = 0;
946
947 SKIP_WHITESPACE ();
948
7ab9ffdd 949 if (needs_align
a6c24e68
NC		 950 && *input_line_pointer == ',')
951 {
952 align = parse_align (needs_align - 1);
7ab9ffdd 953
a6c24e68
NC		 954 if (align == (addressT) -1)
955 return NULL;
956 }
957 else
958 {
959 if (size >= 8)
960 align = 3;
961 else if (size >= 4)
962 align = 2;
963 else if (size >= 2)
964 align = 1;
965 else
966 align = 0;
967 }
968
969 bss_alloc (symbolP, size, align);
970 return symbolP;
971}
972
704209c0 973static void
a6c24e68
NC		 974pe_lcomm (int needs_align)
975{
976 s_comm_internal (needs_align * 2, pe_lcomm_internal);
977}
704209c0 978#endif
a6c24e68 979
29b0f896
AM		 980const pseudo_typeS md_pseudo_table[] =
981{
982#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
983 {"align", s_align_bytes, 0},
984#else
985 {"align", s_align_ptwo, 0},
986#endif
987 {"arch", set_cpu_arch, 0},
988#ifndef I386COFF
989 {"bss", s_bss, 0},
a6c24e68
NC		 990#else
991 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 992#endif
993 {"ffloat", float_cons, 'f'},
994 {"dfloat", float_cons, 'd'},
995 {"tfloat", float_cons, 'x'},
996 {"value", cons, 2},
d182319b 997 {"slong", signed_cons, 4},
29b0f896
AM		 998 {"noopt", s_ignore, 0},
999 {"optim", s_ignore, 0},
1000 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1001 {"code16", set_code_flag, CODE_16BIT},
1002 {"code32", set_code_flag, CODE_32BIT},
1003 {"code64", set_code_flag, CODE_64BIT},
1004 {"intel_syntax", set_intel_syntax, 1},
1005 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1006 {"intel_mnemonic", set_intel_mnemonic, 1},
1007 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1008 {"allow_index_reg", set_allow_index_reg, 1},
1009 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1010 {"sse_check", set_check, 0},
1011 {"operand_check", set_check, 1},
3b22753a
L		 1012#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1013 {"largecomm", handle_large_common, 0},
07a53e5c 1014#else
e3bb37b5 1015 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1016 {"loc", dwarf2_directive_loc, 0},
1017 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1018#endif
6482c264
NC		 1019#ifdef TE_PE
1020 {"secrel32", pe_directive_secrel, 0},
1021#endif
29b0f896
AM		 1022 {0, 0, 0}
1023};
1024
1025/* For interface with expression (). */
1026extern char *input_line_pointer;
1027
1028/* Hash table for instruction mnemonic lookup. */
1029static struct hash_control *op_hash;
1030
1031/* Hash table for register lookup. */
1032static struct hash_control *reg_hash;
1033\f
252b5132 1034void
e3bb37b5 1035i386_align_code (fragS *fragP, int count)
252b5132 1036{
ce8a8b2f
AM		 1037 /* Various efficient no-op patterns for aligning code labels.
1038 Note: Don't try to assemble the instructions in the comments.
1039 0L and 0w are not legal. */
252b5132
RH		 1040 static const char f32_1[] =
1041 {0x90}; /* nop */
1042 static const char f32_2[] =
ccc9c027 1043 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1044 static const char f32_3[] =
1045 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1046 static const char f32_4[] =
1047 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1048 static const char f32_5[] =
1049 {0x90, /* nop */
1050 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1051 static const char f32_6[] =
1052 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1053 static const char f32_7[] =
1054 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1055 static const char f32_8[] =
1056 {0x90, /* nop */
1057 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1058 static const char f32_9[] =
1059 {0x89,0xf6, /* movl %esi,%esi */
1060 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1061 static const char f32_10[] =
1062 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1063 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1064 static const char f32_11[] =
1065 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1066 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1067 static const char f32_12[] =
1068 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1069 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1070 static const char f32_13[] =
1071 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1072 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1073 static const char f32_14[] =
1074 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1075 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1076 static const char f16_3[] =
1077 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1078 static const char f16_4[] =
1079 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1080 static const char f16_5[] =
1081 {0x90, /* nop */
1082 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1083 static const char f16_6[] =
1084 {0x89,0xf6, /* mov %si,%si */
1085 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1086 static const char f16_7[] =
1087 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1088 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1089 static const char f16_8[] =
1090 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1091 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1092 static const char jump_31[] =
1093 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1094 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1095 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1096 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1097 static const char *const f32_patt[] = {
1098 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1099 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1100 };
1101 static const char *const f16_patt[] = {
76bc74dc 1102 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1103 };
ccc9c027
L		 1104 /* nopl (%[re]ax) */
1105 static const char alt_3[] =
1106 {0x0f,0x1f,0x00};
1107 /* nopl 0(%[re]ax) */
1108 static const char alt_4[] =
1109 {0x0f,0x1f,0x40,0x00};
1110 /* nopl 0(%[re]ax,%[re]ax,1) */
1111 static const char alt_5[] =
1112 {0x0f,0x1f,0x44,0x00,0x00};
1113 /* nopw 0(%[re]ax,%[re]ax,1) */
1114 static const char alt_6[] =
1115 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1116 /* nopl 0L(%[re]ax) */
1117 static const char alt_7[] =
1118 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1119 /* nopl 0L(%[re]ax,%[re]ax,1) */
1120 static const char alt_8[] =
1121 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1122 /* nopw 0L(%[re]ax,%[re]ax,1) */
1123 static const char alt_9[] =
1124 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1125 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1126 static const char alt_10[] =
1127 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1128 /* data16
1129 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1130 static const char alt_long_11[] =
1131 {0x66,
1132 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1133 /* data16
1134 data16
1135 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1136 static const char alt_long_12[] =
1137 {0x66,
1138 0x66,
1139 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1140 /* data16
1141 data16
1142 data16
1143 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1144 static const char alt_long_13[] =
1145 {0x66,
1146 0x66,
1147 0x66,
1148 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1149 /* data16
1150 data16
1151 data16
1152 data16
1153 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1154 static const char alt_long_14[] =
1155 {0x66,
1156 0x66,
1157 0x66,
1158 0x66,
1159 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1160 /* data16
1161 data16
1162 data16
1163 data16
1164 data16
1165 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1166 static const char alt_long_15[] =
1167 {0x66,
1168 0x66,
1169 0x66,
1170 0x66,
1171 0x66,
1172 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1173 /* nopl 0(%[re]ax,%[re]ax,1)
1174 nopw 0(%[re]ax,%[re]ax,1) */
1175 static const char alt_short_11[] =
1176 {0x0f,0x1f,0x44,0x00,0x00,
1177 0x66,0x0f,0x1f,0x44,0x00,0x00};
1178 /* nopw 0(%[re]ax,%[re]ax,1)
1179 nopw 0(%[re]ax,%[re]ax,1) */
1180 static const char alt_short_12[] =
1181 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1182 0x66,0x0f,0x1f,0x44,0x00,0x00};
1183 /* nopw 0(%[re]ax,%[re]ax,1)
1184 nopl 0L(%[re]ax) */
1185 static const char alt_short_13[] =
1186 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1187 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1188 /* nopl 0L(%[re]ax)
1189 nopl 0L(%[re]ax) */
1190 static const char alt_short_14[] =
1191 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1192 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1193 /* nopl 0L(%[re]ax)
1194 nopl 0L(%[re]ax,%[re]ax,1) */
1195 static const char alt_short_15[] =
1196 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1197 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1198 static const char *const alt_short_patt[] = {
1199 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1200 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1201 alt_short_14, alt_short_15
1202 };
1203 static const char *const alt_long_patt[] = {
1204 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1205 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1206 alt_long_14, alt_long_15
1207 };
252b5132 1208
76bc74dc
L		 1209 /* Only align for at least a positive non-zero boundary. */
1210 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1211 return;
3e73aa7c 1212
ccc9c027
L		 1213 /* We need to decide which NOP sequence to use for 32bit and
1214 64bit. When -mtune= is used:
4eed87de 1215
76bc74dc
L		 1216 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1217 PROCESSOR_GENERIC32, f32_patt will be used.
1218 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1219 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1220 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1221 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
7b458c12 1222 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
69dd9865 1223 will be used.
ccc9c027 1224
76bc74dc 1225 When -mtune= isn't used, alt_long_patt will be used if
22109423 1226 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1227 be used.
ccc9c027
L		 1228
1229 When -march= or .arch is used, we can't use anything beyond
1230 cpu_arch_isa_flags. */
1231
1232 if (flag_code == CODE_16BIT)
1233 {
ccc9c027 1234 if (count > 8)
33fef721 1235 {
76bc74dc
L		 1236 memcpy (fragP->fr_literal + fragP->fr_fix,
1237 jump_31, count);
1238 /* Adjust jump offset. */
1239 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1240 }
76bc74dc
L		 1241 else
1242 memcpy (fragP->fr_literal + fragP->fr_fix,
1243 f16_patt[count - 1], count);
252b5132 1244 }
33fef721 1245 else
ccc9c027
L		 1246 {
1247 const char *const *patt = NULL;
1248
fbf3f584 1249 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1250 {
1251 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1252 switch (cpu_arch_tune)
1253 {
1254 case PROCESSOR_UNKNOWN:
1255 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1256 optimize with nops. */
1257 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1258 patt = alt_long_patt;
ccc9c027
L		 1259 else
1260 patt = f32_patt;
1261 break;
ccc9c027
L		 1262 case PROCESSOR_PENTIUM4:
1263 case PROCESSOR_NOCONA:
ef05d495 1264 case PROCESSOR_CORE:
76bc74dc 1265 case PROCESSOR_CORE2:
bd5295b2 1266 case PROCESSOR_COREI7:
3632d14b 1267 case PROCESSOR_L1OM:
7a9068fe 1268 case PROCESSOR_K1OM:
76bc74dc
L		 1269 case PROCESSOR_GENERIC64:
1270 patt = alt_long_patt;
1271 break;
ccc9c027
L		 1272 case PROCESSOR_K6:
1273 case PROCESSOR_ATHLON:
1274 case PROCESSOR_K8:
4eed87de 1275 case PROCESSOR_AMDFAM10:
8aedb9fe 1276 case PROCESSOR_BD:
7b458c12 1277 case PROCESSOR_BT:
ccc9c027
L		 1278 patt = alt_short_patt;
1279 break;
76bc74dc 1280 case PROCESSOR_I386:
ccc9c027
L		 1281 case PROCESSOR_I486:
1282 case PROCESSOR_PENTIUM:
2dde1948 1283 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1284 case PROCESSOR_GENERIC32:
1285 patt = f32_patt;
1286 break;
4eed87de 1287 }
ccc9c027
L		 1288 }
1289 else
1290 {
fbf3f584 1291 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1292 {
1293 case PROCESSOR_UNKNOWN:
e6a14101 1294 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1295 PROCESSOR_UNKNOWN. */
1296 abort ();
1297 break;
1298
76bc74dc 1299 case PROCESSOR_I386:
ccc9c027
L		 1300 case PROCESSOR_I486:
1301 case PROCESSOR_PENTIUM:
ccc9c027
L		 1302 case PROCESSOR_K6:
1303 case PROCESSOR_ATHLON:
1304 case PROCESSOR_K8:
4eed87de 1305 case PROCESSOR_AMDFAM10:
8aedb9fe 1306 case PROCESSOR_BD:
7b458c12 1307 case PROCESSOR_BT:
ccc9c027
L		 1308 case PROCESSOR_GENERIC32:
1309 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1310 with nops. */
1311 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1312 patt = alt_short_patt;
1313 else
1314 patt = f32_patt;
1315 break;
76bc74dc
L		 1316 case PROCESSOR_PENTIUMPRO:
1317 case PROCESSOR_PENTIUM4:
1318 case PROCESSOR_NOCONA:
1319 case PROCESSOR_CORE:
ef05d495 1320 case PROCESSOR_CORE2:
bd5295b2 1321 case PROCESSOR_COREI7:
3632d14b 1322 case PROCESSOR_L1OM:
7a9068fe 1323 case PROCESSOR_K1OM:
22109423 1324 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1325 patt = alt_long_patt;
1326 else
1327 patt = f32_patt;
1328 break;
1329 case PROCESSOR_GENERIC64:
76bc74dc 1330 patt = alt_long_patt;
ccc9c027 1331 break;
4eed87de 1332 }
ccc9c027
L		 1333 }
1334
76bc74dc
L		 1335 if (patt == f32_patt)
1336 {
1337 /* If the padding is less than 15 bytes, we use the normal
1338 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1339 its offset. */
1340 int limit;
76ba9986 1341
711eedef
L		 1342 /* For 64bit, the limit is 3 bytes. */
1343 if (flag_code == CODE_64BIT
1344 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1345 limit = 3;
1346 else
1347 limit = 15;
1348 if (count < limit)
76bc74dc
L		 1349 memcpy (fragP->fr_literal + fragP->fr_fix,
1350 patt[count - 1], count);
1351 else
1352 {
1353 memcpy (fragP->fr_literal + fragP->fr_fix,
1354 jump_31, count);
1355 /* Adjust jump offset. */
1356 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1357 }
1358 }
1359 else
1360 {
1361 /* Maximum length of an instruction is 15 byte. If the
1362 padding is greater than 15 bytes and we don't use jump,
1363 we have to break it into smaller pieces. */
1364 int padding = count;
1365 while (padding > 15)
1366 {
1367 padding -= 15;
1368 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1369 patt [14], 15);
1370 }
1371
1372 if (padding)
1373 memcpy (fragP->fr_literal + fragP->fr_fix,
1374 patt [padding - 1], padding);
1375 }
ccc9c027 1376 }
33fef721 1377 fragP->fr_var = count;
252b5132
RH		 1378}
1379
c6fb90c8 1380static INLINE int
0dfbf9d7 1381operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1382{
0dfbf9d7 1383 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1384 {
1385 case 3:
0dfbf9d7 1386 if (x->array[2])
c6fb90c8
L		 1387 return 0;
1388 case 2:
0dfbf9d7 1389 if (x->array[1])
c6fb90c8
L		 1390 return 0;
1391 case 1:
0dfbf9d7 1392 return !x->array[0];
c6fb90c8
L		 1393 default:
1394 abort ();
1395 }
40fb9820
L		 1396}
1397
c6fb90c8 1398static INLINE void
0dfbf9d7 1399operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1400{
0dfbf9d7 1401 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1402 {
1403 case 3:
0dfbf9d7 1404 x->array[2] = v;
c6fb90c8 1405 case 2:
0dfbf9d7 1406 x->array[1] = v;
c6fb90c8 1407 case 1:
0dfbf9d7 1408 x->array[0] = v;
c6fb90c8
L		 1409 break;
1410 default:
1411 abort ();
1412 }
1413}
40fb9820 1414
c6fb90c8 1415static INLINE int
0dfbf9d7
L		 1416operand_type_equal (const union i386_operand_type *x,
1417 const union i386_operand_type *y)
c6fb90c8 1418{
0dfbf9d7 1419 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1420 {
1421 case 3:
0dfbf9d7 1422 if (x->array[2] != y->array[2])
c6fb90c8
L		 1423 return 0;
1424 case 2:
0dfbf9d7 1425 if (x->array[1] != y->array[1])
c6fb90c8
L		 1426 return 0;
1427 case 1:
0dfbf9d7 1428 return x->array[0] == y->array[0];
c6fb90c8
L		 1429 break;
1430 default:
1431 abort ();
1432 }
1433}
40fb9820 1434
0dfbf9d7
L		 1435static INLINE int
1436cpu_flags_all_zero (const union i386_cpu_flags *x)
1437{
1438 switch (ARRAY_SIZE(x->array))
1439 {
1440 case 3:
1441 if (x->array[2])
1442 return 0;
1443 case 2:
1444 if (x->array[1])
1445 return 0;
1446 case 1:
1447 return !x->array[0];
1448 default:
1449 abort ();
1450 }
1451}
1452
1453static INLINE void
1454cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1455{
1456 switch (ARRAY_SIZE(x->array))
1457 {
1458 case 3:
1459 x->array[2] = v;
1460 case 2:
1461 x->array[1] = v;
1462 case 1:
1463 x->array[0] = v;
1464 break;
1465 default:
1466 abort ();
1467 }
1468}
1469
1470static INLINE int
1471cpu_flags_equal (const union i386_cpu_flags *x,
1472 const union i386_cpu_flags *y)
1473{
1474 switch (ARRAY_SIZE(x->array))
1475 {
1476 case 3:
1477 if (x->array[2] != y->array[2])
1478 return 0;
1479 case 2:
1480 if (x->array[1] != y->array[1])
1481 return 0;
1482 case 1:
1483 return x->array[0] == y->array[0];
1484 break;
1485 default:
1486 abort ();
1487 }
1488}
c6fb90c8
L		 1489
1490static INLINE int
1491cpu_flags_check_cpu64 (i386_cpu_flags f)
1492{
1493 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1494 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1495}
1496
c6fb90c8
L		 1497static INLINE i386_cpu_flags
1498cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1499{
c6fb90c8
L		 1500 switch (ARRAY_SIZE (x.array))
1501 {
1502 case 3:
1503 x.array [2] &= y.array [2];
1504 case 2:
1505 x.array [1] &= y.array [1];
1506 case 1:
1507 x.array [0] &= y.array [0];
1508 break;
1509 default:
1510 abort ();
1511 }
1512 return x;
1513}
40fb9820 1514
c6fb90c8
L		 1515static INLINE i386_cpu_flags
1516cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1517{
c6fb90c8 1518 switch (ARRAY_SIZE (x.array))
40fb9820 1519 {
c6fb90c8
L		 1520 case 3:
1521 x.array [2] |= y.array [2];
1522 case 2:
1523 x.array [1] |= y.array [1];
1524 case 1:
1525 x.array [0] |= y.array [0];
40fb9820
L		 1526 break;
1527 default:
1528 abort ();
1529 }
40fb9820
L		 1530 return x;
1531}
1532
309d3373
JB		 1533static INLINE i386_cpu_flags
1534cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1535{
1536 switch (ARRAY_SIZE (x.array))
1537 {
1538 case 3:
1539 x.array [2] &= ~y.array [2];
1540 case 2:
1541 x.array [1] &= ~y.array [1];
1542 case 1:
1543 x.array [0] &= ~y.array [0];
1544 break;
1545 default:
1546 abort ();
1547 }
1548 return x;
1549}
1550
c0f3af97
L		 1551#define CPU_FLAGS_ARCH_MATCH 0x1
1552#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1553#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1554#define CPU_FLAGS_PCLMUL_MATCH 0x8
1555#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1556
a5ff0eb2 1557#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1558 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1559 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1560#define CPU_FLAGS_PERFECT_MATCH \
1561 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1562
1563/* Return CPU flags match bits. */
3629bb00 1564
40fb9820 1565static int
d3ce72d0 1566cpu_flags_match (const insn_template *t)
40fb9820 1567{
c0f3af97
L		 1568 i386_cpu_flags x = t->cpu_flags;
1569 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1570
1571 x.bitfield.cpu64 = 0;
1572 x.bitfield.cpuno64 = 0;
1573
0dfbf9d7 1574 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1575 {
1576 /* This instruction is available on all archs. */
1577 match |= CPU_FLAGS_32BIT_MATCH;
1578 }
3629bb00
L		 1579 else
1580 {
c0f3af97 1581 /* This instruction is available only on some archs. */
3629bb00
L		 1582 i386_cpu_flags cpu = cpu_arch_flags;
1583
1584 cpu.bitfield.cpu64 = 0;
1585 cpu.bitfield.cpuno64 = 0;
1586 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1587 if (!cpu_flags_all_zero (&cpu))
1588 {
a5ff0eb2
L		 1589 if (x.bitfield.cpuavx)
1590 {
ce2f5b3c 1591 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1592 if (cpu.bitfield.cpuavx)
1593 {
1594 /* Check SSE2AVX. */
1595 if (!t->opcode_modifier.sse2avx|| sse2avx)
1596 {
1597 match |= (CPU_FLAGS_ARCH_MATCH
1598 | CPU_FLAGS_AVX_MATCH);
1599 /* Check AES. */
1600 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1601 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1602 /* Check PCLMUL. */
1603 if (!x.bitfield.cpupclmul
1604 || cpu.bitfield.cpupclmul)
1605 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1606 }
1607 }
1608 else
1609 match |= CPU_FLAGS_ARCH_MATCH;
1610 }
1611 else
c0f3af97
L		 1612 match |= CPU_FLAGS_32BIT_MATCH;
1613 }
3629bb00 1614 }
c0f3af97 1615 return match;
40fb9820
L		 1616}
1617
c6fb90c8
L		 1618static INLINE i386_operand_type
1619operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1620{
c6fb90c8
L		 1621 switch (ARRAY_SIZE (x.array))
1622 {
1623 case 3:
1624 x.array [2] &= y.array [2];
1625 case 2:
1626 x.array [1] &= y.array [1];
1627 case 1:
1628 x.array [0] &= y.array [0];
1629 break;
1630 default:
1631 abort ();
1632 }
1633 return x;
40fb9820
L		 1634}
1635
c6fb90c8
L		 1636static INLINE i386_operand_type
1637operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1638{
c6fb90c8 1639 switch (ARRAY_SIZE (x.array))
40fb9820 1640 {
c6fb90c8
L		 1641 case 3:
1642 x.array [2] |= y.array [2];
1643 case 2:
1644 x.array [1] |= y.array [1];
1645 case 1:
1646 x.array [0] |= y.array [0];
40fb9820
L		 1647 break;
1648 default:
1649 abort ();
1650 }
c6fb90c8
L		 1651 return x;
1652}
40fb9820 1653
c6fb90c8
L		 1654static INLINE i386_operand_type
1655operand_type_xor (i386_operand_type x, i386_operand_type y)
1656{
1657 switch (ARRAY_SIZE (x.array))
1658 {
1659 case 3:
1660 x.array [2] ^= y.array [2];
1661 case 2:
1662 x.array [1] ^= y.array [1];
1663 case 1:
1664 x.array [0] ^= y.array [0];
1665 break;
1666 default:
1667 abort ();
1668 }
40fb9820
L		 1669 return x;
1670}
1671
1672static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1673static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1674static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1675static const i386_operand_type inoutportreg
1676 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1677static const i386_operand_type reg16_inoutportreg
1678 = OPERAND_TYPE_REG16_INOUTPORTREG;
1679static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1680static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1681static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1682static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1683static const i386_operand_type anydisp
1684 = OPERAND_TYPE_ANYDISP;
40fb9820 1685static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1686static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1687static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1688static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1689static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1690static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1691static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1692static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1693static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1694static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1695static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1696static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1697static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1698static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1699
1700enum operand_type
1701{
1702 reg,
40fb9820
L		 1703 imm,
1704 disp,
1705 anymem
1706};
1707
c6fb90c8 1708static INLINE int
40fb9820
L		 1709operand_type_check (i386_operand_type t, enum operand_type c)
1710{
1711 switch (c)
1712 {
1713 case reg:
1714 return (t.bitfield.reg8
1715 || t.bitfield.reg16
1716 || t.bitfield.reg32
1717 || t.bitfield.reg64);
1718
40fb9820
L		 1719 case imm:
1720 return (t.bitfield.imm8
1721 || t.bitfield.imm8s
1722 || t.bitfield.imm16
1723 || t.bitfield.imm32
1724 || t.bitfield.imm32s
1725 || t.bitfield.imm64);
1726
1727 case disp:
1728 return (t.bitfield.disp8
1729 || t.bitfield.disp16
1730 || t.bitfield.disp32
1731 || t.bitfield.disp32s
1732 || t.bitfield.disp64);
1733
1734 case anymem:
1735 return (t.bitfield.disp8
1736 || t.bitfield.disp16
1737 || t.bitfield.disp32
1738 || t.bitfield.disp32s
1739 || t.bitfield.disp64
1740 || t.bitfield.baseindex);
1741
1742 default:
1743 abort ();
1744 }
2cfe26b6
AM		 1745
1746 return 0;
40fb9820
L		 1747}
1748
5c07affc
L		 1749/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1750 operand J for instruction template T. */
1751
1752static INLINE int
d3ce72d0 1753match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1754{
1755 return !((i.types[j].bitfield.byte
1756 && !t->operand_types[j].bitfield.byte)
1757 || (i.types[j].bitfield.word
1758 && !t->operand_types[j].bitfield.word)
1759 || (i.types[j].bitfield.dword
1760 && !t->operand_types[j].bitfield.dword)
1761 || (i.types[j].bitfield.qword
1762 && !t->operand_types[j].bitfield.qword));
1763}
1764
1765/* Return 1 if there is no conflict in any size on operand J for
1766 instruction template T. */
1767
1768static INLINE int
d3ce72d0 1769match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1770{
1771 return (match_reg_size (t, j)
1772 && !((i.types[j].bitfield.unspecified
1773 && !t->operand_types[j].bitfield.unspecified)
1774 || (i.types[j].bitfield.fword
1775 && !t->operand_types[j].bitfield.fword)
1776 || (i.types[j].bitfield.tbyte
1777 && !t->operand_types[j].bitfield.tbyte)
1778 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1779 && !t->operand_types[j].bitfield.xmmword)
1780 || (i.types[j].bitfield.ymmword
43234a1e
L		 1781 && !t->operand_types[j].bitfield.ymmword)
1782 || (i.types[j].bitfield.zmmword
1783 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1784}
1785
1786/* Return 1 if there is no size conflict on any operands for
1787 instruction template T. */
1788
1789static INLINE int
d3ce72d0 1790operand_size_match (const insn_template *t)
5c07affc
L		 1791{
1792 unsigned int j;
1793 int match = 1;
1794
1795 /* Don't check jump instructions. */
1796 if (t->opcode_modifier.jump
1797 || t->opcode_modifier.jumpbyte
1798 || t->opcode_modifier.jumpdword
1799 || t->opcode_modifier.jumpintersegment)
1800 return match;
1801
1802 /* Check memory and accumulator operand size. */
1803 for (j = 0; j < i.operands; j++)
1804 {
1805 if (t->operand_types[j].bitfield.anysize)
1806 continue;
1807
1808 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1809 {
1810 match = 0;
1811 break;
1812 }
1813
1814 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1815 {
1816 match = 0;
1817 break;
1818 }
1819 }
1820
891edac4 1821 if (match)
5c07affc 1822 return match;
891edac4
L		 1823 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1824 {
1825mismatch:
86e026a4 1826 i.error = operand_size_mismatch;
891edac4
L		 1827 return 0;
1828 }
5c07affc
L		 1829
1830 /* Check reverse. */
9c2799c2 1831 gas_assert (i.operands == 2);
5c07affc
L		 1832
1833 match = 1;
1834 for (j = 0; j < 2; j++)
1835 {
1836 if (t->operand_types[j].bitfield.acc
1837 && !match_reg_size (t, j ? 0 : 1))
891edac4 1838 goto mismatch;
5c07affc
L		 1839
1840 if (i.types[j].bitfield.mem
1841 && !match_mem_size (t, j ? 0 : 1))
891edac4 1842 goto mismatch;
5c07affc
L		 1843 }
1844
1845 return match;
1846}
1847
c6fb90c8 1848static INLINE int
40fb9820
L		 1849operand_type_match (i386_operand_type overlap,
1850 i386_operand_type given)
1851{
1852 i386_operand_type temp = overlap;
1853
1854 temp.bitfield.jumpabsolute = 0;
7d5e4556 1855 temp.bitfield.unspecified = 0;
5c07affc
L		 1856 temp.bitfield.byte = 0;
1857 temp.bitfield.word = 0;
1858 temp.bitfield.dword = 0;
1859 temp.bitfield.fword = 0;
1860 temp.bitfield.qword = 0;
1861 temp.bitfield.tbyte = 0;
1862 temp.bitfield.xmmword = 0;
c0f3af97 1863 temp.bitfield.ymmword = 0;
43234a1e 1864 temp.bitfield.zmmword = 0;
0dfbf9d7 1865 if (operand_type_all_zero (&temp))
891edac4 1866 goto mismatch;
40fb9820 1867
891edac4
L		 1868 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1869 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1870 return 1;
1871
1872mismatch:
a65babc9 1873 i.error = operand_type_mismatch;
891edac4 1874 return 0;
40fb9820
L		 1875}
1876
7d5e4556 1877/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1878 unless the expected operand type register overlap is null.
1879 Note that Acc in a template matches every size of reg. */
1880
c6fb90c8 1881static INLINE int
40fb9820
L		 1882operand_type_register_match (i386_operand_type m0,
1883 i386_operand_type g0,
1884 i386_operand_type t0,
1885 i386_operand_type m1,
1886 i386_operand_type g1,
1887 i386_operand_type t1)
1888{
1889 if (!operand_type_check (g0, reg))
1890 return 1;
1891
1892 if (!operand_type_check (g1, reg))
1893 return 1;
1894
1895 if (g0.bitfield.reg8 == g1.bitfield.reg8
1896 && g0.bitfield.reg16 == g1.bitfield.reg16
1897 && g0.bitfield.reg32 == g1.bitfield.reg32
1898 && g0.bitfield.reg64 == g1.bitfield.reg64)
1899 return 1;
1900
1901 if (m0.bitfield.acc)
1902 {
1903 t0.bitfield.reg8 = 1;
1904 t0.bitfield.reg16 = 1;
1905 t0.bitfield.reg32 = 1;
1906 t0.bitfield.reg64 = 1;
1907 }
1908
1909 if (m1.bitfield.acc)
1910 {
1911 t1.bitfield.reg8 = 1;
1912 t1.bitfield.reg16 = 1;
1913 t1.bitfield.reg32 = 1;
1914 t1.bitfield.reg64 = 1;
1915 }
1916
891edac4
L		 1917 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1918 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1919 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1920 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1921 return 1;
1922
a65babc9 1923 i.error = register_type_mismatch;
891edac4
L		 1924
1925 return 0;
40fb9820
L		 1926}
1927
4c692bc7
JB		 1928static INLINE unsigned int
1929register_number (const reg_entry *r)
1930{
1931 unsigned int nr = r->reg_num;
1932
1933 if (r->reg_flags & RegRex)
1934 nr += 8;
1935
1936 return nr;
1937}
1938
252b5132 1939static INLINE unsigned int
40fb9820 1940mode_from_disp_size (i386_operand_type t)
252b5132 1941{
43234a1e 1942 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1943 return 1;
1944 else if (t.bitfield.disp16
1945 || t.bitfield.disp32
1946 || t.bitfield.disp32s)
1947 return 2;
1948 else
1949 return 0;
252b5132
RH		 1950}
1951
1952static INLINE int
65879393 1953fits_in_signed_byte (addressT num)
252b5132 1954{
65879393 1955 return num + 0x80 <= 0xff;
47926f60 1956}
252b5132
RH		 1957
1958static INLINE int
65879393 1959fits_in_unsigned_byte (addressT num)
252b5132 1960{
65879393 1961 return num <= 0xff;
47926f60 1962}
252b5132
RH		 1963
1964static INLINE int
65879393 1965fits_in_unsigned_word (addressT num)
252b5132 1966{
65879393 1967 return num <= 0xffff;
47926f60 1968}
252b5132
RH		 1969
1970static INLINE int
65879393 1971fits_in_signed_word (addressT num)
252b5132 1972{
65879393 1973 return num + 0x8000 <= 0xffff;
47926f60 1974}
2a962e6d 1975
3e73aa7c 1976static INLINE int
65879393 1977fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1978{
1979#ifndef BFD64
1980 return 1;
1981#else
65879393 1982 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1983#endif
1984} /* fits_in_signed_long() */
2a962e6d 1985
3e73aa7c 1986static INLINE int
65879393 1987fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1988{
1989#ifndef BFD64
1990 return 1;
1991#else
65879393 1992 return num <= 0xffffffff;
3e73aa7c
JH		 1993#endif
1994} /* fits_in_unsigned_long() */
252b5132 1995
43234a1e
L		 1996static INLINE int
1997fits_in_vec_disp8 (offsetT num)
1998{
1999 int shift = i.memshift;
2000 unsigned int mask;
2001
2002 if (shift == -1)
2003 abort ();
2004
2005 mask = (1 << shift) - 1;
2006
2007 /* Return 0 if NUM isn't properly aligned. */
2008 if ((num & mask))
2009 return 0;
2010
2011 /* Check if NUM will fit in 8bit after shift. */
2012 return fits_in_signed_byte (num >> shift);
2013}
2014
a683cc34
SP		 2015static INLINE int
2016fits_in_imm4 (offsetT num)
2017{
2018 return (num & 0xf) == num;
2019}
2020
40fb9820 2021static i386_operand_type
e3bb37b5 2022smallest_imm_type (offsetT num)
252b5132 2023{
40fb9820 2024 i386_operand_type t;
7ab9ffdd 2025
0dfbf9d7 2026 operand_type_set (&t, 0);
40fb9820
L		 2027 t.bitfield.imm64 = 1;
2028
2029 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2030 {
2031 /* This code is disabled on the 486 because all the Imm1 forms
2032 in the opcode table are slower on the i486. They're the
2033 versions with the implicitly specified single-position
2034 displacement, which has another syntax if you really want to
2035 use that form. */
40fb9820
L		 2036 t.bitfield.imm1 = 1;
2037 t.bitfield.imm8 = 1;
2038 t.bitfield.imm8s = 1;
2039 t.bitfield.imm16 = 1;
2040 t.bitfield.imm32 = 1;
2041 t.bitfield.imm32s = 1;
2042 }
2043 else if (fits_in_signed_byte (num))
2044 {
2045 t.bitfield.imm8 = 1;
2046 t.bitfield.imm8s = 1;
2047 t.bitfield.imm16 = 1;
2048 t.bitfield.imm32 = 1;
2049 t.bitfield.imm32s = 1;
2050 }
2051 else if (fits_in_unsigned_byte (num))
2052 {
2053 t.bitfield.imm8 = 1;
2054 t.bitfield.imm16 = 1;
2055 t.bitfield.imm32 = 1;
2056 t.bitfield.imm32s = 1;
2057 }
2058 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2059 {
2060 t.bitfield.imm16 = 1;
2061 t.bitfield.imm32 = 1;
2062 t.bitfield.imm32s = 1;
2063 }
2064 else if (fits_in_signed_long (num))
2065 {
2066 t.bitfield.imm32 = 1;
2067 t.bitfield.imm32s = 1;
2068 }
2069 else if (fits_in_unsigned_long (num))
2070 t.bitfield.imm32 = 1;
2071
2072 return t;
47926f60 2073}
252b5132 2074
847f7ad4 2075static offsetT
e3bb37b5 2076offset_in_range (offsetT val, int size)
847f7ad4 2077{
508866be 2078 addressT mask;
ba2adb93 2079
847f7ad4
AM		 2080 switch (size)
2081 {
508866be
L		 2082 case 1: mask = ((addressT) 1 << 8) - 1; break;
2083 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2084 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2085#ifdef BFD64
2086 case 8: mask = ((addressT) 2 << 63) - 1; break;
2087#endif
47926f60 2088 default: abort ();
847f7ad4
AM		 2089 }
2090
9de868bf
L		 2091#ifdef BFD64
2092 /* If BFD64, sign extend val for 32bit address mode. */
2093 if (flag_code != CODE_64BIT
2094 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2095 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2096 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2097#endif
ba2adb93 2098
47926f60 2099 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2100 {
2101 char buf1[40], buf2[40];
2102
2103 sprint_value (buf1, val);
2104 sprint_value (buf2, val & mask);
2105 as_warn (_("%s shortened to %s"), buf1, buf2);
2106 }
2107 return val & mask;
2108}
2109
c32fa91d
L		 2110enum PREFIX_GROUP
2111{
2112 PREFIX_EXIST = 0,
2113 PREFIX_LOCK,
2114 PREFIX_REP,
2115 PREFIX_OTHER
2116};
2117
2118/* Returns
2119 a. PREFIX_EXIST if attempting to add a prefix where one from the
2120 same class already exists.
2121 b. PREFIX_LOCK if lock prefix is added.
2122 c. PREFIX_REP if rep/repne prefix is added.
2123 d. PREFIX_OTHER if other prefix is added.
2124 */
2125
2126static enum PREFIX_GROUP
e3bb37b5 2127add_prefix (unsigned int prefix)
252b5132 2128{
c32fa91d 2129 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2130 unsigned int q;
252b5132 2131
29b0f896
AM		 2132 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2133 && flag_code == CODE_64BIT)
b1905489 2134 {
161a04f6
L		 2135 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2136 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2137 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2138 ret = PREFIX_EXIST;
b1905489
JB		 2139 q = REX_PREFIX;
2140 }
3e73aa7c 2141 else
b1905489
JB		 2142 {
2143 switch (prefix)
2144 {
2145 default:
2146 abort ();
2147
2148 case CS_PREFIX_OPCODE:
2149 case DS_PREFIX_OPCODE:
2150 case ES_PREFIX_OPCODE:
2151 case FS_PREFIX_OPCODE:
2152 case GS_PREFIX_OPCODE:
2153 case SS_PREFIX_OPCODE:
2154 q = SEG_PREFIX;
2155 break;
2156
2157 case REPNE_PREFIX_OPCODE:
2158 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2159 q = REP_PREFIX;
2160 ret = PREFIX_REP;
2161 break;
2162
b1905489 2163 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2164 q = LOCK_PREFIX;
2165 ret = PREFIX_LOCK;
b1905489
JB		 2166 break;
2167
2168 case FWAIT_OPCODE:
2169 q = WAIT_PREFIX;
2170 break;
2171
2172 case ADDR_PREFIX_OPCODE:
2173 q = ADDR_PREFIX;
2174 break;
2175
2176 case DATA_PREFIX_OPCODE:
2177 q = DATA_PREFIX;
2178 break;
2179 }
2180 if (i.prefix[q] != 0)
c32fa91d 2181 ret = PREFIX_EXIST;
b1905489 2182 }
252b5132 2183
b1905489 2184 if (ret)
252b5132 2185 {
b1905489
JB		 2186 if (!i.prefix[q])
2187 ++i.prefixes;
2188 i.prefix[q] |= prefix;
252b5132 2189 }
b1905489
JB		 2190 else
2191 as_bad (_("same type of prefix used twice"));
252b5132 2192
252b5132
RH		 2193 return ret;
2194}
2195
2196static void
78f12dd3 2197update_code_flag (int value, int check)
eecb386c 2198{
78f12dd3
L		 2199 PRINTF_LIKE ((*as_error));
2200
1e9cc1c2 2201 flag_code = (enum flag_code) value;
40fb9820
L		 2202 if (flag_code == CODE_64BIT)
2203 {
2204 cpu_arch_flags.bitfield.cpu64 = 1;
2205 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2206 }
2207 else
2208 {
2209 cpu_arch_flags.bitfield.cpu64 = 0;
2210 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2211 }
2212 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2213 {
78f12dd3
L		 2214 if (check)
2215 as_error = as_fatal;
2216 else
2217 as_error = as_bad;
2218 (*as_error) (_("64bit mode not supported on `%s'."),
2219 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2220 }
40fb9820 2221 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2222 {
78f12dd3
L		 2223 if (check)
2224 as_error = as_fatal;
2225 else
2226 as_error = as_bad;
2227 (*as_error) (_("32bit mode not supported on `%s'."),
2228 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2229 }
eecb386c
AM		 2230 stackop_size = '\0';
2231}
2232
78f12dd3
L		 2233static void
2234set_code_flag (int value)
2235{
2236 update_code_flag (value, 0);
2237}
2238
eecb386c 2239static void
e3bb37b5 2240set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2241{
1e9cc1c2 2242 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2243 if (flag_code != CODE_16BIT)
2244 abort ();
2245 cpu_arch_flags.bitfield.cpu64 = 0;
2246 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2247 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2248}
2249
2250static void
e3bb37b5 2251set_intel_syntax (int syntax_flag)
252b5132
RH		 2252{
2253 /* Find out if register prefixing is specified. */
2254 int ask_naked_reg = 0;
2255
2256 SKIP_WHITESPACE ();
29b0f896 2257 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2258 {
2259 char *string = input_line_pointer;
2260 int e = get_symbol_end ();
2261
47926f60 2262 if (strcmp (string, "prefix") == 0)
252b5132 2263 ask_naked_reg = 1;
47926f60 2264 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2265 ask_naked_reg = -1;
2266 else
d0b47220 2267 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2268 *input_line_pointer = e;
2269 }
2270 demand_empty_rest_of_line ();
c3332e24 2271
252b5132
RH		 2272 intel_syntax = syntax_flag;
2273
2274 if (ask_naked_reg == 0)
f86103b7
AM		 2275 allow_naked_reg = (intel_syntax
2276 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2277 else
2278 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2279
ee86248c 2280 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2281
e4a3b5a4 2282 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2283 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2284 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2285}
2286
1efbbeb4
L		 2287static void
2288set_intel_mnemonic (int mnemonic_flag)
2289{
e1d4d893 2290 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2291}
2292
db51cc60
L		 2293static void
2294set_allow_index_reg (int flag)
2295{
2296 allow_index_reg = flag;
2297}
2298
cb19c032 2299static void
7bab8ab5 2300set_check (int what)
cb19c032 2301{
7bab8ab5
JB		 2302 enum check_kind *kind;
2303 const char *str;
2304
2305 if (what)
2306 {
2307 kind = &operand_check;
2308 str = "operand";
2309 }
2310 else
2311 {
2312 kind = &sse_check;
2313 str = "sse";
2314 }
2315
cb19c032
L		 2316 SKIP_WHITESPACE ();
2317
2318 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2319 {
2320 char *string = input_line_pointer;
2321 int e = get_symbol_end ();
2322
2323 if (strcmp (string, "none") == 0)
7bab8ab5 2324 *kind = check_none;
cb19c032 2325 else if (strcmp (string, "warning") == 0)
7bab8ab5 2326 *kind = check_warning;
cb19c032 2327 else if (strcmp (string, "error") == 0)
7bab8ab5 2328 *kind = check_error;
cb19c032 2329 else
7bab8ab5 2330 as_bad (_("bad argument to %s_check directive."), str);
cb19c032
L		 2331 *input_line_pointer = e;
2332 }
2333 else
7bab8ab5 2334 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2335
2336 demand_empty_rest_of_line ();
2337}
2338
8a9036a4
L		 2339static void
2340check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2341 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2342{
2343#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2344 static const char *arch;
2345
2346 /* Intel LIOM is only supported on ELF. */
2347 if (!IS_ELF)
2348 return;
2349
2350 if (!arch)
2351 {
2352 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2353 use default_arch. */
2354 arch = cpu_arch_name;
2355 if (!arch)
2356 arch = default_arch;
2357 }
2358
3632d14b 2359 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2360 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2361 || new_flag.bitfield.cpul1om)
8a9036a4 2362 return;
76ba9986 2363
7a9068fe
L		 2364 /* If we are targeting Intel K1OM, we must enable it. */
2365 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2366 || new_flag.bitfield.cpuk1om)
2367 return;
2368
8a9036a4
L		 2369 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2370#endif
2371}
2372
e413e4e9 2373static void
e3bb37b5 2374set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2375{
47926f60 2376 SKIP_WHITESPACE ();
e413e4e9 2377
29b0f896 2378 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2379 {
2380 char *string = input_line_pointer;
2381 int e = get_symbol_end ();
91d6fa6a 2382 unsigned int j;
40fb9820 2383 i386_cpu_flags flags;
e413e4e9 2384
91d6fa6a 2385 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2386 {
91d6fa6a 2387 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2388 {
91d6fa6a 2389 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2390
5c6af06e
JB		 2391 if (*string != '.')
2392 {
91d6fa6a 2393 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2394 cpu_sub_arch_name = NULL;
91d6fa6a 2395 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2396 if (flag_code == CODE_64BIT)
2397 {
2398 cpu_arch_flags.bitfield.cpu64 = 1;
2399 cpu_arch_flags.bitfield.cpuno64 = 0;
2400 }
2401 else
2402 {
2403 cpu_arch_flags.bitfield.cpu64 = 0;
2404 cpu_arch_flags.bitfield.cpuno64 = 1;
2405 }
91d6fa6a
NC		 2406 cpu_arch_isa = cpu_arch[j].type;
2407 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2408 if (!cpu_arch_tune_set)
2409 {
2410 cpu_arch_tune = cpu_arch_isa;
2411 cpu_arch_tune_flags = cpu_arch_isa_flags;
2412 }
5c6af06e
JB		 2413 break;
2414 }
40fb9820 2415
22109423 2416 if (!cpu_arch[j].negated)
309d3373 2417 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2418 cpu_arch[j].flags);
309d3373
JB		 2419 else
2420 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2421 cpu_arch[j].flags);
0dfbf9d7 2422 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2423 {
6305a203
L		 2424 if (cpu_sub_arch_name)
2425 {
2426 char *name = cpu_sub_arch_name;
2427 cpu_sub_arch_name = concat (name,
91d6fa6a 2428 cpu_arch[j].name,
1bf57e9f 2429 (const char *) NULL);
6305a203
L		 2430 free (name);
2431 }
2432 else
91d6fa6a 2433 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2434 cpu_arch_flags = flags;
a586129e 2435 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2436 }
2437 *input_line_pointer = e;
2438 demand_empty_rest_of_line ();
2439 return;
e413e4e9
AM		 2440 }
2441 }
91d6fa6a 2442 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2443 as_bad (_("no such architecture: `%s'"), string);
2444
2445 *input_line_pointer = e;
2446 }
2447 else
2448 as_bad (_("missing cpu architecture"));
2449
fddf5b5b
AM		 2450 no_cond_jump_promotion = 0;
2451 if (*input_line_pointer == ','
29b0f896 2452 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2453 {
2454 char *string = ++input_line_pointer;
2455 int e = get_symbol_end ();
2456
2457 if (strcmp (string, "nojumps") == 0)
2458 no_cond_jump_promotion = 1;
2459 else if (strcmp (string, "jumps") == 0)
2460 ;
2461 else
2462 as_bad (_("no such architecture modifier: `%s'"), string);
2463
2464 *input_line_pointer = e;
2465 }
2466
e413e4e9
AM		 2467 demand_empty_rest_of_line ();
2468}
2469
8a9036a4
L		 2470enum bfd_architecture
2471i386_arch (void)
2472{
3632d14b 2473 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2474 {
2475 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2476 || flag_code != CODE_64BIT)
2477 as_fatal (_("Intel L1OM is 64bit ELF only"));
2478 return bfd_arch_l1om;
2479 }
7a9068fe
L		 2480 else if (cpu_arch_isa == PROCESSOR_K1OM)
2481 {
2482 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2483 || flag_code != CODE_64BIT)
2484 as_fatal (_("Intel K1OM is 64bit ELF only"));
2485 return bfd_arch_k1om;
2486 }
8a9036a4
L		 2487 else
2488 return bfd_arch_i386;
2489}
2490
b9d79e03 2491unsigned long
7016a5d5 2492i386_mach (void)
b9d79e03 2493{
351f65ca 2494 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2495 {
3632d14b 2496 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2497 {
351f65ca
L		 2498 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2499 || default_arch[6] != '\0')
8a9036a4
L		 2500 as_fatal (_("Intel L1OM is 64bit ELF only"));
2501 return bfd_mach_l1om;
2502 }
7a9068fe
L		 2503 else if (cpu_arch_isa == PROCESSOR_K1OM)
2504 {
2505 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2506 || default_arch[6] != '\0')
2507 as_fatal (_("Intel K1OM is 64bit ELF only"));
2508 return bfd_mach_k1om;
2509 }
351f65ca 2510 else if (default_arch[6] == '\0')
8a9036a4 2511 return bfd_mach_x86_64;
351f65ca
L		 2512 else
2513 return bfd_mach_x64_32;
8a9036a4 2514 }
b9d79e03
JH		 2515 else if (!strcmp (default_arch, "i386"))
2516 return bfd_mach_i386_i386;
2517 else
2b5d6a91 2518 as_fatal (_("unknown architecture"));
b9d79e03 2519}
b9d79e03 2520\f
252b5132 2521void
7016a5d5 2522md_begin (void)
252b5132
RH		 2523{
2524 const char *hash_err;
2525
47926f60 2526 /* Initialize op_hash hash table. */
252b5132
RH		 2527 op_hash = hash_new ();
2528
2529 {
d3ce72d0 2530 const insn_template *optab;
29b0f896 2531 templates *core_optab;
252b5132 2532
47926f60
KH		 2533 /* Setup for loop. */
2534 optab = i386_optab;
252b5132
RH		 2535 core_optab = (templates *) xmalloc (sizeof (templates));
2536 core_optab->start = optab;
2537
2538 while (1)
2539 {
2540 ++optab;
2541 if (optab->name == NULL
2542 || strcmp (optab->name, (optab - 1)->name) != 0)
2543 {
2544 /* different name --> ship out current template list;
47926f60 2545 add to hash table; & begin anew. */
252b5132
RH		 2546 core_optab->end = optab;
2547 hash_err = hash_insert (op_hash,
2548 (optab - 1)->name,
5a49b8ac 2549 (void *) core_optab);
252b5132
RH		 2550 if (hash_err)
2551 {
b37df7c4 2552 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2553 (optab - 1)->name,
2554 hash_err);
2555 }
2556 if (optab->name == NULL)
2557 break;
2558 core_optab = (templates *) xmalloc (sizeof (templates));
2559 core_optab->start = optab;
2560 }
2561 }
2562 }
2563
47926f60 2564 /* Initialize reg_hash hash table. */
252b5132
RH		 2565 reg_hash = hash_new ();
2566 {
29b0f896 2567 const reg_entry *regtab;
c3fe08fa 2568 unsigned int regtab_size = i386_regtab_size;
252b5132 2569
c3fe08fa 2570 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2571 {
5a49b8ac 2572 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2573 if (hash_err)
b37df7c4 2574 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2575 regtab->reg_name,
2576 hash_err);
252b5132
RH		 2577 }
2578 }
2579
47926f60 2580 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2581 {
29b0f896
AM		 2582 int c;
2583 char *p;
252b5132
RH		 2584
2585 for (c = 0; c < 256; c++)
2586 {
3882b010 2587 if (ISDIGIT (c))
252b5132
RH		 2588 {
2589 digit_chars[c] = c;
2590 mnemonic_chars[c] = c;
2591 register_chars[c] = c;
2592 operand_chars[c] = c;
2593 }
3882b010 2594 else if (ISLOWER (c))
252b5132
RH		 2595 {
2596 mnemonic_chars[c] = c;
2597 register_chars[c] = c;
2598 operand_chars[c] = c;
2599 }
3882b010 2600 else if (ISUPPER (c))
252b5132 2601 {
3882b010 2602 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2603 register_chars[c] = mnemonic_chars[c];
2604 operand_chars[c] = c;
2605 }
43234a1e
L		 2606 else if (c == '{' || c == '}')
2607 operand_chars[c] = c;
252b5132 2608
3882b010 2609 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2610 identifier_chars[c] = c;
2611 else if (c >= 128)
2612 {
2613 identifier_chars[c] = c;
2614 operand_chars[c] = c;
2615 }
2616 }
2617
2618#ifdef LEX_AT
2619 identifier_chars['@'] = '@';
32137342
NC		 2620#endif
2621#ifdef LEX_QM
2622 identifier_chars['?'] = '?';
2623 operand_chars['?'] = '?';
252b5132 2624#endif
252b5132 2625 digit_chars['-'] = '-';
c0f3af97 2626 mnemonic_chars['_'] = '_';
791fe849 2627 mnemonic_chars['-'] = '-';
0003779b 2628 mnemonic_chars['.'] = '.';
252b5132
RH		 2629 identifier_chars['_'] = '_';
2630 identifier_chars['.'] = '.';
2631
2632 for (p = operand_special_chars; *p != '\0'; p++)
2633 operand_chars[(unsigned char) *p] = *p;
2634 }
2635
a4447b93
RH		 2636 if (flag_code == CODE_64BIT)
2637 {
ca19b261
KT		 2638#if defined (OBJ_COFF) && defined (TE_PE)
2639 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2640 ? 32 : 16);
2641#else
a4447b93 2642 x86_dwarf2_return_column = 16;
ca19b261 2643#endif
61ff971f 2644 x86_cie_data_alignment = -8;
a4447b93
RH		 2645 }
2646 else
2647 {
2648 x86_dwarf2_return_column = 8;
2649 x86_cie_data_alignment = -4;
2650 }
252b5132
RH		 2651}
2652
2653void
e3bb37b5 2654i386_print_statistics (FILE *file)
252b5132
RH		 2655{
2656 hash_print_statistics (file, "i386 opcode", op_hash);
2657 hash_print_statistics (file, "i386 register", reg_hash);
2658}
2659\f
252b5132
RH		 2660#ifdef DEBUG386
2661
ce8a8b2f 2662/* Debugging routines for md_assemble. */
d3ce72d0 2663static void pte (insn_template *);
40fb9820 2664static void pt (i386_operand_type);
e3bb37b5
L		 2665static void pe (expressionS *);
2666static void ps (symbolS *);
252b5132
RH		 2667
2668static void
e3bb37b5 2669pi (char *line, i386_insn *x)
252b5132 2670{
09137c09 2671 unsigned int j;
252b5132
RH		 2672
2673 fprintf (stdout, "%s: template ", line);
2674 pte (&x->tm);
09f131f2
JH		 2675 fprintf (stdout, " address: base %s index %s scale %x\n",
2676 x->base_reg ? x->base_reg->reg_name : "none",
2677 x->index_reg ? x->index_reg->reg_name : "none",
2678 x->log2_scale_factor);
2679 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2680 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2681 fprintf (stdout, " sib: base %x index %x scale %x\n",
2682 x->sib.base, x->sib.index, x->sib.scale);
2683 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2684 (x->rex & REX_W) != 0,
2685 (x->rex & REX_R) != 0,
2686 (x->rex & REX_X) != 0,
2687 (x->rex & REX_B) != 0);
09137c09 2688 for (j = 0; j < x->operands; j++)
252b5132 2689 {
09137c09
SP		 2690 fprintf (stdout, " #%d: ", j + 1);
2691 pt (x->types[j]);
252b5132 2692 fprintf (stdout, "\n");
09137c09
SP		 2693 if (x->types[j].bitfield.reg8
2694 || x->types[j].bitfield.reg16
2695 || x->types[j].bitfield.reg32
2696 || x->types[j].bitfield.reg64
2697 || x->types[j].bitfield.regmmx
2698 || x->types[j].bitfield.regxmm
2699 || x->types[j].bitfield.regymm
43234a1e 2700 || x->types[j].bitfield.regzmm
09137c09
SP		 2701 || x->types[j].bitfield.sreg2
2702 || x->types[j].bitfield.sreg3
2703 || x->types[j].bitfield.control
2704 || x->types[j].bitfield.debug
2705 || x->types[j].bitfield.test)
2706 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2707 if (operand_type_check (x->types[j], imm))
2708 pe (x->op[j].imms);
2709 if (operand_type_check (x->types[j], disp))
2710 pe (x->op[j].disps);
252b5132
RH		 2711 }
2712}
2713
2714static void
d3ce72d0 2715pte (insn_template *t)
252b5132 2716{
09137c09 2717 unsigned int j;
252b5132 2718 fprintf (stdout, " %d operands ", t->operands);
47926f60 2719 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2720 if (t->extension_opcode != None)
2721 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2722 if (t->opcode_modifier.d)
252b5132 2723 fprintf (stdout, "D");
40fb9820 2724 if (t->opcode_modifier.w)
252b5132
RH		 2725 fprintf (stdout, "W");
2726 fprintf (stdout, "\n");
09137c09 2727 for (j = 0; j < t->operands; j++)
252b5132 2728 {
09137c09
SP		 2729 fprintf (stdout, " #%d type ", j + 1);
2730 pt (t->operand_types[j]);
252b5132
RH		 2731 fprintf (stdout, "\n");
2732 }
2733}
2734
2735static void
e3bb37b5 2736pe (expressionS *e)
252b5132 2737{
24eab124 2738 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2739 fprintf (stdout, " add_number %ld (%lx)\n",
2740 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2741 if (e->X_add_symbol)
2742 {
2743 fprintf (stdout, " add_symbol ");
2744 ps (e->X_add_symbol);
2745 fprintf (stdout, "\n");
2746 }
2747 if (e->X_op_symbol)
2748 {
2749 fprintf (stdout, " op_symbol ");
2750 ps (e->X_op_symbol);
2751 fprintf (stdout, "\n");
2752 }
2753}
2754
2755static void
e3bb37b5 2756ps (symbolS *s)
252b5132
RH		 2757{
2758 fprintf (stdout, "%s type %s%s",
2759 S_GET_NAME (s),
2760 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2761 segment_name (S_GET_SEGMENT (s)));
2762}
2763
7b81dfbb 2764static struct type_name
252b5132 2765 {
40fb9820
L		 2766 i386_operand_type mask;
2767 const char *name;
252b5132 2768 }
7b81dfbb 2769const type_names[] =
252b5132 2770{
40fb9820
L		 2771 { OPERAND_TYPE_REG8, "r8" },
2772 { OPERAND_TYPE_REG16, "r16" },
2773 { OPERAND_TYPE_REG32, "r32" },
2774 { OPERAND_TYPE_REG64, "r64" },
2775 { OPERAND_TYPE_IMM8, "i8" },
2776 { OPERAND_TYPE_IMM8, "i8s" },
2777 { OPERAND_TYPE_IMM16, "i16" },
2778 { OPERAND_TYPE_IMM32, "i32" },
2779 { OPERAND_TYPE_IMM32S, "i32s" },
2780 { OPERAND_TYPE_IMM64, "i64" },
2781 { OPERAND_TYPE_IMM1, "i1" },
2782 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2783 { OPERAND_TYPE_DISP8, "d8" },
2784 { OPERAND_TYPE_DISP16, "d16" },
2785 { OPERAND_TYPE_DISP32, "d32" },
2786 { OPERAND_TYPE_DISP32S, "d32s" },
2787 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2788 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2789 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2790 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2791 { OPERAND_TYPE_CONTROL, "control reg" },
2792 { OPERAND_TYPE_TEST, "test reg" },
2793 { OPERAND_TYPE_DEBUG, "debug reg" },
2794 { OPERAND_TYPE_FLOATREG, "FReg" },
2795 { OPERAND_TYPE_FLOATACC, "FAcc" },
2796 { OPERAND_TYPE_SREG2, "SReg2" },
2797 { OPERAND_TYPE_SREG3, "SReg3" },
2798 { OPERAND_TYPE_ACC, "Acc" },
2799 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2800 { OPERAND_TYPE_REGMMX, "rMMX" },
2801 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2802 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2803 { OPERAND_TYPE_REGZMM, "rZMM" },
2804 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2805 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2806};
2807
2808static void
40fb9820 2809pt (i386_operand_type t)
252b5132 2810{
40fb9820 2811 unsigned int j;
c6fb90c8 2812 i386_operand_type a;
252b5132 2813
40fb9820 2814 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2815 {
2816 a = operand_type_and (t, type_names[j].mask);
0349dc08 2817 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2818 fprintf (stdout, "%s, ", type_names[j].name);
2819 }
252b5132
RH		 2820 fflush (stdout);
2821}
2822
2823#endif /* DEBUG386 */
2824\f
252b5132 2825static bfd_reloc_code_real_type
3956db08 2826reloc (unsigned int size,
64e74474
AM		 2827 int pcrel,
2828 int sign,
c3320543 2829 int bnd_prefix,
64e74474 2830 bfd_reloc_code_real_type other)
252b5132 2831{
47926f60 2832 if (other != NO_RELOC)
3956db08 2833 {
91d6fa6a 2834 reloc_howto_type *rel;
3956db08
JB		 2835
2836 if (size == 8)
2837 switch (other)
2838 {
64e74474
AM		 2839 case BFD_RELOC_X86_64_GOT32:
2840 return BFD_RELOC_X86_64_GOT64;
2841 break;
553d1284
L		 2842 case BFD_RELOC_X86_64_GOTPLT64:
2843 return BFD_RELOC_X86_64_GOTPLT64;
2844 break;
64e74474
AM		 2845 case BFD_RELOC_X86_64_PLTOFF64:
2846 return BFD_RELOC_X86_64_PLTOFF64;
2847 break;
2848 case BFD_RELOC_X86_64_GOTPC32:
2849 other = BFD_RELOC_X86_64_GOTPC64;
2850 break;
2851 case BFD_RELOC_X86_64_GOTPCREL:
2852 other = BFD_RELOC_X86_64_GOTPCREL64;
2853 break;
2854 case BFD_RELOC_X86_64_TPOFF32:
2855 other = BFD_RELOC_X86_64_TPOFF64;
2856 break;
2857 case BFD_RELOC_X86_64_DTPOFF32:
2858 other = BFD_RELOC_X86_64_DTPOFF64;
2859 break;
2860 default:
2861 break;
3956db08 2862 }
e05278af 2863
8ce3d284 2864#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2865 if (other == BFD_RELOC_SIZE32)
2866 {
2867 if (size == 8)
1ab668bf 2868 other = BFD_RELOC_SIZE64;
8fd4256d 2869 if (pcrel)
1ab668bf
AM		 2870 {
2871 as_bad (_("there are no pc-relative size relocations"));
2872 return NO_RELOC;
2873 }
8fd4256d 2874 }
8ce3d284 2875#endif
8fd4256d 2876
e05278af 2877 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2878 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2879 sign = -1;
2880
91d6fa6a
NC		 2881 rel = bfd_reloc_type_lookup (stdoutput, other);
2882 if (!rel)
3956db08 2883 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2884 else if (size != bfd_get_reloc_size (rel))
3956db08 2885 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2886 bfd_get_reloc_size (rel),
3956db08 2887 size);
91d6fa6a 2888 else if (pcrel && !rel->pc_relative)
3956db08 2889 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2890 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2891 && !sign)
91d6fa6a 2892 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2893 && sign > 0))
3956db08
JB		 2894 as_bad (_("relocated field and relocation type differ in signedness"));
2895 else
2896 return other;
2897 return NO_RELOC;
2898 }
252b5132
RH		 2899
2900 if (pcrel)
2901 {
3e73aa7c 2902 if (!sign)
3956db08 2903 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2904 switch (size)
2905 {
2906 case 1: return BFD_RELOC_8_PCREL;
2907 case 2: return BFD_RELOC_16_PCREL;
c3320543
L		 2908 case 4: return (bnd_prefix && object_64bit
2909 ? BFD_RELOC_X86_64_PC32_BND
2910 : BFD_RELOC_32_PCREL);
d6ab8113 2911 case 8: return BFD_RELOC_64_PCREL;
252b5132 2912 }
3956db08 2913 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2914 }
2915 else
2916 {
3956db08 2917 if (sign > 0)
e5cb08ac 2918 switch (size)
3e73aa7c
JH		 2919 {
2920 case 4: return BFD_RELOC_X86_64_32S;
2921 }
2922 else
2923 switch (size)
2924 {
2925 case 1: return BFD_RELOC_8;
2926 case 2: return BFD_RELOC_16;
2927 case 4: return BFD_RELOC_32;
2928 case 8: return BFD_RELOC_64;
2929 }
3956db08
JB		 2930 as_bad (_("cannot do %s %u byte relocation"),
2931 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2932 }
2933
0cc9e1d3 2934 return NO_RELOC;
252b5132
RH		 2935}
2936
47926f60
KH		 2937/* Here we decide which fixups can be adjusted to make them relative to
2938 the beginning of the section instead of the symbol. Basically we need
2939 to make sure that the dynamic relocations are done correctly, so in
2940 some cases we force the original symbol to be used. */
2941
252b5132 2942int
e3bb37b5 2943tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2944{
6d249963 2945#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2946 if (!IS_ELF)
31312f95
AM		 2947 return 1;
2948
a161fe53
AM		 2949 /* Don't adjust pc-relative references to merge sections in 64-bit
2950 mode. */
2951 if (use_rela_relocations
2952 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2953 && fixP->fx_pcrel)
252b5132 2954 return 0;
31312f95 2955
8d01d9a9
AJ		 2956 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2957 and changed later by validate_fix. */
2958 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2959 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2960 return 0;
2961
8fd4256d
L		 2962 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2963 for size relocations. */
2964 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2965 || fixP->fx_r_type == BFD_RELOC_SIZE64
2966 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2967 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2968 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2969 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2970 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2971 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2972 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2973 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2974 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2975 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2976 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2977 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2978 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2979 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2980 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2981 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2982 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2983 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2984 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2985 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2986 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2987 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2988 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2989 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2990 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2991 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2992 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2993 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2994 return 0;
31312f95 2995#endif
252b5132
RH		 2996 return 1;
2997}
252b5132 2998
b4cac588 2999static int
e3bb37b5 3000intel_float_operand (const char *mnemonic)
252b5132 3001{
9306ca4a
JB		 3002 /* Note that the value returned is meaningful only for opcodes with (memory)
3003 operands, hence the code here is free to improperly handle opcodes that
3004 have no operands (for better performance and smaller code). */
3005
3006 if (mnemonic[0] != 'f')
3007 return 0; /* non-math */
3008
3009 switch (mnemonic[1])
3010 {
3011 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3012 the fs segment override prefix not currently handled because no
3013 call path can make opcodes without operands get here */
3014 case 'i':
3015 return 2 /* integer op */;
3016 case 'l':
3017 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3018 return 3; /* fldcw/fldenv */
3019 break;
3020 case 'n':
3021 if (mnemonic[2] != 'o' /* fnop */)
3022 return 3; /* non-waiting control op */
3023 break;
3024 case 'r':
3025 if (mnemonic[2] == 's')
3026 return 3; /* frstor/frstpm */
3027 break;
3028 case 's':
3029 if (mnemonic[2] == 'a')
3030 return 3; /* fsave */
3031 if (mnemonic[2] == 't')
3032 {
3033 switch (mnemonic[3])
3034 {
3035 case 'c': /* fstcw */
3036 case 'd': /* fstdw */
3037 case 'e': /* fstenv */
3038 case 's': /* fsts[gw] */
3039 return 3;
3040 }
3041 }
3042 break;
3043 case 'x':
3044 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3045 return 0; /* fxsave/fxrstor are not really math ops */
3046 break;
3047 }
252b5132 3048
9306ca4a 3049 return 1;
252b5132
RH		 3050}
3051
c0f3af97
L		 3052/* Build the VEX prefix. */
3053
3054static void
d3ce72d0 3055build_vex_prefix (const insn_template *t)
c0f3af97
L		 3056{
3057 unsigned int register_specifier;
3058 unsigned int implied_prefix;
3059 unsigned int vector_length;
3060
3061 /* Check register specifier. */
3062 if (i.vex.register_specifier)
43234a1e
L		 3063 {
3064 register_specifier =
3065 ~register_number (i.vex.register_specifier) & 0xf;
3066 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3067 }
c0f3af97
L		 3068 else
3069 register_specifier = 0xf;
3070
fa99fab2
L		 3071 /* Use 2-byte VEX prefix by swappping destination and source
3072 operand. */
3073 if (!i.swap_operand
3074 && i.operands == i.reg_operands
7f399153 3075 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3076 && i.tm.opcode_modifier.s
3077 && i.rex == REX_B)
3078 {
3079 unsigned int xchg = i.operands - 1;
3080 union i386_op temp_op;
3081 i386_operand_type temp_type;
3082
3083 temp_type = i.types[xchg];
3084 i.types[xchg] = i.types[0];
3085 i.types[0] = temp_type;
3086 temp_op = i.op[xchg];
3087 i.op[xchg] = i.op[0];
3088 i.op[0] = temp_op;
3089
9c2799c2 3090 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3091
3092 i.rex = REX_R;
3093 xchg = i.rm.regmem;
3094 i.rm.regmem = i.rm.reg;
3095 i.rm.reg = xchg;
3096
3097 /* Use the next insn. */
3098 i.tm = t[1];
3099 }
3100
539f890d
L		 3101 if (i.tm.opcode_modifier.vex == VEXScalar)
3102 vector_length = avxscalar;
3103 else
3104 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3105
3106 switch ((i.tm.base_opcode >> 8) & 0xff)
3107 {
3108 case 0:
3109 implied_prefix = 0;
3110 break;
3111 case DATA_PREFIX_OPCODE:
3112 implied_prefix = 1;
3113 break;
3114 case REPE_PREFIX_OPCODE:
3115 implied_prefix = 2;
3116 break;
3117 case REPNE_PREFIX_OPCODE:
3118 implied_prefix = 3;
3119 break;
3120 default:
3121 abort ();
3122 }
3123
3124 /* Use 2-byte VEX prefix if possible. */
7f399153 3125 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3126 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3127 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3128 {
3129 /* 2-byte VEX prefix. */
3130 unsigned int r;
3131
3132 i.vex.length = 2;
3133 i.vex.bytes[0] = 0xc5;
3134
3135 /* Check the REX.R bit. */
3136 r = (i.rex & REX_R) ? 0 : 1;
3137 i.vex.bytes[1] = (r << 7
3138 | register_specifier << 3
3139 | vector_length << 2
3140 | implied_prefix);
3141 }
3142 else
3143 {
3144 /* 3-byte VEX prefix. */
3145 unsigned int m, w;
3146
f88c9eb0 3147 i.vex.length = 3;
f88c9eb0 3148
7f399153 3149 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3150 {
7f399153
L		 3151 case VEX0F:
3152 m = 0x1;
80de6e00 3153 i.vex.bytes[0] = 0xc4;
7f399153
L		 3154 break;
3155 case VEX0F38:
3156 m = 0x2;
80de6e00 3157 i.vex.bytes[0] = 0xc4;
7f399153
L		 3158 break;
3159 case VEX0F3A:
3160 m = 0x3;
80de6e00 3161 i.vex.bytes[0] = 0xc4;
7f399153
L		 3162 break;
3163 case XOP08:
5dd85c99
SP		 3164 m = 0x8;
3165 i.vex.bytes[0] = 0x8f;
7f399153
L		 3166 break;
3167 case XOP09:
f88c9eb0
SP		 3168 m = 0x9;
3169 i.vex.bytes[0] = 0x8f;
7f399153
L		 3170 break;
3171 case XOP0A:
f88c9eb0
SP		 3172 m = 0xa;
3173 i.vex.bytes[0] = 0x8f;
7f399153
L		 3174 break;
3175 default:
3176 abort ();
f88c9eb0 3177 }
c0f3af97 3178
c0f3af97
L		 3179 /* The high 3 bits of the second VEX byte are 1's compliment
3180 of RXB bits from REX. */
3181 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3182
3183 /* Check the REX.W bit. */
3184 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3185 if (i.tm.opcode_modifier.vexw == VEXW1)
3186 w = 1;
c0f3af97
L		 3187
3188 i.vex.bytes[2] = (w << 7
3189 | register_specifier << 3
3190 | vector_length << 2
3191 | implied_prefix);
3192 }
3193}
3194
43234a1e
L		 3195/* Build the EVEX prefix. */
3196
3197static void
3198build_evex_prefix (void)
3199{
3200 unsigned int register_specifier;
3201 unsigned int implied_prefix;
3202 unsigned int m, w;
3203 rex_byte vrex_used = 0;
3204
3205 /* Check register specifier. */
3206 if (i.vex.register_specifier)
3207 {
3208 gas_assert ((i.vrex & REX_X) == 0);
3209
3210 register_specifier = i.vex.register_specifier->reg_num;
3211 if ((i.vex.register_specifier->reg_flags & RegRex))
3212 register_specifier += 8;
3213 /* The upper 16 registers are encoded in the fourth byte of the
3214 EVEX prefix. */
3215 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3216 i.vex.bytes[3] = 0x8;
3217 register_specifier = ~register_specifier & 0xf;
3218 }
3219 else
3220 {
3221 register_specifier = 0xf;
3222
3223 /* Encode upper 16 vector index register in the fourth byte of
3224 the EVEX prefix. */
3225 if (!(i.vrex & REX_X))
3226 i.vex.bytes[3] = 0x8;
3227 else
3228 vrex_used |= REX_X;
3229 }
3230
3231 switch ((i.tm.base_opcode >> 8) & 0xff)
3232 {
3233 case 0:
3234 implied_prefix = 0;
3235 break;
3236 case DATA_PREFIX_OPCODE:
3237 implied_prefix = 1;
3238 break;
3239 case REPE_PREFIX_OPCODE:
3240 implied_prefix = 2;
3241 break;
3242 case REPNE_PREFIX_OPCODE:
3243 implied_prefix = 3;
3244 break;
3245 default:
3246 abort ();
3247 }
3248
3249 /* 4 byte EVEX prefix. */
3250 i.vex.length = 4;
3251 i.vex.bytes[0] = 0x62;
3252
3253 /* mmmm bits. */
3254 switch (i.tm.opcode_modifier.vexopcode)
3255 {
3256 case VEX0F:
3257 m = 1;
3258 break;
3259 case VEX0F38:
3260 m = 2;
3261 break;
3262 case VEX0F3A:
3263 m = 3;
3264 break;
3265 default:
3266 abort ();
3267 break;
3268 }
3269
3270 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3271 bits from REX. */
3272 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3273
3274 /* The fifth bit of the second EVEX byte is 1's compliment of the
3275 REX_R bit in VREX. */
3276 if (!(i.vrex & REX_R))
3277 i.vex.bytes[1] |= 0x10;
3278 else
3279 vrex_used |= REX_R;
3280
3281 if ((i.reg_operands + i.imm_operands) == i.operands)
3282 {
3283 /* When all operands are registers, the REX_X bit in REX is not
3284 used. We reuse it to encode the upper 16 registers, which is
3285 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3286 as 1's compliment. */
3287 if ((i.vrex & REX_B))
3288 {
3289 vrex_used |= REX_B;
3290 i.vex.bytes[1] &= ~0x40;
3291 }
3292 }
3293
3294 /* EVEX instructions shouldn't need the REX prefix. */
3295 i.vrex &= ~vrex_used;
3296 gas_assert (i.vrex == 0);
3297
3298 /* Check the REX.W bit. */
3299 w = (i.rex & REX_W) ? 1 : 0;
3300 if (i.tm.opcode_modifier.vexw)
3301 {
3302 if (i.tm.opcode_modifier.vexw == VEXW1)
3303 w = 1;
3304 }
3305 /* If w is not set it means we are dealing with WIG instruction. */
3306 else if (!w)
3307 {
3308 if (evexwig == evexw1)
3309 w = 1;
3310 }
3311
3312 /* Encode the U bit. */
3313 implied_prefix |= 0x4;
3314
3315 /* The third byte of the EVEX prefix. */
3316 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3317
3318 /* The fourth byte of the EVEX prefix. */
3319 /* The zeroing-masking bit. */
3320 if (i.mask && i.mask->zeroing)
3321 i.vex.bytes[3] |= 0x80;
3322
3323 /* Don't always set the broadcast bit if there is no RC. */
3324 if (!i.rounding)
3325 {
3326 /* Encode the vector length. */
3327 unsigned int vec_length;
3328
3329 switch (i.tm.opcode_modifier.evex)
3330 {
3331 case EVEXLIG: /* LL' is ignored */
3332 vec_length = evexlig << 5;
3333 break;
3334 case EVEX128:
3335 vec_length = 0 << 5;
3336 break;
3337 case EVEX256:
3338 vec_length = 1 << 5;
3339 break;
3340 case EVEX512:
3341 vec_length = 2 << 5;
3342 break;
3343 default:
3344 abort ();
3345 break;
3346 }
3347 i.vex.bytes[3] |= vec_length;
3348 /* Encode the broadcast bit. */
3349 if (i.broadcast)
3350 i.vex.bytes[3] |= 0x10;
3351 }
3352 else
3353 {
3354 if (i.rounding->type != saeonly)
3355 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3356 else
d3d3c6db 3357 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3358 }
3359
3360 if (i.mask && i.mask->mask)
3361 i.vex.bytes[3] |= i.mask->mask->reg_num;
3362}
3363
65da13b5
L		 3364static void
3365process_immext (void)
3366{
3367 expressionS *exp;
3368
4c692bc7
JB		 3369 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3370 && i.operands > 0)
65da13b5 3371 {
4c692bc7
JB		 3372 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3373 with an opcode suffix which is coded in the same place as an
3374 8-bit immediate field would be.
3375 Here we check those operands and remove them afterwards. */
65da13b5
L		 3376 unsigned int x;
3377
3378 for (x = 0; x < i.operands; x++)
4c692bc7 3379 if (register_number (i.op[x].regs) != x)
65da13b5 3380 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3381 register_prefix, i.op[x].regs->reg_name, x + 1,
3382 i.tm.name);
3383
3384 i.operands = 0;
65da13b5
L		 3385 }
3386
c0f3af97 3387 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3388 which is coded in the same place as an 8-bit immediate field
3389 would be. Here we fake an 8-bit immediate operand from the
3390 opcode suffix stored in tm.extension_opcode.
3391
c1e679ec 3392 AVX instructions also use this encoding, for some of
c0f3af97 3393 3 argument instructions. */
65da13b5 3394
43234a1e 3395 gas_assert (i.imm_operands <= 1
7ab9ffdd 3396 && (i.operands <= 2
43234a1e
L		 3397 || ((i.tm.opcode_modifier.vex
3398 || i.tm.opcode_modifier.evex)
7ab9ffdd 3399 && i.operands <= 4)));
65da13b5
L		 3400
3401 exp = &im_expressions[i.imm_operands++];
3402 i.op[i.operands].imms = exp;
3403 i.types[i.operands] = imm8;
3404 i.operands++;
3405 exp->X_op = O_constant;
3406 exp->X_add_number = i.tm.extension_opcode;
3407 i.tm.extension_opcode = None;
3408}
3409
42164a71
L		 3410
3411static int
3412check_hle (void)
3413{
3414 switch (i.tm.opcode_modifier.hleprefixok)
3415 {
3416 default:
3417 abort ();
82c2def5 3418 case HLEPrefixNone:
165de32a
L		 3419 as_bad (_("invalid instruction `%s' after `%s'"),
3420 i.tm.name, i.hle_prefix);
42164a71 3421 return 0;
82c2def5 3422 case HLEPrefixLock:
42164a71
L		 3423 if (i.prefix[LOCK_PREFIX])
3424 return 1;
165de32a 3425 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3426 return 0;
82c2def5 3427 case HLEPrefixAny:
42164a71 3428 return 1;
82c2def5 3429 case HLEPrefixRelease:
42164a71
L		 3430 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3431 {
3432 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3433 i.tm.name);
3434 return 0;
3435 }
3436 if (i.mem_operands == 0
3437 || !operand_type_check (i.types[i.operands - 1], anymem))
3438 {
3439 as_bad (_("memory destination needed for instruction `%s'"
3440 " after `xrelease'"), i.tm.name);
3441 return 0;
3442 }
3443 return 1;
3444 }
3445}
3446
252b5132
RH		 3447/* This is the guts of the machine-dependent assembler. LINE points to a
3448 machine dependent instruction. This function is supposed to emit
3449 the frags/bytes it assembles to. */
3450
3451void
65da13b5 3452md_assemble (char *line)
252b5132 3453{
40fb9820 3454 unsigned int j;
252b5132 3455 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3456 const insn_template *t;
252b5132 3457
47926f60 3458 /* Initialize globals. */
252b5132
RH		 3459 memset (&i, '\0', sizeof (i));
3460 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3461 i.reloc[j] = NO_RELOC;
252b5132
RH		 3462 memset (disp_expressions, '\0', sizeof (disp_expressions));
3463 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3464 save_stack_p = save_stack;
252b5132
RH		 3465
3466 /* First parse an instruction mnemonic & call i386_operand for the operands.
3467 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3468 start of a (possibly prefixed) mnemonic. */
252b5132 3469
29b0f896
AM		 3470 line = parse_insn (line, mnemonic);
3471 if (line == NULL)
3472 return;
252b5132 3473
29b0f896 3474 line = parse_operands (line, mnemonic);
ee86248c 3475 this_operand = -1;
29b0f896
AM		 3476 if (line == NULL)
3477 return;
252b5132 3478
29b0f896
AM		 3479 /* Now we've parsed the mnemonic into a set of templates, and have the
3480 operands at hand. */
3481
3482 /* All intel opcodes have reversed operands except for "bound" and
3483 "enter". We also don't reverse intersegment "jmp" and "call"
3484 instructions with 2 immediate operands so that the immediate segment
050dfa73 3485 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3486 if (intel_syntax
3487 && i.operands > 1
29b0f896 3488 && (strcmp (mnemonic, "bound") != 0)
30123838 3489 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3490 && !(operand_type_check (i.types[0], imm)
3491 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3492 swap_operands ();
3493
ec56d5c0
JB		 3494 /* The order of the immediates should be reversed
3495 for 2 immediates extrq and insertq instructions */
3496 if (i.imm_operands == 2
3497 && (strcmp (mnemonic, "extrq") == 0
3498 || strcmp (mnemonic, "insertq") == 0))
3499 swap_2_operands (0, 1);
3500
29b0f896
AM		 3501 if (i.imm_operands)
3502 optimize_imm ();
3503
b300c311
L		 3504 /* Don't optimize displacement for movabs since it only takes 64bit
3505 displacement. */
3506 if (i.disp_operands
a501d77e 3507 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3508 && (flag_code != CODE_64BIT
3509 || strcmp (mnemonic, "movabs") != 0))
3510 optimize_disp ();
29b0f896
AM		 3511
3512 /* Next, we find a template that matches the given insn,
3513 making sure the overlap of the given operands types is consistent
3514 with the template operand types. */
252b5132 3515
fa99fab2 3516 if (!(t = match_template ()))
29b0f896 3517 return;
252b5132 3518
7bab8ab5 3519 if (sse_check != check_none
81f8a913 3520 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3521 && (i.tm.cpu_flags.bitfield.cpusse
3522 || i.tm.cpu_flags.bitfield.cpusse2
3523 || i.tm.cpu_flags.bitfield.cpusse3
3524 || i.tm.cpu_flags.bitfield.cpussse3
3525 || i.tm.cpu_flags.bitfield.cpusse4_1
3526 || i.tm.cpu_flags.bitfield.cpusse4_2))
3527 {
7bab8ab5 3528 (sse_check == check_warning
daf50ae7
L		 3529 ? as_warn
3530 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3531 }
3532
321fd21e
L		 3533 /* Zap movzx and movsx suffix. The suffix has been set from
3534 "word ptr" or "byte ptr" on the source operand in Intel syntax
3535 or extracted from mnemonic in AT&T syntax. But we'll use
3536 the destination register to choose the suffix for encoding. */
3537 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3538 {
321fd21e
L		 3539 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3540 there is no suffix, the default will be byte extension. */
3541 if (i.reg_operands != 2
3542 && !i.suffix
7ab9ffdd 3543 && intel_syntax)
321fd21e
L		 3544 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3545
3546 i.suffix = 0;
cd61ebfe 3547 }
24eab124 3548
40fb9820 3549 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3550 if (!add_prefix (FWAIT_OPCODE))
3551 return;
252b5132 3552
d5de92cf
L		 3553 /* Check if REP prefix is OK. */
3554 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3555 {
3556 as_bad (_("invalid instruction `%s' after `%s'"),
3557 i.tm.name, i.rep_prefix);
3558 return;
3559 }
3560
c1ba0266
L		 3561 /* Check for lock without a lockable instruction. Destination operand
3562 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3563 if (i.prefix[LOCK_PREFIX]
3564 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3565 || i.mem_operands == 0
3566 || (i.tm.base_opcode != 0x86
3567 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3568 {
3569 as_bad (_("expecting lockable instruction after `lock'"));
3570 return;
3571 }
3572
42164a71 3573 /* Check if HLE prefix is OK. */
165de32a 3574 if (i.hle_prefix && !check_hle ())
42164a71
L		 3575 return;
3576
7e8b059b
L		 3577 /* Check BND prefix. */
3578 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3579 as_bad (_("expecting valid branch instruction after `bnd'"));
3580
3581 if (i.tm.cpu_flags.bitfield.cpumpx
3582 && flag_code == CODE_64BIT
3583 && i.prefix[ADDR_PREFIX])
3584 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3585
3586 /* Insert BND prefix. */
3587 if (add_bnd_prefix
3588 && i.tm.opcode_modifier.bndprefixok
3589 && !i.prefix[BND_PREFIX])
3590 add_prefix (BND_PREFIX_OPCODE);
3591
29b0f896 3592 /* Check string instruction segment overrides. */
40fb9820 3593 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3594 {
3595 if (!check_string ())
5dd0794d 3596 return;
fc0763e6 3597 i.disp_operands = 0;
29b0f896 3598 }
5dd0794d 3599
29b0f896
AM		 3600 if (!process_suffix ())
3601 return;
e413e4e9 3602
bc0844ae
L		 3603 /* Update operand types. */
3604 for (j = 0; j < i.operands; j++)
3605 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3606
29b0f896
AM		 3607 /* Make still unresolved immediate matches conform to size of immediate
3608 given in i.suffix. */
3609 if (!finalize_imm ())
3610 return;
252b5132 3611
40fb9820 3612 if (i.types[0].bitfield.imm1)
29b0f896 3613 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3614
9afe6eb8
L		 3615 /* We only need to check those implicit registers for instructions
3616 with 3 operands or less. */
3617 if (i.operands <= 3)
3618 for (j = 0; j < i.operands; j++)
3619 if (i.types[j].bitfield.inoutportreg
3620 || i.types[j].bitfield.shiftcount
3621 || i.types[j].bitfield.acc
3622 || i.types[j].bitfield.floatacc)
3623 i.reg_operands--;
40fb9820 3624
c0f3af97
L		 3625 /* ImmExt should be processed after SSE2AVX. */
3626 if (!i.tm.opcode_modifier.sse2avx
3627 && i.tm.opcode_modifier.immext)
65da13b5 3628 process_immext ();
252b5132 3629
29b0f896
AM		 3630 /* For insns with operands there are more diddles to do to the opcode. */
3631 if (i.operands)
3632 {
3633 if (!process_operands ())
3634 return;
3635 }
40fb9820 3636 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3637 {
3638 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3639 as_warn (_("translating to `%sp'"), i.tm.name);
3640 }
252b5132 3641
9e5e5283
L		 3642 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3643 {
3644 if (flag_code == CODE_16BIT)
3645 {
3646 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3647 i.tm.name);
3648 return;
3649 }
c0f3af97 3650
9e5e5283
L		 3651 if (i.tm.opcode_modifier.vex)
3652 build_vex_prefix (t);
3653 else
3654 build_evex_prefix ();
3655 }
43234a1e 3656
5dd85c99
SP		 3657 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3658 instructions may define INT_OPCODE as well, so avoid this corner
3659 case for those instructions that use MODRM. */
3660 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3661 && !i.tm.opcode_modifier.modrm
3662 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3663 {
3664 i.tm.base_opcode = INT3_OPCODE;
3665 i.imm_operands = 0;
3666 }
252b5132 3667
40fb9820
L		 3668 if ((i.tm.opcode_modifier.jump
3669 || i.tm.opcode_modifier.jumpbyte
3670 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3671 && i.op[0].disps->X_op == O_constant)
3672 {
3673 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3674 the absolute address given by the constant. Since ix86 jumps and
3675 calls are pc relative, we need to generate a reloc. */
3676 i.op[0].disps->X_add_symbol = &abs_symbol;
3677 i.op[0].disps->X_op = O_symbol;
3678 }
252b5132 3679
40fb9820 3680 if (i.tm.opcode_modifier.rex64)
161a04f6 3681 i.rex |= REX_W;
252b5132 3682
29b0f896
AM		 3683 /* For 8 bit registers we need an empty rex prefix. Also if the
3684 instruction already has a prefix, we need to convert old
3685 registers to new ones. */
773f551c 3686
40fb9820 3687 if ((i.types[0].bitfield.reg8
29b0f896 3688 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3689 || (i.types[1].bitfield.reg8
29b0f896 3690 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3691 || ((i.types[0].bitfield.reg8
3692 || i.types[1].bitfield.reg8)
29b0f896
AM		 3693 && i.rex != 0))
3694 {
3695 int x;
726c5dcd 3696
29b0f896
AM		 3697 i.rex |= REX_OPCODE;
3698 for (x = 0; x < 2; x++)
3699 {
3700 /* Look for 8 bit operand that uses old registers. */
40fb9820 3701 if (i.types[x].bitfield.reg8
29b0f896 3702 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3703 {
29b0f896
AM		 3704 /* In case it is "hi" register, give up. */
3705 if (i.op[x].regs->reg_num > 3)
a540244d 3706 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3707 "instruction requiring REX prefix."),
a540244d 3708 register_prefix, i.op[x].regs->reg_name);
773f551c 3709
29b0f896
AM		 3710 /* Otherwise it is equivalent to the extended register.
3711 Since the encoding doesn't change this is merely
3712 cosmetic cleanup for debug output. */
3713
3714 i.op[x].regs = i.op[x].regs + 8;
773f551c 3715 }
29b0f896
AM		 3716 }
3717 }
773f551c 3718
7ab9ffdd 3719 if (i.rex != 0)
29b0f896
AM		 3720 add_prefix (REX_OPCODE | i.rex);
3721
3722 /* We are ready to output the insn. */
3723 output_insn ();
3724}
3725
3726static char *
e3bb37b5 3727parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3728{
3729 char *l = line;
3730 char *token_start = l;
3731 char *mnem_p;
5c6af06e 3732 int supported;
d3ce72d0 3733 const insn_template *t;
b6169b20 3734 char *dot_p = NULL;
29b0f896 3735
29b0f896
AM		 3736 while (1)
3737 {
3738 mnem_p = mnemonic;
3739 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3740 {
b6169b20
L		 3741 if (*mnem_p == '.')
3742 dot_p = mnem_p;
29b0f896
AM		 3743 mnem_p++;
3744 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3745 {
29b0f896
AM		 3746 as_bad (_("no such instruction: `%s'"), token_start);
3747 return NULL;
3748 }
3749 l++;
3750 }
3751 if (!is_space_char (*l)
3752 && *l != END_OF_INSN
e44823cf
JB		 3753 && (intel_syntax
3754 || (*l != PREFIX_SEPARATOR
3755 && *l != ',')))
29b0f896
AM		 3756 {
3757 as_bad (_("invalid character %s in mnemonic"),
3758 output_invalid (*l));
3759 return NULL;
3760 }
3761 if (token_start == l)
3762 {
e44823cf 3763 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3764 as_bad (_("expecting prefix; got nothing"));
3765 else
3766 as_bad (_("expecting mnemonic; got nothing"));
3767 return NULL;
3768 }
45288df1 3769
29b0f896 3770 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3771 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3772
29b0f896
AM		 3773 if (*l != END_OF_INSN
3774 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3775 && current_templates
40fb9820 3776 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3777 {
c6fb90c8 3778 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3779 {
3780 as_bad ((flag_code != CODE_64BIT
3781 ? _("`%s' is only supported in 64-bit mode")
3782 : _("`%s' is not supported in 64-bit mode")),
3783 current_templates->start->name);
3784 return NULL;
3785 }
29b0f896
AM		 3786 /* If we are in 16-bit mode, do not allow addr16 or data16.
3787 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3788 if ((current_templates->start->opcode_modifier.size16
3789 || current_templates->start->opcode_modifier.size32)
29b0f896 3790 && flag_code != CODE_64BIT
40fb9820 3791 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3792 ^ (flag_code == CODE_16BIT)))
3793 {
3794 as_bad (_("redundant %s prefix"),
3795 current_templates->start->name);
3796 return NULL;
45288df1 3797 }
29b0f896
AM		 3798 /* Add prefix, checking for repeated prefixes. */
3799 switch (add_prefix (current_templates->start->base_opcode))
3800 {
c32fa91d 3801 case PREFIX_EXIST:
29b0f896 3802 return NULL;
c32fa91d 3803 case PREFIX_REP:
42164a71 3804 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3805 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3806 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3807 i.bnd_prefix = current_templates->start->name;
42164a71 3808 else
d5de92cf 3809 i.rep_prefix = current_templates->start->name;
29b0f896 3810 break;
c32fa91d
L		 3811 default:
3812 break;
29b0f896
AM		 3813 }
3814 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3815 token_start = ++l;
3816 }
3817 else
3818 break;
3819 }
45288df1 3820
30a55f88 3821 if (!current_templates)
b6169b20 3822 {
f8a5c266
L		 3823 /* Check if we should swap operand or force 32bit displacement in
3824 encoding. */
30a55f88
L		 3825 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3826 i.swap_operand = 1;
8d63c93e 3827 else if (mnem_p - 3 == dot_p
a501d77e
L		 3828 && dot_p[1] == 'd'
3829 && dot_p[2] == '8')
3830 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3831 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3832 && dot_p[1] == 'd'
3833 && dot_p[2] == '3'
3834 && dot_p[3] == '2')
a501d77e 3835 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3836 else
3837 goto check_suffix;
3838 mnem_p = dot_p;
3839 *dot_p = '\0';
d3ce72d0 3840 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3841 }
3842
29b0f896
AM		 3843 if (!current_templates)
3844 {
b6169b20 3845check_suffix:
29b0f896
AM		 3846 /* See if we can get a match by trimming off a suffix. */
3847 switch (mnem_p[-1])
3848 {
3849 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3850 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3851 i.suffix = SHORT_MNEM_SUFFIX;
3852 else
29b0f896
AM		 3853 case BYTE_MNEM_SUFFIX:
3854 case QWORD_MNEM_SUFFIX:
3855 i.suffix = mnem_p[-1];
3856 mnem_p[-1] = '\0';
d3ce72d0
NC		 3857 current_templates = (const templates *) hash_find (op_hash,
3858 mnemonic);
29b0f896
AM		 3859 break;
3860 case SHORT_MNEM_SUFFIX:
3861 case LONG_MNEM_SUFFIX:
3862 if (!intel_syntax)
3863 {
3864 i.suffix = mnem_p[-1];
3865 mnem_p[-1] = '\0';
d3ce72d0
NC		 3866 current_templates = (const templates *) hash_find (op_hash,
3867 mnemonic);
29b0f896
AM		 3868 }
3869 break;
252b5132 3870
29b0f896
AM		 3871 /* Intel Syntax. */
3872 case 'd':
3873 if (intel_syntax)
3874 {
9306ca4a 3875 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3876 i.suffix = SHORT_MNEM_SUFFIX;
3877 else
3878 i.suffix = LONG_MNEM_SUFFIX;
3879 mnem_p[-1] = '\0';
d3ce72d0
NC		 3880 current_templates = (const templates *) hash_find (op_hash,
3881 mnemonic);
29b0f896
AM		 3882 }
3883 break;
3884 }
3885 if (!current_templates)
3886 {
3887 as_bad (_("no such instruction: `%s'"), token_start);
3888 return NULL;
3889 }
3890 }
252b5132 3891
40fb9820
L		 3892 if (current_templates->start->opcode_modifier.jump
3893 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3894 {
3895 /* Check for a branch hint. We allow ",pt" and ",pn" for
3896 predict taken and predict not taken respectively.
3897 I'm not sure that branch hints actually do anything on loop
3898 and jcxz insns (JumpByte) for current Pentium4 chips. They
3899 may work in the future and it doesn't hurt to accept them
3900 now. */
3901 if (l[0] == ',' && l[1] == 'p')
3902 {
3903 if (l[2] == 't')
3904 {
3905 if (!add_prefix (DS_PREFIX_OPCODE))
3906 return NULL;
3907 l += 3;
3908 }
3909 else if (l[2] == 'n')
3910 {
3911 if (!add_prefix (CS_PREFIX_OPCODE))
3912 return NULL;
3913 l += 3;
3914 }
3915 }
3916 }
3917 /* Any other comma loses. */
3918 if (*l == ',')
3919 {
3920 as_bad (_("invalid character %s in mnemonic"),
3921 output_invalid (*l));
3922 return NULL;
3923 }
252b5132 3924
29b0f896 3925 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3926 supported = 0;
3927 for (t = current_templates->start; t < current_templates->end; ++t)
3928 {
c0f3af97
L		 3929 supported |= cpu_flags_match (t);
3930 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3931 goto skip;
5c6af06e 3932 }
3629bb00 3933
c0f3af97 3934 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3935 {
3936 as_bad (flag_code == CODE_64BIT
3937 ? _("`%s' is not supported in 64-bit mode")
3938 : _("`%s' is only supported in 64-bit mode"),
3939 current_templates->start->name);
3940 return NULL;
3941 }
c0f3af97 3942 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3943 {
3629bb00 3944 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3945 current_templates->start->name,
41aacd83 3946 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3947 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3948 return NULL;
29b0f896 3949 }
3629bb00
L		 3950
3951skip:
3952 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3953 && (flag_code != CODE_16BIT))
29b0f896
AM		 3954 {
3955 as_warn (_("use .code16 to ensure correct addressing mode"));
3956 }
252b5132 3957
29b0f896
AM		 3958 return l;
3959}
252b5132 3960
29b0f896 3961static char *
e3bb37b5 3962parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3963{
3964 char *token_start;
3138f287 3965
29b0f896
AM		 3966 /* 1 if operand is pending after ','. */
3967 unsigned int expecting_operand = 0;
252b5132 3968
29b0f896
AM		 3969 /* Non-zero if operand parens not balanced. */
3970 unsigned int paren_not_balanced;
3971
3972 while (*l != END_OF_INSN)
3973 {
3974 /* Skip optional white space before operand. */
3975 if (is_space_char (*l))
3976 ++l;
3977 if (!is_operand_char (*l) && *l != END_OF_INSN)
3978 {
3979 as_bad (_("invalid character %s before operand %d"),
3980 output_invalid (*l),
3981 i.operands + 1);
3982 return NULL;
3983 }
3984 token_start = l; /* after white space */
3985 paren_not_balanced = 0;
3986 while (paren_not_balanced || *l != ',')
3987 {
3988 if (*l == END_OF_INSN)
3989 {
3990 if (paren_not_balanced)
3991 {
3992 if (!intel_syntax)
3993 as_bad (_("unbalanced parenthesis in operand %d."),
3994 i.operands + 1);
3995 else
3996 as_bad (_("unbalanced brackets in operand %d."),
3997 i.operands + 1);
3998 return NULL;
3999 }
4000 else
4001 break; /* we are done */
4002 }
4003 else if (!is_operand_char (*l) && !is_space_char (*l))
4004 {
4005 as_bad (_("invalid character %s in operand %d"),
4006 output_invalid (*l),
4007 i.operands + 1);
4008 return NULL;
4009 }
4010 if (!intel_syntax)
4011 {
4012 if (*l == '(')
4013 ++paren_not_balanced;
4014 if (*l == ')')
4015 --paren_not_balanced;
4016 }
4017 else
4018 {
4019 if (*l == '[')
4020 ++paren_not_balanced;
4021 if (*l == ']')
4022 --paren_not_balanced;
4023 }
4024 l++;
4025 }
4026 if (l != token_start)
4027 { /* Yes, we've read in another operand. */
4028 unsigned int operand_ok;
4029 this_operand = i.operands++;
7d5e4556 4030 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4031 if (i.operands > MAX_OPERANDS)
4032 {
4033 as_bad (_("spurious operands; (%d operands/instruction max)"),
4034 MAX_OPERANDS);
4035 return NULL;
4036 }
4037 /* Now parse operand adding info to 'i' as we go along. */
4038 END_STRING_AND_SAVE (l);
4039
4040 if (intel_syntax)
4041 operand_ok =
4042 i386_intel_operand (token_start,
4043 intel_float_operand (mnemonic));
4044 else
a7619375 4045 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4046
4047 RESTORE_END_STRING (l);
4048 if (!operand_ok)
4049 return NULL;
4050 }
4051 else
4052 {
4053 if (expecting_operand)
4054 {
4055 expecting_operand_after_comma:
4056 as_bad (_("expecting operand after ','; got nothing"));
4057 return NULL;
4058 }
4059 if (*l == ',')
4060 {
4061 as_bad (_("expecting operand before ','; got nothing"));
4062 return NULL;
4063 }
4064 }
7f3f1ea2 4065
29b0f896
AM		 4066 /* Now *l must be either ',' or END_OF_INSN. */
4067 if (*l == ',')
4068 {
4069 if (*++l == END_OF_INSN)
4070 {
4071 /* Just skip it, if it's \n complain. */
4072 goto expecting_operand_after_comma;
4073 }
4074 expecting_operand = 1;
4075 }
4076 }
4077 return l;
4078}
7f3f1ea2 4079
050dfa73 4080static void
4d456e3d 4081swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4082{
4083 union i386_op temp_op;
40fb9820 4084 i386_operand_type temp_type;
050dfa73 4085 enum bfd_reloc_code_real temp_reloc;
4eed87de 4086
050dfa73
MM		 4087 temp_type = i.types[xchg2];
4088 i.types[xchg2] = i.types[xchg1];
4089 i.types[xchg1] = temp_type;
4090 temp_op = i.op[xchg2];
4091 i.op[xchg2] = i.op[xchg1];
4092 i.op[xchg1] = temp_op;
4093 temp_reloc = i.reloc[xchg2];
4094 i.reloc[xchg2] = i.reloc[xchg1];
4095 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4096
4097 if (i.mask)
4098 {
4099 if (i.mask->operand == xchg1)
4100 i.mask->operand = xchg2;
4101 else if (i.mask->operand == xchg2)
4102 i.mask->operand = xchg1;
4103 }
4104 if (i.broadcast)
4105 {
4106 if (i.broadcast->operand == xchg1)
4107 i.broadcast->operand = xchg2;
4108 else if (i.broadcast->operand == xchg2)
4109 i.broadcast->operand = xchg1;
4110 }
4111 if (i.rounding)
4112 {
4113 if (i.rounding->operand == xchg1)
4114 i.rounding->operand = xchg2;
4115 else if (i.rounding->operand == xchg2)
4116 i.rounding->operand = xchg1;
4117 }
050dfa73
MM		 4118}
4119
29b0f896 4120static void
e3bb37b5 4121swap_operands (void)
29b0f896 4122{
b7c61d9a 4123 switch (i.operands)
050dfa73 4124 {
c0f3af97 4125 case 5:
b7c61d9a 4126 case 4:
4d456e3d 4127 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4128 case 3:
4129 case 2:
4d456e3d 4130 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4131 break;
4132 default:
4133 abort ();
29b0f896 4134 }
29b0f896
AM		 4135
4136 if (i.mem_operands == 2)
4137 {
4138 const seg_entry *temp_seg;
4139 temp_seg = i.seg[0];
4140 i.seg[0] = i.seg[1];
4141 i.seg[1] = temp_seg;
4142 }
4143}
252b5132 4144
29b0f896
AM		 4145/* Try to ensure constant immediates are represented in the smallest
4146 opcode possible. */
4147static void
e3bb37b5 4148optimize_imm (void)
29b0f896
AM		 4149{
4150 char guess_suffix = 0;
4151 int op;
252b5132 4152
29b0f896
AM		 4153 if (i.suffix)
4154 guess_suffix = i.suffix;
4155 else if (i.reg_operands)
4156 {
4157 /* Figure out a suffix from the last register operand specified.
4158 We can't do this properly yet, ie. excluding InOutPortReg,
4159 but the following works for instructions with immediates.
4160 In any case, we can't set i.suffix yet. */
4161 for (op = i.operands; --op >= 0;)
40fb9820 4162 if (i.types[op].bitfield.reg8)
7ab9ffdd 4163 {
40fb9820
L		 4164 guess_suffix = BYTE_MNEM_SUFFIX;
4165 break;
4166 }
4167 else if (i.types[op].bitfield.reg16)
252b5132 4168 {
40fb9820
L		 4169 guess_suffix = WORD_MNEM_SUFFIX;
4170 break;
4171 }
4172 else if (i.types[op].bitfield.reg32)
4173 {
4174 guess_suffix = LONG_MNEM_SUFFIX;
4175 break;
4176 }
4177 else if (i.types[op].bitfield.reg64)
4178 {
4179 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4180 break;
252b5132 4181 }
29b0f896
AM		 4182 }
4183 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4184 guess_suffix = WORD_MNEM_SUFFIX;
4185
4186 for (op = i.operands; --op >= 0;)
40fb9820 4187 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4188 {
4189 switch (i.op[op].imms->X_op)
252b5132 4190 {
29b0f896
AM		 4191 case O_constant:
4192 /* If a suffix is given, this operand may be shortened. */
4193 switch (guess_suffix)
252b5132 4194 {
29b0f896 4195 case LONG_MNEM_SUFFIX:
40fb9820
L		 4196 i.types[op].bitfield.imm32 = 1;
4197 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4198 break;
4199 case WORD_MNEM_SUFFIX:
40fb9820
L		 4200 i.types[op].bitfield.imm16 = 1;
4201 i.types[op].bitfield.imm32 = 1;
4202 i.types[op].bitfield.imm32s = 1;
4203 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4204 break;
4205 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4206 i.types[op].bitfield.imm8 = 1;
4207 i.types[op].bitfield.imm8s = 1;
4208 i.types[op].bitfield.imm16 = 1;
4209 i.types[op].bitfield.imm32 = 1;
4210 i.types[op].bitfield.imm32s = 1;
4211 i.types[op].bitfield.imm64 = 1;
29b0f896 4212 break;
252b5132 4213 }
252b5132 4214
29b0f896
AM		 4215 /* If this operand is at most 16 bits, convert it
4216 to a signed 16 bit number before trying to see
4217 whether it will fit in an even smaller size.
4218 This allows a 16-bit operand such as $0xffe0 to
4219 be recognised as within Imm8S range. */
40fb9820 4220 if ((i.types[op].bitfield.imm16)
29b0f896 4221 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4222 {
29b0f896
AM		 4223 i.op[op].imms->X_add_number =
4224 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4225 }
40fb9820 4226 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4227 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4228 == 0))
4229 {
4230 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4231 ^ ((offsetT) 1 << 31))
4232 - ((offsetT) 1 << 31));
4233 }
40fb9820 4234 i.types[op]
c6fb90c8
L		 4235 = operand_type_or (i.types[op],
4236 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4237
29b0f896
AM		 4238 /* We must avoid matching of Imm32 templates when 64bit
4239 only immediate is available. */
4240 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4241 i.types[op].bitfield.imm32 = 0;
29b0f896 4242 break;
252b5132 4243
29b0f896
AM		 4244 case O_absent:
4245 case O_register:
4246 abort ();
4247
4248 /* Symbols and expressions. */
4249 default:
9cd96992
JB		 4250 /* Convert symbolic operand to proper sizes for matching, but don't
4251 prevent matching a set of insns that only supports sizes other
4252 than those matching the insn suffix. */
4253 {
40fb9820 4254 i386_operand_type mask, allowed;
d3ce72d0 4255 const insn_template *t;
9cd96992 4256
0dfbf9d7
L		 4257 operand_type_set (&mask, 0);
4258 operand_type_set (&allowed, 0);
40fb9820 4259
4eed87de
AM		 4260 for (t = current_templates->start;
4261 t < current_templates->end;
4262 ++t)
c6fb90c8
L		 4263 allowed = operand_type_or (allowed,
4264 t->operand_types[op]);
9cd96992
JB		 4265 switch (guess_suffix)
4266 {
4267 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4268 mask.bitfield.imm64 = 1;
4269 mask.bitfield.imm32s = 1;
9cd96992
JB		 4270 break;
4271 case LONG_MNEM_SUFFIX:
40fb9820 4272 mask.bitfield.imm32 = 1;
9cd96992
JB		 4273 break;
4274 case WORD_MNEM_SUFFIX:
40fb9820 4275 mask.bitfield.imm16 = 1;
9cd96992
JB		 4276 break;
4277 case BYTE_MNEM_SUFFIX:
40fb9820 4278 mask.bitfield.imm8 = 1;
9cd96992
JB		 4279 break;
4280 default:
9cd96992
JB		 4281 break;
4282 }
c6fb90c8 4283 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4284 if (!operand_type_all_zero (&allowed))
c6fb90c8 4285 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4286 }
29b0f896 4287 break;
252b5132 4288 }
29b0f896
AM		 4289 }
4290}
47926f60 4291
29b0f896
AM		 4292/* Try to use the smallest displacement type too. */
4293static void
e3bb37b5 4294optimize_disp (void)
29b0f896
AM		 4295{
4296 int op;
3e73aa7c 4297
29b0f896 4298 for (op = i.operands; --op >= 0;)
40fb9820 4299 if (operand_type_check (i.types[op], disp))
252b5132 4300 {
b300c311 4301 if (i.op[op].disps->X_op == O_constant)
252b5132 4302 {
91d6fa6a 4303 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4304
40fb9820 4305 if (i.types[op].bitfield.disp16
91d6fa6a 4306 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4307 {
4308 /* If this operand is at most 16 bits, convert
4309 to a signed 16 bit number and don't use 64bit
4310 displacement. */
91d6fa6a 4311 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4312 i.types[op].bitfield.disp64 = 0;
b300c311 4313 }
40fb9820 4314 if (i.types[op].bitfield.disp32
91d6fa6a 4315 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4316 {
4317 /* If this operand is at most 32 bits, convert
4318 to a signed 32 bit number and don't use 64bit
4319 displacement. */
91d6fa6a
NC		 4320 op_disp &= (((offsetT) 2 << 31) - 1);
4321 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4322 i.types[op].bitfield.disp64 = 0;
b300c311 4323 }
91d6fa6a 4324 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4325 {
40fb9820
L		 4326 i.types[op].bitfield.disp8 = 0;
4327 i.types[op].bitfield.disp16 = 0;
4328 i.types[op].bitfield.disp32 = 0;
4329 i.types[op].bitfield.disp32s = 0;
4330 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4331 i.op[op].disps = 0;
4332 i.disp_operands--;
4333 }
4334 else if (flag_code == CODE_64BIT)
4335 {
91d6fa6a 4336 if (fits_in_signed_long (op_disp))
28a9d8f5 4337 {
40fb9820
L		 4338 i.types[op].bitfield.disp64 = 0;
4339 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4340 }
0e1147d9 4341 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4342 && fits_in_unsigned_long (op_disp))
40fb9820 4343 i.types[op].bitfield.disp32 = 1;
b300c311 4344 }
40fb9820
L		 4345 if ((i.types[op].bitfield.disp32
4346 || i.types[op].bitfield.disp32s
4347 || i.types[op].bitfield.disp16)
91d6fa6a 4348 && fits_in_signed_byte (op_disp))
40fb9820 4349 i.types[op].bitfield.disp8 = 1;
252b5132 4350 }
67a4f2b7
AO		 4351 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4352 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4353 {
4354 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4355 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4356 i.types[op].bitfield.disp8 = 0;
4357 i.types[op].bitfield.disp16 = 0;
4358 i.types[op].bitfield.disp32 = 0;
4359 i.types[op].bitfield.disp32s = 0;
4360 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4361 }
4362 else
b300c311 4363 /* We only support 64bit displacement on constants. */
40fb9820 4364 i.types[op].bitfield.disp64 = 0;
252b5132 4365 }
29b0f896
AM		 4366}
4367
6c30d220
L		 4368/* Check if operands are valid for the instruction. */
4369
4370static int
4371check_VecOperands (const insn_template *t)
4372{
43234a1e
L		 4373 unsigned int op;
4374
6c30d220
L		 4375 /* Without VSIB byte, we can't have a vector register for index. */
4376 if (!t->opcode_modifier.vecsib
4377 && i.index_reg
4378 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4379 || i.index_reg->reg_type.bitfield.regymm
4380 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4381 {
4382 i.error = unsupported_vector_index_register;
4383 return 1;
4384 }
4385
ad8ecc81
MZ		 4386 /* Check if default mask is allowed. */
4387 if (t->opcode_modifier.nodefmask
4388 && (!i.mask || i.mask->mask->reg_num == 0))
4389 {
4390 i.error = no_default_mask;
4391 return 1;
4392 }
4393
7bab8ab5
JB		 4394 /* For VSIB byte, we need a vector register for index, and all vector
4395 registers must be distinct. */
4396 if (t->opcode_modifier.vecsib)
4397 {
4398 if (!i.index_reg
6c30d220
L		 4399 || !((t->opcode_modifier.vecsib == VecSIB128
4400 && i.index_reg->reg_type.bitfield.regxmm)
4401 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4402 && i.index_reg->reg_type.bitfield.regymm)
4403 || (t->opcode_modifier.vecsib == VecSIB512
4404 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4405 {
4406 i.error = invalid_vsib_address;
4407 return 1;
4408 }
4409
43234a1e
L		 4410 gas_assert (i.reg_operands == 2 || i.mask);
4411 if (i.reg_operands == 2 && !i.mask)
4412 {
4413 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4414 || i.types[0].bitfield.regymm);
43234a1e 4415 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4416 || i.types[2].bitfield.regymm);
43234a1e
L		 4417 if (operand_check == check_none)
4418 return 0;
4419 if (register_number (i.op[0].regs)
4420 != register_number (i.index_reg)
4421 && register_number (i.op[2].regs)
4422 != register_number (i.index_reg)
4423 && register_number (i.op[0].regs)
4424 != register_number (i.op[2].regs))
4425 return 0;
4426 if (operand_check == check_error)
4427 {
4428 i.error = invalid_vector_register_set;
4429 return 1;
4430 }
4431 as_warn (_("mask, index, and destination registers should be distinct"));
4432 }
8444f82a
MZ		 4433 else if (i.reg_operands == 1 && i.mask)
4434 {
4435 if ((i.types[1].bitfield.regymm
4436 || i.types[1].bitfield.regzmm)
4437 && (register_number (i.op[1].regs)
4438 == register_number (i.index_reg)))
4439 {
4440 if (operand_check == check_error)
4441 {
4442 i.error = invalid_vector_register_set;
4443 return 1;
4444 }
4445 if (operand_check != check_none)
4446 as_warn (_("index and destination registers should be distinct"));
4447 }
4448 }
43234a1e 4449 }
7bab8ab5 4450
43234a1e
L		 4451 /* Check if broadcast is supported by the instruction and is applied
4452 to the memory operand. */
4453 if (i.broadcast)
4454 {
4455 int broadcasted_opnd_size;
4456
4457 /* Check if specified broadcast is supported in this instruction,
4458 and it's applied to memory operand of DWORD or QWORD type,
4459 depending on VecESize. */
4460 if (i.broadcast->type != t->opcode_modifier.broadcast
4461 || !i.types[i.broadcast->operand].bitfield.mem
4462 || (t->opcode_modifier.vecesize == 0
4463 && !i.types[i.broadcast->operand].bitfield.dword
4464 && !i.types[i.broadcast->operand].bitfield.unspecified)
4465 || (t->opcode_modifier.vecesize == 1
4466 && !i.types[i.broadcast->operand].bitfield.qword
4467 && !i.types[i.broadcast->operand].bitfield.unspecified))
4468 goto bad_broadcast;
4469
4470 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4471 if (i.broadcast->type == BROADCAST_1TO16)
4472 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4473 else if (i.broadcast->type == BROADCAST_1TO8)
4474 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4475 else if (i.broadcast->type == BROADCAST_1TO4)
4476 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4477 else if (i.broadcast->type == BROADCAST_1TO2)
4478 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4479 else
4480 goto bad_broadcast;
4481
4482 if ((broadcasted_opnd_size == 256
4483 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4484 || (broadcasted_opnd_size == 512
4485 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4486 {
4487 bad_broadcast:
4488 i.error = unsupported_broadcast;
4489 return 1;
4490 }
4491 }
4492 /* If broadcast is supported in this instruction, we need to check if
4493 operand of one-element size isn't specified without broadcast. */
4494 else if (t->opcode_modifier.broadcast && i.mem_operands)
4495 {
4496 /* Find memory operand. */
4497 for (op = 0; op < i.operands; op++)
4498 if (operand_type_check (i.types[op], anymem))
4499 break;
4500 gas_assert (op < i.operands);
4501 /* Check size of the memory operand. */
4502 if ((t->opcode_modifier.vecesize == 0
4503 && i.types[op].bitfield.dword)
4504 || (t->opcode_modifier.vecesize == 1
4505 && i.types[op].bitfield.qword))
4506 {
4507 i.error = broadcast_needed;
4508 return 1;
4509 }
4510 }
4511
4512 /* Check if requested masking is supported. */
4513 if (i.mask
4514 && (!t->opcode_modifier.masking
4515 || (i.mask->zeroing
4516 && t->opcode_modifier.masking == MERGING_MASKING)))
4517 {
4518 i.error = unsupported_masking;
4519 return 1;
4520 }
4521
4522 /* Check if masking is applied to dest operand. */
4523 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4524 {
4525 i.error = mask_not_on_destination;
4526 return 1;
4527 }
4528
43234a1e
L		 4529 /* Check RC/SAE. */
4530 if (i.rounding)
4531 {
4532 if ((i.rounding->type != saeonly
4533 && !t->opcode_modifier.staticrounding)
4534 || (i.rounding->type == saeonly
4535 && (t->opcode_modifier.staticrounding
4536 || !t->opcode_modifier.sae)))
4537 {
4538 i.error = unsupported_rc_sae;
4539 return 1;
4540 }
4541 /* If the instruction has several immediate operands and one of
4542 them is rounding, the rounding operand should be the last
4543 immediate operand. */
4544 if (i.imm_operands > 1
4545 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4546 {
43234a1e 4547 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4548 return 1;
4549 }
6c30d220
L		 4550 }
4551
43234a1e
L		 4552 /* Check vector Disp8 operand. */
4553 if (t->opcode_modifier.disp8memshift)
4554 {
4555 if (i.broadcast)
4556 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4557 else
4558 i.memshift = t->opcode_modifier.disp8memshift;
4559
4560 for (op = 0; op < i.operands; op++)
4561 if (operand_type_check (i.types[op], disp)
4562 && i.op[op].disps->X_op == O_constant)
4563 {
4564 offsetT value = i.op[op].disps->X_add_number;
4565 int vec_disp8_ok = fits_in_vec_disp8 (value);
4566 if (t->operand_types [op].bitfield.vec_disp8)
4567 {
4568 if (vec_disp8_ok)
4569 i.types[op].bitfield.vec_disp8 = 1;
4570 else
4571 {
4572 /* Vector insn can only have Vec_Disp8/Disp32 in
4573 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4574 mode. */
4575 i.types[op].bitfield.disp8 = 0;
4576 if (flag_code != CODE_16BIT)
4577 i.types[op].bitfield.disp16 = 0;
4578 }
4579 }
4580 else if (flag_code != CODE_16BIT)
4581 {
4582 /* One form of this instruction supports vector Disp8.
4583 Try vector Disp8 if we need to use Disp32. */
4584 if (vec_disp8_ok && !fits_in_signed_byte (value))
4585 {
4586 i.error = try_vector_disp8;
4587 return 1;
4588 }
4589 }
4590 }
4591 }
4592 else
4593 i.memshift = -1;
4594
6c30d220
L		 4595 return 0;
4596}
4597
43f3e2ee 4598/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4599 operand types. */
4600
4601static int
4602VEX_check_operands (const insn_template *t)
4603{
43234a1e
L		 4604 /* VREX is only valid with EVEX prefix. */
4605 if (i.need_vrex && !t->opcode_modifier.evex)
4606 {
4607 i.error = invalid_register_operand;
4608 return 1;
4609 }
4610
a683cc34
SP		 4611 if (!t->opcode_modifier.vex)
4612 return 0;
4613
4614 /* Only check VEX_Imm4, which must be the first operand. */
4615 if (t->operand_types[0].bitfield.vec_imm4)
4616 {
4617 if (i.op[0].imms->X_op != O_constant
4618 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4619 {
a65babc9 4620 i.error = bad_imm4;
891edac4
L		 4621 return 1;
4622 }
a683cc34
SP		 4623
4624 /* Turn off Imm8 so that update_imm won't complain. */
4625 i.types[0] = vec_imm4;
4626 }
4627
4628 return 0;
4629}
4630
d3ce72d0 4631static const insn_template *
e3bb37b5 4632match_template (void)
29b0f896
AM		 4633{
4634 /* Points to template once we've found it. */
d3ce72d0 4635 const insn_template *t;
40fb9820 4636 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4637 i386_operand_type overlap4;
29b0f896 4638 unsigned int found_reverse_match;
40fb9820
L		 4639 i386_opcode_modifier suffix_check;
4640 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4641 int addr_prefix_disp;
a5c311ca 4642 unsigned int j;
3629bb00 4643 unsigned int found_cpu_match;
45664ddb 4644 unsigned int check_register;
5614d22c 4645 enum i386_error specific_error = 0;
29b0f896 4646
c0f3af97
L		 4647#if MAX_OPERANDS != 5
4648# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4649#endif
4650
29b0f896 4651 found_reverse_match = 0;
539e75ad 4652 addr_prefix_disp = -1;
40fb9820
L		 4653
4654 memset (&suffix_check, 0, sizeof (suffix_check));
4655 if (i.suffix == BYTE_MNEM_SUFFIX)
4656 suffix_check.no_bsuf = 1;
4657 else if (i.suffix == WORD_MNEM_SUFFIX)
4658 suffix_check.no_wsuf = 1;
4659 else if (i.suffix == SHORT_MNEM_SUFFIX)
4660 suffix_check.no_ssuf = 1;
4661 else if (i.suffix == LONG_MNEM_SUFFIX)
4662 suffix_check.no_lsuf = 1;
4663 else if (i.suffix == QWORD_MNEM_SUFFIX)
4664 suffix_check.no_qsuf = 1;
4665 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4666 suffix_check.no_ldsuf = 1;
29b0f896 4667
01559ecc
L		 4668 /* Must have right number of operands. */
4669 i.error = number_of_operands_mismatch;
4670
45aa61fe 4671 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4672 {
539e75ad
L		 4673 addr_prefix_disp = -1;
4674
29b0f896
AM		 4675 if (i.operands != t->operands)
4676 continue;
4677
50aecf8c 4678 /* Check processor support. */
a65babc9 4679 i.error = unsupported;
c0f3af97
L		 4680 found_cpu_match = (cpu_flags_match (t)
4681 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4682 if (!found_cpu_match)
4683 continue;
4684
e1d4d893 4685 /* Check old gcc support. */
a65babc9 4686 i.error = old_gcc_only;
e1d4d893
L		 4687 if (!old_gcc && t->opcode_modifier.oldgcc)
4688 continue;
4689
4690 /* Check AT&T mnemonic. */
a65babc9 4691 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4692 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4693 continue;
4694
891edac4 4695 /* Check AT&T/Intel syntax. */
a65babc9 4696 i.error = unsupported_syntax;
5c07affc
L		 4697 if ((intel_syntax && t->opcode_modifier.attsyntax)
4698 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4699 continue;
4700
20592a94 4701 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4702 i.error = invalid_instruction_suffix;
567e4e96
L		 4703 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4704 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4705 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4706 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4707 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4708 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4709 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4710 continue;
4711
5c07affc 4712 if (!operand_size_match (t))
7d5e4556 4713 continue;
539e75ad 4714
5c07affc
L		 4715 for (j = 0; j < MAX_OPERANDS; j++)
4716 operand_types[j] = t->operand_types[j];
4717
45aa61fe
AM		 4718 /* In general, don't allow 64-bit operands in 32-bit mode. */
4719 if (i.suffix == QWORD_MNEM_SUFFIX
4720 && flag_code != CODE_64BIT
4721 && (intel_syntax
40fb9820 4722 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4723 && !intel_float_operand (t->name))
4724 : intel_float_operand (t->name) != 2)
40fb9820 4725 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4726 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4727 && !operand_types[0].bitfield.regymm
4728 && !operand_types[0].bitfield.regzmm)
40fb9820 4729 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4730 && operand_types[t->operands > 1].bitfield.regxmm
4731 && operand_types[t->operands > 1].bitfield.regymm
4732 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4733 && (t->base_opcode != 0x0fc7
4734 || t->extension_opcode != 1 /* cmpxchg8b */))
4735 continue;
4736
192dc9c6
JB		 4737 /* In general, don't allow 32-bit operands on pre-386. */
4738 else if (i.suffix == LONG_MNEM_SUFFIX
4739 && !cpu_arch_flags.bitfield.cpui386
4740 && (intel_syntax
4741 ? (!t->opcode_modifier.ignoresize
4742 && !intel_float_operand (t->name))
4743 : intel_float_operand (t->name) != 2)
4744 && ((!operand_types[0].bitfield.regmmx
4745 && !operand_types[0].bitfield.regxmm)
4746 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4747 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4748 continue;
4749
29b0f896 4750 /* Do not verify operands when there are none. */
50aecf8c 4751 else
29b0f896 4752 {
c6fb90c8 4753 if (!t->operands)
2dbab7d5
L		 4754 /* We've found a match; break out of loop. */
4755 break;
29b0f896 4756 }
252b5132 4757
539e75ad
L		 4758 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4759 into Disp32/Disp16/Disp32 operand. */
4760 if (i.prefix[ADDR_PREFIX] != 0)
4761 {
40fb9820 4762 /* There should be only one Disp operand. */
539e75ad
L		 4763 switch (flag_code)
4764 {
4765 case CODE_16BIT:
40fb9820
L		 4766 for (j = 0; j < MAX_OPERANDS; j++)
4767 {
4768 if (operand_types[j].bitfield.disp16)
4769 {
4770 addr_prefix_disp = j;
4771 operand_types[j].bitfield.disp32 = 1;
4772 operand_types[j].bitfield.disp16 = 0;
4773 break;
4774 }
4775 }
539e75ad
L		 4776 break;
4777 case CODE_32BIT:
40fb9820
L		 4778 for (j = 0; j < MAX_OPERANDS; j++)
4779 {
4780 if (operand_types[j].bitfield.disp32)
4781 {
4782 addr_prefix_disp = j;
4783 operand_types[j].bitfield.disp32 = 0;
4784 operand_types[j].bitfield.disp16 = 1;
4785 break;
4786 }
4787 }
539e75ad
L		 4788 break;
4789 case CODE_64BIT:
40fb9820
L		 4790 for (j = 0; j < MAX_OPERANDS; j++)
4791 {
4792 if (operand_types[j].bitfield.disp64)
4793 {
4794 addr_prefix_disp = j;
4795 operand_types[j].bitfield.disp64 = 0;
4796 operand_types[j].bitfield.disp32 = 1;
4797 break;
4798 }
4799 }
539e75ad
L		 4800 break;
4801 }
539e75ad
L		 4802 }
4803
56ffb741
L		 4804 /* We check register size if needed. */
4805 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4806 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4807 switch (t->operands)
4808 {
4809 case 1:
40fb9820 4810 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4811 continue;
4812 break;
4813 case 2:
8b38ad71
L		 4814 /* xchg %eax, %eax is a special case. It is an aliase for nop
4815 only in 32bit mode and we can use opcode 0x90. In 64bit
4816 mode, we can't use 0x90 for xchg %eax, %eax since it should
4817 zero-extend %eax to %rax. */
4818 if (flag_code == CODE_64BIT
4819 && t->base_opcode == 0x90
0dfbf9d7
L		 4820 && operand_type_equal (&i.types [0], &acc32)
4821 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4822 continue;
b6169b20
L		 4823 if (i.swap_operand)
4824 {
4825 /* If we swap operand in encoding, we either match
4826 the next one or reverse direction of operands. */
4827 if (t->opcode_modifier.s)
4828 continue;
4829 else if (t->opcode_modifier.d)
4830 goto check_reverse;
4831 }
4832
29b0f896 4833 case 3:
fa99fab2
L		 4834 /* If we swap operand in encoding, we match the next one. */
4835 if (i.swap_operand && t->opcode_modifier.s)
4836 continue;
f48ff2ae 4837 case 4:
c0f3af97 4838 case 5:
c6fb90c8 4839 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4840 if (!operand_type_match (overlap0, i.types[0])
4841 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4842 || (check_register
4843 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4844 operand_types[0],
4845 overlap1, i.types[1],
4846 operand_types[1])))
29b0f896
AM		 4847 {
4848 /* Check if other direction is valid ... */
40fb9820 4849 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4850 continue;
4851
b6169b20 4852check_reverse:
29b0f896 4853 /* Try reversing direction of operands. */
c6fb90c8
L		 4854 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4855 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4856 if (!operand_type_match (overlap0, i.types[0])
4857 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4858 || (check_register
4859 && !operand_type_register_match (overlap0,
4860 i.types[0],
4861 operand_types[1],
4862 overlap1,
4863 i.types[1],
4864 operand_types[0])))
29b0f896
AM		 4865 {
4866 /* Does not match either direction. */
4867 continue;
4868 }
4869 /* found_reverse_match holds which of D or FloatDR
4870 we've found. */
40fb9820 4871 if (t->opcode_modifier.d)
8a2ed489 4872 found_reverse_match = Opcode_D;
40fb9820 4873 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4874 found_reverse_match = Opcode_FloatD;
4875 else
4876 found_reverse_match = 0;
40fb9820 4877 if (t->opcode_modifier.floatr)
8a2ed489 4878 found_reverse_match |= Opcode_FloatR;
29b0f896 4879 }
f48ff2ae 4880 else
29b0f896 4881 {
f48ff2ae 4882 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4883 switch (t->operands)
4884 {
c0f3af97
L		 4885 case 5:
4886 overlap4 = operand_type_and (i.types[4],
4887 operand_types[4]);
d1cbb4db 4888 case 4:
c6fb90c8
L		 4889 overlap3 = operand_type_and (i.types[3],
4890 operand_types[3]);
d1cbb4db 4891 case 3:
c6fb90c8
L		 4892 overlap2 = operand_type_and (i.types[2],
4893 operand_types[2]);
d1cbb4db
L		 4894 break;
4895 }
29b0f896 4896
f48ff2ae
L		 4897 switch (t->operands)
4898 {
c0f3af97
L		 4899 case 5:
4900 if (!operand_type_match (overlap4, i.types[4])
4901 || !operand_type_register_match (overlap3,
4902 i.types[3],
4903 operand_types[3],
4904 overlap4,
4905 i.types[4],
4906 operand_types[4]))
4907 continue;
f48ff2ae 4908 case 4:
40fb9820 4909 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4910 || (check_register
4911 && !operand_type_register_match (overlap2,
4912 i.types[2],
4913 operand_types[2],
4914 overlap3,
4915 i.types[3],
4916 operand_types[3])))
f48ff2ae
L		 4917 continue;
4918 case 3:
4919 /* Here we make use of the fact that there are no
4920 reverse match 3 operand instructions, and all 3
4921 operand instructions only need to be checked for
4922 register consistency between operands 2 and 3. */
40fb9820 4923 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4924 || (check_register
4925 && !operand_type_register_match (overlap1,
4926 i.types[1],
4927 operand_types[1],
4928 overlap2,
4929 i.types[2],
4930 operand_types[2])))
f48ff2ae
L		 4931 continue;
4932 break;
4933 }
29b0f896 4934 }
f48ff2ae 4935 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4936 slip through to break. */
4937 }
3629bb00 4938 if (!found_cpu_match)
29b0f896
AM		 4939 {
4940 found_reverse_match = 0;
4941 continue;
4942 }
c0f3af97 4943
5614d22c
JB		 4944 /* Check if vector and VEX operands are valid. */
4945 if (check_VecOperands (t) || VEX_check_operands (t))
4946 {
4947 specific_error = i.error;
4948 continue;
4949 }
a683cc34 4950
29b0f896
AM		 4951 /* We've found a match; break out of loop. */
4952 break;
4953 }
4954
4955 if (t == current_templates->end)
4956 {
4957 /* We found no match. */
a65babc9 4958 const char *err_msg;
5614d22c 4959 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4960 {
4961 default:
4962 abort ();
86e026a4 4963 case operand_size_mismatch:
a65babc9
L		 4964 err_msg = _("operand size mismatch");
4965 break;
4966 case operand_type_mismatch:
4967 err_msg = _("operand type mismatch");
4968 break;
4969 case register_type_mismatch:
4970 err_msg = _("register type mismatch");
4971 break;
4972 case number_of_operands_mismatch:
4973 err_msg = _("number of operands mismatch");
4974 break;
4975 case invalid_instruction_suffix:
4976 err_msg = _("invalid instruction suffix");
4977 break;
4978 case bad_imm4:
4a2608e3 4979 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4980 break;
4981 case old_gcc_only:
4982 err_msg = _("only supported with old gcc");
4983 break;
4984 case unsupported_with_intel_mnemonic:
4985 err_msg = _("unsupported with Intel mnemonic");
4986 break;
4987 case unsupported_syntax:
4988 err_msg = _("unsupported syntax");
4989 break;
4990 case unsupported:
35262a23 4991 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4992 current_templates->start->name);
4993 return NULL;
6c30d220
L		 4994 case invalid_vsib_address:
4995 err_msg = _("invalid VSIB address");
4996 break;
7bab8ab5
JB		 4997 case invalid_vector_register_set:
4998 err_msg = _("mask, index, and destination registers must be distinct");
4999 break;
6c30d220
L		 5000 case unsupported_vector_index_register:
5001 err_msg = _("unsupported vector index register");
5002 break;
43234a1e
L		 5003 case unsupported_broadcast:
5004 err_msg = _("unsupported broadcast");
5005 break;
5006 case broadcast_not_on_src_operand:
5007 err_msg = _("broadcast not on source memory operand");
5008 break;
5009 case broadcast_needed:
5010 err_msg = _("broadcast is needed for operand of such type");
5011 break;
5012 case unsupported_masking:
5013 err_msg = _("unsupported masking");
5014 break;
5015 case mask_not_on_destination:
5016 err_msg = _("mask not on destination operand");
5017 break;
5018 case no_default_mask:
5019 err_msg = _("default mask isn't allowed");
5020 break;
5021 case unsupported_rc_sae:
5022 err_msg = _("unsupported static rounding/sae");
5023 break;
5024 case rc_sae_operand_not_last_imm:
5025 if (intel_syntax)
5026 err_msg = _("RC/SAE operand must precede immediate operands");
5027 else
5028 err_msg = _("RC/SAE operand must follow immediate operands");
5029 break;
5030 case invalid_register_operand:
5031 err_msg = _("invalid register operand");
5032 break;
a65babc9
L		 5033 }
5034 as_bad (_("%s for `%s'"), err_msg,
891edac4 5035 current_templates->start->name);
fa99fab2 5036 return NULL;
29b0f896 5037 }
252b5132 5038
29b0f896
AM		 5039 if (!quiet_warnings)
5040 {
5041 if (!intel_syntax
40fb9820
L		 5042 && (i.types[0].bitfield.jumpabsolute
5043 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5044 {
5045 as_warn (_("indirect %s without `*'"), t->name);
5046 }
5047
40fb9820
L		 5048 if (t->opcode_modifier.isprefix
5049 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5050 {
5051 /* Warn them that a data or address size prefix doesn't
5052 affect assembly of the next line of code. */
5053 as_warn (_("stand-alone `%s' prefix"), t->name);
5054 }
5055 }
5056
5057 /* Copy the template we found. */
5058 i.tm = *t;
539e75ad
L		 5059
5060 if (addr_prefix_disp != -1)
5061 i.tm.operand_types[addr_prefix_disp]
5062 = operand_types[addr_prefix_disp];
5063
29b0f896
AM		 5064 if (found_reverse_match)
5065 {
5066 /* If we found a reverse match we must alter the opcode
5067 direction bit. found_reverse_match holds bits to change
5068 (different for int & float insns). */
5069
5070 i.tm.base_opcode ^= found_reverse_match;
5071
539e75ad
L		 5072 i.tm.operand_types[0] = operand_types[1];
5073 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5074 }
5075
fa99fab2 5076 return t;
29b0f896
AM		 5077}
5078
5079static int
e3bb37b5 5080check_string (void)
29b0f896 5081{
40fb9820
L		 5082 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5083 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5084 {
5085 if (i.seg[0] != NULL && i.seg[0] != &es)
5086 {
a87af027 5087 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5088 i.tm.name,
a87af027
JB		 5089 mem_op + 1,
5090 register_prefix);
29b0f896
AM		 5091 return 0;
5092 }
5093 /* There's only ever one segment override allowed per instruction.
5094 This instruction possibly has a legal segment override on the
5095 second operand, so copy the segment to where non-string
5096 instructions store it, allowing common code. */
5097 i.seg[0] = i.seg[1];
5098 }
40fb9820 5099 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5100 {
5101 if (i.seg[1] != NULL && i.seg[1] != &es)
5102 {
a87af027 5103 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5104 i.tm.name,
a87af027
JB		 5105 mem_op + 2,
5106 register_prefix);
29b0f896
AM		 5107 return 0;
5108 }
5109 }
5110 return 1;
5111}
5112
5113static int
543613e9 5114process_suffix (void)
29b0f896
AM		 5115{
5116 /* If matched instruction specifies an explicit instruction mnemonic
5117 suffix, use it. */
40fb9820
L		 5118 if (i.tm.opcode_modifier.size16)
5119 i.suffix = WORD_MNEM_SUFFIX;
5120 else if (i.tm.opcode_modifier.size32)
5121 i.suffix = LONG_MNEM_SUFFIX;
5122 else if (i.tm.opcode_modifier.size64)
5123 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5124 else if (i.reg_operands)
5125 {
5126 /* If there's no instruction mnemonic suffix we try to invent one
5127 based on register operands. */
5128 if (!i.suffix)
5129 {
5130 /* We take i.suffix from the last register operand specified,
5131 Destination register type is more significant than source
381d071f
L		 5132 register type. crc32 in SSE4.2 prefers source register
5133 type. */
5134 if (i.tm.base_opcode == 0xf20f38f1)
5135 {
40fb9820
L		 5136 if (i.types[0].bitfield.reg16)
5137 i.suffix = WORD_MNEM_SUFFIX;
5138 else if (i.types[0].bitfield.reg32)
5139 i.suffix = LONG_MNEM_SUFFIX;
5140 else if (i.types[0].bitfield.reg64)
5141 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5142 }
9344ff29 5143 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5144 {
40fb9820 5145 if (i.types[0].bitfield.reg8)
20592a94
L		 5146 i.suffix = BYTE_MNEM_SUFFIX;
5147 }
381d071f
L		 5148
5149 if (!i.suffix)
5150 {
5151 int op;
5152
20592a94
L		 5153 if (i.tm.base_opcode == 0xf20f38f1
5154 || i.tm.base_opcode == 0xf20f38f0)
5155 {
5156 /* We have to know the operand size for crc32. */
5157 as_bad (_("ambiguous memory operand size for `%s`"),
5158 i.tm.name);
5159 return 0;
5160 }
5161
381d071f 5162 for (op = i.operands; --op >= 0;)
40fb9820 5163 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5164 {
40fb9820
L		 5165 if (i.types[op].bitfield.reg8)
5166 {
5167 i.suffix = BYTE_MNEM_SUFFIX;
5168 break;
5169 }
5170 else if (i.types[op].bitfield.reg16)
5171 {
5172 i.suffix = WORD_MNEM_SUFFIX;
5173 break;
5174 }
5175 else if (i.types[op].bitfield.reg32)
5176 {
5177 i.suffix = LONG_MNEM_SUFFIX;
5178 break;
5179 }
5180 else if (i.types[op].bitfield.reg64)
5181 {
5182 i.suffix = QWORD_MNEM_SUFFIX;
5183 break;
5184 }
381d071f
L		 5185 }
5186 }
29b0f896
AM		 5187 }
5188 else if (i.suffix == BYTE_MNEM_SUFFIX)
5189 {
2eb952a4
L		 5190 if (intel_syntax
5191 && i.tm.opcode_modifier.ignoresize
5192 && i.tm.opcode_modifier.no_bsuf)
5193 i.suffix = 0;
5194 else if (!check_byte_reg ())
29b0f896
AM		 5195 return 0;
5196 }
5197 else if (i.suffix == LONG_MNEM_SUFFIX)
5198 {
2eb952a4
L		 5199 if (intel_syntax
5200 && i.tm.opcode_modifier.ignoresize
5201 && i.tm.opcode_modifier.no_lsuf)
5202 i.suffix = 0;
5203 else if (!check_long_reg ())
29b0f896
AM		 5204 return 0;
5205 }
5206 else if (i.suffix == QWORD_MNEM_SUFFIX)
5207 {
955e1e6a
L		 5208 if (intel_syntax
5209 && i.tm.opcode_modifier.ignoresize
5210 && i.tm.opcode_modifier.no_qsuf)
5211 i.suffix = 0;
5212 else if (!check_qword_reg ())
29b0f896
AM		 5213 return 0;
5214 }
5215 else if (i.suffix == WORD_MNEM_SUFFIX)
5216 {
2eb952a4
L		 5217 if (intel_syntax
5218 && i.tm.opcode_modifier.ignoresize
5219 && i.tm.opcode_modifier.no_wsuf)
5220 i.suffix = 0;
5221 else if (!check_word_reg ())
29b0f896
AM		 5222 return 0;
5223 }
c0f3af97 5224 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5225 || i.suffix == YMMWORD_MNEM_SUFFIX
5226 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5227 {
43234a1e 5228 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5229 should check if it is a valid suffix. */
5230 }
40fb9820 5231 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5232 /* Do nothing if the instruction is going to ignore the prefix. */
5233 ;
5234 else
5235 abort ();
5236 }
40fb9820 5237 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5238 && !i.suffix
5239 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5240 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5241 {
5242 i.suffix = stackop_size;
5243 }
9306ca4a
JB		 5244 else if (intel_syntax
5245 && !i.suffix
40fb9820
L		 5246 && (i.tm.operand_types[0].bitfield.jumpabsolute
5247 || i.tm.opcode_modifier.jumpbyte
5248 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5249 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5250 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5251 {
5252 switch (flag_code)
5253 {
5254 case CODE_64BIT:
40fb9820 5255 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5256 {
5257 i.suffix = QWORD_MNEM_SUFFIX;
5258 break;
5259 }
5260 case CODE_32BIT:
40fb9820 5261 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5262 i.suffix = LONG_MNEM_SUFFIX;
5263 break;
5264 case CODE_16BIT:
40fb9820 5265 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5266 i.suffix = WORD_MNEM_SUFFIX;
5267 break;
5268 }
5269 }
252b5132 5270
9306ca4a 5271 if (!i.suffix)
29b0f896 5272 {
9306ca4a
JB		 5273 if (!intel_syntax)
5274 {
40fb9820 5275 if (i.tm.opcode_modifier.w)
9306ca4a 5276 {
4eed87de
AM		 5277 as_bad (_("no instruction mnemonic suffix given and "
5278 "no register operands; can't size instruction"));
9306ca4a
JB		 5279 return 0;
5280 }
5281 }
5282 else
5283 {
40fb9820 5284 unsigned int suffixes;
7ab9ffdd 5285
40fb9820
L		 5286 suffixes = !i.tm.opcode_modifier.no_bsuf;
5287 if (!i.tm.opcode_modifier.no_wsuf)
5288 suffixes |= 1 << 1;
5289 if (!i.tm.opcode_modifier.no_lsuf)
5290 suffixes |= 1 << 2;
fc4adea1 5291 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5292 suffixes |= 1 << 3;
5293 if (!i.tm.opcode_modifier.no_ssuf)
5294 suffixes |= 1 << 4;
5295 if (!i.tm.opcode_modifier.no_qsuf)
5296 suffixes |= 1 << 5;
5297
5298 /* There are more than suffix matches. */
5299 if (i.tm.opcode_modifier.w
9306ca4a 5300 || ((suffixes & (suffixes - 1))
40fb9820
L		 5301 && !i.tm.opcode_modifier.defaultsize
5302 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5303 {
5304 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5305 return 0;
5306 }
5307 }
29b0f896 5308 }
252b5132 5309
9306ca4a
JB		 5310 /* Change the opcode based on the operand size given by i.suffix;
5311 We don't need to change things for byte insns. */
5312
582d5edd
L		 5313 if (i.suffix
5314 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5315 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5316 && i.suffix != YMMWORD_MNEM_SUFFIX
5317 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5318 {
5319 /* It's not a byte, select word/dword operation. */
40fb9820 5320 if (i.tm.opcode_modifier.w)
29b0f896 5321 {
40fb9820 5322 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5323 i.tm.base_opcode |= 8;
5324 else
5325 i.tm.base_opcode |= 1;
5326 }
0f3f3d8b 5327
29b0f896
AM		 5328 /* Now select between word & dword operations via the operand
5329 size prefix, except for instructions that will ignore this
5330 prefix anyway. */
ca61edf2 5331 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5332 {
ca61edf2
L		 5333 /* The address size override prefix changes the size of the
5334 first operand. */
40fb9820
L		 5335 if ((flag_code == CODE_32BIT
5336 && i.op->regs[0].reg_type.bitfield.reg16)
5337 || (flag_code != CODE_32BIT
5338 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5339 if (!add_prefix (ADDR_PREFIX_OPCODE))
5340 return 0;
5341 }
5342 else if (i.suffix != QWORD_MNEM_SUFFIX
5343 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5344 && !i.tm.opcode_modifier.ignoresize
5345 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5346 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5347 || (flag_code == CODE_64BIT
40fb9820 5348 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5349 {
5350 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5351
40fb9820 5352 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5353 prefix = ADDR_PREFIX_OPCODE;
252b5132 5354
29b0f896
AM		 5355 if (!add_prefix (prefix))
5356 return 0;
24eab124 5357 }
252b5132 5358
29b0f896
AM		 5359 /* Set mode64 for an operand. */
5360 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5361 && flag_code == CODE_64BIT
40fb9820 5362 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5363 {
5364 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5365 need rex64. cmpxchg8b is also a special case. */
5366 if (! (i.operands == 2
5367 && i.tm.base_opcode == 0x90
5368 && i.tm.extension_opcode == None
0dfbf9d7
L		 5369 && operand_type_equal (&i.types [0], &acc64)
5370 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5371 && ! (i.operands == 1
5372 && i.tm.base_opcode == 0xfc7
5373 && i.tm.extension_opcode == 1
40fb9820
L		 5374 && !operand_type_check (i.types [0], reg)
5375 && operand_type_check (i.types [0], anymem)))
f6bee062 5376 i.rex |= REX_W;
46e883c5 5377 }
3e73aa7c 5378
29b0f896
AM		 5379 /* Size floating point instruction. */
5380 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5381 if (i.tm.opcode_modifier.floatmf)
543613e9 5382 i.tm.base_opcode ^= 4;
29b0f896 5383 }
7ecd2f8b 5384
29b0f896
AM		 5385 return 1;
5386}
3e73aa7c 5387
29b0f896 5388static int
543613e9 5389check_byte_reg (void)
29b0f896
AM		 5390{
5391 int op;
543613e9 5392
29b0f896
AM		 5393 for (op = i.operands; --op >= 0;)
5394 {
5395 /* If this is an eight bit register, it's OK. If it's the 16 or
5396 32 bit version of an eight bit register, we will just use the
5397 low portion, and that's OK too. */
40fb9820 5398 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5399 continue;
5400
5a819eb9
JB		 5401 /* I/O port address operands are OK too. */
5402 if (i.tm.operand_types[op].bitfield.inoutportreg)
5403 continue;
5404
9344ff29
L		 5405 /* crc32 doesn't generate this warning. */
5406 if (i.tm.base_opcode == 0xf20f38f0)
5407 continue;
5408
40fb9820
L		 5409 if ((i.types[op].bitfield.reg16
5410 || i.types[op].bitfield.reg32
5411 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5412 && i.op[op].regs->reg_num < 4
5413 /* Prohibit these changes in 64bit mode, since the lowering
5414 would be more complicated. */
5415 && flag_code != CODE_64BIT)
29b0f896 5416 {
29b0f896 5417#if REGISTER_WARNINGS
5a819eb9 5418 if (!quiet_warnings)
a540244d
L		 5419 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5420 register_prefix,
40fb9820 5421 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5422 ? REGNAM_AL - REGNAM_AX
5423 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5424 register_prefix,
29b0f896
AM		 5425 i.op[op].regs->reg_name,
5426 i.suffix);
5427#endif
5428 continue;
5429 }
5430 /* Any other register is bad. */
40fb9820
L		 5431 if (i.types[op].bitfield.reg16
5432 || i.types[op].bitfield.reg32
5433 || i.types[op].bitfield.reg64
5434 || i.types[op].bitfield.regmmx
5435 || i.types[op].bitfield.regxmm
c0f3af97 5436 || i.types[op].bitfield.regymm
43234a1e 5437 || i.types[op].bitfield.regzmm
40fb9820
L		 5438 || i.types[op].bitfield.sreg2
5439 || i.types[op].bitfield.sreg3
5440 || i.types[op].bitfield.control
5441 || i.types[op].bitfield.debug
5442 || i.types[op].bitfield.test
5443 || i.types[op].bitfield.floatreg
5444 || i.types[op].bitfield.floatacc)
29b0f896 5445 {
a540244d
L		 5446 as_bad (_("`%s%s' not allowed with `%s%c'"),
5447 register_prefix,
29b0f896
AM		 5448 i.op[op].regs->reg_name,
5449 i.tm.name,
5450 i.suffix);
5451 return 0;
5452 }
5453 }
5454 return 1;
5455}
5456
5457static int
e3bb37b5 5458check_long_reg (void)
29b0f896
AM		 5459{
5460 int op;
5461
5462 for (op = i.operands; --op >= 0;)
5463 /* Reject eight bit registers, except where the template requires
5464 them. (eg. movzb) */
40fb9820
L		 5465 if (i.types[op].bitfield.reg8
5466 && (i.tm.operand_types[op].bitfield.reg16
5467 || i.tm.operand_types[op].bitfield.reg32
5468 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5469 {
a540244d
L		 5470 as_bad (_("`%s%s' not allowed with `%s%c'"),
5471 register_prefix,
29b0f896
AM		 5472 i.op[op].regs->reg_name,
5473 i.tm.name,
5474 i.suffix);
5475 return 0;
5476 }
e4630f71 5477 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5478 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5479 && i.types[op].bitfield.reg16
5480 && (i.tm.operand_types[op].bitfield.reg32
5481 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5482 {
5483 /* Prohibit these changes in the 64bit mode, since the
5484 lowering is more complicated. */
5485 if (flag_code == CODE_64BIT)
252b5132 5486 {
2b5d6a91 5487 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5488 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5489 i.suffix);
5490 return 0;
252b5132 5491 }
29b0f896 5492#if REGISTER_WARNINGS
cecf1424
JB		 5493 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5494 register_prefix,
5495 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5496 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5497#endif
252b5132 5498 }
e4630f71 5499 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5500 else if (i.types[op].bitfield.reg64
5501 && (i.tm.operand_types[op].bitfield.reg32
5502 || i.tm.operand_types[op].bitfield.acc))
252b5132 5503 {
34828aad 5504 if (intel_syntax
ca61edf2 5505 && i.tm.opcode_modifier.toqword
40fb9820 5506 && !i.types[0].bitfield.regxmm)
34828aad 5507 {
ca61edf2 5508 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5509 i.suffix = QWORD_MNEM_SUFFIX;
5510 }
5511 else
5512 {
2b5d6a91 5513 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5514 register_prefix, i.op[op].regs->reg_name,
5515 i.suffix);
5516 return 0;
5517 }
29b0f896
AM		 5518 }
5519 return 1;
5520}
252b5132 5521
29b0f896 5522static int
e3bb37b5 5523check_qword_reg (void)
29b0f896
AM		 5524{
5525 int op;
252b5132 5526
29b0f896
AM		 5527 for (op = i.operands; --op >= 0; )
5528 /* Reject eight bit registers, except where the template requires
5529 them. (eg. movzb) */
40fb9820
L		 5530 if (i.types[op].bitfield.reg8
5531 && (i.tm.operand_types[op].bitfield.reg16
5532 || i.tm.operand_types[op].bitfield.reg32
5533 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5534 {
a540244d
L		 5535 as_bad (_("`%s%s' not allowed with `%s%c'"),
5536 register_prefix,
29b0f896
AM		 5537 i.op[op].regs->reg_name,
5538 i.tm.name,
5539 i.suffix);
5540 return 0;
5541 }
e4630f71 5542 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5543 else if ((i.types[op].bitfield.reg16
5544 || i.types[op].bitfield.reg32)
5545 && (i.tm.operand_types[op].bitfield.reg32
5546 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5547 {
5548 /* Prohibit these changes in the 64bit mode, since the
5549 lowering is more complicated. */
34828aad 5550 if (intel_syntax
ca61edf2 5551 && i.tm.opcode_modifier.todword
40fb9820 5552 && !i.types[0].bitfield.regxmm)
34828aad 5553 {
ca61edf2 5554 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5555 i.suffix = LONG_MNEM_SUFFIX;
5556 }
5557 else
5558 {
2b5d6a91 5559 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5560 register_prefix, i.op[op].regs->reg_name,
5561 i.suffix);
5562 return 0;
5563 }
252b5132 5564 }
29b0f896
AM		 5565 return 1;
5566}
252b5132 5567
29b0f896 5568static int
e3bb37b5 5569check_word_reg (void)
29b0f896
AM		 5570{
5571 int op;
5572 for (op = i.operands; --op >= 0;)
5573 /* Reject eight bit registers, except where the template requires
5574 them. (eg. movzb) */
40fb9820
L		 5575 if (i.types[op].bitfield.reg8
5576 && (i.tm.operand_types[op].bitfield.reg16
5577 || i.tm.operand_types[op].bitfield.reg32
5578 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5579 {
a540244d
L		 5580 as_bad (_("`%s%s' not allowed with `%s%c'"),
5581 register_prefix,
29b0f896
AM		 5582 i.op[op].regs->reg_name,
5583 i.tm.name,
5584 i.suffix);
5585 return 0;
5586 }
e4630f71 5587 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5588 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5589 && (i.types[op].bitfield.reg32
5590 || i.types[op].bitfield.reg64)
40fb9820
L		 5591 && (i.tm.operand_types[op].bitfield.reg16
5592 || i.tm.operand_types[op].bitfield.acc))
252b5132 5593 {
29b0f896
AM		 5594 /* Prohibit these changes in the 64bit mode, since the
5595 lowering is more complicated. */
5596 if (flag_code == CODE_64BIT)
252b5132 5597 {
2b5d6a91 5598 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5599 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5600 i.suffix);
5601 return 0;
252b5132 5602 }
29b0f896 5603#if REGISTER_WARNINGS
cecf1424
JB		 5604 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5605 register_prefix,
5606 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5607 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5608#endif
5609 }
5610 return 1;
5611}
252b5132 5612
29b0f896 5613static int
40fb9820 5614update_imm (unsigned int j)
29b0f896 5615{
bc0844ae 5616 i386_operand_type overlap = i.types[j];
40fb9820
L		 5617 if ((overlap.bitfield.imm8
5618 || overlap.bitfield.imm8s
5619 || overlap.bitfield.imm16
5620 || overlap.bitfield.imm32
5621 || overlap.bitfield.imm32s
5622 || overlap.bitfield.imm64)
0dfbf9d7
L		 5623 && !operand_type_equal (&overlap, &imm8)
5624 && !operand_type_equal (&overlap, &imm8s)
5625 && !operand_type_equal (&overlap, &imm16)
5626 && !operand_type_equal (&overlap, &imm32)
5627 && !operand_type_equal (&overlap, &imm32s)
5628 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5629 {
5630 if (i.suffix)
5631 {
40fb9820
L		 5632 i386_operand_type temp;
5633
0dfbf9d7 5634 operand_type_set (&temp, 0);
7ab9ffdd 5635 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5636 {
5637 temp.bitfield.imm8 = overlap.bitfield.imm8;
5638 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5639 }
5640 else if (i.suffix == WORD_MNEM_SUFFIX)
5641 temp.bitfield.imm16 = overlap.bitfield.imm16;
5642 else if (i.suffix == QWORD_MNEM_SUFFIX)
5643 {
5644 temp.bitfield.imm64 = overlap.bitfield.imm64;
5645 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5646 }
5647 else
5648 temp.bitfield.imm32 = overlap.bitfield.imm32;
5649 overlap = temp;
29b0f896 5650 }
0dfbf9d7
L		 5651 else if (operand_type_equal (&overlap, &imm16_32_32s)
5652 || operand_type_equal (&overlap, &imm16_32)
5653 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5654 {
40fb9820 5655 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5656 overlap = imm16;
40fb9820 5657 else
65da13b5 5658 overlap = imm32s;
29b0f896 5659 }
0dfbf9d7
L		 5660 if (!operand_type_equal (&overlap, &imm8)
5661 && !operand_type_equal (&overlap, &imm8s)
5662 && !operand_type_equal (&overlap, &imm16)
5663 && !operand_type_equal (&overlap, &imm32)
5664 && !operand_type_equal (&overlap, &imm32s)
5665 && !operand_type_equal (&overlap, &imm64))
29b0f896 5666 {
4eed87de
AM		 5667 as_bad (_("no instruction mnemonic suffix given; "
5668 "can't determine immediate size"));
29b0f896
AM		 5669 return 0;
5670 }
5671 }
40fb9820 5672 i.types[j] = overlap;
29b0f896 5673
40fb9820
L		 5674 return 1;
5675}
5676
5677static int
5678finalize_imm (void)
5679{
bc0844ae 5680 unsigned int j, n;
29b0f896 5681
bc0844ae
L		 5682 /* Update the first 2 immediate operands. */
5683 n = i.operands > 2 ? 2 : i.operands;
5684 if (n)
5685 {
5686 for (j = 0; j < n; j++)
5687 if (update_imm (j) == 0)
5688 return 0;
40fb9820 5689
bc0844ae
L		 5690 /* The 3rd operand can't be immediate operand. */
5691 gas_assert (operand_type_check (i.types[2], imm) == 0);
5692 }
29b0f896
AM		 5693
5694 return 1;
5695}
5696
c0f3af97
L		 5697static int
5698bad_implicit_operand (int xmm)
5699{
91d6fa6a
NC		 5700 const char *ireg = xmm ? "xmm0" : "ymm0";
5701
c0f3af97
L		 5702 if (intel_syntax)
5703 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5704 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5705 else
5706 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5707 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5708 return 0;
5709}
5710
29b0f896 5711static int
e3bb37b5 5712process_operands (void)
29b0f896
AM		 5713{
5714 /* Default segment register this instruction will use for memory
5715 accesses. 0 means unknown. This is only for optimizing out
5716 unnecessary segment overrides. */
5717 const seg_entry *default_seg = 0;
5718
2426c15f 5719 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5720 {
91d6fa6a
NC		 5721 unsigned int dupl = i.operands;
5722 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5723 unsigned int j;
5724
c0f3af97 5725 /* The destination must be an xmm register. */
9c2799c2 5726 gas_assert (i.reg_operands
91d6fa6a 5727 && MAX_OPERANDS > dupl
7ab9ffdd 5728 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5729
5730 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5731 {
c0f3af97 5732 /* The first operand is implicit and must be xmm0. */
9c2799c2 5733 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5734 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5735 return bad_implicit_operand (1);
5736
8cd7925b 5737 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5738 {
5739 /* Keep xmm0 for instructions with VEX prefix and 3
5740 sources. */
5741 goto duplicate;
5742 }
e2ec9d29 5743 else
c0f3af97
L		 5744 {
5745 /* We remove the first xmm0 and keep the number of
5746 operands unchanged, which in fact duplicates the
5747 destination. */
5748 for (j = 1; j < i.operands; j++)
5749 {
5750 i.op[j - 1] = i.op[j];
5751 i.types[j - 1] = i.types[j];
5752 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5753 }
5754 }
5755 }
5756 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5757 {
91d6fa6a 5758 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5759 && (i.tm.opcode_modifier.vexsources
5760 == VEX3SOURCES));
c0f3af97
L		 5761
5762 /* Add the implicit xmm0 for instructions with VEX prefix
5763 and 3 sources. */
5764 for (j = i.operands; j > 0; j--)
5765 {
5766 i.op[j] = i.op[j - 1];
5767 i.types[j] = i.types[j - 1];
5768 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5769 }
5770 i.op[0].regs
5771 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5772 i.types[0] = regxmm;
c0f3af97
L		 5773 i.tm.operand_types[0] = regxmm;
5774
5775 i.operands += 2;
5776 i.reg_operands += 2;
5777 i.tm.operands += 2;
5778
91d6fa6a 5779 dupl++;
c0f3af97 5780 dest++;
91d6fa6a
NC		 5781 i.op[dupl] = i.op[dest];
5782 i.types[dupl] = i.types[dest];
5783 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5784 }
c0f3af97
L		 5785 else
5786 {
5787duplicate:
5788 i.operands++;
5789 i.reg_operands++;
5790 i.tm.operands++;
5791
91d6fa6a
NC		 5792 i.op[dupl] = i.op[dest];
5793 i.types[dupl] = i.types[dest];
5794 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5795 }
5796
5797 if (i.tm.opcode_modifier.immext)
5798 process_immext ();
5799 }
5800 else if (i.tm.opcode_modifier.firstxmm0)
5801 {
5802 unsigned int j;
5803
43234a1e 5804 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5805 gas_assert (i.reg_operands
7ab9ffdd 5806 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5807 || operand_type_equal (&i.types[0], &regymm)
5808 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5809 if (register_number (i.op[0].regs) != 0)
c0f3af97 5810 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5811
5812 for (j = 1; j < i.operands; j++)
5813 {
5814 i.op[j - 1] = i.op[j];
5815 i.types[j - 1] = i.types[j];
5816
5817 /* We need to adjust fields in i.tm since they are used by
5818 build_modrm_byte. */
5819 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5820 }
5821
e2ec9d29
L		 5822 i.operands--;
5823 i.reg_operands--;
e2ec9d29
L		 5824 i.tm.operands--;
5825 }
5826 else if (i.tm.opcode_modifier.regkludge)
5827 {
5828 /* The imul $imm, %reg instruction is converted into
5829 imul $imm, %reg, %reg, and the clr %reg instruction
5830 is converted into xor %reg, %reg. */
5831
5832 unsigned int first_reg_op;
5833
5834 if (operand_type_check (i.types[0], reg))
5835 first_reg_op = 0;
5836 else
5837 first_reg_op = 1;
5838 /* Pretend we saw the extra register operand. */
9c2799c2 5839 gas_assert (i.reg_operands == 1
7ab9ffdd 5840 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5841 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5842 i.types[first_reg_op + 1] = i.types[first_reg_op];
5843 i.operands++;
5844 i.reg_operands++;
29b0f896
AM		 5845 }
5846
40fb9820 5847 if (i.tm.opcode_modifier.shortform)
29b0f896 5848 {
40fb9820
L		 5849 if (i.types[0].bitfield.sreg2
5850 || i.types[0].bitfield.sreg3)
29b0f896 5851 {
4eed87de
AM		 5852 if (i.tm.base_opcode == POP_SEG_SHORT
5853 && i.op[0].regs->reg_num == 1)
29b0f896 5854 {
a87af027 5855 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5856 return 0;
29b0f896 5857 }
4eed87de
AM		 5858 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5859 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5860 i.rex |= REX_B;
4eed87de
AM		 5861 }
5862 else
5863 {
7ab9ffdd 5864 /* The register or float register operand is in operand
85f10a01 5865 0 or 1. */
40fb9820 5866 unsigned int op;
7ab9ffdd
L		 5867
5868 if (i.types[0].bitfield.floatreg
5869 || operand_type_check (i.types[0], reg))
5870 op = 0;
5871 else
5872 op = 1;
4eed87de
AM		 5873 /* Register goes in low 3 bits of opcode. */
5874 i.tm.base_opcode |= i.op[op].regs->reg_num;
5875 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5876 i.rex |= REX_B;
40fb9820 5877 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5878 {
4eed87de
AM		 5879 /* Warn about some common errors, but press on regardless.
5880 The first case can be generated by gcc (<= 2.8.1). */
5881 if (i.operands == 2)
5882 {
5883 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5884 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5885 register_prefix, i.op[!intel_syntax].regs->reg_name,
5886 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5887 }
5888 else
5889 {
5890 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5891 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5892 register_prefix, i.op[0].regs->reg_name);
4eed87de 5893 }
29b0f896
AM		 5894 }
5895 }
5896 }
40fb9820 5897 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5898 {
5899 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5900 must be put into the modrm byte). Now, we make the modrm and
5901 index base bytes based on all the info we've collected. */
29b0f896
AM		 5902
5903 default_seg = build_modrm_byte ();
5904 }
8a2ed489 5905 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5906 {
5907 default_seg = &ds;
5908 }
40fb9820 5909 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5910 {
5911 /* For the string instructions that allow a segment override
5912 on one of their operands, the default segment is ds. */
5913 default_seg = &ds;
5914 }
5915
75178d9d
L		 5916 if (i.tm.base_opcode == 0x8d /* lea */
5917 && i.seg[0]
5918 && !quiet_warnings)
30123838 5919 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5920
5921 /* If a segment was explicitly specified, and the specified segment
5922 is not the default, use an opcode prefix to select it. If we
5923 never figured out what the default segment is, then default_seg
5924 will be zero at this point, and the specified segment prefix will
5925 always be used. */
29b0f896
AM		 5926 if ((i.seg[0]) && (i.seg[0] != default_seg))
5927 {
5928 if (!add_prefix (i.seg[0]->seg_prefix))
5929 return 0;
5930 }
5931 return 1;
5932}
5933
5934static const seg_entry *
e3bb37b5 5935build_modrm_byte (void)
29b0f896
AM		 5936{
5937 const seg_entry *default_seg = 0;
c0f3af97 5938 unsigned int source, dest;
8cd7925b 5939 int vex_3_sources;
c0f3af97
L		 5940
5941 /* The first operand of instructions with VEX prefix and 3 sources
5942 must be VEX_Imm4. */
8cd7925b 5943 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5944 if (vex_3_sources)
5945 {
91d6fa6a 5946 unsigned int nds, reg_slot;
4c2c6516 5947 expressionS *exp;
c0f3af97 5948
922d8de8 5949 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5950 && i.tm.opcode_modifier.immext)
5951 {
5952 dest = i.operands - 2;
5953 gas_assert (dest == 3);
5954 }
922d8de8 5955 else
a683cc34 5956 dest = i.operands - 1;
c0f3af97 5957 nds = dest - 1;
922d8de8 5958
a683cc34
SP		 5959 /* There are 2 kinds of instructions:
5960 1. 5 operands: 4 register operands or 3 register operands
5961 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5962 VexW0 or VexW1. The destination must be either XMM, YMM or
5963 ZMM register.
a683cc34
SP		 5964 2. 4 operands: 4 register operands or 3 register operands
5965 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5966 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5967 || (i.reg_operands == 3 && i.mem_operands == 1))
5968 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5969 && (i.tm.opcode_modifier.veximmext
5970 || (i.imm_operands == 1
5971 && i.types[0].bitfield.vec_imm4
5972 && (i.tm.opcode_modifier.vexw == VEXW0
5973 || i.tm.opcode_modifier.vexw == VEXW1)
5974 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5975 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5976 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5977
5978 if (i.imm_operands == 0)
5979 {
5980 /* When there is no immediate operand, generate an 8bit
5981 immediate operand to encode the first operand. */
5982 exp = &im_expressions[i.imm_operands++];
5983 i.op[i.operands].imms = exp;
5984 i.types[i.operands] = imm8;
5985 i.operands++;
5986 /* If VexW1 is set, the first operand is the source and
5987 the second operand is encoded in the immediate operand. */
5988 if (i.tm.opcode_modifier.vexw == VEXW1)
5989 {
5990 source = 0;
5991 reg_slot = 1;
5992 }
5993 else
5994 {
5995 source = 1;
5996 reg_slot = 0;
5997 }
5998
5999 /* FMA swaps REG and NDS. */
6000 if (i.tm.cpu_flags.bitfield.cpufma)
6001 {
6002 unsigned int tmp;
6003 tmp = reg_slot;
6004 reg_slot = nds;
6005 nds = tmp;
6006 }
6007
24981e7b
L		 6008 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6009 &regxmm)
a683cc34 6010 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6011 &regymm)
6012 || operand_type_equal (&i.tm.operand_types[reg_slot],
6013 &regzmm));
a683cc34 6014 exp->X_op = O_constant;
4c692bc7 6015 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6016 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6017 }
922d8de8 6018 else
a683cc34
SP		 6019 {
6020 unsigned int imm_slot;
6021
6022 if (i.tm.opcode_modifier.vexw == VEXW0)
6023 {
6024 /* If VexW0 is set, the third operand is the source and
6025 the second operand is encoded in the immediate
6026 operand. */
6027 source = 2;
6028 reg_slot = 1;
6029 }
6030 else
6031 {
6032 /* VexW1 is set, the second operand is the source and
6033 the third operand is encoded in the immediate
6034 operand. */
6035 source = 1;
6036 reg_slot = 2;
6037 }
6038
6039 if (i.tm.opcode_modifier.immext)
6040 {
6041 /* When ImmExt is set, the immdiate byte is the last
6042 operand. */
6043 imm_slot = i.operands - 1;
6044 source--;
6045 reg_slot--;
6046 }
6047 else
6048 {
6049 imm_slot = 0;
6050
6051 /* Turn on Imm8 so that output_imm will generate it. */
6052 i.types[imm_slot].bitfield.imm8 = 1;
6053 }
6054
24981e7b
L		 6055 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6056 &regxmm)
6057 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6058 &regymm)
6059 || operand_type_equal (&i.tm.operand_types[reg_slot],
6060 &regzmm));
a683cc34 6061 i.op[imm_slot].imms->X_add_number
4c692bc7 6062 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6063 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6064 }
6065
6066 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6067 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6068 &regymm)
6069 || operand_type_equal (&i.tm.operand_types[nds],
6070 &regzmm));
dae39acc 6071 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6072 }
6073 else
6074 source = dest = 0;
29b0f896
AM		 6075
6076 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6077 implicit registers do not count. If there are 3 register
6078 operands, it must be a instruction with VexNDS. For a
6079 instruction with VexNDD, the destination register is encoded
6080 in VEX prefix. If there are 4 register operands, it must be
6081 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6082 if (i.mem_operands == 0
6083 && ((i.reg_operands == 2
2426c15f 6084 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6085 || (i.reg_operands == 3
2426c15f 6086 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6087 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6088 {
cab737b9
L		 6089 switch (i.operands)
6090 {
6091 case 2:
6092 source = 0;
6093 break;
6094 case 3:
c81128dc
L		 6095 /* When there are 3 operands, one of them may be immediate,
6096 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6097 the first operand must be shift count register (cl) or it
6098 is an instruction with VexNDS. */
9c2799c2 6099 gas_assert (i.imm_operands == 1
7ab9ffdd 6100 || (i.imm_operands == 0
2426c15f 6101 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6102 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6103 if (operand_type_check (i.types[0], imm)
6104 || i.types[0].bitfield.shiftcount)
6105 source = 1;
6106 else
6107 source = 0;
cab737b9
L		 6108 break;
6109 case 4:
368d64cc
L		 6110 /* When there are 4 operands, the first two must be 8bit
6111 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6112 one.
6113
6114 For instructions with VexNDS, if the first operand
6115 an imm8, the source operand is the 2nd one. If the last
6116 operand is imm8, the source operand is the first one. */
9c2799c2 6117 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6118 && i.types[0].bitfield.imm8
6119 && i.types[1].bitfield.imm8)
2426c15f 6120 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6121 && i.imm_operands == 1
6122 && (i.types[0].bitfield.imm8
43234a1e
L		 6123 || i.types[i.operands - 1].bitfield.imm8
6124 || i.rounding)));
9f2670f2
L		 6125 if (i.imm_operands == 2)
6126 source = 2;
6127 else
c0f3af97
L		 6128 {
6129 if (i.types[0].bitfield.imm8)
6130 source = 1;
6131 else
6132 source = 0;
6133 }
c0f3af97
L		 6134 break;
6135 case 5:
43234a1e
L		 6136 if (i.tm.opcode_modifier.evex)
6137 {
6138 /* For EVEX instructions, when there are 5 operands, the
6139 first one must be immediate operand. If the second one
6140 is immediate operand, the source operand is the 3th
6141 one. If the last one is immediate operand, the source
6142 operand is the 2nd one. */
6143 gas_assert (i.imm_operands == 2
6144 && i.tm.opcode_modifier.sae
6145 && operand_type_check (i.types[0], imm));
6146 if (operand_type_check (i.types[1], imm))
6147 source = 2;
6148 else if (operand_type_check (i.types[4], imm))
6149 source = 1;
6150 else
6151 abort ();
6152 }
cab737b9
L		 6153 break;
6154 default:
6155 abort ();
6156 }
6157
c0f3af97
L		 6158 if (!vex_3_sources)
6159 {
6160 dest = source + 1;
6161
43234a1e
L		 6162 /* RC/SAE operand could be between DEST and SRC. That happens
6163 when one operand is GPR and the other one is XMM/YMM/ZMM
6164 register. */
6165 if (i.rounding && i.rounding->operand == (int) dest)
6166 dest++;
6167
2426c15f 6168 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6169 {
43234a1e
L		 6170 /* For instructions with VexNDS, the register-only source
6171 operand must be 32/64bit integer, XMM, YMM or ZMM
6172 register. It is encoded in VEX prefix. We need to
6173 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6174
6175 i386_operand_type op;
6176 unsigned int vvvv;
6177
6178 /* Check register-only source operand when two source
6179 operands are swapped. */
6180 if (!i.tm.operand_types[source].bitfield.baseindex
6181 && i.tm.operand_types[dest].bitfield.baseindex)
6182 {
6183 vvvv = source;
6184 source = dest;
6185 }
6186 else
6187 vvvv = dest;
6188
6189 op = i.tm.operand_types[vvvv];
fa99fab2 6190 op.bitfield.regmem = 0;
c0f3af97 6191 if ((dest + 1) >= i.operands
ac4eb736
AM		 6192 || (!op.bitfield.reg32
6193 && op.bitfield.reg64
f12dc422 6194 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6195 && !operand_type_equal (&op, &regymm)
6196 && !operand_type_equal (&op, &regzmm)
6197 && !operand_type_equal (&op, &regmask)))
c0f3af97 6198 abort ();
f12dc422 6199 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6200 dest++;
6201 }
6202 }
29b0f896
AM		 6203
6204 i.rm.mode = 3;
6205 /* One of the register operands will be encoded in the i.tm.reg
6206 field, the other in the combined i.tm.mode and i.tm.regmem
6207 fields. If no form of this instruction supports a memory
6208 destination operand, then we assume the source operand may
6209 sometimes be a memory operand and so we need to store the
6210 destination in the i.rm.reg field. */
40fb9820
L		 6211 if (!i.tm.operand_types[dest].bitfield.regmem
6212 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6213 {
6214 i.rm.reg = i.op[dest].regs->reg_num;
6215 i.rm.regmem = i.op[source].regs->reg_num;
6216 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6217 i.rex |= REX_R;
43234a1e
L		 6218 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6219 i.vrex |= REX_R;
29b0f896 6220 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6221 i.rex |= REX_B;
43234a1e
L		 6222 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6223 i.vrex |= REX_B;
29b0f896
AM		 6224 }
6225 else
6226 {
6227 i.rm.reg = i.op[source].regs->reg_num;
6228 i.rm.regmem = i.op[dest].regs->reg_num;
6229 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6230 i.rex |= REX_B;
43234a1e
L		 6231 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6232 i.vrex |= REX_B;
29b0f896 6233 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6234 i.rex |= REX_R;
43234a1e
L		 6235 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6236 i.vrex |= REX_R;
29b0f896 6237 }
161a04f6 6238 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6239 {
40fb9820
L		 6240 if (!i.types[0].bitfield.control
6241 && !i.types[1].bitfield.control)
c4a530c5 6242 abort ();
161a04f6 6243 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6244 add_prefix (LOCK_PREFIX_OPCODE);
6245 }
29b0f896
AM		 6246 }
6247 else
6248 { /* If it's not 2 reg operands... */
c0f3af97
L		 6249 unsigned int mem;
6250
29b0f896
AM		 6251 if (i.mem_operands)
6252 {
6253 unsigned int fake_zero_displacement = 0;
99018f42 6254 unsigned int op;
4eed87de 6255
7ab9ffdd
L		 6256 for (op = 0; op < i.operands; op++)
6257 if (operand_type_check (i.types[op], anymem))
6258 break;
7ab9ffdd 6259 gas_assert (op < i.operands);
29b0f896 6260
6c30d220
L		 6261 if (i.tm.opcode_modifier.vecsib)
6262 {
6263 if (i.index_reg->reg_num == RegEiz
6264 || i.index_reg->reg_num == RegRiz)
6265 abort ();
6266
6267 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6268 if (!i.base_reg)
6269 {
6270 i.sib.base = NO_BASE_REGISTER;
6271 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6272 /* No Vec_Disp8 if there is no base. */
6273 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6274 i.types[op].bitfield.disp8 = 0;
6275 i.types[op].bitfield.disp16 = 0;
6276 i.types[op].bitfield.disp64 = 0;
6277 if (flag_code != CODE_64BIT)
6278 {
6279 /* Must be 32 bit */
6280 i.types[op].bitfield.disp32 = 1;
6281 i.types[op].bitfield.disp32s = 0;
6282 }
6283 else
6284 {
6285 i.types[op].bitfield.disp32 = 0;
6286 i.types[op].bitfield.disp32s = 1;
6287 }
6288 }
6289 i.sib.index = i.index_reg->reg_num;
6290 if ((i.index_reg->reg_flags & RegRex) != 0)
6291 i.rex |= REX_X;
43234a1e
L		 6292 if ((i.index_reg->reg_flags & RegVRex) != 0)
6293 i.vrex |= REX_X;
6c30d220
L		 6294 }
6295
29b0f896
AM		 6296 default_seg = &ds;
6297
6298 if (i.base_reg == 0)
6299 {
6300 i.rm.mode = 0;
6301 if (!i.disp_operands)
6c30d220
L		 6302 {
6303 fake_zero_displacement = 1;
6304 /* Instructions with VSIB byte need 32bit displacement
6305 if there is no base register. */
6306 if (i.tm.opcode_modifier.vecsib)
6307 i.types[op].bitfield.disp32 = 1;
6308 }
29b0f896
AM		 6309 if (i.index_reg == 0)
6310 {
6c30d220 6311 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6312 /* Operand is just <disp> */
20f0a1fc 6313 if (flag_code == CODE_64BIT)
29b0f896
AM		 6314 {
6315 /* 64bit mode overwrites the 32bit absolute
6316 addressing by RIP relative addressing and
6317 absolute addressing is encoded by one of the
6318 redundant SIB forms. */
6319 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6320 i.sib.base = NO_BASE_REGISTER;
6321 i.sib.index = NO_INDEX_REGISTER;
fc225355 6322 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6323 ? disp32s : disp32);
20f0a1fc 6324 }
fc225355
L		 6325 else if ((flag_code == CODE_16BIT)
6326 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6327 {
6328 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6329 i.types[op] = disp16;
20f0a1fc
NC		 6330 }
6331 else
6332 {
6333 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6334 i.types[op] = disp32;
29b0f896
AM		 6335 }
6336 }
6c30d220 6337 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6338 {
6c30d220 6339 /* !i.base_reg && i.index_reg */
db51cc60
L		 6340 if (i.index_reg->reg_num == RegEiz
6341 || i.index_reg->reg_num == RegRiz)
6342 i.sib.index = NO_INDEX_REGISTER;
6343 else
6344 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6345 i.sib.base = NO_BASE_REGISTER;
6346 i.sib.scale = i.log2_scale_factor;
6347 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6348 /* No Vec_Disp8 if there is no base. */
6349 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6350 i.types[op].bitfield.disp8 = 0;
6351 i.types[op].bitfield.disp16 = 0;
6352 i.types[op].bitfield.disp64 = 0;
29b0f896 6353 if (flag_code != CODE_64BIT)
40fb9820
L		 6354 {
6355 /* Must be 32 bit */
6356 i.types[op].bitfield.disp32 = 1;
6357 i.types[op].bitfield.disp32s = 0;
6358 }
29b0f896 6359 else
40fb9820
L		 6360 {
6361 i.types[op].bitfield.disp32 = 0;
6362 i.types[op].bitfield.disp32s = 1;
6363 }
29b0f896 6364 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6365 i.rex |= REX_X;
29b0f896
AM		 6366 }
6367 }
6368 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6369 else if (i.base_reg->reg_num == RegRip ||
6370 i.base_reg->reg_num == RegEip)
29b0f896 6371 {
6c30d220 6372 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6373 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6374 i.types[op].bitfield.disp8 = 0;
6375 i.types[op].bitfield.disp16 = 0;
6376 i.types[op].bitfield.disp32 = 0;
6377 i.types[op].bitfield.disp32s = 1;
6378 i.types[op].bitfield.disp64 = 0;
43234a1e 6379 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6380 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6381 if (! i.disp_operands)
6382 fake_zero_displacement = 1;
29b0f896 6383 }
40fb9820 6384 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6385 {
6c30d220 6386 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6387 switch (i.base_reg->reg_num)
6388 {
6389 case 3: /* (%bx) */
6390 if (i.index_reg == 0)
6391 i.rm.regmem = 7;
6392 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6393 i.rm.regmem = i.index_reg->reg_num - 6;
6394 break;
6395 case 5: /* (%bp) */
6396 default_seg = &ss;
6397 if (i.index_reg == 0)
6398 {
6399 i.rm.regmem = 6;
40fb9820 6400 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6401 {
6402 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6403 if (i.tm.operand_types[op].bitfield.vec_disp8)
6404 i.types[op].bitfield.vec_disp8 = 1;
6405 else
6406 i.types[op].bitfield.disp8 = 1;
252b5132 6407 fake_zero_displacement = 1;
29b0f896
AM		 6408 }
6409 }
6410 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6411 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6412 break;
6413 default: /* (%si) -> 4 or (%di) -> 5 */
6414 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6415 }
6416 i.rm.mode = mode_from_disp_size (i.types[op]);
6417 }
6418 else /* i.base_reg and 32/64 bit mode */
6419 {
6420 if (flag_code == CODE_64BIT
40fb9820
L		 6421 && operand_type_check (i.types[op], disp))
6422 {
6423 i386_operand_type temp;
0dfbf9d7 6424 operand_type_set (&temp, 0);
40fb9820 6425 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6426 temp.bitfield.vec_disp8
6427 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6428 i.types[op] = temp;
6429 if (i.prefix[ADDR_PREFIX] == 0)
6430 i.types[op].bitfield.disp32s = 1;
6431 else
6432 i.types[op].bitfield.disp32 = 1;
6433 }
20f0a1fc 6434
6c30d220
L		 6435 if (!i.tm.opcode_modifier.vecsib)
6436 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6437 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6438 i.rex |= REX_B;
29b0f896
AM		 6439 i.sib.base = i.base_reg->reg_num;
6440 /* x86-64 ignores REX prefix bit here to avoid decoder
6441 complications. */
848930b2
JB		 6442 if (!(i.base_reg->reg_flags & RegRex)
6443 && (i.base_reg->reg_num == EBP_REG_NUM
6444 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6445 default_seg = &ss;
848930b2 6446 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6447 {
848930b2 6448 fake_zero_displacement = 1;
43234a1e
L		 6449 if (i.tm.operand_types [op].bitfield.vec_disp8)
6450 i.types[op].bitfield.vec_disp8 = 1;
6451 else
6452 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6453 }
6454 i.sib.scale = i.log2_scale_factor;
6455 if (i.index_reg == 0)
6456 {
6c30d220 6457 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6458 /* <disp>(%esp) becomes two byte modrm with no index
6459 register. We've already stored the code for esp
6460 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6461 Any base register besides %esp will not use the
6462 extra modrm byte. */
6463 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6464 }
6c30d220 6465 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6466 {
db51cc60
L		 6467 if (i.index_reg->reg_num == RegEiz
6468 || i.index_reg->reg_num == RegRiz)
6469 i.sib.index = NO_INDEX_REGISTER;
6470 else
6471 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6472 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6473 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6474 i.rex |= REX_X;
29b0f896 6475 }
67a4f2b7
AO		 6476
6477 if (i.disp_operands
6478 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6479 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6480 i.rm.mode = 0;
6481 else
a501d77e
L		 6482 {
6483 if (!fake_zero_displacement
6484 && !i.disp_operands
6485 && i.disp_encoding)
6486 {
6487 fake_zero_displacement = 1;
6488 if (i.disp_encoding == disp_encoding_8bit)
6489 i.types[op].bitfield.disp8 = 1;
6490 else
6491 i.types[op].bitfield.disp32 = 1;
6492 }
6493 i.rm.mode = mode_from_disp_size (i.types[op]);
6494 }
29b0f896 6495 }
252b5132 6496
29b0f896
AM		 6497 if (fake_zero_displacement)
6498 {
6499 /* Fakes a zero displacement assuming that i.types[op]
6500 holds the correct displacement size. */
6501 expressionS *exp;
6502
9c2799c2 6503 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6504 exp = &disp_expressions[i.disp_operands++];
6505 i.op[op].disps = exp;
6506 exp->X_op = O_constant;
6507 exp->X_add_number = 0;
6508 exp->X_add_symbol = (symbolS *) 0;
6509 exp->X_op_symbol = (symbolS *) 0;
6510 }
c0f3af97
L		 6511
6512 mem = op;
29b0f896 6513 }
c0f3af97
L		 6514 else
6515 mem = ~0;
252b5132 6516
8c43a48b 6517 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6518 {
6519 if (operand_type_check (i.types[0], imm))
6520 i.vex.register_specifier = NULL;
6521 else
6522 {
6523 /* VEX.vvvv encodes one of the sources when the first
6524 operand is not an immediate. */
1ef99a7b 6525 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6526 i.vex.register_specifier = i.op[0].regs;
6527 else
6528 i.vex.register_specifier = i.op[1].regs;
6529 }
6530
6531 /* Destination is a XMM register encoded in the ModRM.reg
6532 and VEX.R bit. */
6533 i.rm.reg = i.op[2].regs->reg_num;
6534 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6535 i.rex |= REX_R;
6536
6537 /* ModRM.rm and VEX.B encodes the other source. */
6538 if (!i.mem_operands)
6539 {
6540 i.rm.mode = 3;
6541
1ef99a7b 6542 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6543 i.rm.regmem = i.op[1].regs->reg_num;
6544 else
6545 i.rm.regmem = i.op[0].regs->reg_num;
6546
6547 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6548 i.rex |= REX_B;
6549 }
6550 }
2426c15f 6551 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6552 {
6553 i.vex.register_specifier = i.op[2].regs;
6554 if (!i.mem_operands)
6555 {
6556 i.rm.mode = 3;
6557 i.rm.regmem = i.op[1].regs->reg_num;
6558 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6559 i.rex |= REX_B;
6560 }
6561 }
29b0f896
AM		 6562 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6563 (if any) based on i.tm.extension_opcode. Again, we must be
6564 careful to make sure that segment/control/debug/test/MMX
6565 registers are coded into the i.rm.reg field. */
f88c9eb0 6566 else if (i.reg_operands)
29b0f896 6567 {
99018f42 6568 unsigned int op;
7ab9ffdd
L		 6569 unsigned int vex_reg = ~0;
6570
6571 for (op = 0; op < i.operands; op++)
6572 if (i.types[op].bitfield.reg8
6573 || i.types[op].bitfield.reg16
6574 || i.types[op].bitfield.reg32
6575 || i.types[op].bitfield.reg64
6576 || i.types[op].bitfield.regmmx
6577 || i.types[op].bitfield.regxmm
6578 || i.types[op].bitfield.regymm
7e8b059b 6579 || i.types[op].bitfield.regbnd
43234a1e
L		 6580 || i.types[op].bitfield.regzmm
6581 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6582 || i.types[op].bitfield.sreg2
6583 || i.types[op].bitfield.sreg3
6584 || i.types[op].bitfield.control
6585 || i.types[op].bitfield.debug
6586 || i.types[op].bitfield.test)
6587 break;
c0209578 6588
7ab9ffdd
L		 6589 if (vex_3_sources)
6590 op = dest;
2426c15f 6591 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6592 {
6593 /* For instructions with VexNDS, the register-only
6594 source operand is encoded in VEX prefix. */
6595 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6596
7ab9ffdd 6597 if (op > mem)
c0f3af97 6598 {
7ab9ffdd
L		 6599 vex_reg = op++;
6600 gas_assert (op < i.operands);
c0f3af97
L		 6601 }
6602 else
c0f3af97 6603 {
f12dc422
L		 6604 /* Check register-only source operand when two source
6605 operands are swapped. */
6606 if (!i.tm.operand_types[op].bitfield.baseindex
6607 && i.tm.operand_types[op + 1].bitfield.baseindex)
6608 {
6609 vex_reg = op;
6610 op += 2;
6611 gas_assert (mem == (vex_reg + 1)
6612 && op < i.operands);
6613 }
6614 else
6615 {
6616 vex_reg = op + 1;
6617 gas_assert (vex_reg < i.operands);
6618 }
c0f3af97 6619 }
7ab9ffdd 6620 }
2426c15f 6621 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6622 {
f12dc422 6623 /* For instructions with VexNDD, the register destination
7ab9ffdd 6624 is encoded in VEX prefix. */
f12dc422
L		 6625 if (i.mem_operands == 0)
6626 {
6627 /* There is no memory operand. */
6628 gas_assert ((op + 2) == i.operands);
6629 vex_reg = op + 1;
6630 }
6631 else
8d63c93e 6632 {
f12dc422
L		 6633 /* There are only 2 operands. */
6634 gas_assert (op < 2 && i.operands == 2);
6635 vex_reg = 1;
6636 }
7ab9ffdd
L		 6637 }
6638 else
6639 gas_assert (op < i.operands);
99018f42 6640
7ab9ffdd
L		 6641 if (vex_reg != (unsigned int) ~0)
6642 {
f12dc422 6643 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6644
f12dc422
L		 6645 if (type->bitfield.reg32 != 1
6646 && type->bitfield.reg64 != 1
6647 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6648 && !operand_type_equal (type, &regymm)
6649 && !operand_type_equal (type, &regzmm)
6650 && !operand_type_equal (type, &regmask))
7ab9ffdd 6651 abort ();
f88c9eb0 6652
7ab9ffdd
L		 6653 i.vex.register_specifier = i.op[vex_reg].regs;
6654 }
6655
1b9f0c97
L		 6656 /* Don't set OP operand twice. */
6657 if (vex_reg != op)
7ab9ffdd 6658 {
1b9f0c97
L		 6659 /* If there is an extension opcode to put here, the
6660 register number must be put into the regmem field. */
6661 if (i.tm.extension_opcode != None)
6662 {
6663 i.rm.regmem = i.op[op].regs->reg_num;
6664 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6665 i.rex |= REX_B;
43234a1e
L		 6666 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6667 i.vrex |= REX_B;
1b9f0c97
L		 6668 }
6669 else
6670 {
6671 i.rm.reg = i.op[op].regs->reg_num;
6672 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6673 i.rex |= REX_R;
43234a1e
L		 6674 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6675 i.vrex |= REX_R;
1b9f0c97 6676 }
7ab9ffdd 6677 }
252b5132 6678
29b0f896
AM		 6679 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6680 must set it to 3 to indicate this is a register operand
6681 in the regmem field. */
6682 if (!i.mem_operands)
6683 i.rm.mode = 3;
6684 }
252b5132 6685
29b0f896 6686 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6687 if (i.tm.extension_opcode != None)
29b0f896
AM		 6688 i.rm.reg = i.tm.extension_opcode;
6689 }
6690 return default_seg;
6691}
252b5132 6692
29b0f896 6693static void
e3bb37b5 6694output_branch (void)
29b0f896
AM		 6695{
6696 char *p;
f8a5c266 6697 int size;
29b0f896
AM		 6698 int code16;
6699 int prefix;
6700 relax_substateT subtype;
6701 symbolS *sym;
6702 offsetT off;
6703
f8a5c266 6704 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6705 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6706
6707 prefix = 0;
6708 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6709 {
29b0f896
AM		 6710 prefix = 1;
6711 i.prefixes -= 1;
6712 code16 ^= CODE16;
252b5132 6713 }
29b0f896
AM		 6714 /* Pentium4 branch hints. */
6715 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6716 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6717 {
29b0f896
AM		 6718 prefix++;
6719 i.prefixes--;
6720 }
6721 if (i.prefix[REX_PREFIX] != 0)
6722 {
6723 prefix++;
6724 i.prefixes--;
2f66722d
AM		 6725 }
6726
7e8b059b
L		 6727 /* BND prefixed jump. */
6728 if (i.prefix[BND_PREFIX] != 0)
6729 {
6730 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6731 i.prefixes -= 1;
6732 }
6733
29b0f896
AM		 6734 if (i.prefixes != 0 && !intel_syntax)
6735 as_warn (_("skipping prefixes on this instruction"));
6736
6737 /* It's always a symbol; End frag & setup for relax.
6738 Make sure there is enough room in this frag for the largest
6739 instruction we may generate in md_convert_frag. This is 2
6740 bytes for the opcode and room for the prefix and largest
6741 displacement. */
6742 frag_grow (prefix + 2 + 4);
6743 /* Prefix and 1 opcode byte go in fr_fix. */
6744 p = frag_more (prefix + 1);
6745 if (i.prefix[DATA_PREFIX] != 0)
6746 *p++ = DATA_PREFIX_OPCODE;
6747 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6748 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6749 *p++ = i.prefix[SEG_PREFIX];
6750 if (i.prefix[REX_PREFIX] != 0)
6751 *p++ = i.prefix[REX_PREFIX];
6752 *p = i.tm.base_opcode;
6753
6754 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6755 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6756 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6757 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6758 else
f8a5c266 6759 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6760 subtype |= code16;
3e73aa7c 6761
29b0f896
AM		 6762 sym = i.op[0].disps->X_add_symbol;
6763 off = i.op[0].disps->X_add_number;
3e73aa7c 6764
29b0f896
AM		 6765 if (i.op[0].disps->X_op != O_constant
6766 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6767 {
29b0f896
AM		 6768 /* Handle complex expressions. */
6769 sym = make_expr_symbol (i.op[0].disps);
6770 off = 0;
6771 }
3e73aa7c 6772
29b0f896
AM		 6773 /* 1 possible extra opcode + 4 byte displacement go in var part.
6774 Pass reloc in fr_var. */
c3320543
L		 6775 frag_var (rs_machine_dependent, 5,
6776 ((!object_64bit
6777 || i.reloc[0] != NO_RELOC
6778 || (i.bnd_prefix == NULL && !add_bnd_prefix))
6779 ? i.reloc[0]
6780 : BFD_RELOC_X86_64_PC32_BND),
6781 subtype, sym, off, p);
29b0f896 6782}
3e73aa7c 6783
29b0f896 6784static void
e3bb37b5 6785output_jump (void)
29b0f896
AM		 6786{
6787 char *p;
6788 int size;
3e02c1cc 6789 fixS *fixP;
29b0f896 6790
40fb9820 6791 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6792 {
6793 /* This is a loop or jecxz type instruction. */
6794 size = 1;
6795 if (i.prefix[ADDR_PREFIX] != 0)
6796 {
6797 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6798 i.prefixes -= 1;
6799 }
6800 /* Pentium4 branch hints. */
6801 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6802 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6803 {
6804 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6805 i.prefixes--;
3e73aa7c
JH		 6806 }
6807 }
29b0f896
AM		 6808 else
6809 {
6810 int code16;
3e73aa7c 6811
29b0f896
AM		 6812 code16 = 0;
6813 if (flag_code == CODE_16BIT)
6814 code16 = CODE16;
3e73aa7c 6815
29b0f896
AM		 6816 if (i.prefix[DATA_PREFIX] != 0)
6817 {
6818 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6819 i.prefixes -= 1;
6820 code16 ^= CODE16;
6821 }
252b5132 6822
29b0f896
AM		 6823 size = 4;
6824 if (code16)
6825 size = 2;
6826 }
9fcc94b6 6827
29b0f896
AM		 6828 if (i.prefix[REX_PREFIX] != 0)
6829 {
6830 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6831 i.prefixes -= 1;
6832 }
252b5132 6833
7e8b059b
L		 6834 /* BND prefixed jump. */
6835 if (i.prefix[BND_PREFIX] != 0)
6836 {
6837 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6838 i.prefixes -= 1;
6839 }
6840
29b0f896
AM		 6841 if (i.prefixes != 0 && !intel_syntax)
6842 as_warn (_("skipping prefixes on this instruction"));
e0890092 6843
42164a71
L		 6844 p = frag_more (i.tm.opcode_length + size);
6845 switch (i.tm.opcode_length)
6846 {
6847 case 2:
6848 *p++ = i.tm.base_opcode >> 8;
6849 case 1:
6850 *p++ = i.tm.base_opcode;
6851 break;
6852 default:
6853 abort ();
6854 }
e0890092 6855
3e02c1cc 6856 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
c3320543
L		 6857 i.op[0].disps, 1, reloc (size, 1, 1,
6858 (i.bnd_prefix != NULL
6859 || add_bnd_prefix),
6860 i.reloc[0]));
3e02c1cc
AM		 6861
6862 /* All jumps handled here are signed, but don't use a signed limit
6863 check for 32 and 16 bit jumps as we want to allow wrap around at
6864 4G and 64k respectively. */
6865 if (size == 1)
6866 fixP->fx_signed = 1;
29b0f896 6867}
e0890092 6868
29b0f896 6869static void
e3bb37b5 6870output_interseg_jump (void)
29b0f896
AM		 6871{
6872 char *p;
6873 int size;
6874 int prefix;
6875 int code16;
252b5132 6876
29b0f896
AM		 6877 code16 = 0;
6878 if (flag_code == CODE_16BIT)
6879 code16 = CODE16;
a217f122 6880
29b0f896
AM		 6881 prefix = 0;
6882 if (i.prefix[DATA_PREFIX] != 0)
6883 {
6884 prefix = 1;
6885 i.prefixes -= 1;
6886 code16 ^= CODE16;
6887 }
6888 if (i.prefix[REX_PREFIX] != 0)
6889 {
6890 prefix++;
6891 i.prefixes -= 1;
6892 }
252b5132 6893
29b0f896
AM		 6894 size = 4;
6895 if (code16)
6896 size = 2;
252b5132 6897
29b0f896
AM		 6898 if (i.prefixes != 0 && !intel_syntax)
6899 as_warn (_("skipping prefixes on this instruction"));
252b5132 6900
29b0f896
AM		 6901 /* 1 opcode; 2 segment; offset */
6902 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6903
29b0f896
AM		 6904 if (i.prefix[DATA_PREFIX] != 0)
6905 *p++ = DATA_PREFIX_OPCODE;
252b5132 6906
29b0f896
AM		 6907 if (i.prefix[REX_PREFIX] != 0)
6908 *p++ = i.prefix[REX_PREFIX];
252b5132 6909
29b0f896
AM		 6910 *p++ = i.tm.base_opcode;
6911 if (i.op[1].imms->X_op == O_constant)
6912 {
6913 offsetT n = i.op[1].imms->X_add_number;
252b5132 6914
29b0f896
AM		 6915 if (size == 2
6916 && !fits_in_unsigned_word (n)
6917 && !fits_in_signed_word (n))
6918 {
6919 as_bad (_("16-bit jump out of range"));
6920 return;
6921 }
6922 md_number_to_chars (p, n, size);
6923 }
6924 else
6925 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
c3320543 6926 i.op[1].imms, 0, reloc (size, 0, 0, 0, i.reloc[1]));
29b0f896
AM		 6927 if (i.op[0].imms->X_op != O_constant)
6928 as_bad (_("can't handle non absolute segment in `%s'"),
6929 i.tm.name);
6930 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6931}
a217f122 6932
29b0f896 6933static void
e3bb37b5 6934output_insn (void)
29b0f896 6935{
2bbd9c25
JJ		 6936 fragS *insn_start_frag;
6937 offsetT insn_start_off;
6938
29b0f896
AM		 6939 /* Tie dwarf2 debug info to the address at the start of the insn.
6940 We can't do this after the insn has been output as the current
6941 frag may have been closed off. eg. by frag_var. */
6942 dwarf2_emit_insn (0);
6943
2bbd9c25
JJ		 6944 insn_start_frag = frag_now;
6945 insn_start_off = frag_now_fix ();
6946
29b0f896 6947 /* Output jumps. */
40fb9820 6948 if (i.tm.opcode_modifier.jump)
29b0f896 6949 output_branch ();
40fb9820
L		 6950 else if (i.tm.opcode_modifier.jumpbyte
6951 || i.tm.opcode_modifier.jumpdword)
29b0f896 6952 output_jump ();
40fb9820 6953 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6954 output_interseg_jump ();
6955 else
6956 {
6957 /* Output normal instructions here. */
6958 char *p;
6959 unsigned char *q;
47465058 6960 unsigned int j;
331d2d0d 6961 unsigned int prefix;
4dffcebc 6962
d022bddd
IT		 6963 /* Some processors fail on LOCK prefix. This options makes
6964 assembler ignore LOCK prefix and serves as a workaround. */
6965 if (omit_lock_prefix)
6966 {
6967 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
6968 return;
6969 i.prefix[LOCK_PREFIX] = 0;
6970 }
6971
43234a1e
L		 6972 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6973 don't need the explicit prefix. */
6974 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6975 {
c0f3af97 6976 switch (i.tm.opcode_length)
bc4bd9ab 6977 {
c0f3af97
L		 6978 case 3:
6979 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6980 {
c0f3af97
L		 6981 prefix = (i.tm.base_opcode >> 24) & 0xff;
6982 goto check_prefix;
6983 }
6984 break;
6985 case 2:
6986 if ((i.tm.base_opcode & 0xff0000) != 0)
6987 {
6988 prefix = (i.tm.base_opcode >> 16) & 0xff;
6989 if (i.tm.cpu_flags.bitfield.cpupadlock)
6990 {
4dffcebc 6991check_prefix:
c0f3af97 6992 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6993 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6994 != REPE_PREFIX_OPCODE))
6995 add_prefix (prefix);
6996 }
6997 else
4dffcebc
L		 6998 add_prefix (prefix);
6999 }
c0f3af97
L		 7000 break;
7001 case 1:
7002 break;
7003 default:
7004 abort ();
bc4bd9ab 7005 }
c0f3af97 7006
6d19a37a 7007#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7008 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7009 R_X86_64_GOTTPOFF relocation so that linker can safely
7010 perform IE->LE optimization. */
7011 if (x86_elf_abi == X86_64_X32_ABI
7012 && i.operands == 2
7013 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7014 && i.prefix[REX_PREFIX] == 0)
7015 add_prefix (REX_OPCODE);
6d19a37a 7016#endif
cf61b747 7017
c0f3af97
L		 7018 /* The prefix bytes. */
7019 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7020 if (*q)
7021 FRAG_APPEND_1_CHAR (*q);
0f10071e 7022 }
ae5c1c7b 7023 else
c0f3af97
L		 7024 {
7025 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7026 if (*q)
7027 switch (j)
7028 {
7029 case REX_PREFIX:
7030 /* REX byte is encoded in VEX prefix. */
7031 break;
7032 case SEG_PREFIX:
7033 case ADDR_PREFIX:
7034 FRAG_APPEND_1_CHAR (*q);
7035 break;
7036 default:
7037 /* There should be no other prefixes for instructions
7038 with VEX prefix. */
7039 abort ();
7040 }
7041
43234a1e
L		 7042 /* For EVEX instructions i.vrex should become 0 after
7043 build_evex_prefix. For VEX instructions upper 16 registers
7044 aren't available, so VREX should be 0. */
7045 if (i.vrex)
7046 abort ();
c0f3af97
L		 7047 /* Now the VEX prefix. */
7048 p = frag_more (i.vex.length);
7049 for (j = 0; j < i.vex.length; j++)
7050 p[j] = i.vex.bytes[j];
7051 }
252b5132 7052
29b0f896 7053 /* Now the opcode; be careful about word order here! */
4dffcebc 7054 if (i.tm.opcode_length == 1)
29b0f896
AM		 7055 {
7056 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7057 }
7058 else
7059 {
4dffcebc 7060 switch (i.tm.opcode_length)
331d2d0d 7061 {
43234a1e
L		 7062 case 4:
7063 p = frag_more (4);
7064 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7065 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7066 break;
4dffcebc 7067 case 3:
331d2d0d
L		 7068 p = frag_more (3);
7069 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7070 break;
7071 case 2:
7072 p = frag_more (2);
7073 break;
7074 default:
7075 abort ();
7076 break;
331d2d0d 7077 }
0f10071e 7078
29b0f896
AM		 7079 /* Put out high byte first: can't use md_number_to_chars! */
7080 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7081 *p = i.tm.base_opcode & 0xff;
7082 }
3e73aa7c 7083
29b0f896 7084 /* Now the modrm byte and sib byte (if present). */
40fb9820 7085 if (i.tm.opcode_modifier.modrm)
29b0f896 7086 {
4a3523fa
L		 7087 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7088 | i.rm.reg << 3
7089 | i.rm.mode << 6));
29b0f896
AM		 7090 /* If i.rm.regmem == ESP (4)
7091 && i.rm.mode != (Register mode)
7092 && not 16 bit
7093 ==> need second modrm byte. */
7094 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7095 && i.rm.mode != 3
40fb9820 7096 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7097 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7098 | i.sib.index << 3
7099 | i.sib.scale << 6));
29b0f896 7100 }
3e73aa7c 7101
29b0f896 7102 if (i.disp_operands)
2bbd9c25 7103 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7104
29b0f896 7105 if (i.imm_operands)
2bbd9c25 7106 output_imm (insn_start_frag, insn_start_off);
29b0f896 7107 }
252b5132 7108
29b0f896
AM		 7109#ifdef DEBUG386
7110 if (flag_debug)
7111 {
7b81dfbb 7112 pi ("" /*line*/, &i);
29b0f896
AM		 7113 }
7114#endif /* DEBUG386 */
7115}
252b5132 7116
e205caa7
L		 7117/* Return the size of the displacement operand N. */
7118
7119static int
7120disp_size (unsigned int n)
7121{
7122 int size = 4;
43234a1e
L		 7123
7124 /* Vec_Disp8 has to be 8bit. */
7125 if (i.types[n].bitfield.vec_disp8)
7126 size = 1;
7127 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7128 size = 8;
7129 else if (i.types[n].bitfield.disp8)
7130 size = 1;
7131 else if (i.types[n].bitfield.disp16)
7132 size = 2;
e205caa7
L		 7133 return size;
7134}
7135
7136/* Return the size of the immediate operand N. */
7137
7138static int
7139imm_size (unsigned int n)
7140{
7141 int size = 4;
40fb9820
L		 7142 if (i.types[n].bitfield.imm64)
7143 size = 8;
7144 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7145 size = 1;
7146 else if (i.types[n].bitfield.imm16)
7147 size = 2;
e205caa7
L		 7148 return size;
7149}
7150
29b0f896 7151static void
64e74474 7152output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7153{
7154 char *p;
7155 unsigned int n;
252b5132 7156
29b0f896
AM		 7157 for (n = 0; n < i.operands; n++)
7158 {
43234a1e
L		 7159 if (i.types[n].bitfield.vec_disp8
7160 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7161 {
7162 if (i.op[n].disps->X_op == O_constant)
7163 {
e205caa7 7164 int size = disp_size (n);
43234a1e 7165 offsetT val = i.op[n].disps->X_add_number;
252b5132 7166
43234a1e
L		 7167 if (i.types[n].bitfield.vec_disp8)
7168 val >>= i.memshift;
7169 val = offset_in_range (val, size);
29b0f896
AM		 7170 p = frag_more (size);
7171 md_number_to_chars (p, val, size);
7172 }
7173 else
7174 {
f86103b7 7175 enum bfd_reloc_code_real reloc_type;
e205caa7 7176 int size = disp_size (n);
40fb9820 7177 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 7178 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7179
e205caa7 7180 /* We can't have 8 bit displacement here. */
9c2799c2 7181 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7182
29b0f896
AM		 7183 /* The PC relative address is computed relative
7184 to the instruction boundary, so in case immediate
7185 fields follows, we need to adjust the value. */
7186 if (pcrel && i.imm_operands)
7187 {
29b0f896 7188 unsigned int n1;
e205caa7 7189 int sz = 0;
252b5132 7190
29b0f896 7191 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7192 if (operand_type_check (i.types[n1], imm))
252b5132 7193 {
e205caa7
L		 7194 /* Only one immediate is allowed for PC
7195 relative address. */
9c2799c2 7196 gas_assert (sz == 0);
e205caa7
L		 7197 sz = imm_size (n1);
7198 i.op[n].disps->X_add_number -= sz;
252b5132 7199 }
29b0f896 7200 /* We should find the immediate. */
9c2799c2 7201 gas_assert (sz != 0);
29b0f896 7202 }
520dc8e8 7203
29b0f896 7204 p = frag_more (size);
c3320543
L		 7205 reloc_type = reloc (size, pcrel, sign,
7206 (i.bnd_prefix != NULL
7207 || add_bnd_prefix),
7208 i.reloc[n]);
d6ab8113 7209 if (GOT_symbol
2bbd9c25 7210 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7211 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7212 || reloc_type == BFD_RELOC_X86_64_32S
7213 || (reloc_type == BFD_RELOC_64
7214 && object_64bit))
d6ab8113
JB		 7215 && (i.op[n].disps->X_op == O_symbol
7216 || (i.op[n].disps->X_op == O_add
7217 && ((symbol_get_value_expression
7218 (i.op[n].disps->X_op_symbol)->X_op)
7219 == O_subtract))))
7220 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7221 {
7222 offsetT add;
7223
7224 if (insn_start_frag == frag_now)
7225 add = (p - frag_now->fr_literal) - insn_start_off;
7226 else
7227 {
7228 fragS *fr;
7229
7230 add = insn_start_frag->fr_fix - insn_start_off;
7231 for (fr = insn_start_frag->fr_next;
7232 fr && fr != frag_now; fr = fr->fr_next)
7233 add += fr->fr_fix;
7234 add += p - frag_now->fr_literal;
7235 }
7236
4fa24527 7237 if (!object_64bit)
7b81dfbb
AJ		 7238 {
7239 reloc_type = BFD_RELOC_386_GOTPC;
7240 i.op[n].imms->X_add_number += add;
7241 }
7242 else if (reloc_type == BFD_RELOC_64)
7243 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7244 else
7b81dfbb
AJ		 7245 /* Don't do the adjustment for x86-64, as there
7246 the pcrel addressing is relative to the _next_
7247 insn, and that is taken care of in other code. */
d6ab8113 7248 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7249 }
062cd5e7 7250 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 7251 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 7252 }
7253 }
7254 }
7255}
252b5132 7256
29b0f896 7257static void
64e74474 7258output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7259{
7260 char *p;
7261 unsigned int n;
252b5132 7262
29b0f896
AM		 7263 for (n = 0; n < i.operands; n++)
7264 {
43234a1e
L		 7265 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7266 if (i.rounding && (int) n == i.rounding->operand)
7267 continue;
7268
40fb9820 7269 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7270 {
7271 if (i.op[n].imms->X_op == O_constant)
7272 {
e205caa7 7273 int size = imm_size (n);
29b0f896 7274 offsetT val;
b4cac588 7275
29b0f896
AM		 7276 val = offset_in_range (i.op[n].imms->X_add_number,
7277 size);
7278 p = frag_more (size);
7279 md_number_to_chars (p, val, size);
7280 }
7281 else
7282 {
7283 /* Not absolute_section.
7284 Need a 32-bit fixup (don't support 8bit
7285 non-absolute imms). Try to support other
7286 sizes ... */
f86103b7 7287 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7288 int size = imm_size (n);
7289 int sign;
29b0f896 7290
40fb9820 7291 if (i.types[n].bitfield.imm32s
a7d61044 7292 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7293 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7294 sign = 1;
e205caa7
L		 7295 else
7296 sign = 0;
520dc8e8 7297
29b0f896 7298 p = frag_more (size);
c3320543 7299 reloc_type = reloc (size, 0, sign, 0, i.reloc[n]);
f86103b7 7300
2bbd9c25
JJ		 7301 /* This is tough to explain. We end up with this one if we
7302 * have operands that look like
7303 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7304 * obtain the absolute address of the GOT, and it is strongly
7305 * preferable from a performance point of view to avoid using
7306 * a runtime relocation for this. The actual sequence of
7307 * instructions often look something like:
7308 *
7309 * call .L66
7310 * .L66:
7311 * popl %ebx
7312 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7313 *
7314 * The call and pop essentially return the absolute address
7315 * of the label .L66 and store it in %ebx. The linker itself
7316 * will ultimately change the first operand of the addl so
7317 * that %ebx points to the GOT, but to keep things simple, the
7318 * .o file must have this operand set so that it generates not
7319 * the absolute address of .L66, but the absolute address of
7320 * itself. This allows the linker itself simply treat a GOTPC
7321 * relocation as asking for a pcrel offset to the GOT to be
7322 * added in, and the addend of the relocation is stored in the
7323 * operand field for the instruction itself.
7324 *
7325 * Our job here is to fix the operand so that it would add
7326 * the correct offset so that %ebx would point to itself. The
7327 * thing that is tricky is that .-.L66 will point to the
7328 * beginning of the instruction, so we need to further modify
7329 * the operand so that it will point to itself. There are
7330 * other cases where you have something like:
7331 *
7332 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7333 *
7334 * and here no correction would be required. Internally in
7335 * the assembler we treat operands of this form as not being
7336 * pcrel since the '.' is explicitly mentioned, and I wonder
7337 * whether it would simplify matters to do it this way. Who
7338 * knows. In earlier versions of the PIC patches, the
7339 * pcrel_adjust field was used to store the correction, but
7340 * since the expression is not pcrel, I felt it would be
7341 * confusing to do it this way. */
7342
d6ab8113 7343 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7344 || reloc_type == BFD_RELOC_X86_64_32S
7345 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7346 && GOT_symbol
7347 && GOT_symbol == i.op[n].imms->X_add_symbol
7348 && (i.op[n].imms->X_op == O_symbol
7349 || (i.op[n].imms->X_op == O_add
7350 && ((symbol_get_value_expression
7351 (i.op[n].imms->X_op_symbol)->X_op)
7352 == O_subtract))))
7353 {
2bbd9c25
JJ		 7354 offsetT add;
7355
7356 if (insn_start_frag == frag_now)
7357 add = (p - frag_now->fr_literal) - insn_start_off;
7358 else
7359 {
7360 fragS *fr;
7361
7362 add = insn_start_frag->fr_fix - insn_start_off;
7363 for (fr = insn_start_frag->fr_next;
7364 fr && fr != frag_now; fr = fr->fr_next)
7365 add += fr->fr_fix;
7366 add += p - frag_now->fr_literal;
7367 }
7368
4fa24527 7369 if (!object_64bit)
d6ab8113 7370 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7371 else if (size == 4)
d6ab8113 7372 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7373 else if (size == 8)
7374 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7375 i.op[n].imms->X_add_number += add;
29b0f896 7376 }
29b0f896
AM		 7377 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7378 i.op[n].imms, 0, reloc_type);
7379 }
7380 }
7381 }
252b5132
RH		 7382}
7383\f
d182319b
JB		 7384/* x86_cons_fix_new is called via the expression parsing code when a
7385 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7386static int cons_sign = -1;
7387
7388void
e3bb37b5 7389x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7390 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7391{
62ebcb5c 7392 r = reloc (len, 0, cons_sign, 0, r);
d182319b
JB		 7393
7394#ifdef TE_PE
7395 if (exp->X_op == O_secrel)
7396 {
7397 exp->X_op = O_symbol;
7398 r = BFD_RELOC_32_SECREL;
7399 }
7400#endif
7401
7402 fix_new_exp (frag, off, len, exp, 0, r);
7403}
7404
357d1bd8
L		 7405/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7406 purpose of the `.dc.a' internal pseudo-op. */
7407
7408int
7409x86_address_bytes (void)
7410{
7411 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7412 return 4;
7413 return stdoutput->arch_info->bits_per_address / 8;
7414}
7415
d382c579
TG		 7416#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7417 || defined (LEX_AT)
c06ec724 7418# define lex_got(reloc, adjust, types, bnd_prefix) NULL
718ddfc0 7419#else
f3c180ae
AM		 7420/* Parse operands of the form
7421 <symbol>@GOTOFF+<nnn>
7422 and similar .plt or .got references.
7423
7424 If we find one, set up the correct relocation in RELOC and copy the
7425 input string, minus the `@GOTOFF' into a malloc'd buffer for
7426 parsing by the calling routine. Return this buffer, and if ADJUST
7427 is non-null set it to the length of the string we removed from the
7428 input line. Otherwise return NULL. */
7429static char *
91d6fa6a 7430lex_got (enum bfd_reloc_code_real *rel,
64e74474 7431 int *adjust,
c3320543
L		 7432 i386_operand_type *types,
7433 int bnd_prefix)
f3c180ae 7434{
7b81dfbb
AJ		 7435 /* Some of the relocations depend on the size of what field is to
7436 be relocated. But in our callers i386_immediate and i386_displacement
7437 we don't yet know the operand size (this will be set by insn
7438 matching). Hence we record the word32 relocation here,
7439 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7440 static const struct {
7441 const char *str;
cff8d58a 7442 int len;
4fa24527 7443 const enum bfd_reloc_code_real rel[2];
40fb9820 7444 const i386_operand_type types64;
f3c180ae 7445 } gotrel[] = {
8ce3d284 7446#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7447 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7448 BFD_RELOC_SIZE32 },
7449 OPERAND_TYPE_IMM32_64 },
8ce3d284 7450#endif
cff8d58a
L		 7451 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7452 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7453 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7454 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7455 BFD_RELOC_X86_64_PLT32 },
40fb9820 7456 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7457 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7458 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7459 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7460 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7461 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7462 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7463 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7464 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7465 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7466 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7467 BFD_RELOC_X86_64_TLSGD },
40fb9820 7468 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7469 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7470 _dummy_first_bfd_reloc_code_real },
40fb9820 7471 OPERAND_TYPE_NONE },
cff8d58a
L		 7472 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7473 BFD_RELOC_X86_64_TLSLD },
40fb9820 7474 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7475 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7476 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7477 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7478 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7479 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7480 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7481 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7482 _dummy_first_bfd_reloc_code_real },
40fb9820 7483 OPERAND_TYPE_NONE },
cff8d58a
L		 7484 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7485 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7486 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7487 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7488 _dummy_first_bfd_reloc_code_real },
40fb9820 7489 OPERAND_TYPE_NONE },
cff8d58a
L		 7490 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7491 _dummy_first_bfd_reloc_code_real },
40fb9820 7492 OPERAND_TYPE_NONE },
cff8d58a
L		 7493 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7494 BFD_RELOC_X86_64_GOT32 },
40fb9820 7495 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7496 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7497 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7498 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7499 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7500 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7501 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7502 };
7503 char *cp;
7504 unsigned int j;
7505
d382c579 7506#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7507 if (!IS_ELF)
7508 return NULL;
d382c579 7509#endif
718ddfc0 7510
f3c180ae 7511 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7512 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7513 return NULL;
7514
47465058 7515 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7516 {
cff8d58a 7517 int len = gotrel[j].len;
28f81592 7518 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7519 {
4fa24527 7520 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7521 {
28f81592
AM		 7522 int first, second;
7523 char *tmpbuf, *past_reloc;
f3c180ae 7524
91d6fa6a 7525 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7526
3956db08
JB		 7527 if (types)
7528 {
7529 if (flag_code != CODE_64BIT)
40fb9820
L		 7530 {
7531 types->bitfield.imm32 = 1;
7532 types->bitfield.disp32 = 1;
7533 }
3956db08
JB		 7534 else
7535 *types = gotrel[j].types64;
7536 }
7537
8fd4256d 7538 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7539 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7540
28f81592 7541 /* The length of the first part of our input line. */
f3c180ae 7542 first = cp - input_line_pointer;
28f81592
AM		 7543
7544 /* The second part goes from after the reloc token until
67c11a9b 7545 (and including) an end_of_line char or comma. */
28f81592 7546 past_reloc = cp + 1 + len;
67c11a9b
AM		 7547 cp = past_reloc;
7548 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7549 ++cp;
7550 second = cp + 1 - past_reloc;
28f81592
AM		 7551
7552 /* Allocate and copy string. The trailing NUL shouldn't
7553 be necessary, but be safe. */
1e9cc1c2 7554 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7555 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7556 if (second != 0 && *past_reloc != ' ')
7557 /* Replace the relocation token with ' ', so that
7558 errors like foo@GOTOFF1 will be detected. */
7559 tmpbuf[first++] = ' ';
af89796a
L		 7560 else
7561 /* Increment length by 1 if the relocation token is
7562 removed. */
7563 len++;
7564 if (adjust)
7565 *adjust = len;
0787a12d
AM		 7566 memcpy (tmpbuf + first, past_reloc, second);
7567 tmpbuf[first + second] = '\0';
c3320543
L		 7568 if (bnd_prefix && *rel == BFD_RELOC_X86_64_PLT32)
7569 *rel = BFD_RELOC_X86_64_PLT32_BND;
f3c180ae
AM		 7570 return tmpbuf;
7571 }
7572
4fa24527
JB		 7573 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7574 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7575 return NULL;
7576 }
7577 }
7578
7579 /* Might be a symbol version string. Don't as_bad here. */
7580 return NULL;
7581}
4e4f7c87 7582#endif
f3c180ae 7583
a988325c
NC		 7584#ifdef TE_PE
7585#ifdef lex_got
7586#undef lex_got
7587#endif
7588/* Parse operands of the form
7589 <symbol>@SECREL32+<nnn>
7590
7591 If we find one, set up the correct relocation in RELOC and copy the
7592 input string, minus the `@SECREL32' into a malloc'd buffer for
7593 parsing by the calling routine. Return this buffer, and if ADJUST
7594 is non-null set it to the length of the string we removed from the
34bca508
L		 7595 input line. Otherwise return NULL.
7596
a988325c
NC		 7597 This function is copied from the ELF version above adjusted for PE targets. */
7598
7599static char *
7600lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7601 int *adjust ATTRIBUTE_UNUSED,
c06ec724
L		 7602 i386_operand_type *types,
7603 int bnd_prefix ATTRIBUTE_UNUSED)
a988325c
NC		 7604{
7605 static const struct
7606 {
7607 const char *str;
7608 int len;
7609 const enum bfd_reloc_code_real rel[2];
7610 const i386_operand_type types64;
7611 }
7612 gotrel[] =
7613 {
7614 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7615 BFD_RELOC_32_SECREL },
7616 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7617 };
7618
7619 char *cp;
7620 unsigned j;
7621
7622 for (cp = input_line_pointer; *cp != '@'; cp++)
7623 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7624 return NULL;
7625
7626 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7627 {
7628 int len = gotrel[j].len;
7629
7630 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7631 {
7632 if (gotrel[j].rel[object_64bit] != 0)
7633 {
7634 int first, second;
7635 char *tmpbuf, *past_reloc;
7636
7637 *rel = gotrel[j].rel[object_64bit];
7638 if (adjust)
7639 *adjust = len;
7640
7641 if (types)
7642 {
7643 if (flag_code != CODE_64BIT)
7644 {
7645 types->bitfield.imm32 = 1;
7646 types->bitfield.disp32 = 1;
7647 }
7648 else
7649 *types = gotrel[j].types64;
7650 }
7651
7652 /* The length of the first part of our input line. */
7653 first = cp - input_line_pointer;
7654
7655 /* The second part goes from after the reloc token until
7656 (and including) an end_of_line char or comma. */
7657 past_reloc = cp + 1 + len;
7658 cp = past_reloc;
7659 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7660 ++cp;
7661 second = cp + 1 - past_reloc;
7662
7663 /* Allocate and copy string. The trailing NUL shouldn't
7664 be necessary, but be safe. */
7665 tmpbuf = (char *) xmalloc (first + second + 2);
7666 memcpy (tmpbuf, input_line_pointer, first);
7667 if (second != 0 && *past_reloc != ' ')
7668 /* Replace the relocation token with ' ', so that
7669 errors like foo@SECLREL321 will be detected. */
7670 tmpbuf[first++] = ' ';
7671 memcpy (tmpbuf + first, past_reloc, second);
7672 tmpbuf[first + second] = '\0';
7673 return tmpbuf;
7674 }
7675
7676 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7677 gotrel[j].str, 1 << (5 + object_64bit));
7678 return NULL;
7679 }
7680 }
7681
7682 /* Might be a symbol version string. Don't as_bad here. */
7683 return NULL;
7684}
7685
7686#endif /* TE_PE */
7687
62ebcb5c 7688bfd_reloc_code_real_type
e3bb37b5 7689x86_cons (expressionS *exp, int size)
f3c180ae 7690{
62ebcb5c
AM		 7691 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7692
ee86248c
JB		 7693 intel_syntax = -intel_syntax;
7694
3c7b9c2c 7695 exp->X_md = 0;
4fa24527 7696 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7697 {
7698 /* Handle @GOTOFF and the like in an expression. */
7699 char *save;
7700 char *gotfree_input_line;
4a57f2cf 7701 int adjust = 0;
f3c180ae
AM		 7702
7703 save = input_line_pointer;
c3320543 7704 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL, 0);
f3c180ae
AM		 7705 if (gotfree_input_line)
7706 input_line_pointer = gotfree_input_line;
7707
7708 expression (exp);
7709
7710 if (gotfree_input_line)
7711 {
7712 /* expression () has merrily parsed up to the end of line,
7713 or a comma - in the wrong buffer. Transfer how far
7714 input_line_pointer has moved to the right buffer. */
7715 input_line_pointer = (save
7716 + (input_line_pointer - gotfree_input_line)
7717 + adjust);
7718 free (gotfree_input_line);
3992d3b7
AM		 7719 if (exp->X_op == O_constant
7720 || exp->X_op == O_absent
7721 || exp->X_op == O_illegal
0398aac5 7722 || exp->X_op == O_register
3992d3b7
AM		 7723 || exp->X_op == O_big)
7724 {
7725 char c = *input_line_pointer;
7726 *input_line_pointer = 0;
7727 as_bad (_("missing or invalid expression `%s'"), save);
7728 *input_line_pointer = c;
7729 }
f3c180ae
AM		 7730 }
7731 }
7732 else
7733 expression (exp);
ee86248c
JB		 7734
7735 intel_syntax = -intel_syntax;
7736
7737 if (intel_syntax)
7738 i386_intel_simplify (exp);
62ebcb5c
AM		 7739
7740 return got_reloc;
f3c180ae 7741}
f3c180ae 7742
9f32dd5b
L		 7743static void
7744signed_cons (int size)
6482c264 7745{
d182319b
JB		 7746 if (flag_code == CODE_64BIT)
7747 cons_sign = 1;
7748 cons (size);
7749 cons_sign = -1;
6482c264
NC		 7750}
7751
d182319b 7752#ifdef TE_PE
6482c264 7753static void
7016a5d5 7754pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7755{
7756 expressionS exp;
7757
7758 do
7759 {
7760 expression (&exp);
7761 if (exp.X_op == O_symbol)
7762 exp.X_op = O_secrel;
7763
7764 emit_expr (&exp, 4);
7765 }
7766 while (*input_line_pointer++ == ',');
7767
7768 input_line_pointer--;
7769 demand_empty_rest_of_line ();
7770}
6482c264
NC		 7771#endif
7772
43234a1e
L		 7773/* Handle Vector operations. */
7774
7775static char *
7776check_VecOperations (char *op_string, char *op_end)
7777{
7778 const reg_entry *mask;
7779 const char *saved;
7780 char *end_op;
7781
7782 while (*op_string
7783 && (op_end == NULL || op_string < op_end))
7784 {
7785 saved = op_string;
7786 if (*op_string == '{')
7787 {
7788 op_string++;
7789
7790 /* Check broadcasts. */
7791 if (strncmp (op_string, "1to", 3) == 0)
7792 {
7793 int bcst_type;
7794
7795 if (i.broadcast)
7796 goto duplicated_vec_op;
7797
7798 op_string += 3;
7799 if (*op_string == '8')
7800 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7801 else if (*op_string == '4')
7802 bcst_type = BROADCAST_1TO4;
7803 else if (*op_string == '2')
7804 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7805 else if (*op_string == '1'
7806 && *(op_string+1) == '6')
7807 {
7808 bcst_type = BROADCAST_1TO16;
7809 op_string++;
7810 }
7811 else
7812 {
7813 as_bad (_("Unsupported broadcast: `%s'"), saved);
7814 return NULL;
7815 }
7816 op_string++;
7817
7818 broadcast_op.type = bcst_type;
7819 broadcast_op.operand = this_operand;
7820 i.broadcast = &broadcast_op;
7821 }
7822 /* Check masking operation. */
7823 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7824 {
7825 /* k0 can't be used for write mask. */
7826 if (mask->reg_num == 0)
7827 {
7828 as_bad (_("`%s' can't be used for write mask"),
7829 op_string);
7830 return NULL;
7831 }
7832
7833 if (!i.mask)
7834 {
7835 mask_op.mask = mask;
7836 mask_op.zeroing = 0;
7837 mask_op.operand = this_operand;
7838 i.mask = &mask_op;
7839 }
7840 else
7841 {
7842 if (i.mask->mask)
7843 goto duplicated_vec_op;
7844
7845 i.mask->mask = mask;
7846
7847 /* Only "{z}" is allowed here. No need to check
7848 zeroing mask explicitly. */
7849 if (i.mask->operand != this_operand)
7850 {
7851 as_bad (_("invalid write mask `%s'"), saved);
7852 return NULL;
7853 }
7854 }
7855
7856 op_string = end_op;
7857 }
7858 /* Check zeroing-flag for masking operation. */
7859 else if (*op_string == 'z')
7860 {
7861 if (!i.mask)
7862 {
7863 mask_op.mask = NULL;
7864 mask_op.zeroing = 1;
7865 mask_op.operand = this_operand;
7866 i.mask = &mask_op;
7867 }
7868 else
7869 {
7870 if (i.mask->zeroing)
7871 {
7872 duplicated_vec_op:
7873 as_bad (_("duplicated `%s'"), saved);
7874 return NULL;
7875 }
7876
7877 i.mask->zeroing = 1;
7878
7879 /* Only "{%k}" is allowed here. No need to check mask
7880 register explicitly. */
7881 if (i.mask->operand != this_operand)
7882 {
7883 as_bad (_("invalid zeroing-masking `%s'"),
7884 saved);
7885 return NULL;
7886 }
7887 }
7888
7889 op_string++;
7890 }
7891 else
7892 goto unknown_vec_op;
7893
7894 if (*op_string != '}')
7895 {
7896 as_bad (_("missing `}' in `%s'"), saved);
7897 return NULL;
7898 }
7899 op_string++;
7900 continue;
7901 }
7902 unknown_vec_op:
7903 /* We don't know this one. */
7904 as_bad (_("unknown vector operation: `%s'"), saved);
7905 return NULL;
7906 }
7907
7908 return op_string;
7909}
7910
252b5132 7911static int
70e41ade 7912i386_immediate (char *imm_start)
252b5132
RH		 7913{
7914 char *save_input_line_pointer;
f3c180ae 7915 char *gotfree_input_line;
252b5132 7916 segT exp_seg = 0;
47926f60 7917 expressionS *exp;
40fb9820
L		 7918 i386_operand_type types;
7919
0dfbf9d7 7920 operand_type_set (&types, ~0);
252b5132
RH		 7921
7922 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7923 {
31b2323c
L		 7924 as_bad (_("at most %d immediate operands are allowed"),
7925 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7926 return 0;
7927 }
7928
7929 exp = &im_expressions[i.imm_operands++];
520dc8e8 7930 i.op[this_operand].imms = exp;
252b5132
RH		 7931
7932 if (is_space_char (*imm_start))
7933 ++imm_start;
7934
7935 save_input_line_pointer = input_line_pointer;
7936 input_line_pointer = imm_start;
7937
c3320543
L		 7938 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
7939 (i.bnd_prefix != NULL
7940 || add_bnd_prefix));
f3c180ae
AM		 7941 if (gotfree_input_line)
7942 input_line_pointer = gotfree_input_line;
252b5132
RH		 7943
7944 exp_seg = expression (exp);
7945
83183c0c 7946 SKIP_WHITESPACE ();
43234a1e
L		 7947
7948 /* Handle vector operations. */
7949 if (*input_line_pointer == '{')
7950 {
7951 input_line_pointer = check_VecOperations (input_line_pointer,
7952 NULL);
7953 if (input_line_pointer == NULL)
7954 return 0;
7955 }
7956
252b5132 7957 if (*input_line_pointer)
f3c180ae 7958 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7959
7960 input_line_pointer = save_input_line_pointer;
f3c180ae 7961 if (gotfree_input_line)
ee86248c
JB		 7962 {
7963 free (gotfree_input_line);
7964
7965 if (exp->X_op == O_constant || exp->X_op == O_register)
7966 exp->X_op = O_illegal;
7967 }
7968
7969 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7970}
252b5132 7971
ee86248c
JB		 7972static int
7973i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7974 i386_operand_type types, const char *imm_start)
7975{
7976 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7977 {
313c53d1
L		 7978 if (imm_start)
7979 as_bad (_("missing or invalid immediate expression `%s'"),
7980 imm_start);
3992d3b7 7981 return 0;
252b5132 7982 }
3e73aa7c 7983 else if (exp->X_op == O_constant)
252b5132 7984 {
47926f60 7985 /* Size it properly later. */
40fb9820 7986 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7987 /* If not 64bit, sign extend val. */
7988 if (flag_code != CODE_64BIT
4eed87de
AM		 7989 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7990 exp->X_add_number
7991 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7992 }
4c63da97 7993#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7994 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7995 && exp_seg != absolute_section
47926f60 7996 && exp_seg != text_section
24eab124
AM		 7997 && exp_seg != data_section
7998 && exp_seg != bss_section
7999 && exp_seg != undefined_section
f86103b7 8000 && !bfd_is_com_section (exp_seg))
252b5132 8001 {
d0b47220 8002 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8003 return 0;
8004 }
8005#endif
a841bdf5 8006 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8007 {
313c53d1
L		 8008 if (imm_start)
8009 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8010 return 0;
8011 }
252b5132
RH		 8012 else
8013 {
8014 /* This is an address. The size of the address will be
24eab124 8015 determined later, depending on destination register,
3e73aa7c 8016 suffix, or the default for the section. */
40fb9820
L		 8017 i.types[this_operand].bitfield.imm8 = 1;
8018 i.types[this_operand].bitfield.imm16 = 1;
8019 i.types[this_operand].bitfield.imm32 = 1;
8020 i.types[this_operand].bitfield.imm32s = 1;
8021 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8022 i.types[this_operand] = operand_type_and (i.types[this_operand],
8023 types);
252b5132
RH		 8024 }
8025
8026 return 1;
8027}
8028
551c1ca1 8029static char *
e3bb37b5 8030i386_scale (char *scale)
252b5132 8031{
551c1ca1
AM		 8032 offsetT val;
8033 char *save = input_line_pointer;
252b5132 8034
551c1ca1
AM		 8035 input_line_pointer = scale;
8036 val = get_absolute_expression ();
8037
8038 switch (val)
252b5132 8039 {
551c1ca1 8040 case 1:
252b5132
RH		 8041 i.log2_scale_factor = 0;
8042 break;
551c1ca1 8043 case 2:
252b5132
RH		 8044 i.log2_scale_factor = 1;
8045 break;
551c1ca1 8046 case 4:
252b5132
RH		 8047 i.log2_scale_factor = 2;
8048 break;
551c1ca1 8049 case 8:
252b5132
RH		 8050 i.log2_scale_factor = 3;
8051 break;
8052 default:
a724f0f4
JB		 8053 {
8054 char sep = *input_line_pointer;
8055
8056 *input_line_pointer = '\0';
8057 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8058 scale);
8059 *input_line_pointer = sep;
8060 input_line_pointer = save;
8061 return NULL;
8062 }
252b5132 8063 }
29b0f896 8064 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8065 {
8066 as_warn (_("scale factor of %d without an index register"),
24eab124 8067 1 << i.log2_scale_factor);
252b5132 8068 i.log2_scale_factor = 0;
252b5132 8069 }
551c1ca1
AM		 8070 scale = input_line_pointer;
8071 input_line_pointer = save;
8072 return scale;
252b5132
RH		 8073}
8074
252b5132 8075static int
e3bb37b5 8076i386_displacement (char *disp_start, char *disp_end)
252b5132 8077{
29b0f896 8078 expressionS *exp;
252b5132
RH		 8079 segT exp_seg = 0;
8080 char *save_input_line_pointer;
f3c180ae 8081 char *gotfree_input_line;
40fb9820
L		 8082 int override;
8083 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8084 int ret;
252b5132 8085
31b2323c
L		 8086 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8087 {
8088 as_bad (_("at most %d displacement operands are allowed"),
8089 MAX_MEMORY_OPERANDS);
8090 return 0;
8091 }
8092
0dfbf9d7 8093 operand_type_set (&bigdisp, 0);
40fb9820
L		 8094 if ((i.types[this_operand].bitfield.jumpabsolute)
8095 || (!current_templates->start->opcode_modifier.jump
8096 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8097 {
40fb9820 8098 bigdisp.bitfield.disp32 = 1;
e05278af 8099 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8100 if (flag_code == CODE_64BIT)
8101 {
8102 if (!override)
8103 {
8104 bigdisp.bitfield.disp32s = 1;
8105 bigdisp.bitfield.disp64 = 1;
8106 }
8107 }
8108 else if ((flag_code == CODE_16BIT) ^ override)
8109 {
8110 bigdisp.bitfield.disp32 = 0;
8111 bigdisp.bitfield.disp16 = 1;
8112 }
e05278af
JB		 8113 }
8114 else
8115 {
8116 /* For PC-relative branches, the width of the displacement
8117 is dependent upon data size, not address size. */
e05278af 8118 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8119 if (flag_code == CODE_64BIT)
8120 {
8121 if (override || i.suffix == WORD_MNEM_SUFFIX)
8122 bigdisp.bitfield.disp16 = 1;
8123 else
8124 {
8125 bigdisp.bitfield.disp32 = 1;
8126 bigdisp.bitfield.disp32s = 1;
8127 }
8128 }
8129 else
e05278af
JB		 8130 {
8131 if (!override)
8132 override = (i.suffix == (flag_code != CODE_16BIT
8133 ? WORD_MNEM_SUFFIX
8134 : LONG_MNEM_SUFFIX));
40fb9820
L		 8135 bigdisp.bitfield.disp32 = 1;
8136 if ((flag_code == CODE_16BIT) ^ override)
8137 {
8138 bigdisp.bitfield.disp32 = 0;
8139 bigdisp.bitfield.disp16 = 1;
8140 }
e05278af 8141 }
e05278af 8142 }
c6fb90c8
L		 8143 i.types[this_operand] = operand_type_or (i.types[this_operand],
8144 bigdisp);
252b5132
RH		 8145
8146 exp = &disp_expressions[i.disp_operands];
520dc8e8 8147 i.op[this_operand].disps = exp;
252b5132
RH		 8148 i.disp_operands++;
8149 save_input_line_pointer = input_line_pointer;
8150 input_line_pointer = disp_start;
8151 END_STRING_AND_SAVE (disp_end);
8152
8153#ifndef GCC_ASM_O_HACK
8154#define GCC_ASM_O_HACK 0
8155#endif
8156#if GCC_ASM_O_HACK
8157 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8158 if (i.types[this_operand].bitfield.baseIndex
24eab124 8159 && displacement_string_end[-1] == '+')
252b5132
RH		 8160 {
8161 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8162 constraint within gcc asm statements.
8163 For instance:
8164
8165 #define _set_tssldt_desc(n,addr,limit,type) \
8166 __asm__ __volatile__ ( \
8167 "movw %w2,%0\n\t" \
8168 "movw %w1,2+%0\n\t" \
8169 "rorl $16,%1\n\t" \
8170 "movb %b1,4+%0\n\t" \
8171 "movb %4,5+%0\n\t" \
8172 "movb $0,6+%0\n\t" \
8173 "movb %h1,7+%0\n\t" \
8174 "rorl $16,%1" \
8175 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8176
8177 This works great except that the output assembler ends
8178 up looking a bit weird if it turns out that there is
8179 no offset. You end up producing code that looks like:
8180
8181 #APP
8182 movw $235,(%eax)
8183 movw %dx,2+(%eax)
8184 rorl $16,%edx
8185 movb %dl,4+(%eax)
8186 movb $137,5+(%eax)
8187 movb $0,6+(%eax)
8188 movb %dh,7+(%eax)
8189 rorl $16,%edx
8190 #NO_APP
8191
47926f60 8192 So here we provide the missing zero. */
24eab124
AM		 8193
8194 *displacement_string_end = '0';
252b5132
RH		 8195 }
8196#endif
c3320543
L		 8197 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
8198 (i.bnd_prefix != NULL
8199 || add_bnd_prefix));
f3c180ae
AM		 8200 if (gotfree_input_line)
8201 input_line_pointer = gotfree_input_line;
252b5132 8202
24eab124 8203 exp_seg = expression (exp);
252b5132 8204
636c26b0
AM		 8205 SKIP_WHITESPACE ();
8206 if (*input_line_pointer)
8207 as_bad (_("junk `%s' after expression"), input_line_pointer);
8208#if GCC_ASM_O_HACK
8209 RESTORE_END_STRING (disp_end + 1);
8210#endif
636c26b0 8211 input_line_pointer = save_input_line_pointer;
636c26b0 8212 if (gotfree_input_line)
ee86248c
JB		 8213 {
8214 free (gotfree_input_line);
8215
8216 if (exp->X_op == O_constant || exp->X_op == O_register)
8217 exp->X_op = O_illegal;
8218 }
8219
8220 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8221
8222 RESTORE_END_STRING (disp_end);
8223
8224 return ret;
8225}
8226
8227static int
8228i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8229 i386_operand_type types, const char *disp_start)
8230{
8231 i386_operand_type bigdisp;
8232 int ret = 1;
636c26b0 8233
24eab124
AM		 8234 /* We do this to make sure that the section symbol is in
8235 the symbol table. We will ultimately change the relocation
47926f60 8236 to be relative to the beginning of the section. */
1ae12ab7 8237 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8238 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8239 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8240 {
636c26b0 8241 if (exp->X_op != O_symbol)
3992d3b7 8242 goto inv_disp;
636c26b0 8243
e5cb08ac 8244 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8245 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8246 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8247 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8248 exp->X_op = O_subtract;
8249 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8250 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8251 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8252 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8253 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8254 else
29b0f896 8255 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8256 }
252b5132 8257
3992d3b7
AM		 8258 else if (exp->X_op == O_absent
8259 || exp->X_op == O_illegal
ee86248c 8260 || exp->X_op == O_big)
2daf4fd8 8261 {
3992d3b7
AM		 8262 inv_disp:
8263 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8264 disp_start);
3992d3b7 8265 ret = 0;
2daf4fd8
AM		 8266 }
8267
0e1147d9
L		 8268 else if (flag_code == CODE_64BIT
8269 && !i.prefix[ADDR_PREFIX]
8270 && exp->X_op == O_constant)
8271 {
8272 /* Since displacement is signed extended to 64bit, don't allow
8273 disp32 and turn off disp32s if they are out of range. */
8274 i.types[this_operand].bitfield.disp32 = 0;
8275 if (!fits_in_signed_long (exp->X_add_number))
8276 {
8277 i.types[this_operand].bitfield.disp32s = 0;
8278 if (i.types[this_operand].bitfield.baseindex)
8279 {
8280 as_bad (_("0x%lx out range of signed 32bit displacement"),
8281 (long) exp->X_add_number);
8282 ret = 0;
8283 }
8284 }
8285 }
8286
4c63da97 8287#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8288 else if (exp->X_op != O_constant
8289 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8290 && exp_seg != absolute_section
8291 && exp_seg != text_section
8292 && exp_seg != data_section
8293 && exp_seg != bss_section
8294 && exp_seg != undefined_section
8295 && !bfd_is_com_section (exp_seg))
24eab124 8296 {
d0b47220 8297 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8298 ret = 0;
24eab124 8299 }
252b5132 8300#endif
3956db08 8301
40fb9820
L		 8302 /* Check if this is a displacement only operand. */
8303 bigdisp = i.types[this_operand];
8304 bigdisp.bitfield.disp8 = 0;
8305 bigdisp.bitfield.disp16 = 0;
8306 bigdisp.bitfield.disp32 = 0;
8307 bigdisp.bitfield.disp32s = 0;
8308 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8309 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8310 i.types[this_operand] = operand_type_and (i.types[this_operand],
8311 types);
3956db08 8312
3992d3b7 8313 return ret;
252b5132
RH		 8314}
8315
eecb386c 8316/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8317 Return 1 on success, 0 on a failure. */
8318
252b5132 8319static int
e3bb37b5 8320i386_index_check (const char *operand_string)
252b5132 8321{
fc0763e6 8322 const char *kind = "base/index";
be05d201
L		 8323 enum flag_code addr_mode;
8324
8325 if (i.prefix[ADDR_PREFIX])
8326 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8327 else
8328 {
8329 addr_mode = flag_code;
8330
24eab124 8331#if INFER_ADDR_PREFIX
be05d201
L		 8332 if (i.mem_operands == 0)
8333 {
8334 /* Infer address prefix from the first memory operand. */
8335 const reg_entry *addr_reg = i.base_reg;
8336
8337 if (addr_reg == NULL)
8338 addr_reg = i.index_reg;
eecb386c 8339
be05d201
L		 8340 if (addr_reg)
8341 {
8342 if (addr_reg->reg_num == RegEip
8343 || addr_reg->reg_num == RegEiz
8344 || addr_reg->reg_type.bitfield.reg32)
8345 addr_mode = CODE_32BIT;
8346 else if (flag_code != CODE_64BIT
8347 && addr_reg->reg_type.bitfield.reg16)
8348 addr_mode = CODE_16BIT;
8349
8350 if (addr_mode != flag_code)
8351 {
8352 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8353 i.prefixes += 1;
8354 /* Change the size of any displacement too. At most one
8355 of Disp16 or Disp32 is set.
8356 FIXME. There doesn't seem to be any real need for
8357 separate Disp16 and Disp32 flags. The same goes for
8358 Imm16 and Imm32. Removing them would probably clean
8359 up the code quite a lot. */
8360 if (flag_code != CODE_64BIT
8361 && (i.types[this_operand].bitfield.disp16
8362 || i.types[this_operand].bitfield.disp32))
8363 i.types[this_operand]
8364 = operand_type_xor (i.types[this_operand], disp16_32);
8365 }
8366 }
8367 }
24eab124 8368#endif
be05d201
L		 8369 }
8370
fc0763e6
JB		 8371 if (current_templates->start->opcode_modifier.isstring
8372 && !current_templates->start->opcode_modifier.immext
8373 && (current_templates->end[-1].opcode_modifier.isstring
8374 || i.mem_operands))
8375 {
8376 /* Memory operands of string insns are special in that they only allow
8377 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8378 const reg_entry *expected_reg;
8379 static const char *di_si[][2] =
8380 {
8381 { "esi", "edi" },
8382 { "si", "di" },
8383 { "rsi", "rdi" }
8384 };
8385 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8386
8387 kind = "string address";
8388
8389 if (current_templates->start->opcode_modifier.w)
8390 {
8391 i386_operand_type type = current_templates->end[-1].operand_types[0];
8392
8393 if (!type.bitfield.baseindex
8394 || ((!i.mem_operands != !intel_syntax)
8395 && current_templates->end[-1].operand_types[1]
8396 .bitfield.baseindex))
8397 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8398 expected_reg = hash_find (reg_hash,
8399 di_si[addr_mode][type.bitfield.esseg]);
8400
fc0763e6
JB		 8401 }
8402 else
be05d201 8403 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8404
be05d201
L		 8405 if (i.base_reg != expected_reg
8406 || i.index_reg
fc0763e6 8407 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8408 {
be05d201
L		 8409 /* The second memory operand must have the same size as
8410 the first one. */
8411 if (i.mem_operands
8412 && i.base_reg
8413 && !((addr_mode == CODE_64BIT
8414 && i.base_reg->reg_type.bitfield.reg64)
8415 || (addr_mode == CODE_32BIT
8416 ? i.base_reg->reg_type.bitfield.reg32
8417 : i.base_reg->reg_type.bitfield.reg16)))
8418 goto bad_address;
8419
fc0763e6
JB		 8420 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8421 operand_string,
8422 intel_syntax ? '[' : '(',
8423 register_prefix,
be05d201 8424 expected_reg->reg_name,
fc0763e6 8425 intel_syntax ? ']' : ')');
be05d201 8426 return 1;
fc0763e6 8427 }
be05d201
L		 8428 else
8429 return 1;
8430
8431bad_address:
8432 as_bad (_("`%s' is not a valid %s expression"),
8433 operand_string, kind);
8434 return 0;
3e73aa7c
JH		 8435 }
8436 else
8437 {
be05d201
L		 8438 if (addr_mode != CODE_16BIT)
8439 {
8440 /* 32-bit/64-bit checks. */
8441 if ((i.base_reg
8442 && (addr_mode == CODE_64BIT
8443 ? !i.base_reg->reg_type.bitfield.reg64
8444 : !i.base_reg->reg_type.bitfield.reg32)
8445 && (i.index_reg
8446 || (i.base_reg->reg_num
8447 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8448 || (i.index_reg
8449 && !i.index_reg->reg_type.bitfield.regxmm
8450 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8451 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8452 && ((addr_mode == CODE_64BIT
8453 ? !(i.index_reg->reg_type.bitfield.reg64
8454 || i.index_reg->reg_num == RegRiz)
8455 : !(i.index_reg->reg_type.bitfield.reg32
8456 || i.index_reg->reg_num == RegEiz))
8457 || !i.index_reg->reg_type.bitfield.baseindex)))
8458 goto bad_address;
8459 }
8460 else
3e73aa7c 8461 {
be05d201 8462 /* 16-bit checks. */
3e73aa7c 8463 if ((i.base_reg
40fb9820
L		 8464 && (!i.base_reg->reg_type.bitfield.reg16
8465 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8466 || (i.index_reg
40fb9820
L		 8467 && (!i.index_reg->reg_type.bitfield.reg16
8468 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8469 || !(i.base_reg
8470 && i.base_reg->reg_num < 6
8471 && i.index_reg->reg_num >= 6
8472 && i.log2_scale_factor == 0))))
be05d201 8473 goto bad_address;
3e73aa7c
JH		 8474 }
8475 }
be05d201 8476 return 1;
24eab124 8477}
252b5132 8478
43234a1e
L		 8479/* Handle vector immediates. */
8480
8481static int
8482RC_SAE_immediate (const char *imm_start)
8483{
8484 unsigned int match_found, j;
8485 const char *pstr = imm_start;
8486 expressionS *exp;
8487
8488 if (*pstr != '{')
8489 return 0;
8490
8491 pstr++;
8492 match_found = 0;
8493 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8494 {
8495 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8496 {
8497 if (!i.rounding)
8498 {
8499 rc_op.type = RC_NamesTable[j].type;
8500 rc_op.operand = this_operand;
8501 i.rounding = &rc_op;
8502 }
8503 else
8504 {
8505 as_bad (_("duplicated `%s'"), imm_start);
8506 return 0;
8507 }
8508 pstr += RC_NamesTable[j].len;
8509 match_found = 1;
8510 break;
8511 }
8512 }
8513 if (!match_found)
8514 return 0;
8515
8516 if (*pstr++ != '}')
8517 {
8518 as_bad (_("Missing '}': '%s'"), imm_start);
8519 return 0;
8520 }
8521 /* RC/SAE immediate string should contain nothing more. */;
8522 if (*pstr != 0)
8523 {
8524 as_bad (_("Junk after '}': '%s'"), imm_start);
8525 return 0;
8526 }
8527
8528 exp = &im_expressions[i.imm_operands++];
8529 i.op[this_operand].imms = exp;
8530
8531 exp->X_op = O_constant;
8532 exp->X_add_number = 0;
8533 exp->X_add_symbol = (symbolS *) 0;
8534 exp->X_op_symbol = (symbolS *) 0;
8535
8536 i.types[this_operand].bitfield.imm8 = 1;
8537 return 1;
8538}
8539
fc0763e6 8540/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8541 on error. */
252b5132 8542
252b5132 8543static int
a7619375 8544i386_att_operand (char *operand_string)
252b5132 8545{
af6bdddf
AM		 8546 const reg_entry *r;
8547 char *end_op;
24eab124 8548 char *op_string = operand_string;
252b5132 8549
24eab124 8550 if (is_space_char (*op_string))
252b5132
RH		 8551 ++op_string;
8552
24eab124 8553 /* We check for an absolute prefix (differentiating,
47926f60 8554 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8555 if (*op_string == ABSOLUTE_PREFIX)
8556 {
8557 ++op_string;
8558 if (is_space_char (*op_string))
8559 ++op_string;
40fb9820 8560 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8561 }
252b5132 8562
47926f60 8563 /* Check if operand is a register. */
4d1bb795 8564 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8565 {
40fb9820
L		 8566 i386_operand_type temp;
8567
24eab124
AM		 8568 /* Check for a segment override by searching for ':' after a
8569 segment register. */
8570 op_string = end_op;
8571 if (is_space_char (*op_string))
8572 ++op_string;
40fb9820
L		 8573 if (*op_string == ':'
8574 && (r->reg_type.bitfield.sreg2
8575 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8576 {
8577 switch (r->reg_num)
8578 {
8579 case 0:
8580 i.seg[i.mem_operands] = &es;
8581 break;
8582 case 1:
8583 i.seg[i.mem_operands] = &cs;
8584 break;
8585 case 2:
8586 i.seg[i.mem_operands] = &ss;
8587 break;
8588 case 3:
8589 i.seg[i.mem_operands] = &ds;
8590 break;
8591 case 4:
8592 i.seg[i.mem_operands] = &fs;
8593 break;
8594 case 5:
8595 i.seg[i.mem_operands] = &gs;
8596 break;
8597 }
252b5132 8598
24eab124 8599 /* Skip the ':' and whitespace. */
252b5132
RH		 8600 ++op_string;
8601 if (is_space_char (*op_string))
24eab124 8602 ++op_string;
252b5132 8603
24eab124
AM		 8604 if (!is_digit_char (*op_string)
8605 && !is_identifier_char (*op_string)
8606 && *op_string != '('
8607 && *op_string != ABSOLUTE_PREFIX)
8608 {
8609 as_bad (_("bad memory operand `%s'"), op_string);
8610 return 0;
8611 }
47926f60 8612 /* Handle case of %es:*foo. */
24eab124
AM		 8613 if (*op_string == ABSOLUTE_PREFIX)
8614 {
8615 ++op_string;
8616 if (is_space_char (*op_string))
8617 ++op_string;
40fb9820 8618 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8619 }
8620 goto do_memory_reference;
8621 }
43234a1e
L		 8622
8623 /* Handle vector operations. */
8624 if (*op_string == '{')
8625 {
8626 op_string = check_VecOperations (op_string, NULL);
8627 if (op_string == NULL)
8628 return 0;
8629 }
8630
24eab124
AM		 8631 if (*op_string)
8632 {
d0b47220 8633 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8634 return 0;
8635 }
40fb9820
L		 8636 temp = r->reg_type;
8637 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8638 i.types[this_operand] = operand_type_or (i.types[this_operand],
8639 temp);
7d5e4556 8640 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8641 i.op[this_operand].regs = r;
24eab124
AM		 8642 i.reg_operands++;
8643 }
af6bdddf
AM		 8644 else if (*op_string == REGISTER_PREFIX)
8645 {
8646 as_bad (_("bad register name `%s'"), op_string);
8647 return 0;
8648 }
24eab124 8649 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8650 {
24eab124 8651 ++op_string;
40fb9820 8652 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8653 {
d0b47220 8654 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8655 return 0;
8656 }
8657 if (!i386_immediate (op_string))
8658 return 0;
8659 }
43234a1e
L		 8660 else if (RC_SAE_immediate (operand_string))
8661 {
8662 /* If it is a RC or SAE immediate, do nothing. */
8663 ;
8664 }
24eab124
AM		 8665 else if (is_digit_char (*op_string)
8666 || is_identifier_char (*op_string)
e5cb08ac 8667 || *op_string == '(')
24eab124 8668 {
47926f60 8669 /* This is a memory reference of some sort. */
af6bdddf 8670 char *base_string;
252b5132 8671
47926f60 8672 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8673 char *displacement_string_start;
8674 char *displacement_string_end;
43234a1e 8675 char *vop_start;
252b5132 8676
24eab124 8677 do_memory_reference:
24eab124 8678 if ((i.mem_operands == 1
40fb9820 8679 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8680 || i.mem_operands == 2)
8681 {
8682 as_bad (_("too many memory references for `%s'"),
8683 current_templates->start->name);
8684 return 0;
8685 }
252b5132 8686
24eab124
AM		 8687 /* Check for base index form. We detect the base index form by
8688 looking for an ')' at the end of the operand, searching
8689 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8690 after the '('. */
af6bdddf 8691 base_string = op_string + strlen (op_string);
c3332e24 8692
43234a1e
L		 8693 /* Handle vector operations. */
8694 vop_start = strchr (op_string, '{');
8695 if (vop_start && vop_start < base_string)
8696 {
8697 if (check_VecOperations (vop_start, base_string) == NULL)
8698 return 0;
8699 base_string = vop_start;
8700 }
8701
af6bdddf
AM		 8702 --base_string;
8703 if (is_space_char (*base_string))
8704 --base_string;
252b5132 8705
47926f60 8706 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8707 displacement_string_start = op_string;
8708 displacement_string_end = base_string + 1;
252b5132 8709
24eab124
AM		 8710 if (*base_string == ')')
8711 {
af6bdddf 8712 char *temp_string;
24eab124
AM		 8713 unsigned int parens_balanced = 1;
8714 /* We've already checked that the number of left & right ()'s are
47926f60 8715 equal, so this loop will not be infinite. */
24eab124
AM		 8716 do
8717 {
8718 base_string--;
8719 if (*base_string == ')')
8720 parens_balanced++;
8721 if (*base_string == '(')
8722 parens_balanced--;
8723 }
8724 while (parens_balanced);
c3332e24 8725
af6bdddf 8726 temp_string = base_string;
c3332e24 8727
24eab124 8728 /* Skip past '(' and whitespace. */
252b5132
RH		 8729 ++base_string;
8730 if (is_space_char (*base_string))
24eab124 8731 ++base_string;
252b5132 8732
af6bdddf 8733 if (*base_string == ','
4eed87de
AM		 8734 || ((i.base_reg = parse_register (base_string, &end_op))
8735 != NULL))
252b5132 8736 {
af6bdddf 8737 displacement_string_end = temp_string;
252b5132 8738
40fb9820 8739 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8740
af6bdddf 8741 if (i.base_reg)
24eab124 8742 {
24eab124
AM		 8743 base_string = end_op;
8744 if (is_space_char (*base_string))
8745 ++base_string;
af6bdddf
AM		 8746 }
8747
8748 /* There may be an index reg or scale factor here. */
8749 if (*base_string == ',')
8750 {
8751 ++base_string;
8752 if (is_space_char (*base_string))
8753 ++base_string;
8754
4eed87de
AM		 8755 if ((i.index_reg = parse_register (base_string, &end_op))
8756 != NULL)
24eab124 8757 {
af6bdddf 8758 base_string = end_op;
24eab124
AM		 8759 if (is_space_char (*base_string))
8760 ++base_string;
af6bdddf
AM		 8761 if (*base_string == ',')
8762 {
8763 ++base_string;
8764 if (is_space_char (*base_string))
8765 ++base_string;
8766 }
e5cb08ac 8767 else if (*base_string != ')')
af6bdddf 8768 {
4eed87de
AM		 8769 as_bad (_("expecting `,' or `)' "
8770 "after index register in `%s'"),
af6bdddf
AM		 8771 operand_string);
8772 return 0;
8773 }
24eab124 8774 }
af6bdddf 8775 else if (*base_string == REGISTER_PREFIX)
24eab124 8776 {
f76bf5e0
L		 8777 end_op = strchr (base_string, ',');
8778 if (end_op)
8779 *end_op = '\0';
af6bdddf 8780 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8781 return 0;
8782 }
252b5132 8783
47926f60 8784 /* Check for scale factor. */
551c1ca1 8785 if (*base_string != ')')
af6bdddf 8786 {
551c1ca1
AM		 8787 char *end_scale = i386_scale (base_string);
8788
8789 if (!end_scale)
af6bdddf 8790 return 0;
24eab124 8791
551c1ca1 8792 base_string = end_scale;
af6bdddf
AM		 8793 if (is_space_char (*base_string))
8794 ++base_string;
8795 if (*base_string != ')')
8796 {
4eed87de
AM		 8797 as_bad (_("expecting `)' "
8798 "after scale factor in `%s'"),
af6bdddf
AM		 8799 operand_string);
8800 return 0;
8801 }
8802 }
8803 else if (!i.index_reg)
24eab124 8804 {
4eed87de
AM		 8805 as_bad (_("expecting index register or scale factor "
8806 "after `,'; got '%c'"),
af6bdddf 8807 *base_string);
24eab124
AM		 8808 return 0;
8809 }
8810 }
af6bdddf 8811 else if (*base_string != ')')
24eab124 8812 {
4eed87de
AM		 8813 as_bad (_("expecting `,' or `)' "
8814 "after base register in `%s'"),
af6bdddf 8815 operand_string);
24eab124
AM		 8816 return 0;
8817 }
c3332e24 8818 }
af6bdddf 8819 else if (*base_string == REGISTER_PREFIX)
c3332e24 8820 {
f76bf5e0
L		 8821 end_op = strchr (base_string, ',');
8822 if (end_op)
8823 *end_op = '\0';
af6bdddf 8824 as_bad (_("bad register name `%s'"), base_string);
24eab124 8825 return 0;
c3332e24 8826 }
24eab124
AM		 8827 }
8828
8829 /* If there's an expression beginning the operand, parse it,
8830 assuming displacement_string_start and
8831 displacement_string_end are meaningful. */
8832 if (displacement_string_start != displacement_string_end)
8833 {
8834 if (!i386_displacement (displacement_string_start,
8835 displacement_string_end))
8836 return 0;
8837 }
8838
8839 /* Special case for (%dx) while doing input/output op. */
8840 if (i.base_reg
0dfbf9d7
L		 8841 && operand_type_equal (&i.base_reg->reg_type,
8842 &reg16_inoutportreg)
24eab124
AM		 8843 && i.index_reg == 0
8844 && i.log2_scale_factor == 0
8845 && i.seg[i.mem_operands] == 0
40fb9820 8846 && !operand_type_check (i.types[this_operand], disp))
24eab124 8847 {
65da13b5 8848 i.types[this_operand] = inoutportreg;
24eab124
AM		 8849 return 1;
8850 }
8851
eecb386c
AM		 8852 if (i386_index_check (operand_string) == 0)
8853 return 0;
5c07affc 8854 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8855 i.mem_operands++;
8856 }
8857 else
ce8a8b2f
AM		 8858 {
8859 /* It's not a memory operand; argh! */
24eab124
AM		 8860 as_bad (_("invalid char %s beginning operand %d `%s'"),
8861 output_invalid (*op_string),
8862 this_operand + 1,
8863 op_string);
8864 return 0;
8865 }
47926f60 8866 return 1; /* Normal return. */
252b5132
RH		 8867}
8868\f
fa94de6b
RM		 8869/* Calculate the maximum variable size (i.e., excluding fr_fix)
8870 that an rs_machine_dependent frag may reach. */
8871
8872unsigned int
8873i386_frag_max_var (fragS *frag)
8874{
8875 /* The only relaxable frags are for jumps.
8876 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8877 gas_assert (frag->fr_type == rs_machine_dependent);
8878 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8879}
8880
ee7fcc42
AM		 8881/* md_estimate_size_before_relax()
8882
8883 Called just before relax() for rs_machine_dependent frags. The x86
8884 assembler uses these frags to handle variable size jump
8885 instructions.
8886
8887 Any symbol that is now undefined will not become defined.
8888 Return the correct fr_subtype in the frag.
8889 Return the initial "guess for variable size of frag" to caller.
8890 The guess is actually the growth beyond the fixed part. Whatever
8891 we do to grow the fixed or variable part contributes to our
8892 returned value. */
8893
252b5132 8894int
7016a5d5 8895md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8896{
252b5132 8897 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8898 check for un-relaxable symbols. On an ELF system, we can't relax
8899 an externally visible symbol, because it may be overridden by a
8900 shared library. */
8901 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8902#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8903 || (IS_ELF
31312f95 8904 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 8905 || S_IS_WEAK (fragP->fr_symbol)
8906 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
8907 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 8908#endif
8909#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8910 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8911 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8912#endif
8913 )
252b5132 8914 {
b98ef147
AM		 8915 /* Symbol is undefined in this segment, or we need to keep a
8916 reloc so that weak symbols can be overridden. */
8917 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8918 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8919 unsigned char *opcode;
8920 int old_fr_fix;
f6af82bd 8921
ee7fcc42 8922 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8923 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8924 else if (size == 2)
f6af82bd
AM		 8925 reloc_type = BFD_RELOC_16_PCREL;
8926 else
8927 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8928
ee7fcc42
AM		 8929 old_fr_fix = fragP->fr_fix;
8930 opcode = (unsigned char *) fragP->fr_opcode;
8931
fddf5b5b 8932 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8933 {
fddf5b5b
AM		 8934 case UNCOND_JUMP:
8935 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8936 opcode[0] = 0xe9;
252b5132 8937 fragP->fr_fix += size;
062cd5e7
AS		 8938 fix_new (fragP, old_fr_fix, size,
8939 fragP->fr_symbol,
8940 fragP->fr_offset, 1,
8941 reloc_type);
252b5132
RH		 8942 break;
8943
fddf5b5b 8944 case COND_JUMP86:
412167cb
AM		 8945 if (size == 2
8946 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8947 {
8948 /* Negate the condition, and branch past an
8949 unconditional jump. */
8950 opcode[0] ^= 1;
8951 opcode[1] = 3;
8952 /* Insert an unconditional jump. */
8953 opcode[2] = 0xe9;
8954 /* We added two extra opcode bytes, and have a two byte
8955 offset. */
8956 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8957 fix_new (fragP, old_fr_fix + 2, 2,
8958 fragP->fr_symbol,
8959 fragP->fr_offset, 1,
8960 reloc_type);
fddf5b5b
AM		 8961 break;
8962 }
8963 /* Fall through. */
8964
8965 case COND_JUMP:
412167cb
AM		 8966 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8967 {
3e02c1cc
AM		 8968 fixS *fixP;
8969
412167cb 8970 fragP->fr_fix += 1;
3e02c1cc
AM		 8971 fixP = fix_new (fragP, old_fr_fix, 1,
8972 fragP->fr_symbol,
8973 fragP->fr_offset, 1,
8974 BFD_RELOC_8_PCREL);
8975 fixP->fx_signed = 1;
412167cb
AM		 8976 break;
8977 }
93c2a809 8978
24eab124 8979 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8980 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8981 opcode[1] = opcode[0] + 0x10;
f6af82bd 8982 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8983 /* We've added an opcode byte. */
8984 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8985 fix_new (fragP, old_fr_fix + 1, size,
8986 fragP->fr_symbol,
8987 fragP->fr_offset, 1,
8988 reloc_type);
252b5132 8989 break;
fddf5b5b
AM		 8990
8991 default:
8992 BAD_CASE (fragP->fr_subtype);
8993 break;
252b5132
RH		 8994 }
8995 frag_wane (fragP);
ee7fcc42 8996 return fragP->fr_fix - old_fr_fix;
252b5132 8997 }
93c2a809 8998
93c2a809
AM		 8999 /* Guess size depending on current relax state. Initially the relax
9000 state will correspond to a short jump and we return 1, because
9001 the variable part of the frag (the branch offset) is one byte
9002 long. However, we can relax a section more than once and in that
9003 case we must either set fr_subtype back to the unrelaxed state,
9004 or return the value for the appropriate branch. */
9005 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9006}
9007
47926f60
KH		 9008/* Called after relax() is finished.
9009
9010 In: Address of frag.
9011 fr_type == rs_machine_dependent.
9012 fr_subtype is what the address relaxed to.
9013
9014 Out: Any fixSs and constants are set up.
9015 Caller will turn frag into a ".space 0". */
9016
252b5132 9017void
7016a5d5
TG		 9018md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9019 fragS *fragP)
252b5132 9020{
29b0f896 9021 unsigned char *opcode;
252b5132 9022 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9023 offsetT target_address;
9024 offsetT opcode_address;
252b5132 9025 unsigned int extension = 0;
847f7ad4 9026 offsetT displacement_from_opcode_start;
252b5132
RH		 9027
9028 opcode = (unsigned char *) fragP->fr_opcode;
9029
47926f60 9030 /* Address we want to reach in file space. */
252b5132 9031 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9032
47926f60 9033 /* Address opcode resides at in file space. */
252b5132
RH		 9034 opcode_address = fragP->fr_address + fragP->fr_fix;
9035
47926f60 9036 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9037 displacement_from_opcode_start = target_address - opcode_address;
9038
fddf5b5b 9039 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9040 {
47926f60
KH		 9041 /* Don't have to change opcode. */
9042 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9043 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9044 }
9045 else
9046 {
9047 if (no_cond_jump_promotion
9048 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9049 as_warn_where (fragP->fr_file, fragP->fr_line,
9050 _("long jump required"));
252b5132 9051
fddf5b5b
AM		 9052 switch (fragP->fr_subtype)
9053 {
9054 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9055 extension = 4; /* 1 opcode + 4 displacement */
9056 opcode[0] = 0xe9;
9057 where_to_put_displacement = &opcode[1];
9058 break;
252b5132 9059
fddf5b5b
AM		 9060 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9061 extension = 2; /* 1 opcode + 2 displacement */
9062 opcode[0] = 0xe9;
9063 where_to_put_displacement = &opcode[1];
9064 break;
252b5132 9065
fddf5b5b
AM		 9066 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9067 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9068 extension = 5; /* 2 opcode + 4 displacement */
9069 opcode[1] = opcode[0] + 0x10;
9070 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9071 where_to_put_displacement = &opcode[2];
9072 break;
252b5132 9073
fddf5b5b
AM		 9074 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9075 extension = 3; /* 2 opcode + 2 displacement */
9076 opcode[1] = opcode[0] + 0x10;
9077 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9078 where_to_put_displacement = &opcode[2];
9079 break;
252b5132 9080
fddf5b5b
AM		 9081 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9082 extension = 4;
9083 opcode[0] ^= 1;
9084 opcode[1] = 3;
9085 opcode[2] = 0xe9;
9086 where_to_put_displacement = &opcode[3];
9087 break;
9088
9089 default:
9090 BAD_CASE (fragP->fr_subtype);
9091 break;
9092 }
252b5132 9093 }
fddf5b5b 9094
7b81dfbb
AJ		 9095 /* If size if less then four we are sure that the operand fits,
9096 but if it's 4, then it could be that the displacement is larger
9097 then -/+ 2GB. */
9098 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9099 && object_64bit
9100 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9101 + ((addressT) 1 << 31))
9102 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9103 {
9104 as_bad_where (fragP->fr_file, fragP->fr_line,
9105 _("jump target out of range"));
9106 /* Make us emit 0. */
9107 displacement_from_opcode_start = extension;
9108 }
47926f60 9109 /* Now put displacement after opcode. */
252b5132
RH		 9110 md_number_to_chars ((char *) where_to_put_displacement,
9111 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9112 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9113 fragP->fr_fix += extension;
9114}
9115\f
7016a5d5 9116/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9117 by our caller that we have all the info we need to fix it up.
9118
7016a5d5
TG		 9119 Parameter valP is the pointer to the value of the bits.
9120
252b5132
RH		 9121 On the 386, immediates, displacements, and data pointers are all in
9122 the same (little-endian) format, so we don't need to care about which
9123 we are handling. */
9124
94f592af 9125void
7016a5d5 9126md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9127{
94f592af 9128 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9129 valueT value = *valP;
252b5132 9130
f86103b7 9131#if !defined (TE_Mach)
93382f6d
AM		 9132 if (fixP->fx_pcrel)
9133 {
9134 switch (fixP->fx_r_type)
9135 {
5865bb77
ILT		 9136 default:
9137 break;
9138
d6ab8113
JB		 9139 case BFD_RELOC_64:
9140 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9141 break;
93382f6d 9142 case BFD_RELOC_32:
ae8887b5 9143 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9144 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9145 break;
9146 case BFD_RELOC_16:
9147 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9148 break;
9149 case BFD_RELOC_8:
9150 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9151 break;
9152 }
9153 }
252b5132 9154
a161fe53 9155 if (fixP->fx_addsy != NULL
31312f95 9156 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9157 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9158 || fixP->fx_r_type == BFD_RELOC_16_PCREL
c3320543
L		 9159 || fixP->fx_r_type == BFD_RELOC_8_PCREL
9160 || fixP->fx_r_type == BFD_RELOC_X86_64_PC32_BND)
31312f95 9161 && !use_rela_relocations)
252b5132 9162 {
31312f95
AM		 9163 /* This is a hack. There should be a better way to handle this.
9164 This covers for the fact that bfd_install_relocation will
9165 subtract the current location (for partial_inplace, PC relative
9166 relocations); see more below. */
252b5132 9167#ifndef OBJ_AOUT
718ddfc0 9168 if (IS_ELF
252b5132
RH		 9169#ifdef TE_PE
9170 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9171#endif
9172 )
9173 value += fixP->fx_where + fixP->fx_frag->fr_address;
9174#endif
9175#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9176 if (IS_ELF)
252b5132 9177 {
6539b54b 9178 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9179
6539b54b 9180 if ((sym_seg == seg
2f66722d 9181 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9182 && sym_seg != absolute_section))
af65af87 9183 && !generic_force_reloc (fixP))
2f66722d
AM		 9184 {
9185 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9186 bfd_install_relocation subtracts them out again. I think
9187 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9188 it. FIXME. */
9189 value += fixP->fx_where + fixP->fx_frag->fr_address;
9190 }
252b5132
RH		 9191 }
9192#endif
9193#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9194 /* For some reason, the PE format does not store a
9195 section address offset for a PC relative symbol. */
9196 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9197 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9198 value += md_pcrel_from (fixP);
9199#endif
9200 }
fbeb56a4 9201#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9202 if (fixP->fx_addsy != NULL
9203 && S_IS_WEAK (fixP->fx_addsy)
9204 /* PR 16858: Do not modify weak function references. */
9205 && ! fixP->fx_pcrel)
fbeb56a4 9206 {
296a8689
NC		 9207#if !defined (TE_PEP)
9208 /* For x86 PE weak function symbols are neither PC-relative
9209 nor do they set S_IS_FUNCTION. So the only reliable way
9210 to detect them is to check the flags of their containing
9211 section. */
9212 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9213 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9214 ;
9215 else
9216#endif
fbeb56a4
DK		 9217 value -= S_GET_VALUE (fixP->fx_addsy);
9218 }
9219#endif
252b5132
RH		 9220
9221 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9222 and we must not disappoint it. */
252b5132 9223#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9224 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9225 switch (fixP->fx_r_type)
9226 {
9227 case BFD_RELOC_386_PLT32:
3e73aa7c 9228 case BFD_RELOC_X86_64_PLT32:
c3320543 9229 case BFD_RELOC_X86_64_PLT32_BND:
47926f60
KH		 9230 /* Make the jump instruction point to the address of the operand. At
9231 runtime we merely add the offset to the actual PLT entry. */
9232 value = -4;
9233 break;
31312f95 9234
13ae64f3
JJ		 9235 case BFD_RELOC_386_TLS_GD:
9236 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9237 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9238 case BFD_RELOC_386_TLS_IE:
9239 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9240 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9241 case BFD_RELOC_X86_64_TLSGD:
9242 case BFD_RELOC_X86_64_TLSLD:
9243 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9244 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9245 value = 0; /* Fully resolved at runtime. No addend. */
9246 /* Fallthrough */
9247 case BFD_RELOC_386_TLS_LE:
9248 case BFD_RELOC_386_TLS_LDO_32:
9249 case BFD_RELOC_386_TLS_LE_32:
9250 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9251 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9252 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9253 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9254 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9255 break;
9256
67a4f2b7
AO		 9257 case BFD_RELOC_386_TLS_DESC_CALL:
9258 case BFD_RELOC_X86_64_TLSDESC_CALL:
9259 value = 0; /* Fully resolved at runtime. No addend. */
9260 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9261 fixP->fx_done = 0;
9262 return;
9263
00f7efb6
JJ		 9264 case BFD_RELOC_386_GOT32:
9265 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9266 value = 0; /* Fully resolved at runtime. No addend. */
9267 break;
47926f60
KH		 9268
9269 case BFD_RELOC_VTABLE_INHERIT:
9270 case BFD_RELOC_VTABLE_ENTRY:
9271 fixP->fx_done = 0;
94f592af 9272 return;
47926f60
KH		 9273
9274 default:
9275 break;
9276 }
9277#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9278 *valP = value;
f86103b7 9279#endif /* !defined (TE_Mach) */
3e73aa7c 9280
3e73aa7c 9281 /* Are we finished with this relocation now? */
c6682705 9282 if (fixP->fx_addsy == NULL)
3e73aa7c 9283 fixP->fx_done = 1;
fbeb56a4
DK		 9284#if defined (OBJ_COFF) && defined (TE_PE)
9285 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9286 {
9287 fixP->fx_done = 0;
9288 /* Remember value for tc_gen_reloc. */
9289 fixP->fx_addnumber = value;
9290 /* Clear out the frag for now. */
9291 value = 0;
9292 }
9293#endif
3e73aa7c
JH		 9294 else if (use_rela_relocations)
9295 {
9296 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9297 /* Remember value for tc_gen_reloc. */
9298 fixP->fx_addnumber = value;
3e73aa7c
JH		 9299 value = 0;
9300 }
f86103b7 9301
94f592af 9302 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9303}
252b5132 9304\f
252b5132 9305char *
499ac353 9306md_atof (int type, char *litP, int *sizeP)
252b5132 9307{
499ac353
NC		 9308 /* This outputs the LITTLENUMs in REVERSE order;
9309 in accord with the bigendian 386. */
9310 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9311}
9312\f
2d545b82 9313static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9314
252b5132 9315static char *
e3bb37b5 9316output_invalid (int c)
252b5132 9317{
3882b010 9318 if (ISPRINT (c))
f9f21a03
L		 9319 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9320 "'%c'", c);
252b5132 9321 else
f9f21a03 9322 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9323 "(0x%x)", (unsigned char) c);
252b5132
RH		 9324 return output_invalid_buf;
9325}
9326
af6bdddf 9327/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9328
9329static const reg_entry *
4d1bb795 9330parse_real_register (char *reg_string, char **end_op)
252b5132 9331{
af6bdddf
AM		 9332 char *s = reg_string;
9333 char *p;
252b5132
RH		 9334 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9335 const reg_entry *r;
9336
9337 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9338 if (*s == REGISTER_PREFIX)
9339 ++s;
9340
9341 if (is_space_char (*s))
9342 ++s;
9343
9344 p = reg_name_given;
af6bdddf 9345 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9346 {
9347 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9348 return (const reg_entry *) NULL;
9349 s++;
252b5132
RH		 9350 }
9351
6588847e
DN		 9352 /* For naked regs, make sure that we are not dealing with an identifier.
9353 This prevents confusing an identifier like `eax_var' with register
9354 `eax'. */
9355 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9356 return (const reg_entry *) NULL;
9357
af6bdddf 9358 *end_op = s;
252b5132
RH		 9359
9360 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9361
5f47d35b 9362 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9363 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9364 {
5f47d35b
AM		 9365 if (is_space_char (*s))
9366 ++s;
9367 if (*s == '(')
9368 {
af6bdddf 9369 ++s;
5f47d35b
AM		 9370 if (is_space_char (*s))
9371 ++s;
9372 if (*s >= '0' && *s <= '7')
9373 {
db557034 9374 int fpr = *s - '0';
af6bdddf 9375 ++s;
5f47d35b
AM		 9376 if (is_space_char (*s))
9377 ++s;
9378 if (*s == ')')
9379 {
9380 *end_op = s + 1;
1e9cc1c2 9381 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9382 know (r);
9383 return r + fpr;
5f47d35b 9384 }
5f47d35b 9385 }
47926f60 9386 /* We have "%st(" then garbage. */
5f47d35b
AM		 9387 return (const reg_entry *) NULL;
9388 }
9389 }
9390
a60de03c
JB		 9391 if (r == NULL || allow_pseudo_reg)
9392 return r;
9393
0dfbf9d7 9394 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9395 return (const reg_entry *) NULL;
9396
192dc9c6
JB		 9397 if ((r->reg_type.bitfield.reg32
9398 || r->reg_type.bitfield.sreg3
9399 || r->reg_type.bitfield.control
9400 || r->reg_type.bitfield.debug
9401 || r->reg_type.bitfield.test)
9402 && !cpu_arch_flags.bitfield.cpui386)
9403 return (const reg_entry *) NULL;
9404
309d3373
JB		 9405 if (r->reg_type.bitfield.floatreg
9406 && !cpu_arch_flags.bitfield.cpu8087
9407 && !cpu_arch_flags.bitfield.cpu287
9408 && !cpu_arch_flags.bitfield.cpu387)
9409 return (const reg_entry *) NULL;
9410
192dc9c6
JB		 9411 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9412 return (const reg_entry *) NULL;
9413
9414 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9415 return (const reg_entry *) NULL;
9416
40f12533
L		 9417 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9418 return (const reg_entry *) NULL;
9419
43234a1e
L		 9420 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9421 && !cpu_arch_flags.bitfield.cpuavx512f)
9422 return (const reg_entry *) NULL;
9423
db51cc60 9424 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9425 if (!allow_index_reg
db51cc60
L		 9426 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9427 return (const reg_entry *) NULL;
9428
43234a1e
L		 9429 /* Upper 16 vector register is only available with VREX in 64bit
9430 mode. */
9431 if ((r->reg_flags & RegVRex))
9432 {
9433 if (!cpu_arch_flags.bitfield.cpuvrex
9434 || flag_code != CODE_64BIT)
9435 return (const reg_entry *) NULL;
9436
9437 i.need_vrex = 1;
9438 }
9439
a60de03c
JB		 9440 if (((r->reg_flags & (RegRex64 | RegRex))
9441 || r->reg_type.bitfield.reg64)
40fb9820 9442 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9443 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9444 && flag_code != CODE_64BIT)
20f0a1fc 9445 return (const reg_entry *) NULL;
1ae00879 9446
b7240065
JB		 9447 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9448 return (const reg_entry *) NULL;
9449
252b5132
RH		 9450 return r;
9451}
4d1bb795
JB		 9452
9453/* REG_STRING starts *before* REGISTER_PREFIX. */
9454
9455static const reg_entry *
9456parse_register (char *reg_string, char **end_op)
9457{
9458 const reg_entry *r;
9459
9460 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9461 r = parse_real_register (reg_string, end_op);
9462 else
9463 r = NULL;
9464 if (!r)
9465 {
9466 char *save = input_line_pointer;
9467 char c;
9468 symbolS *symbolP;
9469
9470 input_line_pointer = reg_string;
9471 c = get_symbol_end ();
9472 symbolP = symbol_find (reg_string);
9473 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9474 {
9475 const expressionS *e = symbol_get_value_expression (symbolP);
9476
0398aac5 9477 know (e->X_op == O_register);
4eed87de 9478 know (e->X_add_number >= 0
c3fe08fa 9479 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9480 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9481 if ((r->reg_flags & RegVRex))
9482 i.need_vrex = 1;
4d1bb795
JB		 9483 *end_op = input_line_pointer;
9484 }
9485 *input_line_pointer = c;
9486 input_line_pointer = save;
9487 }
9488 return r;
9489}
9490
9491int
9492i386_parse_name (char *name, expressionS *e, char *nextcharP)
9493{
9494 const reg_entry *r;
9495 char *end = input_line_pointer;
9496
9497 *end = *nextcharP;
9498 r = parse_register (name, &input_line_pointer);
9499 if (r && end <= input_line_pointer)
9500 {
9501 *nextcharP = *input_line_pointer;
9502 *input_line_pointer = 0;
9503 e->X_op = O_register;
9504 e->X_add_number = r - i386_regtab;
9505 return 1;
9506 }
9507 input_line_pointer = end;
9508 *end = 0;
ee86248c 9509 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9510}
9511
9512void
9513md_operand (expressionS *e)
9514{
ee86248c
JB		 9515 char *end;
9516 const reg_entry *r;
4d1bb795 9517
ee86248c
JB		 9518 switch (*input_line_pointer)
9519 {
9520 case REGISTER_PREFIX:
9521 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9522 if (r)
9523 {
9524 e->X_op = O_register;
9525 e->X_add_number = r - i386_regtab;
9526 input_line_pointer = end;
9527 }
ee86248c
JB		 9528 break;
9529
9530 case '[':
9c2799c2 9531 gas_assert (intel_syntax);
ee86248c
JB		 9532 end = input_line_pointer++;
9533 expression (e);
9534 if (*input_line_pointer == ']')
9535 {
9536 ++input_line_pointer;
9537 e->X_op_symbol = make_expr_symbol (e);
9538 e->X_add_symbol = NULL;
9539 e->X_add_number = 0;
9540 e->X_op = O_index;
9541 }
9542 else
9543 {
9544 e->X_op = O_absent;
9545 input_line_pointer = end;
9546 }
9547 break;
4d1bb795
JB		 9548 }
9549}
9550
252b5132 9551\f
4cc782b5 9552#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9553const char *md_shortopts = "kVQ:sqn";
252b5132 9554#else
12b55ccc 9555const char *md_shortopts = "qn";
252b5132 9556#endif
6e0b89ee 9557
3e73aa7c 9558#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9559#define OPTION_64 (OPTION_MD_BASE + 1)
9560#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9561#define OPTION_MARCH (OPTION_MD_BASE + 3)
9562#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9563#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9564#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9565#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9566#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9567#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9568#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9569#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9570#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9571#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9572#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9573#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9574#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9575#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9576#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
a5094208 9577#define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9578#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
b3b91714 9579
99ad8390
NC		 9580struct option md_longopts[] =
9581{
3e73aa7c 9582 {"32", no_argument, NULL, OPTION_32},
321098a5 9583#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9584 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9585 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9586#endif
9587#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9588 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 9589#endif
b3b91714 9590 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9591 {"march", required_argument, NULL, OPTION_MARCH},
9592 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9593 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9594 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9595 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9596 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9597 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9598 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9599 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9600 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9601 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9602 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9603 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9604 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9605# if defined (TE_PE) || defined (TE_PEP)
9606 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9607#endif
a5094208 9608 {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX},
d3d3c6db 9609 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
252b5132
RH		 9610 {NULL, no_argument, NULL, 0}
9611};
9612size_t md_longopts_size = sizeof (md_longopts);
9613
9614int
9103f4f4 9615md_parse_option (int c, char *arg)
252b5132 9616{
91d6fa6a 9617 unsigned int j;
6305a203 9618 char *arch, *next;
9103f4f4 9619
252b5132
RH		 9620 switch (c)
9621 {
12b55ccc
L		 9622 case 'n':
9623 optimize_align_code = 0;
9624 break;
9625
a38cf1db
AM		 9626 case 'q':
9627 quiet_warnings = 1;
252b5132
RH		 9628 break;
9629
9630#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9631 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9632 should be emitted or not. FIXME: Not implemented. */
9633 case 'Q':
252b5132
RH		 9634 break;
9635
9636 /* -V: SVR4 argument to print version ID. */
9637 case 'V':
9638 print_version_id ();
9639 break;
9640
a38cf1db
AM		 9641 /* -k: Ignore for FreeBSD compatibility. */
9642 case 'k':
252b5132 9643 break;
4cc782b5
ILT		 9644
9645 case 's':
9646 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9647 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9648 break;
99ad8390 9649#endif
321098a5 9650#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9651 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9652 case OPTION_64:
9653 {
9654 const char **list, **l;
9655
3e73aa7c
JH		 9656 list = bfd_target_list ();
9657 for (l = list; *l != NULL; l++)
8620418b 9658 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9659 || strcmp (*l, "coff-x86-64") == 0
9660 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9661 || strcmp (*l, "pei-x86-64") == 0
9662 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9663 {
9664 default_arch = "x86_64";
9665 break;
9666 }
3e73aa7c 9667 if (*l == NULL)
2b5d6a91 9668 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9669 free (list);
9670 }
9671 break;
9672#endif
252b5132 9673
351f65ca 9674#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9675 case OPTION_X32:
351f65ca
L		 9676 if (IS_ELF)
9677 {
9678 const char **list, **l;
9679
9680 list = bfd_target_list ();
9681 for (l = list; *l != NULL; l++)
9682 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9683 {
9684 default_arch = "x86_64:32";
9685 break;
9686 }
9687 if (*l == NULL)
2b5d6a91 9688 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9689 free (list);
9690 }
9691 else
9692 as_fatal (_("32bit x86_64 is only supported for ELF"));
9693 break;
9694#endif
9695
6e0b89ee
AM		 9696 case OPTION_32:
9697 default_arch = "i386";
9698 break;
9699
b3b91714
AM		 9700 case OPTION_DIVIDE:
9701#ifdef SVR4_COMMENT_CHARS
9702 {
9703 char *n, *t;
9704 const char *s;
9705
9706 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9707 t = n;
9708 for (s = i386_comment_chars; *s != '\0'; s++)
9709 if (*s != '/')
9710 *t++ = *s;
9711 *t = '\0';
9712 i386_comment_chars = n;
9713 }
9714#endif
9715 break;
9716
9103f4f4 9717 case OPTION_MARCH:
6305a203
L		 9718 arch = xstrdup (arg);
9719 do
9103f4f4 9720 {
6305a203 9721 if (*arch == '.')
2b5d6a91 9722 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9723 next = strchr (arch, '+');
9724 if (next)
9725 *next++ = '\0';
91d6fa6a 9726 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9727 {
91d6fa6a 9728 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9729 {
6305a203 9730 /* Processor. */
1ded5609
JB		 9731 if (! cpu_arch[j].flags.bitfield.cpui386)
9732 continue;
9733
91d6fa6a 9734 cpu_arch_name = cpu_arch[j].name;
6305a203 9735 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9736 cpu_arch_flags = cpu_arch[j].flags;
9737 cpu_arch_isa = cpu_arch[j].type;
9738 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9739 if (!cpu_arch_tune_set)
9740 {
9741 cpu_arch_tune = cpu_arch_isa;
9742 cpu_arch_tune_flags = cpu_arch_isa_flags;
9743 }
9744 break;
9745 }
91d6fa6a
NC		 9746 else if (*cpu_arch [j].name == '.'
9747 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9748 {
9749 /* ISA entension. */
9750 i386_cpu_flags flags;
309d3373 9751
49021df2 9752 if (!cpu_arch[j].negated)
309d3373 9753 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9754 cpu_arch[j].flags);
309d3373
JB		 9755 else
9756 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9757 cpu_arch[j].flags);
0dfbf9d7 9758 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9759 {
9760 if (cpu_sub_arch_name)
9761 {
9762 char *name = cpu_sub_arch_name;
9763 cpu_sub_arch_name = concat (name,
91d6fa6a 9764 cpu_arch[j].name,
1bf57e9f 9765 (const char *) NULL);
6305a203
L		 9766 free (name);
9767 }
9768 else
91d6fa6a 9769 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9770 cpu_arch_flags = flags;
a586129e 9771 cpu_arch_isa_flags = flags;
6305a203
L		 9772 }
9773 break;
ccc9c027 9774 }
9103f4f4 9775 }
6305a203 9776
91d6fa6a 9777 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9778 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9779
9780 arch = next;
9103f4f4 9781 }
6305a203 9782 while (next != NULL );
9103f4f4
L		 9783 break;
9784
9785 case OPTION_MTUNE:
9786 if (*arg == '.')
2b5d6a91 9787 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9788 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9789 {
91d6fa6a 9790 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9791 {
ccc9c027 9792 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9793 cpu_arch_tune = cpu_arch [j].type;
9794 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9795 break;
9796 }
9797 }
91d6fa6a 9798 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9799 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9800 break;
9801
1efbbeb4
L		 9802 case OPTION_MMNEMONIC:
9803 if (strcasecmp (arg, "att") == 0)
9804 intel_mnemonic = 0;
9805 else if (strcasecmp (arg, "intel") == 0)
9806 intel_mnemonic = 1;
9807 else
2b5d6a91 9808 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9809 break;
9810
9811 case OPTION_MSYNTAX:
9812 if (strcasecmp (arg, "att") == 0)
9813 intel_syntax = 0;
9814 else if (strcasecmp (arg, "intel") == 0)
9815 intel_syntax = 1;
9816 else
2b5d6a91 9817 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9818 break;
9819
9820 case OPTION_MINDEX_REG:
9821 allow_index_reg = 1;
9822 break;
9823
9824 case OPTION_MNAKED_REG:
9825 allow_naked_reg = 1;
9826 break;
9827
9828 case OPTION_MOLD_GCC:
9829 old_gcc = 1;
1efbbeb4
L		 9830 break;
9831
c0f3af97
L		 9832 case OPTION_MSSE2AVX:
9833 sse2avx = 1;
9834 break;
9835
daf50ae7
L		 9836 case OPTION_MSSE_CHECK:
9837 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9838 sse_check = check_error;
daf50ae7 9839 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9840 sse_check = check_warning;
daf50ae7 9841 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9842 sse_check = check_none;
daf50ae7 9843 else
2b5d6a91 9844 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9845 break;
9846
7bab8ab5
JB		 9847 case OPTION_MOPERAND_CHECK:
9848 if (strcasecmp (arg, "error") == 0)
9849 operand_check = check_error;
9850 else if (strcasecmp (arg, "warning") == 0)
9851 operand_check = check_warning;
9852 else if (strcasecmp (arg, "none") == 0)
9853 operand_check = check_none;
9854 else
9855 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9856 break;
9857
539f890d
L		 9858 case OPTION_MAVXSCALAR:
9859 if (strcasecmp (arg, "128") == 0)
9860 avxscalar = vex128;
9861 else if (strcasecmp (arg, "256") == 0)
9862 avxscalar = vex256;
9863 else
2b5d6a91 9864 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9865 break;
9866
7e8b059b
L		 9867 case OPTION_MADD_BND_PREFIX:
9868 add_bnd_prefix = 1;
9869 break;
9870
43234a1e
L		 9871 case OPTION_MEVEXLIG:
9872 if (strcmp (arg, "128") == 0)
9873 evexlig = evexl128;
9874 else if (strcmp (arg, "256") == 0)
9875 evexlig = evexl256;
9876 else if (strcmp (arg, "512") == 0)
9877 evexlig = evexl512;
9878 else
9879 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9880 break;
9881
d3d3c6db
IT		 9882 case OPTION_MEVEXRCIG:
9883 if (strcmp (arg, "rne") == 0)
9884 evexrcig = rne;
9885 else if (strcmp (arg, "rd") == 0)
9886 evexrcig = rd;
9887 else if (strcmp (arg, "ru") == 0)
9888 evexrcig = ru;
9889 else if (strcmp (arg, "rz") == 0)
9890 evexrcig = rz;
9891 else
9892 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
9893 break;
9894
43234a1e
L		 9895 case OPTION_MEVEXWIG:
9896 if (strcmp (arg, "0") == 0)
9897 evexwig = evexw0;
9898 else if (strcmp (arg, "1") == 0)
9899 evexwig = evexw1;
9900 else
9901 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9902 break;
9903
167ad85b
TG		 9904# if defined (TE_PE) || defined (TE_PEP)
9905 case OPTION_MBIG_OBJ:
9906 use_big_obj = 1;
9907 break;
9908#endif
9909
a5094208 9910 case OPTION_OMIT_LOCK_PREFIX:
d022bddd
IT		 9911 if (strcasecmp (arg, "yes") == 0)
9912 omit_lock_prefix = 1;
9913 else if (strcasecmp (arg, "no") == 0)
9914 omit_lock_prefix = 0;
9915 else
9916 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
9917 break;
9918
252b5132
RH		 9919 default:
9920 return 0;
9921 }
9922 return 1;
9923}
9924
8a2c8fef
L		 9925#define MESSAGE_TEMPLATE \
9926" "
9927
9928static void
1ded5609 9929show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9930{
9931 static char message[] = MESSAGE_TEMPLATE;
9932 char *start = message + 27;
9933 char *p;
9934 int size = sizeof (MESSAGE_TEMPLATE);
9935 int left;
9936 const char *name;
9937 int len;
9938 unsigned int j;
9939
9940 p = start;
9941 left = size - (start - message);
9942 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9943 {
9944 /* Should it be skipped? */
9945 if (cpu_arch [j].skip)
9946 continue;
9947
9948 name = cpu_arch [j].name;
9949 len = cpu_arch [j].len;
9950 if (*name == '.')
9951 {
9952 /* It is an extension. Skip if we aren't asked to show it. */
9953 if (ext)
9954 {
9955 name++;
9956 len--;
9957 }
9958 else
9959 continue;
9960 }
9961 else if (ext)
9962 {
9963 /* It is an processor. Skip if we show only extension. */
9964 continue;
9965 }
1ded5609
JB		 9966 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9967 {
9968 /* It is an impossible processor - skip. */
9969 continue;
9970 }
8a2c8fef
L		 9971
9972 /* Reserve 2 spaces for ", " or ",\0" */
9973 left -= len + 2;
9974
9975 /* Check if there is any room. */
9976 if (left >= 0)
9977 {
9978 if (p != start)
9979 {
9980 *p++ = ',';
9981 *p++ = ' ';
9982 }
9983 p = mempcpy (p, name, len);
9984 }
9985 else
9986 {
9987 /* Output the current message now and start a new one. */
9988 *p++ = ',';
9989 *p = '\0';
9990 fprintf (stream, "%s\n", message);
9991 p = start;
9992 left = size - (start - message) - len - 2;
8d63c93e 9993
8a2c8fef
L		 9994 gas_assert (left >= 0);
9995
9996 p = mempcpy (p, name, len);
9997 }
9998 }
9999
10000 *p = '\0';
10001 fprintf (stream, "%s\n", message);
10002}
10003
252b5132 10004void
8a2c8fef 10005md_show_usage (FILE *stream)
252b5132 10006{
4cc782b5
ILT		 10007#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10008 fprintf (stream, _("\
a38cf1db
AM		 10009 -Q ignored\n\
10010 -V print assembler version number\n\
b3b91714
AM		 10011 -k ignored\n"));
10012#endif
10013 fprintf (stream, _("\
12b55ccc 10014 -n Do not optimize code alignment\n\
b3b91714
AM		 10015 -q quieten some warnings\n"));
10016#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10017 fprintf (stream, _("\
a38cf1db 10018 -s ignored\n"));
b3b91714 10019#endif
321098a5
L		 10020#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10021 || defined (TE_PE) || defined (TE_PEP))
751d281c 10022 fprintf (stream, _("\
570561f7 10023 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10024#endif
b3b91714
AM		 10025#ifdef SVR4_COMMENT_CHARS
10026 fprintf (stream, _("\
10027 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10028#else
10029 fprintf (stream, _("\
b3b91714 10030 --divide ignored\n"));
4cc782b5 10031#endif
9103f4f4 10032 fprintf (stream, _("\
6305a203 10033 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10034 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10035 show_arch (stream, 0, 1);
8a2c8fef
L		 10036 fprintf (stream, _("\
10037 EXTENSION is combination of:\n"));
1ded5609 10038 show_arch (stream, 1, 0);
6305a203 10039 fprintf (stream, _("\
8a2c8fef 10040 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10041 show_arch (stream, 0, 0);
ba104c83 10042 fprintf (stream, _("\
c0f3af97
L		 10043 -msse2avx encode SSE instructions with VEX prefix\n"));
10044 fprintf (stream, _("\
daf50ae7
L		 10045 -msse-check=[none|error|warning]\n\
10046 check SSE instructions\n"));
10047 fprintf (stream, _("\
7bab8ab5
JB		 10048 -moperand-check=[none|error|warning]\n\
10049 check operand combinations for validity\n"));
10050 fprintf (stream, _("\
539f890d
L		 10051 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10052 length\n"));
10053 fprintf (stream, _("\
43234a1e
L		 10054 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10055 length\n"));
10056 fprintf (stream, _("\
10057 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10058 for EVEX.W bit ignored instructions\n"));
10059 fprintf (stream, _("\
d3d3c6db
IT		 10060 -mevexrcig=[rne|rd|ru|rz]\n\
10061 encode EVEX instructions with specific EVEX.RC value\n\
10062 for SAE-only ignored instructions\n"));
10063 fprintf (stream, _("\
ba104c83
L		 10064 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10065 fprintf (stream, _("\
10066 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10067 fprintf (stream, _("\
10068 -mindex-reg support pseudo index registers\n"));
10069 fprintf (stream, _("\
10070 -mnaked-reg don't require `%%' prefix for registers\n"));
10071 fprintf (stream, _("\
10072 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10073 fprintf (stream, _("\
10074 -madd-bnd-prefix add BND prefix for all valid branches\n"));
167ad85b
TG		 10075# if defined (TE_PE) || defined (TE_PEP)
10076 fprintf (stream, _("\
10077 -mbig-obj generate big object files\n"));
10078#endif
d022bddd
IT		 10079 fprintf (stream, _("\
10080 -momit-lock-prefix=[no|yes]\n\
10081 strip all lock prefixes\n"));
252b5132
RH		 10082}
10083
3e73aa7c 10084#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10085 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10086 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10087
10088/* Pick the target format to use. */
10089
47926f60 10090const char *
e3bb37b5 10091i386_target_format (void)
252b5132 10092{
351f65ca
L		 10093 if (!strncmp (default_arch, "x86_64", 6))
10094 {
10095 update_code_flag (CODE_64BIT, 1);
10096 if (default_arch[6] == '\0')
7f56bc95 10097 x86_elf_abi = X86_64_ABI;
351f65ca 10098 else
7f56bc95 10099 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10100 }
3e73aa7c 10101 else if (!strcmp (default_arch, "i386"))
78f12dd3 10102 update_code_flag (CODE_32BIT, 1);
3e73aa7c 10103 else
2b5d6a91 10104 as_fatal (_("unknown architecture"));
89507696
JB		 10105
10106 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10107 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10108 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10109 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10110
252b5132
RH		 10111 switch (OUTPUT_FLAVOR)
10112 {
9384f2ff 10113#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10114 case bfd_target_aout_flavour:
47926f60 10115 return AOUT_TARGET_FORMAT;
4c63da97 10116#endif
9384f2ff
AM		 10117#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10118# if defined (TE_PE) || defined (TE_PEP)
10119 case bfd_target_coff_flavour:
167ad85b
TG		 10120 if (flag_code == CODE_64BIT)
10121 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10122 else
10123 return "pe-i386";
9384f2ff 10124# elif defined (TE_GO32)
0561d57c
JK		 10125 case bfd_target_coff_flavour:
10126 return "coff-go32";
9384f2ff 10127# else
252b5132
RH		 10128 case bfd_target_coff_flavour:
10129 return "coff-i386";
9384f2ff 10130# endif
4c63da97 10131#endif
3e73aa7c 10132#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10133 case bfd_target_elf_flavour:
3e73aa7c 10134 {
351f65ca
L		 10135 const char *format;
10136
10137 switch (x86_elf_abi)
4fa24527 10138 {
351f65ca
L		 10139 default:
10140 format = ELF_TARGET_FORMAT;
10141 break;
7f56bc95 10142 case X86_64_ABI:
351f65ca 10143 use_rela_relocations = 1;
4fa24527 10144 object_64bit = 1;
351f65ca
L		 10145 format = ELF_TARGET_FORMAT64;
10146 break;
7f56bc95 10147 case X86_64_X32_ABI:
4fa24527 10148 use_rela_relocations = 1;
351f65ca 10149 object_64bit = 1;
862be3fb 10150 disallow_64bit_reloc = 1;
351f65ca
L		 10151 format = ELF_TARGET_FORMAT32;
10152 break;
4fa24527 10153 }
3632d14b 10154 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10155 {
7f56bc95 10156 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10157 as_fatal (_("Intel L1OM is 64bit only"));
10158 return ELF_TARGET_L1OM_FORMAT;
10159 }
7a9068fe
L		 10160 if (cpu_arch_isa == PROCESSOR_K1OM)
10161 {
10162 if (x86_elf_abi != X86_64_ABI)
10163 as_fatal (_("Intel K1OM is 64bit only"));
10164 return ELF_TARGET_K1OM_FORMAT;
10165 }
8a9036a4 10166 else
351f65ca 10167 return format;
3e73aa7c 10168 }
e57f8c65
TG		 10169#endif
10170#if defined (OBJ_MACH_O)
10171 case bfd_target_mach_o_flavour:
d382c579
TG		 10172 if (flag_code == CODE_64BIT)
10173 {
10174 use_rela_relocations = 1;
10175 object_64bit = 1;
10176 return "mach-o-x86-64";
10177 }
10178 else
10179 return "mach-o-i386";
4c63da97 10180#endif
252b5132
RH		 10181 default:
10182 abort ();
10183 return NULL;
10184 }
10185}
10186
47926f60 10187#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 10188
10189#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 10190void
10191i386_elf_emit_arch_note (void)
a847613f 10192{
718ddfc0 10193 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 10194 {
10195 char *p;
10196 asection *seg = now_seg;
10197 subsegT subseg = now_subseg;
10198 Elf_Internal_Note i_note;
10199 Elf_External_Note e_note;
10200 asection *note_secp;
10201 int len;
10202
10203 /* Create the .note section. */
10204 note_secp = subseg_new (".note", 0);
10205 bfd_set_section_flags (stdoutput,
10206 note_secp,
10207 SEC_HAS_CONTENTS | SEC_READONLY);
10208
10209 /* Process the arch string. */
10210 len = strlen (cpu_arch_name);
10211
10212 i_note.namesz = len + 1;
10213 i_note.descsz = 0;
10214 i_note.type = NT_ARCH;
10215 p = frag_more (sizeof (e_note.namesz));
10216 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
10217 p = frag_more (sizeof (e_note.descsz));
10218 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
10219 p = frag_more (sizeof (e_note.type));
10220 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
10221 p = frag_more (len + 1);
10222 strcpy (p, cpu_arch_name);
10223
10224 frag_align (2, 0, 0);
10225
10226 subseg_set (seg, subseg);
10227 }
10228}
10229#endif
252b5132 10230\f
252b5132 10231symbolS *
7016a5d5 10232md_undefined_symbol (char *name)
252b5132 10233{
18dc2407
ILT		 10234 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10235 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10236 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10237 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10238 {
10239 if (!GOT_symbol)
10240 {
10241 if (symbol_find (name))
10242 as_bad (_("GOT already in symbol table"));
10243 GOT_symbol = symbol_new (name, undefined_section,
10244 (valueT) 0, &zero_address_frag);
10245 };
10246 return GOT_symbol;
10247 }
252b5132
RH		 10248 return 0;
10249}
10250
10251/* Round up a section size to the appropriate boundary. */
47926f60 10252
252b5132 10253valueT
7016a5d5 10254md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10255{
4c63da97
AM		 10256#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10257 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10258 {
10259 /* For a.out, force the section size to be aligned. If we don't do
10260 this, BFD will align it for us, but it will not write out the
10261 final bytes of the section. This may be a bug in BFD, but it is
10262 easier to fix it here since that is how the other a.out targets
10263 work. */
10264 int align;
10265
10266 align = bfd_get_section_alignment (stdoutput, segment);
10267 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10268 }
252b5132
RH		 10269#endif
10270
10271 return size;
10272}
10273
10274/* On the i386, PC-relative offsets are relative to the start of the
10275 next instruction. That is, the address of the offset, plus its
10276 size, since the offset is always the last part of the insn. */
10277
10278long
e3bb37b5 10279md_pcrel_from (fixS *fixP)
252b5132
RH		 10280{
10281 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10282}
10283
10284#ifndef I386COFF
10285
10286static void
e3bb37b5 10287s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10288{
29b0f896 10289 int temp;
252b5132 10290
8a75718c
JB		 10291#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10292 if (IS_ELF)
10293 obj_elf_section_change_hook ();
10294#endif
252b5132
RH		 10295 temp = get_absolute_expression ();
10296 subseg_set (bss_section, (subsegT) temp);
10297 demand_empty_rest_of_line ();
10298}
10299
10300#endif
10301
252b5132 10302void
e3bb37b5 10303i386_validate_fix (fixS *fixp)
252b5132
RH		 10304{
10305 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10306 {
23df1078
JH		 10307 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10308 {
4fa24527 10309 if (!object_64bit)
23df1078
JH		 10310 abort ();
10311 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10312 }
10313 else
10314 {
4fa24527 10315 if (!object_64bit)
d6ab8113
JB		 10316 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10317 else
10318 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 10319 }
252b5132
RH		 10320 fixp->fx_subsy = 0;
10321 }
10322}
10323
252b5132 10324arelent *
7016a5d5 10325tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10326{
10327 arelent *rel;
10328 bfd_reloc_code_real_type code;
10329
10330 switch (fixp->fx_r_type)
10331 {
8ce3d284 10332#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10333 case BFD_RELOC_SIZE32:
10334 case BFD_RELOC_SIZE64:
10335 if (S_IS_DEFINED (fixp->fx_addsy)
10336 && !S_IS_EXTERNAL (fixp->fx_addsy))
10337 {
10338 /* Resolve size relocation against local symbol to size of
10339 the symbol plus addend. */
10340 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10341 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10342 && !fits_in_unsigned_long (value))
10343 as_bad_where (fixp->fx_file, fixp->fx_line,
10344 _("symbol size computation overflow"));
10345 fixp->fx_addsy = NULL;
10346 fixp->fx_subsy = NULL;
10347 md_apply_fix (fixp, (valueT *) &value, NULL);
10348 return NULL;
10349 }
8ce3d284 10350#endif
8fd4256d 10351
3e73aa7c 10352 case BFD_RELOC_X86_64_PLT32:
c3320543 10353 case BFD_RELOC_X86_64_PLT32_BND:
3e73aa7c
JH		 10354 case BFD_RELOC_X86_64_GOT32:
10355 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 10356 case BFD_RELOC_386_PLT32:
10357 case BFD_RELOC_386_GOT32:
10358 case BFD_RELOC_386_GOTOFF:
10359 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10360 case BFD_RELOC_386_TLS_GD:
10361 case BFD_RELOC_386_TLS_LDM:
10362 case BFD_RELOC_386_TLS_LDO_32:
10363 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10364 case BFD_RELOC_386_TLS_IE:
10365 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10366 case BFD_RELOC_386_TLS_LE_32:
10367 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10368 case BFD_RELOC_386_TLS_GOTDESC:
10369 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10370 case BFD_RELOC_X86_64_TLSGD:
10371 case BFD_RELOC_X86_64_TLSLD:
10372 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10373 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10374 case BFD_RELOC_X86_64_GOTTPOFF:
10375 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10376 case BFD_RELOC_X86_64_TPOFF64:
10377 case BFD_RELOC_X86_64_GOTOFF64:
10378 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10379 case BFD_RELOC_X86_64_GOT64:
10380 case BFD_RELOC_X86_64_GOTPCREL64:
10381 case BFD_RELOC_X86_64_GOTPC64:
10382 case BFD_RELOC_X86_64_GOTPLT64:
10383 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10384 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10385 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10386 case BFD_RELOC_RVA:
10387 case BFD_RELOC_VTABLE_ENTRY:
10388 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10389#ifdef TE_PE
10390 case BFD_RELOC_32_SECREL:
10391#endif
252b5132
RH		 10392 code = fixp->fx_r_type;
10393 break;
dbbaec26
L		 10394 case BFD_RELOC_X86_64_32S:
10395 if (!fixp->fx_pcrel)
10396 {
10397 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10398 code = fixp->fx_r_type;
10399 break;
10400 }
252b5132 10401 default:
93382f6d 10402 if (fixp->fx_pcrel)
252b5132 10403 {
93382f6d
AM		 10404 switch (fixp->fx_size)
10405 {
10406 default:
b091f402
AM		 10407 as_bad_where (fixp->fx_file, fixp->fx_line,
10408 _("can not do %d byte pc-relative relocation"),
10409 fixp->fx_size);
93382f6d
AM		 10410 code = BFD_RELOC_32_PCREL;
10411 break;
10412 case 1: code = BFD_RELOC_8_PCREL; break;
10413 case 2: code = BFD_RELOC_16_PCREL; break;
c3320543
L		 10414 case 4:
10415 code = (fixp->fx_r_type == BFD_RELOC_X86_64_PC32_BND
10416 ? fixp-> fx_r_type : BFD_RELOC_32_PCREL);
10417 break;
d6ab8113
JB		 10418#ifdef BFD64
10419 case 8: code = BFD_RELOC_64_PCREL; break;
10420#endif
93382f6d
AM		 10421 }
10422 }
10423 else
10424 {
10425 switch (fixp->fx_size)
10426 {
10427 default:
b091f402
AM		 10428 as_bad_where (fixp->fx_file, fixp->fx_line,
10429 _("can not do %d byte relocation"),
10430 fixp->fx_size);
93382f6d
AM		 10431 code = BFD_RELOC_32;
10432 break;
10433 case 1: code = BFD_RELOC_8; break;
10434 case 2: code = BFD_RELOC_16; break;
10435 case 4: code = BFD_RELOC_32; break;
937149dd 10436#ifdef BFD64
3e73aa7c 10437 case 8: code = BFD_RELOC_64; break;
937149dd 10438#endif
93382f6d 10439 }
252b5132
RH		 10440 }
10441 break;
10442 }
252b5132 10443
d182319b
JB		 10444 if ((code == BFD_RELOC_32
10445 || code == BFD_RELOC_32_PCREL
10446 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10447 && GOT_symbol
10448 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10449 {
4fa24527 10450 if (!object_64bit)
d6ab8113
JB		 10451 code = BFD_RELOC_386_GOTPC;
10452 else
10453 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10454 }
7b81dfbb
AJ		 10455 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10456 && GOT_symbol
10457 && fixp->fx_addsy == GOT_symbol)
10458 {
10459 code = BFD_RELOC_X86_64_GOTPC64;
10460 }
252b5132
RH		 10461
10462 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10463 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10464 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10465
10466 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10467
3e73aa7c
JH		 10468 if (!use_rela_relocations)
10469 {
10470 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10471 vtable entry to be used in the relocation's section offset. */
10472 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10473 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10474#if defined (OBJ_COFF) && defined (TE_PE)
10475 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10476 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10477 else
10478#endif
c6682705 10479 rel->addend = 0;
3e73aa7c
JH		 10480 }
10481 /* Use the rela in 64bit mode. */
252b5132 10482 else
3e73aa7c 10483 {
862be3fb
L		 10484 if (disallow_64bit_reloc)
10485 switch (code)
10486 {
862be3fb
L		 10487 case BFD_RELOC_X86_64_DTPOFF64:
10488 case BFD_RELOC_X86_64_TPOFF64:
10489 case BFD_RELOC_64_PCREL:
10490 case BFD_RELOC_X86_64_GOTOFF64:
10491 case BFD_RELOC_X86_64_GOT64:
10492 case BFD_RELOC_X86_64_GOTPCREL64:
10493 case BFD_RELOC_X86_64_GOTPC64:
10494 case BFD_RELOC_X86_64_GOTPLT64:
10495 case BFD_RELOC_X86_64_PLTOFF64:
10496 as_bad_where (fixp->fx_file, fixp->fx_line,
10497 _("cannot represent relocation type %s in x32 mode"),
10498 bfd_get_reloc_code_name (code));
10499 break;
10500 default:
10501 break;
10502 }
10503
062cd5e7
AS		 10504 if (!fixp->fx_pcrel)
10505 rel->addend = fixp->fx_offset;
10506 else
10507 switch (code)
10508 {
10509 case BFD_RELOC_X86_64_PLT32:
c3320543 10510 case BFD_RELOC_X86_64_PLT32_BND:
062cd5e7
AS		 10511 case BFD_RELOC_X86_64_GOT32:
10512 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 10513 case BFD_RELOC_X86_64_TLSGD:
10514 case BFD_RELOC_X86_64_TLSLD:
10515 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10516 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10517 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10518 rel->addend = fixp->fx_offset - fixp->fx_size;
10519 break;
10520 default:
10521 rel->addend = (section->vma
10522 - fixp->fx_size
10523 + fixp->fx_addnumber
10524 + md_pcrel_from (fixp));
10525 break;
10526 }
3e73aa7c
JH		 10527 }
10528
252b5132
RH		 10529 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10530 if (rel->howto == NULL)
10531 {
10532 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10533 _("cannot represent relocation type %s"),
252b5132
RH		 10534 bfd_get_reloc_code_name (code));
10535 /* Set howto to a garbage value so that we can keep going. */
10536 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10537 gas_assert (rel->howto != NULL);
252b5132
RH		 10538 }
10539
10540 return rel;
10541}
10542
ee86248c 10543#include "tc-i386-intel.c"
54cfded0 10544
a60de03c
JB		 10545void
10546tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10547{
a60de03c
JB		 10548 int saved_naked_reg;
10549 char saved_register_dot;
54cfded0 10550
a60de03c
JB		 10551 saved_naked_reg = allow_naked_reg;
10552 allow_naked_reg = 1;
10553 saved_register_dot = register_chars['.'];
10554 register_chars['.'] = '.';
10555 allow_pseudo_reg = 1;
10556 expression_and_evaluate (exp);
10557 allow_pseudo_reg = 0;
10558 register_chars['.'] = saved_register_dot;
10559 allow_naked_reg = saved_naked_reg;
10560
e96d56a1 10561 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10562 {
a60de03c
JB		 10563 if ((addressT) exp->X_add_number < i386_regtab_size)
10564 {
10565 exp->X_op = O_constant;
10566 exp->X_add_number = i386_regtab[exp->X_add_number]
10567 .dw2_regnum[flag_code >> 1];
10568 }
10569 else
10570 exp->X_op = O_illegal;
54cfded0 10571 }
54cfded0
AM		 10572}
10573
10574void
10575tc_x86_frame_initial_instructions (void)
10576{
a60de03c
JB		 10577 static unsigned int sp_regno[2];
10578
10579 if (!sp_regno[flag_code >> 1])
10580 {
10581 char *saved_input = input_line_pointer;
10582 char sp[][4] = {"esp", "rsp"};
10583 expressionS exp;
a4447b93 10584
a60de03c
JB		 10585 input_line_pointer = sp[flag_code >> 1];
10586 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10587 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10588 sp_regno[flag_code >> 1] = exp.X_add_number;
10589 input_line_pointer = saved_input;
10590 }
a4447b93 10591
61ff971f
L		 10592 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10593 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10594}
d2b2c203 10595
d7921315
L		 10596int
10597x86_dwarf2_addr_size (void)
10598{
10599#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10600 if (x86_elf_abi == X86_64_X32_ABI)
10601 return 4;
10602#endif
10603 return bfd_arch_bits_per_address (stdoutput) / 8;
10604}
10605
d2b2c203
DJ		 10606int
10607i386_elf_section_type (const char *str, size_t len)
10608{
10609 if (flag_code == CODE_64BIT
10610 && len == sizeof ("unwind") - 1
10611 && strncmp (str, "unwind", 6) == 0)
10612 return SHT_X86_64_UNWIND;
10613
10614 return -1;
10615}
bb41ade5 10616
ad5fec3b
EB		 10617#ifdef TE_SOLARIS
10618void
10619i386_solaris_fix_up_eh_frame (segT sec)
10620{
10621 if (flag_code == CODE_64BIT)
10622 elf_section_type (sec) = SHT_X86_64_UNWIND;
10623}
10624#endif
10625
bb41ade5
AM		 10626#ifdef TE_PE
10627void
10628tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10629{
91d6fa6a 10630 expressionS exp;
bb41ade5 10631
91d6fa6a
NC		 10632 exp.X_op = O_secrel;
10633 exp.X_add_symbol = symbol;
10634 exp.X_add_number = 0;
10635 emit_expr (&exp, size);
bb41ade5
AM		 10636}
10637#endif
3b22753a
L		 10638
10639#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10640/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10641
01e1a5bc 10642bfd_vma
3b22753a
L		 10643x86_64_section_letter (int letter, char **ptr_msg)
10644{
10645 if (flag_code == CODE_64BIT)
10646 {
10647 if (letter == 'l')
10648 return SHF_X86_64_LARGE;
10649
8f3bae45 10650 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10651 }
3b22753a 10652 else
8f3bae45 10653 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10654 return -1;
10655}
10656
01e1a5bc 10657bfd_vma
3b22753a
L		 10658x86_64_section_word (char *str, size_t len)
10659{
8620418b 10660 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10661 return SHF_X86_64_LARGE;
10662
10663 return -1;
10664}
10665
10666static void
10667handle_large_common (int small ATTRIBUTE_UNUSED)
10668{
10669 if (flag_code != CODE_64BIT)
10670 {
10671 s_comm_internal (0, elf_common_parse);
10672 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10673 }
10674 else
10675 {
10676 static segT lbss_section;
10677 asection *saved_com_section_ptr = elf_com_section_ptr;
10678 asection *saved_bss_section = bss_section;
10679
10680 if (lbss_section == NULL)
10681 {
10682 flagword applicable;
10683 segT seg = now_seg;
10684 subsegT subseg = now_subseg;
10685
10686 /* The .lbss section is for local .largecomm symbols. */
10687 lbss_section = subseg_new (".lbss", 0);
10688 applicable = bfd_applicable_section_flags (stdoutput);
10689 bfd_set_section_flags (stdoutput, lbss_section,
10690 applicable & SEC_ALLOC);
10691 seg_info (lbss_section)->bss = 1;
10692
10693 subseg_set (seg, subseg);
10694 }
10695
10696 elf_com_section_ptr = &_bfd_elf_large_com_section;
10697 bss_section = lbss_section;
10698
10699 s_comm_internal (0, elf_common_parse);
10700
10701 elf_com_section_ptr = saved_com_section_ptr;
10702 bss_section = saved_bss_section;
10703 }
10704}
10705#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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