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gdb.base/sigstep.exp: xfail gdb/17511 on i?86 Linux
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
4b95cf5c 2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
22109423 136 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 137}
138arch_entry;
139
78f12dd3 140static void update_code_flag (int, int);
e3bb37b5
L		 141static void set_code_flag (int);
142static void set_16bit_gcc_code_flag (int);
143static void set_intel_syntax (int);
1efbbeb4 144static void set_intel_mnemonic (int);
db51cc60 145static void set_allow_index_reg (int);
7bab8ab5 146static void set_check (int);
e3bb37b5 147static void set_cpu_arch (int);
6482c264 148#ifdef TE_PE
e3bb37b5 149static void pe_directive_secrel (int);
6482c264 150#endif
e3bb37b5
L		 151static void signed_cons (int);
152static char *output_invalid (int c);
ee86248c
JB		 153static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
154 const char *);
155static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
156 const char *);
a7619375 157static int i386_att_operand (char *);
e3bb37b5 158static int i386_intel_operand (char *, int);
ee86248c
JB		 159static int i386_intel_simplify (expressionS *);
160static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 161static const reg_entry *parse_register (char *, char **);
162static char *parse_insn (char *, char *);
163static char *parse_operands (char *, const char *);
164static void swap_operands (void);
4d456e3d 165static void swap_2_operands (int, int);
e3bb37b5
L		 166static void optimize_imm (void);
167static void optimize_disp (void);
d3ce72d0 168static const insn_template *match_template (void);
e3bb37b5
L		 169static int check_string (void);
170static int process_suffix (void);
171static int check_byte_reg (void);
172static int check_long_reg (void);
173static int check_qword_reg (void);
174static int check_word_reg (void);
175static int finalize_imm (void);
176static int process_operands (void);
177static const seg_entry *build_modrm_byte (void);
178static void output_insn (void);
179static void output_imm (fragS *, offsetT);
180static void output_disp (fragS *, offsetT);
29b0f896 181#ifndef I386COFF
e3bb37b5 182static void s_bss (int);
252b5132 183#endif
17d4e2a2
L		 184#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185static void handle_large_common (int small ATTRIBUTE_UNUSED);
186#endif
252b5132 187
a847613f 188static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 189
43234a1e
L		 190/* This struct describes rounding control and SAE in the instruction. */
191struct RC_Operation
192{
193 enum rc_type
194 {
195 rne = 0,
196 rd,
197 ru,
198 rz,
199 saeonly
200 } type;
201 int operand;
202};
203
204static struct RC_Operation rc_op;
205
206/* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209struct Mask_Operation
210{
211 const reg_entry *mask;
212 unsigned int zeroing;
213 /* The operand where this operation is associated. */
214 int operand;
215};
216
217static struct Mask_Operation mask_op;
218
219/* The struct describes broadcasting, applied to OPERAND. FACTOR is
220 broadcast factor. */
221struct Broadcast_Operation
222{
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
224 int type;
225
226 /* Index of broadcasted operand. */
227 int operand;
228};
229
230static struct Broadcast_Operation broadcast_op;
231
c0f3af97
L		 232/* VEX prefix. */
233typedef struct
234{
43234a1e
L		 235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes[4];
c0f3af97
L		 237 unsigned int length;
238 /* Destination or source register specifier. */
239 const reg_entry *register_specifier;
240} vex_prefix;
241
252b5132 242/* 'md_assemble ()' gathers together information and puts it into a
47926f60 243 i386_insn. */
252b5132 244
520dc8e8
AM		 245union i386_op
246 {
247 expressionS *disps;
248 expressionS *imms;
249 const reg_entry *regs;
250 };
251
a65babc9
L		 252enum i386_error
253 {
86e026a4 254 operand_size_mismatch,
a65babc9
L		 255 operand_type_mismatch,
256 register_type_mismatch,
257 number_of_operands_mismatch,
258 invalid_instruction_suffix,
259 bad_imm4,
260 old_gcc_only,
261 unsupported_with_intel_mnemonic,
262 unsupported_syntax,
6c30d220
L		 263 unsupported,
264 invalid_vsib_address,
7bab8ab5 265 invalid_vector_register_set,
43234a1e
L		 266 unsupported_vector_index_register,
267 unsupported_broadcast,
268 broadcast_not_on_src_operand,
269 broadcast_needed,
270 unsupported_masking,
271 mask_not_on_destination,
272 no_default_mask,
273 unsupported_rc_sae,
274 rc_sae_operand_not_last_imm,
275 invalid_register_operand,
276 try_vector_disp8
a65babc9
L		 277 };
278
252b5132
RH		 279struct _i386_insn
280 {
47926f60 281 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 282 insn_template tm;
252b5132 283
7d5e4556
L		 284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
252b5132
RH		 286 char suffix;
287
47926f60 288 /* OPERANDS gives the number of given operands. */
252b5132
RH		 289 unsigned int operands;
290
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
47926f60 293 operands. */
252b5132
RH		 294 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
295
296 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 297 use OP[i] for the corresponding operand. */
40fb9820 298 i386_operand_type types[MAX_OPERANDS];
252b5132 299
520dc8e8
AM		 300 /* Displacement expression, immediate expression, or register for each
301 operand. */
302 union i386_op op[MAX_OPERANDS];
252b5132 303
3e73aa7c
JH		 304 /* Flags for operands. */
305 unsigned int flags[MAX_OPERANDS];
306#define Operand_PCrel 1
307
252b5132 308 /* Relocation type for operand */
f86103b7 309 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 310
252b5132
RH		 311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry *base_reg;
314 const reg_entry *index_reg;
315 unsigned int log2_scale_factor;
316
317 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 318 explicit segment overrides are given. */
ce8a8b2f 319 const seg_entry *seg[2];
252b5132
RH		 320
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes;
324 unsigned char prefix[MAX_PREFIXES];
325
326 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 327 addressing modes of this insn are encoded. */
252b5132 328 modrm_byte rm;
3e73aa7c 329 rex_byte rex;
43234a1e 330 rex_byte vrex;
252b5132 331 sib_byte sib;
c0f3af97 332 vex_prefix vex;
b6169b20 333
43234a1e
L		 334 /* Masking attributes. */
335 struct Mask_Operation *mask;
336
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation *rounding;
339
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation *broadcast;
342
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift;
345
b6169b20 346 /* Swap operand in encoding. */
4473e004 347 unsigned int swap_operand;
891edac4 348
a501d77e
L		 349 /* Prefer 8bit or 32bit displacement in encoding. */
350 enum
351 {
352 disp_encoding_default = 0,
353 disp_encoding_8bit,
354 disp_encoding_32bit
355 } disp_encoding;
f8a5c266 356
d5de92cf
L		 357 /* REP prefix. */
358 const char *rep_prefix;
359
165de32a
L		 360 /* HLE prefix. */
361 const char *hle_prefix;
42164a71 362
7e8b059b
L		 363 /* Have BND prefix. */
364 const char *bnd_prefix;
365
43234a1e
L		 366 /* Need VREX to support upper 16 registers. */
367 int need_vrex;
368
891edac4 369 /* Error message. */
a65babc9 370 enum i386_error error;
252b5132
RH		 371 };
372
373typedef struct _i386_insn i386_insn;
374
43234a1e
L		 375/* Link RC type with corresponding string, that'll be looked for in
376 asm. */
377struct RC_name
378{
379 enum rc_type type;
380 const char *name;
381 unsigned int len;
382};
383
384static const struct RC_name RC_NamesTable[] =
385{
386 { rne, STRING_COMMA_LEN ("rn-sae") },
387 { rd, STRING_COMMA_LEN ("rd-sae") },
388 { ru, STRING_COMMA_LEN ("ru-sae") },
389 { rz, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly, STRING_COMMA_LEN ("sae") },
391};
392
252b5132
RH		 393/* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 395const char extra_symbol_chars[] = "*%-([{"
252b5132 396#ifdef LEX_AT
32137342
NC		 397 "@"
398#endif
399#ifdef LEX_QM
400 "?"
252b5132 401#endif
32137342 402 ;
252b5132 403
29b0f896
AM		 404#if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 406 && !defined (TE_GNU) \
29b0f896 407 && !defined (TE_LINUX) \
8d63c93e
RM		 408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
29b0f896 410 && !defined (TE_FreeBSD) \
5b806d27 411 && !defined (TE_DragonFly) \
29b0f896 412 && !defined (TE_NetBSD)))
252b5132 413/* This array holds the chars that always start a comment. If the
b3b91714
AM		 414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416const char *i386_comment_chars = "#/";
417#define SVR4_COMMENT_CHARS 1
252b5132 418#define PREFIX_SEPARATOR '\\'
252b5132 419
b3b91714
AM		 420#else
421const char *i386_comment_chars = "#";
422#define PREFIX_SEPARATOR '/'
423#endif
424
252b5132
RH		 425/* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 429 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
252b5132 432 '/' isn't otherwise defined. */
b3b91714 433const char line_comment_chars[] = "#/";
252b5132 434
63a0b638 435const char line_separator_chars[] = ";";
252b5132 436
ce8a8b2f
AM		 437/* Chars that can be used to separate mant from exp in floating point
438 nums. */
252b5132
RH		 439const char EXP_CHARS[] = "eE";
440
ce8a8b2f
AM		 441/* Chars that mean this number is a floating point constant
442 As in 0f12.456
443 or 0d1.2345e12. */
252b5132
RH		 444const char FLT_CHARS[] = "fFdDxX";
445
ce8a8b2f 446/* Tables for lexical analysis. */
252b5132
RH		 447static char mnemonic_chars[256];
448static char register_chars[256];
449static char operand_chars[256];
450static char identifier_chars[256];
451static char digit_chars[256];
452
ce8a8b2f 453/* Lexical macros. */
252b5132
RH		 454#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455#define is_operand_char(x) (operand_chars[(unsigned char) x])
456#define is_register_char(x) (register_chars[(unsigned char) x])
457#define is_space_char(x) ((x) == ' ')
458#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459#define is_digit_char(x) (digit_chars[(unsigned char) x])
460
0234cb7c 461/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 462static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
463
464/* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
47926f60 467 assembler instruction). */
252b5132 468static char save_stack[32];
ce8a8b2f 469static char *save_stack_p;
252b5132
RH		 470#define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472#define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
474
47926f60 475/* The instruction we're assembling. */
252b5132
RH		 476static i386_insn i;
477
478/* Possible templates for current insn. */
479static const templates *current_templates;
480
31b2323c
L		 481/* Per instruction expressionS buffers: max displacements & immediates. */
482static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
483static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 484
47926f60 485/* Current operand we are working on. */
ee86248c 486static int this_operand = -1;
252b5132 487
3e73aa7c
JH		 488/* We support four different modes. FLAG_CODE variable is used to distinguish
489 these. */
490
491enum flag_code {
492 CODE_32BIT,
493 CODE_16BIT,
494 CODE_64BIT };
495
496static enum flag_code flag_code;
4fa24527 497static unsigned int object_64bit;
862be3fb 498static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 499static int use_rela_relocations = 0;
500
7af8ed2d
NC		 501#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
504
351f65ca
L		 505/* The ELF ABI to use. */
506enum x86_elf_abi
507{
508 I386_ABI,
7f56bc95
L		 509 X86_64_ABI,
510 X86_64_X32_ABI
351f65ca
L		 511};
512
513static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 514#endif
351f65ca 515
167ad85b
TG		 516#if defined (TE_PE) || defined (TE_PEP)
517/* Use big object file format. */
518static int use_big_obj = 0;
519#endif
520
47926f60
KH		 521/* 1 for intel syntax,
522 0 if att syntax. */
523static int intel_syntax = 0;
252b5132 524
1efbbeb4
L		 525/* 1 for intel mnemonic,
526 0 if att mnemonic. */
527static int intel_mnemonic = !SYSV386_COMPAT;
528
5209009a 529/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 530static int old_gcc = OLDGCC_COMPAT;
531
a60de03c
JB		 532/* 1 if pseudo registers are permitted. */
533static int allow_pseudo_reg = 0;
534
47926f60
KH		 535/* 1 if register prefix % not required. */
536static int allow_naked_reg = 0;
252b5132 537
7e8b059b
L		 538/* 1 if the assembler should add BND prefix for all control-tranferring
539 instructions supporting it, even if this prefix wasn't specified
540 explicitly. */
541static int add_bnd_prefix = 0;
542
ba104c83 543/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 544static int allow_index_reg = 0;
545
d022bddd
IT		 546/* 1 if the assembler should ignore LOCK prefix, even if it was
547 specified explicitly. */
548static int omit_lock_prefix = 0;
549
7bab8ab5 550static enum check_kind
daf50ae7 551 {
7bab8ab5
JB		 552 check_none = 0,
553 check_warning,
554 check_error
daf50ae7 555 }
7bab8ab5 556sse_check, operand_check = check_warning;
daf50ae7 557
2ca3ace5
L		 558/* Register prefix used for error message. */
559static const char *register_prefix = "%";
560
47926f60
KH		 561/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
562 leave, push, and pop instructions so that gcc has the same stack
563 frame as in 32 bit mode. */
564static char stackop_size = '\0';
eecb386c 565
12b55ccc
L		 566/* Non-zero to optimize code alignment. */
567int optimize_align_code = 1;
568
47926f60
KH		 569/* Non-zero to quieten some warnings. */
570static int quiet_warnings = 0;
a38cf1db 571
47926f60
KH		 572/* CPU name. */
573static const char *cpu_arch_name = NULL;
6305a203 574static char *cpu_sub_arch_name = NULL;
a38cf1db 575
47926f60 576/* CPU feature flags. */
40fb9820
L		 577static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
578
ccc9c027
L		 579/* If we have selected a cpu we are generating instructions for. */
580static int cpu_arch_tune_set = 0;
581
9103f4f4 582/* Cpu we are generating instructions for. */
fbf3f584 583enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 584
585/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 586static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 587
ccc9c027 588/* CPU instruction set architecture used. */
fbf3f584 589enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 590
9103f4f4 591/* CPU feature flags of instruction set architecture used. */
fbf3f584 592i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 593
fddf5b5b
AM		 594/* If set, conditional jumps are not automatically promoted to handle
595 larger than a byte offset. */
596static unsigned int no_cond_jump_promotion = 0;
597
c0f3af97
L		 598/* Encode SSE instructions with VEX prefix. */
599static unsigned int sse2avx;
600
539f890d
L		 601/* Encode scalar AVX instructions with specific vector length. */
602static enum
603 {
604 vex128 = 0,
605 vex256
606 } avxscalar;
607
43234a1e
L		 608/* Encode scalar EVEX LIG instructions with specific vector length. */
609static enum
610 {
611 evexl128 = 0,
612 evexl256,
613 evexl512
614 } evexlig;
615
616/* Encode EVEX WIG instructions with specific evex.w. */
617static enum
618 {
619 evexw0 = 0,
620 evexw1
621 } evexwig;
622
d3d3c6db
IT		 623/* Value to encode in EVEX RC bits, for SAE-only instructions. */
624static enum rc_type evexrcig = rne;
625
29b0f896 626/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 627static symbolS *GOT_symbol;
29b0f896 628
a4447b93
RH		 629/* The dwarf2 return column, adjusted for 32 or 64 bit. */
630unsigned int x86_dwarf2_return_column;
631
632/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
633int x86_cie_data_alignment;
634
252b5132 635/* Interface to relax_segment.
fddf5b5b
AM		 636 There are 3 major relax states for 386 jump insns because the
637 different types of jumps add different sizes to frags when we're
638 figuring out what sort of jump to choose to reach a given label. */
252b5132 639
47926f60 640/* Types. */
93c2a809
AM		 641#define UNCOND_JUMP 0
642#define COND_JUMP 1
643#define COND_JUMP86 2
fddf5b5b 644
47926f60 645/* Sizes. */
252b5132
RH		 646#define CODE16 1
647#define SMALL 0
29b0f896 648#define SMALL16 (SMALL | CODE16)
252b5132 649#define BIG 2
29b0f896 650#define BIG16 (BIG | CODE16)
252b5132
RH		 651
652#ifndef INLINE
653#ifdef __GNUC__
654#define INLINE __inline__
655#else
656#define INLINE
657#endif
658#endif
659
fddf5b5b
AM		 660#define ENCODE_RELAX_STATE(type, size) \
661 ((relax_substateT) (((type) << 2) | (size)))
662#define TYPE_FROM_RELAX_STATE(s) \
663 ((s) >> 2)
664#define DISP_SIZE_FROM_RELAX_STATE(s) \
665 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 666
667/* This table is used by relax_frag to promote short jumps to long
668 ones where necessary. SMALL (short) jumps may be promoted to BIG
669 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
670 don't allow a short jump in a 32 bit code segment to be promoted to
671 a 16 bit offset jump because it's slower (requires data size
672 prefix), and doesn't work, unless the destination is in the bottom
673 64k of the code segment (The top 16 bits of eip are zeroed). */
674
675const relax_typeS md_relax_table[] =
676{
24eab124
AM		 677 /* The fields are:
678 1) most positive reach of this state,
679 2) most negative reach of this state,
93c2a809 680 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 681 4) which index into the table to try if we can't fit into this one. */
252b5132 682
fddf5b5b 683 /* UNCOND_JUMP states. */
93c2a809
AM		 684 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
685 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
686 /* dword jmp adds 4 bytes to frag:
687 0 extra opcode bytes, 4 displacement bytes. */
252b5132 688 {0, 0, 4, 0},
93c2a809
AM		 689 /* word jmp adds 2 byte2 to frag:
690 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 691 {0, 0, 2, 0},
692
93c2a809
AM		 693 /* COND_JUMP states. */
694 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
696 /* dword conditionals adds 5 bytes to frag:
697 1 extra opcode byte, 4 displacement bytes. */
698 {0, 0, 5, 0},
fddf5b5b 699 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 700 1 extra opcode byte, 2 displacement bytes. */
701 {0, 0, 3, 0},
702
703 /* COND_JUMP86 states. */
704 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
705 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
706 /* dword conditionals adds 5 bytes to frag:
707 1 extra opcode byte, 4 displacement bytes. */
708 {0, 0, 5, 0},
709 /* word conditionals add 4 bytes to frag:
710 1 displacement byte and a 3 byte long branch insn. */
711 {0, 0, 4, 0}
252b5132
RH		 712};
713
9103f4f4
L		 714static const arch_entry cpu_arch[] =
715{
89507696
JB		 716 /* Do not replace the first two entries - i386_target_format()
717 relies on them being there in this order. */
8a2c8fef 718 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 719 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 720 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 721 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 722 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 723 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 724 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 725 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 726 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 727 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 728 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 729 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 730 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 731 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 732 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 733 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 734 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 735 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 736 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 737 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 738 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 739 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 740 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 741 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 742 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 743 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 744 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 745 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 746 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 747 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 748 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 749 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 750 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 751 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 752 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 753 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 754 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 755 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 756 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 757 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 758 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 759 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 760 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 761 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 762 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
763 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 764 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 765 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 766 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 767 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 768 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 769 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 770 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 771 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 772 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 773 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 774 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 775 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 776 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 777 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 778 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 779 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 780 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 781 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 782 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
783 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 784 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
785 CPU_BDVER4_FLAGS, 0, 0 },
7b458c12
L		 786 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
787 CPU_BTVER1_FLAGS, 0, 0 },
788 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
789 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 790 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 791 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 792 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 793 CPU_287_FLAGS, 0, 0 },
8a2c8fef 794 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 795 CPU_387_FLAGS, 0, 0 },
8a2c8fef 796 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 797 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 798 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 799 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 800 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 801 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 802 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 803 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 804 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 805 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 806 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 807 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 808 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 809 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 810 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 811 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 812 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 813 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 814 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 815 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 816 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 817 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 818 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 819 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 820 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
821 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 822 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
823 CPU_AVX512F_FLAGS, 0, 0 },
824 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
825 CPU_AVX512CD_FLAGS, 0, 0 },
826 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
827 CPU_AVX512ER_FLAGS, 0, 0 },
828 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
829 CPU_AVX512PF_FLAGS, 0, 0 },
8a2c8fef 830 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 831 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 832 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 833 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 834 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
835 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 836 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 837 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 838 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 839 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 840 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 841 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 842 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 843 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 844 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 845 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 846 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 847 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 848 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 849 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 850 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 851 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 852 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 853 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 854 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
855 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 856 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 857 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 858 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 859 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 860 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 861 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 862 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 863 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 864 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 865 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 866 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
867 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 868 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 869 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 870 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
871 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 872 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
873 CPU_HLE_FLAGS, 0, 0 },
874 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
875 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 876 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
877 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 878 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 879 CPU_CLFLUSH_FLAGS, 0, 0 },
880 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
881 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 882 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 883 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 884 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 885 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 886 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 887 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 888 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 889 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 890 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 891 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 892 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 893 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 894 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 895 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 896 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 897 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 898 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 899 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 900 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
901 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 902 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
903 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 904 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
905 CPU_ADX_FLAGS, 0, 0 },
906 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
907 CPU_RDSEED_FLAGS, 0, 0 },
908 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
909 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 910 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
911 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 912 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
913 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 914 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
915 CPU_SHA_FLAGS, 0, 0 },
963f3586
IT		 916 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
917 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
918 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
919 CPU_XSAVEC_FLAGS, 0, 0 },
920 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
921 CPU_XSAVES_FLAGS, 0, 0 },
dcf893b5
IT		 922 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
923 CPU_PREFETCHWT1_FLAGS, 0, 0 },
2cf200a4
IT		 924 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
925 CPU_SE1_FLAGS, 0, 0 },
90a915bf
IT		 926 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
927 CPU_AVX512DQ_FLAGS, 0, 0 },
1ba585e8
IT		 928 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
929 CPU_AVX512BW_FLAGS, 0, 0 },
b28d1bda
IT		 930 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
931 CPU_AVX512VL_FLAGS, 0, 0 },
e413e4e9
AM		 932};
933
704209c0 934#ifdef I386COFF
a6c24e68
NC		 935/* Like s_lcomm_internal in gas/read.c but the alignment string
936 is allowed to be optional. */
937
938static symbolS *
939pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
940{
941 addressT align = 0;
942
943 SKIP_WHITESPACE ();
944
7ab9ffdd 945 if (needs_align
a6c24e68
NC		 946 && *input_line_pointer == ',')
947 {
948 align = parse_align (needs_align - 1);
7ab9ffdd 949
a6c24e68
NC		 950 if (align == (addressT) -1)
951 return NULL;
952 }
953 else
954 {
955 if (size >= 8)
956 align = 3;
957 else if (size >= 4)
958 align = 2;
959 else if (size >= 2)
960 align = 1;
961 else
962 align = 0;
963 }
964
965 bss_alloc (symbolP, size, align);
966 return symbolP;
967}
968
704209c0 969static void
a6c24e68
NC		 970pe_lcomm (int needs_align)
971{
972 s_comm_internal (needs_align * 2, pe_lcomm_internal);
973}
704209c0 974#endif
a6c24e68 975
29b0f896
AM		 976const pseudo_typeS md_pseudo_table[] =
977{
978#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
979 {"align", s_align_bytes, 0},
980#else
981 {"align", s_align_ptwo, 0},
982#endif
983 {"arch", set_cpu_arch, 0},
984#ifndef I386COFF
985 {"bss", s_bss, 0},
a6c24e68
NC		 986#else
987 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 988#endif
989 {"ffloat", float_cons, 'f'},
990 {"dfloat", float_cons, 'd'},
991 {"tfloat", float_cons, 'x'},
992 {"value", cons, 2},
d182319b 993 {"slong", signed_cons, 4},
29b0f896
AM		 994 {"noopt", s_ignore, 0},
995 {"optim", s_ignore, 0},
996 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
997 {"code16", set_code_flag, CODE_16BIT},
998 {"code32", set_code_flag, CODE_32BIT},
999 {"code64", set_code_flag, CODE_64BIT},
1000 {"intel_syntax", set_intel_syntax, 1},
1001 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1002 {"intel_mnemonic", set_intel_mnemonic, 1},
1003 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1004 {"allow_index_reg", set_allow_index_reg, 1},
1005 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1006 {"sse_check", set_check, 0},
1007 {"operand_check", set_check, 1},
3b22753a
L		 1008#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1009 {"largecomm", handle_large_common, 0},
07a53e5c 1010#else
e3bb37b5 1011 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1012 {"loc", dwarf2_directive_loc, 0},
1013 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1014#endif
6482c264
NC		 1015#ifdef TE_PE
1016 {"secrel32", pe_directive_secrel, 0},
1017#endif
29b0f896
AM		 1018 {0, 0, 0}
1019};
1020
1021/* For interface with expression (). */
1022extern char *input_line_pointer;
1023
1024/* Hash table for instruction mnemonic lookup. */
1025static struct hash_control *op_hash;
1026
1027/* Hash table for register lookup. */
1028static struct hash_control *reg_hash;
1029\f
252b5132 1030void
e3bb37b5 1031i386_align_code (fragS *fragP, int count)
252b5132 1032{
ce8a8b2f
AM		 1033 /* Various efficient no-op patterns for aligning code labels.
1034 Note: Don't try to assemble the instructions in the comments.
1035 0L and 0w are not legal. */
252b5132
RH		 1036 static const char f32_1[] =
1037 {0x90}; /* nop */
1038 static const char f32_2[] =
ccc9c027 1039 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1040 static const char f32_3[] =
1041 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1042 static const char f32_4[] =
1043 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1044 static const char f32_5[] =
1045 {0x90, /* nop */
1046 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1047 static const char f32_6[] =
1048 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1049 static const char f32_7[] =
1050 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1051 static const char f32_8[] =
1052 {0x90, /* nop */
1053 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1054 static const char f32_9[] =
1055 {0x89,0xf6, /* movl %esi,%esi */
1056 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1057 static const char f32_10[] =
1058 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1059 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1060 static const char f32_11[] =
1061 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1062 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1063 static const char f32_12[] =
1064 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1065 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1066 static const char f32_13[] =
1067 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1068 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1069 static const char f32_14[] =
1070 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1071 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1072 static const char f16_3[] =
1073 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1074 static const char f16_4[] =
1075 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1076 static const char f16_5[] =
1077 {0x90, /* nop */
1078 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1079 static const char f16_6[] =
1080 {0x89,0xf6, /* mov %si,%si */
1081 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1082 static const char f16_7[] =
1083 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1084 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1085 static const char f16_8[] =
1086 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1087 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1088 static const char jump_31[] =
1089 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1090 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1091 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1092 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1093 static const char *const f32_patt[] = {
1094 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1095 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1096 };
1097 static const char *const f16_patt[] = {
76bc74dc 1098 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1099 };
ccc9c027
L		 1100 /* nopl (%[re]ax) */
1101 static const char alt_3[] =
1102 {0x0f,0x1f,0x00};
1103 /* nopl 0(%[re]ax) */
1104 static const char alt_4[] =
1105 {0x0f,0x1f,0x40,0x00};
1106 /* nopl 0(%[re]ax,%[re]ax,1) */
1107 static const char alt_5[] =
1108 {0x0f,0x1f,0x44,0x00,0x00};
1109 /* nopw 0(%[re]ax,%[re]ax,1) */
1110 static const char alt_6[] =
1111 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1112 /* nopl 0L(%[re]ax) */
1113 static const char alt_7[] =
1114 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1115 /* nopl 0L(%[re]ax,%[re]ax,1) */
1116 static const char alt_8[] =
1117 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1118 /* nopw 0L(%[re]ax,%[re]ax,1) */
1119 static const char alt_9[] =
1120 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1121 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1122 static const char alt_10[] =
1123 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1124 /* data16
1125 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1126 static const char alt_long_11[] =
1127 {0x66,
1128 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1129 /* data16
1130 data16
1131 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1132 static const char alt_long_12[] =
1133 {0x66,
1134 0x66,
1135 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1136 /* data16
1137 data16
1138 data16
1139 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1140 static const char alt_long_13[] =
1141 {0x66,
1142 0x66,
1143 0x66,
1144 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1145 /* data16
1146 data16
1147 data16
1148 data16
1149 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1150 static const char alt_long_14[] =
1151 {0x66,
1152 0x66,
1153 0x66,
1154 0x66,
1155 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1156 /* data16
1157 data16
1158 data16
1159 data16
1160 data16
1161 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1162 static const char alt_long_15[] =
1163 {0x66,
1164 0x66,
1165 0x66,
1166 0x66,
1167 0x66,
1168 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1169 /* nopl 0(%[re]ax,%[re]ax,1)
1170 nopw 0(%[re]ax,%[re]ax,1) */
1171 static const char alt_short_11[] =
1172 {0x0f,0x1f,0x44,0x00,0x00,
1173 0x66,0x0f,0x1f,0x44,0x00,0x00};
1174 /* nopw 0(%[re]ax,%[re]ax,1)
1175 nopw 0(%[re]ax,%[re]ax,1) */
1176 static const char alt_short_12[] =
1177 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1178 0x66,0x0f,0x1f,0x44,0x00,0x00};
1179 /* nopw 0(%[re]ax,%[re]ax,1)
1180 nopl 0L(%[re]ax) */
1181 static const char alt_short_13[] =
1182 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1183 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1184 /* nopl 0L(%[re]ax)
1185 nopl 0L(%[re]ax) */
1186 static const char alt_short_14[] =
1187 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1188 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1189 /* nopl 0L(%[re]ax)
1190 nopl 0L(%[re]ax,%[re]ax,1) */
1191 static const char alt_short_15[] =
1192 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1193 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1194 static const char *const alt_short_patt[] = {
1195 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1196 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1197 alt_short_14, alt_short_15
1198 };
1199 static const char *const alt_long_patt[] = {
1200 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1201 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1202 alt_long_14, alt_long_15
1203 };
252b5132 1204
76bc74dc
L		 1205 /* Only align for at least a positive non-zero boundary. */
1206 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1207 return;
3e73aa7c 1208
ccc9c027
L		 1209 /* We need to decide which NOP sequence to use for 32bit and
1210 64bit. When -mtune= is used:
4eed87de 1211
76bc74dc
L		 1212 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1213 PROCESSOR_GENERIC32, f32_patt will be used.
1214 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1215 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1216 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1217 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
7b458c12 1218 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
69dd9865 1219 will be used.
ccc9c027 1220
76bc74dc 1221 When -mtune= isn't used, alt_long_patt will be used if
22109423 1222 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1223 be used.
ccc9c027
L		 1224
1225 When -march= or .arch is used, we can't use anything beyond
1226 cpu_arch_isa_flags. */
1227
1228 if (flag_code == CODE_16BIT)
1229 {
ccc9c027 1230 if (count > 8)
33fef721 1231 {
76bc74dc
L		 1232 memcpy (fragP->fr_literal + fragP->fr_fix,
1233 jump_31, count);
1234 /* Adjust jump offset. */
1235 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1236 }
76bc74dc
L		 1237 else
1238 memcpy (fragP->fr_literal + fragP->fr_fix,
1239 f16_patt[count - 1], count);
252b5132 1240 }
33fef721 1241 else
ccc9c027
L		 1242 {
1243 const char *const *patt = NULL;
1244
fbf3f584 1245 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1246 {
1247 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1248 switch (cpu_arch_tune)
1249 {
1250 case PROCESSOR_UNKNOWN:
1251 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1252 optimize with nops. */
1253 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1254 patt = alt_long_patt;
ccc9c027
L		 1255 else
1256 patt = f32_patt;
1257 break;
ccc9c027
L		 1258 case PROCESSOR_PENTIUM4:
1259 case PROCESSOR_NOCONA:
ef05d495 1260 case PROCESSOR_CORE:
76bc74dc 1261 case PROCESSOR_CORE2:
bd5295b2 1262 case PROCESSOR_COREI7:
3632d14b 1263 case PROCESSOR_L1OM:
7a9068fe 1264 case PROCESSOR_K1OM:
76bc74dc
L		 1265 case PROCESSOR_GENERIC64:
1266 patt = alt_long_patt;
1267 break;
ccc9c027
L		 1268 case PROCESSOR_K6:
1269 case PROCESSOR_ATHLON:
1270 case PROCESSOR_K8:
4eed87de 1271 case PROCESSOR_AMDFAM10:
8aedb9fe 1272 case PROCESSOR_BD:
7b458c12 1273 case PROCESSOR_BT:
ccc9c027
L		 1274 patt = alt_short_patt;
1275 break;
76bc74dc 1276 case PROCESSOR_I386:
ccc9c027
L		 1277 case PROCESSOR_I486:
1278 case PROCESSOR_PENTIUM:
2dde1948 1279 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1280 case PROCESSOR_GENERIC32:
1281 patt = f32_patt;
1282 break;
4eed87de 1283 }
ccc9c027
L		 1284 }
1285 else
1286 {
fbf3f584 1287 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1288 {
1289 case PROCESSOR_UNKNOWN:
e6a14101 1290 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1291 PROCESSOR_UNKNOWN. */
1292 abort ();
1293 break;
1294
76bc74dc 1295 case PROCESSOR_I386:
ccc9c027
L		 1296 case PROCESSOR_I486:
1297 case PROCESSOR_PENTIUM:
ccc9c027
L		 1298 case PROCESSOR_K6:
1299 case PROCESSOR_ATHLON:
1300 case PROCESSOR_K8:
4eed87de 1301 case PROCESSOR_AMDFAM10:
8aedb9fe 1302 case PROCESSOR_BD:
7b458c12 1303 case PROCESSOR_BT:
ccc9c027
L		 1304 case PROCESSOR_GENERIC32:
1305 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1306 with nops. */
1307 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1308 patt = alt_short_patt;
1309 else
1310 patt = f32_patt;
1311 break;
76bc74dc
L		 1312 case PROCESSOR_PENTIUMPRO:
1313 case PROCESSOR_PENTIUM4:
1314 case PROCESSOR_NOCONA:
1315 case PROCESSOR_CORE:
ef05d495 1316 case PROCESSOR_CORE2:
bd5295b2 1317 case PROCESSOR_COREI7:
3632d14b 1318 case PROCESSOR_L1OM:
7a9068fe 1319 case PROCESSOR_K1OM:
22109423 1320 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1321 patt = alt_long_patt;
1322 else
1323 patt = f32_patt;
1324 break;
1325 case PROCESSOR_GENERIC64:
76bc74dc 1326 patt = alt_long_patt;
ccc9c027 1327 break;
4eed87de 1328 }
ccc9c027
L		 1329 }
1330
76bc74dc
L		 1331 if (patt == f32_patt)
1332 {
1333 /* If the padding is less than 15 bytes, we use the normal
1334 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1335 its offset. */
1336 int limit;
76ba9986 1337
711eedef
L		 1338 /* For 64bit, the limit is 3 bytes. */
1339 if (flag_code == CODE_64BIT
1340 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1341 limit = 3;
1342 else
1343 limit = 15;
1344 if (count < limit)
76bc74dc
L		 1345 memcpy (fragP->fr_literal + fragP->fr_fix,
1346 patt[count - 1], count);
1347 else
1348 {
1349 memcpy (fragP->fr_literal + fragP->fr_fix,
1350 jump_31, count);
1351 /* Adjust jump offset. */
1352 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1353 }
1354 }
1355 else
1356 {
1357 /* Maximum length of an instruction is 15 byte. If the
1358 padding is greater than 15 bytes and we don't use jump,
1359 we have to break it into smaller pieces. */
1360 int padding = count;
1361 while (padding > 15)
1362 {
1363 padding -= 15;
1364 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1365 patt [14], 15);
1366 }
1367
1368 if (padding)
1369 memcpy (fragP->fr_literal + fragP->fr_fix,
1370 patt [padding - 1], padding);
1371 }
ccc9c027 1372 }
33fef721 1373 fragP->fr_var = count;
252b5132
RH		 1374}
1375
c6fb90c8 1376static INLINE int
0dfbf9d7 1377operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1378{
0dfbf9d7 1379 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1380 {
1381 case 3:
0dfbf9d7 1382 if (x->array[2])
c6fb90c8
L		 1383 return 0;
1384 case 2:
0dfbf9d7 1385 if (x->array[1])
c6fb90c8
L		 1386 return 0;
1387 case 1:
0dfbf9d7 1388 return !x->array[0];
c6fb90c8
L		 1389 default:
1390 abort ();
1391 }
40fb9820
L		 1392}
1393
c6fb90c8 1394static INLINE void
0dfbf9d7 1395operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1396{
0dfbf9d7 1397 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1398 {
1399 case 3:
0dfbf9d7 1400 x->array[2] = v;
c6fb90c8 1401 case 2:
0dfbf9d7 1402 x->array[1] = v;
c6fb90c8 1403 case 1:
0dfbf9d7 1404 x->array[0] = v;
c6fb90c8
L		 1405 break;
1406 default:
1407 abort ();
1408 }
1409}
40fb9820 1410
c6fb90c8 1411static INLINE int
0dfbf9d7
L		 1412operand_type_equal (const union i386_operand_type *x,
1413 const union i386_operand_type *y)
c6fb90c8 1414{
0dfbf9d7 1415 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1416 {
1417 case 3:
0dfbf9d7 1418 if (x->array[2] != y->array[2])
c6fb90c8
L		 1419 return 0;
1420 case 2:
0dfbf9d7 1421 if (x->array[1] != y->array[1])
c6fb90c8
L		 1422 return 0;
1423 case 1:
0dfbf9d7 1424 return x->array[0] == y->array[0];
c6fb90c8
L		 1425 break;
1426 default:
1427 abort ();
1428 }
1429}
40fb9820 1430
0dfbf9d7
L		 1431static INLINE int
1432cpu_flags_all_zero (const union i386_cpu_flags *x)
1433{
1434 switch (ARRAY_SIZE(x->array))
1435 {
1436 case 3:
1437 if (x->array[2])
1438 return 0;
1439 case 2:
1440 if (x->array[1])
1441 return 0;
1442 case 1:
1443 return !x->array[0];
1444 default:
1445 abort ();
1446 }
1447}
1448
1449static INLINE void
1450cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1451{
1452 switch (ARRAY_SIZE(x->array))
1453 {
1454 case 3:
1455 x->array[2] = v;
1456 case 2:
1457 x->array[1] = v;
1458 case 1:
1459 x->array[0] = v;
1460 break;
1461 default:
1462 abort ();
1463 }
1464}
1465
1466static INLINE int
1467cpu_flags_equal (const union i386_cpu_flags *x,
1468 const union i386_cpu_flags *y)
1469{
1470 switch (ARRAY_SIZE(x->array))
1471 {
1472 case 3:
1473 if (x->array[2] != y->array[2])
1474 return 0;
1475 case 2:
1476 if (x->array[1] != y->array[1])
1477 return 0;
1478 case 1:
1479 return x->array[0] == y->array[0];
1480 break;
1481 default:
1482 abort ();
1483 }
1484}
c6fb90c8
L		 1485
1486static INLINE int
1487cpu_flags_check_cpu64 (i386_cpu_flags f)
1488{
1489 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1490 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1491}
1492
c6fb90c8
L		 1493static INLINE i386_cpu_flags
1494cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1495{
c6fb90c8
L		 1496 switch (ARRAY_SIZE (x.array))
1497 {
1498 case 3:
1499 x.array [2] &= y.array [2];
1500 case 2:
1501 x.array [1] &= y.array [1];
1502 case 1:
1503 x.array [0] &= y.array [0];
1504 break;
1505 default:
1506 abort ();
1507 }
1508 return x;
1509}
40fb9820 1510
c6fb90c8
L		 1511static INLINE i386_cpu_flags
1512cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1513{
c6fb90c8 1514 switch (ARRAY_SIZE (x.array))
40fb9820 1515 {
c6fb90c8
L		 1516 case 3:
1517 x.array [2] |= y.array [2];
1518 case 2:
1519 x.array [1] |= y.array [1];
1520 case 1:
1521 x.array [0] |= y.array [0];
40fb9820
L		 1522 break;
1523 default:
1524 abort ();
1525 }
40fb9820
L		 1526 return x;
1527}
1528
309d3373
JB		 1529static INLINE i386_cpu_flags
1530cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1531{
1532 switch (ARRAY_SIZE (x.array))
1533 {
1534 case 3:
1535 x.array [2] &= ~y.array [2];
1536 case 2:
1537 x.array [1] &= ~y.array [1];
1538 case 1:
1539 x.array [0] &= ~y.array [0];
1540 break;
1541 default:
1542 abort ();
1543 }
1544 return x;
1545}
1546
c0f3af97
L		 1547#define CPU_FLAGS_ARCH_MATCH 0x1
1548#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1549#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1550#define CPU_FLAGS_PCLMUL_MATCH 0x8
1551#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1552
a5ff0eb2 1553#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1554 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1555 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1556#define CPU_FLAGS_PERFECT_MATCH \
1557 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1558
1559/* Return CPU flags match bits. */
3629bb00 1560
40fb9820 1561static int
d3ce72d0 1562cpu_flags_match (const insn_template *t)
40fb9820 1563{
c0f3af97
L		 1564 i386_cpu_flags x = t->cpu_flags;
1565 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1566
1567 x.bitfield.cpu64 = 0;
1568 x.bitfield.cpuno64 = 0;
1569
0dfbf9d7 1570 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1571 {
1572 /* This instruction is available on all archs. */
1573 match |= CPU_FLAGS_32BIT_MATCH;
1574 }
3629bb00
L		 1575 else
1576 {
c0f3af97 1577 /* This instruction is available only on some archs. */
3629bb00
L		 1578 i386_cpu_flags cpu = cpu_arch_flags;
1579
1580 cpu.bitfield.cpu64 = 0;
1581 cpu.bitfield.cpuno64 = 0;
1582 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1583 if (!cpu_flags_all_zero (&cpu))
1584 {
a5ff0eb2
L		 1585 if (x.bitfield.cpuavx)
1586 {
ce2f5b3c 1587 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1588 if (cpu.bitfield.cpuavx)
1589 {
1590 /* Check SSE2AVX. */
1591 if (!t->opcode_modifier.sse2avx|| sse2avx)
1592 {
1593 match |= (CPU_FLAGS_ARCH_MATCH
1594 | CPU_FLAGS_AVX_MATCH);
1595 /* Check AES. */
1596 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1597 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1598 /* Check PCLMUL. */
1599 if (!x.bitfield.cpupclmul
1600 || cpu.bitfield.cpupclmul)
1601 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1602 }
1603 }
1604 else
1605 match |= CPU_FLAGS_ARCH_MATCH;
1606 }
1607 else
c0f3af97
L		 1608 match |= CPU_FLAGS_32BIT_MATCH;
1609 }
3629bb00 1610 }
c0f3af97 1611 return match;
40fb9820
L		 1612}
1613
c6fb90c8
L		 1614static INLINE i386_operand_type
1615operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1616{
c6fb90c8
L		 1617 switch (ARRAY_SIZE (x.array))
1618 {
1619 case 3:
1620 x.array [2] &= y.array [2];
1621 case 2:
1622 x.array [1] &= y.array [1];
1623 case 1:
1624 x.array [0] &= y.array [0];
1625 break;
1626 default:
1627 abort ();
1628 }
1629 return x;
40fb9820
L		 1630}
1631
c6fb90c8
L		 1632static INLINE i386_operand_type
1633operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1634{
c6fb90c8 1635 switch (ARRAY_SIZE (x.array))
40fb9820 1636 {
c6fb90c8
L		 1637 case 3:
1638 x.array [2] |= y.array [2];
1639 case 2:
1640 x.array [1] |= y.array [1];
1641 case 1:
1642 x.array [0] |= y.array [0];
40fb9820
L		 1643 break;
1644 default:
1645 abort ();
1646 }
c6fb90c8
L		 1647 return x;
1648}
40fb9820 1649
c6fb90c8
L		 1650static INLINE i386_operand_type
1651operand_type_xor (i386_operand_type x, i386_operand_type y)
1652{
1653 switch (ARRAY_SIZE (x.array))
1654 {
1655 case 3:
1656 x.array [2] ^= y.array [2];
1657 case 2:
1658 x.array [1] ^= y.array [1];
1659 case 1:
1660 x.array [0] ^= y.array [0];
1661 break;
1662 default:
1663 abort ();
1664 }
40fb9820
L		 1665 return x;
1666}
1667
1668static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1669static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1670static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1671static const i386_operand_type inoutportreg
1672 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1673static const i386_operand_type reg16_inoutportreg
1674 = OPERAND_TYPE_REG16_INOUTPORTREG;
1675static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1676static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1677static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1678static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1679static const i386_operand_type anydisp
1680 = OPERAND_TYPE_ANYDISP;
40fb9820 1681static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1682static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1683static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1684static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1685static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1686static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1687static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1688static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1689static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1690static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1691static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1692static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1693static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1694static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1695
1696enum operand_type
1697{
1698 reg,
40fb9820
L		 1699 imm,
1700 disp,
1701 anymem
1702};
1703
c6fb90c8 1704static INLINE int
40fb9820
L		 1705operand_type_check (i386_operand_type t, enum operand_type c)
1706{
1707 switch (c)
1708 {
1709 case reg:
1710 return (t.bitfield.reg8
1711 || t.bitfield.reg16
1712 || t.bitfield.reg32
1713 || t.bitfield.reg64);
1714
40fb9820
L		 1715 case imm:
1716 return (t.bitfield.imm8
1717 || t.bitfield.imm8s
1718 || t.bitfield.imm16
1719 || t.bitfield.imm32
1720 || t.bitfield.imm32s
1721 || t.bitfield.imm64);
1722
1723 case disp:
1724 return (t.bitfield.disp8
1725 || t.bitfield.disp16
1726 || t.bitfield.disp32
1727 || t.bitfield.disp32s
1728 || t.bitfield.disp64);
1729
1730 case anymem:
1731 return (t.bitfield.disp8
1732 || t.bitfield.disp16
1733 || t.bitfield.disp32
1734 || t.bitfield.disp32s
1735 || t.bitfield.disp64
1736 || t.bitfield.baseindex);
1737
1738 default:
1739 abort ();
1740 }
2cfe26b6
AM		 1741
1742 return 0;
40fb9820
L		 1743}
1744
5c07affc
L		 1745/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1746 operand J for instruction template T. */
1747
1748static INLINE int
d3ce72d0 1749match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1750{
1751 return !((i.types[j].bitfield.byte
1752 && !t->operand_types[j].bitfield.byte)
1753 || (i.types[j].bitfield.word
1754 && !t->operand_types[j].bitfield.word)
1755 || (i.types[j].bitfield.dword
1756 && !t->operand_types[j].bitfield.dword)
1757 || (i.types[j].bitfield.qword
1758 && !t->operand_types[j].bitfield.qword));
1759}
1760
1761/* Return 1 if there is no conflict in any size on operand J for
1762 instruction template T. */
1763
1764static INLINE int
d3ce72d0 1765match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1766{
1767 return (match_reg_size (t, j)
1768 && !((i.types[j].bitfield.unspecified
1769 && !t->operand_types[j].bitfield.unspecified)
1770 || (i.types[j].bitfield.fword
1771 && !t->operand_types[j].bitfield.fword)
1772 || (i.types[j].bitfield.tbyte
1773 && !t->operand_types[j].bitfield.tbyte)
1774 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1775 && !t->operand_types[j].bitfield.xmmword)
1776 || (i.types[j].bitfield.ymmword
43234a1e
L		 1777 && !t->operand_types[j].bitfield.ymmword)
1778 || (i.types[j].bitfield.zmmword
1779 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1780}
1781
1782/* Return 1 if there is no size conflict on any operands for
1783 instruction template T. */
1784
1785static INLINE int
d3ce72d0 1786operand_size_match (const insn_template *t)
5c07affc
L		 1787{
1788 unsigned int j;
1789 int match = 1;
1790
1791 /* Don't check jump instructions. */
1792 if (t->opcode_modifier.jump
1793 || t->opcode_modifier.jumpbyte
1794 || t->opcode_modifier.jumpdword
1795 || t->opcode_modifier.jumpintersegment)
1796 return match;
1797
1798 /* Check memory and accumulator operand size. */
1799 for (j = 0; j < i.operands; j++)
1800 {
1801 if (t->operand_types[j].bitfield.anysize)
1802 continue;
1803
1804 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1805 {
1806 match = 0;
1807 break;
1808 }
1809
1810 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1811 {
1812 match = 0;
1813 break;
1814 }
1815 }
1816
891edac4 1817 if (match)
5c07affc 1818 return match;
891edac4
L		 1819 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1820 {
1821mismatch:
86e026a4 1822 i.error = operand_size_mismatch;
891edac4
L		 1823 return 0;
1824 }
5c07affc
L		 1825
1826 /* Check reverse. */
9c2799c2 1827 gas_assert (i.operands == 2);
5c07affc
L		 1828
1829 match = 1;
1830 for (j = 0; j < 2; j++)
1831 {
1832 if (t->operand_types[j].bitfield.acc
1833 && !match_reg_size (t, j ? 0 : 1))
891edac4 1834 goto mismatch;
5c07affc
L		 1835
1836 if (i.types[j].bitfield.mem
1837 && !match_mem_size (t, j ? 0 : 1))
891edac4 1838 goto mismatch;
5c07affc
L		 1839 }
1840
1841 return match;
1842}
1843
c6fb90c8 1844static INLINE int
40fb9820
L		 1845operand_type_match (i386_operand_type overlap,
1846 i386_operand_type given)
1847{
1848 i386_operand_type temp = overlap;
1849
1850 temp.bitfield.jumpabsolute = 0;
7d5e4556 1851 temp.bitfield.unspecified = 0;
5c07affc
L		 1852 temp.bitfield.byte = 0;
1853 temp.bitfield.word = 0;
1854 temp.bitfield.dword = 0;
1855 temp.bitfield.fword = 0;
1856 temp.bitfield.qword = 0;
1857 temp.bitfield.tbyte = 0;
1858 temp.bitfield.xmmword = 0;
c0f3af97 1859 temp.bitfield.ymmword = 0;
43234a1e 1860 temp.bitfield.zmmword = 0;
0dfbf9d7 1861 if (operand_type_all_zero (&temp))
891edac4 1862 goto mismatch;
40fb9820 1863
891edac4
L		 1864 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1865 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1866 return 1;
1867
1868mismatch:
a65babc9 1869 i.error = operand_type_mismatch;
891edac4 1870 return 0;
40fb9820
L		 1871}
1872
7d5e4556 1873/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1874 unless the expected operand type register overlap is null.
1875 Note that Acc in a template matches every size of reg. */
1876
c6fb90c8 1877static INLINE int
40fb9820
L		 1878operand_type_register_match (i386_operand_type m0,
1879 i386_operand_type g0,
1880 i386_operand_type t0,
1881 i386_operand_type m1,
1882 i386_operand_type g1,
1883 i386_operand_type t1)
1884{
1885 if (!operand_type_check (g0, reg))
1886 return 1;
1887
1888 if (!operand_type_check (g1, reg))
1889 return 1;
1890
1891 if (g0.bitfield.reg8 == g1.bitfield.reg8
1892 && g0.bitfield.reg16 == g1.bitfield.reg16
1893 && g0.bitfield.reg32 == g1.bitfield.reg32
1894 && g0.bitfield.reg64 == g1.bitfield.reg64)
1895 return 1;
1896
1897 if (m0.bitfield.acc)
1898 {
1899 t0.bitfield.reg8 = 1;
1900 t0.bitfield.reg16 = 1;
1901 t0.bitfield.reg32 = 1;
1902 t0.bitfield.reg64 = 1;
1903 }
1904
1905 if (m1.bitfield.acc)
1906 {
1907 t1.bitfield.reg8 = 1;
1908 t1.bitfield.reg16 = 1;
1909 t1.bitfield.reg32 = 1;
1910 t1.bitfield.reg64 = 1;
1911 }
1912
891edac4
L		 1913 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1914 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1915 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1916 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1917 return 1;
1918
a65babc9 1919 i.error = register_type_mismatch;
891edac4
L		 1920
1921 return 0;
40fb9820
L		 1922}
1923
4c692bc7
JB		 1924static INLINE unsigned int
1925register_number (const reg_entry *r)
1926{
1927 unsigned int nr = r->reg_num;
1928
1929 if (r->reg_flags & RegRex)
1930 nr += 8;
1931
1932 return nr;
1933}
1934
252b5132 1935static INLINE unsigned int
40fb9820 1936mode_from_disp_size (i386_operand_type t)
252b5132 1937{
43234a1e 1938 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1939 return 1;
1940 else if (t.bitfield.disp16
1941 || t.bitfield.disp32
1942 || t.bitfield.disp32s)
1943 return 2;
1944 else
1945 return 0;
252b5132
RH		 1946}
1947
1948static INLINE int
65879393 1949fits_in_signed_byte (addressT num)
252b5132 1950{
65879393 1951 return num + 0x80 <= 0xff;
47926f60 1952}
252b5132
RH		 1953
1954static INLINE int
65879393 1955fits_in_unsigned_byte (addressT num)
252b5132 1956{
65879393 1957 return num <= 0xff;
47926f60 1958}
252b5132
RH		 1959
1960static INLINE int
65879393 1961fits_in_unsigned_word (addressT num)
252b5132 1962{
65879393 1963 return num <= 0xffff;
47926f60 1964}
252b5132
RH		 1965
1966static INLINE int
65879393 1967fits_in_signed_word (addressT num)
252b5132 1968{
65879393 1969 return num + 0x8000 <= 0xffff;
47926f60 1970}
2a962e6d 1971
3e73aa7c 1972static INLINE int
65879393 1973fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1974{
1975#ifndef BFD64
1976 return 1;
1977#else
65879393 1978 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1979#endif
1980} /* fits_in_signed_long() */
2a962e6d 1981
3e73aa7c 1982static INLINE int
65879393 1983fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1984{
1985#ifndef BFD64
1986 return 1;
1987#else
65879393 1988 return num <= 0xffffffff;
3e73aa7c
JH		 1989#endif
1990} /* fits_in_unsigned_long() */
252b5132 1991
43234a1e
L		 1992static INLINE int
1993fits_in_vec_disp8 (offsetT num)
1994{
1995 int shift = i.memshift;
1996 unsigned int mask;
1997
1998 if (shift == -1)
1999 abort ();
2000
2001 mask = (1 << shift) - 1;
2002
2003 /* Return 0 if NUM isn't properly aligned. */
2004 if ((num & mask))
2005 return 0;
2006
2007 /* Check if NUM will fit in 8bit after shift. */
2008 return fits_in_signed_byte (num >> shift);
2009}
2010
a683cc34
SP		 2011static INLINE int
2012fits_in_imm4 (offsetT num)
2013{
2014 return (num & 0xf) == num;
2015}
2016
40fb9820 2017static i386_operand_type
e3bb37b5 2018smallest_imm_type (offsetT num)
252b5132 2019{
40fb9820 2020 i386_operand_type t;
7ab9ffdd 2021
0dfbf9d7 2022 operand_type_set (&t, 0);
40fb9820
L		 2023 t.bitfield.imm64 = 1;
2024
2025 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2026 {
2027 /* This code is disabled on the 486 because all the Imm1 forms
2028 in the opcode table are slower on the i486. They're the
2029 versions with the implicitly specified single-position
2030 displacement, which has another syntax if you really want to
2031 use that form. */
40fb9820
L		 2032 t.bitfield.imm1 = 1;
2033 t.bitfield.imm8 = 1;
2034 t.bitfield.imm8s = 1;
2035 t.bitfield.imm16 = 1;
2036 t.bitfield.imm32 = 1;
2037 t.bitfield.imm32s = 1;
2038 }
2039 else if (fits_in_signed_byte (num))
2040 {
2041 t.bitfield.imm8 = 1;
2042 t.bitfield.imm8s = 1;
2043 t.bitfield.imm16 = 1;
2044 t.bitfield.imm32 = 1;
2045 t.bitfield.imm32s = 1;
2046 }
2047 else if (fits_in_unsigned_byte (num))
2048 {
2049 t.bitfield.imm8 = 1;
2050 t.bitfield.imm16 = 1;
2051 t.bitfield.imm32 = 1;
2052 t.bitfield.imm32s = 1;
2053 }
2054 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2055 {
2056 t.bitfield.imm16 = 1;
2057 t.bitfield.imm32 = 1;
2058 t.bitfield.imm32s = 1;
2059 }
2060 else if (fits_in_signed_long (num))
2061 {
2062 t.bitfield.imm32 = 1;
2063 t.bitfield.imm32s = 1;
2064 }
2065 else if (fits_in_unsigned_long (num))
2066 t.bitfield.imm32 = 1;
2067
2068 return t;
47926f60 2069}
252b5132 2070
847f7ad4 2071static offsetT
e3bb37b5 2072offset_in_range (offsetT val, int size)
847f7ad4 2073{
508866be 2074 addressT mask;
ba2adb93 2075
847f7ad4
AM		 2076 switch (size)
2077 {
508866be
L		 2078 case 1: mask = ((addressT) 1 << 8) - 1; break;
2079 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2080 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2081#ifdef BFD64
2082 case 8: mask = ((addressT) 2 << 63) - 1; break;
2083#endif
47926f60 2084 default: abort ();
847f7ad4
AM		 2085 }
2086
9de868bf
L		 2087#ifdef BFD64
2088 /* If BFD64, sign extend val for 32bit address mode. */
2089 if (flag_code != CODE_64BIT
2090 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2091 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2092 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2093#endif
ba2adb93 2094
47926f60 2095 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2096 {
2097 char buf1[40], buf2[40];
2098
2099 sprint_value (buf1, val);
2100 sprint_value (buf2, val & mask);
2101 as_warn (_("%s shortened to %s"), buf1, buf2);
2102 }
2103 return val & mask;
2104}
2105
c32fa91d
L		 2106enum PREFIX_GROUP
2107{
2108 PREFIX_EXIST = 0,
2109 PREFIX_LOCK,
2110 PREFIX_REP,
2111 PREFIX_OTHER
2112};
2113
2114/* Returns
2115 a. PREFIX_EXIST if attempting to add a prefix where one from the
2116 same class already exists.
2117 b. PREFIX_LOCK if lock prefix is added.
2118 c. PREFIX_REP if rep/repne prefix is added.
2119 d. PREFIX_OTHER if other prefix is added.
2120 */
2121
2122static enum PREFIX_GROUP
e3bb37b5 2123add_prefix (unsigned int prefix)
252b5132 2124{
c32fa91d 2125 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2126 unsigned int q;
252b5132 2127
29b0f896
AM		 2128 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2129 && flag_code == CODE_64BIT)
b1905489 2130 {
161a04f6
L		 2131 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2132 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2133 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2134 ret = PREFIX_EXIST;
b1905489
JB		 2135 q = REX_PREFIX;
2136 }
3e73aa7c 2137 else
b1905489
JB		 2138 {
2139 switch (prefix)
2140 {
2141 default:
2142 abort ();
2143
2144 case CS_PREFIX_OPCODE:
2145 case DS_PREFIX_OPCODE:
2146 case ES_PREFIX_OPCODE:
2147 case FS_PREFIX_OPCODE:
2148 case GS_PREFIX_OPCODE:
2149 case SS_PREFIX_OPCODE:
2150 q = SEG_PREFIX;
2151 break;
2152
2153 case REPNE_PREFIX_OPCODE:
2154 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2155 q = REP_PREFIX;
2156 ret = PREFIX_REP;
2157 break;
2158
b1905489 2159 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2160 q = LOCK_PREFIX;
2161 ret = PREFIX_LOCK;
b1905489
JB		 2162 break;
2163
2164 case FWAIT_OPCODE:
2165 q = WAIT_PREFIX;
2166 break;
2167
2168 case ADDR_PREFIX_OPCODE:
2169 q = ADDR_PREFIX;
2170 break;
2171
2172 case DATA_PREFIX_OPCODE:
2173 q = DATA_PREFIX;
2174 break;
2175 }
2176 if (i.prefix[q] != 0)
c32fa91d 2177 ret = PREFIX_EXIST;
b1905489 2178 }
252b5132 2179
b1905489 2180 if (ret)
252b5132 2181 {
b1905489
JB		 2182 if (!i.prefix[q])
2183 ++i.prefixes;
2184 i.prefix[q] |= prefix;
252b5132 2185 }
b1905489
JB		 2186 else
2187 as_bad (_("same type of prefix used twice"));
252b5132 2188
252b5132
RH		 2189 return ret;
2190}
2191
2192static void
78f12dd3 2193update_code_flag (int value, int check)
eecb386c 2194{
78f12dd3
L		 2195 PRINTF_LIKE ((*as_error));
2196
1e9cc1c2 2197 flag_code = (enum flag_code) value;
40fb9820
L		 2198 if (flag_code == CODE_64BIT)
2199 {
2200 cpu_arch_flags.bitfield.cpu64 = 1;
2201 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2202 }
2203 else
2204 {
2205 cpu_arch_flags.bitfield.cpu64 = 0;
2206 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2207 }
2208 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2209 {
78f12dd3
L		 2210 if (check)
2211 as_error = as_fatal;
2212 else
2213 as_error = as_bad;
2214 (*as_error) (_("64bit mode not supported on `%s'."),
2215 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2216 }
40fb9820 2217 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2218 {
78f12dd3
L		 2219 if (check)
2220 as_error = as_fatal;
2221 else
2222 as_error = as_bad;
2223 (*as_error) (_("32bit mode not supported on `%s'."),
2224 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2225 }
eecb386c
AM		 2226 stackop_size = '\0';
2227}
2228
78f12dd3
L		 2229static void
2230set_code_flag (int value)
2231{
2232 update_code_flag (value, 0);
2233}
2234
eecb386c 2235static void
e3bb37b5 2236set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2237{
1e9cc1c2 2238 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2239 if (flag_code != CODE_16BIT)
2240 abort ();
2241 cpu_arch_flags.bitfield.cpu64 = 0;
2242 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2243 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2244}
2245
2246static void
e3bb37b5 2247set_intel_syntax (int syntax_flag)
252b5132
RH		 2248{
2249 /* Find out if register prefixing is specified. */
2250 int ask_naked_reg = 0;
2251
2252 SKIP_WHITESPACE ();
29b0f896 2253 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2254 {
2255 char *string = input_line_pointer;
2256 int e = get_symbol_end ();
2257
47926f60 2258 if (strcmp (string, "prefix") == 0)
252b5132 2259 ask_naked_reg = 1;
47926f60 2260 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2261 ask_naked_reg = -1;
2262 else
d0b47220 2263 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2264 *input_line_pointer = e;
2265 }
2266 demand_empty_rest_of_line ();
c3332e24 2267
252b5132
RH		 2268 intel_syntax = syntax_flag;
2269
2270 if (ask_naked_reg == 0)
f86103b7
AM		 2271 allow_naked_reg = (intel_syntax
2272 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2273 else
2274 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2275
ee86248c 2276 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2277
e4a3b5a4 2278 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2279 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2280 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2281}
2282
1efbbeb4
L		 2283static void
2284set_intel_mnemonic (int mnemonic_flag)
2285{
e1d4d893 2286 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2287}
2288
db51cc60
L		 2289static void
2290set_allow_index_reg (int flag)
2291{
2292 allow_index_reg = flag;
2293}
2294
cb19c032 2295static void
7bab8ab5 2296set_check (int what)
cb19c032 2297{
7bab8ab5
JB		 2298 enum check_kind *kind;
2299 const char *str;
2300
2301 if (what)
2302 {
2303 kind = &operand_check;
2304 str = "operand";
2305 }
2306 else
2307 {
2308 kind = &sse_check;
2309 str = "sse";
2310 }
2311
cb19c032
L		 2312 SKIP_WHITESPACE ();
2313
2314 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2315 {
2316 char *string = input_line_pointer;
2317 int e = get_symbol_end ();
2318
2319 if (strcmp (string, "none") == 0)
7bab8ab5 2320 *kind = check_none;
cb19c032 2321 else if (strcmp (string, "warning") == 0)
7bab8ab5 2322 *kind = check_warning;
cb19c032 2323 else if (strcmp (string, "error") == 0)
7bab8ab5 2324 *kind = check_error;
cb19c032 2325 else
7bab8ab5 2326 as_bad (_("bad argument to %s_check directive."), str);
cb19c032
L		 2327 *input_line_pointer = e;
2328 }
2329 else
7bab8ab5 2330 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2331
2332 demand_empty_rest_of_line ();
2333}
2334
8a9036a4
L		 2335static void
2336check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2337 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2338{
2339#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2340 static const char *arch;
2341
2342 /* Intel LIOM is only supported on ELF. */
2343 if (!IS_ELF)
2344 return;
2345
2346 if (!arch)
2347 {
2348 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2349 use default_arch. */
2350 arch = cpu_arch_name;
2351 if (!arch)
2352 arch = default_arch;
2353 }
2354
3632d14b 2355 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2356 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2357 || new_flag.bitfield.cpul1om)
8a9036a4 2358 return;
76ba9986 2359
7a9068fe
L		 2360 /* If we are targeting Intel K1OM, we must enable it. */
2361 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2362 || new_flag.bitfield.cpuk1om)
2363 return;
2364
8a9036a4
L		 2365 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2366#endif
2367}
2368
e413e4e9 2369static void
e3bb37b5 2370set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2371{
47926f60 2372 SKIP_WHITESPACE ();
e413e4e9 2373
29b0f896 2374 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2375 {
2376 char *string = input_line_pointer;
2377 int e = get_symbol_end ();
91d6fa6a 2378 unsigned int j;
40fb9820 2379 i386_cpu_flags flags;
e413e4e9 2380
91d6fa6a 2381 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2382 {
91d6fa6a 2383 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2384 {
91d6fa6a 2385 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2386
5c6af06e
JB		 2387 if (*string != '.')
2388 {
91d6fa6a 2389 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2390 cpu_sub_arch_name = NULL;
91d6fa6a 2391 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2392 if (flag_code == CODE_64BIT)
2393 {
2394 cpu_arch_flags.bitfield.cpu64 = 1;
2395 cpu_arch_flags.bitfield.cpuno64 = 0;
2396 }
2397 else
2398 {
2399 cpu_arch_flags.bitfield.cpu64 = 0;
2400 cpu_arch_flags.bitfield.cpuno64 = 1;
2401 }
91d6fa6a
NC		 2402 cpu_arch_isa = cpu_arch[j].type;
2403 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2404 if (!cpu_arch_tune_set)
2405 {
2406 cpu_arch_tune = cpu_arch_isa;
2407 cpu_arch_tune_flags = cpu_arch_isa_flags;
2408 }
5c6af06e
JB		 2409 break;
2410 }
40fb9820 2411
22109423 2412 if (!cpu_arch[j].negated)
309d3373 2413 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2414 cpu_arch[j].flags);
309d3373
JB		 2415 else
2416 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2417 cpu_arch[j].flags);
0dfbf9d7 2418 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2419 {
6305a203
L		 2420 if (cpu_sub_arch_name)
2421 {
2422 char *name = cpu_sub_arch_name;
2423 cpu_sub_arch_name = concat (name,
91d6fa6a 2424 cpu_arch[j].name,
1bf57e9f 2425 (const char *) NULL);
6305a203
L		 2426 free (name);
2427 }
2428 else
91d6fa6a 2429 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2430 cpu_arch_flags = flags;
a586129e 2431 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2432 }
2433 *input_line_pointer = e;
2434 demand_empty_rest_of_line ();
2435 return;
e413e4e9
AM		 2436 }
2437 }
91d6fa6a 2438 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2439 as_bad (_("no such architecture: `%s'"), string);
2440
2441 *input_line_pointer = e;
2442 }
2443 else
2444 as_bad (_("missing cpu architecture"));
2445
fddf5b5b
AM		 2446 no_cond_jump_promotion = 0;
2447 if (*input_line_pointer == ','
29b0f896 2448 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2449 {
2450 char *string = ++input_line_pointer;
2451 int e = get_symbol_end ();
2452
2453 if (strcmp (string, "nojumps") == 0)
2454 no_cond_jump_promotion = 1;
2455 else if (strcmp (string, "jumps") == 0)
2456 ;
2457 else
2458 as_bad (_("no such architecture modifier: `%s'"), string);
2459
2460 *input_line_pointer = e;
2461 }
2462
e413e4e9
AM		 2463 demand_empty_rest_of_line ();
2464}
2465
8a9036a4
L		 2466enum bfd_architecture
2467i386_arch (void)
2468{
3632d14b 2469 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2470 {
2471 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2472 || flag_code != CODE_64BIT)
2473 as_fatal (_("Intel L1OM is 64bit ELF only"));
2474 return bfd_arch_l1om;
2475 }
7a9068fe
L		 2476 else if (cpu_arch_isa == PROCESSOR_K1OM)
2477 {
2478 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2479 || flag_code != CODE_64BIT)
2480 as_fatal (_("Intel K1OM is 64bit ELF only"));
2481 return bfd_arch_k1om;
2482 }
8a9036a4
L		 2483 else
2484 return bfd_arch_i386;
2485}
2486
b9d79e03 2487unsigned long
7016a5d5 2488i386_mach (void)
b9d79e03 2489{
351f65ca 2490 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2491 {
3632d14b 2492 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2493 {
351f65ca
L		 2494 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2495 || default_arch[6] != '\0')
8a9036a4
L		 2496 as_fatal (_("Intel L1OM is 64bit ELF only"));
2497 return bfd_mach_l1om;
2498 }
7a9068fe
L		 2499 else if (cpu_arch_isa == PROCESSOR_K1OM)
2500 {
2501 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2502 || default_arch[6] != '\0')
2503 as_fatal (_("Intel K1OM is 64bit ELF only"));
2504 return bfd_mach_k1om;
2505 }
351f65ca 2506 else if (default_arch[6] == '\0')
8a9036a4 2507 return bfd_mach_x86_64;
351f65ca
L		 2508 else
2509 return bfd_mach_x64_32;
8a9036a4 2510 }
b9d79e03
JH		 2511 else if (!strcmp (default_arch, "i386"))
2512 return bfd_mach_i386_i386;
2513 else
2b5d6a91 2514 as_fatal (_("unknown architecture"));
b9d79e03 2515}
b9d79e03 2516\f
252b5132 2517void
7016a5d5 2518md_begin (void)
252b5132
RH		 2519{
2520 const char *hash_err;
2521
47926f60 2522 /* Initialize op_hash hash table. */
252b5132
RH		 2523 op_hash = hash_new ();
2524
2525 {
d3ce72d0 2526 const insn_template *optab;
29b0f896 2527 templates *core_optab;
252b5132 2528
47926f60
KH		 2529 /* Setup for loop. */
2530 optab = i386_optab;
252b5132
RH		 2531 core_optab = (templates *) xmalloc (sizeof (templates));
2532 core_optab->start = optab;
2533
2534 while (1)
2535 {
2536 ++optab;
2537 if (optab->name == NULL
2538 || strcmp (optab->name, (optab - 1)->name) != 0)
2539 {
2540 /* different name --> ship out current template list;
47926f60 2541 add to hash table; & begin anew. */
252b5132
RH		 2542 core_optab->end = optab;
2543 hash_err = hash_insert (op_hash,
2544 (optab - 1)->name,
5a49b8ac 2545 (void *) core_optab);
252b5132
RH		 2546 if (hash_err)
2547 {
b37df7c4 2548 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2549 (optab - 1)->name,
2550 hash_err);
2551 }
2552 if (optab->name == NULL)
2553 break;
2554 core_optab = (templates *) xmalloc (sizeof (templates));
2555 core_optab->start = optab;
2556 }
2557 }
2558 }
2559
47926f60 2560 /* Initialize reg_hash hash table. */
252b5132
RH		 2561 reg_hash = hash_new ();
2562 {
29b0f896 2563 const reg_entry *regtab;
c3fe08fa 2564 unsigned int regtab_size = i386_regtab_size;
252b5132 2565
c3fe08fa 2566 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2567 {
5a49b8ac 2568 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2569 if (hash_err)
b37df7c4 2570 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2571 regtab->reg_name,
2572 hash_err);
252b5132
RH		 2573 }
2574 }
2575
47926f60 2576 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2577 {
29b0f896
AM		 2578 int c;
2579 char *p;
252b5132
RH		 2580
2581 for (c = 0; c < 256; c++)
2582 {
3882b010 2583 if (ISDIGIT (c))
252b5132
RH		 2584 {
2585 digit_chars[c] = c;
2586 mnemonic_chars[c] = c;
2587 register_chars[c] = c;
2588 operand_chars[c] = c;
2589 }
3882b010 2590 else if (ISLOWER (c))
252b5132
RH		 2591 {
2592 mnemonic_chars[c] = c;
2593 register_chars[c] = c;
2594 operand_chars[c] = c;
2595 }
3882b010 2596 else if (ISUPPER (c))
252b5132 2597 {
3882b010 2598 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2599 register_chars[c] = mnemonic_chars[c];
2600 operand_chars[c] = c;
2601 }
43234a1e
L		 2602 else if (c == '{' || c == '}')
2603 operand_chars[c] = c;
252b5132 2604
3882b010 2605 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2606 identifier_chars[c] = c;
2607 else if (c >= 128)
2608 {
2609 identifier_chars[c] = c;
2610 operand_chars[c] = c;
2611 }
2612 }
2613
2614#ifdef LEX_AT
2615 identifier_chars['@'] = '@';
32137342
NC		 2616#endif
2617#ifdef LEX_QM
2618 identifier_chars['?'] = '?';
2619 operand_chars['?'] = '?';
252b5132 2620#endif
252b5132 2621 digit_chars['-'] = '-';
c0f3af97 2622 mnemonic_chars['_'] = '_';
791fe849 2623 mnemonic_chars['-'] = '-';
0003779b 2624 mnemonic_chars['.'] = '.';
252b5132
RH		 2625 identifier_chars['_'] = '_';
2626 identifier_chars['.'] = '.';
2627
2628 for (p = operand_special_chars; *p != '\0'; p++)
2629 operand_chars[(unsigned char) *p] = *p;
2630 }
2631
a4447b93
RH		 2632 if (flag_code == CODE_64BIT)
2633 {
ca19b261
KT		 2634#if defined (OBJ_COFF) && defined (TE_PE)
2635 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2636 ? 32 : 16);
2637#else
a4447b93 2638 x86_dwarf2_return_column = 16;
ca19b261 2639#endif
61ff971f 2640 x86_cie_data_alignment = -8;
a4447b93
RH		 2641 }
2642 else
2643 {
2644 x86_dwarf2_return_column = 8;
2645 x86_cie_data_alignment = -4;
2646 }
252b5132
RH		 2647}
2648
2649void
e3bb37b5 2650i386_print_statistics (FILE *file)
252b5132
RH		 2651{
2652 hash_print_statistics (file, "i386 opcode", op_hash);
2653 hash_print_statistics (file, "i386 register", reg_hash);
2654}
2655\f
252b5132
RH		 2656#ifdef DEBUG386
2657
ce8a8b2f 2658/* Debugging routines for md_assemble. */
d3ce72d0 2659static void pte (insn_template *);
40fb9820 2660static void pt (i386_operand_type);
e3bb37b5
L		 2661static void pe (expressionS *);
2662static void ps (symbolS *);
252b5132
RH		 2663
2664static void
e3bb37b5 2665pi (char *line, i386_insn *x)
252b5132 2666{
09137c09 2667 unsigned int j;
252b5132
RH		 2668
2669 fprintf (stdout, "%s: template ", line);
2670 pte (&x->tm);
09f131f2
JH		 2671 fprintf (stdout, " address: base %s index %s scale %x\n",
2672 x->base_reg ? x->base_reg->reg_name : "none",
2673 x->index_reg ? x->index_reg->reg_name : "none",
2674 x->log2_scale_factor);
2675 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2676 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2677 fprintf (stdout, " sib: base %x index %x scale %x\n",
2678 x->sib.base, x->sib.index, x->sib.scale);
2679 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2680 (x->rex & REX_W) != 0,
2681 (x->rex & REX_R) != 0,
2682 (x->rex & REX_X) != 0,
2683 (x->rex & REX_B) != 0);
09137c09 2684 for (j = 0; j < x->operands; j++)
252b5132 2685 {
09137c09
SP		 2686 fprintf (stdout, " #%d: ", j + 1);
2687 pt (x->types[j]);
252b5132 2688 fprintf (stdout, "\n");
09137c09
SP		 2689 if (x->types[j].bitfield.reg8
2690 || x->types[j].bitfield.reg16
2691 || x->types[j].bitfield.reg32
2692 || x->types[j].bitfield.reg64
2693 || x->types[j].bitfield.regmmx
2694 || x->types[j].bitfield.regxmm
2695 || x->types[j].bitfield.regymm
43234a1e 2696 || x->types[j].bitfield.regzmm
09137c09
SP		 2697 || x->types[j].bitfield.sreg2
2698 || x->types[j].bitfield.sreg3
2699 || x->types[j].bitfield.control
2700 || x->types[j].bitfield.debug
2701 || x->types[j].bitfield.test)
2702 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2703 if (operand_type_check (x->types[j], imm))
2704 pe (x->op[j].imms);
2705 if (operand_type_check (x->types[j], disp))
2706 pe (x->op[j].disps);
252b5132
RH		 2707 }
2708}
2709
2710static void
d3ce72d0 2711pte (insn_template *t)
252b5132 2712{
09137c09 2713 unsigned int j;
252b5132 2714 fprintf (stdout, " %d operands ", t->operands);
47926f60 2715 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2716 if (t->extension_opcode != None)
2717 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2718 if (t->opcode_modifier.d)
252b5132 2719 fprintf (stdout, "D");
40fb9820 2720 if (t->opcode_modifier.w)
252b5132
RH		 2721 fprintf (stdout, "W");
2722 fprintf (stdout, "\n");
09137c09 2723 for (j = 0; j < t->operands; j++)
252b5132 2724 {
09137c09
SP		 2725 fprintf (stdout, " #%d type ", j + 1);
2726 pt (t->operand_types[j]);
252b5132
RH		 2727 fprintf (stdout, "\n");
2728 }
2729}
2730
2731static void
e3bb37b5 2732pe (expressionS *e)
252b5132 2733{
24eab124 2734 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2735 fprintf (stdout, " add_number %ld (%lx)\n",
2736 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2737 if (e->X_add_symbol)
2738 {
2739 fprintf (stdout, " add_symbol ");
2740 ps (e->X_add_symbol);
2741 fprintf (stdout, "\n");
2742 }
2743 if (e->X_op_symbol)
2744 {
2745 fprintf (stdout, " op_symbol ");
2746 ps (e->X_op_symbol);
2747 fprintf (stdout, "\n");
2748 }
2749}
2750
2751static void
e3bb37b5 2752ps (symbolS *s)
252b5132
RH		 2753{
2754 fprintf (stdout, "%s type %s%s",
2755 S_GET_NAME (s),
2756 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2757 segment_name (S_GET_SEGMENT (s)));
2758}
2759
7b81dfbb 2760static struct type_name
252b5132 2761 {
40fb9820
L		 2762 i386_operand_type mask;
2763 const char *name;
252b5132 2764 }
7b81dfbb 2765const type_names[] =
252b5132 2766{
40fb9820
L		 2767 { OPERAND_TYPE_REG8, "r8" },
2768 { OPERAND_TYPE_REG16, "r16" },
2769 { OPERAND_TYPE_REG32, "r32" },
2770 { OPERAND_TYPE_REG64, "r64" },
2771 { OPERAND_TYPE_IMM8, "i8" },
2772 { OPERAND_TYPE_IMM8, "i8s" },
2773 { OPERAND_TYPE_IMM16, "i16" },
2774 { OPERAND_TYPE_IMM32, "i32" },
2775 { OPERAND_TYPE_IMM32S, "i32s" },
2776 { OPERAND_TYPE_IMM64, "i64" },
2777 { OPERAND_TYPE_IMM1, "i1" },
2778 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2779 { OPERAND_TYPE_DISP8, "d8" },
2780 { OPERAND_TYPE_DISP16, "d16" },
2781 { OPERAND_TYPE_DISP32, "d32" },
2782 { OPERAND_TYPE_DISP32S, "d32s" },
2783 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2784 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2785 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2786 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2787 { OPERAND_TYPE_CONTROL, "control reg" },
2788 { OPERAND_TYPE_TEST, "test reg" },
2789 { OPERAND_TYPE_DEBUG, "debug reg" },
2790 { OPERAND_TYPE_FLOATREG, "FReg" },
2791 { OPERAND_TYPE_FLOATACC, "FAcc" },
2792 { OPERAND_TYPE_SREG2, "SReg2" },
2793 { OPERAND_TYPE_SREG3, "SReg3" },
2794 { OPERAND_TYPE_ACC, "Acc" },
2795 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2796 { OPERAND_TYPE_REGMMX, "rMMX" },
2797 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2798 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2799 { OPERAND_TYPE_REGZMM, "rZMM" },
2800 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2801 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2802};
2803
2804static void
40fb9820 2805pt (i386_operand_type t)
252b5132 2806{
40fb9820 2807 unsigned int j;
c6fb90c8 2808 i386_operand_type a;
252b5132 2809
40fb9820 2810 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2811 {
2812 a = operand_type_and (t, type_names[j].mask);
0349dc08 2813 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2814 fprintf (stdout, "%s, ", type_names[j].name);
2815 }
252b5132
RH		 2816 fflush (stdout);
2817}
2818
2819#endif /* DEBUG386 */
2820\f
252b5132 2821static bfd_reloc_code_real_type
3956db08 2822reloc (unsigned int size,
64e74474
AM		 2823 int pcrel,
2824 int sign,
c3320543 2825 int bnd_prefix,
64e74474 2826 bfd_reloc_code_real_type other)
252b5132 2827{
47926f60 2828 if (other != NO_RELOC)
3956db08 2829 {
91d6fa6a 2830 reloc_howto_type *rel;
3956db08
JB		 2831
2832 if (size == 8)
2833 switch (other)
2834 {
64e74474
AM		 2835 case BFD_RELOC_X86_64_GOT32:
2836 return BFD_RELOC_X86_64_GOT64;
2837 break;
2838 case BFD_RELOC_X86_64_PLTOFF64:
2839 return BFD_RELOC_X86_64_PLTOFF64;
2840 break;
2841 case BFD_RELOC_X86_64_GOTPC32:
2842 other = BFD_RELOC_X86_64_GOTPC64;
2843 break;
2844 case BFD_RELOC_X86_64_GOTPCREL:
2845 other = BFD_RELOC_X86_64_GOTPCREL64;
2846 break;
2847 case BFD_RELOC_X86_64_TPOFF32:
2848 other = BFD_RELOC_X86_64_TPOFF64;
2849 break;
2850 case BFD_RELOC_X86_64_DTPOFF32:
2851 other = BFD_RELOC_X86_64_DTPOFF64;
2852 break;
2853 default:
2854 break;
3956db08 2855 }
e05278af 2856
8ce3d284 2857#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2858 if (other == BFD_RELOC_SIZE32)
2859 {
2860 if (size == 8)
1ab668bf 2861 other = BFD_RELOC_SIZE64;
8fd4256d 2862 if (pcrel)
1ab668bf
AM		 2863 {
2864 as_bad (_("there are no pc-relative size relocations"));
2865 return NO_RELOC;
2866 }
8fd4256d 2867 }
8ce3d284 2868#endif
8fd4256d 2869
e05278af 2870 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2871 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2872 sign = -1;
2873
91d6fa6a
NC		 2874 rel = bfd_reloc_type_lookup (stdoutput, other);
2875 if (!rel)
3956db08 2876 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2877 else if (size != bfd_get_reloc_size (rel))
3956db08 2878 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2879 bfd_get_reloc_size (rel),
3956db08 2880 size);
91d6fa6a 2881 else if (pcrel && !rel->pc_relative)
3956db08 2882 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2883 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2884 && !sign)
91d6fa6a 2885 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2886 && sign > 0))
3956db08
JB		 2887 as_bad (_("relocated field and relocation type differ in signedness"));
2888 else
2889 return other;
2890 return NO_RELOC;
2891 }
252b5132
RH		 2892
2893 if (pcrel)
2894 {
3e73aa7c 2895 if (!sign)
3956db08 2896 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2897 switch (size)
2898 {
2899 case 1: return BFD_RELOC_8_PCREL;
2900 case 2: return BFD_RELOC_16_PCREL;
c3320543
L		 2901 case 4: return (bnd_prefix && object_64bit
2902 ? BFD_RELOC_X86_64_PC32_BND
2903 : BFD_RELOC_32_PCREL);
d6ab8113 2904 case 8: return BFD_RELOC_64_PCREL;
252b5132 2905 }
3956db08 2906 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2907 }
2908 else
2909 {
3956db08 2910 if (sign > 0)
e5cb08ac 2911 switch (size)
3e73aa7c
JH		 2912 {
2913 case 4: return BFD_RELOC_X86_64_32S;
2914 }
2915 else
2916 switch (size)
2917 {
2918 case 1: return BFD_RELOC_8;
2919 case 2: return BFD_RELOC_16;
2920 case 4: return BFD_RELOC_32;
2921 case 8: return BFD_RELOC_64;
2922 }
3956db08
JB		 2923 as_bad (_("cannot do %s %u byte relocation"),
2924 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2925 }
2926
0cc9e1d3 2927 return NO_RELOC;
252b5132
RH		 2928}
2929
47926f60
KH		 2930/* Here we decide which fixups can be adjusted to make them relative to
2931 the beginning of the section instead of the symbol. Basically we need
2932 to make sure that the dynamic relocations are done correctly, so in
2933 some cases we force the original symbol to be used. */
2934
252b5132 2935int
e3bb37b5 2936tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2937{
6d249963 2938#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2939 if (!IS_ELF)
31312f95
AM		 2940 return 1;
2941
a161fe53
AM		 2942 /* Don't adjust pc-relative references to merge sections in 64-bit
2943 mode. */
2944 if (use_rela_relocations
2945 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2946 && fixP->fx_pcrel)
252b5132 2947 return 0;
31312f95 2948
8d01d9a9
AJ		 2949 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2950 and changed later by validate_fix. */
2951 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2952 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2953 return 0;
2954
8fd4256d
L		 2955 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2956 for size relocations. */
2957 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2958 || fixP->fx_r_type == BFD_RELOC_SIZE64
2959 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2960 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2961 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2962 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2963 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2964 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2965 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2966 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2967 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2968 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2969 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2970 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2971 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2972 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2973 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2974 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2975 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2976 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2977 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2978 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2979 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2980 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2981 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2982 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2983 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2984 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2985 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2986 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2987 return 0;
31312f95 2988#endif
252b5132
RH		 2989 return 1;
2990}
252b5132 2991
b4cac588 2992static int
e3bb37b5 2993intel_float_operand (const char *mnemonic)
252b5132 2994{
9306ca4a
JB		 2995 /* Note that the value returned is meaningful only for opcodes with (memory)
2996 operands, hence the code here is free to improperly handle opcodes that
2997 have no operands (for better performance and smaller code). */
2998
2999 if (mnemonic[0] != 'f')
3000 return 0; /* non-math */
3001
3002 switch (mnemonic[1])
3003 {
3004 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3005 the fs segment override prefix not currently handled because no
3006 call path can make opcodes without operands get here */
3007 case 'i':
3008 return 2 /* integer op */;
3009 case 'l':
3010 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3011 return 3; /* fldcw/fldenv */
3012 break;
3013 case 'n':
3014 if (mnemonic[2] != 'o' /* fnop */)
3015 return 3; /* non-waiting control op */
3016 break;
3017 case 'r':
3018 if (mnemonic[2] == 's')
3019 return 3; /* frstor/frstpm */
3020 break;
3021 case 's':
3022 if (mnemonic[2] == 'a')
3023 return 3; /* fsave */
3024 if (mnemonic[2] == 't')
3025 {
3026 switch (mnemonic[3])
3027 {
3028 case 'c': /* fstcw */
3029 case 'd': /* fstdw */
3030 case 'e': /* fstenv */
3031 case 's': /* fsts[gw] */
3032 return 3;
3033 }
3034 }
3035 break;
3036 case 'x':
3037 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3038 return 0; /* fxsave/fxrstor are not really math ops */
3039 break;
3040 }
252b5132 3041
9306ca4a 3042 return 1;
252b5132
RH		 3043}
3044
c0f3af97
L		 3045/* Build the VEX prefix. */
3046
3047static void
d3ce72d0 3048build_vex_prefix (const insn_template *t)
c0f3af97
L		 3049{
3050 unsigned int register_specifier;
3051 unsigned int implied_prefix;
3052 unsigned int vector_length;
3053
3054 /* Check register specifier. */
3055 if (i.vex.register_specifier)
43234a1e
L		 3056 {
3057 register_specifier =
3058 ~register_number (i.vex.register_specifier) & 0xf;
3059 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3060 }
c0f3af97
L		 3061 else
3062 register_specifier = 0xf;
3063
fa99fab2
L		 3064 /* Use 2-byte VEX prefix by swappping destination and source
3065 operand. */
3066 if (!i.swap_operand
3067 && i.operands == i.reg_operands
7f399153 3068 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3069 && i.tm.opcode_modifier.s
3070 && i.rex == REX_B)
3071 {
3072 unsigned int xchg = i.operands - 1;
3073 union i386_op temp_op;
3074 i386_operand_type temp_type;
3075
3076 temp_type = i.types[xchg];
3077 i.types[xchg] = i.types[0];
3078 i.types[0] = temp_type;
3079 temp_op = i.op[xchg];
3080 i.op[xchg] = i.op[0];
3081 i.op[0] = temp_op;
3082
9c2799c2 3083 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3084
3085 i.rex = REX_R;
3086 xchg = i.rm.regmem;
3087 i.rm.regmem = i.rm.reg;
3088 i.rm.reg = xchg;
3089
3090 /* Use the next insn. */
3091 i.tm = t[1];
3092 }
3093
539f890d
L		 3094 if (i.tm.opcode_modifier.vex == VEXScalar)
3095 vector_length = avxscalar;
3096 else
3097 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3098
3099 switch ((i.tm.base_opcode >> 8) & 0xff)
3100 {
3101 case 0:
3102 implied_prefix = 0;
3103 break;
3104 case DATA_PREFIX_OPCODE:
3105 implied_prefix = 1;
3106 break;
3107 case REPE_PREFIX_OPCODE:
3108 implied_prefix = 2;
3109 break;
3110 case REPNE_PREFIX_OPCODE:
3111 implied_prefix = 3;
3112 break;
3113 default:
3114 abort ();
3115 }
3116
3117 /* Use 2-byte VEX prefix if possible. */
7f399153 3118 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3119 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3120 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3121 {
3122 /* 2-byte VEX prefix. */
3123 unsigned int r;
3124
3125 i.vex.length = 2;
3126 i.vex.bytes[0] = 0xc5;
3127
3128 /* Check the REX.R bit. */
3129 r = (i.rex & REX_R) ? 0 : 1;
3130 i.vex.bytes[1] = (r << 7
3131 | register_specifier << 3
3132 | vector_length << 2
3133 | implied_prefix);
3134 }
3135 else
3136 {
3137 /* 3-byte VEX prefix. */
3138 unsigned int m, w;
3139
f88c9eb0 3140 i.vex.length = 3;
f88c9eb0 3141
7f399153 3142 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3143 {
7f399153
L		 3144 case VEX0F:
3145 m = 0x1;
80de6e00 3146 i.vex.bytes[0] = 0xc4;
7f399153
L		 3147 break;
3148 case VEX0F38:
3149 m = 0x2;
80de6e00 3150 i.vex.bytes[0] = 0xc4;
7f399153
L		 3151 break;
3152 case VEX0F3A:
3153 m = 0x3;
80de6e00 3154 i.vex.bytes[0] = 0xc4;
7f399153
L		 3155 break;
3156 case XOP08:
5dd85c99
SP		 3157 m = 0x8;
3158 i.vex.bytes[0] = 0x8f;
7f399153
L		 3159 break;
3160 case XOP09:
f88c9eb0
SP		 3161 m = 0x9;
3162 i.vex.bytes[0] = 0x8f;
7f399153
L		 3163 break;
3164 case XOP0A:
f88c9eb0
SP		 3165 m = 0xa;
3166 i.vex.bytes[0] = 0x8f;
7f399153
L		 3167 break;
3168 default:
3169 abort ();
f88c9eb0 3170 }
c0f3af97 3171
c0f3af97
L		 3172 /* The high 3 bits of the second VEX byte are 1's compliment
3173 of RXB bits from REX. */
3174 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3175
3176 /* Check the REX.W bit. */
3177 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3178 if (i.tm.opcode_modifier.vexw == VEXW1)
3179 w = 1;
c0f3af97
L		 3180
3181 i.vex.bytes[2] = (w << 7
3182 | register_specifier << 3
3183 | vector_length << 2
3184 | implied_prefix);
3185 }
3186}
3187
43234a1e
L		 3188/* Build the EVEX prefix. */
3189
3190static void
3191build_evex_prefix (void)
3192{
3193 unsigned int register_specifier;
3194 unsigned int implied_prefix;
3195 unsigned int m, w;
3196 rex_byte vrex_used = 0;
3197
3198 /* Check register specifier. */
3199 if (i.vex.register_specifier)
3200 {
3201 gas_assert ((i.vrex & REX_X) == 0);
3202
3203 register_specifier = i.vex.register_specifier->reg_num;
3204 if ((i.vex.register_specifier->reg_flags & RegRex))
3205 register_specifier += 8;
3206 /* The upper 16 registers are encoded in the fourth byte of the
3207 EVEX prefix. */
3208 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3209 i.vex.bytes[3] = 0x8;
3210 register_specifier = ~register_specifier & 0xf;
3211 }
3212 else
3213 {
3214 register_specifier = 0xf;
3215
3216 /* Encode upper 16 vector index register in the fourth byte of
3217 the EVEX prefix. */
3218 if (!(i.vrex & REX_X))
3219 i.vex.bytes[3] = 0x8;
3220 else
3221 vrex_used |= REX_X;
3222 }
3223
3224 switch ((i.tm.base_opcode >> 8) & 0xff)
3225 {
3226 case 0:
3227 implied_prefix = 0;
3228 break;
3229 case DATA_PREFIX_OPCODE:
3230 implied_prefix = 1;
3231 break;
3232 case REPE_PREFIX_OPCODE:
3233 implied_prefix = 2;
3234 break;
3235 case REPNE_PREFIX_OPCODE:
3236 implied_prefix = 3;
3237 break;
3238 default:
3239 abort ();
3240 }
3241
3242 /* 4 byte EVEX prefix. */
3243 i.vex.length = 4;
3244 i.vex.bytes[0] = 0x62;
3245
3246 /* mmmm bits. */
3247 switch (i.tm.opcode_modifier.vexopcode)
3248 {
3249 case VEX0F:
3250 m = 1;
3251 break;
3252 case VEX0F38:
3253 m = 2;
3254 break;
3255 case VEX0F3A:
3256 m = 3;
3257 break;
3258 default:
3259 abort ();
3260 break;
3261 }
3262
3263 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3264 bits from REX. */
3265 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3266
3267 /* The fifth bit of the second EVEX byte is 1's compliment of the
3268 REX_R bit in VREX. */
3269 if (!(i.vrex & REX_R))
3270 i.vex.bytes[1] |= 0x10;
3271 else
3272 vrex_used |= REX_R;
3273
3274 if ((i.reg_operands + i.imm_operands) == i.operands)
3275 {
3276 /* When all operands are registers, the REX_X bit in REX is not
3277 used. We reuse it to encode the upper 16 registers, which is
3278 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3279 as 1's compliment. */
3280 if ((i.vrex & REX_B))
3281 {
3282 vrex_used |= REX_B;
3283 i.vex.bytes[1] &= ~0x40;
3284 }
3285 }
3286
3287 /* EVEX instructions shouldn't need the REX prefix. */
3288 i.vrex &= ~vrex_used;
3289 gas_assert (i.vrex == 0);
3290
3291 /* Check the REX.W bit. */
3292 w = (i.rex & REX_W) ? 1 : 0;
3293 if (i.tm.opcode_modifier.vexw)
3294 {
3295 if (i.tm.opcode_modifier.vexw == VEXW1)
3296 w = 1;
3297 }
3298 /* If w is not set it means we are dealing with WIG instruction. */
3299 else if (!w)
3300 {
3301 if (evexwig == evexw1)
3302 w = 1;
3303 }
3304
3305 /* Encode the U bit. */
3306 implied_prefix |= 0x4;
3307
3308 /* The third byte of the EVEX prefix. */
3309 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3310
3311 /* The fourth byte of the EVEX prefix. */
3312 /* The zeroing-masking bit. */
3313 if (i.mask && i.mask->zeroing)
3314 i.vex.bytes[3] |= 0x80;
3315
3316 /* Don't always set the broadcast bit if there is no RC. */
3317 if (!i.rounding)
3318 {
3319 /* Encode the vector length. */
3320 unsigned int vec_length;
3321
3322 switch (i.tm.opcode_modifier.evex)
3323 {
3324 case EVEXLIG: /* LL' is ignored */
3325 vec_length = evexlig << 5;
3326 break;
3327 case EVEX128:
3328 vec_length = 0 << 5;
3329 break;
3330 case EVEX256:
3331 vec_length = 1 << 5;
3332 break;
3333 case EVEX512:
3334 vec_length = 2 << 5;
3335 break;
3336 default:
3337 abort ();
3338 break;
3339 }
3340 i.vex.bytes[3] |= vec_length;
3341 /* Encode the broadcast bit. */
3342 if (i.broadcast)
3343 i.vex.bytes[3] |= 0x10;
3344 }
3345 else
3346 {
3347 if (i.rounding->type != saeonly)
3348 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3349 else
d3d3c6db 3350 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3351 }
3352
3353 if (i.mask && i.mask->mask)
3354 i.vex.bytes[3] |= i.mask->mask->reg_num;
3355}
3356
65da13b5
L		 3357static void
3358process_immext (void)
3359{
3360 expressionS *exp;
3361
4c692bc7
JB		 3362 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3363 && i.operands > 0)
65da13b5 3364 {
4c692bc7
JB		 3365 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3366 with an opcode suffix which is coded in the same place as an
3367 8-bit immediate field would be.
3368 Here we check those operands and remove them afterwards. */
65da13b5
L		 3369 unsigned int x;
3370
3371 for (x = 0; x < i.operands; x++)
4c692bc7 3372 if (register_number (i.op[x].regs) != x)
65da13b5 3373 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3374 register_prefix, i.op[x].regs->reg_name, x + 1,
3375 i.tm.name);
3376
3377 i.operands = 0;
65da13b5
L		 3378 }
3379
c0f3af97 3380 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3381 which is coded in the same place as an 8-bit immediate field
3382 would be. Here we fake an 8-bit immediate operand from the
3383 opcode suffix stored in tm.extension_opcode.
3384
c1e679ec 3385 AVX instructions also use this encoding, for some of
c0f3af97 3386 3 argument instructions. */
65da13b5 3387
43234a1e 3388 gas_assert (i.imm_operands <= 1
7ab9ffdd 3389 && (i.operands <= 2
43234a1e
L		 3390 || ((i.tm.opcode_modifier.vex
3391 || i.tm.opcode_modifier.evex)
7ab9ffdd 3392 && i.operands <= 4)));
65da13b5
L		 3393
3394 exp = &im_expressions[i.imm_operands++];
3395 i.op[i.operands].imms = exp;
3396 i.types[i.operands] = imm8;
3397 i.operands++;
3398 exp->X_op = O_constant;
3399 exp->X_add_number = i.tm.extension_opcode;
3400 i.tm.extension_opcode = None;
3401}
3402
42164a71
L		 3403
3404static int
3405check_hle (void)
3406{
3407 switch (i.tm.opcode_modifier.hleprefixok)
3408 {
3409 default:
3410 abort ();
82c2def5 3411 case HLEPrefixNone:
165de32a
L		 3412 as_bad (_("invalid instruction `%s' after `%s'"),
3413 i.tm.name, i.hle_prefix);
42164a71 3414 return 0;
82c2def5 3415 case HLEPrefixLock:
42164a71
L		 3416 if (i.prefix[LOCK_PREFIX])
3417 return 1;
165de32a 3418 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3419 return 0;
82c2def5 3420 case HLEPrefixAny:
42164a71 3421 return 1;
82c2def5 3422 case HLEPrefixRelease:
42164a71
L		 3423 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3424 {
3425 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3426 i.tm.name);
3427 return 0;
3428 }
3429 if (i.mem_operands == 0
3430 || !operand_type_check (i.types[i.operands - 1], anymem))
3431 {
3432 as_bad (_("memory destination needed for instruction `%s'"
3433 " after `xrelease'"), i.tm.name);
3434 return 0;
3435 }
3436 return 1;
3437 }
3438}
3439
252b5132
RH		 3440/* This is the guts of the machine-dependent assembler. LINE points to a
3441 machine dependent instruction. This function is supposed to emit
3442 the frags/bytes it assembles to. */
3443
3444void
65da13b5 3445md_assemble (char *line)
252b5132 3446{
40fb9820 3447 unsigned int j;
252b5132 3448 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3449 const insn_template *t;
252b5132 3450
47926f60 3451 /* Initialize globals. */
252b5132
RH		 3452 memset (&i, '\0', sizeof (i));
3453 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3454 i.reloc[j] = NO_RELOC;
252b5132
RH		 3455 memset (disp_expressions, '\0', sizeof (disp_expressions));
3456 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3457 save_stack_p = save_stack;
252b5132
RH		 3458
3459 /* First parse an instruction mnemonic & call i386_operand for the operands.
3460 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3461 start of a (possibly prefixed) mnemonic. */
252b5132 3462
29b0f896
AM		 3463 line = parse_insn (line, mnemonic);
3464 if (line == NULL)
3465 return;
252b5132 3466
29b0f896 3467 line = parse_operands (line, mnemonic);
ee86248c 3468 this_operand = -1;
29b0f896
AM		 3469 if (line == NULL)
3470 return;
252b5132 3471
29b0f896
AM		 3472 /* Now we've parsed the mnemonic into a set of templates, and have the
3473 operands at hand. */
3474
3475 /* All intel opcodes have reversed operands except for "bound" and
3476 "enter". We also don't reverse intersegment "jmp" and "call"
3477 instructions with 2 immediate operands so that the immediate segment
050dfa73 3478 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3479 if (intel_syntax
3480 && i.operands > 1
29b0f896 3481 && (strcmp (mnemonic, "bound") != 0)
30123838 3482 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3483 && !(operand_type_check (i.types[0], imm)
3484 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3485 swap_operands ();
3486
ec56d5c0
JB		 3487 /* The order of the immediates should be reversed
3488 for 2 immediates extrq and insertq instructions */
3489 if (i.imm_operands == 2
3490 && (strcmp (mnemonic, "extrq") == 0
3491 || strcmp (mnemonic, "insertq") == 0))
3492 swap_2_operands (0, 1);
3493
29b0f896
AM		 3494 if (i.imm_operands)
3495 optimize_imm ();
3496
b300c311
L		 3497 /* Don't optimize displacement for movabs since it only takes 64bit
3498 displacement. */
3499 if (i.disp_operands
a501d77e 3500 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3501 && (flag_code != CODE_64BIT
3502 || strcmp (mnemonic, "movabs") != 0))
3503 optimize_disp ();
29b0f896
AM		 3504
3505 /* Next, we find a template that matches the given insn,
3506 making sure the overlap of the given operands types is consistent
3507 with the template operand types. */
252b5132 3508
fa99fab2 3509 if (!(t = match_template ()))
29b0f896 3510 return;
252b5132 3511
7bab8ab5 3512 if (sse_check != check_none
81f8a913 3513 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3514 && (i.tm.cpu_flags.bitfield.cpusse
3515 || i.tm.cpu_flags.bitfield.cpusse2
3516 || i.tm.cpu_flags.bitfield.cpusse3
3517 || i.tm.cpu_flags.bitfield.cpussse3
3518 || i.tm.cpu_flags.bitfield.cpusse4_1
3519 || i.tm.cpu_flags.bitfield.cpusse4_2))
3520 {
7bab8ab5 3521 (sse_check == check_warning
daf50ae7
L		 3522 ? as_warn
3523 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3524 }
3525
321fd21e
L		 3526 /* Zap movzx and movsx suffix. The suffix has been set from
3527 "word ptr" or "byte ptr" on the source operand in Intel syntax
3528 or extracted from mnemonic in AT&T syntax. But we'll use
3529 the destination register to choose the suffix for encoding. */
3530 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3531 {
321fd21e
L		 3532 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3533 there is no suffix, the default will be byte extension. */
3534 if (i.reg_operands != 2
3535 && !i.suffix
7ab9ffdd 3536 && intel_syntax)
321fd21e
L		 3537 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3538
3539 i.suffix = 0;
cd61ebfe 3540 }
24eab124 3541
40fb9820 3542 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3543 if (!add_prefix (FWAIT_OPCODE))
3544 return;
252b5132 3545
d5de92cf
L		 3546 /* Check if REP prefix is OK. */
3547 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3548 {
3549 as_bad (_("invalid instruction `%s' after `%s'"),
3550 i.tm.name, i.rep_prefix);
3551 return;
3552 }
3553
c1ba0266
L		 3554 /* Check for lock without a lockable instruction. Destination operand
3555 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3556 if (i.prefix[LOCK_PREFIX]
3557 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3558 || i.mem_operands == 0
3559 || (i.tm.base_opcode != 0x86
3560 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3561 {
3562 as_bad (_("expecting lockable instruction after `lock'"));
3563 return;
3564 }
3565
42164a71 3566 /* Check if HLE prefix is OK. */
165de32a 3567 if (i.hle_prefix && !check_hle ())
42164a71
L		 3568 return;
3569
7e8b059b
L		 3570 /* Check BND prefix. */
3571 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3572 as_bad (_("expecting valid branch instruction after `bnd'"));
3573
3574 if (i.tm.cpu_flags.bitfield.cpumpx
3575 && flag_code == CODE_64BIT
3576 && i.prefix[ADDR_PREFIX])
3577 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3578
3579 /* Insert BND prefix. */
3580 if (add_bnd_prefix
3581 && i.tm.opcode_modifier.bndprefixok
3582 && !i.prefix[BND_PREFIX])
3583 add_prefix (BND_PREFIX_OPCODE);
3584
29b0f896 3585 /* Check string instruction segment overrides. */
40fb9820 3586 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3587 {
3588 if (!check_string ())
5dd0794d 3589 return;
fc0763e6 3590 i.disp_operands = 0;
29b0f896 3591 }
5dd0794d 3592
29b0f896
AM		 3593 if (!process_suffix ())
3594 return;
e413e4e9 3595
bc0844ae
L		 3596 /* Update operand types. */
3597 for (j = 0; j < i.operands; j++)
3598 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3599
29b0f896
AM		 3600 /* Make still unresolved immediate matches conform to size of immediate
3601 given in i.suffix. */
3602 if (!finalize_imm ())
3603 return;
252b5132 3604
40fb9820 3605 if (i.types[0].bitfield.imm1)
29b0f896 3606 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3607
9afe6eb8
L		 3608 /* We only need to check those implicit registers for instructions
3609 with 3 operands or less. */
3610 if (i.operands <= 3)
3611 for (j = 0; j < i.operands; j++)
3612 if (i.types[j].bitfield.inoutportreg
3613 || i.types[j].bitfield.shiftcount
3614 || i.types[j].bitfield.acc
3615 || i.types[j].bitfield.floatacc)
3616 i.reg_operands--;
40fb9820 3617
c0f3af97
L		 3618 /* ImmExt should be processed after SSE2AVX. */
3619 if (!i.tm.opcode_modifier.sse2avx
3620 && i.tm.opcode_modifier.immext)
65da13b5 3621 process_immext ();
252b5132 3622
29b0f896
AM		 3623 /* For insns with operands there are more diddles to do to the opcode. */
3624 if (i.operands)
3625 {
3626 if (!process_operands ())
3627 return;
3628 }
40fb9820 3629 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3630 {
3631 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3632 as_warn (_("translating to `%sp'"), i.tm.name);
3633 }
252b5132 3634
9e5e5283
L		 3635 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3636 {
3637 if (flag_code == CODE_16BIT)
3638 {
3639 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3640 i.tm.name);
3641 return;
3642 }
c0f3af97 3643
9e5e5283
L		 3644 if (i.tm.opcode_modifier.vex)
3645 build_vex_prefix (t);
3646 else
3647 build_evex_prefix ();
3648 }
43234a1e 3649
5dd85c99
SP		 3650 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3651 instructions may define INT_OPCODE as well, so avoid this corner
3652 case for those instructions that use MODRM. */
3653 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3654 && !i.tm.opcode_modifier.modrm
3655 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3656 {
3657 i.tm.base_opcode = INT3_OPCODE;
3658 i.imm_operands = 0;
3659 }
252b5132 3660
40fb9820
L		 3661 if ((i.tm.opcode_modifier.jump
3662 || i.tm.opcode_modifier.jumpbyte
3663 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3664 && i.op[0].disps->X_op == O_constant)
3665 {
3666 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3667 the absolute address given by the constant. Since ix86 jumps and
3668 calls are pc relative, we need to generate a reloc. */
3669 i.op[0].disps->X_add_symbol = &abs_symbol;
3670 i.op[0].disps->X_op = O_symbol;
3671 }
252b5132 3672
40fb9820 3673 if (i.tm.opcode_modifier.rex64)
161a04f6 3674 i.rex |= REX_W;
252b5132 3675
29b0f896
AM		 3676 /* For 8 bit registers we need an empty rex prefix. Also if the
3677 instruction already has a prefix, we need to convert old
3678 registers to new ones. */
773f551c 3679
40fb9820 3680 if ((i.types[0].bitfield.reg8
29b0f896 3681 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3682 || (i.types[1].bitfield.reg8
29b0f896 3683 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3684 || ((i.types[0].bitfield.reg8
3685 || i.types[1].bitfield.reg8)
29b0f896
AM		 3686 && i.rex != 0))
3687 {
3688 int x;
726c5dcd 3689
29b0f896
AM		 3690 i.rex |= REX_OPCODE;
3691 for (x = 0; x < 2; x++)
3692 {
3693 /* Look for 8 bit operand that uses old registers. */
40fb9820 3694 if (i.types[x].bitfield.reg8
29b0f896 3695 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3696 {
29b0f896
AM		 3697 /* In case it is "hi" register, give up. */
3698 if (i.op[x].regs->reg_num > 3)
a540244d 3699 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3700 "instruction requiring REX prefix."),
a540244d 3701 register_prefix, i.op[x].regs->reg_name);
773f551c 3702
29b0f896
AM		 3703 /* Otherwise it is equivalent to the extended register.
3704 Since the encoding doesn't change this is merely
3705 cosmetic cleanup for debug output. */
3706
3707 i.op[x].regs = i.op[x].regs + 8;
773f551c 3708 }
29b0f896
AM		 3709 }
3710 }
773f551c 3711
7ab9ffdd 3712 if (i.rex != 0)
29b0f896
AM		 3713 add_prefix (REX_OPCODE | i.rex);
3714
3715 /* We are ready to output the insn. */
3716 output_insn ();
3717}
3718
3719static char *
e3bb37b5 3720parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3721{
3722 char *l = line;
3723 char *token_start = l;
3724 char *mnem_p;
5c6af06e 3725 int supported;
d3ce72d0 3726 const insn_template *t;
b6169b20 3727 char *dot_p = NULL;
29b0f896 3728
29b0f896
AM		 3729 while (1)
3730 {
3731 mnem_p = mnemonic;
3732 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3733 {
b6169b20
L		 3734 if (*mnem_p == '.')
3735 dot_p = mnem_p;
29b0f896
AM		 3736 mnem_p++;
3737 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3738 {
29b0f896
AM		 3739 as_bad (_("no such instruction: `%s'"), token_start);
3740 return NULL;
3741 }
3742 l++;
3743 }
3744 if (!is_space_char (*l)
3745 && *l != END_OF_INSN
e44823cf
JB		 3746 && (intel_syntax
3747 || (*l != PREFIX_SEPARATOR
3748 && *l != ',')))
29b0f896
AM		 3749 {
3750 as_bad (_("invalid character %s in mnemonic"),
3751 output_invalid (*l));
3752 return NULL;
3753 }
3754 if (token_start == l)
3755 {
e44823cf 3756 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3757 as_bad (_("expecting prefix; got nothing"));
3758 else
3759 as_bad (_("expecting mnemonic; got nothing"));
3760 return NULL;
3761 }
45288df1 3762
29b0f896 3763 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3764 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3765
29b0f896
AM		 3766 if (*l != END_OF_INSN
3767 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3768 && current_templates
40fb9820 3769 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3770 {
c6fb90c8 3771 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3772 {
3773 as_bad ((flag_code != CODE_64BIT
3774 ? _("`%s' is only supported in 64-bit mode")
3775 : _("`%s' is not supported in 64-bit mode")),
3776 current_templates->start->name);
3777 return NULL;
3778 }
29b0f896
AM		 3779 /* If we are in 16-bit mode, do not allow addr16 or data16.
3780 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3781 if ((current_templates->start->opcode_modifier.size16
3782 || current_templates->start->opcode_modifier.size32)
29b0f896 3783 && flag_code != CODE_64BIT
40fb9820 3784 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3785 ^ (flag_code == CODE_16BIT)))
3786 {
3787 as_bad (_("redundant %s prefix"),
3788 current_templates->start->name);
3789 return NULL;
45288df1 3790 }
29b0f896
AM		 3791 /* Add prefix, checking for repeated prefixes. */
3792 switch (add_prefix (current_templates->start->base_opcode))
3793 {
c32fa91d 3794 case PREFIX_EXIST:
29b0f896 3795 return NULL;
c32fa91d 3796 case PREFIX_REP:
42164a71 3797 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3798 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3799 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3800 i.bnd_prefix = current_templates->start->name;
42164a71 3801 else
d5de92cf 3802 i.rep_prefix = current_templates->start->name;
29b0f896 3803 break;
c32fa91d
L		 3804 default:
3805 break;
29b0f896
AM		 3806 }
3807 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3808 token_start = ++l;
3809 }
3810 else
3811 break;
3812 }
45288df1 3813
30a55f88 3814 if (!current_templates)
b6169b20 3815 {
f8a5c266
L		 3816 /* Check if we should swap operand or force 32bit displacement in
3817 encoding. */
30a55f88
L		 3818 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3819 i.swap_operand = 1;
8d63c93e 3820 else if (mnem_p - 3 == dot_p
a501d77e
L		 3821 && dot_p[1] == 'd'
3822 && dot_p[2] == '8')
3823 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3824 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3825 && dot_p[1] == 'd'
3826 && dot_p[2] == '3'
3827 && dot_p[3] == '2')
a501d77e 3828 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3829 else
3830 goto check_suffix;
3831 mnem_p = dot_p;
3832 *dot_p = '\0';
d3ce72d0 3833 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3834 }
3835
29b0f896
AM		 3836 if (!current_templates)
3837 {
b6169b20 3838check_suffix:
29b0f896
AM		 3839 /* See if we can get a match by trimming off a suffix. */
3840 switch (mnem_p[-1])
3841 {
3842 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3843 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3844 i.suffix = SHORT_MNEM_SUFFIX;
3845 else
29b0f896
AM		 3846 case BYTE_MNEM_SUFFIX:
3847 case QWORD_MNEM_SUFFIX:
3848 i.suffix = mnem_p[-1];
3849 mnem_p[-1] = '\0';
d3ce72d0
NC		 3850 current_templates = (const templates *) hash_find (op_hash,
3851 mnemonic);
29b0f896
AM		 3852 break;
3853 case SHORT_MNEM_SUFFIX:
3854 case LONG_MNEM_SUFFIX:
3855 if (!intel_syntax)
3856 {
3857 i.suffix = mnem_p[-1];
3858 mnem_p[-1] = '\0';
d3ce72d0
NC		 3859 current_templates = (const templates *) hash_find (op_hash,
3860 mnemonic);
29b0f896
AM		 3861 }
3862 break;
252b5132 3863
29b0f896
AM		 3864 /* Intel Syntax. */
3865 case 'd':
3866 if (intel_syntax)
3867 {
9306ca4a 3868 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3869 i.suffix = SHORT_MNEM_SUFFIX;
3870 else
3871 i.suffix = LONG_MNEM_SUFFIX;
3872 mnem_p[-1] = '\0';
d3ce72d0
NC		 3873 current_templates = (const templates *) hash_find (op_hash,
3874 mnemonic);
29b0f896
AM		 3875 }
3876 break;
3877 }
3878 if (!current_templates)
3879 {
3880 as_bad (_("no such instruction: `%s'"), token_start);
3881 return NULL;
3882 }
3883 }
252b5132 3884
40fb9820
L		 3885 if (current_templates->start->opcode_modifier.jump
3886 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3887 {
3888 /* Check for a branch hint. We allow ",pt" and ",pn" for
3889 predict taken and predict not taken respectively.
3890 I'm not sure that branch hints actually do anything on loop
3891 and jcxz insns (JumpByte) for current Pentium4 chips. They
3892 may work in the future and it doesn't hurt to accept them
3893 now. */
3894 if (l[0] == ',' && l[1] == 'p')
3895 {
3896 if (l[2] == 't')
3897 {
3898 if (!add_prefix (DS_PREFIX_OPCODE))
3899 return NULL;
3900 l += 3;
3901 }
3902 else if (l[2] == 'n')
3903 {
3904 if (!add_prefix (CS_PREFIX_OPCODE))
3905 return NULL;
3906 l += 3;
3907 }
3908 }
3909 }
3910 /* Any other comma loses. */
3911 if (*l == ',')
3912 {
3913 as_bad (_("invalid character %s in mnemonic"),
3914 output_invalid (*l));
3915 return NULL;
3916 }
252b5132 3917
29b0f896 3918 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3919 supported = 0;
3920 for (t = current_templates->start; t < current_templates->end; ++t)
3921 {
c0f3af97
L		 3922 supported |= cpu_flags_match (t);
3923 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3924 goto skip;
5c6af06e 3925 }
3629bb00 3926
c0f3af97 3927 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3928 {
3929 as_bad (flag_code == CODE_64BIT
3930 ? _("`%s' is not supported in 64-bit mode")
3931 : _("`%s' is only supported in 64-bit mode"),
3932 current_templates->start->name);
3933 return NULL;
3934 }
c0f3af97 3935 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3936 {
3629bb00 3937 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3938 current_templates->start->name,
41aacd83 3939 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3940 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3941 return NULL;
29b0f896 3942 }
3629bb00
L		 3943
3944skip:
3945 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3946 && (flag_code != CODE_16BIT))
29b0f896
AM		 3947 {
3948 as_warn (_("use .code16 to ensure correct addressing mode"));
3949 }
252b5132 3950
29b0f896
AM		 3951 return l;
3952}
252b5132 3953
29b0f896 3954static char *
e3bb37b5 3955parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3956{
3957 char *token_start;
3138f287 3958
29b0f896
AM		 3959 /* 1 if operand is pending after ','. */
3960 unsigned int expecting_operand = 0;
252b5132 3961
29b0f896
AM		 3962 /* Non-zero if operand parens not balanced. */
3963 unsigned int paren_not_balanced;
3964
3965 while (*l != END_OF_INSN)
3966 {
3967 /* Skip optional white space before operand. */
3968 if (is_space_char (*l))
3969 ++l;
3970 if (!is_operand_char (*l) && *l != END_OF_INSN)
3971 {
3972 as_bad (_("invalid character %s before operand %d"),
3973 output_invalid (*l),
3974 i.operands + 1);
3975 return NULL;
3976 }
3977 token_start = l; /* after white space */
3978 paren_not_balanced = 0;
3979 while (paren_not_balanced || *l != ',')
3980 {
3981 if (*l == END_OF_INSN)
3982 {
3983 if (paren_not_balanced)
3984 {
3985 if (!intel_syntax)
3986 as_bad (_("unbalanced parenthesis in operand %d."),
3987 i.operands + 1);
3988 else
3989 as_bad (_("unbalanced brackets in operand %d."),
3990 i.operands + 1);
3991 return NULL;
3992 }
3993 else
3994 break; /* we are done */
3995 }
3996 else if (!is_operand_char (*l) && !is_space_char (*l))
3997 {
3998 as_bad (_("invalid character %s in operand %d"),
3999 output_invalid (*l),
4000 i.operands + 1);
4001 return NULL;
4002 }
4003 if (!intel_syntax)
4004 {
4005 if (*l == '(')
4006 ++paren_not_balanced;
4007 if (*l == ')')
4008 --paren_not_balanced;
4009 }
4010 else
4011 {
4012 if (*l == '[')
4013 ++paren_not_balanced;
4014 if (*l == ']')
4015 --paren_not_balanced;
4016 }
4017 l++;
4018 }
4019 if (l != token_start)
4020 { /* Yes, we've read in another operand. */
4021 unsigned int operand_ok;
4022 this_operand = i.operands++;
7d5e4556 4023 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4024 if (i.operands > MAX_OPERANDS)
4025 {
4026 as_bad (_("spurious operands; (%d operands/instruction max)"),
4027 MAX_OPERANDS);
4028 return NULL;
4029 }
4030 /* Now parse operand adding info to 'i' as we go along. */
4031 END_STRING_AND_SAVE (l);
4032
4033 if (intel_syntax)
4034 operand_ok =
4035 i386_intel_operand (token_start,
4036 intel_float_operand (mnemonic));
4037 else
a7619375 4038 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4039
4040 RESTORE_END_STRING (l);
4041 if (!operand_ok)
4042 return NULL;
4043 }
4044 else
4045 {
4046 if (expecting_operand)
4047 {
4048 expecting_operand_after_comma:
4049 as_bad (_("expecting operand after ','; got nothing"));
4050 return NULL;
4051 }
4052 if (*l == ',')
4053 {
4054 as_bad (_("expecting operand before ','; got nothing"));
4055 return NULL;
4056 }
4057 }
7f3f1ea2 4058
29b0f896
AM		 4059 /* Now *l must be either ',' or END_OF_INSN. */
4060 if (*l == ',')
4061 {
4062 if (*++l == END_OF_INSN)
4063 {
4064 /* Just skip it, if it's \n complain. */
4065 goto expecting_operand_after_comma;
4066 }
4067 expecting_operand = 1;
4068 }
4069 }
4070 return l;
4071}
7f3f1ea2 4072
050dfa73 4073static void
4d456e3d 4074swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4075{
4076 union i386_op temp_op;
40fb9820 4077 i386_operand_type temp_type;
050dfa73 4078 enum bfd_reloc_code_real temp_reloc;
4eed87de 4079
050dfa73
MM		 4080 temp_type = i.types[xchg2];
4081 i.types[xchg2] = i.types[xchg1];
4082 i.types[xchg1] = temp_type;
4083 temp_op = i.op[xchg2];
4084 i.op[xchg2] = i.op[xchg1];
4085 i.op[xchg1] = temp_op;
4086 temp_reloc = i.reloc[xchg2];
4087 i.reloc[xchg2] = i.reloc[xchg1];
4088 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4089
4090 if (i.mask)
4091 {
4092 if (i.mask->operand == xchg1)
4093 i.mask->operand = xchg2;
4094 else if (i.mask->operand == xchg2)
4095 i.mask->operand = xchg1;
4096 }
4097 if (i.broadcast)
4098 {
4099 if (i.broadcast->operand == xchg1)
4100 i.broadcast->operand = xchg2;
4101 else if (i.broadcast->operand == xchg2)
4102 i.broadcast->operand = xchg1;
4103 }
4104 if (i.rounding)
4105 {
4106 if (i.rounding->operand == xchg1)
4107 i.rounding->operand = xchg2;
4108 else if (i.rounding->operand == xchg2)
4109 i.rounding->operand = xchg1;
4110 }
050dfa73
MM		 4111}
4112
29b0f896 4113static void
e3bb37b5 4114swap_operands (void)
29b0f896 4115{
b7c61d9a 4116 switch (i.operands)
050dfa73 4117 {
c0f3af97 4118 case 5:
b7c61d9a 4119 case 4:
4d456e3d 4120 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4121 case 3:
4122 case 2:
4d456e3d 4123 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4124 break;
4125 default:
4126 abort ();
29b0f896 4127 }
29b0f896
AM		 4128
4129 if (i.mem_operands == 2)
4130 {
4131 const seg_entry *temp_seg;
4132 temp_seg = i.seg[0];
4133 i.seg[0] = i.seg[1];
4134 i.seg[1] = temp_seg;
4135 }
4136}
252b5132 4137
29b0f896
AM		 4138/* Try to ensure constant immediates are represented in the smallest
4139 opcode possible. */
4140static void
e3bb37b5 4141optimize_imm (void)
29b0f896
AM		 4142{
4143 char guess_suffix = 0;
4144 int op;
252b5132 4145
29b0f896
AM		 4146 if (i.suffix)
4147 guess_suffix = i.suffix;
4148 else if (i.reg_operands)
4149 {
4150 /* Figure out a suffix from the last register operand specified.
4151 We can't do this properly yet, ie. excluding InOutPortReg,
4152 but the following works for instructions with immediates.
4153 In any case, we can't set i.suffix yet. */
4154 for (op = i.operands; --op >= 0;)
40fb9820 4155 if (i.types[op].bitfield.reg8)
7ab9ffdd 4156 {
40fb9820
L		 4157 guess_suffix = BYTE_MNEM_SUFFIX;
4158 break;
4159 }
4160 else if (i.types[op].bitfield.reg16)
252b5132 4161 {
40fb9820
L		 4162 guess_suffix = WORD_MNEM_SUFFIX;
4163 break;
4164 }
4165 else if (i.types[op].bitfield.reg32)
4166 {
4167 guess_suffix = LONG_MNEM_SUFFIX;
4168 break;
4169 }
4170 else if (i.types[op].bitfield.reg64)
4171 {
4172 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4173 break;
252b5132 4174 }
29b0f896
AM		 4175 }
4176 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4177 guess_suffix = WORD_MNEM_SUFFIX;
4178
4179 for (op = i.operands; --op >= 0;)
40fb9820 4180 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4181 {
4182 switch (i.op[op].imms->X_op)
252b5132 4183 {
29b0f896
AM		 4184 case O_constant:
4185 /* If a suffix is given, this operand may be shortened. */
4186 switch (guess_suffix)
252b5132 4187 {
29b0f896 4188 case LONG_MNEM_SUFFIX:
40fb9820
L		 4189 i.types[op].bitfield.imm32 = 1;
4190 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4191 break;
4192 case WORD_MNEM_SUFFIX:
40fb9820
L		 4193 i.types[op].bitfield.imm16 = 1;
4194 i.types[op].bitfield.imm32 = 1;
4195 i.types[op].bitfield.imm32s = 1;
4196 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4197 break;
4198 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4199 i.types[op].bitfield.imm8 = 1;
4200 i.types[op].bitfield.imm8s = 1;
4201 i.types[op].bitfield.imm16 = 1;
4202 i.types[op].bitfield.imm32 = 1;
4203 i.types[op].bitfield.imm32s = 1;
4204 i.types[op].bitfield.imm64 = 1;
29b0f896 4205 break;
252b5132 4206 }
252b5132 4207
29b0f896
AM		 4208 /* If this operand is at most 16 bits, convert it
4209 to a signed 16 bit number before trying to see
4210 whether it will fit in an even smaller size.
4211 This allows a 16-bit operand such as $0xffe0 to
4212 be recognised as within Imm8S range. */
40fb9820 4213 if ((i.types[op].bitfield.imm16)
29b0f896 4214 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4215 {
29b0f896
AM		 4216 i.op[op].imms->X_add_number =
4217 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4218 }
40fb9820 4219 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4220 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4221 == 0))
4222 {
4223 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4224 ^ ((offsetT) 1 << 31))
4225 - ((offsetT) 1 << 31));
4226 }
40fb9820 4227 i.types[op]
c6fb90c8
L		 4228 = operand_type_or (i.types[op],
4229 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4230
29b0f896
AM		 4231 /* We must avoid matching of Imm32 templates when 64bit
4232 only immediate is available. */
4233 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4234 i.types[op].bitfield.imm32 = 0;
29b0f896 4235 break;
252b5132 4236
29b0f896
AM		 4237 case O_absent:
4238 case O_register:
4239 abort ();
4240
4241 /* Symbols and expressions. */
4242 default:
9cd96992
JB		 4243 /* Convert symbolic operand to proper sizes for matching, but don't
4244 prevent matching a set of insns that only supports sizes other
4245 than those matching the insn suffix. */
4246 {
40fb9820 4247 i386_operand_type mask, allowed;
d3ce72d0 4248 const insn_template *t;
9cd96992 4249
0dfbf9d7
L		 4250 operand_type_set (&mask, 0);
4251 operand_type_set (&allowed, 0);
40fb9820 4252
4eed87de
AM		 4253 for (t = current_templates->start;
4254 t < current_templates->end;
4255 ++t)
c6fb90c8
L		 4256 allowed = operand_type_or (allowed,
4257 t->operand_types[op]);
9cd96992
JB		 4258 switch (guess_suffix)
4259 {
4260 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4261 mask.bitfield.imm64 = 1;
4262 mask.bitfield.imm32s = 1;
9cd96992
JB		 4263 break;
4264 case LONG_MNEM_SUFFIX:
40fb9820 4265 mask.bitfield.imm32 = 1;
9cd96992
JB		 4266 break;
4267 case WORD_MNEM_SUFFIX:
40fb9820 4268 mask.bitfield.imm16 = 1;
9cd96992
JB		 4269 break;
4270 case BYTE_MNEM_SUFFIX:
40fb9820 4271 mask.bitfield.imm8 = 1;
9cd96992
JB		 4272 break;
4273 default:
9cd96992
JB		 4274 break;
4275 }
c6fb90c8 4276 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4277 if (!operand_type_all_zero (&allowed))
c6fb90c8 4278 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4279 }
29b0f896 4280 break;
252b5132 4281 }
29b0f896
AM		 4282 }
4283}
47926f60 4284
29b0f896
AM		 4285/* Try to use the smallest displacement type too. */
4286static void
e3bb37b5 4287optimize_disp (void)
29b0f896
AM		 4288{
4289 int op;
3e73aa7c 4290
29b0f896 4291 for (op = i.operands; --op >= 0;)
40fb9820 4292 if (operand_type_check (i.types[op], disp))
252b5132 4293 {
b300c311 4294 if (i.op[op].disps->X_op == O_constant)
252b5132 4295 {
91d6fa6a 4296 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4297
40fb9820 4298 if (i.types[op].bitfield.disp16
91d6fa6a 4299 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4300 {
4301 /* If this operand is at most 16 bits, convert
4302 to a signed 16 bit number and don't use 64bit
4303 displacement. */
91d6fa6a 4304 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4305 i.types[op].bitfield.disp64 = 0;
b300c311 4306 }
40fb9820 4307 if (i.types[op].bitfield.disp32
91d6fa6a 4308 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4309 {
4310 /* If this operand is at most 32 bits, convert
4311 to a signed 32 bit number and don't use 64bit
4312 displacement. */
91d6fa6a
NC		 4313 op_disp &= (((offsetT) 2 << 31) - 1);
4314 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4315 i.types[op].bitfield.disp64 = 0;
b300c311 4316 }
91d6fa6a 4317 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4318 {
40fb9820
L		 4319 i.types[op].bitfield.disp8 = 0;
4320 i.types[op].bitfield.disp16 = 0;
4321 i.types[op].bitfield.disp32 = 0;
4322 i.types[op].bitfield.disp32s = 0;
4323 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4324 i.op[op].disps = 0;
4325 i.disp_operands--;
4326 }
4327 else if (flag_code == CODE_64BIT)
4328 {
91d6fa6a 4329 if (fits_in_signed_long (op_disp))
28a9d8f5 4330 {
40fb9820
L		 4331 i.types[op].bitfield.disp64 = 0;
4332 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4333 }
0e1147d9 4334 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4335 && fits_in_unsigned_long (op_disp))
40fb9820 4336 i.types[op].bitfield.disp32 = 1;
b300c311 4337 }
40fb9820
L		 4338 if ((i.types[op].bitfield.disp32
4339 || i.types[op].bitfield.disp32s
4340 || i.types[op].bitfield.disp16)
91d6fa6a 4341 && fits_in_signed_byte (op_disp))
40fb9820 4342 i.types[op].bitfield.disp8 = 1;
252b5132 4343 }
67a4f2b7
AO		 4344 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4345 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4346 {
4347 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4348 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4349 i.types[op].bitfield.disp8 = 0;
4350 i.types[op].bitfield.disp16 = 0;
4351 i.types[op].bitfield.disp32 = 0;
4352 i.types[op].bitfield.disp32s = 0;
4353 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4354 }
4355 else
b300c311 4356 /* We only support 64bit displacement on constants. */
40fb9820 4357 i.types[op].bitfield.disp64 = 0;
252b5132 4358 }
29b0f896
AM		 4359}
4360
6c30d220
L		 4361/* Check if operands are valid for the instruction. */
4362
4363static int
4364check_VecOperands (const insn_template *t)
4365{
43234a1e
L		 4366 unsigned int op;
4367
6c30d220
L		 4368 /* Without VSIB byte, we can't have a vector register for index. */
4369 if (!t->opcode_modifier.vecsib
4370 && i.index_reg
4371 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4372 || i.index_reg->reg_type.bitfield.regymm
4373 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4374 {
4375 i.error = unsupported_vector_index_register;
4376 return 1;
4377 }
4378
ad8ecc81
MZ		 4379 /* Check if default mask is allowed. */
4380 if (t->opcode_modifier.nodefmask
4381 && (!i.mask || i.mask->mask->reg_num == 0))
4382 {
4383 i.error = no_default_mask;
4384 return 1;
4385 }
4386
7bab8ab5
JB		 4387 /* For VSIB byte, we need a vector register for index, and all vector
4388 registers must be distinct. */
4389 if (t->opcode_modifier.vecsib)
4390 {
4391 if (!i.index_reg
6c30d220
L		 4392 || !((t->opcode_modifier.vecsib == VecSIB128
4393 && i.index_reg->reg_type.bitfield.regxmm)
4394 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4395 && i.index_reg->reg_type.bitfield.regymm)
4396 || (t->opcode_modifier.vecsib == VecSIB512
4397 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4398 {
4399 i.error = invalid_vsib_address;
4400 return 1;
4401 }
4402
43234a1e
L		 4403 gas_assert (i.reg_operands == 2 || i.mask);
4404 if (i.reg_operands == 2 && !i.mask)
4405 {
4406 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4407 || i.types[0].bitfield.regymm);
43234a1e 4408 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4409 || i.types[2].bitfield.regymm);
43234a1e
L		 4410 if (operand_check == check_none)
4411 return 0;
4412 if (register_number (i.op[0].regs)
4413 != register_number (i.index_reg)
4414 && register_number (i.op[2].regs)
4415 != register_number (i.index_reg)
4416 && register_number (i.op[0].regs)
4417 != register_number (i.op[2].regs))
4418 return 0;
4419 if (operand_check == check_error)
4420 {
4421 i.error = invalid_vector_register_set;
4422 return 1;
4423 }
4424 as_warn (_("mask, index, and destination registers should be distinct"));
4425 }
8444f82a
MZ		 4426 else if (i.reg_operands == 1 && i.mask)
4427 {
4428 if ((i.types[1].bitfield.regymm
4429 || i.types[1].bitfield.regzmm)
4430 && (register_number (i.op[1].regs)
4431 == register_number (i.index_reg)))
4432 {
4433 if (operand_check == check_error)
4434 {
4435 i.error = invalid_vector_register_set;
4436 return 1;
4437 }
4438 if (operand_check != check_none)
4439 as_warn (_("index and destination registers should be distinct"));
4440 }
4441 }
43234a1e 4442 }
7bab8ab5 4443
43234a1e
L		 4444 /* Check if broadcast is supported by the instruction and is applied
4445 to the memory operand. */
4446 if (i.broadcast)
4447 {
4448 int broadcasted_opnd_size;
4449
4450 /* Check if specified broadcast is supported in this instruction,
4451 and it's applied to memory operand of DWORD or QWORD type,
4452 depending on VecESize. */
4453 if (i.broadcast->type != t->opcode_modifier.broadcast
4454 || !i.types[i.broadcast->operand].bitfield.mem
4455 || (t->opcode_modifier.vecesize == 0
4456 && !i.types[i.broadcast->operand].bitfield.dword
4457 && !i.types[i.broadcast->operand].bitfield.unspecified)
4458 || (t->opcode_modifier.vecesize == 1
4459 && !i.types[i.broadcast->operand].bitfield.qword
4460 && !i.types[i.broadcast->operand].bitfield.unspecified))
4461 goto bad_broadcast;
4462
4463 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4464 if (i.broadcast->type == BROADCAST_1TO16)
4465 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4466 else if (i.broadcast->type == BROADCAST_1TO8)
4467 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4468 else if (i.broadcast->type == BROADCAST_1TO4)
4469 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4470 else if (i.broadcast->type == BROADCAST_1TO2)
4471 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4472 else
4473 goto bad_broadcast;
4474
4475 if ((broadcasted_opnd_size == 256
4476 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4477 || (broadcasted_opnd_size == 512
4478 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4479 {
4480 bad_broadcast:
4481 i.error = unsupported_broadcast;
4482 return 1;
4483 }
4484 }
4485 /* If broadcast is supported in this instruction, we need to check if
4486 operand of one-element size isn't specified without broadcast. */
4487 else if (t->opcode_modifier.broadcast && i.mem_operands)
4488 {
4489 /* Find memory operand. */
4490 for (op = 0; op < i.operands; op++)
4491 if (operand_type_check (i.types[op], anymem))
4492 break;
4493 gas_assert (op < i.operands);
4494 /* Check size of the memory operand. */
4495 if ((t->opcode_modifier.vecesize == 0
4496 && i.types[op].bitfield.dword)
4497 || (t->opcode_modifier.vecesize == 1
4498 && i.types[op].bitfield.qword))
4499 {
4500 i.error = broadcast_needed;
4501 return 1;
4502 }
4503 }
4504
4505 /* Check if requested masking is supported. */
4506 if (i.mask
4507 && (!t->opcode_modifier.masking
4508 || (i.mask->zeroing
4509 && t->opcode_modifier.masking == MERGING_MASKING)))
4510 {
4511 i.error = unsupported_masking;
4512 return 1;
4513 }
4514
4515 /* Check if masking is applied to dest operand. */
4516 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4517 {
4518 i.error = mask_not_on_destination;
4519 return 1;
4520 }
4521
43234a1e
L		 4522 /* Check RC/SAE. */
4523 if (i.rounding)
4524 {
4525 if ((i.rounding->type != saeonly
4526 && !t->opcode_modifier.staticrounding)
4527 || (i.rounding->type == saeonly
4528 && (t->opcode_modifier.staticrounding
4529 || !t->opcode_modifier.sae)))
4530 {
4531 i.error = unsupported_rc_sae;
4532 return 1;
4533 }
4534 /* If the instruction has several immediate operands and one of
4535 them is rounding, the rounding operand should be the last
4536 immediate operand. */
4537 if (i.imm_operands > 1
4538 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4539 {
43234a1e 4540 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4541 return 1;
4542 }
6c30d220
L		 4543 }
4544
43234a1e
L		 4545 /* Check vector Disp8 operand. */
4546 if (t->opcode_modifier.disp8memshift)
4547 {
4548 if (i.broadcast)
4549 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4550 else
4551 i.memshift = t->opcode_modifier.disp8memshift;
4552
4553 for (op = 0; op < i.operands; op++)
4554 if (operand_type_check (i.types[op], disp)
4555 && i.op[op].disps->X_op == O_constant)
4556 {
4557 offsetT value = i.op[op].disps->X_add_number;
4558 int vec_disp8_ok = fits_in_vec_disp8 (value);
4559 if (t->operand_types [op].bitfield.vec_disp8)
4560 {
4561 if (vec_disp8_ok)
4562 i.types[op].bitfield.vec_disp8 = 1;
4563 else
4564 {
4565 /* Vector insn can only have Vec_Disp8/Disp32 in
4566 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4567 mode. */
4568 i.types[op].bitfield.disp8 = 0;
4569 if (flag_code != CODE_16BIT)
4570 i.types[op].bitfield.disp16 = 0;
4571 }
4572 }
4573 else if (flag_code != CODE_16BIT)
4574 {
4575 /* One form of this instruction supports vector Disp8.
4576 Try vector Disp8 if we need to use Disp32. */
4577 if (vec_disp8_ok && !fits_in_signed_byte (value))
4578 {
4579 i.error = try_vector_disp8;
4580 return 1;
4581 }
4582 }
4583 }
4584 }
4585 else
4586 i.memshift = -1;
4587
6c30d220
L		 4588 return 0;
4589}
4590
43f3e2ee 4591/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4592 operand types. */
4593
4594static int
4595VEX_check_operands (const insn_template *t)
4596{
43234a1e
L		 4597 /* VREX is only valid with EVEX prefix. */
4598 if (i.need_vrex && !t->opcode_modifier.evex)
4599 {
4600 i.error = invalid_register_operand;
4601 return 1;
4602 }
4603
a683cc34
SP		 4604 if (!t->opcode_modifier.vex)
4605 return 0;
4606
4607 /* Only check VEX_Imm4, which must be the first operand. */
4608 if (t->operand_types[0].bitfield.vec_imm4)
4609 {
4610 if (i.op[0].imms->X_op != O_constant
4611 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4612 {
a65babc9 4613 i.error = bad_imm4;
891edac4
L		 4614 return 1;
4615 }
a683cc34
SP		 4616
4617 /* Turn off Imm8 so that update_imm won't complain. */
4618 i.types[0] = vec_imm4;
4619 }
4620
4621 return 0;
4622}
4623
d3ce72d0 4624static const insn_template *
e3bb37b5 4625match_template (void)
29b0f896
AM		 4626{
4627 /* Points to template once we've found it. */
d3ce72d0 4628 const insn_template *t;
40fb9820 4629 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4630 i386_operand_type overlap4;
29b0f896 4631 unsigned int found_reverse_match;
40fb9820
L		 4632 i386_opcode_modifier suffix_check;
4633 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4634 int addr_prefix_disp;
a5c311ca 4635 unsigned int j;
3629bb00 4636 unsigned int found_cpu_match;
45664ddb 4637 unsigned int check_register;
5614d22c 4638 enum i386_error specific_error = 0;
29b0f896 4639
c0f3af97
L		 4640#if MAX_OPERANDS != 5
4641# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4642#endif
4643
29b0f896 4644 found_reverse_match = 0;
539e75ad 4645 addr_prefix_disp = -1;
40fb9820
L		 4646
4647 memset (&suffix_check, 0, sizeof (suffix_check));
4648 if (i.suffix == BYTE_MNEM_SUFFIX)
4649 suffix_check.no_bsuf = 1;
4650 else if (i.suffix == WORD_MNEM_SUFFIX)
4651 suffix_check.no_wsuf = 1;
4652 else if (i.suffix == SHORT_MNEM_SUFFIX)
4653 suffix_check.no_ssuf = 1;
4654 else if (i.suffix == LONG_MNEM_SUFFIX)
4655 suffix_check.no_lsuf = 1;
4656 else if (i.suffix == QWORD_MNEM_SUFFIX)
4657 suffix_check.no_qsuf = 1;
4658 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4659 suffix_check.no_ldsuf = 1;
29b0f896 4660
01559ecc
L		 4661 /* Must have right number of operands. */
4662 i.error = number_of_operands_mismatch;
4663
45aa61fe 4664 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4665 {
539e75ad
L		 4666 addr_prefix_disp = -1;
4667
29b0f896
AM		 4668 if (i.operands != t->operands)
4669 continue;
4670
50aecf8c 4671 /* Check processor support. */
a65babc9 4672 i.error = unsupported;
c0f3af97
L		 4673 found_cpu_match = (cpu_flags_match (t)
4674 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4675 if (!found_cpu_match)
4676 continue;
4677
e1d4d893 4678 /* Check old gcc support. */
a65babc9 4679 i.error = old_gcc_only;
e1d4d893
L		 4680 if (!old_gcc && t->opcode_modifier.oldgcc)
4681 continue;
4682
4683 /* Check AT&T mnemonic. */
a65babc9 4684 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4685 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4686 continue;
4687
891edac4 4688 /* Check AT&T/Intel syntax. */
a65babc9 4689 i.error = unsupported_syntax;
5c07affc
L		 4690 if ((intel_syntax && t->opcode_modifier.attsyntax)
4691 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4692 continue;
4693
20592a94 4694 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4695 i.error = invalid_instruction_suffix;
567e4e96
L		 4696 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4697 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4698 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4699 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4700 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4701 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4702 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4703 continue;
4704
5c07affc 4705 if (!operand_size_match (t))
7d5e4556 4706 continue;
539e75ad 4707
5c07affc
L		 4708 for (j = 0; j < MAX_OPERANDS; j++)
4709 operand_types[j] = t->operand_types[j];
4710
45aa61fe
AM		 4711 /* In general, don't allow 64-bit operands in 32-bit mode. */
4712 if (i.suffix == QWORD_MNEM_SUFFIX
4713 && flag_code != CODE_64BIT
4714 && (intel_syntax
40fb9820 4715 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4716 && !intel_float_operand (t->name))
4717 : intel_float_operand (t->name) != 2)
40fb9820 4718 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4719 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4720 && !operand_types[0].bitfield.regymm
4721 && !operand_types[0].bitfield.regzmm)
40fb9820 4722 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4723 && operand_types[t->operands > 1].bitfield.regxmm
4724 && operand_types[t->operands > 1].bitfield.regymm
4725 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4726 && (t->base_opcode != 0x0fc7
4727 || t->extension_opcode != 1 /* cmpxchg8b */))
4728 continue;
4729
192dc9c6
JB		 4730 /* In general, don't allow 32-bit operands on pre-386. */
4731 else if (i.suffix == LONG_MNEM_SUFFIX
4732 && !cpu_arch_flags.bitfield.cpui386
4733 && (intel_syntax
4734 ? (!t->opcode_modifier.ignoresize
4735 && !intel_float_operand (t->name))
4736 : intel_float_operand (t->name) != 2)
4737 && ((!operand_types[0].bitfield.regmmx
4738 && !operand_types[0].bitfield.regxmm)
4739 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4740 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4741 continue;
4742
29b0f896 4743 /* Do not verify operands when there are none. */
50aecf8c 4744 else
29b0f896 4745 {
c6fb90c8 4746 if (!t->operands)
2dbab7d5
L		 4747 /* We've found a match; break out of loop. */
4748 break;
29b0f896 4749 }
252b5132 4750
539e75ad
L		 4751 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4752 into Disp32/Disp16/Disp32 operand. */
4753 if (i.prefix[ADDR_PREFIX] != 0)
4754 {
40fb9820 4755 /* There should be only one Disp operand. */
539e75ad
L		 4756 switch (flag_code)
4757 {
4758 case CODE_16BIT:
40fb9820
L		 4759 for (j = 0; j < MAX_OPERANDS; j++)
4760 {
4761 if (operand_types[j].bitfield.disp16)
4762 {
4763 addr_prefix_disp = j;
4764 operand_types[j].bitfield.disp32 = 1;
4765 operand_types[j].bitfield.disp16 = 0;
4766 break;
4767 }
4768 }
539e75ad
L		 4769 break;
4770 case CODE_32BIT:
40fb9820
L		 4771 for (j = 0; j < MAX_OPERANDS; j++)
4772 {
4773 if (operand_types[j].bitfield.disp32)
4774 {
4775 addr_prefix_disp = j;
4776 operand_types[j].bitfield.disp32 = 0;
4777 operand_types[j].bitfield.disp16 = 1;
4778 break;
4779 }
4780 }
539e75ad
L		 4781 break;
4782 case CODE_64BIT:
40fb9820
L		 4783 for (j = 0; j < MAX_OPERANDS; j++)
4784 {
4785 if (operand_types[j].bitfield.disp64)
4786 {
4787 addr_prefix_disp = j;
4788 operand_types[j].bitfield.disp64 = 0;
4789 operand_types[j].bitfield.disp32 = 1;
4790 break;
4791 }
4792 }
539e75ad
L		 4793 break;
4794 }
539e75ad
L		 4795 }
4796
56ffb741
L		 4797 /* We check register size if needed. */
4798 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4799 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4800 switch (t->operands)
4801 {
4802 case 1:
40fb9820 4803 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4804 continue;
4805 break;
4806 case 2:
8b38ad71
L		 4807 /* xchg %eax, %eax is a special case. It is an aliase for nop
4808 only in 32bit mode and we can use opcode 0x90. In 64bit
4809 mode, we can't use 0x90 for xchg %eax, %eax since it should
4810 zero-extend %eax to %rax. */
4811 if (flag_code == CODE_64BIT
4812 && t->base_opcode == 0x90
0dfbf9d7
L		 4813 && operand_type_equal (&i.types [0], &acc32)
4814 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4815 continue;
b6169b20
L		 4816 if (i.swap_operand)
4817 {
4818 /* If we swap operand in encoding, we either match
4819 the next one or reverse direction of operands. */
4820 if (t->opcode_modifier.s)
4821 continue;
4822 else if (t->opcode_modifier.d)
4823 goto check_reverse;
4824 }
4825
29b0f896 4826 case 3:
fa99fab2
L		 4827 /* If we swap operand in encoding, we match the next one. */
4828 if (i.swap_operand && t->opcode_modifier.s)
4829 continue;
f48ff2ae 4830 case 4:
c0f3af97 4831 case 5:
c6fb90c8 4832 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4833 if (!operand_type_match (overlap0, i.types[0])
4834 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4835 || (check_register
4836 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4837 operand_types[0],
4838 overlap1, i.types[1],
4839 operand_types[1])))
29b0f896
AM		 4840 {
4841 /* Check if other direction is valid ... */
40fb9820 4842 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4843 continue;
4844
b6169b20 4845check_reverse:
29b0f896 4846 /* Try reversing direction of operands. */
c6fb90c8
L		 4847 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4848 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4849 if (!operand_type_match (overlap0, i.types[0])
4850 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4851 || (check_register
4852 && !operand_type_register_match (overlap0,
4853 i.types[0],
4854 operand_types[1],
4855 overlap1,
4856 i.types[1],
4857 operand_types[0])))
29b0f896
AM		 4858 {
4859 /* Does not match either direction. */
4860 continue;
4861 }
4862 /* found_reverse_match holds which of D or FloatDR
4863 we've found. */
40fb9820 4864 if (t->opcode_modifier.d)
8a2ed489 4865 found_reverse_match = Opcode_D;
40fb9820 4866 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4867 found_reverse_match = Opcode_FloatD;
4868 else
4869 found_reverse_match = 0;
40fb9820 4870 if (t->opcode_modifier.floatr)
8a2ed489 4871 found_reverse_match |= Opcode_FloatR;
29b0f896 4872 }
f48ff2ae 4873 else
29b0f896 4874 {
f48ff2ae 4875 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4876 switch (t->operands)
4877 {
c0f3af97
L		 4878 case 5:
4879 overlap4 = operand_type_and (i.types[4],
4880 operand_types[4]);
d1cbb4db 4881 case 4:
c6fb90c8
L		 4882 overlap3 = operand_type_and (i.types[3],
4883 operand_types[3]);
d1cbb4db 4884 case 3:
c6fb90c8
L		 4885 overlap2 = operand_type_and (i.types[2],
4886 operand_types[2]);
d1cbb4db
L		 4887 break;
4888 }
29b0f896 4889
f48ff2ae
L		 4890 switch (t->operands)
4891 {
c0f3af97
L		 4892 case 5:
4893 if (!operand_type_match (overlap4, i.types[4])
4894 || !operand_type_register_match (overlap3,
4895 i.types[3],
4896 operand_types[3],
4897 overlap4,
4898 i.types[4],
4899 operand_types[4]))
4900 continue;
f48ff2ae 4901 case 4:
40fb9820 4902 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4903 || (check_register
4904 && !operand_type_register_match (overlap2,
4905 i.types[2],
4906 operand_types[2],
4907 overlap3,
4908 i.types[3],
4909 operand_types[3])))
f48ff2ae
L		 4910 continue;
4911 case 3:
4912 /* Here we make use of the fact that there are no
4913 reverse match 3 operand instructions, and all 3
4914 operand instructions only need to be checked for
4915 register consistency between operands 2 and 3. */
40fb9820 4916 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4917 || (check_register
4918 && !operand_type_register_match (overlap1,
4919 i.types[1],
4920 operand_types[1],
4921 overlap2,
4922 i.types[2],
4923 operand_types[2])))
f48ff2ae
L		 4924 continue;
4925 break;
4926 }
29b0f896 4927 }
f48ff2ae 4928 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4929 slip through to break. */
4930 }
3629bb00 4931 if (!found_cpu_match)
29b0f896
AM		 4932 {
4933 found_reverse_match = 0;
4934 continue;
4935 }
c0f3af97 4936
5614d22c
JB		 4937 /* Check if vector and VEX operands are valid. */
4938 if (check_VecOperands (t) || VEX_check_operands (t))
4939 {
4940 specific_error = i.error;
4941 continue;
4942 }
a683cc34 4943
29b0f896
AM		 4944 /* We've found a match; break out of loop. */
4945 break;
4946 }
4947
4948 if (t == current_templates->end)
4949 {
4950 /* We found no match. */
a65babc9 4951 const char *err_msg;
5614d22c 4952 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4953 {
4954 default:
4955 abort ();
86e026a4 4956 case operand_size_mismatch:
a65babc9
L		 4957 err_msg = _("operand size mismatch");
4958 break;
4959 case operand_type_mismatch:
4960 err_msg = _("operand type mismatch");
4961 break;
4962 case register_type_mismatch:
4963 err_msg = _("register type mismatch");
4964 break;
4965 case number_of_operands_mismatch:
4966 err_msg = _("number of operands mismatch");
4967 break;
4968 case invalid_instruction_suffix:
4969 err_msg = _("invalid instruction suffix");
4970 break;
4971 case bad_imm4:
4a2608e3 4972 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4973 break;
4974 case old_gcc_only:
4975 err_msg = _("only supported with old gcc");
4976 break;
4977 case unsupported_with_intel_mnemonic:
4978 err_msg = _("unsupported with Intel mnemonic");
4979 break;
4980 case unsupported_syntax:
4981 err_msg = _("unsupported syntax");
4982 break;
4983 case unsupported:
35262a23 4984 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4985 current_templates->start->name);
4986 return NULL;
6c30d220
L		 4987 case invalid_vsib_address:
4988 err_msg = _("invalid VSIB address");
4989 break;
7bab8ab5
JB		 4990 case invalid_vector_register_set:
4991 err_msg = _("mask, index, and destination registers must be distinct");
4992 break;
6c30d220
L		 4993 case unsupported_vector_index_register:
4994 err_msg = _("unsupported vector index register");
4995 break;
43234a1e
L		 4996 case unsupported_broadcast:
4997 err_msg = _("unsupported broadcast");
4998 break;
4999 case broadcast_not_on_src_operand:
5000 err_msg = _("broadcast not on source memory operand");
5001 break;
5002 case broadcast_needed:
5003 err_msg = _("broadcast is needed for operand of such type");
5004 break;
5005 case unsupported_masking:
5006 err_msg = _("unsupported masking");
5007 break;
5008 case mask_not_on_destination:
5009 err_msg = _("mask not on destination operand");
5010 break;
5011 case no_default_mask:
5012 err_msg = _("default mask isn't allowed");
5013 break;
5014 case unsupported_rc_sae:
5015 err_msg = _("unsupported static rounding/sae");
5016 break;
5017 case rc_sae_operand_not_last_imm:
5018 if (intel_syntax)
5019 err_msg = _("RC/SAE operand must precede immediate operands");
5020 else
5021 err_msg = _("RC/SAE operand must follow immediate operands");
5022 break;
5023 case invalid_register_operand:
5024 err_msg = _("invalid register operand");
5025 break;
a65babc9
L		 5026 }
5027 as_bad (_("%s for `%s'"), err_msg,
891edac4 5028 current_templates->start->name);
fa99fab2 5029 return NULL;
29b0f896 5030 }
252b5132 5031
29b0f896
AM		 5032 if (!quiet_warnings)
5033 {
5034 if (!intel_syntax
40fb9820
L		 5035 && (i.types[0].bitfield.jumpabsolute
5036 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5037 {
5038 as_warn (_("indirect %s without `*'"), t->name);
5039 }
5040
40fb9820
L		 5041 if (t->opcode_modifier.isprefix
5042 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5043 {
5044 /* Warn them that a data or address size prefix doesn't
5045 affect assembly of the next line of code. */
5046 as_warn (_("stand-alone `%s' prefix"), t->name);
5047 }
5048 }
5049
5050 /* Copy the template we found. */
5051 i.tm = *t;
539e75ad
L		 5052
5053 if (addr_prefix_disp != -1)
5054 i.tm.operand_types[addr_prefix_disp]
5055 = operand_types[addr_prefix_disp];
5056
29b0f896
AM		 5057 if (found_reverse_match)
5058 {
5059 /* If we found a reverse match we must alter the opcode
5060 direction bit. found_reverse_match holds bits to change
5061 (different for int & float insns). */
5062
5063 i.tm.base_opcode ^= found_reverse_match;
5064
539e75ad
L		 5065 i.tm.operand_types[0] = operand_types[1];
5066 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5067 }
5068
fa99fab2 5069 return t;
29b0f896
AM		 5070}
5071
5072static int
e3bb37b5 5073check_string (void)
29b0f896 5074{
40fb9820
L		 5075 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5076 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5077 {
5078 if (i.seg[0] != NULL && i.seg[0] != &es)
5079 {
a87af027 5080 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5081 i.tm.name,
a87af027
JB		 5082 mem_op + 1,
5083 register_prefix);
29b0f896
AM		 5084 return 0;
5085 }
5086 /* There's only ever one segment override allowed per instruction.
5087 This instruction possibly has a legal segment override on the
5088 second operand, so copy the segment to where non-string
5089 instructions store it, allowing common code. */
5090 i.seg[0] = i.seg[1];
5091 }
40fb9820 5092 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5093 {
5094 if (i.seg[1] != NULL && i.seg[1] != &es)
5095 {
a87af027 5096 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5097 i.tm.name,
a87af027
JB		 5098 mem_op + 2,
5099 register_prefix);
29b0f896
AM		 5100 return 0;
5101 }
5102 }
5103 return 1;
5104}
5105
5106static int
543613e9 5107process_suffix (void)
29b0f896
AM		 5108{
5109 /* If matched instruction specifies an explicit instruction mnemonic
5110 suffix, use it. */
40fb9820
L		 5111 if (i.tm.opcode_modifier.size16)
5112 i.suffix = WORD_MNEM_SUFFIX;
5113 else if (i.tm.opcode_modifier.size32)
5114 i.suffix = LONG_MNEM_SUFFIX;
5115 else if (i.tm.opcode_modifier.size64)
5116 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5117 else if (i.reg_operands)
5118 {
5119 /* If there's no instruction mnemonic suffix we try to invent one
5120 based on register operands. */
5121 if (!i.suffix)
5122 {
5123 /* We take i.suffix from the last register operand specified,
5124 Destination register type is more significant than source
381d071f
L		 5125 register type. crc32 in SSE4.2 prefers source register
5126 type. */
5127 if (i.tm.base_opcode == 0xf20f38f1)
5128 {
40fb9820
L		 5129 if (i.types[0].bitfield.reg16)
5130 i.suffix = WORD_MNEM_SUFFIX;
5131 else if (i.types[0].bitfield.reg32)
5132 i.suffix = LONG_MNEM_SUFFIX;
5133 else if (i.types[0].bitfield.reg64)
5134 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5135 }
9344ff29 5136 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5137 {
40fb9820 5138 if (i.types[0].bitfield.reg8)
20592a94
L		 5139 i.suffix = BYTE_MNEM_SUFFIX;
5140 }
381d071f
L		 5141
5142 if (!i.suffix)
5143 {
5144 int op;
5145
20592a94
L		 5146 if (i.tm.base_opcode == 0xf20f38f1
5147 || i.tm.base_opcode == 0xf20f38f0)
5148 {
5149 /* We have to know the operand size for crc32. */
5150 as_bad (_("ambiguous memory operand size for `%s`"),
5151 i.tm.name);
5152 return 0;
5153 }
5154
381d071f 5155 for (op = i.operands; --op >= 0;)
40fb9820 5156 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5157 {
40fb9820
L		 5158 if (i.types[op].bitfield.reg8)
5159 {
5160 i.suffix = BYTE_MNEM_SUFFIX;
5161 break;
5162 }
5163 else if (i.types[op].bitfield.reg16)
5164 {
5165 i.suffix = WORD_MNEM_SUFFIX;
5166 break;
5167 }
5168 else if (i.types[op].bitfield.reg32)
5169 {
5170 i.suffix = LONG_MNEM_SUFFIX;
5171 break;
5172 }
5173 else if (i.types[op].bitfield.reg64)
5174 {
5175 i.suffix = QWORD_MNEM_SUFFIX;
5176 break;
5177 }
381d071f
L		 5178 }
5179 }
29b0f896
AM		 5180 }
5181 else if (i.suffix == BYTE_MNEM_SUFFIX)
5182 {
2eb952a4
L		 5183 if (intel_syntax
5184 && i.tm.opcode_modifier.ignoresize
5185 && i.tm.opcode_modifier.no_bsuf)
5186 i.suffix = 0;
5187 else if (!check_byte_reg ())
29b0f896
AM		 5188 return 0;
5189 }
5190 else if (i.suffix == LONG_MNEM_SUFFIX)
5191 {
2eb952a4
L		 5192 if (intel_syntax
5193 && i.tm.opcode_modifier.ignoresize
5194 && i.tm.opcode_modifier.no_lsuf)
5195 i.suffix = 0;
5196 else if (!check_long_reg ())
29b0f896
AM		 5197 return 0;
5198 }
5199 else if (i.suffix == QWORD_MNEM_SUFFIX)
5200 {
955e1e6a
L		 5201 if (intel_syntax
5202 && i.tm.opcode_modifier.ignoresize
5203 && i.tm.opcode_modifier.no_qsuf)
5204 i.suffix = 0;
5205 else if (!check_qword_reg ())
29b0f896
AM		 5206 return 0;
5207 }
5208 else if (i.suffix == WORD_MNEM_SUFFIX)
5209 {
2eb952a4
L		 5210 if (intel_syntax
5211 && i.tm.opcode_modifier.ignoresize
5212 && i.tm.opcode_modifier.no_wsuf)
5213 i.suffix = 0;
5214 else if (!check_word_reg ())
29b0f896
AM		 5215 return 0;
5216 }
c0f3af97 5217 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5218 || i.suffix == YMMWORD_MNEM_SUFFIX
5219 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5220 {
43234a1e 5221 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5222 should check if it is a valid suffix. */
5223 }
40fb9820 5224 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5225 /* Do nothing if the instruction is going to ignore the prefix. */
5226 ;
5227 else
5228 abort ();
5229 }
40fb9820 5230 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5231 && !i.suffix
5232 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5233 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5234 {
5235 i.suffix = stackop_size;
5236 }
9306ca4a
JB		 5237 else if (intel_syntax
5238 && !i.suffix
40fb9820
L		 5239 && (i.tm.operand_types[0].bitfield.jumpabsolute
5240 || i.tm.opcode_modifier.jumpbyte
5241 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5242 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5243 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5244 {
5245 switch (flag_code)
5246 {
5247 case CODE_64BIT:
40fb9820 5248 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5249 {
5250 i.suffix = QWORD_MNEM_SUFFIX;
5251 break;
5252 }
5253 case CODE_32BIT:
40fb9820 5254 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5255 i.suffix = LONG_MNEM_SUFFIX;
5256 break;
5257 case CODE_16BIT:
40fb9820 5258 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5259 i.suffix = WORD_MNEM_SUFFIX;
5260 break;
5261 }
5262 }
252b5132 5263
9306ca4a 5264 if (!i.suffix)
29b0f896 5265 {
9306ca4a
JB		 5266 if (!intel_syntax)
5267 {
40fb9820 5268 if (i.tm.opcode_modifier.w)
9306ca4a 5269 {
4eed87de
AM		 5270 as_bad (_("no instruction mnemonic suffix given and "
5271 "no register operands; can't size instruction"));
9306ca4a
JB		 5272 return 0;
5273 }
5274 }
5275 else
5276 {
40fb9820 5277 unsigned int suffixes;
7ab9ffdd 5278
40fb9820
L		 5279 suffixes = !i.tm.opcode_modifier.no_bsuf;
5280 if (!i.tm.opcode_modifier.no_wsuf)
5281 suffixes |= 1 << 1;
5282 if (!i.tm.opcode_modifier.no_lsuf)
5283 suffixes |= 1 << 2;
fc4adea1 5284 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5285 suffixes |= 1 << 3;
5286 if (!i.tm.opcode_modifier.no_ssuf)
5287 suffixes |= 1 << 4;
5288 if (!i.tm.opcode_modifier.no_qsuf)
5289 suffixes |= 1 << 5;
5290
5291 /* There are more than suffix matches. */
5292 if (i.tm.opcode_modifier.w
9306ca4a 5293 || ((suffixes & (suffixes - 1))
40fb9820
L		 5294 && !i.tm.opcode_modifier.defaultsize
5295 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5296 {
5297 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5298 return 0;
5299 }
5300 }
29b0f896 5301 }
252b5132 5302
9306ca4a
JB		 5303 /* Change the opcode based on the operand size given by i.suffix;
5304 We don't need to change things for byte insns. */
5305
582d5edd
L		 5306 if (i.suffix
5307 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5308 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5309 && i.suffix != YMMWORD_MNEM_SUFFIX
5310 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5311 {
5312 /* It's not a byte, select word/dword operation. */
40fb9820 5313 if (i.tm.opcode_modifier.w)
29b0f896 5314 {
40fb9820 5315 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5316 i.tm.base_opcode |= 8;
5317 else
5318 i.tm.base_opcode |= 1;
5319 }
0f3f3d8b 5320
29b0f896
AM		 5321 /* Now select between word & dword operations via the operand
5322 size prefix, except for instructions that will ignore this
5323 prefix anyway. */
ca61edf2 5324 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5325 {
ca61edf2
L		 5326 /* The address size override prefix changes the size of the
5327 first operand. */
40fb9820
L		 5328 if ((flag_code == CODE_32BIT
5329 && i.op->regs[0].reg_type.bitfield.reg16)
5330 || (flag_code != CODE_32BIT
5331 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5332 if (!add_prefix (ADDR_PREFIX_OPCODE))
5333 return 0;
5334 }
5335 else if (i.suffix != QWORD_MNEM_SUFFIX
5336 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5337 && !i.tm.opcode_modifier.ignoresize
5338 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5339 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5340 || (flag_code == CODE_64BIT
40fb9820 5341 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5342 {
5343 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5344
40fb9820 5345 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5346 prefix = ADDR_PREFIX_OPCODE;
252b5132 5347
29b0f896
AM		 5348 if (!add_prefix (prefix))
5349 return 0;
24eab124 5350 }
252b5132 5351
29b0f896
AM		 5352 /* Set mode64 for an operand. */
5353 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5354 && flag_code == CODE_64BIT
40fb9820 5355 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5356 {
5357 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5358 need rex64. cmpxchg8b is also a special case. */
5359 if (! (i.operands == 2
5360 && i.tm.base_opcode == 0x90
5361 && i.tm.extension_opcode == None
0dfbf9d7
L		 5362 && operand_type_equal (&i.types [0], &acc64)
5363 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5364 && ! (i.operands == 1
5365 && i.tm.base_opcode == 0xfc7
5366 && i.tm.extension_opcode == 1
40fb9820
L		 5367 && !operand_type_check (i.types [0], reg)
5368 && operand_type_check (i.types [0], anymem)))
f6bee062 5369 i.rex |= REX_W;
46e883c5 5370 }
3e73aa7c 5371
29b0f896
AM		 5372 /* Size floating point instruction. */
5373 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5374 if (i.tm.opcode_modifier.floatmf)
543613e9 5375 i.tm.base_opcode ^= 4;
29b0f896 5376 }
7ecd2f8b 5377
29b0f896
AM		 5378 return 1;
5379}
3e73aa7c 5380
29b0f896 5381static int
543613e9 5382check_byte_reg (void)
29b0f896
AM		 5383{
5384 int op;
543613e9 5385
29b0f896
AM		 5386 for (op = i.operands; --op >= 0;)
5387 {
5388 /* If this is an eight bit register, it's OK. If it's the 16 or
5389 32 bit version of an eight bit register, we will just use the
5390 low portion, and that's OK too. */
40fb9820 5391 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5392 continue;
5393
5a819eb9
JB		 5394 /* I/O port address operands are OK too. */
5395 if (i.tm.operand_types[op].bitfield.inoutportreg)
5396 continue;
5397
9344ff29
L		 5398 /* crc32 doesn't generate this warning. */
5399 if (i.tm.base_opcode == 0xf20f38f0)
5400 continue;
5401
40fb9820
L		 5402 if ((i.types[op].bitfield.reg16
5403 || i.types[op].bitfield.reg32
5404 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5405 && i.op[op].regs->reg_num < 4
5406 /* Prohibit these changes in 64bit mode, since the lowering
5407 would be more complicated. */
5408 && flag_code != CODE_64BIT)
29b0f896 5409 {
29b0f896 5410#if REGISTER_WARNINGS
5a819eb9 5411 if (!quiet_warnings)
a540244d
L		 5412 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5413 register_prefix,
40fb9820 5414 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5415 ? REGNAM_AL - REGNAM_AX
5416 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5417 register_prefix,
29b0f896
AM		 5418 i.op[op].regs->reg_name,
5419 i.suffix);
5420#endif
5421 continue;
5422 }
5423 /* Any other register is bad. */
40fb9820
L		 5424 if (i.types[op].bitfield.reg16
5425 || i.types[op].bitfield.reg32
5426 || i.types[op].bitfield.reg64
5427 || i.types[op].bitfield.regmmx
5428 || i.types[op].bitfield.regxmm
c0f3af97 5429 || i.types[op].bitfield.regymm
43234a1e 5430 || i.types[op].bitfield.regzmm
40fb9820
L		 5431 || i.types[op].bitfield.sreg2
5432 || i.types[op].bitfield.sreg3
5433 || i.types[op].bitfield.control
5434 || i.types[op].bitfield.debug
5435 || i.types[op].bitfield.test
5436 || i.types[op].bitfield.floatreg
5437 || i.types[op].bitfield.floatacc)
29b0f896 5438 {
a540244d
L		 5439 as_bad (_("`%s%s' not allowed with `%s%c'"),
5440 register_prefix,
29b0f896
AM		 5441 i.op[op].regs->reg_name,
5442 i.tm.name,
5443 i.suffix);
5444 return 0;
5445 }
5446 }
5447 return 1;
5448}
5449
5450static int
e3bb37b5 5451check_long_reg (void)
29b0f896
AM		 5452{
5453 int op;
5454
5455 for (op = i.operands; --op >= 0;)
5456 /* Reject eight bit registers, except where the template requires
5457 them. (eg. movzb) */
40fb9820
L		 5458 if (i.types[op].bitfield.reg8
5459 && (i.tm.operand_types[op].bitfield.reg16
5460 || i.tm.operand_types[op].bitfield.reg32
5461 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5462 {
a540244d
L		 5463 as_bad (_("`%s%s' not allowed with `%s%c'"),
5464 register_prefix,
29b0f896
AM		 5465 i.op[op].regs->reg_name,
5466 i.tm.name,
5467 i.suffix);
5468 return 0;
5469 }
e4630f71 5470 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5471 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5472 && i.types[op].bitfield.reg16
5473 && (i.tm.operand_types[op].bitfield.reg32
5474 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5475 {
5476 /* Prohibit these changes in the 64bit mode, since the
5477 lowering is more complicated. */
5478 if (flag_code == CODE_64BIT)
252b5132 5479 {
2b5d6a91 5480 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5481 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5482 i.suffix);
5483 return 0;
252b5132 5484 }
29b0f896 5485#if REGISTER_WARNINGS
cecf1424
JB		 5486 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5487 register_prefix,
5488 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5489 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5490#endif
252b5132 5491 }
e4630f71 5492 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5493 else if (i.types[op].bitfield.reg64
5494 && (i.tm.operand_types[op].bitfield.reg32
5495 || i.tm.operand_types[op].bitfield.acc))
252b5132 5496 {
34828aad 5497 if (intel_syntax
ca61edf2 5498 && i.tm.opcode_modifier.toqword
40fb9820 5499 && !i.types[0].bitfield.regxmm)
34828aad 5500 {
ca61edf2 5501 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5502 i.suffix = QWORD_MNEM_SUFFIX;
5503 }
5504 else
5505 {
2b5d6a91 5506 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5507 register_prefix, i.op[op].regs->reg_name,
5508 i.suffix);
5509 return 0;
5510 }
29b0f896
AM		 5511 }
5512 return 1;
5513}
252b5132 5514
29b0f896 5515static int
e3bb37b5 5516check_qword_reg (void)
29b0f896
AM		 5517{
5518 int op;
252b5132 5519
29b0f896
AM		 5520 for (op = i.operands; --op >= 0; )
5521 /* Reject eight bit registers, except where the template requires
5522 them. (eg. movzb) */
40fb9820
L		 5523 if (i.types[op].bitfield.reg8
5524 && (i.tm.operand_types[op].bitfield.reg16
5525 || i.tm.operand_types[op].bitfield.reg32
5526 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5527 {
a540244d
L		 5528 as_bad (_("`%s%s' not allowed with `%s%c'"),
5529 register_prefix,
29b0f896
AM		 5530 i.op[op].regs->reg_name,
5531 i.tm.name,
5532 i.suffix);
5533 return 0;
5534 }
e4630f71 5535 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5536 else if ((i.types[op].bitfield.reg16
5537 || i.types[op].bitfield.reg32)
5538 && (i.tm.operand_types[op].bitfield.reg32
5539 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5540 {
5541 /* Prohibit these changes in the 64bit mode, since the
5542 lowering is more complicated. */
34828aad 5543 if (intel_syntax
ca61edf2 5544 && i.tm.opcode_modifier.todword
40fb9820 5545 && !i.types[0].bitfield.regxmm)
34828aad 5546 {
ca61edf2 5547 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5548 i.suffix = LONG_MNEM_SUFFIX;
5549 }
5550 else
5551 {
2b5d6a91 5552 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5553 register_prefix, i.op[op].regs->reg_name,
5554 i.suffix);
5555 return 0;
5556 }
252b5132 5557 }
29b0f896
AM		 5558 return 1;
5559}
252b5132 5560
29b0f896 5561static int
e3bb37b5 5562check_word_reg (void)
29b0f896
AM		 5563{
5564 int op;
5565 for (op = i.operands; --op >= 0;)
5566 /* Reject eight bit registers, except where the template requires
5567 them. (eg. movzb) */
40fb9820
L		 5568 if (i.types[op].bitfield.reg8
5569 && (i.tm.operand_types[op].bitfield.reg16
5570 || i.tm.operand_types[op].bitfield.reg32
5571 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5572 {
a540244d
L		 5573 as_bad (_("`%s%s' not allowed with `%s%c'"),
5574 register_prefix,
29b0f896
AM		 5575 i.op[op].regs->reg_name,
5576 i.tm.name,
5577 i.suffix);
5578 return 0;
5579 }
e4630f71 5580 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5581 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5582 && (i.types[op].bitfield.reg32
5583 || i.types[op].bitfield.reg64)
40fb9820
L		 5584 && (i.tm.operand_types[op].bitfield.reg16
5585 || i.tm.operand_types[op].bitfield.acc))
252b5132 5586 {
29b0f896
AM		 5587 /* Prohibit these changes in the 64bit mode, since the
5588 lowering is more complicated. */
5589 if (flag_code == CODE_64BIT)
252b5132 5590 {
2b5d6a91 5591 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5592 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5593 i.suffix);
5594 return 0;
252b5132 5595 }
29b0f896 5596#if REGISTER_WARNINGS
cecf1424
JB		 5597 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5598 register_prefix,
5599 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5600 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5601#endif
5602 }
5603 return 1;
5604}
252b5132 5605
29b0f896 5606static int
40fb9820 5607update_imm (unsigned int j)
29b0f896 5608{
bc0844ae 5609 i386_operand_type overlap = i.types[j];
40fb9820
L		 5610 if ((overlap.bitfield.imm8
5611 || overlap.bitfield.imm8s
5612 || overlap.bitfield.imm16
5613 || overlap.bitfield.imm32
5614 || overlap.bitfield.imm32s
5615 || overlap.bitfield.imm64)
0dfbf9d7
L		 5616 && !operand_type_equal (&overlap, &imm8)
5617 && !operand_type_equal (&overlap, &imm8s)
5618 && !operand_type_equal (&overlap, &imm16)
5619 && !operand_type_equal (&overlap, &imm32)
5620 && !operand_type_equal (&overlap, &imm32s)
5621 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5622 {
5623 if (i.suffix)
5624 {
40fb9820
L		 5625 i386_operand_type temp;
5626
0dfbf9d7 5627 operand_type_set (&temp, 0);
7ab9ffdd 5628 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5629 {
5630 temp.bitfield.imm8 = overlap.bitfield.imm8;
5631 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5632 }
5633 else if (i.suffix == WORD_MNEM_SUFFIX)
5634 temp.bitfield.imm16 = overlap.bitfield.imm16;
5635 else if (i.suffix == QWORD_MNEM_SUFFIX)
5636 {
5637 temp.bitfield.imm64 = overlap.bitfield.imm64;
5638 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5639 }
5640 else
5641 temp.bitfield.imm32 = overlap.bitfield.imm32;
5642 overlap = temp;
29b0f896 5643 }
0dfbf9d7
L		 5644 else if (operand_type_equal (&overlap, &imm16_32_32s)
5645 || operand_type_equal (&overlap, &imm16_32)
5646 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5647 {
40fb9820 5648 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5649 overlap = imm16;
40fb9820 5650 else
65da13b5 5651 overlap = imm32s;
29b0f896 5652 }
0dfbf9d7
L		 5653 if (!operand_type_equal (&overlap, &imm8)
5654 && !operand_type_equal (&overlap, &imm8s)
5655 && !operand_type_equal (&overlap, &imm16)
5656 && !operand_type_equal (&overlap, &imm32)
5657 && !operand_type_equal (&overlap, &imm32s)
5658 && !operand_type_equal (&overlap, &imm64))
29b0f896 5659 {
4eed87de
AM		 5660 as_bad (_("no instruction mnemonic suffix given; "
5661 "can't determine immediate size"));
29b0f896
AM		 5662 return 0;
5663 }
5664 }
40fb9820 5665 i.types[j] = overlap;
29b0f896 5666
40fb9820
L		 5667 return 1;
5668}
5669
5670static int
5671finalize_imm (void)
5672{
bc0844ae 5673 unsigned int j, n;
29b0f896 5674
bc0844ae
L		 5675 /* Update the first 2 immediate operands. */
5676 n = i.operands > 2 ? 2 : i.operands;
5677 if (n)
5678 {
5679 for (j = 0; j < n; j++)
5680 if (update_imm (j) == 0)
5681 return 0;
40fb9820 5682
bc0844ae
L		 5683 /* The 3rd operand can't be immediate operand. */
5684 gas_assert (operand_type_check (i.types[2], imm) == 0);
5685 }
29b0f896
AM		 5686
5687 return 1;
5688}
5689
c0f3af97
L		 5690static int
5691bad_implicit_operand (int xmm)
5692{
91d6fa6a
NC		 5693 const char *ireg = xmm ? "xmm0" : "ymm0";
5694
c0f3af97
L		 5695 if (intel_syntax)
5696 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5697 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5698 else
5699 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5700 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5701 return 0;
5702}
5703
29b0f896 5704static int
e3bb37b5 5705process_operands (void)
29b0f896
AM		 5706{
5707 /* Default segment register this instruction will use for memory
5708 accesses. 0 means unknown. This is only for optimizing out
5709 unnecessary segment overrides. */
5710 const seg_entry *default_seg = 0;
5711
2426c15f 5712 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5713 {
91d6fa6a
NC		 5714 unsigned int dupl = i.operands;
5715 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5716 unsigned int j;
5717
c0f3af97 5718 /* The destination must be an xmm register. */
9c2799c2 5719 gas_assert (i.reg_operands
91d6fa6a 5720 && MAX_OPERANDS > dupl
7ab9ffdd 5721 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5722
5723 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5724 {
c0f3af97 5725 /* The first operand is implicit and must be xmm0. */
9c2799c2 5726 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5727 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5728 return bad_implicit_operand (1);
5729
8cd7925b 5730 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5731 {
5732 /* Keep xmm0 for instructions with VEX prefix and 3
5733 sources. */
5734 goto duplicate;
5735 }
e2ec9d29 5736 else
c0f3af97
L		 5737 {
5738 /* We remove the first xmm0 and keep the number of
5739 operands unchanged, which in fact duplicates the
5740 destination. */
5741 for (j = 1; j < i.operands; j++)
5742 {
5743 i.op[j - 1] = i.op[j];
5744 i.types[j - 1] = i.types[j];
5745 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5746 }
5747 }
5748 }
5749 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5750 {
91d6fa6a 5751 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5752 && (i.tm.opcode_modifier.vexsources
5753 == VEX3SOURCES));
c0f3af97
L		 5754
5755 /* Add the implicit xmm0 for instructions with VEX prefix
5756 and 3 sources. */
5757 for (j = i.operands; j > 0; j--)
5758 {
5759 i.op[j] = i.op[j - 1];
5760 i.types[j] = i.types[j - 1];
5761 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5762 }
5763 i.op[0].regs
5764 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5765 i.types[0] = regxmm;
c0f3af97
L		 5766 i.tm.operand_types[0] = regxmm;
5767
5768 i.operands += 2;
5769 i.reg_operands += 2;
5770 i.tm.operands += 2;
5771
91d6fa6a 5772 dupl++;
c0f3af97 5773 dest++;
91d6fa6a
NC		 5774 i.op[dupl] = i.op[dest];
5775 i.types[dupl] = i.types[dest];
5776 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5777 }
c0f3af97
L		 5778 else
5779 {
5780duplicate:
5781 i.operands++;
5782 i.reg_operands++;
5783 i.tm.operands++;
5784
91d6fa6a
NC		 5785 i.op[dupl] = i.op[dest];
5786 i.types[dupl] = i.types[dest];
5787 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5788 }
5789
5790 if (i.tm.opcode_modifier.immext)
5791 process_immext ();
5792 }
5793 else if (i.tm.opcode_modifier.firstxmm0)
5794 {
5795 unsigned int j;
5796
43234a1e 5797 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5798 gas_assert (i.reg_operands
7ab9ffdd 5799 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5800 || operand_type_equal (&i.types[0], &regymm)
5801 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5802 if (register_number (i.op[0].regs) != 0)
c0f3af97 5803 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5804
5805 for (j = 1; j < i.operands; j++)
5806 {
5807 i.op[j - 1] = i.op[j];
5808 i.types[j - 1] = i.types[j];
5809
5810 /* We need to adjust fields in i.tm since they are used by
5811 build_modrm_byte. */
5812 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5813 }
5814
e2ec9d29
L		 5815 i.operands--;
5816 i.reg_operands--;
e2ec9d29
L		 5817 i.tm.operands--;
5818 }
5819 else if (i.tm.opcode_modifier.regkludge)
5820 {
5821 /* The imul $imm, %reg instruction is converted into
5822 imul $imm, %reg, %reg, and the clr %reg instruction
5823 is converted into xor %reg, %reg. */
5824
5825 unsigned int first_reg_op;
5826
5827 if (operand_type_check (i.types[0], reg))
5828 first_reg_op = 0;
5829 else
5830 first_reg_op = 1;
5831 /* Pretend we saw the extra register operand. */
9c2799c2 5832 gas_assert (i.reg_operands == 1
7ab9ffdd 5833 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5834 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5835 i.types[first_reg_op + 1] = i.types[first_reg_op];
5836 i.operands++;
5837 i.reg_operands++;
29b0f896
AM		 5838 }
5839
40fb9820 5840 if (i.tm.opcode_modifier.shortform)
29b0f896 5841 {
40fb9820
L		 5842 if (i.types[0].bitfield.sreg2
5843 || i.types[0].bitfield.sreg3)
29b0f896 5844 {
4eed87de
AM		 5845 if (i.tm.base_opcode == POP_SEG_SHORT
5846 && i.op[0].regs->reg_num == 1)
29b0f896 5847 {
a87af027 5848 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5849 return 0;
29b0f896 5850 }
4eed87de
AM		 5851 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5852 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5853 i.rex |= REX_B;
4eed87de
AM		 5854 }
5855 else
5856 {
7ab9ffdd 5857 /* The register or float register operand is in operand
85f10a01 5858 0 or 1. */
40fb9820 5859 unsigned int op;
7ab9ffdd
L		 5860
5861 if (i.types[0].bitfield.floatreg
5862 || operand_type_check (i.types[0], reg))
5863 op = 0;
5864 else
5865 op = 1;
4eed87de
AM		 5866 /* Register goes in low 3 bits of opcode. */
5867 i.tm.base_opcode |= i.op[op].regs->reg_num;
5868 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5869 i.rex |= REX_B;
40fb9820 5870 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5871 {
4eed87de
AM		 5872 /* Warn about some common errors, but press on regardless.
5873 The first case can be generated by gcc (<= 2.8.1). */
5874 if (i.operands == 2)
5875 {
5876 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5877 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5878 register_prefix, i.op[!intel_syntax].regs->reg_name,
5879 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5880 }
5881 else
5882 {
5883 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5884 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5885 register_prefix, i.op[0].regs->reg_name);
4eed87de 5886 }
29b0f896
AM		 5887 }
5888 }
5889 }
40fb9820 5890 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5891 {
5892 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5893 must be put into the modrm byte). Now, we make the modrm and
5894 index base bytes based on all the info we've collected. */
29b0f896
AM		 5895
5896 default_seg = build_modrm_byte ();
5897 }
8a2ed489 5898 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5899 {
5900 default_seg = &ds;
5901 }
40fb9820 5902 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5903 {
5904 /* For the string instructions that allow a segment override
5905 on one of their operands, the default segment is ds. */
5906 default_seg = &ds;
5907 }
5908
75178d9d
L		 5909 if (i.tm.base_opcode == 0x8d /* lea */
5910 && i.seg[0]
5911 && !quiet_warnings)
30123838 5912 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5913
5914 /* If a segment was explicitly specified, and the specified segment
5915 is not the default, use an opcode prefix to select it. If we
5916 never figured out what the default segment is, then default_seg
5917 will be zero at this point, and the specified segment prefix will
5918 always be used. */
29b0f896
AM		 5919 if ((i.seg[0]) && (i.seg[0] != default_seg))
5920 {
5921 if (!add_prefix (i.seg[0]->seg_prefix))
5922 return 0;
5923 }
5924 return 1;
5925}
5926
5927static const seg_entry *
e3bb37b5 5928build_modrm_byte (void)
29b0f896
AM		 5929{
5930 const seg_entry *default_seg = 0;
c0f3af97 5931 unsigned int source, dest;
8cd7925b 5932 int vex_3_sources;
c0f3af97
L		 5933
5934 /* The first operand of instructions with VEX prefix and 3 sources
5935 must be VEX_Imm4. */
8cd7925b 5936 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5937 if (vex_3_sources)
5938 {
91d6fa6a 5939 unsigned int nds, reg_slot;
4c2c6516 5940 expressionS *exp;
c0f3af97 5941
922d8de8 5942 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5943 && i.tm.opcode_modifier.immext)
5944 {
5945 dest = i.operands - 2;
5946 gas_assert (dest == 3);
5947 }
922d8de8 5948 else
a683cc34 5949 dest = i.operands - 1;
c0f3af97 5950 nds = dest - 1;
922d8de8 5951
a683cc34
SP		 5952 /* There are 2 kinds of instructions:
5953 1. 5 operands: 4 register operands or 3 register operands
5954 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5955 VexW0 or VexW1. The destination must be either XMM, YMM or
5956 ZMM register.
a683cc34
SP		 5957 2. 4 operands: 4 register operands or 3 register operands
5958 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5959 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5960 || (i.reg_operands == 3 && i.mem_operands == 1))
5961 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5962 && (i.tm.opcode_modifier.veximmext
5963 || (i.imm_operands == 1
5964 && i.types[0].bitfield.vec_imm4
5965 && (i.tm.opcode_modifier.vexw == VEXW0
5966 || i.tm.opcode_modifier.vexw == VEXW1)
5967 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5968 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5969 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5970
5971 if (i.imm_operands == 0)
5972 {
5973 /* When there is no immediate operand, generate an 8bit
5974 immediate operand to encode the first operand. */
5975 exp = &im_expressions[i.imm_operands++];
5976 i.op[i.operands].imms = exp;
5977 i.types[i.operands] = imm8;
5978 i.operands++;
5979 /* If VexW1 is set, the first operand is the source and
5980 the second operand is encoded in the immediate operand. */
5981 if (i.tm.opcode_modifier.vexw == VEXW1)
5982 {
5983 source = 0;
5984 reg_slot = 1;
5985 }
5986 else
5987 {
5988 source = 1;
5989 reg_slot = 0;
5990 }
5991
5992 /* FMA swaps REG and NDS. */
5993 if (i.tm.cpu_flags.bitfield.cpufma)
5994 {
5995 unsigned int tmp;
5996 tmp = reg_slot;
5997 reg_slot = nds;
5998 nds = tmp;
5999 }
6000
24981e7b
L		 6001 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6002 &regxmm)
a683cc34 6003 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6004 &regymm)
6005 || operand_type_equal (&i.tm.operand_types[reg_slot],
6006 &regzmm));
a683cc34 6007 exp->X_op = O_constant;
4c692bc7 6008 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6009 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6010 }
922d8de8 6011 else
a683cc34
SP		 6012 {
6013 unsigned int imm_slot;
6014
6015 if (i.tm.opcode_modifier.vexw == VEXW0)
6016 {
6017 /* If VexW0 is set, the third operand is the source and
6018 the second operand is encoded in the immediate
6019 operand. */
6020 source = 2;
6021 reg_slot = 1;
6022 }
6023 else
6024 {
6025 /* VexW1 is set, the second operand is the source and
6026 the third operand is encoded in the immediate
6027 operand. */
6028 source = 1;
6029 reg_slot = 2;
6030 }
6031
6032 if (i.tm.opcode_modifier.immext)
6033 {
6034 /* When ImmExt is set, the immdiate byte is the last
6035 operand. */
6036 imm_slot = i.operands - 1;
6037 source--;
6038 reg_slot--;
6039 }
6040 else
6041 {
6042 imm_slot = 0;
6043
6044 /* Turn on Imm8 so that output_imm will generate it. */
6045 i.types[imm_slot].bitfield.imm8 = 1;
6046 }
6047
24981e7b
L		 6048 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6049 &regxmm)
6050 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6051 &regymm)
6052 || operand_type_equal (&i.tm.operand_types[reg_slot],
6053 &regzmm));
a683cc34 6054 i.op[imm_slot].imms->X_add_number
4c692bc7 6055 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6056 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6057 }
6058
6059 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6060 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6061 &regymm)
6062 || operand_type_equal (&i.tm.operand_types[nds],
6063 &regzmm));
dae39acc 6064 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6065 }
6066 else
6067 source = dest = 0;
29b0f896
AM		 6068
6069 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6070 implicit registers do not count. If there are 3 register
6071 operands, it must be a instruction with VexNDS. For a
6072 instruction with VexNDD, the destination register is encoded
6073 in VEX prefix. If there are 4 register operands, it must be
6074 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6075 if (i.mem_operands == 0
6076 && ((i.reg_operands == 2
2426c15f 6077 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6078 || (i.reg_operands == 3
2426c15f 6079 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6080 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6081 {
cab737b9
L		 6082 switch (i.operands)
6083 {
6084 case 2:
6085 source = 0;
6086 break;
6087 case 3:
c81128dc
L		 6088 /* When there are 3 operands, one of them may be immediate,
6089 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6090 the first operand must be shift count register (cl) or it
6091 is an instruction with VexNDS. */
9c2799c2 6092 gas_assert (i.imm_operands == 1
7ab9ffdd 6093 || (i.imm_operands == 0
2426c15f 6094 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6095 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6096 if (operand_type_check (i.types[0], imm)
6097 || i.types[0].bitfield.shiftcount)
6098 source = 1;
6099 else
6100 source = 0;
cab737b9
L		 6101 break;
6102 case 4:
368d64cc
L		 6103 /* When there are 4 operands, the first two must be 8bit
6104 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6105 one.
6106
6107 For instructions with VexNDS, if the first operand
6108 an imm8, the source operand is the 2nd one. If the last
6109 operand is imm8, the source operand is the first one. */
9c2799c2 6110 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6111 && i.types[0].bitfield.imm8
6112 && i.types[1].bitfield.imm8)
2426c15f 6113 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6114 && i.imm_operands == 1
6115 && (i.types[0].bitfield.imm8
43234a1e
L		 6116 || i.types[i.operands - 1].bitfield.imm8
6117 || i.rounding)));
9f2670f2
L		 6118 if (i.imm_operands == 2)
6119 source = 2;
6120 else
c0f3af97
L		 6121 {
6122 if (i.types[0].bitfield.imm8)
6123 source = 1;
6124 else
6125 source = 0;
6126 }
c0f3af97
L		 6127 break;
6128 case 5:
43234a1e
L		 6129 if (i.tm.opcode_modifier.evex)
6130 {
6131 /* For EVEX instructions, when there are 5 operands, the
6132 first one must be immediate operand. If the second one
6133 is immediate operand, the source operand is the 3th
6134 one. If the last one is immediate operand, the source
6135 operand is the 2nd one. */
6136 gas_assert (i.imm_operands == 2
6137 && i.tm.opcode_modifier.sae
6138 && operand_type_check (i.types[0], imm));
6139 if (operand_type_check (i.types[1], imm))
6140 source = 2;
6141 else if (operand_type_check (i.types[4], imm))
6142 source = 1;
6143 else
6144 abort ();
6145 }
cab737b9
L		 6146 break;
6147 default:
6148 abort ();
6149 }
6150
c0f3af97
L		 6151 if (!vex_3_sources)
6152 {
6153 dest = source + 1;
6154
43234a1e
L		 6155 /* RC/SAE operand could be between DEST and SRC. That happens
6156 when one operand is GPR and the other one is XMM/YMM/ZMM
6157 register. */
6158 if (i.rounding && i.rounding->operand == (int) dest)
6159 dest++;
6160
2426c15f 6161 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6162 {
43234a1e
L		 6163 /* For instructions with VexNDS, the register-only source
6164 operand must be 32/64bit integer, XMM, YMM or ZMM
6165 register. It is encoded in VEX prefix. We need to
6166 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6167
6168 i386_operand_type op;
6169 unsigned int vvvv;
6170
6171 /* Check register-only source operand when two source
6172 operands are swapped. */
6173 if (!i.tm.operand_types[source].bitfield.baseindex
6174 && i.tm.operand_types[dest].bitfield.baseindex)
6175 {
6176 vvvv = source;
6177 source = dest;
6178 }
6179 else
6180 vvvv = dest;
6181
6182 op = i.tm.operand_types[vvvv];
fa99fab2 6183 op.bitfield.regmem = 0;
c0f3af97 6184 if ((dest + 1) >= i.operands
ac4eb736
AM		 6185 || (!op.bitfield.reg32
6186 && op.bitfield.reg64
f12dc422 6187 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6188 && !operand_type_equal (&op, &regymm)
6189 && !operand_type_equal (&op, &regzmm)
6190 && !operand_type_equal (&op, &regmask)))
c0f3af97 6191 abort ();
f12dc422 6192 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6193 dest++;
6194 }
6195 }
29b0f896
AM		 6196
6197 i.rm.mode = 3;
6198 /* One of the register operands will be encoded in the i.tm.reg
6199 field, the other in the combined i.tm.mode and i.tm.regmem
6200 fields. If no form of this instruction supports a memory
6201 destination operand, then we assume the source operand may
6202 sometimes be a memory operand and so we need to store the
6203 destination in the i.rm.reg field. */
40fb9820
L		 6204 if (!i.tm.operand_types[dest].bitfield.regmem
6205 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6206 {
6207 i.rm.reg = i.op[dest].regs->reg_num;
6208 i.rm.regmem = i.op[source].regs->reg_num;
6209 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6210 i.rex |= REX_R;
43234a1e
L		 6211 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6212 i.vrex |= REX_R;
29b0f896 6213 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6214 i.rex |= REX_B;
43234a1e
L		 6215 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6216 i.vrex |= REX_B;
29b0f896
AM		 6217 }
6218 else
6219 {
6220 i.rm.reg = i.op[source].regs->reg_num;
6221 i.rm.regmem = i.op[dest].regs->reg_num;
6222 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6223 i.rex |= REX_B;
43234a1e
L		 6224 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6225 i.vrex |= REX_B;
29b0f896 6226 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6227 i.rex |= REX_R;
43234a1e
L		 6228 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6229 i.vrex |= REX_R;
29b0f896 6230 }
161a04f6 6231 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6232 {
40fb9820
L		 6233 if (!i.types[0].bitfield.control
6234 && !i.types[1].bitfield.control)
c4a530c5 6235 abort ();
161a04f6 6236 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6237 add_prefix (LOCK_PREFIX_OPCODE);
6238 }
29b0f896
AM		 6239 }
6240 else
6241 { /* If it's not 2 reg operands... */
c0f3af97
L		 6242 unsigned int mem;
6243
29b0f896
AM		 6244 if (i.mem_operands)
6245 {
6246 unsigned int fake_zero_displacement = 0;
99018f42 6247 unsigned int op;
4eed87de 6248
7ab9ffdd
L		 6249 for (op = 0; op < i.operands; op++)
6250 if (operand_type_check (i.types[op], anymem))
6251 break;
7ab9ffdd 6252 gas_assert (op < i.operands);
29b0f896 6253
6c30d220
L		 6254 if (i.tm.opcode_modifier.vecsib)
6255 {
6256 if (i.index_reg->reg_num == RegEiz
6257 || i.index_reg->reg_num == RegRiz)
6258 abort ();
6259
6260 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6261 if (!i.base_reg)
6262 {
6263 i.sib.base = NO_BASE_REGISTER;
6264 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6265 /* No Vec_Disp8 if there is no base. */
6266 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6267 i.types[op].bitfield.disp8 = 0;
6268 i.types[op].bitfield.disp16 = 0;
6269 i.types[op].bitfield.disp64 = 0;
6270 if (flag_code != CODE_64BIT)
6271 {
6272 /* Must be 32 bit */
6273 i.types[op].bitfield.disp32 = 1;
6274 i.types[op].bitfield.disp32s = 0;
6275 }
6276 else
6277 {
6278 i.types[op].bitfield.disp32 = 0;
6279 i.types[op].bitfield.disp32s = 1;
6280 }
6281 }
6282 i.sib.index = i.index_reg->reg_num;
6283 if ((i.index_reg->reg_flags & RegRex) != 0)
6284 i.rex |= REX_X;
43234a1e
L		 6285 if ((i.index_reg->reg_flags & RegVRex) != 0)
6286 i.vrex |= REX_X;
6c30d220
L		 6287 }
6288
29b0f896
AM		 6289 default_seg = &ds;
6290
6291 if (i.base_reg == 0)
6292 {
6293 i.rm.mode = 0;
6294 if (!i.disp_operands)
6c30d220
L		 6295 {
6296 fake_zero_displacement = 1;
6297 /* Instructions with VSIB byte need 32bit displacement
6298 if there is no base register. */
6299 if (i.tm.opcode_modifier.vecsib)
6300 i.types[op].bitfield.disp32 = 1;
6301 }
29b0f896
AM		 6302 if (i.index_reg == 0)
6303 {
6c30d220 6304 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6305 /* Operand is just <disp> */
20f0a1fc 6306 if (flag_code == CODE_64BIT)
29b0f896
AM		 6307 {
6308 /* 64bit mode overwrites the 32bit absolute
6309 addressing by RIP relative addressing and
6310 absolute addressing is encoded by one of the
6311 redundant SIB forms. */
6312 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6313 i.sib.base = NO_BASE_REGISTER;
6314 i.sib.index = NO_INDEX_REGISTER;
fc225355 6315 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6316 ? disp32s : disp32);
20f0a1fc 6317 }
fc225355
L		 6318 else if ((flag_code == CODE_16BIT)
6319 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6320 {
6321 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6322 i.types[op] = disp16;
20f0a1fc
NC		 6323 }
6324 else
6325 {
6326 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6327 i.types[op] = disp32;
29b0f896
AM		 6328 }
6329 }
6c30d220 6330 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6331 {
6c30d220 6332 /* !i.base_reg && i.index_reg */
db51cc60
L		 6333 if (i.index_reg->reg_num == RegEiz
6334 || i.index_reg->reg_num == RegRiz)
6335 i.sib.index = NO_INDEX_REGISTER;
6336 else
6337 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6338 i.sib.base = NO_BASE_REGISTER;
6339 i.sib.scale = i.log2_scale_factor;
6340 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6341 /* No Vec_Disp8 if there is no base. */
6342 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6343 i.types[op].bitfield.disp8 = 0;
6344 i.types[op].bitfield.disp16 = 0;
6345 i.types[op].bitfield.disp64 = 0;
29b0f896 6346 if (flag_code != CODE_64BIT)
40fb9820
L		 6347 {
6348 /* Must be 32 bit */
6349 i.types[op].bitfield.disp32 = 1;
6350 i.types[op].bitfield.disp32s = 0;
6351 }
29b0f896 6352 else
40fb9820
L		 6353 {
6354 i.types[op].bitfield.disp32 = 0;
6355 i.types[op].bitfield.disp32s = 1;
6356 }
29b0f896 6357 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6358 i.rex |= REX_X;
29b0f896
AM		 6359 }
6360 }
6361 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6362 else if (i.base_reg->reg_num == RegRip ||
6363 i.base_reg->reg_num == RegEip)
29b0f896 6364 {
6c30d220 6365 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6366 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6367 i.types[op].bitfield.disp8 = 0;
6368 i.types[op].bitfield.disp16 = 0;
6369 i.types[op].bitfield.disp32 = 0;
6370 i.types[op].bitfield.disp32s = 1;
6371 i.types[op].bitfield.disp64 = 0;
43234a1e 6372 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6373 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6374 if (! i.disp_operands)
6375 fake_zero_displacement = 1;
29b0f896 6376 }
40fb9820 6377 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6378 {
6c30d220 6379 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6380 switch (i.base_reg->reg_num)
6381 {
6382 case 3: /* (%bx) */
6383 if (i.index_reg == 0)
6384 i.rm.regmem = 7;
6385 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6386 i.rm.regmem = i.index_reg->reg_num - 6;
6387 break;
6388 case 5: /* (%bp) */
6389 default_seg = &ss;
6390 if (i.index_reg == 0)
6391 {
6392 i.rm.regmem = 6;
40fb9820 6393 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6394 {
6395 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6396 if (i.tm.operand_types[op].bitfield.vec_disp8)
6397 i.types[op].bitfield.vec_disp8 = 1;
6398 else
6399 i.types[op].bitfield.disp8 = 1;
252b5132 6400 fake_zero_displacement = 1;
29b0f896
AM		 6401 }
6402 }
6403 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6404 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6405 break;
6406 default: /* (%si) -> 4 or (%di) -> 5 */
6407 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6408 }
6409 i.rm.mode = mode_from_disp_size (i.types[op]);
6410 }
6411 else /* i.base_reg and 32/64 bit mode */
6412 {
6413 if (flag_code == CODE_64BIT
40fb9820
L		 6414 && operand_type_check (i.types[op], disp))
6415 {
6416 i386_operand_type temp;
0dfbf9d7 6417 operand_type_set (&temp, 0);
40fb9820 6418 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6419 temp.bitfield.vec_disp8
6420 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6421 i.types[op] = temp;
6422 if (i.prefix[ADDR_PREFIX] == 0)
6423 i.types[op].bitfield.disp32s = 1;
6424 else
6425 i.types[op].bitfield.disp32 = 1;
6426 }
20f0a1fc 6427
6c30d220
L		 6428 if (!i.tm.opcode_modifier.vecsib)
6429 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6430 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6431 i.rex |= REX_B;
29b0f896
AM		 6432 i.sib.base = i.base_reg->reg_num;
6433 /* x86-64 ignores REX prefix bit here to avoid decoder
6434 complications. */
848930b2
JB		 6435 if (!(i.base_reg->reg_flags & RegRex)
6436 && (i.base_reg->reg_num == EBP_REG_NUM
6437 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6438 default_seg = &ss;
848930b2 6439 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6440 {
848930b2 6441 fake_zero_displacement = 1;
43234a1e
L		 6442 if (i.tm.operand_types [op].bitfield.vec_disp8)
6443 i.types[op].bitfield.vec_disp8 = 1;
6444 else
6445 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6446 }
6447 i.sib.scale = i.log2_scale_factor;
6448 if (i.index_reg == 0)
6449 {
6c30d220 6450 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6451 /* <disp>(%esp) becomes two byte modrm with no index
6452 register. We've already stored the code for esp
6453 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6454 Any base register besides %esp will not use the
6455 extra modrm byte. */
6456 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6457 }
6c30d220 6458 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6459 {
db51cc60
L		 6460 if (i.index_reg->reg_num == RegEiz
6461 || i.index_reg->reg_num == RegRiz)
6462 i.sib.index = NO_INDEX_REGISTER;
6463 else
6464 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6465 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6466 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6467 i.rex |= REX_X;
29b0f896 6468 }
67a4f2b7
AO		 6469
6470 if (i.disp_operands
6471 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6472 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6473 i.rm.mode = 0;
6474 else
a501d77e
L		 6475 {
6476 if (!fake_zero_displacement
6477 && !i.disp_operands
6478 && i.disp_encoding)
6479 {
6480 fake_zero_displacement = 1;
6481 if (i.disp_encoding == disp_encoding_8bit)
6482 i.types[op].bitfield.disp8 = 1;
6483 else
6484 i.types[op].bitfield.disp32 = 1;
6485 }
6486 i.rm.mode = mode_from_disp_size (i.types[op]);
6487 }
29b0f896 6488 }
252b5132 6489
29b0f896
AM		 6490 if (fake_zero_displacement)
6491 {
6492 /* Fakes a zero displacement assuming that i.types[op]
6493 holds the correct displacement size. */
6494 expressionS *exp;
6495
9c2799c2 6496 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6497 exp = &disp_expressions[i.disp_operands++];
6498 i.op[op].disps = exp;
6499 exp->X_op = O_constant;
6500 exp->X_add_number = 0;
6501 exp->X_add_symbol = (symbolS *) 0;
6502 exp->X_op_symbol = (symbolS *) 0;
6503 }
c0f3af97
L		 6504
6505 mem = op;
29b0f896 6506 }
c0f3af97
L		 6507 else
6508 mem = ~0;
252b5132 6509
8c43a48b 6510 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6511 {
6512 if (operand_type_check (i.types[0], imm))
6513 i.vex.register_specifier = NULL;
6514 else
6515 {
6516 /* VEX.vvvv encodes one of the sources when the first
6517 operand is not an immediate. */
1ef99a7b 6518 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6519 i.vex.register_specifier = i.op[0].regs;
6520 else
6521 i.vex.register_specifier = i.op[1].regs;
6522 }
6523
6524 /* Destination is a XMM register encoded in the ModRM.reg
6525 and VEX.R bit. */
6526 i.rm.reg = i.op[2].regs->reg_num;
6527 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6528 i.rex |= REX_R;
6529
6530 /* ModRM.rm and VEX.B encodes the other source. */
6531 if (!i.mem_operands)
6532 {
6533 i.rm.mode = 3;
6534
1ef99a7b 6535 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6536 i.rm.regmem = i.op[1].regs->reg_num;
6537 else
6538 i.rm.regmem = i.op[0].regs->reg_num;
6539
6540 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6541 i.rex |= REX_B;
6542 }
6543 }
2426c15f 6544 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6545 {
6546 i.vex.register_specifier = i.op[2].regs;
6547 if (!i.mem_operands)
6548 {
6549 i.rm.mode = 3;
6550 i.rm.regmem = i.op[1].regs->reg_num;
6551 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6552 i.rex |= REX_B;
6553 }
6554 }
29b0f896
AM		 6555 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6556 (if any) based on i.tm.extension_opcode. Again, we must be
6557 careful to make sure that segment/control/debug/test/MMX
6558 registers are coded into the i.rm.reg field. */
f88c9eb0 6559 else if (i.reg_operands)
29b0f896 6560 {
99018f42 6561 unsigned int op;
7ab9ffdd
L		 6562 unsigned int vex_reg = ~0;
6563
6564 for (op = 0; op < i.operands; op++)
6565 if (i.types[op].bitfield.reg8
6566 || i.types[op].bitfield.reg16
6567 || i.types[op].bitfield.reg32
6568 || i.types[op].bitfield.reg64
6569 || i.types[op].bitfield.regmmx
6570 || i.types[op].bitfield.regxmm
6571 || i.types[op].bitfield.regymm
7e8b059b 6572 || i.types[op].bitfield.regbnd
43234a1e
L		 6573 || i.types[op].bitfield.regzmm
6574 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6575 || i.types[op].bitfield.sreg2
6576 || i.types[op].bitfield.sreg3
6577 || i.types[op].bitfield.control
6578 || i.types[op].bitfield.debug
6579 || i.types[op].bitfield.test)
6580 break;
c0209578 6581
7ab9ffdd
L		 6582 if (vex_3_sources)
6583 op = dest;
2426c15f 6584 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6585 {
6586 /* For instructions with VexNDS, the register-only
6587 source operand is encoded in VEX prefix. */
6588 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6589
7ab9ffdd 6590 if (op > mem)
c0f3af97 6591 {
7ab9ffdd
L		 6592 vex_reg = op++;
6593 gas_assert (op < i.operands);
c0f3af97
L		 6594 }
6595 else
c0f3af97 6596 {
f12dc422
L		 6597 /* Check register-only source operand when two source
6598 operands are swapped. */
6599 if (!i.tm.operand_types[op].bitfield.baseindex
6600 && i.tm.operand_types[op + 1].bitfield.baseindex)
6601 {
6602 vex_reg = op;
6603 op += 2;
6604 gas_assert (mem == (vex_reg + 1)
6605 && op < i.operands);
6606 }
6607 else
6608 {
6609 vex_reg = op + 1;
6610 gas_assert (vex_reg < i.operands);
6611 }
c0f3af97 6612 }
7ab9ffdd 6613 }
2426c15f 6614 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6615 {
f12dc422 6616 /* For instructions with VexNDD, the register destination
7ab9ffdd 6617 is encoded in VEX prefix. */
f12dc422
L		 6618 if (i.mem_operands == 0)
6619 {
6620 /* There is no memory operand. */
6621 gas_assert ((op + 2) == i.operands);
6622 vex_reg = op + 1;
6623 }
6624 else
8d63c93e 6625 {
f12dc422
L		 6626 /* There are only 2 operands. */
6627 gas_assert (op < 2 && i.operands == 2);
6628 vex_reg = 1;
6629 }
7ab9ffdd
L		 6630 }
6631 else
6632 gas_assert (op < i.operands);
99018f42 6633
7ab9ffdd
L		 6634 if (vex_reg != (unsigned int) ~0)
6635 {
f12dc422 6636 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6637
f12dc422
L		 6638 if (type->bitfield.reg32 != 1
6639 && type->bitfield.reg64 != 1
6640 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6641 && !operand_type_equal (type, &regymm)
6642 && !operand_type_equal (type, &regzmm)
6643 && !operand_type_equal (type, &regmask))
7ab9ffdd 6644 abort ();
f88c9eb0 6645
7ab9ffdd
L		 6646 i.vex.register_specifier = i.op[vex_reg].regs;
6647 }
6648
1b9f0c97
L		 6649 /* Don't set OP operand twice. */
6650 if (vex_reg != op)
7ab9ffdd 6651 {
1b9f0c97
L		 6652 /* If there is an extension opcode to put here, the
6653 register number must be put into the regmem field. */
6654 if (i.tm.extension_opcode != None)
6655 {
6656 i.rm.regmem = i.op[op].regs->reg_num;
6657 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6658 i.rex |= REX_B;
43234a1e
L		 6659 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6660 i.vrex |= REX_B;
1b9f0c97
L		 6661 }
6662 else
6663 {
6664 i.rm.reg = i.op[op].regs->reg_num;
6665 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6666 i.rex |= REX_R;
43234a1e
L		 6667 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6668 i.vrex |= REX_R;
1b9f0c97 6669 }
7ab9ffdd 6670 }
252b5132 6671
29b0f896
AM		 6672 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6673 must set it to 3 to indicate this is a register operand
6674 in the regmem field. */
6675 if (!i.mem_operands)
6676 i.rm.mode = 3;
6677 }
252b5132 6678
29b0f896 6679 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6680 if (i.tm.extension_opcode != None)
29b0f896
AM		 6681 i.rm.reg = i.tm.extension_opcode;
6682 }
6683 return default_seg;
6684}
252b5132 6685
29b0f896 6686static void
e3bb37b5 6687output_branch (void)
29b0f896
AM		 6688{
6689 char *p;
f8a5c266 6690 int size;
29b0f896
AM		 6691 int code16;
6692 int prefix;
6693 relax_substateT subtype;
6694 symbolS *sym;
6695 offsetT off;
6696
f8a5c266 6697 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6698 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6699
6700 prefix = 0;
6701 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6702 {
29b0f896
AM		 6703 prefix = 1;
6704 i.prefixes -= 1;
6705 code16 ^= CODE16;
252b5132 6706 }
29b0f896
AM		 6707 /* Pentium4 branch hints. */
6708 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6709 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6710 {
29b0f896
AM		 6711 prefix++;
6712 i.prefixes--;
6713 }
6714 if (i.prefix[REX_PREFIX] != 0)
6715 {
6716 prefix++;
6717 i.prefixes--;
2f66722d
AM		 6718 }
6719
7e8b059b
L		 6720 /* BND prefixed jump. */
6721 if (i.prefix[BND_PREFIX] != 0)
6722 {
6723 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6724 i.prefixes -= 1;
6725 }
6726
29b0f896
AM		 6727 if (i.prefixes != 0 && !intel_syntax)
6728 as_warn (_("skipping prefixes on this instruction"));
6729
6730 /* It's always a symbol; End frag & setup for relax.
6731 Make sure there is enough room in this frag for the largest
6732 instruction we may generate in md_convert_frag. This is 2
6733 bytes for the opcode and room for the prefix and largest
6734 displacement. */
6735 frag_grow (prefix + 2 + 4);
6736 /* Prefix and 1 opcode byte go in fr_fix. */
6737 p = frag_more (prefix + 1);
6738 if (i.prefix[DATA_PREFIX] != 0)
6739 *p++ = DATA_PREFIX_OPCODE;
6740 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6741 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6742 *p++ = i.prefix[SEG_PREFIX];
6743 if (i.prefix[REX_PREFIX] != 0)
6744 *p++ = i.prefix[REX_PREFIX];
6745 *p = i.tm.base_opcode;
6746
6747 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6748 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6749 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6750 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6751 else
f8a5c266 6752 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6753 subtype |= code16;
3e73aa7c 6754
29b0f896
AM		 6755 sym = i.op[0].disps->X_add_symbol;
6756 off = i.op[0].disps->X_add_number;
3e73aa7c 6757
29b0f896
AM		 6758 if (i.op[0].disps->X_op != O_constant
6759 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6760 {
29b0f896
AM		 6761 /* Handle complex expressions. */
6762 sym = make_expr_symbol (i.op[0].disps);
6763 off = 0;
6764 }
3e73aa7c 6765
29b0f896
AM		 6766 /* 1 possible extra opcode + 4 byte displacement go in var part.
6767 Pass reloc in fr_var. */
c3320543
L		 6768 frag_var (rs_machine_dependent, 5,
6769 ((!object_64bit
6770 || i.reloc[0] != NO_RELOC
6771 || (i.bnd_prefix == NULL && !add_bnd_prefix))
6772 ? i.reloc[0]
6773 : BFD_RELOC_X86_64_PC32_BND),
6774 subtype, sym, off, p);
29b0f896 6775}
3e73aa7c 6776
29b0f896 6777static void
e3bb37b5 6778output_jump (void)
29b0f896
AM		 6779{
6780 char *p;
6781 int size;
3e02c1cc 6782 fixS *fixP;
29b0f896 6783
40fb9820 6784 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6785 {
6786 /* This is a loop or jecxz type instruction. */
6787 size = 1;
6788 if (i.prefix[ADDR_PREFIX] != 0)
6789 {
6790 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6791 i.prefixes -= 1;
6792 }
6793 /* Pentium4 branch hints. */
6794 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6795 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6796 {
6797 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6798 i.prefixes--;
3e73aa7c
JH		 6799 }
6800 }
29b0f896
AM		 6801 else
6802 {
6803 int code16;
3e73aa7c 6804
29b0f896
AM		 6805 code16 = 0;
6806 if (flag_code == CODE_16BIT)
6807 code16 = CODE16;
3e73aa7c 6808
29b0f896
AM		 6809 if (i.prefix[DATA_PREFIX] != 0)
6810 {
6811 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6812 i.prefixes -= 1;
6813 code16 ^= CODE16;
6814 }
252b5132 6815
29b0f896
AM		 6816 size = 4;
6817 if (code16)
6818 size = 2;
6819 }
9fcc94b6 6820
29b0f896
AM		 6821 if (i.prefix[REX_PREFIX] != 0)
6822 {
6823 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6824 i.prefixes -= 1;
6825 }
252b5132 6826
7e8b059b
L		 6827 /* BND prefixed jump. */
6828 if (i.prefix[BND_PREFIX] != 0)
6829 {
6830 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6831 i.prefixes -= 1;
6832 }
6833
29b0f896
AM		 6834 if (i.prefixes != 0 && !intel_syntax)
6835 as_warn (_("skipping prefixes on this instruction"));
e0890092 6836
42164a71
L		 6837 p = frag_more (i.tm.opcode_length + size);
6838 switch (i.tm.opcode_length)
6839 {
6840 case 2:
6841 *p++ = i.tm.base_opcode >> 8;
6842 case 1:
6843 *p++ = i.tm.base_opcode;
6844 break;
6845 default:
6846 abort ();
6847 }
e0890092 6848
3e02c1cc 6849 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
c3320543
L		 6850 i.op[0].disps, 1, reloc (size, 1, 1,
6851 (i.bnd_prefix != NULL
6852 || add_bnd_prefix),
6853 i.reloc[0]));
3e02c1cc
AM		 6854
6855 /* All jumps handled here are signed, but don't use a signed limit
6856 check for 32 and 16 bit jumps as we want to allow wrap around at
6857 4G and 64k respectively. */
6858 if (size == 1)
6859 fixP->fx_signed = 1;
29b0f896 6860}
e0890092 6861
29b0f896 6862static void
e3bb37b5 6863output_interseg_jump (void)
29b0f896
AM		 6864{
6865 char *p;
6866 int size;
6867 int prefix;
6868 int code16;
252b5132 6869
29b0f896
AM		 6870 code16 = 0;
6871 if (flag_code == CODE_16BIT)
6872 code16 = CODE16;
a217f122 6873
29b0f896
AM		 6874 prefix = 0;
6875 if (i.prefix[DATA_PREFIX] != 0)
6876 {
6877 prefix = 1;
6878 i.prefixes -= 1;
6879 code16 ^= CODE16;
6880 }
6881 if (i.prefix[REX_PREFIX] != 0)
6882 {
6883 prefix++;
6884 i.prefixes -= 1;
6885 }
252b5132 6886
29b0f896
AM		 6887 size = 4;
6888 if (code16)
6889 size = 2;
252b5132 6890
29b0f896
AM		 6891 if (i.prefixes != 0 && !intel_syntax)
6892 as_warn (_("skipping prefixes on this instruction"));
252b5132 6893
29b0f896
AM		 6894 /* 1 opcode; 2 segment; offset */
6895 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6896
29b0f896
AM		 6897 if (i.prefix[DATA_PREFIX] != 0)
6898 *p++ = DATA_PREFIX_OPCODE;
252b5132 6899
29b0f896
AM		 6900 if (i.prefix[REX_PREFIX] != 0)
6901 *p++ = i.prefix[REX_PREFIX];
252b5132 6902
29b0f896
AM		 6903 *p++ = i.tm.base_opcode;
6904 if (i.op[1].imms->X_op == O_constant)
6905 {
6906 offsetT n = i.op[1].imms->X_add_number;
252b5132 6907
29b0f896
AM		 6908 if (size == 2
6909 && !fits_in_unsigned_word (n)
6910 && !fits_in_signed_word (n))
6911 {
6912 as_bad (_("16-bit jump out of range"));
6913 return;
6914 }
6915 md_number_to_chars (p, n, size);
6916 }
6917 else
6918 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
c3320543 6919 i.op[1].imms, 0, reloc (size, 0, 0, 0, i.reloc[1]));
29b0f896
AM		 6920 if (i.op[0].imms->X_op != O_constant)
6921 as_bad (_("can't handle non absolute segment in `%s'"),
6922 i.tm.name);
6923 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6924}
a217f122 6925
29b0f896 6926static void
e3bb37b5 6927output_insn (void)
29b0f896 6928{
2bbd9c25
JJ		 6929 fragS *insn_start_frag;
6930 offsetT insn_start_off;
6931
29b0f896
AM		 6932 /* Tie dwarf2 debug info to the address at the start of the insn.
6933 We can't do this after the insn has been output as the current
6934 frag may have been closed off. eg. by frag_var. */
6935 dwarf2_emit_insn (0);
6936
2bbd9c25
JJ		 6937 insn_start_frag = frag_now;
6938 insn_start_off = frag_now_fix ();
6939
29b0f896 6940 /* Output jumps. */
40fb9820 6941 if (i.tm.opcode_modifier.jump)
29b0f896 6942 output_branch ();
40fb9820
L		 6943 else if (i.tm.opcode_modifier.jumpbyte
6944 || i.tm.opcode_modifier.jumpdword)
29b0f896 6945 output_jump ();
40fb9820 6946 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6947 output_interseg_jump ();
6948 else
6949 {
6950 /* Output normal instructions here. */
6951 char *p;
6952 unsigned char *q;
47465058 6953 unsigned int j;
331d2d0d 6954 unsigned int prefix;
4dffcebc 6955
d022bddd
IT		 6956 /* Some processors fail on LOCK prefix. This options makes
6957 assembler ignore LOCK prefix and serves as a workaround. */
6958 if (omit_lock_prefix)
6959 {
6960 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
6961 return;
6962 i.prefix[LOCK_PREFIX] = 0;
6963 }
6964
43234a1e
L		 6965 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6966 don't need the explicit prefix. */
6967 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6968 {
c0f3af97 6969 switch (i.tm.opcode_length)
bc4bd9ab 6970 {
c0f3af97
L		 6971 case 3:
6972 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6973 {
c0f3af97
L		 6974 prefix = (i.tm.base_opcode >> 24) & 0xff;
6975 goto check_prefix;
6976 }
6977 break;
6978 case 2:
6979 if ((i.tm.base_opcode & 0xff0000) != 0)
6980 {
6981 prefix = (i.tm.base_opcode >> 16) & 0xff;
6982 if (i.tm.cpu_flags.bitfield.cpupadlock)
6983 {
4dffcebc 6984check_prefix:
c0f3af97 6985 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6986 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6987 != REPE_PREFIX_OPCODE))
6988 add_prefix (prefix);
6989 }
6990 else
4dffcebc
L		 6991 add_prefix (prefix);
6992 }
c0f3af97
L		 6993 break;
6994 case 1:
6995 break;
6996 default:
6997 abort ();
bc4bd9ab 6998 }
c0f3af97
L		 6999
7000 /* The prefix bytes. */
7001 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7002 if (*q)
7003 FRAG_APPEND_1_CHAR (*q);
0f10071e 7004 }
ae5c1c7b 7005 else
c0f3af97
L		 7006 {
7007 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7008 if (*q)
7009 switch (j)
7010 {
7011 case REX_PREFIX:
7012 /* REX byte is encoded in VEX prefix. */
7013 break;
7014 case SEG_PREFIX:
7015 case ADDR_PREFIX:
7016 FRAG_APPEND_1_CHAR (*q);
7017 break;
7018 default:
7019 /* There should be no other prefixes for instructions
7020 with VEX prefix. */
7021 abort ();
7022 }
7023
43234a1e
L		 7024 /* For EVEX instructions i.vrex should become 0 after
7025 build_evex_prefix. For VEX instructions upper 16 registers
7026 aren't available, so VREX should be 0. */
7027 if (i.vrex)
7028 abort ();
c0f3af97
L		 7029 /* Now the VEX prefix. */
7030 p = frag_more (i.vex.length);
7031 for (j = 0; j < i.vex.length; j++)
7032 p[j] = i.vex.bytes[j];
7033 }
252b5132 7034
29b0f896 7035 /* Now the opcode; be careful about word order here! */
4dffcebc 7036 if (i.tm.opcode_length == 1)
29b0f896
AM		 7037 {
7038 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7039 }
7040 else
7041 {
4dffcebc 7042 switch (i.tm.opcode_length)
331d2d0d 7043 {
43234a1e
L		 7044 case 4:
7045 p = frag_more (4);
7046 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7047 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7048 break;
4dffcebc 7049 case 3:
331d2d0d
L		 7050 p = frag_more (3);
7051 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7052 break;
7053 case 2:
7054 p = frag_more (2);
7055 break;
7056 default:
7057 abort ();
7058 break;
331d2d0d 7059 }
0f10071e 7060
29b0f896
AM		 7061 /* Put out high byte first: can't use md_number_to_chars! */
7062 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7063 *p = i.tm.base_opcode & 0xff;
7064 }
3e73aa7c 7065
29b0f896 7066 /* Now the modrm byte and sib byte (if present). */
40fb9820 7067 if (i.tm.opcode_modifier.modrm)
29b0f896 7068 {
4a3523fa
L		 7069 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7070 | i.rm.reg << 3
7071 | i.rm.mode << 6));
29b0f896
AM		 7072 /* If i.rm.regmem == ESP (4)
7073 && i.rm.mode != (Register mode)
7074 && not 16 bit
7075 ==> need second modrm byte. */
7076 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7077 && i.rm.mode != 3
40fb9820 7078 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7079 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7080 | i.sib.index << 3
7081 | i.sib.scale << 6));
29b0f896 7082 }
3e73aa7c 7083
29b0f896 7084 if (i.disp_operands)
2bbd9c25 7085 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7086
29b0f896 7087 if (i.imm_operands)
2bbd9c25 7088 output_imm (insn_start_frag, insn_start_off);
29b0f896 7089 }
252b5132 7090
29b0f896
AM		 7091#ifdef DEBUG386
7092 if (flag_debug)
7093 {
7b81dfbb 7094 pi ("" /*line*/, &i);
29b0f896
AM		 7095 }
7096#endif /* DEBUG386 */
7097}
252b5132 7098
e205caa7
L		 7099/* Return the size of the displacement operand N. */
7100
7101static int
7102disp_size (unsigned int n)
7103{
7104 int size = 4;
43234a1e
L		 7105
7106 /* Vec_Disp8 has to be 8bit. */
7107 if (i.types[n].bitfield.vec_disp8)
7108 size = 1;
7109 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7110 size = 8;
7111 else if (i.types[n].bitfield.disp8)
7112 size = 1;
7113 else if (i.types[n].bitfield.disp16)
7114 size = 2;
e205caa7
L		 7115 return size;
7116}
7117
7118/* Return the size of the immediate operand N. */
7119
7120static int
7121imm_size (unsigned int n)
7122{
7123 int size = 4;
40fb9820
L		 7124 if (i.types[n].bitfield.imm64)
7125 size = 8;
7126 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7127 size = 1;
7128 else if (i.types[n].bitfield.imm16)
7129 size = 2;
e205caa7
L		 7130 return size;
7131}
7132
29b0f896 7133static void
64e74474 7134output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7135{
7136 char *p;
7137 unsigned int n;
252b5132 7138
29b0f896
AM		 7139 for (n = 0; n < i.operands; n++)
7140 {
43234a1e
L		 7141 if (i.types[n].bitfield.vec_disp8
7142 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7143 {
7144 if (i.op[n].disps->X_op == O_constant)
7145 {
e205caa7 7146 int size = disp_size (n);
43234a1e 7147 offsetT val = i.op[n].disps->X_add_number;
252b5132 7148
43234a1e
L		 7149 if (i.types[n].bitfield.vec_disp8)
7150 val >>= i.memshift;
7151 val = offset_in_range (val, size);
29b0f896
AM		 7152 p = frag_more (size);
7153 md_number_to_chars (p, val, size);
7154 }
7155 else
7156 {
f86103b7 7157 enum bfd_reloc_code_real reloc_type;
e205caa7 7158 int size = disp_size (n);
40fb9820 7159 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 7160 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7161
e205caa7 7162 /* We can't have 8 bit displacement here. */
9c2799c2 7163 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7164
29b0f896
AM		 7165 /* The PC relative address is computed relative
7166 to the instruction boundary, so in case immediate
7167 fields follows, we need to adjust the value. */
7168 if (pcrel && i.imm_operands)
7169 {
29b0f896 7170 unsigned int n1;
e205caa7 7171 int sz = 0;
252b5132 7172
29b0f896 7173 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7174 if (operand_type_check (i.types[n1], imm))
252b5132 7175 {
e205caa7
L		 7176 /* Only one immediate is allowed for PC
7177 relative address. */
9c2799c2 7178 gas_assert (sz == 0);
e205caa7
L		 7179 sz = imm_size (n1);
7180 i.op[n].disps->X_add_number -= sz;
252b5132 7181 }
29b0f896 7182 /* We should find the immediate. */
9c2799c2 7183 gas_assert (sz != 0);
29b0f896 7184 }
520dc8e8 7185
29b0f896 7186 p = frag_more (size);
c3320543
L		 7187 reloc_type = reloc (size, pcrel, sign,
7188 (i.bnd_prefix != NULL
7189 || add_bnd_prefix),
7190 i.reloc[n]);
d6ab8113 7191 if (GOT_symbol
2bbd9c25 7192 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7193 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7194 || reloc_type == BFD_RELOC_X86_64_32S
7195 || (reloc_type == BFD_RELOC_64
7196 && object_64bit))
d6ab8113
JB		 7197 && (i.op[n].disps->X_op == O_symbol
7198 || (i.op[n].disps->X_op == O_add
7199 && ((symbol_get_value_expression
7200 (i.op[n].disps->X_op_symbol)->X_op)
7201 == O_subtract))))
7202 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7203 {
7204 offsetT add;
7205
7206 if (insn_start_frag == frag_now)
7207 add = (p - frag_now->fr_literal) - insn_start_off;
7208 else
7209 {
7210 fragS *fr;
7211
7212 add = insn_start_frag->fr_fix - insn_start_off;
7213 for (fr = insn_start_frag->fr_next;
7214 fr && fr != frag_now; fr = fr->fr_next)
7215 add += fr->fr_fix;
7216 add += p - frag_now->fr_literal;
7217 }
7218
4fa24527 7219 if (!object_64bit)
7b81dfbb
AJ		 7220 {
7221 reloc_type = BFD_RELOC_386_GOTPC;
7222 i.op[n].imms->X_add_number += add;
7223 }
7224 else if (reloc_type == BFD_RELOC_64)
7225 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7226 else
7b81dfbb
AJ		 7227 /* Don't do the adjustment for x86-64, as there
7228 the pcrel addressing is relative to the _next_
7229 insn, and that is taken care of in other code. */
d6ab8113 7230 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7231 }
062cd5e7 7232 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 7233 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 7234 }
7235 }
7236 }
7237}
252b5132 7238
29b0f896 7239static void
64e74474 7240output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7241{
7242 char *p;
7243 unsigned int n;
252b5132 7244
29b0f896
AM		 7245 for (n = 0; n < i.operands; n++)
7246 {
43234a1e
L		 7247 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7248 if (i.rounding && (int) n == i.rounding->operand)
7249 continue;
7250
40fb9820 7251 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7252 {
7253 if (i.op[n].imms->X_op == O_constant)
7254 {
e205caa7 7255 int size = imm_size (n);
29b0f896 7256 offsetT val;
b4cac588 7257
29b0f896
AM		 7258 val = offset_in_range (i.op[n].imms->X_add_number,
7259 size);
7260 p = frag_more (size);
7261 md_number_to_chars (p, val, size);
7262 }
7263 else
7264 {
7265 /* Not absolute_section.
7266 Need a 32-bit fixup (don't support 8bit
7267 non-absolute imms). Try to support other
7268 sizes ... */
f86103b7 7269 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7270 int size = imm_size (n);
7271 int sign;
29b0f896 7272
40fb9820 7273 if (i.types[n].bitfield.imm32s
a7d61044 7274 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7275 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7276 sign = 1;
e205caa7
L		 7277 else
7278 sign = 0;
520dc8e8 7279
29b0f896 7280 p = frag_more (size);
c3320543 7281 reloc_type = reloc (size, 0, sign, 0, i.reloc[n]);
f86103b7 7282
2bbd9c25
JJ		 7283 /* This is tough to explain. We end up with this one if we
7284 * have operands that look like
7285 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7286 * obtain the absolute address of the GOT, and it is strongly
7287 * preferable from a performance point of view to avoid using
7288 * a runtime relocation for this. The actual sequence of
7289 * instructions often look something like:
7290 *
7291 * call .L66
7292 * .L66:
7293 * popl %ebx
7294 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7295 *
7296 * The call and pop essentially return the absolute address
7297 * of the label .L66 and store it in %ebx. The linker itself
7298 * will ultimately change the first operand of the addl so
7299 * that %ebx points to the GOT, but to keep things simple, the
7300 * .o file must have this operand set so that it generates not
7301 * the absolute address of .L66, but the absolute address of
7302 * itself. This allows the linker itself simply treat a GOTPC
7303 * relocation as asking for a pcrel offset to the GOT to be
7304 * added in, and the addend of the relocation is stored in the
7305 * operand field for the instruction itself.
7306 *
7307 * Our job here is to fix the operand so that it would add
7308 * the correct offset so that %ebx would point to itself. The
7309 * thing that is tricky is that .-.L66 will point to the
7310 * beginning of the instruction, so we need to further modify
7311 * the operand so that it will point to itself. There are
7312 * other cases where you have something like:
7313 *
7314 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7315 *
7316 * and here no correction would be required. Internally in
7317 * the assembler we treat operands of this form as not being
7318 * pcrel since the '.' is explicitly mentioned, and I wonder
7319 * whether it would simplify matters to do it this way. Who
7320 * knows. In earlier versions of the PIC patches, the
7321 * pcrel_adjust field was used to store the correction, but
7322 * since the expression is not pcrel, I felt it would be
7323 * confusing to do it this way. */
7324
d6ab8113 7325 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7326 || reloc_type == BFD_RELOC_X86_64_32S
7327 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7328 && GOT_symbol
7329 && GOT_symbol == i.op[n].imms->X_add_symbol
7330 && (i.op[n].imms->X_op == O_symbol
7331 || (i.op[n].imms->X_op == O_add
7332 && ((symbol_get_value_expression
7333 (i.op[n].imms->X_op_symbol)->X_op)
7334 == O_subtract))))
7335 {
2bbd9c25
JJ		 7336 offsetT add;
7337
7338 if (insn_start_frag == frag_now)
7339 add = (p - frag_now->fr_literal) - insn_start_off;
7340 else
7341 {
7342 fragS *fr;
7343
7344 add = insn_start_frag->fr_fix - insn_start_off;
7345 for (fr = insn_start_frag->fr_next;
7346 fr && fr != frag_now; fr = fr->fr_next)
7347 add += fr->fr_fix;
7348 add += p - frag_now->fr_literal;
7349 }
7350
4fa24527 7351 if (!object_64bit)
d6ab8113 7352 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7353 else if (size == 4)
d6ab8113 7354 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7355 else if (size == 8)
7356 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7357 i.op[n].imms->X_add_number += add;
29b0f896 7358 }
29b0f896
AM		 7359 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7360 i.op[n].imms, 0, reloc_type);
7361 }
7362 }
7363 }
252b5132
RH		 7364}
7365\f
d182319b
JB		 7366/* x86_cons_fix_new is called via the expression parsing code when a
7367 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7368static int cons_sign = -1;
7369
7370void
e3bb37b5 7371x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7372 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7373{
62ebcb5c 7374 r = reloc (len, 0, cons_sign, 0, r);
d182319b
JB		 7375
7376#ifdef TE_PE
7377 if (exp->X_op == O_secrel)
7378 {
7379 exp->X_op = O_symbol;
7380 r = BFD_RELOC_32_SECREL;
7381 }
7382#endif
7383
7384 fix_new_exp (frag, off, len, exp, 0, r);
7385}
7386
357d1bd8
L		 7387/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7388 purpose of the `.dc.a' internal pseudo-op. */
7389
7390int
7391x86_address_bytes (void)
7392{
7393 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7394 return 4;
7395 return stdoutput->arch_info->bits_per_address / 8;
7396}
7397
d382c579
TG		 7398#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7399 || defined (LEX_AT)
c06ec724 7400# define lex_got(reloc, adjust, types, bnd_prefix) NULL
718ddfc0 7401#else
f3c180ae
AM		 7402/* Parse operands of the form
7403 <symbol>@GOTOFF+<nnn>
7404 and similar .plt or .got references.
7405
7406 If we find one, set up the correct relocation in RELOC and copy the
7407 input string, minus the `@GOTOFF' into a malloc'd buffer for
7408 parsing by the calling routine. Return this buffer, and if ADJUST
7409 is non-null set it to the length of the string we removed from the
7410 input line. Otherwise return NULL. */
7411static char *
91d6fa6a 7412lex_got (enum bfd_reloc_code_real *rel,
64e74474 7413 int *adjust,
c3320543
L		 7414 i386_operand_type *types,
7415 int bnd_prefix)
f3c180ae 7416{
7b81dfbb
AJ		 7417 /* Some of the relocations depend on the size of what field is to
7418 be relocated. But in our callers i386_immediate and i386_displacement
7419 we don't yet know the operand size (this will be set by insn
7420 matching). Hence we record the word32 relocation here,
7421 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7422 static const struct {
7423 const char *str;
cff8d58a 7424 int len;
4fa24527 7425 const enum bfd_reloc_code_real rel[2];
40fb9820 7426 const i386_operand_type types64;
f3c180ae 7427 } gotrel[] = {
8ce3d284 7428#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7429 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7430 BFD_RELOC_SIZE32 },
7431 OPERAND_TYPE_IMM32_64 },
8ce3d284 7432#endif
cff8d58a
L		 7433 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7434 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7435 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7436 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7437 BFD_RELOC_X86_64_PLT32 },
40fb9820 7438 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7439 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7440 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7441 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7442 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7443 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7444 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7445 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7446 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7447 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7448 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7449 BFD_RELOC_X86_64_TLSGD },
40fb9820 7450 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7451 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7452 _dummy_first_bfd_reloc_code_real },
40fb9820 7453 OPERAND_TYPE_NONE },
cff8d58a
L		 7454 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7455 BFD_RELOC_X86_64_TLSLD },
40fb9820 7456 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7457 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7458 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7459 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7460 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7461 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7462 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7463 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7464 _dummy_first_bfd_reloc_code_real },
40fb9820 7465 OPERAND_TYPE_NONE },
cff8d58a
L		 7466 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7467 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7468 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7469 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7470 _dummy_first_bfd_reloc_code_real },
40fb9820 7471 OPERAND_TYPE_NONE },
cff8d58a
L		 7472 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7473 _dummy_first_bfd_reloc_code_real },
40fb9820 7474 OPERAND_TYPE_NONE },
cff8d58a
L		 7475 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7476 BFD_RELOC_X86_64_GOT32 },
40fb9820 7477 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7478 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7479 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7480 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7481 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7482 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7483 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7484 };
7485 char *cp;
7486 unsigned int j;
7487
d382c579 7488#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7489 if (!IS_ELF)
7490 return NULL;
d382c579 7491#endif
718ddfc0 7492
f3c180ae 7493 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7494 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7495 return NULL;
7496
47465058 7497 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7498 {
cff8d58a 7499 int len = gotrel[j].len;
28f81592 7500 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7501 {
4fa24527 7502 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7503 {
28f81592
AM		 7504 int first, second;
7505 char *tmpbuf, *past_reloc;
f3c180ae 7506
91d6fa6a 7507 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7508
3956db08
JB		 7509 if (types)
7510 {
7511 if (flag_code != CODE_64BIT)
40fb9820
L		 7512 {
7513 types->bitfield.imm32 = 1;
7514 types->bitfield.disp32 = 1;
7515 }
3956db08
JB		 7516 else
7517 *types = gotrel[j].types64;
7518 }
7519
8fd4256d 7520 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7521 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7522
28f81592 7523 /* The length of the first part of our input line. */
f3c180ae 7524 first = cp - input_line_pointer;
28f81592
AM		 7525
7526 /* The second part goes from after the reloc token until
67c11a9b 7527 (and including) an end_of_line char or comma. */
28f81592 7528 past_reloc = cp + 1 + len;
67c11a9b
AM		 7529 cp = past_reloc;
7530 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7531 ++cp;
7532 second = cp + 1 - past_reloc;
28f81592
AM		 7533
7534 /* Allocate and copy string. The trailing NUL shouldn't
7535 be necessary, but be safe. */
1e9cc1c2 7536 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7537 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7538 if (second != 0 && *past_reloc != ' ')
7539 /* Replace the relocation token with ' ', so that
7540 errors like foo@GOTOFF1 will be detected. */
7541 tmpbuf[first++] = ' ';
af89796a
L		 7542 else
7543 /* Increment length by 1 if the relocation token is
7544 removed. */
7545 len++;
7546 if (adjust)
7547 *adjust = len;
0787a12d
AM		 7548 memcpy (tmpbuf + first, past_reloc, second);
7549 tmpbuf[first + second] = '\0';
c3320543
L		 7550 if (bnd_prefix && *rel == BFD_RELOC_X86_64_PLT32)
7551 *rel = BFD_RELOC_X86_64_PLT32_BND;
f3c180ae
AM		 7552 return tmpbuf;
7553 }
7554
4fa24527
JB		 7555 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7556 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7557 return NULL;
7558 }
7559 }
7560
7561 /* Might be a symbol version string. Don't as_bad here. */
7562 return NULL;
7563}
4e4f7c87 7564#endif
f3c180ae 7565
a988325c
NC		 7566#ifdef TE_PE
7567#ifdef lex_got
7568#undef lex_got
7569#endif
7570/* Parse operands of the form
7571 <symbol>@SECREL32+<nnn>
7572
7573 If we find one, set up the correct relocation in RELOC and copy the
7574 input string, minus the `@SECREL32' into a malloc'd buffer for
7575 parsing by the calling routine. Return this buffer, and if ADJUST
7576 is non-null set it to the length of the string we removed from the
34bca508
L		 7577 input line. Otherwise return NULL.
7578
a988325c
NC		 7579 This function is copied from the ELF version above adjusted for PE targets. */
7580
7581static char *
7582lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7583 int *adjust ATTRIBUTE_UNUSED,
c06ec724
L		 7584 i386_operand_type *types,
7585 int bnd_prefix ATTRIBUTE_UNUSED)
a988325c
NC		 7586{
7587 static const struct
7588 {
7589 const char *str;
7590 int len;
7591 const enum bfd_reloc_code_real rel[2];
7592 const i386_operand_type types64;
7593 }
7594 gotrel[] =
7595 {
7596 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7597 BFD_RELOC_32_SECREL },
7598 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7599 };
7600
7601 char *cp;
7602 unsigned j;
7603
7604 for (cp = input_line_pointer; *cp != '@'; cp++)
7605 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7606 return NULL;
7607
7608 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7609 {
7610 int len = gotrel[j].len;
7611
7612 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7613 {
7614 if (gotrel[j].rel[object_64bit] != 0)
7615 {
7616 int first, second;
7617 char *tmpbuf, *past_reloc;
7618
7619 *rel = gotrel[j].rel[object_64bit];
7620 if (adjust)
7621 *adjust = len;
7622
7623 if (types)
7624 {
7625 if (flag_code != CODE_64BIT)
7626 {
7627 types->bitfield.imm32 = 1;
7628 types->bitfield.disp32 = 1;
7629 }
7630 else
7631 *types = gotrel[j].types64;
7632 }
7633
7634 /* The length of the first part of our input line. */
7635 first = cp - input_line_pointer;
7636
7637 /* The second part goes from after the reloc token until
7638 (and including) an end_of_line char or comma. */
7639 past_reloc = cp + 1 + len;
7640 cp = past_reloc;
7641 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7642 ++cp;
7643 second = cp + 1 - past_reloc;
7644
7645 /* Allocate and copy string. The trailing NUL shouldn't
7646 be necessary, but be safe. */
7647 tmpbuf = (char *) xmalloc (first + second + 2);
7648 memcpy (tmpbuf, input_line_pointer, first);
7649 if (second != 0 && *past_reloc != ' ')
7650 /* Replace the relocation token with ' ', so that
7651 errors like foo@SECLREL321 will be detected. */
7652 tmpbuf[first++] = ' ';
7653 memcpy (tmpbuf + first, past_reloc, second);
7654 tmpbuf[first + second] = '\0';
7655 return tmpbuf;
7656 }
7657
7658 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7659 gotrel[j].str, 1 << (5 + object_64bit));
7660 return NULL;
7661 }
7662 }
7663
7664 /* Might be a symbol version string. Don't as_bad here. */
7665 return NULL;
7666}
7667
7668#endif /* TE_PE */
7669
62ebcb5c 7670bfd_reloc_code_real_type
e3bb37b5 7671x86_cons (expressionS *exp, int size)
f3c180ae 7672{
62ebcb5c
AM		 7673 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7674
ee86248c
JB		 7675 intel_syntax = -intel_syntax;
7676
3c7b9c2c 7677 exp->X_md = 0;
4fa24527 7678 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7679 {
7680 /* Handle @GOTOFF and the like in an expression. */
7681 char *save;
7682 char *gotfree_input_line;
4a57f2cf 7683 int adjust = 0;
f3c180ae
AM		 7684
7685 save = input_line_pointer;
c3320543 7686 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL, 0);
f3c180ae
AM		 7687 if (gotfree_input_line)
7688 input_line_pointer = gotfree_input_line;
7689
7690 expression (exp);
7691
7692 if (gotfree_input_line)
7693 {
7694 /* expression () has merrily parsed up to the end of line,
7695 or a comma - in the wrong buffer. Transfer how far
7696 input_line_pointer has moved to the right buffer. */
7697 input_line_pointer = (save
7698 + (input_line_pointer - gotfree_input_line)
7699 + adjust);
7700 free (gotfree_input_line);
3992d3b7
AM		 7701 if (exp->X_op == O_constant
7702 || exp->X_op == O_absent
7703 || exp->X_op == O_illegal
0398aac5 7704 || exp->X_op == O_register
3992d3b7
AM		 7705 || exp->X_op == O_big)
7706 {
7707 char c = *input_line_pointer;
7708 *input_line_pointer = 0;
7709 as_bad (_("missing or invalid expression `%s'"), save);
7710 *input_line_pointer = c;
7711 }
f3c180ae
AM		 7712 }
7713 }
7714 else
7715 expression (exp);
ee86248c
JB		 7716
7717 intel_syntax = -intel_syntax;
7718
7719 if (intel_syntax)
7720 i386_intel_simplify (exp);
62ebcb5c
AM		 7721
7722 return got_reloc;
f3c180ae 7723}
f3c180ae 7724
9f32dd5b
L		 7725static void
7726signed_cons (int size)
6482c264 7727{
d182319b
JB		 7728 if (flag_code == CODE_64BIT)
7729 cons_sign = 1;
7730 cons (size);
7731 cons_sign = -1;
6482c264
NC		 7732}
7733
d182319b 7734#ifdef TE_PE
6482c264 7735static void
7016a5d5 7736pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7737{
7738 expressionS exp;
7739
7740 do
7741 {
7742 expression (&exp);
7743 if (exp.X_op == O_symbol)
7744 exp.X_op = O_secrel;
7745
7746 emit_expr (&exp, 4);
7747 }
7748 while (*input_line_pointer++ == ',');
7749
7750 input_line_pointer--;
7751 demand_empty_rest_of_line ();
7752}
6482c264
NC		 7753#endif
7754
43234a1e
L		 7755/* Handle Vector operations. */
7756
7757static char *
7758check_VecOperations (char *op_string, char *op_end)
7759{
7760 const reg_entry *mask;
7761 const char *saved;
7762 char *end_op;
7763
7764 while (*op_string
7765 && (op_end == NULL || op_string < op_end))
7766 {
7767 saved = op_string;
7768 if (*op_string == '{')
7769 {
7770 op_string++;
7771
7772 /* Check broadcasts. */
7773 if (strncmp (op_string, "1to", 3) == 0)
7774 {
7775 int bcst_type;
7776
7777 if (i.broadcast)
7778 goto duplicated_vec_op;
7779
7780 op_string += 3;
7781 if (*op_string == '8')
7782 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7783 else if (*op_string == '4')
7784 bcst_type = BROADCAST_1TO4;
7785 else if (*op_string == '2')
7786 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7787 else if (*op_string == '1'
7788 && *(op_string+1) == '6')
7789 {
7790 bcst_type = BROADCAST_1TO16;
7791 op_string++;
7792 }
7793 else
7794 {
7795 as_bad (_("Unsupported broadcast: `%s'"), saved);
7796 return NULL;
7797 }
7798 op_string++;
7799
7800 broadcast_op.type = bcst_type;
7801 broadcast_op.operand = this_operand;
7802 i.broadcast = &broadcast_op;
7803 }
7804 /* Check masking operation. */
7805 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7806 {
7807 /* k0 can't be used for write mask. */
7808 if (mask->reg_num == 0)
7809 {
7810 as_bad (_("`%s' can't be used for write mask"),
7811 op_string);
7812 return NULL;
7813 }
7814
7815 if (!i.mask)
7816 {
7817 mask_op.mask = mask;
7818 mask_op.zeroing = 0;
7819 mask_op.operand = this_operand;
7820 i.mask = &mask_op;
7821 }
7822 else
7823 {
7824 if (i.mask->mask)
7825 goto duplicated_vec_op;
7826
7827 i.mask->mask = mask;
7828
7829 /* Only "{z}" is allowed here. No need to check
7830 zeroing mask explicitly. */
7831 if (i.mask->operand != this_operand)
7832 {
7833 as_bad (_("invalid write mask `%s'"), saved);
7834 return NULL;
7835 }
7836 }
7837
7838 op_string = end_op;
7839 }
7840 /* Check zeroing-flag for masking operation. */
7841 else if (*op_string == 'z')
7842 {
7843 if (!i.mask)
7844 {
7845 mask_op.mask = NULL;
7846 mask_op.zeroing = 1;
7847 mask_op.operand = this_operand;
7848 i.mask = &mask_op;
7849 }
7850 else
7851 {
7852 if (i.mask->zeroing)
7853 {
7854 duplicated_vec_op:
7855 as_bad (_("duplicated `%s'"), saved);
7856 return NULL;
7857 }
7858
7859 i.mask->zeroing = 1;
7860
7861 /* Only "{%k}" is allowed here. No need to check mask
7862 register explicitly. */
7863 if (i.mask->operand != this_operand)
7864 {
7865 as_bad (_("invalid zeroing-masking `%s'"),
7866 saved);
7867 return NULL;
7868 }
7869 }
7870
7871 op_string++;
7872 }
7873 else
7874 goto unknown_vec_op;
7875
7876 if (*op_string != '}')
7877 {
7878 as_bad (_("missing `}' in `%s'"), saved);
7879 return NULL;
7880 }
7881 op_string++;
7882 continue;
7883 }
7884 unknown_vec_op:
7885 /* We don't know this one. */
7886 as_bad (_("unknown vector operation: `%s'"), saved);
7887 return NULL;
7888 }
7889
7890 return op_string;
7891}
7892
252b5132 7893static int
70e41ade 7894i386_immediate (char *imm_start)
252b5132
RH		 7895{
7896 char *save_input_line_pointer;
f3c180ae 7897 char *gotfree_input_line;
252b5132 7898 segT exp_seg = 0;
47926f60 7899 expressionS *exp;
40fb9820
L		 7900 i386_operand_type types;
7901
0dfbf9d7 7902 operand_type_set (&types, ~0);
252b5132
RH		 7903
7904 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7905 {
31b2323c
L		 7906 as_bad (_("at most %d immediate operands are allowed"),
7907 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7908 return 0;
7909 }
7910
7911 exp = &im_expressions[i.imm_operands++];
520dc8e8 7912 i.op[this_operand].imms = exp;
252b5132
RH		 7913
7914 if (is_space_char (*imm_start))
7915 ++imm_start;
7916
7917 save_input_line_pointer = input_line_pointer;
7918 input_line_pointer = imm_start;
7919
c3320543
L		 7920 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
7921 (i.bnd_prefix != NULL
7922 || add_bnd_prefix));
f3c180ae
AM		 7923 if (gotfree_input_line)
7924 input_line_pointer = gotfree_input_line;
252b5132
RH		 7925
7926 exp_seg = expression (exp);
7927
83183c0c 7928 SKIP_WHITESPACE ();
43234a1e
L		 7929
7930 /* Handle vector operations. */
7931 if (*input_line_pointer == '{')
7932 {
7933 input_line_pointer = check_VecOperations (input_line_pointer,
7934 NULL);
7935 if (input_line_pointer == NULL)
7936 return 0;
7937 }
7938
252b5132 7939 if (*input_line_pointer)
f3c180ae 7940 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7941
7942 input_line_pointer = save_input_line_pointer;
f3c180ae 7943 if (gotfree_input_line)
ee86248c
JB		 7944 {
7945 free (gotfree_input_line);
7946
7947 if (exp->X_op == O_constant || exp->X_op == O_register)
7948 exp->X_op = O_illegal;
7949 }
7950
7951 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7952}
252b5132 7953
ee86248c
JB		 7954static int
7955i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7956 i386_operand_type types, const char *imm_start)
7957{
7958 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7959 {
313c53d1
L		 7960 if (imm_start)
7961 as_bad (_("missing or invalid immediate expression `%s'"),
7962 imm_start);
3992d3b7 7963 return 0;
252b5132 7964 }
3e73aa7c 7965 else if (exp->X_op == O_constant)
252b5132 7966 {
47926f60 7967 /* Size it properly later. */
40fb9820 7968 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7969 /* If not 64bit, sign extend val. */
7970 if (flag_code != CODE_64BIT
4eed87de
AM		 7971 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7972 exp->X_add_number
7973 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7974 }
4c63da97 7975#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7976 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7977 && exp_seg != absolute_section
47926f60 7978 && exp_seg != text_section
24eab124
AM		 7979 && exp_seg != data_section
7980 && exp_seg != bss_section
7981 && exp_seg != undefined_section
f86103b7 7982 && !bfd_is_com_section (exp_seg))
252b5132 7983 {
d0b47220 7984 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 7985 return 0;
7986 }
7987#endif
a841bdf5 7988 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 7989 {
313c53d1
L		 7990 if (imm_start)
7991 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 7992 return 0;
7993 }
252b5132
RH		 7994 else
7995 {
7996 /* This is an address. The size of the address will be
24eab124 7997 determined later, depending on destination register,
3e73aa7c 7998 suffix, or the default for the section. */
40fb9820
L		 7999 i.types[this_operand].bitfield.imm8 = 1;
8000 i.types[this_operand].bitfield.imm16 = 1;
8001 i.types[this_operand].bitfield.imm32 = 1;
8002 i.types[this_operand].bitfield.imm32s = 1;
8003 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8004 i.types[this_operand] = operand_type_and (i.types[this_operand],
8005 types);
252b5132
RH		 8006 }
8007
8008 return 1;
8009}
8010
551c1ca1 8011static char *
e3bb37b5 8012i386_scale (char *scale)
252b5132 8013{
551c1ca1
AM		 8014 offsetT val;
8015 char *save = input_line_pointer;
252b5132 8016
551c1ca1
AM		 8017 input_line_pointer = scale;
8018 val = get_absolute_expression ();
8019
8020 switch (val)
252b5132 8021 {
551c1ca1 8022 case 1:
252b5132
RH		 8023 i.log2_scale_factor = 0;
8024 break;
551c1ca1 8025 case 2:
252b5132
RH		 8026 i.log2_scale_factor = 1;
8027 break;
551c1ca1 8028 case 4:
252b5132
RH		 8029 i.log2_scale_factor = 2;
8030 break;
551c1ca1 8031 case 8:
252b5132
RH		 8032 i.log2_scale_factor = 3;
8033 break;
8034 default:
a724f0f4
JB		 8035 {
8036 char sep = *input_line_pointer;
8037
8038 *input_line_pointer = '\0';
8039 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8040 scale);
8041 *input_line_pointer = sep;
8042 input_line_pointer = save;
8043 return NULL;
8044 }
252b5132 8045 }
29b0f896 8046 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8047 {
8048 as_warn (_("scale factor of %d without an index register"),
24eab124 8049 1 << i.log2_scale_factor);
252b5132 8050 i.log2_scale_factor = 0;
252b5132 8051 }
551c1ca1
AM		 8052 scale = input_line_pointer;
8053 input_line_pointer = save;
8054 return scale;
252b5132
RH		 8055}
8056
252b5132 8057static int
e3bb37b5 8058i386_displacement (char *disp_start, char *disp_end)
252b5132 8059{
29b0f896 8060 expressionS *exp;
252b5132
RH		 8061 segT exp_seg = 0;
8062 char *save_input_line_pointer;
f3c180ae 8063 char *gotfree_input_line;
40fb9820
L		 8064 int override;
8065 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8066 int ret;
252b5132 8067
31b2323c
L		 8068 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8069 {
8070 as_bad (_("at most %d displacement operands are allowed"),
8071 MAX_MEMORY_OPERANDS);
8072 return 0;
8073 }
8074
0dfbf9d7 8075 operand_type_set (&bigdisp, 0);
40fb9820
L		 8076 if ((i.types[this_operand].bitfield.jumpabsolute)
8077 || (!current_templates->start->opcode_modifier.jump
8078 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8079 {
40fb9820 8080 bigdisp.bitfield.disp32 = 1;
e05278af 8081 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8082 if (flag_code == CODE_64BIT)
8083 {
8084 if (!override)
8085 {
8086 bigdisp.bitfield.disp32s = 1;
8087 bigdisp.bitfield.disp64 = 1;
8088 }
8089 }
8090 else if ((flag_code == CODE_16BIT) ^ override)
8091 {
8092 bigdisp.bitfield.disp32 = 0;
8093 bigdisp.bitfield.disp16 = 1;
8094 }
e05278af
JB		 8095 }
8096 else
8097 {
8098 /* For PC-relative branches, the width of the displacement
8099 is dependent upon data size, not address size. */
e05278af 8100 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8101 if (flag_code == CODE_64BIT)
8102 {
8103 if (override || i.suffix == WORD_MNEM_SUFFIX)
8104 bigdisp.bitfield.disp16 = 1;
8105 else
8106 {
8107 bigdisp.bitfield.disp32 = 1;
8108 bigdisp.bitfield.disp32s = 1;
8109 }
8110 }
8111 else
e05278af
JB		 8112 {
8113 if (!override)
8114 override = (i.suffix == (flag_code != CODE_16BIT
8115 ? WORD_MNEM_SUFFIX
8116 : LONG_MNEM_SUFFIX));
40fb9820
L		 8117 bigdisp.bitfield.disp32 = 1;
8118 if ((flag_code == CODE_16BIT) ^ override)
8119 {
8120 bigdisp.bitfield.disp32 = 0;
8121 bigdisp.bitfield.disp16 = 1;
8122 }
e05278af 8123 }
e05278af 8124 }
c6fb90c8
L		 8125 i.types[this_operand] = operand_type_or (i.types[this_operand],
8126 bigdisp);
252b5132
RH		 8127
8128 exp = &disp_expressions[i.disp_operands];
520dc8e8 8129 i.op[this_operand].disps = exp;
252b5132
RH		 8130 i.disp_operands++;
8131 save_input_line_pointer = input_line_pointer;
8132 input_line_pointer = disp_start;
8133 END_STRING_AND_SAVE (disp_end);
8134
8135#ifndef GCC_ASM_O_HACK
8136#define GCC_ASM_O_HACK 0
8137#endif
8138#if GCC_ASM_O_HACK
8139 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8140 if (i.types[this_operand].bitfield.baseIndex
24eab124 8141 && displacement_string_end[-1] == '+')
252b5132
RH		 8142 {
8143 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8144 constraint within gcc asm statements.
8145 For instance:
8146
8147 #define _set_tssldt_desc(n,addr,limit,type) \
8148 __asm__ __volatile__ ( \
8149 "movw %w2,%0\n\t" \
8150 "movw %w1,2+%0\n\t" \
8151 "rorl $16,%1\n\t" \
8152 "movb %b1,4+%0\n\t" \
8153 "movb %4,5+%0\n\t" \
8154 "movb $0,6+%0\n\t" \
8155 "movb %h1,7+%0\n\t" \
8156 "rorl $16,%1" \
8157 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8158
8159 This works great except that the output assembler ends
8160 up looking a bit weird if it turns out that there is
8161 no offset. You end up producing code that looks like:
8162
8163 #APP
8164 movw $235,(%eax)
8165 movw %dx,2+(%eax)
8166 rorl $16,%edx
8167 movb %dl,4+(%eax)
8168 movb $137,5+(%eax)
8169 movb $0,6+(%eax)
8170 movb %dh,7+(%eax)
8171 rorl $16,%edx
8172 #NO_APP
8173
47926f60 8174 So here we provide the missing zero. */
24eab124
AM		 8175
8176 *displacement_string_end = '0';
252b5132
RH		 8177 }
8178#endif
c3320543
L		 8179 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
8180 (i.bnd_prefix != NULL
8181 || add_bnd_prefix));
f3c180ae
AM		 8182 if (gotfree_input_line)
8183 input_line_pointer = gotfree_input_line;
252b5132 8184
24eab124 8185 exp_seg = expression (exp);
252b5132 8186
636c26b0
AM		 8187 SKIP_WHITESPACE ();
8188 if (*input_line_pointer)
8189 as_bad (_("junk `%s' after expression"), input_line_pointer);
8190#if GCC_ASM_O_HACK
8191 RESTORE_END_STRING (disp_end + 1);
8192#endif
636c26b0 8193 input_line_pointer = save_input_line_pointer;
636c26b0 8194 if (gotfree_input_line)
ee86248c
JB		 8195 {
8196 free (gotfree_input_line);
8197
8198 if (exp->X_op == O_constant || exp->X_op == O_register)
8199 exp->X_op = O_illegal;
8200 }
8201
8202 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8203
8204 RESTORE_END_STRING (disp_end);
8205
8206 return ret;
8207}
8208
8209static int
8210i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8211 i386_operand_type types, const char *disp_start)
8212{
8213 i386_operand_type bigdisp;
8214 int ret = 1;
636c26b0 8215
24eab124
AM		 8216 /* We do this to make sure that the section symbol is in
8217 the symbol table. We will ultimately change the relocation
47926f60 8218 to be relative to the beginning of the section. */
1ae12ab7 8219 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8220 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8221 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8222 {
636c26b0 8223 if (exp->X_op != O_symbol)
3992d3b7 8224 goto inv_disp;
636c26b0 8225
e5cb08ac 8226 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8227 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8228 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8229 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8230 exp->X_op = O_subtract;
8231 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8232 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8233 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8234 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8235 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8236 else
29b0f896 8237 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8238 }
252b5132 8239
3992d3b7
AM		 8240 else if (exp->X_op == O_absent
8241 || exp->X_op == O_illegal
ee86248c 8242 || exp->X_op == O_big)
2daf4fd8 8243 {
3992d3b7
AM		 8244 inv_disp:
8245 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8246 disp_start);
3992d3b7 8247 ret = 0;
2daf4fd8
AM		 8248 }
8249
0e1147d9
L		 8250 else if (flag_code == CODE_64BIT
8251 && !i.prefix[ADDR_PREFIX]
8252 && exp->X_op == O_constant)
8253 {
8254 /* Since displacement is signed extended to 64bit, don't allow
8255 disp32 and turn off disp32s if they are out of range. */
8256 i.types[this_operand].bitfield.disp32 = 0;
8257 if (!fits_in_signed_long (exp->X_add_number))
8258 {
8259 i.types[this_operand].bitfield.disp32s = 0;
8260 if (i.types[this_operand].bitfield.baseindex)
8261 {
8262 as_bad (_("0x%lx out range of signed 32bit displacement"),
8263 (long) exp->X_add_number);
8264 ret = 0;
8265 }
8266 }
8267 }
8268
4c63da97 8269#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8270 else if (exp->X_op != O_constant
8271 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8272 && exp_seg != absolute_section
8273 && exp_seg != text_section
8274 && exp_seg != data_section
8275 && exp_seg != bss_section
8276 && exp_seg != undefined_section
8277 && !bfd_is_com_section (exp_seg))
24eab124 8278 {
d0b47220 8279 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8280 ret = 0;
24eab124 8281 }
252b5132 8282#endif
3956db08 8283
40fb9820
L		 8284 /* Check if this is a displacement only operand. */
8285 bigdisp = i.types[this_operand];
8286 bigdisp.bitfield.disp8 = 0;
8287 bigdisp.bitfield.disp16 = 0;
8288 bigdisp.bitfield.disp32 = 0;
8289 bigdisp.bitfield.disp32s = 0;
8290 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8291 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8292 i.types[this_operand] = operand_type_and (i.types[this_operand],
8293 types);
3956db08 8294
3992d3b7 8295 return ret;
252b5132
RH		 8296}
8297
eecb386c 8298/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8299 Return 1 on success, 0 on a failure. */
8300
252b5132 8301static int
e3bb37b5 8302i386_index_check (const char *operand_string)
252b5132 8303{
fc0763e6 8304 const char *kind = "base/index";
be05d201
L		 8305 enum flag_code addr_mode;
8306
8307 if (i.prefix[ADDR_PREFIX])
8308 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8309 else
8310 {
8311 addr_mode = flag_code;
8312
24eab124 8313#if INFER_ADDR_PREFIX
be05d201
L		 8314 if (i.mem_operands == 0)
8315 {
8316 /* Infer address prefix from the first memory operand. */
8317 const reg_entry *addr_reg = i.base_reg;
8318
8319 if (addr_reg == NULL)
8320 addr_reg = i.index_reg;
eecb386c 8321
be05d201
L		 8322 if (addr_reg)
8323 {
8324 if (addr_reg->reg_num == RegEip
8325 || addr_reg->reg_num == RegEiz
8326 || addr_reg->reg_type.bitfield.reg32)
8327 addr_mode = CODE_32BIT;
8328 else if (flag_code != CODE_64BIT
8329 && addr_reg->reg_type.bitfield.reg16)
8330 addr_mode = CODE_16BIT;
8331
8332 if (addr_mode != flag_code)
8333 {
8334 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8335 i.prefixes += 1;
8336 /* Change the size of any displacement too. At most one
8337 of Disp16 or Disp32 is set.
8338 FIXME. There doesn't seem to be any real need for
8339 separate Disp16 and Disp32 flags. The same goes for
8340 Imm16 and Imm32. Removing them would probably clean
8341 up the code quite a lot. */
8342 if (flag_code != CODE_64BIT
8343 && (i.types[this_operand].bitfield.disp16
8344 || i.types[this_operand].bitfield.disp32))
8345 i.types[this_operand]
8346 = operand_type_xor (i.types[this_operand], disp16_32);
8347 }
8348 }
8349 }
24eab124 8350#endif
be05d201
L		 8351 }
8352
fc0763e6
JB		 8353 if (current_templates->start->opcode_modifier.isstring
8354 && !current_templates->start->opcode_modifier.immext
8355 && (current_templates->end[-1].opcode_modifier.isstring
8356 || i.mem_operands))
8357 {
8358 /* Memory operands of string insns are special in that they only allow
8359 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8360 const reg_entry *expected_reg;
8361 static const char *di_si[][2] =
8362 {
8363 { "esi", "edi" },
8364 { "si", "di" },
8365 { "rsi", "rdi" }
8366 };
8367 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8368
8369 kind = "string address";
8370
8371 if (current_templates->start->opcode_modifier.w)
8372 {
8373 i386_operand_type type = current_templates->end[-1].operand_types[0];
8374
8375 if (!type.bitfield.baseindex
8376 || ((!i.mem_operands != !intel_syntax)
8377 && current_templates->end[-1].operand_types[1]
8378 .bitfield.baseindex))
8379 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8380 expected_reg = hash_find (reg_hash,
8381 di_si[addr_mode][type.bitfield.esseg]);
8382
fc0763e6
JB		 8383 }
8384 else
be05d201 8385 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8386
be05d201
L		 8387 if (i.base_reg != expected_reg
8388 || i.index_reg
fc0763e6 8389 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8390 {
be05d201
L		 8391 /* The second memory operand must have the same size as
8392 the first one. */
8393 if (i.mem_operands
8394 && i.base_reg
8395 && !((addr_mode == CODE_64BIT
8396 && i.base_reg->reg_type.bitfield.reg64)
8397 || (addr_mode == CODE_32BIT
8398 ? i.base_reg->reg_type.bitfield.reg32
8399 : i.base_reg->reg_type.bitfield.reg16)))
8400 goto bad_address;
8401
fc0763e6
JB		 8402 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8403 operand_string,
8404 intel_syntax ? '[' : '(',
8405 register_prefix,
be05d201 8406 expected_reg->reg_name,
fc0763e6 8407 intel_syntax ? ']' : ')');
be05d201 8408 return 1;
fc0763e6 8409 }
be05d201
L		 8410 else
8411 return 1;
8412
8413bad_address:
8414 as_bad (_("`%s' is not a valid %s expression"),
8415 operand_string, kind);
8416 return 0;
3e73aa7c
JH		 8417 }
8418 else
8419 {
be05d201
L		 8420 if (addr_mode != CODE_16BIT)
8421 {
8422 /* 32-bit/64-bit checks. */
8423 if ((i.base_reg
8424 && (addr_mode == CODE_64BIT
8425 ? !i.base_reg->reg_type.bitfield.reg64
8426 : !i.base_reg->reg_type.bitfield.reg32)
8427 && (i.index_reg
8428 || (i.base_reg->reg_num
8429 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8430 || (i.index_reg
8431 && !i.index_reg->reg_type.bitfield.regxmm
8432 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8433 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8434 && ((addr_mode == CODE_64BIT
8435 ? !(i.index_reg->reg_type.bitfield.reg64
8436 || i.index_reg->reg_num == RegRiz)
8437 : !(i.index_reg->reg_type.bitfield.reg32
8438 || i.index_reg->reg_num == RegEiz))
8439 || !i.index_reg->reg_type.bitfield.baseindex)))
8440 goto bad_address;
8441 }
8442 else
3e73aa7c 8443 {
be05d201 8444 /* 16-bit checks. */
3e73aa7c 8445 if ((i.base_reg
40fb9820
L		 8446 && (!i.base_reg->reg_type.bitfield.reg16
8447 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8448 || (i.index_reg
40fb9820
L		 8449 && (!i.index_reg->reg_type.bitfield.reg16
8450 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8451 || !(i.base_reg
8452 && i.base_reg->reg_num < 6
8453 && i.index_reg->reg_num >= 6
8454 && i.log2_scale_factor == 0))))
be05d201 8455 goto bad_address;
3e73aa7c
JH		 8456 }
8457 }
be05d201 8458 return 1;
24eab124 8459}
252b5132 8460
43234a1e
L		 8461/* Handle vector immediates. */
8462
8463static int
8464RC_SAE_immediate (const char *imm_start)
8465{
8466 unsigned int match_found, j;
8467 const char *pstr = imm_start;
8468 expressionS *exp;
8469
8470 if (*pstr != '{')
8471 return 0;
8472
8473 pstr++;
8474 match_found = 0;
8475 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8476 {
8477 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8478 {
8479 if (!i.rounding)
8480 {
8481 rc_op.type = RC_NamesTable[j].type;
8482 rc_op.operand = this_operand;
8483 i.rounding = &rc_op;
8484 }
8485 else
8486 {
8487 as_bad (_("duplicated `%s'"), imm_start);
8488 return 0;
8489 }
8490 pstr += RC_NamesTable[j].len;
8491 match_found = 1;
8492 break;
8493 }
8494 }
8495 if (!match_found)
8496 return 0;
8497
8498 if (*pstr++ != '}')
8499 {
8500 as_bad (_("Missing '}': '%s'"), imm_start);
8501 return 0;
8502 }
8503 /* RC/SAE immediate string should contain nothing more. */;
8504 if (*pstr != 0)
8505 {
8506 as_bad (_("Junk after '}': '%s'"), imm_start);
8507 return 0;
8508 }
8509
8510 exp = &im_expressions[i.imm_operands++];
8511 i.op[this_operand].imms = exp;
8512
8513 exp->X_op = O_constant;
8514 exp->X_add_number = 0;
8515 exp->X_add_symbol = (symbolS *) 0;
8516 exp->X_op_symbol = (symbolS *) 0;
8517
8518 i.types[this_operand].bitfield.imm8 = 1;
8519 return 1;
8520}
8521
fc0763e6 8522/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8523 on error. */
252b5132 8524
252b5132 8525static int
a7619375 8526i386_att_operand (char *operand_string)
252b5132 8527{
af6bdddf
AM		 8528 const reg_entry *r;
8529 char *end_op;
24eab124 8530 char *op_string = operand_string;
252b5132 8531
24eab124 8532 if (is_space_char (*op_string))
252b5132
RH		 8533 ++op_string;
8534
24eab124 8535 /* We check for an absolute prefix (differentiating,
47926f60 8536 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8537 if (*op_string == ABSOLUTE_PREFIX)
8538 {
8539 ++op_string;
8540 if (is_space_char (*op_string))
8541 ++op_string;
40fb9820 8542 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8543 }
252b5132 8544
47926f60 8545 /* Check if operand is a register. */
4d1bb795 8546 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8547 {
40fb9820
L		 8548 i386_operand_type temp;
8549
24eab124
AM		 8550 /* Check for a segment override by searching for ':' after a
8551 segment register. */
8552 op_string = end_op;
8553 if (is_space_char (*op_string))
8554 ++op_string;
40fb9820
L		 8555 if (*op_string == ':'
8556 && (r->reg_type.bitfield.sreg2
8557 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8558 {
8559 switch (r->reg_num)
8560 {
8561 case 0:
8562 i.seg[i.mem_operands] = &es;
8563 break;
8564 case 1:
8565 i.seg[i.mem_operands] = &cs;
8566 break;
8567 case 2:
8568 i.seg[i.mem_operands] = &ss;
8569 break;
8570 case 3:
8571 i.seg[i.mem_operands] = &ds;
8572 break;
8573 case 4:
8574 i.seg[i.mem_operands] = &fs;
8575 break;
8576 case 5:
8577 i.seg[i.mem_operands] = &gs;
8578 break;
8579 }
252b5132 8580
24eab124 8581 /* Skip the ':' and whitespace. */
252b5132
RH		 8582 ++op_string;
8583 if (is_space_char (*op_string))
24eab124 8584 ++op_string;
252b5132 8585
24eab124
AM		 8586 if (!is_digit_char (*op_string)
8587 && !is_identifier_char (*op_string)
8588 && *op_string != '('
8589 && *op_string != ABSOLUTE_PREFIX)
8590 {
8591 as_bad (_("bad memory operand `%s'"), op_string);
8592 return 0;
8593 }
47926f60 8594 /* Handle case of %es:*foo. */
24eab124
AM		 8595 if (*op_string == ABSOLUTE_PREFIX)
8596 {
8597 ++op_string;
8598 if (is_space_char (*op_string))
8599 ++op_string;
40fb9820 8600 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8601 }
8602 goto do_memory_reference;
8603 }
43234a1e
L		 8604
8605 /* Handle vector operations. */
8606 if (*op_string == '{')
8607 {
8608 op_string = check_VecOperations (op_string, NULL);
8609 if (op_string == NULL)
8610 return 0;
8611 }
8612
24eab124
AM		 8613 if (*op_string)
8614 {
d0b47220 8615 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8616 return 0;
8617 }
40fb9820
L		 8618 temp = r->reg_type;
8619 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8620 i.types[this_operand] = operand_type_or (i.types[this_operand],
8621 temp);
7d5e4556 8622 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8623 i.op[this_operand].regs = r;
24eab124
AM		 8624 i.reg_operands++;
8625 }
af6bdddf
AM		 8626 else if (*op_string == REGISTER_PREFIX)
8627 {
8628 as_bad (_("bad register name `%s'"), op_string);
8629 return 0;
8630 }
24eab124 8631 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8632 {
24eab124 8633 ++op_string;
40fb9820 8634 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8635 {
d0b47220 8636 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8637 return 0;
8638 }
8639 if (!i386_immediate (op_string))
8640 return 0;
8641 }
43234a1e
L		 8642 else if (RC_SAE_immediate (operand_string))
8643 {
8644 /* If it is a RC or SAE immediate, do nothing. */
8645 ;
8646 }
24eab124
AM		 8647 else if (is_digit_char (*op_string)
8648 || is_identifier_char (*op_string)
e5cb08ac 8649 || *op_string == '(')
24eab124 8650 {
47926f60 8651 /* This is a memory reference of some sort. */
af6bdddf 8652 char *base_string;
252b5132 8653
47926f60 8654 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8655 char *displacement_string_start;
8656 char *displacement_string_end;
43234a1e 8657 char *vop_start;
252b5132 8658
24eab124 8659 do_memory_reference:
24eab124 8660 if ((i.mem_operands == 1
40fb9820 8661 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8662 || i.mem_operands == 2)
8663 {
8664 as_bad (_("too many memory references for `%s'"),
8665 current_templates->start->name);
8666 return 0;
8667 }
252b5132 8668
24eab124
AM		 8669 /* Check for base index form. We detect the base index form by
8670 looking for an ')' at the end of the operand, searching
8671 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8672 after the '('. */
af6bdddf 8673 base_string = op_string + strlen (op_string);
c3332e24 8674
43234a1e
L		 8675 /* Handle vector operations. */
8676 vop_start = strchr (op_string, '{');
8677 if (vop_start && vop_start < base_string)
8678 {
8679 if (check_VecOperations (vop_start, base_string) == NULL)
8680 return 0;
8681 base_string = vop_start;
8682 }
8683
af6bdddf
AM		 8684 --base_string;
8685 if (is_space_char (*base_string))
8686 --base_string;
252b5132 8687
47926f60 8688 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8689 displacement_string_start = op_string;
8690 displacement_string_end = base_string + 1;
252b5132 8691
24eab124
AM		 8692 if (*base_string == ')')
8693 {
af6bdddf 8694 char *temp_string;
24eab124
AM		 8695 unsigned int parens_balanced = 1;
8696 /* We've already checked that the number of left & right ()'s are
47926f60 8697 equal, so this loop will not be infinite. */
24eab124
AM		 8698 do
8699 {
8700 base_string--;
8701 if (*base_string == ')')
8702 parens_balanced++;
8703 if (*base_string == '(')
8704 parens_balanced--;
8705 }
8706 while (parens_balanced);
c3332e24 8707
af6bdddf 8708 temp_string = base_string;
c3332e24 8709
24eab124 8710 /* Skip past '(' and whitespace. */
252b5132
RH		 8711 ++base_string;
8712 if (is_space_char (*base_string))
24eab124 8713 ++base_string;
252b5132 8714
af6bdddf 8715 if (*base_string == ','
4eed87de
AM		 8716 || ((i.base_reg = parse_register (base_string, &end_op))
8717 != NULL))
252b5132 8718 {
af6bdddf 8719 displacement_string_end = temp_string;
252b5132 8720
40fb9820 8721 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8722
af6bdddf 8723 if (i.base_reg)
24eab124 8724 {
24eab124
AM		 8725 base_string = end_op;
8726 if (is_space_char (*base_string))
8727 ++base_string;
af6bdddf
AM		 8728 }
8729
8730 /* There may be an index reg or scale factor here. */
8731 if (*base_string == ',')
8732 {
8733 ++base_string;
8734 if (is_space_char (*base_string))
8735 ++base_string;
8736
4eed87de
AM		 8737 if ((i.index_reg = parse_register (base_string, &end_op))
8738 != NULL)
24eab124 8739 {
af6bdddf 8740 base_string = end_op;
24eab124
AM		 8741 if (is_space_char (*base_string))
8742 ++base_string;
af6bdddf
AM		 8743 if (*base_string == ',')
8744 {
8745 ++base_string;
8746 if (is_space_char (*base_string))
8747 ++base_string;
8748 }
e5cb08ac 8749 else if (*base_string != ')')
af6bdddf 8750 {
4eed87de
AM		 8751 as_bad (_("expecting `,' or `)' "
8752 "after index register in `%s'"),
af6bdddf
AM		 8753 operand_string);
8754 return 0;
8755 }
24eab124 8756 }
af6bdddf 8757 else if (*base_string == REGISTER_PREFIX)
24eab124 8758 {
f76bf5e0
L		 8759 end_op = strchr (base_string, ',');
8760 if (end_op)
8761 *end_op = '\0';
af6bdddf 8762 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8763 return 0;
8764 }
252b5132 8765
47926f60 8766 /* Check for scale factor. */
551c1ca1 8767 if (*base_string != ')')
af6bdddf 8768 {
551c1ca1
AM		 8769 char *end_scale = i386_scale (base_string);
8770
8771 if (!end_scale)
af6bdddf 8772 return 0;
24eab124 8773
551c1ca1 8774 base_string = end_scale;
af6bdddf
AM		 8775 if (is_space_char (*base_string))
8776 ++base_string;
8777 if (*base_string != ')')
8778 {
4eed87de
AM		 8779 as_bad (_("expecting `)' "
8780 "after scale factor in `%s'"),
af6bdddf
AM		 8781 operand_string);
8782 return 0;
8783 }
8784 }
8785 else if (!i.index_reg)
24eab124 8786 {
4eed87de
AM		 8787 as_bad (_("expecting index register or scale factor "
8788 "after `,'; got '%c'"),
af6bdddf 8789 *base_string);
24eab124
AM		 8790 return 0;
8791 }
8792 }
af6bdddf 8793 else if (*base_string != ')')
24eab124 8794 {
4eed87de
AM		 8795 as_bad (_("expecting `,' or `)' "
8796 "after base register in `%s'"),
af6bdddf 8797 operand_string);
24eab124
AM		 8798 return 0;
8799 }
c3332e24 8800 }
af6bdddf 8801 else if (*base_string == REGISTER_PREFIX)
c3332e24 8802 {
f76bf5e0
L		 8803 end_op = strchr (base_string, ',');
8804 if (end_op)
8805 *end_op = '\0';
af6bdddf 8806 as_bad (_("bad register name `%s'"), base_string);
24eab124 8807 return 0;
c3332e24 8808 }
24eab124
AM		 8809 }
8810
8811 /* If there's an expression beginning the operand, parse it,
8812 assuming displacement_string_start and
8813 displacement_string_end are meaningful. */
8814 if (displacement_string_start != displacement_string_end)
8815 {
8816 if (!i386_displacement (displacement_string_start,
8817 displacement_string_end))
8818 return 0;
8819 }
8820
8821 /* Special case for (%dx) while doing input/output op. */
8822 if (i.base_reg
0dfbf9d7
L		 8823 && operand_type_equal (&i.base_reg->reg_type,
8824 &reg16_inoutportreg)
24eab124
AM		 8825 && i.index_reg == 0
8826 && i.log2_scale_factor == 0
8827 && i.seg[i.mem_operands] == 0
40fb9820 8828 && !operand_type_check (i.types[this_operand], disp))
24eab124 8829 {
65da13b5 8830 i.types[this_operand] = inoutportreg;
24eab124
AM		 8831 return 1;
8832 }
8833
eecb386c
AM		 8834 if (i386_index_check (operand_string) == 0)
8835 return 0;
5c07affc 8836 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8837 i.mem_operands++;
8838 }
8839 else
ce8a8b2f
AM		 8840 {
8841 /* It's not a memory operand; argh! */
24eab124
AM		 8842 as_bad (_("invalid char %s beginning operand %d `%s'"),
8843 output_invalid (*op_string),
8844 this_operand + 1,
8845 op_string);
8846 return 0;
8847 }
47926f60 8848 return 1; /* Normal return. */
252b5132
RH		 8849}
8850\f
fa94de6b
RM		 8851/* Calculate the maximum variable size (i.e., excluding fr_fix)
8852 that an rs_machine_dependent frag may reach. */
8853
8854unsigned int
8855i386_frag_max_var (fragS *frag)
8856{
8857 /* The only relaxable frags are for jumps.
8858 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8859 gas_assert (frag->fr_type == rs_machine_dependent);
8860 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8861}
8862
ee7fcc42
AM		 8863/* md_estimate_size_before_relax()
8864
8865 Called just before relax() for rs_machine_dependent frags. The x86
8866 assembler uses these frags to handle variable size jump
8867 instructions.
8868
8869 Any symbol that is now undefined will not become defined.
8870 Return the correct fr_subtype in the frag.
8871 Return the initial "guess for variable size of frag" to caller.
8872 The guess is actually the growth beyond the fixed part. Whatever
8873 we do to grow the fixed or variable part contributes to our
8874 returned value. */
8875
252b5132 8876int
7016a5d5 8877md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8878{
252b5132 8879 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8880 check for un-relaxable symbols. On an ELF system, we can't relax
8881 an externally visible symbol, because it may be overridden by a
8882 shared library. */
8883 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8884#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8885 || (IS_ELF
31312f95 8886 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 8887 || S_IS_WEAK (fragP->fr_symbol)
8888 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
8889 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 8890#endif
8891#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8892 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8893 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8894#endif
8895 )
252b5132 8896 {
b98ef147
AM		 8897 /* Symbol is undefined in this segment, or we need to keep a
8898 reloc so that weak symbols can be overridden. */
8899 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8900 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8901 unsigned char *opcode;
8902 int old_fr_fix;
f6af82bd 8903
ee7fcc42 8904 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8905 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8906 else if (size == 2)
f6af82bd
AM		 8907 reloc_type = BFD_RELOC_16_PCREL;
8908 else
8909 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8910
ee7fcc42
AM		 8911 old_fr_fix = fragP->fr_fix;
8912 opcode = (unsigned char *) fragP->fr_opcode;
8913
fddf5b5b 8914 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8915 {
fddf5b5b
AM		 8916 case UNCOND_JUMP:
8917 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8918 opcode[0] = 0xe9;
252b5132 8919 fragP->fr_fix += size;
062cd5e7
AS		 8920 fix_new (fragP, old_fr_fix, size,
8921 fragP->fr_symbol,
8922 fragP->fr_offset, 1,
8923 reloc_type);
252b5132
RH		 8924 break;
8925
fddf5b5b 8926 case COND_JUMP86:
412167cb
AM		 8927 if (size == 2
8928 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8929 {
8930 /* Negate the condition, and branch past an
8931 unconditional jump. */
8932 opcode[0] ^= 1;
8933 opcode[1] = 3;
8934 /* Insert an unconditional jump. */
8935 opcode[2] = 0xe9;
8936 /* We added two extra opcode bytes, and have a two byte
8937 offset. */
8938 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8939 fix_new (fragP, old_fr_fix + 2, 2,
8940 fragP->fr_symbol,
8941 fragP->fr_offset, 1,
8942 reloc_type);
fddf5b5b
AM		 8943 break;
8944 }
8945 /* Fall through. */
8946
8947 case COND_JUMP:
412167cb
AM		 8948 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8949 {
3e02c1cc
AM		 8950 fixS *fixP;
8951
412167cb 8952 fragP->fr_fix += 1;
3e02c1cc
AM		 8953 fixP = fix_new (fragP, old_fr_fix, 1,
8954 fragP->fr_symbol,
8955 fragP->fr_offset, 1,
8956 BFD_RELOC_8_PCREL);
8957 fixP->fx_signed = 1;
412167cb
AM		 8958 break;
8959 }
93c2a809 8960
24eab124 8961 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8962 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8963 opcode[1] = opcode[0] + 0x10;
f6af82bd 8964 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8965 /* We've added an opcode byte. */
8966 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8967 fix_new (fragP, old_fr_fix + 1, size,
8968 fragP->fr_symbol,
8969 fragP->fr_offset, 1,
8970 reloc_type);
252b5132 8971 break;
fddf5b5b
AM		 8972
8973 default:
8974 BAD_CASE (fragP->fr_subtype);
8975 break;
252b5132
RH		 8976 }
8977 frag_wane (fragP);
ee7fcc42 8978 return fragP->fr_fix - old_fr_fix;
252b5132 8979 }
93c2a809 8980
93c2a809
AM		 8981 /* Guess size depending on current relax state. Initially the relax
8982 state will correspond to a short jump and we return 1, because
8983 the variable part of the frag (the branch offset) is one byte
8984 long. However, we can relax a section more than once and in that
8985 case we must either set fr_subtype back to the unrelaxed state,
8986 or return the value for the appropriate branch. */
8987 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 8988}
8989
47926f60
KH		 8990/* Called after relax() is finished.
8991
8992 In: Address of frag.
8993 fr_type == rs_machine_dependent.
8994 fr_subtype is what the address relaxed to.
8995
8996 Out: Any fixSs and constants are set up.
8997 Caller will turn frag into a ".space 0". */
8998
252b5132 8999void
7016a5d5
TG		 9000md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9001 fragS *fragP)
252b5132 9002{
29b0f896 9003 unsigned char *opcode;
252b5132 9004 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9005 offsetT target_address;
9006 offsetT opcode_address;
252b5132 9007 unsigned int extension = 0;
847f7ad4 9008 offsetT displacement_from_opcode_start;
252b5132
RH		 9009
9010 opcode = (unsigned char *) fragP->fr_opcode;
9011
47926f60 9012 /* Address we want to reach in file space. */
252b5132 9013 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9014
47926f60 9015 /* Address opcode resides at in file space. */
252b5132
RH		 9016 opcode_address = fragP->fr_address + fragP->fr_fix;
9017
47926f60 9018 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9019 displacement_from_opcode_start = target_address - opcode_address;
9020
fddf5b5b 9021 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9022 {
47926f60
KH		 9023 /* Don't have to change opcode. */
9024 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9025 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9026 }
9027 else
9028 {
9029 if (no_cond_jump_promotion
9030 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9031 as_warn_where (fragP->fr_file, fragP->fr_line,
9032 _("long jump required"));
252b5132 9033
fddf5b5b
AM		 9034 switch (fragP->fr_subtype)
9035 {
9036 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9037 extension = 4; /* 1 opcode + 4 displacement */
9038 opcode[0] = 0xe9;
9039 where_to_put_displacement = &opcode[1];
9040 break;
252b5132 9041
fddf5b5b
AM		 9042 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9043 extension = 2; /* 1 opcode + 2 displacement */
9044 opcode[0] = 0xe9;
9045 where_to_put_displacement = &opcode[1];
9046 break;
252b5132 9047
fddf5b5b
AM		 9048 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9049 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9050 extension = 5; /* 2 opcode + 4 displacement */
9051 opcode[1] = opcode[0] + 0x10;
9052 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9053 where_to_put_displacement = &opcode[2];
9054 break;
252b5132 9055
fddf5b5b
AM		 9056 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9057 extension = 3; /* 2 opcode + 2 displacement */
9058 opcode[1] = opcode[0] + 0x10;
9059 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9060 where_to_put_displacement = &opcode[2];
9061 break;
252b5132 9062
fddf5b5b
AM		 9063 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9064 extension = 4;
9065 opcode[0] ^= 1;
9066 opcode[1] = 3;
9067 opcode[2] = 0xe9;
9068 where_to_put_displacement = &opcode[3];
9069 break;
9070
9071 default:
9072 BAD_CASE (fragP->fr_subtype);
9073 break;
9074 }
252b5132 9075 }
fddf5b5b 9076
7b81dfbb
AJ		 9077 /* If size if less then four we are sure that the operand fits,
9078 but if it's 4, then it could be that the displacement is larger
9079 then -/+ 2GB. */
9080 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9081 && object_64bit
9082 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9083 + ((addressT) 1 << 31))
9084 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9085 {
9086 as_bad_where (fragP->fr_file, fragP->fr_line,
9087 _("jump target out of range"));
9088 /* Make us emit 0. */
9089 displacement_from_opcode_start = extension;
9090 }
47926f60 9091 /* Now put displacement after opcode. */
252b5132
RH		 9092 md_number_to_chars ((char *) where_to_put_displacement,
9093 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9094 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9095 fragP->fr_fix += extension;
9096}
9097\f
7016a5d5 9098/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9099 by our caller that we have all the info we need to fix it up.
9100
7016a5d5
TG		 9101 Parameter valP is the pointer to the value of the bits.
9102
252b5132
RH		 9103 On the 386, immediates, displacements, and data pointers are all in
9104 the same (little-endian) format, so we don't need to care about which
9105 we are handling. */
9106
94f592af 9107void
7016a5d5 9108md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9109{
94f592af 9110 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9111 valueT value = *valP;
252b5132 9112
f86103b7 9113#if !defined (TE_Mach)
93382f6d
AM		 9114 if (fixP->fx_pcrel)
9115 {
9116 switch (fixP->fx_r_type)
9117 {
5865bb77
ILT		 9118 default:
9119 break;
9120
d6ab8113
JB		 9121 case BFD_RELOC_64:
9122 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9123 break;
93382f6d 9124 case BFD_RELOC_32:
ae8887b5 9125 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9126 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9127 break;
9128 case BFD_RELOC_16:
9129 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9130 break;
9131 case BFD_RELOC_8:
9132 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9133 break;
9134 }
9135 }
252b5132 9136
a161fe53 9137 if (fixP->fx_addsy != NULL
31312f95 9138 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9139 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9140 || fixP->fx_r_type == BFD_RELOC_16_PCREL
c3320543
L		 9141 || fixP->fx_r_type == BFD_RELOC_8_PCREL
9142 || fixP->fx_r_type == BFD_RELOC_X86_64_PC32_BND)
31312f95 9143 && !use_rela_relocations)
252b5132 9144 {
31312f95
AM		 9145 /* This is a hack. There should be a better way to handle this.
9146 This covers for the fact that bfd_install_relocation will
9147 subtract the current location (for partial_inplace, PC relative
9148 relocations); see more below. */
252b5132 9149#ifndef OBJ_AOUT
718ddfc0 9150 if (IS_ELF
252b5132
RH		 9151#ifdef TE_PE
9152 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9153#endif
9154 )
9155 value += fixP->fx_where + fixP->fx_frag->fr_address;
9156#endif
9157#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9158 if (IS_ELF)
252b5132 9159 {
6539b54b 9160 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9161
6539b54b 9162 if ((sym_seg == seg
2f66722d 9163 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9164 && sym_seg != absolute_section))
af65af87 9165 && !generic_force_reloc (fixP))
2f66722d
AM		 9166 {
9167 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9168 bfd_install_relocation subtracts them out again. I think
9169 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9170 it. FIXME. */
9171 value += fixP->fx_where + fixP->fx_frag->fr_address;
9172 }
252b5132
RH		 9173 }
9174#endif
9175#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9176 /* For some reason, the PE format does not store a
9177 section address offset for a PC relative symbol. */
9178 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9179 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9180 value += md_pcrel_from (fixP);
9181#endif
9182 }
fbeb56a4 9183#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9184 if (fixP->fx_addsy != NULL
9185 && S_IS_WEAK (fixP->fx_addsy)
9186 /* PR 16858: Do not modify weak function references. */
9187 && ! fixP->fx_pcrel)
fbeb56a4 9188 {
296a8689
NC		 9189#if !defined (TE_PEP)
9190 /* For x86 PE weak function symbols are neither PC-relative
9191 nor do they set S_IS_FUNCTION. So the only reliable way
9192 to detect them is to check the flags of their containing
9193 section. */
9194 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9195 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9196 ;
9197 else
9198#endif
fbeb56a4
DK		 9199 value -= S_GET_VALUE (fixP->fx_addsy);
9200 }
9201#endif
252b5132
RH		 9202
9203 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9204 and we must not disappoint it. */
252b5132 9205#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9206 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9207 switch (fixP->fx_r_type)
9208 {
9209 case BFD_RELOC_386_PLT32:
3e73aa7c 9210 case BFD_RELOC_X86_64_PLT32:
c3320543 9211 case BFD_RELOC_X86_64_PLT32_BND:
47926f60
KH		 9212 /* Make the jump instruction point to the address of the operand. At
9213 runtime we merely add the offset to the actual PLT entry. */
9214 value = -4;
9215 break;
31312f95 9216
13ae64f3
JJ		 9217 case BFD_RELOC_386_TLS_GD:
9218 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9219 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9220 case BFD_RELOC_386_TLS_IE:
9221 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9222 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9223 case BFD_RELOC_X86_64_TLSGD:
9224 case BFD_RELOC_X86_64_TLSLD:
9225 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9226 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9227 value = 0; /* Fully resolved at runtime. No addend. */
9228 /* Fallthrough */
9229 case BFD_RELOC_386_TLS_LE:
9230 case BFD_RELOC_386_TLS_LDO_32:
9231 case BFD_RELOC_386_TLS_LE_32:
9232 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9233 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9234 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9235 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9236 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9237 break;
9238
67a4f2b7
AO		 9239 case BFD_RELOC_386_TLS_DESC_CALL:
9240 case BFD_RELOC_X86_64_TLSDESC_CALL:
9241 value = 0; /* Fully resolved at runtime. No addend. */
9242 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9243 fixP->fx_done = 0;
9244 return;
9245
00f7efb6
JJ		 9246 case BFD_RELOC_386_GOT32:
9247 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9248 value = 0; /* Fully resolved at runtime. No addend. */
9249 break;
47926f60
KH		 9250
9251 case BFD_RELOC_VTABLE_INHERIT:
9252 case BFD_RELOC_VTABLE_ENTRY:
9253 fixP->fx_done = 0;
94f592af 9254 return;
47926f60
KH		 9255
9256 default:
9257 break;
9258 }
9259#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9260 *valP = value;
f86103b7 9261#endif /* !defined (TE_Mach) */
3e73aa7c 9262
3e73aa7c 9263 /* Are we finished with this relocation now? */
c6682705 9264 if (fixP->fx_addsy == NULL)
3e73aa7c 9265 fixP->fx_done = 1;
fbeb56a4
DK		 9266#if defined (OBJ_COFF) && defined (TE_PE)
9267 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9268 {
9269 fixP->fx_done = 0;
9270 /* Remember value for tc_gen_reloc. */
9271 fixP->fx_addnumber = value;
9272 /* Clear out the frag for now. */
9273 value = 0;
9274 }
9275#endif
3e73aa7c
JH		 9276 else if (use_rela_relocations)
9277 {
9278 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9279 /* Remember value for tc_gen_reloc. */
9280 fixP->fx_addnumber = value;
3e73aa7c
JH		 9281 value = 0;
9282 }
f86103b7 9283
94f592af 9284 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9285}
252b5132 9286\f
252b5132 9287char *
499ac353 9288md_atof (int type, char *litP, int *sizeP)
252b5132 9289{
499ac353
NC		 9290 /* This outputs the LITTLENUMs in REVERSE order;
9291 in accord with the bigendian 386. */
9292 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9293}
9294\f
2d545b82 9295static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9296
252b5132 9297static char *
e3bb37b5 9298output_invalid (int c)
252b5132 9299{
3882b010 9300 if (ISPRINT (c))
f9f21a03
L		 9301 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9302 "'%c'", c);
252b5132 9303 else
f9f21a03 9304 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9305 "(0x%x)", (unsigned char) c);
252b5132
RH		 9306 return output_invalid_buf;
9307}
9308
af6bdddf 9309/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9310
9311static const reg_entry *
4d1bb795 9312parse_real_register (char *reg_string, char **end_op)
252b5132 9313{
af6bdddf
AM		 9314 char *s = reg_string;
9315 char *p;
252b5132
RH		 9316 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9317 const reg_entry *r;
9318
9319 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9320 if (*s == REGISTER_PREFIX)
9321 ++s;
9322
9323 if (is_space_char (*s))
9324 ++s;
9325
9326 p = reg_name_given;
af6bdddf 9327 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9328 {
9329 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9330 return (const reg_entry *) NULL;
9331 s++;
252b5132
RH		 9332 }
9333
6588847e
DN		 9334 /* For naked regs, make sure that we are not dealing with an identifier.
9335 This prevents confusing an identifier like `eax_var' with register
9336 `eax'. */
9337 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9338 return (const reg_entry *) NULL;
9339
af6bdddf 9340 *end_op = s;
252b5132
RH		 9341
9342 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9343
5f47d35b 9344 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9345 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9346 {
5f47d35b
AM		 9347 if (is_space_char (*s))
9348 ++s;
9349 if (*s == '(')
9350 {
af6bdddf 9351 ++s;
5f47d35b
AM		 9352 if (is_space_char (*s))
9353 ++s;
9354 if (*s >= '0' && *s <= '7')
9355 {
db557034 9356 int fpr = *s - '0';
af6bdddf 9357 ++s;
5f47d35b
AM		 9358 if (is_space_char (*s))
9359 ++s;
9360 if (*s == ')')
9361 {
9362 *end_op = s + 1;
1e9cc1c2 9363 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9364 know (r);
9365 return r + fpr;
5f47d35b 9366 }
5f47d35b 9367 }
47926f60 9368 /* We have "%st(" then garbage. */
5f47d35b
AM		 9369 return (const reg_entry *) NULL;
9370 }
9371 }
9372
a60de03c
JB		 9373 if (r == NULL || allow_pseudo_reg)
9374 return r;
9375
0dfbf9d7 9376 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9377 return (const reg_entry *) NULL;
9378
192dc9c6
JB		 9379 if ((r->reg_type.bitfield.reg32
9380 || r->reg_type.bitfield.sreg3
9381 || r->reg_type.bitfield.control
9382 || r->reg_type.bitfield.debug
9383 || r->reg_type.bitfield.test)
9384 && !cpu_arch_flags.bitfield.cpui386)
9385 return (const reg_entry *) NULL;
9386
309d3373
JB		 9387 if (r->reg_type.bitfield.floatreg
9388 && !cpu_arch_flags.bitfield.cpu8087
9389 && !cpu_arch_flags.bitfield.cpu287
9390 && !cpu_arch_flags.bitfield.cpu387)
9391 return (const reg_entry *) NULL;
9392
192dc9c6
JB		 9393 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9394 return (const reg_entry *) NULL;
9395
9396 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9397 return (const reg_entry *) NULL;
9398
40f12533
L		 9399 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9400 return (const reg_entry *) NULL;
9401
43234a1e
L		 9402 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9403 && !cpu_arch_flags.bitfield.cpuavx512f)
9404 return (const reg_entry *) NULL;
9405
db51cc60 9406 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9407 if (!allow_index_reg
db51cc60
L		 9408 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9409 return (const reg_entry *) NULL;
9410
43234a1e
L		 9411 /* Upper 16 vector register is only available with VREX in 64bit
9412 mode. */
9413 if ((r->reg_flags & RegVRex))
9414 {
9415 if (!cpu_arch_flags.bitfield.cpuvrex
9416 || flag_code != CODE_64BIT)
9417 return (const reg_entry *) NULL;
9418
9419 i.need_vrex = 1;
9420 }
9421
a60de03c
JB		 9422 if (((r->reg_flags & (RegRex64 | RegRex))
9423 || r->reg_type.bitfield.reg64)
40fb9820 9424 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9425 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9426 && flag_code != CODE_64BIT)
20f0a1fc 9427 return (const reg_entry *) NULL;
1ae00879 9428
b7240065
JB		 9429 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9430 return (const reg_entry *) NULL;
9431
252b5132
RH		 9432 return r;
9433}
4d1bb795
JB		 9434
9435/* REG_STRING starts *before* REGISTER_PREFIX. */
9436
9437static const reg_entry *
9438parse_register (char *reg_string, char **end_op)
9439{
9440 const reg_entry *r;
9441
9442 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9443 r = parse_real_register (reg_string, end_op);
9444 else
9445 r = NULL;
9446 if (!r)
9447 {
9448 char *save = input_line_pointer;
9449 char c;
9450 symbolS *symbolP;
9451
9452 input_line_pointer = reg_string;
9453 c = get_symbol_end ();
9454 symbolP = symbol_find (reg_string);
9455 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9456 {
9457 const expressionS *e = symbol_get_value_expression (symbolP);
9458
0398aac5 9459 know (e->X_op == O_register);
4eed87de 9460 know (e->X_add_number >= 0
c3fe08fa 9461 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9462 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9463 if ((r->reg_flags & RegVRex))
9464 i.need_vrex = 1;
4d1bb795
JB		 9465 *end_op = input_line_pointer;
9466 }
9467 *input_line_pointer = c;
9468 input_line_pointer = save;
9469 }
9470 return r;
9471}
9472
9473int
9474i386_parse_name (char *name, expressionS *e, char *nextcharP)
9475{
9476 const reg_entry *r;
9477 char *end = input_line_pointer;
9478
9479 *end = *nextcharP;
9480 r = parse_register (name, &input_line_pointer);
9481 if (r && end <= input_line_pointer)
9482 {
9483 *nextcharP = *input_line_pointer;
9484 *input_line_pointer = 0;
9485 e->X_op = O_register;
9486 e->X_add_number = r - i386_regtab;
9487 return 1;
9488 }
9489 input_line_pointer = end;
9490 *end = 0;
ee86248c 9491 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9492}
9493
9494void
9495md_operand (expressionS *e)
9496{
ee86248c
JB		 9497 char *end;
9498 const reg_entry *r;
4d1bb795 9499
ee86248c
JB		 9500 switch (*input_line_pointer)
9501 {
9502 case REGISTER_PREFIX:
9503 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9504 if (r)
9505 {
9506 e->X_op = O_register;
9507 e->X_add_number = r - i386_regtab;
9508 input_line_pointer = end;
9509 }
ee86248c
JB		 9510 break;
9511
9512 case '[':
9c2799c2 9513 gas_assert (intel_syntax);
ee86248c
JB		 9514 end = input_line_pointer++;
9515 expression (e);
9516 if (*input_line_pointer == ']')
9517 {
9518 ++input_line_pointer;
9519 e->X_op_symbol = make_expr_symbol (e);
9520 e->X_add_symbol = NULL;
9521 e->X_add_number = 0;
9522 e->X_op = O_index;
9523 }
9524 else
9525 {
9526 e->X_op = O_absent;
9527 input_line_pointer = end;
9528 }
9529 break;
4d1bb795
JB		 9530 }
9531}
9532
252b5132 9533\f
4cc782b5 9534#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9535const char *md_shortopts = "kVQ:sqn";
252b5132 9536#else
12b55ccc 9537const char *md_shortopts = "qn";
252b5132 9538#endif
6e0b89ee 9539
3e73aa7c 9540#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9541#define OPTION_64 (OPTION_MD_BASE + 1)
9542#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9543#define OPTION_MARCH (OPTION_MD_BASE + 3)
9544#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9545#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9546#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9547#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9548#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9549#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9550#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9551#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9552#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9553#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9554#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9555#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9556#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9557#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9558#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
a5094208 9559#define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9560#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
b3b91714 9561
99ad8390
NC		 9562struct option md_longopts[] =
9563{
3e73aa7c 9564 {"32", no_argument, NULL, OPTION_32},
321098a5 9565#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9566 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9567 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9568#endif
9569#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9570 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 9571#endif
b3b91714 9572 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9573 {"march", required_argument, NULL, OPTION_MARCH},
9574 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9575 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9576 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9577 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9578 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9579 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9580 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9581 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9582 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9583 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9584 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9585 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9586 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9587# if defined (TE_PE) || defined (TE_PEP)
9588 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9589#endif
a5094208 9590 {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX},
d3d3c6db 9591 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
252b5132
RH		 9592 {NULL, no_argument, NULL, 0}
9593};
9594size_t md_longopts_size = sizeof (md_longopts);
9595
9596int
9103f4f4 9597md_parse_option (int c, char *arg)
252b5132 9598{
91d6fa6a 9599 unsigned int j;
6305a203 9600 char *arch, *next;
9103f4f4 9601
252b5132
RH		 9602 switch (c)
9603 {
12b55ccc
L		 9604 case 'n':
9605 optimize_align_code = 0;
9606 break;
9607
a38cf1db
AM		 9608 case 'q':
9609 quiet_warnings = 1;
252b5132
RH		 9610 break;
9611
9612#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9613 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9614 should be emitted or not. FIXME: Not implemented. */
9615 case 'Q':
252b5132
RH		 9616 break;
9617
9618 /* -V: SVR4 argument to print version ID. */
9619 case 'V':
9620 print_version_id ();
9621 break;
9622
a38cf1db
AM		 9623 /* -k: Ignore for FreeBSD compatibility. */
9624 case 'k':
252b5132 9625 break;
4cc782b5
ILT		 9626
9627 case 's':
9628 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9629 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9630 break;
99ad8390 9631#endif
321098a5 9632#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9633 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9634 case OPTION_64:
9635 {
9636 const char **list, **l;
9637
3e73aa7c
JH		 9638 list = bfd_target_list ();
9639 for (l = list; *l != NULL; l++)
8620418b 9640 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9641 || strcmp (*l, "coff-x86-64") == 0
9642 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9643 || strcmp (*l, "pei-x86-64") == 0
9644 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9645 {
9646 default_arch = "x86_64";
9647 break;
9648 }
3e73aa7c 9649 if (*l == NULL)
2b5d6a91 9650 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9651 free (list);
9652 }
9653 break;
9654#endif
252b5132 9655
351f65ca 9656#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9657 case OPTION_X32:
351f65ca
L		 9658 if (IS_ELF)
9659 {
9660 const char **list, **l;
9661
9662 list = bfd_target_list ();
9663 for (l = list; *l != NULL; l++)
9664 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9665 {
9666 default_arch = "x86_64:32";
9667 break;
9668 }
9669 if (*l == NULL)
2b5d6a91 9670 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9671 free (list);
9672 }
9673 else
9674 as_fatal (_("32bit x86_64 is only supported for ELF"));
9675 break;
9676#endif
9677
6e0b89ee
AM		 9678 case OPTION_32:
9679 default_arch = "i386";
9680 break;
9681
b3b91714
AM		 9682 case OPTION_DIVIDE:
9683#ifdef SVR4_COMMENT_CHARS
9684 {
9685 char *n, *t;
9686 const char *s;
9687
9688 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9689 t = n;
9690 for (s = i386_comment_chars; *s != '\0'; s++)
9691 if (*s != '/')
9692 *t++ = *s;
9693 *t = '\0';
9694 i386_comment_chars = n;
9695 }
9696#endif
9697 break;
9698
9103f4f4 9699 case OPTION_MARCH:
6305a203
L		 9700 arch = xstrdup (arg);
9701 do
9103f4f4 9702 {
6305a203 9703 if (*arch == '.')
2b5d6a91 9704 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9705 next = strchr (arch, '+');
9706 if (next)
9707 *next++ = '\0';
91d6fa6a 9708 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9709 {
91d6fa6a 9710 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9711 {
6305a203 9712 /* Processor. */
1ded5609
JB		 9713 if (! cpu_arch[j].flags.bitfield.cpui386)
9714 continue;
9715
91d6fa6a 9716 cpu_arch_name = cpu_arch[j].name;
6305a203 9717 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9718 cpu_arch_flags = cpu_arch[j].flags;
9719 cpu_arch_isa = cpu_arch[j].type;
9720 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9721 if (!cpu_arch_tune_set)
9722 {
9723 cpu_arch_tune = cpu_arch_isa;
9724 cpu_arch_tune_flags = cpu_arch_isa_flags;
9725 }
9726 break;
9727 }
91d6fa6a
NC		 9728 else if (*cpu_arch [j].name == '.'
9729 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9730 {
9731 /* ISA entension. */
9732 i386_cpu_flags flags;
309d3373 9733
49021df2 9734 if (!cpu_arch[j].negated)
309d3373 9735 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9736 cpu_arch[j].flags);
309d3373
JB		 9737 else
9738 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9739 cpu_arch[j].flags);
0dfbf9d7 9740 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9741 {
9742 if (cpu_sub_arch_name)
9743 {
9744 char *name = cpu_sub_arch_name;
9745 cpu_sub_arch_name = concat (name,
91d6fa6a 9746 cpu_arch[j].name,
1bf57e9f 9747 (const char *) NULL);
6305a203
L		 9748 free (name);
9749 }
9750 else
91d6fa6a 9751 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9752 cpu_arch_flags = flags;
a586129e 9753 cpu_arch_isa_flags = flags;
6305a203
L		 9754 }
9755 break;
ccc9c027 9756 }
9103f4f4 9757 }
6305a203 9758
91d6fa6a 9759 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9760 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9761
9762 arch = next;
9103f4f4 9763 }
6305a203 9764 while (next != NULL );
9103f4f4
L		 9765 break;
9766
9767 case OPTION_MTUNE:
9768 if (*arg == '.')
2b5d6a91 9769 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9770 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9771 {
91d6fa6a 9772 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9773 {
ccc9c027 9774 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9775 cpu_arch_tune = cpu_arch [j].type;
9776 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9777 break;
9778 }
9779 }
91d6fa6a 9780 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9781 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9782 break;
9783
1efbbeb4
L		 9784 case OPTION_MMNEMONIC:
9785 if (strcasecmp (arg, "att") == 0)
9786 intel_mnemonic = 0;
9787 else if (strcasecmp (arg, "intel") == 0)
9788 intel_mnemonic = 1;
9789 else
2b5d6a91 9790 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9791 break;
9792
9793 case OPTION_MSYNTAX:
9794 if (strcasecmp (arg, "att") == 0)
9795 intel_syntax = 0;
9796 else if (strcasecmp (arg, "intel") == 0)
9797 intel_syntax = 1;
9798 else
2b5d6a91 9799 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9800 break;
9801
9802 case OPTION_MINDEX_REG:
9803 allow_index_reg = 1;
9804 break;
9805
9806 case OPTION_MNAKED_REG:
9807 allow_naked_reg = 1;
9808 break;
9809
9810 case OPTION_MOLD_GCC:
9811 old_gcc = 1;
1efbbeb4
L		 9812 break;
9813
c0f3af97
L		 9814 case OPTION_MSSE2AVX:
9815 sse2avx = 1;
9816 break;
9817
daf50ae7
L		 9818 case OPTION_MSSE_CHECK:
9819 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9820 sse_check = check_error;
daf50ae7 9821 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9822 sse_check = check_warning;
daf50ae7 9823 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9824 sse_check = check_none;
daf50ae7 9825 else
2b5d6a91 9826 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9827 break;
9828
7bab8ab5
JB		 9829 case OPTION_MOPERAND_CHECK:
9830 if (strcasecmp (arg, "error") == 0)
9831 operand_check = check_error;
9832 else if (strcasecmp (arg, "warning") == 0)
9833 operand_check = check_warning;
9834 else if (strcasecmp (arg, "none") == 0)
9835 operand_check = check_none;
9836 else
9837 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9838 break;
9839
539f890d
L		 9840 case OPTION_MAVXSCALAR:
9841 if (strcasecmp (arg, "128") == 0)
9842 avxscalar = vex128;
9843 else if (strcasecmp (arg, "256") == 0)
9844 avxscalar = vex256;
9845 else
2b5d6a91 9846 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9847 break;
9848
7e8b059b
L		 9849 case OPTION_MADD_BND_PREFIX:
9850 add_bnd_prefix = 1;
9851 break;
9852
43234a1e
L		 9853 case OPTION_MEVEXLIG:
9854 if (strcmp (arg, "128") == 0)
9855 evexlig = evexl128;
9856 else if (strcmp (arg, "256") == 0)
9857 evexlig = evexl256;
9858 else if (strcmp (arg, "512") == 0)
9859 evexlig = evexl512;
9860 else
9861 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9862 break;
9863
d3d3c6db
IT		 9864 case OPTION_MEVEXRCIG:
9865 if (strcmp (arg, "rne") == 0)
9866 evexrcig = rne;
9867 else if (strcmp (arg, "rd") == 0)
9868 evexrcig = rd;
9869 else if (strcmp (arg, "ru") == 0)
9870 evexrcig = ru;
9871 else if (strcmp (arg, "rz") == 0)
9872 evexrcig = rz;
9873 else
9874 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
9875 break;
9876
43234a1e
L		 9877 case OPTION_MEVEXWIG:
9878 if (strcmp (arg, "0") == 0)
9879 evexwig = evexw0;
9880 else if (strcmp (arg, "1") == 0)
9881 evexwig = evexw1;
9882 else
9883 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9884 break;
9885
167ad85b
TG		 9886# if defined (TE_PE) || defined (TE_PEP)
9887 case OPTION_MBIG_OBJ:
9888 use_big_obj = 1;
9889 break;
9890#endif
9891
a5094208 9892 case OPTION_OMIT_LOCK_PREFIX:
d022bddd
IT		 9893 if (strcasecmp (arg, "yes") == 0)
9894 omit_lock_prefix = 1;
9895 else if (strcasecmp (arg, "no") == 0)
9896 omit_lock_prefix = 0;
9897 else
9898 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
9899 break;
9900
252b5132
RH		 9901 default:
9902 return 0;
9903 }
9904 return 1;
9905}
9906
8a2c8fef
L		 9907#define MESSAGE_TEMPLATE \
9908" "
9909
9910static void
1ded5609 9911show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9912{
9913 static char message[] = MESSAGE_TEMPLATE;
9914 char *start = message + 27;
9915 char *p;
9916 int size = sizeof (MESSAGE_TEMPLATE);
9917 int left;
9918 const char *name;
9919 int len;
9920 unsigned int j;
9921
9922 p = start;
9923 left = size - (start - message);
9924 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9925 {
9926 /* Should it be skipped? */
9927 if (cpu_arch [j].skip)
9928 continue;
9929
9930 name = cpu_arch [j].name;
9931 len = cpu_arch [j].len;
9932 if (*name == '.')
9933 {
9934 /* It is an extension. Skip if we aren't asked to show it. */
9935 if (ext)
9936 {
9937 name++;
9938 len--;
9939 }
9940 else
9941 continue;
9942 }
9943 else if (ext)
9944 {
9945 /* It is an processor. Skip if we show only extension. */
9946 continue;
9947 }
1ded5609
JB		 9948 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9949 {
9950 /* It is an impossible processor - skip. */
9951 continue;
9952 }
8a2c8fef
L		 9953
9954 /* Reserve 2 spaces for ", " or ",\0" */
9955 left -= len + 2;
9956
9957 /* Check if there is any room. */
9958 if (left >= 0)
9959 {
9960 if (p != start)
9961 {
9962 *p++ = ',';
9963 *p++ = ' ';
9964 }
9965 p = mempcpy (p, name, len);
9966 }
9967 else
9968 {
9969 /* Output the current message now and start a new one. */
9970 *p++ = ',';
9971 *p = '\0';
9972 fprintf (stream, "%s\n", message);
9973 p = start;
9974 left = size - (start - message) - len - 2;
8d63c93e 9975
8a2c8fef
L		 9976 gas_assert (left >= 0);
9977
9978 p = mempcpy (p, name, len);
9979 }
9980 }
9981
9982 *p = '\0';
9983 fprintf (stream, "%s\n", message);
9984}
9985
252b5132 9986void
8a2c8fef 9987md_show_usage (FILE *stream)
252b5132 9988{
4cc782b5
ILT		 9989#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9990 fprintf (stream, _("\
a38cf1db
AM		 9991 -Q ignored\n\
9992 -V print assembler version number\n\
b3b91714
AM		 9993 -k ignored\n"));
9994#endif
9995 fprintf (stream, _("\
12b55ccc 9996 -n Do not optimize code alignment\n\
b3b91714
AM		 9997 -q quieten some warnings\n"));
9998#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9999 fprintf (stream, _("\
a38cf1db 10000 -s ignored\n"));
b3b91714 10001#endif
321098a5
L		 10002#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10003 || defined (TE_PE) || defined (TE_PEP))
751d281c 10004 fprintf (stream, _("\
570561f7 10005 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10006#endif
b3b91714
AM		 10007#ifdef SVR4_COMMENT_CHARS
10008 fprintf (stream, _("\
10009 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10010#else
10011 fprintf (stream, _("\
b3b91714 10012 --divide ignored\n"));
4cc782b5 10013#endif
9103f4f4 10014 fprintf (stream, _("\
6305a203 10015 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10016 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10017 show_arch (stream, 0, 1);
8a2c8fef
L		 10018 fprintf (stream, _("\
10019 EXTENSION is combination of:\n"));
1ded5609 10020 show_arch (stream, 1, 0);
6305a203 10021 fprintf (stream, _("\
8a2c8fef 10022 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10023 show_arch (stream, 0, 0);
ba104c83 10024 fprintf (stream, _("\
c0f3af97
L		 10025 -msse2avx encode SSE instructions with VEX prefix\n"));
10026 fprintf (stream, _("\
daf50ae7
L		 10027 -msse-check=[none|error|warning]\n\
10028 check SSE instructions\n"));
10029 fprintf (stream, _("\
7bab8ab5
JB		 10030 -moperand-check=[none|error|warning]\n\
10031 check operand combinations for validity\n"));
10032 fprintf (stream, _("\
539f890d
L		 10033 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10034 length\n"));
10035 fprintf (stream, _("\
43234a1e
L		 10036 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10037 length\n"));
10038 fprintf (stream, _("\
10039 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10040 for EVEX.W bit ignored instructions\n"));
10041 fprintf (stream, _("\
d3d3c6db
IT		 10042 -mevexrcig=[rne|rd|ru|rz]\n\
10043 encode EVEX instructions with specific EVEX.RC value\n\
10044 for SAE-only ignored instructions\n"));
10045 fprintf (stream, _("\
ba104c83
L		 10046 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10047 fprintf (stream, _("\
10048 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10049 fprintf (stream, _("\
10050 -mindex-reg support pseudo index registers\n"));
10051 fprintf (stream, _("\
10052 -mnaked-reg don't require `%%' prefix for registers\n"));
10053 fprintf (stream, _("\
10054 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10055 fprintf (stream, _("\
10056 -madd-bnd-prefix add BND prefix for all valid branches\n"));
167ad85b
TG		 10057# if defined (TE_PE) || defined (TE_PEP)
10058 fprintf (stream, _("\
10059 -mbig-obj generate big object files\n"));
10060#endif
d022bddd
IT		 10061 fprintf (stream, _("\
10062 -momit-lock-prefix=[no|yes]\n\
10063 strip all lock prefixes\n"));
252b5132
RH		 10064}
10065
3e73aa7c 10066#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10067 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10068 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10069
10070/* Pick the target format to use. */
10071
47926f60 10072const char *
e3bb37b5 10073i386_target_format (void)
252b5132 10074{
351f65ca
L		 10075 if (!strncmp (default_arch, "x86_64", 6))
10076 {
10077 update_code_flag (CODE_64BIT, 1);
10078 if (default_arch[6] == '\0')
7f56bc95 10079 x86_elf_abi = X86_64_ABI;
351f65ca 10080 else
7f56bc95 10081 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10082 }
3e73aa7c 10083 else if (!strcmp (default_arch, "i386"))
78f12dd3 10084 update_code_flag (CODE_32BIT, 1);
3e73aa7c 10085 else
2b5d6a91 10086 as_fatal (_("unknown architecture"));
89507696
JB		 10087
10088 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10089 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10090 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10091 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10092
252b5132
RH		 10093 switch (OUTPUT_FLAVOR)
10094 {
9384f2ff 10095#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10096 case bfd_target_aout_flavour:
47926f60 10097 return AOUT_TARGET_FORMAT;
4c63da97 10098#endif
9384f2ff
AM		 10099#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10100# if defined (TE_PE) || defined (TE_PEP)
10101 case bfd_target_coff_flavour:
167ad85b
TG		 10102 if (flag_code == CODE_64BIT)
10103 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10104 else
10105 return "pe-i386";
9384f2ff 10106# elif defined (TE_GO32)
0561d57c
JK		 10107 case bfd_target_coff_flavour:
10108 return "coff-go32";
9384f2ff 10109# else
252b5132
RH		 10110 case bfd_target_coff_flavour:
10111 return "coff-i386";
9384f2ff 10112# endif
4c63da97 10113#endif
3e73aa7c 10114#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10115 case bfd_target_elf_flavour:
3e73aa7c 10116 {
351f65ca
L		 10117 const char *format;
10118
10119 switch (x86_elf_abi)
4fa24527 10120 {
351f65ca
L		 10121 default:
10122 format = ELF_TARGET_FORMAT;
10123 break;
7f56bc95 10124 case X86_64_ABI:
351f65ca 10125 use_rela_relocations = 1;
4fa24527 10126 object_64bit = 1;
351f65ca
L		 10127 format = ELF_TARGET_FORMAT64;
10128 break;
7f56bc95 10129 case X86_64_X32_ABI:
4fa24527 10130 use_rela_relocations = 1;
351f65ca 10131 object_64bit = 1;
862be3fb 10132 disallow_64bit_reloc = 1;
351f65ca
L		 10133 format = ELF_TARGET_FORMAT32;
10134 break;
4fa24527 10135 }
3632d14b 10136 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10137 {
7f56bc95 10138 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10139 as_fatal (_("Intel L1OM is 64bit only"));
10140 return ELF_TARGET_L1OM_FORMAT;
10141 }
7a9068fe
L		 10142 if (cpu_arch_isa == PROCESSOR_K1OM)
10143 {
10144 if (x86_elf_abi != X86_64_ABI)
10145 as_fatal (_("Intel K1OM is 64bit only"));
10146 return ELF_TARGET_K1OM_FORMAT;
10147 }
8a9036a4 10148 else
351f65ca 10149 return format;
3e73aa7c 10150 }
e57f8c65
TG		 10151#endif
10152#if defined (OBJ_MACH_O)
10153 case bfd_target_mach_o_flavour:
d382c579
TG		 10154 if (flag_code == CODE_64BIT)
10155 {
10156 use_rela_relocations = 1;
10157 object_64bit = 1;
10158 return "mach-o-x86-64";
10159 }
10160 else
10161 return "mach-o-i386";
4c63da97 10162#endif
252b5132
RH		 10163 default:
10164 abort ();
10165 return NULL;
10166 }
10167}
10168
47926f60 10169#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 10170
10171#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 10172void
10173i386_elf_emit_arch_note (void)
a847613f 10174{
718ddfc0 10175 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 10176 {
10177 char *p;
10178 asection *seg = now_seg;
10179 subsegT subseg = now_subseg;
10180 Elf_Internal_Note i_note;
10181 Elf_External_Note e_note;
10182 asection *note_secp;
10183 int len;
10184
10185 /* Create the .note section. */
10186 note_secp = subseg_new (".note", 0);
10187 bfd_set_section_flags (stdoutput,
10188 note_secp,
10189 SEC_HAS_CONTENTS | SEC_READONLY);
10190
10191 /* Process the arch string. */
10192 len = strlen (cpu_arch_name);
10193
10194 i_note.namesz = len + 1;
10195 i_note.descsz = 0;
10196 i_note.type = NT_ARCH;
10197 p = frag_more (sizeof (e_note.namesz));
10198 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
10199 p = frag_more (sizeof (e_note.descsz));
10200 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
10201 p = frag_more (sizeof (e_note.type));
10202 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
10203 p = frag_more (len + 1);
10204 strcpy (p, cpu_arch_name);
10205
10206 frag_align (2, 0, 0);
10207
10208 subseg_set (seg, subseg);
10209 }
10210}
10211#endif
252b5132 10212\f
252b5132 10213symbolS *
7016a5d5 10214md_undefined_symbol (char *name)
252b5132 10215{
18dc2407
ILT		 10216 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10217 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10218 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10219 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10220 {
10221 if (!GOT_symbol)
10222 {
10223 if (symbol_find (name))
10224 as_bad (_("GOT already in symbol table"));
10225 GOT_symbol = symbol_new (name, undefined_section,
10226 (valueT) 0, &zero_address_frag);
10227 };
10228 return GOT_symbol;
10229 }
252b5132
RH		 10230 return 0;
10231}
10232
10233/* Round up a section size to the appropriate boundary. */
47926f60 10234
252b5132 10235valueT
7016a5d5 10236md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10237{
4c63da97
AM		 10238#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10239 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10240 {
10241 /* For a.out, force the section size to be aligned. If we don't do
10242 this, BFD will align it for us, but it will not write out the
10243 final bytes of the section. This may be a bug in BFD, but it is
10244 easier to fix it here since that is how the other a.out targets
10245 work. */
10246 int align;
10247
10248 align = bfd_get_section_alignment (stdoutput, segment);
10249 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10250 }
252b5132
RH		 10251#endif
10252
10253 return size;
10254}
10255
10256/* On the i386, PC-relative offsets are relative to the start of the
10257 next instruction. That is, the address of the offset, plus its
10258 size, since the offset is always the last part of the insn. */
10259
10260long
e3bb37b5 10261md_pcrel_from (fixS *fixP)
252b5132
RH		 10262{
10263 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10264}
10265
10266#ifndef I386COFF
10267
10268static void
e3bb37b5 10269s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10270{
29b0f896 10271 int temp;
252b5132 10272
8a75718c
JB		 10273#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10274 if (IS_ELF)
10275 obj_elf_section_change_hook ();
10276#endif
252b5132
RH		 10277 temp = get_absolute_expression ();
10278 subseg_set (bss_section, (subsegT) temp);
10279 demand_empty_rest_of_line ();
10280}
10281
10282#endif
10283
252b5132 10284void
e3bb37b5 10285i386_validate_fix (fixS *fixp)
252b5132
RH		 10286{
10287 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10288 {
23df1078
JH		 10289 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10290 {
4fa24527 10291 if (!object_64bit)
23df1078
JH		 10292 abort ();
10293 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10294 }
10295 else
10296 {
4fa24527 10297 if (!object_64bit)
d6ab8113
JB		 10298 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10299 else
10300 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 10301 }
252b5132
RH		 10302 fixp->fx_subsy = 0;
10303 }
10304}
10305
252b5132 10306arelent *
7016a5d5 10307tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10308{
10309 arelent *rel;
10310 bfd_reloc_code_real_type code;
10311
10312 switch (fixp->fx_r_type)
10313 {
8ce3d284 10314#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10315 case BFD_RELOC_SIZE32:
10316 case BFD_RELOC_SIZE64:
10317 if (S_IS_DEFINED (fixp->fx_addsy)
10318 && !S_IS_EXTERNAL (fixp->fx_addsy))
10319 {
10320 /* Resolve size relocation against local symbol to size of
10321 the symbol plus addend. */
10322 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10323 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10324 && !fits_in_unsigned_long (value))
10325 as_bad_where (fixp->fx_file, fixp->fx_line,
10326 _("symbol size computation overflow"));
10327 fixp->fx_addsy = NULL;
10328 fixp->fx_subsy = NULL;
10329 md_apply_fix (fixp, (valueT *) &value, NULL);
10330 return NULL;
10331 }
8ce3d284 10332#endif
8fd4256d 10333
3e73aa7c 10334 case BFD_RELOC_X86_64_PLT32:
c3320543 10335 case BFD_RELOC_X86_64_PLT32_BND:
3e73aa7c
JH		 10336 case BFD_RELOC_X86_64_GOT32:
10337 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 10338 case BFD_RELOC_386_PLT32:
10339 case BFD_RELOC_386_GOT32:
10340 case BFD_RELOC_386_GOTOFF:
10341 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10342 case BFD_RELOC_386_TLS_GD:
10343 case BFD_RELOC_386_TLS_LDM:
10344 case BFD_RELOC_386_TLS_LDO_32:
10345 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10346 case BFD_RELOC_386_TLS_IE:
10347 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10348 case BFD_RELOC_386_TLS_LE_32:
10349 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10350 case BFD_RELOC_386_TLS_GOTDESC:
10351 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10352 case BFD_RELOC_X86_64_TLSGD:
10353 case BFD_RELOC_X86_64_TLSLD:
10354 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10355 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10356 case BFD_RELOC_X86_64_GOTTPOFF:
10357 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10358 case BFD_RELOC_X86_64_TPOFF64:
10359 case BFD_RELOC_X86_64_GOTOFF64:
10360 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10361 case BFD_RELOC_X86_64_GOT64:
10362 case BFD_RELOC_X86_64_GOTPCREL64:
10363 case BFD_RELOC_X86_64_GOTPC64:
10364 case BFD_RELOC_X86_64_GOTPLT64:
10365 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10366 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10367 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10368 case BFD_RELOC_RVA:
10369 case BFD_RELOC_VTABLE_ENTRY:
10370 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10371#ifdef TE_PE
10372 case BFD_RELOC_32_SECREL:
10373#endif
252b5132
RH		 10374 code = fixp->fx_r_type;
10375 break;
dbbaec26
L		 10376 case BFD_RELOC_X86_64_32S:
10377 if (!fixp->fx_pcrel)
10378 {
10379 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10380 code = fixp->fx_r_type;
10381 break;
10382 }
252b5132 10383 default:
93382f6d 10384 if (fixp->fx_pcrel)
252b5132 10385 {
93382f6d
AM		 10386 switch (fixp->fx_size)
10387 {
10388 default:
b091f402
AM		 10389 as_bad_where (fixp->fx_file, fixp->fx_line,
10390 _("can not do %d byte pc-relative relocation"),
10391 fixp->fx_size);
93382f6d
AM		 10392 code = BFD_RELOC_32_PCREL;
10393 break;
10394 case 1: code = BFD_RELOC_8_PCREL; break;
10395 case 2: code = BFD_RELOC_16_PCREL; break;
c3320543
L		 10396 case 4:
10397 code = (fixp->fx_r_type == BFD_RELOC_X86_64_PC32_BND
10398 ? fixp-> fx_r_type : BFD_RELOC_32_PCREL);
10399 break;
d6ab8113
JB		 10400#ifdef BFD64
10401 case 8: code = BFD_RELOC_64_PCREL; break;
10402#endif
93382f6d
AM		 10403 }
10404 }
10405 else
10406 {
10407 switch (fixp->fx_size)
10408 {
10409 default:
b091f402
AM		 10410 as_bad_where (fixp->fx_file, fixp->fx_line,
10411 _("can not do %d byte relocation"),
10412 fixp->fx_size);
93382f6d
AM		 10413 code = BFD_RELOC_32;
10414 break;
10415 case 1: code = BFD_RELOC_8; break;
10416 case 2: code = BFD_RELOC_16; break;
10417 case 4: code = BFD_RELOC_32; break;
937149dd 10418#ifdef BFD64
3e73aa7c 10419 case 8: code = BFD_RELOC_64; break;
937149dd 10420#endif
93382f6d 10421 }
252b5132
RH		 10422 }
10423 break;
10424 }
252b5132 10425
d182319b
JB		 10426 if ((code == BFD_RELOC_32
10427 || code == BFD_RELOC_32_PCREL
10428 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10429 && GOT_symbol
10430 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10431 {
4fa24527 10432 if (!object_64bit)
d6ab8113
JB		 10433 code = BFD_RELOC_386_GOTPC;
10434 else
10435 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10436 }
7b81dfbb
AJ		 10437 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10438 && GOT_symbol
10439 && fixp->fx_addsy == GOT_symbol)
10440 {
10441 code = BFD_RELOC_X86_64_GOTPC64;
10442 }
252b5132
RH		 10443
10444 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10445 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10446 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10447
10448 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10449
3e73aa7c
JH		 10450 if (!use_rela_relocations)
10451 {
10452 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10453 vtable entry to be used in the relocation's section offset. */
10454 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10455 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10456#if defined (OBJ_COFF) && defined (TE_PE)
10457 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10458 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10459 else
10460#endif
c6682705 10461 rel->addend = 0;
3e73aa7c
JH		 10462 }
10463 /* Use the rela in 64bit mode. */
252b5132 10464 else
3e73aa7c 10465 {
862be3fb
L		 10466 if (disallow_64bit_reloc)
10467 switch (code)
10468 {
862be3fb
L		 10469 case BFD_RELOC_X86_64_DTPOFF64:
10470 case BFD_RELOC_X86_64_TPOFF64:
10471 case BFD_RELOC_64_PCREL:
10472 case BFD_RELOC_X86_64_GOTOFF64:
10473 case BFD_RELOC_X86_64_GOT64:
10474 case BFD_RELOC_X86_64_GOTPCREL64:
10475 case BFD_RELOC_X86_64_GOTPC64:
10476 case BFD_RELOC_X86_64_GOTPLT64:
10477 case BFD_RELOC_X86_64_PLTOFF64:
10478 as_bad_where (fixp->fx_file, fixp->fx_line,
10479 _("cannot represent relocation type %s in x32 mode"),
10480 bfd_get_reloc_code_name (code));
10481 break;
10482 default:
10483 break;
10484 }
10485
062cd5e7
AS		 10486 if (!fixp->fx_pcrel)
10487 rel->addend = fixp->fx_offset;
10488 else
10489 switch (code)
10490 {
10491 case BFD_RELOC_X86_64_PLT32:
c3320543 10492 case BFD_RELOC_X86_64_PLT32_BND:
062cd5e7
AS		 10493 case BFD_RELOC_X86_64_GOT32:
10494 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 10495 case BFD_RELOC_X86_64_TLSGD:
10496 case BFD_RELOC_X86_64_TLSLD:
10497 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10498 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10499 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10500 rel->addend = fixp->fx_offset - fixp->fx_size;
10501 break;
10502 default:
10503 rel->addend = (section->vma
10504 - fixp->fx_size
10505 + fixp->fx_addnumber
10506 + md_pcrel_from (fixp));
10507 break;
10508 }
3e73aa7c
JH		 10509 }
10510
252b5132
RH		 10511 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10512 if (rel->howto == NULL)
10513 {
10514 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10515 _("cannot represent relocation type %s"),
252b5132
RH		 10516 bfd_get_reloc_code_name (code));
10517 /* Set howto to a garbage value so that we can keep going. */
10518 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10519 gas_assert (rel->howto != NULL);
252b5132
RH		 10520 }
10521
10522 return rel;
10523}
10524
ee86248c 10525#include "tc-i386-intel.c"
54cfded0 10526
a60de03c
JB		 10527void
10528tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10529{
a60de03c
JB		 10530 int saved_naked_reg;
10531 char saved_register_dot;
54cfded0 10532
a60de03c
JB		 10533 saved_naked_reg = allow_naked_reg;
10534 allow_naked_reg = 1;
10535 saved_register_dot = register_chars['.'];
10536 register_chars['.'] = '.';
10537 allow_pseudo_reg = 1;
10538 expression_and_evaluate (exp);
10539 allow_pseudo_reg = 0;
10540 register_chars['.'] = saved_register_dot;
10541 allow_naked_reg = saved_naked_reg;
10542
e96d56a1 10543 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10544 {
a60de03c
JB		 10545 if ((addressT) exp->X_add_number < i386_regtab_size)
10546 {
10547 exp->X_op = O_constant;
10548 exp->X_add_number = i386_regtab[exp->X_add_number]
10549 .dw2_regnum[flag_code >> 1];
10550 }
10551 else
10552 exp->X_op = O_illegal;
54cfded0 10553 }
54cfded0
AM		 10554}
10555
10556void
10557tc_x86_frame_initial_instructions (void)
10558{
a60de03c
JB		 10559 static unsigned int sp_regno[2];
10560
10561 if (!sp_regno[flag_code >> 1])
10562 {
10563 char *saved_input = input_line_pointer;
10564 char sp[][4] = {"esp", "rsp"};
10565 expressionS exp;
a4447b93 10566
a60de03c
JB		 10567 input_line_pointer = sp[flag_code >> 1];
10568 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10569 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10570 sp_regno[flag_code >> 1] = exp.X_add_number;
10571 input_line_pointer = saved_input;
10572 }
a4447b93 10573
61ff971f
L		 10574 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10575 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10576}
d2b2c203 10577
d7921315
L		 10578int
10579x86_dwarf2_addr_size (void)
10580{
10581#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10582 if (x86_elf_abi == X86_64_X32_ABI)
10583 return 4;
10584#endif
10585 return bfd_arch_bits_per_address (stdoutput) / 8;
10586}
10587
d2b2c203
DJ		 10588int
10589i386_elf_section_type (const char *str, size_t len)
10590{
10591 if (flag_code == CODE_64BIT
10592 && len == sizeof ("unwind") - 1
10593 && strncmp (str, "unwind", 6) == 0)
10594 return SHT_X86_64_UNWIND;
10595
10596 return -1;
10597}
bb41ade5 10598
ad5fec3b
EB		 10599#ifdef TE_SOLARIS
10600void
10601i386_solaris_fix_up_eh_frame (segT sec)
10602{
10603 if (flag_code == CODE_64BIT)
10604 elf_section_type (sec) = SHT_X86_64_UNWIND;
10605}
10606#endif
10607
bb41ade5
AM		 10608#ifdef TE_PE
10609void
10610tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10611{
91d6fa6a 10612 expressionS exp;
bb41ade5 10613
91d6fa6a
NC		 10614 exp.X_op = O_secrel;
10615 exp.X_add_symbol = symbol;
10616 exp.X_add_number = 0;
10617 emit_expr (&exp, size);
bb41ade5
AM		 10618}
10619#endif
3b22753a
L		 10620
10621#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10622/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10623
01e1a5bc 10624bfd_vma
3b22753a
L		 10625x86_64_section_letter (int letter, char **ptr_msg)
10626{
10627 if (flag_code == CODE_64BIT)
10628 {
10629 if (letter == 'l')
10630 return SHF_X86_64_LARGE;
10631
8f3bae45 10632 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10633 }
3b22753a 10634 else
8f3bae45 10635 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10636 return -1;
10637}
10638
01e1a5bc 10639bfd_vma
3b22753a
L		 10640x86_64_section_word (char *str, size_t len)
10641{
8620418b 10642 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10643 return SHF_X86_64_LARGE;
10644
10645 return -1;
10646}
10647
10648static void
10649handle_large_common (int small ATTRIBUTE_UNUSED)
10650{
10651 if (flag_code != CODE_64BIT)
10652 {
10653 s_comm_internal (0, elf_common_parse);
10654 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10655 }
10656 else
10657 {
10658 static segT lbss_section;
10659 asection *saved_com_section_ptr = elf_com_section_ptr;
10660 asection *saved_bss_section = bss_section;
10661
10662 if (lbss_section == NULL)
10663 {
10664 flagword applicable;
10665 segT seg = now_seg;
10666 subsegT subseg = now_subseg;
10667
10668 /* The .lbss section is for local .largecomm symbols. */
10669 lbss_section = subseg_new (".lbss", 0);
10670 applicable = bfd_applicable_section_flags (stdoutput);
10671 bfd_set_section_flags (stdoutput, lbss_section,
10672 applicable & SEC_ALLOC);
10673 seg_info (lbss_section)->bss = 1;
10674
10675 subseg_set (seg, subseg);
10676 }
10677
10678 elf_com_section_ptr = &_bfd_elf_large_com_section;
10679 bss_section = lbss_section;
10680
10681 s_comm_internal (0, elf_common_parse);
10682
10683 elf_com_section_ptr = saved_com_section_ptr;
10684 bss_section = saved_bss_section;
10685 }
10686}
10687#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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