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x86: fix swapped operand handling for BNDMOV
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
219d1afa 2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d 68#define LOCK_PREFIX 5
4e9ac44a
L		 69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
6305a203
L		 84/* Intel Syntax. Use a non-ascii letter since since it never appears
85 in instructions. */
86#define LONG_DOUBLE_MNEM_SUFFIX '\1'
87
88#define END_OF_INSN '\0'
89
90/*
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
95 END.
96 */
97typedef struct
98{
d3ce72d0
NC		 99 const insn_template *start;
100 const insn_template *end;
6305a203
L		 101}
102templates;
103
104/* 386 operand encoding bytes: see 386 book for details of this. */
105typedef struct
106{
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
110}
111modrm_byte;
112
113/* x86-64 extension prefix. */
114typedef int rex_byte;
115
6305a203
L		 116/* 386 opcode byte to code indirect addressing. */
117typedef struct
118{
119 unsigned base;
120 unsigned index;
121 unsigned scale;
122}
123sib_byte;
124
6305a203
L		 125/* x86 arch names, types and features */
126typedef struct
127{
128 const char *name; /* arch name */
8a2c8fef 129 unsigned int len; /* arch string length */
6305a203
L		 130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 132 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 133}
134arch_entry;
135
293f5f65
L		 136/* Used to turn off indicated flags. */
137typedef struct
138{
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
142}
143noarch_entry;
144
78f12dd3 145static void update_code_flag (int, int);
e3bb37b5
L		 146static void set_code_flag (int);
147static void set_16bit_gcc_code_flag (int);
148static void set_intel_syntax (int);
1efbbeb4 149static void set_intel_mnemonic (int);
db51cc60 150static void set_allow_index_reg (int);
7bab8ab5 151static void set_check (int);
e3bb37b5 152static void set_cpu_arch (int);
6482c264 153#ifdef TE_PE
e3bb37b5 154static void pe_directive_secrel (int);
6482c264 155#endif
e3bb37b5
L		 156static void signed_cons (int);
157static char *output_invalid (int c);
ee86248c
JB		 158static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
159 const char *);
160static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
161 const char *);
a7619375 162static int i386_att_operand (char *);
e3bb37b5 163static int i386_intel_operand (char *, int);
ee86248c
JB		 164static int i386_intel_simplify (expressionS *);
165static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 166static const reg_entry *parse_register (char *, char **);
167static char *parse_insn (char *, char *);
168static char *parse_operands (char *, const char *);
169static void swap_operands (void);
4d456e3d 170static void swap_2_operands (int, int);
e3bb37b5
L		 171static void optimize_imm (void);
172static void optimize_disp (void);
83b16ac6 173static const insn_template *match_template (char);
e3bb37b5
L		 174static int check_string (void);
175static int process_suffix (void);
176static int check_byte_reg (void);
177static int check_long_reg (void);
178static int check_qword_reg (void);
179static int check_word_reg (void);
180static int finalize_imm (void);
181static int process_operands (void);
182static const seg_entry *build_modrm_byte (void);
183static void output_insn (void);
184static void output_imm (fragS *, offsetT);
185static void output_disp (fragS *, offsetT);
29b0f896 186#ifndef I386COFF
e3bb37b5 187static void s_bss (int);
252b5132 188#endif
17d4e2a2
L		 189#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190static void handle_large_common (int small ATTRIBUTE_UNUSED);
191#endif
252b5132 192
a847613f 193static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 194
43234a1e
L		 195/* This struct describes rounding control and SAE in the instruction. */
196struct RC_Operation
197{
198 enum rc_type
199 {
200 rne = 0,
201 rd,
202 ru,
203 rz,
204 saeonly
205 } type;
206 int operand;
207};
208
209static struct RC_Operation rc_op;
210
211/* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214struct Mask_Operation
215{
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
219 int operand;
220};
221
222static struct Mask_Operation mask_op;
223
224/* The struct describes broadcasting, applied to OPERAND. FACTOR is
225 broadcast factor. */
226struct Broadcast_Operation
227{
228 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
229 int type;
230
231 /* Index of broadcasted operand. */
232 int operand;
233};
234
235static struct Broadcast_Operation broadcast_op;
236
c0f3af97
L		 237/* VEX prefix. */
238typedef struct
239{
43234a1e
L		 240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
c0f3af97
L		 242 unsigned int length;
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
245} vex_prefix;
246
252b5132 247/* 'md_assemble ()' gathers together information and puts it into a
47926f60 248 i386_insn. */
252b5132 249
520dc8e8
AM		 250union i386_op
251 {
252 expressionS *disps;
253 expressionS *imms;
254 const reg_entry *regs;
255 };
256
a65babc9
L		 257enum i386_error
258 {
86e026a4 259 operand_size_mismatch,
a65babc9
L		 260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
264 bad_imm4,
a65babc9
L		 265 unsupported_with_intel_mnemonic,
266 unsupported_syntax,
6c30d220
L		 267 unsupported,
268 invalid_vsib_address,
7bab8ab5 269 invalid_vector_register_set,
43234a1e
L		 270 unsupported_vector_index_register,
271 unsupported_broadcast,
272 broadcast_not_on_src_operand,
273 broadcast_needed,
274 unsupported_masking,
275 mask_not_on_destination,
276 no_default_mask,
277 unsupported_rc_sae,
278 rc_sae_operand_not_last_imm,
279 invalid_register_operand,
a65babc9
L		 280 };
281
252b5132
RH		 282struct _i386_insn
283 {
47926f60 284 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 285 insn_template tm;
252b5132 286
7d5e4556
L		 287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
252b5132
RH		 289 char suffix;
290
47926f60 291 /* OPERANDS gives the number of given operands. */
252b5132
RH		 292 unsigned int operands;
293
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
47926f60 296 operands. */
252b5132
RH		 297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
298
299 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 300 use OP[i] for the corresponding operand. */
40fb9820 301 i386_operand_type types[MAX_OPERANDS];
252b5132 302
520dc8e8
AM		 303 /* Displacement expression, immediate expression, or register for each
304 operand. */
305 union i386_op op[MAX_OPERANDS];
252b5132 306
3e73aa7c
JH		 307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309#define Operand_PCrel 1
310
252b5132 311 /* Relocation type for operand */
f86103b7 312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 313
252b5132
RH		 314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
319
320 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 321 explicit segment overrides are given. */
ce8a8b2f 322 const seg_entry *seg[2];
252b5132 323
8325cc63
JB		 324 /* Copied first memory operand string, for re-checking. */
325 char *memop1_string;
326
252b5132
RH		 327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
331
332 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 333 addressing modes of this insn are encoded. */
252b5132 334 modrm_byte rm;
3e73aa7c 335 rex_byte rex;
43234a1e 336 rex_byte vrex;
252b5132 337 sib_byte sib;
c0f3af97 338 vex_prefix vex;
b6169b20 339
43234a1e
L		 340 /* Masking attributes. */
341 struct Mask_Operation *mask;
342
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
345
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
348
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
351
86fa6981
L		 352 /* Prefer load or store in encoding. */
353 enum
354 {
355 dir_encoding_default = 0,
356 dir_encoding_load,
357 dir_encoding_store
358 } dir_encoding;
891edac4 359
a501d77e
L		 360 /* Prefer 8bit or 32bit displacement in encoding. */
361 enum
362 {
363 disp_encoding_default = 0,
364 disp_encoding_8bit,
365 disp_encoding_32bit
366 } disp_encoding;
f8a5c266 367
6b6b6807
L		 368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding;
370
b6f8c7c4
L		 371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize;
373
86fa6981
L		 374 /* How to encode vector instructions. */
375 enum
376 {
377 vex_encoding_default = 0,
378 vex_encoding_vex2,
379 vex_encoding_vex3,
380 vex_encoding_evex
381 } vec_encoding;
382
d5de92cf
L		 383 /* REP prefix. */
384 const char *rep_prefix;
385
165de32a
L		 386 /* HLE prefix. */
387 const char *hle_prefix;
42164a71 388
7e8b059b
L		 389 /* Have BND prefix. */
390 const char *bnd_prefix;
391
04ef582a
L		 392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix;
394
891edac4 395 /* Error message. */
a65babc9 396 enum i386_error error;
252b5132
RH		 397 };
398
399typedef struct _i386_insn i386_insn;
400
43234a1e
L		 401/* Link RC type with corresponding string, that'll be looked for in
402 asm. */
403struct RC_name
404{
405 enum rc_type type;
406 const char *name;
407 unsigned int len;
408};
409
410static const struct RC_name RC_NamesTable[] =
411{
412 { rne, STRING_COMMA_LEN ("rn-sae") },
413 { rd, STRING_COMMA_LEN ("rd-sae") },
414 { ru, STRING_COMMA_LEN ("ru-sae") },
415 { rz, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly, STRING_COMMA_LEN ("sae") },
417};
418
252b5132
RH		 419/* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 421const char extra_symbol_chars[] = "*%-([{}"
252b5132 422#ifdef LEX_AT
32137342
NC		 423 "@"
424#endif
425#ifdef LEX_QM
426 "?"
252b5132 427#endif
32137342 428 ;
252b5132 429
29b0f896
AM		 430#if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 432 && !defined (TE_GNU) \
29b0f896 433 && !defined (TE_LINUX) \
8d63c93e
RM		 434 && !defined (TE_NACL) \
435 && !defined (TE_NETWARE) \
29b0f896 436 && !defined (TE_FreeBSD) \
5b806d27 437 && !defined (TE_DragonFly) \
29b0f896 438 && !defined (TE_NetBSD)))
252b5132 439/* This array holds the chars that always start a comment. If the
b3b91714
AM		 440 pre-processor is disabled, these aren't very useful. The option
441 --divide will remove '/' from this list. */
442const char *i386_comment_chars = "#/";
443#define SVR4_COMMENT_CHARS 1
252b5132 444#define PREFIX_SEPARATOR '\\'
252b5132 445
b3b91714
AM		 446#else
447const char *i386_comment_chars = "#";
448#define PREFIX_SEPARATOR '/'
449#endif
450
252b5132
RH		 451/* This array holds the chars that only start a comment at the beginning of
452 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 453 .line and .file directives will appear in the pre-processed output.
454 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 455 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 456 #NO_APP at the beginning of its output.
457 Also note that comments started like this one will always work if
252b5132 458 '/' isn't otherwise defined. */
b3b91714 459const char line_comment_chars[] = "#/";
252b5132 460
63a0b638 461const char line_separator_chars[] = ";";
252b5132 462
ce8a8b2f
AM		 463/* Chars that can be used to separate mant from exp in floating point
464 nums. */
252b5132
RH		 465const char EXP_CHARS[] = "eE";
466
ce8a8b2f
AM		 467/* Chars that mean this number is a floating point constant
468 As in 0f12.456
469 or 0d1.2345e12. */
252b5132
RH		 470const char FLT_CHARS[] = "fFdDxX";
471
ce8a8b2f 472/* Tables for lexical analysis. */
252b5132
RH		 473static char mnemonic_chars[256];
474static char register_chars[256];
475static char operand_chars[256];
476static char identifier_chars[256];
477static char digit_chars[256];
478
ce8a8b2f 479/* Lexical macros. */
252b5132
RH		 480#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
481#define is_operand_char(x) (operand_chars[(unsigned char) x])
482#define is_register_char(x) (register_chars[(unsigned char) x])
483#define is_space_char(x) ((x) == ' ')
484#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
485#define is_digit_char(x) (digit_chars[(unsigned char) x])
486
0234cb7c 487/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 488static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
489
490/* md_assemble() always leaves the strings it's passed unaltered. To
491 effect this we maintain a stack of saved characters that we've smashed
492 with '\0's (indicating end of strings for various sub-fields of the
47926f60 493 assembler instruction). */
252b5132 494static char save_stack[32];
ce8a8b2f 495static char *save_stack_p;
252b5132
RH		 496#define END_STRING_AND_SAVE(s) \
497 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
498#define RESTORE_END_STRING(s) \
499 do { *(s) = *--save_stack_p; } while (0)
500
47926f60 501/* The instruction we're assembling. */
252b5132
RH		 502static i386_insn i;
503
504/* Possible templates for current insn. */
505static const templates *current_templates;
506
31b2323c
L		 507/* Per instruction expressionS buffers: max displacements & immediates. */
508static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
509static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 510
47926f60 511/* Current operand we are working on. */
ee86248c 512static int this_operand = -1;
252b5132 513
3e73aa7c
JH		 514/* We support four different modes. FLAG_CODE variable is used to distinguish
515 these. */
516
517enum flag_code {
518 CODE_32BIT,
519 CODE_16BIT,
520 CODE_64BIT };
521
522static enum flag_code flag_code;
4fa24527 523static unsigned int object_64bit;
862be3fb 524static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 525static int use_rela_relocations = 0;
526
7af8ed2d
NC		 527#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
528 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
529 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
530
351f65ca
L		 531/* The ELF ABI to use. */
532enum x86_elf_abi
533{
534 I386_ABI,
7f56bc95
L		 535 X86_64_ABI,
536 X86_64_X32_ABI
351f65ca
L		 537};
538
539static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 540#endif
351f65ca 541
167ad85b
TG		 542#if defined (TE_PE) || defined (TE_PEP)
543/* Use big object file format. */
544static int use_big_obj = 0;
545#endif
546
8dcea932
L		 547#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
548/* 1 if generating code for a shared library. */
549static int shared = 0;
550#endif
551
47926f60
KH		 552/* 1 for intel syntax,
553 0 if att syntax. */
554static int intel_syntax = 0;
252b5132 555
e89c5eaa
L		 556/* 1 for Intel64 ISA,
557 0 if AMD64 ISA. */
558static int intel64;
559
1efbbeb4
L		 560/* 1 for intel mnemonic,
561 0 if att mnemonic. */
562static int intel_mnemonic = !SYSV386_COMPAT;
563
a60de03c
JB		 564/* 1 if pseudo registers are permitted. */
565static int allow_pseudo_reg = 0;
566
47926f60
KH		 567/* 1 if register prefix % not required. */
568static int allow_naked_reg = 0;
252b5132 569
33eaf5de 570/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 571 instructions supporting it, even if this prefix wasn't specified
572 explicitly. */
573static int add_bnd_prefix = 0;
574
ba104c83 575/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 576static int allow_index_reg = 0;
577
d022bddd
IT		 578/* 1 if the assembler should ignore LOCK prefix, even if it was
579 specified explicitly. */
580static int omit_lock_prefix = 0;
581
e4e00185
AS		 582/* 1 if the assembler should encode lfence, mfence, and sfence as
583 "lock addl $0, (%{re}sp)". */
584static int avoid_fence = 0;
585
0cb4071e
L		 586/* 1 if the assembler should generate relax relocations. */
587
588static int generate_relax_relocations
589 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
590
7bab8ab5 591static enum check_kind
daf50ae7 592 {
7bab8ab5
JB		 593 check_none = 0,
594 check_warning,
595 check_error
daf50ae7 596 }
7bab8ab5 597sse_check, operand_check = check_warning;
daf50ae7 598
b6f8c7c4
L		 599/* Optimization:
600 1. Clear the REX_W bit with register operand if possible.
601 2. Above plus use 128bit vector instruction to clear the full vector
602 register.
603 */
604static int optimize = 0;
605
606/* Optimization:
607 1. Clear the REX_W bit with register operand if possible.
608 2. Above plus use 128bit vector instruction to clear the full vector
609 register.
610 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
611 "testb $imm7,%r8".
612 */
613static int optimize_for_space = 0;
614
2ca3ace5
L		 615/* Register prefix used for error message. */
616static const char *register_prefix = "%";
617
47926f60
KH		 618/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
619 leave, push, and pop instructions so that gcc has the same stack
620 frame as in 32 bit mode. */
621static char stackop_size = '\0';
eecb386c 622
12b55ccc
L		 623/* Non-zero to optimize code alignment. */
624int optimize_align_code = 1;
625
47926f60
KH		 626/* Non-zero to quieten some warnings. */
627static int quiet_warnings = 0;
a38cf1db 628
47926f60
KH		 629/* CPU name. */
630static const char *cpu_arch_name = NULL;
6305a203 631static char *cpu_sub_arch_name = NULL;
a38cf1db 632
47926f60 633/* CPU feature flags. */
40fb9820
L		 634static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
635
ccc9c027
L		 636/* If we have selected a cpu we are generating instructions for. */
637static int cpu_arch_tune_set = 0;
638
9103f4f4 639/* Cpu we are generating instructions for. */
fbf3f584 640enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 641
642/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 643static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 644
ccc9c027 645/* CPU instruction set architecture used. */
fbf3f584 646enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 647
9103f4f4 648/* CPU feature flags of instruction set architecture used. */
fbf3f584 649i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 650
fddf5b5b
AM		 651/* If set, conditional jumps are not automatically promoted to handle
652 larger than a byte offset. */
653static unsigned int no_cond_jump_promotion = 0;
654
c0f3af97
L		 655/* Encode SSE instructions with VEX prefix. */
656static unsigned int sse2avx;
657
539f890d
L		 658/* Encode scalar AVX instructions with specific vector length. */
659static enum
660 {
661 vex128 = 0,
662 vex256
663 } avxscalar;
664
43234a1e
L		 665/* Encode scalar EVEX LIG instructions with specific vector length. */
666static enum
667 {
668 evexl128 = 0,
669 evexl256,
670 evexl512
671 } evexlig;
672
673/* Encode EVEX WIG instructions with specific evex.w. */
674static enum
675 {
676 evexw0 = 0,
677 evexw1
678 } evexwig;
679
d3d3c6db
IT		 680/* Value to encode in EVEX RC bits, for SAE-only instructions. */
681static enum rc_type evexrcig = rne;
682
29b0f896 683/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 684static symbolS *GOT_symbol;
29b0f896 685
a4447b93
RH		 686/* The dwarf2 return column, adjusted for 32 or 64 bit. */
687unsigned int x86_dwarf2_return_column;
688
689/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
690int x86_cie_data_alignment;
691
252b5132 692/* Interface to relax_segment.
fddf5b5b
AM		 693 There are 3 major relax states for 386 jump insns because the
694 different types of jumps add different sizes to frags when we're
695 figuring out what sort of jump to choose to reach a given label. */
252b5132 696
47926f60 697/* Types. */
93c2a809
AM		 698#define UNCOND_JUMP 0
699#define COND_JUMP 1
700#define COND_JUMP86 2
fddf5b5b 701
47926f60 702/* Sizes. */
252b5132
RH		 703#define CODE16 1
704#define SMALL 0
29b0f896 705#define SMALL16 (SMALL | CODE16)
252b5132 706#define BIG 2
29b0f896 707#define BIG16 (BIG | CODE16)
252b5132
RH		 708
709#ifndef INLINE
710#ifdef __GNUC__
711#define INLINE __inline__
712#else
713#define INLINE
714#endif
715#endif
716
fddf5b5b
AM		 717#define ENCODE_RELAX_STATE(type, size) \
718 ((relax_substateT) (((type) << 2) | (size)))
719#define TYPE_FROM_RELAX_STATE(s) \
720 ((s) >> 2)
721#define DISP_SIZE_FROM_RELAX_STATE(s) \
722 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 723
724/* This table is used by relax_frag to promote short jumps to long
725 ones where necessary. SMALL (short) jumps may be promoted to BIG
726 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
727 don't allow a short jump in a 32 bit code segment to be promoted to
728 a 16 bit offset jump because it's slower (requires data size
729 prefix), and doesn't work, unless the destination is in the bottom
730 64k of the code segment (The top 16 bits of eip are zeroed). */
731
732const relax_typeS md_relax_table[] =
733{
24eab124
AM		 734 /* The fields are:
735 1) most positive reach of this state,
736 2) most negative reach of this state,
93c2a809 737 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 738 4) which index into the table to try if we can't fit into this one. */
252b5132 739
fddf5b5b 740 /* UNCOND_JUMP states. */
93c2a809
AM		 741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
742 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
743 /* dword jmp adds 4 bytes to frag:
744 0 extra opcode bytes, 4 displacement bytes. */
252b5132 745 {0, 0, 4, 0},
93c2a809
AM		 746 /* word jmp adds 2 byte2 to frag:
747 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 748 {0, 0, 2, 0},
749
93c2a809
AM		 750 /* COND_JUMP states. */
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
752 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
753 /* dword conditionals adds 5 bytes to frag:
754 1 extra opcode byte, 4 displacement bytes. */
755 {0, 0, 5, 0},
fddf5b5b 756 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 757 1 extra opcode byte, 2 displacement bytes. */
758 {0, 0, 3, 0},
759
760 /* COND_JUMP86 states. */
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
762 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
763 /* dword conditionals adds 5 bytes to frag:
764 1 extra opcode byte, 4 displacement bytes. */
765 {0, 0, 5, 0},
766 /* word conditionals add 4 bytes to frag:
767 1 displacement byte and a 3 byte long branch insn. */
768 {0, 0, 4, 0}
252b5132
RH		 769};
770
9103f4f4
L		 771static const arch_entry cpu_arch[] =
772{
89507696
JB		 773 /* Do not replace the first two entries - i386_target_format()
774 relies on them being there in this order. */
8a2c8fef 775 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 776 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 777 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 778 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 779 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 780 CPU_NONE_FLAGS, 0 },
8a2c8fef 781 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 782 CPU_I186_FLAGS, 0 },
8a2c8fef 783 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 784 CPU_I286_FLAGS, 0 },
8a2c8fef 785 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 786 CPU_I386_FLAGS, 0 },
8a2c8fef 787 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 788 CPU_I486_FLAGS, 0 },
8a2c8fef 789 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 790 CPU_I586_FLAGS, 0 },
8a2c8fef 791 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 792 CPU_I686_FLAGS, 0 },
8a2c8fef 793 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 794 CPU_I586_FLAGS, 0 },
8a2c8fef 795 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 796 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 797 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 798 CPU_P2_FLAGS, 0 },
8a2c8fef 799 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 800 CPU_P3_FLAGS, 0 },
8a2c8fef 801 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 802 CPU_P4_FLAGS, 0 },
8a2c8fef 803 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 804 CPU_CORE_FLAGS, 0 },
8a2c8fef 805 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 806 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 807 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 808 CPU_CORE_FLAGS, 1 },
8a2c8fef 809 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 810 CPU_CORE_FLAGS, 0 },
8a2c8fef 811 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 812 CPU_CORE2_FLAGS, 1 },
8a2c8fef 813 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 814 CPU_CORE2_FLAGS, 0 },
8a2c8fef 815 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 816 CPU_COREI7_FLAGS, 0 },
8a2c8fef 817 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 818 CPU_L1OM_FLAGS, 0 },
7a9068fe 819 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 820 CPU_K1OM_FLAGS, 0 },
81486035 821 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 822 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 823 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 824 CPU_K6_FLAGS, 0 },
8a2c8fef 825 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 826 CPU_K6_2_FLAGS, 0 },
8a2c8fef 827 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 828 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 829 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 830 CPU_K8_FLAGS, 1 },
8a2c8fef 831 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 832 CPU_K8_FLAGS, 0 },
8a2c8fef 833 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 834 CPU_K8_FLAGS, 0 },
8a2c8fef 835 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 836 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 837 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 838 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 839 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 840 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 841 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 842 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 843 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 844 CPU_BDVER4_FLAGS, 0 },
029f3522 845 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 846 CPU_ZNVER1_FLAGS, 0 },
7b458c12 847 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 848 CPU_BTVER1_FLAGS, 0 },
7b458c12 849 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 850 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 852 CPU_8087_FLAGS, 0 },
8a2c8fef 853 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 854 CPU_287_FLAGS, 0 },
8a2c8fef 855 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 856 CPU_387_FLAGS, 0 },
1848e567
L		 857 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
858 CPU_687_FLAGS, 0 },
8a2c8fef 859 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 860 CPU_MMX_FLAGS, 0 },
8a2c8fef 861 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 862 CPU_SSE_FLAGS, 0 },
8a2c8fef 863 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 864 CPU_SSE2_FLAGS, 0 },
8a2c8fef 865 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 866 CPU_SSE3_FLAGS, 0 },
8a2c8fef 867 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 868 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 869 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 870 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 871 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 872 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 873 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 874 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 875 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 876 CPU_AVX_FLAGS, 0 },
6c30d220 877 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 878 CPU_AVX2_FLAGS, 0 },
43234a1e 879 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 880 CPU_AVX512F_FLAGS, 0 },
43234a1e 881 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 882 CPU_AVX512CD_FLAGS, 0 },
43234a1e 883 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 884 CPU_AVX512ER_FLAGS, 0 },
43234a1e 885 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 886 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 887 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 888 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 889 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 890 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 891 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 892 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 893 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 894 CPU_VMX_FLAGS, 0 },
8729a6f6 895 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 896 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 897 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 898 CPU_SMX_FLAGS, 0 },
8a2c8fef 899 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 900 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 901 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 902 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 903 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 904 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 905 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 906 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 907 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 908 CPU_AES_FLAGS, 0 },
8a2c8fef 909 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 910 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 911 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 912 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 913 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 914 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 915 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 916 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 917 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 918 CPU_F16C_FLAGS, 0 },
6c30d220 919 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 920 CPU_BMI2_FLAGS, 0 },
8a2c8fef 921 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 922 CPU_FMA_FLAGS, 0 },
8a2c8fef 923 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 924 CPU_FMA4_FLAGS, 0 },
8a2c8fef 925 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 926 CPU_XOP_FLAGS, 0 },
8a2c8fef 927 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 928 CPU_LWP_FLAGS, 0 },
8a2c8fef 929 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 930 CPU_MOVBE_FLAGS, 0 },
60aa667e 931 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 932 CPU_CX16_FLAGS, 0 },
8a2c8fef 933 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 934 CPU_EPT_FLAGS, 0 },
6c30d220 935 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 936 CPU_LZCNT_FLAGS, 0 },
42164a71 937 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 938 CPU_HLE_FLAGS, 0 },
42164a71 939 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 940 CPU_RTM_FLAGS, 0 },
6c30d220 941 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 942 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 943 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 944 CPU_CLFLUSH_FLAGS, 0 },
22109423 945 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 946 CPU_NOP_FLAGS, 0 },
8a2c8fef 947 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 948 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 949 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 950 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 951 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 952 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 953 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 954 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 955 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 956 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 957 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 958 CPU_SVME_FLAGS, 1 },
8a2c8fef 959 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 960 CPU_SVME_FLAGS, 0 },
8a2c8fef 961 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 962 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 963 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 964 CPU_ABM_FLAGS, 0 },
87973e9f 965 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 966 CPU_BMI_FLAGS, 0 },
2a2a0f38 967 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 968 CPU_TBM_FLAGS, 0 },
e2e1fcde 969 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 970 CPU_ADX_FLAGS, 0 },
e2e1fcde 971 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 972 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 973 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 974 CPU_PRFCHW_FLAGS, 0 },
5c111e37 975 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 976 CPU_SMAP_FLAGS, 0 },
7e8b059b 977 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 978 CPU_MPX_FLAGS, 0 },
a0046408 979 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 980 CPU_SHA_FLAGS, 0 },
963f3586 981 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 982 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 983 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 984 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 985 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 986 CPU_SE1_FLAGS, 0 },
c5e7287a 987 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 988 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 989 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 990 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 991 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 992 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 993 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
994 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 995 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
996 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 997 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
998 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
53467f57
IT		 999 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1000 CPU_AVX512_VBMI2_FLAGS, 0 },
8cfcb765
IT		 1001 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1002 CPU_AVX512_VNNI_FLAGS, 0 },
ee6872be
IT		 1003 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1004 CPU_AVX512_BITALG_FLAGS, 0 },
029f3522 1005 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 1006 CPU_CLZERO_FLAGS, 0 },
9916071f 1007 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 1008 CPU_MWAITX_FLAGS, 0 },
8eab4136 1009 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 1010 CPU_OSPKE_FLAGS, 0 },
8bc52696 1011 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 1012 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 1013 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1014 CPU_PTWRITE_FLAGS, 0 },
d777820b
IT		 1015 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1016 CPU_IBT_FLAGS, 0 },
1017 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1018 CPU_SHSTK_FLAGS, 0 },
48521003
IT		 1019 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1020 CPU_GFNI_FLAGS, 0 },
8dcf1fad
IT		 1021 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1022 CPU_VAES_FLAGS, 0 },
ff1982d5
IT		 1023 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1024 CPU_VPCLMULQDQ_FLAGS, 0 },
3233d7d0
IT		 1025 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1026 CPU_WBNOINVD_FLAGS, 0 },
be3a8dca
IT		 1027 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1028 CPU_PCONFIG_FLAGS, 0 },
293f5f65
L		 1029};
1030
1031static const noarch_entry cpu_noarch[] =
1032{
1033 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 1034 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1035 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1036 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 1037 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1038 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1039 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1040 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1041 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1042 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1043 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1044 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1045 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1046 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1047 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1048 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1049 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1050 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1051 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1052 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1053 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1054 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1056 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1057 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1058 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
53467f57 1059 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
8cfcb765 1060 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
ee6872be 1061 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
d777820b
IT		 1062 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1063 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
e413e4e9
AM		 1064};
1065
704209c0 1066#ifdef I386COFF
a6c24e68
NC		 1067/* Like s_lcomm_internal in gas/read.c but the alignment string
1068 is allowed to be optional. */
1069
1070static symbolS *
1071pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1072{
1073 addressT align = 0;
1074
1075 SKIP_WHITESPACE ();
1076
7ab9ffdd 1077 if (needs_align
a6c24e68
NC		 1078 && *input_line_pointer == ',')
1079 {
1080 align = parse_align (needs_align - 1);
7ab9ffdd 1081
a6c24e68
NC		 1082 if (align == (addressT) -1)
1083 return NULL;
1084 }
1085 else
1086 {
1087 if (size >= 8)
1088 align = 3;
1089 else if (size >= 4)
1090 align = 2;
1091 else if (size >= 2)
1092 align = 1;
1093 else
1094 align = 0;
1095 }
1096
1097 bss_alloc (symbolP, size, align);
1098 return symbolP;
1099}
1100
704209c0 1101static void
a6c24e68
NC		 1102pe_lcomm (int needs_align)
1103{
1104 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1105}
704209c0 1106#endif
a6c24e68 1107
29b0f896
AM		 1108const pseudo_typeS md_pseudo_table[] =
1109{
1110#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1111 {"align", s_align_bytes, 0},
1112#else
1113 {"align", s_align_ptwo, 0},
1114#endif
1115 {"arch", set_cpu_arch, 0},
1116#ifndef I386COFF
1117 {"bss", s_bss, 0},
a6c24e68
NC		 1118#else
1119 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1120#endif
1121 {"ffloat", float_cons, 'f'},
1122 {"dfloat", float_cons, 'd'},
1123 {"tfloat", float_cons, 'x'},
1124 {"value", cons, 2},
d182319b 1125 {"slong", signed_cons, 4},
29b0f896
AM		 1126 {"noopt", s_ignore, 0},
1127 {"optim", s_ignore, 0},
1128 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1129 {"code16", set_code_flag, CODE_16BIT},
1130 {"code32", set_code_flag, CODE_32BIT},
da5f19a2 1131#ifdef BFD64
29b0f896 1132 {"code64", set_code_flag, CODE_64BIT},
da5f19a2 1133#endif
29b0f896
AM		 1134 {"intel_syntax", set_intel_syntax, 1},
1135 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1136 {"intel_mnemonic", set_intel_mnemonic, 1},
1137 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1138 {"allow_index_reg", set_allow_index_reg, 1},
1139 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1140 {"sse_check", set_check, 0},
1141 {"operand_check", set_check, 1},
3b22753a
L		 1142#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1143 {"largecomm", handle_large_common, 0},
07a53e5c 1144#else
68d20676 1145 {"file", dwarf2_directive_file, 0},
07a53e5c
RH		 1146 {"loc", dwarf2_directive_loc, 0},
1147 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1148#endif
6482c264
NC		 1149#ifdef TE_PE
1150 {"secrel32", pe_directive_secrel, 0},
1151#endif
29b0f896
AM		 1152 {0, 0, 0}
1153};
1154
1155/* For interface with expression (). */
1156extern char *input_line_pointer;
1157
1158/* Hash table for instruction mnemonic lookup. */
1159static struct hash_control *op_hash;
1160
1161/* Hash table for register lookup. */
1162static struct hash_control *reg_hash;
1163\f
ce8a8b2f
AM		 1164 /* Various efficient no-op patterns for aligning code labels.
1165 Note: Don't try to assemble the instructions in the comments.
1166 0L and 0w are not legal. */
62a02d25
L		 1167static const unsigned char f32_1[] =
1168 {0x90}; /* nop */
1169static const unsigned char f32_2[] =
1170 {0x66,0x90}; /* xchg %ax,%ax */
1171static const unsigned char f32_3[] =
1172 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1173static const unsigned char f32_4[] =
1174 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
62a02d25
L		 1175static const unsigned char f32_6[] =
1176 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1177static const unsigned char f32_7[] =
1178 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
62a02d25 1179static const unsigned char f16_3[] =
3ae729d5 1180 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
62a02d25 1181static const unsigned char f16_4[] =
3ae729d5
L		 1182 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1183static const unsigned char jump_disp8[] =
1184 {0xeb}; /* jmp disp8 */
1185static const unsigned char jump32_disp32[] =
1186 {0xe9}; /* jmp disp32 */
1187static const unsigned char jump16_disp32[] =
1188 {0x66,0xe9}; /* jmp disp32 */
62a02d25
L		 1189/* 32-bit NOPs patterns. */
1190static const unsigned char *const f32_patt[] = {
3ae729d5 1191 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
62a02d25
L		 1192};
1193/* 16-bit NOPs patterns. */
1194static const unsigned char *const f16_patt[] = {
3ae729d5 1195 f32_1, f32_2, f16_3, f16_4
62a02d25
L		 1196};
1197/* nopl (%[re]ax) */
1198static const unsigned char alt_3[] =
1199 {0x0f,0x1f,0x00};
1200/* nopl 0(%[re]ax) */
1201static const unsigned char alt_4[] =
1202 {0x0f,0x1f,0x40,0x00};
1203/* nopl 0(%[re]ax,%[re]ax,1) */
1204static const unsigned char alt_5[] =
1205 {0x0f,0x1f,0x44,0x00,0x00};
1206/* nopw 0(%[re]ax,%[re]ax,1) */
1207static const unsigned char alt_6[] =
1208 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1209/* nopl 0L(%[re]ax) */
1210static const unsigned char alt_7[] =
1211 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1212/* nopl 0L(%[re]ax,%[re]ax,1) */
1213static const unsigned char alt_8[] =
1214 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1215/* nopw 0L(%[re]ax,%[re]ax,1) */
1216static const unsigned char alt_9[] =
1217 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1218/* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1219static const unsigned char alt_10[] =
1220 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
3ae729d5
L		 1221/* data16 nopw %cs:0L(%eax,%eax,1) */
1222static const unsigned char alt_11[] =
1223 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
62a02d25
L		 1224/* 32-bit and 64-bit NOPs patterns. */
1225static const unsigned char *const alt_patt[] = {
1226 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
3ae729d5 1227 alt_9, alt_10, alt_11
62a02d25
L		 1228};
1229
1230/* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1231 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1232
1233static void
1234i386_output_nops (char *where, const unsigned char *const *patt,
1235 int count, int max_single_nop_size)
1236
1237{
3ae729d5
L		 1238 /* Place the longer NOP first. */
1239 int last;
1240 int offset;
1241 const unsigned char *nops = patt[max_single_nop_size - 1];
1242
1243 /* Use the smaller one if the requsted one isn't available. */
1244 if (nops == NULL)
62a02d25 1245 {
3ae729d5
L		 1246 max_single_nop_size--;
1247 nops = patt[max_single_nop_size - 1];
62a02d25
L		 1248 }
1249
3ae729d5
L		 1250 last = count % max_single_nop_size;
1251
1252 count -= last;
1253 for (offset = 0; offset < count; offset += max_single_nop_size)
1254 memcpy (where + offset, nops, max_single_nop_size);
1255
1256 if (last)
1257 {
1258 nops = patt[last - 1];
1259 if (nops == NULL)
1260 {
1261 /* Use the smaller one plus one-byte NOP if the needed one
1262 isn't available. */
1263 last--;
1264 nops = patt[last - 1];
1265 memcpy (where + offset, nops, last);
1266 where[offset + last] = *patt[0];
1267 }
1268 else
1269 memcpy (where + offset, nops, last);
1270 }
62a02d25
L		 1271}
1272
3ae729d5
L		 1273static INLINE int
1274fits_in_imm7 (offsetT num)
1275{
1276 return (num & 0x7f) == num;
1277}
1278
1279static INLINE int
1280fits_in_imm31 (offsetT num)
1281{
1282 return (num & 0x7fffffff) == num;
1283}
62a02d25
L		 1284
1285/* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1286 single NOP instruction LIMIT. */
1287
1288void
3ae729d5 1289i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
62a02d25 1290{
3ae729d5 1291 const unsigned char *const *patt = NULL;
62a02d25 1292 int max_single_nop_size;
3ae729d5
L		 1293 /* Maximum number of NOPs before switching to jump over NOPs. */
1294 int max_number_of_nops;
62a02d25 1295
3ae729d5 1296 switch (fragP->fr_type)
62a02d25 1297 {
3ae729d5
L		 1298 case rs_fill_nop:
1299 case rs_align_code:
1300 break;
1301 default:
62a02d25
L		 1302 return;
1303 }
1304
ccc9c027
L		 1305 /* We need to decide which NOP sequence to use for 32bit and
1306 64bit. When -mtune= is used:
4eed87de 1307
76bc74dc
L		 1308 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1309 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1310 2. For the rest, alt_patt will be used.
1311
1312 When -mtune= isn't used, alt_patt will be used if
22109423 1313 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1314 be used.
ccc9c027
L		 1315
1316 When -march= or .arch is used, we can't use anything beyond
1317 cpu_arch_isa_flags. */
1318
1319 if (flag_code == CODE_16BIT)
1320 {
3ae729d5
L		 1321 patt = f16_patt;
1322 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1323 /* Limit number of NOPs to 2 in 16-bit mode. */
1324 max_number_of_nops = 2;
252b5132 1325 }
33fef721 1326 else
ccc9c027 1327 {
fbf3f584 1328 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1329 {
1330 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1331 switch (cpu_arch_tune)
1332 {
1333 case PROCESSOR_UNKNOWN:
1334 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1335 optimize with nops. */
1336 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1337 patt = alt_patt;
ccc9c027
L		 1338 else
1339 patt = f32_patt;
1340 break;
ccc9c027
L		 1341 case PROCESSOR_PENTIUM4:
1342 case PROCESSOR_NOCONA:
ef05d495 1343 case PROCESSOR_CORE:
76bc74dc 1344 case PROCESSOR_CORE2:
bd5295b2 1345 case PROCESSOR_COREI7:
3632d14b 1346 case PROCESSOR_L1OM:
7a9068fe 1347 case PROCESSOR_K1OM:
76bc74dc 1348 case PROCESSOR_GENERIC64:
ccc9c027
L		 1349 case PROCESSOR_K6:
1350 case PROCESSOR_ATHLON:
1351 case PROCESSOR_K8:
4eed87de 1352 case PROCESSOR_AMDFAM10:
8aedb9fe 1353 case PROCESSOR_BD:
029f3522 1354 case PROCESSOR_ZNVER:
7b458c12 1355 case PROCESSOR_BT:
80b8656c 1356 patt = alt_patt;
ccc9c027 1357 break;
76bc74dc 1358 case PROCESSOR_I386:
ccc9c027
L		 1359 case PROCESSOR_I486:
1360 case PROCESSOR_PENTIUM:
2dde1948 1361 case PROCESSOR_PENTIUMPRO:
81486035 1362 case PROCESSOR_IAMCU:
ccc9c027
L		 1363 case PROCESSOR_GENERIC32:
1364 patt = f32_patt;
1365 break;
4eed87de 1366 }
ccc9c027
L		 1367 }
1368 else
1369 {
fbf3f584 1370 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1371 {
1372 case PROCESSOR_UNKNOWN:
e6a14101 1373 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1374 PROCESSOR_UNKNOWN. */
1375 abort ();
1376 break;
1377
76bc74dc 1378 case PROCESSOR_I386:
ccc9c027
L		 1379 case PROCESSOR_I486:
1380 case PROCESSOR_PENTIUM:
81486035 1381 case PROCESSOR_IAMCU:
ccc9c027
L		 1382 case PROCESSOR_K6:
1383 case PROCESSOR_ATHLON:
1384 case PROCESSOR_K8:
4eed87de 1385 case PROCESSOR_AMDFAM10:
8aedb9fe 1386 case PROCESSOR_BD:
029f3522 1387 case PROCESSOR_ZNVER:
7b458c12 1388 case PROCESSOR_BT:
ccc9c027
L		 1389 case PROCESSOR_GENERIC32:
1390 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1391 with nops. */
1392 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1393 patt = alt_patt;
ccc9c027
L		 1394 else
1395 patt = f32_patt;
1396 break;
76bc74dc
L		 1397 case PROCESSOR_PENTIUMPRO:
1398 case PROCESSOR_PENTIUM4:
1399 case PROCESSOR_NOCONA:
1400 case PROCESSOR_CORE:
ef05d495 1401 case PROCESSOR_CORE2:
bd5295b2 1402 case PROCESSOR_COREI7:
3632d14b 1403 case PROCESSOR_L1OM:
7a9068fe 1404 case PROCESSOR_K1OM:
22109423 1405 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1406 patt = alt_patt;
ccc9c027
L		 1407 else
1408 patt = f32_patt;
1409 break;
1410 case PROCESSOR_GENERIC64:
80b8656c 1411 patt = alt_patt;
ccc9c027 1412 break;
4eed87de 1413 }
ccc9c027
L		 1414 }
1415
76bc74dc
L		 1416 if (patt == f32_patt)
1417 {
3ae729d5
L		 1418 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1419 /* Limit number of NOPs to 2 for older processors. */
1420 max_number_of_nops = 2;
76bc74dc
L		 1421 }
1422 else
1423 {
3ae729d5
L		 1424 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1425 /* Limit number of NOPs to 7 for newer processors. */
1426 max_number_of_nops = 7;
1427 }
1428 }
1429
1430 if (limit == 0)
1431 limit = max_single_nop_size;
1432
1433 if (fragP->fr_type == rs_fill_nop)
1434 {
1435 /* Output NOPs for .nop directive. */
1436 if (limit > max_single_nop_size)
1437 {
1438 as_bad_where (fragP->fr_file, fragP->fr_line,
1439 _("invalid single nop size: %d "
1440 "(expect within [0, %d])"),
1441 limit, max_single_nop_size);
1442 return;
1443 }
1444 }
1445 else
1446 fragP->fr_var = count;
1447
1448 if ((count / max_single_nop_size) > max_number_of_nops)
1449 {
1450 /* Generate jump over NOPs. */
1451 offsetT disp = count - 2;
1452 if (fits_in_imm7 (disp))
1453 {
1454 /* Use "jmp disp8" if possible. */
1455 count = disp;
1456 where[0] = jump_disp8[0];
1457 where[1] = count;
1458 where += 2;
1459 }
1460 else
1461 {
1462 unsigned int size_of_jump;
1463
1464 if (flag_code == CODE_16BIT)
1465 {
1466 where[0] = jump16_disp32[0];
1467 where[1] = jump16_disp32[1];
1468 size_of_jump = 2;
1469 }
1470 else
1471 {
1472 where[0] = jump32_disp32[0];
1473 size_of_jump = 1;
1474 }
1475
1476 count -= size_of_jump + 4;
1477 if (!fits_in_imm31 (count))
1478 {
1479 as_bad_where (fragP->fr_file, fragP->fr_line,
1480 _("jump over nop padding out of range"));
1481 return;
1482 }
1483
1484 md_number_to_chars (where + size_of_jump, count, 4);
1485 where += size_of_jump + 4;
76bc74dc 1486 }
ccc9c027 1487 }
3ae729d5
L		 1488
1489 /* Generate multiple NOPs. */
1490 i386_output_nops (where, patt, count, limit);
252b5132
RH		 1491}
1492
c6fb90c8 1493static INLINE int
0dfbf9d7 1494operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1495{
0dfbf9d7 1496 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1497 {
1498 case 3:
0dfbf9d7 1499 if (x->array[2])
c6fb90c8 1500 return 0;
1a0670f3 1501 /* Fall through. */
c6fb90c8 1502 case 2:
0dfbf9d7 1503 if (x->array[1])
c6fb90c8 1504 return 0;
1a0670f3 1505 /* Fall through. */
c6fb90c8 1506 case 1:
0dfbf9d7 1507 return !x->array[0];
c6fb90c8
L		 1508 default:
1509 abort ();
1510 }
40fb9820
L		 1511}
1512
c6fb90c8 1513static INLINE void
0dfbf9d7 1514operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1515{
0dfbf9d7 1516 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1517 {
1518 case 3:
0dfbf9d7 1519 x->array[2] = v;
1a0670f3 1520 /* Fall through. */
c6fb90c8 1521 case 2:
0dfbf9d7 1522 x->array[1] = v;
1a0670f3 1523 /* Fall through. */
c6fb90c8 1524 case 1:
0dfbf9d7 1525 x->array[0] = v;
1a0670f3 1526 /* Fall through. */
c6fb90c8
L		 1527 break;
1528 default:
1529 abort ();
1530 }
1531}
40fb9820 1532
c6fb90c8 1533static INLINE int
0dfbf9d7
L		 1534operand_type_equal (const union i386_operand_type *x,
1535 const union i386_operand_type *y)
c6fb90c8 1536{
0dfbf9d7 1537 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1538 {
1539 case 3:
0dfbf9d7 1540 if (x->array[2] != y->array[2])
c6fb90c8 1541 return 0;
1a0670f3 1542 /* Fall through. */
c6fb90c8 1543 case 2:
0dfbf9d7 1544 if (x->array[1] != y->array[1])
c6fb90c8 1545 return 0;
1a0670f3 1546 /* Fall through. */
c6fb90c8 1547 case 1:
0dfbf9d7 1548 return x->array[0] == y->array[0];
c6fb90c8
L		 1549 break;
1550 default:
1551 abort ();
1552 }
1553}
40fb9820 1554
0dfbf9d7
L		 1555static INLINE int
1556cpu_flags_all_zero (const union i386_cpu_flags *x)
1557{
1558 switch (ARRAY_SIZE(x->array))
1559 {
53467f57
IT		 1560 case 4:
1561 if (x->array[3])
1562 return 0;
1563 /* Fall through. */
0dfbf9d7
L		 1564 case 3:
1565 if (x->array[2])
1566 return 0;
1a0670f3 1567 /* Fall through. */
0dfbf9d7
L		 1568 case 2:
1569 if (x->array[1])
1570 return 0;
1a0670f3 1571 /* Fall through. */
0dfbf9d7
L		 1572 case 1:
1573 return !x->array[0];
1574 default:
1575 abort ();
1576 }
1577}
1578
0dfbf9d7
L		 1579static INLINE int
1580cpu_flags_equal (const union i386_cpu_flags *x,
1581 const union i386_cpu_flags *y)
1582{
1583 switch (ARRAY_SIZE(x->array))
1584 {
53467f57
IT		 1585 case 4:
1586 if (x->array[3] != y->array[3])
1587 return 0;
1588 /* Fall through. */
0dfbf9d7
L		 1589 case 3:
1590 if (x->array[2] != y->array[2])
1591 return 0;
1a0670f3 1592 /* Fall through. */
0dfbf9d7
L		 1593 case 2:
1594 if (x->array[1] != y->array[1])
1595 return 0;
1a0670f3 1596 /* Fall through. */
0dfbf9d7
L		 1597 case 1:
1598 return x->array[0] == y->array[0];
1599 break;
1600 default:
1601 abort ();
1602 }
1603}
c6fb90c8
L		 1604
1605static INLINE int
1606cpu_flags_check_cpu64 (i386_cpu_flags f)
1607{
1608 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1609 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1610}
1611
c6fb90c8
L		 1612static INLINE i386_cpu_flags
1613cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1614{
c6fb90c8
L		 1615 switch (ARRAY_SIZE (x.array))
1616 {
53467f57
IT		 1617 case 4:
1618 x.array [3] &= y.array [3];
1619 /* Fall through. */
c6fb90c8
L		 1620 case 3:
1621 x.array [2] &= y.array [2];
1a0670f3 1622 /* Fall through. */
c6fb90c8
L		 1623 case 2:
1624 x.array [1] &= y.array [1];
1a0670f3 1625 /* Fall through. */
c6fb90c8
L		 1626 case 1:
1627 x.array [0] &= y.array [0];
1628 break;
1629 default:
1630 abort ();
1631 }
1632 return x;
1633}
40fb9820 1634
c6fb90c8
L		 1635static INLINE i386_cpu_flags
1636cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1637{
c6fb90c8 1638 switch (ARRAY_SIZE (x.array))
40fb9820 1639 {
53467f57
IT		 1640 case 4:
1641 x.array [3] |= y.array [3];
1642 /* Fall through. */
c6fb90c8
L		 1643 case 3:
1644 x.array [2] |= y.array [2];
1a0670f3 1645 /* Fall through. */
c6fb90c8
L		 1646 case 2:
1647 x.array [1] |= y.array [1];
1a0670f3 1648 /* Fall through. */
c6fb90c8
L		 1649 case 1:
1650 x.array [0] |= y.array [0];
40fb9820
L		 1651 break;
1652 default:
1653 abort ();
1654 }
40fb9820
L		 1655 return x;
1656}
1657
309d3373
JB		 1658static INLINE i386_cpu_flags
1659cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1660{
1661 switch (ARRAY_SIZE (x.array))
1662 {
53467f57
IT		 1663 case 4:
1664 x.array [3] &= ~y.array [3];
1665 /* Fall through. */
309d3373
JB		 1666 case 3:
1667 x.array [2] &= ~y.array [2];
1a0670f3 1668 /* Fall through. */
309d3373
JB		 1669 case 2:
1670 x.array [1] &= ~y.array [1];
1a0670f3 1671 /* Fall through. */
309d3373
JB		 1672 case 1:
1673 x.array [0] &= ~y.array [0];
1674 break;
1675 default:
1676 abort ();
1677 }
1678 return x;
1679}
1680
c0f3af97
L		 1681#define CPU_FLAGS_ARCH_MATCH 0x1
1682#define CPU_FLAGS_64BIT_MATCH 0x2
1683
c0f3af97 1684#define CPU_FLAGS_PERFECT_MATCH \
db12e14e 1685 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
c0f3af97
L		 1686
1687/* Return CPU flags match bits. */
3629bb00 1688
40fb9820 1689static int
d3ce72d0 1690cpu_flags_match (const insn_template *t)
40fb9820 1691{
c0f3af97
L		 1692 i386_cpu_flags x = t->cpu_flags;
1693 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1694
1695 x.bitfield.cpu64 = 0;
1696 x.bitfield.cpuno64 = 0;
1697
0dfbf9d7 1698 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1699 {
1700 /* This instruction is available on all archs. */
db12e14e 1701 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1702 }
3629bb00
L		 1703 else
1704 {
c0f3af97 1705 /* This instruction is available only on some archs. */
3629bb00
L		 1706 i386_cpu_flags cpu = cpu_arch_flags;
1707
ab592e75
JB		 1708 /* AVX512VL is no standalone feature - match it and then strip it. */
1709 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1710 return match;
1711 x.bitfield.cpuavx512vl = 0;
1712
3629bb00 1713 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1714 if (!cpu_flags_all_zero (&cpu))
1715 {
a5ff0eb2
L		 1716 if (x.bitfield.cpuavx)
1717 {
929f69fa 1718 /* We need to check a few extra flags with AVX. */
b9d49817
JB		 1719 if (cpu.bitfield.cpuavx
1720 && (!t->opcode_modifier.sse2avx || sse2avx)
1721 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
929f69fa 1722 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
b9d49817
JB		 1723 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1724 match |= CPU_FLAGS_ARCH_MATCH;
a5ff0eb2 1725 }
929f69fa
JB		 1726 else if (x.bitfield.cpuavx512f)
1727 {
1728 /* We need to check a few extra flags with AVX512F. */
1729 if (cpu.bitfield.cpuavx512f
1730 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1731 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1732 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1733 match |= CPU_FLAGS_ARCH_MATCH;
1734 }
a5ff0eb2 1735 else
db12e14e 1736 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1737 }
3629bb00 1738 }
c0f3af97 1739 return match;
40fb9820
L		 1740}
1741
c6fb90c8
L		 1742static INLINE i386_operand_type
1743operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1744{
c6fb90c8
L		 1745 switch (ARRAY_SIZE (x.array))
1746 {
1747 case 3:
1748 x.array [2] &= y.array [2];
1a0670f3 1749 /* Fall through. */
c6fb90c8
L		 1750 case 2:
1751 x.array [1] &= y.array [1];
1a0670f3 1752 /* Fall through. */
c6fb90c8
L		 1753 case 1:
1754 x.array [0] &= y.array [0];
1755 break;
1756 default:
1757 abort ();
1758 }
1759 return x;
40fb9820
L		 1760}
1761
73053c1f
JB		 1762static INLINE i386_operand_type
1763operand_type_and_not (i386_operand_type x, i386_operand_type y)
1764{
1765 switch (ARRAY_SIZE (x.array))
1766 {
1767 case 3:
1768 x.array [2] &= ~y.array [2];
1769 /* Fall through. */
1770 case 2:
1771 x.array [1] &= ~y.array [1];
1772 /* Fall through. */
1773 case 1:
1774 x.array [0] &= ~y.array [0];
1775 break;
1776 default:
1777 abort ();
1778 }
1779 return x;
1780}
1781
c6fb90c8
L		 1782static INLINE i386_operand_type
1783operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1784{
c6fb90c8 1785 switch (ARRAY_SIZE (x.array))
40fb9820 1786 {
c6fb90c8
L		 1787 case 3:
1788 x.array [2] |= y.array [2];
1a0670f3 1789 /* Fall through. */
c6fb90c8
L		 1790 case 2:
1791 x.array [1] |= y.array [1];
1a0670f3 1792 /* Fall through. */
c6fb90c8
L		 1793 case 1:
1794 x.array [0] |= y.array [0];
40fb9820
L		 1795 break;
1796 default:
1797 abort ();
1798 }
c6fb90c8
L		 1799 return x;
1800}
40fb9820 1801
c6fb90c8
L		 1802static INLINE i386_operand_type
1803operand_type_xor (i386_operand_type x, i386_operand_type y)
1804{
1805 switch (ARRAY_SIZE (x.array))
1806 {
1807 case 3:
1808 x.array [2] ^= y.array [2];
1a0670f3 1809 /* Fall through. */
c6fb90c8
L		 1810 case 2:
1811 x.array [1] ^= y.array [1];
1a0670f3 1812 /* Fall through. */
c6fb90c8
L		 1813 case 1:
1814 x.array [0] ^= y.array [0];
1815 break;
1816 default:
1817 abort ();
1818 }
40fb9820
L		 1819 return x;
1820}
1821
1822static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1823static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1824static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1825static const i386_operand_type inoutportreg
1826 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1827static const i386_operand_type reg16_inoutportreg
1828 = OPERAND_TYPE_REG16_INOUTPORTREG;
1829static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1830static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1831static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1832static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1833static const i386_operand_type anydisp
1834 = OPERAND_TYPE_ANYDISP;
40fb9820 1835static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
43234a1e 1836static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1837static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1838static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1839static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1840static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1841static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1842static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1843static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1844static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1845static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1846static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1847
1848enum operand_type
1849{
1850 reg,
40fb9820
L		 1851 imm,
1852 disp,
1853 anymem
1854};
1855
c6fb90c8 1856static INLINE int
40fb9820
L		 1857operand_type_check (i386_operand_type t, enum operand_type c)
1858{
1859 switch (c)
1860 {
1861 case reg:
dc821c5f 1862 return t.bitfield.reg;
40fb9820 1863
40fb9820
L		 1864 case imm:
1865 return (t.bitfield.imm8
1866 || t.bitfield.imm8s
1867 || t.bitfield.imm16
1868 || t.bitfield.imm32
1869 || t.bitfield.imm32s
1870 || t.bitfield.imm64);
1871
1872 case disp:
1873 return (t.bitfield.disp8
1874 || t.bitfield.disp16
1875 || t.bitfield.disp32
1876 || t.bitfield.disp32s
1877 || t.bitfield.disp64);
1878
1879 case anymem:
1880 return (t.bitfield.disp8
1881 || t.bitfield.disp16
1882 || t.bitfield.disp32
1883 || t.bitfield.disp32s
1884 || t.bitfield.disp64
1885 || t.bitfield.baseindex);
1886
1887 default:
1888 abort ();
1889 }
2cfe26b6
AM		 1890
1891 return 0;
40fb9820
L		 1892}
1893
ca0d63fe 1894/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
5c07affc
L		 1895 operand J for instruction template T. */
1896
1897static INLINE int
d3ce72d0 1898match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1899{
1900 return !((i.types[j].bitfield.byte
1901 && !t->operand_types[j].bitfield.byte)
1902 || (i.types[j].bitfield.word
1903 && !t->operand_types[j].bitfield.word)
1904 || (i.types[j].bitfield.dword
1905 && !t->operand_types[j].bitfield.dword)
1906 || (i.types[j].bitfield.qword
ca0d63fe
JB		 1907 && !t->operand_types[j].bitfield.qword)
1908 || (i.types[j].bitfield.tbyte
1909 && !t->operand_types[j].bitfield.tbyte));
5c07affc
L		 1910}
1911
1b54b8d7
JB		 1912/* Return 1 if there is no conflict in SIMD register on
1913 operand J for instruction template T. */
1914
1915static INLINE int
1916match_simd_size (const insn_template *t, unsigned int j)
1917{
1918 return !((i.types[j].bitfield.xmmword
1919 && !t->operand_types[j].bitfield.xmmword)
1920 || (i.types[j].bitfield.ymmword
1921 && !t->operand_types[j].bitfield.ymmword)
1922 || (i.types[j].bitfield.zmmword
1923 && !t->operand_types[j].bitfield.zmmword));
1924}
1925
5c07affc
L		 1926/* Return 1 if there is no conflict in any size on operand J for
1927 instruction template T. */
1928
1929static INLINE int
d3ce72d0 1930match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1931{
1932 return (match_reg_size (t, j)
1933 && !((i.types[j].bitfield.unspecified
af508cb9 1934 && !i.broadcast
5c07affc
L		 1935 && !t->operand_types[j].bitfield.unspecified)
1936 || (i.types[j].bitfield.fword
1937 && !t->operand_types[j].bitfield.fword)
1b54b8d7
JB		 1938 /* For scalar opcode templates to allow register and memory
1939 operands at the same time, some special casing is needed
d6793fa1
JB		 1940 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1941 down-conversion vpmov*. */
1b54b8d7
JB		 1942 || ((t->operand_types[j].bitfield.regsimd
1943 && !t->opcode_modifier.broadcast
d6793fa1
JB		 1944 && (t->operand_types[j].bitfield.byte
1945 || t->operand_types[j].bitfield.word
1946 || t->operand_types[j].bitfield.dword
1b54b8d7
JB		 1947 || t->operand_types[j].bitfield.qword))
1948 ? (i.types[j].bitfield.xmmword
1949 || i.types[j].bitfield.ymmword
1950 || i.types[j].bitfield.zmmword)
1951 : !match_simd_size(t, j))));
5c07affc
L		 1952}
1953
1954/* Return 1 if there is no size conflict on any operands for
1955 instruction template T. */
1956
1957static INLINE int
d3ce72d0 1958operand_size_match (const insn_template *t)
5c07affc
L		 1959{
1960 unsigned int j;
1961 int match = 1;
1962
1963 /* Don't check jump instructions. */
1964 if (t->opcode_modifier.jump
1965 || t->opcode_modifier.jumpbyte
1966 || t->opcode_modifier.jumpdword
1967 || t->opcode_modifier.jumpintersegment)
1968 return match;
1969
1970 /* Check memory and accumulator operand size. */
1971 for (j = 0; j < i.operands; j++)
1972 {
1b54b8d7
JB		 1973 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1974 && t->operand_types[j].bitfield.anysize)
5c07affc
L		 1975 continue;
1976
1b54b8d7 1977 if (t->operand_types[j].bitfield.reg
dc821c5f 1978 && !match_reg_size (t, j))
5c07affc
L		 1979 {
1980 match = 0;
1981 break;
1982 }
1983
1b54b8d7
JB		 1984 if (t->operand_types[j].bitfield.regsimd
1985 && !match_simd_size (t, j))
1986 {
1987 match = 0;
1988 break;
1989 }
1990
1991 if (t->operand_types[j].bitfield.acc
1992 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1993 {
1994 match = 0;
1995 break;
1996 }
1997
5c07affc
L		 1998 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1999 {
2000 match = 0;
2001 break;
2002 }
2003 }
2004
891edac4 2005 if (match)
5c07affc 2006 return match;
38e314eb 2007 else if (!t->opcode_modifier.d)
891edac4
L		 2008 {
2009mismatch:
86e026a4 2010 i.error = operand_size_mismatch;
891edac4
L		 2011 return 0;
2012 }
5c07affc
L		 2013
2014 /* Check reverse. */
9c2799c2 2015 gas_assert (i.operands == 2);
5c07affc
L		 2016
2017 match = 1;
2018 for (j = 0; j < 2; j++)
2019 {
dc821c5f
JB		 2020 if ((t->operand_types[j].bitfield.reg
2021 || t->operand_types[j].bitfield.acc)
5c07affc 2022 && !match_reg_size (t, j ? 0 : 1))
891edac4 2023 goto mismatch;
5c07affc
L		 2024
2025 if (i.types[j].bitfield.mem
2026 && !match_mem_size (t, j ? 0 : 1))
891edac4 2027 goto mismatch;
5c07affc
L		 2028 }
2029
2030 return match;
2031}
2032
c6fb90c8 2033static INLINE int
40fb9820
L		 2034operand_type_match (i386_operand_type overlap,
2035 i386_operand_type given)
2036{
2037 i386_operand_type temp = overlap;
2038
2039 temp.bitfield.jumpabsolute = 0;
7d5e4556 2040 temp.bitfield.unspecified = 0;
5c07affc
L		 2041 temp.bitfield.byte = 0;
2042 temp.bitfield.word = 0;
2043 temp.bitfield.dword = 0;
2044 temp.bitfield.fword = 0;
2045 temp.bitfield.qword = 0;
2046 temp.bitfield.tbyte = 0;
2047 temp.bitfield.xmmword = 0;
c0f3af97 2048 temp.bitfield.ymmword = 0;
43234a1e 2049 temp.bitfield.zmmword = 0;
0dfbf9d7 2050 if (operand_type_all_zero (&temp))
891edac4 2051 goto mismatch;
40fb9820 2052
891edac4
L		 2053 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2054 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2055 return 1;
2056
2057mismatch:
a65babc9 2058 i.error = operand_type_mismatch;
891edac4 2059 return 0;
40fb9820
L		 2060}
2061
7d5e4556 2062/* If given types g0 and g1 are registers they must be of the same type
10c17abd
JB		 2063 unless the expected operand type register overlap is null.
2064 Memory operand size of certain SIMD instructions is also being checked
2065 here. */
40fb9820 2066
c6fb90c8 2067static INLINE int
dc821c5f 2068operand_type_register_match (i386_operand_type g0,
40fb9820 2069 i386_operand_type t0,
40fb9820
L		 2070 i386_operand_type g1,
2071 i386_operand_type t1)
2072{
10c17abd
JB		 2073 if (!g0.bitfield.reg
2074 && !g0.bitfield.regsimd
2075 && (!operand_type_check (g0, anymem)
2076 || g0.bitfield.unspecified
2077 || !t0.bitfield.regsimd))
40fb9820
L		 2078 return 1;
2079
10c17abd
JB		 2080 if (!g1.bitfield.reg
2081 && !g1.bitfield.regsimd
2082 && (!operand_type_check (g1, anymem)
2083 || g1.bitfield.unspecified
2084 || !t1.bitfield.regsimd))
40fb9820
L		 2085 return 1;
2086
dc821c5f
JB		 2087 if (g0.bitfield.byte == g1.bitfield.byte
2088 && g0.bitfield.word == g1.bitfield.word
2089 && g0.bitfield.dword == g1.bitfield.dword
10c17abd
JB		 2090 && g0.bitfield.qword == g1.bitfield.qword
2091 && g0.bitfield.xmmword == g1.bitfield.xmmword
2092 && g0.bitfield.ymmword == g1.bitfield.ymmword
2093 && g0.bitfield.zmmword == g1.bitfield.zmmword)
40fb9820
L		 2094 return 1;
2095
dc821c5f
JB		 2096 if (!(t0.bitfield.byte & t1.bitfield.byte)
2097 && !(t0.bitfield.word & t1.bitfield.word)
2098 && !(t0.bitfield.dword & t1.bitfield.dword)
10c17abd
JB		 2099 && !(t0.bitfield.qword & t1.bitfield.qword)
2100 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2101 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2102 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
891edac4
L		 2103 return 1;
2104
a65babc9 2105 i.error = register_type_mismatch;
891edac4
L		 2106
2107 return 0;
40fb9820
L		 2108}
2109
4c692bc7
JB		 2110static INLINE unsigned int
2111register_number (const reg_entry *r)
2112{
2113 unsigned int nr = r->reg_num;
2114
2115 if (r->reg_flags & RegRex)
2116 nr += 8;
2117
200cbe0f
L		 2118 if (r->reg_flags & RegVRex)
2119 nr += 16;
2120
4c692bc7
JB		 2121 return nr;
2122}
2123
252b5132 2124static INLINE unsigned int
40fb9820 2125mode_from_disp_size (i386_operand_type t)
252b5132 2126{
b5014f7a 2127 if (t.bitfield.disp8)
40fb9820
L		 2128 return 1;
2129 else if (t.bitfield.disp16
2130 || t.bitfield.disp32
2131 || t.bitfield.disp32s)
2132 return 2;
2133 else
2134 return 0;
252b5132
RH		 2135}
2136
2137static INLINE int
65879393 2138fits_in_signed_byte (addressT num)
252b5132 2139{
65879393 2140 return num + 0x80 <= 0xff;
47926f60 2141}
252b5132
RH		 2142
2143static INLINE int
65879393 2144fits_in_unsigned_byte (addressT num)
252b5132 2145{
65879393 2146 return num <= 0xff;
47926f60 2147}
252b5132
RH		 2148
2149static INLINE int
65879393 2150fits_in_unsigned_word (addressT num)
252b5132 2151{
65879393 2152 return num <= 0xffff;
47926f60 2153}
252b5132
RH		 2154
2155static INLINE int
65879393 2156fits_in_signed_word (addressT num)
252b5132 2157{
65879393 2158 return num + 0x8000 <= 0xffff;
47926f60 2159}
2a962e6d 2160
3e73aa7c 2161static INLINE int
65879393 2162fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2163{
2164#ifndef BFD64
2165 return 1;
2166#else
65879393 2167 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2168#endif
2169} /* fits_in_signed_long() */
2a962e6d 2170
3e73aa7c 2171static INLINE int
65879393 2172fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2173{
2174#ifndef BFD64
2175 return 1;
2176#else
65879393 2177 return num <= 0xffffffff;
3e73aa7c
JH		 2178#endif
2179} /* fits_in_unsigned_long() */
252b5132 2180
43234a1e 2181static INLINE int
b5014f7a 2182fits_in_disp8 (offsetT num)
43234a1e
L		 2183{
2184 int shift = i.memshift;
2185 unsigned int mask;
2186
2187 if (shift == -1)
2188 abort ();
2189
2190 mask = (1 << shift) - 1;
2191
2192 /* Return 0 if NUM isn't properly aligned. */
2193 if ((num & mask))
2194 return 0;
2195
2196 /* Check if NUM will fit in 8bit after shift. */
2197 return fits_in_signed_byte (num >> shift);
2198}
2199
a683cc34
SP		 2200static INLINE int
2201fits_in_imm4 (offsetT num)
2202{
2203 return (num & 0xf) == num;
2204}
2205
40fb9820 2206static i386_operand_type
e3bb37b5 2207smallest_imm_type (offsetT num)
252b5132 2208{
40fb9820 2209 i386_operand_type t;
7ab9ffdd 2210
0dfbf9d7 2211 operand_type_set (&t, 0);
40fb9820
L		 2212 t.bitfield.imm64 = 1;
2213
2214 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2215 {
2216 /* This code is disabled on the 486 because all the Imm1 forms
2217 in the opcode table are slower on the i486. They're the
2218 versions with the implicitly specified single-position
2219 displacement, which has another syntax if you really want to
2220 use that form. */
40fb9820
L		 2221 t.bitfield.imm1 = 1;
2222 t.bitfield.imm8 = 1;
2223 t.bitfield.imm8s = 1;
2224 t.bitfield.imm16 = 1;
2225 t.bitfield.imm32 = 1;
2226 t.bitfield.imm32s = 1;
2227 }
2228 else if (fits_in_signed_byte (num))
2229 {
2230 t.bitfield.imm8 = 1;
2231 t.bitfield.imm8s = 1;
2232 t.bitfield.imm16 = 1;
2233 t.bitfield.imm32 = 1;
2234 t.bitfield.imm32s = 1;
2235 }
2236 else if (fits_in_unsigned_byte (num))
2237 {
2238 t.bitfield.imm8 = 1;
2239 t.bitfield.imm16 = 1;
2240 t.bitfield.imm32 = 1;
2241 t.bitfield.imm32s = 1;
2242 }
2243 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2244 {
2245 t.bitfield.imm16 = 1;
2246 t.bitfield.imm32 = 1;
2247 t.bitfield.imm32s = 1;
2248 }
2249 else if (fits_in_signed_long (num))
2250 {
2251 t.bitfield.imm32 = 1;
2252 t.bitfield.imm32s = 1;
2253 }
2254 else if (fits_in_unsigned_long (num))
2255 t.bitfield.imm32 = 1;
2256
2257 return t;
47926f60 2258}
252b5132 2259
847f7ad4 2260static offsetT
e3bb37b5 2261offset_in_range (offsetT val, int size)
847f7ad4 2262{
508866be 2263 addressT mask;
ba2adb93 2264
847f7ad4
AM		 2265 switch (size)
2266 {
508866be
L		 2267 case 1: mask = ((addressT) 1 << 8) - 1; break;
2268 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2269 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2270#ifdef BFD64
2271 case 8: mask = ((addressT) 2 << 63) - 1; break;
2272#endif
47926f60 2273 default: abort ();
847f7ad4
AM		 2274 }
2275
9de868bf
L		 2276#ifdef BFD64
2277 /* If BFD64, sign extend val for 32bit address mode. */
2278 if (flag_code != CODE_64BIT
2279 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2280 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2281 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2282#endif
ba2adb93 2283
47926f60 2284 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2285 {
2286 char buf1[40], buf2[40];
2287
2288 sprint_value (buf1, val);
2289 sprint_value (buf2, val & mask);
2290 as_warn (_("%s shortened to %s"), buf1, buf2);
2291 }
2292 return val & mask;
2293}
2294
c32fa91d
L		 2295enum PREFIX_GROUP
2296{
2297 PREFIX_EXIST = 0,
2298 PREFIX_LOCK,
2299 PREFIX_REP,
04ef582a 2300 PREFIX_DS,
c32fa91d
L		 2301 PREFIX_OTHER
2302};
2303
2304/* Returns
2305 a. PREFIX_EXIST if attempting to add a prefix where one from the
2306 same class already exists.
2307 b. PREFIX_LOCK if lock prefix is added.
2308 c. PREFIX_REP if rep/repne prefix is added.
04ef582a
L		 2309 d. PREFIX_DS if ds prefix is added.
2310 e. PREFIX_OTHER if other prefix is added.
c32fa91d
L		 2311 */
2312
2313static enum PREFIX_GROUP
e3bb37b5 2314add_prefix (unsigned int prefix)
252b5132 2315{
c32fa91d 2316 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2317 unsigned int q;
252b5132 2318
29b0f896
AM		 2319 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2320 && flag_code == CODE_64BIT)
b1905489 2321 {
161a04f6
L		 2322 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2323 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2324 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2325 ret = PREFIX_EXIST;
b1905489
JB		 2326 q = REX_PREFIX;
2327 }
3e73aa7c 2328 else
b1905489
JB		 2329 {
2330 switch (prefix)
2331 {
2332 default:
2333 abort ();
2334
b1905489 2335 case DS_PREFIX_OPCODE:
04ef582a
L		 2336 ret = PREFIX_DS;
2337 /* Fall through. */
2338 case CS_PREFIX_OPCODE:
b1905489
JB		 2339 case ES_PREFIX_OPCODE:
2340 case FS_PREFIX_OPCODE:
2341 case GS_PREFIX_OPCODE:
2342 case SS_PREFIX_OPCODE:
2343 q = SEG_PREFIX;
2344 break;
2345
2346 case REPNE_PREFIX_OPCODE:
2347 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2348 q = REP_PREFIX;
2349 ret = PREFIX_REP;
2350 break;
2351
b1905489 2352 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2353 q = LOCK_PREFIX;
2354 ret = PREFIX_LOCK;
b1905489
JB		 2355 break;
2356
2357 case FWAIT_OPCODE:
2358 q = WAIT_PREFIX;
2359 break;
2360
2361 case ADDR_PREFIX_OPCODE:
2362 q = ADDR_PREFIX;
2363 break;
2364
2365 case DATA_PREFIX_OPCODE:
2366 q = DATA_PREFIX;
2367 break;
2368 }
2369 if (i.prefix[q] != 0)
c32fa91d 2370 ret = PREFIX_EXIST;
b1905489 2371 }
252b5132 2372
b1905489 2373 if (ret)
252b5132 2374 {
b1905489
JB		 2375 if (!i.prefix[q])
2376 ++i.prefixes;
2377 i.prefix[q] |= prefix;
252b5132 2378 }
b1905489
JB		 2379 else
2380 as_bad (_("same type of prefix used twice"));
252b5132 2381
252b5132
RH		 2382 return ret;
2383}
2384
2385static void
78f12dd3 2386update_code_flag (int value, int check)
eecb386c 2387{
78f12dd3
L		 2388 PRINTF_LIKE ((*as_error));
2389
1e9cc1c2 2390 flag_code = (enum flag_code) value;
40fb9820
L		 2391 if (flag_code == CODE_64BIT)
2392 {
2393 cpu_arch_flags.bitfield.cpu64 = 1;
2394 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2395 }
2396 else
2397 {
2398 cpu_arch_flags.bitfield.cpu64 = 0;
2399 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2400 }
2401 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2402 {
78f12dd3
L		 2403 if (check)
2404 as_error = as_fatal;
2405 else
2406 as_error = as_bad;
2407 (*as_error) (_("64bit mode not supported on `%s'."),
2408 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2409 }
40fb9820 2410 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2411 {
78f12dd3
L		 2412 if (check)
2413 as_error = as_fatal;
2414 else
2415 as_error = as_bad;
2416 (*as_error) (_("32bit mode not supported on `%s'."),
2417 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2418 }
eecb386c
AM		 2419 stackop_size = '\0';
2420}
2421
78f12dd3
L		 2422static void
2423set_code_flag (int value)
2424{
2425 update_code_flag (value, 0);
2426}
2427
eecb386c 2428static void
e3bb37b5 2429set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2430{
1e9cc1c2 2431 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2432 if (flag_code != CODE_16BIT)
2433 abort ();
2434 cpu_arch_flags.bitfield.cpu64 = 0;
2435 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2436 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2437}
2438
2439static void
e3bb37b5 2440set_intel_syntax (int syntax_flag)
252b5132
RH		 2441{
2442 /* Find out if register prefixing is specified. */
2443 int ask_naked_reg = 0;
2444
2445 SKIP_WHITESPACE ();
29b0f896 2446 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2447 {
d02603dc
NC		 2448 char *string;
2449 int e = get_symbol_name (&string);
252b5132 2450
47926f60 2451 if (strcmp (string, "prefix") == 0)
252b5132 2452 ask_naked_reg = 1;
47926f60 2453 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2454 ask_naked_reg = -1;
2455 else
d0b47220 2456 as_bad (_("bad argument to syntax directive."));
d02603dc 2457 (void) restore_line_pointer (e);
252b5132
RH		 2458 }
2459 demand_empty_rest_of_line ();
c3332e24 2460
252b5132
RH		 2461 intel_syntax = syntax_flag;
2462
2463 if (ask_naked_reg == 0)
f86103b7
AM		 2464 allow_naked_reg = (intel_syntax
2465 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2466 else
2467 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2468
ee86248c 2469 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2470
e4a3b5a4 2471 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2472 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2473 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2474}
2475
1efbbeb4
L		 2476static void
2477set_intel_mnemonic (int mnemonic_flag)
2478{
e1d4d893 2479 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2480}
2481
db51cc60
L		 2482static void
2483set_allow_index_reg (int flag)
2484{
2485 allow_index_reg = flag;
2486}
2487
cb19c032 2488static void
7bab8ab5 2489set_check (int what)
cb19c032 2490{
7bab8ab5
JB		 2491 enum check_kind *kind;
2492 const char *str;
2493
2494 if (what)
2495 {
2496 kind = &operand_check;
2497 str = "operand";
2498 }
2499 else
2500 {
2501 kind = &sse_check;
2502 str = "sse";
2503 }
2504
cb19c032
L		 2505 SKIP_WHITESPACE ();
2506
2507 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2508 {
d02603dc
NC		 2509 char *string;
2510 int e = get_symbol_name (&string);
cb19c032
L		 2511
2512 if (strcmp (string, "none") == 0)
7bab8ab5 2513 *kind = check_none;
cb19c032 2514 else if (strcmp (string, "warning") == 0)
7bab8ab5 2515 *kind = check_warning;
cb19c032 2516 else if (strcmp (string, "error") == 0)
7bab8ab5 2517 *kind = check_error;
cb19c032 2518 else
7bab8ab5 2519 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2520 (void) restore_line_pointer (e);
cb19c032
L		 2521 }
2522 else
7bab8ab5 2523 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2524
2525 demand_empty_rest_of_line ();
2526}
2527
8a9036a4
L		 2528static void
2529check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2530 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2531{
2532#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2533 static const char *arch;
2534
2535 /* Intel LIOM is only supported on ELF. */
2536 if (!IS_ELF)
2537 return;
2538
2539 if (!arch)
2540 {
2541 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2542 use default_arch. */
2543 arch = cpu_arch_name;
2544 if (!arch)
2545 arch = default_arch;
2546 }
2547
81486035
L		 2548 /* If we are targeting Intel MCU, we must enable it. */
2549 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2550 || new_flag.bitfield.cpuiamcu)
2551 return;
2552
3632d14b 2553 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2554 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2555 || new_flag.bitfield.cpul1om)
8a9036a4 2556 return;
76ba9986 2557
7a9068fe
L		 2558 /* If we are targeting Intel K1OM, we must enable it. */
2559 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2560 || new_flag.bitfield.cpuk1om)
2561 return;
2562
8a9036a4
L		 2563 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2564#endif
2565}
2566
e413e4e9 2567static void
e3bb37b5 2568set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2569{
47926f60 2570 SKIP_WHITESPACE ();
e413e4e9 2571
29b0f896 2572 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2573 {
d02603dc
NC		 2574 char *string;
2575 int e = get_symbol_name (&string);
91d6fa6a 2576 unsigned int j;
40fb9820 2577 i386_cpu_flags flags;
e413e4e9 2578
91d6fa6a 2579 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2580 {
91d6fa6a 2581 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2582 {
91d6fa6a 2583 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2584
5c6af06e
JB		 2585 if (*string != '.')
2586 {
91d6fa6a 2587 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2588 cpu_sub_arch_name = NULL;
91d6fa6a 2589 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2590 if (flag_code == CODE_64BIT)
2591 {
2592 cpu_arch_flags.bitfield.cpu64 = 1;
2593 cpu_arch_flags.bitfield.cpuno64 = 0;
2594 }
2595 else
2596 {
2597 cpu_arch_flags.bitfield.cpu64 = 0;
2598 cpu_arch_flags.bitfield.cpuno64 = 1;
2599 }
91d6fa6a
NC		 2600 cpu_arch_isa = cpu_arch[j].type;
2601 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2602 if (!cpu_arch_tune_set)
2603 {
2604 cpu_arch_tune = cpu_arch_isa;
2605 cpu_arch_tune_flags = cpu_arch_isa_flags;
2606 }
5c6af06e
JB		 2607 break;
2608 }
40fb9820 2609
293f5f65
L		 2610 flags = cpu_flags_or (cpu_arch_flags,
2611 cpu_arch[j].flags);
81486035 2612
5b64d091 2613 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2614 {
6305a203
L		 2615 if (cpu_sub_arch_name)
2616 {
2617 char *name = cpu_sub_arch_name;
2618 cpu_sub_arch_name = concat (name,
91d6fa6a 2619 cpu_arch[j].name,
1bf57e9f 2620 (const char *) NULL);
6305a203
L		 2621 free (name);
2622 }
2623 else
91d6fa6a 2624 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2625 cpu_arch_flags = flags;
a586129e 2626 cpu_arch_isa_flags = flags;
5c6af06e 2627 }
0089dace
L		 2628 else
2629 cpu_arch_isa_flags
2630 = cpu_flags_or (cpu_arch_isa_flags,
2631 cpu_arch[j].flags);
d02603dc 2632 (void) restore_line_pointer (e);
5c6af06e
JB		 2633 demand_empty_rest_of_line ();
2634 return;
e413e4e9
AM		 2635 }
2636 }
293f5f65
L		 2637
2638 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2639 {
33eaf5de 2640 /* Disable an ISA extension. */
293f5f65
L		 2641 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2642 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2643 {
2644 flags = cpu_flags_and_not (cpu_arch_flags,
2645 cpu_noarch[j].flags);
2646 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2647 {
2648 if (cpu_sub_arch_name)
2649 {
2650 char *name = cpu_sub_arch_name;
2651 cpu_sub_arch_name = concat (name, string,
2652 (const char *) NULL);
2653 free (name);
2654 }
2655 else
2656 cpu_sub_arch_name = xstrdup (string);
2657 cpu_arch_flags = flags;
2658 cpu_arch_isa_flags = flags;
2659 }
2660 (void) restore_line_pointer (e);
2661 demand_empty_rest_of_line ();
2662 return;
2663 }
2664
2665 j = ARRAY_SIZE (cpu_arch);
2666 }
2667
91d6fa6a 2668 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2669 as_bad (_("no such architecture: `%s'"), string);
2670
2671 *input_line_pointer = e;
2672 }
2673 else
2674 as_bad (_("missing cpu architecture"));
2675
fddf5b5b
AM		 2676 no_cond_jump_promotion = 0;
2677 if (*input_line_pointer == ','
29b0f896 2678 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2679 {
d02603dc
NC		 2680 char *string;
2681 char e;
2682
2683 ++input_line_pointer;
2684 e = get_symbol_name (&string);
fddf5b5b
AM		 2685
2686 if (strcmp (string, "nojumps") == 0)
2687 no_cond_jump_promotion = 1;
2688 else if (strcmp (string, "jumps") == 0)
2689 ;
2690 else
2691 as_bad (_("no such architecture modifier: `%s'"), string);
2692
d02603dc 2693 (void) restore_line_pointer (e);
fddf5b5b
AM		 2694 }
2695
e413e4e9
AM		 2696 demand_empty_rest_of_line ();
2697}
2698
8a9036a4
L		 2699enum bfd_architecture
2700i386_arch (void)
2701{
3632d14b 2702 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2703 {
2704 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2705 || flag_code != CODE_64BIT)
2706 as_fatal (_("Intel L1OM is 64bit ELF only"));
2707 return bfd_arch_l1om;
2708 }
7a9068fe
L		 2709 else if (cpu_arch_isa == PROCESSOR_K1OM)
2710 {
2711 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2712 || flag_code != CODE_64BIT)
2713 as_fatal (_("Intel K1OM is 64bit ELF only"));
2714 return bfd_arch_k1om;
2715 }
81486035
L		 2716 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2717 {
2718 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2719 || flag_code == CODE_64BIT)
2720 as_fatal (_("Intel MCU is 32bit ELF only"));
2721 return bfd_arch_iamcu;
2722 }
8a9036a4
L		 2723 else
2724 return bfd_arch_i386;
2725}
2726
b9d79e03 2727unsigned long
7016a5d5 2728i386_mach (void)
b9d79e03 2729{
351f65ca 2730 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2731 {
3632d14b 2732 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2733 {
351f65ca
L		 2734 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2735 || default_arch[6] != '\0')
8a9036a4
L		 2736 as_fatal (_("Intel L1OM is 64bit ELF only"));
2737 return bfd_mach_l1om;
2738 }
7a9068fe
L		 2739 else if (cpu_arch_isa == PROCESSOR_K1OM)
2740 {
2741 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2742 || default_arch[6] != '\0')
2743 as_fatal (_("Intel K1OM is 64bit ELF only"));
2744 return bfd_mach_k1om;
2745 }
351f65ca 2746 else if (default_arch[6] == '\0')
8a9036a4 2747 return bfd_mach_x86_64;
351f65ca
L		 2748 else
2749 return bfd_mach_x64_32;
8a9036a4 2750 }
5197d474
L		 2751 else if (!strcmp (default_arch, "i386")
2752 || !strcmp (default_arch, "iamcu"))
81486035
L		 2753 {
2754 if (cpu_arch_isa == PROCESSOR_IAMCU)
2755 {
2756 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2757 as_fatal (_("Intel MCU is 32bit ELF only"));
2758 return bfd_mach_i386_iamcu;
2759 }
2760 else
2761 return bfd_mach_i386_i386;
2762 }
b9d79e03 2763 else
2b5d6a91 2764 as_fatal (_("unknown architecture"));
b9d79e03 2765}
b9d79e03 2766\f
252b5132 2767void
7016a5d5 2768md_begin (void)
252b5132
RH		 2769{
2770 const char *hash_err;
2771
86fa6981
L		 2772 /* Support pseudo prefixes like {disp32}. */
2773 lex_type ['{'] = LEX_BEGIN_NAME;
2774
47926f60 2775 /* Initialize op_hash hash table. */
252b5132
RH		 2776 op_hash = hash_new ();
2777
2778 {
d3ce72d0 2779 const insn_template *optab;
29b0f896 2780 templates *core_optab;
252b5132 2781
47926f60
KH		 2782 /* Setup for loop. */
2783 optab = i386_optab;
add39d23 2784 core_optab = XNEW (templates);
252b5132
RH		 2785 core_optab->start = optab;
2786
2787 while (1)
2788 {
2789 ++optab;
2790 if (optab->name == NULL
2791 || strcmp (optab->name, (optab - 1)->name) != 0)
2792 {
2793 /* different name --> ship out current template list;
47926f60 2794 add to hash table; & begin anew. */
252b5132
RH		 2795 core_optab->end = optab;
2796 hash_err = hash_insert (op_hash,
2797 (optab - 1)->name,
5a49b8ac 2798 (void *) core_optab);
252b5132
RH		 2799 if (hash_err)
2800 {
b37df7c4 2801 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2802 (optab - 1)->name,
2803 hash_err);
2804 }
2805 if (optab->name == NULL)
2806 break;
add39d23 2807 core_optab = XNEW (templates);
252b5132
RH		 2808 core_optab->start = optab;
2809 }
2810 }
2811 }
2812
47926f60 2813 /* Initialize reg_hash hash table. */
252b5132
RH		 2814 reg_hash = hash_new ();
2815 {
29b0f896 2816 const reg_entry *regtab;
c3fe08fa 2817 unsigned int regtab_size = i386_regtab_size;
252b5132 2818
c3fe08fa 2819 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2820 {
5a49b8ac 2821 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2822 if (hash_err)
b37df7c4 2823 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2824 regtab->reg_name,
2825 hash_err);
252b5132
RH		 2826 }
2827 }
2828
47926f60 2829 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2830 {
29b0f896
AM		 2831 int c;
2832 char *p;
252b5132
RH		 2833
2834 for (c = 0; c < 256; c++)
2835 {
3882b010 2836 if (ISDIGIT (c))
252b5132
RH		 2837 {
2838 digit_chars[c] = c;
2839 mnemonic_chars[c] = c;
2840 register_chars[c] = c;
2841 operand_chars[c] = c;
2842 }
3882b010 2843 else if (ISLOWER (c))
252b5132
RH		 2844 {
2845 mnemonic_chars[c] = c;
2846 register_chars[c] = c;
2847 operand_chars[c] = c;
2848 }
3882b010 2849 else if (ISUPPER (c))
252b5132 2850 {
3882b010 2851 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2852 register_chars[c] = mnemonic_chars[c];
2853 operand_chars[c] = c;
2854 }
43234a1e 2855 else if (c == '{' || c == '}')
86fa6981
L		 2856 {
2857 mnemonic_chars[c] = c;
2858 operand_chars[c] = c;
2859 }
252b5132 2860
3882b010 2861 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2862 identifier_chars[c] = c;
2863 else if (c >= 128)
2864 {
2865 identifier_chars[c] = c;
2866 operand_chars[c] = c;
2867 }
2868 }
2869
2870#ifdef LEX_AT
2871 identifier_chars['@'] = '@';
32137342
NC		 2872#endif
2873#ifdef LEX_QM
2874 identifier_chars['?'] = '?';
2875 operand_chars['?'] = '?';
252b5132 2876#endif
252b5132 2877 digit_chars['-'] = '-';
c0f3af97 2878 mnemonic_chars['_'] = '_';
791fe849 2879 mnemonic_chars['-'] = '-';
0003779b 2880 mnemonic_chars['.'] = '.';
252b5132
RH		 2881 identifier_chars['_'] = '_';
2882 identifier_chars['.'] = '.';
2883
2884 for (p = operand_special_chars; *p != '\0'; p++)
2885 operand_chars[(unsigned char) *p] = *p;
2886 }
2887
a4447b93
RH		 2888 if (flag_code == CODE_64BIT)
2889 {
ca19b261
KT		 2890#if defined (OBJ_COFF) && defined (TE_PE)
2891 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2892 ? 32 : 16);
2893#else
a4447b93 2894 x86_dwarf2_return_column = 16;
ca19b261 2895#endif
61ff971f 2896 x86_cie_data_alignment = -8;
a4447b93
RH		 2897 }
2898 else
2899 {
2900 x86_dwarf2_return_column = 8;
2901 x86_cie_data_alignment = -4;
2902 }
252b5132
RH		 2903}
2904
2905void
e3bb37b5 2906i386_print_statistics (FILE *file)
252b5132
RH		 2907{
2908 hash_print_statistics (file, "i386 opcode", op_hash);
2909 hash_print_statistics (file, "i386 register", reg_hash);
2910}
2911\f
252b5132
RH		 2912#ifdef DEBUG386
2913
ce8a8b2f 2914/* Debugging routines for md_assemble. */
d3ce72d0 2915static void pte (insn_template *);
40fb9820 2916static void pt (i386_operand_type);
e3bb37b5
L		 2917static void pe (expressionS *);
2918static void ps (symbolS *);
252b5132
RH		 2919
2920static void
e3bb37b5 2921pi (char *line, i386_insn *x)
252b5132 2922{
09137c09 2923 unsigned int j;
252b5132
RH		 2924
2925 fprintf (stdout, "%s: template ", line);
2926 pte (&x->tm);
09f131f2
JH		 2927 fprintf (stdout, " address: base %s index %s scale %x\n",
2928 x->base_reg ? x->base_reg->reg_name : "none",
2929 x->index_reg ? x->index_reg->reg_name : "none",
2930 x->log2_scale_factor);
2931 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2932 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2933 fprintf (stdout, " sib: base %x index %x scale %x\n",
2934 x->sib.base, x->sib.index, x->sib.scale);
2935 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2936 (x->rex & REX_W) != 0,
2937 (x->rex & REX_R) != 0,
2938 (x->rex & REX_X) != 0,
2939 (x->rex & REX_B) != 0);
09137c09 2940 for (j = 0; j < x->operands; j++)
252b5132 2941 {
09137c09
SP		 2942 fprintf (stdout, " #%d: ", j + 1);
2943 pt (x->types[j]);
252b5132 2944 fprintf (stdout, "\n");
dc821c5f 2945 if (x->types[j].bitfield.reg
09137c09 2946 || x->types[j].bitfield.regmmx
1b54b8d7 2947 || x->types[j].bitfield.regsimd
09137c09
SP		 2948 || x->types[j].bitfield.sreg2
2949 || x->types[j].bitfield.sreg3
2950 || x->types[j].bitfield.control
2951 || x->types[j].bitfield.debug
2952 || x->types[j].bitfield.test)
2953 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2954 if (operand_type_check (x->types[j], imm))
2955 pe (x->op[j].imms);
2956 if (operand_type_check (x->types[j], disp))
2957 pe (x->op[j].disps);
252b5132
RH		 2958 }
2959}
2960
2961static void
d3ce72d0 2962pte (insn_template *t)
252b5132 2963{
09137c09 2964 unsigned int j;
252b5132 2965 fprintf (stdout, " %d operands ", t->operands);
47926f60 2966 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2967 if (t->extension_opcode != None)
2968 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2969 if (t->opcode_modifier.d)
252b5132 2970 fprintf (stdout, "D");
40fb9820 2971 if (t->opcode_modifier.w)
252b5132
RH		 2972 fprintf (stdout, "W");
2973 fprintf (stdout, "\n");
09137c09 2974 for (j = 0; j < t->operands; j++)
252b5132 2975 {
09137c09
SP		 2976 fprintf (stdout, " #%d type ", j + 1);
2977 pt (t->operand_types[j]);
252b5132
RH		 2978 fprintf (stdout, "\n");
2979 }
2980}
2981
2982static void
e3bb37b5 2983pe (expressionS *e)
252b5132 2984{
24eab124 2985 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2986 fprintf (stdout, " add_number %ld (%lx)\n",
2987 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2988 if (e->X_add_symbol)
2989 {
2990 fprintf (stdout, " add_symbol ");
2991 ps (e->X_add_symbol);
2992 fprintf (stdout, "\n");
2993 }
2994 if (e->X_op_symbol)
2995 {
2996 fprintf (stdout, " op_symbol ");
2997 ps (e->X_op_symbol);
2998 fprintf (stdout, "\n");
2999 }
3000}
3001
3002static void
e3bb37b5 3003ps (symbolS *s)
252b5132
RH		 3004{
3005 fprintf (stdout, "%s type %s%s",
3006 S_GET_NAME (s),
3007 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3008 segment_name (S_GET_SEGMENT (s)));
3009}
3010
7b81dfbb 3011static struct type_name
252b5132 3012 {
40fb9820
L		 3013 i386_operand_type mask;
3014 const char *name;
252b5132 3015 }
7b81dfbb 3016const type_names[] =
252b5132 3017{
40fb9820
L		 3018 { OPERAND_TYPE_REG8, "r8" },
3019 { OPERAND_TYPE_REG16, "r16" },
3020 { OPERAND_TYPE_REG32, "r32" },
3021 { OPERAND_TYPE_REG64, "r64" },
3022 { OPERAND_TYPE_IMM8, "i8" },
3023 { OPERAND_TYPE_IMM8, "i8s" },
3024 { OPERAND_TYPE_IMM16, "i16" },
3025 { OPERAND_TYPE_IMM32, "i32" },
3026 { OPERAND_TYPE_IMM32S, "i32s" },
3027 { OPERAND_TYPE_IMM64, "i64" },
3028 { OPERAND_TYPE_IMM1, "i1" },
3029 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3030 { OPERAND_TYPE_DISP8, "d8" },
3031 { OPERAND_TYPE_DISP16, "d16" },
3032 { OPERAND_TYPE_DISP32, "d32" },
3033 { OPERAND_TYPE_DISP32S, "d32s" },
3034 { OPERAND_TYPE_DISP64, "d64" },
3035 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3036 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3037 { OPERAND_TYPE_CONTROL, "control reg" },
3038 { OPERAND_TYPE_TEST, "test reg" },
3039 { OPERAND_TYPE_DEBUG, "debug reg" },
3040 { OPERAND_TYPE_FLOATREG, "FReg" },
3041 { OPERAND_TYPE_FLOATACC, "FAcc" },
3042 { OPERAND_TYPE_SREG2, "SReg2" },
3043 { OPERAND_TYPE_SREG3, "SReg3" },
3044 { OPERAND_TYPE_ACC, "Acc" },
3045 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3046 { OPERAND_TYPE_REGMMX, "rMMX" },
3047 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 3048 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 3049 { OPERAND_TYPE_REGZMM, "rZMM" },
3050 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 3051 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 3052};
3053
3054static void
40fb9820 3055pt (i386_operand_type t)
252b5132 3056{
40fb9820 3057 unsigned int j;
c6fb90c8 3058 i386_operand_type a;
252b5132 3059
40fb9820 3060 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 3061 {
3062 a = operand_type_and (t, type_names[j].mask);
0349dc08 3063 if (!operand_type_all_zero (&a))
c6fb90c8
L		 3064 fprintf (stdout, "%s, ", type_names[j].name);
3065 }
252b5132
RH		 3066 fflush (stdout);
3067}
3068
3069#endif /* DEBUG386 */
3070\f
252b5132 3071static bfd_reloc_code_real_type
3956db08 3072reloc (unsigned int size,
64e74474
AM		 3073 int pcrel,
3074 int sign,
3075 bfd_reloc_code_real_type other)
252b5132 3076{
47926f60 3077 if (other != NO_RELOC)
3956db08 3078 {
91d6fa6a 3079 reloc_howto_type *rel;
3956db08
JB		 3080
3081 if (size == 8)
3082 switch (other)
3083 {
64e74474
AM		 3084 case BFD_RELOC_X86_64_GOT32:
3085 return BFD_RELOC_X86_64_GOT64;
3086 break;
553d1284
L		 3087 case BFD_RELOC_X86_64_GOTPLT64:
3088 return BFD_RELOC_X86_64_GOTPLT64;
3089 break;
64e74474
AM		 3090 case BFD_RELOC_X86_64_PLTOFF64:
3091 return BFD_RELOC_X86_64_PLTOFF64;
3092 break;
3093 case BFD_RELOC_X86_64_GOTPC32:
3094 other = BFD_RELOC_X86_64_GOTPC64;
3095 break;
3096 case BFD_RELOC_X86_64_GOTPCREL:
3097 other = BFD_RELOC_X86_64_GOTPCREL64;
3098 break;
3099 case BFD_RELOC_X86_64_TPOFF32:
3100 other = BFD_RELOC_X86_64_TPOFF64;
3101 break;
3102 case BFD_RELOC_X86_64_DTPOFF32:
3103 other = BFD_RELOC_X86_64_DTPOFF64;
3104 break;
3105 default:
3106 break;
3956db08 3107 }
e05278af 3108
8ce3d284 3109#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 3110 if (other == BFD_RELOC_SIZE32)
3111 {
3112 if (size == 8)
1ab668bf 3113 other = BFD_RELOC_SIZE64;
8fd4256d 3114 if (pcrel)
1ab668bf
AM		 3115 {
3116 as_bad (_("there are no pc-relative size relocations"));
3117 return NO_RELOC;
3118 }
8fd4256d 3119 }
8ce3d284 3120#endif
8fd4256d 3121
e05278af 3122 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 3123 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 3124 sign = -1;
3125
91d6fa6a
NC		 3126 rel = bfd_reloc_type_lookup (stdoutput, other);
3127 if (!rel)
3956db08 3128 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 3129 else if (size != bfd_get_reloc_size (rel))
3956db08 3130 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 3131 bfd_get_reloc_size (rel),
3956db08 3132 size);
91d6fa6a 3133 else if (pcrel && !rel->pc_relative)
3956db08 3134 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 3135 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 3136 && !sign)
91d6fa6a 3137 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 3138 && sign > 0))
3956db08
JB		 3139 as_bad (_("relocated field and relocation type differ in signedness"));
3140 else
3141 return other;
3142 return NO_RELOC;
3143 }
252b5132
RH		 3144
3145 if (pcrel)
3146 {
3e73aa7c 3147 if (!sign)
3956db08 3148 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 3149 switch (size)
3150 {
3151 case 1: return BFD_RELOC_8_PCREL;
3152 case 2: return BFD_RELOC_16_PCREL;
d258b828 3153 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 3154 case 8: return BFD_RELOC_64_PCREL;
252b5132 3155 }
3956db08 3156 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3157 }
3158 else
3159 {
3956db08 3160 if (sign > 0)
e5cb08ac 3161 switch (size)
3e73aa7c
JH		 3162 {
3163 case 4: return BFD_RELOC_X86_64_32S;
3164 }
3165 else
3166 switch (size)
3167 {
3168 case 1: return BFD_RELOC_8;
3169 case 2: return BFD_RELOC_16;
3170 case 4: return BFD_RELOC_32;
3171 case 8: return BFD_RELOC_64;
3172 }
3956db08
JB		 3173 as_bad (_("cannot do %s %u byte relocation"),
3174 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3175 }
3176
0cc9e1d3 3177 return NO_RELOC;
252b5132
RH		 3178}
3179
47926f60
KH		 3180/* Here we decide which fixups can be adjusted to make them relative to
3181 the beginning of the section instead of the symbol. Basically we need
3182 to make sure that the dynamic relocations are done correctly, so in
3183 some cases we force the original symbol to be used. */
3184
252b5132 3185int
e3bb37b5 3186tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3187{
6d249963 3188#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3189 if (!IS_ELF)
31312f95
AM		 3190 return 1;
3191
a161fe53
AM		 3192 /* Don't adjust pc-relative references to merge sections in 64-bit
3193 mode. */
3194 if (use_rela_relocations
3195 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3196 && fixP->fx_pcrel)
252b5132 3197 return 0;
31312f95 3198
8d01d9a9
AJ		 3199 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3200 and changed later by validate_fix. */
3201 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3202 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3203 return 0;
3204
8fd4256d
L		 3205 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3206 for size relocations. */
3207 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3208 || fixP->fx_r_type == BFD_RELOC_SIZE64
3209 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3210 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3211 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3212 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3213 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3214 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3215 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3216 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3217 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3218 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3219 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3220 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3221 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3222 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3223 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3224 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3225 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3226 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3227 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3228 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3229 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3230 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3231 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3232 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3233 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3234 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3235 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3236 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3237 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3238 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3239 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3240 return 0;
31312f95 3241#endif
252b5132
RH		 3242 return 1;
3243}
252b5132 3244
b4cac588 3245static int
e3bb37b5 3246intel_float_operand (const char *mnemonic)
252b5132 3247{
9306ca4a
JB		 3248 /* Note that the value returned is meaningful only for opcodes with (memory)
3249 operands, hence the code here is free to improperly handle opcodes that
3250 have no operands (for better performance and smaller code). */
3251
3252 if (mnemonic[0] != 'f')
3253 return 0; /* non-math */
3254
3255 switch (mnemonic[1])
3256 {
3257 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3258 the fs segment override prefix not currently handled because no
3259 call path can make opcodes without operands get here */
3260 case 'i':
3261 return 2 /* integer op */;
3262 case 'l':
3263 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3264 return 3; /* fldcw/fldenv */
3265 break;
3266 case 'n':
3267 if (mnemonic[2] != 'o' /* fnop */)
3268 return 3; /* non-waiting control op */
3269 break;
3270 case 'r':
3271 if (mnemonic[2] == 's')
3272 return 3; /* frstor/frstpm */
3273 break;
3274 case 's':
3275 if (mnemonic[2] == 'a')
3276 return 3; /* fsave */
3277 if (mnemonic[2] == 't')
3278 {
3279 switch (mnemonic[3])
3280 {
3281 case 'c': /* fstcw */
3282 case 'd': /* fstdw */
3283 case 'e': /* fstenv */
3284 case 's': /* fsts[gw] */
3285 return 3;
3286 }
3287 }
3288 break;
3289 case 'x':
3290 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3291 return 0; /* fxsave/fxrstor are not really math ops */
3292 break;
3293 }
252b5132 3294
9306ca4a 3295 return 1;
252b5132
RH		 3296}
3297
c0f3af97
L		 3298/* Build the VEX prefix. */
3299
3300static void
d3ce72d0 3301build_vex_prefix (const insn_template *t)
c0f3af97
L		 3302{
3303 unsigned int register_specifier;
3304 unsigned int implied_prefix;
3305 unsigned int vector_length;
3306
3307 /* Check register specifier. */
3308 if (i.vex.register_specifier)
43234a1e
L		 3309 {
3310 register_specifier =
3311 ~register_number (i.vex.register_specifier) & 0xf;
3312 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3313 }
c0f3af97
L		 3314 else
3315 register_specifier = 0xf;
3316
33eaf5de 3317 /* Use 2-byte VEX prefix by swapping destination and source
fa99fab2 3318 operand. */
86fa6981
L		 3319 if (i.vec_encoding != vex_encoding_vex3
3320 && i.dir_encoding == dir_encoding_default
fa99fab2 3321 && i.operands == i.reg_operands
7f399153 3322 && i.tm.opcode_modifier.vexopcode == VEX0F
86fa6981 3323 && i.tm.opcode_modifier.load
fa99fab2
L		 3324 && i.rex == REX_B)
3325 {
3326 unsigned int xchg = i.operands - 1;
3327 union i386_op temp_op;
3328 i386_operand_type temp_type;
3329
3330 temp_type = i.types[xchg];
3331 i.types[xchg] = i.types[0];
3332 i.types[0] = temp_type;
3333 temp_op = i.op[xchg];
3334 i.op[xchg] = i.op[0];
3335 i.op[0] = temp_op;
3336
9c2799c2 3337 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3338
3339 i.rex = REX_R;
3340 xchg = i.rm.regmem;
3341 i.rm.regmem = i.rm.reg;
3342 i.rm.reg = xchg;
3343
3344 /* Use the next insn. */
3345 i.tm = t[1];
3346 }
3347
539f890d
L		 3348 if (i.tm.opcode_modifier.vex == VEXScalar)
3349 vector_length = avxscalar;
10c17abd
JB		 3350 else if (i.tm.opcode_modifier.vex == VEX256)
3351 vector_length = 1;
539f890d 3352 else
10c17abd
JB		 3353 {
3354 unsigned int op;
3355
3356 vector_length = 0;
3357 for (op = 0; op < t->operands; ++op)
3358 if (t->operand_types[op].bitfield.xmmword
3359 && t->operand_types[op].bitfield.ymmword
3360 && i.types[op].bitfield.ymmword)
3361 {
3362 vector_length = 1;
3363 break;
3364 }
3365 }
c0f3af97
L		 3366
3367 switch ((i.tm.base_opcode >> 8) & 0xff)
3368 {
3369 case 0:
3370 implied_prefix = 0;
3371 break;
3372 case DATA_PREFIX_OPCODE:
3373 implied_prefix = 1;
3374 break;
3375 case REPE_PREFIX_OPCODE:
3376 implied_prefix = 2;
3377 break;
3378 case REPNE_PREFIX_OPCODE:
3379 implied_prefix = 3;
3380 break;
3381 default:
3382 abort ();
3383 }
3384
3385 /* Use 2-byte VEX prefix if possible. */
86fa6981
L		 3386 if (i.vec_encoding != vex_encoding_vex3
3387 && i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3388 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3389 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3390 {
3391 /* 2-byte VEX prefix. */
3392 unsigned int r;
3393
3394 i.vex.length = 2;
3395 i.vex.bytes[0] = 0xc5;
3396
3397 /* Check the REX.R bit. */
3398 r = (i.rex & REX_R) ? 0 : 1;
3399 i.vex.bytes[1] = (r << 7
3400 | register_specifier << 3
3401 | vector_length << 2
3402 | implied_prefix);
3403 }
3404 else
3405 {
3406 /* 3-byte VEX prefix. */
3407 unsigned int m, w;
3408
f88c9eb0 3409 i.vex.length = 3;
f88c9eb0 3410
7f399153 3411 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3412 {
7f399153
L		 3413 case VEX0F:
3414 m = 0x1;
80de6e00 3415 i.vex.bytes[0] = 0xc4;
7f399153
L		 3416 break;
3417 case VEX0F38:
3418 m = 0x2;
80de6e00 3419 i.vex.bytes[0] = 0xc4;
7f399153
L		 3420 break;
3421 case VEX0F3A:
3422 m = 0x3;
80de6e00 3423 i.vex.bytes[0] = 0xc4;
7f399153
L		 3424 break;
3425 case XOP08:
5dd85c99
SP		 3426 m = 0x8;
3427 i.vex.bytes[0] = 0x8f;
7f399153
L		 3428 break;
3429 case XOP09:
f88c9eb0
SP		 3430 m = 0x9;
3431 i.vex.bytes[0] = 0x8f;
7f399153
L		 3432 break;
3433 case XOP0A:
f88c9eb0
SP		 3434 m = 0xa;
3435 i.vex.bytes[0] = 0x8f;
7f399153
L		 3436 break;
3437 default:
3438 abort ();
f88c9eb0 3439 }
c0f3af97 3440
c0f3af97
L		 3441 /* The high 3 bits of the second VEX byte are 1's compliment
3442 of RXB bits from REX. */
3443 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3444
3445 /* Check the REX.W bit. */
3446 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3447 if (i.tm.opcode_modifier.vexw == VEXW1)
3448 w = 1;
c0f3af97
L		 3449
3450 i.vex.bytes[2] = (w << 7
3451 | register_specifier << 3
3452 | vector_length << 2
3453 | implied_prefix);
3454 }
3455}
3456
e771e7c9
JB		 3457static INLINE bfd_boolean
3458is_evex_encoding (const insn_template *t)
3459{
3460 return t->opcode_modifier.evex
3461 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3462 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3463}
3464
43234a1e
L		 3465/* Build the EVEX prefix. */
3466
3467static void
3468build_evex_prefix (void)
3469{
3470 unsigned int register_specifier;
3471 unsigned int implied_prefix;
3472 unsigned int m, w;
3473 rex_byte vrex_used = 0;
3474
3475 /* Check register specifier. */
3476 if (i.vex.register_specifier)
3477 {
3478 gas_assert ((i.vrex & REX_X) == 0);
3479
3480 register_specifier = i.vex.register_specifier->reg_num;
3481 if ((i.vex.register_specifier->reg_flags & RegRex))
3482 register_specifier += 8;
3483 /* The upper 16 registers are encoded in the fourth byte of the
3484 EVEX prefix. */
3485 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3486 i.vex.bytes[3] = 0x8;
3487 register_specifier = ~register_specifier & 0xf;
3488 }
3489 else
3490 {
3491 register_specifier = 0xf;
3492
3493 /* Encode upper 16 vector index register in the fourth byte of
3494 the EVEX prefix. */
3495 if (!(i.vrex & REX_X))
3496 i.vex.bytes[3] = 0x8;
3497 else
3498 vrex_used |= REX_X;
3499 }
3500
3501 switch ((i.tm.base_opcode >> 8) & 0xff)
3502 {
3503 case 0:
3504 implied_prefix = 0;
3505 break;
3506 case DATA_PREFIX_OPCODE:
3507 implied_prefix = 1;
3508 break;
3509 case REPE_PREFIX_OPCODE:
3510 implied_prefix = 2;
3511 break;
3512 case REPNE_PREFIX_OPCODE:
3513 implied_prefix = 3;
3514 break;
3515 default:
3516 abort ();
3517 }
3518
3519 /* 4 byte EVEX prefix. */
3520 i.vex.length = 4;
3521 i.vex.bytes[0] = 0x62;
3522
3523 /* mmmm bits. */
3524 switch (i.tm.opcode_modifier.vexopcode)
3525 {
3526 case VEX0F:
3527 m = 1;
3528 break;
3529 case VEX0F38:
3530 m = 2;
3531 break;
3532 case VEX0F3A:
3533 m = 3;
3534 break;
3535 default:
3536 abort ();
3537 break;
3538 }
3539
3540 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3541 bits from REX. */
3542 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3543
3544 /* The fifth bit of the second EVEX byte is 1's compliment of the
3545 REX_R bit in VREX. */
3546 if (!(i.vrex & REX_R))
3547 i.vex.bytes[1] |= 0x10;
3548 else
3549 vrex_used |= REX_R;
3550
3551 if ((i.reg_operands + i.imm_operands) == i.operands)
3552 {
3553 /* When all operands are registers, the REX_X bit in REX is not
3554 used. We reuse it to encode the upper 16 registers, which is
3555 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3556 as 1's compliment. */
3557 if ((i.vrex & REX_B))
3558 {
3559 vrex_used |= REX_B;
3560 i.vex.bytes[1] &= ~0x40;
3561 }
3562 }
3563
3564 /* EVEX instructions shouldn't need the REX prefix. */
3565 i.vrex &= ~vrex_used;
3566 gas_assert (i.vrex == 0);
3567
3568 /* Check the REX.W bit. */
3569 w = (i.rex & REX_W) ? 1 : 0;
3570 if (i.tm.opcode_modifier.vexw)
3571 {
3572 if (i.tm.opcode_modifier.vexw == VEXW1)
3573 w = 1;
3574 }
3575 /* If w is not set it means we are dealing with WIG instruction. */
3576 else if (!w)
3577 {
3578 if (evexwig == evexw1)
3579 w = 1;
3580 }
3581
3582 /* Encode the U bit. */
3583 implied_prefix |= 0x4;
3584
3585 /* The third byte of the EVEX prefix. */
3586 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3587
3588 /* The fourth byte of the EVEX prefix. */
3589 /* The zeroing-masking bit. */
3590 if (i.mask && i.mask->zeroing)
3591 i.vex.bytes[3] |= 0x80;
3592
3593 /* Don't always set the broadcast bit if there is no RC. */
3594 if (!i.rounding)
3595 {
3596 /* Encode the vector length. */
3597 unsigned int vec_length;
3598
e771e7c9
JB		 3599 if (!i.tm.opcode_modifier.evex
3600 || i.tm.opcode_modifier.evex == EVEXDYN)
3601 {
3602 unsigned int op;
3603
3604 vec_length = 0;
3605 for (op = 0; op < i.tm.operands; ++op)
3606 if (i.tm.operand_types[op].bitfield.xmmword
3607 + i.tm.operand_types[op].bitfield.ymmword
3608 + i.tm.operand_types[op].bitfield.zmmword > 1)
3609 {
3610 if (i.types[op].bitfield.zmmword)
3611 i.tm.opcode_modifier.evex = EVEX512;
3612 else if (i.types[op].bitfield.ymmword)
3613 i.tm.opcode_modifier.evex = EVEX256;
3614 else if (i.types[op].bitfield.xmmword)
3615 i.tm.opcode_modifier.evex = EVEX128;
3616 else
3617 continue;
3618 break;
3619 }
3620 }
3621
43234a1e
L		 3622 switch (i.tm.opcode_modifier.evex)
3623 {
3624 case EVEXLIG: /* LL' is ignored */
3625 vec_length = evexlig << 5;
3626 break;
3627 case EVEX128:
3628 vec_length = 0 << 5;
3629 break;
3630 case EVEX256:
3631 vec_length = 1 << 5;
3632 break;
3633 case EVEX512:
3634 vec_length = 2 << 5;
3635 break;
3636 default:
3637 abort ();
3638 break;
3639 }
3640 i.vex.bytes[3] |= vec_length;
3641 /* Encode the broadcast bit. */
3642 if (i.broadcast)
3643 i.vex.bytes[3] |= 0x10;
3644 }
3645 else
3646 {
3647 if (i.rounding->type != saeonly)
3648 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3649 else
d3d3c6db 3650 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3651 }
3652
3653 if (i.mask && i.mask->mask)
3654 i.vex.bytes[3] |= i.mask->mask->reg_num;
3655}
3656
65da13b5
L		 3657static void
3658process_immext (void)
3659{
3660 expressionS *exp;
3661
4c692bc7
JB		 3662 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3663 && i.operands > 0)
65da13b5 3664 {
4c692bc7
JB		 3665 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3666 with an opcode suffix which is coded in the same place as an
3667 8-bit immediate field would be.
3668 Here we check those operands and remove them afterwards. */
65da13b5
L		 3669 unsigned int x;
3670
3671 for (x = 0; x < i.operands; x++)
4c692bc7 3672 if (register_number (i.op[x].regs) != x)
65da13b5 3673 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3674 register_prefix, i.op[x].regs->reg_name, x + 1,
3675 i.tm.name);
3676
3677 i.operands = 0;
65da13b5
L		 3678 }
3679
9916071f
AP		 3680 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3681 {
3682 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3683 suffix which is coded in the same place as an 8-bit immediate
3684 field would be.
3685 Here we check those operands and remove them afterwards. */
3686 unsigned int x;
3687
3688 if (i.operands != 3)
3689 abort();
3690
3691 for (x = 0; x < 2; x++)
3692 if (register_number (i.op[x].regs) != x)
3693 goto bad_register_operand;
3694
3695 /* Check for third operand for mwaitx/monitorx insn. */
3696 if (register_number (i.op[x].regs)
3697 != (x + (i.tm.extension_opcode == 0xfb)))
3698 {
3699bad_register_operand:
3700 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3701 register_prefix, i.op[x].regs->reg_name, x+1,
3702 i.tm.name);
3703 }
3704
3705 i.operands = 0;
3706 }
3707
c0f3af97 3708 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3709 which is coded in the same place as an 8-bit immediate field
3710 would be. Here we fake an 8-bit immediate operand from the
3711 opcode suffix stored in tm.extension_opcode.
3712
c1e679ec 3713 AVX instructions also use this encoding, for some of
c0f3af97 3714 3 argument instructions. */
65da13b5 3715
43234a1e 3716 gas_assert (i.imm_operands <= 1
7ab9ffdd 3717 && (i.operands <= 2
43234a1e 3718 || ((i.tm.opcode_modifier.vex
e771e7c9
JB		 3719 || i.tm.opcode_modifier.vexopcode
3720 || is_evex_encoding (&i.tm))
7ab9ffdd 3721 && i.operands <= 4)));
65da13b5
L		 3722
3723 exp = &im_expressions[i.imm_operands++];
3724 i.op[i.operands].imms = exp;
3725 i.types[i.operands] = imm8;
3726 i.operands++;
3727 exp->X_op = O_constant;
3728 exp->X_add_number = i.tm.extension_opcode;
3729 i.tm.extension_opcode = None;
3730}
3731
42164a71
L		 3732
3733static int
3734check_hle (void)
3735{
3736 switch (i.tm.opcode_modifier.hleprefixok)
3737 {
3738 default:
3739 abort ();
82c2def5 3740 case HLEPrefixNone:
165de32a
L		 3741 as_bad (_("invalid instruction `%s' after `%s'"),
3742 i.tm.name, i.hle_prefix);
42164a71 3743 return 0;
82c2def5 3744 case HLEPrefixLock:
42164a71
L		 3745 if (i.prefix[LOCK_PREFIX])
3746 return 1;
165de32a 3747 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3748 return 0;
82c2def5 3749 case HLEPrefixAny:
42164a71 3750 return 1;
82c2def5 3751 case HLEPrefixRelease:
42164a71
L		 3752 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3753 {
3754 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3755 i.tm.name);
3756 return 0;
3757 }
3758 if (i.mem_operands == 0
3759 || !operand_type_check (i.types[i.operands - 1], anymem))
3760 {
3761 as_bad (_("memory destination needed for instruction `%s'"
3762 " after `xrelease'"), i.tm.name);
3763 return 0;
3764 }
3765 return 1;
3766 }
3767}
3768
b6f8c7c4
L		 3769/* Try the shortest encoding by shortening operand size. */
3770
3771static void
3772optimize_encoding (void)
3773{
3774 int j;
3775
3776 if (optimize_for_space
3777 && i.reg_operands == 1
3778 && i.imm_operands == 1
3779 && !i.types[1].bitfield.byte
3780 && i.op[0].imms->X_op == O_constant
3781 && fits_in_imm7 (i.op[0].imms->X_add_number)
3782 && ((i.tm.base_opcode == 0xa8
3783 && i.tm.extension_opcode == None)
3784 || (i.tm.base_opcode == 0xf6
3785 && i.tm.extension_opcode == 0x0)))
3786 {
3787 /* Optimize: -Os:
3788 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3789 */
3790 unsigned int base_regnum = i.op[1].regs->reg_num;
3791 if (flag_code == CODE_64BIT || base_regnum < 4)
3792 {
3793 i.types[1].bitfield.byte = 1;
3794 /* Ignore the suffix. */
3795 i.suffix = 0;
3796 if (base_regnum >= 4
3797 && !(i.op[1].regs->reg_flags & RegRex))
3798 {
3799 /* Handle SP, BP, SI and DI registers. */
3800 if (i.types[1].bitfield.word)
3801 j = 16;
3802 else if (i.types[1].bitfield.dword)
3803 j = 32;
3804 else
3805 j = 48;
3806 i.op[1].regs -= j;
3807 }
3808 }
3809 }
3810 else if (flag_code == CODE_64BIT
d3d50934
L		 3811 && ((i.types[1].bitfield.qword
3812 && i.reg_operands == 1
b6f8c7c4
L		 3813 && i.imm_operands == 1
3814 && i.op[0].imms->X_op == O_constant
3815 && ((i.tm.base_opcode == 0xb0
3816 && i.tm.extension_opcode == None
3817 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3818 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3819 && (((i.tm.base_opcode == 0x24
3820 || i.tm.base_opcode == 0xa8)
3821 && i.tm.extension_opcode == None)
3822 || (i.tm.base_opcode == 0x80
3823 && i.tm.extension_opcode == 0x4)
3824 || ((i.tm.base_opcode == 0xf6
3825 || i.tm.base_opcode == 0xc6)
3826 && i.tm.extension_opcode == 0x0)))))
d3d50934
L		 3827 || (i.types[0].bitfield.qword
3828 && ((i.reg_operands == 2
3829 && i.op[0].regs == i.op[1].regs
3830 && ((i.tm.base_opcode == 0x30
3831 || i.tm.base_opcode == 0x28)
3832 && i.tm.extension_opcode == None))
3833 || (i.reg_operands == 1
3834 && i.operands == 1
3835 && i.tm.base_opcode == 0x30
3836 && i.tm.extension_opcode == None)))))
b6f8c7c4
L		 3837 {
3838 /* Optimize: -O:
3839 andq $imm31, %r64 -> andl $imm31, %r32
3840 testq $imm31, %r64 -> testl $imm31, %r32
3841 xorq %r64, %r64 -> xorl %r32, %r32
3842 subq %r64, %r64 -> subl %r32, %r32
3843 movq $imm31, %r64 -> movl $imm31, %r32
3844 movq $imm32, %r64 -> movl $imm32, %r32
3845 */
3846 i.tm.opcode_modifier.norex64 = 1;
3847 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3848 {
3849 /* Handle
3850 movq $imm31, %r64 -> movl $imm31, %r32
3851 movq $imm32, %r64 -> movl $imm32, %r32
3852 */
3853 i.tm.operand_types[0].bitfield.imm32 = 1;
3854 i.tm.operand_types[0].bitfield.imm32s = 0;
3855 i.tm.operand_types[0].bitfield.imm64 = 0;
3856 i.types[0].bitfield.imm32 = 1;
3857 i.types[0].bitfield.imm32s = 0;
3858 i.types[0].bitfield.imm64 = 0;
3859 i.types[1].bitfield.dword = 1;
3860 i.types[1].bitfield.qword = 0;
3861 if (i.tm.base_opcode == 0xc6)
3862 {
3863 /* Handle
3864 movq $imm31, %r64 -> movl $imm31, %r32
3865 */
3866 i.tm.base_opcode = 0xb0;
3867 i.tm.extension_opcode = None;
3868 i.tm.opcode_modifier.shortform = 1;
3869 i.tm.opcode_modifier.modrm = 0;
3870 }
3871 }
3872 }
3873 else if (optimize > 1
3874 && i.reg_operands == 3
3875 && i.op[0].regs == i.op[1].regs
3876 && !i.types[2].bitfield.xmmword
3877 && (i.tm.opcode_modifier.vex
3878 || (!i.mask
3879 && !i.rounding
e771e7c9 3880 && is_evex_encoding (&i.tm)
80c34c38
L		 3881 && (i.vec_encoding != vex_encoding_evex
3882 || i.tm.cpu_flags.bitfield.cpuavx512vl
0089dace 3883 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
b6f8c7c4
L		 3884 && ((i.tm.base_opcode == 0x55
3885 || i.tm.base_opcode == 0x6655
3886 || i.tm.base_opcode == 0x66df
3887 || i.tm.base_opcode == 0x57
3888 || i.tm.base_opcode == 0x6657
8305403a
L		 3889 || i.tm.base_opcode == 0x66ef
3890 || i.tm.base_opcode == 0x66f8
3891 || i.tm.base_opcode == 0x66f9
3892 || i.tm.base_opcode == 0x66fa
3893 || i.tm.base_opcode == 0x66fb)
b6f8c7c4
L		 3894 && i.tm.extension_opcode == None))
3895 {
3896 /* Optimize: -O2:
8305403a
L		 3897 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3898 vpsubq and vpsubw:
b6f8c7c4
L		 3899 EVEX VOP %zmmM, %zmmM, %zmmN
3900 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3901 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3902 EVEX VOP %ymmM, %ymmM, %ymmN
3903 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3904 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3905 VEX VOP %ymmM, %ymmM, %ymmN
3906 -> VEX VOP %xmmM, %xmmM, %xmmN
3907 VOP, one of vpandn and vpxor:
3908 VEX VOP %ymmM, %ymmM, %ymmN
3909 -> VEX VOP %xmmM, %xmmM, %xmmN
3910 VOP, one of vpandnd and vpandnq:
3911 EVEX VOP %zmmM, %zmmM, %zmmN
3912 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3913 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3914 EVEX VOP %ymmM, %ymmM, %ymmN
3915 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3916 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3917 VOP, one of vpxord and vpxorq:
3918 EVEX VOP %zmmM, %zmmM, %zmmN
3919 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3920 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3921 EVEX VOP %ymmM, %ymmM, %ymmN
3922 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3923 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3924 */
e771e7c9 3925 if (is_evex_encoding (&i.tm))
b6f8c7c4 3926 {
0089dace 3927 if (i.vec_encoding == vex_encoding_evex)
b6f8c7c4
L		 3928 i.tm.opcode_modifier.evex = EVEX128;
3929 else
3930 {
3931 i.tm.opcode_modifier.vex = VEX128;
3932 i.tm.opcode_modifier.vexw = VEXW0;
3933 i.tm.opcode_modifier.evex = 0;
3934 }
3935 }
3936 else
3937 i.tm.opcode_modifier.vex = VEX128;
3938
3939 if (i.tm.opcode_modifier.vex)
3940 for (j = 0; j < 3; j++)
3941 {
3942 i.types[j].bitfield.xmmword = 1;
3943 i.types[j].bitfield.ymmword = 0;
3944 }
3945 }
3946}
3947
252b5132
RH		 3948/* This is the guts of the machine-dependent assembler. LINE points to a
3949 machine dependent instruction. This function is supposed to emit
3950 the frags/bytes it assembles to. */
3951
3952void
65da13b5 3953md_assemble (char *line)
252b5132 3954{
40fb9820 3955 unsigned int j;
83b16ac6 3956 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3957 const insn_template *t;
252b5132 3958
47926f60 3959 /* Initialize globals. */
252b5132
RH		 3960 memset (&i, '\0', sizeof (i));
3961 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3962 i.reloc[j] = NO_RELOC;
252b5132
RH		 3963 memset (disp_expressions, '\0', sizeof (disp_expressions));
3964 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3965 save_stack_p = save_stack;
252b5132
RH		 3966
3967 /* First parse an instruction mnemonic & call i386_operand for the operands.
3968 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3969 start of a (possibly prefixed) mnemonic. */
252b5132 3970
29b0f896
AM		 3971 line = parse_insn (line, mnemonic);
3972 if (line == NULL)
3973 return;
83b16ac6 3974 mnem_suffix = i.suffix;
252b5132 3975
29b0f896 3976 line = parse_operands (line, mnemonic);
ee86248c 3977 this_operand = -1;
8325cc63
JB		 3978 xfree (i.memop1_string);
3979 i.memop1_string = NULL;
29b0f896
AM		 3980 if (line == NULL)
3981 return;
252b5132 3982
29b0f896
AM		 3983 /* Now we've parsed the mnemonic into a set of templates, and have the
3984 operands at hand. */
3985
3986 /* All intel opcodes have reversed operands except for "bound" and
3987 "enter". We also don't reverse intersegment "jmp" and "call"
3988 instructions with 2 immediate operands so that the immediate segment
050dfa73 3989 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3990 if (intel_syntax
3991 && i.operands > 1
29b0f896 3992 && (strcmp (mnemonic, "bound") != 0)
30123838 3993 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3994 && !(operand_type_check (i.types[0], imm)
3995 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3996 swap_operands ();
3997
ec56d5c0
JB		 3998 /* The order of the immediates should be reversed
3999 for 2 immediates extrq and insertq instructions */
4000 if (i.imm_operands == 2
4001 && (strcmp (mnemonic, "extrq") == 0
4002 || strcmp (mnemonic, "insertq") == 0))
4003 swap_2_operands (0, 1);
4004
29b0f896
AM		 4005 if (i.imm_operands)
4006 optimize_imm ();
4007
b300c311
L		 4008 /* Don't optimize displacement for movabs since it only takes 64bit
4009 displacement. */
4010 if (i.disp_operands
a501d77e 4011 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 4012 && (flag_code != CODE_64BIT
4013 || strcmp (mnemonic, "movabs") != 0))
4014 optimize_disp ();
29b0f896
AM		 4015
4016 /* Next, we find a template that matches the given insn,
4017 making sure the overlap of the given operands types is consistent
4018 with the template operand types. */
252b5132 4019
83b16ac6 4020 if (!(t = match_template (mnem_suffix)))
29b0f896 4021 return;
252b5132 4022
7bab8ab5 4023 if (sse_check != check_none
81f8a913 4024 && !i.tm.opcode_modifier.noavx
6e3e5c9e 4025 && !i.tm.cpu_flags.bitfield.cpuavx
daf50ae7
L		 4026 && (i.tm.cpu_flags.bitfield.cpusse
4027 || i.tm.cpu_flags.bitfield.cpusse2
4028 || i.tm.cpu_flags.bitfield.cpusse3
4029 || i.tm.cpu_flags.bitfield.cpussse3
4030 || i.tm.cpu_flags.bitfield.cpusse4_1
6e3e5c9e
JB		 4031 || i.tm.cpu_flags.bitfield.cpusse4_2
4032 || i.tm.cpu_flags.bitfield.cpupclmul
4033 || i.tm.cpu_flags.bitfield.cpuaes
4034 || i.tm.cpu_flags.bitfield.cpugfni))
daf50ae7 4035 {
7bab8ab5 4036 (sse_check == check_warning
daf50ae7
L		 4037 ? as_warn
4038 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4039 }
4040
321fd21e
L		 4041 /* Zap movzx and movsx suffix. The suffix has been set from
4042 "word ptr" or "byte ptr" on the source operand in Intel syntax
4043 or extracted from mnemonic in AT&T syntax. But we'll use
4044 the destination register to choose the suffix for encoding. */
4045 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 4046 {
321fd21e
L		 4047 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4048 there is no suffix, the default will be byte extension. */
4049 if (i.reg_operands != 2
4050 && !i.suffix
7ab9ffdd 4051 && intel_syntax)
321fd21e
L		 4052 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4053
4054 i.suffix = 0;
cd61ebfe 4055 }
24eab124 4056
40fb9820 4057 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 4058 if (!add_prefix (FWAIT_OPCODE))
4059 return;
252b5132 4060
d5de92cf
L		 4061 /* Check if REP prefix is OK. */
4062 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4063 {
4064 as_bad (_("invalid instruction `%s' after `%s'"),
4065 i.tm.name, i.rep_prefix);
4066 return;
4067 }
4068
c1ba0266
L		 4069 /* Check for lock without a lockable instruction. Destination operand
4070 must be memory unless it is xchg (0x86). */
c32fa91d
L		 4071 if (i.prefix[LOCK_PREFIX]
4072 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 4073 || i.mem_operands == 0
4074 || (i.tm.base_opcode != 0x86
4075 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 4076 {
4077 as_bad (_("expecting lockable instruction after `lock'"));
4078 return;
4079 }
4080
42164a71 4081 /* Check if HLE prefix is OK. */
165de32a 4082 if (i.hle_prefix && !check_hle ())
42164a71
L		 4083 return;
4084
7e8b059b
L		 4085 /* Check BND prefix. */
4086 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4087 as_bad (_("expecting valid branch instruction after `bnd'"));
4088
04ef582a 4089 /* Check NOTRACK prefix. */
9fef80d6
L		 4090 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4091 as_bad (_("expecting indirect branch instruction after `notrack'"));
04ef582a 4092
327e8c42
JB		 4093 if (i.tm.cpu_flags.bitfield.cpumpx)
4094 {
4095 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4096 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4097 else if (flag_code != CODE_16BIT
4098 ? i.prefix[ADDR_PREFIX]
4099 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4100 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4101 }
7e8b059b
L		 4102
4103 /* Insert BND prefix. */
4104 if (add_bnd_prefix
4105 && i.tm.opcode_modifier.bndprefixok
4106 && !i.prefix[BND_PREFIX])
4107 add_prefix (BND_PREFIX_OPCODE);
4108
29b0f896 4109 /* Check string instruction segment overrides. */
40fb9820 4110 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 4111 {
4112 if (!check_string ())
5dd0794d 4113 return;
fc0763e6 4114 i.disp_operands = 0;
29b0f896 4115 }
5dd0794d 4116
b6f8c7c4
L		 4117 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4118 optimize_encoding ();
4119
29b0f896
AM		 4120 if (!process_suffix ())
4121 return;
e413e4e9 4122
bc0844ae
L		 4123 /* Update operand types. */
4124 for (j = 0; j < i.operands; j++)
4125 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4126
29b0f896
AM		 4127 /* Make still unresolved immediate matches conform to size of immediate
4128 given in i.suffix. */
4129 if (!finalize_imm ())
4130 return;
252b5132 4131
40fb9820 4132 if (i.types[0].bitfield.imm1)
29b0f896 4133 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 4134
9afe6eb8
L		 4135 /* We only need to check those implicit registers for instructions
4136 with 3 operands or less. */
4137 if (i.operands <= 3)
4138 for (j = 0; j < i.operands; j++)
4139 if (i.types[j].bitfield.inoutportreg
4140 || i.types[j].bitfield.shiftcount
1b54b8d7 4141 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
9afe6eb8 4142 i.reg_operands--;
40fb9820 4143
c0f3af97
L		 4144 /* ImmExt should be processed after SSE2AVX. */
4145 if (!i.tm.opcode_modifier.sse2avx
4146 && i.tm.opcode_modifier.immext)
65da13b5 4147 process_immext ();
252b5132 4148
29b0f896
AM		 4149 /* For insns with operands there are more diddles to do to the opcode. */
4150 if (i.operands)
4151 {
4152 if (!process_operands ())
4153 return;
4154 }
40fb9820 4155 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 4156 {
4157 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4158 as_warn (_("translating to `%sp'"), i.tm.name);
4159 }
252b5132 4160
e771e7c9
JB		 4161 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4162 || is_evex_encoding (&i.tm))
9e5e5283
L		 4163 {
4164 if (flag_code == CODE_16BIT)
4165 {
4166 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4167 i.tm.name);
4168 return;
4169 }
c0f3af97 4170
9e5e5283
L		 4171 if (i.tm.opcode_modifier.vex)
4172 build_vex_prefix (t);
4173 else
4174 build_evex_prefix ();
4175 }
43234a1e 4176
5dd85c99
SP		 4177 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4178 instructions may define INT_OPCODE as well, so avoid this corner
4179 case for those instructions that use MODRM. */
4180 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 4181 && !i.tm.opcode_modifier.modrm
4182 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 4183 {
4184 i.tm.base_opcode = INT3_OPCODE;
4185 i.imm_operands = 0;
4186 }
252b5132 4187
40fb9820
L		 4188 if ((i.tm.opcode_modifier.jump
4189 || i.tm.opcode_modifier.jumpbyte
4190 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 4191 && i.op[0].disps->X_op == O_constant)
4192 {
4193 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4194 the absolute address given by the constant. Since ix86 jumps and
4195 calls are pc relative, we need to generate a reloc. */
4196 i.op[0].disps->X_add_symbol = &abs_symbol;
4197 i.op[0].disps->X_op = O_symbol;
4198 }
252b5132 4199
40fb9820 4200 if (i.tm.opcode_modifier.rex64)
161a04f6 4201 i.rex |= REX_W;
252b5132 4202
29b0f896
AM		 4203 /* For 8 bit registers we need an empty rex prefix. Also if the
4204 instruction already has a prefix, we need to convert old
4205 registers to new ones. */
773f551c 4206
dc821c5f 4207 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
29b0f896 4208 && (i.op[0].regs->reg_flags & RegRex64) != 0)
dc821c5f 4209 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
29b0f896 4210 && (i.op[1].regs->reg_flags & RegRex64) != 0)
dc821c5f
JB		 4211 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4212 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
29b0f896
AM		 4213 && i.rex != 0))
4214 {
4215 int x;
726c5dcd 4216
29b0f896
AM		 4217 i.rex |= REX_OPCODE;
4218 for (x = 0; x < 2; x++)
4219 {
4220 /* Look for 8 bit operand that uses old registers. */
dc821c5f 4221 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
29b0f896 4222 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 4223 {
29b0f896
AM		 4224 /* In case it is "hi" register, give up. */
4225 if (i.op[x].regs->reg_num > 3)
a540244d 4226 as_bad (_("can't encode register '%s%s' in an "
4eed87de 4227 "instruction requiring REX prefix."),
a540244d 4228 register_prefix, i.op[x].regs->reg_name);
773f551c 4229
29b0f896
AM		 4230 /* Otherwise it is equivalent to the extended register.
4231 Since the encoding doesn't change this is merely
4232 cosmetic cleanup for debug output. */
4233
4234 i.op[x].regs = i.op[x].regs + 8;
773f551c 4235 }
29b0f896
AM		 4236 }
4237 }
773f551c 4238
6b6b6807
L		 4239 if (i.rex == 0 && i.rex_encoding)
4240 {
4241 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4242 that uses legacy register. If it is "hi" register, don't add
4243 the REX_OPCODE byte. */
4244 int x;
4245 for (x = 0; x < 2; x++)
4246 if (i.types[x].bitfield.reg
4247 && i.types[x].bitfield.byte
4248 && (i.op[x].regs->reg_flags & RegRex64) == 0
4249 && i.op[x].regs->reg_num > 3)
4250 {
4251 i.rex_encoding = FALSE;
4252 break;
4253 }
4254
4255 if (i.rex_encoding)
4256 i.rex = REX_OPCODE;
4257 }
4258
7ab9ffdd 4259 if (i.rex != 0)
29b0f896
AM		 4260 add_prefix (REX_OPCODE | i.rex);
4261
4262 /* We are ready to output the insn. */
4263 output_insn ();
4264}
4265
4266static char *
e3bb37b5 4267parse_insn (char *line, char *mnemonic)
29b0f896
AM		 4268{
4269 char *l = line;
4270 char *token_start = l;
4271 char *mnem_p;
5c6af06e 4272 int supported;
d3ce72d0 4273 const insn_template *t;
b6169b20 4274 char *dot_p = NULL;
29b0f896 4275
29b0f896
AM		 4276 while (1)
4277 {
4278 mnem_p = mnemonic;
4279 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4280 {
b6169b20
L		 4281 if (*mnem_p == '.')
4282 dot_p = mnem_p;
29b0f896
AM		 4283 mnem_p++;
4284 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 4285 {
29b0f896
AM		 4286 as_bad (_("no such instruction: `%s'"), token_start);
4287 return NULL;
4288 }
4289 l++;
4290 }
4291 if (!is_space_char (*l)
4292 && *l != END_OF_INSN
e44823cf
JB		 4293 && (intel_syntax
4294 || (*l != PREFIX_SEPARATOR
4295 && *l != ',')))
29b0f896
AM		 4296 {
4297 as_bad (_("invalid character %s in mnemonic"),
4298 output_invalid (*l));
4299 return NULL;
4300 }
4301 if (token_start == l)
4302 {
e44823cf 4303 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 4304 as_bad (_("expecting prefix; got nothing"));
4305 else
4306 as_bad (_("expecting mnemonic; got nothing"));
4307 return NULL;
4308 }
45288df1 4309
29b0f896 4310 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 4311 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 4312
29b0f896
AM		 4313 if (*l != END_OF_INSN
4314 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4315 && current_templates
40fb9820 4316 && current_templates->start->opcode_modifier.isprefix)
29b0f896 4317 {
c6fb90c8 4318 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 4319 {
4320 as_bad ((flag_code != CODE_64BIT
4321 ? _("`%s' is only supported in 64-bit mode")
4322 : _("`%s' is not supported in 64-bit mode")),
4323 current_templates->start->name);
4324 return NULL;
4325 }
29b0f896
AM		 4326 /* If we are in 16-bit mode, do not allow addr16 or data16.
4327 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 4328 if ((current_templates->start->opcode_modifier.size16
4329 || current_templates->start->opcode_modifier.size32)
29b0f896 4330 && flag_code != CODE_64BIT
40fb9820 4331 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 4332 ^ (flag_code == CODE_16BIT)))
4333 {
4334 as_bad (_("redundant %s prefix"),
4335 current_templates->start->name);
4336 return NULL;
45288df1 4337 }
86fa6981 4338 if (current_templates->start->opcode_length == 0)
29b0f896 4339 {
86fa6981
L		 4340 /* Handle pseudo prefixes. */
4341 switch (current_templates->start->base_opcode)
4342 {
4343 case 0x0:
4344 /* {disp8} */
4345 i.disp_encoding = disp_encoding_8bit;
4346 break;
4347 case 0x1:
4348 /* {disp32} */
4349 i.disp_encoding = disp_encoding_32bit;
4350 break;
4351 case 0x2:
4352 /* {load} */
4353 i.dir_encoding = dir_encoding_load;
4354 break;
4355 case 0x3:
4356 /* {store} */
4357 i.dir_encoding = dir_encoding_store;
4358 break;
4359 case 0x4:
4360 /* {vex2} */
4361 i.vec_encoding = vex_encoding_vex2;
4362 break;
4363 case 0x5:
4364 /* {vex3} */
4365 i.vec_encoding = vex_encoding_vex3;
4366 break;
4367 case 0x6:
4368 /* {evex} */
4369 i.vec_encoding = vex_encoding_evex;
4370 break;
6b6b6807
L		 4371 case 0x7:
4372 /* {rex} */
4373 i.rex_encoding = TRUE;
4374 break;
b6f8c7c4
L		 4375 case 0x8:
4376 /* {nooptimize} */
4377 i.no_optimize = TRUE;
4378 break;
86fa6981
L		 4379 default:
4380 abort ();
4381 }
4382 }
4383 else
4384 {
4385 /* Add prefix, checking for repeated prefixes. */
4e9ac44a 4386 switch (add_prefix (current_templates->start->base_opcode))
86fa6981 4387 {
4e9ac44a
L		 4388 case PREFIX_EXIST:
4389 return NULL;
4390 case PREFIX_DS:
d777820b 4391 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4e9ac44a
L		 4392 i.notrack_prefix = current_templates->start->name;
4393 break;
4394 case PREFIX_REP:
4395 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4396 i.hle_prefix = current_templates->start->name;
4397 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4398 i.bnd_prefix = current_templates->start->name;
4399 else
4400 i.rep_prefix = current_templates->start->name;
4401 break;
4402 default:
4403 break;
86fa6981 4404 }
29b0f896
AM		 4405 }
4406 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4407 token_start = ++l;
4408 }
4409 else
4410 break;
4411 }
45288df1 4412
30a55f88 4413 if (!current_templates)
b6169b20 4414 {
f8a5c266
L		 4415 /* Check if we should swap operand or force 32bit displacement in
4416 encoding. */
30a55f88 4417 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
86fa6981 4418 i.dir_encoding = dir_encoding_store;
8d63c93e 4419 else if (mnem_p - 3 == dot_p
a501d77e
L		 4420 && dot_p[1] == 'd'
4421 && dot_p[2] == '8')
4422 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4423 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4424 && dot_p[1] == 'd'
4425 && dot_p[2] == '3'
4426 && dot_p[3] == '2')
a501d77e 4427 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4428 else
4429 goto check_suffix;
4430 mnem_p = dot_p;
4431 *dot_p = '\0';
d3ce72d0 4432 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4433 }
4434
29b0f896
AM		 4435 if (!current_templates)
4436 {
b6169b20 4437check_suffix:
29b0f896
AM		 4438 /* See if we can get a match by trimming off a suffix. */
4439 switch (mnem_p[-1])
4440 {
4441 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 4442 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4443 i.suffix = SHORT_MNEM_SUFFIX;
4444 else
1a0670f3 4445 /* Fall through. */
29b0f896
AM		 4446 case BYTE_MNEM_SUFFIX:
4447 case QWORD_MNEM_SUFFIX:
4448 i.suffix = mnem_p[-1];
4449 mnem_p[-1] = '\0';
d3ce72d0
NC		 4450 current_templates = (const templates *) hash_find (op_hash,
4451 mnemonic);
29b0f896
AM		 4452 break;
4453 case SHORT_MNEM_SUFFIX:
4454 case LONG_MNEM_SUFFIX:
4455 if (!intel_syntax)
4456 {
4457 i.suffix = mnem_p[-1];
4458 mnem_p[-1] = '\0';
d3ce72d0
NC		 4459 current_templates = (const templates *) hash_find (op_hash,
4460 mnemonic);
29b0f896
AM		 4461 }
4462 break;
252b5132 4463
29b0f896
AM		 4464 /* Intel Syntax. */
4465 case 'd':
4466 if (intel_syntax)
4467 {
9306ca4a 4468 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 4469 i.suffix = SHORT_MNEM_SUFFIX;
4470 else
4471 i.suffix = LONG_MNEM_SUFFIX;
4472 mnem_p[-1] = '\0';
d3ce72d0
NC		 4473 current_templates = (const templates *) hash_find (op_hash,
4474 mnemonic);
29b0f896
AM		 4475 }
4476 break;
4477 }
4478 if (!current_templates)
4479 {
4480 as_bad (_("no such instruction: `%s'"), token_start);
4481 return NULL;
4482 }
4483 }
252b5132 4484
40fb9820
L		 4485 if (current_templates->start->opcode_modifier.jump
4486 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4487 {
4488 /* Check for a branch hint. We allow ",pt" and ",pn" for
4489 predict taken and predict not taken respectively.
4490 I'm not sure that branch hints actually do anything on loop
4491 and jcxz insns (JumpByte) for current Pentium4 chips. They
4492 may work in the future and it doesn't hurt to accept them
4493 now. */
4494 if (l[0] == ',' && l[1] == 'p')
4495 {
4496 if (l[2] == 't')
4497 {
4498 if (!add_prefix (DS_PREFIX_OPCODE))
4499 return NULL;
4500 l += 3;
4501 }
4502 else if (l[2] == 'n')
4503 {
4504 if (!add_prefix (CS_PREFIX_OPCODE))
4505 return NULL;
4506 l += 3;
4507 }
4508 }
4509 }
4510 /* Any other comma loses. */
4511 if (*l == ',')
4512 {
4513 as_bad (_("invalid character %s in mnemonic"),
4514 output_invalid (*l));
4515 return NULL;
4516 }
252b5132 4517
29b0f896 4518 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4519 supported = 0;
4520 for (t = current_templates->start; t < current_templates->end; ++t)
4521 {
c0f3af97
L		 4522 supported |= cpu_flags_match (t);
4523 if (supported == CPU_FLAGS_PERFECT_MATCH)
548d0ee6
JB		 4524 {
4525 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4526 as_warn (_("use .code16 to ensure correct addressing mode"));
3629bb00 4527
548d0ee6
JB		 4528 return l;
4529 }
29b0f896 4530 }
3629bb00 4531
548d0ee6
JB		 4532 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4533 as_bad (flag_code == CODE_64BIT
4534 ? _("`%s' is not supported in 64-bit mode")
4535 : _("`%s' is only supported in 64-bit mode"),
4536 current_templates->start->name);
4537 else
4538 as_bad (_("`%s' is not supported on `%s%s'"),
4539 current_templates->start->name,
4540 cpu_arch_name ? cpu_arch_name : default_arch,
4541 cpu_sub_arch_name ? cpu_sub_arch_name : "");
252b5132 4542
548d0ee6 4543 return NULL;
29b0f896 4544}
252b5132 4545
29b0f896 4546static char *
e3bb37b5 4547parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4548{
4549 char *token_start;
3138f287 4550
29b0f896
AM		 4551 /* 1 if operand is pending after ','. */
4552 unsigned int expecting_operand = 0;
252b5132 4553
29b0f896
AM		 4554 /* Non-zero if operand parens not balanced. */
4555 unsigned int paren_not_balanced;
4556
4557 while (*l != END_OF_INSN)
4558 {
4559 /* Skip optional white space before operand. */
4560 if (is_space_char (*l))
4561 ++l;
d02603dc 4562 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4563 {
4564 as_bad (_("invalid character %s before operand %d"),
4565 output_invalid (*l),
4566 i.operands + 1);
4567 return NULL;
4568 }
d02603dc 4569 token_start = l; /* After white space. */
29b0f896
AM		 4570 paren_not_balanced = 0;
4571 while (paren_not_balanced || *l != ',')
4572 {
4573 if (*l == END_OF_INSN)
4574 {
4575 if (paren_not_balanced)
4576 {
4577 if (!intel_syntax)
4578 as_bad (_("unbalanced parenthesis in operand %d."),
4579 i.operands + 1);
4580 else
4581 as_bad (_("unbalanced brackets in operand %d."),
4582 i.operands + 1);
4583 return NULL;
4584 }
4585 else
4586 break; /* we are done */
4587 }
d02603dc 4588 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4589 {
4590 as_bad (_("invalid character %s in operand %d"),
4591 output_invalid (*l),
4592 i.operands + 1);
4593 return NULL;
4594 }
4595 if (!intel_syntax)
4596 {
4597 if (*l == '(')
4598 ++paren_not_balanced;
4599 if (*l == ')')
4600 --paren_not_balanced;
4601 }
4602 else
4603 {
4604 if (*l == '[')
4605 ++paren_not_balanced;
4606 if (*l == ']')
4607 --paren_not_balanced;
4608 }
4609 l++;
4610 }
4611 if (l != token_start)
4612 { /* Yes, we've read in another operand. */
4613 unsigned int operand_ok;
4614 this_operand = i.operands++;
4615 if (i.operands > MAX_OPERANDS)
4616 {
4617 as_bad (_("spurious operands; (%d operands/instruction max)"),
4618 MAX_OPERANDS);
4619 return NULL;
4620 }
9d46ce34 4621 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4622 /* Now parse operand adding info to 'i' as we go along. */
4623 END_STRING_AND_SAVE (l);
4624
4625 if (intel_syntax)
4626 operand_ok =
4627 i386_intel_operand (token_start,
4628 intel_float_operand (mnemonic));
4629 else
a7619375 4630 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4631
4632 RESTORE_END_STRING (l);
4633 if (!operand_ok)
4634 return NULL;
4635 }
4636 else
4637 {
4638 if (expecting_operand)
4639 {
4640 expecting_operand_after_comma:
4641 as_bad (_("expecting operand after ','; got nothing"));
4642 return NULL;
4643 }
4644 if (*l == ',')
4645 {
4646 as_bad (_("expecting operand before ','; got nothing"));
4647 return NULL;
4648 }
4649 }
7f3f1ea2 4650
29b0f896
AM		 4651 /* Now *l must be either ',' or END_OF_INSN. */
4652 if (*l == ',')
4653 {
4654 if (*++l == END_OF_INSN)
4655 {
4656 /* Just skip it, if it's \n complain. */
4657 goto expecting_operand_after_comma;
4658 }
4659 expecting_operand = 1;
4660 }
4661 }
4662 return l;
4663}
7f3f1ea2 4664
050dfa73 4665static void
4d456e3d 4666swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4667{
4668 union i386_op temp_op;
40fb9820 4669 i386_operand_type temp_type;
050dfa73 4670 enum bfd_reloc_code_real temp_reloc;
4eed87de 4671
050dfa73
MM		 4672 temp_type = i.types[xchg2];
4673 i.types[xchg2] = i.types[xchg1];
4674 i.types[xchg1] = temp_type;
4675 temp_op = i.op[xchg2];
4676 i.op[xchg2] = i.op[xchg1];
4677 i.op[xchg1] = temp_op;
4678 temp_reloc = i.reloc[xchg2];
4679 i.reloc[xchg2] = i.reloc[xchg1];
4680 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4681
4682 if (i.mask)
4683 {
4684 if (i.mask->operand == xchg1)
4685 i.mask->operand = xchg2;
4686 else if (i.mask->operand == xchg2)
4687 i.mask->operand = xchg1;
4688 }
4689 if (i.broadcast)
4690 {
4691 if (i.broadcast->operand == xchg1)
4692 i.broadcast->operand = xchg2;
4693 else if (i.broadcast->operand == xchg2)
4694 i.broadcast->operand = xchg1;
4695 }
4696 if (i.rounding)
4697 {
4698 if (i.rounding->operand == xchg1)
4699 i.rounding->operand = xchg2;
4700 else if (i.rounding->operand == xchg2)
4701 i.rounding->operand = xchg1;
4702 }
050dfa73
MM		 4703}
4704
29b0f896 4705static void
e3bb37b5 4706swap_operands (void)
29b0f896 4707{
b7c61d9a 4708 switch (i.operands)
050dfa73 4709 {
c0f3af97 4710 case 5:
b7c61d9a 4711 case 4:
4d456e3d 4712 swap_2_operands (1, i.operands - 2);
1a0670f3 4713 /* Fall through. */
b7c61d9a
L		 4714 case 3:
4715 case 2:
4d456e3d 4716 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4717 break;
4718 default:
4719 abort ();
29b0f896 4720 }
29b0f896
AM		 4721
4722 if (i.mem_operands == 2)
4723 {
4724 const seg_entry *temp_seg;
4725 temp_seg = i.seg[0];
4726 i.seg[0] = i.seg[1];
4727 i.seg[1] = temp_seg;
4728 }
4729}
252b5132 4730
29b0f896
AM		 4731/* Try to ensure constant immediates are represented in the smallest
4732 opcode possible. */
4733static void
e3bb37b5 4734optimize_imm (void)
29b0f896
AM		 4735{
4736 char guess_suffix = 0;
4737 int op;
252b5132 4738
29b0f896
AM		 4739 if (i.suffix)
4740 guess_suffix = i.suffix;
4741 else if (i.reg_operands)
4742 {
4743 /* Figure out a suffix from the last register operand specified.
4744 We can't do this properly yet, ie. excluding InOutPortReg,
4745 but the following works for instructions with immediates.
4746 In any case, we can't set i.suffix yet. */
4747 for (op = i.operands; --op >= 0;)
dc821c5f 4748 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
7ab9ffdd 4749 {
40fb9820
L		 4750 guess_suffix = BYTE_MNEM_SUFFIX;
4751 break;
4752 }
dc821c5f 4753 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
252b5132 4754 {
40fb9820
L		 4755 guess_suffix = WORD_MNEM_SUFFIX;
4756 break;
4757 }
dc821c5f 4758 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
40fb9820
L		 4759 {
4760 guess_suffix = LONG_MNEM_SUFFIX;
4761 break;
4762 }
dc821c5f 4763 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
40fb9820
L		 4764 {
4765 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4766 break;
252b5132 4767 }
29b0f896
AM		 4768 }
4769 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4770 guess_suffix = WORD_MNEM_SUFFIX;
4771
4772 for (op = i.operands; --op >= 0;)
40fb9820 4773 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4774 {
4775 switch (i.op[op].imms->X_op)
252b5132 4776 {
29b0f896
AM		 4777 case O_constant:
4778 /* If a suffix is given, this operand may be shortened. */
4779 switch (guess_suffix)
252b5132 4780 {
29b0f896 4781 case LONG_MNEM_SUFFIX:
40fb9820
L		 4782 i.types[op].bitfield.imm32 = 1;
4783 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4784 break;
4785 case WORD_MNEM_SUFFIX:
40fb9820
L		 4786 i.types[op].bitfield.imm16 = 1;
4787 i.types[op].bitfield.imm32 = 1;
4788 i.types[op].bitfield.imm32s = 1;
4789 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4790 break;
4791 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4792 i.types[op].bitfield.imm8 = 1;
4793 i.types[op].bitfield.imm8s = 1;
4794 i.types[op].bitfield.imm16 = 1;
4795 i.types[op].bitfield.imm32 = 1;
4796 i.types[op].bitfield.imm32s = 1;
4797 i.types[op].bitfield.imm64 = 1;
29b0f896 4798 break;
252b5132 4799 }
252b5132 4800
29b0f896
AM		 4801 /* If this operand is at most 16 bits, convert it
4802 to a signed 16 bit number before trying to see
4803 whether it will fit in an even smaller size.
4804 This allows a 16-bit operand such as $0xffe0 to
4805 be recognised as within Imm8S range. */
40fb9820 4806 if ((i.types[op].bitfield.imm16)
29b0f896 4807 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4808 {
29b0f896
AM		 4809 i.op[op].imms->X_add_number =
4810 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4811 }
a28def75
L		 4812#ifdef BFD64
4813 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4814 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4815 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4816 == 0))
4817 {
4818 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4819 ^ ((offsetT) 1 << 31))
4820 - ((offsetT) 1 << 31));
4821 }
a28def75 4822#endif
40fb9820 4823 i.types[op]
c6fb90c8
L		 4824 = operand_type_or (i.types[op],
4825 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4826
29b0f896
AM		 4827 /* We must avoid matching of Imm32 templates when 64bit
4828 only immediate is available. */
4829 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4830 i.types[op].bitfield.imm32 = 0;
29b0f896 4831 break;
252b5132 4832
29b0f896
AM		 4833 case O_absent:
4834 case O_register:
4835 abort ();
4836
4837 /* Symbols and expressions. */
4838 default:
9cd96992
JB		 4839 /* Convert symbolic operand to proper sizes for matching, but don't
4840 prevent matching a set of insns that only supports sizes other
4841 than those matching the insn suffix. */
4842 {
40fb9820 4843 i386_operand_type mask, allowed;
d3ce72d0 4844 const insn_template *t;
9cd96992 4845
0dfbf9d7
L		 4846 operand_type_set (&mask, 0);
4847 operand_type_set (&allowed, 0);
40fb9820 4848
4eed87de
AM		 4849 for (t = current_templates->start;
4850 t < current_templates->end;
4851 ++t)
c6fb90c8
L		 4852 allowed = operand_type_or (allowed,
4853 t->operand_types[op]);
9cd96992
JB		 4854 switch (guess_suffix)
4855 {
4856 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4857 mask.bitfield.imm64 = 1;
4858 mask.bitfield.imm32s = 1;
9cd96992
JB		 4859 break;
4860 case LONG_MNEM_SUFFIX:
40fb9820 4861 mask.bitfield.imm32 = 1;
9cd96992
JB		 4862 break;
4863 case WORD_MNEM_SUFFIX:
40fb9820 4864 mask.bitfield.imm16 = 1;
9cd96992
JB		 4865 break;
4866 case BYTE_MNEM_SUFFIX:
40fb9820 4867 mask.bitfield.imm8 = 1;
9cd96992
JB		 4868 break;
4869 default:
9cd96992
JB		 4870 break;
4871 }
c6fb90c8 4872 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4873 if (!operand_type_all_zero (&allowed))
c6fb90c8 4874 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4875 }
29b0f896 4876 break;
252b5132 4877 }
29b0f896
AM		 4878 }
4879}
47926f60 4880
29b0f896
AM		 4881/* Try to use the smallest displacement type too. */
4882static void
e3bb37b5 4883optimize_disp (void)
29b0f896
AM		 4884{
4885 int op;
3e73aa7c 4886
29b0f896 4887 for (op = i.operands; --op >= 0;)
40fb9820 4888 if (operand_type_check (i.types[op], disp))
252b5132 4889 {
b300c311 4890 if (i.op[op].disps->X_op == O_constant)
252b5132 4891 {
91d6fa6a 4892 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4893
40fb9820 4894 if (i.types[op].bitfield.disp16
91d6fa6a 4895 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4896 {
4897 /* If this operand is at most 16 bits, convert
4898 to a signed 16 bit number and don't use 64bit
4899 displacement. */
91d6fa6a 4900 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4901 i.types[op].bitfield.disp64 = 0;
b300c311 4902 }
a28def75
L		 4903#ifdef BFD64
4904 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4905 if (i.types[op].bitfield.disp32
91d6fa6a 4906 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4907 {
4908 /* If this operand is at most 32 bits, convert
4909 to a signed 32 bit number and don't use 64bit
4910 displacement. */
91d6fa6a
NC		 4911 op_disp &= (((offsetT) 2 << 31) - 1);
4912 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4913 i.types[op].bitfield.disp64 = 0;
b300c311 4914 }
a28def75 4915#endif
91d6fa6a 4916 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4917 {
40fb9820
L		 4918 i.types[op].bitfield.disp8 = 0;
4919 i.types[op].bitfield.disp16 = 0;
4920 i.types[op].bitfield.disp32 = 0;
4921 i.types[op].bitfield.disp32s = 0;
4922 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4923 i.op[op].disps = 0;
4924 i.disp_operands--;
4925 }
4926 else if (flag_code == CODE_64BIT)
4927 {
91d6fa6a 4928 if (fits_in_signed_long (op_disp))
28a9d8f5 4929 {
40fb9820
L		 4930 i.types[op].bitfield.disp64 = 0;
4931 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4932 }
0e1147d9 4933 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4934 && fits_in_unsigned_long (op_disp))
40fb9820 4935 i.types[op].bitfield.disp32 = 1;
b300c311 4936 }
40fb9820
L		 4937 if ((i.types[op].bitfield.disp32
4938 || i.types[op].bitfield.disp32s
4939 || i.types[op].bitfield.disp16)
b5014f7a 4940 && fits_in_disp8 (op_disp))
40fb9820 4941 i.types[op].bitfield.disp8 = 1;
252b5132 4942 }
67a4f2b7
AO		 4943 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4944 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4945 {
4946 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4947 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4948 i.types[op].bitfield.disp8 = 0;
4949 i.types[op].bitfield.disp16 = 0;
4950 i.types[op].bitfield.disp32 = 0;
4951 i.types[op].bitfield.disp32s = 0;
4952 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4953 }
4954 else
b300c311 4955 /* We only support 64bit displacement on constants. */
40fb9820 4956 i.types[op].bitfield.disp64 = 0;
252b5132 4957 }
29b0f896
AM		 4958}
4959
6c30d220
L		 4960/* Check if operands are valid for the instruction. */
4961
4962static int
4963check_VecOperands (const insn_template *t)
4964{
43234a1e
L		 4965 unsigned int op;
4966
6c30d220
L		 4967 /* Without VSIB byte, we can't have a vector register for index. */
4968 if (!t->opcode_modifier.vecsib
4969 && i.index_reg
1b54b8d7
JB		 4970 && (i.index_reg->reg_type.bitfield.xmmword
4971 || i.index_reg->reg_type.bitfield.ymmword
4972 || i.index_reg->reg_type.bitfield.zmmword))
6c30d220
L		 4973 {
4974 i.error = unsupported_vector_index_register;
4975 return 1;
4976 }
4977
ad8ecc81
MZ		 4978 /* Check if default mask is allowed. */
4979 if (t->opcode_modifier.nodefmask
4980 && (!i.mask || i.mask->mask->reg_num == 0))
4981 {
4982 i.error = no_default_mask;
4983 return 1;
4984 }
4985
7bab8ab5
JB		 4986 /* For VSIB byte, we need a vector register for index, and all vector
4987 registers must be distinct. */
4988 if (t->opcode_modifier.vecsib)
4989 {
4990 if (!i.index_reg
6c30d220 4991 || !((t->opcode_modifier.vecsib == VecSIB128
1b54b8d7 4992 && i.index_reg->reg_type.bitfield.xmmword)
6c30d220 4993 || (t->opcode_modifier.vecsib == VecSIB256
1b54b8d7 4994 && i.index_reg->reg_type.bitfield.ymmword)
43234a1e 4995 || (t->opcode_modifier.vecsib == VecSIB512
1b54b8d7 4996 && i.index_reg->reg_type.bitfield.zmmword)))
7bab8ab5
JB		 4997 {
4998 i.error = invalid_vsib_address;
4999 return 1;
5000 }
5001
43234a1e
L		 5002 gas_assert (i.reg_operands == 2 || i.mask);
5003 if (i.reg_operands == 2 && !i.mask)
5004 {
1b54b8d7
JB		 5005 gas_assert (i.types[0].bitfield.regsimd);
5006 gas_assert (i.types[0].bitfield.xmmword
5007 || i.types[0].bitfield.ymmword);
5008 gas_assert (i.types[2].bitfield.regsimd);
5009 gas_assert (i.types[2].bitfield.xmmword
5010 || i.types[2].bitfield.ymmword);
43234a1e
L		 5011 if (operand_check == check_none)
5012 return 0;
5013 if (register_number (i.op[0].regs)
5014 != register_number (i.index_reg)
5015 && register_number (i.op[2].regs)
5016 != register_number (i.index_reg)
5017 && register_number (i.op[0].regs)
5018 != register_number (i.op[2].regs))
5019 return 0;
5020 if (operand_check == check_error)
5021 {
5022 i.error = invalid_vector_register_set;
5023 return 1;
5024 }
5025 as_warn (_("mask, index, and destination registers should be distinct"));
5026 }
8444f82a
MZ		 5027 else if (i.reg_operands == 1 && i.mask)
5028 {
1b54b8d7
JB		 5029 if (i.types[1].bitfield.regsimd
5030 && (i.types[1].bitfield.xmmword
5031 || i.types[1].bitfield.ymmword
5032 || i.types[1].bitfield.zmmword)
8444f82a
MZ		 5033 && (register_number (i.op[1].regs)
5034 == register_number (i.index_reg)))
5035 {
5036 if (operand_check == check_error)
5037 {
5038 i.error = invalid_vector_register_set;
5039 return 1;
5040 }
5041 if (operand_check != check_none)
5042 as_warn (_("index and destination registers should be distinct"));
5043 }
5044 }
43234a1e 5045 }
7bab8ab5 5046
43234a1e
L		 5047 /* Check if broadcast is supported by the instruction and is applied
5048 to the memory operand. */
5049 if (i.broadcast)
5050 {
5051 int broadcasted_opnd_size;
5052
5053 /* Check if specified broadcast is supported in this instruction,
5054 and it's applied to memory operand of DWORD or QWORD type,
5055 depending on VecESize. */
5056 if (i.broadcast->type != t->opcode_modifier.broadcast
5057 || !i.types[i.broadcast->operand].bitfield.mem
5058 || (t->opcode_modifier.vecesize == 0
5059 && !i.types[i.broadcast->operand].bitfield.dword
5060 && !i.types[i.broadcast->operand].bitfield.unspecified)
5061 || (t->opcode_modifier.vecesize == 1
5062 && !i.types[i.broadcast->operand].bitfield.qword
5063 && !i.types[i.broadcast->operand].bitfield.unspecified))
5064 goto bad_broadcast;
5065
5066 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
5067 if (i.broadcast->type == BROADCAST_1TO16)
5068 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
5069 else if (i.broadcast->type == BROADCAST_1TO8)
5070 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 5071 else if (i.broadcast->type == BROADCAST_1TO4)
5072 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
5073 else if (i.broadcast->type == BROADCAST_1TO2)
5074 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 5075 else
5076 goto bad_broadcast;
5077
5078 if ((broadcasted_opnd_size == 256
5079 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
5080 || (broadcasted_opnd_size == 512
5081 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
5082 {
5083 bad_broadcast:
5084 i.error = unsupported_broadcast;
5085 return 1;
5086 }
5087 }
5088 /* If broadcast is supported in this instruction, we need to check if
5089 operand of one-element size isn't specified without broadcast. */
5090 else if (t->opcode_modifier.broadcast && i.mem_operands)
5091 {
5092 /* Find memory operand. */
5093 for (op = 0; op < i.operands; op++)
5094 if (operand_type_check (i.types[op], anymem))
5095 break;
5096 gas_assert (op < i.operands);
5097 /* Check size of the memory operand. */
5098 if ((t->opcode_modifier.vecesize == 0
5099 && i.types[op].bitfield.dword)
5100 || (t->opcode_modifier.vecesize == 1
5101 && i.types[op].bitfield.qword))
5102 {
5103 i.error = broadcast_needed;
5104 return 1;
5105 }
5106 }
5107
5108 /* Check if requested masking is supported. */
5109 if (i.mask
5110 && (!t->opcode_modifier.masking
5111 || (i.mask->zeroing
5112 && t->opcode_modifier.masking == MERGING_MASKING)))
5113 {
5114 i.error = unsupported_masking;
5115 return 1;
5116 }
5117
5118 /* Check if masking is applied to dest operand. */
5119 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5120 {
5121 i.error = mask_not_on_destination;
5122 return 1;
5123 }
5124
43234a1e
L		 5125 /* Check RC/SAE. */
5126 if (i.rounding)
5127 {
5128 if ((i.rounding->type != saeonly
5129 && !t->opcode_modifier.staticrounding)
5130 || (i.rounding->type == saeonly
5131 && (t->opcode_modifier.staticrounding
5132 || !t->opcode_modifier.sae)))
5133 {
5134 i.error = unsupported_rc_sae;
5135 return 1;
5136 }
5137 /* If the instruction has several immediate operands and one of
5138 them is rounding, the rounding operand should be the last
5139 immediate operand. */
5140 if (i.imm_operands > 1
5141 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 5142 {
43234a1e 5143 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 5144 return 1;
5145 }
6c30d220
L		 5146 }
5147
43234a1e 5148 /* Check vector Disp8 operand. */
b5014f7a
JB		 5149 if (t->opcode_modifier.disp8memshift
5150 && i.disp_encoding != disp_encoding_32bit)
43234a1e
L		 5151 {
5152 if (i.broadcast)
5153 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
5154 else
5155 i.memshift = t->opcode_modifier.disp8memshift;
5156
5157 for (op = 0; op < i.operands; op++)
5158 if (operand_type_check (i.types[op], disp)
5159 && i.op[op].disps->X_op == O_constant)
5160 {
b5014f7a 5161 if (fits_in_disp8 (i.op[op].disps->X_add_number))
43234a1e 5162 {
b5014f7a
JB		 5163 i.types[op].bitfield.disp8 = 1;
5164 return 0;
43234a1e 5165 }
b5014f7a 5166 i.types[op].bitfield.disp8 = 0;
43234a1e
L		 5167 }
5168 }
b5014f7a
JB		 5169
5170 i.memshift = 0;
43234a1e 5171
6c30d220
L		 5172 return 0;
5173}
5174
43f3e2ee 5175/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 5176 operand types. */
5177
5178static int
5179VEX_check_operands (const insn_template *t)
5180{
86fa6981 5181 if (i.vec_encoding == vex_encoding_evex)
43234a1e 5182 {
86fa6981 5183 /* This instruction must be encoded with EVEX prefix. */
e771e7c9 5184 if (!is_evex_encoding (t))
86fa6981
L		 5185 {
5186 i.error = unsupported;
5187 return 1;
5188 }
5189 return 0;
43234a1e
L		 5190 }
5191
a683cc34 5192 if (!t->opcode_modifier.vex)
86fa6981
L		 5193 {
5194 /* This instruction template doesn't have VEX prefix. */
5195 if (i.vec_encoding != vex_encoding_default)
5196 {
5197 i.error = unsupported;
5198 return 1;
5199 }
5200 return 0;
5201 }
a683cc34
SP		 5202
5203 /* Only check VEX_Imm4, which must be the first operand. */
5204 if (t->operand_types[0].bitfield.vec_imm4)
5205 {
5206 if (i.op[0].imms->X_op != O_constant
5207 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 5208 {
a65babc9 5209 i.error = bad_imm4;
891edac4
L		 5210 return 1;
5211 }
a683cc34
SP		 5212
5213 /* Turn off Imm8 so that update_imm won't complain. */
5214 i.types[0] = vec_imm4;
5215 }
5216
5217 return 0;
5218}
5219
d3ce72d0 5220static const insn_template *
83b16ac6 5221match_template (char mnem_suffix)
29b0f896
AM		 5222{
5223 /* Points to template once we've found it. */
d3ce72d0 5224 const insn_template *t;
40fb9820 5225 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 5226 i386_operand_type overlap4;
29b0f896 5227 unsigned int found_reverse_match;
83b16ac6 5228 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 5229 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 5230 int addr_prefix_disp;
a5c311ca 5231 unsigned int j;
3629bb00 5232 unsigned int found_cpu_match;
45664ddb 5233 unsigned int check_register;
5614d22c 5234 enum i386_error specific_error = 0;
29b0f896 5235
c0f3af97
L		 5236#if MAX_OPERANDS != 5
5237# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 5238#endif
5239
29b0f896 5240 found_reverse_match = 0;
539e75ad 5241 addr_prefix_disp = -1;
40fb9820
L		 5242
5243 memset (&suffix_check, 0, sizeof (suffix_check));
5244 if (i.suffix == BYTE_MNEM_SUFFIX)
5245 suffix_check.no_bsuf = 1;
5246 else if (i.suffix == WORD_MNEM_SUFFIX)
5247 suffix_check.no_wsuf = 1;
5248 else if (i.suffix == SHORT_MNEM_SUFFIX)
5249 suffix_check.no_ssuf = 1;
5250 else if (i.suffix == LONG_MNEM_SUFFIX)
5251 suffix_check.no_lsuf = 1;
5252 else if (i.suffix == QWORD_MNEM_SUFFIX)
5253 suffix_check.no_qsuf = 1;
5254 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 5255 suffix_check.no_ldsuf = 1;
29b0f896 5256
83b16ac6
JB		 5257 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5258 if (intel_syntax)
5259 {
5260 switch (mnem_suffix)
5261 {
5262 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5263 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5264 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5265 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5266 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5267 }
5268 }
5269
01559ecc
L		 5270 /* Must have right number of operands. */
5271 i.error = number_of_operands_mismatch;
5272
45aa61fe 5273 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 5274 {
539e75ad
L		 5275 addr_prefix_disp = -1;
5276
29b0f896
AM		 5277 if (i.operands != t->operands)
5278 continue;
5279
50aecf8c 5280 /* Check processor support. */
a65babc9 5281 i.error = unsupported;
c0f3af97
L		 5282 found_cpu_match = (cpu_flags_match (t)
5283 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 5284 if (!found_cpu_match)
5285 continue;
5286
e1d4d893 5287 /* Check AT&T mnemonic. */
a65babc9 5288 i.error = unsupported_with_intel_mnemonic;
e1d4d893 5289 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 5290 continue;
5291
e92bae62 5292 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 5293 i.error = unsupported_syntax;
5c07affc 5294 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 5295 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5296 || (intel64 && t->opcode_modifier.amd64)
5297 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 5298 continue;
5299
20592a94 5300 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 5301 i.error = invalid_instruction_suffix;
567e4e96
L		 5302 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5303 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5304 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5305 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5306 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5307 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5308 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 5309 continue;
83b16ac6
JB		 5310 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5311 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5312 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5313 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5314 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5315 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5316 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5317 continue;
29b0f896 5318
5c07affc 5319 if (!operand_size_match (t))
7d5e4556 5320 continue;
539e75ad 5321
5c07affc
L		 5322 for (j = 0; j < MAX_OPERANDS; j++)
5323 operand_types[j] = t->operand_types[j];
5324
45aa61fe
AM		 5325 /* In general, don't allow 64-bit operands in 32-bit mode. */
5326 if (i.suffix == QWORD_MNEM_SUFFIX
5327 && flag_code != CODE_64BIT
5328 && (intel_syntax
40fb9820 5329 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 5330 && !intel_float_operand (t->name))
5331 : intel_float_operand (t->name) != 2)
40fb9820 5332 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5333 && !operand_types[0].bitfield.regsimd)
40fb9820 5334 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5335 && !operand_types[t->operands > 1].bitfield.regsimd))
45aa61fe
AM		 5336 && (t->base_opcode != 0x0fc7
5337 || t->extension_opcode != 1 /* cmpxchg8b */))
5338 continue;
5339
192dc9c6
JB		 5340 /* In general, don't allow 32-bit operands on pre-386. */
5341 else if (i.suffix == LONG_MNEM_SUFFIX
5342 && !cpu_arch_flags.bitfield.cpui386
5343 && (intel_syntax
5344 ? (!t->opcode_modifier.ignoresize
5345 && !intel_float_operand (t->name))
5346 : intel_float_operand (t->name) != 2)
5347 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5348 && !operand_types[0].bitfield.regsimd)
192dc9c6 5349 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5350 && !operand_types[t->operands > 1].bitfield.regsimd)))
192dc9c6
JB		 5351 continue;
5352
29b0f896 5353 /* Do not verify operands when there are none. */
50aecf8c 5354 else
29b0f896 5355 {
c6fb90c8 5356 if (!t->operands)
2dbab7d5
L		 5357 /* We've found a match; break out of loop. */
5358 break;
29b0f896 5359 }
252b5132 5360
539e75ad
L		 5361 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5362 into Disp32/Disp16/Disp32 operand. */
5363 if (i.prefix[ADDR_PREFIX] != 0)
5364 {
40fb9820 5365 /* There should be only one Disp operand. */
539e75ad
L		 5366 switch (flag_code)
5367 {
5368 case CODE_16BIT:
40fb9820
L		 5369 for (j = 0; j < MAX_OPERANDS; j++)
5370 {
5371 if (operand_types[j].bitfield.disp16)
5372 {
5373 addr_prefix_disp = j;
5374 operand_types[j].bitfield.disp32 = 1;
5375 operand_types[j].bitfield.disp16 = 0;
5376 break;
5377 }
5378 }
539e75ad
L		 5379 break;
5380 case CODE_32BIT:
40fb9820
L		 5381 for (j = 0; j < MAX_OPERANDS; j++)
5382 {
5383 if (operand_types[j].bitfield.disp32)
5384 {
5385 addr_prefix_disp = j;
5386 operand_types[j].bitfield.disp32 = 0;
5387 operand_types[j].bitfield.disp16 = 1;
5388 break;
5389 }
5390 }
539e75ad
L		 5391 break;
5392 case CODE_64BIT:
40fb9820
L		 5393 for (j = 0; j < MAX_OPERANDS; j++)
5394 {
5395 if (operand_types[j].bitfield.disp64)
5396 {
5397 addr_prefix_disp = j;
5398 operand_types[j].bitfield.disp64 = 0;
5399 operand_types[j].bitfield.disp32 = 1;
5400 break;
5401 }
5402 }
539e75ad
L		 5403 break;
5404 }
539e75ad
L		 5405 }
5406
02a86693
L		 5407 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5408 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5409 continue;
5410
56ffb741
L		 5411 /* We check register size if needed. */
5412 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 5413 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5414 switch (t->operands)
5415 {
5416 case 1:
40fb9820 5417 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5418 continue;
5419 break;
5420 case 2:
33eaf5de 5421 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5422 only in 32bit mode and we can use opcode 0x90. In 64bit
5423 mode, we can't use 0x90 for xchg %eax, %eax since it should
5424 zero-extend %eax to %rax. */
5425 if (flag_code == CODE_64BIT
5426 && t->base_opcode == 0x90
0dfbf9d7
L		 5427 && operand_type_equal (&i.types [0], &acc32)
5428 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 5429 continue;
86fa6981
L		 5430 /* If we want store form, we reverse direction of operands. */
5431 if (i.dir_encoding == dir_encoding_store
5432 && t->opcode_modifier.d)
5433 goto check_reverse;
1a0670f3 5434 /* Fall through. */
b6169b20 5435
29b0f896 5436 case 3:
86fa6981
L		 5437 /* If we want store form, we skip the current load. */
5438 if (i.dir_encoding == dir_encoding_store
5439 && i.mem_operands == 0
5440 && t->opcode_modifier.load)
fa99fab2 5441 continue;
1a0670f3 5442 /* Fall through. */
f48ff2ae 5443 case 4:
c0f3af97 5444 case 5:
c6fb90c8 5445 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5446 if (!operand_type_match (overlap0, i.types[0])
5447 || !operand_type_match (overlap1, i.types[1])
45664ddb 5448 || (check_register
dc821c5f 5449 && !operand_type_register_match (i.types[0],
40fb9820 5450 operand_types[0],
dc821c5f 5451 i.types[1],
40fb9820 5452 operand_types[1])))
29b0f896
AM		 5453 {
5454 /* Check if other direction is valid ... */
38e314eb 5455 if (!t->opcode_modifier.d)
29b0f896
AM		 5456 continue;
5457
b6169b20 5458check_reverse:
29b0f896 5459 /* Try reversing direction of operands. */
c6fb90c8
L		 5460 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5461 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 5462 if (!operand_type_match (overlap0, i.types[0])
5463 || !operand_type_match (overlap1, i.types[1])
45664ddb 5464 || (check_register
dc821c5f 5465 && !operand_type_register_match (i.types[0],
45664ddb 5466 operand_types[1],
45664ddb
L		 5467 i.types[1],
5468 operand_types[0])))
29b0f896
AM		 5469 {
5470 /* Does not match either direction. */
5471 continue;
5472 }
38e314eb 5473 /* found_reverse_match holds which of D or FloatR
29b0f896 5474 we've found. */
38e314eb
JB		 5475 if (!t->opcode_modifier.d)
5476 found_reverse_match = 0;
5477 else if (operand_types[0].bitfield.tbyte)
8a2ed489
L		 5478 found_reverse_match = Opcode_FloatD;
5479 else
38e314eb 5480 found_reverse_match = Opcode_D;
40fb9820 5481 if (t->opcode_modifier.floatr)
8a2ed489 5482 found_reverse_match |= Opcode_FloatR;
29b0f896 5483 }
f48ff2ae 5484 else
29b0f896 5485 {
f48ff2ae 5486 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5487 switch (t->operands)
5488 {
c0f3af97
L		 5489 case 5:
5490 overlap4 = operand_type_and (i.types[4],
5491 operand_types[4]);
1a0670f3 5492 /* Fall through. */
d1cbb4db 5493 case 4:
c6fb90c8
L		 5494 overlap3 = operand_type_and (i.types[3],
5495 operand_types[3]);
1a0670f3 5496 /* Fall through. */
d1cbb4db 5497 case 3:
c6fb90c8
L		 5498 overlap2 = operand_type_and (i.types[2],
5499 operand_types[2]);
d1cbb4db
L		 5500 break;
5501 }
29b0f896 5502
f48ff2ae
L		 5503 switch (t->operands)
5504 {
c0f3af97
L		 5505 case 5:
5506 if (!operand_type_match (overlap4, i.types[4])
dc821c5f 5507 || !operand_type_register_match (i.types[3],
c0f3af97 5508 operand_types[3],
c0f3af97
L		 5509 i.types[4],
5510 operand_types[4]))
5511 continue;
1a0670f3 5512 /* Fall through. */
f48ff2ae 5513 case 4:
40fb9820 5514 if (!operand_type_match (overlap3, i.types[3])
45664ddb 5515 || (check_register
f7768225
JB		 5516 && (!operand_type_register_match (i.types[1],
5517 operand_types[1],
5518 i.types[3],
5519 operand_types[3])
5520 || !operand_type_register_match (i.types[2],
5521 operand_types[2],
5522 i.types[3],
5523 operand_types[3]))))
f48ff2ae 5524 continue;
1a0670f3 5525 /* Fall through. */
f48ff2ae
L		 5526 case 3:
5527 /* Here we make use of the fact that there are no
23e42951 5528 reverse match 3 operand instructions. */
40fb9820 5529 if (!operand_type_match (overlap2, i.types[2])
45664ddb 5530 || (check_register
23e42951
JB		 5531 && (!operand_type_register_match (i.types[0],
5532 operand_types[0],
5533 i.types[2],
5534 operand_types[2])
5535 || !operand_type_register_match (i.types[1],
5536 operand_types[1],
5537 i.types[2],
5538 operand_types[2]))))
f48ff2ae
L		 5539 continue;
5540 break;
5541 }
29b0f896 5542 }
f48ff2ae 5543 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5544 slip through to break. */
5545 }
3629bb00 5546 if (!found_cpu_match)
29b0f896
AM		 5547 {
5548 found_reverse_match = 0;
5549 continue;
5550 }
c0f3af97 5551
5614d22c
JB		 5552 /* Check if vector and VEX operands are valid. */
5553 if (check_VecOperands (t) || VEX_check_operands (t))
5554 {
5555 specific_error = i.error;
5556 continue;
5557 }
a683cc34 5558
29b0f896
AM		 5559 /* We've found a match; break out of loop. */
5560 break;
5561 }
5562
5563 if (t == current_templates->end)
5564 {
5565 /* We found no match. */
a65babc9 5566 const char *err_msg;
5614d22c 5567 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5568 {
5569 default:
5570 abort ();
86e026a4 5571 case operand_size_mismatch:
a65babc9
L		 5572 err_msg = _("operand size mismatch");
5573 break;
5574 case operand_type_mismatch:
5575 err_msg = _("operand type mismatch");
5576 break;
5577 case register_type_mismatch:
5578 err_msg = _("register type mismatch");
5579 break;
5580 case number_of_operands_mismatch:
5581 err_msg = _("number of operands mismatch");
5582 break;
5583 case invalid_instruction_suffix:
5584 err_msg = _("invalid instruction suffix");
5585 break;
5586 case bad_imm4:
4a2608e3 5587 err_msg = _("constant doesn't fit in 4 bits");
a65babc9 5588 break;
a65babc9
L		 5589 case unsupported_with_intel_mnemonic:
5590 err_msg = _("unsupported with Intel mnemonic");
5591 break;
5592 case unsupported_syntax:
5593 err_msg = _("unsupported syntax");
5594 break;
5595 case unsupported:
35262a23 5596 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5597 current_templates->start->name);
5598 return NULL;
6c30d220
L		 5599 case invalid_vsib_address:
5600 err_msg = _("invalid VSIB address");
5601 break;
7bab8ab5
JB		 5602 case invalid_vector_register_set:
5603 err_msg = _("mask, index, and destination registers must be distinct");
5604 break;
6c30d220
L		 5605 case unsupported_vector_index_register:
5606 err_msg = _("unsupported vector index register");
5607 break;
43234a1e
L		 5608 case unsupported_broadcast:
5609 err_msg = _("unsupported broadcast");
5610 break;
5611 case broadcast_not_on_src_operand:
5612 err_msg = _("broadcast not on source memory operand");
5613 break;
5614 case broadcast_needed:
5615 err_msg = _("broadcast is needed for operand of such type");
5616 break;
5617 case unsupported_masking:
5618 err_msg = _("unsupported masking");
5619 break;
5620 case mask_not_on_destination:
5621 err_msg = _("mask not on destination operand");
5622 break;
5623 case no_default_mask:
5624 err_msg = _("default mask isn't allowed");
5625 break;
5626 case unsupported_rc_sae:
5627 err_msg = _("unsupported static rounding/sae");
5628 break;
5629 case rc_sae_operand_not_last_imm:
5630 if (intel_syntax)
5631 err_msg = _("RC/SAE operand must precede immediate operands");
5632 else
5633 err_msg = _("RC/SAE operand must follow immediate operands");
5634 break;
5635 case invalid_register_operand:
5636 err_msg = _("invalid register operand");
5637 break;
a65babc9
L		 5638 }
5639 as_bad (_("%s for `%s'"), err_msg,
891edac4 5640 current_templates->start->name);
fa99fab2 5641 return NULL;
29b0f896 5642 }
252b5132 5643
29b0f896
AM		 5644 if (!quiet_warnings)
5645 {
5646 if (!intel_syntax
40fb9820
L		 5647 && (i.types[0].bitfield.jumpabsolute
5648 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5649 {
5650 as_warn (_("indirect %s without `*'"), t->name);
5651 }
5652
40fb9820
L		 5653 if (t->opcode_modifier.isprefix
5654 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5655 {
5656 /* Warn them that a data or address size prefix doesn't
5657 affect assembly of the next line of code. */
5658 as_warn (_("stand-alone `%s' prefix"), t->name);
5659 }
5660 }
5661
5662 /* Copy the template we found. */
5663 i.tm = *t;
539e75ad
L		 5664
5665 if (addr_prefix_disp != -1)
5666 i.tm.operand_types[addr_prefix_disp]
5667 = operand_types[addr_prefix_disp];
5668
29b0f896
AM		 5669 if (found_reverse_match)
5670 {
5671 /* If we found a reverse match we must alter the opcode
5672 direction bit. found_reverse_match holds bits to change
5673 (different for int & float insns). */
5674
5675 i.tm.base_opcode ^= found_reverse_match;
5676
539e75ad
L		 5677 i.tm.operand_types[0] = operand_types[1];
5678 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5679 }
5680
fa99fab2 5681 return t;
29b0f896
AM		 5682}
5683
5684static int
e3bb37b5 5685check_string (void)
29b0f896 5686{
40fb9820
L		 5687 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5688 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5689 {
5690 if (i.seg[0] != NULL && i.seg[0] != &es)
5691 {
a87af027 5692 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5693 i.tm.name,
a87af027
JB		 5694 mem_op + 1,
5695 register_prefix);
29b0f896
AM		 5696 return 0;
5697 }
5698 /* There's only ever one segment override allowed per instruction.
5699 This instruction possibly has a legal segment override on the
5700 second operand, so copy the segment to where non-string
5701 instructions store it, allowing common code. */
5702 i.seg[0] = i.seg[1];
5703 }
40fb9820 5704 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5705 {
5706 if (i.seg[1] != NULL && i.seg[1] != &es)
5707 {
a87af027 5708 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5709 i.tm.name,
a87af027
JB		 5710 mem_op + 2,
5711 register_prefix);
29b0f896
AM		 5712 return 0;
5713 }
5714 }
5715 return 1;
5716}
5717
5718static int
543613e9 5719process_suffix (void)
29b0f896
AM		 5720{
5721 /* If matched instruction specifies an explicit instruction mnemonic
5722 suffix, use it. */
40fb9820
L		 5723 if (i.tm.opcode_modifier.size16)
5724 i.suffix = WORD_MNEM_SUFFIX;
5725 else if (i.tm.opcode_modifier.size32)
5726 i.suffix = LONG_MNEM_SUFFIX;
5727 else if (i.tm.opcode_modifier.size64)
5728 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5729 else if (i.reg_operands)
5730 {
5731 /* If there's no instruction mnemonic suffix we try to invent one
5732 based on register operands. */
5733 if (!i.suffix)
5734 {
5735 /* We take i.suffix from the last register operand specified,
5736 Destination register type is more significant than source
381d071f
L		 5737 register type. crc32 in SSE4.2 prefers source register
5738 type. */
5739 if (i.tm.base_opcode == 0xf20f38f1)
5740 {
dc821c5f 5741 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
40fb9820 5742 i.suffix = WORD_MNEM_SUFFIX;
dc821c5f 5743 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
40fb9820 5744 i.suffix = LONG_MNEM_SUFFIX;
dc821c5f 5745 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
40fb9820 5746 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5747 }
9344ff29 5748 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5749 {
dc821c5f 5750 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
20592a94
L		 5751 i.suffix = BYTE_MNEM_SUFFIX;
5752 }
381d071f
L		 5753
5754 if (!i.suffix)
5755 {
5756 int op;
5757
20592a94
L		 5758 if (i.tm.base_opcode == 0xf20f38f1
5759 || i.tm.base_opcode == 0xf20f38f0)
5760 {
5761 /* We have to know the operand size for crc32. */
5762 as_bad (_("ambiguous memory operand size for `%s`"),
5763 i.tm.name);
5764 return 0;
5765 }
5766
381d071f 5767 for (op = i.operands; --op >= 0;)
b76bc5d5
JB		 5768 if (!i.tm.operand_types[op].bitfield.inoutportreg
5769 && !i.tm.operand_types[op].bitfield.shiftcount)
381d071f 5770 {
8819ada6
JB		 5771 if (!i.types[op].bitfield.reg)
5772 continue;
5773 if (i.types[op].bitfield.byte)
5774 i.suffix = BYTE_MNEM_SUFFIX;
5775 else if (i.types[op].bitfield.word)
5776 i.suffix = WORD_MNEM_SUFFIX;
5777 else if (i.types[op].bitfield.dword)
5778 i.suffix = LONG_MNEM_SUFFIX;
5779 else if (i.types[op].bitfield.qword)
5780 i.suffix = QWORD_MNEM_SUFFIX;
5781 else
5782 continue;
5783 break;
381d071f
L		 5784 }
5785 }
29b0f896
AM		 5786 }
5787 else if (i.suffix == BYTE_MNEM_SUFFIX)
5788 {
2eb952a4
L		 5789 if (intel_syntax
5790 && i.tm.opcode_modifier.ignoresize
5791 && i.tm.opcode_modifier.no_bsuf)
5792 i.suffix = 0;
5793 else if (!check_byte_reg ())
29b0f896
AM		 5794 return 0;
5795 }
5796 else if (i.suffix == LONG_MNEM_SUFFIX)
5797 {
2eb952a4
L		 5798 if (intel_syntax
5799 && i.tm.opcode_modifier.ignoresize
5800 && i.tm.opcode_modifier.no_lsuf)
5801 i.suffix = 0;
5802 else if (!check_long_reg ())
29b0f896
AM		 5803 return 0;
5804 }
5805 else if (i.suffix == QWORD_MNEM_SUFFIX)
5806 {
955e1e6a
L		 5807 if (intel_syntax
5808 && i.tm.opcode_modifier.ignoresize
5809 && i.tm.opcode_modifier.no_qsuf)
5810 i.suffix = 0;
5811 else if (!check_qword_reg ())
29b0f896
AM		 5812 return 0;
5813 }
5814 else if (i.suffix == WORD_MNEM_SUFFIX)
5815 {
2eb952a4
L		 5816 if (intel_syntax
5817 && i.tm.opcode_modifier.ignoresize
5818 && i.tm.opcode_modifier.no_wsuf)
5819 i.suffix = 0;
5820 else if (!check_word_reg ())
29b0f896
AM		 5821 return 0;
5822 }
40fb9820 5823 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5824 /* Do nothing if the instruction is going to ignore the prefix. */
5825 ;
5826 else
5827 abort ();
5828 }
40fb9820 5829 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5830 && !i.suffix
5831 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5832 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5833 {
5834 i.suffix = stackop_size;
5835 }
9306ca4a
JB		 5836 else if (intel_syntax
5837 && !i.suffix
40fb9820
L		 5838 && (i.tm.operand_types[0].bitfield.jumpabsolute
5839 || i.tm.opcode_modifier.jumpbyte
5840 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5841 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5842 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5843 {
5844 switch (flag_code)
5845 {
5846 case CODE_64BIT:
40fb9820 5847 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5848 {
5849 i.suffix = QWORD_MNEM_SUFFIX;
5850 break;
5851 }
1a0670f3 5852 /* Fall through. */
9306ca4a 5853 case CODE_32BIT:
40fb9820 5854 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5855 i.suffix = LONG_MNEM_SUFFIX;
5856 break;
5857 case CODE_16BIT:
40fb9820 5858 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5859 i.suffix = WORD_MNEM_SUFFIX;
5860 break;
5861 }
5862 }
252b5132 5863
9306ca4a 5864 if (!i.suffix)
29b0f896 5865 {
9306ca4a
JB		 5866 if (!intel_syntax)
5867 {
40fb9820 5868 if (i.tm.opcode_modifier.w)
9306ca4a 5869 {
4eed87de
AM		 5870 as_bad (_("no instruction mnemonic suffix given and "
5871 "no register operands; can't size instruction"));
9306ca4a
JB		 5872 return 0;
5873 }
5874 }
5875 else
5876 {
40fb9820 5877 unsigned int suffixes;
7ab9ffdd 5878
40fb9820
L		 5879 suffixes = !i.tm.opcode_modifier.no_bsuf;
5880 if (!i.tm.opcode_modifier.no_wsuf)
5881 suffixes |= 1 << 1;
5882 if (!i.tm.opcode_modifier.no_lsuf)
5883 suffixes |= 1 << 2;
fc4adea1 5884 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5885 suffixes |= 1 << 3;
5886 if (!i.tm.opcode_modifier.no_ssuf)
5887 suffixes |= 1 << 4;
c2b9da16 5888 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
40fb9820
L		 5889 suffixes |= 1 << 5;
5890
5891 /* There are more than suffix matches. */
5892 if (i.tm.opcode_modifier.w
9306ca4a 5893 || ((suffixes & (suffixes - 1))
40fb9820
L		 5894 && !i.tm.opcode_modifier.defaultsize
5895 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5896 {
5897 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5898 return 0;
5899 }
5900 }
29b0f896 5901 }
252b5132 5902
d2224064
JB		 5903 /* Change the opcode based on the operand size given by i.suffix. */
5904 switch (i.suffix)
29b0f896 5905 {
d2224064
JB		 5906 /* Size floating point instruction. */
5907 case LONG_MNEM_SUFFIX:
5908 if (i.tm.opcode_modifier.floatmf)
5909 {
5910 i.tm.base_opcode ^= 4;
5911 break;
5912 }
5913 /* fall through */
5914 case WORD_MNEM_SUFFIX:
5915 case QWORD_MNEM_SUFFIX:
29b0f896 5916 /* It's not a byte, select word/dword operation. */
40fb9820 5917 if (i.tm.opcode_modifier.w)
29b0f896 5918 {
40fb9820 5919 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5920 i.tm.base_opcode |= 8;
5921 else
5922 i.tm.base_opcode |= 1;
5923 }
d2224064
JB		 5924 /* fall through */
5925 case SHORT_MNEM_SUFFIX:
29b0f896
AM		 5926 /* Now select between word & dword operations via the operand
5927 size prefix, except for instructions that will ignore this
5928 prefix anyway. */
ca61edf2 5929 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5930 {
ca61edf2
L		 5931 /* The address size override prefix changes the size of the
5932 first operand. */
40fb9820 5933 if ((flag_code == CODE_32BIT
dc821c5f 5934 && i.op->regs[0].reg_type.bitfield.word)
40fb9820 5935 || (flag_code != CODE_32BIT
dc821c5f 5936 && i.op->regs[0].reg_type.bitfield.dword))
cb712a9e
L		 5937 if (!add_prefix (ADDR_PREFIX_OPCODE))
5938 return 0;
5939 }
5940 else if (i.suffix != QWORD_MNEM_SUFFIX
40fb9820
L		 5941 && !i.tm.opcode_modifier.ignoresize
5942 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5943 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5944 || (flag_code == CODE_64BIT
40fb9820 5945 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5946 {
5947 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5948
40fb9820 5949 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5950 prefix = ADDR_PREFIX_OPCODE;
252b5132 5951
29b0f896
AM		 5952 if (!add_prefix (prefix))
5953 return 0;
24eab124 5954 }
252b5132 5955
29b0f896
AM		 5956 /* Set mode64 for an operand. */
5957 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5958 && flag_code == CODE_64BIT
d2224064 5959 && !i.tm.opcode_modifier.norex64
46e883c5 5960 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d2224064
JB		 5961 need rex64. */
5962 && ! (i.operands == 2
5963 && i.tm.base_opcode == 0x90
5964 && i.tm.extension_opcode == None
5965 && operand_type_equal (&i.types [0], &acc64)
5966 && operand_type_equal (&i.types [1], &acc64)))
5967 i.rex |= REX_W;
3e73aa7c 5968
d2224064 5969 break;
29b0f896 5970 }
7ecd2f8b 5971
29b0f896
AM		 5972 return 1;
5973}
3e73aa7c 5974
29b0f896 5975static int
543613e9 5976check_byte_reg (void)
29b0f896
AM		 5977{
5978 int op;
543613e9 5979
29b0f896
AM		 5980 for (op = i.operands; --op >= 0;)
5981 {
dc821c5f
JB		 5982 /* Skip non-register operands. */
5983 if (!i.types[op].bitfield.reg)
5984 continue;
5985
29b0f896
AM		 5986 /* If this is an eight bit register, it's OK. If it's the 16 or
5987 32 bit version of an eight bit register, we will just use the
5988 low portion, and that's OK too. */
dc821c5f 5989 if (i.types[op].bitfield.byte)
29b0f896
AM		 5990 continue;
5991
5a819eb9
JB		 5992 /* I/O port address operands are OK too. */
5993 if (i.tm.operand_types[op].bitfield.inoutportreg)
5994 continue;
5995
9344ff29
L		 5996 /* crc32 doesn't generate this warning. */
5997 if (i.tm.base_opcode == 0xf20f38f0)
5998 continue;
5999
dc821c5f
JB		 6000 if ((i.types[op].bitfield.word
6001 || i.types[op].bitfield.dword
6002 || i.types[op].bitfield.qword)
5a819eb9
JB		 6003 && i.op[op].regs->reg_num < 4
6004 /* Prohibit these changes in 64bit mode, since the lowering
6005 would be more complicated. */
6006 && flag_code != CODE_64BIT)
29b0f896 6007 {
29b0f896 6008#if REGISTER_WARNINGS
5a819eb9 6009 if (!quiet_warnings)
a540244d
L		 6010 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6011 register_prefix,
dc821c5f 6012 (i.op[op].regs + (i.types[op].bitfield.word
29b0f896
AM		 6013 ? REGNAM_AL - REGNAM_AX
6014 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 6015 register_prefix,
29b0f896
AM		 6016 i.op[op].regs->reg_name,
6017 i.suffix);
6018#endif
6019 continue;
6020 }
6021 /* Any other register is bad. */
dc821c5f 6022 if (i.types[op].bitfield.reg
40fb9820 6023 || i.types[op].bitfield.regmmx
1b54b8d7 6024 || i.types[op].bitfield.regsimd
40fb9820
L		 6025 || i.types[op].bitfield.sreg2
6026 || i.types[op].bitfield.sreg3
6027 || i.types[op].bitfield.control
6028 || i.types[op].bitfield.debug
ca0d63fe 6029 || i.types[op].bitfield.test)
29b0f896 6030 {
a540244d
L		 6031 as_bad (_("`%s%s' not allowed with `%s%c'"),
6032 register_prefix,
29b0f896
AM		 6033 i.op[op].regs->reg_name,
6034 i.tm.name,
6035 i.suffix);
6036 return 0;
6037 }
6038 }
6039 return 1;
6040}
6041
6042static int
e3bb37b5 6043check_long_reg (void)
29b0f896
AM		 6044{
6045 int op;
6046
6047 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6048 /* Skip non-register operands. */
6049 if (!i.types[op].bitfield.reg)
6050 continue;
29b0f896
AM		 6051 /* Reject eight bit registers, except where the template requires
6052 them. (eg. movzb) */
dc821c5f
JB		 6053 else if (i.types[op].bitfield.byte
6054 && (i.tm.operand_types[op].bitfield.reg
6055 || i.tm.operand_types[op].bitfield.acc)
6056 && (i.tm.operand_types[op].bitfield.word
6057 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6058 {
a540244d
L		 6059 as_bad (_("`%s%s' not allowed with `%s%c'"),
6060 register_prefix,
29b0f896
AM		 6061 i.op[op].regs->reg_name,
6062 i.tm.name,
6063 i.suffix);
6064 return 0;
6065 }
e4630f71 6066 /* Warn if the e prefix on a general reg is missing. */
29b0f896 6067 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6068 && i.types[op].bitfield.word
6069 && (i.tm.operand_types[op].bitfield.reg
6070 || i.tm.operand_types[op].bitfield.acc)
6071 && i.tm.operand_types[op].bitfield.dword)
29b0f896
AM		 6072 {
6073 /* Prohibit these changes in the 64bit mode, since the
6074 lowering is more complicated. */
6075 if (flag_code == CODE_64BIT)
252b5132 6076 {
2b5d6a91 6077 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6078 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6079 i.suffix);
6080 return 0;
252b5132 6081 }
29b0f896 6082#if REGISTER_WARNINGS
cecf1424
JB		 6083 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6084 register_prefix,
6085 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6086 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 6087#endif
252b5132 6088 }
e4630f71 6089 /* Warn if the r prefix on a general reg is present. */
dc821c5f
JB		 6090 else if (i.types[op].bitfield.qword
6091 && (i.tm.operand_types[op].bitfield.reg
6092 || i.tm.operand_types[op].bitfield.acc)
6093 && i.tm.operand_types[op].bitfield.dword)
252b5132 6094 {
34828aad 6095 if (intel_syntax
ca61edf2 6096 && i.tm.opcode_modifier.toqword
1b54b8d7 6097 && !i.types[0].bitfield.regsimd)
34828aad 6098 {
ca61edf2 6099 /* Convert to QWORD. We want REX byte. */
34828aad
L		 6100 i.suffix = QWORD_MNEM_SUFFIX;
6101 }
6102 else
6103 {
2b5d6a91 6104 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6105 register_prefix, i.op[op].regs->reg_name,
6106 i.suffix);
6107 return 0;
6108 }
29b0f896
AM		 6109 }
6110 return 1;
6111}
252b5132 6112
29b0f896 6113static int
e3bb37b5 6114check_qword_reg (void)
29b0f896
AM		 6115{
6116 int op;
252b5132 6117
29b0f896 6118 for (op = i.operands; --op >= 0; )
dc821c5f
JB		 6119 /* Skip non-register operands. */
6120 if (!i.types[op].bitfield.reg)
6121 continue;
29b0f896
AM		 6122 /* Reject eight bit registers, except where the template requires
6123 them. (eg. movzb) */
dc821c5f
JB		 6124 else if (i.types[op].bitfield.byte
6125 && (i.tm.operand_types[op].bitfield.reg
6126 || i.tm.operand_types[op].bitfield.acc)
6127 && (i.tm.operand_types[op].bitfield.word
6128 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6129 {
a540244d
L		 6130 as_bad (_("`%s%s' not allowed with `%s%c'"),
6131 register_prefix,
29b0f896
AM		 6132 i.op[op].regs->reg_name,
6133 i.tm.name,
6134 i.suffix);
6135 return 0;
6136 }
e4630f71 6137 /* Warn if the r prefix on a general reg is missing. */
dc821c5f
JB		 6138 else if ((i.types[op].bitfield.word
6139 || i.types[op].bitfield.dword)
6140 && (i.tm.operand_types[op].bitfield.reg
6141 || i.tm.operand_types[op].bitfield.acc)
6142 && i.tm.operand_types[op].bitfield.qword)
29b0f896
AM		 6143 {
6144 /* Prohibit these changes in the 64bit mode, since the
6145 lowering is more complicated. */
34828aad 6146 if (intel_syntax
ca61edf2 6147 && i.tm.opcode_modifier.todword
1b54b8d7 6148 && !i.types[0].bitfield.regsimd)
34828aad 6149 {
ca61edf2 6150 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 6151 i.suffix = LONG_MNEM_SUFFIX;
6152 }
6153 else
6154 {
2b5d6a91 6155 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6156 register_prefix, i.op[op].regs->reg_name,
6157 i.suffix);
6158 return 0;
6159 }
252b5132 6160 }
29b0f896
AM		 6161 return 1;
6162}
252b5132 6163
29b0f896 6164static int
e3bb37b5 6165check_word_reg (void)
29b0f896
AM		 6166{
6167 int op;
6168 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6169 /* Skip non-register operands. */
6170 if (!i.types[op].bitfield.reg)
6171 continue;
29b0f896
AM		 6172 /* Reject eight bit registers, except where the template requires
6173 them. (eg. movzb) */
dc821c5f
JB		 6174 else if (i.types[op].bitfield.byte
6175 && (i.tm.operand_types[op].bitfield.reg
6176 || i.tm.operand_types[op].bitfield.acc)
6177 && (i.tm.operand_types[op].bitfield.word
6178 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6179 {
a540244d
L		 6180 as_bad (_("`%s%s' not allowed with `%s%c'"),
6181 register_prefix,
29b0f896
AM		 6182 i.op[op].regs->reg_name,
6183 i.tm.name,
6184 i.suffix);
6185 return 0;
6186 }
e4630f71 6187 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 6188 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6189 && (i.types[op].bitfield.dword
6190 || i.types[op].bitfield.qword)
6191 && (i.tm.operand_types[op].bitfield.reg
6192 || i.tm.operand_types[op].bitfield.acc)
6193 && i.tm.operand_types[op].bitfield.word)
252b5132 6194 {
29b0f896
AM		 6195 /* Prohibit these changes in the 64bit mode, since the
6196 lowering is more complicated. */
6197 if (flag_code == CODE_64BIT)
252b5132 6198 {
2b5d6a91 6199 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6200 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6201 i.suffix);
6202 return 0;
252b5132 6203 }
29b0f896 6204#if REGISTER_WARNINGS
cecf1424
JB		 6205 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6206 register_prefix,
6207 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6208 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 6209#endif
6210 }
6211 return 1;
6212}
252b5132 6213
29b0f896 6214static int
40fb9820 6215update_imm (unsigned int j)
29b0f896 6216{
bc0844ae 6217 i386_operand_type overlap = i.types[j];
40fb9820
L		 6218 if ((overlap.bitfield.imm8
6219 || overlap.bitfield.imm8s
6220 || overlap.bitfield.imm16
6221 || overlap.bitfield.imm32
6222 || overlap.bitfield.imm32s
6223 || overlap.bitfield.imm64)
0dfbf9d7
L		 6224 && !operand_type_equal (&overlap, &imm8)
6225 && !operand_type_equal (&overlap, &imm8s)
6226 && !operand_type_equal (&overlap, &imm16)
6227 && !operand_type_equal (&overlap, &imm32)
6228 && !operand_type_equal (&overlap, &imm32s)
6229 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 6230 {
6231 if (i.suffix)
6232 {
40fb9820
L		 6233 i386_operand_type temp;
6234
0dfbf9d7 6235 operand_type_set (&temp, 0);
7ab9ffdd 6236 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 6237 {
6238 temp.bitfield.imm8 = overlap.bitfield.imm8;
6239 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6240 }
6241 else if (i.suffix == WORD_MNEM_SUFFIX)
6242 temp.bitfield.imm16 = overlap.bitfield.imm16;
6243 else if (i.suffix == QWORD_MNEM_SUFFIX)
6244 {
6245 temp.bitfield.imm64 = overlap.bitfield.imm64;
6246 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6247 }
6248 else
6249 temp.bitfield.imm32 = overlap.bitfield.imm32;
6250 overlap = temp;
29b0f896 6251 }
0dfbf9d7
L		 6252 else if (operand_type_equal (&overlap, &imm16_32_32s)
6253 || operand_type_equal (&overlap, &imm16_32)
6254 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 6255 {
40fb9820 6256 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 6257 overlap = imm16;
40fb9820 6258 else
65da13b5 6259 overlap = imm32s;
29b0f896 6260 }
0dfbf9d7
L		 6261 if (!operand_type_equal (&overlap, &imm8)
6262 && !operand_type_equal (&overlap, &imm8s)
6263 && !operand_type_equal (&overlap, &imm16)
6264 && !operand_type_equal (&overlap, &imm32)
6265 && !operand_type_equal (&overlap, &imm32s)
6266 && !operand_type_equal (&overlap, &imm64))
29b0f896 6267 {
4eed87de
AM		 6268 as_bad (_("no instruction mnemonic suffix given; "
6269 "can't determine immediate size"));
29b0f896
AM		 6270 return 0;
6271 }
6272 }
40fb9820 6273 i.types[j] = overlap;
29b0f896 6274
40fb9820
L		 6275 return 1;
6276}
6277
6278static int
6279finalize_imm (void)
6280{
bc0844ae 6281 unsigned int j, n;
29b0f896 6282
bc0844ae
L		 6283 /* Update the first 2 immediate operands. */
6284 n = i.operands > 2 ? 2 : i.operands;
6285 if (n)
6286 {
6287 for (j = 0; j < n; j++)
6288 if (update_imm (j) == 0)
6289 return 0;
40fb9820 6290
bc0844ae
L		 6291 /* The 3rd operand can't be immediate operand. */
6292 gas_assert (operand_type_check (i.types[2], imm) == 0);
6293 }
29b0f896
AM		 6294
6295 return 1;
6296}
6297
6298static int
e3bb37b5 6299process_operands (void)
29b0f896
AM		 6300{
6301 /* Default segment register this instruction will use for memory
6302 accesses. 0 means unknown. This is only for optimizing out
6303 unnecessary segment overrides. */
6304 const seg_entry *default_seg = 0;
6305
2426c15f 6306 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 6307 {
91d6fa6a
NC		 6308 unsigned int dupl = i.operands;
6309 unsigned int dest = dupl - 1;
9fcfb3d7
L		 6310 unsigned int j;
6311
c0f3af97 6312 /* The destination must be an xmm register. */
9c2799c2 6313 gas_assert (i.reg_operands
91d6fa6a 6314 && MAX_OPERANDS > dupl
7ab9ffdd 6315 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97 6316
1b54b8d7
JB		 6317 if (i.tm.operand_types[0].bitfield.acc
6318 && i.tm.operand_types[0].bitfield.xmmword)
e2ec9d29 6319 {
8cd7925b 6320 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 6321 {
6322 /* Keep xmm0 for instructions with VEX prefix and 3
6323 sources. */
1b54b8d7
JB		 6324 i.tm.operand_types[0].bitfield.acc = 0;
6325 i.tm.operand_types[0].bitfield.regsimd = 1;
c0f3af97
L		 6326 goto duplicate;
6327 }
e2ec9d29 6328 else
c0f3af97
L		 6329 {
6330 /* We remove the first xmm0 and keep the number of
6331 operands unchanged, which in fact duplicates the
6332 destination. */
6333 for (j = 1; j < i.operands; j++)
6334 {
6335 i.op[j - 1] = i.op[j];
6336 i.types[j - 1] = i.types[j];
6337 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6338 }
6339 }
6340 }
6341 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 6342 {
91d6fa6a 6343 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 6344 && (i.tm.opcode_modifier.vexsources
6345 == VEX3SOURCES));
c0f3af97
L		 6346
6347 /* Add the implicit xmm0 for instructions with VEX prefix
6348 and 3 sources. */
6349 for (j = i.operands; j > 0; j--)
6350 {
6351 i.op[j] = i.op[j - 1];
6352 i.types[j] = i.types[j - 1];
6353 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6354 }
6355 i.op[0].regs
6356 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 6357 i.types[0] = regxmm;
c0f3af97
L		 6358 i.tm.operand_types[0] = regxmm;
6359
6360 i.operands += 2;
6361 i.reg_operands += 2;
6362 i.tm.operands += 2;
6363
91d6fa6a 6364 dupl++;
c0f3af97 6365 dest++;
91d6fa6a
NC		 6366 i.op[dupl] = i.op[dest];
6367 i.types[dupl] = i.types[dest];
6368 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6369 }
c0f3af97
L		 6370 else
6371 {
6372duplicate:
6373 i.operands++;
6374 i.reg_operands++;
6375 i.tm.operands++;
6376
91d6fa6a
NC		 6377 i.op[dupl] = i.op[dest];
6378 i.types[dupl] = i.types[dest];
6379 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6380 }
6381
6382 if (i.tm.opcode_modifier.immext)
6383 process_immext ();
6384 }
1b54b8d7
JB		 6385 else if (i.tm.operand_types[0].bitfield.acc
6386 && i.tm.operand_types[0].bitfield.xmmword)
c0f3af97
L		 6387 {
6388 unsigned int j;
6389
9fcfb3d7
L		 6390 for (j = 1; j < i.operands; j++)
6391 {
6392 i.op[j - 1] = i.op[j];
6393 i.types[j - 1] = i.types[j];
6394
6395 /* We need to adjust fields in i.tm since they are used by
6396 build_modrm_byte. */
6397 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6398 }
6399
e2ec9d29
L		 6400 i.operands--;
6401 i.reg_operands--;
e2ec9d29
L		 6402 i.tm.operands--;
6403 }
920d2ddc
IT		 6404 else if (i.tm.opcode_modifier.implicitquadgroup)
6405 {
a477a8c4
JB		 6406 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6407
920d2ddc 6408 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
10c17abd 6409 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
a477a8c4
JB		 6410 regnum = register_number (i.op[1].regs);
6411 first_reg_in_group = regnum & ~3;
6412 last_reg_in_group = first_reg_in_group + 3;
6413 if (regnum != first_reg_in_group)
6414 as_warn (_("source register `%s%s' implicitly denotes"
6415 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6416 register_prefix, i.op[1].regs->reg_name,
6417 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6418 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6419 i.tm.name);
6420 }
e2ec9d29
L		 6421 else if (i.tm.opcode_modifier.regkludge)
6422 {
6423 /* The imul $imm, %reg instruction is converted into
6424 imul $imm, %reg, %reg, and the clr %reg instruction
6425 is converted into xor %reg, %reg. */
6426
6427 unsigned int first_reg_op;
6428
6429 if (operand_type_check (i.types[0], reg))
6430 first_reg_op = 0;
6431 else
6432 first_reg_op = 1;
6433 /* Pretend we saw the extra register operand. */
9c2799c2 6434 gas_assert (i.reg_operands == 1
7ab9ffdd 6435 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6436 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6437 i.types[first_reg_op + 1] = i.types[first_reg_op];
6438 i.operands++;
6439 i.reg_operands++;
29b0f896
AM		 6440 }
6441
40fb9820 6442 if (i.tm.opcode_modifier.shortform)
29b0f896 6443 {
40fb9820
L		 6444 if (i.types[0].bitfield.sreg2
6445 || i.types[0].bitfield.sreg3)
29b0f896 6446 {
4eed87de
AM		 6447 if (i.tm.base_opcode == POP_SEG_SHORT
6448 && i.op[0].regs->reg_num == 1)
29b0f896 6449 {
a87af027 6450 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6451 return 0;
29b0f896 6452 }
4eed87de
AM		 6453 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6454 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6455 i.rex |= REX_B;
4eed87de
AM		 6456 }
6457 else
6458 {
7ab9ffdd 6459 /* The register or float register operand is in operand
85f10a01 6460 0 or 1. */
40fb9820 6461 unsigned int op;
7ab9ffdd 6462
ca0d63fe 6463 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
7ab9ffdd
L		 6464 || operand_type_check (i.types[0], reg))
6465 op = 0;
6466 else
6467 op = 1;
4eed87de
AM		 6468 /* Register goes in low 3 bits of opcode. */
6469 i.tm.base_opcode |= i.op[op].regs->reg_num;
6470 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6471 i.rex |= REX_B;
40fb9820 6472 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6473 {
4eed87de
AM		 6474 /* Warn about some common errors, but press on regardless.
6475 The first case can be generated by gcc (<= 2.8.1). */
6476 if (i.operands == 2)
6477 {
6478 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6479 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6480 register_prefix, i.op[!intel_syntax].regs->reg_name,
6481 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6482 }
6483 else
6484 {
6485 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6486 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6487 register_prefix, i.op[0].regs->reg_name);
4eed87de 6488 }
29b0f896
AM		 6489 }
6490 }
6491 }
40fb9820 6492 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6493 {
6494 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6495 must be put into the modrm byte). Now, we make the modrm and
6496 index base bytes based on all the info we've collected. */
29b0f896
AM		 6497
6498 default_seg = build_modrm_byte ();
6499 }
8a2ed489 6500 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6501 {
6502 default_seg = &ds;
6503 }
40fb9820 6504 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6505 {
6506 /* For the string instructions that allow a segment override
6507 on one of their operands, the default segment is ds. */
6508 default_seg = &ds;
6509 }
6510
75178d9d
L		 6511 if (i.tm.base_opcode == 0x8d /* lea */
6512 && i.seg[0]
6513 && !quiet_warnings)
30123838 6514 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6515
6516 /* If a segment was explicitly specified, and the specified segment
6517 is not the default, use an opcode prefix to select it. If we
6518 never figured out what the default segment is, then default_seg
6519 will be zero at this point, and the specified segment prefix will
6520 always be used. */
29b0f896
AM		 6521 if ((i.seg[0]) && (i.seg[0] != default_seg))
6522 {
6523 if (!add_prefix (i.seg[0]->seg_prefix))
6524 return 0;
6525 }
6526 return 1;
6527}
6528
6529static const seg_entry *
e3bb37b5 6530build_modrm_byte (void)
29b0f896
AM		 6531{
6532 const seg_entry *default_seg = 0;
c0f3af97 6533 unsigned int source, dest;
8cd7925b 6534 int vex_3_sources;
c0f3af97
L		 6535
6536 /* The first operand of instructions with VEX prefix and 3 sources
6537 must be VEX_Imm4. */
8cd7925b 6538 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6539 if (vex_3_sources)
6540 {
91d6fa6a 6541 unsigned int nds, reg_slot;
4c2c6516 6542 expressionS *exp;
c0f3af97 6543
922d8de8 6544 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6545 && i.tm.opcode_modifier.immext)
6546 {
6547 dest = i.operands - 2;
6548 gas_assert (dest == 3);
6549 }
922d8de8 6550 else
a683cc34 6551 dest = i.operands - 1;
c0f3af97 6552 nds = dest - 1;
922d8de8 6553
a683cc34
SP		 6554 /* There are 2 kinds of instructions:
6555 1. 5 operands: 4 register operands or 3 register operands
6556 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6557 VexW0 or VexW1. The destination must be either XMM, YMM or
6558 ZMM register.
a683cc34
SP		 6559 2. 4 operands: 4 register operands or 3 register operands
6560 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6561 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6562 || (i.reg_operands == 3 && i.mem_operands == 1))
6563 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6564 && (i.tm.opcode_modifier.veximmext
6565 || (i.imm_operands == 1
6566 && i.types[0].bitfield.vec_imm4
6567 && (i.tm.opcode_modifier.vexw == VEXW0
6568 || i.tm.opcode_modifier.vexw == VEXW1)
10c17abd 6569 && i.tm.operand_types[dest].bitfield.regsimd)));
a683cc34
SP		 6570
6571 if (i.imm_operands == 0)
6572 {
6573 /* When there is no immediate operand, generate an 8bit
6574 immediate operand to encode the first operand. */
6575 exp = &im_expressions[i.imm_operands++];
6576 i.op[i.operands].imms = exp;
6577 i.types[i.operands] = imm8;
6578 i.operands++;
6579 /* If VexW1 is set, the first operand is the source and
6580 the second operand is encoded in the immediate operand. */
6581 if (i.tm.opcode_modifier.vexw == VEXW1)
6582 {
6583 source = 0;
6584 reg_slot = 1;
6585 }
6586 else
6587 {
6588 source = 1;
6589 reg_slot = 0;
6590 }
6591
6592 /* FMA swaps REG and NDS. */
6593 if (i.tm.cpu_flags.bitfield.cpufma)
6594 {
6595 unsigned int tmp;
6596 tmp = reg_slot;
6597 reg_slot = nds;
6598 nds = tmp;
6599 }
6600
10c17abd 6601 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
a683cc34 6602 exp->X_op = O_constant;
4c692bc7 6603 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6604 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6605 }
922d8de8 6606 else
a683cc34
SP		 6607 {
6608 unsigned int imm_slot;
6609
6610 if (i.tm.opcode_modifier.vexw == VEXW0)
6611 {
6612 /* If VexW0 is set, the third operand is the source and
6613 the second operand is encoded in the immediate
6614 operand. */
6615 source = 2;
6616 reg_slot = 1;
6617 }
6618 else
6619 {
6620 /* VexW1 is set, the second operand is the source and
6621 the third operand is encoded in the immediate
6622 operand. */
6623 source = 1;
6624 reg_slot = 2;
6625 }
6626
6627 if (i.tm.opcode_modifier.immext)
6628 {
33eaf5de 6629 /* When ImmExt is set, the immediate byte is the last
a683cc34
SP		 6630 operand. */
6631 imm_slot = i.operands - 1;
6632 source--;
6633 reg_slot--;
6634 }
6635 else
6636 {
6637 imm_slot = 0;
6638
6639 /* Turn on Imm8 so that output_imm will generate it. */
6640 i.types[imm_slot].bitfield.imm8 = 1;
6641 }
6642
10c17abd 6643 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
a683cc34 6644 i.op[imm_slot].imms->X_add_number
4c692bc7 6645 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6646 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6647 }
6648
10c17abd 6649 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
dae39acc 6650 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6651 }
6652 else
6653 source = dest = 0;
29b0f896
AM		 6654
6655 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6656 implicit registers do not count. If there are 3 register
6657 operands, it must be a instruction with VexNDS. For a
6658 instruction with VexNDD, the destination register is encoded
6659 in VEX prefix. If there are 4 register operands, it must be
6660 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6661 if (i.mem_operands == 0
6662 && ((i.reg_operands == 2
2426c15f 6663 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6664 || (i.reg_operands == 3
2426c15f 6665 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6666 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6667 {
cab737b9
L		 6668 switch (i.operands)
6669 {
6670 case 2:
6671 source = 0;
6672 break;
6673 case 3:
c81128dc
L		 6674 /* When there are 3 operands, one of them may be immediate,
6675 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6676 the first operand must be shift count register (cl) or it
6677 is an instruction with VexNDS. */
9c2799c2 6678 gas_assert (i.imm_operands == 1
7ab9ffdd 6679 || (i.imm_operands == 0
2426c15f 6680 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6681 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6682 if (operand_type_check (i.types[0], imm)
6683 || i.types[0].bitfield.shiftcount)
6684 source = 1;
6685 else
6686 source = 0;
cab737b9
L		 6687 break;
6688 case 4:
368d64cc
L		 6689 /* When there are 4 operands, the first two must be 8bit
6690 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6691 one.
6692
6693 For instructions with VexNDS, if the first operand
6694 an imm8, the source operand is the 2nd one. If the last
6695 operand is imm8, the source operand is the first one. */
9c2799c2 6696 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6697 && i.types[0].bitfield.imm8
6698 && i.types[1].bitfield.imm8)
2426c15f 6699 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6700 && i.imm_operands == 1
6701 && (i.types[0].bitfield.imm8
43234a1e
L		 6702 || i.types[i.operands - 1].bitfield.imm8
6703 || i.rounding)));
9f2670f2
L		 6704 if (i.imm_operands == 2)
6705 source = 2;
6706 else
c0f3af97
L		 6707 {
6708 if (i.types[0].bitfield.imm8)
6709 source = 1;
6710 else
6711 source = 0;
6712 }
c0f3af97
L		 6713 break;
6714 case 5:
e771e7c9 6715 if (is_evex_encoding (&i.tm))
43234a1e
L		 6716 {
6717 /* For EVEX instructions, when there are 5 operands, the
6718 first one must be immediate operand. If the second one
6719 is immediate operand, the source operand is the 3th
6720 one. If the last one is immediate operand, the source
6721 operand is the 2nd one. */
6722 gas_assert (i.imm_operands == 2
6723 && i.tm.opcode_modifier.sae
6724 && operand_type_check (i.types[0], imm));
6725 if (operand_type_check (i.types[1], imm))
6726 source = 2;
6727 else if (operand_type_check (i.types[4], imm))
6728 source = 1;
6729 else
6730 abort ();
6731 }
cab737b9
L		 6732 break;
6733 default:
6734 abort ();
6735 }
6736
c0f3af97
L		 6737 if (!vex_3_sources)
6738 {
6739 dest = source + 1;
6740
43234a1e
L		 6741 /* RC/SAE operand could be between DEST and SRC. That happens
6742 when one operand is GPR and the other one is XMM/YMM/ZMM
6743 register. */
6744 if (i.rounding && i.rounding->operand == (int) dest)
6745 dest++;
6746
2426c15f 6747 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6748 {
43234a1e 6749 /* For instructions with VexNDS, the register-only source
c5d0745b 6750 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
43234a1e
L		 6751 register. It is encoded in VEX prefix. We need to
6752 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6753
6754 i386_operand_type op;
6755 unsigned int vvvv;
6756
6757 /* Check register-only source operand when two source
6758 operands are swapped. */
6759 if (!i.tm.operand_types[source].bitfield.baseindex
6760 && i.tm.operand_types[dest].bitfield.baseindex)
6761 {
6762 vvvv = source;
6763 source = dest;
6764 }
6765 else
6766 vvvv = dest;
6767
6768 op = i.tm.operand_types[vvvv];
fa99fab2 6769 op.bitfield.regmem = 0;
c0f3af97 6770 if ((dest + 1) >= i.operands
dc821c5f
JB		 6771 || ((!op.bitfield.reg
6772 || (!op.bitfield.dword && !op.bitfield.qword))
10c17abd 6773 && !op.bitfield.regsimd
43234a1e 6774 && !operand_type_equal (&op, &regmask)))
c0f3af97 6775 abort ();
f12dc422 6776 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6777 dest++;
6778 }
6779 }
29b0f896
AM		 6780
6781 i.rm.mode = 3;
6782 /* One of the register operands will be encoded in the i.tm.reg
6783 field, the other in the combined i.tm.mode and i.tm.regmem
6784 fields. If no form of this instruction supports a memory
6785 destination operand, then we assume the source operand may
6786 sometimes be a memory operand and so we need to store the
6787 destination in the i.rm.reg field. */
40fb9820
L		 6788 if (!i.tm.operand_types[dest].bitfield.regmem
6789 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6790 {
6791 i.rm.reg = i.op[dest].regs->reg_num;
6792 i.rm.regmem = i.op[source].regs->reg_num;
6793 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6794 i.rex |= REX_R;
43234a1e
L		 6795 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6796 i.vrex |= REX_R;
29b0f896 6797 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6798 i.rex |= REX_B;
43234a1e
L		 6799 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6800 i.vrex |= REX_B;
29b0f896
AM		 6801 }
6802 else
6803 {
6804 i.rm.reg = i.op[source].regs->reg_num;
6805 i.rm.regmem = i.op[dest].regs->reg_num;
6806 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6807 i.rex |= REX_B;
43234a1e
L		 6808 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6809 i.vrex |= REX_B;
29b0f896 6810 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6811 i.rex |= REX_R;
43234a1e
L		 6812 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6813 i.vrex |= REX_R;
29b0f896 6814 }
161a04f6 6815 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6816 {
40fb9820
L		 6817 if (!i.types[0].bitfield.control
6818 && !i.types[1].bitfield.control)
c4a530c5 6819 abort ();
161a04f6 6820 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6821 add_prefix (LOCK_PREFIX_OPCODE);
6822 }
29b0f896
AM		 6823 }
6824 else
6825 { /* If it's not 2 reg operands... */
c0f3af97
L		 6826 unsigned int mem;
6827
29b0f896
AM		 6828 if (i.mem_operands)
6829 {
6830 unsigned int fake_zero_displacement = 0;
99018f42 6831 unsigned int op;
4eed87de 6832
7ab9ffdd
L		 6833 for (op = 0; op < i.operands; op++)
6834 if (operand_type_check (i.types[op], anymem))
6835 break;
7ab9ffdd 6836 gas_assert (op < i.operands);
29b0f896 6837
6c30d220
L		 6838 if (i.tm.opcode_modifier.vecsib)
6839 {
6840 if (i.index_reg->reg_num == RegEiz
6841 || i.index_reg->reg_num == RegRiz)
6842 abort ();
6843
6844 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6845 if (!i.base_reg)
6846 {
6847 i.sib.base = NO_BASE_REGISTER;
6848 i.sib.scale = i.log2_scale_factor;
6849 i.types[op].bitfield.disp8 = 0;
6850 i.types[op].bitfield.disp16 = 0;
6851 i.types[op].bitfield.disp64 = 0;
43083a50 6852 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6c30d220
L		 6853 {
6854 /* Must be 32 bit */
6855 i.types[op].bitfield.disp32 = 1;
6856 i.types[op].bitfield.disp32s = 0;
6857 }
6858 else
6859 {
6860 i.types[op].bitfield.disp32 = 0;
6861 i.types[op].bitfield.disp32s = 1;
6862 }
6863 }
6864 i.sib.index = i.index_reg->reg_num;
6865 if ((i.index_reg->reg_flags & RegRex) != 0)
6866 i.rex |= REX_X;
43234a1e
L		 6867 if ((i.index_reg->reg_flags & RegVRex) != 0)
6868 i.vrex |= REX_X;
6c30d220
L		 6869 }
6870
29b0f896
AM		 6871 default_seg = &ds;
6872
6873 if (i.base_reg == 0)
6874 {
6875 i.rm.mode = 0;
6876 if (!i.disp_operands)
9bb129e8 6877 fake_zero_displacement = 1;
29b0f896
AM		 6878 if (i.index_reg == 0)
6879 {
73053c1f
JB		 6880 i386_operand_type newdisp;
6881
6c30d220 6882 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6883 /* Operand is just <disp> */
20f0a1fc 6884 if (flag_code == CODE_64BIT)
29b0f896
AM		 6885 {
6886 /* 64bit mode overwrites the 32bit absolute
6887 addressing by RIP relative addressing and
6888 absolute addressing is encoded by one of the
6889 redundant SIB forms. */
6890 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6891 i.sib.base = NO_BASE_REGISTER;
6892 i.sib.index = NO_INDEX_REGISTER;
73053c1f 6893 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
20f0a1fc 6894 }
fc225355
L		 6895 else if ((flag_code == CODE_16BIT)
6896 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6897 {
6898 i.rm.regmem = NO_BASE_REGISTER_16;
73053c1f 6899 newdisp = disp16;
20f0a1fc
NC		 6900 }
6901 else
6902 {
6903 i.rm.regmem = NO_BASE_REGISTER;
73053c1f 6904 newdisp = disp32;
29b0f896 6905 }
73053c1f
JB		 6906 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6907 i.types[op] = operand_type_or (i.types[op], newdisp);
29b0f896 6908 }
6c30d220 6909 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6910 {
6c30d220 6911 /* !i.base_reg && i.index_reg */
db51cc60
L		 6912 if (i.index_reg->reg_num == RegEiz
6913 || i.index_reg->reg_num == RegRiz)
6914 i.sib.index = NO_INDEX_REGISTER;
6915 else
6916 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6917 i.sib.base = NO_BASE_REGISTER;
6918 i.sib.scale = i.log2_scale_factor;
6919 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 6920 i.types[op].bitfield.disp8 = 0;
6921 i.types[op].bitfield.disp16 = 0;
6922 i.types[op].bitfield.disp64 = 0;
43083a50 6923 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
40fb9820
L		 6924 {
6925 /* Must be 32 bit */
6926 i.types[op].bitfield.disp32 = 1;
6927 i.types[op].bitfield.disp32s = 0;
6928 }
29b0f896 6929 else
40fb9820
L		 6930 {
6931 i.types[op].bitfield.disp32 = 0;
6932 i.types[op].bitfield.disp32s = 1;
6933 }
29b0f896 6934 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6935 i.rex |= REX_X;
29b0f896
AM		 6936 }
6937 }
6938 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6939 else if (i.base_reg->reg_num == RegRip ||
6940 i.base_reg->reg_num == RegEip)
29b0f896 6941 {
6c30d220 6942 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6943 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6944 i.types[op].bitfield.disp8 = 0;
6945 i.types[op].bitfield.disp16 = 0;
6946 i.types[op].bitfield.disp32 = 0;
6947 i.types[op].bitfield.disp32s = 1;
6948 i.types[op].bitfield.disp64 = 0;
71903a11 6949 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6950 if (! i.disp_operands)
6951 fake_zero_displacement = 1;
29b0f896 6952 }
dc821c5f 6953 else if (i.base_reg->reg_type.bitfield.word)
29b0f896 6954 {
6c30d220 6955 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6956 switch (i.base_reg->reg_num)
6957 {
6958 case 3: /* (%bx) */
6959 if (i.index_reg == 0)
6960 i.rm.regmem = 7;
6961 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6962 i.rm.regmem = i.index_reg->reg_num - 6;
6963 break;
6964 case 5: /* (%bp) */
6965 default_seg = &ss;
6966 if (i.index_reg == 0)
6967 {
6968 i.rm.regmem = 6;
40fb9820 6969 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6970 {
6971 /* fake (%bp) into 0(%bp) */
b5014f7a 6972 i.types[op].bitfield.disp8 = 1;
252b5132 6973 fake_zero_displacement = 1;
29b0f896
AM		 6974 }
6975 }
6976 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6977 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6978 break;
6979 default: /* (%si) -> 4 or (%di) -> 5 */
6980 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6981 }
6982 i.rm.mode = mode_from_disp_size (i.types[op]);
6983 }
6984 else /* i.base_reg and 32/64 bit mode */
6985 {
6986 if (flag_code == CODE_64BIT
40fb9820
L		 6987 && operand_type_check (i.types[op], disp))
6988 {
73053c1f
JB		 6989 i.types[op].bitfield.disp16 = 0;
6990 i.types[op].bitfield.disp64 = 0;
40fb9820 6991 if (i.prefix[ADDR_PREFIX] == 0)
73053c1f
JB		 6992 {
6993 i.types[op].bitfield.disp32 = 0;
6994 i.types[op].bitfield.disp32s = 1;
6995 }
40fb9820 6996 else
73053c1f
JB		 6997 {
6998 i.types[op].bitfield.disp32 = 1;
6999 i.types[op].bitfield.disp32s = 0;
7000 }
40fb9820 7001 }
20f0a1fc 7002
6c30d220
L		 7003 if (!i.tm.opcode_modifier.vecsib)
7004 i.rm.regmem = i.base_reg->reg_num;
29b0f896 7005 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 7006 i.rex |= REX_B;
29b0f896
AM		 7007 i.sib.base = i.base_reg->reg_num;
7008 /* x86-64 ignores REX prefix bit here to avoid decoder
7009 complications. */
848930b2
JB		 7010 if (!(i.base_reg->reg_flags & RegRex)
7011 && (i.base_reg->reg_num == EBP_REG_NUM
7012 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 7013 default_seg = &ss;
848930b2 7014 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 7015 {
848930b2 7016 fake_zero_displacement = 1;
b5014f7a 7017 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 7018 }
7019 i.sib.scale = i.log2_scale_factor;
7020 if (i.index_reg == 0)
7021 {
6c30d220 7022 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 7023 /* <disp>(%esp) becomes two byte modrm with no index
7024 register. We've already stored the code for esp
7025 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7026 Any base register besides %esp will not use the
7027 extra modrm byte. */
7028 i.sib.index = NO_INDEX_REGISTER;
29b0f896 7029 }
6c30d220 7030 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 7031 {
db51cc60
L		 7032 if (i.index_reg->reg_num == RegEiz
7033 || i.index_reg->reg_num == RegRiz)
7034 i.sib.index = NO_INDEX_REGISTER;
7035 else
7036 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 7037 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7038 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 7039 i.rex |= REX_X;
29b0f896 7040 }
67a4f2b7
AO		 7041
7042 if (i.disp_operands
7043 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7044 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7045 i.rm.mode = 0;
7046 else
a501d77e
L		 7047 {
7048 if (!fake_zero_displacement
7049 && !i.disp_operands
7050 && i.disp_encoding)
7051 {
7052 fake_zero_displacement = 1;
7053 if (i.disp_encoding == disp_encoding_8bit)
7054 i.types[op].bitfield.disp8 = 1;
7055 else
7056 i.types[op].bitfield.disp32 = 1;
7057 }
7058 i.rm.mode = mode_from_disp_size (i.types[op]);
7059 }
29b0f896 7060 }
252b5132 7061
29b0f896
AM		 7062 if (fake_zero_displacement)
7063 {
7064 /* Fakes a zero displacement assuming that i.types[op]
7065 holds the correct displacement size. */
7066 expressionS *exp;
7067
9c2799c2 7068 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 7069 exp = &disp_expressions[i.disp_operands++];
7070 i.op[op].disps = exp;
7071 exp->X_op = O_constant;
7072 exp->X_add_number = 0;
7073 exp->X_add_symbol = (symbolS *) 0;
7074 exp->X_op_symbol = (symbolS *) 0;
7075 }
c0f3af97
L		 7076
7077 mem = op;
29b0f896 7078 }
c0f3af97
L		 7079 else
7080 mem = ~0;
252b5132 7081
8c43a48b 7082 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 7083 {
7084 if (operand_type_check (i.types[0], imm))
7085 i.vex.register_specifier = NULL;
7086 else
7087 {
7088 /* VEX.vvvv encodes one of the sources when the first
7089 operand is not an immediate. */
1ef99a7b 7090 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7091 i.vex.register_specifier = i.op[0].regs;
7092 else
7093 i.vex.register_specifier = i.op[1].regs;
7094 }
7095
7096 /* Destination is a XMM register encoded in the ModRM.reg
7097 and VEX.R bit. */
7098 i.rm.reg = i.op[2].regs->reg_num;
7099 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7100 i.rex |= REX_R;
7101
7102 /* ModRM.rm and VEX.B encodes the other source. */
7103 if (!i.mem_operands)
7104 {
7105 i.rm.mode = 3;
7106
1ef99a7b 7107 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7108 i.rm.regmem = i.op[1].regs->reg_num;
7109 else
7110 i.rm.regmem = i.op[0].regs->reg_num;
7111
7112 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7113 i.rex |= REX_B;
7114 }
7115 }
2426c15f 7116 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 7117 {
7118 i.vex.register_specifier = i.op[2].regs;
7119 if (!i.mem_operands)
7120 {
7121 i.rm.mode = 3;
7122 i.rm.regmem = i.op[1].regs->reg_num;
7123 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7124 i.rex |= REX_B;
7125 }
7126 }
29b0f896
AM		 7127 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7128 (if any) based on i.tm.extension_opcode. Again, we must be
7129 careful to make sure that segment/control/debug/test/MMX
7130 registers are coded into the i.rm.reg field. */
f88c9eb0 7131 else if (i.reg_operands)
29b0f896 7132 {
99018f42 7133 unsigned int op;
7ab9ffdd
L		 7134 unsigned int vex_reg = ~0;
7135
7136 for (op = 0; op < i.operands; op++)
dc821c5f 7137 if (i.types[op].bitfield.reg
7ab9ffdd 7138 || i.types[op].bitfield.regmmx
1b54b8d7 7139 || i.types[op].bitfield.regsimd
7e8b059b 7140 || i.types[op].bitfield.regbnd
43234a1e 7141 || i.types[op].bitfield.regmask
7ab9ffdd
L		 7142 || i.types[op].bitfield.sreg2
7143 || i.types[op].bitfield.sreg3
7144 || i.types[op].bitfield.control
7145 || i.types[op].bitfield.debug
7146 || i.types[op].bitfield.test)
7147 break;
c0209578 7148
7ab9ffdd
L		 7149 if (vex_3_sources)
7150 op = dest;
2426c15f 7151 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 7152 {
7153 /* For instructions with VexNDS, the register-only
7154 source operand is encoded in VEX prefix. */
7155 gas_assert (mem != (unsigned int) ~0);
c0f3af97 7156
7ab9ffdd 7157 if (op > mem)
c0f3af97 7158 {
7ab9ffdd
L		 7159 vex_reg = op++;
7160 gas_assert (op < i.operands);
c0f3af97
L		 7161 }
7162 else
c0f3af97 7163 {
f12dc422
L		 7164 /* Check register-only source operand when two source
7165 operands are swapped. */
7166 if (!i.tm.operand_types[op].bitfield.baseindex
7167 && i.tm.operand_types[op + 1].bitfield.baseindex)
7168 {
7169 vex_reg = op;
7170 op += 2;
7171 gas_assert (mem == (vex_reg + 1)
7172 && op < i.operands);
7173 }
7174 else
7175 {
7176 vex_reg = op + 1;
7177 gas_assert (vex_reg < i.operands);
7178 }
c0f3af97 7179 }
7ab9ffdd 7180 }
2426c15f 7181 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 7182 {
f12dc422 7183 /* For instructions with VexNDD, the register destination
7ab9ffdd 7184 is encoded in VEX prefix. */
f12dc422
L		 7185 if (i.mem_operands == 0)
7186 {
7187 /* There is no memory operand. */
7188 gas_assert ((op + 2) == i.operands);
7189 vex_reg = op + 1;
7190 }
7191 else
8d63c93e 7192 {
ed438a93
JB		 7193 /* There are only 2 non-immediate operands. */
7194 gas_assert (op < i.imm_operands + 2
7195 && i.operands == i.imm_operands + 2);
7196 vex_reg = i.imm_operands + 1;
f12dc422 7197 }
7ab9ffdd
L		 7198 }
7199 else
7200 gas_assert (op < i.operands);
99018f42 7201
7ab9ffdd
L		 7202 if (vex_reg != (unsigned int) ~0)
7203 {
f12dc422 7204 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 7205
dc821c5f
JB		 7206 if ((!type->bitfield.reg
7207 || (!type->bitfield.dword && !type->bitfield.qword))
10c17abd 7208 && !type->bitfield.regsimd
43234a1e 7209 && !operand_type_equal (type, &regmask))
7ab9ffdd 7210 abort ();
f88c9eb0 7211
7ab9ffdd
L		 7212 i.vex.register_specifier = i.op[vex_reg].regs;
7213 }
7214
1b9f0c97
L		 7215 /* Don't set OP operand twice. */
7216 if (vex_reg != op)
7ab9ffdd 7217 {
1b9f0c97
L		 7218 /* If there is an extension opcode to put here, the
7219 register number must be put into the regmem field. */
7220 if (i.tm.extension_opcode != None)
7221 {
7222 i.rm.regmem = i.op[op].regs->reg_num;
7223 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7224 i.rex |= REX_B;
43234a1e
L		 7225 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7226 i.vrex |= REX_B;
1b9f0c97
L		 7227 }
7228 else
7229 {
7230 i.rm.reg = i.op[op].regs->reg_num;
7231 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7232 i.rex |= REX_R;
43234a1e
L		 7233 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7234 i.vrex |= REX_R;
1b9f0c97 7235 }
7ab9ffdd 7236 }
252b5132 7237
29b0f896
AM		 7238 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7239 must set it to 3 to indicate this is a register operand
7240 in the regmem field. */
7241 if (!i.mem_operands)
7242 i.rm.mode = 3;
7243 }
252b5132 7244
29b0f896 7245 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 7246 if (i.tm.extension_opcode != None)
29b0f896
AM		 7247 i.rm.reg = i.tm.extension_opcode;
7248 }
7249 return default_seg;
7250}
252b5132 7251
29b0f896 7252static void
e3bb37b5 7253output_branch (void)
29b0f896
AM		 7254{
7255 char *p;
f8a5c266 7256 int size;
29b0f896
AM		 7257 int code16;
7258 int prefix;
7259 relax_substateT subtype;
7260 symbolS *sym;
7261 offsetT off;
7262
f8a5c266 7263 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 7264 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 7265
7266 prefix = 0;
7267 if (i.prefix[DATA_PREFIX] != 0)
252b5132 7268 {
29b0f896
AM		 7269 prefix = 1;
7270 i.prefixes -= 1;
7271 code16 ^= CODE16;
252b5132 7272 }
29b0f896
AM		 7273 /* Pentium4 branch hints. */
7274 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7275 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 7276 {
29b0f896
AM		 7277 prefix++;
7278 i.prefixes--;
7279 }
7280 if (i.prefix[REX_PREFIX] != 0)
7281 {
7282 prefix++;
7283 i.prefixes--;
2f66722d
AM		 7284 }
7285
7e8b059b
L		 7286 /* BND prefixed jump. */
7287 if (i.prefix[BND_PREFIX] != 0)
7288 {
7289 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7290 i.prefixes -= 1;
7291 }
7292
29b0f896
AM		 7293 if (i.prefixes != 0 && !intel_syntax)
7294 as_warn (_("skipping prefixes on this instruction"));
7295
7296 /* It's always a symbol; End frag & setup for relax.
7297 Make sure there is enough room in this frag for the largest
7298 instruction we may generate in md_convert_frag. This is 2
7299 bytes for the opcode and room for the prefix and largest
7300 displacement. */
7301 frag_grow (prefix + 2 + 4);
7302 /* Prefix and 1 opcode byte go in fr_fix. */
7303 p = frag_more (prefix + 1);
7304 if (i.prefix[DATA_PREFIX] != 0)
7305 *p++ = DATA_PREFIX_OPCODE;
7306 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7307 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7308 *p++ = i.prefix[SEG_PREFIX];
7309 if (i.prefix[REX_PREFIX] != 0)
7310 *p++ = i.prefix[REX_PREFIX];
7311 *p = i.tm.base_opcode;
7312
7313 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 7314 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 7315 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 7316 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 7317 else
f8a5c266 7318 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 7319 subtype |= code16;
3e73aa7c 7320
29b0f896
AM		 7321 sym = i.op[0].disps->X_add_symbol;
7322 off = i.op[0].disps->X_add_number;
3e73aa7c 7323
29b0f896
AM		 7324 if (i.op[0].disps->X_op != O_constant
7325 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7326 {
29b0f896
AM		 7327 /* Handle complex expressions. */
7328 sym = make_expr_symbol (i.op[0].disps);
7329 off = 0;
7330 }
3e73aa7c 7331
29b0f896
AM		 7332 /* 1 possible extra opcode + 4 byte displacement go in var part.
7333 Pass reloc in fr_var. */
d258b828 7334 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7335}
3e73aa7c 7336
bd7ab16b
L		 7337#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7338/* Return TRUE iff PLT32 relocation should be used for branching to
7339 symbol S. */
7340
7341static bfd_boolean
7342need_plt32_p (symbolS *s)
7343{
7344 /* PLT32 relocation is ELF only. */
7345 if (!IS_ELF)
7346 return FALSE;
7347
7348 /* Since there is no need to prepare for PLT branch on x86-64, we
7349 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7350 be used as a marker for 32-bit PC-relative branches. */
7351 if (!object_64bit)
7352 return FALSE;
7353
7354 /* Weak or undefined symbol need PLT32 relocation. */
7355 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7356 return TRUE;
7357
7358 /* Non-global symbol doesn't need PLT32 relocation. */
7359 if (! S_IS_EXTERNAL (s))
7360 return FALSE;
7361
7362 /* Other global symbols need PLT32 relocation. NB: Symbol with
7363 non-default visibilities are treated as normal global symbol
7364 so that PLT32 relocation can be used as a marker for 32-bit
7365 PC-relative branches. It is useful for linker relaxation. */
7366 return TRUE;
7367}
7368#endif
7369
29b0f896 7370static void
e3bb37b5 7371output_jump (void)
29b0f896
AM		 7372{
7373 char *p;
7374 int size;
3e02c1cc 7375 fixS *fixP;
bd7ab16b 7376 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
29b0f896 7377
40fb9820 7378 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7379 {
7380 /* This is a loop or jecxz type instruction. */
7381 size = 1;
7382 if (i.prefix[ADDR_PREFIX] != 0)
7383 {
7384 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7385 i.prefixes -= 1;
7386 }
7387 /* Pentium4 branch hints. */
7388 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7389 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7390 {
7391 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7392 i.prefixes--;
3e73aa7c
JH		 7393 }
7394 }
29b0f896
AM		 7395 else
7396 {
7397 int code16;
3e73aa7c 7398
29b0f896
AM		 7399 code16 = 0;
7400 if (flag_code == CODE_16BIT)
7401 code16 = CODE16;
3e73aa7c 7402
29b0f896
AM		 7403 if (i.prefix[DATA_PREFIX] != 0)
7404 {
7405 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7406 i.prefixes -= 1;
7407 code16 ^= CODE16;
7408 }
252b5132 7409
29b0f896
AM		 7410 size = 4;
7411 if (code16)
7412 size = 2;
7413 }
9fcc94b6 7414
29b0f896
AM		 7415 if (i.prefix[REX_PREFIX] != 0)
7416 {
7417 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7418 i.prefixes -= 1;
7419 }
252b5132 7420
7e8b059b
L		 7421 /* BND prefixed jump. */
7422 if (i.prefix[BND_PREFIX] != 0)
7423 {
7424 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7425 i.prefixes -= 1;
7426 }
7427
29b0f896
AM		 7428 if (i.prefixes != 0 && !intel_syntax)
7429 as_warn (_("skipping prefixes on this instruction"));
e0890092 7430
42164a71
L		 7431 p = frag_more (i.tm.opcode_length + size);
7432 switch (i.tm.opcode_length)
7433 {
7434 case 2:
7435 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7436 /* Fall through. */
42164a71
L		 7437 case 1:
7438 *p++ = i.tm.base_opcode;
7439 break;
7440 default:
7441 abort ();
7442 }
e0890092 7443
bd7ab16b
L		 7444#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7445 if (size == 4
7446 && jump_reloc == NO_RELOC
7447 && need_plt32_p (i.op[0].disps->X_add_symbol))
7448 jump_reloc = BFD_RELOC_X86_64_PLT32;
7449#endif
7450
7451 jump_reloc = reloc (size, 1, 1, jump_reloc);
7452
3e02c1cc 7453 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
bd7ab16b 7454 i.op[0].disps, 1, jump_reloc);
3e02c1cc
AM		 7455
7456 /* All jumps handled here are signed, but don't use a signed limit
7457 check for 32 and 16 bit jumps as we want to allow wrap around at
7458 4G and 64k respectively. */
7459 if (size == 1)
7460 fixP->fx_signed = 1;
29b0f896 7461}
e0890092 7462
29b0f896 7463static void
e3bb37b5 7464output_interseg_jump (void)
29b0f896
AM		 7465{
7466 char *p;
7467 int size;
7468 int prefix;
7469 int code16;
252b5132 7470
29b0f896
AM		 7471 code16 = 0;
7472 if (flag_code == CODE_16BIT)
7473 code16 = CODE16;
a217f122 7474
29b0f896
AM		 7475 prefix = 0;
7476 if (i.prefix[DATA_PREFIX] != 0)
7477 {
7478 prefix = 1;
7479 i.prefixes -= 1;
7480 code16 ^= CODE16;
7481 }
7482 if (i.prefix[REX_PREFIX] != 0)
7483 {
7484 prefix++;
7485 i.prefixes -= 1;
7486 }
252b5132 7487
29b0f896
AM		 7488 size = 4;
7489 if (code16)
7490 size = 2;
252b5132 7491
29b0f896
AM		 7492 if (i.prefixes != 0 && !intel_syntax)
7493 as_warn (_("skipping prefixes on this instruction"));
252b5132 7494
29b0f896
AM		 7495 /* 1 opcode; 2 segment; offset */
7496 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7497
29b0f896
AM		 7498 if (i.prefix[DATA_PREFIX] != 0)
7499 *p++ = DATA_PREFIX_OPCODE;
252b5132 7500
29b0f896
AM		 7501 if (i.prefix[REX_PREFIX] != 0)
7502 *p++ = i.prefix[REX_PREFIX];
252b5132 7503
29b0f896
AM		 7504 *p++ = i.tm.base_opcode;
7505 if (i.op[1].imms->X_op == O_constant)
7506 {
7507 offsetT n = i.op[1].imms->X_add_number;
252b5132 7508
29b0f896
AM		 7509 if (size == 2
7510 && !fits_in_unsigned_word (n)
7511 && !fits_in_signed_word (n))
7512 {
7513 as_bad (_("16-bit jump out of range"));
7514 return;
7515 }
7516 md_number_to_chars (p, n, size);
7517 }
7518 else
7519 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7520 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7521 if (i.op[0].imms->X_op != O_constant)
7522 as_bad (_("can't handle non absolute segment in `%s'"),
7523 i.tm.name);
7524 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7525}
a217f122 7526
29b0f896 7527static void
e3bb37b5 7528output_insn (void)
29b0f896 7529{
2bbd9c25
JJ		 7530 fragS *insn_start_frag;
7531 offsetT insn_start_off;
7532
29b0f896
AM		 7533 /* Tie dwarf2 debug info to the address at the start of the insn.
7534 We can't do this after the insn has been output as the current
7535 frag may have been closed off. eg. by frag_var. */
7536 dwarf2_emit_insn (0);
7537
2bbd9c25
JJ		 7538 insn_start_frag = frag_now;
7539 insn_start_off = frag_now_fix ();
7540
29b0f896 7541 /* Output jumps. */
40fb9820 7542 if (i.tm.opcode_modifier.jump)
29b0f896 7543 output_branch ();
40fb9820
L		 7544 else if (i.tm.opcode_modifier.jumpbyte
7545 || i.tm.opcode_modifier.jumpdword)
29b0f896 7546 output_jump ();
40fb9820 7547 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7548 output_interseg_jump ();
7549 else
7550 {
7551 /* Output normal instructions here. */
7552 char *p;
7553 unsigned char *q;
47465058 7554 unsigned int j;
331d2d0d 7555 unsigned int prefix;
4dffcebc 7556
e4e00185
AS		 7557 if (avoid_fence
7558 && i.tm.base_opcode == 0xfae
7559 && i.operands == 1
7560 && i.imm_operands == 1
7561 && (i.op[0].imms->X_add_number == 0xe8
7562 || i.op[0].imms->X_add_number == 0xf0
7563 || i.op[0].imms->X_add_number == 0xf8))
7564 {
7565 /* Encode lfence, mfence, and sfence as
7566 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7567 offsetT val = 0x240483f0ULL;
7568 p = frag_more (5);
7569 md_number_to_chars (p, val, 5);
7570 return;
7571 }
7572
d022bddd
IT		 7573 /* Some processors fail on LOCK prefix. This options makes
7574 assembler ignore LOCK prefix and serves as a workaround. */
7575 if (omit_lock_prefix)
7576 {
7577 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7578 return;
7579 i.prefix[LOCK_PREFIX] = 0;
7580 }
7581
43234a1e
L		 7582 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7583 don't need the explicit prefix. */
7584 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7585 {
c0f3af97 7586 switch (i.tm.opcode_length)
bc4bd9ab 7587 {
c0f3af97
L		 7588 case 3:
7589 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7590 {
c0f3af97
L		 7591 prefix = (i.tm.base_opcode >> 24) & 0xff;
7592 goto check_prefix;
7593 }
7594 break;
7595 case 2:
7596 if ((i.tm.base_opcode & 0xff0000) != 0)
7597 {
7598 prefix = (i.tm.base_opcode >> 16) & 0xff;
7599 if (i.tm.cpu_flags.bitfield.cpupadlock)
7600 {
4dffcebc 7601check_prefix:
c0f3af97 7602 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7603 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7604 != REPE_PREFIX_OPCODE))
7605 add_prefix (prefix);
7606 }
7607 else
4dffcebc
L		 7608 add_prefix (prefix);
7609 }
c0f3af97
L		 7610 break;
7611 case 1:
7612 break;
390c91cf
L		 7613 case 0:
7614 /* Check for pseudo prefixes. */
7615 as_bad_where (insn_start_frag->fr_file,
7616 insn_start_frag->fr_line,
7617 _("pseudo prefix without instruction"));
7618 return;
c0f3af97
L		 7619 default:
7620 abort ();
bc4bd9ab 7621 }
c0f3af97 7622
6d19a37a 7623#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7624 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7625 R_X86_64_GOTTPOFF relocation so that linker can safely
7626 perform IE->LE optimization. */
7627 if (x86_elf_abi == X86_64_X32_ABI
7628 && i.operands == 2
7629 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7630 && i.prefix[REX_PREFIX] == 0)
7631 add_prefix (REX_OPCODE);
6d19a37a 7632#endif
cf61b747 7633
c0f3af97
L		 7634 /* The prefix bytes. */
7635 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7636 if (*q)
7637 FRAG_APPEND_1_CHAR (*q);
0f10071e 7638 }
ae5c1c7b 7639 else
c0f3af97
L		 7640 {
7641 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7642 if (*q)
7643 switch (j)
7644 {
7645 case REX_PREFIX:
7646 /* REX byte is encoded in VEX prefix. */
7647 break;
7648 case SEG_PREFIX:
7649 case ADDR_PREFIX:
7650 FRAG_APPEND_1_CHAR (*q);
7651 break;
7652 default:
7653 /* There should be no other prefixes for instructions
7654 with VEX prefix. */
7655 abort ();
7656 }
7657
43234a1e
L		 7658 /* For EVEX instructions i.vrex should become 0 after
7659 build_evex_prefix. For VEX instructions upper 16 registers
7660 aren't available, so VREX should be 0. */
7661 if (i.vrex)
7662 abort ();
c0f3af97
L		 7663 /* Now the VEX prefix. */
7664 p = frag_more (i.vex.length);
7665 for (j = 0; j < i.vex.length; j++)
7666 p[j] = i.vex.bytes[j];
7667 }
252b5132 7668
29b0f896 7669 /* Now the opcode; be careful about word order here! */
4dffcebc 7670 if (i.tm.opcode_length == 1)
29b0f896
AM		 7671 {
7672 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7673 }
7674 else
7675 {
4dffcebc 7676 switch (i.tm.opcode_length)
331d2d0d 7677 {
43234a1e
L		 7678 case 4:
7679 p = frag_more (4);
7680 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7681 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7682 break;
4dffcebc 7683 case 3:
331d2d0d
L		 7684 p = frag_more (3);
7685 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7686 break;
7687 case 2:
7688 p = frag_more (2);
7689 break;
7690 default:
7691 abort ();
7692 break;
331d2d0d 7693 }
0f10071e 7694
29b0f896
AM		 7695 /* Put out high byte first: can't use md_number_to_chars! */
7696 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7697 *p = i.tm.base_opcode & 0xff;
7698 }
3e73aa7c 7699
29b0f896 7700 /* Now the modrm byte and sib byte (if present). */
40fb9820 7701 if (i.tm.opcode_modifier.modrm)
29b0f896 7702 {
4a3523fa
L		 7703 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7704 | i.rm.reg << 3
7705 | i.rm.mode << 6));
29b0f896
AM		 7706 /* If i.rm.regmem == ESP (4)
7707 && i.rm.mode != (Register mode)
7708 && not 16 bit
7709 ==> need second modrm byte. */
7710 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7711 && i.rm.mode != 3
dc821c5f 7712 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
4a3523fa
L		 7713 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7714 | i.sib.index << 3
7715 | i.sib.scale << 6));
29b0f896 7716 }
3e73aa7c 7717
29b0f896 7718 if (i.disp_operands)
2bbd9c25 7719 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7720
29b0f896 7721 if (i.imm_operands)
2bbd9c25 7722 output_imm (insn_start_frag, insn_start_off);
29b0f896 7723 }
252b5132 7724
29b0f896
AM		 7725#ifdef DEBUG386
7726 if (flag_debug)
7727 {
7b81dfbb 7728 pi ("" /*line*/, &i);
29b0f896
AM		 7729 }
7730#endif /* DEBUG386 */
7731}
252b5132 7732
e205caa7
L		 7733/* Return the size of the displacement operand N. */
7734
7735static int
7736disp_size (unsigned int n)
7737{
7738 int size = 4;
43234a1e 7739
b5014f7a 7740 if (i.types[n].bitfield.disp64)
40fb9820
L		 7741 size = 8;
7742 else if (i.types[n].bitfield.disp8)
7743 size = 1;
7744 else if (i.types[n].bitfield.disp16)
7745 size = 2;
e205caa7
L		 7746 return size;
7747}
7748
7749/* Return the size of the immediate operand N. */
7750
7751static int
7752imm_size (unsigned int n)
7753{
7754 int size = 4;
40fb9820
L		 7755 if (i.types[n].bitfield.imm64)
7756 size = 8;
7757 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7758 size = 1;
7759 else if (i.types[n].bitfield.imm16)
7760 size = 2;
e205caa7
L		 7761 return size;
7762}
7763
29b0f896 7764static void
64e74474 7765output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7766{
7767 char *p;
7768 unsigned int n;
252b5132 7769
29b0f896
AM		 7770 for (n = 0; n < i.operands; n++)
7771 {
b5014f7a 7772 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 7773 {
7774 if (i.op[n].disps->X_op == O_constant)
7775 {
e205caa7 7776 int size = disp_size (n);
43234a1e 7777 offsetT val = i.op[n].disps->X_add_number;
252b5132 7778
b5014f7a 7779 val = offset_in_range (val >> i.memshift, size);
29b0f896
AM		 7780 p = frag_more (size);
7781 md_number_to_chars (p, val, size);
7782 }
7783 else
7784 {
f86103b7 7785 enum bfd_reloc_code_real reloc_type;
e205caa7 7786 int size = disp_size (n);
40fb9820 7787 int sign = i.types[n].bitfield.disp32s;
29b0f896 7788 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7789 fixS *fixP;
29b0f896 7790
e205caa7 7791 /* We can't have 8 bit displacement here. */
9c2799c2 7792 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7793
29b0f896
AM		 7794 /* The PC relative address is computed relative
7795 to the instruction boundary, so in case immediate
7796 fields follows, we need to adjust the value. */
7797 if (pcrel && i.imm_operands)
7798 {
29b0f896 7799 unsigned int n1;
e205caa7 7800 int sz = 0;
252b5132 7801
29b0f896 7802 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7803 if (operand_type_check (i.types[n1], imm))
252b5132 7804 {
e205caa7
L		 7805 /* Only one immediate is allowed for PC
7806 relative address. */
9c2799c2 7807 gas_assert (sz == 0);
e205caa7
L		 7808 sz = imm_size (n1);
7809 i.op[n].disps->X_add_number -= sz;
252b5132 7810 }
29b0f896 7811 /* We should find the immediate. */
9c2799c2 7812 gas_assert (sz != 0);
29b0f896 7813 }
520dc8e8 7814
29b0f896 7815 p = frag_more (size);
d258b828 7816 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7817 if (GOT_symbol
2bbd9c25 7818 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7819 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7820 || reloc_type == BFD_RELOC_X86_64_32S
7821 || (reloc_type == BFD_RELOC_64
7822 && object_64bit))
d6ab8113
JB		 7823 && (i.op[n].disps->X_op == O_symbol
7824 || (i.op[n].disps->X_op == O_add
7825 && ((symbol_get_value_expression
7826 (i.op[n].disps->X_op_symbol)->X_op)
7827 == O_subtract))))
7828 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7829 {
7830 offsetT add;
7831
7832 if (insn_start_frag == frag_now)
7833 add = (p - frag_now->fr_literal) - insn_start_off;
7834 else
7835 {
7836 fragS *fr;
7837
7838 add = insn_start_frag->fr_fix - insn_start_off;
7839 for (fr = insn_start_frag->fr_next;
7840 fr && fr != frag_now; fr = fr->fr_next)
7841 add += fr->fr_fix;
7842 add += p - frag_now->fr_literal;
7843 }
7844
4fa24527 7845 if (!object_64bit)
7b81dfbb
AJ		 7846 {
7847 reloc_type = BFD_RELOC_386_GOTPC;
7848 i.op[n].imms->X_add_number += add;
7849 }
7850 else if (reloc_type == BFD_RELOC_64)
7851 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7852 else
7b81dfbb
AJ		 7853 /* Don't do the adjustment for x86-64, as there
7854 the pcrel addressing is relative to the _next_
7855 insn, and that is taken care of in other code. */
d6ab8113 7856 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7857 }
02a86693
L		 7858 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7859 size, i.op[n].disps, pcrel,
7860 reloc_type);
7861 /* Check for "call/jmp *mem", "mov mem, %reg",
7862 "test %reg, mem" and "binop mem, %reg" where binop
7863 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7864 instructions. Always generate R_386_GOT32X for
7865 "sym*GOT" operand in 32-bit mode. */
7866 if ((generate_relax_relocations
7867 || (!object_64bit
7868 && i.rm.mode == 0
7869 && i.rm.regmem == 5))
7870 && (i.rm.mode == 2
7871 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7872 && ((i.operands == 1
7873 && i.tm.base_opcode == 0xff
7874 && (i.rm.reg == 2 || i.rm.reg == 4))
7875 || (i.operands == 2
7876 && (i.tm.base_opcode == 0x8b
7877 || i.tm.base_opcode == 0x85
7878 || (i.tm.base_opcode & 0xc7) == 0x03))))
7879 {
7880 if (object_64bit)
7881 {
7882 fixP->fx_tcbit = i.rex != 0;
7883 if (i.base_reg
7884 && (i.base_reg->reg_num == RegRip
7885 || i.base_reg->reg_num == RegEip))
7886 fixP->fx_tcbit2 = 1;
7887 }
7888 else
7889 fixP->fx_tcbit2 = 1;
7890 }
29b0f896
AM		 7891 }
7892 }
7893 }
7894}
252b5132 7895
29b0f896 7896static void
64e74474 7897output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7898{
7899 char *p;
7900 unsigned int n;
252b5132 7901
29b0f896
AM		 7902 for (n = 0; n < i.operands; n++)
7903 {
43234a1e
L		 7904 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7905 if (i.rounding && (int) n == i.rounding->operand)
7906 continue;
7907
40fb9820 7908 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7909 {
7910 if (i.op[n].imms->X_op == O_constant)
7911 {
e205caa7 7912 int size = imm_size (n);
29b0f896 7913 offsetT val;
b4cac588 7914
29b0f896
AM		 7915 val = offset_in_range (i.op[n].imms->X_add_number,
7916 size);
7917 p = frag_more (size);
7918 md_number_to_chars (p, val, size);
7919 }
7920 else
7921 {
7922 /* Not absolute_section.
7923 Need a 32-bit fixup (don't support 8bit
7924 non-absolute imms). Try to support other
7925 sizes ... */
f86103b7 7926 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7927 int size = imm_size (n);
7928 int sign;
29b0f896 7929
40fb9820 7930 if (i.types[n].bitfield.imm32s
a7d61044 7931 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7932 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7933 sign = 1;
e205caa7
L		 7934 else
7935 sign = 0;
520dc8e8 7936
29b0f896 7937 p = frag_more (size);
d258b828 7938 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7939
2bbd9c25
JJ		 7940 /* This is tough to explain. We end up with this one if we
7941 * have operands that look like
7942 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7943 * obtain the absolute address of the GOT, and it is strongly
7944 * preferable from a performance point of view to avoid using
7945 * a runtime relocation for this. The actual sequence of
7946 * instructions often look something like:
7947 *
7948 * call .L66
7949 * .L66:
7950 * popl %ebx
7951 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7952 *
7953 * The call and pop essentially return the absolute address
7954 * of the label .L66 and store it in %ebx. The linker itself
7955 * will ultimately change the first operand of the addl so
7956 * that %ebx points to the GOT, but to keep things simple, the
7957 * .o file must have this operand set so that it generates not
7958 * the absolute address of .L66, but the absolute address of
7959 * itself. This allows the linker itself simply treat a GOTPC
7960 * relocation as asking for a pcrel offset to the GOT to be
7961 * added in, and the addend of the relocation is stored in the
7962 * operand field for the instruction itself.
7963 *
7964 * Our job here is to fix the operand so that it would add
7965 * the correct offset so that %ebx would point to itself. The
7966 * thing that is tricky is that .-.L66 will point to the
7967 * beginning of the instruction, so we need to further modify
7968 * the operand so that it will point to itself. There are
7969 * other cases where you have something like:
7970 *
7971 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7972 *
7973 * and here no correction would be required. Internally in
7974 * the assembler we treat operands of this form as not being
7975 * pcrel since the '.' is explicitly mentioned, and I wonder
7976 * whether it would simplify matters to do it this way. Who
7977 * knows. In earlier versions of the PIC patches, the
7978 * pcrel_adjust field was used to store the correction, but
7979 * since the expression is not pcrel, I felt it would be
7980 * confusing to do it this way. */
7981
d6ab8113 7982 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7983 || reloc_type == BFD_RELOC_X86_64_32S
7984 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7985 && GOT_symbol
7986 && GOT_symbol == i.op[n].imms->X_add_symbol
7987 && (i.op[n].imms->X_op == O_symbol
7988 || (i.op[n].imms->X_op == O_add
7989 && ((symbol_get_value_expression
7990 (i.op[n].imms->X_op_symbol)->X_op)
7991 == O_subtract))))
7992 {
2bbd9c25
JJ		 7993 offsetT add;
7994
7995 if (insn_start_frag == frag_now)
7996 add = (p - frag_now->fr_literal) - insn_start_off;
7997 else
7998 {
7999 fragS *fr;
8000
8001 add = insn_start_frag->fr_fix - insn_start_off;
8002 for (fr = insn_start_frag->fr_next;
8003 fr && fr != frag_now; fr = fr->fr_next)
8004 add += fr->fr_fix;
8005 add += p - frag_now->fr_literal;
8006 }
8007
4fa24527 8008 if (!object_64bit)
d6ab8113 8009 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 8010 else if (size == 4)
d6ab8113 8011 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 8012 else if (size == 8)
8013 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 8014 i.op[n].imms->X_add_number += add;
29b0f896 8015 }
29b0f896
AM		 8016 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8017 i.op[n].imms, 0, reloc_type);
8018 }
8019 }
8020 }
252b5132
RH		 8021}
8022\f
d182319b
JB		 8023/* x86_cons_fix_new is called via the expression parsing code when a
8024 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 8025static int cons_sign = -1;
8026
8027void
e3bb37b5 8028x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 8029 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 8030{
d258b828 8031 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 8032
8033#ifdef TE_PE
8034 if (exp->X_op == O_secrel)
8035 {
8036 exp->X_op = O_symbol;
8037 r = BFD_RELOC_32_SECREL;
8038 }
8039#endif
8040
8041 fix_new_exp (frag, off, len, exp, 0, r);
8042}
8043
357d1bd8
L		 8044/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8045 purpose of the `.dc.a' internal pseudo-op. */
8046
8047int
8048x86_address_bytes (void)
8049{
8050 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8051 return 4;
8052 return stdoutput->arch_info->bits_per_address / 8;
8053}
8054
d382c579
TG		 8055#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8056 || defined (LEX_AT)
d258b828 8057# define lex_got(reloc, adjust, types) NULL
718ddfc0 8058#else
f3c180ae
AM		 8059/* Parse operands of the form
8060 <symbol>@GOTOFF+<nnn>
8061 and similar .plt or .got references.
8062
8063 If we find one, set up the correct relocation in RELOC and copy the
8064 input string, minus the `@GOTOFF' into a malloc'd buffer for
8065 parsing by the calling routine. Return this buffer, and if ADJUST
8066 is non-null set it to the length of the string we removed from the
8067 input line. Otherwise return NULL. */
8068static char *
91d6fa6a 8069lex_got (enum bfd_reloc_code_real *rel,
64e74474 8070 int *adjust,
d258b828 8071 i386_operand_type *types)
f3c180ae 8072{
7b81dfbb
AJ		 8073 /* Some of the relocations depend on the size of what field is to
8074 be relocated. But in our callers i386_immediate and i386_displacement
8075 we don't yet know the operand size (this will be set by insn
8076 matching). Hence we record the word32 relocation here,
8077 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 8078 static const struct {
8079 const char *str;
cff8d58a 8080 int len;
4fa24527 8081 const enum bfd_reloc_code_real rel[2];
40fb9820 8082 const i386_operand_type types64;
f3c180ae 8083 } gotrel[] = {
8ce3d284 8084#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 8085 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8086 BFD_RELOC_SIZE32 },
8087 OPERAND_TYPE_IMM32_64 },
8ce3d284 8088#endif
cff8d58a
L		 8089 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8090 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 8091 OPERAND_TYPE_IMM64 },
cff8d58a
L		 8092 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8093 BFD_RELOC_X86_64_PLT32 },
40fb9820 8094 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8095 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8096 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 8097 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8098 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8099 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 8100 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8101 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8102 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 8103 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8104 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8105 BFD_RELOC_X86_64_TLSGD },
40fb9820 8106 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8107 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8108 _dummy_first_bfd_reloc_code_real },
40fb9820 8109 OPERAND_TYPE_NONE },
cff8d58a
L		 8110 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8111 BFD_RELOC_X86_64_TLSLD },
40fb9820 8112 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8113 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8114 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 8115 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8116 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8117 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 8118 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8119 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8120 _dummy_first_bfd_reloc_code_real },
40fb9820 8121 OPERAND_TYPE_NONE },
cff8d58a
L		 8122 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8123 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 8124 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8125 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8126 _dummy_first_bfd_reloc_code_real },
40fb9820 8127 OPERAND_TYPE_NONE },
cff8d58a
L		 8128 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8129 _dummy_first_bfd_reloc_code_real },
40fb9820 8130 OPERAND_TYPE_NONE },
cff8d58a
L		 8131 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8132 BFD_RELOC_X86_64_GOT32 },
40fb9820 8133 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 8134 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8135 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 8136 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8137 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8138 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 8139 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 8140 };
8141 char *cp;
8142 unsigned int j;
8143
d382c579 8144#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 8145 if (!IS_ELF)
8146 return NULL;
d382c579 8147#endif
718ddfc0 8148
f3c180ae 8149 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 8150 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 8151 return NULL;
8152
47465058 8153 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 8154 {
cff8d58a 8155 int len = gotrel[j].len;
28f81592 8156 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 8157 {
4fa24527 8158 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 8159 {
28f81592
AM		 8160 int first, second;
8161 char *tmpbuf, *past_reloc;
f3c180ae 8162
91d6fa6a 8163 *rel = gotrel[j].rel[object_64bit];
f3c180ae 8164
3956db08
JB		 8165 if (types)
8166 {
8167 if (flag_code != CODE_64BIT)
40fb9820
L		 8168 {
8169 types->bitfield.imm32 = 1;
8170 types->bitfield.disp32 = 1;
8171 }
3956db08
JB		 8172 else
8173 *types = gotrel[j].types64;
8174 }
8175
8fd4256d 8176 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 8177 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8178
28f81592 8179 /* The length of the first part of our input line. */
f3c180ae 8180 first = cp - input_line_pointer;
28f81592
AM		 8181
8182 /* The second part goes from after the reloc token until
67c11a9b 8183 (and including) an end_of_line char or comma. */
28f81592 8184 past_reloc = cp + 1 + len;
67c11a9b
AM		 8185 cp = past_reloc;
8186 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8187 ++cp;
8188 second = cp + 1 - past_reloc;
28f81592
AM		 8189
8190 /* Allocate and copy string. The trailing NUL shouldn't
8191 be necessary, but be safe. */
add39d23 8192 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 8193 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 8194 if (second != 0 && *past_reloc != ' ')
8195 /* Replace the relocation token with ' ', so that
8196 errors like foo@GOTOFF1 will be detected. */
8197 tmpbuf[first++] = ' ';
af89796a
L		 8198 else
8199 /* Increment length by 1 if the relocation token is
8200 removed. */
8201 len++;
8202 if (adjust)
8203 *adjust = len;
0787a12d
AM		 8204 memcpy (tmpbuf + first, past_reloc, second);
8205 tmpbuf[first + second] = '\0';
f3c180ae
AM		 8206 return tmpbuf;
8207 }
8208
4fa24527
JB		 8209 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8210 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 8211 return NULL;
8212 }
8213 }
8214
8215 /* Might be a symbol version string. Don't as_bad here. */
8216 return NULL;
8217}
4e4f7c87 8218#endif
f3c180ae 8219
a988325c
NC		 8220#ifdef TE_PE
8221#ifdef lex_got
8222#undef lex_got
8223#endif
8224/* Parse operands of the form
8225 <symbol>@SECREL32+<nnn>
8226
8227 If we find one, set up the correct relocation in RELOC and copy the
8228 input string, minus the `@SECREL32' into a malloc'd buffer for
8229 parsing by the calling routine. Return this buffer, and if ADJUST
8230 is non-null set it to the length of the string we removed from the
34bca508
L		 8231 input line. Otherwise return NULL.
8232
a988325c
NC		 8233 This function is copied from the ELF version above adjusted for PE targets. */
8234
8235static char *
8236lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8237 int *adjust ATTRIBUTE_UNUSED,
d258b828 8238 i386_operand_type *types)
a988325c
NC		 8239{
8240 static const struct
8241 {
8242 const char *str;
8243 int len;
8244 const enum bfd_reloc_code_real rel[2];
8245 const i386_operand_type types64;
8246 }
8247 gotrel[] =
8248 {
8249 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8250 BFD_RELOC_32_SECREL },
8251 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8252 };
8253
8254 char *cp;
8255 unsigned j;
8256
8257 for (cp = input_line_pointer; *cp != '@'; cp++)
8258 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8259 return NULL;
8260
8261 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8262 {
8263 int len = gotrel[j].len;
8264
8265 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8266 {
8267 if (gotrel[j].rel[object_64bit] != 0)
8268 {
8269 int first, second;
8270 char *tmpbuf, *past_reloc;
8271
8272 *rel = gotrel[j].rel[object_64bit];
8273 if (adjust)
8274 *adjust = len;
8275
8276 if (types)
8277 {
8278 if (flag_code != CODE_64BIT)
8279 {
8280 types->bitfield.imm32 = 1;
8281 types->bitfield.disp32 = 1;
8282 }
8283 else
8284 *types = gotrel[j].types64;
8285 }
8286
8287 /* The length of the first part of our input line. */
8288 first = cp - input_line_pointer;
8289
8290 /* The second part goes from after the reloc token until
8291 (and including) an end_of_line char or comma. */
8292 past_reloc = cp + 1 + len;
8293 cp = past_reloc;
8294 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8295 ++cp;
8296 second = cp + 1 - past_reloc;
8297
8298 /* Allocate and copy string. The trailing NUL shouldn't
8299 be necessary, but be safe. */
add39d23 8300 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 8301 memcpy (tmpbuf, input_line_pointer, first);
8302 if (second != 0 && *past_reloc != ' ')
8303 /* Replace the relocation token with ' ', so that
8304 errors like foo@SECLREL321 will be detected. */
8305 tmpbuf[first++] = ' ';
8306 memcpy (tmpbuf + first, past_reloc, second);
8307 tmpbuf[first + second] = '\0';
8308 return tmpbuf;
8309 }
8310
8311 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8312 gotrel[j].str, 1 << (5 + object_64bit));
8313 return NULL;
8314 }
8315 }
8316
8317 /* Might be a symbol version string. Don't as_bad here. */
8318 return NULL;
8319}
8320
8321#endif /* TE_PE */
8322
62ebcb5c 8323bfd_reloc_code_real_type
e3bb37b5 8324x86_cons (expressionS *exp, int size)
f3c180ae 8325{
62ebcb5c
AM		 8326 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8327
ee86248c
JB		 8328 intel_syntax = -intel_syntax;
8329
3c7b9c2c 8330 exp->X_md = 0;
4fa24527 8331 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 8332 {
8333 /* Handle @GOTOFF and the like in an expression. */
8334 char *save;
8335 char *gotfree_input_line;
4a57f2cf 8336 int adjust = 0;
f3c180ae
AM		 8337
8338 save = input_line_pointer;
d258b828 8339 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 8340 if (gotfree_input_line)
8341 input_line_pointer = gotfree_input_line;
8342
8343 expression (exp);
8344
8345 if (gotfree_input_line)
8346 {
8347 /* expression () has merrily parsed up to the end of line,
8348 or a comma - in the wrong buffer. Transfer how far
8349 input_line_pointer has moved to the right buffer. */
8350 input_line_pointer = (save
8351 + (input_line_pointer - gotfree_input_line)
8352 + adjust);
8353 free (gotfree_input_line);
3992d3b7
AM		 8354 if (exp->X_op == O_constant
8355 || exp->X_op == O_absent
8356 || exp->X_op == O_illegal
0398aac5 8357 || exp->X_op == O_register
3992d3b7
AM		 8358 || exp->X_op == O_big)
8359 {
8360 char c = *input_line_pointer;
8361 *input_line_pointer = 0;
8362 as_bad (_("missing or invalid expression `%s'"), save);
8363 *input_line_pointer = c;
8364 }
f3c180ae
AM		 8365 }
8366 }
8367 else
8368 expression (exp);
ee86248c
JB		 8369
8370 intel_syntax = -intel_syntax;
8371
8372 if (intel_syntax)
8373 i386_intel_simplify (exp);
62ebcb5c
AM		 8374
8375 return got_reloc;
f3c180ae 8376}
f3c180ae 8377
9f32dd5b
L		 8378static void
8379signed_cons (int size)
6482c264 8380{
d182319b
JB		 8381 if (flag_code == CODE_64BIT)
8382 cons_sign = 1;
8383 cons (size);
8384 cons_sign = -1;
6482c264
NC		 8385}
8386
d182319b 8387#ifdef TE_PE
6482c264 8388static void
7016a5d5 8389pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 8390{
8391 expressionS exp;
8392
8393 do
8394 {
8395 expression (&exp);
8396 if (exp.X_op == O_symbol)
8397 exp.X_op = O_secrel;
8398
8399 emit_expr (&exp, 4);
8400 }
8401 while (*input_line_pointer++ == ',');
8402
8403 input_line_pointer--;
8404 demand_empty_rest_of_line ();
8405}
6482c264
NC		 8406#endif
8407
43234a1e
L		 8408/* Handle Vector operations. */
8409
8410static char *
8411check_VecOperations (char *op_string, char *op_end)
8412{
8413 const reg_entry *mask;
8414 const char *saved;
8415 char *end_op;
8416
8417 while (*op_string
8418 && (op_end == NULL || op_string < op_end))
8419 {
8420 saved = op_string;
8421 if (*op_string == '{')
8422 {
8423 op_string++;
8424
8425 /* Check broadcasts. */
8426 if (strncmp (op_string, "1to", 3) == 0)
8427 {
8428 int bcst_type;
8429
8430 if (i.broadcast)
8431 goto duplicated_vec_op;
8432
8433 op_string += 3;
8434 if (*op_string == '8')
8435 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 8436 else if (*op_string == '4')
8437 bcst_type = BROADCAST_1TO4;
8438 else if (*op_string == '2')
8439 bcst_type = BROADCAST_1TO2;
43234a1e
L		 8440 else if (*op_string == '1'
8441 && *(op_string+1) == '6')
8442 {
8443 bcst_type = BROADCAST_1TO16;
8444 op_string++;
8445 }
8446 else
8447 {
8448 as_bad (_("Unsupported broadcast: `%s'"), saved);
8449 return NULL;
8450 }
8451 op_string++;
8452
8453 broadcast_op.type = bcst_type;
8454 broadcast_op.operand = this_operand;
8455 i.broadcast = &broadcast_op;
8456 }
8457 /* Check masking operation. */
8458 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8459 {
8460 /* k0 can't be used for write mask. */
6d2cd6b2 8461 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
43234a1e 8462 {
6d2cd6b2
JB		 8463 as_bad (_("`%s%s' can't be used for write mask"),
8464 register_prefix, mask->reg_name);
43234a1e
L		 8465 return NULL;
8466 }
8467
8468 if (!i.mask)
8469 {
8470 mask_op.mask = mask;
8471 mask_op.zeroing = 0;
8472 mask_op.operand = this_operand;
8473 i.mask = &mask_op;
8474 }
8475 else
8476 {
8477 if (i.mask->mask)
8478 goto duplicated_vec_op;
8479
8480 i.mask->mask = mask;
8481
8482 /* Only "{z}" is allowed here. No need to check
8483 zeroing mask explicitly. */
8484 if (i.mask->operand != this_operand)
8485 {
8486 as_bad (_("invalid write mask `%s'"), saved);
8487 return NULL;
8488 }
8489 }
8490
8491 op_string = end_op;
8492 }
8493 /* Check zeroing-flag for masking operation. */
8494 else if (*op_string == 'z')
8495 {
8496 if (!i.mask)
8497 {
8498 mask_op.mask = NULL;
8499 mask_op.zeroing = 1;
8500 mask_op.operand = this_operand;
8501 i.mask = &mask_op;
8502 }
8503 else
8504 {
8505 if (i.mask->zeroing)
8506 {
8507 duplicated_vec_op:
8508 as_bad (_("duplicated `%s'"), saved);
8509 return NULL;
8510 }
8511
8512 i.mask->zeroing = 1;
8513
8514 /* Only "{%k}" is allowed here. No need to check mask
8515 register explicitly. */
8516 if (i.mask->operand != this_operand)
8517 {
8518 as_bad (_("invalid zeroing-masking `%s'"),
8519 saved);
8520 return NULL;
8521 }
8522 }
8523
8524 op_string++;
8525 }
8526 else
8527 goto unknown_vec_op;
8528
8529 if (*op_string != '}')
8530 {
8531 as_bad (_("missing `}' in `%s'"), saved);
8532 return NULL;
8533 }
8534 op_string++;
0ba3a731
L		 8535
8536 /* Strip whitespace since the addition of pseudo prefixes
8537 changed how the scrubber treats '{'. */
8538 if (is_space_char (*op_string))
8539 ++op_string;
8540
43234a1e
L		 8541 continue;
8542 }
8543 unknown_vec_op:
8544 /* We don't know this one. */
8545 as_bad (_("unknown vector operation: `%s'"), saved);
8546 return NULL;
8547 }
8548
6d2cd6b2
JB		 8549 if (i.mask && i.mask->zeroing && !i.mask->mask)
8550 {
8551 as_bad (_("zeroing-masking only allowed with write mask"));
8552 return NULL;
8553 }
8554
43234a1e
L		 8555 return op_string;
8556}
8557
252b5132 8558static int
70e41ade 8559i386_immediate (char *imm_start)
252b5132
RH		 8560{
8561 char *save_input_line_pointer;
f3c180ae 8562 char *gotfree_input_line;
252b5132 8563 segT exp_seg = 0;
47926f60 8564 expressionS *exp;
40fb9820
L		 8565 i386_operand_type types;
8566
0dfbf9d7 8567 operand_type_set (&types, ~0);
252b5132
RH		 8568
8569 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8570 {
31b2323c
L		 8571 as_bad (_("at most %d immediate operands are allowed"),
8572 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8573 return 0;
8574 }
8575
8576 exp = &im_expressions[i.imm_operands++];
520dc8e8 8577 i.op[this_operand].imms = exp;
252b5132
RH		 8578
8579 if (is_space_char (*imm_start))
8580 ++imm_start;
8581
8582 save_input_line_pointer = input_line_pointer;
8583 input_line_pointer = imm_start;
8584
d258b828 8585 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8586 if (gotfree_input_line)
8587 input_line_pointer = gotfree_input_line;
252b5132
RH		 8588
8589 exp_seg = expression (exp);
8590
83183c0c 8591 SKIP_WHITESPACE ();
43234a1e
L		 8592
8593 /* Handle vector operations. */
8594 if (*input_line_pointer == '{')
8595 {
8596 input_line_pointer = check_VecOperations (input_line_pointer,
8597 NULL);
8598 if (input_line_pointer == NULL)
8599 return 0;
8600 }
8601
252b5132 8602 if (*input_line_pointer)
f3c180ae 8603 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8604
8605 input_line_pointer = save_input_line_pointer;
f3c180ae 8606 if (gotfree_input_line)
ee86248c
JB		 8607 {
8608 free (gotfree_input_line);
8609
8610 if (exp->X_op == O_constant || exp->X_op == O_register)
8611 exp->X_op = O_illegal;
8612 }
8613
8614 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8615}
252b5132 8616
ee86248c
JB		 8617static int
8618i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8619 i386_operand_type types, const char *imm_start)
8620{
8621 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8622 {
313c53d1
L		 8623 if (imm_start)
8624 as_bad (_("missing or invalid immediate expression `%s'"),
8625 imm_start);
3992d3b7 8626 return 0;
252b5132 8627 }
3e73aa7c 8628 else if (exp->X_op == O_constant)
252b5132 8629 {
47926f60 8630 /* Size it properly later. */
40fb9820 8631 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8632 /* If not 64bit, sign extend val. */
8633 if (flag_code != CODE_64BIT
4eed87de
AM		 8634 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8635 exp->X_add_number
8636 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8637 }
4c63da97 8638#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8639 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8640 && exp_seg != absolute_section
47926f60 8641 && exp_seg != text_section
24eab124
AM		 8642 && exp_seg != data_section
8643 && exp_seg != bss_section
8644 && exp_seg != undefined_section
f86103b7 8645 && !bfd_is_com_section (exp_seg))
252b5132 8646 {
d0b47220 8647 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8648 return 0;
8649 }
8650#endif
a841bdf5 8651 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8652 {
313c53d1
L		 8653 if (imm_start)
8654 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8655 return 0;
8656 }
252b5132
RH		 8657 else
8658 {
8659 /* This is an address. The size of the address will be
24eab124 8660 determined later, depending on destination register,
3e73aa7c 8661 suffix, or the default for the section. */
40fb9820
L		 8662 i.types[this_operand].bitfield.imm8 = 1;
8663 i.types[this_operand].bitfield.imm16 = 1;
8664 i.types[this_operand].bitfield.imm32 = 1;
8665 i.types[this_operand].bitfield.imm32s = 1;
8666 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8667 i.types[this_operand] = operand_type_and (i.types[this_operand],
8668 types);
252b5132
RH		 8669 }
8670
8671 return 1;
8672}
8673
551c1ca1 8674static char *
e3bb37b5 8675i386_scale (char *scale)
252b5132 8676{
551c1ca1
AM		 8677 offsetT val;
8678 char *save = input_line_pointer;
252b5132 8679
551c1ca1
AM		 8680 input_line_pointer = scale;
8681 val = get_absolute_expression ();
8682
8683 switch (val)
252b5132 8684 {
551c1ca1 8685 case 1:
252b5132
RH		 8686 i.log2_scale_factor = 0;
8687 break;
551c1ca1 8688 case 2:
252b5132
RH		 8689 i.log2_scale_factor = 1;
8690 break;
551c1ca1 8691 case 4:
252b5132
RH		 8692 i.log2_scale_factor = 2;
8693 break;
551c1ca1 8694 case 8:
252b5132
RH		 8695 i.log2_scale_factor = 3;
8696 break;
8697 default:
a724f0f4
JB		 8698 {
8699 char sep = *input_line_pointer;
8700
8701 *input_line_pointer = '\0';
8702 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8703 scale);
8704 *input_line_pointer = sep;
8705 input_line_pointer = save;
8706 return NULL;
8707 }
252b5132 8708 }
29b0f896 8709 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8710 {
8711 as_warn (_("scale factor of %d without an index register"),
24eab124 8712 1 << i.log2_scale_factor);
252b5132 8713 i.log2_scale_factor = 0;
252b5132 8714 }
551c1ca1
AM		 8715 scale = input_line_pointer;
8716 input_line_pointer = save;
8717 return scale;
252b5132
RH		 8718}
8719
252b5132 8720static int
e3bb37b5 8721i386_displacement (char *disp_start, char *disp_end)
252b5132 8722{
29b0f896 8723 expressionS *exp;
252b5132
RH		 8724 segT exp_seg = 0;
8725 char *save_input_line_pointer;
f3c180ae 8726 char *gotfree_input_line;
40fb9820
L		 8727 int override;
8728 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8729 int ret;
252b5132 8730
31b2323c
L		 8731 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8732 {
8733 as_bad (_("at most %d displacement operands are allowed"),
8734 MAX_MEMORY_OPERANDS);
8735 return 0;
8736 }
8737
0dfbf9d7 8738 operand_type_set (&bigdisp, 0);
40fb9820
L		 8739 if ((i.types[this_operand].bitfield.jumpabsolute)
8740 || (!current_templates->start->opcode_modifier.jump
8741 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8742 {
40fb9820 8743 bigdisp.bitfield.disp32 = 1;
e05278af 8744 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8745 if (flag_code == CODE_64BIT)
8746 {
8747 if (!override)
8748 {
8749 bigdisp.bitfield.disp32s = 1;
8750 bigdisp.bitfield.disp64 = 1;
8751 }
8752 }
8753 else if ((flag_code == CODE_16BIT) ^ override)
8754 {
8755 bigdisp.bitfield.disp32 = 0;
8756 bigdisp.bitfield.disp16 = 1;
8757 }
e05278af
JB		 8758 }
8759 else
8760 {
8761 /* For PC-relative branches, the width of the displacement
8762 is dependent upon data size, not address size. */
e05278af 8763 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8764 if (flag_code == CODE_64BIT)
8765 {
8766 if (override || i.suffix == WORD_MNEM_SUFFIX)
8767 bigdisp.bitfield.disp16 = 1;
8768 else
8769 {
8770 bigdisp.bitfield.disp32 = 1;
8771 bigdisp.bitfield.disp32s = 1;
8772 }
8773 }
8774 else
e05278af
JB		 8775 {
8776 if (!override)
8777 override = (i.suffix == (flag_code != CODE_16BIT
8778 ? WORD_MNEM_SUFFIX
8779 : LONG_MNEM_SUFFIX));
40fb9820
L		 8780 bigdisp.bitfield.disp32 = 1;
8781 if ((flag_code == CODE_16BIT) ^ override)
8782 {
8783 bigdisp.bitfield.disp32 = 0;
8784 bigdisp.bitfield.disp16 = 1;
8785 }
e05278af 8786 }
e05278af 8787 }
c6fb90c8
L		 8788 i.types[this_operand] = operand_type_or (i.types[this_operand],
8789 bigdisp);
252b5132
RH		 8790
8791 exp = &disp_expressions[i.disp_operands];
520dc8e8 8792 i.op[this_operand].disps = exp;
252b5132
RH		 8793 i.disp_operands++;
8794 save_input_line_pointer = input_line_pointer;
8795 input_line_pointer = disp_start;
8796 END_STRING_AND_SAVE (disp_end);
8797
8798#ifndef GCC_ASM_O_HACK
8799#define GCC_ASM_O_HACK 0
8800#endif
8801#if GCC_ASM_O_HACK
8802 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8803 if (i.types[this_operand].bitfield.baseIndex
24eab124 8804 && displacement_string_end[-1] == '+')
252b5132
RH		 8805 {
8806 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8807 constraint within gcc asm statements.
8808 For instance:
8809
8810 #define _set_tssldt_desc(n,addr,limit,type) \
8811 __asm__ __volatile__ ( \
8812 "movw %w2,%0\n\t" \
8813 "movw %w1,2+%0\n\t" \
8814 "rorl $16,%1\n\t" \
8815 "movb %b1,4+%0\n\t" \
8816 "movb %4,5+%0\n\t" \
8817 "movb $0,6+%0\n\t" \
8818 "movb %h1,7+%0\n\t" \
8819 "rorl $16,%1" \
8820 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8821
8822 This works great except that the output assembler ends
8823 up looking a bit weird if it turns out that there is
8824 no offset. You end up producing code that looks like:
8825
8826 #APP
8827 movw $235,(%eax)
8828 movw %dx,2+(%eax)
8829 rorl $16,%edx
8830 movb %dl,4+(%eax)
8831 movb $137,5+(%eax)
8832 movb $0,6+(%eax)
8833 movb %dh,7+(%eax)
8834 rorl $16,%edx
8835 #NO_APP
8836
47926f60 8837 So here we provide the missing zero. */
24eab124
AM		 8838
8839 *displacement_string_end = '0';
252b5132
RH		 8840 }
8841#endif
d258b828 8842 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8843 if (gotfree_input_line)
8844 input_line_pointer = gotfree_input_line;
252b5132 8845
24eab124 8846 exp_seg = expression (exp);
252b5132 8847
636c26b0
AM		 8848 SKIP_WHITESPACE ();
8849 if (*input_line_pointer)
8850 as_bad (_("junk `%s' after expression"), input_line_pointer);
8851#if GCC_ASM_O_HACK
8852 RESTORE_END_STRING (disp_end + 1);
8853#endif
636c26b0 8854 input_line_pointer = save_input_line_pointer;
636c26b0 8855 if (gotfree_input_line)
ee86248c
JB		 8856 {
8857 free (gotfree_input_line);
8858
8859 if (exp->X_op == O_constant || exp->X_op == O_register)
8860 exp->X_op = O_illegal;
8861 }
8862
8863 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8864
8865 RESTORE_END_STRING (disp_end);
8866
8867 return ret;
8868}
8869
8870static int
8871i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8872 i386_operand_type types, const char *disp_start)
8873{
8874 i386_operand_type bigdisp;
8875 int ret = 1;
636c26b0 8876
24eab124
AM		 8877 /* We do this to make sure that the section symbol is in
8878 the symbol table. We will ultimately change the relocation
47926f60 8879 to be relative to the beginning of the section. */
1ae12ab7 8880 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8881 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8882 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8883 {
636c26b0 8884 if (exp->X_op != O_symbol)
3992d3b7 8885 goto inv_disp;
636c26b0 8886
e5cb08ac 8887 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8888 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8889 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8890 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8891 exp->X_op = O_subtract;
8892 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8893 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8894 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8895 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8896 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8897 else
29b0f896 8898 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8899 }
252b5132 8900
3992d3b7
AM		 8901 else if (exp->X_op == O_absent
8902 || exp->X_op == O_illegal
ee86248c 8903 || exp->X_op == O_big)
2daf4fd8 8904 {
3992d3b7
AM		 8905 inv_disp:
8906 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8907 disp_start);
3992d3b7 8908 ret = 0;
2daf4fd8
AM		 8909 }
8910
0e1147d9
L		 8911 else if (flag_code == CODE_64BIT
8912 && !i.prefix[ADDR_PREFIX]
8913 && exp->X_op == O_constant)
8914 {
8915 /* Since displacement is signed extended to 64bit, don't allow
8916 disp32 and turn off disp32s if they are out of range. */
8917 i.types[this_operand].bitfield.disp32 = 0;
8918 if (!fits_in_signed_long (exp->X_add_number))
8919 {
8920 i.types[this_operand].bitfield.disp32s = 0;
8921 if (i.types[this_operand].bitfield.baseindex)
8922 {
8923 as_bad (_("0x%lx out range of signed 32bit displacement"),
8924 (long) exp->X_add_number);
8925 ret = 0;
8926 }
8927 }
8928 }
8929
4c63da97 8930#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8931 else if (exp->X_op != O_constant
8932 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8933 && exp_seg != absolute_section
8934 && exp_seg != text_section
8935 && exp_seg != data_section
8936 && exp_seg != bss_section
8937 && exp_seg != undefined_section
8938 && !bfd_is_com_section (exp_seg))
24eab124 8939 {
d0b47220 8940 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8941 ret = 0;
24eab124 8942 }
252b5132 8943#endif
3956db08 8944
40fb9820
L		 8945 /* Check if this is a displacement only operand. */
8946 bigdisp = i.types[this_operand];
8947 bigdisp.bitfield.disp8 = 0;
8948 bigdisp.bitfield.disp16 = 0;
8949 bigdisp.bitfield.disp32 = 0;
8950 bigdisp.bitfield.disp32s = 0;
8951 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8952 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8953 i.types[this_operand] = operand_type_and (i.types[this_operand],
8954 types);
3956db08 8955
3992d3b7 8956 return ret;
252b5132
RH		 8957}
8958
2abc2bec
JB		 8959/* Return the active addressing mode, taking address override and
8960 registers forming the address into consideration. Update the
8961 address override prefix if necessary. */
47926f60 8962
2abc2bec
JB		 8963static enum flag_code
8964i386_addressing_mode (void)
252b5132 8965{
be05d201
L		 8966 enum flag_code addr_mode;
8967
8968 if (i.prefix[ADDR_PREFIX])
8969 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8970 else
8971 {
8972 addr_mode = flag_code;
8973
24eab124 8974#if INFER_ADDR_PREFIX
be05d201
L		 8975 if (i.mem_operands == 0)
8976 {
8977 /* Infer address prefix from the first memory operand. */
8978 const reg_entry *addr_reg = i.base_reg;
8979
8980 if (addr_reg == NULL)
8981 addr_reg = i.index_reg;
eecb386c 8982
be05d201
L		 8983 if (addr_reg)
8984 {
8985 if (addr_reg->reg_num == RegEip
8986 || addr_reg->reg_num == RegEiz
dc821c5f 8987 || addr_reg->reg_type.bitfield.dword)
be05d201
L		 8988 addr_mode = CODE_32BIT;
8989 else if (flag_code != CODE_64BIT
dc821c5f 8990 && addr_reg->reg_type.bitfield.word)
be05d201
L		 8991 addr_mode = CODE_16BIT;
8992
8993 if (addr_mode != flag_code)
8994 {
8995 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8996 i.prefixes += 1;
8997 /* Change the size of any displacement too. At most one
8998 of Disp16 or Disp32 is set.
8999 FIXME. There doesn't seem to be any real need for
9000 separate Disp16 and Disp32 flags. The same goes for
9001 Imm16 and Imm32. Removing them would probably clean
9002 up the code quite a lot. */
9003 if (flag_code != CODE_64BIT
9004 && (i.types[this_operand].bitfield.disp16
9005 || i.types[this_operand].bitfield.disp32))
9006 i.types[this_operand]
9007 = operand_type_xor (i.types[this_operand], disp16_32);
9008 }
9009 }
9010 }
24eab124 9011#endif
be05d201
L		 9012 }
9013
2abc2bec
JB		 9014 return addr_mode;
9015}
9016
9017/* Make sure the memory operand we've been dealt is valid.
9018 Return 1 on success, 0 on a failure. */
9019
9020static int
9021i386_index_check (const char *operand_string)
9022{
9023 const char *kind = "base/index";
9024 enum flag_code addr_mode = i386_addressing_mode ();
9025
fc0763e6
JB		 9026 if (current_templates->start->opcode_modifier.isstring
9027 && !current_templates->start->opcode_modifier.immext
9028 && (current_templates->end[-1].opcode_modifier.isstring
9029 || i.mem_operands))
9030 {
9031 /* Memory operands of string insns are special in that they only allow
9032 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 9033 const reg_entry *expected_reg;
9034 static const char *di_si[][2] =
9035 {
9036 { "esi", "edi" },
9037 { "si", "di" },
9038 { "rsi", "rdi" }
9039 };
9040 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 9041
9042 kind = "string address";
9043
8325cc63 9044 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 9045 {
9046 i386_operand_type type = current_templates->end[-1].operand_types[0];
9047
9048 if (!type.bitfield.baseindex
9049 || ((!i.mem_operands != !intel_syntax)
9050 && current_templates->end[-1].operand_types[1]
9051 .bitfield.baseindex))
9052 type = current_templates->end[-1].operand_types[1];
be05d201
L		 9053 expected_reg = hash_find (reg_hash,
9054 di_si[addr_mode][type.bitfield.esseg]);
9055
fc0763e6
JB		 9056 }
9057 else
be05d201 9058 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 9059
be05d201
L		 9060 if (i.base_reg != expected_reg
9061 || i.index_reg
fc0763e6 9062 || operand_type_check (i.types[this_operand], disp))
fc0763e6 9063 {
be05d201
L		 9064 /* The second memory operand must have the same size as
9065 the first one. */
9066 if (i.mem_operands
9067 && i.base_reg
9068 && !((addr_mode == CODE_64BIT
dc821c5f 9069 && i.base_reg->reg_type.bitfield.qword)
be05d201 9070 || (addr_mode == CODE_32BIT
dc821c5f
JB		 9071 ? i.base_reg->reg_type.bitfield.dword
9072 : i.base_reg->reg_type.bitfield.word)))
be05d201
L		 9073 goto bad_address;
9074
fc0763e6
JB		 9075 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9076 operand_string,
9077 intel_syntax ? '[' : '(',
9078 register_prefix,
be05d201 9079 expected_reg->reg_name,
fc0763e6 9080 intel_syntax ? ']' : ')');
be05d201 9081 return 1;
fc0763e6 9082 }
be05d201
L		 9083 else
9084 return 1;
9085
9086bad_address:
9087 as_bad (_("`%s' is not a valid %s expression"),
9088 operand_string, kind);
9089 return 0;
3e73aa7c
JH		 9090 }
9091 else
9092 {
be05d201
L		 9093 if (addr_mode != CODE_16BIT)
9094 {
9095 /* 32-bit/64-bit checks. */
9096 if ((i.base_reg
9097 && (addr_mode == CODE_64BIT
dc821c5f
JB		 9098 ? !i.base_reg->reg_type.bitfield.qword
9099 : !i.base_reg->reg_type.bitfield.dword)
be05d201
L		 9100 && (i.index_reg
9101 || (i.base_reg->reg_num
9102 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9103 || (i.index_reg
1b54b8d7
JB		 9104 && !i.index_reg->reg_type.bitfield.xmmword
9105 && !i.index_reg->reg_type.bitfield.ymmword
9106 && !i.index_reg->reg_type.bitfield.zmmword
be05d201 9107 && ((addr_mode == CODE_64BIT
dc821c5f 9108 ? !(i.index_reg->reg_type.bitfield.qword
be05d201 9109 || i.index_reg->reg_num == RegRiz)
dc821c5f 9110 : !(i.index_reg->reg_type.bitfield.dword
be05d201
L		 9111 || i.index_reg->reg_num == RegEiz))
9112 || !i.index_reg->reg_type.bitfield.baseindex)))
9113 goto bad_address;
8178be5b
JB		 9114
9115 /* bndmk, bndldx, and bndstx have special restrictions. */
9116 if (current_templates->start->base_opcode == 0xf30f1b
9117 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9118 {
9119 /* They cannot use RIP-relative addressing. */
9120 if (i.base_reg && i.base_reg->reg_num == RegRip)
9121 {
9122 as_bad (_("`%s' cannot be used here"), operand_string);
9123 return 0;
9124 }
9125
9126 /* bndldx and bndstx ignore their scale factor. */
9127 if (current_templates->start->base_opcode != 0xf30f1b
9128 && i.log2_scale_factor)
9129 as_warn (_("register scaling is being ignored here"));
9130 }
be05d201
L		 9131 }
9132 else
3e73aa7c 9133 {
be05d201 9134 /* 16-bit checks. */
3e73aa7c 9135 if ((i.base_reg
dc821c5f 9136 && (!i.base_reg->reg_type.bitfield.word
40fb9820 9137 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 9138 || (i.index_reg
dc821c5f 9139 && (!i.index_reg->reg_type.bitfield.word
40fb9820 9140 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 9141 || !(i.base_reg
9142 && i.base_reg->reg_num < 6
9143 && i.index_reg->reg_num >= 6
9144 && i.log2_scale_factor == 0))))
be05d201 9145 goto bad_address;
3e73aa7c
JH		 9146 }
9147 }
be05d201 9148 return 1;
24eab124 9149}
252b5132 9150
43234a1e
L		 9151/* Handle vector immediates. */
9152
9153static int
9154RC_SAE_immediate (const char *imm_start)
9155{
9156 unsigned int match_found, j;
9157 const char *pstr = imm_start;
9158 expressionS *exp;
9159
9160 if (*pstr != '{')
9161 return 0;
9162
9163 pstr++;
9164 match_found = 0;
9165 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9166 {
9167 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9168 {
9169 if (!i.rounding)
9170 {
9171 rc_op.type = RC_NamesTable[j].type;
9172 rc_op.operand = this_operand;
9173 i.rounding = &rc_op;
9174 }
9175 else
9176 {
9177 as_bad (_("duplicated `%s'"), imm_start);
9178 return 0;
9179 }
9180 pstr += RC_NamesTable[j].len;
9181 match_found = 1;
9182 break;
9183 }
9184 }
9185 if (!match_found)
9186 return 0;
9187
9188 if (*pstr++ != '}')
9189 {
9190 as_bad (_("Missing '}': '%s'"), imm_start);
9191 return 0;
9192 }
9193 /* RC/SAE immediate string should contain nothing more. */;
9194 if (*pstr != 0)
9195 {
9196 as_bad (_("Junk after '}': '%s'"), imm_start);
9197 return 0;
9198 }
9199
9200 exp = &im_expressions[i.imm_operands++];
9201 i.op[this_operand].imms = exp;
9202
9203 exp->X_op = O_constant;
9204 exp->X_add_number = 0;
9205 exp->X_add_symbol = (symbolS *) 0;
9206 exp->X_op_symbol = (symbolS *) 0;
9207
9208 i.types[this_operand].bitfield.imm8 = 1;
9209 return 1;
9210}
9211
8325cc63
JB		 9212/* Only string instructions can have a second memory operand, so
9213 reduce current_templates to just those if it contains any. */
9214static int
9215maybe_adjust_templates (void)
9216{
9217 const insn_template *t;
9218
9219 gas_assert (i.mem_operands == 1);
9220
9221 for (t = current_templates->start; t < current_templates->end; ++t)
9222 if (t->opcode_modifier.isstring)
9223 break;
9224
9225 if (t < current_templates->end)
9226 {
9227 static templates aux_templates;
9228 bfd_boolean recheck;
9229
9230 aux_templates.start = t;
9231 for (; t < current_templates->end; ++t)
9232 if (!t->opcode_modifier.isstring)
9233 break;
9234 aux_templates.end = t;
9235
9236 /* Determine whether to re-check the first memory operand. */
9237 recheck = (aux_templates.start != current_templates->start
9238 || t != current_templates->end);
9239
9240 current_templates = &aux_templates;
9241
9242 if (recheck)
9243 {
9244 i.mem_operands = 0;
9245 if (i.memop1_string != NULL
9246 && i386_index_check (i.memop1_string) == 0)
9247 return 0;
9248 i.mem_operands = 1;
9249 }
9250 }
9251
9252 return 1;
9253}
9254
fc0763e6 9255/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 9256 on error. */
252b5132 9257
252b5132 9258static int
a7619375 9259i386_att_operand (char *operand_string)
252b5132 9260{
af6bdddf
AM		 9261 const reg_entry *r;
9262 char *end_op;
24eab124 9263 char *op_string = operand_string;
252b5132 9264
24eab124 9265 if (is_space_char (*op_string))
252b5132
RH		 9266 ++op_string;
9267
24eab124 9268 /* We check for an absolute prefix (differentiating,
47926f60 9269 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 9270 if (*op_string == ABSOLUTE_PREFIX)
9271 {
9272 ++op_string;
9273 if (is_space_char (*op_string))
9274 ++op_string;
40fb9820 9275 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 9276 }
252b5132 9277
47926f60 9278 /* Check if operand is a register. */
4d1bb795 9279 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 9280 {
40fb9820
L		 9281 i386_operand_type temp;
9282
24eab124
AM		 9283 /* Check for a segment override by searching for ':' after a
9284 segment register. */
9285 op_string = end_op;
9286 if (is_space_char (*op_string))
9287 ++op_string;
40fb9820
L		 9288 if (*op_string == ':'
9289 && (r->reg_type.bitfield.sreg2
9290 || r->reg_type.bitfield.sreg3))
24eab124
AM		 9291 {
9292 switch (r->reg_num)
9293 {
9294 case 0:
9295 i.seg[i.mem_operands] = &es;
9296 break;
9297 case 1:
9298 i.seg[i.mem_operands] = &cs;
9299 break;
9300 case 2:
9301 i.seg[i.mem_operands] = &ss;
9302 break;
9303 case 3:
9304 i.seg[i.mem_operands] = &ds;
9305 break;
9306 case 4:
9307 i.seg[i.mem_operands] = &fs;
9308 break;
9309 case 5:
9310 i.seg[i.mem_operands] = &gs;
9311 break;
9312 }
252b5132 9313
24eab124 9314 /* Skip the ':' and whitespace. */
252b5132
RH		 9315 ++op_string;
9316 if (is_space_char (*op_string))
24eab124 9317 ++op_string;
252b5132 9318
24eab124
AM		 9319 if (!is_digit_char (*op_string)
9320 && !is_identifier_char (*op_string)
9321 && *op_string != '('
9322 && *op_string != ABSOLUTE_PREFIX)
9323 {
9324 as_bad (_("bad memory operand `%s'"), op_string);
9325 return 0;
9326 }
47926f60 9327 /* Handle case of %es:*foo. */
24eab124
AM		 9328 if (*op_string == ABSOLUTE_PREFIX)
9329 {
9330 ++op_string;
9331 if (is_space_char (*op_string))
9332 ++op_string;
40fb9820 9333 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 9334 }
9335 goto do_memory_reference;
9336 }
43234a1e
L		 9337
9338 /* Handle vector operations. */
9339 if (*op_string == '{')
9340 {
9341 op_string = check_VecOperations (op_string, NULL);
9342 if (op_string == NULL)
9343 return 0;
9344 }
9345
24eab124
AM		 9346 if (*op_string)
9347 {
d0b47220 9348 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 9349 return 0;
9350 }
40fb9820
L		 9351 temp = r->reg_type;
9352 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9353 i.types[this_operand] = operand_type_or (i.types[this_operand],
9354 temp);
7d5e4556 9355 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 9356 i.op[this_operand].regs = r;
24eab124
AM		 9357 i.reg_operands++;
9358 }
af6bdddf
AM		 9359 else if (*op_string == REGISTER_PREFIX)
9360 {
9361 as_bad (_("bad register name `%s'"), op_string);
9362 return 0;
9363 }
24eab124 9364 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 9365 {
24eab124 9366 ++op_string;
40fb9820 9367 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 9368 {
d0b47220 9369 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 9370 return 0;
9371 }
9372 if (!i386_immediate (op_string))
9373 return 0;
9374 }
43234a1e
L		 9375 else if (RC_SAE_immediate (operand_string))
9376 {
9377 /* If it is a RC or SAE immediate, do nothing. */
9378 ;
9379 }
24eab124
AM		 9380 else if (is_digit_char (*op_string)
9381 || is_identifier_char (*op_string)
d02603dc 9382 || *op_string == '"'
e5cb08ac 9383 || *op_string == '(')
24eab124 9384 {
47926f60 9385 /* This is a memory reference of some sort. */
af6bdddf 9386 char *base_string;
252b5132 9387
47926f60 9388 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 9389 char *displacement_string_start;
9390 char *displacement_string_end;
43234a1e 9391 char *vop_start;
252b5132 9392
24eab124 9393 do_memory_reference:
8325cc63
JB		 9394 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9395 return 0;
24eab124 9396 if ((i.mem_operands == 1
40fb9820 9397 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 9398 || i.mem_operands == 2)
9399 {
9400 as_bad (_("too many memory references for `%s'"),
9401 current_templates->start->name);
9402 return 0;
9403 }
252b5132 9404
24eab124
AM		 9405 /* Check for base index form. We detect the base index form by
9406 looking for an ')' at the end of the operand, searching
9407 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9408 after the '('. */
af6bdddf 9409 base_string = op_string + strlen (op_string);
c3332e24 9410
43234a1e
L		 9411 /* Handle vector operations. */
9412 vop_start = strchr (op_string, '{');
9413 if (vop_start && vop_start < base_string)
9414 {
9415 if (check_VecOperations (vop_start, base_string) == NULL)
9416 return 0;
9417 base_string = vop_start;
9418 }
9419
af6bdddf
AM		 9420 --base_string;
9421 if (is_space_char (*base_string))
9422 --base_string;
252b5132 9423
47926f60 9424 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 9425 displacement_string_start = op_string;
9426 displacement_string_end = base_string + 1;
252b5132 9427
24eab124
AM		 9428 if (*base_string == ')')
9429 {
af6bdddf 9430 char *temp_string;
24eab124
AM		 9431 unsigned int parens_balanced = 1;
9432 /* We've already checked that the number of left & right ()'s are
47926f60 9433 equal, so this loop will not be infinite. */
24eab124
AM		 9434 do
9435 {
9436 base_string--;
9437 if (*base_string == ')')
9438 parens_balanced++;
9439 if (*base_string == '(')
9440 parens_balanced--;
9441 }
9442 while (parens_balanced);
c3332e24 9443
af6bdddf 9444 temp_string = base_string;
c3332e24 9445
24eab124 9446 /* Skip past '(' and whitespace. */
252b5132
RH		 9447 ++base_string;
9448 if (is_space_char (*base_string))
24eab124 9449 ++base_string;
252b5132 9450
af6bdddf 9451 if (*base_string == ','
4eed87de
AM		 9452 || ((i.base_reg = parse_register (base_string, &end_op))
9453 != NULL))
252b5132 9454 {
af6bdddf 9455 displacement_string_end = temp_string;
252b5132 9456
40fb9820 9457 i.types[this_operand].bitfield.baseindex = 1;
252b5132 9458
af6bdddf 9459 if (i.base_reg)
24eab124 9460 {
24eab124
AM		 9461 base_string = end_op;
9462 if (is_space_char (*base_string))
9463 ++base_string;
af6bdddf
AM		 9464 }
9465
9466 /* There may be an index reg or scale factor here. */
9467 if (*base_string == ',')
9468 {
9469 ++base_string;
9470 if (is_space_char (*base_string))
9471 ++base_string;
9472
4eed87de
AM		 9473 if ((i.index_reg = parse_register (base_string, &end_op))
9474 != NULL)
24eab124 9475 {
af6bdddf 9476 base_string = end_op;
24eab124
AM		 9477 if (is_space_char (*base_string))
9478 ++base_string;
af6bdddf
AM		 9479 if (*base_string == ',')
9480 {
9481 ++base_string;
9482 if (is_space_char (*base_string))
9483 ++base_string;
9484 }
e5cb08ac 9485 else if (*base_string != ')')
af6bdddf 9486 {
4eed87de
AM		 9487 as_bad (_("expecting `,' or `)' "
9488 "after index register in `%s'"),
af6bdddf
AM		 9489 operand_string);
9490 return 0;
9491 }
24eab124 9492 }
af6bdddf 9493 else if (*base_string == REGISTER_PREFIX)
24eab124 9494 {
f76bf5e0
L		 9495 end_op = strchr (base_string, ',');
9496 if (end_op)
9497 *end_op = '\0';
af6bdddf 9498 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9499 return 0;
9500 }
252b5132 9501
47926f60 9502 /* Check for scale factor. */
551c1ca1 9503 if (*base_string != ')')
af6bdddf 9504 {
551c1ca1
AM		 9505 char *end_scale = i386_scale (base_string);
9506
9507 if (!end_scale)
af6bdddf 9508 return 0;
24eab124 9509
551c1ca1 9510 base_string = end_scale;
af6bdddf
AM		 9511 if (is_space_char (*base_string))
9512 ++base_string;
9513 if (*base_string != ')')
9514 {
4eed87de
AM		 9515 as_bad (_("expecting `)' "
9516 "after scale factor in `%s'"),
af6bdddf
AM		 9517 operand_string);
9518 return 0;
9519 }
9520 }
9521 else if (!i.index_reg)
24eab124 9522 {
4eed87de
AM		 9523 as_bad (_("expecting index register or scale factor "
9524 "after `,'; got '%c'"),
af6bdddf 9525 *base_string);
24eab124
AM		 9526 return 0;
9527 }
9528 }
af6bdddf 9529 else if (*base_string != ')')
24eab124 9530 {
4eed87de
AM		 9531 as_bad (_("expecting `,' or `)' "
9532 "after base register in `%s'"),
af6bdddf 9533 operand_string);
24eab124
AM		 9534 return 0;
9535 }
c3332e24 9536 }
af6bdddf 9537 else if (*base_string == REGISTER_PREFIX)
c3332e24 9538 {
f76bf5e0
L		 9539 end_op = strchr (base_string, ',');
9540 if (end_op)
9541 *end_op = '\0';
af6bdddf 9542 as_bad (_("bad register name `%s'"), base_string);
24eab124 9543 return 0;
c3332e24 9544 }
24eab124
AM		 9545 }
9546
9547 /* If there's an expression beginning the operand, parse it,
9548 assuming displacement_string_start and
9549 displacement_string_end are meaningful. */
9550 if (displacement_string_start != displacement_string_end)
9551 {
9552 if (!i386_displacement (displacement_string_start,
9553 displacement_string_end))
9554 return 0;
9555 }
9556
9557 /* Special case for (%dx) while doing input/output op. */
9558 if (i.base_reg
0dfbf9d7
L		 9559 && operand_type_equal (&i.base_reg->reg_type,
9560 &reg16_inoutportreg)
24eab124
AM		 9561 && i.index_reg == 0
9562 && i.log2_scale_factor == 0
9563 && i.seg[i.mem_operands] == 0
40fb9820 9564 && !operand_type_check (i.types[this_operand], disp))
24eab124 9565 {
65da13b5 9566 i.types[this_operand] = inoutportreg;
24eab124
AM		 9567 return 1;
9568 }
9569
eecb386c
AM		 9570 if (i386_index_check (operand_string) == 0)
9571 return 0;
5c07affc 9572 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9573 if (i.mem_operands == 0)
9574 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9575 i.mem_operands++;
9576 }
9577 else
ce8a8b2f
AM		 9578 {
9579 /* It's not a memory operand; argh! */
24eab124
AM		 9580 as_bad (_("invalid char %s beginning operand %d `%s'"),
9581 output_invalid (*op_string),
9582 this_operand + 1,
9583 op_string);
9584 return 0;
9585 }
47926f60 9586 return 1; /* Normal return. */
252b5132
RH		 9587}
9588\f
fa94de6b
RM		 9589/* Calculate the maximum variable size (i.e., excluding fr_fix)
9590 that an rs_machine_dependent frag may reach. */
9591
9592unsigned int
9593i386_frag_max_var (fragS *frag)
9594{
9595 /* The only relaxable frags are for jumps.
9596 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9597 gas_assert (frag->fr_type == rs_machine_dependent);
9598 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9599}
9600
b084df0b
L		 9601#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9602static int
8dcea932 9603elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9604{
9605 /* STT_GNU_IFUNC symbol must go through PLT. */
9606 if ((symbol_get_bfdsym (fr_symbol)->flags
9607 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9608 return 0;
9609
9610 if (!S_IS_EXTERNAL (fr_symbol))
9611 /* Symbol may be weak or local. */
9612 return !S_IS_WEAK (fr_symbol);
9613
8dcea932
L		 9614 /* Global symbols with non-default visibility can't be preempted. */
9615 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9616 return 1;
9617
9618 if (fr_var != NO_RELOC)
9619 switch ((enum bfd_reloc_code_real) fr_var)
9620 {
9621 case BFD_RELOC_386_PLT32:
9622 case BFD_RELOC_X86_64_PLT32:
33eaf5de 9623 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 9624 return 0;
9625 default:
9626 abort ();
9627 }
9628
b084df0b
L		 9629 /* Global symbols with default visibility in a shared library may be
9630 preempted by another definition. */
8dcea932 9631 return !shared;
b084df0b
L		 9632}
9633#endif
9634
ee7fcc42
AM		 9635/* md_estimate_size_before_relax()
9636
9637 Called just before relax() for rs_machine_dependent frags. The x86
9638 assembler uses these frags to handle variable size jump
9639 instructions.
9640
9641 Any symbol that is now undefined will not become defined.
9642 Return the correct fr_subtype in the frag.
9643 Return the initial "guess for variable size of frag" to caller.
9644 The guess is actually the growth beyond the fixed part. Whatever
9645 we do to grow the fixed or variable part contributes to our
9646 returned value. */
9647
252b5132 9648int
7016a5d5 9649md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9650{
252b5132 9651 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9652 check for un-relaxable symbols. On an ELF system, we can't relax
9653 an externally visible symbol, because it may be overridden by a
9654 shared library. */
9655 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9656#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9657 || (IS_ELF
8dcea932
L		 9658 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9659 fragP->fr_var))
fbeb56a4
DK		 9660#endif
9661#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9662 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9663 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9664#endif
9665 )
252b5132 9666 {
b98ef147
AM		 9667 /* Symbol is undefined in this segment, or we need to keep a
9668 reloc so that weak symbols can be overridden. */
9669 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9670 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9671 unsigned char *opcode;
9672 int old_fr_fix;
f6af82bd 9673
ee7fcc42 9674 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9675 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9676 else if (size == 2)
f6af82bd 9677 reloc_type = BFD_RELOC_16_PCREL;
bd7ab16b
L		 9678#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9679 else if (need_plt32_p (fragP->fr_symbol))
9680 reloc_type = BFD_RELOC_X86_64_PLT32;
9681#endif
f6af82bd
AM		 9682 else
9683 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9684
ee7fcc42
AM		 9685 old_fr_fix = fragP->fr_fix;
9686 opcode = (unsigned char *) fragP->fr_opcode;
9687
fddf5b5b 9688 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9689 {
fddf5b5b
AM		 9690 case UNCOND_JUMP:
9691 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9692 opcode[0] = 0xe9;
252b5132 9693 fragP->fr_fix += size;
062cd5e7
AS		 9694 fix_new (fragP, old_fr_fix, size,
9695 fragP->fr_symbol,
9696 fragP->fr_offset, 1,
9697 reloc_type);
252b5132
RH		 9698 break;
9699
fddf5b5b 9700 case COND_JUMP86:
412167cb
AM		 9701 if (size == 2
9702 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9703 {
9704 /* Negate the condition, and branch past an
9705 unconditional jump. */
9706 opcode[0] ^= 1;
9707 opcode[1] = 3;
9708 /* Insert an unconditional jump. */
9709 opcode[2] = 0xe9;
9710 /* We added two extra opcode bytes, and have a two byte
9711 offset. */
9712 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9713 fix_new (fragP, old_fr_fix + 2, 2,
9714 fragP->fr_symbol,
9715 fragP->fr_offset, 1,
9716 reloc_type);
fddf5b5b
AM		 9717 break;
9718 }
9719 /* Fall through. */
9720
9721 case COND_JUMP:
412167cb
AM		 9722 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9723 {
3e02c1cc
AM		 9724 fixS *fixP;
9725
412167cb 9726 fragP->fr_fix += 1;
3e02c1cc
AM		 9727 fixP = fix_new (fragP, old_fr_fix, 1,
9728 fragP->fr_symbol,
9729 fragP->fr_offset, 1,
9730 BFD_RELOC_8_PCREL);
9731 fixP->fx_signed = 1;
412167cb
AM		 9732 break;
9733 }
93c2a809 9734
24eab124 9735 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9736 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9737 opcode[1] = opcode[0] + 0x10;
f6af82bd 9738 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9739 /* We've added an opcode byte. */
9740 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9741 fix_new (fragP, old_fr_fix + 1, size,
9742 fragP->fr_symbol,
9743 fragP->fr_offset, 1,
9744 reloc_type);
252b5132 9745 break;
fddf5b5b
AM		 9746
9747 default:
9748 BAD_CASE (fragP->fr_subtype);
9749 break;
252b5132
RH		 9750 }
9751 frag_wane (fragP);
ee7fcc42 9752 return fragP->fr_fix - old_fr_fix;
252b5132 9753 }
93c2a809 9754
93c2a809
AM		 9755 /* Guess size depending on current relax state. Initially the relax
9756 state will correspond to a short jump and we return 1, because
9757 the variable part of the frag (the branch offset) is one byte
9758 long. However, we can relax a section more than once and in that
9759 case we must either set fr_subtype back to the unrelaxed state,
9760 or return the value for the appropriate branch. */
9761 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9762}
9763
47926f60
KH		 9764/* Called after relax() is finished.
9765
9766 In: Address of frag.
9767 fr_type == rs_machine_dependent.
9768 fr_subtype is what the address relaxed to.
9769
9770 Out: Any fixSs and constants are set up.
9771 Caller will turn frag into a ".space 0". */
9772
252b5132 9773void
7016a5d5
TG		 9774md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9775 fragS *fragP)
252b5132 9776{
29b0f896 9777 unsigned char *opcode;
252b5132 9778 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9779 offsetT target_address;
9780 offsetT opcode_address;
252b5132 9781 unsigned int extension = 0;
847f7ad4 9782 offsetT displacement_from_opcode_start;
252b5132
RH		 9783
9784 opcode = (unsigned char *) fragP->fr_opcode;
9785
47926f60 9786 /* Address we want to reach in file space. */
252b5132 9787 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9788
47926f60 9789 /* Address opcode resides at in file space. */
252b5132
RH		 9790 opcode_address = fragP->fr_address + fragP->fr_fix;
9791
47926f60 9792 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9793 displacement_from_opcode_start = target_address - opcode_address;
9794
fddf5b5b 9795 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9796 {
47926f60
KH		 9797 /* Don't have to change opcode. */
9798 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9799 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9800 }
9801 else
9802 {
9803 if (no_cond_jump_promotion
9804 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9805 as_warn_where (fragP->fr_file, fragP->fr_line,
9806 _("long jump required"));
252b5132 9807
fddf5b5b
AM		 9808 switch (fragP->fr_subtype)
9809 {
9810 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9811 extension = 4; /* 1 opcode + 4 displacement */
9812 opcode[0] = 0xe9;
9813 where_to_put_displacement = &opcode[1];
9814 break;
252b5132 9815
fddf5b5b
AM		 9816 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9817 extension = 2; /* 1 opcode + 2 displacement */
9818 opcode[0] = 0xe9;
9819 where_to_put_displacement = &opcode[1];
9820 break;
252b5132 9821
fddf5b5b
AM		 9822 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9823 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9824 extension = 5; /* 2 opcode + 4 displacement */
9825 opcode[1] = opcode[0] + 0x10;
9826 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9827 where_to_put_displacement = &opcode[2];
9828 break;
252b5132 9829
fddf5b5b
AM		 9830 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9831 extension = 3; /* 2 opcode + 2 displacement */
9832 opcode[1] = opcode[0] + 0x10;
9833 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9834 where_to_put_displacement = &opcode[2];
9835 break;
252b5132 9836
fddf5b5b
AM		 9837 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9838 extension = 4;
9839 opcode[0] ^= 1;
9840 opcode[1] = 3;
9841 opcode[2] = 0xe9;
9842 where_to_put_displacement = &opcode[3];
9843 break;
9844
9845 default:
9846 BAD_CASE (fragP->fr_subtype);
9847 break;
9848 }
252b5132 9849 }
fddf5b5b 9850
7b81dfbb
AJ		 9851 /* If size if less then four we are sure that the operand fits,
9852 but if it's 4, then it could be that the displacement is larger
9853 then -/+ 2GB. */
9854 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9855 && object_64bit
9856 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9857 + ((addressT) 1 << 31))
9858 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9859 {
9860 as_bad_where (fragP->fr_file, fragP->fr_line,
9861 _("jump target out of range"));
9862 /* Make us emit 0. */
9863 displacement_from_opcode_start = extension;
9864 }
47926f60 9865 /* Now put displacement after opcode. */
252b5132
RH		 9866 md_number_to_chars ((char *) where_to_put_displacement,
9867 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9868 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9869 fragP->fr_fix += extension;
9870}
9871\f
7016a5d5 9872/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9873 by our caller that we have all the info we need to fix it up.
9874
7016a5d5
TG		 9875 Parameter valP is the pointer to the value of the bits.
9876
252b5132
RH		 9877 On the 386, immediates, displacements, and data pointers are all in
9878 the same (little-endian) format, so we don't need to care about which
9879 we are handling. */
9880
94f592af 9881void
7016a5d5 9882md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9883{
94f592af 9884 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9885 valueT value = *valP;
252b5132 9886
f86103b7 9887#if !defined (TE_Mach)
93382f6d
AM		 9888 if (fixP->fx_pcrel)
9889 {
9890 switch (fixP->fx_r_type)
9891 {
5865bb77
ILT		 9892 default:
9893 break;
9894
d6ab8113
JB		 9895 case BFD_RELOC_64:
9896 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9897 break;
93382f6d 9898 case BFD_RELOC_32:
ae8887b5 9899 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9900 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9901 break;
9902 case BFD_RELOC_16:
9903 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9904 break;
9905 case BFD_RELOC_8:
9906 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9907 break;
9908 }
9909 }
252b5132 9910
a161fe53 9911 if (fixP->fx_addsy != NULL
31312f95 9912 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9913 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9914 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9915 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9916 && !use_rela_relocations)
252b5132 9917 {
31312f95
AM		 9918 /* This is a hack. There should be a better way to handle this.
9919 This covers for the fact that bfd_install_relocation will
9920 subtract the current location (for partial_inplace, PC relative
9921 relocations); see more below. */
252b5132 9922#ifndef OBJ_AOUT
718ddfc0 9923 if (IS_ELF
252b5132
RH		 9924#ifdef TE_PE
9925 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9926#endif
9927 )
9928 value += fixP->fx_where + fixP->fx_frag->fr_address;
9929#endif
9930#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9931 if (IS_ELF)
252b5132 9932 {
6539b54b 9933 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9934
6539b54b 9935 if ((sym_seg == seg
2f66722d 9936 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9937 && sym_seg != absolute_section))
af65af87 9938 && !generic_force_reloc (fixP))
2f66722d
AM		 9939 {
9940 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9941 bfd_install_relocation subtracts them out again. I think
9942 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9943 it. FIXME. */
9944 value += fixP->fx_where + fixP->fx_frag->fr_address;
9945 }
252b5132
RH		 9946 }
9947#endif
9948#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9949 /* For some reason, the PE format does not store a
9950 section address offset for a PC relative symbol. */
9951 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9952 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9953 value += md_pcrel_from (fixP);
9954#endif
9955 }
fbeb56a4 9956#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9957 if (fixP->fx_addsy != NULL
9958 && S_IS_WEAK (fixP->fx_addsy)
9959 /* PR 16858: Do not modify weak function references. */
9960 && ! fixP->fx_pcrel)
fbeb56a4 9961 {
296a8689
NC		 9962#if !defined (TE_PEP)
9963 /* For x86 PE weak function symbols are neither PC-relative
9964 nor do they set S_IS_FUNCTION. So the only reliable way
9965 to detect them is to check the flags of their containing
9966 section. */
9967 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9968 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9969 ;
9970 else
9971#endif
fbeb56a4
DK		 9972 value -= S_GET_VALUE (fixP->fx_addsy);
9973 }
9974#endif
252b5132
RH		 9975
9976 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9977 and we must not disappoint it. */
252b5132 9978#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9979 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9980 switch (fixP->fx_r_type)
9981 {
9982 case BFD_RELOC_386_PLT32:
3e73aa7c 9983 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9984 /* Make the jump instruction point to the address of the operand. At
9985 runtime we merely add the offset to the actual PLT entry. */
9986 value = -4;
9987 break;
31312f95 9988
13ae64f3
JJ		 9989 case BFD_RELOC_386_TLS_GD:
9990 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9991 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9992 case BFD_RELOC_386_TLS_IE:
9993 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9994 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9995 case BFD_RELOC_X86_64_TLSGD:
9996 case BFD_RELOC_X86_64_TLSLD:
9997 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9998 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9999 value = 0; /* Fully resolved at runtime. No addend. */
10000 /* Fallthrough */
10001 case BFD_RELOC_386_TLS_LE:
10002 case BFD_RELOC_386_TLS_LDO_32:
10003 case BFD_RELOC_386_TLS_LE_32:
10004 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10005 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 10006 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 10007 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 10008 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10009 break;
10010
67a4f2b7
AO		 10011 case BFD_RELOC_386_TLS_DESC_CALL:
10012 case BFD_RELOC_X86_64_TLSDESC_CALL:
10013 value = 0; /* Fully resolved at runtime. No addend. */
10014 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10015 fixP->fx_done = 0;
10016 return;
10017
47926f60
KH		 10018 case BFD_RELOC_VTABLE_INHERIT:
10019 case BFD_RELOC_VTABLE_ENTRY:
10020 fixP->fx_done = 0;
94f592af 10021 return;
47926f60
KH		 10022
10023 default:
10024 break;
10025 }
10026#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 10027 *valP = value;
f86103b7 10028#endif /* !defined (TE_Mach) */
3e73aa7c 10029
3e73aa7c 10030 /* Are we finished with this relocation now? */
c6682705 10031 if (fixP->fx_addsy == NULL)
3e73aa7c 10032 fixP->fx_done = 1;
fbeb56a4
DK		 10033#if defined (OBJ_COFF) && defined (TE_PE)
10034 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10035 {
10036 fixP->fx_done = 0;
10037 /* Remember value for tc_gen_reloc. */
10038 fixP->fx_addnumber = value;
10039 /* Clear out the frag for now. */
10040 value = 0;
10041 }
10042#endif
3e73aa7c
JH		 10043 else if (use_rela_relocations)
10044 {
10045 fixP->fx_no_overflow = 1;
062cd5e7
AS		 10046 /* Remember value for tc_gen_reloc. */
10047 fixP->fx_addnumber = value;
3e73aa7c
JH		 10048 value = 0;
10049 }
f86103b7 10050
94f592af 10051 md_number_to_chars (p, value, fixP->fx_size);
252b5132 10052}
252b5132 10053\f
6d4af3c2 10054const char *
499ac353 10055md_atof (int type, char *litP, int *sizeP)
252b5132 10056{
499ac353
NC		 10057 /* This outputs the LITTLENUMs in REVERSE order;
10058 in accord with the bigendian 386. */
10059 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 10060}
10061\f
2d545b82 10062static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 10063
252b5132 10064static char *
e3bb37b5 10065output_invalid (int c)
252b5132 10066{
3882b010 10067 if (ISPRINT (c))
f9f21a03
L		 10068 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10069 "'%c'", c);
252b5132 10070 else
f9f21a03 10071 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 10072 "(0x%x)", (unsigned char) c);
252b5132
RH		 10073 return output_invalid_buf;
10074}
10075
af6bdddf 10076/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 10077
10078static const reg_entry *
4d1bb795 10079parse_real_register (char *reg_string, char **end_op)
252b5132 10080{
af6bdddf
AM		 10081 char *s = reg_string;
10082 char *p;
252b5132
RH		 10083 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10084 const reg_entry *r;
10085
10086 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10087 if (*s == REGISTER_PREFIX)
10088 ++s;
10089
10090 if (is_space_char (*s))
10091 ++s;
10092
10093 p = reg_name_given;
af6bdddf 10094 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 10095 {
10096 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 10097 return (const reg_entry *) NULL;
10098 s++;
252b5132
RH		 10099 }
10100
6588847e
DN		 10101 /* For naked regs, make sure that we are not dealing with an identifier.
10102 This prevents confusing an identifier like `eax_var' with register
10103 `eax'. */
10104 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10105 return (const reg_entry *) NULL;
10106
af6bdddf 10107 *end_op = s;
252b5132
RH		 10108
10109 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10110
5f47d35b 10111 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 10112 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 10113 {
5f47d35b
AM		 10114 if (is_space_char (*s))
10115 ++s;
10116 if (*s == '(')
10117 {
af6bdddf 10118 ++s;
5f47d35b
AM		 10119 if (is_space_char (*s))
10120 ++s;
10121 if (*s >= '0' && *s <= '7')
10122 {
db557034 10123 int fpr = *s - '0';
af6bdddf 10124 ++s;
5f47d35b
AM		 10125 if (is_space_char (*s))
10126 ++s;
10127 if (*s == ')')
10128 {
10129 *end_op = s + 1;
1e9cc1c2 10130 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 10131 know (r);
10132 return r + fpr;
5f47d35b 10133 }
5f47d35b 10134 }
47926f60 10135 /* We have "%st(" then garbage. */
5f47d35b
AM		 10136 return (const reg_entry *) NULL;
10137 }
10138 }
10139
a60de03c
JB		 10140 if (r == NULL || allow_pseudo_reg)
10141 return r;
10142
0dfbf9d7 10143 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 10144 return (const reg_entry *) NULL;
10145
dc821c5f 10146 if ((r->reg_type.bitfield.dword
192dc9c6
JB		 10147 || r->reg_type.bitfield.sreg3
10148 || r->reg_type.bitfield.control
10149 || r->reg_type.bitfield.debug
10150 || r->reg_type.bitfield.test)
10151 && !cpu_arch_flags.bitfield.cpui386)
10152 return (const reg_entry *) NULL;
10153
ca0d63fe 10154 if (r->reg_type.bitfield.tbyte
309d3373
JB		 10155 && !cpu_arch_flags.bitfield.cpu8087
10156 && !cpu_arch_flags.bitfield.cpu287
10157 && !cpu_arch_flags.bitfield.cpu387)
10158 return (const reg_entry *) NULL;
10159
1848e567 10160 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
192dc9c6
JB		 10161 return (const reg_entry *) NULL;
10162
1b54b8d7 10163 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
192dc9c6
JB		 10164 return (const reg_entry *) NULL;
10165
1b54b8d7 10166 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
40f12533
L		 10167 return (const reg_entry *) NULL;
10168
1b54b8d7 10169 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
1848e567
L		 10170 return (const reg_entry *) NULL;
10171
10172 if (r->reg_type.bitfield.regmask
10173 && !cpu_arch_flags.bitfield.cpuregmask)
43234a1e
L		 10174 return (const reg_entry *) NULL;
10175
db51cc60 10176 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 10177 if (!allow_index_reg
db51cc60
L		 10178 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10179 return (const reg_entry *) NULL;
10180
43234a1e
L		 10181 /* Upper 16 vector register is only available with VREX in 64bit
10182 mode. */
10183 if ((r->reg_flags & RegVRex))
10184 {
86fa6981
L		 10185 if (i.vec_encoding == vex_encoding_default)
10186 i.vec_encoding = vex_encoding_evex;
10187
43234a1e 10188 if (!cpu_arch_flags.bitfield.cpuvrex
86fa6981 10189 || i.vec_encoding != vex_encoding_evex
43234a1e
L		 10190 || flag_code != CODE_64BIT)
10191 return (const reg_entry *) NULL;
43234a1e
L		 10192 }
10193
a60de03c 10194 if (((r->reg_flags & (RegRex64 | RegRex))
dc821c5f 10195 || r->reg_type.bitfield.qword)
40fb9820 10196 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 10197 || !operand_type_equal (&r->reg_type, &control))
1ae00879 10198 && flag_code != CODE_64BIT)
20f0a1fc 10199 return (const reg_entry *) NULL;
1ae00879 10200
b7240065
JB		 10201 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10202 return (const reg_entry *) NULL;
10203
252b5132
RH		 10204 return r;
10205}
4d1bb795
JB		 10206
10207/* REG_STRING starts *before* REGISTER_PREFIX. */
10208
10209static const reg_entry *
10210parse_register (char *reg_string, char **end_op)
10211{
10212 const reg_entry *r;
10213
10214 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10215 r = parse_real_register (reg_string, end_op);
10216 else
10217 r = NULL;
10218 if (!r)
10219 {
10220 char *save = input_line_pointer;
10221 char c;
10222 symbolS *symbolP;
10223
10224 input_line_pointer = reg_string;
d02603dc 10225 c = get_symbol_name (&reg_string);
4d1bb795
JB		 10226 symbolP = symbol_find (reg_string);
10227 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10228 {
10229 const expressionS *e = symbol_get_value_expression (symbolP);
10230
0398aac5 10231 know (e->X_op == O_register);
4eed87de 10232 know (e->X_add_number >= 0
c3fe08fa 10233 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 10234 r = i386_regtab + e->X_add_number;
d3bb6b49 10235 if ((r->reg_flags & RegVRex))
86fa6981 10236 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 10237 *end_op = input_line_pointer;
10238 }
10239 *input_line_pointer = c;
10240 input_line_pointer = save;
10241 }
10242 return r;
10243}
10244
10245int
10246i386_parse_name (char *name, expressionS *e, char *nextcharP)
10247{
10248 const reg_entry *r;
10249 char *end = input_line_pointer;
10250
10251 *end = *nextcharP;
10252 r = parse_register (name, &input_line_pointer);
10253 if (r && end <= input_line_pointer)
10254 {
10255 *nextcharP = *input_line_pointer;
10256 *input_line_pointer = 0;
10257 e->X_op = O_register;
10258 e->X_add_number = r - i386_regtab;
10259 return 1;
10260 }
10261 input_line_pointer = end;
10262 *end = 0;
ee86248c 10263 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 10264}
10265
10266void
10267md_operand (expressionS *e)
10268{
ee86248c
JB		 10269 char *end;
10270 const reg_entry *r;
4d1bb795 10271
ee86248c
JB		 10272 switch (*input_line_pointer)
10273 {
10274 case REGISTER_PREFIX:
10275 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 10276 if (r)
10277 {
10278 e->X_op = O_register;
10279 e->X_add_number = r - i386_regtab;
10280 input_line_pointer = end;
10281 }
ee86248c
JB		 10282 break;
10283
10284 case '[':
9c2799c2 10285 gas_assert (intel_syntax);
ee86248c
JB		 10286 end = input_line_pointer++;
10287 expression (e);
10288 if (*input_line_pointer == ']')
10289 {
10290 ++input_line_pointer;
10291 e->X_op_symbol = make_expr_symbol (e);
10292 e->X_add_symbol = NULL;
10293 e->X_add_number = 0;
10294 e->X_op = O_index;
10295 }
10296 else
10297 {
10298 e->X_op = O_absent;
10299 input_line_pointer = end;
10300 }
10301 break;
4d1bb795
JB		 10302 }
10303}
10304
252b5132 10305\f
4cc782b5 10306#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
b6f8c7c4 10307const char *md_shortopts = "kVQ:sqnO::";
252b5132 10308#else
b6f8c7c4 10309const char *md_shortopts = "qnO::";
252b5132 10310#endif
6e0b89ee 10311
3e73aa7c 10312#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 10313#define OPTION_64 (OPTION_MD_BASE + 1)
10314#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 10315#define OPTION_MARCH (OPTION_MD_BASE + 3)
10316#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 10317#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10318#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10319#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10320#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
bd5dea88 10321#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
c0f3af97 10322#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 10323#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 10324#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10325#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10326#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 10327#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 10328#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10329#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 10330#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 10331#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 10332#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 10333#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 10334#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10335#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 10336#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
b3b91714 10337
99ad8390
NC		 10338struct option md_longopts[] =
10339{
3e73aa7c 10340 {"32", no_argument, NULL, OPTION_32},
321098a5 10341#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10342 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 10343 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 10344#endif
10345#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10346 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 10347 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 10348#endif
b3b91714 10349 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 10350 {"march", required_argument, NULL, OPTION_MARCH},
10351 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 10352 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10353 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10354 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10355 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
c0f3af97 10356 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 10357 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 10358 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 10359 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 10360 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 10361 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10362 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 10363# if defined (TE_PE) || defined (TE_PEP)
10364 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10365#endif
d1982f93 10366 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 10367 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 10368 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 10369 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 10370 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10371 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 10372 {NULL, no_argument, NULL, 0}
10373};
10374size_t md_longopts_size = sizeof (md_longopts);
10375
10376int
17b9d67d 10377md_parse_option (int c, const char *arg)
252b5132 10378{
91d6fa6a 10379 unsigned int j;
293f5f65 10380 char *arch, *next, *saved;
9103f4f4 10381
252b5132
RH		 10382 switch (c)
10383 {
12b55ccc
L		 10384 case 'n':
10385 optimize_align_code = 0;
10386 break;
10387
a38cf1db
AM		 10388 case 'q':
10389 quiet_warnings = 1;
252b5132
RH		 10390 break;
10391
10392#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 10393 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10394 should be emitted or not. FIXME: Not implemented. */
10395 case 'Q':
252b5132
RH		 10396 break;
10397
10398 /* -V: SVR4 argument to print version ID. */
10399 case 'V':
10400 print_version_id ();
10401 break;
10402
a38cf1db
AM		 10403 /* -k: Ignore for FreeBSD compatibility. */
10404 case 'k':
252b5132 10405 break;
4cc782b5
ILT		 10406
10407 case 's':
10408 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 10409 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 10410 break;
8dcea932
L		 10411
10412 case OPTION_MSHARED:
10413 shared = 1;
10414 break;
99ad8390 10415#endif
321098a5 10416#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10417 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 10418 case OPTION_64:
10419 {
10420 const char **list, **l;
10421
3e73aa7c
JH		 10422 list = bfd_target_list ();
10423 for (l = list; *l != NULL; l++)
8620418b 10424 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 10425 || strcmp (*l, "coff-x86-64") == 0
10426 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 10427 || strcmp (*l, "pei-x86-64") == 0
10428 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 10429 {
10430 default_arch = "x86_64";
10431 break;
10432 }
3e73aa7c 10433 if (*l == NULL)
2b5d6a91 10434 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 10435 free (list);
10436 }
10437 break;
10438#endif
252b5132 10439
351f65ca 10440#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10441 case OPTION_X32:
351f65ca
L		 10442 if (IS_ELF)
10443 {
10444 const char **list, **l;
10445
10446 list = bfd_target_list ();
10447 for (l = list; *l != NULL; l++)
10448 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10449 {
10450 default_arch = "x86_64:32";
10451 break;
10452 }
10453 if (*l == NULL)
2b5d6a91 10454 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 10455 free (list);
10456 }
10457 else
10458 as_fatal (_("32bit x86_64 is only supported for ELF"));
10459 break;
10460#endif
10461
6e0b89ee
AM		 10462 case OPTION_32:
10463 default_arch = "i386";
10464 break;
10465
b3b91714
AM		 10466 case OPTION_DIVIDE:
10467#ifdef SVR4_COMMENT_CHARS
10468 {
10469 char *n, *t;
10470 const char *s;
10471
add39d23 10472 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 10473 t = n;
10474 for (s = i386_comment_chars; *s != '\0'; s++)
10475 if (*s != '/')
10476 *t++ = *s;
10477 *t = '\0';
10478 i386_comment_chars = n;
10479 }
10480#endif
10481 break;
10482
9103f4f4 10483 case OPTION_MARCH:
293f5f65
L		 10484 saved = xstrdup (arg);
10485 arch = saved;
10486 /* Allow -march=+nosse. */
10487 if (*arch == '+')
10488 arch++;
6305a203 10489 do
9103f4f4 10490 {
6305a203 10491 if (*arch == '.')
2b5d6a91 10492 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10493 next = strchr (arch, '+');
10494 if (next)
10495 *next++ = '\0';
91d6fa6a 10496 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10497 {
91d6fa6a 10498 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10499 {
6305a203 10500 /* Processor. */
1ded5609
JB		 10501 if (! cpu_arch[j].flags.bitfield.cpui386)
10502 continue;
10503
91d6fa6a 10504 cpu_arch_name = cpu_arch[j].name;
6305a203 10505 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10506 cpu_arch_flags = cpu_arch[j].flags;
10507 cpu_arch_isa = cpu_arch[j].type;
10508 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10509 if (!cpu_arch_tune_set)
10510 {
10511 cpu_arch_tune = cpu_arch_isa;
10512 cpu_arch_tune_flags = cpu_arch_isa_flags;
10513 }
10514 break;
10515 }
91d6fa6a
NC		 10516 else if (*cpu_arch [j].name == '.'
10517 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 10518 {
33eaf5de 10519 /* ISA extension. */
6305a203 10520 i386_cpu_flags flags;
309d3373 10521
293f5f65
L		 10522 flags = cpu_flags_or (cpu_arch_flags,
10523 cpu_arch[j].flags);
81486035 10524
5b64d091 10525 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10526 {
10527 if (cpu_sub_arch_name)
10528 {
10529 char *name = cpu_sub_arch_name;
10530 cpu_sub_arch_name = concat (name,
91d6fa6a 10531 cpu_arch[j].name,
1bf57e9f 10532 (const char *) NULL);
6305a203
L		 10533 free (name);
10534 }
10535 else
91d6fa6a 10536 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10537 cpu_arch_flags = flags;
a586129e 10538 cpu_arch_isa_flags = flags;
6305a203 10539 }
0089dace
L		 10540 else
10541 cpu_arch_isa_flags
10542 = cpu_flags_or (cpu_arch_isa_flags,
10543 cpu_arch[j].flags);
6305a203 10544 break;
ccc9c027 10545 }
9103f4f4 10546 }
6305a203 10547
293f5f65
L		 10548 if (j >= ARRAY_SIZE (cpu_arch))
10549 {
33eaf5de 10550 /* Disable an ISA extension. */
293f5f65
L		 10551 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10552 if (strcmp (arch, cpu_noarch [j].name) == 0)
10553 {
10554 i386_cpu_flags flags;
10555
10556 flags = cpu_flags_and_not (cpu_arch_flags,
10557 cpu_noarch[j].flags);
10558 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10559 {
10560 if (cpu_sub_arch_name)
10561 {
10562 char *name = cpu_sub_arch_name;
10563 cpu_sub_arch_name = concat (arch,
10564 (const char *) NULL);
10565 free (name);
10566 }
10567 else
10568 cpu_sub_arch_name = xstrdup (arch);
10569 cpu_arch_flags = flags;
10570 cpu_arch_isa_flags = flags;
10571 }
10572 break;
10573 }
10574
10575 if (j >= ARRAY_SIZE (cpu_noarch))
10576 j = ARRAY_SIZE (cpu_arch);
10577 }
10578
91d6fa6a 10579 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10580 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10581
10582 arch = next;
9103f4f4 10583 }
293f5f65
L		 10584 while (next != NULL);
10585 free (saved);
9103f4f4
L		 10586 break;
10587
10588 case OPTION_MTUNE:
10589 if (*arg == '.')
2b5d6a91 10590 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10591 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10592 {
91d6fa6a 10593 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10594 {
ccc9c027 10595 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10596 cpu_arch_tune = cpu_arch [j].type;
10597 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10598 break;
10599 }
10600 }
91d6fa6a 10601 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10602 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10603 break;
10604
1efbbeb4
L		 10605 case OPTION_MMNEMONIC:
10606 if (strcasecmp (arg, "att") == 0)
10607 intel_mnemonic = 0;
10608 else if (strcasecmp (arg, "intel") == 0)
10609 intel_mnemonic = 1;
10610 else
2b5d6a91 10611 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10612 break;
10613
10614 case OPTION_MSYNTAX:
10615 if (strcasecmp (arg, "att") == 0)
10616 intel_syntax = 0;
10617 else if (strcasecmp (arg, "intel") == 0)
10618 intel_syntax = 1;
10619 else
2b5d6a91 10620 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10621 break;
10622
10623 case OPTION_MINDEX_REG:
10624 allow_index_reg = 1;
10625 break;
10626
10627 case OPTION_MNAKED_REG:
10628 allow_naked_reg = 1;
10629 break;
10630
c0f3af97
L		 10631 case OPTION_MSSE2AVX:
10632 sse2avx = 1;
10633 break;
10634
daf50ae7
L		 10635 case OPTION_MSSE_CHECK:
10636 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10637 sse_check = check_error;
daf50ae7 10638 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10639 sse_check = check_warning;
daf50ae7 10640 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10641 sse_check = check_none;
daf50ae7 10642 else
2b5d6a91 10643 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10644 break;
10645
7bab8ab5
JB		 10646 case OPTION_MOPERAND_CHECK:
10647 if (strcasecmp (arg, "error") == 0)
10648 operand_check = check_error;
10649 else if (strcasecmp (arg, "warning") == 0)
10650 operand_check = check_warning;
10651 else if (strcasecmp (arg, "none") == 0)
10652 operand_check = check_none;
10653 else
10654 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10655 break;
10656
539f890d
L		 10657 case OPTION_MAVXSCALAR:
10658 if (strcasecmp (arg, "128") == 0)
10659 avxscalar = vex128;
10660 else if (strcasecmp (arg, "256") == 0)
10661 avxscalar = vex256;
10662 else
2b5d6a91 10663 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10664 break;
10665
7e8b059b
L		 10666 case OPTION_MADD_BND_PREFIX:
10667 add_bnd_prefix = 1;
10668 break;
10669
43234a1e
L		 10670 case OPTION_MEVEXLIG:
10671 if (strcmp (arg, "128") == 0)
10672 evexlig = evexl128;
10673 else if (strcmp (arg, "256") == 0)
10674 evexlig = evexl256;
10675 else if (strcmp (arg, "512") == 0)
10676 evexlig = evexl512;
10677 else
10678 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10679 break;
10680
d3d3c6db
IT		 10681 case OPTION_MEVEXRCIG:
10682 if (strcmp (arg, "rne") == 0)
10683 evexrcig = rne;
10684 else if (strcmp (arg, "rd") == 0)
10685 evexrcig = rd;
10686 else if (strcmp (arg, "ru") == 0)
10687 evexrcig = ru;
10688 else if (strcmp (arg, "rz") == 0)
10689 evexrcig = rz;
10690 else
10691 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10692 break;
10693
43234a1e
L		 10694 case OPTION_MEVEXWIG:
10695 if (strcmp (arg, "0") == 0)
10696 evexwig = evexw0;
10697 else if (strcmp (arg, "1") == 0)
10698 evexwig = evexw1;
10699 else
10700 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10701 break;
10702
167ad85b
TG		 10703# if defined (TE_PE) || defined (TE_PEP)
10704 case OPTION_MBIG_OBJ:
10705 use_big_obj = 1;
10706 break;
10707#endif
10708
d1982f93 10709 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10710 if (strcasecmp (arg, "yes") == 0)
10711 omit_lock_prefix = 1;
10712 else if (strcasecmp (arg, "no") == 0)
10713 omit_lock_prefix = 0;
10714 else
10715 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10716 break;
10717
e4e00185
AS		 10718 case OPTION_MFENCE_AS_LOCK_ADD:
10719 if (strcasecmp (arg, "yes") == 0)
10720 avoid_fence = 1;
10721 else if (strcasecmp (arg, "no") == 0)
10722 avoid_fence = 0;
10723 else
10724 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10725 break;
10726
0cb4071e
L		 10727 case OPTION_MRELAX_RELOCATIONS:
10728 if (strcasecmp (arg, "yes") == 0)
10729 generate_relax_relocations = 1;
10730 else if (strcasecmp (arg, "no") == 0)
10731 generate_relax_relocations = 0;
10732 else
10733 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10734 break;
10735
5db04b09 10736 case OPTION_MAMD64:
e89c5eaa 10737 intel64 = 0;
5db04b09
L		 10738 break;
10739
10740 case OPTION_MINTEL64:
e89c5eaa 10741 intel64 = 1;
5db04b09
L		 10742 break;
10743
b6f8c7c4
L		 10744 case 'O':
10745 if (arg == NULL)
10746 {
10747 optimize = 1;
10748 /* Turn off -Os. */
10749 optimize_for_space = 0;
10750 }
10751 else if (*arg == 's')
10752 {
10753 optimize_for_space = 1;
10754 /* Turn on all encoding optimizations. */
10755 optimize = -1;
10756 }
10757 else
10758 {
10759 optimize = atoi (arg);
10760 /* Turn off -Os. */
10761 optimize_for_space = 0;
10762 }
10763 break;
10764
252b5132
RH		 10765 default:
10766 return 0;
10767 }
10768 return 1;
10769}
10770
8a2c8fef
L		 10771#define MESSAGE_TEMPLATE \
10772" "
10773
293f5f65
L		 10774static char *
10775output_message (FILE *stream, char *p, char *message, char *start,
10776 int *left_p, const char *name, int len)
10777{
10778 int size = sizeof (MESSAGE_TEMPLATE);
10779 int left = *left_p;
10780
10781 /* Reserve 2 spaces for ", " or ",\0" */
10782 left -= len + 2;
10783
10784 /* Check if there is any room. */
10785 if (left >= 0)
10786 {
10787 if (p != start)
10788 {
10789 *p++ = ',';
10790 *p++ = ' ';
10791 }
10792 p = mempcpy (p, name, len);
10793 }
10794 else
10795 {
10796 /* Output the current message now and start a new one. */
10797 *p++ = ',';
10798 *p = '\0';
10799 fprintf (stream, "%s\n", message);
10800 p = start;
10801 left = size - (start - message) - len - 2;
10802
10803 gas_assert (left >= 0);
10804
10805 p = mempcpy (p, name, len);
10806 }
10807
10808 *left_p = left;
10809 return p;
10810}
10811
8a2c8fef 10812static void
1ded5609 10813show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10814{
10815 static char message[] = MESSAGE_TEMPLATE;
10816 char *start = message + 27;
10817 char *p;
10818 int size = sizeof (MESSAGE_TEMPLATE);
10819 int left;
10820 const char *name;
10821 int len;
10822 unsigned int j;
10823
10824 p = start;
10825 left = size - (start - message);
10826 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10827 {
10828 /* Should it be skipped? */
10829 if (cpu_arch [j].skip)
10830 continue;
10831
10832 name = cpu_arch [j].name;
10833 len = cpu_arch [j].len;
10834 if (*name == '.')
10835 {
10836 /* It is an extension. Skip if we aren't asked to show it. */
10837 if (ext)
10838 {
10839 name++;
10840 len--;
10841 }
10842 else
10843 continue;
10844 }
10845 else if (ext)
10846 {
10847 /* It is an processor. Skip if we show only extension. */
10848 continue;
10849 }
1ded5609
JB		 10850 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10851 {
10852 /* It is an impossible processor - skip. */
10853 continue;
10854 }
8a2c8fef 10855
293f5f65 10856 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10857 }
10858
293f5f65
L		 10859 /* Display disabled extensions. */
10860 if (ext)
10861 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10862 {
10863 name = cpu_noarch [j].name;
10864 len = cpu_noarch [j].len;
10865 p = output_message (stream, p, message, start, &left, name,
10866 len);
10867 }
10868
8a2c8fef
L		 10869 *p = '\0';
10870 fprintf (stream, "%s\n", message);
10871}
10872
252b5132 10873void
8a2c8fef 10874md_show_usage (FILE *stream)
252b5132 10875{
4cc782b5
ILT		 10876#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10877 fprintf (stream, _("\
a38cf1db
AM		 10878 -Q ignored\n\
10879 -V print assembler version number\n\
b3b91714
AM		 10880 -k ignored\n"));
10881#endif
10882 fprintf (stream, _("\
12b55ccc 10883 -n Do not optimize code alignment\n\
b3b91714
AM		 10884 -q quieten some warnings\n"));
10885#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10886 fprintf (stream, _("\
a38cf1db 10887 -s ignored\n"));
b3b91714 10888#endif
321098a5
L		 10889#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10890 || defined (TE_PE) || defined (TE_PEP))
751d281c 10891 fprintf (stream, _("\
570561f7 10892 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10893#endif
b3b91714
AM		 10894#ifdef SVR4_COMMENT_CHARS
10895 fprintf (stream, _("\
10896 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10897#else
10898 fprintf (stream, _("\
b3b91714 10899 --divide ignored\n"));
4cc782b5 10900#endif
9103f4f4 10901 fprintf (stream, _("\
6305a203 10902 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10903 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10904 show_arch (stream, 0, 1);
8a2c8fef
L		 10905 fprintf (stream, _("\
10906 EXTENSION is combination of:\n"));
1ded5609 10907 show_arch (stream, 1, 0);
6305a203 10908 fprintf (stream, _("\
8a2c8fef 10909 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10910 show_arch (stream, 0, 0);
ba104c83 10911 fprintf (stream, _("\
c0f3af97
L		 10912 -msse2avx encode SSE instructions with VEX prefix\n"));
10913 fprintf (stream, _("\
daf50ae7
L		 10914 -msse-check=[none|error|warning]\n\
10915 check SSE instructions\n"));
10916 fprintf (stream, _("\
7bab8ab5
JB		 10917 -moperand-check=[none|error|warning]\n\
10918 check operand combinations for validity\n"));
10919 fprintf (stream, _("\
539f890d
L		 10920 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10921 length\n"));
10922 fprintf (stream, _("\
43234a1e
L		 10923 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10924 length\n"));
10925 fprintf (stream, _("\
10926 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10927 for EVEX.W bit ignored instructions\n"));
10928 fprintf (stream, _("\
d3d3c6db
IT		 10929 -mevexrcig=[rne|rd|ru|rz]\n\
10930 encode EVEX instructions with specific EVEX.RC value\n\
10931 for SAE-only ignored instructions\n"));
10932 fprintf (stream, _("\
ba104c83
L		 10933 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10934 fprintf (stream, _("\
10935 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10936 fprintf (stream, _("\
10937 -mindex-reg support pseudo index registers\n"));
10938 fprintf (stream, _("\
10939 -mnaked-reg don't require `%%' prefix for registers\n"));
10940 fprintf (stream, _("\
7e8b059b 10941 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10942 fprintf (stream, _("\
10943 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10944# if defined (TE_PE) || defined (TE_PEP)
10945 fprintf (stream, _("\
10946 -mbig-obj generate big object files\n"));
10947#endif
d022bddd
IT		 10948 fprintf (stream, _("\
10949 -momit-lock-prefix=[no|yes]\n\
10950 strip all lock prefixes\n"));
5db04b09 10951 fprintf (stream, _("\
e4e00185
AS		 10952 -mfence-as-lock-add=[no|yes]\n\
10953 encode lfence, mfence and sfence as\n\
10954 lock addl $0x0, (%%{re}sp)\n"));
10955 fprintf (stream, _("\
0cb4071e
L		 10956 -mrelax-relocations=[no|yes]\n\
10957 generate relax relocations\n"));
10958 fprintf (stream, _("\
5db04b09
L		 10959 -mamd64 accept only AMD64 ISA\n"));
10960 fprintf (stream, _("\
10961 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10962}
10963
3e73aa7c 10964#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10965 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10966 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10967
10968/* Pick the target format to use. */
10969
47926f60 10970const char *
e3bb37b5 10971i386_target_format (void)
252b5132 10972{
351f65ca
L		 10973 if (!strncmp (default_arch, "x86_64", 6))
10974 {
10975 update_code_flag (CODE_64BIT, 1);
10976 if (default_arch[6] == '\0')
7f56bc95 10977 x86_elf_abi = X86_64_ABI;
351f65ca 10978 else
7f56bc95 10979 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10980 }
3e73aa7c 10981 else if (!strcmp (default_arch, "i386"))
78f12dd3 10982 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10983 else if (!strcmp (default_arch, "iamcu"))
10984 {
10985 update_code_flag (CODE_32BIT, 1);
10986 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10987 {
10988 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10989 cpu_arch_name = "iamcu";
10990 cpu_sub_arch_name = NULL;
10991 cpu_arch_flags = iamcu_flags;
10992 cpu_arch_isa = PROCESSOR_IAMCU;
10993 cpu_arch_isa_flags = iamcu_flags;
10994 if (!cpu_arch_tune_set)
10995 {
10996 cpu_arch_tune = cpu_arch_isa;
10997 cpu_arch_tune_flags = cpu_arch_isa_flags;
10998 }
10999 }
8d471ec1 11000 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 11001 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11002 cpu_arch_name);
11003 }
3e73aa7c 11004 else
2b5d6a91 11005 as_fatal (_("unknown architecture"));
89507696
JB		 11006
11007 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11008 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11009 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11010 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11011
252b5132
RH		 11012 switch (OUTPUT_FLAVOR)
11013 {
9384f2ff 11014#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 11015 case bfd_target_aout_flavour:
47926f60 11016 return AOUT_TARGET_FORMAT;
4c63da97 11017#endif
9384f2ff
AM		 11018#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11019# if defined (TE_PE) || defined (TE_PEP)
11020 case bfd_target_coff_flavour:
167ad85b
TG		 11021 if (flag_code == CODE_64BIT)
11022 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11023 else
11024 return "pe-i386";
9384f2ff 11025# elif defined (TE_GO32)
0561d57c
JK		 11026 case bfd_target_coff_flavour:
11027 return "coff-go32";
9384f2ff 11028# else
252b5132
RH		 11029 case bfd_target_coff_flavour:
11030 return "coff-i386";
9384f2ff 11031# endif
4c63da97 11032#endif
3e73aa7c 11033#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 11034 case bfd_target_elf_flavour:
3e73aa7c 11035 {
351f65ca
L		 11036 const char *format;
11037
11038 switch (x86_elf_abi)
4fa24527 11039 {
351f65ca
L		 11040 default:
11041 format = ELF_TARGET_FORMAT;
11042 break;
7f56bc95 11043 case X86_64_ABI:
351f65ca 11044 use_rela_relocations = 1;
4fa24527 11045 object_64bit = 1;
351f65ca
L		 11046 format = ELF_TARGET_FORMAT64;
11047 break;
7f56bc95 11048 case X86_64_X32_ABI:
4fa24527 11049 use_rela_relocations = 1;
351f65ca 11050 object_64bit = 1;
862be3fb 11051 disallow_64bit_reloc = 1;
351f65ca
L		 11052 format = ELF_TARGET_FORMAT32;
11053 break;
4fa24527 11054 }
3632d14b 11055 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 11056 {
7f56bc95 11057 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 11058 as_fatal (_("Intel L1OM is 64bit only"));
11059 return ELF_TARGET_L1OM_FORMAT;
11060 }
b49f93f6 11061 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 11062 {
11063 if (x86_elf_abi != X86_64_ABI)
11064 as_fatal (_("Intel K1OM is 64bit only"));
11065 return ELF_TARGET_K1OM_FORMAT;
11066 }
81486035
L		 11067 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11068 {
11069 if (x86_elf_abi != I386_ABI)
11070 as_fatal (_("Intel MCU is 32bit only"));
11071 return ELF_TARGET_IAMCU_FORMAT;
11072 }
8a9036a4 11073 else
351f65ca 11074 return format;
3e73aa7c 11075 }
e57f8c65
TG		 11076#endif
11077#if defined (OBJ_MACH_O)
11078 case bfd_target_mach_o_flavour:
d382c579
TG		 11079 if (flag_code == CODE_64BIT)
11080 {
11081 use_rela_relocations = 1;
11082 object_64bit = 1;
11083 return "mach-o-x86-64";
11084 }
11085 else
11086 return "mach-o-i386";
4c63da97 11087#endif
252b5132
RH		 11088 default:
11089 abort ();
11090 return NULL;
11091 }
11092}
11093
47926f60 11094#endif /* OBJ_MAYBE_ more than one */
252b5132 11095\f
252b5132 11096symbolS *
7016a5d5 11097md_undefined_symbol (char *name)
252b5132 11098{
18dc2407
ILT		 11099 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11100 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11101 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11102 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 11103 {
11104 if (!GOT_symbol)
11105 {
11106 if (symbol_find (name))
11107 as_bad (_("GOT already in symbol table"));
11108 GOT_symbol = symbol_new (name, undefined_section,
11109 (valueT) 0, &zero_address_frag);
11110 };
11111 return GOT_symbol;
11112 }
252b5132
RH		 11113 return 0;
11114}
11115
11116/* Round up a section size to the appropriate boundary. */
47926f60 11117
252b5132 11118valueT
7016a5d5 11119md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 11120{
4c63da97
AM		 11121#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11122 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11123 {
11124 /* For a.out, force the section size to be aligned. If we don't do
11125 this, BFD will align it for us, but it will not write out the
11126 final bytes of the section. This may be a bug in BFD, but it is
11127 easier to fix it here since that is how the other a.out targets
11128 work. */
11129 int align;
11130
11131 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 11132 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 11133 }
252b5132
RH		 11134#endif
11135
11136 return size;
11137}
11138
11139/* On the i386, PC-relative offsets are relative to the start of the
11140 next instruction. That is, the address of the offset, plus its
11141 size, since the offset is always the last part of the insn. */
11142
11143long
e3bb37b5 11144md_pcrel_from (fixS *fixP)
252b5132
RH		 11145{
11146 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11147}
11148
11149#ifndef I386COFF
11150
11151static void
e3bb37b5 11152s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 11153{
29b0f896 11154 int temp;
252b5132 11155
8a75718c
JB		 11156#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11157 if (IS_ELF)
11158 obj_elf_section_change_hook ();
11159#endif
252b5132
RH		 11160 temp = get_absolute_expression ();
11161 subseg_set (bss_section, (subsegT) temp);
11162 demand_empty_rest_of_line ();
11163}
11164
11165#endif
11166
252b5132 11167void
e3bb37b5 11168i386_validate_fix (fixS *fixp)
252b5132 11169{
02a86693 11170 if (fixp->fx_subsy)
252b5132 11171 {
02a86693 11172 if (fixp->fx_subsy == GOT_symbol)
23df1078 11173 {
02a86693
L		 11174 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11175 {
11176 if (!object_64bit)
11177 abort ();
11178#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11179 if (fixp->fx_tcbit2)
56ceb5b5
L		 11180 fixp->fx_r_type = (fixp->fx_tcbit
11181 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11182 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 11183 else
11184#endif
11185 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11186 }
d6ab8113 11187 else
02a86693
L		 11188 {
11189 if (!object_64bit)
11190 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11191 else
11192 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11193 }
11194 fixp->fx_subsy = 0;
23df1078 11195 }
252b5132 11196 }
02a86693
L		 11197#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11198 else if (!object_64bit)
11199 {
11200 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11201 && fixp->fx_tcbit2)
11202 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11203 }
11204#endif
252b5132
RH		 11205}
11206
252b5132 11207arelent *
7016a5d5 11208tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 11209{
11210 arelent *rel;
11211 bfd_reloc_code_real_type code;
11212
11213 switch (fixp->fx_r_type)
11214 {
8ce3d284 11215#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 11216 case BFD_RELOC_SIZE32:
11217 case BFD_RELOC_SIZE64:
11218 if (S_IS_DEFINED (fixp->fx_addsy)
11219 && !S_IS_EXTERNAL (fixp->fx_addsy))
11220 {
11221 /* Resolve size relocation against local symbol to size of
11222 the symbol plus addend. */
11223 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11224 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11225 && !fits_in_unsigned_long (value))
11226 as_bad_where (fixp->fx_file, fixp->fx_line,
11227 _("symbol size computation overflow"));
11228 fixp->fx_addsy = NULL;
11229 fixp->fx_subsy = NULL;
11230 md_apply_fix (fixp, (valueT *) &value, NULL);
11231 return NULL;
11232 }
8ce3d284 11233#endif
1a0670f3 11234 /* Fall through. */
8fd4256d 11235
3e73aa7c
JH		 11236 case BFD_RELOC_X86_64_PLT32:
11237 case BFD_RELOC_X86_64_GOT32:
11238 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11239 case BFD_RELOC_X86_64_GOTPCRELX:
11240 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 11241 case BFD_RELOC_386_PLT32:
11242 case BFD_RELOC_386_GOT32:
02a86693 11243 case BFD_RELOC_386_GOT32X:
252b5132
RH		 11244 case BFD_RELOC_386_GOTOFF:
11245 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 11246 case BFD_RELOC_386_TLS_GD:
11247 case BFD_RELOC_386_TLS_LDM:
11248 case BFD_RELOC_386_TLS_LDO_32:
11249 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 11250 case BFD_RELOC_386_TLS_IE:
11251 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 11252 case BFD_RELOC_386_TLS_LE_32:
11253 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 11254 case BFD_RELOC_386_TLS_GOTDESC:
11255 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 11256 case BFD_RELOC_X86_64_TLSGD:
11257 case BFD_RELOC_X86_64_TLSLD:
11258 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 11259 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 11260 case BFD_RELOC_X86_64_GOTTPOFF:
11261 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 11262 case BFD_RELOC_X86_64_TPOFF64:
11263 case BFD_RELOC_X86_64_GOTOFF64:
11264 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 11265 case BFD_RELOC_X86_64_GOT64:
11266 case BFD_RELOC_X86_64_GOTPCREL64:
11267 case BFD_RELOC_X86_64_GOTPC64:
11268 case BFD_RELOC_X86_64_GOTPLT64:
11269 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 11270 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11271 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 11272 case BFD_RELOC_RVA:
11273 case BFD_RELOC_VTABLE_ENTRY:
11274 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 11275#ifdef TE_PE
11276 case BFD_RELOC_32_SECREL:
11277#endif
252b5132
RH		 11278 code = fixp->fx_r_type;
11279 break;
dbbaec26
L		 11280 case BFD_RELOC_X86_64_32S:
11281 if (!fixp->fx_pcrel)
11282 {
11283 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11284 code = fixp->fx_r_type;
11285 break;
11286 }
1a0670f3 11287 /* Fall through. */
252b5132 11288 default:
93382f6d 11289 if (fixp->fx_pcrel)
252b5132 11290 {
93382f6d
AM		 11291 switch (fixp->fx_size)
11292 {
11293 default:
b091f402
AM		 11294 as_bad_where (fixp->fx_file, fixp->fx_line,
11295 _("can not do %d byte pc-relative relocation"),
11296 fixp->fx_size);
93382f6d
AM		 11297 code = BFD_RELOC_32_PCREL;
11298 break;
11299 case 1: code = BFD_RELOC_8_PCREL; break;
11300 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 11301 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 11302#ifdef BFD64
11303 case 8: code = BFD_RELOC_64_PCREL; break;
11304#endif
93382f6d
AM		 11305 }
11306 }
11307 else
11308 {
11309 switch (fixp->fx_size)
11310 {
11311 default:
b091f402
AM		 11312 as_bad_where (fixp->fx_file, fixp->fx_line,
11313 _("can not do %d byte relocation"),
11314 fixp->fx_size);
93382f6d
AM		 11315 code = BFD_RELOC_32;
11316 break;
11317 case 1: code = BFD_RELOC_8; break;
11318 case 2: code = BFD_RELOC_16; break;
11319 case 4: code = BFD_RELOC_32; break;
937149dd 11320#ifdef BFD64
3e73aa7c 11321 case 8: code = BFD_RELOC_64; break;
937149dd 11322#endif
93382f6d 11323 }
252b5132
RH		 11324 }
11325 break;
11326 }
252b5132 11327
d182319b
JB		 11328 if ((code == BFD_RELOC_32
11329 || code == BFD_RELOC_32_PCREL
11330 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 11331 && GOT_symbol
11332 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 11333 {
4fa24527 11334 if (!object_64bit)
d6ab8113
JB		 11335 code = BFD_RELOC_386_GOTPC;
11336 else
11337 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 11338 }
7b81dfbb
AJ		 11339 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11340 && GOT_symbol
11341 && fixp->fx_addsy == GOT_symbol)
11342 {
11343 code = BFD_RELOC_X86_64_GOTPC64;
11344 }
252b5132 11345
add39d23
TS		 11346 rel = XNEW (arelent);
11347 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 11348 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 11349
11350 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 11351
3e73aa7c
JH		 11352 if (!use_rela_relocations)
11353 {
11354 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11355 vtable entry to be used in the relocation's section offset. */
11356 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11357 rel->address = fixp->fx_offset;
fbeb56a4
DK		 11358#if defined (OBJ_COFF) && defined (TE_PE)
11359 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11360 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11361 else
11362#endif
c6682705 11363 rel->addend = 0;
3e73aa7c
JH		 11364 }
11365 /* Use the rela in 64bit mode. */
252b5132 11366 else
3e73aa7c 11367 {
862be3fb
L		 11368 if (disallow_64bit_reloc)
11369 switch (code)
11370 {
862be3fb
L		 11371 case BFD_RELOC_X86_64_DTPOFF64:
11372 case BFD_RELOC_X86_64_TPOFF64:
11373 case BFD_RELOC_64_PCREL:
11374 case BFD_RELOC_X86_64_GOTOFF64:
11375 case BFD_RELOC_X86_64_GOT64:
11376 case BFD_RELOC_X86_64_GOTPCREL64:
11377 case BFD_RELOC_X86_64_GOTPC64:
11378 case BFD_RELOC_X86_64_GOTPLT64:
11379 case BFD_RELOC_X86_64_PLTOFF64:
11380 as_bad_where (fixp->fx_file, fixp->fx_line,
11381 _("cannot represent relocation type %s in x32 mode"),
11382 bfd_get_reloc_code_name (code));
11383 break;
11384 default:
11385 break;
11386 }
11387
062cd5e7
AS		 11388 if (!fixp->fx_pcrel)
11389 rel->addend = fixp->fx_offset;
11390 else
11391 switch (code)
11392 {
11393 case BFD_RELOC_X86_64_PLT32:
11394 case BFD_RELOC_X86_64_GOT32:
11395 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11396 case BFD_RELOC_X86_64_GOTPCRELX:
11397 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 11398 case BFD_RELOC_X86_64_TLSGD:
11399 case BFD_RELOC_X86_64_TLSLD:
11400 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 11401 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11402 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 11403 rel->addend = fixp->fx_offset - fixp->fx_size;
11404 break;
11405 default:
11406 rel->addend = (section->vma
11407 - fixp->fx_size
11408 + fixp->fx_addnumber
11409 + md_pcrel_from (fixp));
11410 break;
11411 }
3e73aa7c
JH		 11412 }
11413
252b5132
RH		 11414 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11415 if (rel->howto == NULL)
11416 {
11417 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 11418 _("cannot represent relocation type %s"),
252b5132
RH		 11419 bfd_get_reloc_code_name (code));
11420 /* Set howto to a garbage value so that we can keep going. */
11421 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 11422 gas_assert (rel->howto != NULL);
252b5132
RH		 11423 }
11424
11425 return rel;
11426}
11427
ee86248c 11428#include "tc-i386-intel.c"
54cfded0 11429
a60de03c
JB		 11430void
11431tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 11432{
a60de03c
JB		 11433 int saved_naked_reg;
11434 char saved_register_dot;
54cfded0 11435
a60de03c
JB		 11436 saved_naked_reg = allow_naked_reg;
11437 allow_naked_reg = 1;
11438 saved_register_dot = register_chars['.'];
11439 register_chars['.'] = '.';
11440 allow_pseudo_reg = 1;
11441 expression_and_evaluate (exp);
11442 allow_pseudo_reg = 0;
11443 register_chars['.'] = saved_register_dot;
11444 allow_naked_reg = saved_naked_reg;
11445
e96d56a1 11446 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 11447 {
a60de03c
JB		 11448 if ((addressT) exp->X_add_number < i386_regtab_size)
11449 {
11450 exp->X_op = O_constant;
11451 exp->X_add_number = i386_regtab[exp->X_add_number]
11452 .dw2_regnum[flag_code >> 1];
11453 }
11454 else
11455 exp->X_op = O_illegal;
54cfded0 11456 }
54cfded0
AM		 11457}
11458
11459void
11460tc_x86_frame_initial_instructions (void)
11461{
a60de03c
JB		 11462 static unsigned int sp_regno[2];
11463
11464 if (!sp_regno[flag_code >> 1])
11465 {
11466 char *saved_input = input_line_pointer;
11467 char sp[][4] = {"esp", "rsp"};
11468 expressionS exp;
a4447b93 11469
a60de03c
JB		 11470 input_line_pointer = sp[flag_code >> 1];
11471 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 11472 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 11473 sp_regno[flag_code >> 1] = exp.X_add_number;
11474 input_line_pointer = saved_input;
11475 }
a4447b93 11476
61ff971f
L		 11477 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11478 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 11479}
d2b2c203 11480
d7921315
L		 11481int
11482x86_dwarf2_addr_size (void)
11483{
11484#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11485 if (x86_elf_abi == X86_64_X32_ABI)
11486 return 4;
11487#endif
11488 return bfd_arch_bits_per_address (stdoutput) / 8;
11489}
11490
d2b2c203
DJ		 11491int
11492i386_elf_section_type (const char *str, size_t len)
11493{
11494 if (flag_code == CODE_64BIT
11495 && len == sizeof ("unwind") - 1
11496 && strncmp (str, "unwind", 6) == 0)
11497 return SHT_X86_64_UNWIND;
11498
11499 return -1;
11500}
bb41ade5 11501
ad5fec3b
EB		 11502#ifdef TE_SOLARIS
11503void
11504i386_solaris_fix_up_eh_frame (segT sec)
11505{
11506 if (flag_code == CODE_64BIT)
11507 elf_section_type (sec) = SHT_X86_64_UNWIND;
11508}
11509#endif
11510
bb41ade5
AM		 11511#ifdef TE_PE
11512void
11513tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11514{
91d6fa6a 11515 expressionS exp;
bb41ade5 11516
91d6fa6a
NC		 11517 exp.X_op = O_secrel;
11518 exp.X_add_symbol = symbol;
11519 exp.X_add_number = 0;
11520 emit_expr (&exp, size);
bb41ade5
AM		 11521}
11522#endif
3b22753a
L		 11523
11524#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11525/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11526
01e1a5bc 11527bfd_vma
6d4af3c2 11528x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11529{
11530 if (flag_code == CODE_64BIT)
11531 {
11532 if (letter == 'l')
11533 return SHF_X86_64_LARGE;
11534
8f3bae45 11535 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11536 }
3b22753a 11537 else
8f3bae45 11538 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11539 return -1;
11540}
11541
01e1a5bc 11542bfd_vma
3b22753a
L		 11543x86_64_section_word (char *str, size_t len)
11544{
8620418b 11545 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11546 return SHF_X86_64_LARGE;
11547
11548 return -1;
11549}
11550
11551static void
11552handle_large_common (int small ATTRIBUTE_UNUSED)
11553{
11554 if (flag_code != CODE_64BIT)
11555 {
11556 s_comm_internal (0, elf_common_parse);
11557 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11558 }
11559 else
11560 {
11561 static segT lbss_section;
11562 asection *saved_com_section_ptr = elf_com_section_ptr;
11563 asection *saved_bss_section = bss_section;
11564
11565 if (lbss_section == NULL)
11566 {
11567 flagword applicable;
11568 segT seg = now_seg;
11569 subsegT subseg = now_subseg;
11570
11571 /* The .lbss section is for local .largecomm symbols. */
11572 lbss_section = subseg_new (".lbss", 0);
11573 applicable = bfd_applicable_section_flags (stdoutput);
11574 bfd_set_section_flags (stdoutput, lbss_section,
11575 applicable & SEC_ALLOC);
11576 seg_info (lbss_section)->bss = 1;
11577
11578 subseg_set (seg, subseg);
11579 }
11580
11581 elf_com_section_ptr = &_bfd_elf_large_com_section;
11582 bss_section = lbss_section;
11583
11584 s_comm_internal (0, elf_common_parse);
11585
11586 elf_com_section_ptr = saved_com_section_ptr;
11587 bss_section = saved_bss_section;
11588 }
11589}
11590#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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