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* elf-bfd.h (struct bfd_elf_section_data): Clarify sec_group
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
67a4f2b7 3 2000, 2001, 2002, 2003, 2004, 2005, 2006
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
d182319b 83static void signed_cons PARAMS ((int));
29b0f896
AM		 84static char *output_invalid PARAMS ((int c));
85static int i386_operand PARAMS ((char *operand_string));
86static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
87static const reg_entry *parse_register PARAMS ((char *reg_string,
88 char **end_op));
89static char *parse_insn PARAMS ((char *, char *));
90static char *parse_operands PARAMS ((char *, const char *));
91static void swap_operands PARAMS ((void));
050dfa73 92static void swap_imm_operands PARAMS ((void));
29b0f896
AM		 93static void optimize_imm PARAMS ((void));
94static void optimize_disp PARAMS ((void));
95static int match_template PARAMS ((void));
96static int check_string PARAMS ((void));
97static int process_suffix PARAMS ((void));
98static int check_byte_reg PARAMS ((void));
99static int check_long_reg PARAMS ((void));
100static int check_qword_reg PARAMS ((void));
101static int check_word_reg PARAMS ((void));
102static int finalize_imm PARAMS ((void));
103static int process_operands PARAMS ((void));
104static const seg_entry *build_modrm_byte PARAMS ((void));
105static void output_insn PARAMS ((void));
106static void output_branch PARAMS ((void));
107static void output_jump PARAMS ((void));
108static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 109static void output_imm PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
111static void output_disp PARAMS ((fragS *insn_start_frag,
112 offsetT insn_start_off));
29b0f896
AM		 113#ifndef I386COFF
114static void s_bss PARAMS ((int));
252b5132 115#endif
17d4e2a2
L		 116#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
117static void handle_large_common (int small ATTRIBUTE_UNUSED);
118#endif
252b5132 119
a847613f 120static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 121
252b5132 122/* 'md_assemble ()' gathers together information and puts it into a
47926f60 123 i386_insn. */
252b5132 124
520dc8e8
AM		 125union i386_op
126 {
127 expressionS *disps;
128 expressionS *imms;
129 const reg_entry *regs;
130 };
131
252b5132
RH		 132struct _i386_insn
133 {
47926f60 134 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 135 template tm;
136
137 /* SUFFIX holds the instruction mnemonic suffix if given.
138 (e.g. 'l' for 'movl') */
139 char suffix;
140
47926f60 141 /* OPERANDS gives the number of given operands. */
252b5132
RH		 142 unsigned int operands;
143
144 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
145 of given register, displacement, memory operands and immediate
47926f60 146 operands. */
252b5132
RH		 147 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
148
149 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 150 use OP[i] for the corresponding operand. */
252b5132
RH		 151 unsigned int types[MAX_OPERANDS];
152
520dc8e8
AM		 153 /* Displacement expression, immediate expression, or register for each
154 operand. */
155 union i386_op op[MAX_OPERANDS];
252b5132 156
3e73aa7c
JH		 157 /* Flags for operands. */
158 unsigned int flags[MAX_OPERANDS];
159#define Operand_PCrel 1
160
252b5132 161 /* Relocation type for operand */
f86103b7 162 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 163
252b5132
RH		 164 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
165 the base index byte below. */
166 const reg_entry *base_reg;
167 const reg_entry *index_reg;
168 unsigned int log2_scale_factor;
169
170 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 171 explicit segment overrides are given. */
ce8a8b2f 172 const seg_entry *seg[2];
252b5132
RH		 173
174 /* PREFIX holds all the given prefix opcodes (usually null).
175 PREFIXES is the number of prefix opcodes. */
176 unsigned int prefixes;
177 unsigned char prefix[MAX_PREFIXES];
178
179 /* RM and SIB are the modrm byte and the sib byte where the
180 addressing modes of this insn are encoded. */
181
182 modrm_byte rm;
3e73aa7c 183 rex_byte rex;
252b5132
RH		 184 sib_byte sib;
185 };
186
187typedef struct _i386_insn i386_insn;
188
189/* List of chars besides those in app.c:symbol_chars that can start an
190 operand. Used to prevent the scrubber eating vital white-space. */
32137342 191const char extra_symbol_chars[] = "*%-(["
252b5132 192#ifdef LEX_AT
32137342
NC		 193 "@"
194#endif
195#ifdef LEX_QM
196 "?"
252b5132 197#endif
32137342 198 ;
252b5132 199
29b0f896
AM		 200#if (defined (TE_I386AIX) \
201 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 202 && !defined (TE_GNU) \
29b0f896 203 && !defined (TE_LINUX) \
32137342 204 && !defined (TE_NETWARE) \
29b0f896
AM		 205 && !defined (TE_FreeBSD) \
206 && !defined (TE_NetBSD)))
252b5132 207/* This array holds the chars that always start a comment. If the
b3b91714
AM		 208 pre-processor is disabled, these aren't very useful. The option
209 --divide will remove '/' from this list. */
210const char *i386_comment_chars = "#/";
211#define SVR4_COMMENT_CHARS 1
252b5132 212#define PREFIX_SEPARATOR '\\'
252b5132 213
b3b91714
AM		 214#else
215const char *i386_comment_chars = "#";
216#define PREFIX_SEPARATOR '/'
217#endif
218
252b5132
RH		 219/* This array holds the chars that only start a comment at the beginning of
220 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 221 .line and .file directives will appear in the pre-processed output.
222 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 223 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 224 #NO_APP at the beginning of its output.
225 Also note that comments started like this one will always work if
252b5132 226 '/' isn't otherwise defined. */
b3b91714 227const char line_comment_chars[] = "#/";
252b5132 228
63a0b638 229const char line_separator_chars[] = ";";
252b5132 230
ce8a8b2f
AM		 231/* Chars that can be used to separate mant from exp in floating point
232 nums. */
252b5132
RH		 233const char EXP_CHARS[] = "eE";
234
ce8a8b2f
AM		 235/* Chars that mean this number is a floating point constant
236 As in 0f12.456
237 or 0d1.2345e12. */
252b5132
RH		 238const char FLT_CHARS[] = "fFdDxX";
239
ce8a8b2f 240/* Tables for lexical analysis. */
252b5132
RH		 241static char mnemonic_chars[256];
242static char register_chars[256];
243static char operand_chars[256];
244static char identifier_chars[256];
245static char digit_chars[256];
246
ce8a8b2f 247/* Lexical macros. */
252b5132
RH		 248#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
249#define is_operand_char(x) (operand_chars[(unsigned char) x])
250#define is_register_char(x) (register_chars[(unsigned char) x])
251#define is_space_char(x) ((x) == ' ')
252#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
253#define is_digit_char(x) (digit_chars[(unsigned char) x])
254
0234cb7c 255/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 256static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
257
258/* md_assemble() always leaves the strings it's passed unaltered. To
259 effect this we maintain a stack of saved characters that we've smashed
260 with '\0's (indicating end of strings for various sub-fields of the
47926f60 261 assembler instruction). */
252b5132 262static char save_stack[32];
ce8a8b2f 263static char *save_stack_p;
252b5132
RH		 264#define END_STRING_AND_SAVE(s) \
265 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
266#define RESTORE_END_STRING(s) \
267 do { *(s) = *--save_stack_p; } while (0)
268
47926f60 269/* The instruction we're assembling. */
252b5132
RH		 270static i386_insn i;
271
272/* Possible templates for current insn. */
273static const templates *current_templates;
274
47926f60 275/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 276static expressionS disp_expressions[2], im_expressions[2];
277
47926f60
KH		 278/* Current operand we are working on. */
279static int this_operand;
252b5132 280
3e73aa7c
JH		 281/* We support four different modes. FLAG_CODE variable is used to distinguish
282 these. */
283
284enum flag_code {
285 CODE_32BIT,
286 CODE_16BIT,
287 CODE_64BIT };
f3c180ae 288#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 289
290static enum flag_code flag_code;
4fa24527 291static unsigned int object_64bit;
3e73aa7c
JH		 292static int use_rela_relocations = 0;
293
294/* The names used to print error messages. */
b77a7acd 295static const char *flag_code_names[] =
3e73aa7c
JH		 296 {
297 "32",
298 "16",
299 "64"
300 };
252b5132 301
47926f60
KH		 302/* 1 for intel syntax,
303 0 if att syntax. */
304static int intel_syntax = 0;
252b5132 305
47926f60
KH		 306/* 1 if register prefix % not required. */
307static int allow_naked_reg = 0;
252b5132 308
47926f60
KH		 309/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
310 leave, push, and pop instructions so that gcc has the same stack
311 frame as in 32 bit mode. */
312static char stackop_size = '\0';
eecb386c 313
12b55ccc
L		 314/* Non-zero to optimize code alignment. */
315int optimize_align_code = 1;
316
47926f60
KH		 317/* Non-zero to quieten some warnings. */
318static int quiet_warnings = 0;
a38cf1db 319
47926f60
KH		 320/* CPU name. */
321static const char *cpu_arch_name = NULL;
5c6af06e 322static const char *cpu_sub_arch_name = NULL;
a38cf1db 323
47926f60 324/* CPU feature flags. */
29b0f896 325static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 326
ccc9c027
L		 327/* If we have selected a cpu we are generating instructions for. */
328static int cpu_arch_tune_set = 0;
329
9103f4f4
L		 330/* Cpu we are generating instructions for. */
331static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
332
333/* CPU feature flags of cpu we are generating instructions for. */
334static unsigned int cpu_arch_tune_flags = 0;
335
ccc9c027
L		 336/* CPU instruction set architecture used. */
337static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
338
9103f4f4
L		 339/* CPU feature flags of instruction set architecture used. */
340static unsigned int cpu_arch_isa_flags = 0;
341
fddf5b5b
AM		 342/* If set, conditional jumps are not automatically promoted to handle
343 larger than a byte offset. */
344static unsigned int no_cond_jump_promotion = 0;
345
29b0f896 346/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 347static symbolS *GOT_symbol;
29b0f896 348
a4447b93
RH		 349/* The dwarf2 return column, adjusted for 32 or 64 bit. */
350unsigned int x86_dwarf2_return_column;
351
352/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
353int x86_cie_data_alignment;
354
252b5132 355/* Interface to relax_segment.
fddf5b5b
AM		 356 There are 3 major relax states for 386 jump insns because the
357 different types of jumps add different sizes to frags when we're
358 figuring out what sort of jump to choose to reach a given label. */
252b5132 359
47926f60 360/* Types. */
93c2a809
AM		 361#define UNCOND_JUMP 0
362#define COND_JUMP 1
363#define COND_JUMP86 2
fddf5b5b 364
47926f60 365/* Sizes. */
252b5132
RH		 366#define CODE16 1
367#define SMALL 0
29b0f896 368#define SMALL16 (SMALL | CODE16)
252b5132 369#define BIG 2
29b0f896 370#define BIG16 (BIG | CODE16)
252b5132
RH		 371
372#ifndef INLINE
373#ifdef __GNUC__
374#define INLINE __inline__
375#else
376#define INLINE
377#endif
378#endif
379
fddf5b5b
AM		 380#define ENCODE_RELAX_STATE(type, size) \
381 ((relax_substateT) (((type) << 2) | (size)))
382#define TYPE_FROM_RELAX_STATE(s) \
383 ((s) >> 2)
384#define DISP_SIZE_FROM_RELAX_STATE(s) \
385 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 386
387/* This table is used by relax_frag to promote short jumps to long
388 ones where necessary. SMALL (short) jumps may be promoted to BIG
389 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
390 don't allow a short jump in a 32 bit code segment to be promoted to
391 a 16 bit offset jump because it's slower (requires data size
392 prefix), and doesn't work, unless the destination is in the bottom
393 64k of the code segment (The top 16 bits of eip are zeroed). */
394
395const relax_typeS md_relax_table[] =
396{
24eab124
AM		 397 /* The fields are:
398 1) most positive reach of this state,
399 2) most negative reach of this state,
93c2a809 400 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 401 4) which index into the table to try if we can't fit into this one. */
252b5132 402
fddf5b5b 403 /* UNCOND_JUMP states. */
93c2a809
AM		 404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
406 /* dword jmp adds 4 bytes to frag:
407 0 extra opcode bytes, 4 displacement bytes. */
252b5132 408 {0, 0, 4, 0},
93c2a809
AM		 409 /* word jmp adds 2 byte2 to frag:
410 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 411 {0, 0, 2, 0},
412
93c2a809
AM		 413 /* COND_JUMP states. */
414 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
415 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
416 /* dword conditionals adds 5 bytes to frag:
417 1 extra opcode byte, 4 displacement bytes. */
418 {0, 0, 5, 0},
fddf5b5b 419 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 420 1 extra opcode byte, 2 displacement bytes. */
421 {0, 0, 3, 0},
422
423 /* COND_JUMP86 states. */
424 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
425 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
426 /* dword conditionals adds 5 bytes to frag:
427 1 extra opcode byte, 4 displacement bytes. */
428 {0, 0, 5, 0},
429 /* word conditionals add 4 bytes to frag:
430 1 displacement byte and a 3 byte long branch insn. */
431 {0, 0, 4, 0}
252b5132
RH		 432};
433
9103f4f4
L		 434static const arch_entry cpu_arch[] =
435{
436 {"generic32", PROCESSOR_GENERIC32,
d32cad65 437 Cpu186|Cpu286|Cpu386},
9103f4f4 438 {"generic64", PROCESSOR_GENERIC64,
d32cad65 439 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 440 |CpuMMX2|CpuSSE|CpuSSE2},
441 {"i8086", PROCESSOR_UNKNOWN,
d32cad65 442 0},
9103f4f4 443 {"i186", PROCESSOR_UNKNOWN,
d32cad65 444 Cpu186},
9103f4f4 445 {"i286", PROCESSOR_UNKNOWN,
d32cad65 446 Cpu186|Cpu286},
9103f4f4 447 {"i386", PROCESSOR_GENERIC32,
d32cad65 448 Cpu186|Cpu286|Cpu386},
9103f4f4 449 {"i486", PROCESSOR_I486,
d32cad65 450 Cpu186|Cpu286|Cpu386|Cpu486},
9103f4f4 451 {"i586", PROCESSOR_PENTIUM,
d32cad65 452 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 453 {"i686", PROCESSOR_PENTIUMPRO,
d32cad65 454 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 455 {"pentium", PROCESSOR_PENTIUM,
d32cad65 456 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 457 {"pentiumpro",PROCESSOR_PENTIUMPRO,
d32cad65 458 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 459 {"pentiumii", PROCESSOR_PENTIUMPRO,
d32cad65 460 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
9103f4f4 461 {"pentiumiii",PROCESSOR_PENTIUMPRO,
d32cad65 462 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
9103f4f4 463 {"pentium4", PROCESSOR_PENTIUM4,
d32cad65 464 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 465 |CpuMMX2|CpuSSE|CpuSSE2},
466 {"prescott", PROCESSOR_NOCONA,
d32cad65 467 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 468 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
469 {"nocona", PROCESSOR_NOCONA,
d32cad65 470 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 471 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 472 {"yonah", PROCESSOR_CORE,
d32cad65 473 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 474 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 475 {"core", PROCESSOR_CORE,
d32cad65 476 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
ef05d495
L		 477 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
478 {"merom", PROCESSOR_CORE2,
479 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
480 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
481 {"core2", PROCESSOR_CORE2,
482 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
483 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4 484 {"k6", PROCESSOR_K6,
d32cad65 485 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
9103f4f4 486 {"k6_2", PROCESSOR_K6,
d32cad65 487 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
9103f4f4 488 {"athlon", PROCESSOR_ATHLON,
d32cad65 489 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 490 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
491 {"sledgehammer", PROCESSOR_K8,
d32cad65 492 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 493 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
494 {"opteron", PROCESSOR_K8,
d32cad65 495 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 496 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
497 {"k8", PROCESSOR_K8,
d32cad65 498 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4 499 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
050dfa73 500 {"amdfam10", PROCESSOR_AMDFAM10,
d32cad65
L		 501 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
502 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
503 |CpuABM},
9103f4f4
L		 504 {".mmx", PROCESSOR_UNKNOWN,
505 CpuMMX},
506 {".sse", PROCESSOR_UNKNOWN,
507 CpuMMX|CpuMMX2|CpuSSE},
508 {".sse2", PROCESSOR_UNKNOWN,
509 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
510 {".sse3", PROCESSOR_UNKNOWN,
511 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495
L		 512 {".ssse3", PROCESSOR_UNKNOWN,
513 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4
L		 514 {".3dnow", PROCESSOR_UNKNOWN,
515 CpuMMX|Cpu3dnow},
516 {".3dnowa", PROCESSOR_UNKNOWN,
517 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
518 {".padlock", PROCESSOR_UNKNOWN,
519 CpuPadLock},
520 {".pacifica", PROCESSOR_UNKNOWN,
521 CpuSVME},
522 {".svme", PROCESSOR_UNKNOWN,
050dfa73
MM		 523 CpuSVME},
524 {".sse4a", PROCESSOR_UNKNOWN,
525 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
526 {".abm", PROCESSOR_UNKNOWN,
527 CpuABM}
e413e4e9
AM		 528};
529
29b0f896
AM		 530const pseudo_typeS md_pseudo_table[] =
531{
532#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
533 {"align", s_align_bytes, 0},
534#else
535 {"align", s_align_ptwo, 0},
536#endif
537 {"arch", set_cpu_arch, 0},
538#ifndef I386COFF
539 {"bss", s_bss, 0},
540#endif
541 {"ffloat", float_cons, 'f'},
542 {"dfloat", float_cons, 'd'},
543 {"tfloat", float_cons, 'x'},
544 {"value", cons, 2},
d182319b 545 {"slong", signed_cons, 4},
29b0f896
AM		 546 {"noopt", s_ignore, 0},
547 {"optim", s_ignore, 0},
548 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
549 {"code16", set_code_flag, CODE_16BIT},
550 {"code32", set_code_flag, CODE_32BIT},
551 {"code64", set_code_flag, CODE_64BIT},
552 {"intel_syntax", set_intel_syntax, 1},
553 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 554#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
555 {"largecomm", handle_large_common, 0},
07a53e5c
RH		 556#else
557 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
558 {"loc", dwarf2_directive_loc, 0},
559 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 560#endif
6482c264
NC		 561#ifdef TE_PE
562 {"secrel32", pe_directive_secrel, 0},
563#endif
29b0f896
AM		 564 {0, 0, 0}
565};
566
567/* For interface with expression (). */
568extern char *input_line_pointer;
569
570/* Hash table for instruction mnemonic lookup. */
571static struct hash_control *op_hash;
572
573/* Hash table for register lookup. */
574static struct hash_control *reg_hash;
575\f
252b5132
RH		 576void
577i386_align_code (fragP, count)
578 fragS *fragP;
579 int count;
580{
ce8a8b2f
AM		 581 /* Various efficient no-op patterns for aligning code labels.
582 Note: Don't try to assemble the instructions in the comments.
583 0L and 0w are not legal. */
252b5132
RH		 584 static const char f32_1[] =
585 {0x90}; /* nop */
586 static const char f32_2[] =
ccc9c027 587 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 588 static const char f32_3[] =
589 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
590 static const char f32_4[] =
591 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
592 static const char f32_5[] =
593 {0x90, /* nop */
594 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
595 static const char f32_6[] =
596 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
597 static const char f32_7[] =
598 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
599 static const char f32_8[] =
600 {0x90, /* nop */
601 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
602 static const char f32_9[] =
603 {0x89,0xf6, /* movl %esi,%esi */
604 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
605 static const char f32_10[] =
606 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
607 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
608 static const char f32_11[] =
609 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
610 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
611 static const char f32_12[] =
612 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
613 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
614 static const char f32_13[] =
615 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
616 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
617 static const char f32_14[] =
618 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
619 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
620 static const char f32_15[] =
621 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
622 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 623 static const char f16_3[] =
624 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 625 static const char f16_4[] =
626 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
627 static const char f16_5[] =
628 {0x90, /* nop */
629 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
630 static const char f16_6[] =
631 {0x89,0xf6, /* mov %si,%si */
632 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
633 static const char f16_7[] =
634 {0x8d,0x74,0x00, /* lea 0(%si),%si */
635 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
636 static const char f16_8[] =
637 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
638 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
639 static const char *const f32_patt[] = {
640 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
641 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
642 };
643 static const char *const f16_patt[] = {
c3332e24 644 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 645 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
646 };
ccc9c027
L		 647 /* nopl (%[re]ax) */
648 static const char alt_3[] =
649 {0x0f,0x1f,0x00};
650 /* nopl 0(%[re]ax) */
651 static const char alt_4[] =
652 {0x0f,0x1f,0x40,0x00};
653 /* nopl 0(%[re]ax,%[re]ax,1) */
654 static const char alt_5[] =
655 {0x0f,0x1f,0x44,0x00,0x00};
656 /* nopw 0(%[re]ax,%[re]ax,1) */
657 static const char alt_6[] =
658 {0x66,0x0f,0x1f,0x44,0x00,0x00};
659 /* nopl 0L(%[re]ax) */
660 static const char alt_7[] =
661 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
662 /* nopl 0L(%[re]ax,%[re]ax,1) */
663 static const char alt_8[] =
664 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
665 /* nopw 0L(%[re]ax,%[re]ax,1) */
666 static const char alt_9[] =
667 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
668 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
669 static const char alt_10[] =
670 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
671 /* data16
672 nopw %cs:0L(%[re]ax,%[re]ax,1) */
673 static const char alt_long_11[] =
674 {0x66,
675 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
676 /* data16
677 data16
678 nopw %cs:0L(%[re]ax,%[re]ax,1) */
679 static const char alt_long_12[] =
680 {0x66,
681 0x66,
682 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
683 /* data16
684 data16
685 data16
686 nopw %cs:0L(%[re]ax,%[re]ax,1) */
687 static const char alt_long_13[] =
688 {0x66,
689 0x66,
690 0x66,
691 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
692 /* data16
693 data16
694 data16
695 data16
696 nopw %cs:0L(%[re]ax,%[re]ax,1) */
697 static const char alt_long_14[] =
698 {0x66,
699 0x66,
700 0x66,
701 0x66,
702 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
703 /* data16
704 data16
705 data16
706 data16
707 data16
708 nopw %cs:0L(%[re]ax,%[re]ax,1) */
709 static const char alt_long_15[] =
710 {0x66,
711 0x66,
712 0x66,
713 0x66,
714 0x66,
715 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
716 /* nopl 0(%[re]ax,%[re]ax,1)
717 nopw 0(%[re]ax,%[re]ax,1) */
718 static const char alt_short_11[] =
719 {0x0f,0x1f,0x44,0x00,0x00,
720 0x66,0x0f,0x1f,0x44,0x00,0x00};
721 /* nopw 0(%[re]ax,%[re]ax,1)
722 nopw 0(%[re]ax,%[re]ax,1) */
723 static const char alt_short_12[] =
724 {0x66,0x0f,0x1f,0x44,0x00,0x00,
725 0x66,0x0f,0x1f,0x44,0x00,0x00};
726 /* nopw 0(%[re]ax,%[re]ax,1)
727 nopl 0L(%[re]ax) */
728 static const char alt_short_13[] =
729 {0x66,0x0f,0x1f,0x44,0x00,0x00,
730 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
731 /* nopl 0L(%[re]ax)
732 nopl 0L(%[re]ax) */
733 static const char alt_short_14[] =
734 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
735 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
736 /* nopl 0L(%[re]ax)
737 nopl 0L(%[re]ax,%[re]ax,1) */
738 static const char alt_short_15[] =
739 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
740 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
741 static const char *const alt_short_patt[] = {
742 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
743 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
744 alt_short_14, alt_short_15
745 };
746 static const char *const alt_long_patt[] = {
747 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
748 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
749 alt_long_14, alt_long_15
750 };
252b5132 751
33fef721
JH		 752 if (count <= 0 || count > 15)
753 return;
3e73aa7c 754
ccc9c027
L		 755 /* We need to decide which NOP sequence to use for 32bit and
756 64bit. When -mtune= is used:
757
758 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
759 f32_patt will be used.
050dfa73 760 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with 0x66 prefix will be used.
ef05d495 761 3. For PROCESSOR_CORE2, alt_long_patt will be used.
ccc9c027 762 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
ef05d495 763 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
ccc9c027
L		 764 and PROCESSOR_GENERIC64, alt_short_patt will be used.
765
766 When -mtune= isn't used, alt_short_patt will be used if
767 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
768
769 When -march= or .arch is used, we can't use anything beyond
770 cpu_arch_isa_flags. */
771
772 if (flag_code == CODE_16BIT)
773 {
774 memcpy (fragP->fr_literal + fragP->fr_fix,
775 f16_patt[count - 1], count);
776 if (count > 8)
777 /* Adjust jump offset. */
778 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
779 }
780 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
252b5132 781 {
33fef721
JH		 782 int i;
783 int nnops = (count + 3) / 4;
784 int len = count / nnops;
785 int remains = count - nnops * len;
786 int pos = 0;
787
ccc9c027
L		 788 /* The recommended way to pad 64bit code is to use NOPs preceded
789 by maximally four 0x66 prefixes. Balance the size of nops. */
33fef721 790 for (i = 0; i < remains; i++)
252b5132 791 {
33fef721
JH		 792 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
793 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
794 pos += len + 1;
795 }
796 for (; i < nnops; i++)
797 {
798 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
799 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
800 pos += len;
252b5132 801 }
252b5132 802 }
33fef721 803 else
ccc9c027
L		 804 {
805 const char *const *patt = NULL;
806
807 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
808 {
809 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
810 switch (cpu_arch_tune)
811 {
812 case PROCESSOR_UNKNOWN:
813 /* We use cpu_arch_isa_flags to check if we SHOULD
814 optimize for Cpu686. */
815 if ((cpu_arch_isa_flags & Cpu686) != 0)
816 patt = alt_short_patt;
817 else
818 patt = f32_patt;
819 break;
ef05d495 820 case PROCESSOR_CORE2:
ccc9c027
L		 821 patt = alt_long_patt;
822 break;
823 case PROCESSOR_PENTIUMPRO:
824 case PROCESSOR_PENTIUM4:
825 case PROCESSOR_NOCONA:
ef05d495 826 case PROCESSOR_CORE:
ccc9c027
L		 827 case PROCESSOR_K6:
828 case PROCESSOR_ATHLON:
829 case PROCESSOR_K8:
830 case PROCESSOR_GENERIC64:
050dfa73 831 case PROCESSOR_AMDFAM10:
ccc9c027
L		 832 patt = alt_short_patt;
833 break;
834 case PROCESSOR_I486:
835 case PROCESSOR_PENTIUM:
836 case PROCESSOR_GENERIC32:
837 patt = f32_patt;
838 break;
839 }
840 }
841 else
842 {
843 switch (cpu_arch_tune)
844 {
845 case PROCESSOR_UNKNOWN:
846 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
847 PROCESSOR_UNKNOWN. */
848 abort ();
849 break;
850
851 case PROCESSOR_I486:
852 case PROCESSOR_PENTIUM:
853 case PROCESSOR_PENTIUMPRO:
854 case PROCESSOR_PENTIUM4:
855 case PROCESSOR_NOCONA:
ef05d495 856 case PROCESSOR_CORE:
ccc9c027
L		 857 case PROCESSOR_K6:
858 case PROCESSOR_ATHLON:
859 case PROCESSOR_K8:
050dfa73 860 case PROCESSOR_AMDFAM10:
ccc9c027
L		 861 case PROCESSOR_GENERIC32:
862 /* We use cpu_arch_isa_flags to check if we CAN optimize
863 for Cpu686. */
864 if ((cpu_arch_isa_flags & Cpu686) != 0)
865 patt = alt_short_patt;
866 else
867 patt = f32_patt;
868 break;
ef05d495 869 case PROCESSOR_CORE2:
ccc9c027
L		 870 if ((cpu_arch_isa_flags & Cpu686) != 0)
871 patt = alt_long_patt;
872 else
873 patt = f32_patt;
874 break;
875 case PROCESSOR_GENERIC64:
876 patt = alt_short_patt;
877 break;
878 }
879 }
880
33fef721 881 memcpy (fragP->fr_literal + fragP->fr_fix,
ccc9c027
L		 882 patt[count - 1], count);
883 }
33fef721 884 fragP->fr_var = count;
252b5132
RH		 885}
886
252b5132
RH		 887static INLINE unsigned int
888mode_from_disp_size (t)
889 unsigned int t;
890{
3e73aa7c 891 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 892}
893
894static INLINE int
895fits_in_signed_byte (num)
847f7ad4 896 offsetT num;
252b5132
RH		 897{
898 return (num >= -128) && (num <= 127);
47926f60 899}
252b5132
RH		 900
901static INLINE int
902fits_in_unsigned_byte (num)
847f7ad4 903 offsetT num;
252b5132
RH		 904{
905 return (num & 0xff) == num;
47926f60 906}
252b5132
RH		 907
908static INLINE int
909fits_in_unsigned_word (num)
847f7ad4 910 offsetT num;
252b5132
RH		 911{
912 return (num & 0xffff) == num;
47926f60 913}
252b5132
RH		 914
915static INLINE int
916fits_in_signed_word (num)
847f7ad4 917 offsetT num;
252b5132
RH		 918{
919 return (-32768 <= num) && (num <= 32767);
47926f60 920}
3e73aa7c
JH		 921static INLINE int
922fits_in_signed_long (num)
923 offsetT num ATTRIBUTE_UNUSED;
924{
925#ifndef BFD64
926 return 1;
927#else
928 return (!(((offsetT) -1 << 31) & num)
929 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
930#endif
931} /* fits_in_signed_long() */
932static INLINE int
933fits_in_unsigned_long (num)
934 offsetT num ATTRIBUTE_UNUSED;
935{
936#ifndef BFD64
937 return 1;
938#else
939 return (num & (((offsetT) 2 << 31) - 1)) == num;
940#endif
941} /* fits_in_unsigned_long() */
252b5132
RH		 942
943static int
944smallest_imm_type (num)
847f7ad4 945 offsetT num;
252b5132 946{
d32cad65 947 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 948 {
949 /* This code is disabled on the 486 because all the Imm1 forms
950 in the opcode table are slower on the i486. They're the
951 versions with the implicitly specified single-position
952 displacement, which has another syntax if you really want to
953 use that form. */
954 if (num == 1)
3e73aa7c 955 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 956 }
252b5132 957 return (fits_in_signed_byte (num)
3e73aa7c 958 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 959 : fits_in_unsigned_byte (num)
3e73aa7c 960 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 961 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 962 ? (Imm16 | Imm32 | Imm32S | Imm64)
963 : fits_in_signed_long (num)
964 ? (Imm32 | Imm32S | Imm64)
965 : fits_in_unsigned_long (num)
966 ? (Imm32 | Imm64)
967 : Imm64);
47926f60 968}
252b5132 969
847f7ad4
AM		 970static offsetT
971offset_in_range (val, size)
972 offsetT val;
973 int size;
974{
508866be 975 addressT mask;
ba2adb93 976
847f7ad4
AM		 977 switch (size)
978 {
508866be
L		 979 case 1: mask = ((addressT) 1 << 8) - 1; break;
980 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 981 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 982#ifdef BFD64
983 case 8: mask = ((addressT) 2 << 63) - 1; break;
984#endif
47926f60 985 default: abort ();
847f7ad4
AM		 986 }
987
ba2adb93 988 /* If BFD64, sign extend val. */
3e73aa7c
JH		 989 if (!use_rela_relocations)
990 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
991 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 992
47926f60 993 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 994 {
995 char buf1[40], buf2[40];
996
997 sprint_value (buf1, val);
998 sprint_value (buf2, val & mask);
999 as_warn (_("%s shortened to %s"), buf1, buf2);
1000 }
1001 return val & mask;
1002}
1003
252b5132
RH		 1004/* Returns 0 if attempting to add a prefix where one from the same
1005 class already exists, 1 if non rep/repne added, 2 if rep/repne
1006 added. */
1007static int
1008add_prefix (prefix)
1009 unsigned int prefix;
1010{
1011 int ret = 1;
b1905489 1012 unsigned int q;
252b5132 1013
29b0f896
AM		 1014 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1015 && flag_code == CODE_64BIT)
b1905489
JB		 1016 {
1017 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
1018 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
1019 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
1020 ret = 0;
1021 q = REX_PREFIX;
1022 }
3e73aa7c 1023 else
b1905489
JB		 1024 {
1025 switch (prefix)
1026 {
1027 default:
1028 abort ();
1029
1030 case CS_PREFIX_OPCODE:
1031 case DS_PREFIX_OPCODE:
1032 case ES_PREFIX_OPCODE:
1033 case FS_PREFIX_OPCODE:
1034 case GS_PREFIX_OPCODE:
1035 case SS_PREFIX_OPCODE:
1036 q = SEG_PREFIX;
1037 break;
1038
1039 case REPNE_PREFIX_OPCODE:
1040 case REPE_PREFIX_OPCODE:
1041 ret = 2;
1042 /* fall thru */
1043 case LOCK_PREFIX_OPCODE:
1044 q = LOCKREP_PREFIX;
1045 break;
1046
1047 case FWAIT_OPCODE:
1048 q = WAIT_PREFIX;
1049 break;
1050
1051 case ADDR_PREFIX_OPCODE:
1052 q = ADDR_PREFIX;
1053 break;
1054
1055 case DATA_PREFIX_OPCODE:
1056 q = DATA_PREFIX;
1057 break;
1058 }
1059 if (i.prefix[q] != 0)
1060 ret = 0;
1061 }
252b5132 1062
b1905489 1063 if (ret)
252b5132 1064 {
b1905489
JB		 1065 if (!i.prefix[q])
1066 ++i.prefixes;
1067 i.prefix[q] |= prefix;
252b5132 1068 }
b1905489
JB		 1069 else
1070 as_bad (_("same type of prefix used twice"));
252b5132 1071
252b5132
RH		 1072 return ret;
1073}
1074
1075static void
3e73aa7c 1076set_code_flag (value)
e5cb08ac 1077 int value;
eecb386c 1078{
3e73aa7c
JH		 1079 flag_code = value;
1080 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1081 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1082 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1083 {
1084 as_bad (_("64bit mode not supported on this CPU."));
1085 }
1086 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1087 {
1088 as_bad (_("32bit mode not supported on this CPU."));
1089 }
eecb386c
AM		 1090 stackop_size = '\0';
1091}
1092
1093static void
3e73aa7c
JH		 1094set_16bit_gcc_code_flag (new_code_flag)
1095 int new_code_flag;
252b5132 1096{
3e73aa7c
JH		 1097 flag_code = new_code_flag;
1098 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1099 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 1100 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1101}
1102
1103static void
1104set_intel_syntax (syntax_flag)
eecb386c 1105 int syntax_flag;
252b5132
RH		 1106{
1107 /* Find out if register prefixing is specified. */
1108 int ask_naked_reg = 0;
1109
1110 SKIP_WHITESPACE ();
29b0f896 1111 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1112 {
1113 char *string = input_line_pointer;
1114 int e = get_symbol_end ();
1115
47926f60 1116 if (strcmp (string, "prefix") == 0)
252b5132 1117 ask_naked_reg = 1;
47926f60 1118 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1119 ask_naked_reg = -1;
1120 else
d0b47220 1121 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1122 *input_line_pointer = e;
1123 }
1124 demand_empty_rest_of_line ();
c3332e24 1125
252b5132
RH		 1126 intel_syntax = syntax_flag;
1127
1128 if (ask_naked_reg == 0)
f86103b7
AM		 1129 allow_naked_reg = (intel_syntax
1130 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1131 else
1132 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 1133
1134 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1135 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 1136}
1137
e413e4e9
AM		 1138static void
1139set_cpu_arch (dummy)
47926f60 1140 int dummy ATTRIBUTE_UNUSED;
e413e4e9 1141{
47926f60 1142 SKIP_WHITESPACE ();
e413e4e9 1143
29b0f896 1144 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1145 {
1146 char *string = input_line_pointer;
1147 int e = get_symbol_end ();
9103f4f4 1148 unsigned int i;
e413e4e9 1149
9103f4f4 1150 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1151 {
1152 if (strcmp (string, cpu_arch[i].name) == 0)
1153 {
5c6af06e
JB		 1154 if (*string != '.')
1155 {
1156 cpu_arch_name = cpu_arch[i].name;
1157 cpu_sub_arch_name = NULL;
1158 cpu_arch_flags = (cpu_arch[i].flags
1159 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
ccc9c027 1160 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1161 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1162 if (!cpu_arch_tune_set)
1163 {
1164 cpu_arch_tune = cpu_arch_isa;
1165 cpu_arch_tune_flags = cpu_arch_isa_flags;
1166 }
5c6af06e
JB		 1167 break;
1168 }
1169 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1170 {
1171 cpu_sub_arch_name = cpu_arch[i].name;
1172 cpu_arch_flags |= cpu_arch[i].flags;
1173 }
1174 *input_line_pointer = e;
1175 demand_empty_rest_of_line ();
1176 return;
e413e4e9
AM		 1177 }
1178 }
9103f4f4 1179 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1180 as_bad (_("no such architecture: `%s'"), string);
1181
1182 *input_line_pointer = e;
1183 }
1184 else
1185 as_bad (_("missing cpu architecture"));
1186
fddf5b5b
AM		 1187 no_cond_jump_promotion = 0;
1188 if (*input_line_pointer == ','
29b0f896 1189 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1190 {
1191 char *string = ++input_line_pointer;
1192 int e = get_symbol_end ();
1193
1194 if (strcmp (string, "nojumps") == 0)
1195 no_cond_jump_promotion = 1;
1196 else if (strcmp (string, "jumps") == 0)
1197 ;
1198 else
1199 as_bad (_("no such architecture modifier: `%s'"), string);
1200
1201 *input_line_pointer = e;
1202 }
1203
e413e4e9
AM		 1204 demand_empty_rest_of_line ();
1205}
1206
b9d79e03
JH		 1207unsigned long
1208i386_mach ()
1209{
1210 if (!strcmp (default_arch, "x86_64"))
1211 return bfd_mach_x86_64;
1212 else if (!strcmp (default_arch, "i386"))
1213 return bfd_mach_i386_i386;
1214 else
1215 as_fatal (_("Unknown architecture"));
1216}
b9d79e03 1217\f
252b5132
RH		 1218void
1219md_begin ()
1220{
1221 const char *hash_err;
1222
47926f60 1223 /* Initialize op_hash hash table. */
252b5132
RH		 1224 op_hash = hash_new ();
1225
1226 {
29b0f896
AM		 1227 const template *optab;
1228 templates *core_optab;
252b5132 1229
47926f60
KH		 1230 /* Setup for loop. */
1231 optab = i386_optab;
252b5132
RH		 1232 core_optab = (templates *) xmalloc (sizeof (templates));
1233 core_optab->start = optab;
1234
1235 while (1)
1236 {
1237 ++optab;
1238 if (optab->name == NULL
1239 || strcmp (optab->name, (optab - 1)->name) != 0)
1240 {
1241 /* different name --> ship out current template list;
47926f60 1242 add to hash table; & begin anew. */
252b5132
RH		 1243 core_optab->end = optab;
1244 hash_err = hash_insert (op_hash,
1245 (optab - 1)->name,
1246 (PTR) core_optab);
1247 if (hash_err)
1248 {
252b5132
RH		 1249 as_fatal (_("Internal Error: Can't hash %s: %s"),
1250 (optab - 1)->name,
1251 hash_err);
1252 }
1253 if (optab->name == NULL)
1254 break;
1255 core_optab = (templates *) xmalloc (sizeof (templates));
1256 core_optab->start = optab;
1257 }
1258 }
1259 }
1260
47926f60 1261 /* Initialize reg_hash hash table. */
252b5132
RH		 1262 reg_hash = hash_new ();
1263 {
29b0f896 1264 const reg_entry *regtab;
252b5132
RH		 1265
1266 for (regtab = i386_regtab;
1267 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
1268 regtab++)
1269 {
1270 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1271 if (hash_err)
3e73aa7c
JH		 1272 as_fatal (_("Internal Error: Can't hash %s: %s"),
1273 regtab->reg_name,
1274 hash_err);
252b5132
RH		 1275 }
1276 }
1277
47926f60 1278 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1279 {
29b0f896
AM		 1280 int c;
1281 char *p;
252b5132
RH		 1282
1283 for (c = 0; c < 256; c++)
1284 {
3882b010 1285 if (ISDIGIT (c))
252b5132
RH		 1286 {
1287 digit_chars[c] = c;
1288 mnemonic_chars[c] = c;
1289 register_chars[c] = c;
1290 operand_chars[c] = c;
1291 }
3882b010 1292 else if (ISLOWER (c))
252b5132
RH		 1293 {
1294 mnemonic_chars[c] = c;
1295 register_chars[c] = c;
1296 operand_chars[c] = c;
1297 }
3882b010 1298 else if (ISUPPER (c))
252b5132 1299 {
3882b010 1300 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1301 register_chars[c] = mnemonic_chars[c];
1302 operand_chars[c] = c;
1303 }
1304
3882b010 1305 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1306 identifier_chars[c] = c;
1307 else if (c >= 128)
1308 {
1309 identifier_chars[c] = c;
1310 operand_chars[c] = c;
1311 }
1312 }
1313
1314#ifdef LEX_AT
1315 identifier_chars['@'] = '@';
32137342
NC		 1316#endif
1317#ifdef LEX_QM
1318 identifier_chars['?'] = '?';
1319 operand_chars['?'] = '?';
252b5132 1320#endif
252b5132 1321 digit_chars['-'] = '-';
791fe849 1322 mnemonic_chars['-'] = '-';
252b5132
RH		 1323 identifier_chars['_'] = '_';
1324 identifier_chars['.'] = '.';
1325
1326 for (p = operand_special_chars; *p != '\0'; p++)
1327 operand_chars[(unsigned char) *p] = *p;
1328 }
1329
1330#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1331 if (IS_ELF)
252b5132
RH		 1332 {
1333 record_alignment (text_section, 2);
1334 record_alignment (data_section, 2);
1335 record_alignment (bss_section, 2);
1336 }
1337#endif
a4447b93
RH		 1338
1339 if (flag_code == CODE_64BIT)
1340 {
1341 x86_dwarf2_return_column = 16;
1342 x86_cie_data_alignment = -8;
1343 }
1344 else
1345 {
1346 x86_dwarf2_return_column = 8;
1347 x86_cie_data_alignment = -4;
1348 }
252b5132
RH		 1349}
1350
1351void
1352i386_print_statistics (file)
1353 FILE *file;
1354{
1355 hash_print_statistics (file, "i386 opcode", op_hash);
1356 hash_print_statistics (file, "i386 register", reg_hash);
1357}
1358\f
252b5132
RH		 1359#ifdef DEBUG386
1360
ce8a8b2f 1361/* Debugging routines for md_assemble. */
252b5132
RH		 1362static void pi PARAMS ((char *, i386_insn *));
1363static void pte PARAMS ((template *));
1364static void pt PARAMS ((unsigned int));
1365static void pe PARAMS ((expressionS *));
1366static void ps PARAMS ((symbolS *));
1367
1368static void
1369pi (line, x)
1370 char *line;
1371 i386_insn *x;
1372{
09f131f2 1373 unsigned int i;
252b5132
RH		 1374
1375 fprintf (stdout, "%s: template ", line);
1376 pte (&x->tm);
09f131f2
JH		 1377 fprintf (stdout, " address: base %s index %s scale %x\n",
1378 x->base_reg ? x->base_reg->reg_name : "none",
1379 x->index_reg ? x->index_reg->reg_name : "none",
1380 x->log2_scale_factor);
1381 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1382 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1383 fprintf (stdout, " sib: base %x index %x scale %x\n",
1384 x->sib.base, x->sib.index, x->sib.scale);
1385 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1386 (x->rex & REX_MODE64) != 0,
1387 (x->rex & REX_EXTX) != 0,
1388 (x->rex & REX_EXTY) != 0,
1389 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1390 for (i = 0; i < x->operands; i++)
1391 {
1392 fprintf (stdout, " #%d: ", i + 1);
1393 pt (x->types[i]);
1394 fprintf (stdout, "\n");
1395 if (x->types[i]
3f4438ab 1396 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1397 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1398 if (x->types[i] & Imm)
520dc8e8 1399 pe (x->op[i].imms);
252b5132 1400 if (x->types[i] & Disp)
520dc8e8 1401 pe (x->op[i].disps);
252b5132
RH		 1402 }
1403}
1404
1405static void
1406pte (t)
1407 template *t;
1408{
09f131f2 1409 unsigned int i;
252b5132 1410 fprintf (stdout, " %d operands ", t->operands);
47926f60 1411 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1412 if (t->extension_opcode != None)
1413 fprintf (stdout, "ext %x ", t->extension_opcode);
1414 if (t->opcode_modifier & D)
1415 fprintf (stdout, "D");
1416 if (t->opcode_modifier & W)
1417 fprintf (stdout, "W");
1418 fprintf (stdout, "\n");
1419 for (i = 0; i < t->operands; i++)
1420 {
1421 fprintf (stdout, " #%d type ", i + 1);
1422 pt (t->operand_types[i]);
1423 fprintf (stdout, "\n");
1424 }
1425}
1426
1427static void
1428pe (e)
1429 expressionS *e;
1430{
24eab124 1431 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1432 fprintf (stdout, " add_number %ld (%lx)\n",
1433 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1434 if (e->X_add_symbol)
1435 {
1436 fprintf (stdout, " add_symbol ");
1437 ps (e->X_add_symbol);
1438 fprintf (stdout, "\n");
1439 }
1440 if (e->X_op_symbol)
1441 {
1442 fprintf (stdout, " op_symbol ");
1443 ps (e->X_op_symbol);
1444 fprintf (stdout, "\n");
1445 }
1446}
1447
1448static void
1449ps (s)
1450 symbolS *s;
1451{
1452 fprintf (stdout, "%s type %s%s",
1453 S_GET_NAME (s),
1454 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1455 segment_name (S_GET_SEGMENT (s)));
1456}
1457
7b81dfbb 1458static struct type_name
252b5132
RH		 1459 {
1460 unsigned int mask;
1461 char *tname;
1462 }
7b81dfbb 1463const type_names[] =
252b5132
RH		 1464{
1465 { Reg8, "r8" },
1466 { Reg16, "r16" },
1467 { Reg32, "r32" },
09f131f2 1468 { Reg64, "r64" },
252b5132
RH		 1469 { Imm8, "i8" },
1470 { Imm8S, "i8s" },
1471 { Imm16, "i16" },
1472 { Imm32, "i32" },
09f131f2
JH		 1473 { Imm32S, "i32s" },
1474 { Imm64, "i64" },
252b5132
RH		 1475 { Imm1, "i1" },
1476 { BaseIndex, "BaseIndex" },
1477 { Disp8, "d8" },
1478 { Disp16, "d16" },
1479 { Disp32, "d32" },
09f131f2
JH		 1480 { Disp32S, "d32s" },
1481 { Disp64, "d64" },
252b5132
RH		 1482 { InOutPortReg, "InOutPortReg" },
1483 { ShiftCount, "ShiftCount" },
1484 { Control, "control reg" },
1485 { Test, "test reg" },
1486 { Debug, "debug reg" },
1487 { FloatReg, "FReg" },
1488 { FloatAcc, "FAcc" },
1489 { SReg2, "SReg2" },
1490 { SReg3, "SReg3" },
1491 { Acc, "Acc" },
1492 { JumpAbsolute, "Jump Absolute" },
1493 { RegMMX, "rMMX" },
3f4438ab 1494 { RegXMM, "rXMM" },
252b5132
RH		 1495 { EsSeg, "es" },
1496 { 0, "" }
1497};
1498
1499static void
1500pt (t)
1501 unsigned int t;
1502{
29b0f896 1503 const struct type_name *ty;
252b5132 1504
09f131f2
JH		 1505 for (ty = type_names; ty->mask; ty++)
1506 if (t & ty->mask)
1507 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1508 fflush (stdout);
1509}
1510
1511#endif /* DEBUG386 */
1512\f
252b5132 1513static bfd_reloc_code_real_type
3956db08 1514reloc (unsigned int size,
64e74474
AM		 1515 int pcrel,
1516 int sign,
1517 bfd_reloc_code_real_type other)
252b5132 1518{
47926f60 1519 if (other != NO_RELOC)
3956db08
JB		 1520 {
1521 reloc_howto_type *reloc;
1522
1523 if (size == 8)
1524 switch (other)
1525 {
64e74474
AM		 1526 case BFD_RELOC_X86_64_GOT32:
1527 return BFD_RELOC_X86_64_GOT64;
1528 break;
1529 case BFD_RELOC_X86_64_PLTOFF64:
1530 return BFD_RELOC_X86_64_PLTOFF64;
1531 break;
1532 case BFD_RELOC_X86_64_GOTPC32:
1533 other = BFD_RELOC_X86_64_GOTPC64;
1534 break;
1535 case BFD_RELOC_X86_64_GOTPCREL:
1536 other = BFD_RELOC_X86_64_GOTPCREL64;
1537 break;
1538 case BFD_RELOC_X86_64_TPOFF32:
1539 other = BFD_RELOC_X86_64_TPOFF64;
1540 break;
1541 case BFD_RELOC_X86_64_DTPOFF32:
1542 other = BFD_RELOC_X86_64_DTPOFF64;
1543 break;
1544 default:
1545 break;
3956db08 1546 }
e05278af
JB		 1547
1548 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1549 if (size == 4 && flag_code != CODE_64BIT)
1550 sign = -1;
1551
3956db08
JB		 1552 reloc = bfd_reloc_type_lookup (stdoutput, other);
1553 if (!reloc)
1554 as_bad (_("unknown relocation (%u)"), other);
1555 else if (size != bfd_get_reloc_size (reloc))
1556 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1557 bfd_get_reloc_size (reloc),
1558 size);
1559 else if (pcrel && !reloc->pc_relative)
1560 as_bad (_("non-pc-relative relocation for pc-relative field"));
1561 else if ((reloc->complain_on_overflow == complain_overflow_signed
1562 && !sign)
1563 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1564 && sign > 0))
3956db08
JB		 1565 as_bad (_("relocated field and relocation type differ in signedness"));
1566 else
1567 return other;
1568 return NO_RELOC;
1569 }
252b5132
RH		 1570
1571 if (pcrel)
1572 {
3e73aa7c 1573 if (!sign)
3956db08 1574 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1575 switch (size)
1576 {
1577 case 1: return BFD_RELOC_8_PCREL;
1578 case 2: return BFD_RELOC_16_PCREL;
1579 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1580 case 8: return BFD_RELOC_64_PCREL;
252b5132 1581 }
3956db08 1582 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1583 }
1584 else
1585 {
3956db08 1586 if (sign > 0)
e5cb08ac 1587 switch (size)
3e73aa7c
JH		 1588 {
1589 case 4: return BFD_RELOC_X86_64_32S;
1590 }
1591 else
1592 switch (size)
1593 {
1594 case 1: return BFD_RELOC_8;
1595 case 2: return BFD_RELOC_16;
1596 case 4: return BFD_RELOC_32;
1597 case 8: return BFD_RELOC_64;
1598 }
3956db08
JB		 1599 as_bad (_("cannot do %s %u byte relocation"),
1600 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1601 }
1602
bfb32b52 1603 abort ();
252b5132
RH		 1604 return BFD_RELOC_NONE;
1605}
1606
47926f60
KH		 1607/* Here we decide which fixups can be adjusted to make them relative to
1608 the beginning of the section instead of the symbol. Basically we need
1609 to make sure that the dynamic relocations are done correctly, so in
1610 some cases we force the original symbol to be used. */
1611
252b5132 1612int
c0c949c7 1613tc_i386_fix_adjustable (fixP)
31312f95 1614 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1615{
6d249963 1616#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1617 if (!IS_ELF)
31312f95
AM		 1618 return 1;
1619
a161fe53
AM		 1620 /* Don't adjust pc-relative references to merge sections in 64-bit
1621 mode. */
1622 if (use_rela_relocations
1623 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1624 && fixP->fx_pcrel)
252b5132 1625 return 0;
31312f95 1626
8d01d9a9
AJ		 1627 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1628 and changed later by validate_fix. */
1629 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1630 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1631 return 0;
1632
ce8a8b2f 1633 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1634 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1635 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1636 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1637 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1638 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1639 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1640 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1641 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1642 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1643 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1644 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1645 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1646 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1647 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1648 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1649 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1650 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1651 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1652 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1653 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1654 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1655 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1656 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1657 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1658 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1659 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1660 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1661 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1662 return 0;
31312f95 1663#endif
252b5132
RH		 1664 return 1;
1665}
252b5132 1666
29b0f896 1667static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1668
1669static int
252b5132 1670intel_float_operand (mnemonic)
29b0f896 1671 const char *mnemonic;
252b5132 1672{
9306ca4a
JB		 1673 /* Note that the value returned is meaningful only for opcodes with (memory)
1674 operands, hence the code here is free to improperly handle opcodes that
1675 have no operands (for better performance and smaller code). */
1676
1677 if (mnemonic[0] != 'f')
1678 return 0; /* non-math */
1679
1680 switch (mnemonic[1])
1681 {
1682 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1683 the fs segment override prefix not currently handled because no
1684 call path can make opcodes without operands get here */
1685 case 'i':
1686 return 2 /* integer op */;
1687 case 'l':
1688 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1689 return 3; /* fldcw/fldenv */
1690 break;
1691 case 'n':
1692 if (mnemonic[2] != 'o' /* fnop */)
1693 return 3; /* non-waiting control op */
1694 break;
1695 case 'r':
1696 if (mnemonic[2] == 's')
1697 return 3; /* frstor/frstpm */
1698 break;
1699 case 's':
1700 if (mnemonic[2] == 'a')
1701 return 3; /* fsave */
1702 if (mnemonic[2] == 't')
1703 {
1704 switch (mnemonic[3])
1705 {
1706 case 'c': /* fstcw */
1707 case 'd': /* fstdw */
1708 case 'e': /* fstenv */
1709 case 's': /* fsts[gw] */
1710 return 3;
1711 }
1712 }
1713 break;
1714 case 'x':
1715 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1716 return 0; /* fxsave/fxrstor are not really math ops */
1717 break;
1718 }
252b5132 1719
9306ca4a 1720 return 1;
252b5132
RH		 1721}
1722
1723/* This is the guts of the machine-dependent assembler. LINE points to a
1724 machine dependent instruction. This function is supposed to emit
1725 the frags/bytes it assembles to. */
1726
1727void
1728md_assemble (line)
1729 char *line;
1730{
252b5132 1731 int j;
252b5132
RH		 1732 char mnemonic[MAX_MNEM_SIZE];
1733
47926f60 1734 /* Initialize globals. */
252b5132
RH		 1735 memset (&i, '\0', sizeof (i));
1736 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1737 i.reloc[j] = NO_RELOC;
252b5132
RH		 1738 memset (disp_expressions, '\0', sizeof (disp_expressions));
1739 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1740 save_stack_p = save_stack;
252b5132
RH		 1741
1742 /* First parse an instruction mnemonic & call i386_operand for the operands.
1743 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1744 start of a (possibly prefixed) mnemonic. */
252b5132 1745
29b0f896
AM		 1746 line = parse_insn (line, mnemonic);
1747 if (line == NULL)
1748 return;
252b5132 1749
29b0f896
AM		 1750 line = parse_operands (line, mnemonic);
1751 if (line == NULL)
1752 return;
252b5132 1753
050dfa73
MM		 1754 /* The order of the immediates should be reversed
1755 for 2 immediates extrq and insertq instructions */
1756 if ((i.imm_operands == 2) &&
1757 ((strcmp (mnemonic, "extrq") == 0)
1758 || (strcmp (mnemonic, "insertq") == 0)))
1759 {
1760 swap_imm_operands ();
1761 /* "extrq" and insertq" are the only two instructions whose operands
1762 have to be reversed even though they have two immediate operands.
1763 */
1764 if (intel_syntax)
1765 swap_operands ();
1766 }
1767
29b0f896
AM		 1768 /* Now we've parsed the mnemonic into a set of templates, and have the
1769 operands at hand. */
1770
1771 /* All intel opcodes have reversed operands except for "bound" and
1772 "enter". We also don't reverse intersegment "jmp" and "call"
1773 instructions with 2 immediate operands so that the immediate segment
050dfa73 1774 precedes the offset, as it does when in AT&T mode. */
29b0f896
AM		 1775 if (intel_syntax && i.operands > 1
1776 && (strcmp (mnemonic, "bound") != 0)
30123838 1777 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1778 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1779 swap_operands ();
1780
1781 if (i.imm_operands)
1782 optimize_imm ();
1783
b300c311
L		 1784 /* Don't optimize displacement for movabs since it only takes 64bit
1785 displacement. */
1786 if (i.disp_operands
1787 && (flag_code != CODE_64BIT
1788 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1789 optimize_disp ();
1790
1791 /* Next, we find a template that matches the given insn,
1792 making sure the overlap of the given operands types is consistent
1793 with the template operand types. */
252b5132 1794
29b0f896
AM		 1795 if (!match_template ())
1796 return;
252b5132 1797
cd61ebfe
AM		 1798 if (intel_syntax)
1799 {
1800 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1801 if (SYSV386_COMPAT
1802 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1803 i.tm.base_opcode ^= FloatR;
1804
1805 /* Zap movzx and movsx suffix. The suffix may have been set from
1806 "word ptr" or "byte ptr" on the source operand, but we'll use
1807 the suffix later to choose the destination register. */
1808 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1809 {
1810 if (i.reg_operands < 2
1811 && !i.suffix
1812 && (~i.tm.opcode_modifier
1813 & (No_bSuf
1814 | No_wSuf
1815 | No_lSuf
1816 | No_sSuf
1817 | No_xSuf
1818 | No_qSuf)))
1819 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1820
1821 i.suffix = 0;
1822 }
cd61ebfe 1823 }
24eab124 1824
29b0f896
AM		 1825 if (i.tm.opcode_modifier & FWait)
1826 if (!add_prefix (FWAIT_OPCODE))
1827 return;
252b5132 1828
29b0f896
AM		 1829 /* Check string instruction segment overrides. */
1830 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1831 {
1832 if (!check_string ())
5dd0794d 1833 return;
29b0f896 1834 }
5dd0794d 1835
29b0f896
AM		 1836 if (!process_suffix ())
1837 return;
e413e4e9 1838
29b0f896
AM		 1839 /* Make still unresolved immediate matches conform to size of immediate
1840 given in i.suffix. */
1841 if (!finalize_imm ())
1842 return;
252b5132 1843
29b0f896
AM		 1844 if (i.types[0] & Imm1)
1845 i.imm_operands = 0; /* kludge for shift insns. */
1846 if (i.types[0] & ImplicitRegister)
1847 i.reg_operands--;
1848 if (i.types[1] & ImplicitRegister)
1849 i.reg_operands--;
1850 if (i.types[2] & ImplicitRegister)
1851 i.reg_operands--;
252b5132 1852
29b0f896
AM		 1853 if (i.tm.opcode_modifier & ImmExt)
1854 {
02fc3089
L		 1855 expressionS *exp;
1856
b7d9ef37 1857 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
ca164297 1858 {
b7d9ef37 1859 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 1860 operands with an opcode suffix which is coded in the same
1861 place as an 8-bit immediate field would be. Here we check
1862 those operands and remove them afterwards. */
1863 unsigned int x;
1864
a4622f40 1865 for (x = 0; x < i.operands; x++)
ca164297
L		 1866 if (i.op[x].regs->reg_num != x)
1867 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
64e74474 1868 i.op[x].regs->reg_name, x + 1, i.tm.name);
ca164297
L		 1869 i.operands = 0;
1870 }
1871
29b0f896
AM		 1872 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1873 opcode suffix which is coded in the same place as an 8-bit
1874 immediate field would be. Here we fake an 8-bit immediate
1875 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1876
29b0f896 1877 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1878
29b0f896
AM		 1879 exp = &im_expressions[i.imm_operands++];
1880 i.op[i.operands].imms = exp;
1881 i.types[i.operands++] = Imm8;
1882 exp->X_op = O_constant;
1883 exp->X_add_number = i.tm.extension_opcode;
1884 i.tm.extension_opcode = None;
1885 }
252b5132 1886
29b0f896
AM		 1887 /* For insns with operands there are more diddles to do to the opcode. */
1888 if (i.operands)
1889 {
1890 if (!process_operands ())
1891 return;
1892 }
1893 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1894 {
1895 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1896 as_warn (_("translating to `%sp'"), i.tm.name);
1897 }
252b5132 1898
29b0f896
AM		 1899 /* Handle conversion of 'int $3' --> special int3 insn. */
1900 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1901 {
1902 i.tm.base_opcode = INT3_OPCODE;
1903 i.imm_operands = 0;
1904 }
252b5132 1905
29b0f896
AM		 1906 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1907 && i.op[0].disps->X_op == O_constant)
1908 {
1909 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1910 the absolute address given by the constant. Since ix86 jumps and
1911 calls are pc relative, we need to generate a reloc. */
1912 i.op[0].disps->X_add_symbol = &abs_symbol;
1913 i.op[0].disps->X_op = O_symbol;
1914 }
252b5132 1915
29b0f896
AM		 1916 if ((i.tm.opcode_modifier & Rex64) != 0)
1917 i.rex |= REX_MODE64;
252b5132 1918
29b0f896
AM		 1919 /* For 8 bit registers we need an empty rex prefix. Also if the
1920 instruction already has a prefix, we need to convert old
1921 registers to new ones. */
773f551c 1922
29b0f896
AM		 1923 if (((i.types[0] & Reg8) != 0
1924 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1925 || ((i.types[1] & Reg8) != 0
1926 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1927 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1928 && i.rex != 0))
1929 {
1930 int x;
726c5dcd 1931
29b0f896
AM		 1932 i.rex |= REX_OPCODE;
1933 for (x = 0; x < 2; x++)
1934 {
1935 /* Look for 8 bit operand that uses old registers. */
1936 if ((i.types[x] & Reg8) != 0
1937 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1938 {
29b0f896
AM		 1939 /* In case it is "hi" register, give up. */
1940 if (i.op[x].regs->reg_num > 3)
0477af35 1941 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1942 i.op[x].regs->reg_name);
773f551c 1943
29b0f896
AM		 1944 /* Otherwise it is equivalent to the extended register.
1945 Since the encoding doesn't change this is merely
1946 cosmetic cleanup for debug output. */
1947
1948 i.op[x].regs = i.op[x].regs + 8;
773f551c 1949 }
29b0f896
AM		 1950 }
1951 }
773f551c 1952
29b0f896
AM		 1953 if (i.rex != 0)
1954 add_prefix (REX_OPCODE | i.rex);
1955
1956 /* We are ready to output the insn. */
1957 output_insn ();
1958}
1959
1960static char *
1961parse_insn (line, mnemonic)
1962 char *line;
1963 char *mnemonic;
1964{
1965 char *l = line;
1966 char *token_start = l;
1967 char *mnem_p;
5c6af06e
JB		 1968 int supported;
1969 const template *t;
29b0f896
AM		 1970
1971 /* Non-zero if we found a prefix only acceptable with string insns. */
1972 const char *expecting_string_instruction = NULL;
45288df1 1973
29b0f896
AM		 1974 while (1)
1975 {
1976 mnem_p = mnemonic;
1977 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1978 {
1979 mnem_p++;
1980 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1981 {
29b0f896
AM		 1982 as_bad (_("no such instruction: `%s'"), token_start);
1983 return NULL;
1984 }
1985 l++;
1986 }
1987 if (!is_space_char (*l)
1988 && *l != END_OF_INSN
e44823cf
JB		 1989 && (intel_syntax
1990 || (*l != PREFIX_SEPARATOR
1991 && *l != ',')))
29b0f896
AM		 1992 {
1993 as_bad (_("invalid character %s in mnemonic"),
1994 output_invalid (*l));
1995 return NULL;
1996 }
1997 if (token_start == l)
1998 {
e44823cf 1999 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2000 as_bad (_("expecting prefix; got nothing"));
2001 else
2002 as_bad (_("expecting mnemonic; got nothing"));
2003 return NULL;
2004 }
45288df1 2005
29b0f896
AM		 2006 /* Look up instruction (or prefix) via hash table. */
2007 current_templates = hash_find (op_hash, mnemonic);
47926f60 2008
29b0f896
AM		 2009 if (*l != END_OF_INSN
2010 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2011 && current_templates
2012 && (current_templates->start->opcode_modifier & IsPrefix))
2013 {
2dd88dca
JB		 2014 if (current_templates->start->cpu_flags
2015 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
2016 {
2017 as_bad ((flag_code != CODE_64BIT
2018 ? _("`%s' is only supported in 64-bit mode")
2019 : _("`%s' is not supported in 64-bit mode")),
2020 current_templates->start->name);
2021 return NULL;
2022 }
29b0f896
AM		 2023 /* If we are in 16-bit mode, do not allow addr16 or data16.
2024 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2025 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
2026 && flag_code != CODE_64BIT
2027 && (((current_templates->start->opcode_modifier & Size32) != 0)
2028 ^ (flag_code == CODE_16BIT)))
2029 {
2030 as_bad (_("redundant %s prefix"),
2031 current_templates->start->name);
2032 return NULL;
45288df1 2033 }
29b0f896
AM		 2034 /* Add prefix, checking for repeated prefixes. */
2035 switch (add_prefix (current_templates->start->base_opcode))
2036 {
2037 case 0:
2038 return NULL;
2039 case 2:
2040 expecting_string_instruction = current_templates->start->name;
2041 break;
2042 }
2043 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2044 token_start = ++l;
2045 }
2046 else
2047 break;
2048 }
45288df1 2049
29b0f896
AM		 2050 if (!current_templates)
2051 {
2052 /* See if we can get a match by trimming off a suffix. */
2053 switch (mnem_p[-1])
2054 {
2055 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2056 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2057 i.suffix = SHORT_MNEM_SUFFIX;
2058 else
29b0f896
AM		 2059 case BYTE_MNEM_SUFFIX:
2060 case QWORD_MNEM_SUFFIX:
2061 i.suffix = mnem_p[-1];
2062 mnem_p[-1] = '\0';
2063 current_templates = hash_find (op_hash, mnemonic);
2064 break;
2065 case SHORT_MNEM_SUFFIX:
2066 case LONG_MNEM_SUFFIX:
2067 if (!intel_syntax)
2068 {
2069 i.suffix = mnem_p[-1];
2070 mnem_p[-1] = '\0';
2071 current_templates = hash_find (op_hash, mnemonic);
2072 }
2073 break;
252b5132 2074
29b0f896
AM		 2075 /* Intel Syntax. */
2076 case 'd':
2077 if (intel_syntax)
2078 {
9306ca4a 2079 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2080 i.suffix = SHORT_MNEM_SUFFIX;
2081 else
2082 i.suffix = LONG_MNEM_SUFFIX;
2083 mnem_p[-1] = '\0';
2084 current_templates = hash_find (op_hash, mnemonic);
2085 }
2086 break;
2087 }
2088 if (!current_templates)
2089 {
2090 as_bad (_("no such instruction: `%s'"), token_start);
2091 return NULL;
2092 }
2093 }
252b5132 2094
29b0f896
AM		 2095 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2096 {
2097 /* Check for a branch hint. We allow ",pt" and ",pn" for
2098 predict taken and predict not taken respectively.
2099 I'm not sure that branch hints actually do anything on loop
2100 and jcxz insns (JumpByte) for current Pentium4 chips. They
2101 may work in the future and it doesn't hurt to accept them
2102 now. */
2103 if (l[0] == ',' && l[1] == 'p')
2104 {
2105 if (l[2] == 't')
2106 {
2107 if (!add_prefix (DS_PREFIX_OPCODE))
2108 return NULL;
2109 l += 3;
2110 }
2111 else if (l[2] == 'n')
2112 {
2113 if (!add_prefix (CS_PREFIX_OPCODE))
2114 return NULL;
2115 l += 3;
2116 }
2117 }
2118 }
2119 /* Any other comma loses. */
2120 if (*l == ',')
2121 {
2122 as_bad (_("invalid character %s in mnemonic"),
2123 output_invalid (*l));
2124 return NULL;
2125 }
252b5132 2126
29b0f896 2127 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2128 supported = 0;
2129 for (t = current_templates->start; t < current_templates->end; ++t)
2130 {
2131 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2132 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 2133 supported |= 1;
5c6af06e 2134 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 2135 supported |= 2;
5c6af06e
JB		 2136 }
2137 if (!(supported & 2))
2138 {
2139 as_bad (flag_code == CODE_64BIT
2140 ? _("`%s' is not supported in 64-bit mode")
2141 : _("`%s' is only supported in 64-bit mode"),
2142 current_templates->start->name);
2143 return NULL;
2144 }
2145 if (!(supported & 1))
29b0f896 2146 {
5c6af06e
JB		 2147 as_warn (_("`%s' is not supported on `%s%s'"),
2148 current_templates->start->name,
2149 cpu_arch_name,
2150 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 2151 }
2152 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2153 {
2154 as_warn (_("use .code16 to ensure correct addressing mode"));
2155 }
252b5132 2156
29b0f896 2157 /* Check for rep/repne without a string instruction. */
f41bbced 2158 if (expecting_string_instruction)
29b0f896 2159 {
f41bbced
JB		 2160 static templates override;
2161
2162 for (t = current_templates->start; t < current_templates->end; ++t)
2163 if (t->opcode_modifier & IsString)
2164 break;
2165 if (t >= current_templates->end)
2166 {
2167 as_bad (_("expecting string instruction after `%s'"),
64e74474 2168 expecting_string_instruction);
f41bbced
JB		 2169 return NULL;
2170 }
2171 for (override.start = t; t < current_templates->end; ++t)
2172 if (!(t->opcode_modifier & IsString))
2173 break;
2174 override.end = t;
2175 current_templates = &override;
29b0f896 2176 }
252b5132 2177
29b0f896
AM		 2178 return l;
2179}
252b5132 2180
29b0f896
AM		 2181static char *
2182parse_operands (l, mnemonic)
2183 char *l;
2184 const char *mnemonic;
2185{
2186 char *token_start;
3138f287 2187
29b0f896
AM		 2188 /* 1 if operand is pending after ','. */
2189 unsigned int expecting_operand = 0;
252b5132 2190
29b0f896
AM		 2191 /* Non-zero if operand parens not balanced. */
2192 unsigned int paren_not_balanced;
2193
2194 while (*l != END_OF_INSN)
2195 {
2196 /* Skip optional white space before operand. */
2197 if (is_space_char (*l))
2198 ++l;
2199 if (!is_operand_char (*l) && *l != END_OF_INSN)
2200 {
2201 as_bad (_("invalid character %s before operand %d"),
2202 output_invalid (*l),
2203 i.operands + 1);
2204 return NULL;
2205 }
2206 token_start = l; /* after white space */
2207 paren_not_balanced = 0;
2208 while (paren_not_balanced || *l != ',')
2209 {
2210 if (*l == END_OF_INSN)
2211 {
2212 if (paren_not_balanced)
2213 {
2214 if (!intel_syntax)
2215 as_bad (_("unbalanced parenthesis in operand %d."),
2216 i.operands + 1);
2217 else
2218 as_bad (_("unbalanced brackets in operand %d."),
2219 i.operands + 1);
2220 return NULL;
2221 }
2222 else
2223 break; /* we are done */
2224 }
2225 else if (!is_operand_char (*l) && !is_space_char (*l))
2226 {
2227 as_bad (_("invalid character %s in operand %d"),
2228 output_invalid (*l),
2229 i.operands + 1);
2230 return NULL;
2231 }
2232 if (!intel_syntax)
2233 {
2234 if (*l == '(')
2235 ++paren_not_balanced;
2236 if (*l == ')')
2237 --paren_not_balanced;
2238 }
2239 else
2240 {
2241 if (*l == '[')
2242 ++paren_not_balanced;
2243 if (*l == ']')
2244 --paren_not_balanced;
2245 }
2246 l++;
2247 }
2248 if (l != token_start)
2249 { /* Yes, we've read in another operand. */
2250 unsigned int operand_ok;
2251 this_operand = i.operands++;
2252 if (i.operands > MAX_OPERANDS)
2253 {
2254 as_bad (_("spurious operands; (%d operands/instruction max)"),
2255 MAX_OPERANDS);
2256 return NULL;
2257 }
2258 /* Now parse operand adding info to 'i' as we go along. */
2259 END_STRING_AND_SAVE (l);
2260
2261 if (intel_syntax)
2262 operand_ok =
2263 i386_intel_operand (token_start,
2264 intel_float_operand (mnemonic));
2265 else
2266 operand_ok = i386_operand (token_start);
2267
2268 RESTORE_END_STRING (l);
2269 if (!operand_ok)
2270 return NULL;
2271 }
2272 else
2273 {
2274 if (expecting_operand)
2275 {
2276 expecting_operand_after_comma:
2277 as_bad (_("expecting operand after ','; got nothing"));
2278 return NULL;
2279 }
2280 if (*l == ',')
2281 {
2282 as_bad (_("expecting operand before ','; got nothing"));
2283 return NULL;
2284 }
2285 }
7f3f1ea2 2286
29b0f896
AM		 2287 /* Now *l must be either ',' or END_OF_INSN. */
2288 if (*l == ',')
2289 {
2290 if (*++l == END_OF_INSN)
2291 {
2292 /* Just skip it, if it's \n complain. */
2293 goto expecting_operand_after_comma;
2294 }
2295 expecting_operand = 1;
2296 }
2297 }
2298 return l;
2299}
7f3f1ea2 2300
050dfa73
MM		 2301static void
2302swap_imm_operands ()
2303{
2304 union i386_op temp_op;
2305 unsigned int temp_type;
2306 enum bfd_reloc_code_real temp_reloc;
2307 int xchg1 = 0;
2308 int xchg2 = 1;
2309
2310 temp_type = i.types[xchg2];
2311 i.types[xchg2] = i.types[xchg1];
2312 i.types[xchg1] = temp_type;
2313 temp_op = i.op[xchg2];
2314 i.op[xchg2] = i.op[xchg1];
2315 i.op[xchg1] = temp_op;
2316 temp_reloc = i.reloc[xchg2];
2317 i.reloc[xchg2] = i.reloc[xchg1];
2318 i.reloc[xchg1] = temp_reloc;
2319}
2320
2321
29b0f896
AM		 2322static void
2323swap_operands ()
2324{
2325 union i386_op temp_op;
2326 unsigned int temp_type;
f86103b7 2327 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 2328 int xchg1 = 0;
2329 int xchg2 = 0;
252b5132 2330
050dfa73
MM		 2331 if (i.operands == 4)
2332 /* There will be two exchanges in a 4 operand instruction.
2333 First exchange is the done inside this block.(1st and 4rth operand)
2334 The next exchange is done outside this block.(2nd and 3rd operand) */
2335 {
2336 xchg1 = 0;
2337 xchg2 = 3;
2338 temp_type = i.types[xchg2];
2339 i.types[xchg2] = i.types[xchg1];
2340 i.types[xchg1] = temp_type;
2341 temp_op = i.op[xchg2];
2342 i.op[xchg2] = i.op[xchg1];
2343 i.op[xchg1] = temp_op;
2344 temp_reloc = i.reloc[xchg2];
2345 i.reloc[xchg2] = i.reloc[xchg1];
2346 i.reloc[xchg1] = temp_reloc;
2347 xchg1 = 1;
2348 xchg2 = 2;
2349 }
2350
29b0f896
AM		 2351 if (i.operands == 2)
2352 {
2353 xchg1 = 0;
2354 xchg2 = 1;
2355 }
2356 else if (i.operands == 3)
2357 {
2358 xchg1 = 0;
2359 xchg2 = 2;
2360 }
2361 temp_type = i.types[xchg2];
2362 i.types[xchg2] = i.types[xchg1];
2363 i.types[xchg1] = temp_type;
2364 temp_op = i.op[xchg2];
2365 i.op[xchg2] = i.op[xchg1];
2366 i.op[xchg1] = temp_op;
2367 temp_reloc = i.reloc[xchg2];
2368 i.reloc[xchg2] = i.reloc[xchg1];
2369 i.reloc[xchg1] = temp_reloc;
2370
2371 if (i.mem_operands == 2)
2372 {
2373 const seg_entry *temp_seg;
2374 temp_seg = i.seg[0];
2375 i.seg[0] = i.seg[1];
2376 i.seg[1] = temp_seg;
2377 }
2378}
252b5132 2379
29b0f896
AM		 2380/* Try to ensure constant immediates are represented in the smallest
2381 opcode possible. */
2382static void
2383optimize_imm ()
2384{
2385 char guess_suffix = 0;
2386 int op;
252b5132 2387
29b0f896
AM		 2388 if (i.suffix)
2389 guess_suffix = i.suffix;
2390 else if (i.reg_operands)
2391 {
2392 /* Figure out a suffix from the last register operand specified.
2393 We can't do this properly yet, ie. excluding InOutPortReg,
2394 but the following works for instructions with immediates.
2395 In any case, we can't set i.suffix yet. */
2396 for (op = i.operands; --op >= 0;)
2397 if (i.types[op] & Reg)
252b5132 2398 {
29b0f896
AM		 2399 if (i.types[op] & Reg8)
2400 guess_suffix = BYTE_MNEM_SUFFIX;
2401 else if (i.types[op] & Reg16)
2402 guess_suffix = WORD_MNEM_SUFFIX;
2403 else if (i.types[op] & Reg32)
2404 guess_suffix = LONG_MNEM_SUFFIX;
2405 else if (i.types[op] & Reg64)
2406 guess_suffix = QWORD_MNEM_SUFFIX;
2407 break;
252b5132 2408 }
29b0f896
AM		 2409 }
2410 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2411 guess_suffix = WORD_MNEM_SUFFIX;
2412
2413 for (op = i.operands; --op >= 0;)
2414 if (i.types[op] & Imm)
2415 {
2416 switch (i.op[op].imms->X_op)
252b5132 2417 {
29b0f896
AM		 2418 case O_constant:
2419 /* If a suffix is given, this operand may be shortened. */
2420 switch (guess_suffix)
252b5132 2421 {
29b0f896
AM		 2422 case LONG_MNEM_SUFFIX:
2423 i.types[op] |= Imm32 | Imm64;
2424 break;
2425 case WORD_MNEM_SUFFIX:
2426 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2427 break;
2428 case BYTE_MNEM_SUFFIX:
2429 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2430 break;
252b5132 2431 }
252b5132 2432
29b0f896
AM		 2433 /* If this operand is at most 16 bits, convert it
2434 to a signed 16 bit number before trying to see
2435 whether it will fit in an even smaller size.
2436 This allows a 16-bit operand such as $0xffe0 to
2437 be recognised as within Imm8S range. */
2438 if ((i.types[op] & Imm16)
2439 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2440 {
29b0f896
AM		 2441 i.op[op].imms->X_add_number =
2442 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2443 }
2444 if ((i.types[op] & Imm32)
2445 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2446 == 0))
2447 {
2448 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2449 ^ ((offsetT) 1 << 31))
2450 - ((offsetT) 1 << 31));
2451 }
2452 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2453
29b0f896
AM		 2454 /* We must avoid matching of Imm32 templates when 64bit
2455 only immediate is available. */
2456 if (guess_suffix == QWORD_MNEM_SUFFIX)
2457 i.types[op] &= ~Imm32;
2458 break;
252b5132 2459
29b0f896
AM		 2460 case O_absent:
2461 case O_register:
2462 abort ();
2463
2464 /* Symbols and expressions. */
2465 default:
9cd96992
JB		 2466 /* Convert symbolic operand to proper sizes for matching, but don't
2467 prevent matching a set of insns that only supports sizes other
2468 than those matching the insn suffix. */
2469 {
2470 unsigned int mask, allowed = 0;
2471 const template *t;
2472
2473 for (t = current_templates->start; t < current_templates->end; ++t)
2474 allowed |= t->operand_types[op];
2475 switch (guess_suffix)
2476 {
2477 case QWORD_MNEM_SUFFIX:
2478 mask = Imm64 | Imm32S;
2479 break;
2480 case LONG_MNEM_SUFFIX:
2481 mask = Imm32;
2482 break;
2483 case WORD_MNEM_SUFFIX:
2484 mask = Imm16;
2485 break;
2486 case BYTE_MNEM_SUFFIX:
2487 mask = Imm8;
2488 break;
2489 default:
2490 mask = 0;
2491 break;
2492 }
64e74474
AM		 2493 if (mask & allowed)
2494 i.types[op] &= mask;
9cd96992 2495 }
29b0f896 2496 break;
252b5132 2497 }
29b0f896
AM		 2498 }
2499}
47926f60 2500
29b0f896
AM		 2501/* Try to use the smallest displacement type too. */
2502static void
2503optimize_disp ()
2504{
2505 int op;
3e73aa7c 2506
29b0f896 2507 for (op = i.operands; --op >= 0;)
b300c311 2508 if (i.types[op] & Disp)
252b5132 2509 {
b300c311 2510 if (i.op[op].disps->X_op == O_constant)
252b5132 2511 {
b300c311 2512 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2513
b300c311
L		 2514 if ((i.types[op] & Disp16)
2515 && (disp & ~(offsetT) 0xffff) == 0)
2516 {
2517 /* If this operand is at most 16 bits, convert
2518 to a signed 16 bit number and don't use 64bit
2519 displacement. */
2520 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2521 i.types[op] &= ~Disp64;
2522 }
2523 if ((i.types[op] & Disp32)
2524 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2525 {
2526 /* If this operand is at most 32 bits, convert
2527 to a signed 32 bit number and don't use 64bit
2528 displacement. */
2529 disp &= (((offsetT) 2 << 31) - 1);
2530 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2531 i.types[op] &= ~Disp64;
2532 }
2533 if (!disp && (i.types[op] & BaseIndex))
2534 {
2535 i.types[op] &= ~Disp;
2536 i.op[op].disps = 0;
2537 i.disp_operands--;
2538 }
2539 else if (flag_code == CODE_64BIT)
2540 {
2541 if (fits_in_signed_long (disp))
28a9d8f5
L		 2542 {
2543 i.types[op] &= ~Disp64;
2544 i.types[op] |= Disp32S;
2545 }
b300c311
L		 2546 if (fits_in_unsigned_long (disp))
2547 i.types[op] |= Disp32;
2548 }
2549 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2550 && fits_in_signed_byte (disp))
2551 i.types[op] |= Disp8;
252b5132 2552 }
67a4f2b7
AO		 2553 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2554 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2555 {
2556 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2557 i.op[op].disps, 0, i.reloc[op]);
2558 i.types[op] &= ~Disp;
2559 }
2560 else
b300c311
L		 2561 /* We only support 64bit displacement on constants. */
2562 i.types[op] &= ~Disp64;
252b5132 2563 }
29b0f896
AM		 2564}
2565
2566static int
2567match_template ()
2568{
2569 /* Points to template once we've found it. */
2570 const template *t;
f48ff2ae 2571 unsigned int overlap0, overlap1, overlap2, overlap3;
29b0f896
AM		 2572 unsigned int found_reverse_match;
2573 int suffix_check;
f48ff2ae 2574 unsigned int operand_types [MAX_OPERANDS];
539e75ad 2575 int addr_prefix_disp;
a5c311ca 2576 unsigned int j;
29b0f896 2577
f48ff2ae
L		 2578#if MAX_OPERANDS != 4
2579# error "MAX_OPERANDS must be 4."
2580#endif
2581
29b0f896
AM		 2582#define MATCH(overlap, given, template) \
2583 ((overlap & ~JumpAbsolute) \
2584 && (((given) & (BaseIndex | JumpAbsolute)) \
2585 == ((overlap) & (BaseIndex | JumpAbsolute))))
2586
2587 /* If given types r0 and r1 are registers they must be of the same type
2588 unless the expected operand type register overlap is null.
2589 Note that Acc in a template matches every size of reg. */
2590#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2591 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2592 || ((g0) & Reg) == ((g1) & Reg) \
2593 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2594
2595 overlap0 = 0;
2596 overlap1 = 0;
2597 overlap2 = 0;
f48ff2ae 2598 overlap3 = 0;
29b0f896 2599 found_reverse_match = 0;
a5c311ca
L		 2600 for (j = 0; j < MAX_OPERANDS; j++)
2601 operand_types [j] = 0;
539e75ad 2602 addr_prefix_disp = -1;
29b0f896
AM		 2603 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2604 ? No_bSuf
2605 : (i.suffix == WORD_MNEM_SUFFIX
2606 ? No_wSuf
2607 : (i.suffix == SHORT_MNEM_SUFFIX
2608 ? No_sSuf
2609 : (i.suffix == LONG_MNEM_SUFFIX
2610 ? No_lSuf
2611 : (i.suffix == QWORD_MNEM_SUFFIX
2612 ? No_qSuf
2613 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2614 ? No_xSuf : 0))))));
2615
45aa61fe 2616 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2617 {
539e75ad
L		 2618 addr_prefix_disp = -1;
2619
29b0f896
AM		 2620 /* Must have right number of operands. */
2621 if (i.operands != t->operands)
2622 continue;
2623
2624 /* Check the suffix, except for some instructions in intel mode. */
2625 if ((t->opcode_modifier & suffix_check)
2626 && !(intel_syntax
9306ca4a 2627 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2628 continue;
2629
a5c311ca
L		 2630 for (j = 0; j < MAX_OPERANDS; j++)
2631 operand_types [j] = t->operand_types [j];
539e75ad 2632
45aa61fe
AM		 2633 /* In general, don't allow 64-bit operands in 32-bit mode. */
2634 if (i.suffix == QWORD_MNEM_SUFFIX
2635 && flag_code != CODE_64BIT
2636 && (intel_syntax
2637 ? (!(t->opcode_modifier & IgnoreSize)
2638 && !intel_float_operand (t->name))
2639 : intel_float_operand (t->name) != 2)
539e75ad
L		 2640 && (!(operand_types[0] & (RegMMX | RegXMM))
2641 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
45aa61fe
AM		 2642 && (t->base_opcode != 0x0fc7
2643 || t->extension_opcode != 1 /* cmpxchg8b */))
2644 continue;
2645
29b0f896
AM		 2646 /* Do not verify operands when there are none. */
2647 else if (!t->operands)
2648 {
2649 if (t->cpu_flags & ~cpu_arch_flags)
2650 continue;
2651 /* We've found a match; break out of loop. */
2652 break;
2653 }
252b5132 2654
539e75ad
L		 2655 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2656 into Disp32/Disp16/Disp32 operand. */
2657 if (i.prefix[ADDR_PREFIX] != 0)
2658 {
a5c311ca 2659 unsigned int DispOn = 0, DispOff = 0;
539e75ad
L		 2660
2661 switch (flag_code)
2662 {
2663 case CODE_16BIT:
2664 DispOn = Disp32;
2665 DispOff = Disp16;
2666 break;
2667 case CODE_32BIT:
2668 DispOn = Disp16;
2669 DispOff = Disp32;
2670 break;
2671 case CODE_64BIT:
2672 DispOn = Disp32;
2673 DispOff = Disp64;
2674 break;
2675 }
2676
f48ff2ae 2677 for (j = 0; j < MAX_OPERANDS; j++)
539e75ad
L		 2678 {
2679 /* There should be only one Disp operand. */
2680 if ((operand_types[j] & DispOff))
2681 {
2682 addr_prefix_disp = j;
2683 operand_types[j] |= DispOn;
2684 operand_types[j] &= ~DispOff;
2685 break;
2686 }
2687 }
2688 }
2689
2690 overlap0 = i.types[0] & operand_types[0];
29b0f896
AM		 2691 switch (t->operands)
2692 {
2693 case 1:
539e75ad 2694 if (!MATCH (overlap0, i.types[0], operand_types[0]))
29b0f896
AM		 2695 continue;
2696 break;
2697 case 2:
2698 case 3:
f48ff2ae 2699 case 4:
539e75ad
L		 2700 overlap1 = i.types[1] & operand_types[1];
2701 if (!MATCH (overlap0, i.types[0], operand_types[0])
2702 || !MATCH (overlap1, i.types[1], operand_types[1])
cb712a9e 2703 /* monitor in SSE3 is a very special case. The first
708587a4 2704 register and the second register may have different
cb712a9e
L		 2705 sizes. */
2706 || !((t->base_opcode == 0x0f01
2707 && t->extension_opcode == 0xc8)
2708 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2709 operand_types[0],
cb712a9e 2710 overlap1, i.types[1],
539e75ad 2711 operand_types[1])))
29b0f896
AM		 2712 {
2713 /* Check if other direction is valid ... */
2714 if ((t->opcode_modifier & (D | FloatD)) == 0)
2715 continue;
2716
2717 /* Try reversing direction of operands. */
539e75ad
L		 2718 overlap0 = i.types[0] & operand_types[1];
2719 overlap1 = i.types[1] & operand_types[0];
2720 if (!MATCH (overlap0, i.types[0], operand_types[1])
2721 || !MATCH (overlap1, i.types[1], operand_types[0])
29b0f896 2722 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2723 operand_types[1],
29b0f896 2724 overlap1, i.types[1],
539e75ad 2725 operand_types[0]))
29b0f896
AM		 2726 {
2727 /* Does not match either direction. */
2728 continue;
2729 }
2730 /* found_reverse_match holds which of D or FloatDR
2731 we've found. */
2732 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2733 }
f48ff2ae 2734 else
29b0f896 2735 {
f48ff2ae
L		 2736 /* Found a forward 2 operand match here. */
2737 if (t->operands > 2)
2738 overlap2 = i.types[2] & operand_types[2];
2739 if (t->operands > 3)
2740 overlap3 = i.types[3] & operand_types[3];
29b0f896 2741
f48ff2ae
L		 2742 switch (t->operands)
2743 {
2744 case 4:
2745 if (!MATCH (overlap3, i.types[3], operand_types[3])
2746 || !CONSISTENT_REGISTER_MATCH (overlap2,
2747 i.types[2],
2748 operand_types[2],
2749 overlap3,
2750 i.types[3],
2751 operand_types[3]))
2752 continue;
2753 case 3:
2754 /* Here we make use of the fact that there are no
2755 reverse match 3 operand instructions, and all 3
2756 operand instructions only need to be checked for
2757 register consistency between operands 2 and 3. */
2758 if (!MATCH (overlap2, i.types[2], operand_types[2])
2759 || !CONSISTENT_REGISTER_MATCH (overlap1,
2760 i.types[1],
2761 operand_types[1],
2762 overlap2,
2763 i.types[2],
2764 operand_types[2]))
2765 continue;
2766 break;
2767 }
29b0f896 2768 }
f48ff2ae 2769 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 2770 slip through to break. */
2771 }
2772 if (t->cpu_flags & ~cpu_arch_flags)
2773 {
2774 found_reverse_match = 0;
2775 continue;
2776 }
2777 /* We've found a match; break out of loop. */
2778 break;
2779 }
2780
2781 if (t == current_templates->end)
2782 {
2783 /* We found no match. */
2784 as_bad (_("suffix or operands invalid for `%s'"),
2785 current_templates->start->name);
2786 return 0;
2787 }
252b5132 2788
29b0f896
AM		 2789 if (!quiet_warnings)
2790 {
2791 if (!intel_syntax
2792 && ((i.types[0] & JumpAbsolute)
539e75ad 2793 != (operand_types[0] & JumpAbsolute)))
29b0f896
AM		 2794 {
2795 as_warn (_("indirect %s without `*'"), t->name);
2796 }
2797
2798 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2799 == (IsPrefix | IgnoreSize))
2800 {
2801 /* Warn them that a data or address size prefix doesn't
2802 affect assembly of the next line of code. */
2803 as_warn (_("stand-alone `%s' prefix"), t->name);
2804 }
2805 }
2806
2807 /* Copy the template we found. */
2808 i.tm = *t;
539e75ad
L		 2809
2810 if (addr_prefix_disp != -1)
2811 i.tm.operand_types[addr_prefix_disp]
2812 = operand_types[addr_prefix_disp];
2813
29b0f896
AM		 2814 if (found_reverse_match)
2815 {
2816 /* If we found a reverse match we must alter the opcode
2817 direction bit. found_reverse_match holds bits to change
2818 (different for int & float insns). */
2819
2820 i.tm.base_opcode ^= found_reverse_match;
2821
539e75ad
L		 2822 i.tm.operand_types[0] = operand_types[1];
2823 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 2824 }
2825
2826 return 1;
2827}
2828
2829static int
2830check_string ()
2831{
2832 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2833 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2834 {
2835 if (i.seg[0] != NULL && i.seg[0] != &es)
2836 {
2837 as_bad (_("`%s' operand %d must use `%%es' segment"),
2838 i.tm.name,
2839 mem_op + 1);
2840 return 0;
2841 }
2842 /* There's only ever one segment override allowed per instruction.
2843 This instruction possibly has a legal segment override on the
2844 second operand, so copy the segment to where non-string
2845 instructions store it, allowing common code. */
2846 i.seg[0] = i.seg[1];
2847 }
2848 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2849 {
2850 if (i.seg[1] != NULL && i.seg[1] != &es)
2851 {
2852 as_bad (_("`%s' operand %d must use `%%es' segment"),
2853 i.tm.name,
2854 mem_op + 2);
2855 return 0;
2856 }
2857 }
2858 return 1;
2859}
2860
2861static int
543613e9 2862process_suffix (void)
29b0f896
AM		 2863{
2864 /* If matched instruction specifies an explicit instruction mnemonic
2865 suffix, use it. */
2866 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2867 {
2868 if (i.tm.opcode_modifier & Size16)
2869 i.suffix = WORD_MNEM_SUFFIX;
2870 else if (i.tm.opcode_modifier & Size64)
2871 i.suffix = QWORD_MNEM_SUFFIX;
2872 else
2873 i.suffix = LONG_MNEM_SUFFIX;
2874 }
2875 else if (i.reg_operands)
2876 {
2877 /* If there's no instruction mnemonic suffix we try to invent one
2878 based on register operands. */
2879 if (!i.suffix)
2880 {
2881 /* We take i.suffix from the last register operand specified,
2882 Destination register type is more significant than source
2883 register type. */
2884 int op;
543613e9 2885
29b0f896
AM		 2886 for (op = i.operands; --op >= 0;)
2887 if ((i.types[op] & Reg)
2888 && !(i.tm.operand_types[op] & InOutPortReg))
2889 {
2890 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2891 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2892 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2893 LONG_MNEM_SUFFIX);
2894 break;
2895 }
2896 }
2897 else if (i.suffix == BYTE_MNEM_SUFFIX)
2898 {
2899 if (!check_byte_reg ())
2900 return 0;
2901 }
2902 else if (i.suffix == LONG_MNEM_SUFFIX)
2903 {
2904 if (!check_long_reg ())
2905 return 0;
2906 }
2907 else if (i.suffix == QWORD_MNEM_SUFFIX)
2908 {
2909 if (!check_qword_reg ())
2910 return 0;
2911 }
2912 else if (i.suffix == WORD_MNEM_SUFFIX)
2913 {
2914 if (!check_word_reg ())
2915 return 0;
2916 }
2917 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2918 /* Do nothing if the instruction is going to ignore the prefix. */
2919 ;
2920 else
2921 abort ();
2922 }
9306ca4a
JB		 2923 else if ((i.tm.opcode_modifier & DefaultSize)
2924 && !i.suffix
2925 /* exclude fldenv/frstor/fsave/fstenv */
2926 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2927 {
2928 i.suffix = stackop_size;
2929 }
9306ca4a
JB		 2930 else if (intel_syntax
2931 && !i.suffix
2932 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2933 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2934 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2935 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2936 {
2937 switch (flag_code)
2938 {
2939 case CODE_64BIT:
2940 if (!(i.tm.opcode_modifier & No_qSuf))
2941 {
2942 i.suffix = QWORD_MNEM_SUFFIX;
2943 break;
2944 }
2945 case CODE_32BIT:
2946 if (!(i.tm.opcode_modifier & No_lSuf))
2947 i.suffix = LONG_MNEM_SUFFIX;
2948 break;
2949 case CODE_16BIT:
2950 if (!(i.tm.opcode_modifier & No_wSuf))
2951 i.suffix = WORD_MNEM_SUFFIX;
2952 break;
2953 }
2954 }
252b5132 2955
9306ca4a 2956 if (!i.suffix)
29b0f896 2957 {
9306ca4a
JB		 2958 if (!intel_syntax)
2959 {
2960 if (i.tm.opcode_modifier & W)
2961 {
2962 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2963 return 0;
2964 }
2965 }
2966 else
2967 {
64e74474
AM		 2968 unsigned int suffixes = (~i.tm.opcode_modifier
2969 & (No_bSuf
2970 | No_wSuf
2971 | No_lSuf
2972 | No_sSuf
2973 | No_xSuf
2974 | No_qSuf));
9306ca4a
JB		 2975
2976 if ((i.tm.opcode_modifier & W)
2977 || ((suffixes & (suffixes - 1))
2978 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2979 {
2980 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2981 return 0;
2982 }
2983 }
29b0f896 2984 }
252b5132 2985
9306ca4a
JB		 2986 /* Change the opcode based on the operand size given by i.suffix;
2987 We don't need to change things for byte insns. */
2988
29b0f896
AM		 2989 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2990 {
2991 /* It's not a byte, select word/dword operation. */
2992 if (i.tm.opcode_modifier & W)
2993 {
2994 if (i.tm.opcode_modifier & ShortForm)
2995 i.tm.base_opcode |= 8;
2996 else
2997 i.tm.base_opcode |= 1;
2998 }
0f3f3d8b 2999
29b0f896
AM		 3000 /* Now select between word & dword operations via the operand
3001 size prefix, except for instructions that will ignore this
3002 prefix anyway. */
cb712a9e
L		 3003 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
3004 {
3005 /* monitor in SSE3 is a very special case. The default size
3006 of AX is the size of mode. The address size override
3007 prefix will change the size of AX. */
3008 if (i.op->regs[0].reg_type &
3009 (flag_code == CODE_32BIT ? Reg16 : Reg32))
3010 if (!add_prefix (ADDR_PREFIX_OPCODE))
3011 return 0;
3012 }
3013 else if (i.suffix != QWORD_MNEM_SUFFIX
3014 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
3015 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
3016 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3017 || (flag_code == CODE_64BIT
3018 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 3019 {
3020 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3021
29b0f896
AM		 3022 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
3023 prefix = ADDR_PREFIX_OPCODE;
252b5132 3024
29b0f896
AM		 3025 if (!add_prefix (prefix))
3026 return 0;
24eab124 3027 }
252b5132 3028
29b0f896
AM		 3029 /* Set mode64 for an operand. */
3030 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3031 && flag_code == CODE_64BIT
29b0f896 3032 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L		 3033 {
3034 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3035 need rex64. */
3036 if (i.operands != 2
3037 || i.types [0] != (Acc | Reg64)
3038 || i.types [1] != (Acc | Reg64)
3039 || strcmp (i.tm.name, "xchg") != 0)
3040 i.rex |= REX_MODE64;
3041 }
3e73aa7c 3042
29b0f896
AM		 3043 /* Size floating point instruction. */
3044 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 3045 if (i.tm.opcode_modifier & FloatMF)
3046 i.tm.base_opcode ^= 4;
29b0f896 3047 }
7ecd2f8b 3048
29b0f896
AM		 3049 return 1;
3050}
3e73aa7c 3051
29b0f896 3052static int
543613e9 3053check_byte_reg (void)
29b0f896
AM		 3054{
3055 int op;
543613e9 3056
29b0f896
AM		 3057 for (op = i.operands; --op >= 0;)
3058 {
3059 /* If this is an eight bit register, it's OK. If it's the 16 or
3060 32 bit version of an eight bit register, we will just use the
3061 low portion, and that's OK too. */
3062 if (i.types[op] & Reg8)
3063 continue;
3064
3065 /* movzx and movsx should not generate this warning. */
3066 if (intel_syntax
3067 && (i.tm.base_opcode == 0xfb7
3068 || i.tm.base_opcode == 0xfb6
3069 || i.tm.base_opcode == 0x63
3070 || i.tm.base_opcode == 0xfbe
3071 || i.tm.base_opcode == 0xfbf))
3072 continue;
3073
65ec77d2 3074 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3075 {
3076 /* Prohibit these changes in the 64bit mode, since the
3077 lowering is more complicated. */
3078 if (flag_code == CODE_64BIT
3079 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3080 {
0f3f3d8b 3081 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3082 i.op[op].regs->reg_name,
3083 i.suffix);
3084 return 0;
3085 }
3086#if REGISTER_WARNINGS
3087 if (!quiet_warnings
3088 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3089 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3090 (i.op[op].regs + (i.types[op] & Reg16
3091 ? REGNAM_AL - REGNAM_AX
3092 : REGNAM_AL - REGNAM_EAX))->reg_name,
3093 i.op[op].regs->reg_name,
3094 i.suffix);
3095#endif
3096 continue;
3097 }
3098 /* Any other register is bad. */
3099 if (i.types[op] & (Reg | RegMMX | RegXMM
3100 | SReg2 | SReg3
3101 | Control | Debug | Test
3102 | FloatReg | FloatAcc))
3103 {
3104 as_bad (_("`%%%s' not allowed with `%s%c'"),
3105 i.op[op].regs->reg_name,
3106 i.tm.name,
3107 i.suffix);
3108 return 0;
3109 }
3110 }
3111 return 1;
3112}
3113
3114static int
3115check_long_reg ()
3116{
3117 int op;
3118
3119 for (op = i.operands; --op >= 0;)
3120 /* Reject eight bit registers, except where the template requires
3121 them. (eg. movzb) */
3122 if ((i.types[op] & Reg8) != 0
3123 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3124 {
3125 as_bad (_("`%%%s' not allowed with `%s%c'"),
3126 i.op[op].regs->reg_name,
3127 i.tm.name,
3128 i.suffix);
3129 return 0;
3130 }
3131 /* Warn if the e prefix on a general reg is missing. */
3132 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3133 && (i.types[op] & Reg16) != 0
3134 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3135 {
3136 /* Prohibit these changes in the 64bit mode, since the
3137 lowering is more complicated. */
3138 if (flag_code == CODE_64BIT)
252b5132 3139 {
0f3f3d8b 3140 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3141 i.op[op].regs->reg_name,
3142 i.suffix);
3143 return 0;
252b5132 3144 }
29b0f896
AM		 3145#if REGISTER_WARNINGS
3146 else
3147 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3148 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3149 i.op[op].regs->reg_name,
3150 i.suffix);
3151#endif
252b5132 3152 }
29b0f896
AM		 3153 /* Warn if the r prefix on a general reg is missing. */
3154 else if ((i.types[op] & Reg64) != 0
3155 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 3156 {
0f3f3d8b 3157 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3158 i.op[op].regs->reg_name,
3159 i.suffix);
3160 return 0;
3161 }
3162 return 1;
3163}
252b5132 3164
29b0f896
AM		 3165static int
3166check_qword_reg ()
3167{
3168 int op;
252b5132 3169
29b0f896
AM		 3170 for (op = i.operands; --op >= 0; )
3171 /* Reject eight bit registers, except where the template requires
3172 them. (eg. movzb) */
3173 if ((i.types[op] & Reg8) != 0
3174 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3175 {
3176 as_bad (_("`%%%s' not allowed with `%s%c'"),
3177 i.op[op].regs->reg_name,
3178 i.tm.name,
3179 i.suffix);
3180 return 0;
3181 }
3182 /* Warn if the e prefix on a general reg is missing. */
3183 else if (((i.types[op] & Reg16) != 0
3184 || (i.types[op] & Reg32) != 0)
3185 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3186 {
3187 /* Prohibit these changes in the 64bit mode, since the
3188 lowering is more complicated. */
0f3f3d8b 3189 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3190 i.op[op].regs->reg_name,
3191 i.suffix);
3192 return 0;
252b5132 3193 }
29b0f896
AM		 3194 return 1;
3195}
252b5132 3196
29b0f896
AM		 3197static int
3198check_word_reg ()
3199{
3200 int op;
3201 for (op = i.operands; --op >= 0;)
3202 /* Reject eight bit registers, except where the template requires
3203 them. (eg. movzb) */
3204 if ((i.types[op] & Reg8) != 0
3205 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3206 {
3207 as_bad (_("`%%%s' not allowed with `%s%c'"),
3208 i.op[op].regs->reg_name,
3209 i.tm.name,
3210 i.suffix);
3211 return 0;
3212 }
3213 /* Warn if the e prefix on a general reg is present. */
3214 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3215 && (i.types[op] & Reg32) != 0
3216 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 3217 {
29b0f896
AM		 3218 /* Prohibit these changes in the 64bit mode, since the
3219 lowering is more complicated. */
3220 if (flag_code == CODE_64BIT)
252b5132 3221 {
0f3f3d8b 3222 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3223 i.op[op].regs->reg_name,
3224 i.suffix);
3225 return 0;
252b5132 3226 }
29b0f896
AM		 3227 else
3228#if REGISTER_WARNINGS
3229 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3230 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3231 i.op[op].regs->reg_name,
3232 i.suffix);
3233#endif
3234 }
3235 return 1;
3236}
252b5132 3237
29b0f896
AM		 3238static int
3239finalize_imm ()
3240{
3241 unsigned int overlap0, overlap1, overlap2;
3242
3243 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 3244 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 3245 && overlap0 != Imm8 && overlap0 != Imm8S
3246 && overlap0 != Imm16 && overlap0 != Imm32S
3247 && overlap0 != Imm32 && overlap0 != Imm64)
3248 {
3249 if (i.suffix)
3250 {
3251 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3252 ? Imm8 | Imm8S
3253 : (i.suffix == WORD_MNEM_SUFFIX
3254 ? Imm16
3255 : (i.suffix == QWORD_MNEM_SUFFIX
3256 ? Imm64 | Imm32S
3257 : Imm32)));
3258 }
3259 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3260 || overlap0 == (Imm16 | Imm32)
3261 || overlap0 == (Imm16 | Imm32S))
3262 {
3263 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3264 ? Imm16 : Imm32S);
3265 }
3266 if (overlap0 != Imm8 && overlap0 != Imm8S
3267 && overlap0 != Imm16 && overlap0 != Imm32S
3268 && overlap0 != Imm32 && overlap0 != Imm64)
3269 {
3270 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
3271 return 0;
3272 }
3273 }
3274 i.types[0] = overlap0;
3275
3276 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 3277 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 3278 && overlap1 != Imm8 && overlap1 != Imm8S
3279 && overlap1 != Imm16 && overlap1 != Imm32S
3280 && overlap1 != Imm32 && overlap1 != Imm64)
3281 {
3282 if (i.suffix)
3283 {
3284 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3285 ? Imm8 | Imm8S
3286 : (i.suffix == WORD_MNEM_SUFFIX
3287 ? Imm16
3288 : (i.suffix == QWORD_MNEM_SUFFIX
3289 ? Imm64 | Imm32S
3290 : Imm32)));
3291 }
3292 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3293 || overlap1 == (Imm16 | Imm32)
3294 || overlap1 == (Imm16 | Imm32S))
3295 {
3296 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3297 ? Imm16 : Imm32S);
3298 }
3299 if (overlap1 != Imm8 && overlap1 != Imm8S
3300 && overlap1 != Imm16 && overlap1 != Imm32S
3301 && overlap1 != Imm32 && overlap1 != Imm64)
3302 {
3303 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
3304 return 0;
3305 }
3306 }
3307 i.types[1] = overlap1;
3308
3309 overlap2 = i.types[2] & i.tm.operand_types[2];
3310 assert ((overlap2 & Imm) == 0);
3311 i.types[2] = overlap2;
3312
3313 return 1;
3314}
3315
3316static int
3317process_operands ()
3318{
3319 /* Default segment register this instruction will use for memory
3320 accesses. 0 means unknown. This is only for optimizing out
3321 unnecessary segment overrides. */
3322 const seg_entry *default_seg = 0;
3323
3324 /* The imul $imm, %reg instruction is converted into
3325 imul $imm, %reg, %reg, and the clr %reg instruction
3326 is converted into xor %reg, %reg. */
3327 if (i.tm.opcode_modifier & regKludge)
3328 {
3329 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3330 /* Pretend we saw the extra register operand. */
3331 assert (i.op[first_reg_op + 1].regs == 0);
3332 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3333 i.types[first_reg_op + 1] = i.types[first_reg_op];
3334 i.reg_operands = 2;
3335 }
3336
3337 if (i.tm.opcode_modifier & ShortForm)
3338 {
3339 /* The register or float register operand is in operand 0 or 1. */
3340 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3341 /* Register goes in low 3 bits of opcode. */
3342 i.tm.base_opcode |= i.op[op].regs->reg_num;
3343 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3344 i.rex |= REX_EXTZ;
3345 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
3346 {
3347 /* Warn about some common errors, but press on regardless.
3348 The first case can be generated by gcc (<= 2.8.1). */
3349 if (i.operands == 2)
3350 {
3351 /* Reversed arguments on faddp, fsubp, etc. */
3352 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3353 i.op[1].regs->reg_name,
3354 i.op[0].regs->reg_name);
3355 }
3356 else
3357 {
3358 /* Extraneous `l' suffix on fp insn. */
3359 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3360 i.op[0].regs->reg_name);
3361 }
3362 }
3363 }
3364 else if (i.tm.opcode_modifier & Modrm)
3365 {
3366 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3367 must be put into the modrm byte). Now, we make the modrm and
3368 index base bytes based on all the info we've collected. */
29b0f896
AM		 3369
3370 default_seg = build_modrm_byte ();
3371 }
3372 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
3373 {
3374 if (i.tm.base_opcode == POP_SEG_SHORT
3375 && i.op[0].regs->reg_num == 1)
3376 {
3377 as_bad (_("you can't `pop %%cs'"));
3378 return 0;
3379 }
3380 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3381 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3382 i.rex |= REX_EXTZ;
3383 }
3384 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
3385 {
3386 default_seg = &ds;
3387 }
3388 else if ((i.tm.opcode_modifier & IsString) != 0)
3389 {
3390 /* For the string instructions that allow a segment override
3391 on one of their operands, the default segment is ds. */
3392 default_seg = &ds;
3393 }
3394
30123838
JB		 3395 if ((i.tm.base_opcode == 0x8d /* lea */
3396 || (i.tm.cpu_flags & CpuSVME))
3397 && i.seg[0] && !quiet_warnings)
3398 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3399
3400 /* If a segment was explicitly specified, and the specified segment
3401 is not the default, use an opcode prefix to select it. If we
3402 never figured out what the default segment is, then default_seg
3403 will be zero at this point, and the specified segment prefix will
3404 always be used. */
29b0f896
AM		 3405 if ((i.seg[0]) && (i.seg[0] != default_seg))
3406 {
3407 if (!add_prefix (i.seg[0]->seg_prefix))
3408 return 0;
3409 }
3410 return 1;
3411}
3412
3413static const seg_entry *
3414build_modrm_byte ()
3415{
3416 const seg_entry *default_seg = 0;
3417
3418 /* i.reg_operands MUST be the number of real register operands;
3419 implicit registers do not count. */
3420 if (i.reg_operands == 2)
3421 {
3422 unsigned int source, dest;
3423 source = ((i.types[0]
3424 & (Reg | RegMMX | RegXMM
3425 | SReg2 | SReg3
3426 | Control | Debug | Test))
3427 ? 0 : 1);
050dfa73
MM		 3428
3429 /* In 4 operands instructions with 2 immediate operands, the first two are immediate
3430 bytes and hence source operand will be in the next byte after the immediates */
3431 if ((i.operands == 4)&&(i.imm_operands=2)) source++;
29b0f896
AM		 3432 dest = source + 1;
3433
3434 i.rm.mode = 3;
3435 /* One of the register operands will be encoded in the i.tm.reg
3436 field, the other in the combined i.tm.mode and i.tm.regmem
3437 fields. If no form of this instruction supports a memory
3438 destination operand, then we assume the source operand may
3439 sometimes be a memory operand and so we need to store the
3440 destination in the i.rm.reg field. */
3441 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3442 {
3443 i.rm.reg = i.op[dest].regs->reg_num;
3444 i.rm.regmem = i.op[source].regs->reg_num;
3445 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3446 i.rex |= REX_EXTX;
3447 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3448 i.rex |= REX_EXTZ;
3449 }
3450 else
3451 {
3452 i.rm.reg = i.op[source].regs->reg_num;
3453 i.rm.regmem = i.op[dest].regs->reg_num;
3454 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3455 i.rex |= REX_EXTZ;
3456 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3457 i.rex |= REX_EXTX;
3458 }
c4a530c5
JB		 3459 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3460 {
3461 if (!((i.types[0] | i.types[1]) & Control))
3462 abort ();
3463 i.rex &= ~(REX_EXTX | REX_EXTZ);
3464 add_prefix (LOCK_PREFIX_OPCODE);
3465 }
29b0f896
AM		 3466 }
3467 else
3468 { /* If it's not 2 reg operands... */
3469 if (i.mem_operands)
3470 {
3471 unsigned int fake_zero_displacement = 0;
3472 unsigned int op = ((i.types[0] & AnyMem)
3473 ? 0
3474 : (i.types[1] & AnyMem) ? 1 : 2);
3475
3476 default_seg = &ds;
3477
3478 if (i.base_reg == 0)
3479 {
3480 i.rm.mode = 0;
3481 if (!i.disp_operands)
3482 fake_zero_displacement = 1;
3483 if (i.index_reg == 0)
3484 {
3485 /* Operand is just <disp> */
20f0a1fc 3486 if (flag_code == CODE_64BIT)
29b0f896
AM		 3487 {
3488 /* 64bit mode overwrites the 32bit absolute
3489 addressing by RIP relative addressing and
3490 absolute addressing is encoded by one of the
3491 redundant SIB forms. */
3492 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3493 i.sib.base = NO_BASE_REGISTER;
3494 i.sib.index = NO_INDEX_REGISTER;
20f0a1fc
NC		 3495 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
3496 }
3497 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3498 {
3499 i.rm.regmem = NO_BASE_REGISTER_16;
3500 i.types[op] = Disp16;
3501 }
3502 else
3503 {
3504 i.rm.regmem = NO_BASE_REGISTER;
3505 i.types[op] = Disp32;
29b0f896
AM		 3506 }
3507 }
3508 else /* !i.base_reg && i.index_reg */
3509 {
3510 i.sib.index = i.index_reg->reg_num;
3511 i.sib.base = NO_BASE_REGISTER;
3512 i.sib.scale = i.log2_scale_factor;
3513 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3514 i.types[op] &= ~Disp;
3515 if (flag_code != CODE_64BIT)
3516 i.types[op] |= Disp32; /* Must be 32 bit */
3517 else
3518 i.types[op] |= Disp32S;
3519 if ((i.index_reg->reg_flags & RegRex) != 0)
3520 i.rex |= REX_EXTY;
3521 }
3522 }
3523 /* RIP addressing for 64bit mode. */
3524 else if (i.base_reg->reg_type == BaseIndex)
3525 {
3526 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3527 i.types[op] &= ~ Disp;
29b0f896 3528 i.types[op] |= Disp32S;
71903a11 3529 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 3530 if (! i.disp_operands)
3531 fake_zero_displacement = 1;
29b0f896
AM		 3532 }
3533 else if (i.base_reg->reg_type & Reg16)
3534 {
3535 switch (i.base_reg->reg_num)
3536 {
3537 case 3: /* (%bx) */
3538 if (i.index_reg == 0)
3539 i.rm.regmem = 7;
3540 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3541 i.rm.regmem = i.index_reg->reg_num - 6;
3542 break;
3543 case 5: /* (%bp) */
3544 default_seg = &ss;
3545 if (i.index_reg == 0)
3546 {
3547 i.rm.regmem = 6;
3548 if ((i.types[op] & Disp) == 0)
3549 {
3550 /* fake (%bp) into 0(%bp) */
3551 i.types[op] |= Disp8;
252b5132 3552 fake_zero_displacement = 1;
29b0f896
AM		 3553 }
3554 }
3555 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3556 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3557 break;
3558 default: /* (%si) -> 4 or (%di) -> 5 */
3559 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3560 }
3561 i.rm.mode = mode_from_disp_size (i.types[op]);
3562 }
3563 else /* i.base_reg and 32/64 bit mode */
3564 {
3565 if (flag_code == CODE_64BIT
3566 && (i.types[op] & Disp))
20f0a1fc
NC		 3567 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3568
29b0f896
AM		 3569 i.rm.regmem = i.base_reg->reg_num;
3570 if ((i.base_reg->reg_flags & RegRex) != 0)
3571 i.rex |= REX_EXTZ;
3572 i.sib.base = i.base_reg->reg_num;
3573 /* x86-64 ignores REX prefix bit here to avoid decoder
3574 complications. */
3575 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3576 {
3577 default_seg = &ss;
3578 if (i.disp_operands == 0)
3579 {
3580 fake_zero_displacement = 1;
3581 i.types[op] |= Disp8;
3582 }
3583 }
3584 else if (i.base_reg->reg_num == ESP_REG_NUM)
3585 {
3586 default_seg = &ss;
3587 }
3588 i.sib.scale = i.log2_scale_factor;
3589 if (i.index_reg == 0)
3590 {
3591 /* <disp>(%esp) becomes two byte modrm with no index
3592 register. We've already stored the code for esp
3593 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3594 Any base register besides %esp will not use the
3595 extra modrm byte. */
3596 i.sib.index = NO_INDEX_REGISTER;
3597#if !SCALE1_WHEN_NO_INDEX
3598 /* Another case where we force the second modrm byte. */
3599 if (i.log2_scale_factor)
3600 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3601#endif
29b0f896
AM		 3602 }
3603 else
3604 {
3605 i.sib.index = i.index_reg->reg_num;
3606 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3607 if ((i.index_reg->reg_flags & RegRex) != 0)
3608 i.rex |= REX_EXTY;
3609 }
67a4f2b7
AO		 3610
3611 if (i.disp_operands
3612 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3613 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3614 i.rm.mode = 0;
3615 else
3616 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3617 }
252b5132 3618
29b0f896
AM		 3619 if (fake_zero_displacement)
3620 {
3621 /* Fakes a zero displacement assuming that i.types[op]
3622 holds the correct displacement size. */
3623 expressionS *exp;
3624
3625 assert (i.op[op].disps == 0);
3626 exp = &disp_expressions[i.disp_operands++];
3627 i.op[op].disps = exp;
3628 exp->X_op = O_constant;
3629 exp->X_add_number = 0;
3630 exp->X_add_symbol = (symbolS *) 0;
3631 exp->X_op_symbol = (symbolS *) 0;
3632 }
3633 }
252b5132 3634
29b0f896
AM		 3635 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3636 (if any) based on i.tm.extension_opcode. Again, we must be
3637 careful to make sure that segment/control/debug/test/MMX
3638 registers are coded into the i.rm.reg field. */
3639 if (i.reg_operands)
3640 {
3641 unsigned int op =
3642 ((i.types[0]
3643 & (Reg | RegMMX | RegXMM
3644 | SReg2 | SReg3
3645 | Control | Debug | Test))
3646 ? 0
3647 : ((i.types[1]
3648 & (Reg | RegMMX | RegXMM
3649 | SReg2 | SReg3
3650 | Control | Debug | Test))
3651 ? 1
3652 : 2));
3653 /* If there is an extension opcode to put here, the register
3654 number must be put into the regmem field. */
3655 if (i.tm.extension_opcode != None)
3656 {
3657 i.rm.regmem = i.op[op].regs->reg_num;
3658 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3659 i.rex |= REX_EXTZ;
3660 }
3661 else
3662 {
3663 i.rm.reg = i.op[op].regs->reg_num;
3664 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3665 i.rex |= REX_EXTX;
3666 }
252b5132 3667
29b0f896
AM		 3668 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3669 must set it to 3 to indicate this is a register operand
3670 in the regmem field. */
3671 if (!i.mem_operands)
3672 i.rm.mode = 3;
3673 }
252b5132 3674
29b0f896
AM		 3675 /* Fill in i.rm.reg field with extension opcode (if any). */
3676 if (i.tm.extension_opcode != None)
3677 i.rm.reg = i.tm.extension_opcode;
3678 }
3679 return default_seg;
3680}
252b5132 3681
29b0f896
AM		 3682static void
3683output_branch ()
3684{
3685 char *p;
3686 int code16;
3687 int prefix;
3688 relax_substateT subtype;
3689 symbolS *sym;
3690 offsetT off;
3691
3692 code16 = 0;
3693 if (flag_code == CODE_16BIT)
3694 code16 = CODE16;
3695
3696 prefix = 0;
3697 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3698 {
29b0f896
AM		 3699 prefix = 1;
3700 i.prefixes -= 1;
3701 code16 ^= CODE16;
252b5132 3702 }
29b0f896
AM		 3703 /* Pentium4 branch hints. */
3704 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3705 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3706 {
29b0f896
AM		 3707 prefix++;
3708 i.prefixes--;
3709 }
3710 if (i.prefix[REX_PREFIX] != 0)
3711 {
3712 prefix++;
3713 i.prefixes--;
2f66722d
AM		 3714 }
3715
29b0f896
AM		 3716 if (i.prefixes != 0 && !intel_syntax)
3717 as_warn (_("skipping prefixes on this instruction"));
3718
3719 /* It's always a symbol; End frag & setup for relax.
3720 Make sure there is enough room in this frag for the largest
3721 instruction we may generate in md_convert_frag. This is 2
3722 bytes for the opcode and room for the prefix and largest
3723 displacement. */
3724 frag_grow (prefix + 2 + 4);
3725 /* Prefix and 1 opcode byte go in fr_fix. */
3726 p = frag_more (prefix + 1);
3727 if (i.prefix[DATA_PREFIX] != 0)
3728 *p++ = DATA_PREFIX_OPCODE;
3729 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3730 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3731 *p++ = i.prefix[SEG_PREFIX];
3732 if (i.prefix[REX_PREFIX] != 0)
3733 *p++ = i.prefix[REX_PREFIX];
3734 *p = i.tm.base_opcode;
3735
3736 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3737 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3738 else if ((cpu_arch_flags & Cpu386) != 0)
3739 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3740 else
3741 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3742 subtype |= code16;
3e73aa7c 3743
29b0f896
AM		 3744 sym = i.op[0].disps->X_add_symbol;
3745 off = i.op[0].disps->X_add_number;
3e73aa7c 3746
29b0f896
AM		 3747 if (i.op[0].disps->X_op != O_constant
3748 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3749 {
29b0f896
AM		 3750 /* Handle complex expressions. */
3751 sym = make_expr_symbol (i.op[0].disps);
3752 off = 0;
3753 }
3e73aa7c 3754
29b0f896
AM		 3755 /* 1 possible extra opcode + 4 byte displacement go in var part.
3756 Pass reloc in fr_var. */
3757 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3758}
3e73aa7c 3759
29b0f896
AM		 3760static void
3761output_jump ()
3762{
3763 char *p;
3764 int size;
3e02c1cc 3765 fixS *fixP;
29b0f896
AM		 3766
3767 if (i.tm.opcode_modifier & JumpByte)
3768 {
3769 /* This is a loop or jecxz type instruction. */
3770 size = 1;
3771 if (i.prefix[ADDR_PREFIX] != 0)
3772 {
3773 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3774 i.prefixes -= 1;
3775 }
3776 /* Pentium4 branch hints. */
3777 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3778 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3779 {
3780 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3781 i.prefixes--;
3e73aa7c
JH		 3782 }
3783 }
29b0f896
AM		 3784 else
3785 {
3786 int code16;
3e73aa7c 3787
29b0f896
AM		 3788 code16 = 0;
3789 if (flag_code == CODE_16BIT)
3790 code16 = CODE16;
3e73aa7c 3791
29b0f896
AM		 3792 if (i.prefix[DATA_PREFIX] != 0)
3793 {
3794 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3795 i.prefixes -= 1;
3796 code16 ^= CODE16;
3797 }
252b5132 3798
29b0f896
AM		 3799 size = 4;
3800 if (code16)
3801 size = 2;
3802 }
9fcc94b6 3803
29b0f896
AM		 3804 if (i.prefix[REX_PREFIX] != 0)
3805 {
3806 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3807 i.prefixes -= 1;
3808 }
252b5132 3809
29b0f896
AM		 3810 if (i.prefixes != 0 && !intel_syntax)
3811 as_warn (_("skipping prefixes on this instruction"));
e0890092 3812
29b0f896
AM		 3813 p = frag_more (1 + size);
3814 *p++ = i.tm.base_opcode;
e0890092 3815
3e02c1cc
AM		 3816 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3817 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3818
3819 /* All jumps handled here are signed, but don't use a signed limit
3820 check for 32 and 16 bit jumps as we want to allow wrap around at
3821 4G and 64k respectively. */
3822 if (size == 1)
3823 fixP->fx_signed = 1;
29b0f896 3824}
e0890092 3825
29b0f896
AM		 3826static void
3827output_interseg_jump ()
3828{
3829 char *p;
3830 int size;
3831 int prefix;
3832 int code16;
252b5132 3833
29b0f896
AM		 3834 code16 = 0;
3835 if (flag_code == CODE_16BIT)
3836 code16 = CODE16;
a217f122 3837
29b0f896
AM		 3838 prefix = 0;
3839 if (i.prefix[DATA_PREFIX] != 0)
3840 {
3841 prefix = 1;
3842 i.prefixes -= 1;
3843 code16 ^= CODE16;
3844 }
3845 if (i.prefix[REX_PREFIX] != 0)
3846 {
3847 prefix++;
3848 i.prefixes -= 1;
3849 }
252b5132 3850
29b0f896
AM		 3851 size = 4;
3852 if (code16)
3853 size = 2;
252b5132 3854
29b0f896
AM		 3855 if (i.prefixes != 0 && !intel_syntax)
3856 as_warn (_("skipping prefixes on this instruction"));
252b5132 3857
29b0f896
AM		 3858 /* 1 opcode; 2 segment; offset */
3859 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3860
29b0f896
AM		 3861 if (i.prefix[DATA_PREFIX] != 0)
3862 *p++ = DATA_PREFIX_OPCODE;
252b5132 3863
29b0f896
AM		 3864 if (i.prefix[REX_PREFIX] != 0)
3865 *p++ = i.prefix[REX_PREFIX];
252b5132 3866
29b0f896
AM		 3867 *p++ = i.tm.base_opcode;
3868 if (i.op[1].imms->X_op == O_constant)
3869 {
3870 offsetT n = i.op[1].imms->X_add_number;
252b5132 3871
29b0f896
AM		 3872 if (size == 2
3873 && !fits_in_unsigned_word (n)
3874 && !fits_in_signed_word (n))
3875 {
3876 as_bad (_("16-bit jump out of range"));
3877 return;
3878 }
3879 md_number_to_chars (p, n, size);
3880 }
3881 else
3882 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3883 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3884 if (i.op[0].imms->X_op != O_constant)
3885 as_bad (_("can't handle non absolute segment in `%s'"),
3886 i.tm.name);
3887 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3888}
a217f122 3889
29b0f896
AM		 3890static void
3891output_insn ()
3892{
2bbd9c25
JJ		 3893 fragS *insn_start_frag;
3894 offsetT insn_start_off;
3895
29b0f896
AM		 3896 /* Tie dwarf2 debug info to the address at the start of the insn.
3897 We can't do this after the insn has been output as the current
3898 frag may have been closed off. eg. by frag_var. */
3899 dwarf2_emit_insn (0);
3900
2bbd9c25
JJ		 3901 insn_start_frag = frag_now;
3902 insn_start_off = frag_now_fix ();
3903
29b0f896
AM		 3904 /* Output jumps. */
3905 if (i.tm.opcode_modifier & Jump)
3906 output_branch ();
3907 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3908 output_jump ();
3909 else if (i.tm.opcode_modifier & JumpInterSegment)
3910 output_interseg_jump ();
3911 else
3912 {
3913 /* Output normal instructions here. */
3914 char *p;
3915 unsigned char *q;
331d2d0d 3916 unsigned int prefix;
252b5132 3917
ef05d495
L		 3918 /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
3919 Streaming SIMD extensions 3 Instructions have 3 bytes. We may
3920 use one more higher byte to specify a prefix the instruction
3921 requires. */
3922 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
bc4bd9ab 3923 {
331d2d0d
L		 3924 if (i.tm.base_opcode & 0xff000000)
3925 {
3926 prefix = (i.tm.base_opcode >> 24) & 0xff;
3927 goto check_prefix;
3928 }
3929 }
3930 else if ((i.tm.base_opcode & 0xff0000) != 0)
3931 {
3932 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 3933 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3934 {
64e74474 3935 check_prefix:
bc4bd9ab
MK		 3936 if (prefix != REPE_PREFIX_OPCODE
3937 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3938 add_prefix (prefix);
3939 }
3940 else
331d2d0d 3941 add_prefix (prefix);
0f10071e 3942 }
252b5132 3943
29b0f896
AM		 3944 /* The prefix bytes. */
3945 for (q = i.prefix;
3946 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3947 q++)
3948 {
3949 if (*q)
3950 {
3951 p = frag_more (1);
3952 md_number_to_chars (p, (valueT) *q, 1);
3953 }
3954 }
252b5132 3955
29b0f896
AM		 3956 /* Now the opcode; be careful about word order here! */
3957 if (fits_in_unsigned_byte (i.tm.base_opcode))
3958 {
3959 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3960 }
3961 else
3962 {
ef05d495 3963 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
331d2d0d
L		 3964 {
3965 p = frag_more (3);
3966 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3967 }
3968 else
3969 p = frag_more (2);
0f10071e 3970
29b0f896
AM		 3971 /* Put out high byte first: can't use md_number_to_chars! */
3972 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3973 *p = i.tm.base_opcode & 0xff;
3974 }
3e73aa7c 3975
29b0f896
AM		 3976 /* Now the modrm byte and sib byte (if present). */
3977 if (i.tm.opcode_modifier & Modrm)
3978 {
3979 p = frag_more (1);
3980 md_number_to_chars (p,
3981 (valueT) (i.rm.regmem << 0
3982 | i.rm.reg << 3
3983 | i.rm.mode << 6),
3984 1);
3985 /* If i.rm.regmem == ESP (4)
3986 && i.rm.mode != (Register mode)
3987 && not 16 bit
3988 ==> need second modrm byte. */
3989 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3990 && i.rm.mode != 3
3991 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3992 {
3993 p = frag_more (1);
3994 md_number_to_chars (p,
3995 (valueT) (i.sib.base << 0
3996 | i.sib.index << 3
3997 | i.sib.scale << 6),
3998 1);
3999 }
4000 }
3e73aa7c 4001
29b0f896 4002 if (i.disp_operands)
2bbd9c25 4003 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 4004
29b0f896 4005 if (i.imm_operands)
2bbd9c25 4006 output_imm (insn_start_frag, insn_start_off);
29b0f896 4007 }
252b5132 4008
29b0f896
AM		 4009#ifdef DEBUG386
4010 if (flag_debug)
4011 {
7b81dfbb 4012 pi ("" /*line*/, &i);
29b0f896
AM		 4013 }
4014#endif /* DEBUG386 */
4015}
252b5132 4016
29b0f896 4017static void
64e74474 4018output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4019{
4020 char *p;
4021 unsigned int n;
252b5132 4022
29b0f896
AM		 4023 for (n = 0; n < i.operands; n++)
4024 {
4025 if (i.types[n] & Disp)
4026 {
4027 if (i.op[n].disps->X_op == O_constant)
4028 {
4029 int size;
4030 offsetT val;
252b5132 4031
29b0f896
AM		 4032 size = 4;
4033 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4034 {
4035 size = 2;
4036 if (i.types[n] & Disp8)
4037 size = 1;
4038 if (i.types[n] & Disp64)
4039 size = 8;
4040 }
4041 val = offset_in_range (i.op[n].disps->X_add_number,
4042 size);
4043 p = frag_more (size);
4044 md_number_to_chars (p, val, size);
4045 }
4046 else
4047 {
f86103b7 4048 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4049 int size = 4;
4050 int sign = 0;
4051 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4052
4053 /* The PC relative address is computed relative
4054 to the instruction boundary, so in case immediate
4055 fields follows, we need to adjust the value. */
4056 if (pcrel && i.imm_operands)
4057 {
4058 int imm_size = 4;
4059 unsigned int n1;
252b5132 4060
29b0f896
AM		 4061 for (n1 = 0; n1 < i.operands; n1++)
4062 if (i.types[n1] & Imm)
252b5132 4063 {
29b0f896 4064 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 4065 {
29b0f896
AM		 4066 imm_size = 2;
4067 if (i.types[n1] & (Imm8 | Imm8S))
4068 imm_size = 1;
4069 if (i.types[n1] & Imm64)
4070 imm_size = 8;
252b5132 4071 }
29b0f896 4072 break;
252b5132 4073 }
29b0f896
AM		 4074 /* We should find the immediate. */
4075 if (n1 == i.operands)
4076 abort ();
4077 i.op[n].disps->X_add_number -= imm_size;
4078 }
520dc8e8 4079
29b0f896
AM		 4080 if (i.types[n] & Disp32S)
4081 sign = 1;
3e73aa7c 4082
29b0f896
AM		 4083 if (i.types[n] & (Disp16 | Disp64))
4084 {
4085 size = 2;
4086 if (i.types[n] & Disp64)
4087 size = 8;
4088 }
520dc8e8 4089
29b0f896 4090 p = frag_more (size);
2bbd9c25 4091 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4092 if (GOT_symbol
2bbd9c25 4093 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4094 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4095 || reloc_type == BFD_RELOC_X86_64_32S
4096 || (reloc_type == BFD_RELOC_64
4097 && object_64bit))
d6ab8113
JB		 4098 && (i.op[n].disps->X_op == O_symbol
4099 || (i.op[n].disps->X_op == O_add
4100 && ((symbol_get_value_expression
4101 (i.op[n].disps->X_op_symbol)->X_op)
4102 == O_subtract))))
4103 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4104 {
4105 offsetT add;
4106
4107 if (insn_start_frag == frag_now)
4108 add = (p - frag_now->fr_literal) - insn_start_off;
4109 else
4110 {
4111 fragS *fr;
4112
4113 add = insn_start_frag->fr_fix - insn_start_off;
4114 for (fr = insn_start_frag->fr_next;
4115 fr && fr != frag_now; fr = fr->fr_next)
4116 add += fr->fr_fix;
4117 add += p - frag_now->fr_literal;
4118 }
4119
4fa24527 4120 if (!object_64bit)
7b81dfbb
AJ		 4121 {
4122 reloc_type = BFD_RELOC_386_GOTPC;
4123 i.op[n].imms->X_add_number += add;
4124 }
4125 else if (reloc_type == BFD_RELOC_64)
4126 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4127 else
7b81dfbb
AJ		 4128 /* Don't do the adjustment for x86-64, as there
4129 the pcrel addressing is relative to the _next_
4130 insn, and that is taken care of in other code. */
d6ab8113 4131 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4132 }
062cd5e7 4133 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4134 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4135 }
4136 }
4137 }
4138}
252b5132 4139
29b0f896 4140static void
64e74474 4141output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4142{
4143 char *p;
4144 unsigned int n;
252b5132 4145
29b0f896
AM		 4146 for (n = 0; n < i.operands; n++)
4147 {
4148 if (i.types[n] & Imm)
4149 {
4150 if (i.op[n].imms->X_op == O_constant)
4151 {
4152 int size;
4153 offsetT val;
b4cac588 4154
29b0f896
AM		 4155 size = 4;
4156 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4157 {
4158 size = 2;
4159 if (i.types[n] & (Imm8 | Imm8S))
4160 size = 1;
4161 else if (i.types[n] & Imm64)
4162 size = 8;
4163 }
4164 val = offset_in_range (i.op[n].imms->X_add_number,
4165 size);
4166 p = frag_more (size);
4167 md_number_to_chars (p, val, size);
4168 }
4169 else
4170 {
4171 /* Not absolute_section.
4172 Need a 32-bit fixup (don't support 8bit
4173 non-absolute imms). Try to support other
4174 sizes ... */
f86103b7 4175 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4176 int size = 4;
4177 int sign = 0;
4178
4179 if ((i.types[n] & (Imm32S))
a7d61044
JB		 4180 && (i.suffix == QWORD_MNEM_SUFFIX
4181 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 4182 sign = 1;
4183 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4184 {
4185 size = 2;
4186 if (i.types[n] & (Imm8 | Imm8S))
4187 size = 1;
4188 if (i.types[n] & Imm64)
4189 size = 8;
4190 }
520dc8e8 4191
29b0f896
AM		 4192 p = frag_more (size);
4193 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4194
2bbd9c25
JJ		 4195 /* This is tough to explain. We end up with this one if we
4196 * have operands that look like
4197 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4198 * obtain the absolute address of the GOT, and it is strongly
4199 * preferable from a performance point of view to avoid using
4200 * a runtime relocation for this. The actual sequence of
4201 * instructions often look something like:
4202 *
4203 * call .L66
4204 * .L66:
4205 * popl %ebx
4206 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4207 *
4208 * The call and pop essentially return the absolute address
4209 * of the label .L66 and store it in %ebx. The linker itself
4210 * will ultimately change the first operand of the addl so
4211 * that %ebx points to the GOT, but to keep things simple, the
4212 * .o file must have this operand set so that it generates not
4213 * the absolute address of .L66, but the absolute address of
4214 * itself. This allows the linker itself simply treat a GOTPC
4215 * relocation as asking for a pcrel offset to the GOT to be
4216 * added in, and the addend of the relocation is stored in the
4217 * operand field for the instruction itself.
4218 *
4219 * Our job here is to fix the operand so that it would add
4220 * the correct offset so that %ebx would point to itself. The
4221 * thing that is tricky is that .-.L66 will point to the
4222 * beginning of the instruction, so we need to further modify
4223 * the operand so that it will point to itself. There are
4224 * other cases where you have something like:
4225 *
4226 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4227 *
4228 * and here no correction would be required. Internally in
4229 * the assembler we treat operands of this form as not being
4230 * pcrel since the '.' is explicitly mentioned, and I wonder
4231 * whether it would simplify matters to do it this way. Who
4232 * knows. In earlier versions of the PIC patches, the
4233 * pcrel_adjust field was used to store the correction, but
4234 * since the expression is not pcrel, I felt it would be
4235 * confusing to do it this way. */
4236
d6ab8113 4237 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4238 || reloc_type == BFD_RELOC_X86_64_32S
4239 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4240 && GOT_symbol
4241 && GOT_symbol == i.op[n].imms->X_add_symbol
4242 && (i.op[n].imms->X_op == O_symbol
4243 || (i.op[n].imms->X_op == O_add
4244 && ((symbol_get_value_expression
4245 (i.op[n].imms->X_op_symbol)->X_op)
4246 == O_subtract))))
4247 {
2bbd9c25
JJ		 4248 offsetT add;
4249
4250 if (insn_start_frag == frag_now)
4251 add = (p - frag_now->fr_literal) - insn_start_off;
4252 else
4253 {
4254 fragS *fr;
4255
4256 add = insn_start_frag->fr_fix - insn_start_off;
4257 for (fr = insn_start_frag->fr_next;
4258 fr && fr != frag_now; fr = fr->fr_next)
4259 add += fr->fr_fix;
4260 add += p - frag_now->fr_literal;
4261 }
4262
4fa24527 4263 if (!object_64bit)
d6ab8113 4264 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4265 else if (size == 4)
d6ab8113 4266 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4267 else if (size == 8)
4268 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4269 i.op[n].imms->X_add_number += add;
29b0f896 4270 }
29b0f896
AM		 4271 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4272 i.op[n].imms, 0, reloc_type);
4273 }
4274 }
4275 }
252b5132
RH		 4276}
4277\f
d182319b
JB		 4278/* x86_cons_fix_new is called via the expression parsing code when a
4279 reloc is needed. We use this hook to get the correct .got reloc. */
4280static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4281static int cons_sign = -1;
4282
4283void
4284x86_cons_fix_new (fragS *frag,
64e74474
AM		 4285 unsigned int off,
4286 unsigned int len,
4287 expressionS *exp)
d182319b
JB		 4288{
4289 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4290
4291 got_reloc = NO_RELOC;
4292
4293#ifdef TE_PE
4294 if (exp->X_op == O_secrel)
4295 {
4296 exp->X_op = O_symbol;
4297 r = BFD_RELOC_32_SECREL;
4298 }
4299#endif
4300
4301 fix_new_exp (frag, off, len, exp, 0, r);
4302}
4303
718ddfc0
JB		 4304#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4305# define lex_got(reloc, adjust, types) NULL
4306#else
f3c180ae
AM		 4307/* Parse operands of the form
4308 <symbol>@GOTOFF+<nnn>
4309 and similar .plt or .got references.
4310
4311 If we find one, set up the correct relocation in RELOC and copy the
4312 input string, minus the `@GOTOFF' into a malloc'd buffer for
4313 parsing by the calling routine. Return this buffer, and if ADJUST
4314 is non-null set it to the length of the string we removed from the
4315 input line. Otherwise return NULL. */
4316static char *
3956db08 4317lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 4318 int *adjust,
4319 unsigned int *types)
f3c180ae 4320{
7b81dfbb
AJ		 4321 /* Some of the relocations depend on the size of what field is to
4322 be relocated. But in our callers i386_immediate and i386_displacement
4323 we don't yet know the operand size (this will be set by insn
4324 matching). Hence we record the word32 relocation here,
4325 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4326 static const struct {
4327 const char *str;
4fa24527 4328 const enum bfd_reloc_code_real rel[2];
3956db08 4329 const unsigned int types64;
f3c180ae 4330 } gotrel[] = {
7b81dfbb 4331 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
4fa24527 4332 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
7b81dfbb 4333 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
4fa24527
JB		 4334 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
4335 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
4336 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
4337 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
4338 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
4339 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
4340 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4341 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
4342 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4343 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
4344 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
7b81dfbb 4345 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 },
67a4f2b7
AO		 4346 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
4347 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 4348 };
4349 char *cp;
4350 unsigned int j;
4351
718ddfc0
JB		 4352 if (!IS_ELF)
4353 return NULL;
4354
f3c180ae
AM		 4355 for (cp = input_line_pointer; *cp != '@'; cp++)
4356 if (is_end_of_line[(unsigned char) *cp])
4357 return NULL;
4358
4359 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4360 {
4361 int len;
4362
4363 len = strlen (gotrel[j].str);
28f81592 4364 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4365 {
4fa24527 4366 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4367 {
28f81592
AM		 4368 int first, second;
4369 char *tmpbuf, *past_reloc;
f3c180ae 4370
4fa24527 4371 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 4372 if (adjust)
4373 *adjust = len;
f3c180ae 4374
3956db08
JB		 4375 if (types)
4376 {
4377 if (flag_code != CODE_64BIT)
4378 *types = Imm32|Disp32;
4379 else
4380 *types = gotrel[j].types64;
4381 }
4382
f3c180ae
AM		 4383 if (GOT_symbol == NULL)
4384 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4385
4386 /* Replace the relocation token with ' ', so that
4387 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 4388
4389 /* The length of the first part of our input line. */
f3c180ae 4390 first = cp - input_line_pointer;
28f81592
AM		 4391
4392 /* The second part goes from after the reloc token until
4393 (and including) an end_of_line char. Don't use strlen
4394 here as the end_of_line char may not be a NUL. */
4395 past_reloc = cp + 1 + len;
4396 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4397 ;
4398 second = cp - past_reloc;
4399
4400 /* Allocate and copy string. The trailing NUL shouldn't
4401 be necessary, but be safe. */
4402 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 4403 memcpy (tmpbuf, input_line_pointer, first);
4404 tmpbuf[first] = ' ';
28f81592
AM		 4405 memcpy (tmpbuf + first + 1, past_reloc, second);
4406 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 4407 return tmpbuf;
4408 }
4409
4fa24527
JB		 4410 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4411 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 4412 return NULL;
4413 }
4414 }
4415
4416 /* Might be a symbol version string. Don't as_bad here. */
4417 return NULL;
4418}
4419
f3c180ae
AM		 4420void
4421x86_cons (exp, size)
4422 expressionS *exp;
4423 int size;
4424{
4fa24527 4425 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 4426 {
4427 /* Handle @GOTOFF and the like in an expression. */
4428 char *save;
4429 char *gotfree_input_line;
4430 int adjust;
4431
4432 save = input_line_pointer;
3956db08 4433 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4434 if (gotfree_input_line)
4435 input_line_pointer = gotfree_input_line;
4436
4437 expression (exp);
4438
4439 if (gotfree_input_line)
4440 {
4441 /* expression () has merrily parsed up to the end of line,
4442 or a comma - in the wrong buffer. Transfer how far
4443 input_line_pointer has moved to the right buffer. */
4444 input_line_pointer = (save
4445 + (input_line_pointer - gotfree_input_line)
4446 + adjust);
4447 free (gotfree_input_line);
4448 }
4449 }
4450 else
4451 expression (exp);
4452}
4453#endif
4454
d182319b 4455static void signed_cons (int size)
6482c264 4456{
d182319b
JB		 4457 if (flag_code == CODE_64BIT)
4458 cons_sign = 1;
4459 cons (size);
4460 cons_sign = -1;
6482c264
NC		 4461}
4462
d182319b 4463#ifdef TE_PE
6482c264
NC		 4464static void
4465pe_directive_secrel (dummy)
4466 int dummy ATTRIBUTE_UNUSED;
4467{
4468 expressionS exp;
4469
4470 do
4471 {
4472 expression (&exp);
4473 if (exp.X_op == O_symbol)
4474 exp.X_op = O_secrel;
4475
4476 emit_expr (&exp, 4);
4477 }
4478 while (*input_line_pointer++ == ',');
4479
4480 input_line_pointer--;
4481 demand_empty_rest_of_line ();
4482}
6482c264
NC		 4483#endif
4484
252b5132
RH		 4485static int i386_immediate PARAMS ((char *));
4486
4487static int
4488i386_immediate (imm_start)
4489 char *imm_start;
4490{
4491 char *save_input_line_pointer;
f3c180ae 4492 char *gotfree_input_line;
252b5132 4493 segT exp_seg = 0;
47926f60 4494 expressionS *exp;
3956db08 4495 unsigned int types = ~0U;
252b5132
RH		 4496
4497 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4498 {
d0b47220 4499 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 4500 return 0;
4501 }
4502
4503 exp = &im_expressions[i.imm_operands++];
520dc8e8 4504 i.op[this_operand].imms = exp;
252b5132
RH		 4505
4506 if (is_space_char (*imm_start))
4507 ++imm_start;
4508
4509 save_input_line_pointer = input_line_pointer;
4510 input_line_pointer = imm_start;
4511
3956db08 4512 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4513 if (gotfree_input_line)
4514 input_line_pointer = gotfree_input_line;
252b5132
RH		 4515
4516 exp_seg = expression (exp);
4517
83183c0c 4518 SKIP_WHITESPACE ();
252b5132 4519 if (*input_line_pointer)
f3c180ae 4520 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4521
4522 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4523 if (gotfree_input_line)
4524 free (gotfree_input_line);
252b5132 4525
2daf4fd8 4526 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4527 {
47926f60 4528 /* Missing or bad expr becomes absolute 0. */
d0b47220 4529 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4530 imm_start);
252b5132
RH		 4531 exp->X_op = O_constant;
4532 exp->X_add_number = 0;
4533 exp->X_add_symbol = (symbolS *) 0;
4534 exp->X_op_symbol = (symbolS *) 0;
252b5132 4535 }
3e73aa7c 4536 else if (exp->X_op == O_constant)
252b5132 4537 {
47926f60 4538 /* Size it properly later. */
3e73aa7c
JH		 4539 i.types[this_operand] |= Imm64;
4540 /* If BFD64, sign extend val. */
4541 if (!use_rela_relocations)
4542 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4543 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4544 }
4c63da97 4545#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4546 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4547 && exp_seg != absolute_section
47926f60 4548 && exp_seg != text_section
24eab124
AM		 4549 && exp_seg != data_section
4550 && exp_seg != bss_section
4551 && exp_seg != undefined_section
f86103b7 4552 && !bfd_is_com_section (exp_seg))
252b5132 4553 {
d0b47220 4554 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4555 return 0;
4556 }
4557#endif
bb8f5920
L		 4558 else if (!intel_syntax && exp->X_op == O_register)
4559 {
4560 as_bad (_("illegal immediate register operand %s"), imm_start);
4561 return 0;
4562 }
252b5132
RH		 4563 else
4564 {
4565 /* This is an address. The size of the address will be
24eab124 4566 determined later, depending on destination register,
3e73aa7c
JH		 4567 suffix, or the default for the section. */
4568 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4569 i.types[this_operand] &= types;
252b5132
RH		 4570 }
4571
4572 return 1;
4573}
4574
551c1ca1 4575static char *i386_scale PARAMS ((char *));
252b5132 4576
551c1ca1 4577static char *
252b5132
RH		 4578i386_scale (scale)
4579 char *scale;
4580{
551c1ca1
AM		 4581 offsetT val;
4582 char *save = input_line_pointer;
252b5132 4583
551c1ca1
AM		 4584 input_line_pointer = scale;
4585 val = get_absolute_expression ();
4586
4587 switch (val)
252b5132 4588 {
551c1ca1 4589 case 1:
252b5132
RH		 4590 i.log2_scale_factor = 0;
4591 break;
551c1ca1 4592 case 2:
252b5132
RH		 4593 i.log2_scale_factor = 1;
4594 break;
551c1ca1 4595 case 4:
252b5132
RH		 4596 i.log2_scale_factor = 2;
4597 break;
551c1ca1 4598 case 8:
252b5132
RH		 4599 i.log2_scale_factor = 3;
4600 break;
4601 default:
a724f0f4
JB		 4602 {
4603 char sep = *input_line_pointer;
4604
4605 *input_line_pointer = '\0';
4606 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4607 scale);
4608 *input_line_pointer = sep;
4609 input_line_pointer = save;
4610 return NULL;
4611 }
252b5132 4612 }
29b0f896 4613 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4614 {
4615 as_warn (_("scale factor of %d without an index register"),
24eab124 4616 1 << i.log2_scale_factor);
252b5132
RH		 4617#if SCALE1_WHEN_NO_INDEX
4618 i.log2_scale_factor = 0;
4619#endif
4620 }
551c1ca1
AM		 4621 scale = input_line_pointer;
4622 input_line_pointer = save;
4623 return scale;
252b5132
RH		 4624}
4625
4626static int i386_displacement PARAMS ((char *, char *));
4627
4628static int
4629i386_displacement (disp_start, disp_end)
4630 char *disp_start;
4631 char *disp_end;
4632{
29b0f896 4633 expressionS *exp;
252b5132
RH		 4634 segT exp_seg = 0;
4635 char *save_input_line_pointer;
f3c180ae 4636 char *gotfree_input_line;
e05278af 4637 int bigdisp, override;
3956db08 4638 unsigned int types = Disp;
252b5132 4639
e05278af
JB		 4640 if ((i.types[this_operand] & JumpAbsolute)
4641 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4642 {
4643 bigdisp = Disp32;
4644 override = (i.prefix[ADDR_PREFIX] != 0);
4645 }
4646 else
4647 {
4648 /* For PC-relative branches, the width of the displacement
4649 is dependent upon data size, not address size. */
4650 bigdisp = 0;
4651 override = (i.prefix[DATA_PREFIX] != 0);
4652 }
3e73aa7c 4653 if (flag_code == CODE_64BIT)
7ecd2f8b 4654 {
e05278af 4655 if (!bigdisp)
64e74474
AM		 4656 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4657 ? Disp16
4658 : Disp32S | Disp32);
e05278af 4659 else if (!override)
3956db08 4660 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4661 }
e05278af
JB		 4662 else
4663 {
4664 if (!bigdisp)
4665 {
4666 if (!override)
4667 override = (i.suffix == (flag_code != CODE_16BIT
4668 ? WORD_MNEM_SUFFIX
4669 : LONG_MNEM_SUFFIX));
4670 bigdisp = Disp32;
4671 }
4672 if ((flag_code == CODE_16BIT) ^ override)
4673 bigdisp = Disp16;
4674 }
252b5132
RH		 4675 i.types[this_operand] |= bigdisp;
4676
4677 exp = &disp_expressions[i.disp_operands];
520dc8e8 4678 i.op[this_operand].disps = exp;
252b5132
RH		 4679 i.disp_operands++;
4680 save_input_line_pointer = input_line_pointer;
4681 input_line_pointer = disp_start;
4682 END_STRING_AND_SAVE (disp_end);
4683
4684#ifndef GCC_ASM_O_HACK
4685#define GCC_ASM_O_HACK 0
4686#endif
4687#if GCC_ASM_O_HACK
4688 END_STRING_AND_SAVE (disp_end + 1);
4689 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4690 && displacement_string_end[-1] == '+')
252b5132
RH		 4691 {
4692 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4693 constraint within gcc asm statements.
4694 For instance:
4695
4696 #define _set_tssldt_desc(n,addr,limit,type) \
4697 __asm__ __volatile__ ( \
4698 "movw %w2,%0\n\t" \
4699 "movw %w1,2+%0\n\t" \
4700 "rorl $16,%1\n\t" \
4701 "movb %b1,4+%0\n\t" \
4702 "movb %4,5+%0\n\t" \
4703 "movb $0,6+%0\n\t" \
4704 "movb %h1,7+%0\n\t" \
4705 "rorl $16,%1" \
4706 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4707
4708 This works great except that the output assembler ends
4709 up looking a bit weird if it turns out that there is
4710 no offset. You end up producing code that looks like:
4711
4712 #APP
4713 movw $235,(%eax)
4714 movw %dx,2+(%eax)
4715 rorl $16,%edx
4716 movb %dl,4+(%eax)
4717 movb $137,5+(%eax)
4718 movb $0,6+(%eax)
4719 movb %dh,7+(%eax)
4720 rorl $16,%edx
4721 #NO_APP
4722
47926f60 4723 So here we provide the missing zero. */
24eab124
AM		 4724
4725 *displacement_string_end = '0';
252b5132
RH		 4726 }
4727#endif
3956db08 4728 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4729 if (gotfree_input_line)
4730 input_line_pointer = gotfree_input_line;
252b5132 4731
24eab124 4732 exp_seg = expression (exp);
252b5132 4733
636c26b0
AM		 4734 SKIP_WHITESPACE ();
4735 if (*input_line_pointer)
4736 as_bad (_("junk `%s' after expression"), input_line_pointer);
4737#if GCC_ASM_O_HACK
4738 RESTORE_END_STRING (disp_end + 1);
4739#endif
4740 RESTORE_END_STRING (disp_end);
4741 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4742 if (gotfree_input_line)
4743 free (gotfree_input_line);
636c26b0 4744
24eab124
AM		 4745 /* We do this to make sure that the section symbol is in
4746 the symbol table. We will ultimately change the relocation
47926f60 4747 to be relative to the beginning of the section. */
1ae12ab7 4748 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4749 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4750 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4751 {
636c26b0
AM		 4752 if (exp->X_op != O_symbol)
4753 {
4754 as_bad (_("bad expression used with @%s"),
4755 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4756 ? "GOTPCREL"
4757 : "GOTOFF"));
4758 return 0;
4759 }
4760
e5cb08ac 4761 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4762 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4763 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4764 exp->X_op = O_subtract;
4765 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4766 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4767 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4768 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4769 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4770 else
29b0f896 4771 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4772 }
252b5132 4773
2daf4fd8
AM		 4774 if (exp->X_op == O_absent || exp->X_op == O_big)
4775 {
47926f60 4776 /* Missing or bad expr becomes absolute 0. */
d0b47220 4777 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4778 disp_start);
4779 exp->X_op = O_constant;
4780 exp->X_add_number = 0;
4781 exp->X_add_symbol = (symbolS *) 0;
4782 exp->X_op_symbol = (symbolS *) 0;
4783 }
4784
4c63da97 4785#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4786 if (exp->X_op != O_constant
45288df1 4787 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4788 && exp_seg != absolute_section
45288df1
AM		 4789 && exp_seg != text_section
4790 && exp_seg != data_section
4791 && exp_seg != bss_section
31312f95 4792 && exp_seg != undefined_section
f86103b7 4793 && !bfd_is_com_section (exp_seg))
24eab124 4794 {
d0b47220 4795 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4796 return 0;
4797 }
252b5132 4798#endif
3956db08
JB		 4799
4800 if (!(i.types[this_operand] & ~Disp))
4801 i.types[this_operand] &= types;
4802
252b5132
RH		 4803 return 1;
4804}
4805
e5cb08ac 4806static int i386_index_check PARAMS ((const char *));
252b5132 4807
eecb386c 4808/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4809 Return 1 on success, 0 on a failure. */
4810
252b5132 4811static int
eecb386c
AM		 4812i386_index_check (operand_string)
4813 const char *operand_string;
252b5132 4814{
3e73aa7c 4815 int ok;
24eab124 4816#if INFER_ADDR_PREFIX
eecb386c
AM		 4817 int fudged = 0;
4818
24eab124
AM		 4819 tryprefix:
4820#endif
3e73aa7c 4821 ok = 1;
30123838
JB		 4822 if ((current_templates->start->cpu_flags & CpuSVME)
4823 && current_templates->end[-1].operand_types[0] == AnyMem)
4824 {
4825 /* Memory operands of SVME insns are special in that they only allow
4826 rAX as their memory address and ignore any segment override. */
4827 unsigned RegXX;
4828
4829 /* SKINIT is even more restrictive: it always requires EAX. */
4830 if (strcmp (current_templates->start->name, "skinit") == 0)
4831 RegXX = Reg32;
4832 else if (flag_code == CODE_64BIT)
4833 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4834 else
64e74474
AM		 4835 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4836 ? Reg16
4837 : Reg32);
30123838
JB		 4838 if (!i.base_reg
4839 || !(i.base_reg->reg_type & Acc)
4840 || !(i.base_reg->reg_type & RegXX)
4841 || i.index_reg
4842 || (i.types[0] & Disp))
4843 ok = 0;
4844 }
4845 else if (flag_code == CODE_64BIT)
64e74474
AM		 4846 {
4847 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4848
4849 if ((i.base_reg
4850 && ((i.base_reg->reg_type & RegXX) == 0)
4851 && (i.base_reg->reg_type != BaseIndex
4852 || i.index_reg))
4853 || (i.index_reg
4854 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4855 != (RegXX | BaseIndex))))
4856 ok = 0;
3e73aa7c
JH		 4857 }
4858 else
4859 {
4860 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4861 {
4862 /* 16bit checks. */
4863 if ((i.base_reg
29b0f896
AM		 4864 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4865 != (Reg16 | BaseIndex)))
3e73aa7c 4866 || (i.index_reg
29b0f896
AM		 4867 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4868 != (Reg16 | BaseIndex))
4869 || !(i.base_reg
4870 && i.base_reg->reg_num < 6
4871 && i.index_reg->reg_num >= 6
4872 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4873 ok = 0;
4874 }
4875 else
e5cb08ac 4876 {
3e73aa7c
JH		 4877 /* 32bit checks. */
4878 if ((i.base_reg
4879 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4880 || (i.index_reg
29b0f896
AM		 4881 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4882 != (Reg32 | BaseIndex))))
e5cb08ac 4883 ok = 0;
3e73aa7c
JH		 4884 }
4885 }
4886 if (!ok)
24eab124
AM		 4887 {
4888#if INFER_ADDR_PREFIX
20f0a1fc 4889 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4890 {
4891 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4892 i.prefixes += 1;
b23bac36
AM		 4893 /* Change the size of any displacement too. At most one of
4894 Disp16 or Disp32 is set.
4895 FIXME. There doesn't seem to be any real need for separate
4896 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4897 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4898 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 4899 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4900 fudged = 1;
24eab124
AM		 4901 goto tryprefix;
4902 }
eecb386c
AM		 4903 if (fudged)
4904 as_bad (_("`%s' is not a valid base/index expression"),
4905 operand_string);
4906 else
c388dee8 4907#endif
eecb386c
AM		 4908 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4909 operand_string,
3e73aa7c 4910 flag_code_names[flag_code]);
24eab124 4911 }
20f0a1fc 4912 return ok;
24eab124 4913}
252b5132 4914
252b5132 4915/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4916 on error. */
252b5132 4917
252b5132
RH		 4918static int
4919i386_operand (operand_string)
4920 char *operand_string;
4921{
af6bdddf
AM		 4922 const reg_entry *r;
4923 char *end_op;
24eab124 4924 char *op_string = operand_string;
252b5132 4925
24eab124 4926 if (is_space_char (*op_string))
252b5132
RH		 4927 ++op_string;
4928
24eab124 4929 /* We check for an absolute prefix (differentiating,
47926f60 4930 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4931 if (*op_string == ABSOLUTE_PREFIX)
4932 {
4933 ++op_string;
4934 if (is_space_char (*op_string))
4935 ++op_string;
4936 i.types[this_operand] |= JumpAbsolute;
4937 }
252b5132 4938
47926f60 4939 /* Check if operand is a register. */
4d1bb795 4940 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 4941 {
24eab124
AM		 4942 /* Check for a segment override by searching for ':' after a
4943 segment register. */
4944 op_string = end_op;
4945 if (is_space_char (*op_string))
4946 ++op_string;
4947 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4948 {
4949 switch (r->reg_num)
4950 {
4951 case 0:
4952 i.seg[i.mem_operands] = &es;
4953 break;
4954 case 1:
4955 i.seg[i.mem_operands] = &cs;
4956 break;
4957 case 2:
4958 i.seg[i.mem_operands] = &ss;
4959 break;
4960 case 3:
4961 i.seg[i.mem_operands] = &ds;
4962 break;
4963 case 4:
4964 i.seg[i.mem_operands] = &fs;
4965 break;
4966 case 5:
4967 i.seg[i.mem_operands] = &gs;
4968 break;
4969 }
252b5132 4970
24eab124 4971 /* Skip the ':' and whitespace. */
252b5132
RH		 4972 ++op_string;
4973 if (is_space_char (*op_string))
24eab124 4974 ++op_string;
252b5132 4975
24eab124
AM		 4976 if (!is_digit_char (*op_string)
4977 && !is_identifier_char (*op_string)
4978 && *op_string != '('
4979 && *op_string != ABSOLUTE_PREFIX)
4980 {
4981 as_bad (_("bad memory operand `%s'"), op_string);
4982 return 0;
4983 }
47926f60 4984 /* Handle case of %es:*foo. */
24eab124
AM		 4985 if (*op_string == ABSOLUTE_PREFIX)
4986 {
4987 ++op_string;
4988 if (is_space_char (*op_string))
4989 ++op_string;
4990 i.types[this_operand] |= JumpAbsolute;
4991 }
4992 goto do_memory_reference;
4993 }
4994 if (*op_string)
4995 {
d0b47220 4996 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4997 return 0;
4998 }
4999 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 5000 i.op[this_operand].regs = r;
24eab124
AM		 5001 i.reg_operands++;
5002 }
af6bdddf
AM		 5003 else if (*op_string == REGISTER_PREFIX)
5004 {
5005 as_bad (_("bad register name `%s'"), op_string);
5006 return 0;
5007 }
24eab124 5008 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 5009 {
24eab124
AM		 5010 ++op_string;
5011 if (i.types[this_operand] & JumpAbsolute)
5012 {
d0b47220 5013 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 5014 return 0;
5015 }
5016 if (!i386_immediate (op_string))
5017 return 0;
5018 }
5019 else if (is_digit_char (*op_string)
5020 || is_identifier_char (*op_string)
e5cb08ac 5021 || *op_string == '(')
24eab124 5022 {
47926f60 5023 /* This is a memory reference of some sort. */
af6bdddf 5024 char *base_string;
252b5132 5025
47926f60 5026 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 5027 char *displacement_string_start;
5028 char *displacement_string_end;
252b5132 5029
24eab124 5030 do_memory_reference:
24eab124
AM		 5031 if ((i.mem_operands == 1
5032 && (current_templates->start->opcode_modifier & IsString) == 0)
5033 || i.mem_operands == 2)
5034 {
5035 as_bad (_("too many memory references for `%s'"),
5036 current_templates->start->name);
5037 return 0;
5038 }
252b5132 5039
24eab124
AM		 5040 /* Check for base index form. We detect the base index form by
5041 looking for an ')' at the end of the operand, searching
5042 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5043 after the '('. */
af6bdddf 5044 base_string = op_string + strlen (op_string);
c3332e24 5045
af6bdddf
AM		 5046 --base_string;
5047 if (is_space_char (*base_string))
5048 --base_string;
252b5132 5049
47926f60 5050 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 5051 displacement_string_start = op_string;
5052 displacement_string_end = base_string + 1;
252b5132 5053
24eab124
AM		 5054 if (*base_string == ')')
5055 {
af6bdddf 5056 char *temp_string;
24eab124
AM		 5057 unsigned int parens_balanced = 1;
5058 /* We've already checked that the number of left & right ()'s are
47926f60 5059 equal, so this loop will not be infinite. */
24eab124
AM		 5060 do
5061 {
5062 base_string--;
5063 if (*base_string == ')')
5064 parens_balanced++;
5065 if (*base_string == '(')
5066 parens_balanced--;
5067 }
5068 while (parens_balanced);
c3332e24 5069
af6bdddf 5070 temp_string = base_string;
c3332e24 5071
24eab124 5072 /* Skip past '(' and whitespace. */
252b5132
RH		 5073 ++base_string;
5074 if (is_space_char (*base_string))
24eab124 5075 ++base_string;
252b5132 5076
af6bdddf 5077 if (*base_string == ','
4d1bb795 5078 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 5079 {
af6bdddf 5080 displacement_string_end = temp_string;
252b5132 5081
af6bdddf 5082 i.types[this_operand] |= BaseIndex;
252b5132 5083
af6bdddf 5084 if (i.base_reg)
24eab124 5085 {
24eab124
AM		 5086 base_string = end_op;
5087 if (is_space_char (*base_string))
5088 ++base_string;
af6bdddf
AM		 5089 }
5090
5091 /* There may be an index reg or scale factor here. */
5092 if (*base_string == ',')
5093 {
5094 ++base_string;
5095 if (is_space_char (*base_string))
5096 ++base_string;
5097
4d1bb795 5098 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 5099 {
af6bdddf 5100 base_string = end_op;
24eab124
AM		 5101 if (is_space_char (*base_string))
5102 ++base_string;
af6bdddf
AM		 5103 if (*base_string == ',')
5104 {
5105 ++base_string;
5106 if (is_space_char (*base_string))
5107 ++base_string;
5108 }
e5cb08ac 5109 else if (*base_string != ')')
af6bdddf
AM		 5110 {
5111 as_bad (_("expecting `,' or `)' after index register in `%s'"),
5112 operand_string);
5113 return 0;
5114 }
24eab124 5115 }
af6bdddf 5116 else if (*base_string == REGISTER_PREFIX)
24eab124 5117 {
af6bdddf 5118 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5119 return 0;
5120 }
252b5132 5121
47926f60 5122 /* Check for scale factor. */
551c1ca1 5123 if (*base_string != ')')
af6bdddf 5124 {
551c1ca1
AM		 5125 char *end_scale = i386_scale (base_string);
5126
5127 if (!end_scale)
af6bdddf 5128 return 0;
24eab124 5129
551c1ca1 5130 base_string = end_scale;
af6bdddf
AM		 5131 if (is_space_char (*base_string))
5132 ++base_string;
5133 if (*base_string != ')')
5134 {
5135 as_bad (_("expecting `)' after scale factor in `%s'"),
5136 operand_string);
5137 return 0;
5138 }
5139 }
5140 else if (!i.index_reg)
24eab124 5141 {
af6bdddf
AM		 5142 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
5143 *base_string);
24eab124
AM		 5144 return 0;
5145 }
5146 }
af6bdddf 5147 else if (*base_string != ')')
24eab124 5148 {
af6bdddf
AM		 5149 as_bad (_("expecting `,' or `)' after base register in `%s'"),
5150 operand_string);
24eab124
AM		 5151 return 0;
5152 }
c3332e24 5153 }
af6bdddf 5154 else if (*base_string == REGISTER_PREFIX)
c3332e24 5155 {
af6bdddf 5156 as_bad (_("bad register name `%s'"), base_string);
24eab124 5157 return 0;
c3332e24 5158 }
24eab124
AM		 5159 }
5160
5161 /* If there's an expression beginning the operand, parse it,
5162 assuming displacement_string_start and
5163 displacement_string_end are meaningful. */
5164 if (displacement_string_start != displacement_string_end)
5165 {
5166 if (!i386_displacement (displacement_string_start,
5167 displacement_string_end))
5168 return 0;
5169 }
5170
5171 /* Special case for (%dx) while doing input/output op. */
5172 if (i.base_reg
5173 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5174 && i.index_reg == 0
5175 && i.log2_scale_factor == 0
5176 && i.seg[i.mem_operands] == 0
5177 && (i.types[this_operand] & Disp) == 0)
5178 {
5179 i.types[this_operand] = InOutPortReg;
5180 return 1;
5181 }
5182
eecb386c
AM		 5183 if (i386_index_check (operand_string) == 0)
5184 return 0;
24eab124
AM		 5185 i.mem_operands++;
5186 }
5187 else
ce8a8b2f
AM		 5188 {
5189 /* It's not a memory operand; argh! */
24eab124
AM		 5190 as_bad (_("invalid char %s beginning operand %d `%s'"),
5191 output_invalid (*op_string),
5192 this_operand + 1,
5193 op_string);
5194 return 0;
5195 }
47926f60 5196 return 1; /* Normal return. */
252b5132
RH		 5197}
5198\f
ee7fcc42
AM		 5199/* md_estimate_size_before_relax()
5200
5201 Called just before relax() for rs_machine_dependent frags. The x86
5202 assembler uses these frags to handle variable size jump
5203 instructions.
5204
5205 Any symbol that is now undefined will not become defined.
5206 Return the correct fr_subtype in the frag.
5207 Return the initial "guess for variable size of frag" to caller.
5208 The guess is actually the growth beyond the fixed part. Whatever
5209 we do to grow the fixed or variable part contributes to our
5210 returned value. */
5211
252b5132
RH		 5212int
5213md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5214 fragS *fragP;
5215 segT segment;
252b5132 5216{
252b5132 5217 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5218 check for un-relaxable symbols. On an ELF system, we can't relax
5219 an externally visible symbol, because it may be overridden by a
5220 shared library. */
5221 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5222#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5223 || (IS_ELF
31312f95
AM		 5224 && (S_IS_EXTERNAL (fragP->fr_symbol)
5225 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5226#endif
5227 )
252b5132 5228 {
b98ef147
AM		 5229 /* Symbol is undefined in this segment, or we need to keep a
5230 reloc so that weak symbols can be overridden. */
5231 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5232 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5233 unsigned char *opcode;
5234 int old_fr_fix;
f6af82bd 5235
ee7fcc42
AM		 5236 if (fragP->fr_var != NO_RELOC)
5237 reloc_type = fragP->fr_var;
b98ef147 5238 else if (size == 2)
f6af82bd
AM		 5239 reloc_type = BFD_RELOC_16_PCREL;
5240 else
5241 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5242
ee7fcc42
AM		 5243 old_fr_fix = fragP->fr_fix;
5244 opcode = (unsigned char *) fragP->fr_opcode;
5245
fddf5b5b 5246 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5247 {
fddf5b5b
AM		 5248 case UNCOND_JUMP:
5249 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5250 opcode[0] = 0xe9;
252b5132 5251 fragP->fr_fix += size;
062cd5e7
AS		 5252 fix_new (fragP, old_fr_fix, size,
5253 fragP->fr_symbol,
5254 fragP->fr_offset, 1,
5255 reloc_type);
252b5132
RH		 5256 break;
5257
fddf5b5b 5258 case COND_JUMP86:
412167cb
AM		 5259 if (size == 2
5260 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5261 {
5262 /* Negate the condition, and branch past an
5263 unconditional jump. */
5264 opcode[0] ^= 1;
5265 opcode[1] = 3;
5266 /* Insert an unconditional jump. */
5267 opcode[2] = 0xe9;
5268 /* We added two extra opcode bytes, and have a two byte
5269 offset. */
5270 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5271 fix_new (fragP, old_fr_fix + 2, 2,
5272 fragP->fr_symbol,
5273 fragP->fr_offset, 1,
5274 reloc_type);
fddf5b5b
AM		 5275 break;
5276 }
5277 /* Fall through. */
5278
5279 case COND_JUMP:
412167cb
AM		 5280 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5281 {
3e02c1cc
AM		 5282 fixS *fixP;
5283
412167cb 5284 fragP->fr_fix += 1;
3e02c1cc
AM		 5285 fixP = fix_new (fragP, old_fr_fix, 1,
5286 fragP->fr_symbol,
5287 fragP->fr_offset, 1,
5288 BFD_RELOC_8_PCREL);
5289 fixP->fx_signed = 1;
412167cb
AM		 5290 break;
5291 }
93c2a809 5292
24eab124 5293 /* This changes the byte-displacement jump 0x7N
fddf5b5b 5294 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 5295 opcode[1] = opcode[0] + 0x10;
f6af82bd 5296 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 5297 /* We've added an opcode byte. */
5298 fragP->fr_fix += 1 + size;
062cd5e7
AS		 5299 fix_new (fragP, old_fr_fix + 1, size,
5300 fragP->fr_symbol,
5301 fragP->fr_offset, 1,
5302 reloc_type);
252b5132 5303 break;
fddf5b5b
AM		 5304
5305 default:
5306 BAD_CASE (fragP->fr_subtype);
5307 break;
252b5132
RH		 5308 }
5309 frag_wane (fragP);
ee7fcc42 5310 return fragP->fr_fix - old_fr_fix;
252b5132 5311 }
93c2a809 5312
93c2a809
AM		 5313 /* Guess size depending on current relax state. Initially the relax
5314 state will correspond to a short jump and we return 1, because
5315 the variable part of the frag (the branch offset) is one byte
5316 long. However, we can relax a section more than once and in that
5317 case we must either set fr_subtype back to the unrelaxed state,
5318 or return the value for the appropriate branch. */
5319 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 5320}
5321
47926f60
KH		 5322/* Called after relax() is finished.
5323
5324 In: Address of frag.
5325 fr_type == rs_machine_dependent.
5326 fr_subtype is what the address relaxed to.
5327
5328 Out: Any fixSs and constants are set up.
5329 Caller will turn frag into a ".space 0". */
5330
252b5132
RH		 5331void
5332md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 5333 bfd *abfd ATTRIBUTE_UNUSED;
5334 segT sec ATTRIBUTE_UNUSED;
29b0f896 5335 fragS *fragP;
252b5132 5336{
29b0f896 5337 unsigned char *opcode;
252b5132 5338 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 5339 offsetT target_address;
5340 offsetT opcode_address;
252b5132 5341 unsigned int extension = 0;
847f7ad4 5342 offsetT displacement_from_opcode_start;
252b5132
RH		 5343
5344 opcode = (unsigned char *) fragP->fr_opcode;
5345
47926f60 5346 /* Address we want to reach in file space. */
252b5132 5347 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 5348
47926f60 5349 /* Address opcode resides at in file space. */
252b5132
RH		 5350 opcode_address = fragP->fr_address + fragP->fr_fix;
5351
47926f60 5352 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 5353 displacement_from_opcode_start = target_address - opcode_address;
5354
fddf5b5b 5355 if ((fragP->fr_subtype & BIG) == 0)
252b5132 5356 {
47926f60
KH		 5357 /* Don't have to change opcode. */
5358 extension = 1; /* 1 opcode + 1 displacement */
252b5132 5359 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 5360 }
5361 else
5362 {
5363 if (no_cond_jump_promotion
5364 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
5365 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 5366
fddf5b5b
AM		 5367 switch (fragP->fr_subtype)
5368 {
5369 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5370 extension = 4; /* 1 opcode + 4 displacement */
5371 opcode[0] = 0xe9;
5372 where_to_put_displacement = &opcode[1];
5373 break;
252b5132 5374
fddf5b5b
AM		 5375 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5376 extension = 2; /* 1 opcode + 2 displacement */
5377 opcode[0] = 0xe9;
5378 where_to_put_displacement = &opcode[1];
5379 break;
252b5132 5380
fddf5b5b
AM		 5381 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5382 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5383 extension = 5; /* 2 opcode + 4 displacement */
5384 opcode[1] = opcode[0] + 0x10;
5385 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5386 where_to_put_displacement = &opcode[2];
5387 break;
252b5132 5388
fddf5b5b
AM		 5389 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5390 extension = 3; /* 2 opcode + 2 displacement */
5391 opcode[1] = opcode[0] + 0x10;
5392 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5393 where_to_put_displacement = &opcode[2];
5394 break;
252b5132 5395
fddf5b5b
AM		 5396 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5397 extension = 4;
5398 opcode[0] ^= 1;
5399 opcode[1] = 3;
5400 opcode[2] = 0xe9;
5401 where_to_put_displacement = &opcode[3];
5402 break;
5403
5404 default:
5405 BAD_CASE (fragP->fr_subtype);
5406 break;
5407 }
252b5132 5408 }
fddf5b5b 5409
7b81dfbb
AJ		 5410 /* If size if less then four we are sure that the operand fits,
5411 but if it's 4, then it could be that the displacement is larger
5412 then -/+ 2GB. */
5413 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5414 && object_64bit
5415 && ((addressT) (displacement_from_opcode_start - extension
5416 + ((addressT) 1 << 31))
5417 > (((addressT) 2 << 31) - 1)))
5418 {
5419 as_bad_where (fragP->fr_file, fragP->fr_line,
5420 _("jump target out of range"));
5421 /* Make us emit 0. */
5422 displacement_from_opcode_start = extension;
5423 }
47926f60 5424 /* Now put displacement after opcode. */
252b5132
RH		 5425 md_number_to_chars ((char *) where_to_put_displacement,
5426 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5427 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5428 fragP->fr_fix += extension;
5429}
5430\f
47926f60
KH		 5431/* Size of byte displacement jmp. */
5432int md_short_jump_size = 2;
5433
5434/* Size of dword displacement jmp. */
5435int md_long_jump_size = 5;
252b5132 5436
252b5132
RH		 5437void
5438md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5439 char *ptr;
5440 addressT from_addr, to_addr;
ab9da554
ILT		 5441 fragS *frag ATTRIBUTE_UNUSED;
5442 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5443{
847f7ad4 5444 offsetT offset;
252b5132
RH		 5445
5446 offset = to_addr - (from_addr + 2);
47926f60
KH		 5447 /* Opcode for byte-disp jump. */
5448 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5449 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5450}
5451
5452void
5453md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5454 char *ptr;
5455 addressT from_addr, to_addr;
a38cf1db
AM		 5456 fragS *frag ATTRIBUTE_UNUSED;
5457 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5458{
847f7ad4 5459 offsetT offset;
252b5132 5460
a38cf1db
AM		 5461 offset = to_addr - (from_addr + 5);
5462 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5463 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5464}
5465\f
5466/* Apply a fixup (fixS) to segment data, once it has been determined
5467 by our caller that we have all the info we need to fix it up.
5468
5469 On the 386, immediates, displacements, and data pointers are all in
5470 the same (little-endian) format, so we don't need to care about which
5471 we are handling. */
5472
94f592af 5473void
55cf6793 5474md_apply_fix (fixP, valP, seg)
47926f60
KH		 5475 /* The fix we're to put in. */
5476 fixS *fixP;
47926f60 5477 /* Pointer to the value of the bits. */
c6682705 5478 valueT *valP;
47926f60
KH		 5479 /* Segment fix is from. */
5480 segT seg ATTRIBUTE_UNUSED;
252b5132 5481{
94f592af 5482 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5483 valueT value = *valP;
252b5132 5484
f86103b7 5485#if !defined (TE_Mach)
93382f6d
AM		 5486 if (fixP->fx_pcrel)
5487 {
5488 switch (fixP->fx_r_type)
5489 {
5865bb77
ILT		 5490 default:
5491 break;
5492
d6ab8113
JB		 5493 case BFD_RELOC_64:
5494 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5495 break;
93382f6d 5496 case BFD_RELOC_32:
ae8887b5 5497 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5498 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5499 break;
5500 case BFD_RELOC_16:
5501 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5502 break;
5503 case BFD_RELOC_8:
5504 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5505 break;
5506 }
5507 }
252b5132 5508
a161fe53 5509 if (fixP->fx_addsy != NULL
31312f95 5510 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5511 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5512 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5513 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5514 && !use_rela_relocations)
252b5132 5515 {
31312f95
AM		 5516 /* This is a hack. There should be a better way to handle this.
5517 This covers for the fact that bfd_install_relocation will
5518 subtract the current location (for partial_inplace, PC relative
5519 relocations); see more below. */
252b5132 5520#ifndef OBJ_AOUT
718ddfc0 5521 if (IS_ELF
252b5132
RH		 5522#ifdef TE_PE
5523 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5524#endif
5525 )
5526 value += fixP->fx_where + fixP->fx_frag->fr_address;
5527#endif
5528#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5529 if (IS_ELF)
252b5132 5530 {
6539b54b 5531 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5532
6539b54b 5533 if ((sym_seg == seg
2f66722d 5534 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5535 && sym_seg != absolute_section))
ae6063d4 5536 && !generic_force_reloc (fixP))
2f66722d
AM		 5537 {
5538 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5539 bfd_install_relocation subtracts them out again. I think
5540 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5541 it. FIXME. */
5542 value += fixP->fx_where + fixP->fx_frag->fr_address;
5543 }
252b5132
RH		 5544 }
5545#endif
5546#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5547 /* For some reason, the PE format does not store a
5548 section address offset for a PC relative symbol. */
5549 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5550 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5551 value += md_pcrel_from (fixP);
5552#endif
5553 }
5554
5555 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5556 and we must not disappoint it. */
252b5132 5557#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5558 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5559 switch (fixP->fx_r_type)
5560 {
5561 case BFD_RELOC_386_PLT32:
3e73aa7c 5562 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5563 /* Make the jump instruction point to the address of the operand. At
5564 runtime we merely add the offset to the actual PLT entry. */
5565 value = -4;
5566 break;
31312f95 5567
13ae64f3
JJ		 5568 case BFD_RELOC_386_TLS_GD:
5569 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5570 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5571 case BFD_RELOC_386_TLS_IE:
5572 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5573 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5574 case BFD_RELOC_X86_64_TLSGD:
5575 case BFD_RELOC_X86_64_TLSLD:
5576 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5577 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5578 value = 0; /* Fully resolved at runtime. No addend. */
5579 /* Fallthrough */
5580 case BFD_RELOC_386_TLS_LE:
5581 case BFD_RELOC_386_TLS_LDO_32:
5582 case BFD_RELOC_386_TLS_LE_32:
5583 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5584 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5585 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5586 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5587 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5588 break;
5589
67a4f2b7
AO		 5590 case BFD_RELOC_386_TLS_DESC_CALL:
5591 case BFD_RELOC_X86_64_TLSDESC_CALL:
5592 value = 0; /* Fully resolved at runtime. No addend. */
5593 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5594 fixP->fx_done = 0;
5595 return;
5596
00f7efb6
JJ		 5597 case BFD_RELOC_386_GOT32:
5598 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5599 value = 0; /* Fully resolved at runtime. No addend. */
5600 break;
47926f60
KH		 5601
5602 case BFD_RELOC_VTABLE_INHERIT:
5603 case BFD_RELOC_VTABLE_ENTRY:
5604 fixP->fx_done = 0;
94f592af 5605 return;
47926f60
KH		 5606
5607 default:
5608 break;
5609 }
5610#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5611 *valP = value;
f86103b7 5612#endif /* !defined (TE_Mach) */
3e73aa7c 5613
3e73aa7c 5614 /* Are we finished with this relocation now? */
c6682705 5615 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5616 fixP->fx_done = 1;
5617 else if (use_rela_relocations)
5618 {
5619 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5620 /* Remember value for tc_gen_reloc. */
5621 fixP->fx_addnumber = value;
3e73aa7c
JH		 5622 value = 0;
5623 }
f86103b7 5624
94f592af 5625 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5626}
252b5132 5627\f
252b5132
RH		 5628#define MAX_LITTLENUMS 6
5629
47926f60
KH		 5630/* Turn the string pointed to by litP into a floating point constant
5631 of type TYPE, and emit the appropriate bytes. The number of
5632 LITTLENUMS emitted is stored in *SIZEP. An error message is
5633 returned, or NULL on OK. */
5634
252b5132
RH		 5635char *
5636md_atof (type, litP, sizeP)
2ab9b79e 5637 int type;
252b5132
RH		 5638 char *litP;
5639 int *sizeP;
5640{
5641 int prec;
5642 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5643 LITTLENUM_TYPE *wordP;
5644 char *t;
5645
5646 switch (type)
5647 {
5648 case 'f':
5649 case 'F':
5650 prec = 2;
5651 break;
5652
5653 case 'd':
5654 case 'D':
5655 prec = 4;
5656 break;
5657
5658 case 'x':
5659 case 'X':
5660 prec = 5;
5661 break;
5662
5663 default:
5664 *sizeP = 0;
5665 return _("Bad call to md_atof ()");
5666 }
5667 t = atof_ieee (input_line_pointer, type, words);
5668 if (t)
5669 input_line_pointer = t;
5670
5671 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5672 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5673 the bigendian 386. */
5674 for (wordP = words + prec - 1; prec--;)
5675 {
5676 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5677 litP += sizeof (LITTLENUM_TYPE);
5678 }
5679 return 0;
5680}
5681\f
2d545b82 5682static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5683
252b5132
RH		 5684static char *
5685output_invalid (c)
5686 int c;
5687{
3882b010 5688 if (ISPRINT (c))
f9f21a03
L		 5689 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5690 "'%c'", c);
252b5132 5691 else
f9f21a03 5692 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5693 "(0x%x)", (unsigned char) c);
252b5132
RH		 5694 return output_invalid_buf;
5695}
5696
af6bdddf 5697/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5698
5699static const reg_entry *
4d1bb795 5700parse_real_register (char *reg_string, char **end_op)
252b5132 5701{
af6bdddf
AM		 5702 char *s = reg_string;
5703 char *p;
252b5132
RH		 5704 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5705 const reg_entry *r;
5706
5707 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5708 if (*s == REGISTER_PREFIX)
5709 ++s;
5710
5711 if (is_space_char (*s))
5712 ++s;
5713
5714 p = reg_name_given;
af6bdddf 5715 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5716 {
5717 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5718 return (const reg_entry *) NULL;
5719 s++;
252b5132
RH		 5720 }
5721
6588847e
DN		 5722 /* For naked regs, make sure that we are not dealing with an identifier.
5723 This prevents confusing an identifier like `eax_var' with register
5724 `eax'. */
5725 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5726 return (const reg_entry *) NULL;
5727
af6bdddf 5728 *end_op = s;
252b5132
RH		 5729
5730 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5731
5f47d35b 5732 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5733 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5734 {
5f47d35b
AM		 5735 if (is_space_char (*s))
5736 ++s;
5737 if (*s == '(')
5738 {
af6bdddf 5739 ++s;
5f47d35b
AM		 5740 if (is_space_char (*s))
5741 ++s;
5742 if (*s >= '0' && *s <= '7')
5743 {
5744 r = &i386_float_regtab[*s - '0'];
af6bdddf 5745 ++s;
5f47d35b
AM		 5746 if (is_space_char (*s))
5747 ++s;
5748 if (*s == ')')
5749 {
5750 *end_op = s + 1;
5751 return r;
5752 }
5f47d35b 5753 }
47926f60 5754 /* We have "%st(" then garbage. */
5f47d35b
AM		 5755 return (const reg_entry *) NULL;
5756 }
5757 }
5758
1ae00879 5759 if (r != NULL
20f0a1fc 5760 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5761 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5762 && flag_code != CODE_64BIT)
20f0a1fc 5763 return (const reg_entry *) NULL;
1ae00879 5764
252b5132
RH		 5765 return r;
5766}
4d1bb795
JB		 5767
5768/* REG_STRING starts *before* REGISTER_PREFIX. */
5769
5770static const reg_entry *
5771parse_register (char *reg_string, char **end_op)
5772{
5773 const reg_entry *r;
5774
5775 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5776 r = parse_real_register (reg_string, end_op);
5777 else
5778 r = NULL;
5779 if (!r)
5780 {
5781 char *save = input_line_pointer;
5782 char c;
5783 symbolS *symbolP;
5784
5785 input_line_pointer = reg_string;
5786 c = get_symbol_end ();
5787 symbolP = symbol_find (reg_string);
5788 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5789 {
5790 const expressionS *e = symbol_get_value_expression (symbolP);
5791
5792 know (e->X_op == O_register);
5793 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5794 r = i386_regtab + e->X_add_number;
5795 *end_op = input_line_pointer;
5796 }
5797 *input_line_pointer = c;
5798 input_line_pointer = save;
5799 }
5800 return r;
5801}
5802
5803int
5804i386_parse_name (char *name, expressionS *e, char *nextcharP)
5805{
5806 const reg_entry *r;
5807 char *end = input_line_pointer;
5808
5809 *end = *nextcharP;
5810 r = parse_register (name, &input_line_pointer);
5811 if (r && end <= input_line_pointer)
5812 {
5813 *nextcharP = *input_line_pointer;
5814 *input_line_pointer = 0;
5815 e->X_op = O_register;
5816 e->X_add_number = r - i386_regtab;
5817 return 1;
5818 }
5819 input_line_pointer = end;
5820 *end = 0;
5821 return 0;
5822}
5823
5824void
5825md_operand (expressionS *e)
5826{
5827 if (*input_line_pointer == REGISTER_PREFIX)
5828 {
5829 char *end;
5830 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5831
5832 if (r)
5833 {
5834 e->X_op = O_register;
5835 e->X_add_number = r - i386_regtab;
5836 input_line_pointer = end;
5837 }
5838 }
5839}
5840
252b5132 5841\f
4cc782b5 5842#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5843const char *md_shortopts = "kVQ:sqn";
252b5132 5844#else
12b55ccc 5845const char *md_shortopts = "qn";
252b5132 5846#endif
6e0b89ee 5847
3e73aa7c 5848#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5849#define OPTION_64 (OPTION_MD_BASE + 1)
5850#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 5851#define OPTION_MARCH (OPTION_MD_BASE + 3)
5852#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 5853
99ad8390
NC		 5854struct option md_longopts[] =
5855{
3e73aa7c 5856 {"32", no_argument, NULL, OPTION_32},
99ad8390 5857#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 5858 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5859#endif
b3b91714 5860 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 5861 {"march", required_argument, NULL, OPTION_MARCH},
5862 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 5863 {NULL, no_argument, NULL, 0}
5864};
5865size_t md_longopts_size = sizeof (md_longopts);
5866
5867int
9103f4f4 5868md_parse_option (int c, char *arg)
252b5132 5869{
9103f4f4
L		 5870 unsigned int i;
5871
252b5132
RH		 5872 switch (c)
5873 {
12b55ccc
L		 5874 case 'n':
5875 optimize_align_code = 0;
5876 break;
5877
a38cf1db
AM		 5878 case 'q':
5879 quiet_warnings = 1;
252b5132
RH		 5880 break;
5881
5882#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5883 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5884 should be emitted or not. FIXME: Not implemented. */
5885 case 'Q':
252b5132
RH		 5886 break;
5887
5888 /* -V: SVR4 argument to print version ID. */
5889 case 'V':
5890 print_version_id ();
5891 break;
5892
a38cf1db
AM		 5893 /* -k: Ignore for FreeBSD compatibility. */
5894 case 'k':
252b5132 5895 break;
4cc782b5
ILT		 5896
5897 case 's':
5898 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5899 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5900 break;
99ad8390
NC		 5901#endif
5902#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 5903 case OPTION_64:
5904 {
5905 const char **list, **l;
5906
3e73aa7c
JH		 5907 list = bfd_target_list ();
5908 for (l = list; *l != NULL; l++)
8620418b 5909 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 5910 || strcmp (*l, "coff-x86-64") == 0
5911 || strcmp (*l, "pe-x86-64") == 0
5912 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 5913 {
5914 default_arch = "x86_64";
5915 break;
5916 }
3e73aa7c 5917 if (*l == NULL)
6e0b89ee 5918 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5919 free (list);
5920 }
5921 break;
5922#endif
252b5132 5923
6e0b89ee
AM		 5924 case OPTION_32:
5925 default_arch = "i386";
5926 break;
5927
b3b91714
AM		 5928 case OPTION_DIVIDE:
5929#ifdef SVR4_COMMENT_CHARS
5930 {
5931 char *n, *t;
5932 const char *s;
5933
5934 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5935 t = n;
5936 for (s = i386_comment_chars; *s != '\0'; s++)
5937 if (*s != '/')
5938 *t++ = *s;
5939 *t = '\0';
5940 i386_comment_chars = n;
5941 }
5942#endif
5943 break;
5944
9103f4f4
L		 5945 case OPTION_MARCH:
5946 if (*arg == '.')
5947 as_fatal (_("Invalid -march= option: `%s'"), arg);
5948 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5949 {
5950 if (strcmp (arg, cpu_arch [i].name) == 0)
5951 {
ccc9c027 5952 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 5953 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 5954 if (!cpu_arch_tune_set)
5955 {
5956 cpu_arch_tune = cpu_arch_isa;
5957 cpu_arch_tune_flags = cpu_arch_isa_flags;
5958 }
9103f4f4
L		 5959 break;
5960 }
5961 }
5962 if (i >= ARRAY_SIZE (cpu_arch))
5963 as_fatal (_("Invalid -march= option: `%s'"), arg);
5964 break;
5965
5966 case OPTION_MTUNE:
5967 if (*arg == '.')
5968 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5969 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5970 {
5971 if (strcmp (arg, cpu_arch [i].name) == 0)
5972 {
ccc9c027 5973 cpu_arch_tune_set = 1;
9103f4f4
L		 5974 cpu_arch_tune = cpu_arch [i].type;
5975 cpu_arch_tune_flags = cpu_arch[i].flags;
5976 break;
5977 }
5978 }
5979 if (i >= ARRAY_SIZE (cpu_arch))
5980 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5981 break;
5982
252b5132
RH		 5983 default:
5984 return 0;
5985 }
5986 return 1;
5987}
5988
5989void
5990md_show_usage (stream)
5991 FILE *stream;
5992{
4cc782b5
ILT		 5993#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5994 fprintf (stream, _("\
a38cf1db
AM		 5995 -Q ignored\n\
5996 -V print assembler version number\n\
b3b91714
AM		 5997 -k ignored\n"));
5998#endif
5999 fprintf (stream, _("\
12b55ccc 6000 -n Do not optimize code alignment\n\
b3b91714
AM		 6001 -q quieten some warnings\n"));
6002#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6003 fprintf (stream, _("\
a38cf1db 6004 -s ignored\n"));
b3b91714
AM		 6005#endif
6006#ifdef SVR4_COMMENT_CHARS
6007 fprintf (stream, _("\
6008 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 6009#else
6010 fprintf (stream, _("\
b3b91714 6011 --divide ignored\n"));
4cc782b5 6012#endif
9103f4f4
L		 6013 fprintf (stream, _("\
6014 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6015 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
ef05d495 6016 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 6017
252b5132
RH		 6018}
6019
99ad8390
NC		 6020#if defined(TE_PEP)
6021const char *
6022x86_64_target_format (void)
6023{
6024 if (strcmp (default_arch, "x86_64") == 0)
6025 {
6026 set_code_flag (CODE_64BIT);
6027 return COFF_TARGET_FORMAT;
6028 }
6029 else if (strcmp (default_arch, "i386") == 0)
6030 {
6031 set_code_flag (CODE_32BIT);
6032 return "coff-i386";
6033 }
6034
6035 as_fatal (_("Unknown architecture"));
6036 return NULL;
6037}
6038#endif
6039
3e73aa7c
JH		 6040#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6041 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 6042
6043/* Pick the target format to use. */
6044
47926f60 6045const char *
252b5132
RH		 6046i386_target_format ()
6047{
3e73aa7c 6048 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 6049 {
6050 set_code_flag (CODE_64BIT);
6051 if (cpu_arch_isa_flags == 0)
d32cad65 6052 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
9103f4f4
L		 6053 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6054 |CpuSSE|CpuSSE2;
ccc9c027 6055 if (cpu_arch_tune_flags == 0)
d32cad65 6056 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
ccc9c027
L		 6057 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6058 |CpuSSE|CpuSSE2;
9103f4f4 6059 }
3e73aa7c 6060 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 6061 {
6062 set_code_flag (CODE_32BIT);
6063 if (cpu_arch_isa_flags == 0)
d32cad65 6064 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
ccc9c027 6065 if (cpu_arch_tune_flags == 0)
d32cad65 6066 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
9103f4f4 6067 }
3e73aa7c
JH		 6068 else
6069 as_fatal (_("Unknown architecture"));
252b5132
RH		 6070 switch (OUTPUT_FLAVOR)
6071 {
4c63da97
AM		 6072#ifdef OBJ_MAYBE_AOUT
6073 case bfd_target_aout_flavour:
47926f60 6074 return AOUT_TARGET_FORMAT;
4c63da97
AM		 6075#endif
6076#ifdef OBJ_MAYBE_COFF
252b5132
RH		 6077 case bfd_target_coff_flavour:
6078 return "coff-i386";
4c63da97 6079#endif
3e73aa7c 6080#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 6081 case bfd_target_elf_flavour:
3e73aa7c 6082 {
e5cb08ac 6083 if (flag_code == CODE_64BIT)
4fa24527
JB		 6084 {
6085 object_64bit = 1;
6086 use_rela_relocations = 1;
6087 }
9d7cbccd 6088 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6089 }
4c63da97 6090#endif
252b5132
RH		 6091 default:
6092 abort ();
6093 return NULL;
6094 }
6095}
6096
47926f60 6097#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 6098
6099#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6100void i386_elf_emit_arch_note ()
6101{
718ddfc0 6102 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 6103 {
6104 char *p;
6105 asection *seg = now_seg;
6106 subsegT subseg = now_subseg;
6107 Elf_Internal_Note i_note;
6108 Elf_External_Note e_note;
6109 asection *note_secp;
6110 int len;
6111
6112 /* Create the .note section. */
6113 note_secp = subseg_new (".note", 0);
6114 bfd_set_section_flags (stdoutput,
6115 note_secp,
6116 SEC_HAS_CONTENTS | SEC_READONLY);
6117
6118 /* Process the arch string. */
6119 len = strlen (cpu_arch_name);
6120
6121 i_note.namesz = len + 1;
6122 i_note.descsz = 0;
6123 i_note.type = NT_ARCH;
6124 p = frag_more (sizeof (e_note.namesz));
6125 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6126 p = frag_more (sizeof (e_note.descsz));
6127 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6128 p = frag_more (sizeof (e_note.type));
6129 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6130 p = frag_more (len + 1);
6131 strcpy (p, cpu_arch_name);
6132
6133 frag_align (2, 0, 0);
6134
6135 subseg_set (seg, subseg);
6136 }
6137}
6138#endif
252b5132 6139\f
252b5132
RH		 6140symbolS *
6141md_undefined_symbol (name)
6142 char *name;
6143{
18dc2407
ILT		 6144 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6145 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6146 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6147 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6148 {
6149 if (!GOT_symbol)
6150 {
6151 if (symbol_find (name))
6152 as_bad (_("GOT already in symbol table"));
6153 GOT_symbol = symbol_new (name, undefined_section,
6154 (valueT) 0, &zero_address_frag);
6155 };
6156 return GOT_symbol;
6157 }
252b5132
RH		 6158 return 0;
6159}
6160
6161/* Round up a section size to the appropriate boundary. */
47926f60 6162
252b5132
RH		 6163valueT
6164md_section_align (segment, size)
ab9da554 6165 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6166 valueT size;
6167{
4c63da97
AM		 6168#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6169 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6170 {
6171 /* For a.out, force the section size to be aligned. If we don't do
6172 this, BFD will align it for us, but it will not write out the
6173 final bytes of the section. This may be a bug in BFD, but it is
6174 easier to fix it here since that is how the other a.out targets
6175 work. */
6176 int align;
6177
6178 align = bfd_get_section_alignment (stdoutput, segment);
6179 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6180 }
252b5132
RH		 6181#endif
6182
6183 return size;
6184}
6185
6186/* On the i386, PC-relative offsets are relative to the start of the
6187 next instruction. That is, the address of the offset, plus its
6188 size, since the offset is always the last part of the insn. */
6189
6190long
6191md_pcrel_from (fixP)
6192 fixS *fixP;
6193{
6194 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6195}
6196
6197#ifndef I386COFF
6198
6199static void
6200s_bss (ignore)
ab9da554 6201 int ignore ATTRIBUTE_UNUSED;
252b5132 6202{
29b0f896 6203 int temp;
252b5132 6204
8a75718c
JB		 6205#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6206 if (IS_ELF)
6207 obj_elf_section_change_hook ();
6208#endif
252b5132
RH		 6209 temp = get_absolute_expression ();
6210 subseg_set (bss_section, (subsegT) temp);
6211 demand_empty_rest_of_line ();
6212}
6213
6214#endif
6215
252b5132
RH		 6216void
6217i386_validate_fix (fixp)
6218 fixS *fixp;
6219{
6220 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6221 {
23df1078
JH		 6222 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6223 {
4fa24527 6224 if (!object_64bit)
23df1078
JH		 6225 abort ();
6226 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6227 }
6228 else
6229 {
4fa24527 6230 if (!object_64bit)
d6ab8113
JB		 6231 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6232 else
6233 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6234 }
252b5132
RH		 6235 fixp->fx_subsy = 0;
6236 }
6237}
6238
252b5132
RH		 6239arelent *
6240tc_gen_reloc (section, fixp)
ab9da554 6241 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6242 fixS *fixp;
6243{
6244 arelent *rel;
6245 bfd_reloc_code_real_type code;
6246
6247 switch (fixp->fx_r_type)
6248 {
3e73aa7c
JH		 6249 case BFD_RELOC_X86_64_PLT32:
6250 case BFD_RELOC_X86_64_GOT32:
6251 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6252 case BFD_RELOC_386_PLT32:
6253 case BFD_RELOC_386_GOT32:
6254 case BFD_RELOC_386_GOTOFF:
6255 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 6256 case BFD_RELOC_386_TLS_GD:
6257 case BFD_RELOC_386_TLS_LDM:
6258 case BFD_RELOC_386_TLS_LDO_32:
6259 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6260 case BFD_RELOC_386_TLS_IE:
6261 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 6262 case BFD_RELOC_386_TLS_LE_32:
6263 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 6264 case BFD_RELOC_386_TLS_GOTDESC:
6265 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 6266 case BFD_RELOC_X86_64_TLSGD:
6267 case BFD_RELOC_X86_64_TLSLD:
6268 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6269 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 6270 case BFD_RELOC_X86_64_GOTTPOFF:
6271 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 6272 case BFD_RELOC_X86_64_TPOFF64:
6273 case BFD_RELOC_X86_64_GOTOFF64:
6274 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 6275 case BFD_RELOC_X86_64_GOT64:
6276 case BFD_RELOC_X86_64_GOTPCREL64:
6277 case BFD_RELOC_X86_64_GOTPC64:
6278 case BFD_RELOC_X86_64_GOTPLT64:
6279 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 6280 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6281 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 6282 case BFD_RELOC_RVA:
6283 case BFD_RELOC_VTABLE_ENTRY:
6284 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 6285#ifdef TE_PE
6286 case BFD_RELOC_32_SECREL:
6287#endif
252b5132
RH		 6288 code = fixp->fx_r_type;
6289 break;
dbbaec26
L		 6290 case BFD_RELOC_X86_64_32S:
6291 if (!fixp->fx_pcrel)
6292 {
6293 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6294 code = fixp->fx_r_type;
6295 break;
6296 }
252b5132 6297 default:
93382f6d 6298 if (fixp->fx_pcrel)
252b5132 6299 {
93382f6d
AM		 6300 switch (fixp->fx_size)
6301 {
6302 default:
b091f402
AM		 6303 as_bad_where (fixp->fx_file, fixp->fx_line,
6304 _("can not do %d byte pc-relative relocation"),
6305 fixp->fx_size);
93382f6d
AM		 6306 code = BFD_RELOC_32_PCREL;
6307 break;
6308 case 1: code = BFD_RELOC_8_PCREL; break;
6309 case 2: code = BFD_RELOC_16_PCREL; break;
6310 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 6311#ifdef BFD64
6312 case 8: code = BFD_RELOC_64_PCREL; break;
6313#endif
93382f6d
AM		 6314 }
6315 }
6316 else
6317 {
6318 switch (fixp->fx_size)
6319 {
6320 default:
b091f402
AM		 6321 as_bad_where (fixp->fx_file, fixp->fx_line,
6322 _("can not do %d byte relocation"),
6323 fixp->fx_size);
93382f6d
AM		 6324 code = BFD_RELOC_32;
6325 break;
6326 case 1: code = BFD_RELOC_8; break;
6327 case 2: code = BFD_RELOC_16; break;
6328 case 4: code = BFD_RELOC_32; break;
937149dd 6329#ifdef BFD64
3e73aa7c 6330 case 8: code = BFD_RELOC_64; break;
937149dd 6331#endif
93382f6d 6332 }
252b5132
RH		 6333 }
6334 break;
6335 }
252b5132 6336
d182319b
JB		 6337 if ((code == BFD_RELOC_32
6338 || code == BFD_RELOC_32_PCREL
6339 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 6340 && GOT_symbol
6341 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 6342 {
4fa24527 6343 if (!object_64bit)
d6ab8113
JB		 6344 code = BFD_RELOC_386_GOTPC;
6345 else
6346 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 6347 }
7b81dfbb
AJ		 6348 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6349 && GOT_symbol
6350 && fixp->fx_addsy == GOT_symbol)
6351 {
6352 code = BFD_RELOC_X86_64_GOTPC64;
6353 }
252b5132
RH		 6354
6355 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 6356 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6357 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 6358
6359 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 6360
3e73aa7c
JH		 6361 if (!use_rela_relocations)
6362 {
6363 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6364 vtable entry to be used in the relocation's section offset. */
6365 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6366 rel->address = fixp->fx_offset;
252b5132 6367
c6682705 6368 rel->addend = 0;
3e73aa7c
JH		 6369 }
6370 /* Use the rela in 64bit mode. */
252b5132 6371 else
3e73aa7c 6372 {
062cd5e7
AS		 6373 if (!fixp->fx_pcrel)
6374 rel->addend = fixp->fx_offset;
6375 else
6376 switch (code)
6377 {
6378 case BFD_RELOC_X86_64_PLT32:
6379 case BFD_RELOC_X86_64_GOT32:
6380 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 6381 case BFD_RELOC_X86_64_TLSGD:
6382 case BFD_RELOC_X86_64_TLSLD:
6383 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 6384 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6385 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 6386 rel->addend = fixp->fx_offset - fixp->fx_size;
6387 break;
6388 default:
6389 rel->addend = (section->vma
6390 - fixp->fx_size
6391 + fixp->fx_addnumber
6392 + md_pcrel_from (fixp));
6393 break;
6394 }
3e73aa7c
JH		 6395 }
6396
252b5132
RH		 6397 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6398 if (rel->howto == NULL)
6399 {
6400 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 6401 _("cannot represent relocation type %s"),
252b5132
RH		 6402 bfd_get_reloc_code_name (code));
6403 /* Set howto to a garbage value so that we can keep going. */
6404 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6405 assert (rel->howto != NULL);
6406 }
6407
6408 return rel;
6409}
6410
64a0c779
DN		 6411\f
6412/* Parse operands using Intel syntax. This implements a recursive descent
6413 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6414 Programmer's Guide.
6415
6416 FIXME: We do not recognize the full operand grammar defined in the MASM
6417 documentation. In particular, all the structure/union and
6418 high-level macro operands are missing.
6419
6420 Uppercase words are terminals, lower case words are non-terminals.
6421 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6422 bars '|' denote choices. Most grammar productions are implemented in
6423 functions called 'intel_<production>'.
6424
6425 Initial production is 'expr'.
6426
9306ca4a 6427 addOp + | -
64a0c779
DN		 6428
6429 alpha [a-zA-Z]
6430
9306ca4a
JB		 6431 binOp & | AND | \| | OR | ^ | XOR
6432
64a0c779
DN		 6433 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6434
6435 constant digits [[ radixOverride ]]
6436
9306ca4a 6437 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 6438
6439 digits decdigit
b77a7acd
AJ		 6440 | digits decdigit
6441 | digits hexdigit
64a0c779
DN		 6442
6443 decdigit [0-9]
6444
9306ca4a
JB		 6445 e04 e04 addOp e05
6446 | e05
6447
6448 e05 e05 binOp e06
b77a7acd 6449 | e06
64a0c779
DN		 6450
6451 e06 e06 mulOp e09
b77a7acd 6452 | e09
64a0c779
DN		 6453
6454 e09 OFFSET e10
a724f0f4
JB		 6455 | SHORT e10
6456 | + e10
6457 | - e10
9306ca4a
JB		 6458 | ~ e10
6459 | NOT e10
64a0c779
DN		 6460 | e09 PTR e10
6461 | e09 : e10
6462 | e10
6463
6464 e10 e10 [ expr ]
b77a7acd 6465 | e11
64a0c779
DN		 6466
6467 e11 ( expr )
b77a7acd 6468 | [ expr ]
64a0c779
DN		 6469 | constant
6470 | dataType
6471 | id
6472 | $
6473 | register
6474
a724f0f4 6475 => expr expr cmpOp e04
9306ca4a 6476 | e04
64a0c779
DN		 6477
6478 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 6479 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 6480
6481 hexdigit a | b | c | d | e | f
b77a7acd 6482 | A | B | C | D | E | F
64a0c779
DN		 6483
6484 id alpha
b77a7acd 6485 | id alpha
64a0c779
DN		 6486 | id decdigit
6487
9306ca4a 6488 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 6489
6490 quote " | '
6491
6492 register specialRegister
b77a7acd 6493 | gpRegister
64a0c779
DN		 6494 | byteRegister
6495
6496 segmentRegister CS | DS | ES | FS | GS | SS
6497
9306ca4a 6498 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 6499 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 6500 | TR3 | TR4 | TR5 | TR6 | TR7
6501
64a0c779
DN		 6502 We simplify the grammar in obvious places (e.g., register parsing is
6503 done by calling parse_register) and eliminate immediate left recursion
6504 to implement a recursive-descent parser.
6505
a724f0f4
JB		 6506 expr e04 expr'
6507
6508 expr' cmpOp e04 expr'
6509 | Empty
9306ca4a
JB		 6510
6511 e04 e05 e04'
6512
6513 e04' addOp e05 e04'
6514 | Empty
64a0c779
DN		 6515
6516 e05 e06 e05'
6517
9306ca4a 6518 e05' binOp e06 e05'
b77a7acd 6519 | Empty
64a0c779
DN		 6520
6521 e06 e09 e06'
6522
6523 e06' mulOp e09 e06'
b77a7acd 6524 | Empty
64a0c779
DN		 6525
6526 e09 OFFSET e10 e09'
a724f0f4
JB		 6527 | SHORT e10'
6528 | + e10'
6529 | - e10'
6530 | ~ e10'
6531 | NOT e10'
b77a7acd 6532 | e10 e09'
64a0c779
DN		 6533
6534 e09' PTR e10 e09'
b77a7acd 6535 | : e10 e09'
64a0c779
DN		 6536 | Empty
6537
6538 e10 e11 e10'
6539
6540 e10' [ expr ] e10'
b77a7acd 6541 | Empty
64a0c779
DN		 6542
6543 e11 ( expr )
b77a7acd 6544 | [ expr ]
64a0c779
DN		 6545 | BYTE
6546 | WORD
6547 | DWORD
9306ca4a 6548 | FWORD
64a0c779 6549 | QWORD
9306ca4a
JB		 6550 | TBYTE
6551 | OWORD
6552 | XMMWORD
64a0c779
DN		 6553 | .
6554 | $
6555 | register
6556 | id
6557 | constant */
6558
6559/* Parsing structure for the intel syntax parser. Used to implement the
6560 semantic actions for the operand grammar. */
6561struct intel_parser_s
6562 {
6563 char *op_string; /* The string being parsed. */
6564 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6565 int op_modifier; /* Operand modifier. */
64a0c779 6566 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 6567 int in_offset; /* >=1 if parsing operand of offset. */
6568 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6569 const reg_entry *reg; /* Last register reference found. */
6570 char *disp; /* Displacement string being built. */
a724f0f4 6571 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6572 };
6573
6574static struct intel_parser_s intel_parser;
6575
6576/* Token structure for parsing intel syntax. */
6577struct intel_token
6578 {
6579 int code; /* Token code. */
6580 const reg_entry *reg; /* Register entry for register tokens. */
6581 char *str; /* String representation. */
6582 };
6583
6584static struct intel_token cur_token, prev_token;
6585
50705ef4
AM		 6586/* Token codes for the intel parser. Since T_SHORT is already used
6587 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6588#define T_NIL -1
6589#define T_CONST 1
6590#define T_REG 2
6591#define T_BYTE 3
6592#define T_WORD 4
9306ca4a
JB		 6593#define T_DWORD 5
6594#define T_FWORD 6
6595#define T_QWORD 7
6596#define T_TBYTE 8
6597#define T_XMMWORD 9
50705ef4 6598#undef T_SHORT
9306ca4a
JB		 6599#define T_SHORT 10
6600#define T_OFFSET 11
6601#define T_PTR 12
6602#define T_ID 13
6603#define T_SHL 14
6604#define T_SHR 15
64a0c779
DN		 6605
6606/* Prototypes for intel parser functions. */
6607static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 6608static void intel_get_token PARAMS ((void));
6609static void intel_putback_token PARAMS ((void));
6610static int intel_expr PARAMS ((void));
9306ca4a 6611static int intel_e04 PARAMS ((void));
cce0cbdc 6612static int intel_e05 PARAMS ((void));
cce0cbdc 6613static int intel_e06 PARAMS ((void));
cce0cbdc 6614static int intel_e09 PARAMS ((void));
a724f0f4 6615static int intel_bracket_expr PARAMS ((void));
cce0cbdc 6616static int intel_e10 PARAMS ((void));
cce0cbdc 6617static int intel_e11 PARAMS ((void));
64a0c779 6618
64a0c779
DN		 6619static int
6620i386_intel_operand (operand_string, got_a_float)
6621 char *operand_string;
6622 int got_a_float;
6623{
6624 int ret;
6625 char *p;
6626
a724f0f4
JB		 6627 p = intel_parser.op_string = xstrdup (operand_string);
6628 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6629
6630 for (;;)
64a0c779 6631 {
a724f0f4
JB		 6632 /* Initialize token holders. */
6633 cur_token.code = prev_token.code = T_NIL;
6634 cur_token.reg = prev_token.reg = NULL;
6635 cur_token.str = prev_token.str = NULL;
6636
6637 /* Initialize parser structure. */
6638 intel_parser.got_a_float = got_a_float;
6639 intel_parser.op_modifier = 0;
6640 intel_parser.is_mem = 0;
6641 intel_parser.in_offset = 0;
6642 intel_parser.in_bracket = 0;
6643 intel_parser.reg = NULL;
6644 intel_parser.disp[0] = '\0';
6645 intel_parser.next_operand = NULL;
6646
6647 /* Read the first token and start the parser. */
6648 intel_get_token ();
6649 ret = intel_expr ();
6650
6651 if (!ret)
6652 break;
6653
9306ca4a
JB		 6654 if (cur_token.code != T_NIL)
6655 {
6656 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6657 current_templates->start->name, cur_token.str);
6658 ret = 0;
6659 }
64a0c779
DN		 6660 /* If we found a memory reference, hand it over to i386_displacement
6661 to fill in the rest of the operand fields. */
9306ca4a 6662 else if (intel_parser.is_mem)
64a0c779
DN		 6663 {
6664 if ((i.mem_operands == 1
6665 && (current_templates->start->opcode_modifier & IsString) == 0)
6666 || i.mem_operands == 2)
6667 {
6668 as_bad (_("too many memory references for '%s'"),
6669 current_templates->start->name);
6670 ret = 0;
6671 }
6672 else
6673 {
6674 char *s = intel_parser.disp;
6675 i.mem_operands++;
6676
a724f0f4
JB		 6677 if (!quiet_warnings && intel_parser.is_mem < 0)
6678 /* See the comments in intel_bracket_expr. */
6679 as_warn (_("Treating `%s' as memory reference"), operand_string);
6680
64a0c779
DN		 6681 /* Add the displacement expression. */
6682 if (*s != '\0')
a4622f40
AM		 6683 ret = i386_displacement (s, s + strlen (s));
6684 if (ret)
a724f0f4
JB		 6685 {
6686 /* Swap base and index in 16-bit memory operands like
6687 [si+bx]. Since i386_index_check is also used in AT&T
6688 mode we have to do that here. */
6689 if (i.base_reg
6690 && i.index_reg
6691 && (i.base_reg->reg_type & Reg16)
6692 && (i.index_reg->reg_type & Reg16)
6693 && i.base_reg->reg_num >= 6
6694 && i.index_reg->reg_num < 6)
6695 {
6696 const reg_entry *base = i.index_reg;
6697
6698 i.index_reg = i.base_reg;
6699 i.base_reg = base;
6700 }
6701 ret = i386_index_check (operand_string);
6702 }
64a0c779
DN		 6703 }
6704 }
6705
6706 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6707 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6708 || intel_parser.reg == NULL)
6709 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6710
6711 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6712 ret = 0;
6713 if (!ret || !intel_parser.next_operand)
6714 break;
6715 intel_parser.op_string = intel_parser.next_operand;
6716 this_operand = i.operands++;
64a0c779
DN		 6717 }
6718
6719 free (p);
6720 free (intel_parser.disp);
6721
6722 return ret;
6723}
6724
a724f0f4
JB		 6725#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6726
6727/* expr e04 expr'
6728
6729 expr' cmpOp e04 expr'
6730 | Empty */
64a0c779
DN		 6731static int
6732intel_expr ()
6733{
a724f0f4
JB		 6734 /* XXX Implement the comparison operators. */
6735 return intel_e04 ();
9306ca4a
JB		 6736}
6737
a724f0f4 6738/* e04 e05 e04'
9306ca4a 6739
a724f0f4 6740 e04' addOp e05 e04'
9306ca4a
JB		 6741 | Empty */
6742static int
6743intel_e04 ()
6744{
a724f0f4 6745 int nregs = -1;
9306ca4a 6746
a724f0f4 6747 for (;;)
9306ca4a 6748 {
a724f0f4
JB		 6749 if (!intel_e05())
6750 return 0;
9306ca4a 6751
a724f0f4
JB		 6752 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6753 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6754
a724f0f4
JB		 6755 if (cur_token.code == '+')
6756 nregs = -1;
6757 else if (cur_token.code == '-')
6758 nregs = NUM_ADDRESS_REGS;
6759 else
6760 return 1;
64a0c779 6761
a724f0f4
JB		 6762 strcat (intel_parser.disp, cur_token.str);
6763 intel_match_token (cur_token.code);
6764 }
64a0c779
DN		 6765}
6766
64a0c779
DN		 6767/* e05 e06 e05'
6768
9306ca4a 6769 e05' binOp e06 e05'
64a0c779
DN		 6770 | Empty */
6771static int
6772intel_e05 ()
6773{
a724f0f4 6774 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6775
a724f0f4 6776 for (;;)
64a0c779 6777 {
a724f0f4
JB		 6778 if (!intel_e06())
6779 return 0;
6780
6781 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6782 {
6783 char str[2];
6784
6785 str[0] = cur_token.code;
6786 str[1] = 0;
6787 strcat (intel_parser.disp, str);
6788 }
6789 else
6790 break;
9306ca4a 6791
64a0c779
DN		 6792 intel_match_token (cur_token.code);
6793
a724f0f4
JB		 6794 if (nregs < 0)
6795 nregs = ~nregs;
64a0c779 6796 }
a724f0f4
JB		 6797 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6798 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6799 return 1;
4a1805b1 6800}
64a0c779
DN		 6801
6802/* e06 e09 e06'
6803
6804 e06' mulOp e09 e06'
b77a7acd 6805 | Empty */
64a0c779
DN		 6806static int
6807intel_e06 ()
6808{
a724f0f4 6809 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6810
a724f0f4 6811 for (;;)
64a0c779 6812 {
a724f0f4
JB		 6813 if (!intel_e09())
6814 return 0;
9306ca4a 6815
a724f0f4
JB		 6816 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6817 {
6818 char str[2];
9306ca4a 6819
a724f0f4
JB		 6820 str[0] = cur_token.code;
6821 str[1] = 0;
6822 strcat (intel_parser.disp, str);
6823 }
6824 else if (cur_token.code == T_SHL)
6825 strcat (intel_parser.disp, "<<");
6826 else if (cur_token.code == T_SHR)
6827 strcat (intel_parser.disp, ">>");
6828 else
6829 break;
9306ca4a 6830
64e74474 6831 intel_match_token (cur_token.code);
64a0c779 6832
a724f0f4
JB		 6833 if (nregs < 0)
6834 nregs = ~nregs;
64a0c779 6835 }
a724f0f4
JB		 6836 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6837 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6838 return 1;
64a0c779
DN		 6839}
6840
a724f0f4
JB		 6841/* e09 OFFSET e09
6842 | SHORT e09
6843 | + e09
6844 | - e09
6845 | ~ e09
6846 | NOT e09
9306ca4a
JB		 6847 | e10 e09'
6848
64a0c779 6849 e09' PTR e10 e09'
b77a7acd 6850 | : e10 e09'
64a0c779
DN		 6851 | Empty */
6852static int
6853intel_e09 ()
6854{
a724f0f4
JB		 6855 int nregs = ~NUM_ADDRESS_REGS;
6856 int in_offset = 0;
6857
6858 for (;;)
64a0c779 6859 {
a724f0f4
JB		 6860 /* Don't consume constants here. */
6861 if (cur_token.code == '+' || cur_token.code == '-')
6862 {
6863 /* Need to look one token ahead - if the next token
6864 is a constant, the current token is its sign. */
6865 int next_code;
6866
6867 intel_match_token (cur_token.code);
6868 next_code = cur_token.code;
6869 intel_putback_token ();
6870 if (next_code == T_CONST)
6871 break;
6872 }
6873
6874 /* e09 OFFSET e09 */
6875 if (cur_token.code == T_OFFSET)
6876 {
6877 if (!in_offset++)
6878 ++intel_parser.in_offset;
6879 }
6880
6881 /* e09 SHORT e09 */
6882 else if (cur_token.code == T_SHORT)
6883 intel_parser.op_modifier |= 1 << T_SHORT;
6884
6885 /* e09 + e09 */
6886 else if (cur_token.code == '+')
6887 strcat (intel_parser.disp, "+");
6888
6889 /* e09 - e09
6890 | ~ e09
6891 | NOT e09 */
6892 else if (cur_token.code == '-' || cur_token.code == '~')
6893 {
6894 char str[2];
64a0c779 6895
a724f0f4
JB		 6896 if (nregs < 0)
6897 nregs = ~nregs;
6898 str[0] = cur_token.code;
6899 str[1] = 0;
6900 strcat (intel_parser.disp, str);
6901 }
6902
6903 /* e09 e10 e09' */
6904 else
6905 break;
6906
6907 intel_match_token (cur_token.code);
64a0c779
DN		 6908 }
6909
a724f0f4 6910 for (;;)
9306ca4a 6911 {
a724f0f4
JB		 6912 if (!intel_e10 ())
6913 return 0;
9306ca4a 6914
a724f0f4
JB		 6915 /* e09' PTR e10 e09' */
6916 if (cur_token.code == T_PTR)
6917 {
6918 char suffix;
9306ca4a 6919
a724f0f4
JB		 6920 if (prev_token.code == T_BYTE)
6921 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6922
a724f0f4
JB		 6923 else if (prev_token.code == T_WORD)
6924 {
6925 if (current_templates->start->name[0] == 'l'
6926 && current_templates->start->name[2] == 's'
6927 && current_templates->start->name[3] == 0)
6928 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6929 else if (intel_parser.got_a_float == 2) /* "fi..." */
6930 suffix = SHORT_MNEM_SUFFIX;
6931 else
6932 suffix = WORD_MNEM_SUFFIX;
6933 }
64a0c779 6934
a724f0f4
JB		 6935 else if (prev_token.code == T_DWORD)
6936 {
6937 if (current_templates->start->name[0] == 'l'
6938 && current_templates->start->name[2] == 's'
6939 && current_templates->start->name[3] == 0)
6940 suffix = WORD_MNEM_SUFFIX;
6941 else if (flag_code == CODE_16BIT
6942 && (current_templates->start->opcode_modifier
435acd52 6943 & (Jump | JumpDword)))
a724f0f4
JB		 6944 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6945 else if (intel_parser.got_a_float == 1) /* "f..." */
6946 suffix = SHORT_MNEM_SUFFIX;
6947 else
6948 suffix = LONG_MNEM_SUFFIX;
6949 }
9306ca4a 6950
a724f0f4
JB		 6951 else if (prev_token.code == T_FWORD)
6952 {
6953 if (current_templates->start->name[0] == 'l'
6954 && current_templates->start->name[2] == 's'
6955 && current_templates->start->name[3] == 0)
6956 suffix = LONG_MNEM_SUFFIX;
6957 else if (!intel_parser.got_a_float)
6958 {
6959 if (flag_code == CODE_16BIT)
6960 add_prefix (DATA_PREFIX_OPCODE);
6961 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6962 }
6963 else
6964 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6965 }
64a0c779 6966
a724f0f4
JB		 6967 else if (prev_token.code == T_QWORD)
6968 {
6969 if (intel_parser.got_a_float == 1) /* "f..." */
6970 suffix = LONG_MNEM_SUFFIX;
6971 else
6972 suffix = QWORD_MNEM_SUFFIX;
6973 }
64a0c779 6974
a724f0f4
JB		 6975 else if (prev_token.code == T_TBYTE)
6976 {
6977 if (intel_parser.got_a_float == 1)
6978 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6979 else
6980 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6981 }
9306ca4a 6982
a724f0f4 6983 else if (prev_token.code == T_XMMWORD)
9306ca4a 6984 {
a724f0f4
JB		 6985 /* XXX ignored for now, but accepted since gcc uses it */
6986 suffix = 0;
9306ca4a 6987 }
64a0c779 6988
f16b83df 6989 else
a724f0f4
JB		 6990 {
6991 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6992 return 0;
6993 }
6994
435acd52
JB		 6995 /* Operands for jump/call using 'ptr' notation denote absolute
6996 addresses. */
6997 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6998 i.types[this_operand] |= JumpAbsolute;
6999
a724f0f4
JB		 7000 if (current_templates->start->base_opcode == 0x8d /* lea */)
7001 ;
7002 else if (!i.suffix)
7003 i.suffix = suffix;
7004 else if (i.suffix != suffix)
7005 {
7006 as_bad (_("Conflicting operand modifiers"));
7007 return 0;
7008 }
64a0c779 7009
9306ca4a
JB		 7010 }
7011
a724f0f4
JB		 7012 /* e09' : e10 e09' */
7013 else if (cur_token.code == ':')
9306ca4a 7014 {
a724f0f4
JB		 7015 if (prev_token.code != T_REG)
7016 {
7017 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7018 segment/group identifier (which we don't have), using comma
7019 as the operand separator there is even less consistent, since
7020 there all branches only have a single operand. */
7021 if (this_operand != 0
7022 || intel_parser.in_offset
7023 || intel_parser.in_bracket
7024 || (!(current_templates->start->opcode_modifier
7025 & (Jump|JumpDword|JumpInterSegment))
7026 && !(current_templates->start->operand_types[0]
7027 & JumpAbsolute)))
7028 return intel_match_token (T_NIL);
7029 /* Remember the start of the 2nd operand and terminate 1st
7030 operand here.
7031 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7032 another expression), but it gets at least the simplest case
7033 (a plain number or symbol on the left side) right. */
7034 intel_parser.next_operand = intel_parser.op_string;
7035 *--intel_parser.op_string = '\0';
7036 return intel_match_token (':');
7037 }
9306ca4a 7038 }
64a0c779 7039
a724f0f4 7040 /* e09' Empty */
64a0c779 7041 else
a724f0f4 7042 break;
64a0c779 7043
a724f0f4
JB		 7044 intel_match_token (cur_token.code);
7045
7046 }
7047
7048 if (in_offset)
7049 {
7050 --intel_parser.in_offset;
7051 if (nregs < 0)
7052 nregs = ~nregs;
7053 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 7054 {
a724f0f4 7055 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 7056 return 0;
7057 }
a724f0f4
JB		 7058 intel_parser.op_modifier |= 1 << T_OFFSET;
7059 }
9306ca4a 7060
a724f0f4
JB		 7061 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7062 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7063 return 1;
7064}
64a0c779 7065
a724f0f4
JB		 7066static int
7067intel_bracket_expr ()
7068{
7069 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7070 const char *start = intel_parser.op_string;
7071 int len;
7072
7073 if (i.op[this_operand].regs)
7074 return intel_match_token (T_NIL);
7075
7076 intel_match_token ('[');
7077
7078 /* Mark as a memory operand only if it's not already known to be an
7079 offset expression. If it's an offset expression, we need to keep
7080 the brace in. */
7081 if (!intel_parser.in_offset)
7082 {
7083 ++intel_parser.in_bracket;
435acd52
JB		 7084
7085 /* Operands for jump/call inside brackets denote absolute addresses. */
7086 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7087 i.types[this_operand] |= JumpAbsolute;
7088
a724f0f4
JB		 7089 /* Unfortunately gas always diverged from MASM in a respect that can't
7090 be easily fixed without risking to break code sequences likely to be
7091 encountered (the testsuite even check for this): MASM doesn't consider
7092 an expression inside brackets unconditionally as a memory reference.
7093 When that is e.g. a constant, an offset expression, or the sum of the
7094 two, this is still taken as a constant load. gas, however, always
7095 treated these as memory references. As a compromise, we'll try to make
7096 offset expressions inside brackets work the MASM way (since that's
7097 less likely to be found in real world code), but make constants alone
7098 continue to work the traditional gas way. In either case, issue a
7099 warning. */
7100 intel_parser.op_modifier &= ~was_offset;
64a0c779 7101 }
a724f0f4 7102 else
64e74474 7103 strcat (intel_parser.disp, "[");
a724f0f4
JB		 7104
7105 /* Add a '+' to the displacement string if necessary. */
7106 if (*intel_parser.disp != '\0'
7107 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7108 strcat (intel_parser.disp, "+");
64a0c779 7109
a724f0f4
JB		 7110 if (intel_expr ()
7111 && (len = intel_parser.op_string - start - 1,
7112 intel_match_token (']')))
64a0c779 7113 {
a724f0f4
JB		 7114 /* Preserve brackets when the operand is an offset expression. */
7115 if (intel_parser.in_offset)
7116 strcat (intel_parser.disp, "]");
7117 else
7118 {
7119 --intel_parser.in_bracket;
7120 if (i.base_reg || i.index_reg)
7121 intel_parser.is_mem = 1;
7122 if (!intel_parser.is_mem)
7123 {
7124 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7125 /* Defer the warning until all of the operand was parsed. */
7126 intel_parser.is_mem = -1;
7127 else if (!quiet_warnings)
7128 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
7129 }
7130 }
7131 intel_parser.op_modifier |= was_offset;
64a0c779 7132
a724f0f4 7133 return 1;
64a0c779 7134 }
a724f0f4 7135 return 0;
64a0c779
DN		 7136}
7137
7138/* e10 e11 e10'
7139
7140 e10' [ expr ] e10'
b77a7acd 7141 | Empty */
64a0c779
DN		 7142static int
7143intel_e10 ()
7144{
a724f0f4
JB		 7145 if (!intel_e11 ())
7146 return 0;
64a0c779 7147
a724f0f4 7148 while (cur_token.code == '[')
64a0c779 7149 {
a724f0f4 7150 if (!intel_bracket_expr ())
21d6c4af 7151 return 0;
64a0c779
DN		 7152 }
7153
a724f0f4 7154 return 1;
64a0c779
DN		 7155}
7156
64a0c779 7157/* e11 ( expr )
b77a7acd 7158 | [ expr ]
64a0c779
DN		 7159 | BYTE
7160 | WORD
7161 | DWORD
9306ca4a 7162 | FWORD
64a0c779 7163 | QWORD
9306ca4a
JB		 7164 | TBYTE
7165 | OWORD
7166 | XMMWORD
4a1805b1 7167 | $
64a0c779
DN		 7168 | .
7169 | register
7170 | id
7171 | constant */
7172static int
7173intel_e11 ()
7174{
a724f0f4 7175 switch (cur_token.code)
64a0c779 7176 {
a724f0f4
JB		 7177 /* e11 ( expr ) */
7178 case '(':
64a0c779
DN		 7179 intel_match_token ('(');
7180 strcat (intel_parser.disp, "(");
7181
7182 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7183 {
7184 strcat (intel_parser.disp, ")");
7185 return 1;
7186 }
a724f0f4 7187 return 0;
4a1805b1 7188
a724f0f4
JB		 7189 /* e11 [ expr ] */
7190 case '[':
a724f0f4 7191 return intel_bracket_expr ();
64a0c779 7192
a724f0f4
JB		 7193 /* e11 $
7194 | . */
7195 case '.':
64a0c779
DN		 7196 strcat (intel_parser.disp, cur_token.str);
7197 intel_match_token (cur_token.code);
21d6c4af
DN		 7198
7199 /* Mark as a memory operand only if it's not already known to be an
7200 offset expression. */
a724f0f4 7201 if (!intel_parser.in_offset)
21d6c4af 7202 intel_parser.is_mem = 1;
64a0c779
DN		 7203
7204 return 1;
64a0c779 7205
a724f0f4
JB		 7206 /* e11 register */
7207 case T_REG:
7208 {
7209 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7210
a724f0f4 7211 intel_match_token (T_REG);
64a0c779 7212
a724f0f4
JB		 7213 /* Check for segment change. */
7214 if (cur_token.code == ':')
7215 {
7216 if (!(reg->reg_type & (SReg2 | SReg3)))
7217 {
7218 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
7219 return 0;
7220 }
7221 else if (i.seg[i.mem_operands])
7222 as_warn (_("Extra segment override ignored"));
7223 else
7224 {
7225 if (!intel_parser.in_offset)
7226 intel_parser.is_mem = 1;
7227 switch (reg->reg_num)
7228 {
7229 case 0:
7230 i.seg[i.mem_operands] = &es;
7231 break;
7232 case 1:
7233 i.seg[i.mem_operands] = &cs;
7234 break;
7235 case 2:
7236 i.seg[i.mem_operands] = &ss;
7237 break;
7238 case 3:
7239 i.seg[i.mem_operands] = &ds;
7240 break;
7241 case 4:
7242 i.seg[i.mem_operands] = &fs;
7243 break;
7244 case 5:
7245 i.seg[i.mem_operands] = &gs;
7246 break;
7247 }
7248 }
7249 }
64a0c779 7250
a724f0f4
JB		 7251 /* Not a segment register. Check for register scaling. */
7252 else if (cur_token.code == '*')
7253 {
7254 if (!intel_parser.in_bracket)
7255 {
7256 as_bad (_("Register scaling only allowed in memory operands"));
7257 return 0;
7258 }
64a0c779 7259
a724f0f4
JB		 7260 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7261 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7262 else if (i.index_reg)
7263 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 7264
a724f0f4
JB		 7265 /* What follows must be a valid scale. */
7266 intel_match_token ('*');
7267 i.index_reg = reg;
7268 i.types[this_operand] |= BaseIndex;
64a0c779 7269
a724f0f4
JB		 7270 /* Set the scale after setting the register (otherwise,
7271 i386_scale will complain) */
7272 if (cur_token.code == '+' || cur_token.code == '-')
7273 {
7274 char *str, sign = cur_token.code;
7275 intel_match_token (cur_token.code);
7276 if (cur_token.code != T_CONST)
7277 {
7278 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7279 cur_token.str);
7280 return 0;
7281 }
7282 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7283 strcpy (str + 1, cur_token.str);
7284 *str = sign;
7285 if (!i386_scale (str))
7286 return 0;
7287 free (str);
7288 }
7289 else if (!i386_scale (cur_token.str))
64a0c779 7290 return 0;
a724f0f4
JB		 7291 intel_match_token (cur_token.code);
7292 }
64a0c779 7293
a724f0f4
JB		 7294 /* No scaling. If this is a memory operand, the register is either a
7295 base register (first occurrence) or an index register (second
7296 occurrence). */
7b0441f6 7297 else if (intel_parser.in_bracket)
a724f0f4 7298 {
64a0c779 7299
a724f0f4
JB		 7300 if (!i.base_reg)
7301 i.base_reg = reg;
7302 else if (!i.index_reg)
7303 i.index_reg = reg;
7304 else
7305 {
7306 as_bad (_("Too many register references in memory operand"));
7307 return 0;
7308 }
64a0c779 7309
a724f0f4
JB		 7310 i.types[this_operand] |= BaseIndex;
7311 }
4a1805b1 7312
4d1bb795
JB		 7313 /* It's neither base nor index. */
7314 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 7315 {
7316 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7317 i.op[this_operand].regs = reg;
7318 i.reg_operands++;
7319 }
7320 else
7321 {
7322 as_bad (_("Invalid use of register"));
7323 return 0;
7324 }
64a0c779 7325
a724f0f4
JB		 7326 /* Since registers are not part of the displacement string (except
7327 when we're parsing offset operands), we may need to remove any
7328 preceding '+' from the displacement string. */
7329 if (*intel_parser.disp != '\0'
7330 && !intel_parser.in_offset)
7331 {
7332 char *s = intel_parser.disp;
7333 s += strlen (s) - 1;
7334 if (*s == '+')
7335 *s = '\0';
7336 }
4a1805b1 7337
a724f0f4
JB		 7338 return 1;
7339 }
7340
7341 /* e11 BYTE
7342 | WORD
7343 | DWORD
7344 | FWORD
7345 | QWORD
7346 | TBYTE
7347 | OWORD
7348 | XMMWORD */
7349 case T_BYTE:
7350 case T_WORD:
7351 case T_DWORD:
7352 case T_FWORD:
7353 case T_QWORD:
7354 case T_TBYTE:
7355 case T_XMMWORD:
7356 intel_match_token (cur_token.code);
64a0c779 7357
a724f0f4
JB		 7358 if (cur_token.code == T_PTR)
7359 return 1;
7360
7361 /* It must have been an identifier. */
7362 intel_putback_token ();
7363 cur_token.code = T_ID;
7364 /* FALLTHRU */
7365
7366 /* e11 id
7367 | constant */
7368 case T_ID:
7369 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 7370 {
7371 symbolS *symbolP;
7372
a724f0f4
JB		 7373 /* The identifier represents a memory reference only if it's not
7374 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 7375 symbolP = symbol_find(cur_token.str);
7376 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7377 intel_parser.is_mem = 1;
7378 }
a724f0f4 7379 /* FALLTHRU */
64a0c779 7380
a724f0f4
JB		 7381 case T_CONST:
7382 case '-':
7383 case '+':
7384 {
7385 char *save_str, sign = 0;
64a0c779 7386
a724f0f4
JB		 7387 /* Allow constants that start with `+' or `-'. */
7388 if (cur_token.code == '-' || cur_token.code == '+')
7389 {
7390 sign = cur_token.code;
7391 intel_match_token (cur_token.code);
7392 if (cur_token.code != T_CONST)
7393 {
7394 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7395 cur_token.str);
7396 return 0;
7397 }
7398 }
64a0c779 7399
a724f0f4
JB		 7400 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7401 strcpy (save_str + !!sign, cur_token.str);
7402 if (sign)
7403 *save_str = sign;
64a0c779 7404
a724f0f4
JB		 7405 /* Get the next token to check for register scaling. */
7406 intel_match_token (cur_token.code);
64a0c779 7407
a724f0f4
JB		 7408 /* Check if this constant is a scaling factor for an index register. */
7409 if (cur_token.code == '*')
7410 {
7411 if (intel_match_token ('*') && cur_token.code == T_REG)
7412 {
7413 const reg_entry *reg = cur_token.reg;
7414
7415 if (!intel_parser.in_bracket)
7416 {
7417 as_bad (_("Register scaling only allowed in memory operands"));
7418 return 0;
7419 }
7420
7421 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
7422 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7423 else if (i.index_reg)
7424 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7425
7426 /* The constant is followed by `* reg', so it must be
7427 a valid scale. */
7428 i.index_reg = reg;
7429 i.types[this_operand] |= BaseIndex;
7430
7431 /* Set the scale after setting the register (otherwise,
7432 i386_scale will complain) */
7433 if (!i386_scale (save_str))
64a0c779 7434 return 0;
a724f0f4
JB		 7435 intel_match_token (T_REG);
7436
7437 /* Since registers are not part of the displacement
7438 string, we may need to remove any preceding '+' from
7439 the displacement string. */
7440 if (*intel_parser.disp != '\0')
7441 {
7442 char *s = intel_parser.disp;
7443 s += strlen (s) - 1;
7444 if (*s == '+')
7445 *s = '\0';
7446 }
7447
7448 free (save_str);
7449
7450 return 1;
7451 }
64a0c779 7452
a724f0f4
JB		 7453 /* The constant was not used for register scaling. Since we have
7454 already consumed the token following `*' we now need to put it
7455 back in the stream. */
64a0c779 7456 intel_putback_token ();
a724f0f4 7457 }
64a0c779 7458
a724f0f4
JB		 7459 /* Add the constant to the displacement string. */
7460 strcat (intel_parser.disp, save_str);
7461 free (save_str);
64a0c779 7462
a724f0f4
JB		 7463 return 1;
7464 }
64a0c779
DN		 7465 }
7466
64a0c779
DN		 7467 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7468 return 0;
7469}
7470
64a0c779
DN		 7471/* Match the given token against cur_token. If they match, read the next
7472 token from the operand string. */
7473static int
7474intel_match_token (code)
e5cb08ac 7475 int code;
64a0c779
DN		 7476{
7477 if (cur_token.code == code)
7478 {
7479 intel_get_token ();
7480 return 1;
7481 }
7482 else
7483 {
0477af35 7484 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 7485 return 0;
7486 }
7487}
7488
64a0c779
DN		 7489/* Read a new token from intel_parser.op_string and store it in cur_token. */
7490static void
7491intel_get_token ()
7492{
7493 char *end_op;
7494 const reg_entry *reg;
7495 struct intel_token new_token;
7496
7497 new_token.code = T_NIL;
7498 new_token.reg = NULL;
7499 new_token.str = NULL;
7500
4a1805b1 7501 /* Free the memory allocated to the previous token and move
64a0c779
DN		 7502 cur_token to prev_token. */
7503 if (prev_token.str)
7504 free (prev_token.str);
7505
7506 prev_token = cur_token;
7507
7508 /* Skip whitespace. */
7509 while (is_space_char (*intel_parser.op_string))
7510 intel_parser.op_string++;
7511
7512 /* Return an empty token if we find nothing else on the line. */
7513 if (*intel_parser.op_string == '\0')
7514 {
7515 cur_token = new_token;
7516 return;
7517 }
7518
7519 /* The new token cannot be larger than the remainder of the operand
7520 string. */
a724f0f4 7521 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7522 new_token.str[0] = '\0';
7523
7524 if (strchr ("0123456789", *intel_parser.op_string))
7525 {
7526 char *p = new_token.str;
7527 char *q = intel_parser.op_string;
7528 new_token.code = T_CONST;
7529
7530 /* Allow any kind of identifier char to encompass floating point and
7531 hexadecimal numbers. */
7532 while (is_identifier_char (*q))
7533 *p++ = *q++;
7534 *p = '\0';
7535
7536 /* Recognize special symbol names [0-9][bf]. */
7537 if (strlen (intel_parser.op_string) == 2
4a1805b1 7538 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7539 || intel_parser.op_string[1] == 'f'))
7540 new_token.code = T_ID;
7541 }
7542
4d1bb795 7543 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7544 {
4d1bb795
JB		 7545 size_t len = end_op - intel_parser.op_string;
7546
64a0c779
DN		 7547 new_token.code = T_REG;
7548 new_token.reg = reg;
7549
4d1bb795
JB		 7550 memcpy (new_token.str, intel_parser.op_string, len);
7551 new_token.str[len] = '\0';
64a0c779
DN		 7552 }
7553
7554 else if (is_identifier_char (*intel_parser.op_string))
7555 {
7556 char *p = new_token.str;
7557 char *q = intel_parser.op_string;
7558
7559 /* A '.' or '$' followed by an identifier char is an identifier.
7560 Otherwise, it's operator '.' followed by an expression. */
7561 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7562 {
9306ca4a
JB		 7563 new_token.code = '.';
7564 new_token.str[0] = '.';
64a0c779
DN		 7565 new_token.str[1] = '\0';
7566 }
7567 else
7568 {
7569 while (is_identifier_char (*q) || *q == '@')
7570 *p++ = *q++;
7571 *p = '\0';
7572
9306ca4a
JB		 7573 if (strcasecmp (new_token.str, "NOT") == 0)
7574 new_token.code = '~';
7575
7576 else if (strcasecmp (new_token.str, "MOD") == 0)
7577 new_token.code = '%';
7578
7579 else if (strcasecmp (new_token.str, "AND") == 0)
7580 new_token.code = '&';
7581
7582 else if (strcasecmp (new_token.str, "OR") == 0)
7583 new_token.code = '|';
7584
7585 else if (strcasecmp (new_token.str, "XOR") == 0)
7586 new_token.code = '^';
7587
7588 else if (strcasecmp (new_token.str, "SHL") == 0)
7589 new_token.code = T_SHL;
7590
7591 else if (strcasecmp (new_token.str, "SHR") == 0)
7592 new_token.code = T_SHR;
7593
7594 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7595 new_token.code = T_BYTE;
7596
7597 else if (strcasecmp (new_token.str, "WORD") == 0)
7598 new_token.code = T_WORD;
7599
7600 else if (strcasecmp (new_token.str, "DWORD") == 0)
7601 new_token.code = T_DWORD;
7602
9306ca4a
JB		 7603 else if (strcasecmp (new_token.str, "FWORD") == 0)
7604 new_token.code = T_FWORD;
7605
64a0c779
DN		 7606 else if (strcasecmp (new_token.str, "QWORD") == 0)
7607 new_token.code = T_QWORD;
7608
9306ca4a
JB		 7609 else if (strcasecmp (new_token.str, "TBYTE") == 0
7610 /* XXX remove (gcc still uses it) */
7611 || strcasecmp (new_token.str, "XWORD") == 0)
7612 new_token.code = T_TBYTE;
7613
7614 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7615 || strcasecmp (new_token.str, "OWORD") == 0)
7616 new_token.code = T_XMMWORD;
64a0c779
DN		 7617
7618 else if (strcasecmp (new_token.str, "PTR") == 0)
7619 new_token.code = T_PTR;
7620
7621 else if (strcasecmp (new_token.str, "SHORT") == 0)
7622 new_token.code = T_SHORT;
7623
7624 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7625 {
7626 new_token.code = T_OFFSET;
7627
7628 /* ??? This is not mentioned in the MASM grammar but gcc
7629 makes use of it with -mintel-syntax. OFFSET may be
7630 followed by FLAT: */
7631 if (strncasecmp (q, " FLAT:", 6) == 0)
7632 strcat (new_token.str, " FLAT:");
7633 }
7634
7635 /* ??? This is not mentioned in the MASM grammar. */
7636 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7637 {
7638 new_token.code = T_OFFSET;
7639 if (*q == ':')
7640 strcat (new_token.str, ":");
7641 else
7642 as_bad (_("`:' expected"));
7643 }
64a0c779
DN		 7644
7645 else
7646 new_token.code = T_ID;
7647 }
7648 }
7649
9306ca4a
JB		 7650 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7651 {
7652 new_token.code = *intel_parser.op_string;
7653 new_token.str[0] = *intel_parser.op_string;
7654 new_token.str[1] = '\0';
7655 }
7656
7657 else if (strchr ("<>", *intel_parser.op_string)
7658 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7659 {
7660 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7661 new_token.str[0] = *intel_parser.op_string;
7662 new_token.str[1] = *intel_parser.op_string;
7663 new_token.str[2] = '\0';
7664 }
7665
64a0c779 7666 else
0477af35 7667 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7668
7669 intel_parser.op_string += strlen (new_token.str);
7670 cur_token = new_token;
7671}
7672
64a0c779
DN		 7673/* Put cur_token back into the token stream and make cur_token point to
7674 prev_token. */
7675static void
7676intel_putback_token ()
7677{
a724f0f4
JB		 7678 if (cur_token.code != T_NIL)
7679 {
7680 intel_parser.op_string -= strlen (cur_token.str);
7681 free (cur_token.str);
7682 }
64a0c779 7683 cur_token = prev_token;
4a1805b1 7684
64a0c779
DN		 7685 /* Forget prev_token. */
7686 prev_token.code = T_NIL;
7687 prev_token.reg = NULL;
7688 prev_token.str = NULL;
7689}
54cfded0 7690
a4447b93 7691int
1df69f4f 7692tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 7693{
7694 unsigned int regnum;
7695 unsigned int regnames_count;
089dfecd 7696 static const char *const regnames_32[] =
54cfded0 7697 {
a4447b93
RH		 7698 "eax", "ecx", "edx", "ebx",
7699 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7700 "eip", "eflags", NULL,
7701 "st0", "st1", "st2", "st3",
7702 "st4", "st5", "st6", "st7",
7703 NULL, NULL,
7704 "xmm0", "xmm1", "xmm2", "xmm3",
7705 "xmm4", "xmm5", "xmm6", "xmm7",
7706 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7707 "mm4", "mm5", "mm6", "mm7",
7708 "fcw", "fsw", "mxcsr",
7709 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7710 "tr", "ldtr"
54cfded0 7711 };
089dfecd 7712 static const char *const regnames_64[] =
54cfded0 7713 {
089dfecd
JB		 7714 "rax", "rdx", "rcx", "rbx",
7715 "rsi", "rdi", "rbp", "rsp",
7716 "r8", "r9", "r10", "r11",
54cfded0 7717 "r12", "r13", "r14", "r15",
089dfecd
JB		 7718 "rip",
7719 "xmm0", "xmm1", "xmm2", "xmm3",
7720 "xmm4", "xmm5", "xmm6", "xmm7",
7721 "xmm8", "xmm9", "xmm10", "xmm11",
7722 "xmm12", "xmm13", "xmm14", "xmm15",
7723 "st0", "st1", "st2", "st3",
7724 "st4", "st5", "st6", "st7",
7725 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7726 "mm4", "mm5", "mm6", "mm7",
7727 "rflags",
7728 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7729 "fs.base", "gs.base", NULL, NULL,
7730 "tr", "ldtr",
7731 "mxcsr", "fcw", "fsw"
54cfded0 7732 };
089dfecd 7733 const char *const *regnames;
54cfded0
AM		 7734
7735 if (flag_code == CODE_64BIT)
7736 {
7737 regnames = regnames_64;
0cea6190 7738 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7739 }
7740 else
7741 {
7742 regnames = regnames_32;
0cea6190 7743 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7744 }
7745
7746 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7747 if (regnames[regnum] != NULL
7748 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7749 return regnum;
7750
54cfded0
AM		 7751 return -1;
7752}
7753
7754void
7755tc_x86_frame_initial_instructions (void)
7756{
a4447b93
RH		 7757 static unsigned int sp_regno;
7758
7759 if (!sp_regno)
7760 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7761 ? "rsp" : "esp");
7762
7763 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7764 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7765}
d2b2c203
DJ		 7766
7767int
7768i386_elf_section_type (const char *str, size_t len)
7769{
7770 if (flag_code == CODE_64BIT
7771 && len == sizeof ("unwind") - 1
7772 && strncmp (str, "unwind", 6) == 0)
7773 return SHT_X86_64_UNWIND;
7774
7775 return -1;
7776}
bb41ade5
AM		 7777
7778#ifdef TE_PE
7779void
7780tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7781{
7782 expressionS expr;
7783
7784 expr.X_op = O_secrel;
7785 expr.X_add_symbol = symbol;
7786 expr.X_add_number = 0;
7787 emit_expr (&expr, size);
7788}
7789#endif
3b22753a
L		 7790
7791#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7792/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7793
7794int
7795x86_64_section_letter (int letter, char **ptr_msg)
7796{
7797 if (flag_code == CODE_64BIT)
7798 {
7799 if (letter == 'l')
7800 return SHF_X86_64_LARGE;
7801
7802 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7803 }
3b22753a 7804 else
64e74474 7805 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7806 return -1;
7807}
7808
7809int
7810x86_64_section_word (char *str, size_t len)
7811{
8620418b 7812 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 7813 return SHF_X86_64_LARGE;
7814
7815 return -1;
7816}
7817
7818static void
7819handle_large_common (int small ATTRIBUTE_UNUSED)
7820{
7821 if (flag_code != CODE_64BIT)
7822 {
7823 s_comm_internal (0, elf_common_parse);
7824 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7825 }
7826 else
7827 {
7828 static segT lbss_section;
7829 asection *saved_com_section_ptr = elf_com_section_ptr;
7830 asection *saved_bss_section = bss_section;
7831
7832 if (lbss_section == NULL)
7833 {
7834 flagword applicable;
7835 segT seg = now_seg;
7836 subsegT subseg = now_subseg;
7837
7838 /* The .lbss section is for local .largecomm symbols. */
7839 lbss_section = subseg_new (".lbss", 0);
7840 applicable = bfd_applicable_section_flags (stdoutput);
7841 bfd_set_section_flags (stdoutput, lbss_section,
7842 applicable & SEC_ALLOC);
7843 seg_info (lbss_section)->bss = 1;
7844
7845 subseg_set (seg, subseg);
7846 }
7847
7848 elf_com_section_ptr = &_bfd_elf_large_com_section;
7849 bss_section = lbss_section;
7850
7851 s_comm_internal (0, elf_common_parse);
7852
7853 elf_com_section_ptr = saved_com_section_ptr;
7854 bss_section = saved_bss_section;
7855 }
7856}
7857#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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