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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
67a4f2b7 3 2000, 2001, 2002, 2003, 2004, 2005, 2006
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
d182319b 83static void signed_cons PARAMS ((int));
29b0f896
AM		 84static char *output_invalid PARAMS ((int c));
85static int i386_operand PARAMS ((char *operand_string));
86static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
87static const reg_entry *parse_register PARAMS ((char *reg_string,
88 char **end_op));
89static char *parse_insn PARAMS ((char *, char *));
90static char *parse_operands PARAMS ((char *, const char *));
91static void swap_operands PARAMS ((void));
050dfa73 92static void swap_imm_operands PARAMS ((void));
29b0f896
AM		 93static void optimize_imm PARAMS ((void));
94static void optimize_disp PARAMS ((void));
95static int match_template PARAMS ((void));
96static int check_string PARAMS ((void));
97static int process_suffix PARAMS ((void));
98static int check_byte_reg PARAMS ((void));
99static int check_long_reg PARAMS ((void));
100static int check_qword_reg PARAMS ((void));
101static int check_word_reg PARAMS ((void));
102static int finalize_imm PARAMS ((void));
103static int process_operands PARAMS ((void));
104static const seg_entry *build_modrm_byte PARAMS ((void));
105static void output_insn PARAMS ((void));
106static void output_branch PARAMS ((void));
107static void output_jump PARAMS ((void));
108static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 109static void output_imm PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
111static void output_disp PARAMS ((fragS *insn_start_frag,
112 offsetT insn_start_off));
29b0f896
AM		 113#ifndef I386COFF
114static void s_bss PARAMS ((int));
252b5132 115#endif
17d4e2a2
L		 116#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
117static void handle_large_common (int small ATTRIBUTE_UNUSED);
118#endif
252b5132 119
a847613f 120static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 121
252b5132 122/* 'md_assemble ()' gathers together information and puts it into a
47926f60 123 i386_insn. */
252b5132 124
520dc8e8
AM		 125union i386_op
126 {
127 expressionS *disps;
128 expressionS *imms;
129 const reg_entry *regs;
130 };
131
252b5132
RH		 132struct _i386_insn
133 {
47926f60 134 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 135 template tm;
136
137 /* SUFFIX holds the instruction mnemonic suffix if given.
138 (e.g. 'l' for 'movl') */
139 char suffix;
140
47926f60 141 /* OPERANDS gives the number of given operands. */
252b5132
RH		 142 unsigned int operands;
143
144 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
145 of given register, displacement, memory operands and immediate
47926f60 146 operands. */
252b5132
RH		 147 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
148
149 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 150 use OP[i] for the corresponding operand. */
252b5132
RH		 151 unsigned int types[MAX_OPERANDS];
152
520dc8e8
AM		 153 /* Displacement expression, immediate expression, or register for each
154 operand. */
155 union i386_op op[MAX_OPERANDS];
252b5132 156
3e73aa7c
JH		 157 /* Flags for operands. */
158 unsigned int flags[MAX_OPERANDS];
159#define Operand_PCrel 1
160
252b5132 161 /* Relocation type for operand */
f86103b7 162 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 163
252b5132
RH		 164 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
165 the base index byte below. */
166 const reg_entry *base_reg;
167 const reg_entry *index_reg;
168 unsigned int log2_scale_factor;
169
170 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 171 explicit segment overrides are given. */
ce8a8b2f 172 const seg_entry *seg[2];
252b5132
RH		 173
174 /* PREFIX holds all the given prefix opcodes (usually null).
175 PREFIXES is the number of prefix opcodes. */
176 unsigned int prefixes;
177 unsigned char prefix[MAX_PREFIXES];
178
179 /* RM and SIB are the modrm byte and the sib byte where the
180 addressing modes of this insn are encoded. */
181
182 modrm_byte rm;
3e73aa7c 183 rex_byte rex;
252b5132
RH		 184 sib_byte sib;
185 };
186
187typedef struct _i386_insn i386_insn;
188
189/* List of chars besides those in app.c:symbol_chars that can start an
190 operand. Used to prevent the scrubber eating vital white-space. */
32137342 191const char extra_symbol_chars[] = "*%-(["
252b5132 192#ifdef LEX_AT
32137342
NC		 193 "@"
194#endif
195#ifdef LEX_QM
196 "?"
252b5132 197#endif
32137342 198 ;
252b5132 199
29b0f896
AM		 200#if (defined (TE_I386AIX) \
201 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 202 && !defined (TE_GNU) \
29b0f896 203 && !defined (TE_LINUX) \
32137342 204 && !defined (TE_NETWARE) \
29b0f896
AM		 205 && !defined (TE_FreeBSD) \
206 && !defined (TE_NetBSD)))
252b5132 207/* This array holds the chars that always start a comment. If the
b3b91714
AM		 208 pre-processor is disabled, these aren't very useful. The option
209 --divide will remove '/' from this list. */
210const char *i386_comment_chars = "#/";
211#define SVR4_COMMENT_CHARS 1
252b5132 212#define PREFIX_SEPARATOR '\\'
252b5132 213
b3b91714
AM		 214#else
215const char *i386_comment_chars = "#";
216#define PREFIX_SEPARATOR '/'
217#endif
218
252b5132
RH		 219/* This array holds the chars that only start a comment at the beginning of
220 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 221 .line and .file directives will appear in the pre-processed output.
222 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 223 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 224 #NO_APP at the beginning of its output.
225 Also note that comments started like this one will always work if
252b5132 226 '/' isn't otherwise defined. */
b3b91714 227const char line_comment_chars[] = "#/";
252b5132 228
63a0b638 229const char line_separator_chars[] = ";";
252b5132 230
ce8a8b2f
AM		 231/* Chars that can be used to separate mant from exp in floating point
232 nums. */
252b5132
RH		 233const char EXP_CHARS[] = "eE";
234
ce8a8b2f
AM		 235/* Chars that mean this number is a floating point constant
236 As in 0f12.456
237 or 0d1.2345e12. */
252b5132
RH		 238const char FLT_CHARS[] = "fFdDxX";
239
ce8a8b2f 240/* Tables for lexical analysis. */
252b5132
RH		 241static char mnemonic_chars[256];
242static char register_chars[256];
243static char operand_chars[256];
244static char identifier_chars[256];
245static char digit_chars[256];
246
ce8a8b2f 247/* Lexical macros. */
252b5132
RH		 248#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
249#define is_operand_char(x) (operand_chars[(unsigned char) x])
250#define is_register_char(x) (register_chars[(unsigned char) x])
251#define is_space_char(x) ((x) == ' ')
252#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
253#define is_digit_char(x) (digit_chars[(unsigned char) x])
254
0234cb7c 255/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 256static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
257
258/* md_assemble() always leaves the strings it's passed unaltered. To
259 effect this we maintain a stack of saved characters that we've smashed
260 with '\0's (indicating end of strings for various sub-fields of the
47926f60 261 assembler instruction). */
252b5132 262static char save_stack[32];
ce8a8b2f 263static char *save_stack_p;
252b5132
RH		 264#define END_STRING_AND_SAVE(s) \
265 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
266#define RESTORE_END_STRING(s) \
267 do { *(s) = *--save_stack_p; } while (0)
268
47926f60 269/* The instruction we're assembling. */
252b5132
RH		 270static i386_insn i;
271
272/* Possible templates for current insn. */
273static const templates *current_templates;
274
47926f60 275/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 276static expressionS disp_expressions[2], im_expressions[2];
277
47926f60
KH		 278/* Current operand we are working on. */
279static int this_operand;
252b5132 280
3e73aa7c
JH		 281/* We support four different modes. FLAG_CODE variable is used to distinguish
282 these. */
283
284enum flag_code {
285 CODE_32BIT,
286 CODE_16BIT,
287 CODE_64BIT };
f3c180ae 288#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 289
290static enum flag_code flag_code;
4fa24527 291static unsigned int object_64bit;
3e73aa7c
JH		 292static int use_rela_relocations = 0;
293
294/* The names used to print error messages. */
b77a7acd 295static const char *flag_code_names[] =
3e73aa7c
JH		 296 {
297 "32",
298 "16",
299 "64"
300 };
252b5132 301
47926f60
KH		 302/* 1 for intel syntax,
303 0 if att syntax. */
304static int intel_syntax = 0;
252b5132 305
47926f60
KH		 306/* 1 if register prefix % not required. */
307static int allow_naked_reg = 0;
252b5132 308
47926f60
KH		 309/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
310 leave, push, and pop instructions so that gcc has the same stack
311 frame as in 32 bit mode. */
312static char stackop_size = '\0';
eecb386c 313
12b55ccc
L		 314/* Non-zero to optimize code alignment. */
315int optimize_align_code = 1;
316
47926f60
KH		 317/* Non-zero to quieten some warnings. */
318static int quiet_warnings = 0;
a38cf1db 319
47926f60
KH		 320/* CPU name. */
321static const char *cpu_arch_name = NULL;
5c6af06e 322static const char *cpu_sub_arch_name = NULL;
a38cf1db 323
47926f60 324/* CPU feature flags. */
29b0f896 325static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 326
ccc9c027
L		 327/* If we have selected a cpu we are generating instructions for. */
328static int cpu_arch_tune_set = 0;
329
9103f4f4
L		 330/* Cpu we are generating instructions for. */
331static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
332
333/* CPU feature flags of cpu we are generating instructions for. */
334static unsigned int cpu_arch_tune_flags = 0;
335
ccc9c027
L		 336/* CPU instruction set architecture used. */
337static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
338
9103f4f4
L		 339/* CPU feature flags of instruction set architecture used. */
340static unsigned int cpu_arch_isa_flags = 0;
341
fddf5b5b
AM		 342/* If set, conditional jumps are not automatically promoted to handle
343 larger than a byte offset. */
344static unsigned int no_cond_jump_promotion = 0;
345
29b0f896 346/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 347static symbolS *GOT_symbol;
29b0f896 348
a4447b93
RH		 349/* The dwarf2 return column, adjusted for 32 or 64 bit. */
350unsigned int x86_dwarf2_return_column;
351
352/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
353int x86_cie_data_alignment;
354
252b5132 355/* Interface to relax_segment.
fddf5b5b
AM		 356 There are 3 major relax states for 386 jump insns because the
357 different types of jumps add different sizes to frags when we're
358 figuring out what sort of jump to choose to reach a given label. */
252b5132 359
47926f60 360/* Types. */
93c2a809
AM		 361#define UNCOND_JUMP 0
362#define COND_JUMP 1
363#define COND_JUMP86 2
fddf5b5b 364
47926f60 365/* Sizes. */
252b5132
RH		 366#define CODE16 1
367#define SMALL 0
29b0f896 368#define SMALL16 (SMALL | CODE16)
252b5132 369#define BIG 2
29b0f896 370#define BIG16 (BIG | CODE16)
252b5132
RH		 371
372#ifndef INLINE
373#ifdef __GNUC__
374#define INLINE __inline__
375#else
376#define INLINE
377#endif
378#endif
379
fddf5b5b
AM		 380#define ENCODE_RELAX_STATE(type, size) \
381 ((relax_substateT) (((type) << 2) | (size)))
382#define TYPE_FROM_RELAX_STATE(s) \
383 ((s) >> 2)
384#define DISP_SIZE_FROM_RELAX_STATE(s) \
385 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 386
387/* This table is used by relax_frag to promote short jumps to long
388 ones where necessary. SMALL (short) jumps may be promoted to BIG
389 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
390 don't allow a short jump in a 32 bit code segment to be promoted to
391 a 16 bit offset jump because it's slower (requires data size
392 prefix), and doesn't work, unless the destination is in the bottom
393 64k of the code segment (The top 16 bits of eip are zeroed). */
394
395const relax_typeS md_relax_table[] =
396{
24eab124
AM		 397 /* The fields are:
398 1) most positive reach of this state,
399 2) most negative reach of this state,
93c2a809 400 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 401 4) which index into the table to try if we can't fit into this one. */
252b5132 402
fddf5b5b 403 /* UNCOND_JUMP states. */
93c2a809
AM		 404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
406 /* dword jmp adds 4 bytes to frag:
407 0 extra opcode bytes, 4 displacement bytes. */
252b5132 408 {0, 0, 4, 0},
93c2a809
AM		 409 /* word jmp adds 2 byte2 to frag:
410 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 411 {0, 0, 2, 0},
412
93c2a809
AM		 413 /* COND_JUMP states. */
414 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
415 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
416 /* dword conditionals adds 5 bytes to frag:
417 1 extra opcode byte, 4 displacement bytes. */
418 {0, 0, 5, 0},
fddf5b5b 419 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 420 1 extra opcode byte, 2 displacement bytes. */
421 {0, 0, 3, 0},
422
423 /* COND_JUMP86 states. */
424 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
425 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
426 /* dword conditionals adds 5 bytes to frag:
427 1 extra opcode byte, 4 displacement bytes. */
428 {0, 0, 5, 0},
429 /* word conditionals add 4 bytes to frag:
430 1 displacement byte and a 3 byte long branch insn. */
431 {0, 0, 4, 0}
252b5132
RH		 432};
433
9103f4f4
L		 434static const arch_entry cpu_arch[] =
435{
436 {"generic32", PROCESSOR_GENERIC32,
d32cad65 437 Cpu186|Cpu286|Cpu386},
9103f4f4 438 {"generic64", PROCESSOR_GENERIC64,
d32cad65 439 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 440 |CpuMMX2|CpuSSE|CpuSSE2},
441 {"i8086", PROCESSOR_UNKNOWN,
d32cad65 442 0},
9103f4f4 443 {"i186", PROCESSOR_UNKNOWN,
d32cad65 444 Cpu186},
9103f4f4 445 {"i286", PROCESSOR_UNKNOWN,
d32cad65 446 Cpu186|Cpu286},
9103f4f4 447 {"i386", PROCESSOR_GENERIC32,
d32cad65 448 Cpu186|Cpu286|Cpu386},
9103f4f4 449 {"i486", PROCESSOR_I486,
d32cad65 450 Cpu186|Cpu286|Cpu386|Cpu486},
9103f4f4 451 {"i586", PROCESSOR_PENTIUM,
d32cad65 452 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 453 {"i686", PROCESSOR_PENTIUMPRO,
d32cad65 454 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 455 {"pentium", PROCESSOR_PENTIUM,
d32cad65 456 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 457 {"pentiumpro",PROCESSOR_PENTIUMPRO,
d32cad65 458 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 459 {"pentiumii", PROCESSOR_PENTIUMPRO,
d32cad65 460 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
9103f4f4 461 {"pentiumiii",PROCESSOR_PENTIUMPRO,
d32cad65 462 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
9103f4f4 463 {"pentium4", PROCESSOR_PENTIUM4,
d32cad65 464 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 465 |CpuMMX2|CpuSSE|CpuSSE2},
466 {"prescott", PROCESSOR_NOCONA,
d32cad65 467 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 468 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
469 {"nocona", PROCESSOR_NOCONA,
d32cad65 470 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 471 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
472 {"yonah", PROCESSOR_YONAH,
d32cad65 473 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 474 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
475 {"merom", PROCESSOR_MEROM,
d32cad65 476 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 477 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuMNI},
478 {"k6", PROCESSOR_K6,
d32cad65 479 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
9103f4f4 480 {"k6_2", PROCESSOR_K6,
d32cad65 481 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
9103f4f4 482 {"athlon", PROCESSOR_ATHLON,
d32cad65 483 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 484 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
485 {"sledgehammer", PROCESSOR_K8,
d32cad65 486 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 487 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
488 {"opteron", PROCESSOR_K8,
d32cad65 489 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 490 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
491 {"k8", PROCESSOR_K8,
d32cad65 492 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4 493 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
050dfa73 494 {"amdfam10", PROCESSOR_AMDFAM10,
d32cad65
L		 495 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
496 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
497 |CpuABM},
9103f4f4
L		 498 {".mmx", PROCESSOR_UNKNOWN,
499 CpuMMX},
500 {".sse", PROCESSOR_UNKNOWN,
501 CpuMMX|CpuMMX2|CpuSSE},
502 {".sse2", PROCESSOR_UNKNOWN,
503 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
504 {".sse3", PROCESSOR_UNKNOWN,
505 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
506 {".3dnow", PROCESSOR_UNKNOWN,
507 CpuMMX|Cpu3dnow},
508 {".3dnowa", PROCESSOR_UNKNOWN,
509 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
510 {".padlock", PROCESSOR_UNKNOWN,
511 CpuPadLock},
512 {".pacifica", PROCESSOR_UNKNOWN,
513 CpuSVME},
514 {".svme", PROCESSOR_UNKNOWN,
050dfa73
MM		 515 CpuSVME},
516 {".sse4a", PROCESSOR_UNKNOWN,
517 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
518 {".abm", PROCESSOR_UNKNOWN,
519 CpuABM}
e413e4e9
AM		 520};
521
29b0f896
AM		 522const pseudo_typeS md_pseudo_table[] =
523{
524#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
525 {"align", s_align_bytes, 0},
526#else
527 {"align", s_align_ptwo, 0},
528#endif
529 {"arch", set_cpu_arch, 0},
530#ifndef I386COFF
531 {"bss", s_bss, 0},
532#endif
533 {"ffloat", float_cons, 'f'},
534 {"dfloat", float_cons, 'd'},
535 {"tfloat", float_cons, 'x'},
536 {"value", cons, 2},
d182319b 537 {"slong", signed_cons, 4},
29b0f896
AM		 538 {"noopt", s_ignore, 0},
539 {"optim", s_ignore, 0},
540 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
541 {"code16", set_code_flag, CODE_16BIT},
542 {"code32", set_code_flag, CODE_32BIT},
543 {"code64", set_code_flag, CODE_64BIT},
544 {"intel_syntax", set_intel_syntax, 1},
545 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 546#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 {"largecomm", handle_large_common, 0},
07a53e5c
RH		 548#else
549 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
550 {"loc", dwarf2_directive_loc, 0},
551 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 552#endif
6482c264
NC		 553#ifdef TE_PE
554 {"secrel32", pe_directive_secrel, 0},
555#endif
29b0f896
AM		 556 {0, 0, 0}
557};
558
559/* For interface with expression (). */
560extern char *input_line_pointer;
561
562/* Hash table for instruction mnemonic lookup. */
563static struct hash_control *op_hash;
564
565/* Hash table for register lookup. */
566static struct hash_control *reg_hash;
567\f
252b5132
RH		 568void
569i386_align_code (fragP, count)
570 fragS *fragP;
571 int count;
572{
ce8a8b2f
AM		 573 /* Various efficient no-op patterns for aligning code labels.
574 Note: Don't try to assemble the instructions in the comments.
575 0L and 0w are not legal. */
252b5132
RH		 576 static const char f32_1[] =
577 {0x90}; /* nop */
578 static const char f32_2[] =
ccc9c027 579 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 580 static const char f32_3[] =
581 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
582 static const char f32_4[] =
583 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
584 static const char f32_5[] =
585 {0x90, /* nop */
586 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
587 static const char f32_6[] =
588 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
589 static const char f32_7[] =
590 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
591 static const char f32_8[] =
592 {0x90, /* nop */
593 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
594 static const char f32_9[] =
595 {0x89,0xf6, /* movl %esi,%esi */
596 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
597 static const char f32_10[] =
598 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
599 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
600 static const char f32_11[] =
601 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
602 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
603 static const char f32_12[] =
604 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
605 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
606 static const char f32_13[] =
607 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
608 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
609 static const char f32_14[] =
610 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
611 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
612 static const char f32_15[] =
613 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
614 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 615 static const char f16_3[] =
616 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 617 static const char f16_4[] =
618 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
619 static const char f16_5[] =
620 {0x90, /* nop */
621 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
622 static const char f16_6[] =
623 {0x89,0xf6, /* mov %si,%si */
624 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
625 static const char f16_7[] =
626 {0x8d,0x74,0x00, /* lea 0(%si),%si */
627 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
628 static const char f16_8[] =
629 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
630 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
631 static const char *const f32_patt[] = {
632 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
633 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
634 };
635 static const char *const f16_patt[] = {
c3332e24 636 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 637 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
638 };
ccc9c027
L		 639 /* nopl (%[re]ax) */
640 static const char alt_3[] =
641 {0x0f,0x1f,0x00};
642 /* nopl 0(%[re]ax) */
643 static const char alt_4[] =
644 {0x0f,0x1f,0x40,0x00};
645 /* nopl 0(%[re]ax,%[re]ax,1) */
646 static const char alt_5[] =
647 {0x0f,0x1f,0x44,0x00,0x00};
648 /* nopw 0(%[re]ax,%[re]ax,1) */
649 static const char alt_6[] =
650 {0x66,0x0f,0x1f,0x44,0x00,0x00};
651 /* nopl 0L(%[re]ax) */
652 static const char alt_7[] =
653 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
654 /* nopl 0L(%[re]ax,%[re]ax,1) */
655 static const char alt_8[] =
656 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
657 /* nopw 0L(%[re]ax,%[re]ax,1) */
658 static const char alt_9[] =
659 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
660 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
661 static const char alt_10[] =
662 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
663 /* data16
664 nopw %cs:0L(%[re]ax,%[re]ax,1) */
665 static const char alt_long_11[] =
666 {0x66,
667 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
668 /* data16
669 data16
670 nopw %cs:0L(%[re]ax,%[re]ax,1) */
671 static const char alt_long_12[] =
672 {0x66,
673 0x66,
674 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
675 /* data16
676 data16
677 data16
678 nopw %cs:0L(%[re]ax,%[re]ax,1) */
679 static const char alt_long_13[] =
680 {0x66,
681 0x66,
682 0x66,
683 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
684 /* data16
685 data16
686 data16
687 data16
688 nopw %cs:0L(%[re]ax,%[re]ax,1) */
689 static const char alt_long_14[] =
690 {0x66,
691 0x66,
692 0x66,
693 0x66,
694 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
695 /* data16
696 data16
697 data16
698 data16
699 data16
700 nopw %cs:0L(%[re]ax,%[re]ax,1) */
701 static const char alt_long_15[] =
702 {0x66,
703 0x66,
704 0x66,
705 0x66,
706 0x66,
707 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
708 /* nopl 0(%[re]ax,%[re]ax,1)
709 nopw 0(%[re]ax,%[re]ax,1) */
710 static const char alt_short_11[] =
711 {0x0f,0x1f,0x44,0x00,0x00,
712 0x66,0x0f,0x1f,0x44,0x00,0x00};
713 /* nopw 0(%[re]ax,%[re]ax,1)
714 nopw 0(%[re]ax,%[re]ax,1) */
715 static const char alt_short_12[] =
716 {0x66,0x0f,0x1f,0x44,0x00,0x00,
717 0x66,0x0f,0x1f,0x44,0x00,0x00};
718 /* nopw 0(%[re]ax,%[re]ax,1)
719 nopl 0L(%[re]ax) */
720 static const char alt_short_13[] =
721 {0x66,0x0f,0x1f,0x44,0x00,0x00,
722 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
723 /* nopl 0L(%[re]ax)
724 nopl 0L(%[re]ax) */
725 static const char alt_short_14[] =
726 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
727 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
728 /* nopl 0L(%[re]ax)
729 nopl 0L(%[re]ax,%[re]ax,1) */
730 static const char alt_short_15[] =
731 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
732 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
733 static const char *const alt_short_patt[] = {
734 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
735 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
736 alt_short_14, alt_short_15
737 };
738 static const char *const alt_long_patt[] = {
739 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
740 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
741 alt_long_14, alt_long_15
742 };
252b5132 743
33fef721
JH		 744 if (count <= 0 || count > 15)
745 return;
3e73aa7c 746
ccc9c027
L		 747 /* We need to decide which NOP sequence to use for 32bit and
748 64bit. When -mtune= is used:
749
750 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
751 f32_patt will be used.
050dfa73 752 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with 0x66 prefix will be used.
ccc9c027
L		 753 3. For PROCESSOR_MEROM, alt_long_patt will be used.
754 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
755 PROCESSOR_YONAH, PROCESSOR_MEROM, PROCESSOR_K6, PROCESSOR_ATHLON
756 and PROCESSOR_GENERIC64, alt_short_patt will be used.
757
758 When -mtune= isn't used, alt_short_patt will be used if
759 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
760
761 When -march= or .arch is used, we can't use anything beyond
762 cpu_arch_isa_flags. */
763
764 if (flag_code == CODE_16BIT)
765 {
766 memcpy (fragP->fr_literal + fragP->fr_fix,
767 f16_patt[count - 1], count);
768 if (count > 8)
769 /* Adjust jump offset. */
770 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
771 }
772 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
252b5132 773 {
33fef721
JH		 774 int i;
775 int nnops = (count + 3) / 4;
776 int len = count / nnops;
777 int remains = count - nnops * len;
778 int pos = 0;
779
ccc9c027
L		 780 /* The recommended way to pad 64bit code is to use NOPs preceded
781 by maximally four 0x66 prefixes. Balance the size of nops. */
33fef721 782 for (i = 0; i < remains; i++)
252b5132 783 {
33fef721
JH		 784 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
785 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
786 pos += len + 1;
787 }
788 for (; i < nnops; i++)
789 {
790 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
791 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
792 pos += len;
252b5132 793 }
252b5132 794 }
33fef721 795 else
ccc9c027
L		 796 {
797 const char *const *patt = NULL;
798
799 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
800 {
801 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
802 switch (cpu_arch_tune)
803 {
804 case PROCESSOR_UNKNOWN:
805 /* We use cpu_arch_isa_flags to check if we SHOULD
806 optimize for Cpu686. */
807 if ((cpu_arch_isa_flags & Cpu686) != 0)
808 patt = alt_short_patt;
809 else
810 patt = f32_patt;
811 break;
812 case PROCESSOR_MEROM:
813 patt = alt_long_patt;
814 break;
815 case PROCESSOR_PENTIUMPRO:
816 case PROCESSOR_PENTIUM4:
817 case PROCESSOR_NOCONA:
818 case PROCESSOR_YONAH:
819 case PROCESSOR_K6:
820 case PROCESSOR_ATHLON:
821 case PROCESSOR_K8:
822 case PROCESSOR_GENERIC64:
050dfa73 823 case PROCESSOR_AMDFAM10:
ccc9c027
L		 824 patt = alt_short_patt;
825 break;
826 case PROCESSOR_I486:
827 case PROCESSOR_PENTIUM:
828 case PROCESSOR_GENERIC32:
829 patt = f32_patt;
830 break;
831 }
832 }
833 else
834 {
835 switch (cpu_arch_tune)
836 {
837 case PROCESSOR_UNKNOWN:
838 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
839 PROCESSOR_UNKNOWN. */
840 abort ();
841 break;
842
843 case PROCESSOR_I486:
844 case PROCESSOR_PENTIUM:
845 case PROCESSOR_PENTIUMPRO:
846 case PROCESSOR_PENTIUM4:
847 case PROCESSOR_NOCONA:
848 case PROCESSOR_YONAH:
849 case PROCESSOR_K6:
850 case PROCESSOR_ATHLON:
851 case PROCESSOR_K8:
050dfa73 852 case PROCESSOR_AMDFAM10:
ccc9c027
L		 853 case PROCESSOR_GENERIC32:
854 /* We use cpu_arch_isa_flags to check if we CAN optimize
855 for Cpu686. */
856 if ((cpu_arch_isa_flags & Cpu686) != 0)
857 patt = alt_short_patt;
858 else
859 patt = f32_patt;
860 break;
861 case PROCESSOR_MEROM:
862 if ((cpu_arch_isa_flags & Cpu686) != 0)
863 patt = alt_long_patt;
864 else
865 patt = f32_patt;
866 break;
867 case PROCESSOR_GENERIC64:
868 patt = alt_short_patt;
869 break;
870 }
871 }
872
33fef721 873 memcpy (fragP->fr_literal + fragP->fr_fix,
ccc9c027
L		 874 patt[count - 1], count);
875 }
33fef721 876 fragP->fr_var = count;
252b5132
RH		 877}
878
252b5132
RH		 879static INLINE unsigned int
880mode_from_disp_size (t)
881 unsigned int t;
882{
3e73aa7c 883 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 884}
885
886static INLINE int
887fits_in_signed_byte (num)
847f7ad4 888 offsetT num;
252b5132
RH		 889{
890 return (num >= -128) && (num <= 127);
47926f60 891}
252b5132
RH		 892
893static INLINE int
894fits_in_unsigned_byte (num)
847f7ad4 895 offsetT num;
252b5132
RH		 896{
897 return (num & 0xff) == num;
47926f60 898}
252b5132
RH		 899
900static INLINE int
901fits_in_unsigned_word (num)
847f7ad4 902 offsetT num;
252b5132
RH		 903{
904 return (num & 0xffff) == num;
47926f60 905}
252b5132
RH		 906
907static INLINE int
908fits_in_signed_word (num)
847f7ad4 909 offsetT num;
252b5132
RH		 910{
911 return (-32768 <= num) && (num <= 32767);
47926f60 912}
3e73aa7c
JH		 913static INLINE int
914fits_in_signed_long (num)
915 offsetT num ATTRIBUTE_UNUSED;
916{
917#ifndef BFD64
918 return 1;
919#else
920 return (!(((offsetT) -1 << 31) & num)
921 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
922#endif
923} /* fits_in_signed_long() */
924static INLINE int
925fits_in_unsigned_long (num)
926 offsetT num ATTRIBUTE_UNUSED;
927{
928#ifndef BFD64
929 return 1;
930#else
931 return (num & (((offsetT) 2 << 31) - 1)) == num;
932#endif
933} /* fits_in_unsigned_long() */
252b5132
RH		 934
935static int
936smallest_imm_type (num)
847f7ad4 937 offsetT num;
252b5132 938{
d32cad65 939 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 940 {
941 /* This code is disabled on the 486 because all the Imm1 forms
942 in the opcode table are slower on the i486. They're the
943 versions with the implicitly specified single-position
944 displacement, which has another syntax if you really want to
945 use that form. */
946 if (num == 1)
3e73aa7c 947 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 948 }
252b5132 949 return (fits_in_signed_byte (num)
3e73aa7c 950 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 951 : fits_in_unsigned_byte (num)
3e73aa7c 952 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 953 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 954 ? (Imm16 | Imm32 | Imm32S | Imm64)
955 : fits_in_signed_long (num)
956 ? (Imm32 | Imm32S | Imm64)
957 : fits_in_unsigned_long (num)
958 ? (Imm32 | Imm64)
959 : Imm64);
47926f60 960}
252b5132 961
847f7ad4
AM		 962static offsetT
963offset_in_range (val, size)
964 offsetT val;
965 int size;
966{
508866be 967 addressT mask;
ba2adb93 968
847f7ad4
AM		 969 switch (size)
970 {
508866be
L		 971 case 1: mask = ((addressT) 1 << 8) - 1; break;
972 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 973 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 974#ifdef BFD64
975 case 8: mask = ((addressT) 2 << 63) - 1; break;
976#endif
47926f60 977 default: abort ();
847f7ad4
AM		 978 }
979
ba2adb93 980 /* If BFD64, sign extend val. */
3e73aa7c
JH		 981 if (!use_rela_relocations)
982 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
983 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 984
47926f60 985 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 986 {
987 char buf1[40], buf2[40];
988
989 sprint_value (buf1, val);
990 sprint_value (buf2, val & mask);
991 as_warn (_("%s shortened to %s"), buf1, buf2);
992 }
993 return val & mask;
994}
995
252b5132
RH		 996/* Returns 0 if attempting to add a prefix where one from the same
997 class already exists, 1 if non rep/repne added, 2 if rep/repne
998 added. */
999static int
1000add_prefix (prefix)
1001 unsigned int prefix;
1002{
1003 int ret = 1;
b1905489 1004 unsigned int q;
252b5132 1005
29b0f896
AM		 1006 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1007 && flag_code == CODE_64BIT)
b1905489
JB		 1008 {
1009 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
1010 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
1011 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
1012 ret = 0;
1013 q = REX_PREFIX;
1014 }
3e73aa7c 1015 else
b1905489
JB		 1016 {
1017 switch (prefix)
1018 {
1019 default:
1020 abort ();
1021
1022 case CS_PREFIX_OPCODE:
1023 case DS_PREFIX_OPCODE:
1024 case ES_PREFIX_OPCODE:
1025 case FS_PREFIX_OPCODE:
1026 case GS_PREFIX_OPCODE:
1027 case SS_PREFIX_OPCODE:
1028 q = SEG_PREFIX;
1029 break;
1030
1031 case REPNE_PREFIX_OPCODE:
1032 case REPE_PREFIX_OPCODE:
1033 ret = 2;
1034 /* fall thru */
1035 case LOCK_PREFIX_OPCODE:
1036 q = LOCKREP_PREFIX;
1037 break;
1038
1039 case FWAIT_OPCODE:
1040 q = WAIT_PREFIX;
1041 break;
1042
1043 case ADDR_PREFIX_OPCODE:
1044 q = ADDR_PREFIX;
1045 break;
1046
1047 case DATA_PREFIX_OPCODE:
1048 q = DATA_PREFIX;
1049 break;
1050 }
1051 if (i.prefix[q] != 0)
1052 ret = 0;
1053 }
252b5132 1054
b1905489 1055 if (ret)
252b5132 1056 {
b1905489
JB		 1057 if (!i.prefix[q])
1058 ++i.prefixes;
1059 i.prefix[q] |= prefix;
252b5132 1060 }
b1905489
JB		 1061 else
1062 as_bad (_("same type of prefix used twice"));
252b5132 1063
252b5132
RH		 1064 return ret;
1065}
1066
1067static void
3e73aa7c 1068set_code_flag (value)
e5cb08ac 1069 int value;
eecb386c 1070{
3e73aa7c
JH		 1071 flag_code = value;
1072 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1073 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1074 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1075 {
1076 as_bad (_("64bit mode not supported on this CPU."));
1077 }
1078 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1079 {
1080 as_bad (_("32bit mode not supported on this CPU."));
1081 }
eecb386c
AM		 1082 stackop_size = '\0';
1083}
1084
1085static void
3e73aa7c
JH		 1086set_16bit_gcc_code_flag (new_code_flag)
1087 int new_code_flag;
252b5132 1088{
3e73aa7c
JH		 1089 flag_code = new_code_flag;
1090 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1091 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 1092 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1093}
1094
1095static void
1096set_intel_syntax (syntax_flag)
eecb386c 1097 int syntax_flag;
252b5132
RH		 1098{
1099 /* Find out if register prefixing is specified. */
1100 int ask_naked_reg = 0;
1101
1102 SKIP_WHITESPACE ();
29b0f896 1103 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1104 {
1105 char *string = input_line_pointer;
1106 int e = get_symbol_end ();
1107
47926f60 1108 if (strcmp (string, "prefix") == 0)
252b5132 1109 ask_naked_reg = 1;
47926f60 1110 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1111 ask_naked_reg = -1;
1112 else
d0b47220 1113 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1114 *input_line_pointer = e;
1115 }
1116 demand_empty_rest_of_line ();
c3332e24 1117
252b5132
RH		 1118 intel_syntax = syntax_flag;
1119
1120 if (ask_naked_reg == 0)
f86103b7
AM		 1121 allow_naked_reg = (intel_syntax
1122 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1123 else
1124 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 1125
1126 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1127 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 1128}
1129
e413e4e9
AM		 1130static void
1131set_cpu_arch (dummy)
47926f60 1132 int dummy ATTRIBUTE_UNUSED;
e413e4e9 1133{
47926f60 1134 SKIP_WHITESPACE ();
e413e4e9 1135
29b0f896 1136 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1137 {
1138 char *string = input_line_pointer;
1139 int e = get_symbol_end ();
9103f4f4 1140 unsigned int i;
e413e4e9 1141
9103f4f4 1142 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1143 {
1144 if (strcmp (string, cpu_arch[i].name) == 0)
1145 {
5c6af06e
JB		 1146 if (*string != '.')
1147 {
1148 cpu_arch_name = cpu_arch[i].name;
1149 cpu_sub_arch_name = NULL;
1150 cpu_arch_flags = (cpu_arch[i].flags
1151 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
ccc9c027 1152 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1153 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1154 if (!cpu_arch_tune_set)
1155 {
1156 cpu_arch_tune = cpu_arch_isa;
1157 cpu_arch_tune_flags = cpu_arch_isa_flags;
1158 }
5c6af06e
JB		 1159 break;
1160 }
1161 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1162 {
1163 cpu_sub_arch_name = cpu_arch[i].name;
1164 cpu_arch_flags |= cpu_arch[i].flags;
1165 }
1166 *input_line_pointer = e;
1167 demand_empty_rest_of_line ();
1168 return;
e413e4e9
AM		 1169 }
1170 }
9103f4f4 1171 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1172 as_bad (_("no such architecture: `%s'"), string);
1173
1174 *input_line_pointer = e;
1175 }
1176 else
1177 as_bad (_("missing cpu architecture"));
1178
fddf5b5b
AM		 1179 no_cond_jump_promotion = 0;
1180 if (*input_line_pointer == ','
29b0f896 1181 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1182 {
1183 char *string = ++input_line_pointer;
1184 int e = get_symbol_end ();
1185
1186 if (strcmp (string, "nojumps") == 0)
1187 no_cond_jump_promotion = 1;
1188 else if (strcmp (string, "jumps") == 0)
1189 ;
1190 else
1191 as_bad (_("no such architecture modifier: `%s'"), string);
1192
1193 *input_line_pointer = e;
1194 }
1195
e413e4e9
AM		 1196 demand_empty_rest_of_line ();
1197}
1198
b9d79e03
JH		 1199unsigned long
1200i386_mach ()
1201{
1202 if (!strcmp (default_arch, "x86_64"))
1203 return bfd_mach_x86_64;
1204 else if (!strcmp (default_arch, "i386"))
1205 return bfd_mach_i386_i386;
1206 else
1207 as_fatal (_("Unknown architecture"));
1208}
b9d79e03 1209\f
252b5132
RH		 1210void
1211md_begin ()
1212{
1213 const char *hash_err;
1214
47926f60 1215 /* Initialize op_hash hash table. */
252b5132
RH		 1216 op_hash = hash_new ();
1217
1218 {
29b0f896
AM		 1219 const template *optab;
1220 templates *core_optab;
252b5132 1221
47926f60
KH		 1222 /* Setup for loop. */
1223 optab = i386_optab;
252b5132
RH		 1224 core_optab = (templates *) xmalloc (sizeof (templates));
1225 core_optab->start = optab;
1226
1227 while (1)
1228 {
1229 ++optab;
1230 if (optab->name == NULL
1231 || strcmp (optab->name, (optab - 1)->name) != 0)
1232 {
1233 /* different name --> ship out current template list;
47926f60 1234 add to hash table; & begin anew. */
252b5132
RH		 1235 core_optab->end = optab;
1236 hash_err = hash_insert (op_hash,
1237 (optab - 1)->name,
1238 (PTR) core_optab);
1239 if (hash_err)
1240 {
252b5132
RH		 1241 as_fatal (_("Internal Error: Can't hash %s: %s"),
1242 (optab - 1)->name,
1243 hash_err);
1244 }
1245 if (optab->name == NULL)
1246 break;
1247 core_optab = (templates *) xmalloc (sizeof (templates));
1248 core_optab->start = optab;
1249 }
1250 }
1251 }
1252
47926f60 1253 /* Initialize reg_hash hash table. */
252b5132
RH		 1254 reg_hash = hash_new ();
1255 {
29b0f896 1256 const reg_entry *regtab;
252b5132
RH		 1257
1258 for (regtab = i386_regtab;
1259 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
1260 regtab++)
1261 {
1262 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1263 if (hash_err)
3e73aa7c
JH		 1264 as_fatal (_("Internal Error: Can't hash %s: %s"),
1265 regtab->reg_name,
1266 hash_err);
252b5132
RH		 1267 }
1268 }
1269
47926f60 1270 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1271 {
29b0f896
AM		 1272 int c;
1273 char *p;
252b5132
RH		 1274
1275 for (c = 0; c < 256; c++)
1276 {
3882b010 1277 if (ISDIGIT (c))
252b5132
RH		 1278 {
1279 digit_chars[c] = c;
1280 mnemonic_chars[c] = c;
1281 register_chars[c] = c;
1282 operand_chars[c] = c;
1283 }
3882b010 1284 else if (ISLOWER (c))
252b5132
RH		 1285 {
1286 mnemonic_chars[c] = c;
1287 register_chars[c] = c;
1288 operand_chars[c] = c;
1289 }
3882b010 1290 else if (ISUPPER (c))
252b5132 1291 {
3882b010 1292 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1293 register_chars[c] = mnemonic_chars[c];
1294 operand_chars[c] = c;
1295 }
1296
3882b010 1297 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1298 identifier_chars[c] = c;
1299 else if (c >= 128)
1300 {
1301 identifier_chars[c] = c;
1302 operand_chars[c] = c;
1303 }
1304 }
1305
1306#ifdef LEX_AT
1307 identifier_chars['@'] = '@';
32137342
NC		 1308#endif
1309#ifdef LEX_QM
1310 identifier_chars['?'] = '?';
1311 operand_chars['?'] = '?';
252b5132 1312#endif
252b5132 1313 digit_chars['-'] = '-';
791fe849 1314 mnemonic_chars['-'] = '-';
252b5132
RH		 1315 identifier_chars['_'] = '_';
1316 identifier_chars['.'] = '.';
1317
1318 for (p = operand_special_chars; *p != '\0'; p++)
1319 operand_chars[(unsigned char) *p] = *p;
1320 }
1321
1322#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1323 if (IS_ELF)
252b5132
RH		 1324 {
1325 record_alignment (text_section, 2);
1326 record_alignment (data_section, 2);
1327 record_alignment (bss_section, 2);
1328 }
1329#endif
a4447b93
RH		 1330
1331 if (flag_code == CODE_64BIT)
1332 {
1333 x86_dwarf2_return_column = 16;
1334 x86_cie_data_alignment = -8;
1335 }
1336 else
1337 {
1338 x86_dwarf2_return_column = 8;
1339 x86_cie_data_alignment = -4;
1340 }
252b5132
RH		 1341}
1342
1343void
1344i386_print_statistics (file)
1345 FILE *file;
1346{
1347 hash_print_statistics (file, "i386 opcode", op_hash);
1348 hash_print_statistics (file, "i386 register", reg_hash);
1349}
1350\f
252b5132
RH		 1351#ifdef DEBUG386
1352
ce8a8b2f 1353/* Debugging routines for md_assemble. */
252b5132
RH		 1354static void pi PARAMS ((char *, i386_insn *));
1355static void pte PARAMS ((template *));
1356static void pt PARAMS ((unsigned int));
1357static void pe PARAMS ((expressionS *));
1358static void ps PARAMS ((symbolS *));
1359
1360static void
1361pi (line, x)
1362 char *line;
1363 i386_insn *x;
1364{
09f131f2 1365 unsigned int i;
252b5132
RH		 1366
1367 fprintf (stdout, "%s: template ", line);
1368 pte (&x->tm);
09f131f2
JH		 1369 fprintf (stdout, " address: base %s index %s scale %x\n",
1370 x->base_reg ? x->base_reg->reg_name : "none",
1371 x->index_reg ? x->index_reg->reg_name : "none",
1372 x->log2_scale_factor);
1373 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1374 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1375 fprintf (stdout, " sib: base %x index %x scale %x\n",
1376 x->sib.base, x->sib.index, x->sib.scale);
1377 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1378 (x->rex & REX_MODE64) != 0,
1379 (x->rex & REX_EXTX) != 0,
1380 (x->rex & REX_EXTY) != 0,
1381 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1382 for (i = 0; i < x->operands; i++)
1383 {
1384 fprintf (stdout, " #%d: ", i + 1);
1385 pt (x->types[i]);
1386 fprintf (stdout, "\n");
1387 if (x->types[i]
3f4438ab 1388 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1389 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1390 if (x->types[i] & Imm)
520dc8e8 1391 pe (x->op[i].imms);
252b5132 1392 if (x->types[i] & Disp)
520dc8e8 1393 pe (x->op[i].disps);
252b5132
RH		 1394 }
1395}
1396
1397static void
1398pte (t)
1399 template *t;
1400{
09f131f2 1401 unsigned int i;
252b5132 1402 fprintf (stdout, " %d operands ", t->operands);
47926f60 1403 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1404 if (t->extension_opcode != None)
1405 fprintf (stdout, "ext %x ", t->extension_opcode);
1406 if (t->opcode_modifier & D)
1407 fprintf (stdout, "D");
1408 if (t->opcode_modifier & W)
1409 fprintf (stdout, "W");
1410 fprintf (stdout, "\n");
1411 for (i = 0; i < t->operands; i++)
1412 {
1413 fprintf (stdout, " #%d type ", i + 1);
1414 pt (t->operand_types[i]);
1415 fprintf (stdout, "\n");
1416 }
1417}
1418
1419static void
1420pe (e)
1421 expressionS *e;
1422{
24eab124 1423 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1424 fprintf (stdout, " add_number %ld (%lx)\n",
1425 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1426 if (e->X_add_symbol)
1427 {
1428 fprintf (stdout, " add_symbol ");
1429 ps (e->X_add_symbol);
1430 fprintf (stdout, "\n");
1431 }
1432 if (e->X_op_symbol)
1433 {
1434 fprintf (stdout, " op_symbol ");
1435 ps (e->X_op_symbol);
1436 fprintf (stdout, "\n");
1437 }
1438}
1439
1440static void
1441ps (s)
1442 symbolS *s;
1443{
1444 fprintf (stdout, "%s type %s%s",
1445 S_GET_NAME (s),
1446 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1447 segment_name (S_GET_SEGMENT (s)));
1448}
1449
7b81dfbb 1450static struct type_name
252b5132
RH		 1451 {
1452 unsigned int mask;
1453 char *tname;
1454 }
7b81dfbb 1455const type_names[] =
252b5132
RH		 1456{
1457 { Reg8, "r8" },
1458 { Reg16, "r16" },
1459 { Reg32, "r32" },
09f131f2 1460 { Reg64, "r64" },
252b5132
RH		 1461 { Imm8, "i8" },
1462 { Imm8S, "i8s" },
1463 { Imm16, "i16" },
1464 { Imm32, "i32" },
09f131f2
JH		 1465 { Imm32S, "i32s" },
1466 { Imm64, "i64" },
252b5132
RH		 1467 { Imm1, "i1" },
1468 { BaseIndex, "BaseIndex" },
1469 { Disp8, "d8" },
1470 { Disp16, "d16" },
1471 { Disp32, "d32" },
09f131f2
JH		 1472 { Disp32S, "d32s" },
1473 { Disp64, "d64" },
252b5132
RH		 1474 { InOutPortReg, "InOutPortReg" },
1475 { ShiftCount, "ShiftCount" },
1476 { Control, "control reg" },
1477 { Test, "test reg" },
1478 { Debug, "debug reg" },
1479 { FloatReg, "FReg" },
1480 { FloatAcc, "FAcc" },
1481 { SReg2, "SReg2" },
1482 { SReg3, "SReg3" },
1483 { Acc, "Acc" },
1484 { JumpAbsolute, "Jump Absolute" },
1485 { RegMMX, "rMMX" },
3f4438ab 1486 { RegXMM, "rXMM" },
252b5132
RH		 1487 { EsSeg, "es" },
1488 { 0, "" }
1489};
1490
1491static void
1492pt (t)
1493 unsigned int t;
1494{
29b0f896 1495 const struct type_name *ty;
252b5132 1496
09f131f2
JH		 1497 for (ty = type_names; ty->mask; ty++)
1498 if (t & ty->mask)
1499 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1500 fflush (stdout);
1501}
1502
1503#endif /* DEBUG386 */
1504\f
252b5132 1505static bfd_reloc_code_real_type
3956db08 1506reloc (unsigned int size,
64e74474
AM		 1507 int pcrel,
1508 int sign,
1509 bfd_reloc_code_real_type other)
252b5132 1510{
47926f60 1511 if (other != NO_RELOC)
3956db08
JB		 1512 {
1513 reloc_howto_type *reloc;
1514
1515 if (size == 8)
1516 switch (other)
1517 {
64e74474
AM		 1518 case BFD_RELOC_X86_64_GOT32:
1519 return BFD_RELOC_X86_64_GOT64;
1520 break;
1521 case BFD_RELOC_X86_64_PLTOFF64:
1522 return BFD_RELOC_X86_64_PLTOFF64;
1523 break;
1524 case BFD_RELOC_X86_64_GOTPC32:
1525 other = BFD_RELOC_X86_64_GOTPC64;
1526 break;
1527 case BFD_RELOC_X86_64_GOTPCREL:
1528 other = BFD_RELOC_X86_64_GOTPCREL64;
1529 break;
1530 case BFD_RELOC_X86_64_TPOFF32:
1531 other = BFD_RELOC_X86_64_TPOFF64;
1532 break;
1533 case BFD_RELOC_X86_64_DTPOFF32:
1534 other = BFD_RELOC_X86_64_DTPOFF64;
1535 break;
1536 default:
1537 break;
3956db08 1538 }
e05278af
JB		 1539
1540 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1541 if (size == 4 && flag_code != CODE_64BIT)
1542 sign = -1;
1543
3956db08
JB		 1544 reloc = bfd_reloc_type_lookup (stdoutput, other);
1545 if (!reloc)
1546 as_bad (_("unknown relocation (%u)"), other);
1547 else if (size != bfd_get_reloc_size (reloc))
1548 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1549 bfd_get_reloc_size (reloc),
1550 size);
1551 else if (pcrel && !reloc->pc_relative)
1552 as_bad (_("non-pc-relative relocation for pc-relative field"));
1553 else if ((reloc->complain_on_overflow == complain_overflow_signed
1554 && !sign)
1555 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1556 && sign > 0))
3956db08
JB		 1557 as_bad (_("relocated field and relocation type differ in signedness"));
1558 else
1559 return other;
1560 return NO_RELOC;
1561 }
252b5132
RH		 1562
1563 if (pcrel)
1564 {
3e73aa7c 1565 if (!sign)
3956db08 1566 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1567 switch (size)
1568 {
1569 case 1: return BFD_RELOC_8_PCREL;
1570 case 2: return BFD_RELOC_16_PCREL;
1571 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1572 case 8: return BFD_RELOC_64_PCREL;
252b5132 1573 }
3956db08 1574 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1575 }
1576 else
1577 {
3956db08 1578 if (sign > 0)
e5cb08ac 1579 switch (size)
3e73aa7c
JH		 1580 {
1581 case 4: return BFD_RELOC_X86_64_32S;
1582 }
1583 else
1584 switch (size)
1585 {
1586 case 1: return BFD_RELOC_8;
1587 case 2: return BFD_RELOC_16;
1588 case 4: return BFD_RELOC_32;
1589 case 8: return BFD_RELOC_64;
1590 }
3956db08
JB		 1591 as_bad (_("cannot do %s %u byte relocation"),
1592 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1593 }
1594
bfb32b52 1595 abort ();
252b5132
RH		 1596 return BFD_RELOC_NONE;
1597}
1598
47926f60
KH		 1599/* Here we decide which fixups can be adjusted to make them relative to
1600 the beginning of the section instead of the symbol. Basically we need
1601 to make sure that the dynamic relocations are done correctly, so in
1602 some cases we force the original symbol to be used. */
1603
252b5132 1604int
c0c949c7 1605tc_i386_fix_adjustable (fixP)
31312f95 1606 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1607{
6d249963 1608#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1609 if (!IS_ELF)
31312f95
AM		 1610 return 1;
1611
a161fe53
AM		 1612 /* Don't adjust pc-relative references to merge sections in 64-bit
1613 mode. */
1614 if (use_rela_relocations
1615 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1616 && fixP->fx_pcrel)
252b5132 1617 return 0;
31312f95 1618
8d01d9a9
AJ		 1619 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1620 and changed later by validate_fix. */
1621 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1622 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1623 return 0;
1624
ce8a8b2f 1625 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1626 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1627 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1628 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1629 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1630 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1631 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1632 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1633 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1634 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1635 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1636 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1637 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1638 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1639 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1640 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1641 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1642 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1643 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1644 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1645 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1646 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1647 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1648 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1649 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1650 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1651 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1652 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1653 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1654 return 0;
31312f95 1655#endif
252b5132
RH		 1656 return 1;
1657}
252b5132 1658
29b0f896 1659static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1660
1661static int
252b5132 1662intel_float_operand (mnemonic)
29b0f896 1663 const char *mnemonic;
252b5132 1664{
9306ca4a
JB		 1665 /* Note that the value returned is meaningful only for opcodes with (memory)
1666 operands, hence the code here is free to improperly handle opcodes that
1667 have no operands (for better performance and smaller code). */
1668
1669 if (mnemonic[0] != 'f')
1670 return 0; /* non-math */
1671
1672 switch (mnemonic[1])
1673 {
1674 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1675 the fs segment override prefix not currently handled because no
1676 call path can make opcodes without operands get here */
1677 case 'i':
1678 return 2 /* integer op */;
1679 case 'l':
1680 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1681 return 3; /* fldcw/fldenv */
1682 break;
1683 case 'n':
1684 if (mnemonic[2] != 'o' /* fnop */)
1685 return 3; /* non-waiting control op */
1686 break;
1687 case 'r':
1688 if (mnemonic[2] == 's')
1689 return 3; /* frstor/frstpm */
1690 break;
1691 case 's':
1692 if (mnemonic[2] == 'a')
1693 return 3; /* fsave */
1694 if (mnemonic[2] == 't')
1695 {
1696 switch (mnemonic[3])
1697 {
1698 case 'c': /* fstcw */
1699 case 'd': /* fstdw */
1700 case 'e': /* fstenv */
1701 case 's': /* fsts[gw] */
1702 return 3;
1703 }
1704 }
1705 break;
1706 case 'x':
1707 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1708 return 0; /* fxsave/fxrstor are not really math ops */
1709 break;
1710 }
252b5132 1711
9306ca4a 1712 return 1;
252b5132
RH		 1713}
1714
1715/* This is the guts of the machine-dependent assembler. LINE points to a
1716 machine dependent instruction. This function is supposed to emit
1717 the frags/bytes it assembles to. */
1718
1719void
1720md_assemble (line)
1721 char *line;
1722{
252b5132 1723 int j;
252b5132
RH		 1724 char mnemonic[MAX_MNEM_SIZE];
1725
47926f60 1726 /* Initialize globals. */
252b5132
RH		 1727 memset (&i, '\0', sizeof (i));
1728 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1729 i.reloc[j] = NO_RELOC;
252b5132
RH		 1730 memset (disp_expressions, '\0', sizeof (disp_expressions));
1731 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1732 save_stack_p = save_stack;
252b5132
RH		 1733
1734 /* First parse an instruction mnemonic & call i386_operand for the operands.
1735 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1736 start of a (possibly prefixed) mnemonic. */
252b5132 1737
29b0f896
AM		 1738 line = parse_insn (line, mnemonic);
1739 if (line == NULL)
1740 return;
252b5132 1741
29b0f896
AM		 1742 line = parse_operands (line, mnemonic);
1743 if (line == NULL)
1744 return;
252b5132 1745
050dfa73
MM		 1746 /* The order of the immediates should be reversed
1747 for 2 immediates extrq and insertq instructions */
1748 if ((i.imm_operands == 2) &&
1749 ((strcmp (mnemonic, "extrq") == 0)
1750 || (strcmp (mnemonic, "insertq") == 0)))
1751 {
1752 swap_imm_operands ();
1753 /* "extrq" and insertq" are the only two instructions whose operands
1754 have to be reversed even though they have two immediate operands.
1755 */
1756 if (intel_syntax)
1757 swap_operands ();
1758 }
1759
29b0f896
AM		 1760 /* Now we've parsed the mnemonic into a set of templates, and have the
1761 operands at hand. */
1762
1763 /* All intel opcodes have reversed operands except for "bound" and
1764 "enter". We also don't reverse intersegment "jmp" and "call"
1765 instructions with 2 immediate operands so that the immediate segment
050dfa73 1766 precedes the offset, as it does when in AT&T mode. */
29b0f896
AM		 1767 if (intel_syntax && i.operands > 1
1768 && (strcmp (mnemonic, "bound") != 0)
30123838 1769 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1770 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1771 swap_operands ();
1772
1773 if (i.imm_operands)
1774 optimize_imm ();
1775
b300c311
L		 1776 /* Don't optimize displacement for movabs since it only takes 64bit
1777 displacement. */
1778 if (i.disp_operands
1779 && (flag_code != CODE_64BIT
1780 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1781 optimize_disp ();
1782
1783 /* Next, we find a template that matches the given insn,
1784 making sure the overlap of the given operands types is consistent
1785 with the template operand types. */
252b5132 1786
29b0f896
AM		 1787 if (!match_template ())
1788 return;
252b5132 1789
cd61ebfe
AM		 1790 if (intel_syntax)
1791 {
1792 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1793 if (SYSV386_COMPAT
1794 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1795 i.tm.base_opcode ^= FloatR;
1796
1797 /* Zap movzx and movsx suffix. The suffix may have been set from
1798 "word ptr" or "byte ptr" on the source operand, but we'll use
1799 the suffix later to choose the destination register. */
1800 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1801 {
1802 if (i.reg_operands < 2
1803 && !i.suffix
1804 && (~i.tm.opcode_modifier
1805 & (No_bSuf
1806 | No_wSuf
1807 | No_lSuf
1808 | No_sSuf
1809 | No_xSuf
1810 | No_qSuf)))
1811 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1812
1813 i.suffix = 0;
1814 }
cd61ebfe 1815 }
24eab124 1816
29b0f896
AM		 1817 if (i.tm.opcode_modifier & FWait)
1818 if (!add_prefix (FWAIT_OPCODE))
1819 return;
252b5132 1820
29b0f896
AM		 1821 /* Check string instruction segment overrides. */
1822 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1823 {
1824 if (!check_string ())
5dd0794d 1825 return;
29b0f896 1826 }
5dd0794d 1827
29b0f896
AM		 1828 if (!process_suffix ())
1829 return;
e413e4e9 1830
29b0f896
AM		 1831 /* Make still unresolved immediate matches conform to size of immediate
1832 given in i.suffix. */
1833 if (!finalize_imm ())
1834 return;
252b5132 1835
29b0f896
AM		 1836 if (i.types[0] & Imm1)
1837 i.imm_operands = 0; /* kludge for shift insns. */
1838 if (i.types[0] & ImplicitRegister)
1839 i.reg_operands--;
1840 if (i.types[1] & ImplicitRegister)
1841 i.reg_operands--;
1842 if (i.types[2] & ImplicitRegister)
1843 i.reg_operands--;
252b5132 1844
29b0f896
AM		 1845 if (i.tm.opcode_modifier & ImmExt)
1846 {
02fc3089
L		 1847 expressionS *exp;
1848
ca164297
L		 1849 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1850 {
67c1ffbe 1851 /* These Intel Prescott New Instructions have the fixed
ca164297
L		 1852 operands with an opcode suffix which is coded in the same
1853 place as an 8-bit immediate field would be. Here we check
1854 those operands and remove them afterwards. */
1855 unsigned int x;
1856
a4622f40 1857 for (x = 0; x < i.operands; x++)
ca164297
L		 1858 if (i.op[x].regs->reg_num != x)
1859 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
64e74474 1860 i.op[x].regs->reg_name, x + 1, i.tm.name);
ca164297
L		 1861 i.operands = 0;
1862 }
1863
29b0f896
AM		 1864 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1865 opcode suffix which is coded in the same place as an 8-bit
1866 immediate field would be. Here we fake an 8-bit immediate
1867 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1868
29b0f896 1869 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1870
29b0f896
AM		 1871 exp = &im_expressions[i.imm_operands++];
1872 i.op[i.operands].imms = exp;
1873 i.types[i.operands++] = Imm8;
1874 exp->X_op = O_constant;
1875 exp->X_add_number = i.tm.extension_opcode;
1876 i.tm.extension_opcode = None;
1877 }
252b5132 1878
29b0f896
AM		 1879 /* For insns with operands there are more diddles to do to the opcode. */
1880 if (i.operands)
1881 {
1882 if (!process_operands ())
1883 return;
1884 }
1885 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1886 {
1887 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1888 as_warn (_("translating to `%sp'"), i.tm.name);
1889 }
252b5132 1890
29b0f896
AM		 1891 /* Handle conversion of 'int $3' --> special int3 insn. */
1892 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1893 {
1894 i.tm.base_opcode = INT3_OPCODE;
1895 i.imm_operands = 0;
1896 }
252b5132 1897
29b0f896
AM		 1898 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1899 && i.op[0].disps->X_op == O_constant)
1900 {
1901 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1902 the absolute address given by the constant. Since ix86 jumps and
1903 calls are pc relative, we need to generate a reloc. */
1904 i.op[0].disps->X_add_symbol = &abs_symbol;
1905 i.op[0].disps->X_op = O_symbol;
1906 }
252b5132 1907
29b0f896
AM		 1908 if ((i.tm.opcode_modifier & Rex64) != 0)
1909 i.rex |= REX_MODE64;
252b5132 1910
29b0f896
AM		 1911 /* For 8 bit registers we need an empty rex prefix. Also if the
1912 instruction already has a prefix, we need to convert old
1913 registers to new ones. */
773f551c 1914
29b0f896
AM		 1915 if (((i.types[0] & Reg8) != 0
1916 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1917 || ((i.types[1] & Reg8) != 0
1918 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1919 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1920 && i.rex != 0))
1921 {
1922 int x;
726c5dcd 1923
29b0f896
AM		 1924 i.rex |= REX_OPCODE;
1925 for (x = 0; x < 2; x++)
1926 {
1927 /* Look for 8 bit operand that uses old registers. */
1928 if ((i.types[x] & Reg8) != 0
1929 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1930 {
29b0f896
AM		 1931 /* In case it is "hi" register, give up. */
1932 if (i.op[x].regs->reg_num > 3)
0477af35 1933 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1934 i.op[x].regs->reg_name);
773f551c 1935
29b0f896
AM		 1936 /* Otherwise it is equivalent to the extended register.
1937 Since the encoding doesn't change this is merely
1938 cosmetic cleanup for debug output. */
1939
1940 i.op[x].regs = i.op[x].regs + 8;
773f551c 1941 }
29b0f896
AM		 1942 }
1943 }
773f551c 1944
29b0f896
AM		 1945 if (i.rex != 0)
1946 add_prefix (REX_OPCODE | i.rex);
1947
1948 /* We are ready to output the insn. */
1949 output_insn ();
1950}
1951
1952static char *
1953parse_insn (line, mnemonic)
1954 char *line;
1955 char *mnemonic;
1956{
1957 char *l = line;
1958 char *token_start = l;
1959 char *mnem_p;
5c6af06e
JB		 1960 int supported;
1961 const template *t;
29b0f896
AM		 1962
1963 /* Non-zero if we found a prefix only acceptable with string insns. */
1964 const char *expecting_string_instruction = NULL;
45288df1 1965
29b0f896
AM		 1966 while (1)
1967 {
1968 mnem_p = mnemonic;
1969 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1970 {
1971 mnem_p++;
1972 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1973 {
29b0f896
AM		 1974 as_bad (_("no such instruction: `%s'"), token_start);
1975 return NULL;
1976 }
1977 l++;
1978 }
1979 if (!is_space_char (*l)
1980 && *l != END_OF_INSN
e44823cf
JB		 1981 && (intel_syntax
1982 || (*l != PREFIX_SEPARATOR
1983 && *l != ',')))
29b0f896
AM		 1984 {
1985 as_bad (_("invalid character %s in mnemonic"),
1986 output_invalid (*l));
1987 return NULL;
1988 }
1989 if (token_start == l)
1990 {
e44823cf 1991 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1992 as_bad (_("expecting prefix; got nothing"));
1993 else
1994 as_bad (_("expecting mnemonic; got nothing"));
1995 return NULL;
1996 }
45288df1 1997
29b0f896
AM		 1998 /* Look up instruction (or prefix) via hash table. */
1999 current_templates = hash_find (op_hash, mnemonic);
47926f60 2000
29b0f896
AM		 2001 if (*l != END_OF_INSN
2002 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2003 && current_templates
2004 && (current_templates->start->opcode_modifier & IsPrefix))
2005 {
2dd88dca
JB		 2006 if (current_templates->start->cpu_flags
2007 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
2008 {
2009 as_bad ((flag_code != CODE_64BIT
2010 ? _("`%s' is only supported in 64-bit mode")
2011 : _("`%s' is not supported in 64-bit mode")),
2012 current_templates->start->name);
2013 return NULL;
2014 }
29b0f896
AM		 2015 /* If we are in 16-bit mode, do not allow addr16 or data16.
2016 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2017 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
2018 && flag_code != CODE_64BIT
2019 && (((current_templates->start->opcode_modifier & Size32) != 0)
2020 ^ (flag_code == CODE_16BIT)))
2021 {
2022 as_bad (_("redundant %s prefix"),
2023 current_templates->start->name);
2024 return NULL;
45288df1 2025 }
29b0f896
AM		 2026 /* Add prefix, checking for repeated prefixes. */
2027 switch (add_prefix (current_templates->start->base_opcode))
2028 {
2029 case 0:
2030 return NULL;
2031 case 2:
2032 expecting_string_instruction = current_templates->start->name;
2033 break;
2034 }
2035 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2036 token_start = ++l;
2037 }
2038 else
2039 break;
2040 }
45288df1 2041
29b0f896
AM		 2042 if (!current_templates)
2043 {
2044 /* See if we can get a match by trimming off a suffix. */
2045 switch (mnem_p[-1])
2046 {
2047 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2048 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2049 i.suffix = SHORT_MNEM_SUFFIX;
2050 else
29b0f896
AM		 2051 case BYTE_MNEM_SUFFIX:
2052 case QWORD_MNEM_SUFFIX:
2053 i.suffix = mnem_p[-1];
2054 mnem_p[-1] = '\0';
2055 current_templates = hash_find (op_hash, mnemonic);
2056 break;
2057 case SHORT_MNEM_SUFFIX:
2058 case LONG_MNEM_SUFFIX:
2059 if (!intel_syntax)
2060 {
2061 i.suffix = mnem_p[-1];
2062 mnem_p[-1] = '\0';
2063 current_templates = hash_find (op_hash, mnemonic);
2064 }
2065 break;
252b5132 2066
29b0f896
AM		 2067 /* Intel Syntax. */
2068 case 'd':
2069 if (intel_syntax)
2070 {
9306ca4a 2071 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2072 i.suffix = SHORT_MNEM_SUFFIX;
2073 else
2074 i.suffix = LONG_MNEM_SUFFIX;
2075 mnem_p[-1] = '\0';
2076 current_templates = hash_find (op_hash, mnemonic);
2077 }
2078 break;
2079 }
2080 if (!current_templates)
2081 {
2082 as_bad (_("no such instruction: `%s'"), token_start);
2083 return NULL;
2084 }
2085 }
252b5132 2086
29b0f896
AM		 2087 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2088 {
2089 /* Check for a branch hint. We allow ",pt" and ",pn" for
2090 predict taken and predict not taken respectively.
2091 I'm not sure that branch hints actually do anything on loop
2092 and jcxz insns (JumpByte) for current Pentium4 chips. They
2093 may work in the future and it doesn't hurt to accept them
2094 now. */
2095 if (l[0] == ',' && l[1] == 'p')
2096 {
2097 if (l[2] == 't')
2098 {
2099 if (!add_prefix (DS_PREFIX_OPCODE))
2100 return NULL;
2101 l += 3;
2102 }
2103 else if (l[2] == 'n')
2104 {
2105 if (!add_prefix (CS_PREFIX_OPCODE))
2106 return NULL;
2107 l += 3;
2108 }
2109 }
2110 }
2111 /* Any other comma loses. */
2112 if (*l == ',')
2113 {
2114 as_bad (_("invalid character %s in mnemonic"),
2115 output_invalid (*l));
2116 return NULL;
2117 }
252b5132 2118
29b0f896 2119 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2120 supported = 0;
2121 for (t = current_templates->start; t < current_templates->end; ++t)
2122 {
2123 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2124 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 2125 supported |= 1;
5c6af06e 2126 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 2127 supported |= 2;
5c6af06e
JB		 2128 }
2129 if (!(supported & 2))
2130 {
2131 as_bad (flag_code == CODE_64BIT
2132 ? _("`%s' is not supported in 64-bit mode")
2133 : _("`%s' is only supported in 64-bit mode"),
2134 current_templates->start->name);
2135 return NULL;
2136 }
2137 if (!(supported & 1))
29b0f896 2138 {
5c6af06e
JB		 2139 as_warn (_("`%s' is not supported on `%s%s'"),
2140 current_templates->start->name,
2141 cpu_arch_name,
2142 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 2143 }
2144 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2145 {
2146 as_warn (_("use .code16 to ensure correct addressing mode"));
2147 }
252b5132 2148
29b0f896 2149 /* Check for rep/repne without a string instruction. */
f41bbced 2150 if (expecting_string_instruction)
29b0f896 2151 {
f41bbced
JB		 2152 static templates override;
2153
2154 for (t = current_templates->start; t < current_templates->end; ++t)
2155 if (t->opcode_modifier & IsString)
2156 break;
2157 if (t >= current_templates->end)
2158 {
2159 as_bad (_("expecting string instruction after `%s'"),
64e74474 2160 expecting_string_instruction);
f41bbced
JB		 2161 return NULL;
2162 }
2163 for (override.start = t; t < current_templates->end; ++t)
2164 if (!(t->opcode_modifier & IsString))
2165 break;
2166 override.end = t;
2167 current_templates = &override;
29b0f896 2168 }
252b5132 2169
29b0f896
AM		 2170 return l;
2171}
252b5132 2172
29b0f896
AM		 2173static char *
2174parse_operands (l, mnemonic)
2175 char *l;
2176 const char *mnemonic;
2177{
2178 char *token_start;
3138f287 2179
29b0f896
AM		 2180 /* 1 if operand is pending after ','. */
2181 unsigned int expecting_operand = 0;
252b5132 2182
29b0f896
AM		 2183 /* Non-zero if operand parens not balanced. */
2184 unsigned int paren_not_balanced;
2185
2186 while (*l != END_OF_INSN)
2187 {
2188 /* Skip optional white space before operand. */
2189 if (is_space_char (*l))
2190 ++l;
2191 if (!is_operand_char (*l) && *l != END_OF_INSN)
2192 {
2193 as_bad (_("invalid character %s before operand %d"),
2194 output_invalid (*l),
2195 i.operands + 1);
2196 return NULL;
2197 }
2198 token_start = l; /* after white space */
2199 paren_not_balanced = 0;
2200 while (paren_not_balanced || *l != ',')
2201 {
2202 if (*l == END_OF_INSN)
2203 {
2204 if (paren_not_balanced)
2205 {
2206 if (!intel_syntax)
2207 as_bad (_("unbalanced parenthesis in operand %d."),
2208 i.operands + 1);
2209 else
2210 as_bad (_("unbalanced brackets in operand %d."),
2211 i.operands + 1);
2212 return NULL;
2213 }
2214 else
2215 break; /* we are done */
2216 }
2217 else if (!is_operand_char (*l) && !is_space_char (*l))
2218 {
2219 as_bad (_("invalid character %s in operand %d"),
2220 output_invalid (*l),
2221 i.operands + 1);
2222 return NULL;
2223 }
2224 if (!intel_syntax)
2225 {
2226 if (*l == '(')
2227 ++paren_not_balanced;
2228 if (*l == ')')
2229 --paren_not_balanced;
2230 }
2231 else
2232 {
2233 if (*l == '[')
2234 ++paren_not_balanced;
2235 if (*l == ']')
2236 --paren_not_balanced;
2237 }
2238 l++;
2239 }
2240 if (l != token_start)
2241 { /* Yes, we've read in another operand. */
2242 unsigned int operand_ok;
2243 this_operand = i.operands++;
2244 if (i.operands > MAX_OPERANDS)
2245 {
2246 as_bad (_("spurious operands; (%d operands/instruction max)"),
2247 MAX_OPERANDS);
2248 return NULL;
2249 }
2250 /* Now parse operand adding info to 'i' as we go along. */
2251 END_STRING_AND_SAVE (l);
2252
2253 if (intel_syntax)
2254 operand_ok =
2255 i386_intel_operand (token_start,
2256 intel_float_operand (mnemonic));
2257 else
2258 operand_ok = i386_operand (token_start);
2259
2260 RESTORE_END_STRING (l);
2261 if (!operand_ok)
2262 return NULL;
2263 }
2264 else
2265 {
2266 if (expecting_operand)
2267 {
2268 expecting_operand_after_comma:
2269 as_bad (_("expecting operand after ','; got nothing"));
2270 return NULL;
2271 }
2272 if (*l == ',')
2273 {
2274 as_bad (_("expecting operand before ','; got nothing"));
2275 return NULL;
2276 }
2277 }
7f3f1ea2 2278
29b0f896
AM		 2279 /* Now *l must be either ',' or END_OF_INSN. */
2280 if (*l == ',')
2281 {
2282 if (*++l == END_OF_INSN)
2283 {
2284 /* Just skip it, if it's \n complain. */
2285 goto expecting_operand_after_comma;
2286 }
2287 expecting_operand = 1;
2288 }
2289 }
2290 return l;
2291}
7f3f1ea2 2292
050dfa73
MM		 2293static void
2294swap_imm_operands ()
2295{
2296 union i386_op temp_op;
2297 unsigned int temp_type;
2298 enum bfd_reloc_code_real temp_reloc;
2299 int xchg1 = 0;
2300 int xchg2 = 1;
2301
2302 temp_type = i.types[xchg2];
2303 i.types[xchg2] = i.types[xchg1];
2304 i.types[xchg1] = temp_type;
2305 temp_op = i.op[xchg2];
2306 i.op[xchg2] = i.op[xchg1];
2307 i.op[xchg1] = temp_op;
2308 temp_reloc = i.reloc[xchg2];
2309 i.reloc[xchg2] = i.reloc[xchg1];
2310 i.reloc[xchg1] = temp_reloc;
2311}
2312
2313
29b0f896
AM		 2314static void
2315swap_operands ()
2316{
2317 union i386_op temp_op;
2318 unsigned int temp_type;
f86103b7 2319 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 2320 int xchg1 = 0;
2321 int xchg2 = 0;
252b5132 2322
050dfa73
MM		 2323 if (i.operands == 4)
2324 /* There will be two exchanges in a 4 operand instruction.
2325 First exchange is the done inside this block.(1st and 4rth operand)
2326 The next exchange is done outside this block.(2nd and 3rd operand) */
2327 {
2328 xchg1 = 0;
2329 xchg2 = 3;
2330 temp_type = i.types[xchg2];
2331 i.types[xchg2] = i.types[xchg1];
2332 i.types[xchg1] = temp_type;
2333 temp_op = i.op[xchg2];
2334 i.op[xchg2] = i.op[xchg1];
2335 i.op[xchg1] = temp_op;
2336 temp_reloc = i.reloc[xchg2];
2337 i.reloc[xchg2] = i.reloc[xchg1];
2338 i.reloc[xchg1] = temp_reloc;
2339 xchg1 = 1;
2340 xchg2 = 2;
2341 }
2342
29b0f896
AM		 2343 if (i.operands == 2)
2344 {
2345 xchg1 = 0;
2346 xchg2 = 1;
2347 }
2348 else if (i.operands == 3)
2349 {
2350 xchg1 = 0;
2351 xchg2 = 2;
2352 }
2353 temp_type = i.types[xchg2];
2354 i.types[xchg2] = i.types[xchg1];
2355 i.types[xchg1] = temp_type;
2356 temp_op = i.op[xchg2];
2357 i.op[xchg2] = i.op[xchg1];
2358 i.op[xchg1] = temp_op;
2359 temp_reloc = i.reloc[xchg2];
2360 i.reloc[xchg2] = i.reloc[xchg1];
2361 i.reloc[xchg1] = temp_reloc;
2362
2363 if (i.mem_operands == 2)
2364 {
2365 const seg_entry *temp_seg;
2366 temp_seg = i.seg[0];
2367 i.seg[0] = i.seg[1];
2368 i.seg[1] = temp_seg;
2369 }
2370}
252b5132 2371
29b0f896
AM		 2372/* Try to ensure constant immediates are represented in the smallest
2373 opcode possible. */
2374static void
2375optimize_imm ()
2376{
2377 char guess_suffix = 0;
2378 int op;
252b5132 2379
29b0f896
AM		 2380 if (i.suffix)
2381 guess_suffix = i.suffix;
2382 else if (i.reg_operands)
2383 {
2384 /* Figure out a suffix from the last register operand specified.
2385 We can't do this properly yet, ie. excluding InOutPortReg,
2386 but the following works for instructions with immediates.
2387 In any case, we can't set i.suffix yet. */
2388 for (op = i.operands; --op >= 0;)
2389 if (i.types[op] & Reg)
252b5132 2390 {
29b0f896
AM		 2391 if (i.types[op] & Reg8)
2392 guess_suffix = BYTE_MNEM_SUFFIX;
2393 else if (i.types[op] & Reg16)
2394 guess_suffix = WORD_MNEM_SUFFIX;
2395 else if (i.types[op] & Reg32)
2396 guess_suffix = LONG_MNEM_SUFFIX;
2397 else if (i.types[op] & Reg64)
2398 guess_suffix = QWORD_MNEM_SUFFIX;
2399 break;
252b5132 2400 }
29b0f896
AM		 2401 }
2402 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2403 guess_suffix = WORD_MNEM_SUFFIX;
2404
2405 for (op = i.operands; --op >= 0;)
2406 if (i.types[op] & Imm)
2407 {
2408 switch (i.op[op].imms->X_op)
252b5132 2409 {
29b0f896
AM		 2410 case O_constant:
2411 /* If a suffix is given, this operand may be shortened. */
2412 switch (guess_suffix)
252b5132 2413 {
29b0f896
AM		 2414 case LONG_MNEM_SUFFIX:
2415 i.types[op] |= Imm32 | Imm64;
2416 break;
2417 case WORD_MNEM_SUFFIX:
2418 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2419 break;
2420 case BYTE_MNEM_SUFFIX:
2421 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2422 break;
252b5132 2423 }
252b5132 2424
29b0f896
AM		 2425 /* If this operand is at most 16 bits, convert it
2426 to a signed 16 bit number before trying to see
2427 whether it will fit in an even smaller size.
2428 This allows a 16-bit operand such as $0xffe0 to
2429 be recognised as within Imm8S range. */
2430 if ((i.types[op] & Imm16)
2431 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2432 {
29b0f896
AM		 2433 i.op[op].imms->X_add_number =
2434 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2435 }
2436 if ((i.types[op] & Imm32)
2437 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2438 == 0))
2439 {
2440 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2441 ^ ((offsetT) 1 << 31))
2442 - ((offsetT) 1 << 31));
2443 }
2444 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2445
29b0f896
AM		 2446 /* We must avoid matching of Imm32 templates when 64bit
2447 only immediate is available. */
2448 if (guess_suffix == QWORD_MNEM_SUFFIX)
2449 i.types[op] &= ~Imm32;
2450 break;
252b5132 2451
29b0f896
AM		 2452 case O_absent:
2453 case O_register:
2454 abort ();
2455
2456 /* Symbols and expressions. */
2457 default:
9cd96992
JB		 2458 /* Convert symbolic operand to proper sizes for matching, but don't
2459 prevent matching a set of insns that only supports sizes other
2460 than those matching the insn suffix. */
2461 {
2462 unsigned int mask, allowed = 0;
2463 const template *t;
2464
2465 for (t = current_templates->start; t < current_templates->end; ++t)
2466 allowed |= t->operand_types[op];
2467 switch (guess_suffix)
2468 {
2469 case QWORD_MNEM_SUFFIX:
2470 mask = Imm64 | Imm32S;
2471 break;
2472 case LONG_MNEM_SUFFIX:
2473 mask = Imm32;
2474 break;
2475 case WORD_MNEM_SUFFIX:
2476 mask = Imm16;
2477 break;
2478 case BYTE_MNEM_SUFFIX:
2479 mask = Imm8;
2480 break;
2481 default:
2482 mask = 0;
2483 break;
2484 }
64e74474
AM		 2485 if (mask & allowed)
2486 i.types[op] &= mask;
9cd96992 2487 }
29b0f896 2488 break;
252b5132 2489 }
29b0f896
AM		 2490 }
2491}
47926f60 2492
29b0f896
AM		 2493/* Try to use the smallest displacement type too. */
2494static void
2495optimize_disp ()
2496{
2497 int op;
3e73aa7c 2498
29b0f896 2499 for (op = i.operands; --op >= 0;)
b300c311 2500 if (i.types[op] & Disp)
252b5132 2501 {
b300c311 2502 if (i.op[op].disps->X_op == O_constant)
252b5132 2503 {
b300c311 2504 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2505
b300c311
L		 2506 if ((i.types[op] & Disp16)
2507 && (disp & ~(offsetT) 0xffff) == 0)
2508 {
2509 /* If this operand is at most 16 bits, convert
2510 to a signed 16 bit number and don't use 64bit
2511 displacement. */
2512 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2513 i.types[op] &= ~Disp64;
2514 }
2515 if ((i.types[op] & Disp32)
2516 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2517 {
2518 /* If this operand is at most 32 bits, convert
2519 to a signed 32 bit number and don't use 64bit
2520 displacement. */
2521 disp &= (((offsetT) 2 << 31) - 1);
2522 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2523 i.types[op] &= ~Disp64;
2524 }
2525 if (!disp && (i.types[op] & BaseIndex))
2526 {
2527 i.types[op] &= ~Disp;
2528 i.op[op].disps = 0;
2529 i.disp_operands--;
2530 }
2531 else if (flag_code == CODE_64BIT)
2532 {
2533 if (fits_in_signed_long (disp))
28a9d8f5
L		 2534 {
2535 i.types[op] &= ~Disp64;
2536 i.types[op] |= Disp32S;
2537 }
b300c311
L		 2538 if (fits_in_unsigned_long (disp))
2539 i.types[op] |= Disp32;
2540 }
2541 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2542 && fits_in_signed_byte (disp))
2543 i.types[op] |= Disp8;
252b5132 2544 }
67a4f2b7
AO		 2545 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2546 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2547 {
2548 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2549 i.op[op].disps, 0, i.reloc[op]);
2550 i.types[op] &= ~Disp;
2551 }
2552 else
b300c311
L		 2553 /* We only support 64bit displacement on constants. */
2554 i.types[op] &= ~Disp64;
252b5132 2555 }
29b0f896
AM		 2556}
2557
2558static int
2559match_template ()
2560{
2561 /* Points to template once we've found it. */
2562 const template *t;
2563 unsigned int overlap0, overlap1, overlap2;
2564 unsigned int found_reverse_match;
2565 int suffix_check;
2566
2567#define MATCH(overlap, given, template) \
2568 ((overlap & ~JumpAbsolute) \
2569 && (((given) & (BaseIndex | JumpAbsolute)) \
2570 == ((overlap) & (BaseIndex | JumpAbsolute))))
2571
2572 /* If given types r0 and r1 are registers they must be of the same type
2573 unless the expected operand type register overlap is null.
2574 Note that Acc in a template matches every size of reg. */
2575#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2576 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2577 || ((g0) & Reg) == ((g1) & Reg) \
2578 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2579
2580 overlap0 = 0;
2581 overlap1 = 0;
2582 overlap2 = 0;
2583 found_reverse_match = 0;
2584 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2585 ? No_bSuf
2586 : (i.suffix == WORD_MNEM_SUFFIX
2587 ? No_wSuf
2588 : (i.suffix == SHORT_MNEM_SUFFIX
2589 ? No_sSuf
2590 : (i.suffix == LONG_MNEM_SUFFIX
2591 ? No_lSuf
2592 : (i.suffix == QWORD_MNEM_SUFFIX
2593 ? No_qSuf
2594 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2595 ? No_xSuf : 0))))));
2596
45aa61fe 2597 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896
AM		 2598 {
2599 /* Must have right number of operands. */
2600 if (i.operands != t->operands)
2601 continue;
2602
2603 /* Check the suffix, except for some instructions in intel mode. */
2604 if ((t->opcode_modifier & suffix_check)
2605 && !(intel_syntax
9306ca4a 2606 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2607 continue;
2608
45aa61fe
AM		 2609 /* In general, don't allow 64-bit operands in 32-bit mode. */
2610 if (i.suffix == QWORD_MNEM_SUFFIX
2611 && flag_code != CODE_64BIT
2612 && (intel_syntax
2613 ? (!(t->opcode_modifier & IgnoreSize)
2614 && !intel_float_operand (t->name))
2615 : intel_float_operand (t->name) != 2)
2616 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2617 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2618 && (t->base_opcode != 0x0fc7
2619 || t->extension_opcode != 1 /* cmpxchg8b */))
2620 continue;
2621
29b0f896
AM		 2622 /* Do not verify operands when there are none. */
2623 else if (!t->operands)
2624 {
2625 if (t->cpu_flags & ~cpu_arch_flags)
2626 continue;
2627 /* We've found a match; break out of loop. */
2628 break;
2629 }
252b5132 2630
29b0f896
AM		 2631 overlap0 = i.types[0] & t->operand_types[0];
2632 switch (t->operands)
2633 {
2634 case 1:
2635 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2636 continue;
2637 break;
2638 case 2:
2639 case 3:
2640 overlap1 = i.types[1] & t->operand_types[1];
2641 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2642 || !MATCH (overlap1, i.types[1], t->operand_types[1])
cb712a9e 2643 /* monitor in SSE3 is a very special case. The first
708587a4 2644 register and the second register may have different
cb712a9e
L		 2645 sizes. */
2646 || !((t->base_opcode == 0x0f01
2647 && t->extension_opcode == 0xc8)
2648 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2649 t->operand_types[0],
2650 overlap1, i.types[1],
2651 t->operand_types[1])))
29b0f896
AM		 2652 {
2653 /* Check if other direction is valid ... */
2654 if ((t->opcode_modifier & (D | FloatD)) == 0)
2655 continue;
2656
2657 /* Try reversing direction of operands. */
2658 overlap0 = i.types[0] & t->operand_types[1];
2659 overlap1 = i.types[1] & t->operand_types[0];
2660 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2661 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2662 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2663 t->operand_types[1],
2664 overlap1, i.types[1],
2665 t->operand_types[0]))
2666 {
2667 /* Does not match either direction. */
2668 continue;
2669 }
2670 /* found_reverse_match holds which of D or FloatDR
2671 we've found. */
2672 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2673 }
2674 /* Found a forward 2 operand match here. */
2675 else if (t->operands == 3)
2676 {
2677 /* Here we make use of the fact that there are no
2678 reverse match 3 operand instructions, and all 3
2679 operand instructions only need to be checked for
2680 register consistency between operands 2 and 3. */
2681 overlap2 = i.types[2] & t->operand_types[2];
2682 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2683 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2684 t->operand_types[1],
2685 overlap2, i.types[2],
2686 t->operand_types[2]))
2687
2688 continue;
2689 }
2690 /* Found either forward/reverse 2 or 3 operand match here:
2691 slip through to break. */
2692 }
2693 if (t->cpu_flags & ~cpu_arch_flags)
2694 {
2695 found_reverse_match = 0;
2696 continue;
2697 }
2698 /* We've found a match; break out of loop. */
2699 break;
2700 }
2701
2702 if (t == current_templates->end)
2703 {
2704 /* We found no match. */
2705 as_bad (_("suffix or operands invalid for `%s'"),
2706 current_templates->start->name);
2707 return 0;
2708 }
252b5132 2709
29b0f896
AM		 2710 if (!quiet_warnings)
2711 {
2712 if (!intel_syntax
2713 && ((i.types[0] & JumpAbsolute)
2714 != (t->operand_types[0] & JumpAbsolute)))
2715 {
2716 as_warn (_("indirect %s without `*'"), t->name);
2717 }
2718
2719 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2720 == (IsPrefix | IgnoreSize))
2721 {
2722 /* Warn them that a data or address size prefix doesn't
2723 affect assembly of the next line of code. */
2724 as_warn (_("stand-alone `%s' prefix"), t->name);
2725 }
2726 }
2727
2728 /* Copy the template we found. */
2729 i.tm = *t;
2730 if (found_reverse_match)
2731 {
2732 /* If we found a reverse match we must alter the opcode
2733 direction bit. found_reverse_match holds bits to change
2734 (different for int & float insns). */
2735
2736 i.tm.base_opcode ^= found_reverse_match;
2737
2738 i.tm.operand_types[0] = t->operand_types[1];
2739 i.tm.operand_types[1] = t->operand_types[0];
2740 }
2741
2742 return 1;
2743}
2744
2745static int
2746check_string ()
2747{
2748 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2749 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2750 {
2751 if (i.seg[0] != NULL && i.seg[0] != &es)
2752 {
2753 as_bad (_("`%s' operand %d must use `%%es' segment"),
2754 i.tm.name,
2755 mem_op + 1);
2756 return 0;
2757 }
2758 /* There's only ever one segment override allowed per instruction.
2759 This instruction possibly has a legal segment override on the
2760 second operand, so copy the segment to where non-string
2761 instructions store it, allowing common code. */
2762 i.seg[0] = i.seg[1];
2763 }
2764 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2765 {
2766 if (i.seg[1] != NULL && i.seg[1] != &es)
2767 {
2768 as_bad (_("`%s' operand %d must use `%%es' segment"),
2769 i.tm.name,
2770 mem_op + 2);
2771 return 0;
2772 }
2773 }
2774 return 1;
2775}
2776
2777static int
543613e9 2778process_suffix (void)
29b0f896
AM		 2779{
2780 /* If matched instruction specifies an explicit instruction mnemonic
2781 suffix, use it. */
2782 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2783 {
2784 if (i.tm.opcode_modifier & Size16)
2785 i.suffix = WORD_MNEM_SUFFIX;
2786 else if (i.tm.opcode_modifier & Size64)
2787 i.suffix = QWORD_MNEM_SUFFIX;
2788 else
2789 i.suffix = LONG_MNEM_SUFFIX;
2790 }
2791 else if (i.reg_operands)
2792 {
2793 /* If there's no instruction mnemonic suffix we try to invent one
2794 based on register operands. */
2795 if (!i.suffix)
2796 {
2797 /* We take i.suffix from the last register operand specified,
2798 Destination register type is more significant than source
2799 register type. */
2800 int op;
543613e9 2801
29b0f896
AM		 2802 for (op = i.operands; --op >= 0;)
2803 if ((i.types[op] & Reg)
2804 && !(i.tm.operand_types[op] & InOutPortReg))
2805 {
2806 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2807 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2808 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2809 LONG_MNEM_SUFFIX);
2810 break;
2811 }
2812 }
2813 else if (i.suffix == BYTE_MNEM_SUFFIX)
2814 {
2815 if (!check_byte_reg ())
2816 return 0;
2817 }
2818 else if (i.suffix == LONG_MNEM_SUFFIX)
2819 {
2820 if (!check_long_reg ())
2821 return 0;
2822 }
2823 else if (i.suffix == QWORD_MNEM_SUFFIX)
2824 {
2825 if (!check_qword_reg ())
2826 return 0;
2827 }
2828 else if (i.suffix == WORD_MNEM_SUFFIX)
2829 {
2830 if (!check_word_reg ())
2831 return 0;
2832 }
2833 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2834 /* Do nothing if the instruction is going to ignore the prefix. */
2835 ;
2836 else
2837 abort ();
2838 }
9306ca4a
JB		 2839 else if ((i.tm.opcode_modifier & DefaultSize)
2840 && !i.suffix
2841 /* exclude fldenv/frstor/fsave/fstenv */
2842 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2843 {
2844 i.suffix = stackop_size;
2845 }
9306ca4a
JB		 2846 else if (intel_syntax
2847 && !i.suffix
2848 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2849 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2850 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2851 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2852 {
2853 switch (flag_code)
2854 {
2855 case CODE_64BIT:
2856 if (!(i.tm.opcode_modifier & No_qSuf))
2857 {
2858 i.suffix = QWORD_MNEM_SUFFIX;
2859 break;
2860 }
2861 case CODE_32BIT:
2862 if (!(i.tm.opcode_modifier & No_lSuf))
2863 i.suffix = LONG_MNEM_SUFFIX;
2864 break;
2865 case CODE_16BIT:
2866 if (!(i.tm.opcode_modifier & No_wSuf))
2867 i.suffix = WORD_MNEM_SUFFIX;
2868 break;
2869 }
2870 }
252b5132 2871
9306ca4a 2872 if (!i.suffix)
29b0f896 2873 {
9306ca4a
JB		 2874 if (!intel_syntax)
2875 {
2876 if (i.tm.opcode_modifier & W)
2877 {
2878 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2879 return 0;
2880 }
2881 }
2882 else
2883 {
64e74474
AM		 2884 unsigned int suffixes = (~i.tm.opcode_modifier
2885 & (No_bSuf
2886 | No_wSuf
2887 | No_lSuf
2888 | No_sSuf
2889 | No_xSuf
2890 | No_qSuf));
9306ca4a
JB		 2891
2892 if ((i.tm.opcode_modifier & W)
2893 || ((suffixes & (suffixes - 1))
2894 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2895 {
2896 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2897 return 0;
2898 }
2899 }
29b0f896 2900 }
252b5132 2901
9306ca4a
JB		 2902 /* Change the opcode based on the operand size given by i.suffix;
2903 We don't need to change things for byte insns. */
2904
29b0f896
AM		 2905 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2906 {
2907 /* It's not a byte, select word/dword operation. */
2908 if (i.tm.opcode_modifier & W)
2909 {
2910 if (i.tm.opcode_modifier & ShortForm)
2911 i.tm.base_opcode |= 8;
2912 else
2913 i.tm.base_opcode |= 1;
2914 }
0f3f3d8b 2915
29b0f896
AM		 2916 /* Now select between word & dword operations via the operand
2917 size prefix, except for instructions that will ignore this
2918 prefix anyway. */
cb712a9e
L		 2919 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2920 {
2921 /* monitor in SSE3 is a very special case. The default size
2922 of AX is the size of mode. The address size override
2923 prefix will change the size of AX. */
2924 if (i.op->regs[0].reg_type &
2925 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2926 if (!add_prefix (ADDR_PREFIX_OPCODE))
2927 return 0;
2928 }
2929 else if (i.suffix != QWORD_MNEM_SUFFIX
2930 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2931 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2932 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2933 || (flag_code == CODE_64BIT
2934 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2935 {
2936 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2937
29b0f896
AM		 2938 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2939 prefix = ADDR_PREFIX_OPCODE;
252b5132 2940
29b0f896
AM		 2941 if (!add_prefix (prefix))
2942 return 0;
24eab124 2943 }
252b5132 2944
29b0f896
AM		 2945 /* Set mode64 for an operand. */
2946 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2947 && flag_code == CODE_64BIT
29b0f896 2948 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L		 2949 {
2950 /* Special case for xchg %rax,%rax. It is NOP and doesn't
2951 need rex64. */
2952 if (i.operands != 2
2953 || i.types [0] != (Acc | Reg64)
2954 || i.types [1] != (Acc | Reg64)
2955 || strcmp (i.tm.name, "xchg") != 0)
2956 i.rex |= REX_MODE64;
2957 }
3e73aa7c 2958
29b0f896
AM		 2959 /* Size floating point instruction. */
2960 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 2961 if (i.tm.opcode_modifier & FloatMF)
2962 i.tm.base_opcode ^= 4;
29b0f896 2963 }
7ecd2f8b 2964
29b0f896
AM		 2965 return 1;
2966}
3e73aa7c 2967
29b0f896 2968static int
543613e9 2969check_byte_reg (void)
29b0f896
AM		 2970{
2971 int op;
543613e9 2972
29b0f896
AM		 2973 for (op = i.operands; --op >= 0;)
2974 {
2975 /* If this is an eight bit register, it's OK. If it's the 16 or
2976 32 bit version of an eight bit register, we will just use the
2977 low portion, and that's OK too. */
2978 if (i.types[op] & Reg8)
2979 continue;
2980
2981 /* movzx and movsx should not generate this warning. */
2982 if (intel_syntax
2983 && (i.tm.base_opcode == 0xfb7
2984 || i.tm.base_opcode == 0xfb6
2985 || i.tm.base_opcode == 0x63
2986 || i.tm.base_opcode == 0xfbe
2987 || i.tm.base_opcode == 0xfbf))
2988 continue;
2989
65ec77d2 2990 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 2991 {
2992 /* Prohibit these changes in the 64bit mode, since the
2993 lowering is more complicated. */
2994 if (flag_code == CODE_64BIT
2995 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2996 {
0f3f3d8b 2997 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2998 i.op[op].regs->reg_name,
2999 i.suffix);
3000 return 0;
3001 }
3002#if REGISTER_WARNINGS
3003 if (!quiet_warnings
3004 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3005 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3006 (i.op[op].regs + (i.types[op] & Reg16
3007 ? REGNAM_AL - REGNAM_AX
3008 : REGNAM_AL - REGNAM_EAX))->reg_name,
3009 i.op[op].regs->reg_name,
3010 i.suffix);
3011#endif
3012 continue;
3013 }
3014 /* Any other register is bad. */
3015 if (i.types[op] & (Reg | RegMMX | RegXMM
3016 | SReg2 | SReg3
3017 | Control | Debug | Test
3018 | FloatReg | FloatAcc))
3019 {
3020 as_bad (_("`%%%s' not allowed with `%s%c'"),
3021 i.op[op].regs->reg_name,
3022 i.tm.name,
3023 i.suffix);
3024 return 0;
3025 }
3026 }
3027 return 1;
3028}
3029
3030static int
3031check_long_reg ()
3032{
3033 int op;
3034
3035 for (op = i.operands; --op >= 0;)
3036 /* Reject eight bit registers, except where the template requires
3037 them. (eg. movzb) */
3038 if ((i.types[op] & Reg8) != 0
3039 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3040 {
3041 as_bad (_("`%%%s' not allowed with `%s%c'"),
3042 i.op[op].regs->reg_name,
3043 i.tm.name,
3044 i.suffix);
3045 return 0;
3046 }
3047 /* Warn if the e prefix on a general reg is missing. */
3048 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3049 && (i.types[op] & Reg16) != 0
3050 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3051 {
3052 /* Prohibit these changes in the 64bit mode, since the
3053 lowering is more complicated. */
3054 if (flag_code == CODE_64BIT)
252b5132 3055 {
0f3f3d8b 3056 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3057 i.op[op].regs->reg_name,
3058 i.suffix);
3059 return 0;
252b5132 3060 }
29b0f896
AM		 3061#if REGISTER_WARNINGS
3062 else
3063 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3064 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3065 i.op[op].regs->reg_name,
3066 i.suffix);
3067#endif
252b5132 3068 }
29b0f896
AM		 3069 /* Warn if the r prefix on a general reg is missing. */
3070 else if ((i.types[op] & Reg64) != 0
3071 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 3072 {
0f3f3d8b 3073 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3074 i.op[op].regs->reg_name,
3075 i.suffix);
3076 return 0;
3077 }
3078 return 1;
3079}
252b5132 3080
29b0f896
AM		 3081static int
3082check_qword_reg ()
3083{
3084 int op;
252b5132 3085
29b0f896
AM		 3086 for (op = i.operands; --op >= 0; )
3087 /* Reject eight bit registers, except where the template requires
3088 them. (eg. movzb) */
3089 if ((i.types[op] & Reg8) != 0
3090 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3091 {
3092 as_bad (_("`%%%s' not allowed with `%s%c'"),
3093 i.op[op].regs->reg_name,
3094 i.tm.name,
3095 i.suffix);
3096 return 0;
3097 }
3098 /* Warn if the e prefix on a general reg is missing. */
3099 else if (((i.types[op] & Reg16) != 0
3100 || (i.types[op] & Reg32) != 0)
3101 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3102 {
3103 /* Prohibit these changes in the 64bit mode, since the
3104 lowering is more complicated. */
0f3f3d8b 3105 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3106 i.op[op].regs->reg_name,
3107 i.suffix);
3108 return 0;
252b5132 3109 }
29b0f896
AM		 3110 return 1;
3111}
252b5132 3112
29b0f896
AM		 3113static int
3114check_word_reg ()
3115{
3116 int op;
3117 for (op = i.operands; --op >= 0;)
3118 /* Reject eight bit registers, except where the template requires
3119 them. (eg. movzb) */
3120 if ((i.types[op] & Reg8) != 0
3121 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3122 {
3123 as_bad (_("`%%%s' not allowed with `%s%c'"),
3124 i.op[op].regs->reg_name,
3125 i.tm.name,
3126 i.suffix);
3127 return 0;
3128 }
3129 /* Warn if the e prefix on a general reg is present. */
3130 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3131 && (i.types[op] & Reg32) != 0
3132 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 3133 {
29b0f896
AM		 3134 /* Prohibit these changes in the 64bit mode, since the
3135 lowering is more complicated. */
3136 if (flag_code == CODE_64BIT)
252b5132 3137 {
0f3f3d8b 3138 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3139 i.op[op].regs->reg_name,
3140 i.suffix);
3141 return 0;
252b5132 3142 }
29b0f896
AM		 3143 else
3144#if REGISTER_WARNINGS
3145 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3146 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3147 i.op[op].regs->reg_name,
3148 i.suffix);
3149#endif
3150 }
3151 return 1;
3152}
252b5132 3153
29b0f896
AM		 3154static int
3155finalize_imm ()
3156{
3157 unsigned int overlap0, overlap1, overlap2;
3158
3159 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 3160 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 3161 && overlap0 != Imm8 && overlap0 != Imm8S
3162 && overlap0 != Imm16 && overlap0 != Imm32S
3163 && overlap0 != Imm32 && overlap0 != Imm64)
3164 {
3165 if (i.suffix)
3166 {
3167 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3168 ? Imm8 | Imm8S
3169 : (i.suffix == WORD_MNEM_SUFFIX
3170 ? Imm16
3171 : (i.suffix == QWORD_MNEM_SUFFIX
3172 ? Imm64 | Imm32S
3173 : Imm32)));
3174 }
3175 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3176 || overlap0 == (Imm16 | Imm32)
3177 || overlap0 == (Imm16 | Imm32S))
3178 {
3179 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3180 ? Imm16 : Imm32S);
3181 }
3182 if (overlap0 != Imm8 && overlap0 != Imm8S
3183 && overlap0 != Imm16 && overlap0 != Imm32S
3184 && overlap0 != Imm32 && overlap0 != Imm64)
3185 {
3186 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
3187 return 0;
3188 }
3189 }
3190 i.types[0] = overlap0;
3191
3192 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 3193 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 3194 && overlap1 != Imm8 && overlap1 != Imm8S
3195 && overlap1 != Imm16 && overlap1 != Imm32S
3196 && overlap1 != Imm32 && overlap1 != Imm64)
3197 {
3198 if (i.suffix)
3199 {
3200 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3201 ? Imm8 | Imm8S
3202 : (i.suffix == WORD_MNEM_SUFFIX
3203 ? Imm16
3204 : (i.suffix == QWORD_MNEM_SUFFIX
3205 ? Imm64 | Imm32S
3206 : Imm32)));
3207 }
3208 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3209 || overlap1 == (Imm16 | Imm32)
3210 || overlap1 == (Imm16 | Imm32S))
3211 {
3212 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3213 ? Imm16 : Imm32S);
3214 }
3215 if (overlap1 != Imm8 && overlap1 != Imm8S
3216 && overlap1 != Imm16 && overlap1 != Imm32S
3217 && overlap1 != Imm32 && overlap1 != Imm64)
3218 {
3219 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
3220 return 0;
3221 }
3222 }
3223 i.types[1] = overlap1;
3224
3225 overlap2 = i.types[2] & i.tm.operand_types[2];
3226 assert ((overlap2 & Imm) == 0);
3227 i.types[2] = overlap2;
3228
3229 return 1;
3230}
3231
3232static int
3233process_operands ()
3234{
3235 /* Default segment register this instruction will use for memory
3236 accesses. 0 means unknown. This is only for optimizing out
3237 unnecessary segment overrides. */
3238 const seg_entry *default_seg = 0;
3239
3240 /* The imul $imm, %reg instruction is converted into
3241 imul $imm, %reg, %reg, and the clr %reg instruction
3242 is converted into xor %reg, %reg. */
3243 if (i.tm.opcode_modifier & regKludge)
3244 {
3245 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3246 /* Pretend we saw the extra register operand. */
3247 assert (i.op[first_reg_op + 1].regs == 0);
3248 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3249 i.types[first_reg_op + 1] = i.types[first_reg_op];
3250 i.reg_operands = 2;
3251 }
3252
3253 if (i.tm.opcode_modifier & ShortForm)
3254 {
3255 /* The register or float register operand is in operand 0 or 1. */
3256 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3257 /* Register goes in low 3 bits of opcode. */
3258 i.tm.base_opcode |= i.op[op].regs->reg_num;
3259 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3260 i.rex |= REX_EXTZ;
3261 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
3262 {
3263 /* Warn about some common errors, but press on regardless.
3264 The first case can be generated by gcc (<= 2.8.1). */
3265 if (i.operands == 2)
3266 {
3267 /* Reversed arguments on faddp, fsubp, etc. */
3268 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3269 i.op[1].regs->reg_name,
3270 i.op[0].regs->reg_name);
3271 }
3272 else
3273 {
3274 /* Extraneous `l' suffix on fp insn. */
3275 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3276 i.op[0].regs->reg_name);
3277 }
3278 }
3279 }
3280 else if (i.tm.opcode_modifier & Modrm)
3281 {
3282 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3283 must be put into the modrm byte). Now, we make the modrm and
3284 index base bytes based on all the info we've collected. */
29b0f896
AM		 3285
3286 default_seg = build_modrm_byte ();
3287 }
3288 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
3289 {
3290 if (i.tm.base_opcode == POP_SEG_SHORT
3291 && i.op[0].regs->reg_num == 1)
3292 {
3293 as_bad (_("you can't `pop %%cs'"));
3294 return 0;
3295 }
3296 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3297 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3298 i.rex |= REX_EXTZ;
3299 }
3300 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
3301 {
3302 default_seg = &ds;
3303 }
3304 else if ((i.tm.opcode_modifier & IsString) != 0)
3305 {
3306 /* For the string instructions that allow a segment override
3307 on one of their operands, the default segment is ds. */
3308 default_seg = &ds;
3309 }
3310
30123838
JB		 3311 if ((i.tm.base_opcode == 0x8d /* lea */
3312 || (i.tm.cpu_flags & CpuSVME))
3313 && i.seg[0] && !quiet_warnings)
3314 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3315
3316 /* If a segment was explicitly specified, and the specified segment
3317 is not the default, use an opcode prefix to select it. If we
3318 never figured out what the default segment is, then default_seg
3319 will be zero at this point, and the specified segment prefix will
3320 always be used. */
29b0f896
AM		 3321 if ((i.seg[0]) && (i.seg[0] != default_seg))
3322 {
3323 if (!add_prefix (i.seg[0]->seg_prefix))
3324 return 0;
3325 }
3326 return 1;
3327}
3328
3329static const seg_entry *
3330build_modrm_byte ()
3331{
3332 const seg_entry *default_seg = 0;
3333
3334 /* i.reg_operands MUST be the number of real register operands;
3335 implicit registers do not count. */
3336 if (i.reg_operands == 2)
3337 {
3338 unsigned int source, dest;
3339 source = ((i.types[0]
3340 & (Reg | RegMMX | RegXMM
3341 | SReg2 | SReg3
3342 | Control | Debug | Test))
3343 ? 0 : 1);
050dfa73
MM		 3344
3345 /* In 4 operands instructions with 2 immediate operands, the first two are immediate
3346 bytes and hence source operand will be in the next byte after the immediates */
3347 if ((i.operands == 4)&&(i.imm_operands=2)) source++;
29b0f896
AM		 3348 dest = source + 1;
3349
3350 i.rm.mode = 3;
3351 /* One of the register operands will be encoded in the i.tm.reg
3352 field, the other in the combined i.tm.mode and i.tm.regmem
3353 fields. If no form of this instruction supports a memory
3354 destination operand, then we assume the source operand may
3355 sometimes be a memory operand and so we need to store the
3356 destination in the i.rm.reg field. */
3357 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3358 {
3359 i.rm.reg = i.op[dest].regs->reg_num;
3360 i.rm.regmem = i.op[source].regs->reg_num;
3361 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3362 i.rex |= REX_EXTX;
3363 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3364 i.rex |= REX_EXTZ;
3365 }
3366 else
3367 {
3368 i.rm.reg = i.op[source].regs->reg_num;
3369 i.rm.regmem = i.op[dest].regs->reg_num;
3370 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3371 i.rex |= REX_EXTZ;
3372 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3373 i.rex |= REX_EXTX;
3374 }
c4a530c5
JB		 3375 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3376 {
3377 if (!((i.types[0] | i.types[1]) & Control))
3378 abort ();
3379 i.rex &= ~(REX_EXTX | REX_EXTZ);
3380 add_prefix (LOCK_PREFIX_OPCODE);
3381 }
29b0f896
AM		 3382 }
3383 else
3384 { /* If it's not 2 reg operands... */
3385 if (i.mem_operands)
3386 {
3387 unsigned int fake_zero_displacement = 0;
3388 unsigned int op = ((i.types[0] & AnyMem)
3389 ? 0
3390 : (i.types[1] & AnyMem) ? 1 : 2);
3391
3392 default_seg = &ds;
3393
3394 if (i.base_reg == 0)
3395 {
3396 i.rm.mode = 0;
3397 if (!i.disp_operands)
3398 fake_zero_displacement = 1;
3399 if (i.index_reg == 0)
3400 {
3401 /* Operand is just <disp> */
20f0a1fc 3402 if (flag_code == CODE_64BIT)
29b0f896
AM		 3403 {
3404 /* 64bit mode overwrites the 32bit absolute
3405 addressing by RIP relative addressing and
3406 absolute addressing is encoded by one of the
3407 redundant SIB forms. */
3408 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3409 i.sib.base = NO_BASE_REGISTER;
3410 i.sib.index = NO_INDEX_REGISTER;
20f0a1fc
NC		 3411 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
3412 }
3413 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3414 {
3415 i.rm.regmem = NO_BASE_REGISTER_16;
3416 i.types[op] = Disp16;
3417 }
3418 else
3419 {
3420 i.rm.regmem = NO_BASE_REGISTER;
3421 i.types[op] = Disp32;
29b0f896
AM		 3422 }
3423 }
3424 else /* !i.base_reg && i.index_reg */
3425 {
3426 i.sib.index = i.index_reg->reg_num;
3427 i.sib.base = NO_BASE_REGISTER;
3428 i.sib.scale = i.log2_scale_factor;
3429 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3430 i.types[op] &= ~Disp;
3431 if (flag_code != CODE_64BIT)
3432 i.types[op] |= Disp32; /* Must be 32 bit */
3433 else
3434 i.types[op] |= Disp32S;
3435 if ((i.index_reg->reg_flags & RegRex) != 0)
3436 i.rex |= REX_EXTY;
3437 }
3438 }
3439 /* RIP addressing for 64bit mode. */
3440 else if (i.base_reg->reg_type == BaseIndex)
3441 {
3442 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3443 i.types[op] &= ~ Disp;
29b0f896
AM		 3444 i.types[op] |= Disp32S;
3445 i.flags[op] = Operand_PCrel;
20f0a1fc
NC		 3446 if (! i.disp_operands)
3447 fake_zero_displacement = 1;
29b0f896
AM		 3448 }
3449 else if (i.base_reg->reg_type & Reg16)
3450 {
3451 switch (i.base_reg->reg_num)
3452 {
3453 case 3: /* (%bx) */
3454 if (i.index_reg == 0)
3455 i.rm.regmem = 7;
3456 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3457 i.rm.regmem = i.index_reg->reg_num - 6;
3458 break;
3459 case 5: /* (%bp) */
3460 default_seg = &ss;
3461 if (i.index_reg == 0)
3462 {
3463 i.rm.regmem = 6;
3464 if ((i.types[op] & Disp) == 0)
3465 {
3466 /* fake (%bp) into 0(%bp) */
3467 i.types[op] |= Disp8;
252b5132 3468 fake_zero_displacement = 1;
29b0f896
AM		 3469 }
3470 }
3471 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3472 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3473 break;
3474 default: /* (%si) -> 4 or (%di) -> 5 */
3475 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3476 }
3477 i.rm.mode = mode_from_disp_size (i.types[op]);
3478 }
3479 else /* i.base_reg and 32/64 bit mode */
3480 {
3481 if (flag_code == CODE_64BIT
3482 && (i.types[op] & Disp))
20f0a1fc
NC		 3483 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3484
29b0f896
AM		 3485 i.rm.regmem = i.base_reg->reg_num;
3486 if ((i.base_reg->reg_flags & RegRex) != 0)
3487 i.rex |= REX_EXTZ;
3488 i.sib.base = i.base_reg->reg_num;
3489 /* x86-64 ignores REX prefix bit here to avoid decoder
3490 complications. */
3491 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3492 {
3493 default_seg = &ss;
3494 if (i.disp_operands == 0)
3495 {
3496 fake_zero_displacement = 1;
3497 i.types[op] |= Disp8;
3498 }
3499 }
3500 else if (i.base_reg->reg_num == ESP_REG_NUM)
3501 {
3502 default_seg = &ss;
3503 }
3504 i.sib.scale = i.log2_scale_factor;
3505 if (i.index_reg == 0)
3506 {
3507 /* <disp>(%esp) becomes two byte modrm with no index
3508 register. We've already stored the code for esp
3509 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3510 Any base register besides %esp will not use the
3511 extra modrm byte. */
3512 i.sib.index = NO_INDEX_REGISTER;
3513#if !SCALE1_WHEN_NO_INDEX
3514 /* Another case where we force the second modrm byte. */
3515 if (i.log2_scale_factor)
3516 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3517#endif
29b0f896
AM		 3518 }
3519 else
3520 {
3521 i.sib.index = i.index_reg->reg_num;
3522 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3523 if ((i.index_reg->reg_flags & RegRex) != 0)
3524 i.rex |= REX_EXTY;
3525 }
67a4f2b7
AO		 3526
3527 if (i.disp_operands
3528 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3529 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3530 i.rm.mode = 0;
3531 else
3532 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3533 }
252b5132 3534
29b0f896
AM		 3535 if (fake_zero_displacement)
3536 {
3537 /* Fakes a zero displacement assuming that i.types[op]
3538 holds the correct displacement size. */
3539 expressionS *exp;
3540
3541 assert (i.op[op].disps == 0);
3542 exp = &disp_expressions[i.disp_operands++];
3543 i.op[op].disps = exp;
3544 exp->X_op = O_constant;
3545 exp->X_add_number = 0;
3546 exp->X_add_symbol = (symbolS *) 0;
3547 exp->X_op_symbol = (symbolS *) 0;
3548 }
3549 }
252b5132 3550
29b0f896
AM		 3551 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3552 (if any) based on i.tm.extension_opcode. Again, we must be
3553 careful to make sure that segment/control/debug/test/MMX
3554 registers are coded into the i.rm.reg field. */
3555 if (i.reg_operands)
3556 {
3557 unsigned int op =
3558 ((i.types[0]
3559 & (Reg | RegMMX | RegXMM
3560 | SReg2 | SReg3
3561 | Control | Debug | Test))
3562 ? 0
3563 : ((i.types[1]
3564 & (Reg | RegMMX | RegXMM
3565 | SReg2 | SReg3
3566 | Control | Debug | Test))
3567 ? 1
3568 : 2));
3569 /* If there is an extension opcode to put here, the register
3570 number must be put into the regmem field. */
3571 if (i.tm.extension_opcode != None)
3572 {
3573 i.rm.regmem = i.op[op].regs->reg_num;
3574 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3575 i.rex |= REX_EXTZ;
3576 }
3577 else
3578 {
3579 i.rm.reg = i.op[op].regs->reg_num;
3580 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3581 i.rex |= REX_EXTX;
3582 }
252b5132 3583
29b0f896
AM		 3584 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3585 must set it to 3 to indicate this is a register operand
3586 in the regmem field. */
3587 if (!i.mem_operands)
3588 i.rm.mode = 3;
3589 }
252b5132 3590
29b0f896
AM		 3591 /* Fill in i.rm.reg field with extension opcode (if any). */
3592 if (i.tm.extension_opcode != None)
3593 i.rm.reg = i.tm.extension_opcode;
3594 }
3595 return default_seg;
3596}
252b5132 3597
29b0f896
AM		 3598static void
3599output_branch ()
3600{
3601 char *p;
3602 int code16;
3603 int prefix;
3604 relax_substateT subtype;
3605 symbolS *sym;
3606 offsetT off;
3607
3608 code16 = 0;
3609 if (flag_code == CODE_16BIT)
3610 code16 = CODE16;
3611
3612 prefix = 0;
3613 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3614 {
29b0f896
AM		 3615 prefix = 1;
3616 i.prefixes -= 1;
3617 code16 ^= CODE16;
252b5132 3618 }
29b0f896
AM		 3619 /* Pentium4 branch hints. */
3620 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3621 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3622 {
29b0f896
AM		 3623 prefix++;
3624 i.prefixes--;
3625 }
3626 if (i.prefix[REX_PREFIX] != 0)
3627 {
3628 prefix++;
3629 i.prefixes--;
2f66722d
AM		 3630 }
3631
29b0f896
AM		 3632 if (i.prefixes != 0 && !intel_syntax)
3633 as_warn (_("skipping prefixes on this instruction"));
3634
3635 /* It's always a symbol; End frag & setup for relax.
3636 Make sure there is enough room in this frag for the largest
3637 instruction we may generate in md_convert_frag. This is 2
3638 bytes for the opcode and room for the prefix and largest
3639 displacement. */
3640 frag_grow (prefix + 2 + 4);
3641 /* Prefix and 1 opcode byte go in fr_fix. */
3642 p = frag_more (prefix + 1);
3643 if (i.prefix[DATA_PREFIX] != 0)
3644 *p++ = DATA_PREFIX_OPCODE;
3645 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3646 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3647 *p++ = i.prefix[SEG_PREFIX];
3648 if (i.prefix[REX_PREFIX] != 0)
3649 *p++ = i.prefix[REX_PREFIX];
3650 *p = i.tm.base_opcode;
3651
3652 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3653 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3654 else if ((cpu_arch_flags & Cpu386) != 0)
3655 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3656 else
3657 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3658 subtype |= code16;
3e73aa7c 3659
29b0f896
AM		 3660 sym = i.op[0].disps->X_add_symbol;
3661 off = i.op[0].disps->X_add_number;
3e73aa7c 3662
29b0f896
AM		 3663 if (i.op[0].disps->X_op != O_constant
3664 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3665 {
29b0f896
AM		 3666 /* Handle complex expressions. */
3667 sym = make_expr_symbol (i.op[0].disps);
3668 off = 0;
3669 }
3e73aa7c 3670
29b0f896
AM		 3671 /* 1 possible extra opcode + 4 byte displacement go in var part.
3672 Pass reloc in fr_var. */
3673 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3674}
3e73aa7c 3675
29b0f896
AM		 3676static void
3677output_jump ()
3678{
3679 char *p;
3680 int size;
3e02c1cc 3681 fixS *fixP;
29b0f896
AM		 3682
3683 if (i.tm.opcode_modifier & JumpByte)
3684 {
3685 /* This is a loop or jecxz type instruction. */
3686 size = 1;
3687 if (i.prefix[ADDR_PREFIX] != 0)
3688 {
3689 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3690 i.prefixes -= 1;
3691 }
3692 /* Pentium4 branch hints. */
3693 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3694 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3695 {
3696 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3697 i.prefixes--;
3e73aa7c
JH		 3698 }
3699 }
29b0f896
AM		 3700 else
3701 {
3702 int code16;
3e73aa7c 3703
29b0f896
AM		 3704 code16 = 0;
3705 if (flag_code == CODE_16BIT)
3706 code16 = CODE16;
3e73aa7c 3707
29b0f896
AM		 3708 if (i.prefix[DATA_PREFIX] != 0)
3709 {
3710 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3711 i.prefixes -= 1;
3712 code16 ^= CODE16;
3713 }
252b5132 3714
29b0f896
AM		 3715 size = 4;
3716 if (code16)
3717 size = 2;
3718 }
9fcc94b6 3719
29b0f896
AM		 3720 if (i.prefix[REX_PREFIX] != 0)
3721 {
3722 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3723 i.prefixes -= 1;
3724 }
252b5132 3725
29b0f896
AM		 3726 if (i.prefixes != 0 && !intel_syntax)
3727 as_warn (_("skipping prefixes on this instruction"));
e0890092 3728
29b0f896
AM		 3729 p = frag_more (1 + size);
3730 *p++ = i.tm.base_opcode;
e0890092 3731
3e02c1cc
AM		 3732 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3733 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3734
3735 /* All jumps handled here are signed, but don't use a signed limit
3736 check for 32 and 16 bit jumps as we want to allow wrap around at
3737 4G and 64k respectively. */
3738 if (size == 1)
3739 fixP->fx_signed = 1;
29b0f896 3740}
e0890092 3741
29b0f896
AM		 3742static void
3743output_interseg_jump ()
3744{
3745 char *p;
3746 int size;
3747 int prefix;
3748 int code16;
252b5132 3749
29b0f896
AM		 3750 code16 = 0;
3751 if (flag_code == CODE_16BIT)
3752 code16 = CODE16;
a217f122 3753
29b0f896
AM		 3754 prefix = 0;
3755 if (i.prefix[DATA_PREFIX] != 0)
3756 {
3757 prefix = 1;
3758 i.prefixes -= 1;
3759 code16 ^= CODE16;
3760 }
3761 if (i.prefix[REX_PREFIX] != 0)
3762 {
3763 prefix++;
3764 i.prefixes -= 1;
3765 }
252b5132 3766
29b0f896
AM		 3767 size = 4;
3768 if (code16)
3769 size = 2;
252b5132 3770
29b0f896
AM		 3771 if (i.prefixes != 0 && !intel_syntax)
3772 as_warn (_("skipping prefixes on this instruction"));
252b5132 3773
29b0f896
AM		 3774 /* 1 opcode; 2 segment; offset */
3775 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3776
29b0f896
AM		 3777 if (i.prefix[DATA_PREFIX] != 0)
3778 *p++ = DATA_PREFIX_OPCODE;
252b5132 3779
29b0f896
AM		 3780 if (i.prefix[REX_PREFIX] != 0)
3781 *p++ = i.prefix[REX_PREFIX];
252b5132 3782
29b0f896
AM		 3783 *p++ = i.tm.base_opcode;
3784 if (i.op[1].imms->X_op == O_constant)
3785 {
3786 offsetT n = i.op[1].imms->X_add_number;
252b5132 3787
29b0f896
AM		 3788 if (size == 2
3789 && !fits_in_unsigned_word (n)
3790 && !fits_in_signed_word (n))
3791 {
3792 as_bad (_("16-bit jump out of range"));
3793 return;
3794 }
3795 md_number_to_chars (p, n, size);
3796 }
3797 else
3798 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3799 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3800 if (i.op[0].imms->X_op != O_constant)
3801 as_bad (_("can't handle non absolute segment in `%s'"),
3802 i.tm.name);
3803 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3804}
a217f122 3805
29b0f896
AM		 3806static void
3807output_insn ()
3808{
2bbd9c25
JJ		 3809 fragS *insn_start_frag;
3810 offsetT insn_start_off;
3811
29b0f896
AM		 3812 /* Tie dwarf2 debug info to the address at the start of the insn.
3813 We can't do this after the insn has been output as the current
3814 frag may have been closed off. eg. by frag_var. */
3815 dwarf2_emit_insn (0);
3816
2bbd9c25
JJ		 3817 insn_start_frag = frag_now;
3818 insn_start_off = frag_now_fix ();
3819
29b0f896
AM		 3820 /* Output jumps. */
3821 if (i.tm.opcode_modifier & Jump)
3822 output_branch ();
3823 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3824 output_jump ();
3825 else if (i.tm.opcode_modifier & JumpInterSegment)
3826 output_interseg_jump ();
3827 else
3828 {
3829 /* Output normal instructions here. */
3830 char *p;
3831 unsigned char *q;
331d2d0d 3832 unsigned int prefix;
252b5132 3833
331d2d0d
L		 3834 /* All opcodes on i386 have either 1 or 2 bytes. Merom New
3835 Instructions have 3 bytes. We may use one more higher byte
3836 to specify a prefix the instruction requires. */
3837 if ((i.tm.cpu_flags & CpuMNI) != 0)
bc4bd9ab 3838 {
331d2d0d
L		 3839 if (i.tm.base_opcode & 0xff000000)
3840 {
3841 prefix = (i.tm.base_opcode >> 24) & 0xff;
3842 goto check_prefix;
3843 }
3844 }
3845 else if ((i.tm.base_opcode & 0xff0000) != 0)
3846 {
3847 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 3848 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3849 {
64e74474 3850 check_prefix:
bc4bd9ab
MK		 3851 if (prefix != REPE_PREFIX_OPCODE
3852 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3853 add_prefix (prefix);
3854 }
3855 else
331d2d0d 3856 add_prefix (prefix);
0f10071e 3857 }
252b5132 3858
29b0f896
AM		 3859 /* The prefix bytes. */
3860 for (q = i.prefix;
3861 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3862 q++)
3863 {
3864 if (*q)
3865 {
3866 p = frag_more (1);
3867 md_number_to_chars (p, (valueT) *q, 1);
3868 }
3869 }
252b5132 3870
29b0f896
AM		 3871 /* Now the opcode; be careful about word order here! */
3872 if (fits_in_unsigned_byte (i.tm.base_opcode))
3873 {
3874 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3875 }
3876 else
3877 {
331d2d0d
L		 3878 if ((i.tm.cpu_flags & CpuMNI) != 0)
3879 {
3880 p = frag_more (3);
3881 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3882 }
3883 else
3884 p = frag_more (2);
0f10071e 3885
29b0f896
AM		 3886 /* Put out high byte first: can't use md_number_to_chars! */
3887 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3888 *p = i.tm.base_opcode & 0xff;
3889 }
3e73aa7c 3890
29b0f896
AM		 3891 /* Now the modrm byte and sib byte (if present). */
3892 if (i.tm.opcode_modifier & Modrm)
3893 {
3894 p = frag_more (1);
3895 md_number_to_chars (p,
3896 (valueT) (i.rm.regmem << 0
3897 | i.rm.reg << 3
3898 | i.rm.mode << 6),
3899 1);
3900 /* If i.rm.regmem == ESP (4)
3901 && i.rm.mode != (Register mode)
3902 && not 16 bit
3903 ==> need second modrm byte. */
3904 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3905 && i.rm.mode != 3
3906 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3907 {
3908 p = frag_more (1);
3909 md_number_to_chars (p,
3910 (valueT) (i.sib.base << 0
3911 | i.sib.index << 3
3912 | i.sib.scale << 6),
3913 1);
3914 }
3915 }
3e73aa7c 3916
29b0f896 3917 if (i.disp_operands)
2bbd9c25 3918 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3919
29b0f896 3920 if (i.imm_operands)
2bbd9c25 3921 output_imm (insn_start_frag, insn_start_off);
29b0f896 3922 }
252b5132 3923
29b0f896
AM		 3924#ifdef DEBUG386
3925 if (flag_debug)
3926 {
7b81dfbb 3927 pi ("" /*line*/, &i);
29b0f896
AM		 3928 }
3929#endif /* DEBUG386 */
3930}
252b5132 3931
29b0f896 3932static void
64e74474 3933output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 3934{
3935 char *p;
3936 unsigned int n;
252b5132 3937
29b0f896
AM		 3938 for (n = 0; n < i.operands; n++)
3939 {
3940 if (i.types[n] & Disp)
3941 {
3942 if (i.op[n].disps->X_op == O_constant)
3943 {
3944 int size;
3945 offsetT val;
252b5132 3946
29b0f896
AM		 3947 size = 4;
3948 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3949 {
3950 size = 2;
3951 if (i.types[n] & Disp8)
3952 size = 1;
3953 if (i.types[n] & Disp64)
3954 size = 8;
3955 }
3956 val = offset_in_range (i.op[n].disps->X_add_number,
3957 size);
3958 p = frag_more (size);
3959 md_number_to_chars (p, val, size);
3960 }
3961 else
3962 {
f86103b7 3963 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3964 int size = 4;
3965 int sign = 0;
3966 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3967
3968 /* The PC relative address is computed relative
3969 to the instruction boundary, so in case immediate
3970 fields follows, we need to adjust the value. */
3971 if (pcrel && i.imm_operands)
3972 {
3973 int imm_size = 4;
3974 unsigned int n1;
252b5132 3975
29b0f896
AM		 3976 for (n1 = 0; n1 < i.operands; n1++)
3977 if (i.types[n1] & Imm)
252b5132 3978 {
29b0f896 3979 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3980 {
29b0f896
AM		 3981 imm_size = 2;
3982 if (i.types[n1] & (Imm8 | Imm8S))
3983 imm_size = 1;
3984 if (i.types[n1] & Imm64)
3985 imm_size = 8;
252b5132 3986 }
29b0f896 3987 break;
252b5132 3988 }
29b0f896
AM		 3989 /* We should find the immediate. */
3990 if (n1 == i.operands)
3991 abort ();
3992 i.op[n].disps->X_add_number -= imm_size;
3993 }
520dc8e8 3994
29b0f896
AM		 3995 if (i.types[n] & Disp32S)
3996 sign = 1;
3e73aa7c 3997
29b0f896
AM		 3998 if (i.types[n] & (Disp16 | Disp64))
3999 {
4000 size = 2;
4001 if (i.types[n] & Disp64)
4002 size = 8;
4003 }
520dc8e8 4004
29b0f896 4005 p = frag_more (size);
2bbd9c25 4006 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4007 if (GOT_symbol
2bbd9c25 4008 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4009 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4010 || reloc_type == BFD_RELOC_X86_64_32S
4011 || (reloc_type == BFD_RELOC_64
4012 && object_64bit))
d6ab8113
JB		 4013 && (i.op[n].disps->X_op == O_symbol
4014 || (i.op[n].disps->X_op == O_add
4015 && ((symbol_get_value_expression
4016 (i.op[n].disps->X_op_symbol)->X_op)
4017 == O_subtract))))
4018 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4019 {
4020 offsetT add;
4021
4022 if (insn_start_frag == frag_now)
4023 add = (p - frag_now->fr_literal) - insn_start_off;
4024 else
4025 {
4026 fragS *fr;
4027
4028 add = insn_start_frag->fr_fix - insn_start_off;
4029 for (fr = insn_start_frag->fr_next;
4030 fr && fr != frag_now; fr = fr->fr_next)
4031 add += fr->fr_fix;
4032 add += p - frag_now->fr_literal;
4033 }
4034
4fa24527 4035 if (!object_64bit)
7b81dfbb
AJ		 4036 {
4037 reloc_type = BFD_RELOC_386_GOTPC;
4038 i.op[n].imms->X_add_number += add;
4039 }
4040 else if (reloc_type == BFD_RELOC_64)
4041 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4042 else
7b81dfbb
AJ		 4043 /* Don't do the adjustment for x86-64, as there
4044 the pcrel addressing is relative to the _next_
4045 insn, and that is taken care of in other code. */
d6ab8113 4046 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4047 }
062cd5e7 4048 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4049 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4050 }
4051 }
4052 }
4053}
252b5132 4054
29b0f896 4055static void
64e74474 4056output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4057{
4058 char *p;
4059 unsigned int n;
252b5132 4060
29b0f896
AM		 4061 for (n = 0; n < i.operands; n++)
4062 {
4063 if (i.types[n] & Imm)
4064 {
4065 if (i.op[n].imms->X_op == O_constant)
4066 {
4067 int size;
4068 offsetT val;
b4cac588 4069
29b0f896
AM		 4070 size = 4;
4071 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4072 {
4073 size = 2;
4074 if (i.types[n] & (Imm8 | Imm8S))
4075 size = 1;
4076 else if (i.types[n] & Imm64)
4077 size = 8;
4078 }
4079 val = offset_in_range (i.op[n].imms->X_add_number,
4080 size);
4081 p = frag_more (size);
4082 md_number_to_chars (p, val, size);
4083 }
4084 else
4085 {
4086 /* Not absolute_section.
4087 Need a 32-bit fixup (don't support 8bit
4088 non-absolute imms). Try to support other
4089 sizes ... */
f86103b7 4090 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4091 int size = 4;
4092 int sign = 0;
4093
4094 if ((i.types[n] & (Imm32S))
a7d61044
JB		 4095 && (i.suffix == QWORD_MNEM_SUFFIX
4096 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 4097 sign = 1;
4098 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4099 {
4100 size = 2;
4101 if (i.types[n] & (Imm8 | Imm8S))
4102 size = 1;
4103 if (i.types[n] & Imm64)
4104 size = 8;
4105 }
520dc8e8 4106
29b0f896
AM		 4107 p = frag_more (size);
4108 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4109
2bbd9c25
JJ		 4110 /* This is tough to explain. We end up with this one if we
4111 * have operands that look like
4112 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4113 * obtain the absolute address of the GOT, and it is strongly
4114 * preferable from a performance point of view to avoid using
4115 * a runtime relocation for this. The actual sequence of
4116 * instructions often look something like:
4117 *
4118 * call .L66
4119 * .L66:
4120 * popl %ebx
4121 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4122 *
4123 * The call and pop essentially return the absolute address
4124 * of the label .L66 and store it in %ebx. The linker itself
4125 * will ultimately change the first operand of the addl so
4126 * that %ebx points to the GOT, but to keep things simple, the
4127 * .o file must have this operand set so that it generates not
4128 * the absolute address of .L66, but the absolute address of
4129 * itself. This allows the linker itself simply treat a GOTPC
4130 * relocation as asking for a pcrel offset to the GOT to be
4131 * added in, and the addend of the relocation is stored in the
4132 * operand field for the instruction itself.
4133 *
4134 * Our job here is to fix the operand so that it would add
4135 * the correct offset so that %ebx would point to itself. The
4136 * thing that is tricky is that .-.L66 will point to the
4137 * beginning of the instruction, so we need to further modify
4138 * the operand so that it will point to itself. There are
4139 * other cases where you have something like:
4140 *
4141 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4142 *
4143 * and here no correction would be required. Internally in
4144 * the assembler we treat operands of this form as not being
4145 * pcrel since the '.' is explicitly mentioned, and I wonder
4146 * whether it would simplify matters to do it this way. Who
4147 * knows. In earlier versions of the PIC patches, the
4148 * pcrel_adjust field was used to store the correction, but
4149 * since the expression is not pcrel, I felt it would be
4150 * confusing to do it this way. */
4151
d6ab8113 4152 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4153 || reloc_type == BFD_RELOC_X86_64_32S
4154 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4155 && GOT_symbol
4156 && GOT_symbol == i.op[n].imms->X_add_symbol
4157 && (i.op[n].imms->X_op == O_symbol
4158 || (i.op[n].imms->X_op == O_add
4159 && ((symbol_get_value_expression
4160 (i.op[n].imms->X_op_symbol)->X_op)
4161 == O_subtract))))
4162 {
2bbd9c25
JJ		 4163 offsetT add;
4164
4165 if (insn_start_frag == frag_now)
4166 add = (p - frag_now->fr_literal) - insn_start_off;
4167 else
4168 {
4169 fragS *fr;
4170
4171 add = insn_start_frag->fr_fix - insn_start_off;
4172 for (fr = insn_start_frag->fr_next;
4173 fr && fr != frag_now; fr = fr->fr_next)
4174 add += fr->fr_fix;
4175 add += p - frag_now->fr_literal;
4176 }
4177
4fa24527 4178 if (!object_64bit)
d6ab8113 4179 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4180 else if (size == 4)
d6ab8113 4181 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4182 else if (size == 8)
4183 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4184 i.op[n].imms->X_add_number += add;
29b0f896 4185 }
29b0f896
AM		 4186 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4187 i.op[n].imms, 0, reloc_type);
4188 }
4189 }
4190 }
252b5132
RH		 4191}
4192\f
d182319b
JB		 4193/* x86_cons_fix_new is called via the expression parsing code when a
4194 reloc is needed. We use this hook to get the correct .got reloc. */
4195static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4196static int cons_sign = -1;
4197
4198void
4199x86_cons_fix_new (fragS *frag,
64e74474
AM		 4200 unsigned int off,
4201 unsigned int len,
4202 expressionS *exp)
d182319b
JB		 4203{
4204 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4205
4206 got_reloc = NO_RELOC;
4207
4208#ifdef TE_PE
4209 if (exp->X_op == O_secrel)
4210 {
4211 exp->X_op = O_symbol;
4212 r = BFD_RELOC_32_SECREL;
4213 }
4214#endif
4215
4216 fix_new_exp (frag, off, len, exp, 0, r);
4217}
4218
718ddfc0
JB		 4219#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4220# define lex_got(reloc, adjust, types) NULL
4221#else
f3c180ae
AM		 4222/* Parse operands of the form
4223 <symbol>@GOTOFF+<nnn>
4224 and similar .plt or .got references.
4225
4226 If we find one, set up the correct relocation in RELOC and copy the
4227 input string, minus the `@GOTOFF' into a malloc'd buffer for
4228 parsing by the calling routine. Return this buffer, and if ADJUST
4229 is non-null set it to the length of the string we removed from the
4230 input line. Otherwise return NULL. */
4231static char *
3956db08 4232lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 4233 int *adjust,
4234 unsigned int *types)
f3c180ae 4235{
7b81dfbb
AJ		 4236 /* Some of the relocations depend on the size of what field is to
4237 be relocated. But in our callers i386_immediate and i386_displacement
4238 we don't yet know the operand size (this will be set by insn
4239 matching). Hence we record the word32 relocation here,
4240 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4241 static const struct {
4242 const char *str;
4fa24527 4243 const enum bfd_reloc_code_real rel[2];
3956db08 4244 const unsigned int types64;
f3c180ae 4245 } gotrel[] = {
7b81dfbb 4246 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
4fa24527 4247 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
7b81dfbb 4248 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
4fa24527
JB		 4249 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
4250 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
4251 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
4252 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
4253 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
4254 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
4255 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4256 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
4257 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4258 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
4259 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
7b81dfbb 4260 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 },
67a4f2b7
AO		 4261 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
4262 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 4263 };
4264 char *cp;
4265 unsigned int j;
4266
718ddfc0
JB		 4267 if (!IS_ELF)
4268 return NULL;
4269
f3c180ae
AM		 4270 for (cp = input_line_pointer; *cp != '@'; cp++)
4271 if (is_end_of_line[(unsigned char) *cp])
4272 return NULL;
4273
4274 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4275 {
4276 int len;
4277
4278 len = strlen (gotrel[j].str);
28f81592 4279 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4280 {
4fa24527 4281 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4282 {
28f81592
AM		 4283 int first, second;
4284 char *tmpbuf, *past_reloc;
f3c180ae 4285
4fa24527 4286 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 4287 if (adjust)
4288 *adjust = len;
f3c180ae 4289
3956db08
JB		 4290 if (types)
4291 {
4292 if (flag_code != CODE_64BIT)
4293 *types = Imm32|Disp32;
4294 else
4295 *types = gotrel[j].types64;
4296 }
4297
f3c180ae
AM		 4298 if (GOT_symbol == NULL)
4299 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4300
4301 /* Replace the relocation token with ' ', so that
4302 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 4303
4304 /* The length of the first part of our input line. */
f3c180ae 4305 first = cp - input_line_pointer;
28f81592
AM		 4306
4307 /* The second part goes from after the reloc token until
4308 (and including) an end_of_line char. Don't use strlen
4309 here as the end_of_line char may not be a NUL. */
4310 past_reloc = cp + 1 + len;
4311 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4312 ;
4313 second = cp - past_reloc;
4314
4315 /* Allocate and copy string. The trailing NUL shouldn't
4316 be necessary, but be safe. */
4317 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 4318 memcpy (tmpbuf, input_line_pointer, first);
4319 tmpbuf[first] = ' ';
28f81592
AM		 4320 memcpy (tmpbuf + first + 1, past_reloc, second);
4321 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 4322 return tmpbuf;
4323 }
4324
4fa24527
JB		 4325 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4326 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 4327 return NULL;
4328 }
4329 }
4330
4331 /* Might be a symbol version string. Don't as_bad here. */
4332 return NULL;
4333}
4334
f3c180ae
AM		 4335void
4336x86_cons (exp, size)
4337 expressionS *exp;
4338 int size;
4339{
4fa24527 4340 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 4341 {
4342 /* Handle @GOTOFF and the like in an expression. */
4343 char *save;
4344 char *gotfree_input_line;
4345 int adjust;
4346
4347 save = input_line_pointer;
3956db08 4348 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4349 if (gotfree_input_line)
4350 input_line_pointer = gotfree_input_line;
4351
4352 expression (exp);
4353
4354 if (gotfree_input_line)
4355 {
4356 /* expression () has merrily parsed up to the end of line,
4357 or a comma - in the wrong buffer. Transfer how far
4358 input_line_pointer has moved to the right buffer. */
4359 input_line_pointer = (save
4360 + (input_line_pointer - gotfree_input_line)
4361 + adjust);
4362 free (gotfree_input_line);
4363 }
4364 }
4365 else
4366 expression (exp);
4367}
4368#endif
4369
d182319b 4370static void signed_cons (int size)
6482c264 4371{
d182319b
JB		 4372 if (flag_code == CODE_64BIT)
4373 cons_sign = 1;
4374 cons (size);
4375 cons_sign = -1;
6482c264
NC		 4376}
4377
d182319b 4378#ifdef TE_PE
6482c264
NC		 4379static void
4380pe_directive_secrel (dummy)
4381 int dummy ATTRIBUTE_UNUSED;
4382{
4383 expressionS exp;
4384
4385 do
4386 {
4387 expression (&exp);
4388 if (exp.X_op == O_symbol)
4389 exp.X_op = O_secrel;
4390
4391 emit_expr (&exp, 4);
4392 }
4393 while (*input_line_pointer++ == ',');
4394
4395 input_line_pointer--;
4396 demand_empty_rest_of_line ();
4397}
6482c264
NC		 4398#endif
4399
252b5132
RH		 4400static int i386_immediate PARAMS ((char *));
4401
4402static int
4403i386_immediate (imm_start)
4404 char *imm_start;
4405{
4406 char *save_input_line_pointer;
f3c180ae 4407 char *gotfree_input_line;
252b5132 4408 segT exp_seg = 0;
47926f60 4409 expressionS *exp;
3956db08 4410 unsigned int types = ~0U;
252b5132
RH		 4411
4412 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4413 {
d0b47220 4414 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 4415 return 0;
4416 }
4417
4418 exp = &im_expressions[i.imm_operands++];
520dc8e8 4419 i.op[this_operand].imms = exp;
252b5132
RH		 4420
4421 if (is_space_char (*imm_start))
4422 ++imm_start;
4423
4424 save_input_line_pointer = input_line_pointer;
4425 input_line_pointer = imm_start;
4426
3956db08 4427 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4428 if (gotfree_input_line)
4429 input_line_pointer = gotfree_input_line;
252b5132
RH		 4430
4431 exp_seg = expression (exp);
4432
83183c0c 4433 SKIP_WHITESPACE ();
252b5132 4434 if (*input_line_pointer)
f3c180ae 4435 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4436
4437 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4438 if (gotfree_input_line)
4439 free (gotfree_input_line);
252b5132 4440
2daf4fd8 4441 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4442 {
47926f60 4443 /* Missing or bad expr becomes absolute 0. */
d0b47220 4444 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4445 imm_start);
252b5132
RH		 4446 exp->X_op = O_constant;
4447 exp->X_add_number = 0;
4448 exp->X_add_symbol = (symbolS *) 0;
4449 exp->X_op_symbol = (symbolS *) 0;
252b5132 4450 }
3e73aa7c 4451 else if (exp->X_op == O_constant)
252b5132 4452 {
47926f60 4453 /* Size it properly later. */
3e73aa7c
JH		 4454 i.types[this_operand] |= Imm64;
4455 /* If BFD64, sign extend val. */
4456 if (!use_rela_relocations)
4457 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4458 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4459 }
4c63da97 4460#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4461 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4462 && exp_seg != absolute_section
47926f60 4463 && exp_seg != text_section
24eab124
AM		 4464 && exp_seg != data_section
4465 && exp_seg != bss_section
4466 && exp_seg != undefined_section
f86103b7 4467 && !bfd_is_com_section (exp_seg))
252b5132 4468 {
d0b47220 4469 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4470 return 0;
4471 }
4472#endif
bb8f5920
L		 4473 else if (!intel_syntax && exp->X_op == O_register)
4474 {
4475 as_bad (_("illegal immediate register operand %s"), imm_start);
4476 return 0;
4477 }
252b5132
RH		 4478 else
4479 {
4480 /* This is an address. The size of the address will be
24eab124 4481 determined later, depending on destination register,
3e73aa7c
JH		 4482 suffix, or the default for the section. */
4483 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4484 i.types[this_operand] &= types;
252b5132
RH		 4485 }
4486
4487 return 1;
4488}
4489
551c1ca1 4490static char *i386_scale PARAMS ((char *));
252b5132 4491
551c1ca1 4492static char *
252b5132
RH		 4493i386_scale (scale)
4494 char *scale;
4495{
551c1ca1
AM		 4496 offsetT val;
4497 char *save = input_line_pointer;
252b5132 4498
551c1ca1
AM		 4499 input_line_pointer = scale;
4500 val = get_absolute_expression ();
4501
4502 switch (val)
252b5132 4503 {
551c1ca1 4504 case 1:
252b5132
RH		 4505 i.log2_scale_factor = 0;
4506 break;
551c1ca1 4507 case 2:
252b5132
RH		 4508 i.log2_scale_factor = 1;
4509 break;
551c1ca1 4510 case 4:
252b5132
RH		 4511 i.log2_scale_factor = 2;
4512 break;
551c1ca1 4513 case 8:
252b5132
RH		 4514 i.log2_scale_factor = 3;
4515 break;
4516 default:
a724f0f4
JB		 4517 {
4518 char sep = *input_line_pointer;
4519
4520 *input_line_pointer = '\0';
4521 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4522 scale);
4523 *input_line_pointer = sep;
4524 input_line_pointer = save;
4525 return NULL;
4526 }
252b5132 4527 }
29b0f896 4528 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4529 {
4530 as_warn (_("scale factor of %d without an index register"),
24eab124 4531 1 << i.log2_scale_factor);
252b5132
RH		 4532#if SCALE1_WHEN_NO_INDEX
4533 i.log2_scale_factor = 0;
4534#endif
4535 }
551c1ca1
AM		 4536 scale = input_line_pointer;
4537 input_line_pointer = save;
4538 return scale;
252b5132
RH		 4539}
4540
4541static int i386_displacement PARAMS ((char *, char *));
4542
4543static int
4544i386_displacement (disp_start, disp_end)
4545 char *disp_start;
4546 char *disp_end;
4547{
29b0f896 4548 expressionS *exp;
252b5132
RH		 4549 segT exp_seg = 0;
4550 char *save_input_line_pointer;
f3c180ae 4551 char *gotfree_input_line;
e05278af 4552 int bigdisp, override;
3956db08 4553 unsigned int types = Disp;
252b5132 4554
e05278af
JB		 4555 if ((i.types[this_operand] & JumpAbsolute)
4556 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4557 {
4558 bigdisp = Disp32;
4559 override = (i.prefix[ADDR_PREFIX] != 0);
4560 }
4561 else
4562 {
4563 /* For PC-relative branches, the width of the displacement
4564 is dependent upon data size, not address size. */
4565 bigdisp = 0;
4566 override = (i.prefix[DATA_PREFIX] != 0);
4567 }
3e73aa7c 4568 if (flag_code == CODE_64BIT)
7ecd2f8b 4569 {
e05278af 4570 if (!bigdisp)
64e74474
AM		 4571 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4572 ? Disp16
4573 : Disp32S | Disp32);
e05278af 4574 else if (!override)
3956db08 4575 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4576 }
e05278af
JB		 4577 else
4578 {
4579 if (!bigdisp)
4580 {
4581 if (!override)
4582 override = (i.suffix == (flag_code != CODE_16BIT
4583 ? WORD_MNEM_SUFFIX
4584 : LONG_MNEM_SUFFIX));
4585 bigdisp = Disp32;
4586 }
4587 if ((flag_code == CODE_16BIT) ^ override)
4588 bigdisp = Disp16;
4589 }
252b5132
RH		 4590 i.types[this_operand] |= bigdisp;
4591
4592 exp = &disp_expressions[i.disp_operands];
520dc8e8 4593 i.op[this_operand].disps = exp;
252b5132
RH		 4594 i.disp_operands++;
4595 save_input_line_pointer = input_line_pointer;
4596 input_line_pointer = disp_start;
4597 END_STRING_AND_SAVE (disp_end);
4598
4599#ifndef GCC_ASM_O_HACK
4600#define GCC_ASM_O_HACK 0
4601#endif
4602#if GCC_ASM_O_HACK
4603 END_STRING_AND_SAVE (disp_end + 1);
4604 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4605 && displacement_string_end[-1] == '+')
252b5132
RH		 4606 {
4607 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4608 constraint within gcc asm statements.
4609 For instance:
4610
4611 #define _set_tssldt_desc(n,addr,limit,type) \
4612 __asm__ __volatile__ ( \
4613 "movw %w2,%0\n\t" \
4614 "movw %w1,2+%0\n\t" \
4615 "rorl $16,%1\n\t" \
4616 "movb %b1,4+%0\n\t" \
4617 "movb %4,5+%0\n\t" \
4618 "movb $0,6+%0\n\t" \
4619 "movb %h1,7+%0\n\t" \
4620 "rorl $16,%1" \
4621 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4622
4623 This works great except that the output assembler ends
4624 up looking a bit weird if it turns out that there is
4625 no offset. You end up producing code that looks like:
4626
4627 #APP
4628 movw $235,(%eax)
4629 movw %dx,2+(%eax)
4630 rorl $16,%edx
4631 movb %dl,4+(%eax)
4632 movb $137,5+(%eax)
4633 movb $0,6+(%eax)
4634 movb %dh,7+(%eax)
4635 rorl $16,%edx
4636 #NO_APP
4637
47926f60 4638 So here we provide the missing zero. */
24eab124
AM		 4639
4640 *displacement_string_end = '0';
252b5132
RH		 4641 }
4642#endif
3956db08 4643 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4644 if (gotfree_input_line)
4645 input_line_pointer = gotfree_input_line;
252b5132 4646
24eab124 4647 exp_seg = expression (exp);
252b5132 4648
636c26b0
AM		 4649 SKIP_WHITESPACE ();
4650 if (*input_line_pointer)
4651 as_bad (_("junk `%s' after expression"), input_line_pointer);
4652#if GCC_ASM_O_HACK
4653 RESTORE_END_STRING (disp_end + 1);
4654#endif
4655 RESTORE_END_STRING (disp_end);
4656 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4657 if (gotfree_input_line)
4658 free (gotfree_input_line);
636c26b0 4659
24eab124
AM		 4660 /* We do this to make sure that the section symbol is in
4661 the symbol table. We will ultimately change the relocation
47926f60 4662 to be relative to the beginning of the section. */
1ae12ab7 4663 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4664 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4665 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4666 {
636c26b0
AM		 4667 if (exp->X_op != O_symbol)
4668 {
4669 as_bad (_("bad expression used with @%s"),
4670 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4671 ? "GOTPCREL"
4672 : "GOTOFF"));
4673 return 0;
4674 }
4675
e5cb08ac 4676 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4677 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4678 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4679 exp->X_op = O_subtract;
4680 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4681 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4682 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4683 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4684 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4685 else
29b0f896 4686 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4687 }
252b5132 4688
2daf4fd8
AM		 4689 if (exp->X_op == O_absent || exp->X_op == O_big)
4690 {
47926f60 4691 /* Missing or bad expr becomes absolute 0. */
d0b47220 4692 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4693 disp_start);
4694 exp->X_op = O_constant;
4695 exp->X_add_number = 0;
4696 exp->X_add_symbol = (symbolS *) 0;
4697 exp->X_op_symbol = (symbolS *) 0;
4698 }
4699
4c63da97 4700#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4701 if (exp->X_op != O_constant
45288df1 4702 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4703 && exp_seg != absolute_section
45288df1
AM		 4704 && exp_seg != text_section
4705 && exp_seg != data_section
4706 && exp_seg != bss_section
31312f95 4707 && exp_seg != undefined_section
f86103b7 4708 && !bfd_is_com_section (exp_seg))
24eab124 4709 {
d0b47220 4710 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4711 return 0;
4712 }
252b5132 4713#endif
3956db08
JB		 4714
4715 if (!(i.types[this_operand] & ~Disp))
4716 i.types[this_operand] &= types;
4717
252b5132
RH		 4718 return 1;
4719}
4720
e5cb08ac 4721static int i386_index_check PARAMS ((const char *));
252b5132 4722
eecb386c 4723/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4724 Return 1 on success, 0 on a failure. */
4725
252b5132 4726static int
eecb386c
AM		 4727i386_index_check (operand_string)
4728 const char *operand_string;
252b5132 4729{
3e73aa7c 4730 int ok;
24eab124 4731#if INFER_ADDR_PREFIX
eecb386c
AM		 4732 int fudged = 0;
4733
24eab124
AM		 4734 tryprefix:
4735#endif
3e73aa7c 4736 ok = 1;
30123838
JB		 4737 if ((current_templates->start->cpu_flags & CpuSVME)
4738 && current_templates->end[-1].operand_types[0] == AnyMem)
4739 {
4740 /* Memory operands of SVME insns are special in that they only allow
4741 rAX as their memory address and ignore any segment override. */
4742 unsigned RegXX;
4743
4744 /* SKINIT is even more restrictive: it always requires EAX. */
4745 if (strcmp (current_templates->start->name, "skinit") == 0)
4746 RegXX = Reg32;
4747 else if (flag_code == CODE_64BIT)
4748 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4749 else
64e74474
AM		 4750 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4751 ? Reg16
4752 : Reg32);
30123838
JB		 4753 if (!i.base_reg
4754 || !(i.base_reg->reg_type & Acc)
4755 || !(i.base_reg->reg_type & RegXX)
4756 || i.index_reg
4757 || (i.types[0] & Disp))
4758 ok = 0;
4759 }
4760 else if (flag_code == CODE_64BIT)
64e74474
AM		 4761 {
4762 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4763
4764 if ((i.base_reg
4765 && ((i.base_reg->reg_type & RegXX) == 0)
4766 && (i.base_reg->reg_type != BaseIndex
4767 || i.index_reg))
4768 || (i.index_reg
4769 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4770 != (RegXX | BaseIndex))))
4771 ok = 0;
3e73aa7c
JH		 4772 }
4773 else
4774 {
4775 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4776 {
4777 /* 16bit checks. */
4778 if ((i.base_reg
29b0f896
AM		 4779 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4780 != (Reg16 | BaseIndex)))
3e73aa7c 4781 || (i.index_reg
29b0f896
AM		 4782 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4783 != (Reg16 | BaseIndex))
4784 || !(i.base_reg
4785 && i.base_reg->reg_num < 6
4786 && i.index_reg->reg_num >= 6
4787 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4788 ok = 0;
4789 }
4790 else
e5cb08ac 4791 {
3e73aa7c
JH		 4792 /* 32bit checks. */
4793 if ((i.base_reg
4794 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4795 || (i.index_reg
29b0f896
AM		 4796 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4797 != (Reg32 | BaseIndex))))
e5cb08ac 4798 ok = 0;
3e73aa7c
JH		 4799 }
4800 }
4801 if (!ok)
24eab124
AM		 4802 {
4803#if INFER_ADDR_PREFIX
20f0a1fc 4804 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4805 {
4806 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4807 i.prefixes += 1;
b23bac36
AM		 4808 /* Change the size of any displacement too. At most one of
4809 Disp16 or Disp32 is set.
4810 FIXME. There doesn't seem to be any real need for separate
4811 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4812 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4813 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 4814 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4815 fudged = 1;
24eab124
AM		 4816 goto tryprefix;
4817 }
eecb386c
AM		 4818 if (fudged)
4819 as_bad (_("`%s' is not a valid base/index expression"),
4820 operand_string);
4821 else
c388dee8 4822#endif
eecb386c
AM		 4823 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4824 operand_string,
3e73aa7c 4825 flag_code_names[flag_code]);
24eab124 4826 }
20f0a1fc 4827 return ok;
24eab124 4828}
252b5132 4829
252b5132 4830/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4831 on error. */
252b5132 4832
252b5132
RH		 4833static int
4834i386_operand (operand_string)
4835 char *operand_string;
4836{
af6bdddf
AM		 4837 const reg_entry *r;
4838 char *end_op;
24eab124 4839 char *op_string = operand_string;
252b5132 4840
24eab124 4841 if (is_space_char (*op_string))
252b5132
RH		 4842 ++op_string;
4843
24eab124 4844 /* We check for an absolute prefix (differentiating,
47926f60 4845 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4846 if (*op_string == ABSOLUTE_PREFIX)
4847 {
4848 ++op_string;
4849 if (is_space_char (*op_string))
4850 ++op_string;
4851 i.types[this_operand] |= JumpAbsolute;
4852 }
252b5132 4853
47926f60 4854 /* Check if operand is a register. */
4d1bb795 4855 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 4856 {
24eab124
AM		 4857 /* Check for a segment override by searching for ':' after a
4858 segment register. */
4859 op_string = end_op;
4860 if (is_space_char (*op_string))
4861 ++op_string;
4862 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4863 {
4864 switch (r->reg_num)
4865 {
4866 case 0:
4867 i.seg[i.mem_operands] = &es;
4868 break;
4869 case 1:
4870 i.seg[i.mem_operands] = &cs;
4871 break;
4872 case 2:
4873 i.seg[i.mem_operands] = &ss;
4874 break;
4875 case 3:
4876 i.seg[i.mem_operands] = &ds;
4877 break;
4878 case 4:
4879 i.seg[i.mem_operands] = &fs;
4880 break;
4881 case 5:
4882 i.seg[i.mem_operands] = &gs;
4883 break;
4884 }
252b5132 4885
24eab124 4886 /* Skip the ':' and whitespace. */
252b5132
RH		 4887 ++op_string;
4888 if (is_space_char (*op_string))
24eab124 4889 ++op_string;
252b5132 4890
24eab124
AM		 4891 if (!is_digit_char (*op_string)
4892 && !is_identifier_char (*op_string)
4893 && *op_string != '('
4894 && *op_string != ABSOLUTE_PREFIX)
4895 {
4896 as_bad (_("bad memory operand `%s'"), op_string);
4897 return 0;
4898 }
47926f60 4899 /* Handle case of %es:*foo. */
24eab124
AM		 4900 if (*op_string == ABSOLUTE_PREFIX)
4901 {
4902 ++op_string;
4903 if (is_space_char (*op_string))
4904 ++op_string;
4905 i.types[this_operand] |= JumpAbsolute;
4906 }
4907 goto do_memory_reference;
4908 }
4909 if (*op_string)
4910 {
d0b47220 4911 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4912 return 0;
4913 }
4914 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4915 i.op[this_operand].regs = r;
24eab124
AM		 4916 i.reg_operands++;
4917 }
af6bdddf
AM		 4918 else if (*op_string == REGISTER_PREFIX)
4919 {
4920 as_bad (_("bad register name `%s'"), op_string);
4921 return 0;
4922 }
24eab124 4923 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4924 {
24eab124
AM		 4925 ++op_string;
4926 if (i.types[this_operand] & JumpAbsolute)
4927 {
d0b47220 4928 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4929 return 0;
4930 }
4931 if (!i386_immediate (op_string))
4932 return 0;
4933 }
4934 else if (is_digit_char (*op_string)
4935 || is_identifier_char (*op_string)
e5cb08ac 4936 || *op_string == '(')
24eab124 4937 {
47926f60 4938 /* This is a memory reference of some sort. */
af6bdddf 4939 char *base_string;
252b5132 4940
47926f60 4941 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4942 char *displacement_string_start;
4943 char *displacement_string_end;
252b5132 4944
24eab124 4945 do_memory_reference:
24eab124
AM		 4946 if ((i.mem_operands == 1
4947 && (current_templates->start->opcode_modifier & IsString) == 0)
4948 || i.mem_operands == 2)
4949 {
4950 as_bad (_("too many memory references for `%s'"),
4951 current_templates->start->name);
4952 return 0;
4953 }
252b5132 4954
24eab124
AM		 4955 /* Check for base index form. We detect the base index form by
4956 looking for an ')' at the end of the operand, searching
4957 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4958 after the '('. */
af6bdddf 4959 base_string = op_string + strlen (op_string);
c3332e24 4960
af6bdddf
AM		 4961 --base_string;
4962 if (is_space_char (*base_string))
4963 --base_string;
252b5132 4964
47926f60 4965 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4966 displacement_string_start = op_string;
4967 displacement_string_end = base_string + 1;
252b5132 4968
24eab124
AM		 4969 if (*base_string == ')')
4970 {
af6bdddf 4971 char *temp_string;
24eab124
AM		 4972 unsigned int parens_balanced = 1;
4973 /* We've already checked that the number of left & right ()'s are
47926f60 4974 equal, so this loop will not be infinite. */
24eab124
AM		 4975 do
4976 {
4977 base_string--;
4978 if (*base_string == ')')
4979 parens_balanced++;
4980 if (*base_string == '(')
4981 parens_balanced--;
4982 }
4983 while (parens_balanced);
c3332e24 4984
af6bdddf 4985 temp_string = base_string;
c3332e24 4986
24eab124 4987 /* Skip past '(' and whitespace. */
252b5132
RH		 4988 ++base_string;
4989 if (is_space_char (*base_string))
24eab124 4990 ++base_string;
252b5132 4991
af6bdddf 4992 if (*base_string == ','
4d1bb795 4993 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4994 {
af6bdddf 4995 displacement_string_end = temp_string;
252b5132 4996
af6bdddf 4997 i.types[this_operand] |= BaseIndex;
252b5132 4998
af6bdddf 4999 if (i.base_reg)
24eab124 5000 {
24eab124
AM		 5001 base_string = end_op;
5002 if (is_space_char (*base_string))
5003 ++base_string;
af6bdddf
AM		 5004 }
5005
5006 /* There may be an index reg or scale factor here. */
5007 if (*base_string == ',')
5008 {
5009 ++base_string;
5010 if (is_space_char (*base_string))
5011 ++base_string;
5012
4d1bb795 5013 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 5014 {
af6bdddf 5015 base_string = end_op;
24eab124
AM		 5016 if (is_space_char (*base_string))
5017 ++base_string;
af6bdddf
AM		 5018 if (*base_string == ',')
5019 {
5020 ++base_string;
5021 if (is_space_char (*base_string))
5022 ++base_string;
5023 }
e5cb08ac 5024 else if (*base_string != ')')
af6bdddf
AM		 5025 {
5026 as_bad (_("expecting `,' or `)' after index register in `%s'"),
5027 operand_string);
5028 return 0;
5029 }
24eab124 5030 }
af6bdddf 5031 else if (*base_string == REGISTER_PREFIX)
24eab124 5032 {
af6bdddf 5033 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5034 return 0;
5035 }
252b5132 5036
47926f60 5037 /* Check for scale factor. */
551c1ca1 5038 if (*base_string != ')')
af6bdddf 5039 {
551c1ca1
AM		 5040 char *end_scale = i386_scale (base_string);
5041
5042 if (!end_scale)
af6bdddf 5043 return 0;
24eab124 5044
551c1ca1 5045 base_string = end_scale;
af6bdddf
AM		 5046 if (is_space_char (*base_string))
5047 ++base_string;
5048 if (*base_string != ')')
5049 {
5050 as_bad (_("expecting `)' after scale factor in `%s'"),
5051 operand_string);
5052 return 0;
5053 }
5054 }
5055 else if (!i.index_reg)
24eab124 5056 {
af6bdddf
AM		 5057 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
5058 *base_string);
24eab124
AM		 5059 return 0;
5060 }
5061 }
af6bdddf 5062 else if (*base_string != ')')
24eab124 5063 {
af6bdddf
AM		 5064 as_bad (_("expecting `,' or `)' after base register in `%s'"),
5065 operand_string);
24eab124
AM		 5066 return 0;
5067 }
c3332e24 5068 }
af6bdddf 5069 else if (*base_string == REGISTER_PREFIX)
c3332e24 5070 {
af6bdddf 5071 as_bad (_("bad register name `%s'"), base_string);
24eab124 5072 return 0;
c3332e24 5073 }
24eab124
AM		 5074 }
5075
5076 /* If there's an expression beginning the operand, parse it,
5077 assuming displacement_string_start and
5078 displacement_string_end are meaningful. */
5079 if (displacement_string_start != displacement_string_end)
5080 {
5081 if (!i386_displacement (displacement_string_start,
5082 displacement_string_end))
5083 return 0;
5084 }
5085
5086 /* Special case for (%dx) while doing input/output op. */
5087 if (i.base_reg
5088 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5089 && i.index_reg == 0
5090 && i.log2_scale_factor == 0
5091 && i.seg[i.mem_operands] == 0
5092 && (i.types[this_operand] & Disp) == 0)
5093 {
5094 i.types[this_operand] = InOutPortReg;
5095 return 1;
5096 }
5097
eecb386c
AM		 5098 if (i386_index_check (operand_string) == 0)
5099 return 0;
24eab124
AM		 5100 i.mem_operands++;
5101 }
5102 else
ce8a8b2f
AM		 5103 {
5104 /* It's not a memory operand; argh! */
24eab124
AM		 5105 as_bad (_("invalid char %s beginning operand %d `%s'"),
5106 output_invalid (*op_string),
5107 this_operand + 1,
5108 op_string);
5109 return 0;
5110 }
47926f60 5111 return 1; /* Normal return. */
252b5132
RH		 5112}
5113\f
ee7fcc42
AM		 5114/* md_estimate_size_before_relax()
5115
5116 Called just before relax() for rs_machine_dependent frags. The x86
5117 assembler uses these frags to handle variable size jump
5118 instructions.
5119
5120 Any symbol that is now undefined will not become defined.
5121 Return the correct fr_subtype in the frag.
5122 Return the initial "guess for variable size of frag" to caller.
5123 The guess is actually the growth beyond the fixed part. Whatever
5124 we do to grow the fixed or variable part contributes to our
5125 returned value. */
5126
252b5132
RH		 5127int
5128md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5129 fragS *fragP;
5130 segT segment;
252b5132 5131{
252b5132 5132 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5133 check for un-relaxable symbols. On an ELF system, we can't relax
5134 an externally visible symbol, because it may be overridden by a
5135 shared library. */
5136 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5137#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5138 || (IS_ELF
31312f95
AM		 5139 && (S_IS_EXTERNAL (fragP->fr_symbol)
5140 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5141#endif
5142 )
252b5132 5143 {
b98ef147
AM		 5144 /* Symbol is undefined in this segment, or we need to keep a
5145 reloc so that weak symbols can be overridden. */
5146 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5147 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5148 unsigned char *opcode;
5149 int old_fr_fix;
f6af82bd 5150
ee7fcc42
AM		 5151 if (fragP->fr_var != NO_RELOC)
5152 reloc_type = fragP->fr_var;
b98ef147 5153 else if (size == 2)
f6af82bd
AM		 5154 reloc_type = BFD_RELOC_16_PCREL;
5155 else
5156 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5157
ee7fcc42
AM		 5158 old_fr_fix = fragP->fr_fix;
5159 opcode = (unsigned char *) fragP->fr_opcode;
5160
fddf5b5b 5161 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5162 {
fddf5b5b
AM		 5163 case UNCOND_JUMP:
5164 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5165 opcode[0] = 0xe9;
252b5132 5166 fragP->fr_fix += size;
062cd5e7
AS		 5167 fix_new (fragP, old_fr_fix, size,
5168 fragP->fr_symbol,
5169 fragP->fr_offset, 1,
5170 reloc_type);
252b5132
RH		 5171 break;
5172
fddf5b5b 5173 case COND_JUMP86:
412167cb
AM		 5174 if (size == 2
5175 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5176 {
5177 /* Negate the condition, and branch past an
5178 unconditional jump. */
5179 opcode[0] ^= 1;
5180 opcode[1] = 3;
5181 /* Insert an unconditional jump. */
5182 opcode[2] = 0xe9;
5183 /* We added two extra opcode bytes, and have a two byte
5184 offset. */
5185 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5186 fix_new (fragP, old_fr_fix + 2, 2,
5187 fragP->fr_symbol,
5188 fragP->fr_offset, 1,
5189 reloc_type);
fddf5b5b
AM		 5190 break;
5191 }
5192 /* Fall through. */
5193
5194 case COND_JUMP:
412167cb
AM		 5195 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5196 {
3e02c1cc
AM		 5197 fixS *fixP;
5198
412167cb 5199 fragP->fr_fix += 1;
3e02c1cc
AM		 5200 fixP = fix_new (fragP, old_fr_fix, 1,
5201 fragP->fr_symbol,
5202 fragP->fr_offset, 1,
5203 BFD_RELOC_8_PCREL);
5204 fixP->fx_signed = 1;
412167cb
AM		 5205 break;
5206 }
93c2a809 5207
24eab124 5208 /* This changes the byte-displacement jump 0x7N
fddf5b5b 5209 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 5210 opcode[1] = opcode[0] + 0x10;
f6af82bd 5211 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 5212 /* We've added an opcode byte. */
5213 fragP->fr_fix += 1 + size;
062cd5e7
AS		 5214 fix_new (fragP, old_fr_fix + 1, size,
5215 fragP->fr_symbol,
5216 fragP->fr_offset, 1,
5217 reloc_type);
252b5132 5218 break;
fddf5b5b
AM		 5219
5220 default:
5221 BAD_CASE (fragP->fr_subtype);
5222 break;
252b5132
RH		 5223 }
5224 frag_wane (fragP);
ee7fcc42 5225 return fragP->fr_fix - old_fr_fix;
252b5132 5226 }
93c2a809 5227
93c2a809
AM		 5228 /* Guess size depending on current relax state. Initially the relax
5229 state will correspond to a short jump and we return 1, because
5230 the variable part of the frag (the branch offset) is one byte
5231 long. However, we can relax a section more than once and in that
5232 case we must either set fr_subtype back to the unrelaxed state,
5233 or return the value for the appropriate branch. */
5234 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 5235}
5236
47926f60
KH		 5237/* Called after relax() is finished.
5238
5239 In: Address of frag.
5240 fr_type == rs_machine_dependent.
5241 fr_subtype is what the address relaxed to.
5242
5243 Out: Any fixSs and constants are set up.
5244 Caller will turn frag into a ".space 0". */
5245
252b5132
RH		 5246void
5247md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 5248 bfd *abfd ATTRIBUTE_UNUSED;
5249 segT sec ATTRIBUTE_UNUSED;
29b0f896 5250 fragS *fragP;
252b5132 5251{
29b0f896 5252 unsigned char *opcode;
252b5132 5253 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 5254 offsetT target_address;
5255 offsetT opcode_address;
252b5132 5256 unsigned int extension = 0;
847f7ad4 5257 offsetT displacement_from_opcode_start;
252b5132
RH		 5258
5259 opcode = (unsigned char *) fragP->fr_opcode;
5260
47926f60 5261 /* Address we want to reach in file space. */
252b5132 5262 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 5263
47926f60 5264 /* Address opcode resides at in file space. */
252b5132
RH		 5265 opcode_address = fragP->fr_address + fragP->fr_fix;
5266
47926f60 5267 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 5268 displacement_from_opcode_start = target_address - opcode_address;
5269
fddf5b5b 5270 if ((fragP->fr_subtype & BIG) == 0)
252b5132 5271 {
47926f60
KH		 5272 /* Don't have to change opcode. */
5273 extension = 1; /* 1 opcode + 1 displacement */
252b5132 5274 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 5275 }
5276 else
5277 {
5278 if (no_cond_jump_promotion
5279 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
5280 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 5281
fddf5b5b
AM		 5282 switch (fragP->fr_subtype)
5283 {
5284 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5285 extension = 4; /* 1 opcode + 4 displacement */
5286 opcode[0] = 0xe9;
5287 where_to_put_displacement = &opcode[1];
5288 break;
252b5132 5289
fddf5b5b
AM		 5290 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5291 extension = 2; /* 1 opcode + 2 displacement */
5292 opcode[0] = 0xe9;
5293 where_to_put_displacement = &opcode[1];
5294 break;
252b5132 5295
fddf5b5b
AM		 5296 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5297 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5298 extension = 5; /* 2 opcode + 4 displacement */
5299 opcode[1] = opcode[0] + 0x10;
5300 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5301 where_to_put_displacement = &opcode[2];
5302 break;
252b5132 5303
fddf5b5b
AM		 5304 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5305 extension = 3; /* 2 opcode + 2 displacement */
5306 opcode[1] = opcode[0] + 0x10;
5307 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5308 where_to_put_displacement = &opcode[2];
5309 break;
252b5132 5310
fddf5b5b
AM		 5311 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5312 extension = 4;
5313 opcode[0] ^= 1;
5314 opcode[1] = 3;
5315 opcode[2] = 0xe9;
5316 where_to_put_displacement = &opcode[3];
5317 break;
5318
5319 default:
5320 BAD_CASE (fragP->fr_subtype);
5321 break;
5322 }
252b5132 5323 }
fddf5b5b 5324
7b81dfbb
AJ		 5325 /* If size if less then four we are sure that the operand fits,
5326 but if it's 4, then it could be that the displacement is larger
5327 then -/+ 2GB. */
5328 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5329 && object_64bit
5330 && ((addressT) (displacement_from_opcode_start - extension
5331 + ((addressT) 1 << 31))
5332 > (((addressT) 2 << 31) - 1)))
5333 {
5334 as_bad_where (fragP->fr_file, fragP->fr_line,
5335 _("jump target out of range"));
5336 /* Make us emit 0. */
5337 displacement_from_opcode_start = extension;
5338 }
47926f60 5339 /* Now put displacement after opcode. */
252b5132
RH		 5340 md_number_to_chars ((char *) where_to_put_displacement,
5341 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5342 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5343 fragP->fr_fix += extension;
5344}
5345\f
47926f60
KH		 5346/* Size of byte displacement jmp. */
5347int md_short_jump_size = 2;
5348
5349/* Size of dword displacement jmp. */
5350int md_long_jump_size = 5;
252b5132 5351
252b5132
RH		 5352void
5353md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5354 char *ptr;
5355 addressT from_addr, to_addr;
ab9da554
ILT		 5356 fragS *frag ATTRIBUTE_UNUSED;
5357 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5358{
847f7ad4 5359 offsetT offset;
252b5132
RH		 5360
5361 offset = to_addr - (from_addr + 2);
47926f60
KH		 5362 /* Opcode for byte-disp jump. */
5363 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5364 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5365}
5366
5367void
5368md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5369 char *ptr;
5370 addressT from_addr, to_addr;
a38cf1db
AM		 5371 fragS *frag ATTRIBUTE_UNUSED;
5372 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5373{
847f7ad4 5374 offsetT offset;
252b5132 5375
a38cf1db
AM		 5376 offset = to_addr - (from_addr + 5);
5377 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5378 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5379}
5380\f
5381/* Apply a fixup (fixS) to segment data, once it has been determined
5382 by our caller that we have all the info we need to fix it up.
5383
5384 On the 386, immediates, displacements, and data pointers are all in
5385 the same (little-endian) format, so we don't need to care about which
5386 we are handling. */
5387
94f592af 5388void
55cf6793 5389md_apply_fix (fixP, valP, seg)
47926f60
KH		 5390 /* The fix we're to put in. */
5391 fixS *fixP;
47926f60 5392 /* Pointer to the value of the bits. */
c6682705 5393 valueT *valP;
47926f60
KH		 5394 /* Segment fix is from. */
5395 segT seg ATTRIBUTE_UNUSED;
252b5132 5396{
94f592af 5397 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5398 valueT value = *valP;
252b5132 5399
f86103b7 5400#if !defined (TE_Mach)
93382f6d
AM		 5401 if (fixP->fx_pcrel)
5402 {
5403 switch (fixP->fx_r_type)
5404 {
5865bb77
ILT		 5405 default:
5406 break;
5407
d6ab8113
JB		 5408 case BFD_RELOC_64:
5409 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5410 break;
93382f6d 5411 case BFD_RELOC_32:
ae8887b5 5412 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5413 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5414 break;
5415 case BFD_RELOC_16:
5416 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5417 break;
5418 case BFD_RELOC_8:
5419 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5420 break;
5421 }
5422 }
252b5132 5423
a161fe53 5424 if (fixP->fx_addsy != NULL
31312f95 5425 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5426 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5427 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5428 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5429 && !use_rela_relocations)
252b5132 5430 {
31312f95
AM		 5431 /* This is a hack. There should be a better way to handle this.
5432 This covers for the fact that bfd_install_relocation will
5433 subtract the current location (for partial_inplace, PC relative
5434 relocations); see more below. */
252b5132 5435#ifndef OBJ_AOUT
718ddfc0 5436 if (IS_ELF
252b5132
RH		 5437#ifdef TE_PE
5438 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5439#endif
5440 )
5441 value += fixP->fx_where + fixP->fx_frag->fr_address;
5442#endif
5443#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5444 if (IS_ELF)
252b5132 5445 {
6539b54b 5446 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5447
6539b54b 5448 if ((sym_seg == seg
2f66722d 5449 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5450 && sym_seg != absolute_section))
ae6063d4 5451 && !generic_force_reloc (fixP))
2f66722d
AM		 5452 {
5453 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5454 bfd_install_relocation subtracts them out again. I think
5455 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5456 it. FIXME. */
5457 value += fixP->fx_where + fixP->fx_frag->fr_address;
5458 }
252b5132
RH		 5459 }
5460#endif
5461#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5462 /* For some reason, the PE format does not store a
5463 section address offset for a PC relative symbol. */
5464 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5465 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5466 value += md_pcrel_from (fixP);
5467#endif
5468 }
5469
5470 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5471 and we must not disappoint it. */
252b5132 5472#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5473 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5474 switch (fixP->fx_r_type)
5475 {
5476 case BFD_RELOC_386_PLT32:
3e73aa7c 5477 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5478 /* Make the jump instruction point to the address of the operand. At
5479 runtime we merely add the offset to the actual PLT entry. */
5480 value = -4;
5481 break;
31312f95 5482
13ae64f3
JJ		 5483 case BFD_RELOC_386_TLS_GD:
5484 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5485 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5486 case BFD_RELOC_386_TLS_IE:
5487 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5488 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5489 case BFD_RELOC_X86_64_TLSGD:
5490 case BFD_RELOC_X86_64_TLSLD:
5491 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5492 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5493 value = 0; /* Fully resolved at runtime. No addend. */
5494 /* Fallthrough */
5495 case BFD_RELOC_386_TLS_LE:
5496 case BFD_RELOC_386_TLS_LDO_32:
5497 case BFD_RELOC_386_TLS_LE_32:
5498 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5499 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5500 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5501 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5502 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5503 break;
5504
67a4f2b7
AO		 5505 case BFD_RELOC_386_TLS_DESC_CALL:
5506 case BFD_RELOC_X86_64_TLSDESC_CALL:
5507 value = 0; /* Fully resolved at runtime. No addend. */
5508 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5509 fixP->fx_done = 0;
5510 return;
5511
00f7efb6
JJ		 5512 case BFD_RELOC_386_GOT32:
5513 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5514 value = 0; /* Fully resolved at runtime. No addend. */
5515 break;
47926f60
KH		 5516
5517 case BFD_RELOC_VTABLE_INHERIT:
5518 case BFD_RELOC_VTABLE_ENTRY:
5519 fixP->fx_done = 0;
94f592af 5520 return;
47926f60
KH		 5521
5522 default:
5523 break;
5524 }
5525#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5526 *valP = value;
f86103b7 5527#endif /* !defined (TE_Mach) */
3e73aa7c 5528
3e73aa7c 5529 /* Are we finished with this relocation now? */
c6682705 5530 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5531 fixP->fx_done = 1;
5532 else if (use_rela_relocations)
5533 {
5534 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5535 /* Remember value for tc_gen_reloc. */
5536 fixP->fx_addnumber = value;
3e73aa7c
JH		 5537 value = 0;
5538 }
f86103b7 5539
94f592af 5540 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5541}
252b5132 5542\f
252b5132
RH		 5543#define MAX_LITTLENUMS 6
5544
47926f60
KH		 5545/* Turn the string pointed to by litP into a floating point constant
5546 of type TYPE, and emit the appropriate bytes. The number of
5547 LITTLENUMS emitted is stored in *SIZEP. An error message is
5548 returned, or NULL on OK. */
5549
252b5132
RH		 5550char *
5551md_atof (type, litP, sizeP)
2ab9b79e 5552 int type;
252b5132
RH		 5553 char *litP;
5554 int *sizeP;
5555{
5556 int prec;
5557 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5558 LITTLENUM_TYPE *wordP;
5559 char *t;
5560
5561 switch (type)
5562 {
5563 case 'f':
5564 case 'F':
5565 prec = 2;
5566 break;
5567
5568 case 'd':
5569 case 'D':
5570 prec = 4;
5571 break;
5572
5573 case 'x':
5574 case 'X':
5575 prec = 5;
5576 break;
5577
5578 default:
5579 *sizeP = 0;
5580 return _("Bad call to md_atof ()");
5581 }
5582 t = atof_ieee (input_line_pointer, type, words);
5583 if (t)
5584 input_line_pointer = t;
5585
5586 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5587 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5588 the bigendian 386. */
5589 for (wordP = words + prec - 1; prec--;)
5590 {
5591 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5592 litP += sizeof (LITTLENUM_TYPE);
5593 }
5594 return 0;
5595}
5596\f
2d545b82 5597static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5598
252b5132
RH		 5599static char *
5600output_invalid (c)
5601 int c;
5602{
3882b010 5603 if (ISPRINT (c))
f9f21a03
L		 5604 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5605 "'%c'", c);
252b5132 5606 else
f9f21a03 5607 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5608 "(0x%x)", (unsigned char) c);
252b5132
RH		 5609 return output_invalid_buf;
5610}
5611
af6bdddf 5612/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5613
5614static const reg_entry *
4d1bb795 5615parse_real_register (char *reg_string, char **end_op)
252b5132 5616{
af6bdddf
AM		 5617 char *s = reg_string;
5618 char *p;
252b5132
RH		 5619 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5620 const reg_entry *r;
5621
5622 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5623 if (*s == REGISTER_PREFIX)
5624 ++s;
5625
5626 if (is_space_char (*s))
5627 ++s;
5628
5629 p = reg_name_given;
af6bdddf 5630 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5631 {
5632 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5633 return (const reg_entry *) NULL;
5634 s++;
252b5132
RH		 5635 }
5636
6588847e
DN		 5637 /* For naked regs, make sure that we are not dealing with an identifier.
5638 This prevents confusing an identifier like `eax_var' with register
5639 `eax'. */
5640 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5641 return (const reg_entry *) NULL;
5642
af6bdddf 5643 *end_op = s;
252b5132
RH		 5644
5645 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5646
5f47d35b 5647 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5648 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5649 {
5f47d35b
AM		 5650 if (is_space_char (*s))
5651 ++s;
5652 if (*s == '(')
5653 {
af6bdddf 5654 ++s;
5f47d35b
AM		 5655 if (is_space_char (*s))
5656 ++s;
5657 if (*s >= '0' && *s <= '7')
5658 {
5659 r = &i386_float_regtab[*s - '0'];
af6bdddf 5660 ++s;
5f47d35b
AM		 5661 if (is_space_char (*s))
5662 ++s;
5663 if (*s == ')')
5664 {
5665 *end_op = s + 1;
5666 return r;
5667 }
5f47d35b 5668 }
47926f60 5669 /* We have "%st(" then garbage. */
5f47d35b
AM		 5670 return (const reg_entry *) NULL;
5671 }
5672 }
5673
1ae00879 5674 if (r != NULL
20f0a1fc 5675 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5676 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5677 && flag_code != CODE_64BIT)
20f0a1fc 5678 return (const reg_entry *) NULL;
1ae00879 5679
252b5132
RH		 5680 return r;
5681}
4d1bb795
JB		 5682
5683/* REG_STRING starts *before* REGISTER_PREFIX. */
5684
5685static const reg_entry *
5686parse_register (char *reg_string, char **end_op)
5687{
5688 const reg_entry *r;
5689
5690 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5691 r = parse_real_register (reg_string, end_op);
5692 else
5693 r = NULL;
5694 if (!r)
5695 {
5696 char *save = input_line_pointer;
5697 char c;
5698 symbolS *symbolP;
5699
5700 input_line_pointer = reg_string;
5701 c = get_symbol_end ();
5702 symbolP = symbol_find (reg_string);
5703 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5704 {
5705 const expressionS *e = symbol_get_value_expression (symbolP);
5706
5707 know (e->X_op == O_register);
5708 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5709 r = i386_regtab + e->X_add_number;
5710 *end_op = input_line_pointer;
5711 }
5712 *input_line_pointer = c;
5713 input_line_pointer = save;
5714 }
5715 return r;
5716}
5717
5718int
5719i386_parse_name (char *name, expressionS *e, char *nextcharP)
5720{
5721 const reg_entry *r;
5722 char *end = input_line_pointer;
5723
5724 *end = *nextcharP;
5725 r = parse_register (name, &input_line_pointer);
5726 if (r && end <= input_line_pointer)
5727 {
5728 *nextcharP = *input_line_pointer;
5729 *input_line_pointer = 0;
5730 e->X_op = O_register;
5731 e->X_add_number = r - i386_regtab;
5732 return 1;
5733 }
5734 input_line_pointer = end;
5735 *end = 0;
5736 return 0;
5737}
5738
5739void
5740md_operand (expressionS *e)
5741{
5742 if (*input_line_pointer == REGISTER_PREFIX)
5743 {
5744 char *end;
5745 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5746
5747 if (r)
5748 {
5749 e->X_op = O_register;
5750 e->X_add_number = r - i386_regtab;
5751 input_line_pointer = end;
5752 }
5753 }
5754}
5755
252b5132 5756\f
4cc782b5 5757#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5758const char *md_shortopts = "kVQ:sqn";
252b5132 5759#else
12b55ccc 5760const char *md_shortopts = "qn";
252b5132 5761#endif
6e0b89ee 5762
3e73aa7c 5763#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5764#define OPTION_64 (OPTION_MD_BASE + 1)
5765#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 5766#define OPTION_MARCH (OPTION_MD_BASE + 3)
5767#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 5768
99ad8390
NC		 5769struct option md_longopts[] =
5770{
3e73aa7c 5771 {"32", no_argument, NULL, OPTION_32},
99ad8390 5772#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 5773 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5774#endif
b3b91714 5775 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 5776 {"march", required_argument, NULL, OPTION_MARCH},
5777 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 5778 {NULL, no_argument, NULL, 0}
5779};
5780size_t md_longopts_size = sizeof (md_longopts);
5781
5782int
9103f4f4 5783md_parse_option (int c, char *arg)
252b5132 5784{
9103f4f4
L		 5785 unsigned int i;
5786
252b5132
RH		 5787 switch (c)
5788 {
12b55ccc
L		 5789 case 'n':
5790 optimize_align_code = 0;
5791 break;
5792
a38cf1db
AM		 5793 case 'q':
5794 quiet_warnings = 1;
252b5132
RH		 5795 break;
5796
5797#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5798 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5799 should be emitted or not. FIXME: Not implemented. */
5800 case 'Q':
252b5132
RH		 5801 break;
5802
5803 /* -V: SVR4 argument to print version ID. */
5804 case 'V':
5805 print_version_id ();
5806 break;
5807
a38cf1db
AM		 5808 /* -k: Ignore for FreeBSD compatibility. */
5809 case 'k':
252b5132 5810 break;
4cc782b5
ILT		 5811
5812 case 's':
5813 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5814 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5815 break;
99ad8390
NC		 5816#endif
5817#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 5818 case OPTION_64:
5819 {
5820 const char **list, **l;
5821
3e73aa7c
JH		 5822 list = bfd_target_list ();
5823 for (l = list; *l != NULL; l++)
99ad8390
NC		 5824 if ( strncmp (*l, "elf64-x86-64", 12) == 0
5825 || strcmp (*l, "coff-x86-64") == 0
5826 || strcmp (*l, "pe-x86-64") == 0
5827 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 5828 {
5829 default_arch = "x86_64";
5830 break;
5831 }
3e73aa7c 5832 if (*l == NULL)
6e0b89ee 5833 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5834 free (list);
5835 }
5836 break;
5837#endif
252b5132 5838
6e0b89ee
AM		 5839 case OPTION_32:
5840 default_arch = "i386";
5841 break;
5842
b3b91714
AM		 5843 case OPTION_DIVIDE:
5844#ifdef SVR4_COMMENT_CHARS
5845 {
5846 char *n, *t;
5847 const char *s;
5848
5849 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5850 t = n;
5851 for (s = i386_comment_chars; *s != '\0'; s++)
5852 if (*s != '/')
5853 *t++ = *s;
5854 *t = '\0';
5855 i386_comment_chars = n;
5856 }
5857#endif
5858 break;
5859
9103f4f4
L		 5860 case OPTION_MARCH:
5861 if (*arg == '.')
5862 as_fatal (_("Invalid -march= option: `%s'"), arg);
5863 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5864 {
5865 if (strcmp (arg, cpu_arch [i].name) == 0)
5866 {
ccc9c027 5867 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 5868 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 5869 if (!cpu_arch_tune_set)
5870 {
5871 cpu_arch_tune = cpu_arch_isa;
5872 cpu_arch_tune_flags = cpu_arch_isa_flags;
5873 }
9103f4f4
L		 5874 break;
5875 }
5876 }
5877 if (i >= ARRAY_SIZE (cpu_arch))
5878 as_fatal (_("Invalid -march= option: `%s'"), arg);
5879 break;
5880
5881 case OPTION_MTUNE:
5882 if (*arg == '.')
5883 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5884 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5885 {
5886 if (strcmp (arg, cpu_arch [i].name) == 0)
5887 {
ccc9c027 5888 cpu_arch_tune_set = 1;
9103f4f4
L		 5889 cpu_arch_tune = cpu_arch [i].type;
5890 cpu_arch_tune_flags = cpu_arch[i].flags;
5891 break;
5892 }
5893 }
5894 if (i >= ARRAY_SIZE (cpu_arch))
5895 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5896 break;
5897
252b5132
RH		 5898 default:
5899 return 0;
5900 }
5901 return 1;
5902}
5903
5904void
5905md_show_usage (stream)
5906 FILE *stream;
5907{
4cc782b5
ILT		 5908#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5909 fprintf (stream, _("\
a38cf1db
AM		 5910 -Q ignored\n\
5911 -V print assembler version number\n\
b3b91714
AM		 5912 -k ignored\n"));
5913#endif
5914 fprintf (stream, _("\
12b55ccc 5915 -n Do not optimize code alignment\n\
b3b91714
AM		 5916 -q quieten some warnings\n"));
5917#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5918 fprintf (stream, _("\
a38cf1db 5919 -s ignored\n"));
b3b91714
AM		 5920#endif
5921#ifdef SVR4_COMMENT_CHARS
5922 fprintf (stream, _("\
5923 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 5924#else
5925 fprintf (stream, _("\
b3b91714 5926 --divide ignored\n"));
4cc782b5 5927#endif
9103f4f4
L		 5928 fprintf (stream, _("\
5929 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
5930 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
5931 yonah, merom, k6, athlon, k8, generic32, generic64\n"));
5932
252b5132
RH		 5933}
5934
99ad8390
NC		 5935#if defined(TE_PEP)
5936const char *
5937x86_64_target_format (void)
5938{
5939 if (strcmp (default_arch, "x86_64") == 0)
5940 {
5941 set_code_flag (CODE_64BIT);
5942 return COFF_TARGET_FORMAT;
5943 }
5944 else if (strcmp (default_arch, "i386") == 0)
5945 {
5946 set_code_flag (CODE_32BIT);
5947 return "coff-i386";
5948 }
5949
5950 as_fatal (_("Unknown architecture"));
5951 return NULL;
5952}
5953#endif
5954
3e73aa7c
JH		 5955#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5956 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 5957
5958/* Pick the target format to use. */
5959
47926f60 5960const char *
252b5132
RH		 5961i386_target_format ()
5962{
3e73aa7c 5963 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 5964 {
5965 set_code_flag (CODE_64BIT);
5966 if (cpu_arch_isa_flags == 0)
d32cad65 5967 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
9103f4f4
L		 5968 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
5969 |CpuSSE|CpuSSE2;
ccc9c027 5970 if (cpu_arch_tune_flags == 0)
d32cad65 5971 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
ccc9c027
L		 5972 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
5973 |CpuSSE|CpuSSE2;
9103f4f4 5974 }
3e73aa7c 5975 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 5976 {
5977 set_code_flag (CODE_32BIT);
5978 if (cpu_arch_isa_flags == 0)
d32cad65 5979 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
ccc9c027 5980 if (cpu_arch_tune_flags == 0)
d32cad65 5981 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
9103f4f4 5982 }
3e73aa7c
JH		 5983 else
5984 as_fatal (_("Unknown architecture"));
252b5132
RH		 5985 switch (OUTPUT_FLAVOR)
5986 {
4c63da97
AM		 5987#ifdef OBJ_MAYBE_AOUT
5988 case bfd_target_aout_flavour:
47926f60 5989 return AOUT_TARGET_FORMAT;
4c63da97
AM		 5990#endif
5991#ifdef OBJ_MAYBE_COFF
252b5132
RH		 5992 case bfd_target_coff_flavour:
5993 return "coff-i386";
4c63da97 5994#endif
3e73aa7c 5995#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 5996 case bfd_target_elf_flavour:
3e73aa7c 5997 {
e5cb08ac 5998 if (flag_code == CODE_64BIT)
4fa24527
JB		 5999 {
6000 object_64bit = 1;
6001 use_rela_relocations = 1;
6002 }
9d7cbccd 6003 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6004 }
4c63da97 6005#endif
252b5132
RH		 6006 default:
6007 abort ();
6008 return NULL;
6009 }
6010}
6011
47926f60 6012#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 6013
6014#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6015void i386_elf_emit_arch_note ()
6016{
718ddfc0 6017 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 6018 {
6019 char *p;
6020 asection *seg = now_seg;
6021 subsegT subseg = now_subseg;
6022 Elf_Internal_Note i_note;
6023 Elf_External_Note e_note;
6024 asection *note_secp;
6025 int len;
6026
6027 /* Create the .note section. */
6028 note_secp = subseg_new (".note", 0);
6029 bfd_set_section_flags (stdoutput,
6030 note_secp,
6031 SEC_HAS_CONTENTS | SEC_READONLY);
6032
6033 /* Process the arch string. */
6034 len = strlen (cpu_arch_name);
6035
6036 i_note.namesz = len + 1;
6037 i_note.descsz = 0;
6038 i_note.type = NT_ARCH;
6039 p = frag_more (sizeof (e_note.namesz));
6040 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6041 p = frag_more (sizeof (e_note.descsz));
6042 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6043 p = frag_more (sizeof (e_note.type));
6044 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6045 p = frag_more (len + 1);
6046 strcpy (p, cpu_arch_name);
6047
6048 frag_align (2, 0, 0);
6049
6050 subseg_set (seg, subseg);
6051 }
6052}
6053#endif
252b5132 6054\f
252b5132
RH		 6055symbolS *
6056md_undefined_symbol (name)
6057 char *name;
6058{
18dc2407
ILT		 6059 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6060 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6061 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6062 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6063 {
6064 if (!GOT_symbol)
6065 {
6066 if (symbol_find (name))
6067 as_bad (_("GOT already in symbol table"));
6068 GOT_symbol = symbol_new (name, undefined_section,
6069 (valueT) 0, &zero_address_frag);
6070 };
6071 return GOT_symbol;
6072 }
252b5132
RH		 6073 return 0;
6074}
6075
6076/* Round up a section size to the appropriate boundary. */
47926f60 6077
252b5132
RH		 6078valueT
6079md_section_align (segment, size)
ab9da554 6080 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6081 valueT size;
6082{
4c63da97
AM		 6083#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6084 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6085 {
6086 /* For a.out, force the section size to be aligned. If we don't do
6087 this, BFD will align it for us, but it will not write out the
6088 final bytes of the section. This may be a bug in BFD, but it is
6089 easier to fix it here since that is how the other a.out targets
6090 work. */
6091 int align;
6092
6093 align = bfd_get_section_alignment (stdoutput, segment);
6094 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6095 }
252b5132
RH		 6096#endif
6097
6098 return size;
6099}
6100
6101/* On the i386, PC-relative offsets are relative to the start of the
6102 next instruction. That is, the address of the offset, plus its
6103 size, since the offset is always the last part of the insn. */
6104
6105long
6106md_pcrel_from (fixP)
6107 fixS *fixP;
6108{
6109 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6110}
6111
6112#ifndef I386COFF
6113
6114static void
6115s_bss (ignore)
ab9da554 6116 int ignore ATTRIBUTE_UNUSED;
252b5132 6117{
29b0f896 6118 int temp;
252b5132 6119
8a75718c
JB		 6120#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6121 if (IS_ELF)
6122 obj_elf_section_change_hook ();
6123#endif
252b5132
RH		 6124 temp = get_absolute_expression ();
6125 subseg_set (bss_section, (subsegT) temp);
6126 demand_empty_rest_of_line ();
6127}
6128
6129#endif
6130
252b5132
RH		 6131void
6132i386_validate_fix (fixp)
6133 fixS *fixp;
6134{
6135 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6136 {
23df1078
JH		 6137 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6138 {
4fa24527 6139 if (!object_64bit)
23df1078
JH		 6140 abort ();
6141 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6142 }
6143 else
6144 {
4fa24527 6145 if (!object_64bit)
d6ab8113
JB		 6146 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6147 else
6148 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6149 }
252b5132
RH		 6150 fixp->fx_subsy = 0;
6151 }
6152}
6153
252b5132
RH		 6154arelent *
6155tc_gen_reloc (section, fixp)
ab9da554 6156 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6157 fixS *fixp;
6158{
6159 arelent *rel;
6160 bfd_reloc_code_real_type code;
6161
6162 switch (fixp->fx_r_type)
6163 {
3e73aa7c
JH		 6164 case BFD_RELOC_X86_64_PLT32:
6165 case BFD_RELOC_X86_64_GOT32:
6166 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6167 case BFD_RELOC_386_PLT32:
6168 case BFD_RELOC_386_GOT32:
6169 case BFD_RELOC_386_GOTOFF:
6170 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 6171 case BFD_RELOC_386_TLS_GD:
6172 case BFD_RELOC_386_TLS_LDM:
6173 case BFD_RELOC_386_TLS_LDO_32:
6174 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6175 case BFD_RELOC_386_TLS_IE:
6176 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 6177 case BFD_RELOC_386_TLS_LE_32:
6178 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 6179 case BFD_RELOC_386_TLS_GOTDESC:
6180 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 6181 case BFD_RELOC_X86_64_TLSGD:
6182 case BFD_RELOC_X86_64_TLSLD:
6183 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6184 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 6185 case BFD_RELOC_X86_64_GOTTPOFF:
6186 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 6187 case BFD_RELOC_X86_64_TPOFF64:
6188 case BFD_RELOC_X86_64_GOTOFF64:
6189 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 6190 case BFD_RELOC_X86_64_GOT64:
6191 case BFD_RELOC_X86_64_GOTPCREL64:
6192 case BFD_RELOC_X86_64_GOTPC64:
6193 case BFD_RELOC_X86_64_GOTPLT64:
6194 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 6195 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6196 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 6197 case BFD_RELOC_RVA:
6198 case BFD_RELOC_VTABLE_ENTRY:
6199 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 6200#ifdef TE_PE
6201 case BFD_RELOC_32_SECREL:
6202#endif
252b5132
RH		 6203 code = fixp->fx_r_type;
6204 break;
dbbaec26
L		 6205 case BFD_RELOC_X86_64_32S:
6206 if (!fixp->fx_pcrel)
6207 {
6208 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6209 code = fixp->fx_r_type;
6210 break;
6211 }
252b5132 6212 default:
93382f6d 6213 if (fixp->fx_pcrel)
252b5132 6214 {
93382f6d
AM		 6215 switch (fixp->fx_size)
6216 {
6217 default:
b091f402
AM		 6218 as_bad_where (fixp->fx_file, fixp->fx_line,
6219 _("can not do %d byte pc-relative relocation"),
6220 fixp->fx_size);
93382f6d
AM		 6221 code = BFD_RELOC_32_PCREL;
6222 break;
6223 case 1: code = BFD_RELOC_8_PCREL; break;
6224 case 2: code = BFD_RELOC_16_PCREL; break;
6225 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 6226#ifdef BFD64
6227 case 8: code = BFD_RELOC_64_PCREL; break;
6228#endif
93382f6d
AM		 6229 }
6230 }
6231 else
6232 {
6233 switch (fixp->fx_size)
6234 {
6235 default:
b091f402
AM		 6236 as_bad_where (fixp->fx_file, fixp->fx_line,
6237 _("can not do %d byte relocation"),
6238 fixp->fx_size);
93382f6d
AM		 6239 code = BFD_RELOC_32;
6240 break;
6241 case 1: code = BFD_RELOC_8; break;
6242 case 2: code = BFD_RELOC_16; break;
6243 case 4: code = BFD_RELOC_32; break;
937149dd 6244#ifdef BFD64
3e73aa7c 6245 case 8: code = BFD_RELOC_64; break;
937149dd 6246#endif
93382f6d 6247 }
252b5132
RH		 6248 }
6249 break;
6250 }
252b5132 6251
d182319b
JB		 6252 if ((code == BFD_RELOC_32
6253 || code == BFD_RELOC_32_PCREL
6254 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 6255 && GOT_symbol
6256 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 6257 {
4fa24527 6258 if (!object_64bit)
d6ab8113
JB		 6259 code = BFD_RELOC_386_GOTPC;
6260 else
6261 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 6262 }
7b81dfbb
AJ		 6263 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6264 && GOT_symbol
6265 && fixp->fx_addsy == GOT_symbol)
6266 {
6267 code = BFD_RELOC_X86_64_GOTPC64;
6268 }
252b5132
RH		 6269
6270 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 6271 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6272 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 6273
6274 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 6275
3e73aa7c
JH		 6276 if (!use_rela_relocations)
6277 {
6278 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6279 vtable entry to be used in the relocation's section offset. */
6280 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6281 rel->address = fixp->fx_offset;
252b5132 6282
c6682705 6283 rel->addend = 0;
3e73aa7c
JH		 6284 }
6285 /* Use the rela in 64bit mode. */
252b5132 6286 else
3e73aa7c 6287 {
062cd5e7
AS		 6288 if (!fixp->fx_pcrel)
6289 rel->addend = fixp->fx_offset;
6290 else
6291 switch (code)
6292 {
6293 case BFD_RELOC_X86_64_PLT32:
6294 case BFD_RELOC_X86_64_GOT32:
6295 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 6296 case BFD_RELOC_X86_64_TLSGD:
6297 case BFD_RELOC_X86_64_TLSLD:
6298 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 6299 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6300 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 6301 rel->addend = fixp->fx_offset - fixp->fx_size;
6302 break;
6303 default:
6304 rel->addend = (section->vma
6305 - fixp->fx_size
6306 + fixp->fx_addnumber
6307 + md_pcrel_from (fixp));
6308 break;
6309 }
3e73aa7c
JH		 6310 }
6311
252b5132
RH		 6312 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6313 if (rel->howto == NULL)
6314 {
6315 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 6316 _("cannot represent relocation type %s"),
252b5132
RH		 6317 bfd_get_reloc_code_name (code));
6318 /* Set howto to a garbage value so that we can keep going. */
6319 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6320 assert (rel->howto != NULL);
6321 }
6322
6323 return rel;
6324}
6325
64a0c779
DN		 6326\f
6327/* Parse operands using Intel syntax. This implements a recursive descent
6328 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6329 Programmer's Guide.
6330
6331 FIXME: We do not recognize the full operand grammar defined in the MASM
6332 documentation. In particular, all the structure/union and
6333 high-level macro operands are missing.
6334
6335 Uppercase words are terminals, lower case words are non-terminals.
6336 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6337 bars '|' denote choices. Most grammar productions are implemented in
6338 functions called 'intel_<production>'.
6339
6340 Initial production is 'expr'.
6341
9306ca4a 6342 addOp + | -
64a0c779
DN		 6343
6344 alpha [a-zA-Z]
6345
9306ca4a
JB		 6346 binOp & | AND | \| | OR | ^ | XOR
6347
64a0c779
DN		 6348 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6349
6350 constant digits [[ radixOverride ]]
6351
9306ca4a 6352 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 6353
6354 digits decdigit
b77a7acd
AJ		 6355 | digits decdigit
6356 | digits hexdigit
64a0c779
DN		 6357
6358 decdigit [0-9]
6359
9306ca4a
JB		 6360 e04 e04 addOp e05
6361 | e05
6362
6363 e05 e05 binOp e06
b77a7acd 6364 | e06
64a0c779
DN		 6365
6366 e06 e06 mulOp e09
b77a7acd 6367 | e09
64a0c779
DN		 6368
6369 e09 OFFSET e10
a724f0f4
JB		 6370 | SHORT e10
6371 | + e10
6372 | - e10
9306ca4a
JB		 6373 | ~ e10
6374 | NOT e10
64a0c779
DN		 6375 | e09 PTR e10
6376 | e09 : e10
6377 | e10
6378
6379 e10 e10 [ expr ]
b77a7acd 6380 | e11
64a0c779
DN		 6381
6382 e11 ( expr )
b77a7acd 6383 | [ expr ]
64a0c779
DN		 6384 | constant
6385 | dataType
6386 | id
6387 | $
6388 | register
6389
a724f0f4 6390 => expr expr cmpOp e04
9306ca4a 6391 | e04
64a0c779
DN		 6392
6393 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 6394 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 6395
6396 hexdigit a | b | c | d | e | f
b77a7acd 6397 | A | B | C | D | E | F
64a0c779
DN		 6398
6399 id alpha
b77a7acd 6400 | id alpha
64a0c779
DN		 6401 | id decdigit
6402
9306ca4a 6403 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 6404
6405 quote " | '
6406
6407 register specialRegister
b77a7acd 6408 | gpRegister
64a0c779
DN		 6409 | byteRegister
6410
6411 segmentRegister CS | DS | ES | FS | GS | SS
6412
9306ca4a 6413 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 6414 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 6415 | TR3 | TR4 | TR5 | TR6 | TR7
6416
64a0c779
DN		 6417 We simplify the grammar in obvious places (e.g., register parsing is
6418 done by calling parse_register) and eliminate immediate left recursion
6419 to implement a recursive-descent parser.
6420
a724f0f4
JB		 6421 expr e04 expr'
6422
6423 expr' cmpOp e04 expr'
6424 | Empty
9306ca4a
JB		 6425
6426 e04 e05 e04'
6427
6428 e04' addOp e05 e04'
6429 | Empty
64a0c779
DN		 6430
6431 e05 e06 e05'
6432
9306ca4a 6433 e05' binOp e06 e05'
b77a7acd 6434 | Empty
64a0c779
DN		 6435
6436 e06 e09 e06'
6437
6438 e06' mulOp e09 e06'
b77a7acd 6439 | Empty
64a0c779
DN		 6440
6441 e09 OFFSET e10 e09'
a724f0f4
JB		 6442 | SHORT e10'
6443 | + e10'
6444 | - e10'
6445 | ~ e10'
6446 | NOT e10'
b77a7acd 6447 | e10 e09'
64a0c779
DN		 6448
6449 e09' PTR e10 e09'
b77a7acd 6450 | : e10 e09'
64a0c779
DN		 6451 | Empty
6452
6453 e10 e11 e10'
6454
6455 e10' [ expr ] e10'
b77a7acd 6456 | Empty
64a0c779
DN		 6457
6458 e11 ( expr )
b77a7acd 6459 | [ expr ]
64a0c779
DN		 6460 | BYTE
6461 | WORD
6462 | DWORD
9306ca4a 6463 | FWORD
64a0c779 6464 | QWORD
9306ca4a
JB		 6465 | TBYTE
6466 | OWORD
6467 | XMMWORD
64a0c779
DN		 6468 | .
6469 | $
6470 | register
6471 | id
6472 | constant */
6473
6474/* Parsing structure for the intel syntax parser. Used to implement the
6475 semantic actions for the operand grammar. */
6476struct intel_parser_s
6477 {
6478 char *op_string; /* The string being parsed. */
6479 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6480 int op_modifier; /* Operand modifier. */
64a0c779 6481 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 6482 int in_offset; /* >=1 if parsing operand of offset. */
6483 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6484 const reg_entry *reg; /* Last register reference found. */
6485 char *disp; /* Displacement string being built. */
a724f0f4 6486 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6487 };
6488
6489static struct intel_parser_s intel_parser;
6490
6491/* Token structure for parsing intel syntax. */
6492struct intel_token
6493 {
6494 int code; /* Token code. */
6495 const reg_entry *reg; /* Register entry for register tokens. */
6496 char *str; /* String representation. */
6497 };
6498
6499static struct intel_token cur_token, prev_token;
6500
50705ef4
AM		 6501/* Token codes for the intel parser. Since T_SHORT is already used
6502 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6503#define T_NIL -1
6504#define T_CONST 1
6505#define T_REG 2
6506#define T_BYTE 3
6507#define T_WORD 4
9306ca4a
JB		 6508#define T_DWORD 5
6509#define T_FWORD 6
6510#define T_QWORD 7
6511#define T_TBYTE 8
6512#define T_XMMWORD 9
50705ef4 6513#undef T_SHORT
9306ca4a
JB		 6514#define T_SHORT 10
6515#define T_OFFSET 11
6516#define T_PTR 12
6517#define T_ID 13
6518#define T_SHL 14
6519#define T_SHR 15
64a0c779
DN		 6520
6521/* Prototypes for intel parser functions. */
6522static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 6523static void intel_get_token PARAMS ((void));
6524static void intel_putback_token PARAMS ((void));
6525static int intel_expr PARAMS ((void));
9306ca4a 6526static int intel_e04 PARAMS ((void));
cce0cbdc 6527static int intel_e05 PARAMS ((void));
cce0cbdc 6528static int intel_e06 PARAMS ((void));
cce0cbdc 6529static int intel_e09 PARAMS ((void));
a724f0f4 6530static int intel_bracket_expr PARAMS ((void));
cce0cbdc 6531static int intel_e10 PARAMS ((void));
cce0cbdc 6532static int intel_e11 PARAMS ((void));
64a0c779 6533
64a0c779
DN		 6534static int
6535i386_intel_operand (operand_string, got_a_float)
6536 char *operand_string;
6537 int got_a_float;
6538{
6539 int ret;
6540 char *p;
6541
a724f0f4
JB		 6542 p = intel_parser.op_string = xstrdup (operand_string);
6543 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6544
6545 for (;;)
64a0c779 6546 {
a724f0f4
JB		 6547 /* Initialize token holders. */
6548 cur_token.code = prev_token.code = T_NIL;
6549 cur_token.reg = prev_token.reg = NULL;
6550 cur_token.str = prev_token.str = NULL;
6551
6552 /* Initialize parser structure. */
6553 intel_parser.got_a_float = got_a_float;
6554 intel_parser.op_modifier = 0;
6555 intel_parser.is_mem = 0;
6556 intel_parser.in_offset = 0;
6557 intel_parser.in_bracket = 0;
6558 intel_parser.reg = NULL;
6559 intel_parser.disp[0] = '\0';
6560 intel_parser.next_operand = NULL;
6561
6562 /* Read the first token and start the parser. */
6563 intel_get_token ();
6564 ret = intel_expr ();
6565
6566 if (!ret)
6567 break;
6568
9306ca4a
JB		 6569 if (cur_token.code != T_NIL)
6570 {
6571 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6572 current_templates->start->name, cur_token.str);
6573 ret = 0;
6574 }
64a0c779
DN		 6575 /* If we found a memory reference, hand it over to i386_displacement
6576 to fill in the rest of the operand fields. */
9306ca4a 6577 else if (intel_parser.is_mem)
64a0c779
DN		 6578 {
6579 if ((i.mem_operands == 1
6580 && (current_templates->start->opcode_modifier & IsString) == 0)
6581 || i.mem_operands == 2)
6582 {
6583 as_bad (_("too many memory references for '%s'"),
6584 current_templates->start->name);
6585 ret = 0;
6586 }
6587 else
6588 {
6589 char *s = intel_parser.disp;
6590 i.mem_operands++;
6591
a724f0f4
JB		 6592 if (!quiet_warnings && intel_parser.is_mem < 0)
6593 /* See the comments in intel_bracket_expr. */
6594 as_warn (_("Treating `%s' as memory reference"), operand_string);
6595
64a0c779
DN		 6596 /* Add the displacement expression. */
6597 if (*s != '\0')
a4622f40
AM		 6598 ret = i386_displacement (s, s + strlen (s));
6599 if (ret)
a724f0f4
JB		 6600 {
6601 /* Swap base and index in 16-bit memory operands like
6602 [si+bx]. Since i386_index_check is also used in AT&T
6603 mode we have to do that here. */
6604 if (i.base_reg
6605 && i.index_reg
6606 && (i.base_reg->reg_type & Reg16)
6607 && (i.index_reg->reg_type & Reg16)
6608 && i.base_reg->reg_num >= 6
6609 && i.index_reg->reg_num < 6)
6610 {
6611 const reg_entry *base = i.index_reg;
6612
6613 i.index_reg = i.base_reg;
6614 i.base_reg = base;
6615 }
6616 ret = i386_index_check (operand_string);
6617 }
64a0c779
DN		 6618 }
6619 }
6620
6621 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6622 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6623 || intel_parser.reg == NULL)
6624 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6625
6626 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6627 ret = 0;
6628 if (!ret || !intel_parser.next_operand)
6629 break;
6630 intel_parser.op_string = intel_parser.next_operand;
6631 this_operand = i.operands++;
64a0c779
DN		 6632 }
6633
6634 free (p);
6635 free (intel_parser.disp);
6636
6637 return ret;
6638}
6639
a724f0f4
JB		 6640#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6641
6642/* expr e04 expr'
6643
6644 expr' cmpOp e04 expr'
6645 | Empty */
64a0c779
DN		 6646static int
6647intel_expr ()
6648{
a724f0f4
JB		 6649 /* XXX Implement the comparison operators. */
6650 return intel_e04 ();
9306ca4a
JB		 6651}
6652
a724f0f4 6653/* e04 e05 e04'
9306ca4a 6654
a724f0f4 6655 e04' addOp e05 e04'
9306ca4a
JB		 6656 | Empty */
6657static int
6658intel_e04 ()
6659{
a724f0f4 6660 int nregs = -1;
9306ca4a 6661
a724f0f4 6662 for (;;)
9306ca4a 6663 {
a724f0f4
JB		 6664 if (!intel_e05())
6665 return 0;
9306ca4a 6666
a724f0f4
JB		 6667 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6668 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6669
a724f0f4
JB		 6670 if (cur_token.code == '+')
6671 nregs = -1;
6672 else if (cur_token.code == '-')
6673 nregs = NUM_ADDRESS_REGS;
6674 else
6675 return 1;
64a0c779 6676
a724f0f4
JB		 6677 strcat (intel_parser.disp, cur_token.str);
6678 intel_match_token (cur_token.code);
6679 }
64a0c779
DN		 6680}
6681
64a0c779
DN		 6682/* e05 e06 e05'
6683
9306ca4a 6684 e05' binOp e06 e05'
64a0c779
DN		 6685 | Empty */
6686static int
6687intel_e05 ()
6688{
a724f0f4 6689 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6690
a724f0f4 6691 for (;;)
64a0c779 6692 {
a724f0f4
JB		 6693 if (!intel_e06())
6694 return 0;
6695
6696 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6697 {
6698 char str[2];
6699
6700 str[0] = cur_token.code;
6701 str[1] = 0;
6702 strcat (intel_parser.disp, str);
6703 }
6704 else
6705 break;
9306ca4a 6706
64a0c779
DN		 6707 intel_match_token (cur_token.code);
6708
a724f0f4
JB		 6709 if (nregs < 0)
6710 nregs = ~nregs;
64a0c779 6711 }
a724f0f4
JB		 6712 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6713 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6714 return 1;
4a1805b1 6715}
64a0c779
DN		 6716
6717/* e06 e09 e06'
6718
6719 e06' mulOp e09 e06'
b77a7acd 6720 | Empty */
64a0c779
DN		 6721static int
6722intel_e06 ()
6723{
a724f0f4 6724 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6725
a724f0f4 6726 for (;;)
64a0c779 6727 {
a724f0f4
JB		 6728 if (!intel_e09())
6729 return 0;
9306ca4a 6730
a724f0f4
JB		 6731 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6732 {
6733 char str[2];
9306ca4a 6734
a724f0f4
JB		 6735 str[0] = cur_token.code;
6736 str[1] = 0;
6737 strcat (intel_parser.disp, str);
6738 }
6739 else if (cur_token.code == T_SHL)
6740 strcat (intel_parser.disp, "<<");
6741 else if (cur_token.code == T_SHR)
6742 strcat (intel_parser.disp, ">>");
6743 else
6744 break;
9306ca4a 6745
64e74474 6746 intel_match_token (cur_token.code);
64a0c779 6747
a724f0f4
JB		 6748 if (nregs < 0)
6749 nregs = ~nregs;
64a0c779 6750 }
a724f0f4
JB		 6751 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6752 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6753 return 1;
64a0c779
DN		 6754}
6755
a724f0f4
JB		 6756/* e09 OFFSET e09
6757 | SHORT e09
6758 | + e09
6759 | - e09
6760 | ~ e09
6761 | NOT e09
9306ca4a
JB		 6762 | e10 e09'
6763
64a0c779 6764 e09' PTR e10 e09'
b77a7acd 6765 | : e10 e09'
64a0c779
DN		 6766 | Empty */
6767static int
6768intel_e09 ()
6769{
a724f0f4
JB		 6770 int nregs = ~NUM_ADDRESS_REGS;
6771 int in_offset = 0;
6772
6773 for (;;)
64a0c779 6774 {
a724f0f4
JB		 6775 /* Don't consume constants here. */
6776 if (cur_token.code == '+' || cur_token.code == '-')
6777 {
6778 /* Need to look one token ahead - if the next token
6779 is a constant, the current token is its sign. */
6780 int next_code;
6781
6782 intel_match_token (cur_token.code);
6783 next_code = cur_token.code;
6784 intel_putback_token ();
6785 if (next_code == T_CONST)
6786 break;
6787 }
6788
6789 /* e09 OFFSET e09 */
6790 if (cur_token.code == T_OFFSET)
6791 {
6792 if (!in_offset++)
6793 ++intel_parser.in_offset;
6794 }
6795
6796 /* e09 SHORT e09 */
6797 else if (cur_token.code == T_SHORT)
6798 intel_parser.op_modifier |= 1 << T_SHORT;
6799
6800 /* e09 + e09 */
6801 else if (cur_token.code == '+')
6802 strcat (intel_parser.disp, "+");
6803
6804 /* e09 - e09
6805 | ~ e09
6806 | NOT e09 */
6807 else if (cur_token.code == '-' || cur_token.code == '~')
6808 {
6809 char str[2];
64a0c779 6810
a724f0f4
JB		 6811 if (nregs < 0)
6812 nregs = ~nregs;
6813 str[0] = cur_token.code;
6814 str[1] = 0;
6815 strcat (intel_parser.disp, str);
6816 }
6817
6818 /* e09 e10 e09' */
6819 else
6820 break;
6821
6822 intel_match_token (cur_token.code);
64a0c779
DN		 6823 }
6824
a724f0f4 6825 for (;;)
9306ca4a 6826 {
a724f0f4
JB		 6827 if (!intel_e10 ())
6828 return 0;
9306ca4a 6829
a724f0f4
JB		 6830 /* e09' PTR e10 e09' */
6831 if (cur_token.code == T_PTR)
6832 {
6833 char suffix;
9306ca4a 6834
a724f0f4
JB		 6835 if (prev_token.code == T_BYTE)
6836 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6837
a724f0f4
JB		 6838 else if (prev_token.code == T_WORD)
6839 {
6840 if (current_templates->start->name[0] == 'l'
6841 && current_templates->start->name[2] == 's'
6842 && current_templates->start->name[3] == 0)
6843 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6844 else if (intel_parser.got_a_float == 2) /* "fi..." */
6845 suffix = SHORT_MNEM_SUFFIX;
6846 else
6847 suffix = WORD_MNEM_SUFFIX;
6848 }
64a0c779 6849
a724f0f4
JB		 6850 else if (prev_token.code == T_DWORD)
6851 {
6852 if (current_templates->start->name[0] == 'l'
6853 && current_templates->start->name[2] == 's'
6854 && current_templates->start->name[3] == 0)
6855 suffix = WORD_MNEM_SUFFIX;
6856 else if (flag_code == CODE_16BIT
6857 && (current_templates->start->opcode_modifier
435acd52 6858 & (Jump | JumpDword)))
a724f0f4
JB		 6859 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6860 else if (intel_parser.got_a_float == 1) /* "f..." */
6861 suffix = SHORT_MNEM_SUFFIX;
6862 else
6863 suffix = LONG_MNEM_SUFFIX;
6864 }
9306ca4a 6865
a724f0f4
JB		 6866 else if (prev_token.code == T_FWORD)
6867 {
6868 if (current_templates->start->name[0] == 'l'
6869 && current_templates->start->name[2] == 's'
6870 && current_templates->start->name[3] == 0)
6871 suffix = LONG_MNEM_SUFFIX;
6872 else if (!intel_parser.got_a_float)
6873 {
6874 if (flag_code == CODE_16BIT)
6875 add_prefix (DATA_PREFIX_OPCODE);
6876 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6877 }
6878 else
6879 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6880 }
64a0c779 6881
a724f0f4
JB		 6882 else if (prev_token.code == T_QWORD)
6883 {
6884 if (intel_parser.got_a_float == 1) /* "f..." */
6885 suffix = LONG_MNEM_SUFFIX;
6886 else
6887 suffix = QWORD_MNEM_SUFFIX;
6888 }
64a0c779 6889
a724f0f4
JB		 6890 else if (prev_token.code == T_TBYTE)
6891 {
6892 if (intel_parser.got_a_float == 1)
6893 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6894 else
6895 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6896 }
9306ca4a 6897
a724f0f4 6898 else if (prev_token.code == T_XMMWORD)
9306ca4a 6899 {
a724f0f4
JB		 6900 /* XXX ignored for now, but accepted since gcc uses it */
6901 suffix = 0;
9306ca4a 6902 }
64a0c779 6903
f16b83df 6904 else
a724f0f4
JB		 6905 {
6906 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6907 return 0;
6908 }
6909
435acd52
JB		 6910 /* Operands for jump/call using 'ptr' notation denote absolute
6911 addresses. */
6912 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6913 i.types[this_operand] |= JumpAbsolute;
6914
a724f0f4
JB		 6915 if (current_templates->start->base_opcode == 0x8d /* lea */)
6916 ;
6917 else if (!i.suffix)
6918 i.suffix = suffix;
6919 else if (i.suffix != suffix)
6920 {
6921 as_bad (_("Conflicting operand modifiers"));
6922 return 0;
6923 }
64a0c779 6924
9306ca4a
JB		 6925 }
6926
a724f0f4
JB		 6927 /* e09' : e10 e09' */
6928 else if (cur_token.code == ':')
9306ca4a 6929 {
a724f0f4
JB		 6930 if (prev_token.code != T_REG)
6931 {
6932 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6933 segment/group identifier (which we don't have), using comma
6934 as the operand separator there is even less consistent, since
6935 there all branches only have a single operand. */
6936 if (this_operand != 0
6937 || intel_parser.in_offset
6938 || intel_parser.in_bracket
6939 || (!(current_templates->start->opcode_modifier
6940 & (Jump|JumpDword|JumpInterSegment))
6941 && !(current_templates->start->operand_types[0]
6942 & JumpAbsolute)))
6943 return intel_match_token (T_NIL);
6944 /* Remember the start of the 2nd operand and terminate 1st
6945 operand here.
6946 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6947 another expression), but it gets at least the simplest case
6948 (a plain number or symbol on the left side) right. */
6949 intel_parser.next_operand = intel_parser.op_string;
6950 *--intel_parser.op_string = '\0';
6951 return intel_match_token (':');
6952 }
9306ca4a 6953 }
64a0c779 6954
a724f0f4 6955 /* e09' Empty */
64a0c779 6956 else
a724f0f4 6957 break;
64a0c779 6958
a724f0f4
JB		 6959 intel_match_token (cur_token.code);
6960
6961 }
6962
6963 if (in_offset)
6964 {
6965 --intel_parser.in_offset;
6966 if (nregs < 0)
6967 nregs = ~nregs;
6968 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 6969 {
a724f0f4 6970 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 6971 return 0;
6972 }
a724f0f4
JB		 6973 intel_parser.op_modifier |= 1 << T_OFFSET;
6974 }
9306ca4a 6975
a724f0f4
JB		 6976 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6977 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
6978 return 1;
6979}
64a0c779 6980
a724f0f4
JB		 6981static int
6982intel_bracket_expr ()
6983{
6984 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
6985 const char *start = intel_parser.op_string;
6986 int len;
6987
6988 if (i.op[this_operand].regs)
6989 return intel_match_token (T_NIL);
6990
6991 intel_match_token ('[');
6992
6993 /* Mark as a memory operand only if it's not already known to be an
6994 offset expression. If it's an offset expression, we need to keep
6995 the brace in. */
6996 if (!intel_parser.in_offset)
6997 {
6998 ++intel_parser.in_bracket;
435acd52
JB		 6999
7000 /* Operands for jump/call inside brackets denote absolute addresses. */
7001 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7002 i.types[this_operand] |= JumpAbsolute;
7003
a724f0f4
JB		 7004 /* Unfortunately gas always diverged from MASM in a respect that can't
7005 be easily fixed without risking to break code sequences likely to be
7006 encountered (the testsuite even check for this): MASM doesn't consider
7007 an expression inside brackets unconditionally as a memory reference.
7008 When that is e.g. a constant, an offset expression, or the sum of the
7009 two, this is still taken as a constant load. gas, however, always
7010 treated these as memory references. As a compromise, we'll try to make
7011 offset expressions inside brackets work the MASM way (since that's
7012 less likely to be found in real world code), but make constants alone
7013 continue to work the traditional gas way. In either case, issue a
7014 warning. */
7015 intel_parser.op_modifier &= ~was_offset;
64a0c779 7016 }
a724f0f4 7017 else
64e74474 7018 strcat (intel_parser.disp, "[");
a724f0f4
JB		 7019
7020 /* Add a '+' to the displacement string if necessary. */
7021 if (*intel_parser.disp != '\0'
7022 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7023 strcat (intel_parser.disp, "+");
64a0c779 7024
a724f0f4
JB		 7025 if (intel_expr ()
7026 && (len = intel_parser.op_string - start - 1,
7027 intel_match_token (']')))
64a0c779 7028 {
a724f0f4
JB		 7029 /* Preserve brackets when the operand is an offset expression. */
7030 if (intel_parser.in_offset)
7031 strcat (intel_parser.disp, "]");
7032 else
7033 {
7034 --intel_parser.in_bracket;
7035 if (i.base_reg || i.index_reg)
7036 intel_parser.is_mem = 1;
7037 if (!intel_parser.is_mem)
7038 {
7039 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7040 /* Defer the warning until all of the operand was parsed. */
7041 intel_parser.is_mem = -1;
7042 else if (!quiet_warnings)
7043 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
7044 }
7045 }
7046 intel_parser.op_modifier |= was_offset;
64a0c779 7047
a724f0f4 7048 return 1;
64a0c779 7049 }
a724f0f4 7050 return 0;
64a0c779
DN		 7051}
7052
7053/* e10 e11 e10'
7054
7055 e10' [ expr ] e10'
b77a7acd 7056 | Empty */
64a0c779
DN		 7057static int
7058intel_e10 ()
7059{
a724f0f4
JB		 7060 if (!intel_e11 ())
7061 return 0;
64a0c779 7062
a724f0f4 7063 while (cur_token.code == '[')
64a0c779 7064 {
a724f0f4 7065 if (!intel_bracket_expr ())
21d6c4af 7066 return 0;
64a0c779
DN		 7067 }
7068
a724f0f4 7069 return 1;
64a0c779
DN		 7070}
7071
64a0c779 7072/* e11 ( expr )
b77a7acd 7073 | [ expr ]
64a0c779
DN		 7074 | BYTE
7075 | WORD
7076 | DWORD
9306ca4a 7077 | FWORD
64a0c779 7078 | QWORD
9306ca4a
JB		 7079 | TBYTE
7080 | OWORD
7081 | XMMWORD
4a1805b1 7082 | $
64a0c779
DN		 7083 | .
7084 | register
7085 | id
7086 | constant */
7087static int
7088intel_e11 ()
7089{
a724f0f4 7090 switch (cur_token.code)
64a0c779 7091 {
a724f0f4
JB		 7092 /* e11 ( expr ) */
7093 case '(':
64a0c779
DN		 7094 intel_match_token ('(');
7095 strcat (intel_parser.disp, "(");
7096
7097 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7098 {
7099 strcat (intel_parser.disp, ")");
7100 return 1;
7101 }
a724f0f4 7102 return 0;
4a1805b1 7103
a724f0f4
JB		 7104 /* e11 [ expr ] */
7105 case '[':
a724f0f4 7106 return intel_bracket_expr ();
64a0c779 7107
a724f0f4
JB		 7108 /* e11 $
7109 | . */
7110 case '.':
64a0c779
DN		 7111 strcat (intel_parser.disp, cur_token.str);
7112 intel_match_token (cur_token.code);
21d6c4af
DN		 7113
7114 /* Mark as a memory operand only if it's not already known to be an
7115 offset expression. */
a724f0f4 7116 if (!intel_parser.in_offset)
21d6c4af 7117 intel_parser.is_mem = 1;
64a0c779
DN		 7118
7119 return 1;
64a0c779 7120
a724f0f4
JB		 7121 /* e11 register */
7122 case T_REG:
7123 {
7124 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7125
a724f0f4 7126 intel_match_token (T_REG);
64a0c779 7127
a724f0f4
JB		 7128 /* Check for segment change. */
7129 if (cur_token.code == ':')
7130 {
7131 if (!(reg->reg_type & (SReg2 | SReg3)))
7132 {
7133 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
7134 return 0;
7135 }
7136 else if (i.seg[i.mem_operands])
7137 as_warn (_("Extra segment override ignored"));
7138 else
7139 {
7140 if (!intel_parser.in_offset)
7141 intel_parser.is_mem = 1;
7142 switch (reg->reg_num)
7143 {
7144 case 0:
7145 i.seg[i.mem_operands] = &es;
7146 break;
7147 case 1:
7148 i.seg[i.mem_operands] = &cs;
7149 break;
7150 case 2:
7151 i.seg[i.mem_operands] = &ss;
7152 break;
7153 case 3:
7154 i.seg[i.mem_operands] = &ds;
7155 break;
7156 case 4:
7157 i.seg[i.mem_operands] = &fs;
7158 break;
7159 case 5:
7160 i.seg[i.mem_operands] = &gs;
7161 break;
7162 }
7163 }
7164 }
64a0c779 7165
a724f0f4
JB		 7166 /* Not a segment register. Check for register scaling. */
7167 else if (cur_token.code == '*')
7168 {
7169 if (!intel_parser.in_bracket)
7170 {
7171 as_bad (_("Register scaling only allowed in memory operands"));
7172 return 0;
7173 }
64a0c779 7174
a724f0f4
JB		 7175 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7176 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7177 else if (i.index_reg)
7178 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 7179
a724f0f4
JB		 7180 /* What follows must be a valid scale. */
7181 intel_match_token ('*');
7182 i.index_reg = reg;
7183 i.types[this_operand] |= BaseIndex;
64a0c779 7184
a724f0f4
JB		 7185 /* Set the scale after setting the register (otherwise,
7186 i386_scale will complain) */
7187 if (cur_token.code == '+' || cur_token.code == '-')
7188 {
7189 char *str, sign = cur_token.code;
7190 intel_match_token (cur_token.code);
7191 if (cur_token.code != T_CONST)
7192 {
7193 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7194 cur_token.str);
7195 return 0;
7196 }
7197 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7198 strcpy (str + 1, cur_token.str);
7199 *str = sign;
7200 if (!i386_scale (str))
7201 return 0;
7202 free (str);
7203 }
7204 else if (!i386_scale (cur_token.str))
64a0c779 7205 return 0;
a724f0f4
JB		 7206 intel_match_token (cur_token.code);
7207 }
64a0c779 7208
a724f0f4
JB		 7209 /* No scaling. If this is a memory operand, the register is either a
7210 base register (first occurrence) or an index register (second
7211 occurrence). */
7b0441f6 7212 else if (intel_parser.in_bracket)
a724f0f4 7213 {
64a0c779 7214
a724f0f4
JB		 7215 if (!i.base_reg)
7216 i.base_reg = reg;
7217 else if (!i.index_reg)
7218 i.index_reg = reg;
7219 else
7220 {
7221 as_bad (_("Too many register references in memory operand"));
7222 return 0;
7223 }
64a0c779 7224
a724f0f4
JB		 7225 i.types[this_operand] |= BaseIndex;
7226 }
4a1805b1 7227
4d1bb795
JB		 7228 /* It's neither base nor index. */
7229 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 7230 {
7231 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7232 i.op[this_operand].regs = reg;
7233 i.reg_operands++;
7234 }
7235 else
7236 {
7237 as_bad (_("Invalid use of register"));
7238 return 0;
7239 }
64a0c779 7240
a724f0f4
JB		 7241 /* Since registers are not part of the displacement string (except
7242 when we're parsing offset operands), we may need to remove any
7243 preceding '+' from the displacement string. */
7244 if (*intel_parser.disp != '\0'
7245 && !intel_parser.in_offset)
7246 {
7247 char *s = intel_parser.disp;
7248 s += strlen (s) - 1;
7249 if (*s == '+')
7250 *s = '\0';
7251 }
4a1805b1 7252
a724f0f4
JB		 7253 return 1;
7254 }
7255
7256 /* e11 BYTE
7257 | WORD
7258 | DWORD
7259 | FWORD
7260 | QWORD
7261 | TBYTE
7262 | OWORD
7263 | XMMWORD */
7264 case T_BYTE:
7265 case T_WORD:
7266 case T_DWORD:
7267 case T_FWORD:
7268 case T_QWORD:
7269 case T_TBYTE:
7270 case T_XMMWORD:
7271 intel_match_token (cur_token.code);
64a0c779 7272
a724f0f4
JB		 7273 if (cur_token.code == T_PTR)
7274 return 1;
7275
7276 /* It must have been an identifier. */
7277 intel_putback_token ();
7278 cur_token.code = T_ID;
7279 /* FALLTHRU */
7280
7281 /* e11 id
7282 | constant */
7283 case T_ID:
7284 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 7285 {
7286 symbolS *symbolP;
7287
a724f0f4
JB		 7288 /* The identifier represents a memory reference only if it's not
7289 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 7290 symbolP = symbol_find(cur_token.str);
7291 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7292 intel_parser.is_mem = 1;
7293 }
a724f0f4 7294 /* FALLTHRU */
64a0c779 7295
a724f0f4
JB		 7296 case T_CONST:
7297 case '-':
7298 case '+':
7299 {
7300 char *save_str, sign = 0;
64a0c779 7301
a724f0f4
JB		 7302 /* Allow constants that start with `+' or `-'. */
7303 if (cur_token.code == '-' || cur_token.code == '+')
7304 {
7305 sign = cur_token.code;
7306 intel_match_token (cur_token.code);
7307 if (cur_token.code != T_CONST)
7308 {
7309 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7310 cur_token.str);
7311 return 0;
7312 }
7313 }
64a0c779 7314
a724f0f4
JB		 7315 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7316 strcpy (save_str + !!sign, cur_token.str);
7317 if (sign)
7318 *save_str = sign;
64a0c779 7319
a724f0f4
JB		 7320 /* Get the next token to check for register scaling. */
7321 intel_match_token (cur_token.code);
64a0c779 7322
a724f0f4
JB		 7323 /* Check if this constant is a scaling factor for an index register. */
7324 if (cur_token.code == '*')
7325 {
7326 if (intel_match_token ('*') && cur_token.code == T_REG)
7327 {
7328 const reg_entry *reg = cur_token.reg;
7329
7330 if (!intel_parser.in_bracket)
7331 {
7332 as_bad (_("Register scaling only allowed in memory operands"));
7333 return 0;
7334 }
7335
7336 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
7337 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7338 else if (i.index_reg)
7339 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7340
7341 /* The constant is followed by `* reg', so it must be
7342 a valid scale. */
7343 i.index_reg = reg;
7344 i.types[this_operand] |= BaseIndex;
7345
7346 /* Set the scale after setting the register (otherwise,
7347 i386_scale will complain) */
7348 if (!i386_scale (save_str))
64a0c779 7349 return 0;
a724f0f4
JB		 7350 intel_match_token (T_REG);
7351
7352 /* Since registers are not part of the displacement
7353 string, we may need to remove any preceding '+' from
7354 the displacement string. */
7355 if (*intel_parser.disp != '\0')
7356 {
7357 char *s = intel_parser.disp;
7358 s += strlen (s) - 1;
7359 if (*s == '+')
7360 *s = '\0';
7361 }
7362
7363 free (save_str);
7364
7365 return 1;
7366 }
64a0c779 7367
a724f0f4
JB		 7368 /* The constant was not used for register scaling. Since we have
7369 already consumed the token following `*' we now need to put it
7370 back in the stream. */
64a0c779 7371 intel_putback_token ();
a724f0f4 7372 }
64a0c779 7373
a724f0f4
JB		 7374 /* Add the constant to the displacement string. */
7375 strcat (intel_parser.disp, save_str);
7376 free (save_str);
64a0c779 7377
a724f0f4
JB		 7378 return 1;
7379 }
64a0c779
DN		 7380 }
7381
64a0c779
DN		 7382 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7383 return 0;
7384}
7385
64a0c779
DN		 7386/* Match the given token against cur_token. If they match, read the next
7387 token from the operand string. */
7388static int
7389intel_match_token (code)
e5cb08ac 7390 int code;
64a0c779
DN		 7391{
7392 if (cur_token.code == code)
7393 {
7394 intel_get_token ();
7395 return 1;
7396 }
7397 else
7398 {
0477af35 7399 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 7400 return 0;
7401 }
7402}
7403
64a0c779
DN		 7404/* Read a new token from intel_parser.op_string and store it in cur_token. */
7405static void
7406intel_get_token ()
7407{
7408 char *end_op;
7409 const reg_entry *reg;
7410 struct intel_token new_token;
7411
7412 new_token.code = T_NIL;
7413 new_token.reg = NULL;
7414 new_token.str = NULL;
7415
4a1805b1 7416 /* Free the memory allocated to the previous token and move
64a0c779
DN		 7417 cur_token to prev_token. */
7418 if (prev_token.str)
7419 free (prev_token.str);
7420
7421 prev_token = cur_token;
7422
7423 /* Skip whitespace. */
7424 while (is_space_char (*intel_parser.op_string))
7425 intel_parser.op_string++;
7426
7427 /* Return an empty token if we find nothing else on the line. */
7428 if (*intel_parser.op_string == '\0')
7429 {
7430 cur_token = new_token;
7431 return;
7432 }
7433
7434 /* The new token cannot be larger than the remainder of the operand
7435 string. */
a724f0f4 7436 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7437 new_token.str[0] = '\0';
7438
7439 if (strchr ("0123456789", *intel_parser.op_string))
7440 {
7441 char *p = new_token.str;
7442 char *q = intel_parser.op_string;
7443 new_token.code = T_CONST;
7444
7445 /* Allow any kind of identifier char to encompass floating point and
7446 hexadecimal numbers. */
7447 while (is_identifier_char (*q))
7448 *p++ = *q++;
7449 *p = '\0';
7450
7451 /* Recognize special symbol names [0-9][bf]. */
7452 if (strlen (intel_parser.op_string) == 2
4a1805b1 7453 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7454 || intel_parser.op_string[1] == 'f'))
7455 new_token.code = T_ID;
7456 }
7457
4d1bb795 7458 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7459 {
4d1bb795
JB		 7460 size_t len = end_op - intel_parser.op_string;
7461
64a0c779
DN		 7462 new_token.code = T_REG;
7463 new_token.reg = reg;
7464
4d1bb795
JB		 7465 memcpy (new_token.str, intel_parser.op_string, len);
7466 new_token.str[len] = '\0';
64a0c779
DN		 7467 }
7468
7469 else if (is_identifier_char (*intel_parser.op_string))
7470 {
7471 char *p = new_token.str;
7472 char *q = intel_parser.op_string;
7473
7474 /* A '.' or '$' followed by an identifier char is an identifier.
7475 Otherwise, it's operator '.' followed by an expression. */
7476 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7477 {
9306ca4a
JB		 7478 new_token.code = '.';
7479 new_token.str[0] = '.';
64a0c779
DN		 7480 new_token.str[1] = '\0';
7481 }
7482 else
7483 {
7484 while (is_identifier_char (*q) || *q == '@')
7485 *p++ = *q++;
7486 *p = '\0';
7487
9306ca4a
JB		 7488 if (strcasecmp (new_token.str, "NOT") == 0)
7489 new_token.code = '~';
7490
7491 else if (strcasecmp (new_token.str, "MOD") == 0)
7492 new_token.code = '%';
7493
7494 else if (strcasecmp (new_token.str, "AND") == 0)
7495 new_token.code = '&';
7496
7497 else if (strcasecmp (new_token.str, "OR") == 0)
7498 new_token.code = '|';
7499
7500 else if (strcasecmp (new_token.str, "XOR") == 0)
7501 new_token.code = '^';
7502
7503 else if (strcasecmp (new_token.str, "SHL") == 0)
7504 new_token.code = T_SHL;
7505
7506 else if (strcasecmp (new_token.str, "SHR") == 0)
7507 new_token.code = T_SHR;
7508
7509 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7510 new_token.code = T_BYTE;
7511
7512 else if (strcasecmp (new_token.str, "WORD") == 0)
7513 new_token.code = T_WORD;
7514
7515 else if (strcasecmp (new_token.str, "DWORD") == 0)
7516 new_token.code = T_DWORD;
7517
9306ca4a
JB		 7518 else if (strcasecmp (new_token.str, "FWORD") == 0)
7519 new_token.code = T_FWORD;
7520
64a0c779
DN		 7521 else if (strcasecmp (new_token.str, "QWORD") == 0)
7522 new_token.code = T_QWORD;
7523
9306ca4a
JB		 7524 else if (strcasecmp (new_token.str, "TBYTE") == 0
7525 /* XXX remove (gcc still uses it) */
7526 || strcasecmp (new_token.str, "XWORD") == 0)
7527 new_token.code = T_TBYTE;
7528
7529 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7530 || strcasecmp (new_token.str, "OWORD") == 0)
7531 new_token.code = T_XMMWORD;
64a0c779
DN		 7532
7533 else if (strcasecmp (new_token.str, "PTR") == 0)
7534 new_token.code = T_PTR;
7535
7536 else if (strcasecmp (new_token.str, "SHORT") == 0)
7537 new_token.code = T_SHORT;
7538
7539 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7540 {
7541 new_token.code = T_OFFSET;
7542
7543 /* ??? This is not mentioned in the MASM grammar but gcc
7544 makes use of it with -mintel-syntax. OFFSET may be
7545 followed by FLAT: */
7546 if (strncasecmp (q, " FLAT:", 6) == 0)
7547 strcat (new_token.str, " FLAT:");
7548 }
7549
7550 /* ??? This is not mentioned in the MASM grammar. */
7551 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7552 {
7553 new_token.code = T_OFFSET;
7554 if (*q == ':')
7555 strcat (new_token.str, ":");
7556 else
7557 as_bad (_("`:' expected"));
7558 }
64a0c779
DN		 7559
7560 else
7561 new_token.code = T_ID;
7562 }
7563 }
7564
9306ca4a
JB		 7565 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7566 {
7567 new_token.code = *intel_parser.op_string;
7568 new_token.str[0] = *intel_parser.op_string;
7569 new_token.str[1] = '\0';
7570 }
7571
7572 else if (strchr ("<>", *intel_parser.op_string)
7573 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7574 {
7575 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7576 new_token.str[0] = *intel_parser.op_string;
7577 new_token.str[1] = *intel_parser.op_string;
7578 new_token.str[2] = '\0';
7579 }
7580
64a0c779 7581 else
0477af35 7582 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7583
7584 intel_parser.op_string += strlen (new_token.str);
7585 cur_token = new_token;
7586}
7587
64a0c779
DN		 7588/* Put cur_token back into the token stream and make cur_token point to
7589 prev_token. */
7590static void
7591intel_putback_token ()
7592{
a724f0f4
JB		 7593 if (cur_token.code != T_NIL)
7594 {
7595 intel_parser.op_string -= strlen (cur_token.str);
7596 free (cur_token.str);
7597 }
64a0c779 7598 cur_token = prev_token;
4a1805b1 7599
64a0c779
DN		 7600 /* Forget prev_token. */
7601 prev_token.code = T_NIL;
7602 prev_token.reg = NULL;
7603 prev_token.str = NULL;
7604}
54cfded0 7605
a4447b93 7606int
1df69f4f 7607tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 7608{
7609 unsigned int regnum;
7610 unsigned int regnames_count;
089dfecd 7611 static const char *const regnames_32[] =
54cfded0 7612 {
a4447b93
RH		 7613 "eax", "ecx", "edx", "ebx",
7614 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7615 "eip", "eflags", NULL,
7616 "st0", "st1", "st2", "st3",
7617 "st4", "st5", "st6", "st7",
7618 NULL, NULL,
7619 "xmm0", "xmm1", "xmm2", "xmm3",
7620 "xmm4", "xmm5", "xmm6", "xmm7",
7621 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7622 "mm4", "mm5", "mm6", "mm7",
7623 "fcw", "fsw", "mxcsr",
7624 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7625 "tr", "ldtr"
54cfded0 7626 };
089dfecd 7627 static const char *const regnames_64[] =
54cfded0 7628 {
089dfecd
JB		 7629 "rax", "rdx", "rcx", "rbx",
7630 "rsi", "rdi", "rbp", "rsp",
7631 "r8", "r9", "r10", "r11",
54cfded0 7632 "r12", "r13", "r14", "r15",
089dfecd
JB		 7633 "rip",
7634 "xmm0", "xmm1", "xmm2", "xmm3",
7635 "xmm4", "xmm5", "xmm6", "xmm7",
7636 "xmm8", "xmm9", "xmm10", "xmm11",
7637 "xmm12", "xmm13", "xmm14", "xmm15",
7638 "st0", "st1", "st2", "st3",
7639 "st4", "st5", "st6", "st7",
7640 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7641 "mm4", "mm5", "mm6", "mm7",
7642 "rflags",
7643 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7644 "fs.base", "gs.base", NULL, NULL,
7645 "tr", "ldtr",
7646 "mxcsr", "fcw", "fsw"
54cfded0 7647 };
089dfecd 7648 const char *const *regnames;
54cfded0
AM		 7649
7650 if (flag_code == CODE_64BIT)
7651 {
7652 regnames = regnames_64;
0cea6190 7653 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7654 }
7655 else
7656 {
7657 regnames = regnames_32;
0cea6190 7658 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7659 }
7660
7661 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7662 if (regnames[regnum] != NULL
7663 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7664 return regnum;
7665
54cfded0
AM		 7666 return -1;
7667}
7668
7669void
7670tc_x86_frame_initial_instructions (void)
7671{
a4447b93
RH		 7672 static unsigned int sp_regno;
7673
7674 if (!sp_regno)
7675 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7676 ? "rsp" : "esp");
7677
7678 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7679 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7680}
d2b2c203
DJ		 7681
7682int
7683i386_elf_section_type (const char *str, size_t len)
7684{
7685 if (flag_code == CODE_64BIT
7686 && len == sizeof ("unwind") - 1
7687 && strncmp (str, "unwind", 6) == 0)
7688 return SHT_X86_64_UNWIND;
7689
7690 return -1;
7691}
bb41ade5
AM		 7692
7693#ifdef TE_PE
7694void
7695tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7696{
7697 expressionS expr;
7698
7699 expr.X_op = O_secrel;
7700 expr.X_add_symbol = symbol;
7701 expr.X_add_number = 0;
7702 emit_expr (&expr, size);
7703}
7704#endif
3b22753a
L		 7705
7706#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7707/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7708
7709int
7710x86_64_section_letter (int letter, char **ptr_msg)
7711{
7712 if (flag_code == CODE_64BIT)
7713 {
7714 if (letter == 'l')
7715 return SHF_X86_64_LARGE;
7716
7717 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7718 }
3b22753a 7719 else
64e74474 7720 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7721 return -1;
7722}
7723
7724int
7725x86_64_section_word (char *str, size_t len)
7726{
7727 if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
7728 return SHF_X86_64_LARGE;
7729
7730 return -1;
7731}
7732
7733static void
7734handle_large_common (int small ATTRIBUTE_UNUSED)
7735{
7736 if (flag_code != CODE_64BIT)
7737 {
7738 s_comm_internal (0, elf_common_parse);
7739 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7740 }
7741 else
7742 {
7743 static segT lbss_section;
7744 asection *saved_com_section_ptr = elf_com_section_ptr;
7745 asection *saved_bss_section = bss_section;
7746
7747 if (lbss_section == NULL)
7748 {
7749 flagword applicable;
7750 segT seg = now_seg;
7751 subsegT subseg = now_subseg;
7752
7753 /* The .lbss section is for local .largecomm symbols. */
7754 lbss_section = subseg_new (".lbss", 0);
7755 applicable = bfd_applicable_section_flags (stdoutput);
7756 bfd_set_section_flags (stdoutput, lbss_section,
7757 applicable & SEC_ALLOC);
7758 seg_info (lbss_section)->bss = 1;
7759
7760 subseg_set (seg, subseg);
7761 }
7762
7763 elf_com_section_ptr = &_bfd_elf_large_com_section;
7764 bss_section = lbss_section;
7765
7766 s_comm_internal (0, elf_common_parse);
7767
7768 elf_com_section_ptr = saved_com_section_ptr;
7769 bss_section = saved_bss_section;
7770 }
7771}
7772#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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