projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
x86: drop pointless VecESize
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
219d1afa 2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d 68#define LOCK_PREFIX 5
4e9ac44a
L		 69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
6305a203
L		 84/* Intel Syntax. Use a non-ascii letter since since it never appears
85 in instructions. */
86#define LONG_DOUBLE_MNEM_SUFFIX '\1'
87
88#define END_OF_INSN '\0'
89
90/*
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
95 END.
96 */
97typedef struct
98{
d3ce72d0
NC		 99 const insn_template *start;
100 const insn_template *end;
6305a203
L		 101}
102templates;
103
104/* 386 operand encoding bytes: see 386 book for details of this. */
105typedef struct
106{
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
110}
111modrm_byte;
112
113/* x86-64 extension prefix. */
114typedef int rex_byte;
115
6305a203
L		 116/* 386 opcode byte to code indirect addressing. */
117typedef struct
118{
119 unsigned base;
120 unsigned index;
121 unsigned scale;
122}
123sib_byte;
124
6305a203
L		 125/* x86 arch names, types and features */
126typedef struct
127{
128 const char *name; /* arch name */
8a2c8fef 129 unsigned int len; /* arch string length */
6305a203
L		 130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 132 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 133}
134arch_entry;
135
293f5f65
L		 136/* Used to turn off indicated flags. */
137typedef struct
138{
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
142}
143noarch_entry;
144
78f12dd3 145static void update_code_flag (int, int);
e3bb37b5
L		 146static void set_code_flag (int);
147static void set_16bit_gcc_code_flag (int);
148static void set_intel_syntax (int);
1efbbeb4 149static void set_intel_mnemonic (int);
db51cc60 150static void set_allow_index_reg (int);
7bab8ab5 151static void set_check (int);
e3bb37b5 152static void set_cpu_arch (int);
6482c264 153#ifdef TE_PE
e3bb37b5 154static void pe_directive_secrel (int);
6482c264 155#endif
e3bb37b5
L		 156static void signed_cons (int);
157static char *output_invalid (int c);
ee86248c
JB		 158static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
159 const char *);
160static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
161 const char *);
a7619375 162static int i386_att_operand (char *);
e3bb37b5 163static int i386_intel_operand (char *, int);
ee86248c
JB		 164static int i386_intel_simplify (expressionS *);
165static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 166static const reg_entry *parse_register (char *, char **);
167static char *parse_insn (char *, char *);
168static char *parse_operands (char *, const char *);
169static void swap_operands (void);
4d456e3d 170static void swap_2_operands (int, int);
e3bb37b5
L		 171static void optimize_imm (void);
172static void optimize_disp (void);
83b16ac6 173static const insn_template *match_template (char);
e3bb37b5
L		 174static int check_string (void);
175static int process_suffix (void);
176static int check_byte_reg (void);
177static int check_long_reg (void);
178static int check_qword_reg (void);
179static int check_word_reg (void);
180static int finalize_imm (void);
181static int process_operands (void);
182static const seg_entry *build_modrm_byte (void);
183static void output_insn (void);
184static void output_imm (fragS *, offsetT);
185static void output_disp (fragS *, offsetT);
29b0f896 186#ifndef I386COFF
e3bb37b5 187static void s_bss (int);
252b5132 188#endif
17d4e2a2
L		 189#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190static void handle_large_common (int small ATTRIBUTE_UNUSED);
191#endif
252b5132 192
a847613f 193static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 194
43234a1e
L		 195/* This struct describes rounding control and SAE in the instruction. */
196struct RC_Operation
197{
198 enum rc_type
199 {
200 rne = 0,
201 rd,
202 ru,
203 rz,
204 saeonly
205 } type;
206 int operand;
207};
208
209static struct RC_Operation rc_op;
210
211/* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214struct Mask_Operation
215{
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
219 int operand;
220};
221
222static struct Mask_Operation mask_op;
223
224/* The struct describes broadcasting, applied to OPERAND. FACTOR is
225 broadcast factor. */
226struct Broadcast_Operation
227{
228 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
229 int type;
230
231 /* Index of broadcasted operand. */
232 int operand;
233};
234
235static struct Broadcast_Operation broadcast_op;
236
c0f3af97
L		 237/* VEX prefix. */
238typedef struct
239{
43234a1e
L		 240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
c0f3af97
L		 242 unsigned int length;
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
245} vex_prefix;
246
252b5132 247/* 'md_assemble ()' gathers together information and puts it into a
47926f60 248 i386_insn. */
252b5132 249
520dc8e8
AM		 250union i386_op
251 {
252 expressionS *disps;
253 expressionS *imms;
254 const reg_entry *regs;
255 };
256
a65babc9
L		 257enum i386_error
258 {
86e026a4 259 operand_size_mismatch,
a65babc9
L		 260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
264 bad_imm4,
a65babc9
L		 265 unsupported_with_intel_mnemonic,
266 unsupported_syntax,
6c30d220
L		 267 unsupported,
268 invalid_vsib_address,
7bab8ab5 269 invalid_vector_register_set,
43234a1e
L		 270 unsupported_vector_index_register,
271 unsupported_broadcast,
272 broadcast_not_on_src_operand,
273 broadcast_needed,
274 unsupported_masking,
275 mask_not_on_destination,
276 no_default_mask,
277 unsupported_rc_sae,
278 rc_sae_operand_not_last_imm,
279 invalid_register_operand,
a65babc9
L		 280 };
281
252b5132
RH		 282struct _i386_insn
283 {
47926f60 284 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 285 insn_template tm;
252b5132 286
7d5e4556
L		 287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
252b5132
RH		 289 char suffix;
290
47926f60 291 /* OPERANDS gives the number of given operands. */
252b5132
RH		 292 unsigned int operands;
293
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
47926f60 296 operands. */
252b5132
RH		 297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
298
299 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 300 use OP[i] for the corresponding operand. */
40fb9820 301 i386_operand_type types[MAX_OPERANDS];
252b5132 302
520dc8e8
AM		 303 /* Displacement expression, immediate expression, or register for each
304 operand. */
305 union i386_op op[MAX_OPERANDS];
252b5132 306
3e73aa7c
JH		 307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309#define Operand_PCrel 1
310
252b5132 311 /* Relocation type for operand */
f86103b7 312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 313
252b5132
RH		 314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
319
320 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 321 explicit segment overrides are given. */
ce8a8b2f 322 const seg_entry *seg[2];
252b5132 323
8325cc63
JB		 324 /* Copied first memory operand string, for re-checking. */
325 char *memop1_string;
326
252b5132
RH		 327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
331
332 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 333 addressing modes of this insn are encoded. */
252b5132 334 modrm_byte rm;
3e73aa7c 335 rex_byte rex;
43234a1e 336 rex_byte vrex;
252b5132 337 sib_byte sib;
c0f3af97 338 vex_prefix vex;
b6169b20 339
43234a1e
L		 340 /* Masking attributes. */
341 struct Mask_Operation *mask;
342
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
345
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
348
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
351
86fa6981
L		 352 /* Prefer load or store in encoding. */
353 enum
354 {
355 dir_encoding_default = 0,
356 dir_encoding_load,
357 dir_encoding_store
358 } dir_encoding;
891edac4 359
a501d77e
L		 360 /* Prefer 8bit or 32bit displacement in encoding. */
361 enum
362 {
363 disp_encoding_default = 0,
364 disp_encoding_8bit,
365 disp_encoding_32bit
366 } disp_encoding;
f8a5c266 367
6b6b6807
L		 368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding;
370
b6f8c7c4
L		 371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize;
373
86fa6981
L		 374 /* How to encode vector instructions. */
375 enum
376 {
377 vex_encoding_default = 0,
378 vex_encoding_vex2,
379 vex_encoding_vex3,
380 vex_encoding_evex
381 } vec_encoding;
382
d5de92cf
L		 383 /* REP prefix. */
384 const char *rep_prefix;
385
165de32a
L		 386 /* HLE prefix. */
387 const char *hle_prefix;
42164a71 388
7e8b059b
L		 389 /* Have BND prefix. */
390 const char *bnd_prefix;
391
04ef582a
L		 392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix;
394
891edac4 395 /* Error message. */
a65babc9 396 enum i386_error error;
252b5132
RH		 397 };
398
399typedef struct _i386_insn i386_insn;
400
43234a1e
L		 401/* Link RC type with corresponding string, that'll be looked for in
402 asm. */
403struct RC_name
404{
405 enum rc_type type;
406 const char *name;
407 unsigned int len;
408};
409
410static const struct RC_name RC_NamesTable[] =
411{
412 { rne, STRING_COMMA_LEN ("rn-sae") },
413 { rd, STRING_COMMA_LEN ("rd-sae") },
414 { ru, STRING_COMMA_LEN ("ru-sae") },
415 { rz, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly, STRING_COMMA_LEN ("sae") },
417};
418
252b5132
RH		 419/* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 421const char extra_symbol_chars[] = "*%-([{}"
252b5132 422#ifdef LEX_AT
32137342
NC		 423 "@"
424#endif
425#ifdef LEX_QM
426 "?"
252b5132 427#endif
32137342 428 ;
252b5132 429
29b0f896
AM		 430#if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 432 && !defined (TE_GNU) \
29b0f896 433 && !defined (TE_LINUX) \
8d63c93e
RM		 434 && !defined (TE_NACL) \
435 && !defined (TE_NETWARE) \
29b0f896 436 && !defined (TE_FreeBSD) \
5b806d27 437 && !defined (TE_DragonFly) \
29b0f896 438 && !defined (TE_NetBSD)))
252b5132 439/* This array holds the chars that always start a comment. If the
b3b91714
AM		 440 pre-processor is disabled, these aren't very useful. The option
441 --divide will remove '/' from this list. */
442const char *i386_comment_chars = "#/";
443#define SVR4_COMMENT_CHARS 1
252b5132 444#define PREFIX_SEPARATOR '\\'
252b5132 445
b3b91714
AM		 446#else
447const char *i386_comment_chars = "#";
448#define PREFIX_SEPARATOR '/'
449#endif
450
252b5132
RH		 451/* This array holds the chars that only start a comment at the beginning of
452 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 453 .line and .file directives will appear in the pre-processed output.
454 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 455 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 456 #NO_APP at the beginning of its output.
457 Also note that comments started like this one will always work if
252b5132 458 '/' isn't otherwise defined. */
b3b91714 459const char line_comment_chars[] = "#/";
252b5132 460
63a0b638 461const char line_separator_chars[] = ";";
252b5132 462
ce8a8b2f
AM		 463/* Chars that can be used to separate mant from exp in floating point
464 nums. */
252b5132
RH		 465const char EXP_CHARS[] = "eE";
466
ce8a8b2f
AM		 467/* Chars that mean this number is a floating point constant
468 As in 0f12.456
469 or 0d1.2345e12. */
252b5132
RH		 470const char FLT_CHARS[] = "fFdDxX";
471
ce8a8b2f 472/* Tables for lexical analysis. */
252b5132
RH		 473static char mnemonic_chars[256];
474static char register_chars[256];
475static char operand_chars[256];
476static char identifier_chars[256];
477static char digit_chars[256];
478
ce8a8b2f 479/* Lexical macros. */
252b5132
RH		 480#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
481#define is_operand_char(x) (operand_chars[(unsigned char) x])
482#define is_register_char(x) (register_chars[(unsigned char) x])
483#define is_space_char(x) ((x) == ' ')
484#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
485#define is_digit_char(x) (digit_chars[(unsigned char) x])
486
0234cb7c 487/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 488static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
489
490/* md_assemble() always leaves the strings it's passed unaltered. To
491 effect this we maintain a stack of saved characters that we've smashed
492 with '\0's (indicating end of strings for various sub-fields of the
47926f60 493 assembler instruction). */
252b5132 494static char save_stack[32];
ce8a8b2f 495static char *save_stack_p;
252b5132
RH		 496#define END_STRING_AND_SAVE(s) \
497 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
498#define RESTORE_END_STRING(s) \
499 do { *(s) = *--save_stack_p; } while (0)
500
47926f60 501/* The instruction we're assembling. */
252b5132
RH		 502static i386_insn i;
503
504/* Possible templates for current insn. */
505static const templates *current_templates;
506
31b2323c
L		 507/* Per instruction expressionS buffers: max displacements & immediates. */
508static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
509static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 510
47926f60 511/* Current operand we are working on. */
ee86248c 512static int this_operand = -1;
252b5132 513
3e73aa7c
JH		 514/* We support four different modes. FLAG_CODE variable is used to distinguish
515 these. */
516
517enum flag_code {
518 CODE_32BIT,
519 CODE_16BIT,
520 CODE_64BIT };
521
522static enum flag_code flag_code;
4fa24527 523static unsigned int object_64bit;
862be3fb 524static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 525static int use_rela_relocations = 0;
526
7af8ed2d
NC		 527#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
528 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
529 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
530
351f65ca
L		 531/* The ELF ABI to use. */
532enum x86_elf_abi
533{
534 I386_ABI,
7f56bc95
L		 535 X86_64_ABI,
536 X86_64_X32_ABI
351f65ca
L		 537};
538
539static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 540#endif
351f65ca 541
167ad85b
TG		 542#if defined (TE_PE) || defined (TE_PEP)
543/* Use big object file format. */
544static int use_big_obj = 0;
545#endif
546
8dcea932
L		 547#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
548/* 1 if generating code for a shared library. */
549static int shared = 0;
550#endif
551
47926f60
KH		 552/* 1 for intel syntax,
553 0 if att syntax. */
554static int intel_syntax = 0;
252b5132 555
e89c5eaa
L		 556/* 1 for Intel64 ISA,
557 0 if AMD64 ISA. */
558static int intel64;
559
1efbbeb4
L		 560/* 1 for intel mnemonic,
561 0 if att mnemonic. */
562static int intel_mnemonic = !SYSV386_COMPAT;
563
a60de03c
JB		 564/* 1 if pseudo registers are permitted. */
565static int allow_pseudo_reg = 0;
566
47926f60
KH		 567/* 1 if register prefix % not required. */
568static int allow_naked_reg = 0;
252b5132 569
33eaf5de 570/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 571 instructions supporting it, even if this prefix wasn't specified
572 explicitly. */
573static int add_bnd_prefix = 0;
574
ba104c83 575/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 576static int allow_index_reg = 0;
577
d022bddd
IT		 578/* 1 if the assembler should ignore LOCK prefix, even if it was
579 specified explicitly. */
580static int omit_lock_prefix = 0;
581
e4e00185
AS		 582/* 1 if the assembler should encode lfence, mfence, and sfence as
583 "lock addl $0, (%{re}sp)". */
584static int avoid_fence = 0;
585
0cb4071e
L		 586/* 1 if the assembler should generate relax relocations. */
587
588static int generate_relax_relocations
589 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
590
7bab8ab5 591static enum check_kind
daf50ae7 592 {
7bab8ab5
JB		 593 check_none = 0,
594 check_warning,
595 check_error
daf50ae7 596 }
7bab8ab5 597sse_check, operand_check = check_warning;
daf50ae7 598
b6f8c7c4
L		 599/* Optimization:
600 1. Clear the REX_W bit with register operand if possible.
601 2. Above plus use 128bit vector instruction to clear the full vector
602 register.
603 */
604static int optimize = 0;
605
606/* Optimization:
607 1. Clear the REX_W bit with register operand if possible.
608 2. Above plus use 128bit vector instruction to clear the full vector
609 register.
610 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
611 "testb $imm7,%r8".
612 */
613static int optimize_for_space = 0;
614
2ca3ace5
L		 615/* Register prefix used for error message. */
616static const char *register_prefix = "%";
617
47926f60
KH		 618/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
619 leave, push, and pop instructions so that gcc has the same stack
620 frame as in 32 bit mode. */
621static char stackop_size = '\0';
eecb386c 622
12b55ccc
L		 623/* Non-zero to optimize code alignment. */
624int optimize_align_code = 1;
625
47926f60
KH		 626/* Non-zero to quieten some warnings. */
627static int quiet_warnings = 0;
a38cf1db 628
47926f60
KH		 629/* CPU name. */
630static const char *cpu_arch_name = NULL;
6305a203 631static char *cpu_sub_arch_name = NULL;
a38cf1db 632
47926f60 633/* CPU feature flags. */
40fb9820
L		 634static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
635
ccc9c027
L		 636/* If we have selected a cpu we are generating instructions for. */
637static int cpu_arch_tune_set = 0;
638
9103f4f4 639/* Cpu we are generating instructions for. */
fbf3f584 640enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 641
642/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 643static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 644
ccc9c027 645/* CPU instruction set architecture used. */
fbf3f584 646enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 647
9103f4f4 648/* CPU feature flags of instruction set architecture used. */
fbf3f584 649i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 650
fddf5b5b
AM		 651/* If set, conditional jumps are not automatically promoted to handle
652 larger than a byte offset. */
653static unsigned int no_cond_jump_promotion = 0;
654
c0f3af97
L		 655/* Encode SSE instructions with VEX prefix. */
656static unsigned int sse2avx;
657
539f890d
L		 658/* Encode scalar AVX instructions with specific vector length. */
659static enum
660 {
661 vex128 = 0,
662 vex256
663 } avxscalar;
664
43234a1e
L		 665/* Encode scalar EVEX LIG instructions with specific vector length. */
666static enum
667 {
668 evexl128 = 0,
669 evexl256,
670 evexl512
671 } evexlig;
672
673/* Encode EVEX WIG instructions with specific evex.w. */
674static enum
675 {
676 evexw0 = 0,
677 evexw1
678 } evexwig;
679
d3d3c6db
IT		 680/* Value to encode in EVEX RC bits, for SAE-only instructions. */
681static enum rc_type evexrcig = rne;
682
29b0f896 683/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 684static symbolS *GOT_symbol;
29b0f896 685
a4447b93
RH		 686/* The dwarf2 return column, adjusted for 32 or 64 bit. */
687unsigned int x86_dwarf2_return_column;
688
689/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
690int x86_cie_data_alignment;
691
252b5132 692/* Interface to relax_segment.
fddf5b5b
AM		 693 There are 3 major relax states for 386 jump insns because the
694 different types of jumps add different sizes to frags when we're
695 figuring out what sort of jump to choose to reach a given label. */
252b5132 696
47926f60 697/* Types. */
93c2a809
AM		 698#define UNCOND_JUMP 0
699#define COND_JUMP 1
700#define COND_JUMP86 2
fddf5b5b 701
47926f60 702/* Sizes. */
252b5132
RH		 703#define CODE16 1
704#define SMALL 0
29b0f896 705#define SMALL16 (SMALL | CODE16)
252b5132 706#define BIG 2
29b0f896 707#define BIG16 (BIG | CODE16)
252b5132
RH		 708
709#ifndef INLINE
710#ifdef __GNUC__
711#define INLINE __inline__
712#else
713#define INLINE
714#endif
715#endif
716
fddf5b5b
AM		 717#define ENCODE_RELAX_STATE(type, size) \
718 ((relax_substateT) (((type) << 2) | (size)))
719#define TYPE_FROM_RELAX_STATE(s) \
720 ((s) >> 2)
721#define DISP_SIZE_FROM_RELAX_STATE(s) \
722 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 723
724/* This table is used by relax_frag to promote short jumps to long
725 ones where necessary. SMALL (short) jumps may be promoted to BIG
726 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
727 don't allow a short jump in a 32 bit code segment to be promoted to
728 a 16 bit offset jump because it's slower (requires data size
729 prefix), and doesn't work, unless the destination is in the bottom
730 64k of the code segment (The top 16 bits of eip are zeroed). */
731
732const relax_typeS md_relax_table[] =
733{
24eab124
AM		 734 /* The fields are:
735 1) most positive reach of this state,
736 2) most negative reach of this state,
93c2a809 737 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 738 4) which index into the table to try if we can't fit into this one. */
252b5132 739
fddf5b5b 740 /* UNCOND_JUMP states. */
93c2a809
AM		 741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
742 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
743 /* dword jmp adds 4 bytes to frag:
744 0 extra opcode bytes, 4 displacement bytes. */
252b5132 745 {0, 0, 4, 0},
93c2a809
AM		 746 /* word jmp adds 2 byte2 to frag:
747 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 748 {0, 0, 2, 0},
749
93c2a809
AM		 750 /* COND_JUMP states. */
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
752 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
753 /* dword conditionals adds 5 bytes to frag:
754 1 extra opcode byte, 4 displacement bytes. */
755 {0, 0, 5, 0},
fddf5b5b 756 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 757 1 extra opcode byte, 2 displacement bytes. */
758 {0, 0, 3, 0},
759
760 /* COND_JUMP86 states. */
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
762 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
763 /* dword conditionals adds 5 bytes to frag:
764 1 extra opcode byte, 4 displacement bytes. */
765 {0, 0, 5, 0},
766 /* word conditionals add 4 bytes to frag:
767 1 displacement byte and a 3 byte long branch insn. */
768 {0, 0, 4, 0}
252b5132
RH		 769};
770
9103f4f4
L		 771static const arch_entry cpu_arch[] =
772{
89507696
JB		 773 /* Do not replace the first two entries - i386_target_format()
774 relies on them being there in this order. */
8a2c8fef 775 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 776 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 777 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 778 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 779 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 780 CPU_NONE_FLAGS, 0 },
8a2c8fef 781 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 782 CPU_I186_FLAGS, 0 },
8a2c8fef 783 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 784 CPU_I286_FLAGS, 0 },
8a2c8fef 785 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 786 CPU_I386_FLAGS, 0 },
8a2c8fef 787 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 788 CPU_I486_FLAGS, 0 },
8a2c8fef 789 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 790 CPU_I586_FLAGS, 0 },
8a2c8fef 791 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 792 CPU_I686_FLAGS, 0 },
8a2c8fef 793 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 794 CPU_I586_FLAGS, 0 },
8a2c8fef 795 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 796 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 797 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 798 CPU_P2_FLAGS, 0 },
8a2c8fef 799 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 800 CPU_P3_FLAGS, 0 },
8a2c8fef 801 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 802 CPU_P4_FLAGS, 0 },
8a2c8fef 803 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 804 CPU_CORE_FLAGS, 0 },
8a2c8fef 805 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 806 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 807 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 808 CPU_CORE_FLAGS, 1 },
8a2c8fef 809 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 810 CPU_CORE_FLAGS, 0 },
8a2c8fef 811 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 812 CPU_CORE2_FLAGS, 1 },
8a2c8fef 813 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 814 CPU_CORE2_FLAGS, 0 },
8a2c8fef 815 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 816 CPU_COREI7_FLAGS, 0 },
8a2c8fef 817 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 818 CPU_L1OM_FLAGS, 0 },
7a9068fe 819 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 820 CPU_K1OM_FLAGS, 0 },
81486035 821 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 822 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 823 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 824 CPU_K6_FLAGS, 0 },
8a2c8fef 825 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 826 CPU_K6_2_FLAGS, 0 },
8a2c8fef 827 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 828 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 829 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 830 CPU_K8_FLAGS, 1 },
8a2c8fef 831 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 832 CPU_K8_FLAGS, 0 },
8a2c8fef 833 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 834 CPU_K8_FLAGS, 0 },
8a2c8fef 835 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 836 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 837 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 838 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 839 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 840 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 841 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 842 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 843 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 844 CPU_BDVER4_FLAGS, 0 },
029f3522 845 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 846 CPU_ZNVER1_FLAGS, 0 },
7b458c12 847 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 848 CPU_BTVER1_FLAGS, 0 },
7b458c12 849 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 850 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 852 CPU_8087_FLAGS, 0 },
8a2c8fef 853 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 854 CPU_287_FLAGS, 0 },
8a2c8fef 855 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 856 CPU_387_FLAGS, 0 },
1848e567
L		 857 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
858 CPU_687_FLAGS, 0 },
8a2c8fef 859 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 860 CPU_MMX_FLAGS, 0 },
8a2c8fef 861 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 862 CPU_SSE_FLAGS, 0 },
8a2c8fef 863 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 864 CPU_SSE2_FLAGS, 0 },
8a2c8fef 865 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 866 CPU_SSE3_FLAGS, 0 },
8a2c8fef 867 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 868 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 869 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 870 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 871 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 872 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 873 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 874 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 875 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 876 CPU_AVX_FLAGS, 0 },
6c30d220 877 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 878 CPU_AVX2_FLAGS, 0 },
43234a1e 879 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 880 CPU_AVX512F_FLAGS, 0 },
43234a1e 881 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 882 CPU_AVX512CD_FLAGS, 0 },
43234a1e 883 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 884 CPU_AVX512ER_FLAGS, 0 },
43234a1e 885 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 886 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 887 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 888 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 889 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 890 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 891 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 892 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 893 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 894 CPU_VMX_FLAGS, 0 },
8729a6f6 895 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 896 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 897 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 898 CPU_SMX_FLAGS, 0 },
8a2c8fef 899 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 900 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 901 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 902 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 903 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 904 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 905 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 906 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 907 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 908 CPU_AES_FLAGS, 0 },
8a2c8fef 909 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 910 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 911 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 912 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 913 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 914 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 915 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 916 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 917 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 918 CPU_F16C_FLAGS, 0 },
6c30d220 919 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 920 CPU_BMI2_FLAGS, 0 },
8a2c8fef 921 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 922 CPU_FMA_FLAGS, 0 },
8a2c8fef 923 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 924 CPU_FMA4_FLAGS, 0 },
8a2c8fef 925 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 926 CPU_XOP_FLAGS, 0 },
8a2c8fef 927 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 928 CPU_LWP_FLAGS, 0 },
8a2c8fef 929 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 930 CPU_MOVBE_FLAGS, 0 },
60aa667e 931 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 932 CPU_CX16_FLAGS, 0 },
8a2c8fef 933 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 934 CPU_EPT_FLAGS, 0 },
6c30d220 935 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 936 CPU_LZCNT_FLAGS, 0 },
42164a71 937 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 938 CPU_HLE_FLAGS, 0 },
42164a71 939 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 940 CPU_RTM_FLAGS, 0 },
6c30d220 941 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 942 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 943 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 944 CPU_CLFLUSH_FLAGS, 0 },
22109423 945 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 946 CPU_NOP_FLAGS, 0 },
8a2c8fef 947 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 948 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 949 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 950 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 951 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 952 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 953 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 954 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 955 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 956 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 957 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 958 CPU_SVME_FLAGS, 1 },
8a2c8fef 959 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 960 CPU_SVME_FLAGS, 0 },
8a2c8fef 961 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 962 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 963 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 964 CPU_ABM_FLAGS, 0 },
87973e9f 965 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 966 CPU_BMI_FLAGS, 0 },
2a2a0f38 967 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 968 CPU_TBM_FLAGS, 0 },
e2e1fcde 969 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 970 CPU_ADX_FLAGS, 0 },
e2e1fcde 971 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 972 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 973 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 974 CPU_PRFCHW_FLAGS, 0 },
5c111e37 975 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 976 CPU_SMAP_FLAGS, 0 },
7e8b059b 977 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 978 CPU_MPX_FLAGS, 0 },
a0046408 979 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 980 CPU_SHA_FLAGS, 0 },
963f3586 981 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 982 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 983 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 984 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 985 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 986 CPU_SE1_FLAGS, 0 },
c5e7287a 987 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 988 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 989 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 990 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 991 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 992 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 993 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
994 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 995 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
996 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 997 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
998 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
53467f57
IT		 999 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1000 CPU_AVX512_VBMI2_FLAGS, 0 },
8cfcb765
IT		 1001 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1002 CPU_AVX512_VNNI_FLAGS, 0 },
ee6872be
IT		 1003 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1004 CPU_AVX512_BITALG_FLAGS, 0 },
029f3522 1005 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 1006 CPU_CLZERO_FLAGS, 0 },
9916071f 1007 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 1008 CPU_MWAITX_FLAGS, 0 },
8eab4136 1009 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 1010 CPU_OSPKE_FLAGS, 0 },
8bc52696 1011 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 1012 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 1013 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1014 CPU_PTWRITE_FLAGS, 0 },
d777820b
IT		 1015 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1016 CPU_IBT_FLAGS, 0 },
1017 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1018 CPU_SHSTK_FLAGS, 0 },
48521003
IT		 1019 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1020 CPU_GFNI_FLAGS, 0 },
8dcf1fad
IT		 1021 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1022 CPU_VAES_FLAGS, 0 },
ff1982d5
IT		 1023 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1024 CPU_VPCLMULQDQ_FLAGS, 0 },
3233d7d0
IT		 1025 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1026 CPU_WBNOINVD_FLAGS, 0 },
be3a8dca
IT		 1027 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1028 CPU_PCONFIG_FLAGS, 0 },
293f5f65
L		 1029};
1030
1031static const noarch_entry cpu_noarch[] =
1032{
1033 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 1034 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1035 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1036 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 1037 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1038 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1039 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1040 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1041 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1042 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1043 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1044 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1045 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1046 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1047 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1048 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1049 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1050 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1051 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1052 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1053 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1054 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1056 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1057 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1058 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
53467f57 1059 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
8cfcb765 1060 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
ee6872be 1061 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
d777820b
IT		 1062 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1063 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
e413e4e9
AM		 1064};
1065
704209c0 1066#ifdef I386COFF
a6c24e68
NC		 1067/* Like s_lcomm_internal in gas/read.c but the alignment string
1068 is allowed to be optional. */
1069
1070static symbolS *
1071pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1072{
1073 addressT align = 0;
1074
1075 SKIP_WHITESPACE ();
1076
7ab9ffdd 1077 if (needs_align
a6c24e68
NC		 1078 && *input_line_pointer == ',')
1079 {
1080 align = parse_align (needs_align - 1);
7ab9ffdd 1081
a6c24e68
NC		 1082 if (align == (addressT) -1)
1083 return NULL;
1084 }
1085 else
1086 {
1087 if (size >= 8)
1088 align = 3;
1089 else if (size >= 4)
1090 align = 2;
1091 else if (size >= 2)
1092 align = 1;
1093 else
1094 align = 0;
1095 }
1096
1097 bss_alloc (symbolP, size, align);
1098 return symbolP;
1099}
1100
704209c0 1101static void
a6c24e68
NC		 1102pe_lcomm (int needs_align)
1103{
1104 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1105}
704209c0 1106#endif
a6c24e68 1107
29b0f896
AM		 1108const pseudo_typeS md_pseudo_table[] =
1109{
1110#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1111 {"align", s_align_bytes, 0},
1112#else
1113 {"align", s_align_ptwo, 0},
1114#endif
1115 {"arch", set_cpu_arch, 0},
1116#ifndef I386COFF
1117 {"bss", s_bss, 0},
a6c24e68
NC		 1118#else
1119 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1120#endif
1121 {"ffloat", float_cons, 'f'},
1122 {"dfloat", float_cons, 'd'},
1123 {"tfloat", float_cons, 'x'},
1124 {"value", cons, 2},
d182319b 1125 {"slong", signed_cons, 4},
29b0f896
AM		 1126 {"noopt", s_ignore, 0},
1127 {"optim", s_ignore, 0},
1128 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1129 {"code16", set_code_flag, CODE_16BIT},
1130 {"code32", set_code_flag, CODE_32BIT},
da5f19a2 1131#ifdef BFD64
29b0f896 1132 {"code64", set_code_flag, CODE_64BIT},
da5f19a2 1133#endif
29b0f896
AM		 1134 {"intel_syntax", set_intel_syntax, 1},
1135 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1136 {"intel_mnemonic", set_intel_mnemonic, 1},
1137 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1138 {"allow_index_reg", set_allow_index_reg, 1},
1139 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1140 {"sse_check", set_check, 0},
1141 {"operand_check", set_check, 1},
3b22753a
L		 1142#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1143 {"largecomm", handle_large_common, 0},
07a53e5c 1144#else
68d20676 1145 {"file", dwarf2_directive_file, 0},
07a53e5c
RH		 1146 {"loc", dwarf2_directive_loc, 0},
1147 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1148#endif
6482c264
NC		 1149#ifdef TE_PE
1150 {"secrel32", pe_directive_secrel, 0},
1151#endif
29b0f896
AM		 1152 {0, 0, 0}
1153};
1154
1155/* For interface with expression (). */
1156extern char *input_line_pointer;
1157
1158/* Hash table for instruction mnemonic lookup. */
1159static struct hash_control *op_hash;
1160
1161/* Hash table for register lookup. */
1162static struct hash_control *reg_hash;
1163\f
ce8a8b2f
AM		 1164 /* Various efficient no-op patterns for aligning code labels.
1165 Note: Don't try to assemble the instructions in the comments.
1166 0L and 0w are not legal. */
62a02d25
L		 1167static const unsigned char f32_1[] =
1168 {0x90}; /* nop */
1169static const unsigned char f32_2[] =
1170 {0x66,0x90}; /* xchg %ax,%ax */
1171static const unsigned char f32_3[] =
1172 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1173static const unsigned char f32_4[] =
1174 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
62a02d25
L		 1175static const unsigned char f32_6[] =
1176 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1177static const unsigned char f32_7[] =
1178 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
62a02d25 1179static const unsigned char f16_3[] =
3ae729d5 1180 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
62a02d25 1181static const unsigned char f16_4[] =
3ae729d5
L		 1182 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1183static const unsigned char jump_disp8[] =
1184 {0xeb}; /* jmp disp8 */
1185static const unsigned char jump32_disp32[] =
1186 {0xe9}; /* jmp disp32 */
1187static const unsigned char jump16_disp32[] =
1188 {0x66,0xe9}; /* jmp disp32 */
62a02d25
L		 1189/* 32-bit NOPs patterns. */
1190static const unsigned char *const f32_patt[] = {
3ae729d5 1191 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
62a02d25
L		 1192};
1193/* 16-bit NOPs patterns. */
1194static const unsigned char *const f16_patt[] = {
3ae729d5 1195 f32_1, f32_2, f16_3, f16_4
62a02d25
L		 1196};
1197/* nopl (%[re]ax) */
1198static const unsigned char alt_3[] =
1199 {0x0f,0x1f,0x00};
1200/* nopl 0(%[re]ax) */
1201static const unsigned char alt_4[] =
1202 {0x0f,0x1f,0x40,0x00};
1203/* nopl 0(%[re]ax,%[re]ax,1) */
1204static const unsigned char alt_5[] =
1205 {0x0f,0x1f,0x44,0x00,0x00};
1206/* nopw 0(%[re]ax,%[re]ax,1) */
1207static const unsigned char alt_6[] =
1208 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1209/* nopl 0L(%[re]ax) */
1210static const unsigned char alt_7[] =
1211 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1212/* nopl 0L(%[re]ax,%[re]ax,1) */
1213static const unsigned char alt_8[] =
1214 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1215/* nopw 0L(%[re]ax,%[re]ax,1) */
1216static const unsigned char alt_9[] =
1217 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1218/* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1219static const unsigned char alt_10[] =
1220 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
3ae729d5
L		 1221/* data16 nopw %cs:0L(%eax,%eax,1) */
1222static const unsigned char alt_11[] =
1223 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
62a02d25
L		 1224/* 32-bit and 64-bit NOPs patterns. */
1225static const unsigned char *const alt_patt[] = {
1226 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
3ae729d5 1227 alt_9, alt_10, alt_11
62a02d25
L		 1228};
1229
1230/* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1231 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1232
1233static void
1234i386_output_nops (char *where, const unsigned char *const *patt,
1235 int count, int max_single_nop_size)
1236
1237{
3ae729d5
L		 1238 /* Place the longer NOP first. */
1239 int last;
1240 int offset;
1241 const unsigned char *nops = patt[max_single_nop_size - 1];
1242
1243 /* Use the smaller one if the requsted one isn't available. */
1244 if (nops == NULL)
62a02d25 1245 {
3ae729d5
L		 1246 max_single_nop_size--;
1247 nops = patt[max_single_nop_size - 1];
62a02d25
L		 1248 }
1249
3ae729d5
L		 1250 last = count % max_single_nop_size;
1251
1252 count -= last;
1253 for (offset = 0; offset < count; offset += max_single_nop_size)
1254 memcpy (where + offset, nops, max_single_nop_size);
1255
1256 if (last)
1257 {
1258 nops = patt[last - 1];
1259 if (nops == NULL)
1260 {
1261 /* Use the smaller one plus one-byte NOP if the needed one
1262 isn't available. */
1263 last--;
1264 nops = patt[last - 1];
1265 memcpy (where + offset, nops, last);
1266 where[offset + last] = *patt[0];
1267 }
1268 else
1269 memcpy (where + offset, nops, last);
1270 }
62a02d25
L		 1271}
1272
3ae729d5
L		 1273static INLINE int
1274fits_in_imm7 (offsetT num)
1275{
1276 return (num & 0x7f) == num;
1277}
1278
1279static INLINE int
1280fits_in_imm31 (offsetT num)
1281{
1282 return (num & 0x7fffffff) == num;
1283}
62a02d25
L		 1284
1285/* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1286 single NOP instruction LIMIT. */
1287
1288void
3ae729d5 1289i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
62a02d25 1290{
3ae729d5 1291 const unsigned char *const *patt = NULL;
62a02d25 1292 int max_single_nop_size;
3ae729d5
L		 1293 /* Maximum number of NOPs before switching to jump over NOPs. */
1294 int max_number_of_nops;
62a02d25 1295
3ae729d5 1296 switch (fragP->fr_type)
62a02d25 1297 {
3ae729d5
L		 1298 case rs_fill_nop:
1299 case rs_align_code:
1300 break;
1301 default:
62a02d25
L		 1302 return;
1303 }
1304
ccc9c027
L		 1305 /* We need to decide which NOP sequence to use for 32bit and
1306 64bit. When -mtune= is used:
4eed87de 1307
76bc74dc
L		 1308 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1309 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1310 2. For the rest, alt_patt will be used.
1311
1312 When -mtune= isn't used, alt_patt will be used if
22109423 1313 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1314 be used.
ccc9c027
L		 1315
1316 When -march= or .arch is used, we can't use anything beyond
1317 cpu_arch_isa_flags. */
1318
1319 if (flag_code == CODE_16BIT)
1320 {
3ae729d5
L		 1321 patt = f16_patt;
1322 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1323 /* Limit number of NOPs to 2 in 16-bit mode. */
1324 max_number_of_nops = 2;
252b5132 1325 }
33fef721 1326 else
ccc9c027 1327 {
fbf3f584 1328 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1329 {
1330 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1331 switch (cpu_arch_tune)
1332 {
1333 case PROCESSOR_UNKNOWN:
1334 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1335 optimize with nops. */
1336 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1337 patt = alt_patt;
ccc9c027
L		 1338 else
1339 patt = f32_patt;
1340 break;
ccc9c027
L		 1341 case PROCESSOR_PENTIUM4:
1342 case PROCESSOR_NOCONA:
ef05d495 1343 case PROCESSOR_CORE:
76bc74dc 1344 case PROCESSOR_CORE2:
bd5295b2 1345 case PROCESSOR_COREI7:
3632d14b 1346 case PROCESSOR_L1OM:
7a9068fe 1347 case PROCESSOR_K1OM:
76bc74dc 1348 case PROCESSOR_GENERIC64:
ccc9c027
L		 1349 case PROCESSOR_K6:
1350 case PROCESSOR_ATHLON:
1351 case PROCESSOR_K8:
4eed87de 1352 case PROCESSOR_AMDFAM10:
8aedb9fe 1353 case PROCESSOR_BD:
029f3522 1354 case PROCESSOR_ZNVER:
7b458c12 1355 case PROCESSOR_BT:
80b8656c 1356 patt = alt_patt;
ccc9c027 1357 break;
76bc74dc 1358 case PROCESSOR_I386:
ccc9c027
L		 1359 case PROCESSOR_I486:
1360 case PROCESSOR_PENTIUM:
2dde1948 1361 case PROCESSOR_PENTIUMPRO:
81486035 1362 case PROCESSOR_IAMCU:
ccc9c027
L		 1363 case PROCESSOR_GENERIC32:
1364 patt = f32_patt;
1365 break;
4eed87de 1366 }
ccc9c027
L		 1367 }
1368 else
1369 {
fbf3f584 1370 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1371 {
1372 case PROCESSOR_UNKNOWN:
e6a14101 1373 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1374 PROCESSOR_UNKNOWN. */
1375 abort ();
1376 break;
1377
76bc74dc 1378 case PROCESSOR_I386:
ccc9c027
L		 1379 case PROCESSOR_I486:
1380 case PROCESSOR_PENTIUM:
81486035 1381 case PROCESSOR_IAMCU:
ccc9c027
L		 1382 case PROCESSOR_K6:
1383 case PROCESSOR_ATHLON:
1384 case PROCESSOR_K8:
4eed87de 1385 case PROCESSOR_AMDFAM10:
8aedb9fe 1386 case PROCESSOR_BD:
029f3522 1387 case PROCESSOR_ZNVER:
7b458c12 1388 case PROCESSOR_BT:
ccc9c027
L		 1389 case PROCESSOR_GENERIC32:
1390 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1391 with nops. */
1392 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1393 patt = alt_patt;
ccc9c027
L		 1394 else
1395 patt = f32_patt;
1396 break;
76bc74dc
L		 1397 case PROCESSOR_PENTIUMPRO:
1398 case PROCESSOR_PENTIUM4:
1399 case PROCESSOR_NOCONA:
1400 case PROCESSOR_CORE:
ef05d495 1401 case PROCESSOR_CORE2:
bd5295b2 1402 case PROCESSOR_COREI7:
3632d14b 1403 case PROCESSOR_L1OM:
7a9068fe 1404 case PROCESSOR_K1OM:
22109423 1405 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1406 patt = alt_patt;
ccc9c027
L		 1407 else
1408 patt = f32_patt;
1409 break;
1410 case PROCESSOR_GENERIC64:
80b8656c 1411 patt = alt_patt;
ccc9c027 1412 break;
4eed87de 1413 }
ccc9c027
L		 1414 }
1415
76bc74dc
L		 1416 if (patt == f32_patt)
1417 {
3ae729d5
L		 1418 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1419 /* Limit number of NOPs to 2 for older processors. */
1420 max_number_of_nops = 2;
76bc74dc
L		 1421 }
1422 else
1423 {
3ae729d5
L		 1424 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1425 /* Limit number of NOPs to 7 for newer processors. */
1426 max_number_of_nops = 7;
1427 }
1428 }
1429
1430 if (limit == 0)
1431 limit = max_single_nop_size;
1432
1433 if (fragP->fr_type == rs_fill_nop)
1434 {
1435 /* Output NOPs for .nop directive. */
1436 if (limit > max_single_nop_size)
1437 {
1438 as_bad_where (fragP->fr_file, fragP->fr_line,
1439 _("invalid single nop size: %d "
1440 "(expect within [0, %d])"),
1441 limit, max_single_nop_size);
1442 return;
1443 }
1444 }
1445 else
1446 fragP->fr_var = count;
1447
1448 if ((count / max_single_nop_size) > max_number_of_nops)
1449 {
1450 /* Generate jump over NOPs. */
1451 offsetT disp = count - 2;
1452 if (fits_in_imm7 (disp))
1453 {
1454 /* Use "jmp disp8" if possible. */
1455 count = disp;
1456 where[0] = jump_disp8[0];
1457 where[1] = count;
1458 where += 2;
1459 }
1460 else
1461 {
1462 unsigned int size_of_jump;
1463
1464 if (flag_code == CODE_16BIT)
1465 {
1466 where[0] = jump16_disp32[0];
1467 where[1] = jump16_disp32[1];
1468 size_of_jump = 2;
1469 }
1470 else
1471 {
1472 where[0] = jump32_disp32[0];
1473 size_of_jump = 1;
1474 }
1475
1476 count -= size_of_jump + 4;
1477 if (!fits_in_imm31 (count))
1478 {
1479 as_bad_where (fragP->fr_file, fragP->fr_line,
1480 _("jump over nop padding out of range"));
1481 return;
1482 }
1483
1484 md_number_to_chars (where + size_of_jump, count, 4);
1485 where += size_of_jump + 4;
76bc74dc 1486 }
ccc9c027 1487 }
3ae729d5
L		 1488
1489 /* Generate multiple NOPs. */
1490 i386_output_nops (where, patt, count, limit);
252b5132
RH		 1491}
1492
c6fb90c8 1493static INLINE int
0dfbf9d7 1494operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1495{
0dfbf9d7 1496 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1497 {
1498 case 3:
0dfbf9d7 1499 if (x->array[2])
c6fb90c8 1500 return 0;
1a0670f3 1501 /* Fall through. */
c6fb90c8 1502 case 2:
0dfbf9d7 1503 if (x->array[1])
c6fb90c8 1504 return 0;
1a0670f3 1505 /* Fall through. */
c6fb90c8 1506 case 1:
0dfbf9d7 1507 return !x->array[0];
c6fb90c8
L		 1508 default:
1509 abort ();
1510 }
40fb9820
L		 1511}
1512
c6fb90c8 1513static INLINE void
0dfbf9d7 1514operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1515{
0dfbf9d7 1516 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1517 {
1518 case 3:
0dfbf9d7 1519 x->array[2] = v;
1a0670f3 1520 /* Fall through. */
c6fb90c8 1521 case 2:
0dfbf9d7 1522 x->array[1] = v;
1a0670f3 1523 /* Fall through. */
c6fb90c8 1524 case 1:
0dfbf9d7 1525 x->array[0] = v;
1a0670f3 1526 /* Fall through. */
c6fb90c8
L		 1527 break;
1528 default:
1529 abort ();
1530 }
1531}
40fb9820 1532
c6fb90c8 1533static INLINE int
0dfbf9d7
L		 1534operand_type_equal (const union i386_operand_type *x,
1535 const union i386_operand_type *y)
c6fb90c8 1536{
0dfbf9d7 1537 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1538 {
1539 case 3:
0dfbf9d7 1540 if (x->array[2] != y->array[2])
c6fb90c8 1541 return 0;
1a0670f3 1542 /* Fall through. */
c6fb90c8 1543 case 2:
0dfbf9d7 1544 if (x->array[1] != y->array[1])
c6fb90c8 1545 return 0;
1a0670f3 1546 /* Fall through. */
c6fb90c8 1547 case 1:
0dfbf9d7 1548 return x->array[0] == y->array[0];
c6fb90c8
L		 1549 break;
1550 default:
1551 abort ();
1552 }
1553}
40fb9820 1554
0dfbf9d7
L		 1555static INLINE int
1556cpu_flags_all_zero (const union i386_cpu_flags *x)
1557{
1558 switch (ARRAY_SIZE(x->array))
1559 {
53467f57
IT		 1560 case 4:
1561 if (x->array[3])
1562 return 0;
1563 /* Fall through. */
0dfbf9d7
L		 1564 case 3:
1565 if (x->array[2])
1566 return 0;
1a0670f3 1567 /* Fall through. */
0dfbf9d7
L		 1568 case 2:
1569 if (x->array[1])
1570 return 0;
1a0670f3 1571 /* Fall through. */
0dfbf9d7
L		 1572 case 1:
1573 return !x->array[0];
1574 default:
1575 abort ();
1576 }
1577}
1578
0dfbf9d7
L		 1579static INLINE int
1580cpu_flags_equal (const union i386_cpu_flags *x,
1581 const union i386_cpu_flags *y)
1582{
1583 switch (ARRAY_SIZE(x->array))
1584 {
53467f57
IT		 1585 case 4:
1586 if (x->array[3] != y->array[3])
1587 return 0;
1588 /* Fall through. */
0dfbf9d7
L		 1589 case 3:
1590 if (x->array[2] != y->array[2])
1591 return 0;
1a0670f3 1592 /* Fall through. */
0dfbf9d7
L		 1593 case 2:
1594 if (x->array[1] != y->array[1])
1595 return 0;
1a0670f3 1596 /* Fall through. */
0dfbf9d7
L		 1597 case 1:
1598 return x->array[0] == y->array[0];
1599 break;
1600 default:
1601 abort ();
1602 }
1603}
c6fb90c8
L		 1604
1605static INLINE int
1606cpu_flags_check_cpu64 (i386_cpu_flags f)
1607{
1608 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1609 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1610}
1611
c6fb90c8
L		 1612static INLINE i386_cpu_flags
1613cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1614{
c6fb90c8
L		 1615 switch (ARRAY_SIZE (x.array))
1616 {
53467f57
IT		 1617 case 4:
1618 x.array [3] &= y.array [3];
1619 /* Fall through. */
c6fb90c8
L		 1620 case 3:
1621 x.array [2] &= y.array [2];
1a0670f3 1622 /* Fall through. */
c6fb90c8
L		 1623 case 2:
1624 x.array [1] &= y.array [1];
1a0670f3 1625 /* Fall through. */
c6fb90c8
L		 1626 case 1:
1627 x.array [0] &= y.array [0];
1628 break;
1629 default:
1630 abort ();
1631 }
1632 return x;
1633}
40fb9820 1634
c6fb90c8
L		 1635static INLINE i386_cpu_flags
1636cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1637{
c6fb90c8 1638 switch (ARRAY_SIZE (x.array))
40fb9820 1639 {
53467f57
IT		 1640 case 4:
1641 x.array [3] |= y.array [3];
1642 /* Fall through. */
c6fb90c8
L		 1643 case 3:
1644 x.array [2] |= y.array [2];
1a0670f3 1645 /* Fall through. */
c6fb90c8
L		 1646 case 2:
1647 x.array [1] |= y.array [1];
1a0670f3 1648 /* Fall through. */
c6fb90c8
L		 1649 case 1:
1650 x.array [0] |= y.array [0];
40fb9820
L		 1651 break;
1652 default:
1653 abort ();
1654 }
40fb9820
L		 1655 return x;
1656}
1657
309d3373
JB		 1658static INLINE i386_cpu_flags
1659cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1660{
1661 switch (ARRAY_SIZE (x.array))
1662 {
53467f57
IT		 1663 case 4:
1664 x.array [3] &= ~y.array [3];
1665 /* Fall through. */
309d3373
JB		 1666 case 3:
1667 x.array [2] &= ~y.array [2];
1a0670f3 1668 /* Fall through. */
309d3373
JB		 1669 case 2:
1670 x.array [1] &= ~y.array [1];
1a0670f3 1671 /* Fall through. */
309d3373
JB		 1672 case 1:
1673 x.array [0] &= ~y.array [0];
1674 break;
1675 default:
1676 abort ();
1677 }
1678 return x;
1679}
1680
c0f3af97
L		 1681#define CPU_FLAGS_ARCH_MATCH 0x1
1682#define CPU_FLAGS_64BIT_MATCH 0x2
1683
c0f3af97 1684#define CPU_FLAGS_PERFECT_MATCH \
db12e14e 1685 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
c0f3af97
L		 1686
1687/* Return CPU flags match bits. */
3629bb00 1688
40fb9820 1689static int
d3ce72d0 1690cpu_flags_match (const insn_template *t)
40fb9820 1691{
c0f3af97
L		 1692 i386_cpu_flags x = t->cpu_flags;
1693 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1694
1695 x.bitfield.cpu64 = 0;
1696 x.bitfield.cpuno64 = 0;
1697
0dfbf9d7 1698 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1699 {
1700 /* This instruction is available on all archs. */
db12e14e 1701 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1702 }
3629bb00
L		 1703 else
1704 {
c0f3af97 1705 /* This instruction is available only on some archs. */
3629bb00
L		 1706 i386_cpu_flags cpu = cpu_arch_flags;
1707
ab592e75
JB		 1708 /* AVX512VL is no standalone feature - match it and then strip it. */
1709 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1710 return match;
1711 x.bitfield.cpuavx512vl = 0;
1712
3629bb00 1713 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1714 if (!cpu_flags_all_zero (&cpu))
1715 {
a5ff0eb2
L		 1716 if (x.bitfield.cpuavx)
1717 {
929f69fa 1718 /* We need to check a few extra flags with AVX. */
b9d49817
JB		 1719 if (cpu.bitfield.cpuavx
1720 && (!t->opcode_modifier.sse2avx || sse2avx)
1721 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
929f69fa 1722 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
b9d49817
JB		 1723 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1724 match |= CPU_FLAGS_ARCH_MATCH;
a5ff0eb2 1725 }
929f69fa
JB		 1726 else if (x.bitfield.cpuavx512f)
1727 {
1728 /* We need to check a few extra flags with AVX512F. */
1729 if (cpu.bitfield.cpuavx512f
1730 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1731 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1732 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1733 match |= CPU_FLAGS_ARCH_MATCH;
1734 }
a5ff0eb2 1735 else
db12e14e 1736 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1737 }
3629bb00 1738 }
c0f3af97 1739 return match;
40fb9820
L		 1740}
1741
c6fb90c8
L		 1742static INLINE i386_operand_type
1743operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1744{
c6fb90c8
L		 1745 switch (ARRAY_SIZE (x.array))
1746 {
1747 case 3:
1748 x.array [2] &= y.array [2];
1a0670f3 1749 /* Fall through. */
c6fb90c8
L		 1750 case 2:
1751 x.array [1] &= y.array [1];
1a0670f3 1752 /* Fall through. */
c6fb90c8
L		 1753 case 1:
1754 x.array [0] &= y.array [0];
1755 break;
1756 default:
1757 abort ();
1758 }
1759 return x;
40fb9820
L		 1760}
1761
73053c1f
JB		 1762static INLINE i386_operand_type
1763operand_type_and_not (i386_operand_type x, i386_operand_type y)
1764{
1765 switch (ARRAY_SIZE (x.array))
1766 {
1767 case 3:
1768 x.array [2] &= ~y.array [2];
1769 /* Fall through. */
1770 case 2:
1771 x.array [1] &= ~y.array [1];
1772 /* Fall through. */
1773 case 1:
1774 x.array [0] &= ~y.array [0];
1775 break;
1776 default:
1777 abort ();
1778 }
1779 return x;
1780}
1781
c6fb90c8
L		 1782static INLINE i386_operand_type
1783operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1784{
c6fb90c8 1785 switch (ARRAY_SIZE (x.array))
40fb9820 1786 {
c6fb90c8
L		 1787 case 3:
1788 x.array [2] |= y.array [2];
1a0670f3 1789 /* Fall through. */
c6fb90c8
L		 1790 case 2:
1791 x.array [1] |= y.array [1];
1a0670f3 1792 /* Fall through. */
c6fb90c8
L		 1793 case 1:
1794 x.array [0] |= y.array [0];
40fb9820
L		 1795 break;
1796 default:
1797 abort ();
1798 }
c6fb90c8
L		 1799 return x;
1800}
40fb9820 1801
c6fb90c8
L		 1802static INLINE i386_operand_type
1803operand_type_xor (i386_operand_type x, i386_operand_type y)
1804{
1805 switch (ARRAY_SIZE (x.array))
1806 {
1807 case 3:
1808 x.array [2] ^= y.array [2];
1a0670f3 1809 /* Fall through. */
c6fb90c8
L		 1810 case 2:
1811 x.array [1] ^= y.array [1];
1a0670f3 1812 /* Fall through. */
c6fb90c8
L		 1813 case 1:
1814 x.array [0] ^= y.array [0];
1815 break;
1816 default:
1817 abort ();
1818 }
40fb9820
L		 1819 return x;
1820}
1821
1822static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1823static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1824static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1825static const i386_operand_type inoutportreg
1826 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1827static const i386_operand_type reg16_inoutportreg
1828 = OPERAND_TYPE_REG16_INOUTPORTREG;
1829static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1830static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1831static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1832static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1833static const i386_operand_type anydisp
1834 = OPERAND_TYPE_ANYDISP;
40fb9820 1835static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
43234a1e 1836static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1837static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1838static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1839static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1840static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1841static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1842static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1843static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1844static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1845static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1846static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1847
1848enum operand_type
1849{
1850 reg,
40fb9820
L		 1851 imm,
1852 disp,
1853 anymem
1854};
1855
c6fb90c8 1856static INLINE int
40fb9820
L		 1857operand_type_check (i386_operand_type t, enum operand_type c)
1858{
1859 switch (c)
1860 {
1861 case reg:
dc821c5f 1862 return t.bitfield.reg;
40fb9820 1863
40fb9820
L		 1864 case imm:
1865 return (t.bitfield.imm8
1866 || t.bitfield.imm8s
1867 || t.bitfield.imm16
1868 || t.bitfield.imm32
1869 || t.bitfield.imm32s
1870 || t.bitfield.imm64);
1871
1872 case disp:
1873 return (t.bitfield.disp8
1874 || t.bitfield.disp16
1875 || t.bitfield.disp32
1876 || t.bitfield.disp32s
1877 || t.bitfield.disp64);
1878
1879 case anymem:
1880 return (t.bitfield.disp8
1881 || t.bitfield.disp16
1882 || t.bitfield.disp32
1883 || t.bitfield.disp32s
1884 || t.bitfield.disp64
1885 || t.bitfield.baseindex);
1886
1887 default:
1888 abort ();
1889 }
2cfe26b6
AM		 1890
1891 return 0;
40fb9820
L		 1892}
1893
ca0d63fe 1894/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
5c07affc
L		 1895 operand J for instruction template T. */
1896
1897static INLINE int
d3ce72d0 1898match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1899{
1900 return !((i.types[j].bitfield.byte
1901 && !t->operand_types[j].bitfield.byte)
1902 || (i.types[j].bitfield.word
1903 && !t->operand_types[j].bitfield.word)
1904 || (i.types[j].bitfield.dword
1905 && !t->operand_types[j].bitfield.dword)
1906 || (i.types[j].bitfield.qword
ca0d63fe
JB		 1907 && !t->operand_types[j].bitfield.qword)
1908 || (i.types[j].bitfield.tbyte
1909 && !t->operand_types[j].bitfield.tbyte));
5c07affc
L		 1910}
1911
1b54b8d7
JB		 1912/* Return 1 if there is no conflict in SIMD register on
1913 operand J for instruction template T. */
1914
1915static INLINE int
1916match_simd_size (const insn_template *t, unsigned int j)
1917{
1918 return !((i.types[j].bitfield.xmmword
1919 && !t->operand_types[j].bitfield.xmmword)
1920 || (i.types[j].bitfield.ymmword
1921 && !t->operand_types[j].bitfield.ymmword)
1922 || (i.types[j].bitfield.zmmword
1923 && !t->operand_types[j].bitfield.zmmword));
1924}
1925
5c07affc
L		 1926/* Return 1 if there is no conflict in any size on operand J for
1927 instruction template T. */
1928
1929static INLINE int
d3ce72d0 1930match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1931{
1932 return (match_reg_size (t, j)
1933 && !((i.types[j].bitfield.unspecified
af508cb9 1934 && !i.broadcast
5c07affc
L		 1935 && !t->operand_types[j].bitfield.unspecified)
1936 || (i.types[j].bitfield.fword
1937 && !t->operand_types[j].bitfield.fword)
1b54b8d7
JB		 1938 /* For scalar opcode templates to allow register and memory
1939 operands at the same time, some special casing is needed
d6793fa1
JB		 1940 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1941 down-conversion vpmov*. */
1b54b8d7
JB		 1942 || ((t->operand_types[j].bitfield.regsimd
1943 && !t->opcode_modifier.broadcast
d6793fa1
JB		 1944 && (t->operand_types[j].bitfield.byte
1945 || t->operand_types[j].bitfield.word
1946 || t->operand_types[j].bitfield.dword
1b54b8d7
JB		 1947 || t->operand_types[j].bitfield.qword))
1948 ? (i.types[j].bitfield.xmmword
1949 || i.types[j].bitfield.ymmword
1950 || i.types[j].bitfield.zmmword)
1951 : !match_simd_size(t, j))));
5c07affc
L		 1952}
1953
1954/* Return 1 if there is no size conflict on any operands for
1955 instruction template T. */
1956
1957static INLINE int
d3ce72d0 1958operand_size_match (const insn_template *t)
5c07affc
L		 1959{
1960 unsigned int j;
1961 int match = 1;
1962
1963 /* Don't check jump instructions. */
1964 if (t->opcode_modifier.jump
1965 || t->opcode_modifier.jumpbyte
1966 || t->opcode_modifier.jumpdword
1967 || t->opcode_modifier.jumpintersegment)
1968 return match;
1969
1970 /* Check memory and accumulator operand size. */
1971 for (j = 0; j < i.operands; j++)
1972 {
1b54b8d7
JB		 1973 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1974 && t->operand_types[j].bitfield.anysize)
5c07affc
L		 1975 continue;
1976
1b54b8d7 1977 if (t->operand_types[j].bitfield.reg
dc821c5f 1978 && !match_reg_size (t, j))
5c07affc
L		 1979 {
1980 match = 0;
1981 break;
1982 }
1983
1b54b8d7
JB		 1984 if (t->operand_types[j].bitfield.regsimd
1985 && !match_simd_size (t, j))
1986 {
1987 match = 0;
1988 break;
1989 }
1990
1991 if (t->operand_types[j].bitfield.acc
1992 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1993 {
1994 match = 0;
1995 break;
1996 }
1997
5c07affc
L		 1998 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1999 {
2000 match = 0;
2001 break;
2002 }
2003 }
2004
891edac4 2005 if (match)
5c07affc 2006 return match;
38e314eb 2007 else if (!t->opcode_modifier.d)
891edac4
L		 2008 {
2009mismatch:
86e026a4 2010 i.error = operand_size_mismatch;
891edac4
L		 2011 return 0;
2012 }
5c07affc
L		 2013
2014 /* Check reverse. */
9c2799c2 2015 gas_assert (i.operands == 2);
5c07affc
L		 2016
2017 match = 1;
2018 for (j = 0; j < 2; j++)
2019 {
dc821c5f
JB		 2020 if ((t->operand_types[j].bitfield.reg
2021 || t->operand_types[j].bitfield.acc)
5c07affc 2022 && !match_reg_size (t, j ? 0 : 1))
891edac4 2023 goto mismatch;
5c07affc
L		 2024
2025 if (i.types[j].bitfield.mem
2026 && !match_mem_size (t, j ? 0 : 1))
891edac4 2027 goto mismatch;
5c07affc
L		 2028 }
2029
2030 return match;
2031}
2032
c6fb90c8 2033static INLINE int
40fb9820
L		 2034operand_type_match (i386_operand_type overlap,
2035 i386_operand_type given)
2036{
2037 i386_operand_type temp = overlap;
2038
2039 temp.bitfield.jumpabsolute = 0;
7d5e4556 2040 temp.bitfield.unspecified = 0;
5c07affc
L		 2041 temp.bitfield.byte = 0;
2042 temp.bitfield.word = 0;
2043 temp.bitfield.dword = 0;
2044 temp.bitfield.fword = 0;
2045 temp.bitfield.qword = 0;
2046 temp.bitfield.tbyte = 0;
2047 temp.bitfield.xmmword = 0;
c0f3af97 2048 temp.bitfield.ymmword = 0;
43234a1e 2049 temp.bitfield.zmmword = 0;
0dfbf9d7 2050 if (operand_type_all_zero (&temp))
891edac4 2051 goto mismatch;
40fb9820 2052
891edac4
L		 2053 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2054 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2055 return 1;
2056
2057mismatch:
a65babc9 2058 i.error = operand_type_mismatch;
891edac4 2059 return 0;
40fb9820
L		 2060}
2061
7d5e4556 2062/* If given types g0 and g1 are registers they must be of the same type
10c17abd
JB		 2063 unless the expected operand type register overlap is null.
2064 Memory operand size of certain SIMD instructions is also being checked
2065 here. */
40fb9820 2066
c6fb90c8 2067static INLINE int
dc821c5f 2068operand_type_register_match (i386_operand_type g0,
40fb9820 2069 i386_operand_type t0,
40fb9820
L		 2070 i386_operand_type g1,
2071 i386_operand_type t1)
2072{
10c17abd
JB		 2073 if (!g0.bitfield.reg
2074 && !g0.bitfield.regsimd
2075 && (!operand_type_check (g0, anymem)
2076 || g0.bitfield.unspecified
2077 || !t0.bitfield.regsimd))
40fb9820
L		 2078 return 1;
2079
10c17abd
JB		 2080 if (!g1.bitfield.reg
2081 && !g1.bitfield.regsimd
2082 && (!operand_type_check (g1, anymem)
2083 || g1.bitfield.unspecified
2084 || !t1.bitfield.regsimd))
40fb9820
L		 2085 return 1;
2086
dc821c5f
JB		 2087 if (g0.bitfield.byte == g1.bitfield.byte
2088 && g0.bitfield.word == g1.bitfield.word
2089 && g0.bitfield.dword == g1.bitfield.dword
10c17abd
JB		 2090 && g0.bitfield.qword == g1.bitfield.qword
2091 && g0.bitfield.xmmword == g1.bitfield.xmmword
2092 && g0.bitfield.ymmword == g1.bitfield.ymmword
2093 && g0.bitfield.zmmword == g1.bitfield.zmmword)
40fb9820
L		 2094 return 1;
2095
dc821c5f
JB		 2096 if (!(t0.bitfield.byte & t1.bitfield.byte)
2097 && !(t0.bitfield.word & t1.bitfield.word)
2098 && !(t0.bitfield.dword & t1.bitfield.dword)
10c17abd
JB		 2099 && !(t0.bitfield.qword & t1.bitfield.qword)
2100 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2101 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2102 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
891edac4
L		 2103 return 1;
2104
a65babc9 2105 i.error = register_type_mismatch;
891edac4
L		 2106
2107 return 0;
40fb9820
L		 2108}
2109
4c692bc7
JB		 2110static INLINE unsigned int
2111register_number (const reg_entry *r)
2112{
2113 unsigned int nr = r->reg_num;
2114
2115 if (r->reg_flags & RegRex)
2116 nr += 8;
2117
200cbe0f
L		 2118 if (r->reg_flags & RegVRex)
2119 nr += 16;
2120
4c692bc7
JB		 2121 return nr;
2122}
2123
252b5132 2124static INLINE unsigned int
40fb9820 2125mode_from_disp_size (i386_operand_type t)
252b5132 2126{
b5014f7a 2127 if (t.bitfield.disp8)
40fb9820
L		 2128 return 1;
2129 else if (t.bitfield.disp16
2130 || t.bitfield.disp32
2131 || t.bitfield.disp32s)
2132 return 2;
2133 else
2134 return 0;
252b5132
RH		 2135}
2136
2137static INLINE int
65879393 2138fits_in_signed_byte (addressT num)
252b5132 2139{
65879393 2140 return num + 0x80 <= 0xff;
47926f60 2141}
252b5132
RH		 2142
2143static INLINE int
65879393 2144fits_in_unsigned_byte (addressT num)
252b5132 2145{
65879393 2146 return num <= 0xff;
47926f60 2147}
252b5132
RH		 2148
2149static INLINE int
65879393 2150fits_in_unsigned_word (addressT num)
252b5132 2151{
65879393 2152 return num <= 0xffff;
47926f60 2153}
252b5132
RH		 2154
2155static INLINE int
65879393 2156fits_in_signed_word (addressT num)
252b5132 2157{
65879393 2158 return num + 0x8000 <= 0xffff;
47926f60 2159}
2a962e6d 2160
3e73aa7c 2161static INLINE int
65879393 2162fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2163{
2164#ifndef BFD64
2165 return 1;
2166#else
65879393 2167 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2168#endif
2169} /* fits_in_signed_long() */
2a962e6d 2170
3e73aa7c 2171static INLINE int
65879393 2172fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2173{
2174#ifndef BFD64
2175 return 1;
2176#else
65879393 2177 return num <= 0xffffffff;
3e73aa7c
JH		 2178#endif
2179} /* fits_in_unsigned_long() */
252b5132 2180
43234a1e 2181static INLINE int
b5014f7a 2182fits_in_disp8 (offsetT num)
43234a1e
L		 2183{
2184 int shift = i.memshift;
2185 unsigned int mask;
2186
2187 if (shift == -1)
2188 abort ();
2189
2190 mask = (1 << shift) - 1;
2191
2192 /* Return 0 if NUM isn't properly aligned. */
2193 if ((num & mask))
2194 return 0;
2195
2196 /* Check if NUM will fit in 8bit after shift. */
2197 return fits_in_signed_byte (num >> shift);
2198}
2199
a683cc34
SP		 2200static INLINE int
2201fits_in_imm4 (offsetT num)
2202{
2203 return (num & 0xf) == num;
2204}
2205
40fb9820 2206static i386_operand_type
e3bb37b5 2207smallest_imm_type (offsetT num)
252b5132 2208{
40fb9820 2209 i386_operand_type t;
7ab9ffdd 2210
0dfbf9d7 2211 operand_type_set (&t, 0);
40fb9820
L		 2212 t.bitfield.imm64 = 1;
2213
2214 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2215 {
2216 /* This code is disabled on the 486 because all the Imm1 forms
2217 in the opcode table are slower on the i486. They're the
2218 versions with the implicitly specified single-position
2219 displacement, which has another syntax if you really want to
2220 use that form. */
40fb9820
L		 2221 t.bitfield.imm1 = 1;
2222 t.bitfield.imm8 = 1;
2223 t.bitfield.imm8s = 1;
2224 t.bitfield.imm16 = 1;
2225 t.bitfield.imm32 = 1;
2226 t.bitfield.imm32s = 1;
2227 }
2228 else if (fits_in_signed_byte (num))
2229 {
2230 t.bitfield.imm8 = 1;
2231 t.bitfield.imm8s = 1;
2232 t.bitfield.imm16 = 1;
2233 t.bitfield.imm32 = 1;
2234 t.bitfield.imm32s = 1;
2235 }
2236 else if (fits_in_unsigned_byte (num))
2237 {
2238 t.bitfield.imm8 = 1;
2239 t.bitfield.imm16 = 1;
2240 t.bitfield.imm32 = 1;
2241 t.bitfield.imm32s = 1;
2242 }
2243 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2244 {
2245 t.bitfield.imm16 = 1;
2246 t.bitfield.imm32 = 1;
2247 t.bitfield.imm32s = 1;
2248 }
2249 else if (fits_in_signed_long (num))
2250 {
2251 t.bitfield.imm32 = 1;
2252 t.bitfield.imm32s = 1;
2253 }
2254 else if (fits_in_unsigned_long (num))
2255 t.bitfield.imm32 = 1;
2256
2257 return t;
47926f60 2258}
252b5132 2259
847f7ad4 2260static offsetT
e3bb37b5 2261offset_in_range (offsetT val, int size)
847f7ad4 2262{
508866be 2263 addressT mask;
ba2adb93 2264
847f7ad4
AM		 2265 switch (size)
2266 {
508866be
L		 2267 case 1: mask = ((addressT) 1 << 8) - 1; break;
2268 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2269 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2270#ifdef BFD64
2271 case 8: mask = ((addressT) 2 << 63) - 1; break;
2272#endif
47926f60 2273 default: abort ();
847f7ad4
AM		 2274 }
2275
9de868bf
L		 2276#ifdef BFD64
2277 /* If BFD64, sign extend val for 32bit address mode. */
2278 if (flag_code != CODE_64BIT
2279 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2280 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2281 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2282#endif
ba2adb93 2283
47926f60 2284 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2285 {
2286 char buf1[40], buf2[40];
2287
2288 sprint_value (buf1, val);
2289 sprint_value (buf2, val & mask);
2290 as_warn (_("%s shortened to %s"), buf1, buf2);
2291 }
2292 return val & mask;
2293}
2294
c32fa91d
L		 2295enum PREFIX_GROUP
2296{
2297 PREFIX_EXIST = 0,
2298 PREFIX_LOCK,
2299 PREFIX_REP,
04ef582a 2300 PREFIX_DS,
c32fa91d
L		 2301 PREFIX_OTHER
2302};
2303
2304/* Returns
2305 a. PREFIX_EXIST if attempting to add a prefix where one from the
2306 same class already exists.
2307 b. PREFIX_LOCK if lock prefix is added.
2308 c. PREFIX_REP if rep/repne prefix is added.
04ef582a
L		 2309 d. PREFIX_DS if ds prefix is added.
2310 e. PREFIX_OTHER if other prefix is added.
c32fa91d
L		 2311 */
2312
2313static enum PREFIX_GROUP
e3bb37b5 2314add_prefix (unsigned int prefix)
252b5132 2315{
c32fa91d 2316 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2317 unsigned int q;
252b5132 2318
29b0f896
AM		 2319 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2320 && flag_code == CODE_64BIT)
b1905489 2321 {
161a04f6
L		 2322 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2323 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2324 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2325 ret = PREFIX_EXIST;
b1905489
JB		 2326 q = REX_PREFIX;
2327 }
3e73aa7c 2328 else
b1905489
JB		 2329 {
2330 switch (prefix)
2331 {
2332 default:
2333 abort ();
2334
b1905489 2335 case DS_PREFIX_OPCODE:
04ef582a
L		 2336 ret = PREFIX_DS;
2337 /* Fall through. */
2338 case CS_PREFIX_OPCODE:
b1905489
JB		 2339 case ES_PREFIX_OPCODE:
2340 case FS_PREFIX_OPCODE:
2341 case GS_PREFIX_OPCODE:
2342 case SS_PREFIX_OPCODE:
2343 q = SEG_PREFIX;
2344 break;
2345
2346 case REPNE_PREFIX_OPCODE:
2347 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2348 q = REP_PREFIX;
2349 ret = PREFIX_REP;
2350 break;
2351
b1905489 2352 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2353 q = LOCK_PREFIX;
2354 ret = PREFIX_LOCK;
b1905489
JB		 2355 break;
2356
2357 case FWAIT_OPCODE:
2358 q = WAIT_PREFIX;
2359 break;
2360
2361 case ADDR_PREFIX_OPCODE:
2362 q = ADDR_PREFIX;
2363 break;
2364
2365 case DATA_PREFIX_OPCODE:
2366 q = DATA_PREFIX;
2367 break;
2368 }
2369 if (i.prefix[q] != 0)
c32fa91d 2370 ret = PREFIX_EXIST;
b1905489 2371 }
252b5132 2372
b1905489 2373 if (ret)
252b5132 2374 {
b1905489
JB		 2375 if (!i.prefix[q])
2376 ++i.prefixes;
2377 i.prefix[q] |= prefix;
252b5132 2378 }
b1905489
JB		 2379 else
2380 as_bad (_("same type of prefix used twice"));
252b5132 2381
252b5132
RH		 2382 return ret;
2383}
2384
2385static void
78f12dd3 2386update_code_flag (int value, int check)
eecb386c 2387{
78f12dd3
L		 2388 PRINTF_LIKE ((*as_error));
2389
1e9cc1c2 2390 flag_code = (enum flag_code) value;
40fb9820
L		 2391 if (flag_code == CODE_64BIT)
2392 {
2393 cpu_arch_flags.bitfield.cpu64 = 1;
2394 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2395 }
2396 else
2397 {
2398 cpu_arch_flags.bitfield.cpu64 = 0;
2399 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2400 }
2401 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2402 {
78f12dd3
L		 2403 if (check)
2404 as_error = as_fatal;
2405 else
2406 as_error = as_bad;
2407 (*as_error) (_("64bit mode not supported on `%s'."),
2408 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2409 }
40fb9820 2410 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2411 {
78f12dd3
L		 2412 if (check)
2413 as_error = as_fatal;
2414 else
2415 as_error = as_bad;
2416 (*as_error) (_("32bit mode not supported on `%s'."),
2417 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2418 }
eecb386c
AM		 2419 stackop_size = '\0';
2420}
2421
78f12dd3
L		 2422static void
2423set_code_flag (int value)
2424{
2425 update_code_flag (value, 0);
2426}
2427
eecb386c 2428static void
e3bb37b5 2429set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2430{
1e9cc1c2 2431 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2432 if (flag_code != CODE_16BIT)
2433 abort ();
2434 cpu_arch_flags.bitfield.cpu64 = 0;
2435 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2436 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2437}
2438
2439static void
e3bb37b5 2440set_intel_syntax (int syntax_flag)
252b5132
RH		 2441{
2442 /* Find out if register prefixing is specified. */
2443 int ask_naked_reg = 0;
2444
2445 SKIP_WHITESPACE ();
29b0f896 2446 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2447 {
d02603dc
NC		 2448 char *string;
2449 int e = get_symbol_name (&string);
252b5132 2450
47926f60 2451 if (strcmp (string, "prefix") == 0)
252b5132 2452 ask_naked_reg = 1;
47926f60 2453 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2454 ask_naked_reg = -1;
2455 else
d0b47220 2456 as_bad (_("bad argument to syntax directive."));
d02603dc 2457 (void) restore_line_pointer (e);
252b5132
RH		 2458 }
2459 demand_empty_rest_of_line ();
c3332e24 2460
252b5132
RH		 2461 intel_syntax = syntax_flag;
2462
2463 if (ask_naked_reg == 0)
f86103b7
AM		 2464 allow_naked_reg = (intel_syntax
2465 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2466 else
2467 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2468
ee86248c 2469 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2470
e4a3b5a4 2471 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2472 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2473 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2474}
2475
1efbbeb4
L		 2476static void
2477set_intel_mnemonic (int mnemonic_flag)
2478{
e1d4d893 2479 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2480}
2481
db51cc60
L		 2482static void
2483set_allow_index_reg (int flag)
2484{
2485 allow_index_reg = flag;
2486}
2487
cb19c032 2488static void
7bab8ab5 2489set_check (int what)
cb19c032 2490{
7bab8ab5
JB		 2491 enum check_kind *kind;
2492 const char *str;
2493
2494 if (what)
2495 {
2496 kind = &operand_check;
2497 str = "operand";
2498 }
2499 else
2500 {
2501 kind = &sse_check;
2502 str = "sse";
2503 }
2504
cb19c032
L		 2505 SKIP_WHITESPACE ();
2506
2507 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2508 {
d02603dc
NC		 2509 char *string;
2510 int e = get_symbol_name (&string);
cb19c032
L		 2511
2512 if (strcmp (string, "none") == 0)
7bab8ab5 2513 *kind = check_none;
cb19c032 2514 else if (strcmp (string, "warning") == 0)
7bab8ab5 2515 *kind = check_warning;
cb19c032 2516 else if (strcmp (string, "error") == 0)
7bab8ab5 2517 *kind = check_error;
cb19c032 2518 else
7bab8ab5 2519 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2520 (void) restore_line_pointer (e);
cb19c032
L		 2521 }
2522 else
7bab8ab5 2523 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2524
2525 demand_empty_rest_of_line ();
2526}
2527
8a9036a4
L		 2528static void
2529check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2530 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2531{
2532#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2533 static const char *arch;
2534
2535 /* Intel LIOM is only supported on ELF. */
2536 if (!IS_ELF)
2537 return;
2538
2539 if (!arch)
2540 {
2541 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2542 use default_arch. */
2543 arch = cpu_arch_name;
2544 if (!arch)
2545 arch = default_arch;
2546 }
2547
81486035
L		 2548 /* If we are targeting Intel MCU, we must enable it. */
2549 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2550 || new_flag.bitfield.cpuiamcu)
2551 return;
2552
3632d14b 2553 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2554 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2555 || new_flag.bitfield.cpul1om)
8a9036a4 2556 return;
76ba9986 2557
7a9068fe
L		 2558 /* If we are targeting Intel K1OM, we must enable it. */
2559 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2560 || new_flag.bitfield.cpuk1om)
2561 return;
2562
8a9036a4
L		 2563 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2564#endif
2565}
2566
e413e4e9 2567static void
e3bb37b5 2568set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2569{
47926f60 2570 SKIP_WHITESPACE ();
e413e4e9 2571
29b0f896 2572 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2573 {
d02603dc
NC		 2574 char *string;
2575 int e = get_symbol_name (&string);
91d6fa6a 2576 unsigned int j;
40fb9820 2577 i386_cpu_flags flags;
e413e4e9 2578
91d6fa6a 2579 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2580 {
91d6fa6a 2581 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2582 {
91d6fa6a 2583 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2584
5c6af06e
JB		 2585 if (*string != '.')
2586 {
91d6fa6a 2587 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2588 cpu_sub_arch_name = NULL;
91d6fa6a 2589 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2590 if (flag_code == CODE_64BIT)
2591 {
2592 cpu_arch_flags.bitfield.cpu64 = 1;
2593 cpu_arch_flags.bitfield.cpuno64 = 0;
2594 }
2595 else
2596 {
2597 cpu_arch_flags.bitfield.cpu64 = 0;
2598 cpu_arch_flags.bitfield.cpuno64 = 1;
2599 }
91d6fa6a
NC		 2600 cpu_arch_isa = cpu_arch[j].type;
2601 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2602 if (!cpu_arch_tune_set)
2603 {
2604 cpu_arch_tune = cpu_arch_isa;
2605 cpu_arch_tune_flags = cpu_arch_isa_flags;
2606 }
5c6af06e
JB		 2607 break;
2608 }
40fb9820 2609
293f5f65
L		 2610 flags = cpu_flags_or (cpu_arch_flags,
2611 cpu_arch[j].flags);
81486035 2612
5b64d091 2613 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2614 {
6305a203
L		 2615 if (cpu_sub_arch_name)
2616 {
2617 char *name = cpu_sub_arch_name;
2618 cpu_sub_arch_name = concat (name,
91d6fa6a 2619 cpu_arch[j].name,
1bf57e9f 2620 (const char *) NULL);
6305a203
L		 2621 free (name);
2622 }
2623 else
91d6fa6a 2624 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2625 cpu_arch_flags = flags;
a586129e 2626 cpu_arch_isa_flags = flags;
5c6af06e 2627 }
0089dace
L		 2628 else
2629 cpu_arch_isa_flags
2630 = cpu_flags_or (cpu_arch_isa_flags,
2631 cpu_arch[j].flags);
d02603dc 2632 (void) restore_line_pointer (e);
5c6af06e
JB		 2633 demand_empty_rest_of_line ();
2634 return;
e413e4e9
AM		 2635 }
2636 }
293f5f65
L		 2637
2638 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2639 {
33eaf5de 2640 /* Disable an ISA extension. */
293f5f65
L		 2641 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2642 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2643 {
2644 flags = cpu_flags_and_not (cpu_arch_flags,
2645 cpu_noarch[j].flags);
2646 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2647 {
2648 if (cpu_sub_arch_name)
2649 {
2650 char *name = cpu_sub_arch_name;
2651 cpu_sub_arch_name = concat (name, string,
2652 (const char *) NULL);
2653 free (name);
2654 }
2655 else
2656 cpu_sub_arch_name = xstrdup (string);
2657 cpu_arch_flags = flags;
2658 cpu_arch_isa_flags = flags;
2659 }
2660 (void) restore_line_pointer (e);
2661 demand_empty_rest_of_line ();
2662 return;
2663 }
2664
2665 j = ARRAY_SIZE (cpu_arch);
2666 }
2667
91d6fa6a 2668 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2669 as_bad (_("no such architecture: `%s'"), string);
2670
2671 *input_line_pointer = e;
2672 }
2673 else
2674 as_bad (_("missing cpu architecture"));
2675
fddf5b5b
AM		 2676 no_cond_jump_promotion = 0;
2677 if (*input_line_pointer == ','
29b0f896 2678 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2679 {
d02603dc
NC		 2680 char *string;
2681 char e;
2682
2683 ++input_line_pointer;
2684 e = get_symbol_name (&string);
fddf5b5b
AM		 2685
2686 if (strcmp (string, "nojumps") == 0)
2687 no_cond_jump_promotion = 1;
2688 else if (strcmp (string, "jumps") == 0)
2689 ;
2690 else
2691 as_bad (_("no such architecture modifier: `%s'"), string);
2692
d02603dc 2693 (void) restore_line_pointer (e);
fddf5b5b
AM		 2694 }
2695
e413e4e9
AM		 2696 demand_empty_rest_of_line ();
2697}
2698
8a9036a4
L		 2699enum bfd_architecture
2700i386_arch (void)
2701{
3632d14b 2702 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2703 {
2704 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2705 || flag_code != CODE_64BIT)
2706 as_fatal (_("Intel L1OM is 64bit ELF only"));
2707 return bfd_arch_l1om;
2708 }
7a9068fe
L		 2709 else if (cpu_arch_isa == PROCESSOR_K1OM)
2710 {
2711 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2712 || flag_code != CODE_64BIT)
2713 as_fatal (_("Intel K1OM is 64bit ELF only"));
2714 return bfd_arch_k1om;
2715 }
81486035
L		 2716 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2717 {
2718 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2719 || flag_code == CODE_64BIT)
2720 as_fatal (_("Intel MCU is 32bit ELF only"));
2721 return bfd_arch_iamcu;
2722 }
8a9036a4
L		 2723 else
2724 return bfd_arch_i386;
2725}
2726
b9d79e03 2727unsigned long
7016a5d5 2728i386_mach (void)
b9d79e03 2729{
351f65ca 2730 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2731 {
3632d14b 2732 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2733 {
351f65ca
L		 2734 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2735 || default_arch[6] != '\0')
8a9036a4
L		 2736 as_fatal (_("Intel L1OM is 64bit ELF only"));
2737 return bfd_mach_l1om;
2738 }
7a9068fe
L		 2739 else if (cpu_arch_isa == PROCESSOR_K1OM)
2740 {
2741 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2742 || default_arch[6] != '\0')
2743 as_fatal (_("Intel K1OM is 64bit ELF only"));
2744 return bfd_mach_k1om;
2745 }
351f65ca 2746 else if (default_arch[6] == '\0')
8a9036a4 2747 return bfd_mach_x86_64;
351f65ca
L		 2748 else
2749 return bfd_mach_x64_32;
8a9036a4 2750 }
5197d474
L		 2751 else if (!strcmp (default_arch, "i386")
2752 || !strcmp (default_arch, "iamcu"))
81486035
L		 2753 {
2754 if (cpu_arch_isa == PROCESSOR_IAMCU)
2755 {
2756 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2757 as_fatal (_("Intel MCU is 32bit ELF only"));
2758 return bfd_mach_i386_iamcu;
2759 }
2760 else
2761 return bfd_mach_i386_i386;
2762 }
b9d79e03 2763 else
2b5d6a91 2764 as_fatal (_("unknown architecture"));
b9d79e03 2765}
b9d79e03 2766\f
252b5132 2767void
7016a5d5 2768md_begin (void)
252b5132
RH		 2769{
2770 const char *hash_err;
2771
86fa6981
L		 2772 /* Support pseudo prefixes like {disp32}. */
2773 lex_type ['{'] = LEX_BEGIN_NAME;
2774
47926f60 2775 /* Initialize op_hash hash table. */
252b5132
RH		 2776 op_hash = hash_new ();
2777
2778 {
d3ce72d0 2779 const insn_template *optab;
29b0f896 2780 templates *core_optab;
252b5132 2781
47926f60
KH		 2782 /* Setup for loop. */
2783 optab = i386_optab;
add39d23 2784 core_optab = XNEW (templates);
252b5132
RH		 2785 core_optab->start = optab;
2786
2787 while (1)
2788 {
2789 ++optab;
2790 if (optab->name == NULL
2791 || strcmp (optab->name, (optab - 1)->name) != 0)
2792 {
2793 /* different name --> ship out current template list;
47926f60 2794 add to hash table; & begin anew. */
252b5132
RH		 2795 core_optab->end = optab;
2796 hash_err = hash_insert (op_hash,
2797 (optab - 1)->name,
5a49b8ac 2798 (void *) core_optab);
252b5132
RH		 2799 if (hash_err)
2800 {
b37df7c4 2801 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2802 (optab - 1)->name,
2803 hash_err);
2804 }
2805 if (optab->name == NULL)
2806 break;
add39d23 2807 core_optab = XNEW (templates);
252b5132
RH		 2808 core_optab->start = optab;
2809 }
2810 }
2811 }
2812
47926f60 2813 /* Initialize reg_hash hash table. */
252b5132
RH		 2814 reg_hash = hash_new ();
2815 {
29b0f896 2816 const reg_entry *regtab;
c3fe08fa 2817 unsigned int regtab_size = i386_regtab_size;
252b5132 2818
c3fe08fa 2819 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2820 {
5a49b8ac 2821 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2822 if (hash_err)
b37df7c4 2823 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2824 regtab->reg_name,
2825 hash_err);
252b5132
RH		 2826 }
2827 }
2828
47926f60 2829 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2830 {
29b0f896
AM		 2831 int c;
2832 char *p;
252b5132
RH		 2833
2834 for (c = 0; c < 256; c++)
2835 {
3882b010 2836 if (ISDIGIT (c))
252b5132
RH		 2837 {
2838 digit_chars[c] = c;
2839 mnemonic_chars[c] = c;
2840 register_chars[c] = c;
2841 operand_chars[c] = c;
2842 }
3882b010 2843 else if (ISLOWER (c))
252b5132
RH		 2844 {
2845 mnemonic_chars[c] = c;
2846 register_chars[c] = c;
2847 operand_chars[c] = c;
2848 }
3882b010 2849 else if (ISUPPER (c))
252b5132 2850 {
3882b010 2851 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2852 register_chars[c] = mnemonic_chars[c];
2853 operand_chars[c] = c;
2854 }
43234a1e 2855 else if (c == '{' || c == '}')
86fa6981
L		 2856 {
2857 mnemonic_chars[c] = c;
2858 operand_chars[c] = c;
2859 }
252b5132 2860
3882b010 2861 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2862 identifier_chars[c] = c;
2863 else if (c >= 128)
2864 {
2865 identifier_chars[c] = c;
2866 operand_chars[c] = c;
2867 }
2868 }
2869
2870#ifdef LEX_AT
2871 identifier_chars['@'] = '@';
32137342
NC		 2872#endif
2873#ifdef LEX_QM
2874 identifier_chars['?'] = '?';
2875 operand_chars['?'] = '?';
252b5132 2876#endif
252b5132 2877 digit_chars['-'] = '-';
c0f3af97 2878 mnemonic_chars['_'] = '_';
791fe849 2879 mnemonic_chars['-'] = '-';
0003779b 2880 mnemonic_chars['.'] = '.';
252b5132
RH		 2881 identifier_chars['_'] = '_';
2882 identifier_chars['.'] = '.';
2883
2884 for (p = operand_special_chars; *p != '\0'; p++)
2885 operand_chars[(unsigned char) *p] = *p;
2886 }
2887
a4447b93
RH		 2888 if (flag_code == CODE_64BIT)
2889 {
ca19b261
KT		 2890#if defined (OBJ_COFF) && defined (TE_PE)
2891 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2892 ? 32 : 16);
2893#else
a4447b93 2894 x86_dwarf2_return_column = 16;
ca19b261 2895#endif
61ff971f 2896 x86_cie_data_alignment = -8;
a4447b93
RH		 2897 }
2898 else
2899 {
2900 x86_dwarf2_return_column = 8;
2901 x86_cie_data_alignment = -4;
2902 }
252b5132
RH		 2903}
2904
2905void
e3bb37b5 2906i386_print_statistics (FILE *file)
252b5132
RH		 2907{
2908 hash_print_statistics (file, "i386 opcode", op_hash);
2909 hash_print_statistics (file, "i386 register", reg_hash);
2910}
2911\f
252b5132
RH		 2912#ifdef DEBUG386
2913
ce8a8b2f 2914/* Debugging routines for md_assemble. */
d3ce72d0 2915static void pte (insn_template *);
40fb9820 2916static void pt (i386_operand_type);
e3bb37b5
L		 2917static void pe (expressionS *);
2918static void ps (symbolS *);
252b5132
RH		 2919
2920static void
e3bb37b5 2921pi (char *line, i386_insn *x)
252b5132 2922{
09137c09 2923 unsigned int j;
252b5132
RH		 2924
2925 fprintf (stdout, "%s: template ", line);
2926 pte (&x->tm);
09f131f2
JH		 2927 fprintf (stdout, " address: base %s index %s scale %x\n",
2928 x->base_reg ? x->base_reg->reg_name : "none",
2929 x->index_reg ? x->index_reg->reg_name : "none",
2930 x->log2_scale_factor);
2931 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2932 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2933 fprintf (stdout, " sib: base %x index %x scale %x\n",
2934 x->sib.base, x->sib.index, x->sib.scale);
2935 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2936 (x->rex & REX_W) != 0,
2937 (x->rex & REX_R) != 0,
2938 (x->rex & REX_X) != 0,
2939 (x->rex & REX_B) != 0);
09137c09 2940 for (j = 0; j < x->operands; j++)
252b5132 2941 {
09137c09
SP		 2942 fprintf (stdout, " #%d: ", j + 1);
2943 pt (x->types[j]);
252b5132 2944 fprintf (stdout, "\n");
dc821c5f 2945 if (x->types[j].bitfield.reg
09137c09 2946 || x->types[j].bitfield.regmmx
1b54b8d7 2947 || x->types[j].bitfield.regsimd
09137c09
SP		 2948 || x->types[j].bitfield.sreg2
2949 || x->types[j].bitfield.sreg3
2950 || x->types[j].bitfield.control
2951 || x->types[j].bitfield.debug
2952 || x->types[j].bitfield.test)
2953 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2954 if (operand_type_check (x->types[j], imm))
2955 pe (x->op[j].imms);
2956 if (operand_type_check (x->types[j], disp))
2957 pe (x->op[j].disps);
252b5132
RH		 2958 }
2959}
2960
2961static void
d3ce72d0 2962pte (insn_template *t)
252b5132 2963{
09137c09 2964 unsigned int j;
252b5132 2965 fprintf (stdout, " %d operands ", t->operands);
47926f60 2966 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2967 if (t->extension_opcode != None)
2968 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2969 if (t->opcode_modifier.d)
252b5132 2970 fprintf (stdout, "D");
40fb9820 2971 if (t->opcode_modifier.w)
252b5132
RH		 2972 fprintf (stdout, "W");
2973 fprintf (stdout, "\n");
09137c09 2974 for (j = 0; j < t->operands; j++)
252b5132 2975 {
09137c09
SP		 2976 fprintf (stdout, " #%d type ", j + 1);
2977 pt (t->operand_types[j]);
252b5132
RH		 2978 fprintf (stdout, "\n");
2979 }
2980}
2981
2982static void
e3bb37b5 2983pe (expressionS *e)
252b5132 2984{
24eab124 2985 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2986 fprintf (stdout, " add_number %ld (%lx)\n",
2987 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2988 if (e->X_add_symbol)
2989 {
2990 fprintf (stdout, " add_symbol ");
2991 ps (e->X_add_symbol);
2992 fprintf (stdout, "\n");
2993 }
2994 if (e->X_op_symbol)
2995 {
2996 fprintf (stdout, " op_symbol ");
2997 ps (e->X_op_symbol);
2998 fprintf (stdout, "\n");
2999 }
3000}
3001
3002static void
e3bb37b5 3003ps (symbolS *s)
252b5132
RH		 3004{
3005 fprintf (stdout, "%s type %s%s",
3006 S_GET_NAME (s),
3007 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3008 segment_name (S_GET_SEGMENT (s)));
3009}
3010
7b81dfbb 3011static struct type_name
252b5132 3012 {
40fb9820
L		 3013 i386_operand_type mask;
3014 const char *name;
252b5132 3015 }
7b81dfbb 3016const type_names[] =
252b5132 3017{
40fb9820
L		 3018 { OPERAND_TYPE_REG8, "r8" },
3019 { OPERAND_TYPE_REG16, "r16" },
3020 { OPERAND_TYPE_REG32, "r32" },
3021 { OPERAND_TYPE_REG64, "r64" },
3022 { OPERAND_TYPE_IMM8, "i8" },
3023 { OPERAND_TYPE_IMM8, "i8s" },
3024 { OPERAND_TYPE_IMM16, "i16" },
3025 { OPERAND_TYPE_IMM32, "i32" },
3026 { OPERAND_TYPE_IMM32S, "i32s" },
3027 { OPERAND_TYPE_IMM64, "i64" },
3028 { OPERAND_TYPE_IMM1, "i1" },
3029 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3030 { OPERAND_TYPE_DISP8, "d8" },
3031 { OPERAND_TYPE_DISP16, "d16" },
3032 { OPERAND_TYPE_DISP32, "d32" },
3033 { OPERAND_TYPE_DISP32S, "d32s" },
3034 { OPERAND_TYPE_DISP64, "d64" },
3035 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3036 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3037 { OPERAND_TYPE_CONTROL, "control reg" },
3038 { OPERAND_TYPE_TEST, "test reg" },
3039 { OPERAND_TYPE_DEBUG, "debug reg" },
3040 { OPERAND_TYPE_FLOATREG, "FReg" },
3041 { OPERAND_TYPE_FLOATACC, "FAcc" },
3042 { OPERAND_TYPE_SREG2, "SReg2" },
3043 { OPERAND_TYPE_SREG3, "SReg3" },
3044 { OPERAND_TYPE_ACC, "Acc" },
3045 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3046 { OPERAND_TYPE_REGMMX, "rMMX" },
3047 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 3048 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 3049 { OPERAND_TYPE_REGZMM, "rZMM" },
3050 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 3051 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 3052};
3053
3054static void
40fb9820 3055pt (i386_operand_type t)
252b5132 3056{
40fb9820 3057 unsigned int j;
c6fb90c8 3058 i386_operand_type a;
252b5132 3059
40fb9820 3060 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 3061 {
3062 a = operand_type_and (t, type_names[j].mask);
0349dc08 3063 if (!operand_type_all_zero (&a))
c6fb90c8
L		 3064 fprintf (stdout, "%s, ", type_names[j].name);
3065 }
252b5132
RH		 3066 fflush (stdout);
3067}
3068
3069#endif /* DEBUG386 */
3070\f
252b5132 3071static bfd_reloc_code_real_type
3956db08 3072reloc (unsigned int size,
64e74474
AM		 3073 int pcrel,
3074 int sign,
3075 bfd_reloc_code_real_type other)
252b5132 3076{
47926f60 3077 if (other != NO_RELOC)
3956db08 3078 {
91d6fa6a 3079 reloc_howto_type *rel;
3956db08
JB		 3080
3081 if (size == 8)
3082 switch (other)
3083 {
64e74474
AM		 3084 case BFD_RELOC_X86_64_GOT32:
3085 return BFD_RELOC_X86_64_GOT64;
3086 break;
553d1284
L		 3087 case BFD_RELOC_X86_64_GOTPLT64:
3088 return BFD_RELOC_X86_64_GOTPLT64;
3089 break;
64e74474
AM		 3090 case BFD_RELOC_X86_64_PLTOFF64:
3091 return BFD_RELOC_X86_64_PLTOFF64;
3092 break;
3093 case BFD_RELOC_X86_64_GOTPC32:
3094 other = BFD_RELOC_X86_64_GOTPC64;
3095 break;
3096 case BFD_RELOC_X86_64_GOTPCREL:
3097 other = BFD_RELOC_X86_64_GOTPCREL64;
3098 break;
3099 case BFD_RELOC_X86_64_TPOFF32:
3100 other = BFD_RELOC_X86_64_TPOFF64;
3101 break;
3102 case BFD_RELOC_X86_64_DTPOFF32:
3103 other = BFD_RELOC_X86_64_DTPOFF64;
3104 break;
3105 default:
3106 break;
3956db08 3107 }
e05278af 3108
8ce3d284 3109#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 3110 if (other == BFD_RELOC_SIZE32)
3111 {
3112 if (size == 8)
1ab668bf 3113 other = BFD_RELOC_SIZE64;
8fd4256d 3114 if (pcrel)
1ab668bf
AM		 3115 {
3116 as_bad (_("there are no pc-relative size relocations"));
3117 return NO_RELOC;
3118 }
8fd4256d 3119 }
8ce3d284 3120#endif
8fd4256d 3121
e05278af 3122 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 3123 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 3124 sign = -1;
3125
91d6fa6a
NC		 3126 rel = bfd_reloc_type_lookup (stdoutput, other);
3127 if (!rel)
3956db08 3128 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 3129 else if (size != bfd_get_reloc_size (rel))
3956db08 3130 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 3131 bfd_get_reloc_size (rel),
3956db08 3132 size);
91d6fa6a 3133 else if (pcrel && !rel->pc_relative)
3956db08 3134 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 3135 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 3136 && !sign)
91d6fa6a 3137 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 3138 && sign > 0))
3956db08
JB		 3139 as_bad (_("relocated field and relocation type differ in signedness"));
3140 else
3141 return other;
3142 return NO_RELOC;
3143 }
252b5132
RH		 3144
3145 if (pcrel)
3146 {
3e73aa7c 3147 if (!sign)
3956db08 3148 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 3149 switch (size)
3150 {
3151 case 1: return BFD_RELOC_8_PCREL;
3152 case 2: return BFD_RELOC_16_PCREL;
d258b828 3153 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 3154 case 8: return BFD_RELOC_64_PCREL;
252b5132 3155 }
3956db08 3156 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3157 }
3158 else
3159 {
3956db08 3160 if (sign > 0)
e5cb08ac 3161 switch (size)
3e73aa7c
JH		 3162 {
3163 case 4: return BFD_RELOC_X86_64_32S;
3164 }
3165 else
3166 switch (size)
3167 {
3168 case 1: return BFD_RELOC_8;
3169 case 2: return BFD_RELOC_16;
3170 case 4: return BFD_RELOC_32;
3171 case 8: return BFD_RELOC_64;
3172 }
3956db08
JB		 3173 as_bad (_("cannot do %s %u byte relocation"),
3174 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3175 }
3176
0cc9e1d3 3177 return NO_RELOC;
252b5132
RH		 3178}
3179
47926f60
KH		 3180/* Here we decide which fixups can be adjusted to make them relative to
3181 the beginning of the section instead of the symbol. Basically we need
3182 to make sure that the dynamic relocations are done correctly, so in
3183 some cases we force the original symbol to be used. */
3184
252b5132 3185int
e3bb37b5 3186tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3187{
6d249963 3188#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3189 if (!IS_ELF)
31312f95
AM		 3190 return 1;
3191
a161fe53
AM		 3192 /* Don't adjust pc-relative references to merge sections in 64-bit
3193 mode. */
3194 if (use_rela_relocations
3195 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3196 && fixP->fx_pcrel)
252b5132 3197 return 0;
31312f95 3198
8d01d9a9
AJ		 3199 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3200 and changed later by validate_fix. */
3201 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3202 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3203 return 0;
3204
8fd4256d
L		 3205 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3206 for size relocations. */
3207 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3208 || fixP->fx_r_type == BFD_RELOC_SIZE64
3209 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3210 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3211 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3212 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3213 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3214 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3215 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3216 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3217 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3218 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3219 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3220 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3221 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3222 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3223 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3224 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3225 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3226 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3227 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3228 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3229 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3230 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3231 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3232 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3233 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3234 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3235 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3236 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3237 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3238 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3239 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3240 return 0;
31312f95 3241#endif
252b5132
RH		 3242 return 1;
3243}
252b5132 3244
b4cac588 3245static int
e3bb37b5 3246intel_float_operand (const char *mnemonic)
252b5132 3247{
9306ca4a
JB		 3248 /* Note that the value returned is meaningful only for opcodes with (memory)
3249 operands, hence the code here is free to improperly handle opcodes that
3250 have no operands (for better performance and smaller code). */
3251
3252 if (mnemonic[0] != 'f')
3253 return 0; /* non-math */
3254
3255 switch (mnemonic[1])
3256 {
3257 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3258 the fs segment override prefix not currently handled because no
3259 call path can make opcodes without operands get here */
3260 case 'i':
3261 return 2 /* integer op */;
3262 case 'l':
3263 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3264 return 3; /* fldcw/fldenv */
3265 break;
3266 case 'n':
3267 if (mnemonic[2] != 'o' /* fnop */)
3268 return 3; /* non-waiting control op */
3269 break;
3270 case 'r':
3271 if (mnemonic[2] == 's')
3272 return 3; /* frstor/frstpm */
3273 break;
3274 case 's':
3275 if (mnemonic[2] == 'a')
3276 return 3; /* fsave */
3277 if (mnemonic[2] == 't')
3278 {
3279 switch (mnemonic[3])
3280 {
3281 case 'c': /* fstcw */
3282 case 'd': /* fstdw */
3283 case 'e': /* fstenv */
3284 case 's': /* fsts[gw] */
3285 return 3;
3286 }
3287 }
3288 break;
3289 case 'x':
3290 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3291 return 0; /* fxsave/fxrstor are not really math ops */
3292 break;
3293 }
252b5132 3294
9306ca4a 3295 return 1;
252b5132
RH		 3296}
3297
c0f3af97
L		 3298/* Build the VEX prefix. */
3299
3300static void
d3ce72d0 3301build_vex_prefix (const insn_template *t)
c0f3af97
L		 3302{
3303 unsigned int register_specifier;
3304 unsigned int implied_prefix;
3305 unsigned int vector_length;
3306
3307 /* Check register specifier. */
3308 if (i.vex.register_specifier)
43234a1e
L		 3309 {
3310 register_specifier =
3311 ~register_number (i.vex.register_specifier) & 0xf;
3312 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3313 }
c0f3af97
L		 3314 else
3315 register_specifier = 0xf;
3316
33eaf5de 3317 /* Use 2-byte VEX prefix by swapping destination and source
fa99fab2 3318 operand. */
86fa6981
L		 3319 if (i.vec_encoding != vex_encoding_vex3
3320 && i.dir_encoding == dir_encoding_default
fa99fab2 3321 && i.operands == i.reg_operands
7f399153 3322 && i.tm.opcode_modifier.vexopcode == VEX0F
86fa6981 3323 && i.tm.opcode_modifier.load
fa99fab2
L		 3324 && i.rex == REX_B)
3325 {
3326 unsigned int xchg = i.operands - 1;
3327 union i386_op temp_op;
3328 i386_operand_type temp_type;
3329
3330 temp_type = i.types[xchg];
3331 i.types[xchg] = i.types[0];
3332 i.types[0] = temp_type;
3333 temp_op = i.op[xchg];
3334 i.op[xchg] = i.op[0];
3335 i.op[0] = temp_op;
3336
9c2799c2 3337 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3338
3339 i.rex = REX_R;
3340 xchg = i.rm.regmem;
3341 i.rm.regmem = i.rm.reg;
3342 i.rm.reg = xchg;
3343
3344 /* Use the next insn. */
3345 i.tm = t[1];
3346 }
3347
539f890d
L		 3348 if (i.tm.opcode_modifier.vex == VEXScalar)
3349 vector_length = avxscalar;
10c17abd
JB		 3350 else if (i.tm.opcode_modifier.vex == VEX256)
3351 vector_length = 1;
539f890d 3352 else
10c17abd
JB		 3353 {
3354 unsigned int op;
3355
3356 vector_length = 0;
3357 for (op = 0; op < t->operands; ++op)
3358 if (t->operand_types[op].bitfield.xmmword
3359 && t->operand_types[op].bitfield.ymmword
3360 && i.types[op].bitfield.ymmword)
3361 {
3362 vector_length = 1;
3363 break;
3364 }
3365 }
c0f3af97
L		 3366
3367 switch ((i.tm.base_opcode >> 8) & 0xff)
3368 {
3369 case 0:
3370 implied_prefix = 0;
3371 break;
3372 case DATA_PREFIX_OPCODE:
3373 implied_prefix = 1;
3374 break;
3375 case REPE_PREFIX_OPCODE:
3376 implied_prefix = 2;
3377 break;
3378 case REPNE_PREFIX_OPCODE:
3379 implied_prefix = 3;
3380 break;
3381 default:
3382 abort ();
3383 }
3384
3385 /* Use 2-byte VEX prefix if possible. */
86fa6981
L		 3386 if (i.vec_encoding != vex_encoding_vex3
3387 && i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3388 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3389 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3390 {
3391 /* 2-byte VEX prefix. */
3392 unsigned int r;
3393
3394 i.vex.length = 2;
3395 i.vex.bytes[0] = 0xc5;
3396
3397 /* Check the REX.R bit. */
3398 r = (i.rex & REX_R) ? 0 : 1;
3399 i.vex.bytes[1] = (r << 7
3400 | register_specifier << 3
3401 | vector_length << 2
3402 | implied_prefix);
3403 }
3404 else
3405 {
3406 /* 3-byte VEX prefix. */
3407 unsigned int m, w;
3408
f88c9eb0 3409 i.vex.length = 3;
f88c9eb0 3410
7f399153 3411 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3412 {
7f399153
L		 3413 case VEX0F:
3414 m = 0x1;
80de6e00 3415 i.vex.bytes[0] = 0xc4;
7f399153
L		 3416 break;
3417 case VEX0F38:
3418 m = 0x2;
80de6e00 3419 i.vex.bytes[0] = 0xc4;
7f399153
L		 3420 break;
3421 case VEX0F3A:
3422 m = 0x3;
80de6e00 3423 i.vex.bytes[0] = 0xc4;
7f399153
L		 3424 break;
3425 case XOP08:
5dd85c99
SP		 3426 m = 0x8;
3427 i.vex.bytes[0] = 0x8f;
7f399153
L		 3428 break;
3429 case XOP09:
f88c9eb0
SP		 3430 m = 0x9;
3431 i.vex.bytes[0] = 0x8f;
7f399153
L		 3432 break;
3433 case XOP0A:
f88c9eb0
SP		 3434 m = 0xa;
3435 i.vex.bytes[0] = 0x8f;
7f399153
L		 3436 break;
3437 default:
3438 abort ();
f88c9eb0 3439 }
c0f3af97 3440
c0f3af97
L		 3441 /* The high 3 bits of the second VEX byte are 1's compliment
3442 of RXB bits from REX. */
3443 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3444
3445 /* Check the REX.W bit. */
3446 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3447 if (i.tm.opcode_modifier.vexw == VEXW1)
3448 w = 1;
c0f3af97
L		 3449
3450 i.vex.bytes[2] = (w << 7
3451 | register_specifier << 3
3452 | vector_length << 2
3453 | implied_prefix);
3454 }
3455}
3456
e771e7c9
JB		 3457static INLINE bfd_boolean
3458is_evex_encoding (const insn_template *t)
3459{
3460 return t->opcode_modifier.evex
3461 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3462 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3463}
3464
43234a1e
L		 3465/* Build the EVEX prefix. */
3466
3467static void
3468build_evex_prefix (void)
3469{
3470 unsigned int register_specifier;
3471 unsigned int implied_prefix;
3472 unsigned int m, w;
3473 rex_byte vrex_used = 0;
3474
3475 /* Check register specifier. */
3476 if (i.vex.register_specifier)
3477 {
3478 gas_assert ((i.vrex & REX_X) == 0);
3479
3480 register_specifier = i.vex.register_specifier->reg_num;
3481 if ((i.vex.register_specifier->reg_flags & RegRex))
3482 register_specifier += 8;
3483 /* The upper 16 registers are encoded in the fourth byte of the
3484 EVEX prefix. */
3485 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3486 i.vex.bytes[3] = 0x8;
3487 register_specifier = ~register_specifier & 0xf;
3488 }
3489 else
3490 {
3491 register_specifier = 0xf;
3492
3493 /* Encode upper 16 vector index register in the fourth byte of
3494 the EVEX prefix. */
3495 if (!(i.vrex & REX_X))
3496 i.vex.bytes[3] = 0x8;
3497 else
3498 vrex_used |= REX_X;
3499 }
3500
3501 switch ((i.tm.base_opcode >> 8) & 0xff)
3502 {
3503 case 0:
3504 implied_prefix = 0;
3505 break;
3506 case DATA_PREFIX_OPCODE:
3507 implied_prefix = 1;
3508 break;
3509 case REPE_PREFIX_OPCODE:
3510 implied_prefix = 2;
3511 break;
3512 case REPNE_PREFIX_OPCODE:
3513 implied_prefix = 3;
3514 break;
3515 default:
3516 abort ();
3517 }
3518
3519 /* 4 byte EVEX prefix. */
3520 i.vex.length = 4;
3521 i.vex.bytes[0] = 0x62;
3522
3523 /* mmmm bits. */
3524 switch (i.tm.opcode_modifier.vexopcode)
3525 {
3526 case VEX0F:
3527 m = 1;
3528 break;
3529 case VEX0F38:
3530 m = 2;
3531 break;
3532 case VEX0F3A:
3533 m = 3;
3534 break;
3535 default:
3536 abort ();
3537 break;
3538 }
3539
3540 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3541 bits from REX. */
3542 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3543
3544 /* The fifth bit of the second EVEX byte is 1's compliment of the
3545 REX_R bit in VREX. */
3546 if (!(i.vrex & REX_R))
3547 i.vex.bytes[1] |= 0x10;
3548 else
3549 vrex_used |= REX_R;
3550
3551 if ((i.reg_operands + i.imm_operands) == i.operands)
3552 {
3553 /* When all operands are registers, the REX_X bit in REX is not
3554 used. We reuse it to encode the upper 16 registers, which is
3555 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3556 as 1's compliment. */
3557 if ((i.vrex & REX_B))
3558 {
3559 vrex_used |= REX_B;
3560 i.vex.bytes[1] &= ~0x40;
3561 }
3562 }
3563
3564 /* EVEX instructions shouldn't need the REX prefix. */
3565 i.vrex &= ~vrex_used;
3566 gas_assert (i.vrex == 0);
3567
3568 /* Check the REX.W bit. */
3569 w = (i.rex & REX_W) ? 1 : 0;
3570 if (i.tm.opcode_modifier.vexw)
3571 {
3572 if (i.tm.opcode_modifier.vexw == VEXW1)
3573 w = 1;
3574 }
3575 /* If w is not set it means we are dealing with WIG instruction. */
3576 else if (!w)
3577 {
3578 if (evexwig == evexw1)
3579 w = 1;
3580 }
3581
3582 /* Encode the U bit. */
3583 implied_prefix |= 0x4;
3584
3585 /* The third byte of the EVEX prefix. */
3586 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3587
3588 /* The fourth byte of the EVEX prefix. */
3589 /* The zeroing-masking bit. */
3590 if (i.mask && i.mask->zeroing)
3591 i.vex.bytes[3] |= 0x80;
3592
3593 /* Don't always set the broadcast bit if there is no RC. */
3594 if (!i.rounding)
3595 {
3596 /* Encode the vector length. */
3597 unsigned int vec_length;
3598
e771e7c9
JB		 3599 if (!i.tm.opcode_modifier.evex
3600 || i.tm.opcode_modifier.evex == EVEXDYN)
3601 {
3602 unsigned int op;
3603
3604 vec_length = 0;
3605 for (op = 0; op < i.tm.operands; ++op)
3606 if (i.tm.operand_types[op].bitfield.xmmword
3607 + i.tm.operand_types[op].bitfield.ymmword
3608 + i.tm.operand_types[op].bitfield.zmmword > 1)
3609 {
3610 if (i.types[op].bitfield.zmmword)
3611 i.tm.opcode_modifier.evex = EVEX512;
3612 else if (i.types[op].bitfield.ymmword)
3613 i.tm.opcode_modifier.evex = EVEX256;
3614 else if (i.types[op].bitfield.xmmword)
3615 i.tm.opcode_modifier.evex = EVEX128;
3616 else
3617 continue;
3618 break;
3619 }
3620 }
3621
43234a1e
L		 3622 switch (i.tm.opcode_modifier.evex)
3623 {
3624 case EVEXLIG: /* LL' is ignored */
3625 vec_length = evexlig << 5;
3626 break;
3627 case EVEX128:
3628 vec_length = 0 << 5;
3629 break;
3630 case EVEX256:
3631 vec_length = 1 << 5;
3632 break;
3633 case EVEX512:
3634 vec_length = 2 << 5;
3635 break;
3636 default:
3637 abort ();
3638 break;
3639 }
3640 i.vex.bytes[3] |= vec_length;
3641 /* Encode the broadcast bit. */
3642 if (i.broadcast)
3643 i.vex.bytes[3] |= 0x10;
3644 }
3645 else
3646 {
3647 if (i.rounding->type != saeonly)
3648 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3649 else
d3d3c6db 3650 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3651 }
3652
3653 if (i.mask && i.mask->mask)
3654 i.vex.bytes[3] |= i.mask->mask->reg_num;
3655}
3656
65da13b5
L		 3657static void
3658process_immext (void)
3659{
3660 expressionS *exp;
3661
4c692bc7
JB		 3662 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3663 && i.operands > 0)
65da13b5 3664 {
4c692bc7
JB		 3665 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3666 with an opcode suffix which is coded in the same place as an
3667 8-bit immediate field would be.
3668 Here we check those operands and remove them afterwards. */
65da13b5
L		 3669 unsigned int x;
3670
3671 for (x = 0; x < i.operands; x++)
4c692bc7 3672 if (register_number (i.op[x].regs) != x)
65da13b5 3673 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3674 register_prefix, i.op[x].regs->reg_name, x + 1,
3675 i.tm.name);
3676
3677 i.operands = 0;
65da13b5
L		 3678 }
3679
9916071f
AP		 3680 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3681 {
3682 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3683 suffix which is coded in the same place as an 8-bit immediate
3684 field would be.
3685 Here we check those operands and remove them afterwards. */
3686 unsigned int x;
3687
3688 if (i.operands != 3)
3689 abort();
3690
3691 for (x = 0; x < 2; x++)
3692 if (register_number (i.op[x].regs) != x)
3693 goto bad_register_operand;
3694
3695 /* Check for third operand for mwaitx/monitorx insn. */
3696 if (register_number (i.op[x].regs)
3697 != (x + (i.tm.extension_opcode == 0xfb)))
3698 {
3699bad_register_operand:
3700 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3701 register_prefix, i.op[x].regs->reg_name, x+1,
3702 i.tm.name);
3703 }
3704
3705 i.operands = 0;
3706 }
3707
c0f3af97 3708 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3709 which is coded in the same place as an 8-bit immediate field
3710 would be. Here we fake an 8-bit immediate operand from the
3711 opcode suffix stored in tm.extension_opcode.
3712
c1e679ec 3713 AVX instructions also use this encoding, for some of
c0f3af97 3714 3 argument instructions. */
65da13b5 3715
43234a1e 3716 gas_assert (i.imm_operands <= 1
7ab9ffdd 3717 && (i.operands <= 2
43234a1e 3718 || ((i.tm.opcode_modifier.vex
e771e7c9
JB		 3719 || i.tm.opcode_modifier.vexopcode
3720 || is_evex_encoding (&i.tm))
7ab9ffdd 3721 && i.operands <= 4)));
65da13b5
L		 3722
3723 exp = &im_expressions[i.imm_operands++];
3724 i.op[i.operands].imms = exp;
3725 i.types[i.operands] = imm8;
3726 i.operands++;
3727 exp->X_op = O_constant;
3728 exp->X_add_number = i.tm.extension_opcode;
3729 i.tm.extension_opcode = None;
3730}
3731
42164a71
L		 3732
3733static int
3734check_hle (void)
3735{
3736 switch (i.tm.opcode_modifier.hleprefixok)
3737 {
3738 default:
3739 abort ();
82c2def5 3740 case HLEPrefixNone:
165de32a
L		 3741 as_bad (_("invalid instruction `%s' after `%s'"),
3742 i.tm.name, i.hle_prefix);
42164a71 3743 return 0;
82c2def5 3744 case HLEPrefixLock:
42164a71
L		 3745 if (i.prefix[LOCK_PREFIX])
3746 return 1;
165de32a 3747 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3748 return 0;
82c2def5 3749 case HLEPrefixAny:
42164a71 3750 return 1;
82c2def5 3751 case HLEPrefixRelease:
42164a71
L		 3752 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3753 {
3754 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3755 i.tm.name);
3756 return 0;
3757 }
3758 if (i.mem_operands == 0
3759 || !operand_type_check (i.types[i.operands - 1], anymem))
3760 {
3761 as_bad (_("memory destination needed for instruction `%s'"
3762 " after `xrelease'"), i.tm.name);
3763 return 0;
3764 }
3765 return 1;
3766 }
3767}
3768
b6f8c7c4
L		 3769/* Try the shortest encoding by shortening operand size. */
3770
3771static void
3772optimize_encoding (void)
3773{
3774 int j;
3775
3776 if (optimize_for_space
3777 && i.reg_operands == 1
3778 && i.imm_operands == 1
3779 && !i.types[1].bitfield.byte
3780 && i.op[0].imms->X_op == O_constant
3781 && fits_in_imm7 (i.op[0].imms->X_add_number)
3782 && ((i.tm.base_opcode == 0xa8
3783 && i.tm.extension_opcode == None)
3784 || (i.tm.base_opcode == 0xf6
3785 && i.tm.extension_opcode == 0x0)))
3786 {
3787 /* Optimize: -Os:
3788 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3789 */
3790 unsigned int base_regnum = i.op[1].regs->reg_num;
3791 if (flag_code == CODE_64BIT || base_regnum < 4)
3792 {
3793 i.types[1].bitfield.byte = 1;
3794 /* Ignore the suffix. */
3795 i.suffix = 0;
3796 if (base_regnum >= 4
3797 && !(i.op[1].regs->reg_flags & RegRex))
3798 {
3799 /* Handle SP, BP, SI and DI registers. */
3800 if (i.types[1].bitfield.word)
3801 j = 16;
3802 else if (i.types[1].bitfield.dword)
3803 j = 32;
3804 else
3805 j = 48;
3806 i.op[1].regs -= j;
3807 }
3808 }
3809 }
3810 else if (flag_code == CODE_64BIT
d3d50934
L		 3811 && ((i.types[1].bitfield.qword
3812 && i.reg_operands == 1
b6f8c7c4
L		 3813 && i.imm_operands == 1
3814 && i.op[0].imms->X_op == O_constant
3815 && ((i.tm.base_opcode == 0xb0
3816 && i.tm.extension_opcode == None
3817 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3818 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3819 && (((i.tm.base_opcode == 0x24
3820 || i.tm.base_opcode == 0xa8)
3821 && i.tm.extension_opcode == None)
3822 || (i.tm.base_opcode == 0x80
3823 && i.tm.extension_opcode == 0x4)
3824 || ((i.tm.base_opcode == 0xf6
3825 || i.tm.base_opcode == 0xc6)
3826 && i.tm.extension_opcode == 0x0)))))
d3d50934
L		 3827 || (i.types[0].bitfield.qword
3828 && ((i.reg_operands == 2
3829 && i.op[0].regs == i.op[1].regs
3830 && ((i.tm.base_opcode == 0x30
3831 || i.tm.base_opcode == 0x28)
3832 && i.tm.extension_opcode == None))
3833 || (i.reg_operands == 1
3834 && i.operands == 1
3835 && i.tm.base_opcode == 0x30
3836 && i.tm.extension_opcode == None)))))
b6f8c7c4
L		 3837 {
3838 /* Optimize: -O:
3839 andq $imm31, %r64 -> andl $imm31, %r32
3840 testq $imm31, %r64 -> testl $imm31, %r32
3841 xorq %r64, %r64 -> xorl %r32, %r32
3842 subq %r64, %r64 -> subl %r32, %r32
3843 movq $imm31, %r64 -> movl $imm31, %r32
3844 movq $imm32, %r64 -> movl $imm32, %r32
3845 */
3846 i.tm.opcode_modifier.norex64 = 1;
3847 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3848 {
3849 /* Handle
3850 movq $imm31, %r64 -> movl $imm31, %r32
3851 movq $imm32, %r64 -> movl $imm32, %r32
3852 */
3853 i.tm.operand_types[0].bitfield.imm32 = 1;
3854 i.tm.operand_types[0].bitfield.imm32s = 0;
3855 i.tm.operand_types[0].bitfield.imm64 = 0;
3856 i.types[0].bitfield.imm32 = 1;
3857 i.types[0].bitfield.imm32s = 0;
3858 i.types[0].bitfield.imm64 = 0;
3859 i.types[1].bitfield.dword = 1;
3860 i.types[1].bitfield.qword = 0;
3861 if (i.tm.base_opcode == 0xc6)
3862 {
3863 /* Handle
3864 movq $imm31, %r64 -> movl $imm31, %r32
3865 */
3866 i.tm.base_opcode = 0xb0;
3867 i.tm.extension_opcode = None;
3868 i.tm.opcode_modifier.shortform = 1;
3869 i.tm.opcode_modifier.modrm = 0;
3870 }
3871 }
3872 }
3873 else if (optimize > 1
3874 && i.reg_operands == 3
3875 && i.op[0].regs == i.op[1].regs
3876 && !i.types[2].bitfield.xmmword
3877 && (i.tm.opcode_modifier.vex
3878 || (!i.mask
3879 && !i.rounding
e771e7c9 3880 && is_evex_encoding (&i.tm)
80c34c38
L		 3881 && (i.vec_encoding != vex_encoding_evex
3882 || i.tm.cpu_flags.bitfield.cpuavx512vl
0089dace 3883 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
b6f8c7c4
L		 3884 && ((i.tm.base_opcode == 0x55
3885 || i.tm.base_opcode == 0x6655
3886 || i.tm.base_opcode == 0x66df
3887 || i.tm.base_opcode == 0x57
3888 || i.tm.base_opcode == 0x6657
8305403a
L		 3889 || i.tm.base_opcode == 0x66ef
3890 || i.tm.base_opcode == 0x66f8
3891 || i.tm.base_opcode == 0x66f9
3892 || i.tm.base_opcode == 0x66fa
3893 || i.tm.base_opcode == 0x66fb)
b6f8c7c4
L		 3894 && i.tm.extension_opcode == None))
3895 {
3896 /* Optimize: -O2:
8305403a
L		 3897 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3898 vpsubq and vpsubw:
b6f8c7c4
L		 3899 EVEX VOP %zmmM, %zmmM, %zmmN
3900 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3901 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3902 EVEX VOP %ymmM, %ymmM, %ymmN
3903 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3904 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3905 VEX VOP %ymmM, %ymmM, %ymmN
3906 -> VEX VOP %xmmM, %xmmM, %xmmN
3907 VOP, one of vpandn and vpxor:
3908 VEX VOP %ymmM, %ymmM, %ymmN
3909 -> VEX VOP %xmmM, %xmmM, %xmmN
3910 VOP, one of vpandnd and vpandnq:
3911 EVEX VOP %zmmM, %zmmM, %zmmN
3912 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3913 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3914 EVEX VOP %ymmM, %ymmM, %ymmN
3915 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3916 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3917 VOP, one of vpxord and vpxorq:
3918 EVEX VOP %zmmM, %zmmM, %zmmN
3919 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3920 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3921 EVEX VOP %ymmM, %ymmM, %ymmN
3922 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3923 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3924 */
e771e7c9 3925 if (is_evex_encoding (&i.tm))
b6f8c7c4 3926 {
0089dace 3927 if (i.vec_encoding == vex_encoding_evex)
b6f8c7c4
L		 3928 i.tm.opcode_modifier.evex = EVEX128;
3929 else
3930 {
3931 i.tm.opcode_modifier.vex = VEX128;
3932 i.tm.opcode_modifier.vexw = VEXW0;
3933 i.tm.opcode_modifier.evex = 0;
3934 }
3935 }
3936 else
3937 i.tm.opcode_modifier.vex = VEX128;
3938
3939 if (i.tm.opcode_modifier.vex)
3940 for (j = 0; j < 3; j++)
3941 {
3942 i.types[j].bitfield.xmmword = 1;
3943 i.types[j].bitfield.ymmword = 0;
3944 }
3945 }
3946}
3947
252b5132
RH		 3948/* This is the guts of the machine-dependent assembler. LINE points to a
3949 machine dependent instruction. This function is supposed to emit
3950 the frags/bytes it assembles to. */
3951
3952void
65da13b5 3953md_assemble (char *line)
252b5132 3954{
40fb9820 3955 unsigned int j;
83b16ac6 3956 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3957 const insn_template *t;
252b5132 3958
47926f60 3959 /* Initialize globals. */
252b5132
RH		 3960 memset (&i, '\0', sizeof (i));
3961 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3962 i.reloc[j] = NO_RELOC;
252b5132
RH		 3963 memset (disp_expressions, '\0', sizeof (disp_expressions));
3964 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3965 save_stack_p = save_stack;
252b5132
RH		 3966
3967 /* First parse an instruction mnemonic & call i386_operand for the operands.
3968 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3969 start of a (possibly prefixed) mnemonic. */
252b5132 3970
29b0f896
AM		 3971 line = parse_insn (line, mnemonic);
3972 if (line == NULL)
3973 return;
83b16ac6 3974 mnem_suffix = i.suffix;
252b5132 3975
29b0f896 3976 line = parse_operands (line, mnemonic);
ee86248c 3977 this_operand = -1;
8325cc63
JB		 3978 xfree (i.memop1_string);
3979 i.memop1_string = NULL;
29b0f896
AM		 3980 if (line == NULL)
3981 return;
252b5132 3982
29b0f896
AM		 3983 /* Now we've parsed the mnemonic into a set of templates, and have the
3984 operands at hand. */
3985
3986 /* All intel opcodes have reversed operands except for "bound" and
3987 "enter". We also don't reverse intersegment "jmp" and "call"
3988 instructions with 2 immediate operands so that the immediate segment
050dfa73 3989 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3990 if (intel_syntax
3991 && i.operands > 1
29b0f896 3992 && (strcmp (mnemonic, "bound") != 0)
30123838 3993 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3994 && !(operand_type_check (i.types[0], imm)
3995 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3996 swap_operands ();
3997
ec56d5c0
JB		 3998 /* The order of the immediates should be reversed
3999 for 2 immediates extrq and insertq instructions */
4000 if (i.imm_operands == 2
4001 && (strcmp (mnemonic, "extrq") == 0
4002 || strcmp (mnemonic, "insertq") == 0))
4003 swap_2_operands (0, 1);
4004
29b0f896
AM		 4005 if (i.imm_operands)
4006 optimize_imm ();
4007
b300c311
L		 4008 /* Don't optimize displacement for movabs since it only takes 64bit
4009 displacement. */
4010 if (i.disp_operands
a501d77e 4011 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 4012 && (flag_code != CODE_64BIT
4013 || strcmp (mnemonic, "movabs") != 0))
4014 optimize_disp ();
29b0f896
AM		 4015
4016 /* Next, we find a template that matches the given insn,
4017 making sure the overlap of the given operands types is consistent
4018 with the template operand types. */
252b5132 4019
83b16ac6 4020 if (!(t = match_template (mnem_suffix)))
29b0f896 4021 return;
252b5132 4022
7bab8ab5 4023 if (sse_check != check_none
81f8a913 4024 && !i.tm.opcode_modifier.noavx
6e3e5c9e 4025 && !i.tm.cpu_flags.bitfield.cpuavx
daf50ae7
L		 4026 && (i.tm.cpu_flags.bitfield.cpusse
4027 || i.tm.cpu_flags.bitfield.cpusse2
4028 || i.tm.cpu_flags.bitfield.cpusse3
4029 || i.tm.cpu_flags.bitfield.cpussse3
4030 || i.tm.cpu_flags.bitfield.cpusse4_1
6e3e5c9e
JB		 4031 || i.tm.cpu_flags.bitfield.cpusse4_2
4032 || i.tm.cpu_flags.bitfield.cpupclmul
4033 || i.tm.cpu_flags.bitfield.cpuaes
4034 || i.tm.cpu_flags.bitfield.cpugfni))
daf50ae7 4035 {
7bab8ab5 4036 (sse_check == check_warning
daf50ae7
L		 4037 ? as_warn
4038 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4039 }
4040
321fd21e
L		 4041 /* Zap movzx and movsx suffix. The suffix has been set from
4042 "word ptr" or "byte ptr" on the source operand in Intel syntax
4043 or extracted from mnemonic in AT&T syntax. But we'll use
4044 the destination register to choose the suffix for encoding. */
4045 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 4046 {
321fd21e
L		 4047 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4048 there is no suffix, the default will be byte extension. */
4049 if (i.reg_operands != 2
4050 && !i.suffix
7ab9ffdd 4051 && intel_syntax)
321fd21e
L		 4052 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4053
4054 i.suffix = 0;
cd61ebfe 4055 }
24eab124 4056
40fb9820 4057 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 4058 if (!add_prefix (FWAIT_OPCODE))
4059 return;
252b5132 4060
d5de92cf
L		 4061 /* Check if REP prefix is OK. */
4062 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4063 {
4064 as_bad (_("invalid instruction `%s' after `%s'"),
4065 i.tm.name, i.rep_prefix);
4066 return;
4067 }
4068
c1ba0266
L		 4069 /* Check for lock without a lockable instruction. Destination operand
4070 must be memory unless it is xchg (0x86). */
c32fa91d
L		 4071 if (i.prefix[LOCK_PREFIX]
4072 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 4073 || i.mem_operands == 0
4074 || (i.tm.base_opcode != 0x86
4075 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 4076 {
4077 as_bad (_("expecting lockable instruction after `lock'"));
4078 return;
4079 }
4080
42164a71 4081 /* Check if HLE prefix is OK. */
165de32a 4082 if (i.hle_prefix && !check_hle ())
42164a71
L		 4083 return;
4084
7e8b059b
L		 4085 /* Check BND prefix. */
4086 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4087 as_bad (_("expecting valid branch instruction after `bnd'"));
4088
04ef582a 4089 /* Check NOTRACK prefix. */
9fef80d6
L		 4090 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4091 as_bad (_("expecting indirect branch instruction after `notrack'"));
04ef582a 4092
327e8c42
JB		 4093 if (i.tm.cpu_flags.bitfield.cpumpx)
4094 {
4095 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4096 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4097 else if (flag_code != CODE_16BIT
4098 ? i.prefix[ADDR_PREFIX]
4099 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4100 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4101 }
7e8b059b
L		 4102
4103 /* Insert BND prefix. */
4104 if (add_bnd_prefix
4105 && i.tm.opcode_modifier.bndprefixok
4106 && !i.prefix[BND_PREFIX])
4107 add_prefix (BND_PREFIX_OPCODE);
4108
29b0f896 4109 /* Check string instruction segment overrides. */
40fb9820 4110 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 4111 {
4112 if (!check_string ())
5dd0794d 4113 return;
fc0763e6 4114 i.disp_operands = 0;
29b0f896 4115 }
5dd0794d 4116
b6f8c7c4
L		 4117 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4118 optimize_encoding ();
4119
29b0f896
AM		 4120 if (!process_suffix ())
4121 return;
e413e4e9 4122
bc0844ae
L		 4123 /* Update operand types. */
4124 for (j = 0; j < i.operands; j++)
4125 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4126
29b0f896
AM		 4127 /* Make still unresolved immediate matches conform to size of immediate
4128 given in i.suffix. */
4129 if (!finalize_imm ())
4130 return;
252b5132 4131
40fb9820 4132 if (i.types[0].bitfield.imm1)
29b0f896 4133 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 4134
9afe6eb8
L		 4135 /* We only need to check those implicit registers for instructions
4136 with 3 operands or less. */
4137 if (i.operands <= 3)
4138 for (j = 0; j < i.operands; j++)
4139 if (i.types[j].bitfield.inoutportreg
4140 || i.types[j].bitfield.shiftcount
1b54b8d7 4141 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
9afe6eb8 4142 i.reg_operands--;
40fb9820 4143
c0f3af97
L		 4144 /* ImmExt should be processed after SSE2AVX. */
4145 if (!i.tm.opcode_modifier.sse2avx
4146 && i.tm.opcode_modifier.immext)
65da13b5 4147 process_immext ();
252b5132 4148
29b0f896
AM		 4149 /* For insns with operands there are more diddles to do to the opcode. */
4150 if (i.operands)
4151 {
4152 if (!process_operands ())
4153 return;
4154 }
40fb9820 4155 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 4156 {
4157 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4158 as_warn (_("translating to `%sp'"), i.tm.name);
4159 }
252b5132 4160
e771e7c9
JB		 4161 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4162 || is_evex_encoding (&i.tm))
9e5e5283
L		 4163 {
4164 if (flag_code == CODE_16BIT)
4165 {
4166 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4167 i.tm.name);
4168 return;
4169 }
c0f3af97 4170
9e5e5283
L		 4171 if (i.tm.opcode_modifier.vex)
4172 build_vex_prefix (t);
4173 else
4174 build_evex_prefix ();
4175 }
43234a1e 4176
5dd85c99
SP		 4177 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4178 instructions may define INT_OPCODE as well, so avoid this corner
4179 case for those instructions that use MODRM. */
4180 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 4181 && !i.tm.opcode_modifier.modrm
4182 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 4183 {
4184 i.tm.base_opcode = INT3_OPCODE;
4185 i.imm_operands = 0;
4186 }
252b5132 4187
40fb9820
L		 4188 if ((i.tm.opcode_modifier.jump
4189 || i.tm.opcode_modifier.jumpbyte
4190 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 4191 && i.op[0].disps->X_op == O_constant)
4192 {
4193 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4194 the absolute address given by the constant. Since ix86 jumps and
4195 calls are pc relative, we need to generate a reloc. */
4196 i.op[0].disps->X_add_symbol = &abs_symbol;
4197 i.op[0].disps->X_op = O_symbol;
4198 }
252b5132 4199
40fb9820 4200 if (i.tm.opcode_modifier.rex64)
161a04f6 4201 i.rex |= REX_W;
252b5132 4202
29b0f896
AM		 4203 /* For 8 bit registers we need an empty rex prefix. Also if the
4204 instruction already has a prefix, we need to convert old
4205 registers to new ones. */
773f551c 4206
dc821c5f 4207 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
29b0f896 4208 && (i.op[0].regs->reg_flags & RegRex64) != 0)
dc821c5f 4209 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
29b0f896 4210 && (i.op[1].regs->reg_flags & RegRex64) != 0)
dc821c5f
JB		 4211 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4212 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
29b0f896
AM		 4213 && i.rex != 0))
4214 {
4215 int x;
726c5dcd 4216
29b0f896
AM		 4217 i.rex |= REX_OPCODE;
4218 for (x = 0; x < 2; x++)
4219 {
4220 /* Look for 8 bit operand that uses old registers. */
dc821c5f 4221 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
29b0f896 4222 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 4223 {
29b0f896
AM		 4224 /* In case it is "hi" register, give up. */
4225 if (i.op[x].regs->reg_num > 3)
a540244d 4226 as_bad (_("can't encode register '%s%s' in an "
4eed87de 4227 "instruction requiring REX prefix."),
a540244d 4228 register_prefix, i.op[x].regs->reg_name);
773f551c 4229
29b0f896
AM		 4230 /* Otherwise it is equivalent to the extended register.
4231 Since the encoding doesn't change this is merely
4232 cosmetic cleanup for debug output. */
4233
4234 i.op[x].regs = i.op[x].regs + 8;
773f551c 4235 }
29b0f896
AM		 4236 }
4237 }
773f551c 4238
6b6b6807
L		 4239 if (i.rex == 0 && i.rex_encoding)
4240 {
4241 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4242 that uses legacy register. If it is "hi" register, don't add
4243 the REX_OPCODE byte. */
4244 int x;
4245 for (x = 0; x < 2; x++)
4246 if (i.types[x].bitfield.reg
4247 && i.types[x].bitfield.byte
4248 && (i.op[x].regs->reg_flags & RegRex64) == 0
4249 && i.op[x].regs->reg_num > 3)
4250 {
4251 i.rex_encoding = FALSE;
4252 break;
4253 }
4254
4255 if (i.rex_encoding)
4256 i.rex = REX_OPCODE;
4257 }
4258
7ab9ffdd 4259 if (i.rex != 0)
29b0f896
AM		 4260 add_prefix (REX_OPCODE | i.rex);
4261
4262 /* We are ready to output the insn. */
4263 output_insn ();
4264}
4265
4266static char *
e3bb37b5 4267parse_insn (char *line, char *mnemonic)
29b0f896
AM		 4268{
4269 char *l = line;
4270 char *token_start = l;
4271 char *mnem_p;
5c6af06e 4272 int supported;
d3ce72d0 4273 const insn_template *t;
b6169b20 4274 char *dot_p = NULL;
29b0f896 4275
29b0f896
AM		 4276 while (1)
4277 {
4278 mnem_p = mnemonic;
4279 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4280 {
b6169b20
L		 4281 if (*mnem_p == '.')
4282 dot_p = mnem_p;
29b0f896
AM		 4283 mnem_p++;
4284 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 4285 {
29b0f896
AM		 4286 as_bad (_("no such instruction: `%s'"), token_start);
4287 return NULL;
4288 }
4289 l++;
4290 }
4291 if (!is_space_char (*l)
4292 && *l != END_OF_INSN
e44823cf
JB		 4293 && (intel_syntax
4294 || (*l != PREFIX_SEPARATOR
4295 && *l != ',')))
29b0f896
AM		 4296 {
4297 as_bad (_("invalid character %s in mnemonic"),
4298 output_invalid (*l));
4299 return NULL;
4300 }
4301 if (token_start == l)
4302 {
e44823cf 4303 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 4304 as_bad (_("expecting prefix; got nothing"));
4305 else
4306 as_bad (_("expecting mnemonic; got nothing"));
4307 return NULL;
4308 }
45288df1 4309
29b0f896 4310 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 4311 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 4312
29b0f896
AM		 4313 if (*l != END_OF_INSN
4314 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4315 && current_templates
40fb9820 4316 && current_templates->start->opcode_modifier.isprefix)
29b0f896 4317 {
c6fb90c8 4318 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 4319 {
4320 as_bad ((flag_code != CODE_64BIT
4321 ? _("`%s' is only supported in 64-bit mode")
4322 : _("`%s' is not supported in 64-bit mode")),
4323 current_templates->start->name);
4324 return NULL;
4325 }
29b0f896
AM		 4326 /* If we are in 16-bit mode, do not allow addr16 or data16.
4327 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 4328 if ((current_templates->start->opcode_modifier.size16
4329 || current_templates->start->opcode_modifier.size32)
29b0f896 4330 && flag_code != CODE_64BIT
40fb9820 4331 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 4332 ^ (flag_code == CODE_16BIT)))
4333 {
4334 as_bad (_("redundant %s prefix"),
4335 current_templates->start->name);
4336 return NULL;
45288df1 4337 }
86fa6981 4338 if (current_templates->start->opcode_length == 0)
29b0f896 4339 {
86fa6981
L		 4340 /* Handle pseudo prefixes. */
4341 switch (current_templates->start->base_opcode)
4342 {
4343 case 0x0:
4344 /* {disp8} */
4345 i.disp_encoding = disp_encoding_8bit;
4346 break;
4347 case 0x1:
4348 /* {disp32} */
4349 i.disp_encoding = disp_encoding_32bit;
4350 break;
4351 case 0x2:
4352 /* {load} */
4353 i.dir_encoding = dir_encoding_load;
4354 break;
4355 case 0x3:
4356 /* {store} */
4357 i.dir_encoding = dir_encoding_store;
4358 break;
4359 case 0x4:
4360 /* {vex2} */
4361 i.vec_encoding = vex_encoding_vex2;
4362 break;
4363 case 0x5:
4364 /* {vex3} */
4365 i.vec_encoding = vex_encoding_vex3;
4366 break;
4367 case 0x6:
4368 /* {evex} */
4369 i.vec_encoding = vex_encoding_evex;
4370 break;
6b6b6807
L		 4371 case 0x7:
4372 /* {rex} */
4373 i.rex_encoding = TRUE;
4374 break;
b6f8c7c4
L		 4375 case 0x8:
4376 /* {nooptimize} */
4377 i.no_optimize = TRUE;
4378 break;
86fa6981
L		 4379 default:
4380 abort ();
4381 }
4382 }
4383 else
4384 {
4385 /* Add prefix, checking for repeated prefixes. */
4e9ac44a 4386 switch (add_prefix (current_templates->start->base_opcode))
86fa6981 4387 {
4e9ac44a
L		 4388 case PREFIX_EXIST:
4389 return NULL;
4390 case PREFIX_DS:
d777820b 4391 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4e9ac44a
L		 4392 i.notrack_prefix = current_templates->start->name;
4393 break;
4394 case PREFIX_REP:
4395 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4396 i.hle_prefix = current_templates->start->name;
4397 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4398 i.bnd_prefix = current_templates->start->name;
4399 else
4400 i.rep_prefix = current_templates->start->name;
4401 break;
4402 default:
4403 break;
86fa6981 4404 }
29b0f896
AM		 4405 }
4406 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4407 token_start = ++l;
4408 }
4409 else
4410 break;
4411 }
45288df1 4412
30a55f88 4413 if (!current_templates)
b6169b20 4414 {
f8a5c266
L		 4415 /* Check if we should swap operand or force 32bit displacement in
4416 encoding. */
30a55f88 4417 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
86fa6981 4418 i.dir_encoding = dir_encoding_store;
8d63c93e 4419 else if (mnem_p - 3 == dot_p
a501d77e
L		 4420 && dot_p[1] == 'd'
4421 && dot_p[2] == '8')
4422 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4423 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4424 && dot_p[1] == 'd'
4425 && dot_p[2] == '3'
4426 && dot_p[3] == '2')
a501d77e 4427 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4428 else
4429 goto check_suffix;
4430 mnem_p = dot_p;
4431 *dot_p = '\0';
d3ce72d0 4432 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4433 }
4434
29b0f896
AM		 4435 if (!current_templates)
4436 {
b6169b20 4437check_suffix:
29b0f896
AM		 4438 /* See if we can get a match by trimming off a suffix. */
4439 switch (mnem_p[-1])
4440 {
4441 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 4442 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4443 i.suffix = SHORT_MNEM_SUFFIX;
4444 else
1a0670f3 4445 /* Fall through. */
29b0f896
AM		 4446 case BYTE_MNEM_SUFFIX:
4447 case QWORD_MNEM_SUFFIX:
4448 i.suffix = mnem_p[-1];
4449 mnem_p[-1] = '\0';
d3ce72d0
NC		 4450 current_templates = (const templates *) hash_find (op_hash,
4451 mnemonic);
29b0f896
AM		 4452 break;
4453 case SHORT_MNEM_SUFFIX:
4454 case LONG_MNEM_SUFFIX:
4455 if (!intel_syntax)
4456 {
4457 i.suffix = mnem_p[-1];
4458 mnem_p[-1] = '\0';
d3ce72d0
NC		 4459 current_templates = (const templates *) hash_find (op_hash,
4460 mnemonic);
29b0f896
AM		 4461 }
4462 break;
252b5132 4463
29b0f896
AM		 4464 /* Intel Syntax. */
4465 case 'd':
4466 if (intel_syntax)
4467 {
9306ca4a 4468 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 4469 i.suffix = SHORT_MNEM_SUFFIX;
4470 else
4471 i.suffix = LONG_MNEM_SUFFIX;
4472 mnem_p[-1] = '\0';
d3ce72d0
NC		 4473 current_templates = (const templates *) hash_find (op_hash,
4474 mnemonic);
29b0f896
AM		 4475 }
4476 break;
4477 }
4478 if (!current_templates)
4479 {
4480 as_bad (_("no such instruction: `%s'"), token_start);
4481 return NULL;
4482 }
4483 }
252b5132 4484
40fb9820
L		 4485 if (current_templates->start->opcode_modifier.jump
4486 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4487 {
4488 /* Check for a branch hint. We allow ",pt" and ",pn" for
4489 predict taken and predict not taken respectively.
4490 I'm not sure that branch hints actually do anything on loop
4491 and jcxz insns (JumpByte) for current Pentium4 chips. They
4492 may work in the future and it doesn't hurt to accept them
4493 now. */
4494 if (l[0] == ',' && l[1] == 'p')
4495 {
4496 if (l[2] == 't')
4497 {
4498 if (!add_prefix (DS_PREFIX_OPCODE))
4499 return NULL;
4500 l += 3;
4501 }
4502 else if (l[2] == 'n')
4503 {
4504 if (!add_prefix (CS_PREFIX_OPCODE))
4505 return NULL;
4506 l += 3;
4507 }
4508 }
4509 }
4510 /* Any other comma loses. */
4511 if (*l == ',')
4512 {
4513 as_bad (_("invalid character %s in mnemonic"),
4514 output_invalid (*l));
4515 return NULL;
4516 }
252b5132 4517
29b0f896 4518 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4519 supported = 0;
4520 for (t = current_templates->start; t < current_templates->end; ++t)
4521 {
c0f3af97
L		 4522 supported |= cpu_flags_match (t);
4523 if (supported == CPU_FLAGS_PERFECT_MATCH)
548d0ee6
JB		 4524 {
4525 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4526 as_warn (_("use .code16 to ensure correct addressing mode"));
3629bb00 4527
548d0ee6
JB		 4528 return l;
4529 }
29b0f896 4530 }
3629bb00 4531
548d0ee6
JB		 4532 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4533 as_bad (flag_code == CODE_64BIT
4534 ? _("`%s' is not supported in 64-bit mode")
4535 : _("`%s' is only supported in 64-bit mode"),
4536 current_templates->start->name);
4537 else
4538 as_bad (_("`%s' is not supported on `%s%s'"),
4539 current_templates->start->name,
4540 cpu_arch_name ? cpu_arch_name : default_arch,
4541 cpu_sub_arch_name ? cpu_sub_arch_name : "");
252b5132 4542
548d0ee6 4543 return NULL;
29b0f896 4544}
252b5132 4545
29b0f896 4546static char *
e3bb37b5 4547parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4548{
4549 char *token_start;
3138f287 4550
29b0f896
AM		 4551 /* 1 if operand is pending after ','. */
4552 unsigned int expecting_operand = 0;
252b5132 4553
29b0f896
AM		 4554 /* Non-zero if operand parens not balanced. */
4555 unsigned int paren_not_balanced;
4556
4557 while (*l != END_OF_INSN)
4558 {
4559 /* Skip optional white space before operand. */
4560 if (is_space_char (*l))
4561 ++l;
d02603dc 4562 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4563 {
4564 as_bad (_("invalid character %s before operand %d"),
4565 output_invalid (*l),
4566 i.operands + 1);
4567 return NULL;
4568 }
d02603dc 4569 token_start = l; /* After white space. */
29b0f896
AM		 4570 paren_not_balanced = 0;
4571 while (paren_not_balanced || *l != ',')
4572 {
4573 if (*l == END_OF_INSN)
4574 {
4575 if (paren_not_balanced)
4576 {
4577 if (!intel_syntax)
4578 as_bad (_("unbalanced parenthesis in operand %d."),
4579 i.operands + 1);
4580 else
4581 as_bad (_("unbalanced brackets in operand %d."),
4582 i.operands + 1);
4583 return NULL;
4584 }
4585 else
4586 break; /* we are done */
4587 }
d02603dc 4588 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4589 {
4590 as_bad (_("invalid character %s in operand %d"),
4591 output_invalid (*l),
4592 i.operands + 1);
4593 return NULL;
4594 }
4595 if (!intel_syntax)
4596 {
4597 if (*l == '(')
4598 ++paren_not_balanced;
4599 if (*l == ')')
4600 --paren_not_balanced;
4601 }
4602 else
4603 {
4604 if (*l == '[')
4605 ++paren_not_balanced;
4606 if (*l == ']')
4607 --paren_not_balanced;
4608 }
4609 l++;
4610 }
4611 if (l != token_start)
4612 { /* Yes, we've read in another operand. */
4613 unsigned int operand_ok;
4614 this_operand = i.operands++;
4615 if (i.operands > MAX_OPERANDS)
4616 {
4617 as_bad (_("spurious operands; (%d operands/instruction max)"),
4618 MAX_OPERANDS);
4619 return NULL;
4620 }
9d46ce34 4621 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4622 /* Now parse operand adding info to 'i' as we go along. */
4623 END_STRING_AND_SAVE (l);
4624
4625 if (intel_syntax)
4626 operand_ok =
4627 i386_intel_operand (token_start,
4628 intel_float_operand (mnemonic));
4629 else
a7619375 4630 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4631
4632 RESTORE_END_STRING (l);
4633 if (!operand_ok)
4634 return NULL;
4635 }
4636 else
4637 {
4638 if (expecting_operand)
4639 {
4640 expecting_operand_after_comma:
4641 as_bad (_("expecting operand after ','; got nothing"));
4642 return NULL;
4643 }
4644 if (*l == ',')
4645 {
4646 as_bad (_("expecting operand before ','; got nothing"));
4647 return NULL;
4648 }
4649 }
7f3f1ea2 4650
29b0f896
AM		 4651 /* Now *l must be either ',' or END_OF_INSN. */
4652 if (*l == ',')
4653 {
4654 if (*++l == END_OF_INSN)
4655 {
4656 /* Just skip it, if it's \n complain. */
4657 goto expecting_operand_after_comma;
4658 }
4659 expecting_operand = 1;
4660 }
4661 }
4662 return l;
4663}
7f3f1ea2 4664
050dfa73 4665static void
4d456e3d 4666swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4667{
4668 union i386_op temp_op;
40fb9820 4669 i386_operand_type temp_type;
050dfa73 4670 enum bfd_reloc_code_real temp_reloc;
4eed87de 4671
050dfa73
MM		 4672 temp_type = i.types[xchg2];
4673 i.types[xchg2] = i.types[xchg1];
4674 i.types[xchg1] = temp_type;
4675 temp_op = i.op[xchg2];
4676 i.op[xchg2] = i.op[xchg1];
4677 i.op[xchg1] = temp_op;
4678 temp_reloc = i.reloc[xchg2];
4679 i.reloc[xchg2] = i.reloc[xchg1];
4680 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4681
4682 if (i.mask)
4683 {
4684 if (i.mask->operand == xchg1)
4685 i.mask->operand = xchg2;
4686 else if (i.mask->operand == xchg2)
4687 i.mask->operand = xchg1;
4688 }
4689 if (i.broadcast)
4690 {
4691 if (i.broadcast->operand == xchg1)
4692 i.broadcast->operand = xchg2;
4693 else if (i.broadcast->operand == xchg2)
4694 i.broadcast->operand = xchg1;
4695 }
4696 if (i.rounding)
4697 {
4698 if (i.rounding->operand == xchg1)
4699 i.rounding->operand = xchg2;
4700 else if (i.rounding->operand == xchg2)
4701 i.rounding->operand = xchg1;
4702 }
050dfa73
MM		 4703}
4704
29b0f896 4705static void
e3bb37b5 4706swap_operands (void)
29b0f896 4707{
b7c61d9a 4708 switch (i.operands)
050dfa73 4709 {
c0f3af97 4710 case 5:
b7c61d9a 4711 case 4:
4d456e3d 4712 swap_2_operands (1, i.operands - 2);
1a0670f3 4713 /* Fall through. */
b7c61d9a
L		 4714 case 3:
4715 case 2:
4d456e3d 4716 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4717 break;
4718 default:
4719 abort ();
29b0f896 4720 }
29b0f896
AM		 4721
4722 if (i.mem_operands == 2)
4723 {
4724 const seg_entry *temp_seg;
4725 temp_seg = i.seg[0];
4726 i.seg[0] = i.seg[1];
4727 i.seg[1] = temp_seg;
4728 }
4729}
252b5132 4730
29b0f896
AM		 4731/* Try to ensure constant immediates are represented in the smallest
4732 opcode possible. */
4733static void
e3bb37b5 4734optimize_imm (void)
29b0f896
AM		 4735{
4736 char guess_suffix = 0;
4737 int op;
252b5132 4738
29b0f896
AM		 4739 if (i.suffix)
4740 guess_suffix = i.suffix;
4741 else if (i.reg_operands)
4742 {
4743 /* Figure out a suffix from the last register operand specified.
4744 We can't do this properly yet, ie. excluding InOutPortReg,
4745 but the following works for instructions with immediates.
4746 In any case, we can't set i.suffix yet. */
4747 for (op = i.operands; --op >= 0;)
dc821c5f 4748 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
7ab9ffdd 4749 {
40fb9820
L		 4750 guess_suffix = BYTE_MNEM_SUFFIX;
4751 break;
4752 }
dc821c5f 4753 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
252b5132 4754 {
40fb9820
L		 4755 guess_suffix = WORD_MNEM_SUFFIX;
4756 break;
4757 }
dc821c5f 4758 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
40fb9820
L		 4759 {
4760 guess_suffix = LONG_MNEM_SUFFIX;
4761 break;
4762 }
dc821c5f 4763 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
40fb9820
L		 4764 {
4765 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4766 break;
252b5132 4767 }
29b0f896
AM		 4768 }
4769 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4770 guess_suffix = WORD_MNEM_SUFFIX;
4771
4772 for (op = i.operands; --op >= 0;)
40fb9820 4773 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4774 {
4775 switch (i.op[op].imms->X_op)
252b5132 4776 {
29b0f896
AM		 4777 case O_constant:
4778 /* If a suffix is given, this operand may be shortened. */
4779 switch (guess_suffix)
252b5132 4780 {
29b0f896 4781 case LONG_MNEM_SUFFIX:
40fb9820
L		 4782 i.types[op].bitfield.imm32 = 1;
4783 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4784 break;
4785 case WORD_MNEM_SUFFIX:
40fb9820
L		 4786 i.types[op].bitfield.imm16 = 1;
4787 i.types[op].bitfield.imm32 = 1;
4788 i.types[op].bitfield.imm32s = 1;
4789 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4790 break;
4791 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4792 i.types[op].bitfield.imm8 = 1;
4793 i.types[op].bitfield.imm8s = 1;
4794 i.types[op].bitfield.imm16 = 1;
4795 i.types[op].bitfield.imm32 = 1;
4796 i.types[op].bitfield.imm32s = 1;
4797 i.types[op].bitfield.imm64 = 1;
29b0f896 4798 break;
252b5132 4799 }
252b5132 4800
29b0f896
AM		 4801 /* If this operand is at most 16 bits, convert it
4802 to a signed 16 bit number before trying to see
4803 whether it will fit in an even smaller size.
4804 This allows a 16-bit operand such as $0xffe0 to
4805 be recognised as within Imm8S range. */
40fb9820 4806 if ((i.types[op].bitfield.imm16)
29b0f896 4807 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4808 {
29b0f896
AM		 4809 i.op[op].imms->X_add_number =
4810 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4811 }
a28def75
L		 4812#ifdef BFD64
4813 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4814 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4815 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4816 == 0))
4817 {
4818 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4819 ^ ((offsetT) 1 << 31))
4820 - ((offsetT) 1 << 31));
4821 }
a28def75 4822#endif
40fb9820 4823 i.types[op]
c6fb90c8
L		 4824 = operand_type_or (i.types[op],
4825 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4826
29b0f896
AM		 4827 /* We must avoid matching of Imm32 templates when 64bit
4828 only immediate is available. */
4829 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4830 i.types[op].bitfield.imm32 = 0;
29b0f896 4831 break;
252b5132 4832
29b0f896
AM		 4833 case O_absent:
4834 case O_register:
4835 abort ();
4836
4837 /* Symbols and expressions. */
4838 default:
9cd96992
JB		 4839 /* Convert symbolic operand to proper sizes for matching, but don't
4840 prevent matching a set of insns that only supports sizes other
4841 than those matching the insn suffix. */
4842 {
40fb9820 4843 i386_operand_type mask, allowed;
d3ce72d0 4844 const insn_template *t;
9cd96992 4845
0dfbf9d7
L		 4846 operand_type_set (&mask, 0);
4847 operand_type_set (&allowed, 0);
40fb9820 4848
4eed87de
AM		 4849 for (t = current_templates->start;
4850 t < current_templates->end;
4851 ++t)
c6fb90c8
L		 4852 allowed = operand_type_or (allowed,
4853 t->operand_types[op]);
9cd96992
JB		 4854 switch (guess_suffix)
4855 {
4856 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4857 mask.bitfield.imm64 = 1;
4858 mask.bitfield.imm32s = 1;
9cd96992
JB		 4859 break;
4860 case LONG_MNEM_SUFFIX:
40fb9820 4861 mask.bitfield.imm32 = 1;
9cd96992
JB		 4862 break;
4863 case WORD_MNEM_SUFFIX:
40fb9820 4864 mask.bitfield.imm16 = 1;
9cd96992
JB		 4865 break;
4866 case BYTE_MNEM_SUFFIX:
40fb9820 4867 mask.bitfield.imm8 = 1;
9cd96992
JB		 4868 break;
4869 default:
9cd96992
JB		 4870 break;
4871 }
c6fb90c8 4872 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4873 if (!operand_type_all_zero (&allowed))
c6fb90c8 4874 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4875 }
29b0f896 4876 break;
252b5132 4877 }
29b0f896
AM		 4878 }
4879}
47926f60 4880
29b0f896
AM		 4881/* Try to use the smallest displacement type too. */
4882static void
e3bb37b5 4883optimize_disp (void)
29b0f896
AM		 4884{
4885 int op;
3e73aa7c 4886
29b0f896 4887 for (op = i.operands; --op >= 0;)
40fb9820 4888 if (operand_type_check (i.types[op], disp))
252b5132 4889 {
b300c311 4890 if (i.op[op].disps->X_op == O_constant)
252b5132 4891 {
91d6fa6a 4892 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4893
40fb9820 4894 if (i.types[op].bitfield.disp16
91d6fa6a 4895 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4896 {
4897 /* If this operand is at most 16 bits, convert
4898 to a signed 16 bit number and don't use 64bit
4899 displacement. */
91d6fa6a 4900 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4901 i.types[op].bitfield.disp64 = 0;
b300c311 4902 }
a28def75
L		 4903#ifdef BFD64
4904 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4905 if (i.types[op].bitfield.disp32
91d6fa6a 4906 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4907 {
4908 /* If this operand is at most 32 bits, convert
4909 to a signed 32 bit number and don't use 64bit
4910 displacement. */
91d6fa6a
NC		 4911 op_disp &= (((offsetT) 2 << 31) - 1);
4912 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4913 i.types[op].bitfield.disp64 = 0;
b300c311 4914 }
a28def75 4915#endif
91d6fa6a 4916 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4917 {
40fb9820
L		 4918 i.types[op].bitfield.disp8 = 0;
4919 i.types[op].bitfield.disp16 = 0;
4920 i.types[op].bitfield.disp32 = 0;
4921 i.types[op].bitfield.disp32s = 0;
4922 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4923 i.op[op].disps = 0;
4924 i.disp_operands--;
4925 }
4926 else if (flag_code == CODE_64BIT)
4927 {
91d6fa6a 4928 if (fits_in_signed_long (op_disp))
28a9d8f5 4929 {
40fb9820
L		 4930 i.types[op].bitfield.disp64 = 0;
4931 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4932 }
0e1147d9 4933 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4934 && fits_in_unsigned_long (op_disp))
40fb9820 4935 i.types[op].bitfield.disp32 = 1;
b300c311 4936 }
40fb9820
L		 4937 if ((i.types[op].bitfield.disp32
4938 || i.types[op].bitfield.disp32s
4939 || i.types[op].bitfield.disp16)
b5014f7a 4940 && fits_in_disp8 (op_disp))
40fb9820 4941 i.types[op].bitfield.disp8 = 1;
252b5132 4942 }
67a4f2b7
AO		 4943 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4944 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4945 {
4946 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4947 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4948 i.types[op].bitfield.disp8 = 0;
4949 i.types[op].bitfield.disp16 = 0;
4950 i.types[op].bitfield.disp32 = 0;
4951 i.types[op].bitfield.disp32s = 0;
4952 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4953 }
4954 else
b300c311 4955 /* We only support 64bit displacement on constants. */
40fb9820 4956 i.types[op].bitfield.disp64 = 0;
252b5132 4957 }
29b0f896
AM		 4958}
4959
6c30d220
L		 4960/* Check if operands are valid for the instruction. */
4961
4962static int
4963check_VecOperands (const insn_template *t)
4964{
43234a1e
L		 4965 unsigned int op;
4966
6c30d220
L		 4967 /* Without VSIB byte, we can't have a vector register for index. */
4968 if (!t->opcode_modifier.vecsib
4969 && i.index_reg
1b54b8d7
JB		 4970 && (i.index_reg->reg_type.bitfield.xmmword
4971 || i.index_reg->reg_type.bitfield.ymmword
4972 || i.index_reg->reg_type.bitfield.zmmword))
6c30d220
L		 4973 {
4974 i.error = unsupported_vector_index_register;
4975 return 1;
4976 }
4977
ad8ecc81
MZ		 4978 /* Check if default mask is allowed. */
4979 if (t->opcode_modifier.nodefmask
4980 && (!i.mask || i.mask->mask->reg_num == 0))
4981 {
4982 i.error = no_default_mask;
4983 return 1;
4984 }
4985
7bab8ab5
JB		 4986 /* For VSIB byte, we need a vector register for index, and all vector
4987 registers must be distinct. */
4988 if (t->opcode_modifier.vecsib)
4989 {
4990 if (!i.index_reg
6c30d220 4991 || !((t->opcode_modifier.vecsib == VecSIB128
1b54b8d7 4992 && i.index_reg->reg_type.bitfield.xmmword)
6c30d220 4993 || (t->opcode_modifier.vecsib == VecSIB256
1b54b8d7 4994 && i.index_reg->reg_type.bitfield.ymmword)
43234a1e 4995 || (t->opcode_modifier.vecsib == VecSIB512
1b54b8d7 4996 && i.index_reg->reg_type.bitfield.zmmword)))
7bab8ab5
JB		 4997 {
4998 i.error = invalid_vsib_address;
4999 return 1;
5000 }
5001
43234a1e
L		 5002 gas_assert (i.reg_operands == 2 || i.mask);
5003 if (i.reg_operands == 2 && !i.mask)
5004 {
1b54b8d7
JB		 5005 gas_assert (i.types[0].bitfield.regsimd);
5006 gas_assert (i.types[0].bitfield.xmmword
5007 || i.types[0].bitfield.ymmword);
5008 gas_assert (i.types[2].bitfield.regsimd);
5009 gas_assert (i.types[2].bitfield.xmmword
5010 || i.types[2].bitfield.ymmword);
43234a1e
L		 5011 if (operand_check == check_none)
5012 return 0;
5013 if (register_number (i.op[0].regs)
5014 != register_number (i.index_reg)
5015 && register_number (i.op[2].regs)
5016 != register_number (i.index_reg)
5017 && register_number (i.op[0].regs)
5018 != register_number (i.op[2].regs))
5019 return 0;
5020 if (operand_check == check_error)
5021 {
5022 i.error = invalid_vector_register_set;
5023 return 1;
5024 }
5025 as_warn (_("mask, index, and destination registers should be distinct"));
5026 }
8444f82a
MZ		 5027 else if (i.reg_operands == 1 && i.mask)
5028 {
1b54b8d7
JB		 5029 if (i.types[1].bitfield.regsimd
5030 && (i.types[1].bitfield.xmmword
5031 || i.types[1].bitfield.ymmword
5032 || i.types[1].bitfield.zmmword)
8444f82a
MZ		 5033 && (register_number (i.op[1].regs)
5034 == register_number (i.index_reg)))
5035 {
5036 if (operand_check == check_error)
5037 {
5038 i.error = invalid_vector_register_set;
5039 return 1;
5040 }
5041 if (operand_check != check_none)
5042 as_warn (_("index and destination registers should be distinct"));
5043 }
5044 }
43234a1e 5045 }
7bab8ab5 5046
43234a1e
L		 5047 /* Check if broadcast is supported by the instruction and is applied
5048 to the memory operand. */
5049 if (i.broadcast)
5050 {
5051 int broadcasted_opnd_size;
5052
5053 /* Check if specified broadcast is supported in this instruction,
5054 and it's applied to memory operand of DWORD or QWORD type,
5055 depending on VecESize. */
5056 if (i.broadcast->type != t->opcode_modifier.broadcast
5057 || !i.types[i.broadcast->operand].bitfield.mem
5058 || (t->opcode_modifier.vecesize == 0
5059 && !i.types[i.broadcast->operand].bitfield.dword
5060 && !i.types[i.broadcast->operand].bitfield.unspecified)
5061 || (t->opcode_modifier.vecesize == 1
5062 && !i.types[i.broadcast->operand].bitfield.qword
5063 && !i.types[i.broadcast->operand].bitfield.unspecified))
5064 goto bad_broadcast;
5065
5066 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
5067 if (i.broadcast->type == BROADCAST_1TO16)
5068 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
5069 else if (i.broadcast->type == BROADCAST_1TO8)
5070 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 5071 else if (i.broadcast->type == BROADCAST_1TO4)
5072 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
5073 else if (i.broadcast->type == BROADCAST_1TO2)
5074 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 5075 else
5076 goto bad_broadcast;
5077
5078 if ((broadcasted_opnd_size == 256
5079 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
5080 || (broadcasted_opnd_size == 512
5081 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
5082 {
5083 bad_broadcast:
5084 i.error = unsupported_broadcast;
5085 return 1;
5086 }
5087 }
5088 /* If broadcast is supported in this instruction, we need to check if
5089 operand of one-element size isn't specified without broadcast. */
5090 else if (t->opcode_modifier.broadcast && i.mem_operands)
5091 {
5092 /* Find memory operand. */
5093 for (op = 0; op < i.operands; op++)
5094 if (operand_type_check (i.types[op], anymem))
5095 break;
5096 gas_assert (op < i.operands);
5097 /* Check size of the memory operand. */
5098 if ((t->opcode_modifier.vecesize == 0
5099 && i.types[op].bitfield.dword)
5100 || (t->opcode_modifier.vecesize == 1
5101 && i.types[op].bitfield.qword))
5102 {
5103 i.error = broadcast_needed;
5104 return 1;
5105 }
5106 }
5107
5108 /* Check if requested masking is supported. */
5109 if (i.mask
5110 && (!t->opcode_modifier.masking
5111 || (i.mask->zeroing
5112 && t->opcode_modifier.masking == MERGING_MASKING)))
5113 {
5114 i.error = unsupported_masking;
5115 return 1;
5116 }
5117
5118 /* Check if masking is applied to dest operand. */
5119 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5120 {
5121 i.error = mask_not_on_destination;
5122 return 1;
5123 }
5124
43234a1e
L		 5125 /* Check RC/SAE. */
5126 if (i.rounding)
5127 {
5128 if ((i.rounding->type != saeonly
5129 && !t->opcode_modifier.staticrounding)
5130 || (i.rounding->type == saeonly
5131 && (t->opcode_modifier.staticrounding
5132 || !t->opcode_modifier.sae)))
5133 {
5134 i.error = unsupported_rc_sae;
5135 return 1;
5136 }
5137 /* If the instruction has several immediate operands and one of
5138 them is rounding, the rounding operand should be the last
5139 immediate operand. */
5140 if (i.imm_operands > 1
5141 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 5142 {
43234a1e 5143 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 5144 return 1;
5145 }
6c30d220
L		 5146 }
5147
43234a1e 5148 /* Check vector Disp8 operand. */
b5014f7a
JB		 5149 if (t->opcode_modifier.disp8memshift
5150 && i.disp_encoding != disp_encoding_32bit)
43234a1e
L		 5151 {
5152 if (i.broadcast)
5153 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
5154 else
5155 i.memshift = t->opcode_modifier.disp8memshift;
5156
5157 for (op = 0; op < i.operands; op++)
5158 if (operand_type_check (i.types[op], disp)
5159 && i.op[op].disps->X_op == O_constant)
5160 {
b5014f7a 5161 if (fits_in_disp8 (i.op[op].disps->X_add_number))
43234a1e 5162 {
b5014f7a
JB		 5163 i.types[op].bitfield.disp8 = 1;
5164 return 0;
43234a1e 5165 }
b5014f7a 5166 i.types[op].bitfield.disp8 = 0;
43234a1e
L		 5167 }
5168 }
b5014f7a
JB		 5169
5170 i.memshift = 0;
43234a1e 5171
6c30d220
L		 5172 return 0;
5173}
5174
43f3e2ee 5175/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 5176 operand types. */
5177
5178static int
5179VEX_check_operands (const insn_template *t)
5180{
86fa6981 5181 if (i.vec_encoding == vex_encoding_evex)
43234a1e 5182 {
86fa6981 5183 /* This instruction must be encoded with EVEX prefix. */
e771e7c9 5184 if (!is_evex_encoding (t))
86fa6981
L		 5185 {
5186 i.error = unsupported;
5187 return 1;
5188 }
5189 return 0;
43234a1e
L		 5190 }
5191
a683cc34 5192 if (!t->opcode_modifier.vex)
86fa6981
L		 5193 {
5194 /* This instruction template doesn't have VEX prefix. */
5195 if (i.vec_encoding != vex_encoding_default)
5196 {
5197 i.error = unsupported;
5198 return 1;
5199 }
5200 return 0;
5201 }
a683cc34
SP		 5202
5203 /* Only check VEX_Imm4, which must be the first operand. */
5204 if (t->operand_types[0].bitfield.vec_imm4)
5205 {
5206 if (i.op[0].imms->X_op != O_constant
5207 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 5208 {
a65babc9 5209 i.error = bad_imm4;
891edac4
L		 5210 return 1;
5211 }
a683cc34
SP		 5212
5213 /* Turn off Imm8 so that update_imm won't complain. */
5214 i.types[0] = vec_imm4;
5215 }
5216
5217 return 0;
5218}
5219
d3ce72d0 5220static const insn_template *
83b16ac6 5221match_template (char mnem_suffix)
29b0f896
AM		 5222{
5223 /* Points to template once we've found it. */
d3ce72d0 5224 const insn_template *t;
40fb9820 5225 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 5226 i386_operand_type overlap4;
29b0f896 5227 unsigned int found_reverse_match;
83b16ac6 5228 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 5229 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 5230 int addr_prefix_disp;
a5c311ca 5231 unsigned int j;
3629bb00 5232 unsigned int found_cpu_match;
45664ddb 5233 unsigned int check_register;
5614d22c 5234 enum i386_error specific_error = 0;
29b0f896 5235
c0f3af97
L		 5236#if MAX_OPERANDS != 5
5237# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 5238#endif
5239
29b0f896 5240 found_reverse_match = 0;
539e75ad 5241 addr_prefix_disp = -1;
40fb9820
L		 5242
5243 memset (&suffix_check, 0, sizeof (suffix_check));
5244 if (i.suffix == BYTE_MNEM_SUFFIX)
5245 suffix_check.no_bsuf = 1;
5246 else if (i.suffix == WORD_MNEM_SUFFIX)
5247 suffix_check.no_wsuf = 1;
5248 else if (i.suffix == SHORT_MNEM_SUFFIX)
5249 suffix_check.no_ssuf = 1;
5250 else if (i.suffix == LONG_MNEM_SUFFIX)
5251 suffix_check.no_lsuf = 1;
5252 else if (i.suffix == QWORD_MNEM_SUFFIX)
5253 suffix_check.no_qsuf = 1;
5254 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 5255 suffix_check.no_ldsuf = 1;
29b0f896 5256
83b16ac6
JB		 5257 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5258 if (intel_syntax)
5259 {
5260 switch (mnem_suffix)
5261 {
5262 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5263 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5264 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5265 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5266 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5267 }
5268 }
5269
01559ecc
L		 5270 /* Must have right number of operands. */
5271 i.error = number_of_operands_mismatch;
5272
45aa61fe 5273 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 5274 {
539e75ad
L		 5275 addr_prefix_disp = -1;
5276
29b0f896
AM		 5277 if (i.operands != t->operands)
5278 continue;
5279
50aecf8c 5280 /* Check processor support. */
a65babc9 5281 i.error = unsupported;
c0f3af97
L		 5282 found_cpu_match = (cpu_flags_match (t)
5283 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 5284 if (!found_cpu_match)
5285 continue;
5286
e1d4d893 5287 /* Check AT&T mnemonic. */
a65babc9 5288 i.error = unsupported_with_intel_mnemonic;
e1d4d893 5289 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 5290 continue;
5291
e92bae62 5292 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 5293 i.error = unsupported_syntax;
5c07affc 5294 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 5295 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5296 || (intel64 && t->opcode_modifier.amd64)
5297 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 5298 continue;
5299
20592a94 5300 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 5301 i.error = invalid_instruction_suffix;
567e4e96
L		 5302 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5303 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5304 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5305 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5306 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5307 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5308 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 5309 continue;
83b16ac6
JB		 5310 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5311 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5312 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5313 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5314 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5315 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5316 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5317 continue;
29b0f896 5318
5c07affc 5319 if (!operand_size_match (t))
7d5e4556 5320 continue;
539e75ad 5321
5c07affc
L		 5322 for (j = 0; j < MAX_OPERANDS; j++)
5323 operand_types[j] = t->operand_types[j];
5324
45aa61fe
AM		 5325 /* In general, don't allow 64-bit operands in 32-bit mode. */
5326 if (i.suffix == QWORD_MNEM_SUFFIX
5327 && flag_code != CODE_64BIT
5328 && (intel_syntax
40fb9820 5329 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 5330 && !intel_float_operand (t->name))
5331 : intel_float_operand (t->name) != 2)
40fb9820 5332 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5333 && !operand_types[0].bitfield.regsimd)
40fb9820 5334 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5335 && !operand_types[t->operands > 1].bitfield.regsimd))
45aa61fe
AM		 5336 && (t->base_opcode != 0x0fc7
5337 || t->extension_opcode != 1 /* cmpxchg8b */))
5338 continue;
5339
192dc9c6
JB		 5340 /* In general, don't allow 32-bit operands on pre-386. */
5341 else if (i.suffix == LONG_MNEM_SUFFIX
5342 && !cpu_arch_flags.bitfield.cpui386
5343 && (intel_syntax
5344 ? (!t->opcode_modifier.ignoresize
5345 && !intel_float_operand (t->name))
5346 : intel_float_operand (t->name) != 2)
5347 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5348 && !operand_types[0].bitfield.regsimd)
192dc9c6 5349 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5350 && !operand_types[t->operands > 1].bitfield.regsimd)))
192dc9c6
JB		 5351 continue;
5352
29b0f896 5353 /* Do not verify operands when there are none. */
50aecf8c 5354 else
29b0f896 5355 {
c6fb90c8 5356 if (!t->operands)
2dbab7d5
L		 5357 /* We've found a match; break out of loop. */
5358 break;
29b0f896 5359 }
252b5132 5360
539e75ad
L		 5361 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5362 into Disp32/Disp16/Disp32 operand. */
5363 if (i.prefix[ADDR_PREFIX] != 0)
5364 {
40fb9820 5365 /* There should be only one Disp operand. */
539e75ad
L		 5366 switch (flag_code)
5367 {
5368 case CODE_16BIT:
40fb9820
L		 5369 for (j = 0; j < MAX_OPERANDS; j++)
5370 {
5371 if (operand_types[j].bitfield.disp16)
5372 {
5373 addr_prefix_disp = j;
5374 operand_types[j].bitfield.disp32 = 1;
5375 operand_types[j].bitfield.disp16 = 0;
5376 break;
5377 }
5378 }
539e75ad
L		 5379 break;
5380 case CODE_32BIT:
40fb9820
L		 5381 for (j = 0; j < MAX_OPERANDS; j++)
5382 {
5383 if (operand_types[j].bitfield.disp32)
5384 {
5385 addr_prefix_disp = j;
5386 operand_types[j].bitfield.disp32 = 0;
5387 operand_types[j].bitfield.disp16 = 1;
5388 break;
5389 }
5390 }
539e75ad
L		 5391 break;
5392 case CODE_64BIT:
40fb9820
L		 5393 for (j = 0; j < MAX_OPERANDS; j++)
5394 {
5395 if (operand_types[j].bitfield.disp64)
5396 {
5397 addr_prefix_disp = j;
5398 operand_types[j].bitfield.disp64 = 0;
5399 operand_types[j].bitfield.disp32 = 1;
5400 break;
5401 }
5402 }
539e75ad
L		 5403 break;
5404 }
539e75ad
L		 5405 }
5406
02a86693
L		 5407 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5408 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5409 continue;
5410
56ffb741
L		 5411 /* We check register size if needed. */
5412 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 5413 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5414 switch (t->operands)
5415 {
5416 case 1:
40fb9820 5417 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5418 continue;
5419 break;
5420 case 2:
33eaf5de 5421 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5422 only in 32bit mode and we can use opcode 0x90. In 64bit
5423 mode, we can't use 0x90 for xchg %eax, %eax since it should
5424 zero-extend %eax to %rax. */
5425 if (flag_code == CODE_64BIT
5426 && t->base_opcode == 0x90
0dfbf9d7
L		 5427 && operand_type_equal (&i.types [0], &acc32)
5428 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 5429 continue;
1212781b
JB		 5430 /* xrelease mov %eax, <disp> is another special case. It must not
5431 match the accumulator-only encoding of mov. */
5432 if (flag_code != CODE_64BIT
5433 && i.hle_prefix
5434 && t->base_opcode == 0xa0
5435 && i.types[0].bitfield.acc
5436 && operand_type_check (i.types[1], anymem))
5437 continue;
86fa6981
L		 5438 /* If we want store form, we reverse direction of operands. */
5439 if (i.dir_encoding == dir_encoding_store
5440 && t->opcode_modifier.d)
5441 goto check_reverse;
1a0670f3 5442 /* Fall through. */
b6169b20 5443
29b0f896 5444 case 3:
86fa6981
L		 5445 /* If we want store form, we skip the current load. */
5446 if (i.dir_encoding == dir_encoding_store
5447 && i.mem_operands == 0
5448 && t->opcode_modifier.load)
fa99fab2 5449 continue;
1a0670f3 5450 /* Fall through. */
f48ff2ae 5451 case 4:
c0f3af97 5452 case 5:
c6fb90c8 5453 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5454 if (!operand_type_match (overlap0, i.types[0])
5455 || !operand_type_match (overlap1, i.types[1])
45664ddb 5456 || (check_register
dc821c5f 5457 && !operand_type_register_match (i.types[0],
40fb9820 5458 operand_types[0],
dc821c5f 5459 i.types[1],
40fb9820 5460 operand_types[1])))
29b0f896
AM		 5461 {
5462 /* Check if other direction is valid ... */
38e314eb 5463 if (!t->opcode_modifier.d)
29b0f896
AM		 5464 continue;
5465
b6169b20 5466check_reverse:
29b0f896 5467 /* Try reversing direction of operands. */
c6fb90c8
L		 5468 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5469 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 5470 if (!operand_type_match (overlap0, i.types[0])
5471 || !operand_type_match (overlap1, i.types[1])
45664ddb 5472 || (check_register
dc821c5f 5473 && !operand_type_register_match (i.types[0],
45664ddb 5474 operand_types[1],
45664ddb
L		 5475 i.types[1],
5476 operand_types[0])))
29b0f896
AM		 5477 {
5478 /* Does not match either direction. */
5479 continue;
5480 }
38e314eb 5481 /* found_reverse_match holds which of D or FloatR
29b0f896 5482 we've found. */
38e314eb
JB		 5483 if (!t->opcode_modifier.d)
5484 found_reverse_match = 0;
5485 else if (operand_types[0].bitfield.tbyte)
8a2ed489
L		 5486 found_reverse_match = Opcode_FloatD;
5487 else
38e314eb 5488 found_reverse_match = Opcode_D;
40fb9820 5489 if (t->opcode_modifier.floatr)
8a2ed489 5490 found_reverse_match |= Opcode_FloatR;
29b0f896 5491 }
f48ff2ae 5492 else
29b0f896 5493 {
f48ff2ae 5494 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5495 switch (t->operands)
5496 {
c0f3af97
L		 5497 case 5:
5498 overlap4 = operand_type_and (i.types[4],
5499 operand_types[4]);
1a0670f3 5500 /* Fall through. */
d1cbb4db 5501 case 4:
c6fb90c8
L		 5502 overlap3 = operand_type_and (i.types[3],
5503 operand_types[3]);
1a0670f3 5504 /* Fall through. */
d1cbb4db 5505 case 3:
c6fb90c8
L		 5506 overlap2 = operand_type_and (i.types[2],
5507 operand_types[2]);
d1cbb4db
L		 5508 break;
5509 }
29b0f896 5510
f48ff2ae
L		 5511 switch (t->operands)
5512 {
c0f3af97
L		 5513 case 5:
5514 if (!operand_type_match (overlap4, i.types[4])
dc821c5f 5515 || !operand_type_register_match (i.types[3],
c0f3af97 5516 operand_types[3],
c0f3af97
L		 5517 i.types[4],
5518 operand_types[4]))
5519 continue;
1a0670f3 5520 /* Fall through. */
f48ff2ae 5521 case 4:
40fb9820 5522 if (!operand_type_match (overlap3, i.types[3])
45664ddb 5523 || (check_register
f7768225
JB		 5524 && (!operand_type_register_match (i.types[1],
5525 operand_types[1],
5526 i.types[3],
5527 operand_types[3])
5528 || !operand_type_register_match (i.types[2],
5529 operand_types[2],
5530 i.types[3],
5531 operand_types[3]))))
f48ff2ae 5532 continue;
1a0670f3 5533 /* Fall through. */
f48ff2ae
L		 5534 case 3:
5535 /* Here we make use of the fact that there are no
23e42951 5536 reverse match 3 operand instructions. */
40fb9820 5537 if (!operand_type_match (overlap2, i.types[2])
45664ddb 5538 || (check_register
23e42951
JB		 5539 && (!operand_type_register_match (i.types[0],
5540 operand_types[0],
5541 i.types[2],
5542 operand_types[2])
5543 || !operand_type_register_match (i.types[1],
5544 operand_types[1],
5545 i.types[2],
5546 operand_types[2]))))
f48ff2ae
L		 5547 continue;
5548 break;
5549 }
29b0f896 5550 }
f48ff2ae 5551 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5552 slip through to break. */
5553 }
3629bb00 5554 if (!found_cpu_match)
29b0f896
AM		 5555 {
5556 found_reverse_match = 0;
5557 continue;
5558 }
c0f3af97 5559
5614d22c
JB		 5560 /* Check if vector and VEX operands are valid. */
5561 if (check_VecOperands (t) || VEX_check_operands (t))
5562 {
5563 specific_error = i.error;
5564 continue;
5565 }
a683cc34 5566
29b0f896
AM		 5567 /* We've found a match; break out of loop. */
5568 break;
5569 }
5570
5571 if (t == current_templates->end)
5572 {
5573 /* We found no match. */
a65babc9 5574 const char *err_msg;
5614d22c 5575 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5576 {
5577 default:
5578 abort ();
86e026a4 5579 case operand_size_mismatch:
a65babc9
L		 5580 err_msg = _("operand size mismatch");
5581 break;
5582 case operand_type_mismatch:
5583 err_msg = _("operand type mismatch");
5584 break;
5585 case register_type_mismatch:
5586 err_msg = _("register type mismatch");
5587 break;
5588 case number_of_operands_mismatch:
5589 err_msg = _("number of operands mismatch");
5590 break;
5591 case invalid_instruction_suffix:
5592 err_msg = _("invalid instruction suffix");
5593 break;
5594 case bad_imm4:
4a2608e3 5595 err_msg = _("constant doesn't fit in 4 bits");
a65babc9 5596 break;
a65babc9
L		 5597 case unsupported_with_intel_mnemonic:
5598 err_msg = _("unsupported with Intel mnemonic");
5599 break;
5600 case unsupported_syntax:
5601 err_msg = _("unsupported syntax");
5602 break;
5603 case unsupported:
35262a23 5604 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5605 current_templates->start->name);
5606 return NULL;
6c30d220
L		 5607 case invalid_vsib_address:
5608 err_msg = _("invalid VSIB address");
5609 break;
7bab8ab5
JB		 5610 case invalid_vector_register_set:
5611 err_msg = _("mask, index, and destination registers must be distinct");
5612 break;
6c30d220
L		 5613 case unsupported_vector_index_register:
5614 err_msg = _("unsupported vector index register");
5615 break;
43234a1e
L		 5616 case unsupported_broadcast:
5617 err_msg = _("unsupported broadcast");
5618 break;
5619 case broadcast_not_on_src_operand:
5620 err_msg = _("broadcast not on source memory operand");
5621 break;
5622 case broadcast_needed:
5623 err_msg = _("broadcast is needed for operand of such type");
5624 break;
5625 case unsupported_masking:
5626 err_msg = _("unsupported masking");
5627 break;
5628 case mask_not_on_destination:
5629 err_msg = _("mask not on destination operand");
5630 break;
5631 case no_default_mask:
5632 err_msg = _("default mask isn't allowed");
5633 break;
5634 case unsupported_rc_sae:
5635 err_msg = _("unsupported static rounding/sae");
5636 break;
5637 case rc_sae_operand_not_last_imm:
5638 if (intel_syntax)
5639 err_msg = _("RC/SAE operand must precede immediate operands");
5640 else
5641 err_msg = _("RC/SAE operand must follow immediate operands");
5642 break;
5643 case invalid_register_operand:
5644 err_msg = _("invalid register operand");
5645 break;
a65babc9
L		 5646 }
5647 as_bad (_("%s for `%s'"), err_msg,
891edac4 5648 current_templates->start->name);
fa99fab2 5649 return NULL;
29b0f896 5650 }
252b5132 5651
29b0f896
AM		 5652 if (!quiet_warnings)
5653 {
5654 if (!intel_syntax
40fb9820
L		 5655 && (i.types[0].bitfield.jumpabsolute
5656 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5657 {
5658 as_warn (_("indirect %s without `*'"), t->name);
5659 }
5660
40fb9820
L		 5661 if (t->opcode_modifier.isprefix
5662 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5663 {
5664 /* Warn them that a data or address size prefix doesn't
5665 affect assembly of the next line of code. */
5666 as_warn (_("stand-alone `%s' prefix"), t->name);
5667 }
5668 }
5669
5670 /* Copy the template we found. */
5671 i.tm = *t;
539e75ad
L		 5672
5673 if (addr_prefix_disp != -1)
5674 i.tm.operand_types[addr_prefix_disp]
5675 = operand_types[addr_prefix_disp];
5676
29b0f896
AM		 5677 if (found_reverse_match)
5678 {
5679 /* If we found a reverse match we must alter the opcode
5680 direction bit. found_reverse_match holds bits to change
5681 (different for int & float insns). */
5682
5683 i.tm.base_opcode ^= found_reverse_match;
5684
539e75ad
L		 5685 i.tm.operand_types[0] = operand_types[1];
5686 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5687 }
5688
fa99fab2 5689 return t;
29b0f896
AM		 5690}
5691
5692static int
e3bb37b5 5693check_string (void)
29b0f896 5694{
40fb9820
L		 5695 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5696 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5697 {
5698 if (i.seg[0] != NULL && i.seg[0] != &es)
5699 {
a87af027 5700 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5701 i.tm.name,
a87af027
JB		 5702 mem_op + 1,
5703 register_prefix);
29b0f896
AM		 5704 return 0;
5705 }
5706 /* There's only ever one segment override allowed per instruction.
5707 This instruction possibly has a legal segment override on the
5708 second operand, so copy the segment to where non-string
5709 instructions store it, allowing common code. */
5710 i.seg[0] = i.seg[1];
5711 }
40fb9820 5712 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5713 {
5714 if (i.seg[1] != NULL && i.seg[1] != &es)
5715 {
a87af027 5716 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5717 i.tm.name,
a87af027
JB		 5718 mem_op + 2,
5719 register_prefix);
29b0f896
AM		 5720 return 0;
5721 }
5722 }
5723 return 1;
5724}
5725
5726static int
543613e9 5727process_suffix (void)
29b0f896
AM		 5728{
5729 /* If matched instruction specifies an explicit instruction mnemonic
5730 suffix, use it. */
40fb9820
L		 5731 if (i.tm.opcode_modifier.size16)
5732 i.suffix = WORD_MNEM_SUFFIX;
5733 else if (i.tm.opcode_modifier.size32)
5734 i.suffix = LONG_MNEM_SUFFIX;
5735 else if (i.tm.opcode_modifier.size64)
5736 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5737 else if (i.reg_operands)
5738 {
5739 /* If there's no instruction mnemonic suffix we try to invent one
5740 based on register operands. */
5741 if (!i.suffix)
5742 {
5743 /* We take i.suffix from the last register operand specified,
5744 Destination register type is more significant than source
381d071f
L		 5745 register type. crc32 in SSE4.2 prefers source register
5746 type. */
5747 if (i.tm.base_opcode == 0xf20f38f1)
5748 {
dc821c5f 5749 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
40fb9820 5750 i.suffix = WORD_MNEM_SUFFIX;
dc821c5f 5751 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
40fb9820 5752 i.suffix = LONG_MNEM_SUFFIX;
dc821c5f 5753 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
40fb9820 5754 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5755 }
9344ff29 5756 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5757 {
dc821c5f 5758 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
20592a94
L		 5759 i.suffix = BYTE_MNEM_SUFFIX;
5760 }
381d071f
L		 5761
5762 if (!i.suffix)
5763 {
5764 int op;
5765
20592a94
L		 5766 if (i.tm.base_opcode == 0xf20f38f1
5767 || i.tm.base_opcode == 0xf20f38f0)
5768 {
5769 /* We have to know the operand size for crc32. */
5770 as_bad (_("ambiguous memory operand size for `%s`"),
5771 i.tm.name);
5772 return 0;
5773 }
5774
381d071f 5775 for (op = i.operands; --op >= 0;)
b76bc5d5
JB		 5776 if (!i.tm.operand_types[op].bitfield.inoutportreg
5777 && !i.tm.operand_types[op].bitfield.shiftcount)
381d071f 5778 {
8819ada6
JB		 5779 if (!i.types[op].bitfield.reg)
5780 continue;
5781 if (i.types[op].bitfield.byte)
5782 i.suffix = BYTE_MNEM_SUFFIX;
5783 else if (i.types[op].bitfield.word)
5784 i.suffix = WORD_MNEM_SUFFIX;
5785 else if (i.types[op].bitfield.dword)
5786 i.suffix = LONG_MNEM_SUFFIX;
5787 else if (i.types[op].bitfield.qword)
5788 i.suffix = QWORD_MNEM_SUFFIX;
5789 else
5790 continue;
5791 break;
381d071f
L		 5792 }
5793 }
29b0f896
AM		 5794 }
5795 else if (i.suffix == BYTE_MNEM_SUFFIX)
5796 {
2eb952a4
L		 5797 if (intel_syntax
5798 && i.tm.opcode_modifier.ignoresize
5799 && i.tm.opcode_modifier.no_bsuf)
5800 i.suffix = 0;
5801 else if (!check_byte_reg ())
29b0f896
AM		 5802 return 0;
5803 }
5804 else if (i.suffix == LONG_MNEM_SUFFIX)
5805 {
2eb952a4
L		 5806 if (intel_syntax
5807 && i.tm.opcode_modifier.ignoresize
5808 && i.tm.opcode_modifier.no_lsuf)
5809 i.suffix = 0;
5810 else if (!check_long_reg ())
29b0f896
AM		 5811 return 0;
5812 }
5813 else if (i.suffix == QWORD_MNEM_SUFFIX)
5814 {
955e1e6a
L		 5815 if (intel_syntax
5816 && i.tm.opcode_modifier.ignoresize
5817 && i.tm.opcode_modifier.no_qsuf)
5818 i.suffix = 0;
5819 else if (!check_qword_reg ())
29b0f896
AM		 5820 return 0;
5821 }
5822 else if (i.suffix == WORD_MNEM_SUFFIX)
5823 {
2eb952a4
L		 5824 if (intel_syntax
5825 && i.tm.opcode_modifier.ignoresize
5826 && i.tm.opcode_modifier.no_wsuf)
5827 i.suffix = 0;
5828 else if (!check_word_reg ())
29b0f896
AM		 5829 return 0;
5830 }
40fb9820 5831 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5832 /* Do nothing if the instruction is going to ignore the prefix. */
5833 ;
5834 else
5835 abort ();
5836 }
40fb9820 5837 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5838 && !i.suffix
5839 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5840 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5841 {
5842 i.suffix = stackop_size;
5843 }
9306ca4a
JB		 5844 else if (intel_syntax
5845 && !i.suffix
40fb9820
L		 5846 && (i.tm.operand_types[0].bitfield.jumpabsolute
5847 || i.tm.opcode_modifier.jumpbyte
5848 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5849 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5850 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5851 {
5852 switch (flag_code)
5853 {
5854 case CODE_64BIT:
40fb9820 5855 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5856 {
5857 i.suffix = QWORD_MNEM_SUFFIX;
5858 break;
5859 }
1a0670f3 5860 /* Fall through. */
9306ca4a 5861 case CODE_32BIT:
40fb9820 5862 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5863 i.suffix = LONG_MNEM_SUFFIX;
5864 break;
5865 case CODE_16BIT:
40fb9820 5866 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5867 i.suffix = WORD_MNEM_SUFFIX;
5868 break;
5869 }
5870 }
252b5132 5871
9306ca4a 5872 if (!i.suffix)
29b0f896 5873 {
9306ca4a
JB		 5874 if (!intel_syntax)
5875 {
40fb9820 5876 if (i.tm.opcode_modifier.w)
9306ca4a 5877 {
4eed87de
AM		 5878 as_bad (_("no instruction mnemonic suffix given and "
5879 "no register operands; can't size instruction"));
9306ca4a
JB		 5880 return 0;
5881 }
5882 }
5883 else
5884 {
40fb9820 5885 unsigned int suffixes;
7ab9ffdd 5886
40fb9820
L		 5887 suffixes = !i.tm.opcode_modifier.no_bsuf;
5888 if (!i.tm.opcode_modifier.no_wsuf)
5889 suffixes |= 1 << 1;
5890 if (!i.tm.opcode_modifier.no_lsuf)
5891 suffixes |= 1 << 2;
fc4adea1 5892 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5893 suffixes |= 1 << 3;
5894 if (!i.tm.opcode_modifier.no_ssuf)
5895 suffixes |= 1 << 4;
c2b9da16 5896 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
40fb9820
L		 5897 suffixes |= 1 << 5;
5898
5899 /* There are more than suffix matches. */
5900 if (i.tm.opcode_modifier.w
9306ca4a 5901 || ((suffixes & (suffixes - 1))
40fb9820
L		 5902 && !i.tm.opcode_modifier.defaultsize
5903 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5904 {
5905 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5906 return 0;
5907 }
5908 }
29b0f896 5909 }
252b5132 5910
d2224064
JB		 5911 /* Change the opcode based on the operand size given by i.suffix. */
5912 switch (i.suffix)
29b0f896 5913 {
d2224064
JB		 5914 /* Size floating point instruction. */
5915 case LONG_MNEM_SUFFIX:
5916 if (i.tm.opcode_modifier.floatmf)
5917 {
5918 i.tm.base_opcode ^= 4;
5919 break;
5920 }
5921 /* fall through */
5922 case WORD_MNEM_SUFFIX:
5923 case QWORD_MNEM_SUFFIX:
29b0f896 5924 /* It's not a byte, select word/dword operation. */
40fb9820 5925 if (i.tm.opcode_modifier.w)
29b0f896 5926 {
40fb9820 5927 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5928 i.tm.base_opcode |= 8;
5929 else
5930 i.tm.base_opcode |= 1;
5931 }
d2224064
JB		 5932 /* fall through */
5933 case SHORT_MNEM_SUFFIX:
29b0f896
AM		 5934 /* Now select between word & dword operations via the operand
5935 size prefix, except for instructions that will ignore this
5936 prefix anyway. */
ca61edf2 5937 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5938 {
ca61edf2
L		 5939 /* The address size override prefix changes the size of the
5940 first operand. */
40fb9820 5941 if ((flag_code == CODE_32BIT
dc821c5f 5942 && i.op->regs[0].reg_type.bitfield.word)
40fb9820 5943 || (flag_code != CODE_32BIT
dc821c5f 5944 && i.op->regs[0].reg_type.bitfield.dword))
cb712a9e
L		 5945 if (!add_prefix (ADDR_PREFIX_OPCODE))
5946 return 0;
5947 }
5948 else if (i.suffix != QWORD_MNEM_SUFFIX
40fb9820
L		 5949 && !i.tm.opcode_modifier.ignoresize
5950 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5951 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5952 || (flag_code == CODE_64BIT
40fb9820 5953 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5954 {
5955 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5956
40fb9820 5957 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5958 prefix = ADDR_PREFIX_OPCODE;
252b5132 5959
29b0f896
AM		 5960 if (!add_prefix (prefix))
5961 return 0;
24eab124 5962 }
252b5132 5963
29b0f896
AM		 5964 /* Set mode64 for an operand. */
5965 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5966 && flag_code == CODE_64BIT
d2224064 5967 && !i.tm.opcode_modifier.norex64
46e883c5 5968 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d2224064
JB		 5969 need rex64. */
5970 && ! (i.operands == 2
5971 && i.tm.base_opcode == 0x90
5972 && i.tm.extension_opcode == None
5973 && operand_type_equal (&i.types [0], &acc64)
5974 && operand_type_equal (&i.types [1], &acc64)))
5975 i.rex |= REX_W;
3e73aa7c 5976
d2224064 5977 break;
29b0f896 5978 }
7ecd2f8b 5979
29b0f896
AM		 5980 return 1;
5981}
3e73aa7c 5982
29b0f896 5983static int
543613e9 5984check_byte_reg (void)
29b0f896
AM		 5985{
5986 int op;
543613e9 5987
29b0f896
AM		 5988 for (op = i.operands; --op >= 0;)
5989 {
dc821c5f
JB		 5990 /* Skip non-register operands. */
5991 if (!i.types[op].bitfield.reg)
5992 continue;
5993
29b0f896
AM		 5994 /* If this is an eight bit register, it's OK. If it's the 16 or
5995 32 bit version of an eight bit register, we will just use the
5996 low portion, and that's OK too. */
dc821c5f 5997 if (i.types[op].bitfield.byte)
29b0f896
AM		 5998 continue;
5999
5a819eb9
JB		 6000 /* I/O port address operands are OK too. */
6001 if (i.tm.operand_types[op].bitfield.inoutportreg)
6002 continue;
6003
9344ff29
L		 6004 /* crc32 doesn't generate this warning. */
6005 if (i.tm.base_opcode == 0xf20f38f0)
6006 continue;
6007
dc821c5f
JB		 6008 if ((i.types[op].bitfield.word
6009 || i.types[op].bitfield.dword
6010 || i.types[op].bitfield.qword)
5a819eb9
JB		 6011 && i.op[op].regs->reg_num < 4
6012 /* Prohibit these changes in 64bit mode, since the lowering
6013 would be more complicated. */
6014 && flag_code != CODE_64BIT)
29b0f896 6015 {
29b0f896 6016#if REGISTER_WARNINGS
5a819eb9 6017 if (!quiet_warnings)
a540244d
L		 6018 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6019 register_prefix,
dc821c5f 6020 (i.op[op].regs + (i.types[op].bitfield.word
29b0f896
AM		 6021 ? REGNAM_AL - REGNAM_AX
6022 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 6023 register_prefix,
29b0f896
AM		 6024 i.op[op].regs->reg_name,
6025 i.suffix);
6026#endif
6027 continue;
6028 }
6029 /* Any other register is bad. */
dc821c5f 6030 if (i.types[op].bitfield.reg
40fb9820 6031 || i.types[op].bitfield.regmmx
1b54b8d7 6032 || i.types[op].bitfield.regsimd
40fb9820
L		 6033 || i.types[op].bitfield.sreg2
6034 || i.types[op].bitfield.sreg3
6035 || i.types[op].bitfield.control
6036 || i.types[op].bitfield.debug
ca0d63fe 6037 || i.types[op].bitfield.test)
29b0f896 6038 {
a540244d
L		 6039 as_bad (_("`%s%s' not allowed with `%s%c'"),
6040 register_prefix,
29b0f896
AM		 6041 i.op[op].regs->reg_name,
6042 i.tm.name,
6043 i.suffix);
6044 return 0;
6045 }
6046 }
6047 return 1;
6048}
6049
6050static int
e3bb37b5 6051check_long_reg (void)
29b0f896
AM		 6052{
6053 int op;
6054
6055 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6056 /* Skip non-register operands. */
6057 if (!i.types[op].bitfield.reg)
6058 continue;
29b0f896
AM		 6059 /* Reject eight bit registers, except where the template requires
6060 them. (eg. movzb) */
dc821c5f
JB		 6061 else if (i.types[op].bitfield.byte
6062 && (i.tm.operand_types[op].bitfield.reg
6063 || i.tm.operand_types[op].bitfield.acc)
6064 && (i.tm.operand_types[op].bitfield.word
6065 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6066 {
a540244d
L		 6067 as_bad (_("`%s%s' not allowed with `%s%c'"),
6068 register_prefix,
29b0f896
AM		 6069 i.op[op].regs->reg_name,
6070 i.tm.name,
6071 i.suffix);
6072 return 0;
6073 }
e4630f71 6074 /* Warn if the e prefix on a general reg is missing. */
29b0f896 6075 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6076 && i.types[op].bitfield.word
6077 && (i.tm.operand_types[op].bitfield.reg
6078 || i.tm.operand_types[op].bitfield.acc)
6079 && i.tm.operand_types[op].bitfield.dword)
29b0f896
AM		 6080 {
6081 /* Prohibit these changes in the 64bit mode, since the
6082 lowering is more complicated. */
6083 if (flag_code == CODE_64BIT)
252b5132 6084 {
2b5d6a91 6085 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6086 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6087 i.suffix);
6088 return 0;
252b5132 6089 }
29b0f896 6090#if REGISTER_WARNINGS
cecf1424
JB		 6091 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6092 register_prefix,
6093 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6094 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 6095#endif
252b5132 6096 }
e4630f71 6097 /* Warn if the r prefix on a general reg is present. */
dc821c5f
JB		 6098 else if (i.types[op].bitfield.qword
6099 && (i.tm.operand_types[op].bitfield.reg
6100 || i.tm.operand_types[op].bitfield.acc)
6101 && i.tm.operand_types[op].bitfield.dword)
252b5132 6102 {
34828aad 6103 if (intel_syntax
ca61edf2 6104 && i.tm.opcode_modifier.toqword
1b54b8d7 6105 && !i.types[0].bitfield.regsimd)
34828aad 6106 {
ca61edf2 6107 /* Convert to QWORD. We want REX byte. */
34828aad
L		 6108 i.suffix = QWORD_MNEM_SUFFIX;
6109 }
6110 else
6111 {
2b5d6a91 6112 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6113 register_prefix, i.op[op].regs->reg_name,
6114 i.suffix);
6115 return 0;
6116 }
29b0f896
AM		 6117 }
6118 return 1;
6119}
252b5132 6120
29b0f896 6121static int
e3bb37b5 6122check_qword_reg (void)
29b0f896
AM		 6123{
6124 int op;
252b5132 6125
29b0f896 6126 for (op = i.operands; --op >= 0; )
dc821c5f
JB		 6127 /* Skip non-register operands. */
6128 if (!i.types[op].bitfield.reg)
6129 continue;
29b0f896
AM		 6130 /* Reject eight bit registers, except where the template requires
6131 them. (eg. movzb) */
dc821c5f
JB		 6132 else if (i.types[op].bitfield.byte
6133 && (i.tm.operand_types[op].bitfield.reg
6134 || i.tm.operand_types[op].bitfield.acc)
6135 && (i.tm.operand_types[op].bitfield.word
6136 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6137 {
a540244d
L		 6138 as_bad (_("`%s%s' not allowed with `%s%c'"),
6139 register_prefix,
29b0f896
AM		 6140 i.op[op].regs->reg_name,
6141 i.tm.name,
6142 i.suffix);
6143 return 0;
6144 }
e4630f71 6145 /* Warn if the r prefix on a general reg is missing. */
dc821c5f
JB		 6146 else if ((i.types[op].bitfield.word
6147 || i.types[op].bitfield.dword)
6148 && (i.tm.operand_types[op].bitfield.reg
6149 || i.tm.operand_types[op].bitfield.acc)
6150 && i.tm.operand_types[op].bitfield.qword)
29b0f896
AM		 6151 {
6152 /* Prohibit these changes in the 64bit mode, since the
6153 lowering is more complicated. */
34828aad 6154 if (intel_syntax
ca61edf2 6155 && i.tm.opcode_modifier.todword
1b54b8d7 6156 && !i.types[0].bitfield.regsimd)
34828aad 6157 {
ca61edf2 6158 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 6159 i.suffix = LONG_MNEM_SUFFIX;
6160 }
6161 else
6162 {
2b5d6a91 6163 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6164 register_prefix, i.op[op].regs->reg_name,
6165 i.suffix);
6166 return 0;
6167 }
252b5132 6168 }
29b0f896
AM		 6169 return 1;
6170}
252b5132 6171
29b0f896 6172static int
e3bb37b5 6173check_word_reg (void)
29b0f896
AM		 6174{
6175 int op;
6176 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6177 /* Skip non-register operands. */
6178 if (!i.types[op].bitfield.reg)
6179 continue;
29b0f896
AM		 6180 /* Reject eight bit registers, except where the template requires
6181 them. (eg. movzb) */
dc821c5f
JB		 6182 else if (i.types[op].bitfield.byte
6183 && (i.tm.operand_types[op].bitfield.reg
6184 || i.tm.operand_types[op].bitfield.acc)
6185 && (i.tm.operand_types[op].bitfield.word
6186 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6187 {
a540244d
L		 6188 as_bad (_("`%s%s' not allowed with `%s%c'"),
6189 register_prefix,
29b0f896
AM		 6190 i.op[op].regs->reg_name,
6191 i.tm.name,
6192 i.suffix);
6193 return 0;
6194 }
e4630f71 6195 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 6196 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6197 && (i.types[op].bitfield.dword
6198 || i.types[op].bitfield.qword)
6199 && (i.tm.operand_types[op].bitfield.reg
6200 || i.tm.operand_types[op].bitfield.acc)
6201 && i.tm.operand_types[op].bitfield.word)
252b5132 6202 {
29b0f896
AM		 6203 /* Prohibit these changes in the 64bit mode, since the
6204 lowering is more complicated. */
6205 if (flag_code == CODE_64BIT)
252b5132 6206 {
2b5d6a91 6207 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6208 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6209 i.suffix);
6210 return 0;
252b5132 6211 }
29b0f896 6212#if REGISTER_WARNINGS
cecf1424
JB		 6213 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6214 register_prefix,
6215 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6216 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 6217#endif
6218 }
6219 return 1;
6220}
252b5132 6221
29b0f896 6222static int
40fb9820 6223update_imm (unsigned int j)
29b0f896 6224{
bc0844ae 6225 i386_operand_type overlap = i.types[j];
40fb9820
L		 6226 if ((overlap.bitfield.imm8
6227 || overlap.bitfield.imm8s
6228 || overlap.bitfield.imm16
6229 || overlap.bitfield.imm32
6230 || overlap.bitfield.imm32s
6231 || overlap.bitfield.imm64)
0dfbf9d7
L		 6232 && !operand_type_equal (&overlap, &imm8)
6233 && !operand_type_equal (&overlap, &imm8s)
6234 && !operand_type_equal (&overlap, &imm16)
6235 && !operand_type_equal (&overlap, &imm32)
6236 && !operand_type_equal (&overlap, &imm32s)
6237 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 6238 {
6239 if (i.suffix)
6240 {
40fb9820
L		 6241 i386_operand_type temp;
6242
0dfbf9d7 6243 operand_type_set (&temp, 0);
7ab9ffdd 6244 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 6245 {
6246 temp.bitfield.imm8 = overlap.bitfield.imm8;
6247 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6248 }
6249 else if (i.suffix == WORD_MNEM_SUFFIX)
6250 temp.bitfield.imm16 = overlap.bitfield.imm16;
6251 else if (i.suffix == QWORD_MNEM_SUFFIX)
6252 {
6253 temp.bitfield.imm64 = overlap.bitfield.imm64;
6254 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6255 }
6256 else
6257 temp.bitfield.imm32 = overlap.bitfield.imm32;
6258 overlap = temp;
29b0f896 6259 }
0dfbf9d7
L		 6260 else if (operand_type_equal (&overlap, &imm16_32_32s)
6261 || operand_type_equal (&overlap, &imm16_32)
6262 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 6263 {
40fb9820 6264 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 6265 overlap = imm16;
40fb9820 6266 else
65da13b5 6267 overlap = imm32s;
29b0f896 6268 }
0dfbf9d7
L		 6269 if (!operand_type_equal (&overlap, &imm8)
6270 && !operand_type_equal (&overlap, &imm8s)
6271 && !operand_type_equal (&overlap, &imm16)
6272 && !operand_type_equal (&overlap, &imm32)
6273 && !operand_type_equal (&overlap, &imm32s)
6274 && !operand_type_equal (&overlap, &imm64))
29b0f896 6275 {
4eed87de
AM		 6276 as_bad (_("no instruction mnemonic suffix given; "
6277 "can't determine immediate size"));
29b0f896
AM		 6278 return 0;
6279 }
6280 }
40fb9820 6281 i.types[j] = overlap;
29b0f896 6282
40fb9820
L		 6283 return 1;
6284}
6285
6286static int
6287finalize_imm (void)
6288{
bc0844ae 6289 unsigned int j, n;
29b0f896 6290
bc0844ae
L		 6291 /* Update the first 2 immediate operands. */
6292 n = i.operands > 2 ? 2 : i.operands;
6293 if (n)
6294 {
6295 for (j = 0; j < n; j++)
6296 if (update_imm (j) == 0)
6297 return 0;
40fb9820 6298
bc0844ae
L		 6299 /* The 3rd operand can't be immediate operand. */
6300 gas_assert (operand_type_check (i.types[2], imm) == 0);
6301 }
29b0f896
AM		 6302
6303 return 1;
6304}
6305
6306static int
e3bb37b5 6307process_operands (void)
29b0f896
AM		 6308{
6309 /* Default segment register this instruction will use for memory
6310 accesses. 0 means unknown. This is only for optimizing out
6311 unnecessary segment overrides. */
6312 const seg_entry *default_seg = 0;
6313
2426c15f 6314 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 6315 {
91d6fa6a
NC		 6316 unsigned int dupl = i.operands;
6317 unsigned int dest = dupl - 1;
9fcfb3d7
L		 6318 unsigned int j;
6319
c0f3af97 6320 /* The destination must be an xmm register. */
9c2799c2 6321 gas_assert (i.reg_operands
91d6fa6a 6322 && MAX_OPERANDS > dupl
7ab9ffdd 6323 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97 6324
1b54b8d7
JB		 6325 if (i.tm.operand_types[0].bitfield.acc
6326 && i.tm.operand_types[0].bitfield.xmmword)
e2ec9d29 6327 {
8cd7925b 6328 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 6329 {
6330 /* Keep xmm0 for instructions with VEX prefix and 3
6331 sources. */
1b54b8d7
JB		 6332 i.tm.operand_types[0].bitfield.acc = 0;
6333 i.tm.operand_types[0].bitfield.regsimd = 1;
c0f3af97
L		 6334 goto duplicate;
6335 }
e2ec9d29 6336 else
c0f3af97
L		 6337 {
6338 /* We remove the first xmm0 and keep the number of
6339 operands unchanged, which in fact duplicates the
6340 destination. */
6341 for (j = 1; j < i.operands; j++)
6342 {
6343 i.op[j - 1] = i.op[j];
6344 i.types[j - 1] = i.types[j];
6345 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6346 }
6347 }
6348 }
6349 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 6350 {
91d6fa6a 6351 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 6352 && (i.tm.opcode_modifier.vexsources
6353 == VEX3SOURCES));
c0f3af97
L		 6354
6355 /* Add the implicit xmm0 for instructions with VEX prefix
6356 and 3 sources. */
6357 for (j = i.operands; j > 0; j--)
6358 {
6359 i.op[j] = i.op[j - 1];
6360 i.types[j] = i.types[j - 1];
6361 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6362 }
6363 i.op[0].regs
6364 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 6365 i.types[0] = regxmm;
c0f3af97
L		 6366 i.tm.operand_types[0] = regxmm;
6367
6368 i.operands += 2;
6369 i.reg_operands += 2;
6370 i.tm.operands += 2;
6371
91d6fa6a 6372 dupl++;
c0f3af97 6373 dest++;
91d6fa6a
NC		 6374 i.op[dupl] = i.op[dest];
6375 i.types[dupl] = i.types[dest];
6376 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6377 }
c0f3af97
L		 6378 else
6379 {
6380duplicate:
6381 i.operands++;
6382 i.reg_operands++;
6383 i.tm.operands++;
6384
91d6fa6a
NC		 6385 i.op[dupl] = i.op[dest];
6386 i.types[dupl] = i.types[dest];
6387 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6388 }
6389
6390 if (i.tm.opcode_modifier.immext)
6391 process_immext ();
6392 }
1b54b8d7
JB		 6393 else if (i.tm.operand_types[0].bitfield.acc
6394 && i.tm.operand_types[0].bitfield.xmmword)
c0f3af97
L		 6395 {
6396 unsigned int j;
6397
9fcfb3d7
L		 6398 for (j = 1; j < i.operands; j++)
6399 {
6400 i.op[j - 1] = i.op[j];
6401 i.types[j - 1] = i.types[j];
6402
6403 /* We need to adjust fields in i.tm since they are used by
6404 build_modrm_byte. */
6405 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6406 }
6407
e2ec9d29
L		 6408 i.operands--;
6409 i.reg_operands--;
e2ec9d29
L		 6410 i.tm.operands--;
6411 }
920d2ddc
IT		 6412 else if (i.tm.opcode_modifier.implicitquadgroup)
6413 {
a477a8c4
JB		 6414 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6415
920d2ddc 6416 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
10c17abd 6417 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
a477a8c4
JB		 6418 regnum = register_number (i.op[1].regs);
6419 first_reg_in_group = regnum & ~3;
6420 last_reg_in_group = first_reg_in_group + 3;
6421 if (regnum != first_reg_in_group)
6422 as_warn (_("source register `%s%s' implicitly denotes"
6423 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6424 register_prefix, i.op[1].regs->reg_name,
6425 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6426 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6427 i.tm.name);
6428 }
e2ec9d29
L		 6429 else if (i.tm.opcode_modifier.regkludge)
6430 {
6431 /* The imul $imm, %reg instruction is converted into
6432 imul $imm, %reg, %reg, and the clr %reg instruction
6433 is converted into xor %reg, %reg. */
6434
6435 unsigned int first_reg_op;
6436
6437 if (operand_type_check (i.types[0], reg))
6438 first_reg_op = 0;
6439 else
6440 first_reg_op = 1;
6441 /* Pretend we saw the extra register operand. */
9c2799c2 6442 gas_assert (i.reg_operands == 1
7ab9ffdd 6443 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6444 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6445 i.types[first_reg_op + 1] = i.types[first_reg_op];
6446 i.operands++;
6447 i.reg_operands++;
29b0f896
AM		 6448 }
6449
40fb9820 6450 if (i.tm.opcode_modifier.shortform)
29b0f896 6451 {
40fb9820
L		 6452 if (i.types[0].bitfield.sreg2
6453 || i.types[0].bitfield.sreg3)
29b0f896 6454 {
4eed87de
AM		 6455 if (i.tm.base_opcode == POP_SEG_SHORT
6456 && i.op[0].regs->reg_num == 1)
29b0f896 6457 {
a87af027 6458 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6459 return 0;
29b0f896 6460 }
4eed87de
AM		 6461 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6462 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6463 i.rex |= REX_B;
4eed87de
AM		 6464 }
6465 else
6466 {
7ab9ffdd 6467 /* The register or float register operand is in operand
85f10a01 6468 0 or 1. */
40fb9820 6469 unsigned int op;
7ab9ffdd 6470
ca0d63fe 6471 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
7ab9ffdd
L		 6472 || operand_type_check (i.types[0], reg))
6473 op = 0;
6474 else
6475 op = 1;
4eed87de
AM		 6476 /* Register goes in low 3 bits of opcode. */
6477 i.tm.base_opcode |= i.op[op].regs->reg_num;
6478 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6479 i.rex |= REX_B;
40fb9820 6480 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6481 {
4eed87de
AM		 6482 /* Warn about some common errors, but press on regardless.
6483 The first case can be generated by gcc (<= 2.8.1). */
6484 if (i.operands == 2)
6485 {
6486 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6487 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6488 register_prefix, i.op[!intel_syntax].regs->reg_name,
6489 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6490 }
6491 else
6492 {
6493 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6494 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6495 register_prefix, i.op[0].regs->reg_name);
4eed87de 6496 }
29b0f896
AM		 6497 }
6498 }
6499 }
40fb9820 6500 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6501 {
6502 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6503 must be put into the modrm byte). Now, we make the modrm and
6504 index base bytes based on all the info we've collected. */
29b0f896
AM		 6505
6506 default_seg = build_modrm_byte ();
6507 }
8a2ed489 6508 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6509 {
6510 default_seg = &ds;
6511 }
40fb9820 6512 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6513 {
6514 /* For the string instructions that allow a segment override
6515 on one of their operands, the default segment is ds. */
6516 default_seg = &ds;
6517 }
6518
75178d9d
L		 6519 if (i.tm.base_opcode == 0x8d /* lea */
6520 && i.seg[0]
6521 && !quiet_warnings)
30123838 6522 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6523
6524 /* If a segment was explicitly specified, and the specified segment
6525 is not the default, use an opcode prefix to select it. If we
6526 never figured out what the default segment is, then default_seg
6527 will be zero at this point, and the specified segment prefix will
6528 always be used. */
29b0f896
AM		 6529 if ((i.seg[0]) && (i.seg[0] != default_seg))
6530 {
6531 if (!add_prefix (i.seg[0]->seg_prefix))
6532 return 0;
6533 }
6534 return 1;
6535}
6536
6537static const seg_entry *
e3bb37b5 6538build_modrm_byte (void)
29b0f896
AM		 6539{
6540 const seg_entry *default_seg = 0;
c0f3af97 6541 unsigned int source, dest;
8cd7925b 6542 int vex_3_sources;
c0f3af97
L		 6543
6544 /* The first operand of instructions with VEX prefix and 3 sources
6545 must be VEX_Imm4. */
8cd7925b 6546 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6547 if (vex_3_sources)
6548 {
91d6fa6a 6549 unsigned int nds, reg_slot;
4c2c6516 6550 expressionS *exp;
c0f3af97 6551
922d8de8 6552 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6553 && i.tm.opcode_modifier.immext)
6554 {
6555 dest = i.operands - 2;
6556 gas_assert (dest == 3);
6557 }
922d8de8 6558 else
a683cc34 6559 dest = i.operands - 1;
c0f3af97 6560 nds = dest - 1;
922d8de8 6561
a683cc34
SP		 6562 /* There are 2 kinds of instructions:
6563 1. 5 operands: 4 register operands or 3 register operands
6564 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6565 VexW0 or VexW1. The destination must be either XMM, YMM or
6566 ZMM register.
a683cc34
SP		 6567 2. 4 operands: 4 register operands or 3 register operands
6568 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6569 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6570 || (i.reg_operands == 3 && i.mem_operands == 1))
6571 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6572 && (i.tm.opcode_modifier.veximmext
6573 || (i.imm_operands == 1
6574 && i.types[0].bitfield.vec_imm4
6575 && (i.tm.opcode_modifier.vexw == VEXW0
6576 || i.tm.opcode_modifier.vexw == VEXW1)
10c17abd 6577 && i.tm.operand_types[dest].bitfield.regsimd)));
a683cc34
SP		 6578
6579 if (i.imm_operands == 0)
6580 {
6581 /* When there is no immediate operand, generate an 8bit
6582 immediate operand to encode the first operand. */
6583 exp = &im_expressions[i.imm_operands++];
6584 i.op[i.operands].imms = exp;
6585 i.types[i.operands] = imm8;
6586 i.operands++;
6587 /* If VexW1 is set, the first operand is the source and
6588 the second operand is encoded in the immediate operand. */
6589 if (i.tm.opcode_modifier.vexw == VEXW1)
6590 {
6591 source = 0;
6592 reg_slot = 1;
6593 }
6594 else
6595 {
6596 source = 1;
6597 reg_slot = 0;
6598 }
6599
6600 /* FMA swaps REG and NDS. */
6601 if (i.tm.cpu_flags.bitfield.cpufma)
6602 {
6603 unsigned int tmp;
6604 tmp = reg_slot;
6605 reg_slot = nds;
6606 nds = tmp;
6607 }
6608
10c17abd 6609 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
a683cc34 6610 exp->X_op = O_constant;
4c692bc7 6611 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6612 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6613 }
922d8de8 6614 else
a683cc34
SP		 6615 {
6616 unsigned int imm_slot;
6617
6618 if (i.tm.opcode_modifier.vexw == VEXW0)
6619 {
6620 /* If VexW0 is set, the third operand is the source and
6621 the second operand is encoded in the immediate
6622 operand. */
6623 source = 2;
6624 reg_slot = 1;
6625 }
6626 else
6627 {
6628 /* VexW1 is set, the second operand is the source and
6629 the third operand is encoded in the immediate
6630 operand. */
6631 source = 1;
6632 reg_slot = 2;
6633 }
6634
6635 if (i.tm.opcode_modifier.immext)
6636 {
33eaf5de 6637 /* When ImmExt is set, the immediate byte is the last
a683cc34
SP		 6638 operand. */
6639 imm_slot = i.operands - 1;
6640 source--;
6641 reg_slot--;
6642 }
6643 else
6644 {
6645 imm_slot = 0;
6646
6647 /* Turn on Imm8 so that output_imm will generate it. */
6648 i.types[imm_slot].bitfield.imm8 = 1;
6649 }
6650
10c17abd 6651 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
a683cc34 6652 i.op[imm_slot].imms->X_add_number
4c692bc7 6653 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6654 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6655 }
6656
10c17abd 6657 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
dae39acc 6658 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6659 }
6660 else
6661 source = dest = 0;
29b0f896
AM		 6662
6663 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6664 implicit registers do not count. If there are 3 register
6665 operands, it must be a instruction with VexNDS. For a
6666 instruction with VexNDD, the destination register is encoded
6667 in VEX prefix. If there are 4 register operands, it must be
6668 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6669 if (i.mem_operands == 0
6670 && ((i.reg_operands == 2
2426c15f 6671 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6672 || (i.reg_operands == 3
2426c15f 6673 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6674 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6675 {
cab737b9
L		 6676 switch (i.operands)
6677 {
6678 case 2:
6679 source = 0;
6680 break;
6681 case 3:
c81128dc
L		 6682 /* When there are 3 operands, one of them may be immediate,
6683 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6684 the first operand must be shift count register (cl) or it
6685 is an instruction with VexNDS. */
9c2799c2 6686 gas_assert (i.imm_operands == 1
7ab9ffdd 6687 || (i.imm_operands == 0
2426c15f 6688 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6689 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6690 if (operand_type_check (i.types[0], imm)
6691 || i.types[0].bitfield.shiftcount)
6692 source = 1;
6693 else
6694 source = 0;
cab737b9
L		 6695 break;
6696 case 4:
368d64cc
L		 6697 /* When there are 4 operands, the first two must be 8bit
6698 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6699 one.
6700
6701 For instructions with VexNDS, if the first operand
6702 an imm8, the source operand is the 2nd one. If the last
6703 operand is imm8, the source operand is the first one. */
9c2799c2 6704 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6705 && i.types[0].bitfield.imm8
6706 && i.types[1].bitfield.imm8)
2426c15f 6707 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6708 && i.imm_operands == 1
6709 && (i.types[0].bitfield.imm8
43234a1e
L		 6710 || i.types[i.operands - 1].bitfield.imm8
6711 || i.rounding)));
9f2670f2
L		 6712 if (i.imm_operands == 2)
6713 source = 2;
6714 else
c0f3af97
L		 6715 {
6716 if (i.types[0].bitfield.imm8)
6717 source = 1;
6718 else
6719 source = 0;
6720 }
c0f3af97
L		 6721 break;
6722 case 5:
e771e7c9 6723 if (is_evex_encoding (&i.tm))
43234a1e
L		 6724 {
6725 /* For EVEX instructions, when there are 5 operands, the
6726 first one must be immediate operand. If the second one
6727 is immediate operand, the source operand is the 3th
6728 one. If the last one is immediate operand, the source
6729 operand is the 2nd one. */
6730 gas_assert (i.imm_operands == 2
6731 && i.tm.opcode_modifier.sae
6732 && operand_type_check (i.types[0], imm));
6733 if (operand_type_check (i.types[1], imm))
6734 source = 2;
6735 else if (operand_type_check (i.types[4], imm))
6736 source = 1;
6737 else
6738 abort ();
6739 }
cab737b9
L		 6740 break;
6741 default:
6742 abort ();
6743 }
6744
c0f3af97
L		 6745 if (!vex_3_sources)
6746 {
6747 dest = source + 1;
6748
43234a1e
L		 6749 /* RC/SAE operand could be between DEST and SRC. That happens
6750 when one operand is GPR and the other one is XMM/YMM/ZMM
6751 register. */
6752 if (i.rounding && i.rounding->operand == (int) dest)
6753 dest++;
6754
2426c15f 6755 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6756 {
43234a1e 6757 /* For instructions with VexNDS, the register-only source
c5d0745b 6758 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
43234a1e
L		 6759 register. It is encoded in VEX prefix. We need to
6760 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6761
6762 i386_operand_type op;
6763 unsigned int vvvv;
6764
6765 /* Check register-only source operand when two source
6766 operands are swapped. */
6767 if (!i.tm.operand_types[source].bitfield.baseindex
6768 && i.tm.operand_types[dest].bitfield.baseindex)
6769 {
6770 vvvv = source;
6771 source = dest;
6772 }
6773 else
6774 vvvv = dest;
6775
6776 op = i.tm.operand_types[vvvv];
fa99fab2 6777 op.bitfield.regmem = 0;
c0f3af97 6778 if ((dest + 1) >= i.operands
dc821c5f
JB		 6779 || ((!op.bitfield.reg
6780 || (!op.bitfield.dword && !op.bitfield.qword))
10c17abd 6781 && !op.bitfield.regsimd
43234a1e 6782 && !operand_type_equal (&op, &regmask)))
c0f3af97 6783 abort ();
f12dc422 6784 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6785 dest++;
6786 }
6787 }
29b0f896
AM		 6788
6789 i.rm.mode = 3;
6790 /* One of the register operands will be encoded in the i.tm.reg
6791 field, the other in the combined i.tm.mode and i.tm.regmem
6792 fields. If no form of this instruction supports a memory
6793 destination operand, then we assume the source operand may
6794 sometimes be a memory operand and so we need to store the
6795 destination in the i.rm.reg field. */
40fb9820
L		 6796 if (!i.tm.operand_types[dest].bitfield.regmem
6797 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6798 {
6799 i.rm.reg = i.op[dest].regs->reg_num;
6800 i.rm.regmem = i.op[source].regs->reg_num;
6801 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6802 i.rex |= REX_R;
43234a1e
L		 6803 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6804 i.vrex |= REX_R;
29b0f896 6805 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6806 i.rex |= REX_B;
43234a1e
L		 6807 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6808 i.vrex |= REX_B;
29b0f896
AM		 6809 }
6810 else
6811 {
6812 i.rm.reg = i.op[source].regs->reg_num;
6813 i.rm.regmem = i.op[dest].regs->reg_num;
6814 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6815 i.rex |= REX_B;
43234a1e
L		 6816 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6817 i.vrex |= REX_B;
29b0f896 6818 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6819 i.rex |= REX_R;
43234a1e
L		 6820 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6821 i.vrex |= REX_R;
29b0f896 6822 }
161a04f6 6823 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6824 {
40fb9820
L		 6825 if (!i.types[0].bitfield.control
6826 && !i.types[1].bitfield.control)
c4a530c5 6827 abort ();
161a04f6 6828 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6829 add_prefix (LOCK_PREFIX_OPCODE);
6830 }
29b0f896
AM		 6831 }
6832 else
6833 { /* If it's not 2 reg operands... */
c0f3af97
L		 6834 unsigned int mem;
6835
29b0f896
AM		 6836 if (i.mem_operands)
6837 {
6838 unsigned int fake_zero_displacement = 0;
99018f42 6839 unsigned int op;
4eed87de 6840
7ab9ffdd
L		 6841 for (op = 0; op < i.operands; op++)
6842 if (operand_type_check (i.types[op], anymem))
6843 break;
7ab9ffdd 6844 gas_assert (op < i.operands);
29b0f896 6845
6c30d220
L		 6846 if (i.tm.opcode_modifier.vecsib)
6847 {
6848 if (i.index_reg->reg_num == RegEiz
6849 || i.index_reg->reg_num == RegRiz)
6850 abort ();
6851
6852 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6853 if (!i.base_reg)
6854 {
6855 i.sib.base = NO_BASE_REGISTER;
6856 i.sib.scale = i.log2_scale_factor;
6857 i.types[op].bitfield.disp8 = 0;
6858 i.types[op].bitfield.disp16 = 0;
6859 i.types[op].bitfield.disp64 = 0;
43083a50 6860 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6c30d220
L		 6861 {
6862 /* Must be 32 bit */
6863 i.types[op].bitfield.disp32 = 1;
6864 i.types[op].bitfield.disp32s = 0;
6865 }
6866 else
6867 {
6868 i.types[op].bitfield.disp32 = 0;
6869 i.types[op].bitfield.disp32s = 1;
6870 }
6871 }
6872 i.sib.index = i.index_reg->reg_num;
6873 if ((i.index_reg->reg_flags & RegRex) != 0)
6874 i.rex |= REX_X;
43234a1e
L		 6875 if ((i.index_reg->reg_flags & RegVRex) != 0)
6876 i.vrex |= REX_X;
6c30d220
L		 6877 }
6878
29b0f896
AM		 6879 default_seg = &ds;
6880
6881 if (i.base_reg == 0)
6882 {
6883 i.rm.mode = 0;
6884 if (!i.disp_operands)
9bb129e8 6885 fake_zero_displacement = 1;
29b0f896
AM		 6886 if (i.index_reg == 0)
6887 {
73053c1f
JB		 6888 i386_operand_type newdisp;
6889
6c30d220 6890 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6891 /* Operand is just <disp> */
20f0a1fc 6892 if (flag_code == CODE_64BIT)
29b0f896
AM		 6893 {
6894 /* 64bit mode overwrites the 32bit absolute
6895 addressing by RIP relative addressing and
6896 absolute addressing is encoded by one of the
6897 redundant SIB forms. */
6898 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6899 i.sib.base = NO_BASE_REGISTER;
6900 i.sib.index = NO_INDEX_REGISTER;
73053c1f 6901 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
20f0a1fc 6902 }
fc225355
L		 6903 else if ((flag_code == CODE_16BIT)
6904 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6905 {
6906 i.rm.regmem = NO_BASE_REGISTER_16;
73053c1f 6907 newdisp = disp16;
20f0a1fc
NC		 6908 }
6909 else
6910 {
6911 i.rm.regmem = NO_BASE_REGISTER;
73053c1f 6912 newdisp = disp32;
29b0f896 6913 }
73053c1f
JB		 6914 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6915 i.types[op] = operand_type_or (i.types[op], newdisp);
29b0f896 6916 }
6c30d220 6917 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6918 {
6c30d220 6919 /* !i.base_reg && i.index_reg */
db51cc60
L		 6920 if (i.index_reg->reg_num == RegEiz
6921 || i.index_reg->reg_num == RegRiz)
6922 i.sib.index = NO_INDEX_REGISTER;
6923 else
6924 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6925 i.sib.base = NO_BASE_REGISTER;
6926 i.sib.scale = i.log2_scale_factor;
6927 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 6928 i.types[op].bitfield.disp8 = 0;
6929 i.types[op].bitfield.disp16 = 0;
6930 i.types[op].bitfield.disp64 = 0;
43083a50 6931 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
40fb9820
L		 6932 {
6933 /* Must be 32 bit */
6934 i.types[op].bitfield.disp32 = 1;
6935 i.types[op].bitfield.disp32s = 0;
6936 }
29b0f896 6937 else
40fb9820
L		 6938 {
6939 i.types[op].bitfield.disp32 = 0;
6940 i.types[op].bitfield.disp32s = 1;
6941 }
29b0f896 6942 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6943 i.rex |= REX_X;
29b0f896
AM		 6944 }
6945 }
6946 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6947 else if (i.base_reg->reg_num == RegRip ||
6948 i.base_reg->reg_num == RegEip)
29b0f896 6949 {
6c30d220 6950 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6951 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6952 i.types[op].bitfield.disp8 = 0;
6953 i.types[op].bitfield.disp16 = 0;
6954 i.types[op].bitfield.disp32 = 0;
6955 i.types[op].bitfield.disp32s = 1;
6956 i.types[op].bitfield.disp64 = 0;
71903a11 6957 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6958 if (! i.disp_operands)
6959 fake_zero_displacement = 1;
29b0f896 6960 }
dc821c5f 6961 else if (i.base_reg->reg_type.bitfield.word)
29b0f896 6962 {
6c30d220 6963 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6964 switch (i.base_reg->reg_num)
6965 {
6966 case 3: /* (%bx) */
6967 if (i.index_reg == 0)
6968 i.rm.regmem = 7;
6969 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6970 i.rm.regmem = i.index_reg->reg_num - 6;
6971 break;
6972 case 5: /* (%bp) */
6973 default_seg = &ss;
6974 if (i.index_reg == 0)
6975 {
6976 i.rm.regmem = 6;
40fb9820 6977 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6978 {
6979 /* fake (%bp) into 0(%bp) */
b5014f7a 6980 i.types[op].bitfield.disp8 = 1;
252b5132 6981 fake_zero_displacement = 1;
29b0f896
AM		 6982 }
6983 }
6984 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6985 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6986 break;
6987 default: /* (%si) -> 4 or (%di) -> 5 */
6988 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6989 }
6990 i.rm.mode = mode_from_disp_size (i.types[op]);
6991 }
6992 else /* i.base_reg and 32/64 bit mode */
6993 {
6994 if (flag_code == CODE_64BIT
40fb9820
L		 6995 && operand_type_check (i.types[op], disp))
6996 {
73053c1f
JB		 6997 i.types[op].bitfield.disp16 = 0;
6998 i.types[op].bitfield.disp64 = 0;
40fb9820 6999 if (i.prefix[ADDR_PREFIX] == 0)
73053c1f
JB		 7000 {
7001 i.types[op].bitfield.disp32 = 0;
7002 i.types[op].bitfield.disp32s = 1;
7003 }
40fb9820 7004 else
73053c1f
JB		 7005 {
7006 i.types[op].bitfield.disp32 = 1;
7007 i.types[op].bitfield.disp32s = 0;
7008 }
40fb9820 7009 }
20f0a1fc 7010
6c30d220
L		 7011 if (!i.tm.opcode_modifier.vecsib)
7012 i.rm.regmem = i.base_reg->reg_num;
29b0f896 7013 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 7014 i.rex |= REX_B;
29b0f896
AM		 7015 i.sib.base = i.base_reg->reg_num;
7016 /* x86-64 ignores REX prefix bit here to avoid decoder
7017 complications. */
848930b2
JB		 7018 if (!(i.base_reg->reg_flags & RegRex)
7019 && (i.base_reg->reg_num == EBP_REG_NUM
7020 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 7021 default_seg = &ss;
848930b2 7022 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 7023 {
848930b2 7024 fake_zero_displacement = 1;
b5014f7a 7025 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 7026 }
7027 i.sib.scale = i.log2_scale_factor;
7028 if (i.index_reg == 0)
7029 {
6c30d220 7030 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 7031 /* <disp>(%esp) becomes two byte modrm with no index
7032 register. We've already stored the code for esp
7033 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7034 Any base register besides %esp will not use the
7035 extra modrm byte. */
7036 i.sib.index = NO_INDEX_REGISTER;
29b0f896 7037 }
6c30d220 7038 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 7039 {
db51cc60
L		 7040 if (i.index_reg->reg_num == RegEiz
7041 || i.index_reg->reg_num == RegRiz)
7042 i.sib.index = NO_INDEX_REGISTER;
7043 else
7044 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 7045 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7046 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 7047 i.rex |= REX_X;
29b0f896 7048 }
67a4f2b7
AO		 7049
7050 if (i.disp_operands
7051 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7052 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7053 i.rm.mode = 0;
7054 else
a501d77e
L		 7055 {
7056 if (!fake_zero_displacement
7057 && !i.disp_operands
7058 && i.disp_encoding)
7059 {
7060 fake_zero_displacement = 1;
7061 if (i.disp_encoding == disp_encoding_8bit)
7062 i.types[op].bitfield.disp8 = 1;
7063 else
7064 i.types[op].bitfield.disp32 = 1;
7065 }
7066 i.rm.mode = mode_from_disp_size (i.types[op]);
7067 }
29b0f896 7068 }
252b5132 7069
29b0f896
AM		 7070 if (fake_zero_displacement)
7071 {
7072 /* Fakes a zero displacement assuming that i.types[op]
7073 holds the correct displacement size. */
7074 expressionS *exp;
7075
9c2799c2 7076 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 7077 exp = &disp_expressions[i.disp_operands++];
7078 i.op[op].disps = exp;
7079 exp->X_op = O_constant;
7080 exp->X_add_number = 0;
7081 exp->X_add_symbol = (symbolS *) 0;
7082 exp->X_op_symbol = (symbolS *) 0;
7083 }
c0f3af97
L		 7084
7085 mem = op;
29b0f896 7086 }
c0f3af97
L		 7087 else
7088 mem = ~0;
252b5132 7089
8c43a48b 7090 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 7091 {
7092 if (operand_type_check (i.types[0], imm))
7093 i.vex.register_specifier = NULL;
7094 else
7095 {
7096 /* VEX.vvvv encodes one of the sources when the first
7097 operand is not an immediate. */
1ef99a7b 7098 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7099 i.vex.register_specifier = i.op[0].regs;
7100 else
7101 i.vex.register_specifier = i.op[1].regs;
7102 }
7103
7104 /* Destination is a XMM register encoded in the ModRM.reg
7105 and VEX.R bit. */
7106 i.rm.reg = i.op[2].regs->reg_num;
7107 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7108 i.rex |= REX_R;
7109
7110 /* ModRM.rm and VEX.B encodes the other source. */
7111 if (!i.mem_operands)
7112 {
7113 i.rm.mode = 3;
7114
1ef99a7b 7115 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7116 i.rm.regmem = i.op[1].regs->reg_num;
7117 else
7118 i.rm.regmem = i.op[0].regs->reg_num;
7119
7120 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7121 i.rex |= REX_B;
7122 }
7123 }
2426c15f 7124 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 7125 {
7126 i.vex.register_specifier = i.op[2].regs;
7127 if (!i.mem_operands)
7128 {
7129 i.rm.mode = 3;
7130 i.rm.regmem = i.op[1].regs->reg_num;
7131 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7132 i.rex |= REX_B;
7133 }
7134 }
29b0f896
AM		 7135 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7136 (if any) based on i.tm.extension_opcode. Again, we must be
7137 careful to make sure that segment/control/debug/test/MMX
7138 registers are coded into the i.rm.reg field. */
f88c9eb0 7139 else if (i.reg_operands)
29b0f896 7140 {
99018f42 7141 unsigned int op;
7ab9ffdd
L		 7142 unsigned int vex_reg = ~0;
7143
7144 for (op = 0; op < i.operands; op++)
dc821c5f 7145 if (i.types[op].bitfield.reg
7ab9ffdd 7146 || i.types[op].bitfield.regmmx
1b54b8d7 7147 || i.types[op].bitfield.regsimd
7e8b059b 7148 || i.types[op].bitfield.regbnd
43234a1e 7149 || i.types[op].bitfield.regmask
7ab9ffdd
L		 7150 || i.types[op].bitfield.sreg2
7151 || i.types[op].bitfield.sreg3
7152 || i.types[op].bitfield.control
7153 || i.types[op].bitfield.debug
7154 || i.types[op].bitfield.test)
7155 break;
c0209578 7156
7ab9ffdd
L		 7157 if (vex_3_sources)
7158 op = dest;
2426c15f 7159 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 7160 {
7161 /* For instructions with VexNDS, the register-only
7162 source operand is encoded in VEX prefix. */
7163 gas_assert (mem != (unsigned int) ~0);
c0f3af97 7164
7ab9ffdd 7165 if (op > mem)
c0f3af97 7166 {
7ab9ffdd
L		 7167 vex_reg = op++;
7168 gas_assert (op < i.operands);
c0f3af97
L		 7169 }
7170 else
c0f3af97 7171 {
f12dc422
L		 7172 /* Check register-only source operand when two source
7173 operands are swapped. */
7174 if (!i.tm.operand_types[op].bitfield.baseindex
7175 && i.tm.operand_types[op + 1].bitfield.baseindex)
7176 {
7177 vex_reg = op;
7178 op += 2;
7179 gas_assert (mem == (vex_reg + 1)
7180 && op < i.operands);
7181 }
7182 else
7183 {
7184 vex_reg = op + 1;
7185 gas_assert (vex_reg < i.operands);
7186 }
c0f3af97 7187 }
7ab9ffdd 7188 }
2426c15f 7189 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 7190 {
f12dc422 7191 /* For instructions with VexNDD, the register destination
7ab9ffdd 7192 is encoded in VEX prefix. */
f12dc422
L		 7193 if (i.mem_operands == 0)
7194 {
7195 /* There is no memory operand. */
7196 gas_assert ((op + 2) == i.operands);
7197 vex_reg = op + 1;
7198 }
7199 else
8d63c93e 7200 {
ed438a93
JB		 7201 /* There are only 2 non-immediate operands. */
7202 gas_assert (op < i.imm_operands + 2
7203 && i.operands == i.imm_operands + 2);
7204 vex_reg = i.imm_operands + 1;
f12dc422 7205 }
7ab9ffdd
L		 7206 }
7207 else
7208 gas_assert (op < i.operands);
99018f42 7209
7ab9ffdd
L		 7210 if (vex_reg != (unsigned int) ~0)
7211 {
f12dc422 7212 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 7213
dc821c5f
JB		 7214 if ((!type->bitfield.reg
7215 || (!type->bitfield.dword && !type->bitfield.qword))
10c17abd 7216 && !type->bitfield.regsimd
43234a1e 7217 && !operand_type_equal (type, &regmask))
7ab9ffdd 7218 abort ();
f88c9eb0 7219
7ab9ffdd
L		 7220 i.vex.register_specifier = i.op[vex_reg].regs;
7221 }
7222
1b9f0c97
L		 7223 /* Don't set OP operand twice. */
7224 if (vex_reg != op)
7ab9ffdd 7225 {
1b9f0c97
L		 7226 /* If there is an extension opcode to put here, the
7227 register number must be put into the regmem field. */
7228 if (i.tm.extension_opcode != None)
7229 {
7230 i.rm.regmem = i.op[op].regs->reg_num;
7231 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7232 i.rex |= REX_B;
43234a1e
L		 7233 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7234 i.vrex |= REX_B;
1b9f0c97
L		 7235 }
7236 else
7237 {
7238 i.rm.reg = i.op[op].regs->reg_num;
7239 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7240 i.rex |= REX_R;
43234a1e
L		 7241 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7242 i.vrex |= REX_R;
1b9f0c97 7243 }
7ab9ffdd 7244 }
252b5132 7245
29b0f896
AM		 7246 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7247 must set it to 3 to indicate this is a register operand
7248 in the regmem field. */
7249 if (!i.mem_operands)
7250 i.rm.mode = 3;
7251 }
252b5132 7252
29b0f896 7253 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 7254 if (i.tm.extension_opcode != None)
29b0f896
AM		 7255 i.rm.reg = i.tm.extension_opcode;
7256 }
7257 return default_seg;
7258}
252b5132 7259
29b0f896 7260static void
e3bb37b5 7261output_branch (void)
29b0f896
AM		 7262{
7263 char *p;
f8a5c266 7264 int size;
29b0f896
AM		 7265 int code16;
7266 int prefix;
7267 relax_substateT subtype;
7268 symbolS *sym;
7269 offsetT off;
7270
f8a5c266 7271 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 7272 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 7273
7274 prefix = 0;
7275 if (i.prefix[DATA_PREFIX] != 0)
252b5132 7276 {
29b0f896
AM		 7277 prefix = 1;
7278 i.prefixes -= 1;
7279 code16 ^= CODE16;
252b5132 7280 }
29b0f896
AM		 7281 /* Pentium4 branch hints. */
7282 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7283 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 7284 {
29b0f896
AM		 7285 prefix++;
7286 i.prefixes--;
7287 }
7288 if (i.prefix[REX_PREFIX] != 0)
7289 {
7290 prefix++;
7291 i.prefixes--;
2f66722d
AM		 7292 }
7293
7e8b059b
L		 7294 /* BND prefixed jump. */
7295 if (i.prefix[BND_PREFIX] != 0)
7296 {
7297 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7298 i.prefixes -= 1;
7299 }
7300
29b0f896
AM		 7301 if (i.prefixes != 0 && !intel_syntax)
7302 as_warn (_("skipping prefixes on this instruction"));
7303
7304 /* It's always a symbol; End frag & setup for relax.
7305 Make sure there is enough room in this frag for the largest
7306 instruction we may generate in md_convert_frag. This is 2
7307 bytes for the opcode and room for the prefix and largest
7308 displacement. */
7309 frag_grow (prefix + 2 + 4);
7310 /* Prefix and 1 opcode byte go in fr_fix. */
7311 p = frag_more (prefix + 1);
7312 if (i.prefix[DATA_PREFIX] != 0)
7313 *p++ = DATA_PREFIX_OPCODE;
7314 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7315 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7316 *p++ = i.prefix[SEG_PREFIX];
7317 if (i.prefix[REX_PREFIX] != 0)
7318 *p++ = i.prefix[REX_PREFIX];
7319 *p = i.tm.base_opcode;
7320
7321 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 7322 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 7323 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 7324 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 7325 else
f8a5c266 7326 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 7327 subtype |= code16;
3e73aa7c 7328
29b0f896
AM		 7329 sym = i.op[0].disps->X_add_symbol;
7330 off = i.op[0].disps->X_add_number;
3e73aa7c 7331
29b0f896
AM		 7332 if (i.op[0].disps->X_op != O_constant
7333 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7334 {
29b0f896
AM		 7335 /* Handle complex expressions. */
7336 sym = make_expr_symbol (i.op[0].disps);
7337 off = 0;
7338 }
3e73aa7c 7339
29b0f896
AM		 7340 /* 1 possible extra opcode + 4 byte displacement go in var part.
7341 Pass reloc in fr_var. */
d258b828 7342 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7343}
3e73aa7c 7344
bd7ab16b
L		 7345#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7346/* Return TRUE iff PLT32 relocation should be used for branching to
7347 symbol S. */
7348
7349static bfd_boolean
7350need_plt32_p (symbolS *s)
7351{
7352 /* PLT32 relocation is ELF only. */
7353 if (!IS_ELF)
7354 return FALSE;
7355
7356 /* Since there is no need to prepare for PLT branch on x86-64, we
7357 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7358 be used as a marker for 32-bit PC-relative branches. */
7359 if (!object_64bit)
7360 return FALSE;
7361
7362 /* Weak or undefined symbol need PLT32 relocation. */
7363 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7364 return TRUE;
7365
7366 /* Non-global symbol doesn't need PLT32 relocation. */
7367 if (! S_IS_EXTERNAL (s))
7368 return FALSE;
7369
7370 /* Other global symbols need PLT32 relocation. NB: Symbol with
7371 non-default visibilities are treated as normal global symbol
7372 so that PLT32 relocation can be used as a marker for 32-bit
7373 PC-relative branches. It is useful for linker relaxation. */
7374 return TRUE;
7375}
7376#endif
7377
29b0f896 7378static void
e3bb37b5 7379output_jump (void)
29b0f896
AM		 7380{
7381 char *p;
7382 int size;
3e02c1cc 7383 fixS *fixP;
bd7ab16b 7384 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
29b0f896 7385
40fb9820 7386 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7387 {
7388 /* This is a loop or jecxz type instruction. */
7389 size = 1;
7390 if (i.prefix[ADDR_PREFIX] != 0)
7391 {
7392 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7393 i.prefixes -= 1;
7394 }
7395 /* Pentium4 branch hints. */
7396 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7397 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7398 {
7399 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7400 i.prefixes--;
3e73aa7c
JH		 7401 }
7402 }
29b0f896
AM		 7403 else
7404 {
7405 int code16;
3e73aa7c 7406
29b0f896
AM		 7407 code16 = 0;
7408 if (flag_code == CODE_16BIT)
7409 code16 = CODE16;
3e73aa7c 7410
29b0f896
AM		 7411 if (i.prefix[DATA_PREFIX] != 0)
7412 {
7413 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7414 i.prefixes -= 1;
7415 code16 ^= CODE16;
7416 }
252b5132 7417
29b0f896
AM		 7418 size = 4;
7419 if (code16)
7420 size = 2;
7421 }
9fcc94b6 7422
29b0f896
AM		 7423 if (i.prefix[REX_PREFIX] != 0)
7424 {
7425 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7426 i.prefixes -= 1;
7427 }
252b5132 7428
7e8b059b
L		 7429 /* BND prefixed jump. */
7430 if (i.prefix[BND_PREFIX] != 0)
7431 {
7432 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7433 i.prefixes -= 1;
7434 }
7435
29b0f896
AM		 7436 if (i.prefixes != 0 && !intel_syntax)
7437 as_warn (_("skipping prefixes on this instruction"));
e0890092 7438
42164a71
L		 7439 p = frag_more (i.tm.opcode_length + size);
7440 switch (i.tm.opcode_length)
7441 {
7442 case 2:
7443 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7444 /* Fall through. */
42164a71
L		 7445 case 1:
7446 *p++ = i.tm.base_opcode;
7447 break;
7448 default:
7449 abort ();
7450 }
e0890092 7451
bd7ab16b
L		 7452#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7453 if (size == 4
7454 && jump_reloc == NO_RELOC
7455 && need_plt32_p (i.op[0].disps->X_add_symbol))
7456 jump_reloc = BFD_RELOC_X86_64_PLT32;
7457#endif
7458
7459 jump_reloc = reloc (size, 1, 1, jump_reloc);
7460
3e02c1cc 7461 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
bd7ab16b 7462 i.op[0].disps, 1, jump_reloc);
3e02c1cc
AM		 7463
7464 /* All jumps handled here are signed, but don't use a signed limit
7465 check for 32 and 16 bit jumps as we want to allow wrap around at
7466 4G and 64k respectively. */
7467 if (size == 1)
7468 fixP->fx_signed = 1;
29b0f896 7469}
e0890092 7470
29b0f896 7471static void
e3bb37b5 7472output_interseg_jump (void)
29b0f896
AM		 7473{
7474 char *p;
7475 int size;
7476 int prefix;
7477 int code16;
252b5132 7478
29b0f896
AM		 7479 code16 = 0;
7480 if (flag_code == CODE_16BIT)
7481 code16 = CODE16;
a217f122 7482
29b0f896
AM		 7483 prefix = 0;
7484 if (i.prefix[DATA_PREFIX] != 0)
7485 {
7486 prefix = 1;
7487 i.prefixes -= 1;
7488 code16 ^= CODE16;
7489 }
7490 if (i.prefix[REX_PREFIX] != 0)
7491 {
7492 prefix++;
7493 i.prefixes -= 1;
7494 }
252b5132 7495
29b0f896
AM		 7496 size = 4;
7497 if (code16)
7498 size = 2;
252b5132 7499
29b0f896
AM		 7500 if (i.prefixes != 0 && !intel_syntax)
7501 as_warn (_("skipping prefixes on this instruction"));
252b5132 7502
29b0f896
AM		 7503 /* 1 opcode; 2 segment; offset */
7504 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7505
29b0f896
AM		 7506 if (i.prefix[DATA_PREFIX] != 0)
7507 *p++ = DATA_PREFIX_OPCODE;
252b5132 7508
29b0f896
AM		 7509 if (i.prefix[REX_PREFIX] != 0)
7510 *p++ = i.prefix[REX_PREFIX];
252b5132 7511
29b0f896
AM		 7512 *p++ = i.tm.base_opcode;
7513 if (i.op[1].imms->X_op == O_constant)
7514 {
7515 offsetT n = i.op[1].imms->X_add_number;
252b5132 7516
29b0f896
AM		 7517 if (size == 2
7518 && !fits_in_unsigned_word (n)
7519 && !fits_in_signed_word (n))
7520 {
7521 as_bad (_("16-bit jump out of range"));
7522 return;
7523 }
7524 md_number_to_chars (p, n, size);
7525 }
7526 else
7527 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7528 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7529 if (i.op[0].imms->X_op != O_constant)
7530 as_bad (_("can't handle non absolute segment in `%s'"),
7531 i.tm.name);
7532 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7533}
a217f122 7534
29b0f896 7535static void
e3bb37b5 7536output_insn (void)
29b0f896 7537{
2bbd9c25
JJ		 7538 fragS *insn_start_frag;
7539 offsetT insn_start_off;
7540
29b0f896
AM		 7541 /* Tie dwarf2 debug info to the address at the start of the insn.
7542 We can't do this after the insn has been output as the current
7543 frag may have been closed off. eg. by frag_var. */
7544 dwarf2_emit_insn (0);
7545
2bbd9c25
JJ		 7546 insn_start_frag = frag_now;
7547 insn_start_off = frag_now_fix ();
7548
29b0f896 7549 /* Output jumps. */
40fb9820 7550 if (i.tm.opcode_modifier.jump)
29b0f896 7551 output_branch ();
40fb9820
L		 7552 else if (i.tm.opcode_modifier.jumpbyte
7553 || i.tm.opcode_modifier.jumpdword)
29b0f896 7554 output_jump ();
40fb9820 7555 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7556 output_interseg_jump ();
7557 else
7558 {
7559 /* Output normal instructions here. */
7560 char *p;
7561 unsigned char *q;
47465058 7562 unsigned int j;
331d2d0d 7563 unsigned int prefix;
4dffcebc 7564
e4e00185
AS		 7565 if (avoid_fence
7566 && i.tm.base_opcode == 0xfae
7567 && i.operands == 1
7568 && i.imm_operands == 1
7569 && (i.op[0].imms->X_add_number == 0xe8
7570 || i.op[0].imms->X_add_number == 0xf0
7571 || i.op[0].imms->X_add_number == 0xf8))
7572 {
7573 /* Encode lfence, mfence, and sfence as
7574 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7575 offsetT val = 0x240483f0ULL;
7576 p = frag_more (5);
7577 md_number_to_chars (p, val, 5);
7578 return;
7579 }
7580
d022bddd
IT		 7581 /* Some processors fail on LOCK prefix. This options makes
7582 assembler ignore LOCK prefix and serves as a workaround. */
7583 if (omit_lock_prefix)
7584 {
7585 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7586 return;
7587 i.prefix[LOCK_PREFIX] = 0;
7588 }
7589
43234a1e
L		 7590 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7591 don't need the explicit prefix. */
7592 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7593 {
c0f3af97 7594 switch (i.tm.opcode_length)
bc4bd9ab 7595 {
c0f3af97
L		 7596 case 3:
7597 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7598 {
c0f3af97
L		 7599 prefix = (i.tm.base_opcode >> 24) & 0xff;
7600 goto check_prefix;
7601 }
7602 break;
7603 case 2:
7604 if ((i.tm.base_opcode & 0xff0000) != 0)
7605 {
7606 prefix = (i.tm.base_opcode >> 16) & 0xff;
7607 if (i.tm.cpu_flags.bitfield.cpupadlock)
7608 {
4dffcebc 7609check_prefix:
c0f3af97 7610 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7611 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7612 != REPE_PREFIX_OPCODE))
7613 add_prefix (prefix);
7614 }
7615 else
4dffcebc
L		 7616 add_prefix (prefix);
7617 }
c0f3af97
L		 7618 break;
7619 case 1:
7620 break;
390c91cf
L		 7621 case 0:
7622 /* Check for pseudo prefixes. */
7623 as_bad_where (insn_start_frag->fr_file,
7624 insn_start_frag->fr_line,
7625 _("pseudo prefix without instruction"));
7626 return;
c0f3af97
L		 7627 default:
7628 abort ();
bc4bd9ab 7629 }
c0f3af97 7630
6d19a37a 7631#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7632 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7633 R_X86_64_GOTTPOFF relocation so that linker can safely
7634 perform IE->LE optimization. */
7635 if (x86_elf_abi == X86_64_X32_ABI
7636 && i.operands == 2
7637 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7638 && i.prefix[REX_PREFIX] == 0)
7639 add_prefix (REX_OPCODE);
6d19a37a 7640#endif
cf61b747 7641
c0f3af97
L		 7642 /* The prefix bytes. */
7643 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7644 if (*q)
7645 FRAG_APPEND_1_CHAR (*q);
0f10071e 7646 }
ae5c1c7b 7647 else
c0f3af97
L		 7648 {
7649 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7650 if (*q)
7651 switch (j)
7652 {
7653 case REX_PREFIX:
7654 /* REX byte is encoded in VEX prefix. */
7655 break;
7656 case SEG_PREFIX:
7657 case ADDR_PREFIX:
7658 FRAG_APPEND_1_CHAR (*q);
7659 break;
7660 default:
7661 /* There should be no other prefixes for instructions
7662 with VEX prefix. */
7663 abort ();
7664 }
7665
43234a1e
L		 7666 /* For EVEX instructions i.vrex should become 0 after
7667 build_evex_prefix. For VEX instructions upper 16 registers
7668 aren't available, so VREX should be 0. */
7669 if (i.vrex)
7670 abort ();
c0f3af97
L		 7671 /* Now the VEX prefix. */
7672 p = frag_more (i.vex.length);
7673 for (j = 0; j < i.vex.length; j++)
7674 p[j] = i.vex.bytes[j];
7675 }
252b5132 7676
29b0f896 7677 /* Now the opcode; be careful about word order here! */
4dffcebc 7678 if (i.tm.opcode_length == 1)
29b0f896
AM		 7679 {
7680 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7681 }
7682 else
7683 {
4dffcebc 7684 switch (i.tm.opcode_length)
331d2d0d 7685 {
43234a1e
L		 7686 case 4:
7687 p = frag_more (4);
7688 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7689 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7690 break;
4dffcebc 7691 case 3:
331d2d0d
L		 7692 p = frag_more (3);
7693 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7694 break;
7695 case 2:
7696 p = frag_more (2);
7697 break;
7698 default:
7699 abort ();
7700 break;
331d2d0d 7701 }
0f10071e 7702
29b0f896
AM		 7703 /* Put out high byte first: can't use md_number_to_chars! */
7704 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7705 *p = i.tm.base_opcode & 0xff;
7706 }
3e73aa7c 7707
29b0f896 7708 /* Now the modrm byte and sib byte (if present). */
40fb9820 7709 if (i.tm.opcode_modifier.modrm)
29b0f896 7710 {
4a3523fa
L		 7711 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7712 | i.rm.reg << 3
7713 | i.rm.mode << 6));
29b0f896
AM		 7714 /* If i.rm.regmem == ESP (4)
7715 && i.rm.mode != (Register mode)
7716 && not 16 bit
7717 ==> need second modrm byte. */
7718 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7719 && i.rm.mode != 3
dc821c5f 7720 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
4a3523fa
L		 7721 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7722 | i.sib.index << 3
7723 | i.sib.scale << 6));
29b0f896 7724 }
3e73aa7c 7725
29b0f896 7726 if (i.disp_operands)
2bbd9c25 7727 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7728
29b0f896 7729 if (i.imm_operands)
2bbd9c25 7730 output_imm (insn_start_frag, insn_start_off);
29b0f896 7731 }
252b5132 7732
29b0f896
AM		 7733#ifdef DEBUG386
7734 if (flag_debug)
7735 {
7b81dfbb 7736 pi ("" /*line*/, &i);
29b0f896
AM		 7737 }
7738#endif /* DEBUG386 */
7739}
252b5132 7740
e205caa7
L		 7741/* Return the size of the displacement operand N. */
7742
7743static int
7744disp_size (unsigned int n)
7745{
7746 int size = 4;
43234a1e 7747
b5014f7a 7748 if (i.types[n].bitfield.disp64)
40fb9820
L		 7749 size = 8;
7750 else if (i.types[n].bitfield.disp8)
7751 size = 1;
7752 else if (i.types[n].bitfield.disp16)
7753 size = 2;
e205caa7
L		 7754 return size;
7755}
7756
7757/* Return the size of the immediate operand N. */
7758
7759static int
7760imm_size (unsigned int n)
7761{
7762 int size = 4;
40fb9820
L		 7763 if (i.types[n].bitfield.imm64)
7764 size = 8;
7765 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7766 size = 1;
7767 else if (i.types[n].bitfield.imm16)
7768 size = 2;
e205caa7
L		 7769 return size;
7770}
7771
29b0f896 7772static void
64e74474 7773output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7774{
7775 char *p;
7776 unsigned int n;
252b5132 7777
29b0f896
AM		 7778 for (n = 0; n < i.operands; n++)
7779 {
b5014f7a 7780 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 7781 {
7782 if (i.op[n].disps->X_op == O_constant)
7783 {
e205caa7 7784 int size = disp_size (n);
43234a1e 7785 offsetT val = i.op[n].disps->X_add_number;
252b5132 7786
b5014f7a 7787 val = offset_in_range (val >> i.memshift, size);
29b0f896
AM		 7788 p = frag_more (size);
7789 md_number_to_chars (p, val, size);
7790 }
7791 else
7792 {
f86103b7 7793 enum bfd_reloc_code_real reloc_type;
e205caa7 7794 int size = disp_size (n);
40fb9820 7795 int sign = i.types[n].bitfield.disp32s;
29b0f896 7796 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7797 fixS *fixP;
29b0f896 7798
e205caa7 7799 /* We can't have 8 bit displacement here. */
9c2799c2 7800 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7801
29b0f896
AM		 7802 /* The PC relative address is computed relative
7803 to the instruction boundary, so in case immediate
7804 fields follows, we need to adjust the value. */
7805 if (pcrel && i.imm_operands)
7806 {
29b0f896 7807 unsigned int n1;
e205caa7 7808 int sz = 0;
252b5132 7809
29b0f896 7810 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7811 if (operand_type_check (i.types[n1], imm))
252b5132 7812 {
e205caa7
L		 7813 /* Only one immediate is allowed for PC
7814 relative address. */
9c2799c2 7815 gas_assert (sz == 0);
e205caa7
L		 7816 sz = imm_size (n1);
7817 i.op[n].disps->X_add_number -= sz;
252b5132 7818 }
29b0f896 7819 /* We should find the immediate. */
9c2799c2 7820 gas_assert (sz != 0);
29b0f896 7821 }
520dc8e8 7822
29b0f896 7823 p = frag_more (size);
d258b828 7824 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7825 if (GOT_symbol
2bbd9c25 7826 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7827 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7828 || reloc_type == BFD_RELOC_X86_64_32S
7829 || (reloc_type == BFD_RELOC_64
7830 && object_64bit))
d6ab8113
JB		 7831 && (i.op[n].disps->X_op == O_symbol
7832 || (i.op[n].disps->X_op == O_add
7833 && ((symbol_get_value_expression
7834 (i.op[n].disps->X_op_symbol)->X_op)
7835 == O_subtract))))
7836 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7837 {
7838 offsetT add;
7839
7840 if (insn_start_frag == frag_now)
7841 add = (p - frag_now->fr_literal) - insn_start_off;
7842 else
7843 {
7844 fragS *fr;
7845
7846 add = insn_start_frag->fr_fix - insn_start_off;
7847 for (fr = insn_start_frag->fr_next;
7848 fr && fr != frag_now; fr = fr->fr_next)
7849 add += fr->fr_fix;
7850 add += p - frag_now->fr_literal;
7851 }
7852
4fa24527 7853 if (!object_64bit)
7b81dfbb
AJ		 7854 {
7855 reloc_type = BFD_RELOC_386_GOTPC;
7856 i.op[n].imms->X_add_number += add;
7857 }
7858 else if (reloc_type == BFD_RELOC_64)
7859 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7860 else
7b81dfbb
AJ		 7861 /* Don't do the adjustment for x86-64, as there
7862 the pcrel addressing is relative to the _next_
7863 insn, and that is taken care of in other code. */
d6ab8113 7864 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7865 }
02a86693
L		 7866 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7867 size, i.op[n].disps, pcrel,
7868 reloc_type);
7869 /* Check for "call/jmp *mem", "mov mem, %reg",
7870 "test %reg, mem" and "binop mem, %reg" where binop
7871 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7872 instructions. Always generate R_386_GOT32X for
7873 "sym*GOT" operand in 32-bit mode. */
7874 if ((generate_relax_relocations
7875 || (!object_64bit
7876 && i.rm.mode == 0
7877 && i.rm.regmem == 5))
7878 && (i.rm.mode == 2
7879 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7880 && ((i.operands == 1
7881 && i.tm.base_opcode == 0xff
7882 && (i.rm.reg == 2 || i.rm.reg == 4))
7883 || (i.operands == 2
7884 && (i.tm.base_opcode == 0x8b
7885 || i.tm.base_opcode == 0x85
7886 || (i.tm.base_opcode & 0xc7) == 0x03))))
7887 {
7888 if (object_64bit)
7889 {
7890 fixP->fx_tcbit = i.rex != 0;
7891 if (i.base_reg
7892 && (i.base_reg->reg_num == RegRip
7893 || i.base_reg->reg_num == RegEip))
7894 fixP->fx_tcbit2 = 1;
7895 }
7896 else
7897 fixP->fx_tcbit2 = 1;
7898 }
29b0f896
AM		 7899 }
7900 }
7901 }
7902}
252b5132 7903
29b0f896 7904static void
64e74474 7905output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7906{
7907 char *p;
7908 unsigned int n;
252b5132 7909
29b0f896
AM		 7910 for (n = 0; n < i.operands; n++)
7911 {
43234a1e
L		 7912 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7913 if (i.rounding && (int) n == i.rounding->operand)
7914 continue;
7915
40fb9820 7916 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7917 {
7918 if (i.op[n].imms->X_op == O_constant)
7919 {
e205caa7 7920 int size = imm_size (n);
29b0f896 7921 offsetT val;
b4cac588 7922
29b0f896
AM		 7923 val = offset_in_range (i.op[n].imms->X_add_number,
7924 size);
7925 p = frag_more (size);
7926 md_number_to_chars (p, val, size);
7927 }
7928 else
7929 {
7930 /* Not absolute_section.
7931 Need a 32-bit fixup (don't support 8bit
7932 non-absolute imms). Try to support other
7933 sizes ... */
f86103b7 7934 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7935 int size = imm_size (n);
7936 int sign;
29b0f896 7937
40fb9820 7938 if (i.types[n].bitfield.imm32s
a7d61044 7939 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7940 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7941 sign = 1;
e205caa7
L		 7942 else
7943 sign = 0;
520dc8e8 7944
29b0f896 7945 p = frag_more (size);
d258b828 7946 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7947
2bbd9c25
JJ		 7948 /* This is tough to explain. We end up with this one if we
7949 * have operands that look like
7950 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7951 * obtain the absolute address of the GOT, and it is strongly
7952 * preferable from a performance point of view to avoid using
7953 * a runtime relocation for this. The actual sequence of
7954 * instructions often look something like:
7955 *
7956 * call .L66
7957 * .L66:
7958 * popl %ebx
7959 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7960 *
7961 * The call and pop essentially return the absolute address
7962 * of the label .L66 and store it in %ebx. The linker itself
7963 * will ultimately change the first operand of the addl so
7964 * that %ebx points to the GOT, but to keep things simple, the
7965 * .o file must have this operand set so that it generates not
7966 * the absolute address of .L66, but the absolute address of
7967 * itself. This allows the linker itself simply treat a GOTPC
7968 * relocation as asking for a pcrel offset to the GOT to be
7969 * added in, and the addend of the relocation is stored in the
7970 * operand field for the instruction itself.
7971 *
7972 * Our job here is to fix the operand so that it would add
7973 * the correct offset so that %ebx would point to itself. The
7974 * thing that is tricky is that .-.L66 will point to the
7975 * beginning of the instruction, so we need to further modify
7976 * the operand so that it will point to itself. There are
7977 * other cases where you have something like:
7978 *
7979 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7980 *
7981 * and here no correction would be required. Internally in
7982 * the assembler we treat operands of this form as not being
7983 * pcrel since the '.' is explicitly mentioned, and I wonder
7984 * whether it would simplify matters to do it this way. Who
7985 * knows. In earlier versions of the PIC patches, the
7986 * pcrel_adjust field was used to store the correction, but
7987 * since the expression is not pcrel, I felt it would be
7988 * confusing to do it this way. */
7989
d6ab8113 7990 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7991 || reloc_type == BFD_RELOC_X86_64_32S
7992 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7993 && GOT_symbol
7994 && GOT_symbol == i.op[n].imms->X_add_symbol
7995 && (i.op[n].imms->X_op == O_symbol
7996 || (i.op[n].imms->X_op == O_add
7997 && ((symbol_get_value_expression
7998 (i.op[n].imms->X_op_symbol)->X_op)
7999 == O_subtract))))
8000 {
2bbd9c25
JJ		 8001 offsetT add;
8002
8003 if (insn_start_frag == frag_now)
8004 add = (p - frag_now->fr_literal) - insn_start_off;
8005 else
8006 {
8007 fragS *fr;
8008
8009 add = insn_start_frag->fr_fix - insn_start_off;
8010 for (fr = insn_start_frag->fr_next;
8011 fr && fr != frag_now; fr = fr->fr_next)
8012 add += fr->fr_fix;
8013 add += p - frag_now->fr_literal;
8014 }
8015
4fa24527 8016 if (!object_64bit)
d6ab8113 8017 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 8018 else if (size == 4)
d6ab8113 8019 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 8020 else if (size == 8)
8021 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 8022 i.op[n].imms->X_add_number += add;
29b0f896 8023 }
29b0f896
AM		 8024 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8025 i.op[n].imms, 0, reloc_type);
8026 }
8027 }
8028 }
252b5132
RH		 8029}
8030\f
d182319b
JB		 8031/* x86_cons_fix_new is called via the expression parsing code when a
8032 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 8033static int cons_sign = -1;
8034
8035void
e3bb37b5 8036x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 8037 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 8038{
d258b828 8039 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 8040
8041#ifdef TE_PE
8042 if (exp->X_op == O_secrel)
8043 {
8044 exp->X_op = O_symbol;
8045 r = BFD_RELOC_32_SECREL;
8046 }
8047#endif
8048
8049 fix_new_exp (frag, off, len, exp, 0, r);
8050}
8051
357d1bd8
L		 8052/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8053 purpose of the `.dc.a' internal pseudo-op. */
8054
8055int
8056x86_address_bytes (void)
8057{
8058 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8059 return 4;
8060 return stdoutput->arch_info->bits_per_address / 8;
8061}
8062
d382c579
TG		 8063#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8064 || defined (LEX_AT)
d258b828 8065# define lex_got(reloc, adjust, types) NULL
718ddfc0 8066#else
f3c180ae
AM		 8067/* Parse operands of the form
8068 <symbol>@GOTOFF+<nnn>
8069 and similar .plt or .got references.
8070
8071 If we find one, set up the correct relocation in RELOC and copy the
8072 input string, minus the `@GOTOFF' into a malloc'd buffer for
8073 parsing by the calling routine. Return this buffer, and if ADJUST
8074 is non-null set it to the length of the string we removed from the
8075 input line. Otherwise return NULL. */
8076static char *
91d6fa6a 8077lex_got (enum bfd_reloc_code_real *rel,
64e74474 8078 int *adjust,
d258b828 8079 i386_operand_type *types)
f3c180ae 8080{
7b81dfbb
AJ		 8081 /* Some of the relocations depend on the size of what field is to
8082 be relocated. But in our callers i386_immediate and i386_displacement
8083 we don't yet know the operand size (this will be set by insn
8084 matching). Hence we record the word32 relocation here,
8085 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 8086 static const struct {
8087 const char *str;
cff8d58a 8088 int len;
4fa24527 8089 const enum bfd_reloc_code_real rel[2];
40fb9820 8090 const i386_operand_type types64;
f3c180ae 8091 } gotrel[] = {
8ce3d284 8092#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 8093 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8094 BFD_RELOC_SIZE32 },
8095 OPERAND_TYPE_IMM32_64 },
8ce3d284 8096#endif
cff8d58a
L		 8097 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8098 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 8099 OPERAND_TYPE_IMM64 },
cff8d58a
L		 8100 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8101 BFD_RELOC_X86_64_PLT32 },
40fb9820 8102 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8103 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8104 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 8105 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8106 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8107 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 8108 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8109 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8110 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 8111 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8112 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8113 BFD_RELOC_X86_64_TLSGD },
40fb9820 8114 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8115 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8116 _dummy_first_bfd_reloc_code_real },
40fb9820 8117 OPERAND_TYPE_NONE },
cff8d58a
L		 8118 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8119 BFD_RELOC_X86_64_TLSLD },
40fb9820 8120 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8121 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8122 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 8123 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8124 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8125 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 8126 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8127 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8128 _dummy_first_bfd_reloc_code_real },
40fb9820 8129 OPERAND_TYPE_NONE },
cff8d58a
L		 8130 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8131 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 8132 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8133 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8134 _dummy_first_bfd_reloc_code_real },
40fb9820 8135 OPERAND_TYPE_NONE },
cff8d58a
L		 8136 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8137 _dummy_first_bfd_reloc_code_real },
40fb9820 8138 OPERAND_TYPE_NONE },
cff8d58a
L		 8139 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8140 BFD_RELOC_X86_64_GOT32 },
40fb9820 8141 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 8142 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8143 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 8144 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8145 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8146 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 8147 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 8148 };
8149 char *cp;
8150 unsigned int j;
8151
d382c579 8152#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 8153 if (!IS_ELF)
8154 return NULL;
d382c579 8155#endif
718ddfc0 8156
f3c180ae 8157 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 8158 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 8159 return NULL;
8160
47465058 8161 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 8162 {
cff8d58a 8163 int len = gotrel[j].len;
28f81592 8164 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 8165 {
4fa24527 8166 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 8167 {
28f81592
AM		 8168 int first, second;
8169 char *tmpbuf, *past_reloc;
f3c180ae 8170
91d6fa6a 8171 *rel = gotrel[j].rel[object_64bit];
f3c180ae 8172
3956db08
JB		 8173 if (types)
8174 {
8175 if (flag_code != CODE_64BIT)
40fb9820
L		 8176 {
8177 types->bitfield.imm32 = 1;
8178 types->bitfield.disp32 = 1;
8179 }
3956db08
JB		 8180 else
8181 *types = gotrel[j].types64;
8182 }
8183
8fd4256d 8184 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 8185 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8186
28f81592 8187 /* The length of the first part of our input line. */
f3c180ae 8188 first = cp - input_line_pointer;
28f81592
AM		 8189
8190 /* The second part goes from after the reloc token until
67c11a9b 8191 (and including) an end_of_line char or comma. */
28f81592 8192 past_reloc = cp + 1 + len;
67c11a9b
AM		 8193 cp = past_reloc;
8194 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8195 ++cp;
8196 second = cp + 1 - past_reloc;
28f81592
AM		 8197
8198 /* Allocate and copy string. The trailing NUL shouldn't
8199 be necessary, but be safe. */
add39d23 8200 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 8201 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 8202 if (second != 0 && *past_reloc != ' ')
8203 /* Replace the relocation token with ' ', so that
8204 errors like foo@GOTOFF1 will be detected. */
8205 tmpbuf[first++] = ' ';
af89796a
L		 8206 else
8207 /* Increment length by 1 if the relocation token is
8208 removed. */
8209 len++;
8210 if (adjust)
8211 *adjust = len;
0787a12d
AM		 8212 memcpy (tmpbuf + first, past_reloc, second);
8213 tmpbuf[first + second] = '\0';
f3c180ae
AM		 8214 return tmpbuf;
8215 }
8216
4fa24527
JB		 8217 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8218 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 8219 return NULL;
8220 }
8221 }
8222
8223 /* Might be a symbol version string. Don't as_bad here. */
8224 return NULL;
8225}
4e4f7c87 8226#endif
f3c180ae 8227
a988325c
NC		 8228#ifdef TE_PE
8229#ifdef lex_got
8230#undef lex_got
8231#endif
8232/* Parse operands of the form
8233 <symbol>@SECREL32+<nnn>
8234
8235 If we find one, set up the correct relocation in RELOC and copy the
8236 input string, minus the `@SECREL32' into a malloc'd buffer for
8237 parsing by the calling routine. Return this buffer, and if ADJUST
8238 is non-null set it to the length of the string we removed from the
34bca508
L		 8239 input line. Otherwise return NULL.
8240
a988325c
NC		 8241 This function is copied from the ELF version above adjusted for PE targets. */
8242
8243static char *
8244lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8245 int *adjust ATTRIBUTE_UNUSED,
d258b828 8246 i386_operand_type *types)
a988325c
NC		 8247{
8248 static const struct
8249 {
8250 const char *str;
8251 int len;
8252 const enum bfd_reloc_code_real rel[2];
8253 const i386_operand_type types64;
8254 }
8255 gotrel[] =
8256 {
8257 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8258 BFD_RELOC_32_SECREL },
8259 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8260 };
8261
8262 char *cp;
8263 unsigned j;
8264
8265 for (cp = input_line_pointer; *cp != '@'; cp++)
8266 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8267 return NULL;
8268
8269 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8270 {
8271 int len = gotrel[j].len;
8272
8273 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8274 {
8275 if (gotrel[j].rel[object_64bit] != 0)
8276 {
8277 int first, second;
8278 char *tmpbuf, *past_reloc;
8279
8280 *rel = gotrel[j].rel[object_64bit];
8281 if (adjust)
8282 *adjust = len;
8283
8284 if (types)
8285 {
8286 if (flag_code != CODE_64BIT)
8287 {
8288 types->bitfield.imm32 = 1;
8289 types->bitfield.disp32 = 1;
8290 }
8291 else
8292 *types = gotrel[j].types64;
8293 }
8294
8295 /* The length of the first part of our input line. */
8296 first = cp - input_line_pointer;
8297
8298 /* The second part goes from after the reloc token until
8299 (and including) an end_of_line char or comma. */
8300 past_reloc = cp + 1 + len;
8301 cp = past_reloc;
8302 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8303 ++cp;
8304 second = cp + 1 - past_reloc;
8305
8306 /* Allocate and copy string. The trailing NUL shouldn't
8307 be necessary, but be safe. */
add39d23 8308 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 8309 memcpy (tmpbuf, input_line_pointer, first);
8310 if (second != 0 && *past_reloc != ' ')
8311 /* Replace the relocation token with ' ', so that
8312 errors like foo@SECLREL321 will be detected. */
8313 tmpbuf[first++] = ' ';
8314 memcpy (tmpbuf + first, past_reloc, second);
8315 tmpbuf[first + second] = '\0';
8316 return tmpbuf;
8317 }
8318
8319 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8320 gotrel[j].str, 1 << (5 + object_64bit));
8321 return NULL;
8322 }
8323 }
8324
8325 /* Might be a symbol version string. Don't as_bad here. */
8326 return NULL;
8327}
8328
8329#endif /* TE_PE */
8330
62ebcb5c 8331bfd_reloc_code_real_type
e3bb37b5 8332x86_cons (expressionS *exp, int size)
f3c180ae 8333{
62ebcb5c
AM		 8334 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8335
ee86248c
JB		 8336 intel_syntax = -intel_syntax;
8337
3c7b9c2c 8338 exp->X_md = 0;
4fa24527 8339 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 8340 {
8341 /* Handle @GOTOFF and the like in an expression. */
8342 char *save;
8343 char *gotfree_input_line;
4a57f2cf 8344 int adjust = 0;
f3c180ae
AM		 8345
8346 save = input_line_pointer;
d258b828 8347 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 8348 if (gotfree_input_line)
8349 input_line_pointer = gotfree_input_line;
8350
8351 expression (exp);
8352
8353 if (gotfree_input_line)
8354 {
8355 /* expression () has merrily parsed up to the end of line,
8356 or a comma - in the wrong buffer. Transfer how far
8357 input_line_pointer has moved to the right buffer. */
8358 input_line_pointer = (save
8359 + (input_line_pointer - gotfree_input_line)
8360 + adjust);
8361 free (gotfree_input_line);
3992d3b7
AM		 8362 if (exp->X_op == O_constant
8363 || exp->X_op == O_absent
8364 || exp->X_op == O_illegal
0398aac5 8365 || exp->X_op == O_register
3992d3b7
AM		 8366 || exp->X_op == O_big)
8367 {
8368 char c = *input_line_pointer;
8369 *input_line_pointer = 0;
8370 as_bad (_("missing or invalid expression `%s'"), save);
8371 *input_line_pointer = c;
8372 }
f3c180ae
AM		 8373 }
8374 }
8375 else
8376 expression (exp);
ee86248c
JB		 8377
8378 intel_syntax = -intel_syntax;
8379
8380 if (intel_syntax)
8381 i386_intel_simplify (exp);
62ebcb5c
AM		 8382
8383 return got_reloc;
f3c180ae 8384}
f3c180ae 8385
9f32dd5b
L		 8386static void
8387signed_cons (int size)
6482c264 8388{
d182319b
JB		 8389 if (flag_code == CODE_64BIT)
8390 cons_sign = 1;
8391 cons (size);
8392 cons_sign = -1;
6482c264
NC		 8393}
8394
d182319b 8395#ifdef TE_PE
6482c264 8396static void
7016a5d5 8397pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 8398{
8399 expressionS exp;
8400
8401 do
8402 {
8403 expression (&exp);
8404 if (exp.X_op == O_symbol)
8405 exp.X_op = O_secrel;
8406
8407 emit_expr (&exp, 4);
8408 }
8409 while (*input_line_pointer++ == ',');
8410
8411 input_line_pointer--;
8412 demand_empty_rest_of_line ();
8413}
6482c264
NC		 8414#endif
8415
43234a1e
L		 8416/* Handle Vector operations. */
8417
8418static char *
8419check_VecOperations (char *op_string, char *op_end)
8420{
8421 const reg_entry *mask;
8422 const char *saved;
8423 char *end_op;
8424
8425 while (*op_string
8426 && (op_end == NULL || op_string < op_end))
8427 {
8428 saved = op_string;
8429 if (*op_string == '{')
8430 {
8431 op_string++;
8432
8433 /* Check broadcasts. */
8434 if (strncmp (op_string, "1to", 3) == 0)
8435 {
8436 int bcst_type;
8437
8438 if (i.broadcast)
8439 goto duplicated_vec_op;
8440
8441 op_string += 3;
8442 if (*op_string == '8')
8443 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 8444 else if (*op_string == '4')
8445 bcst_type = BROADCAST_1TO4;
8446 else if (*op_string == '2')
8447 bcst_type = BROADCAST_1TO2;
43234a1e
L		 8448 else if (*op_string == '1'
8449 && *(op_string+1) == '6')
8450 {
8451 bcst_type = BROADCAST_1TO16;
8452 op_string++;
8453 }
8454 else
8455 {
8456 as_bad (_("Unsupported broadcast: `%s'"), saved);
8457 return NULL;
8458 }
8459 op_string++;
8460
8461 broadcast_op.type = bcst_type;
8462 broadcast_op.operand = this_operand;
8463 i.broadcast = &broadcast_op;
8464 }
8465 /* Check masking operation. */
8466 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8467 {
8468 /* k0 can't be used for write mask. */
6d2cd6b2 8469 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
43234a1e 8470 {
6d2cd6b2
JB		 8471 as_bad (_("`%s%s' can't be used for write mask"),
8472 register_prefix, mask->reg_name);
43234a1e
L		 8473 return NULL;
8474 }
8475
8476 if (!i.mask)
8477 {
8478 mask_op.mask = mask;
8479 mask_op.zeroing = 0;
8480 mask_op.operand = this_operand;
8481 i.mask = &mask_op;
8482 }
8483 else
8484 {
8485 if (i.mask->mask)
8486 goto duplicated_vec_op;
8487
8488 i.mask->mask = mask;
8489
8490 /* Only "{z}" is allowed here. No need to check
8491 zeroing mask explicitly. */
8492 if (i.mask->operand != this_operand)
8493 {
8494 as_bad (_("invalid write mask `%s'"), saved);
8495 return NULL;
8496 }
8497 }
8498
8499 op_string = end_op;
8500 }
8501 /* Check zeroing-flag for masking operation. */
8502 else if (*op_string == 'z')
8503 {
8504 if (!i.mask)
8505 {
8506 mask_op.mask = NULL;
8507 mask_op.zeroing = 1;
8508 mask_op.operand = this_operand;
8509 i.mask = &mask_op;
8510 }
8511 else
8512 {
8513 if (i.mask->zeroing)
8514 {
8515 duplicated_vec_op:
8516 as_bad (_("duplicated `%s'"), saved);
8517 return NULL;
8518 }
8519
8520 i.mask->zeroing = 1;
8521
8522 /* Only "{%k}" is allowed here. No need to check mask
8523 register explicitly. */
8524 if (i.mask->operand != this_operand)
8525 {
8526 as_bad (_("invalid zeroing-masking `%s'"),
8527 saved);
8528 return NULL;
8529 }
8530 }
8531
8532 op_string++;
8533 }
8534 else
8535 goto unknown_vec_op;
8536
8537 if (*op_string != '}')
8538 {
8539 as_bad (_("missing `}' in `%s'"), saved);
8540 return NULL;
8541 }
8542 op_string++;
0ba3a731
L		 8543
8544 /* Strip whitespace since the addition of pseudo prefixes
8545 changed how the scrubber treats '{'. */
8546 if (is_space_char (*op_string))
8547 ++op_string;
8548
43234a1e
L		 8549 continue;
8550 }
8551 unknown_vec_op:
8552 /* We don't know this one. */
8553 as_bad (_("unknown vector operation: `%s'"), saved);
8554 return NULL;
8555 }
8556
6d2cd6b2
JB		 8557 if (i.mask && i.mask->zeroing && !i.mask->mask)
8558 {
8559 as_bad (_("zeroing-masking only allowed with write mask"));
8560 return NULL;
8561 }
8562
43234a1e
L		 8563 return op_string;
8564}
8565
252b5132 8566static int
70e41ade 8567i386_immediate (char *imm_start)
252b5132
RH		 8568{
8569 char *save_input_line_pointer;
f3c180ae 8570 char *gotfree_input_line;
252b5132 8571 segT exp_seg = 0;
47926f60 8572 expressionS *exp;
40fb9820
L		 8573 i386_operand_type types;
8574
0dfbf9d7 8575 operand_type_set (&types, ~0);
252b5132
RH		 8576
8577 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8578 {
31b2323c
L		 8579 as_bad (_("at most %d immediate operands are allowed"),
8580 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8581 return 0;
8582 }
8583
8584 exp = &im_expressions[i.imm_operands++];
520dc8e8 8585 i.op[this_operand].imms = exp;
252b5132
RH		 8586
8587 if (is_space_char (*imm_start))
8588 ++imm_start;
8589
8590 save_input_line_pointer = input_line_pointer;
8591 input_line_pointer = imm_start;
8592
d258b828 8593 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8594 if (gotfree_input_line)
8595 input_line_pointer = gotfree_input_line;
252b5132
RH		 8596
8597 exp_seg = expression (exp);
8598
83183c0c 8599 SKIP_WHITESPACE ();
43234a1e
L		 8600
8601 /* Handle vector operations. */
8602 if (*input_line_pointer == '{')
8603 {
8604 input_line_pointer = check_VecOperations (input_line_pointer,
8605 NULL);
8606 if (input_line_pointer == NULL)
8607 return 0;
8608 }
8609
252b5132 8610 if (*input_line_pointer)
f3c180ae 8611 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8612
8613 input_line_pointer = save_input_line_pointer;
f3c180ae 8614 if (gotfree_input_line)
ee86248c
JB		 8615 {
8616 free (gotfree_input_line);
8617
8618 if (exp->X_op == O_constant || exp->X_op == O_register)
8619 exp->X_op = O_illegal;
8620 }
8621
8622 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8623}
252b5132 8624
ee86248c
JB		 8625static int
8626i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8627 i386_operand_type types, const char *imm_start)
8628{
8629 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8630 {
313c53d1
L		 8631 if (imm_start)
8632 as_bad (_("missing or invalid immediate expression `%s'"),
8633 imm_start);
3992d3b7 8634 return 0;
252b5132 8635 }
3e73aa7c 8636 else if (exp->X_op == O_constant)
252b5132 8637 {
47926f60 8638 /* Size it properly later. */
40fb9820 8639 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8640 /* If not 64bit, sign extend val. */
8641 if (flag_code != CODE_64BIT
4eed87de
AM		 8642 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8643 exp->X_add_number
8644 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8645 }
4c63da97 8646#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8647 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8648 && exp_seg != absolute_section
47926f60 8649 && exp_seg != text_section
24eab124
AM		 8650 && exp_seg != data_section
8651 && exp_seg != bss_section
8652 && exp_seg != undefined_section
f86103b7 8653 && !bfd_is_com_section (exp_seg))
252b5132 8654 {
d0b47220 8655 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8656 return 0;
8657 }
8658#endif
a841bdf5 8659 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8660 {
313c53d1
L		 8661 if (imm_start)
8662 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8663 return 0;
8664 }
252b5132
RH		 8665 else
8666 {
8667 /* This is an address. The size of the address will be
24eab124 8668 determined later, depending on destination register,
3e73aa7c 8669 suffix, or the default for the section. */
40fb9820
L		 8670 i.types[this_operand].bitfield.imm8 = 1;
8671 i.types[this_operand].bitfield.imm16 = 1;
8672 i.types[this_operand].bitfield.imm32 = 1;
8673 i.types[this_operand].bitfield.imm32s = 1;
8674 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8675 i.types[this_operand] = operand_type_and (i.types[this_operand],
8676 types);
252b5132
RH		 8677 }
8678
8679 return 1;
8680}
8681
551c1ca1 8682static char *
e3bb37b5 8683i386_scale (char *scale)
252b5132 8684{
551c1ca1
AM		 8685 offsetT val;
8686 char *save = input_line_pointer;
252b5132 8687
551c1ca1
AM		 8688 input_line_pointer = scale;
8689 val = get_absolute_expression ();
8690
8691 switch (val)
252b5132 8692 {
551c1ca1 8693 case 1:
252b5132
RH		 8694 i.log2_scale_factor = 0;
8695 break;
551c1ca1 8696 case 2:
252b5132
RH		 8697 i.log2_scale_factor = 1;
8698 break;
551c1ca1 8699 case 4:
252b5132
RH		 8700 i.log2_scale_factor = 2;
8701 break;
551c1ca1 8702 case 8:
252b5132
RH		 8703 i.log2_scale_factor = 3;
8704 break;
8705 default:
a724f0f4
JB		 8706 {
8707 char sep = *input_line_pointer;
8708
8709 *input_line_pointer = '\0';
8710 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8711 scale);
8712 *input_line_pointer = sep;
8713 input_line_pointer = save;
8714 return NULL;
8715 }
252b5132 8716 }
29b0f896 8717 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8718 {
8719 as_warn (_("scale factor of %d without an index register"),
24eab124 8720 1 << i.log2_scale_factor);
252b5132 8721 i.log2_scale_factor = 0;
252b5132 8722 }
551c1ca1
AM		 8723 scale = input_line_pointer;
8724 input_line_pointer = save;
8725 return scale;
252b5132
RH		 8726}
8727
252b5132 8728static int
e3bb37b5 8729i386_displacement (char *disp_start, char *disp_end)
252b5132 8730{
29b0f896 8731 expressionS *exp;
252b5132
RH		 8732 segT exp_seg = 0;
8733 char *save_input_line_pointer;
f3c180ae 8734 char *gotfree_input_line;
40fb9820
L		 8735 int override;
8736 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8737 int ret;
252b5132 8738
31b2323c
L		 8739 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8740 {
8741 as_bad (_("at most %d displacement operands are allowed"),
8742 MAX_MEMORY_OPERANDS);
8743 return 0;
8744 }
8745
0dfbf9d7 8746 operand_type_set (&bigdisp, 0);
40fb9820
L		 8747 if ((i.types[this_operand].bitfield.jumpabsolute)
8748 || (!current_templates->start->opcode_modifier.jump
8749 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8750 {
40fb9820 8751 bigdisp.bitfield.disp32 = 1;
e05278af 8752 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8753 if (flag_code == CODE_64BIT)
8754 {
8755 if (!override)
8756 {
8757 bigdisp.bitfield.disp32s = 1;
8758 bigdisp.bitfield.disp64 = 1;
8759 }
8760 }
8761 else if ((flag_code == CODE_16BIT) ^ override)
8762 {
8763 bigdisp.bitfield.disp32 = 0;
8764 bigdisp.bitfield.disp16 = 1;
8765 }
e05278af
JB		 8766 }
8767 else
8768 {
8769 /* For PC-relative branches, the width of the displacement
8770 is dependent upon data size, not address size. */
e05278af 8771 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8772 if (flag_code == CODE_64BIT)
8773 {
8774 if (override || i.suffix == WORD_MNEM_SUFFIX)
8775 bigdisp.bitfield.disp16 = 1;
8776 else
8777 {
8778 bigdisp.bitfield.disp32 = 1;
8779 bigdisp.bitfield.disp32s = 1;
8780 }
8781 }
8782 else
e05278af
JB		 8783 {
8784 if (!override)
8785 override = (i.suffix == (flag_code != CODE_16BIT
8786 ? WORD_MNEM_SUFFIX
8787 : LONG_MNEM_SUFFIX));
40fb9820
L		 8788 bigdisp.bitfield.disp32 = 1;
8789 if ((flag_code == CODE_16BIT) ^ override)
8790 {
8791 bigdisp.bitfield.disp32 = 0;
8792 bigdisp.bitfield.disp16 = 1;
8793 }
e05278af 8794 }
e05278af 8795 }
c6fb90c8
L		 8796 i.types[this_operand] = operand_type_or (i.types[this_operand],
8797 bigdisp);
252b5132
RH		 8798
8799 exp = &disp_expressions[i.disp_operands];
520dc8e8 8800 i.op[this_operand].disps = exp;
252b5132
RH		 8801 i.disp_operands++;
8802 save_input_line_pointer = input_line_pointer;
8803 input_line_pointer = disp_start;
8804 END_STRING_AND_SAVE (disp_end);
8805
8806#ifndef GCC_ASM_O_HACK
8807#define GCC_ASM_O_HACK 0
8808#endif
8809#if GCC_ASM_O_HACK
8810 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8811 if (i.types[this_operand].bitfield.baseIndex
24eab124 8812 && displacement_string_end[-1] == '+')
252b5132
RH		 8813 {
8814 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8815 constraint within gcc asm statements.
8816 For instance:
8817
8818 #define _set_tssldt_desc(n,addr,limit,type) \
8819 __asm__ __volatile__ ( \
8820 "movw %w2,%0\n\t" \
8821 "movw %w1,2+%0\n\t" \
8822 "rorl $16,%1\n\t" \
8823 "movb %b1,4+%0\n\t" \
8824 "movb %4,5+%0\n\t" \
8825 "movb $0,6+%0\n\t" \
8826 "movb %h1,7+%0\n\t" \
8827 "rorl $16,%1" \
8828 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8829
8830 This works great except that the output assembler ends
8831 up looking a bit weird if it turns out that there is
8832 no offset. You end up producing code that looks like:
8833
8834 #APP
8835 movw $235,(%eax)
8836 movw %dx,2+(%eax)
8837 rorl $16,%edx
8838 movb %dl,4+(%eax)
8839 movb $137,5+(%eax)
8840 movb $0,6+(%eax)
8841 movb %dh,7+(%eax)
8842 rorl $16,%edx
8843 #NO_APP
8844
47926f60 8845 So here we provide the missing zero. */
24eab124
AM		 8846
8847 *displacement_string_end = '0';
252b5132
RH		 8848 }
8849#endif
d258b828 8850 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8851 if (gotfree_input_line)
8852 input_line_pointer = gotfree_input_line;
252b5132 8853
24eab124 8854 exp_seg = expression (exp);
252b5132 8855
636c26b0
AM		 8856 SKIP_WHITESPACE ();
8857 if (*input_line_pointer)
8858 as_bad (_("junk `%s' after expression"), input_line_pointer);
8859#if GCC_ASM_O_HACK
8860 RESTORE_END_STRING (disp_end + 1);
8861#endif
636c26b0 8862 input_line_pointer = save_input_line_pointer;
636c26b0 8863 if (gotfree_input_line)
ee86248c
JB		 8864 {
8865 free (gotfree_input_line);
8866
8867 if (exp->X_op == O_constant || exp->X_op == O_register)
8868 exp->X_op = O_illegal;
8869 }
8870
8871 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8872
8873 RESTORE_END_STRING (disp_end);
8874
8875 return ret;
8876}
8877
8878static int
8879i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8880 i386_operand_type types, const char *disp_start)
8881{
8882 i386_operand_type bigdisp;
8883 int ret = 1;
636c26b0 8884
24eab124
AM		 8885 /* We do this to make sure that the section symbol is in
8886 the symbol table. We will ultimately change the relocation
47926f60 8887 to be relative to the beginning of the section. */
1ae12ab7 8888 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8889 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8890 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8891 {
636c26b0 8892 if (exp->X_op != O_symbol)
3992d3b7 8893 goto inv_disp;
636c26b0 8894
e5cb08ac 8895 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8896 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8897 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8898 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8899 exp->X_op = O_subtract;
8900 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8901 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8902 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8903 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8904 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8905 else
29b0f896 8906 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8907 }
252b5132 8908
3992d3b7
AM		 8909 else if (exp->X_op == O_absent
8910 || exp->X_op == O_illegal
ee86248c 8911 || exp->X_op == O_big)
2daf4fd8 8912 {
3992d3b7
AM		 8913 inv_disp:
8914 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8915 disp_start);
3992d3b7 8916 ret = 0;
2daf4fd8
AM		 8917 }
8918
0e1147d9
L		 8919 else if (flag_code == CODE_64BIT
8920 && !i.prefix[ADDR_PREFIX]
8921 && exp->X_op == O_constant)
8922 {
8923 /* Since displacement is signed extended to 64bit, don't allow
8924 disp32 and turn off disp32s if they are out of range. */
8925 i.types[this_operand].bitfield.disp32 = 0;
8926 if (!fits_in_signed_long (exp->X_add_number))
8927 {
8928 i.types[this_operand].bitfield.disp32s = 0;
8929 if (i.types[this_operand].bitfield.baseindex)
8930 {
8931 as_bad (_("0x%lx out range of signed 32bit displacement"),
8932 (long) exp->X_add_number);
8933 ret = 0;
8934 }
8935 }
8936 }
8937
4c63da97 8938#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8939 else if (exp->X_op != O_constant
8940 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8941 && exp_seg != absolute_section
8942 && exp_seg != text_section
8943 && exp_seg != data_section
8944 && exp_seg != bss_section
8945 && exp_seg != undefined_section
8946 && !bfd_is_com_section (exp_seg))
24eab124 8947 {
d0b47220 8948 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8949 ret = 0;
24eab124 8950 }
252b5132 8951#endif
3956db08 8952
40fb9820
L		 8953 /* Check if this is a displacement only operand. */
8954 bigdisp = i.types[this_operand];
8955 bigdisp.bitfield.disp8 = 0;
8956 bigdisp.bitfield.disp16 = 0;
8957 bigdisp.bitfield.disp32 = 0;
8958 bigdisp.bitfield.disp32s = 0;
8959 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8960 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8961 i.types[this_operand] = operand_type_and (i.types[this_operand],
8962 types);
3956db08 8963
3992d3b7 8964 return ret;
252b5132
RH		 8965}
8966
2abc2bec
JB		 8967/* Return the active addressing mode, taking address override and
8968 registers forming the address into consideration. Update the
8969 address override prefix if necessary. */
47926f60 8970
2abc2bec
JB		 8971static enum flag_code
8972i386_addressing_mode (void)
252b5132 8973{
be05d201
L		 8974 enum flag_code addr_mode;
8975
8976 if (i.prefix[ADDR_PREFIX])
8977 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8978 else
8979 {
8980 addr_mode = flag_code;
8981
24eab124 8982#if INFER_ADDR_PREFIX
be05d201
L		 8983 if (i.mem_operands == 0)
8984 {
8985 /* Infer address prefix from the first memory operand. */
8986 const reg_entry *addr_reg = i.base_reg;
8987
8988 if (addr_reg == NULL)
8989 addr_reg = i.index_reg;
eecb386c 8990
be05d201
L		 8991 if (addr_reg)
8992 {
8993 if (addr_reg->reg_num == RegEip
8994 || addr_reg->reg_num == RegEiz
dc821c5f 8995 || addr_reg->reg_type.bitfield.dword)
be05d201
L		 8996 addr_mode = CODE_32BIT;
8997 else if (flag_code != CODE_64BIT
dc821c5f 8998 && addr_reg->reg_type.bitfield.word)
be05d201
L		 8999 addr_mode = CODE_16BIT;
9000
9001 if (addr_mode != flag_code)
9002 {
9003 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9004 i.prefixes += 1;
9005 /* Change the size of any displacement too. At most one
9006 of Disp16 or Disp32 is set.
9007 FIXME. There doesn't seem to be any real need for
9008 separate Disp16 and Disp32 flags. The same goes for
9009 Imm16 and Imm32. Removing them would probably clean
9010 up the code quite a lot. */
9011 if (flag_code != CODE_64BIT
9012 && (i.types[this_operand].bitfield.disp16
9013 || i.types[this_operand].bitfield.disp32))
9014 i.types[this_operand]
9015 = operand_type_xor (i.types[this_operand], disp16_32);
9016 }
9017 }
9018 }
24eab124 9019#endif
be05d201
L		 9020 }
9021
2abc2bec
JB		 9022 return addr_mode;
9023}
9024
9025/* Make sure the memory operand we've been dealt is valid.
9026 Return 1 on success, 0 on a failure. */
9027
9028static int
9029i386_index_check (const char *operand_string)
9030{
9031 const char *kind = "base/index";
9032 enum flag_code addr_mode = i386_addressing_mode ();
9033
fc0763e6
JB		 9034 if (current_templates->start->opcode_modifier.isstring
9035 && !current_templates->start->opcode_modifier.immext
9036 && (current_templates->end[-1].opcode_modifier.isstring
9037 || i.mem_operands))
9038 {
9039 /* Memory operands of string insns are special in that they only allow
9040 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 9041 const reg_entry *expected_reg;
9042 static const char *di_si[][2] =
9043 {
9044 { "esi", "edi" },
9045 { "si", "di" },
9046 { "rsi", "rdi" }
9047 };
9048 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 9049
9050 kind = "string address";
9051
8325cc63 9052 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 9053 {
9054 i386_operand_type type = current_templates->end[-1].operand_types[0];
9055
9056 if (!type.bitfield.baseindex
9057 || ((!i.mem_operands != !intel_syntax)
9058 && current_templates->end[-1].operand_types[1]
9059 .bitfield.baseindex))
9060 type = current_templates->end[-1].operand_types[1];
be05d201
L		 9061 expected_reg = hash_find (reg_hash,
9062 di_si[addr_mode][type.bitfield.esseg]);
9063
fc0763e6
JB		 9064 }
9065 else
be05d201 9066 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 9067
be05d201
L		 9068 if (i.base_reg != expected_reg
9069 || i.index_reg
fc0763e6 9070 || operand_type_check (i.types[this_operand], disp))
fc0763e6 9071 {
be05d201
L		 9072 /* The second memory operand must have the same size as
9073 the first one. */
9074 if (i.mem_operands
9075 && i.base_reg
9076 && !((addr_mode == CODE_64BIT
dc821c5f 9077 && i.base_reg->reg_type.bitfield.qword)
be05d201 9078 || (addr_mode == CODE_32BIT
dc821c5f
JB		 9079 ? i.base_reg->reg_type.bitfield.dword
9080 : i.base_reg->reg_type.bitfield.word)))
be05d201
L		 9081 goto bad_address;
9082
fc0763e6
JB		 9083 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9084 operand_string,
9085 intel_syntax ? '[' : '(',
9086 register_prefix,
be05d201 9087 expected_reg->reg_name,
fc0763e6 9088 intel_syntax ? ']' : ')');
be05d201 9089 return 1;
fc0763e6 9090 }
be05d201
L		 9091 else
9092 return 1;
9093
9094bad_address:
9095 as_bad (_("`%s' is not a valid %s expression"),
9096 operand_string, kind);
9097 return 0;
3e73aa7c
JH		 9098 }
9099 else
9100 {
be05d201
L		 9101 if (addr_mode != CODE_16BIT)
9102 {
9103 /* 32-bit/64-bit checks. */
9104 if ((i.base_reg
9105 && (addr_mode == CODE_64BIT
dc821c5f
JB		 9106 ? !i.base_reg->reg_type.bitfield.qword
9107 : !i.base_reg->reg_type.bitfield.dword)
be05d201
L		 9108 && (i.index_reg
9109 || (i.base_reg->reg_num
9110 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9111 || (i.index_reg
1b54b8d7
JB		 9112 && !i.index_reg->reg_type.bitfield.xmmword
9113 && !i.index_reg->reg_type.bitfield.ymmword
9114 && !i.index_reg->reg_type.bitfield.zmmword
be05d201 9115 && ((addr_mode == CODE_64BIT
dc821c5f 9116 ? !(i.index_reg->reg_type.bitfield.qword
be05d201 9117 || i.index_reg->reg_num == RegRiz)
dc821c5f 9118 : !(i.index_reg->reg_type.bitfield.dword
be05d201
L		 9119 || i.index_reg->reg_num == RegEiz))
9120 || !i.index_reg->reg_type.bitfield.baseindex)))
9121 goto bad_address;
8178be5b
JB		 9122
9123 /* bndmk, bndldx, and bndstx have special restrictions. */
9124 if (current_templates->start->base_opcode == 0xf30f1b
9125 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9126 {
9127 /* They cannot use RIP-relative addressing. */
9128 if (i.base_reg && i.base_reg->reg_num == RegRip)
9129 {
9130 as_bad (_("`%s' cannot be used here"), operand_string);
9131 return 0;
9132 }
9133
9134 /* bndldx and bndstx ignore their scale factor. */
9135 if (current_templates->start->base_opcode != 0xf30f1b
9136 && i.log2_scale_factor)
9137 as_warn (_("register scaling is being ignored here"));
9138 }
be05d201
L		 9139 }
9140 else
3e73aa7c 9141 {
be05d201 9142 /* 16-bit checks. */
3e73aa7c 9143 if ((i.base_reg
dc821c5f 9144 && (!i.base_reg->reg_type.bitfield.word
40fb9820 9145 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 9146 || (i.index_reg
dc821c5f 9147 && (!i.index_reg->reg_type.bitfield.word
40fb9820 9148 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 9149 || !(i.base_reg
9150 && i.base_reg->reg_num < 6
9151 && i.index_reg->reg_num >= 6
9152 && i.log2_scale_factor == 0))))
be05d201 9153 goto bad_address;
3e73aa7c
JH		 9154 }
9155 }
be05d201 9156 return 1;
24eab124 9157}
252b5132 9158
43234a1e
L		 9159/* Handle vector immediates. */
9160
9161static int
9162RC_SAE_immediate (const char *imm_start)
9163{
9164 unsigned int match_found, j;
9165 const char *pstr = imm_start;
9166 expressionS *exp;
9167
9168 if (*pstr != '{')
9169 return 0;
9170
9171 pstr++;
9172 match_found = 0;
9173 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9174 {
9175 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9176 {
9177 if (!i.rounding)
9178 {
9179 rc_op.type = RC_NamesTable[j].type;
9180 rc_op.operand = this_operand;
9181 i.rounding = &rc_op;
9182 }
9183 else
9184 {
9185 as_bad (_("duplicated `%s'"), imm_start);
9186 return 0;
9187 }
9188 pstr += RC_NamesTable[j].len;
9189 match_found = 1;
9190 break;
9191 }
9192 }
9193 if (!match_found)
9194 return 0;
9195
9196 if (*pstr++ != '}')
9197 {
9198 as_bad (_("Missing '}': '%s'"), imm_start);
9199 return 0;
9200 }
9201 /* RC/SAE immediate string should contain nothing more. */;
9202 if (*pstr != 0)
9203 {
9204 as_bad (_("Junk after '}': '%s'"), imm_start);
9205 return 0;
9206 }
9207
9208 exp = &im_expressions[i.imm_operands++];
9209 i.op[this_operand].imms = exp;
9210
9211 exp->X_op = O_constant;
9212 exp->X_add_number = 0;
9213 exp->X_add_symbol = (symbolS *) 0;
9214 exp->X_op_symbol = (symbolS *) 0;
9215
9216 i.types[this_operand].bitfield.imm8 = 1;
9217 return 1;
9218}
9219
8325cc63
JB		 9220/* Only string instructions can have a second memory operand, so
9221 reduce current_templates to just those if it contains any. */
9222static int
9223maybe_adjust_templates (void)
9224{
9225 const insn_template *t;
9226
9227 gas_assert (i.mem_operands == 1);
9228
9229 for (t = current_templates->start; t < current_templates->end; ++t)
9230 if (t->opcode_modifier.isstring)
9231 break;
9232
9233 if (t < current_templates->end)
9234 {
9235 static templates aux_templates;
9236 bfd_boolean recheck;
9237
9238 aux_templates.start = t;
9239 for (; t < current_templates->end; ++t)
9240 if (!t->opcode_modifier.isstring)
9241 break;
9242 aux_templates.end = t;
9243
9244 /* Determine whether to re-check the first memory operand. */
9245 recheck = (aux_templates.start != current_templates->start
9246 || t != current_templates->end);
9247
9248 current_templates = &aux_templates;
9249
9250 if (recheck)
9251 {
9252 i.mem_operands = 0;
9253 if (i.memop1_string != NULL
9254 && i386_index_check (i.memop1_string) == 0)
9255 return 0;
9256 i.mem_operands = 1;
9257 }
9258 }
9259
9260 return 1;
9261}
9262
fc0763e6 9263/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 9264 on error. */
252b5132 9265
252b5132 9266static int
a7619375 9267i386_att_operand (char *operand_string)
252b5132 9268{
af6bdddf
AM		 9269 const reg_entry *r;
9270 char *end_op;
24eab124 9271 char *op_string = operand_string;
252b5132 9272
24eab124 9273 if (is_space_char (*op_string))
252b5132
RH		 9274 ++op_string;
9275
24eab124 9276 /* We check for an absolute prefix (differentiating,
47926f60 9277 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 9278 if (*op_string == ABSOLUTE_PREFIX)
9279 {
9280 ++op_string;
9281 if (is_space_char (*op_string))
9282 ++op_string;
40fb9820 9283 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 9284 }
252b5132 9285
47926f60 9286 /* Check if operand is a register. */
4d1bb795 9287 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 9288 {
40fb9820
L		 9289 i386_operand_type temp;
9290
24eab124
AM		 9291 /* Check for a segment override by searching for ':' after a
9292 segment register. */
9293 op_string = end_op;
9294 if (is_space_char (*op_string))
9295 ++op_string;
40fb9820
L		 9296 if (*op_string == ':'
9297 && (r->reg_type.bitfield.sreg2
9298 || r->reg_type.bitfield.sreg3))
24eab124
AM		 9299 {
9300 switch (r->reg_num)
9301 {
9302 case 0:
9303 i.seg[i.mem_operands] = &es;
9304 break;
9305 case 1:
9306 i.seg[i.mem_operands] = &cs;
9307 break;
9308 case 2:
9309 i.seg[i.mem_operands] = &ss;
9310 break;
9311 case 3:
9312 i.seg[i.mem_operands] = &ds;
9313 break;
9314 case 4:
9315 i.seg[i.mem_operands] = &fs;
9316 break;
9317 case 5:
9318 i.seg[i.mem_operands] = &gs;
9319 break;
9320 }
252b5132 9321
24eab124 9322 /* Skip the ':' and whitespace. */
252b5132
RH		 9323 ++op_string;
9324 if (is_space_char (*op_string))
24eab124 9325 ++op_string;
252b5132 9326
24eab124
AM		 9327 if (!is_digit_char (*op_string)
9328 && !is_identifier_char (*op_string)
9329 && *op_string != '('
9330 && *op_string != ABSOLUTE_PREFIX)
9331 {
9332 as_bad (_("bad memory operand `%s'"), op_string);
9333 return 0;
9334 }
47926f60 9335 /* Handle case of %es:*foo. */
24eab124
AM		 9336 if (*op_string == ABSOLUTE_PREFIX)
9337 {
9338 ++op_string;
9339 if (is_space_char (*op_string))
9340 ++op_string;
40fb9820 9341 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 9342 }
9343 goto do_memory_reference;
9344 }
43234a1e
L		 9345
9346 /* Handle vector operations. */
9347 if (*op_string == '{')
9348 {
9349 op_string = check_VecOperations (op_string, NULL);
9350 if (op_string == NULL)
9351 return 0;
9352 }
9353
24eab124
AM		 9354 if (*op_string)
9355 {
d0b47220 9356 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 9357 return 0;
9358 }
40fb9820
L		 9359 temp = r->reg_type;
9360 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9361 i.types[this_operand] = operand_type_or (i.types[this_operand],
9362 temp);
7d5e4556 9363 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 9364 i.op[this_operand].regs = r;
24eab124
AM		 9365 i.reg_operands++;
9366 }
af6bdddf
AM		 9367 else if (*op_string == REGISTER_PREFIX)
9368 {
9369 as_bad (_("bad register name `%s'"), op_string);
9370 return 0;
9371 }
24eab124 9372 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 9373 {
24eab124 9374 ++op_string;
40fb9820 9375 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 9376 {
d0b47220 9377 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 9378 return 0;
9379 }
9380 if (!i386_immediate (op_string))
9381 return 0;
9382 }
43234a1e
L		 9383 else if (RC_SAE_immediate (operand_string))
9384 {
9385 /* If it is a RC or SAE immediate, do nothing. */
9386 ;
9387 }
24eab124
AM		 9388 else if (is_digit_char (*op_string)
9389 || is_identifier_char (*op_string)
d02603dc 9390 || *op_string == '"'
e5cb08ac 9391 || *op_string == '(')
24eab124 9392 {
47926f60 9393 /* This is a memory reference of some sort. */
af6bdddf 9394 char *base_string;
252b5132 9395
47926f60 9396 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 9397 char *displacement_string_start;
9398 char *displacement_string_end;
43234a1e 9399 char *vop_start;
252b5132 9400
24eab124 9401 do_memory_reference:
8325cc63
JB		 9402 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9403 return 0;
24eab124 9404 if ((i.mem_operands == 1
40fb9820 9405 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 9406 || i.mem_operands == 2)
9407 {
9408 as_bad (_("too many memory references for `%s'"),
9409 current_templates->start->name);
9410 return 0;
9411 }
252b5132 9412
24eab124
AM		 9413 /* Check for base index form. We detect the base index form by
9414 looking for an ')' at the end of the operand, searching
9415 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9416 after the '('. */
af6bdddf 9417 base_string = op_string + strlen (op_string);
c3332e24 9418
43234a1e
L		 9419 /* Handle vector operations. */
9420 vop_start = strchr (op_string, '{');
9421 if (vop_start && vop_start < base_string)
9422 {
9423 if (check_VecOperations (vop_start, base_string) == NULL)
9424 return 0;
9425 base_string = vop_start;
9426 }
9427
af6bdddf
AM		 9428 --base_string;
9429 if (is_space_char (*base_string))
9430 --base_string;
252b5132 9431
47926f60 9432 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 9433 displacement_string_start = op_string;
9434 displacement_string_end = base_string + 1;
252b5132 9435
24eab124
AM		 9436 if (*base_string == ')')
9437 {
af6bdddf 9438 char *temp_string;
24eab124
AM		 9439 unsigned int parens_balanced = 1;
9440 /* We've already checked that the number of left & right ()'s are
47926f60 9441 equal, so this loop will not be infinite. */
24eab124
AM		 9442 do
9443 {
9444 base_string--;
9445 if (*base_string == ')')
9446 parens_balanced++;
9447 if (*base_string == '(')
9448 parens_balanced--;
9449 }
9450 while (parens_balanced);
c3332e24 9451
af6bdddf 9452 temp_string = base_string;
c3332e24 9453
24eab124 9454 /* Skip past '(' and whitespace. */
252b5132
RH		 9455 ++base_string;
9456 if (is_space_char (*base_string))
24eab124 9457 ++base_string;
252b5132 9458
af6bdddf 9459 if (*base_string == ','
4eed87de
AM		 9460 || ((i.base_reg = parse_register (base_string, &end_op))
9461 != NULL))
252b5132 9462 {
af6bdddf 9463 displacement_string_end = temp_string;
252b5132 9464
40fb9820 9465 i.types[this_operand].bitfield.baseindex = 1;
252b5132 9466
af6bdddf 9467 if (i.base_reg)
24eab124 9468 {
24eab124
AM		 9469 base_string = end_op;
9470 if (is_space_char (*base_string))
9471 ++base_string;
af6bdddf
AM		 9472 }
9473
9474 /* There may be an index reg or scale factor here. */
9475 if (*base_string == ',')
9476 {
9477 ++base_string;
9478 if (is_space_char (*base_string))
9479 ++base_string;
9480
4eed87de
AM		 9481 if ((i.index_reg = parse_register (base_string, &end_op))
9482 != NULL)
24eab124 9483 {
af6bdddf 9484 base_string = end_op;
24eab124
AM		 9485 if (is_space_char (*base_string))
9486 ++base_string;
af6bdddf
AM		 9487 if (*base_string == ',')
9488 {
9489 ++base_string;
9490 if (is_space_char (*base_string))
9491 ++base_string;
9492 }
e5cb08ac 9493 else if (*base_string != ')')
af6bdddf 9494 {
4eed87de
AM		 9495 as_bad (_("expecting `,' or `)' "
9496 "after index register in `%s'"),
af6bdddf
AM		 9497 operand_string);
9498 return 0;
9499 }
24eab124 9500 }
af6bdddf 9501 else if (*base_string == REGISTER_PREFIX)
24eab124 9502 {
f76bf5e0
L		 9503 end_op = strchr (base_string, ',');
9504 if (end_op)
9505 *end_op = '\0';
af6bdddf 9506 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9507 return 0;
9508 }
252b5132 9509
47926f60 9510 /* Check for scale factor. */
551c1ca1 9511 if (*base_string != ')')
af6bdddf 9512 {
551c1ca1
AM		 9513 char *end_scale = i386_scale (base_string);
9514
9515 if (!end_scale)
af6bdddf 9516 return 0;
24eab124 9517
551c1ca1 9518 base_string = end_scale;
af6bdddf
AM		 9519 if (is_space_char (*base_string))
9520 ++base_string;
9521 if (*base_string != ')')
9522 {
4eed87de
AM		 9523 as_bad (_("expecting `)' "
9524 "after scale factor in `%s'"),
af6bdddf
AM		 9525 operand_string);
9526 return 0;
9527 }
9528 }
9529 else if (!i.index_reg)
24eab124 9530 {
4eed87de
AM		 9531 as_bad (_("expecting index register or scale factor "
9532 "after `,'; got '%c'"),
af6bdddf 9533 *base_string);
24eab124
AM		 9534 return 0;
9535 }
9536 }
af6bdddf 9537 else if (*base_string != ')')
24eab124 9538 {
4eed87de
AM		 9539 as_bad (_("expecting `,' or `)' "
9540 "after base register in `%s'"),
af6bdddf 9541 operand_string);
24eab124
AM		 9542 return 0;
9543 }
c3332e24 9544 }
af6bdddf 9545 else if (*base_string == REGISTER_PREFIX)
c3332e24 9546 {
f76bf5e0
L		 9547 end_op = strchr (base_string, ',');
9548 if (end_op)
9549 *end_op = '\0';
af6bdddf 9550 as_bad (_("bad register name `%s'"), base_string);
24eab124 9551 return 0;
c3332e24 9552 }
24eab124
AM		 9553 }
9554
9555 /* If there's an expression beginning the operand, parse it,
9556 assuming displacement_string_start and
9557 displacement_string_end are meaningful. */
9558 if (displacement_string_start != displacement_string_end)
9559 {
9560 if (!i386_displacement (displacement_string_start,
9561 displacement_string_end))
9562 return 0;
9563 }
9564
9565 /* Special case for (%dx) while doing input/output op. */
9566 if (i.base_reg
0dfbf9d7
L		 9567 && operand_type_equal (&i.base_reg->reg_type,
9568 &reg16_inoutportreg)
24eab124
AM		 9569 && i.index_reg == 0
9570 && i.log2_scale_factor == 0
9571 && i.seg[i.mem_operands] == 0
40fb9820 9572 && !operand_type_check (i.types[this_operand], disp))
24eab124 9573 {
65da13b5 9574 i.types[this_operand] = inoutportreg;
24eab124
AM		 9575 return 1;
9576 }
9577
eecb386c
AM		 9578 if (i386_index_check (operand_string) == 0)
9579 return 0;
5c07affc 9580 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9581 if (i.mem_operands == 0)
9582 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9583 i.mem_operands++;
9584 }
9585 else
ce8a8b2f
AM		 9586 {
9587 /* It's not a memory operand; argh! */
24eab124
AM		 9588 as_bad (_("invalid char %s beginning operand %d `%s'"),
9589 output_invalid (*op_string),
9590 this_operand + 1,
9591 op_string);
9592 return 0;
9593 }
47926f60 9594 return 1; /* Normal return. */
252b5132
RH		 9595}
9596\f
fa94de6b
RM		 9597/* Calculate the maximum variable size (i.e., excluding fr_fix)
9598 that an rs_machine_dependent frag may reach. */
9599
9600unsigned int
9601i386_frag_max_var (fragS *frag)
9602{
9603 /* The only relaxable frags are for jumps.
9604 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9605 gas_assert (frag->fr_type == rs_machine_dependent);
9606 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9607}
9608
b084df0b
L		 9609#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9610static int
8dcea932 9611elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9612{
9613 /* STT_GNU_IFUNC symbol must go through PLT. */
9614 if ((symbol_get_bfdsym (fr_symbol)->flags
9615 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9616 return 0;
9617
9618 if (!S_IS_EXTERNAL (fr_symbol))
9619 /* Symbol may be weak or local. */
9620 return !S_IS_WEAK (fr_symbol);
9621
8dcea932
L		 9622 /* Global symbols with non-default visibility can't be preempted. */
9623 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9624 return 1;
9625
9626 if (fr_var != NO_RELOC)
9627 switch ((enum bfd_reloc_code_real) fr_var)
9628 {
9629 case BFD_RELOC_386_PLT32:
9630 case BFD_RELOC_X86_64_PLT32:
33eaf5de 9631 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 9632 return 0;
9633 default:
9634 abort ();
9635 }
9636
b084df0b
L		 9637 /* Global symbols with default visibility in a shared library may be
9638 preempted by another definition. */
8dcea932 9639 return !shared;
b084df0b
L		 9640}
9641#endif
9642
ee7fcc42
AM		 9643/* md_estimate_size_before_relax()
9644
9645 Called just before relax() for rs_machine_dependent frags. The x86
9646 assembler uses these frags to handle variable size jump
9647 instructions.
9648
9649 Any symbol that is now undefined will not become defined.
9650 Return the correct fr_subtype in the frag.
9651 Return the initial "guess for variable size of frag" to caller.
9652 The guess is actually the growth beyond the fixed part. Whatever
9653 we do to grow the fixed or variable part contributes to our
9654 returned value. */
9655
252b5132 9656int
7016a5d5 9657md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9658{
252b5132 9659 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9660 check for un-relaxable symbols. On an ELF system, we can't relax
9661 an externally visible symbol, because it may be overridden by a
9662 shared library. */
9663 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9664#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9665 || (IS_ELF
8dcea932
L		 9666 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9667 fragP->fr_var))
fbeb56a4
DK		 9668#endif
9669#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9670 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9671 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9672#endif
9673 )
252b5132 9674 {
b98ef147
AM		 9675 /* Symbol is undefined in this segment, or we need to keep a
9676 reloc so that weak symbols can be overridden. */
9677 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9678 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9679 unsigned char *opcode;
9680 int old_fr_fix;
f6af82bd 9681
ee7fcc42 9682 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9683 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9684 else if (size == 2)
f6af82bd 9685 reloc_type = BFD_RELOC_16_PCREL;
bd7ab16b
L		 9686#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9687 else if (need_plt32_p (fragP->fr_symbol))
9688 reloc_type = BFD_RELOC_X86_64_PLT32;
9689#endif
f6af82bd
AM		 9690 else
9691 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9692
ee7fcc42
AM		 9693 old_fr_fix = fragP->fr_fix;
9694 opcode = (unsigned char *) fragP->fr_opcode;
9695
fddf5b5b 9696 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9697 {
fddf5b5b
AM		 9698 case UNCOND_JUMP:
9699 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9700 opcode[0] = 0xe9;
252b5132 9701 fragP->fr_fix += size;
062cd5e7
AS		 9702 fix_new (fragP, old_fr_fix, size,
9703 fragP->fr_symbol,
9704 fragP->fr_offset, 1,
9705 reloc_type);
252b5132
RH		 9706 break;
9707
fddf5b5b 9708 case COND_JUMP86:
412167cb
AM		 9709 if (size == 2
9710 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9711 {
9712 /* Negate the condition, and branch past an
9713 unconditional jump. */
9714 opcode[0] ^= 1;
9715 opcode[1] = 3;
9716 /* Insert an unconditional jump. */
9717 opcode[2] = 0xe9;
9718 /* We added two extra opcode bytes, and have a two byte
9719 offset. */
9720 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9721 fix_new (fragP, old_fr_fix + 2, 2,
9722 fragP->fr_symbol,
9723 fragP->fr_offset, 1,
9724 reloc_type);
fddf5b5b
AM		 9725 break;
9726 }
9727 /* Fall through. */
9728
9729 case COND_JUMP:
412167cb
AM		 9730 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9731 {
3e02c1cc
AM		 9732 fixS *fixP;
9733
412167cb 9734 fragP->fr_fix += 1;
3e02c1cc
AM		 9735 fixP = fix_new (fragP, old_fr_fix, 1,
9736 fragP->fr_symbol,
9737 fragP->fr_offset, 1,
9738 BFD_RELOC_8_PCREL);
9739 fixP->fx_signed = 1;
412167cb
AM		 9740 break;
9741 }
93c2a809 9742
24eab124 9743 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9744 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9745 opcode[1] = opcode[0] + 0x10;
f6af82bd 9746 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9747 /* We've added an opcode byte. */
9748 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9749 fix_new (fragP, old_fr_fix + 1, size,
9750 fragP->fr_symbol,
9751 fragP->fr_offset, 1,
9752 reloc_type);
252b5132 9753 break;
fddf5b5b
AM		 9754
9755 default:
9756 BAD_CASE (fragP->fr_subtype);
9757 break;
252b5132
RH		 9758 }
9759 frag_wane (fragP);
ee7fcc42 9760 return fragP->fr_fix - old_fr_fix;
252b5132 9761 }
93c2a809 9762
93c2a809
AM		 9763 /* Guess size depending on current relax state. Initially the relax
9764 state will correspond to a short jump and we return 1, because
9765 the variable part of the frag (the branch offset) is one byte
9766 long. However, we can relax a section more than once and in that
9767 case we must either set fr_subtype back to the unrelaxed state,
9768 or return the value for the appropriate branch. */
9769 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9770}
9771
47926f60
KH		 9772/* Called after relax() is finished.
9773
9774 In: Address of frag.
9775 fr_type == rs_machine_dependent.
9776 fr_subtype is what the address relaxed to.
9777
9778 Out: Any fixSs and constants are set up.
9779 Caller will turn frag into a ".space 0". */
9780
252b5132 9781void
7016a5d5
TG		 9782md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9783 fragS *fragP)
252b5132 9784{
29b0f896 9785 unsigned char *opcode;
252b5132 9786 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9787 offsetT target_address;
9788 offsetT opcode_address;
252b5132 9789 unsigned int extension = 0;
847f7ad4 9790 offsetT displacement_from_opcode_start;
252b5132
RH		 9791
9792 opcode = (unsigned char *) fragP->fr_opcode;
9793
47926f60 9794 /* Address we want to reach in file space. */
252b5132 9795 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9796
47926f60 9797 /* Address opcode resides at in file space. */
252b5132
RH		 9798 opcode_address = fragP->fr_address + fragP->fr_fix;
9799
47926f60 9800 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9801 displacement_from_opcode_start = target_address - opcode_address;
9802
fddf5b5b 9803 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9804 {
47926f60
KH		 9805 /* Don't have to change opcode. */
9806 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9807 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9808 }
9809 else
9810 {
9811 if (no_cond_jump_promotion
9812 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9813 as_warn_where (fragP->fr_file, fragP->fr_line,
9814 _("long jump required"));
252b5132 9815
fddf5b5b
AM		 9816 switch (fragP->fr_subtype)
9817 {
9818 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9819 extension = 4; /* 1 opcode + 4 displacement */
9820 opcode[0] = 0xe9;
9821 where_to_put_displacement = &opcode[1];
9822 break;
252b5132 9823
fddf5b5b
AM		 9824 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9825 extension = 2; /* 1 opcode + 2 displacement */
9826 opcode[0] = 0xe9;
9827 where_to_put_displacement = &opcode[1];
9828 break;
252b5132 9829
fddf5b5b
AM		 9830 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9831 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9832 extension = 5; /* 2 opcode + 4 displacement */
9833 opcode[1] = opcode[0] + 0x10;
9834 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9835 where_to_put_displacement = &opcode[2];
9836 break;
252b5132 9837
fddf5b5b
AM		 9838 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9839 extension = 3; /* 2 opcode + 2 displacement */
9840 opcode[1] = opcode[0] + 0x10;
9841 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9842 where_to_put_displacement = &opcode[2];
9843 break;
252b5132 9844
fddf5b5b
AM		 9845 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9846 extension = 4;
9847 opcode[0] ^= 1;
9848 opcode[1] = 3;
9849 opcode[2] = 0xe9;
9850 where_to_put_displacement = &opcode[3];
9851 break;
9852
9853 default:
9854 BAD_CASE (fragP->fr_subtype);
9855 break;
9856 }
252b5132 9857 }
fddf5b5b 9858
7b81dfbb
AJ		 9859 /* If size if less then four we are sure that the operand fits,
9860 but if it's 4, then it could be that the displacement is larger
9861 then -/+ 2GB. */
9862 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9863 && object_64bit
9864 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9865 + ((addressT) 1 << 31))
9866 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9867 {
9868 as_bad_where (fragP->fr_file, fragP->fr_line,
9869 _("jump target out of range"));
9870 /* Make us emit 0. */
9871 displacement_from_opcode_start = extension;
9872 }
47926f60 9873 /* Now put displacement after opcode. */
252b5132
RH		 9874 md_number_to_chars ((char *) where_to_put_displacement,
9875 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9876 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9877 fragP->fr_fix += extension;
9878}
9879\f
7016a5d5 9880/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9881 by our caller that we have all the info we need to fix it up.
9882
7016a5d5
TG		 9883 Parameter valP is the pointer to the value of the bits.
9884
252b5132
RH		 9885 On the 386, immediates, displacements, and data pointers are all in
9886 the same (little-endian) format, so we don't need to care about which
9887 we are handling. */
9888
94f592af 9889void
7016a5d5 9890md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9891{
94f592af 9892 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9893 valueT value = *valP;
252b5132 9894
f86103b7 9895#if !defined (TE_Mach)
93382f6d
AM		 9896 if (fixP->fx_pcrel)
9897 {
9898 switch (fixP->fx_r_type)
9899 {
5865bb77
ILT		 9900 default:
9901 break;
9902
d6ab8113
JB		 9903 case BFD_RELOC_64:
9904 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9905 break;
93382f6d 9906 case BFD_RELOC_32:
ae8887b5 9907 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9908 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9909 break;
9910 case BFD_RELOC_16:
9911 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9912 break;
9913 case BFD_RELOC_8:
9914 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9915 break;
9916 }
9917 }
252b5132 9918
a161fe53 9919 if (fixP->fx_addsy != NULL
31312f95 9920 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9921 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9922 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9923 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9924 && !use_rela_relocations)
252b5132 9925 {
31312f95
AM		 9926 /* This is a hack. There should be a better way to handle this.
9927 This covers for the fact that bfd_install_relocation will
9928 subtract the current location (for partial_inplace, PC relative
9929 relocations); see more below. */
252b5132 9930#ifndef OBJ_AOUT
718ddfc0 9931 if (IS_ELF
252b5132
RH		 9932#ifdef TE_PE
9933 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9934#endif
9935 )
9936 value += fixP->fx_where + fixP->fx_frag->fr_address;
9937#endif
9938#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9939 if (IS_ELF)
252b5132 9940 {
6539b54b 9941 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9942
6539b54b 9943 if ((sym_seg == seg
2f66722d 9944 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9945 && sym_seg != absolute_section))
af65af87 9946 && !generic_force_reloc (fixP))
2f66722d
AM		 9947 {
9948 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9949 bfd_install_relocation subtracts them out again. I think
9950 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9951 it. FIXME. */
9952 value += fixP->fx_where + fixP->fx_frag->fr_address;
9953 }
252b5132
RH		 9954 }
9955#endif
9956#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9957 /* For some reason, the PE format does not store a
9958 section address offset for a PC relative symbol. */
9959 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9960 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9961 value += md_pcrel_from (fixP);
9962#endif
9963 }
fbeb56a4 9964#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9965 if (fixP->fx_addsy != NULL
9966 && S_IS_WEAK (fixP->fx_addsy)
9967 /* PR 16858: Do not modify weak function references. */
9968 && ! fixP->fx_pcrel)
fbeb56a4 9969 {
296a8689
NC		 9970#if !defined (TE_PEP)
9971 /* For x86 PE weak function symbols are neither PC-relative
9972 nor do they set S_IS_FUNCTION. So the only reliable way
9973 to detect them is to check the flags of their containing
9974 section. */
9975 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9976 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9977 ;
9978 else
9979#endif
fbeb56a4
DK		 9980 value -= S_GET_VALUE (fixP->fx_addsy);
9981 }
9982#endif
252b5132
RH		 9983
9984 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9985 and we must not disappoint it. */
252b5132 9986#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9987 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9988 switch (fixP->fx_r_type)
9989 {
9990 case BFD_RELOC_386_PLT32:
3e73aa7c 9991 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9992 /* Make the jump instruction point to the address of the operand. At
9993 runtime we merely add the offset to the actual PLT entry. */
9994 value = -4;
9995 break;
31312f95 9996
13ae64f3
JJ		 9997 case BFD_RELOC_386_TLS_GD:
9998 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9999 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10000 case BFD_RELOC_386_TLS_IE:
10001 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 10002 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 10003 case BFD_RELOC_X86_64_TLSGD:
10004 case BFD_RELOC_X86_64_TLSLD:
10005 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 10006 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 10007 value = 0; /* Fully resolved at runtime. No addend. */
10008 /* Fallthrough */
10009 case BFD_RELOC_386_TLS_LE:
10010 case BFD_RELOC_386_TLS_LDO_32:
10011 case BFD_RELOC_386_TLS_LE_32:
10012 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10013 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 10014 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 10015 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 10016 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10017 break;
10018
67a4f2b7
AO		 10019 case BFD_RELOC_386_TLS_DESC_CALL:
10020 case BFD_RELOC_X86_64_TLSDESC_CALL:
10021 value = 0; /* Fully resolved at runtime. No addend. */
10022 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10023 fixP->fx_done = 0;
10024 return;
10025
47926f60
KH		 10026 case BFD_RELOC_VTABLE_INHERIT:
10027 case BFD_RELOC_VTABLE_ENTRY:
10028 fixP->fx_done = 0;
94f592af 10029 return;
47926f60
KH		 10030
10031 default:
10032 break;
10033 }
10034#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 10035 *valP = value;
f86103b7 10036#endif /* !defined (TE_Mach) */
3e73aa7c 10037
3e73aa7c 10038 /* Are we finished with this relocation now? */
c6682705 10039 if (fixP->fx_addsy == NULL)
3e73aa7c 10040 fixP->fx_done = 1;
fbeb56a4
DK		 10041#if defined (OBJ_COFF) && defined (TE_PE)
10042 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10043 {
10044 fixP->fx_done = 0;
10045 /* Remember value for tc_gen_reloc. */
10046 fixP->fx_addnumber = value;
10047 /* Clear out the frag for now. */
10048 value = 0;
10049 }
10050#endif
3e73aa7c
JH		 10051 else if (use_rela_relocations)
10052 {
10053 fixP->fx_no_overflow = 1;
062cd5e7
AS		 10054 /* Remember value for tc_gen_reloc. */
10055 fixP->fx_addnumber = value;
3e73aa7c
JH		 10056 value = 0;
10057 }
f86103b7 10058
94f592af 10059 md_number_to_chars (p, value, fixP->fx_size);
252b5132 10060}
252b5132 10061\f
6d4af3c2 10062const char *
499ac353 10063md_atof (int type, char *litP, int *sizeP)
252b5132 10064{
499ac353
NC		 10065 /* This outputs the LITTLENUMs in REVERSE order;
10066 in accord with the bigendian 386. */
10067 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 10068}
10069\f
2d545b82 10070static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 10071
252b5132 10072static char *
e3bb37b5 10073output_invalid (int c)
252b5132 10074{
3882b010 10075 if (ISPRINT (c))
f9f21a03
L		 10076 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10077 "'%c'", c);
252b5132 10078 else
f9f21a03 10079 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 10080 "(0x%x)", (unsigned char) c);
252b5132
RH		 10081 return output_invalid_buf;
10082}
10083
af6bdddf 10084/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 10085
10086static const reg_entry *
4d1bb795 10087parse_real_register (char *reg_string, char **end_op)
252b5132 10088{
af6bdddf
AM		 10089 char *s = reg_string;
10090 char *p;
252b5132
RH		 10091 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10092 const reg_entry *r;
10093
10094 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10095 if (*s == REGISTER_PREFIX)
10096 ++s;
10097
10098 if (is_space_char (*s))
10099 ++s;
10100
10101 p = reg_name_given;
af6bdddf 10102 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 10103 {
10104 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 10105 return (const reg_entry *) NULL;
10106 s++;
252b5132
RH		 10107 }
10108
6588847e
DN		 10109 /* For naked regs, make sure that we are not dealing with an identifier.
10110 This prevents confusing an identifier like `eax_var' with register
10111 `eax'. */
10112 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10113 return (const reg_entry *) NULL;
10114
af6bdddf 10115 *end_op = s;
252b5132
RH		 10116
10117 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10118
5f47d35b 10119 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 10120 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 10121 {
5f47d35b
AM		 10122 if (is_space_char (*s))
10123 ++s;
10124 if (*s == '(')
10125 {
af6bdddf 10126 ++s;
5f47d35b
AM		 10127 if (is_space_char (*s))
10128 ++s;
10129 if (*s >= '0' && *s <= '7')
10130 {
db557034 10131 int fpr = *s - '0';
af6bdddf 10132 ++s;
5f47d35b
AM		 10133 if (is_space_char (*s))
10134 ++s;
10135 if (*s == ')')
10136 {
10137 *end_op = s + 1;
1e9cc1c2 10138 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 10139 know (r);
10140 return r + fpr;
5f47d35b 10141 }
5f47d35b 10142 }
47926f60 10143 /* We have "%st(" then garbage. */
5f47d35b
AM		 10144 return (const reg_entry *) NULL;
10145 }
10146 }
10147
a60de03c
JB		 10148 if (r == NULL || allow_pseudo_reg)
10149 return r;
10150
0dfbf9d7 10151 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 10152 return (const reg_entry *) NULL;
10153
dc821c5f 10154 if ((r->reg_type.bitfield.dword
192dc9c6
JB		 10155 || r->reg_type.bitfield.sreg3
10156 || r->reg_type.bitfield.control
10157 || r->reg_type.bitfield.debug
10158 || r->reg_type.bitfield.test)
10159 && !cpu_arch_flags.bitfield.cpui386)
10160 return (const reg_entry *) NULL;
10161
ca0d63fe 10162 if (r->reg_type.bitfield.tbyte
309d3373
JB		 10163 && !cpu_arch_flags.bitfield.cpu8087
10164 && !cpu_arch_flags.bitfield.cpu287
10165 && !cpu_arch_flags.bitfield.cpu387)
10166 return (const reg_entry *) NULL;
10167
1848e567 10168 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
192dc9c6
JB		 10169 return (const reg_entry *) NULL;
10170
1b54b8d7 10171 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
192dc9c6
JB		 10172 return (const reg_entry *) NULL;
10173
1b54b8d7 10174 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
40f12533
L		 10175 return (const reg_entry *) NULL;
10176
1b54b8d7 10177 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
1848e567
L		 10178 return (const reg_entry *) NULL;
10179
10180 if (r->reg_type.bitfield.regmask
10181 && !cpu_arch_flags.bitfield.cpuregmask)
43234a1e
L		 10182 return (const reg_entry *) NULL;
10183
db51cc60 10184 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 10185 if (!allow_index_reg
db51cc60
L		 10186 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10187 return (const reg_entry *) NULL;
10188
43234a1e
L		 10189 /* Upper 16 vector register is only available with VREX in 64bit
10190 mode. */
10191 if ((r->reg_flags & RegVRex))
10192 {
86fa6981
L		 10193 if (i.vec_encoding == vex_encoding_default)
10194 i.vec_encoding = vex_encoding_evex;
10195
43234a1e 10196 if (!cpu_arch_flags.bitfield.cpuvrex
86fa6981 10197 || i.vec_encoding != vex_encoding_evex
43234a1e
L		 10198 || flag_code != CODE_64BIT)
10199 return (const reg_entry *) NULL;
43234a1e
L		 10200 }
10201
a60de03c 10202 if (((r->reg_flags & (RegRex64 | RegRex))
dc821c5f 10203 || r->reg_type.bitfield.qword)
40fb9820 10204 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 10205 || !operand_type_equal (&r->reg_type, &control))
1ae00879 10206 && flag_code != CODE_64BIT)
20f0a1fc 10207 return (const reg_entry *) NULL;
1ae00879 10208
b7240065
JB		 10209 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10210 return (const reg_entry *) NULL;
10211
252b5132
RH		 10212 return r;
10213}
4d1bb795
JB		 10214
10215/* REG_STRING starts *before* REGISTER_PREFIX. */
10216
10217static const reg_entry *
10218parse_register (char *reg_string, char **end_op)
10219{
10220 const reg_entry *r;
10221
10222 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10223 r = parse_real_register (reg_string, end_op);
10224 else
10225 r = NULL;
10226 if (!r)
10227 {
10228 char *save = input_line_pointer;
10229 char c;
10230 symbolS *symbolP;
10231
10232 input_line_pointer = reg_string;
d02603dc 10233 c = get_symbol_name (&reg_string);
4d1bb795
JB		 10234 symbolP = symbol_find (reg_string);
10235 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10236 {
10237 const expressionS *e = symbol_get_value_expression (symbolP);
10238
0398aac5 10239 know (e->X_op == O_register);
4eed87de 10240 know (e->X_add_number >= 0
c3fe08fa 10241 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 10242 r = i386_regtab + e->X_add_number;
d3bb6b49 10243 if ((r->reg_flags & RegVRex))
86fa6981 10244 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 10245 *end_op = input_line_pointer;
10246 }
10247 *input_line_pointer = c;
10248 input_line_pointer = save;
10249 }
10250 return r;
10251}
10252
10253int
10254i386_parse_name (char *name, expressionS *e, char *nextcharP)
10255{
10256 const reg_entry *r;
10257 char *end = input_line_pointer;
10258
10259 *end = *nextcharP;
10260 r = parse_register (name, &input_line_pointer);
10261 if (r && end <= input_line_pointer)
10262 {
10263 *nextcharP = *input_line_pointer;
10264 *input_line_pointer = 0;
10265 e->X_op = O_register;
10266 e->X_add_number = r - i386_regtab;
10267 return 1;
10268 }
10269 input_line_pointer = end;
10270 *end = 0;
ee86248c 10271 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 10272}
10273
10274void
10275md_operand (expressionS *e)
10276{
ee86248c
JB		 10277 char *end;
10278 const reg_entry *r;
4d1bb795 10279
ee86248c
JB		 10280 switch (*input_line_pointer)
10281 {
10282 case REGISTER_PREFIX:
10283 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 10284 if (r)
10285 {
10286 e->X_op = O_register;
10287 e->X_add_number = r - i386_regtab;
10288 input_line_pointer = end;
10289 }
ee86248c
JB		 10290 break;
10291
10292 case '[':
9c2799c2 10293 gas_assert (intel_syntax);
ee86248c
JB		 10294 end = input_line_pointer++;
10295 expression (e);
10296 if (*input_line_pointer == ']')
10297 {
10298 ++input_line_pointer;
10299 e->X_op_symbol = make_expr_symbol (e);
10300 e->X_add_symbol = NULL;
10301 e->X_add_number = 0;
10302 e->X_op = O_index;
10303 }
10304 else
10305 {
10306 e->X_op = O_absent;
10307 input_line_pointer = end;
10308 }
10309 break;
4d1bb795
JB		 10310 }
10311}
10312
252b5132 10313\f
4cc782b5 10314#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
b6f8c7c4 10315const char *md_shortopts = "kVQ:sqnO::";
252b5132 10316#else
b6f8c7c4 10317const char *md_shortopts = "qnO::";
252b5132 10318#endif
6e0b89ee 10319
3e73aa7c 10320#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 10321#define OPTION_64 (OPTION_MD_BASE + 1)
10322#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 10323#define OPTION_MARCH (OPTION_MD_BASE + 3)
10324#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 10325#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10326#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10327#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10328#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
bd5dea88 10329#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
c0f3af97 10330#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 10331#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 10332#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10333#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10334#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 10335#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 10336#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10337#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 10338#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 10339#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 10340#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 10341#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 10342#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10343#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 10344#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
b3b91714 10345
99ad8390
NC		 10346struct option md_longopts[] =
10347{
3e73aa7c 10348 {"32", no_argument, NULL, OPTION_32},
321098a5 10349#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10350 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 10351 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 10352#endif
10353#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10354 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 10355 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 10356#endif
b3b91714 10357 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 10358 {"march", required_argument, NULL, OPTION_MARCH},
10359 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 10360 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10361 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10362 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10363 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
c0f3af97 10364 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 10365 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 10366 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 10367 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 10368 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 10369 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10370 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 10371# if defined (TE_PE) || defined (TE_PEP)
10372 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10373#endif
d1982f93 10374 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 10375 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 10376 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 10377 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 10378 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10379 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 10380 {NULL, no_argument, NULL, 0}
10381};
10382size_t md_longopts_size = sizeof (md_longopts);
10383
10384int
17b9d67d 10385md_parse_option (int c, const char *arg)
252b5132 10386{
91d6fa6a 10387 unsigned int j;
293f5f65 10388 char *arch, *next, *saved;
9103f4f4 10389
252b5132
RH		 10390 switch (c)
10391 {
12b55ccc
L		 10392 case 'n':
10393 optimize_align_code = 0;
10394 break;
10395
a38cf1db
AM		 10396 case 'q':
10397 quiet_warnings = 1;
252b5132
RH		 10398 break;
10399
10400#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 10401 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10402 should be emitted or not. FIXME: Not implemented. */
10403 case 'Q':
252b5132
RH		 10404 break;
10405
10406 /* -V: SVR4 argument to print version ID. */
10407 case 'V':
10408 print_version_id ();
10409 break;
10410
a38cf1db
AM		 10411 /* -k: Ignore for FreeBSD compatibility. */
10412 case 'k':
252b5132 10413 break;
4cc782b5
ILT		 10414
10415 case 's':
10416 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 10417 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 10418 break;
8dcea932
L		 10419
10420 case OPTION_MSHARED:
10421 shared = 1;
10422 break;
99ad8390 10423#endif
321098a5 10424#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10425 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 10426 case OPTION_64:
10427 {
10428 const char **list, **l;
10429
3e73aa7c
JH		 10430 list = bfd_target_list ();
10431 for (l = list; *l != NULL; l++)
8620418b 10432 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 10433 || strcmp (*l, "coff-x86-64") == 0
10434 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 10435 || strcmp (*l, "pei-x86-64") == 0
10436 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 10437 {
10438 default_arch = "x86_64";
10439 break;
10440 }
3e73aa7c 10441 if (*l == NULL)
2b5d6a91 10442 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 10443 free (list);
10444 }
10445 break;
10446#endif
252b5132 10447
351f65ca 10448#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10449 case OPTION_X32:
351f65ca
L		 10450 if (IS_ELF)
10451 {
10452 const char **list, **l;
10453
10454 list = bfd_target_list ();
10455 for (l = list; *l != NULL; l++)
10456 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10457 {
10458 default_arch = "x86_64:32";
10459 break;
10460 }
10461 if (*l == NULL)
2b5d6a91 10462 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 10463 free (list);
10464 }
10465 else
10466 as_fatal (_("32bit x86_64 is only supported for ELF"));
10467 break;
10468#endif
10469
6e0b89ee
AM		 10470 case OPTION_32:
10471 default_arch = "i386";
10472 break;
10473
b3b91714
AM		 10474 case OPTION_DIVIDE:
10475#ifdef SVR4_COMMENT_CHARS
10476 {
10477 char *n, *t;
10478 const char *s;
10479
add39d23 10480 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 10481 t = n;
10482 for (s = i386_comment_chars; *s != '\0'; s++)
10483 if (*s != '/')
10484 *t++ = *s;
10485 *t = '\0';
10486 i386_comment_chars = n;
10487 }
10488#endif
10489 break;
10490
9103f4f4 10491 case OPTION_MARCH:
293f5f65
L		 10492 saved = xstrdup (arg);
10493 arch = saved;
10494 /* Allow -march=+nosse. */
10495 if (*arch == '+')
10496 arch++;
6305a203 10497 do
9103f4f4 10498 {
6305a203 10499 if (*arch == '.')
2b5d6a91 10500 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10501 next = strchr (arch, '+');
10502 if (next)
10503 *next++ = '\0';
91d6fa6a 10504 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10505 {
91d6fa6a 10506 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10507 {
6305a203 10508 /* Processor. */
1ded5609
JB		 10509 if (! cpu_arch[j].flags.bitfield.cpui386)
10510 continue;
10511
91d6fa6a 10512 cpu_arch_name = cpu_arch[j].name;
6305a203 10513 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10514 cpu_arch_flags = cpu_arch[j].flags;
10515 cpu_arch_isa = cpu_arch[j].type;
10516 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10517 if (!cpu_arch_tune_set)
10518 {
10519 cpu_arch_tune = cpu_arch_isa;
10520 cpu_arch_tune_flags = cpu_arch_isa_flags;
10521 }
10522 break;
10523 }
91d6fa6a
NC		 10524 else if (*cpu_arch [j].name == '.'
10525 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 10526 {
33eaf5de 10527 /* ISA extension. */
6305a203 10528 i386_cpu_flags flags;
309d3373 10529
293f5f65
L		 10530 flags = cpu_flags_or (cpu_arch_flags,
10531 cpu_arch[j].flags);
81486035 10532
5b64d091 10533 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10534 {
10535 if (cpu_sub_arch_name)
10536 {
10537 char *name = cpu_sub_arch_name;
10538 cpu_sub_arch_name = concat (name,
91d6fa6a 10539 cpu_arch[j].name,
1bf57e9f 10540 (const char *) NULL);
6305a203
L		 10541 free (name);
10542 }
10543 else
91d6fa6a 10544 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10545 cpu_arch_flags = flags;
a586129e 10546 cpu_arch_isa_flags = flags;
6305a203 10547 }
0089dace
L		 10548 else
10549 cpu_arch_isa_flags
10550 = cpu_flags_or (cpu_arch_isa_flags,
10551 cpu_arch[j].flags);
6305a203 10552 break;
ccc9c027 10553 }
9103f4f4 10554 }
6305a203 10555
293f5f65
L		 10556 if (j >= ARRAY_SIZE (cpu_arch))
10557 {
33eaf5de 10558 /* Disable an ISA extension. */
293f5f65
L		 10559 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10560 if (strcmp (arch, cpu_noarch [j].name) == 0)
10561 {
10562 i386_cpu_flags flags;
10563
10564 flags = cpu_flags_and_not (cpu_arch_flags,
10565 cpu_noarch[j].flags);
10566 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10567 {
10568 if (cpu_sub_arch_name)
10569 {
10570 char *name = cpu_sub_arch_name;
10571 cpu_sub_arch_name = concat (arch,
10572 (const char *) NULL);
10573 free (name);
10574 }
10575 else
10576 cpu_sub_arch_name = xstrdup (arch);
10577 cpu_arch_flags = flags;
10578 cpu_arch_isa_flags = flags;
10579 }
10580 break;
10581 }
10582
10583 if (j >= ARRAY_SIZE (cpu_noarch))
10584 j = ARRAY_SIZE (cpu_arch);
10585 }
10586
91d6fa6a 10587 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10588 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10589
10590 arch = next;
9103f4f4 10591 }
293f5f65
L		 10592 while (next != NULL);
10593 free (saved);
9103f4f4
L		 10594 break;
10595
10596 case OPTION_MTUNE:
10597 if (*arg == '.')
2b5d6a91 10598 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10599 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10600 {
91d6fa6a 10601 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10602 {
ccc9c027 10603 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10604 cpu_arch_tune = cpu_arch [j].type;
10605 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10606 break;
10607 }
10608 }
91d6fa6a 10609 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10610 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10611 break;
10612
1efbbeb4
L		 10613 case OPTION_MMNEMONIC:
10614 if (strcasecmp (arg, "att") == 0)
10615 intel_mnemonic = 0;
10616 else if (strcasecmp (arg, "intel") == 0)
10617 intel_mnemonic = 1;
10618 else
2b5d6a91 10619 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10620 break;
10621
10622 case OPTION_MSYNTAX:
10623 if (strcasecmp (arg, "att") == 0)
10624 intel_syntax = 0;
10625 else if (strcasecmp (arg, "intel") == 0)
10626 intel_syntax = 1;
10627 else
2b5d6a91 10628 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10629 break;
10630
10631 case OPTION_MINDEX_REG:
10632 allow_index_reg = 1;
10633 break;
10634
10635 case OPTION_MNAKED_REG:
10636 allow_naked_reg = 1;
10637 break;
10638
c0f3af97
L		 10639 case OPTION_MSSE2AVX:
10640 sse2avx = 1;
10641 break;
10642
daf50ae7
L		 10643 case OPTION_MSSE_CHECK:
10644 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10645 sse_check = check_error;
daf50ae7 10646 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10647 sse_check = check_warning;
daf50ae7 10648 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10649 sse_check = check_none;
daf50ae7 10650 else
2b5d6a91 10651 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10652 break;
10653
7bab8ab5
JB		 10654 case OPTION_MOPERAND_CHECK:
10655 if (strcasecmp (arg, "error") == 0)
10656 operand_check = check_error;
10657 else if (strcasecmp (arg, "warning") == 0)
10658 operand_check = check_warning;
10659 else if (strcasecmp (arg, "none") == 0)
10660 operand_check = check_none;
10661 else
10662 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10663 break;
10664
539f890d
L		 10665 case OPTION_MAVXSCALAR:
10666 if (strcasecmp (arg, "128") == 0)
10667 avxscalar = vex128;
10668 else if (strcasecmp (arg, "256") == 0)
10669 avxscalar = vex256;
10670 else
2b5d6a91 10671 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10672 break;
10673
7e8b059b
L		 10674 case OPTION_MADD_BND_PREFIX:
10675 add_bnd_prefix = 1;
10676 break;
10677
43234a1e
L		 10678 case OPTION_MEVEXLIG:
10679 if (strcmp (arg, "128") == 0)
10680 evexlig = evexl128;
10681 else if (strcmp (arg, "256") == 0)
10682 evexlig = evexl256;
10683 else if (strcmp (arg, "512") == 0)
10684 evexlig = evexl512;
10685 else
10686 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10687 break;
10688
d3d3c6db
IT		 10689 case OPTION_MEVEXRCIG:
10690 if (strcmp (arg, "rne") == 0)
10691 evexrcig = rne;
10692 else if (strcmp (arg, "rd") == 0)
10693 evexrcig = rd;
10694 else if (strcmp (arg, "ru") == 0)
10695 evexrcig = ru;
10696 else if (strcmp (arg, "rz") == 0)
10697 evexrcig = rz;
10698 else
10699 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10700 break;
10701
43234a1e
L		 10702 case OPTION_MEVEXWIG:
10703 if (strcmp (arg, "0") == 0)
10704 evexwig = evexw0;
10705 else if (strcmp (arg, "1") == 0)
10706 evexwig = evexw1;
10707 else
10708 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10709 break;
10710
167ad85b
TG		 10711# if defined (TE_PE) || defined (TE_PEP)
10712 case OPTION_MBIG_OBJ:
10713 use_big_obj = 1;
10714 break;
10715#endif
10716
d1982f93 10717 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10718 if (strcasecmp (arg, "yes") == 0)
10719 omit_lock_prefix = 1;
10720 else if (strcasecmp (arg, "no") == 0)
10721 omit_lock_prefix = 0;
10722 else
10723 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10724 break;
10725
e4e00185
AS		 10726 case OPTION_MFENCE_AS_LOCK_ADD:
10727 if (strcasecmp (arg, "yes") == 0)
10728 avoid_fence = 1;
10729 else if (strcasecmp (arg, "no") == 0)
10730 avoid_fence = 0;
10731 else
10732 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10733 break;
10734
0cb4071e
L		 10735 case OPTION_MRELAX_RELOCATIONS:
10736 if (strcasecmp (arg, "yes") == 0)
10737 generate_relax_relocations = 1;
10738 else if (strcasecmp (arg, "no") == 0)
10739 generate_relax_relocations = 0;
10740 else
10741 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10742 break;
10743
5db04b09 10744 case OPTION_MAMD64:
e89c5eaa 10745 intel64 = 0;
5db04b09
L		 10746 break;
10747
10748 case OPTION_MINTEL64:
e89c5eaa 10749 intel64 = 1;
5db04b09
L		 10750 break;
10751
b6f8c7c4
L		 10752 case 'O':
10753 if (arg == NULL)
10754 {
10755 optimize = 1;
10756 /* Turn off -Os. */
10757 optimize_for_space = 0;
10758 }
10759 else if (*arg == 's')
10760 {
10761 optimize_for_space = 1;
10762 /* Turn on all encoding optimizations. */
10763 optimize = -1;
10764 }
10765 else
10766 {
10767 optimize = atoi (arg);
10768 /* Turn off -Os. */
10769 optimize_for_space = 0;
10770 }
10771 break;
10772
252b5132
RH		 10773 default:
10774 return 0;
10775 }
10776 return 1;
10777}
10778
8a2c8fef
L		 10779#define MESSAGE_TEMPLATE \
10780" "
10781
293f5f65
L		 10782static char *
10783output_message (FILE *stream, char *p, char *message, char *start,
10784 int *left_p, const char *name, int len)
10785{
10786 int size = sizeof (MESSAGE_TEMPLATE);
10787 int left = *left_p;
10788
10789 /* Reserve 2 spaces for ", " or ",\0" */
10790 left -= len + 2;
10791
10792 /* Check if there is any room. */
10793 if (left >= 0)
10794 {
10795 if (p != start)
10796 {
10797 *p++ = ',';
10798 *p++ = ' ';
10799 }
10800 p = mempcpy (p, name, len);
10801 }
10802 else
10803 {
10804 /* Output the current message now and start a new one. */
10805 *p++ = ',';
10806 *p = '\0';
10807 fprintf (stream, "%s\n", message);
10808 p = start;
10809 left = size - (start - message) - len - 2;
10810
10811 gas_assert (left >= 0);
10812
10813 p = mempcpy (p, name, len);
10814 }
10815
10816 *left_p = left;
10817 return p;
10818}
10819
8a2c8fef 10820static void
1ded5609 10821show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10822{
10823 static char message[] = MESSAGE_TEMPLATE;
10824 char *start = message + 27;
10825 char *p;
10826 int size = sizeof (MESSAGE_TEMPLATE);
10827 int left;
10828 const char *name;
10829 int len;
10830 unsigned int j;
10831
10832 p = start;
10833 left = size - (start - message);
10834 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10835 {
10836 /* Should it be skipped? */
10837 if (cpu_arch [j].skip)
10838 continue;
10839
10840 name = cpu_arch [j].name;
10841 len = cpu_arch [j].len;
10842 if (*name == '.')
10843 {
10844 /* It is an extension. Skip if we aren't asked to show it. */
10845 if (ext)
10846 {
10847 name++;
10848 len--;
10849 }
10850 else
10851 continue;
10852 }
10853 else if (ext)
10854 {
10855 /* It is an processor. Skip if we show only extension. */
10856 continue;
10857 }
1ded5609
JB		 10858 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10859 {
10860 /* It is an impossible processor - skip. */
10861 continue;
10862 }
8a2c8fef 10863
293f5f65 10864 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10865 }
10866
293f5f65
L		 10867 /* Display disabled extensions. */
10868 if (ext)
10869 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10870 {
10871 name = cpu_noarch [j].name;
10872 len = cpu_noarch [j].len;
10873 p = output_message (stream, p, message, start, &left, name,
10874 len);
10875 }
10876
8a2c8fef
L		 10877 *p = '\0';
10878 fprintf (stream, "%s\n", message);
10879}
10880
252b5132 10881void
8a2c8fef 10882md_show_usage (FILE *stream)
252b5132 10883{
4cc782b5
ILT		 10884#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10885 fprintf (stream, _("\
a38cf1db
AM		 10886 -Q ignored\n\
10887 -V print assembler version number\n\
b3b91714
AM		 10888 -k ignored\n"));
10889#endif
10890 fprintf (stream, _("\
12b55ccc 10891 -n Do not optimize code alignment\n\
b3b91714
AM		 10892 -q quieten some warnings\n"));
10893#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10894 fprintf (stream, _("\
a38cf1db 10895 -s ignored\n"));
b3b91714 10896#endif
321098a5
L		 10897#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10898 || defined (TE_PE) || defined (TE_PEP))
751d281c 10899 fprintf (stream, _("\
570561f7 10900 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10901#endif
b3b91714
AM		 10902#ifdef SVR4_COMMENT_CHARS
10903 fprintf (stream, _("\
10904 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10905#else
10906 fprintf (stream, _("\
b3b91714 10907 --divide ignored\n"));
4cc782b5 10908#endif
9103f4f4 10909 fprintf (stream, _("\
6305a203 10910 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10911 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10912 show_arch (stream, 0, 1);
8a2c8fef
L		 10913 fprintf (stream, _("\
10914 EXTENSION is combination of:\n"));
1ded5609 10915 show_arch (stream, 1, 0);
6305a203 10916 fprintf (stream, _("\
8a2c8fef 10917 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10918 show_arch (stream, 0, 0);
ba104c83 10919 fprintf (stream, _("\
c0f3af97
L		 10920 -msse2avx encode SSE instructions with VEX prefix\n"));
10921 fprintf (stream, _("\
daf50ae7
L		 10922 -msse-check=[none|error|warning]\n\
10923 check SSE instructions\n"));
10924 fprintf (stream, _("\
7bab8ab5
JB		 10925 -moperand-check=[none|error|warning]\n\
10926 check operand combinations for validity\n"));
10927 fprintf (stream, _("\
539f890d
L		 10928 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10929 length\n"));
10930 fprintf (stream, _("\
43234a1e
L		 10931 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10932 length\n"));
10933 fprintf (stream, _("\
10934 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10935 for EVEX.W bit ignored instructions\n"));
10936 fprintf (stream, _("\
d3d3c6db
IT		 10937 -mevexrcig=[rne|rd|ru|rz]\n\
10938 encode EVEX instructions with specific EVEX.RC value\n\
10939 for SAE-only ignored instructions\n"));
10940 fprintf (stream, _("\
ba104c83
L		 10941 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10942 fprintf (stream, _("\
10943 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10944 fprintf (stream, _("\
10945 -mindex-reg support pseudo index registers\n"));
10946 fprintf (stream, _("\
10947 -mnaked-reg don't require `%%' prefix for registers\n"));
10948 fprintf (stream, _("\
7e8b059b 10949 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10950 fprintf (stream, _("\
10951 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10952# if defined (TE_PE) || defined (TE_PEP)
10953 fprintf (stream, _("\
10954 -mbig-obj generate big object files\n"));
10955#endif
d022bddd
IT		 10956 fprintf (stream, _("\
10957 -momit-lock-prefix=[no|yes]\n\
10958 strip all lock prefixes\n"));
5db04b09 10959 fprintf (stream, _("\
e4e00185
AS		 10960 -mfence-as-lock-add=[no|yes]\n\
10961 encode lfence, mfence and sfence as\n\
10962 lock addl $0x0, (%%{re}sp)\n"));
10963 fprintf (stream, _("\
0cb4071e
L		 10964 -mrelax-relocations=[no|yes]\n\
10965 generate relax relocations\n"));
10966 fprintf (stream, _("\
5db04b09
L		 10967 -mamd64 accept only AMD64 ISA\n"));
10968 fprintf (stream, _("\
10969 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10970}
10971
3e73aa7c 10972#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10973 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10974 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10975
10976/* Pick the target format to use. */
10977
47926f60 10978const char *
e3bb37b5 10979i386_target_format (void)
252b5132 10980{
351f65ca
L		 10981 if (!strncmp (default_arch, "x86_64", 6))
10982 {
10983 update_code_flag (CODE_64BIT, 1);
10984 if (default_arch[6] == '\0')
7f56bc95 10985 x86_elf_abi = X86_64_ABI;
351f65ca 10986 else
7f56bc95 10987 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10988 }
3e73aa7c 10989 else if (!strcmp (default_arch, "i386"))
78f12dd3 10990 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10991 else if (!strcmp (default_arch, "iamcu"))
10992 {
10993 update_code_flag (CODE_32BIT, 1);
10994 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10995 {
10996 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10997 cpu_arch_name = "iamcu";
10998 cpu_sub_arch_name = NULL;
10999 cpu_arch_flags = iamcu_flags;
11000 cpu_arch_isa = PROCESSOR_IAMCU;
11001 cpu_arch_isa_flags = iamcu_flags;
11002 if (!cpu_arch_tune_set)
11003 {
11004 cpu_arch_tune = cpu_arch_isa;
11005 cpu_arch_tune_flags = cpu_arch_isa_flags;
11006 }
11007 }
8d471ec1 11008 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 11009 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11010 cpu_arch_name);
11011 }
3e73aa7c 11012 else
2b5d6a91 11013 as_fatal (_("unknown architecture"));
89507696
JB		 11014
11015 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11016 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11017 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11018 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11019
252b5132
RH		 11020 switch (OUTPUT_FLAVOR)
11021 {
9384f2ff 11022#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 11023 case bfd_target_aout_flavour:
47926f60 11024 return AOUT_TARGET_FORMAT;
4c63da97 11025#endif
9384f2ff
AM		 11026#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11027# if defined (TE_PE) || defined (TE_PEP)
11028 case bfd_target_coff_flavour:
167ad85b
TG		 11029 if (flag_code == CODE_64BIT)
11030 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11031 else
11032 return "pe-i386";
9384f2ff 11033# elif defined (TE_GO32)
0561d57c
JK		 11034 case bfd_target_coff_flavour:
11035 return "coff-go32";
9384f2ff 11036# else
252b5132
RH		 11037 case bfd_target_coff_flavour:
11038 return "coff-i386";
9384f2ff 11039# endif
4c63da97 11040#endif
3e73aa7c 11041#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 11042 case bfd_target_elf_flavour:
3e73aa7c 11043 {
351f65ca
L		 11044 const char *format;
11045
11046 switch (x86_elf_abi)
4fa24527 11047 {
351f65ca
L		 11048 default:
11049 format = ELF_TARGET_FORMAT;
11050 break;
7f56bc95 11051 case X86_64_ABI:
351f65ca 11052 use_rela_relocations = 1;
4fa24527 11053 object_64bit = 1;
351f65ca
L		 11054 format = ELF_TARGET_FORMAT64;
11055 break;
7f56bc95 11056 case X86_64_X32_ABI:
4fa24527 11057 use_rela_relocations = 1;
351f65ca 11058 object_64bit = 1;
862be3fb 11059 disallow_64bit_reloc = 1;
351f65ca
L		 11060 format = ELF_TARGET_FORMAT32;
11061 break;
4fa24527 11062 }
3632d14b 11063 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 11064 {
7f56bc95 11065 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 11066 as_fatal (_("Intel L1OM is 64bit only"));
11067 return ELF_TARGET_L1OM_FORMAT;
11068 }
b49f93f6 11069 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 11070 {
11071 if (x86_elf_abi != X86_64_ABI)
11072 as_fatal (_("Intel K1OM is 64bit only"));
11073 return ELF_TARGET_K1OM_FORMAT;
11074 }
81486035
L		 11075 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11076 {
11077 if (x86_elf_abi != I386_ABI)
11078 as_fatal (_("Intel MCU is 32bit only"));
11079 return ELF_TARGET_IAMCU_FORMAT;
11080 }
8a9036a4 11081 else
351f65ca 11082 return format;
3e73aa7c 11083 }
e57f8c65
TG		 11084#endif
11085#if defined (OBJ_MACH_O)
11086 case bfd_target_mach_o_flavour:
d382c579
TG		 11087 if (flag_code == CODE_64BIT)
11088 {
11089 use_rela_relocations = 1;
11090 object_64bit = 1;
11091 return "mach-o-x86-64";
11092 }
11093 else
11094 return "mach-o-i386";
4c63da97 11095#endif
252b5132
RH		 11096 default:
11097 abort ();
11098 return NULL;
11099 }
11100}
11101
47926f60 11102#endif /* OBJ_MAYBE_ more than one */
252b5132 11103\f
252b5132 11104symbolS *
7016a5d5 11105md_undefined_symbol (char *name)
252b5132 11106{
18dc2407
ILT		 11107 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11108 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11109 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11110 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 11111 {
11112 if (!GOT_symbol)
11113 {
11114 if (symbol_find (name))
11115 as_bad (_("GOT already in symbol table"));
11116 GOT_symbol = symbol_new (name, undefined_section,
11117 (valueT) 0, &zero_address_frag);
11118 };
11119 return GOT_symbol;
11120 }
252b5132
RH		 11121 return 0;
11122}
11123
11124/* Round up a section size to the appropriate boundary. */
47926f60 11125
252b5132 11126valueT
7016a5d5 11127md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 11128{
4c63da97
AM		 11129#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11130 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11131 {
11132 /* For a.out, force the section size to be aligned. If we don't do
11133 this, BFD will align it for us, but it will not write out the
11134 final bytes of the section. This may be a bug in BFD, but it is
11135 easier to fix it here since that is how the other a.out targets
11136 work. */
11137 int align;
11138
11139 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 11140 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 11141 }
252b5132
RH		 11142#endif
11143
11144 return size;
11145}
11146
11147/* On the i386, PC-relative offsets are relative to the start of the
11148 next instruction. That is, the address of the offset, plus its
11149 size, since the offset is always the last part of the insn. */
11150
11151long
e3bb37b5 11152md_pcrel_from (fixS *fixP)
252b5132
RH		 11153{
11154 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11155}
11156
11157#ifndef I386COFF
11158
11159static void
e3bb37b5 11160s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 11161{
29b0f896 11162 int temp;
252b5132 11163
8a75718c
JB		 11164#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11165 if (IS_ELF)
11166 obj_elf_section_change_hook ();
11167#endif
252b5132
RH		 11168 temp = get_absolute_expression ();
11169 subseg_set (bss_section, (subsegT) temp);
11170 demand_empty_rest_of_line ();
11171}
11172
11173#endif
11174
252b5132 11175void
e3bb37b5 11176i386_validate_fix (fixS *fixp)
252b5132 11177{
02a86693 11178 if (fixp->fx_subsy)
252b5132 11179 {
02a86693 11180 if (fixp->fx_subsy == GOT_symbol)
23df1078 11181 {
02a86693
L		 11182 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11183 {
11184 if (!object_64bit)
11185 abort ();
11186#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11187 if (fixp->fx_tcbit2)
56ceb5b5
L		 11188 fixp->fx_r_type = (fixp->fx_tcbit
11189 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11190 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 11191 else
11192#endif
11193 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11194 }
d6ab8113 11195 else
02a86693
L		 11196 {
11197 if (!object_64bit)
11198 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11199 else
11200 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11201 }
11202 fixp->fx_subsy = 0;
23df1078 11203 }
252b5132 11204 }
02a86693
L		 11205#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11206 else if (!object_64bit)
11207 {
11208 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11209 && fixp->fx_tcbit2)
11210 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11211 }
11212#endif
252b5132
RH		 11213}
11214
252b5132 11215arelent *
7016a5d5 11216tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 11217{
11218 arelent *rel;
11219 bfd_reloc_code_real_type code;
11220
11221 switch (fixp->fx_r_type)
11222 {
8ce3d284 11223#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 11224 case BFD_RELOC_SIZE32:
11225 case BFD_RELOC_SIZE64:
11226 if (S_IS_DEFINED (fixp->fx_addsy)
11227 && !S_IS_EXTERNAL (fixp->fx_addsy))
11228 {
11229 /* Resolve size relocation against local symbol to size of
11230 the symbol plus addend. */
11231 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11232 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11233 && !fits_in_unsigned_long (value))
11234 as_bad_where (fixp->fx_file, fixp->fx_line,
11235 _("symbol size computation overflow"));
11236 fixp->fx_addsy = NULL;
11237 fixp->fx_subsy = NULL;
11238 md_apply_fix (fixp, (valueT *) &value, NULL);
11239 return NULL;
11240 }
8ce3d284 11241#endif
1a0670f3 11242 /* Fall through. */
8fd4256d 11243
3e73aa7c
JH		 11244 case BFD_RELOC_X86_64_PLT32:
11245 case BFD_RELOC_X86_64_GOT32:
11246 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11247 case BFD_RELOC_X86_64_GOTPCRELX:
11248 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 11249 case BFD_RELOC_386_PLT32:
11250 case BFD_RELOC_386_GOT32:
02a86693 11251 case BFD_RELOC_386_GOT32X:
252b5132
RH		 11252 case BFD_RELOC_386_GOTOFF:
11253 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 11254 case BFD_RELOC_386_TLS_GD:
11255 case BFD_RELOC_386_TLS_LDM:
11256 case BFD_RELOC_386_TLS_LDO_32:
11257 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 11258 case BFD_RELOC_386_TLS_IE:
11259 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 11260 case BFD_RELOC_386_TLS_LE_32:
11261 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 11262 case BFD_RELOC_386_TLS_GOTDESC:
11263 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 11264 case BFD_RELOC_X86_64_TLSGD:
11265 case BFD_RELOC_X86_64_TLSLD:
11266 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 11267 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 11268 case BFD_RELOC_X86_64_GOTTPOFF:
11269 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 11270 case BFD_RELOC_X86_64_TPOFF64:
11271 case BFD_RELOC_X86_64_GOTOFF64:
11272 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 11273 case BFD_RELOC_X86_64_GOT64:
11274 case BFD_RELOC_X86_64_GOTPCREL64:
11275 case BFD_RELOC_X86_64_GOTPC64:
11276 case BFD_RELOC_X86_64_GOTPLT64:
11277 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 11278 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11279 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 11280 case BFD_RELOC_RVA:
11281 case BFD_RELOC_VTABLE_ENTRY:
11282 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 11283#ifdef TE_PE
11284 case BFD_RELOC_32_SECREL:
11285#endif
252b5132
RH		 11286 code = fixp->fx_r_type;
11287 break;
dbbaec26
L		 11288 case BFD_RELOC_X86_64_32S:
11289 if (!fixp->fx_pcrel)
11290 {
11291 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11292 code = fixp->fx_r_type;
11293 break;
11294 }
1a0670f3 11295 /* Fall through. */
252b5132 11296 default:
93382f6d 11297 if (fixp->fx_pcrel)
252b5132 11298 {
93382f6d
AM		 11299 switch (fixp->fx_size)
11300 {
11301 default:
b091f402
AM		 11302 as_bad_where (fixp->fx_file, fixp->fx_line,
11303 _("can not do %d byte pc-relative relocation"),
11304 fixp->fx_size);
93382f6d
AM		 11305 code = BFD_RELOC_32_PCREL;
11306 break;
11307 case 1: code = BFD_RELOC_8_PCREL; break;
11308 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 11309 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 11310#ifdef BFD64
11311 case 8: code = BFD_RELOC_64_PCREL; break;
11312#endif
93382f6d
AM		 11313 }
11314 }
11315 else
11316 {
11317 switch (fixp->fx_size)
11318 {
11319 default:
b091f402
AM		 11320 as_bad_where (fixp->fx_file, fixp->fx_line,
11321 _("can not do %d byte relocation"),
11322 fixp->fx_size);
93382f6d
AM		 11323 code = BFD_RELOC_32;
11324 break;
11325 case 1: code = BFD_RELOC_8; break;
11326 case 2: code = BFD_RELOC_16; break;
11327 case 4: code = BFD_RELOC_32; break;
937149dd 11328#ifdef BFD64
3e73aa7c 11329 case 8: code = BFD_RELOC_64; break;
937149dd 11330#endif
93382f6d 11331 }
252b5132
RH		 11332 }
11333 break;
11334 }
252b5132 11335
d182319b
JB		 11336 if ((code == BFD_RELOC_32
11337 || code == BFD_RELOC_32_PCREL
11338 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 11339 && GOT_symbol
11340 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 11341 {
4fa24527 11342 if (!object_64bit)
d6ab8113
JB		 11343 code = BFD_RELOC_386_GOTPC;
11344 else
11345 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 11346 }
7b81dfbb
AJ		 11347 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11348 && GOT_symbol
11349 && fixp->fx_addsy == GOT_symbol)
11350 {
11351 code = BFD_RELOC_X86_64_GOTPC64;
11352 }
252b5132 11353
add39d23
TS		 11354 rel = XNEW (arelent);
11355 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 11356 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 11357
11358 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 11359
3e73aa7c
JH		 11360 if (!use_rela_relocations)
11361 {
11362 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11363 vtable entry to be used in the relocation's section offset. */
11364 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11365 rel->address = fixp->fx_offset;
fbeb56a4
DK		 11366#if defined (OBJ_COFF) && defined (TE_PE)
11367 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11368 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11369 else
11370#endif
c6682705 11371 rel->addend = 0;
3e73aa7c
JH		 11372 }
11373 /* Use the rela in 64bit mode. */
252b5132 11374 else
3e73aa7c 11375 {
862be3fb
L		 11376 if (disallow_64bit_reloc)
11377 switch (code)
11378 {
862be3fb
L		 11379 case BFD_RELOC_X86_64_DTPOFF64:
11380 case BFD_RELOC_X86_64_TPOFF64:
11381 case BFD_RELOC_64_PCREL:
11382 case BFD_RELOC_X86_64_GOTOFF64:
11383 case BFD_RELOC_X86_64_GOT64:
11384 case BFD_RELOC_X86_64_GOTPCREL64:
11385 case BFD_RELOC_X86_64_GOTPC64:
11386 case BFD_RELOC_X86_64_GOTPLT64:
11387 case BFD_RELOC_X86_64_PLTOFF64:
11388 as_bad_where (fixp->fx_file, fixp->fx_line,
11389 _("cannot represent relocation type %s in x32 mode"),
11390 bfd_get_reloc_code_name (code));
11391 break;
11392 default:
11393 break;
11394 }
11395
062cd5e7
AS		 11396 if (!fixp->fx_pcrel)
11397 rel->addend = fixp->fx_offset;
11398 else
11399 switch (code)
11400 {
11401 case BFD_RELOC_X86_64_PLT32:
11402 case BFD_RELOC_X86_64_GOT32:
11403 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11404 case BFD_RELOC_X86_64_GOTPCRELX:
11405 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 11406 case BFD_RELOC_X86_64_TLSGD:
11407 case BFD_RELOC_X86_64_TLSLD:
11408 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 11409 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11410 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 11411 rel->addend = fixp->fx_offset - fixp->fx_size;
11412 break;
11413 default:
11414 rel->addend = (section->vma
11415 - fixp->fx_size
11416 + fixp->fx_addnumber
11417 + md_pcrel_from (fixp));
11418 break;
11419 }
3e73aa7c
JH		 11420 }
11421
252b5132
RH		 11422 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11423 if (rel->howto == NULL)
11424 {
11425 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 11426 _("cannot represent relocation type %s"),
252b5132
RH		 11427 bfd_get_reloc_code_name (code));
11428 /* Set howto to a garbage value so that we can keep going. */
11429 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 11430 gas_assert (rel->howto != NULL);
252b5132
RH		 11431 }
11432
11433 return rel;
11434}
11435
ee86248c 11436#include "tc-i386-intel.c"
54cfded0 11437
a60de03c
JB		 11438void
11439tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 11440{
a60de03c
JB		 11441 int saved_naked_reg;
11442 char saved_register_dot;
54cfded0 11443
a60de03c
JB		 11444 saved_naked_reg = allow_naked_reg;
11445 allow_naked_reg = 1;
11446 saved_register_dot = register_chars['.'];
11447 register_chars['.'] = '.';
11448 allow_pseudo_reg = 1;
11449 expression_and_evaluate (exp);
11450 allow_pseudo_reg = 0;
11451 register_chars['.'] = saved_register_dot;
11452 allow_naked_reg = saved_naked_reg;
11453
e96d56a1 11454 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 11455 {
a60de03c
JB		 11456 if ((addressT) exp->X_add_number < i386_regtab_size)
11457 {
11458 exp->X_op = O_constant;
11459 exp->X_add_number = i386_regtab[exp->X_add_number]
11460 .dw2_regnum[flag_code >> 1];
11461 }
11462 else
11463 exp->X_op = O_illegal;
54cfded0 11464 }
54cfded0
AM		 11465}
11466
11467void
11468tc_x86_frame_initial_instructions (void)
11469{
a60de03c
JB		 11470 static unsigned int sp_regno[2];
11471
11472 if (!sp_regno[flag_code >> 1])
11473 {
11474 char *saved_input = input_line_pointer;
11475 char sp[][4] = {"esp", "rsp"};
11476 expressionS exp;
a4447b93 11477
a60de03c
JB		 11478 input_line_pointer = sp[flag_code >> 1];
11479 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 11480 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 11481 sp_regno[flag_code >> 1] = exp.X_add_number;
11482 input_line_pointer = saved_input;
11483 }
a4447b93 11484
61ff971f
L		 11485 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11486 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 11487}
d2b2c203 11488
d7921315
L		 11489int
11490x86_dwarf2_addr_size (void)
11491{
11492#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11493 if (x86_elf_abi == X86_64_X32_ABI)
11494 return 4;
11495#endif
11496 return bfd_arch_bits_per_address (stdoutput) / 8;
11497}
11498
d2b2c203
DJ		 11499int
11500i386_elf_section_type (const char *str, size_t len)
11501{
11502 if (flag_code == CODE_64BIT
11503 && len == sizeof ("unwind") - 1
11504 && strncmp (str, "unwind", 6) == 0)
11505 return SHT_X86_64_UNWIND;
11506
11507 return -1;
11508}
bb41ade5 11509
ad5fec3b
EB		 11510#ifdef TE_SOLARIS
11511void
11512i386_solaris_fix_up_eh_frame (segT sec)
11513{
11514 if (flag_code == CODE_64BIT)
11515 elf_section_type (sec) = SHT_X86_64_UNWIND;
11516}
11517#endif
11518
bb41ade5
AM		 11519#ifdef TE_PE
11520void
11521tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11522{
91d6fa6a 11523 expressionS exp;
bb41ade5 11524
91d6fa6a
NC		 11525 exp.X_op = O_secrel;
11526 exp.X_add_symbol = symbol;
11527 exp.X_add_number = 0;
11528 emit_expr (&exp, size);
bb41ade5
AM		 11529}
11530#endif
3b22753a
L		 11531
11532#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11533/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11534
01e1a5bc 11535bfd_vma
6d4af3c2 11536x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11537{
11538 if (flag_code == CODE_64BIT)
11539 {
11540 if (letter == 'l')
11541 return SHF_X86_64_LARGE;
11542
8f3bae45 11543 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11544 }
3b22753a 11545 else
8f3bae45 11546 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11547 return -1;
11548}
11549
01e1a5bc 11550bfd_vma
3b22753a
L		 11551x86_64_section_word (char *str, size_t len)
11552{
8620418b 11553 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11554 return SHF_X86_64_LARGE;
11555
11556 return -1;
11557}
11558
11559static void
11560handle_large_common (int small ATTRIBUTE_UNUSED)
11561{
11562 if (flag_code != CODE_64BIT)
11563 {
11564 s_comm_internal (0, elf_common_parse);
11565 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11566 }
11567 else
11568 {
11569 static segT lbss_section;
11570 asection *saved_com_section_ptr = elf_com_section_ptr;
11571 asection *saved_bss_section = bss_section;
11572
11573 if (lbss_section == NULL)
11574 {
11575 flagword applicable;
11576 segT seg = now_seg;
11577 subsegT subseg = now_subseg;
11578
11579 /* The .lbss section is for local .largecomm symbols. */
11580 lbss_section = subseg_new (".lbss", 0);
11581 applicable = bfd_applicable_section_flags (stdoutput);
11582 bfd_set_section_flags (stdoutput, lbss_section,
11583 applicable & SEC_ALLOC);
11584 seg_info (lbss_section)->bss = 1;
11585
11586 subseg_set (seg, subseg);
11587 }
11588
11589 elf_com_section_ptr = &_bfd_elf_large_com_section;
11590 bss_section = lbss_section;
11591
11592 s_comm_internal (0, elf_common_parse);
11593
11594 elf_com_section_ptr = saved_com_section_ptr;
11595 bss_section = saved_bss_section;
11596 }
11597}
11598#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
This page took 2.694391 seconds and 4 git commands to generate.