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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0bfee649 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
c32fa91d 62 REP_PREFIX, LOCK_PREFIX. */
6305a203
L		 63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
c32fa91d
L		 67#define REP_PREFIX 4
68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 86/* Intel Syntax. Use a non-ascii letter since since it never appears
87 in instructions. */
88#define LONG_DOUBLE_MNEM_SUFFIX '\1'
89
90#define END_OF_INSN '\0'
91
92/*
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
97 END.
98 */
99typedef struct
100{
d3ce72d0
NC		 101 const insn_template *start;
102 const insn_template *end;
6305a203
L		 103}
104templates;
105
106/* 386 operand encoding bytes: see 386 book for details of this. */
107typedef struct
108{
109 unsigned int regmem; /* codes register or memory operand */
110 unsigned int reg; /* codes register operand (or extended opcode) */
111 unsigned int mode; /* how to interpret regmem & reg */
112}
113modrm_byte;
114
115/* x86-64 extension prefix. */
116typedef int rex_byte;
117
6305a203
L		 118/* 386 opcode byte to code indirect addressing. */
119typedef struct
120{
121 unsigned base;
122 unsigned index;
123 unsigned scale;
124}
125sib_byte;
126
6305a203
L		 127/* x86 arch names, types and features */
128typedef struct
129{
130 const char *name; /* arch name */
8a2c8fef 131 unsigned int len; /* arch string length */
6305a203
L		 132 enum processor_type type; /* arch type */
133 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 134 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 135}
136arch_entry;
137
e3bb37b5
L		 138static void set_code_flag (int);
139static void set_16bit_gcc_code_flag (int);
140static void set_intel_syntax (int);
1efbbeb4 141static void set_intel_mnemonic (int);
db51cc60 142static void set_allow_index_reg (int);
cb19c032 143static void set_sse_check (int);
e3bb37b5 144static void set_cpu_arch (int);
6482c264 145#ifdef TE_PE
e3bb37b5 146static void pe_directive_secrel (int);
6482c264 147#endif
e3bb37b5
L		 148static void signed_cons (int);
149static char *output_invalid (int c);
ee86248c
JB		 150static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
151 const char *);
152static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
153 const char *);
a7619375 154static int i386_att_operand (char *);
e3bb37b5 155static int i386_intel_operand (char *, int);
ee86248c
JB		 156static int i386_intel_simplify (expressionS *);
157static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 158static const reg_entry *parse_register (char *, char **);
159static char *parse_insn (char *, char *);
160static char *parse_operands (char *, const char *);
161static void swap_operands (void);
4d456e3d 162static void swap_2_operands (int, int);
e3bb37b5
L		 163static void optimize_imm (void);
164static void optimize_disp (void);
d3ce72d0 165static const insn_template *match_template (void);
e3bb37b5
L		 166static int check_string (void);
167static int process_suffix (void);
168static int check_byte_reg (void);
169static int check_long_reg (void);
170static int check_qword_reg (void);
171static int check_word_reg (void);
172static int finalize_imm (void);
173static int process_operands (void);
174static const seg_entry *build_modrm_byte (void);
175static void output_insn (void);
176static void output_imm (fragS *, offsetT);
177static void output_disp (fragS *, offsetT);
29b0f896 178#ifndef I386COFF
e3bb37b5 179static void s_bss (int);
252b5132 180#endif
17d4e2a2
L		 181#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
182static void handle_large_common (int small ATTRIBUTE_UNUSED);
183#endif
252b5132 184
a847613f 185static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 186
c0f3af97
L		 187/* VEX prefix. */
188typedef struct
189{
190 /* VEX prefix is either 2 byte or 3 byte. */
191 unsigned char bytes[3];
192 unsigned int length;
193 /* Destination or source register specifier. */
194 const reg_entry *register_specifier;
195} vex_prefix;
196
252b5132 197/* 'md_assemble ()' gathers together information and puts it into a
47926f60 198 i386_insn. */
252b5132 199
520dc8e8
AM		 200union i386_op
201 {
202 expressionS *disps;
203 expressionS *imms;
204 const reg_entry *regs;
205 };
206
252b5132
RH		 207struct _i386_insn
208 {
47926f60 209 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 210 insn_template tm;
252b5132 211
7d5e4556
L		 212 /* SUFFIX holds the instruction size suffix for byte, word, dword
213 or qword, if given. */
252b5132
RH		 214 char suffix;
215
47926f60 216 /* OPERANDS gives the number of given operands. */
252b5132
RH		 217 unsigned int operands;
218
219 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
220 of given register, displacement, memory operands and immediate
47926f60 221 operands. */
252b5132
RH		 222 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
223
224 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 225 use OP[i] for the corresponding operand. */
40fb9820 226 i386_operand_type types[MAX_OPERANDS];
252b5132 227
520dc8e8
AM		 228 /* Displacement expression, immediate expression, or register for each
229 operand. */
230 union i386_op op[MAX_OPERANDS];
252b5132 231
3e73aa7c
JH		 232 /* Flags for operands. */
233 unsigned int flags[MAX_OPERANDS];
234#define Operand_PCrel 1
235
252b5132 236 /* Relocation type for operand */
f86103b7 237 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 238
252b5132
RH		 239 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
240 the base index byte below. */
241 const reg_entry *base_reg;
242 const reg_entry *index_reg;
243 unsigned int log2_scale_factor;
244
245 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 246 explicit segment overrides are given. */
ce8a8b2f 247 const seg_entry *seg[2];
252b5132
RH		 248
249 /* PREFIX holds all the given prefix opcodes (usually null).
250 PREFIXES is the number of prefix opcodes. */
251 unsigned int prefixes;
252 unsigned char prefix[MAX_PREFIXES];
253
254 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 255 addressing modes of this insn are encoded. */
252b5132 256 modrm_byte rm;
3e73aa7c 257 rex_byte rex;
252b5132 258 sib_byte sib;
c0f3af97 259 vex_prefix vex;
b6169b20
L		 260
261 /* Swap operand in encoding. */
4473e004 262 unsigned int swap_operand;
252b5132
RH		 263 };
264
265typedef struct _i386_insn i386_insn;
266
267/* List of chars besides those in app.c:symbol_chars that can start an
268 operand. Used to prevent the scrubber eating vital white-space. */
32137342 269const char extra_symbol_chars[] = "*%-(["
252b5132 270#ifdef LEX_AT
32137342
NC		 271 "@"
272#endif
273#ifdef LEX_QM
274 "?"
252b5132 275#endif
32137342 276 ;
252b5132 277
29b0f896
AM		 278#if (defined (TE_I386AIX) \
279 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 280 && !defined (TE_GNU) \
29b0f896 281 && !defined (TE_LINUX) \
32137342 282 && !defined (TE_NETWARE) \
29b0f896
AM		 283 && !defined (TE_FreeBSD) \
284 && !defined (TE_NetBSD)))
252b5132 285/* This array holds the chars that always start a comment. If the
b3b91714
AM		 286 pre-processor is disabled, these aren't very useful. The option
287 --divide will remove '/' from this list. */
288const char *i386_comment_chars = "#/";
289#define SVR4_COMMENT_CHARS 1
252b5132 290#define PREFIX_SEPARATOR '\\'
252b5132 291
b3b91714
AM		 292#else
293const char *i386_comment_chars = "#";
294#define PREFIX_SEPARATOR '/'
295#endif
296
252b5132
RH		 297/* This array holds the chars that only start a comment at the beginning of
298 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 299 .line and .file directives will appear in the pre-processed output.
300 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 301 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 302 #NO_APP at the beginning of its output.
303 Also note that comments started like this one will always work if
252b5132 304 '/' isn't otherwise defined. */
b3b91714 305const char line_comment_chars[] = "#/";
252b5132 306
63a0b638 307const char line_separator_chars[] = ";";
252b5132 308
ce8a8b2f
AM		 309/* Chars that can be used to separate mant from exp in floating point
310 nums. */
252b5132
RH		 311const char EXP_CHARS[] = "eE";
312
ce8a8b2f
AM		 313/* Chars that mean this number is a floating point constant
314 As in 0f12.456
315 or 0d1.2345e12. */
252b5132
RH		 316const char FLT_CHARS[] = "fFdDxX";
317
ce8a8b2f 318/* Tables for lexical analysis. */
252b5132
RH		 319static char mnemonic_chars[256];
320static char register_chars[256];
321static char operand_chars[256];
322static char identifier_chars[256];
323static char digit_chars[256];
324
ce8a8b2f 325/* Lexical macros. */
252b5132
RH		 326#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
327#define is_operand_char(x) (operand_chars[(unsigned char) x])
328#define is_register_char(x) (register_chars[(unsigned char) x])
329#define is_space_char(x) ((x) == ' ')
330#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
331#define is_digit_char(x) (digit_chars[(unsigned char) x])
332
0234cb7c 333/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 334static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
335
336/* md_assemble() always leaves the strings it's passed unaltered. To
337 effect this we maintain a stack of saved characters that we've smashed
338 with '\0's (indicating end of strings for various sub-fields of the
47926f60 339 assembler instruction). */
252b5132 340static char save_stack[32];
ce8a8b2f 341static char *save_stack_p;
252b5132
RH		 342#define END_STRING_AND_SAVE(s) \
343 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
344#define RESTORE_END_STRING(s) \
345 do { *(s) = *--save_stack_p; } while (0)
346
47926f60 347/* The instruction we're assembling. */
252b5132
RH		 348static i386_insn i;
349
350/* Possible templates for current insn. */
351static const templates *current_templates;
352
31b2323c
L		 353/* Per instruction expressionS buffers: max displacements & immediates. */
354static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
355static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 356
47926f60 357/* Current operand we are working on. */
ee86248c 358static int this_operand = -1;
252b5132 359
3e73aa7c
JH		 360/* We support four different modes. FLAG_CODE variable is used to distinguish
361 these. */
362
363enum flag_code {
364 CODE_32BIT,
365 CODE_16BIT,
366 CODE_64BIT };
367
368static enum flag_code flag_code;
4fa24527 369static unsigned int object_64bit;
3e73aa7c
JH		 370static int use_rela_relocations = 0;
371
372/* The names used to print error messages. */
b77a7acd 373static const char *flag_code_names[] =
3e73aa7c
JH		 374 {
375 "32",
376 "16",
377 "64"
378 };
252b5132 379
47926f60
KH		 380/* 1 for intel syntax,
381 0 if att syntax. */
382static int intel_syntax = 0;
252b5132 383
1efbbeb4
L		 384/* 1 for intel mnemonic,
385 0 if att mnemonic. */
386static int intel_mnemonic = !SYSV386_COMPAT;
387
5209009a 388/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 389static int old_gcc = OLDGCC_COMPAT;
390
a60de03c
JB		 391/* 1 if pseudo registers are permitted. */
392static int allow_pseudo_reg = 0;
393
47926f60
KH		 394/* 1 if register prefix % not required. */
395static int allow_naked_reg = 0;
252b5132 396
ba104c83 397/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 398static int allow_index_reg = 0;
399
daf50ae7
L		 400static enum
401 {
402 sse_check_none = 0,
403 sse_check_warning,
404 sse_check_error
405 }
406sse_check;
407
2ca3ace5
L		 408/* Register prefix used for error message. */
409static const char *register_prefix = "%";
410
47926f60
KH		 411/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
412 leave, push, and pop instructions so that gcc has the same stack
413 frame as in 32 bit mode. */
414static char stackop_size = '\0';
eecb386c 415
12b55ccc
L		 416/* Non-zero to optimize code alignment. */
417int optimize_align_code = 1;
418
47926f60
KH		 419/* Non-zero to quieten some warnings. */
420static int quiet_warnings = 0;
a38cf1db 421
47926f60
KH		 422/* CPU name. */
423static const char *cpu_arch_name = NULL;
6305a203 424static char *cpu_sub_arch_name = NULL;
a38cf1db 425
47926f60 426/* CPU feature flags. */
40fb9820
L		 427static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
428
ccc9c027
L		 429/* If we have selected a cpu we are generating instructions for. */
430static int cpu_arch_tune_set = 0;
431
9103f4f4 432/* Cpu we are generating instructions for. */
fbf3f584 433enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 434
435/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 436static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 437
ccc9c027 438/* CPU instruction set architecture used. */
fbf3f584 439enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 440
9103f4f4 441/* CPU feature flags of instruction set architecture used. */
fbf3f584 442i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 443
fddf5b5b
AM		 444/* If set, conditional jumps are not automatically promoted to handle
445 larger than a byte offset. */
446static unsigned int no_cond_jump_promotion = 0;
447
c0f3af97
L		 448/* Encode SSE instructions with VEX prefix. */
449static unsigned int sse2avx;
450
29b0f896 451/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 452static symbolS *GOT_symbol;
29b0f896 453
a4447b93
RH		 454/* The dwarf2 return column, adjusted for 32 or 64 bit. */
455unsigned int x86_dwarf2_return_column;
456
457/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
458int x86_cie_data_alignment;
459
252b5132 460/* Interface to relax_segment.
fddf5b5b
AM		 461 There are 3 major relax states for 386 jump insns because the
462 different types of jumps add different sizes to frags when we're
463 figuring out what sort of jump to choose to reach a given label. */
252b5132 464
47926f60 465/* Types. */
93c2a809
AM		 466#define UNCOND_JUMP 0
467#define COND_JUMP 1
468#define COND_JUMP86 2
fddf5b5b 469
47926f60 470/* Sizes. */
252b5132
RH		 471#define CODE16 1
472#define SMALL 0
29b0f896 473#define SMALL16 (SMALL | CODE16)
252b5132 474#define BIG 2
29b0f896 475#define BIG16 (BIG | CODE16)
252b5132
RH		 476
477#ifndef INLINE
478#ifdef __GNUC__
479#define INLINE __inline__
480#else
481#define INLINE
482#endif
483#endif
484
fddf5b5b
AM		 485#define ENCODE_RELAX_STATE(type, size) \
486 ((relax_substateT) (((type) << 2) | (size)))
487#define TYPE_FROM_RELAX_STATE(s) \
488 ((s) >> 2)
489#define DISP_SIZE_FROM_RELAX_STATE(s) \
490 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 491
492/* This table is used by relax_frag to promote short jumps to long
493 ones where necessary. SMALL (short) jumps may be promoted to BIG
494 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
495 don't allow a short jump in a 32 bit code segment to be promoted to
496 a 16 bit offset jump because it's slower (requires data size
497 prefix), and doesn't work, unless the destination is in the bottom
498 64k of the code segment (The top 16 bits of eip are zeroed). */
499
500const relax_typeS md_relax_table[] =
501{
24eab124
AM		 502 /* The fields are:
503 1) most positive reach of this state,
504 2) most negative reach of this state,
93c2a809 505 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 506 4) which index into the table to try if we can't fit into this one. */
252b5132 507
fddf5b5b 508 /* UNCOND_JUMP states. */
93c2a809
AM		 509 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
510 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
511 /* dword jmp adds 4 bytes to frag:
512 0 extra opcode bytes, 4 displacement bytes. */
252b5132 513 {0, 0, 4, 0},
93c2a809
AM		 514 /* word jmp adds 2 byte2 to frag:
515 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 516 {0, 0, 2, 0},
517
93c2a809
AM		 518 /* COND_JUMP states. */
519 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
520 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
521 /* dword conditionals adds 5 bytes to frag:
522 1 extra opcode byte, 4 displacement bytes. */
523 {0, 0, 5, 0},
fddf5b5b 524 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 525 1 extra opcode byte, 2 displacement bytes. */
526 {0, 0, 3, 0},
527
528 /* COND_JUMP86 states. */
529 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
530 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
531 /* dword conditionals adds 5 bytes to frag:
532 1 extra opcode byte, 4 displacement bytes. */
533 {0, 0, 5, 0},
534 /* word conditionals add 4 bytes to frag:
535 1 displacement byte and a 3 byte long branch insn. */
536 {0, 0, 4, 0}
252b5132
RH		 537};
538
9103f4f4
L		 539static const arch_entry cpu_arch[] =
540{
8a2c8fef
L		 541 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
542 CPU_GENERIC32_FLAGS, 0 },
543 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
544 CPU_GENERIC64_FLAGS, 0 },
545 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
546 CPU_NONE_FLAGS, 0 },
547 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
548 CPU_I186_FLAGS, 0 },
549 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
550 CPU_I286_FLAGS, 0 },
551 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
552 CPU_I386_FLAGS, 0 },
553 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
554 CPU_I486_FLAGS, 0 },
555 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
556 CPU_I586_FLAGS, 0 },
557 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
558 CPU_I686_FLAGS, 0 },
559 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
560 CPU_I586_FLAGS, 0 },
561 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
562 CPU_I686_FLAGS, 0 },
563 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
564 CPU_P2_FLAGS, 0 },
565 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
566 CPU_P3_FLAGS, 0 },
567 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
568 CPU_P4_FLAGS, 0 },
569 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
570 CPU_CORE_FLAGS, 0 },
571 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
572 CPU_NOCONA_FLAGS, 0 },
573 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
574 CPU_CORE_FLAGS, 1 },
575 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
576 CPU_CORE_FLAGS, 0 },
577 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
578 CPU_CORE2_FLAGS, 1 },
579 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
580 CPU_CORE2_FLAGS, 0 },
581 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
582 CPU_COREI7_FLAGS, 0 },
583 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
584 CPU_L1OM_FLAGS, 0 },
585 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
586 CPU_K6_FLAGS, 0 },
587 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
588 CPU_K6_2_FLAGS, 0 },
589 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
590 CPU_ATHLON_FLAGS, 0 },
591 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
592 CPU_K8_FLAGS, 1 },
593 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
594 CPU_K8_FLAGS, 0 },
595 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
596 CPU_K8_FLAGS, 0 },
597 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
598 CPU_AMDFAM10_FLAGS, 0 },
69dd9865
SP		 599 { STRING_COMMA_LEN ("amdfam15"), PROCESSOR_AMDFAM15,
600 CPU_AMDFAM15_FLAGS, 0 },
8a2c8fef
L		 601 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
602 CPU_8087_FLAGS, 0 },
603 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
604 CPU_287_FLAGS, 0 },
605 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
606 CPU_387_FLAGS, 0 },
607 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
608 CPU_ANY87_FLAGS, 0 },
609 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
610 CPU_MMX_FLAGS, 0 },
611 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
612 CPU_3DNOWA_FLAGS, 0 },
613 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
614 CPU_SSE_FLAGS, 0 },
615 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
616 CPU_SSE2_FLAGS, 0 },
617 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
618 CPU_SSE3_FLAGS, 0 },
619 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
620 CPU_SSSE3_FLAGS, 0 },
621 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
622 CPU_SSE4_1_FLAGS, 0 },
623 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
624 CPU_SSE4_2_FLAGS, 0 },
625 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
626 CPU_SSE4_2_FLAGS, 0 },
627 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
628 CPU_ANY_SSE_FLAGS, 0 },
629 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
630 CPU_AVX_FLAGS, 0 },
631 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
632 CPU_ANY_AVX_FLAGS, 0 },
633 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
634 CPU_VMX_FLAGS, 0 },
635 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
636 CPU_SMX_FLAGS, 0 },
637 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
638 CPU_XSAVE_FLAGS, 0 },
639 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
640 CPU_AES_FLAGS, 0 },
641 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
642 CPU_PCLMUL_FLAGS, 0 },
643 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
644 CPU_PCLMUL_FLAGS, 1 },
645 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
646 CPU_FMA_FLAGS, 0 },
647 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
648 CPU_FMA4_FLAGS, 0 },
649 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
650 CPU_XOP_FLAGS, 0 },
651 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
652 CPU_LWP_FLAGS, 0 },
653 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
654 CPU_MOVBE_FLAGS, 0 },
655 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
656 CPU_EPT_FLAGS, 0 },
657 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
658 CPU_CLFLUSH_FLAGS, 0 },
659 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
660 CPU_SYSCALL_FLAGS, 0 },
661 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
662 CPU_RDTSCP_FLAGS, 0 },
663 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
664 CPU_3DNOW_FLAGS, 0 },
665 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
666 CPU_3DNOWA_FLAGS, 0 },
667 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
668 CPU_PADLOCK_FLAGS, 0 },
669 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
670 CPU_SVME_FLAGS, 1 },
671 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
672 CPU_SVME_FLAGS, 0 },
673 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
674 CPU_SSE4A_FLAGS, 0 },
675 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
676 CPU_ABM_FLAGS, 0 },
e413e4e9
AM		 677};
678
704209c0 679#ifdef I386COFF
a6c24e68
NC		 680/* Like s_lcomm_internal in gas/read.c but the alignment string
681 is allowed to be optional. */
682
683static symbolS *
684pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
685{
686 addressT align = 0;
687
688 SKIP_WHITESPACE ();
689
7ab9ffdd 690 if (needs_align
a6c24e68
NC		 691 && *input_line_pointer == ',')
692 {
693 align = parse_align (needs_align - 1);
7ab9ffdd 694
a6c24e68
NC		 695 if (align == (addressT) -1)
696 return NULL;
697 }
698 else
699 {
700 if (size >= 8)
701 align = 3;
702 else if (size >= 4)
703 align = 2;
704 else if (size >= 2)
705 align = 1;
706 else
707 align = 0;
708 }
709
710 bss_alloc (symbolP, size, align);
711 return symbolP;
712}
713
704209c0 714static void
a6c24e68
NC		 715pe_lcomm (int needs_align)
716{
717 s_comm_internal (needs_align * 2, pe_lcomm_internal);
718}
704209c0 719#endif
a6c24e68 720
29b0f896
AM		 721const pseudo_typeS md_pseudo_table[] =
722{
723#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
724 {"align", s_align_bytes, 0},
725#else
726 {"align", s_align_ptwo, 0},
727#endif
728 {"arch", set_cpu_arch, 0},
729#ifndef I386COFF
730 {"bss", s_bss, 0},
a6c24e68
NC		 731#else
732 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 733#endif
734 {"ffloat", float_cons, 'f'},
735 {"dfloat", float_cons, 'd'},
736 {"tfloat", float_cons, 'x'},
737 {"value", cons, 2},
d182319b 738 {"slong", signed_cons, 4},
29b0f896
AM		 739 {"noopt", s_ignore, 0},
740 {"optim", s_ignore, 0},
741 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
742 {"code16", set_code_flag, CODE_16BIT},
743 {"code32", set_code_flag, CODE_32BIT},
744 {"code64", set_code_flag, CODE_64BIT},
745 {"intel_syntax", set_intel_syntax, 1},
746 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 747 {"intel_mnemonic", set_intel_mnemonic, 1},
748 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 749 {"allow_index_reg", set_allow_index_reg, 1},
750 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 751 {"sse_check", set_sse_check, 0},
3b22753a
L		 752#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
753 {"largecomm", handle_large_common, 0},
07a53e5c 754#else
e3bb37b5 755 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 756 {"loc", dwarf2_directive_loc, 0},
757 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 758#endif
6482c264
NC		 759#ifdef TE_PE
760 {"secrel32", pe_directive_secrel, 0},
761#endif
29b0f896
AM		 762 {0, 0, 0}
763};
764
765/* For interface with expression (). */
766extern char *input_line_pointer;
767
768/* Hash table for instruction mnemonic lookup. */
769static struct hash_control *op_hash;
770
771/* Hash table for register lookup. */
772static struct hash_control *reg_hash;
773\f
252b5132 774void
e3bb37b5 775i386_align_code (fragS *fragP, int count)
252b5132 776{
ce8a8b2f
AM		 777 /* Various efficient no-op patterns for aligning code labels.
778 Note: Don't try to assemble the instructions in the comments.
779 0L and 0w are not legal. */
252b5132
RH		 780 static const char f32_1[] =
781 {0x90}; /* nop */
782 static const char f32_2[] =
ccc9c027 783 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 784 static const char f32_3[] =
785 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
786 static const char f32_4[] =
787 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
788 static const char f32_5[] =
789 {0x90, /* nop */
790 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
791 static const char f32_6[] =
792 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
793 static const char f32_7[] =
794 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
795 static const char f32_8[] =
796 {0x90, /* nop */
797 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
798 static const char f32_9[] =
799 {0x89,0xf6, /* movl %esi,%esi */
800 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
801 static const char f32_10[] =
802 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
803 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
804 static const char f32_11[] =
805 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
806 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
807 static const char f32_12[] =
808 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
809 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
810 static const char f32_13[] =
811 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
812 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
813 static const char f32_14[] =
814 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
815 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 816 static const char f16_3[] =
817 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 818 static const char f16_4[] =
819 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
820 static const char f16_5[] =
821 {0x90, /* nop */
822 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
823 static const char f16_6[] =
824 {0x89,0xf6, /* mov %si,%si */
825 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
826 static const char f16_7[] =
827 {0x8d,0x74,0x00, /* lea 0(%si),%si */
828 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
829 static const char f16_8[] =
830 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
831 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 832 static const char jump_31[] =
833 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
834 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
835 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
836 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 837 static const char *const f32_patt[] = {
838 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 839 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 840 };
841 static const char *const f16_patt[] = {
76bc74dc 842 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 843 };
ccc9c027
L		 844 /* nopl (%[re]ax) */
845 static const char alt_3[] =
846 {0x0f,0x1f,0x00};
847 /* nopl 0(%[re]ax) */
848 static const char alt_4[] =
849 {0x0f,0x1f,0x40,0x00};
850 /* nopl 0(%[re]ax,%[re]ax,1) */
851 static const char alt_5[] =
852 {0x0f,0x1f,0x44,0x00,0x00};
853 /* nopw 0(%[re]ax,%[re]ax,1) */
854 static const char alt_6[] =
855 {0x66,0x0f,0x1f,0x44,0x00,0x00};
856 /* nopl 0L(%[re]ax) */
857 static const char alt_7[] =
858 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
859 /* nopl 0L(%[re]ax,%[re]ax,1) */
860 static const char alt_8[] =
861 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
862 /* nopw 0L(%[re]ax,%[re]ax,1) */
863 static const char alt_9[] =
864 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
865 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
866 static const char alt_10[] =
867 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
868 /* data16
869 nopw %cs:0L(%[re]ax,%[re]ax,1) */
870 static const char alt_long_11[] =
871 {0x66,
872 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
873 /* data16
874 data16
875 nopw %cs:0L(%[re]ax,%[re]ax,1) */
876 static const char alt_long_12[] =
877 {0x66,
878 0x66,
879 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
880 /* data16
881 data16
882 data16
883 nopw %cs:0L(%[re]ax,%[re]ax,1) */
884 static const char alt_long_13[] =
885 {0x66,
886 0x66,
887 0x66,
888 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
889 /* data16
890 data16
891 data16
892 data16
893 nopw %cs:0L(%[re]ax,%[re]ax,1) */
894 static const char alt_long_14[] =
895 {0x66,
896 0x66,
897 0x66,
898 0x66,
899 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
900 /* data16
901 data16
902 data16
903 data16
904 data16
905 nopw %cs:0L(%[re]ax,%[re]ax,1) */
906 static const char alt_long_15[] =
907 {0x66,
908 0x66,
909 0x66,
910 0x66,
911 0x66,
912 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
913 /* nopl 0(%[re]ax,%[re]ax,1)
914 nopw 0(%[re]ax,%[re]ax,1) */
915 static const char alt_short_11[] =
916 {0x0f,0x1f,0x44,0x00,0x00,
917 0x66,0x0f,0x1f,0x44,0x00,0x00};
918 /* nopw 0(%[re]ax,%[re]ax,1)
919 nopw 0(%[re]ax,%[re]ax,1) */
920 static const char alt_short_12[] =
921 {0x66,0x0f,0x1f,0x44,0x00,0x00,
922 0x66,0x0f,0x1f,0x44,0x00,0x00};
923 /* nopw 0(%[re]ax,%[re]ax,1)
924 nopl 0L(%[re]ax) */
925 static const char alt_short_13[] =
926 {0x66,0x0f,0x1f,0x44,0x00,0x00,
927 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
928 /* nopl 0L(%[re]ax)
929 nopl 0L(%[re]ax) */
930 static const char alt_short_14[] =
931 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
932 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
933 /* nopl 0L(%[re]ax)
934 nopl 0L(%[re]ax,%[re]ax,1) */
935 static const char alt_short_15[] =
936 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
937 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
938 static const char *const alt_short_patt[] = {
939 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
940 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
941 alt_short_14, alt_short_15
942 };
943 static const char *const alt_long_patt[] = {
944 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
945 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
946 alt_long_14, alt_long_15
947 };
252b5132 948
76bc74dc
L		 949 /* Only align for at least a positive non-zero boundary. */
950 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 951 return;
3e73aa7c 952
ccc9c027
L		 953 /* We need to decide which NOP sequence to use for 32bit and
954 64bit. When -mtune= is used:
4eed87de 955
76bc74dc
L		 956 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
957 PROCESSOR_GENERIC32, f32_patt will be used.
958 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 959 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
960 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 961 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
69dd9865
SP		 962 PROCESSOR_AMDFAM10, and PROCESSOR_AMDFAM15, alt_short_patt
963 will be used.
ccc9c027 964
76bc74dc
L		 965 When -mtune= isn't used, alt_long_patt will be used if
966 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
967 be used.
ccc9c027
L		 968
969 When -march= or .arch is used, we can't use anything beyond
970 cpu_arch_isa_flags. */
971
972 if (flag_code == CODE_16BIT)
973 {
ccc9c027 974 if (count > 8)
33fef721 975 {
76bc74dc
L		 976 memcpy (fragP->fr_literal + fragP->fr_fix,
977 jump_31, count);
978 /* Adjust jump offset. */
979 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 980 }
76bc74dc
L		 981 else
982 memcpy (fragP->fr_literal + fragP->fr_fix,
983 f16_patt[count - 1], count);
252b5132 984 }
33fef721 985 else
ccc9c027
L		 986 {
987 const char *const *patt = NULL;
988
fbf3f584 989 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 990 {
991 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
992 switch (cpu_arch_tune)
993 {
994 case PROCESSOR_UNKNOWN:
995 /* We use cpu_arch_isa_flags to check if we SHOULD
996 optimize for Cpu686. */
fbf3f584 997 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
76bc74dc 998 patt = alt_long_patt;
ccc9c027
L		 999 else
1000 patt = f32_patt;
1001 break;
ccc9c027
L		 1002 case PROCESSOR_PENTIUMPRO:
1003 case PROCESSOR_PENTIUM4:
1004 case PROCESSOR_NOCONA:
ef05d495 1005 case PROCESSOR_CORE:
76bc74dc 1006 case PROCESSOR_CORE2:
bd5295b2 1007 case PROCESSOR_COREI7:
3632d14b 1008 case PROCESSOR_L1OM:
76bc74dc
L		 1009 case PROCESSOR_GENERIC64:
1010 patt = alt_long_patt;
1011 break;
ccc9c027
L		 1012 case PROCESSOR_K6:
1013 case PROCESSOR_ATHLON:
1014 case PROCESSOR_K8:
4eed87de 1015 case PROCESSOR_AMDFAM10:
69dd9865 1016 case PROCESSOR_AMDFAM15:
ccc9c027
L		 1017 patt = alt_short_patt;
1018 break;
76bc74dc 1019 case PROCESSOR_I386:
ccc9c027
L		 1020 case PROCESSOR_I486:
1021 case PROCESSOR_PENTIUM:
1022 case PROCESSOR_GENERIC32:
1023 patt = f32_patt;
1024 break;
4eed87de 1025 }
ccc9c027
L		 1026 }
1027 else
1028 {
fbf3f584 1029 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1030 {
1031 case PROCESSOR_UNKNOWN:
e6a14101 1032 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1033 PROCESSOR_UNKNOWN. */
1034 abort ();
1035 break;
1036
76bc74dc 1037 case PROCESSOR_I386:
ccc9c027
L		 1038 case PROCESSOR_I486:
1039 case PROCESSOR_PENTIUM:
ccc9c027
L		 1040 case PROCESSOR_K6:
1041 case PROCESSOR_ATHLON:
1042 case PROCESSOR_K8:
4eed87de 1043 case PROCESSOR_AMDFAM10:
69dd9865 1044 case PROCESSOR_AMDFAM15:
ccc9c027
L		 1045 case PROCESSOR_GENERIC32:
1046 /* We use cpu_arch_isa_flags to check if we CAN optimize
1047 for Cpu686. */
fbf3f584 1048 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1049 patt = alt_short_patt;
1050 else
1051 patt = f32_patt;
1052 break;
76bc74dc
L		 1053 case PROCESSOR_PENTIUMPRO:
1054 case PROCESSOR_PENTIUM4:
1055 case PROCESSOR_NOCONA:
1056 case PROCESSOR_CORE:
ef05d495 1057 case PROCESSOR_CORE2:
bd5295b2 1058 case PROCESSOR_COREI7:
3632d14b 1059 case PROCESSOR_L1OM:
fbf3f584 1060 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1061 patt = alt_long_patt;
1062 else
1063 patt = f32_patt;
1064 break;
1065 case PROCESSOR_GENERIC64:
76bc74dc 1066 patt = alt_long_patt;
ccc9c027 1067 break;
4eed87de 1068 }
ccc9c027
L		 1069 }
1070
76bc74dc
L		 1071 if (patt == f32_patt)
1072 {
1073 /* If the padding is less than 15 bytes, we use the normal
1074 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1075 its offset. */
1076 int limit;
76ba9986 1077
711eedef
L		 1078 /* For 64bit, the limit is 3 bytes. */
1079 if (flag_code == CODE_64BIT
1080 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1081 limit = 3;
1082 else
1083 limit = 15;
1084 if (count < limit)
76bc74dc
L		 1085 memcpy (fragP->fr_literal + fragP->fr_fix,
1086 patt[count - 1], count);
1087 else
1088 {
1089 memcpy (fragP->fr_literal + fragP->fr_fix,
1090 jump_31, count);
1091 /* Adjust jump offset. */
1092 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1093 }
1094 }
1095 else
1096 {
1097 /* Maximum length of an instruction is 15 byte. If the
1098 padding is greater than 15 bytes and we don't use jump,
1099 we have to break it into smaller pieces. */
1100 int padding = count;
1101 while (padding > 15)
1102 {
1103 padding -= 15;
1104 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1105 patt [14], 15);
1106 }
1107
1108 if (padding)
1109 memcpy (fragP->fr_literal + fragP->fr_fix,
1110 patt [padding - 1], padding);
1111 }
ccc9c027 1112 }
33fef721 1113 fragP->fr_var = count;
252b5132
RH		 1114}
1115
c6fb90c8 1116static INLINE int
0dfbf9d7 1117operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1118{
0dfbf9d7 1119 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1120 {
1121 case 3:
0dfbf9d7 1122 if (x->array[2])
c6fb90c8
L		 1123 return 0;
1124 case 2:
0dfbf9d7 1125 if (x->array[1])
c6fb90c8
L		 1126 return 0;
1127 case 1:
0dfbf9d7 1128 return !x->array[0];
c6fb90c8
L		 1129 default:
1130 abort ();
1131 }
40fb9820
L		 1132}
1133
c6fb90c8 1134static INLINE void
0dfbf9d7 1135operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1136{
0dfbf9d7 1137 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1138 {
1139 case 3:
0dfbf9d7 1140 x->array[2] = v;
c6fb90c8 1141 case 2:
0dfbf9d7 1142 x->array[1] = v;
c6fb90c8 1143 case 1:
0dfbf9d7 1144 x->array[0] = v;
c6fb90c8
L		 1145 break;
1146 default:
1147 abort ();
1148 }
1149}
40fb9820 1150
c6fb90c8 1151static INLINE int
0dfbf9d7
L		 1152operand_type_equal (const union i386_operand_type *x,
1153 const union i386_operand_type *y)
c6fb90c8 1154{
0dfbf9d7 1155 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1156 {
1157 case 3:
0dfbf9d7 1158 if (x->array[2] != y->array[2])
c6fb90c8
L		 1159 return 0;
1160 case 2:
0dfbf9d7 1161 if (x->array[1] != y->array[1])
c6fb90c8
L		 1162 return 0;
1163 case 1:
0dfbf9d7 1164 return x->array[0] == y->array[0];
c6fb90c8
L		 1165 break;
1166 default:
1167 abort ();
1168 }
1169}
40fb9820 1170
0dfbf9d7
L		 1171static INLINE int
1172cpu_flags_all_zero (const union i386_cpu_flags *x)
1173{
1174 switch (ARRAY_SIZE(x->array))
1175 {
1176 case 3:
1177 if (x->array[2])
1178 return 0;
1179 case 2:
1180 if (x->array[1])
1181 return 0;
1182 case 1:
1183 return !x->array[0];
1184 default:
1185 abort ();
1186 }
1187}
1188
1189static INLINE void
1190cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1191{
1192 switch (ARRAY_SIZE(x->array))
1193 {
1194 case 3:
1195 x->array[2] = v;
1196 case 2:
1197 x->array[1] = v;
1198 case 1:
1199 x->array[0] = v;
1200 break;
1201 default:
1202 abort ();
1203 }
1204}
1205
1206static INLINE int
1207cpu_flags_equal (const union i386_cpu_flags *x,
1208 const union i386_cpu_flags *y)
1209{
1210 switch (ARRAY_SIZE(x->array))
1211 {
1212 case 3:
1213 if (x->array[2] != y->array[2])
1214 return 0;
1215 case 2:
1216 if (x->array[1] != y->array[1])
1217 return 0;
1218 case 1:
1219 return x->array[0] == y->array[0];
1220 break;
1221 default:
1222 abort ();
1223 }
1224}
c6fb90c8
L		 1225
1226static INLINE int
1227cpu_flags_check_cpu64 (i386_cpu_flags f)
1228{
1229 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1230 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1231}
1232
c6fb90c8
L		 1233static INLINE i386_cpu_flags
1234cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1235{
c6fb90c8
L		 1236 switch (ARRAY_SIZE (x.array))
1237 {
1238 case 3:
1239 x.array [2] &= y.array [2];
1240 case 2:
1241 x.array [1] &= y.array [1];
1242 case 1:
1243 x.array [0] &= y.array [0];
1244 break;
1245 default:
1246 abort ();
1247 }
1248 return x;
1249}
40fb9820 1250
c6fb90c8
L		 1251static INLINE i386_cpu_flags
1252cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1253{
c6fb90c8 1254 switch (ARRAY_SIZE (x.array))
40fb9820 1255 {
c6fb90c8
L		 1256 case 3:
1257 x.array [2] |= y.array [2];
1258 case 2:
1259 x.array [1] |= y.array [1];
1260 case 1:
1261 x.array [0] |= y.array [0];
40fb9820
L		 1262 break;
1263 default:
1264 abort ();
1265 }
40fb9820
L		 1266 return x;
1267}
1268
309d3373
JB		 1269static INLINE i386_cpu_flags
1270cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1271{
1272 switch (ARRAY_SIZE (x.array))
1273 {
1274 case 3:
1275 x.array [2] &= ~y.array [2];
1276 case 2:
1277 x.array [1] &= ~y.array [1];
1278 case 1:
1279 x.array [0] &= ~y.array [0];
1280 break;
1281 default:
1282 abort ();
1283 }
1284 return x;
1285}
1286
c0f3af97
L		 1287#define CPU_FLAGS_ARCH_MATCH 0x1
1288#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1289#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1290#define CPU_FLAGS_PCLMUL_MATCH 0x8
1291#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1292
a5ff0eb2 1293#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1294 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1295 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1296#define CPU_FLAGS_PERFECT_MATCH \
1297 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1298
1299/* Return CPU flags match bits. */
3629bb00 1300
40fb9820 1301static int
d3ce72d0 1302cpu_flags_match (const insn_template *t)
40fb9820 1303{
c0f3af97
L		 1304 i386_cpu_flags x = t->cpu_flags;
1305 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1306
1307 x.bitfield.cpu64 = 0;
1308 x.bitfield.cpuno64 = 0;
1309
0dfbf9d7 1310 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1311 {
1312 /* This instruction is available on all archs. */
1313 match |= CPU_FLAGS_32BIT_MATCH;
1314 }
3629bb00
L		 1315 else
1316 {
c0f3af97 1317 /* This instruction is available only on some archs. */
3629bb00
L		 1318 i386_cpu_flags cpu = cpu_arch_flags;
1319
1320 cpu.bitfield.cpu64 = 0;
1321 cpu.bitfield.cpuno64 = 0;
1322 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1323 if (!cpu_flags_all_zero (&cpu))
1324 {
a5ff0eb2
L		 1325 if (x.bitfield.cpuavx)
1326 {
ce2f5b3c 1327 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1328 if (cpu.bitfield.cpuavx)
1329 {
1330 /* Check SSE2AVX. */
1331 if (!t->opcode_modifier.sse2avx|| sse2avx)
1332 {
1333 match |= (CPU_FLAGS_ARCH_MATCH
1334 | CPU_FLAGS_AVX_MATCH);
1335 /* Check AES. */
1336 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1337 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1338 /* Check PCLMUL. */
1339 if (!x.bitfield.cpupclmul
1340 || cpu.bitfield.cpupclmul)
1341 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1342 }
1343 }
1344 else
1345 match |= CPU_FLAGS_ARCH_MATCH;
1346 }
1347 else
c0f3af97
L		 1348 match |= CPU_FLAGS_32BIT_MATCH;
1349 }
3629bb00 1350 }
c0f3af97 1351 return match;
40fb9820
L		 1352}
1353
c6fb90c8
L		 1354static INLINE i386_operand_type
1355operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1356{
c6fb90c8
L		 1357 switch (ARRAY_SIZE (x.array))
1358 {
1359 case 3:
1360 x.array [2] &= y.array [2];
1361 case 2:
1362 x.array [1] &= y.array [1];
1363 case 1:
1364 x.array [0] &= y.array [0];
1365 break;
1366 default:
1367 abort ();
1368 }
1369 return x;
40fb9820
L		 1370}
1371
c6fb90c8
L		 1372static INLINE i386_operand_type
1373operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1374{
c6fb90c8 1375 switch (ARRAY_SIZE (x.array))
40fb9820 1376 {
c6fb90c8
L		 1377 case 3:
1378 x.array [2] |= y.array [2];
1379 case 2:
1380 x.array [1] |= y.array [1];
1381 case 1:
1382 x.array [0] |= y.array [0];
40fb9820
L		 1383 break;
1384 default:
1385 abort ();
1386 }
c6fb90c8
L		 1387 return x;
1388}
40fb9820 1389
c6fb90c8
L		 1390static INLINE i386_operand_type
1391operand_type_xor (i386_operand_type x, i386_operand_type y)
1392{
1393 switch (ARRAY_SIZE (x.array))
1394 {
1395 case 3:
1396 x.array [2] ^= y.array [2];
1397 case 2:
1398 x.array [1] ^= y.array [1];
1399 case 1:
1400 x.array [0] ^= y.array [0];
1401 break;
1402 default:
1403 abort ();
1404 }
40fb9820
L		 1405 return x;
1406}
1407
1408static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1409static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1410static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1411static const i386_operand_type inoutportreg
1412 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1413static const i386_operand_type reg16_inoutportreg
1414 = OPERAND_TYPE_REG16_INOUTPORTREG;
1415static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1416static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1417static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1418static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1419static const i386_operand_type anydisp
1420 = OPERAND_TYPE_ANYDISP;
40fb9820 1421static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1422static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1423static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1424static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1425static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1426static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1427static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1428static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1429static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1430static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1431static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1432
1433enum operand_type
1434{
1435 reg,
40fb9820
L		 1436 imm,
1437 disp,
1438 anymem
1439};
1440
c6fb90c8 1441static INLINE int
40fb9820
L		 1442operand_type_check (i386_operand_type t, enum operand_type c)
1443{
1444 switch (c)
1445 {
1446 case reg:
1447 return (t.bitfield.reg8
1448 || t.bitfield.reg16
1449 || t.bitfield.reg32
1450 || t.bitfield.reg64);
1451
40fb9820
L		 1452 case imm:
1453 return (t.bitfield.imm8
1454 || t.bitfield.imm8s
1455 || t.bitfield.imm16
1456 || t.bitfield.imm32
1457 || t.bitfield.imm32s
1458 || t.bitfield.imm64);
1459
1460 case disp:
1461 return (t.bitfield.disp8
1462 || t.bitfield.disp16
1463 || t.bitfield.disp32
1464 || t.bitfield.disp32s
1465 || t.bitfield.disp64);
1466
1467 case anymem:
1468 return (t.bitfield.disp8
1469 || t.bitfield.disp16
1470 || t.bitfield.disp32
1471 || t.bitfield.disp32s
1472 || t.bitfield.disp64
1473 || t.bitfield.baseindex);
1474
1475 default:
1476 abort ();
1477 }
2cfe26b6
AM		 1478
1479 return 0;
40fb9820
L		 1480}
1481
5c07affc
L		 1482/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1483 operand J for instruction template T. */
1484
1485static INLINE int
d3ce72d0 1486match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1487{
1488 return !((i.types[j].bitfield.byte
1489 && !t->operand_types[j].bitfield.byte)
1490 || (i.types[j].bitfield.word
1491 && !t->operand_types[j].bitfield.word)
1492 || (i.types[j].bitfield.dword
1493 && !t->operand_types[j].bitfield.dword)
1494 || (i.types[j].bitfield.qword
1495 && !t->operand_types[j].bitfield.qword));
1496}
1497
1498/* Return 1 if there is no conflict in any size on operand J for
1499 instruction template T. */
1500
1501static INLINE int
d3ce72d0 1502match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1503{
1504 return (match_reg_size (t, j)
1505 && !((i.types[j].bitfield.unspecified
1506 && !t->operand_types[j].bitfield.unspecified)
1507 || (i.types[j].bitfield.fword
1508 && !t->operand_types[j].bitfield.fword)
1509 || (i.types[j].bitfield.tbyte
1510 && !t->operand_types[j].bitfield.tbyte)
1511 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1512 && !t->operand_types[j].bitfield.xmmword)
1513 || (i.types[j].bitfield.ymmword
1514 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1515}
1516
1517/* Return 1 if there is no size conflict on any operands for
1518 instruction template T. */
1519
1520static INLINE int
d3ce72d0 1521operand_size_match (const insn_template *t)
5c07affc
L		 1522{
1523 unsigned int j;
1524 int match = 1;
1525
1526 /* Don't check jump instructions. */
1527 if (t->opcode_modifier.jump
1528 || t->opcode_modifier.jumpbyte
1529 || t->opcode_modifier.jumpdword
1530 || t->opcode_modifier.jumpintersegment)
1531 return match;
1532
1533 /* Check memory and accumulator operand size. */
1534 for (j = 0; j < i.operands; j++)
1535 {
1536 if (t->operand_types[j].bitfield.anysize)
1537 continue;
1538
1539 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1540 {
1541 match = 0;
1542 break;
1543 }
1544
1545 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1546 {
1547 match = 0;
1548 break;
1549 }
1550 }
1551
1552 if (match
1553 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1554 return match;
1555
1556 /* Check reverse. */
9c2799c2 1557 gas_assert (i.operands == 2);
5c07affc
L		 1558
1559 match = 1;
1560 for (j = 0; j < 2; j++)
1561 {
1562 if (t->operand_types[j].bitfield.acc
1563 && !match_reg_size (t, j ? 0 : 1))
1564 {
1565 match = 0;
1566 break;
1567 }
1568
1569 if (i.types[j].bitfield.mem
1570 && !match_mem_size (t, j ? 0 : 1))
1571 {
1572 match = 0;
1573 break;
1574 }
1575 }
1576
1577 return match;
1578}
1579
c6fb90c8 1580static INLINE int
40fb9820
L		 1581operand_type_match (i386_operand_type overlap,
1582 i386_operand_type given)
1583{
1584 i386_operand_type temp = overlap;
1585
1586 temp.bitfield.jumpabsolute = 0;
7d5e4556 1587 temp.bitfield.unspecified = 0;
5c07affc
L		 1588 temp.bitfield.byte = 0;
1589 temp.bitfield.word = 0;
1590 temp.bitfield.dword = 0;
1591 temp.bitfield.fword = 0;
1592 temp.bitfield.qword = 0;
1593 temp.bitfield.tbyte = 0;
1594 temp.bitfield.xmmword = 0;
c0f3af97 1595 temp.bitfield.ymmword = 0;
0dfbf9d7 1596 if (operand_type_all_zero (&temp))
40fb9820
L		 1597 return 0;
1598
1599 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1600 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1601}
1602
7d5e4556 1603/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1604 unless the expected operand type register overlap is null.
1605 Note that Acc in a template matches every size of reg. */
1606
c6fb90c8 1607static INLINE int
40fb9820
L		 1608operand_type_register_match (i386_operand_type m0,
1609 i386_operand_type g0,
1610 i386_operand_type t0,
1611 i386_operand_type m1,
1612 i386_operand_type g1,
1613 i386_operand_type t1)
1614{
1615 if (!operand_type_check (g0, reg))
1616 return 1;
1617
1618 if (!operand_type_check (g1, reg))
1619 return 1;
1620
1621 if (g0.bitfield.reg8 == g1.bitfield.reg8
1622 && g0.bitfield.reg16 == g1.bitfield.reg16
1623 && g0.bitfield.reg32 == g1.bitfield.reg32
1624 && g0.bitfield.reg64 == g1.bitfield.reg64)
1625 return 1;
1626
1627 if (m0.bitfield.acc)
1628 {
1629 t0.bitfield.reg8 = 1;
1630 t0.bitfield.reg16 = 1;
1631 t0.bitfield.reg32 = 1;
1632 t0.bitfield.reg64 = 1;
1633 }
1634
1635 if (m1.bitfield.acc)
1636 {
1637 t1.bitfield.reg8 = 1;
1638 t1.bitfield.reg16 = 1;
1639 t1.bitfield.reg32 = 1;
1640 t1.bitfield.reg64 = 1;
1641 }
1642
1643 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1644 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1645 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1646 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1647}
1648
252b5132 1649static INLINE unsigned int
40fb9820 1650mode_from_disp_size (i386_operand_type t)
252b5132 1651{
40fb9820
L		 1652 if (t.bitfield.disp8)
1653 return 1;
1654 else if (t.bitfield.disp16
1655 || t.bitfield.disp32
1656 || t.bitfield.disp32s)
1657 return 2;
1658 else
1659 return 0;
252b5132
RH		 1660}
1661
1662static INLINE int
e3bb37b5 1663fits_in_signed_byte (offsetT num)
252b5132
RH		 1664{
1665 return (num >= -128) && (num <= 127);
47926f60 1666}
252b5132
RH		 1667
1668static INLINE int
e3bb37b5 1669fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1670{
1671 return (num & 0xff) == num;
47926f60 1672}
252b5132
RH		 1673
1674static INLINE int
e3bb37b5 1675fits_in_unsigned_word (offsetT num)
252b5132
RH		 1676{
1677 return (num & 0xffff) == num;
47926f60 1678}
252b5132
RH		 1679
1680static INLINE int
e3bb37b5 1681fits_in_signed_word (offsetT num)
252b5132
RH		 1682{
1683 return (-32768 <= num) && (num <= 32767);
47926f60 1684}
2a962e6d 1685
3e73aa7c 1686static INLINE int
e3bb37b5 1687fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1688{
1689#ifndef BFD64
1690 return 1;
1691#else
1692 return (!(((offsetT) -1 << 31) & num)
1693 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1694#endif
1695} /* fits_in_signed_long() */
2a962e6d 1696
3e73aa7c 1697static INLINE int
e3bb37b5 1698fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1699{
1700#ifndef BFD64
1701 return 1;
1702#else
1703 return (num & (((offsetT) 2 << 31) - 1)) == num;
1704#endif
1705} /* fits_in_unsigned_long() */
252b5132 1706
40fb9820 1707static i386_operand_type
e3bb37b5 1708smallest_imm_type (offsetT num)
252b5132 1709{
40fb9820 1710 i386_operand_type t;
7ab9ffdd 1711
0dfbf9d7 1712 operand_type_set (&t, 0);
40fb9820
L		 1713 t.bitfield.imm64 = 1;
1714
1715 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1716 {
1717 /* This code is disabled on the 486 because all the Imm1 forms
1718 in the opcode table are slower on the i486. They're the
1719 versions with the implicitly specified single-position
1720 displacement, which has another syntax if you really want to
1721 use that form. */
40fb9820
L		 1722 t.bitfield.imm1 = 1;
1723 t.bitfield.imm8 = 1;
1724 t.bitfield.imm8s = 1;
1725 t.bitfield.imm16 = 1;
1726 t.bitfield.imm32 = 1;
1727 t.bitfield.imm32s = 1;
1728 }
1729 else if (fits_in_signed_byte (num))
1730 {
1731 t.bitfield.imm8 = 1;
1732 t.bitfield.imm8s = 1;
1733 t.bitfield.imm16 = 1;
1734 t.bitfield.imm32 = 1;
1735 t.bitfield.imm32s = 1;
1736 }
1737 else if (fits_in_unsigned_byte (num))
1738 {
1739 t.bitfield.imm8 = 1;
1740 t.bitfield.imm16 = 1;
1741 t.bitfield.imm32 = 1;
1742 t.bitfield.imm32s = 1;
1743 }
1744 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1745 {
1746 t.bitfield.imm16 = 1;
1747 t.bitfield.imm32 = 1;
1748 t.bitfield.imm32s = 1;
1749 }
1750 else if (fits_in_signed_long (num))
1751 {
1752 t.bitfield.imm32 = 1;
1753 t.bitfield.imm32s = 1;
1754 }
1755 else if (fits_in_unsigned_long (num))
1756 t.bitfield.imm32 = 1;
1757
1758 return t;
47926f60 1759}
252b5132 1760
847f7ad4 1761static offsetT
e3bb37b5 1762offset_in_range (offsetT val, int size)
847f7ad4 1763{
508866be 1764 addressT mask;
ba2adb93 1765
847f7ad4
AM		 1766 switch (size)
1767 {
508866be
L		 1768 case 1: mask = ((addressT) 1 << 8) - 1; break;
1769 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1770 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1771#ifdef BFD64
1772 case 8: mask = ((addressT) 2 << 63) - 1; break;
1773#endif
47926f60 1774 default: abort ();
847f7ad4
AM		 1775 }
1776
9de868bf
L		 1777#ifdef BFD64
1778 /* If BFD64, sign extend val for 32bit address mode. */
1779 if (flag_code != CODE_64BIT
1780 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1781 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1782 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1783#endif
ba2adb93 1784
47926f60 1785 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1786 {
1787 char buf1[40], buf2[40];
1788
1789 sprint_value (buf1, val);
1790 sprint_value (buf2, val & mask);
1791 as_warn (_("%s shortened to %s"), buf1, buf2);
1792 }
1793 return val & mask;
1794}
1795
c32fa91d
L		 1796enum PREFIX_GROUP
1797{
1798 PREFIX_EXIST = 0,
1799 PREFIX_LOCK,
1800 PREFIX_REP,
1801 PREFIX_OTHER
1802};
1803
1804/* Returns
1805 a. PREFIX_EXIST if attempting to add a prefix where one from the
1806 same class already exists.
1807 b. PREFIX_LOCK if lock prefix is added.
1808 c. PREFIX_REP if rep/repne prefix is added.
1809 d. PREFIX_OTHER if other prefix is added.
1810 */
1811
1812static enum PREFIX_GROUP
e3bb37b5 1813add_prefix (unsigned int prefix)
252b5132 1814{
c32fa91d 1815 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1816 unsigned int q;
252b5132 1817
29b0f896
AM		 1818 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1819 && flag_code == CODE_64BIT)
b1905489 1820 {
161a04f6
L		 1821 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1822 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1823 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1824 ret = PREFIX_EXIST;
b1905489
JB		 1825 q = REX_PREFIX;
1826 }
3e73aa7c 1827 else
b1905489
JB		 1828 {
1829 switch (prefix)
1830 {
1831 default:
1832 abort ();
1833
1834 case CS_PREFIX_OPCODE:
1835 case DS_PREFIX_OPCODE:
1836 case ES_PREFIX_OPCODE:
1837 case FS_PREFIX_OPCODE:
1838 case GS_PREFIX_OPCODE:
1839 case SS_PREFIX_OPCODE:
1840 q = SEG_PREFIX;
1841 break;
1842
1843 case REPNE_PREFIX_OPCODE:
1844 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1845 q = REP_PREFIX;
1846 ret = PREFIX_REP;
1847 break;
1848
b1905489 1849 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1850 q = LOCK_PREFIX;
1851 ret = PREFIX_LOCK;
b1905489
JB		 1852 break;
1853
1854 case FWAIT_OPCODE:
1855 q = WAIT_PREFIX;
1856 break;
1857
1858 case ADDR_PREFIX_OPCODE:
1859 q = ADDR_PREFIX;
1860 break;
1861
1862 case DATA_PREFIX_OPCODE:
1863 q = DATA_PREFIX;
1864 break;
1865 }
1866 if (i.prefix[q] != 0)
c32fa91d 1867 ret = PREFIX_EXIST;
b1905489 1868 }
252b5132 1869
b1905489 1870 if (ret)
252b5132 1871 {
b1905489
JB		 1872 if (!i.prefix[q])
1873 ++i.prefixes;
1874 i.prefix[q] |= prefix;
252b5132 1875 }
b1905489
JB		 1876 else
1877 as_bad (_("same type of prefix used twice"));
252b5132 1878
252b5132
RH		 1879 return ret;
1880}
1881
1882static void
e3bb37b5 1883set_code_flag (int value)
eecb386c 1884{
1e9cc1c2 1885 flag_code = (enum flag_code) value;
40fb9820
L		 1886 if (flag_code == CODE_64BIT)
1887 {
1888 cpu_arch_flags.bitfield.cpu64 = 1;
1889 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1890 }
1891 else
1892 {
1893 cpu_arch_flags.bitfield.cpu64 = 0;
1894 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1895 }
1896 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1897 {
1898 as_bad (_("64bit mode not supported on this CPU."));
1899 }
40fb9820 1900 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1901 {
1902 as_bad (_("32bit mode not supported on this CPU."));
1903 }
eecb386c
AM		 1904 stackop_size = '\0';
1905}
1906
1907static void
e3bb37b5 1908set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1909{
1e9cc1c2 1910 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 1911 if (flag_code != CODE_16BIT)
1912 abort ();
1913 cpu_arch_flags.bitfield.cpu64 = 0;
1914 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1915 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1916}
1917
1918static void
e3bb37b5 1919set_intel_syntax (int syntax_flag)
252b5132
RH		 1920{
1921 /* Find out if register prefixing is specified. */
1922 int ask_naked_reg = 0;
1923
1924 SKIP_WHITESPACE ();
29b0f896 1925 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1926 {
1927 char *string = input_line_pointer;
1928 int e = get_symbol_end ();
1929
47926f60 1930 if (strcmp (string, "prefix") == 0)
252b5132 1931 ask_naked_reg = 1;
47926f60 1932 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1933 ask_naked_reg = -1;
1934 else
d0b47220 1935 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1936 *input_line_pointer = e;
1937 }
1938 demand_empty_rest_of_line ();
c3332e24 1939
252b5132
RH		 1940 intel_syntax = syntax_flag;
1941
1942 if (ask_naked_reg == 0)
f86103b7
AM		 1943 allow_naked_reg = (intel_syntax
1944 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1945 else
1946 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1947
ee86248c 1948 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 1949
e4a3b5a4 1950 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1951 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1952 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1953}
1954
1efbbeb4
L		 1955static void
1956set_intel_mnemonic (int mnemonic_flag)
1957{
e1d4d893 1958 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1959}
1960
db51cc60
L		 1961static void
1962set_allow_index_reg (int flag)
1963{
1964 allow_index_reg = flag;
1965}
1966
cb19c032
L		 1967static void
1968set_sse_check (int dummy ATTRIBUTE_UNUSED)
1969{
1970 SKIP_WHITESPACE ();
1971
1972 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1973 {
1974 char *string = input_line_pointer;
1975 int e = get_symbol_end ();
1976
1977 if (strcmp (string, "none") == 0)
1978 sse_check = sse_check_none;
1979 else if (strcmp (string, "warning") == 0)
1980 sse_check = sse_check_warning;
1981 else if (strcmp (string, "error") == 0)
1982 sse_check = sse_check_error;
1983 else
1984 as_bad (_("bad argument to sse_check directive."));
1985 *input_line_pointer = e;
1986 }
1987 else
1988 as_bad (_("missing argument for sse_check directive"));
1989
1990 demand_empty_rest_of_line ();
1991}
1992
8a9036a4
L		 1993static void
1994check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 1995 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 1996{
1997#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1998 static const char *arch;
1999
2000 /* Intel LIOM is only supported on ELF. */
2001 if (!IS_ELF)
2002 return;
2003
2004 if (!arch)
2005 {
2006 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2007 use default_arch. */
2008 arch = cpu_arch_name;
2009 if (!arch)
2010 arch = default_arch;
2011 }
2012
3632d14b 2013 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2014 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2015 || new_flag.bitfield.cpul1om)
8a9036a4 2016 return;
76ba9986 2017
8a9036a4
L		 2018 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2019#endif
2020}
2021
e413e4e9 2022static void
e3bb37b5 2023set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2024{
47926f60 2025 SKIP_WHITESPACE ();
e413e4e9 2026
29b0f896 2027 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2028 {
2029 char *string = input_line_pointer;
2030 int e = get_symbol_end ();
91d6fa6a 2031 unsigned int j;
40fb9820 2032 i386_cpu_flags flags;
e413e4e9 2033
91d6fa6a 2034 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2035 {
91d6fa6a 2036 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2037 {
91d6fa6a 2038 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2039
5c6af06e
JB		 2040 if (*string != '.')
2041 {
91d6fa6a 2042 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2043 cpu_sub_arch_name = NULL;
91d6fa6a 2044 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2045 if (flag_code == CODE_64BIT)
2046 {
2047 cpu_arch_flags.bitfield.cpu64 = 1;
2048 cpu_arch_flags.bitfield.cpuno64 = 0;
2049 }
2050 else
2051 {
2052 cpu_arch_flags.bitfield.cpu64 = 0;
2053 cpu_arch_flags.bitfield.cpuno64 = 1;
2054 }
91d6fa6a
NC		 2055 cpu_arch_isa = cpu_arch[j].type;
2056 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2057 if (!cpu_arch_tune_set)
2058 {
2059 cpu_arch_tune = cpu_arch_isa;
2060 cpu_arch_tune_flags = cpu_arch_isa_flags;
2061 }
5c6af06e
JB		 2062 break;
2063 }
40fb9820 2064
309d3373
JB		 2065 if (strncmp (string + 1, "no", 2))
2066 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2067 cpu_arch[j].flags);
309d3373
JB		 2068 else
2069 flags = cpu_flags_and_not (cpu_arch_flags,
91d6fa6a 2070 cpu_arch[j].flags);
0dfbf9d7 2071 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2072 {
6305a203
L		 2073 if (cpu_sub_arch_name)
2074 {
2075 char *name = cpu_sub_arch_name;
2076 cpu_sub_arch_name = concat (name,
91d6fa6a 2077 cpu_arch[j].name,
1bf57e9f 2078 (const char *) NULL);
6305a203
L		 2079 free (name);
2080 }
2081 else
91d6fa6a 2082 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2083 cpu_arch_flags = flags;
5c6af06e
JB		 2084 }
2085 *input_line_pointer = e;
2086 demand_empty_rest_of_line ();
2087 return;
e413e4e9
AM		 2088 }
2089 }
91d6fa6a 2090 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2091 as_bad (_("no such architecture: `%s'"), string);
2092
2093 *input_line_pointer = e;
2094 }
2095 else
2096 as_bad (_("missing cpu architecture"));
2097
fddf5b5b
AM		 2098 no_cond_jump_promotion = 0;
2099 if (*input_line_pointer == ','
29b0f896 2100 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2101 {
2102 char *string = ++input_line_pointer;
2103 int e = get_symbol_end ();
2104
2105 if (strcmp (string, "nojumps") == 0)
2106 no_cond_jump_promotion = 1;
2107 else if (strcmp (string, "jumps") == 0)
2108 ;
2109 else
2110 as_bad (_("no such architecture modifier: `%s'"), string);
2111
2112 *input_line_pointer = e;
2113 }
2114
e413e4e9
AM		 2115 demand_empty_rest_of_line ();
2116}
2117
8a9036a4
L		 2118enum bfd_architecture
2119i386_arch (void)
2120{
3632d14b 2121 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2122 {
2123 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2124 || flag_code != CODE_64BIT)
2125 as_fatal (_("Intel L1OM is 64bit ELF only"));
2126 return bfd_arch_l1om;
2127 }
2128 else
2129 return bfd_arch_i386;
2130}
2131
b9d79e03
JH		 2132unsigned long
2133i386_mach ()
2134{
2135 if (!strcmp (default_arch, "x86_64"))
8a9036a4 2136 {
3632d14b 2137 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2138 {
2139 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2140 as_fatal (_("Intel L1OM is 64bit ELF only"));
2141 return bfd_mach_l1om;
2142 }
2143 else
2144 return bfd_mach_x86_64;
2145 }
b9d79e03
JH		 2146 else if (!strcmp (default_arch, "i386"))
2147 return bfd_mach_i386_i386;
2148 else
2149 as_fatal (_("Unknown architecture"));
2150}
b9d79e03 2151\f
252b5132
RH		 2152void
2153md_begin ()
2154{
2155 const char *hash_err;
2156
47926f60 2157 /* Initialize op_hash hash table. */
252b5132
RH		 2158 op_hash = hash_new ();
2159
2160 {
d3ce72d0 2161 const insn_template *optab;
29b0f896 2162 templates *core_optab;
252b5132 2163
47926f60
KH		 2164 /* Setup for loop. */
2165 optab = i386_optab;
252b5132
RH		 2166 core_optab = (templates *) xmalloc (sizeof (templates));
2167 core_optab->start = optab;
2168
2169 while (1)
2170 {
2171 ++optab;
2172 if (optab->name == NULL
2173 || strcmp (optab->name, (optab - 1)->name) != 0)
2174 {
2175 /* different name --> ship out current template list;
47926f60 2176 add to hash table; & begin anew. */
252b5132
RH		 2177 core_optab->end = optab;
2178 hash_err = hash_insert (op_hash,
2179 (optab - 1)->name,
5a49b8ac 2180 (void *) core_optab);
252b5132
RH		 2181 if (hash_err)
2182 {
252b5132
RH		 2183 as_fatal (_("Internal Error: Can't hash %s: %s"),
2184 (optab - 1)->name,
2185 hash_err);
2186 }
2187 if (optab->name == NULL)
2188 break;
2189 core_optab = (templates *) xmalloc (sizeof (templates));
2190 core_optab->start = optab;
2191 }
2192 }
2193 }
2194
47926f60 2195 /* Initialize reg_hash hash table. */
252b5132
RH		 2196 reg_hash = hash_new ();
2197 {
29b0f896 2198 const reg_entry *regtab;
c3fe08fa 2199 unsigned int regtab_size = i386_regtab_size;
252b5132 2200
c3fe08fa 2201 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2202 {
5a49b8ac 2203 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2204 if (hash_err)
3e73aa7c
JH		 2205 as_fatal (_("Internal Error: Can't hash %s: %s"),
2206 regtab->reg_name,
2207 hash_err);
252b5132
RH		 2208 }
2209 }
2210
47926f60 2211 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2212 {
29b0f896
AM		 2213 int c;
2214 char *p;
252b5132
RH		 2215
2216 for (c = 0; c < 256; c++)
2217 {
3882b010 2218 if (ISDIGIT (c))
252b5132
RH		 2219 {
2220 digit_chars[c] = c;
2221 mnemonic_chars[c] = c;
2222 register_chars[c] = c;
2223 operand_chars[c] = c;
2224 }
3882b010 2225 else if (ISLOWER (c))
252b5132
RH		 2226 {
2227 mnemonic_chars[c] = c;
2228 register_chars[c] = c;
2229 operand_chars[c] = c;
2230 }
3882b010 2231 else if (ISUPPER (c))
252b5132 2232 {
3882b010 2233 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2234 register_chars[c] = mnemonic_chars[c];
2235 operand_chars[c] = c;
2236 }
2237
3882b010 2238 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2239 identifier_chars[c] = c;
2240 else if (c >= 128)
2241 {
2242 identifier_chars[c] = c;
2243 operand_chars[c] = c;
2244 }
2245 }
2246
2247#ifdef LEX_AT
2248 identifier_chars['@'] = '@';
32137342
NC		 2249#endif
2250#ifdef LEX_QM
2251 identifier_chars['?'] = '?';
2252 operand_chars['?'] = '?';
252b5132 2253#endif
252b5132 2254 digit_chars['-'] = '-';
c0f3af97 2255 mnemonic_chars['_'] = '_';
791fe849 2256 mnemonic_chars['-'] = '-';
0003779b 2257 mnemonic_chars['.'] = '.';
252b5132
RH		 2258 identifier_chars['_'] = '_';
2259 identifier_chars['.'] = '.';
2260
2261 for (p = operand_special_chars; *p != '\0'; p++)
2262 operand_chars[(unsigned char) *p] = *p;
2263 }
2264
2265#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2266 if (IS_ELF)
252b5132
RH		 2267 {
2268 record_alignment (text_section, 2);
2269 record_alignment (data_section, 2);
2270 record_alignment (bss_section, 2);
2271 }
2272#endif
a4447b93
RH		 2273
2274 if (flag_code == CODE_64BIT)
2275 {
2276 x86_dwarf2_return_column = 16;
2277 x86_cie_data_alignment = -8;
2278 }
2279 else
2280 {
2281 x86_dwarf2_return_column = 8;
2282 x86_cie_data_alignment = -4;
2283 }
252b5132
RH		 2284}
2285
2286void
e3bb37b5 2287i386_print_statistics (FILE *file)
252b5132
RH		 2288{
2289 hash_print_statistics (file, "i386 opcode", op_hash);
2290 hash_print_statistics (file, "i386 register", reg_hash);
2291}
2292\f
252b5132
RH		 2293#ifdef DEBUG386
2294
ce8a8b2f 2295/* Debugging routines for md_assemble. */
d3ce72d0 2296static void pte (insn_template *);
40fb9820 2297static void pt (i386_operand_type);
e3bb37b5
L		 2298static void pe (expressionS *);
2299static void ps (symbolS *);
252b5132
RH		 2300
2301static void
e3bb37b5 2302pi (char *line, i386_insn *x)
252b5132 2303{
09f131f2 2304 unsigned int i;
252b5132
RH		 2305
2306 fprintf (stdout, "%s: template ", line);
2307 pte (&x->tm);
09f131f2
JH		 2308 fprintf (stdout, " address: base %s index %s scale %x\n",
2309 x->base_reg ? x->base_reg->reg_name : "none",
2310 x->index_reg ? x->index_reg->reg_name : "none",
2311 x->log2_scale_factor);
2312 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2313 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2314 fprintf (stdout, " sib: base %x index %x scale %x\n",
2315 x->sib.base, x->sib.index, x->sib.scale);
2316 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2317 (x->rex & REX_W) != 0,
2318 (x->rex & REX_R) != 0,
2319 (x->rex & REX_X) != 0,
2320 (x->rex & REX_B) != 0);
252b5132
RH		 2321 for (i = 0; i < x->operands; i++)
2322 {
2323 fprintf (stdout, " #%d: ", i + 1);
2324 pt (x->types[i]);
2325 fprintf (stdout, "\n");
40fb9820
L		 2326 if (x->types[i].bitfield.reg8
2327 || x->types[i].bitfield.reg16
2328 || x->types[i].bitfield.reg32
2329 || x->types[i].bitfield.reg64
2330 || x->types[i].bitfield.regmmx
2331 || x->types[i].bitfield.regxmm
c0f3af97 2332 || x->types[i].bitfield.regymm
40fb9820
L		 2333 || x->types[i].bitfield.sreg2
2334 || x->types[i].bitfield.sreg3
2335 || x->types[i].bitfield.control
2336 || x->types[i].bitfield.debug
2337 || x->types[i].bitfield.test)
520dc8e8 2338 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2339 if (operand_type_check (x->types[i], imm))
520dc8e8 2340 pe (x->op[i].imms);
40fb9820 2341 if (operand_type_check (x->types[i], disp))
520dc8e8 2342 pe (x->op[i].disps);
252b5132
RH		 2343 }
2344}
2345
2346static void
d3ce72d0 2347pte (insn_template *t)
252b5132 2348{
09f131f2 2349 unsigned int i;
252b5132 2350 fprintf (stdout, " %d operands ", t->operands);
47926f60 2351 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2352 if (t->extension_opcode != None)
2353 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2354 if (t->opcode_modifier.d)
252b5132 2355 fprintf (stdout, "D");
40fb9820 2356 if (t->opcode_modifier.w)
252b5132
RH		 2357 fprintf (stdout, "W");
2358 fprintf (stdout, "\n");
2359 for (i = 0; i < t->operands; i++)
2360 {
2361 fprintf (stdout, " #%d type ", i + 1);
2362 pt (t->operand_types[i]);
2363 fprintf (stdout, "\n");
2364 }
2365}
2366
2367static void
e3bb37b5 2368pe (expressionS *e)
252b5132 2369{
24eab124 2370 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2371 fprintf (stdout, " add_number %ld (%lx)\n",
2372 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2373 if (e->X_add_symbol)
2374 {
2375 fprintf (stdout, " add_symbol ");
2376 ps (e->X_add_symbol);
2377 fprintf (stdout, "\n");
2378 }
2379 if (e->X_op_symbol)
2380 {
2381 fprintf (stdout, " op_symbol ");
2382 ps (e->X_op_symbol);
2383 fprintf (stdout, "\n");
2384 }
2385}
2386
2387static void
e3bb37b5 2388ps (symbolS *s)
252b5132
RH		 2389{
2390 fprintf (stdout, "%s type %s%s",
2391 S_GET_NAME (s),
2392 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2393 segment_name (S_GET_SEGMENT (s)));
2394}
2395
7b81dfbb 2396static struct type_name
252b5132 2397 {
40fb9820
L		 2398 i386_operand_type mask;
2399 const char *name;
252b5132 2400 }
7b81dfbb 2401const type_names[] =
252b5132 2402{
40fb9820
L		 2403 { OPERAND_TYPE_REG8, "r8" },
2404 { OPERAND_TYPE_REG16, "r16" },
2405 { OPERAND_TYPE_REG32, "r32" },
2406 { OPERAND_TYPE_REG64, "r64" },
2407 { OPERAND_TYPE_IMM8, "i8" },
2408 { OPERAND_TYPE_IMM8, "i8s" },
2409 { OPERAND_TYPE_IMM16, "i16" },
2410 { OPERAND_TYPE_IMM32, "i32" },
2411 { OPERAND_TYPE_IMM32S, "i32s" },
2412 { OPERAND_TYPE_IMM64, "i64" },
2413 { OPERAND_TYPE_IMM1, "i1" },
2414 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2415 { OPERAND_TYPE_DISP8, "d8" },
2416 { OPERAND_TYPE_DISP16, "d16" },
2417 { OPERAND_TYPE_DISP32, "d32" },
2418 { OPERAND_TYPE_DISP32S, "d32s" },
2419 { OPERAND_TYPE_DISP64, "d64" },
2420 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2421 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2422 { OPERAND_TYPE_CONTROL, "control reg" },
2423 { OPERAND_TYPE_TEST, "test reg" },
2424 { OPERAND_TYPE_DEBUG, "debug reg" },
2425 { OPERAND_TYPE_FLOATREG, "FReg" },
2426 { OPERAND_TYPE_FLOATACC, "FAcc" },
2427 { OPERAND_TYPE_SREG2, "SReg2" },
2428 { OPERAND_TYPE_SREG3, "SReg3" },
2429 { OPERAND_TYPE_ACC, "Acc" },
2430 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2431 { OPERAND_TYPE_REGMMX, "rMMX" },
2432 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2433 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2434 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2435};
2436
2437static void
40fb9820 2438pt (i386_operand_type t)
252b5132 2439{
40fb9820 2440 unsigned int j;
c6fb90c8 2441 i386_operand_type a;
252b5132 2442
40fb9820 2443 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2444 {
2445 a = operand_type_and (t, type_names[j].mask);
0349dc08 2446 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2447 fprintf (stdout, "%s, ", type_names[j].name);
2448 }
252b5132
RH		 2449 fflush (stdout);
2450}
2451
2452#endif /* DEBUG386 */
2453\f
252b5132 2454static bfd_reloc_code_real_type
3956db08 2455reloc (unsigned int size,
64e74474
AM		 2456 int pcrel,
2457 int sign,
2458 bfd_reloc_code_real_type other)
252b5132 2459{
47926f60 2460 if (other != NO_RELOC)
3956db08 2461 {
91d6fa6a 2462 reloc_howto_type *rel;
3956db08
JB		 2463
2464 if (size == 8)
2465 switch (other)
2466 {
64e74474
AM		 2467 case BFD_RELOC_X86_64_GOT32:
2468 return BFD_RELOC_X86_64_GOT64;
2469 break;
2470 case BFD_RELOC_X86_64_PLTOFF64:
2471 return BFD_RELOC_X86_64_PLTOFF64;
2472 break;
2473 case BFD_RELOC_X86_64_GOTPC32:
2474 other = BFD_RELOC_X86_64_GOTPC64;
2475 break;
2476 case BFD_RELOC_X86_64_GOTPCREL:
2477 other = BFD_RELOC_X86_64_GOTPCREL64;
2478 break;
2479 case BFD_RELOC_X86_64_TPOFF32:
2480 other = BFD_RELOC_X86_64_TPOFF64;
2481 break;
2482 case BFD_RELOC_X86_64_DTPOFF32:
2483 other = BFD_RELOC_X86_64_DTPOFF64;
2484 break;
2485 default:
2486 break;
3956db08 2487 }
e05278af
JB		 2488
2489 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2490 if (size == 4 && flag_code != CODE_64BIT)
2491 sign = -1;
2492
91d6fa6a
NC		 2493 rel = bfd_reloc_type_lookup (stdoutput, other);
2494 if (!rel)
3956db08 2495 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2496 else if (size != bfd_get_reloc_size (rel))
3956db08 2497 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2498 bfd_get_reloc_size (rel),
3956db08 2499 size);
91d6fa6a 2500 else if (pcrel && !rel->pc_relative)
3956db08 2501 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2502 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2503 && !sign)
91d6fa6a 2504 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2505 && sign > 0))
3956db08
JB		 2506 as_bad (_("relocated field and relocation type differ in signedness"));
2507 else
2508 return other;
2509 return NO_RELOC;
2510 }
252b5132
RH		 2511
2512 if (pcrel)
2513 {
3e73aa7c 2514 if (!sign)
3956db08 2515 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2516 switch (size)
2517 {
2518 case 1: return BFD_RELOC_8_PCREL;
2519 case 2: return BFD_RELOC_16_PCREL;
2520 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2521 case 8: return BFD_RELOC_64_PCREL;
252b5132 2522 }
3956db08 2523 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2524 }
2525 else
2526 {
3956db08 2527 if (sign > 0)
e5cb08ac 2528 switch (size)
3e73aa7c
JH		 2529 {
2530 case 4: return BFD_RELOC_X86_64_32S;
2531 }
2532 else
2533 switch (size)
2534 {
2535 case 1: return BFD_RELOC_8;
2536 case 2: return BFD_RELOC_16;
2537 case 4: return BFD_RELOC_32;
2538 case 8: return BFD_RELOC_64;
2539 }
3956db08
JB		 2540 as_bad (_("cannot do %s %u byte relocation"),
2541 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2542 }
2543
0cc9e1d3 2544 return NO_RELOC;
252b5132
RH		 2545}
2546
47926f60
KH		 2547/* Here we decide which fixups can be adjusted to make them relative to
2548 the beginning of the section instead of the symbol. Basically we need
2549 to make sure that the dynamic relocations are done correctly, so in
2550 some cases we force the original symbol to be used. */
2551
252b5132 2552int
e3bb37b5 2553tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2554{
6d249963 2555#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2556 if (!IS_ELF)
31312f95
AM		 2557 return 1;
2558
a161fe53
AM		 2559 /* Don't adjust pc-relative references to merge sections in 64-bit
2560 mode. */
2561 if (use_rela_relocations
2562 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2563 && fixP->fx_pcrel)
252b5132 2564 return 0;
31312f95 2565
8d01d9a9
AJ		 2566 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2567 and changed later by validate_fix. */
2568 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2569 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2570 return 0;
2571
ce8a8b2f 2572 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2573 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2574 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2575 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2576 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2577 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2578 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2579 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2580 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2581 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2582 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2583 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2584 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2585 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2586 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2587 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2588 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2589 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2590 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2591 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2592 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2593 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2594 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2595 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2596 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2597 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2598 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2599 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2600 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2601 return 0;
31312f95 2602#endif
252b5132
RH		 2603 return 1;
2604}
252b5132 2605
b4cac588 2606static int
e3bb37b5 2607intel_float_operand (const char *mnemonic)
252b5132 2608{
9306ca4a
JB		 2609 /* Note that the value returned is meaningful only for opcodes with (memory)
2610 operands, hence the code here is free to improperly handle opcodes that
2611 have no operands (for better performance and smaller code). */
2612
2613 if (mnemonic[0] != 'f')
2614 return 0; /* non-math */
2615
2616 switch (mnemonic[1])
2617 {
2618 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2619 the fs segment override prefix not currently handled because no
2620 call path can make opcodes without operands get here */
2621 case 'i':
2622 return 2 /* integer op */;
2623 case 'l':
2624 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2625 return 3; /* fldcw/fldenv */
2626 break;
2627 case 'n':
2628 if (mnemonic[2] != 'o' /* fnop */)
2629 return 3; /* non-waiting control op */
2630 break;
2631 case 'r':
2632 if (mnemonic[2] == 's')
2633 return 3; /* frstor/frstpm */
2634 break;
2635 case 's':
2636 if (mnemonic[2] == 'a')
2637 return 3; /* fsave */
2638 if (mnemonic[2] == 't')
2639 {
2640 switch (mnemonic[3])
2641 {
2642 case 'c': /* fstcw */
2643 case 'd': /* fstdw */
2644 case 'e': /* fstenv */
2645 case 's': /* fsts[gw] */
2646 return 3;
2647 }
2648 }
2649 break;
2650 case 'x':
2651 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2652 return 0; /* fxsave/fxrstor are not really math ops */
2653 break;
2654 }
252b5132 2655
9306ca4a 2656 return 1;
252b5132
RH		 2657}
2658
c0f3af97
L		 2659/* Build the VEX prefix. */
2660
2661static void
d3ce72d0 2662build_vex_prefix (const insn_template *t)
c0f3af97
L		 2663{
2664 unsigned int register_specifier;
2665 unsigned int implied_prefix;
2666 unsigned int vector_length;
2667
2668 /* Check register specifier. */
2669 if (i.vex.register_specifier)
2670 {
2671 register_specifier = i.vex.register_specifier->reg_num;
2672 if ((i.vex.register_specifier->reg_flags & RegRex))
2673 register_specifier += 8;
2674 register_specifier = ~register_specifier & 0xf;
2675 }
2676 else
2677 register_specifier = 0xf;
2678
fa99fab2
L		 2679 /* Use 2-byte VEX prefix by swappping destination and source
2680 operand. */
2681 if (!i.swap_operand
2682 && i.operands == i.reg_operands
7f399153 2683 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2684 && i.tm.opcode_modifier.s
2685 && i.rex == REX_B)
2686 {
2687 unsigned int xchg = i.operands - 1;
2688 union i386_op temp_op;
2689 i386_operand_type temp_type;
2690
2691 temp_type = i.types[xchg];
2692 i.types[xchg] = i.types[0];
2693 i.types[0] = temp_type;
2694 temp_op = i.op[xchg];
2695 i.op[xchg] = i.op[0];
2696 i.op[0] = temp_op;
2697
9c2799c2 2698 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2699
2700 i.rex = REX_R;
2701 xchg = i.rm.regmem;
2702 i.rm.regmem = i.rm.reg;
2703 i.rm.reg = xchg;
2704
2705 /* Use the next insn. */
2706 i.tm = t[1];
2707 }
2708
e3c58833 2709 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2710
2711 switch ((i.tm.base_opcode >> 8) & 0xff)
2712 {
2713 case 0:
2714 implied_prefix = 0;
2715 break;
2716 case DATA_PREFIX_OPCODE:
2717 implied_prefix = 1;
2718 break;
2719 case REPE_PREFIX_OPCODE:
2720 implied_prefix = 2;
2721 break;
2722 case REPNE_PREFIX_OPCODE:
2723 implied_prefix = 3;
2724 break;
2725 default:
2726 abort ();
2727 }
2728
2729 /* Use 2-byte VEX prefix if possible. */
7f399153 2730 if (i.tm.opcode_modifier.vexopcode == VEX0F
c0f3af97
L		 2731 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2732 {
2733 /* 2-byte VEX prefix. */
2734 unsigned int r;
2735
2736 i.vex.length = 2;
2737 i.vex.bytes[0] = 0xc5;
2738
2739 /* Check the REX.R bit. */
2740 r = (i.rex & REX_R) ? 0 : 1;
2741 i.vex.bytes[1] = (r << 7
2742 | register_specifier << 3
2743 | vector_length << 2
2744 | implied_prefix);
2745 }
2746 else
2747 {
2748 /* 3-byte VEX prefix. */
2749 unsigned int m, w;
2750
f88c9eb0 2751 i.vex.length = 3;
f88c9eb0 2752
7f399153 2753 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2754 {
7f399153
L		 2755 case VEX0F:
2756 m = 0x1;
80de6e00 2757 i.vex.bytes[0] = 0xc4;
7f399153
L		 2758 break;
2759 case VEX0F38:
2760 m = 0x2;
80de6e00 2761 i.vex.bytes[0] = 0xc4;
7f399153
L		 2762 break;
2763 case VEX0F3A:
2764 m = 0x3;
80de6e00 2765 i.vex.bytes[0] = 0xc4;
7f399153
L		 2766 break;
2767 case XOP08:
5dd85c99
SP		 2768 m = 0x8;
2769 i.vex.bytes[0] = 0x8f;
7f399153
L		 2770 break;
2771 case XOP09:
f88c9eb0
SP		 2772 m = 0x9;
2773 i.vex.bytes[0] = 0x8f;
7f399153
L		 2774 break;
2775 case XOP0A:
f88c9eb0
SP		 2776 m = 0xa;
2777 i.vex.bytes[0] = 0x8f;
7f399153
L		 2778 break;
2779 default:
2780 abort ();
f88c9eb0 2781 }
c0f3af97 2782
c0f3af97
L		 2783 /* The high 3 bits of the second VEX byte are 1's compliment
2784 of RXB bits from REX. */
2785 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2786
2787 /* Check the REX.W bit. */
2788 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 2789 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 2790 {
2791 if (w)
2792 abort ();
2793
1ef99a7b 2794 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 2795 w = 1;
2796 }
2797
2798 i.vex.bytes[2] = (w << 7
2799 | register_specifier << 3
2800 | vector_length << 2
2801 | implied_prefix);
2802 }
2803}
2804
65da13b5
L		 2805static void
2806process_immext (void)
2807{
2808 expressionS *exp;
2809
2810 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2811 {
1fed0ba1
L		 2812 /* SSE3 Instructions have the fixed operands with an opcode
2813 suffix which is coded in the same place as an 8-bit immediate
2814 field would be. Here we check those operands and remove them
2815 afterwards. */
65da13b5
L		 2816 unsigned int x;
2817
2818 for (x = 0; x < i.operands; x++)
2819 if (i.op[x].regs->reg_num != x)
2820 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2821 register_prefix, i.op[x].regs->reg_name, x + 1,
2822 i.tm.name);
2823
2824 i.operands = 0;
65da13b5
L		 2825 }
2826
c0f3af97 2827 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2828 which is coded in the same place as an 8-bit immediate field
2829 would be. Here we fake an 8-bit immediate operand from the
2830 opcode suffix stored in tm.extension_opcode.
2831
c1e679ec 2832 AVX instructions also use this encoding, for some of
c0f3af97 2833 3 argument instructions. */
65da13b5 2834
9c2799c2 2835 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2836 && (i.operands <= 2
2837 || (i.tm.opcode_modifier.vex
2838 && i.operands <= 4)));
65da13b5
L		 2839
2840 exp = &im_expressions[i.imm_operands++];
2841 i.op[i.operands].imms = exp;
2842 i.types[i.operands] = imm8;
2843 i.operands++;
2844 exp->X_op = O_constant;
2845 exp->X_add_number = i.tm.extension_opcode;
2846 i.tm.extension_opcode = None;
2847}
2848
252b5132
RH		 2849/* This is the guts of the machine-dependent assembler. LINE points to a
2850 machine dependent instruction. This function is supposed to emit
2851 the frags/bytes it assembles to. */
2852
2853void
65da13b5 2854md_assemble (char *line)
252b5132 2855{
40fb9820 2856 unsigned int j;
252b5132 2857 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 2858 const insn_template *t;
252b5132 2859
47926f60 2860 /* Initialize globals. */
252b5132
RH		 2861 memset (&i, '\0', sizeof (i));
2862 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2863 i.reloc[j] = NO_RELOC;
252b5132
RH		 2864 memset (disp_expressions, '\0', sizeof (disp_expressions));
2865 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2866 save_stack_p = save_stack;
252b5132
RH		 2867
2868 /* First parse an instruction mnemonic & call i386_operand for the operands.
2869 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2870 start of a (possibly prefixed) mnemonic. */
252b5132 2871
29b0f896
AM		 2872 line = parse_insn (line, mnemonic);
2873 if (line == NULL)
2874 return;
252b5132 2875
29b0f896 2876 line = parse_operands (line, mnemonic);
ee86248c 2877 this_operand = -1;
29b0f896
AM		 2878 if (line == NULL)
2879 return;
252b5132 2880
29b0f896
AM		 2881 /* Now we've parsed the mnemonic into a set of templates, and have the
2882 operands at hand. */
2883
2884 /* All intel opcodes have reversed operands except for "bound" and
2885 "enter". We also don't reverse intersegment "jmp" and "call"
2886 instructions with 2 immediate operands so that the immediate segment
050dfa73 2887 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2888 if (intel_syntax
2889 && i.operands > 1
29b0f896 2890 && (strcmp (mnemonic, "bound") != 0)
30123838 2891 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2892 && !(operand_type_check (i.types[0], imm)
2893 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2894 swap_operands ();
2895
ec56d5c0
JB		 2896 /* The order of the immediates should be reversed
2897 for 2 immediates extrq and insertq instructions */
2898 if (i.imm_operands == 2
2899 && (strcmp (mnemonic, "extrq") == 0
2900 || strcmp (mnemonic, "insertq") == 0))
2901 swap_2_operands (0, 1);
2902
29b0f896
AM		 2903 if (i.imm_operands)
2904 optimize_imm ();
2905
b300c311
L		 2906 /* Don't optimize displacement for movabs since it only takes 64bit
2907 displacement. */
2908 if (i.disp_operands
2909 && (flag_code != CODE_64BIT
2910 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2911 optimize_disp ();
2912
2913 /* Next, we find a template that matches the given insn,
2914 making sure the overlap of the given operands types is consistent
2915 with the template operand types. */
252b5132 2916
fa99fab2 2917 if (!(t = match_template ()))
29b0f896 2918 return;
252b5132 2919
daf50ae7 2920 if (sse_check != sse_check_none
81f8a913 2921 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2922 && (i.tm.cpu_flags.bitfield.cpusse
2923 || i.tm.cpu_flags.bitfield.cpusse2
2924 || i.tm.cpu_flags.bitfield.cpusse3
2925 || i.tm.cpu_flags.bitfield.cpussse3
2926 || i.tm.cpu_flags.bitfield.cpusse4_1
2927 || i.tm.cpu_flags.bitfield.cpusse4_2))
2928 {
2929 (sse_check == sse_check_warning
2930 ? as_warn
2931 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2932 }
2933
321fd21e
L		 2934 /* Zap movzx and movsx suffix. The suffix has been set from
2935 "word ptr" or "byte ptr" on the source operand in Intel syntax
2936 or extracted from mnemonic in AT&T syntax. But we'll use
2937 the destination register to choose the suffix for encoding. */
2938 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2939 {
321fd21e
L		 2940 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2941 there is no suffix, the default will be byte extension. */
2942 if (i.reg_operands != 2
2943 && !i.suffix
7ab9ffdd 2944 && intel_syntax)
321fd21e
L		 2945 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2946
2947 i.suffix = 0;
cd61ebfe 2948 }
24eab124 2949
40fb9820 2950 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2951 if (!add_prefix (FWAIT_OPCODE))
2952 return;
252b5132 2953
c1ba0266
L		 2954 /* Check for lock without a lockable instruction. Destination operand
2955 must be memory unless it is xchg (0x86). */
c32fa91d
L		 2956 if (i.prefix[LOCK_PREFIX]
2957 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 2958 || i.mem_operands == 0
2959 || (i.tm.base_opcode != 0x86
2960 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 2961 {
2962 as_bad (_("expecting lockable instruction after `lock'"));
2963 return;
2964 }
2965
29b0f896 2966 /* Check string instruction segment overrides. */
40fb9820 2967 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2968 {
2969 if (!check_string ())
5dd0794d 2970 return;
fc0763e6 2971 i.disp_operands = 0;
29b0f896 2972 }
5dd0794d 2973
29b0f896
AM		 2974 if (!process_suffix ())
2975 return;
e413e4e9 2976
bc0844ae
L		 2977 /* Update operand types. */
2978 for (j = 0; j < i.operands; j++)
2979 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
2980
29b0f896
AM		 2981 /* Make still unresolved immediate matches conform to size of immediate
2982 given in i.suffix. */
2983 if (!finalize_imm ())
2984 return;
252b5132 2985
40fb9820 2986 if (i.types[0].bitfield.imm1)
29b0f896 2987 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2988
9afe6eb8
L		 2989 /* We only need to check those implicit registers for instructions
2990 with 3 operands or less. */
2991 if (i.operands <= 3)
2992 for (j = 0; j < i.operands; j++)
2993 if (i.types[j].bitfield.inoutportreg
2994 || i.types[j].bitfield.shiftcount
2995 || i.types[j].bitfield.acc
2996 || i.types[j].bitfield.floatacc)
2997 i.reg_operands--;
40fb9820 2998
c0f3af97
L		 2999 /* ImmExt should be processed after SSE2AVX. */
3000 if (!i.tm.opcode_modifier.sse2avx
3001 && i.tm.opcode_modifier.immext)
65da13b5 3002 process_immext ();
252b5132 3003
29b0f896
AM		 3004 /* For insns with operands there are more diddles to do to the opcode. */
3005 if (i.operands)
3006 {
3007 if (!process_operands ())
3008 return;
3009 }
40fb9820 3010 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3011 {
3012 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3013 as_warn (_("translating to `%sp'"), i.tm.name);
3014 }
252b5132 3015
c0f3af97 3016 if (i.tm.opcode_modifier.vex)
fa99fab2 3017 build_vex_prefix (t);
c0f3af97 3018
5dd85c99
SP		 3019 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3020 instructions may define INT_OPCODE as well, so avoid this corner
3021 case for those instructions that use MODRM. */
3022 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3023 && !i.tm.opcode_modifier.modrm
3024 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3025 {
3026 i.tm.base_opcode = INT3_OPCODE;
3027 i.imm_operands = 0;
3028 }
252b5132 3029
40fb9820
L		 3030 if ((i.tm.opcode_modifier.jump
3031 || i.tm.opcode_modifier.jumpbyte
3032 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3033 && i.op[0].disps->X_op == O_constant)
3034 {
3035 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3036 the absolute address given by the constant. Since ix86 jumps and
3037 calls are pc relative, we need to generate a reloc. */
3038 i.op[0].disps->X_add_symbol = &abs_symbol;
3039 i.op[0].disps->X_op = O_symbol;
3040 }
252b5132 3041
40fb9820 3042 if (i.tm.opcode_modifier.rex64)
161a04f6 3043 i.rex |= REX_W;
252b5132 3044
29b0f896
AM		 3045 /* For 8 bit registers we need an empty rex prefix. Also if the
3046 instruction already has a prefix, we need to convert old
3047 registers to new ones. */
773f551c 3048
40fb9820 3049 if ((i.types[0].bitfield.reg8
29b0f896 3050 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3051 || (i.types[1].bitfield.reg8
29b0f896 3052 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3053 || ((i.types[0].bitfield.reg8
3054 || i.types[1].bitfield.reg8)
29b0f896
AM		 3055 && i.rex != 0))
3056 {
3057 int x;
726c5dcd 3058
29b0f896
AM		 3059 i.rex |= REX_OPCODE;
3060 for (x = 0; x < 2; x++)
3061 {
3062 /* Look for 8 bit operand that uses old registers. */
40fb9820 3063 if (i.types[x].bitfield.reg8
29b0f896 3064 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3065 {
29b0f896
AM		 3066 /* In case it is "hi" register, give up. */
3067 if (i.op[x].regs->reg_num > 3)
a540244d 3068 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3069 "instruction requiring REX prefix."),
a540244d 3070 register_prefix, i.op[x].regs->reg_name);
773f551c 3071
29b0f896
AM		 3072 /* Otherwise it is equivalent to the extended register.
3073 Since the encoding doesn't change this is merely
3074 cosmetic cleanup for debug output. */
3075
3076 i.op[x].regs = i.op[x].regs + 8;
773f551c 3077 }
29b0f896
AM		 3078 }
3079 }
773f551c 3080
7ab9ffdd 3081 if (i.rex != 0)
29b0f896
AM		 3082 add_prefix (REX_OPCODE | i.rex);
3083
3084 /* We are ready to output the insn. */
3085 output_insn ();
3086}
3087
3088static char *
e3bb37b5 3089parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3090{
3091 char *l = line;
3092 char *token_start = l;
3093 char *mnem_p;
5c6af06e 3094 int supported;
d3ce72d0 3095 const insn_template *t;
b6169b20 3096 char *dot_p = NULL;
29b0f896
AM		 3097
3098 /* Non-zero if we found a prefix only acceptable with string insns. */
3099 const char *expecting_string_instruction = NULL;
45288df1 3100
29b0f896
AM		 3101 while (1)
3102 {
3103 mnem_p = mnemonic;
3104 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3105 {
b6169b20
L		 3106 if (*mnem_p == '.')
3107 dot_p = mnem_p;
29b0f896
AM		 3108 mnem_p++;
3109 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3110 {
29b0f896
AM		 3111 as_bad (_("no such instruction: `%s'"), token_start);
3112 return NULL;
3113 }
3114 l++;
3115 }
3116 if (!is_space_char (*l)
3117 && *l != END_OF_INSN
e44823cf
JB		 3118 && (intel_syntax
3119 || (*l != PREFIX_SEPARATOR
3120 && *l != ',')))
29b0f896
AM		 3121 {
3122 as_bad (_("invalid character %s in mnemonic"),
3123 output_invalid (*l));
3124 return NULL;
3125 }
3126 if (token_start == l)
3127 {
e44823cf 3128 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3129 as_bad (_("expecting prefix; got nothing"));
3130 else
3131 as_bad (_("expecting mnemonic; got nothing"));
3132 return NULL;
3133 }
45288df1 3134
29b0f896 3135 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3136 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3137
29b0f896
AM		 3138 if (*l != END_OF_INSN
3139 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3140 && current_templates
40fb9820 3141 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3142 {
c6fb90c8 3143 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3144 {
3145 as_bad ((flag_code != CODE_64BIT
3146 ? _("`%s' is only supported in 64-bit mode")
3147 : _("`%s' is not supported in 64-bit mode")),
3148 current_templates->start->name);
3149 return NULL;
3150 }
29b0f896
AM		 3151 /* If we are in 16-bit mode, do not allow addr16 or data16.
3152 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3153 if ((current_templates->start->opcode_modifier.size16
3154 || current_templates->start->opcode_modifier.size32)
29b0f896 3155 && flag_code != CODE_64BIT
40fb9820 3156 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3157 ^ (flag_code == CODE_16BIT)))
3158 {
3159 as_bad (_("redundant %s prefix"),
3160 current_templates->start->name);
3161 return NULL;
45288df1 3162 }
29b0f896
AM		 3163 /* Add prefix, checking for repeated prefixes. */
3164 switch (add_prefix (current_templates->start->base_opcode))
3165 {
c32fa91d 3166 case PREFIX_EXIST:
29b0f896 3167 return NULL;
c32fa91d 3168 case PREFIX_REP:
29b0f896
AM		 3169 expecting_string_instruction = current_templates->start->name;
3170 break;
c32fa91d
L		 3171 default:
3172 break;
29b0f896
AM		 3173 }
3174 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3175 token_start = ++l;
3176 }
3177 else
3178 break;
3179 }
45288df1 3180
30a55f88 3181 if (!current_templates)
b6169b20 3182 {
30a55f88
L		 3183 /* Check if we should swap operand in encoding. */
3184 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3185 i.swap_operand = 1;
3186 else
3187 goto check_suffix;
3188 mnem_p = dot_p;
3189 *dot_p = '\0';
d3ce72d0 3190 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3191 }
3192
29b0f896
AM		 3193 if (!current_templates)
3194 {
b6169b20 3195check_suffix:
29b0f896
AM		 3196 /* See if we can get a match by trimming off a suffix. */
3197 switch (mnem_p[-1])
3198 {
3199 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3200 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3201 i.suffix = SHORT_MNEM_SUFFIX;
3202 else
29b0f896
AM		 3203 case BYTE_MNEM_SUFFIX:
3204 case QWORD_MNEM_SUFFIX:
3205 i.suffix = mnem_p[-1];
3206 mnem_p[-1] = '\0';
d3ce72d0
NC		 3207 current_templates = (const templates *) hash_find (op_hash,
3208 mnemonic);
29b0f896
AM		 3209 break;
3210 case SHORT_MNEM_SUFFIX:
3211 case LONG_MNEM_SUFFIX:
3212 if (!intel_syntax)
3213 {
3214 i.suffix = mnem_p[-1];
3215 mnem_p[-1] = '\0';
d3ce72d0
NC		 3216 current_templates = (const templates *) hash_find (op_hash,
3217 mnemonic);
29b0f896
AM		 3218 }
3219 break;
252b5132 3220
29b0f896
AM		 3221 /* Intel Syntax. */
3222 case 'd':
3223 if (intel_syntax)
3224 {
9306ca4a 3225 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3226 i.suffix = SHORT_MNEM_SUFFIX;
3227 else
3228 i.suffix = LONG_MNEM_SUFFIX;
3229 mnem_p[-1] = '\0';
d3ce72d0
NC		 3230 current_templates = (const templates *) hash_find (op_hash,
3231 mnemonic);
29b0f896
AM		 3232 }
3233 break;
3234 }
3235 if (!current_templates)
3236 {
3237 as_bad (_("no such instruction: `%s'"), token_start);
3238 return NULL;
3239 }
3240 }
252b5132 3241
40fb9820
L		 3242 if (current_templates->start->opcode_modifier.jump
3243 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3244 {
3245 /* Check for a branch hint. We allow ",pt" and ",pn" for
3246 predict taken and predict not taken respectively.
3247 I'm not sure that branch hints actually do anything on loop
3248 and jcxz insns (JumpByte) for current Pentium4 chips. They
3249 may work in the future and it doesn't hurt to accept them
3250 now. */
3251 if (l[0] == ',' && l[1] == 'p')
3252 {
3253 if (l[2] == 't')
3254 {
3255 if (!add_prefix (DS_PREFIX_OPCODE))
3256 return NULL;
3257 l += 3;
3258 }
3259 else if (l[2] == 'n')
3260 {
3261 if (!add_prefix (CS_PREFIX_OPCODE))
3262 return NULL;
3263 l += 3;
3264 }
3265 }
3266 }
3267 /* Any other comma loses. */
3268 if (*l == ',')
3269 {
3270 as_bad (_("invalid character %s in mnemonic"),
3271 output_invalid (*l));
3272 return NULL;
3273 }
252b5132 3274
29b0f896 3275 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3276 supported = 0;
3277 for (t = current_templates->start; t < current_templates->end; ++t)
3278 {
c0f3af97
L		 3279 supported |= cpu_flags_match (t);
3280 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3281 goto skip;
5c6af06e 3282 }
3629bb00 3283
c0f3af97 3284 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3285 {
3286 as_bad (flag_code == CODE_64BIT
3287 ? _("`%s' is not supported in 64-bit mode")
3288 : _("`%s' is only supported in 64-bit mode"),
3289 current_templates->start->name);
3290 return NULL;
3291 }
c0f3af97 3292 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3293 {
3629bb00 3294 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3295 current_templates->start->name,
41aacd83 3296 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3297 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3298 return NULL;
29b0f896 3299 }
3629bb00
L		 3300
3301skip:
3302 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3303 && (flag_code != CODE_16BIT))
29b0f896
AM		 3304 {
3305 as_warn (_("use .code16 to ensure correct addressing mode"));
3306 }
252b5132 3307
29b0f896 3308 /* Check for rep/repne without a string instruction. */
f41bbced 3309 if (expecting_string_instruction)
29b0f896 3310 {
f41bbced
JB		 3311 static templates override;
3312
3313 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3314 if (t->opcode_modifier.isstring)
f41bbced
JB		 3315 break;
3316 if (t >= current_templates->end)
3317 {
3318 as_bad (_("expecting string instruction after `%s'"),
64e74474 3319 expecting_string_instruction);
f41bbced
JB		 3320 return NULL;
3321 }
3322 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3323 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3324 break;
3325 override.end = t;
3326 current_templates = &override;
29b0f896 3327 }
252b5132 3328
29b0f896
AM		 3329 return l;
3330}
252b5132 3331
29b0f896 3332static char *
e3bb37b5 3333parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3334{
3335 char *token_start;
3138f287 3336
29b0f896
AM		 3337 /* 1 if operand is pending after ','. */
3338 unsigned int expecting_operand = 0;
252b5132 3339
29b0f896
AM		 3340 /* Non-zero if operand parens not balanced. */
3341 unsigned int paren_not_balanced;
3342
3343 while (*l != END_OF_INSN)
3344 {
3345 /* Skip optional white space before operand. */
3346 if (is_space_char (*l))
3347 ++l;
3348 if (!is_operand_char (*l) && *l != END_OF_INSN)
3349 {
3350 as_bad (_("invalid character %s before operand %d"),
3351 output_invalid (*l),
3352 i.operands + 1);
3353 return NULL;
3354 }
3355 token_start = l; /* after white space */
3356 paren_not_balanced = 0;
3357 while (paren_not_balanced || *l != ',')
3358 {
3359 if (*l == END_OF_INSN)
3360 {
3361 if (paren_not_balanced)
3362 {
3363 if (!intel_syntax)
3364 as_bad (_("unbalanced parenthesis in operand %d."),
3365 i.operands + 1);
3366 else
3367 as_bad (_("unbalanced brackets in operand %d."),
3368 i.operands + 1);
3369 return NULL;
3370 }
3371 else
3372 break; /* we are done */
3373 }
3374 else if (!is_operand_char (*l) && !is_space_char (*l))
3375 {
3376 as_bad (_("invalid character %s in operand %d"),
3377 output_invalid (*l),
3378 i.operands + 1);
3379 return NULL;
3380 }
3381 if (!intel_syntax)
3382 {
3383 if (*l == '(')
3384 ++paren_not_balanced;
3385 if (*l == ')')
3386 --paren_not_balanced;
3387 }
3388 else
3389 {
3390 if (*l == '[')
3391 ++paren_not_balanced;
3392 if (*l == ']')
3393 --paren_not_balanced;
3394 }
3395 l++;
3396 }
3397 if (l != token_start)
3398 { /* Yes, we've read in another operand. */
3399 unsigned int operand_ok;
3400 this_operand = i.operands++;
7d5e4556 3401 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3402 if (i.operands > MAX_OPERANDS)
3403 {
3404 as_bad (_("spurious operands; (%d operands/instruction max)"),
3405 MAX_OPERANDS);
3406 return NULL;
3407 }
3408 /* Now parse operand adding info to 'i' as we go along. */
3409 END_STRING_AND_SAVE (l);
3410
3411 if (intel_syntax)
3412 operand_ok =
3413 i386_intel_operand (token_start,
3414 intel_float_operand (mnemonic));
3415 else
a7619375 3416 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3417
3418 RESTORE_END_STRING (l);
3419 if (!operand_ok)
3420 return NULL;
3421 }
3422 else
3423 {
3424 if (expecting_operand)
3425 {
3426 expecting_operand_after_comma:
3427 as_bad (_("expecting operand after ','; got nothing"));
3428 return NULL;
3429 }
3430 if (*l == ',')
3431 {
3432 as_bad (_("expecting operand before ','; got nothing"));
3433 return NULL;
3434 }
3435 }
7f3f1ea2 3436
29b0f896
AM		 3437 /* Now *l must be either ',' or END_OF_INSN. */
3438 if (*l == ',')
3439 {
3440 if (*++l == END_OF_INSN)
3441 {
3442 /* Just skip it, if it's \n complain. */
3443 goto expecting_operand_after_comma;
3444 }
3445 expecting_operand = 1;
3446 }
3447 }
3448 return l;
3449}
7f3f1ea2 3450
050dfa73 3451static void
4d456e3d 3452swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3453{
3454 union i386_op temp_op;
40fb9820 3455 i386_operand_type temp_type;
050dfa73 3456 enum bfd_reloc_code_real temp_reloc;
4eed87de 3457
050dfa73
MM		 3458 temp_type = i.types[xchg2];
3459 i.types[xchg2] = i.types[xchg1];
3460 i.types[xchg1] = temp_type;
3461 temp_op = i.op[xchg2];
3462 i.op[xchg2] = i.op[xchg1];
3463 i.op[xchg1] = temp_op;
3464 temp_reloc = i.reloc[xchg2];
3465 i.reloc[xchg2] = i.reloc[xchg1];
3466 i.reloc[xchg1] = temp_reloc;
3467}
3468
29b0f896 3469static void
e3bb37b5 3470swap_operands (void)
29b0f896 3471{
b7c61d9a 3472 switch (i.operands)
050dfa73 3473 {
c0f3af97 3474 case 5:
b7c61d9a 3475 case 4:
4d456e3d 3476 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3477 case 3:
3478 case 2:
4d456e3d 3479 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3480 break;
3481 default:
3482 abort ();
29b0f896 3483 }
29b0f896
AM		 3484
3485 if (i.mem_operands == 2)
3486 {
3487 const seg_entry *temp_seg;
3488 temp_seg = i.seg[0];
3489 i.seg[0] = i.seg[1];
3490 i.seg[1] = temp_seg;
3491 }
3492}
252b5132 3493
29b0f896
AM		 3494/* Try to ensure constant immediates are represented in the smallest
3495 opcode possible. */
3496static void
e3bb37b5 3497optimize_imm (void)
29b0f896
AM		 3498{
3499 char guess_suffix = 0;
3500 int op;
252b5132 3501
29b0f896
AM		 3502 if (i.suffix)
3503 guess_suffix = i.suffix;
3504 else if (i.reg_operands)
3505 {
3506 /* Figure out a suffix from the last register operand specified.
3507 We can't do this properly yet, ie. excluding InOutPortReg,
3508 but the following works for instructions with immediates.
3509 In any case, we can't set i.suffix yet. */
3510 for (op = i.operands; --op >= 0;)
40fb9820 3511 if (i.types[op].bitfield.reg8)
7ab9ffdd 3512 {
40fb9820
L		 3513 guess_suffix = BYTE_MNEM_SUFFIX;
3514 break;
3515 }
3516 else if (i.types[op].bitfield.reg16)
252b5132 3517 {
40fb9820
L		 3518 guess_suffix = WORD_MNEM_SUFFIX;
3519 break;
3520 }
3521 else if (i.types[op].bitfield.reg32)
3522 {
3523 guess_suffix = LONG_MNEM_SUFFIX;
3524 break;
3525 }
3526 else if (i.types[op].bitfield.reg64)
3527 {
3528 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3529 break;
252b5132 3530 }
29b0f896
AM		 3531 }
3532 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3533 guess_suffix = WORD_MNEM_SUFFIX;
3534
3535 for (op = i.operands; --op >= 0;)
40fb9820 3536 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3537 {
3538 switch (i.op[op].imms->X_op)
252b5132 3539 {
29b0f896
AM		 3540 case O_constant:
3541 /* If a suffix is given, this operand may be shortened. */
3542 switch (guess_suffix)
252b5132 3543 {
29b0f896 3544 case LONG_MNEM_SUFFIX:
40fb9820
L		 3545 i.types[op].bitfield.imm32 = 1;
3546 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3547 break;
3548 case WORD_MNEM_SUFFIX:
40fb9820
L		 3549 i.types[op].bitfield.imm16 = 1;
3550 i.types[op].bitfield.imm32 = 1;
3551 i.types[op].bitfield.imm32s = 1;
3552 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3553 break;
3554 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3555 i.types[op].bitfield.imm8 = 1;
3556 i.types[op].bitfield.imm8s = 1;
3557 i.types[op].bitfield.imm16 = 1;
3558 i.types[op].bitfield.imm32 = 1;
3559 i.types[op].bitfield.imm32s = 1;
3560 i.types[op].bitfield.imm64 = 1;
29b0f896 3561 break;
252b5132 3562 }
252b5132 3563
29b0f896
AM		 3564 /* If this operand is at most 16 bits, convert it
3565 to a signed 16 bit number before trying to see
3566 whether it will fit in an even smaller size.
3567 This allows a 16-bit operand such as $0xffe0 to
3568 be recognised as within Imm8S range. */
40fb9820 3569 if ((i.types[op].bitfield.imm16)
29b0f896 3570 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3571 {
29b0f896
AM		 3572 i.op[op].imms->X_add_number =
3573 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3574 }
40fb9820 3575 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3576 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3577 == 0))
3578 {
3579 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3580 ^ ((offsetT) 1 << 31))
3581 - ((offsetT) 1 << 31));
3582 }
40fb9820 3583 i.types[op]
c6fb90c8
L		 3584 = operand_type_or (i.types[op],
3585 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3586
29b0f896
AM		 3587 /* We must avoid matching of Imm32 templates when 64bit
3588 only immediate is available. */
3589 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3590 i.types[op].bitfield.imm32 = 0;
29b0f896 3591 break;
252b5132 3592
29b0f896
AM		 3593 case O_absent:
3594 case O_register:
3595 abort ();
3596
3597 /* Symbols and expressions. */
3598 default:
9cd96992
JB		 3599 /* Convert symbolic operand to proper sizes for matching, but don't
3600 prevent matching a set of insns that only supports sizes other
3601 than those matching the insn suffix. */
3602 {
40fb9820 3603 i386_operand_type mask, allowed;
d3ce72d0 3604 const insn_template *t;
9cd96992 3605
0dfbf9d7
L		 3606 operand_type_set (&mask, 0);
3607 operand_type_set (&allowed, 0);
40fb9820 3608
4eed87de
AM		 3609 for (t = current_templates->start;
3610 t < current_templates->end;
3611 ++t)
c6fb90c8
L		 3612 allowed = operand_type_or (allowed,
3613 t->operand_types[op]);
9cd96992
JB		 3614 switch (guess_suffix)
3615 {
3616 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3617 mask.bitfield.imm64 = 1;
3618 mask.bitfield.imm32s = 1;
9cd96992
JB		 3619 break;
3620 case LONG_MNEM_SUFFIX:
40fb9820 3621 mask.bitfield.imm32 = 1;
9cd96992
JB		 3622 break;
3623 case WORD_MNEM_SUFFIX:
40fb9820 3624 mask.bitfield.imm16 = 1;
9cd96992
JB		 3625 break;
3626 case BYTE_MNEM_SUFFIX:
40fb9820 3627 mask.bitfield.imm8 = 1;
9cd96992
JB		 3628 break;
3629 default:
9cd96992
JB		 3630 break;
3631 }
c6fb90c8 3632 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3633 if (!operand_type_all_zero (&allowed))
c6fb90c8 3634 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3635 }
29b0f896 3636 break;
252b5132 3637 }
29b0f896
AM		 3638 }
3639}
47926f60 3640
29b0f896
AM		 3641/* Try to use the smallest displacement type too. */
3642static void
e3bb37b5 3643optimize_disp (void)
29b0f896
AM		 3644{
3645 int op;
3e73aa7c 3646
29b0f896 3647 for (op = i.operands; --op >= 0;)
40fb9820 3648 if (operand_type_check (i.types[op], disp))
252b5132 3649 {
b300c311 3650 if (i.op[op].disps->X_op == O_constant)
252b5132 3651 {
91d6fa6a 3652 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3653
40fb9820 3654 if (i.types[op].bitfield.disp16
91d6fa6a 3655 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3656 {
3657 /* If this operand is at most 16 bits, convert
3658 to a signed 16 bit number and don't use 64bit
3659 displacement. */
91d6fa6a 3660 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3661 i.types[op].bitfield.disp64 = 0;
b300c311 3662 }
40fb9820 3663 if (i.types[op].bitfield.disp32
91d6fa6a 3664 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3665 {
3666 /* If this operand is at most 32 bits, convert
3667 to a signed 32 bit number and don't use 64bit
3668 displacement. */
91d6fa6a
NC		 3669 op_disp &= (((offsetT) 2 << 31) - 1);
3670 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3671 i.types[op].bitfield.disp64 = 0;
b300c311 3672 }
91d6fa6a 3673 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3674 {
40fb9820
L		 3675 i.types[op].bitfield.disp8 = 0;
3676 i.types[op].bitfield.disp16 = 0;
3677 i.types[op].bitfield.disp32 = 0;
3678 i.types[op].bitfield.disp32s = 0;
3679 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3680 i.op[op].disps = 0;
3681 i.disp_operands--;
3682 }
3683 else if (flag_code == CODE_64BIT)
3684 {
91d6fa6a 3685 if (fits_in_signed_long (op_disp))
28a9d8f5 3686 {
40fb9820
L		 3687 i.types[op].bitfield.disp64 = 0;
3688 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3689 }
0e1147d9 3690 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3691 && fits_in_unsigned_long (op_disp))
40fb9820 3692 i.types[op].bitfield.disp32 = 1;
b300c311 3693 }
40fb9820
L		 3694 if ((i.types[op].bitfield.disp32
3695 || i.types[op].bitfield.disp32s
3696 || i.types[op].bitfield.disp16)
91d6fa6a 3697 && fits_in_signed_byte (op_disp))
40fb9820 3698 i.types[op].bitfield.disp8 = 1;
252b5132 3699 }
67a4f2b7
AO		 3700 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3701 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3702 {
3703 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3704 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3705 i.types[op].bitfield.disp8 = 0;
3706 i.types[op].bitfield.disp16 = 0;
3707 i.types[op].bitfield.disp32 = 0;
3708 i.types[op].bitfield.disp32s = 0;
3709 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3710 }
3711 else
b300c311 3712 /* We only support 64bit displacement on constants. */
40fb9820 3713 i.types[op].bitfield.disp64 = 0;
252b5132 3714 }
29b0f896
AM		 3715}
3716
d3ce72d0 3717static const insn_template *
e3bb37b5 3718match_template (void)
29b0f896
AM		 3719{
3720 /* Points to template once we've found it. */
d3ce72d0 3721 const insn_template *t;
40fb9820 3722 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3723 i386_operand_type overlap4;
29b0f896 3724 unsigned int found_reverse_match;
40fb9820
L		 3725 i386_opcode_modifier suffix_check;
3726 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3727 int addr_prefix_disp;
a5c311ca 3728 unsigned int j;
3629bb00 3729 unsigned int found_cpu_match;
45664ddb 3730 unsigned int check_register;
29b0f896 3731
c0f3af97
L		 3732#if MAX_OPERANDS != 5
3733# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3734#endif
3735
29b0f896 3736 found_reverse_match = 0;
539e75ad 3737 addr_prefix_disp = -1;
40fb9820
L		 3738
3739 memset (&suffix_check, 0, sizeof (suffix_check));
3740 if (i.suffix == BYTE_MNEM_SUFFIX)
3741 suffix_check.no_bsuf = 1;
3742 else if (i.suffix == WORD_MNEM_SUFFIX)
3743 suffix_check.no_wsuf = 1;
3744 else if (i.suffix == SHORT_MNEM_SUFFIX)
3745 suffix_check.no_ssuf = 1;
3746 else if (i.suffix == LONG_MNEM_SUFFIX)
3747 suffix_check.no_lsuf = 1;
3748 else if (i.suffix == QWORD_MNEM_SUFFIX)
3749 suffix_check.no_qsuf = 1;
3750 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3751 suffix_check.no_ldsuf = 1;
29b0f896 3752
45aa61fe 3753 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3754 {
539e75ad
L		 3755 addr_prefix_disp = -1;
3756
29b0f896
AM		 3757 /* Must have right number of operands. */
3758 if (i.operands != t->operands)
3759 continue;
3760
50aecf8c 3761 /* Check processor support. */
c0f3af97
L		 3762 found_cpu_match = (cpu_flags_match (t)
3763 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3764 if (!found_cpu_match)
3765 continue;
3766
e1d4d893
L		 3767 /* Check old gcc support. */
3768 if (!old_gcc && t->opcode_modifier.oldgcc)
3769 continue;
3770
3771 /* Check AT&T mnemonic. */
3772 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3773 continue;
3774
5c07affc
L		 3775 /* Check AT&T syntax Intel syntax. */
3776 if ((intel_syntax && t->opcode_modifier.attsyntax)
3777 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3778 continue;
3779
20592a94 3780 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3781 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3782 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3783 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3784 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3785 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3786 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3787 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3788 continue;
3789
5c07affc 3790 if (!operand_size_match (t))
7d5e4556 3791 continue;
539e75ad 3792
5c07affc
L		 3793 for (j = 0; j < MAX_OPERANDS; j++)
3794 operand_types[j] = t->operand_types[j];
3795
45aa61fe
AM		 3796 /* In general, don't allow 64-bit operands in 32-bit mode. */
3797 if (i.suffix == QWORD_MNEM_SUFFIX
3798 && flag_code != CODE_64BIT
3799 && (intel_syntax
40fb9820 3800 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3801 && !intel_float_operand (t->name))
3802 : intel_float_operand (t->name) != 2)
40fb9820 3803 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3804 && !operand_types[0].bitfield.regxmm
3805 && !operand_types[0].bitfield.regymm)
40fb9820 3806 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3807 && !!operand_types[t->operands > 1].bitfield.regxmm
3808 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3809 && (t->base_opcode != 0x0fc7
3810 || t->extension_opcode != 1 /* cmpxchg8b */))
3811 continue;
3812
192dc9c6
JB		 3813 /* In general, don't allow 32-bit operands on pre-386. */
3814 else if (i.suffix == LONG_MNEM_SUFFIX
3815 && !cpu_arch_flags.bitfield.cpui386
3816 && (intel_syntax
3817 ? (!t->opcode_modifier.ignoresize
3818 && !intel_float_operand (t->name))
3819 : intel_float_operand (t->name) != 2)
3820 && ((!operand_types[0].bitfield.regmmx
3821 && !operand_types[0].bitfield.regxmm)
3822 || (!operand_types[t->operands > 1].bitfield.regmmx
3823 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3824 continue;
3825
29b0f896 3826 /* Do not verify operands when there are none. */
50aecf8c 3827 else
29b0f896 3828 {
c6fb90c8 3829 if (!t->operands)
2dbab7d5
L		 3830 /* We've found a match; break out of loop. */
3831 break;
29b0f896 3832 }
252b5132 3833
539e75ad
L		 3834 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3835 into Disp32/Disp16/Disp32 operand. */
3836 if (i.prefix[ADDR_PREFIX] != 0)
3837 {
40fb9820 3838 /* There should be only one Disp operand. */
539e75ad
L		 3839 switch (flag_code)
3840 {
3841 case CODE_16BIT:
40fb9820
L		 3842 for (j = 0; j < MAX_OPERANDS; j++)
3843 {
3844 if (operand_types[j].bitfield.disp16)
3845 {
3846 addr_prefix_disp = j;
3847 operand_types[j].bitfield.disp32 = 1;
3848 operand_types[j].bitfield.disp16 = 0;
3849 break;
3850 }
3851 }
539e75ad
L		 3852 break;
3853 case CODE_32BIT:
40fb9820
L		 3854 for (j = 0; j < MAX_OPERANDS; j++)
3855 {
3856 if (operand_types[j].bitfield.disp32)
3857 {
3858 addr_prefix_disp = j;
3859 operand_types[j].bitfield.disp32 = 0;
3860 operand_types[j].bitfield.disp16 = 1;
3861 break;
3862 }
3863 }
539e75ad
L		 3864 break;
3865 case CODE_64BIT:
40fb9820
L		 3866 for (j = 0; j < MAX_OPERANDS; j++)
3867 {
3868 if (operand_types[j].bitfield.disp64)
3869 {
3870 addr_prefix_disp = j;
3871 operand_types[j].bitfield.disp64 = 0;
3872 operand_types[j].bitfield.disp32 = 1;
3873 break;
3874 }
3875 }
539e75ad
L		 3876 break;
3877 }
539e75ad
L		 3878 }
3879
45664ddb
L		 3880 /* We check register size only if size of operands can be
3881 encoded the canonical way. */
3882 check_register = t->opcode_modifier.w;
c6fb90c8 3883 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3884 switch (t->operands)
3885 {
3886 case 1:
40fb9820 3887 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3888 continue;
3889 break;
3890 case 2:
8b38ad71
L		 3891 /* xchg %eax, %eax is a special case. It is an aliase for nop
3892 only in 32bit mode and we can use opcode 0x90. In 64bit
3893 mode, we can't use 0x90 for xchg %eax, %eax since it should
3894 zero-extend %eax to %rax. */
3895 if (flag_code == CODE_64BIT
3896 && t->base_opcode == 0x90
0dfbf9d7
L		 3897 && operand_type_equal (&i.types [0], &acc32)
3898 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3899 continue;
b6169b20
L		 3900 if (i.swap_operand)
3901 {
3902 /* If we swap operand in encoding, we either match
3903 the next one or reverse direction of operands. */
3904 if (t->opcode_modifier.s)
3905 continue;
3906 else if (t->opcode_modifier.d)
3907 goto check_reverse;
3908 }
3909
29b0f896 3910 case 3:
fa99fab2
L		 3911 /* If we swap operand in encoding, we match the next one. */
3912 if (i.swap_operand && t->opcode_modifier.s)
3913 continue;
f48ff2ae 3914 case 4:
c0f3af97 3915 case 5:
c6fb90c8 3916 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3917 if (!operand_type_match (overlap0, i.types[0])
3918 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3919 || (check_register
3920 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3921 operand_types[0],
3922 overlap1, i.types[1],
3923 operand_types[1])))
29b0f896
AM		 3924 {
3925 /* Check if other direction is valid ... */
40fb9820 3926 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3927 continue;
3928
b6169b20 3929check_reverse:
29b0f896 3930 /* Try reversing direction of operands. */
c6fb90c8
L		 3931 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3932 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3933 if (!operand_type_match (overlap0, i.types[0])
3934 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3935 || (check_register
3936 && !operand_type_register_match (overlap0,
3937 i.types[0],
3938 operand_types[1],
3939 overlap1,
3940 i.types[1],
3941 operand_types[0])))
29b0f896
AM		 3942 {
3943 /* Does not match either direction. */
3944 continue;
3945 }
3946 /* found_reverse_match holds which of D or FloatDR
3947 we've found. */
40fb9820 3948 if (t->opcode_modifier.d)
8a2ed489 3949 found_reverse_match = Opcode_D;
40fb9820 3950 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3951 found_reverse_match = Opcode_FloatD;
3952 else
3953 found_reverse_match = 0;
40fb9820 3954 if (t->opcode_modifier.floatr)
8a2ed489 3955 found_reverse_match |= Opcode_FloatR;
29b0f896 3956 }
f48ff2ae 3957 else
29b0f896 3958 {
f48ff2ae 3959 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3960 switch (t->operands)
3961 {
c0f3af97
L		 3962 case 5:
3963 overlap4 = operand_type_and (i.types[4],
3964 operand_types[4]);
d1cbb4db 3965 case 4:
c6fb90c8
L		 3966 overlap3 = operand_type_and (i.types[3],
3967 operand_types[3]);
d1cbb4db 3968 case 3:
c6fb90c8
L		 3969 overlap2 = operand_type_and (i.types[2],
3970 operand_types[2]);
d1cbb4db
L		 3971 break;
3972 }
29b0f896 3973
f48ff2ae
L		 3974 switch (t->operands)
3975 {
c0f3af97
L		 3976 case 5:
3977 if (!operand_type_match (overlap4, i.types[4])
3978 || !operand_type_register_match (overlap3,
3979 i.types[3],
3980 operand_types[3],
3981 overlap4,
3982 i.types[4],
3983 operand_types[4]))
3984 continue;
f48ff2ae 3985 case 4:
40fb9820 3986 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3987 || (check_register
3988 && !operand_type_register_match (overlap2,
3989 i.types[2],
3990 operand_types[2],
3991 overlap3,
3992 i.types[3],
3993 operand_types[3])))
f48ff2ae
L		 3994 continue;
3995 case 3:
3996 /* Here we make use of the fact that there are no
3997 reverse match 3 operand instructions, and all 3
3998 operand instructions only need to be checked for
3999 register consistency between operands 2 and 3. */
40fb9820 4000 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4001 || (check_register
4002 && !operand_type_register_match (overlap1,
4003 i.types[1],
4004 operand_types[1],
4005 overlap2,
4006 i.types[2],
4007 operand_types[2])))
f48ff2ae
L		 4008 continue;
4009 break;
4010 }
29b0f896 4011 }
f48ff2ae 4012 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4013 slip through to break. */
4014 }
3629bb00 4015 if (!found_cpu_match)
29b0f896
AM		 4016 {
4017 found_reverse_match = 0;
4018 continue;
4019 }
c0f3af97 4020
29b0f896
AM		 4021 /* We've found a match; break out of loop. */
4022 break;
4023 }
4024
4025 if (t == current_templates->end)
4026 {
4027 /* We found no match. */
95f283e8
L		 4028 if (intel_syntax)
4029 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
4030 current_templates->start->name);
4031 else
4032 as_bad (_("suffix or operands invalid for `%s'"),
4033 current_templates->start->name);
fa99fab2 4034 return NULL;
29b0f896 4035 }
252b5132 4036
29b0f896
AM		 4037 if (!quiet_warnings)
4038 {
4039 if (!intel_syntax
40fb9820
L		 4040 && (i.types[0].bitfield.jumpabsolute
4041 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4042 {
4043 as_warn (_("indirect %s without `*'"), t->name);
4044 }
4045
40fb9820
L		 4046 if (t->opcode_modifier.isprefix
4047 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4048 {
4049 /* Warn them that a data or address size prefix doesn't
4050 affect assembly of the next line of code. */
4051 as_warn (_("stand-alone `%s' prefix"), t->name);
4052 }
4053 }
4054
4055 /* Copy the template we found. */
4056 i.tm = *t;
539e75ad
L		 4057
4058 if (addr_prefix_disp != -1)
4059 i.tm.operand_types[addr_prefix_disp]
4060 = operand_types[addr_prefix_disp];
4061
29b0f896
AM		 4062 if (found_reverse_match)
4063 {
4064 /* If we found a reverse match we must alter the opcode
4065 direction bit. found_reverse_match holds bits to change
4066 (different for int & float insns). */
4067
4068 i.tm.base_opcode ^= found_reverse_match;
4069
539e75ad
L		 4070 i.tm.operand_types[0] = operand_types[1];
4071 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4072 }
4073
fa99fab2 4074 return t;
29b0f896
AM		 4075}
4076
4077static int
e3bb37b5 4078check_string (void)
29b0f896 4079{
40fb9820
L		 4080 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4081 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4082 {
4083 if (i.seg[0] != NULL && i.seg[0] != &es)
4084 {
a87af027 4085 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4086 i.tm.name,
a87af027
JB		 4087 mem_op + 1,
4088 register_prefix);
29b0f896
AM		 4089 return 0;
4090 }
4091 /* There's only ever one segment override allowed per instruction.
4092 This instruction possibly has a legal segment override on the
4093 second operand, so copy the segment to where non-string
4094 instructions store it, allowing common code. */
4095 i.seg[0] = i.seg[1];
4096 }
40fb9820 4097 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4098 {
4099 if (i.seg[1] != NULL && i.seg[1] != &es)
4100 {
a87af027 4101 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4102 i.tm.name,
a87af027
JB		 4103 mem_op + 2,
4104 register_prefix);
29b0f896
AM		 4105 return 0;
4106 }
4107 }
4108 return 1;
4109}
4110
4111static int
543613e9 4112process_suffix (void)
29b0f896
AM		 4113{
4114 /* If matched instruction specifies an explicit instruction mnemonic
4115 suffix, use it. */
40fb9820
L		 4116 if (i.tm.opcode_modifier.size16)
4117 i.suffix = WORD_MNEM_SUFFIX;
4118 else if (i.tm.opcode_modifier.size32)
4119 i.suffix = LONG_MNEM_SUFFIX;
4120 else if (i.tm.opcode_modifier.size64)
4121 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4122 else if (i.reg_operands)
4123 {
4124 /* If there's no instruction mnemonic suffix we try to invent one
4125 based on register operands. */
4126 if (!i.suffix)
4127 {
4128 /* We take i.suffix from the last register operand specified,
4129 Destination register type is more significant than source
381d071f
L		 4130 register type. crc32 in SSE4.2 prefers source register
4131 type. */
4132 if (i.tm.base_opcode == 0xf20f38f1)
4133 {
40fb9820
L		 4134 if (i.types[0].bitfield.reg16)
4135 i.suffix = WORD_MNEM_SUFFIX;
4136 else if (i.types[0].bitfield.reg32)
4137 i.suffix = LONG_MNEM_SUFFIX;
4138 else if (i.types[0].bitfield.reg64)
4139 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4140 }
9344ff29 4141 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4142 {
40fb9820 4143 if (i.types[0].bitfield.reg8)
20592a94
L		 4144 i.suffix = BYTE_MNEM_SUFFIX;
4145 }
381d071f
L		 4146
4147 if (!i.suffix)
4148 {
4149 int op;
4150
20592a94
L		 4151 if (i.tm.base_opcode == 0xf20f38f1
4152 || i.tm.base_opcode == 0xf20f38f0)
4153 {
4154 /* We have to know the operand size for crc32. */
4155 as_bad (_("ambiguous memory operand size for `%s`"),
4156 i.tm.name);
4157 return 0;
4158 }
4159
381d071f 4160 for (op = i.operands; --op >= 0;)
40fb9820 4161 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4162 {
40fb9820
L		 4163 if (i.types[op].bitfield.reg8)
4164 {
4165 i.suffix = BYTE_MNEM_SUFFIX;
4166 break;
4167 }
4168 else if (i.types[op].bitfield.reg16)
4169 {
4170 i.suffix = WORD_MNEM_SUFFIX;
4171 break;
4172 }
4173 else if (i.types[op].bitfield.reg32)
4174 {
4175 i.suffix = LONG_MNEM_SUFFIX;
4176 break;
4177 }
4178 else if (i.types[op].bitfield.reg64)
4179 {
4180 i.suffix = QWORD_MNEM_SUFFIX;
4181 break;
4182 }
381d071f
L		 4183 }
4184 }
29b0f896
AM		 4185 }
4186 else if (i.suffix == BYTE_MNEM_SUFFIX)
4187 {
2eb952a4
L		 4188 if (intel_syntax
4189 && i.tm.opcode_modifier.ignoresize
4190 && i.tm.opcode_modifier.no_bsuf)
4191 i.suffix = 0;
4192 else if (!check_byte_reg ())
29b0f896
AM		 4193 return 0;
4194 }
4195 else if (i.suffix == LONG_MNEM_SUFFIX)
4196 {
2eb952a4
L		 4197 if (intel_syntax
4198 && i.tm.opcode_modifier.ignoresize
4199 && i.tm.opcode_modifier.no_lsuf)
4200 i.suffix = 0;
4201 else if (!check_long_reg ())
29b0f896
AM		 4202 return 0;
4203 }
4204 else if (i.suffix == QWORD_MNEM_SUFFIX)
4205 {
955e1e6a
L		 4206 if (intel_syntax
4207 && i.tm.opcode_modifier.ignoresize
4208 && i.tm.opcode_modifier.no_qsuf)
4209 i.suffix = 0;
4210 else if (!check_qword_reg ())
29b0f896
AM		 4211 return 0;
4212 }
4213 else if (i.suffix == WORD_MNEM_SUFFIX)
4214 {
2eb952a4
L		 4215 if (intel_syntax
4216 && i.tm.opcode_modifier.ignoresize
4217 && i.tm.opcode_modifier.no_wsuf)
4218 i.suffix = 0;
4219 else if (!check_word_reg ())
29b0f896
AM		 4220 return 0;
4221 }
c0f3af97
L		 4222 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4223 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4224 {
c0f3af97 4225 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4226 should check if it is a valid suffix. */
4227 }
40fb9820 4228 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4229 /* Do nothing if the instruction is going to ignore the prefix. */
4230 ;
4231 else
4232 abort ();
4233 }
40fb9820 4234 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4235 && !i.suffix
4236 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4237 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4238 {
4239 i.suffix = stackop_size;
4240 }
9306ca4a
JB		 4241 else if (intel_syntax
4242 && !i.suffix
40fb9820
L		 4243 && (i.tm.operand_types[0].bitfield.jumpabsolute
4244 || i.tm.opcode_modifier.jumpbyte
4245 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4246 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4247 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4248 {
4249 switch (flag_code)
4250 {
4251 case CODE_64BIT:
40fb9820 4252 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4253 {
4254 i.suffix = QWORD_MNEM_SUFFIX;
4255 break;
4256 }
4257 case CODE_32BIT:
40fb9820 4258 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4259 i.suffix = LONG_MNEM_SUFFIX;
4260 break;
4261 case CODE_16BIT:
40fb9820 4262 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4263 i.suffix = WORD_MNEM_SUFFIX;
4264 break;
4265 }
4266 }
252b5132 4267
9306ca4a 4268 if (!i.suffix)
29b0f896 4269 {
9306ca4a
JB		 4270 if (!intel_syntax)
4271 {
40fb9820 4272 if (i.tm.opcode_modifier.w)
9306ca4a 4273 {
4eed87de
AM		 4274 as_bad (_("no instruction mnemonic suffix given and "
4275 "no register operands; can't size instruction"));
9306ca4a
JB		 4276 return 0;
4277 }
4278 }
4279 else
4280 {
40fb9820 4281 unsigned int suffixes;
7ab9ffdd 4282
40fb9820
L		 4283 suffixes = !i.tm.opcode_modifier.no_bsuf;
4284 if (!i.tm.opcode_modifier.no_wsuf)
4285 suffixes |= 1 << 1;
4286 if (!i.tm.opcode_modifier.no_lsuf)
4287 suffixes |= 1 << 2;
fc4adea1 4288 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4289 suffixes |= 1 << 3;
4290 if (!i.tm.opcode_modifier.no_ssuf)
4291 suffixes |= 1 << 4;
4292 if (!i.tm.opcode_modifier.no_qsuf)
4293 suffixes |= 1 << 5;
4294
4295 /* There are more than suffix matches. */
4296 if (i.tm.opcode_modifier.w
9306ca4a 4297 || ((suffixes & (suffixes - 1))
40fb9820
L		 4298 && !i.tm.opcode_modifier.defaultsize
4299 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4300 {
4301 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4302 return 0;
4303 }
4304 }
29b0f896 4305 }
252b5132 4306
9306ca4a
JB		 4307 /* Change the opcode based on the operand size given by i.suffix;
4308 We don't need to change things for byte insns. */
4309
582d5edd
L		 4310 if (i.suffix
4311 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4312 && i.suffix != XMMWORD_MNEM_SUFFIX
4313 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4314 {
4315 /* It's not a byte, select word/dword operation. */
40fb9820 4316 if (i.tm.opcode_modifier.w)
29b0f896 4317 {
40fb9820 4318 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4319 i.tm.base_opcode |= 8;
4320 else
4321 i.tm.base_opcode |= 1;
4322 }
0f3f3d8b 4323
29b0f896
AM		 4324 /* Now select between word & dword operations via the operand
4325 size prefix, except for instructions that will ignore this
4326 prefix anyway. */
ca61edf2 4327 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4328 {
ca61edf2
L		 4329 /* The address size override prefix changes the size of the
4330 first operand. */
40fb9820
L		 4331 if ((flag_code == CODE_32BIT
4332 && i.op->regs[0].reg_type.bitfield.reg16)
4333 || (flag_code != CODE_32BIT
4334 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4335 if (!add_prefix (ADDR_PREFIX_OPCODE))
4336 return 0;
4337 }
4338 else if (i.suffix != QWORD_MNEM_SUFFIX
4339 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4340 && !i.tm.opcode_modifier.ignoresize
4341 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4342 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4343 || (flag_code == CODE_64BIT
40fb9820 4344 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4345 {
4346 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4347
40fb9820 4348 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4349 prefix = ADDR_PREFIX_OPCODE;
252b5132 4350
29b0f896
AM		 4351 if (!add_prefix (prefix))
4352 return 0;
24eab124 4353 }
252b5132 4354
29b0f896
AM		 4355 /* Set mode64 for an operand. */
4356 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4357 && flag_code == CODE_64BIT
40fb9820 4358 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4359 {
4360 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4361 need rex64. cmpxchg8b is also a special case. */
4362 if (! (i.operands == 2
4363 && i.tm.base_opcode == 0x90
4364 && i.tm.extension_opcode == None
0dfbf9d7
L		 4365 && operand_type_equal (&i.types [0], &acc64)
4366 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4367 && ! (i.operands == 1
4368 && i.tm.base_opcode == 0xfc7
4369 && i.tm.extension_opcode == 1
40fb9820
L		 4370 && !operand_type_check (i.types [0], reg)
4371 && operand_type_check (i.types [0], anymem)))
f6bee062 4372 i.rex |= REX_W;
46e883c5 4373 }
3e73aa7c 4374
29b0f896
AM		 4375 /* Size floating point instruction. */
4376 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4377 if (i.tm.opcode_modifier.floatmf)
543613e9 4378 i.tm.base_opcode ^= 4;
29b0f896 4379 }
7ecd2f8b 4380
29b0f896
AM		 4381 return 1;
4382}
3e73aa7c 4383
29b0f896 4384static int
543613e9 4385check_byte_reg (void)
29b0f896
AM		 4386{
4387 int op;
543613e9 4388
29b0f896
AM		 4389 for (op = i.operands; --op >= 0;)
4390 {
4391 /* If this is an eight bit register, it's OK. If it's the 16 or
4392 32 bit version of an eight bit register, we will just use the
4393 low portion, and that's OK too. */
40fb9820 4394 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4395 continue;
4396
9344ff29
L		 4397 /* crc32 doesn't generate this warning. */
4398 if (i.tm.base_opcode == 0xf20f38f0)
4399 continue;
4400
40fb9820
L		 4401 if ((i.types[op].bitfield.reg16
4402 || i.types[op].bitfield.reg32
4403 || i.types[op].bitfield.reg64)
4404 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4405 {
4406 /* Prohibit these changes in the 64bit mode, since the
4407 lowering is more complicated. */
4408 if (flag_code == CODE_64BIT
40fb9820 4409 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4410 {
2ca3ace5
L		 4411 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4412 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4413 i.suffix);
4414 return 0;
4415 }
4416#if REGISTER_WARNINGS
4417 if (!quiet_warnings
40fb9820 4418 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4419 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4420 register_prefix,
40fb9820 4421 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4422 ? REGNAM_AL - REGNAM_AX
4423 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4424 register_prefix,
29b0f896
AM		 4425 i.op[op].regs->reg_name,
4426 i.suffix);
4427#endif
4428 continue;
4429 }
4430 /* Any other register is bad. */
40fb9820
L		 4431 if (i.types[op].bitfield.reg16
4432 || i.types[op].bitfield.reg32
4433 || i.types[op].bitfield.reg64
4434 || i.types[op].bitfield.regmmx
4435 || i.types[op].bitfield.regxmm
c0f3af97 4436 || i.types[op].bitfield.regymm
40fb9820
L		 4437 || i.types[op].bitfield.sreg2
4438 || i.types[op].bitfield.sreg3
4439 || i.types[op].bitfield.control
4440 || i.types[op].bitfield.debug
4441 || i.types[op].bitfield.test
4442 || i.types[op].bitfield.floatreg
4443 || i.types[op].bitfield.floatacc)
29b0f896 4444 {
a540244d
L		 4445 as_bad (_("`%s%s' not allowed with `%s%c'"),
4446 register_prefix,
29b0f896
AM		 4447 i.op[op].regs->reg_name,
4448 i.tm.name,
4449 i.suffix);
4450 return 0;
4451 }
4452 }
4453 return 1;
4454}
4455
4456static int
e3bb37b5 4457check_long_reg (void)
29b0f896
AM		 4458{
4459 int op;
4460
4461 for (op = i.operands; --op >= 0;)
4462 /* Reject eight bit registers, except where the template requires
4463 them. (eg. movzb) */
40fb9820
L		 4464 if (i.types[op].bitfield.reg8
4465 && (i.tm.operand_types[op].bitfield.reg16
4466 || i.tm.operand_types[op].bitfield.reg32
4467 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4468 {
a540244d
L		 4469 as_bad (_("`%s%s' not allowed with `%s%c'"),
4470 register_prefix,
29b0f896
AM		 4471 i.op[op].regs->reg_name,
4472 i.tm.name,
4473 i.suffix);
4474 return 0;
4475 }
4476 /* Warn if the e prefix on a general reg is missing. */
4477 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4478 && i.types[op].bitfield.reg16
4479 && (i.tm.operand_types[op].bitfield.reg32
4480 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4481 {
4482 /* Prohibit these changes in the 64bit mode, since the
4483 lowering is more complicated. */
4484 if (flag_code == CODE_64BIT)
252b5132 4485 {
2ca3ace5
L		 4486 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4487 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4488 i.suffix);
4489 return 0;
252b5132 4490 }
29b0f896
AM		 4491#if REGISTER_WARNINGS
4492 else
a540244d
L		 4493 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4494 register_prefix,
29b0f896 4495 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4496 register_prefix,
29b0f896
AM		 4497 i.op[op].regs->reg_name,
4498 i.suffix);
4499#endif
252b5132 4500 }
29b0f896 4501 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4502 else if (i.types[op].bitfield.reg64
4503 && (i.tm.operand_types[op].bitfield.reg32
4504 || i.tm.operand_types[op].bitfield.acc))
252b5132 4505 {
34828aad 4506 if (intel_syntax
ca61edf2 4507 && i.tm.opcode_modifier.toqword
40fb9820 4508 && !i.types[0].bitfield.regxmm)
34828aad 4509 {
ca61edf2 4510 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4511 i.suffix = QWORD_MNEM_SUFFIX;
4512 }
4513 else
4514 {
4515 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4516 register_prefix, i.op[op].regs->reg_name,
4517 i.suffix);
4518 return 0;
4519 }
29b0f896
AM		 4520 }
4521 return 1;
4522}
252b5132 4523
29b0f896 4524static int
e3bb37b5 4525check_qword_reg (void)
29b0f896
AM		 4526{
4527 int op;
252b5132 4528
29b0f896
AM		 4529 for (op = i.operands; --op >= 0; )
4530 /* Reject eight bit registers, except where the template requires
4531 them. (eg. movzb) */
40fb9820
L		 4532 if (i.types[op].bitfield.reg8
4533 && (i.tm.operand_types[op].bitfield.reg16
4534 || i.tm.operand_types[op].bitfield.reg32
4535 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4536 {
a540244d
L		 4537 as_bad (_("`%s%s' not allowed with `%s%c'"),
4538 register_prefix,
29b0f896
AM		 4539 i.op[op].regs->reg_name,
4540 i.tm.name,
4541 i.suffix);
4542 return 0;
4543 }
4544 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4545 else if ((i.types[op].bitfield.reg16
4546 || i.types[op].bitfield.reg32)
4547 && (i.tm.operand_types[op].bitfield.reg32
4548 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4549 {
4550 /* Prohibit these changes in the 64bit mode, since the
4551 lowering is more complicated. */
34828aad 4552 if (intel_syntax
ca61edf2 4553 && i.tm.opcode_modifier.todword
40fb9820 4554 && !i.types[0].bitfield.regxmm)
34828aad 4555 {
ca61edf2 4556 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4557 i.suffix = LONG_MNEM_SUFFIX;
4558 }
4559 else
4560 {
4561 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4562 register_prefix, i.op[op].regs->reg_name,
4563 i.suffix);
4564 return 0;
4565 }
252b5132 4566 }
29b0f896
AM		 4567 return 1;
4568}
252b5132 4569
29b0f896 4570static int
e3bb37b5 4571check_word_reg (void)
29b0f896
AM		 4572{
4573 int op;
4574 for (op = i.operands; --op >= 0;)
4575 /* Reject eight bit registers, except where the template requires
4576 them. (eg. movzb) */
40fb9820
L		 4577 if (i.types[op].bitfield.reg8
4578 && (i.tm.operand_types[op].bitfield.reg16
4579 || i.tm.operand_types[op].bitfield.reg32
4580 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4581 {
a540244d
L		 4582 as_bad (_("`%s%s' not allowed with `%s%c'"),
4583 register_prefix,
29b0f896
AM		 4584 i.op[op].regs->reg_name,
4585 i.tm.name,
4586 i.suffix);
4587 return 0;
4588 }
4589 /* Warn if the e prefix on a general reg is present. */
4590 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4591 && i.types[op].bitfield.reg32
4592 && (i.tm.operand_types[op].bitfield.reg16
4593 || i.tm.operand_types[op].bitfield.acc))
252b5132 4594 {
29b0f896
AM		 4595 /* Prohibit these changes in the 64bit mode, since the
4596 lowering is more complicated. */
4597 if (flag_code == CODE_64BIT)
252b5132 4598 {
2ca3ace5
L		 4599 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4600 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4601 i.suffix);
4602 return 0;
252b5132 4603 }
29b0f896
AM		 4604 else
4605#if REGISTER_WARNINGS
a540244d
L		 4606 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4607 register_prefix,
29b0f896 4608 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4609 register_prefix,
29b0f896
AM		 4610 i.op[op].regs->reg_name,
4611 i.suffix);
4612#endif
4613 }
4614 return 1;
4615}
252b5132 4616
29b0f896 4617static int
40fb9820 4618update_imm (unsigned int j)
29b0f896 4619{
bc0844ae 4620 i386_operand_type overlap = i.types[j];
40fb9820
L		 4621 if ((overlap.bitfield.imm8
4622 || overlap.bitfield.imm8s
4623 || overlap.bitfield.imm16
4624 || overlap.bitfield.imm32
4625 || overlap.bitfield.imm32s
4626 || overlap.bitfield.imm64)
0dfbf9d7
L		 4627 && !operand_type_equal (&overlap, &imm8)
4628 && !operand_type_equal (&overlap, &imm8s)
4629 && !operand_type_equal (&overlap, &imm16)
4630 && !operand_type_equal (&overlap, &imm32)
4631 && !operand_type_equal (&overlap, &imm32s)
4632 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4633 {
4634 if (i.suffix)
4635 {
40fb9820
L		 4636 i386_operand_type temp;
4637
0dfbf9d7 4638 operand_type_set (&temp, 0);
7ab9ffdd 4639 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4640 {
4641 temp.bitfield.imm8 = overlap.bitfield.imm8;
4642 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4643 }
4644 else if (i.suffix == WORD_MNEM_SUFFIX)
4645 temp.bitfield.imm16 = overlap.bitfield.imm16;
4646 else if (i.suffix == QWORD_MNEM_SUFFIX)
4647 {
4648 temp.bitfield.imm64 = overlap.bitfield.imm64;
4649 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4650 }
4651 else
4652 temp.bitfield.imm32 = overlap.bitfield.imm32;
4653 overlap = temp;
29b0f896 4654 }
0dfbf9d7
L		 4655 else if (operand_type_equal (&overlap, &imm16_32_32s)
4656 || operand_type_equal (&overlap, &imm16_32)
4657 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4658 {
40fb9820 4659 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4660 overlap = imm16;
40fb9820 4661 else
65da13b5 4662 overlap = imm32s;
29b0f896 4663 }
0dfbf9d7
L		 4664 if (!operand_type_equal (&overlap, &imm8)
4665 && !operand_type_equal (&overlap, &imm8s)
4666 && !operand_type_equal (&overlap, &imm16)
4667 && !operand_type_equal (&overlap, &imm32)
4668 && !operand_type_equal (&overlap, &imm32s)
4669 && !operand_type_equal (&overlap, &imm64))
29b0f896 4670 {
4eed87de
AM		 4671 as_bad (_("no instruction mnemonic suffix given; "
4672 "can't determine immediate size"));
29b0f896
AM		 4673 return 0;
4674 }
4675 }
40fb9820 4676 i.types[j] = overlap;
29b0f896 4677
40fb9820
L		 4678 return 1;
4679}
4680
4681static int
4682finalize_imm (void)
4683{
bc0844ae 4684 unsigned int j, n;
29b0f896 4685
bc0844ae
L		 4686 /* Update the first 2 immediate operands. */
4687 n = i.operands > 2 ? 2 : i.operands;
4688 if (n)
4689 {
4690 for (j = 0; j < n; j++)
4691 if (update_imm (j) == 0)
4692 return 0;
40fb9820 4693
bc0844ae
L		 4694 /* The 3rd operand can't be immediate operand. */
4695 gas_assert (operand_type_check (i.types[2], imm) == 0);
4696 }
29b0f896
AM		 4697
4698 return 1;
4699}
4700
c0f3af97
L		 4701static int
4702bad_implicit_operand (int xmm)
4703{
91d6fa6a
NC		 4704 const char *ireg = xmm ? "xmm0" : "ymm0";
4705
c0f3af97
L		 4706 if (intel_syntax)
4707 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 4708 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4709 else
4710 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 4711 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4712 return 0;
4713}
4714
29b0f896 4715static int
e3bb37b5 4716process_operands (void)
29b0f896
AM		 4717{
4718 /* Default segment register this instruction will use for memory
4719 accesses. 0 means unknown. This is only for optimizing out
4720 unnecessary segment overrides. */
4721 const seg_entry *default_seg = 0;
4722
2426c15f 4723 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 4724 {
91d6fa6a
NC		 4725 unsigned int dupl = i.operands;
4726 unsigned int dest = dupl - 1;
9fcfb3d7
L		 4727 unsigned int j;
4728
c0f3af97 4729 /* The destination must be an xmm register. */
9c2799c2 4730 gas_assert (i.reg_operands
91d6fa6a 4731 && MAX_OPERANDS > dupl
7ab9ffdd 4732 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4733
4734 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4735 {
c0f3af97 4736 /* The first operand is implicit and must be xmm0. */
9c2799c2 4737 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4738 if (i.op[0].regs->reg_num != 0)
4739 return bad_implicit_operand (1);
4740
8cd7925b 4741 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 4742 {
4743 /* Keep xmm0 for instructions with VEX prefix and 3
4744 sources. */
4745 goto duplicate;
4746 }
e2ec9d29 4747 else
c0f3af97
L		 4748 {
4749 /* We remove the first xmm0 and keep the number of
4750 operands unchanged, which in fact duplicates the
4751 destination. */
4752 for (j = 1; j < i.operands; j++)
4753 {
4754 i.op[j - 1] = i.op[j];
4755 i.types[j - 1] = i.types[j];
4756 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4757 }
4758 }
4759 }
4760 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 4761 {
91d6fa6a 4762 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 4763 && (i.tm.opcode_modifier.vexsources
4764 == VEX3SOURCES));
c0f3af97
L		 4765
4766 /* Add the implicit xmm0 for instructions with VEX prefix
4767 and 3 sources. */
4768 for (j = i.operands; j > 0; j--)
4769 {
4770 i.op[j] = i.op[j - 1];
4771 i.types[j] = i.types[j - 1];
4772 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4773 }
4774 i.op[0].regs
4775 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 4776 i.types[0] = regxmm;
c0f3af97
L		 4777 i.tm.operand_types[0] = regxmm;
4778
4779 i.operands += 2;
4780 i.reg_operands += 2;
4781 i.tm.operands += 2;
4782
91d6fa6a 4783 dupl++;
c0f3af97 4784 dest++;
91d6fa6a
NC		 4785 i.op[dupl] = i.op[dest];
4786 i.types[dupl] = i.types[dest];
4787 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 4788 }
c0f3af97
L		 4789 else
4790 {
4791duplicate:
4792 i.operands++;
4793 i.reg_operands++;
4794 i.tm.operands++;
4795
91d6fa6a
NC		 4796 i.op[dupl] = i.op[dest];
4797 i.types[dupl] = i.types[dest];
4798 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 4799 }
4800
4801 if (i.tm.opcode_modifier.immext)
4802 process_immext ();
4803 }
4804 else if (i.tm.opcode_modifier.firstxmm0)
4805 {
4806 unsigned int j;
4807
4808 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 4809 gas_assert (i.reg_operands
7ab9ffdd
L		 4810 && (operand_type_equal (&i.types[0], &regxmm)
4811 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 4812 if (i.op[0].regs->reg_num != 0)
4813 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4814
4815 for (j = 1; j < i.operands; j++)
4816 {
4817 i.op[j - 1] = i.op[j];
4818 i.types[j - 1] = i.types[j];
4819
4820 /* We need to adjust fields in i.tm since they are used by
4821 build_modrm_byte. */
4822 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4823 }
4824
e2ec9d29
L		 4825 i.operands--;
4826 i.reg_operands--;
e2ec9d29
L		 4827 i.tm.operands--;
4828 }
4829 else if (i.tm.opcode_modifier.regkludge)
4830 {
4831 /* The imul $imm, %reg instruction is converted into
4832 imul $imm, %reg, %reg, and the clr %reg instruction
4833 is converted into xor %reg, %reg. */
4834
4835 unsigned int first_reg_op;
4836
4837 if (operand_type_check (i.types[0], reg))
4838 first_reg_op = 0;
4839 else
4840 first_reg_op = 1;
4841 /* Pretend we saw the extra register operand. */
9c2799c2 4842 gas_assert (i.reg_operands == 1
7ab9ffdd 4843 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 4844 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4845 i.types[first_reg_op + 1] = i.types[first_reg_op];
4846 i.operands++;
4847 i.reg_operands++;
29b0f896
AM		 4848 }
4849
40fb9820 4850 if (i.tm.opcode_modifier.shortform)
29b0f896 4851 {
40fb9820
L		 4852 if (i.types[0].bitfield.sreg2
4853 || i.types[0].bitfield.sreg3)
29b0f896 4854 {
4eed87de
AM		 4855 if (i.tm.base_opcode == POP_SEG_SHORT
4856 && i.op[0].regs->reg_num == 1)
29b0f896 4857 {
a87af027 4858 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 4859 return 0;
29b0f896 4860 }
4eed87de
AM		 4861 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4862 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4863 i.rex |= REX_B;
4eed87de
AM		 4864 }
4865 else
4866 {
7ab9ffdd 4867 /* The register or float register operand is in operand
85f10a01 4868 0 or 1. */
40fb9820 4869 unsigned int op;
7ab9ffdd
L		 4870
4871 if (i.types[0].bitfield.floatreg
4872 || operand_type_check (i.types[0], reg))
4873 op = 0;
4874 else
4875 op = 1;
4eed87de
AM		 4876 /* Register goes in low 3 bits of opcode. */
4877 i.tm.base_opcode |= i.op[op].regs->reg_num;
4878 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4879 i.rex |= REX_B;
40fb9820 4880 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4881 {
4eed87de
AM		 4882 /* Warn about some common errors, but press on regardless.
4883 The first case can be generated by gcc (<= 2.8.1). */
4884 if (i.operands == 2)
4885 {
4886 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 4887 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 4888 register_prefix, i.op[!intel_syntax].regs->reg_name,
4889 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 4890 }
4891 else
4892 {
4893 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4894 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4895 register_prefix, i.op[0].regs->reg_name);
4eed87de 4896 }
29b0f896
AM		 4897 }
4898 }
4899 }
40fb9820 4900 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4901 {
4902 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4903 must be put into the modrm byte). Now, we make the modrm and
4904 index base bytes based on all the info we've collected. */
29b0f896
AM		 4905
4906 default_seg = build_modrm_byte ();
4907 }
8a2ed489 4908 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4909 {
4910 default_seg = &ds;
4911 }
40fb9820 4912 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4913 {
4914 /* For the string instructions that allow a segment override
4915 on one of their operands, the default segment is ds. */
4916 default_seg = &ds;
4917 }
4918
75178d9d
L		 4919 if (i.tm.base_opcode == 0x8d /* lea */
4920 && i.seg[0]
4921 && !quiet_warnings)
30123838 4922 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4923
4924 /* If a segment was explicitly specified, and the specified segment
4925 is not the default, use an opcode prefix to select it. If we
4926 never figured out what the default segment is, then default_seg
4927 will be zero at this point, and the specified segment prefix will
4928 always be used. */
29b0f896
AM		 4929 if ((i.seg[0]) && (i.seg[0] != default_seg))
4930 {
4931 if (!add_prefix (i.seg[0]->seg_prefix))
4932 return 0;
4933 }
4934 return 1;
4935}
4936
4937static const seg_entry *
e3bb37b5 4938build_modrm_byte (void)
29b0f896
AM		 4939{
4940 const seg_entry *default_seg = 0;
c0f3af97 4941 unsigned int source, dest;
8cd7925b 4942 int vex_3_sources;
c0f3af97
L		 4943
4944 /* The first operand of instructions with VEX prefix and 3 sources
4945 must be VEX_Imm4. */
8cd7925b 4946 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 4947 if (vex_3_sources)
4948 {
91d6fa6a 4949 unsigned int nds, reg_slot;
4c2c6516 4950 expressionS *exp;
c0f3af97 4951
922d8de8
DR		 4952 if (i.tm.opcode_modifier.veximmext
4953 && i.tm.opcode_modifier.immext)
4954 {
4955 dest = i.operands - 2;
4956 gas_assert (dest == 3);
4957 }
4958 else
91d6fa6a 4959 dest = i.operands - 1;
c0f3af97 4960 nds = dest - 1;
922d8de8 4961
76ba9986
L		 4962 /* This instruction must have 4 register operands
4963 or 3 register operands plus 1 memory operand.
922d8de8
DR		 4964 It must have VexNDS and VexImmExt. */
4965 gas_assert ((i.reg_operands == 4
7ab9ffdd 4966 || (i.reg_operands == 3 && i.mem_operands == 1))
2426c15f 4967 && i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 4968 && i.tm.opcode_modifier.veximmext
922d8de8
DR		 4969 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
4970 || operand_type_equal (&i.tm.operand_types[dest], &regymm)));
c0f3af97 4971
0bfee649
L		 4972 /* Generate an 8bit immediate operand to encode the register
4973 operand. */
4c2c6516 4974 exp = &im_expressions[i.imm_operands++];
0bfee649
L		 4975 i.op[i.operands].imms = exp;
4976 i.types[i.operands] = imm8;
4977 i.operands++;
922d8de8
DR		 4978 /* If VexW1 is set, the first operand is the source and
4979 the second operand is encoded in the immediate operand. */
1ef99a7b 4980 if (i.tm.opcode_modifier.vexw == VEXW1)
922d8de8
DR		 4981 {
4982 source = 0;
91d6fa6a 4983 reg_slot = 1;
922d8de8
DR		 4984 }
4985 else
4986 {
4987 source = 1;
91d6fa6a 4988 reg_slot = 0;
76ba9986 4989 }
91d6fa6a
NC		 4990 gas_assert ((operand_type_equal (&i.tm.operand_types[reg_slot], &regxmm)
4991 || operand_type_equal (&i.tm.operand_types[reg_slot],
76ba9986 4992 &regymm))
922d8de8 4993 && (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
76ba9986 4994 || operand_type_equal (&i.tm.operand_types[nds],
922d8de8 4995 &regymm)));
0bfee649
L		 4996 exp->X_op = O_constant;
4997 exp->X_add_number
91d6fa6a
NC		 4998 = ((i.op[reg_slot].regs->reg_num
4999 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
dae39acc 5000 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5001 }
5002 else
5003 source = dest = 0;
29b0f896
AM		 5004
5005 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5006 implicit registers do not count. If there are 3 register
5007 operands, it must be a instruction with VexNDS. For a
5008 instruction with VexNDD, the destination register is encoded
5009 in VEX prefix. If there are 4 register operands, it must be
5010 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5011 if (i.mem_operands == 0
5012 && ((i.reg_operands == 2
2426c15f 5013 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5014 || (i.reg_operands == 3
2426c15f 5015 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5016 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5017 {
cab737b9
L		 5018 switch (i.operands)
5019 {
5020 case 2:
5021 source = 0;
5022 break;
5023 case 3:
c81128dc
L		 5024 /* When there are 3 operands, one of them may be immediate,
5025 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5026 the first operand must be shift count register (cl) or it
5027 is an instruction with VexNDS. */
9c2799c2 5028 gas_assert (i.imm_operands == 1
7ab9ffdd 5029 || (i.imm_operands == 0
2426c15f 5030 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 5031 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5032 if (operand_type_check (i.types[0], imm)
5033 || i.types[0].bitfield.shiftcount)
5034 source = 1;
5035 else
5036 source = 0;
cab737b9
L		 5037 break;
5038 case 4:
368d64cc
L		 5039 /* When there are 4 operands, the first two must be 8bit
5040 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5041 one.
5042
5043 For instructions with VexNDS, if the first operand
5044 an imm8, the source operand is the 2nd one. If the last
5045 operand is imm8, the source operand is the first one. */
9c2799c2 5046 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5047 && i.types[0].bitfield.imm8
5048 && i.types[1].bitfield.imm8)
2426c15f 5049 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 5050 && i.imm_operands == 1
5051 && (i.types[0].bitfield.imm8
5052 || i.types[i.operands - 1].bitfield.imm8)));
2426c15f 5053 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5054 {
5055 if (i.types[0].bitfield.imm8)
5056 source = 1;
5057 else
5058 source = 0;
5059 }
5060 else
5061 source = 2;
5062 break;
5063 case 5:
cab737b9
L		 5064 break;
5065 default:
5066 abort ();
5067 }
5068
c0f3af97
L		 5069 if (!vex_3_sources)
5070 {
5071 dest = source + 1;
5072
2426c15f 5073 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5074 {
5075 /* For instructions with VexNDS, the register-only
5076 source operand must be XMM or YMM register. It is
fa99fab2
L		 5077 encoded in VEX prefix. We need to clear RegMem bit
5078 before calling operand_type_equal. */
5079 i386_operand_type op = i.tm.operand_types[dest];
5080 op.bitfield.regmem = 0;
c0f3af97 5081 if ((dest + 1) >= i.operands
fa99fab2
L		 5082 || (!operand_type_equal (&op, &regxmm)
5083 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 5084 abort ();
5085 i.vex.register_specifier = i.op[dest].regs;
5086 dest++;
5087 }
5088 }
29b0f896
AM		 5089
5090 i.rm.mode = 3;
5091 /* One of the register operands will be encoded in the i.tm.reg
5092 field, the other in the combined i.tm.mode and i.tm.regmem
5093 fields. If no form of this instruction supports a memory
5094 destination operand, then we assume the source operand may
5095 sometimes be a memory operand and so we need to store the
5096 destination in the i.rm.reg field. */
40fb9820
L		 5097 if (!i.tm.operand_types[dest].bitfield.regmem
5098 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5099 {
5100 i.rm.reg = i.op[dest].regs->reg_num;
5101 i.rm.regmem = i.op[source].regs->reg_num;
5102 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5103 i.rex |= REX_R;
29b0f896 5104 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5105 i.rex |= REX_B;
29b0f896
AM		 5106 }
5107 else
5108 {
5109 i.rm.reg = i.op[source].regs->reg_num;
5110 i.rm.regmem = i.op[dest].regs->reg_num;
5111 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5112 i.rex |= REX_B;
29b0f896 5113 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5114 i.rex |= REX_R;
29b0f896 5115 }
161a04f6 5116 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5117 {
40fb9820
L		 5118 if (!i.types[0].bitfield.control
5119 && !i.types[1].bitfield.control)
c4a530c5 5120 abort ();
161a04f6 5121 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5122 add_prefix (LOCK_PREFIX_OPCODE);
5123 }
29b0f896
AM		 5124 }
5125 else
5126 { /* If it's not 2 reg operands... */
c0f3af97
L		 5127 unsigned int mem;
5128
29b0f896
AM		 5129 if (i.mem_operands)
5130 {
5131 unsigned int fake_zero_displacement = 0;
99018f42 5132 unsigned int op;
4eed87de 5133
7ab9ffdd
L		 5134 for (op = 0; op < i.operands; op++)
5135 if (operand_type_check (i.types[op], anymem))
5136 break;
7ab9ffdd 5137 gas_assert (op < i.operands);
29b0f896
AM		 5138
5139 default_seg = &ds;
5140
5141 if (i.base_reg == 0)
5142 {
5143 i.rm.mode = 0;
5144 if (!i.disp_operands)
5145 fake_zero_displacement = 1;
5146 if (i.index_reg == 0)
5147 {
5148 /* Operand is just <disp> */
20f0a1fc 5149 if (flag_code == CODE_64BIT)
29b0f896
AM		 5150 {
5151 /* 64bit mode overwrites the 32bit absolute
5152 addressing by RIP relative addressing and
5153 absolute addressing is encoded by one of the
5154 redundant SIB forms. */
5155 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5156 i.sib.base = NO_BASE_REGISTER;
5157 i.sib.index = NO_INDEX_REGISTER;
fc225355 5158 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5159 ? disp32s : disp32);
20f0a1fc 5160 }
fc225355
L		 5161 else if ((flag_code == CODE_16BIT)
5162 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5163 {
5164 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5165 i.types[op] = disp16;
20f0a1fc
NC		 5166 }
5167 else
5168 {
5169 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5170 i.types[op] = disp32;
29b0f896
AM		 5171 }
5172 }
5173 else /* !i.base_reg && i.index_reg */
5174 {
db51cc60
L		 5175 if (i.index_reg->reg_num == RegEiz
5176 || i.index_reg->reg_num == RegRiz)
5177 i.sib.index = NO_INDEX_REGISTER;
5178 else
5179 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5180 i.sib.base = NO_BASE_REGISTER;
5181 i.sib.scale = i.log2_scale_factor;
5182 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5183 i.types[op].bitfield.disp8 = 0;
5184 i.types[op].bitfield.disp16 = 0;
5185 i.types[op].bitfield.disp64 = 0;
29b0f896 5186 if (flag_code != CODE_64BIT)
40fb9820
L		 5187 {
5188 /* Must be 32 bit */
5189 i.types[op].bitfield.disp32 = 1;
5190 i.types[op].bitfield.disp32s = 0;
5191 }
29b0f896 5192 else
40fb9820
L		 5193 {
5194 i.types[op].bitfield.disp32 = 0;
5195 i.types[op].bitfield.disp32s = 1;
5196 }
29b0f896 5197 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5198 i.rex |= REX_X;
29b0f896
AM		 5199 }
5200 }
5201 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5202 else if (i.base_reg->reg_num == RegRip ||
5203 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5204 {
5205 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5206 i.types[op].bitfield.disp8 = 0;
5207 i.types[op].bitfield.disp16 = 0;
5208 i.types[op].bitfield.disp32 = 0;
5209 i.types[op].bitfield.disp32s = 1;
5210 i.types[op].bitfield.disp64 = 0;
71903a11 5211 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5212 if (! i.disp_operands)
5213 fake_zero_displacement = 1;
29b0f896 5214 }
40fb9820 5215 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5216 {
5217 switch (i.base_reg->reg_num)
5218 {
5219 case 3: /* (%bx) */
5220 if (i.index_reg == 0)
5221 i.rm.regmem = 7;
5222 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5223 i.rm.regmem = i.index_reg->reg_num - 6;
5224 break;
5225 case 5: /* (%bp) */
5226 default_seg = &ss;
5227 if (i.index_reg == 0)
5228 {
5229 i.rm.regmem = 6;
40fb9820 5230 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5231 {
5232 /* fake (%bp) into 0(%bp) */
40fb9820 5233 i.types[op].bitfield.disp8 = 1;
252b5132 5234 fake_zero_displacement = 1;
29b0f896
AM		 5235 }
5236 }
5237 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5238 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5239 break;
5240 default: /* (%si) -> 4 or (%di) -> 5 */
5241 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5242 }
5243 i.rm.mode = mode_from_disp_size (i.types[op]);
5244 }
5245 else /* i.base_reg and 32/64 bit mode */
5246 {
5247 if (flag_code == CODE_64BIT
40fb9820
L		 5248 && operand_type_check (i.types[op], disp))
5249 {
5250 i386_operand_type temp;
0dfbf9d7 5251 operand_type_set (&temp, 0);
40fb9820
L		 5252 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5253 i.types[op] = temp;
5254 if (i.prefix[ADDR_PREFIX] == 0)
5255 i.types[op].bitfield.disp32s = 1;
5256 else
5257 i.types[op].bitfield.disp32 = 1;
5258 }
20f0a1fc 5259
29b0f896
AM		 5260 i.rm.regmem = i.base_reg->reg_num;
5261 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5262 i.rex |= REX_B;
29b0f896
AM		 5263 i.sib.base = i.base_reg->reg_num;
5264 /* x86-64 ignores REX prefix bit here to avoid decoder
5265 complications. */
5266 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5267 {
5268 default_seg = &ss;
5269 if (i.disp_operands == 0)
5270 {
5271 fake_zero_displacement = 1;
40fb9820 5272 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5273 }
5274 }
5275 else if (i.base_reg->reg_num == ESP_REG_NUM)
5276 {
5277 default_seg = &ss;
5278 }
5279 i.sib.scale = i.log2_scale_factor;
5280 if (i.index_reg == 0)
5281 {
5282 /* <disp>(%esp) becomes two byte modrm with no index
5283 register. We've already stored the code for esp
5284 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5285 Any base register besides %esp will not use the
5286 extra modrm byte. */
5287 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5288 }
5289 else
5290 {
db51cc60
L		 5291 if (i.index_reg->reg_num == RegEiz
5292 || i.index_reg->reg_num == RegRiz)
5293 i.sib.index = NO_INDEX_REGISTER;
5294 else
5295 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5296 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5297 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5298 i.rex |= REX_X;
29b0f896 5299 }
67a4f2b7
AO		 5300
5301 if (i.disp_operands
5302 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5303 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5304 i.rm.mode = 0;
5305 else
5306 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5307 }
252b5132 5308
29b0f896
AM		 5309 if (fake_zero_displacement)
5310 {
5311 /* Fakes a zero displacement assuming that i.types[op]
5312 holds the correct displacement size. */
5313 expressionS *exp;
5314
9c2799c2 5315 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5316 exp = &disp_expressions[i.disp_operands++];
5317 i.op[op].disps = exp;
5318 exp->X_op = O_constant;
5319 exp->X_add_number = 0;
5320 exp->X_add_symbol = (symbolS *) 0;
5321 exp->X_op_symbol = (symbolS *) 0;
5322 }
c0f3af97
L		 5323
5324 mem = op;
29b0f896 5325 }
c0f3af97
L		 5326 else
5327 mem = ~0;
252b5132 5328
8c43a48b 5329 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5330 {
5331 if (operand_type_check (i.types[0], imm))
5332 i.vex.register_specifier = NULL;
5333 else
5334 {
5335 /* VEX.vvvv encodes one of the sources when the first
5336 operand is not an immediate. */
1ef99a7b 5337 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5338 i.vex.register_specifier = i.op[0].regs;
5339 else
5340 i.vex.register_specifier = i.op[1].regs;
5341 }
5342
5343 /* Destination is a XMM register encoded in the ModRM.reg
5344 and VEX.R bit. */
5345 i.rm.reg = i.op[2].regs->reg_num;
5346 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5347 i.rex |= REX_R;
5348
5349 /* ModRM.rm and VEX.B encodes the other source. */
5350 if (!i.mem_operands)
5351 {
5352 i.rm.mode = 3;
5353
1ef99a7b 5354 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5355 i.rm.regmem = i.op[1].regs->reg_num;
5356 else
5357 i.rm.regmem = i.op[0].regs->reg_num;
5358
5359 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5360 i.rex |= REX_B;
5361 }
5362 }
2426c15f 5363 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 5364 {
5365 i.vex.register_specifier = i.op[2].regs;
5366 if (!i.mem_operands)
5367 {
5368 i.rm.mode = 3;
5369 i.rm.regmem = i.op[1].regs->reg_num;
5370 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5371 i.rex |= REX_B;
5372 }
5373 }
29b0f896
AM		 5374 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5375 (if any) based on i.tm.extension_opcode. Again, we must be
5376 careful to make sure that segment/control/debug/test/MMX
5377 registers are coded into the i.rm.reg field. */
f88c9eb0 5378 else if (i.reg_operands)
29b0f896 5379 {
99018f42 5380 unsigned int op;
7ab9ffdd
L		 5381 unsigned int vex_reg = ~0;
5382
5383 for (op = 0; op < i.operands; op++)
5384 if (i.types[op].bitfield.reg8
5385 || i.types[op].bitfield.reg16
5386 || i.types[op].bitfield.reg32
5387 || i.types[op].bitfield.reg64
5388 || i.types[op].bitfield.regmmx
5389 || i.types[op].bitfield.regxmm
5390 || i.types[op].bitfield.regymm
5391 || i.types[op].bitfield.sreg2
5392 || i.types[op].bitfield.sreg3
5393 || i.types[op].bitfield.control
5394 || i.types[op].bitfield.debug
5395 || i.types[op].bitfield.test)
5396 break;
c0209578 5397
7ab9ffdd
L		 5398 if (vex_3_sources)
5399 op = dest;
2426c15f 5400 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 5401 {
5402 /* For instructions with VexNDS, the register-only
5403 source operand is encoded in VEX prefix. */
5404 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5405
7ab9ffdd 5406 if (op > mem)
c0f3af97 5407 {
7ab9ffdd
L		 5408 vex_reg = op++;
5409 gas_assert (op < i.operands);
c0f3af97
L		 5410 }
5411 else
c0f3af97 5412 {
7ab9ffdd
L		 5413 vex_reg = op + 1;
5414 gas_assert (vex_reg < i.operands);
c0f3af97 5415 }
7ab9ffdd 5416 }
2426c15f 5417 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd
L		 5418 {
5419 /* For instructions with VexNDD, there should be
5420 no memory operand and the register destination
5421 is encoded in VEX prefix. */
5422 gas_assert (i.mem_operands == 0
5423 && (op + 2) == i.operands);
5424 vex_reg = op + 1;
5425 }
5426 else
5427 gas_assert (op < i.operands);
99018f42 5428
7ab9ffdd
L		 5429 if (vex_reg != (unsigned int) ~0)
5430 {
5431 gas_assert (i.reg_operands == 2);
5432
5433 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
76ba9986 5434 &regxmm)
7ab9ffdd
L		 5435 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5436 &regymm))
5437 abort ();
f88c9eb0 5438
7ab9ffdd
L		 5439 i.vex.register_specifier = i.op[vex_reg].regs;
5440 }
5441
1b9f0c97
L		 5442 /* Don't set OP operand twice. */
5443 if (vex_reg != op)
7ab9ffdd 5444 {
1b9f0c97
L		 5445 /* If there is an extension opcode to put here, the
5446 register number must be put into the regmem field. */
5447 if (i.tm.extension_opcode != None)
5448 {
5449 i.rm.regmem = i.op[op].regs->reg_num;
5450 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5451 i.rex |= REX_B;
5452 }
5453 else
5454 {
5455 i.rm.reg = i.op[op].regs->reg_num;
5456 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5457 i.rex |= REX_R;
5458 }
7ab9ffdd 5459 }
252b5132 5460
29b0f896
AM		 5461 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5462 must set it to 3 to indicate this is a register operand
5463 in the regmem field. */
5464 if (!i.mem_operands)
5465 i.rm.mode = 3;
5466 }
252b5132 5467
29b0f896 5468 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5469 if (i.tm.extension_opcode != None)
29b0f896
AM		 5470 i.rm.reg = i.tm.extension_opcode;
5471 }
5472 return default_seg;
5473}
252b5132 5474
29b0f896 5475static void
e3bb37b5 5476output_branch (void)
29b0f896
AM		 5477{
5478 char *p;
5479 int code16;
5480 int prefix;
5481 relax_substateT subtype;
5482 symbolS *sym;
5483 offsetT off;
5484
5485 code16 = 0;
5486 if (flag_code == CODE_16BIT)
5487 code16 = CODE16;
5488
5489 prefix = 0;
5490 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5491 {
29b0f896
AM		 5492 prefix = 1;
5493 i.prefixes -= 1;
5494 code16 ^= CODE16;
252b5132 5495 }
29b0f896
AM		 5496 /* Pentium4 branch hints. */
5497 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5498 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5499 {
29b0f896
AM		 5500 prefix++;
5501 i.prefixes--;
5502 }
5503 if (i.prefix[REX_PREFIX] != 0)
5504 {
5505 prefix++;
5506 i.prefixes--;
2f66722d
AM		 5507 }
5508
29b0f896
AM		 5509 if (i.prefixes != 0 && !intel_syntax)
5510 as_warn (_("skipping prefixes on this instruction"));
5511
5512 /* It's always a symbol; End frag & setup for relax.
5513 Make sure there is enough room in this frag for the largest
5514 instruction we may generate in md_convert_frag. This is 2
5515 bytes for the opcode and room for the prefix and largest
5516 displacement. */
5517 frag_grow (prefix + 2 + 4);
5518 /* Prefix and 1 opcode byte go in fr_fix. */
5519 p = frag_more (prefix + 1);
5520 if (i.prefix[DATA_PREFIX] != 0)
5521 *p++ = DATA_PREFIX_OPCODE;
5522 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5523 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5524 *p++ = i.prefix[SEG_PREFIX];
5525 if (i.prefix[REX_PREFIX] != 0)
5526 *p++ = i.prefix[REX_PREFIX];
5527 *p = i.tm.base_opcode;
5528
5529 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5530 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5531 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5532 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5533 else
5534 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5535 subtype |= code16;
3e73aa7c 5536
29b0f896
AM		 5537 sym = i.op[0].disps->X_add_symbol;
5538 off = i.op[0].disps->X_add_number;
3e73aa7c 5539
29b0f896
AM		 5540 if (i.op[0].disps->X_op != O_constant
5541 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5542 {
29b0f896
AM		 5543 /* Handle complex expressions. */
5544 sym = make_expr_symbol (i.op[0].disps);
5545 off = 0;
5546 }
3e73aa7c 5547
29b0f896
AM		 5548 /* 1 possible extra opcode + 4 byte displacement go in var part.
5549 Pass reloc in fr_var. */
5550 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5551}
3e73aa7c 5552
29b0f896 5553static void
e3bb37b5 5554output_jump (void)
29b0f896
AM		 5555{
5556 char *p;
5557 int size;
3e02c1cc 5558 fixS *fixP;
29b0f896 5559
40fb9820 5560 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5561 {
5562 /* This is a loop or jecxz type instruction. */
5563 size = 1;
5564 if (i.prefix[ADDR_PREFIX] != 0)
5565 {
5566 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5567 i.prefixes -= 1;
5568 }
5569 /* Pentium4 branch hints. */
5570 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5571 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5572 {
5573 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5574 i.prefixes--;
3e73aa7c
JH		 5575 }
5576 }
29b0f896
AM		 5577 else
5578 {
5579 int code16;
3e73aa7c 5580
29b0f896
AM		 5581 code16 = 0;
5582 if (flag_code == CODE_16BIT)
5583 code16 = CODE16;
3e73aa7c 5584
29b0f896
AM		 5585 if (i.prefix[DATA_PREFIX] != 0)
5586 {
5587 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5588 i.prefixes -= 1;
5589 code16 ^= CODE16;
5590 }
252b5132 5591
29b0f896
AM		 5592 size = 4;
5593 if (code16)
5594 size = 2;
5595 }
9fcc94b6 5596
29b0f896
AM		 5597 if (i.prefix[REX_PREFIX] != 0)
5598 {
5599 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5600 i.prefixes -= 1;
5601 }
252b5132 5602
29b0f896
AM		 5603 if (i.prefixes != 0 && !intel_syntax)
5604 as_warn (_("skipping prefixes on this instruction"));
e0890092 5605
29b0f896
AM		 5606 p = frag_more (1 + size);
5607 *p++ = i.tm.base_opcode;
e0890092 5608
3e02c1cc
AM		 5609 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5610 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5611
5612 /* All jumps handled here are signed, but don't use a signed limit
5613 check for 32 and 16 bit jumps as we want to allow wrap around at
5614 4G and 64k respectively. */
5615 if (size == 1)
5616 fixP->fx_signed = 1;
29b0f896 5617}
e0890092 5618
29b0f896 5619static void
e3bb37b5 5620output_interseg_jump (void)
29b0f896
AM		 5621{
5622 char *p;
5623 int size;
5624 int prefix;
5625 int code16;
252b5132 5626
29b0f896
AM		 5627 code16 = 0;
5628 if (flag_code == CODE_16BIT)
5629 code16 = CODE16;
a217f122 5630
29b0f896
AM		 5631 prefix = 0;
5632 if (i.prefix[DATA_PREFIX] != 0)
5633 {
5634 prefix = 1;
5635 i.prefixes -= 1;
5636 code16 ^= CODE16;
5637 }
5638 if (i.prefix[REX_PREFIX] != 0)
5639 {
5640 prefix++;
5641 i.prefixes -= 1;
5642 }
252b5132 5643
29b0f896
AM		 5644 size = 4;
5645 if (code16)
5646 size = 2;
252b5132 5647
29b0f896
AM		 5648 if (i.prefixes != 0 && !intel_syntax)
5649 as_warn (_("skipping prefixes on this instruction"));
252b5132 5650
29b0f896
AM		 5651 /* 1 opcode; 2 segment; offset */
5652 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5653
29b0f896
AM		 5654 if (i.prefix[DATA_PREFIX] != 0)
5655 *p++ = DATA_PREFIX_OPCODE;
252b5132 5656
29b0f896
AM		 5657 if (i.prefix[REX_PREFIX] != 0)
5658 *p++ = i.prefix[REX_PREFIX];
252b5132 5659
29b0f896
AM		 5660 *p++ = i.tm.base_opcode;
5661 if (i.op[1].imms->X_op == O_constant)
5662 {
5663 offsetT n = i.op[1].imms->X_add_number;
252b5132 5664
29b0f896
AM		 5665 if (size == 2
5666 && !fits_in_unsigned_word (n)
5667 && !fits_in_signed_word (n))
5668 {
5669 as_bad (_("16-bit jump out of range"));
5670 return;
5671 }
5672 md_number_to_chars (p, n, size);
5673 }
5674 else
5675 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5676 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5677 if (i.op[0].imms->X_op != O_constant)
5678 as_bad (_("can't handle non absolute segment in `%s'"),
5679 i.tm.name);
5680 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5681}
a217f122 5682
29b0f896 5683static void
e3bb37b5 5684output_insn (void)
29b0f896 5685{
2bbd9c25
JJ		 5686 fragS *insn_start_frag;
5687 offsetT insn_start_off;
5688
29b0f896
AM		 5689 /* Tie dwarf2 debug info to the address at the start of the insn.
5690 We can't do this after the insn has been output as the current
5691 frag may have been closed off. eg. by frag_var. */
5692 dwarf2_emit_insn (0);
5693
2bbd9c25
JJ		 5694 insn_start_frag = frag_now;
5695 insn_start_off = frag_now_fix ();
5696
29b0f896 5697 /* Output jumps. */
40fb9820 5698 if (i.tm.opcode_modifier.jump)
29b0f896 5699 output_branch ();
40fb9820
L		 5700 else if (i.tm.opcode_modifier.jumpbyte
5701 || i.tm.opcode_modifier.jumpdword)
29b0f896 5702 output_jump ();
40fb9820 5703 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5704 output_interseg_jump ();
5705 else
5706 {
5707 /* Output normal instructions here. */
5708 char *p;
5709 unsigned char *q;
47465058 5710 unsigned int j;
331d2d0d 5711 unsigned int prefix;
4dffcebc 5712
c0f3af97
L		 5713 /* Since the VEX prefix contains the implicit prefix, we don't
5714 need the explicit prefix. */
5715 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5716 {
c0f3af97 5717 switch (i.tm.opcode_length)
bc4bd9ab 5718 {
c0f3af97
L		 5719 case 3:
5720 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5721 {
c0f3af97
L		 5722 prefix = (i.tm.base_opcode >> 24) & 0xff;
5723 goto check_prefix;
5724 }
5725 break;
5726 case 2:
5727 if ((i.tm.base_opcode & 0xff0000) != 0)
5728 {
5729 prefix = (i.tm.base_opcode >> 16) & 0xff;
5730 if (i.tm.cpu_flags.bitfield.cpupadlock)
5731 {
4dffcebc 5732check_prefix:
c0f3af97 5733 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 5734 || (i.prefix[REP_PREFIX]
c0f3af97
L		 5735 != REPE_PREFIX_OPCODE))
5736 add_prefix (prefix);
5737 }
5738 else
4dffcebc
L		 5739 add_prefix (prefix);
5740 }
c0f3af97
L		 5741 break;
5742 case 1:
5743 break;
5744 default:
5745 abort ();
bc4bd9ab 5746 }
c0f3af97
L		 5747
5748 /* The prefix bytes. */
5749 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5750 if (*q)
5751 FRAG_APPEND_1_CHAR (*q);
0f10071e 5752 }
252b5132 5753
c0f3af97
L		 5754 if (i.tm.opcode_modifier.vex)
5755 {
5756 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5757 if (*q)
5758 switch (j)
5759 {
5760 case REX_PREFIX:
5761 /* REX byte is encoded in VEX prefix. */
5762 break;
5763 case SEG_PREFIX:
5764 case ADDR_PREFIX:
5765 FRAG_APPEND_1_CHAR (*q);
5766 break;
5767 default:
5768 /* There should be no other prefixes for instructions
5769 with VEX prefix. */
5770 abort ();
5771 }
5772
5773 /* Now the VEX prefix. */
5774 p = frag_more (i.vex.length);
5775 for (j = 0; j < i.vex.length; j++)
5776 p[j] = i.vex.bytes[j];
5777 }
252b5132 5778
29b0f896 5779 /* Now the opcode; be careful about word order here! */
4dffcebc 5780 if (i.tm.opcode_length == 1)
29b0f896
AM		 5781 {
5782 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5783 }
5784 else
5785 {
4dffcebc 5786 switch (i.tm.opcode_length)
331d2d0d 5787 {
4dffcebc 5788 case 3:
331d2d0d
L		 5789 p = frag_more (3);
5790 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5791 break;
5792 case 2:
5793 p = frag_more (2);
5794 break;
5795 default:
5796 abort ();
5797 break;
331d2d0d 5798 }
0f10071e 5799
29b0f896
AM		 5800 /* Put out high byte first: can't use md_number_to_chars! */
5801 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5802 *p = i.tm.base_opcode & 0xff;
5803 }
3e73aa7c 5804
29b0f896 5805 /* Now the modrm byte and sib byte (if present). */
40fb9820 5806 if (i.tm.opcode_modifier.modrm)
29b0f896 5807 {
4a3523fa
L		 5808 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5809 | i.rm.reg << 3
5810 | i.rm.mode << 6));
29b0f896
AM		 5811 /* If i.rm.regmem == ESP (4)
5812 && i.rm.mode != (Register mode)
5813 && not 16 bit
5814 ==> need second modrm byte. */
5815 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5816 && i.rm.mode != 3
40fb9820 5817 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5818 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5819 | i.sib.index << 3
5820 | i.sib.scale << 6));
29b0f896 5821 }
3e73aa7c 5822
29b0f896 5823 if (i.disp_operands)
2bbd9c25 5824 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5825
29b0f896 5826 if (i.imm_operands)
2bbd9c25 5827 output_imm (insn_start_frag, insn_start_off);
29b0f896 5828 }
252b5132 5829
29b0f896
AM		 5830#ifdef DEBUG386
5831 if (flag_debug)
5832 {
7b81dfbb 5833 pi ("" /*line*/, &i);
29b0f896
AM		 5834 }
5835#endif /* DEBUG386 */
5836}
252b5132 5837
e205caa7
L		 5838/* Return the size of the displacement operand N. */
5839
5840static int
5841disp_size (unsigned int n)
5842{
5843 int size = 4;
40fb9820
L		 5844 if (i.types[n].bitfield.disp64)
5845 size = 8;
5846 else if (i.types[n].bitfield.disp8)
5847 size = 1;
5848 else if (i.types[n].bitfield.disp16)
5849 size = 2;
e205caa7
L		 5850 return size;
5851}
5852
5853/* Return the size of the immediate operand N. */
5854
5855static int
5856imm_size (unsigned int n)
5857{
5858 int size = 4;
40fb9820
L		 5859 if (i.types[n].bitfield.imm64)
5860 size = 8;
5861 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5862 size = 1;
5863 else if (i.types[n].bitfield.imm16)
5864 size = 2;
e205caa7
L		 5865 return size;
5866}
5867
29b0f896 5868static void
64e74474 5869output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5870{
5871 char *p;
5872 unsigned int n;
252b5132 5873
29b0f896
AM		 5874 for (n = 0; n < i.operands; n++)
5875 {
40fb9820 5876 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5877 {
5878 if (i.op[n].disps->X_op == O_constant)
5879 {
e205caa7 5880 int size = disp_size (n);
29b0f896 5881 offsetT val;
252b5132 5882
29b0f896
AM		 5883 val = offset_in_range (i.op[n].disps->X_add_number,
5884 size);
5885 p = frag_more (size);
5886 md_number_to_chars (p, val, size);
5887 }
5888 else
5889 {
f86103b7 5890 enum bfd_reloc_code_real reloc_type;
e205caa7 5891 int size = disp_size (n);
40fb9820 5892 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5893 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5894
e205caa7 5895 /* We can't have 8 bit displacement here. */
9c2799c2 5896 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 5897
29b0f896
AM		 5898 /* The PC relative address is computed relative
5899 to the instruction boundary, so in case immediate
5900 fields follows, we need to adjust the value. */
5901 if (pcrel && i.imm_operands)
5902 {
29b0f896 5903 unsigned int n1;
e205caa7 5904 int sz = 0;
252b5132 5905
29b0f896 5906 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5907 if (operand_type_check (i.types[n1], imm))
252b5132 5908 {
e205caa7
L		 5909 /* Only one immediate is allowed for PC
5910 relative address. */
9c2799c2 5911 gas_assert (sz == 0);
e205caa7
L		 5912 sz = imm_size (n1);
5913 i.op[n].disps->X_add_number -= sz;
252b5132 5914 }
29b0f896 5915 /* We should find the immediate. */
9c2799c2 5916 gas_assert (sz != 0);
29b0f896 5917 }
520dc8e8 5918
29b0f896 5919 p = frag_more (size);
2bbd9c25 5920 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5921 if (GOT_symbol
2bbd9c25 5922 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5923 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5924 || reloc_type == BFD_RELOC_X86_64_32S
5925 || (reloc_type == BFD_RELOC_64
5926 && object_64bit))
d6ab8113
JB		 5927 && (i.op[n].disps->X_op == O_symbol
5928 || (i.op[n].disps->X_op == O_add
5929 && ((symbol_get_value_expression
5930 (i.op[n].disps->X_op_symbol)->X_op)
5931 == O_subtract))))
5932 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5933 {
5934 offsetT add;
5935
5936 if (insn_start_frag == frag_now)
5937 add = (p - frag_now->fr_literal) - insn_start_off;
5938 else
5939 {
5940 fragS *fr;
5941
5942 add = insn_start_frag->fr_fix - insn_start_off;
5943 for (fr = insn_start_frag->fr_next;
5944 fr && fr != frag_now; fr = fr->fr_next)
5945 add += fr->fr_fix;
5946 add += p - frag_now->fr_literal;
5947 }
5948
4fa24527 5949 if (!object_64bit)
7b81dfbb
AJ		 5950 {
5951 reloc_type = BFD_RELOC_386_GOTPC;
5952 i.op[n].imms->X_add_number += add;
5953 }
5954 else if (reloc_type == BFD_RELOC_64)
5955 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5956 else
7b81dfbb
AJ		 5957 /* Don't do the adjustment for x86-64, as there
5958 the pcrel addressing is relative to the _next_
5959 insn, and that is taken care of in other code. */
d6ab8113 5960 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5961 }
062cd5e7 5962 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5963 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5964 }
5965 }
5966 }
5967}
252b5132 5968
29b0f896 5969static void
64e74474 5970output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5971{
5972 char *p;
5973 unsigned int n;
252b5132 5974
29b0f896
AM		 5975 for (n = 0; n < i.operands; n++)
5976 {
40fb9820 5977 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5978 {
5979 if (i.op[n].imms->X_op == O_constant)
5980 {
e205caa7 5981 int size = imm_size (n);
29b0f896 5982 offsetT val;
b4cac588 5983
29b0f896
AM		 5984 val = offset_in_range (i.op[n].imms->X_add_number,
5985 size);
5986 p = frag_more (size);
5987 md_number_to_chars (p, val, size);
5988 }
5989 else
5990 {
5991 /* Not absolute_section.
5992 Need a 32-bit fixup (don't support 8bit
5993 non-absolute imms). Try to support other
5994 sizes ... */
f86103b7 5995 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5996 int size = imm_size (n);
5997 int sign;
29b0f896 5998
40fb9820 5999 if (i.types[n].bitfield.imm32s
a7d61044 6000 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6001 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6002 sign = 1;
e205caa7
L		 6003 else
6004 sign = 0;
520dc8e8 6005
29b0f896
AM		 6006 p = frag_more (size);
6007 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6008
2bbd9c25
JJ		 6009 /* This is tough to explain. We end up with this one if we
6010 * have operands that look like
6011 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6012 * obtain the absolute address of the GOT, and it is strongly
6013 * preferable from a performance point of view to avoid using
6014 * a runtime relocation for this. The actual sequence of
6015 * instructions often look something like:
6016 *
6017 * call .L66
6018 * .L66:
6019 * popl %ebx
6020 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6021 *
6022 * The call and pop essentially return the absolute address
6023 * of the label .L66 and store it in %ebx. The linker itself
6024 * will ultimately change the first operand of the addl so
6025 * that %ebx points to the GOT, but to keep things simple, the
6026 * .o file must have this operand set so that it generates not
6027 * the absolute address of .L66, but the absolute address of
6028 * itself. This allows the linker itself simply treat a GOTPC
6029 * relocation as asking for a pcrel offset to the GOT to be
6030 * added in, and the addend of the relocation is stored in the
6031 * operand field for the instruction itself.
6032 *
6033 * Our job here is to fix the operand so that it would add
6034 * the correct offset so that %ebx would point to itself. The
6035 * thing that is tricky is that .-.L66 will point to the
6036 * beginning of the instruction, so we need to further modify
6037 * the operand so that it will point to itself. There are
6038 * other cases where you have something like:
6039 *
6040 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6041 *
6042 * and here no correction would be required. Internally in
6043 * the assembler we treat operands of this form as not being
6044 * pcrel since the '.' is explicitly mentioned, and I wonder
6045 * whether it would simplify matters to do it this way. Who
6046 * knows. In earlier versions of the PIC patches, the
6047 * pcrel_adjust field was used to store the correction, but
6048 * since the expression is not pcrel, I felt it would be
6049 * confusing to do it this way. */
6050
d6ab8113 6051 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6052 || reloc_type == BFD_RELOC_X86_64_32S
6053 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6054 && GOT_symbol
6055 && GOT_symbol == i.op[n].imms->X_add_symbol
6056 && (i.op[n].imms->X_op == O_symbol
6057 || (i.op[n].imms->X_op == O_add
6058 && ((symbol_get_value_expression
6059 (i.op[n].imms->X_op_symbol)->X_op)
6060 == O_subtract))))
6061 {
2bbd9c25
JJ		 6062 offsetT add;
6063
6064 if (insn_start_frag == frag_now)
6065 add = (p - frag_now->fr_literal) - insn_start_off;
6066 else
6067 {
6068 fragS *fr;
6069
6070 add = insn_start_frag->fr_fix - insn_start_off;
6071 for (fr = insn_start_frag->fr_next;
6072 fr && fr != frag_now; fr = fr->fr_next)
6073 add += fr->fr_fix;
6074 add += p - frag_now->fr_literal;
6075 }
6076
4fa24527 6077 if (!object_64bit)
d6ab8113 6078 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6079 else if (size == 4)
d6ab8113 6080 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6081 else if (size == 8)
6082 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6083 i.op[n].imms->X_add_number += add;
29b0f896 6084 }
29b0f896
AM		 6085 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6086 i.op[n].imms, 0, reloc_type);
6087 }
6088 }
6089 }
252b5132
RH		 6090}
6091\f
d182319b
JB		 6092/* x86_cons_fix_new is called via the expression parsing code when a
6093 reloc is needed. We use this hook to get the correct .got reloc. */
6094static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6095static int cons_sign = -1;
6096
6097void
e3bb37b5 6098x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6099 expressionS *exp)
d182319b
JB		 6100{
6101 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6102
6103 got_reloc = NO_RELOC;
6104
6105#ifdef TE_PE
6106 if (exp->X_op == O_secrel)
6107 {
6108 exp->X_op = O_symbol;
6109 r = BFD_RELOC_32_SECREL;
6110 }
6111#endif
6112
6113 fix_new_exp (frag, off, len, exp, 0, r);
6114}
6115
718ddfc0
JB		 6116#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6117# define lex_got(reloc, adjust, types) NULL
6118#else
f3c180ae
AM		 6119/* Parse operands of the form
6120 <symbol>@GOTOFF+<nnn>
6121 and similar .plt or .got references.
6122
6123 If we find one, set up the correct relocation in RELOC and copy the
6124 input string, minus the `@GOTOFF' into a malloc'd buffer for
6125 parsing by the calling routine. Return this buffer, and if ADJUST
6126 is non-null set it to the length of the string we removed from the
6127 input line. Otherwise return NULL. */
6128static char *
91d6fa6a 6129lex_got (enum bfd_reloc_code_real *rel,
64e74474 6130 int *adjust,
40fb9820 6131 i386_operand_type *types)
f3c180ae 6132{
7b81dfbb
AJ		 6133 /* Some of the relocations depend on the size of what field is to
6134 be relocated. But in our callers i386_immediate and i386_displacement
6135 we don't yet know the operand size (this will be set by insn
6136 matching). Hence we record the word32 relocation here,
6137 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6138 static const struct {
6139 const char *str;
4fa24527 6140 const enum bfd_reloc_code_real rel[2];
40fb9820 6141 const i386_operand_type types64;
f3c180ae 6142 } gotrel[] = {
1e9cc1c2 6143 { "PLTOFF", { _dummy_first_bfd_reloc_code_real,
4eed87de 6144 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6145 OPERAND_TYPE_IMM64 },
4eed87de
AM		 6146 { "PLT", { BFD_RELOC_386_PLT32,
6147 BFD_RELOC_X86_64_PLT32 },
40fb9820 6148 OPERAND_TYPE_IMM32_32S_DISP32 },
1e9cc1c2 6149 { "GOTPLT", { _dummy_first_bfd_reloc_code_real,
4eed87de 6150 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6151 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6152 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
6153 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6154 OPERAND_TYPE_IMM64_DISP64 },
1e9cc1c2 6155 { "GOTPCREL", { _dummy_first_bfd_reloc_code_real,
4eed87de 6156 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6157 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6158 { "TLSGD", { BFD_RELOC_386_TLS_GD,
6159 BFD_RELOC_X86_64_TLSGD },
40fb9820 6160 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de 6161 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
1e9cc1c2 6162 _dummy_first_bfd_reloc_code_real },
40fb9820 6163 OPERAND_TYPE_NONE },
1e9cc1c2 6164 { "TLSLD", { _dummy_first_bfd_reloc_code_real,
4eed87de 6165 BFD_RELOC_X86_64_TLSLD },
40fb9820 6166 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6167 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
6168 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6169 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6170 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
6171 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6172 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de 6173 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
1e9cc1c2 6174 _dummy_first_bfd_reloc_code_real },
40fb9820 6175 OPERAND_TYPE_NONE },
4eed87de
AM		 6176 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
6177 BFD_RELOC_X86_64_DTPOFF32 },
7ab9ffdd 6178
40fb9820 6179 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de 6180 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
1e9cc1c2 6181 _dummy_first_bfd_reloc_code_real },
40fb9820 6182 OPERAND_TYPE_NONE },
4eed87de 6183 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
1e9cc1c2 6184 _dummy_first_bfd_reloc_code_real },
40fb9820 6185 OPERAND_TYPE_NONE },
4eed87de
AM		 6186 { "GOT", { BFD_RELOC_386_GOT32,
6187 BFD_RELOC_X86_64_GOT32 },
40fb9820 6188 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 6189 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
6190 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6191 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6192 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
6193 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6194 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6195 };
6196 char *cp;
6197 unsigned int j;
6198
718ddfc0
JB		 6199 if (!IS_ELF)
6200 return NULL;
6201
f3c180ae 6202 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6203 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6204 return NULL;
6205
47465058 6206 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 6207 {
6208 int len;
6209
6210 len = strlen (gotrel[j].str);
28f81592 6211 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6212 {
4fa24527 6213 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6214 {
28f81592
AM		 6215 int first, second;
6216 char *tmpbuf, *past_reloc;
f3c180ae 6217
91d6fa6a 6218 *rel = gotrel[j].rel[object_64bit];
28f81592
AM		 6219 if (adjust)
6220 *adjust = len;
f3c180ae 6221
3956db08
JB		 6222 if (types)
6223 {
6224 if (flag_code != CODE_64BIT)
40fb9820
L		 6225 {
6226 types->bitfield.imm32 = 1;
6227 types->bitfield.disp32 = 1;
6228 }
3956db08
JB		 6229 else
6230 *types = gotrel[j].types64;
6231 }
6232
f3c180ae
AM		 6233 if (GOT_symbol == NULL)
6234 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6235
28f81592 6236 /* The length of the first part of our input line. */
f3c180ae 6237 first = cp - input_line_pointer;
28f81592
AM		 6238
6239 /* The second part goes from after the reloc token until
67c11a9b 6240 (and including) an end_of_line char or comma. */
28f81592 6241 past_reloc = cp + 1 + len;
67c11a9b
AM		 6242 cp = past_reloc;
6243 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6244 ++cp;
6245 second = cp + 1 - past_reloc;
28f81592
AM		 6246
6247 /* Allocate and copy string. The trailing NUL shouldn't
6248 be necessary, but be safe. */
1e9cc1c2 6249 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6250 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6251 if (second != 0 && *past_reloc != ' ')
6252 /* Replace the relocation token with ' ', so that
6253 errors like foo@GOTOFF1 will be detected. */
6254 tmpbuf[first++] = ' ';
6255 memcpy (tmpbuf + first, past_reloc, second);
6256 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6257 return tmpbuf;
6258 }
6259
4fa24527
JB		 6260 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6261 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6262 return NULL;
6263 }
6264 }
6265
6266 /* Might be a symbol version string. Don't as_bad here. */
6267 return NULL;
6268}
6269
f3c180ae 6270void
e3bb37b5 6271x86_cons (expressionS *exp, int size)
f3c180ae 6272{
ee86248c
JB		 6273 intel_syntax = -intel_syntax;
6274
4fa24527 6275 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6276 {
6277 /* Handle @GOTOFF and the like in an expression. */
6278 char *save;
6279 char *gotfree_input_line;
6280 int adjust;
6281
6282 save = input_line_pointer;
3956db08 6283 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6284 if (gotfree_input_line)
6285 input_line_pointer = gotfree_input_line;
6286
6287 expression (exp);
6288
6289 if (gotfree_input_line)
6290 {
6291 /* expression () has merrily parsed up to the end of line,
6292 or a comma - in the wrong buffer. Transfer how far
6293 input_line_pointer has moved to the right buffer. */
6294 input_line_pointer = (save
6295 + (input_line_pointer - gotfree_input_line)
6296 + adjust);
6297 free (gotfree_input_line);
3992d3b7
AM		 6298 if (exp->X_op == O_constant
6299 || exp->X_op == O_absent
6300 || exp->X_op == O_illegal
6301 || exp->X_op == O_register
6302 || exp->X_op == O_big)
6303 {
6304 char c = *input_line_pointer;
6305 *input_line_pointer = 0;
6306 as_bad (_("missing or invalid expression `%s'"), save);
6307 *input_line_pointer = c;
6308 }
f3c180ae
AM		 6309 }
6310 }
6311 else
6312 expression (exp);
ee86248c
JB		 6313
6314 intel_syntax = -intel_syntax;
6315
6316 if (intel_syntax)
6317 i386_intel_simplify (exp);
f3c180ae
AM		 6318}
6319#endif
6320
9f32dd5b
L		 6321static void
6322signed_cons (int size)
6482c264 6323{
d182319b
JB		 6324 if (flag_code == CODE_64BIT)
6325 cons_sign = 1;
6326 cons (size);
6327 cons_sign = -1;
6482c264
NC		 6328}
6329
d182319b 6330#ifdef TE_PE
6482c264
NC		 6331static void
6332pe_directive_secrel (dummy)
6333 int dummy ATTRIBUTE_UNUSED;
6334{
6335 expressionS exp;
6336
6337 do
6338 {
6339 expression (&exp);
6340 if (exp.X_op == O_symbol)
6341 exp.X_op = O_secrel;
6342
6343 emit_expr (&exp, 4);
6344 }
6345 while (*input_line_pointer++ == ',');
6346
6347 input_line_pointer--;
6348 demand_empty_rest_of_line ();
6349}
6482c264
NC		 6350#endif
6351
252b5132 6352static int
70e41ade 6353i386_immediate (char *imm_start)
252b5132
RH		 6354{
6355 char *save_input_line_pointer;
f3c180ae 6356 char *gotfree_input_line;
252b5132 6357 segT exp_seg = 0;
47926f60 6358 expressionS *exp;
40fb9820
L		 6359 i386_operand_type types;
6360
0dfbf9d7 6361 operand_type_set (&types, ~0);
252b5132
RH		 6362
6363 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6364 {
31b2323c
L		 6365 as_bad (_("at most %d immediate operands are allowed"),
6366 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6367 return 0;
6368 }
6369
6370 exp = &im_expressions[i.imm_operands++];
520dc8e8 6371 i.op[this_operand].imms = exp;
252b5132
RH		 6372
6373 if (is_space_char (*imm_start))
6374 ++imm_start;
6375
6376 save_input_line_pointer = input_line_pointer;
6377 input_line_pointer = imm_start;
6378
3956db08 6379 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6380 if (gotfree_input_line)
6381 input_line_pointer = gotfree_input_line;
252b5132
RH		 6382
6383 exp_seg = expression (exp);
6384
83183c0c 6385 SKIP_WHITESPACE ();
252b5132 6386 if (*input_line_pointer)
f3c180ae 6387 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6388
6389 input_line_pointer = save_input_line_pointer;
f3c180ae 6390 if (gotfree_input_line)
ee86248c
JB		 6391 {
6392 free (gotfree_input_line);
6393
6394 if (exp->X_op == O_constant || exp->X_op == O_register)
6395 exp->X_op = O_illegal;
6396 }
6397
6398 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6399}
252b5132 6400
ee86248c
JB		 6401static int
6402i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6403 i386_operand_type types, const char *imm_start)
6404{
6405 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6406 {
313c53d1
L		 6407 if (imm_start)
6408 as_bad (_("missing or invalid immediate expression `%s'"),
6409 imm_start);
3992d3b7 6410 return 0;
252b5132 6411 }
3e73aa7c 6412 else if (exp->X_op == O_constant)
252b5132 6413 {
47926f60 6414 /* Size it properly later. */
40fb9820 6415 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6416 /* If BFD64, sign extend val. */
4eed87de
AM		 6417 if (!use_rela_relocations
6418 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6419 exp->X_add_number
6420 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6421 }
4c63da97 6422#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6423 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6424 && exp_seg != absolute_section
47926f60 6425 && exp_seg != text_section
24eab124
AM		 6426 && exp_seg != data_section
6427 && exp_seg != bss_section
6428 && exp_seg != undefined_section
f86103b7 6429 && !bfd_is_com_section (exp_seg))
252b5132 6430 {
d0b47220 6431 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6432 return 0;
6433 }
6434#endif
bb8f5920
L		 6435 else if (!intel_syntax && exp->X_op == O_register)
6436 {
313c53d1
L		 6437 if (imm_start)
6438 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 6439 return 0;
6440 }
252b5132
RH		 6441 else
6442 {
6443 /* This is an address. The size of the address will be
24eab124 6444 determined later, depending on destination register,
3e73aa7c 6445 suffix, or the default for the section. */
40fb9820
L		 6446 i.types[this_operand].bitfield.imm8 = 1;
6447 i.types[this_operand].bitfield.imm16 = 1;
6448 i.types[this_operand].bitfield.imm32 = 1;
6449 i.types[this_operand].bitfield.imm32s = 1;
6450 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6451 i.types[this_operand] = operand_type_and (i.types[this_operand],
6452 types);
252b5132
RH		 6453 }
6454
6455 return 1;
6456}
6457
551c1ca1 6458static char *
e3bb37b5 6459i386_scale (char *scale)
252b5132 6460{
551c1ca1
AM		 6461 offsetT val;
6462 char *save = input_line_pointer;
252b5132 6463
551c1ca1
AM		 6464 input_line_pointer = scale;
6465 val = get_absolute_expression ();
6466
6467 switch (val)
252b5132 6468 {
551c1ca1 6469 case 1:
252b5132
RH		 6470 i.log2_scale_factor = 0;
6471 break;
551c1ca1 6472 case 2:
252b5132
RH		 6473 i.log2_scale_factor = 1;
6474 break;
551c1ca1 6475 case 4:
252b5132
RH		 6476 i.log2_scale_factor = 2;
6477 break;
551c1ca1 6478 case 8:
252b5132
RH		 6479 i.log2_scale_factor = 3;
6480 break;
6481 default:
a724f0f4
JB		 6482 {
6483 char sep = *input_line_pointer;
6484
6485 *input_line_pointer = '\0';
6486 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6487 scale);
6488 *input_line_pointer = sep;
6489 input_line_pointer = save;
6490 return NULL;
6491 }
252b5132 6492 }
29b0f896 6493 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6494 {
6495 as_warn (_("scale factor of %d without an index register"),
24eab124 6496 1 << i.log2_scale_factor);
252b5132 6497 i.log2_scale_factor = 0;
252b5132 6498 }
551c1ca1
AM		 6499 scale = input_line_pointer;
6500 input_line_pointer = save;
6501 return scale;
252b5132
RH		 6502}
6503
252b5132 6504static int
e3bb37b5 6505i386_displacement (char *disp_start, char *disp_end)
252b5132 6506{
29b0f896 6507 expressionS *exp;
252b5132
RH		 6508 segT exp_seg = 0;
6509 char *save_input_line_pointer;
f3c180ae 6510 char *gotfree_input_line;
40fb9820
L		 6511 int override;
6512 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6513 int ret;
252b5132 6514
31b2323c
L		 6515 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6516 {
6517 as_bad (_("at most %d displacement operands are allowed"),
6518 MAX_MEMORY_OPERANDS);
6519 return 0;
6520 }
6521
0dfbf9d7 6522 operand_type_set (&bigdisp, 0);
40fb9820
L		 6523 if ((i.types[this_operand].bitfield.jumpabsolute)
6524 || (!current_templates->start->opcode_modifier.jump
6525 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6526 {
40fb9820 6527 bigdisp.bitfield.disp32 = 1;
e05278af 6528 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6529 if (flag_code == CODE_64BIT)
6530 {
6531 if (!override)
6532 {
6533 bigdisp.bitfield.disp32s = 1;
6534 bigdisp.bitfield.disp64 = 1;
6535 }
6536 }
6537 else if ((flag_code == CODE_16BIT) ^ override)
6538 {
6539 bigdisp.bitfield.disp32 = 0;
6540 bigdisp.bitfield.disp16 = 1;
6541 }
e05278af
JB		 6542 }
6543 else
6544 {
6545 /* For PC-relative branches, the width of the displacement
6546 is dependent upon data size, not address size. */
e05278af 6547 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6548 if (flag_code == CODE_64BIT)
6549 {
6550 if (override || i.suffix == WORD_MNEM_SUFFIX)
6551 bigdisp.bitfield.disp16 = 1;
6552 else
6553 {
6554 bigdisp.bitfield.disp32 = 1;
6555 bigdisp.bitfield.disp32s = 1;
6556 }
6557 }
6558 else
e05278af
JB		 6559 {
6560 if (!override)
6561 override = (i.suffix == (flag_code != CODE_16BIT
6562 ? WORD_MNEM_SUFFIX
6563 : LONG_MNEM_SUFFIX));
40fb9820
L		 6564 bigdisp.bitfield.disp32 = 1;
6565 if ((flag_code == CODE_16BIT) ^ override)
6566 {
6567 bigdisp.bitfield.disp32 = 0;
6568 bigdisp.bitfield.disp16 = 1;
6569 }
e05278af 6570 }
e05278af 6571 }
c6fb90c8
L		 6572 i.types[this_operand] = operand_type_or (i.types[this_operand],
6573 bigdisp);
252b5132
RH		 6574
6575 exp = &disp_expressions[i.disp_operands];
520dc8e8 6576 i.op[this_operand].disps = exp;
252b5132
RH		 6577 i.disp_operands++;
6578 save_input_line_pointer = input_line_pointer;
6579 input_line_pointer = disp_start;
6580 END_STRING_AND_SAVE (disp_end);
6581
6582#ifndef GCC_ASM_O_HACK
6583#define GCC_ASM_O_HACK 0
6584#endif
6585#if GCC_ASM_O_HACK
6586 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6587 if (i.types[this_operand].bitfield.baseIndex
24eab124 6588 && displacement_string_end[-1] == '+')
252b5132
RH		 6589 {
6590 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6591 constraint within gcc asm statements.
6592 For instance:
6593
6594 #define _set_tssldt_desc(n,addr,limit,type) \
6595 __asm__ __volatile__ ( \
6596 "movw %w2,%0\n\t" \
6597 "movw %w1,2+%0\n\t" \
6598 "rorl $16,%1\n\t" \
6599 "movb %b1,4+%0\n\t" \
6600 "movb %4,5+%0\n\t" \
6601 "movb $0,6+%0\n\t" \
6602 "movb %h1,7+%0\n\t" \
6603 "rorl $16,%1" \
6604 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6605
6606 This works great except that the output assembler ends
6607 up looking a bit weird if it turns out that there is
6608 no offset. You end up producing code that looks like:
6609
6610 #APP
6611 movw $235,(%eax)
6612 movw %dx,2+(%eax)
6613 rorl $16,%edx
6614 movb %dl,4+(%eax)
6615 movb $137,5+(%eax)
6616 movb $0,6+(%eax)
6617 movb %dh,7+(%eax)
6618 rorl $16,%edx
6619 #NO_APP
6620
47926f60 6621 So here we provide the missing zero. */
24eab124
AM		 6622
6623 *displacement_string_end = '0';
252b5132
RH		 6624 }
6625#endif
3956db08 6626 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6627 if (gotfree_input_line)
6628 input_line_pointer = gotfree_input_line;
252b5132 6629
24eab124 6630 exp_seg = expression (exp);
252b5132 6631
636c26b0
AM		 6632 SKIP_WHITESPACE ();
6633 if (*input_line_pointer)
6634 as_bad (_("junk `%s' after expression"), input_line_pointer);
6635#if GCC_ASM_O_HACK
6636 RESTORE_END_STRING (disp_end + 1);
6637#endif
636c26b0 6638 input_line_pointer = save_input_line_pointer;
636c26b0 6639 if (gotfree_input_line)
ee86248c
JB		 6640 {
6641 free (gotfree_input_line);
6642
6643 if (exp->X_op == O_constant || exp->X_op == O_register)
6644 exp->X_op = O_illegal;
6645 }
6646
6647 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6648
6649 RESTORE_END_STRING (disp_end);
6650
6651 return ret;
6652}
6653
6654static int
6655i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6656 i386_operand_type types, const char *disp_start)
6657{
6658 i386_operand_type bigdisp;
6659 int ret = 1;
636c26b0 6660
24eab124
AM		 6661 /* We do this to make sure that the section symbol is in
6662 the symbol table. We will ultimately change the relocation
47926f60 6663 to be relative to the beginning of the section. */
1ae12ab7 6664 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6665 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6666 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6667 {
636c26b0 6668 if (exp->X_op != O_symbol)
3992d3b7 6669 goto inv_disp;
636c26b0 6670
e5cb08ac 6671 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6672 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6673 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6674 exp->X_op = O_subtract;
6675 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6676 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6677 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6678 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6679 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6680 else
29b0f896 6681 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6682 }
252b5132 6683
3992d3b7
AM		 6684 else if (exp->X_op == O_absent
6685 || exp->X_op == O_illegal
ee86248c 6686 || exp->X_op == O_big)
2daf4fd8 6687 {
3992d3b7
AM		 6688 inv_disp:
6689 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6690 disp_start);
3992d3b7 6691 ret = 0;
2daf4fd8
AM		 6692 }
6693
0e1147d9
L		 6694 else if (flag_code == CODE_64BIT
6695 && !i.prefix[ADDR_PREFIX]
6696 && exp->X_op == O_constant)
6697 {
6698 /* Since displacement is signed extended to 64bit, don't allow
6699 disp32 and turn off disp32s if they are out of range. */
6700 i.types[this_operand].bitfield.disp32 = 0;
6701 if (!fits_in_signed_long (exp->X_add_number))
6702 {
6703 i.types[this_operand].bitfield.disp32s = 0;
6704 if (i.types[this_operand].bitfield.baseindex)
6705 {
6706 as_bad (_("0x%lx out range of signed 32bit displacement"),
6707 (long) exp->X_add_number);
6708 ret = 0;
6709 }
6710 }
6711 }
6712
4c63da97 6713#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6714 else if (exp->X_op != O_constant
6715 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6716 && exp_seg != absolute_section
6717 && exp_seg != text_section
6718 && exp_seg != data_section
6719 && exp_seg != bss_section
6720 && exp_seg != undefined_section
6721 && !bfd_is_com_section (exp_seg))
24eab124 6722 {
d0b47220 6723 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6724 ret = 0;
24eab124 6725 }
252b5132 6726#endif
3956db08 6727
40fb9820
L		 6728 /* Check if this is a displacement only operand. */
6729 bigdisp = i.types[this_operand];
6730 bigdisp.bitfield.disp8 = 0;
6731 bigdisp.bitfield.disp16 = 0;
6732 bigdisp.bitfield.disp32 = 0;
6733 bigdisp.bitfield.disp32s = 0;
6734 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6735 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6736 i.types[this_operand] = operand_type_and (i.types[this_operand],
6737 types);
3956db08 6738
3992d3b7 6739 return ret;
252b5132
RH		 6740}
6741
eecb386c 6742/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6743 Return 1 on success, 0 on a failure. */
6744
252b5132 6745static int
e3bb37b5 6746i386_index_check (const char *operand_string)
252b5132 6747{
3e73aa7c 6748 int ok;
fc0763e6 6749 const char *kind = "base/index";
24eab124 6750#if INFER_ADDR_PREFIX
eecb386c
AM		 6751 int fudged = 0;
6752
24eab124
AM		 6753 tryprefix:
6754#endif
3e73aa7c 6755 ok = 1;
fc0763e6
JB		 6756 if (current_templates->start->opcode_modifier.isstring
6757 && !current_templates->start->opcode_modifier.immext
6758 && (current_templates->end[-1].opcode_modifier.isstring
6759 || i.mem_operands))
6760 {
6761 /* Memory operands of string insns are special in that they only allow
6762 a single register (rDI, rSI, or rBX) as their memory address. */
6763 unsigned int expected;
6764
6765 kind = "string address";
6766
6767 if (current_templates->start->opcode_modifier.w)
6768 {
6769 i386_operand_type type = current_templates->end[-1].operand_types[0];
6770
6771 if (!type.bitfield.baseindex
6772 || ((!i.mem_operands != !intel_syntax)
6773 && current_templates->end[-1].operand_types[1]
6774 .bitfield.baseindex))
6775 type = current_templates->end[-1].operand_types[1];
6776 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6777 }
6778 else
6779 expected = 3 /* rBX */;
6780
6781 if (!i.base_reg || i.index_reg
6782 || operand_type_check (i.types[this_operand], disp))
6783 ok = -1;
6784 else if (!(flag_code == CODE_64BIT
6785 ? i.prefix[ADDR_PREFIX]
6786 ? i.base_reg->reg_type.bitfield.reg32
6787 : i.base_reg->reg_type.bitfield.reg64
6788 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6789 ? i.base_reg->reg_type.bitfield.reg32
6790 : i.base_reg->reg_type.bitfield.reg16))
6791 ok = 0;
6792 else if (i.base_reg->reg_num != expected)
6793 ok = -1;
6794
6795 if (ok < 0)
6796 {
6797 unsigned int j;
6798
6799 for (j = 0; j < i386_regtab_size; ++j)
6800 if ((flag_code == CODE_64BIT
6801 ? i.prefix[ADDR_PREFIX]
6802 ? i386_regtab[j].reg_type.bitfield.reg32
6803 : i386_regtab[j].reg_type.bitfield.reg64
6804 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6805 ? i386_regtab[j].reg_type.bitfield.reg32
6806 : i386_regtab[j].reg_type.bitfield.reg16)
6807 && i386_regtab[j].reg_num == expected)
6808 break;
9c2799c2 6809 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 6810 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6811 operand_string,
6812 intel_syntax ? '[' : '(',
6813 register_prefix,
6814 i386_regtab[j].reg_name,
6815 intel_syntax ? ']' : ')');
6816 ok = 1;
6817 }
6818 }
6819 else if (flag_code == CODE_64BIT)
64e74474 6820 {
64e74474 6821 if ((i.base_reg
40fb9820
L		 6822 && ((i.prefix[ADDR_PREFIX] == 0
6823 && !i.base_reg->reg_type.bitfield.reg64)
6824 || (i.prefix[ADDR_PREFIX]
6825 && !i.base_reg->reg_type.bitfield.reg32))
6826 && (i.index_reg
9a04903e
JB		 6827 || i.base_reg->reg_num !=
6828 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6829 || (i.index_reg
40fb9820
L		 6830 && (!i.index_reg->reg_type.bitfield.baseindex
6831 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6832 && i.index_reg->reg_num != RegRiz
6833 && !i.index_reg->reg_type.bitfield.reg64
6834 )
40fb9820 6835 || (i.prefix[ADDR_PREFIX]
db51cc60 6836 && i.index_reg->reg_num != RegEiz
40fb9820 6837 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6838 ok = 0;
3e73aa7c
JH		 6839 }
6840 else
6841 {
6842 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6843 {
6844 /* 16bit checks. */
6845 if ((i.base_reg
40fb9820
L		 6846 && (!i.base_reg->reg_type.bitfield.reg16
6847 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6848 || (i.index_reg
40fb9820
L		 6849 && (!i.index_reg->reg_type.bitfield.reg16
6850 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6851 || !(i.base_reg
6852 && i.base_reg->reg_num < 6
6853 && i.index_reg->reg_num >= 6
6854 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6855 ok = 0;
6856 }
6857 else
e5cb08ac 6858 {
3e73aa7c
JH		 6859 /* 32bit checks. */
6860 if ((i.base_reg
40fb9820 6861 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6862 || (i.index_reg
db51cc60
L		 6863 && ((!i.index_reg->reg_type.bitfield.reg32
6864 && i.index_reg->reg_num != RegEiz)
40fb9820 6865 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6866 ok = 0;
3e73aa7c
JH		 6867 }
6868 }
6869 if (!ok)
24eab124
AM		 6870 {
6871#if INFER_ADDR_PREFIX
fc0763e6 6872 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 6873 {
6874 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6875 i.prefixes += 1;
b23bac36
AM		 6876 /* Change the size of any displacement too. At most one of
6877 Disp16 or Disp32 is set.
6878 FIXME. There doesn't seem to be any real need for separate
6879 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6880 Removing them would probably clean up the code quite a lot. */
4eed87de 6881 if (flag_code != CODE_64BIT
40fb9820
L		 6882 && (i.types[this_operand].bitfield.disp16
6883 || i.types[this_operand].bitfield.disp32))
6884 i.types[this_operand]
c6fb90c8 6885 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6886 fudged = 1;
24eab124
AM		 6887 goto tryprefix;
6888 }
eecb386c 6889 if (fudged)
fc0763e6
JB		 6890 as_bad (_("`%s' is not a valid %s expression"),
6891 operand_string,
6892 kind);
eecb386c 6893 else
c388dee8 6894#endif
fc0763e6 6895 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 6896 operand_string,
fc0763e6
JB		 6897 flag_code_names[i.prefix[ADDR_PREFIX]
6898 ? flag_code == CODE_32BIT
6899 ? CODE_16BIT
6900 : CODE_32BIT
6901 : flag_code],
6902 kind);
24eab124 6903 }
20f0a1fc 6904 return ok;
24eab124 6905}
252b5132 6906
fc0763e6 6907/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 6908 on error. */
252b5132 6909
252b5132 6910static int
a7619375 6911i386_att_operand (char *operand_string)
252b5132 6912{
af6bdddf
AM		 6913 const reg_entry *r;
6914 char *end_op;
24eab124 6915 char *op_string = operand_string;
252b5132 6916
24eab124 6917 if (is_space_char (*op_string))
252b5132
RH		 6918 ++op_string;
6919
24eab124 6920 /* We check for an absolute prefix (differentiating,
47926f60 6921 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6922 if (*op_string == ABSOLUTE_PREFIX)
6923 {
6924 ++op_string;
6925 if (is_space_char (*op_string))
6926 ++op_string;
40fb9820 6927 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6928 }
252b5132 6929
47926f60 6930 /* Check if operand is a register. */
4d1bb795 6931 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6932 {
40fb9820
L		 6933 i386_operand_type temp;
6934
24eab124
AM		 6935 /* Check for a segment override by searching for ':' after a
6936 segment register. */
6937 op_string = end_op;
6938 if (is_space_char (*op_string))
6939 ++op_string;
40fb9820
L		 6940 if (*op_string == ':'
6941 && (r->reg_type.bitfield.sreg2
6942 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6943 {
6944 switch (r->reg_num)
6945 {
6946 case 0:
6947 i.seg[i.mem_operands] = &es;
6948 break;
6949 case 1:
6950 i.seg[i.mem_operands] = &cs;
6951 break;
6952 case 2:
6953 i.seg[i.mem_operands] = &ss;
6954 break;
6955 case 3:
6956 i.seg[i.mem_operands] = &ds;
6957 break;
6958 case 4:
6959 i.seg[i.mem_operands] = &fs;
6960 break;
6961 case 5:
6962 i.seg[i.mem_operands] = &gs;
6963 break;
6964 }
252b5132 6965
24eab124 6966 /* Skip the ':' and whitespace. */
252b5132
RH		 6967 ++op_string;
6968 if (is_space_char (*op_string))
24eab124 6969 ++op_string;
252b5132 6970
24eab124
AM		 6971 if (!is_digit_char (*op_string)
6972 && !is_identifier_char (*op_string)
6973 && *op_string != '('
6974 && *op_string != ABSOLUTE_PREFIX)
6975 {
6976 as_bad (_("bad memory operand `%s'"), op_string);
6977 return 0;
6978 }
47926f60 6979 /* Handle case of %es:*foo. */
24eab124
AM		 6980 if (*op_string == ABSOLUTE_PREFIX)
6981 {
6982 ++op_string;
6983 if (is_space_char (*op_string))
6984 ++op_string;
40fb9820 6985 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6986 }
6987 goto do_memory_reference;
6988 }
6989 if (*op_string)
6990 {
d0b47220 6991 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6992 return 0;
6993 }
40fb9820
L		 6994 temp = r->reg_type;
6995 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6996 i.types[this_operand] = operand_type_or (i.types[this_operand],
6997 temp);
7d5e4556 6998 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 6999 i.op[this_operand].regs = r;
24eab124
AM		 7000 i.reg_operands++;
7001 }
af6bdddf
AM		 7002 else if (*op_string == REGISTER_PREFIX)
7003 {
7004 as_bad (_("bad register name `%s'"), op_string);
7005 return 0;
7006 }
24eab124 7007 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7008 {
24eab124 7009 ++op_string;
40fb9820 7010 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7011 {
d0b47220 7012 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7013 return 0;
7014 }
7015 if (!i386_immediate (op_string))
7016 return 0;
7017 }
7018 else if (is_digit_char (*op_string)
7019 || is_identifier_char (*op_string)
e5cb08ac 7020 || *op_string == '(')
24eab124 7021 {
47926f60 7022 /* This is a memory reference of some sort. */
af6bdddf 7023 char *base_string;
252b5132 7024
47926f60 7025 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7026 char *displacement_string_start;
7027 char *displacement_string_end;
252b5132 7028
24eab124 7029 do_memory_reference:
24eab124 7030 if ((i.mem_operands == 1
40fb9820 7031 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7032 || i.mem_operands == 2)
7033 {
7034 as_bad (_("too many memory references for `%s'"),
7035 current_templates->start->name);
7036 return 0;
7037 }
252b5132 7038
24eab124
AM		 7039 /* Check for base index form. We detect the base index form by
7040 looking for an ')' at the end of the operand, searching
7041 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7042 after the '('. */
af6bdddf 7043 base_string = op_string + strlen (op_string);
c3332e24 7044
af6bdddf
AM		 7045 --base_string;
7046 if (is_space_char (*base_string))
7047 --base_string;
252b5132 7048
47926f60 7049 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7050 displacement_string_start = op_string;
7051 displacement_string_end = base_string + 1;
252b5132 7052
24eab124
AM		 7053 if (*base_string == ')')
7054 {
af6bdddf 7055 char *temp_string;
24eab124
AM		 7056 unsigned int parens_balanced = 1;
7057 /* We've already checked that the number of left & right ()'s are
47926f60 7058 equal, so this loop will not be infinite. */
24eab124
AM		 7059 do
7060 {
7061 base_string--;
7062 if (*base_string == ')')
7063 parens_balanced++;
7064 if (*base_string == '(')
7065 parens_balanced--;
7066 }
7067 while (parens_balanced);
c3332e24 7068
af6bdddf 7069 temp_string = base_string;
c3332e24 7070
24eab124 7071 /* Skip past '(' and whitespace. */
252b5132
RH		 7072 ++base_string;
7073 if (is_space_char (*base_string))
24eab124 7074 ++base_string;
252b5132 7075
af6bdddf 7076 if (*base_string == ','
4eed87de
AM		 7077 || ((i.base_reg = parse_register (base_string, &end_op))
7078 != NULL))
252b5132 7079 {
af6bdddf 7080 displacement_string_end = temp_string;
252b5132 7081
40fb9820 7082 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7083
af6bdddf 7084 if (i.base_reg)
24eab124 7085 {
24eab124
AM		 7086 base_string = end_op;
7087 if (is_space_char (*base_string))
7088 ++base_string;
af6bdddf
AM		 7089 }
7090
7091 /* There may be an index reg or scale factor here. */
7092 if (*base_string == ',')
7093 {
7094 ++base_string;
7095 if (is_space_char (*base_string))
7096 ++base_string;
7097
4eed87de
AM		 7098 if ((i.index_reg = parse_register (base_string, &end_op))
7099 != NULL)
24eab124 7100 {
af6bdddf 7101 base_string = end_op;
24eab124
AM		 7102 if (is_space_char (*base_string))
7103 ++base_string;
af6bdddf
AM		 7104 if (*base_string == ',')
7105 {
7106 ++base_string;
7107 if (is_space_char (*base_string))
7108 ++base_string;
7109 }
e5cb08ac 7110 else if (*base_string != ')')
af6bdddf 7111 {
4eed87de
AM		 7112 as_bad (_("expecting `,' or `)' "
7113 "after index register in `%s'"),
af6bdddf
AM		 7114 operand_string);
7115 return 0;
7116 }
24eab124 7117 }
af6bdddf 7118 else if (*base_string == REGISTER_PREFIX)
24eab124 7119 {
af6bdddf 7120 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7121 return 0;
7122 }
252b5132 7123
47926f60 7124 /* Check for scale factor. */
551c1ca1 7125 if (*base_string != ')')
af6bdddf 7126 {
551c1ca1
AM		 7127 char *end_scale = i386_scale (base_string);
7128
7129 if (!end_scale)
af6bdddf 7130 return 0;
24eab124 7131
551c1ca1 7132 base_string = end_scale;
af6bdddf
AM		 7133 if (is_space_char (*base_string))
7134 ++base_string;
7135 if (*base_string != ')')
7136 {
4eed87de
AM		 7137 as_bad (_("expecting `)' "
7138 "after scale factor in `%s'"),
af6bdddf
AM		 7139 operand_string);
7140 return 0;
7141 }
7142 }
7143 else if (!i.index_reg)
24eab124 7144 {
4eed87de
AM		 7145 as_bad (_("expecting index register or scale factor "
7146 "after `,'; got '%c'"),
af6bdddf 7147 *base_string);
24eab124
AM		 7148 return 0;
7149 }
7150 }
af6bdddf 7151 else if (*base_string != ')')
24eab124 7152 {
4eed87de
AM		 7153 as_bad (_("expecting `,' or `)' "
7154 "after base register in `%s'"),
af6bdddf 7155 operand_string);
24eab124
AM		 7156 return 0;
7157 }
c3332e24 7158 }
af6bdddf 7159 else if (*base_string == REGISTER_PREFIX)
c3332e24 7160 {
af6bdddf 7161 as_bad (_("bad register name `%s'"), base_string);
24eab124 7162 return 0;
c3332e24 7163 }
24eab124
AM		 7164 }
7165
7166 /* If there's an expression beginning the operand, parse it,
7167 assuming displacement_string_start and
7168 displacement_string_end are meaningful. */
7169 if (displacement_string_start != displacement_string_end)
7170 {
7171 if (!i386_displacement (displacement_string_start,
7172 displacement_string_end))
7173 return 0;
7174 }
7175
7176 /* Special case for (%dx) while doing input/output op. */
7177 if (i.base_reg
0dfbf9d7
L		 7178 && operand_type_equal (&i.base_reg->reg_type,
7179 &reg16_inoutportreg)
24eab124
AM		 7180 && i.index_reg == 0
7181 && i.log2_scale_factor == 0
7182 && i.seg[i.mem_operands] == 0
40fb9820 7183 && !operand_type_check (i.types[this_operand], disp))
24eab124 7184 {
65da13b5 7185 i.types[this_operand] = inoutportreg;
24eab124
AM		 7186 return 1;
7187 }
7188
eecb386c
AM		 7189 if (i386_index_check (operand_string) == 0)
7190 return 0;
5c07affc 7191 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7192 i.mem_operands++;
7193 }
7194 else
ce8a8b2f
AM		 7195 {
7196 /* It's not a memory operand; argh! */
24eab124
AM		 7197 as_bad (_("invalid char %s beginning operand %d `%s'"),
7198 output_invalid (*op_string),
7199 this_operand + 1,
7200 op_string);
7201 return 0;
7202 }
47926f60 7203 return 1; /* Normal return. */
252b5132
RH		 7204}
7205\f
ee7fcc42
AM		 7206/* md_estimate_size_before_relax()
7207
7208 Called just before relax() for rs_machine_dependent frags. The x86
7209 assembler uses these frags to handle variable size jump
7210 instructions.
7211
7212 Any symbol that is now undefined will not become defined.
7213 Return the correct fr_subtype in the frag.
7214 Return the initial "guess for variable size of frag" to caller.
7215 The guess is actually the growth beyond the fixed part. Whatever
7216 we do to grow the fixed or variable part contributes to our
7217 returned value. */
7218
252b5132
RH		 7219int
7220md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7221 fragS *fragP;
7222 segT segment;
252b5132 7223{
252b5132 7224 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7225 check for un-relaxable symbols. On an ELF system, we can't relax
7226 an externally visible symbol, because it may be overridden by a
7227 shared library. */
7228 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7229#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7230 || (IS_ELF
31312f95 7231 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7232 || S_IS_WEAK (fragP->fr_symbol)
7233 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7234 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7235#endif
7236#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7237 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7238 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7239#endif
7240 )
252b5132 7241 {
b98ef147
AM		 7242 /* Symbol is undefined in this segment, or we need to keep a
7243 reloc so that weak symbols can be overridden. */
7244 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7245 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7246 unsigned char *opcode;
7247 int old_fr_fix;
f6af82bd 7248
ee7fcc42 7249 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7250 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7251 else if (size == 2)
f6af82bd
AM		 7252 reloc_type = BFD_RELOC_16_PCREL;
7253 else
7254 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7255
ee7fcc42
AM		 7256 old_fr_fix = fragP->fr_fix;
7257 opcode = (unsigned char *) fragP->fr_opcode;
7258
fddf5b5b 7259 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7260 {
fddf5b5b
AM		 7261 case UNCOND_JUMP:
7262 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7263 opcode[0] = 0xe9;
252b5132 7264 fragP->fr_fix += size;
062cd5e7
AS		 7265 fix_new (fragP, old_fr_fix, size,
7266 fragP->fr_symbol,
7267 fragP->fr_offset, 1,
7268 reloc_type);
252b5132
RH		 7269 break;
7270
fddf5b5b 7271 case COND_JUMP86:
412167cb
AM		 7272 if (size == 2
7273 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7274 {
7275 /* Negate the condition, and branch past an
7276 unconditional jump. */
7277 opcode[0] ^= 1;
7278 opcode[1] = 3;
7279 /* Insert an unconditional jump. */
7280 opcode[2] = 0xe9;
7281 /* We added two extra opcode bytes, and have a two byte
7282 offset. */
7283 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7284 fix_new (fragP, old_fr_fix + 2, 2,
7285 fragP->fr_symbol,
7286 fragP->fr_offset, 1,
7287 reloc_type);
fddf5b5b
AM		 7288 break;
7289 }
7290 /* Fall through. */
7291
7292 case COND_JUMP:
412167cb
AM		 7293 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7294 {
3e02c1cc
AM		 7295 fixS *fixP;
7296
412167cb 7297 fragP->fr_fix += 1;
3e02c1cc
AM		 7298 fixP = fix_new (fragP, old_fr_fix, 1,
7299 fragP->fr_symbol,
7300 fragP->fr_offset, 1,
7301 BFD_RELOC_8_PCREL);
7302 fixP->fx_signed = 1;
412167cb
AM		 7303 break;
7304 }
93c2a809 7305
24eab124 7306 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7307 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7308 opcode[1] = opcode[0] + 0x10;
f6af82bd 7309 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7310 /* We've added an opcode byte. */
7311 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7312 fix_new (fragP, old_fr_fix + 1, size,
7313 fragP->fr_symbol,
7314 fragP->fr_offset, 1,
7315 reloc_type);
252b5132 7316 break;
fddf5b5b
AM		 7317
7318 default:
7319 BAD_CASE (fragP->fr_subtype);
7320 break;
252b5132
RH		 7321 }
7322 frag_wane (fragP);
ee7fcc42 7323 return fragP->fr_fix - old_fr_fix;
252b5132 7324 }
93c2a809 7325
93c2a809
AM		 7326 /* Guess size depending on current relax state. Initially the relax
7327 state will correspond to a short jump and we return 1, because
7328 the variable part of the frag (the branch offset) is one byte
7329 long. However, we can relax a section more than once and in that
7330 case we must either set fr_subtype back to the unrelaxed state,
7331 or return the value for the appropriate branch. */
7332 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7333}
7334
47926f60
KH		 7335/* Called after relax() is finished.
7336
7337 In: Address of frag.
7338 fr_type == rs_machine_dependent.
7339 fr_subtype is what the address relaxed to.
7340
7341 Out: Any fixSs and constants are set up.
7342 Caller will turn frag into a ".space 0". */
7343
252b5132
RH		 7344void
7345md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7346 bfd *abfd ATTRIBUTE_UNUSED;
7347 segT sec ATTRIBUTE_UNUSED;
29b0f896 7348 fragS *fragP;
252b5132 7349{
29b0f896 7350 unsigned char *opcode;
252b5132 7351 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7352 offsetT target_address;
7353 offsetT opcode_address;
252b5132 7354 unsigned int extension = 0;
847f7ad4 7355 offsetT displacement_from_opcode_start;
252b5132
RH		 7356
7357 opcode = (unsigned char *) fragP->fr_opcode;
7358
47926f60 7359 /* Address we want to reach in file space. */
252b5132 7360 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7361
47926f60 7362 /* Address opcode resides at in file space. */
252b5132
RH		 7363 opcode_address = fragP->fr_address + fragP->fr_fix;
7364
47926f60 7365 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7366 displacement_from_opcode_start = target_address - opcode_address;
7367
fddf5b5b 7368 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7369 {
47926f60
KH		 7370 /* Don't have to change opcode. */
7371 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7372 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7373 }
7374 else
7375 {
7376 if (no_cond_jump_promotion
7377 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7378 as_warn_where (fragP->fr_file, fragP->fr_line,
7379 _("long jump required"));
252b5132 7380
fddf5b5b
AM		 7381 switch (fragP->fr_subtype)
7382 {
7383 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7384 extension = 4; /* 1 opcode + 4 displacement */
7385 opcode[0] = 0xe9;
7386 where_to_put_displacement = &opcode[1];
7387 break;
252b5132 7388
fddf5b5b
AM		 7389 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7390 extension = 2; /* 1 opcode + 2 displacement */
7391 opcode[0] = 0xe9;
7392 where_to_put_displacement = &opcode[1];
7393 break;
252b5132 7394
fddf5b5b
AM		 7395 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7396 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7397 extension = 5; /* 2 opcode + 4 displacement */
7398 opcode[1] = opcode[0] + 0x10;
7399 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7400 where_to_put_displacement = &opcode[2];
7401 break;
252b5132 7402
fddf5b5b
AM		 7403 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7404 extension = 3; /* 2 opcode + 2 displacement */
7405 opcode[1] = opcode[0] + 0x10;
7406 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7407 where_to_put_displacement = &opcode[2];
7408 break;
252b5132 7409
fddf5b5b
AM		 7410 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7411 extension = 4;
7412 opcode[0] ^= 1;
7413 opcode[1] = 3;
7414 opcode[2] = 0xe9;
7415 where_to_put_displacement = &opcode[3];
7416 break;
7417
7418 default:
7419 BAD_CASE (fragP->fr_subtype);
7420 break;
7421 }
252b5132 7422 }
fddf5b5b 7423
7b81dfbb
AJ		 7424 /* If size if less then four we are sure that the operand fits,
7425 but if it's 4, then it could be that the displacement is larger
7426 then -/+ 2GB. */
7427 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7428 && object_64bit
7429 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7430 + ((addressT) 1 << 31))
7431 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7432 {
7433 as_bad_where (fragP->fr_file, fragP->fr_line,
7434 _("jump target out of range"));
7435 /* Make us emit 0. */
7436 displacement_from_opcode_start = extension;
7437 }
47926f60 7438 /* Now put displacement after opcode. */
252b5132
RH		 7439 md_number_to_chars ((char *) where_to_put_displacement,
7440 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7441 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7442 fragP->fr_fix += extension;
7443}
7444\f
252b5132
RH		 7445/* Apply a fixup (fixS) to segment data, once it has been determined
7446 by our caller that we have all the info we need to fix it up.
7447
7448 On the 386, immediates, displacements, and data pointers are all in
7449 the same (little-endian) format, so we don't need to care about which
7450 we are handling. */
7451
94f592af 7452void
55cf6793 7453md_apply_fix (fixP, valP, seg)
47926f60
KH		 7454 /* The fix we're to put in. */
7455 fixS *fixP;
47926f60 7456 /* Pointer to the value of the bits. */
c6682705 7457 valueT *valP;
47926f60
KH		 7458 /* Segment fix is from. */
7459 segT seg ATTRIBUTE_UNUSED;
252b5132 7460{
94f592af 7461 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7462 valueT value = *valP;
252b5132 7463
f86103b7 7464#if !defined (TE_Mach)
93382f6d
AM		 7465 if (fixP->fx_pcrel)
7466 {
7467 switch (fixP->fx_r_type)
7468 {
5865bb77
ILT		 7469 default:
7470 break;
7471
d6ab8113
JB		 7472 case BFD_RELOC_64:
7473 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7474 break;
93382f6d 7475 case BFD_RELOC_32:
ae8887b5 7476 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7477 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7478 break;
7479 case BFD_RELOC_16:
7480 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7481 break;
7482 case BFD_RELOC_8:
7483 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7484 break;
7485 }
7486 }
252b5132 7487
a161fe53 7488 if (fixP->fx_addsy != NULL
31312f95 7489 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7490 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7491 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7492 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7493 && !use_rela_relocations)
252b5132 7494 {
31312f95
AM		 7495 /* This is a hack. There should be a better way to handle this.
7496 This covers for the fact that bfd_install_relocation will
7497 subtract the current location (for partial_inplace, PC relative
7498 relocations); see more below. */
252b5132 7499#ifndef OBJ_AOUT
718ddfc0 7500 if (IS_ELF
252b5132
RH		 7501#ifdef TE_PE
7502 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7503#endif
7504 )
7505 value += fixP->fx_where + fixP->fx_frag->fr_address;
7506#endif
7507#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7508 if (IS_ELF)
252b5132 7509 {
6539b54b 7510 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7511
6539b54b 7512 if ((sym_seg == seg
2f66722d 7513 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7514 && sym_seg != absolute_section))
af65af87 7515 && !generic_force_reloc (fixP))
2f66722d
AM		 7516 {
7517 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7518 bfd_install_relocation subtracts them out again. I think
7519 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7520 it. FIXME. */
7521 value += fixP->fx_where + fixP->fx_frag->fr_address;
7522 }
252b5132
RH		 7523 }
7524#endif
7525#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7526 /* For some reason, the PE format does not store a
7527 section address offset for a PC relative symbol. */
7528 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7529 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7530 value += md_pcrel_from (fixP);
7531#endif
7532 }
fbeb56a4
DK		 7533#if defined (OBJ_COFF) && defined (TE_PE)
7534 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7535 {
7536 value -= S_GET_VALUE (fixP->fx_addsy);
7537 }
7538#endif
252b5132
RH		 7539
7540 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7541 and we must not disappoint it. */
252b5132 7542#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7543 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7544 switch (fixP->fx_r_type)
7545 {
7546 case BFD_RELOC_386_PLT32:
3e73aa7c 7547 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7548 /* Make the jump instruction point to the address of the operand. At
7549 runtime we merely add the offset to the actual PLT entry. */
7550 value = -4;
7551 break;
31312f95 7552
13ae64f3
JJ		 7553 case BFD_RELOC_386_TLS_GD:
7554 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7555 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7556 case BFD_RELOC_386_TLS_IE:
7557 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7558 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7559 case BFD_RELOC_X86_64_TLSGD:
7560 case BFD_RELOC_X86_64_TLSLD:
7561 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7562 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7563 value = 0; /* Fully resolved at runtime. No addend. */
7564 /* Fallthrough */
7565 case BFD_RELOC_386_TLS_LE:
7566 case BFD_RELOC_386_TLS_LDO_32:
7567 case BFD_RELOC_386_TLS_LE_32:
7568 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7569 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7570 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7571 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7572 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7573 break;
7574
67a4f2b7
AO		 7575 case BFD_RELOC_386_TLS_DESC_CALL:
7576 case BFD_RELOC_X86_64_TLSDESC_CALL:
7577 value = 0; /* Fully resolved at runtime. No addend. */
7578 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7579 fixP->fx_done = 0;
7580 return;
7581
00f7efb6
JJ		 7582 case BFD_RELOC_386_GOT32:
7583 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7584 value = 0; /* Fully resolved at runtime. No addend. */
7585 break;
47926f60
KH		 7586
7587 case BFD_RELOC_VTABLE_INHERIT:
7588 case BFD_RELOC_VTABLE_ENTRY:
7589 fixP->fx_done = 0;
94f592af 7590 return;
47926f60
KH		 7591
7592 default:
7593 break;
7594 }
7595#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7596 *valP = value;
f86103b7 7597#endif /* !defined (TE_Mach) */
3e73aa7c 7598
3e73aa7c 7599 /* Are we finished with this relocation now? */
c6682705 7600 if (fixP->fx_addsy == NULL)
3e73aa7c 7601 fixP->fx_done = 1;
fbeb56a4
DK		 7602#if defined (OBJ_COFF) && defined (TE_PE)
7603 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7604 {
7605 fixP->fx_done = 0;
7606 /* Remember value for tc_gen_reloc. */
7607 fixP->fx_addnumber = value;
7608 /* Clear out the frag for now. */
7609 value = 0;
7610 }
7611#endif
3e73aa7c
JH		 7612 else if (use_rela_relocations)
7613 {
7614 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7615 /* Remember value for tc_gen_reloc. */
7616 fixP->fx_addnumber = value;
3e73aa7c
JH		 7617 value = 0;
7618 }
f86103b7 7619
94f592af 7620 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7621}
252b5132 7622\f
252b5132 7623char *
499ac353 7624md_atof (int type, char *litP, int *sizeP)
252b5132 7625{
499ac353
NC		 7626 /* This outputs the LITTLENUMs in REVERSE order;
7627 in accord with the bigendian 386. */
7628 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7629}
7630\f
2d545b82 7631static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7632
252b5132 7633static char *
e3bb37b5 7634output_invalid (int c)
252b5132 7635{
3882b010 7636 if (ISPRINT (c))
f9f21a03
L		 7637 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7638 "'%c'", c);
252b5132 7639 else
f9f21a03 7640 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7641 "(0x%x)", (unsigned char) c);
252b5132
RH		 7642 return output_invalid_buf;
7643}
7644
af6bdddf 7645/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7646
7647static const reg_entry *
4d1bb795 7648parse_real_register (char *reg_string, char **end_op)
252b5132 7649{
af6bdddf
AM		 7650 char *s = reg_string;
7651 char *p;
252b5132
RH		 7652 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7653 const reg_entry *r;
7654
7655 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7656 if (*s == REGISTER_PREFIX)
7657 ++s;
7658
7659 if (is_space_char (*s))
7660 ++s;
7661
7662 p = reg_name_given;
af6bdddf 7663 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7664 {
7665 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7666 return (const reg_entry *) NULL;
7667 s++;
252b5132
RH		 7668 }
7669
6588847e
DN		 7670 /* For naked regs, make sure that we are not dealing with an identifier.
7671 This prevents confusing an identifier like `eax_var' with register
7672 `eax'. */
7673 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7674 return (const reg_entry *) NULL;
7675
af6bdddf 7676 *end_op = s;
252b5132
RH		 7677
7678 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7679
5f47d35b 7680 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7681 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7682 {
5f47d35b
AM		 7683 if (is_space_char (*s))
7684 ++s;
7685 if (*s == '(')
7686 {
af6bdddf 7687 ++s;
5f47d35b
AM		 7688 if (is_space_char (*s))
7689 ++s;
7690 if (*s >= '0' && *s <= '7')
7691 {
db557034 7692 int fpr = *s - '0';
af6bdddf 7693 ++s;
5f47d35b
AM		 7694 if (is_space_char (*s))
7695 ++s;
7696 if (*s == ')')
7697 {
7698 *end_op = s + 1;
1e9cc1c2 7699 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 7700 know (r);
7701 return r + fpr;
5f47d35b 7702 }
5f47d35b 7703 }
47926f60 7704 /* We have "%st(" then garbage. */
5f47d35b
AM		 7705 return (const reg_entry *) NULL;
7706 }
7707 }
7708
a60de03c
JB		 7709 if (r == NULL || allow_pseudo_reg)
7710 return r;
7711
0dfbf9d7 7712 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7713 return (const reg_entry *) NULL;
7714
192dc9c6
JB		 7715 if ((r->reg_type.bitfield.reg32
7716 || r->reg_type.bitfield.sreg3
7717 || r->reg_type.bitfield.control
7718 || r->reg_type.bitfield.debug
7719 || r->reg_type.bitfield.test)
7720 && !cpu_arch_flags.bitfield.cpui386)
7721 return (const reg_entry *) NULL;
7722
309d3373
JB		 7723 if (r->reg_type.bitfield.floatreg
7724 && !cpu_arch_flags.bitfield.cpu8087
7725 && !cpu_arch_flags.bitfield.cpu287
7726 && !cpu_arch_flags.bitfield.cpu387)
7727 return (const reg_entry *) NULL;
7728
192dc9c6
JB		 7729 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7730 return (const reg_entry *) NULL;
7731
7732 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7733 return (const reg_entry *) NULL;
7734
40f12533
L		 7735 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7736 return (const reg_entry *) NULL;
7737
db51cc60 7738 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7739 if (!allow_index_reg
db51cc60
L		 7740 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7741 return (const reg_entry *) NULL;
7742
a60de03c
JB		 7743 if (((r->reg_flags & (RegRex64 | RegRex))
7744 || r->reg_type.bitfield.reg64)
40fb9820 7745 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7746 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7747 && flag_code != CODE_64BIT)
20f0a1fc 7748 return (const reg_entry *) NULL;
1ae00879 7749
b7240065
JB		 7750 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7751 return (const reg_entry *) NULL;
7752
252b5132
RH		 7753 return r;
7754}
4d1bb795
JB		 7755
7756/* REG_STRING starts *before* REGISTER_PREFIX. */
7757
7758static const reg_entry *
7759parse_register (char *reg_string, char **end_op)
7760{
7761 const reg_entry *r;
7762
7763 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7764 r = parse_real_register (reg_string, end_op);
7765 else
7766 r = NULL;
7767 if (!r)
7768 {
7769 char *save = input_line_pointer;
7770 char c;
7771 symbolS *symbolP;
7772
7773 input_line_pointer = reg_string;
7774 c = get_symbol_end ();
7775 symbolP = symbol_find (reg_string);
7776 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7777 {
7778 const expressionS *e = symbol_get_value_expression (symbolP);
7779
7780 know (e->X_op == O_register);
4eed87de 7781 know (e->X_add_number >= 0
c3fe08fa 7782 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7783 r = i386_regtab + e->X_add_number;
7784 *end_op = input_line_pointer;
7785 }
7786 *input_line_pointer = c;
7787 input_line_pointer = save;
7788 }
7789 return r;
7790}
7791
7792int
7793i386_parse_name (char *name, expressionS *e, char *nextcharP)
7794{
7795 const reg_entry *r;
7796 char *end = input_line_pointer;
7797
7798 *end = *nextcharP;
7799 r = parse_register (name, &input_line_pointer);
7800 if (r && end <= input_line_pointer)
7801 {
7802 *nextcharP = *input_line_pointer;
7803 *input_line_pointer = 0;
7804 e->X_op = O_register;
7805 e->X_add_number = r - i386_regtab;
7806 return 1;
7807 }
7808 input_line_pointer = end;
7809 *end = 0;
ee86248c 7810 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 7811}
7812
7813void
7814md_operand (expressionS *e)
7815{
ee86248c
JB		 7816 char *end;
7817 const reg_entry *r;
4d1bb795 7818
ee86248c
JB		 7819 switch (*input_line_pointer)
7820 {
7821 case REGISTER_PREFIX:
7822 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 7823 if (r)
7824 {
7825 e->X_op = O_register;
7826 e->X_add_number = r - i386_regtab;
7827 input_line_pointer = end;
7828 }
ee86248c
JB		 7829 break;
7830
7831 case '[':
9c2799c2 7832 gas_assert (intel_syntax);
ee86248c
JB		 7833 end = input_line_pointer++;
7834 expression (e);
7835 if (*input_line_pointer == ']')
7836 {
7837 ++input_line_pointer;
7838 e->X_op_symbol = make_expr_symbol (e);
7839 e->X_add_symbol = NULL;
7840 e->X_add_number = 0;
7841 e->X_op = O_index;
7842 }
7843 else
7844 {
7845 e->X_op = O_absent;
7846 input_line_pointer = end;
7847 }
7848 break;
4d1bb795
JB		 7849 }
7850}
7851
252b5132 7852\f
4cc782b5 7853#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7854const char *md_shortopts = "kVQ:sqn";
252b5132 7855#else
12b55ccc 7856const char *md_shortopts = "qn";
252b5132 7857#endif
6e0b89ee 7858
3e73aa7c 7859#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7860#define OPTION_64 (OPTION_MD_BASE + 1)
7861#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7862#define OPTION_MARCH (OPTION_MD_BASE + 3)
7863#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7864#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7865#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7866#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7867#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7868#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 7869#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 7870#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
b3b91714 7871
99ad8390
NC		 7872struct option md_longopts[] =
7873{
3e73aa7c 7874 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 7875#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7876 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 7877 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7878#endif
b3b91714 7879 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7880 {"march", required_argument, NULL, OPTION_MARCH},
7881 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7882 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7883 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7884 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7885 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7886 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 7887 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 7888 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
252b5132
RH		 7889 {NULL, no_argument, NULL, 0}
7890};
7891size_t md_longopts_size = sizeof (md_longopts);
7892
7893int
9103f4f4 7894md_parse_option (int c, char *arg)
252b5132 7895{
91d6fa6a 7896 unsigned int j;
6305a203 7897 char *arch, *next;
9103f4f4 7898
252b5132
RH		 7899 switch (c)
7900 {
12b55ccc
L		 7901 case 'n':
7902 optimize_align_code = 0;
7903 break;
7904
a38cf1db
AM		 7905 case 'q':
7906 quiet_warnings = 1;
252b5132
RH		 7907 break;
7908
7909#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7910 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7911 should be emitted or not. FIXME: Not implemented. */
7912 case 'Q':
252b5132
RH		 7913 break;
7914
7915 /* -V: SVR4 argument to print version ID. */
7916 case 'V':
7917 print_version_id ();
7918 break;
7919
a38cf1db
AM		 7920 /* -k: Ignore for FreeBSD compatibility. */
7921 case 'k':
252b5132 7922 break;
4cc782b5
ILT		 7923
7924 case 's':
7925 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7926 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7927 break;
99ad8390 7928#endif
321098a5
L		 7929#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7930 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 7931 case OPTION_64:
7932 {
7933 const char **list, **l;
7934
3e73aa7c
JH		 7935 list = bfd_target_list ();
7936 for (l = list; *l != NULL; l++)
8620418b 7937 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7938 || strcmp (*l, "coff-x86-64") == 0
7939 || strcmp (*l, "pe-x86-64") == 0
7940 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7941 {
7942 default_arch = "x86_64";
7943 break;
7944 }
3e73aa7c 7945 if (*l == NULL)
6e0b89ee 7946 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7947 free (list);
7948 }
7949 break;
7950#endif
252b5132 7951
6e0b89ee
AM		 7952 case OPTION_32:
7953 default_arch = "i386";
7954 break;
7955
b3b91714
AM		 7956 case OPTION_DIVIDE:
7957#ifdef SVR4_COMMENT_CHARS
7958 {
7959 char *n, *t;
7960 const char *s;
7961
7962 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7963 t = n;
7964 for (s = i386_comment_chars; *s != '\0'; s++)
7965 if (*s != '/')
7966 *t++ = *s;
7967 *t = '\0';
7968 i386_comment_chars = n;
7969 }
7970#endif
7971 break;
7972
9103f4f4 7973 case OPTION_MARCH:
6305a203
L		 7974 arch = xstrdup (arg);
7975 do
9103f4f4 7976 {
6305a203
L		 7977 if (*arch == '.')
7978 as_fatal (_("Invalid -march= option: `%s'"), arg);
7979 next = strchr (arch, '+');
7980 if (next)
7981 *next++ = '\0';
91d6fa6a 7982 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 7983 {
91d6fa6a 7984 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 7985 {
6305a203 7986 /* Processor. */
91d6fa6a 7987 cpu_arch_name = cpu_arch[j].name;
6305a203 7988 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 7989 cpu_arch_flags = cpu_arch[j].flags;
7990 cpu_arch_isa = cpu_arch[j].type;
7991 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 7992 if (!cpu_arch_tune_set)
7993 {
7994 cpu_arch_tune = cpu_arch_isa;
7995 cpu_arch_tune_flags = cpu_arch_isa_flags;
7996 }
7997 break;
7998 }
91d6fa6a
NC		 7999 else if (*cpu_arch [j].name == '.'
8000 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 8001 {
8002 /* ISA entension. */
8003 i386_cpu_flags flags;
309d3373
JB		 8004
8005 if (strncmp (arch, "no", 2))
8006 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 8007 cpu_arch[j].flags);
309d3373
JB		 8008 else
8009 flags = cpu_flags_and_not (cpu_arch_flags,
91d6fa6a 8010 cpu_arch[j].flags);
0dfbf9d7 8011 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8012 {
8013 if (cpu_sub_arch_name)
8014 {
8015 char *name = cpu_sub_arch_name;
8016 cpu_sub_arch_name = concat (name,
91d6fa6a 8017 cpu_arch[j].name,
1bf57e9f 8018 (const char *) NULL);
6305a203
L		 8019 free (name);
8020 }
8021 else
91d6fa6a 8022 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203
L		 8023 cpu_arch_flags = flags;
8024 }
8025 break;
ccc9c027 8026 }
9103f4f4 8027 }
6305a203 8028
91d6fa6a 8029 if (j >= ARRAY_SIZE (cpu_arch))
6305a203
L		 8030 as_fatal (_("Invalid -march= option: `%s'"), arg);
8031
8032 arch = next;
9103f4f4 8033 }
6305a203 8034 while (next != NULL );
9103f4f4
L		 8035 break;
8036
8037 case OPTION_MTUNE:
8038 if (*arg == '.')
8039 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
91d6fa6a 8040 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8041 {
91d6fa6a 8042 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8043 {
ccc9c027 8044 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8045 cpu_arch_tune = cpu_arch [j].type;
8046 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8047 break;
8048 }
8049 }
91d6fa6a 8050 if (j >= ARRAY_SIZE (cpu_arch))
9103f4f4
L		 8051 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8052 break;
8053
1efbbeb4
L		 8054 case OPTION_MMNEMONIC:
8055 if (strcasecmp (arg, "att") == 0)
8056 intel_mnemonic = 0;
8057 else if (strcasecmp (arg, "intel") == 0)
8058 intel_mnemonic = 1;
8059 else
8060 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8061 break;
8062
8063 case OPTION_MSYNTAX:
8064 if (strcasecmp (arg, "att") == 0)
8065 intel_syntax = 0;
8066 else if (strcasecmp (arg, "intel") == 0)
8067 intel_syntax = 1;
8068 else
8069 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8070 break;
8071
8072 case OPTION_MINDEX_REG:
8073 allow_index_reg = 1;
8074 break;
8075
8076 case OPTION_MNAKED_REG:
8077 allow_naked_reg = 1;
8078 break;
8079
8080 case OPTION_MOLD_GCC:
8081 old_gcc = 1;
1efbbeb4
L		 8082 break;
8083
c0f3af97
L		 8084 case OPTION_MSSE2AVX:
8085 sse2avx = 1;
8086 break;
8087
daf50ae7
L		 8088 case OPTION_MSSE_CHECK:
8089 if (strcasecmp (arg, "error") == 0)
8090 sse_check = sse_check_error;
8091 else if (strcasecmp (arg, "warning") == 0)
8092 sse_check = sse_check_warning;
8093 else if (strcasecmp (arg, "none") == 0)
8094 sse_check = sse_check_none;
8095 else
8096 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8097 break;
8098
252b5132
RH		 8099 default:
8100 return 0;
8101 }
8102 return 1;
8103}
8104
8a2c8fef
L		 8105#define MESSAGE_TEMPLATE \
8106" "
8107
8108static void
8109show_arch (FILE *stream, int ext)
8110{
8111 static char message[] = MESSAGE_TEMPLATE;
8112 char *start = message + 27;
8113 char *p;
8114 int size = sizeof (MESSAGE_TEMPLATE);
8115 int left;
8116 const char *name;
8117 int len;
8118 unsigned int j;
8119
8120 p = start;
8121 left = size - (start - message);
8122 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8123 {
8124 /* Should it be skipped? */
8125 if (cpu_arch [j].skip)
8126 continue;
8127
8128 name = cpu_arch [j].name;
8129 len = cpu_arch [j].len;
8130 if (*name == '.')
8131 {
8132 /* It is an extension. Skip if we aren't asked to show it. */
8133 if (ext)
8134 {
8135 name++;
8136 len--;
8137 }
8138 else
8139 continue;
8140 }
8141 else if (ext)
8142 {
8143 /* It is an processor. Skip if we show only extension. */
8144 continue;
8145 }
8146
8147 /* Reserve 2 spaces for ", " or ",\0" */
8148 left -= len + 2;
8149
8150 /* Check if there is any room. */
8151 if (left >= 0)
8152 {
8153 if (p != start)
8154 {
8155 *p++ = ',';
8156 *p++ = ' ';
8157 }
8158 p = mempcpy (p, name, len);
8159 }
8160 else
8161 {
8162 /* Output the current message now and start a new one. */
8163 *p++ = ',';
8164 *p = '\0';
8165 fprintf (stream, "%s\n", message);
8166 p = start;
8167 left = size - (start - message) - len - 2;
8168
8169 gas_assert (left >= 0);
8170
8171 p = mempcpy (p, name, len);
8172 }
8173 }
8174
8175 *p = '\0';
8176 fprintf (stream, "%s\n", message);
8177}
8178
252b5132 8179void
8a2c8fef 8180md_show_usage (FILE *stream)
252b5132 8181{
4cc782b5
ILT		 8182#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8183 fprintf (stream, _("\
a38cf1db
AM		 8184 -Q ignored\n\
8185 -V print assembler version number\n\
b3b91714
AM		 8186 -k ignored\n"));
8187#endif
8188 fprintf (stream, _("\
12b55ccc 8189 -n Do not optimize code alignment\n\
b3b91714
AM		 8190 -q quieten some warnings\n"));
8191#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8192 fprintf (stream, _("\
a38cf1db 8193 -s ignored\n"));
b3b91714 8194#endif
321098a5
L		 8195#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8196 || defined (TE_PE) || defined (TE_PEP))
751d281c
L		 8197 fprintf (stream, _("\
8198 --32/--64 generate 32bit/64bit code\n"));
8199#endif
b3b91714
AM		 8200#ifdef SVR4_COMMENT_CHARS
8201 fprintf (stream, _("\
8202 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8203#else
8204 fprintf (stream, _("\
b3b91714 8205 --divide ignored\n"));
4cc782b5 8206#endif
9103f4f4 8207 fprintf (stream, _("\
6305a203 8208 -march=CPU[,+EXTENSION...]\n\
8a2c8fef
L		 8209 generate code for CPU and EXTENSION, CPU is one of:\n"));
8210 show_arch (stream, 0);
8211 fprintf (stream, _("\
8212 EXTENSION is combination of:\n"));
8213 show_arch (stream, 1);
6305a203 8214 fprintf (stream, _("\
8a2c8fef
L		 8215 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8216 show_arch (stream, 0);
ba104c83 8217 fprintf (stream, _("\
c0f3af97
L		 8218 -msse2avx encode SSE instructions with VEX prefix\n"));
8219 fprintf (stream, _("\
daf50ae7
L		 8220 -msse-check=[none|error|warning]\n\
8221 check SSE instructions\n"));
8222 fprintf (stream, _("\
ba104c83
L		 8223 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8224 fprintf (stream, _("\
8225 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8226 fprintf (stream, _("\
8227 -mindex-reg support pseudo index registers\n"));
8228 fprintf (stream, _("\
8229 -mnaked-reg don't require `%%' prefix for registers\n"));
8230 fprintf (stream, _("\
8231 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8232}
8233
3e73aa7c 8234#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8235 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8236 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8237
8238/* Pick the target format to use. */
8239
47926f60 8240const char *
e3bb37b5 8241i386_target_format (void)
252b5132 8242{
3e73aa7c 8243 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 8244 {
8245 set_code_flag (CODE_64BIT);
0dfbf9d7 8246 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8247 {
8248 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8249 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8250 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8251 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8252 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8253 cpu_arch_isa_flags.bitfield.cpui686 = 1;
bd5295b2 8254 cpu_arch_isa_flags.bitfield.cpuclflush = 1;
40fb9820 8255 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 8256 cpu_arch_isa_flags.bitfield.cpusse = 1;
8257 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
711eedef 8258 cpu_arch_isa_flags.bitfield.cpulm = 1;
40fb9820 8259 }
0dfbf9d7 8260 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8261 {
8262 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8263 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8264 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8265 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8266 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8267 cpu_arch_tune_flags.bitfield.cpui686 = 1;
bd5295b2 8268 cpu_arch_tune_flags.bitfield.cpuclflush = 1;
40fb9820 8269 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 8270 cpu_arch_tune_flags.bitfield.cpusse = 1;
8271 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8272 }
9103f4f4 8273 }
3e73aa7c 8274 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 8275 {
8276 set_code_flag (CODE_32BIT);
0dfbf9d7 8277 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8278 {
8279 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8280 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8281 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8282 }
0dfbf9d7 8283 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8284 {
8285 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8286 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8287 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8288 }
9103f4f4 8289 }
3e73aa7c
JH		 8290 else
8291 as_fatal (_("Unknown architecture"));
252b5132
RH		 8292 switch (OUTPUT_FLAVOR)
8293 {
9384f2ff 8294#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8295 case bfd_target_aout_flavour:
47926f60 8296 return AOUT_TARGET_FORMAT;
4c63da97 8297#endif
9384f2ff
AM		 8298#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8299# if defined (TE_PE) || defined (TE_PEP)
8300 case bfd_target_coff_flavour:
8301 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8302# elif defined (TE_GO32)
0561d57c
JK		 8303 case bfd_target_coff_flavour:
8304 return "coff-go32";
9384f2ff 8305# else
252b5132
RH		 8306 case bfd_target_coff_flavour:
8307 return "coff-i386";
9384f2ff 8308# endif
4c63da97 8309#endif
3e73aa7c 8310#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8311 case bfd_target_elf_flavour:
3e73aa7c 8312 {
e5cb08ac 8313 if (flag_code == CODE_64BIT)
4fa24527
JB		 8314 {
8315 object_64bit = 1;
8316 use_rela_relocations = 1;
8317 }
3632d14b 8318 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 8319 {
8320 if (flag_code != CODE_64BIT)
8321 as_fatal (_("Intel L1OM is 64bit only"));
8322 return ELF_TARGET_L1OM_FORMAT;
8323 }
8324 else
8325 return (flag_code == CODE_64BIT
8326 ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT);
3e73aa7c 8327 }
e57f8c65
TG		 8328#endif
8329#if defined (OBJ_MACH_O)
8330 case bfd_target_mach_o_flavour:
8331 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 8332#endif
252b5132
RH		 8333 default:
8334 abort ();
8335 return NULL;
8336 }
8337}
8338
47926f60 8339#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8340
8341#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8342void
8343i386_elf_emit_arch_note (void)
a847613f 8344{
718ddfc0 8345 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8346 {
8347 char *p;
8348 asection *seg = now_seg;
8349 subsegT subseg = now_subseg;
8350 Elf_Internal_Note i_note;
8351 Elf_External_Note e_note;
8352 asection *note_secp;
8353 int len;
8354
8355 /* Create the .note section. */
8356 note_secp = subseg_new (".note", 0);
8357 bfd_set_section_flags (stdoutput,
8358 note_secp,
8359 SEC_HAS_CONTENTS | SEC_READONLY);
8360
8361 /* Process the arch string. */
8362 len = strlen (cpu_arch_name);
8363
8364 i_note.namesz = len + 1;
8365 i_note.descsz = 0;
8366 i_note.type = NT_ARCH;
8367 p = frag_more (sizeof (e_note.namesz));
8368 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8369 p = frag_more (sizeof (e_note.descsz));
8370 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8371 p = frag_more (sizeof (e_note.type));
8372 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8373 p = frag_more (len + 1);
8374 strcpy (p, cpu_arch_name);
8375
8376 frag_align (2, 0, 0);
8377
8378 subseg_set (seg, subseg);
8379 }
8380}
8381#endif
252b5132 8382\f
252b5132
RH		 8383symbolS *
8384md_undefined_symbol (name)
8385 char *name;
8386{
18dc2407
ILT		 8387 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8388 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8389 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8390 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8391 {
8392 if (!GOT_symbol)
8393 {
8394 if (symbol_find (name))
8395 as_bad (_("GOT already in symbol table"));
8396 GOT_symbol = symbol_new (name, undefined_section,
8397 (valueT) 0, &zero_address_frag);
8398 };
8399 return GOT_symbol;
8400 }
252b5132
RH		 8401 return 0;
8402}
8403
8404/* Round up a section size to the appropriate boundary. */
47926f60 8405
252b5132
RH		 8406valueT
8407md_section_align (segment, size)
ab9da554 8408 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8409 valueT size;
8410{
4c63da97
AM		 8411#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8412 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8413 {
8414 /* For a.out, force the section size to be aligned. If we don't do
8415 this, BFD will align it for us, but it will not write out the
8416 final bytes of the section. This may be a bug in BFD, but it is
8417 easier to fix it here since that is how the other a.out targets
8418 work. */
8419 int align;
8420
8421 align = bfd_get_section_alignment (stdoutput, segment);
8422 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8423 }
252b5132
RH		 8424#endif
8425
8426 return size;
8427}
8428
8429/* On the i386, PC-relative offsets are relative to the start of the
8430 next instruction. That is, the address of the offset, plus its
8431 size, since the offset is always the last part of the insn. */
8432
8433long
e3bb37b5 8434md_pcrel_from (fixS *fixP)
252b5132
RH		 8435{
8436 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8437}
8438
8439#ifndef I386COFF
8440
8441static void
e3bb37b5 8442s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8443{
29b0f896 8444 int temp;
252b5132 8445
8a75718c
JB		 8446#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8447 if (IS_ELF)
8448 obj_elf_section_change_hook ();
8449#endif
252b5132
RH		 8450 temp = get_absolute_expression ();
8451 subseg_set (bss_section, (subsegT) temp);
8452 demand_empty_rest_of_line ();
8453}
8454
8455#endif
8456
252b5132 8457void
e3bb37b5 8458i386_validate_fix (fixS *fixp)
252b5132
RH		 8459{
8460 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8461 {
23df1078
JH		 8462 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8463 {
4fa24527 8464 if (!object_64bit)
23df1078
JH		 8465 abort ();
8466 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8467 }
8468 else
8469 {
4fa24527 8470 if (!object_64bit)
d6ab8113
JB		 8471 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8472 else
8473 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8474 }
252b5132
RH		 8475 fixp->fx_subsy = 0;
8476 }
8477}
8478
252b5132
RH		 8479arelent *
8480tc_gen_reloc (section, fixp)
ab9da554 8481 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8482 fixS *fixp;
8483{
8484 arelent *rel;
8485 bfd_reloc_code_real_type code;
8486
8487 switch (fixp->fx_r_type)
8488 {
3e73aa7c
JH		 8489 case BFD_RELOC_X86_64_PLT32:
8490 case BFD_RELOC_X86_64_GOT32:
8491 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8492 case BFD_RELOC_386_PLT32:
8493 case BFD_RELOC_386_GOT32:
8494 case BFD_RELOC_386_GOTOFF:
8495 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8496 case BFD_RELOC_386_TLS_GD:
8497 case BFD_RELOC_386_TLS_LDM:
8498 case BFD_RELOC_386_TLS_LDO_32:
8499 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8500 case BFD_RELOC_386_TLS_IE:
8501 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8502 case BFD_RELOC_386_TLS_LE_32:
8503 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8504 case BFD_RELOC_386_TLS_GOTDESC:
8505 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8506 case BFD_RELOC_X86_64_TLSGD:
8507 case BFD_RELOC_X86_64_TLSLD:
8508 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8509 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8510 case BFD_RELOC_X86_64_GOTTPOFF:
8511 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8512 case BFD_RELOC_X86_64_TPOFF64:
8513 case BFD_RELOC_X86_64_GOTOFF64:
8514 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8515 case BFD_RELOC_X86_64_GOT64:
8516 case BFD_RELOC_X86_64_GOTPCREL64:
8517 case BFD_RELOC_X86_64_GOTPC64:
8518 case BFD_RELOC_X86_64_GOTPLT64:
8519 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8520 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8521 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8522 case BFD_RELOC_RVA:
8523 case BFD_RELOC_VTABLE_ENTRY:
8524 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8525#ifdef TE_PE
8526 case BFD_RELOC_32_SECREL:
8527#endif
252b5132
RH		 8528 code = fixp->fx_r_type;
8529 break;
dbbaec26
L		 8530 case BFD_RELOC_X86_64_32S:
8531 if (!fixp->fx_pcrel)
8532 {
8533 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8534 code = fixp->fx_r_type;
8535 break;
8536 }
252b5132 8537 default:
93382f6d 8538 if (fixp->fx_pcrel)
252b5132 8539 {
93382f6d
AM		 8540 switch (fixp->fx_size)
8541 {
8542 default:
b091f402
AM		 8543 as_bad_where (fixp->fx_file, fixp->fx_line,
8544 _("can not do %d byte pc-relative relocation"),
8545 fixp->fx_size);
93382f6d
AM		 8546 code = BFD_RELOC_32_PCREL;
8547 break;
8548 case 1: code = BFD_RELOC_8_PCREL; break;
8549 case 2: code = BFD_RELOC_16_PCREL; break;
8550 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8551#ifdef BFD64
8552 case 8: code = BFD_RELOC_64_PCREL; break;
8553#endif
93382f6d
AM		 8554 }
8555 }
8556 else
8557 {
8558 switch (fixp->fx_size)
8559 {
8560 default:
b091f402
AM		 8561 as_bad_where (fixp->fx_file, fixp->fx_line,
8562 _("can not do %d byte relocation"),
8563 fixp->fx_size);
93382f6d
AM		 8564 code = BFD_RELOC_32;
8565 break;
8566 case 1: code = BFD_RELOC_8; break;
8567 case 2: code = BFD_RELOC_16; break;
8568 case 4: code = BFD_RELOC_32; break;
937149dd 8569#ifdef BFD64
3e73aa7c 8570 case 8: code = BFD_RELOC_64; break;
937149dd 8571#endif
93382f6d 8572 }
252b5132
RH		 8573 }
8574 break;
8575 }
252b5132 8576
d182319b
JB		 8577 if ((code == BFD_RELOC_32
8578 || code == BFD_RELOC_32_PCREL
8579 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8580 && GOT_symbol
8581 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8582 {
4fa24527 8583 if (!object_64bit)
d6ab8113
JB		 8584 code = BFD_RELOC_386_GOTPC;
8585 else
8586 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8587 }
7b81dfbb
AJ		 8588 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8589 && GOT_symbol
8590 && fixp->fx_addsy == GOT_symbol)
8591 {
8592 code = BFD_RELOC_X86_64_GOTPC64;
8593 }
252b5132
RH		 8594
8595 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8596 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8597 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8598
8599 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8600
3e73aa7c
JH		 8601 if (!use_rela_relocations)
8602 {
8603 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8604 vtable entry to be used in the relocation's section offset. */
8605 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8606 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8607#if defined (OBJ_COFF) && defined (TE_PE)
8608 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8609 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8610 else
8611#endif
c6682705 8612 rel->addend = 0;
3e73aa7c
JH		 8613 }
8614 /* Use the rela in 64bit mode. */
252b5132 8615 else
3e73aa7c 8616 {
062cd5e7
AS		 8617 if (!fixp->fx_pcrel)
8618 rel->addend = fixp->fx_offset;
8619 else
8620 switch (code)
8621 {
8622 case BFD_RELOC_X86_64_PLT32:
8623 case BFD_RELOC_X86_64_GOT32:
8624 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8625 case BFD_RELOC_X86_64_TLSGD:
8626 case BFD_RELOC_X86_64_TLSLD:
8627 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8628 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8629 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8630 rel->addend = fixp->fx_offset - fixp->fx_size;
8631 break;
8632 default:
8633 rel->addend = (section->vma
8634 - fixp->fx_size
8635 + fixp->fx_addnumber
8636 + md_pcrel_from (fixp));
8637 break;
8638 }
3e73aa7c
JH		 8639 }
8640
252b5132
RH		 8641 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8642 if (rel->howto == NULL)
8643 {
8644 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8645 _("cannot represent relocation type %s"),
252b5132
RH		 8646 bfd_get_reloc_code_name (code));
8647 /* Set howto to a garbage value so that we can keep going. */
8648 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 8649 gas_assert (rel->howto != NULL);
252b5132
RH		 8650 }
8651
8652 return rel;
8653}
8654
ee86248c 8655#include "tc-i386-intel.c"
54cfded0 8656
a60de03c
JB		 8657void
8658tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 8659{
a60de03c
JB		 8660 int saved_naked_reg;
8661 char saved_register_dot;
54cfded0 8662
a60de03c
JB		 8663 saved_naked_reg = allow_naked_reg;
8664 allow_naked_reg = 1;
8665 saved_register_dot = register_chars['.'];
8666 register_chars['.'] = '.';
8667 allow_pseudo_reg = 1;
8668 expression_and_evaluate (exp);
8669 allow_pseudo_reg = 0;
8670 register_chars['.'] = saved_register_dot;
8671 allow_naked_reg = saved_naked_reg;
8672
8673 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 8674 {
a60de03c
JB		 8675 if ((addressT) exp->X_add_number < i386_regtab_size)
8676 {
8677 exp->X_op = O_constant;
8678 exp->X_add_number = i386_regtab[exp->X_add_number]
8679 .dw2_regnum[flag_code >> 1];
8680 }
8681 else
8682 exp->X_op = O_illegal;
54cfded0 8683 }
54cfded0
AM		 8684}
8685
8686void
8687tc_x86_frame_initial_instructions (void)
8688{
a60de03c
JB		 8689 static unsigned int sp_regno[2];
8690
8691 if (!sp_regno[flag_code >> 1])
8692 {
8693 char *saved_input = input_line_pointer;
8694 char sp[][4] = {"esp", "rsp"};
8695 expressionS exp;
a4447b93 8696
a60de03c
JB		 8697 input_line_pointer = sp[flag_code >> 1];
8698 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 8699 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 8700 sp_regno[flag_code >> 1] = exp.X_add_number;
8701 input_line_pointer = saved_input;
8702 }
a4447b93 8703
a60de03c 8704 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 8705 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8706}
d2b2c203
DJ		 8707
8708int
8709i386_elf_section_type (const char *str, size_t len)
8710{
8711 if (flag_code == CODE_64BIT
8712 && len == sizeof ("unwind") - 1
8713 && strncmp (str, "unwind", 6) == 0)
8714 return SHT_X86_64_UNWIND;
8715
8716 return -1;
8717}
bb41ade5 8718
ad5fec3b
EB		 8719#ifdef TE_SOLARIS
8720void
8721i386_solaris_fix_up_eh_frame (segT sec)
8722{
8723 if (flag_code == CODE_64BIT)
8724 elf_section_type (sec) = SHT_X86_64_UNWIND;
8725}
8726#endif
8727
bb41ade5
AM		 8728#ifdef TE_PE
8729void
8730tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8731{
91d6fa6a 8732 expressionS exp;
bb41ade5 8733
91d6fa6a
NC		 8734 exp.X_op = O_secrel;
8735 exp.X_add_symbol = symbol;
8736 exp.X_add_number = 0;
8737 emit_expr (&exp, size);
bb41ade5
AM		 8738}
8739#endif
3b22753a
L		 8740
8741#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8742/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8743
01e1a5bc 8744bfd_vma
3b22753a
L		 8745x86_64_section_letter (int letter, char **ptr_msg)
8746{
8747 if (flag_code == CODE_64BIT)
8748 {
8749 if (letter == 'l')
8750 return SHF_X86_64_LARGE;
8751
8752 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8753 }
3b22753a 8754 else
64e74474 8755 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8756 return -1;
8757}
8758
01e1a5bc 8759bfd_vma
3b22753a
L		 8760x86_64_section_word (char *str, size_t len)
8761{
8620418b 8762 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8763 return SHF_X86_64_LARGE;
8764
8765 return -1;
8766}
8767
8768static void
8769handle_large_common (int small ATTRIBUTE_UNUSED)
8770{
8771 if (flag_code != CODE_64BIT)
8772 {
8773 s_comm_internal (0, elf_common_parse);
8774 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8775 }
8776 else
8777 {
8778 static segT lbss_section;
8779 asection *saved_com_section_ptr = elf_com_section_ptr;
8780 asection *saved_bss_section = bss_section;
8781
8782 if (lbss_section == NULL)
8783 {
8784 flagword applicable;
8785 segT seg = now_seg;
8786 subsegT subseg = now_subseg;
8787
8788 /* The .lbss section is for local .largecomm symbols. */
8789 lbss_section = subseg_new (".lbss", 0);
8790 applicable = bfd_applicable_section_flags (stdoutput);
8791 bfd_set_section_flags (stdoutput, lbss_section,
8792 applicable & SEC_ALLOC);
8793 seg_info (lbss_section)->bss = 1;
8794
8795 subseg_set (seg, subseg);
8796 }
8797
8798 elf_com_section_ptr = &_bfd_elf_large_com_section;
8799 bss_section = lbss_section;
8800
8801 s_comm_internal (0, elf_common_parse);
8802
8803 elf_com_section_ptr = saved_com_section_ptr;
8804 bss_section = saved_bss_section;
8805 }
8806}
8807#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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