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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
219d1afa 2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d 68#define LOCK_PREFIX 5
4e9ac44a
L		 69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
6305a203
L		 84/* Intel Syntax. Use a non-ascii letter since since it never appears
85 in instructions. */
86#define LONG_DOUBLE_MNEM_SUFFIX '\1'
87
88#define END_OF_INSN '\0'
89
90/*
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
95 END.
96 */
97typedef struct
98{
d3ce72d0
NC		 99 const insn_template *start;
100 const insn_template *end;
6305a203
L		 101}
102templates;
103
104/* 386 operand encoding bytes: see 386 book for details of this. */
105typedef struct
106{
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
110}
111modrm_byte;
112
113/* x86-64 extension prefix. */
114typedef int rex_byte;
115
6305a203
L		 116/* 386 opcode byte to code indirect addressing. */
117typedef struct
118{
119 unsigned base;
120 unsigned index;
121 unsigned scale;
122}
123sib_byte;
124
6305a203
L		 125/* x86 arch names, types and features */
126typedef struct
127{
128 const char *name; /* arch name */
8a2c8fef 129 unsigned int len; /* arch string length */
6305a203
L		 130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 132 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 133}
134arch_entry;
135
293f5f65
L		 136/* Used to turn off indicated flags. */
137typedef struct
138{
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
142}
143noarch_entry;
144
78f12dd3 145static void update_code_flag (int, int);
e3bb37b5
L		 146static void set_code_flag (int);
147static void set_16bit_gcc_code_flag (int);
148static void set_intel_syntax (int);
1efbbeb4 149static void set_intel_mnemonic (int);
db51cc60 150static void set_allow_index_reg (int);
7bab8ab5 151static void set_check (int);
e3bb37b5 152static void set_cpu_arch (int);
6482c264 153#ifdef TE_PE
e3bb37b5 154static void pe_directive_secrel (int);
6482c264 155#endif
e3bb37b5
L		 156static void signed_cons (int);
157static char *output_invalid (int c);
ee86248c
JB		 158static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
159 const char *);
160static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
161 const char *);
a7619375 162static int i386_att_operand (char *);
e3bb37b5 163static int i386_intel_operand (char *, int);
ee86248c
JB		 164static int i386_intel_simplify (expressionS *);
165static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 166static const reg_entry *parse_register (char *, char **);
167static char *parse_insn (char *, char *);
168static char *parse_operands (char *, const char *);
169static void swap_operands (void);
4d456e3d 170static void swap_2_operands (int, int);
e3bb37b5
L		 171static void optimize_imm (void);
172static void optimize_disp (void);
83b16ac6 173static const insn_template *match_template (char);
e3bb37b5
L		 174static int check_string (void);
175static int process_suffix (void);
176static int check_byte_reg (void);
177static int check_long_reg (void);
178static int check_qword_reg (void);
179static int check_word_reg (void);
180static int finalize_imm (void);
181static int process_operands (void);
182static const seg_entry *build_modrm_byte (void);
183static void output_insn (void);
184static void output_imm (fragS *, offsetT);
185static void output_disp (fragS *, offsetT);
29b0f896 186#ifndef I386COFF
e3bb37b5 187static void s_bss (int);
252b5132 188#endif
17d4e2a2
L		 189#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190static void handle_large_common (int small ATTRIBUTE_UNUSED);
191#endif
252b5132 192
a847613f 193static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 194
43234a1e
L		 195/* This struct describes rounding control and SAE in the instruction. */
196struct RC_Operation
197{
198 enum rc_type
199 {
200 rne = 0,
201 rd,
202 ru,
203 rz,
204 saeonly
205 } type;
206 int operand;
207};
208
209static struct RC_Operation rc_op;
210
211/* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214struct Mask_Operation
215{
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
219 int operand;
220};
221
222static struct Mask_Operation mask_op;
223
224/* The struct describes broadcasting, applied to OPERAND. FACTOR is
225 broadcast factor. */
226struct Broadcast_Operation
227{
8e6e0792 228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
43234a1e
L		 229 int type;
230
231 /* Index of broadcasted operand. */
232 int operand;
233};
234
235static struct Broadcast_Operation broadcast_op;
236
c0f3af97
L		 237/* VEX prefix. */
238typedef struct
239{
43234a1e
L		 240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
c0f3af97
L		 242 unsigned int length;
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
245} vex_prefix;
246
252b5132 247/* 'md_assemble ()' gathers together information and puts it into a
47926f60 248 i386_insn. */
252b5132 249
520dc8e8
AM		 250union i386_op
251 {
252 expressionS *disps;
253 expressionS *imms;
254 const reg_entry *regs;
255 };
256
a65babc9
L		 257enum i386_error
258 {
86e026a4 259 operand_size_mismatch,
a65babc9
L		 260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
264 bad_imm4,
a65babc9
L		 265 unsupported_with_intel_mnemonic,
266 unsupported_syntax,
6c30d220
L		 267 unsupported,
268 invalid_vsib_address,
7bab8ab5 269 invalid_vector_register_set,
43234a1e
L		 270 unsupported_vector_index_register,
271 unsupported_broadcast,
272 broadcast_not_on_src_operand,
273 broadcast_needed,
274 unsupported_masking,
275 mask_not_on_destination,
276 no_default_mask,
277 unsupported_rc_sae,
278 rc_sae_operand_not_last_imm,
279 invalid_register_operand,
a65babc9
L		 280 };
281
252b5132
RH		 282struct _i386_insn
283 {
47926f60 284 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 285 insn_template tm;
252b5132 286
7d5e4556
L		 287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
252b5132
RH		 289 char suffix;
290
47926f60 291 /* OPERANDS gives the number of given operands. */
252b5132
RH		 292 unsigned int operands;
293
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
47926f60 296 operands. */
252b5132
RH		 297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
298
299 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 300 use OP[i] for the corresponding operand. */
40fb9820 301 i386_operand_type types[MAX_OPERANDS];
252b5132 302
520dc8e8
AM		 303 /* Displacement expression, immediate expression, or register for each
304 operand. */
305 union i386_op op[MAX_OPERANDS];
252b5132 306
3e73aa7c
JH		 307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309#define Operand_PCrel 1
310
252b5132 311 /* Relocation type for operand */
f86103b7 312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 313
252b5132
RH		 314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
319
320 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 321 explicit segment overrides are given. */
ce8a8b2f 322 const seg_entry *seg[2];
252b5132 323
8325cc63
JB		 324 /* Copied first memory operand string, for re-checking. */
325 char *memop1_string;
326
252b5132
RH		 327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
331
332 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 333 addressing modes of this insn are encoded. */
252b5132 334 modrm_byte rm;
3e73aa7c 335 rex_byte rex;
43234a1e 336 rex_byte vrex;
252b5132 337 sib_byte sib;
c0f3af97 338 vex_prefix vex;
b6169b20 339
43234a1e
L		 340 /* Masking attributes. */
341 struct Mask_Operation *mask;
342
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
345
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
348
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
351
86fa6981
L		 352 /* Prefer load or store in encoding. */
353 enum
354 {
355 dir_encoding_default = 0,
356 dir_encoding_load,
357 dir_encoding_store
358 } dir_encoding;
891edac4 359
a501d77e
L		 360 /* Prefer 8bit or 32bit displacement in encoding. */
361 enum
362 {
363 disp_encoding_default = 0,
364 disp_encoding_8bit,
365 disp_encoding_32bit
366 } disp_encoding;
f8a5c266 367
6b6b6807
L		 368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding;
370
b6f8c7c4
L		 371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize;
373
86fa6981
L		 374 /* How to encode vector instructions. */
375 enum
376 {
377 vex_encoding_default = 0,
378 vex_encoding_vex2,
379 vex_encoding_vex3,
380 vex_encoding_evex
381 } vec_encoding;
382
d5de92cf
L		 383 /* REP prefix. */
384 const char *rep_prefix;
385
165de32a
L		 386 /* HLE prefix. */
387 const char *hle_prefix;
42164a71 388
7e8b059b
L		 389 /* Have BND prefix. */
390 const char *bnd_prefix;
391
04ef582a
L		 392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix;
394
891edac4 395 /* Error message. */
a65babc9 396 enum i386_error error;
252b5132
RH		 397 };
398
399typedef struct _i386_insn i386_insn;
400
43234a1e
L		 401/* Link RC type with corresponding string, that'll be looked for in
402 asm. */
403struct RC_name
404{
405 enum rc_type type;
406 const char *name;
407 unsigned int len;
408};
409
410static const struct RC_name RC_NamesTable[] =
411{
412 { rne, STRING_COMMA_LEN ("rn-sae") },
413 { rd, STRING_COMMA_LEN ("rd-sae") },
414 { ru, STRING_COMMA_LEN ("ru-sae") },
415 { rz, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly, STRING_COMMA_LEN ("sae") },
417};
418
252b5132
RH		 419/* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 421const char extra_symbol_chars[] = "*%-([{}"
252b5132 422#ifdef LEX_AT
32137342
NC		 423 "@"
424#endif
425#ifdef LEX_QM
426 "?"
252b5132 427#endif
32137342 428 ;
252b5132 429
29b0f896
AM		 430#if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 432 && !defined (TE_GNU) \
29b0f896 433 && !defined (TE_LINUX) \
8d63c93e 434 && !defined (TE_NACL) \
29b0f896 435 && !defined (TE_FreeBSD) \
5b806d27 436 && !defined (TE_DragonFly) \
29b0f896 437 && !defined (TE_NetBSD)))
252b5132 438/* This array holds the chars that always start a comment. If the
b3b91714
AM		 439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441const char *i386_comment_chars = "#/";
442#define SVR4_COMMENT_CHARS 1
252b5132 443#define PREFIX_SEPARATOR '\\'
252b5132 444
b3b91714
AM		 445#else
446const char *i386_comment_chars = "#";
447#define PREFIX_SEPARATOR '/'
448#endif
449
252b5132
RH		 450/* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 454 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
252b5132 457 '/' isn't otherwise defined. */
b3b91714 458const char line_comment_chars[] = "#/";
252b5132 459
63a0b638 460const char line_separator_chars[] = ";";
252b5132 461
ce8a8b2f
AM		 462/* Chars that can be used to separate mant from exp in floating point
463 nums. */
252b5132
RH		 464const char EXP_CHARS[] = "eE";
465
ce8a8b2f
AM		 466/* Chars that mean this number is a floating point constant
467 As in 0f12.456
468 or 0d1.2345e12. */
252b5132
RH		 469const char FLT_CHARS[] = "fFdDxX";
470
ce8a8b2f 471/* Tables for lexical analysis. */
252b5132
RH		 472static char mnemonic_chars[256];
473static char register_chars[256];
474static char operand_chars[256];
475static char identifier_chars[256];
476static char digit_chars[256];
477
ce8a8b2f 478/* Lexical macros. */
252b5132
RH		 479#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480#define is_operand_char(x) (operand_chars[(unsigned char) x])
481#define is_register_char(x) (register_chars[(unsigned char) x])
482#define is_space_char(x) ((x) == ' ')
483#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484#define is_digit_char(x) (digit_chars[(unsigned char) x])
485
0234cb7c 486/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 487static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
488
489/* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
47926f60 492 assembler instruction). */
252b5132 493static char save_stack[32];
ce8a8b2f 494static char *save_stack_p;
252b5132
RH		 495#define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497#define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
499
47926f60 500/* The instruction we're assembling. */
252b5132
RH		 501static i386_insn i;
502
503/* Possible templates for current insn. */
504static const templates *current_templates;
505
31b2323c
L		 506/* Per instruction expressionS buffers: max displacements & immediates. */
507static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
508static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 509
47926f60 510/* Current operand we are working on. */
ee86248c 511static int this_operand = -1;
252b5132 512
3e73aa7c
JH		 513/* We support four different modes. FLAG_CODE variable is used to distinguish
514 these. */
515
516enum flag_code {
517 CODE_32BIT,
518 CODE_16BIT,
519 CODE_64BIT };
520
521static enum flag_code flag_code;
4fa24527 522static unsigned int object_64bit;
862be3fb 523static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 524static int use_rela_relocations = 0;
525
7af8ed2d
NC		 526#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
529
351f65ca
L		 530/* The ELF ABI to use. */
531enum x86_elf_abi
532{
533 I386_ABI,
7f56bc95
L		 534 X86_64_ABI,
535 X86_64_X32_ABI
351f65ca
L		 536};
537
538static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 539#endif
351f65ca 540
167ad85b
TG		 541#if defined (TE_PE) || defined (TE_PEP)
542/* Use big object file format. */
543static int use_big_obj = 0;
544#endif
545
8dcea932
L		 546#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547/* 1 if generating code for a shared library. */
548static int shared = 0;
549#endif
550
47926f60
KH		 551/* 1 for intel syntax,
552 0 if att syntax. */
553static int intel_syntax = 0;
252b5132 554
e89c5eaa
L		 555/* 1 for Intel64 ISA,
556 0 if AMD64 ISA. */
557static int intel64;
558
1efbbeb4
L		 559/* 1 for intel mnemonic,
560 0 if att mnemonic. */
561static int intel_mnemonic = !SYSV386_COMPAT;
562
a60de03c
JB		 563/* 1 if pseudo registers are permitted. */
564static int allow_pseudo_reg = 0;
565
47926f60
KH		 566/* 1 if register prefix % not required. */
567static int allow_naked_reg = 0;
252b5132 568
33eaf5de 569/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 570 instructions supporting it, even if this prefix wasn't specified
571 explicitly. */
572static int add_bnd_prefix = 0;
573
ba104c83 574/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 575static int allow_index_reg = 0;
576
d022bddd
IT		 577/* 1 if the assembler should ignore LOCK prefix, even if it was
578 specified explicitly. */
579static int omit_lock_prefix = 0;
580
e4e00185
AS		 581/* 1 if the assembler should encode lfence, mfence, and sfence as
582 "lock addl $0, (%{re}sp)". */
583static int avoid_fence = 0;
584
0cb4071e
L		 585/* 1 if the assembler should generate relax relocations. */
586
587static int generate_relax_relocations
588 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
589
7bab8ab5 590static enum check_kind
daf50ae7 591 {
7bab8ab5
JB		 592 check_none = 0,
593 check_warning,
594 check_error
daf50ae7 595 }
7bab8ab5 596sse_check, operand_check = check_warning;
daf50ae7 597
b6f8c7c4
L		 598/* Optimization:
599 1. Clear the REX_W bit with register operand if possible.
600 2. Above plus use 128bit vector instruction to clear the full vector
601 register.
602 */
603static int optimize = 0;
604
605/* Optimization:
606 1. Clear the REX_W bit with register operand if possible.
607 2. Above plus use 128bit vector instruction to clear the full vector
608 register.
609 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
610 "testb $imm7,%r8".
611 */
612static int optimize_for_space = 0;
613
2ca3ace5
L		 614/* Register prefix used for error message. */
615static const char *register_prefix = "%";
616
47926f60
KH		 617/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
618 leave, push, and pop instructions so that gcc has the same stack
619 frame as in 32 bit mode. */
620static char stackop_size = '\0';
eecb386c 621
12b55ccc
L		 622/* Non-zero to optimize code alignment. */
623int optimize_align_code = 1;
624
47926f60
KH		 625/* Non-zero to quieten some warnings. */
626static int quiet_warnings = 0;
a38cf1db 627
47926f60
KH		 628/* CPU name. */
629static const char *cpu_arch_name = NULL;
6305a203 630static char *cpu_sub_arch_name = NULL;
a38cf1db 631
47926f60 632/* CPU feature flags. */
40fb9820
L		 633static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
634
ccc9c027
L		 635/* If we have selected a cpu we are generating instructions for. */
636static int cpu_arch_tune_set = 0;
637
9103f4f4 638/* Cpu we are generating instructions for. */
fbf3f584 639enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 640
641/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 642static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 643
ccc9c027 644/* CPU instruction set architecture used. */
fbf3f584 645enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 646
9103f4f4 647/* CPU feature flags of instruction set architecture used. */
fbf3f584 648i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 649
fddf5b5b
AM		 650/* If set, conditional jumps are not automatically promoted to handle
651 larger than a byte offset. */
652static unsigned int no_cond_jump_promotion = 0;
653
c0f3af97
L		 654/* Encode SSE instructions with VEX prefix. */
655static unsigned int sse2avx;
656
539f890d
L		 657/* Encode scalar AVX instructions with specific vector length. */
658static enum
659 {
660 vex128 = 0,
661 vex256
662 } avxscalar;
663
43234a1e
L		 664/* Encode scalar EVEX LIG instructions with specific vector length. */
665static enum
666 {
667 evexl128 = 0,
668 evexl256,
669 evexl512
670 } evexlig;
671
672/* Encode EVEX WIG instructions with specific evex.w. */
673static enum
674 {
675 evexw0 = 0,
676 evexw1
677 } evexwig;
678
d3d3c6db
IT		 679/* Value to encode in EVEX RC bits, for SAE-only instructions. */
680static enum rc_type evexrcig = rne;
681
29b0f896 682/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 683static symbolS *GOT_symbol;
29b0f896 684
a4447b93
RH		 685/* The dwarf2 return column, adjusted for 32 or 64 bit. */
686unsigned int x86_dwarf2_return_column;
687
688/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
689int x86_cie_data_alignment;
690
252b5132 691/* Interface to relax_segment.
fddf5b5b
AM		 692 There are 3 major relax states for 386 jump insns because the
693 different types of jumps add different sizes to frags when we're
694 figuring out what sort of jump to choose to reach a given label. */
252b5132 695
47926f60 696/* Types. */
93c2a809
AM		 697#define UNCOND_JUMP 0
698#define COND_JUMP 1
699#define COND_JUMP86 2
fddf5b5b 700
47926f60 701/* Sizes. */
252b5132
RH		 702#define CODE16 1
703#define SMALL 0
29b0f896 704#define SMALL16 (SMALL | CODE16)
252b5132 705#define BIG 2
29b0f896 706#define BIG16 (BIG | CODE16)
252b5132
RH		 707
708#ifndef INLINE
709#ifdef __GNUC__
710#define INLINE __inline__
711#else
712#define INLINE
713#endif
714#endif
715
fddf5b5b
AM		 716#define ENCODE_RELAX_STATE(type, size) \
717 ((relax_substateT) (((type) << 2) | (size)))
718#define TYPE_FROM_RELAX_STATE(s) \
719 ((s) >> 2)
720#define DISP_SIZE_FROM_RELAX_STATE(s) \
721 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 722
723/* This table is used by relax_frag to promote short jumps to long
724 ones where necessary. SMALL (short) jumps may be promoted to BIG
725 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
726 don't allow a short jump in a 32 bit code segment to be promoted to
727 a 16 bit offset jump because it's slower (requires data size
728 prefix), and doesn't work, unless the destination is in the bottom
729 64k of the code segment (The top 16 bits of eip are zeroed). */
730
731const relax_typeS md_relax_table[] =
732{
24eab124
AM		 733 /* The fields are:
734 1) most positive reach of this state,
735 2) most negative reach of this state,
93c2a809 736 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 737 4) which index into the table to try if we can't fit into this one. */
252b5132 738
fddf5b5b 739 /* UNCOND_JUMP states. */
93c2a809
AM		 740 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
742 /* dword jmp adds 4 bytes to frag:
743 0 extra opcode bytes, 4 displacement bytes. */
252b5132 744 {0, 0, 4, 0},
93c2a809
AM		 745 /* word jmp adds 2 byte2 to frag:
746 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 747 {0, 0, 2, 0},
748
93c2a809
AM		 749 /* COND_JUMP states. */
750 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
752 /* dword conditionals adds 5 bytes to frag:
753 1 extra opcode byte, 4 displacement bytes. */
754 {0, 0, 5, 0},
fddf5b5b 755 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 756 1 extra opcode byte, 2 displacement bytes. */
757 {0, 0, 3, 0},
758
759 /* COND_JUMP86 states. */
760 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
762 /* dword conditionals adds 5 bytes to frag:
763 1 extra opcode byte, 4 displacement bytes. */
764 {0, 0, 5, 0},
765 /* word conditionals add 4 bytes to frag:
766 1 displacement byte and a 3 byte long branch insn. */
767 {0, 0, 4, 0}
252b5132
RH		 768};
769
9103f4f4
L		 770static const arch_entry cpu_arch[] =
771{
89507696
JB		 772 /* Do not replace the first two entries - i386_target_format()
773 relies on them being there in this order. */
8a2c8fef 774 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 775 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 776 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 777 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 778 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 779 CPU_NONE_FLAGS, 0 },
8a2c8fef 780 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 781 CPU_I186_FLAGS, 0 },
8a2c8fef 782 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 783 CPU_I286_FLAGS, 0 },
8a2c8fef 784 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 785 CPU_I386_FLAGS, 0 },
8a2c8fef 786 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 787 CPU_I486_FLAGS, 0 },
8a2c8fef 788 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 789 CPU_I586_FLAGS, 0 },
8a2c8fef 790 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 791 CPU_I686_FLAGS, 0 },
8a2c8fef 792 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 793 CPU_I586_FLAGS, 0 },
8a2c8fef 794 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 795 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 796 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 797 CPU_P2_FLAGS, 0 },
8a2c8fef 798 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 799 CPU_P3_FLAGS, 0 },
8a2c8fef 800 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 801 CPU_P4_FLAGS, 0 },
8a2c8fef 802 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 803 CPU_CORE_FLAGS, 0 },
8a2c8fef 804 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 805 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 806 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 807 CPU_CORE_FLAGS, 1 },
8a2c8fef 808 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 809 CPU_CORE_FLAGS, 0 },
8a2c8fef 810 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 811 CPU_CORE2_FLAGS, 1 },
8a2c8fef 812 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 813 CPU_CORE2_FLAGS, 0 },
8a2c8fef 814 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 815 CPU_COREI7_FLAGS, 0 },
8a2c8fef 816 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 817 CPU_L1OM_FLAGS, 0 },
7a9068fe 818 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 819 CPU_K1OM_FLAGS, 0 },
81486035 820 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 821 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 822 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 823 CPU_K6_FLAGS, 0 },
8a2c8fef 824 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 825 CPU_K6_2_FLAGS, 0 },
8a2c8fef 826 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 827 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 828 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 829 CPU_K8_FLAGS, 1 },
8a2c8fef 830 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 831 CPU_K8_FLAGS, 0 },
8a2c8fef 832 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 833 CPU_K8_FLAGS, 0 },
8a2c8fef 834 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 835 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 836 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 837 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 838 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 839 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 840 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 841 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 842 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 843 CPU_BDVER4_FLAGS, 0 },
029f3522 844 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 845 CPU_ZNVER1_FLAGS, 0 },
7b458c12 846 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 847 CPU_BTVER1_FLAGS, 0 },
7b458c12 848 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 849 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 850 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 851 CPU_8087_FLAGS, 0 },
8a2c8fef 852 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 853 CPU_287_FLAGS, 0 },
8a2c8fef 854 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 855 CPU_387_FLAGS, 0 },
1848e567
L		 856 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
857 CPU_687_FLAGS, 0 },
8a2c8fef 858 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 859 CPU_MMX_FLAGS, 0 },
8a2c8fef 860 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 861 CPU_SSE_FLAGS, 0 },
8a2c8fef 862 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 863 CPU_SSE2_FLAGS, 0 },
8a2c8fef 864 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 865 CPU_SSE3_FLAGS, 0 },
8a2c8fef 866 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 867 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 868 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 869 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 870 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 871 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 872 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 873 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 874 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 875 CPU_AVX_FLAGS, 0 },
6c30d220 876 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 877 CPU_AVX2_FLAGS, 0 },
43234a1e 878 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 879 CPU_AVX512F_FLAGS, 0 },
43234a1e 880 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 881 CPU_AVX512CD_FLAGS, 0 },
43234a1e 882 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 883 CPU_AVX512ER_FLAGS, 0 },
43234a1e 884 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 885 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 886 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 887 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 888 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 889 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 890 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 891 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 892 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 893 CPU_VMX_FLAGS, 0 },
8729a6f6 894 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 895 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 896 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 897 CPU_SMX_FLAGS, 0 },
8a2c8fef 898 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 899 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 900 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 901 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 902 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 903 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 904 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 905 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 906 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 907 CPU_AES_FLAGS, 0 },
8a2c8fef 908 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 909 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 910 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 911 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 912 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 913 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 914 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 915 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 916 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 917 CPU_F16C_FLAGS, 0 },
6c30d220 918 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 919 CPU_BMI2_FLAGS, 0 },
8a2c8fef 920 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 921 CPU_FMA_FLAGS, 0 },
8a2c8fef 922 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 923 CPU_FMA4_FLAGS, 0 },
8a2c8fef 924 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 925 CPU_XOP_FLAGS, 0 },
8a2c8fef 926 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 927 CPU_LWP_FLAGS, 0 },
8a2c8fef 928 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 929 CPU_MOVBE_FLAGS, 0 },
60aa667e 930 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 931 CPU_CX16_FLAGS, 0 },
8a2c8fef 932 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 933 CPU_EPT_FLAGS, 0 },
6c30d220 934 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 935 CPU_LZCNT_FLAGS, 0 },
42164a71 936 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 937 CPU_HLE_FLAGS, 0 },
42164a71 938 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 939 CPU_RTM_FLAGS, 0 },
6c30d220 940 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 941 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 942 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 943 CPU_CLFLUSH_FLAGS, 0 },
22109423 944 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 945 CPU_NOP_FLAGS, 0 },
8a2c8fef 946 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 947 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 948 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 949 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 950 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 951 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 952 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 953 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 954 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 955 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 956 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 957 CPU_SVME_FLAGS, 1 },
8a2c8fef 958 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 959 CPU_SVME_FLAGS, 0 },
8a2c8fef 960 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 961 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 962 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 963 CPU_ABM_FLAGS, 0 },
87973e9f 964 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 965 CPU_BMI_FLAGS, 0 },
2a2a0f38 966 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 967 CPU_TBM_FLAGS, 0 },
e2e1fcde 968 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 969 CPU_ADX_FLAGS, 0 },
e2e1fcde 970 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 971 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 972 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 973 CPU_PRFCHW_FLAGS, 0 },
5c111e37 974 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 975 CPU_SMAP_FLAGS, 0 },
7e8b059b 976 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 977 CPU_MPX_FLAGS, 0 },
a0046408 978 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 979 CPU_SHA_FLAGS, 0 },
963f3586 980 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 981 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 982 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 983 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 984 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 985 CPU_SE1_FLAGS, 0 },
c5e7287a 986 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 987 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 988 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 989 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 990 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 991 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 992 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
993 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 994 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
995 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 996 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
997 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
53467f57
IT		 998 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
999 CPU_AVX512_VBMI2_FLAGS, 0 },
8cfcb765
IT		 1000 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1001 CPU_AVX512_VNNI_FLAGS, 0 },
ee6872be
IT		 1002 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1003 CPU_AVX512_BITALG_FLAGS, 0 },
029f3522 1004 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 1005 CPU_CLZERO_FLAGS, 0 },
9916071f 1006 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 1007 CPU_MWAITX_FLAGS, 0 },
8eab4136 1008 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 1009 CPU_OSPKE_FLAGS, 0 },
8bc52696 1010 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 1011 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 1012 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1013 CPU_PTWRITE_FLAGS, 0 },
d777820b
IT		 1014 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1015 CPU_IBT_FLAGS, 0 },
1016 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1017 CPU_SHSTK_FLAGS, 0 },
48521003
IT		 1018 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1019 CPU_GFNI_FLAGS, 0 },
8dcf1fad
IT		 1020 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1021 CPU_VAES_FLAGS, 0 },
ff1982d5
IT		 1022 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1023 CPU_VPCLMULQDQ_FLAGS, 0 },
3233d7d0
IT		 1024 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1025 CPU_WBNOINVD_FLAGS, 0 },
be3a8dca
IT		 1026 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1027 CPU_PCONFIG_FLAGS, 0 },
de89d0a3
IT		 1028 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1029 CPU_WAITPKG_FLAGS, 0 },
c48935d7
IT		 1030 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1031 CPU_CLDEMOTE_FLAGS, 0 },
c0a30a9f
L		 1032 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN,
1033 CPU_MOVDIRI_FLAGS, 0 },
1034 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
1035 CPU_MOVDIR64B_FLAGS, 0 },
293f5f65
L		 1036};
1037
1038static const noarch_entry cpu_noarch[] =
1039{
1040 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 1041 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1042 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1043 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 1044 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1045 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1046 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1047 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1048 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1049 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1050 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1051 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1052 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1053 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1054 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1063 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1064 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1065 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
53467f57 1066 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
8cfcb765 1067 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
ee6872be 1068 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
d777820b
IT		 1069 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1070 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
c0a30a9f
L		 1071 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
1072 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
e413e4e9
AM		 1073};
1074
704209c0 1075#ifdef I386COFF
a6c24e68
NC		 1076/* Like s_lcomm_internal in gas/read.c but the alignment string
1077 is allowed to be optional. */
1078
1079static symbolS *
1080pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1081{
1082 addressT align = 0;
1083
1084 SKIP_WHITESPACE ();
1085
7ab9ffdd 1086 if (needs_align
a6c24e68
NC		 1087 && *input_line_pointer == ',')
1088 {
1089 align = parse_align (needs_align - 1);
7ab9ffdd 1090
a6c24e68
NC		 1091 if (align == (addressT) -1)
1092 return NULL;
1093 }
1094 else
1095 {
1096 if (size >= 8)
1097 align = 3;
1098 else if (size >= 4)
1099 align = 2;
1100 else if (size >= 2)
1101 align = 1;
1102 else
1103 align = 0;
1104 }
1105
1106 bss_alloc (symbolP, size, align);
1107 return symbolP;
1108}
1109
704209c0 1110static void
a6c24e68
NC		 1111pe_lcomm (int needs_align)
1112{
1113 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1114}
704209c0 1115#endif
a6c24e68 1116
29b0f896
AM		 1117const pseudo_typeS md_pseudo_table[] =
1118{
1119#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1120 {"align", s_align_bytes, 0},
1121#else
1122 {"align", s_align_ptwo, 0},
1123#endif
1124 {"arch", set_cpu_arch, 0},
1125#ifndef I386COFF
1126 {"bss", s_bss, 0},
a6c24e68
NC		 1127#else
1128 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1129#endif
1130 {"ffloat", float_cons, 'f'},
1131 {"dfloat", float_cons, 'd'},
1132 {"tfloat", float_cons, 'x'},
1133 {"value", cons, 2},
d182319b 1134 {"slong", signed_cons, 4},
29b0f896
AM		 1135 {"noopt", s_ignore, 0},
1136 {"optim", s_ignore, 0},
1137 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1138 {"code16", set_code_flag, CODE_16BIT},
1139 {"code32", set_code_flag, CODE_32BIT},
da5f19a2 1140#ifdef BFD64
29b0f896 1141 {"code64", set_code_flag, CODE_64BIT},
da5f19a2 1142#endif
29b0f896
AM		 1143 {"intel_syntax", set_intel_syntax, 1},
1144 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1145 {"intel_mnemonic", set_intel_mnemonic, 1},
1146 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1147 {"allow_index_reg", set_allow_index_reg, 1},
1148 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1149 {"sse_check", set_check, 0},
1150 {"operand_check", set_check, 1},
3b22753a
L		 1151#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1152 {"largecomm", handle_large_common, 0},
07a53e5c 1153#else
68d20676 1154 {"file", dwarf2_directive_file, 0},
07a53e5c
RH		 1155 {"loc", dwarf2_directive_loc, 0},
1156 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1157#endif
6482c264
NC		 1158#ifdef TE_PE
1159 {"secrel32", pe_directive_secrel, 0},
1160#endif
29b0f896
AM		 1161 {0, 0, 0}
1162};
1163
1164/* For interface with expression (). */
1165extern char *input_line_pointer;
1166
1167/* Hash table for instruction mnemonic lookup. */
1168static struct hash_control *op_hash;
1169
1170/* Hash table for register lookup. */
1171static struct hash_control *reg_hash;
1172\f
ce8a8b2f
AM		 1173 /* Various efficient no-op patterns for aligning code labels.
1174 Note: Don't try to assemble the instructions in the comments.
1175 0L and 0w are not legal. */
62a02d25
L		 1176static const unsigned char f32_1[] =
1177 {0x90}; /* nop */
1178static const unsigned char f32_2[] =
1179 {0x66,0x90}; /* xchg %ax,%ax */
1180static const unsigned char f32_3[] =
1181 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1182static const unsigned char f32_4[] =
1183 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
62a02d25
L		 1184static const unsigned char f32_6[] =
1185 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1186static const unsigned char f32_7[] =
1187 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
62a02d25 1188static const unsigned char f16_3[] =
3ae729d5 1189 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
62a02d25 1190static const unsigned char f16_4[] =
3ae729d5
L		 1191 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1192static const unsigned char jump_disp8[] =
1193 {0xeb}; /* jmp disp8 */
1194static const unsigned char jump32_disp32[] =
1195 {0xe9}; /* jmp disp32 */
1196static const unsigned char jump16_disp32[] =
1197 {0x66,0xe9}; /* jmp disp32 */
62a02d25
L		 1198/* 32-bit NOPs patterns. */
1199static const unsigned char *const f32_patt[] = {
3ae729d5 1200 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
62a02d25
L		 1201};
1202/* 16-bit NOPs patterns. */
1203static const unsigned char *const f16_patt[] = {
3ae729d5 1204 f32_1, f32_2, f16_3, f16_4
62a02d25
L		 1205};
1206/* nopl (%[re]ax) */
1207static const unsigned char alt_3[] =
1208 {0x0f,0x1f,0x00};
1209/* nopl 0(%[re]ax) */
1210static const unsigned char alt_4[] =
1211 {0x0f,0x1f,0x40,0x00};
1212/* nopl 0(%[re]ax,%[re]ax,1) */
1213static const unsigned char alt_5[] =
1214 {0x0f,0x1f,0x44,0x00,0x00};
1215/* nopw 0(%[re]ax,%[re]ax,1) */
1216static const unsigned char alt_6[] =
1217 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1218/* nopl 0L(%[re]ax) */
1219static const unsigned char alt_7[] =
1220 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1221/* nopl 0L(%[re]ax,%[re]ax,1) */
1222static const unsigned char alt_8[] =
1223 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1224/* nopw 0L(%[re]ax,%[re]ax,1) */
1225static const unsigned char alt_9[] =
1226 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1227/* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1228static const unsigned char alt_10[] =
1229 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
3ae729d5
L		 1230/* data16 nopw %cs:0L(%eax,%eax,1) */
1231static const unsigned char alt_11[] =
1232 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
62a02d25
L		 1233/* 32-bit and 64-bit NOPs patterns. */
1234static const unsigned char *const alt_patt[] = {
1235 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
3ae729d5 1236 alt_9, alt_10, alt_11
62a02d25
L		 1237};
1238
1239/* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1240 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1241
1242static void
1243i386_output_nops (char *where, const unsigned char *const *patt,
1244 int count, int max_single_nop_size)
1245
1246{
3ae729d5
L		 1247 /* Place the longer NOP first. */
1248 int last;
1249 int offset;
1250 const unsigned char *nops = patt[max_single_nop_size - 1];
1251
1252 /* Use the smaller one if the requsted one isn't available. */
1253 if (nops == NULL)
62a02d25 1254 {
3ae729d5
L		 1255 max_single_nop_size--;
1256 nops = patt[max_single_nop_size - 1];
62a02d25
L		 1257 }
1258
3ae729d5
L		 1259 last = count % max_single_nop_size;
1260
1261 count -= last;
1262 for (offset = 0; offset < count; offset += max_single_nop_size)
1263 memcpy (where + offset, nops, max_single_nop_size);
1264
1265 if (last)
1266 {
1267 nops = patt[last - 1];
1268 if (nops == NULL)
1269 {
1270 /* Use the smaller one plus one-byte NOP if the needed one
1271 isn't available. */
1272 last--;
1273 nops = patt[last - 1];
1274 memcpy (where + offset, nops, last);
1275 where[offset + last] = *patt[0];
1276 }
1277 else
1278 memcpy (where + offset, nops, last);
1279 }
62a02d25
L		 1280}
1281
3ae729d5
L		 1282static INLINE int
1283fits_in_imm7 (offsetT num)
1284{
1285 return (num & 0x7f) == num;
1286}
1287
1288static INLINE int
1289fits_in_imm31 (offsetT num)
1290{
1291 return (num & 0x7fffffff) == num;
1292}
62a02d25
L		 1293
1294/* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1295 single NOP instruction LIMIT. */
1296
1297void
3ae729d5 1298i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
62a02d25 1299{
3ae729d5 1300 const unsigned char *const *patt = NULL;
62a02d25 1301 int max_single_nop_size;
3ae729d5
L		 1302 /* Maximum number of NOPs before switching to jump over NOPs. */
1303 int max_number_of_nops;
62a02d25 1304
3ae729d5 1305 switch (fragP->fr_type)
62a02d25 1306 {
3ae729d5
L		 1307 case rs_fill_nop:
1308 case rs_align_code:
1309 break;
1310 default:
62a02d25
L		 1311 return;
1312 }
1313
ccc9c027
L		 1314 /* We need to decide which NOP sequence to use for 32bit and
1315 64bit. When -mtune= is used:
4eed87de 1316
76bc74dc
L		 1317 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1318 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1319 2. For the rest, alt_patt will be used.
1320
1321 When -mtune= isn't used, alt_patt will be used if
22109423 1322 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1323 be used.
ccc9c027
L		 1324
1325 When -march= or .arch is used, we can't use anything beyond
1326 cpu_arch_isa_flags. */
1327
1328 if (flag_code == CODE_16BIT)
1329 {
3ae729d5
L		 1330 patt = f16_patt;
1331 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1332 /* Limit number of NOPs to 2 in 16-bit mode. */
1333 max_number_of_nops = 2;
252b5132 1334 }
33fef721 1335 else
ccc9c027 1336 {
fbf3f584 1337 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1338 {
1339 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1340 switch (cpu_arch_tune)
1341 {
1342 case PROCESSOR_UNKNOWN:
1343 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1344 optimize with nops. */
1345 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1346 patt = alt_patt;
ccc9c027
L		 1347 else
1348 patt = f32_patt;
1349 break;
ccc9c027
L		 1350 case PROCESSOR_PENTIUM4:
1351 case PROCESSOR_NOCONA:
ef05d495 1352 case PROCESSOR_CORE:
76bc74dc 1353 case PROCESSOR_CORE2:
bd5295b2 1354 case PROCESSOR_COREI7:
3632d14b 1355 case PROCESSOR_L1OM:
7a9068fe 1356 case PROCESSOR_K1OM:
76bc74dc 1357 case PROCESSOR_GENERIC64:
ccc9c027
L		 1358 case PROCESSOR_K6:
1359 case PROCESSOR_ATHLON:
1360 case PROCESSOR_K8:
4eed87de 1361 case PROCESSOR_AMDFAM10:
8aedb9fe 1362 case PROCESSOR_BD:
029f3522 1363 case PROCESSOR_ZNVER:
7b458c12 1364 case PROCESSOR_BT:
80b8656c 1365 patt = alt_patt;
ccc9c027 1366 break;
76bc74dc 1367 case PROCESSOR_I386:
ccc9c027
L		 1368 case PROCESSOR_I486:
1369 case PROCESSOR_PENTIUM:
2dde1948 1370 case PROCESSOR_PENTIUMPRO:
81486035 1371 case PROCESSOR_IAMCU:
ccc9c027
L		 1372 case PROCESSOR_GENERIC32:
1373 patt = f32_patt;
1374 break;
4eed87de 1375 }
ccc9c027
L		 1376 }
1377 else
1378 {
fbf3f584 1379 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1380 {
1381 case PROCESSOR_UNKNOWN:
e6a14101 1382 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1383 PROCESSOR_UNKNOWN. */
1384 abort ();
1385 break;
1386
76bc74dc 1387 case PROCESSOR_I386:
ccc9c027
L		 1388 case PROCESSOR_I486:
1389 case PROCESSOR_PENTIUM:
81486035 1390 case PROCESSOR_IAMCU:
ccc9c027
L		 1391 case PROCESSOR_K6:
1392 case PROCESSOR_ATHLON:
1393 case PROCESSOR_K8:
4eed87de 1394 case PROCESSOR_AMDFAM10:
8aedb9fe 1395 case PROCESSOR_BD:
029f3522 1396 case PROCESSOR_ZNVER:
7b458c12 1397 case PROCESSOR_BT:
ccc9c027
L		 1398 case PROCESSOR_GENERIC32:
1399 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1400 with nops. */
1401 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1402 patt = alt_patt;
ccc9c027
L		 1403 else
1404 patt = f32_patt;
1405 break;
76bc74dc
L		 1406 case PROCESSOR_PENTIUMPRO:
1407 case PROCESSOR_PENTIUM4:
1408 case PROCESSOR_NOCONA:
1409 case PROCESSOR_CORE:
ef05d495 1410 case PROCESSOR_CORE2:
bd5295b2 1411 case PROCESSOR_COREI7:
3632d14b 1412 case PROCESSOR_L1OM:
7a9068fe 1413 case PROCESSOR_K1OM:
22109423 1414 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1415 patt = alt_patt;
ccc9c027
L		 1416 else
1417 patt = f32_patt;
1418 break;
1419 case PROCESSOR_GENERIC64:
80b8656c 1420 patt = alt_patt;
ccc9c027 1421 break;
4eed87de 1422 }
ccc9c027
L		 1423 }
1424
76bc74dc
L		 1425 if (patt == f32_patt)
1426 {
3ae729d5
L		 1427 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1428 /* Limit number of NOPs to 2 for older processors. */
1429 max_number_of_nops = 2;
76bc74dc
L		 1430 }
1431 else
1432 {
3ae729d5
L		 1433 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1434 /* Limit number of NOPs to 7 for newer processors. */
1435 max_number_of_nops = 7;
1436 }
1437 }
1438
1439 if (limit == 0)
1440 limit = max_single_nop_size;
1441
1442 if (fragP->fr_type == rs_fill_nop)
1443 {
1444 /* Output NOPs for .nop directive. */
1445 if (limit > max_single_nop_size)
1446 {
1447 as_bad_where (fragP->fr_file, fragP->fr_line,
1448 _("invalid single nop size: %d "
1449 "(expect within [0, %d])"),
1450 limit, max_single_nop_size);
1451 return;
1452 }
1453 }
1454 else
1455 fragP->fr_var = count;
1456
1457 if ((count / max_single_nop_size) > max_number_of_nops)
1458 {
1459 /* Generate jump over NOPs. */
1460 offsetT disp = count - 2;
1461 if (fits_in_imm7 (disp))
1462 {
1463 /* Use "jmp disp8" if possible. */
1464 count = disp;
1465 where[0] = jump_disp8[0];
1466 where[1] = count;
1467 where += 2;
1468 }
1469 else
1470 {
1471 unsigned int size_of_jump;
1472
1473 if (flag_code == CODE_16BIT)
1474 {
1475 where[0] = jump16_disp32[0];
1476 where[1] = jump16_disp32[1];
1477 size_of_jump = 2;
1478 }
1479 else
1480 {
1481 where[0] = jump32_disp32[0];
1482 size_of_jump = 1;
1483 }
1484
1485 count -= size_of_jump + 4;
1486 if (!fits_in_imm31 (count))
1487 {
1488 as_bad_where (fragP->fr_file, fragP->fr_line,
1489 _("jump over nop padding out of range"));
1490 return;
1491 }
1492
1493 md_number_to_chars (where + size_of_jump, count, 4);
1494 where += size_of_jump + 4;
76bc74dc 1495 }
ccc9c027 1496 }
3ae729d5
L		 1497
1498 /* Generate multiple NOPs. */
1499 i386_output_nops (where, patt, count, limit);
252b5132
RH		 1500}
1501
c6fb90c8 1502static INLINE int
0dfbf9d7 1503operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1504{
0dfbf9d7 1505 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1506 {
1507 case 3:
0dfbf9d7 1508 if (x->array[2])
c6fb90c8 1509 return 0;
1a0670f3 1510 /* Fall through. */
c6fb90c8 1511 case 2:
0dfbf9d7 1512 if (x->array[1])
c6fb90c8 1513 return 0;
1a0670f3 1514 /* Fall through. */
c6fb90c8 1515 case 1:
0dfbf9d7 1516 return !x->array[0];
c6fb90c8
L		 1517 default:
1518 abort ();
1519 }
40fb9820
L		 1520}
1521
c6fb90c8 1522static INLINE void
0dfbf9d7 1523operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1524{
0dfbf9d7 1525 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1526 {
1527 case 3:
0dfbf9d7 1528 x->array[2] = v;
1a0670f3 1529 /* Fall through. */
c6fb90c8 1530 case 2:
0dfbf9d7 1531 x->array[1] = v;
1a0670f3 1532 /* Fall through. */
c6fb90c8 1533 case 1:
0dfbf9d7 1534 x->array[0] = v;
1a0670f3 1535 /* Fall through. */
c6fb90c8
L		 1536 break;
1537 default:
1538 abort ();
1539 }
1540}
40fb9820 1541
c6fb90c8 1542static INLINE int
0dfbf9d7
L		 1543operand_type_equal (const union i386_operand_type *x,
1544 const union i386_operand_type *y)
c6fb90c8 1545{
0dfbf9d7 1546 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1547 {
1548 case 3:
0dfbf9d7 1549 if (x->array[2] != y->array[2])
c6fb90c8 1550 return 0;
1a0670f3 1551 /* Fall through. */
c6fb90c8 1552 case 2:
0dfbf9d7 1553 if (x->array[1] != y->array[1])
c6fb90c8 1554 return 0;
1a0670f3 1555 /* Fall through. */
c6fb90c8 1556 case 1:
0dfbf9d7 1557 return x->array[0] == y->array[0];
c6fb90c8
L		 1558 break;
1559 default:
1560 abort ();
1561 }
1562}
40fb9820 1563
0dfbf9d7
L		 1564static INLINE int
1565cpu_flags_all_zero (const union i386_cpu_flags *x)
1566{
1567 switch (ARRAY_SIZE(x->array))
1568 {
53467f57
IT		 1569 case 4:
1570 if (x->array[3])
1571 return 0;
1572 /* Fall through. */
0dfbf9d7
L		 1573 case 3:
1574 if (x->array[2])
1575 return 0;
1a0670f3 1576 /* Fall through. */
0dfbf9d7
L		 1577 case 2:
1578 if (x->array[1])
1579 return 0;
1a0670f3 1580 /* Fall through. */
0dfbf9d7
L		 1581 case 1:
1582 return !x->array[0];
1583 default:
1584 abort ();
1585 }
1586}
1587
0dfbf9d7
L		 1588static INLINE int
1589cpu_flags_equal (const union i386_cpu_flags *x,
1590 const union i386_cpu_flags *y)
1591{
1592 switch (ARRAY_SIZE(x->array))
1593 {
53467f57
IT		 1594 case 4:
1595 if (x->array[3] != y->array[3])
1596 return 0;
1597 /* Fall through. */
0dfbf9d7
L		 1598 case 3:
1599 if (x->array[2] != y->array[2])
1600 return 0;
1a0670f3 1601 /* Fall through. */
0dfbf9d7
L		 1602 case 2:
1603 if (x->array[1] != y->array[1])
1604 return 0;
1a0670f3 1605 /* Fall through. */
0dfbf9d7
L		 1606 case 1:
1607 return x->array[0] == y->array[0];
1608 break;
1609 default:
1610 abort ();
1611 }
1612}
c6fb90c8
L		 1613
1614static INLINE int
1615cpu_flags_check_cpu64 (i386_cpu_flags f)
1616{
1617 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1618 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1619}
1620
c6fb90c8
L		 1621static INLINE i386_cpu_flags
1622cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1623{
c6fb90c8
L		 1624 switch (ARRAY_SIZE (x.array))
1625 {
53467f57
IT		 1626 case 4:
1627 x.array [3] &= y.array [3];
1628 /* Fall through. */
c6fb90c8
L		 1629 case 3:
1630 x.array [2] &= y.array [2];
1a0670f3 1631 /* Fall through. */
c6fb90c8
L		 1632 case 2:
1633 x.array [1] &= y.array [1];
1a0670f3 1634 /* Fall through. */
c6fb90c8
L		 1635 case 1:
1636 x.array [0] &= y.array [0];
1637 break;
1638 default:
1639 abort ();
1640 }
1641 return x;
1642}
40fb9820 1643
c6fb90c8
L		 1644static INLINE i386_cpu_flags
1645cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1646{
c6fb90c8 1647 switch (ARRAY_SIZE (x.array))
40fb9820 1648 {
53467f57
IT		 1649 case 4:
1650 x.array [3] |= y.array [3];
1651 /* Fall through. */
c6fb90c8
L		 1652 case 3:
1653 x.array [2] |= y.array [2];
1a0670f3 1654 /* Fall through. */
c6fb90c8
L		 1655 case 2:
1656 x.array [1] |= y.array [1];
1a0670f3 1657 /* Fall through. */
c6fb90c8
L		 1658 case 1:
1659 x.array [0] |= y.array [0];
40fb9820
L		 1660 break;
1661 default:
1662 abort ();
1663 }
40fb9820
L		 1664 return x;
1665}
1666
309d3373
JB		 1667static INLINE i386_cpu_flags
1668cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1669{
1670 switch (ARRAY_SIZE (x.array))
1671 {
53467f57
IT		 1672 case 4:
1673 x.array [3] &= ~y.array [3];
1674 /* Fall through. */
309d3373
JB		 1675 case 3:
1676 x.array [2] &= ~y.array [2];
1a0670f3 1677 /* Fall through. */
309d3373
JB		 1678 case 2:
1679 x.array [1] &= ~y.array [1];
1a0670f3 1680 /* Fall through. */
309d3373
JB		 1681 case 1:
1682 x.array [0] &= ~y.array [0];
1683 break;
1684 default:
1685 abort ();
1686 }
1687 return x;
1688}
1689
c0f3af97
L		 1690#define CPU_FLAGS_ARCH_MATCH 0x1
1691#define CPU_FLAGS_64BIT_MATCH 0x2
1692
c0f3af97 1693#define CPU_FLAGS_PERFECT_MATCH \
db12e14e 1694 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
c0f3af97
L		 1695
1696/* Return CPU flags match bits. */
3629bb00 1697
40fb9820 1698static int
d3ce72d0 1699cpu_flags_match (const insn_template *t)
40fb9820 1700{
c0f3af97
L		 1701 i386_cpu_flags x = t->cpu_flags;
1702 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1703
1704 x.bitfield.cpu64 = 0;
1705 x.bitfield.cpuno64 = 0;
1706
0dfbf9d7 1707 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1708 {
1709 /* This instruction is available on all archs. */
db12e14e 1710 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1711 }
3629bb00
L		 1712 else
1713 {
c0f3af97 1714 /* This instruction is available only on some archs. */
3629bb00
L		 1715 i386_cpu_flags cpu = cpu_arch_flags;
1716
ab592e75
JB		 1717 /* AVX512VL is no standalone feature - match it and then strip it. */
1718 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1719 return match;
1720 x.bitfield.cpuavx512vl = 0;
1721
3629bb00 1722 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1723 if (!cpu_flags_all_zero (&cpu))
1724 {
a5ff0eb2
L		 1725 if (x.bitfield.cpuavx)
1726 {
929f69fa 1727 /* We need to check a few extra flags with AVX. */
b9d49817
JB		 1728 if (cpu.bitfield.cpuavx
1729 && (!t->opcode_modifier.sse2avx || sse2avx)
1730 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
929f69fa 1731 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
b9d49817
JB		 1732 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1733 match |= CPU_FLAGS_ARCH_MATCH;
a5ff0eb2 1734 }
929f69fa
JB		 1735 else if (x.bitfield.cpuavx512f)
1736 {
1737 /* We need to check a few extra flags with AVX512F. */
1738 if (cpu.bitfield.cpuavx512f
1739 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1740 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1741 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1742 match |= CPU_FLAGS_ARCH_MATCH;
1743 }
a5ff0eb2 1744 else
db12e14e 1745 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1746 }
3629bb00 1747 }
c0f3af97 1748 return match;
40fb9820
L		 1749}
1750
c6fb90c8
L		 1751static INLINE i386_operand_type
1752operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1753{
c6fb90c8
L		 1754 switch (ARRAY_SIZE (x.array))
1755 {
1756 case 3:
1757 x.array [2] &= y.array [2];
1a0670f3 1758 /* Fall through. */
c6fb90c8
L		 1759 case 2:
1760 x.array [1] &= y.array [1];
1a0670f3 1761 /* Fall through. */
c6fb90c8
L		 1762 case 1:
1763 x.array [0] &= y.array [0];
1764 break;
1765 default:
1766 abort ();
1767 }
1768 return x;
40fb9820
L		 1769}
1770
73053c1f
JB		 1771static INLINE i386_operand_type
1772operand_type_and_not (i386_operand_type x, i386_operand_type y)
1773{
1774 switch (ARRAY_SIZE (x.array))
1775 {
1776 case 3:
1777 x.array [2] &= ~y.array [2];
1778 /* Fall through. */
1779 case 2:
1780 x.array [1] &= ~y.array [1];
1781 /* Fall through. */
1782 case 1:
1783 x.array [0] &= ~y.array [0];
1784 break;
1785 default:
1786 abort ();
1787 }
1788 return x;
1789}
1790
c6fb90c8
L		 1791static INLINE i386_operand_type
1792operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1793{
c6fb90c8 1794 switch (ARRAY_SIZE (x.array))
40fb9820 1795 {
c6fb90c8
L		 1796 case 3:
1797 x.array [2] |= y.array [2];
1a0670f3 1798 /* Fall through. */
c6fb90c8
L		 1799 case 2:
1800 x.array [1] |= y.array [1];
1a0670f3 1801 /* Fall through. */
c6fb90c8
L		 1802 case 1:
1803 x.array [0] |= y.array [0];
40fb9820
L		 1804 break;
1805 default:
1806 abort ();
1807 }
c6fb90c8
L		 1808 return x;
1809}
40fb9820 1810
c6fb90c8
L		 1811static INLINE i386_operand_type
1812operand_type_xor (i386_operand_type x, i386_operand_type y)
1813{
1814 switch (ARRAY_SIZE (x.array))
1815 {
1816 case 3:
1817 x.array [2] ^= y.array [2];
1a0670f3 1818 /* Fall through. */
c6fb90c8
L		 1819 case 2:
1820 x.array [1] ^= y.array [1];
1a0670f3 1821 /* Fall through. */
c6fb90c8
L		 1822 case 1:
1823 x.array [0] ^= y.array [0];
1824 break;
1825 default:
1826 abort ();
1827 }
40fb9820
L		 1828 return x;
1829}
1830
1831static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1832static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1833static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1834static const i386_operand_type inoutportreg
1835 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1836static const i386_operand_type reg16_inoutportreg
1837 = OPERAND_TYPE_REG16_INOUTPORTREG;
1838static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1839static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1840static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1841static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1842static const i386_operand_type anydisp
1843 = OPERAND_TYPE_ANYDISP;
40fb9820 1844static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
43234a1e 1845static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1846static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1847static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1848static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1849static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1850static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1851static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1852static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1853static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1854static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1855static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1856
1857enum operand_type
1858{
1859 reg,
40fb9820
L		 1860 imm,
1861 disp,
1862 anymem
1863};
1864
c6fb90c8 1865static INLINE int
40fb9820
L		 1866operand_type_check (i386_operand_type t, enum operand_type c)
1867{
1868 switch (c)
1869 {
1870 case reg:
dc821c5f 1871 return t.bitfield.reg;
40fb9820 1872
40fb9820
L		 1873 case imm:
1874 return (t.bitfield.imm8
1875 || t.bitfield.imm8s
1876 || t.bitfield.imm16
1877 || t.bitfield.imm32
1878 || t.bitfield.imm32s
1879 || t.bitfield.imm64);
1880
1881 case disp:
1882 return (t.bitfield.disp8
1883 || t.bitfield.disp16
1884 || t.bitfield.disp32
1885 || t.bitfield.disp32s
1886 || t.bitfield.disp64);
1887
1888 case anymem:
1889 return (t.bitfield.disp8
1890 || t.bitfield.disp16
1891 || t.bitfield.disp32
1892 || t.bitfield.disp32s
1893 || t.bitfield.disp64
1894 || t.bitfield.baseindex);
1895
1896 default:
1897 abort ();
1898 }
2cfe26b6
AM		 1899
1900 return 0;
40fb9820
L		 1901}
1902
ca0d63fe 1903/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
5c07affc
L		 1904 operand J for instruction template T. */
1905
1906static INLINE int
d3ce72d0 1907match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1908{
1909 return !((i.types[j].bitfield.byte
1910 && !t->operand_types[j].bitfield.byte)
1911 || (i.types[j].bitfield.word
1912 && !t->operand_types[j].bitfield.word)
1913 || (i.types[j].bitfield.dword
1914 && !t->operand_types[j].bitfield.dword)
1915 || (i.types[j].bitfield.qword
ca0d63fe
JB		 1916 && !t->operand_types[j].bitfield.qword)
1917 || (i.types[j].bitfield.tbyte
1918 && !t->operand_types[j].bitfield.tbyte));
5c07affc
L		 1919}
1920
1b54b8d7
JB		 1921/* Return 1 if there is no conflict in SIMD register on
1922 operand J for instruction template T. */
1923
1924static INLINE int
1925match_simd_size (const insn_template *t, unsigned int j)
1926{
1927 return !((i.types[j].bitfield.xmmword
1928 && !t->operand_types[j].bitfield.xmmword)
1929 || (i.types[j].bitfield.ymmword
1930 && !t->operand_types[j].bitfield.ymmword)
1931 || (i.types[j].bitfield.zmmword
1932 && !t->operand_types[j].bitfield.zmmword));
1933}
1934
5c07affc
L		 1935/* Return 1 if there is no conflict in any size on operand J for
1936 instruction template T. */
1937
1938static INLINE int
d3ce72d0 1939match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1940{
1941 return (match_reg_size (t, j)
1942 && !((i.types[j].bitfield.unspecified
af508cb9 1943 && !i.broadcast
5c07affc
L		 1944 && !t->operand_types[j].bitfield.unspecified)
1945 || (i.types[j].bitfield.fword
1946 && !t->operand_types[j].bitfield.fword)
1b54b8d7
JB		 1947 /* For scalar opcode templates to allow register and memory
1948 operands at the same time, some special casing is needed
d6793fa1
JB		 1949 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1950 down-conversion vpmov*. */
1b54b8d7
JB		 1951 || ((t->operand_types[j].bitfield.regsimd
1952 && !t->opcode_modifier.broadcast
d6793fa1
JB		 1953 && (t->operand_types[j].bitfield.byte
1954 || t->operand_types[j].bitfield.word
1955 || t->operand_types[j].bitfield.dword
1b54b8d7
JB		 1956 || t->operand_types[j].bitfield.qword))
1957 ? (i.types[j].bitfield.xmmword
1958 || i.types[j].bitfield.ymmword
1959 || i.types[j].bitfield.zmmword)
1960 : !match_simd_size(t, j))));
5c07affc
L		 1961}
1962
1963/* Return 1 if there is no size conflict on any operands for
1964 instruction template T. */
1965
1966static INLINE int
d3ce72d0 1967operand_size_match (const insn_template *t)
5c07affc
L		 1968{
1969 unsigned int j;
1970 int match = 1;
1971
1972 /* Don't check jump instructions. */
1973 if (t->opcode_modifier.jump
1974 || t->opcode_modifier.jumpbyte
1975 || t->opcode_modifier.jumpdword
1976 || t->opcode_modifier.jumpintersegment)
1977 return match;
1978
1979 /* Check memory and accumulator operand size. */
1980 for (j = 0; j < i.operands; j++)
1981 {
1b54b8d7
JB		 1982 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1983 && t->operand_types[j].bitfield.anysize)
5c07affc
L		 1984 continue;
1985
1b54b8d7 1986 if (t->operand_types[j].bitfield.reg
dc821c5f 1987 && !match_reg_size (t, j))
5c07affc
L		 1988 {
1989 match = 0;
1990 break;
1991 }
1992
1b54b8d7
JB		 1993 if (t->operand_types[j].bitfield.regsimd
1994 && !match_simd_size (t, j))
1995 {
1996 match = 0;
1997 break;
1998 }
1999
2000 if (t->operand_types[j].bitfield.acc
2001 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
2002 {
2003 match = 0;
2004 break;
2005 }
2006
5c07affc
L		 2007 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
2008 {
2009 match = 0;
2010 break;
2011 }
2012 }
2013
891edac4 2014 if (match)
5c07affc 2015 return match;
38e314eb 2016 else if (!t->opcode_modifier.d)
891edac4
L		 2017 {
2018mismatch:
86e026a4 2019 i.error = operand_size_mismatch;
891edac4
L		 2020 return 0;
2021 }
5c07affc
L		 2022
2023 /* Check reverse. */
9c2799c2 2024 gas_assert (i.operands == 2);
5c07affc
L		 2025
2026 match = 1;
2027 for (j = 0; j < 2; j++)
2028 {
dc821c5f
JB		 2029 if ((t->operand_types[j].bitfield.reg
2030 || t->operand_types[j].bitfield.acc)
5c07affc 2031 && !match_reg_size (t, j ? 0 : 1))
891edac4 2032 goto mismatch;
5c07affc
L		 2033
2034 if (i.types[j].bitfield.mem
2035 && !match_mem_size (t, j ? 0 : 1))
891edac4 2036 goto mismatch;
5c07affc
L		 2037 }
2038
2039 return match;
2040}
2041
c6fb90c8 2042static INLINE int
40fb9820
L		 2043operand_type_match (i386_operand_type overlap,
2044 i386_operand_type given)
2045{
2046 i386_operand_type temp = overlap;
2047
2048 temp.bitfield.jumpabsolute = 0;
7d5e4556 2049 temp.bitfield.unspecified = 0;
5c07affc
L		 2050 temp.bitfield.byte = 0;
2051 temp.bitfield.word = 0;
2052 temp.bitfield.dword = 0;
2053 temp.bitfield.fword = 0;
2054 temp.bitfield.qword = 0;
2055 temp.bitfield.tbyte = 0;
2056 temp.bitfield.xmmword = 0;
c0f3af97 2057 temp.bitfield.ymmword = 0;
43234a1e 2058 temp.bitfield.zmmword = 0;
0dfbf9d7 2059 if (operand_type_all_zero (&temp))
891edac4 2060 goto mismatch;
40fb9820 2061
891edac4
L		 2062 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2063 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2064 return 1;
2065
2066mismatch:
a65babc9 2067 i.error = operand_type_mismatch;
891edac4 2068 return 0;
40fb9820
L		 2069}
2070
7d5e4556 2071/* If given types g0 and g1 are registers they must be of the same type
10c17abd
JB		 2072 unless the expected operand type register overlap is null.
2073 Memory operand size of certain SIMD instructions is also being checked
2074 here. */
40fb9820 2075
c6fb90c8 2076static INLINE int
dc821c5f 2077operand_type_register_match (i386_operand_type g0,
40fb9820 2078 i386_operand_type t0,
40fb9820
L		 2079 i386_operand_type g1,
2080 i386_operand_type t1)
2081{
10c17abd
JB		 2082 if (!g0.bitfield.reg
2083 && !g0.bitfield.regsimd
2084 && (!operand_type_check (g0, anymem)
2085 || g0.bitfield.unspecified
2086 || !t0.bitfield.regsimd))
40fb9820
L		 2087 return 1;
2088
10c17abd
JB		 2089 if (!g1.bitfield.reg
2090 && !g1.bitfield.regsimd
2091 && (!operand_type_check (g1, anymem)
2092 || g1.bitfield.unspecified
2093 || !t1.bitfield.regsimd))
40fb9820
L		 2094 return 1;
2095
dc821c5f
JB		 2096 if (g0.bitfield.byte == g1.bitfield.byte
2097 && g0.bitfield.word == g1.bitfield.word
2098 && g0.bitfield.dword == g1.bitfield.dword
10c17abd
JB		 2099 && g0.bitfield.qword == g1.bitfield.qword
2100 && g0.bitfield.xmmword == g1.bitfield.xmmword
2101 && g0.bitfield.ymmword == g1.bitfield.ymmword
2102 && g0.bitfield.zmmword == g1.bitfield.zmmword)
40fb9820
L		 2103 return 1;
2104
dc821c5f
JB		 2105 if (!(t0.bitfield.byte & t1.bitfield.byte)
2106 && !(t0.bitfield.word & t1.bitfield.word)
2107 && !(t0.bitfield.dword & t1.bitfield.dword)
10c17abd
JB		 2108 && !(t0.bitfield.qword & t1.bitfield.qword)
2109 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2110 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2111 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
891edac4
L		 2112 return 1;
2113
a65babc9 2114 i.error = register_type_mismatch;
891edac4
L		 2115
2116 return 0;
40fb9820
L		 2117}
2118
4c692bc7
JB		 2119static INLINE unsigned int
2120register_number (const reg_entry *r)
2121{
2122 unsigned int nr = r->reg_num;
2123
2124 if (r->reg_flags & RegRex)
2125 nr += 8;
2126
200cbe0f
L		 2127 if (r->reg_flags & RegVRex)
2128 nr += 16;
2129
4c692bc7
JB		 2130 return nr;
2131}
2132
252b5132 2133static INLINE unsigned int
40fb9820 2134mode_from_disp_size (i386_operand_type t)
252b5132 2135{
b5014f7a 2136 if (t.bitfield.disp8)
40fb9820
L		 2137 return 1;
2138 else if (t.bitfield.disp16
2139 || t.bitfield.disp32
2140 || t.bitfield.disp32s)
2141 return 2;
2142 else
2143 return 0;
252b5132
RH		 2144}
2145
2146static INLINE int
65879393 2147fits_in_signed_byte (addressT num)
252b5132 2148{
65879393 2149 return num + 0x80 <= 0xff;
47926f60 2150}
252b5132
RH		 2151
2152static INLINE int
65879393 2153fits_in_unsigned_byte (addressT num)
252b5132 2154{
65879393 2155 return num <= 0xff;
47926f60 2156}
252b5132
RH		 2157
2158static INLINE int
65879393 2159fits_in_unsigned_word (addressT num)
252b5132 2160{
65879393 2161 return num <= 0xffff;
47926f60 2162}
252b5132
RH		 2163
2164static INLINE int
65879393 2165fits_in_signed_word (addressT num)
252b5132 2166{
65879393 2167 return num + 0x8000 <= 0xffff;
47926f60 2168}
2a962e6d 2169
3e73aa7c 2170static INLINE int
65879393 2171fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2172{
2173#ifndef BFD64
2174 return 1;
2175#else
65879393 2176 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2177#endif
2178} /* fits_in_signed_long() */
2a962e6d 2179
3e73aa7c 2180static INLINE int
65879393 2181fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2182{
2183#ifndef BFD64
2184 return 1;
2185#else
65879393 2186 return num <= 0xffffffff;
3e73aa7c
JH		 2187#endif
2188} /* fits_in_unsigned_long() */
252b5132 2189
43234a1e 2190static INLINE int
b5014f7a 2191fits_in_disp8 (offsetT num)
43234a1e
L		 2192{
2193 int shift = i.memshift;
2194 unsigned int mask;
2195
2196 if (shift == -1)
2197 abort ();
2198
2199 mask = (1 << shift) - 1;
2200
2201 /* Return 0 if NUM isn't properly aligned. */
2202 if ((num & mask))
2203 return 0;
2204
2205 /* Check if NUM will fit in 8bit after shift. */
2206 return fits_in_signed_byte (num >> shift);
2207}
2208
a683cc34
SP		 2209static INLINE int
2210fits_in_imm4 (offsetT num)
2211{
2212 return (num & 0xf) == num;
2213}
2214
40fb9820 2215static i386_operand_type
e3bb37b5 2216smallest_imm_type (offsetT num)
252b5132 2217{
40fb9820 2218 i386_operand_type t;
7ab9ffdd 2219
0dfbf9d7 2220 operand_type_set (&t, 0);
40fb9820
L		 2221 t.bitfield.imm64 = 1;
2222
2223 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2224 {
2225 /* This code is disabled on the 486 because all the Imm1 forms
2226 in the opcode table are slower on the i486. They're the
2227 versions with the implicitly specified single-position
2228 displacement, which has another syntax if you really want to
2229 use that form. */
40fb9820
L		 2230 t.bitfield.imm1 = 1;
2231 t.bitfield.imm8 = 1;
2232 t.bitfield.imm8s = 1;
2233 t.bitfield.imm16 = 1;
2234 t.bitfield.imm32 = 1;
2235 t.bitfield.imm32s = 1;
2236 }
2237 else if (fits_in_signed_byte (num))
2238 {
2239 t.bitfield.imm8 = 1;
2240 t.bitfield.imm8s = 1;
2241 t.bitfield.imm16 = 1;
2242 t.bitfield.imm32 = 1;
2243 t.bitfield.imm32s = 1;
2244 }
2245 else if (fits_in_unsigned_byte (num))
2246 {
2247 t.bitfield.imm8 = 1;
2248 t.bitfield.imm16 = 1;
2249 t.bitfield.imm32 = 1;
2250 t.bitfield.imm32s = 1;
2251 }
2252 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2253 {
2254 t.bitfield.imm16 = 1;
2255 t.bitfield.imm32 = 1;
2256 t.bitfield.imm32s = 1;
2257 }
2258 else if (fits_in_signed_long (num))
2259 {
2260 t.bitfield.imm32 = 1;
2261 t.bitfield.imm32s = 1;
2262 }
2263 else if (fits_in_unsigned_long (num))
2264 t.bitfield.imm32 = 1;
2265
2266 return t;
47926f60 2267}
252b5132 2268
847f7ad4 2269static offsetT
e3bb37b5 2270offset_in_range (offsetT val, int size)
847f7ad4 2271{
508866be 2272 addressT mask;
ba2adb93 2273
847f7ad4
AM		 2274 switch (size)
2275 {
508866be
L		 2276 case 1: mask = ((addressT) 1 << 8) - 1; break;
2277 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2278 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2279#ifdef BFD64
2280 case 8: mask = ((addressT) 2 << 63) - 1; break;
2281#endif
47926f60 2282 default: abort ();
847f7ad4
AM		 2283 }
2284
9de868bf
L		 2285#ifdef BFD64
2286 /* If BFD64, sign extend val for 32bit address mode. */
2287 if (flag_code != CODE_64BIT
2288 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2289 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2290 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2291#endif
ba2adb93 2292
47926f60 2293 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2294 {
2295 char buf1[40], buf2[40];
2296
2297 sprint_value (buf1, val);
2298 sprint_value (buf2, val & mask);
2299 as_warn (_("%s shortened to %s"), buf1, buf2);
2300 }
2301 return val & mask;
2302}
2303
c32fa91d
L		 2304enum PREFIX_GROUP
2305{
2306 PREFIX_EXIST = 0,
2307 PREFIX_LOCK,
2308 PREFIX_REP,
04ef582a 2309 PREFIX_DS,
c32fa91d
L		 2310 PREFIX_OTHER
2311};
2312
2313/* Returns
2314 a. PREFIX_EXIST if attempting to add a prefix where one from the
2315 same class already exists.
2316 b. PREFIX_LOCK if lock prefix is added.
2317 c. PREFIX_REP if rep/repne prefix is added.
04ef582a
L		 2318 d. PREFIX_DS if ds prefix is added.
2319 e. PREFIX_OTHER if other prefix is added.
c32fa91d
L		 2320 */
2321
2322static enum PREFIX_GROUP
e3bb37b5 2323add_prefix (unsigned int prefix)
252b5132 2324{
c32fa91d 2325 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2326 unsigned int q;
252b5132 2327
29b0f896
AM		 2328 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2329 && flag_code == CODE_64BIT)
b1905489 2330 {
161a04f6
L		 2331 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2332 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2333 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2334 ret = PREFIX_EXIST;
b1905489
JB		 2335 q = REX_PREFIX;
2336 }
3e73aa7c 2337 else
b1905489
JB		 2338 {
2339 switch (prefix)
2340 {
2341 default:
2342 abort ();
2343
b1905489 2344 case DS_PREFIX_OPCODE:
04ef582a
L		 2345 ret = PREFIX_DS;
2346 /* Fall through. */
2347 case CS_PREFIX_OPCODE:
b1905489
JB		 2348 case ES_PREFIX_OPCODE:
2349 case FS_PREFIX_OPCODE:
2350 case GS_PREFIX_OPCODE:
2351 case SS_PREFIX_OPCODE:
2352 q = SEG_PREFIX;
2353 break;
2354
2355 case REPNE_PREFIX_OPCODE:
2356 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2357 q = REP_PREFIX;
2358 ret = PREFIX_REP;
2359 break;
2360
b1905489 2361 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2362 q = LOCK_PREFIX;
2363 ret = PREFIX_LOCK;
b1905489
JB		 2364 break;
2365
2366 case FWAIT_OPCODE:
2367 q = WAIT_PREFIX;
2368 break;
2369
2370 case ADDR_PREFIX_OPCODE:
2371 q = ADDR_PREFIX;
2372 break;
2373
2374 case DATA_PREFIX_OPCODE:
2375 q = DATA_PREFIX;
2376 break;
2377 }
2378 if (i.prefix[q] != 0)
c32fa91d 2379 ret = PREFIX_EXIST;
b1905489 2380 }
252b5132 2381
b1905489 2382 if (ret)
252b5132 2383 {
b1905489
JB		 2384 if (!i.prefix[q])
2385 ++i.prefixes;
2386 i.prefix[q] |= prefix;
252b5132 2387 }
b1905489
JB		 2388 else
2389 as_bad (_("same type of prefix used twice"));
252b5132 2390
252b5132
RH		 2391 return ret;
2392}
2393
2394static void
78f12dd3 2395update_code_flag (int value, int check)
eecb386c 2396{
78f12dd3
L		 2397 PRINTF_LIKE ((*as_error));
2398
1e9cc1c2 2399 flag_code = (enum flag_code) value;
40fb9820
L		 2400 if (flag_code == CODE_64BIT)
2401 {
2402 cpu_arch_flags.bitfield.cpu64 = 1;
2403 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2404 }
2405 else
2406 {
2407 cpu_arch_flags.bitfield.cpu64 = 0;
2408 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2409 }
2410 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2411 {
78f12dd3
L		 2412 if (check)
2413 as_error = as_fatal;
2414 else
2415 as_error = as_bad;
2416 (*as_error) (_("64bit mode not supported on `%s'."),
2417 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2418 }
40fb9820 2419 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2420 {
78f12dd3
L		 2421 if (check)
2422 as_error = as_fatal;
2423 else
2424 as_error = as_bad;
2425 (*as_error) (_("32bit mode not supported on `%s'."),
2426 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2427 }
eecb386c
AM		 2428 stackop_size = '\0';
2429}
2430
78f12dd3
L		 2431static void
2432set_code_flag (int value)
2433{
2434 update_code_flag (value, 0);
2435}
2436
eecb386c 2437static void
e3bb37b5 2438set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2439{
1e9cc1c2 2440 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2441 if (flag_code != CODE_16BIT)
2442 abort ();
2443 cpu_arch_flags.bitfield.cpu64 = 0;
2444 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2445 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2446}
2447
2448static void
e3bb37b5 2449set_intel_syntax (int syntax_flag)
252b5132
RH		 2450{
2451 /* Find out if register prefixing is specified. */
2452 int ask_naked_reg = 0;
2453
2454 SKIP_WHITESPACE ();
29b0f896 2455 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2456 {
d02603dc
NC		 2457 char *string;
2458 int e = get_symbol_name (&string);
252b5132 2459
47926f60 2460 if (strcmp (string, "prefix") == 0)
252b5132 2461 ask_naked_reg = 1;
47926f60 2462 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2463 ask_naked_reg = -1;
2464 else
d0b47220 2465 as_bad (_("bad argument to syntax directive."));
d02603dc 2466 (void) restore_line_pointer (e);
252b5132
RH		 2467 }
2468 demand_empty_rest_of_line ();
c3332e24 2469
252b5132
RH		 2470 intel_syntax = syntax_flag;
2471
2472 if (ask_naked_reg == 0)
f86103b7
AM		 2473 allow_naked_reg = (intel_syntax
2474 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2475 else
2476 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2477
ee86248c 2478 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2479
e4a3b5a4 2480 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2481 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2482 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2483}
2484
1efbbeb4
L		 2485static void
2486set_intel_mnemonic (int mnemonic_flag)
2487{
e1d4d893 2488 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2489}
2490
db51cc60
L		 2491static void
2492set_allow_index_reg (int flag)
2493{
2494 allow_index_reg = flag;
2495}
2496
cb19c032 2497static void
7bab8ab5 2498set_check (int what)
cb19c032 2499{
7bab8ab5
JB		 2500 enum check_kind *kind;
2501 const char *str;
2502
2503 if (what)
2504 {
2505 kind = &operand_check;
2506 str = "operand";
2507 }
2508 else
2509 {
2510 kind = &sse_check;
2511 str = "sse";
2512 }
2513
cb19c032
L		 2514 SKIP_WHITESPACE ();
2515
2516 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2517 {
d02603dc
NC		 2518 char *string;
2519 int e = get_symbol_name (&string);
cb19c032
L		 2520
2521 if (strcmp (string, "none") == 0)
7bab8ab5 2522 *kind = check_none;
cb19c032 2523 else if (strcmp (string, "warning") == 0)
7bab8ab5 2524 *kind = check_warning;
cb19c032 2525 else if (strcmp (string, "error") == 0)
7bab8ab5 2526 *kind = check_error;
cb19c032 2527 else
7bab8ab5 2528 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2529 (void) restore_line_pointer (e);
cb19c032
L		 2530 }
2531 else
7bab8ab5 2532 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2533
2534 demand_empty_rest_of_line ();
2535}
2536
8a9036a4
L		 2537static void
2538check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2539 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2540{
2541#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2542 static const char *arch;
2543
2544 /* Intel LIOM is only supported on ELF. */
2545 if (!IS_ELF)
2546 return;
2547
2548 if (!arch)
2549 {
2550 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2551 use default_arch. */
2552 arch = cpu_arch_name;
2553 if (!arch)
2554 arch = default_arch;
2555 }
2556
81486035
L		 2557 /* If we are targeting Intel MCU, we must enable it. */
2558 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2559 || new_flag.bitfield.cpuiamcu)
2560 return;
2561
3632d14b 2562 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2563 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2564 || new_flag.bitfield.cpul1om)
8a9036a4 2565 return;
76ba9986 2566
7a9068fe
L		 2567 /* If we are targeting Intel K1OM, we must enable it. */
2568 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2569 || new_flag.bitfield.cpuk1om)
2570 return;
2571
8a9036a4
L		 2572 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2573#endif
2574}
2575
e413e4e9 2576static void
e3bb37b5 2577set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2578{
47926f60 2579 SKIP_WHITESPACE ();
e413e4e9 2580
29b0f896 2581 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2582 {
d02603dc
NC		 2583 char *string;
2584 int e = get_symbol_name (&string);
91d6fa6a 2585 unsigned int j;
40fb9820 2586 i386_cpu_flags flags;
e413e4e9 2587
91d6fa6a 2588 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2589 {
91d6fa6a 2590 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2591 {
91d6fa6a 2592 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2593
5c6af06e
JB		 2594 if (*string != '.')
2595 {
91d6fa6a 2596 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2597 cpu_sub_arch_name = NULL;
91d6fa6a 2598 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2599 if (flag_code == CODE_64BIT)
2600 {
2601 cpu_arch_flags.bitfield.cpu64 = 1;
2602 cpu_arch_flags.bitfield.cpuno64 = 0;
2603 }
2604 else
2605 {
2606 cpu_arch_flags.bitfield.cpu64 = 0;
2607 cpu_arch_flags.bitfield.cpuno64 = 1;
2608 }
91d6fa6a
NC		 2609 cpu_arch_isa = cpu_arch[j].type;
2610 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2611 if (!cpu_arch_tune_set)
2612 {
2613 cpu_arch_tune = cpu_arch_isa;
2614 cpu_arch_tune_flags = cpu_arch_isa_flags;
2615 }
5c6af06e
JB		 2616 break;
2617 }
40fb9820 2618
293f5f65
L		 2619 flags = cpu_flags_or (cpu_arch_flags,
2620 cpu_arch[j].flags);
81486035 2621
5b64d091 2622 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2623 {
6305a203
L		 2624 if (cpu_sub_arch_name)
2625 {
2626 char *name = cpu_sub_arch_name;
2627 cpu_sub_arch_name = concat (name,
91d6fa6a 2628 cpu_arch[j].name,
1bf57e9f 2629 (const char *) NULL);
6305a203
L		 2630 free (name);
2631 }
2632 else
91d6fa6a 2633 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2634 cpu_arch_flags = flags;
a586129e 2635 cpu_arch_isa_flags = flags;
5c6af06e 2636 }
0089dace
L		 2637 else
2638 cpu_arch_isa_flags
2639 = cpu_flags_or (cpu_arch_isa_flags,
2640 cpu_arch[j].flags);
d02603dc 2641 (void) restore_line_pointer (e);
5c6af06e
JB		 2642 demand_empty_rest_of_line ();
2643 return;
e413e4e9
AM		 2644 }
2645 }
293f5f65
L		 2646
2647 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2648 {
33eaf5de 2649 /* Disable an ISA extension. */
293f5f65
L		 2650 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2651 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2652 {
2653 flags = cpu_flags_and_not (cpu_arch_flags,
2654 cpu_noarch[j].flags);
2655 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2656 {
2657 if (cpu_sub_arch_name)
2658 {
2659 char *name = cpu_sub_arch_name;
2660 cpu_sub_arch_name = concat (name, string,
2661 (const char *) NULL);
2662 free (name);
2663 }
2664 else
2665 cpu_sub_arch_name = xstrdup (string);
2666 cpu_arch_flags = flags;
2667 cpu_arch_isa_flags = flags;
2668 }
2669 (void) restore_line_pointer (e);
2670 demand_empty_rest_of_line ();
2671 return;
2672 }
2673
2674 j = ARRAY_SIZE (cpu_arch);
2675 }
2676
91d6fa6a 2677 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2678 as_bad (_("no such architecture: `%s'"), string);
2679
2680 *input_line_pointer = e;
2681 }
2682 else
2683 as_bad (_("missing cpu architecture"));
2684
fddf5b5b
AM		 2685 no_cond_jump_promotion = 0;
2686 if (*input_line_pointer == ','
29b0f896 2687 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2688 {
d02603dc
NC		 2689 char *string;
2690 char e;
2691
2692 ++input_line_pointer;
2693 e = get_symbol_name (&string);
fddf5b5b
AM		 2694
2695 if (strcmp (string, "nojumps") == 0)
2696 no_cond_jump_promotion = 1;
2697 else if (strcmp (string, "jumps") == 0)
2698 ;
2699 else
2700 as_bad (_("no such architecture modifier: `%s'"), string);
2701
d02603dc 2702 (void) restore_line_pointer (e);
fddf5b5b
AM		 2703 }
2704
e413e4e9
AM		 2705 demand_empty_rest_of_line ();
2706}
2707
8a9036a4
L		 2708enum bfd_architecture
2709i386_arch (void)
2710{
3632d14b 2711 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2712 {
2713 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2714 || flag_code != CODE_64BIT)
2715 as_fatal (_("Intel L1OM is 64bit ELF only"));
2716 return bfd_arch_l1om;
2717 }
7a9068fe
L		 2718 else if (cpu_arch_isa == PROCESSOR_K1OM)
2719 {
2720 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2721 || flag_code != CODE_64BIT)
2722 as_fatal (_("Intel K1OM is 64bit ELF only"));
2723 return bfd_arch_k1om;
2724 }
81486035
L		 2725 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2726 {
2727 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2728 || flag_code == CODE_64BIT)
2729 as_fatal (_("Intel MCU is 32bit ELF only"));
2730 return bfd_arch_iamcu;
2731 }
8a9036a4
L		 2732 else
2733 return bfd_arch_i386;
2734}
2735
b9d79e03 2736unsigned long
7016a5d5 2737i386_mach (void)
b9d79e03 2738{
351f65ca 2739 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2740 {
3632d14b 2741 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2742 {
351f65ca
L		 2743 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2744 || default_arch[6] != '\0')
8a9036a4
L		 2745 as_fatal (_("Intel L1OM is 64bit ELF only"));
2746 return bfd_mach_l1om;
2747 }
7a9068fe
L		 2748 else if (cpu_arch_isa == PROCESSOR_K1OM)
2749 {
2750 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2751 || default_arch[6] != '\0')
2752 as_fatal (_("Intel K1OM is 64bit ELF only"));
2753 return bfd_mach_k1om;
2754 }
351f65ca 2755 else if (default_arch[6] == '\0')
8a9036a4 2756 return bfd_mach_x86_64;
351f65ca
L		 2757 else
2758 return bfd_mach_x64_32;
8a9036a4 2759 }
5197d474
L		 2760 else if (!strcmp (default_arch, "i386")
2761 || !strcmp (default_arch, "iamcu"))
81486035
L		 2762 {
2763 if (cpu_arch_isa == PROCESSOR_IAMCU)
2764 {
2765 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2766 as_fatal (_("Intel MCU is 32bit ELF only"));
2767 return bfd_mach_i386_iamcu;
2768 }
2769 else
2770 return bfd_mach_i386_i386;
2771 }
b9d79e03 2772 else
2b5d6a91 2773 as_fatal (_("unknown architecture"));
b9d79e03 2774}
b9d79e03 2775\f
252b5132 2776void
7016a5d5 2777md_begin (void)
252b5132
RH		 2778{
2779 const char *hash_err;
2780
86fa6981
L		 2781 /* Support pseudo prefixes like {disp32}. */
2782 lex_type ['{'] = LEX_BEGIN_NAME;
2783
47926f60 2784 /* Initialize op_hash hash table. */
252b5132
RH		 2785 op_hash = hash_new ();
2786
2787 {
d3ce72d0 2788 const insn_template *optab;
29b0f896 2789 templates *core_optab;
252b5132 2790
47926f60
KH		 2791 /* Setup for loop. */
2792 optab = i386_optab;
add39d23 2793 core_optab = XNEW (templates);
252b5132
RH		 2794 core_optab->start = optab;
2795
2796 while (1)
2797 {
2798 ++optab;
2799 if (optab->name == NULL
2800 || strcmp (optab->name, (optab - 1)->name) != 0)
2801 {
2802 /* different name --> ship out current template list;
47926f60 2803 add to hash table; & begin anew. */
252b5132
RH		 2804 core_optab->end = optab;
2805 hash_err = hash_insert (op_hash,
2806 (optab - 1)->name,
5a49b8ac 2807 (void *) core_optab);
252b5132
RH		 2808 if (hash_err)
2809 {
b37df7c4 2810 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2811 (optab - 1)->name,
2812 hash_err);
2813 }
2814 if (optab->name == NULL)
2815 break;
add39d23 2816 core_optab = XNEW (templates);
252b5132
RH		 2817 core_optab->start = optab;
2818 }
2819 }
2820 }
2821
47926f60 2822 /* Initialize reg_hash hash table. */
252b5132
RH		 2823 reg_hash = hash_new ();
2824 {
29b0f896 2825 const reg_entry *regtab;
c3fe08fa 2826 unsigned int regtab_size = i386_regtab_size;
252b5132 2827
c3fe08fa 2828 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2829 {
5a49b8ac 2830 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2831 if (hash_err)
b37df7c4 2832 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2833 regtab->reg_name,
2834 hash_err);
252b5132
RH		 2835 }
2836 }
2837
47926f60 2838 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2839 {
29b0f896
AM		 2840 int c;
2841 char *p;
252b5132
RH		 2842
2843 for (c = 0; c < 256; c++)
2844 {
3882b010 2845 if (ISDIGIT (c))
252b5132
RH		 2846 {
2847 digit_chars[c] = c;
2848 mnemonic_chars[c] = c;
2849 register_chars[c] = c;
2850 operand_chars[c] = c;
2851 }
3882b010 2852 else if (ISLOWER (c))
252b5132
RH		 2853 {
2854 mnemonic_chars[c] = c;
2855 register_chars[c] = c;
2856 operand_chars[c] = c;
2857 }
3882b010 2858 else if (ISUPPER (c))
252b5132 2859 {
3882b010 2860 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2861 register_chars[c] = mnemonic_chars[c];
2862 operand_chars[c] = c;
2863 }
43234a1e 2864 else if (c == '{' || c == '}')
86fa6981
L		 2865 {
2866 mnemonic_chars[c] = c;
2867 operand_chars[c] = c;
2868 }
252b5132 2869
3882b010 2870 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2871 identifier_chars[c] = c;
2872 else if (c >= 128)
2873 {
2874 identifier_chars[c] = c;
2875 operand_chars[c] = c;
2876 }
2877 }
2878
2879#ifdef LEX_AT
2880 identifier_chars['@'] = '@';
32137342
NC		 2881#endif
2882#ifdef LEX_QM
2883 identifier_chars['?'] = '?';
2884 operand_chars['?'] = '?';
252b5132 2885#endif
252b5132 2886 digit_chars['-'] = '-';
c0f3af97 2887 mnemonic_chars['_'] = '_';
791fe849 2888 mnemonic_chars['-'] = '-';
0003779b 2889 mnemonic_chars['.'] = '.';
252b5132
RH		 2890 identifier_chars['_'] = '_';
2891 identifier_chars['.'] = '.';
2892
2893 for (p = operand_special_chars; *p != '\0'; p++)
2894 operand_chars[(unsigned char) *p] = *p;
2895 }
2896
a4447b93
RH		 2897 if (flag_code == CODE_64BIT)
2898 {
ca19b261
KT		 2899#if defined (OBJ_COFF) && defined (TE_PE)
2900 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2901 ? 32 : 16);
2902#else
a4447b93 2903 x86_dwarf2_return_column = 16;
ca19b261 2904#endif
61ff971f 2905 x86_cie_data_alignment = -8;
a4447b93
RH		 2906 }
2907 else
2908 {
2909 x86_dwarf2_return_column = 8;
2910 x86_cie_data_alignment = -4;
2911 }
252b5132
RH		 2912}
2913
2914void
e3bb37b5 2915i386_print_statistics (FILE *file)
252b5132
RH		 2916{
2917 hash_print_statistics (file, "i386 opcode", op_hash);
2918 hash_print_statistics (file, "i386 register", reg_hash);
2919}
2920\f
252b5132
RH		 2921#ifdef DEBUG386
2922
ce8a8b2f 2923/* Debugging routines for md_assemble. */
d3ce72d0 2924static void pte (insn_template *);
40fb9820 2925static void pt (i386_operand_type);
e3bb37b5
L		 2926static void pe (expressionS *);
2927static void ps (symbolS *);
252b5132
RH		 2928
2929static void
e3bb37b5 2930pi (char *line, i386_insn *x)
252b5132 2931{
09137c09 2932 unsigned int j;
252b5132
RH		 2933
2934 fprintf (stdout, "%s: template ", line);
2935 pte (&x->tm);
09f131f2
JH		 2936 fprintf (stdout, " address: base %s index %s scale %x\n",
2937 x->base_reg ? x->base_reg->reg_name : "none",
2938 x->index_reg ? x->index_reg->reg_name : "none",
2939 x->log2_scale_factor);
2940 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2941 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2942 fprintf (stdout, " sib: base %x index %x scale %x\n",
2943 x->sib.base, x->sib.index, x->sib.scale);
2944 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2945 (x->rex & REX_W) != 0,
2946 (x->rex & REX_R) != 0,
2947 (x->rex & REX_X) != 0,
2948 (x->rex & REX_B) != 0);
09137c09 2949 for (j = 0; j < x->operands; j++)
252b5132 2950 {
09137c09
SP		 2951 fprintf (stdout, " #%d: ", j + 1);
2952 pt (x->types[j]);
252b5132 2953 fprintf (stdout, "\n");
dc821c5f 2954 if (x->types[j].bitfield.reg
09137c09 2955 || x->types[j].bitfield.regmmx
1b54b8d7 2956 || x->types[j].bitfield.regsimd
09137c09
SP		 2957 || x->types[j].bitfield.sreg2
2958 || x->types[j].bitfield.sreg3
2959 || x->types[j].bitfield.control
2960 || x->types[j].bitfield.debug
2961 || x->types[j].bitfield.test)
2962 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2963 if (operand_type_check (x->types[j], imm))
2964 pe (x->op[j].imms);
2965 if (operand_type_check (x->types[j], disp))
2966 pe (x->op[j].disps);
252b5132
RH		 2967 }
2968}
2969
2970static void
d3ce72d0 2971pte (insn_template *t)
252b5132 2972{
09137c09 2973 unsigned int j;
252b5132 2974 fprintf (stdout, " %d operands ", t->operands);
47926f60 2975 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2976 if (t->extension_opcode != None)
2977 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2978 if (t->opcode_modifier.d)
252b5132 2979 fprintf (stdout, "D");
40fb9820 2980 if (t->opcode_modifier.w)
252b5132
RH		 2981 fprintf (stdout, "W");
2982 fprintf (stdout, "\n");
09137c09 2983 for (j = 0; j < t->operands; j++)
252b5132 2984 {
09137c09
SP		 2985 fprintf (stdout, " #%d type ", j + 1);
2986 pt (t->operand_types[j]);
252b5132
RH		 2987 fprintf (stdout, "\n");
2988 }
2989}
2990
2991static void
e3bb37b5 2992pe (expressionS *e)
252b5132 2993{
24eab124 2994 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2995 fprintf (stdout, " add_number %ld (%lx)\n",
2996 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2997 if (e->X_add_symbol)
2998 {
2999 fprintf (stdout, " add_symbol ");
3000 ps (e->X_add_symbol);
3001 fprintf (stdout, "\n");
3002 }
3003 if (e->X_op_symbol)
3004 {
3005 fprintf (stdout, " op_symbol ");
3006 ps (e->X_op_symbol);
3007 fprintf (stdout, "\n");
3008 }
3009}
3010
3011static void
e3bb37b5 3012ps (symbolS *s)
252b5132
RH		 3013{
3014 fprintf (stdout, "%s type %s%s",
3015 S_GET_NAME (s),
3016 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3017 segment_name (S_GET_SEGMENT (s)));
3018}
3019
7b81dfbb 3020static struct type_name
252b5132 3021 {
40fb9820
L		 3022 i386_operand_type mask;
3023 const char *name;
252b5132 3024 }
7b81dfbb 3025const type_names[] =
252b5132 3026{
40fb9820
L		 3027 { OPERAND_TYPE_REG8, "r8" },
3028 { OPERAND_TYPE_REG16, "r16" },
3029 { OPERAND_TYPE_REG32, "r32" },
3030 { OPERAND_TYPE_REG64, "r64" },
3031 { OPERAND_TYPE_IMM8, "i8" },
3032 { OPERAND_TYPE_IMM8, "i8s" },
3033 { OPERAND_TYPE_IMM16, "i16" },
3034 { OPERAND_TYPE_IMM32, "i32" },
3035 { OPERAND_TYPE_IMM32S, "i32s" },
3036 { OPERAND_TYPE_IMM64, "i64" },
3037 { OPERAND_TYPE_IMM1, "i1" },
3038 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3039 { OPERAND_TYPE_DISP8, "d8" },
3040 { OPERAND_TYPE_DISP16, "d16" },
3041 { OPERAND_TYPE_DISP32, "d32" },
3042 { OPERAND_TYPE_DISP32S, "d32s" },
3043 { OPERAND_TYPE_DISP64, "d64" },
3044 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3045 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3046 { OPERAND_TYPE_CONTROL, "control reg" },
3047 { OPERAND_TYPE_TEST, "test reg" },
3048 { OPERAND_TYPE_DEBUG, "debug reg" },
3049 { OPERAND_TYPE_FLOATREG, "FReg" },
3050 { OPERAND_TYPE_FLOATACC, "FAcc" },
3051 { OPERAND_TYPE_SREG2, "SReg2" },
3052 { OPERAND_TYPE_SREG3, "SReg3" },
3053 { OPERAND_TYPE_ACC, "Acc" },
3054 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3055 { OPERAND_TYPE_REGMMX, "rMMX" },
3056 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 3057 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 3058 { OPERAND_TYPE_REGZMM, "rZMM" },
3059 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 3060 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 3061};
3062
3063static void
40fb9820 3064pt (i386_operand_type t)
252b5132 3065{
40fb9820 3066 unsigned int j;
c6fb90c8 3067 i386_operand_type a;
252b5132 3068
40fb9820 3069 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 3070 {
3071 a = operand_type_and (t, type_names[j].mask);
0349dc08 3072 if (!operand_type_all_zero (&a))
c6fb90c8
L		 3073 fprintf (stdout, "%s, ", type_names[j].name);
3074 }
252b5132
RH		 3075 fflush (stdout);
3076}
3077
3078#endif /* DEBUG386 */
3079\f
252b5132 3080static bfd_reloc_code_real_type
3956db08 3081reloc (unsigned int size,
64e74474
AM		 3082 int pcrel,
3083 int sign,
3084 bfd_reloc_code_real_type other)
252b5132 3085{
47926f60 3086 if (other != NO_RELOC)
3956db08 3087 {
91d6fa6a 3088 reloc_howto_type *rel;
3956db08
JB		 3089
3090 if (size == 8)
3091 switch (other)
3092 {
64e74474
AM		 3093 case BFD_RELOC_X86_64_GOT32:
3094 return BFD_RELOC_X86_64_GOT64;
3095 break;
553d1284
L		 3096 case BFD_RELOC_X86_64_GOTPLT64:
3097 return BFD_RELOC_X86_64_GOTPLT64;
3098 break;
64e74474
AM		 3099 case BFD_RELOC_X86_64_PLTOFF64:
3100 return BFD_RELOC_X86_64_PLTOFF64;
3101 break;
3102 case BFD_RELOC_X86_64_GOTPC32:
3103 other = BFD_RELOC_X86_64_GOTPC64;
3104 break;
3105 case BFD_RELOC_X86_64_GOTPCREL:
3106 other = BFD_RELOC_X86_64_GOTPCREL64;
3107 break;
3108 case BFD_RELOC_X86_64_TPOFF32:
3109 other = BFD_RELOC_X86_64_TPOFF64;
3110 break;
3111 case BFD_RELOC_X86_64_DTPOFF32:
3112 other = BFD_RELOC_X86_64_DTPOFF64;
3113 break;
3114 default:
3115 break;
3956db08 3116 }
e05278af 3117
8ce3d284 3118#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 3119 if (other == BFD_RELOC_SIZE32)
3120 {
3121 if (size == 8)
1ab668bf 3122 other = BFD_RELOC_SIZE64;
8fd4256d 3123 if (pcrel)
1ab668bf
AM		 3124 {
3125 as_bad (_("there are no pc-relative size relocations"));
3126 return NO_RELOC;
3127 }
8fd4256d 3128 }
8ce3d284 3129#endif
8fd4256d 3130
e05278af 3131 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 3132 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 3133 sign = -1;
3134
91d6fa6a
NC		 3135 rel = bfd_reloc_type_lookup (stdoutput, other);
3136 if (!rel)
3956db08 3137 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 3138 else if (size != bfd_get_reloc_size (rel))
3956db08 3139 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 3140 bfd_get_reloc_size (rel),
3956db08 3141 size);
91d6fa6a 3142 else if (pcrel && !rel->pc_relative)
3956db08 3143 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 3144 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 3145 && !sign)
91d6fa6a 3146 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 3147 && sign > 0))
3956db08
JB		 3148 as_bad (_("relocated field and relocation type differ in signedness"));
3149 else
3150 return other;
3151 return NO_RELOC;
3152 }
252b5132
RH		 3153
3154 if (pcrel)
3155 {
3e73aa7c 3156 if (!sign)
3956db08 3157 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 3158 switch (size)
3159 {
3160 case 1: return BFD_RELOC_8_PCREL;
3161 case 2: return BFD_RELOC_16_PCREL;
d258b828 3162 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 3163 case 8: return BFD_RELOC_64_PCREL;
252b5132 3164 }
3956db08 3165 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3166 }
3167 else
3168 {
3956db08 3169 if (sign > 0)
e5cb08ac 3170 switch (size)
3e73aa7c
JH		 3171 {
3172 case 4: return BFD_RELOC_X86_64_32S;
3173 }
3174 else
3175 switch (size)
3176 {
3177 case 1: return BFD_RELOC_8;
3178 case 2: return BFD_RELOC_16;
3179 case 4: return BFD_RELOC_32;
3180 case 8: return BFD_RELOC_64;
3181 }
3956db08
JB		 3182 as_bad (_("cannot do %s %u byte relocation"),
3183 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3184 }
3185
0cc9e1d3 3186 return NO_RELOC;
252b5132
RH		 3187}
3188
47926f60
KH		 3189/* Here we decide which fixups can be adjusted to make them relative to
3190 the beginning of the section instead of the symbol. Basically we need
3191 to make sure that the dynamic relocations are done correctly, so in
3192 some cases we force the original symbol to be used. */
3193
252b5132 3194int
e3bb37b5 3195tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3196{
6d249963 3197#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3198 if (!IS_ELF)
31312f95
AM		 3199 return 1;
3200
a161fe53
AM		 3201 /* Don't adjust pc-relative references to merge sections in 64-bit
3202 mode. */
3203 if (use_rela_relocations
3204 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3205 && fixP->fx_pcrel)
252b5132 3206 return 0;
31312f95 3207
8d01d9a9
AJ		 3208 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3209 and changed later by validate_fix. */
3210 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3211 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3212 return 0;
3213
8fd4256d
L		 3214 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3215 for size relocations. */
3216 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3217 || fixP->fx_r_type == BFD_RELOC_SIZE64
3218 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3219 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3220 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3221 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3222 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3223 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3224 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3225 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3226 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3227 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3228 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3229 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3230 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3231 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3232 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3233 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3234 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3235 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3236 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3237 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3238 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3239 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3240 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3241 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3242 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3243 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3244 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3245 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3246 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3247 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3248 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3249 return 0;
31312f95 3250#endif
252b5132
RH		 3251 return 1;
3252}
252b5132 3253
b4cac588 3254static int
e3bb37b5 3255intel_float_operand (const char *mnemonic)
252b5132 3256{
9306ca4a
JB		 3257 /* Note that the value returned is meaningful only for opcodes with (memory)
3258 operands, hence the code here is free to improperly handle opcodes that
3259 have no operands (for better performance and smaller code). */
3260
3261 if (mnemonic[0] != 'f')
3262 return 0; /* non-math */
3263
3264 switch (mnemonic[1])
3265 {
3266 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3267 the fs segment override prefix not currently handled because no
3268 call path can make opcodes without operands get here */
3269 case 'i':
3270 return 2 /* integer op */;
3271 case 'l':
3272 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3273 return 3; /* fldcw/fldenv */
3274 break;
3275 case 'n':
3276 if (mnemonic[2] != 'o' /* fnop */)
3277 return 3; /* non-waiting control op */
3278 break;
3279 case 'r':
3280 if (mnemonic[2] == 's')
3281 return 3; /* frstor/frstpm */
3282 break;
3283 case 's':
3284 if (mnemonic[2] == 'a')
3285 return 3; /* fsave */
3286 if (mnemonic[2] == 't')
3287 {
3288 switch (mnemonic[3])
3289 {
3290 case 'c': /* fstcw */
3291 case 'd': /* fstdw */
3292 case 'e': /* fstenv */
3293 case 's': /* fsts[gw] */
3294 return 3;
3295 }
3296 }
3297 break;
3298 case 'x':
3299 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3300 return 0; /* fxsave/fxrstor are not really math ops */
3301 break;
3302 }
252b5132 3303
9306ca4a 3304 return 1;
252b5132
RH		 3305}
3306
c0f3af97
L		 3307/* Build the VEX prefix. */
3308
3309static void
d3ce72d0 3310build_vex_prefix (const insn_template *t)
c0f3af97
L		 3311{
3312 unsigned int register_specifier;
3313 unsigned int implied_prefix;
3314 unsigned int vector_length;
3315
3316 /* Check register specifier. */
3317 if (i.vex.register_specifier)
43234a1e
L		 3318 {
3319 register_specifier =
3320 ~register_number (i.vex.register_specifier) & 0xf;
3321 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3322 }
c0f3af97
L		 3323 else
3324 register_specifier = 0xf;
3325
33eaf5de 3326 /* Use 2-byte VEX prefix by swapping destination and source
fa99fab2 3327 operand. */
86fa6981
L		 3328 if (i.vec_encoding != vex_encoding_vex3
3329 && i.dir_encoding == dir_encoding_default
fa99fab2 3330 && i.operands == i.reg_operands
7f399153 3331 && i.tm.opcode_modifier.vexopcode == VEX0F
86fa6981 3332 && i.tm.opcode_modifier.load
fa99fab2
L		 3333 && i.rex == REX_B)
3334 {
3335 unsigned int xchg = i.operands - 1;
3336 union i386_op temp_op;
3337 i386_operand_type temp_type;
3338
3339 temp_type = i.types[xchg];
3340 i.types[xchg] = i.types[0];
3341 i.types[0] = temp_type;
3342 temp_op = i.op[xchg];
3343 i.op[xchg] = i.op[0];
3344 i.op[0] = temp_op;
3345
9c2799c2 3346 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3347
3348 i.rex = REX_R;
3349 xchg = i.rm.regmem;
3350 i.rm.regmem = i.rm.reg;
3351 i.rm.reg = xchg;
3352
3353 /* Use the next insn. */
3354 i.tm = t[1];
3355 }
3356
539f890d
L		 3357 if (i.tm.opcode_modifier.vex == VEXScalar)
3358 vector_length = avxscalar;
10c17abd
JB		 3359 else if (i.tm.opcode_modifier.vex == VEX256)
3360 vector_length = 1;
539f890d 3361 else
10c17abd
JB		 3362 {
3363 unsigned int op;
3364
3365 vector_length = 0;
3366 for (op = 0; op < t->operands; ++op)
3367 if (t->operand_types[op].bitfield.xmmword
3368 && t->operand_types[op].bitfield.ymmword
3369 && i.types[op].bitfield.ymmword)
3370 {
3371 vector_length = 1;
3372 break;
3373 }
3374 }
c0f3af97
L		 3375
3376 switch ((i.tm.base_opcode >> 8) & 0xff)
3377 {
3378 case 0:
3379 implied_prefix = 0;
3380 break;
3381 case DATA_PREFIX_OPCODE:
3382 implied_prefix = 1;
3383 break;
3384 case REPE_PREFIX_OPCODE:
3385 implied_prefix = 2;
3386 break;
3387 case REPNE_PREFIX_OPCODE:
3388 implied_prefix = 3;
3389 break;
3390 default:
3391 abort ();
3392 }
3393
3394 /* Use 2-byte VEX prefix if possible. */
86fa6981
L		 3395 if (i.vec_encoding != vex_encoding_vex3
3396 && i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3397 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3398 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3399 {
3400 /* 2-byte VEX prefix. */
3401 unsigned int r;
3402
3403 i.vex.length = 2;
3404 i.vex.bytes[0] = 0xc5;
3405
3406 /* Check the REX.R bit. */
3407 r = (i.rex & REX_R) ? 0 : 1;
3408 i.vex.bytes[1] = (r << 7
3409 | register_specifier << 3
3410 | vector_length << 2
3411 | implied_prefix);
3412 }
3413 else
3414 {
3415 /* 3-byte VEX prefix. */
3416 unsigned int m, w;
3417
f88c9eb0 3418 i.vex.length = 3;
f88c9eb0 3419
7f399153 3420 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3421 {
7f399153
L		 3422 case VEX0F:
3423 m = 0x1;
80de6e00 3424 i.vex.bytes[0] = 0xc4;
7f399153
L		 3425 break;
3426 case VEX0F38:
3427 m = 0x2;
80de6e00 3428 i.vex.bytes[0] = 0xc4;
7f399153
L		 3429 break;
3430 case VEX0F3A:
3431 m = 0x3;
80de6e00 3432 i.vex.bytes[0] = 0xc4;
7f399153
L		 3433 break;
3434 case XOP08:
5dd85c99
SP		 3435 m = 0x8;
3436 i.vex.bytes[0] = 0x8f;
7f399153
L		 3437 break;
3438 case XOP09:
f88c9eb0
SP		 3439 m = 0x9;
3440 i.vex.bytes[0] = 0x8f;
7f399153
L		 3441 break;
3442 case XOP0A:
f88c9eb0
SP		 3443 m = 0xa;
3444 i.vex.bytes[0] = 0x8f;
7f399153
L		 3445 break;
3446 default:
3447 abort ();
f88c9eb0 3448 }
c0f3af97 3449
c0f3af97
L		 3450 /* The high 3 bits of the second VEX byte are 1's compliment
3451 of RXB bits from REX. */
3452 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3453
3454 /* Check the REX.W bit. */
3455 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3456 if (i.tm.opcode_modifier.vexw == VEXW1)
3457 w = 1;
c0f3af97
L		 3458
3459 i.vex.bytes[2] = (w << 7
3460 | register_specifier << 3
3461 | vector_length << 2
3462 | implied_prefix);
3463 }
3464}
3465
e771e7c9
JB		 3466static INLINE bfd_boolean
3467is_evex_encoding (const insn_template *t)
3468{
3469 return t->opcode_modifier.evex
3470 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3471 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3472}
3473
43234a1e
L		 3474/* Build the EVEX prefix. */
3475
3476static void
3477build_evex_prefix (void)
3478{
3479 unsigned int register_specifier;
3480 unsigned int implied_prefix;
3481 unsigned int m, w;
3482 rex_byte vrex_used = 0;
3483
3484 /* Check register specifier. */
3485 if (i.vex.register_specifier)
3486 {
3487 gas_assert ((i.vrex & REX_X) == 0);
3488
3489 register_specifier = i.vex.register_specifier->reg_num;
3490 if ((i.vex.register_specifier->reg_flags & RegRex))
3491 register_specifier += 8;
3492 /* The upper 16 registers are encoded in the fourth byte of the
3493 EVEX prefix. */
3494 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3495 i.vex.bytes[3] = 0x8;
3496 register_specifier = ~register_specifier & 0xf;
3497 }
3498 else
3499 {
3500 register_specifier = 0xf;
3501
3502 /* Encode upper 16 vector index register in the fourth byte of
3503 the EVEX prefix. */
3504 if (!(i.vrex & REX_X))
3505 i.vex.bytes[3] = 0x8;
3506 else
3507 vrex_used |= REX_X;
3508 }
3509
3510 switch ((i.tm.base_opcode >> 8) & 0xff)
3511 {
3512 case 0:
3513 implied_prefix = 0;
3514 break;
3515 case DATA_PREFIX_OPCODE:
3516 implied_prefix = 1;
3517 break;
3518 case REPE_PREFIX_OPCODE:
3519 implied_prefix = 2;
3520 break;
3521 case REPNE_PREFIX_OPCODE:
3522 implied_prefix = 3;
3523 break;
3524 default:
3525 abort ();
3526 }
3527
3528 /* 4 byte EVEX prefix. */
3529 i.vex.length = 4;
3530 i.vex.bytes[0] = 0x62;
3531
3532 /* mmmm bits. */
3533 switch (i.tm.opcode_modifier.vexopcode)
3534 {
3535 case VEX0F:
3536 m = 1;
3537 break;
3538 case VEX0F38:
3539 m = 2;
3540 break;
3541 case VEX0F3A:
3542 m = 3;
3543 break;
3544 default:
3545 abort ();
3546 break;
3547 }
3548
3549 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3550 bits from REX. */
3551 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3552
3553 /* The fifth bit of the second EVEX byte is 1's compliment of the
3554 REX_R bit in VREX. */
3555 if (!(i.vrex & REX_R))
3556 i.vex.bytes[1] |= 0x10;
3557 else
3558 vrex_used |= REX_R;
3559
3560 if ((i.reg_operands + i.imm_operands) == i.operands)
3561 {
3562 /* When all operands are registers, the REX_X bit in REX is not
3563 used. We reuse it to encode the upper 16 registers, which is
3564 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3565 as 1's compliment. */
3566 if ((i.vrex & REX_B))
3567 {
3568 vrex_used |= REX_B;
3569 i.vex.bytes[1] &= ~0x40;
3570 }
3571 }
3572
3573 /* EVEX instructions shouldn't need the REX prefix. */
3574 i.vrex &= ~vrex_used;
3575 gas_assert (i.vrex == 0);
3576
3577 /* Check the REX.W bit. */
3578 w = (i.rex & REX_W) ? 1 : 0;
3579 if (i.tm.opcode_modifier.vexw)
3580 {
3581 if (i.tm.opcode_modifier.vexw == VEXW1)
3582 w = 1;
3583 }
3584 /* If w is not set it means we are dealing with WIG instruction. */
3585 else if (!w)
3586 {
3587 if (evexwig == evexw1)
3588 w = 1;
3589 }
3590
3591 /* Encode the U bit. */
3592 implied_prefix |= 0x4;
3593
3594 /* The third byte of the EVEX prefix. */
3595 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3596
3597 /* The fourth byte of the EVEX prefix. */
3598 /* The zeroing-masking bit. */
3599 if (i.mask && i.mask->zeroing)
3600 i.vex.bytes[3] |= 0x80;
3601
3602 /* Don't always set the broadcast bit if there is no RC. */
3603 if (!i.rounding)
3604 {
3605 /* Encode the vector length. */
3606 unsigned int vec_length;
3607
e771e7c9
JB		 3608 if (!i.tm.opcode_modifier.evex
3609 || i.tm.opcode_modifier.evex == EVEXDYN)
3610 {
3611 unsigned int op;
3612
3613 vec_length = 0;
3614 for (op = 0; op < i.tm.operands; ++op)
3615 if (i.tm.operand_types[op].bitfield.xmmword
3616 + i.tm.operand_types[op].bitfield.ymmword
3617 + i.tm.operand_types[op].bitfield.zmmword > 1)
3618 {
3619 if (i.types[op].bitfield.zmmword)
3620 i.tm.opcode_modifier.evex = EVEX512;
3621 else if (i.types[op].bitfield.ymmword)
3622 i.tm.opcode_modifier.evex = EVEX256;
3623 else if (i.types[op].bitfield.xmmword)
3624 i.tm.opcode_modifier.evex = EVEX128;
3625 else
3626 continue;
3627 break;
3628 }
3629 }
3630
43234a1e
L		 3631 switch (i.tm.opcode_modifier.evex)
3632 {
3633 case EVEXLIG: /* LL' is ignored */
3634 vec_length = evexlig << 5;
3635 break;
3636 case EVEX128:
3637 vec_length = 0 << 5;
3638 break;
3639 case EVEX256:
3640 vec_length = 1 << 5;
3641 break;
3642 case EVEX512:
3643 vec_length = 2 << 5;
3644 break;
3645 default:
3646 abort ();
3647 break;
3648 }
3649 i.vex.bytes[3] |= vec_length;
3650 /* Encode the broadcast bit. */
3651 if (i.broadcast)
3652 i.vex.bytes[3] |= 0x10;
3653 }
3654 else
3655 {
3656 if (i.rounding->type != saeonly)
3657 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3658 else
d3d3c6db 3659 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3660 }
3661
3662 if (i.mask && i.mask->mask)
3663 i.vex.bytes[3] |= i.mask->mask->reg_num;
3664}
3665
65da13b5
L		 3666static void
3667process_immext (void)
3668{
3669 expressionS *exp;
3670
4c692bc7
JB		 3671 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3672 && i.operands > 0)
65da13b5 3673 {
4c692bc7
JB		 3674 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3675 with an opcode suffix which is coded in the same place as an
3676 8-bit immediate field would be.
3677 Here we check those operands and remove them afterwards. */
65da13b5
L		 3678 unsigned int x;
3679
3680 for (x = 0; x < i.operands; x++)
4c692bc7 3681 if (register_number (i.op[x].regs) != x)
65da13b5 3682 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3683 register_prefix, i.op[x].regs->reg_name, x + 1,
3684 i.tm.name);
3685
3686 i.operands = 0;
65da13b5
L		 3687 }
3688
9916071f
AP		 3689 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3690 {
3691 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3692 suffix which is coded in the same place as an 8-bit immediate
3693 field would be.
3694 Here we check those operands and remove them afterwards. */
3695 unsigned int x;
3696
3697 if (i.operands != 3)
3698 abort();
3699
3700 for (x = 0; x < 2; x++)
3701 if (register_number (i.op[x].regs) != x)
3702 goto bad_register_operand;
3703
3704 /* Check for third operand for mwaitx/monitorx insn. */
3705 if (register_number (i.op[x].regs)
3706 != (x + (i.tm.extension_opcode == 0xfb)))
3707 {
3708bad_register_operand:
3709 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3710 register_prefix, i.op[x].regs->reg_name, x+1,
3711 i.tm.name);
3712 }
3713
3714 i.operands = 0;
3715 }
3716
c0f3af97 3717 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3718 which is coded in the same place as an 8-bit immediate field
3719 would be. Here we fake an 8-bit immediate operand from the
3720 opcode suffix stored in tm.extension_opcode.
3721
c1e679ec 3722 AVX instructions also use this encoding, for some of
c0f3af97 3723 3 argument instructions. */
65da13b5 3724
43234a1e 3725 gas_assert (i.imm_operands <= 1
7ab9ffdd 3726 && (i.operands <= 2
43234a1e 3727 || ((i.tm.opcode_modifier.vex
e771e7c9
JB		 3728 || i.tm.opcode_modifier.vexopcode
3729 || is_evex_encoding (&i.tm))
7ab9ffdd 3730 && i.operands <= 4)));
65da13b5
L		 3731
3732 exp = &im_expressions[i.imm_operands++];
3733 i.op[i.operands].imms = exp;
3734 i.types[i.operands] = imm8;
3735 i.operands++;
3736 exp->X_op = O_constant;
3737 exp->X_add_number = i.tm.extension_opcode;
3738 i.tm.extension_opcode = None;
3739}
3740
42164a71
L		 3741
3742static int
3743check_hle (void)
3744{
3745 switch (i.tm.opcode_modifier.hleprefixok)
3746 {
3747 default:
3748 abort ();
82c2def5 3749 case HLEPrefixNone:
165de32a
L		 3750 as_bad (_("invalid instruction `%s' after `%s'"),
3751 i.tm.name, i.hle_prefix);
42164a71 3752 return 0;
82c2def5 3753 case HLEPrefixLock:
42164a71
L		 3754 if (i.prefix[LOCK_PREFIX])
3755 return 1;
165de32a 3756 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3757 return 0;
82c2def5 3758 case HLEPrefixAny:
42164a71 3759 return 1;
82c2def5 3760 case HLEPrefixRelease:
42164a71
L		 3761 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3762 {
3763 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3764 i.tm.name);
3765 return 0;
3766 }
3767 if (i.mem_operands == 0
3768 || !operand_type_check (i.types[i.operands - 1], anymem))
3769 {
3770 as_bad (_("memory destination needed for instruction `%s'"
3771 " after `xrelease'"), i.tm.name);
3772 return 0;
3773 }
3774 return 1;
3775 }
3776}
3777
b6f8c7c4
L		 3778/* Try the shortest encoding by shortening operand size. */
3779
3780static void
3781optimize_encoding (void)
3782{
3783 int j;
3784
3785 if (optimize_for_space
3786 && i.reg_operands == 1
3787 && i.imm_operands == 1
3788 && !i.types[1].bitfield.byte
3789 && i.op[0].imms->X_op == O_constant
3790 && fits_in_imm7 (i.op[0].imms->X_add_number)
3791 && ((i.tm.base_opcode == 0xa8
3792 && i.tm.extension_opcode == None)
3793 || (i.tm.base_opcode == 0xf6
3794 && i.tm.extension_opcode == 0x0)))
3795 {
3796 /* Optimize: -Os:
3797 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3798 */
3799 unsigned int base_regnum = i.op[1].regs->reg_num;
3800 if (flag_code == CODE_64BIT || base_regnum < 4)
3801 {
3802 i.types[1].bitfield.byte = 1;
3803 /* Ignore the suffix. */
3804 i.suffix = 0;
3805 if (base_regnum >= 4
3806 && !(i.op[1].regs->reg_flags & RegRex))
3807 {
3808 /* Handle SP, BP, SI and DI registers. */
3809 if (i.types[1].bitfield.word)
3810 j = 16;
3811 else if (i.types[1].bitfield.dword)
3812 j = 32;
3813 else
3814 j = 48;
3815 i.op[1].regs -= j;
3816 }
3817 }
3818 }
3819 else if (flag_code == CODE_64BIT
d3d50934
L		 3820 && ((i.types[1].bitfield.qword
3821 && i.reg_operands == 1
b6f8c7c4
L		 3822 && i.imm_operands == 1
3823 && i.op[0].imms->X_op == O_constant
3824 && ((i.tm.base_opcode == 0xb0
3825 && i.tm.extension_opcode == None
3826 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3827 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3828 && (((i.tm.base_opcode == 0x24
3829 || i.tm.base_opcode == 0xa8)
3830 && i.tm.extension_opcode == None)
3831 || (i.tm.base_opcode == 0x80
3832 && i.tm.extension_opcode == 0x4)
3833 || ((i.tm.base_opcode == 0xf6
3834 || i.tm.base_opcode == 0xc6)
3835 && i.tm.extension_opcode == 0x0)))))
d3d50934
L		 3836 || (i.types[0].bitfield.qword
3837 && ((i.reg_operands == 2
3838 && i.op[0].regs == i.op[1].regs
3839 && ((i.tm.base_opcode == 0x30
3840 || i.tm.base_opcode == 0x28)
3841 && i.tm.extension_opcode == None))
3842 || (i.reg_operands == 1
3843 && i.operands == 1
3844 && i.tm.base_opcode == 0x30
3845 && i.tm.extension_opcode == None)))))
b6f8c7c4
L		 3846 {
3847 /* Optimize: -O:
3848 andq $imm31, %r64 -> andl $imm31, %r32
3849 testq $imm31, %r64 -> testl $imm31, %r32
3850 xorq %r64, %r64 -> xorl %r32, %r32
3851 subq %r64, %r64 -> subl %r32, %r32
3852 movq $imm31, %r64 -> movl $imm31, %r32
3853 movq $imm32, %r64 -> movl $imm32, %r32
3854 */
3855 i.tm.opcode_modifier.norex64 = 1;
3856 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3857 {
3858 /* Handle
3859 movq $imm31, %r64 -> movl $imm31, %r32
3860 movq $imm32, %r64 -> movl $imm32, %r32
3861 */
3862 i.tm.operand_types[0].bitfield.imm32 = 1;
3863 i.tm.operand_types[0].bitfield.imm32s = 0;
3864 i.tm.operand_types[0].bitfield.imm64 = 0;
3865 i.types[0].bitfield.imm32 = 1;
3866 i.types[0].bitfield.imm32s = 0;
3867 i.types[0].bitfield.imm64 = 0;
3868 i.types[1].bitfield.dword = 1;
3869 i.types[1].bitfield.qword = 0;
3870 if (i.tm.base_opcode == 0xc6)
3871 {
3872 /* Handle
3873 movq $imm31, %r64 -> movl $imm31, %r32
3874 */
3875 i.tm.base_opcode = 0xb0;
3876 i.tm.extension_opcode = None;
3877 i.tm.opcode_modifier.shortform = 1;
3878 i.tm.opcode_modifier.modrm = 0;
3879 }
3880 }
3881 }
3882 else if (optimize > 1
3883 && i.reg_operands == 3
3884 && i.op[0].regs == i.op[1].regs
3885 && !i.types[2].bitfield.xmmword
3886 && (i.tm.opcode_modifier.vex
7a69eac3 3887 || ((!i.mask || i.mask->zeroing)
b6f8c7c4 3888 && !i.rounding
e771e7c9 3889 && is_evex_encoding (&i.tm)
80c34c38
L		 3890 && (i.vec_encoding != vex_encoding_evex
3891 || i.tm.cpu_flags.bitfield.cpuavx512vl
0089dace 3892 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
b6f8c7c4
L		 3893 && ((i.tm.base_opcode == 0x55
3894 || i.tm.base_opcode == 0x6655
3895 || i.tm.base_opcode == 0x66df
3896 || i.tm.base_opcode == 0x57
3897 || i.tm.base_opcode == 0x6657
8305403a
L		 3898 || i.tm.base_opcode == 0x66ef
3899 || i.tm.base_opcode == 0x66f8
3900 || i.tm.base_opcode == 0x66f9
3901 || i.tm.base_opcode == 0x66fa
3902 || i.tm.base_opcode == 0x66fb)
b6f8c7c4
L		 3903 && i.tm.extension_opcode == None))
3904 {
3905 /* Optimize: -O2:
8305403a
L		 3906 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3907 vpsubq and vpsubw:
b6f8c7c4
L		 3908 EVEX VOP %zmmM, %zmmM, %zmmN
3909 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3910 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3911 EVEX VOP %ymmM, %ymmM, %ymmN
3912 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3913 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3914 VEX VOP %ymmM, %ymmM, %ymmN
3915 -> VEX VOP %xmmM, %xmmM, %xmmN
3916 VOP, one of vpandn and vpxor:
3917 VEX VOP %ymmM, %ymmM, %ymmN
3918 -> VEX VOP %xmmM, %xmmM, %xmmN
3919 VOP, one of vpandnd and vpandnq:
3920 EVEX VOP %zmmM, %zmmM, %zmmN
3921 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3922 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3923 EVEX VOP %ymmM, %ymmM, %ymmN
3924 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3925 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3926 VOP, one of vpxord and vpxorq:
3927 EVEX VOP %zmmM, %zmmM, %zmmN
3928 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3929 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3930 EVEX VOP %ymmM, %ymmM, %ymmN
3931 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3932 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3933 */
e771e7c9 3934 if (is_evex_encoding (&i.tm))
b6f8c7c4 3935 {
0089dace 3936 if (i.vec_encoding == vex_encoding_evex)
b6f8c7c4
L		 3937 i.tm.opcode_modifier.evex = EVEX128;
3938 else
3939 {
3940 i.tm.opcode_modifier.vex = VEX128;
3941 i.tm.opcode_modifier.vexw = VEXW0;
3942 i.tm.opcode_modifier.evex = 0;
3943 }
3944 }
3945 else
3946 i.tm.opcode_modifier.vex = VEX128;
3947
3948 if (i.tm.opcode_modifier.vex)
3949 for (j = 0; j < 3; j++)
3950 {
3951 i.types[j].bitfield.xmmword = 1;
3952 i.types[j].bitfield.ymmword = 0;
3953 }
3954 }
3955}
3956
252b5132
RH		 3957/* This is the guts of the machine-dependent assembler. LINE points to a
3958 machine dependent instruction. This function is supposed to emit
3959 the frags/bytes it assembles to. */
3960
3961void
65da13b5 3962md_assemble (char *line)
252b5132 3963{
40fb9820 3964 unsigned int j;
83b16ac6 3965 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3966 const insn_template *t;
252b5132 3967
47926f60 3968 /* Initialize globals. */
252b5132
RH		 3969 memset (&i, '\0', sizeof (i));
3970 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3971 i.reloc[j] = NO_RELOC;
252b5132
RH		 3972 memset (disp_expressions, '\0', sizeof (disp_expressions));
3973 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3974 save_stack_p = save_stack;
252b5132
RH		 3975
3976 /* First parse an instruction mnemonic & call i386_operand for the operands.
3977 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3978 start of a (possibly prefixed) mnemonic. */
252b5132 3979
29b0f896
AM		 3980 line = parse_insn (line, mnemonic);
3981 if (line == NULL)
3982 return;
83b16ac6 3983 mnem_suffix = i.suffix;
252b5132 3984
29b0f896 3985 line = parse_operands (line, mnemonic);
ee86248c 3986 this_operand = -1;
8325cc63
JB		 3987 xfree (i.memop1_string);
3988 i.memop1_string = NULL;
29b0f896
AM		 3989 if (line == NULL)
3990 return;
252b5132 3991
29b0f896
AM		 3992 /* Now we've parsed the mnemonic into a set of templates, and have the
3993 operands at hand. */
3994
3995 /* All intel opcodes have reversed operands except for "bound" and
3996 "enter". We also don't reverse intersegment "jmp" and "call"
3997 instructions with 2 immediate operands so that the immediate segment
050dfa73 3998 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3999 if (intel_syntax
4000 && i.operands > 1
29b0f896 4001 && (strcmp (mnemonic, "bound") != 0)
30123838 4002 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 4003 && !(operand_type_check (i.types[0], imm)
4004 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 4005 swap_operands ();
4006
ec56d5c0
JB		 4007 /* The order of the immediates should be reversed
4008 for 2 immediates extrq and insertq instructions */
4009 if (i.imm_operands == 2
4010 && (strcmp (mnemonic, "extrq") == 0
4011 || strcmp (mnemonic, "insertq") == 0))
4012 swap_2_operands (0, 1);
4013
29b0f896
AM		 4014 if (i.imm_operands)
4015 optimize_imm ();
4016
b300c311
L		 4017 /* Don't optimize displacement for movabs since it only takes 64bit
4018 displacement. */
4019 if (i.disp_operands
a501d77e 4020 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 4021 && (flag_code != CODE_64BIT
4022 || strcmp (mnemonic, "movabs") != 0))
4023 optimize_disp ();
29b0f896
AM		 4024
4025 /* Next, we find a template that matches the given insn,
4026 making sure the overlap of the given operands types is consistent
4027 with the template operand types. */
252b5132 4028
83b16ac6 4029 if (!(t = match_template (mnem_suffix)))
29b0f896 4030 return;
252b5132 4031
7bab8ab5 4032 if (sse_check != check_none
81f8a913 4033 && !i.tm.opcode_modifier.noavx
6e3e5c9e 4034 && !i.tm.cpu_flags.bitfield.cpuavx
daf50ae7
L		 4035 && (i.tm.cpu_flags.bitfield.cpusse
4036 || i.tm.cpu_flags.bitfield.cpusse2
4037 || i.tm.cpu_flags.bitfield.cpusse3
4038 || i.tm.cpu_flags.bitfield.cpussse3
4039 || i.tm.cpu_flags.bitfield.cpusse4_1
6e3e5c9e
JB		 4040 || i.tm.cpu_flags.bitfield.cpusse4_2
4041 || i.tm.cpu_flags.bitfield.cpupclmul
4042 || i.tm.cpu_flags.bitfield.cpuaes
4043 || i.tm.cpu_flags.bitfield.cpugfni))
daf50ae7 4044 {
7bab8ab5 4045 (sse_check == check_warning
daf50ae7
L		 4046 ? as_warn
4047 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4048 }
4049
321fd21e
L		 4050 /* Zap movzx and movsx suffix. The suffix has been set from
4051 "word ptr" or "byte ptr" on the source operand in Intel syntax
4052 or extracted from mnemonic in AT&T syntax. But we'll use
4053 the destination register to choose the suffix for encoding. */
4054 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 4055 {
321fd21e
L		 4056 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4057 there is no suffix, the default will be byte extension. */
4058 if (i.reg_operands != 2
4059 && !i.suffix
7ab9ffdd 4060 && intel_syntax)
321fd21e
L		 4061 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4062
4063 i.suffix = 0;
cd61ebfe 4064 }
24eab124 4065
40fb9820 4066 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 4067 if (!add_prefix (FWAIT_OPCODE))
4068 return;
252b5132 4069
d5de92cf
L		 4070 /* Check if REP prefix is OK. */
4071 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4072 {
4073 as_bad (_("invalid instruction `%s' after `%s'"),
4074 i.tm.name, i.rep_prefix);
4075 return;
4076 }
4077
c1ba0266
L		 4078 /* Check for lock without a lockable instruction. Destination operand
4079 must be memory unless it is xchg (0x86). */
c32fa91d
L		 4080 if (i.prefix[LOCK_PREFIX]
4081 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 4082 || i.mem_operands == 0
4083 || (i.tm.base_opcode != 0x86
4084 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 4085 {
4086 as_bad (_("expecting lockable instruction after `lock'"));
4087 return;
4088 }
4089
42164a71 4090 /* Check if HLE prefix is OK. */
165de32a 4091 if (i.hle_prefix && !check_hle ())
42164a71
L		 4092 return;
4093
7e8b059b
L		 4094 /* Check BND prefix. */
4095 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4096 as_bad (_("expecting valid branch instruction after `bnd'"));
4097
04ef582a 4098 /* Check NOTRACK prefix. */
9fef80d6
L		 4099 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4100 as_bad (_("expecting indirect branch instruction after `notrack'"));
04ef582a 4101
327e8c42
JB		 4102 if (i.tm.cpu_flags.bitfield.cpumpx)
4103 {
4104 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4105 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4106 else if (flag_code != CODE_16BIT
4107 ? i.prefix[ADDR_PREFIX]
4108 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4109 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4110 }
7e8b059b
L		 4111
4112 /* Insert BND prefix. */
4113 if (add_bnd_prefix
4114 && i.tm.opcode_modifier.bndprefixok
4115 && !i.prefix[BND_PREFIX])
4116 add_prefix (BND_PREFIX_OPCODE);
4117
29b0f896 4118 /* Check string instruction segment overrides. */
40fb9820 4119 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 4120 {
4121 if (!check_string ())
5dd0794d 4122 return;
fc0763e6 4123 i.disp_operands = 0;
29b0f896 4124 }
5dd0794d 4125
b6f8c7c4
L		 4126 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4127 optimize_encoding ();
4128
29b0f896
AM		 4129 if (!process_suffix ())
4130 return;
e413e4e9 4131
bc0844ae
L		 4132 /* Update operand types. */
4133 for (j = 0; j < i.operands; j++)
4134 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4135
29b0f896
AM		 4136 /* Make still unresolved immediate matches conform to size of immediate
4137 given in i.suffix. */
4138 if (!finalize_imm ())
4139 return;
252b5132 4140
40fb9820 4141 if (i.types[0].bitfield.imm1)
29b0f896 4142 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 4143
9afe6eb8
L		 4144 /* We only need to check those implicit registers for instructions
4145 with 3 operands or less. */
4146 if (i.operands <= 3)
4147 for (j = 0; j < i.operands; j++)
4148 if (i.types[j].bitfield.inoutportreg
4149 || i.types[j].bitfield.shiftcount
1b54b8d7 4150 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
9afe6eb8 4151 i.reg_operands--;
40fb9820 4152
c0f3af97
L		 4153 /* ImmExt should be processed after SSE2AVX. */
4154 if (!i.tm.opcode_modifier.sse2avx
4155 && i.tm.opcode_modifier.immext)
65da13b5 4156 process_immext ();
252b5132 4157
29b0f896
AM		 4158 /* For insns with operands there are more diddles to do to the opcode. */
4159 if (i.operands)
4160 {
4161 if (!process_operands ())
4162 return;
4163 }
40fb9820 4164 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 4165 {
4166 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4167 as_warn (_("translating to `%sp'"), i.tm.name);
4168 }
252b5132 4169
e771e7c9
JB		 4170 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4171 || is_evex_encoding (&i.tm))
9e5e5283
L		 4172 {
4173 if (flag_code == CODE_16BIT)
4174 {
4175 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4176 i.tm.name);
4177 return;
4178 }
c0f3af97 4179
9e5e5283
L		 4180 if (i.tm.opcode_modifier.vex)
4181 build_vex_prefix (t);
4182 else
4183 build_evex_prefix ();
4184 }
43234a1e 4185
5dd85c99
SP		 4186 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4187 instructions may define INT_OPCODE as well, so avoid this corner
4188 case for those instructions that use MODRM. */
4189 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 4190 && !i.tm.opcode_modifier.modrm
4191 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 4192 {
4193 i.tm.base_opcode = INT3_OPCODE;
4194 i.imm_operands = 0;
4195 }
252b5132 4196
40fb9820
L		 4197 if ((i.tm.opcode_modifier.jump
4198 || i.tm.opcode_modifier.jumpbyte
4199 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 4200 && i.op[0].disps->X_op == O_constant)
4201 {
4202 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4203 the absolute address given by the constant. Since ix86 jumps and
4204 calls are pc relative, we need to generate a reloc. */
4205 i.op[0].disps->X_add_symbol = &abs_symbol;
4206 i.op[0].disps->X_op = O_symbol;
4207 }
252b5132 4208
40fb9820 4209 if (i.tm.opcode_modifier.rex64)
161a04f6 4210 i.rex |= REX_W;
252b5132 4211
29b0f896
AM		 4212 /* For 8 bit registers we need an empty rex prefix. Also if the
4213 instruction already has a prefix, we need to convert old
4214 registers to new ones. */
773f551c 4215
dc821c5f 4216 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
29b0f896 4217 && (i.op[0].regs->reg_flags & RegRex64) != 0)
dc821c5f 4218 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
29b0f896 4219 && (i.op[1].regs->reg_flags & RegRex64) != 0)
dc821c5f
JB		 4220 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4221 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
29b0f896
AM		 4222 && i.rex != 0))
4223 {
4224 int x;
726c5dcd 4225
29b0f896
AM		 4226 i.rex |= REX_OPCODE;
4227 for (x = 0; x < 2; x++)
4228 {
4229 /* Look for 8 bit operand that uses old registers. */
dc821c5f 4230 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
29b0f896 4231 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 4232 {
29b0f896
AM		 4233 /* In case it is "hi" register, give up. */
4234 if (i.op[x].regs->reg_num > 3)
a540244d 4235 as_bad (_("can't encode register '%s%s' in an "
4eed87de 4236 "instruction requiring REX prefix."),
a540244d 4237 register_prefix, i.op[x].regs->reg_name);
773f551c 4238
29b0f896
AM		 4239 /* Otherwise it is equivalent to the extended register.
4240 Since the encoding doesn't change this is merely
4241 cosmetic cleanup for debug output. */
4242
4243 i.op[x].regs = i.op[x].regs + 8;
773f551c 4244 }
29b0f896
AM		 4245 }
4246 }
773f551c 4247
6b6b6807
L		 4248 if (i.rex == 0 && i.rex_encoding)
4249 {
4250 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4251 that uses legacy register. If it is "hi" register, don't add
4252 the REX_OPCODE byte. */
4253 int x;
4254 for (x = 0; x < 2; x++)
4255 if (i.types[x].bitfield.reg
4256 && i.types[x].bitfield.byte
4257 && (i.op[x].regs->reg_flags & RegRex64) == 0
4258 && i.op[x].regs->reg_num > 3)
4259 {
4260 i.rex_encoding = FALSE;
4261 break;
4262 }
4263
4264 if (i.rex_encoding)
4265 i.rex = REX_OPCODE;
4266 }
4267
7ab9ffdd 4268 if (i.rex != 0)
29b0f896
AM		 4269 add_prefix (REX_OPCODE | i.rex);
4270
4271 /* We are ready to output the insn. */
4272 output_insn ();
4273}
4274
4275static char *
e3bb37b5 4276parse_insn (char *line, char *mnemonic)
29b0f896
AM		 4277{
4278 char *l = line;
4279 char *token_start = l;
4280 char *mnem_p;
5c6af06e 4281 int supported;
d3ce72d0 4282 const insn_template *t;
b6169b20 4283 char *dot_p = NULL;
29b0f896 4284
29b0f896
AM		 4285 while (1)
4286 {
4287 mnem_p = mnemonic;
4288 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4289 {
b6169b20
L		 4290 if (*mnem_p == '.')
4291 dot_p = mnem_p;
29b0f896
AM		 4292 mnem_p++;
4293 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 4294 {
29b0f896
AM		 4295 as_bad (_("no such instruction: `%s'"), token_start);
4296 return NULL;
4297 }
4298 l++;
4299 }
4300 if (!is_space_char (*l)
4301 && *l != END_OF_INSN
e44823cf
JB		 4302 && (intel_syntax
4303 || (*l != PREFIX_SEPARATOR
4304 && *l != ',')))
29b0f896
AM		 4305 {
4306 as_bad (_("invalid character %s in mnemonic"),
4307 output_invalid (*l));
4308 return NULL;
4309 }
4310 if (token_start == l)
4311 {
e44823cf 4312 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 4313 as_bad (_("expecting prefix; got nothing"));
4314 else
4315 as_bad (_("expecting mnemonic; got nothing"));
4316 return NULL;
4317 }
45288df1 4318
29b0f896 4319 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 4320 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 4321
29b0f896
AM		 4322 if (*l != END_OF_INSN
4323 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4324 && current_templates
40fb9820 4325 && current_templates->start->opcode_modifier.isprefix)
29b0f896 4326 {
c6fb90c8 4327 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 4328 {
4329 as_bad ((flag_code != CODE_64BIT
4330 ? _("`%s' is only supported in 64-bit mode")
4331 : _("`%s' is not supported in 64-bit mode")),
4332 current_templates->start->name);
4333 return NULL;
4334 }
29b0f896
AM		 4335 /* If we are in 16-bit mode, do not allow addr16 or data16.
4336 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 4337 if ((current_templates->start->opcode_modifier.size16
4338 || current_templates->start->opcode_modifier.size32)
29b0f896 4339 && flag_code != CODE_64BIT
40fb9820 4340 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 4341 ^ (flag_code == CODE_16BIT)))
4342 {
4343 as_bad (_("redundant %s prefix"),
4344 current_templates->start->name);
4345 return NULL;
45288df1 4346 }
86fa6981 4347 if (current_templates->start->opcode_length == 0)
29b0f896 4348 {
86fa6981
L		 4349 /* Handle pseudo prefixes. */
4350 switch (current_templates->start->base_opcode)
4351 {
4352 case 0x0:
4353 /* {disp8} */
4354 i.disp_encoding = disp_encoding_8bit;
4355 break;
4356 case 0x1:
4357 /* {disp32} */
4358 i.disp_encoding = disp_encoding_32bit;
4359 break;
4360 case 0x2:
4361 /* {load} */
4362 i.dir_encoding = dir_encoding_load;
4363 break;
4364 case 0x3:
4365 /* {store} */
4366 i.dir_encoding = dir_encoding_store;
4367 break;
4368 case 0x4:
4369 /* {vex2} */
4370 i.vec_encoding = vex_encoding_vex2;
4371 break;
4372 case 0x5:
4373 /* {vex3} */
4374 i.vec_encoding = vex_encoding_vex3;
4375 break;
4376 case 0x6:
4377 /* {evex} */
4378 i.vec_encoding = vex_encoding_evex;
4379 break;
6b6b6807
L		 4380 case 0x7:
4381 /* {rex} */
4382 i.rex_encoding = TRUE;
4383 break;
b6f8c7c4
L		 4384 case 0x8:
4385 /* {nooptimize} */
4386 i.no_optimize = TRUE;
4387 break;
86fa6981
L		 4388 default:
4389 abort ();
4390 }
4391 }
4392 else
4393 {
4394 /* Add prefix, checking for repeated prefixes. */
4e9ac44a 4395 switch (add_prefix (current_templates->start->base_opcode))
86fa6981 4396 {
4e9ac44a
L		 4397 case PREFIX_EXIST:
4398 return NULL;
4399 case PREFIX_DS:
d777820b 4400 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4e9ac44a
L		 4401 i.notrack_prefix = current_templates->start->name;
4402 break;
4403 case PREFIX_REP:
4404 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4405 i.hle_prefix = current_templates->start->name;
4406 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4407 i.bnd_prefix = current_templates->start->name;
4408 else
4409 i.rep_prefix = current_templates->start->name;
4410 break;
4411 default:
4412 break;
86fa6981 4413 }
29b0f896
AM		 4414 }
4415 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4416 token_start = ++l;
4417 }
4418 else
4419 break;
4420 }
45288df1 4421
30a55f88 4422 if (!current_templates)
b6169b20 4423 {
f8a5c266
L		 4424 /* Check if we should swap operand or force 32bit displacement in
4425 encoding. */
30a55f88 4426 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
86fa6981 4427 i.dir_encoding = dir_encoding_store;
8d63c93e 4428 else if (mnem_p - 3 == dot_p
a501d77e
L		 4429 && dot_p[1] == 'd'
4430 && dot_p[2] == '8')
4431 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4432 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4433 && dot_p[1] == 'd'
4434 && dot_p[2] == '3'
4435 && dot_p[3] == '2')
a501d77e 4436 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4437 else
4438 goto check_suffix;
4439 mnem_p = dot_p;
4440 *dot_p = '\0';
d3ce72d0 4441 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4442 }
4443
29b0f896
AM		 4444 if (!current_templates)
4445 {
b6169b20 4446check_suffix:
29b0f896
AM		 4447 /* See if we can get a match by trimming off a suffix. */
4448 switch (mnem_p[-1])
4449 {
4450 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 4451 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4452 i.suffix = SHORT_MNEM_SUFFIX;
4453 else
1a0670f3 4454 /* Fall through. */
29b0f896
AM		 4455 case BYTE_MNEM_SUFFIX:
4456 case QWORD_MNEM_SUFFIX:
4457 i.suffix = mnem_p[-1];
4458 mnem_p[-1] = '\0';
d3ce72d0
NC		 4459 current_templates = (const templates *) hash_find (op_hash,
4460 mnemonic);
29b0f896
AM		 4461 break;
4462 case SHORT_MNEM_SUFFIX:
4463 case LONG_MNEM_SUFFIX:
4464 if (!intel_syntax)
4465 {
4466 i.suffix = mnem_p[-1];
4467 mnem_p[-1] = '\0';
d3ce72d0
NC		 4468 current_templates = (const templates *) hash_find (op_hash,
4469 mnemonic);
29b0f896
AM		 4470 }
4471 break;
252b5132 4472
29b0f896
AM		 4473 /* Intel Syntax. */
4474 case 'd':
4475 if (intel_syntax)
4476 {
9306ca4a 4477 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 4478 i.suffix = SHORT_MNEM_SUFFIX;
4479 else
4480 i.suffix = LONG_MNEM_SUFFIX;
4481 mnem_p[-1] = '\0';
d3ce72d0
NC		 4482 current_templates = (const templates *) hash_find (op_hash,
4483 mnemonic);
29b0f896
AM		 4484 }
4485 break;
4486 }
4487 if (!current_templates)
4488 {
4489 as_bad (_("no such instruction: `%s'"), token_start);
4490 return NULL;
4491 }
4492 }
252b5132 4493
40fb9820
L		 4494 if (current_templates->start->opcode_modifier.jump
4495 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4496 {
4497 /* Check for a branch hint. We allow ",pt" and ",pn" for
4498 predict taken and predict not taken respectively.
4499 I'm not sure that branch hints actually do anything on loop
4500 and jcxz insns (JumpByte) for current Pentium4 chips. They
4501 may work in the future and it doesn't hurt to accept them
4502 now. */
4503 if (l[0] == ',' && l[1] == 'p')
4504 {
4505 if (l[2] == 't')
4506 {
4507 if (!add_prefix (DS_PREFIX_OPCODE))
4508 return NULL;
4509 l += 3;
4510 }
4511 else if (l[2] == 'n')
4512 {
4513 if (!add_prefix (CS_PREFIX_OPCODE))
4514 return NULL;
4515 l += 3;
4516 }
4517 }
4518 }
4519 /* Any other comma loses. */
4520 if (*l == ',')
4521 {
4522 as_bad (_("invalid character %s in mnemonic"),
4523 output_invalid (*l));
4524 return NULL;
4525 }
252b5132 4526
29b0f896 4527 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4528 supported = 0;
4529 for (t = current_templates->start; t < current_templates->end; ++t)
4530 {
c0f3af97
L		 4531 supported |= cpu_flags_match (t);
4532 if (supported == CPU_FLAGS_PERFECT_MATCH)
548d0ee6
JB		 4533 {
4534 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4535 as_warn (_("use .code16 to ensure correct addressing mode"));
3629bb00 4536
548d0ee6
JB		 4537 return l;
4538 }
29b0f896 4539 }
3629bb00 4540
548d0ee6
JB		 4541 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4542 as_bad (flag_code == CODE_64BIT
4543 ? _("`%s' is not supported in 64-bit mode")
4544 : _("`%s' is only supported in 64-bit mode"),
4545 current_templates->start->name);
4546 else
4547 as_bad (_("`%s' is not supported on `%s%s'"),
4548 current_templates->start->name,
4549 cpu_arch_name ? cpu_arch_name : default_arch,
4550 cpu_sub_arch_name ? cpu_sub_arch_name : "");
252b5132 4551
548d0ee6 4552 return NULL;
29b0f896 4553}
252b5132 4554
29b0f896 4555static char *
e3bb37b5 4556parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4557{
4558 char *token_start;
3138f287 4559
29b0f896
AM		 4560 /* 1 if operand is pending after ','. */
4561 unsigned int expecting_operand = 0;
252b5132 4562
29b0f896
AM		 4563 /* Non-zero if operand parens not balanced. */
4564 unsigned int paren_not_balanced;
4565
4566 while (*l != END_OF_INSN)
4567 {
4568 /* Skip optional white space before operand. */
4569 if (is_space_char (*l))
4570 ++l;
d02603dc 4571 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4572 {
4573 as_bad (_("invalid character %s before operand %d"),
4574 output_invalid (*l),
4575 i.operands + 1);
4576 return NULL;
4577 }
d02603dc 4578 token_start = l; /* After white space. */
29b0f896
AM		 4579 paren_not_balanced = 0;
4580 while (paren_not_balanced || *l != ',')
4581 {
4582 if (*l == END_OF_INSN)
4583 {
4584 if (paren_not_balanced)
4585 {
4586 if (!intel_syntax)
4587 as_bad (_("unbalanced parenthesis in operand %d."),
4588 i.operands + 1);
4589 else
4590 as_bad (_("unbalanced brackets in operand %d."),
4591 i.operands + 1);
4592 return NULL;
4593 }
4594 else
4595 break; /* we are done */
4596 }
d02603dc 4597 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4598 {
4599 as_bad (_("invalid character %s in operand %d"),
4600 output_invalid (*l),
4601 i.operands + 1);
4602 return NULL;
4603 }
4604 if (!intel_syntax)
4605 {
4606 if (*l == '(')
4607 ++paren_not_balanced;
4608 if (*l == ')')
4609 --paren_not_balanced;
4610 }
4611 else
4612 {
4613 if (*l == '[')
4614 ++paren_not_balanced;
4615 if (*l == ']')
4616 --paren_not_balanced;
4617 }
4618 l++;
4619 }
4620 if (l != token_start)
4621 { /* Yes, we've read in another operand. */
4622 unsigned int operand_ok;
4623 this_operand = i.operands++;
4624 if (i.operands > MAX_OPERANDS)
4625 {
4626 as_bad (_("spurious operands; (%d operands/instruction max)"),
4627 MAX_OPERANDS);
4628 return NULL;
4629 }
9d46ce34 4630 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4631 /* Now parse operand adding info to 'i' as we go along. */
4632 END_STRING_AND_SAVE (l);
4633
4634 if (intel_syntax)
4635 operand_ok =
4636 i386_intel_operand (token_start,
4637 intel_float_operand (mnemonic));
4638 else
a7619375 4639 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4640
4641 RESTORE_END_STRING (l);
4642 if (!operand_ok)
4643 return NULL;
4644 }
4645 else
4646 {
4647 if (expecting_operand)
4648 {
4649 expecting_operand_after_comma:
4650 as_bad (_("expecting operand after ','; got nothing"));
4651 return NULL;
4652 }
4653 if (*l == ',')
4654 {
4655 as_bad (_("expecting operand before ','; got nothing"));
4656 return NULL;
4657 }
4658 }
7f3f1ea2 4659
29b0f896
AM		 4660 /* Now *l must be either ',' or END_OF_INSN. */
4661 if (*l == ',')
4662 {
4663 if (*++l == END_OF_INSN)
4664 {
4665 /* Just skip it, if it's \n complain. */
4666 goto expecting_operand_after_comma;
4667 }
4668 expecting_operand = 1;
4669 }
4670 }
4671 return l;
4672}
7f3f1ea2 4673
050dfa73 4674static void
4d456e3d 4675swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4676{
4677 union i386_op temp_op;
40fb9820 4678 i386_operand_type temp_type;
050dfa73 4679 enum bfd_reloc_code_real temp_reloc;
4eed87de 4680
050dfa73
MM		 4681 temp_type = i.types[xchg2];
4682 i.types[xchg2] = i.types[xchg1];
4683 i.types[xchg1] = temp_type;
4684 temp_op = i.op[xchg2];
4685 i.op[xchg2] = i.op[xchg1];
4686 i.op[xchg1] = temp_op;
4687 temp_reloc = i.reloc[xchg2];
4688 i.reloc[xchg2] = i.reloc[xchg1];
4689 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4690
4691 if (i.mask)
4692 {
4693 if (i.mask->operand == xchg1)
4694 i.mask->operand = xchg2;
4695 else if (i.mask->operand == xchg2)
4696 i.mask->operand = xchg1;
4697 }
4698 if (i.broadcast)
4699 {
4700 if (i.broadcast->operand == xchg1)
4701 i.broadcast->operand = xchg2;
4702 else if (i.broadcast->operand == xchg2)
4703 i.broadcast->operand = xchg1;
4704 }
4705 if (i.rounding)
4706 {
4707 if (i.rounding->operand == xchg1)
4708 i.rounding->operand = xchg2;
4709 else if (i.rounding->operand == xchg2)
4710 i.rounding->operand = xchg1;
4711 }
050dfa73
MM		 4712}
4713
29b0f896 4714static void
e3bb37b5 4715swap_operands (void)
29b0f896 4716{
b7c61d9a 4717 switch (i.operands)
050dfa73 4718 {
c0f3af97 4719 case 5:
b7c61d9a 4720 case 4:
4d456e3d 4721 swap_2_operands (1, i.operands - 2);
1a0670f3 4722 /* Fall through. */
b7c61d9a
L		 4723 case 3:
4724 case 2:
4d456e3d 4725 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4726 break;
4727 default:
4728 abort ();
29b0f896 4729 }
29b0f896
AM		 4730
4731 if (i.mem_operands == 2)
4732 {
4733 const seg_entry *temp_seg;
4734 temp_seg = i.seg[0];
4735 i.seg[0] = i.seg[1];
4736 i.seg[1] = temp_seg;
4737 }
4738}
252b5132 4739
29b0f896
AM		 4740/* Try to ensure constant immediates are represented in the smallest
4741 opcode possible. */
4742static void
e3bb37b5 4743optimize_imm (void)
29b0f896
AM		 4744{
4745 char guess_suffix = 0;
4746 int op;
252b5132 4747
29b0f896
AM		 4748 if (i.suffix)
4749 guess_suffix = i.suffix;
4750 else if (i.reg_operands)
4751 {
4752 /* Figure out a suffix from the last register operand specified.
4753 We can't do this properly yet, ie. excluding InOutPortReg,
4754 but the following works for instructions with immediates.
4755 In any case, we can't set i.suffix yet. */
4756 for (op = i.operands; --op >= 0;)
dc821c5f 4757 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
7ab9ffdd 4758 {
40fb9820
L		 4759 guess_suffix = BYTE_MNEM_SUFFIX;
4760 break;
4761 }
dc821c5f 4762 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
252b5132 4763 {
40fb9820
L		 4764 guess_suffix = WORD_MNEM_SUFFIX;
4765 break;
4766 }
dc821c5f 4767 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
40fb9820
L		 4768 {
4769 guess_suffix = LONG_MNEM_SUFFIX;
4770 break;
4771 }
dc821c5f 4772 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
40fb9820
L		 4773 {
4774 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4775 break;
252b5132 4776 }
29b0f896
AM		 4777 }
4778 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4779 guess_suffix = WORD_MNEM_SUFFIX;
4780
4781 for (op = i.operands; --op >= 0;)
40fb9820 4782 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4783 {
4784 switch (i.op[op].imms->X_op)
252b5132 4785 {
29b0f896
AM		 4786 case O_constant:
4787 /* If a suffix is given, this operand may be shortened. */
4788 switch (guess_suffix)
252b5132 4789 {
29b0f896 4790 case LONG_MNEM_SUFFIX:
40fb9820
L		 4791 i.types[op].bitfield.imm32 = 1;
4792 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4793 break;
4794 case WORD_MNEM_SUFFIX:
40fb9820
L		 4795 i.types[op].bitfield.imm16 = 1;
4796 i.types[op].bitfield.imm32 = 1;
4797 i.types[op].bitfield.imm32s = 1;
4798 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4799 break;
4800 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4801 i.types[op].bitfield.imm8 = 1;
4802 i.types[op].bitfield.imm8s = 1;
4803 i.types[op].bitfield.imm16 = 1;
4804 i.types[op].bitfield.imm32 = 1;
4805 i.types[op].bitfield.imm32s = 1;
4806 i.types[op].bitfield.imm64 = 1;
29b0f896 4807 break;
252b5132 4808 }
252b5132 4809
29b0f896
AM		 4810 /* If this operand is at most 16 bits, convert it
4811 to a signed 16 bit number before trying to see
4812 whether it will fit in an even smaller size.
4813 This allows a 16-bit operand such as $0xffe0 to
4814 be recognised as within Imm8S range. */
40fb9820 4815 if ((i.types[op].bitfield.imm16)
29b0f896 4816 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4817 {
29b0f896
AM		 4818 i.op[op].imms->X_add_number =
4819 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4820 }
a28def75
L		 4821#ifdef BFD64
4822 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4823 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4824 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4825 == 0))
4826 {
4827 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4828 ^ ((offsetT) 1 << 31))
4829 - ((offsetT) 1 << 31));
4830 }
a28def75 4831#endif
40fb9820 4832 i.types[op]
c6fb90c8
L		 4833 = operand_type_or (i.types[op],
4834 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4835
29b0f896
AM		 4836 /* We must avoid matching of Imm32 templates when 64bit
4837 only immediate is available. */
4838 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4839 i.types[op].bitfield.imm32 = 0;
29b0f896 4840 break;
252b5132 4841
29b0f896
AM		 4842 case O_absent:
4843 case O_register:
4844 abort ();
4845
4846 /* Symbols and expressions. */
4847 default:
9cd96992
JB		 4848 /* Convert symbolic operand to proper sizes for matching, but don't
4849 prevent matching a set of insns that only supports sizes other
4850 than those matching the insn suffix. */
4851 {
40fb9820 4852 i386_operand_type mask, allowed;
d3ce72d0 4853 const insn_template *t;
9cd96992 4854
0dfbf9d7
L		 4855 operand_type_set (&mask, 0);
4856 operand_type_set (&allowed, 0);
40fb9820 4857
4eed87de
AM		 4858 for (t = current_templates->start;
4859 t < current_templates->end;
4860 ++t)
c6fb90c8
L		 4861 allowed = operand_type_or (allowed,
4862 t->operand_types[op]);
9cd96992
JB		 4863 switch (guess_suffix)
4864 {
4865 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4866 mask.bitfield.imm64 = 1;
4867 mask.bitfield.imm32s = 1;
9cd96992
JB		 4868 break;
4869 case LONG_MNEM_SUFFIX:
40fb9820 4870 mask.bitfield.imm32 = 1;
9cd96992
JB		 4871 break;
4872 case WORD_MNEM_SUFFIX:
40fb9820 4873 mask.bitfield.imm16 = 1;
9cd96992
JB		 4874 break;
4875 case BYTE_MNEM_SUFFIX:
40fb9820 4876 mask.bitfield.imm8 = 1;
9cd96992
JB		 4877 break;
4878 default:
9cd96992
JB		 4879 break;
4880 }
c6fb90c8 4881 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4882 if (!operand_type_all_zero (&allowed))
c6fb90c8 4883 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4884 }
29b0f896 4885 break;
252b5132 4886 }
29b0f896
AM		 4887 }
4888}
47926f60 4889
29b0f896
AM		 4890/* Try to use the smallest displacement type too. */
4891static void
e3bb37b5 4892optimize_disp (void)
29b0f896
AM		 4893{
4894 int op;
3e73aa7c 4895
29b0f896 4896 for (op = i.operands; --op >= 0;)
40fb9820 4897 if (operand_type_check (i.types[op], disp))
252b5132 4898 {
b300c311 4899 if (i.op[op].disps->X_op == O_constant)
252b5132 4900 {
91d6fa6a 4901 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4902
40fb9820 4903 if (i.types[op].bitfield.disp16
91d6fa6a 4904 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4905 {
4906 /* If this operand is at most 16 bits, convert
4907 to a signed 16 bit number and don't use 64bit
4908 displacement. */
91d6fa6a 4909 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4910 i.types[op].bitfield.disp64 = 0;
b300c311 4911 }
a28def75
L		 4912#ifdef BFD64
4913 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4914 if (i.types[op].bitfield.disp32
91d6fa6a 4915 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4916 {
4917 /* If this operand is at most 32 bits, convert
4918 to a signed 32 bit number and don't use 64bit
4919 displacement. */
91d6fa6a
NC		 4920 op_disp &= (((offsetT) 2 << 31) - 1);
4921 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4922 i.types[op].bitfield.disp64 = 0;
b300c311 4923 }
a28def75 4924#endif
91d6fa6a 4925 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4926 {
40fb9820
L		 4927 i.types[op].bitfield.disp8 = 0;
4928 i.types[op].bitfield.disp16 = 0;
4929 i.types[op].bitfield.disp32 = 0;
4930 i.types[op].bitfield.disp32s = 0;
4931 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4932 i.op[op].disps = 0;
4933 i.disp_operands--;
4934 }
4935 else if (flag_code == CODE_64BIT)
4936 {
91d6fa6a 4937 if (fits_in_signed_long (op_disp))
28a9d8f5 4938 {
40fb9820
L		 4939 i.types[op].bitfield.disp64 = 0;
4940 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4941 }
0e1147d9 4942 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4943 && fits_in_unsigned_long (op_disp))
40fb9820 4944 i.types[op].bitfield.disp32 = 1;
b300c311 4945 }
40fb9820
L		 4946 if ((i.types[op].bitfield.disp32
4947 || i.types[op].bitfield.disp32s
4948 || i.types[op].bitfield.disp16)
b5014f7a 4949 && fits_in_disp8 (op_disp))
40fb9820 4950 i.types[op].bitfield.disp8 = 1;
252b5132 4951 }
67a4f2b7
AO		 4952 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4953 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4954 {
4955 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4956 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4957 i.types[op].bitfield.disp8 = 0;
4958 i.types[op].bitfield.disp16 = 0;
4959 i.types[op].bitfield.disp32 = 0;
4960 i.types[op].bitfield.disp32s = 0;
4961 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4962 }
4963 else
b300c311 4964 /* We only support 64bit displacement on constants. */
40fb9820 4965 i.types[op].bitfield.disp64 = 0;
252b5132 4966 }
29b0f896
AM		 4967}
4968
6c30d220
L		 4969/* Check if operands are valid for the instruction. */
4970
4971static int
4972check_VecOperands (const insn_template *t)
4973{
43234a1e 4974 unsigned int op;
e2195274
JB		 4975 i386_cpu_flags cpu;
4976 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
4977
4978 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
4979 any one operand are implicity requiring AVX512VL support if the actual
4980 operand size is YMMword or XMMword. Since this function runs after
4981 template matching, there's no need to check for YMMword/XMMword in
4982 the template. */
4983 cpu = cpu_flags_and (t->cpu_flags, avx512);
4984 if (!cpu_flags_all_zero (&cpu)
4985 && !t->cpu_flags.bitfield.cpuavx512vl
4986 && !cpu_arch_flags.bitfield.cpuavx512vl)
4987 {
4988 for (op = 0; op < t->operands; ++op)
4989 {
4990 if (t->operand_types[op].bitfield.zmmword
4991 && (i.types[op].bitfield.ymmword
4992 || i.types[op].bitfield.xmmword))
4993 {
4994 i.error = unsupported;
4995 return 1;
4996 }
4997 }
4998 }
43234a1e 4999
6c30d220
L		 5000 /* Without VSIB byte, we can't have a vector register for index. */
5001 if (!t->opcode_modifier.vecsib
5002 && i.index_reg
1b54b8d7
JB		 5003 && (i.index_reg->reg_type.bitfield.xmmword
5004 || i.index_reg->reg_type.bitfield.ymmword
5005 || i.index_reg->reg_type.bitfield.zmmword))
6c30d220
L		 5006 {
5007 i.error = unsupported_vector_index_register;
5008 return 1;
5009 }
5010
ad8ecc81
MZ		 5011 /* Check if default mask is allowed. */
5012 if (t->opcode_modifier.nodefmask
5013 && (!i.mask || i.mask->mask->reg_num == 0))
5014 {
5015 i.error = no_default_mask;
5016 return 1;
5017 }
5018
7bab8ab5
JB		 5019 /* For VSIB byte, we need a vector register for index, and all vector
5020 registers must be distinct. */
5021 if (t->opcode_modifier.vecsib)
5022 {
5023 if (!i.index_reg
6c30d220 5024 || !((t->opcode_modifier.vecsib == VecSIB128
1b54b8d7 5025 && i.index_reg->reg_type.bitfield.xmmword)
6c30d220 5026 || (t->opcode_modifier.vecsib == VecSIB256
1b54b8d7 5027 && i.index_reg->reg_type.bitfield.ymmword)
43234a1e 5028 || (t->opcode_modifier.vecsib == VecSIB512
1b54b8d7 5029 && i.index_reg->reg_type.bitfield.zmmword)))
7bab8ab5
JB		 5030 {
5031 i.error = invalid_vsib_address;
5032 return 1;
5033 }
5034
43234a1e
L		 5035 gas_assert (i.reg_operands == 2 || i.mask);
5036 if (i.reg_operands == 2 && !i.mask)
5037 {
1b54b8d7
JB		 5038 gas_assert (i.types[0].bitfield.regsimd);
5039 gas_assert (i.types[0].bitfield.xmmword
5040 || i.types[0].bitfield.ymmword);
5041 gas_assert (i.types[2].bitfield.regsimd);
5042 gas_assert (i.types[2].bitfield.xmmword
5043 || i.types[2].bitfield.ymmword);
43234a1e
L		 5044 if (operand_check == check_none)
5045 return 0;
5046 if (register_number (i.op[0].regs)
5047 != register_number (i.index_reg)
5048 && register_number (i.op[2].regs)
5049 != register_number (i.index_reg)
5050 && register_number (i.op[0].regs)
5051 != register_number (i.op[2].regs))
5052 return 0;
5053 if (operand_check == check_error)
5054 {
5055 i.error = invalid_vector_register_set;
5056 return 1;
5057 }
5058 as_warn (_("mask, index, and destination registers should be distinct"));
5059 }
8444f82a
MZ		 5060 else if (i.reg_operands == 1 && i.mask)
5061 {
1b54b8d7
JB		 5062 if (i.types[1].bitfield.regsimd
5063 && (i.types[1].bitfield.xmmword
5064 || i.types[1].bitfield.ymmword
5065 || i.types[1].bitfield.zmmword)
8444f82a
MZ		 5066 && (register_number (i.op[1].regs)
5067 == register_number (i.index_reg)))
5068 {
5069 if (operand_check == check_error)
5070 {
5071 i.error = invalid_vector_register_set;
5072 return 1;
5073 }
5074 if (operand_check != check_none)
5075 as_warn (_("index and destination registers should be distinct"));
5076 }
5077 }
43234a1e 5078 }
7bab8ab5 5079
43234a1e
L		 5080 /* Check if broadcast is supported by the instruction and is applied
5081 to the memory operand. */
5082 if (i.broadcast)
5083 {
8e6e0792 5084 i386_operand_type type, overlap;
43234a1e
L		 5085
5086 /* Check if specified broadcast is supported in this instruction,
c39e5b26 5087 and it's applied to memory operand of DWORD or QWORD type. */
32546502 5088 op = i.broadcast->operand;
8e6e0792 5089 if (!t->opcode_modifier.broadcast
32546502 5090 || !i.types[op].bitfield.mem
c39e5b26
JB		 5091 || (!i.types[op].bitfield.unspecified
5092 && (t->operand_types[op].bitfield.dword
5093 ? !i.types[op].bitfield.dword
5094 : !i.types[op].bitfield.qword)))
43234a1e
L		 5095 {
5096 bad_broadcast:
5097 i.error = unsupported_broadcast;
5098 return 1;
5099 }
8e6e0792
JB		 5100
5101 operand_type_set (&type, 0);
c39e5b26 5102 switch ((t->operand_types[op].bitfield.dword ? 4 : 8) * i.broadcast->type)
8e6e0792
JB		 5103 {
5104 case 8:
5105 type.bitfield.qword = 1;
5106 break;
5107 case 16:
5108 type.bitfield.xmmword = 1;
5109 break;
5110 case 32:
5111 type.bitfield.ymmword = 1;
5112 break;
5113 case 64:
5114 type.bitfield.zmmword = 1;
5115 break;
5116 default:
5117 goto bad_broadcast;
5118 }
5119
5120 overlap = operand_type_and (type, t->operand_types[op]);
5121 if (operand_type_all_zero (&overlap))
5122 goto bad_broadcast;
5123
5124 if (t->opcode_modifier.checkregsize)
5125 {
5126 unsigned int j;
5127
e2195274 5128 type.bitfield.baseindex = 1;
8e6e0792
JB		 5129 for (j = 0; j < i.operands; ++j)
5130 {
5131 if (j != op
5132 && !operand_type_register_match(i.types[j],
5133 t->operand_types[j],
5134 type,
5135 t->operand_types[op]))
5136 goto bad_broadcast;
5137 }
5138 }
43234a1e
L		 5139 }
5140 /* If broadcast is supported in this instruction, we need to check if
5141 operand of one-element size isn't specified without broadcast. */
5142 else if (t->opcode_modifier.broadcast && i.mem_operands)
5143 {
5144 /* Find memory operand. */
5145 for (op = 0; op < i.operands; op++)
5146 if (operand_type_check (i.types[op], anymem))
5147 break;
5148 gas_assert (op < i.operands);
5149 /* Check size of the memory operand. */
c39e5b26
JB		 5150 if (t->operand_types[op].bitfield.dword
5151 ? i.types[op].bitfield.dword
5152 : i.types[op].bitfield.qword)
43234a1e
L		 5153 {
5154 i.error = broadcast_needed;
5155 return 1;
5156 }
5157 }
c39e5b26
JB		 5158 else
5159 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
43234a1e
L		 5160
5161 /* Check if requested masking is supported. */
5162 if (i.mask
5163 && (!t->opcode_modifier.masking
5164 || (i.mask->zeroing
5165 && t->opcode_modifier.masking == MERGING_MASKING)))
5166 {
5167 i.error = unsupported_masking;
5168 return 1;
5169 }
5170
5171 /* Check if masking is applied to dest operand. */
5172 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5173 {
5174 i.error = mask_not_on_destination;
5175 return 1;
5176 }
5177
43234a1e
L		 5178 /* Check RC/SAE. */
5179 if (i.rounding)
5180 {
5181 if ((i.rounding->type != saeonly
5182 && !t->opcode_modifier.staticrounding)
5183 || (i.rounding->type == saeonly
5184 && (t->opcode_modifier.staticrounding
5185 || !t->opcode_modifier.sae)))
5186 {
5187 i.error = unsupported_rc_sae;
5188 return 1;
5189 }
5190 /* If the instruction has several immediate operands and one of
5191 them is rounding, the rounding operand should be the last
5192 immediate operand. */
5193 if (i.imm_operands > 1
5194 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 5195 {
43234a1e 5196 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 5197 return 1;
5198 }
6c30d220
L		 5199 }
5200
43234a1e 5201 /* Check vector Disp8 operand. */
b5014f7a
JB		 5202 if (t->opcode_modifier.disp8memshift
5203 && i.disp_encoding != disp_encoding_32bit)
43234a1e
L		 5204 {
5205 if (i.broadcast)
c39e5b26 5206 i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
43234a1e
L		 5207 else
5208 i.memshift = t->opcode_modifier.disp8memshift;
5209
5210 for (op = 0; op < i.operands; op++)
5211 if (operand_type_check (i.types[op], disp)
5212 && i.op[op].disps->X_op == O_constant)
5213 {
b5014f7a 5214 if (fits_in_disp8 (i.op[op].disps->X_add_number))
43234a1e 5215 {
b5014f7a
JB		 5216 i.types[op].bitfield.disp8 = 1;
5217 return 0;
43234a1e 5218 }
b5014f7a 5219 i.types[op].bitfield.disp8 = 0;
43234a1e
L		 5220 }
5221 }
b5014f7a
JB		 5222
5223 i.memshift = 0;
43234a1e 5224
6c30d220
L		 5225 return 0;
5226}
5227
43f3e2ee 5228/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 5229 operand types. */
5230
5231static int
5232VEX_check_operands (const insn_template *t)
5233{
86fa6981 5234 if (i.vec_encoding == vex_encoding_evex)
43234a1e 5235 {
86fa6981 5236 /* This instruction must be encoded with EVEX prefix. */
e771e7c9 5237 if (!is_evex_encoding (t))
86fa6981
L		 5238 {
5239 i.error = unsupported;
5240 return 1;
5241 }
5242 return 0;
43234a1e
L		 5243 }
5244
a683cc34 5245 if (!t->opcode_modifier.vex)
86fa6981
L		 5246 {
5247 /* This instruction template doesn't have VEX prefix. */
5248 if (i.vec_encoding != vex_encoding_default)
5249 {
5250 i.error = unsupported;
5251 return 1;
5252 }
5253 return 0;
5254 }
a683cc34
SP		 5255
5256 /* Only check VEX_Imm4, which must be the first operand. */
5257 if (t->operand_types[0].bitfield.vec_imm4)
5258 {
5259 if (i.op[0].imms->X_op != O_constant
5260 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 5261 {
a65babc9 5262 i.error = bad_imm4;
891edac4
L		 5263 return 1;
5264 }
a683cc34
SP		 5265
5266 /* Turn off Imm8 so that update_imm won't complain. */
5267 i.types[0] = vec_imm4;
5268 }
5269
5270 return 0;
5271}
5272
d3ce72d0 5273static const insn_template *
83b16ac6 5274match_template (char mnem_suffix)
29b0f896
AM		 5275{
5276 /* Points to template once we've found it. */
d3ce72d0 5277 const insn_template *t;
40fb9820 5278 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 5279 i386_operand_type overlap4;
29b0f896 5280 unsigned int found_reverse_match;
83b16ac6 5281 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 5282 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 5283 int addr_prefix_disp;
a5c311ca 5284 unsigned int j;
3629bb00 5285 unsigned int found_cpu_match;
45664ddb 5286 unsigned int check_register;
5614d22c 5287 enum i386_error specific_error = 0;
29b0f896 5288
c0f3af97
L		 5289#if MAX_OPERANDS != 5
5290# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 5291#endif
5292
29b0f896 5293 found_reverse_match = 0;
539e75ad 5294 addr_prefix_disp = -1;
40fb9820
L		 5295
5296 memset (&suffix_check, 0, sizeof (suffix_check));
e2195274
JB		 5297 if (intel_syntax && i.broadcast)
5298 /* nothing */;
5299 else if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5300 suffix_check.no_bsuf = 1;
5301 else if (i.suffix == WORD_MNEM_SUFFIX)
5302 suffix_check.no_wsuf = 1;
5303 else if (i.suffix == SHORT_MNEM_SUFFIX)
5304 suffix_check.no_ssuf = 1;
5305 else if (i.suffix == LONG_MNEM_SUFFIX)
5306 suffix_check.no_lsuf = 1;
5307 else if (i.suffix == QWORD_MNEM_SUFFIX)
5308 suffix_check.no_qsuf = 1;
5309 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 5310 suffix_check.no_ldsuf = 1;
29b0f896 5311
83b16ac6
JB		 5312 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5313 if (intel_syntax)
5314 {
5315 switch (mnem_suffix)
5316 {
5317 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5318 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5319 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5320 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5321 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5322 }
5323 }
5324
01559ecc
L		 5325 /* Must have right number of operands. */
5326 i.error = number_of_operands_mismatch;
5327
45aa61fe 5328 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 5329 {
539e75ad
L		 5330 addr_prefix_disp = -1;
5331
29b0f896
AM		 5332 if (i.operands != t->operands)
5333 continue;
5334
50aecf8c 5335 /* Check processor support. */
a65babc9 5336 i.error = unsupported;
c0f3af97
L		 5337 found_cpu_match = (cpu_flags_match (t)
5338 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 5339 if (!found_cpu_match)
5340 continue;
5341
e1d4d893 5342 /* Check AT&T mnemonic. */
a65babc9 5343 i.error = unsupported_with_intel_mnemonic;
e1d4d893 5344 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 5345 continue;
5346
e92bae62 5347 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 5348 i.error = unsupported_syntax;
5c07affc 5349 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 5350 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5351 || (intel64 && t->opcode_modifier.amd64)
5352 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 5353 continue;
5354
20592a94 5355 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 5356 i.error = invalid_instruction_suffix;
567e4e96
L		 5357 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5358 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5359 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5360 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5361 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5362 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5363 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 5364 continue;
83b16ac6
JB		 5365 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5366 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5367 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5368 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5369 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5370 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5371 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5372 continue;
29b0f896 5373
5c07affc 5374 if (!operand_size_match (t))
7d5e4556 5375 continue;
539e75ad 5376
5c07affc
L		 5377 for (j = 0; j < MAX_OPERANDS; j++)
5378 operand_types[j] = t->operand_types[j];
5379
45aa61fe
AM		 5380 /* In general, don't allow 64-bit operands in 32-bit mode. */
5381 if (i.suffix == QWORD_MNEM_SUFFIX
5382 && flag_code != CODE_64BIT
5383 && (intel_syntax
40fb9820 5384 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 5385 && !intel_float_operand (t->name))
5386 : intel_float_operand (t->name) != 2)
40fb9820 5387 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5388 && !operand_types[0].bitfield.regsimd)
40fb9820 5389 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5390 && !operand_types[t->operands > 1].bitfield.regsimd))
45aa61fe
AM		 5391 && (t->base_opcode != 0x0fc7
5392 || t->extension_opcode != 1 /* cmpxchg8b */))
5393 continue;
5394
192dc9c6
JB		 5395 /* In general, don't allow 32-bit operands on pre-386. */
5396 else if (i.suffix == LONG_MNEM_SUFFIX
5397 && !cpu_arch_flags.bitfield.cpui386
5398 && (intel_syntax
5399 ? (!t->opcode_modifier.ignoresize
5400 && !intel_float_operand (t->name))
5401 : intel_float_operand (t->name) != 2)
5402 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5403 && !operand_types[0].bitfield.regsimd)
192dc9c6 5404 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5405 && !operand_types[t->operands > 1].bitfield.regsimd)))
192dc9c6
JB		 5406 continue;
5407
29b0f896 5408 /* Do not verify operands when there are none. */
50aecf8c 5409 else
29b0f896 5410 {
c6fb90c8 5411 if (!t->operands)
2dbab7d5
L		 5412 /* We've found a match; break out of loop. */
5413 break;
29b0f896 5414 }
252b5132 5415
539e75ad
L		 5416 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5417 into Disp32/Disp16/Disp32 operand. */
5418 if (i.prefix[ADDR_PREFIX] != 0)
5419 {
40fb9820 5420 /* There should be only one Disp operand. */
539e75ad
L		 5421 switch (flag_code)
5422 {
5423 case CODE_16BIT:
40fb9820
L		 5424 for (j = 0; j < MAX_OPERANDS; j++)
5425 {
5426 if (operand_types[j].bitfield.disp16)
5427 {
5428 addr_prefix_disp = j;
5429 operand_types[j].bitfield.disp32 = 1;
5430 operand_types[j].bitfield.disp16 = 0;
5431 break;
5432 }
5433 }
539e75ad
L		 5434 break;
5435 case CODE_32BIT:
40fb9820
L		 5436 for (j = 0; j < MAX_OPERANDS; j++)
5437 {
5438 if (operand_types[j].bitfield.disp32)
5439 {
5440 addr_prefix_disp = j;
5441 operand_types[j].bitfield.disp32 = 0;
5442 operand_types[j].bitfield.disp16 = 1;
5443 break;
5444 }
5445 }
539e75ad
L		 5446 break;
5447 case CODE_64BIT:
40fb9820
L		 5448 for (j = 0; j < MAX_OPERANDS; j++)
5449 {
5450 if (operand_types[j].bitfield.disp64)
5451 {
5452 addr_prefix_disp = j;
5453 operand_types[j].bitfield.disp64 = 0;
5454 operand_types[j].bitfield.disp32 = 1;
5455 break;
5456 }
5457 }
539e75ad
L		 5458 break;
5459 }
539e75ad
L		 5460 }
5461
02a86693
L		 5462 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5463 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5464 continue;
5465
56ffb741 5466 /* We check register size if needed. */
e2195274
JB		 5467 if (t->opcode_modifier.checkregsize)
5468 {
5469 check_register = (1 << t->operands) - 1;
5470 if (i.broadcast)
5471 check_register &= ~(1 << i.broadcast->operand);
5472 }
5473 else
5474 check_register = 0;
5475
c6fb90c8 5476 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5477 switch (t->operands)
5478 {
5479 case 1:
40fb9820 5480 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5481 continue;
5482 break;
5483 case 2:
33eaf5de 5484 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5485 only in 32bit mode and we can use opcode 0x90. In 64bit
5486 mode, we can't use 0x90 for xchg %eax, %eax since it should
5487 zero-extend %eax to %rax. */
5488 if (flag_code == CODE_64BIT
5489 && t->base_opcode == 0x90
0dfbf9d7
L		 5490 && operand_type_equal (&i.types [0], &acc32)
5491 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 5492 continue;
1212781b
JB		 5493 /* xrelease mov %eax, <disp> is another special case. It must not
5494 match the accumulator-only encoding of mov. */
5495 if (flag_code != CODE_64BIT
5496 && i.hle_prefix
5497 && t->base_opcode == 0xa0
5498 && i.types[0].bitfield.acc
5499 && operand_type_check (i.types[1], anymem))
5500 continue;
86fa6981
L		 5501 /* If we want store form, we reverse direction of operands. */
5502 if (i.dir_encoding == dir_encoding_store
5503 && t->opcode_modifier.d)
5504 goto check_reverse;
1a0670f3 5505 /* Fall through. */
b6169b20 5506
29b0f896 5507 case 3:
86fa6981
L		 5508 /* If we want store form, we skip the current load. */
5509 if (i.dir_encoding == dir_encoding_store
5510 && i.mem_operands == 0
5511 && t->opcode_modifier.load)
fa99fab2 5512 continue;
1a0670f3 5513 /* Fall through. */
f48ff2ae 5514 case 4:
c0f3af97 5515 case 5:
c6fb90c8 5516 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5517 if (!operand_type_match (overlap0, i.types[0])
5518 || !operand_type_match (overlap1, i.types[1])
e2195274 5519 || ((check_register & 3) == 3
dc821c5f 5520 && !operand_type_register_match (i.types[0],
40fb9820 5521 operand_types[0],
dc821c5f 5522 i.types[1],
40fb9820 5523 operand_types[1])))
29b0f896
AM		 5524 {
5525 /* Check if other direction is valid ... */
38e314eb 5526 if (!t->opcode_modifier.d)
29b0f896
AM		 5527 continue;
5528
b6169b20 5529check_reverse:
29b0f896 5530 /* Try reversing direction of operands. */
c6fb90c8
L		 5531 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5532 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 5533 if (!operand_type_match (overlap0, i.types[0])
5534 || !operand_type_match (overlap1, i.types[1])
45664ddb 5535 || (check_register
dc821c5f 5536 && !operand_type_register_match (i.types[0],
45664ddb 5537 operand_types[1],
45664ddb
L		 5538 i.types[1],
5539 operand_types[0])))
29b0f896
AM		 5540 {
5541 /* Does not match either direction. */
5542 continue;
5543 }
38e314eb 5544 /* found_reverse_match holds which of D or FloatR
29b0f896 5545 we've found. */
38e314eb
JB		 5546 if (!t->opcode_modifier.d)
5547 found_reverse_match = 0;
5548 else if (operand_types[0].bitfield.tbyte)
8a2ed489
L		 5549 found_reverse_match = Opcode_FloatD;
5550 else
38e314eb 5551 found_reverse_match = Opcode_D;
40fb9820 5552 if (t->opcode_modifier.floatr)
8a2ed489 5553 found_reverse_match |= Opcode_FloatR;
29b0f896 5554 }
f48ff2ae 5555 else
29b0f896 5556 {
f48ff2ae 5557 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5558 switch (t->operands)
5559 {
c0f3af97
L		 5560 case 5:
5561 overlap4 = operand_type_and (i.types[4],
5562 operand_types[4]);
1a0670f3 5563 /* Fall through. */
d1cbb4db 5564 case 4:
c6fb90c8
L		 5565 overlap3 = operand_type_and (i.types[3],
5566 operand_types[3]);
1a0670f3 5567 /* Fall through. */
d1cbb4db 5568 case 3:
c6fb90c8
L		 5569 overlap2 = operand_type_and (i.types[2],
5570 operand_types[2]);
d1cbb4db
L		 5571 break;
5572 }
29b0f896 5573
f48ff2ae
L		 5574 switch (t->operands)
5575 {
c0f3af97
L		 5576 case 5:
5577 if (!operand_type_match (overlap4, i.types[4])
dc821c5f 5578 || !operand_type_register_match (i.types[3],
c0f3af97 5579 operand_types[3],
c0f3af97
L		 5580 i.types[4],
5581 operand_types[4]))
5582 continue;
1a0670f3 5583 /* Fall through. */
f48ff2ae 5584 case 4:
40fb9820 5585 if (!operand_type_match (overlap3, i.types[3])
e2195274
JB		 5586 || ((check_register & 0xa) == 0xa
5587 && !operand_type_register_match (i.types[1],
f7768225
JB		 5588 operand_types[1],
5589 i.types[3],
e2195274
JB		 5590 operand_types[3]))
5591 || ((check_register & 0xc) == 0xc
5592 && !operand_type_register_match (i.types[2],
5593 operand_types[2],
5594 i.types[3],
5595 operand_types[3])))
f48ff2ae 5596 continue;
1a0670f3 5597 /* Fall through. */
f48ff2ae
L		 5598 case 3:
5599 /* Here we make use of the fact that there are no
23e42951 5600 reverse match 3 operand instructions. */
40fb9820 5601 if (!operand_type_match (overlap2, i.types[2])
e2195274
JB		 5602 || ((check_register & 5) == 5
5603 && !operand_type_register_match (i.types[0],
23e42951
JB		 5604 operand_types[0],
5605 i.types[2],
e2195274
JB		 5606 operand_types[2]))
5607 || ((check_register & 6) == 6
5608 && !operand_type_register_match (i.types[1],
5609 operand_types[1],
5610 i.types[2],
5611 operand_types[2])))
f48ff2ae
L		 5612 continue;
5613 break;
5614 }
29b0f896 5615 }
f48ff2ae 5616 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5617 slip through to break. */
5618 }
3629bb00 5619 if (!found_cpu_match)
29b0f896
AM		 5620 {
5621 found_reverse_match = 0;
5622 continue;
5623 }
c0f3af97 5624
5614d22c
JB		 5625 /* Check if vector and VEX operands are valid. */
5626 if (check_VecOperands (t) || VEX_check_operands (t))
5627 {
5628 specific_error = i.error;
5629 continue;
5630 }
a683cc34 5631
29b0f896
AM		 5632 /* We've found a match; break out of loop. */
5633 break;
5634 }
5635
5636 if (t == current_templates->end)
5637 {
5638 /* We found no match. */
a65babc9 5639 const char *err_msg;
5614d22c 5640 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5641 {
5642 default:
5643 abort ();
86e026a4 5644 case operand_size_mismatch:
a65babc9
L		 5645 err_msg = _("operand size mismatch");
5646 break;
5647 case operand_type_mismatch:
5648 err_msg = _("operand type mismatch");
5649 break;
5650 case register_type_mismatch:
5651 err_msg = _("register type mismatch");
5652 break;
5653 case number_of_operands_mismatch:
5654 err_msg = _("number of operands mismatch");
5655 break;
5656 case invalid_instruction_suffix:
5657 err_msg = _("invalid instruction suffix");
5658 break;
5659 case bad_imm4:
4a2608e3 5660 err_msg = _("constant doesn't fit in 4 bits");
a65babc9 5661 break;
a65babc9
L		 5662 case unsupported_with_intel_mnemonic:
5663 err_msg = _("unsupported with Intel mnemonic");
5664 break;
5665 case unsupported_syntax:
5666 err_msg = _("unsupported syntax");
5667 break;
5668 case unsupported:
35262a23 5669 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5670 current_templates->start->name);
5671 return NULL;
6c30d220
L		 5672 case invalid_vsib_address:
5673 err_msg = _("invalid VSIB address");
5674 break;
7bab8ab5
JB		 5675 case invalid_vector_register_set:
5676 err_msg = _("mask, index, and destination registers must be distinct");
5677 break;
6c30d220
L		 5678 case unsupported_vector_index_register:
5679 err_msg = _("unsupported vector index register");
5680 break;
43234a1e
L		 5681 case unsupported_broadcast:
5682 err_msg = _("unsupported broadcast");
5683 break;
5684 case broadcast_not_on_src_operand:
5685 err_msg = _("broadcast not on source memory operand");
5686 break;
5687 case broadcast_needed:
5688 err_msg = _("broadcast is needed for operand of such type");
5689 break;
5690 case unsupported_masking:
5691 err_msg = _("unsupported masking");
5692 break;
5693 case mask_not_on_destination:
5694 err_msg = _("mask not on destination operand");
5695 break;
5696 case no_default_mask:
5697 err_msg = _("default mask isn't allowed");
5698 break;
5699 case unsupported_rc_sae:
5700 err_msg = _("unsupported static rounding/sae");
5701 break;
5702 case rc_sae_operand_not_last_imm:
5703 if (intel_syntax)
5704 err_msg = _("RC/SAE operand must precede immediate operands");
5705 else
5706 err_msg = _("RC/SAE operand must follow immediate operands");
5707 break;
5708 case invalid_register_operand:
5709 err_msg = _("invalid register operand");
5710 break;
a65babc9
L		 5711 }
5712 as_bad (_("%s for `%s'"), err_msg,
891edac4 5713 current_templates->start->name);
fa99fab2 5714 return NULL;
29b0f896 5715 }
252b5132 5716
29b0f896
AM		 5717 if (!quiet_warnings)
5718 {
5719 if (!intel_syntax
40fb9820
L		 5720 && (i.types[0].bitfield.jumpabsolute
5721 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5722 {
5723 as_warn (_("indirect %s without `*'"), t->name);
5724 }
5725
40fb9820
L		 5726 if (t->opcode_modifier.isprefix
5727 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5728 {
5729 /* Warn them that a data or address size prefix doesn't
5730 affect assembly of the next line of code. */
5731 as_warn (_("stand-alone `%s' prefix"), t->name);
5732 }
5733 }
5734
5735 /* Copy the template we found. */
5736 i.tm = *t;
539e75ad
L		 5737
5738 if (addr_prefix_disp != -1)
5739 i.tm.operand_types[addr_prefix_disp]
5740 = operand_types[addr_prefix_disp];
5741
29b0f896
AM		 5742 if (found_reverse_match)
5743 {
5744 /* If we found a reverse match we must alter the opcode
5745 direction bit. found_reverse_match holds bits to change
5746 (different for int & float insns). */
5747
5748 i.tm.base_opcode ^= found_reverse_match;
5749
539e75ad
L		 5750 i.tm.operand_types[0] = operand_types[1];
5751 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5752 }
5753
fa99fab2 5754 return t;
29b0f896
AM		 5755}
5756
5757static int
e3bb37b5 5758check_string (void)
29b0f896 5759{
40fb9820
L		 5760 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5761 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5762 {
5763 if (i.seg[0] != NULL && i.seg[0] != &es)
5764 {
a87af027 5765 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5766 i.tm.name,
a87af027
JB		 5767 mem_op + 1,
5768 register_prefix);
29b0f896
AM		 5769 return 0;
5770 }
5771 /* There's only ever one segment override allowed per instruction.
5772 This instruction possibly has a legal segment override on the
5773 second operand, so copy the segment to where non-string
5774 instructions store it, allowing common code. */
5775 i.seg[0] = i.seg[1];
5776 }
40fb9820 5777 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5778 {
5779 if (i.seg[1] != NULL && i.seg[1] != &es)
5780 {
a87af027 5781 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5782 i.tm.name,
a87af027
JB		 5783 mem_op + 2,
5784 register_prefix);
29b0f896
AM		 5785 return 0;
5786 }
5787 }
5788 return 1;
5789}
5790
5791static int
543613e9 5792process_suffix (void)
29b0f896
AM		 5793{
5794 /* If matched instruction specifies an explicit instruction mnemonic
5795 suffix, use it. */
40fb9820
L		 5796 if (i.tm.opcode_modifier.size16)
5797 i.suffix = WORD_MNEM_SUFFIX;
5798 else if (i.tm.opcode_modifier.size32)
5799 i.suffix = LONG_MNEM_SUFFIX;
5800 else if (i.tm.opcode_modifier.size64)
5801 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5802 else if (i.reg_operands)
5803 {
5804 /* If there's no instruction mnemonic suffix we try to invent one
5805 based on register operands. */
5806 if (!i.suffix)
5807 {
5808 /* We take i.suffix from the last register operand specified,
5809 Destination register type is more significant than source
381d071f
L		 5810 register type. crc32 in SSE4.2 prefers source register
5811 type. */
5812 if (i.tm.base_opcode == 0xf20f38f1)
5813 {
dc821c5f 5814 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
40fb9820 5815 i.suffix = WORD_MNEM_SUFFIX;
dc821c5f 5816 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
40fb9820 5817 i.suffix = LONG_MNEM_SUFFIX;
dc821c5f 5818 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
40fb9820 5819 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5820 }
9344ff29 5821 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5822 {
dc821c5f 5823 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
20592a94
L		 5824 i.suffix = BYTE_MNEM_SUFFIX;
5825 }
381d071f
L		 5826
5827 if (!i.suffix)
5828 {
5829 int op;
5830
20592a94
L		 5831 if (i.tm.base_opcode == 0xf20f38f1
5832 || i.tm.base_opcode == 0xf20f38f0)
5833 {
5834 /* We have to know the operand size for crc32. */
5835 as_bad (_("ambiguous memory operand size for `%s`"),
5836 i.tm.name);
5837 return 0;
5838 }
5839
381d071f 5840 for (op = i.operands; --op >= 0;)
b76bc5d5
JB		 5841 if (!i.tm.operand_types[op].bitfield.inoutportreg
5842 && !i.tm.operand_types[op].bitfield.shiftcount)
381d071f 5843 {
8819ada6
JB		 5844 if (!i.types[op].bitfield.reg)
5845 continue;
5846 if (i.types[op].bitfield.byte)
5847 i.suffix = BYTE_MNEM_SUFFIX;
5848 else if (i.types[op].bitfield.word)
5849 i.suffix = WORD_MNEM_SUFFIX;
5850 else if (i.types[op].bitfield.dword)
5851 i.suffix = LONG_MNEM_SUFFIX;
5852 else if (i.types[op].bitfield.qword)
5853 i.suffix = QWORD_MNEM_SUFFIX;
5854 else
5855 continue;
5856 break;
381d071f
L		 5857 }
5858 }
29b0f896
AM		 5859 }
5860 else if (i.suffix == BYTE_MNEM_SUFFIX)
5861 {
2eb952a4
L		 5862 if (intel_syntax
5863 && i.tm.opcode_modifier.ignoresize
5864 && i.tm.opcode_modifier.no_bsuf)
5865 i.suffix = 0;
5866 else if (!check_byte_reg ())
29b0f896
AM		 5867 return 0;
5868 }
5869 else if (i.suffix == LONG_MNEM_SUFFIX)
5870 {
2eb952a4
L		 5871 if (intel_syntax
5872 && i.tm.opcode_modifier.ignoresize
9f123b91
JB		 5873 && i.tm.opcode_modifier.no_lsuf
5874 && !i.tm.opcode_modifier.todword
5875 && !i.tm.opcode_modifier.toqword)
2eb952a4
L		 5876 i.suffix = 0;
5877 else if (!check_long_reg ())
29b0f896
AM		 5878 return 0;
5879 }
5880 else if (i.suffix == QWORD_MNEM_SUFFIX)
5881 {
955e1e6a
L		 5882 if (intel_syntax
5883 && i.tm.opcode_modifier.ignoresize
9f123b91
JB		 5884 && i.tm.opcode_modifier.no_qsuf
5885 && !i.tm.opcode_modifier.todword
5886 && !i.tm.opcode_modifier.toqword)
955e1e6a
L		 5887 i.suffix = 0;
5888 else if (!check_qword_reg ())
29b0f896
AM		 5889 return 0;
5890 }
5891 else if (i.suffix == WORD_MNEM_SUFFIX)
5892 {
2eb952a4
L		 5893 if (intel_syntax
5894 && i.tm.opcode_modifier.ignoresize
5895 && i.tm.opcode_modifier.no_wsuf)
5896 i.suffix = 0;
5897 else if (!check_word_reg ())
29b0f896
AM		 5898 return 0;
5899 }
40fb9820 5900 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5901 /* Do nothing if the instruction is going to ignore the prefix. */
5902 ;
5903 else
5904 abort ();
5905 }
40fb9820 5906 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5907 && !i.suffix
5908 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5909 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5910 {
5911 i.suffix = stackop_size;
5912 }
9306ca4a
JB		 5913 else if (intel_syntax
5914 && !i.suffix
40fb9820
L		 5915 && (i.tm.operand_types[0].bitfield.jumpabsolute
5916 || i.tm.opcode_modifier.jumpbyte
5917 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5918 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5919 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5920 {
5921 switch (flag_code)
5922 {
5923 case CODE_64BIT:
40fb9820 5924 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5925 {
5926 i.suffix = QWORD_MNEM_SUFFIX;
5927 break;
5928 }
1a0670f3 5929 /* Fall through. */
9306ca4a 5930 case CODE_32BIT:
40fb9820 5931 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5932 i.suffix = LONG_MNEM_SUFFIX;
5933 break;
5934 case CODE_16BIT:
40fb9820 5935 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5936 i.suffix = WORD_MNEM_SUFFIX;
5937 break;
5938 }
5939 }
252b5132 5940
9306ca4a 5941 if (!i.suffix)
29b0f896 5942 {
9306ca4a
JB		 5943 if (!intel_syntax)
5944 {
40fb9820 5945 if (i.tm.opcode_modifier.w)
9306ca4a 5946 {
4eed87de
AM		 5947 as_bad (_("no instruction mnemonic suffix given and "
5948 "no register operands; can't size instruction"));
9306ca4a
JB		 5949 return 0;
5950 }
5951 }
5952 else
5953 {
40fb9820 5954 unsigned int suffixes;
7ab9ffdd 5955
40fb9820
L		 5956 suffixes = !i.tm.opcode_modifier.no_bsuf;
5957 if (!i.tm.opcode_modifier.no_wsuf)
5958 suffixes |= 1 << 1;
5959 if (!i.tm.opcode_modifier.no_lsuf)
5960 suffixes |= 1 << 2;
fc4adea1 5961 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5962 suffixes |= 1 << 3;
5963 if (!i.tm.opcode_modifier.no_ssuf)
5964 suffixes |= 1 << 4;
c2b9da16 5965 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
40fb9820
L		 5966 suffixes |= 1 << 5;
5967
5968 /* There are more than suffix matches. */
5969 if (i.tm.opcode_modifier.w
9306ca4a 5970 || ((suffixes & (suffixes - 1))
40fb9820
L		 5971 && !i.tm.opcode_modifier.defaultsize
5972 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5973 {
5974 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5975 return 0;
5976 }
5977 }
29b0f896 5978 }
252b5132 5979
d2224064
JB		 5980 /* Change the opcode based on the operand size given by i.suffix. */
5981 switch (i.suffix)
29b0f896 5982 {
d2224064
JB		 5983 /* Size floating point instruction. */
5984 case LONG_MNEM_SUFFIX:
5985 if (i.tm.opcode_modifier.floatmf)
5986 {
5987 i.tm.base_opcode ^= 4;
5988 break;
5989 }
5990 /* fall through */
5991 case WORD_MNEM_SUFFIX:
5992 case QWORD_MNEM_SUFFIX:
29b0f896 5993 /* It's not a byte, select word/dword operation. */
40fb9820 5994 if (i.tm.opcode_modifier.w)
29b0f896 5995 {
40fb9820 5996 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5997 i.tm.base_opcode |= 8;
5998 else
5999 i.tm.base_opcode |= 1;
6000 }
d2224064
JB		 6001 /* fall through */
6002 case SHORT_MNEM_SUFFIX:
29b0f896
AM		 6003 /* Now select between word & dword operations via the operand
6004 size prefix, except for instructions that will ignore this
6005 prefix anyway. */
75c0a438
L		 6006 if (i.reg_operands > 0
6007 && i.types[0].bitfield.reg
6008 && i.tm.opcode_modifier.addrprefixopreg
6009 && (i.tm.opcode_modifier.immext
6010 || i.operands == 1))
cb712a9e 6011 {
ca61edf2
L		 6012 /* The address size override prefix changes the size of the
6013 first operand. */
40fb9820 6014 if ((flag_code == CODE_32BIT
75c0a438 6015 && i.op[0].regs->reg_type.bitfield.word)
40fb9820 6016 || (flag_code != CODE_32BIT
75c0a438 6017 && i.op[0].regs->reg_type.bitfield.dword))
cb712a9e
L		 6018 if (!add_prefix (ADDR_PREFIX_OPCODE))
6019 return 0;
6020 }
6021 else if (i.suffix != QWORD_MNEM_SUFFIX
40fb9820
L		 6022 && !i.tm.opcode_modifier.ignoresize
6023 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 6024 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
6025 || (flag_code == CODE_64BIT
40fb9820 6026 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 6027 {
6028 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 6029
40fb9820 6030 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 6031 prefix = ADDR_PREFIX_OPCODE;
252b5132 6032
29b0f896
AM		 6033 if (!add_prefix (prefix))
6034 return 0;
24eab124 6035 }
252b5132 6036
29b0f896
AM		 6037 /* Set mode64 for an operand. */
6038 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 6039 && flag_code == CODE_64BIT
d2224064 6040 && !i.tm.opcode_modifier.norex64
46e883c5 6041 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d2224064
JB		 6042 need rex64. */
6043 && ! (i.operands == 2
6044 && i.tm.base_opcode == 0x90
6045 && i.tm.extension_opcode == None
6046 && operand_type_equal (&i.types [0], &acc64)
6047 && operand_type_equal (&i.types [1], &acc64)))
6048 i.rex |= REX_W;
3e73aa7c 6049
d2224064 6050 break;
29b0f896 6051 }
7ecd2f8b 6052
c0a30a9f
L		 6053 if (i.reg_operands != 0
6054 && i.operands > 1
6055 && i.tm.opcode_modifier.addrprefixopreg
6056 && !i.tm.opcode_modifier.immext)
6057 {
6058 /* Check invalid register operand when the address size override
6059 prefix changes the size of register operands. */
6060 unsigned int op;
6061 enum { need_word, need_dword, need_qword } need;
6062
6063 if (flag_code == CODE_32BIT)
6064 need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
6065 else
6066 {
6067 if (i.prefix[ADDR_PREFIX])
6068 need = need_dword;
6069 else
6070 need = flag_code == CODE_64BIT ? need_qword : need_word;
6071 }
6072
6073 for (op = 0; op < i.operands; op++)
6074 if (i.types[op].bitfield.reg
6075 && ((need == need_word
6076 && !i.op[op].regs->reg_type.bitfield.word)
6077 || (need == need_dword
6078 && !i.op[op].regs->reg_type.bitfield.dword)
6079 || (need == need_qword
6080 && !i.op[op].regs->reg_type.bitfield.qword)))
6081 {
6082 as_bad (_("invalid register operand size for `%s'"),
6083 i.tm.name);
6084 return 0;
6085 }
6086 }
6087
29b0f896
AM		 6088 return 1;
6089}
3e73aa7c 6090
29b0f896 6091static int
543613e9 6092check_byte_reg (void)
29b0f896
AM		 6093{
6094 int op;
543613e9 6095
29b0f896
AM		 6096 for (op = i.operands; --op >= 0;)
6097 {
dc821c5f
JB		 6098 /* Skip non-register operands. */
6099 if (!i.types[op].bitfield.reg)
6100 continue;
6101
29b0f896
AM		 6102 /* If this is an eight bit register, it's OK. If it's the 16 or
6103 32 bit version of an eight bit register, we will just use the
6104 low portion, and that's OK too. */
dc821c5f 6105 if (i.types[op].bitfield.byte)
29b0f896
AM		 6106 continue;
6107
5a819eb9
JB		 6108 /* I/O port address operands are OK too. */
6109 if (i.tm.operand_types[op].bitfield.inoutportreg)
6110 continue;
6111
9344ff29
L		 6112 /* crc32 doesn't generate this warning. */
6113 if (i.tm.base_opcode == 0xf20f38f0)
6114 continue;
6115
dc821c5f
JB		 6116 if ((i.types[op].bitfield.word
6117 || i.types[op].bitfield.dword
6118 || i.types[op].bitfield.qword)
5a819eb9
JB		 6119 && i.op[op].regs->reg_num < 4
6120 /* Prohibit these changes in 64bit mode, since the lowering
6121 would be more complicated. */
6122 && flag_code != CODE_64BIT)
29b0f896 6123 {
29b0f896 6124#if REGISTER_WARNINGS
5a819eb9 6125 if (!quiet_warnings)
a540244d
L		 6126 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6127 register_prefix,
dc821c5f 6128 (i.op[op].regs + (i.types[op].bitfield.word
29b0f896
AM		 6129 ? REGNAM_AL - REGNAM_AX
6130 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 6131 register_prefix,
29b0f896
AM		 6132 i.op[op].regs->reg_name,
6133 i.suffix);
6134#endif
6135 continue;
6136 }
6137 /* Any other register is bad. */
dc821c5f 6138 if (i.types[op].bitfield.reg
40fb9820 6139 || i.types[op].bitfield.regmmx
1b54b8d7 6140 || i.types[op].bitfield.regsimd
40fb9820
L		 6141 || i.types[op].bitfield.sreg2
6142 || i.types[op].bitfield.sreg3
6143 || i.types[op].bitfield.control
6144 || i.types[op].bitfield.debug
ca0d63fe 6145 || i.types[op].bitfield.test)
29b0f896 6146 {
a540244d
L		 6147 as_bad (_("`%s%s' not allowed with `%s%c'"),
6148 register_prefix,
29b0f896
AM		 6149 i.op[op].regs->reg_name,
6150 i.tm.name,
6151 i.suffix);
6152 return 0;
6153 }
6154 }
6155 return 1;
6156}
6157
6158static int
e3bb37b5 6159check_long_reg (void)
29b0f896
AM		 6160{
6161 int op;
6162
6163 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6164 /* Skip non-register operands. */
6165 if (!i.types[op].bitfield.reg)
6166 continue;
29b0f896
AM		 6167 /* Reject eight bit registers, except where the template requires
6168 them. (eg. movzb) */
dc821c5f
JB		 6169 else if (i.types[op].bitfield.byte
6170 && (i.tm.operand_types[op].bitfield.reg
6171 || i.tm.operand_types[op].bitfield.acc)
6172 && (i.tm.operand_types[op].bitfield.word
6173 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6174 {
a540244d
L		 6175 as_bad (_("`%s%s' not allowed with `%s%c'"),
6176 register_prefix,
29b0f896
AM		 6177 i.op[op].regs->reg_name,
6178 i.tm.name,
6179 i.suffix);
6180 return 0;
6181 }
e4630f71 6182 /* Warn if the e prefix on a general reg is missing. */
29b0f896 6183 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6184 && i.types[op].bitfield.word
6185 && (i.tm.operand_types[op].bitfield.reg
6186 || i.tm.operand_types[op].bitfield.acc)
6187 && i.tm.operand_types[op].bitfield.dword)
29b0f896
AM		 6188 {
6189 /* Prohibit these changes in the 64bit mode, since the
6190 lowering is more complicated. */
6191 if (flag_code == CODE_64BIT)
252b5132 6192 {
2b5d6a91 6193 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6194 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6195 i.suffix);
6196 return 0;
252b5132 6197 }
29b0f896 6198#if REGISTER_WARNINGS
cecf1424
JB		 6199 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6200 register_prefix,
6201 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6202 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 6203#endif
252b5132 6204 }
e4630f71 6205 /* Warn if the r prefix on a general reg is present. */
dc821c5f
JB		 6206 else if (i.types[op].bitfield.qword
6207 && (i.tm.operand_types[op].bitfield.reg
6208 || i.tm.operand_types[op].bitfield.acc)
6209 && i.tm.operand_types[op].bitfield.dword)
252b5132 6210 {
34828aad 6211 if (intel_syntax
ca61edf2 6212 && i.tm.opcode_modifier.toqword
1b54b8d7 6213 && !i.types[0].bitfield.regsimd)
34828aad 6214 {
ca61edf2 6215 /* Convert to QWORD. We want REX byte. */
34828aad
L		 6216 i.suffix = QWORD_MNEM_SUFFIX;
6217 }
6218 else
6219 {
2b5d6a91 6220 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6221 register_prefix, i.op[op].regs->reg_name,
6222 i.suffix);
6223 return 0;
6224 }
29b0f896
AM		 6225 }
6226 return 1;
6227}
252b5132 6228
29b0f896 6229static int
e3bb37b5 6230check_qword_reg (void)
29b0f896
AM		 6231{
6232 int op;
252b5132 6233
29b0f896 6234 for (op = i.operands; --op >= 0; )
dc821c5f
JB		 6235 /* Skip non-register operands. */
6236 if (!i.types[op].bitfield.reg)
6237 continue;
29b0f896
AM		 6238 /* Reject eight bit registers, except where the template requires
6239 them. (eg. movzb) */
dc821c5f
JB		 6240 else if (i.types[op].bitfield.byte
6241 && (i.tm.operand_types[op].bitfield.reg
6242 || i.tm.operand_types[op].bitfield.acc)
6243 && (i.tm.operand_types[op].bitfield.word
6244 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6245 {
a540244d
L		 6246 as_bad (_("`%s%s' not allowed with `%s%c'"),
6247 register_prefix,
29b0f896
AM		 6248 i.op[op].regs->reg_name,
6249 i.tm.name,
6250 i.suffix);
6251 return 0;
6252 }
e4630f71 6253 /* Warn if the r prefix on a general reg is missing. */
dc821c5f
JB		 6254 else if ((i.types[op].bitfield.word
6255 || i.types[op].bitfield.dword)
6256 && (i.tm.operand_types[op].bitfield.reg
6257 || i.tm.operand_types[op].bitfield.acc)
6258 && i.tm.operand_types[op].bitfield.qword)
29b0f896
AM		 6259 {
6260 /* Prohibit these changes in the 64bit mode, since the
6261 lowering is more complicated. */
34828aad 6262 if (intel_syntax
ca61edf2 6263 && i.tm.opcode_modifier.todword
1b54b8d7 6264 && !i.types[0].bitfield.regsimd)
34828aad 6265 {
ca61edf2 6266 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 6267 i.suffix = LONG_MNEM_SUFFIX;
6268 }
6269 else
6270 {
2b5d6a91 6271 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6272 register_prefix, i.op[op].regs->reg_name,
6273 i.suffix);
6274 return 0;
6275 }
252b5132 6276 }
29b0f896
AM		 6277 return 1;
6278}
252b5132 6279
29b0f896 6280static int
e3bb37b5 6281check_word_reg (void)
29b0f896
AM		 6282{
6283 int op;
6284 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6285 /* Skip non-register operands. */
6286 if (!i.types[op].bitfield.reg)
6287 continue;
29b0f896
AM		 6288 /* Reject eight bit registers, except where the template requires
6289 them. (eg. movzb) */
dc821c5f
JB		 6290 else if (i.types[op].bitfield.byte
6291 && (i.tm.operand_types[op].bitfield.reg
6292 || i.tm.operand_types[op].bitfield.acc)
6293 && (i.tm.operand_types[op].bitfield.word
6294 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6295 {
a540244d
L		 6296 as_bad (_("`%s%s' not allowed with `%s%c'"),
6297 register_prefix,
29b0f896
AM		 6298 i.op[op].regs->reg_name,
6299 i.tm.name,
6300 i.suffix);
6301 return 0;
6302 }
e4630f71 6303 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 6304 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6305 && (i.types[op].bitfield.dword
6306 || i.types[op].bitfield.qword)
6307 && (i.tm.operand_types[op].bitfield.reg
6308 || i.tm.operand_types[op].bitfield.acc)
6309 && i.tm.operand_types[op].bitfield.word)
252b5132 6310 {
29b0f896
AM		 6311 /* Prohibit these changes in the 64bit mode, since the
6312 lowering is more complicated. */
6313 if (flag_code == CODE_64BIT)
252b5132 6314 {
2b5d6a91 6315 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6316 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6317 i.suffix);
6318 return 0;
252b5132 6319 }
29b0f896 6320#if REGISTER_WARNINGS
cecf1424
JB		 6321 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6322 register_prefix,
6323 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6324 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 6325#endif
6326 }
6327 return 1;
6328}
252b5132 6329
29b0f896 6330static int
40fb9820 6331update_imm (unsigned int j)
29b0f896 6332{
bc0844ae 6333 i386_operand_type overlap = i.types[j];
40fb9820
L		 6334 if ((overlap.bitfield.imm8
6335 || overlap.bitfield.imm8s
6336 || overlap.bitfield.imm16
6337 || overlap.bitfield.imm32
6338 || overlap.bitfield.imm32s
6339 || overlap.bitfield.imm64)
0dfbf9d7
L		 6340 && !operand_type_equal (&overlap, &imm8)
6341 && !operand_type_equal (&overlap, &imm8s)
6342 && !operand_type_equal (&overlap, &imm16)
6343 && !operand_type_equal (&overlap, &imm32)
6344 && !operand_type_equal (&overlap, &imm32s)
6345 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 6346 {
6347 if (i.suffix)
6348 {
40fb9820
L		 6349 i386_operand_type temp;
6350
0dfbf9d7 6351 operand_type_set (&temp, 0);
7ab9ffdd 6352 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 6353 {
6354 temp.bitfield.imm8 = overlap.bitfield.imm8;
6355 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6356 }
6357 else if (i.suffix == WORD_MNEM_SUFFIX)
6358 temp.bitfield.imm16 = overlap.bitfield.imm16;
6359 else if (i.suffix == QWORD_MNEM_SUFFIX)
6360 {
6361 temp.bitfield.imm64 = overlap.bitfield.imm64;
6362 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6363 }
6364 else
6365 temp.bitfield.imm32 = overlap.bitfield.imm32;
6366 overlap = temp;
29b0f896 6367 }
0dfbf9d7
L		 6368 else if (operand_type_equal (&overlap, &imm16_32_32s)
6369 || operand_type_equal (&overlap, &imm16_32)
6370 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 6371 {
40fb9820 6372 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 6373 overlap = imm16;
40fb9820 6374 else
65da13b5 6375 overlap = imm32s;
29b0f896 6376 }
0dfbf9d7
L		 6377 if (!operand_type_equal (&overlap, &imm8)
6378 && !operand_type_equal (&overlap, &imm8s)
6379 && !operand_type_equal (&overlap, &imm16)
6380 && !operand_type_equal (&overlap, &imm32)
6381 && !operand_type_equal (&overlap, &imm32s)
6382 && !operand_type_equal (&overlap, &imm64))
29b0f896 6383 {
4eed87de
AM		 6384 as_bad (_("no instruction mnemonic suffix given; "
6385 "can't determine immediate size"));
29b0f896
AM		 6386 return 0;
6387 }
6388 }
40fb9820 6389 i.types[j] = overlap;
29b0f896 6390
40fb9820
L		 6391 return 1;
6392}
6393
6394static int
6395finalize_imm (void)
6396{
bc0844ae 6397 unsigned int j, n;
29b0f896 6398
bc0844ae
L		 6399 /* Update the first 2 immediate operands. */
6400 n = i.operands > 2 ? 2 : i.operands;
6401 if (n)
6402 {
6403 for (j = 0; j < n; j++)
6404 if (update_imm (j) == 0)
6405 return 0;
40fb9820 6406
bc0844ae
L		 6407 /* The 3rd operand can't be immediate operand. */
6408 gas_assert (operand_type_check (i.types[2], imm) == 0);
6409 }
29b0f896
AM		 6410
6411 return 1;
6412}
6413
6414static int
e3bb37b5 6415process_operands (void)
29b0f896
AM		 6416{
6417 /* Default segment register this instruction will use for memory
6418 accesses. 0 means unknown. This is only for optimizing out
6419 unnecessary segment overrides. */
6420 const seg_entry *default_seg = 0;
6421
2426c15f 6422 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 6423 {
91d6fa6a
NC		 6424 unsigned int dupl = i.operands;
6425 unsigned int dest = dupl - 1;
9fcfb3d7
L		 6426 unsigned int j;
6427
c0f3af97 6428 /* The destination must be an xmm register. */
9c2799c2 6429 gas_assert (i.reg_operands
91d6fa6a 6430 && MAX_OPERANDS > dupl
7ab9ffdd 6431 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97 6432
1b54b8d7
JB		 6433 if (i.tm.operand_types[0].bitfield.acc
6434 && i.tm.operand_types[0].bitfield.xmmword)
e2ec9d29 6435 {
8cd7925b 6436 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 6437 {
6438 /* Keep xmm0 for instructions with VEX prefix and 3
6439 sources. */
1b54b8d7
JB		 6440 i.tm.operand_types[0].bitfield.acc = 0;
6441 i.tm.operand_types[0].bitfield.regsimd = 1;
c0f3af97
L		 6442 goto duplicate;
6443 }
e2ec9d29 6444 else
c0f3af97
L		 6445 {
6446 /* We remove the first xmm0 and keep the number of
6447 operands unchanged, which in fact duplicates the
6448 destination. */
6449 for (j = 1; j < i.operands; j++)
6450 {
6451 i.op[j - 1] = i.op[j];
6452 i.types[j - 1] = i.types[j];
6453 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6454 }
6455 }
6456 }
6457 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 6458 {
91d6fa6a 6459 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 6460 && (i.tm.opcode_modifier.vexsources
6461 == VEX3SOURCES));
c0f3af97
L		 6462
6463 /* Add the implicit xmm0 for instructions with VEX prefix
6464 and 3 sources. */
6465 for (j = i.operands; j > 0; j--)
6466 {
6467 i.op[j] = i.op[j - 1];
6468 i.types[j] = i.types[j - 1];
6469 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6470 }
6471 i.op[0].regs
6472 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 6473 i.types[0] = regxmm;
c0f3af97
L		 6474 i.tm.operand_types[0] = regxmm;
6475
6476 i.operands += 2;
6477 i.reg_operands += 2;
6478 i.tm.operands += 2;
6479
91d6fa6a 6480 dupl++;
c0f3af97 6481 dest++;
91d6fa6a
NC		 6482 i.op[dupl] = i.op[dest];
6483 i.types[dupl] = i.types[dest];
6484 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6485 }
c0f3af97
L		 6486 else
6487 {
6488duplicate:
6489 i.operands++;
6490 i.reg_operands++;
6491 i.tm.operands++;
6492
91d6fa6a
NC		 6493 i.op[dupl] = i.op[dest];
6494 i.types[dupl] = i.types[dest];
6495 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6496 }
6497
6498 if (i.tm.opcode_modifier.immext)
6499 process_immext ();
6500 }
1b54b8d7
JB		 6501 else if (i.tm.operand_types[0].bitfield.acc
6502 && i.tm.operand_types[0].bitfield.xmmword)
c0f3af97
L		 6503 {
6504 unsigned int j;
6505
9fcfb3d7
L		 6506 for (j = 1; j < i.operands; j++)
6507 {
6508 i.op[j - 1] = i.op[j];
6509 i.types[j - 1] = i.types[j];
6510
6511 /* We need to adjust fields in i.tm since they are used by
6512 build_modrm_byte. */
6513 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6514 }
6515
e2ec9d29
L		 6516 i.operands--;
6517 i.reg_operands--;
e2ec9d29
L		 6518 i.tm.operands--;
6519 }
920d2ddc
IT		 6520 else if (i.tm.opcode_modifier.implicitquadgroup)
6521 {
a477a8c4
JB		 6522 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6523
920d2ddc 6524 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
10c17abd 6525 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
a477a8c4
JB		 6526 regnum = register_number (i.op[1].regs);
6527 first_reg_in_group = regnum & ~3;
6528 last_reg_in_group = first_reg_in_group + 3;
6529 if (regnum != first_reg_in_group)
6530 as_warn (_("source register `%s%s' implicitly denotes"
6531 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6532 register_prefix, i.op[1].regs->reg_name,
6533 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6534 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6535 i.tm.name);
6536 }
e2ec9d29
L		 6537 else if (i.tm.opcode_modifier.regkludge)
6538 {
6539 /* The imul $imm, %reg instruction is converted into
6540 imul $imm, %reg, %reg, and the clr %reg instruction
6541 is converted into xor %reg, %reg. */
6542
6543 unsigned int first_reg_op;
6544
6545 if (operand_type_check (i.types[0], reg))
6546 first_reg_op = 0;
6547 else
6548 first_reg_op = 1;
6549 /* Pretend we saw the extra register operand. */
9c2799c2 6550 gas_assert (i.reg_operands == 1
7ab9ffdd 6551 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6552 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6553 i.types[first_reg_op + 1] = i.types[first_reg_op];
6554 i.operands++;
6555 i.reg_operands++;
29b0f896
AM		 6556 }
6557
40fb9820 6558 if (i.tm.opcode_modifier.shortform)
29b0f896 6559 {
40fb9820
L		 6560 if (i.types[0].bitfield.sreg2
6561 || i.types[0].bitfield.sreg3)
29b0f896 6562 {
4eed87de
AM		 6563 if (i.tm.base_opcode == POP_SEG_SHORT
6564 && i.op[0].regs->reg_num == 1)
29b0f896 6565 {
a87af027 6566 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6567 return 0;
29b0f896 6568 }
4eed87de
AM		 6569 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6570 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6571 i.rex |= REX_B;
4eed87de
AM		 6572 }
6573 else
6574 {
7ab9ffdd 6575 /* The register or float register operand is in operand
85f10a01 6576 0 or 1. */
40fb9820 6577 unsigned int op;
7ab9ffdd 6578
ca0d63fe 6579 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
7ab9ffdd
L		 6580 || operand_type_check (i.types[0], reg))
6581 op = 0;
6582 else
6583 op = 1;
4eed87de
AM		 6584 /* Register goes in low 3 bits of opcode. */
6585 i.tm.base_opcode |= i.op[op].regs->reg_num;
6586 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6587 i.rex |= REX_B;
40fb9820 6588 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6589 {
4eed87de
AM		 6590 /* Warn about some common errors, but press on regardless.
6591 The first case can be generated by gcc (<= 2.8.1). */
6592 if (i.operands == 2)
6593 {
6594 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6595 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6596 register_prefix, i.op[!intel_syntax].regs->reg_name,
6597 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6598 }
6599 else
6600 {
6601 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6602 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6603 register_prefix, i.op[0].regs->reg_name);
4eed87de 6604 }
29b0f896
AM		 6605 }
6606 }
6607 }
40fb9820 6608 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6609 {
6610 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6611 must be put into the modrm byte). Now, we make the modrm and
6612 index base bytes based on all the info we've collected. */
29b0f896
AM		 6613
6614 default_seg = build_modrm_byte ();
6615 }
8a2ed489 6616 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6617 {
6618 default_seg = &ds;
6619 }
40fb9820 6620 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6621 {
6622 /* For the string instructions that allow a segment override
6623 on one of their operands, the default segment is ds. */
6624 default_seg = &ds;
6625 }
6626
75178d9d
L		 6627 if (i.tm.base_opcode == 0x8d /* lea */
6628 && i.seg[0]
6629 && !quiet_warnings)
30123838 6630 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6631
6632 /* If a segment was explicitly specified, and the specified segment
6633 is not the default, use an opcode prefix to select it. If we
6634 never figured out what the default segment is, then default_seg
6635 will be zero at this point, and the specified segment prefix will
6636 always be used. */
29b0f896
AM		 6637 if ((i.seg[0]) && (i.seg[0] != default_seg))
6638 {
6639 if (!add_prefix (i.seg[0]->seg_prefix))
6640 return 0;
6641 }
6642 return 1;
6643}
6644
6645static const seg_entry *
e3bb37b5 6646build_modrm_byte (void)
29b0f896
AM		 6647{
6648 const seg_entry *default_seg = 0;
c0f3af97 6649 unsigned int source, dest;
8cd7925b 6650 int vex_3_sources;
c0f3af97 6651
8cd7925b 6652 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6653 if (vex_3_sources)
6654 {
91d6fa6a 6655 unsigned int nds, reg_slot;
4c2c6516 6656 expressionS *exp;
c0f3af97 6657
6b8d3588 6658 dest = i.operands - 1;
c0f3af97 6659 nds = dest - 1;
922d8de8 6660
a683cc34 6661 /* There are 2 kinds of instructions:
bed3d976
JB		 6662 1. 5 operands: 4 register operands or 3 register operands
6663 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6664 VexW0 or VexW1. The destination must be either XMM, YMM or
43234a1e 6665 ZMM register.
bed3d976 6666 2. 4 operands: 4 register operands or 3 register operands
2f1bada2 6667 plus 1 memory operand, with VexXDS. */
922d8de8 6668 gas_assert ((i.reg_operands == 4
bed3d976
JB		 6669 || (i.reg_operands == 3 && i.mem_operands == 1))
6670 && i.tm.opcode_modifier.vexvvvv == VEXXDS
dcd7e323
JB		 6671 && i.tm.opcode_modifier.vexw
6672 && i.tm.operand_types[dest].bitfield.regsimd);
a683cc34 6673
48db9223
JB		 6674 /* If VexW1 is set, the first non-immediate operand is the source and
6675 the second non-immediate one is encoded in the immediate operand. */
6676 if (i.tm.opcode_modifier.vexw == VEXW1)
6677 {
6678 source = i.imm_operands;
6679 reg_slot = i.imm_operands + 1;
6680 }
6681 else
6682 {
6683 source = i.imm_operands + 1;
6684 reg_slot = i.imm_operands;
6685 }
6686
a683cc34 6687 if (i.imm_operands == 0)
bed3d976
JB		 6688 {
6689 /* When there is no immediate operand, generate an 8bit
6690 immediate operand to encode the first operand. */
6691 exp = &im_expressions[i.imm_operands++];
6692 i.op[i.operands].imms = exp;
6693 i.types[i.operands] = imm8;
6694 i.operands++;
6695
6696 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6697 exp->X_op = O_constant;
6698 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6699 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6700 }
922d8de8 6701 else
bed3d976
JB		 6702 {
6703 unsigned int imm_slot;
a683cc34 6704
2f1bada2
JB		 6705 gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
6706
bed3d976
JB		 6707 if (i.tm.opcode_modifier.immext)
6708 {
6709 /* When ImmExt is set, the immediate byte is the last
6710 operand. */
6711 imm_slot = i.operands - 1;
6712 source--;
6713 reg_slot--;
6714 }
6715 else
6716 {
6717 imm_slot = 0;
6718
6719 /* Turn on Imm8 so that output_imm will generate it. */
6720 i.types[imm_slot].bitfield.imm8 = 1;
6721 }
6722
6723 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6724 i.op[imm_slot].imms->X_add_number
6725 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6726 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
bed3d976 6727 }
a683cc34 6728
10c17abd 6729 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
dae39acc 6730 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6731 }
6732 else
6733 source = dest = 0;
29b0f896
AM		 6734
6735 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6736 implicit registers do not count. If there are 3 register
6737 operands, it must be a instruction with VexNDS. For a
6738 instruction with VexNDD, the destination register is encoded
6739 in VEX prefix. If there are 4 register operands, it must be
6740 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6741 if (i.mem_operands == 0
6742 && ((i.reg_operands == 2
2426c15f 6743 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6744 || (i.reg_operands == 3
2426c15f 6745 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6746 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6747 {
cab737b9
L		 6748 switch (i.operands)
6749 {
6750 case 2:
6751 source = 0;
6752 break;
6753 case 3:
c81128dc
L		 6754 /* When there are 3 operands, one of them may be immediate,
6755 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6756 the first operand must be shift count register (cl) or it
6757 is an instruction with VexNDS. */
9c2799c2 6758 gas_assert (i.imm_operands == 1
7ab9ffdd 6759 || (i.imm_operands == 0
2426c15f 6760 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6761 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6762 if (operand_type_check (i.types[0], imm)
6763 || i.types[0].bitfield.shiftcount)
6764 source = 1;
6765 else
6766 source = 0;
cab737b9
L		 6767 break;
6768 case 4:
368d64cc
L		 6769 /* When there are 4 operands, the first two must be 8bit
6770 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6771 one.
6772
6773 For instructions with VexNDS, if the first operand
6774 an imm8, the source operand is the 2nd one. If the last
6775 operand is imm8, the source operand is the first one. */
9c2799c2 6776 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6777 && i.types[0].bitfield.imm8
6778 && i.types[1].bitfield.imm8)
2426c15f 6779 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6780 && i.imm_operands == 1
6781 && (i.types[0].bitfield.imm8
43234a1e
L		 6782 || i.types[i.operands - 1].bitfield.imm8
6783 || i.rounding)));
9f2670f2
L		 6784 if (i.imm_operands == 2)
6785 source = 2;
6786 else
c0f3af97
L		 6787 {
6788 if (i.types[0].bitfield.imm8)
6789 source = 1;
6790 else
6791 source = 0;
6792 }
c0f3af97
L		 6793 break;
6794 case 5:
e771e7c9 6795 if (is_evex_encoding (&i.tm))
43234a1e
L		 6796 {
6797 /* For EVEX instructions, when there are 5 operands, the
6798 first one must be immediate operand. If the second one
6799 is immediate operand, the source operand is the 3th
6800 one. If the last one is immediate operand, the source
6801 operand is the 2nd one. */
6802 gas_assert (i.imm_operands == 2
6803 && i.tm.opcode_modifier.sae
6804 && operand_type_check (i.types[0], imm));
6805 if (operand_type_check (i.types[1], imm))
6806 source = 2;
6807 else if (operand_type_check (i.types[4], imm))
6808 source = 1;
6809 else
6810 abort ();
6811 }
cab737b9
L		 6812 break;
6813 default:
6814 abort ();
6815 }
6816
c0f3af97
L		 6817 if (!vex_3_sources)
6818 {
6819 dest = source + 1;
6820
43234a1e
L		 6821 /* RC/SAE operand could be between DEST and SRC. That happens
6822 when one operand is GPR and the other one is XMM/YMM/ZMM
6823 register. */
6824 if (i.rounding && i.rounding->operand == (int) dest)
6825 dest++;
6826
2426c15f 6827 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6828 {
43234a1e 6829 /* For instructions with VexNDS, the register-only source
c5d0745b 6830 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
43234a1e
L		 6831 register. It is encoded in VEX prefix. We need to
6832 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6833
6834 i386_operand_type op;
6835 unsigned int vvvv;
6836
6837 /* Check register-only source operand when two source
6838 operands are swapped. */
6839 if (!i.tm.operand_types[source].bitfield.baseindex
6840 && i.tm.operand_types[dest].bitfield.baseindex)
6841 {
6842 vvvv = source;
6843 source = dest;
6844 }
6845 else
6846 vvvv = dest;
6847
6848 op = i.tm.operand_types[vvvv];
fa99fab2 6849 op.bitfield.regmem = 0;
c0f3af97 6850 if ((dest + 1) >= i.operands
dc821c5f
JB		 6851 || ((!op.bitfield.reg
6852 || (!op.bitfield.dword && !op.bitfield.qword))
10c17abd 6853 && !op.bitfield.regsimd
43234a1e 6854 && !operand_type_equal (&op, &regmask)))
c0f3af97 6855 abort ();
f12dc422 6856 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6857 dest++;
6858 }
6859 }
29b0f896
AM		 6860
6861 i.rm.mode = 3;
6862 /* One of the register operands will be encoded in the i.tm.reg
6863 field, the other in the combined i.tm.mode and i.tm.regmem
6864 fields. If no form of this instruction supports a memory
6865 destination operand, then we assume the source operand may
6866 sometimes be a memory operand and so we need to store the
6867 destination in the i.rm.reg field. */
40fb9820
L		 6868 if (!i.tm.operand_types[dest].bitfield.regmem
6869 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6870 {
6871 i.rm.reg = i.op[dest].regs->reg_num;
6872 i.rm.regmem = i.op[source].regs->reg_num;
6873 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6874 i.rex |= REX_R;
43234a1e
L		 6875 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6876 i.vrex |= REX_R;
29b0f896 6877 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6878 i.rex |= REX_B;
43234a1e
L		 6879 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6880 i.vrex |= REX_B;
29b0f896
AM		 6881 }
6882 else
6883 {
6884 i.rm.reg = i.op[source].regs->reg_num;
6885 i.rm.regmem = i.op[dest].regs->reg_num;
6886 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6887 i.rex |= REX_B;
43234a1e
L		 6888 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6889 i.vrex |= REX_B;
29b0f896 6890 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6891 i.rex |= REX_R;
43234a1e
L		 6892 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6893 i.vrex |= REX_R;
29b0f896 6894 }
161a04f6 6895 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6896 {
40fb9820
L		 6897 if (!i.types[0].bitfield.control
6898 && !i.types[1].bitfield.control)
c4a530c5 6899 abort ();
161a04f6 6900 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6901 add_prefix (LOCK_PREFIX_OPCODE);
6902 }
29b0f896
AM		 6903 }
6904 else
6905 { /* If it's not 2 reg operands... */
c0f3af97
L		 6906 unsigned int mem;
6907
29b0f896
AM		 6908 if (i.mem_operands)
6909 {
6910 unsigned int fake_zero_displacement = 0;
99018f42 6911 unsigned int op;
4eed87de 6912
7ab9ffdd
L		 6913 for (op = 0; op < i.operands; op++)
6914 if (operand_type_check (i.types[op], anymem))
6915 break;
7ab9ffdd 6916 gas_assert (op < i.operands);
29b0f896 6917
6c30d220
L		 6918 if (i.tm.opcode_modifier.vecsib)
6919 {
6920 if (i.index_reg->reg_num == RegEiz
6921 || i.index_reg->reg_num == RegRiz)
6922 abort ();
6923
6924 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6925 if (!i.base_reg)
6926 {
6927 i.sib.base = NO_BASE_REGISTER;
6928 i.sib.scale = i.log2_scale_factor;
6929 i.types[op].bitfield.disp8 = 0;
6930 i.types[op].bitfield.disp16 = 0;
6931 i.types[op].bitfield.disp64 = 0;
43083a50 6932 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6c30d220
L		 6933 {
6934 /* Must be 32 bit */
6935 i.types[op].bitfield.disp32 = 1;
6936 i.types[op].bitfield.disp32s = 0;
6937 }
6938 else
6939 {
6940 i.types[op].bitfield.disp32 = 0;
6941 i.types[op].bitfield.disp32s = 1;
6942 }
6943 }
6944 i.sib.index = i.index_reg->reg_num;
6945 if ((i.index_reg->reg_flags & RegRex) != 0)
6946 i.rex |= REX_X;
43234a1e
L		 6947 if ((i.index_reg->reg_flags & RegVRex) != 0)
6948 i.vrex |= REX_X;
6c30d220
L		 6949 }
6950
29b0f896
AM		 6951 default_seg = &ds;
6952
6953 if (i.base_reg == 0)
6954 {
6955 i.rm.mode = 0;
6956 if (!i.disp_operands)
9bb129e8 6957 fake_zero_displacement = 1;
29b0f896
AM		 6958 if (i.index_reg == 0)
6959 {
73053c1f
JB		 6960 i386_operand_type newdisp;
6961
6c30d220 6962 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6963 /* Operand is just <disp> */
20f0a1fc 6964 if (flag_code == CODE_64BIT)
29b0f896
AM		 6965 {
6966 /* 64bit mode overwrites the 32bit absolute
6967 addressing by RIP relative addressing and
6968 absolute addressing is encoded by one of the
6969 redundant SIB forms. */
6970 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6971 i.sib.base = NO_BASE_REGISTER;
6972 i.sib.index = NO_INDEX_REGISTER;
73053c1f 6973 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
20f0a1fc 6974 }
fc225355
L		 6975 else if ((flag_code == CODE_16BIT)
6976 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6977 {
6978 i.rm.regmem = NO_BASE_REGISTER_16;
73053c1f 6979 newdisp = disp16;
20f0a1fc
NC		 6980 }
6981 else
6982 {
6983 i.rm.regmem = NO_BASE_REGISTER;
73053c1f 6984 newdisp = disp32;
29b0f896 6985 }
73053c1f
JB		 6986 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6987 i.types[op] = operand_type_or (i.types[op], newdisp);
29b0f896 6988 }
6c30d220 6989 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6990 {
6c30d220 6991 /* !i.base_reg && i.index_reg */
db51cc60
L		 6992 if (i.index_reg->reg_num == RegEiz
6993 || i.index_reg->reg_num == RegRiz)
6994 i.sib.index = NO_INDEX_REGISTER;
6995 else
6996 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6997 i.sib.base = NO_BASE_REGISTER;
6998 i.sib.scale = i.log2_scale_factor;
6999 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 7000 i.types[op].bitfield.disp8 = 0;
7001 i.types[op].bitfield.disp16 = 0;
7002 i.types[op].bitfield.disp64 = 0;
43083a50 7003 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
40fb9820
L		 7004 {
7005 /* Must be 32 bit */
7006 i.types[op].bitfield.disp32 = 1;
7007 i.types[op].bitfield.disp32s = 0;
7008 }
29b0f896 7009 else
40fb9820
L		 7010 {
7011 i.types[op].bitfield.disp32 = 0;
7012 i.types[op].bitfield.disp32s = 1;
7013 }
29b0f896 7014 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 7015 i.rex |= REX_X;
29b0f896
AM		 7016 }
7017 }
7018 /* RIP addressing for 64bit mode. */
9a04903e
JB		 7019 else if (i.base_reg->reg_num == RegRip ||
7020 i.base_reg->reg_num == RegEip)
29b0f896 7021 {
6c30d220 7022 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 7023 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 7024 i.types[op].bitfield.disp8 = 0;
7025 i.types[op].bitfield.disp16 = 0;
7026 i.types[op].bitfield.disp32 = 0;
7027 i.types[op].bitfield.disp32s = 1;
7028 i.types[op].bitfield.disp64 = 0;
71903a11 7029 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 7030 if (! i.disp_operands)
7031 fake_zero_displacement = 1;
29b0f896 7032 }
dc821c5f 7033 else if (i.base_reg->reg_type.bitfield.word)
29b0f896 7034 {
6c30d220 7035 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 7036 switch (i.base_reg->reg_num)
7037 {
7038 case 3: /* (%bx) */
7039 if (i.index_reg == 0)
7040 i.rm.regmem = 7;
7041 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7042 i.rm.regmem = i.index_reg->reg_num - 6;
7043 break;
7044 case 5: /* (%bp) */
7045 default_seg = &ss;
7046 if (i.index_reg == 0)
7047 {
7048 i.rm.regmem = 6;
40fb9820 7049 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 7050 {
7051 /* fake (%bp) into 0(%bp) */
b5014f7a 7052 i.types[op].bitfield.disp8 = 1;
252b5132 7053 fake_zero_displacement = 1;
29b0f896
AM		 7054 }
7055 }
7056 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7057 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7058 break;
7059 default: /* (%si) -> 4 or (%di) -> 5 */
7060 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7061 }
7062 i.rm.mode = mode_from_disp_size (i.types[op]);
7063 }
7064 else /* i.base_reg and 32/64 bit mode */
7065 {
7066 if (flag_code == CODE_64BIT
40fb9820
L		 7067 && operand_type_check (i.types[op], disp))
7068 {
73053c1f
JB		 7069 i.types[op].bitfield.disp16 = 0;
7070 i.types[op].bitfield.disp64 = 0;
40fb9820 7071 if (i.prefix[ADDR_PREFIX] == 0)
73053c1f
JB		 7072 {
7073 i.types[op].bitfield.disp32 = 0;
7074 i.types[op].bitfield.disp32s = 1;
7075 }
40fb9820 7076 else
73053c1f
JB		 7077 {
7078 i.types[op].bitfield.disp32 = 1;
7079 i.types[op].bitfield.disp32s = 0;
7080 }
40fb9820 7081 }
20f0a1fc 7082
6c30d220
L		 7083 if (!i.tm.opcode_modifier.vecsib)
7084 i.rm.regmem = i.base_reg->reg_num;
29b0f896 7085 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 7086 i.rex |= REX_B;
29b0f896
AM		 7087 i.sib.base = i.base_reg->reg_num;
7088 /* x86-64 ignores REX prefix bit here to avoid decoder
7089 complications. */
848930b2
JB		 7090 if (!(i.base_reg->reg_flags & RegRex)
7091 && (i.base_reg->reg_num == EBP_REG_NUM
7092 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 7093 default_seg = &ss;
848930b2 7094 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 7095 {
848930b2 7096 fake_zero_displacement = 1;
b5014f7a 7097 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 7098 }
7099 i.sib.scale = i.log2_scale_factor;
7100 if (i.index_reg == 0)
7101 {
6c30d220 7102 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 7103 /* <disp>(%esp) becomes two byte modrm with no index
7104 register. We've already stored the code for esp
7105 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7106 Any base register besides %esp will not use the
7107 extra modrm byte. */
7108 i.sib.index = NO_INDEX_REGISTER;
29b0f896 7109 }
6c30d220 7110 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 7111 {
db51cc60
L		 7112 if (i.index_reg->reg_num == RegEiz
7113 || i.index_reg->reg_num == RegRiz)
7114 i.sib.index = NO_INDEX_REGISTER;
7115 else
7116 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 7117 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7118 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 7119 i.rex |= REX_X;
29b0f896 7120 }
67a4f2b7
AO		 7121
7122 if (i.disp_operands
7123 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7124 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7125 i.rm.mode = 0;
7126 else
a501d77e
L		 7127 {
7128 if (!fake_zero_displacement
7129 && !i.disp_operands
7130 && i.disp_encoding)
7131 {
7132 fake_zero_displacement = 1;
7133 if (i.disp_encoding == disp_encoding_8bit)
7134 i.types[op].bitfield.disp8 = 1;
7135 else
7136 i.types[op].bitfield.disp32 = 1;
7137 }
7138 i.rm.mode = mode_from_disp_size (i.types[op]);
7139 }
29b0f896 7140 }
252b5132 7141
29b0f896
AM		 7142 if (fake_zero_displacement)
7143 {
7144 /* Fakes a zero displacement assuming that i.types[op]
7145 holds the correct displacement size. */
7146 expressionS *exp;
7147
9c2799c2 7148 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 7149 exp = &disp_expressions[i.disp_operands++];
7150 i.op[op].disps = exp;
7151 exp->X_op = O_constant;
7152 exp->X_add_number = 0;
7153 exp->X_add_symbol = (symbolS *) 0;
7154 exp->X_op_symbol = (symbolS *) 0;
7155 }
c0f3af97
L		 7156
7157 mem = op;
29b0f896 7158 }
c0f3af97
L		 7159 else
7160 mem = ~0;
252b5132 7161
8c43a48b 7162 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 7163 {
7164 if (operand_type_check (i.types[0], imm))
7165 i.vex.register_specifier = NULL;
7166 else
7167 {
7168 /* VEX.vvvv encodes one of the sources when the first
7169 operand is not an immediate. */
1ef99a7b 7170 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7171 i.vex.register_specifier = i.op[0].regs;
7172 else
7173 i.vex.register_specifier = i.op[1].regs;
7174 }
7175
7176 /* Destination is a XMM register encoded in the ModRM.reg
7177 and VEX.R bit. */
7178 i.rm.reg = i.op[2].regs->reg_num;
7179 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7180 i.rex |= REX_R;
7181
7182 /* ModRM.rm and VEX.B encodes the other source. */
7183 if (!i.mem_operands)
7184 {
7185 i.rm.mode = 3;
7186
1ef99a7b 7187 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7188 i.rm.regmem = i.op[1].regs->reg_num;
7189 else
7190 i.rm.regmem = i.op[0].regs->reg_num;
7191
7192 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7193 i.rex |= REX_B;
7194 }
7195 }
2426c15f 7196 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 7197 {
7198 i.vex.register_specifier = i.op[2].regs;
7199 if (!i.mem_operands)
7200 {
7201 i.rm.mode = 3;
7202 i.rm.regmem = i.op[1].regs->reg_num;
7203 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7204 i.rex |= REX_B;
7205 }
7206 }
29b0f896
AM		 7207 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7208 (if any) based on i.tm.extension_opcode. Again, we must be
7209 careful to make sure that segment/control/debug/test/MMX
7210 registers are coded into the i.rm.reg field. */
f88c9eb0 7211 else if (i.reg_operands)
29b0f896 7212 {
99018f42 7213 unsigned int op;
7ab9ffdd
L		 7214 unsigned int vex_reg = ~0;
7215
7216 for (op = 0; op < i.operands; op++)
dc821c5f 7217 if (i.types[op].bitfield.reg
7ab9ffdd 7218 || i.types[op].bitfield.regmmx
1b54b8d7 7219 || i.types[op].bitfield.regsimd
7e8b059b 7220 || i.types[op].bitfield.regbnd
43234a1e 7221 || i.types[op].bitfield.regmask
7ab9ffdd
L		 7222 || i.types[op].bitfield.sreg2
7223 || i.types[op].bitfield.sreg3
7224 || i.types[op].bitfield.control
7225 || i.types[op].bitfield.debug
7226 || i.types[op].bitfield.test)
7227 break;
c0209578 7228
7ab9ffdd
L		 7229 if (vex_3_sources)
7230 op = dest;
2426c15f 7231 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 7232 {
7233 /* For instructions with VexNDS, the register-only
7234 source operand is encoded in VEX prefix. */
7235 gas_assert (mem != (unsigned int) ~0);
c0f3af97 7236
7ab9ffdd 7237 if (op > mem)
c0f3af97 7238 {
7ab9ffdd
L		 7239 vex_reg = op++;
7240 gas_assert (op < i.operands);
c0f3af97
L		 7241 }
7242 else
c0f3af97 7243 {
f12dc422
L		 7244 /* Check register-only source operand when two source
7245 operands are swapped. */
7246 if (!i.tm.operand_types[op].bitfield.baseindex
7247 && i.tm.operand_types[op + 1].bitfield.baseindex)
7248 {
7249 vex_reg = op;
7250 op += 2;
7251 gas_assert (mem == (vex_reg + 1)
7252 && op < i.operands);
7253 }
7254 else
7255 {
7256 vex_reg = op + 1;
7257 gas_assert (vex_reg < i.operands);
7258 }
c0f3af97 7259 }
7ab9ffdd 7260 }
2426c15f 7261 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 7262 {
f12dc422 7263 /* For instructions with VexNDD, the register destination
7ab9ffdd 7264 is encoded in VEX prefix. */
f12dc422
L		 7265 if (i.mem_operands == 0)
7266 {
7267 /* There is no memory operand. */
7268 gas_assert ((op + 2) == i.operands);
7269 vex_reg = op + 1;
7270 }
7271 else
8d63c93e 7272 {
ed438a93
JB		 7273 /* There are only 2 non-immediate operands. */
7274 gas_assert (op < i.imm_operands + 2
7275 && i.operands == i.imm_operands + 2);
7276 vex_reg = i.imm_operands + 1;
f12dc422 7277 }
7ab9ffdd
L		 7278 }
7279 else
7280 gas_assert (op < i.operands);
99018f42 7281
7ab9ffdd
L		 7282 if (vex_reg != (unsigned int) ~0)
7283 {
f12dc422 7284 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 7285
dc821c5f
JB		 7286 if ((!type->bitfield.reg
7287 || (!type->bitfield.dword && !type->bitfield.qword))
10c17abd 7288 && !type->bitfield.regsimd
43234a1e 7289 && !operand_type_equal (type, &regmask))
7ab9ffdd 7290 abort ();
f88c9eb0 7291
7ab9ffdd
L		 7292 i.vex.register_specifier = i.op[vex_reg].regs;
7293 }
7294
1b9f0c97
L		 7295 /* Don't set OP operand twice. */
7296 if (vex_reg != op)
7ab9ffdd 7297 {
1b9f0c97
L		 7298 /* If there is an extension opcode to put here, the
7299 register number must be put into the regmem field. */
7300 if (i.tm.extension_opcode != None)
7301 {
7302 i.rm.regmem = i.op[op].regs->reg_num;
7303 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7304 i.rex |= REX_B;
43234a1e
L		 7305 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7306 i.vrex |= REX_B;
1b9f0c97
L		 7307 }
7308 else
7309 {
7310 i.rm.reg = i.op[op].regs->reg_num;
7311 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7312 i.rex |= REX_R;
43234a1e
L		 7313 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7314 i.vrex |= REX_R;
1b9f0c97 7315 }
7ab9ffdd 7316 }
252b5132 7317
29b0f896
AM		 7318 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7319 must set it to 3 to indicate this is a register operand
7320 in the regmem field. */
7321 if (!i.mem_operands)
7322 i.rm.mode = 3;
7323 }
252b5132 7324
29b0f896 7325 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 7326 if (i.tm.extension_opcode != None)
29b0f896
AM		 7327 i.rm.reg = i.tm.extension_opcode;
7328 }
7329 return default_seg;
7330}
252b5132 7331
29b0f896 7332static void
e3bb37b5 7333output_branch (void)
29b0f896
AM		 7334{
7335 char *p;
f8a5c266 7336 int size;
29b0f896
AM		 7337 int code16;
7338 int prefix;
7339 relax_substateT subtype;
7340 symbolS *sym;
7341 offsetT off;
7342
f8a5c266 7343 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 7344 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 7345
7346 prefix = 0;
7347 if (i.prefix[DATA_PREFIX] != 0)
252b5132 7348 {
29b0f896
AM		 7349 prefix = 1;
7350 i.prefixes -= 1;
7351 code16 ^= CODE16;
252b5132 7352 }
29b0f896
AM		 7353 /* Pentium4 branch hints. */
7354 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7355 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 7356 {
29b0f896
AM		 7357 prefix++;
7358 i.prefixes--;
7359 }
7360 if (i.prefix[REX_PREFIX] != 0)
7361 {
7362 prefix++;
7363 i.prefixes--;
2f66722d
AM		 7364 }
7365
7e8b059b
L		 7366 /* BND prefixed jump. */
7367 if (i.prefix[BND_PREFIX] != 0)
7368 {
7369 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7370 i.prefixes -= 1;
7371 }
7372
29b0f896
AM		 7373 if (i.prefixes != 0 && !intel_syntax)
7374 as_warn (_("skipping prefixes on this instruction"));
7375
7376 /* It's always a symbol; End frag & setup for relax.
7377 Make sure there is enough room in this frag for the largest
7378 instruction we may generate in md_convert_frag. This is 2
7379 bytes for the opcode and room for the prefix and largest
7380 displacement. */
7381 frag_grow (prefix + 2 + 4);
7382 /* Prefix and 1 opcode byte go in fr_fix. */
7383 p = frag_more (prefix + 1);
7384 if (i.prefix[DATA_PREFIX] != 0)
7385 *p++ = DATA_PREFIX_OPCODE;
7386 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7387 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7388 *p++ = i.prefix[SEG_PREFIX];
7389 if (i.prefix[REX_PREFIX] != 0)
7390 *p++ = i.prefix[REX_PREFIX];
7391 *p = i.tm.base_opcode;
7392
7393 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 7394 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 7395 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 7396 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 7397 else
f8a5c266 7398 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 7399 subtype |= code16;
3e73aa7c 7400
29b0f896
AM		 7401 sym = i.op[0].disps->X_add_symbol;
7402 off = i.op[0].disps->X_add_number;
3e73aa7c 7403
29b0f896
AM		 7404 if (i.op[0].disps->X_op != O_constant
7405 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7406 {
29b0f896
AM		 7407 /* Handle complex expressions. */
7408 sym = make_expr_symbol (i.op[0].disps);
7409 off = 0;
7410 }
3e73aa7c 7411
29b0f896
AM		 7412 /* 1 possible extra opcode + 4 byte displacement go in var part.
7413 Pass reloc in fr_var. */
d258b828 7414 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7415}
3e73aa7c 7416
bd7ab16b
L		 7417#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7418/* Return TRUE iff PLT32 relocation should be used for branching to
7419 symbol S. */
7420
7421static bfd_boolean
7422need_plt32_p (symbolS *s)
7423{
7424 /* PLT32 relocation is ELF only. */
7425 if (!IS_ELF)
7426 return FALSE;
7427
7428 /* Since there is no need to prepare for PLT branch on x86-64, we
7429 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7430 be used as a marker for 32-bit PC-relative branches. */
7431 if (!object_64bit)
7432 return FALSE;
7433
7434 /* Weak or undefined symbol need PLT32 relocation. */
7435 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7436 return TRUE;
7437
7438 /* Non-global symbol doesn't need PLT32 relocation. */
7439 if (! S_IS_EXTERNAL (s))
7440 return FALSE;
7441
7442 /* Other global symbols need PLT32 relocation. NB: Symbol with
7443 non-default visibilities are treated as normal global symbol
7444 so that PLT32 relocation can be used as a marker for 32-bit
7445 PC-relative branches. It is useful for linker relaxation. */
7446 return TRUE;
7447}
7448#endif
7449
29b0f896 7450static void
e3bb37b5 7451output_jump (void)
29b0f896
AM		 7452{
7453 char *p;
7454 int size;
3e02c1cc 7455 fixS *fixP;
bd7ab16b 7456 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
29b0f896 7457
40fb9820 7458 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7459 {
7460 /* This is a loop or jecxz type instruction. */
7461 size = 1;
7462 if (i.prefix[ADDR_PREFIX] != 0)
7463 {
7464 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7465 i.prefixes -= 1;
7466 }
7467 /* Pentium4 branch hints. */
7468 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7469 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7470 {
7471 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7472 i.prefixes--;
3e73aa7c
JH		 7473 }
7474 }
29b0f896
AM		 7475 else
7476 {
7477 int code16;
3e73aa7c 7478
29b0f896
AM		 7479 code16 = 0;
7480 if (flag_code == CODE_16BIT)
7481 code16 = CODE16;
3e73aa7c 7482
29b0f896
AM		 7483 if (i.prefix[DATA_PREFIX] != 0)
7484 {
7485 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7486 i.prefixes -= 1;
7487 code16 ^= CODE16;
7488 }
252b5132 7489
29b0f896
AM		 7490 size = 4;
7491 if (code16)
7492 size = 2;
7493 }
9fcc94b6 7494
29b0f896
AM		 7495 if (i.prefix[REX_PREFIX] != 0)
7496 {
7497 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7498 i.prefixes -= 1;
7499 }
252b5132 7500
7e8b059b
L		 7501 /* BND prefixed jump. */
7502 if (i.prefix[BND_PREFIX] != 0)
7503 {
7504 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7505 i.prefixes -= 1;
7506 }
7507
29b0f896
AM		 7508 if (i.prefixes != 0 && !intel_syntax)
7509 as_warn (_("skipping prefixes on this instruction"));
e0890092 7510
42164a71
L		 7511 p = frag_more (i.tm.opcode_length + size);
7512 switch (i.tm.opcode_length)
7513 {
7514 case 2:
7515 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7516 /* Fall through. */
42164a71
L		 7517 case 1:
7518 *p++ = i.tm.base_opcode;
7519 break;
7520 default:
7521 abort ();
7522 }
e0890092 7523
bd7ab16b
L		 7524#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7525 if (size == 4
7526 && jump_reloc == NO_RELOC
7527 && need_plt32_p (i.op[0].disps->X_add_symbol))
7528 jump_reloc = BFD_RELOC_X86_64_PLT32;
7529#endif
7530
7531 jump_reloc = reloc (size, 1, 1, jump_reloc);
7532
3e02c1cc 7533 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
bd7ab16b 7534 i.op[0].disps, 1, jump_reloc);
3e02c1cc
AM		 7535
7536 /* All jumps handled here are signed, but don't use a signed limit
7537 check for 32 and 16 bit jumps as we want to allow wrap around at
7538 4G and 64k respectively. */
7539 if (size == 1)
7540 fixP->fx_signed = 1;
29b0f896 7541}
e0890092 7542
29b0f896 7543static void
e3bb37b5 7544output_interseg_jump (void)
29b0f896
AM		 7545{
7546 char *p;
7547 int size;
7548 int prefix;
7549 int code16;
252b5132 7550
29b0f896
AM		 7551 code16 = 0;
7552 if (flag_code == CODE_16BIT)
7553 code16 = CODE16;
a217f122 7554
29b0f896
AM		 7555 prefix = 0;
7556 if (i.prefix[DATA_PREFIX] != 0)
7557 {
7558 prefix = 1;
7559 i.prefixes -= 1;
7560 code16 ^= CODE16;
7561 }
7562 if (i.prefix[REX_PREFIX] != 0)
7563 {
7564 prefix++;
7565 i.prefixes -= 1;
7566 }
252b5132 7567
29b0f896
AM		 7568 size = 4;
7569 if (code16)
7570 size = 2;
252b5132 7571
29b0f896
AM		 7572 if (i.prefixes != 0 && !intel_syntax)
7573 as_warn (_("skipping prefixes on this instruction"));
252b5132 7574
29b0f896
AM		 7575 /* 1 opcode; 2 segment; offset */
7576 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7577
29b0f896
AM		 7578 if (i.prefix[DATA_PREFIX] != 0)
7579 *p++ = DATA_PREFIX_OPCODE;
252b5132 7580
29b0f896
AM		 7581 if (i.prefix[REX_PREFIX] != 0)
7582 *p++ = i.prefix[REX_PREFIX];
252b5132 7583
29b0f896
AM		 7584 *p++ = i.tm.base_opcode;
7585 if (i.op[1].imms->X_op == O_constant)
7586 {
7587 offsetT n = i.op[1].imms->X_add_number;
252b5132 7588
29b0f896
AM		 7589 if (size == 2
7590 && !fits_in_unsigned_word (n)
7591 && !fits_in_signed_word (n))
7592 {
7593 as_bad (_("16-bit jump out of range"));
7594 return;
7595 }
7596 md_number_to_chars (p, n, size);
7597 }
7598 else
7599 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7600 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7601 if (i.op[0].imms->X_op != O_constant)
7602 as_bad (_("can't handle non absolute segment in `%s'"),
7603 i.tm.name);
7604 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7605}
a217f122 7606
29b0f896 7607static void
e3bb37b5 7608output_insn (void)
29b0f896 7609{
2bbd9c25
JJ		 7610 fragS *insn_start_frag;
7611 offsetT insn_start_off;
7612
29b0f896
AM		 7613 /* Tie dwarf2 debug info to the address at the start of the insn.
7614 We can't do this after the insn has been output as the current
7615 frag may have been closed off. eg. by frag_var. */
7616 dwarf2_emit_insn (0);
7617
2bbd9c25
JJ		 7618 insn_start_frag = frag_now;
7619 insn_start_off = frag_now_fix ();
7620
29b0f896 7621 /* Output jumps. */
40fb9820 7622 if (i.tm.opcode_modifier.jump)
29b0f896 7623 output_branch ();
40fb9820
L		 7624 else if (i.tm.opcode_modifier.jumpbyte
7625 || i.tm.opcode_modifier.jumpdword)
29b0f896 7626 output_jump ();
40fb9820 7627 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7628 output_interseg_jump ();
7629 else
7630 {
7631 /* Output normal instructions here. */
7632 char *p;
7633 unsigned char *q;
47465058 7634 unsigned int j;
331d2d0d 7635 unsigned int prefix;
4dffcebc 7636
e4e00185
AS		 7637 if (avoid_fence
7638 && i.tm.base_opcode == 0xfae
7639 && i.operands == 1
7640 && i.imm_operands == 1
7641 && (i.op[0].imms->X_add_number == 0xe8
7642 || i.op[0].imms->X_add_number == 0xf0
7643 || i.op[0].imms->X_add_number == 0xf8))
7644 {
7645 /* Encode lfence, mfence, and sfence as
7646 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7647 offsetT val = 0x240483f0ULL;
7648 p = frag_more (5);
7649 md_number_to_chars (p, val, 5);
7650 return;
7651 }
7652
d022bddd
IT		 7653 /* Some processors fail on LOCK prefix. This options makes
7654 assembler ignore LOCK prefix and serves as a workaround. */
7655 if (omit_lock_prefix)
7656 {
7657 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7658 return;
7659 i.prefix[LOCK_PREFIX] = 0;
7660 }
7661
43234a1e
L		 7662 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7663 don't need the explicit prefix. */
7664 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7665 {
c0f3af97 7666 switch (i.tm.opcode_length)
bc4bd9ab 7667 {
c0f3af97
L		 7668 case 3:
7669 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7670 {
c0f3af97
L		 7671 prefix = (i.tm.base_opcode >> 24) & 0xff;
7672 goto check_prefix;
7673 }
7674 break;
7675 case 2:
7676 if ((i.tm.base_opcode & 0xff0000) != 0)
7677 {
7678 prefix = (i.tm.base_opcode >> 16) & 0xff;
7679 if (i.tm.cpu_flags.bitfield.cpupadlock)
7680 {
4dffcebc 7681check_prefix:
c0f3af97 7682 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7683 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7684 != REPE_PREFIX_OPCODE))
7685 add_prefix (prefix);
7686 }
7687 else
4dffcebc
L		 7688 add_prefix (prefix);
7689 }
c0f3af97
L		 7690 break;
7691 case 1:
7692 break;
390c91cf
L		 7693 case 0:
7694 /* Check for pseudo prefixes. */
7695 as_bad_where (insn_start_frag->fr_file,
7696 insn_start_frag->fr_line,
7697 _("pseudo prefix without instruction"));
7698 return;
c0f3af97
L		 7699 default:
7700 abort ();
bc4bd9ab 7701 }
c0f3af97 7702
6d19a37a 7703#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7704 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7705 R_X86_64_GOTTPOFF relocation so that linker can safely
7706 perform IE->LE optimization. */
7707 if (x86_elf_abi == X86_64_X32_ABI
7708 && i.operands == 2
7709 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7710 && i.prefix[REX_PREFIX] == 0)
7711 add_prefix (REX_OPCODE);
6d19a37a 7712#endif
cf61b747 7713
c0f3af97
L		 7714 /* The prefix bytes. */
7715 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7716 if (*q)
7717 FRAG_APPEND_1_CHAR (*q);
0f10071e 7718 }
ae5c1c7b 7719 else
c0f3af97
L		 7720 {
7721 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7722 if (*q)
7723 switch (j)
7724 {
7725 case REX_PREFIX:
7726 /* REX byte is encoded in VEX prefix. */
7727 break;
7728 case SEG_PREFIX:
7729 case ADDR_PREFIX:
7730 FRAG_APPEND_1_CHAR (*q);
7731 break;
7732 default:
7733 /* There should be no other prefixes for instructions
7734 with VEX prefix. */
7735 abort ();
7736 }
7737
43234a1e
L		 7738 /* For EVEX instructions i.vrex should become 0 after
7739 build_evex_prefix. For VEX instructions upper 16 registers
7740 aren't available, so VREX should be 0. */
7741 if (i.vrex)
7742 abort ();
c0f3af97
L		 7743 /* Now the VEX prefix. */
7744 p = frag_more (i.vex.length);
7745 for (j = 0; j < i.vex.length; j++)
7746 p[j] = i.vex.bytes[j];
7747 }
252b5132 7748
29b0f896 7749 /* Now the opcode; be careful about word order here! */
4dffcebc 7750 if (i.tm.opcode_length == 1)
29b0f896
AM		 7751 {
7752 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7753 }
7754 else
7755 {
4dffcebc 7756 switch (i.tm.opcode_length)
331d2d0d 7757 {
43234a1e
L		 7758 case 4:
7759 p = frag_more (4);
7760 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7761 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7762 break;
4dffcebc 7763 case 3:
331d2d0d
L		 7764 p = frag_more (3);
7765 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7766 break;
7767 case 2:
7768 p = frag_more (2);
7769 break;
7770 default:
7771 abort ();
7772 break;
331d2d0d 7773 }
0f10071e 7774
29b0f896
AM		 7775 /* Put out high byte first: can't use md_number_to_chars! */
7776 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7777 *p = i.tm.base_opcode & 0xff;
7778 }
3e73aa7c 7779
29b0f896 7780 /* Now the modrm byte and sib byte (if present). */
40fb9820 7781 if (i.tm.opcode_modifier.modrm)
29b0f896 7782 {
4a3523fa
L		 7783 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7784 | i.rm.reg << 3
7785 | i.rm.mode << 6));
29b0f896
AM		 7786 /* If i.rm.regmem == ESP (4)
7787 && i.rm.mode != (Register mode)
7788 && not 16 bit
7789 ==> need second modrm byte. */
7790 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7791 && i.rm.mode != 3
dc821c5f 7792 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
4a3523fa
L		 7793 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7794 | i.sib.index << 3
7795 | i.sib.scale << 6));
29b0f896 7796 }
3e73aa7c 7797
29b0f896 7798 if (i.disp_operands)
2bbd9c25 7799 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7800
29b0f896 7801 if (i.imm_operands)
2bbd9c25 7802 output_imm (insn_start_frag, insn_start_off);
29b0f896 7803 }
252b5132 7804
29b0f896
AM		 7805#ifdef DEBUG386
7806 if (flag_debug)
7807 {
7b81dfbb 7808 pi ("" /*line*/, &i);
29b0f896
AM		 7809 }
7810#endif /* DEBUG386 */
7811}
252b5132 7812
e205caa7
L		 7813/* Return the size of the displacement operand N. */
7814
7815static int
7816disp_size (unsigned int n)
7817{
7818 int size = 4;
43234a1e 7819
b5014f7a 7820 if (i.types[n].bitfield.disp64)
40fb9820
L		 7821 size = 8;
7822 else if (i.types[n].bitfield.disp8)
7823 size = 1;
7824 else if (i.types[n].bitfield.disp16)
7825 size = 2;
e205caa7
L		 7826 return size;
7827}
7828
7829/* Return the size of the immediate operand N. */
7830
7831static int
7832imm_size (unsigned int n)
7833{
7834 int size = 4;
40fb9820
L		 7835 if (i.types[n].bitfield.imm64)
7836 size = 8;
7837 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7838 size = 1;
7839 else if (i.types[n].bitfield.imm16)
7840 size = 2;
e205caa7
L		 7841 return size;
7842}
7843
29b0f896 7844static void
64e74474 7845output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7846{
7847 char *p;
7848 unsigned int n;
252b5132 7849
29b0f896
AM		 7850 for (n = 0; n < i.operands; n++)
7851 {
b5014f7a 7852 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 7853 {
7854 if (i.op[n].disps->X_op == O_constant)
7855 {
e205caa7 7856 int size = disp_size (n);
43234a1e 7857 offsetT val = i.op[n].disps->X_add_number;
252b5132 7858
b5014f7a 7859 val = offset_in_range (val >> i.memshift, size);
29b0f896
AM		 7860 p = frag_more (size);
7861 md_number_to_chars (p, val, size);
7862 }
7863 else
7864 {
f86103b7 7865 enum bfd_reloc_code_real reloc_type;
e205caa7 7866 int size = disp_size (n);
40fb9820 7867 int sign = i.types[n].bitfield.disp32s;
29b0f896 7868 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7869 fixS *fixP;
29b0f896 7870
e205caa7 7871 /* We can't have 8 bit displacement here. */
9c2799c2 7872 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7873
29b0f896
AM		 7874 /* The PC relative address is computed relative
7875 to the instruction boundary, so in case immediate
7876 fields follows, we need to adjust the value. */
7877 if (pcrel && i.imm_operands)
7878 {
29b0f896 7879 unsigned int n1;
e205caa7 7880 int sz = 0;
252b5132 7881
29b0f896 7882 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7883 if (operand_type_check (i.types[n1], imm))
252b5132 7884 {
e205caa7
L		 7885 /* Only one immediate is allowed for PC
7886 relative address. */
9c2799c2 7887 gas_assert (sz == 0);
e205caa7
L		 7888 sz = imm_size (n1);
7889 i.op[n].disps->X_add_number -= sz;
252b5132 7890 }
29b0f896 7891 /* We should find the immediate. */
9c2799c2 7892 gas_assert (sz != 0);
29b0f896 7893 }
520dc8e8 7894
29b0f896 7895 p = frag_more (size);
d258b828 7896 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7897 if (GOT_symbol
2bbd9c25 7898 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7899 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7900 || reloc_type == BFD_RELOC_X86_64_32S
7901 || (reloc_type == BFD_RELOC_64
7902 && object_64bit))
d6ab8113
JB		 7903 && (i.op[n].disps->X_op == O_symbol
7904 || (i.op[n].disps->X_op == O_add
7905 && ((symbol_get_value_expression
7906 (i.op[n].disps->X_op_symbol)->X_op)
7907 == O_subtract))))
7908 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7909 {
7910 offsetT add;
7911
7912 if (insn_start_frag == frag_now)
7913 add = (p - frag_now->fr_literal) - insn_start_off;
7914 else
7915 {
7916 fragS *fr;
7917
7918 add = insn_start_frag->fr_fix - insn_start_off;
7919 for (fr = insn_start_frag->fr_next;
7920 fr && fr != frag_now; fr = fr->fr_next)
7921 add += fr->fr_fix;
7922 add += p - frag_now->fr_literal;
7923 }
7924
4fa24527 7925 if (!object_64bit)
7b81dfbb
AJ		 7926 {
7927 reloc_type = BFD_RELOC_386_GOTPC;
7928 i.op[n].imms->X_add_number += add;
7929 }
7930 else if (reloc_type == BFD_RELOC_64)
7931 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7932 else
7b81dfbb
AJ		 7933 /* Don't do the adjustment for x86-64, as there
7934 the pcrel addressing is relative to the _next_
7935 insn, and that is taken care of in other code. */
d6ab8113 7936 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7937 }
02a86693
L		 7938 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7939 size, i.op[n].disps, pcrel,
7940 reloc_type);
7941 /* Check for "call/jmp *mem", "mov mem, %reg",
7942 "test %reg, mem" and "binop mem, %reg" where binop
7943 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7944 instructions. Always generate R_386_GOT32X for
7945 "sym*GOT" operand in 32-bit mode. */
7946 if ((generate_relax_relocations
7947 || (!object_64bit
7948 && i.rm.mode == 0
7949 && i.rm.regmem == 5))
7950 && (i.rm.mode == 2
7951 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7952 && ((i.operands == 1
7953 && i.tm.base_opcode == 0xff
7954 && (i.rm.reg == 2 || i.rm.reg == 4))
7955 || (i.operands == 2
7956 && (i.tm.base_opcode == 0x8b
7957 || i.tm.base_opcode == 0x85
7958 || (i.tm.base_opcode & 0xc7) == 0x03))))
7959 {
7960 if (object_64bit)
7961 {
7962 fixP->fx_tcbit = i.rex != 0;
7963 if (i.base_reg
7964 && (i.base_reg->reg_num == RegRip
7965 || i.base_reg->reg_num == RegEip))
7966 fixP->fx_tcbit2 = 1;
7967 }
7968 else
7969 fixP->fx_tcbit2 = 1;
7970 }
29b0f896
AM		 7971 }
7972 }
7973 }
7974}
252b5132 7975
29b0f896 7976static void
64e74474 7977output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7978{
7979 char *p;
7980 unsigned int n;
252b5132 7981
29b0f896
AM		 7982 for (n = 0; n < i.operands; n++)
7983 {
43234a1e
L		 7984 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7985 if (i.rounding && (int) n == i.rounding->operand)
7986 continue;
7987
40fb9820 7988 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7989 {
7990 if (i.op[n].imms->X_op == O_constant)
7991 {
e205caa7 7992 int size = imm_size (n);
29b0f896 7993 offsetT val;
b4cac588 7994
29b0f896
AM		 7995 val = offset_in_range (i.op[n].imms->X_add_number,
7996 size);
7997 p = frag_more (size);
7998 md_number_to_chars (p, val, size);
7999 }
8000 else
8001 {
8002 /* Not absolute_section.
8003 Need a 32-bit fixup (don't support 8bit
8004 non-absolute imms). Try to support other
8005 sizes ... */
f86103b7 8006 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 8007 int size = imm_size (n);
8008 int sign;
29b0f896 8009
40fb9820 8010 if (i.types[n].bitfield.imm32s
a7d61044 8011 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 8012 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 8013 sign = 1;
e205caa7
L		 8014 else
8015 sign = 0;
520dc8e8 8016
29b0f896 8017 p = frag_more (size);
d258b828 8018 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 8019
2bbd9c25
JJ		 8020 /* This is tough to explain. We end up with this one if we
8021 * have operands that look like
8022 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8023 * obtain the absolute address of the GOT, and it is strongly
8024 * preferable from a performance point of view to avoid using
8025 * a runtime relocation for this. The actual sequence of
8026 * instructions often look something like:
8027 *
8028 * call .L66
8029 * .L66:
8030 * popl %ebx
8031 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8032 *
8033 * The call and pop essentially return the absolute address
8034 * of the label .L66 and store it in %ebx. The linker itself
8035 * will ultimately change the first operand of the addl so
8036 * that %ebx points to the GOT, but to keep things simple, the
8037 * .o file must have this operand set so that it generates not
8038 * the absolute address of .L66, but the absolute address of
8039 * itself. This allows the linker itself simply treat a GOTPC
8040 * relocation as asking for a pcrel offset to the GOT to be
8041 * added in, and the addend of the relocation is stored in the
8042 * operand field for the instruction itself.
8043 *
8044 * Our job here is to fix the operand so that it would add
8045 * the correct offset so that %ebx would point to itself. The
8046 * thing that is tricky is that .-.L66 will point to the
8047 * beginning of the instruction, so we need to further modify
8048 * the operand so that it will point to itself. There are
8049 * other cases where you have something like:
8050 *
8051 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8052 *
8053 * and here no correction would be required. Internally in
8054 * the assembler we treat operands of this form as not being
8055 * pcrel since the '.' is explicitly mentioned, and I wonder
8056 * whether it would simplify matters to do it this way. Who
8057 * knows. In earlier versions of the PIC patches, the
8058 * pcrel_adjust field was used to store the correction, but
8059 * since the expression is not pcrel, I felt it would be
8060 * confusing to do it this way. */
8061
d6ab8113 8062 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 8063 || reloc_type == BFD_RELOC_X86_64_32S
8064 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 8065 && GOT_symbol
8066 && GOT_symbol == i.op[n].imms->X_add_symbol
8067 && (i.op[n].imms->X_op == O_symbol
8068 || (i.op[n].imms->X_op == O_add
8069 && ((symbol_get_value_expression
8070 (i.op[n].imms->X_op_symbol)->X_op)
8071 == O_subtract))))
8072 {
2bbd9c25
JJ		 8073 offsetT add;
8074
8075 if (insn_start_frag == frag_now)
8076 add = (p - frag_now->fr_literal) - insn_start_off;
8077 else
8078 {
8079 fragS *fr;
8080
8081 add = insn_start_frag->fr_fix - insn_start_off;
8082 for (fr = insn_start_frag->fr_next;
8083 fr && fr != frag_now; fr = fr->fr_next)
8084 add += fr->fr_fix;
8085 add += p - frag_now->fr_literal;
8086 }
8087
4fa24527 8088 if (!object_64bit)
d6ab8113 8089 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 8090 else if (size == 4)
d6ab8113 8091 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 8092 else if (size == 8)
8093 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 8094 i.op[n].imms->X_add_number += add;
29b0f896 8095 }
29b0f896
AM		 8096 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8097 i.op[n].imms, 0, reloc_type);
8098 }
8099 }
8100 }
252b5132
RH		 8101}
8102\f
d182319b
JB		 8103/* x86_cons_fix_new is called via the expression parsing code when a
8104 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 8105static int cons_sign = -1;
8106
8107void
e3bb37b5 8108x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 8109 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 8110{
d258b828 8111 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 8112
8113#ifdef TE_PE
8114 if (exp->X_op == O_secrel)
8115 {
8116 exp->X_op = O_symbol;
8117 r = BFD_RELOC_32_SECREL;
8118 }
8119#endif
8120
8121 fix_new_exp (frag, off, len, exp, 0, r);
8122}
8123
357d1bd8
L		 8124/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8125 purpose of the `.dc.a' internal pseudo-op. */
8126
8127int
8128x86_address_bytes (void)
8129{
8130 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8131 return 4;
8132 return stdoutput->arch_info->bits_per_address / 8;
8133}
8134
d382c579
TG		 8135#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8136 || defined (LEX_AT)
d258b828 8137# define lex_got(reloc, adjust, types) NULL
718ddfc0 8138#else
f3c180ae
AM		 8139/* Parse operands of the form
8140 <symbol>@GOTOFF+<nnn>
8141 and similar .plt or .got references.
8142
8143 If we find one, set up the correct relocation in RELOC and copy the
8144 input string, minus the `@GOTOFF' into a malloc'd buffer for
8145 parsing by the calling routine. Return this buffer, and if ADJUST
8146 is non-null set it to the length of the string we removed from the
8147 input line. Otherwise return NULL. */
8148static char *
91d6fa6a 8149lex_got (enum bfd_reloc_code_real *rel,
64e74474 8150 int *adjust,
d258b828 8151 i386_operand_type *types)
f3c180ae 8152{
7b81dfbb
AJ		 8153 /* Some of the relocations depend on the size of what field is to
8154 be relocated. But in our callers i386_immediate and i386_displacement
8155 we don't yet know the operand size (this will be set by insn
8156 matching). Hence we record the word32 relocation here,
8157 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 8158 static const struct {
8159 const char *str;
cff8d58a 8160 int len;
4fa24527 8161 const enum bfd_reloc_code_real rel[2];
40fb9820 8162 const i386_operand_type types64;
f3c180ae 8163 } gotrel[] = {
8ce3d284 8164#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 8165 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8166 BFD_RELOC_SIZE32 },
8167 OPERAND_TYPE_IMM32_64 },
8ce3d284 8168#endif
cff8d58a
L		 8169 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8170 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 8171 OPERAND_TYPE_IMM64 },
cff8d58a
L		 8172 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8173 BFD_RELOC_X86_64_PLT32 },
40fb9820 8174 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8175 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8176 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 8177 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8178 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8179 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 8180 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8181 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8182 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 8183 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8184 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8185 BFD_RELOC_X86_64_TLSGD },
40fb9820 8186 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8187 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8188 _dummy_first_bfd_reloc_code_real },
40fb9820 8189 OPERAND_TYPE_NONE },
cff8d58a
L		 8190 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8191 BFD_RELOC_X86_64_TLSLD },
40fb9820 8192 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8193 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8194 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 8195 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8196 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8197 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 8198 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8199 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8200 _dummy_first_bfd_reloc_code_real },
40fb9820 8201 OPERAND_TYPE_NONE },
cff8d58a
L		 8202 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8203 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 8204 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8205 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8206 _dummy_first_bfd_reloc_code_real },
40fb9820 8207 OPERAND_TYPE_NONE },
cff8d58a
L		 8208 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8209 _dummy_first_bfd_reloc_code_real },
40fb9820 8210 OPERAND_TYPE_NONE },
cff8d58a
L		 8211 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8212 BFD_RELOC_X86_64_GOT32 },
40fb9820 8213 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 8214 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8215 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 8216 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8217 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8218 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 8219 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 8220 };
8221 char *cp;
8222 unsigned int j;
8223
d382c579 8224#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 8225 if (!IS_ELF)
8226 return NULL;
d382c579 8227#endif
718ddfc0 8228
f3c180ae 8229 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 8230 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 8231 return NULL;
8232
47465058 8233 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 8234 {
cff8d58a 8235 int len = gotrel[j].len;
28f81592 8236 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 8237 {
4fa24527 8238 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 8239 {
28f81592
AM		 8240 int first, second;
8241 char *tmpbuf, *past_reloc;
f3c180ae 8242
91d6fa6a 8243 *rel = gotrel[j].rel[object_64bit];
f3c180ae 8244
3956db08
JB		 8245 if (types)
8246 {
8247 if (flag_code != CODE_64BIT)
40fb9820
L		 8248 {
8249 types->bitfield.imm32 = 1;
8250 types->bitfield.disp32 = 1;
8251 }
3956db08
JB		 8252 else
8253 *types = gotrel[j].types64;
8254 }
8255
8fd4256d 8256 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 8257 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8258
28f81592 8259 /* The length of the first part of our input line. */
f3c180ae 8260 first = cp - input_line_pointer;
28f81592
AM		 8261
8262 /* The second part goes from after the reloc token until
67c11a9b 8263 (and including) an end_of_line char or comma. */
28f81592 8264 past_reloc = cp + 1 + len;
67c11a9b
AM		 8265 cp = past_reloc;
8266 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8267 ++cp;
8268 second = cp + 1 - past_reloc;
28f81592
AM		 8269
8270 /* Allocate and copy string. The trailing NUL shouldn't
8271 be necessary, but be safe. */
add39d23 8272 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 8273 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 8274 if (second != 0 && *past_reloc != ' ')
8275 /* Replace the relocation token with ' ', so that
8276 errors like foo@GOTOFF1 will be detected. */
8277 tmpbuf[first++] = ' ';
af89796a
L		 8278 else
8279 /* Increment length by 1 if the relocation token is
8280 removed. */
8281 len++;
8282 if (adjust)
8283 *adjust = len;
0787a12d
AM		 8284 memcpy (tmpbuf + first, past_reloc, second);
8285 tmpbuf[first + second] = '\0';
f3c180ae
AM		 8286 return tmpbuf;
8287 }
8288
4fa24527
JB		 8289 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8290 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 8291 return NULL;
8292 }
8293 }
8294
8295 /* Might be a symbol version string. Don't as_bad here. */
8296 return NULL;
8297}
4e4f7c87 8298#endif
f3c180ae 8299
a988325c
NC		 8300#ifdef TE_PE
8301#ifdef lex_got
8302#undef lex_got
8303#endif
8304/* Parse operands of the form
8305 <symbol>@SECREL32+<nnn>
8306
8307 If we find one, set up the correct relocation in RELOC and copy the
8308 input string, minus the `@SECREL32' into a malloc'd buffer for
8309 parsing by the calling routine. Return this buffer, and if ADJUST
8310 is non-null set it to the length of the string we removed from the
34bca508
L		 8311 input line. Otherwise return NULL.
8312
a988325c
NC		 8313 This function is copied from the ELF version above adjusted for PE targets. */
8314
8315static char *
8316lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8317 int *adjust ATTRIBUTE_UNUSED,
d258b828 8318 i386_operand_type *types)
a988325c
NC		 8319{
8320 static const struct
8321 {
8322 const char *str;
8323 int len;
8324 const enum bfd_reloc_code_real rel[2];
8325 const i386_operand_type types64;
8326 }
8327 gotrel[] =
8328 {
8329 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8330 BFD_RELOC_32_SECREL },
8331 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8332 };
8333
8334 char *cp;
8335 unsigned j;
8336
8337 for (cp = input_line_pointer; *cp != '@'; cp++)
8338 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8339 return NULL;
8340
8341 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8342 {
8343 int len = gotrel[j].len;
8344
8345 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8346 {
8347 if (gotrel[j].rel[object_64bit] != 0)
8348 {
8349 int first, second;
8350 char *tmpbuf, *past_reloc;
8351
8352 *rel = gotrel[j].rel[object_64bit];
8353 if (adjust)
8354 *adjust = len;
8355
8356 if (types)
8357 {
8358 if (flag_code != CODE_64BIT)
8359 {
8360 types->bitfield.imm32 = 1;
8361 types->bitfield.disp32 = 1;
8362 }
8363 else
8364 *types = gotrel[j].types64;
8365 }
8366
8367 /* The length of the first part of our input line. */
8368 first = cp - input_line_pointer;
8369
8370 /* The second part goes from after the reloc token until
8371 (and including) an end_of_line char or comma. */
8372 past_reloc = cp + 1 + len;
8373 cp = past_reloc;
8374 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8375 ++cp;
8376 second = cp + 1 - past_reloc;
8377
8378 /* Allocate and copy string. The trailing NUL shouldn't
8379 be necessary, but be safe. */
add39d23 8380 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 8381 memcpy (tmpbuf, input_line_pointer, first);
8382 if (second != 0 && *past_reloc != ' ')
8383 /* Replace the relocation token with ' ', so that
8384 errors like foo@SECLREL321 will be detected. */
8385 tmpbuf[first++] = ' ';
8386 memcpy (tmpbuf + first, past_reloc, second);
8387 tmpbuf[first + second] = '\0';
8388 return tmpbuf;
8389 }
8390
8391 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8392 gotrel[j].str, 1 << (5 + object_64bit));
8393 return NULL;
8394 }
8395 }
8396
8397 /* Might be a symbol version string. Don't as_bad here. */
8398 return NULL;
8399}
8400
8401#endif /* TE_PE */
8402
62ebcb5c 8403bfd_reloc_code_real_type
e3bb37b5 8404x86_cons (expressionS *exp, int size)
f3c180ae 8405{
62ebcb5c
AM		 8406 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8407
ee86248c
JB		 8408 intel_syntax = -intel_syntax;
8409
3c7b9c2c 8410 exp->X_md = 0;
4fa24527 8411 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 8412 {
8413 /* Handle @GOTOFF and the like in an expression. */
8414 char *save;
8415 char *gotfree_input_line;
4a57f2cf 8416 int adjust = 0;
f3c180ae
AM		 8417
8418 save = input_line_pointer;
d258b828 8419 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 8420 if (gotfree_input_line)
8421 input_line_pointer = gotfree_input_line;
8422
8423 expression (exp);
8424
8425 if (gotfree_input_line)
8426 {
8427 /* expression () has merrily parsed up to the end of line,
8428 or a comma - in the wrong buffer. Transfer how far
8429 input_line_pointer has moved to the right buffer. */
8430 input_line_pointer = (save
8431 + (input_line_pointer - gotfree_input_line)
8432 + adjust);
8433 free (gotfree_input_line);
3992d3b7
AM		 8434 if (exp->X_op == O_constant
8435 || exp->X_op == O_absent
8436 || exp->X_op == O_illegal
0398aac5 8437 || exp->X_op == O_register
3992d3b7
AM		 8438 || exp->X_op == O_big)
8439 {
8440 char c = *input_line_pointer;
8441 *input_line_pointer = 0;
8442 as_bad (_("missing or invalid expression `%s'"), save);
8443 *input_line_pointer = c;
8444 }
f3c180ae
AM		 8445 }
8446 }
8447 else
8448 expression (exp);
ee86248c
JB		 8449
8450 intel_syntax = -intel_syntax;
8451
8452 if (intel_syntax)
8453 i386_intel_simplify (exp);
62ebcb5c
AM		 8454
8455 return got_reloc;
f3c180ae 8456}
f3c180ae 8457
9f32dd5b
L		 8458static void
8459signed_cons (int size)
6482c264 8460{
d182319b
JB		 8461 if (flag_code == CODE_64BIT)
8462 cons_sign = 1;
8463 cons (size);
8464 cons_sign = -1;
6482c264
NC		 8465}
8466
d182319b 8467#ifdef TE_PE
6482c264 8468static void
7016a5d5 8469pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 8470{
8471 expressionS exp;
8472
8473 do
8474 {
8475 expression (&exp);
8476 if (exp.X_op == O_symbol)
8477 exp.X_op = O_secrel;
8478
8479 emit_expr (&exp, 4);
8480 }
8481 while (*input_line_pointer++ == ',');
8482
8483 input_line_pointer--;
8484 demand_empty_rest_of_line ();
8485}
6482c264
NC		 8486#endif
8487
43234a1e
L		 8488/* Handle Vector operations. */
8489
8490static char *
8491check_VecOperations (char *op_string, char *op_end)
8492{
8493 const reg_entry *mask;
8494 const char *saved;
8495 char *end_op;
8496
8497 while (*op_string
8498 && (op_end == NULL || op_string < op_end))
8499 {
8500 saved = op_string;
8501 if (*op_string == '{')
8502 {
8503 op_string++;
8504
8505 /* Check broadcasts. */
8506 if (strncmp (op_string, "1to", 3) == 0)
8507 {
8508 int bcst_type;
8509
8510 if (i.broadcast)
8511 goto duplicated_vec_op;
8512
8513 op_string += 3;
8514 if (*op_string == '8')
8e6e0792 8515 bcst_type = 8;
b28d1bda 8516 else if (*op_string == '4')
8e6e0792 8517 bcst_type = 4;
b28d1bda 8518 else if (*op_string == '2')
8e6e0792 8519 bcst_type = 2;
43234a1e
L		 8520 else if (*op_string == '1'
8521 && *(op_string+1) == '6')
8522 {
8e6e0792 8523 bcst_type = 16;
43234a1e
L		 8524 op_string++;
8525 }
8526 else
8527 {
8528 as_bad (_("Unsupported broadcast: `%s'"), saved);
8529 return NULL;
8530 }
8531 op_string++;
8532
8533 broadcast_op.type = bcst_type;
8534 broadcast_op.operand = this_operand;
8535 i.broadcast = &broadcast_op;
8536 }
8537 /* Check masking operation. */
8538 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8539 {
8540 /* k0 can't be used for write mask. */
6d2cd6b2 8541 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
43234a1e 8542 {
6d2cd6b2
JB		 8543 as_bad (_("`%s%s' can't be used for write mask"),
8544 register_prefix, mask->reg_name);
43234a1e
L		 8545 return NULL;
8546 }
8547
8548 if (!i.mask)
8549 {
8550 mask_op.mask = mask;
8551 mask_op.zeroing = 0;
8552 mask_op.operand = this_operand;
8553 i.mask = &mask_op;
8554 }
8555 else
8556 {
8557 if (i.mask->mask)
8558 goto duplicated_vec_op;
8559
8560 i.mask->mask = mask;
8561
8562 /* Only "{z}" is allowed here. No need to check
8563 zeroing mask explicitly. */
8564 if (i.mask->operand != this_operand)
8565 {
8566 as_bad (_("invalid write mask `%s'"), saved);
8567 return NULL;
8568 }
8569 }
8570
8571 op_string = end_op;
8572 }
8573 /* Check zeroing-flag for masking operation. */
8574 else if (*op_string == 'z')
8575 {
8576 if (!i.mask)
8577 {
8578 mask_op.mask = NULL;
8579 mask_op.zeroing = 1;
8580 mask_op.operand = this_operand;
8581 i.mask = &mask_op;
8582 }
8583 else
8584 {
8585 if (i.mask->zeroing)
8586 {
8587 duplicated_vec_op:
8588 as_bad (_("duplicated `%s'"), saved);
8589 return NULL;
8590 }
8591
8592 i.mask->zeroing = 1;
8593
8594 /* Only "{%k}" is allowed here. No need to check mask
8595 register explicitly. */
8596 if (i.mask->operand != this_operand)
8597 {
8598 as_bad (_("invalid zeroing-masking `%s'"),
8599 saved);
8600 return NULL;
8601 }
8602 }
8603
8604 op_string++;
8605 }
8606 else
8607 goto unknown_vec_op;
8608
8609 if (*op_string != '}')
8610 {
8611 as_bad (_("missing `}' in `%s'"), saved);
8612 return NULL;
8613 }
8614 op_string++;
0ba3a731
L		 8615
8616 /* Strip whitespace since the addition of pseudo prefixes
8617 changed how the scrubber treats '{'. */
8618 if (is_space_char (*op_string))
8619 ++op_string;
8620
43234a1e
L		 8621 continue;
8622 }
8623 unknown_vec_op:
8624 /* We don't know this one. */
8625 as_bad (_("unknown vector operation: `%s'"), saved);
8626 return NULL;
8627 }
8628
6d2cd6b2
JB		 8629 if (i.mask && i.mask->zeroing && !i.mask->mask)
8630 {
8631 as_bad (_("zeroing-masking only allowed with write mask"));
8632 return NULL;
8633 }
8634
43234a1e
L		 8635 return op_string;
8636}
8637
252b5132 8638static int
70e41ade 8639i386_immediate (char *imm_start)
252b5132
RH		 8640{
8641 char *save_input_line_pointer;
f3c180ae 8642 char *gotfree_input_line;
252b5132 8643 segT exp_seg = 0;
47926f60 8644 expressionS *exp;
40fb9820
L		 8645 i386_operand_type types;
8646
0dfbf9d7 8647 operand_type_set (&types, ~0);
252b5132
RH		 8648
8649 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8650 {
31b2323c
L		 8651 as_bad (_("at most %d immediate operands are allowed"),
8652 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8653 return 0;
8654 }
8655
8656 exp = &im_expressions[i.imm_operands++];
520dc8e8 8657 i.op[this_operand].imms = exp;
252b5132
RH		 8658
8659 if (is_space_char (*imm_start))
8660 ++imm_start;
8661
8662 save_input_line_pointer = input_line_pointer;
8663 input_line_pointer = imm_start;
8664
d258b828 8665 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8666 if (gotfree_input_line)
8667 input_line_pointer = gotfree_input_line;
252b5132
RH		 8668
8669 exp_seg = expression (exp);
8670
83183c0c 8671 SKIP_WHITESPACE ();
43234a1e
L		 8672
8673 /* Handle vector operations. */
8674 if (*input_line_pointer == '{')
8675 {
8676 input_line_pointer = check_VecOperations (input_line_pointer,
8677 NULL);
8678 if (input_line_pointer == NULL)
8679 return 0;
8680 }
8681
252b5132 8682 if (*input_line_pointer)
f3c180ae 8683 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8684
8685 input_line_pointer = save_input_line_pointer;
f3c180ae 8686 if (gotfree_input_line)
ee86248c
JB		 8687 {
8688 free (gotfree_input_line);
8689
8690 if (exp->X_op == O_constant || exp->X_op == O_register)
8691 exp->X_op = O_illegal;
8692 }
8693
8694 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8695}
252b5132 8696
ee86248c
JB		 8697static int
8698i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8699 i386_operand_type types, const char *imm_start)
8700{
8701 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8702 {
313c53d1
L		 8703 if (imm_start)
8704 as_bad (_("missing or invalid immediate expression `%s'"),
8705 imm_start);
3992d3b7 8706 return 0;
252b5132 8707 }
3e73aa7c 8708 else if (exp->X_op == O_constant)
252b5132 8709 {
47926f60 8710 /* Size it properly later. */
40fb9820 8711 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8712 /* If not 64bit, sign extend val. */
8713 if (flag_code != CODE_64BIT
4eed87de
AM		 8714 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8715 exp->X_add_number
8716 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8717 }
4c63da97 8718#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8719 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8720 && exp_seg != absolute_section
47926f60 8721 && exp_seg != text_section
24eab124
AM		 8722 && exp_seg != data_section
8723 && exp_seg != bss_section
8724 && exp_seg != undefined_section
f86103b7 8725 && !bfd_is_com_section (exp_seg))
252b5132 8726 {
d0b47220 8727 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8728 return 0;
8729 }
8730#endif
a841bdf5 8731 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8732 {
313c53d1
L		 8733 if (imm_start)
8734 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8735 return 0;
8736 }
252b5132
RH		 8737 else
8738 {
8739 /* This is an address. The size of the address will be
24eab124 8740 determined later, depending on destination register,
3e73aa7c 8741 suffix, or the default for the section. */
40fb9820
L		 8742 i.types[this_operand].bitfield.imm8 = 1;
8743 i.types[this_operand].bitfield.imm16 = 1;
8744 i.types[this_operand].bitfield.imm32 = 1;
8745 i.types[this_operand].bitfield.imm32s = 1;
8746 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8747 i.types[this_operand] = operand_type_and (i.types[this_operand],
8748 types);
252b5132
RH		 8749 }
8750
8751 return 1;
8752}
8753
551c1ca1 8754static char *
e3bb37b5 8755i386_scale (char *scale)
252b5132 8756{
551c1ca1
AM		 8757 offsetT val;
8758 char *save = input_line_pointer;
252b5132 8759
551c1ca1
AM		 8760 input_line_pointer = scale;
8761 val = get_absolute_expression ();
8762
8763 switch (val)
252b5132 8764 {
551c1ca1 8765 case 1:
252b5132
RH		 8766 i.log2_scale_factor = 0;
8767 break;
551c1ca1 8768 case 2:
252b5132
RH		 8769 i.log2_scale_factor = 1;
8770 break;
551c1ca1 8771 case 4:
252b5132
RH		 8772 i.log2_scale_factor = 2;
8773 break;
551c1ca1 8774 case 8:
252b5132
RH		 8775 i.log2_scale_factor = 3;
8776 break;
8777 default:
a724f0f4
JB		 8778 {
8779 char sep = *input_line_pointer;
8780
8781 *input_line_pointer = '\0';
8782 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8783 scale);
8784 *input_line_pointer = sep;
8785 input_line_pointer = save;
8786 return NULL;
8787 }
252b5132 8788 }
29b0f896 8789 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8790 {
8791 as_warn (_("scale factor of %d without an index register"),
24eab124 8792 1 << i.log2_scale_factor);
252b5132 8793 i.log2_scale_factor = 0;
252b5132 8794 }
551c1ca1
AM		 8795 scale = input_line_pointer;
8796 input_line_pointer = save;
8797 return scale;
252b5132
RH		 8798}
8799
252b5132 8800static int
e3bb37b5 8801i386_displacement (char *disp_start, char *disp_end)
252b5132 8802{
29b0f896 8803 expressionS *exp;
252b5132
RH		 8804 segT exp_seg = 0;
8805 char *save_input_line_pointer;
f3c180ae 8806 char *gotfree_input_line;
40fb9820
L		 8807 int override;
8808 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8809 int ret;
252b5132 8810
31b2323c
L		 8811 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8812 {
8813 as_bad (_("at most %d displacement operands are allowed"),
8814 MAX_MEMORY_OPERANDS);
8815 return 0;
8816 }
8817
0dfbf9d7 8818 operand_type_set (&bigdisp, 0);
40fb9820
L		 8819 if ((i.types[this_operand].bitfield.jumpabsolute)
8820 || (!current_templates->start->opcode_modifier.jump
8821 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8822 {
40fb9820 8823 bigdisp.bitfield.disp32 = 1;
e05278af 8824 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8825 if (flag_code == CODE_64BIT)
8826 {
8827 if (!override)
8828 {
8829 bigdisp.bitfield.disp32s = 1;
8830 bigdisp.bitfield.disp64 = 1;
8831 }
8832 }
8833 else if ((flag_code == CODE_16BIT) ^ override)
8834 {
8835 bigdisp.bitfield.disp32 = 0;
8836 bigdisp.bitfield.disp16 = 1;
8837 }
e05278af
JB		 8838 }
8839 else
8840 {
8841 /* For PC-relative branches, the width of the displacement
8842 is dependent upon data size, not address size. */
e05278af 8843 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8844 if (flag_code == CODE_64BIT)
8845 {
8846 if (override || i.suffix == WORD_MNEM_SUFFIX)
8847 bigdisp.bitfield.disp16 = 1;
8848 else
8849 {
8850 bigdisp.bitfield.disp32 = 1;
8851 bigdisp.bitfield.disp32s = 1;
8852 }
8853 }
8854 else
e05278af
JB		 8855 {
8856 if (!override)
8857 override = (i.suffix == (flag_code != CODE_16BIT
8858 ? WORD_MNEM_SUFFIX
8859 : LONG_MNEM_SUFFIX));
40fb9820
L		 8860 bigdisp.bitfield.disp32 = 1;
8861 if ((flag_code == CODE_16BIT) ^ override)
8862 {
8863 bigdisp.bitfield.disp32 = 0;
8864 bigdisp.bitfield.disp16 = 1;
8865 }
e05278af 8866 }
e05278af 8867 }
c6fb90c8
L		 8868 i.types[this_operand] = operand_type_or (i.types[this_operand],
8869 bigdisp);
252b5132
RH		 8870
8871 exp = &disp_expressions[i.disp_operands];
520dc8e8 8872 i.op[this_operand].disps = exp;
252b5132
RH		 8873 i.disp_operands++;
8874 save_input_line_pointer = input_line_pointer;
8875 input_line_pointer = disp_start;
8876 END_STRING_AND_SAVE (disp_end);
8877
8878#ifndef GCC_ASM_O_HACK
8879#define GCC_ASM_O_HACK 0
8880#endif
8881#if GCC_ASM_O_HACK
8882 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8883 if (i.types[this_operand].bitfield.baseIndex
24eab124 8884 && displacement_string_end[-1] == '+')
252b5132
RH		 8885 {
8886 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8887 constraint within gcc asm statements.
8888 For instance:
8889
8890 #define _set_tssldt_desc(n,addr,limit,type) \
8891 __asm__ __volatile__ ( \
8892 "movw %w2,%0\n\t" \
8893 "movw %w1,2+%0\n\t" \
8894 "rorl $16,%1\n\t" \
8895 "movb %b1,4+%0\n\t" \
8896 "movb %4,5+%0\n\t" \
8897 "movb $0,6+%0\n\t" \
8898 "movb %h1,7+%0\n\t" \
8899 "rorl $16,%1" \
8900 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8901
8902 This works great except that the output assembler ends
8903 up looking a bit weird if it turns out that there is
8904 no offset. You end up producing code that looks like:
8905
8906 #APP
8907 movw $235,(%eax)
8908 movw %dx,2+(%eax)
8909 rorl $16,%edx
8910 movb %dl,4+(%eax)
8911 movb $137,5+(%eax)
8912 movb $0,6+(%eax)
8913 movb %dh,7+(%eax)
8914 rorl $16,%edx
8915 #NO_APP
8916
47926f60 8917 So here we provide the missing zero. */
24eab124
AM		 8918
8919 *displacement_string_end = '0';
252b5132
RH		 8920 }
8921#endif
d258b828 8922 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8923 if (gotfree_input_line)
8924 input_line_pointer = gotfree_input_line;
252b5132 8925
24eab124 8926 exp_seg = expression (exp);
252b5132 8927
636c26b0
AM		 8928 SKIP_WHITESPACE ();
8929 if (*input_line_pointer)
8930 as_bad (_("junk `%s' after expression"), input_line_pointer);
8931#if GCC_ASM_O_HACK
8932 RESTORE_END_STRING (disp_end + 1);
8933#endif
636c26b0 8934 input_line_pointer = save_input_line_pointer;
636c26b0 8935 if (gotfree_input_line)
ee86248c
JB		 8936 {
8937 free (gotfree_input_line);
8938
8939 if (exp->X_op == O_constant || exp->X_op == O_register)
8940 exp->X_op = O_illegal;
8941 }
8942
8943 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8944
8945 RESTORE_END_STRING (disp_end);
8946
8947 return ret;
8948}
8949
8950static int
8951i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8952 i386_operand_type types, const char *disp_start)
8953{
8954 i386_operand_type bigdisp;
8955 int ret = 1;
636c26b0 8956
24eab124
AM		 8957 /* We do this to make sure that the section symbol is in
8958 the symbol table. We will ultimately change the relocation
47926f60 8959 to be relative to the beginning of the section. */
1ae12ab7 8960 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8961 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8962 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8963 {
636c26b0 8964 if (exp->X_op != O_symbol)
3992d3b7 8965 goto inv_disp;
636c26b0 8966
e5cb08ac 8967 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8968 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8969 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8970 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8971 exp->X_op = O_subtract;
8972 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8973 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8974 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8975 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8976 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8977 else
29b0f896 8978 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8979 }
252b5132 8980
3992d3b7
AM		 8981 else if (exp->X_op == O_absent
8982 || exp->X_op == O_illegal
ee86248c 8983 || exp->X_op == O_big)
2daf4fd8 8984 {
3992d3b7
AM		 8985 inv_disp:
8986 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8987 disp_start);
3992d3b7 8988 ret = 0;
2daf4fd8
AM		 8989 }
8990
0e1147d9
L		 8991 else if (flag_code == CODE_64BIT
8992 && !i.prefix[ADDR_PREFIX]
8993 && exp->X_op == O_constant)
8994 {
8995 /* Since displacement is signed extended to 64bit, don't allow
8996 disp32 and turn off disp32s if they are out of range. */
8997 i.types[this_operand].bitfield.disp32 = 0;
8998 if (!fits_in_signed_long (exp->X_add_number))
8999 {
9000 i.types[this_operand].bitfield.disp32s = 0;
9001 if (i.types[this_operand].bitfield.baseindex)
9002 {
9003 as_bad (_("0x%lx out range of signed 32bit displacement"),
9004 (long) exp->X_add_number);
9005 ret = 0;
9006 }
9007 }
9008 }
9009
4c63da97 9010#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 9011 else if (exp->X_op != O_constant
9012 && OUTPUT_FLAVOR == bfd_target_aout_flavour
9013 && exp_seg != absolute_section
9014 && exp_seg != text_section
9015 && exp_seg != data_section
9016 && exp_seg != bss_section
9017 && exp_seg != undefined_section
9018 && !bfd_is_com_section (exp_seg))
24eab124 9019 {
d0b47220 9020 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 9021 ret = 0;
24eab124 9022 }
252b5132 9023#endif
3956db08 9024
40fb9820
L		 9025 /* Check if this is a displacement only operand. */
9026 bigdisp = i.types[this_operand];
9027 bigdisp.bitfield.disp8 = 0;
9028 bigdisp.bitfield.disp16 = 0;
9029 bigdisp.bitfield.disp32 = 0;
9030 bigdisp.bitfield.disp32s = 0;
9031 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 9032 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 9033 i.types[this_operand] = operand_type_and (i.types[this_operand],
9034 types);
3956db08 9035
3992d3b7 9036 return ret;
252b5132
RH		 9037}
9038
2abc2bec
JB		 9039/* Return the active addressing mode, taking address override and
9040 registers forming the address into consideration. Update the
9041 address override prefix if necessary. */
47926f60 9042
2abc2bec
JB		 9043static enum flag_code
9044i386_addressing_mode (void)
252b5132 9045{
be05d201
L		 9046 enum flag_code addr_mode;
9047
9048 if (i.prefix[ADDR_PREFIX])
9049 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9050 else
9051 {
9052 addr_mode = flag_code;
9053
24eab124 9054#if INFER_ADDR_PREFIX
be05d201
L		 9055 if (i.mem_operands == 0)
9056 {
9057 /* Infer address prefix from the first memory operand. */
9058 const reg_entry *addr_reg = i.base_reg;
9059
9060 if (addr_reg == NULL)
9061 addr_reg = i.index_reg;
eecb386c 9062
be05d201
L		 9063 if (addr_reg)
9064 {
9065 if (addr_reg->reg_num == RegEip
9066 || addr_reg->reg_num == RegEiz
dc821c5f 9067 || addr_reg->reg_type.bitfield.dword)
be05d201
L		 9068 addr_mode = CODE_32BIT;
9069 else if (flag_code != CODE_64BIT
dc821c5f 9070 && addr_reg->reg_type.bitfield.word)
be05d201
L		 9071 addr_mode = CODE_16BIT;
9072
9073 if (addr_mode != flag_code)
9074 {
9075 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9076 i.prefixes += 1;
9077 /* Change the size of any displacement too. At most one
9078 of Disp16 or Disp32 is set.
9079 FIXME. There doesn't seem to be any real need for
9080 separate Disp16 and Disp32 flags. The same goes for
9081 Imm16 and Imm32. Removing them would probably clean
9082 up the code quite a lot. */
9083 if (flag_code != CODE_64BIT
9084 && (i.types[this_operand].bitfield.disp16
9085 || i.types[this_operand].bitfield.disp32))
9086 i.types[this_operand]
9087 = operand_type_xor (i.types[this_operand], disp16_32);
9088 }
9089 }
9090 }
24eab124 9091#endif
be05d201
L		 9092 }
9093
2abc2bec
JB		 9094 return addr_mode;
9095}
9096
9097/* Make sure the memory operand we've been dealt is valid.
9098 Return 1 on success, 0 on a failure. */
9099
9100static int
9101i386_index_check (const char *operand_string)
9102{
9103 const char *kind = "base/index";
9104 enum flag_code addr_mode = i386_addressing_mode ();
9105
fc0763e6
JB		 9106 if (current_templates->start->opcode_modifier.isstring
9107 && !current_templates->start->opcode_modifier.immext
9108 && (current_templates->end[-1].opcode_modifier.isstring
9109 || i.mem_operands))
9110 {
9111 /* Memory operands of string insns are special in that they only allow
9112 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 9113 const reg_entry *expected_reg;
9114 static const char *di_si[][2] =
9115 {
9116 { "esi", "edi" },
9117 { "si", "di" },
9118 { "rsi", "rdi" }
9119 };
9120 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 9121
9122 kind = "string address";
9123
8325cc63 9124 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 9125 {
9126 i386_operand_type type = current_templates->end[-1].operand_types[0];
9127
9128 if (!type.bitfield.baseindex
9129 || ((!i.mem_operands != !intel_syntax)
9130 && current_templates->end[-1].operand_types[1]
9131 .bitfield.baseindex))
9132 type = current_templates->end[-1].operand_types[1];
be05d201
L		 9133 expected_reg = hash_find (reg_hash,
9134 di_si[addr_mode][type.bitfield.esseg]);
9135
fc0763e6
JB		 9136 }
9137 else
be05d201 9138 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 9139
be05d201
L		 9140 if (i.base_reg != expected_reg
9141 || i.index_reg
fc0763e6 9142 || operand_type_check (i.types[this_operand], disp))
fc0763e6 9143 {
be05d201
L		 9144 /* The second memory operand must have the same size as
9145 the first one. */
9146 if (i.mem_operands
9147 && i.base_reg
9148 && !((addr_mode == CODE_64BIT
dc821c5f 9149 && i.base_reg->reg_type.bitfield.qword)
be05d201 9150 || (addr_mode == CODE_32BIT
dc821c5f
JB		 9151 ? i.base_reg->reg_type.bitfield.dword
9152 : i.base_reg->reg_type.bitfield.word)))
be05d201
L		 9153 goto bad_address;
9154
fc0763e6
JB		 9155 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9156 operand_string,
9157 intel_syntax ? '[' : '(',
9158 register_prefix,
be05d201 9159 expected_reg->reg_name,
fc0763e6 9160 intel_syntax ? ']' : ')');
be05d201 9161 return 1;
fc0763e6 9162 }
be05d201
L		 9163 else
9164 return 1;
9165
9166bad_address:
9167 as_bad (_("`%s' is not a valid %s expression"),
9168 operand_string, kind);
9169 return 0;
3e73aa7c
JH		 9170 }
9171 else
9172 {
be05d201
L		 9173 if (addr_mode != CODE_16BIT)
9174 {
9175 /* 32-bit/64-bit checks. */
9176 if ((i.base_reg
9177 && (addr_mode == CODE_64BIT
dc821c5f
JB		 9178 ? !i.base_reg->reg_type.bitfield.qword
9179 : !i.base_reg->reg_type.bitfield.dword)
be05d201
L		 9180 && (i.index_reg
9181 || (i.base_reg->reg_num
9182 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9183 || (i.index_reg
1b54b8d7
JB		 9184 && !i.index_reg->reg_type.bitfield.xmmword
9185 && !i.index_reg->reg_type.bitfield.ymmword
9186 && !i.index_reg->reg_type.bitfield.zmmword
be05d201 9187 && ((addr_mode == CODE_64BIT
dc821c5f 9188 ? !(i.index_reg->reg_type.bitfield.qword
be05d201 9189 || i.index_reg->reg_num == RegRiz)
dc821c5f 9190 : !(i.index_reg->reg_type.bitfield.dword
be05d201
L		 9191 || i.index_reg->reg_num == RegEiz))
9192 || !i.index_reg->reg_type.bitfield.baseindex)))
9193 goto bad_address;
8178be5b
JB		 9194
9195 /* bndmk, bndldx, and bndstx have special restrictions. */
9196 if (current_templates->start->base_opcode == 0xf30f1b
9197 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9198 {
9199 /* They cannot use RIP-relative addressing. */
9200 if (i.base_reg && i.base_reg->reg_num == RegRip)
9201 {
9202 as_bad (_("`%s' cannot be used here"), operand_string);
9203 return 0;
9204 }
9205
9206 /* bndldx and bndstx ignore their scale factor. */
9207 if (current_templates->start->base_opcode != 0xf30f1b
9208 && i.log2_scale_factor)
9209 as_warn (_("register scaling is being ignored here"));
9210 }
be05d201
L		 9211 }
9212 else
3e73aa7c 9213 {
be05d201 9214 /* 16-bit checks. */
3e73aa7c 9215 if ((i.base_reg
dc821c5f 9216 && (!i.base_reg->reg_type.bitfield.word
40fb9820 9217 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 9218 || (i.index_reg
dc821c5f 9219 && (!i.index_reg->reg_type.bitfield.word
40fb9820 9220 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 9221 || !(i.base_reg
9222 && i.base_reg->reg_num < 6
9223 && i.index_reg->reg_num >= 6
9224 && i.log2_scale_factor == 0))))
be05d201 9225 goto bad_address;
3e73aa7c
JH		 9226 }
9227 }
be05d201 9228 return 1;
24eab124 9229}
252b5132 9230
43234a1e
L		 9231/* Handle vector immediates. */
9232
9233static int
9234RC_SAE_immediate (const char *imm_start)
9235{
9236 unsigned int match_found, j;
9237 const char *pstr = imm_start;
9238 expressionS *exp;
9239
9240 if (*pstr != '{')
9241 return 0;
9242
9243 pstr++;
9244 match_found = 0;
9245 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9246 {
9247 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9248 {
9249 if (!i.rounding)
9250 {
9251 rc_op.type = RC_NamesTable[j].type;
9252 rc_op.operand = this_operand;
9253 i.rounding = &rc_op;
9254 }
9255 else
9256 {
9257 as_bad (_("duplicated `%s'"), imm_start);
9258 return 0;
9259 }
9260 pstr += RC_NamesTable[j].len;
9261 match_found = 1;
9262 break;
9263 }
9264 }
9265 if (!match_found)
9266 return 0;
9267
9268 if (*pstr++ != '}')
9269 {
9270 as_bad (_("Missing '}': '%s'"), imm_start);
9271 return 0;
9272 }
9273 /* RC/SAE immediate string should contain nothing more. */;
9274 if (*pstr != 0)
9275 {
9276 as_bad (_("Junk after '}': '%s'"), imm_start);
9277 return 0;
9278 }
9279
9280 exp = &im_expressions[i.imm_operands++];
9281 i.op[this_operand].imms = exp;
9282
9283 exp->X_op = O_constant;
9284 exp->X_add_number = 0;
9285 exp->X_add_symbol = (symbolS *) 0;
9286 exp->X_op_symbol = (symbolS *) 0;
9287
9288 i.types[this_operand].bitfield.imm8 = 1;
9289 return 1;
9290}
9291
8325cc63
JB		 9292/* Only string instructions can have a second memory operand, so
9293 reduce current_templates to just those if it contains any. */
9294static int
9295maybe_adjust_templates (void)
9296{
9297 const insn_template *t;
9298
9299 gas_assert (i.mem_operands == 1);
9300
9301 for (t = current_templates->start; t < current_templates->end; ++t)
9302 if (t->opcode_modifier.isstring)
9303 break;
9304
9305 if (t < current_templates->end)
9306 {
9307 static templates aux_templates;
9308 bfd_boolean recheck;
9309
9310 aux_templates.start = t;
9311 for (; t < current_templates->end; ++t)
9312 if (!t->opcode_modifier.isstring)
9313 break;
9314 aux_templates.end = t;
9315
9316 /* Determine whether to re-check the first memory operand. */
9317 recheck = (aux_templates.start != current_templates->start
9318 || t != current_templates->end);
9319
9320 current_templates = &aux_templates;
9321
9322 if (recheck)
9323 {
9324 i.mem_operands = 0;
9325 if (i.memop1_string != NULL
9326 && i386_index_check (i.memop1_string) == 0)
9327 return 0;
9328 i.mem_operands = 1;
9329 }
9330 }
9331
9332 return 1;
9333}
9334
fc0763e6 9335/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 9336 on error. */
252b5132 9337
252b5132 9338static int
a7619375 9339i386_att_operand (char *operand_string)
252b5132 9340{
af6bdddf
AM		 9341 const reg_entry *r;
9342 char *end_op;
24eab124 9343 char *op_string = operand_string;
252b5132 9344
24eab124 9345 if (is_space_char (*op_string))
252b5132
RH		 9346 ++op_string;
9347
24eab124 9348 /* We check for an absolute prefix (differentiating,
47926f60 9349 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 9350 if (*op_string == ABSOLUTE_PREFIX)
9351 {
9352 ++op_string;
9353 if (is_space_char (*op_string))
9354 ++op_string;
40fb9820 9355 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 9356 }
252b5132 9357
47926f60 9358 /* Check if operand is a register. */
4d1bb795 9359 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 9360 {
40fb9820
L		 9361 i386_operand_type temp;
9362
24eab124
AM		 9363 /* Check for a segment override by searching for ':' after a
9364 segment register. */
9365 op_string = end_op;
9366 if (is_space_char (*op_string))
9367 ++op_string;
40fb9820
L		 9368 if (*op_string == ':'
9369 && (r->reg_type.bitfield.sreg2
9370 || r->reg_type.bitfield.sreg3))
24eab124
AM		 9371 {
9372 switch (r->reg_num)
9373 {
9374 case 0:
9375 i.seg[i.mem_operands] = &es;
9376 break;
9377 case 1:
9378 i.seg[i.mem_operands] = &cs;
9379 break;
9380 case 2:
9381 i.seg[i.mem_operands] = &ss;
9382 break;
9383 case 3:
9384 i.seg[i.mem_operands] = &ds;
9385 break;
9386 case 4:
9387 i.seg[i.mem_operands] = &fs;
9388 break;
9389 case 5:
9390 i.seg[i.mem_operands] = &gs;
9391 break;
9392 }
252b5132 9393
24eab124 9394 /* Skip the ':' and whitespace. */
252b5132
RH		 9395 ++op_string;
9396 if (is_space_char (*op_string))
24eab124 9397 ++op_string;
252b5132 9398
24eab124
AM		 9399 if (!is_digit_char (*op_string)
9400 && !is_identifier_char (*op_string)
9401 && *op_string != '('
9402 && *op_string != ABSOLUTE_PREFIX)
9403 {
9404 as_bad (_("bad memory operand `%s'"), op_string);
9405 return 0;
9406 }
47926f60 9407 /* Handle case of %es:*foo. */
24eab124
AM		 9408 if (*op_string == ABSOLUTE_PREFIX)
9409 {
9410 ++op_string;
9411 if (is_space_char (*op_string))
9412 ++op_string;
40fb9820 9413 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 9414 }
9415 goto do_memory_reference;
9416 }
43234a1e
L		 9417
9418 /* Handle vector operations. */
9419 if (*op_string == '{')
9420 {
9421 op_string = check_VecOperations (op_string, NULL);
9422 if (op_string == NULL)
9423 return 0;
9424 }
9425
24eab124
AM		 9426 if (*op_string)
9427 {
d0b47220 9428 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 9429 return 0;
9430 }
40fb9820
L		 9431 temp = r->reg_type;
9432 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9433 i.types[this_operand] = operand_type_or (i.types[this_operand],
9434 temp);
7d5e4556 9435 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 9436 i.op[this_operand].regs = r;
24eab124
AM		 9437 i.reg_operands++;
9438 }
af6bdddf
AM		 9439 else if (*op_string == REGISTER_PREFIX)
9440 {
9441 as_bad (_("bad register name `%s'"), op_string);
9442 return 0;
9443 }
24eab124 9444 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 9445 {
24eab124 9446 ++op_string;
40fb9820 9447 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 9448 {
d0b47220 9449 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 9450 return 0;
9451 }
9452 if (!i386_immediate (op_string))
9453 return 0;
9454 }
43234a1e
L		 9455 else if (RC_SAE_immediate (operand_string))
9456 {
9457 /* If it is a RC or SAE immediate, do nothing. */
9458 ;
9459 }
24eab124
AM		 9460 else if (is_digit_char (*op_string)
9461 || is_identifier_char (*op_string)
d02603dc 9462 || *op_string == '"'
e5cb08ac 9463 || *op_string == '(')
24eab124 9464 {
47926f60 9465 /* This is a memory reference of some sort. */
af6bdddf 9466 char *base_string;
252b5132 9467
47926f60 9468 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 9469 char *displacement_string_start;
9470 char *displacement_string_end;
43234a1e 9471 char *vop_start;
252b5132 9472
24eab124 9473 do_memory_reference:
8325cc63
JB		 9474 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9475 return 0;
24eab124 9476 if ((i.mem_operands == 1
40fb9820 9477 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 9478 || i.mem_operands == 2)
9479 {
9480 as_bad (_("too many memory references for `%s'"),
9481 current_templates->start->name);
9482 return 0;
9483 }
252b5132 9484
24eab124
AM		 9485 /* Check for base index form. We detect the base index form by
9486 looking for an ')' at the end of the operand, searching
9487 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9488 after the '('. */
af6bdddf 9489 base_string = op_string + strlen (op_string);
c3332e24 9490
43234a1e
L		 9491 /* Handle vector operations. */
9492 vop_start = strchr (op_string, '{');
9493 if (vop_start && vop_start < base_string)
9494 {
9495 if (check_VecOperations (vop_start, base_string) == NULL)
9496 return 0;
9497 base_string = vop_start;
9498 }
9499
af6bdddf
AM		 9500 --base_string;
9501 if (is_space_char (*base_string))
9502 --base_string;
252b5132 9503
47926f60 9504 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 9505 displacement_string_start = op_string;
9506 displacement_string_end = base_string + 1;
252b5132 9507
24eab124
AM		 9508 if (*base_string == ')')
9509 {
af6bdddf 9510 char *temp_string;
24eab124
AM		 9511 unsigned int parens_balanced = 1;
9512 /* We've already checked that the number of left & right ()'s are
47926f60 9513 equal, so this loop will not be infinite. */
24eab124
AM		 9514 do
9515 {
9516 base_string--;
9517 if (*base_string == ')')
9518 parens_balanced++;
9519 if (*base_string == '(')
9520 parens_balanced--;
9521 }
9522 while (parens_balanced);
c3332e24 9523
af6bdddf 9524 temp_string = base_string;
c3332e24 9525
24eab124 9526 /* Skip past '(' and whitespace. */
252b5132
RH		 9527 ++base_string;
9528 if (is_space_char (*base_string))
24eab124 9529 ++base_string;
252b5132 9530
af6bdddf 9531 if (*base_string == ','
4eed87de
AM		 9532 || ((i.base_reg = parse_register (base_string, &end_op))
9533 != NULL))
252b5132 9534 {
af6bdddf 9535 displacement_string_end = temp_string;
252b5132 9536
40fb9820 9537 i.types[this_operand].bitfield.baseindex = 1;
252b5132 9538
af6bdddf 9539 if (i.base_reg)
24eab124 9540 {
24eab124
AM		 9541 base_string = end_op;
9542 if (is_space_char (*base_string))
9543 ++base_string;
af6bdddf
AM		 9544 }
9545
9546 /* There may be an index reg or scale factor here. */
9547 if (*base_string == ',')
9548 {
9549 ++base_string;
9550 if (is_space_char (*base_string))
9551 ++base_string;
9552
4eed87de
AM		 9553 if ((i.index_reg = parse_register (base_string, &end_op))
9554 != NULL)
24eab124 9555 {
af6bdddf 9556 base_string = end_op;
24eab124
AM		 9557 if (is_space_char (*base_string))
9558 ++base_string;
af6bdddf
AM		 9559 if (*base_string == ',')
9560 {
9561 ++base_string;
9562 if (is_space_char (*base_string))
9563 ++base_string;
9564 }
e5cb08ac 9565 else if (*base_string != ')')
af6bdddf 9566 {
4eed87de
AM		 9567 as_bad (_("expecting `,' or `)' "
9568 "after index register in `%s'"),
af6bdddf
AM		 9569 operand_string);
9570 return 0;
9571 }
24eab124 9572 }
af6bdddf 9573 else if (*base_string == REGISTER_PREFIX)
24eab124 9574 {
f76bf5e0
L		 9575 end_op = strchr (base_string, ',');
9576 if (end_op)
9577 *end_op = '\0';
af6bdddf 9578 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9579 return 0;
9580 }
252b5132 9581
47926f60 9582 /* Check for scale factor. */
551c1ca1 9583 if (*base_string != ')')
af6bdddf 9584 {
551c1ca1
AM		 9585 char *end_scale = i386_scale (base_string);
9586
9587 if (!end_scale)
af6bdddf 9588 return 0;
24eab124 9589
551c1ca1 9590 base_string = end_scale;
af6bdddf
AM		 9591 if (is_space_char (*base_string))
9592 ++base_string;
9593 if (*base_string != ')')
9594 {
4eed87de
AM		 9595 as_bad (_("expecting `)' "
9596 "after scale factor in `%s'"),
af6bdddf
AM		 9597 operand_string);
9598 return 0;
9599 }
9600 }
9601 else if (!i.index_reg)
24eab124 9602 {
4eed87de
AM		 9603 as_bad (_("expecting index register or scale factor "
9604 "after `,'; got '%c'"),
af6bdddf 9605 *base_string);
24eab124
AM		 9606 return 0;
9607 }
9608 }
af6bdddf 9609 else if (*base_string != ')')
24eab124 9610 {
4eed87de
AM		 9611 as_bad (_("expecting `,' or `)' "
9612 "after base register in `%s'"),
af6bdddf 9613 operand_string);
24eab124
AM		 9614 return 0;
9615 }
c3332e24 9616 }
af6bdddf 9617 else if (*base_string == REGISTER_PREFIX)
c3332e24 9618 {
f76bf5e0
L		 9619 end_op = strchr (base_string, ',');
9620 if (end_op)
9621 *end_op = '\0';
af6bdddf 9622 as_bad (_("bad register name `%s'"), base_string);
24eab124 9623 return 0;
c3332e24 9624 }
24eab124
AM		 9625 }
9626
9627 /* If there's an expression beginning the operand, parse it,
9628 assuming displacement_string_start and
9629 displacement_string_end are meaningful. */
9630 if (displacement_string_start != displacement_string_end)
9631 {
9632 if (!i386_displacement (displacement_string_start,
9633 displacement_string_end))
9634 return 0;
9635 }
9636
9637 /* Special case for (%dx) while doing input/output op. */
9638 if (i.base_reg
0dfbf9d7
L		 9639 && operand_type_equal (&i.base_reg->reg_type,
9640 &reg16_inoutportreg)
24eab124
AM		 9641 && i.index_reg == 0
9642 && i.log2_scale_factor == 0
9643 && i.seg[i.mem_operands] == 0
40fb9820 9644 && !operand_type_check (i.types[this_operand], disp))
24eab124 9645 {
65da13b5 9646 i.types[this_operand] = inoutportreg;
24eab124
AM		 9647 return 1;
9648 }
9649
eecb386c
AM		 9650 if (i386_index_check (operand_string) == 0)
9651 return 0;
5c07affc 9652 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9653 if (i.mem_operands == 0)
9654 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9655 i.mem_operands++;
9656 }
9657 else
ce8a8b2f
AM		 9658 {
9659 /* It's not a memory operand; argh! */
24eab124
AM		 9660 as_bad (_("invalid char %s beginning operand %d `%s'"),
9661 output_invalid (*op_string),
9662 this_operand + 1,
9663 op_string);
9664 return 0;
9665 }
47926f60 9666 return 1; /* Normal return. */
252b5132
RH		 9667}
9668\f
fa94de6b
RM		 9669/* Calculate the maximum variable size (i.e., excluding fr_fix)
9670 that an rs_machine_dependent frag may reach. */
9671
9672unsigned int
9673i386_frag_max_var (fragS *frag)
9674{
9675 /* The only relaxable frags are for jumps.
9676 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9677 gas_assert (frag->fr_type == rs_machine_dependent);
9678 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9679}
9680
b084df0b
L		 9681#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9682static int
8dcea932 9683elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9684{
9685 /* STT_GNU_IFUNC symbol must go through PLT. */
9686 if ((symbol_get_bfdsym (fr_symbol)->flags
9687 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9688 return 0;
9689
9690 if (!S_IS_EXTERNAL (fr_symbol))
9691 /* Symbol may be weak or local. */
9692 return !S_IS_WEAK (fr_symbol);
9693
8dcea932
L		 9694 /* Global symbols with non-default visibility can't be preempted. */
9695 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9696 return 1;
9697
9698 if (fr_var != NO_RELOC)
9699 switch ((enum bfd_reloc_code_real) fr_var)
9700 {
9701 case BFD_RELOC_386_PLT32:
9702 case BFD_RELOC_X86_64_PLT32:
33eaf5de 9703 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 9704 return 0;
9705 default:
9706 abort ();
9707 }
9708
b084df0b
L		 9709 /* Global symbols with default visibility in a shared library may be
9710 preempted by another definition. */
8dcea932 9711 return !shared;
b084df0b
L		 9712}
9713#endif
9714
ee7fcc42
AM		 9715/* md_estimate_size_before_relax()
9716
9717 Called just before relax() for rs_machine_dependent frags. The x86
9718 assembler uses these frags to handle variable size jump
9719 instructions.
9720
9721 Any symbol that is now undefined will not become defined.
9722 Return the correct fr_subtype in the frag.
9723 Return the initial "guess for variable size of frag" to caller.
9724 The guess is actually the growth beyond the fixed part. Whatever
9725 we do to grow the fixed or variable part contributes to our
9726 returned value. */
9727
252b5132 9728int
7016a5d5 9729md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9730{
252b5132 9731 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9732 check for un-relaxable symbols. On an ELF system, we can't relax
9733 an externally visible symbol, because it may be overridden by a
9734 shared library. */
9735 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9736#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9737 || (IS_ELF
8dcea932
L		 9738 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9739 fragP->fr_var))
fbeb56a4
DK		 9740#endif
9741#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9742 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9743 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9744#endif
9745 )
252b5132 9746 {
b98ef147
AM		 9747 /* Symbol is undefined in this segment, or we need to keep a
9748 reloc so that weak symbols can be overridden. */
9749 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9750 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9751 unsigned char *opcode;
9752 int old_fr_fix;
f6af82bd 9753
ee7fcc42 9754 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9755 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9756 else if (size == 2)
f6af82bd 9757 reloc_type = BFD_RELOC_16_PCREL;
bd7ab16b
L		 9758#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9759 else if (need_plt32_p (fragP->fr_symbol))
9760 reloc_type = BFD_RELOC_X86_64_PLT32;
9761#endif
f6af82bd
AM		 9762 else
9763 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9764
ee7fcc42
AM		 9765 old_fr_fix = fragP->fr_fix;
9766 opcode = (unsigned char *) fragP->fr_opcode;
9767
fddf5b5b 9768 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9769 {
fddf5b5b
AM		 9770 case UNCOND_JUMP:
9771 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9772 opcode[0] = 0xe9;
252b5132 9773 fragP->fr_fix += size;
062cd5e7
AS		 9774 fix_new (fragP, old_fr_fix, size,
9775 fragP->fr_symbol,
9776 fragP->fr_offset, 1,
9777 reloc_type);
252b5132
RH		 9778 break;
9779
fddf5b5b 9780 case COND_JUMP86:
412167cb
AM		 9781 if (size == 2
9782 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9783 {
9784 /* Negate the condition, and branch past an
9785 unconditional jump. */
9786 opcode[0] ^= 1;
9787 opcode[1] = 3;
9788 /* Insert an unconditional jump. */
9789 opcode[2] = 0xe9;
9790 /* We added two extra opcode bytes, and have a two byte
9791 offset. */
9792 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9793 fix_new (fragP, old_fr_fix + 2, 2,
9794 fragP->fr_symbol,
9795 fragP->fr_offset, 1,
9796 reloc_type);
fddf5b5b
AM		 9797 break;
9798 }
9799 /* Fall through. */
9800
9801 case COND_JUMP:
412167cb
AM		 9802 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9803 {
3e02c1cc
AM		 9804 fixS *fixP;
9805
412167cb 9806 fragP->fr_fix += 1;
3e02c1cc
AM		 9807 fixP = fix_new (fragP, old_fr_fix, 1,
9808 fragP->fr_symbol,
9809 fragP->fr_offset, 1,
9810 BFD_RELOC_8_PCREL);
9811 fixP->fx_signed = 1;
412167cb
AM		 9812 break;
9813 }
93c2a809 9814
24eab124 9815 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9816 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9817 opcode[1] = opcode[0] + 0x10;
f6af82bd 9818 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9819 /* We've added an opcode byte. */
9820 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9821 fix_new (fragP, old_fr_fix + 1, size,
9822 fragP->fr_symbol,
9823 fragP->fr_offset, 1,
9824 reloc_type);
252b5132 9825 break;
fddf5b5b
AM		 9826
9827 default:
9828 BAD_CASE (fragP->fr_subtype);
9829 break;
252b5132
RH		 9830 }
9831 frag_wane (fragP);
ee7fcc42 9832 return fragP->fr_fix - old_fr_fix;
252b5132 9833 }
93c2a809 9834
93c2a809
AM		 9835 /* Guess size depending on current relax state. Initially the relax
9836 state will correspond to a short jump and we return 1, because
9837 the variable part of the frag (the branch offset) is one byte
9838 long. However, we can relax a section more than once and in that
9839 case we must either set fr_subtype back to the unrelaxed state,
9840 or return the value for the appropriate branch. */
9841 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9842}
9843
47926f60
KH		 9844/* Called after relax() is finished.
9845
9846 In: Address of frag.
9847 fr_type == rs_machine_dependent.
9848 fr_subtype is what the address relaxed to.
9849
9850 Out: Any fixSs and constants are set up.
9851 Caller will turn frag into a ".space 0". */
9852
252b5132 9853void
7016a5d5
TG		 9854md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9855 fragS *fragP)
252b5132 9856{
29b0f896 9857 unsigned char *opcode;
252b5132 9858 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9859 offsetT target_address;
9860 offsetT opcode_address;
252b5132 9861 unsigned int extension = 0;
847f7ad4 9862 offsetT displacement_from_opcode_start;
252b5132
RH		 9863
9864 opcode = (unsigned char *) fragP->fr_opcode;
9865
47926f60 9866 /* Address we want to reach in file space. */
252b5132 9867 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9868
47926f60 9869 /* Address opcode resides at in file space. */
252b5132
RH		 9870 opcode_address = fragP->fr_address + fragP->fr_fix;
9871
47926f60 9872 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9873 displacement_from_opcode_start = target_address - opcode_address;
9874
fddf5b5b 9875 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9876 {
47926f60
KH		 9877 /* Don't have to change opcode. */
9878 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9879 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9880 }
9881 else
9882 {
9883 if (no_cond_jump_promotion
9884 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9885 as_warn_where (fragP->fr_file, fragP->fr_line,
9886 _("long jump required"));
252b5132 9887
fddf5b5b
AM		 9888 switch (fragP->fr_subtype)
9889 {
9890 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9891 extension = 4; /* 1 opcode + 4 displacement */
9892 opcode[0] = 0xe9;
9893 where_to_put_displacement = &opcode[1];
9894 break;
252b5132 9895
fddf5b5b
AM		 9896 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9897 extension = 2; /* 1 opcode + 2 displacement */
9898 opcode[0] = 0xe9;
9899 where_to_put_displacement = &opcode[1];
9900 break;
252b5132 9901
fddf5b5b
AM		 9902 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9903 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9904 extension = 5; /* 2 opcode + 4 displacement */
9905 opcode[1] = opcode[0] + 0x10;
9906 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9907 where_to_put_displacement = &opcode[2];
9908 break;
252b5132 9909
fddf5b5b
AM		 9910 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9911 extension = 3; /* 2 opcode + 2 displacement */
9912 opcode[1] = opcode[0] + 0x10;
9913 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9914 where_to_put_displacement = &opcode[2];
9915 break;
252b5132 9916
fddf5b5b
AM		 9917 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9918 extension = 4;
9919 opcode[0] ^= 1;
9920 opcode[1] = 3;
9921 opcode[2] = 0xe9;
9922 where_to_put_displacement = &opcode[3];
9923 break;
9924
9925 default:
9926 BAD_CASE (fragP->fr_subtype);
9927 break;
9928 }
252b5132 9929 }
fddf5b5b 9930
7b81dfbb
AJ		 9931 /* If size if less then four we are sure that the operand fits,
9932 but if it's 4, then it could be that the displacement is larger
9933 then -/+ 2GB. */
9934 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9935 && object_64bit
9936 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9937 + ((addressT) 1 << 31))
9938 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9939 {
9940 as_bad_where (fragP->fr_file, fragP->fr_line,
9941 _("jump target out of range"));
9942 /* Make us emit 0. */
9943 displacement_from_opcode_start = extension;
9944 }
47926f60 9945 /* Now put displacement after opcode. */
252b5132
RH		 9946 md_number_to_chars ((char *) where_to_put_displacement,
9947 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9948 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9949 fragP->fr_fix += extension;
9950}
9951\f
7016a5d5 9952/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9953 by our caller that we have all the info we need to fix it up.
9954
7016a5d5
TG		 9955 Parameter valP is the pointer to the value of the bits.
9956
252b5132
RH		 9957 On the 386, immediates, displacements, and data pointers are all in
9958 the same (little-endian) format, so we don't need to care about which
9959 we are handling. */
9960
94f592af 9961void
7016a5d5 9962md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9963{
94f592af 9964 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9965 valueT value = *valP;
252b5132 9966
f86103b7 9967#if !defined (TE_Mach)
93382f6d
AM		 9968 if (fixP->fx_pcrel)
9969 {
9970 switch (fixP->fx_r_type)
9971 {
5865bb77
ILT		 9972 default:
9973 break;
9974
d6ab8113
JB		 9975 case BFD_RELOC_64:
9976 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9977 break;
93382f6d 9978 case BFD_RELOC_32:
ae8887b5 9979 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9980 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9981 break;
9982 case BFD_RELOC_16:
9983 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9984 break;
9985 case BFD_RELOC_8:
9986 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9987 break;
9988 }
9989 }
252b5132 9990
a161fe53 9991 if (fixP->fx_addsy != NULL
31312f95 9992 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9993 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9994 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9995 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9996 && !use_rela_relocations)
252b5132 9997 {
31312f95
AM		 9998 /* This is a hack. There should be a better way to handle this.
9999 This covers for the fact that bfd_install_relocation will
10000 subtract the current location (for partial_inplace, PC relative
10001 relocations); see more below. */
252b5132 10002#ifndef OBJ_AOUT
718ddfc0 10003 if (IS_ELF
252b5132
RH		 10004#ifdef TE_PE
10005 || OUTPUT_FLAVOR == bfd_target_coff_flavour
10006#endif
10007 )
10008 value += fixP->fx_where + fixP->fx_frag->fr_address;
10009#endif
10010#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 10011 if (IS_ELF)
252b5132 10012 {
6539b54b 10013 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 10014
6539b54b 10015 if ((sym_seg == seg
2f66722d 10016 || (symbol_section_p (fixP->fx_addsy)
6539b54b 10017 && sym_seg != absolute_section))
af65af87 10018 && !generic_force_reloc (fixP))
2f66722d
AM		 10019 {
10020 /* Yes, we add the values in twice. This is because
6539b54b
AM		 10021 bfd_install_relocation subtracts them out again. I think
10022 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 10023 it. FIXME. */
10024 value += fixP->fx_where + fixP->fx_frag->fr_address;
10025 }
252b5132
RH		 10026 }
10027#endif
10028#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 10029 /* For some reason, the PE format does not store a
10030 section address offset for a PC relative symbol. */
10031 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 10032 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 10033 value += md_pcrel_from (fixP);
10034#endif
10035 }
fbeb56a4 10036#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 10037 if (fixP->fx_addsy != NULL
10038 && S_IS_WEAK (fixP->fx_addsy)
10039 /* PR 16858: Do not modify weak function references. */
10040 && ! fixP->fx_pcrel)
fbeb56a4 10041 {
296a8689
NC		 10042#if !defined (TE_PEP)
10043 /* For x86 PE weak function symbols are neither PC-relative
10044 nor do they set S_IS_FUNCTION. So the only reliable way
10045 to detect them is to check the flags of their containing
10046 section. */
10047 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
10048 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10049 ;
10050 else
10051#endif
fbeb56a4
DK		 10052 value -= S_GET_VALUE (fixP->fx_addsy);
10053 }
10054#endif
252b5132
RH		 10055
10056 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 10057 and we must not disappoint it. */
252b5132 10058#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 10059 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 10060 switch (fixP->fx_r_type)
10061 {
10062 case BFD_RELOC_386_PLT32:
3e73aa7c 10063 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 10064 /* Make the jump instruction point to the address of the operand. At
10065 runtime we merely add the offset to the actual PLT entry. */
10066 value = -4;
10067 break;
31312f95 10068
13ae64f3
JJ		 10069 case BFD_RELOC_386_TLS_GD:
10070 case BFD_RELOC_386_TLS_LDM:
13ae64f3 10071 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10072 case BFD_RELOC_386_TLS_IE:
10073 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 10074 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 10075 case BFD_RELOC_X86_64_TLSGD:
10076 case BFD_RELOC_X86_64_TLSLD:
10077 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 10078 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 10079 value = 0; /* Fully resolved at runtime. No addend. */
10080 /* Fallthrough */
10081 case BFD_RELOC_386_TLS_LE:
10082 case BFD_RELOC_386_TLS_LDO_32:
10083 case BFD_RELOC_386_TLS_LE_32:
10084 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10085 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 10086 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 10087 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 10088 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10089 break;
10090
67a4f2b7
AO		 10091 case BFD_RELOC_386_TLS_DESC_CALL:
10092 case BFD_RELOC_X86_64_TLSDESC_CALL:
10093 value = 0; /* Fully resolved at runtime. No addend. */
10094 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10095 fixP->fx_done = 0;
10096 return;
10097
47926f60
KH		 10098 case BFD_RELOC_VTABLE_INHERIT:
10099 case BFD_RELOC_VTABLE_ENTRY:
10100 fixP->fx_done = 0;
94f592af 10101 return;
47926f60
KH		 10102
10103 default:
10104 break;
10105 }
10106#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 10107 *valP = value;
f86103b7 10108#endif /* !defined (TE_Mach) */
3e73aa7c 10109
3e73aa7c 10110 /* Are we finished with this relocation now? */
c6682705 10111 if (fixP->fx_addsy == NULL)
3e73aa7c 10112 fixP->fx_done = 1;
fbeb56a4
DK		 10113#if defined (OBJ_COFF) && defined (TE_PE)
10114 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10115 {
10116 fixP->fx_done = 0;
10117 /* Remember value for tc_gen_reloc. */
10118 fixP->fx_addnumber = value;
10119 /* Clear out the frag for now. */
10120 value = 0;
10121 }
10122#endif
3e73aa7c
JH		 10123 else if (use_rela_relocations)
10124 {
10125 fixP->fx_no_overflow = 1;
062cd5e7
AS		 10126 /* Remember value for tc_gen_reloc. */
10127 fixP->fx_addnumber = value;
3e73aa7c
JH		 10128 value = 0;
10129 }
f86103b7 10130
94f592af 10131 md_number_to_chars (p, value, fixP->fx_size);
252b5132 10132}
252b5132 10133\f
6d4af3c2 10134const char *
499ac353 10135md_atof (int type, char *litP, int *sizeP)
252b5132 10136{
499ac353
NC		 10137 /* This outputs the LITTLENUMs in REVERSE order;
10138 in accord with the bigendian 386. */
10139 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 10140}
10141\f
2d545b82 10142static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 10143
252b5132 10144static char *
e3bb37b5 10145output_invalid (int c)
252b5132 10146{
3882b010 10147 if (ISPRINT (c))
f9f21a03
L		 10148 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10149 "'%c'", c);
252b5132 10150 else
f9f21a03 10151 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 10152 "(0x%x)", (unsigned char) c);
252b5132
RH		 10153 return output_invalid_buf;
10154}
10155
af6bdddf 10156/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 10157
10158static const reg_entry *
4d1bb795 10159parse_real_register (char *reg_string, char **end_op)
252b5132 10160{
af6bdddf
AM		 10161 char *s = reg_string;
10162 char *p;
252b5132
RH		 10163 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10164 const reg_entry *r;
10165
10166 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10167 if (*s == REGISTER_PREFIX)
10168 ++s;
10169
10170 if (is_space_char (*s))
10171 ++s;
10172
10173 p = reg_name_given;
af6bdddf 10174 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 10175 {
10176 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 10177 return (const reg_entry *) NULL;
10178 s++;
252b5132
RH		 10179 }
10180
6588847e
DN		 10181 /* For naked regs, make sure that we are not dealing with an identifier.
10182 This prevents confusing an identifier like `eax_var' with register
10183 `eax'. */
10184 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10185 return (const reg_entry *) NULL;
10186
af6bdddf 10187 *end_op = s;
252b5132
RH		 10188
10189 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10190
5f47d35b 10191 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 10192 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 10193 {
0e0eea78
JB		 10194 if (!cpu_arch_flags.bitfield.cpu8087
10195 && !cpu_arch_flags.bitfield.cpu287
10196 && !cpu_arch_flags.bitfield.cpu387)
10197 return (const reg_entry *) NULL;
10198
5f47d35b
AM		 10199 if (is_space_char (*s))
10200 ++s;
10201 if (*s == '(')
10202 {
af6bdddf 10203 ++s;
5f47d35b
AM		 10204 if (is_space_char (*s))
10205 ++s;
10206 if (*s >= '0' && *s <= '7')
10207 {
db557034 10208 int fpr = *s - '0';
af6bdddf 10209 ++s;
5f47d35b
AM		 10210 if (is_space_char (*s))
10211 ++s;
10212 if (*s == ')')
10213 {
10214 *end_op = s + 1;
1e9cc1c2 10215 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 10216 know (r);
10217 return r + fpr;
5f47d35b 10218 }
5f47d35b 10219 }
47926f60 10220 /* We have "%st(" then garbage. */
5f47d35b
AM		 10221 return (const reg_entry *) NULL;
10222 }
10223 }
10224
a60de03c
JB		 10225 if (r == NULL || allow_pseudo_reg)
10226 return r;
10227
0dfbf9d7 10228 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 10229 return (const reg_entry *) NULL;
10230
dc821c5f 10231 if ((r->reg_type.bitfield.dword
192dc9c6
JB		 10232 || r->reg_type.bitfield.sreg3
10233 || r->reg_type.bitfield.control
10234 || r->reg_type.bitfield.debug
10235 || r->reg_type.bitfield.test)
10236 && !cpu_arch_flags.bitfield.cpui386)
10237 return (const reg_entry *) NULL;
10238
6e041cf4 10239 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
192dc9c6
JB		 10240 return (const reg_entry *) NULL;
10241
6e041cf4
JB		 10242 if (!cpu_arch_flags.bitfield.cpuavx512f)
10243 {
10244 if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
10245 return (const reg_entry *) NULL;
40f12533 10246
6e041cf4
JB		 10247 if (!cpu_arch_flags.bitfield.cpuavx)
10248 {
10249 if (r->reg_type.bitfield.ymmword)
10250 return (const reg_entry *) NULL;
1848e567 10251
6e041cf4
JB		 10252 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
10253 return (const reg_entry *) NULL;
10254 }
10255 }
43234a1e 10256
1adf7f56
JB		 10257 if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
10258 return (const reg_entry *) NULL;
10259
db51cc60 10260 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 10261 if (!allow_index_reg
db51cc60
L		 10262 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10263 return (const reg_entry *) NULL;
10264
1d3f8286
JB		 10265 /* Upper 16 vector registers are only available with VREX in 64bit
10266 mode, and require EVEX encoding. */
10267 if (r->reg_flags & RegVRex)
43234a1e
L		 10268 {
10269 if (!cpu_arch_flags.bitfield.cpuvrex
10270 || flag_code != CODE_64BIT)
10271 return (const reg_entry *) NULL;
1d3f8286
JB		 10272
10273 i.vec_encoding = vex_encoding_evex;
43234a1e
L		 10274 }
10275
a60de03c 10276 if (((r->reg_flags & (RegRex64 | RegRex))
dc821c5f 10277 || r->reg_type.bitfield.qword)
40fb9820 10278 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 10279 || !operand_type_equal (&r->reg_type, &control))
1ae00879 10280 && flag_code != CODE_64BIT)
20f0a1fc 10281 return (const reg_entry *) NULL;
1ae00879 10282
b7240065
JB		 10283 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10284 return (const reg_entry *) NULL;
10285
252b5132
RH		 10286 return r;
10287}
4d1bb795
JB		 10288
10289/* REG_STRING starts *before* REGISTER_PREFIX. */
10290
10291static const reg_entry *
10292parse_register (char *reg_string, char **end_op)
10293{
10294 const reg_entry *r;
10295
10296 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10297 r = parse_real_register (reg_string, end_op);
10298 else
10299 r = NULL;
10300 if (!r)
10301 {
10302 char *save = input_line_pointer;
10303 char c;
10304 symbolS *symbolP;
10305
10306 input_line_pointer = reg_string;
d02603dc 10307 c = get_symbol_name (&reg_string);
4d1bb795
JB		 10308 symbolP = symbol_find (reg_string);
10309 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10310 {
10311 const expressionS *e = symbol_get_value_expression (symbolP);
10312
0398aac5 10313 know (e->X_op == O_register);
4eed87de 10314 know (e->X_add_number >= 0
c3fe08fa 10315 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 10316 r = i386_regtab + e->X_add_number;
d3bb6b49 10317 if ((r->reg_flags & RegVRex))
86fa6981 10318 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 10319 *end_op = input_line_pointer;
10320 }
10321 *input_line_pointer = c;
10322 input_line_pointer = save;
10323 }
10324 return r;
10325}
10326
10327int
10328i386_parse_name (char *name, expressionS *e, char *nextcharP)
10329{
10330 const reg_entry *r;
10331 char *end = input_line_pointer;
10332
10333 *end = *nextcharP;
10334 r = parse_register (name, &input_line_pointer);
10335 if (r && end <= input_line_pointer)
10336 {
10337 *nextcharP = *input_line_pointer;
10338 *input_line_pointer = 0;
10339 e->X_op = O_register;
10340 e->X_add_number = r - i386_regtab;
10341 return 1;
10342 }
10343 input_line_pointer = end;
10344 *end = 0;
ee86248c 10345 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 10346}
10347
10348void
10349md_operand (expressionS *e)
10350{
ee86248c
JB		 10351 char *end;
10352 const reg_entry *r;
4d1bb795 10353
ee86248c
JB		 10354 switch (*input_line_pointer)
10355 {
10356 case REGISTER_PREFIX:
10357 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 10358 if (r)
10359 {
10360 e->X_op = O_register;
10361 e->X_add_number = r - i386_regtab;
10362 input_line_pointer = end;
10363 }
ee86248c
JB		 10364 break;
10365
10366 case '[':
9c2799c2 10367 gas_assert (intel_syntax);
ee86248c
JB		 10368 end = input_line_pointer++;
10369 expression (e);
10370 if (*input_line_pointer == ']')
10371 {
10372 ++input_line_pointer;
10373 e->X_op_symbol = make_expr_symbol (e);
10374 e->X_add_symbol = NULL;
10375 e->X_add_number = 0;
10376 e->X_op = O_index;
10377 }
10378 else
10379 {
10380 e->X_op = O_absent;
10381 input_line_pointer = end;
10382 }
10383 break;
4d1bb795
JB		 10384 }
10385}
10386
252b5132 10387\f
4cc782b5 10388#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
b6f8c7c4 10389const char *md_shortopts = "kVQ:sqnO::";
252b5132 10390#else
b6f8c7c4 10391const char *md_shortopts = "qnO::";
252b5132 10392#endif
6e0b89ee 10393
3e73aa7c 10394#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 10395#define OPTION_64 (OPTION_MD_BASE + 1)
10396#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 10397#define OPTION_MARCH (OPTION_MD_BASE + 3)
10398#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 10399#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10400#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10401#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10402#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
bd5dea88 10403#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
c0f3af97 10404#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 10405#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 10406#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10407#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10408#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 10409#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 10410#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10411#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 10412#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 10413#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 10414#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 10415#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 10416#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10417#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 10418#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
b3b91714 10419
99ad8390
NC		 10420struct option md_longopts[] =
10421{
3e73aa7c 10422 {"32", no_argument, NULL, OPTION_32},
321098a5 10423#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10424 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 10425 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 10426#endif
10427#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10428 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 10429 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 10430#endif
b3b91714 10431 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 10432 {"march", required_argument, NULL, OPTION_MARCH},
10433 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 10434 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10435 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10436 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10437 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
c0f3af97 10438 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 10439 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 10440 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 10441 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 10442 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 10443 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10444 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 10445# if defined (TE_PE) || defined (TE_PEP)
10446 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10447#endif
d1982f93 10448 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 10449 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 10450 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 10451 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 10452 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10453 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 10454 {NULL, no_argument, NULL, 0}
10455};
10456size_t md_longopts_size = sizeof (md_longopts);
10457
10458int
17b9d67d 10459md_parse_option (int c, const char *arg)
252b5132 10460{
91d6fa6a 10461 unsigned int j;
293f5f65 10462 char *arch, *next, *saved;
9103f4f4 10463
252b5132
RH		 10464 switch (c)
10465 {
12b55ccc
L		 10466 case 'n':
10467 optimize_align_code = 0;
10468 break;
10469
a38cf1db
AM		 10470 case 'q':
10471 quiet_warnings = 1;
252b5132
RH		 10472 break;
10473
10474#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 10475 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10476 should be emitted or not. FIXME: Not implemented. */
10477 case 'Q':
252b5132
RH		 10478 break;
10479
10480 /* -V: SVR4 argument to print version ID. */
10481 case 'V':
10482 print_version_id ();
10483 break;
10484
a38cf1db
AM		 10485 /* -k: Ignore for FreeBSD compatibility. */
10486 case 'k':
252b5132 10487 break;
4cc782b5
ILT		 10488
10489 case 's':
10490 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 10491 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 10492 break;
8dcea932
L		 10493
10494 case OPTION_MSHARED:
10495 shared = 1;
10496 break;
99ad8390 10497#endif
321098a5 10498#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10499 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 10500 case OPTION_64:
10501 {
10502 const char **list, **l;
10503
3e73aa7c
JH		 10504 list = bfd_target_list ();
10505 for (l = list; *l != NULL; l++)
8620418b 10506 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 10507 || strcmp (*l, "coff-x86-64") == 0
10508 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 10509 || strcmp (*l, "pei-x86-64") == 0
10510 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 10511 {
10512 default_arch = "x86_64";
10513 break;
10514 }
3e73aa7c 10515 if (*l == NULL)
2b5d6a91 10516 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 10517 free (list);
10518 }
10519 break;
10520#endif
252b5132 10521
351f65ca 10522#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10523 case OPTION_X32:
351f65ca
L		 10524 if (IS_ELF)
10525 {
10526 const char **list, **l;
10527
10528 list = bfd_target_list ();
10529 for (l = list; *l != NULL; l++)
10530 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10531 {
10532 default_arch = "x86_64:32";
10533 break;
10534 }
10535 if (*l == NULL)
2b5d6a91 10536 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 10537 free (list);
10538 }
10539 else
10540 as_fatal (_("32bit x86_64 is only supported for ELF"));
10541 break;
10542#endif
10543
6e0b89ee
AM		 10544 case OPTION_32:
10545 default_arch = "i386";
10546 break;
10547
b3b91714
AM		 10548 case OPTION_DIVIDE:
10549#ifdef SVR4_COMMENT_CHARS
10550 {
10551 char *n, *t;
10552 const char *s;
10553
add39d23 10554 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 10555 t = n;
10556 for (s = i386_comment_chars; *s != '\0'; s++)
10557 if (*s != '/')
10558 *t++ = *s;
10559 *t = '\0';
10560 i386_comment_chars = n;
10561 }
10562#endif
10563 break;
10564
9103f4f4 10565 case OPTION_MARCH:
293f5f65
L		 10566 saved = xstrdup (arg);
10567 arch = saved;
10568 /* Allow -march=+nosse. */
10569 if (*arch == '+')
10570 arch++;
6305a203 10571 do
9103f4f4 10572 {
6305a203 10573 if (*arch == '.')
2b5d6a91 10574 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10575 next = strchr (arch, '+');
10576 if (next)
10577 *next++ = '\0';
91d6fa6a 10578 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10579 {
91d6fa6a 10580 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10581 {
6305a203 10582 /* Processor. */
1ded5609
JB		 10583 if (! cpu_arch[j].flags.bitfield.cpui386)
10584 continue;
10585
91d6fa6a 10586 cpu_arch_name = cpu_arch[j].name;
6305a203 10587 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10588 cpu_arch_flags = cpu_arch[j].flags;
10589 cpu_arch_isa = cpu_arch[j].type;
10590 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10591 if (!cpu_arch_tune_set)
10592 {
10593 cpu_arch_tune = cpu_arch_isa;
10594 cpu_arch_tune_flags = cpu_arch_isa_flags;
10595 }
10596 break;
10597 }
91d6fa6a
NC		 10598 else if (*cpu_arch [j].name == '.'
10599 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 10600 {
33eaf5de 10601 /* ISA extension. */
6305a203 10602 i386_cpu_flags flags;
309d3373 10603
293f5f65
L		 10604 flags = cpu_flags_or (cpu_arch_flags,
10605 cpu_arch[j].flags);
81486035 10606
5b64d091 10607 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10608 {
10609 if (cpu_sub_arch_name)
10610 {
10611 char *name = cpu_sub_arch_name;
10612 cpu_sub_arch_name = concat (name,
91d6fa6a 10613 cpu_arch[j].name,
1bf57e9f 10614 (const char *) NULL);
6305a203
L		 10615 free (name);
10616 }
10617 else
91d6fa6a 10618 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10619 cpu_arch_flags = flags;
a586129e 10620 cpu_arch_isa_flags = flags;
6305a203 10621 }
0089dace
L		 10622 else
10623 cpu_arch_isa_flags
10624 = cpu_flags_or (cpu_arch_isa_flags,
10625 cpu_arch[j].flags);
6305a203 10626 break;
ccc9c027 10627 }
9103f4f4 10628 }
6305a203 10629
293f5f65
L		 10630 if (j >= ARRAY_SIZE (cpu_arch))
10631 {
33eaf5de 10632 /* Disable an ISA extension. */
293f5f65
L		 10633 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10634 if (strcmp (arch, cpu_noarch [j].name) == 0)
10635 {
10636 i386_cpu_flags flags;
10637
10638 flags = cpu_flags_and_not (cpu_arch_flags,
10639 cpu_noarch[j].flags);
10640 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10641 {
10642 if (cpu_sub_arch_name)
10643 {
10644 char *name = cpu_sub_arch_name;
10645 cpu_sub_arch_name = concat (arch,
10646 (const char *) NULL);
10647 free (name);
10648 }
10649 else
10650 cpu_sub_arch_name = xstrdup (arch);
10651 cpu_arch_flags = flags;
10652 cpu_arch_isa_flags = flags;
10653 }
10654 break;
10655 }
10656
10657 if (j >= ARRAY_SIZE (cpu_noarch))
10658 j = ARRAY_SIZE (cpu_arch);
10659 }
10660
91d6fa6a 10661 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10662 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10663
10664 arch = next;
9103f4f4 10665 }
293f5f65
L		 10666 while (next != NULL);
10667 free (saved);
9103f4f4
L		 10668 break;
10669
10670 case OPTION_MTUNE:
10671 if (*arg == '.')
2b5d6a91 10672 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10673 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10674 {
91d6fa6a 10675 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10676 {
ccc9c027 10677 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10678 cpu_arch_tune = cpu_arch [j].type;
10679 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10680 break;
10681 }
10682 }
91d6fa6a 10683 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10684 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10685 break;
10686
1efbbeb4
L		 10687 case OPTION_MMNEMONIC:
10688 if (strcasecmp (arg, "att") == 0)
10689 intel_mnemonic = 0;
10690 else if (strcasecmp (arg, "intel") == 0)
10691 intel_mnemonic = 1;
10692 else
2b5d6a91 10693 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10694 break;
10695
10696 case OPTION_MSYNTAX:
10697 if (strcasecmp (arg, "att") == 0)
10698 intel_syntax = 0;
10699 else if (strcasecmp (arg, "intel") == 0)
10700 intel_syntax = 1;
10701 else
2b5d6a91 10702 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10703 break;
10704
10705 case OPTION_MINDEX_REG:
10706 allow_index_reg = 1;
10707 break;
10708
10709 case OPTION_MNAKED_REG:
10710 allow_naked_reg = 1;
10711 break;
10712
c0f3af97
L		 10713 case OPTION_MSSE2AVX:
10714 sse2avx = 1;
10715 break;
10716
daf50ae7
L		 10717 case OPTION_MSSE_CHECK:
10718 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10719 sse_check = check_error;
daf50ae7 10720 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10721 sse_check = check_warning;
daf50ae7 10722 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10723 sse_check = check_none;
daf50ae7 10724 else
2b5d6a91 10725 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10726 break;
10727
7bab8ab5
JB		 10728 case OPTION_MOPERAND_CHECK:
10729 if (strcasecmp (arg, "error") == 0)
10730 operand_check = check_error;
10731 else if (strcasecmp (arg, "warning") == 0)
10732 operand_check = check_warning;
10733 else if (strcasecmp (arg, "none") == 0)
10734 operand_check = check_none;
10735 else
10736 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10737 break;
10738
539f890d
L		 10739 case OPTION_MAVXSCALAR:
10740 if (strcasecmp (arg, "128") == 0)
10741 avxscalar = vex128;
10742 else if (strcasecmp (arg, "256") == 0)
10743 avxscalar = vex256;
10744 else
2b5d6a91 10745 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10746 break;
10747
7e8b059b
L		 10748 case OPTION_MADD_BND_PREFIX:
10749 add_bnd_prefix = 1;
10750 break;
10751
43234a1e
L		 10752 case OPTION_MEVEXLIG:
10753 if (strcmp (arg, "128") == 0)
10754 evexlig = evexl128;
10755 else if (strcmp (arg, "256") == 0)
10756 evexlig = evexl256;
10757 else if (strcmp (arg, "512") == 0)
10758 evexlig = evexl512;
10759 else
10760 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10761 break;
10762
d3d3c6db
IT		 10763 case OPTION_MEVEXRCIG:
10764 if (strcmp (arg, "rne") == 0)
10765 evexrcig = rne;
10766 else if (strcmp (arg, "rd") == 0)
10767 evexrcig = rd;
10768 else if (strcmp (arg, "ru") == 0)
10769 evexrcig = ru;
10770 else if (strcmp (arg, "rz") == 0)
10771 evexrcig = rz;
10772 else
10773 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10774 break;
10775
43234a1e
L		 10776 case OPTION_MEVEXWIG:
10777 if (strcmp (arg, "0") == 0)
10778 evexwig = evexw0;
10779 else if (strcmp (arg, "1") == 0)
10780 evexwig = evexw1;
10781 else
10782 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10783 break;
10784
167ad85b
TG		 10785# if defined (TE_PE) || defined (TE_PEP)
10786 case OPTION_MBIG_OBJ:
10787 use_big_obj = 1;
10788 break;
10789#endif
10790
d1982f93 10791 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10792 if (strcasecmp (arg, "yes") == 0)
10793 omit_lock_prefix = 1;
10794 else if (strcasecmp (arg, "no") == 0)
10795 omit_lock_prefix = 0;
10796 else
10797 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10798 break;
10799
e4e00185
AS		 10800 case OPTION_MFENCE_AS_LOCK_ADD:
10801 if (strcasecmp (arg, "yes") == 0)
10802 avoid_fence = 1;
10803 else if (strcasecmp (arg, "no") == 0)
10804 avoid_fence = 0;
10805 else
10806 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10807 break;
10808
0cb4071e
L		 10809 case OPTION_MRELAX_RELOCATIONS:
10810 if (strcasecmp (arg, "yes") == 0)
10811 generate_relax_relocations = 1;
10812 else if (strcasecmp (arg, "no") == 0)
10813 generate_relax_relocations = 0;
10814 else
10815 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10816 break;
10817
5db04b09 10818 case OPTION_MAMD64:
e89c5eaa 10819 intel64 = 0;
5db04b09
L		 10820 break;
10821
10822 case OPTION_MINTEL64:
e89c5eaa 10823 intel64 = 1;
5db04b09
L		 10824 break;
10825
b6f8c7c4
L		 10826 case 'O':
10827 if (arg == NULL)
10828 {
10829 optimize = 1;
10830 /* Turn off -Os. */
10831 optimize_for_space = 0;
10832 }
10833 else if (*arg == 's')
10834 {
10835 optimize_for_space = 1;
10836 /* Turn on all encoding optimizations. */
10837 optimize = -1;
10838 }
10839 else
10840 {
10841 optimize = atoi (arg);
10842 /* Turn off -Os. */
10843 optimize_for_space = 0;
10844 }
10845 break;
10846
252b5132
RH		 10847 default:
10848 return 0;
10849 }
10850 return 1;
10851}
10852
8a2c8fef
L		 10853#define MESSAGE_TEMPLATE \
10854" "
10855
293f5f65
L		 10856static char *
10857output_message (FILE *stream, char *p, char *message, char *start,
10858 int *left_p, const char *name, int len)
10859{
10860 int size = sizeof (MESSAGE_TEMPLATE);
10861 int left = *left_p;
10862
10863 /* Reserve 2 spaces for ", " or ",\0" */
10864 left -= len + 2;
10865
10866 /* Check if there is any room. */
10867 if (left >= 0)
10868 {
10869 if (p != start)
10870 {
10871 *p++ = ',';
10872 *p++ = ' ';
10873 }
10874 p = mempcpy (p, name, len);
10875 }
10876 else
10877 {
10878 /* Output the current message now and start a new one. */
10879 *p++ = ',';
10880 *p = '\0';
10881 fprintf (stream, "%s\n", message);
10882 p = start;
10883 left = size - (start - message) - len - 2;
10884
10885 gas_assert (left >= 0);
10886
10887 p = mempcpy (p, name, len);
10888 }
10889
10890 *left_p = left;
10891 return p;
10892}
10893
8a2c8fef 10894static void
1ded5609 10895show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10896{
10897 static char message[] = MESSAGE_TEMPLATE;
10898 char *start = message + 27;
10899 char *p;
10900 int size = sizeof (MESSAGE_TEMPLATE);
10901 int left;
10902 const char *name;
10903 int len;
10904 unsigned int j;
10905
10906 p = start;
10907 left = size - (start - message);
10908 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10909 {
10910 /* Should it be skipped? */
10911 if (cpu_arch [j].skip)
10912 continue;
10913
10914 name = cpu_arch [j].name;
10915 len = cpu_arch [j].len;
10916 if (*name == '.')
10917 {
10918 /* It is an extension. Skip if we aren't asked to show it. */
10919 if (ext)
10920 {
10921 name++;
10922 len--;
10923 }
10924 else
10925 continue;
10926 }
10927 else if (ext)
10928 {
10929 /* It is an processor. Skip if we show only extension. */
10930 continue;
10931 }
1ded5609
JB		 10932 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10933 {
10934 /* It is an impossible processor - skip. */
10935 continue;
10936 }
8a2c8fef 10937
293f5f65 10938 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10939 }
10940
293f5f65
L		 10941 /* Display disabled extensions. */
10942 if (ext)
10943 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10944 {
10945 name = cpu_noarch [j].name;
10946 len = cpu_noarch [j].len;
10947 p = output_message (stream, p, message, start, &left, name,
10948 len);
10949 }
10950
8a2c8fef
L		 10951 *p = '\0';
10952 fprintf (stream, "%s\n", message);
10953}
10954
252b5132 10955void
8a2c8fef 10956md_show_usage (FILE *stream)
252b5132 10957{
4cc782b5
ILT		 10958#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10959 fprintf (stream, _("\
a38cf1db
AM		 10960 -Q ignored\n\
10961 -V print assembler version number\n\
b3b91714
AM		 10962 -k ignored\n"));
10963#endif
10964 fprintf (stream, _("\
12b55ccc 10965 -n Do not optimize code alignment\n\
b3b91714
AM		 10966 -q quieten some warnings\n"));
10967#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10968 fprintf (stream, _("\
a38cf1db 10969 -s ignored\n"));
b3b91714 10970#endif
321098a5
L		 10971#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10972 || defined (TE_PE) || defined (TE_PEP))
751d281c 10973 fprintf (stream, _("\
570561f7 10974 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10975#endif
b3b91714
AM		 10976#ifdef SVR4_COMMENT_CHARS
10977 fprintf (stream, _("\
10978 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10979#else
10980 fprintf (stream, _("\
b3b91714 10981 --divide ignored\n"));
4cc782b5 10982#endif
9103f4f4 10983 fprintf (stream, _("\
6305a203 10984 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10985 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10986 show_arch (stream, 0, 1);
8a2c8fef
L		 10987 fprintf (stream, _("\
10988 EXTENSION is combination of:\n"));
1ded5609 10989 show_arch (stream, 1, 0);
6305a203 10990 fprintf (stream, _("\
8a2c8fef 10991 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10992 show_arch (stream, 0, 0);
ba104c83 10993 fprintf (stream, _("\
c0f3af97
L		 10994 -msse2avx encode SSE instructions with VEX prefix\n"));
10995 fprintf (stream, _("\
daf50ae7
L		 10996 -msse-check=[none|error|warning]\n\
10997 check SSE instructions\n"));
10998 fprintf (stream, _("\
7bab8ab5
JB		 10999 -moperand-check=[none|error|warning]\n\
11000 check operand combinations for validity\n"));
11001 fprintf (stream, _("\
539f890d
L		 11002 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
11003 length\n"));
11004 fprintf (stream, _("\
43234a1e
L		 11005 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
11006 length\n"));
11007 fprintf (stream, _("\
11008 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
11009 for EVEX.W bit ignored instructions\n"));
11010 fprintf (stream, _("\
d3d3c6db
IT		 11011 -mevexrcig=[rne|rd|ru|rz]\n\
11012 encode EVEX instructions with specific EVEX.RC value\n\
11013 for SAE-only ignored instructions\n"));
11014 fprintf (stream, _("\
ba104c83
L		 11015 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
11016 fprintf (stream, _("\
11017 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
11018 fprintf (stream, _("\
11019 -mindex-reg support pseudo index registers\n"));
11020 fprintf (stream, _("\
11021 -mnaked-reg don't require `%%' prefix for registers\n"));
11022 fprintf (stream, _("\
7e8b059b 11023 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 11024 fprintf (stream, _("\
11025 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 11026# if defined (TE_PE) || defined (TE_PEP)
11027 fprintf (stream, _("\
11028 -mbig-obj generate big object files\n"));
11029#endif
d022bddd
IT		 11030 fprintf (stream, _("\
11031 -momit-lock-prefix=[no|yes]\n\
11032 strip all lock prefixes\n"));
5db04b09 11033 fprintf (stream, _("\
e4e00185
AS		 11034 -mfence-as-lock-add=[no|yes]\n\
11035 encode lfence, mfence and sfence as\n\
11036 lock addl $0x0, (%%{re}sp)\n"));
11037 fprintf (stream, _("\
0cb4071e
L		 11038 -mrelax-relocations=[no|yes]\n\
11039 generate relax relocations\n"));
11040 fprintf (stream, _("\
5db04b09
L		 11041 -mamd64 accept only AMD64 ISA\n"));
11042 fprintf (stream, _("\
11043 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 11044}
11045
3e73aa7c 11046#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 11047 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 11048 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 11049
11050/* Pick the target format to use. */
11051
47926f60 11052const char *
e3bb37b5 11053i386_target_format (void)
252b5132 11054{
351f65ca
L		 11055 if (!strncmp (default_arch, "x86_64", 6))
11056 {
11057 update_code_flag (CODE_64BIT, 1);
11058 if (default_arch[6] == '\0')
7f56bc95 11059 x86_elf_abi = X86_64_ABI;
351f65ca 11060 else
7f56bc95 11061 x86_elf_abi = X86_64_X32_ABI;
351f65ca 11062 }
3e73aa7c 11063 else if (!strcmp (default_arch, "i386"))
78f12dd3 11064 update_code_flag (CODE_32BIT, 1);
5197d474
L		 11065 else if (!strcmp (default_arch, "iamcu"))
11066 {
11067 update_code_flag (CODE_32BIT, 1);
11068 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11069 {
11070 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11071 cpu_arch_name = "iamcu";
11072 cpu_sub_arch_name = NULL;
11073 cpu_arch_flags = iamcu_flags;
11074 cpu_arch_isa = PROCESSOR_IAMCU;
11075 cpu_arch_isa_flags = iamcu_flags;
11076 if (!cpu_arch_tune_set)
11077 {
11078 cpu_arch_tune = cpu_arch_isa;
11079 cpu_arch_tune_flags = cpu_arch_isa_flags;
11080 }
11081 }
8d471ec1 11082 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 11083 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11084 cpu_arch_name);
11085 }
3e73aa7c 11086 else
2b5d6a91 11087 as_fatal (_("unknown architecture"));
89507696
JB		 11088
11089 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11090 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11091 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11092 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11093
252b5132
RH		 11094 switch (OUTPUT_FLAVOR)
11095 {
9384f2ff 11096#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 11097 case bfd_target_aout_flavour:
47926f60 11098 return AOUT_TARGET_FORMAT;
4c63da97 11099#endif
9384f2ff
AM		 11100#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11101# if defined (TE_PE) || defined (TE_PEP)
11102 case bfd_target_coff_flavour:
167ad85b
TG		 11103 if (flag_code == CODE_64BIT)
11104 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11105 else
11106 return "pe-i386";
9384f2ff 11107# elif defined (TE_GO32)
0561d57c
JK		 11108 case bfd_target_coff_flavour:
11109 return "coff-go32";
9384f2ff 11110# else
252b5132
RH		 11111 case bfd_target_coff_flavour:
11112 return "coff-i386";
9384f2ff 11113# endif
4c63da97 11114#endif
3e73aa7c 11115#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 11116 case bfd_target_elf_flavour:
3e73aa7c 11117 {
351f65ca
L		 11118 const char *format;
11119
11120 switch (x86_elf_abi)
4fa24527 11121 {
351f65ca
L		 11122 default:
11123 format = ELF_TARGET_FORMAT;
11124 break;
7f56bc95 11125 case X86_64_ABI:
351f65ca 11126 use_rela_relocations = 1;
4fa24527 11127 object_64bit = 1;
351f65ca
L		 11128 format = ELF_TARGET_FORMAT64;
11129 break;
7f56bc95 11130 case X86_64_X32_ABI:
4fa24527 11131 use_rela_relocations = 1;
351f65ca 11132 object_64bit = 1;
862be3fb 11133 disallow_64bit_reloc = 1;
351f65ca
L		 11134 format = ELF_TARGET_FORMAT32;
11135 break;
4fa24527 11136 }
3632d14b 11137 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 11138 {
7f56bc95 11139 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 11140 as_fatal (_("Intel L1OM is 64bit only"));
11141 return ELF_TARGET_L1OM_FORMAT;
11142 }
b49f93f6 11143 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 11144 {
11145 if (x86_elf_abi != X86_64_ABI)
11146 as_fatal (_("Intel K1OM is 64bit only"));
11147 return ELF_TARGET_K1OM_FORMAT;
11148 }
81486035
L		 11149 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11150 {
11151 if (x86_elf_abi != I386_ABI)
11152 as_fatal (_("Intel MCU is 32bit only"));
11153 return ELF_TARGET_IAMCU_FORMAT;
11154 }
8a9036a4 11155 else
351f65ca 11156 return format;
3e73aa7c 11157 }
e57f8c65
TG		 11158#endif
11159#if defined (OBJ_MACH_O)
11160 case bfd_target_mach_o_flavour:
d382c579
TG		 11161 if (flag_code == CODE_64BIT)
11162 {
11163 use_rela_relocations = 1;
11164 object_64bit = 1;
11165 return "mach-o-x86-64";
11166 }
11167 else
11168 return "mach-o-i386";
4c63da97 11169#endif
252b5132
RH		 11170 default:
11171 abort ();
11172 return NULL;
11173 }
11174}
11175
47926f60 11176#endif /* OBJ_MAYBE_ more than one */
252b5132 11177\f
252b5132 11178symbolS *
7016a5d5 11179md_undefined_symbol (char *name)
252b5132 11180{
18dc2407
ILT		 11181 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11182 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11183 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11184 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 11185 {
11186 if (!GOT_symbol)
11187 {
11188 if (symbol_find (name))
11189 as_bad (_("GOT already in symbol table"));
11190 GOT_symbol = symbol_new (name, undefined_section,
11191 (valueT) 0, &zero_address_frag);
11192 };
11193 return GOT_symbol;
11194 }
252b5132
RH		 11195 return 0;
11196}
11197
11198/* Round up a section size to the appropriate boundary. */
47926f60 11199
252b5132 11200valueT
7016a5d5 11201md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 11202{
4c63da97
AM		 11203#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11204 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11205 {
11206 /* For a.out, force the section size to be aligned. If we don't do
11207 this, BFD will align it for us, but it will not write out the
11208 final bytes of the section. This may be a bug in BFD, but it is
11209 easier to fix it here since that is how the other a.out targets
11210 work. */
11211 int align;
11212
11213 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 11214 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 11215 }
252b5132
RH		 11216#endif
11217
11218 return size;
11219}
11220
11221/* On the i386, PC-relative offsets are relative to the start of the
11222 next instruction. That is, the address of the offset, plus its
11223 size, since the offset is always the last part of the insn. */
11224
11225long
e3bb37b5 11226md_pcrel_from (fixS *fixP)
252b5132
RH		 11227{
11228 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11229}
11230
11231#ifndef I386COFF
11232
11233static void
e3bb37b5 11234s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 11235{
29b0f896 11236 int temp;
252b5132 11237
8a75718c
JB		 11238#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11239 if (IS_ELF)
11240 obj_elf_section_change_hook ();
11241#endif
252b5132
RH		 11242 temp = get_absolute_expression ();
11243 subseg_set (bss_section, (subsegT) temp);
11244 demand_empty_rest_of_line ();
11245}
11246
11247#endif
11248
252b5132 11249void
e3bb37b5 11250i386_validate_fix (fixS *fixp)
252b5132 11251{
02a86693 11252 if (fixp->fx_subsy)
252b5132 11253 {
02a86693 11254 if (fixp->fx_subsy == GOT_symbol)
23df1078 11255 {
02a86693
L		 11256 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11257 {
11258 if (!object_64bit)
11259 abort ();
11260#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11261 if (fixp->fx_tcbit2)
56ceb5b5
L		 11262 fixp->fx_r_type = (fixp->fx_tcbit
11263 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11264 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 11265 else
11266#endif
11267 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11268 }
d6ab8113 11269 else
02a86693
L		 11270 {
11271 if (!object_64bit)
11272 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11273 else
11274 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11275 }
11276 fixp->fx_subsy = 0;
23df1078 11277 }
252b5132 11278 }
02a86693
L		 11279#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11280 else if (!object_64bit)
11281 {
11282 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11283 && fixp->fx_tcbit2)
11284 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11285 }
11286#endif
252b5132
RH		 11287}
11288
252b5132 11289arelent *
7016a5d5 11290tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 11291{
11292 arelent *rel;
11293 bfd_reloc_code_real_type code;
11294
11295 switch (fixp->fx_r_type)
11296 {
8ce3d284 11297#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 11298 case BFD_RELOC_SIZE32:
11299 case BFD_RELOC_SIZE64:
11300 if (S_IS_DEFINED (fixp->fx_addsy)
11301 && !S_IS_EXTERNAL (fixp->fx_addsy))
11302 {
11303 /* Resolve size relocation against local symbol to size of
11304 the symbol plus addend. */
11305 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11306 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11307 && !fits_in_unsigned_long (value))
11308 as_bad_where (fixp->fx_file, fixp->fx_line,
11309 _("symbol size computation overflow"));
11310 fixp->fx_addsy = NULL;
11311 fixp->fx_subsy = NULL;
11312 md_apply_fix (fixp, (valueT *) &value, NULL);
11313 return NULL;
11314 }
8ce3d284 11315#endif
1a0670f3 11316 /* Fall through. */
8fd4256d 11317
3e73aa7c
JH		 11318 case BFD_RELOC_X86_64_PLT32:
11319 case BFD_RELOC_X86_64_GOT32:
11320 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11321 case BFD_RELOC_X86_64_GOTPCRELX:
11322 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 11323 case BFD_RELOC_386_PLT32:
11324 case BFD_RELOC_386_GOT32:
02a86693 11325 case BFD_RELOC_386_GOT32X:
252b5132
RH		 11326 case BFD_RELOC_386_GOTOFF:
11327 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 11328 case BFD_RELOC_386_TLS_GD:
11329 case BFD_RELOC_386_TLS_LDM:
11330 case BFD_RELOC_386_TLS_LDO_32:
11331 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 11332 case BFD_RELOC_386_TLS_IE:
11333 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 11334 case BFD_RELOC_386_TLS_LE_32:
11335 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 11336 case BFD_RELOC_386_TLS_GOTDESC:
11337 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 11338 case BFD_RELOC_X86_64_TLSGD:
11339 case BFD_RELOC_X86_64_TLSLD:
11340 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 11341 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 11342 case BFD_RELOC_X86_64_GOTTPOFF:
11343 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 11344 case BFD_RELOC_X86_64_TPOFF64:
11345 case BFD_RELOC_X86_64_GOTOFF64:
11346 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 11347 case BFD_RELOC_X86_64_GOT64:
11348 case BFD_RELOC_X86_64_GOTPCREL64:
11349 case BFD_RELOC_X86_64_GOTPC64:
11350 case BFD_RELOC_X86_64_GOTPLT64:
11351 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 11352 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11353 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 11354 case BFD_RELOC_RVA:
11355 case BFD_RELOC_VTABLE_ENTRY:
11356 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 11357#ifdef TE_PE
11358 case BFD_RELOC_32_SECREL:
11359#endif
252b5132
RH		 11360 code = fixp->fx_r_type;
11361 break;
dbbaec26
L		 11362 case BFD_RELOC_X86_64_32S:
11363 if (!fixp->fx_pcrel)
11364 {
11365 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11366 code = fixp->fx_r_type;
11367 break;
11368 }
1a0670f3 11369 /* Fall through. */
252b5132 11370 default:
93382f6d 11371 if (fixp->fx_pcrel)
252b5132 11372 {
93382f6d
AM		 11373 switch (fixp->fx_size)
11374 {
11375 default:
b091f402
AM		 11376 as_bad_where (fixp->fx_file, fixp->fx_line,
11377 _("can not do %d byte pc-relative relocation"),
11378 fixp->fx_size);
93382f6d
AM		 11379 code = BFD_RELOC_32_PCREL;
11380 break;
11381 case 1: code = BFD_RELOC_8_PCREL; break;
11382 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 11383 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 11384#ifdef BFD64
11385 case 8: code = BFD_RELOC_64_PCREL; break;
11386#endif
93382f6d
AM		 11387 }
11388 }
11389 else
11390 {
11391 switch (fixp->fx_size)
11392 {
11393 default:
b091f402
AM		 11394 as_bad_where (fixp->fx_file, fixp->fx_line,
11395 _("can not do %d byte relocation"),
11396 fixp->fx_size);
93382f6d
AM		 11397 code = BFD_RELOC_32;
11398 break;
11399 case 1: code = BFD_RELOC_8; break;
11400 case 2: code = BFD_RELOC_16; break;
11401 case 4: code = BFD_RELOC_32; break;
937149dd 11402#ifdef BFD64
3e73aa7c 11403 case 8: code = BFD_RELOC_64; break;
937149dd 11404#endif
93382f6d 11405 }
252b5132
RH		 11406 }
11407 break;
11408 }
252b5132 11409
d182319b
JB		 11410 if ((code == BFD_RELOC_32
11411 || code == BFD_RELOC_32_PCREL
11412 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 11413 && GOT_symbol
11414 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 11415 {
4fa24527 11416 if (!object_64bit)
d6ab8113
JB		 11417 code = BFD_RELOC_386_GOTPC;
11418 else
11419 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 11420 }
7b81dfbb
AJ		 11421 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11422 && GOT_symbol
11423 && fixp->fx_addsy == GOT_symbol)
11424 {
11425 code = BFD_RELOC_X86_64_GOTPC64;
11426 }
252b5132 11427
add39d23
TS		 11428 rel = XNEW (arelent);
11429 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 11430 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 11431
11432 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 11433
3e73aa7c
JH		 11434 if (!use_rela_relocations)
11435 {
11436 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11437 vtable entry to be used in the relocation's section offset. */
11438 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11439 rel->address = fixp->fx_offset;
fbeb56a4
DK		 11440#if defined (OBJ_COFF) && defined (TE_PE)
11441 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11442 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11443 else
11444#endif
c6682705 11445 rel->addend = 0;
3e73aa7c
JH		 11446 }
11447 /* Use the rela in 64bit mode. */
252b5132 11448 else
3e73aa7c 11449 {
862be3fb
L		 11450 if (disallow_64bit_reloc)
11451 switch (code)
11452 {
862be3fb
L		 11453 case BFD_RELOC_X86_64_DTPOFF64:
11454 case BFD_RELOC_X86_64_TPOFF64:
11455 case BFD_RELOC_64_PCREL:
11456 case BFD_RELOC_X86_64_GOTOFF64:
11457 case BFD_RELOC_X86_64_GOT64:
11458 case BFD_RELOC_X86_64_GOTPCREL64:
11459 case BFD_RELOC_X86_64_GOTPC64:
11460 case BFD_RELOC_X86_64_GOTPLT64:
11461 case BFD_RELOC_X86_64_PLTOFF64:
11462 as_bad_where (fixp->fx_file, fixp->fx_line,
11463 _("cannot represent relocation type %s in x32 mode"),
11464 bfd_get_reloc_code_name (code));
11465 break;
11466 default:
11467 break;
11468 }
11469
062cd5e7
AS		 11470 if (!fixp->fx_pcrel)
11471 rel->addend = fixp->fx_offset;
11472 else
11473 switch (code)
11474 {
11475 case BFD_RELOC_X86_64_PLT32:
11476 case BFD_RELOC_X86_64_GOT32:
11477 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11478 case BFD_RELOC_X86_64_GOTPCRELX:
11479 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 11480 case BFD_RELOC_X86_64_TLSGD:
11481 case BFD_RELOC_X86_64_TLSLD:
11482 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 11483 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11484 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 11485 rel->addend = fixp->fx_offset - fixp->fx_size;
11486 break;
11487 default:
11488 rel->addend = (section->vma
11489 - fixp->fx_size
11490 + fixp->fx_addnumber
11491 + md_pcrel_from (fixp));
11492 break;
11493 }
3e73aa7c
JH		 11494 }
11495
252b5132
RH		 11496 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11497 if (rel->howto == NULL)
11498 {
11499 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 11500 _("cannot represent relocation type %s"),
252b5132
RH		 11501 bfd_get_reloc_code_name (code));
11502 /* Set howto to a garbage value so that we can keep going. */
11503 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 11504 gas_assert (rel->howto != NULL);
252b5132
RH		 11505 }
11506
11507 return rel;
11508}
11509
ee86248c 11510#include "tc-i386-intel.c"
54cfded0 11511
a60de03c
JB		 11512void
11513tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 11514{
a60de03c
JB		 11515 int saved_naked_reg;
11516 char saved_register_dot;
54cfded0 11517
a60de03c
JB		 11518 saved_naked_reg = allow_naked_reg;
11519 allow_naked_reg = 1;
11520 saved_register_dot = register_chars['.'];
11521 register_chars['.'] = '.';
11522 allow_pseudo_reg = 1;
11523 expression_and_evaluate (exp);
11524 allow_pseudo_reg = 0;
11525 register_chars['.'] = saved_register_dot;
11526 allow_naked_reg = saved_naked_reg;
11527
e96d56a1 11528 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 11529 {
a60de03c
JB		 11530 if ((addressT) exp->X_add_number < i386_regtab_size)
11531 {
11532 exp->X_op = O_constant;
11533 exp->X_add_number = i386_regtab[exp->X_add_number]
11534 .dw2_regnum[flag_code >> 1];
11535 }
11536 else
11537 exp->X_op = O_illegal;
54cfded0 11538 }
54cfded0
AM		 11539}
11540
11541void
11542tc_x86_frame_initial_instructions (void)
11543{
a60de03c
JB		 11544 static unsigned int sp_regno[2];
11545
11546 if (!sp_regno[flag_code >> 1])
11547 {
11548 char *saved_input = input_line_pointer;
11549 char sp[][4] = {"esp", "rsp"};
11550 expressionS exp;
a4447b93 11551
a60de03c
JB		 11552 input_line_pointer = sp[flag_code >> 1];
11553 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 11554 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 11555 sp_regno[flag_code >> 1] = exp.X_add_number;
11556 input_line_pointer = saved_input;
11557 }
a4447b93 11558
61ff971f
L		 11559 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11560 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 11561}
d2b2c203 11562
d7921315
L		 11563int
11564x86_dwarf2_addr_size (void)
11565{
11566#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11567 if (x86_elf_abi == X86_64_X32_ABI)
11568 return 4;
11569#endif
11570 return bfd_arch_bits_per_address (stdoutput) / 8;
11571}
11572
d2b2c203
DJ		 11573int
11574i386_elf_section_type (const char *str, size_t len)
11575{
11576 if (flag_code == CODE_64BIT
11577 && len == sizeof ("unwind") - 1
11578 && strncmp (str, "unwind", 6) == 0)
11579 return SHT_X86_64_UNWIND;
11580
11581 return -1;
11582}
bb41ade5 11583
ad5fec3b
EB		 11584#ifdef TE_SOLARIS
11585void
11586i386_solaris_fix_up_eh_frame (segT sec)
11587{
11588 if (flag_code == CODE_64BIT)
11589 elf_section_type (sec) = SHT_X86_64_UNWIND;
11590}
11591#endif
11592
bb41ade5
AM		 11593#ifdef TE_PE
11594void
11595tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11596{
91d6fa6a 11597 expressionS exp;
bb41ade5 11598
91d6fa6a
NC		 11599 exp.X_op = O_secrel;
11600 exp.X_add_symbol = symbol;
11601 exp.X_add_number = 0;
11602 emit_expr (&exp, size);
bb41ade5
AM		 11603}
11604#endif
3b22753a
L		 11605
11606#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11607/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11608
01e1a5bc 11609bfd_vma
6d4af3c2 11610x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11611{
11612 if (flag_code == CODE_64BIT)
11613 {
11614 if (letter == 'l')
11615 return SHF_X86_64_LARGE;
11616
8f3bae45 11617 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11618 }
3b22753a 11619 else
8f3bae45 11620 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11621 return -1;
11622}
11623
01e1a5bc 11624bfd_vma
3b22753a
L		 11625x86_64_section_word (char *str, size_t len)
11626{
8620418b 11627 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11628 return SHF_X86_64_LARGE;
11629
11630 return -1;
11631}
11632
11633static void
11634handle_large_common (int small ATTRIBUTE_UNUSED)
11635{
11636 if (flag_code != CODE_64BIT)
11637 {
11638 s_comm_internal (0, elf_common_parse);
11639 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11640 }
11641 else
11642 {
11643 static segT lbss_section;
11644 asection *saved_com_section_ptr = elf_com_section_ptr;
11645 asection *saved_bss_section = bss_section;
11646
11647 if (lbss_section == NULL)
11648 {
11649 flagword applicable;
11650 segT seg = now_seg;
11651 subsegT subseg = now_subseg;
11652
11653 /* The .lbss section is for local .largecomm symbols. */
11654 lbss_section = subseg_new (".lbss", 0);
11655 applicable = bfd_applicable_section_flags (stdoutput);
11656 bfd_set_section_flags (stdoutput, lbss_section,
11657 applicable & SEC_ALLOC);
11658 seg_info (lbss_section)->bss = 1;
11659
11660 subseg_set (seg, subseg);
11661 }
11662
11663 elf_com_section_ptr = &_bfd_elf_large_com_section;
11664 bss_section = lbss_section;
11665
11666 s_comm_internal (0, elf_common_parse);
11667
11668 elf_com_section_ptr = saved_com_section_ptr;
11669 bss_section = saved_bss_section;
11670 }
11671}
11672#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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